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043405e1 CO |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * derived from drivers/kvm/kvm_main.c | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
7 | * Copyright (C) 2008 Qumranet, Inc. |
8 | * Copyright IBM Corporation, 2008 | |
9611c187 | 9 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
043405e1 CO |
10 | * |
11 | * Authors: | |
12 | * Avi Kivity <avi@qumranet.com> | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
14 | * Amit Shah <amit.shah@qumranet.com> |
15 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
16 | * |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | * | |
20 | */ | |
21 | ||
edf88417 | 22 | #include <linux/kvm_host.h> |
313a3dc7 | 23 | #include "irq.h" |
1d737c8a | 24 | #include "mmu.h" |
7837699f | 25 | #include "i8254.h" |
37817f29 | 26 | #include "tss.h" |
5fdbf976 | 27 | #include "kvm_cache_regs.h" |
26eef70c | 28 | #include "x86.h" |
00b27a3e | 29 | #include "cpuid.h" |
313a3dc7 | 30 | |
18068523 | 31 | #include <linux/clocksource.h> |
4d5c5d0f | 32 | #include <linux/interrupt.h> |
313a3dc7 CO |
33 | #include <linux/kvm.h> |
34 | #include <linux/fs.h> | |
35 | #include <linux/vmalloc.h> | |
5fb76f9b | 36 | #include <linux/module.h> |
0de10343 | 37 | #include <linux/mman.h> |
2bacc55c | 38 | #include <linux/highmem.h> |
19de40a8 | 39 | #include <linux/iommu.h> |
62c476c7 | 40 | #include <linux/intel-iommu.h> |
c8076604 | 41 | #include <linux/cpufreq.h> |
18863bdd | 42 | #include <linux/user-return-notifier.h> |
a983fb23 | 43 | #include <linux/srcu.h> |
5a0e3ad6 | 44 | #include <linux/slab.h> |
ff9d07a0 | 45 | #include <linux/perf_event.h> |
7bee342a | 46 | #include <linux/uaccess.h> |
af585b92 | 47 | #include <linux/hash.h> |
a1b60c1c | 48 | #include <linux/pci.h> |
16e8d74d MT |
49 | #include <linux/timekeeper_internal.h> |
50 | #include <linux/pvclock_gtod.h> | |
aec51dc4 | 51 | #include <trace/events/kvm.h> |
2ed152af | 52 | |
229456fc MT |
53 | #define CREATE_TRACE_POINTS |
54 | #include "trace.h" | |
043405e1 | 55 | |
24f1e32c | 56 | #include <asm/debugreg.h> |
d825ed0a | 57 | #include <asm/msr.h> |
a5f61300 | 58 | #include <asm/desc.h> |
0bed3b56 | 59 | #include <asm/mtrr.h> |
890ca9ae | 60 | #include <asm/mce.h> |
7cf30855 | 61 | #include <asm/i387.h> |
1361b83a | 62 | #include <asm/fpu-internal.h> /* Ugh! */ |
98918833 | 63 | #include <asm/xcr.h> |
1d5f066e | 64 | #include <asm/pvclock.h> |
217fc9cf | 65 | #include <asm/div64.h> |
043405e1 | 66 | |
313a3dc7 | 67 | #define MAX_IO_MSRS 256 |
890ca9ae | 68 | #define KVM_MAX_MCE_BANKS 32 |
5854dbca | 69 | #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P) |
890ca9ae | 70 | |
0f65dd70 AK |
71 | #define emul_to_vcpu(ctxt) \ |
72 | container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) | |
73 | ||
50a37eb4 JR |
74 | /* EFER defaults: |
75 | * - enable syscall per default because its emulated by KVM | |
76 | * - enable LME and LMA per default on 64 bit KVM | |
77 | */ | |
78 | #ifdef CONFIG_X86_64 | |
1260edbe LJ |
79 | static |
80 | u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); | |
50a37eb4 | 81 | #else |
1260edbe | 82 | static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); |
50a37eb4 | 83 | #endif |
313a3dc7 | 84 | |
ba1389b7 AK |
85 | #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM |
86 | #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU | |
417bc304 | 87 | |
cb142eb7 | 88 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
7460fb4a | 89 | static void process_nmi(struct kvm_vcpu *vcpu); |
674eea0f | 90 | |
97896d04 | 91 | struct kvm_x86_ops *kvm_x86_ops; |
5fdbf976 | 92 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 93 | |
476bc001 RR |
94 | static bool ignore_msrs = 0; |
95 | module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); | |
ed85c068 | 96 | |
92a1f12d JR |
97 | bool kvm_has_tsc_control; |
98 | EXPORT_SYMBOL_GPL(kvm_has_tsc_control); | |
99 | u32 kvm_max_guest_tsc_khz; | |
100 | EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); | |
101 | ||
cc578287 ZA |
102 | /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ |
103 | static u32 tsc_tolerance_ppm = 250; | |
104 | module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); | |
105 | ||
18863bdd AK |
106 | #define KVM_NR_SHARED_MSRS 16 |
107 | ||
108 | struct kvm_shared_msrs_global { | |
109 | int nr; | |
2bf78fa7 | 110 | u32 msrs[KVM_NR_SHARED_MSRS]; |
18863bdd AK |
111 | }; |
112 | ||
113 | struct kvm_shared_msrs { | |
114 | struct user_return_notifier urn; | |
115 | bool registered; | |
2bf78fa7 SY |
116 | struct kvm_shared_msr_values { |
117 | u64 host; | |
118 | u64 curr; | |
119 | } values[KVM_NR_SHARED_MSRS]; | |
18863bdd AK |
120 | }; |
121 | ||
122 | static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; | |
013f6a5d | 123 | static struct kvm_shared_msrs __percpu *shared_msrs; |
18863bdd | 124 | |
417bc304 | 125 | struct kvm_stats_debugfs_item debugfs_entries[] = { |
ba1389b7 AK |
126 | { "pf_fixed", VCPU_STAT(pf_fixed) }, |
127 | { "pf_guest", VCPU_STAT(pf_guest) }, | |
128 | { "tlb_flush", VCPU_STAT(tlb_flush) }, | |
129 | { "invlpg", VCPU_STAT(invlpg) }, | |
130 | { "exits", VCPU_STAT(exits) }, | |
131 | { "io_exits", VCPU_STAT(io_exits) }, | |
132 | { "mmio_exits", VCPU_STAT(mmio_exits) }, | |
133 | { "signal_exits", VCPU_STAT(signal_exits) }, | |
134 | { "irq_window", VCPU_STAT(irq_window_exits) }, | |
f08864b4 | 135 | { "nmi_window", VCPU_STAT(nmi_window_exits) }, |
ba1389b7 AK |
136 | { "halt_exits", VCPU_STAT(halt_exits) }, |
137 | { "halt_wakeup", VCPU_STAT(halt_wakeup) }, | |
f11c3a8d | 138 | { "hypercalls", VCPU_STAT(hypercalls) }, |
ba1389b7 AK |
139 | { "request_irq", VCPU_STAT(request_irq_exits) }, |
140 | { "irq_exits", VCPU_STAT(irq_exits) }, | |
141 | { "host_state_reload", VCPU_STAT(host_state_reload) }, | |
142 | { "efer_reload", VCPU_STAT(efer_reload) }, | |
143 | { "fpu_reload", VCPU_STAT(fpu_reload) }, | |
144 | { "insn_emulation", VCPU_STAT(insn_emulation) }, | |
145 | { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, | |
fa89a817 | 146 | { "irq_injections", VCPU_STAT(irq_injections) }, |
c4abb7c9 | 147 | { "nmi_injections", VCPU_STAT(nmi_injections) }, |
4cee5764 AK |
148 | { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, |
149 | { "mmu_pte_write", VM_STAT(mmu_pte_write) }, | |
150 | { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, | |
151 | { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, | |
152 | { "mmu_flooded", VM_STAT(mmu_flooded) }, | |
153 | { "mmu_recycled", VM_STAT(mmu_recycled) }, | |
dfc5aa00 | 154 | { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, |
4731d4c7 | 155 | { "mmu_unsync", VM_STAT(mmu_unsync) }, |
0f74a24c | 156 | { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, |
05da4558 | 157 | { "largepages", VM_STAT(lpages) }, |
417bc304 HB |
158 | { NULL } |
159 | }; | |
160 | ||
2acf923e DC |
161 | u64 __read_mostly host_xcr0; |
162 | ||
b6785def | 163 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); |
d6aa1000 | 164 | |
af585b92 GN |
165 | static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) |
166 | { | |
167 | int i; | |
168 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) | |
169 | vcpu->arch.apf.gfns[i] = ~0; | |
170 | } | |
171 | ||
18863bdd AK |
172 | static void kvm_on_user_return(struct user_return_notifier *urn) |
173 | { | |
174 | unsigned slot; | |
18863bdd AK |
175 | struct kvm_shared_msrs *locals |
176 | = container_of(urn, struct kvm_shared_msrs, urn); | |
2bf78fa7 | 177 | struct kvm_shared_msr_values *values; |
18863bdd AK |
178 | |
179 | for (slot = 0; slot < shared_msrs_global.nr; ++slot) { | |
2bf78fa7 SY |
180 | values = &locals->values[slot]; |
181 | if (values->host != values->curr) { | |
182 | wrmsrl(shared_msrs_global.msrs[slot], values->host); | |
183 | values->curr = values->host; | |
18863bdd AK |
184 | } |
185 | } | |
186 | locals->registered = false; | |
187 | user_return_notifier_unregister(urn); | |
188 | } | |
189 | ||
2bf78fa7 | 190 | static void shared_msr_update(unsigned slot, u32 msr) |
18863bdd | 191 | { |
18863bdd | 192 | u64 value; |
013f6a5d MT |
193 | unsigned int cpu = smp_processor_id(); |
194 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
18863bdd | 195 | |
2bf78fa7 SY |
196 | /* only read, and nobody should modify it at this time, |
197 | * so don't need lock */ | |
198 | if (slot >= shared_msrs_global.nr) { | |
199 | printk(KERN_ERR "kvm: invalid MSR slot!"); | |
200 | return; | |
201 | } | |
202 | rdmsrl_safe(msr, &value); | |
203 | smsr->values[slot].host = value; | |
204 | smsr->values[slot].curr = value; | |
205 | } | |
206 | ||
207 | void kvm_define_shared_msr(unsigned slot, u32 msr) | |
208 | { | |
18863bdd AK |
209 | if (slot >= shared_msrs_global.nr) |
210 | shared_msrs_global.nr = slot + 1; | |
2bf78fa7 SY |
211 | shared_msrs_global.msrs[slot] = msr; |
212 | /* we need ensured the shared_msr_global have been updated */ | |
213 | smp_wmb(); | |
18863bdd AK |
214 | } |
215 | EXPORT_SYMBOL_GPL(kvm_define_shared_msr); | |
216 | ||
217 | static void kvm_shared_msr_cpu_online(void) | |
218 | { | |
219 | unsigned i; | |
18863bdd AK |
220 | |
221 | for (i = 0; i < shared_msrs_global.nr; ++i) | |
2bf78fa7 | 222 | shared_msr_update(i, shared_msrs_global.msrs[i]); |
18863bdd AK |
223 | } |
224 | ||
d5696725 | 225 | void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) |
18863bdd | 226 | { |
013f6a5d MT |
227 | unsigned int cpu = smp_processor_id(); |
228 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
18863bdd | 229 | |
2bf78fa7 | 230 | if (((value ^ smsr->values[slot].curr) & mask) == 0) |
18863bdd | 231 | return; |
2bf78fa7 SY |
232 | smsr->values[slot].curr = value; |
233 | wrmsrl(shared_msrs_global.msrs[slot], value); | |
18863bdd AK |
234 | if (!smsr->registered) { |
235 | smsr->urn.on_user_return = kvm_on_user_return; | |
236 | user_return_notifier_register(&smsr->urn); | |
237 | smsr->registered = true; | |
238 | } | |
239 | } | |
240 | EXPORT_SYMBOL_GPL(kvm_set_shared_msr); | |
241 | ||
3548bab5 AK |
242 | static void drop_user_return_notifiers(void *ignore) |
243 | { | |
013f6a5d MT |
244 | unsigned int cpu = smp_processor_id(); |
245 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
3548bab5 AK |
246 | |
247 | if (smsr->registered) | |
248 | kvm_on_user_return(&smsr->urn); | |
249 | } | |
250 | ||
6866b83e CO |
251 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
252 | { | |
8a5a87d9 | 253 | return vcpu->arch.apic_base; |
6866b83e CO |
254 | } |
255 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
256 | ||
257 | void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data) | |
258 | { | |
259 | /* TODO: reserve bits check */ | |
8a5a87d9 | 260 | kvm_lapic_set_base(vcpu, data); |
6866b83e CO |
261 | } |
262 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
263 | ||
e3ba45b8 GL |
264 | asmlinkage void kvm_spurious_fault(void) |
265 | { | |
266 | /* Fault while not rebooting. We want the trace. */ | |
267 | BUG(); | |
268 | } | |
269 | EXPORT_SYMBOL_GPL(kvm_spurious_fault); | |
270 | ||
3fd28fce ED |
271 | #define EXCPT_BENIGN 0 |
272 | #define EXCPT_CONTRIBUTORY 1 | |
273 | #define EXCPT_PF 2 | |
274 | ||
275 | static int exception_class(int vector) | |
276 | { | |
277 | switch (vector) { | |
278 | case PF_VECTOR: | |
279 | return EXCPT_PF; | |
280 | case DE_VECTOR: | |
281 | case TS_VECTOR: | |
282 | case NP_VECTOR: | |
283 | case SS_VECTOR: | |
284 | case GP_VECTOR: | |
285 | return EXCPT_CONTRIBUTORY; | |
286 | default: | |
287 | break; | |
288 | } | |
289 | return EXCPT_BENIGN; | |
290 | } | |
291 | ||
292 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, | |
ce7ddec4 JR |
293 | unsigned nr, bool has_error, u32 error_code, |
294 | bool reinject) | |
3fd28fce ED |
295 | { |
296 | u32 prev_nr; | |
297 | int class1, class2; | |
298 | ||
3842d135 AK |
299 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
300 | ||
3fd28fce ED |
301 | if (!vcpu->arch.exception.pending) { |
302 | queue: | |
303 | vcpu->arch.exception.pending = true; | |
304 | vcpu->arch.exception.has_error_code = has_error; | |
305 | vcpu->arch.exception.nr = nr; | |
306 | vcpu->arch.exception.error_code = error_code; | |
3f0fd292 | 307 | vcpu->arch.exception.reinject = reinject; |
3fd28fce ED |
308 | return; |
309 | } | |
310 | ||
311 | /* to check exception */ | |
312 | prev_nr = vcpu->arch.exception.nr; | |
313 | if (prev_nr == DF_VECTOR) { | |
314 | /* triple fault -> shutdown */ | |
a8eeb04a | 315 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
3fd28fce ED |
316 | return; |
317 | } | |
318 | class1 = exception_class(prev_nr); | |
319 | class2 = exception_class(nr); | |
320 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) | |
321 | || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
322 | /* generate double fault per SDM Table 5-5 */ | |
323 | vcpu->arch.exception.pending = true; | |
324 | vcpu->arch.exception.has_error_code = true; | |
325 | vcpu->arch.exception.nr = DF_VECTOR; | |
326 | vcpu->arch.exception.error_code = 0; | |
327 | } else | |
328 | /* replace previous exception with a new one in a hope | |
329 | that instruction re-execution will regenerate lost | |
330 | exception */ | |
331 | goto queue; | |
332 | } | |
333 | ||
298101da AK |
334 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
335 | { | |
ce7ddec4 | 336 | kvm_multiple_exception(vcpu, nr, false, 0, false); |
298101da AK |
337 | } |
338 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
339 | ||
ce7ddec4 JR |
340 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
341 | { | |
342 | kvm_multiple_exception(vcpu, nr, false, 0, true); | |
343 | } | |
344 | EXPORT_SYMBOL_GPL(kvm_requeue_exception); | |
345 | ||
db8fcefa | 346 | void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) |
c3c91fee | 347 | { |
db8fcefa AP |
348 | if (err) |
349 | kvm_inject_gp(vcpu, 0); | |
350 | else | |
351 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
352 | } | |
353 | EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); | |
8df25a32 | 354 | |
6389ee94 | 355 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
c3c91fee AK |
356 | { |
357 | ++vcpu->stat.pf_guest; | |
6389ee94 AK |
358 | vcpu->arch.cr2 = fault->address; |
359 | kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); | |
c3c91fee | 360 | } |
27d6c865 | 361 | EXPORT_SYMBOL_GPL(kvm_inject_page_fault); |
c3c91fee | 362 | |
6389ee94 | 363 | void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
d4f8cf66 | 364 | { |
6389ee94 AK |
365 | if (mmu_is_nested(vcpu) && !fault->nested_page_fault) |
366 | vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); | |
d4f8cf66 | 367 | else |
6389ee94 | 368 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
d4f8cf66 JR |
369 | } |
370 | ||
3419ffc8 SY |
371 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
372 | { | |
7460fb4a AK |
373 | atomic_inc(&vcpu->arch.nmi_queued); |
374 | kvm_make_request(KVM_REQ_NMI, vcpu); | |
3419ffc8 SY |
375 | } |
376 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
377 | ||
298101da AK |
378 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
379 | { | |
ce7ddec4 | 380 | kvm_multiple_exception(vcpu, nr, true, error_code, false); |
298101da AK |
381 | } |
382 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
383 | ||
ce7ddec4 JR |
384 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
385 | { | |
386 | kvm_multiple_exception(vcpu, nr, true, error_code, true); | |
387 | } | |
388 | EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); | |
389 | ||
0a79b009 AK |
390 | /* |
391 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
392 | * a #GP and return false. | |
393 | */ | |
394 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 395 | { |
0a79b009 AK |
396 | if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) |
397 | return true; | |
398 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
399 | return false; | |
298101da | 400 | } |
0a79b009 | 401 | EXPORT_SYMBOL_GPL(kvm_require_cpl); |
298101da | 402 | |
ec92fe44 JR |
403 | /* |
404 | * This function will be used to read from the physical memory of the currently | |
405 | * running guest. The difference to kvm_read_guest_page is that this function | |
406 | * can read from guest physical or from the guest's guest physical memory. | |
407 | */ | |
408 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
409 | gfn_t ngfn, void *data, int offset, int len, | |
410 | u32 access) | |
411 | { | |
412 | gfn_t real_gfn; | |
413 | gpa_t ngpa; | |
414 | ||
415 | ngpa = gfn_to_gpa(ngfn); | |
416 | real_gfn = mmu->translate_gpa(vcpu, ngpa, access); | |
417 | if (real_gfn == UNMAPPED_GVA) | |
418 | return -EFAULT; | |
419 | ||
420 | real_gfn = gpa_to_gfn(real_gfn); | |
421 | ||
422 | return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len); | |
423 | } | |
424 | EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); | |
425 | ||
3d06b8bf JR |
426 | int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, |
427 | void *data, int offset, int len, u32 access) | |
428 | { | |
429 | return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, | |
430 | data, offset, len, access); | |
431 | } | |
432 | ||
a03490ed CO |
433 | /* |
434 | * Load the pae pdptrs. Return true is they are all valid. | |
435 | */ | |
ff03a073 | 436 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) |
a03490ed CO |
437 | { |
438 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
439 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
440 | int i; | |
441 | int ret; | |
ff03a073 | 442 | u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; |
a03490ed | 443 | |
ff03a073 JR |
444 | ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, |
445 | offset * sizeof(u64), sizeof(pdpte), | |
446 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
a03490ed CO |
447 | if (ret < 0) { |
448 | ret = 0; | |
449 | goto out; | |
450 | } | |
451 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
43a3795a | 452 | if (is_present_gpte(pdpte[i]) && |
20c466b5 | 453 | (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) { |
a03490ed CO |
454 | ret = 0; |
455 | goto out; | |
456 | } | |
457 | } | |
458 | ret = 1; | |
459 | ||
ff03a073 | 460 | memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); |
6de4f3ad AK |
461 | __set_bit(VCPU_EXREG_PDPTR, |
462 | (unsigned long *)&vcpu->arch.regs_avail); | |
463 | __set_bit(VCPU_EXREG_PDPTR, | |
464 | (unsigned long *)&vcpu->arch.regs_dirty); | |
a03490ed | 465 | out: |
a03490ed CO |
466 | |
467 | return ret; | |
468 | } | |
cc4b6871 | 469 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 470 | |
d835dfec AK |
471 | static bool pdptrs_changed(struct kvm_vcpu *vcpu) |
472 | { | |
ff03a073 | 473 | u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; |
d835dfec | 474 | bool changed = true; |
3d06b8bf JR |
475 | int offset; |
476 | gfn_t gfn; | |
d835dfec AK |
477 | int r; |
478 | ||
479 | if (is_long_mode(vcpu) || !is_pae(vcpu)) | |
480 | return false; | |
481 | ||
6de4f3ad AK |
482 | if (!test_bit(VCPU_EXREG_PDPTR, |
483 | (unsigned long *)&vcpu->arch.regs_avail)) | |
484 | return true; | |
485 | ||
9f8fe504 AK |
486 | gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT; |
487 | offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1); | |
3d06b8bf JR |
488 | r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), |
489 | PFERR_USER_MASK | PFERR_WRITE_MASK); | |
d835dfec AK |
490 | if (r < 0) |
491 | goto out; | |
ff03a073 | 492 | changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; |
d835dfec | 493 | out: |
d835dfec AK |
494 | |
495 | return changed; | |
496 | } | |
497 | ||
49a9b07e | 498 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 499 | { |
aad82703 SY |
500 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
501 | unsigned long update_bits = X86_CR0_PG | X86_CR0_WP | | |
502 | X86_CR0_CD | X86_CR0_NW; | |
503 | ||
f9a48e6a AK |
504 | cr0 |= X86_CR0_ET; |
505 | ||
ab344828 | 506 | #ifdef CONFIG_X86_64 |
0f12244f GN |
507 | if (cr0 & 0xffffffff00000000UL) |
508 | return 1; | |
ab344828 GN |
509 | #endif |
510 | ||
511 | cr0 &= ~CR0_RESERVED_BITS; | |
a03490ed | 512 | |
0f12244f GN |
513 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) |
514 | return 1; | |
a03490ed | 515 | |
0f12244f GN |
516 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) |
517 | return 1; | |
a03490ed CO |
518 | |
519 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { | |
520 | #ifdef CONFIG_X86_64 | |
f6801dff | 521 | if ((vcpu->arch.efer & EFER_LME)) { |
a03490ed CO |
522 | int cs_db, cs_l; |
523 | ||
0f12244f GN |
524 | if (!is_pae(vcpu)) |
525 | return 1; | |
a03490ed | 526 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
0f12244f GN |
527 | if (cs_l) |
528 | return 1; | |
a03490ed CO |
529 | } else |
530 | #endif | |
ff03a073 | 531 | if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
9f8fe504 | 532 | kvm_read_cr3(vcpu))) |
0f12244f | 533 | return 1; |
a03490ed CO |
534 | } |
535 | ||
ad756a16 MJ |
536 | if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) |
537 | return 1; | |
538 | ||
a03490ed | 539 | kvm_x86_ops->set_cr0(vcpu, cr0); |
a03490ed | 540 | |
d170c419 | 541 | if ((cr0 ^ old_cr0) & X86_CR0_PG) { |
e5f3f027 | 542 | kvm_clear_async_pf_completion_queue(vcpu); |
d170c419 LJ |
543 | kvm_async_pf_hash_reset(vcpu); |
544 | } | |
e5f3f027 | 545 | |
aad82703 SY |
546 | if ((cr0 ^ old_cr0) & update_bits) |
547 | kvm_mmu_reset_context(vcpu); | |
0f12244f GN |
548 | return 0; |
549 | } | |
2d3ad1f4 | 550 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 551 | |
2d3ad1f4 | 552 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 553 | { |
49a9b07e | 554 | (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); |
a03490ed | 555 | } |
2d3ad1f4 | 556 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 557 | |
42bdf991 MT |
558 | static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) |
559 | { | |
560 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && | |
561 | !vcpu->guest_xcr0_loaded) { | |
562 | /* kvm_set_xcr() also depends on this */ | |
563 | xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); | |
564 | vcpu->guest_xcr0_loaded = 1; | |
565 | } | |
566 | } | |
567 | ||
568 | static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) | |
569 | { | |
570 | if (vcpu->guest_xcr0_loaded) { | |
571 | if (vcpu->arch.xcr0 != host_xcr0) | |
572 | xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); | |
573 | vcpu->guest_xcr0_loaded = 0; | |
574 | } | |
575 | } | |
576 | ||
2acf923e DC |
577 | int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) |
578 | { | |
579 | u64 xcr0; | |
580 | ||
581 | /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ | |
582 | if (index != XCR_XFEATURE_ENABLED_MASK) | |
583 | return 1; | |
584 | xcr0 = xcr; | |
585 | if (kvm_x86_ops->get_cpl(vcpu) != 0) | |
586 | return 1; | |
587 | if (!(xcr0 & XSTATE_FP)) | |
588 | return 1; | |
589 | if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE)) | |
590 | return 1; | |
591 | if (xcr0 & ~host_xcr0) | |
592 | return 1; | |
42bdf991 | 593 | kvm_put_guest_xcr0(vcpu); |
2acf923e | 594 | vcpu->arch.xcr0 = xcr0; |
2acf923e DC |
595 | return 0; |
596 | } | |
597 | ||
598 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) | |
599 | { | |
600 | if (__kvm_set_xcr(vcpu, index, xcr)) { | |
601 | kvm_inject_gp(vcpu, 0); | |
602 | return 1; | |
603 | } | |
604 | return 0; | |
605 | } | |
606 | EXPORT_SYMBOL_GPL(kvm_set_xcr); | |
607 | ||
a83b29c6 | 608 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 609 | { |
fc78f519 | 610 | unsigned long old_cr4 = kvm_read_cr4(vcpu); |
c68b734f YW |
611 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | |
612 | X86_CR4_PAE | X86_CR4_SMEP; | |
0f12244f GN |
613 | if (cr4 & CR4_RESERVED_BITS) |
614 | return 1; | |
a03490ed | 615 | |
2acf923e DC |
616 | if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE)) |
617 | return 1; | |
618 | ||
c68b734f YW |
619 | if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP)) |
620 | return 1; | |
621 | ||
74dc2b4f YW |
622 | if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS)) |
623 | return 1; | |
624 | ||
a03490ed | 625 | if (is_long_mode(vcpu)) { |
0f12244f GN |
626 | if (!(cr4 & X86_CR4_PAE)) |
627 | return 1; | |
a2edf57f AK |
628 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
629 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
9f8fe504 AK |
630 | && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
631 | kvm_read_cr3(vcpu))) | |
0f12244f GN |
632 | return 1; |
633 | ||
ad756a16 MJ |
634 | if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { |
635 | if (!guest_cpuid_has_pcid(vcpu)) | |
636 | return 1; | |
637 | ||
638 | /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ | |
639 | if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) | |
640 | return 1; | |
641 | } | |
642 | ||
5e1746d6 | 643 | if (kvm_x86_ops->set_cr4(vcpu, cr4)) |
0f12244f | 644 | return 1; |
a03490ed | 645 | |
ad756a16 MJ |
646 | if (((cr4 ^ old_cr4) & pdptr_bits) || |
647 | (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) | |
aad82703 | 648 | kvm_mmu_reset_context(vcpu); |
0f12244f | 649 | |
2acf923e | 650 | if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE) |
00b27a3e | 651 | kvm_update_cpuid(vcpu); |
2acf923e | 652 | |
0f12244f GN |
653 | return 0; |
654 | } | |
2d3ad1f4 | 655 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 656 | |
2390218b | 657 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 658 | { |
9f8fe504 | 659 | if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { |
0ba73cda | 660 | kvm_mmu_sync_roots(vcpu); |
d835dfec | 661 | kvm_mmu_flush_tlb(vcpu); |
0f12244f | 662 | return 0; |
d835dfec AK |
663 | } |
664 | ||
a03490ed | 665 | if (is_long_mode(vcpu)) { |
471842ec | 666 | if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) { |
ad756a16 MJ |
667 | if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS) |
668 | return 1; | |
669 | } else | |
670 | if (cr3 & CR3_L_MODE_RESERVED_BITS) | |
671 | return 1; | |
a03490ed CO |
672 | } else { |
673 | if (is_pae(vcpu)) { | |
0f12244f GN |
674 | if (cr3 & CR3_PAE_RESERVED_BITS) |
675 | return 1; | |
ff03a073 JR |
676 | if (is_paging(vcpu) && |
677 | !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) | |
0f12244f | 678 | return 1; |
a03490ed CO |
679 | } |
680 | /* | |
681 | * We don't check reserved bits in nonpae mode, because | |
682 | * this isn't enforced, and VMware depends on this. | |
683 | */ | |
684 | } | |
685 | ||
a03490ed CO |
686 | /* |
687 | * Does the new cr3 value map to physical memory? (Note, we | |
688 | * catch an invalid cr3 even in real-mode, because it would | |
689 | * cause trouble later on when we turn on paging anyway.) | |
690 | * | |
691 | * A real CPU would silently accept an invalid cr3 and would | |
692 | * attempt to use it - with largely undefined (and often hard | |
693 | * to debug) behavior on the guest side. | |
694 | */ | |
695 | if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT))) | |
0f12244f GN |
696 | return 1; |
697 | vcpu->arch.cr3 = cr3; | |
aff48baa | 698 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); |
0f12244f GN |
699 | vcpu->arch.mmu.new_cr3(vcpu); |
700 | return 0; | |
701 | } | |
2d3ad1f4 | 702 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 703 | |
eea1cff9 | 704 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed | 705 | { |
0f12244f GN |
706 | if (cr8 & CR8_RESERVED_BITS) |
707 | return 1; | |
a03490ed CO |
708 | if (irqchip_in_kernel(vcpu->kvm)) |
709 | kvm_lapic_set_tpr(vcpu, cr8); | |
710 | else | |
ad312c7c | 711 | vcpu->arch.cr8 = cr8; |
0f12244f GN |
712 | return 0; |
713 | } | |
2d3ad1f4 | 714 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 715 | |
2d3ad1f4 | 716 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed CO |
717 | { |
718 | if (irqchip_in_kernel(vcpu->kvm)) | |
719 | return kvm_lapic_get_cr8(vcpu); | |
720 | else | |
ad312c7c | 721 | return vcpu->arch.cr8; |
a03490ed | 722 | } |
2d3ad1f4 | 723 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 724 | |
c8639010 JK |
725 | static void kvm_update_dr7(struct kvm_vcpu *vcpu) |
726 | { | |
727 | unsigned long dr7; | |
728 | ||
729 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
730 | dr7 = vcpu->arch.guest_debug_dr7; | |
731 | else | |
732 | dr7 = vcpu->arch.dr7; | |
733 | kvm_x86_ops->set_dr7(vcpu, dr7); | |
734 | vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK); | |
735 | } | |
736 | ||
338dbc97 | 737 | static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) |
020df079 GN |
738 | { |
739 | switch (dr) { | |
740 | case 0 ... 3: | |
741 | vcpu->arch.db[dr] = val; | |
742 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
743 | vcpu->arch.eff_db[dr] = val; | |
744 | break; | |
745 | case 4: | |
338dbc97 GN |
746 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) |
747 | return 1; /* #UD */ | |
020df079 GN |
748 | /* fall through */ |
749 | case 6: | |
338dbc97 GN |
750 | if (val & 0xffffffff00000000ULL) |
751 | return -1; /* #GP */ | |
020df079 GN |
752 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1; |
753 | break; | |
754 | case 5: | |
338dbc97 GN |
755 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) |
756 | return 1; /* #UD */ | |
020df079 GN |
757 | /* fall through */ |
758 | default: /* 7 */ | |
338dbc97 GN |
759 | if (val & 0xffffffff00000000ULL) |
760 | return -1; /* #GP */ | |
020df079 | 761 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; |
c8639010 | 762 | kvm_update_dr7(vcpu); |
020df079 GN |
763 | break; |
764 | } | |
765 | ||
766 | return 0; | |
767 | } | |
338dbc97 GN |
768 | |
769 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) | |
770 | { | |
771 | int res; | |
772 | ||
773 | res = __kvm_set_dr(vcpu, dr, val); | |
774 | if (res > 0) | |
775 | kvm_queue_exception(vcpu, UD_VECTOR); | |
776 | else if (res < 0) | |
777 | kvm_inject_gp(vcpu, 0); | |
778 | ||
779 | return res; | |
780 | } | |
020df079 GN |
781 | EXPORT_SYMBOL_GPL(kvm_set_dr); |
782 | ||
338dbc97 | 783 | static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) |
020df079 GN |
784 | { |
785 | switch (dr) { | |
786 | case 0 ... 3: | |
787 | *val = vcpu->arch.db[dr]; | |
788 | break; | |
789 | case 4: | |
338dbc97 | 790 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) |
020df079 | 791 | return 1; |
020df079 GN |
792 | /* fall through */ |
793 | case 6: | |
794 | *val = vcpu->arch.dr6; | |
795 | break; | |
796 | case 5: | |
338dbc97 | 797 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) |
020df079 | 798 | return 1; |
020df079 GN |
799 | /* fall through */ |
800 | default: /* 7 */ | |
801 | *val = vcpu->arch.dr7; | |
802 | break; | |
803 | } | |
804 | ||
805 | return 0; | |
806 | } | |
338dbc97 GN |
807 | |
808 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) | |
809 | { | |
810 | if (_kvm_get_dr(vcpu, dr, val)) { | |
811 | kvm_queue_exception(vcpu, UD_VECTOR); | |
812 | return 1; | |
813 | } | |
814 | return 0; | |
815 | } | |
020df079 GN |
816 | EXPORT_SYMBOL_GPL(kvm_get_dr); |
817 | ||
022cd0e8 AK |
818 | bool kvm_rdpmc(struct kvm_vcpu *vcpu) |
819 | { | |
820 | u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
821 | u64 data; | |
822 | int err; | |
823 | ||
824 | err = kvm_pmu_read_pmc(vcpu, ecx, &data); | |
825 | if (err) | |
826 | return err; | |
827 | kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data); | |
828 | kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32); | |
829 | return err; | |
830 | } | |
831 | EXPORT_SYMBOL_GPL(kvm_rdpmc); | |
832 | ||
043405e1 CO |
833 | /* |
834 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
835 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
836 | * | |
837 | * This list is modified at module load time to reflect the | |
e3267cbb GC |
838 | * capabilities of the host cpu. This capabilities test skips MSRs that are |
839 | * kvm-specific. Those are put in the beginning of the list. | |
043405e1 | 840 | */ |
e3267cbb | 841 | |
439793d4 | 842 | #define KVM_SAVE_MSRS_BEGIN 10 |
043405e1 | 843 | static u32 msrs_to_save[] = { |
e3267cbb | 844 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, |
11c6bffa | 845 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, |
55cd8e5a | 846 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, |
c9aaa895 | 847 | HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, |
ae7a2a3f | 848 | MSR_KVM_PV_EOI_EN, |
043405e1 | 849 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, |
8c06585d | 850 | MSR_STAR, |
043405e1 CO |
851 | #ifdef CONFIG_X86_64 |
852 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
853 | #endif | |
e90aa41e | 854 | MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA |
043405e1 CO |
855 | }; |
856 | ||
857 | static unsigned num_msrs_to_save; | |
858 | ||
f1d24831 | 859 | static const u32 emulated_msrs[] = { |
ba904635 | 860 | MSR_IA32_TSC_ADJUST, |
a3e06bbe | 861 | MSR_IA32_TSCDEADLINE, |
043405e1 | 862 | MSR_IA32_MISC_ENABLE, |
908e75f3 AK |
863 | MSR_IA32_MCG_STATUS, |
864 | MSR_IA32_MCG_CTL, | |
043405e1 CO |
865 | }; |
866 | ||
384bb783 | 867 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) |
15c4a640 | 868 | { |
b69e8cae | 869 | if (efer & efer_reserved_bits) |
384bb783 | 870 | return false; |
15c4a640 | 871 | |
1b2fd70c AG |
872 | if (efer & EFER_FFXSR) { |
873 | struct kvm_cpuid_entry2 *feat; | |
874 | ||
875 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
b69e8cae | 876 | if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) |
384bb783 | 877 | return false; |
1b2fd70c AG |
878 | } |
879 | ||
d8017474 AG |
880 | if (efer & EFER_SVME) { |
881 | struct kvm_cpuid_entry2 *feat; | |
882 | ||
883 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
b69e8cae | 884 | if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) |
384bb783 | 885 | return false; |
d8017474 AG |
886 | } |
887 | ||
384bb783 JK |
888 | return true; |
889 | } | |
890 | EXPORT_SYMBOL_GPL(kvm_valid_efer); | |
891 | ||
892 | static int set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
893 | { | |
894 | u64 old_efer = vcpu->arch.efer; | |
895 | ||
896 | if (!kvm_valid_efer(vcpu, efer)) | |
897 | return 1; | |
898 | ||
899 | if (is_paging(vcpu) | |
900 | && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) | |
901 | return 1; | |
902 | ||
15c4a640 | 903 | efer &= ~EFER_LMA; |
f6801dff | 904 | efer |= vcpu->arch.efer & EFER_LMA; |
15c4a640 | 905 | |
a3d204e2 SY |
906 | kvm_x86_ops->set_efer(vcpu, efer); |
907 | ||
aad82703 SY |
908 | /* Update reserved bits */ |
909 | if ((efer ^ old_efer) & EFER_NX) | |
910 | kvm_mmu_reset_context(vcpu); | |
911 | ||
b69e8cae | 912 | return 0; |
15c4a640 CO |
913 | } |
914 | ||
f2b4b7dd JR |
915 | void kvm_enable_efer_bits(u64 mask) |
916 | { | |
917 | efer_reserved_bits &= ~mask; | |
918 | } | |
919 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
920 | ||
921 | ||
15c4a640 CO |
922 | /* |
923 | * Writes msr value into into the appropriate "register". | |
924 | * Returns 0 on success, non-0 otherwise. | |
925 | * Assumes vcpu_load() was already called. | |
926 | */ | |
8fe8ab46 | 927 | int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) |
15c4a640 | 928 | { |
8fe8ab46 | 929 | return kvm_x86_ops->set_msr(vcpu, msr); |
15c4a640 CO |
930 | } |
931 | ||
313a3dc7 CO |
932 | /* |
933 | * Adapt set_msr() to msr_io()'s calling convention | |
934 | */ | |
935 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
936 | { | |
8fe8ab46 WA |
937 | struct msr_data msr; |
938 | ||
939 | msr.data = *data; | |
940 | msr.index = index; | |
941 | msr.host_initiated = true; | |
942 | return kvm_set_msr(vcpu, &msr); | |
313a3dc7 CO |
943 | } |
944 | ||
16e8d74d MT |
945 | #ifdef CONFIG_X86_64 |
946 | struct pvclock_gtod_data { | |
947 | seqcount_t seq; | |
948 | ||
949 | struct { /* extract of a clocksource struct */ | |
950 | int vclock_mode; | |
951 | cycle_t cycle_last; | |
952 | cycle_t mask; | |
953 | u32 mult; | |
954 | u32 shift; | |
955 | } clock; | |
956 | ||
957 | /* open coded 'struct timespec' */ | |
958 | u64 monotonic_time_snsec; | |
959 | time_t monotonic_time_sec; | |
960 | }; | |
961 | ||
962 | static struct pvclock_gtod_data pvclock_gtod_data; | |
963 | ||
964 | static void update_pvclock_gtod(struct timekeeper *tk) | |
965 | { | |
966 | struct pvclock_gtod_data *vdata = &pvclock_gtod_data; | |
967 | ||
968 | write_seqcount_begin(&vdata->seq); | |
969 | ||
970 | /* copy pvclock gtod data */ | |
971 | vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode; | |
972 | vdata->clock.cycle_last = tk->clock->cycle_last; | |
973 | vdata->clock.mask = tk->clock->mask; | |
974 | vdata->clock.mult = tk->mult; | |
975 | vdata->clock.shift = tk->shift; | |
976 | ||
977 | vdata->monotonic_time_sec = tk->xtime_sec | |
978 | + tk->wall_to_monotonic.tv_sec; | |
979 | vdata->monotonic_time_snsec = tk->xtime_nsec | |
980 | + (tk->wall_to_monotonic.tv_nsec | |
981 | << tk->shift); | |
982 | while (vdata->monotonic_time_snsec >= | |
983 | (((u64)NSEC_PER_SEC) << tk->shift)) { | |
984 | vdata->monotonic_time_snsec -= | |
985 | ((u64)NSEC_PER_SEC) << tk->shift; | |
986 | vdata->monotonic_time_sec++; | |
987 | } | |
988 | ||
989 | write_seqcount_end(&vdata->seq); | |
990 | } | |
991 | #endif | |
992 | ||
993 | ||
18068523 GOC |
994 | static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) |
995 | { | |
9ed3c444 AK |
996 | int version; |
997 | int r; | |
50d0a0f9 | 998 | struct pvclock_wall_clock wc; |
923de3cf | 999 | struct timespec boot; |
18068523 GOC |
1000 | |
1001 | if (!wall_clock) | |
1002 | return; | |
1003 | ||
9ed3c444 AK |
1004 | r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); |
1005 | if (r) | |
1006 | return; | |
1007 | ||
1008 | if (version & 1) | |
1009 | ++version; /* first time write, random junk */ | |
1010 | ||
1011 | ++version; | |
18068523 | 1012 | |
18068523 GOC |
1013 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); |
1014 | ||
50d0a0f9 GH |
1015 | /* |
1016 | * The guest calculates current wall clock time by adding | |
34c238a1 | 1017 | * system time (updated by kvm_guest_time_update below) to the |
50d0a0f9 GH |
1018 | * wall clock specified here. guest system time equals host |
1019 | * system time for us, thus we must fill in host boot time here. | |
1020 | */ | |
923de3cf | 1021 | getboottime(&boot); |
50d0a0f9 | 1022 | |
4b648665 BR |
1023 | if (kvm->arch.kvmclock_offset) { |
1024 | struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset); | |
1025 | boot = timespec_sub(boot, ts); | |
1026 | } | |
50d0a0f9 GH |
1027 | wc.sec = boot.tv_sec; |
1028 | wc.nsec = boot.tv_nsec; | |
1029 | wc.version = version; | |
18068523 GOC |
1030 | |
1031 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
1032 | ||
1033 | version++; | |
1034 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
1035 | } |
1036 | ||
50d0a0f9 GH |
1037 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
1038 | { | |
1039 | uint32_t quotient, remainder; | |
1040 | ||
1041 | /* Don't try to replace with do_div(), this one calculates | |
1042 | * "(dividend << 32) / divisor" */ | |
1043 | __asm__ ( "divl %4" | |
1044 | : "=a" (quotient), "=d" (remainder) | |
1045 | : "0" (0), "1" (dividend), "r" (divisor) ); | |
1046 | return quotient; | |
1047 | } | |
1048 | ||
5f4e3f88 ZA |
1049 | static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz, |
1050 | s8 *pshift, u32 *pmultiplier) | |
50d0a0f9 | 1051 | { |
5f4e3f88 | 1052 | uint64_t scaled64; |
50d0a0f9 GH |
1053 | int32_t shift = 0; |
1054 | uint64_t tps64; | |
1055 | uint32_t tps32; | |
1056 | ||
5f4e3f88 ZA |
1057 | tps64 = base_khz * 1000LL; |
1058 | scaled64 = scaled_khz * 1000LL; | |
50933623 | 1059 | while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { |
50d0a0f9 GH |
1060 | tps64 >>= 1; |
1061 | shift--; | |
1062 | } | |
1063 | ||
1064 | tps32 = (uint32_t)tps64; | |
50933623 JK |
1065 | while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { |
1066 | if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) | |
5f4e3f88 ZA |
1067 | scaled64 >>= 1; |
1068 | else | |
1069 | tps32 <<= 1; | |
50d0a0f9 GH |
1070 | shift++; |
1071 | } | |
1072 | ||
5f4e3f88 ZA |
1073 | *pshift = shift; |
1074 | *pmultiplier = div_frac(scaled64, tps32); | |
50d0a0f9 | 1075 | |
5f4e3f88 ZA |
1076 | pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n", |
1077 | __func__, base_khz, scaled_khz, shift, *pmultiplier); | |
50d0a0f9 GH |
1078 | } |
1079 | ||
759379dd ZA |
1080 | static inline u64 get_kernel_ns(void) |
1081 | { | |
1082 | struct timespec ts; | |
1083 | ||
1084 | WARN_ON(preemptible()); | |
1085 | ktime_get_ts(&ts); | |
1086 | monotonic_to_bootbased(&ts); | |
1087 | return timespec_to_ns(&ts); | |
50d0a0f9 GH |
1088 | } |
1089 | ||
d828199e | 1090 | #ifdef CONFIG_X86_64 |
16e8d74d | 1091 | static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); |
d828199e | 1092 | #endif |
16e8d74d | 1093 | |
c8076604 | 1094 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
c285545f | 1095 | unsigned long max_tsc_khz; |
c8076604 | 1096 | |
cc578287 | 1097 | static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec) |
8cfdc000 | 1098 | { |
cc578287 ZA |
1099 | return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult, |
1100 | vcpu->arch.virtual_tsc_shift); | |
8cfdc000 ZA |
1101 | } |
1102 | ||
cc578287 | 1103 | static u32 adjust_tsc_khz(u32 khz, s32 ppm) |
1e993611 | 1104 | { |
cc578287 ZA |
1105 | u64 v = (u64)khz * (1000000 + ppm); |
1106 | do_div(v, 1000000); | |
1107 | return v; | |
1e993611 JR |
1108 | } |
1109 | ||
cc578287 | 1110 | static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz) |
759379dd | 1111 | { |
cc578287 ZA |
1112 | u32 thresh_lo, thresh_hi; |
1113 | int use_scaling = 0; | |
217fc9cf | 1114 | |
03ba32ca MT |
1115 | /* tsc_khz can be zero if TSC calibration fails */ |
1116 | if (this_tsc_khz == 0) | |
1117 | return; | |
1118 | ||
c285545f ZA |
1119 | /* Compute a scale to convert nanoseconds in TSC cycles */ |
1120 | kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000, | |
cc578287 ZA |
1121 | &vcpu->arch.virtual_tsc_shift, |
1122 | &vcpu->arch.virtual_tsc_mult); | |
1123 | vcpu->arch.virtual_tsc_khz = this_tsc_khz; | |
1124 | ||
1125 | /* | |
1126 | * Compute the variation in TSC rate which is acceptable | |
1127 | * within the range of tolerance and decide if the | |
1128 | * rate being applied is within that bounds of the hardware | |
1129 | * rate. If so, no scaling or compensation need be done. | |
1130 | */ | |
1131 | thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); | |
1132 | thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); | |
1133 | if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) { | |
1134 | pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi); | |
1135 | use_scaling = 1; | |
1136 | } | |
1137 | kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling); | |
c285545f ZA |
1138 | } |
1139 | ||
1140 | static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) | |
1141 | { | |
e26101b1 | 1142 | u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, |
cc578287 ZA |
1143 | vcpu->arch.virtual_tsc_mult, |
1144 | vcpu->arch.virtual_tsc_shift); | |
e26101b1 | 1145 | tsc += vcpu->arch.this_tsc_write; |
c285545f ZA |
1146 | return tsc; |
1147 | } | |
1148 | ||
b48aa97e MT |
1149 | void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) |
1150 | { | |
1151 | #ifdef CONFIG_X86_64 | |
1152 | bool vcpus_matched; | |
1153 | bool do_request = false; | |
1154 | struct kvm_arch *ka = &vcpu->kvm->arch; | |
1155 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
1156 | ||
1157 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
1158 | atomic_read(&vcpu->kvm->online_vcpus)); | |
1159 | ||
1160 | if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC) | |
1161 | if (!ka->use_master_clock) | |
1162 | do_request = 1; | |
1163 | ||
1164 | if (!vcpus_matched && ka->use_master_clock) | |
1165 | do_request = 1; | |
1166 | ||
1167 | if (do_request) | |
1168 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); | |
1169 | ||
1170 | trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, | |
1171 | atomic_read(&vcpu->kvm->online_vcpus), | |
1172 | ka->use_master_clock, gtod->clock.vclock_mode); | |
1173 | #endif | |
1174 | } | |
1175 | ||
ba904635 WA |
1176 | static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) |
1177 | { | |
1178 | u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu); | |
1179 | vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; | |
1180 | } | |
1181 | ||
8fe8ab46 | 1182 | void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) |
99e3e30a ZA |
1183 | { |
1184 | struct kvm *kvm = vcpu->kvm; | |
f38e098f | 1185 | u64 offset, ns, elapsed; |
99e3e30a | 1186 | unsigned long flags; |
02626b6a | 1187 | s64 usdiff; |
b48aa97e | 1188 | bool matched; |
8fe8ab46 | 1189 | u64 data = msr->data; |
99e3e30a | 1190 | |
038f8c11 | 1191 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); |
857e4099 | 1192 | offset = kvm_x86_ops->compute_tsc_offset(vcpu, data); |
759379dd | 1193 | ns = get_kernel_ns(); |
f38e098f | 1194 | elapsed = ns - kvm->arch.last_tsc_nsec; |
5d3cb0f6 | 1195 | |
03ba32ca MT |
1196 | if (vcpu->arch.virtual_tsc_khz) { |
1197 | /* n.b - signed multiplication and division required */ | |
1198 | usdiff = data - kvm->arch.last_tsc_write; | |
5d3cb0f6 | 1199 | #ifdef CONFIG_X86_64 |
03ba32ca | 1200 | usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz; |
5d3cb0f6 | 1201 | #else |
03ba32ca MT |
1202 | /* do_div() only does unsigned */ |
1203 | asm("idivl %2; xor %%edx, %%edx" | |
1204 | : "=A"(usdiff) | |
1205 | : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz)); | |
5d3cb0f6 | 1206 | #endif |
03ba32ca MT |
1207 | do_div(elapsed, 1000); |
1208 | usdiff -= elapsed; | |
1209 | if (usdiff < 0) | |
1210 | usdiff = -usdiff; | |
1211 | } else | |
1212 | usdiff = USEC_PER_SEC; /* disable TSC match window below */ | |
f38e098f ZA |
1213 | |
1214 | /* | |
5d3cb0f6 ZA |
1215 | * Special case: TSC write with a small delta (1 second) of virtual |
1216 | * cycle time against real time is interpreted as an attempt to | |
1217 | * synchronize the CPU. | |
1218 | * | |
1219 | * For a reliable TSC, we can match TSC offsets, and for an unstable | |
1220 | * TSC, we add elapsed time in this computation. We could let the | |
1221 | * compensation code attempt to catch up if we fall behind, but | |
1222 | * it's better to try to match offsets from the beginning. | |
1223 | */ | |
02626b6a | 1224 | if (usdiff < USEC_PER_SEC && |
5d3cb0f6 | 1225 | vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { |
f38e098f | 1226 | if (!check_tsc_unstable()) { |
e26101b1 | 1227 | offset = kvm->arch.cur_tsc_offset; |
f38e098f ZA |
1228 | pr_debug("kvm: matched tsc offset for %llu\n", data); |
1229 | } else { | |
857e4099 | 1230 | u64 delta = nsec_to_cycles(vcpu, elapsed); |
5d3cb0f6 ZA |
1231 | data += delta; |
1232 | offset = kvm_x86_ops->compute_tsc_offset(vcpu, data); | |
759379dd | 1233 | pr_debug("kvm: adjusted tsc offset by %llu\n", delta); |
f38e098f | 1234 | } |
b48aa97e | 1235 | matched = true; |
e26101b1 ZA |
1236 | } else { |
1237 | /* | |
1238 | * We split periods of matched TSC writes into generations. | |
1239 | * For each generation, we track the original measured | |
1240 | * nanosecond time, offset, and write, so if TSCs are in | |
1241 | * sync, we can match exact offset, and if not, we can match | |
4a969980 | 1242 | * exact software computation in compute_guest_tsc() |
e26101b1 ZA |
1243 | * |
1244 | * These values are tracked in kvm->arch.cur_xxx variables. | |
1245 | */ | |
1246 | kvm->arch.cur_tsc_generation++; | |
1247 | kvm->arch.cur_tsc_nsec = ns; | |
1248 | kvm->arch.cur_tsc_write = data; | |
1249 | kvm->arch.cur_tsc_offset = offset; | |
b48aa97e | 1250 | matched = false; |
e26101b1 ZA |
1251 | pr_debug("kvm: new tsc generation %u, clock %llu\n", |
1252 | kvm->arch.cur_tsc_generation, data); | |
f38e098f | 1253 | } |
e26101b1 ZA |
1254 | |
1255 | /* | |
1256 | * We also track th most recent recorded KHZ, write and time to | |
1257 | * allow the matching interval to be extended at each write. | |
1258 | */ | |
f38e098f ZA |
1259 | kvm->arch.last_tsc_nsec = ns; |
1260 | kvm->arch.last_tsc_write = data; | |
5d3cb0f6 | 1261 | kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; |
99e3e30a ZA |
1262 | |
1263 | /* Reset of TSC must disable overshoot protection below */ | |
1264 | vcpu->arch.hv_clock.tsc_timestamp = 0; | |
b183aa58 | 1265 | vcpu->arch.last_guest_tsc = data; |
e26101b1 ZA |
1266 | |
1267 | /* Keep track of which generation this VCPU has synchronized to */ | |
1268 | vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; | |
1269 | vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; | |
1270 | vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; | |
1271 | ||
ba904635 WA |
1272 | if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated) |
1273 | update_ia32_tsc_adjust_msr(vcpu, offset); | |
e26101b1 ZA |
1274 | kvm_x86_ops->write_tsc_offset(vcpu, offset); |
1275 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); | |
b48aa97e MT |
1276 | |
1277 | spin_lock(&kvm->arch.pvclock_gtod_sync_lock); | |
1278 | if (matched) | |
1279 | kvm->arch.nr_vcpus_matched_tsc++; | |
1280 | else | |
1281 | kvm->arch.nr_vcpus_matched_tsc = 0; | |
1282 | ||
1283 | kvm_track_tsc_matching(vcpu); | |
1284 | spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); | |
99e3e30a | 1285 | } |
e26101b1 | 1286 | |
99e3e30a ZA |
1287 | EXPORT_SYMBOL_GPL(kvm_write_tsc); |
1288 | ||
d828199e MT |
1289 | #ifdef CONFIG_X86_64 |
1290 | ||
1291 | static cycle_t read_tsc(void) | |
1292 | { | |
1293 | cycle_t ret; | |
1294 | u64 last; | |
1295 | ||
1296 | /* | |
1297 | * Empirically, a fence (of type that depends on the CPU) | |
1298 | * before rdtsc is enough to ensure that rdtsc is ordered | |
1299 | * with respect to loads. The various CPU manuals are unclear | |
1300 | * as to whether rdtsc can be reordered with later loads, | |
1301 | * but no one has ever seen it happen. | |
1302 | */ | |
1303 | rdtsc_barrier(); | |
1304 | ret = (cycle_t)vget_cycles(); | |
1305 | ||
1306 | last = pvclock_gtod_data.clock.cycle_last; | |
1307 | ||
1308 | if (likely(ret >= last)) | |
1309 | return ret; | |
1310 | ||
1311 | /* | |
1312 | * GCC likes to generate cmov here, but this branch is extremely | |
1313 | * predictable (it's just a funciton of time and the likely is | |
1314 | * very likely) and there's a data dependence, so force GCC | |
1315 | * to generate a branch instead. I don't barrier() because | |
1316 | * we don't actually need a barrier, and if this function | |
1317 | * ever gets inlined it will generate worse code. | |
1318 | */ | |
1319 | asm volatile (""); | |
1320 | return last; | |
1321 | } | |
1322 | ||
1323 | static inline u64 vgettsc(cycle_t *cycle_now) | |
1324 | { | |
1325 | long v; | |
1326 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
1327 | ||
1328 | *cycle_now = read_tsc(); | |
1329 | ||
1330 | v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask; | |
1331 | return v * gtod->clock.mult; | |
1332 | } | |
1333 | ||
1334 | static int do_monotonic(struct timespec *ts, cycle_t *cycle_now) | |
1335 | { | |
1336 | unsigned long seq; | |
1337 | u64 ns; | |
1338 | int mode; | |
1339 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
1340 | ||
1341 | ts->tv_nsec = 0; | |
1342 | do { | |
1343 | seq = read_seqcount_begin(>od->seq); | |
1344 | mode = gtod->clock.vclock_mode; | |
1345 | ts->tv_sec = gtod->monotonic_time_sec; | |
1346 | ns = gtod->monotonic_time_snsec; | |
1347 | ns += vgettsc(cycle_now); | |
1348 | ns >>= gtod->clock.shift; | |
1349 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); | |
1350 | timespec_add_ns(ts, ns); | |
1351 | ||
1352 | return mode; | |
1353 | } | |
1354 | ||
1355 | /* returns true if host is using tsc clocksource */ | |
1356 | static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now) | |
1357 | { | |
1358 | struct timespec ts; | |
1359 | ||
1360 | /* checked again under seqlock below */ | |
1361 | if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC) | |
1362 | return false; | |
1363 | ||
1364 | if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC) | |
1365 | return false; | |
1366 | ||
1367 | monotonic_to_bootbased(&ts); | |
1368 | *kernel_ns = timespec_to_ns(&ts); | |
1369 | ||
1370 | return true; | |
1371 | } | |
1372 | #endif | |
1373 | ||
1374 | /* | |
1375 | * | |
b48aa97e MT |
1376 | * Assuming a stable TSC across physical CPUS, and a stable TSC |
1377 | * across virtual CPUs, the following condition is possible. | |
1378 | * Each numbered line represents an event visible to both | |
d828199e MT |
1379 | * CPUs at the next numbered event. |
1380 | * | |
1381 | * "timespecX" represents host monotonic time. "tscX" represents | |
1382 | * RDTSC value. | |
1383 | * | |
1384 | * VCPU0 on CPU0 | VCPU1 on CPU1 | |
1385 | * | |
1386 | * 1. read timespec0,tsc0 | |
1387 | * 2. | timespec1 = timespec0 + N | |
1388 | * | tsc1 = tsc0 + M | |
1389 | * 3. transition to guest | transition to guest | |
1390 | * 4. ret0 = timespec0 + (rdtsc - tsc0) | | |
1391 | * 5. | ret1 = timespec1 + (rdtsc - tsc1) | |
1392 | * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) | |
1393 | * | |
1394 | * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: | |
1395 | * | |
1396 | * - ret0 < ret1 | |
1397 | * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) | |
1398 | * ... | |
1399 | * - 0 < N - M => M < N | |
1400 | * | |
1401 | * That is, when timespec0 != timespec1, M < N. Unfortunately that is not | |
1402 | * always the case (the difference between two distinct xtime instances | |
1403 | * might be smaller then the difference between corresponding TSC reads, | |
1404 | * when updating guest vcpus pvclock areas). | |
1405 | * | |
1406 | * To avoid that problem, do not allow visibility of distinct | |
1407 | * system_timestamp/tsc_timestamp values simultaneously: use a master | |
1408 | * copy of host monotonic time values. Update that master copy | |
1409 | * in lockstep. | |
1410 | * | |
b48aa97e | 1411 | * Rely on synchronization of host TSCs and guest TSCs for monotonicity. |
d828199e MT |
1412 | * |
1413 | */ | |
1414 | ||
1415 | static void pvclock_update_vm_gtod_copy(struct kvm *kvm) | |
1416 | { | |
1417 | #ifdef CONFIG_X86_64 | |
1418 | struct kvm_arch *ka = &kvm->arch; | |
1419 | int vclock_mode; | |
b48aa97e MT |
1420 | bool host_tsc_clocksource, vcpus_matched; |
1421 | ||
1422 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
1423 | atomic_read(&kvm->online_vcpus)); | |
d828199e MT |
1424 | |
1425 | /* | |
1426 | * If the host uses TSC clock, then passthrough TSC as stable | |
1427 | * to the guest. | |
1428 | */ | |
b48aa97e | 1429 | host_tsc_clocksource = kvm_get_time_and_clockread( |
d828199e MT |
1430 | &ka->master_kernel_ns, |
1431 | &ka->master_cycle_now); | |
1432 | ||
b48aa97e MT |
1433 | ka->use_master_clock = host_tsc_clocksource & vcpus_matched; |
1434 | ||
d828199e MT |
1435 | if (ka->use_master_clock) |
1436 | atomic_set(&kvm_guest_has_master_clock, 1); | |
1437 | ||
1438 | vclock_mode = pvclock_gtod_data.clock.vclock_mode; | |
b48aa97e MT |
1439 | trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, |
1440 | vcpus_matched); | |
d828199e MT |
1441 | #endif |
1442 | } | |
1443 | ||
34c238a1 | 1444 | static int kvm_guest_time_update(struct kvm_vcpu *v) |
18068523 | 1445 | { |
d828199e | 1446 | unsigned long flags, this_tsc_khz; |
18068523 | 1447 | struct kvm_vcpu_arch *vcpu = &v->arch; |
d828199e | 1448 | struct kvm_arch *ka = &v->kvm->arch; |
1d5f066e | 1449 | s64 kernel_ns, max_kernel_ns; |
d828199e | 1450 | u64 tsc_timestamp, host_tsc; |
0b79459b | 1451 | struct pvclock_vcpu_time_info guest_hv_clock; |
51d59c6b | 1452 | u8 pvclock_flags; |
d828199e MT |
1453 | bool use_master_clock; |
1454 | ||
1455 | kernel_ns = 0; | |
1456 | host_tsc = 0; | |
18068523 | 1457 | |
d828199e MT |
1458 | /* |
1459 | * If the host uses TSC clock, then passthrough TSC as stable | |
1460 | * to the guest. | |
1461 | */ | |
1462 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
1463 | use_master_clock = ka->use_master_clock; | |
1464 | if (use_master_clock) { | |
1465 | host_tsc = ka->master_cycle_now; | |
1466 | kernel_ns = ka->master_kernel_ns; | |
1467 | } | |
1468 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
c09664bb MT |
1469 | |
1470 | /* Keep irq disabled to prevent changes to the clock */ | |
1471 | local_irq_save(flags); | |
1472 | this_tsc_khz = __get_cpu_var(cpu_tsc_khz); | |
1473 | if (unlikely(this_tsc_khz == 0)) { | |
1474 | local_irq_restore(flags); | |
1475 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); | |
1476 | return 1; | |
1477 | } | |
d828199e MT |
1478 | if (!use_master_clock) { |
1479 | host_tsc = native_read_tsc(); | |
1480 | kernel_ns = get_kernel_ns(); | |
1481 | } | |
1482 | ||
1483 | tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc); | |
1484 | ||
c285545f ZA |
1485 | /* |
1486 | * We may have to catch up the TSC to match elapsed wall clock | |
1487 | * time for two reasons, even if kvmclock is used. | |
1488 | * 1) CPU could have been running below the maximum TSC rate | |
1489 | * 2) Broken TSC compensation resets the base at each VCPU | |
1490 | * entry to avoid unknown leaps of TSC even when running | |
1491 | * again on the same CPU. This may cause apparent elapsed | |
1492 | * time to disappear, and the guest to stand still or run | |
1493 | * very slowly. | |
1494 | */ | |
1495 | if (vcpu->tsc_catchup) { | |
1496 | u64 tsc = compute_guest_tsc(v, kernel_ns); | |
1497 | if (tsc > tsc_timestamp) { | |
f1e2b260 | 1498 | adjust_tsc_offset_guest(v, tsc - tsc_timestamp); |
c285545f ZA |
1499 | tsc_timestamp = tsc; |
1500 | } | |
50d0a0f9 GH |
1501 | } |
1502 | ||
18068523 GOC |
1503 | local_irq_restore(flags); |
1504 | ||
0b79459b | 1505 | if (!vcpu->pv_time_enabled) |
c285545f | 1506 | return 0; |
18068523 | 1507 | |
1d5f066e ZA |
1508 | /* |
1509 | * Time as measured by the TSC may go backwards when resetting the base | |
1510 | * tsc_timestamp. The reason for this is that the TSC resolution is | |
1511 | * higher than the resolution of the other clock scales. Thus, many | |
1512 | * possible measurments of the TSC correspond to one measurement of any | |
1513 | * other clock, and so a spread of values is possible. This is not a | |
1514 | * problem for the computation of the nanosecond clock; with TSC rates | |
1515 | * around 1GHZ, there can only be a few cycles which correspond to one | |
1516 | * nanosecond value, and any path through this code will inevitably | |
1517 | * take longer than that. However, with the kernel_ns value itself, | |
1518 | * the precision may be much lower, down to HZ granularity. If the | |
1519 | * first sampling of TSC against kernel_ns ends in the low part of the | |
1520 | * range, and the second in the high end of the range, we can get: | |
1521 | * | |
1522 | * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new | |
1523 | * | |
1524 | * As the sampling errors potentially range in the thousands of cycles, | |
1525 | * it is possible such a time value has already been observed by the | |
1526 | * guest. To protect against this, we must compute the system time as | |
1527 | * observed by the guest and ensure the new system time is greater. | |
1528 | */ | |
1529 | max_kernel_ns = 0; | |
b183aa58 | 1530 | if (vcpu->hv_clock.tsc_timestamp) { |
1d5f066e ZA |
1531 | max_kernel_ns = vcpu->last_guest_tsc - |
1532 | vcpu->hv_clock.tsc_timestamp; | |
1533 | max_kernel_ns = pvclock_scale_delta(max_kernel_ns, | |
1534 | vcpu->hv_clock.tsc_to_system_mul, | |
1535 | vcpu->hv_clock.tsc_shift); | |
1536 | max_kernel_ns += vcpu->last_kernel_ns; | |
1537 | } | |
afbcf7ab | 1538 | |
e48672fa | 1539 | if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) { |
5f4e3f88 ZA |
1540 | kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz, |
1541 | &vcpu->hv_clock.tsc_shift, | |
1542 | &vcpu->hv_clock.tsc_to_system_mul); | |
e48672fa | 1543 | vcpu->hw_tsc_khz = this_tsc_khz; |
8cfdc000 ZA |
1544 | } |
1545 | ||
d828199e MT |
1546 | /* with a master <monotonic time, tsc value> tuple, |
1547 | * pvclock clock reads always increase at the (scaled) rate | |
1548 | * of guest TSC - no need to deal with sampling errors. | |
1549 | */ | |
1550 | if (!use_master_clock) { | |
1551 | if (max_kernel_ns > kernel_ns) | |
1552 | kernel_ns = max_kernel_ns; | |
1553 | } | |
8cfdc000 | 1554 | /* With all the info we got, fill in the values */ |
1d5f066e | 1555 | vcpu->hv_clock.tsc_timestamp = tsc_timestamp; |
759379dd | 1556 | vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; |
1d5f066e | 1557 | vcpu->last_kernel_ns = kernel_ns; |
28e4639a | 1558 | vcpu->last_guest_tsc = tsc_timestamp; |
51d59c6b | 1559 | |
18068523 GOC |
1560 | /* |
1561 | * The interface expects us to write an even number signaling that the | |
1562 | * update is finished. Since the guest won't see the intermediate | |
50d0a0f9 | 1563 | * state, we just increase by 2 at the end. |
18068523 | 1564 | */ |
50d0a0f9 | 1565 | vcpu->hv_clock.version += 2; |
18068523 | 1566 | |
0b79459b AH |
1567 | if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, |
1568 | &guest_hv_clock, sizeof(guest_hv_clock)))) | |
1569 | return 0; | |
78c0337a MT |
1570 | |
1571 | /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ | |
0b79459b | 1572 | pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); |
78c0337a MT |
1573 | |
1574 | if (vcpu->pvclock_set_guest_stopped_request) { | |
1575 | pvclock_flags |= PVCLOCK_GUEST_STOPPED; | |
1576 | vcpu->pvclock_set_guest_stopped_request = false; | |
1577 | } | |
1578 | ||
d828199e MT |
1579 | /* If the host uses TSC clocksource, then it is stable */ |
1580 | if (use_master_clock) | |
1581 | pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; | |
1582 | ||
78c0337a MT |
1583 | vcpu->hv_clock.flags = pvclock_flags; |
1584 | ||
0b79459b AH |
1585 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
1586 | &vcpu->hv_clock, | |
1587 | sizeof(vcpu->hv_clock)); | |
8cfdc000 | 1588 | return 0; |
c8076604 GH |
1589 | } |
1590 | ||
9ba075a6 AK |
1591 | static bool msr_mtrr_valid(unsigned msr) |
1592 | { | |
1593 | switch (msr) { | |
1594 | case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1: | |
1595 | case MSR_MTRRfix64K_00000: | |
1596 | case MSR_MTRRfix16K_80000: | |
1597 | case MSR_MTRRfix16K_A0000: | |
1598 | case MSR_MTRRfix4K_C0000: | |
1599 | case MSR_MTRRfix4K_C8000: | |
1600 | case MSR_MTRRfix4K_D0000: | |
1601 | case MSR_MTRRfix4K_D8000: | |
1602 | case MSR_MTRRfix4K_E0000: | |
1603 | case MSR_MTRRfix4K_E8000: | |
1604 | case MSR_MTRRfix4K_F0000: | |
1605 | case MSR_MTRRfix4K_F8000: | |
1606 | case MSR_MTRRdefType: | |
1607 | case MSR_IA32_CR_PAT: | |
1608 | return true; | |
1609 | case 0x2f8: | |
1610 | return true; | |
1611 | } | |
1612 | return false; | |
1613 | } | |
1614 | ||
d6289b93 MT |
1615 | static bool valid_pat_type(unsigned t) |
1616 | { | |
1617 | return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */ | |
1618 | } | |
1619 | ||
1620 | static bool valid_mtrr_type(unsigned t) | |
1621 | { | |
1622 | return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */ | |
1623 | } | |
1624 | ||
1625 | static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1626 | { | |
1627 | int i; | |
1628 | ||
1629 | if (!msr_mtrr_valid(msr)) | |
1630 | return false; | |
1631 | ||
1632 | if (msr == MSR_IA32_CR_PAT) { | |
1633 | for (i = 0; i < 8; i++) | |
1634 | if (!valid_pat_type((data >> (i * 8)) & 0xff)) | |
1635 | return false; | |
1636 | return true; | |
1637 | } else if (msr == MSR_MTRRdefType) { | |
1638 | if (data & ~0xcff) | |
1639 | return false; | |
1640 | return valid_mtrr_type(data & 0xff); | |
1641 | } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) { | |
1642 | for (i = 0; i < 8 ; i++) | |
1643 | if (!valid_mtrr_type((data >> (i * 8)) & 0xff)) | |
1644 | return false; | |
1645 | return true; | |
1646 | } | |
1647 | ||
1648 | /* variable MTRRs */ | |
1649 | return valid_mtrr_type(data & 0xff); | |
1650 | } | |
1651 | ||
9ba075a6 AK |
1652 | static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
1653 | { | |
0bed3b56 SY |
1654 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; |
1655 | ||
d6289b93 | 1656 | if (!mtrr_valid(vcpu, msr, data)) |
9ba075a6 AK |
1657 | return 1; |
1658 | ||
0bed3b56 SY |
1659 | if (msr == MSR_MTRRdefType) { |
1660 | vcpu->arch.mtrr_state.def_type = data; | |
1661 | vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10; | |
1662 | } else if (msr == MSR_MTRRfix64K_00000) | |
1663 | p[0] = data; | |
1664 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
1665 | p[1 + msr - MSR_MTRRfix16K_80000] = data; | |
1666 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
1667 | p[3 + msr - MSR_MTRRfix4K_C0000] = data; | |
1668 | else if (msr == MSR_IA32_CR_PAT) | |
1669 | vcpu->arch.pat = data; | |
1670 | else { /* Variable MTRRs */ | |
1671 | int idx, is_mtrr_mask; | |
1672 | u64 *pt; | |
1673 | ||
1674 | idx = (msr - 0x200) / 2; | |
1675 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
1676 | if (!is_mtrr_mask) | |
1677 | pt = | |
1678 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
1679 | else | |
1680 | pt = | |
1681 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
1682 | *pt = data; | |
1683 | } | |
1684 | ||
1685 | kvm_mmu_reset_context(vcpu); | |
9ba075a6 AK |
1686 | return 0; |
1687 | } | |
15c4a640 | 1688 | |
890ca9ae | 1689 | static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
15c4a640 | 1690 | { |
890ca9ae HY |
1691 | u64 mcg_cap = vcpu->arch.mcg_cap; |
1692 | unsigned bank_num = mcg_cap & 0xff; | |
1693 | ||
15c4a640 | 1694 | switch (msr) { |
15c4a640 | 1695 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 1696 | vcpu->arch.mcg_status = data; |
15c4a640 | 1697 | break; |
c7ac679c | 1698 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
1699 | if (!(mcg_cap & MCG_CTL_P)) |
1700 | return 1; | |
1701 | if (data != 0 && data != ~(u64)0) | |
1702 | return -1; | |
1703 | vcpu->arch.mcg_ctl = data; | |
1704 | break; | |
1705 | default: | |
1706 | if (msr >= MSR_IA32_MC0_CTL && | |
1707 | msr < MSR_IA32_MC0_CTL + 4 * bank_num) { | |
1708 | u32 offset = msr - MSR_IA32_MC0_CTL; | |
114be429 AP |
1709 | /* only 0 or all 1s can be written to IA32_MCi_CTL |
1710 | * some Linux kernels though clear bit 10 in bank 4 to | |
1711 | * workaround a BIOS/GART TBL issue on AMD K8s, ignore | |
1712 | * this to avoid an uncatched #GP in the guest | |
1713 | */ | |
890ca9ae | 1714 | if ((offset & 0x3) == 0 && |
114be429 | 1715 | data != 0 && (data | (1 << 10)) != ~(u64)0) |
890ca9ae HY |
1716 | return -1; |
1717 | vcpu->arch.mce_banks[offset] = data; | |
1718 | break; | |
1719 | } | |
1720 | return 1; | |
1721 | } | |
1722 | return 0; | |
1723 | } | |
1724 | ||
ffde22ac ES |
1725 | static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) |
1726 | { | |
1727 | struct kvm *kvm = vcpu->kvm; | |
1728 | int lm = is_long_mode(vcpu); | |
1729 | u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 | |
1730 | : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; | |
1731 | u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 | |
1732 | : kvm->arch.xen_hvm_config.blob_size_32; | |
1733 | u32 page_num = data & ~PAGE_MASK; | |
1734 | u64 page_addr = data & PAGE_MASK; | |
1735 | u8 *page; | |
1736 | int r; | |
1737 | ||
1738 | r = -E2BIG; | |
1739 | if (page_num >= blob_size) | |
1740 | goto out; | |
1741 | r = -ENOMEM; | |
ff5c2c03 SL |
1742 | page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); |
1743 | if (IS_ERR(page)) { | |
1744 | r = PTR_ERR(page); | |
ffde22ac | 1745 | goto out; |
ff5c2c03 | 1746 | } |
ffde22ac ES |
1747 | if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE)) |
1748 | goto out_free; | |
1749 | r = 0; | |
1750 | out_free: | |
1751 | kfree(page); | |
1752 | out: | |
1753 | return r; | |
1754 | } | |
1755 | ||
55cd8e5a GN |
1756 | static bool kvm_hv_hypercall_enabled(struct kvm *kvm) |
1757 | { | |
1758 | return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE; | |
1759 | } | |
1760 | ||
1761 | static bool kvm_hv_msr_partition_wide(u32 msr) | |
1762 | { | |
1763 | bool r = false; | |
1764 | switch (msr) { | |
1765 | case HV_X64_MSR_GUEST_OS_ID: | |
1766 | case HV_X64_MSR_HYPERCALL: | |
1767 | r = true; | |
1768 | break; | |
1769 | } | |
1770 | ||
1771 | return r; | |
1772 | } | |
1773 | ||
1774 | static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1775 | { | |
1776 | struct kvm *kvm = vcpu->kvm; | |
1777 | ||
1778 | switch (msr) { | |
1779 | case HV_X64_MSR_GUEST_OS_ID: | |
1780 | kvm->arch.hv_guest_os_id = data; | |
1781 | /* setting guest os id to zero disables hypercall page */ | |
1782 | if (!kvm->arch.hv_guest_os_id) | |
1783 | kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE; | |
1784 | break; | |
1785 | case HV_X64_MSR_HYPERCALL: { | |
1786 | u64 gfn; | |
1787 | unsigned long addr; | |
1788 | u8 instructions[4]; | |
1789 | ||
1790 | /* if guest os id is not set hypercall should remain disabled */ | |
1791 | if (!kvm->arch.hv_guest_os_id) | |
1792 | break; | |
1793 | if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) { | |
1794 | kvm->arch.hv_hypercall = data; | |
1795 | break; | |
1796 | } | |
1797 | gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT; | |
1798 | addr = gfn_to_hva(kvm, gfn); | |
1799 | if (kvm_is_error_hva(addr)) | |
1800 | return 1; | |
1801 | kvm_x86_ops->patch_hypercall(vcpu, instructions); | |
1802 | ((unsigned char *)instructions)[3] = 0xc3; /* ret */ | |
8b0cedff | 1803 | if (__copy_to_user((void __user *)addr, instructions, 4)) |
55cd8e5a GN |
1804 | return 1; |
1805 | kvm->arch.hv_hypercall = data; | |
1806 | break; | |
1807 | } | |
1808 | default: | |
a737f256 CD |
1809 | vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " |
1810 | "data 0x%llx\n", msr, data); | |
55cd8e5a GN |
1811 | return 1; |
1812 | } | |
1813 | return 0; | |
1814 | } | |
1815 | ||
1816 | static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1817 | { | |
10388a07 GN |
1818 | switch (msr) { |
1819 | case HV_X64_MSR_APIC_ASSIST_PAGE: { | |
1820 | unsigned long addr; | |
55cd8e5a | 1821 | |
10388a07 GN |
1822 | if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) { |
1823 | vcpu->arch.hv_vapic = data; | |
1824 | break; | |
1825 | } | |
1826 | addr = gfn_to_hva(vcpu->kvm, data >> | |
1827 | HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT); | |
1828 | if (kvm_is_error_hva(addr)) | |
1829 | return 1; | |
8b0cedff | 1830 | if (__clear_user((void __user *)addr, PAGE_SIZE)) |
10388a07 GN |
1831 | return 1; |
1832 | vcpu->arch.hv_vapic = data; | |
1833 | break; | |
1834 | } | |
1835 | case HV_X64_MSR_EOI: | |
1836 | return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data); | |
1837 | case HV_X64_MSR_ICR: | |
1838 | return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data); | |
1839 | case HV_X64_MSR_TPR: | |
1840 | return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data); | |
1841 | default: | |
a737f256 CD |
1842 | vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " |
1843 | "data 0x%llx\n", msr, data); | |
10388a07 GN |
1844 | return 1; |
1845 | } | |
1846 | ||
1847 | return 0; | |
55cd8e5a GN |
1848 | } |
1849 | ||
344d9588 GN |
1850 | static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) |
1851 | { | |
1852 | gpa_t gpa = data & ~0x3f; | |
1853 | ||
4a969980 | 1854 | /* Bits 2:5 are reserved, Should be zero */ |
6adba527 | 1855 | if (data & 0x3c) |
344d9588 GN |
1856 | return 1; |
1857 | ||
1858 | vcpu->arch.apf.msr_val = data; | |
1859 | ||
1860 | if (!(data & KVM_ASYNC_PF_ENABLED)) { | |
1861 | kvm_clear_async_pf_completion_queue(vcpu); | |
1862 | kvm_async_pf_hash_reset(vcpu); | |
1863 | return 0; | |
1864 | } | |
1865 | ||
8f964525 AH |
1866 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, |
1867 | sizeof(u32))) | |
344d9588 GN |
1868 | return 1; |
1869 | ||
6adba527 | 1870 | vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); |
344d9588 GN |
1871 | kvm_async_pf_wakeup_all(vcpu); |
1872 | return 0; | |
1873 | } | |
1874 | ||
12f9a48f GC |
1875 | static void kvmclock_reset(struct kvm_vcpu *vcpu) |
1876 | { | |
0b79459b | 1877 | vcpu->arch.pv_time_enabled = false; |
12f9a48f GC |
1878 | } |
1879 | ||
c9aaa895 GC |
1880 | static void accumulate_steal_time(struct kvm_vcpu *vcpu) |
1881 | { | |
1882 | u64 delta; | |
1883 | ||
1884 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) | |
1885 | return; | |
1886 | ||
1887 | delta = current->sched_info.run_delay - vcpu->arch.st.last_steal; | |
1888 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
1889 | vcpu->arch.st.accum_steal = delta; | |
1890 | } | |
1891 | ||
1892 | static void record_steal_time(struct kvm_vcpu *vcpu) | |
1893 | { | |
1894 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) | |
1895 | return; | |
1896 | ||
1897 | if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, | |
1898 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) | |
1899 | return; | |
1900 | ||
1901 | vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal; | |
1902 | vcpu->arch.st.steal.version += 2; | |
1903 | vcpu->arch.st.accum_steal = 0; | |
1904 | ||
1905 | kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, | |
1906 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); | |
1907 | } | |
1908 | ||
8fe8ab46 | 1909 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 1910 | { |
5753785f | 1911 | bool pr = false; |
8fe8ab46 WA |
1912 | u32 msr = msr_info->index; |
1913 | u64 data = msr_info->data; | |
5753785f | 1914 | |
15c4a640 | 1915 | switch (msr) { |
2e32b719 BP |
1916 | case MSR_AMD64_NB_CFG: |
1917 | case MSR_IA32_UCODE_REV: | |
1918 | case MSR_IA32_UCODE_WRITE: | |
1919 | case MSR_VM_HSAVE_PA: | |
1920 | case MSR_AMD64_PATCH_LOADER: | |
1921 | case MSR_AMD64_BU_CFG2: | |
1922 | break; | |
1923 | ||
15c4a640 | 1924 | case MSR_EFER: |
b69e8cae | 1925 | return set_efer(vcpu, data); |
8f1589d9 AP |
1926 | case MSR_K7_HWCR: |
1927 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
82494028 | 1928 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ |
a223c313 | 1929 | data &= ~(u64)0x8; /* ignore TLB cache disable */ |
8f1589d9 | 1930 | if (data != 0) { |
a737f256 CD |
1931 | vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", |
1932 | data); | |
8f1589d9 AP |
1933 | return 1; |
1934 | } | |
15c4a640 | 1935 | break; |
f7c6d140 AP |
1936 | case MSR_FAM10H_MMIO_CONF_BASE: |
1937 | if (data != 0) { | |
a737f256 CD |
1938 | vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " |
1939 | "0x%llx\n", data); | |
f7c6d140 AP |
1940 | return 1; |
1941 | } | |
15c4a640 | 1942 | break; |
b5e2fec0 AG |
1943 | case MSR_IA32_DEBUGCTLMSR: |
1944 | if (!data) { | |
1945 | /* We support the non-activated case already */ | |
1946 | break; | |
1947 | } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { | |
1948 | /* Values other than LBR and BTF are vendor-specific, | |
1949 | thus reserved and should throw a #GP */ | |
1950 | return 1; | |
1951 | } | |
a737f256 CD |
1952 | vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", |
1953 | __func__, data); | |
b5e2fec0 | 1954 | break; |
9ba075a6 AK |
1955 | case 0x200 ... 0x2ff: |
1956 | return set_msr_mtrr(vcpu, msr, data); | |
15c4a640 CO |
1957 | case MSR_IA32_APICBASE: |
1958 | kvm_set_apic_base(vcpu, data); | |
1959 | break; | |
0105d1a5 GN |
1960 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
1961 | return kvm_x2apic_msr_write(vcpu, msr, data); | |
a3e06bbe LJ |
1962 | case MSR_IA32_TSCDEADLINE: |
1963 | kvm_set_lapic_tscdeadline_msr(vcpu, data); | |
1964 | break; | |
ba904635 WA |
1965 | case MSR_IA32_TSC_ADJUST: |
1966 | if (guest_cpuid_has_tsc_adjust(vcpu)) { | |
1967 | if (!msr_info->host_initiated) { | |
1968 | u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; | |
1969 | kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true); | |
1970 | } | |
1971 | vcpu->arch.ia32_tsc_adjust_msr = data; | |
1972 | } | |
1973 | break; | |
15c4a640 | 1974 | case MSR_IA32_MISC_ENABLE: |
ad312c7c | 1975 | vcpu->arch.ia32_misc_enable_msr = data; |
15c4a640 | 1976 | break; |
11c6bffa | 1977 | case MSR_KVM_WALL_CLOCK_NEW: |
18068523 GOC |
1978 | case MSR_KVM_WALL_CLOCK: |
1979 | vcpu->kvm->arch.wall_clock = data; | |
1980 | kvm_write_wall_clock(vcpu->kvm, data); | |
1981 | break; | |
11c6bffa | 1982 | case MSR_KVM_SYSTEM_TIME_NEW: |
18068523 | 1983 | case MSR_KVM_SYSTEM_TIME: { |
0b79459b | 1984 | u64 gpa_offset; |
12f9a48f | 1985 | kvmclock_reset(vcpu); |
18068523 GOC |
1986 | |
1987 | vcpu->arch.time = data; | |
c285545f | 1988 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
18068523 GOC |
1989 | |
1990 | /* we verify if the enable bit is set... */ | |
1991 | if (!(data & 1)) | |
1992 | break; | |
1993 | ||
0b79459b | 1994 | gpa_offset = data & ~(PAGE_MASK | 1); |
18068523 | 1995 | |
0b79459b | 1996 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, |
8f964525 AH |
1997 | &vcpu->arch.pv_time, data & ~1ULL, |
1998 | sizeof(struct pvclock_vcpu_time_info))) | |
0b79459b AH |
1999 | vcpu->arch.pv_time_enabled = false; |
2000 | else | |
2001 | vcpu->arch.pv_time_enabled = true; | |
32cad84f | 2002 | |
18068523 GOC |
2003 | break; |
2004 | } | |
344d9588 GN |
2005 | case MSR_KVM_ASYNC_PF_EN: |
2006 | if (kvm_pv_enable_async_pf(vcpu, data)) | |
2007 | return 1; | |
2008 | break; | |
c9aaa895 GC |
2009 | case MSR_KVM_STEAL_TIME: |
2010 | ||
2011 | if (unlikely(!sched_info_on())) | |
2012 | return 1; | |
2013 | ||
2014 | if (data & KVM_STEAL_RESERVED_MASK) | |
2015 | return 1; | |
2016 | ||
2017 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, | |
8f964525 AH |
2018 | data & KVM_STEAL_VALID_BITS, |
2019 | sizeof(struct kvm_steal_time))) | |
c9aaa895 GC |
2020 | return 1; |
2021 | ||
2022 | vcpu->arch.st.msr_val = data; | |
2023 | ||
2024 | if (!(data & KVM_MSR_ENABLED)) | |
2025 | break; | |
2026 | ||
2027 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
2028 | ||
2029 | preempt_disable(); | |
2030 | accumulate_steal_time(vcpu); | |
2031 | preempt_enable(); | |
2032 | ||
2033 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); | |
2034 | ||
2035 | break; | |
ae7a2a3f MT |
2036 | case MSR_KVM_PV_EOI_EN: |
2037 | if (kvm_lapic_enable_pv_eoi(vcpu, data)) | |
2038 | return 1; | |
2039 | break; | |
c9aaa895 | 2040 | |
890ca9ae HY |
2041 | case MSR_IA32_MCG_CTL: |
2042 | case MSR_IA32_MCG_STATUS: | |
2043 | case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1: | |
2044 | return set_msr_mce(vcpu, msr, data); | |
71db6023 AP |
2045 | |
2046 | /* Performance counters are not protected by a CPUID bit, | |
2047 | * so we should check all of them in the generic path for the sake of | |
2048 | * cross vendor migration. | |
2049 | * Writing a zero into the event select MSRs disables them, | |
2050 | * which we perfectly emulate ;-). Any other value should be at least | |
2051 | * reported, some guests depend on them. | |
2052 | */ | |
71db6023 AP |
2053 | case MSR_K7_EVNTSEL0: |
2054 | case MSR_K7_EVNTSEL1: | |
2055 | case MSR_K7_EVNTSEL2: | |
2056 | case MSR_K7_EVNTSEL3: | |
2057 | if (data != 0) | |
a737f256 CD |
2058 | vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: " |
2059 | "0x%x data 0x%llx\n", msr, data); | |
71db6023 AP |
2060 | break; |
2061 | /* at least RHEL 4 unconditionally writes to the perfctr registers, | |
2062 | * so we ignore writes to make it happy. | |
2063 | */ | |
71db6023 AP |
2064 | case MSR_K7_PERFCTR0: |
2065 | case MSR_K7_PERFCTR1: | |
2066 | case MSR_K7_PERFCTR2: | |
2067 | case MSR_K7_PERFCTR3: | |
a737f256 CD |
2068 | vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: " |
2069 | "0x%x data 0x%llx\n", msr, data); | |
71db6023 | 2070 | break; |
5753785f GN |
2071 | case MSR_P6_PERFCTR0: |
2072 | case MSR_P6_PERFCTR1: | |
2073 | pr = true; | |
2074 | case MSR_P6_EVNTSEL0: | |
2075 | case MSR_P6_EVNTSEL1: | |
2076 | if (kvm_pmu_msr(vcpu, msr)) | |
afd80d85 | 2077 | return kvm_pmu_set_msr(vcpu, msr_info); |
5753785f GN |
2078 | |
2079 | if (pr || data != 0) | |
a737f256 CD |
2080 | vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " |
2081 | "0x%x data 0x%llx\n", msr, data); | |
5753785f | 2082 | break; |
84e0cefa JS |
2083 | case MSR_K7_CLK_CTL: |
2084 | /* | |
2085 | * Ignore all writes to this no longer documented MSR. | |
2086 | * Writes are only relevant for old K7 processors, | |
2087 | * all pre-dating SVM, but a recommended workaround from | |
4a969980 | 2088 | * AMD for these chips. It is possible to specify the |
84e0cefa JS |
2089 | * affected processor models on the command line, hence |
2090 | * the need to ignore the workaround. | |
2091 | */ | |
2092 | break; | |
55cd8e5a GN |
2093 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
2094 | if (kvm_hv_msr_partition_wide(msr)) { | |
2095 | int r; | |
2096 | mutex_lock(&vcpu->kvm->lock); | |
2097 | r = set_msr_hyperv_pw(vcpu, msr, data); | |
2098 | mutex_unlock(&vcpu->kvm->lock); | |
2099 | return r; | |
2100 | } else | |
2101 | return set_msr_hyperv(vcpu, msr, data); | |
2102 | break; | |
91c9c3ed | 2103 | case MSR_IA32_BBL_CR_CTL3: |
2104 | /* Drop writes to this legacy MSR -- see rdmsr | |
2105 | * counterpart for further detail. | |
2106 | */ | |
a737f256 | 2107 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data); |
91c9c3ed | 2108 | break; |
2b036c6b BO |
2109 | case MSR_AMD64_OSVW_ID_LENGTH: |
2110 | if (!guest_cpuid_has_osvw(vcpu)) | |
2111 | return 1; | |
2112 | vcpu->arch.osvw.length = data; | |
2113 | break; | |
2114 | case MSR_AMD64_OSVW_STATUS: | |
2115 | if (!guest_cpuid_has_osvw(vcpu)) | |
2116 | return 1; | |
2117 | vcpu->arch.osvw.status = data; | |
2118 | break; | |
15c4a640 | 2119 | default: |
ffde22ac ES |
2120 | if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) |
2121 | return xen_hvm_config(vcpu, data); | |
f5132b01 | 2122 | if (kvm_pmu_msr(vcpu, msr)) |
afd80d85 | 2123 | return kvm_pmu_set_msr(vcpu, msr_info); |
ed85c068 | 2124 | if (!ignore_msrs) { |
a737f256 CD |
2125 | vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", |
2126 | msr, data); | |
ed85c068 AP |
2127 | return 1; |
2128 | } else { | |
a737f256 CD |
2129 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", |
2130 | msr, data); | |
ed85c068 AP |
2131 | break; |
2132 | } | |
15c4a640 CO |
2133 | } |
2134 | return 0; | |
2135 | } | |
2136 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
2137 | ||
2138 | ||
2139 | /* | |
2140 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
2141 | * Returns 0 on success, non-0 otherwise. | |
2142 | * Assumes vcpu_load() was already called. | |
2143 | */ | |
2144 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
2145 | { | |
2146 | return kvm_x86_ops->get_msr(vcpu, msr_index, pdata); | |
2147 | } | |
2148 | ||
9ba075a6 AK |
2149 | static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
2150 | { | |
0bed3b56 SY |
2151 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; |
2152 | ||
9ba075a6 AK |
2153 | if (!msr_mtrr_valid(msr)) |
2154 | return 1; | |
2155 | ||
0bed3b56 SY |
2156 | if (msr == MSR_MTRRdefType) |
2157 | *pdata = vcpu->arch.mtrr_state.def_type + | |
2158 | (vcpu->arch.mtrr_state.enabled << 10); | |
2159 | else if (msr == MSR_MTRRfix64K_00000) | |
2160 | *pdata = p[0]; | |
2161 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
2162 | *pdata = p[1 + msr - MSR_MTRRfix16K_80000]; | |
2163 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
2164 | *pdata = p[3 + msr - MSR_MTRRfix4K_C0000]; | |
2165 | else if (msr == MSR_IA32_CR_PAT) | |
2166 | *pdata = vcpu->arch.pat; | |
2167 | else { /* Variable MTRRs */ | |
2168 | int idx, is_mtrr_mask; | |
2169 | u64 *pt; | |
2170 | ||
2171 | idx = (msr - 0x200) / 2; | |
2172 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
2173 | if (!is_mtrr_mask) | |
2174 | pt = | |
2175 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
2176 | else | |
2177 | pt = | |
2178 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
2179 | *pdata = *pt; | |
2180 | } | |
2181 | ||
9ba075a6 AK |
2182 | return 0; |
2183 | } | |
2184 | ||
890ca9ae | 2185 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
15c4a640 CO |
2186 | { |
2187 | u64 data; | |
890ca9ae HY |
2188 | u64 mcg_cap = vcpu->arch.mcg_cap; |
2189 | unsigned bank_num = mcg_cap & 0xff; | |
15c4a640 CO |
2190 | |
2191 | switch (msr) { | |
15c4a640 CO |
2192 | case MSR_IA32_P5_MC_ADDR: |
2193 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
2194 | data = 0; |
2195 | break; | |
15c4a640 | 2196 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
2197 | data = vcpu->arch.mcg_cap; |
2198 | break; | |
c7ac679c | 2199 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
2200 | if (!(mcg_cap & MCG_CTL_P)) |
2201 | return 1; | |
2202 | data = vcpu->arch.mcg_ctl; | |
2203 | break; | |
2204 | case MSR_IA32_MCG_STATUS: | |
2205 | data = vcpu->arch.mcg_status; | |
2206 | break; | |
2207 | default: | |
2208 | if (msr >= MSR_IA32_MC0_CTL && | |
2209 | msr < MSR_IA32_MC0_CTL + 4 * bank_num) { | |
2210 | u32 offset = msr - MSR_IA32_MC0_CTL; | |
2211 | data = vcpu->arch.mce_banks[offset]; | |
2212 | break; | |
2213 | } | |
2214 | return 1; | |
2215 | } | |
2216 | *pdata = data; | |
2217 | return 0; | |
2218 | } | |
2219 | ||
55cd8e5a GN |
2220 | static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
2221 | { | |
2222 | u64 data = 0; | |
2223 | struct kvm *kvm = vcpu->kvm; | |
2224 | ||
2225 | switch (msr) { | |
2226 | case HV_X64_MSR_GUEST_OS_ID: | |
2227 | data = kvm->arch.hv_guest_os_id; | |
2228 | break; | |
2229 | case HV_X64_MSR_HYPERCALL: | |
2230 | data = kvm->arch.hv_hypercall; | |
2231 | break; | |
2232 | default: | |
a737f256 | 2233 | vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); |
55cd8e5a GN |
2234 | return 1; |
2235 | } | |
2236 | ||
2237 | *pdata = data; | |
2238 | return 0; | |
2239 | } | |
2240 | ||
2241 | static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) | |
2242 | { | |
2243 | u64 data = 0; | |
2244 | ||
2245 | switch (msr) { | |
2246 | case HV_X64_MSR_VP_INDEX: { | |
2247 | int r; | |
2248 | struct kvm_vcpu *v; | |
2249 | kvm_for_each_vcpu(r, v, vcpu->kvm) | |
2250 | if (v == vcpu) | |
2251 | data = r; | |
2252 | break; | |
2253 | } | |
10388a07 GN |
2254 | case HV_X64_MSR_EOI: |
2255 | return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata); | |
2256 | case HV_X64_MSR_ICR: | |
2257 | return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata); | |
2258 | case HV_X64_MSR_TPR: | |
2259 | return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata); | |
14fa67ee | 2260 | case HV_X64_MSR_APIC_ASSIST_PAGE: |
d1613ad5 MW |
2261 | data = vcpu->arch.hv_vapic; |
2262 | break; | |
55cd8e5a | 2263 | default: |
a737f256 | 2264 | vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); |
55cd8e5a GN |
2265 | return 1; |
2266 | } | |
2267 | *pdata = data; | |
2268 | return 0; | |
2269 | } | |
2270 | ||
890ca9ae HY |
2271 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
2272 | { | |
2273 | u64 data; | |
2274 | ||
2275 | switch (msr) { | |
890ca9ae | 2276 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 2277 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
2278 | case MSR_IA32_DEBUGCTLMSR: |
2279 | case MSR_IA32_LASTBRANCHFROMIP: | |
2280 | case MSR_IA32_LASTBRANCHTOIP: | |
2281 | case MSR_IA32_LASTINTFROMIP: | |
2282 | case MSR_IA32_LASTINTTOIP: | |
60af2ecd JSR |
2283 | case MSR_K8_SYSCFG: |
2284 | case MSR_K7_HWCR: | |
61a6bd67 | 2285 | case MSR_VM_HSAVE_PA: |
9e699624 | 2286 | case MSR_K7_EVNTSEL0: |
1f3ee616 | 2287 | case MSR_K7_PERFCTR0: |
1fdbd48c | 2288 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 2289 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 2290 | case MSR_FAM10H_MMIO_CONF_BASE: |
2e32b719 | 2291 | case MSR_AMD64_BU_CFG2: |
15c4a640 CO |
2292 | data = 0; |
2293 | break; | |
5753785f GN |
2294 | case MSR_P6_PERFCTR0: |
2295 | case MSR_P6_PERFCTR1: | |
2296 | case MSR_P6_EVNTSEL0: | |
2297 | case MSR_P6_EVNTSEL1: | |
2298 | if (kvm_pmu_msr(vcpu, msr)) | |
2299 | return kvm_pmu_get_msr(vcpu, msr, pdata); | |
2300 | data = 0; | |
2301 | break; | |
742bc670 MT |
2302 | case MSR_IA32_UCODE_REV: |
2303 | data = 0x100000000ULL; | |
2304 | break; | |
9ba075a6 AK |
2305 | case MSR_MTRRcap: |
2306 | data = 0x500 | KVM_NR_VAR_MTRR; | |
2307 | break; | |
2308 | case 0x200 ... 0x2ff: | |
2309 | return get_msr_mtrr(vcpu, msr, pdata); | |
15c4a640 CO |
2310 | case 0xcd: /* fsb frequency */ |
2311 | data = 3; | |
2312 | break; | |
7b914098 JS |
2313 | /* |
2314 | * MSR_EBC_FREQUENCY_ID | |
2315 | * Conservative value valid for even the basic CPU models. | |
2316 | * Models 0,1: 000 in bits 23:21 indicating a bus speed of | |
2317 | * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, | |
2318 | * and 266MHz for model 3, or 4. Set Core Clock | |
2319 | * Frequency to System Bus Frequency Ratio to 1 (bits | |
2320 | * 31:24) even though these are only valid for CPU | |
2321 | * models > 2, however guests may end up dividing or | |
2322 | * multiplying by zero otherwise. | |
2323 | */ | |
2324 | case MSR_EBC_FREQUENCY_ID: | |
2325 | data = 1 << 24; | |
2326 | break; | |
15c4a640 CO |
2327 | case MSR_IA32_APICBASE: |
2328 | data = kvm_get_apic_base(vcpu); | |
2329 | break; | |
0105d1a5 GN |
2330 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
2331 | return kvm_x2apic_msr_read(vcpu, msr, pdata); | |
2332 | break; | |
a3e06bbe LJ |
2333 | case MSR_IA32_TSCDEADLINE: |
2334 | data = kvm_get_lapic_tscdeadline_msr(vcpu); | |
2335 | break; | |
ba904635 WA |
2336 | case MSR_IA32_TSC_ADJUST: |
2337 | data = (u64)vcpu->arch.ia32_tsc_adjust_msr; | |
2338 | break; | |
15c4a640 | 2339 | case MSR_IA32_MISC_ENABLE: |
ad312c7c | 2340 | data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 2341 | break; |
847f0ad8 AG |
2342 | case MSR_IA32_PERF_STATUS: |
2343 | /* TSC increment by tick */ | |
2344 | data = 1000ULL; | |
2345 | /* CPU multiplier */ | |
2346 | data |= (((uint64_t)4ULL) << 40); | |
2347 | break; | |
15c4a640 | 2348 | case MSR_EFER: |
f6801dff | 2349 | data = vcpu->arch.efer; |
15c4a640 | 2350 | break; |
18068523 | 2351 | case MSR_KVM_WALL_CLOCK: |
11c6bffa | 2352 | case MSR_KVM_WALL_CLOCK_NEW: |
18068523 GOC |
2353 | data = vcpu->kvm->arch.wall_clock; |
2354 | break; | |
2355 | case MSR_KVM_SYSTEM_TIME: | |
11c6bffa | 2356 | case MSR_KVM_SYSTEM_TIME_NEW: |
18068523 GOC |
2357 | data = vcpu->arch.time; |
2358 | break; | |
344d9588 GN |
2359 | case MSR_KVM_ASYNC_PF_EN: |
2360 | data = vcpu->arch.apf.msr_val; | |
2361 | break; | |
c9aaa895 GC |
2362 | case MSR_KVM_STEAL_TIME: |
2363 | data = vcpu->arch.st.msr_val; | |
2364 | break; | |
1d92128f MT |
2365 | case MSR_KVM_PV_EOI_EN: |
2366 | data = vcpu->arch.pv_eoi.msr_val; | |
2367 | break; | |
890ca9ae HY |
2368 | case MSR_IA32_P5_MC_ADDR: |
2369 | case MSR_IA32_P5_MC_TYPE: | |
2370 | case MSR_IA32_MCG_CAP: | |
2371 | case MSR_IA32_MCG_CTL: | |
2372 | case MSR_IA32_MCG_STATUS: | |
2373 | case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1: | |
2374 | return get_msr_mce(vcpu, msr, pdata); | |
84e0cefa JS |
2375 | case MSR_K7_CLK_CTL: |
2376 | /* | |
2377 | * Provide expected ramp-up count for K7. All other | |
2378 | * are set to zero, indicating minimum divisors for | |
2379 | * every field. | |
2380 | * | |
2381 | * This prevents guest kernels on AMD host with CPU | |
2382 | * type 6, model 8 and higher from exploding due to | |
2383 | * the rdmsr failing. | |
2384 | */ | |
2385 | data = 0x20000000; | |
2386 | break; | |
55cd8e5a GN |
2387 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
2388 | if (kvm_hv_msr_partition_wide(msr)) { | |
2389 | int r; | |
2390 | mutex_lock(&vcpu->kvm->lock); | |
2391 | r = get_msr_hyperv_pw(vcpu, msr, pdata); | |
2392 | mutex_unlock(&vcpu->kvm->lock); | |
2393 | return r; | |
2394 | } else | |
2395 | return get_msr_hyperv(vcpu, msr, pdata); | |
2396 | break; | |
91c9c3ed | 2397 | case MSR_IA32_BBL_CR_CTL3: |
2398 | /* This legacy MSR exists but isn't fully documented in current | |
2399 | * silicon. It is however accessed by winxp in very narrow | |
2400 | * scenarios where it sets bit #19, itself documented as | |
2401 | * a "reserved" bit. Best effort attempt to source coherent | |
2402 | * read data here should the balance of the register be | |
2403 | * interpreted by the guest: | |
2404 | * | |
2405 | * L2 cache control register 3: 64GB range, 256KB size, | |
2406 | * enabled, latency 0x1, configured | |
2407 | */ | |
2408 | data = 0xbe702111; | |
2409 | break; | |
2b036c6b BO |
2410 | case MSR_AMD64_OSVW_ID_LENGTH: |
2411 | if (!guest_cpuid_has_osvw(vcpu)) | |
2412 | return 1; | |
2413 | data = vcpu->arch.osvw.length; | |
2414 | break; | |
2415 | case MSR_AMD64_OSVW_STATUS: | |
2416 | if (!guest_cpuid_has_osvw(vcpu)) | |
2417 | return 1; | |
2418 | data = vcpu->arch.osvw.status; | |
2419 | break; | |
15c4a640 | 2420 | default: |
f5132b01 GN |
2421 | if (kvm_pmu_msr(vcpu, msr)) |
2422 | return kvm_pmu_get_msr(vcpu, msr, pdata); | |
ed85c068 | 2423 | if (!ignore_msrs) { |
a737f256 | 2424 | vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr); |
ed85c068 AP |
2425 | return 1; |
2426 | } else { | |
a737f256 | 2427 | vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr); |
ed85c068 AP |
2428 | data = 0; |
2429 | } | |
2430 | break; | |
15c4a640 CO |
2431 | } |
2432 | *pdata = data; | |
2433 | return 0; | |
2434 | } | |
2435 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
2436 | ||
313a3dc7 CO |
2437 | /* |
2438 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
2439 | * | |
2440 | * @return number of msrs set successfully. | |
2441 | */ | |
2442 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
2443 | struct kvm_msr_entry *entries, | |
2444 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
2445 | unsigned index, u64 *data)) | |
2446 | { | |
f656ce01 | 2447 | int i, idx; |
313a3dc7 | 2448 | |
f656ce01 | 2449 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
313a3dc7 CO |
2450 | for (i = 0; i < msrs->nmsrs; ++i) |
2451 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
2452 | break; | |
f656ce01 | 2453 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 2454 | |
313a3dc7 CO |
2455 | return i; |
2456 | } | |
2457 | ||
2458 | /* | |
2459 | * Read or write a bunch of msrs. Parameters are user addresses. | |
2460 | * | |
2461 | * @return number of msrs set successfully. | |
2462 | */ | |
2463 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
2464 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
2465 | unsigned index, u64 *data), | |
2466 | int writeback) | |
2467 | { | |
2468 | struct kvm_msrs msrs; | |
2469 | struct kvm_msr_entry *entries; | |
2470 | int r, n; | |
2471 | unsigned size; | |
2472 | ||
2473 | r = -EFAULT; | |
2474 | if (copy_from_user(&msrs, user_msrs, sizeof msrs)) | |
2475 | goto out; | |
2476 | ||
2477 | r = -E2BIG; | |
2478 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
2479 | goto out; | |
2480 | ||
313a3dc7 | 2481 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; |
ff5c2c03 SL |
2482 | entries = memdup_user(user_msrs->entries, size); |
2483 | if (IS_ERR(entries)) { | |
2484 | r = PTR_ERR(entries); | |
313a3dc7 | 2485 | goto out; |
ff5c2c03 | 2486 | } |
313a3dc7 CO |
2487 | |
2488 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
2489 | if (r < 0) | |
2490 | goto out_free; | |
2491 | ||
2492 | r = -EFAULT; | |
2493 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
2494 | goto out_free; | |
2495 | ||
2496 | r = n; | |
2497 | ||
2498 | out_free: | |
7a73c028 | 2499 | kfree(entries); |
313a3dc7 CO |
2500 | out: |
2501 | return r; | |
2502 | } | |
2503 | ||
018d00d2 ZX |
2504 | int kvm_dev_ioctl_check_extension(long ext) |
2505 | { | |
2506 | int r; | |
2507 | ||
2508 | switch (ext) { | |
2509 | case KVM_CAP_IRQCHIP: | |
2510 | case KVM_CAP_HLT: | |
2511 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 2512 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 2513 | case KVM_CAP_EXT_CPUID: |
c8076604 | 2514 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 2515 | case KVM_CAP_PIT: |
a28e4f5a | 2516 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 2517 | case KVM_CAP_MP_STATE: |
ed848624 | 2518 | case KVM_CAP_SYNC_MMU: |
a355c85c | 2519 | case KVM_CAP_USER_NMI: |
52d939a0 | 2520 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 2521 | case KVM_CAP_IRQ_INJECT_STATUS: |
721eecbf | 2522 | case KVM_CAP_IRQFD: |
d34e6b17 | 2523 | case KVM_CAP_IOEVENTFD: |
c5ff41ce | 2524 | case KVM_CAP_PIT2: |
e9f42757 | 2525 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 2526 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
ffde22ac | 2527 | case KVM_CAP_XEN_HVM: |
afbcf7ab | 2528 | case KVM_CAP_ADJUST_CLOCK: |
3cfc3092 | 2529 | case KVM_CAP_VCPU_EVENTS: |
55cd8e5a | 2530 | case KVM_CAP_HYPERV: |
10388a07 | 2531 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 2532 | case KVM_CAP_HYPERV_SPIN: |
ab9f4ecb | 2533 | case KVM_CAP_PCI_SEGMENT: |
a1efbe77 | 2534 | case KVM_CAP_DEBUGREGS: |
d2be1651 | 2535 | case KVM_CAP_X86_ROBUST_SINGLESTEP: |
2d5b5a66 | 2536 | case KVM_CAP_XSAVE: |
344d9588 | 2537 | case KVM_CAP_ASYNC_PF: |
92a1f12d | 2538 | case KVM_CAP_GET_TSC_KHZ: |
1c0b28c2 | 2539 | case KVM_CAP_KVMCLOCK_CTRL: |
4d8b81ab | 2540 | case KVM_CAP_READONLY_MEM: |
2a5bab10 AW |
2541 | #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT |
2542 | case KVM_CAP_ASSIGN_DEV_IRQ: | |
2543 | case KVM_CAP_PCI_2_3: | |
2544 | #endif | |
018d00d2 ZX |
2545 | r = 1; |
2546 | break; | |
542472b5 LV |
2547 | case KVM_CAP_COALESCED_MMIO: |
2548 | r = KVM_COALESCED_MMIO_PAGE_OFFSET; | |
2549 | break; | |
774ead3a AK |
2550 | case KVM_CAP_VAPIC: |
2551 | r = !kvm_x86_ops->cpu_has_accelerated_tpr(); | |
2552 | break; | |
f725230a | 2553 | case KVM_CAP_NR_VCPUS: |
8c3ba334 SL |
2554 | r = KVM_SOFT_MAX_VCPUS; |
2555 | break; | |
2556 | case KVM_CAP_MAX_VCPUS: | |
f725230a AK |
2557 | r = KVM_MAX_VCPUS; |
2558 | break; | |
a988b910 | 2559 | case KVM_CAP_NR_MEMSLOTS: |
bbacc0c1 | 2560 | r = KVM_USER_MEM_SLOTS; |
a988b910 | 2561 | break; |
a68a6a72 MT |
2562 | case KVM_CAP_PV_MMU: /* obsolete */ |
2563 | r = 0; | |
2f333bcb | 2564 | break; |
4cee4b72 | 2565 | #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT |
62c476c7 | 2566 | case KVM_CAP_IOMMU: |
a1b60c1c | 2567 | r = iommu_present(&pci_bus_type); |
62c476c7 | 2568 | break; |
4cee4b72 | 2569 | #endif |
890ca9ae HY |
2570 | case KVM_CAP_MCE: |
2571 | r = KVM_MAX_MCE_BANKS; | |
2572 | break; | |
2d5b5a66 SY |
2573 | case KVM_CAP_XCRS: |
2574 | r = cpu_has_xsave; | |
2575 | break; | |
92a1f12d JR |
2576 | case KVM_CAP_TSC_CONTROL: |
2577 | r = kvm_has_tsc_control; | |
2578 | break; | |
4d25a066 JK |
2579 | case KVM_CAP_TSC_DEADLINE_TIMER: |
2580 | r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER); | |
2581 | break; | |
018d00d2 ZX |
2582 | default: |
2583 | r = 0; | |
2584 | break; | |
2585 | } | |
2586 | return r; | |
2587 | ||
2588 | } | |
2589 | ||
043405e1 CO |
2590 | long kvm_arch_dev_ioctl(struct file *filp, |
2591 | unsigned int ioctl, unsigned long arg) | |
2592 | { | |
2593 | void __user *argp = (void __user *)arg; | |
2594 | long r; | |
2595 | ||
2596 | switch (ioctl) { | |
2597 | case KVM_GET_MSR_INDEX_LIST: { | |
2598 | struct kvm_msr_list __user *user_msr_list = argp; | |
2599 | struct kvm_msr_list msr_list; | |
2600 | unsigned n; | |
2601 | ||
2602 | r = -EFAULT; | |
2603 | if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) | |
2604 | goto out; | |
2605 | n = msr_list.nmsrs; | |
2606 | msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs); | |
2607 | if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) | |
2608 | goto out; | |
2609 | r = -E2BIG; | |
e125e7b6 | 2610 | if (n < msr_list.nmsrs) |
043405e1 CO |
2611 | goto out; |
2612 | r = -EFAULT; | |
2613 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
2614 | num_msrs_to_save * sizeof(u32))) | |
2615 | goto out; | |
e125e7b6 | 2616 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 CO |
2617 | &emulated_msrs, |
2618 | ARRAY_SIZE(emulated_msrs) * sizeof(u32))) | |
2619 | goto out; | |
2620 | r = 0; | |
2621 | break; | |
2622 | } | |
674eea0f AK |
2623 | case KVM_GET_SUPPORTED_CPUID: { |
2624 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
2625 | struct kvm_cpuid2 cpuid; | |
2626 | ||
2627 | r = -EFAULT; | |
2628 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2629 | goto out; | |
2630 | r = kvm_dev_ioctl_get_supported_cpuid(&cpuid, | |
19355475 | 2631 | cpuid_arg->entries); |
674eea0f AK |
2632 | if (r) |
2633 | goto out; | |
2634 | ||
2635 | r = -EFAULT; | |
2636 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
2637 | goto out; | |
2638 | r = 0; | |
2639 | break; | |
2640 | } | |
890ca9ae HY |
2641 | case KVM_X86_GET_MCE_CAP_SUPPORTED: { |
2642 | u64 mce_cap; | |
2643 | ||
2644 | mce_cap = KVM_MCE_CAP_SUPPORTED; | |
2645 | r = -EFAULT; | |
2646 | if (copy_to_user(argp, &mce_cap, sizeof mce_cap)) | |
2647 | goto out; | |
2648 | r = 0; | |
2649 | break; | |
2650 | } | |
043405e1 CO |
2651 | default: |
2652 | r = -EINVAL; | |
2653 | } | |
2654 | out: | |
2655 | return r; | |
2656 | } | |
2657 | ||
f5f48ee1 SY |
2658 | static void wbinvd_ipi(void *garbage) |
2659 | { | |
2660 | wbinvd(); | |
2661 | } | |
2662 | ||
2663 | static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
2664 | { | |
2665 | return vcpu->kvm->arch.iommu_domain && | |
2666 | !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY); | |
2667 | } | |
2668 | ||
313a3dc7 CO |
2669 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
2670 | { | |
f5f48ee1 SY |
2671 | /* Address WBINVD may be executed by guest */ |
2672 | if (need_emulate_wbinvd(vcpu)) { | |
2673 | if (kvm_x86_ops->has_wbinvd_exit()) | |
2674 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
2675 | else if (vcpu->cpu != -1 && vcpu->cpu != cpu) | |
2676 | smp_call_function_single(vcpu->cpu, | |
2677 | wbinvd_ipi, NULL, 1); | |
2678 | } | |
2679 | ||
313a3dc7 | 2680 | kvm_x86_ops->vcpu_load(vcpu, cpu); |
8f6055cb | 2681 | |
0dd6a6ed ZA |
2682 | /* Apply any externally detected TSC adjustments (due to suspend) */ |
2683 | if (unlikely(vcpu->arch.tsc_offset_adjustment)) { | |
2684 | adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); | |
2685 | vcpu->arch.tsc_offset_adjustment = 0; | |
2686 | set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests); | |
2687 | } | |
8f6055cb | 2688 | |
48434c20 | 2689 | if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) { |
6f526ec5 ZA |
2690 | s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : |
2691 | native_read_tsc() - vcpu->arch.last_host_tsc; | |
e48672fa ZA |
2692 | if (tsc_delta < 0) |
2693 | mark_tsc_unstable("KVM discovered backwards TSC"); | |
c285545f | 2694 | if (check_tsc_unstable()) { |
b183aa58 ZA |
2695 | u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu, |
2696 | vcpu->arch.last_guest_tsc); | |
2697 | kvm_x86_ops->write_tsc_offset(vcpu, offset); | |
c285545f | 2698 | vcpu->arch.tsc_catchup = 1; |
c285545f | 2699 | } |
d98d07ca MT |
2700 | /* |
2701 | * On a host with synchronized TSC, there is no need to update | |
2702 | * kvmclock on vcpu->cpu migration | |
2703 | */ | |
2704 | if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) | |
2705 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
c285545f ZA |
2706 | if (vcpu->cpu != cpu) |
2707 | kvm_migrate_timers(vcpu); | |
e48672fa | 2708 | vcpu->cpu = cpu; |
6b7d7e76 | 2709 | } |
c9aaa895 GC |
2710 | |
2711 | accumulate_steal_time(vcpu); | |
2712 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); | |
313a3dc7 CO |
2713 | } |
2714 | ||
2715 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) | |
2716 | { | |
02daab21 | 2717 | kvm_x86_ops->vcpu_put(vcpu); |
1c11e713 | 2718 | kvm_put_guest_fpu(vcpu); |
6f526ec5 | 2719 | vcpu->arch.last_host_tsc = native_read_tsc(); |
313a3dc7 CO |
2720 | } |
2721 | ||
313a3dc7 CO |
2722 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
2723 | struct kvm_lapic_state *s) | |
2724 | { | |
5a71785d | 2725 | kvm_x86_ops->sync_pir_to_irr(vcpu); |
ad312c7c | 2726 | memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s); |
313a3dc7 CO |
2727 | |
2728 | return 0; | |
2729 | } | |
2730 | ||
2731 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
2732 | struct kvm_lapic_state *s) | |
2733 | { | |
64eb0620 | 2734 | kvm_apic_post_state_restore(vcpu, s); |
cb142eb7 | 2735 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
2736 | |
2737 | return 0; | |
2738 | } | |
2739 | ||
f77bc6a4 ZX |
2740 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
2741 | struct kvm_interrupt *irq) | |
2742 | { | |
02cdb50f | 2743 | if (irq->irq >= KVM_NR_INTERRUPTS) |
f77bc6a4 ZX |
2744 | return -EINVAL; |
2745 | if (irqchip_in_kernel(vcpu->kvm)) | |
2746 | return -ENXIO; | |
f77bc6a4 | 2747 | |
66fd3f7f | 2748 | kvm_queue_interrupt(vcpu, irq->irq, false); |
3842d135 | 2749 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f77bc6a4 | 2750 | |
f77bc6a4 ZX |
2751 | return 0; |
2752 | } | |
2753 | ||
c4abb7c9 JK |
2754 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
2755 | { | |
c4abb7c9 | 2756 | kvm_inject_nmi(vcpu); |
c4abb7c9 JK |
2757 | |
2758 | return 0; | |
2759 | } | |
2760 | ||
b209749f AK |
2761 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
2762 | struct kvm_tpr_access_ctl *tac) | |
2763 | { | |
2764 | if (tac->flags) | |
2765 | return -EINVAL; | |
2766 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
2767 | return 0; | |
2768 | } | |
2769 | ||
890ca9ae HY |
2770 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
2771 | u64 mcg_cap) | |
2772 | { | |
2773 | int r; | |
2774 | unsigned bank_num = mcg_cap & 0xff, bank; | |
2775 | ||
2776 | r = -EINVAL; | |
a9e38c3e | 2777 | if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) |
890ca9ae HY |
2778 | goto out; |
2779 | if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000)) | |
2780 | goto out; | |
2781 | r = 0; | |
2782 | vcpu->arch.mcg_cap = mcg_cap; | |
2783 | /* Init IA32_MCG_CTL to all 1s */ | |
2784 | if (mcg_cap & MCG_CTL_P) | |
2785 | vcpu->arch.mcg_ctl = ~(u64)0; | |
2786 | /* Init IA32_MCi_CTL to all 1s */ | |
2787 | for (bank = 0; bank < bank_num; bank++) | |
2788 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
2789 | out: | |
2790 | return r; | |
2791 | } | |
2792 | ||
2793 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
2794 | struct kvm_x86_mce *mce) | |
2795 | { | |
2796 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
2797 | unsigned bank_num = mcg_cap & 0xff; | |
2798 | u64 *banks = vcpu->arch.mce_banks; | |
2799 | ||
2800 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
2801 | return -EINVAL; | |
2802 | /* | |
2803 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
2804 | * reporting is disabled | |
2805 | */ | |
2806 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
2807 | vcpu->arch.mcg_ctl != ~(u64)0) | |
2808 | return 0; | |
2809 | banks += 4 * mce->bank; | |
2810 | /* | |
2811 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
2812 | * reporting is disabled for the bank | |
2813 | */ | |
2814 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
2815 | return 0; | |
2816 | if (mce->status & MCI_STATUS_UC) { | |
2817 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
fc78f519 | 2818 | !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { |
a8eeb04a | 2819 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
890ca9ae HY |
2820 | return 0; |
2821 | } | |
2822 | if (banks[1] & MCI_STATUS_VAL) | |
2823 | mce->status |= MCI_STATUS_OVER; | |
2824 | banks[2] = mce->addr; | |
2825 | banks[3] = mce->misc; | |
2826 | vcpu->arch.mcg_status = mce->mcg_status; | |
2827 | banks[1] = mce->status; | |
2828 | kvm_queue_exception(vcpu, MC_VECTOR); | |
2829 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
2830 | || !(banks[1] & MCI_STATUS_UC)) { | |
2831 | if (banks[1] & MCI_STATUS_VAL) | |
2832 | mce->status |= MCI_STATUS_OVER; | |
2833 | banks[2] = mce->addr; | |
2834 | banks[3] = mce->misc; | |
2835 | banks[1] = mce->status; | |
2836 | } else | |
2837 | banks[1] |= MCI_STATUS_OVER; | |
2838 | return 0; | |
2839 | } | |
2840 | ||
3cfc3092 JK |
2841 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
2842 | struct kvm_vcpu_events *events) | |
2843 | { | |
7460fb4a | 2844 | process_nmi(vcpu); |
03b82a30 JK |
2845 | events->exception.injected = |
2846 | vcpu->arch.exception.pending && | |
2847 | !kvm_exception_is_soft(vcpu->arch.exception.nr); | |
3cfc3092 JK |
2848 | events->exception.nr = vcpu->arch.exception.nr; |
2849 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
97e69aa6 | 2850 | events->exception.pad = 0; |
3cfc3092 JK |
2851 | events->exception.error_code = vcpu->arch.exception.error_code; |
2852 | ||
03b82a30 JK |
2853 | events->interrupt.injected = |
2854 | vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; | |
3cfc3092 | 2855 | events->interrupt.nr = vcpu->arch.interrupt.nr; |
03b82a30 | 2856 | events->interrupt.soft = 0; |
48005f64 JK |
2857 | events->interrupt.shadow = |
2858 | kvm_x86_ops->get_interrupt_shadow(vcpu, | |
2859 | KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI); | |
3cfc3092 JK |
2860 | |
2861 | events->nmi.injected = vcpu->arch.nmi_injected; | |
7460fb4a | 2862 | events->nmi.pending = vcpu->arch.nmi_pending != 0; |
3cfc3092 | 2863 | events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); |
97e69aa6 | 2864 | events->nmi.pad = 0; |
3cfc3092 | 2865 | |
66450a21 | 2866 | events->sipi_vector = 0; /* never valid when reporting to user space */ |
3cfc3092 | 2867 | |
dab4b911 | 2868 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 | 2869 | | KVM_VCPUEVENT_VALID_SHADOW); |
97e69aa6 | 2870 | memset(&events->reserved, 0, sizeof(events->reserved)); |
3cfc3092 JK |
2871 | } |
2872 | ||
2873 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, | |
2874 | struct kvm_vcpu_events *events) | |
2875 | { | |
dab4b911 | 2876 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 JK |
2877 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
2878 | | KVM_VCPUEVENT_VALID_SHADOW)) | |
3cfc3092 JK |
2879 | return -EINVAL; |
2880 | ||
7460fb4a | 2881 | process_nmi(vcpu); |
3cfc3092 JK |
2882 | vcpu->arch.exception.pending = events->exception.injected; |
2883 | vcpu->arch.exception.nr = events->exception.nr; | |
2884 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
2885 | vcpu->arch.exception.error_code = events->exception.error_code; | |
2886 | ||
2887 | vcpu->arch.interrupt.pending = events->interrupt.injected; | |
2888 | vcpu->arch.interrupt.nr = events->interrupt.nr; | |
2889 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
48005f64 JK |
2890 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) |
2891 | kvm_x86_ops->set_interrupt_shadow(vcpu, | |
2892 | events->interrupt.shadow); | |
3cfc3092 JK |
2893 | |
2894 | vcpu->arch.nmi_injected = events->nmi.injected; | |
dab4b911 JK |
2895 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) |
2896 | vcpu->arch.nmi_pending = events->nmi.pending; | |
3cfc3092 JK |
2897 | kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); |
2898 | ||
66450a21 JK |
2899 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && |
2900 | kvm_vcpu_has_lapic(vcpu)) | |
2901 | vcpu->arch.apic->sipi_vector = events->sipi_vector; | |
3cfc3092 | 2902 | |
3842d135 AK |
2903 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
2904 | ||
3cfc3092 JK |
2905 | return 0; |
2906 | } | |
2907 | ||
a1efbe77 JK |
2908 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, |
2909 | struct kvm_debugregs *dbgregs) | |
2910 | { | |
a1efbe77 JK |
2911 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); |
2912 | dbgregs->dr6 = vcpu->arch.dr6; | |
2913 | dbgregs->dr7 = vcpu->arch.dr7; | |
2914 | dbgregs->flags = 0; | |
97e69aa6 | 2915 | memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); |
a1efbe77 JK |
2916 | } |
2917 | ||
2918 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
2919 | struct kvm_debugregs *dbgregs) | |
2920 | { | |
2921 | if (dbgregs->flags) | |
2922 | return -EINVAL; | |
2923 | ||
a1efbe77 JK |
2924 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); |
2925 | vcpu->arch.dr6 = dbgregs->dr6; | |
2926 | vcpu->arch.dr7 = dbgregs->dr7; | |
2927 | ||
a1efbe77 JK |
2928 | return 0; |
2929 | } | |
2930 | ||
2d5b5a66 SY |
2931 | static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, |
2932 | struct kvm_xsave *guest_xsave) | |
2933 | { | |
2934 | if (cpu_has_xsave) | |
2935 | memcpy(guest_xsave->region, | |
2936 | &vcpu->arch.guest_fpu.state->xsave, | |
f45755b8 | 2937 | xstate_size); |
2d5b5a66 SY |
2938 | else { |
2939 | memcpy(guest_xsave->region, | |
2940 | &vcpu->arch.guest_fpu.state->fxsave, | |
2941 | sizeof(struct i387_fxsave_struct)); | |
2942 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = | |
2943 | XSTATE_FPSSE; | |
2944 | } | |
2945 | } | |
2946 | ||
2947 | static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, | |
2948 | struct kvm_xsave *guest_xsave) | |
2949 | { | |
2950 | u64 xstate_bv = | |
2951 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; | |
2952 | ||
2953 | if (cpu_has_xsave) | |
2954 | memcpy(&vcpu->arch.guest_fpu.state->xsave, | |
f45755b8 | 2955 | guest_xsave->region, xstate_size); |
2d5b5a66 SY |
2956 | else { |
2957 | if (xstate_bv & ~XSTATE_FPSSE) | |
2958 | return -EINVAL; | |
2959 | memcpy(&vcpu->arch.guest_fpu.state->fxsave, | |
2960 | guest_xsave->region, sizeof(struct i387_fxsave_struct)); | |
2961 | } | |
2962 | return 0; | |
2963 | } | |
2964 | ||
2965 | static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, | |
2966 | struct kvm_xcrs *guest_xcrs) | |
2967 | { | |
2968 | if (!cpu_has_xsave) { | |
2969 | guest_xcrs->nr_xcrs = 0; | |
2970 | return; | |
2971 | } | |
2972 | ||
2973 | guest_xcrs->nr_xcrs = 1; | |
2974 | guest_xcrs->flags = 0; | |
2975 | guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; | |
2976 | guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; | |
2977 | } | |
2978 | ||
2979 | static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, | |
2980 | struct kvm_xcrs *guest_xcrs) | |
2981 | { | |
2982 | int i, r = 0; | |
2983 | ||
2984 | if (!cpu_has_xsave) | |
2985 | return -EINVAL; | |
2986 | ||
2987 | if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) | |
2988 | return -EINVAL; | |
2989 | ||
2990 | for (i = 0; i < guest_xcrs->nr_xcrs; i++) | |
2991 | /* Only support XCR0 currently */ | |
2992 | if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) { | |
2993 | r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, | |
2994 | guest_xcrs->xcrs[0].value); | |
2995 | break; | |
2996 | } | |
2997 | if (r) | |
2998 | r = -EINVAL; | |
2999 | return r; | |
3000 | } | |
3001 | ||
1c0b28c2 EM |
3002 | /* |
3003 | * kvm_set_guest_paused() indicates to the guest kernel that it has been | |
3004 | * stopped by the hypervisor. This function will be called from the host only. | |
3005 | * EINVAL is returned when the host attempts to set the flag for a guest that | |
3006 | * does not support pv clocks. | |
3007 | */ | |
3008 | static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) | |
3009 | { | |
0b79459b | 3010 | if (!vcpu->arch.pv_time_enabled) |
1c0b28c2 | 3011 | return -EINVAL; |
51d59c6b | 3012 | vcpu->arch.pvclock_set_guest_stopped_request = true; |
1c0b28c2 EM |
3013 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
3014 | return 0; | |
3015 | } | |
3016 | ||
313a3dc7 CO |
3017 | long kvm_arch_vcpu_ioctl(struct file *filp, |
3018 | unsigned int ioctl, unsigned long arg) | |
3019 | { | |
3020 | struct kvm_vcpu *vcpu = filp->private_data; | |
3021 | void __user *argp = (void __user *)arg; | |
3022 | int r; | |
d1ac91d8 AK |
3023 | union { |
3024 | struct kvm_lapic_state *lapic; | |
3025 | struct kvm_xsave *xsave; | |
3026 | struct kvm_xcrs *xcrs; | |
3027 | void *buffer; | |
3028 | } u; | |
3029 | ||
3030 | u.buffer = NULL; | |
313a3dc7 CO |
3031 | switch (ioctl) { |
3032 | case KVM_GET_LAPIC: { | |
2204ae3c MT |
3033 | r = -EINVAL; |
3034 | if (!vcpu->arch.apic) | |
3035 | goto out; | |
d1ac91d8 | 3036 | u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); |
313a3dc7 | 3037 | |
b772ff36 | 3038 | r = -ENOMEM; |
d1ac91d8 | 3039 | if (!u.lapic) |
b772ff36 | 3040 | goto out; |
d1ac91d8 | 3041 | r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); |
313a3dc7 CO |
3042 | if (r) |
3043 | goto out; | |
3044 | r = -EFAULT; | |
d1ac91d8 | 3045 | if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
3046 | goto out; |
3047 | r = 0; | |
3048 | break; | |
3049 | } | |
3050 | case KVM_SET_LAPIC: { | |
2204ae3c MT |
3051 | r = -EINVAL; |
3052 | if (!vcpu->arch.apic) | |
3053 | goto out; | |
ff5c2c03 | 3054 | u.lapic = memdup_user(argp, sizeof(*u.lapic)); |
18595411 GC |
3055 | if (IS_ERR(u.lapic)) |
3056 | return PTR_ERR(u.lapic); | |
ff5c2c03 | 3057 | |
d1ac91d8 | 3058 | r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); |
313a3dc7 CO |
3059 | break; |
3060 | } | |
f77bc6a4 ZX |
3061 | case KVM_INTERRUPT: { |
3062 | struct kvm_interrupt irq; | |
3063 | ||
3064 | r = -EFAULT; | |
3065 | if (copy_from_user(&irq, argp, sizeof irq)) | |
3066 | goto out; | |
3067 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
f77bc6a4 ZX |
3068 | break; |
3069 | } | |
c4abb7c9 JK |
3070 | case KVM_NMI: { |
3071 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
c4abb7c9 JK |
3072 | break; |
3073 | } | |
313a3dc7 CO |
3074 | case KVM_SET_CPUID: { |
3075 | struct kvm_cpuid __user *cpuid_arg = argp; | |
3076 | struct kvm_cpuid cpuid; | |
3077 | ||
3078 | r = -EFAULT; | |
3079 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
3080 | goto out; | |
3081 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
313a3dc7 CO |
3082 | break; |
3083 | } | |
07716717 DK |
3084 | case KVM_SET_CPUID2: { |
3085 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
3086 | struct kvm_cpuid2 cpuid; | |
3087 | ||
3088 | r = -EFAULT; | |
3089 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
3090 | goto out; | |
3091 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 3092 | cpuid_arg->entries); |
07716717 DK |
3093 | break; |
3094 | } | |
3095 | case KVM_GET_CPUID2: { | |
3096 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
3097 | struct kvm_cpuid2 cpuid; | |
3098 | ||
3099 | r = -EFAULT; | |
3100 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
3101 | goto out; | |
3102 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 3103 | cpuid_arg->entries); |
07716717 DK |
3104 | if (r) |
3105 | goto out; | |
3106 | r = -EFAULT; | |
3107 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
3108 | goto out; | |
3109 | r = 0; | |
3110 | break; | |
3111 | } | |
313a3dc7 CO |
3112 | case KVM_GET_MSRS: |
3113 | r = msr_io(vcpu, argp, kvm_get_msr, 1); | |
3114 | break; | |
3115 | case KVM_SET_MSRS: | |
3116 | r = msr_io(vcpu, argp, do_set_msr, 0); | |
3117 | break; | |
b209749f AK |
3118 | case KVM_TPR_ACCESS_REPORTING: { |
3119 | struct kvm_tpr_access_ctl tac; | |
3120 | ||
3121 | r = -EFAULT; | |
3122 | if (copy_from_user(&tac, argp, sizeof tac)) | |
3123 | goto out; | |
3124 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
3125 | if (r) | |
3126 | goto out; | |
3127 | r = -EFAULT; | |
3128 | if (copy_to_user(argp, &tac, sizeof tac)) | |
3129 | goto out; | |
3130 | r = 0; | |
3131 | break; | |
3132 | }; | |
b93463aa AK |
3133 | case KVM_SET_VAPIC_ADDR: { |
3134 | struct kvm_vapic_addr va; | |
3135 | ||
3136 | r = -EINVAL; | |
3137 | if (!irqchip_in_kernel(vcpu->kvm)) | |
3138 | goto out; | |
3139 | r = -EFAULT; | |
3140 | if (copy_from_user(&va, argp, sizeof va)) | |
3141 | goto out; | |
3142 | r = 0; | |
3143 | kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); | |
3144 | break; | |
3145 | } | |
890ca9ae HY |
3146 | case KVM_X86_SETUP_MCE: { |
3147 | u64 mcg_cap; | |
3148 | ||
3149 | r = -EFAULT; | |
3150 | if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) | |
3151 | goto out; | |
3152 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
3153 | break; | |
3154 | } | |
3155 | case KVM_X86_SET_MCE: { | |
3156 | struct kvm_x86_mce mce; | |
3157 | ||
3158 | r = -EFAULT; | |
3159 | if (copy_from_user(&mce, argp, sizeof mce)) | |
3160 | goto out; | |
3161 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
3162 | break; | |
3163 | } | |
3cfc3092 JK |
3164 | case KVM_GET_VCPU_EVENTS: { |
3165 | struct kvm_vcpu_events events; | |
3166 | ||
3167 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
3168 | ||
3169 | r = -EFAULT; | |
3170 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
3171 | break; | |
3172 | r = 0; | |
3173 | break; | |
3174 | } | |
3175 | case KVM_SET_VCPU_EVENTS: { | |
3176 | struct kvm_vcpu_events events; | |
3177 | ||
3178 | r = -EFAULT; | |
3179 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
3180 | break; | |
3181 | ||
3182 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
3183 | break; | |
3184 | } | |
a1efbe77 JK |
3185 | case KVM_GET_DEBUGREGS: { |
3186 | struct kvm_debugregs dbgregs; | |
3187 | ||
3188 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
3189 | ||
3190 | r = -EFAULT; | |
3191 | if (copy_to_user(argp, &dbgregs, | |
3192 | sizeof(struct kvm_debugregs))) | |
3193 | break; | |
3194 | r = 0; | |
3195 | break; | |
3196 | } | |
3197 | case KVM_SET_DEBUGREGS: { | |
3198 | struct kvm_debugregs dbgregs; | |
3199 | ||
3200 | r = -EFAULT; | |
3201 | if (copy_from_user(&dbgregs, argp, | |
3202 | sizeof(struct kvm_debugregs))) | |
3203 | break; | |
3204 | ||
3205 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
3206 | break; | |
3207 | } | |
2d5b5a66 | 3208 | case KVM_GET_XSAVE: { |
d1ac91d8 | 3209 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); |
2d5b5a66 | 3210 | r = -ENOMEM; |
d1ac91d8 | 3211 | if (!u.xsave) |
2d5b5a66 SY |
3212 | break; |
3213 | ||
d1ac91d8 | 3214 | kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
3215 | |
3216 | r = -EFAULT; | |
d1ac91d8 | 3217 | if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
3218 | break; |
3219 | r = 0; | |
3220 | break; | |
3221 | } | |
3222 | case KVM_SET_XSAVE: { | |
ff5c2c03 | 3223 | u.xsave = memdup_user(argp, sizeof(*u.xsave)); |
18595411 GC |
3224 | if (IS_ERR(u.xsave)) |
3225 | return PTR_ERR(u.xsave); | |
2d5b5a66 | 3226 | |
d1ac91d8 | 3227 | r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
3228 | break; |
3229 | } | |
3230 | case KVM_GET_XCRS: { | |
d1ac91d8 | 3231 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); |
2d5b5a66 | 3232 | r = -ENOMEM; |
d1ac91d8 | 3233 | if (!u.xcrs) |
2d5b5a66 SY |
3234 | break; |
3235 | ||
d1ac91d8 | 3236 | kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
3237 | |
3238 | r = -EFAULT; | |
d1ac91d8 | 3239 | if (copy_to_user(argp, u.xcrs, |
2d5b5a66 SY |
3240 | sizeof(struct kvm_xcrs))) |
3241 | break; | |
3242 | r = 0; | |
3243 | break; | |
3244 | } | |
3245 | case KVM_SET_XCRS: { | |
ff5c2c03 | 3246 | u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); |
18595411 GC |
3247 | if (IS_ERR(u.xcrs)) |
3248 | return PTR_ERR(u.xcrs); | |
2d5b5a66 | 3249 | |
d1ac91d8 | 3250 | r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
3251 | break; |
3252 | } | |
92a1f12d JR |
3253 | case KVM_SET_TSC_KHZ: { |
3254 | u32 user_tsc_khz; | |
3255 | ||
3256 | r = -EINVAL; | |
92a1f12d JR |
3257 | user_tsc_khz = (u32)arg; |
3258 | ||
3259 | if (user_tsc_khz >= kvm_max_guest_tsc_khz) | |
3260 | goto out; | |
3261 | ||
cc578287 ZA |
3262 | if (user_tsc_khz == 0) |
3263 | user_tsc_khz = tsc_khz; | |
3264 | ||
3265 | kvm_set_tsc_khz(vcpu, user_tsc_khz); | |
92a1f12d JR |
3266 | |
3267 | r = 0; | |
3268 | goto out; | |
3269 | } | |
3270 | case KVM_GET_TSC_KHZ: { | |
cc578287 | 3271 | r = vcpu->arch.virtual_tsc_khz; |
92a1f12d JR |
3272 | goto out; |
3273 | } | |
1c0b28c2 EM |
3274 | case KVM_KVMCLOCK_CTRL: { |
3275 | r = kvm_set_guest_paused(vcpu); | |
3276 | goto out; | |
3277 | } | |
313a3dc7 CO |
3278 | default: |
3279 | r = -EINVAL; | |
3280 | } | |
3281 | out: | |
d1ac91d8 | 3282 | kfree(u.buffer); |
313a3dc7 CO |
3283 | return r; |
3284 | } | |
3285 | ||
5b1c1493 CO |
3286 | int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) |
3287 | { | |
3288 | return VM_FAULT_SIGBUS; | |
3289 | } | |
3290 | ||
1fe779f8 CO |
3291 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
3292 | { | |
3293 | int ret; | |
3294 | ||
3295 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
951179ce | 3296 | return -EINVAL; |
1fe779f8 CO |
3297 | ret = kvm_x86_ops->set_tss_addr(kvm, addr); |
3298 | return ret; | |
3299 | } | |
3300 | ||
b927a3ce SY |
3301 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
3302 | u64 ident_addr) | |
3303 | { | |
3304 | kvm->arch.ept_identity_map_addr = ident_addr; | |
3305 | return 0; | |
3306 | } | |
3307 | ||
1fe779f8 CO |
3308 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
3309 | u32 kvm_nr_mmu_pages) | |
3310 | { | |
3311 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
3312 | return -EINVAL; | |
3313 | ||
79fac95e | 3314 | mutex_lock(&kvm->slots_lock); |
1fe779f8 CO |
3315 | |
3316 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 3317 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 3318 | |
79fac95e | 3319 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
3320 | return 0; |
3321 | } | |
3322 | ||
3323 | static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) | |
3324 | { | |
39de71ec | 3325 | return kvm->arch.n_max_mmu_pages; |
1fe779f8 CO |
3326 | } |
3327 | ||
1fe779f8 CO |
3328 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) |
3329 | { | |
3330 | int r; | |
3331 | ||
3332 | r = 0; | |
3333 | switch (chip->chip_id) { | |
3334 | case KVM_IRQCHIP_PIC_MASTER: | |
3335 | memcpy(&chip->chip.pic, | |
3336 | &pic_irqchip(kvm)->pics[0], | |
3337 | sizeof(struct kvm_pic_state)); | |
3338 | break; | |
3339 | case KVM_IRQCHIP_PIC_SLAVE: | |
3340 | memcpy(&chip->chip.pic, | |
3341 | &pic_irqchip(kvm)->pics[1], | |
3342 | sizeof(struct kvm_pic_state)); | |
3343 | break; | |
3344 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 3345 | r = kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
3346 | break; |
3347 | default: | |
3348 | r = -EINVAL; | |
3349 | break; | |
3350 | } | |
3351 | return r; | |
3352 | } | |
3353 | ||
3354 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
3355 | { | |
3356 | int r; | |
3357 | ||
3358 | r = 0; | |
3359 | switch (chip->chip_id) { | |
3360 | case KVM_IRQCHIP_PIC_MASTER: | |
f4f51050 | 3361 | spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3362 | memcpy(&pic_irqchip(kvm)->pics[0], |
3363 | &chip->chip.pic, | |
3364 | sizeof(struct kvm_pic_state)); | |
f4f51050 | 3365 | spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3366 | break; |
3367 | case KVM_IRQCHIP_PIC_SLAVE: | |
f4f51050 | 3368 | spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3369 | memcpy(&pic_irqchip(kvm)->pics[1], |
3370 | &chip->chip.pic, | |
3371 | sizeof(struct kvm_pic_state)); | |
f4f51050 | 3372 | spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3373 | break; |
3374 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 3375 | r = kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
3376 | break; |
3377 | default: | |
3378 | r = -EINVAL; | |
3379 | break; | |
3380 | } | |
3381 | kvm_pic_update_irq(pic_irqchip(kvm)); | |
3382 | return r; | |
3383 | } | |
3384 | ||
e0f63cb9 SY |
3385 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
3386 | { | |
3387 | int r = 0; | |
3388 | ||
894a9c55 | 3389 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 | 3390 | memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state)); |
894a9c55 | 3391 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 SY |
3392 | return r; |
3393 | } | |
3394 | ||
3395 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
3396 | { | |
3397 | int r = 0; | |
3398 | ||
894a9c55 | 3399 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 | 3400 | memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state)); |
e9f42757 BK |
3401 | kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0); |
3402 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
3403 | return r; | |
3404 | } | |
3405 | ||
3406 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
3407 | { | |
3408 | int r = 0; | |
3409 | ||
3410 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
3411 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
3412 | sizeof(ps->channels)); | |
3413 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
3414 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
97e69aa6 | 3415 | memset(&ps->reserved, 0, sizeof(ps->reserved)); |
e9f42757 BK |
3416 | return r; |
3417 | } | |
3418 | ||
3419 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
3420 | { | |
3421 | int r = 0, start = 0; | |
3422 | u32 prev_legacy, cur_legacy; | |
3423 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
3424 | prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
3425 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
3426 | if (!prev_legacy && cur_legacy) | |
3427 | start = 1; | |
3428 | memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels, | |
3429 | sizeof(kvm->arch.vpit->pit_state.channels)); | |
3430 | kvm->arch.vpit->pit_state.flags = ps->flags; | |
3431 | kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start); | |
894a9c55 | 3432 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 SY |
3433 | return r; |
3434 | } | |
3435 | ||
52d939a0 MT |
3436 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
3437 | struct kvm_reinject_control *control) | |
3438 | { | |
3439 | if (!kvm->arch.vpit) | |
3440 | return -ENXIO; | |
894a9c55 | 3441 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
26ef1924 | 3442 | kvm->arch.vpit->pit_state.reinject = control->pit_reinject; |
894a9c55 | 3443 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
52d939a0 MT |
3444 | return 0; |
3445 | } | |
3446 | ||
95d4c16c | 3447 | /** |
60c34612 TY |
3448 | * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot |
3449 | * @kvm: kvm instance | |
3450 | * @log: slot id and address to which we copy the log | |
95d4c16c | 3451 | * |
60c34612 TY |
3452 | * We need to keep it in mind that VCPU threads can write to the bitmap |
3453 | * concurrently. So, to avoid losing data, we keep the following order for | |
3454 | * each bit: | |
95d4c16c | 3455 | * |
60c34612 TY |
3456 | * 1. Take a snapshot of the bit and clear it if needed. |
3457 | * 2. Write protect the corresponding page. | |
3458 | * 3. Flush TLB's if needed. | |
3459 | * 4. Copy the snapshot to the userspace. | |
95d4c16c | 3460 | * |
60c34612 TY |
3461 | * Between 2 and 3, the guest may write to the page using the remaining TLB |
3462 | * entry. This is not a problem because the page will be reported dirty at | |
3463 | * step 4 using the snapshot taken before and step 3 ensures that successive | |
3464 | * writes will be logged for the next call. | |
5bb064dc | 3465 | */ |
60c34612 | 3466 | int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) |
5bb064dc | 3467 | { |
7850ac54 | 3468 | int r; |
5bb064dc | 3469 | struct kvm_memory_slot *memslot; |
60c34612 TY |
3470 | unsigned long n, i; |
3471 | unsigned long *dirty_bitmap; | |
3472 | unsigned long *dirty_bitmap_buffer; | |
3473 | bool is_dirty = false; | |
5bb064dc | 3474 | |
79fac95e | 3475 | mutex_lock(&kvm->slots_lock); |
5bb064dc | 3476 | |
b050b015 | 3477 | r = -EINVAL; |
bbacc0c1 | 3478 | if (log->slot >= KVM_USER_MEM_SLOTS) |
b050b015 MT |
3479 | goto out; |
3480 | ||
28a37544 | 3481 | memslot = id_to_memslot(kvm->memslots, log->slot); |
60c34612 TY |
3482 | |
3483 | dirty_bitmap = memslot->dirty_bitmap; | |
b050b015 | 3484 | r = -ENOENT; |
60c34612 | 3485 | if (!dirty_bitmap) |
b050b015 MT |
3486 | goto out; |
3487 | ||
87bf6e7d | 3488 | n = kvm_dirty_bitmap_bytes(memslot); |
b050b015 | 3489 | |
60c34612 TY |
3490 | dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long); |
3491 | memset(dirty_bitmap_buffer, 0, n); | |
b050b015 | 3492 | |
60c34612 | 3493 | spin_lock(&kvm->mmu_lock); |
b050b015 | 3494 | |
60c34612 TY |
3495 | for (i = 0; i < n / sizeof(long); i++) { |
3496 | unsigned long mask; | |
3497 | gfn_t offset; | |
cdfca7b3 | 3498 | |
60c34612 TY |
3499 | if (!dirty_bitmap[i]) |
3500 | continue; | |
b050b015 | 3501 | |
60c34612 | 3502 | is_dirty = true; |
914ebccd | 3503 | |
60c34612 TY |
3504 | mask = xchg(&dirty_bitmap[i], 0); |
3505 | dirty_bitmap_buffer[i] = mask; | |
edde99ce | 3506 | |
60c34612 TY |
3507 | offset = i * BITS_PER_LONG; |
3508 | kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask); | |
5bb064dc | 3509 | } |
60c34612 TY |
3510 | if (is_dirty) |
3511 | kvm_flush_remote_tlbs(kvm); | |
3512 | ||
3513 | spin_unlock(&kvm->mmu_lock); | |
3514 | ||
3515 | r = -EFAULT; | |
3516 | if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n)) | |
3517 | goto out; | |
b050b015 | 3518 | |
5bb064dc ZX |
3519 | r = 0; |
3520 | out: | |
79fac95e | 3521 | mutex_unlock(&kvm->slots_lock); |
5bb064dc ZX |
3522 | return r; |
3523 | } | |
3524 | ||
aa2fbe6d YZ |
3525 | int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, |
3526 | bool line_status) | |
23d43cf9 CD |
3527 | { |
3528 | if (!irqchip_in_kernel(kvm)) | |
3529 | return -ENXIO; | |
3530 | ||
3531 | irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, | |
aa2fbe6d YZ |
3532 | irq_event->irq, irq_event->level, |
3533 | line_status); | |
23d43cf9 CD |
3534 | return 0; |
3535 | } | |
3536 | ||
1fe779f8 CO |
3537 | long kvm_arch_vm_ioctl(struct file *filp, |
3538 | unsigned int ioctl, unsigned long arg) | |
3539 | { | |
3540 | struct kvm *kvm = filp->private_data; | |
3541 | void __user *argp = (void __user *)arg; | |
367e1319 | 3542 | int r = -ENOTTY; |
f0d66275 DH |
3543 | /* |
3544 | * This union makes it completely explicit to gcc-3.x | |
3545 | * that these two variables' stack usage should be | |
3546 | * combined, not added together. | |
3547 | */ | |
3548 | union { | |
3549 | struct kvm_pit_state ps; | |
e9f42757 | 3550 | struct kvm_pit_state2 ps2; |
c5ff41ce | 3551 | struct kvm_pit_config pit_config; |
f0d66275 | 3552 | } u; |
1fe779f8 CO |
3553 | |
3554 | switch (ioctl) { | |
3555 | case KVM_SET_TSS_ADDR: | |
3556 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
1fe779f8 | 3557 | break; |
b927a3ce SY |
3558 | case KVM_SET_IDENTITY_MAP_ADDR: { |
3559 | u64 ident_addr; | |
3560 | ||
3561 | r = -EFAULT; | |
3562 | if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) | |
3563 | goto out; | |
3564 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); | |
b927a3ce SY |
3565 | break; |
3566 | } | |
1fe779f8 CO |
3567 | case KVM_SET_NR_MMU_PAGES: |
3568 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
1fe779f8 CO |
3569 | break; |
3570 | case KVM_GET_NR_MMU_PAGES: | |
3571 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
3572 | break; | |
3ddea128 MT |
3573 | case KVM_CREATE_IRQCHIP: { |
3574 | struct kvm_pic *vpic; | |
3575 | ||
3576 | mutex_lock(&kvm->lock); | |
3577 | r = -EEXIST; | |
3578 | if (kvm->arch.vpic) | |
3579 | goto create_irqchip_unlock; | |
3e515705 AK |
3580 | r = -EINVAL; |
3581 | if (atomic_read(&kvm->online_vcpus)) | |
3582 | goto create_irqchip_unlock; | |
1fe779f8 | 3583 | r = -ENOMEM; |
3ddea128 MT |
3584 | vpic = kvm_create_pic(kvm); |
3585 | if (vpic) { | |
1fe779f8 CO |
3586 | r = kvm_ioapic_init(kvm); |
3587 | if (r) { | |
175504cd | 3588 | mutex_lock(&kvm->slots_lock); |
72bb2fcd | 3589 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, |
743eeb0b SL |
3590 | &vpic->dev_master); |
3591 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, | |
3592 | &vpic->dev_slave); | |
3593 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, | |
3594 | &vpic->dev_eclr); | |
175504cd | 3595 | mutex_unlock(&kvm->slots_lock); |
3ddea128 MT |
3596 | kfree(vpic); |
3597 | goto create_irqchip_unlock; | |
1fe779f8 CO |
3598 | } |
3599 | } else | |
3ddea128 MT |
3600 | goto create_irqchip_unlock; |
3601 | smp_wmb(); | |
3602 | kvm->arch.vpic = vpic; | |
3603 | smp_wmb(); | |
399ec807 AK |
3604 | r = kvm_setup_default_irq_routing(kvm); |
3605 | if (r) { | |
175504cd | 3606 | mutex_lock(&kvm->slots_lock); |
3ddea128 | 3607 | mutex_lock(&kvm->irq_lock); |
72bb2fcd WY |
3608 | kvm_ioapic_destroy(kvm); |
3609 | kvm_destroy_pic(kvm); | |
3ddea128 | 3610 | mutex_unlock(&kvm->irq_lock); |
175504cd | 3611 | mutex_unlock(&kvm->slots_lock); |
399ec807 | 3612 | } |
3ddea128 MT |
3613 | create_irqchip_unlock: |
3614 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 3615 | break; |
3ddea128 | 3616 | } |
7837699f | 3617 | case KVM_CREATE_PIT: |
c5ff41ce JK |
3618 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
3619 | goto create_pit; | |
3620 | case KVM_CREATE_PIT2: | |
3621 | r = -EFAULT; | |
3622 | if (copy_from_user(&u.pit_config, argp, | |
3623 | sizeof(struct kvm_pit_config))) | |
3624 | goto out; | |
3625 | create_pit: | |
79fac95e | 3626 | mutex_lock(&kvm->slots_lock); |
269e05e4 AK |
3627 | r = -EEXIST; |
3628 | if (kvm->arch.vpit) | |
3629 | goto create_pit_unlock; | |
7837699f | 3630 | r = -ENOMEM; |
c5ff41ce | 3631 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
3632 | if (kvm->arch.vpit) |
3633 | r = 0; | |
269e05e4 | 3634 | create_pit_unlock: |
79fac95e | 3635 | mutex_unlock(&kvm->slots_lock); |
7837699f | 3636 | break; |
1fe779f8 CO |
3637 | case KVM_GET_IRQCHIP: { |
3638 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 3639 | struct kvm_irqchip *chip; |
1fe779f8 | 3640 | |
ff5c2c03 SL |
3641 | chip = memdup_user(argp, sizeof(*chip)); |
3642 | if (IS_ERR(chip)) { | |
3643 | r = PTR_ERR(chip); | |
1fe779f8 | 3644 | goto out; |
ff5c2c03 SL |
3645 | } |
3646 | ||
1fe779f8 CO |
3647 | r = -ENXIO; |
3648 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
3649 | goto get_irqchip_out; |
3650 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 3651 | if (r) |
f0d66275 | 3652 | goto get_irqchip_out; |
1fe779f8 | 3653 | r = -EFAULT; |
f0d66275 DH |
3654 | if (copy_to_user(argp, chip, sizeof *chip)) |
3655 | goto get_irqchip_out; | |
1fe779f8 | 3656 | r = 0; |
f0d66275 DH |
3657 | get_irqchip_out: |
3658 | kfree(chip); | |
1fe779f8 CO |
3659 | break; |
3660 | } | |
3661 | case KVM_SET_IRQCHIP: { | |
3662 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 3663 | struct kvm_irqchip *chip; |
1fe779f8 | 3664 | |
ff5c2c03 SL |
3665 | chip = memdup_user(argp, sizeof(*chip)); |
3666 | if (IS_ERR(chip)) { | |
3667 | r = PTR_ERR(chip); | |
1fe779f8 | 3668 | goto out; |
ff5c2c03 SL |
3669 | } |
3670 | ||
1fe779f8 CO |
3671 | r = -ENXIO; |
3672 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
3673 | goto set_irqchip_out; |
3674 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
1fe779f8 | 3675 | if (r) |
f0d66275 | 3676 | goto set_irqchip_out; |
1fe779f8 | 3677 | r = 0; |
f0d66275 DH |
3678 | set_irqchip_out: |
3679 | kfree(chip); | |
1fe779f8 CO |
3680 | break; |
3681 | } | |
e0f63cb9 | 3682 | case KVM_GET_PIT: { |
e0f63cb9 | 3683 | r = -EFAULT; |
f0d66275 | 3684 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
3685 | goto out; |
3686 | r = -ENXIO; | |
3687 | if (!kvm->arch.vpit) | |
3688 | goto out; | |
f0d66275 | 3689 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
3690 | if (r) |
3691 | goto out; | |
3692 | r = -EFAULT; | |
f0d66275 | 3693 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
3694 | goto out; |
3695 | r = 0; | |
3696 | break; | |
3697 | } | |
3698 | case KVM_SET_PIT: { | |
e0f63cb9 | 3699 | r = -EFAULT; |
f0d66275 | 3700 | if (copy_from_user(&u.ps, argp, sizeof u.ps)) |
e0f63cb9 SY |
3701 | goto out; |
3702 | r = -ENXIO; | |
3703 | if (!kvm->arch.vpit) | |
3704 | goto out; | |
f0d66275 | 3705 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
e0f63cb9 SY |
3706 | break; |
3707 | } | |
e9f42757 BK |
3708 | case KVM_GET_PIT2: { |
3709 | r = -ENXIO; | |
3710 | if (!kvm->arch.vpit) | |
3711 | goto out; | |
3712 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
3713 | if (r) | |
3714 | goto out; | |
3715 | r = -EFAULT; | |
3716 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
3717 | goto out; | |
3718 | r = 0; | |
3719 | break; | |
3720 | } | |
3721 | case KVM_SET_PIT2: { | |
3722 | r = -EFAULT; | |
3723 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
3724 | goto out; | |
3725 | r = -ENXIO; | |
3726 | if (!kvm->arch.vpit) | |
3727 | goto out; | |
3728 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); | |
e9f42757 BK |
3729 | break; |
3730 | } | |
52d939a0 MT |
3731 | case KVM_REINJECT_CONTROL: { |
3732 | struct kvm_reinject_control control; | |
3733 | r = -EFAULT; | |
3734 | if (copy_from_user(&control, argp, sizeof(control))) | |
3735 | goto out; | |
3736 | r = kvm_vm_ioctl_reinject(kvm, &control); | |
52d939a0 MT |
3737 | break; |
3738 | } | |
ffde22ac ES |
3739 | case KVM_XEN_HVM_CONFIG: { |
3740 | r = -EFAULT; | |
3741 | if (copy_from_user(&kvm->arch.xen_hvm_config, argp, | |
3742 | sizeof(struct kvm_xen_hvm_config))) | |
3743 | goto out; | |
3744 | r = -EINVAL; | |
3745 | if (kvm->arch.xen_hvm_config.flags) | |
3746 | goto out; | |
3747 | r = 0; | |
3748 | break; | |
3749 | } | |
afbcf7ab | 3750 | case KVM_SET_CLOCK: { |
afbcf7ab GC |
3751 | struct kvm_clock_data user_ns; |
3752 | u64 now_ns; | |
3753 | s64 delta; | |
3754 | ||
3755 | r = -EFAULT; | |
3756 | if (copy_from_user(&user_ns, argp, sizeof(user_ns))) | |
3757 | goto out; | |
3758 | ||
3759 | r = -EINVAL; | |
3760 | if (user_ns.flags) | |
3761 | goto out; | |
3762 | ||
3763 | r = 0; | |
395c6b0a | 3764 | local_irq_disable(); |
759379dd | 3765 | now_ns = get_kernel_ns(); |
afbcf7ab | 3766 | delta = user_ns.clock - now_ns; |
395c6b0a | 3767 | local_irq_enable(); |
afbcf7ab GC |
3768 | kvm->arch.kvmclock_offset = delta; |
3769 | break; | |
3770 | } | |
3771 | case KVM_GET_CLOCK: { | |
afbcf7ab GC |
3772 | struct kvm_clock_data user_ns; |
3773 | u64 now_ns; | |
3774 | ||
395c6b0a | 3775 | local_irq_disable(); |
759379dd | 3776 | now_ns = get_kernel_ns(); |
afbcf7ab | 3777 | user_ns.clock = kvm->arch.kvmclock_offset + now_ns; |
395c6b0a | 3778 | local_irq_enable(); |
afbcf7ab | 3779 | user_ns.flags = 0; |
97e69aa6 | 3780 | memset(&user_ns.pad, 0, sizeof(user_ns.pad)); |
afbcf7ab GC |
3781 | |
3782 | r = -EFAULT; | |
3783 | if (copy_to_user(argp, &user_ns, sizeof(user_ns))) | |
3784 | goto out; | |
3785 | r = 0; | |
3786 | break; | |
3787 | } | |
3788 | ||
1fe779f8 CO |
3789 | default: |
3790 | ; | |
3791 | } | |
3792 | out: | |
3793 | return r; | |
3794 | } | |
3795 | ||
a16b043c | 3796 | static void kvm_init_msr_list(void) |
043405e1 CO |
3797 | { |
3798 | u32 dummy[2]; | |
3799 | unsigned i, j; | |
3800 | ||
e3267cbb GC |
3801 | /* skip the first msrs in the list. KVM-specific */ |
3802 | for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) { | |
043405e1 CO |
3803 | if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) |
3804 | continue; | |
3805 | if (j < i) | |
3806 | msrs_to_save[j] = msrs_to_save[i]; | |
3807 | j++; | |
3808 | } | |
3809 | num_msrs_to_save = j; | |
3810 | } | |
3811 | ||
bda9020e MT |
3812 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
3813 | const void *v) | |
bbd9b64e | 3814 | { |
70252a10 AK |
3815 | int handled = 0; |
3816 | int n; | |
3817 | ||
3818 | do { | |
3819 | n = min(len, 8); | |
3820 | if (!(vcpu->arch.apic && | |
3821 | !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v)) | |
3822 | && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v)) | |
3823 | break; | |
3824 | handled += n; | |
3825 | addr += n; | |
3826 | len -= n; | |
3827 | v += n; | |
3828 | } while (len); | |
bbd9b64e | 3829 | |
70252a10 | 3830 | return handled; |
bbd9b64e CO |
3831 | } |
3832 | ||
bda9020e | 3833 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 3834 | { |
70252a10 AK |
3835 | int handled = 0; |
3836 | int n; | |
3837 | ||
3838 | do { | |
3839 | n = min(len, 8); | |
3840 | if (!(vcpu->arch.apic && | |
3841 | !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v)) | |
3842 | && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v)) | |
3843 | break; | |
3844 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v); | |
3845 | handled += n; | |
3846 | addr += n; | |
3847 | len -= n; | |
3848 | v += n; | |
3849 | } while (len); | |
bbd9b64e | 3850 | |
70252a10 | 3851 | return handled; |
bbd9b64e CO |
3852 | } |
3853 | ||
2dafc6c2 GN |
3854 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
3855 | struct kvm_segment *var, int seg) | |
3856 | { | |
3857 | kvm_x86_ops->set_segment(vcpu, var, seg); | |
3858 | } | |
3859 | ||
3860 | void kvm_get_segment(struct kvm_vcpu *vcpu, | |
3861 | struct kvm_segment *var, int seg) | |
3862 | { | |
3863 | kvm_x86_ops->get_segment(vcpu, var, seg); | |
3864 | } | |
3865 | ||
e459e322 | 3866 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access) |
02f59dc9 JR |
3867 | { |
3868 | gpa_t t_gpa; | |
ab9ae313 | 3869 | struct x86_exception exception; |
02f59dc9 JR |
3870 | |
3871 | BUG_ON(!mmu_is_nested(vcpu)); | |
3872 | ||
3873 | /* NPT walks are always user-walks */ | |
3874 | access |= PFERR_USER_MASK; | |
ab9ae313 | 3875 | t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception); |
02f59dc9 JR |
3876 | |
3877 | return t_gpa; | |
3878 | } | |
3879 | ||
ab9ae313 AK |
3880 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
3881 | struct x86_exception *exception) | |
1871c602 GN |
3882 | { |
3883 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
ab9ae313 | 3884 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
3885 | } |
3886 | ||
ab9ae313 AK |
3887 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, |
3888 | struct x86_exception *exception) | |
1871c602 GN |
3889 | { |
3890 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3891 | access |= PFERR_FETCH_MASK; | |
ab9ae313 | 3892 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
3893 | } |
3894 | ||
ab9ae313 AK |
3895 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, |
3896 | struct x86_exception *exception) | |
1871c602 GN |
3897 | { |
3898 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3899 | access |= PFERR_WRITE_MASK; | |
ab9ae313 | 3900 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
3901 | } |
3902 | ||
3903 | /* uses this to access any guest's mapped memory without checking CPL */ | |
ab9ae313 AK |
3904 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, |
3905 | struct x86_exception *exception) | |
1871c602 | 3906 | { |
ab9ae313 | 3907 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); |
1871c602 GN |
3908 | } |
3909 | ||
3910 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
3911 | struct kvm_vcpu *vcpu, u32 access, | |
bcc55cba | 3912 | struct x86_exception *exception) |
bbd9b64e CO |
3913 | { |
3914 | void *data = val; | |
10589a46 | 3915 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
3916 | |
3917 | while (bytes) { | |
14dfe855 | 3918 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, |
ab9ae313 | 3919 | exception); |
bbd9b64e | 3920 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 3921 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
3922 | int ret; |
3923 | ||
bcc55cba | 3924 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 3925 | return X86EMUL_PROPAGATE_FAULT; |
77c2002e | 3926 | ret = kvm_read_guest(vcpu->kvm, gpa, data, toread); |
10589a46 | 3927 | if (ret < 0) { |
c3cd7ffa | 3928 | r = X86EMUL_IO_NEEDED; |
10589a46 MT |
3929 | goto out; |
3930 | } | |
bbd9b64e | 3931 | |
77c2002e IE |
3932 | bytes -= toread; |
3933 | data += toread; | |
3934 | addr += toread; | |
bbd9b64e | 3935 | } |
10589a46 | 3936 | out: |
10589a46 | 3937 | return r; |
bbd9b64e | 3938 | } |
77c2002e | 3939 | |
1871c602 | 3940 | /* used for instruction fetching */ |
0f65dd70 AK |
3941 | static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, |
3942 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 3943 | struct x86_exception *exception) |
1871c602 | 3944 | { |
0f65dd70 | 3945 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
1871c602 | 3946 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
0f65dd70 | 3947 | |
1871c602 | 3948 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, |
bcc55cba AK |
3949 | access | PFERR_FETCH_MASK, |
3950 | exception); | |
1871c602 GN |
3951 | } |
3952 | ||
064aea77 | 3953 | int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt, |
0f65dd70 | 3954 | gva_t addr, void *val, unsigned int bytes, |
bcc55cba | 3955 | struct x86_exception *exception) |
1871c602 | 3956 | { |
0f65dd70 | 3957 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
1871c602 | 3958 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
0f65dd70 | 3959 | |
1871c602 | 3960 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, |
bcc55cba | 3961 | exception); |
1871c602 | 3962 | } |
064aea77 | 3963 | EXPORT_SYMBOL_GPL(kvm_read_guest_virt); |
1871c602 | 3964 | |
0f65dd70 AK |
3965 | static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt, |
3966 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 3967 | struct x86_exception *exception) |
1871c602 | 3968 | { |
0f65dd70 | 3969 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
bcc55cba | 3970 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception); |
1871c602 GN |
3971 | } |
3972 | ||
6a4d7550 | 3973 | int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt, |
0f65dd70 | 3974 | gva_t addr, void *val, |
2dafc6c2 | 3975 | unsigned int bytes, |
bcc55cba | 3976 | struct x86_exception *exception) |
77c2002e | 3977 | { |
0f65dd70 | 3978 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
77c2002e IE |
3979 | void *data = val; |
3980 | int r = X86EMUL_CONTINUE; | |
3981 | ||
3982 | while (bytes) { | |
14dfe855 JR |
3983 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, |
3984 | PFERR_WRITE_MASK, | |
ab9ae313 | 3985 | exception); |
77c2002e IE |
3986 | unsigned offset = addr & (PAGE_SIZE-1); |
3987 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
3988 | int ret; | |
3989 | ||
bcc55cba | 3990 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 3991 | return X86EMUL_PROPAGATE_FAULT; |
77c2002e IE |
3992 | ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite); |
3993 | if (ret < 0) { | |
c3cd7ffa | 3994 | r = X86EMUL_IO_NEEDED; |
77c2002e IE |
3995 | goto out; |
3996 | } | |
3997 | ||
3998 | bytes -= towrite; | |
3999 | data += towrite; | |
4000 | addr += towrite; | |
4001 | } | |
4002 | out: | |
4003 | return r; | |
4004 | } | |
6a4d7550 | 4005 | EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); |
77c2002e | 4006 | |
af7cc7d1 XG |
4007 | static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
4008 | gpa_t *gpa, struct x86_exception *exception, | |
4009 | bool write) | |
4010 | { | |
97d64b78 AK |
4011 | u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) |
4012 | | (write ? PFERR_WRITE_MASK : 0); | |
af7cc7d1 | 4013 | |
97d64b78 AK |
4014 | if (vcpu_match_mmio_gva(vcpu, gva) |
4015 | && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) { | |
bebb106a XG |
4016 | *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | |
4017 | (gva & (PAGE_SIZE - 1)); | |
4f022648 | 4018 | trace_vcpu_match_mmio(gva, *gpa, write, false); |
bebb106a XG |
4019 | return 1; |
4020 | } | |
4021 | ||
af7cc7d1 XG |
4022 | *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
4023 | ||
4024 | if (*gpa == UNMAPPED_GVA) | |
4025 | return -1; | |
4026 | ||
4027 | /* For APIC access vmexit */ | |
4028 | if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
4029 | return 1; | |
4030 | ||
4f022648 XG |
4031 | if (vcpu_match_mmio_gpa(vcpu, *gpa)) { |
4032 | trace_vcpu_match_mmio(gva, *gpa, write, true); | |
bebb106a | 4033 | return 1; |
4f022648 | 4034 | } |
bebb106a | 4035 | |
af7cc7d1 XG |
4036 | return 0; |
4037 | } | |
4038 | ||
3200f405 | 4039 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
bcc55cba | 4040 | const void *val, int bytes) |
bbd9b64e CO |
4041 | { |
4042 | int ret; | |
4043 | ||
4044 | ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes); | |
9f811285 | 4045 | if (ret < 0) |
bbd9b64e | 4046 | return 0; |
f57f2ef5 | 4047 | kvm_mmu_pte_write(vcpu, gpa, val, bytes); |
bbd9b64e CO |
4048 | return 1; |
4049 | } | |
4050 | ||
77d197b2 XG |
4051 | struct read_write_emulator_ops { |
4052 | int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, | |
4053 | int bytes); | |
4054 | int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4055 | void *val, int bytes); | |
4056 | int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4057 | int bytes, void *val); | |
4058 | int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4059 | void *val, int bytes); | |
4060 | bool write; | |
4061 | }; | |
4062 | ||
4063 | static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) | |
4064 | { | |
4065 | if (vcpu->mmio_read_completed) { | |
77d197b2 | 4066 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
f78146b0 | 4067 | vcpu->mmio_fragments[0].gpa, *(u64 *)val); |
77d197b2 XG |
4068 | vcpu->mmio_read_completed = 0; |
4069 | return 1; | |
4070 | } | |
4071 | ||
4072 | return 0; | |
4073 | } | |
4074 | ||
4075 | static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4076 | void *val, int bytes) | |
4077 | { | |
4078 | return !kvm_read_guest(vcpu->kvm, gpa, val, bytes); | |
4079 | } | |
4080 | ||
4081 | static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4082 | void *val, int bytes) | |
4083 | { | |
4084 | return emulator_write_phys(vcpu, gpa, val, bytes); | |
4085 | } | |
4086 | ||
4087 | static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) | |
4088 | { | |
4089 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); | |
4090 | return vcpu_mmio_write(vcpu, gpa, bytes, val); | |
4091 | } | |
4092 | ||
4093 | static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4094 | void *val, int bytes) | |
4095 | { | |
4096 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); | |
4097 | return X86EMUL_IO_NEEDED; | |
4098 | } | |
4099 | ||
4100 | static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4101 | void *val, int bytes) | |
4102 | { | |
f78146b0 AK |
4103 | struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; |
4104 | ||
87da7e66 | 4105 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); |
77d197b2 XG |
4106 | return X86EMUL_CONTINUE; |
4107 | } | |
4108 | ||
0fbe9b0b | 4109 | static const struct read_write_emulator_ops read_emultor = { |
77d197b2 XG |
4110 | .read_write_prepare = read_prepare, |
4111 | .read_write_emulate = read_emulate, | |
4112 | .read_write_mmio = vcpu_mmio_read, | |
4113 | .read_write_exit_mmio = read_exit_mmio, | |
4114 | }; | |
4115 | ||
0fbe9b0b | 4116 | static const struct read_write_emulator_ops write_emultor = { |
77d197b2 XG |
4117 | .read_write_emulate = write_emulate, |
4118 | .read_write_mmio = write_mmio, | |
4119 | .read_write_exit_mmio = write_exit_mmio, | |
4120 | .write = true, | |
4121 | }; | |
4122 | ||
22388a3c XG |
4123 | static int emulator_read_write_onepage(unsigned long addr, void *val, |
4124 | unsigned int bytes, | |
4125 | struct x86_exception *exception, | |
4126 | struct kvm_vcpu *vcpu, | |
0fbe9b0b | 4127 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 4128 | { |
af7cc7d1 XG |
4129 | gpa_t gpa; |
4130 | int handled, ret; | |
22388a3c | 4131 | bool write = ops->write; |
f78146b0 | 4132 | struct kvm_mmio_fragment *frag; |
10589a46 | 4133 | |
22388a3c | 4134 | ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); |
bbd9b64e | 4135 | |
af7cc7d1 | 4136 | if (ret < 0) |
bbd9b64e | 4137 | return X86EMUL_PROPAGATE_FAULT; |
bbd9b64e CO |
4138 | |
4139 | /* For APIC access vmexit */ | |
af7cc7d1 | 4140 | if (ret) |
bbd9b64e CO |
4141 | goto mmio; |
4142 | ||
22388a3c | 4143 | if (ops->read_write_emulate(vcpu, gpa, val, bytes)) |
bbd9b64e CO |
4144 | return X86EMUL_CONTINUE; |
4145 | ||
4146 | mmio: | |
4147 | /* | |
4148 | * Is this MMIO handled locally? | |
4149 | */ | |
22388a3c | 4150 | handled = ops->read_write_mmio(vcpu, gpa, bytes, val); |
70252a10 | 4151 | if (handled == bytes) |
bbd9b64e | 4152 | return X86EMUL_CONTINUE; |
bbd9b64e | 4153 | |
70252a10 AK |
4154 | gpa += handled; |
4155 | bytes -= handled; | |
4156 | val += handled; | |
4157 | ||
87da7e66 XG |
4158 | WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); |
4159 | frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; | |
4160 | frag->gpa = gpa; | |
4161 | frag->data = val; | |
4162 | frag->len = bytes; | |
f78146b0 | 4163 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
4164 | } |
4165 | ||
22388a3c XG |
4166 | int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr, |
4167 | void *val, unsigned int bytes, | |
4168 | struct x86_exception *exception, | |
0fbe9b0b | 4169 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 4170 | { |
0f65dd70 | 4171 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
f78146b0 AK |
4172 | gpa_t gpa; |
4173 | int rc; | |
4174 | ||
4175 | if (ops->read_write_prepare && | |
4176 | ops->read_write_prepare(vcpu, val, bytes)) | |
4177 | return X86EMUL_CONTINUE; | |
4178 | ||
4179 | vcpu->mmio_nr_fragments = 0; | |
0f65dd70 | 4180 | |
bbd9b64e CO |
4181 | /* Crossing a page boundary? */ |
4182 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
f78146b0 | 4183 | int now; |
bbd9b64e CO |
4184 | |
4185 | now = -addr & ~PAGE_MASK; | |
22388a3c XG |
4186 | rc = emulator_read_write_onepage(addr, val, now, exception, |
4187 | vcpu, ops); | |
4188 | ||
bbd9b64e CO |
4189 | if (rc != X86EMUL_CONTINUE) |
4190 | return rc; | |
4191 | addr += now; | |
4192 | val += now; | |
4193 | bytes -= now; | |
4194 | } | |
22388a3c | 4195 | |
f78146b0 AK |
4196 | rc = emulator_read_write_onepage(addr, val, bytes, exception, |
4197 | vcpu, ops); | |
4198 | if (rc != X86EMUL_CONTINUE) | |
4199 | return rc; | |
4200 | ||
4201 | if (!vcpu->mmio_nr_fragments) | |
4202 | return rc; | |
4203 | ||
4204 | gpa = vcpu->mmio_fragments[0].gpa; | |
4205 | ||
4206 | vcpu->mmio_needed = 1; | |
4207 | vcpu->mmio_cur_fragment = 0; | |
4208 | ||
87da7e66 | 4209 | vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); |
f78146b0 AK |
4210 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; |
4211 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
4212 | vcpu->run->mmio.phys_addr = gpa; | |
4213 | ||
4214 | return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); | |
22388a3c XG |
4215 | } |
4216 | ||
4217 | static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, | |
4218 | unsigned long addr, | |
4219 | void *val, | |
4220 | unsigned int bytes, | |
4221 | struct x86_exception *exception) | |
4222 | { | |
4223 | return emulator_read_write(ctxt, addr, val, bytes, | |
4224 | exception, &read_emultor); | |
4225 | } | |
4226 | ||
4227 | int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, | |
4228 | unsigned long addr, | |
4229 | const void *val, | |
4230 | unsigned int bytes, | |
4231 | struct x86_exception *exception) | |
4232 | { | |
4233 | return emulator_read_write(ctxt, addr, (void *)val, bytes, | |
4234 | exception, &write_emultor); | |
bbd9b64e | 4235 | } |
bbd9b64e | 4236 | |
daea3e73 AK |
4237 | #define CMPXCHG_TYPE(t, ptr, old, new) \ |
4238 | (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) | |
4239 | ||
4240 | #ifdef CONFIG_X86_64 | |
4241 | # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) | |
4242 | #else | |
4243 | # define CMPXCHG64(ptr, old, new) \ | |
9749a6c0 | 4244 | (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) |
daea3e73 AK |
4245 | #endif |
4246 | ||
0f65dd70 AK |
4247 | static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, |
4248 | unsigned long addr, | |
bbd9b64e CO |
4249 | const void *old, |
4250 | const void *new, | |
4251 | unsigned int bytes, | |
0f65dd70 | 4252 | struct x86_exception *exception) |
bbd9b64e | 4253 | { |
0f65dd70 | 4254 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
daea3e73 AK |
4255 | gpa_t gpa; |
4256 | struct page *page; | |
4257 | char *kaddr; | |
4258 | bool exchanged; | |
2bacc55c | 4259 | |
daea3e73 AK |
4260 | /* guests cmpxchg8b have to be emulated atomically */ |
4261 | if (bytes > 8 || (bytes & (bytes - 1))) | |
4262 | goto emul_write; | |
10589a46 | 4263 | |
daea3e73 | 4264 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); |
2bacc55c | 4265 | |
daea3e73 AK |
4266 | if (gpa == UNMAPPED_GVA || |
4267 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
4268 | goto emul_write; | |
2bacc55c | 4269 | |
daea3e73 AK |
4270 | if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) |
4271 | goto emul_write; | |
72dc67a6 | 4272 | |
daea3e73 | 4273 | page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
32cad84f | 4274 | if (is_error_page(page)) |
c19b8bd6 | 4275 | goto emul_write; |
72dc67a6 | 4276 | |
8fd75e12 | 4277 | kaddr = kmap_atomic(page); |
daea3e73 AK |
4278 | kaddr += offset_in_page(gpa); |
4279 | switch (bytes) { | |
4280 | case 1: | |
4281 | exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); | |
4282 | break; | |
4283 | case 2: | |
4284 | exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); | |
4285 | break; | |
4286 | case 4: | |
4287 | exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); | |
4288 | break; | |
4289 | case 8: | |
4290 | exchanged = CMPXCHG64(kaddr, old, new); | |
4291 | break; | |
4292 | default: | |
4293 | BUG(); | |
2bacc55c | 4294 | } |
8fd75e12 | 4295 | kunmap_atomic(kaddr); |
daea3e73 AK |
4296 | kvm_release_page_dirty(page); |
4297 | ||
4298 | if (!exchanged) | |
4299 | return X86EMUL_CMPXCHG_FAILED; | |
4300 | ||
f57f2ef5 | 4301 | kvm_mmu_pte_write(vcpu, gpa, new, bytes); |
8f6abd06 GN |
4302 | |
4303 | return X86EMUL_CONTINUE; | |
4a5f48f6 | 4304 | |
3200f405 | 4305 | emul_write: |
daea3e73 | 4306 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); |
2bacc55c | 4307 | |
0f65dd70 | 4308 | return emulator_write_emulated(ctxt, addr, new, bytes, exception); |
bbd9b64e CO |
4309 | } |
4310 | ||
cf8f70bf GN |
4311 | static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) |
4312 | { | |
4313 | /* TODO: String I/O for in kernel device */ | |
4314 | int r; | |
4315 | ||
4316 | if (vcpu->arch.pio.in) | |
4317 | r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port, | |
4318 | vcpu->arch.pio.size, pd); | |
4319 | else | |
4320 | r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS, | |
4321 | vcpu->arch.pio.port, vcpu->arch.pio.size, | |
4322 | pd); | |
4323 | return r; | |
4324 | } | |
4325 | ||
6f6fbe98 XG |
4326 | static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, |
4327 | unsigned short port, void *val, | |
4328 | unsigned int count, bool in) | |
cf8f70bf | 4329 | { |
6f6fbe98 | 4330 | trace_kvm_pio(!in, port, size, count); |
cf8f70bf GN |
4331 | |
4332 | vcpu->arch.pio.port = port; | |
6f6fbe98 | 4333 | vcpu->arch.pio.in = in; |
7972995b | 4334 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
4335 | vcpu->arch.pio.size = size; |
4336 | ||
4337 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
7972995b | 4338 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
4339 | return 1; |
4340 | } | |
4341 | ||
4342 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
6f6fbe98 | 4343 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; |
cf8f70bf GN |
4344 | vcpu->run->io.size = size; |
4345 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
4346 | vcpu->run->io.count = count; | |
4347 | vcpu->run->io.port = port; | |
4348 | ||
4349 | return 0; | |
4350 | } | |
4351 | ||
6f6fbe98 XG |
4352 | static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
4353 | int size, unsigned short port, void *val, | |
4354 | unsigned int count) | |
cf8f70bf | 4355 | { |
ca1d4a9e | 4356 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
6f6fbe98 | 4357 | int ret; |
ca1d4a9e | 4358 | |
6f6fbe98 XG |
4359 | if (vcpu->arch.pio.count) |
4360 | goto data_avail; | |
cf8f70bf | 4361 | |
6f6fbe98 XG |
4362 | ret = emulator_pio_in_out(vcpu, size, port, val, count, true); |
4363 | if (ret) { | |
4364 | data_avail: | |
4365 | memcpy(val, vcpu->arch.pio_data, size * count); | |
7972995b | 4366 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
4367 | return 1; |
4368 | } | |
4369 | ||
cf8f70bf GN |
4370 | return 0; |
4371 | } | |
4372 | ||
6f6fbe98 XG |
4373 | static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, |
4374 | int size, unsigned short port, | |
4375 | const void *val, unsigned int count) | |
4376 | { | |
4377 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
4378 | ||
4379 | memcpy(vcpu->arch.pio_data, val, size * count); | |
4380 | return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); | |
4381 | } | |
4382 | ||
bbd9b64e CO |
4383 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) |
4384 | { | |
4385 | return kvm_x86_ops->get_segment_base(vcpu, seg); | |
4386 | } | |
4387 | ||
3cb16fe7 | 4388 | static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) |
bbd9b64e | 4389 | { |
3cb16fe7 | 4390 | kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); |
bbd9b64e CO |
4391 | } |
4392 | ||
f5f48ee1 SY |
4393 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) |
4394 | { | |
4395 | if (!need_emulate_wbinvd(vcpu)) | |
4396 | return X86EMUL_CONTINUE; | |
4397 | ||
4398 | if (kvm_x86_ops->has_wbinvd_exit()) { | |
2eec7343 JK |
4399 | int cpu = get_cpu(); |
4400 | ||
4401 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
f5f48ee1 SY |
4402 | smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, |
4403 | wbinvd_ipi, NULL, 1); | |
2eec7343 | 4404 | put_cpu(); |
f5f48ee1 | 4405 | cpumask_clear(vcpu->arch.wbinvd_dirty_mask); |
2eec7343 JK |
4406 | } else |
4407 | wbinvd(); | |
f5f48ee1 SY |
4408 | return X86EMUL_CONTINUE; |
4409 | } | |
4410 | EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); | |
4411 | ||
bcaf5cc5 AK |
4412 | static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) |
4413 | { | |
4414 | kvm_emulate_wbinvd(emul_to_vcpu(ctxt)); | |
4415 | } | |
4416 | ||
717746e3 | 4417 | int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest) |
bbd9b64e | 4418 | { |
717746e3 | 4419 | return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); |
bbd9b64e CO |
4420 | } |
4421 | ||
717746e3 | 4422 | int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value) |
bbd9b64e | 4423 | { |
338dbc97 | 4424 | |
717746e3 | 4425 | return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); |
bbd9b64e CO |
4426 | } |
4427 | ||
52a46617 | 4428 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) |
5fdbf976 | 4429 | { |
52a46617 | 4430 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; |
5fdbf976 MT |
4431 | } |
4432 | ||
717746e3 | 4433 | static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) |
bbd9b64e | 4434 | { |
717746e3 | 4435 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
52a46617 GN |
4436 | unsigned long value; |
4437 | ||
4438 | switch (cr) { | |
4439 | case 0: | |
4440 | value = kvm_read_cr0(vcpu); | |
4441 | break; | |
4442 | case 2: | |
4443 | value = vcpu->arch.cr2; | |
4444 | break; | |
4445 | case 3: | |
9f8fe504 | 4446 | value = kvm_read_cr3(vcpu); |
52a46617 GN |
4447 | break; |
4448 | case 4: | |
4449 | value = kvm_read_cr4(vcpu); | |
4450 | break; | |
4451 | case 8: | |
4452 | value = kvm_get_cr8(vcpu); | |
4453 | break; | |
4454 | default: | |
a737f256 | 4455 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
52a46617 GN |
4456 | return 0; |
4457 | } | |
4458 | ||
4459 | return value; | |
4460 | } | |
4461 | ||
717746e3 | 4462 | static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) |
52a46617 | 4463 | { |
717746e3 | 4464 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
0f12244f GN |
4465 | int res = 0; |
4466 | ||
52a46617 GN |
4467 | switch (cr) { |
4468 | case 0: | |
49a9b07e | 4469 | res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
52a46617 GN |
4470 | break; |
4471 | case 2: | |
4472 | vcpu->arch.cr2 = val; | |
4473 | break; | |
4474 | case 3: | |
2390218b | 4475 | res = kvm_set_cr3(vcpu, val); |
52a46617 GN |
4476 | break; |
4477 | case 4: | |
a83b29c6 | 4478 | res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
52a46617 GN |
4479 | break; |
4480 | case 8: | |
eea1cff9 | 4481 | res = kvm_set_cr8(vcpu, val); |
52a46617 GN |
4482 | break; |
4483 | default: | |
a737f256 | 4484 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
0f12244f | 4485 | res = -1; |
52a46617 | 4486 | } |
0f12244f GN |
4487 | |
4488 | return res; | |
52a46617 GN |
4489 | } |
4490 | ||
4cee4798 KW |
4491 | static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val) |
4492 | { | |
4493 | kvm_set_rflags(emul_to_vcpu(ctxt), val); | |
4494 | } | |
4495 | ||
717746e3 | 4496 | static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) |
9c537244 | 4497 | { |
717746e3 | 4498 | return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); |
9c537244 GN |
4499 | } |
4500 | ||
4bff1e86 | 4501 | static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
2dafc6c2 | 4502 | { |
4bff1e86 | 4503 | kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); |
2dafc6c2 GN |
4504 | } |
4505 | ||
4bff1e86 | 4506 | static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
160ce1f1 | 4507 | { |
4bff1e86 | 4508 | kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); |
160ce1f1 MG |
4509 | } |
4510 | ||
1ac9d0cf AK |
4511 | static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
4512 | { | |
4513 | kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); | |
4514 | } | |
4515 | ||
4516 | static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) | |
4517 | { | |
4518 | kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); | |
4519 | } | |
4520 | ||
4bff1e86 AK |
4521 | static unsigned long emulator_get_cached_segment_base( |
4522 | struct x86_emulate_ctxt *ctxt, int seg) | |
5951c442 | 4523 | { |
4bff1e86 | 4524 | return get_segment_base(emul_to_vcpu(ctxt), seg); |
5951c442 GN |
4525 | } |
4526 | ||
1aa36616 AK |
4527 | static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, |
4528 | struct desc_struct *desc, u32 *base3, | |
4529 | int seg) | |
2dafc6c2 GN |
4530 | { |
4531 | struct kvm_segment var; | |
4532 | ||
4bff1e86 | 4533 | kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); |
1aa36616 | 4534 | *selector = var.selector; |
2dafc6c2 | 4535 | |
378a8b09 GN |
4536 | if (var.unusable) { |
4537 | memset(desc, 0, sizeof(*desc)); | |
2dafc6c2 | 4538 | return false; |
378a8b09 | 4539 | } |
2dafc6c2 GN |
4540 | |
4541 | if (var.g) | |
4542 | var.limit >>= 12; | |
4543 | set_desc_limit(desc, var.limit); | |
4544 | set_desc_base(desc, (unsigned long)var.base); | |
5601d05b GN |
4545 | #ifdef CONFIG_X86_64 |
4546 | if (base3) | |
4547 | *base3 = var.base >> 32; | |
4548 | #endif | |
2dafc6c2 GN |
4549 | desc->type = var.type; |
4550 | desc->s = var.s; | |
4551 | desc->dpl = var.dpl; | |
4552 | desc->p = var.present; | |
4553 | desc->avl = var.avl; | |
4554 | desc->l = var.l; | |
4555 | desc->d = var.db; | |
4556 | desc->g = var.g; | |
4557 | ||
4558 | return true; | |
4559 | } | |
4560 | ||
1aa36616 AK |
4561 | static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, |
4562 | struct desc_struct *desc, u32 base3, | |
4563 | int seg) | |
2dafc6c2 | 4564 | { |
4bff1e86 | 4565 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
2dafc6c2 GN |
4566 | struct kvm_segment var; |
4567 | ||
1aa36616 | 4568 | var.selector = selector; |
2dafc6c2 | 4569 | var.base = get_desc_base(desc); |
5601d05b GN |
4570 | #ifdef CONFIG_X86_64 |
4571 | var.base |= ((u64)base3) << 32; | |
4572 | #endif | |
2dafc6c2 GN |
4573 | var.limit = get_desc_limit(desc); |
4574 | if (desc->g) | |
4575 | var.limit = (var.limit << 12) | 0xfff; | |
4576 | var.type = desc->type; | |
4577 | var.present = desc->p; | |
4578 | var.dpl = desc->dpl; | |
4579 | var.db = desc->d; | |
4580 | var.s = desc->s; | |
4581 | var.l = desc->l; | |
4582 | var.g = desc->g; | |
4583 | var.avl = desc->avl; | |
4584 | var.present = desc->p; | |
4585 | var.unusable = !var.present; | |
4586 | var.padding = 0; | |
4587 | ||
4588 | kvm_set_segment(vcpu, &var, seg); | |
4589 | return; | |
4590 | } | |
4591 | ||
717746e3 AK |
4592 | static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, |
4593 | u32 msr_index, u64 *pdata) | |
4594 | { | |
4595 | return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata); | |
4596 | } | |
4597 | ||
4598 | static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, | |
4599 | u32 msr_index, u64 data) | |
4600 | { | |
8fe8ab46 WA |
4601 | struct msr_data msr; |
4602 | ||
4603 | msr.data = data; | |
4604 | msr.index = msr_index; | |
4605 | msr.host_initiated = false; | |
4606 | return kvm_set_msr(emul_to_vcpu(ctxt), &msr); | |
717746e3 AK |
4607 | } |
4608 | ||
222d21aa AK |
4609 | static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, |
4610 | u32 pmc, u64 *pdata) | |
4611 | { | |
4612 | return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata); | |
4613 | } | |
4614 | ||
6c3287f7 AK |
4615 | static void emulator_halt(struct x86_emulate_ctxt *ctxt) |
4616 | { | |
4617 | emul_to_vcpu(ctxt)->arch.halt_request = 1; | |
4618 | } | |
4619 | ||
5037f6f3 AK |
4620 | static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt) |
4621 | { | |
4622 | preempt_disable(); | |
5197b808 | 4623 | kvm_load_guest_fpu(emul_to_vcpu(ctxt)); |
5037f6f3 AK |
4624 | /* |
4625 | * CR0.TS may reference the host fpu state, not the guest fpu state, | |
4626 | * so it may be clear at this point. | |
4627 | */ | |
4628 | clts(); | |
4629 | } | |
4630 | ||
4631 | static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt) | |
4632 | { | |
4633 | preempt_enable(); | |
4634 | } | |
4635 | ||
2953538e | 4636 | static int emulator_intercept(struct x86_emulate_ctxt *ctxt, |
8a76d7f2 | 4637 | struct x86_instruction_info *info, |
c4f035c6 AK |
4638 | enum x86_intercept_stage stage) |
4639 | { | |
2953538e | 4640 | return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); |
c4f035c6 AK |
4641 | } |
4642 | ||
0017f93a | 4643 | static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, |
bdb42f5a SB |
4644 | u32 *eax, u32 *ebx, u32 *ecx, u32 *edx) |
4645 | { | |
0017f93a | 4646 | kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx); |
bdb42f5a SB |
4647 | } |
4648 | ||
dd856efa AK |
4649 | static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) |
4650 | { | |
4651 | return kvm_register_read(emul_to_vcpu(ctxt), reg); | |
4652 | } | |
4653 | ||
4654 | static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) | |
4655 | { | |
4656 | kvm_register_write(emul_to_vcpu(ctxt), reg, val); | |
4657 | } | |
4658 | ||
0225fb50 | 4659 | static const struct x86_emulate_ops emulate_ops = { |
dd856efa AK |
4660 | .read_gpr = emulator_read_gpr, |
4661 | .write_gpr = emulator_write_gpr, | |
1871c602 | 4662 | .read_std = kvm_read_guest_virt_system, |
2dafc6c2 | 4663 | .write_std = kvm_write_guest_virt_system, |
1871c602 | 4664 | .fetch = kvm_fetch_guest_virt, |
bbd9b64e CO |
4665 | .read_emulated = emulator_read_emulated, |
4666 | .write_emulated = emulator_write_emulated, | |
4667 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
3cb16fe7 | 4668 | .invlpg = emulator_invlpg, |
cf8f70bf GN |
4669 | .pio_in_emulated = emulator_pio_in_emulated, |
4670 | .pio_out_emulated = emulator_pio_out_emulated, | |
1aa36616 AK |
4671 | .get_segment = emulator_get_segment, |
4672 | .set_segment = emulator_set_segment, | |
5951c442 | 4673 | .get_cached_segment_base = emulator_get_cached_segment_base, |
2dafc6c2 | 4674 | .get_gdt = emulator_get_gdt, |
160ce1f1 | 4675 | .get_idt = emulator_get_idt, |
1ac9d0cf AK |
4676 | .set_gdt = emulator_set_gdt, |
4677 | .set_idt = emulator_set_idt, | |
52a46617 GN |
4678 | .get_cr = emulator_get_cr, |
4679 | .set_cr = emulator_set_cr, | |
4cee4798 | 4680 | .set_rflags = emulator_set_rflags, |
9c537244 | 4681 | .cpl = emulator_get_cpl, |
35aa5375 GN |
4682 | .get_dr = emulator_get_dr, |
4683 | .set_dr = emulator_set_dr, | |
717746e3 AK |
4684 | .set_msr = emulator_set_msr, |
4685 | .get_msr = emulator_get_msr, | |
222d21aa | 4686 | .read_pmc = emulator_read_pmc, |
6c3287f7 | 4687 | .halt = emulator_halt, |
bcaf5cc5 | 4688 | .wbinvd = emulator_wbinvd, |
d6aa1000 | 4689 | .fix_hypercall = emulator_fix_hypercall, |
5037f6f3 AK |
4690 | .get_fpu = emulator_get_fpu, |
4691 | .put_fpu = emulator_put_fpu, | |
c4f035c6 | 4692 | .intercept = emulator_intercept, |
bdb42f5a | 4693 | .get_cpuid = emulator_get_cpuid, |
bbd9b64e CO |
4694 | }; |
4695 | ||
95cb2295 GN |
4696 | static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) |
4697 | { | |
4698 | u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask); | |
4699 | /* | |
4700 | * an sti; sti; sequence only disable interrupts for the first | |
4701 | * instruction. So, if the last instruction, be it emulated or | |
4702 | * not, left the system with the INT_STI flag enabled, it | |
4703 | * means that the last instruction is an sti. We should not | |
4704 | * leave the flag on in this case. The same goes for mov ss | |
4705 | */ | |
4706 | if (!(int_shadow & mask)) | |
4707 | kvm_x86_ops->set_interrupt_shadow(vcpu, mask); | |
4708 | } | |
4709 | ||
54b8486f GN |
4710 | static void inject_emulated_exception(struct kvm_vcpu *vcpu) |
4711 | { | |
4712 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; | |
da9cb575 | 4713 | if (ctxt->exception.vector == PF_VECTOR) |
6389ee94 | 4714 | kvm_propagate_fault(vcpu, &ctxt->exception); |
da9cb575 AK |
4715 | else if (ctxt->exception.error_code_valid) |
4716 | kvm_queue_exception_e(vcpu, ctxt->exception.vector, | |
4717 | ctxt->exception.error_code); | |
54b8486f | 4718 | else |
da9cb575 | 4719 | kvm_queue_exception(vcpu, ctxt->exception.vector); |
54b8486f GN |
4720 | } |
4721 | ||
dd856efa | 4722 | static void init_decode_cache(struct x86_emulate_ctxt *ctxt) |
b5c9ff73 | 4723 | { |
9dac77fa | 4724 | memset(&ctxt->twobyte, 0, |
dd856efa | 4725 | (void *)&ctxt->_regs - (void *)&ctxt->twobyte); |
b5c9ff73 | 4726 | |
9dac77fa AK |
4727 | ctxt->fetch.start = 0; |
4728 | ctxt->fetch.end = 0; | |
4729 | ctxt->io_read.pos = 0; | |
4730 | ctxt->io_read.end = 0; | |
4731 | ctxt->mem_read.pos = 0; | |
4732 | ctxt->mem_read.end = 0; | |
b5c9ff73 TY |
4733 | } |
4734 | ||
8ec4722d MG |
4735 | static void init_emulate_ctxt(struct kvm_vcpu *vcpu) |
4736 | { | |
adf52235 | 4737 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
8ec4722d MG |
4738 | int cs_db, cs_l; |
4739 | ||
8ec4722d MG |
4740 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
4741 | ||
adf52235 TY |
4742 | ctxt->eflags = kvm_get_rflags(vcpu); |
4743 | ctxt->eip = kvm_rip_read(vcpu); | |
4744 | ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : | |
4745 | (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : | |
4746 | cs_l ? X86EMUL_MODE_PROT64 : | |
4747 | cs_db ? X86EMUL_MODE_PROT32 : | |
4748 | X86EMUL_MODE_PROT16; | |
4749 | ctxt->guest_mode = is_guest_mode(vcpu); | |
4750 | ||
dd856efa | 4751 | init_decode_cache(ctxt); |
7ae441ea | 4752 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; |
8ec4722d MG |
4753 | } |
4754 | ||
71f9833b | 4755 | int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) |
63995653 | 4756 | { |
9d74191a | 4757 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
63995653 MG |
4758 | int ret; |
4759 | ||
4760 | init_emulate_ctxt(vcpu); | |
4761 | ||
9dac77fa AK |
4762 | ctxt->op_bytes = 2; |
4763 | ctxt->ad_bytes = 2; | |
4764 | ctxt->_eip = ctxt->eip + inc_eip; | |
9d74191a | 4765 | ret = emulate_int_real(ctxt, irq); |
63995653 MG |
4766 | |
4767 | if (ret != X86EMUL_CONTINUE) | |
4768 | return EMULATE_FAIL; | |
4769 | ||
9dac77fa | 4770 | ctxt->eip = ctxt->_eip; |
9d74191a TY |
4771 | kvm_rip_write(vcpu, ctxt->eip); |
4772 | kvm_set_rflags(vcpu, ctxt->eflags); | |
63995653 MG |
4773 | |
4774 | if (irq == NMI_VECTOR) | |
7460fb4a | 4775 | vcpu->arch.nmi_pending = 0; |
63995653 MG |
4776 | else |
4777 | vcpu->arch.interrupt.pending = false; | |
4778 | ||
4779 | return EMULATE_DONE; | |
4780 | } | |
4781 | EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); | |
4782 | ||
6d77dbfc GN |
4783 | static int handle_emulation_failure(struct kvm_vcpu *vcpu) |
4784 | { | |
fc3a9157 JR |
4785 | int r = EMULATE_DONE; |
4786 | ||
6d77dbfc GN |
4787 | ++vcpu->stat.insn_emulation_fail; |
4788 | trace_kvm_emulate_insn_failed(vcpu); | |
fc3a9157 JR |
4789 | if (!is_guest_mode(vcpu)) { |
4790 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
4791 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
4792 | vcpu->run->internal.ndata = 0; | |
4793 | r = EMULATE_FAIL; | |
4794 | } | |
6d77dbfc | 4795 | kvm_queue_exception(vcpu, UD_VECTOR); |
fc3a9157 JR |
4796 | |
4797 | return r; | |
6d77dbfc GN |
4798 | } |
4799 | ||
93c05d3e | 4800 | static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, |
991eebf9 GN |
4801 | bool write_fault_to_shadow_pgtable, |
4802 | int emulation_type) | |
a6f177ef | 4803 | { |
95b3cf69 | 4804 | gpa_t gpa = cr2; |
8e3d9d06 | 4805 | pfn_t pfn; |
a6f177ef | 4806 | |
991eebf9 GN |
4807 | if (emulation_type & EMULTYPE_NO_REEXECUTE) |
4808 | return false; | |
4809 | ||
95b3cf69 XG |
4810 | if (!vcpu->arch.mmu.direct_map) { |
4811 | /* | |
4812 | * Write permission should be allowed since only | |
4813 | * write access need to be emulated. | |
4814 | */ | |
4815 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); | |
a6f177ef | 4816 | |
95b3cf69 XG |
4817 | /* |
4818 | * If the mapping is invalid in guest, let cpu retry | |
4819 | * it to generate fault. | |
4820 | */ | |
4821 | if (gpa == UNMAPPED_GVA) | |
4822 | return true; | |
4823 | } | |
a6f177ef | 4824 | |
8e3d9d06 XG |
4825 | /* |
4826 | * Do not retry the unhandleable instruction if it faults on the | |
4827 | * readonly host memory, otherwise it will goto a infinite loop: | |
4828 | * retry instruction -> write #PF -> emulation fail -> retry | |
4829 | * instruction -> ... | |
4830 | */ | |
4831 | pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); | |
95b3cf69 XG |
4832 | |
4833 | /* | |
4834 | * If the instruction failed on the error pfn, it can not be fixed, | |
4835 | * report the error to userspace. | |
4836 | */ | |
4837 | if (is_error_noslot_pfn(pfn)) | |
4838 | return false; | |
4839 | ||
4840 | kvm_release_pfn_clean(pfn); | |
4841 | ||
4842 | /* The instructions are well-emulated on direct mmu. */ | |
4843 | if (vcpu->arch.mmu.direct_map) { | |
4844 | unsigned int indirect_shadow_pages; | |
4845 | ||
4846 | spin_lock(&vcpu->kvm->mmu_lock); | |
4847 | indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; | |
4848 | spin_unlock(&vcpu->kvm->mmu_lock); | |
4849 | ||
4850 | if (indirect_shadow_pages) | |
4851 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
4852 | ||
a6f177ef | 4853 | return true; |
8e3d9d06 | 4854 | } |
a6f177ef | 4855 | |
95b3cf69 XG |
4856 | /* |
4857 | * if emulation was due to access to shadowed page table | |
4858 | * and it failed try to unshadow page and re-enter the | |
4859 | * guest to let CPU execute the instruction. | |
4860 | */ | |
4861 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
93c05d3e XG |
4862 | |
4863 | /* | |
4864 | * If the access faults on its page table, it can not | |
4865 | * be fixed by unprotecting shadow page and it should | |
4866 | * be reported to userspace. | |
4867 | */ | |
4868 | return !write_fault_to_shadow_pgtable; | |
a6f177ef GN |
4869 | } |
4870 | ||
1cb3f3ae XG |
4871 | static bool retry_instruction(struct x86_emulate_ctxt *ctxt, |
4872 | unsigned long cr2, int emulation_type) | |
4873 | { | |
4874 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
4875 | unsigned long last_retry_eip, last_retry_addr, gpa = cr2; | |
4876 | ||
4877 | last_retry_eip = vcpu->arch.last_retry_eip; | |
4878 | last_retry_addr = vcpu->arch.last_retry_addr; | |
4879 | ||
4880 | /* | |
4881 | * If the emulation is caused by #PF and it is non-page_table | |
4882 | * writing instruction, it means the VM-EXIT is caused by shadow | |
4883 | * page protected, we can zap the shadow page and retry this | |
4884 | * instruction directly. | |
4885 | * | |
4886 | * Note: if the guest uses a non-page-table modifying instruction | |
4887 | * on the PDE that points to the instruction, then we will unmap | |
4888 | * the instruction and go to an infinite loop. So, we cache the | |
4889 | * last retried eip and the last fault address, if we meet the eip | |
4890 | * and the address again, we can break out of the potential infinite | |
4891 | * loop. | |
4892 | */ | |
4893 | vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; | |
4894 | ||
4895 | if (!(emulation_type & EMULTYPE_RETRY)) | |
4896 | return false; | |
4897 | ||
4898 | if (x86_page_table_writing_insn(ctxt)) | |
4899 | return false; | |
4900 | ||
4901 | if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) | |
4902 | return false; | |
4903 | ||
4904 | vcpu->arch.last_retry_eip = ctxt->eip; | |
4905 | vcpu->arch.last_retry_addr = cr2; | |
4906 | ||
4907 | if (!vcpu->arch.mmu.direct_map) | |
4908 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); | |
4909 | ||
22368028 | 4910 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); |
1cb3f3ae XG |
4911 | |
4912 | return true; | |
4913 | } | |
4914 | ||
716d51ab GN |
4915 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu); |
4916 | static int complete_emulated_pio(struct kvm_vcpu *vcpu); | |
4917 | ||
51d8b661 AP |
4918 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, |
4919 | unsigned long cr2, | |
dc25e89e AP |
4920 | int emulation_type, |
4921 | void *insn, | |
4922 | int insn_len) | |
bbd9b64e | 4923 | { |
95cb2295 | 4924 | int r; |
9d74191a | 4925 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
7ae441ea | 4926 | bool writeback = true; |
93c05d3e | 4927 | bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; |
bbd9b64e | 4928 | |
93c05d3e XG |
4929 | /* |
4930 | * Clear write_fault_to_shadow_pgtable here to ensure it is | |
4931 | * never reused. | |
4932 | */ | |
4933 | vcpu->arch.write_fault_to_shadow_pgtable = false; | |
26eef70c | 4934 | kvm_clear_exception_queue(vcpu); |
8d7d8102 | 4935 | |
571008da | 4936 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
8ec4722d | 4937 | init_emulate_ctxt(vcpu); |
9d74191a TY |
4938 | ctxt->interruptibility = 0; |
4939 | ctxt->have_exception = false; | |
4940 | ctxt->perm_ok = false; | |
bbd9b64e | 4941 | |
9d74191a | 4942 | ctxt->only_vendor_specific_insn |
4005996e AK |
4943 | = emulation_type & EMULTYPE_TRAP_UD; |
4944 | ||
9d74191a | 4945 | r = x86_decode_insn(ctxt, insn, insn_len); |
bbd9b64e | 4946 | |
e46479f8 | 4947 | trace_kvm_emulate_insn_start(vcpu); |
f2b5756b | 4948 | ++vcpu->stat.insn_emulation; |
1d2887e2 | 4949 | if (r != EMULATION_OK) { |
4005996e AK |
4950 | if (emulation_type & EMULTYPE_TRAP_UD) |
4951 | return EMULATE_FAIL; | |
991eebf9 GN |
4952 | if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, |
4953 | emulation_type)) | |
bbd9b64e | 4954 | return EMULATE_DONE; |
6d77dbfc GN |
4955 | if (emulation_type & EMULTYPE_SKIP) |
4956 | return EMULATE_FAIL; | |
4957 | return handle_emulation_failure(vcpu); | |
bbd9b64e CO |
4958 | } |
4959 | } | |
4960 | ||
ba8afb6b | 4961 | if (emulation_type & EMULTYPE_SKIP) { |
9dac77fa | 4962 | kvm_rip_write(vcpu, ctxt->_eip); |
ba8afb6b GN |
4963 | return EMULATE_DONE; |
4964 | } | |
4965 | ||
1cb3f3ae XG |
4966 | if (retry_instruction(ctxt, cr2, emulation_type)) |
4967 | return EMULATE_DONE; | |
4968 | ||
7ae441ea | 4969 | /* this is needed for vmware backdoor interface to work since it |
4d2179e1 | 4970 | changes registers values during IO operation */ |
7ae441ea GN |
4971 | if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { |
4972 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; | |
dd856efa | 4973 | emulator_invalidate_register_cache(ctxt); |
7ae441ea | 4974 | } |
4d2179e1 | 4975 | |
5cd21917 | 4976 | restart: |
9d74191a | 4977 | r = x86_emulate_insn(ctxt); |
bbd9b64e | 4978 | |
775fde86 JR |
4979 | if (r == EMULATION_INTERCEPTED) |
4980 | return EMULATE_DONE; | |
4981 | ||
d2ddd1c4 | 4982 | if (r == EMULATION_FAILED) { |
991eebf9 GN |
4983 | if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, |
4984 | emulation_type)) | |
c3cd7ffa GN |
4985 | return EMULATE_DONE; |
4986 | ||
6d77dbfc | 4987 | return handle_emulation_failure(vcpu); |
bbd9b64e CO |
4988 | } |
4989 | ||
9d74191a | 4990 | if (ctxt->have_exception) { |
54b8486f | 4991 | inject_emulated_exception(vcpu); |
d2ddd1c4 GN |
4992 | r = EMULATE_DONE; |
4993 | } else if (vcpu->arch.pio.count) { | |
3457e419 GN |
4994 | if (!vcpu->arch.pio.in) |
4995 | vcpu->arch.pio.count = 0; | |
716d51ab | 4996 | else { |
7ae441ea | 4997 | writeback = false; |
716d51ab GN |
4998 | vcpu->arch.complete_userspace_io = complete_emulated_pio; |
4999 | } | |
e85d28f8 | 5000 | r = EMULATE_DO_MMIO; |
7ae441ea GN |
5001 | } else if (vcpu->mmio_needed) { |
5002 | if (!vcpu->mmio_is_write) | |
5003 | writeback = false; | |
e85d28f8 | 5004 | r = EMULATE_DO_MMIO; |
716d51ab | 5005 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; |
7ae441ea | 5006 | } else if (r == EMULATION_RESTART) |
5cd21917 | 5007 | goto restart; |
d2ddd1c4 GN |
5008 | else |
5009 | r = EMULATE_DONE; | |
f850e2e6 | 5010 | |
7ae441ea | 5011 | if (writeback) { |
9d74191a TY |
5012 | toggle_interruptibility(vcpu, ctxt->interruptibility); |
5013 | kvm_set_rflags(vcpu, ctxt->eflags); | |
7ae441ea | 5014 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
7ae441ea | 5015 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
9d74191a | 5016 | kvm_rip_write(vcpu, ctxt->eip); |
7ae441ea GN |
5017 | } else |
5018 | vcpu->arch.emulate_regs_need_sync_to_vcpu = true; | |
e85d28f8 GN |
5019 | |
5020 | return r; | |
de7d789a | 5021 | } |
51d8b661 | 5022 | EXPORT_SYMBOL_GPL(x86_emulate_instruction); |
de7d789a | 5023 | |
cf8f70bf | 5024 | int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port) |
de7d789a | 5025 | { |
cf8f70bf | 5026 | unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); |
ca1d4a9e AK |
5027 | int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, |
5028 | size, port, &val, 1); | |
cf8f70bf | 5029 | /* do not return to emulator after return from userspace */ |
7972995b | 5030 | vcpu->arch.pio.count = 0; |
de7d789a CO |
5031 | return ret; |
5032 | } | |
cf8f70bf | 5033 | EXPORT_SYMBOL_GPL(kvm_fast_pio_out); |
de7d789a | 5034 | |
8cfdc000 ZA |
5035 | static void tsc_bad(void *info) |
5036 | { | |
0a3aee0d | 5037 | __this_cpu_write(cpu_tsc_khz, 0); |
8cfdc000 ZA |
5038 | } |
5039 | ||
5040 | static void tsc_khz_changed(void *data) | |
c8076604 | 5041 | { |
8cfdc000 ZA |
5042 | struct cpufreq_freqs *freq = data; |
5043 | unsigned long khz = 0; | |
5044 | ||
5045 | if (data) | |
5046 | khz = freq->new; | |
5047 | else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
5048 | khz = cpufreq_quick_get(raw_smp_processor_id()); | |
5049 | if (!khz) | |
5050 | khz = tsc_khz; | |
0a3aee0d | 5051 | __this_cpu_write(cpu_tsc_khz, khz); |
c8076604 GH |
5052 | } |
5053 | ||
c8076604 GH |
5054 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, |
5055 | void *data) | |
5056 | { | |
5057 | struct cpufreq_freqs *freq = data; | |
5058 | struct kvm *kvm; | |
5059 | struct kvm_vcpu *vcpu; | |
5060 | int i, send_ipi = 0; | |
5061 | ||
8cfdc000 ZA |
5062 | /* |
5063 | * We allow guests to temporarily run on slowing clocks, | |
5064 | * provided we notify them after, or to run on accelerating | |
5065 | * clocks, provided we notify them before. Thus time never | |
5066 | * goes backwards. | |
5067 | * | |
5068 | * However, we have a problem. We can't atomically update | |
5069 | * the frequency of a given CPU from this function; it is | |
5070 | * merely a notifier, which can be called from any CPU. | |
5071 | * Changing the TSC frequency at arbitrary points in time | |
5072 | * requires a recomputation of local variables related to | |
5073 | * the TSC for each VCPU. We must flag these local variables | |
5074 | * to be updated and be sure the update takes place with the | |
5075 | * new frequency before any guests proceed. | |
5076 | * | |
5077 | * Unfortunately, the combination of hotplug CPU and frequency | |
5078 | * change creates an intractable locking scenario; the order | |
5079 | * of when these callouts happen is undefined with respect to | |
5080 | * CPU hotplug, and they can race with each other. As such, | |
5081 | * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is | |
5082 | * undefined; you can actually have a CPU frequency change take | |
5083 | * place in between the computation of X and the setting of the | |
5084 | * variable. To protect against this problem, all updates of | |
5085 | * the per_cpu tsc_khz variable are done in an interrupt | |
5086 | * protected IPI, and all callers wishing to update the value | |
5087 | * must wait for a synchronous IPI to complete (which is trivial | |
5088 | * if the caller is on the CPU already). This establishes the | |
5089 | * necessary total order on variable updates. | |
5090 | * | |
5091 | * Note that because a guest time update may take place | |
5092 | * anytime after the setting of the VCPU's request bit, the | |
5093 | * correct TSC value must be set before the request. However, | |
5094 | * to ensure the update actually makes it to any guest which | |
5095 | * starts running in hardware virtualization between the set | |
5096 | * and the acquisition of the spinlock, we must also ping the | |
5097 | * CPU after setting the request bit. | |
5098 | * | |
5099 | */ | |
5100 | ||
c8076604 GH |
5101 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) |
5102 | return 0; | |
5103 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
5104 | return 0; | |
8cfdc000 ZA |
5105 | |
5106 | smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); | |
c8076604 | 5107 | |
e935b837 | 5108 | raw_spin_lock(&kvm_lock); |
c8076604 | 5109 | list_for_each_entry(kvm, &vm_list, vm_list) { |
988a2cae | 5110 | kvm_for_each_vcpu(i, vcpu, kvm) { |
c8076604 GH |
5111 | if (vcpu->cpu != freq->cpu) |
5112 | continue; | |
c285545f | 5113 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
c8076604 | 5114 | if (vcpu->cpu != smp_processor_id()) |
8cfdc000 | 5115 | send_ipi = 1; |
c8076604 GH |
5116 | } |
5117 | } | |
e935b837 | 5118 | raw_spin_unlock(&kvm_lock); |
c8076604 GH |
5119 | |
5120 | if (freq->old < freq->new && send_ipi) { | |
5121 | /* | |
5122 | * We upscale the frequency. Must make the guest | |
5123 | * doesn't see old kvmclock values while running with | |
5124 | * the new frequency, otherwise we risk the guest sees | |
5125 | * time go backwards. | |
5126 | * | |
5127 | * In case we update the frequency for another cpu | |
5128 | * (which might be in guest context) send an interrupt | |
5129 | * to kick the cpu out of guest context. Next time | |
5130 | * guest context is entered kvmclock will be updated, | |
5131 | * so the guest will not see stale values. | |
5132 | */ | |
8cfdc000 | 5133 | smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); |
c8076604 GH |
5134 | } |
5135 | return 0; | |
5136 | } | |
5137 | ||
5138 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
8cfdc000 ZA |
5139 | .notifier_call = kvmclock_cpufreq_notifier |
5140 | }; | |
5141 | ||
5142 | static int kvmclock_cpu_notifier(struct notifier_block *nfb, | |
5143 | unsigned long action, void *hcpu) | |
5144 | { | |
5145 | unsigned int cpu = (unsigned long)hcpu; | |
5146 | ||
5147 | switch (action) { | |
5148 | case CPU_ONLINE: | |
5149 | case CPU_DOWN_FAILED: | |
5150 | smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); | |
5151 | break; | |
5152 | case CPU_DOWN_PREPARE: | |
5153 | smp_call_function_single(cpu, tsc_bad, NULL, 1); | |
5154 | break; | |
5155 | } | |
5156 | return NOTIFY_OK; | |
5157 | } | |
5158 | ||
5159 | static struct notifier_block kvmclock_cpu_notifier_block = { | |
5160 | .notifier_call = kvmclock_cpu_notifier, | |
5161 | .priority = -INT_MAX | |
c8076604 GH |
5162 | }; |
5163 | ||
b820cc0c ZA |
5164 | static void kvm_timer_init(void) |
5165 | { | |
5166 | int cpu; | |
5167 | ||
c285545f | 5168 | max_tsc_khz = tsc_khz; |
8cfdc000 | 5169 | register_hotcpu_notifier(&kvmclock_cpu_notifier_block); |
b820cc0c | 5170 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
c285545f ZA |
5171 | #ifdef CONFIG_CPU_FREQ |
5172 | struct cpufreq_policy policy; | |
5173 | memset(&policy, 0, sizeof(policy)); | |
3e26f230 AK |
5174 | cpu = get_cpu(); |
5175 | cpufreq_get_policy(&policy, cpu); | |
c285545f ZA |
5176 | if (policy.cpuinfo.max_freq) |
5177 | max_tsc_khz = policy.cpuinfo.max_freq; | |
3e26f230 | 5178 | put_cpu(); |
c285545f | 5179 | #endif |
b820cc0c ZA |
5180 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
5181 | CPUFREQ_TRANSITION_NOTIFIER); | |
5182 | } | |
c285545f | 5183 | pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); |
8cfdc000 ZA |
5184 | for_each_online_cpu(cpu) |
5185 | smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); | |
b820cc0c ZA |
5186 | } |
5187 | ||
ff9d07a0 ZY |
5188 | static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); |
5189 | ||
f5132b01 | 5190 | int kvm_is_in_guest(void) |
ff9d07a0 | 5191 | { |
086c9855 | 5192 | return __this_cpu_read(current_vcpu) != NULL; |
ff9d07a0 ZY |
5193 | } |
5194 | ||
5195 | static int kvm_is_user_mode(void) | |
5196 | { | |
5197 | int user_mode = 3; | |
dcf46b94 | 5198 | |
086c9855 AS |
5199 | if (__this_cpu_read(current_vcpu)) |
5200 | user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 5201 | |
ff9d07a0 ZY |
5202 | return user_mode != 0; |
5203 | } | |
5204 | ||
5205 | static unsigned long kvm_get_guest_ip(void) | |
5206 | { | |
5207 | unsigned long ip = 0; | |
dcf46b94 | 5208 | |
086c9855 AS |
5209 | if (__this_cpu_read(current_vcpu)) |
5210 | ip = kvm_rip_read(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 5211 | |
ff9d07a0 ZY |
5212 | return ip; |
5213 | } | |
5214 | ||
5215 | static struct perf_guest_info_callbacks kvm_guest_cbs = { | |
5216 | .is_in_guest = kvm_is_in_guest, | |
5217 | .is_user_mode = kvm_is_user_mode, | |
5218 | .get_guest_ip = kvm_get_guest_ip, | |
5219 | }; | |
5220 | ||
5221 | void kvm_before_handle_nmi(struct kvm_vcpu *vcpu) | |
5222 | { | |
086c9855 | 5223 | __this_cpu_write(current_vcpu, vcpu); |
ff9d07a0 ZY |
5224 | } |
5225 | EXPORT_SYMBOL_GPL(kvm_before_handle_nmi); | |
5226 | ||
5227 | void kvm_after_handle_nmi(struct kvm_vcpu *vcpu) | |
5228 | { | |
086c9855 | 5229 | __this_cpu_write(current_vcpu, NULL); |
ff9d07a0 ZY |
5230 | } |
5231 | EXPORT_SYMBOL_GPL(kvm_after_handle_nmi); | |
5232 | ||
ce88decf XG |
5233 | static void kvm_set_mmio_spte_mask(void) |
5234 | { | |
5235 | u64 mask; | |
5236 | int maxphyaddr = boot_cpu_data.x86_phys_bits; | |
5237 | ||
5238 | /* | |
5239 | * Set the reserved bits and the present bit of an paging-structure | |
5240 | * entry to generate page fault with PFER.RSV = 1. | |
5241 | */ | |
5242 | mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr; | |
5243 | mask |= 1ull; | |
5244 | ||
5245 | #ifdef CONFIG_X86_64 | |
5246 | /* | |
5247 | * If reserved bit is not supported, clear the present bit to disable | |
5248 | * mmio page fault. | |
5249 | */ | |
5250 | if (maxphyaddr == 52) | |
5251 | mask &= ~1ull; | |
5252 | #endif | |
5253 | ||
5254 | kvm_mmu_set_mmio_spte_mask(mask); | |
5255 | } | |
5256 | ||
16e8d74d MT |
5257 | #ifdef CONFIG_X86_64 |
5258 | static void pvclock_gtod_update_fn(struct work_struct *work) | |
5259 | { | |
d828199e MT |
5260 | struct kvm *kvm; |
5261 | ||
5262 | struct kvm_vcpu *vcpu; | |
5263 | int i; | |
5264 | ||
5265 | raw_spin_lock(&kvm_lock); | |
5266 | list_for_each_entry(kvm, &vm_list, vm_list) | |
5267 | kvm_for_each_vcpu(i, vcpu, kvm) | |
5268 | set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests); | |
5269 | atomic_set(&kvm_guest_has_master_clock, 0); | |
5270 | raw_spin_unlock(&kvm_lock); | |
16e8d74d MT |
5271 | } |
5272 | ||
5273 | static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); | |
5274 | ||
5275 | /* | |
5276 | * Notification about pvclock gtod data update. | |
5277 | */ | |
5278 | static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, | |
5279 | void *priv) | |
5280 | { | |
5281 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
5282 | struct timekeeper *tk = priv; | |
5283 | ||
5284 | update_pvclock_gtod(tk); | |
5285 | ||
5286 | /* disable master clock if host does not trust, or does not | |
5287 | * use, TSC clocksource | |
5288 | */ | |
5289 | if (gtod->clock.vclock_mode != VCLOCK_TSC && | |
5290 | atomic_read(&kvm_guest_has_master_clock) != 0) | |
5291 | queue_work(system_long_wq, &pvclock_gtod_work); | |
5292 | ||
5293 | return 0; | |
5294 | } | |
5295 | ||
5296 | static struct notifier_block pvclock_gtod_notifier = { | |
5297 | .notifier_call = pvclock_gtod_notify, | |
5298 | }; | |
5299 | #endif | |
5300 | ||
f8c16bba | 5301 | int kvm_arch_init(void *opaque) |
043405e1 | 5302 | { |
b820cc0c | 5303 | int r; |
f8c16bba ZX |
5304 | struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque; |
5305 | ||
f8c16bba ZX |
5306 | if (kvm_x86_ops) { |
5307 | printk(KERN_ERR "kvm: already loaded the other module\n"); | |
56c6d28a ZX |
5308 | r = -EEXIST; |
5309 | goto out; | |
f8c16bba ZX |
5310 | } |
5311 | ||
5312 | if (!ops->cpu_has_kvm_support()) { | |
5313 | printk(KERN_ERR "kvm: no hardware support\n"); | |
56c6d28a ZX |
5314 | r = -EOPNOTSUPP; |
5315 | goto out; | |
f8c16bba ZX |
5316 | } |
5317 | if (ops->disabled_by_bios()) { | |
5318 | printk(KERN_ERR "kvm: disabled by bios\n"); | |
56c6d28a ZX |
5319 | r = -EOPNOTSUPP; |
5320 | goto out; | |
f8c16bba ZX |
5321 | } |
5322 | ||
013f6a5d MT |
5323 | r = -ENOMEM; |
5324 | shared_msrs = alloc_percpu(struct kvm_shared_msrs); | |
5325 | if (!shared_msrs) { | |
5326 | printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); | |
5327 | goto out; | |
5328 | } | |
5329 | ||
97db56ce AK |
5330 | r = kvm_mmu_module_init(); |
5331 | if (r) | |
013f6a5d | 5332 | goto out_free_percpu; |
97db56ce | 5333 | |
ce88decf | 5334 | kvm_set_mmio_spte_mask(); |
97db56ce AK |
5335 | kvm_init_msr_list(); |
5336 | ||
f8c16bba | 5337 | kvm_x86_ops = ops; |
7b52345e | 5338 | kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, |
4b12f0de | 5339 | PT_DIRTY_MASK, PT64_NX_MASK, 0); |
c8076604 | 5340 | |
b820cc0c | 5341 | kvm_timer_init(); |
c8076604 | 5342 | |
ff9d07a0 ZY |
5343 | perf_register_guest_info_callbacks(&kvm_guest_cbs); |
5344 | ||
2acf923e DC |
5345 | if (cpu_has_xsave) |
5346 | host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); | |
5347 | ||
c5cc421b | 5348 | kvm_lapic_init(); |
16e8d74d MT |
5349 | #ifdef CONFIG_X86_64 |
5350 | pvclock_gtod_register_notifier(&pvclock_gtod_notifier); | |
5351 | #endif | |
5352 | ||
f8c16bba | 5353 | return 0; |
56c6d28a | 5354 | |
013f6a5d MT |
5355 | out_free_percpu: |
5356 | free_percpu(shared_msrs); | |
56c6d28a | 5357 | out: |
56c6d28a | 5358 | return r; |
043405e1 | 5359 | } |
8776e519 | 5360 | |
f8c16bba ZX |
5361 | void kvm_arch_exit(void) |
5362 | { | |
ff9d07a0 ZY |
5363 | perf_unregister_guest_info_callbacks(&kvm_guest_cbs); |
5364 | ||
888d256e JK |
5365 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
5366 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
5367 | CPUFREQ_TRANSITION_NOTIFIER); | |
8cfdc000 | 5368 | unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block); |
16e8d74d MT |
5369 | #ifdef CONFIG_X86_64 |
5370 | pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); | |
5371 | #endif | |
f8c16bba | 5372 | kvm_x86_ops = NULL; |
56c6d28a | 5373 | kvm_mmu_module_exit(); |
013f6a5d | 5374 | free_percpu(shared_msrs); |
56c6d28a | 5375 | } |
f8c16bba | 5376 | |
8776e519 HB |
5377 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) |
5378 | { | |
5379 | ++vcpu->stat.halt_exits; | |
5380 | if (irqchip_in_kernel(vcpu->kvm)) { | |
a4535290 | 5381 | vcpu->arch.mp_state = KVM_MP_STATE_HALTED; |
8776e519 HB |
5382 | return 1; |
5383 | } else { | |
5384 | vcpu->run->exit_reason = KVM_EXIT_HLT; | |
5385 | return 0; | |
5386 | } | |
5387 | } | |
5388 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); | |
5389 | ||
55cd8e5a GN |
5390 | int kvm_hv_hypercall(struct kvm_vcpu *vcpu) |
5391 | { | |
5392 | u64 param, ingpa, outgpa, ret; | |
5393 | uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0; | |
5394 | bool fast, longmode; | |
5395 | int cs_db, cs_l; | |
5396 | ||
5397 | /* | |
5398 | * hypercall generates UD from non zero cpl and real mode | |
5399 | * per HYPER-V spec | |
5400 | */ | |
3eeb3288 | 5401 | if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) { |
55cd8e5a GN |
5402 | kvm_queue_exception(vcpu, UD_VECTOR); |
5403 | return 0; | |
5404 | } | |
5405 | ||
5406 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
5407 | longmode = is_long_mode(vcpu) && cs_l == 1; | |
5408 | ||
5409 | if (!longmode) { | |
ccd46936 GN |
5410 | param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) | |
5411 | (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff); | |
5412 | ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) | | |
5413 | (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff); | |
5414 | outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) | | |
5415 | (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff); | |
55cd8e5a GN |
5416 | } |
5417 | #ifdef CONFIG_X86_64 | |
5418 | else { | |
5419 | param = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
5420 | ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
5421 | outgpa = kvm_register_read(vcpu, VCPU_REGS_R8); | |
5422 | } | |
5423 | #endif | |
5424 | ||
5425 | code = param & 0xffff; | |
5426 | fast = (param >> 16) & 0x1; | |
5427 | rep_cnt = (param >> 32) & 0xfff; | |
5428 | rep_idx = (param >> 48) & 0xfff; | |
5429 | ||
5430 | trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa); | |
5431 | ||
c25bc163 GN |
5432 | switch (code) { |
5433 | case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT: | |
5434 | kvm_vcpu_on_spin(vcpu); | |
5435 | break; | |
5436 | default: | |
5437 | res = HV_STATUS_INVALID_HYPERCALL_CODE; | |
5438 | break; | |
5439 | } | |
55cd8e5a GN |
5440 | |
5441 | ret = res | (((u64)rep_done & 0xfff) << 32); | |
5442 | if (longmode) { | |
5443 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); | |
5444 | } else { | |
5445 | kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32); | |
5446 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff); | |
5447 | } | |
5448 | ||
5449 | return 1; | |
5450 | } | |
5451 | ||
8776e519 HB |
5452 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
5453 | { | |
5454 | unsigned long nr, a0, a1, a2, a3, ret; | |
2f333bcb | 5455 | int r = 1; |
8776e519 | 5456 | |
55cd8e5a GN |
5457 | if (kvm_hv_hypercall_enabled(vcpu->kvm)) |
5458 | return kvm_hv_hypercall(vcpu); | |
5459 | ||
5fdbf976 MT |
5460 | nr = kvm_register_read(vcpu, VCPU_REGS_RAX); |
5461 | a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
5462 | a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
5463 | a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
5464 | a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
8776e519 | 5465 | |
229456fc | 5466 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 5467 | |
8776e519 HB |
5468 | if (!is_long_mode(vcpu)) { |
5469 | nr &= 0xFFFFFFFF; | |
5470 | a0 &= 0xFFFFFFFF; | |
5471 | a1 &= 0xFFFFFFFF; | |
5472 | a2 &= 0xFFFFFFFF; | |
5473 | a3 &= 0xFFFFFFFF; | |
5474 | } | |
5475 | ||
07708c4a JK |
5476 | if (kvm_x86_ops->get_cpl(vcpu) != 0) { |
5477 | ret = -KVM_EPERM; | |
5478 | goto out; | |
5479 | } | |
5480 | ||
8776e519 | 5481 | switch (nr) { |
b93463aa AK |
5482 | case KVM_HC_VAPIC_POLL_IRQ: |
5483 | ret = 0; | |
5484 | break; | |
8776e519 HB |
5485 | default: |
5486 | ret = -KVM_ENOSYS; | |
5487 | break; | |
5488 | } | |
07708c4a | 5489 | out: |
5fdbf976 | 5490 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); |
f11c3a8d | 5491 | ++vcpu->stat.hypercalls; |
2f333bcb | 5492 | return r; |
8776e519 HB |
5493 | } |
5494 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
5495 | ||
b6785def | 5496 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) |
8776e519 | 5497 | { |
d6aa1000 | 5498 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
8776e519 | 5499 | char instruction[3]; |
5fdbf976 | 5500 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 5501 | |
8776e519 HB |
5502 | /* |
5503 | * Blow out the MMU to ensure that no other VCPU has an active mapping | |
5504 | * to ensure that the updated hypercall appears atomically across all | |
5505 | * VCPUs. | |
5506 | */ | |
5507 | kvm_mmu_zap_all(vcpu->kvm); | |
5508 | ||
8776e519 | 5509 | kvm_x86_ops->patch_hypercall(vcpu, instruction); |
8776e519 | 5510 | |
9d74191a | 5511 | return emulator_write_emulated(ctxt, rip, instruction, 3, NULL); |
8776e519 HB |
5512 | } |
5513 | ||
b6c7a5dc HB |
5514 | /* |
5515 | * Check if userspace requested an interrupt window, and that the | |
5516 | * interrupt window is open. | |
5517 | * | |
5518 | * No need to exit to userspace if we already have an interrupt queued. | |
5519 | */ | |
851ba692 | 5520 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 5521 | { |
8061823a | 5522 | return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) && |
851ba692 | 5523 | vcpu->run->request_interrupt_window && |
5df56646 | 5524 | kvm_arch_interrupt_allowed(vcpu)); |
b6c7a5dc HB |
5525 | } |
5526 | ||
851ba692 | 5527 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 5528 | { |
851ba692 AK |
5529 | struct kvm_run *kvm_run = vcpu->run; |
5530 | ||
91586a3b | 5531 | kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; |
2d3ad1f4 | 5532 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 5533 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
4531220b | 5534 | if (irqchip_in_kernel(vcpu->kvm)) |
b6c7a5dc | 5535 | kvm_run->ready_for_interrupt_injection = 1; |
4531220b | 5536 | else |
b6c7a5dc | 5537 | kvm_run->ready_for_interrupt_injection = |
fa9726b0 GN |
5538 | kvm_arch_interrupt_allowed(vcpu) && |
5539 | !kvm_cpu_has_interrupt(vcpu) && | |
5540 | !kvm_event_needs_reinjection(vcpu); | |
b6c7a5dc HB |
5541 | } |
5542 | ||
4484141a | 5543 | static int vapic_enter(struct kvm_vcpu *vcpu) |
b93463aa AK |
5544 | { |
5545 | struct kvm_lapic *apic = vcpu->arch.apic; | |
5546 | struct page *page; | |
5547 | ||
5548 | if (!apic || !apic->vapic_addr) | |
4484141a | 5549 | return 0; |
b93463aa AK |
5550 | |
5551 | page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT); | |
4484141a XG |
5552 | if (is_error_page(page)) |
5553 | return -EFAULT; | |
72dc67a6 IE |
5554 | |
5555 | vcpu->arch.apic->vapic_page = page; | |
4484141a | 5556 | return 0; |
b93463aa AK |
5557 | } |
5558 | ||
5559 | static void vapic_exit(struct kvm_vcpu *vcpu) | |
5560 | { | |
5561 | struct kvm_lapic *apic = vcpu->arch.apic; | |
f656ce01 | 5562 | int idx; |
b93463aa AK |
5563 | |
5564 | if (!apic || !apic->vapic_addr) | |
5565 | return; | |
5566 | ||
f656ce01 | 5567 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
b93463aa AK |
5568 | kvm_release_page_dirty(apic->vapic_page); |
5569 | mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT); | |
f656ce01 | 5570 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b93463aa AK |
5571 | } |
5572 | ||
95ba8273 GN |
5573 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
5574 | { | |
5575 | int max_irr, tpr; | |
5576 | ||
5577 | if (!kvm_x86_ops->update_cr8_intercept) | |
5578 | return; | |
5579 | ||
88c808fd AK |
5580 | if (!vcpu->arch.apic) |
5581 | return; | |
5582 | ||
8db3baa2 GN |
5583 | if (!vcpu->arch.apic->vapic_addr) |
5584 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
5585 | else | |
5586 | max_irr = -1; | |
95ba8273 GN |
5587 | |
5588 | if (max_irr != -1) | |
5589 | max_irr >>= 4; | |
5590 | ||
5591 | tpr = kvm_lapic_get_cr8(vcpu); | |
5592 | ||
5593 | kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); | |
5594 | } | |
5595 | ||
851ba692 | 5596 | static void inject_pending_event(struct kvm_vcpu *vcpu) |
95ba8273 GN |
5597 | { |
5598 | /* try to reinject previous events if any */ | |
b59bb7bd | 5599 | if (vcpu->arch.exception.pending) { |
5c1c85d0 AK |
5600 | trace_kvm_inj_exception(vcpu->arch.exception.nr, |
5601 | vcpu->arch.exception.has_error_code, | |
5602 | vcpu->arch.exception.error_code); | |
b59bb7bd GN |
5603 | kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, |
5604 | vcpu->arch.exception.has_error_code, | |
ce7ddec4 JR |
5605 | vcpu->arch.exception.error_code, |
5606 | vcpu->arch.exception.reinject); | |
b59bb7bd GN |
5607 | return; |
5608 | } | |
5609 | ||
95ba8273 GN |
5610 | if (vcpu->arch.nmi_injected) { |
5611 | kvm_x86_ops->set_nmi(vcpu); | |
5612 | return; | |
5613 | } | |
5614 | ||
5615 | if (vcpu->arch.interrupt.pending) { | |
66fd3f7f | 5616 | kvm_x86_ops->set_irq(vcpu); |
95ba8273 GN |
5617 | return; |
5618 | } | |
5619 | ||
5620 | /* try to inject new event if pending */ | |
5621 | if (vcpu->arch.nmi_pending) { | |
5622 | if (kvm_x86_ops->nmi_allowed(vcpu)) { | |
7460fb4a | 5623 | --vcpu->arch.nmi_pending; |
95ba8273 GN |
5624 | vcpu->arch.nmi_injected = true; |
5625 | kvm_x86_ops->set_nmi(vcpu); | |
5626 | } | |
c7c9c56c | 5627 | } else if (kvm_cpu_has_injectable_intr(vcpu)) { |
95ba8273 | 5628 | if (kvm_x86_ops->interrupt_allowed(vcpu)) { |
66fd3f7f GN |
5629 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), |
5630 | false); | |
5631 | kvm_x86_ops->set_irq(vcpu); | |
95ba8273 GN |
5632 | } |
5633 | } | |
5634 | } | |
5635 | ||
7460fb4a AK |
5636 | static void process_nmi(struct kvm_vcpu *vcpu) |
5637 | { | |
5638 | unsigned limit = 2; | |
5639 | ||
5640 | /* | |
5641 | * x86 is limited to one NMI running, and one NMI pending after it. | |
5642 | * If an NMI is already in progress, limit further NMIs to just one. | |
5643 | * Otherwise, allow two (and we'll inject the first one immediately). | |
5644 | */ | |
5645 | if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) | |
5646 | limit = 1; | |
5647 | ||
5648 | vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); | |
5649 | vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); | |
5650 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
5651 | } | |
5652 | ||
d828199e MT |
5653 | static void kvm_gen_update_masterclock(struct kvm *kvm) |
5654 | { | |
5655 | #ifdef CONFIG_X86_64 | |
5656 | int i; | |
5657 | struct kvm_vcpu *vcpu; | |
5658 | struct kvm_arch *ka = &kvm->arch; | |
5659 | ||
5660 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
5661 | kvm_make_mclock_inprogress_request(kvm); | |
5662 | /* no guest entries from this point */ | |
5663 | pvclock_update_vm_gtod_copy(kvm); | |
5664 | ||
5665 | kvm_for_each_vcpu(i, vcpu, kvm) | |
5666 | set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests); | |
5667 | ||
5668 | /* guest entries allowed */ | |
5669 | kvm_for_each_vcpu(i, vcpu, kvm) | |
5670 | clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests); | |
5671 | ||
5672 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
5673 | #endif | |
5674 | } | |
5675 | ||
3d81bc7e | 5676 | static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) |
c7c9c56c YZ |
5677 | { |
5678 | u64 eoi_exit_bitmap[4]; | |
cf9e65b7 | 5679 | u32 tmr[8]; |
c7c9c56c | 5680 | |
3d81bc7e YZ |
5681 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) |
5682 | return; | |
c7c9c56c YZ |
5683 | |
5684 | memset(eoi_exit_bitmap, 0, 32); | |
cf9e65b7 | 5685 | memset(tmr, 0, 32); |
c7c9c56c | 5686 | |
cf9e65b7 | 5687 | kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr); |
c7c9c56c | 5688 | kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); |
cf9e65b7 | 5689 | kvm_apic_update_tmr(vcpu, tmr); |
c7c9c56c YZ |
5690 | } |
5691 | ||
851ba692 | 5692 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
5693 | { |
5694 | int r; | |
6a8b1d13 | 5695 | bool req_int_win = !irqchip_in_kernel(vcpu->kvm) && |
851ba692 | 5696 | vcpu->run->request_interrupt_window; |
730dca42 | 5697 | bool req_immediate_exit = false; |
b6c7a5dc | 5698 | |
3e007509 | 5699 | if (vcpu->requests) { |
a8eeb04a | 5700 | if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) |
2e53d63a | 5701 | kvm_mmu_unload(vcpu); |
a8eeb04a | 5702 | if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) |
2f599714 | 5703 | __kvm_migrate_timers(vcpu); |
d828199e MT |
5704 | if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) |
5705 | kvm_gen_update_masterclock(vcpu->kvm); | |
34c238a1 ZA |
5706 | if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { |
5707 | r = kvm_guest_time_update(vcpu); | |
8cfdc000 ZA |
5708 | if (unlikely(r)) |
5709 | goto out; | |
5710 | } | |
a8eeb04a | 5711 | if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) |
4731d4c7 | 5712 | kvm_mmu_sync_roots(vcpu); |
a8eeb04a | 5713 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) |
d4acf7e7 | 5714 | kvm_x86_ops->tlb_flush(vcpu); |
a8eeb04a | 5715 | if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { |
851ba692 | 5716 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
5717 | r = 0; |
5718 | goto out; | |
5719 | } | |
a8eeb04a | 5720 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
851ba692 | 5721 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
71c4dfaf JR |
5722 | r = 0; |
5723 | goto out; | |
5724 | } | |
a8eeb04a | 5725 | if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) { |
02daab21 AK |
5726 | vcpu->fpu_active = 0; |
5727 | kvm_x86_ops->fpu_deactivate(vcpu); | |
5728 | } | |
af585b92 GN |
5729 | if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { |
5730 | /* Page is swapped out. Do synthetic halt */ | |
5731 | vcpu->arch.apf.halted = true; | |
5732 | r = 1; | |
5733 | goto out; | |
5734 | } | |
c9aaa895 GC |
5735 | if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) |
5736 | record_steal_time(vcpu); | |
7460fb4a AK |
5737 | if (kvm_check_request(KVM_REQ_NMI, vcpu)) |
5738 | process_nmi(vcpu); | |
f5132b01 GN |
5739 | if (kvm_check_request(KVM_REQ_PMU, vcpu)) |
5740 | kvm_handle_pmu_event(vcpu); | |
5741 | if (kvm_check_request(KVM_REQ_PMI, vcpu)) | |
5742 | kvm_deliver_pmi(vcpu); | |
3d81bc7e YZ |
5743 | if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) |
5744 | vcpu_scan_ioapic(vcpu); | |
2f52d58c | 5745 | } |
b93463aa | 5746 | |
b463a6f7 | 5747 | if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { |
66450a21 JK |
5748 | kvm_apic_accept_events(vcpu); |
5749 | if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { | |
5750 | r = 1; | |
5751 | goto out; | |
5752 | } | |
5753 | ||
b463a6f7 AK |
5754 | inject_pending_event(vcpu); |
5755 | ||
5756 | /* enable NMI/IRQ window open exits if needed */ | |
7460fb4a | 5757 | if (vcpu->arch.nmi_pending) |
03b28f81 JK |
5758 | req_immediate_exit = |
5759 | kvm_x86_ops->enable_nmi_window(vcpu) != 0; | |
c7c9c56c | 5760 | else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) |
730dca42 JK |
5761 | req_immediate_exit = |
5762 | kvm_x86_ops->enable_irq_window(vcpu) != 0; | |
b463a6f7 AK |
5763 | |
5764 | if (kvm_lapic_enabled(vcpu)) { | |
c7c9c56c YZ |
5765 | /* |
5766 | * Update architecture specific hints for APIC | |
5767 | * virtual interrupt delivery. | |
5768 | */ | |
5769 | if (kvm_x86_ops->hwapic_irr_update) | |
5770 | kvm_x86_ops->hwapic_irr_update(vcpu, | |
5771 | kvm_lapic_find_highest_irr(vcpu)); | |
b463a6f7 AK |
5772 | update_cr8_intercept(vcpu); |
5773 | kvm_lapic_sync_to_vapic(vcpu); | |
5774 | } | |
5775 | } | |
5776 | ||
d8368af8 AK |
5777 | r = kvm_mmu_reload(vcpu); |
5778 | if (unlikely(r)) { | |
d905c069 | 5779 | goto cancel_injection; |
d8368af8 AK |
5780 | } |
5781 | ||
b6c7a5dc HB |
5782 | preempt_disable(); |
5783 | ||
5784 | kvm_x86_ops->prepare_guest_switch(vcpu); | |
2608d7a1 AK |
5785 | if (vcpu->fpu_active) |
5786 | kvm_load_guest_fpu(vcpu); | |
2acf923e | 5787 | kvm_load_guest_xcr0(vcpu); |
b6c7a5dc | 5788 | |
6b7e2d09 XG |
5789 | vcpu->mode = IN_GUEST_MODE; |
5790 | ||
5791 | /* We should set ->mode before check ->requests, | |
5792 | * see the comment in make_all_cpus_request. | |
5793 | */ | |
5794 | smp_mb(); | |
b6c7a5dc | 5795 | |
d94e1dc9 | 5796 | local_irq_disable(); |
32f88400 | 5797 | |
6b7e2d09 | 5798 | if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests |
d94e1dc9 | 5799 | || need_resched() || signal_pending(current)) { |
6b7e2d09 | 5800 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 5801 | smp_wmb(); |
6c142801 AK |
5802 | local_irq_enable(); |
5803 | preempt_enable(); | |
5804 | r = 1; | |
d905c069 | 5805 | goto cancel_injection; |
6c142801 AK |
5806 | } |
5807 | ||
f656ce01 | 5808 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
3200f405 | 5809 | |
d6185f20 NHE |
5810 | if (req_immediate_exit) |
5811 | smp_send_reschedule(vcpu->cpu); | |
5812 | ||
b6c7a5dc HB |
5813 | kvm_guest_enter(); |
5814 | ||
42dbaa5a | 5815 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
5816 | set_debugreg(0, 7); |
5817 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
5818 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
5819 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
5820 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
5821 | } | |
b6c7a5dc | 5822 | |
229456fc | 5823 | trace_kvm_entry(vcpu->vcpu_id); |
851ba692 | 5824 | kvm_x86_ops->run(vcpu); |
b6c7a5dc | 5825 | |
24f1e32c FW |
5826 | /* |
5827 | * If the guest has used debug registers, at least dr7 | |
5828 | * will be disabled while returning to the host. | |
5829 | * If we don't have active breakpoints in the host, we don't | |
5830 | * care about the messed up debug address registers. But if | |
5831 | * we have some of them active, restore the old state. | |
5832 | */ | |
59d8eb53 | 5833 | if (hw_breakpoint_active()) |
24f1e32c | 5834 | hw_breakpoint_restore(); |
42dbaa5a | 5835 | |
886b470c MT |
5836 | vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, |
5837 | native_read_tsc()); | |
1d5f066e | 5838 | |
6b7e2d09 | 5839 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 5840 | smp_wmb(); |
a547c6db YZ |
5841 | |
5842 | /* Interrupt is enabled by handle_external_intr() */ | |
5843 | kvm_x86_ops->handle_external_intr(vcpu); | |
b6c7a5dc HB |
5844 | |
5845 | ++vcpu->stat.exits; | |
5846 | ||
5847 | /* | |
5848 | * We must have an instruction between local_irq_enable() and | |
5849 | * kvm_guest_exit(), so the timer interrupt isn't delayed by | |
5850 | * the interrupt shadow. The stat.exits increment will do nicely. | |
5851 | * But we need to prevent reordering, hence this barrier(): | |
5852 | */ | |
5853 | barrier(); | |
5854 | ||
5855 | kvm_guest_exit(); | |
5856 | ||
5857 | preempt_enable(); | |
5858 | ||
f656ce01 | 5859 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
3200f405 | 5860 | |
b6c7a5dc HB |
5861 | /* |
5862 | * Profile KVM exit RIPs: | |
5863 | */ | |
5864 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
5865 | unsigned long rip = kvm_rip_read(vcpu); |
5866 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
5867 | } |
5868 | ||
cc578287 ZA |
5869 | if (unlikely(vcpu->arch.tsc_always_catchup)) |
5870 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
298101da | 5871 | |
5cfb1d5a MT |
5872 | if (vcpu->arch.apic_attention) |
5873 | kvm_lapic_sync_from_vapic(vcpu); | |
b93463aa | 5874 | |
851ba692 | 5875 | r = kvm_x86_ops->handle_exit(vcpu); |
d905c069 MT |
5876 | return r; |
5877 | ||
5878 | cancel_injection: | |
5879 | kvm_x86_ops->cancel_injection(vcpu); | |
ae7a2a3f MT |
5880 | if (unlikely(vcpu->arch.apic_attention)) |
5881 | kvm_lapic_sync_from_vapic(vcpu); | |
d7690175 MT |
5882 | out: |
5883 | return r; | |
5884 | } | |
b6c7a5dc | 5885 | |
09cec754 | 5886 | |
851ba692 | 5887 | static int __vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
5888 | { |
5889 | int r; | |
f656ce01 | 5890 | struct kvm *kvm = vcpu->kvm; |
d7690175 | 5891 | |
f656ce01 | 5892 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
4484141a XG |
5893 | r = vapic_enter(vcpu); |
5894 | if (r) { | |
5895 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); | |
5896 | return r; | |
5897 | } | |
d7690175 MT |
5898 | |
5899 | r = 1; | |
5900 | while (r > 0) { | |
af585b92 GN |
5901 | if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
5902 | !vcpu->arch.apf.halted) | |
851ba692 | 5903 | r = vcpu_enter_guest(vcpu); |
d7690175 | 5904 | else { |
f656ce01 | 5905 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
d7690175 | 5906 | kvm_vcpu_block(vcpu); |
f656ce01 | 5907 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
66450a21 JK |
5908 | if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) { |
5909 | kvm_apic_accept_events(vcpu); | |
09cec754 GN |
5910 | switch(vcpu->arch.mp_state) { |
5911 | case KVM_MP_STATE_HALTED: | |
d7690175 | 5912 | vcpu->arch.mp_state = |
09cec754 GN |
5913 | KVM_MP_STATE_RUNNABLE; |
5914 | case KVM_MP_STATE_RUNNABLE: | |
af585b92 | 5915 | vcpu->arch.apf.halted = false; |
09cec754 | 5916 | break; |
66450a21 JK |
5917 | case KVM_MP_STATE_INIT_RECEIVED: |
5918 | break; | |
09cec754 GN |
5919 | default: |
5920 | r = -EINTR; | |
5921 | break; | |
5922 | } | |
5923 | } | |
d7690175 MT |
5924 | } |
5925 | ||
09cec754 GN |
5926 | if (r <= 0) |
5927 | break; | |
5928 | ||
5929 | clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); | |
5930 | if (kvm_cpu_has_pending_timer(vcpu)) | |
5931 | kvm_inject_pending_timer_irqs(vcpu); | |
5932 | ||
851ba692 | 5933 | if (dm_request_for_irq_injection(vcpu)) { |
09cec754 | 5934 | r = -EINTR; |
851ba692 | 5935 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 GN |
5936 | ++vcpu->stat.request_irq_exits; |
5937 | } | |
af585b92 GN |
5938 | |
5939 | kvm_check_async_pf_completion(vcpu); | |
5940 | ||
09cec754 GN |
5941 | if (signal_pending(current)) { |
5942 | r = -EINTR; | |
851ba692 | 5943 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 GN |
5944 | ++vcpu->stat.signal_exits; |
5945 | } | |
5946 | if (need_resched()) { | |
f656ce01 | 5947 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
09cec754 | 5948 | kvm_resched(vcpu); |
f656ce01 | 5949 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 5950 | } |
b6c7a5dc HB |
5951 | } |
5952 | ||
f656ce01 | 5953 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
b6c7a5dc | 5954 | |
b93463aa AK |
5955 | vapic_exit(vcpu); |
5956 | ||
b6c7a5dc HB |
5957 | return r; |
5958 | } | |
5959 | ||
716d51ab GN |
5960 | static inline int complete_emulated_io(struct kvm_vcpu *vcpu) |
5961 | { | |
5962 | int r; | |
5963 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); | |
5964 | r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE); | |
5965 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); | |
5966 | if (r != EMULATE_DONE) | |
5967 | return 0; | |
5968 | return 1; | |
5969 | } | |
5970 | ||
5971 | static int complete_emulated_pio(struct kvm_vcpu *vcpu) | |
5972 | { | |
5973 | BUG_ON(!vcpu->arch.pio.count); | |
5974 | ||
5975 | return complete_emulated_io(vcpu); | |
5976 | } | |
5977 | ||
f78146b0 AK |
5978 | /* |
5979 | * Implements the following, as a state machine: | |
5980 | * | |
5981 | * read: | |
5982 | * for each fragment | |
87da7e66 XG |
5983 | * for each mmio piece in the fragment |
5984 | * write gpa, len | |
5985 | * exit | |
5986 | * copy data | |
f78146b0 AK |
5987 | * execute insn |
5988 | * | |
5989 | * write: | |
5990 | * for each fragment | |
87da7e66 XG |
5991 | * for each mmio piece in the fragment |
5992 | * write gpa, len | |
5993 | * copy data | |
5994 | * exit | |
f78146b0 | 5995 | */ |
716d51ab | 5996 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu) |
5287f194 AK |
5997 | { |
5998 | struct kvm_run *run = vcpu->run; | |
f78146b0 | 5999 | struct kvm_mmio_fragment *frag; |
87da7e66 | 6000 | unsigned len; |
5287f194 | 6001 | |
716d51ab | 6002 | BUG_ON(!vcpu->mmio_needed); |
5287f194 | 6003 | |
716d51ab | 6004 | /* Complete previous fragment */ |
87da7e66 XG |
6005 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; |
6006 | len = min(8u, frag->len); | |
716d51ab | 6007 | if (!vcpu->mmio_is_write) |
87da7e66 XG |
6008 | memcpy(frag->data, run->mmio.data, len); |
6009 | ||
6010 | if (frag->len <= 8) { | |
6011 | /* Switch to the next fragment. */ | |
6012 | frag++; | |
6013 | vcpu->mmio_cur_fragment++; | |
6014 | } else { | |
6015 | /* Go forward to the next mmio piece. */ | |
6016 | frag->data += len; | |
6017 | frag->gpa += len; | |
6018 | frag->len -= len; | |
6019 | } | |
6020 | ||
716d51ab GN |
6021 | if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) { |
6022 | vcpu->mmio_needed = 0; | |
cef4dea0 | 6023 | if (vcpu->mmio_is_write) |
716d51ab GN |
6024 | return 1; |
6025 | vcpu->mmio_read_completed = 1; | |
6026 | return complete_emulated_io(vcpu); | |
6027 | } | |
87da7e66 | 6028 | |
716d51ab GN |
6029 | run->exit_reason = KVM_EXIT_MMIO; |
6030 | run->mmio.phys_addr = frag->gpa; | |
6031 | if (vcpu->mmio_is_write) | |
87da7e66 XG |
6032 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); |
6033 | run->mmio.len = min(8u, frag->len); | |
716d51ab GN |
6034 | run->mmio.is_write = vcpu->mmio_is_write; |
6035 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; | |
6036 | return 0; | |
5287f194 AK |
6037 | } |
6038 | ||
716d51ab | 6039 | |
b6c7a5dc HB |
6040 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
6041 | { | |
6042 | int r; | |
6043 | sigset_t sigsaved; | |
6044 | ||
e5c30142 AK |
6045 | if (!tsk_used_math(current) && init_fpu(current)) |
6046 | return -ENOMEM; | |
6047 | ||
ac9f6dc0 AK |
6048 | if (vcpu->sigset_active) |
6049 | sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); | |
6050 | ||
a4535290 | 6051 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
b6c7a5dc | 6052 | kvm_vcpu_block(vcpu); |
66450a21 | 6053 | kvm_apic_accept_events(vcpu); |
d7690175 | 6054 | clear_bit(KVM_REQ_UNHALT, &vcpu->requests); |
ac9f6dc0 AK |
6055 | r = -EAGAIN; |
6056 | goto out; | |
b6c7a5dc HB |
6057 | } |
6058 | ||
b6c7a5dc | 6059 | /* re-sync apic's tpr */ |
eea1cff9 AP |
6060 | if (!irqchip_in_kernel(vcpu->kvm)) { |
6061 | if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { | |
6062 | r = -EINVAL; | |
6063 | goto out; | |
6064 | } | |
6065 | } | |
b6c7a5dc | 6066 | |
716d51ab GN |
6067 | if (unlikely(vcpu->arch.complete_userspace_io)) { |
6068 | int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; | |
6069 | vcpu->arch.complete_userspace_io = NULL; | |
6070 | r = cui(vcpu); | |
6071 | if (r <= 0) | |
6072 | goto out; | |
6073 | } else | |
6074 | WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); | |
5287f194 | 6075 | |
851ba692 | 6076 | r = __vcpu_run(vcpu); |
b6c7a5dc HB |
6077 | |
6078 | out: | |
f1d86e46 | 6079 | post_kvm_run_save(vcpu); |
b6c7a5dc HB |
6080 | if (vcpu->sigset_active) |
6081 | sigprocmask(SIG_SETMASK, &sigsaved, NULL); | |
6082 | ||
b6c7a5dc HB |
6083 | return r; |
6084 | } | |
6085 | ||
6086 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
6087 | { | |
7ae441ea GN |
6088 | if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { |
6089 | /* | |
6090 | * We are here if userspace calls get_regs() in the middle of | |
6091 | * instruction emulation. Registers state needs to be copied | |
4a969980 | 6092 | * back from emulation context to vcpu. Userspace shouldn't do |
7ae441ea GN |
6093 | * that usually, but some bad designed PV devices (vmware |
6094 | * backdoor interface) need this to work | |
6095 | */ | |
dd856efa | 6096 | emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); |
7ae441ea GN |
6097 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
6098 | } | |
5fdbf976 MT |
6099 | regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); |
6100 | regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
6101 | regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
6102 | regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
6103 | regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
6104 | regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
6105 | regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
6106 | regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); | |
b6c7a5dc | 6107 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
6108 | regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); |
6109 | regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); | |
6110 | regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); | |
6111 | regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); | |
6112 | regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); | |
6113 | regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); | |
6114 | regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); | |
6115 | regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); | |
b6c7a5dc HB |
6116 | #endif |
6117 | ||
5fdbf976 | 6118 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 6119 | regs->rflags = kvm_get_rflags(vcpu); |
b6c7a5dc | 6120 | |
b6c7a5dc HB |
6121 | return 0; |
6122 | } | |
6123 | ||
6124 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
6125 | { | |
7ae441ea GN |
6126 | vcpu->arch.emulate_regs_need_sync_from_vcpu = true; |
6127 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; | |
6128 | ||
5fdbf976 MT |
6129 | kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); |
6130 | kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); | |
6131 | kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); | |
6132 | kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); | |
6133 | kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); | |
6134 | kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); | |
6135 | kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); | |
6136 | kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); | |
b6c7a5dc | 6137 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
6138 | kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); |
6139 | kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); | |
6140 | kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); | |
6141 | kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); | |
6142 | kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); | |
6143 | kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); | |
6144 | kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); | |
6145 | kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); | |
b6c7a5dc HB |
6146 | #endif |
6147 | ||
5fdbf976 | 6148 | kvm_rip_write(vcpu, regs->rip); |
91586a3b | 6149 | kvm_set_rflags(vcpu, regs->rflags); |
b6c7a5dc | 6150 | |
b4f14abd JK |
6151 | vcpu->arch.exception.pending = false; |
6152 | ||
3842d135 AK |
6153 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
6154 | ||
b6c7a5dc HB |
6155 | return 0; |
6156 | } | |
6157 | ||
b6c7a5dc HB |
6158 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
6159 | { | |
6160 | struct kvm_segment cs; | |
6161 | ||
3e6e0aab | 6162 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
6163 | *db = cs.db; |
6164 | *l = cs.l; | |
6165 | } | |
6166 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
6167 | ||
6168 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, | |
6169 | struct kvm_sregs *sregs) | |
6170 | { | |
89a27f4d | 6171 | struct desc_ptr dt; |
b6c7a5dc | 6172 | |
3e6e0aab GT |
6173 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
6174 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
6175 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
6176 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
6177 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
6178 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 6179 | |
3e6e0aab GT |
6180 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
6181 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc HB |
6182 | |
6183 | kvm_x86_ops->get_idt(vcpu, &dt); | |
89a27f4d GN |
6184 | sregs->idt.limit = dt.size; |
6185 | sregs->idt.base = dt.address; | |
b6c7a5dc | 6186 | kvm_x86_ops->get_gdt(vcpu, &dt); |
89a27f4d GN |
6187 | sregs->gdt.limit = dt.size; |
6188 | sregs->gdt.base = dt.address; | |
b6c7a5dc | 6189 | |
4d4ec087 | 6190 | sregs->cr0 = kvm_read_cr0(vcpu); |
ad312c7c | 6191 | sregs->cr2 = vcpu->arch.cr2; |
9f8fe504 | 6192 | sregs->cr3 = kvm_read_cr3(vcpu); |
fc78f519 | 6193 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 6194 | sregs->cr8 = kvm_get_cr8(vcpu); |
f6801dff | 6195 | sregs->efer = vcpu->arch.efer; |
b6c7a5dc HB |
6196 | sregs->apic_base = kvm_get_apic_base(vcpu); |
6197 | ||
923c61bb | 6198 | memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); |
b6c7a5dc | 6199 | |
36752c9b | 6200 | if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
6201 | set_bit(vcpu->arch.interrupt.nr, |
6202 | (unsigned long *)sregs->interrupt_bitmap); | |
16d7a191 | 6203 | |
b6c7a5dc HB |
6204 | return 0; |
6205 | } | |
6206 | ||
62d9f0db MT |
6207 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
6208 | struct kvm_mp_state *mp_state) | |
6209 | { | |
66450a21 | 6210 | kvm_apic_accept_events(vcpu); |
62d9f0db | 6211 | mp_state->mp_state = vcpu->arch.mp_state; |
62d9f0db MT |
6212 | return 0; |
6213 | } | |
6214 | ||
6215 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
6216 | struct kvm_mp_state *mp_state) | |
6217 | { | |
66450a21 JK |
6218 | if (!kvm_vcpu_has_lapic(vcpu) && |
6219 | mp_state->mp_state != KVM_MP_STATE_RUNNABLE) | |
6220 | return -EINVAL; | |
6221 | ||
6222 | if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { | |
6223 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
6224 | set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); | |
6225 | } else | |
6226 | vcpu->arch.mp_state = mp_state->mp_state; | |
3842d135 | 6227 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
62d9f0db MT |
6228 | return 0; |
6229 | } | |
6230 | ||
7f3d35fd KW |
6231 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
6232 | int reason, bool has_error_code, u32 error_code) | |
b6c7a5dc | 6233 | { |
9d74191a | 6234 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
8ec4722d | 6235 | int ret; |
e01c2426 | 6236 | |
8ec4722d | 6237 | init_emulate_ctxt(vcpu); |
c697518a | 6238 | |
7f3d35fd | 6239 | ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, |
9d74191a | 6240 | has_error_code, error_code); |
c697518a | 6241 | |
c697518a | 6242 | if (ret) |
19d04437 | 6243 | return EMULATE_FAIL; |
37817f29 | 6244 | |
9d74191a TY |
6245 | kvm_rip_write(vcpu, ctxt->eip); |
6246 | kvm_set_rflags(vcpu, ctxt->eflags); | |
3842d135 | 6247 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
19d04437 | 6248 | return EMULATE_DONE; |
37817f29 IE |
6249 | } |
6250 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
6251 | ||
b6c7a5dc HB |
6252 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, |
6253 | struct kvm_sregs *sregs) | |
6254 | { | |
6255 | int mmu_reset_needed = 0; | |
63f42e02 | 6256 | int pending_vec, max_bits, idx; |
89a27f4d | 6257 | struct desc_ptr dt; |
b6c7a5dc | 6258 | |
6d1068b3 PM |
6259 | if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE)) |
6260 | return -EINVAL; | |
6261 | ||
89a27f4d GN |
6262 | dt.size = sregs->idt.limit; |
6263 | dt.address = sregs->idt.base; | |
b6c7a5dc | 6264 | kvm_x86_ops->set_idt(vcpu, &dt); |
89a27f4d GN |
6265 | dt.size = sregs->gdt.limit; |
6266 | dt.address = sregs->gdt.base; | |
b6c7a5dc HB |
6267 | kvm_x86_ops->set_gdt(vcpu, &dt); |
6268 | ||
ad312c7c | 6269 | vcpu->arch.cr2 = sregs->cr2; |
9f8fe504 | 6270 | mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; |
dc7e795e | 6271 | vcpu->arch.cr3 = sregs->cr3; |
aff48baa | 6272 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); |
b6c7a5dc | 6273 | |
2d3ad1f4 | 6274 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 6275 | |
f6801dff | 6276 | mmu_reset_needed |= vcpu->arch.efer != sregs->efer; |
b6c7a5dc | 6277 | kvm_x86_ops->set_efer(vcpu, sregs->efer); |
b6c7a5dc HB |
6278 | kvm_set_apic_base(vcpu, sregs->apic_base); |
6279 | ||
4d4ec087 | 6280 | mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
b6c7a5dc | 6281 | kvm_x86_ops->set_cr0(vcpu, sregs->cr0); |
d7306163 | 6282 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 6283 | |
fc78f519 | 6284 | mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
b6c7a5dc | 6285 | kvm_x86_ops->set_cr4(vcpu, sregs->cr4); |
3ea3aa8c | 6286 | if (sregs->cr4 & X86_CR4_OSXSAVE) |
00b27a3e | 6287 | kvm_update_cpuid(vcpu); |
63f42e02 XG |
6288 | |
6289 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
7c93be44 | 6290 | if (!is_long_mode(vcpu) && is_pae(vcpu)) { |
9f8fe504 | 6291 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
7c93be44 MT |
6292 | mmu_reset_needed = 1; |
6293 | } | |
63f42e02 | 6294 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b6c7a5dc HB |
6295 | |
6296 | if (mmu_reset_needed) | |
6297 | kvm_mmu_reset_context(vcpu); | |
6298 | ||
a50abc3b | 6299 | max_bits = KVM_NR_INTERRUPTS; |
923c61bb GN |
6300 | pending_vec = find_first_bit( |
6301 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
6302 | if (pending_vec < max_bits) { | |
66fd3f7f | 6303 | kvm_queue_interrupt(vcpu, pending_vec, false); |
923c61bb | 6304 | pr_debug("Set back pending irq %d\n", pending_vec); |
b6c7a5dc HB |
6305 | } |
6306 | ||
3e6e0aab GT |
6307 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
6308 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
6309 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
6310 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
6311 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
6312 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 6313 | |
3e6e0aab GT |
6314 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
6315 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 6316 | |
5f0269f5 ME |
6317 | update_cr8_intercept(vcpu); |
6318 | ||
9c3e4aab | 6319 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 6320 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 6321 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
3eeb3288 | 6322 | !is_protmode(vcpu)) |
9c3e4aab MT |
6323 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
6324 | ||
3842d135 AK |
6325 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
6326 | ||
b6c7a5dc HB |
6327 | return 0; |
6328 | } | |
6329 | ||
d0bfb940 JK |
6330 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
6331 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 6332 | { |
355be0b9 | 6333 | unsigned long rflags; |
ae675ef0 | 6334 | int i, r; |
b6c7a5dc | 6335 | |
4f926bf2 JK |
6336 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
6337 | r = -EBUSY; | |
6338 | if (vcpu->arch.exception.pending) | |
2122ff5e | 6339 | goto out; |
4f926bf2 JK |
6340 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
6341 | kvm_queue_exception(vcpu, DB_VECTOR); | |
6342 | else | |
6343 | kvm_queue_exception(vcpu, BP_VECTOR); | |
6344 | } | |
6345 | ||
91586a3b JK |
6346 | /* |
6347 | * Read rflags as long as potentially injected trace flags are still | |
6348 | * filtered out. | |
6349 | */ | |
6350 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
6351 | |
6352 | vcpu->guest_debug = dbg->control; | |
6353 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
6354 | vcpu->guest_debug = 0; | |
6355 | ||
6356 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
6357 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
6358 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
c8639010 | 6359 | vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; |
ae675ef0 JK |
6360 | } else { |
6361 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
6362 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
ae675ef0 | 6363 | } |
c8639010 | 6364 | kvm_update_dr7(vcpu); |
ae675ef0 | 6365 | |
f92653ee JK |
6366 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
6367 | vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + | |
6368 | get_segment_base(vcpu, VCPU_SREG_CS); | |
94fe45da | 6369 | |
91586a3b JK |
6370 | /* |
6371 | * Trigger an rflags update that will inject or remove the trace | |
6372 | * flags. | |
6373 | */ | |
6374 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 6375 | |
c8639010 | 6376 | kvm_x86_ops->update_db_bp_intercept(vcpu); |
b6c7a5dc | 6377 | |
4f926bf2 | 6378 | r = 0; |
d0bfb940 | 6379 | |
2122ff5e | 6380 | out: |
b6c7a5dc HB |
6381 | |
6382 | return r; | |
6383 | } | |
6384 | ||
8b006791 ZX |
6385 | /* |
6386 | * Translate a guest virtual address to a guest physical address. | |
6387 | */ | |
6388 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
6389 | struct kvm_translation *tr) | |
6390 | { | |
6391 | unsigned long vaddr = tr->linear_address; | |
6392 | gpa_t gpa; | |
f656ce01 | 6393 | int idx; |
8b006791 | 6394 | |
f656ce01 | 6395 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1871c602 | 6396 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); |
f656ce01 | 6397 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 ZX |
6398 | tr->physical_address = gpa; |
6399 | tr->valid = gpa != UNMAPPED_GVA; | |
6400 | tr->writeable = 1; | |
6401 | tr->usermode = 0; | |
8b006791 ZX |
6402 | |
6403 | return 0; | |
6404 | } | |
6405 | ||
d0752060 HB |
6406 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
6407 | { | |
98918833 SY |
6408 | struct i387_fxsave_struct *fxsave = |
6409 | &vcpu->arch.guest_fpu.state->fxsave; | |
d0752060 | 6410 | |
d0752060 HB |
6411 | memcpy(fpu->fpr, fxsave->st_space, 128); |
6412 | fpu->fcw = fxsave->cwd; | |
6413 | fpu->fsw = fxsave->swd; | |
6414 | fpu->ftwx = fxsave->twd; | |
6415 | fpu->last_opcode = fxsave->fop; | |
6416 | fpu->last_ip = fxsave->rip; | |
6417 | fpu->last_dp = fxsave->rdp; | |
6418 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); | |
6419 | ||
d0752060 HB |
6420 | return 0; |
6421 | } | |
6422 | ||
6423 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
6424 | { | |
98918833 SY |
6425 | struct i387_fxsave_struct *fxsave = |
6426 | &vcpu->arch.guest_fpu.state->fxsave; | |
d0752060 | 6427 | |
d0752060 HB |
6428 | memcpy(fxsave->st_space, fpu->fpr, 128); |
6429 | fxsave->cwd = fpu->fcw; | |
6430 | fxsave->swd = fpu->fsw; | |
6431 | fxsave->twd = fpu->ftwx; | |
6432 | fxsave->fop = fpu->last_opcode; | |
6433 | fxsave->rip = fpu->last_ip; | |
6434 | fxsave->rdp = fpu->last_dp; | |
6435 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); | |
6436 | ||
d0752060 HB |
6437 | return 0; |
6438 | } | |
6439 | ||
10ab25cd | 6440 | int fx_init(struct kvm_vcpu *vcpu) |
d0752060 | 6441 | { |
10ab25cd JK |
6442 | int err; |
6443 | ||
6444 | err = fpu_alloc(&vcpu->arch.guest_fpu); | |
6445 | if (err) | |
6446 | return err; | |
6447 | ||
98918833 | 6448 | fpu_finit(&vcpu->arch.guest_fpu); |
d0752060 | 6449 | |
2acf923e DC |
6450 | /* |
6451 | * Ensure guest xcr0 is valid for loading | |
6452 | */ | |
6453 | vcpu->arch.xcr0 = XSTATE_FP; | |
6454 | ||
ad312c7c | 6455 | vcpu->arch.cr0 |= X86_CR0_ET; |
10ab25cd JK |
6456 | |
6457 | return 0; | |
d0752060 HB |
6458 | } |
6459 | EXPORT_SYMBOL_GPL(fx_init); | |
6460 | ||
98918833 SY |
6461 | static void fx_free(struct kvm_vcpu *vcpu) |
6462 | { | |
6463 | fpu_free(&vcpu->arch.guest_fpu); | |
6464 | } | |
6465 | ||
d0752060 HB |
6466 | void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) |
6467 | { | |
2608d7a1 | 6468 | if (vcpu->guest_fpu_loaded) |
d0752060 HB |
6469 | return; |
6470 | ||
2acf923e DC |
6471 | /* |
6472 | * Restore all possible states in the guest, | |
6473 | * and assume host would use all available bits. | |
6474 | * Guest xcr0 would be loaded later. | |
6475 | */ | |
6476 | kvm_put_guest_xcr0(vcpu); | |
d0752060 | 6477 | vcpu->guest_fpu_loaded = 1; |
b1a74bf8 | 6478 | __kernel_fpu_begin(); |
98918833 | 6479 | fpu_restore_checking(&vcpu->arch.guest_fpu); |
0c04851c | 6480 | trace_kvm_fpu(1); |
d0752060 | 6481 | } |
d0752060 HB |
6482 | |
6483 | void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
6484 | { | |
2acf923e DC |
6485 | kvm_put_guest_xcr0(vcpu); |
6486 | ||
d0752060 HB |
6487 | if (!vcpu->guest_fpu_loaded) |
6488 | return; | |
6489 | ||
6490 | vcpu->guest_fpu_loaded = 0; | |
98918833 | 6491 | fpu_save_init(&vcpu->arch.guest_fpu); |
b1a74bf8 | 6492 | __kernel_fpu_end(); |
f096ed85 | 6493 | ++vcpu->stat.fpu_reload; |
a8eeb04a | 6494 | kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu); |
0c04851c | 6495 | trace_kvm_fpu(0); |
d0752060 | 6496 | } |
e9b11c17 ZX |
6497 | |
6498 | void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) | |
6499 | { | |
12f9a48f | 6500 | kvmclock_reset(vcpu); |
7f1ea208 | 6501 | |
f5f48ee1 | 6502 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); |
98918833 | 6503 | fx_free(vcpu); |
e9b11c17 ZX |
6504 | kvm_x86_ops->vcpu_free(vcpu); |
6505 | } | |
6506 | ||
6507 | struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, | |
6508 | unsigned int id) | |
6509 | { | |
6755bae8 ZA |
6510 | if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) |
6511 | printk_once(KERN_WARNING | |
6512 | "kvm: SMP vm created on host with unstable TSC; " | |
6513 | "guest TSC will not be reliable\n"); | |
26e5215f AK |
6514 | return kvm_x86_ops->vcpu_create(kvm, id); |
6515 | } | |
e9b11c17 | 6516 | |
26e5215f AK |
6517 | int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) |
6518 | { | |
6519 | int r; | |
e9b11c17 | 6520 | |
0bed3b56 | 6521 | vcpu->arch.mtrr_state.have_fixed = 1; |
9fc77441 MT |
6522 | r = vcpu_load(vcpu); |
6523 | if (r) | |
6524 | return r; | |
57f252f2 JK |
6525 | kvm_vcpu_reset(vcpu); |
6526 | r = kvm_mmu_setup(vcpu); | |
e9b11c17 | 6527 | vcpu_put(vcpu); |
e9b11c17 | 6528 | |
26e5215f | 6529 | return r; |
e9b11c17 ZX |
6530 | } |
6531 | ||
42897d86 MT |
6532 | int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) |
6533 | { | |
6534 | int r; | |
8fe8ab46 | 6535 | struct msr_data msr; |
42897d86 MT |
6536 | |
6537 | r = vcpu_load(vcpu); | |
6538 | if (r) | |
6539 | return r; | |
8fe8ab46 WA |
6540 | msr.data = 0x0; |
6541 | msr.index = MSR_IA32_TSC; | |
6542 | msr.host_initiated = true; | |
6543 | kvm_write_tsc(vcpu, &msr); | |
42897d86 MT |
6544 | vcpu_put(vcpu); |
6545 | ||
6546 | return r; | |
6547 | } | |
6548 | ||
d40ccc62 | 6549 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 | 6550 | { |
9fc77441 | 6551 | int r; |
344d9588 GN |
6552 | vcpu->arch.apf.msr_val = 0; |
6553 | ||
9fc77441 MT |
6554 | r = vcpu_load(vcpu); |
6555 | BUG_ON(r); | |
e9b11c17 ZX |
6556 | kvm_mmu_unload(vcpu); |
6557 | vcpu_put(vcpu); | |
6558 | ||
98918833 | 6559 | fx_free(vcpu); |
e9b11c17 ZX |
6560 | kvm_x86_ops->vcpu_free(vcpu); |
6561 | } | |
6562 | ||
66450a21 | 6563 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu) |
e9b11c17 | 6564 | { |
7460fb4a AK |
6565 | atomic_set(&vcpu->arch.nmi_queued, 0); |
6566 | vcpu->arch.nmi_pending = 0; | |
448fa4a9 JK |
6567 | vcpu->arch.nmi_injected = false; |
6568 | ||
42dbaa5a JK |
6569 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); |
6570 | vcpu->arch.dr6 = DR6_FIXED_1; | |
6571 | vcpu->arch.dr7 = DR7_FIXED_1; | |
c8639010 | 6572 | kvm_update_dr7(vcpu); |
42dbaa5a | 6573 | |
3842d135 | 6574 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
344d9588 | 6575 | vcpu->arch.apf.msr_val = 0; |
c9aaa895 | 6576 | vcpu->arch.st.msr_val = 0; |
3842d135 | 6577 | |
12f9a48f GC |
6578 | kvmclock_reset(vcpu); |
6579 | ||
af585b92 GN |
6580 | kvm_clear_async_pf_completion_queue(vcpu); |
6581 | kvm_async_pf_hash_reset(vcpu); | |
6582 | vcpu->arch.apf.halted = false; | |
3842d135 | 6583 | |
f5132b01 GN |
6584 | kvm_pmu_reset(vcpu); |
6585 | ||
66f7b72e JS |
6586 | memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); |
6587 | vcpu->arch.regs_avail = ~0; | |
6588 | vcpu->arch.regs_dirty = ~0; | |
6589 | ||
57f252f2 | 6590 | kvm_x86_ops->vcpu_reset(vcpu); |
e9b11c17 ZX |
6591 | } |
6592 | ||
66450a21 JK |
6593 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector) |
6594 | { | |
6595 | struct kvm_segment cs; | |
6596 | ||
6597 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
6598 | cs.selector = vector << 8; | |
6599 | cs.base = vector << 12; | |
6600 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
6601 | kvm_rip_write(vcpu, 0); | |
e9b11c17 ZX |
6602 | } |
6603 | ||
10474ae8 | 6604 | int kvm_arch_hardware_enable(void *garbage) |
e9b11c17 | 6605 | { |
ca84d1a2 ZA |
6606 | struct kvm *kvm; |
6607 | struct kvm_vcpu *vcpu; | |
6608 | int i; | |
0dd6a6ed ZA |
6609 | int ret; |
6610 | u64 local_tsc; | |
6611 | u64 max_tsc = 0; | |
6612 | bool stable, backwards_tsc = false; | |
18863bdd AK |
6613 | |
6614 | kvm_shared_msr_cpu_online(); | |
0dd6a6ed ZA |
6615 | ret = kvm_x86_ops->hardware_enable(garbage); |
6616 | if (ret != 0) | |
6617 | return ret; | |
6618 | ||
6619 | local_tsc = native_read_tsc(); | |
6620 | stable = !check_tsc_unstable(); | |
6621 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
6622 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
6623 | if (!stable && vcpu->cpu == smp_processor_id()) | |
6624 | set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests); | |
6625 | if (stable && vcpu->arch.last_host_tsc > local_tsc) { | |
6626 | backwards_tsc = true; | |
6627 | if (vcpu->arch.last_host_tsc > max_tsc) | |
6628 | max_tsc = vcpu->arch.last_host_tsc; | |
6629 | } | |
6630 | } | |
6631 | } | |
6632 | ||
6633 | /* | |
6634 | * Sometimes, even reliable TSCs go backwards. This happens on | |
6635 | * platforms that reset TSC during suspend or hibernate actions, but | |
6636 | * maintain synchronization. We must compensate. Fortunately, we can | |
6637 | * detect that condition here, which happens early in CPU bringup, | |
6638 | * before any KVM threads can be running. Unfortunately, we can't | |
6639 | * bring the TSCs fully up to date with real time, as we aren't yet far | |
6640 | * enough into CPU bringup that we know how much real time has actually | |
6641 | * elapsed; our helper function, get_kernel_ns() will be using boot | |
6642 | * variables that haven't been updated yet. | |
6643 | * | |
6644 | * So we simply find the maximum observed TSC above, then record the | |
6645 | * adjustment to TSC in each VCPU. When the VCPU later gets loaded, | |
6646 | * the adjustment will be applied. Note that we accumulate | |
6647 | * adjustments, in case multiple suspend cycles happen before some VCPU | |
6648 | * gets a chance to run again. In the event that no KVM threads get a | |
6649 | * chance to run, we will miss the entire elapsed period, as we'll have | |
6650 | * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may | |
6651 | * loose cycle time. This isn't too big a deal, since the loss will be | |
6652 | * uniform across all VCPUs (not to mention the scenario is extremely | |
6653 | * unlikely). It is possible that a second hibernate recovery happens | |
6654 | * much faster than a first, causing the observed TSC here to be | |
6655 | * smaller; this would require additional padding adjustment, which is | |
6656 | * why we set last_host_tsc to the local tsc observed here. | |
6657 | * | |
6658 | * N.B. - this code below runs only on platforms with reliable TSC, | |
6659 | * as that is the only way backwards_tsc is set above. Also note | |
6660 | * that this runs for ALL vcpus, which is not a bug; all VCPUs should | |
6661 | * have the same delta_cyc adjustment applied if backwards_tsc | |
6662 | * is detected. Note further, this adjustment is only done once, | |
6663 | * as we reset last_host_tsc on all VCPUs to stop this from being | |
6664 | * called multiple times (one for each physical CPU bringup). | |
6665 | * | |
4a969980 | 6666 | * Platforms with unreliable TSCs don't have to deal with this, they |
0dd6a6ed ZA |
6667 | * will be compensated by the logic in vcpu_load, which sets the TSC to |
6668 | * catchup mode. This will catchup all VCPUs to real time, but cannot | |
6669 | * guarantee that they stay in perfect synchronization. | |
6670 | */ | |
6671 | if (backwards_tsc) { | |
6672 | u64 delta_cyc = max_tsc - local_tsc; | |
6673 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
6674 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
6675 | vcpu->arch.tsc_offset_adjustment += delta_cyc; | |
6676 | vcpu->arch.last_host_tsc = local_tsc; | |
d828199e MT |
6677 | set_bit(KVM_REQ_MASTERCLOCK_UPDATE, |
6678 | &vcpu->requests); | |
0dd6a6ed ZA |
6679 | } |
6680 | ||
6681 | /* | |
6682 | * We have to disable TSC offset matching.. if you were | |
6683 | * booting a VM while issuing an S4 host suspend.... | |
6684 | * you may have some problem. Solving this issue is | |
6685 | * left as an exercise to the reader. | |
6686 | */ | |
6687 | kvm->arch.last_tsc_nsec = 0; | |
6688 | kvm->arch.last_tsc_write = 0; | |
6689 | } | |
6690 | ||
6691 | } | |
6692 | return 0; | |
e9b11c17 ZX |
6693 | } |
6694 | ||
6695 | void kvm_arch_hardware_disable(void *garbage) | |
6696 | { | |
6697 | kvm_x86_ops->hardware_disable(garbage); | |
3548bab5 | 6698 | drop_user_return_notifiers(garbage); |
e9b11c17 ZX |
6699 | } |
6700 | ||
6701 | int kvm_arch_hardware_setup(void) | |
6702 | { | |
6703 | return kvm_x86_ops->hardware_setup(); | |
6704 | } | |
6705 | ||
6706 | void kvm_arch_hardware_unsetup(void) | |
6707 | { | |
6708 | kvm_x86_ops->hardware_unsetup(); | |
6709 | } | |
6710 | ||
6711 | void kvm_arch_check_processor_compat(void *rtn) | |
6712 | { | |
6713 | kvm_x86_ops->check_processor_compatibility(rtn); | |
6714 | } | |
6715 | ||
3e515705 AK |
6716 | bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu) |
6717 | { | |
6718 | return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL); | |
6719 | } | |
6720 | ||
54e9818f GN |
6721 | struct static_key kvm_no_apic_vcpu __read_mostly; |
6722 | ||
e9b11c17 ZX |
6723 | int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) |
6724 | { | |
6725 | struct page *page; | |
6726 | struct kvm *kvm; | |
6727 | int r; | |
6728 | ||
6729 | BUG_ON(vcpu->kvm == NULL); | |
6730 | kvm = vcpu->kvm; | |
6731 | ||
9aabc88f | 6732 | vcpu->arch.emulate_ctxt.ops = &emulate_ops; |
c5af89b6 | 6733 | if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu)) |
a4535290 | 6734 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
e9b11c17 | 6735 | else |
a4535290 | 6736 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; |
e9b11c17 ZX |
6737 | |
6738 | page = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
6739 | if (!page) { | |
6740 | r = -ENOMEM; | |
6741 | goto fail; | |
6742 | } | |
ad312c7c | 6743 | vcpu->arch.pio_data = page_address(page); |
e9b11c17 | 6744 | |
cc578287 | 6745 | kvm_set_tsc_khz(vcpu, max_tsc_khz); |
c285545f | 6746 | |
e9b11c17 ZX |
6747 | r = kvm_mmu_create(vcpu); |
6748 | if (r < 0) | |
6749 | goto fail_free_pio_data; | |
6750 | ||
6751 | if (irqchip_in_kernel(kvm)) { | |
6752 | r = kvm_create_lapic(vcpu); | |
6753 | if (r < 0) | |
6754 | goto fail_mmu_destroy; | |
54e9818f GN |
6755 | } else |
6756 | static_key_slow_inc(&kvm_no_apic_vcpu); | |
e9b11c17 | 6757 | |
890ca9ae HY |
6758 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, |
6759 | GFP_KERNEL); | |
6760 | if (!vcpu->arch.mce_banks) { | |
6761 | r = -ENOMEM; | |
443c39bc | 6762 | goto fail_free_lapic; |
890ca9ae HY |
6763 | } |
6764 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
6765 | ||
f1797359 WY |
6766 | if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) { |
6767 | r = -ENOMEM; | |
f5f48ee1 | 6768 | goto fail_free_mce_banks; |
f1797359 | 6769 | } |
f5f48ee1 | 6770 | |
66f7b72e JS |
6771 | r = fx_init(vcpu); |
6772 | if (r) | |
6773 | goto fail_free_wbinvd_dirty_mask; | |
6774 | ||
ba904635 | 6775 | vcpu->arch.ia32_tsc_adjust_msr = 0x0; |
0b79459b | 6776 | vcpu->arch.pv_time_enabled = false; |
af585b92 | 6777 | kvm_async_pf_hash_reset(vcpu); |
f5132b01 | 6778 | kvm_pmu_init(vcpu); |
af585b92 | 6779 | |
e9b11c17 | 6780 | return 0; |
66f7b72e JS |
6781 | fail_free_wbinvd_dirty_mask: |
6782 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); | |
f5f48ee1 SY |
6783 | fail_free_mce_banks: |
6784 | kfree(vcpu->arch.mce_banks); | |
443c39bc WY |
6785 | fail_free_lapic: |
6786 | kvm_free_lapic(vcpu); | |
e9b11c17 ZX |
6787 | fail_mmu_destroy: |
6788 | kvm_mmu_destroy(vcpu); | |
6789 | fail_free_pio_data: | |
ad312c7c | 6790 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 ZX |
6791 | fail: |
6792 | return r; | |
6793 | } | |
6794 | ||
6795 | void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) | |
6796 | { | |
f656ce01 MT |
6797 | int idx; |
6798 | ||
f5132b01 | 6799 | kvm_pmu_destroy(vcpu); |
36cb93fd | 6800 | kfree(vcpu->arch.mce_banks); |
e9b11c17 | 6801 | kvm_free_lapic(vcpu); |
f656ce01 | 6802 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
e9b11c17 | 6803 | kvm_mmu_destroy(vcpu); |
f656ce01 | 6804 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
ad312c7c | 6805 | free_page((unsigned long)vcpu->arch.pio_data); |
54e9818f GN |
6806 | if (!irqchip_in_kernel(vcpu->kvm)) |
6807 | static_key_slow_dec(&kvm_no_apic_vcpu); | |
e9b11c17 | 6808 | } |
d19a9cd2 | 6809 | |
e08b9637 | 6810 | int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) |
d19a9cd2 | 6811 | { |
e08b9637 CO |
6812 | if (type) |
6813 | return -EINVAL; | |
6814 | ||
f05e70ac | 6815 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
4d5c5d0f | 6816 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
d19a9cd2 | 6817 | |
5550af4d SY |
6818 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
6819 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
7a84428a AW |
6820 | /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ |
6821 | set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, | |
6822 | &kvm->arch.irq_sources_bitmap); | |
5550af4d | 6823 | |
038f8c11 | 6824 | raw_spin_lock_init(&kvm->arch.tsc_write_lock); |
1e08ec4a | 6825 | mutex_init(&kvm->arch.apic_map_lock); |
d828199e MT |
6826 | spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); |
6827 | ||
6828 | pvclock_update_vm_gtod_copy(kvm); | |
53f658b3 | 6829 | |
d89f5eff | 6830 | return 0; |
d19a9cd2 ZX |
6831 | } |
6832 | ||
6833 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) | |
6834 | { | |
9fc77441 MT |
6835 | int r; |
6836 | r = vcpu_load(vcpu); | |
6837 | BUG_ON(r); | |
d19a9cd2 ZX |
6838 | kvm_mmu_unload(vcpu); |
6839 | vcpu_put(vcpu); | |
6840 | } | |
6841 | ||
6842 | static void kvm_free_vcpus(struct kvm *kvm) | |
6843 | { | |
6844 | unsigned int i; | |
988a2cae | 6845 | struct kvm_vcpu *vcpu; |
d19a9cd2 ZX |
6846 | |
6847 | /* | |
6848 | * Unpin any mmu pages first. | |
6849 | */ | |
af585b92 GN |
6850 | kvm_for_each_vcpu(i, vcpu, kvm) { |
6851 | kvm_clear_async_pf_completion_queue(vcpu); | |
988a2cae | 6852 | kvm_unload_vcpu_mmu(vcpu); |
af585b92 | 6853 | } |
988a2cae GN |
6854 | kvm_for_each_vcpu(i, vcpu, kvm) |
6855 | kvm_arch_vcpu_free(vcpu); | |
6856 | ||
6857 | mutex_lock(&kvm->lock); | |
6858 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
6859 | kvm->vcpus[i] = NULL; | |
d19a9cd2 | 6860 | |
988a2cae GN |
6861 | atomic_set(&kvm->online_vcpus, 0); |
6862 | mutex_unlock(&kvm->lock); | |
d19a9cd2 ZX |
6863 | } |
6864 | ||
ad8ba2cd SY |
6865 | void kvm_arch_sync_events(struct kvm *kvm) |
6866 | { | |
ba4cef31 | 6867 | kvm_free_all_assigned_devices(kvm); |
aea924f6 | 6868 | kvm_free_pit(kvm); |
ad8ba2cd SY |
6869 | } |
6870 | ||
d19a9cd2 ZX |
6871 | void kvm_arch_destroy_vm(struct kvm *kvm) |
6872 | { | |
27469d29 AH |
6873 | if (current->mm == kvm->mm) { |
6874 | /* | |
6875 | * Free memory regions allocated on behalf of userspace, | |
6876 | * unless the the memory map has changed due to process exit | |
6877 | * or fd copying. | |
6878 | */ | |
6879 | struct kvm_userspace_memory_region mem; | |
6880 | memset(&mem, 0, sizeof(mem)); | |
6881 | mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT; | |
6882 | kvm_set_memory_region(kvm, &mem); | |
6883 | ||
6884 | mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT; | |
6885 | kvm_set_memory_region(kvm, &mem); | |
6886 | ||
6887 | mem.slot = TSS_PRIVATE_MEMSLOT; | |
6888 | kvm_set_memory_region(kvm, &mem); | |
6889 | } | |
6eb55818 | 6890 | kvm_iommu_unmap_guest(kvm); |
d7deeeb0 ZX |
6891 | kfree(kvm->arch.vpic); |
6892 | kfree(kvm->arch.vioapic); | |
d19a9cd2 | 6893 | kvm_free_vcpus(kvm); |
3d45830c AK |
6894 | if (kvm->arch.apic_access_page) |
6895 | put_page(kvm->arch.apic_access_page); | |
b7ebfb05 SY |
6896 | if (kvm->arch.ept_identity_pagetable) |
6897 | put_page(kvm->arch.ept_identity_pagetable); | |
1e08ec4a | 6898 | kfree(rcu_dereference_check(kvm->arch.apic_map, 1)); |
d19a9cd2 | 6899 | } |
0de10343 | 6900 | |
db3fe4eb TY |
6901 | void kvm_arch_free_memslot(struct kvm_memory_slot *free, |
6902 | struct kvm_memory_slot *dont) | |
6903 | { | |
6904 | int i; | |
6905 | ||
d89cc617 TY |
6906 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
6907 | if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { | |
6908 | kvm_kvfree(free->arch.rmap[i]); | |
6909 | free->arch.rmap[i] = NULL; | |
77d11309 | 6910 | } |
d89cc617 TY |
6911 | if (i == 0) |
6912 | continue; | |
6913 | ||
6914 | if (!dont || free->arch.lpage_info[i - 1] != | |
6915 | dont->arch.lpage_info[i - 1]) { | |
6916 | kvm_kvfree(free->arch.lpage_info[i - 1]); | |
6917 | free->arch.lpage_info[i - 1] = NULL; | |
db3fe4eb TY |
6918 | } |
6919 | } | |
6920 | } | |
6921 | ||
6922 | int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages) | |
6923 | { | |
6924 | int i; | |
6925 | ||
d89cc617 | 6926 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
db3fe4eb TY |
6927 | unsigned long ugfn; |
6928 | int lpages; | |
d89cc617 | 6929 | int level = i + 1; |
db3fe4eb TY |
6930 | |
6931 | lpages = gfn_to_index(slot->base_gfn + npages - 1, | |
6932 | slot->base_gfn, level) + 1; | |
6933 | ||
d89cc617 TY |
6934 | slot->arch.rmap[i] = |
6935 | kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i])); | |
6936 | if (!slot->arch.rmap[i]) | |
77d11309 | 6937 | goto out_free; |
d89cc617 TY |
6938 | if (i == 0) |
6939 | continue; | |
77d11309 | 6940 | |
d89cc617 TY |
6941 | slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages * |
6942 | sizeof(*slot->arch.lpage_info[i - 1])); | |
6943 | if (!slot->arch.lpage_info[i - 1]) | |
db3fe4eb TY |
6944 | goto out_free; |
6945 | ||
6946 | if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) | |
d89cc617 | 6947 | slot->arch.lpage_info[i - 1][0].write_count = 1; |
db3fe4eb | 6948 | if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) |
d89cc617 | 6949 | slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1; |
db3fe4eb TY |
6950 | ugfn = slot->userspace_addr >> PAGE_SHIFT; |
6951 | /* | |
6952 | * If the gfn and userspace address are not aligned wrt each | |
6953 | * other, or if explicitly asked to, disable large page | |
6954 | * support for this slot | |
6955 | */ | |
6956 | if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || | |
6957 | !kvm_largepages_enabled()) { | |
6958 | unsigned long j; | |
6959 | ||
6960 | for (j = 0; j < lpages; ++j) | |
d89cc617 | 6961 | slot->arch.lpage_info[i - 1][j].write_count = 1; |
db3fe4eb TY |
6962 | } |
6963 | } | |
6964 | ||
6965 | return 0; | |
6966 | ||
6967 | out_free: | |
d89cc617 TY |
6968 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
6969 | kvm_kvfree(slot->arch.rmap[i]); | |
6970 | slot->arch.rmap[i] = NULL; | |
6971 | if (i == 0) | |
6972 | continue; | |
6973 | ||
6974 | kvm_kvfree(slot->arch.lpage_info[i - 1]); | |
6975 | slot->arch.lpage_info[i - 1] = NULL; | |
db3fe4eb TY |
6976 | } |
6977 | return -ENOMEM; | |
6978 | } | |
6979 | ||
f7784b8e MT |
6980 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
6981 | struct kvm_memory_slot *memslot, | |
f7784b8e | 6982 | struct kvm_userspace_memory_region *mem, |
7b6195a9 | 6983 | enum kvm_mr_change change) |
0de10343 | 6984 | { |
7a905b14 TY |
6985 | /* |
6986 | * Only private memory slots need to be mapped here since | |
6987 | * KVM_SET_MEMORY_REGION ioctl is no longer supported. | |
0de10343 | 6988 | */ |
7b6195a9 | 6989 | if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) { |
7a905b14 | 6990 | unsigned long userspace_addr; |
604b38ac | 6991 | |
7a905b14 TY |
6992 | /* |
6993 | * MAP_SHARED to prevent internal slot pages from being moved | |
6994 | * by fork()/COW. | |
6995 | */ | |
7b6195a9 | 6996 | userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE, |
7a905b14 TY |
6997 | PROT_READ | PROT_WRITE, |
6998 | MAP_SHARED | MAP_ANONYMOUS, 0); | |
0de10343 | 6999 | |
7a905b14 TY |
7000 | if (IS_ERR((void *)userspace_addr)) |
7001 | return PTR_ERR((void *)userspace_addr); | |
604b38ac | 7002 | |
7a905b14 | 7003 | memslot->userspace_addr = userspace_addr; |
0de10343 ZX |
7004 | } |
7005 | ||
f7784b8e MT |
7006 | return 0; |
7007 | } | |
7008 | ||
7009 | void kvm_arch_commit_memory_region(struct kvm *kvm, | |
7010 | struct kvm_userspace_memory_region *mem, | |
8482644a TY |
7011 | const struct kvm_memory_slot *old, |
7012 | enum kvm_mr_change change) | |
f7784b8e MT |
7013 | { |
7014 | ||
8482644a | 7015 | int nr_mmu_pages = 0; |
f7784b8e | 7016 | |
8482644a | 7017 | if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) { |
f7784b8e MT |
7018 | int ret; |
7019 | ||
8482644a TY |
7020 | ret = vm_munmap(old->userspace_addr, |
7021 | old->npages * PAGE_SIZE); | |
f7784b8e MT |
7022 | if (ret < 0) |
7023 | printk(KERN_WARNING | |
7024 | "kvm_vm_ioctl_set_memory_region: " | |
7025 | "failed to munmap memory\n"); | |
7026 | } | |
7027 | ||
48c0e4e9 XG |
7028 | if (!kvm->arch.n_requested_mmu_pages) |
7029 | nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); | |
7030 | ||
48c0e4e9 | 7031 | if (nr_mmu_pages) |
0de10343 | 7032 | kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); |
c972f3b1 TY |
7033 | /* |
7034 | * Write protect all pages for dirty logging. | |
7035 | * Existing largepage mappings are destroyed here and new ones will | |
7036 | * not be created until the end of the logging. | |
7037 | */ | |
8482644a | 7038 | if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES)) |
c972f3b1 | 7039 | kvm_mmu_slot_remove_write_access(kvm, mem->slot); |
3b4dc3a0 MT |
7040 | /* |
7041 | * If memory slot is created, or moved, we need to clear all | |
7042 | * mmio sptes. | |
7043 | */ | |
8482644a | 7044 | if ((change == KVM_MR_CREATE) || (change == KVM_MR_MOVE)) { |
982b3394 | 7045 | kvm_mmu_zap_mmio_sptes(kvm); |
3b4dc3a0 MT |
7046 | kvm_reload_remote_mmus(kvm); |
7047 | } | |
0de10343 | 7048 | } |
1d737c8a | 7049 | |
2df72e9b | 7050 | void kvm_arch_flush_shadow_all(struct kvm *kvm) |
34d4cb8f MT |
7051 | { |
7052 | kvm_mmu_zap_all(kvm); | |
8986ecc0 | 7053 | kvm_reload_remote_mmus(kvm); |
34d4cb8f MT |
7054 | } |
7055 | ||
2df72e9b MT |
7056 | void kvm_arch_flush_shadow_memslot(struct kvm *kvm, |
7057 | struct kvm_memory_slot *slot) | |
7058 | { | |
7059 | kvm_arch_flush_shadow_all(kvm); | |
7060 | } | |
7061 | ||
1d737c8a ZX |
7062 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
7063 | { | |
af585b92 GN |
7064 | return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
7065 | !vcpu->arch.apf.halted) | |
7066 | || !list_empty_careful(&vcpu->async_pf.done) | |
66450a21 | 7067 | || kvm_apic_has_events(vcpu) |
7460fb4a | 7068 | || atomic_read(&vcpu->arch.nmi_queued) || |
a1b37100 GN |
7069 | (kvm_arch_interrupt_allowed(vcpu) && |
7070 | kvm_cpu_has_interrupt(vcpu)); | |
1d737c8a | 7071 | } |
5736199a | 7072 | |
b6d33834 | 7073 | int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) |
5736199a | 7074 | { |
b6d33834 | 7075 | return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; |
5736199a | 7076 | } |
78646121 GN |
7077 | |
7078 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
7079 | { | |
7080 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
7081 | } | |
229456fc | 7082 | |
f92653ee JK |
7083 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) |
7084 | { | |
7085 | unsigned long current_rip = kvm_rip_read(vcpu) + | |
7086 | get_segment_base(vcpu, VCPU_SREG_CS); | |
7087 | ||
7088 | return current_rip == linear_rip; | |
7089 | } | |
7090 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
7091 | ||
94fe45da JK |
7092 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
7093 | { | |
7094 | unsigned long rflags; | |
7095 | ||
7096 | rflags = kvm_x86_ops->get_rflags(vcpu); | |
7097 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
c310bac5 | 7098 | rflags &= ~X86_EFLAGS_TF; |
94fe45da JK |
7099 | return rflags; |
7100 | } | |
7101 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
7102 | ||
7103 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
7104 | { | |
7105 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
f92653ee | 7106 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) |
c310bac5 | 7107 | rflags |= X86_EFLAGS_TF; |
94fe45da | 7108 | kvm_x86_ops->set_rflags(vcpu, rflags); |
3842d135 | 7109 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
94fe45da JK |
7110 | } |
7111 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
7112 | ||
56028d08 GN |
7113 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) |
7114 | { | |
7115 | int r; | |
7116 | ||
fb67e14f | 7117 | if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) || |
c4806acd | 7118 | is_error_page(work->page)) |
56028d08 GN |
7119 | return; |
7120 | ||
7121 | r = kvm_mmu_reload(vcpu); | |
7122 | if (unlikely(r)) | |
7123 | return; | |
7124 | ||
fb67e14f XG |
7125 | if (!vcpu->arch.mmu.direct_map && |
7126 | work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu)) | |
7127 | return; | |
7128 | ||
56028d08 GN |
7129 | vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); |
7130 | } | |
7131 | ||
af585b92 GN |
7132 | static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) |
7133 | { | |
7134 | return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); | |
7135 | } | |
7136 | ||
7137 | static inline u32 kvm_async_pf_next_probe(u32 key) | |
7138 | { | |
7139 | return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); | |
7140 | } | |
7141 | ||
7142 | static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
7143 | { | |
7144 | u32 key = kvm_async_pf_hash_fn(gfn); | |
7145 | ||
7146 | while (vcpu->arch.apf.gfns[key] != ~0) | |
7147 | key = kvm_async_pf_next_probe(key); | |
7148 | ||
7149 | vcpu->arch.apf.gfns[key] = gfn; | |
7150 | } | |
7151 | ||
7152 | static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) | |
7153 | { | |
7154 | int i; | |
7155 | u32 key = kvm_async_pf_hash_fn(gfn); | |
7156 | ||
7157 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && | |
c7d28c24 XG |
7158 | (vcpu->arch.apf.gfns[key] != gfn && |
7159 | vcpu->arch.apf.gfns[key] != ~0); i++) | |
af585b92 GN |
7160 | key = kvm_async_pf_next_probe(key); |
7161 | ||
7162 | return key; | |
7163 | } | |
7164 | ||
7165 | bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
7166 | { | |
7167 | return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; | |
7168 | } | |
7169 | ||
7170 | static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
7171 | { | |
7172 | u32 i, j, k; | |
7173 | ||
7174 | i = j = kvm_async_pf_gfn_slot(vcpu, gfn); | |
7175 | while (true) { | |
7176 | vcpu->arch.apf.gfns[i] = ~0; | |
7177 | do { | |
7178 | j = kvm_async_pf_next_probe(j); | |
7179 | if (vcpu->arch.apf.gfns[j] == ~0) | |
7180 | return; | |
7181 | k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); | |
7182 | /* | |
7183 | * k lies cyclically in ]i,j] | |
7184 | * | i.k.j | | |
7185 | * |....j i.k.| or |.k..j i...| | |
7186 | */ | |
7187 | } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); | |
7188 | vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; | |
7189 | i = j; | |
7190 | } | |
7191 | } | |
7192 | ||
7c90705b GN |
7193 | static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) |
7194 | { | |
7195 | ||
7196 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, | |
7197 | sizeof(val)); | |
7198 | } | |
7199 | ||
af585b92 GN |
7200 | void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
7201 | struct kvm_async_pf *work) | |
7202 | { | |
6389ee94 AK |
7203 | struct x86_exception fault; |
7204 | ||
7c90705b | 7205 | trace_kvm_async_pf_not_present(work->arch.token, work->gva); |
af585b92 | 7206 | kvm_add_async_pf_gfn(vcpu, work->arch.gfn); |
7c90705b GN |
7207 | |
7208 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || | |
fc5f06fa GN |
7209 | (vcpu->arch.apf.send_user_only && |
7210 | kvm_x86_ops->get_cpl(vcpu) == 0)) | |
7c90705b GN |
7211 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); |
7212 | else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { | |
6389ee94 AK |
7213 | fault.vector = PF_VECTOR; |
7214 | fault.error_code_valid = true; | |
7215 | fault.error_code = 0; | |
7216 | fault.nested_page_fault = false; | |
7217 | fault.address = work->arch.token; | |
7218 | kvm_inject_page_fault(vcpu, &fault); | |
7c90705b | 7219 | } |
af585b92 GN |
7220 | } |
7221 | ||
7222 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
7223 | struct kvm_async_pf *work) | |
7224 | { | |
6389ee94 AK |
7225 | struct x86_exception fault; |
7226 | ||
7c90705b GN |
7227 | trace_kvm_async_pf_ready(work->arch.token, work->gva); |
7228 | if (is_error_page(work->page)) | |
7229 | work->arch.token = ~0; /* broadcast wakeup */ | |
7230 | else | |
7231 | kvm_del_async_pf_gfn(vcpu, work->arch.gfn); | |
7232 | ||
7233 | if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) && | |
7234 | !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { | |
6389ee94 AK |
7235 | fault.vector = PF_VECTOR; |
7236 | fault.error_code_valid = true; | |
7237 | fault.error_code = 0; | |
7238 | fault.nested_page_fault = false; | |
7239 | fault.address = work->arch.token; | |
7240 | kvm_inject_page_fault(vcpu, &fault); | |
7c90705b | 7241 | } |
e6d53e3b | 7242 | vcpu->arch.apf.halted = false; |
a4fa1635 | 7243 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
7c90705b GN |
7244 | } |
7245 | ||
7246 | bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) | |
7247 | { | |
7248 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) | |
7249 | return true; | |
7250 | else | |
7251 | return !kvm_event_needs_reinjection(vcpu) && | |
7252 | kvm_x86_ops->interrupt_allowed(vcpu); | |
af585b92 GN |
7253 | } |
7254 | ||
229456fc MT |
7255 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
7256 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); | |
7257 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
7258 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
7259 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
0ac406de | 7260 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); |
d8cabddf | 7261 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 7262 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 7263 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
ec1ff790 | 7264 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 7265 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |
2e554e8d | 7266 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); |