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KVM: Count the number of dirty pages for dirty logging
[mirror_ubuntu-jammy-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
af585b92 46#include <linux/hash.h>
a1b60c1c 47#include <linux/pci.h>
aec51dc4 48#include <trace/events/kvm.h>
2ed152af 49
229456fc
MT		 50#define CREATE_TRACE_POINTS
51#include "trace.h"
043405e1 52
24f1e32c 53#include <asm/debugreg.h>
d825ed0a 54#include <asm/msr.h>
a5f61300 55#include <asm/desc.h>
0bed3b56 56#include <asm/mtrr.h>
890ca9ae 57#include <asm/mce.h>
7cf30855 58#include <asm/i387.h>
98918833 59#include <asm/xcr.h>
1d5f066e 60#include <asm/pvclock.h>
217fc9cf 61#include <asm/div64.h>
043405e1 62
313a3dc7 63#define MAX_IO_MSRS 256
890ca9ae 64#define KVM_MAX_MCE_BANKS 32
5854dbca 65#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 66
0f65dd70
AK		 67#define emul_to_vcpu(ctxt) \
68 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
69
50a37eb4
JR		 70/* EFER defaults:
71 * - enable syscall per default because its emulated by KVM
72 * - enable LME and LMA per default on 64 bit KVM
73 */
74#ifdef CONFIG_X86_64
1260edbe
LJ		 75static
76u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 77#else
1260edbe 78static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 79#endif
313a3dc7 80
ba1389b7
AK		 81#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
82#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 83
cb142eb7 84static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 85static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
86 struct kvm_cpuid_entry2 __user *entries);
7460fb4a 87static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 88
97896d04 89struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 90EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 91
ed85c068
AP		 92int ignore_msrs = 0;
93module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
94
92a1f12d
JR		 95bool kvm_has_tsc_control;
96EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
97u32 kvm_max_guest_tsc_khz;
98EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
99
18863bdd
AK		 100#define KVM_NR_SHARED_MSRS 16
101
102struct kvm_shared_msrs_global {
103 int nr;
2bf78fa7 104 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 105};
106
107struct kvm_shared_msrs {
108 struct user_return_notifier urn;
109 bool registered;
2bf78fa7
SY		 110 struct kvm_shared_msr_values {
111 u64 host;
112 u64 curr;
113 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 114};
115
116static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
117static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
118
417bc304 119struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 120 { "pf_fixed", VCPU_STAT(pf_fixed) },
121 { "pf_guest", VCPU_STAT(pf_guest) },
122 { "tlb_flush", VCPU_STAT(tlb_flush) },
123 { "invlpg", VCPU_STAT(invlpg) },
124 { "exits", VCPU_STAT(exits) },
125 { "io_exits", VCPU_STAT(io_exits) },
126 { "mmio_exits", VCPU_STAT(mmio_exits) },
127 { "signal_exits", VCPU_STAT(signal_exits) },
128 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 129 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 130 { "halt_exits", VCPU_STAT(halt_exits) },
131 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 132 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 133 { "request_irq", VCPU_STAT(request_irq_exits) },
134 { "irq_exits", VCPU_STAT(irq_exits) },
135 { "host_state_reload", VCPU_STAT(host_state_reload) },
136 { "efer_reload", VCPU_STAT(efer_reload) },
137 { "fpu_reload", VCPU_STAT(fpu_reload) },
138 { "insn_emulation", VCPU_STAT(insn_emulation) },
139 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 140 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 141 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 142 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
143 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
144 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
145 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
146 { "mmu_flooded", VM_STAT(mmu_flooded) },
147 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 148 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 149 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 150 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 151 { "largepages", VM_STAT(lpages) },
417bc304
HB		 152 { NULL }
153};
154
2acf923e
DC		 155u64 __read_mostly host_xcr0;
156
d6aa1000
AK		 157int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
158
af585b92
GN		 159static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
160{
161 int i;
162 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
163 vcpu->arch.apf.gfns[i] = ~0;
164}
165
18863bdd
AK		 166static void kvm_on_user_return(struct user_return_notifier *urn)
167{
168 unsigned slot;
18863bdd
AK		 169 struct kvm_shared_msrs *locals
170 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 171 struct kvm_shared_msr_values *values;
18863bdd
AK		 172
173 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 174 values = &locals->values[slot];
175 if (values->host != values->curr) {
176 wrmsrl(shared_msrs_global.msrs[slot], values->host);
177 values->curr = values->host;
18863bdd
AK		 178 }
179 }
180 locals->registered = false;
181 user_return_notifier_unregister(urn);
182}
183
2bf78fa7 184static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 185{
2bf78fa7 186 struct kvm_shared_msrs *smsr;
18863bdd
AK		 187 u64 value;
188
2bf78fa7
SY		 189 smsr = &__get_cpu_var(shared_msrs);
190 /* only read, and nobody should modify it at this time,
191 * so don't need lock */
192 if (slot >= shared_msrs_global.nr) {
193 printk(KERN_ERR "kvm: invalid MSR slot!");
194 return;
195 }
196 rdmsrl_safe(msr, &value);
197 smsr->values[slot].host = value;
198 smsr->values[slot].curr = value;
199}
200
201void kvm_define_shared_msr(unsigned slot, u32 msr)
202{
18863bdd
AK		 203 if (slot >= shared_msrs_global.nr)
204 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 205 shared_msrs_global.msrs[slot] = msr;
206 /* we need ensured the shared_msr_global have been updated */
207 smp_wmb();
18863bdd
AK		 208}
209EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
210
211static void kvm_shared_msr_cpu_online(void)
212{
213 unsigned i;
18863bdd
AK		 214
215 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 216 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 217}
218
d5696725 219void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 220{
221 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
222
2bf78fa7 223 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 224 return;
2bf78fa7
SY		 225 smsr->values[slot].curr = value;
226 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 227 if (!smsr->registered) {
228 smsr->urn.on_user_return = kvm_on_user_return;
229 user_return_notifier_register(&smsr->urn);
230 smsr->registered = true;
231 }
232}
233EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
234
3548bab5
AK		 235static void drop_user_return_notifiers(void *ignore)
236{
237 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
238
239 if (smsr->registered)
240 kvm_on_user_return(&smsr->urn);
241}
242
6866b83e
CO		 243u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
244{
245 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 246 return vcpu->arch.apic_base;
6866b83e 247 else
ad312c7c 248 return vcpu->arch.apic_base;
6866b83e
CO		 249}
250EXPORT_SYMBOL_GPL(kvm_get_apic_base);
251
252void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
253{
254 /* TODO: reserve bits check */
255 if (irqchip_in_kernel(vcpu->kvm))
256 kvm_lapic_set_base(vcpu, data);
257 else
ad312c7c 258 vcpu->arch.apic_base = data;
6866b83e
CO		 259}
260EXPORT_SYMBOL_GPL(kvm_set_apic_base);
261
3fd28fce
ED		 262#define EXCPT_BENIGN 0
263#define EXCPT_CONTRIBUTORY 1
264#define EXCPT_PF 2
265
266static int exception_class(int vector)
267{
268 switch (vector) {
269 case PF_VECTOR:
270 return EXCPT_PF;
271 case DE_VECTOR:
272 case TS_VECTOR:
273 case NP_VECTOR:
274 case SS_VECTOR:
275 case GP_VECTOR:
276 return EXCPT_CONTRIBUTORY;
277 default:
278 break;
279 }
280 return EXCPT_BENIGN;
281}
282
283static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 284 unsigned nr, bool has_error, u32 error_code,
285 bool reinject)
3fd28fce
ED		 286{
287 u32 prev_nr;
288 int class1, class2;
289
3842d135
AK		 290 kvm_make_request(KVM_REQ_EVENT, vcpu);
291
3fd28fce
ED		 292 if (!vcpu->arch.exception.pending) {
293 queue:
294 vcpu->arch.exception.pending = true;
295 vcpu->arch.exception.has_error_code = has_error;
296 vcpu->arch.exception.nr = nr;
297 vcpu->arch.exception.error_code = error_code;
3f0fd292 298 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 299 return;
300 }
301
302 /* to check exception */
303 prev_nr = vcpu->arch.exception.nr;
304 if (prev_nr == DF_VECTOR) {
305 /* triple fault -> shutdown */
a8eeb04a 306 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 307 return;
308 }
309 class1 = exception_class(prev_nr);
310 class2 = exception_class(nr);
311 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
312 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
313 /* generate double fault per SDM Table 5-5 */
314 vcpu->arch.exception.pending = true;
315 vcpu->arch.exception.has_error_code = true;
316 vcpu->arch.exception.nr = DF_VECTOR;
317 vcpu->arch.exception.error_code = 0;
318 } else
319 /* replace previous exception with a new one in a hope
320 that instruction re-execution will regenerate lost
321 exception */
322 goto queue;
323}
324
298101da
AK		 325void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
326{
ce7ddec4 327 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 328}
329EXPORT_SYMBOL_GPL(kvm_queue_exception);
330
ce7ddec4
JR		 331void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
332{
333 kvm_multiple_exception(vcpu, nr, false, 0, true);
334}
335EXPORT_SYMBOL_GPL(kvm_requeue_exception);
336
db8fcefa 337void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 338{
db8fcefa
AP		 339 if (err)
340 kvm_inject_gp(vcpu, 0);
341 else
342 kvm_x86_ops->skip_emulated_instruction(vcpu);
343}
344EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 345
6389ee94 346void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 347{
348 ++vcpu->stat.pf_guest;
6389ee94
AK		 349 vcpu->arch.cr2 = fault->address;
350 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 351}
27d6c865 352EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 353
6389ee94 354void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 355{
6389ee94
AK		 356 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
357 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 358 else
6389ee94 359 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 360}
361
3419ffc8
SY		 362void kvm_inject_nmi(struct kvm_vcpu *vcpu)
363{
7460fb4a
AK		 364 atomic_inc(&vcpu->arch.nmi_queued);
365 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 366}
367EXPORT_SYMBOL_GPL(kvm_inject_nmi);
368
298101da
AK		 369void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
370{
ce7ddec4 371 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 372}
373EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
374
ce7ddec4
JR		 375void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
376{
377 kvm_multiple_exception(vcpu, nr, true, error_code, true);
378}
379EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
380
0a79b009
AK		 381/*
382 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
383 * a #GP and return false.
384 */
385bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 386{
0a79b009
AK		 387 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
388 return true;
389 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
390 return false;
298101da 391}
0a79b009 392EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 393
ec92fe44
JR		 394/*
395 * This function will be used to read from the physical memory of the currently
396 * running guest. The difference to kvm_read_guest_page is that this function
397 * can read from guest physical or from the guest's guest physical memory.
398 */
399int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
400 gfn_t ngfn, void *data, int offset, int len,
401 u32 access)
402{
403 gfn_t real_gfn;
404 gpa_t ngpa;
405
406 ngpa = gfn_to_gpa(ngfn);
407 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
408 if (real_gfn == UNMAPPED_GVA)
409 return -EFAULT;
410
411 real_gfn = gpa_to_gfn(real_gfn);
412
413 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
414}
415EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
416
3d06b8bf
JR		 417int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
418 void *data, int offset, int len, u32 access)
419{
420 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
421 data, offset, len, access);
422}
423
a03490ed
CO		 424/*
425 * Load the pae pdptrs. Return true is they are all valid.
426 */
ff03a073 427int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 428{
429 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
430 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
431 int i;
432 int ret;
ff03a073 433 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 434
ff03a073
JR		 435 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
436 offset * sizeof(u64), sizeof(pdpte),
437 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 438 if (ret < 0) {
439 ret = 0;
440 goto out;
441 }
442 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 443 if (is_present_gpte(pdpte[i]) &&
20c466b5 444 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 445 ret = 0;
446 goto out;
447 }
448 }
449 ret = 1;
450
ff03a073 451 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 452 __set_bit(VCPU_EXREG_PDPTR,
453 (unsigned long *)&vcpu->arch.regs_avail);
454 __set_bit(VCPU_EXREG_PDPTR,
455 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 456out:
a03490ed
CO		 457
458 return ret;
459}
cc4b6871 460EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 461
d835dfec
AK		 462static bool pdptrs_changed(struct kvm_vcpu *vcpu)
463{
ff03a073 464 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 465 bool changed = true;
3d06b8bf
JR		 466 int offset;
467 gfn_t gfn;
d835dfec
AK		 468 int r;
469
470 if (is_long_mode(vcpu) || !is_pae(vcpu))
471 return false;
472
6de4f3ad
AK		 473 if (!test_bit(VCPU_EXREG_PDPTR,
474 (unsigned long *)&vcpu->arch.regs_avail))
475 return true;
476
9f8fe504
AK		 477 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
478 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 479 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
480 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 481 if (r < 0)
482 goto out;
ff03a073 483 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 484out:
d835dfec
AK		 485
486 return changed;
487}
488
49a9b07e 489int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 490{
aad82703
SY		 491 unsigned long old_cr0 = kvm_read_cr0(vcpu);
492 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
493 X86_CR0_CD | X86_CR0_NW;
494
f9a48e6a
AK		 495 cr0 |= X86_CR0_ET;
496
ab344828 497#ifdef CONFIG_X86_64
0f12244f
GN		 498 if (cr0 & 0xffffffff00000000UL)
499 return 1;
ab344828
GN		 500#endif
501
502 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 503
0f12244f
GN		 504 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
505 return 1;
a03490ed 506
0f12244f
GN		 507 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
508 return 1;
a03490ed
CO		 509
510 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
511#ifdef CONFIG_X86_64
f6801dff 512 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 513 int cs_db, cs_l;
514
0f12244f
GN		 515 if (!is_pae(vcpu))
516 return 1;
a03490ed 517 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 518 if (cs_l)
519 return 1;
a03490ed
CO		 520 } else
521#endif
ff03a073 522 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 523 kvm_read_cr3(vcpu)))
0f12244f 524 return 1;
a03490ed
CO		 525 }
526
527 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 528
d170c419 529 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 530 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 531 kvm_async_pf_hash_reset(vcpu);
532 }
e5f3f027 533
aad82703
SY		 534 if ((cr0 ^ old_cr0) & update_bits)
535 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 536 return 0;
537}
2d3ad1f4 538EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 539
2d3ad1f4 540void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 541{
49a9b07e 542 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 543}
2d3ad1f4 544EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 545
2acf923e
DC		 546int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
547{
548 u64 xcr0;
549
550 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
551 if (index != XCR_XFEATURE_ENABLED_MASK)
552 return 1;
553 xcr0 = xcr;
554 if (kvm_x86_ops->get_cpl(vcpu) != 0)
555 return 1;
556 if (!(xcr0 & XSTATE_FP))
557 return 1;
558 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
559 return 1;
560 if (xcr0 & ~host_xcr0)
561 return 1;
562 vcpu->arch.xcr0 = xcr0;
563 vcpu->guest_xcr0_loaded = 0;
564 return 0;
565}
566
567int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
568{
569 if (__kvm_set_xcr(vcpu, index, xcr)) {
570 kvm_inject_gp(vcpu, 0);
571 return 1;
572 }
573 return 0;
574}
575EXPORT_SYMBOL_GPL(kvm_set_xcr);
576
577static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
578{
579 struct kvm_cpuid_entry2 *best;
580
581 best = kvm_find_cpuid_entry(vcpu, 1, 0);
582 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
583}
584
c68b734f
YW		 585static bool guest_cpuid_has_smep(struct kvm_vcpu *vcpu)
586{
587 struct kvm_cpuid_entry2 *best;
588
589 best = kvm_find_cpuid_entry(vcpu, 7, 0);
590 return best && (best->ebx & bit(X86_FEATURE_SMEP));
591}
592
74dc2b4f
YW		 593static bool guest_cpuid_has_fsgsbase(struct kvm_vcpu *vcpu)
594{
595 struct kvm_cpuid_entry2 *best;
596
597 best = kvm_find_cpuid_entry(vcpu, 7, 0);
598 return best && (best->ebx & bit(X86_FEATURE_FSGSBASE));
599}
600
2acf923e
DC		 601static void update_cpuid(struct kvm_vcpu *vcpu)
602{
603 struct kvm_cpuid_entry2 *best;
a3e06bbe 604 struct kvm_lapic *apic = vcpu->arch.apic;
2acf923e
DC		 605
606 best = kvm_find_cpuid_entry(vcpu, 1, 0);
607 if (!best)
608 return;
609
610 /* Update OSXSAVE bit */
611 if (cpu_has_xsave && best->function == 0x1) {
612 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
613 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
614 best->ecx |= bit(X86_FEATURE_OSXSAVE);
615 }
a3e06bbe 616
4d25a066
JK		 617 if (apic) {
618 if (best->ecx & bit(X86_FEATURE_TSC_DEADLINE_TIMER))
619 apic->lapic_timer.timer_mode_mask = 3 << 17;
620 else
621 apic->lapic_timer.timer_mode_mask = 1 << 17;
622 }
2acf923e
DC		 623}
624
a83b29c6 625int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 626{
fc78f519 627 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 628 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
629 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 630 if (cr4 & CR4_RESERVED_BITS)
631 return 1;
a03490ed 632
2acf923e
DC		 633 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
634 return 1;
635
c68b734f
YW		 636 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
637 return 1;
638
74dc2b4f
YW		 639 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
640 return 1;
641
a03490ed 642 if (is_long_mode(vcpu)) {
0f12244f
GN		 643 if (!(cr4 & X86_CR4_PAE))
644 return 1;
a2edf57f
AK		 645 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
646 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 647 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
648 kvm_read_cr3(vcpu)))
0f12244f
GN		 649 return 1;
650
5e1746d6 651 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 652 return 1;
a03490ed 653
aad82703
SY		 654 if ((cr4 ^ old_cr4) & pdptr_bits)
655 kvm_mmu_reset_context(vcpu);
0f12244f 656
2acf923e
DC		 657 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
658 update_cpuid(vcpu);
659
0f12244f
GN		 660 return 0;
661}
2d3ad1f4 662EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 663
2390218b 664int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 665{
9f8fe504 666 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 667 kvm_mmu_sync_roots(vcpu);
d835dfec 668 kvm_mmu_flush_tlb(vcpu);
0f12244f 669 return 0;
d835dfec
AK		 670 }
671
a03490ed 672 if (is_long_mode(vcpu)) {
0f12244f
GN		 673 if (cr3 & CR3_L_MODE_RESERVED_BITS)
674 return 1;
a03490ed
CO		 675 } else {
676 if (is_pae(vcpu)) {
0f12244f
GN		 677 if (cr3 & CR3_PAE_RESERVED_BITS)
678 return 1;
ff03a073
JR		 679 if (is_paging(vcpu) &&
680 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 681 return 1;
a03490ed
CO		 682 }
683 /*
684 * We don't check reserved bits in nonpae mode, because
685 * this isn't enforced, and VMware depends on this.
686 */
687 }
688
a03490ed
CO		 689 /*
690 * Does the new cr3 value map to physical memory? (Note, we
691 * catch an invalid cr3 even in real-mode, because it would
692 * cause trouble later on when we turn on paging anyway.)
693 *
694 * A real CPU would silently accept an invalid cr3 and would
695 * attempt to use it - with largely undefined (and often hard
696 * to debug) behavior on the guest side.
697 */
698 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 699 return 1;
700 vcpu->arch.cr3 = cr3;
aff48baa 701 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 702 vcpu->arch.mmu.new_cr3(vcpu);
703 return 0;
704}
2d3ad1f4 705EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 706
eea1cff9 707int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 708{
0f12244f
GN		 709 if (cr8 & CR8_RESERVED_BITS)
710 return 1;
a03490ed
CO		 711 if (irqchip_in_kernel(vcpu->kvm))
712 kvm_lapic_set_tpr(vcpu, cr8);
713 else
ad312c7c 714 vcpu->arch.cr8 = cr8;
0f12244f
GN		 715 return 0;
716}
2d3ad1f4 717EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 718
2d3ad1f4 719unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 720{
721 if (irqchip_in_kernel(vcpu->kvm))
722 return kvm_lapic_get_cr8(vcpu);
723 else
ad312c7c 724 return vcpu->arch.cr8;
a03490ed 725}
2d3ad1f4 726EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 727
338dbc97 728static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 729{
730 switch (dr) {
731 case 0 ... 3:
732 vcpu->arch.db[dr] = val;
733 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
734 vcpu->arch.eff_db[dr] = val;
735 break;
736 case 4:
338dbc97
GN		 737 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
738 return 1; /* #UD */
020df079
GN		 739 /* fall through */
740 case 6:
338dbc97
GN		 741 if (val & 0xffffffff00000000ULL)
742 return -1; /* #GP */
020df079
GN		 743 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
744 break;
745 case 5:
338dbc97
GN		 746 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
747 return 1; /* #UD */
020df079
GN		 748 /* fall through */
749 default: /* 7 */
338dbc97
GN		 750 if (val & 0xffffffff00000000ULL)
751 return -1; /* #GP */
020df079
GN		 752 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
753 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
754 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
755 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
756 }
757 break;
758 }
759
760 return 0;
761}
338dbc97
GN		 762
763int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
764{
765 int res;
766
767 res = __kvm_set_dr(vcpu, dr, val);
768 if (res > 0)
769 kvm_queue_exception(vcpu, UD_VECTOR);
770 else if (res < 0)
771 kvm_inject_gp(vcpu, 0);
772
773 return res;
774}
020df079
GN		 775EXPORT_SYMBOL_GPL(kvm_set_dr);
776
338dbc97 777static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 778{
779 switch (dr) {
780 case 0 ... 3:
781 *val = vcpu->arch.db[dr];
782 break;
783 case 4:
338dbc97 784 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 785 return 1;
020df079
GN		 786 /* fall through */
787 case 6:
788 *val = vcpu->arch.dr6;
789 break;
790 case 5:
338dbc97 791 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 792 return 1;
020df079
GN		 793 /* fall through */
794 default: /* 7 */
795 *val = vcpu->arch.dr7;
796 break;
797 }
798
799 return 0;
800}
338dbc97
GN		 801
802int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
803{
804 if (_kvm_get_dr(vcpu, dr, val)) {
805 kvm_queue_exception(vcpu, UD_VECTOR);
806 return 1;
807 }
808 return 0;
809}
020df079
GN		 810EXPORT_SYMBOL_GPL(kvm_get_dr);
811
043405e1
CO		 812/*
813 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
814 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
815 *
816 * This list is modified at module load time to reflect the
e3267cbb
GC		 817 * capabilities of the host cpu. This capabilities test skips MSRs that are
818 * kvm-specific. Those are put in the beginning of the list.
043405e1 819 */
e3267cbb 820
c9aaa895 821#define KVM_SAVE_MSRS_BEGIN 9
043405e1 822static u32 msrs_to_save[] = {
e3267cbb 823 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 824 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 825 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 826 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
043405e1 827 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 828 MSR_STAR,
043405e1
CO		 829#ifdef CONFIG_X86_64
830 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
831#endif
e90aa41e 832 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 833};
834
835static unsigned num_msrs_to_save;
836
837static u32 emulated_msrs[] = {
a3e06bbe 838 MSR_IA32_TSCDEADLINE,
043405e1 839 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 840 MSR_IA32_MCG_STATUS,
841 MSR_IA32_MCG_CTL,
043405e1
CO		 842};
843
b69e8cae 844static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 845{
aad82703
SY		 846 u64 old_efer = vcpu->arch.efer;
847
b69e8cae
RJ		 848 if (efer & efer_reserved_bits)
849 return 1;
15c4a640
CO		 850
851 if (is_paging(vcpu)
b69e8cae
RJ		 852 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
853 return 1;
15c4a640 854
1b2fd70c
AG		 855 if (efer & EFER_FFXSR) {
856 struct kvm_cpuid_entry2 *feat;
857
858 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 859 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
860 return 1;
1b2fd70c
AG		 861 }
862
d8017474
AG		 863 if (efer & EFER_SVME) {
864 struct kvm_cpuid_entry2 *feat;
865
866 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 867 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
868 return 1;
d8017474
AG		 869 }
870
15c4a640 871 efer &= ~EFER_LMA;
f6801dff 872 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 873
a3d204e2
SY		 874 kvm_x86_ops->set_efer(vcpu, efer);
875
9645bb56 876 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 877
aad82703
SY		 878 /* Update reserved bits */
879 if ((efer ^ old_efer) & EFER_NX)
880 kvm_mmu_reset_context(vcpu);
881
b69e8cae 882 return 0;
15c4a640
CO		 883}
884
f2b4b7dd
JR		 885void kvm_enable_efer_bits(u64 mask)
886{
887 efer_reserved_bits &= ~mask;
888}
889EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
890
891
15c4a640
CO		 892/*
893 * Writes msr value into into the appropriate "register".
894 * Returns 0 on success, non-0 otherwise.
895 * Assumes vcpu_load() was already called.
896 */
897int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
898{
899 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
900}
901
313a3dc7
CO		 902/*
903 * Adapt set_msr() to msr_io()'s calling convention
904 */
905static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
906{
907 return kvm_set_msr(vcpu, index, *data);
908}
909
18068523
GOC		 910static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
911{
9ed3c444
AK		 912 int version;
913 int r;
50d0a0f9 914 struct pvclock_wall_clock wc;
923de3cf 915 struct timespec boot;
18068523
GOC		 916
917 if (!wall_clock)
918 return;
919
9ed3c444
AK		 920 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
921 if (r)
922 return;
923
924 if (version & 1)
925 ++version; /* first time write, random junk */
926
927 ++version;
18068523 928
18068523
GOC		 929 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
930
50d0a0f9
GH		 931 /*
932 * The guest calculates current wall clock time by adding
34c238a1 933 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 934 * wall clock specified here. guest system time equals host
935 * system time for us, thus we must fill in host boot time here.
936 */
923de3cf 937 getboottime(&boot);
50d0a0f9
GH		 938
939 wc.sec = boot.tv_sec;
940 wc.nsec = boot.tv_nsec;
941 wc.version = version;
18068523
GOC		 942
943 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
944
945 version++;
946 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 947}
948
50d0a0f9
GH		 949static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
950{
951 uint32_t quotient, remainder;
952
953 /* Don't try to replace with do_div(), this one calculates
954 * "(dividend << 32) / divisor" */
955 __asm__ ( "divl %4"
956 : "=a" (quotient), "=d" (remainder)
957 : "0" (0), "1" (dividend), "r" (divisor) );
958 return quotient;
959}
960
5f4e3f88
ZA		 961static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
962 s8 *pshift, u32 *pmultiplier)
50d0a0f9 963{
5f4e3f88 964 uint64_t scaled64;
50d0a0f9
GH		 965 int32_t shift = 0;
966 uint64_t tps64;
967 uint32_t tps32;
968
5f4e3f88
ZA		 969 tps64 = base_khz * 1000LL;
970 scaled64 = scaled_khz * 1000LL;
50933623 971 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 972 tps64 >>= 1;
973 shift--;
974 }
975
976 tps32 = (uint32_t)tps64;
50933623
JK		 977 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
978 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 979 scaled64 >>= 1;
980 else
981 tps32 <<= 1;
50d0a0f9
GH		 982 shift++;
983 }
984
5f4e3f88
ZA		 985 *pshift = shift;
986 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 987
5f4e3f88
ZA		 988 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
989 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 990}
991
759379dd
ZA		 992static inline u64 get_kernel_ns(void)
993{
994 struct timespec ts;
995
996 WARN_ON(preemptible());
997 ktime_get_ts(&ts);
998 monotonic_to_bootbased(&ts);
999 return timespec_to_ns(&ts);
50d0a0f9
GH		 1000}
1001
c8076604 1002static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1003unsigned long max_tsc_khz;
c8076604 1004
8cfdc000
ZA		 1005static inline int kvm_tsc_changes_freq(void)
1006{
1007 int cpu = get_cpu();
1008 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
1009 cpufreq_quick_get(cpu) != 0;
1010 put_cpu();
1011 return ret;
1012}
1013
a3e06bbe 1014u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu)
1e993611
JR		 1015{
1016 if (vcpu->arch.virtual_tsc_khz)
1017 return vcpu->arch.virtual_tsc_khz;
1018 else
1019 return __this_cpu_read(cpu_tsc_khz);
1020}
1021
857e4099 1022static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
759379dd 1023{
217fc9cf
AK		 1024 u64 ret;
1025
759379dd
ZA		 1026 WARN_ON(preemptible());
1027 if (kvm_tsc_changes_freq())
1028 printk_once(KERN_WARNING
1029 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
857e4099 1030 ret = nsec * vcpu_tsc_khz(vcpu);
217fc9cf
AK		 1031 do_div(ret, USEC_PER_SEC);
1032 return ret;
759379dd
ZA		 1033}
1034
1e993611 1035static void kvm_init_tsc_catchup(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
c285545f
ZA		 1036{
1037 /* Compute a scale to convert nanoseconds in TSC cycles */
1038 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1e993611
JR		 1039 &vcpu->arch.tsc_catchup_shift,
1040 &vcpu->arch.tsc_catchup_mult);
c285545f
ZA		 1041}
1042
1043static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1044{
1045 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
1e993611
JR		 1046 vcpu->arch.tsc_catchup_mult,
1047 vcpu->arch.tsc_catchup_shift);
c285545f
ZA		 1048 tsc += vcpu->arch.last_tsc_write;
1049 return tsc;
1050}
1051
99e3e30a
ZA		 1052void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1053{
1054 struct kvm *kvm = vcpu->kvm;
f38e098f 1055 u64 offset, ns, elapsed;
99e3e30a 1056 unsigned long flags;
46543ba4 1057 s64 sdiff;
99e3e30a 1058
038f8c11 1059 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1060 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1061 ns = get_kernel_ns();
f38e098f 1062 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 1063 sdiff = data - kvm->arch.last_tsc_write;
1064 if (sdiff < 0)
1065 sdiff = -sdiff;
f38e098f
ZA		 1066
1067 /*
46543ba4 1068 * Special case: close write to TSC within 5 seconds of
f38e098f 1069 * another CPU is interpreted as an attempt to synchronize
0d2eb44f 1070 * The 5 seconds is to accommodate host load / swapping as
46543ba4 1071 * well as any reset of TSC during the boot process.
f38e098f
ZA		 1072 *
1073 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 1074 * or make a best guest using elapsed value.
f38e098f 1075 */
857e4099 1076 if (sdiff < nsec_to_cycles(vcpu, 5ULL * NSEC_PER_SEC) &&
46543ba4 1077 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 1078 if (!check_tsc_unstable()) {
1079 offset = kvm->arch.last_tsc_offset;
1080 pr_debug("kvm: matched tsc offset for %llu\n", data);
1081 } else {
857e4099 1082 u64 delta = nsec_to_cycles(vcpu, elapsed);
759379dd
ZA		 1083 offset += delta;
1084 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1085 }
1086 ns = kvm->arch.last_tsc_nsec;
1087 }
1088 kvm->arch.last_tsc_nsec = ns;
1089 kvm->arch.last_tsc_write = data;
1090 kvm->arch.last_tsc_offset = offset;
99e3e30a 1091 kvm_x86_ops->write_tsc_offset(vcpu, offset);
038f8c11 1092 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
99e3e30a
ZA		 1093
1094 /* Reset of TSC must disable overshoot protection below */
1095 vcpu->arch.hv_clock.tsc_timestamp = 0;
c285545f
ZA		 1096 vcpu->arch.last_tsc_write = data;
1097 vcpu->arch.last_tsc_nsec = ns;
99e3e30a
ZA		 1098}
1099EXPORT_SYMBOL_GPL(kvm_write_tsc);
1100
34c238a1 1101static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1102{
18068523
GOC		 1103 unsigned long flags;
1104 struct kvm_vcpu_arch *vcpu = &v->arch;
1105 void *shared_kaddr;
463656c0 1106 unsigned long this_tsc_khz;
1d5f066e
ZA		 1107 s64 kernel_ns, max_kernel_ns;
1108 u64 tsc_timestamp;
18068523 1109
18068523
GOC		 1110 /* Keep irq disabled to prevent changes to the clock */
1111 local_irq_save(flags);
d5c1785d 1112 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v);
759379dd 1113 kernel_ns = get_kernel_ns();
1e993611 1114 this_tsc_khz = vcpu_tsc_khz(v);
8cfdc000 1115 if (unlikely(this_tsc_khz == 0)) {
c285545f 1116 local_irq_restore(flags);
34c238a1 1117 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1118 return 1;
1119 }
18068523 1120
c285545f
ZA		 1121 /*
1122 * We may have to catch up the TSC to match elapsed wall clock
1123 * time for two reasons, even if kvmclock is used.
1124 * 1) CPU could have been running below the maximum TSC rate
1125 * 2) Broken TSC compensation resets the base at each VCPU
1126 * entry to avoid unknown leaps of TSC even when running
1127 * again on the same CPU. This may cause apparent elapsed
1128 * time to disappear, and the guest to stand still or run
1129 * very slowly.
1130 */
1131 if (vcpu->tsc_catchup) {
1132 u64 tsc = compute_guest_tsc(v, kernel_ns);
1133 if (tsc > tsc_timestamp) {
1134 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1135 tsc_timestamp = tsc;
1136 }
50d0a0f9
GH		 1137 }
1138
18068523
GOC		 1139 local_irq_restore(flags);
1140
c285545f
ZA		 1141 if (!vcpu->time_page)
1142 return 0;
18068523 1143
1d5f066e
ZA		 1144 /*
1145 * Time as measured by the TSC may go backwards when resetting the base
1146 * tsc_timestamp. The reason for this is that the TSC resolution is
1147 * higher than the resolution of the other clock scales. Thus, many
1148 * possible measurments of the TSC correspond to one measurement of any
1149 * other clock, and so a spread of values is possible. This is not a
1150 * problem for the computation of the nanosecond clock; with TSC rates
1151 * around 1GHZ, there can only be a few cycles which correspond to one
1152 * nanosecond value, and any path through this code will inevitably
1153 * take longer than that. However, with the kernel_ns value itself,
1154 * the precision may be much lower, down to HZ granularity. If the
1155 * first sampling of TSC against kernel_ns ends in the low part of the
1156 * range, and the second in the high end of the range, we can get:
1157 *
1158 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1159 *
1160 * As the sampling errors potentially range in the thousands of cycles,
1161 * it is possible such a time value has already been observed by the
1162 * guest. To protect against this, we must compute the system time as
1163 * observed by the guest and ensure the new system time is greater.
1164 */
1165 max_kernel_ns = 0;
1166 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1167 max_kernel_ns = vcpu->last_guest_tsc -
1168 vcpu->hv_clock.tsc_timestamp;
1169 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1170 vcpu->hv_clock.tsc_to_system_mul,
1171 vcpu->hv_clock.tsc_shift);
1172 max_kernel_ns += vcpu->last_kernel_ns;
1173 }
afbcf7ab 1174
e48672fa 1175 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1176 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1177 &vcpu->hv_clock.tsc_shift,
1178 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1179 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1180 }
1181
1d5f066e
ZA		 1182 if (max_kernel_ns > kernel_ns)
1183 kernel_ns = max_kernel_ns;
1184
8cfdc000 1185 /* With all the info we got, fill in the values */
1d5f066e 1186 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1187 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1188 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1189 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1190 vcpu->hv_clock.flags = 0;
1191
18068523
GOC		 1192 /*
1193 * The interface expects us to write an even number signaling that the
1194 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1195 * state, we just increase by 2 at the end.
18068523 1196 */
50d0a0f9 1197 vcpu->hv_clock.version += 2;
18068523
GOC		 1198
1199 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1200
1201 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1202 sizeof(vcpu->hv_clock));
18068523
GOC		 1203
1204 kunmap_atomic(shared_kaddr, KM_USER0);
1205
1206 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1207 return 0;
c8076604
GH		 1208}
1209
9ba075a6
AK		 1210static bool msr_mtrr_valid(unsigned msr)
1211{
1212 switch (msr) {
1213 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1214 case MSR_MTRRfix64K_00000:
1215 case MSR_MTRRfix16K_80000:
1216 case MSR_MTRRfix16K_A0000:
1217 case MSR_MTRRfix4K_C0000:
1218 case MSR_MTRRfix4K_C8000:
1219 case MSR_MTRRfix4K_D0000:
1220 case MSR_MTRRfix4K_D8000:
1221 case MSR_MTRRfix4K_E0000:
1222 case MSR_MTRRfix4K_E8000:
1223 case MSR_MTRRfix4K_F0000:
1224 case MSR_MTRRfix4K_F8000:
1225 case MSR_MTRRdefType:
1226 case MSR_IA32_CR_PAT:
1227 return true;
1228 case 0x2f8:
1229 return true;
1230 }
1231 return false;
1232}
1233
d6289b93
MT		 1234static bool valid_pat_type(unsigned t)
1235{
1236 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1237}
1238
1239static bool valid_mtrr_type(unsigned t)
1240{
1241 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1242}
1243
1244static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1245{
1246 int i;
1247
1248 if (!msr_mtrr_valid(msr))
1249 return false;
1250
1251 if (msr == MSR_IA32_CR_PAT) {
1252 for (i = 0; i < 8; i++)
1253 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1254 return false;
1255 return true;
1256 } else if (msr == MSR_MTRRdefType) {
1257 if (data & ~0xcff)
1258 return false;
1259 return valid_mtrr_type(data & 0xff);
1260 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1261 for (i = 0; i < 8 ; i++)
1262 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1263 return false;
1264 return true;
1265 }
1266
1267 /* variable MTRRs */
1268 return valid_mtrr_type(data & 0xff);
1269}
1270
9ba075a6
AK		 1271static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1272{
0bed3b56
SY		 1273 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1274
d6289b93 1275 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1276 return 1;
1277
0bed3b56
SY		 1278 if (msr == MSR_MTRRdefType) {
1279 vcpu->arch.mtrr_state.def_type = data;
1280 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1281 } else if (msr == MSR_MTRRfix64K_00000)
1282 p[0] = data;
1283 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1284 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1285 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1286 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1287 else if (msr == MSR_IA32_CR_PAT)
1288 vcpu->arch.pat = data;
1289 else { /* Variable MTRRs */
1290 int idx, is_mtrr_mask;
1291 u64 *pt;
1292
1293 idx = (msr - 0x200) / 2;
1294 is_mtrr_mask = msr - 0x200 - 2 * idx;
1295 if (!is_mtrr_mask)
1296 pt =
1297 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1298 else
1299 pt =
1300 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1301 *pt = data;
1302 }
1303
1304 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1305 return 0;
1306}
15c4a640 1307
890ca9ae 1308static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1309{
890ca9ae
HY		 1310 u64 mcg_cap = vcpu->arch.mcg_cap;
1311 unsigned bank_num = mcg_cap & 0xff;
1312
15c4a640 1313 switch (msr) {
15c4a640 1314 case MSR_IA32_MCG_STATUS:
890ca9ae 1315 vcpu->arch.mcg_status = data;
15c4a640 1316 break;
c7ac679c 1317 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1318 if (!(mcg_cap & MCG_CTL_P))
1319 return 1;
1320 if (data != 0 && data != ~(u64)0)
1321 return -1;
1322 vcpu->arch.mcg_ctl = data;
1323 break;
1324 default:
1325 if (msr >= MSR_IA32_MC0_CTL &&
1326 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1327 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1328 /* only 0 or all 1s can be written to IA32_MCi_CTL
1329 * some Linux kernels though clear bit 10 in bank 4 to
1330 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1331 * this to avoid an uncatched #GP in the guest
1332 */
890ca9ae 1333 if ((offset & 0x3) == 0 &&
114be429 1334 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1335 return -1;
1336 vcpu->arch.mce_banks[offset] = data;
1337 break;
1338 }
1339 return 1;
1340 }
1341 return 0;
1342}
1343
ffde22ac
ES		 1344static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1345{
1346 struct kvm *kvm = vcpu->kvm;
1347 int lm = is_long_mode(vcpu);
1348 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1349 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1350 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1351 : kvm->arch.xen_hvm_config.blob_size_32;
1352 u32 page_num = data & ~PAGE_MASK;
1353 u64 page_addr = data & PAGE_MASK;
1354 u8 *page;
1355 int r;
1356
1357 r = -E2BIG;
1358 if (page_num >= blob_size)
1359 goto out;
1360 r = -ENOMEM;
1361 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1362 if (!page)
1363 goto out;
1364 r = -EFAULT;
1365 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1366 goto out_free;
1367 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1368 goto out_free;
1369 r = 0;
1370out_free:
1371 kfree(page);
1372out:
1373 return r;
1374}
1375
55cd8e5a
GN		 1376static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1377{
1378 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1379}
1380
1381static bool kvm_hv_msr_partition_wide(u32 msr)
1382{
1383 bool r = false;
1384 switch (msr) {
1385 case HV_X64_MSR_GUEST_OS_ID:
1386 case HV_X64_MSR_HYPERCALL:
1387 r = true;
1388 break;
1389 }
1390
1391 return r;
1392}
1393
1394static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1395{
1396 struct kvm *kvm = vcpu->kvm;
1397
1398 switch (msr) {
1399 case HV_X64_MSR_GUEST_OS_ID:
1400 kvm->arch.hv_guest_os_id = data;
1401 /* setting guest os id to zero disables hypercall page */
1402 if (!kvm->arch.hv_guest_os_id)
1403 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1404 break;
1405 case HV_X64_MSR_HYPERCALL: {
1406 u64 gfn;
1407 unsigned long addr;
1408 u8 instructions[4];
1409
1410 /* if guest os id is not set hypercall should remain disabled */
1411 if (!kvm->arch.hv_guest_os_id)
1412 break;
1413 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1414 kvm->arch.hv_hypercall = data;
1415 break;
1416 }
1417 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1418 addr = gfn_to_hva(kvm, gfn);
1419 if (kvm_is_error_hva(addr))
1420 return 1;
1421 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1422 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1423 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1424 return 1;
1425 kvm->arch.hv_hypercall = data;
1426 break;
1427 }
1428 default:
1429 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1430 "data 0x%llx\n", msr, data);
1431 return 1;
1432 }
1433 return 0;
1434}
1435
1436static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1437{
10388a07
GN		 1438 switch (msr) {
1439 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1440 unsigned long addr;
55cd8e5a 1441
10388a07
GN		 1442 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1443 vcpu->arch.hv_vapic = data;
1444 break;
1445 }
1446 addr = gfn_to_hva(vcpu->kvm, data >>
1447 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1448 if (kvm_is_error_hva(addr))
1449 return 1;
8b0cedff 1450 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1451 return 1;
1452 vcpu->arch.hv_vapic = data;
1453 break;
1454 }
1455 case HV_X64_MSR_EOI:
1456 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1457 case HV_X64_MSR_ICR:
1458 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1459 case HV_X64_MSR_TPR:
1460 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1461 default:
1462 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1463 "data 0x%llx\n", msr, data);
1464 return 1;
1465 }
1466
1467 return 0;
55cd8e5a
GN		 1468}
1469
344d9588
GN		 1470static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1471{
1472 gpa_t gpa = data & ~0x3f;
1473
6adba527
GN		 1474 /* Bits 2:5 are resrved, Should be zero */
1475 if (data & 0x3c)
344d9588
GN		 1476 return 1;
1477
1478 vcpu->arch.apf.msr_val = data;
1479
1480 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1481 kvm_clear_async_pf_completion_queue(vcpu);
1482 kvm_async_pf_hash_reset(vcpu);
1483 return 0;
1484 }
1485
1486 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1487 return 1;
1488
6adba527 1489 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1490 kvm_async_pf_wakeup_all(vcpu);
1491 return 0;
1492}
1493
12f9a48f
GC		 1494static void kvmclock_reset(struct kvm_vcpu *vcpu)
1495{
1496 if (vcpu->arch.time_page) {
1497 kvm_release_page_dirty(vcpu->arch.time_page);
1498 vcpu->arch.time_page = NULL;
1499 }
1500}
1501
c9aaa895
GC		 1502static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1503{
1504 u64 delta;
1505
1506 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1507 return;
1508
1509 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1510 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1511 vcpu->arch.st.accum_steal = delta;
1512}
1513
1514static void record_steal_time(struct kvm_vcpu *vcpu)
1515{
1516 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1517 return;
1518
1519 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1520 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1521 return;
1522
1523 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1524 vcpu->arch.st.steal.version += 2;
1525 vcpu->arch.st.accum_steal = 0;
1526
1527 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1528 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1529}
1530
15c4a640
CO		 1531int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1532{
1533 switch (msr) {
15c4a640 1534 case MSR_EFER:
b69e8cae 1535 return set_efer(vcpu, data);
8f1589d9
AP		 1536 case MSR_K7_HWCR:
1537 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1538 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1539 if (data != 0) {
1540 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1541 data);
1542 return 1;
1543 }
15c4a640 1544 break;
f7c6d140
AP		 1545 case MSR_FAM10H_MMIO_CONF_BASE:
1546 if (data != 0) {
1547 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1548 "0x%llx\n", data);
1549 return 1;
1550 }
15c4a640 1551 break;
c323c0e5 1552 case MSR_AMD64_NB_CFG:
c7ac679c 1553 break;
b5e2fec0
AG		 1554 case MSR_IA32_DEBUGCTLMSR:
1555 if (!data) {
1556 /* We support the non-activated case already */
1557 break;
1558 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1559 /* Values other than LBR and BTF are vendor-specific,
1560 thus reserved and should throw a #GP */
1561 return 1;
1562 }
1563 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1564 __func__, data);
1565 break;
15c4a640
CO		 1566 case MSR_IA32_UCODE_REV:
1567 case MSR_IA32_UCODE_WRITE:
61a6bd67 1568 case MSR_VM_HSAVE_PA:
6098ca93 1569 case MSR_AMD64_PATCH_LOADER:
15c4a640 1570 break;
9ba075a6
AK		 1571 case 0x200 ... 0x2ff:
1572 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1573 case MSR_IA32_APICBASE:
1574 kvm_set_apic_base(vcpu, data);
1575 break;
0105d1a5
GN		 1576 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1577 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1578 case MSR_IA32_TSCDEADLINE:
1579 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1580 break;
15c4a640 1581 case MSR_IA32_MISC_ENABLE:
ad312c7c 1582 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1583 break;
11c6bffa 1584 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1585 case MSR_KVM_WALL_CLOCK:
1586 vcpu->kvm->arch.wall_clock = data;
1587 kvm_write_wall_clock(vcpu->kvm, data);
1588 break;
11c6bffa 1589 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1590 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1591 kvmclock_reset(vcpu);
18068523
GOC		 1592
1593 vcpu->arch.time = data;
c285545f 1594 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1595
1596 /* we verify if the enable bit is set... */
1597 if (!(data & 1))
1598 break;
1599
1600 /* ...but clean it before doing the actual write */
1601 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1602
18068523
GOC		 1603 vcpu->arch.time_page =
1604 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1605
1606 if (is_error_page(vcpu->arch.time_page)) {
1607 kvm_release_page_clean(vcpu->arch.time_page);
1608 vcpu->arch.time_page = NULL;
1609 }
18068523
GOC		 1610 break;
1611 }
344d9588
GN		 1612 case MSR_KVM_ASYNC_PF_EN:
1613 if (kvm_pv_enable_async_pf(vcpu, data))
1614 return 1;
1615 break;
c9aaa895
GC		 1616 case MSR_KVM_STEAL_TIME:
1617
1618 if (unlikely(!sched_info_on()))
1619 return 1;
1620
1621 if (data & KVM_STEAL_RESERVED_MASK)
1622 return 1;
1623
1624 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1625 data & KVM_STEAL_VALID_BITS))
1626 return 1;
1627
1628 vcpu->arch.st.msr_val = data;
1629
1630 if (!(data & KVM_MSR_ENABLED))
1631 break;
1632
1633 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1634
1635 preempt_disable();
1636 accumulate_steal_time(vcpu);
1637 preempt_enable();
1638
1639 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1640
1641 break;
1642
890ca9ae
HY		 1643 case MSR_IA32_MCG_CTL:
1644 case MSR_IA32_MCG_STATUS:
1645 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1646 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1647
1648 /* Performance counters are not protected by a CPUID bit,
1649 * so we should check all of them in the generic path for the sake of
1650 * cross vendor migration.
1651 * Writing a zero into the event select MSRs disables them,
1652 * which we perfectly emulate ;-). Any other value should be at least
1653 * reported, some guests depend on them.
1654 */
1655 case MSR_P6_EVNTSEL0:
1656 case MSR_P6_EVNTSEL1:
1657 case MSR_K7_EVNTSEL0:
1658 case MSR_K7_EVNTSEL1:
1659 case MSR_K7_EVNTSEL2:
1660 case MSR_K7_EVNTSEL3:
1661 if (data != 0)
1662 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1663 "0x%x data 0x%llx\n", msr, data);
1664 break;
1665 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1666 * so we ignore writes to make it happy.
1667 */
1668 case MSR_P6_PERFCTR0:
1669 case MSR_P6_PERFCTR1:
1670 case MSR_K7_PERFCTR0:
1671 case MSR_K7_PERFCTR1:
1672 case MSR_K7_PERFCTR2:
1673 case MSR_K7_PERFCTR3:
1674 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1675 "0x%x data 0x%llx\n", msr, data);
1676 break;
84e0cefa
JS		 1677 case MSR_K7_CLK_CTL:
1678 /*
1679 * Ignore all writes to this no longer documented MSR.
1680 * Writes are only relevant for old K7 processors,
1681 * all pre-dating SVM, but a recommended workaround from
1682 * AMD for these chips. It is possible to speicify the
1683 * affected processor models on the command line, hence
1684 * the need to ignore the workaround.
1685 */
1686 break;
55cd8e5a
GN		 1687 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1688 if (kvm_hv_msr_partition_wide(msr)) {
1689 int r;
1690 mutex_lock(&vcpu->kvm->lock);
1691 r = set_msr_hyperv_pw(vcpu, msr, data);
1692 mutex_unlock(&vcpu->kvm->lock);
1693 return r;
1694 } else
1695 return set_msr_hyperv(vcpu, msr, data);
1696 break;
91c9c3ed 1697 case MSR_IA32_BBL_CR_CTL3:
1698 /* Drop writes to this legacy MSR -- see rdmsr
1699 * counterpart for further detail.
1700 */
1701 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1702 break;
15c4a640 1703 default:
ffde22ac
ES		 1704 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1705 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1706 if (!ignore_msrs) {
1707 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1708 msr, data);
1709 return 1;
1710 } else {
1711 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1712 msr, data);
1713 break;
1714 }
15c4a640
CO		 1715 }
1716 return 0;
1717}
1718EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1719
1720
1721/*
1722 * Reads an msr value (of 'msr_index') into 'pdata'.
1723 * Returns 0 on success, non-0 otherwise.
1724 * Assumes vcpu_load() was already called.
1725 */
1726int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1727{
1728 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1729}
1730
9ba075a6
AK		 1731static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1732{
0bed3b56
SY		 1733 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1734
9ba075a6
AK		 1735 if (!msr_mtrr_valid(msr))
1736 return 1;
1737
0bed3b56
SY		 1738 if (msr == MSR_MTRRdefType)
1739 *pdata = vcpu->arch.mtrr_state.def_type +
1740 (vcpu->arch.mtrr_state.enabled << 10);
1741 else if (msr == MSR_MTRRfix64K_00000)
1742 *pdata = p[0];
1743 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1744 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1745 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1746 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1747 else if (msr == MSR_IA32_CR_PAT)
1748 *pdata = vcpu->arch.pat;
1749 else { /* Variable MTRRs */
1750 int idx, is_mtrr_mask;
1751 u64 *pt;
1752
1753 idx = (msr - 0x200) / 2;
1754 is_mtrr_mask = msr - 0x200 - 2 * idx;
1755 if (!is_mtrr_mask)
1756 pt =
1757 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1758 else
1759 pt =
1760 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1761 *pdata = *pt;
1762 }
1763
9ba075a6
AK		 1764 return 0;
1765}
1766
890ca9ae 1767static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1768{
1769 u64 data;
890ca9ae
HY		 1770 u64 mcg_cap = vcpu->arch.mcg_cap;
1771 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1772
1773 switch (msr) {
15c4a640
CO		 1774 case MSR_IA32_P5_MC_ADDR:
1775 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1776 data = 0;
1777 break;
15c4a640 1778 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1779 data = vcpu->arch.mcg_cap;
1780 break;
c7ac679c 1781 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1782 if (!(mcg_cap & MCG_CTL_P))
1783 return 1;
1784 data = vcpu->arch.mcg_ctl;
1785 break;
1786 case MSR_IA32_MCG_STATUS:
1787 data = vcpu->arch.mcg_status;
1788 break;
1789 default:
1790 if (msr >= MSR_IA32_MC0_CTL &&
1791 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1792 u32 offset = msr - MSR_IA32_MC0_CTL;
1793 data = vcpu->arch.mce_banks[offset];
1794 break;
1795 }
1796 return 1;
1797 }
1798 *pdata = data;
1799 return 0;
1800}
1801
55cd8e5a
GN		 1802static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1803{
1804 u64 data = 0;
1805 struct kvm *kvm = vcpu->kvm;
1806
1807 switch (msr) {
1808 case HV_X64_MSR_GUEST_OS_ID:
1809 data = kvm->arch.hv_guest_os_id;
1810 break;
1811 case HV_X64_MSR_HYPERCALL:
1812 data = kvm->arch.hv_hypercall;
1813 break;
1814 default:
1815 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1816 return 1;
1817 }
1818
1819 *pdata = data;
1820 return 0;
1821}
1822
1823static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1824{
1825 u64 data = 0;
1826
1827 switch (msr) {
1828 case HV_X64_MSR_VP_INDEX: {
1829 int r;
1830 struct kvm_vcpu *v;
1831 kvm_for_each_vcpu(r, v, vcpu->kvm)
1832 if (v == vcpu)
1833 data = r;
1834 break;
1835 }
10388a07
GN		 1836 case HV_X64_MSR_EOI:
1837 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1838 case HV_X64_MSR_ICR:
1839 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1840 case HV_X64_MSR_TPR:
1841 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 1842 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 1843 data = vcpu->arch.hv_vapic;
1844 break;
55cd8e5a
GN		 1845 default:
1846 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1847 return 1;
1848 }
1849 *pdata = data;
1850 return 0;
1851}
1852
890ca9ae
HY		 1853int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1854{
1855 u64 data;
1856
1857 switch (msr) {
890ca9ae 1858 case MSR_IA32_PLATFORM_ID:
15c4a640 1859 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1860 case MSR_IA32_DEBUGCTLMSR:
1861 case MSR_IA32_LASTBRANCHFROMIP:
1862 case MSR_IA32_LASTBRANCHTOIP:
1863 case MSR_IA32_LASTINTFROMIP:
1864 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1865 case MSR_K8_SYSCFG:
1866 case MSR_K7_HWCR:
61a6bd67 1867 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1868 case MSR_P6_PERFCTR0:
1869 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1870 case MSR_P6_EVNTSEL0:
1871 case MSR_P6_EVNTSEL1:
9e699624 1872 case MSR_K7_EVNTSEL0:
1f3ee616 1873 case MSR_K7_PERFCTR0:
1fdbd48c 1874 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1875 case MSR_AMD64_NB_CFG:
f7c6d140 1876 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1877 data = 0;
1878 break;
742bc670
MT		 1879 case MSR_IA32_UCODE_REV:
1880 data = 0x100000000ULL;
1881 break;
9ba075a6
AK		 1882 case MSR_MTRRcap:
1883 data = 0x500 | KVM_NR_VAR_MTRR;
1884 break;
1885 case 0x200 ... 0x2ff:
1886 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1887 case 0xcd: /* fsb frequency */
1888 data = 3;
1889 break;
7b914098
JS		 1890 /*
1891 * MSR_EBC_FREQUENCY_ID
1892 * Conservative value valid for even the basic CPU models.
1893 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1894 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1895 * and 266MHz for model 3, or 4. Set Core Clock
1896 * Frequency to System Bus Frequency Ratio to 1 (bits
1897 * 31:24) even though these are only valid for CPU
1898 * models > 2, however guests may end up dividing or
1899 * multiplying by zero otherwise.
1900 */
1901 case MSR_EBC_FREQUENCY_ID:
1902 data = 1 << 24;
1903 break;
15c4a640
CO		 1904 case MSR_IA32_APICBASE:
1905 data = kvm_get_apic_base(vcpu);
1906 break;
0105d1a5
GN		 1907 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1908 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1909 break;
a3e06bbe
LJ		 1910 case MSR_IA32_TSCDEADLINE:
1911 data = kvm_get_lapic_tscdeadline_msr(vcpu);
1912 break;
15c4a640 1913 case MSR_IA32_MISC_ENABLE:
ad312c7c 1914 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1915 break;
847f0ad8
AG		 1916 case MSR_IA32_PERF_STATUS:
1917 /* TSC increment by tick */
1918 data = 1000ULL;
1919 /* CPU multiplier */
1920 data |= (((uint64_t)4ULL) << 40);
1921 break;
15c4a640 1922 case MSR_EFER:
f6801dff 1923 data = vcpu->arch.efer;
15c4a640 1924 break;
18068523 1925 case MSR_KVM_WALL_CLOCK:
11c6bffa 1926 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1927 data = vcpu->kvm->arch.wall_clock;
1928 break;
1929 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1930 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1931 data = vcpu->arch.time;
1932 break;
344d9588
GN		 1933 case MSR_KVM_ASYNC_PF_EN:
1934 data = vcpu->arch.apf.msr_val;
1935 break;
c9aaa895
GC		 1936 case MSR_KVM_STEAL_TIME:
1937 data = vcpu->arch.st.msr_val;
1938 break;
890ca9ae
HY		 1939 case MSR_IA32_P5_MC_ADDR:
1940 case MSR_IA32_P5_MC_TYPE:
1941 case MSR_IA32_MCG_CAP:
1942 case MSR_IA32_MCG_CTL:
1943 case MSR_IA32_MCG_STATUS:
1944 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1945 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1946 case MSR_K7_CLK_CTL:
1947 /*
1948 * Provide expected ramp-up count for K7. All other
1949 * are set to zero, indicating minimum divisors for
1950 * every field.
1951 *
1952 * This prevents guest kernels on AMD host with CPU
1953 * type 6, model 8 and higher from exploding due to
1954 * the rdmsr failing.
1955 */
1956 data = 0x20000000;
1957 break;
55cd8e5a
GN		 1958 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1959 if (kvm_hv_msr_partition_wide(msr)) {
1960 int r;
1961 mutex_lock(&vcpu->kvm->lock);
1962 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1963 mutex_unlock(&vcpu->kvm->lock);
1964 return r;
1965 } else
1966 return get_msr_hyperv(vcpu, msr, pdata);
1967 break;
91c9c3ed 1968 case MSR_IA32_BBL_CR_CTL3:
1969 /* This legacy MSR exists but isn't fully documented in current
1970 * silicon. It is however accessed by winxp in very narrow
1971 * scenarios where it sets bit #19, itself documented as
1972 * a "reserved" bit. Best effort attempt to source coherent
1973 * read data here should the balance of the register be
1974 * interpreted by the guest:
1975 *
1976 * L2 cache control register 3: 64GB range, 256KB size,
1977 * enabled, latency 0x1, configured
1978 */
1979 data = 0xbe702111;
1980 break;
15c4a640 1981 default:
ed85c068
AP		 1982 if (!ignore_msrs) {
1983 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1984 return 1;
1985 } else {
1986 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1987 data = 0;
1988 }
1989 break;
15c4a640
CO		 1990 }
1991 *pdata = data;
1992 return 0;
1993}
1994EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1995
313a3dc7
CO		 1996/*
1997 * Read or write a bunch of msrs. All parameters are kernel addresses.
1998 *
1999 * @return number of msrs set successfully.
2000 */
2001static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2002 struct kvm_msr_entry *entries,
2003 int (*do_msr)(struct kvm_vcpu *vcpu,
2004 unsigned index, u64 *data))
2005{
f656ce01 2006 int i, idx;
313a3dc7 2007
f656ce01 2008 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2009 for (i = 0; i < msrs->nmsrs; ++i)
2010 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2011 break;
f656ce01 2012 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2013
313a3dc7
CO		 2014 return i;
2015}
2016
2017/*
2018 * Read or write a bunch of msrs. Parameters are user addresses.
2019 *
2020 * @return number of msrs set successfully.
2021 */
2022static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2023 int (*do_msr)(struct kvm_vcpu *vcpu,
2024 unsigned index, u64 *data),
2025 int writeback)
2026{
2027 struct kvm_msrs msrs;
2028 struct kvm_msr_entry *entries;
2029 int r, n;
2030 unsigned size;
2031
2032 r = -EFAULT;
2033 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2034 goto out;
2035
2036 r = -E2BIG;
2037 if (msrs.nmsrs >= MAX_IO_MSRS)
2038 goto out;
2039
2040 r = -ENOMEM;
2041 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 2042 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 2043 if (!entries)
2044 goto out;
2045
2046 r = -EFAULT;
2047 if (copy_from_user(entries, user_msrs->entries, size))
2048 goto out_free;
2049
2050 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2051 if (r < 0)
2052 goto out_free;
2053
2054 r = -EFAULT;
2055 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2056 goto out_free;
2057
2058 r = n;
2059
2060out_free:
7a73c028 2061 kfree(entries);
313a3dc7
CO		 2062out:
2063 return r;
2064}
2065
018d00d2
ZX		 2066int kvm_dev_ioctl_check_extension(long ext)
2067{
2068 int r;
2069
2070 switch (ext) {
2071 case KVM_CAP_IRQCHIP:
2072 case KVM_CAP_HLT:
2073 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2074 case KVM_CAP_SET_TSS_ADDR:
07716717 2075 case KVM_CAP_EXT_CPUID:
c8076604 2076 case KVM_CAP_CLOCKSOURCE:
7837699f 2077 case KVM_CAP_PIT:
a28e4f5a 2078 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2079 case KVM_CAP_MP_STATE:
ed848624 2080 case KVM_CAP_SYNC_MMU:
a355c85c 2081 case KVM_CAP_USER_NMI:
52d939a0 2082 case KVM_CAP_REINJECT_CONTROL:
4925663a 2083 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 2084 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 2085 case KVM_CAP_IRQFD:
d34e6b17 2086 case KVM_CAP_IOEVENTFD:
c5ff41ce 2087 case KVM_CAP_PIT2:
e9f42757 2088 case KVM_CAP_PIT_STATE2:
b927a3ce 2089 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2090 case KVM_CAP_XEN_HVM:
afbcf7ab 2091 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2092 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2093 case KVM_CAP_HYPERV:
10388a07 2094 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2095 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2096 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2097 case KVM_CAP_DEBUGREGS:
d2be1651 2098 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2099 case KVM_CAP_XSAVE:
344d9588 2100 case KVM_CAP_ASYNC_PF:
92a1f12d 2101 case KVM_CAP_GET_TSC_KHZ:
018d00d2
ZX		 2102 r = 1;
2103 break;
542472b5
LV		 2104 case KVM_CAP_COALESCED_MMIO:
2105 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2106 break;
774ead3a
AK		 2107 case KVM_CAP_VAPIC:
2108 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2109 break;
f725230a 2110 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2111 r = KVM_SOFT_MAX_VCPUS;
2112 break;
2113 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2114 r = KVM_MAX_VCPUS;
2115 break;
a988b910
AK		 2116 case KVM_CAP_NR_MEMSLOTS:
2117 r = KVM_MEMORY_SLOTS;
2118 break;
a68a6a72
MT		 2119 case KVM_CAP_PV_MMU: /* obsolete */
2120 r = 0;
2f333bcb 2121 break;
62c476c7 2122 case KVM_CAP_IOMMU:
a1b60c1c 2123 r = iommu_present(&pci_bus_type);
62c476c7 2124 break;
890ca9ae
HY		 2125 case KVM_CAP_MCE:
2126 r = KVM_MAX_MCE_BANKS;
2127 break;
2d5b5a66
SY		 2128 case KVM_CAP_XCRS:
2129 r = cpu_has_xsave;
2130 break;
92a1f12d
JR		 2131 case KVM_CAP_TSC_CONTROL:
2132 r = kvm_has_tsc_control;
2133 break;
4d25a066
JK		 2134 case KVM_CAP_TSC_DEADLINE_TIMER:
2135 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2136 break;
018d00d2
ZX		 2137 default:
2138 r = 0;
2139 break;
2140 }
2141 return r;
2142
2143}
2144
043405e1
CO		 2145long kvm_arch_dev_ioctl(struct file *filp,
2146 unsigned int ioctl, unsigned long arg)
2147{
2148 void __user *argp = (void __user *)arg;
2149 long r;
2150
2151 switch (ioctl) {
2152 case KVM_GET_MSR_INDEX_LIST: {
2153 struct kvm_msr_list __user *user_msr_list = argp;
2154 struct kvm_msr_list msr_list;
2155 unsigned n;
2156
2157 r = -EFAULT;
2158 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2159 goto out;
2160 n = msr_list.nmsrs;
2161 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2162 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2163 goto out;
2164 r = -E2BIG;
e125e7b6 2165 if (n < msr_list.nmsrs)
043405e1
CO		 2166 goto out;
2167 r = -EFAULT;
2168 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2169 num_msrs_to_save * sizeof(u32)))
2170 goto out;
e125e7b6 2171 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2172 &emulated_msrs,
2173 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2174 goto out;
2175 r = 0;
2176 break;
2177 }
674eea0f
AK		 2178 case KVM_GET_SUPPORTED_CPUID: {
2179 struct kvm_cpuid2 __user *cpuid_arg = argp;
2180 struct kvm_cpuid2 cpuid;
2181
2182 r = -EFAULT;
2183 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2184 goto out;
2185 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2186 cpuid_arg->entries);
674eea0f
AK		 2187 if (r)
2188 goto out;
2189
2190 r = -EFAULT;
2191 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2192 goto out;
2193 r = 0;
2194 break;
2195 }
890ca9ae
HY		 2196 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2197 u64 mce_cap;
2198
2199 mce_cap = KVM_MCE_CAP_SUPPORTED;
2200 r = -EFAULT;
2201 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2202 goto out;
2203 r = 0;
2204 break;
2205 }
043405e1
CO		 2206 default:
2207 r = -EINVAL;
2208 }
2209out:
2210 return r;
2211}
2212
f5f48ee1
SY		 2213static void wbinvd_ipi(void *garbage)
2214{
2215 wbinvd();
2216}
2217
2218static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2219{
2220 return vcpu->kvm->arch.iommu_domain &&
2221 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2222}
2223
313a3dc7
CO		 2224void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2225{
f5f48ee1
SY		 2226 /* Address WBINVD may be executed by guest */
2227 if (need_emulate_wbinvd(vcpu)) {
2228 if (kvm_x86_ops->has_wbinvd_exit())
2229 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2230 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2231 smp_call_function_single(vcpu->cpu,
2232 wbinvd_ipi, NULL, 1);
2233 }
2234
313a3dc7 2235 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2236 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa 2237 /* Make sure TSC doesn't go backwards */
8f6055cb
JR		 2238 s64 tsc_delta;
2239 u64 tsc;
2240
d5c1785d 2241 tsc = kvm_x86_ops->read_l1_tsc(vcpu);
8f6055cb
JR		 2242 tsc_delta = !vcpu->arch.last_guest_tsc ? 0 :
2243 tsc - vcpu->arch.last_guest_tsc;
2244
e48672fa
ZA		 2245 if (tsc_delta < 0)
2246 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2247 if (check_tsc_unstable()) {
e48672fa 2248 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
c285545f 2249 vcpu->arch.tsc_catchup = 1;
c285545f 2250 }
1aa8ceef 2251 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2252 if (vcpu->cpu != cpu)
2253 kvm_migrate_timers(vcpu);
e48672fa 2254 vcpu->cpu = cpu;
6b7d7e76 2255 }
c9aaa895
GC		 2256
2257 accumulate_steal_time(vcpu);
2258 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2259}
2260
2261void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2262{
02daab21 2263 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2264 kvm_put_guest_fpu(vcpu);
d5c1785d 2265 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
313a3dc7
CO		 2266}
2267
07716717 2268static int is_efer_nx(void)
313a3dc7 2269{
e286e86e 2270 unsigned long long efer = 0;
313a3dc7 2271
e286e86e 2272 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 2273 return efer & EFER_NX;
2274}
2275
2276static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2277{
2278 int i;
2279 struct kvm_cpuid_entry2 *e, *entry;
2280
313a3dc7 2281 entry = NULL;
ad312c7c
ZX		 2282 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2283 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 2284 if (e->function == 0x80000001) {
2285 entry = e;
2286 break;
2287 }
2288 }
07716717 2289 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 2290 entry->edx &= ~(1 << 20);
2291 printk(KERN_INFO "kvm: guest NX capability removed\n");
2292 }
2293}
2294
07716717 2295/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 2296static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2297 struct kvm_cpuid *cpuid,
2298 struct kvm_cpuid_entry __user *entries)
07716717
DK		 2299{
2300 int r, i;
2301 struct kvm_cpuid_entry *cpuid_entries;
2302
2303 r = -E2BIG;
2304 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2305 goto out;
2306 r = -ENOMEM;
2307 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2308 if (!cpuid_entries)
2309 goto out;
2310 r = -EFAULT;
2311 if (copy_from_user(cpuid_entries, entries,
2312 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2313 goto out_free;
2314 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 2315 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2316 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2317 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2318 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2319 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2320 vcpu->arch.cpuid_entries[i].index = 0;
2321 vcpu->arch.cpuid_entries[i].flags = 0;
2322 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2323 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2324 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2325 }
2326 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2327 cpuid_fix_nx_cap(vcpu);
2328 r = 0;
fc61b800 2329 kvm_apic_set_version(vcpu);
0e851880 2330 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2331 update_cpuid(vcpu);
07716717
DK		 2332
2333out_free:
2334 vfree(cpuid_entries);
2335out:
2336 return r;
2337}
2338
2339static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2340 struct kvm_cpuid2 *cpuid,
2341 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2342{
2343 int r;
2344
2345 r = -E2BIG;
2346 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2347 goto out;
2348 r = -EFAULT;
ad312c7c 2349 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2350 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2351 goto out;
ad312c7c 2352 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2353 kvm_apic_set_version(vcpu);
0e851880 2354 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2355 update_cpuid(vcpu);
313a3dc7
CO		 2356 return 0;
2357
2358out:
2359 return r;
2360}
2361
07716717 2362static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2363 struct kvm_cpuid2 *cpuid,
2364 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2365{
2366 int r;
2367
2368 r = -E2BIG;
ad312c7c 2369 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2370 goto out;
2371 r = -EFAULT;
ad312c7c 2372 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2373 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2374 goto out;
2375 return 0;
2376
2377out:
ad312c7c 2378 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2379 return r;
2380}
2381
945ee35e
AK		 2382static void cpuid_mask(u32 *word, int wordnum)
2383{
2384 *word &= boot_cpu_data.x86_capability[wordnum];
2385}
2386
07716717 2387static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2388 u32 index)
07716717
DK		 2389{
2390 entry->function = function;
2391 entry->index = index;
2392 cpuid_count(entry->function, entry->index,
19355475 2393 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2394 entry->flags = 0;
2395}
2396
24c82e57
AK		 2397static bool supported_xcr0_bit(unsigned bit)
2398{
2399 u64 mask = ((u64)1 << bit);
2400
2401 return mask & (XSTATE_FP | XSTATE_SSE | XSTATE_YMM) & host_xcr0;
2402}
2403
7faa4ee1
AK		 2404#define F(x) bit(X86_FEATURE_##x)
2405
07716717
DK		 2406static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2407 u32 index, int *nent, int maxnent)
2408{
7faa4ee1 2409 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2410#ifdef CONFIG_X86_64
17cc3935
SY		 2411 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2412 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2413 unsigned f_lm = F(LM);
2414#else
17cc3935 2415 unsigned f_gbpages = 0;
7faa4ee1 2416 unsigned f_lm = 0;
07716717 2417#endif
4e47c7a6 2418 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2419
2420 /* cpuid 1.edx */
2421 const u32 kvm_supported_word0_x86_features =
2422 F(FPU) | F(VME) | F(DE) | F(PSE) |
2423 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2424 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2425 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2426 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2427 0 /* Reserved, DS, ACPI */ | F(MMX) |
2428 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2429 0 /* HTT, TM, Reserved, PBE */;
2430 /* cpuid 0x80000001.edx */
2431 const u32 kvm_supported_word1_x86_features =
2432 F(FPU) | F(VME) | F(DE) | F(PSE) |
2433 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2434 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2435 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2436 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2437 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2438 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2439 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2440 /* cpuid 1.ecx */
2441 const u32 kvm_supported_word4_x86_features =
6c3f6041 2442 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2443 0 /* DS-CPL, VMX, SMX, EST */ |
2444 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2445 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2446 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2447 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6d886fd0 2448 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
4a00efdf 2449 F(F16C) | F(RDRAND);
7faa4ee1 2450 /* cpuid 0x80000001.ecx */
07716717 2451 const u32 kvm_supported_word6_x86_features =
4c62a2dc 2452 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
7faa4ee1 2453 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
7ef8aa72 2454 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) |
6d886fd0 2455 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM);
07716717 2456
4429d5dc
B		 2457 /* cpuid 0xC0000001.edx */
2458 const u32 kvm_supported_word5_x86_features =
2459 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |
2460 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
2461 F(PMM) | F(PMM_EN);
2462
611c120f
YW		 2463 /* cpuid 7.0.ebx */
2464 const u32 kvm_supported_word9_x86_features =
a01c8f9b 2465 F(SMEP) | F(FSGSBASE) | F(ERMS);
611c120f 2466
19355475 2467 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2468 get_cpu();
2469 do_cpuid_1_ent(entry, function, index);
2470 ++*nent;
2471
2472 switch (function) {
2473 case 0:
2acf923e 2474 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2475 break;
2476 case 1:
2477 entry->edx &= kvm_supported_word0_x86_features;
945ee35e 2478 cpuid_mask(&entry->edx, 0);
7faa4ee1 2479 entry->ecx &= kvm_supported_word4_x86_features;
945ee35e 2480 cpuid_mask(&entry->ecx, 4);
0d1de2d9
GN		 2481 /* we support x2apic emulation even if host does not support
2482 * it since we emulate x2apic in software */
2483 entry->ecx |= F(X2APIC);
07716717
DK		 2484 break;
2485 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2486 * may return different values. This forces us to get_cpu() before
2487 * issuing the first command, and also to emulate this annoying behavior
2488 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2489 case 2: {
2490 int t, times = entry->eax & 0xff;
2491
2492 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2493 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2494 for (t = 1; t < times && *nent < maxnent; ++t) {
2495 do_cpuid_1_ent(&entry[t], function, 0);
2496 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2497 ++*nent;
2498 }
2499 break;
2500 }
611c120f 2501 /* function 4 has additional index. */
07716717 2502 case 4: {
14af3f3c 2503 int i, cache_type;
07716717
DK		 2504
2505 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2506 /* read more entries until cache_type is zero */
14af3f3c
HH		 2507 for (i = 1; *nent < maxnent; ++i) {
2508 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2509 if (!cache_type)
2510 break;
14af3f3c
HH		 2511 do_cpuid_1_ent(&entry[i], function, i);
2512 entry[i].flags |=
07716717
DK		 2513 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2514 ++*nent;
2515 }
2516 break;
2517 }
611c120f
YW		 2518 case 7: {
2519 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2520 /* Mask ebx against host capbability word 9 */
2521 if (index == 0) {
2522 entry->ebx &= kvm_supported_word9_x86_features;
2523 cpuid_mask(&entry->ebx, 9);
2524 } else
2525 entry->ebx = 0;
2526 entry->eax = 0;
2527 entry->ecx = 0;
2528 entry->edx = 0;
2529 break;
2530 }
24c82e57
AK		 2531 case 9:
2532 break;
611c120f 2533 /* function 0xb has additional index. */
07716717 2534 case 0xb: {
14af3f3c 2535 int i, level_type;
07716717
DK		 2536
2537 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2538 /* read more entries until level_type is zero */
14af3f3c 2539 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2540 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2541 if (!level_type)
2542 break;
14af3f3c
HH		 2543 do_cpuid_1_ent(&entry[i], function, i);
2544 entry[i].flags |=
07716717
DK		 2545 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2546 ++*nent;
2547 }
2548 break;
2549 }
2acf923e 2550 case 0xd: {
02668b06 2551 int idx, i;
2acf923e
DC		 2552
2553 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
02668b06
AP		 2554 for (idx = 1, i = 1; *nent < maxnent && idx < 64; ++idx) {
2555 do_cpuid_1_ent(&entry[i], function, idx);
2556 if (entry[i].eax == 0 || !supported_xcr0_bit(idx))
20800bc9 2557 continue;
2acf923e
DC		 2558 entry[i].flags |=
2559 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2560 ++*nent;
02668b06 2561 ++i;
2acf923e
DC		 2562 }
2563 break;
2564 }
84478c82
GC		 2565 case KVM_CPUID_SIGNATURE: {
2566 char signature[12] = "KVMKVMKVM\0\0";
2567 u32 *sigptr = (u32 *)signature;
2568 entry->eax = 0;
2569 entry->ebx = sigptr[0];
2570 entry->ecx = sigptr[1];
2571 entry->edx = sigptr[2];
2572 break;
2573 }
2574 case KVM_CPUID_FEATURES:
2575 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2576 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64 2577 (1 << KVM_FEATURE_CLOCKSOURCE2) |
32918924 2578 (1 << KVM_FEATURE_ASYNC_PF) |
371bcf64 2579 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
c9aaa895
GC		 2580
2581 if (sched_info_on())
2582 entry->eax |= (1 << KVM_FEATURE_STEAL_TIME);
2583
84478c82
GC		 2584 entry->ebx = 0;
2585 entry->ecx = 0;
2586 entry->edx = 0;
2587 break;
07716717
DK		 2588 case 0x80000000:
2589 entry->eax = min(entry->eax, 0x8000001a);
2590 break;
2591 case 0x80000001:
2592 entry->edx &= kvm_supported_word1_x86_features;
945ee35e 2593 cpuid_mask(&entry->edx, 1);
07716717 2594 entry->ecx &= kvm_supported_word6_x86_features;
945ee35e 2595 cpuid_mask(&entry->ecx, 6);
07716717 2596 break;
24c82e57
AK		 2597 case 0x80000008: {
2598 unsigned g_phys_as = (entry->eax >> 16) & 0xff;
2599 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U);
2600 unsigned phys_as = entry->eax & 0xff;
2601
2602 if (!g_phys_as)
2603 g_phys_as = phys_as;
2604 entry->eax = g_phys_as | (virt_as << 8);
2605 entry->ebx = entry->edx = 0;
2606 break;
2607 }
2608 case 0x80000019:
2609 entry->ecx = entry->edx = 0;
2610 break;
2611 case 0x8000001a:
2612 break;
2613 case 0x8000001d:
2614 break;
4429d5dc
B		 2615 /*Add support for Centaur's CPUID instruction*/
2616 case 0xC0000000:
2617 /*Just support up to 0xC0000004 now*/
2618 entry->eax = min(entry->eax, 0xC0000004);
2619 break;
2620 case 0xC0000001:
2621 entry->edx &= kvm_supported_word5_x86_features;
2622 cpuid_mask(&entry->edx, 5);
2623 break;
24c82e57
AK		 2624 case 3: /* Processor serial number */
2625 case 5: /* MONITOR/MWAIT */
2626 case 6: /* Thermal management */
2627 case 0xA: /* Architectural Performance Monitoring */
2628 case 0x80000007: /* Advanced power management */
4429d5dc
B		 2629 case 0xC0000002:
2630 case 0xC0000003:
2631 case 0xC0000004:
24c82e57
AK		 2632 default:
2633 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
4429d5dc 2634 break;
07716717 2635 }
d4330ef2
JR		 2636
2637 kvm_x86_ops->set_supported_cpuid(function, entry);
2638
07716717
DK		 2639 put_cpu();
2640}
2641
7faa4ee1
AK		 2642#undef F
2643
674eea0f 2644static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2645 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2646{
2647 struct kvm_cpuid_entry2 *cpuid_entries;
2648 int limit, nent = 0, r = -E2BIG;
2649 u32 func;
2650
2651 if (cpuid->nent < 1)
2652 goto out;
6a544355
AK		 2653 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2654 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2655 r = -ENOMEM;
2656 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2657 if (!cpuid_entries)
2658 goto out;
2659
2660 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2661 limit = cpuid_entries[0].eax;
2662 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2663 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2664 &nent, cpuid->nent);
07716717
DK		 2665 r = -E2BIG;
2666 if (nent >= cpuid->nent)
2667 goto out_free;
2668
2669 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2670 limit = cpuid_entries[nent - 1].eax;
2671 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2672 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2673 &nent, cpuid->nent);
84478c82
GC		 2674
2675
2676
2677 r = -E2BIG;
2678 if (nent >= cpuid->nent)
2679 goto out_free;
2680
4429d5dc
B		 2681 /* Add support for Centaur's CPUID instruction. */
2682 if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR) {
2683 do_cpuid_ent(&cpuid_entries[nent], 0xC0000000, 0,
2684 &nent, cpuid->nent);
2685
2686 r = -E2BIG;
2687 if (nent >= cpuid->nent)
2688 goto out_free;
2689
2690 limit = cpuid_entries[nent - 1].eax;
2691 for (func = 0xC0000001;
2692 func <= limit && nent < cpuid->nent; ++func)
2693 do_cpuid_ent(&cpuid_entries[nent], func, 0,
2694 &nent, cpuid->nent);
2695
2696 r = -E2BIG;
2697 if (nent >= cpuid->nent)
2698 goto out_free;
2699 }
2700
84478c82
GC		 2701 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2702 cpuid->nent);
2703
2704 r = -E2BIG;
2705 if (nent >= cpuid->nent)
2706 goto out_free;
2707
2708 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2709 cpuid->nent);
2710
cb007648
MM		 2711 r = -E2BIG;
2712 if (nent >= cpuid->nent)
2713 goto out_free;
2714
07716717
DK		 2715 r = -EFAULT;
2716 if (copy_to_user(entries, cpuid_entries,
19355475 2717 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2718 goto out_free;
2719 cpuid->nent = nent;
2720 r = 0;
2721
2722out_free:
2723 vfree(cpuid_entries);
2724out:
2725 return r;
2726}
2727
313a3dc7
CO		 2728static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2729 struct kvm_lapic_state *s)
2730{
ad312c7c 2731 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2732
2733 return 0;
2734}
2735
2736static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2737 struct kvm_lapic_state *s)
2738{
ad312c7c 2739 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2740 kvm_apic_post_state_restore(vcpu);
cb142eb7 2741 update_cr8_intercept(vcpu);
313a3dc7
CO		 2742
2743 return 0;
2744}
2745
f77bc6a4
ZX		 2746static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2747 struct kvm_interrupt *irq)
2748{
2749 if (irq->irq < 0 || irq->irq >= 256)
2750 return -EINVAL;
2751 if (irqchip_in_kernel(vcpu->kvm))
2752 return -ENXIO;
f77bc6a4 2753
66fd3f7f 2754 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2755 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2756
f77bc6a4
ZX		 2757 return 0;
2758}
2759
c4abb7c9
JK		 2760static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2761{
c4abb7c9 2762 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2763
2764 return 0;
2765}
2766
b209749f
AK		 2767static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2768 struct kvm_tpr_access_ctl *tac)
2769{
2770 if (tac->flags)
2771 return -EINVAL;
2772 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2773 return 0;
2774}
2775
890ca9ae
HY		 2776static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2777 u64 mcg_cap)
2778{
2779 int r;
2780 unsigned bank_num = mcg_cap & 0xff, bank;
2781
2782 r = -EINVAL;
a9e38c3e 2783 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2784 goto out;
2785 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2786 goto out;
2787 r = 0;
2788 vcpu->arch.mcg_cap = mcg_cap;
2789 /* Init IA32_MCG_CTL to all 1s */
2790 if (mcg_cap & MCG_CTL_P)
2791 vcpu->arch.mcg_ctl = ~(u64)0;
2792 /* Init IA32_MCi_CTL to all 1s */
2793 for (bank = 0; bank < bank_num; bank++)
2794 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2795out:
2796 return r;
2797}
2798
2799static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2800 struct kvm_x86_mce *mce)
2801{
2802 u64 mcg_cap = vcpu->arch.mcg_cap;
2803 unsigned bank_num = mcg_cap & 0xff;
2804 u64 *banks = vcpu->arch.mce_banks;
2805
2806 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2807 return -EINVAL;
2808 /*
2809 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2810 * reporting is disabled
2811 */
2812 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2813 vcpu->arch.mcg_ctl != ~(u64)0)
2814 return 0;
2815 banks += 4 * mce->bank;
2816 /*
2817 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2818 * reporting is disabled for the bank
2819 */
2820 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2821 return 0;
2822 if (mce->status & MCI_STATUS_UC) {
2823 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2824 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2825 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2826 return 0;
2827 }
2828 if (banks[1] & MCI_STATUS_VAL)
2829 mce->status |= MCI_STATUS_OVER;
2830 banks[2] = mce->addr;
2831 banks[3] = mce->misc;
2832 vcpu->arch.mcg_status = mce->mcg_status;
2833 banks[1] = mce->status;
2834 kvm_queue_exception(vcpu, MC_VECTOR);
2835 } else if (!(banks[1] & MCI_STATUS_VAL)
2836 || !(banks[1] & MCI_STATUS_UC)) {
2837 if (banks[1] & MCI_STATUS_VAL)
2838 mce->status |= MCI_STATUS_OVER;
2839 banks[2] = mce->addr;
2840 banks[3] = mce->misc;
2841 banks[1] = mce->status;
2842 } else
2843 banks[1] |= MCI_STATUS_OVER;
2844 return 0;
2845}
2846
3cfc3092
JK		 2847static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2848 struct kvm_vcpu_events *events)
2849{
7460fb4a 2850 process_nmi(vcpu);
03b82a30
JK		 2851 events->exception.injected =
2852 vcpu->arch.exception.pending &&
2853 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2854 events->exception.nr = vcpu->arch.exception.nr;
2855 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2856 events->exception.pad = 0;
3cfc3092
JK		 2857 events->exception.error_code = vcpu->arch.exception.error_code;
2858
03b82a30
JK		 2859 events->interrupt.injected =
2860 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2861 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2862 events->interrupt.soft = 0;
48005f64
JK		 2863 events->interrupt.shadow =
2864 kvm_x86_ops->get_interrupt_shadow(vcpu,
2865 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2866
2867 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2868 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2869 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2870 events->nmi.pad = 0;
3cfc3092
JK		 2871
2872 events->sipi_vector = vcpu->arch.sipi_vector;
2873
dab4b911 2874 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2875 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2876 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2877 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2878}
2879
2880static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2881 struct kvm_vcpu_events *events)
2882{
dab4b911 2883 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2884 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2885 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2886 return -EINVAL;
2887
7460fb4a 2888 process_nmi(vcpu);
3cfc3092
JK		 2889 vcpu->arch.exception.pending = events->exception.injected;
2890 vcpu->arch.exception.nr = events->exception.nr;
2891 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2892 vcpu->arch.exception.error_code = events->exception.error_code;
2893
2894 vcpu->arch.interrupt.pending = events->interrupt.injected;
2895 vcpu->arch.interrupt.nr = events->interrupt.nr;
2896 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2897 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2898 kvm_x86_ops->set_interrupt_shadow(vcpu,
2899 events->interrupt.shadow);
3cfc3092
JK		 2900
2901 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2902 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2903 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2904 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2905
dab4b911
JK		 2906 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2907 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2908
3842d135
AK		 2909 kvm_make_request(KVM_REQ_EVENT, vcpu);
2910
3cfc3092
JK		 2911 return 0;
2912}
2913
a1efbe77
JK		 2914static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2915 struct kvm_debugregs *dbgregs)
2916{
a1efbe77
JK		 2917 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2918 dbgregs->dr6 = vcpu->arch.dr6;
2919 dbgregs->dr7 = vcpu->arch.dr7;
2920 dbgregs->flags = 0;
97e69aa6 2921 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2922}
2923
2924static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2925 struct kvm_debugregs *dbgregs)
2926{
2927 if (dbgregs->flags)
2928 return -EINVAL;
2929
a1efbe77
JK		 2930 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2931 vcpu->arch.dr6 = dbgregs->dr6;
2932 vcpu->arch.dr7 = dbgregs->dr7;
2933
a1efbe77
JK		 2934 return 0;
2935}
2936
2d5b5a66
SY		 2937static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2938 struct kvm_xsave *guest_xsave)
2939{
2940 if (cpu_has_xsave)
2941 memcpy(guest_xsave->region,
2942 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2943 xstate_size);
2d5b5a66
SY		 2944 else {
2945 memcpy(guest_xsave->region,
2946 &vcpu->arch.guest_fpu.state->fxsave,
2947 sizeof(struct i387_fxsave_struct));
2948 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2949 XSTATE_FPSSE;
2950 }
2951}
2952
2953static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2954 struct kvm_xsave *guest_xsave)
2955{
2956 u64 xstate_bv =
2957 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2958
2959 if (cpu_has_xsave)
2960 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2961 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2962 else {
2963 if (xstate_bv & ~XSTATE_FPSSE)
2964 return -EINVAL;
2965 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2966 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2967 }
2968 return 0;
2969}
2970
2971static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2972 struct kvm_xcrs *guest_xcrs)
2973{
2974 if (!cpu_has_xsave) {
2975 guest_xcrs->nr_xcrs = 0;
2976 return;
2977 }
2978
2979 guest_xcrs->nr_xcrs = 1;
2980 guest_xcrs->flags = 0;
2981 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2982 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2983}
2984
2985static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2986 struct kvm_xcrs *guest_xcrs)
2987{
2988 int i, r = 0;
2989
2990 if (!cpu_has_xsave)
2991 return -EINVAL;
2992
2993 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2994 return -EINVAL;
2995
2996 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2997 /* Only support XCR0 currently */
2998 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2999 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3000 guest_xcrs->xcrs[0].value);
3001 break;
3002 }
3003 if (r)
3004 r = -EINVAL;
3005 return r;
3006}
3007
313a3dc7
CO		 3008long kvm_arch_vcpu_ioctl(struct file *filp,
3009 unsigned int ioctl, unsigned long arg)
3010{
3011 struct kvm_vcpu *vcpu = filp->private_data;
3012 void __user *argp = (void __user *)arg;
3013 int r;
d1ac91d8
AK		 3014 union {
3015 struct kvm_lapic_state *lapic;
3016 struct kvm_xsave *xsave;
3017 struct kvm_xcrs *xcrs;
3018 void *buffer;
3019 } u;
3020
3021 u.buffer = NULL;
313a3dc7
CO		 3022 switch (ioctl) {
3023 case KVM_GET_LAPIC: {
2204ae3c
MT		 3024 r = -EINVAL;
3025 if (!vcpu->arch.apic)
3026 goto out;
d1ac91d8 3027 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3028
b772ff36 3029 r = -ENOMEM;
d1ac91d8 3030 if (!u.lapic)
b772ff36 3031 goto out;
d1ac91d8 3032 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3033 if (r)
3034 goto out;
3035 r = -EFAULT;
d1ac91d8 3036 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3037 goto out;
3038 r = 0;
3039 break;
3040 }
3041 case KVM_SET_LAPIC: {
2204ae3c
MT		 3042 r = -EINVAL;
3043 if (!vcpu->arch.apic)
3044 goto out;
d1ac91d8 3045 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 3046 r = -ENOMEM;
d1ac91d8 3047 if (!u.lapic)
b772ff36 3048 goto out;
313a3dc7 3049 r = -EFAULT;
d1ac91d8 3050 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 3051 goto out;
d1ac91d8 3052 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3053 if (r)
3054 goto out;
3055 r = 0;
3056 break;
3057 }
f77bc6a4
ZX		 3058 case KVM_INTERRUPT: {
3059 struct kvm_interrupt irq;
3060
3061 r = -EFAULT;
3062 if (copy_from_user(&irq, argp, sizeof irq))
3063 goto out;
3064 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3065 if (r)
3066 goto out;
3067 r = 0;
3068 break;
3069 }
c4abb7c9
JK		 3070 case KVM_NMI: {
3071 r = kvm_vcpu_ioctl_nmi(vcpu);
3072 if (r)
3073 goto out;
3074 r = 0;
3075 break;
3076 }
313a3dc7
CO		 3077 case KVM_SET_CPUID: {
3078 struct kvm_cpuid __user *cpuid_arg = argp;
3079 struct kvm_cpuid cpuid;
3080
3081 r = -EFAULT;
3082 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3083 goto out;
3084 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3085 if (r)
3086 goto out;
3087 break;
3088 }
07716717
DK		 3089 case KVM_SET_CPUID2: {
3090 struct kvm_cpuid2 __user *cpuid_arg = argp;
3091 struct kvm_cpuid2 cpuid;
3092
3093 r = -EFAULT;
3094 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3095 goto out;
3096 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3097 cpuid_arg->entries);
07716717
DK		 3098 if (r)
3099 goto out;
3100 break;
3101 }
3102 case KVM_GET_CPUID2: {
3103 struct kvm_cpuid2 __user *cpuid_arg = argp;
3104 struct kvm_cpuid2 cpuid;
3105
3106 r = -EFAULT;
3107 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3108 goto out;
3109 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3110 cpuid_arg->entries);
07716717
DK		 3111 if (r)
3112 goto out;
3113 r = -EFAULT;
3114 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3115 goto out;
3116 r = 0;
3117 break;
3118 }
313a3dc7
CO		 3119 case KVM_GET_MSRS:
3120 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3121 break;
3122 case KVM_SET_MSRS:
3123 r = msr_io(vcpu, argp, do_set_msr, 0);
3124 break;
b209749f
AK		 3125 case KVM_TPR_ACCESS_REPORTING: {
3126 struct kvm_tpr_access_ctl tac;
3127
3128 r = -EFAULT;
3129 if (copy_from_user(&tac, argp, sizeof tac))
3130 goto out;
3131 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3132 if (r)
3133 goto out;
3134 r = -EFAULT;
3135 if (copy_to_user(argp, &tac, sizeof tac))
3136 goto out;
3137 r = 0;
3138 break;
3139 };
b93463aa
AK		 3140 case KVM_SET_VAPIC_ADDR: {
3141 struct kvm_vapic_addr va;
3142
3143 r = -EINVAL;
3144 if (!irqchip_in_kernel(vcpu->kvm))
3145 goto out;
3146 r = -EFAULT;
3147 if (copy_from_user(&va, argp, sizeof va))
3148 goto out;
3149 r = 0;
3150 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3151 break;
3152 }
890ca9ae
HY		 3153 case KVM_X86_SETUP_MCE: {
3154 u64 mcg_cap;
3155
3156 r = -EFAULT;
3157 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3158 goto out;
3159 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3160 break;
3161 }
3162 case KVM_X86_SET_MCE: {
3163 struct kvm_x86_mce mce;
3164
3165 r = -EFAULT;
3166 if (copy_from_user(&mce, argp, sizeof mce))
3167 goto out;
3168 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3169 break;
3170 }
3cfc3092
JK		 3171 case KVM_GET_VCPU_EVENTS: {
3172 struct kvm_vcpu_events events;
3173
3174 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3175
3176 r = -EFAULT;
3177 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3178 break;
3179 r = 0;
3180 break;
3181 }
3182 case KVM_SET_VCPU_EVENTS: {
3183 struct kvm_vcpu_events events;
3184
3185 r = -EFAULT;
3186 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3187 break;
3188
3189 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3190 break;
3191 }
a1efbe77
JK		 3192 case KVM_GET_DEBUGREGS: {
3193 struct kvm_debugregs dbgregs;
3194
3195 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3196
3197 r = -EFAULT;
3198 if (copy_to_user(argp, &dbgregs,
3199 sizeof(struct kvm_debugregs)))
3200 break;
3201 r = 0;
3202 break;
3203 }
3204 case KVM_SET_DEBUGREGS: {
3205 struct kvm_debugregs dbgregs;
3206
3207 r = -EFAULT;
3208 if (copy_from_user(&dbgregs, argp,
3209 sizeof(struct kvm_debugregs)))
3210 break;
3211
3212 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3213 break;
3214 }
2d5b5a66 3215 case KVM_GET_XSAVE: {
d1ac91d8 3216 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3217 r = -ENOMEM;
d1ac91d8 3218 if (!u.xsave)
2d5b5a66
SY		 3219 break;
3220
d1ac91d8 3221 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3222
3223 r = -EFAULT;
d1ac91d8 3224 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3225 break;
3226 r = 0;
3227 break;
3228 }
3229 case KVM_SET_XSAVE: {
d1ac91d8 3230 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3231 r = -ENOMEM;
d1ac91d8 3232 if (!u.xsave)
2d5b5a66
SY		 3233 break;
3234
3235 r = -EFAULT;
d1ac91d8 3236 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3237 break;
3238
d1ac91d8 3239 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3240 break;
3241 }
3242 case KVM_GET_XCRS: {
d1ac91d8 3243 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3244 r = -ENOMEM;
d1ac91d8 3245 if (!u.xcrs)
2d5b5a66
SY		 3246 break;
3247
d1ac91d8 3248 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3249
3250 r = -EFAULT;
d1ac91d8 3251 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3252 sizeof(struct kvm_xcrs)))
3253 break;
3254 r = 0;
3255 break;
3256 }
3257 case KVM_SET_XCRS: {
d1ac91d8 3258 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3259 r = -ENOMEM;
d1ac91d8 3260 if (!u.xcrs)
2d5b5a66
SY		 3261 break;
3262
3263 r = -EFAULT;
d1ac91d8 3264 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 3265 sizeof(struct kvm_xcrs)))
3266 break;
3267
d1ac91d8 3268 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3269 break;
3270 }
92a1f12d
JR		 3271 case KVM_SET_TSC_KHZ: {
3272 u32 user_tsc_khz;
3273
3274 r = -EINVAL;
3275 if (!kvm_has_tsc_control)
3276 break;
3277
3278 user_tsc_khz = (u32)arg;
3279
3280 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3281 goto out;
3282
3283 kvm_x86_ops->set_tsc_khz(vcpu, user_tsc_khz);
3284
3285 r = 0;
3286 goto out;
3287 }
3288 case KVM_GET_TSC_KHZ: {
3289 r = -EIO;
3290 if (check_tsc_unstable())
3291 goto out;
3292
3293 r = vcpu_tsc_khz(vcpu);
3294
3295 goto out;
3296 }
313a3dc7
CO		 3297 default:
3298 r = -EINVAL;
3299 }
3300out:
d1ac91d8 3301 kfree(u.buffer);
313a3dc7
CO		 3302 return r;
3303}
3304
1fe779f8
CO		 3305static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3306{
3307 int ret;
3308
3309 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3310 return -1;
3311 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3312 return ret;
3313}
3314
b927a3ce
SY		 3315static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3316 u64 ident_addr)
3317{
3318 kvm->arch.ept_identity_map_addr = ident_addr;
3319 return 0;
3320}
3321
1fe779f8
CO		 3322static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3323 u32 kvm_nr_mmu_pages)
3324{
3325 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3326 return -EINVAL;
3327
79fac95e 3328 mutex_lock(&kvm->slots_lock);
7c8a83b7 3329 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 3330
3331 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3332 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3333
7c8a83b7 3334 spin_unlock(&kvm->mmu_lock);
79fac95e 3335 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3336 return 0;
3337}
3338
3339static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3340{
39de71ec 3341 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3342}
3343
1fe779f8
CO		 3344static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3345{
3346 int r;
3347
3348 r = 0;
3349 switch (chip->chip_id) {
3350 case KVM_IRQCHIP_PIC_MASTER:
3351 memcpy(&chip->chip.pic,
3352 &pic_irqchip(kvm)->pics[0],
3353 sizeof(struct kvm_pic_state));
3354 break;
3355 case KVM_IRQCHIP_PIC_SLAVE:
3356 memcpy(&chip->chip.pic,
3357 &pic_irqchip(kvm)->pics[1],
3358 sizeof(struct kvm_pic_state));
3359 break;
3360 case KVM_IRQCHIP_IOAPIC:
eba0226b 3361 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3362 break;
3363 default:
3364 r = -EINVAL;
3365 break;
3366 }
3367 return r;
3368}
3369
3370static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3371{
3372 int r;
3373
3374 r = 0;
3375 switch (chip->chip_id) {
3376 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3377 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3378 memcpy(&pic_irqchip(kvm)->pics[0],
3379 &chip->chip.pic,
3380 sizeof(struct kvm_pic_state));
f4f51050 3381 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3382 break;
3383 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3384 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3385 memcpy(&pic_irqchip(kvm)->pics[1],
3386 &chip->chip.pic,
3387 sizeof(struct kvm_pic_state));
f4f51050 3388 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3389 break;
3390 case KVM_IRQCHIP_IOAPIC:
eba0226b 3391 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3392 break;
3393 default:
3394 r = -EINVAL;
3395 break;
3396 }
3397 kvm_pic_update_irq(pic_irqchip(kvm));
3398 return r;
3399}
3400
e0f63cb9
SY		 3401static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3402{
3403 int r = 0;
3404
894a9c55 3405 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3406 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3407 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3408 return r;
3409}
3410
3411static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3412{
3413 int r = 0;
3414
894a9c55 3415 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3416 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3417 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3418 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3419 return r;
3420}
3421
3422static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3423{
3424 int r = 0;
3425
3426 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3427 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3428 sizeof(ps->channels));
3429 ps->flags = kvm->arch.vpit->pit_state.flags;
3430 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3431 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3432 return r;
3433}
3434
3435static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3436{
3437 int r = 0, start = 0;
3438 u32 prev_legacy, cur_legacy;
3439 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3440 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3441 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3442 if (!prev_legacy && cur_legacy)
3443 start = 1;
3444 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3445 sizeof(kvm->arch.vpit->pit_state.channels));
3446 kvm->arch.vpit->pit_state.flags = ps->flags;
3447 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3448 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3449 return r;
3450}
3451
52d939a0
MT		 3452static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3453 struct kvm_reinject_control *control)
3454{
3455 if (!kvm->arch.vpit)
3456 return -ENXIO;
894a9c55 3457 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3458 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3459 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3460 return 0;
3461}
3462
5bb064dc
ZX		 3463/*
3464 * Get (and clear) the dirty memory log for a memory slot.
3465 */
3466int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3467 struct kvm_dirty_log *log)
3468{
7850ac54 3469 int r;
5bb064dc 3470 struct kvm_memory_slot *memslot;
87bf6e7d 3471 unsigned long n;
5bb064dc 3472
79fac95e 3473 mutex_lock(&kvm->slots_lock);
5bb064dc 3474
b050b015
MT		 3475 r = -EINVAL;
3476 if (log->slot >= KVM_MEMORY_SLOTS)
3477 goto out;
3478
3479 memslot = &kvm->memslots->memslots[log->slot];
3480 r = -ENOENT;
3481 if (!memslot->dirty_bitmap)
3482 goto out;
3483
87bf6e7d 3484 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3485
5bb064dc 3486 /* If nothing is dirty, don't bother messing with page tables. */
7850ac54 3487 if (memslot->nr_dirty_pages) {
b050b015 3488 struct kvm_memslots *slots, *old_slots;
914ebccd 3489 unsigned long *dirty_bitmap;
b050b015 3490
515a0127
TY		 3491 dirty_bitmap = memslot->dirty_bitmap_head;
3492 if (memslot->dirty_bitmap == dirty_bitmap)
3493 dirty_bitmap += n / sizeof(long);
914ebccd 3494 memset(dirty_bitmap, 0, n);
b050b015 3495
914ebccd
TY		 3496 r = -ENOMEM;
3497 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
515a0127 3498 if (!slots)
914ebccd 3499 goto out;
b050b015
MT		 3500 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3501 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
7850ac54 3502 slots->memslots[log->slot].nr_dirty_pages = 0;
49c7754c 3503 slots->generation++;
b050b015
MT		 3504
3505 old_slots = kvm->memslots;
3506 rcu_assign_pointer(kvm->memslots, slots);
3507 synchronize_srcu_expedited(&kvm->srcu);
3508 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3509 kfree(old_slots);
914ebccd 3510
edde99ce
MT		 3511 spin_lock(&kvm->mmu_lock);
3512 kvm_mmu_slot_remove_write_access(kvm, log->slot);
3513 spin_unlock(&kvm->mmu_lock);
3514
914ebccd 3515 r = -EFAULT;
515a0127 3516 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
914ebccd 3517 goto out;
914ebccd
TY		 3518 } else {
3519 r = -EFAULT;
3520 if (clear_user(log->dirty_bitmap, n))
3521 goto out;
5bb064dc 3522 }
b050b015 3523
5bb064dc
ZX		 3524 r = 0;
3525out:
79fac95e 3526 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3527 return r;
3528}
3529
1fe779f8
CO		 3530long kvm_arch_vm_ioctl(struct file *filp,
3531 unsigned int ioctl, unsigned long arg)
3532{
3533 struct kvm *kvm = filp->private_data;
3534 void __user *argp = (void __user *)arg;
367e1319 3535 int r = -ENOTTY;
f0d66275
DH		 3536 /*
3537 * This union makes it completely explicit to gcc-3.x
3538 * that these two variables' stack usage should be
3539 * combined, not added together.
3540 */
3541 union {
3542 struct kvm_pit_state ps;
e9f42757 3543 struct kvm_pit_state2 ps2;
c5ff41ce 3544 struct kvm_pit_config pit_config;
f0d66275 3545 } u;
1fe779f8
CO		 3546
3547 switch (ioctl) {
3548 case KVM_SET_TSS_ADDR:
3549 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3550 if (r < 0)
3551 goto out;
3552 break;
b927a3ce
SY		 3553 case KVM_SET_IDENTITY_MAP_ADDR: {
3554 u64 ident_addr;
3555
3556 r = -EFAULT;
3557 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3558 goto out;
3559 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3560 if (r < 0)
3561 goto out;
3562 break;
3563 }
1fe779f8
CO		 3564 case KVM_SET_NR_MMU_PAGES:
3565 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3566 if (r)
3567 goto out;
3568 break;
3569 case KVM_GET_NR_MMU_PAGES:
3570 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3571 break;
3ddea128
MT		 3572 case KVM_CREATE_IRQCHIP: {
3573 struct kvm_pic *vpic;
3574
3575 mutex_lock(&kvm->lock);
3576 r = -EEXIST;
3577 if (kvm->arch.vpic)
3578 goto create_irqchip_unlock;
1fe779f8 3579 r = -ENOMEM;
3ddea128
MT		 3580 vpic = kvm_create_pic(kvm);
3581 if (vpic) {
1fe779f8
CO		 3582 r = kvm_ioapic_init(kvm);
3583 if (r) {
175504cd 3584 mutex_lock(&kvm->slots_lock);
72bb2fcd 3585 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3586 &vpic->dev_master);
3587 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3588 &vpic->dev_slave);
3589 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3590 &vpic->dev_eclr);
175504cd 3591 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3592 kfree(vpic);
3593 goto create_irqchip_unlock;
1fe779f8
CO		 3594 }
3595 } else
3ddea128
MT		 3596 goto create_irqchip_unlock;
3597 smp_wmb();
3598 kvm->arch.vpic = vpic;
3599 smp_wmb();
399ec807
AK		 3600 r = kvm_setup_default_irq_routing(kvm);
3601 if (r) {
175504cd 3602 mutex_lock(&kvm->slots_lock);
3ddea128 3603 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3604 kvm_ioapic_destroy(kvm);
3605 kvm_destroy_pic(kvm);
3ddea128 3606 mutex_unlock(&kvm->irq_lock);
175504cd 3607 mutex_unlock(&kvm->slots_lock);
399ec807 3608 }
3ddea128
MT		 3609 create_irqchip_unlock:
3610 mutex_unlock(&kvm->lock);
1fe779f8 3611 break;
3ddea128 3612 }
7837699f 3613 case KVM_CREATE_PIT:
c5ff41ce
JK		 3614 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3615 goto create_pit;
3616 case KVM_CREATE_PIT2:
3617 r = -EFAULT;
3618 if (copy_from_user(&u.pit_config, argp,
3619 sizeof(struct kvm_pit_config)))
3620 goto out;
3621 create_pit:
79fac95e 3622 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3623 r = -EEXIST;
3624 if (kvm->arch.vpit)
3625 goto create_pit_unlock;
7837699f 3626 r = -ENOMEM;
c5ff41ce 3627 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3628 if (kvm->arch.vpit)
3629 r = 0;
269e05e4 3630 create_pit_unlock:
79fac95e 3631 mutex_unlock(&kvm->slots_lock);
7837699f 3632 break;
4925663a 3633 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3634 case KVM_IRQ_LINE: {
3635 struct kvm_irq_level irq_event;
3636
3637 r = -EFAULT;
3638 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3639 goto out;
160d2f6c 3640 r = -ENXIO;
1fe779f8 3641 if (irqchip_in_kernel(kvm)) {
4925663a 3642 __s32 status;
4925663a
GN		 3643 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3644 irq_event.irq, irq_event.level);
4925663a 3645 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3646 r = -EFAULT;
4925663a
GN		 3647 irq_event.status = status;
3648 if (copy_to_user(argp, &irq_event,
3649 sizeof irq_event))
3650 goto out;
3651 }
1fe779f8
CO		 3652 r = 0;
3653 }
3654 break;
3655 }
3656 case KVM_GET_IRQCHIP: {
3657 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3658 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3659
f0d66275
DH		 3660 r = -ENOMEM;
3661 if (!chip)
1fe779f8 3662 goto out;
f0d66275
DH		 3663 r = -EFAULT;
3664 if (copy_from_user(chip, argp, sizeof *chip))
3665 goto get_irqchip_out;
1fe779f8
CO		 3666 r = -ENXIO;
3667 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3668 goto get_irqchip_out;
3669 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3670 if (r)
f0d66275 3671 goto get_irqchip_out;
1fe779f8 3672 r = -EFAULT;
f0d66275
DH		 3673 if (copy_to_user(argp, chip, sizeof *chip))
3674 goto get_irqchip_out;
1fe779f8 3675 r = 0;
f0d66275
DH		 3676 get_irqchip_out:
3677 kfree(chip);
3678 if (r)
3679 goto out;
1fe779f8
CO		 3680 break;
3681 }
3682 case KVM_SET_IRQCHIP: {
3683 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3684 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3685
f0d66275
DH		 3686 r = -ENOMEM;
3687 if (!chip)
1fe779f8 3688 goto out;
f0d66275
DH		 3689 r = -EFAULT;
3690 if (copy_from_user(chip, argp, sizeof *chip))
3691 goto set_irqchip_out;
1fe779f8
CO		 3692 r = -ENXIO;
3693 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3694 goto set_irqchip_out;
3695 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3696 if (r)
f0d66275 3697 goto set_irqchip_out;
1fe779f8 3698 r = 0;
f0d66275
DH		 3699 set_irqchip_out:
3700 kfree(chip);
3701 if (r)
3702 goto out;
1fe779f8
CO		 3703 break;
3704 }
e0f63cb9 3705 case KVM_GET_PIT: {
e0f63cb9 3706 r = -EFAULT;
f0d66275 3707 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3708 goto out;
3709 r = -ENXIO;
3710 if (!kvm->arch.vpit)
3711 goto out;
f0d66275 3712 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3713 if (r)
3714 goto out;
3715 r = -EFAULT;
f0d66275 3716 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3717 goto out;
3718 r = 0;
3719 break;
3720 }
3721 case KVM_SET_PIT: {
e0f63cb9 3722 r = -EFAULT;
f0d66275 3723 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3724 goto out;
3725 r = -ENXIO;
3726 if (!kvm->arch.vpit)
3727 goto out;
f0d66275 3728 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3729 if (r)
3730 goto out;
3731 r = 0;
3732 break;
3733 }
e9f42757
BK		 3734 case KVM_GET_PIT2: {
3735 r = -ENXIO;
3736 if (!kvm->arch.vpit)
3737 goto out;
3738 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3739 if (r)
3740 goto out;
3741 r = -EFAULT;
3742 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3743 goto out;
3744 r = 0;
3745 break;
3746 }
3747 case KVM_SET_PIT2: {
3748 r = -EFAULT;
3749 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3750 goto out;
3751 r = -ENXIO;
3752 if (!kvm->arch.vpit)
3753 goto out;
3754 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3755 if (r)
3756 goto out;
3757 r = 0;
3758 break;
3759 }
52d939a0
MT		 3760 case KVM_REINJECT_CONTROL: {
3761 struct kvm_reinject_control control;
3762 r = -EFAULT;
3763 if (copy_from_user(&control, argp, sizeof(control)))
3764 goto out;
3765 r = kvm_vm_ioctl_reinject(kvm, &control);
3766 if (r)
3767 goto out;
3768 r = 0;
3769 break;
3770 }
ffde22ac
ES		 3771 case KVM_XEN_HVM_CONFIG: {
3772 r = -EFAULT;
3773 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3774 sizeof(struct kvm_xen_hvm_config)))
3775 goto out;
3776 r = -EINVAL;
3777 if (kvm->arch.xen_hvm_config.flags)
3778 goto out;
3779 r = 0;
3780 break;
3781 }
afbcf7ab 3782 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3783 struct kvm_clock_data user_ns;
3784 u64 now_ns;
3785 s64 delta;
3786
3787 r = -EFAULT;
3788 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3789 goto out;
3790
3791 r = -EINVAL;
3792 if (user_ns.flags)
3793 goto out;
3794
3795 r = 0;
395c6b0a 3796 local_irq_disable();
759379dd 3797 now_ns = get_kernel_ns();
afbcf7ab 3798 delta = user_ns.clock - now_ns;
395c6b0a 3799 local_irq_enable();
afbcf7ab
GC		 3800 kvm->arch.kvmclock_offset = delta;
3801 break;
3802 }
3803 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3804 struct kvm_clock_data user_ns;
3805 u64 now_ns;
3806
395c6b0a 3807 local_irq_disable();
759379dd 3808 now_ns = get_kernel_ns();
afbcf7ab 3809 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3810 local_irq_enable();
afbcf7ab 3811 user_ns.flags = 0;
97e69aa6 3812 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3813
3814 r = -EFAULT;
3815 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3816 goto out;
3817 r = 0;
3818 break;
3819 }
3820
1fe779f8
CO		 3821 default:
3822 ;
3823 }
3824out:
3825 return r;
3826}
3827
a16b043c 3828static void kvm_init_msr_list(void)
043405e1
CO		 3829{
3830 u32 dummy[2];
3831 unsigned i, j;
3832
e3267cbb
GC		 3833 /* skip the first msrs in the list. KVM-specific */
3834 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3835 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3836 continue;
3837 if (j < i)
3838 msrs_to_save[j] = msrs_to_save[i];
3839 j++;
3840 }
3841 num_msrs_to_save = j;
3842}
3843
bda9020e
MT		 3844static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3845 const void *v)
bbd9b64e 3846{
70252a10
AK		 3847 int handled = 0;
3848 int n;
3849
3850 do {
3851 n = min(len, 8);
3852 if (!(vcpu->arch.apic &&
3853 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3854 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3855 break;
3856 handled += n;
3857 addr += n;
3858 len -= n;
3859 v += n;
3860 } while (len);
bbd9b64e 3861
70252a10 3862 return handled;
bbd9b64e
CO		 3863}
3864
bda9020e 3865static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3866{
70252a10
AK		 3867 int handled = 0;
3868 int n;
3869
3870 do {
3871 n = min(len, 8);
3872 if (!(vcpu->arch.apic &&
3873 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3874 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3875 break;
3876 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3877 handled += n;
3878 addr += n;
3879 len -= n;
3880 v += n;
3881 } while (len);
bbd9b64e 3882
70252a10 3883 return handled;
bbd9b64e
CO		 3884}
3885
2dafc6c2
GN		 3886static void kvm_set_segment(struct kvm_vcpu *vcpu,
3887 struct kvm_segment *var, int seg)
3888{
3889 kvm_x86_ops->set_segment(vcpu, var, seg);
3890}
3891
3892void kvm_get_segment(struct kvm_vcpu *vcpu,
3893 struct kvm_segment *var, int seg)
3894{
3895 kvm_x86_ops->get_segment(vcpu, var, seg);
3896}
3897
c30a358d
JR		 3898static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3899{
3900 return gpa;
3901}
3902
02f59dc9
JR		 3903static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3904{
3905 gpa_t t_gpa;
ab9ae313 3906 struct x86_exception exception;
02f59dc9
JR		 3907
3908 BUG_ON(!mmu_is_nested(vcpu));
3909
3910 /* NPT walks are always user-walks */
3911 access |= PFERR_USER_MASK;
ab9ae313 3912 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3913
3914 return t_gpa;
3915}
3916
ab9ae313
AK		 3917gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3918 struct x86_exception *exception)
1871c602
GN		 3919{
3920 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3921 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3922}
3923
ab9ae313
AK		 3924 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3925 struct x86_exception *exception)
1871c602
GN		 3926{
3927 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3928 access |= PFERR_FETCH_MASK;
ab9ae313 3929 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3930}
3931
ab9ae313
AK		 3932gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3933 struct x86_exception *exception)
1871c602
GN		 3934{
3935 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3936 access |= PFERR_WRITE_MASK;
ab9ae313 3937 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3938}
3939
3940/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3941gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3942 struct x86_exception *exception)
1871c602 3943{
ab9ae313 3944 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3945}
3946
3947static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3948 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3949 struct x86_exception *exception)
bbd9b64e
CO		 3950{
3951 void *data = val;
10589a46 3952 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3953
3954 while (bytes) {
14dfe855 3955 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3956 exception);
bbd9b64e 3957 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3958 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3959 int ret;
3960
bcc55cba 3961 if (gpa == UNMAPPED_GVA)
ab9ae313 3962 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3963 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3964 if (ret < 0) {
c3cd7ffa 3965 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3966 goto out;
3967 }
bbd9b64e 3968
77c2002e
IE		 3969 bytes -= toread;
3970 data += toread;
3971 addr += toread;
bbd9b64e 3972 }
10589a46 3973out:
10589a46 3974 return r;
bbd9b64e 3975}
77c2002e 3976
1871c602 3977/* used for instruction fetching */
0f65dd70
AK		 3978static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3979 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3980 struct x86_exception *exception)
1871c602 3981{
0f65dd70 3982 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3983 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3984
1871c602 3985 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3986 access | PFERR_FETCH_MASK,
3987 exception);
1871c602
GN		 3988}
3989
064aea77 3990int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3991 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3992 struct x86_exception *exception)
1871c602 3993{
0f65dd70 3994 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3995 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3996
1871c602 3997 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3998 exception);
1871c602 3999}
064aea77 4000EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4001
0f65dd70
AK		 4002static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4003 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4004 struct x86_exception *exception)
1871c602 4005{
0f65dd70 4006 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4007 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4008}
4009
6a4d7550 4010int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4011 gva_t addr, void *val,
2dafc6c2 4012 unsigned int bytes,
bcc55cba 4013 struct x86_exception *exception)
77c2002e 4014{
0f65dd70 4015 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4016 void *data = val;
4017 int r = X86EMUL_CONTINUE;
4018
4019 while (bytes) {
14dfe855
JR		 4020 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4021 PFERR_WRITE_MASK,
ab9ae313 4022 exception);
77c2002e
IE		 4023 unsigned offset = addr & (PAGE_SIZE-1);
4024 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4025 int ret;
4026
bcc55cba 4027 if (gpa == UNMAPPED_GVA)
ab9ae313 4028 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4029 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4030 if (ret < 0) {
c3cd7ffa 4031 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4032 goto out;
4033 }
4034
4035 bytes -= towrite;
4036 data += towrite;
4037 addr += towrite;
4038 }
4039out:
4040 return r;
4041}
6a4d7550 4042EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4043
af7cc7d1
XG		 4044static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4045 gpa_t *gpa, struct x86_exception *exception,
4046 bool write)
4047{
4048 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4049
bebb106a
XG		 4050 if (vcpu_match_mmio_gva(vcpu, gva) &&
4051 check_write_user_access(vcpu, write, access,
4052 vcpu->arch.access)) {
4053 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4054 (gva & (PAGE_SIZE - 1));
4f022648 4055 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4056 return 1;
4057 }
4058
af7cc7d1
XG		 4059 if (write)
4060 access |= PFERR_WRITE_MASK;
4061
4062 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4063
4064 if (*gpa == UNMAPPED_GVA)
4065 return -1;
4066
4067 /* For APIC access vmexit */
4068 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4069 return 1;
4070
4f022648
XG		 4071 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4072 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4073 return 1;
4f022648 4074 }
bebb106a 4075
af7cc7d1
XG		 4076 return 0;
4077}
4078
3200f405 4079int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4080 const void *val, int bytes)
bbd9b64e
CO		 4081{
4082 int ret;
4083
4084 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4085 if (ret < 0)
bbd9b64e 4086 return 0;
f57f2ef5 4087 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4088 return 1;
4089}
4090
77d197b2
XG		 4091struct read_write_emulator_ops {
4092 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4093 int bytes);
4094 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4095 void *val, int bytes);
4096 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4097 int bytes, void *val);
4098 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4099 void *val, int bytes);
4100 bool write;
4101};
4102
4103static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4104{
4105 if (vcpu->mmio_read_completed) {
4106 memcpy(val, vcpu->mmio_data, bytes);
4107 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4108 vcpu->mmio_phys_addr, *(u64 *)val);
4109 vcpu->mmio_read_completed = 0;
4110 return 1;
4111 }
4112
4113 return 0;
4114}
4115
4116static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4117 void *val, int bytes)
4118{
4119 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4120}
4121
4122static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4123 void *val, int bytes)
4124{
4125 return emulator_write_phys(vcpu, gpa, val, bytes);
4126}
4127
4128static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4129{
4130 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4131 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4132}
4133
4134static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4135 void *val, int bytes)
4136{
4137 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4138 return X86EMUL_IO_NEEDED;
4139}
4140
4141static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4142 void *val, int bytes)
4143{
4144 memcpy(vcpu->mmio_data, val, bytes);
4145 memcpy(vcpu->run->mmio.data, vcpu->mmio_data, 8);
4146 return X86EMUL_CONTINUE;
4147}
4148
4149static struct read_write_emulator_ops read_emultor = {
4150 .read_write_prepare = read_prepare,
4151 .read_write_emulate = read_emulate,
4152 .read_write_mmio = vcpu_mmio_read,
4153 .read_write_exit_mmio = read_exit_mmio,
4154};
4155
4156static struct read_write_emulator_ops write_emultor = {
4157 .read_write_emulate = write_emulate,
4158 .read_write_mmio = write_mmio,
4159 .read_write_exit_mmio = write_exit_mmio,
4160 .write = true,
4161};
4162
22388a3c
XG		 4163static int emulator_read_write_onepage(unsigned long addr, void *val,
4164 unsigned int bytes,
4165 struct x86_exception *exception,
4166 struct kvm_vcpu *vcpu,
4167 struct read_write_emulator_ops *ops)
bbd9b64e 4168{
af7cc7d1
XG		 4169 gpa_t gpa;
4170 int handled, ret;
22388a3c
XG		 4171 bool write = ops->write;
4172
4173 if (ops->read_write_prepare &&
4174 ops->read_write_prepare(vcpu, val, bytes))
4175 return X86EMUL_CONTINUE;
10589a46 4176
22388a3c 4177 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4178
af7cc7d1 4179 if (ret < 0)
bbd9b64e 4180 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4181
4182 /* For APIC access vmexit */
af7cc7d1 4183 if (ret)
bbd9b64e
CO		 4184 goto mmio;
4185
22388a3c 4186 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4187 return X86EMUL_CONTINUE;
4188
4189mmio:
4190 /*
4191 * Is this MMIO handled locally?
4192 */
22388a3c 4193 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4194 if (handled == bytes)
bbd9b64e 4195 return X86EMUL_CONTINUE;
bbd9b64e 4196
70252a10
AK		 4197 gpa += handled;
4198 bytes -= handled;
4199 val += handled;
4200
bbd9b64e 4201 vcpu->mmio_needed = 1;
411c35b7
GN		 4202 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4203 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
cef4dea0
AK		 4204 vcpu->mmio_size = bytes;
4205 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
22388a3c 4206 vcpu->run->mmio.is_write = vcpu->mmio_is_write = write;
cef4dea0 4207 vcpu->mmio_index = 0;
bbd9b64e 4208
22388a3c 4209 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4210}
4211
22388a3c
XG		 4212int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4213 void *val, unsigned int bytes,
4214 struct x86_exception *exception,
4215 struct read_write_emulator_ops *ops)
bbd9b64e 4216{
0f65dd70
AK		 4217 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4218
bbd9b64e
CO		 4219 /* Crossing a page boundary? */
4220 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4221 int rc, now;
4222
4223 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4224 rc = emulator_read_write_onepage(addr, val, now, exception,
4225 vcpu, ops);
4226
bbd9b64e
CO		 4227 if (rc != X86EMUL_CONTINUE)
4228 return rc;
4229 addr += now;
4230 val += now;
4231 bytes -= now;
4232 }
22388a3c
XG		 4233
4234 return emulator_read_write_onepage(addr, val, bytes, exception,
4235 vcpu, ops);
4236}
4237
4238static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4239 unsigned long addr,
4240 void *val,
4241 unsigned int bytes,
4242 struct x86_exception *exception)
4243{
4244 return emulator_read_write(ctxt, addr, val, bytes,
4245 exception, &read_emultor);
4246}
4247
4248int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4249 unsigned long addr,
4250 const void *val,
4251 unsigned int bytes,
4252 struct x86_exception *exception)
4253{
4254 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4255 exception, &write_emultor);
bbd9b64e 4256}
bbd9b64e 4257
daea3e73
AK		 4258#define CMPXCHG_TYPE(t, ptr, old, new) \
4259 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4260
4261#ifdef CONFIG_X86_64
4262# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4263#else
4264# define CMPXCHG64(ptr, old, new) \
9749a6c0 4265 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4266#endif
4267
0f65dd70
AK		 4268static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4269 unsigned long addr,
bbd9b64e
CO		 4270 const void *old,
4271 const void *new,
4272 unsigned int bytes,
0f65dd70 4273 struct x86_exception *exception)
bbd9b64e 4274{
0f65dd70 4275 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4276 gpa_t gpa;
4277 struct page *page;
4278 char *kaddr;
4279 bool exchanged;
2bacc55c 4280
daea3e73
AK		 4281 /* guests cmpxchg8b have to be emulated atomically */
4282 if (bytes > 8 || (bytes & (bytes - 1)))
4283 goto emul_write;
10589a46 4284
daea3e73 4285 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4286
daea3e73
AK		 4287 if (gpa == UNMAPPED_GVA ||
4288 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4289 goto emul_write;
2bacc55c 4290
daea3e73
AK		 4291 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4292 goto emul_write;
72dc67a6 4293
daea3e73 4294 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 4295 if (is_error_page(page)) {
4296 kvm_release_page_clean(page);
4297 goto emul_write;
4298 }
72dc67a6 4299
daea3e73
AK		 4300 kaddr = kmap_atomic(page, KM_USER0);
4301 kaddr += offset_in_page(gpa);
4302 switch (bytes) {
4303 case 1:
4304 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4305 break;
4306 case 2:
4307 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4308 break;
4309 case 4:
4310 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4311 break;
4312 case 8:
4313 exchanged = CMPXCHG64(kaddr, old, new);
4314 break;
4315 default:
4316 BUG();
2bacc55c 4317 }
daea3e73
AK		 4318 kunmap_atomic(kaddr, KM_USER0);
4319 kvm_release_page_dirty(page);
4320
4321 if (!exchanged)
4322 return X86EMUL_CMPXCHG_FAILED;
4323
f57f2ef5 4324 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4325
4326 return X86EMUL_CONTINUE;
4a5f48f6 4327
3200f405 4328emul_write:
daea3e73 4329 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4330
0f65dd70 4331 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4332}
4333
cf8f70bf
GN		 4334static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4335{
4336 /* TODO: String I/O for in kernel device */
4337 int r;
4338
4339 if (vcpu->arch.pio.in)
4340 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4341 vcpu->arch.pio.size, pd);
4342 else
4343 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4344 vcpu->arch.pio.port, vcpu->arch.pio.size,
4345 pd);
4346 return r;
4347}
4348
6f6fbe98
XG		 4349static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4350 unsigned short port, void *val,
4351 unsigned int count, bool in)
cf8f70bf 4352{
6f6fbe98 4353 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 4354
4355 vcpu->arch.pio.port = port;
6f6fbe98 4356 vcpu->arch.pio.in = in;
7972995b 4357 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4358 vcpu->arch.pio.size = size;
4359
4360 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4361 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4362 return 1;
4363 }
4364
4365 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4366 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4367 vcpu->run->io.size = size;
4368 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4369 vcpu->run->io.count = count;
4370 vcpu->run->io.port = port;
4371
4372 return 0;
4373}
4374
6f6fbe98
XG		 4375static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4376 int size, unsigned short port, void *val,
4377 unsigned int count)
cf8f70bf 4378{
ca1d4a9e 4379 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4380 int ret;
ca1d4a9e 4381
6f6fbe98
XG		 4382 if (vcpu->arch.pio.count)
4383 goto data_avail;
cf8f70bf 4384
6f6fbe98
XG		 4385 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4386 if (ret) {
4387data_avail:
4388 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4389 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4390 return 1;
4391 }
4392
cf8f70bf
GN		 4393 return 0;
4394}
4395
6f6fbe98
XG		 4396static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4397 int size, unsigned short port,
4398 const void *val, unsigned int count)
4399{
4400 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4401
4402 memcpy(vcpu->arch.pio_data, val, size * count);
4403 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4404}
4405
bbd9b64e
CO		 4406static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4407{
4408 return kvm_x86_ops->get_segment_base(vcpu, seg);
4409}
4410
3cb16fe7 4411static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4412{
3cb16fe7 4413 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4414}
4415
f5f48ee1
SY		 4416int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4417{
4418 if (!need_emulate_wbinvd(vcpu))
4419 return X86EMUL_CONTINUE;
4420
4421 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4422 int cpu = get_cpu();
4423
4424 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4425 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4426 wbinvd_ipi, NULL, 1);
2eec7343 4427 put_cpu();
f5f48ee1 4428 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4429 } else
4430 wbinvd();
f5f48ee1
SY		 4431 return X86EMUL_CONTINUE;
4432}
4433EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4434
bcaf5cc5
AK		 4435static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4436{
4437 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4438}
4439
717746e3 4440int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4441{
717746e3 4442 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4443}
4444
717746e3 4445int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4446{
338dbc97 4447
717746e3 4448 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4449}
4450
52a46617 4451static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4452{
52a46617 4453 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4454}
4455
717746e3 4456static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4457{
717746e3 4458 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4459 unsigned long value;
4460
4461 switch (cr) {
4462 case 0:
4463 value = kvm_read_cr0(vcpu);
4464 break;
4465 case 2:
4466 value = vcpu->arch.cr2;
4467 break;
4468 case 3:
9f8fe504 4469 value = kvm_read_cr3(vcpu);
52a46617
GN		 4470 break;
4471 case 4:
4472 value = kvm_read_cr4(vcpu);
4473 break;
4474 case 8:
4475 value = kvm_get_cr8(vcpu);
4476 break;
4477 default:
4478 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4479 return 0;
4480 }
4481
4482 return value;
4483}
4484
717746e3 4485static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4486{
717746e3 4487 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4488 int res = 0;
4489
52a46617
GN		 4490 switch (cr) {
4491 case 0:
49a9b07e 4492 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4493 break;
4494 case 2:
4495 vcpu->arch.cr2 = val;
4496 break;
4497 case 3:
2390218b 4498 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4499 break;
4500 case 4:
a83b29c6 4501 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4502 break;
4503 case 8:
eea1cff9 4504 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4505 break;
4506 default:
4507 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4508 res = -1;
52a46617 4509 }
0f12244f
GN		 4510
4511 return res;
52a46617
GN		 4512}
4513
717746e3 4514static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4515{
717746e3 4516 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4517}
4518
4bff1e86 4519static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4520{
4bff1e86 4521 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4522}
4523
4bff1e86 4524static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4525{
4bff1e86 4526 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4527}
4528
1ac9d0cf
AK		 4529static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4530{
4531 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4532}
4533
4534static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4535{
4536 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4537}
4538
4bff1e86
AK		 4539static unsigned long emulator_get_cached_segment_base(
4540 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4541{
4bff1e86 4542 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4543}
4544
1aa36616
AK		 4545static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4546 struct desc_struct *desc, u32 *base3,
4547 int seg)
2dafc6c2
GN		 4548{
4549 struct kvm_segment var;
4550
4bff1e86 4551 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4552 *selector = var.selector;
2dafc6c2
GN		 4553
4554 if (var.unusable)
4555 return false;
4556
4557 if (var.g)
4558 var.limit >>= 12;
4559 set_desc_limit(desc, var.limit);
4560 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4561#ifdef CONFIG_X86_64
4562 if (base3)
4563 *base3 = var.base >> 32;
4564#endif
2dafc6c2
GN		 4565 desc->type = var.type;
4566 desc->s = var.s;
4567 desc->dpl = var.dpl;
4568 desc->p = var.present;
4569 desc->avl = var.avl;
4570 desc->l = var.l;
4571 desc->d = var.db;
4572 desc->g = var.g;
4573
4574 return true;
4575}
4576
1aa36616
AK		 4577static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4578 struct desc_struct *desc, u32 base3,
4579 int seg)
2dafc6c2 4580{
4bff1e86 4581 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4582 struct kvm_segment var;
4583
1aa36616 4584 var.selector = selector;
2dafc6c2 4585 var.base = get_desc_base(desc);
5601d05b
GN		 4586#ifdef CONFIG_X86_64
4587 var.base |= ((u64)base3) << 32;
4588#endif
2dafc6c2
GN		 4589 var.limit = get_desc_limit(desc);
4590 if (desc->g)
4591 var.limit = (var.limit << 12) | 0xfff;
4592 var.type = desc->type;
4593 var.present = desc->p;
4594 var.dpl = desc->dpl;
4595 var.db = desc->d;
4596 var.s = desc->s;
4597 var.l = desc->l;
4598 var.g = desc->g;
4599 var.avl = desc->avl;
4600 var.present = desc->p;
4601 var.unusable = !var.present;
4602 var.padding = 0;
4603
4604 kvm_set_segment(vcpu, &var, seg);
4605 return;
4606}
4607
717746e3
AK		 4608static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4609 u32 msr_index, u64 *pdata)
4610{
4611 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4612}
4613
4614static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4615 u32 msr_index, u64 data)
4616{
4617 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4618}
4619
6c3287f7
AK		 4620static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4621{
4622 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4623}
4624
5037f6f3
AK		 4625static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4626{
4627 preempt_disable();
5197b808 4628 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4629 /*
4630 * CR0.TS may reference the host fpu state, not the guest fpu state,
4631 * so it may be clear at this point.
4632 */
4633 clts();
4634}
4635
4636static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4637{
4638 preempt_enable();
4639}
4640
2953538e 4641static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4642 struct x86_instruction_info *info,
c4f035c6
AK		 4643 enum x86_intercept_stage stage)
4644{
2953538e 4645 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4646}
4647
14af3f3c 4648static struct x86_emulate_ops emulate_ops = {
1871c602 4649 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4650 .write_std = kvm_write_guest_virt_system,
1871c602 4651 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4652 .read_emulated = emulator_read_emulated,
4653 .write_emulated = emulator_write_emulated,
4654 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4655 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4656 .pio_in_emulated = emulator_pio_in_emulated,
4657 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4658 .get_segment = emulator_get_segment,
4659 .set_segment = emulator_set_segment,
5951c442 4660 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4661 .get_gdt = emulator_get_gdt,
160ce1f1 4662 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4663 .set_gdt = emulator_set_gdt,
4664 .set_idt = emulator_set_idt,
52a46617
GN		 4665 .get_cr = emulator_get_cr,
4666 .set_cr = emulator_set_cr,
9c537244 4667 .cpl = emulator_get_cpl,
35aa5375
GN		 4668 .get_dr = emulator_get_dr,
4669 .set_dr = emulator_set_dr,
717746e3
AK		 4670 .set_msr = emulator_set_msr,
4671 .get_msr = emulator_get_msr,
6c3287f7 4672 .halt = emulator_halt,
bcaf5cc5 4673 .wbinvd = emulator_wbinvd,
d6aa1000 4674 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4675 .get_fpu = emulator_get_fpu,
4676 .put_fpu = emulator_put_fpu,
c4f035c6 4677 .intercept = emulator_intercept,
bbd9b64e
CO		 4678};
4679
5fdbf976
MT		 4680static void cache_all_regs(struct kvm_vcpu *vcpu)
4681{
4682 kvm_register_read(vcpu, VCPU_REGS_RAX);
4683 kvm_register_read(vcpu, VCPU_REGS_RSP);
4684 kvm_register_read(vcpu, VCPU_REGS_RIP);
4685 vcpu->arch.regs_dirty = ~0;
4686}
4687
95cb2295
GN		 4688static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4689{
4690 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4691 /*
4692 * an sti; sti; sequence only disable interrupts for the first
4693 * instruction. So, if the last instruction, be it emulated or
4694 * not, left the system with the INT_STI flag enabled, it
4695 * means that the last instruction is an sti. We should not
4696 * leave the flag on in this case. The same goes for mov ss
4697 */
4698 if (!(int_shadow & mask))
4699 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4700}
4701
54b8486f
GN		 4702static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4703{
4704 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4705 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4706 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4707 else if (ctxt->exception.error_code_valid)
4708 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4709 ctxt->exception.error_code);
54b8486f 4710 else
da9cb575 4711 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4712}
4713
9dac77fa 4714static void init_decode_cache(struct x86_emulate_ctxt *ctxt,
b5c9ff73
TY		 4715 const unsigned long *regs)
4716{
9dac77fa
AK		 4717 memset(&ctxt->twobyte, 0,
4718 (void *)&ctxt->regs - (void *)&ctxt->twobyte);
4719 memcpy(ctxt->regs, regs, sizeof(ctxt->regs));
b5c9ff73 4720
9dac77fa
AK		 4721 ctxt->fetch.start = 0;
4722 ctxt->fetch.end = 0;
4723 ctxt->io_read.pos = 0;
4724 ctxt->io_read.end = 0;
4725 ctxt->mem_read.pos = 0;
4726 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4727}
4728
8ec4722d
MG		 4729static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4730{
adf52235 4731 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4732 int cs_db, cs_l;
4733
2aab2c5b
GN		 4734 /*
4735 * TODO: fix emulate.c to use guest_read/write_register
4736 * instead of direct ->regs accesses, can save hundred cycles
4737 * on Intel for instructions that don't read/change RSP, for
4738 * for example.
4739 */
8ec4722d
MG		 4740 cache_all_regs(vcpu);
4741
4742 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4743
adf52235
TY		 4744 ctxt->eflags = kvm_get_rflags(vcpu);
4745 ctxt->eip = kvm_rip_read(vcpu);
4746 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4747 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4748 cs_l ? X86EMUL_MODE_PROT64 :
4749 cs_db ? X86EMUL_MODE_PROT32 :
4750 X86EMUL_MODE_PROT16;
4751 ctxt->guest_mode = is_guest_mode(vcpu);
4752
9dac77fa 4753 init_decode_cache(ctxt, vcpu->arch.regs);
7ae441ea 4754 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4755}
4756
71f9833b 4757int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4758{
9d74191a 4759 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4760 int ret;
4761
4762 init_emulate_ctxt(vcpu);
4763
9dac77fa
AK		 4764 ctxt->op_bytes = 2;
4765 ctxt->ad_bytes = 2;
4766 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4767 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4768
4769 if (ret != X86EMUL_CONTINUE)
4770 return EMULATE_FAIL;
4771
9dac77fa
AK		 4772 ctxt->eip = ctxt->_eip;
4773 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 4774 kvm_rip_write(vcpu, ctxt->eip);
4775 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4776
4777 if (irq == NMI_VECTOR)
7460fb4a 4778 vcpu->arch.nmi_pending = 0;
63995653
MG		 4779 else
4780 vcpu->arch.interrupt.pending = false;
4781
4782 return EMULATE_DONE;
4783}
4784EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4785
6d77dbfc
GN		 4786static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4787{
fc3a9157
JR		 4788 int r = EMULATE_DONE;
4789
6d77dbfc
GN		 4790 ++vcpu->stat.insn_emulation_fail;
4791 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4792 if (!is_guest_mode(vcpu)) {
4793 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4794 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4795 vcpu->run->internal.ndata = 0;
4796 r = EMULATE_FAIL;
4797 }
6d77dbfc 4798 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4799
4800 return r;
6d77dbfc
GN		 4801}
4802
a6f177ef
GN		 4803static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4804{
4805 gpa_t gpa;
4806
68be0803
GN		 4807 if (tdp_enabled)
4808 return false;
4809
a6f177ef
GN		 4810 /*
4811 * if emulation was due to access to shadowed page table
4812 * and it failed try to unshadow page and re-entetr the
4813 * guest to let CPU execute the instruction.
4814 */
4815 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4816 return true;
4817
4818 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4819
4820 if (gpa == UNMAPPED_GVA)
4821 return true; /* let cpu generate fault */
4822
4823 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4824 return true;
4825
4826 return false;
4827}
4828
1cb3f3ae
XG		 4829static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4830 unsigned long cr2, int emulation_type)
4831{
4832 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4833 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4834
4835 last_retry_eip = vcpu->arch.last_retry_eip;
4836 last_retry_addr = vcpu->arch.last_retry_addr;
4837
4838 /*
4839 * If the emulation is caused by #PF and it is non-page_table
4840 * writing instruction, it means the VM-EXIT is caused by shadow
4841 * page protected, we can zap the shadow page and retry this
4842 * instruction directly.
4843 *
4844 * Note: if the guest uses a non-page-table modifying instruction
4845 * on the PDE that points to the instruction, then we will unmap
4846 * the instruction and go to an infinite loop. So, we cache the
4847 * last retried eip and the last fault address, if we meet the eip
4848 * and the address again, we can break out of the potential infinite
4849 * loop.
4850 */
4851 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4852
4853 if (!(emulation_type & EMULTYPE_RETRY))
4854 return false;
4855
4856 if (x86_page_table_writing_insn(ctxt))
4857 return false;
4858
4859 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4860 return false;
4861
4862 vcpu->arch.last_retry_eip = ctxt->eip;
4863 vcpu->arch.last_retry_addr = cr2;
4864
4865 if (!vcpu->arch.mmu.direct_map)
4866 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4867
4868 kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4869
4870 return true;
4871}
4872
51d8b661
AP		 4873int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4874 unsigned long cr2,
dc25e89e
AP		 4875 int emulation_type,
4876 void *insn,
4877 int insn_len)
bbd9b64e 4878{
95cb2295 4879 int r;
9d74191a 4880 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 4881 bool writeback = true;
bbd9b64e 4882
26eef70c 4883 kvm_clear_exception_queue(vcpu);
8d7d8102 4884
571008da 4885 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4886 init_emulate_ctxt(vcpu);
9d74191a
TY		 4887 ctxt->interruptibility = 0;
4888 ctxt->have_exception = false;
4889 ctxt->perm_ok = false;
bbd9b64e 4890
9d74191a 4891 ctxt->only_vendor_specific_insn
4005996e
AK		 4892 = emulation_type & EMULTYPE_TRAP_UD;
4893
9d74191a 4894 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 4895
e46479f8 4896 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4897 ++vcpu->stat.insn_emulation;
1d2887e2 4898 if (r != EMULATION_OK) {
4005996e
AK		 4899 if (emulation_type & EMULTYPE_TRAP_UD)
4900 return EMULATE_FAIL;
a6f177ef 4901 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4902 return EMULATE_DONE;
6d77dbfc
GN		 4903 if (emulation_type & EMULTYPE_SKIP)
4904 return EMULATE_FAIL;
4905 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4906 }
4907 }
4908
ba8afb6b 4909 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 4910 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 4911 return EMULATE_DONE;
4912 }
4913
1cb3f3ae
XG		 4914 if (retry_instruction(ctxt, cr2, emulation_type))
4915 return EMULATE_DONE;
4916
7ae441ea 4917 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4918 changes registers values during IO operation */
7ae441ea
GN		 4919 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4920 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
9dac77fa 4921 memcpy(ctxt->regs, vcpu->arch.regs, sizeof ctxt->regs);
7ae441ea 4922 }
4d2179e1 4923
5cd21917 4924restart:
9d74191a 4925 r = x86_emulate_insn(ctxt);
bbd9b64e 4926
775fde86
JR		 4927 if (r == EMULATION_INTERCEPTED)
4928 return EMULATE_DONE;
4929
d2ddd1c4 4930 if (r == EMULATION_FAILED) {
a6f177ef 4931 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4932 return EMULATE_DONE;
4933
6d77dbfc 4934 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4935 }
4936
9d74191a 4937 if (ctxt->have_exception) {
54b8486f 4938 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4939 r = EMULATE_DONE;
4940 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4941 if (!vcpu->arch.pio.in)
4942 vcpu->arch.pio.count = 0;
7ae441ea
GN		 4943 else
4944 writeback = false;
e85d28f8 4945 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4946 } else if (vcpu->mmio_needed) {
4947 if (!vcpu->mmio_is_write)
4948 writeback = false;
e85d28f8 4949 r = EMULATE_DO_MMIO;
7ae441ea 4950 } else if (r == EMULATION_RESTART)
5cd21917 4951 goto restart;
d2ddd1c4
GN		 4952 else
4953 r = EMULATE_DONE;
f850e2e6 4954
7ae441ea 4955 if (writeback) {
9d74191a
TY		 4956 toggle_interruptibility(vcpu, ctxt->interruptibility);
4957 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea 4958 kvm_make_request(KVM_REQ_EVENT, vcpu);
9dac77fa 4959 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea 4960 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 4961 kvm_rip_write(vcpu, ctxt->eip);
7ae441ea
GN		 4962 } else
4963 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4964
4965 return r;
de7d789a 4966}
51d8b661 4967EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4968
cf8f70bf 4969int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4970{
cf8f70bf 4971 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 4972 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4973 size, port, &val, 1);
cf8f70bf 4974 /* do not return to emulator after return from userspace */
7972995b 4975 vcpu->arch.pio.count = 0;
de7d789a
CO		 4976 return ret;
4977}
cf8f70bf 4978EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4979
8cfdc000
ZA		 4980static void tsc_bad(void *info)
4981{
0a3aee0d 4982 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4983}
4984
4985static void tsc_khz_changed(void *data)
c8076604 4986{
8cfdc000
ZA		 4987 struct cpufreq_freqs *freq = data;
4988 unsigned long khz = 0;
4989
4990 if (data)
4991 khz = freq->new;
4992 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4993 khz = cpufreq_quick_get(raw_smp_processor_id());
4994 if (!khz)
4995 khz = tsc_khz;
0a3aee0d 4996 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 4997}
4998
c8076604
GH		 4999static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5000 void *data)
5001{
5002 struct cpufreq_freqs *freq = data;
5003 struct kvm *kvm;
5004 struct kvm_vcpu *vcpu;
5005 int i, send_ipi = 0;
5006
8cfdc000
ZA		 5007 /*
5008 * We allow guests to temporarily run on slowing clocks,
5009 * provided we notify them after, or to run on accelerating
5010 * clocks, provided we notify them before. Thus time never
5011 * goes backwards.
5012 *
5013 * However, we have a problem. We can't atomically update
5014 * the frequency of a given CPU from this function; it is
5015 * merely a notifier, which can be called from any CPU.
5016 * Changing the TSC frequency at arbitrary points in time
5017 * requires a recomputation of local variables related to
5018 * the TSC for each VCPU. We must flag these local variables
5019 * to be updated and be sure the update takes place with the
5020 * new frequency before any guests proceed.
5021 *
5022 * Unfortunately, the combination of hotplug CPU and frequency
5023 * change creates an intractable locking scenario; the order
5024 * of when these callouts happen is undefined with respect to
5025 * CPU hotplug, and they can race with each other. As such,
5026 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5027 * undefined; you can actually have a CPU frequency change take
5028 * place in between the computation of X and the setting of the
5029 * variable. To protect against this problem, all updates of
5030 * the per_cpu tsc_khz variable are done in an interrupt
5031 * protected IPI, and all callers wishing to update the value
5032 * must wait for a synchronous IPI to complete (which is trivial
5033 * if the caller is on the CPU already). This establishes the
5034 * necessary total order on variable updates.
5035 *
5036 * Note that because a guest time update may take place
5037 * anytime after the setting of the VCPU's request bit, the
5038 * correct TSC value must be set before the request. However,
5039 * to ensure the update actually makes it to any guest which
5040 * starts running in hardware virtualization between the set
5041 * and the acquisition of the spinlock, we must also ping the
5042 * CPU after setting the request bit.
5043 *
5044 */
5045
c8076604
GH		 5046 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5047 return 0;
5048 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5049 return 0;
8cfdc000
ZA		 5050
5051 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5052
e935b837 5053 raw_spin_lock(&kvm_lock);
c8076604 5054 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5055 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5056 if (vcpu->cpu != freq->cpu)
5057 continue;
c285545f 5058 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5059 if (vcpu->cpu != smp_processor_id())
8cfdc000 5060 send_ipi = 1;
c8076604
GH		 5061 }
5062 }
e935b837 5063 raw_spin_unlock(&kvm_lock);
c8076604
GH		 5064
5065 if (freq->old < freq->new && send_ipi) {
5066 /*
5067 * We upscale the frequency. Must make the guest
5068 * doesn't see old kvmclock values while running with
5069 * the new frequency, otherwise we risk the guest sees
5070 * time go backwards.
5071 *
5072 * In case we update the frequency for another cpu
5073 * (which might be in guest context) send an interrupt
5074 * to kick the cpu out of guest context. Next time
5075 * guest context is entered kvmclock will be updated,
5076 * so the guest will not see stale values.
5077 */
8cfdc000 5078 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5079 }
5080 return 0;
5081}
5082
5083static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5084 .notifier_call = kvmclock_cpufreq_notifier
5085};
5086
5087static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5088 unsigned long action, void *hcpu)
5089{
5090 unsigned int cpu = (unsigned long)hcpu;
5091
5092 switch (action) {
5093 case CPU_ONLINE:
5094 case CPU_DOWN_FAILED:
5095 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5096 break;
5097 case CPU_DOWN_PREPARE:
5098 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5099 break;
5100 }
5101 return NOTIFY_OK;
5102}
5103
5104static struct notifier_block kvmclock_cpu_notifier_block = {
5105 .notifier_call = kvmclock_cpu_notifier,
5106 .priority = -INT_MAX
c8076604
GH		 5107};
5108
b820cc0c
ZA		 5109static void kvm_timer_init(void)
5110{
5111 int cpu;
5112
c285545f 5113 max_tsc_khz = tsc_khz;
8cfdc000 5114 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 5115 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5116#ifdef CONFIG_CPU_FREQ
5117 struct cpufreq_policy policy;
5118 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5119 cpu = get_cpu();
5120 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5121 if (policy.cpuinfo.max_freq)
5122 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5123 put_cpu();
c285545f 5124#endif
b820cc0c
ZA		 5125 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5126 CPUFREQ_TRANSITION_NOTIFIER);
5127 }
c285545f 5128 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5129 for_each_online_cpu(cpu)
5130 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 5131}
5132
ff9d07a0
ZY		 5133static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5134
5135static int kvm_is_in_guest(void)
5136{
5137 return percpu_read(current_vcpu) != NULL;
5138}
5139
5140static int kvm_is_user_mode(void)
5141{
5142 int user_mode = 3;
dcf46b94 5143
ff9d07a0
ZY		 5144 if (percpu_read(current_vcpu))
5145 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 5146
ff9d07a0
ZY		 5147 return user_mode != 0;
5148}
5149
5150static unsigned long kvm_get_guest_ip(void)
5151{
5152 unsigned long ip = 0;
dcf46b94 5153
ff9d07a0
ZY		 5154 if (percpu_read(current_vcpu))
5155 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 5156
ff9d07a0
ZY		 5157 return ip;
5158}
5159
5160static struct perf_guest_info_callbacks kvm_guest_cbs = {
5161 .is_in_guest = kvm_is_in_guest,
5162 .is_user_mode = kvm_is_user_mode,
5163 .get_guest_ip = kvm_get_guest_ip,
5164};
5165
5166void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5167{
5168 percpu_write(current_vcpu, vcpu);
5169}
5170EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5171
5172void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5173{
5174 percpu_write(current_vcpu, NULL);
5175}
5176EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5177
ce88decf
XG		 5178static void kvm_set_mmio_spte_mask(void)
5179{
5180 u64 mask;
5181 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5182
5183 /*
5184 * Set the reserved bits and the present bit of an paging-structure
5185 * entry to generate page fault with PFER.RSV = 1.
5186 */
5187 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
5188 mask |= 1ull;
5189
5190#ifdef CONFIG_X86_64
5191 /*
5192 * If reserved bit is not supported, clear the present bit to disable
5193 * mmio page fault.
5194 */
5195 if (maxphyaddr == 52)
5196 mask &= ~1ull;
5197#endif
5198
5199 kvm_mmu_set_mmio_spte_mask(mask);
5200}
5201
f8c16bba 5202int kvm_arch_init(void *opaque)
043405e1 5203{
b820cc0c 5204 int r;
f8c16bba
ZX		 5205 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
5206
f8c16bba
ZX		 5207 if (kvm_x86_ops) {
5208 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5209 r = -EEXIST;
5210 goto out;
f8c16bba
ZX		 5211 }
5212
5213 if (!ops->cpu_has_kvm_support()) {
5214 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5215 r = -EOPNOTSUPP;
5216 goto out;
f8c16bba
ZX		 5217 }
5218 if (ops->disabled_by_bios()) {
5219 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5220 r = -EOPNOTSUPP;
5221 goto out;
f8c16bba
ZX		 5222 }
5223
97db56ce
AK		 5224 r = kvm_mmu_module_init();
5225 if (r)
5226 goto out;
5227
ce88decf 5228 kvm_set_mmio_spte_mask();
97db56ce
AK		 5229 kvm_init_msr_list();
5230
f8c16bba 5231 kvm_x86_ops = ops;
7b52345e 5232 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5233 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5234
b820cc0c 5235 kvm_timer_init();
c8076604 5236
ff9d07a0
ZY		 5237 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5238
2acf923e
DC		 5239 if (cpu_has_xsave)
5240 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5241
f8c16bba 5242 return 0;
56c6d28a
ZX		 5243
5244out:
56c6d28a 5245 return r;
043405e1 5246}
8776e519 5247
f8c16bba
ZX		 5248void kvm_arch_exit(void)
5249{
ff9d07a0
ZY		 5250 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5251
888d256e
JK		 5252 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5253 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5254 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5255 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 5256 kvm_x86_ops = NULL;
56c6d28a
ZX		 5257 kvm_mmu_module_exit();
5258}
f8c16bba 5259
8776e519
HB		 5260int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5261{
5262 ++vcpu->stat.halt_exits;
5263 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5264 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5265 return 1;
5266 } else {
5267 vcpu->run->exit_reason = KVM_EXIT_HLT;
5268 return 0;
5269 }
5270}
5271EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5272
55cd8e5a
GN		 5273int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5274{
5275 u64 param, ingpa, outgpa, ret;
5276 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5277 bool fast, longmode;
5278 int cs_db, cs_l;
5279
5280 /*
5281 * hypercall generates UD from non zero cpl and real mode
5282 * per HYPER-V spec
5283 */
3eeb3288 5284 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5285 kvm_queue_exception(vcpu, UD_VECTOR);
5286 return 0;
5287 }
5288
5289 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5290 longmode = is_long_mode(vcpu) && cs_l == 1;
5291
5292 if (!longmode) {
ccd46936
GN		 5293 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5294 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5295 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5296 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5297 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5298 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5299 }
5300#ifdef CONFIG_X86_64
5301 else {
5302 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5303 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5304 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5305 }
5306#endif
5307
5308 code = param & 0xffff;
5309 fast = (param >> 16) & 0x1;
5310 rep_cnt = (param >> 32) & 0xfff;
5311 rep_idx = (param >> 48) & 0xfff;
5312
5313 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5314
c25bc163
GN		 5315 switch (code) {
5316 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5317 kvm_vcpu_on_spin(vcpu);
5318 break;
5319 default:
5320 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5321 break;
5322 }
55cd8e5a
GN		 5323
5324 ret = res | (((u64)rep_done & 0xfff) << 32);
5325 if (longmode) {
5326 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5327 } else {
5328 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5329 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5330 }
5331
5332 return 1;
5333}
5334
8776e519
HB		 5335int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5336{
5337 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5338 int r = 1;
8776e519 5339
55cd8e5a
GN		 5340 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5341 return kvm_hv_hypercall(vcpu);
5342
5fdbf976
MT		 5343 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5344 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5345 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5346 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5347 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5348
229456fc 5349 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5350
8776e519
HB		 5351 if (!is_long_mode(vcpu)) {
5352 nr &= 0xFFFFFFFF;
5353 a0 &= 0xFFFFFFFF;
5354 a1 &= 0xFFFFFFFF;
5355 a2 &= 0xFFFFFFFF;
5356 a3 &= 0xFFFFFFFF;
5357 }
5358
07708c4a
JK		 5359 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5360 ret = -KVM_EPERM;
5361 goto out;
5362 }
5363
8776e519 5364 switch (nr) {
b93463aa
AK		 5365 case KVM_HC_VAPIC_POLL_IRQ:
5366 ret = 0;
5367 break;
8776e519
HB		 5368 default:
5369 ret = -KVM_ENOSYS;
5370 break;
5371 }
07708c4a 5372out:
5fdbf976 5373 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5374 ++vcpu->stat.hypercalls;
2f333bcb 5375 return r;
8776e519
HB		 5376}
5377EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5378
d6aa1000 5379int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5380{
d6aa1000 5381 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5382 char instruction[3];
5fdbf976 5383 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5384
8776e519
HB		 5385 /*
5386 * Blow out the MMU to ensure that no other VCPU has an active mapping
5387 * to ensure that the updated hypercall appears atomically across all
5388 * VCPUs.
5389 */
5390 kvm_mmu_zap_all(vcpu->kvm);
5391
8776e519 5392 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5393
9d74191a 5394 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5395}
5396
07716717
DK		 5397static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
5398{
ad312c7c
ZX		 5399 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
5400 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 5401
5402 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
5403 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 5404 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 5405 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 5406 if (ej->function == e->function) {
5407 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
5408 return j;
5409 }
5410 }
5411 return 0; /* silence gcc, even though control never reaches here */
5412}
5413
5414/* find an entry with matching function, matching index (if needed), and that
5415 * should be read next (if it's stateful) */
5416static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
5417 u32 function, u32 index)
5418{
5419 if (e->function != function)
5420 return 0;
5421 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
5422 return 0;
5423 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 5424 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 5425 return 0;
5426 return 1;
5427}
5428
d8017474
AG		 5429struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
5430 u32 function, u32 index)
8776e519
HB		 5431{
5432 int i;
d8017474 5433 struct kvm_cpuid_entry2 *best = NULL;
8776e519 5434
ad312c7c 5435 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 5436 struct kvm_cpuid_entry2 *e;
5437
ad312c7c 5438 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 5439 if (is_matching_cpuid_entry(e, function, index)) {
5440 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
5441 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 5442 best = e;
5443 break;
5444 }
8776e519 5445 }
d8017474
AG		 5446 return best;
5447}
0e851880 5448EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 5449
82725b20
DE		 5450int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
5451{
5452 struct kvm_cpuid_entry2 *best;
5453
f7a71197
AK		 5454 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
5455 if (!best || best->eax < 0x80000008)
5456 goto not_found;
82725b20
DE		 5457 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
5458 if (best)
5459 return best->eax & 0xff;
f7a71197 5460not_found:
82725b20
DE		 5461 return 36;
5462}
5463
bd22f5cf
AP		 5464/*
5465 * If no match is found, check whether we exceed the vCPU's limit
5466 * and return the content of the highest valid _standard_ leaf instead.
5467 * This is to satisfy the CPUID specification.
5468 */
5469static struct kvm_cpuid_entry2* check_cpuid_limit(struct kvm_vcpu *vcpu,
5470 u32 function, u32 index)
5471{
5472 struct kvm_cpuid_entry2 *maxlevel;
5473
5474 maxlevel = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0);
5475 if (!maxlevel || maxlevel->eax >= function)
5476 return NULL;
5477 if (function & 0x80000000) {
5478 maxlevel = kvm_find_cpuid_entry(vcpu, 0, 0);
5479 if (!maxlevel)
5480 return NULL;
5481 }
5482 return kvm_find_cpuid_entry(vcpu, maxlevel->eax, index);
5483}
5484
d8017474
AG		 5485void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
5486{
5487 u32 function, index;
5488 struct kvm_cpuid_entry2 *best;
5489
5490 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
5491 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5492 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
5493 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
5494 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
5495 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
5496 best = kvm_find_cpuid_entry(vcpu, function, index);
bd22f5cf
AP		 5497
5498 if (!best)
5499 best = check_cpuid_limit(vcpu, function, index);
5500
8776e519 5501 if (best) {
5fdbf976
MT		 5502 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
5503 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
5504 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
5505 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 5506 }
8776e519 5507 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 5508 trace_kvm_cpuid(function,
5509 kvm_register_read(vcpu, VCPU_REGS_RAX),
5510 kvm_register_read(vcpu, VCPU_REGS_RBX),
5511 kvm_register_read(vcpu, VCPU_REGS_RCX),
5512 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 5513}
5514EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 5515
b6c7a5dc
HB		 5516/*
5517 * Check if userspace requested an interrupt window, and that the
5518 * interrupt window is open.
5519 *
5520 * No need to exit to userspace if we already have an interrupt queued.
5521 */
851ba692 5522static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5523{
8061823a 5524 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5525 vcpu->run->request_interrupt_window &&
5df56646 5526 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5527}
5528
851ba692 5529static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5530{
851ba692
AK		 5531 struct kvm_run *kvm_run = vcpu->run;
5532
91586a3b 5533 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5534 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5535 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5536 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5537 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5538 else
b6c7a5dc 5539 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5540 kvm_arch_interrupt_allowed(vcpu) &&
5541 !kvm_cpu_has_interrupt(vcpu) &&
5542 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5543}
5544
b93463aa
AK		 5545static void vapic_enter(struct kvm_vcpu *vcpu)
5546{
5547 struct kvm_lapic *apic = vcpu->arch.apic;
5548 struct page *page;
5549
5550 if (!apic || !apic->vapic_addr)
5551 return;
5552
5553 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 5554
5555 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 5556}
5557
5558static void vapic_exit(struct kvm_vcpu *vcpu)
5559{
5560 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5561 int idx;
b93463aa
AK		 5562
5563 if (!apic || !apic->vapic_addr)
5564 return;
5565
f656ce01 5566 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5567 kvm_release_page_dirty(apic->vapic_page);
5568 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5569 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5570}
5571
95ba8273
GN		 5572static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5573{
5574 int max_irr, tpr;
5575
5576 if (!kvm_x86_ops->update_cr8_intercept)
5577 return;
5578
88c808fd
AK		 5579 if (!vcpu->arch.apic)
5580 return;
5581
8db3baa2
GN		 5582 if (!vcpu->arch.apic->vapic_addr)
5583 max_irr = kvm_lapic_find_highest_irr(vcpu);
5584 else
5585 max_irr = -1;
95ba8273
GN		 5586
5587 if (max_irr != -1)
5588 max_irr >>= 4;
5589
5590 tpr = kvm_lapic_get_cr8(vcpu);
5591
5592 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5593}
5594
851ba692 5595static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5596{
5597 /* try to reinject previous events if any */
b59bb7bd 5598 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5599 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5600 vcpu->arch.exception.has_error_code,
5601 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5602 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5603 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5604 vcpu->arch.exception.error_code,
5605 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5606 return;
5607 }
5608
95ba8273
GN		 5609 if (vcpu->arch.nmi_injected) {
5610 kvm_x86_ops->set_nmi(vcpu);
5611 return;
5612 }
5613
5614 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5615 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5616 return;
5617 }
5618
5619 /* try to inject new event if pending */
5620 if (vcpu->arch.nmi_pending) {
5621 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5622 --vcpu->arch.nmi_pending;
95ba8273
GN		 5623 vcpu->arch.nmi_injected = true;
5624 kvm_x86_ops->set_nmi(vcpu);
5625 }
5626 } else if (kvm_cpu_has_interrupt(vcpu)) {
5627 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5628 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5629 false);
5630 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5631 }
5632 }
5633}
5634
2acf923e
DC		 5635static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5636{
5637 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5638 !vcpu->guest_xcr0_loaded) {
5639 /* kvm_set_xcr() also depends on this */
5640 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5641 vcpu->guest_xcr0_loaded = 1;
5642 }
5643}
5644
5645static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5646{
5647 if (vcpu->guest_xcr0_loaded) {
5648 if (vcpu->arch.xcr0 != host_xcr0)
5649 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5650 vcpu->guest_xcr0_loaded = 0;
5651 }
5652}
5653
7460fb4a
AK		 5654static void process_nmi(struct kvm_vcpu *vcpu)
5655{
5656 unsigned limit = 2;
5657
5658 /*
5659 * x86 is limited to one NMI running, and one NMI pending after it.
5660 * If an NMI is already in progress, limit further NMIs to just one.
5661 * Otherwise, allow two (and we'll inject the first one immediately).
5662 */
5663 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5664 limit = 1;
5665
5666 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5667 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5668 kvm_make_request(KVM_REQ_EVENT, vcpu);
5669}
5670
851ba692 5671static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5672{
5673 int r;
6a8b1d13 5674 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5675 vcpu->run->request_interrupt_window;
d6185f20 5676 bool req_immediate_exit = 0;
b6c7a5dc 5677
3e007509 5678 if (vcpu->requests) {
a8eeb04a 5679 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5680 kvm_mmu_unload(vcpu);
a8eeb04a 5681 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5682 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5683 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5684 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5685 if (unlikely(r))
5686 goto out;
5687 }
a8eeb04a 5688 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5689 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5690 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5691 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5692 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5693 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5694 r = 0;
5695 goto out;
5696 }
a8eeb04a 5697 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5698 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5699 r = 0;
5700 goto out;
5701 }
a8eeb04a 5702 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5703 vcpu->fpu_active = 0;
5704 kvm_x86_ops->fpu_deactivate(vcpu);
5705 }
af585b92
GN		 5706 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5707 /* Page is swapped out. Do synthetic halt */
5708 vcpu->arch.apf.halted = true;
5709 r = 1;
5710 goto out;
5711 }
c9aaa895
GC		 5712 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5713 record_steal_time(vcpu);
7460fb4a
AK		 5714 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5715 process_nmi(vcpu);
d6185f20
NHE		 5716 req_immediate_exit =
5717 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
2f52d58c 5718 }
b93463aa 5719
3e007509
AK		 5720 r = kvm_mmu_reload(vcpu);
5721 if (unlikely(r))
5722 goto out;
5723
b463a6f7
AK		 5724 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5725 inject_pending_event(vcpu);
5726
5727 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5728 if (vcpu->arch.nmi_pending)
b463a6f7
AK		 5729 kvm_x86_ops->enable_nmi_window(vcpu);
5730 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5731 kvm_x86_ops->enable_irq_window(vcpu);
5732
5733 if (kvm_lapic_enabled(vcpu)) {
5734 update_cr8_intercept(vcpu);
5735 kvm_lapic_sync_to_vapic(vcpu);
5736 }
5737 }
5738
b6c7a5dc
HB		 5739 preempt_disable();
5740
5741 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5742 if (vcpu->fpu_active)
5743 kvm_load_guest_fpu(vcpu);
2acf923e 5744 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5745
6b7e2d09
XG		 5746 vcpu->mode = IN_GUEST_MODE;
5747
5748 /* We should set ->mode before check ->requests,
5749 * see the comment in make_all_cpus_request.
5750 */
5751 smp_mb();
b6c7a5dc 5752
d94e1dc9 5753 local_irq_disable();
32f88400 5754
6b7e2d09 5755 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5756 || need_resched() || signal_pending(current)) {
6b7e2d09 5757 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5758 smp_wmb();
6c142801
AK		 5759 local_irq_enable();
5760 preempt_enable();
b463a6f7 5761 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5762 r = 1;
5763 goto out;
5764 }
5765
f656ce01 5766 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5767
d6185f20
NHE		 5768 if (req_immediate_exit)
5769 smp_send_reschedule(vcpu->cpu);
5770
b6c7a5dc
HB		 5771 kvm_guest_enter();
5772
42dbaa5a 5773 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5774 set_debugreg(0, 7);
5775 set_debugreg(vcpu->arch.eff_db[0], 0);
5776 set_debugreg(vcpu->arch.eff_db[1], 1);
5777 set_debugreg(vcpu->arch.eff_db[2], 2);
5778 set_debugreg(vcpu->arch.eff_db[3], 3);
5779 }
b6c7a5dc 5780
229456fc 5781 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5782 kvm_x86_ops->run(vcpu);
b6c7a5dc 5783
24f1e32c
FW		 5784 /*
5785 * If the guest has used debug registers, at least dr7
5786 * will be disabled while returning to the host.
5787 * If we don't have active breakpoints in the host, we don't
5788 * care about the messed up debug address registers. But if
5789 * we have some of them active, restore the old state.
5790 */
59d8eb53 5791 if (hw_breakpoint_active())
24f1e32c 5792 hw_breakpoint_restore();
42dbaa5a 5793
d5c1785d 5794 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
1d5f066e 5795
6b7e2d09 5796 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5797 smp_wmb();
b6c7a5dc
HB		 5798 local_irq_enable();
5799
5800 ++vcpu->stat.exits;
5801
5802 /*
5803 * We must have an instruction between local_irq_enable() and
5804 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5805 * the interrupt shadow. The stat.exits increment will do nicely.
5806 * But we need to prevent reordering, hence this barrier():
5807 */
5808 barrier();
5809
5810 kvm_guest_exit();
5811
5812 preempt_enable();
5813
f656ce01 5814 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5815
b6c7a5dc
HB		 5816 /*
5817 * Profile KVM exit RIPs:
5818 */
5819 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5820 unsigned long rip = kvm_rip_read(vcpu);
5821 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5822 }
5823
298101da 5824
b93463aa
AK		 5825 kvm_lapic_sync_from_vapic(vcpu);
5826
851ba692 5827 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5828out:
5829 return r;
5830}
b6c7a5dc 5831
09cec754 5832
851ba692 5833static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5834{
5835 int r;
f656ce01 5836 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5837
5838 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5839 pr_debug("vcpu %d received sipi with vector # %x\n",
5840 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5841 kvm_lapic_reset(vcpu);
5f179287 5842 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5843 if (r)
5844 return r;
5845 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5846 }
5847
f656ce01 5848 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5849 vapic_enter(vcpu);
5850
5851 r = 1;
5852 while (r > 0) {
af585b92
GN		 5853 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5854 !vcpu->arch.apf.halted)
851ba692 5855 r = vcpu_enter_guest(vcpu);
d7690175 5856 else {
f656ce01 5857 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5858 kvm_vcpu_block(vcpu);
f656ce01 5859 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5860 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5861 {
5862 switch(vcpu->arch.mp_state) {
5863 case KVM_MP_STATE_HALTED:
d7690175 5864 vcpu->arch.mp_state =
09cec754
GN		 5865 KVM_MP_STATE_RUNNABLE;
5866 case KVM_MP_STATE_RUNNABLE:
af585b92 5867 vcpu->arch.apf.halted = false;
09cec754
GN		 5868 break;
5869 case KVM_MP_STATE_SIPI_RECEIVED:
5870 default:
5871 r = -EINTR;
5872 break;
5873 }
5874 }
d7690175
MT		 5875 }
5876
09cec754
GN		 5877 if (r <= 0)
5878 break;
5879
5880 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5881 if (kvm_cpu_has_pending_timer(vcpu))
5882 kvm_inject_pending_timer_irqs(vcpu);
5883
851ba692 5884 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5885 r = -EINTR;
851ba692 5886 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5887 ++vcpu->stat.request_irq_exits;
5888 }
af585b92
GN		 5889
5890 kvm_check_async_pf_completion(vcpu);
5891
09cec754
GN		 5892 if (signal_pending(current)) {
5893 r = -EINTR;
851ba692 5894 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5895 ++vcpu->stat.signal_exits;
5896 }
5897 if (need_resched()) {
f656ce01 5898 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5899 kvm_resched(vcpu);
f656ce01 5900 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5901 }
b6c7a5dc
HB		 5902 }
5903
f656ce01 5904 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5905
b93463aa
AK		 5906 vapic_exit(vcpu);
5907
b6c7a5dc
HB		 5908 return r;
5909}
5910
5287f194
AK		 5911static int complete_mmio(struct kvm_vcpu *vcpu)
5912{
5913 struct kvm_run *run = vcpu->run;
5914 int r;
5915
5916 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5917 return 1;
5918
5919 if (vcpu->mmio_needed) {
5287f194 5920 vcpu->mmio_needed = 0;
cef4dea0 5921 if (!vcpu->mmio_is_write)
0004c7c2
GN		 5922 memcpy(vcpu->mmio_data + vcpu->mmio_index,
5923 run->mmio.data, 8);
cef4dea0
AK		 5924 vcpu->mmio_index += 8;
5925 if (vcpu->mmio_index < vcpu->mmio_size) {
5926 run->exit_reason = KVM_EXIT_MMIO;
5927 run->mmio.phys_addr = vcpu->mmio_phys_addr + vcpu->mmio_index;
5928 memcpy(run->mmio.data, vcpu->mmio_data + vcpu->mmio_index, 8);
5929 run->mmio.len = min(vcpu->mmio_size - vcpu->mmio_index, 8);
5930 run->mmio.is_write = vcpu->mmio_is_write;
5931 vcpu->mmio_needed = 1;
5932 return 0;
5933 }
5934 if (vcpu->mmio_is_write)
5935 return 1;
5936 vcpu->mmio_read_completed = 1;
5287f194
AK		 5937 }
5938 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5939 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5940 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5941 if (r != EMULATE_DONE)
5942 return 0;
5943 return 1;
5944}
5945
b6c7a5dc
HB		 5946int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5947{
5948 int r;
5949 sigset_t sigsaved;
5950
e5c30142
AK		 5951 if (!tsk_used_math(current) && init_fpu(current))
5952 return -ENOMEM;
5953
ac9f6dc0
AK		 5954 if (vcpu->sigset_active)
5955 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5956
a4535290 5957 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5958 kvm_vcpu_block(vcpu);
d7690175 5959 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5960 r = -EAGAIN;
5961 goto out;
b6c7a5dc
HB		 5962 }
5963
b6c7a5dc 5964 /* re-sync apic's tpr */
eea1cff9
AP		 5965 if (!irqchip_in_kernel(vcpu->kvm)) {
5966 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5967 r = -EINVAL;
5968 goto out;
5969 }
5970 }
b6c7a5dc 5971
5287f194
AK		 5972 r = complete_mmio(vcpu);
5973 if (r <= 0)
5974 goto out;
5975
5fdbf976
MT		 5976 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5977 kvm_register_write(vcpu, VCPU_REGS_RAX,
5978 kvm_run->hypercall.ret);
b6c7a5dc 5979
851ba692 5980 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5981
5982out:
f1d86e46 5983 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5984 if (vcpu->sigset_active)
5985 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5986
b6c7a5dc
HB		 5987 return r;
5988}
5989
5990int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5991{
7ae441ea
GN		 5992 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5993 /*
5994 * We are here if userspace calls get_regs() in the middle of
5995 * instruction emulation. Registers state needs to be copied
5996 * back from emulation context to vcpu. Usrapace shouldn't do
5997 * that usually, but some bad designed PV devices (vmware
5998 * backdoor interface) need this to work
5999 */
9dac77fa
AK		 6000 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6001 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea
GN		 6002 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6003 }
5fdbf976
MT		 6004 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6005 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6006 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6007 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6008 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6009 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6010 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6011 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6012#ifdef CONFIG_X86_64
5fdbf976
MT		 6013 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6014 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6015 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6016 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6017 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6018 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6019 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6020 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6021#endif
6022
5fdbf976 6023 regs->rip = kvm_rip_read(vcpu);
91586a3b 6024 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6025
b6c7a5dc
HB		 6026 return 0;
6027}
6028
6029int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6030{
7ae441ea
GN		 6031 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6032 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6033
5fdbf976
MT		 6034 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6035 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6036 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6037 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6038 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6039 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6040 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6041 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6042#ifdef CONFIG_X86_64
5fdbf976
MT		 6043 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6044 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6045 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6046 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6047 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6048 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6049 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6050 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6051#endif
6052
5fdbf976 6053 kvm_rip_write(vcpu, regs->rip);
91586a3b 6054 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6055
b4f14abd
JK		 6056 vcpu->arch.exception.pending = false;
6057
3842d135
AK		 6058 kvm_make_request(KVM_REQ_EVENT, vcpu);
6059
b6c7a5dc
HB		 6060 return 0;
6061}
6062
b6c7a5dc
HB		 6063void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6064{
6065 struct kvm_segment cs;
6066
3e6e0aab 6067 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6068 *db = cs.db;
6069 *l = cs.l;
6070}
6071EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6072
6073int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6074 struct kvm_sregs *sregs)
6075{
89a27f4d 6076 struct desc_ptr dt;
b6c7a5dc 6077
3e6e0aab
GT		 6078 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6079 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6080 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6081 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6082 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6083 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6084
3e6e0aab
GT		 6085 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6086 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6087
6088 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6089 sregs->idt.limit = dt.size;
6090 sregs->idt.base = dt.address;
b6c7a5dc 6091 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6092 sregs->gdt.limit = dt.size;
6093 sregs->gdt.base = dt.address;
b6c7a5dc 6094
4d4ec087 6095 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6096 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6097 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6098 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6099 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6100 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6101 sregs->apic_base = kvm_get_apic_base(vcpu);
6102
923c61bb 6103 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6104
36752c9b 6105 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6106 set_bit(vcpu->arch.interrupt.nr,
6107 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6108
b6c7a5dc
HB		 6109 return 0;
6110}
6111
62d9f0db
MT		 6112int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6113 struct kvm_mp_state *mp_state)
6114{
62d9f0db 6115 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 6116 return 0;
6117}
6118
6119int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6120 struct kvm_mp_state *mp_state)
6121{
62d9f0db 6122 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6123 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6124 return 0;
6125}
6126
e269fb21
JK		 6127int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
6128 bool has_error_code, u32 error_code)
b6c7a5dc 6129{
9d74191a 6130 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6131 int ret;
e01c2426 6132
8ec4722d 6133 init_emulate_ctxt(vcpu);
c697518a 6134
9d74191a
TY		 6135 ret = emulator_task_switch(ctxt, tss_selector, reason,
6136 has_error_code, error_code);
c697518a 6137
c697518a 6138 if (ret)
19d04437 6139 return EMULATE_FAIL;
37817f29 6140
9dac77fa 6141 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 6142 kvm_rip_write(vcpu, ctxt->eip);
6143 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6144 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6145 return EMULATE_DONE;
37817f29
IE		 6146}
6147EXPORT_SYMBOL_GPL(kvm_task_switch);
6148
b6c7a5dc
HB		 6149int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6150 struct kvm_sregs *sregs)
6151{
6152 int mmu_reset_needed = 0;
63f42e02 6153 int pending_vec, max_bits, idx;
89a27f4d 6154 struct desc_ptr dt;
b6c7a5dc 6155
89a27f4d
GN		 6156 dt.size = sregs->idt.limit;
6157 dt.address = sregs->idt.base;
b6c7a5dc 6158 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6159 dt.size = sregs->gdt.limit;
6160 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6161 kvm_x86_ops->set_gdt(vcpu, &dt);
6162
ad312c7c 6163 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6164 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6165 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6166 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6167
2d3ad1f4 6168 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6169
f6801dff 6170 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6171 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 6172 kvm_set_apic_base(vcpu, sregs->apic_base);
6173
4d4ec087 6174 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6175 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6176 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6177
fc78f519 6178 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6179 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c
SY		 6180 if (sregs->cr4 & X86_CR4_OSXSAVE)
6181 update_cpuid(vcpu);
63f42e02
XG		 6182
6183 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6184 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6185 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6186 mmu_reset_needed = 1;
6187 }
63f42e02 6188 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6189
6190 if (mmu_reset_needed)
6191 kvm_mmu_reset_context(vcpu);
6192
923c61bb
GN		 6193 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
6194 pending_vec = find_first_bit(
6195 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6196 if (pending_vec < max_bits) {
66fd3f7f 6197 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6198 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6199 }
6200
3e6e0aab
GT		 6201 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6202 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6203 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6204 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6205 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6206 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6207
3e6e0aab
GT		 6208 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6209 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6210
5f0269f5
ME		 6211 update_cr8_intercept(vcpu);
6212
9c3e4aab 6213 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6214 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6215 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6216 !is_protmode(vcpu))
9c3e4aab
MT		 6217 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6218
3842d135
AK		 6219 kvm_make_request(KVM_REQ_EVENT, vcpu);
6220
b6c7a5dc
HB		 6221 return 0;
6222}
6223
d0bfb940
JK		 6224int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6225 struct kvm_guest_debug *dbg)
b6c7a5dc 6226{
355be0b9 6227 unsigned long rflags;
ae675ef0 6228 int i, r;
b6c7a5dc 6229
4f926bf2
JK		 6230 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6231 r = -EBUSY;
6232 if (vcpu->arch.exception.pending)
2122ff5e 6233 goto out;
4f926bf2
JK		 6234 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6235 kvm_queue_exception(vcpu, DB_VECTOR);
6236 else
6237 kvm_queue_exception(vcpu, BP_VECTOR);
6238 }
6239
91586a3b
JK		 6240 /*
6241 * Read rflags as long as potentially injected trace flags are still
6242 * filtered out.
6243 */
6244 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6245
6246 vcpu->guest_debug = dbg->control;
6247 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6248 vcpu->guest_debug = 0;
6249
6250 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6251 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6252 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6253 vcpu->arch.switch_db_regs =
6254 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
6255 } else {
6256 for (i = 0; i < KVM_NR_DB_REGS; i++)
6257 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6258 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
6259 }
6260
f92653ee
JK		 6261 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6262 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6263 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6264
91586a3b
JK		 6265 /*
6266 * Trigger an rflags update that will inject or remove the trace
6267 * flags.
6268 */
6269 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6270
355be0b9 6271 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 6272
4f926bf2 6273 r = 0;
d0bfb940 6274
2122ff5e 6275out:
b6c7a5dc
HB		 6276
6277 return r;
6278}
6279
8b006791
ZX		 6280/*
6281 * Translate a guest virtual address to a guest physical address.
6282 */
6283int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6284 struct kvm_translation *tr)
6285{
6286 unsigned long vaddr = tr->linear_address;
6287 gpa_t gpa;
f656ce01 6288 int idx;
8b006791 6289
f656ce01 6290 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6291 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6292 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6293 tr->physical_address = gpa;
6294 tr->valid = gpa != UNMAPPED_GVA;
6295 tr->writeable = 1;
6296 tr->usermode = 0;
8b006791
ZX		 6297
6298 return 0;
6299}
6300
d0752060
HB		 6301int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6302{
98918833
SY		 6303 struct i387_fxsave_struct *fxsave =
6304 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6305
d0752060
HB		 6306 memcpy(fpu->fpr, fxsave->st_space, 128);
6307 fpu->fcw = fxsave->cwd;
6308 fpu->fsw = fxsave->swd;
6309 fpu->ftwx = fxsave->twd;
6310 fpu->last_opcode = fxsave->fop;
6311 fpu->last_ip = fxsave->rip;
6312 fpu->last_dp = fxsave->rdp;
6313 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6314
d0752060
HB		 6315 return 0;
6316}
6317
6318int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6319{
98918833
SY		 6320 struct i387_fxsave_struct *fxsave =
6321 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6322
d0752060
HB		 6323 memcpy(fxsave->st_space, fpu->fpr, 128);
6324 fxsave->cwd = fpu->fcw;
6325 fxsave->swd = fpu->fsw;
6326 fxsave->twd = fpu->ftwx;
6327 fxsave->fop = fpu->last_opcode;
6328 fxsave->rip = fpu->last_ip;
6329 fxsave->rdp = fpu->last_dp;
6330 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6331
d0752060
HB		 6332 return 0;
6333}
6334
10ab25cd 6335int fx_init(struct kvm_vcpu *vcpu)
d0752060 6336{
10ab25cd
JK		 6337 int err;
6338
6339 err = fpu_alloc(&vcpu->arch.guest_fpu);
6340 if (err)
6341 return err;
6342
98918833 6343 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6344
2acf923e
DC		 6345 /*
6346 * Ensure guest xcr0 is valid for loading
6347 */
6348 vcpu->arch.xcr0 = XSTATE_FP;
6349
ad312c7c 6350 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6351
6352 return 0;
d0752060
HB		 6353}
6354EXPORT_SYMBOL_GPL(fx_init);
6355
98918833
SY		 6356static void fx_free(struct kvm_vcpu *vcpu)
6357{
6358 fpu_free(&vcpu->arch.guest_fpu);
6359}
6360
d0752060
HB		 6361void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6362{
2608d7a1 6363 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6364 return;
6365
2acf923e
DC		 6366 /*
6367 * Restore all possible states in the guest,
6368 * and assume host would use all available bits.
6369 * Guest xcr0 would be loaded later.
6370 */
6371 kvm_put_guest_xcr0(vcpu);
d0752060 6372 vcpu->guest_fpu_loaded = 1;
7cf30855 6373 unlazy_fpu(current);
98918833 6374 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6375 trace_kvm_fpu(1);
d0752060 6376}
d0752060
HB		 6377
6378void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6379{
2acf923e
DC		 6380 kvm_put_guest_xcr0(vcpu);
6381
d0752060
HB		 6382 if (!vcpu->guest_fpu_loaded)
6383 return;
6384
6385 vcpu->guest_fpu_loaded = 0;
98918833 6386 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 6387 ++vcpu->stat.fpu_reload;
a8eeb04a 6388 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6389 trace_kvm_fpu(0);
d0752060 6390}
e9b11c17
ZX		 6391
6392void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6393{
12f9a48f 6394 kvmclock_reset(vcpu);
7f1ea208 6395
f5f48ee1 6396 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6397 fx_free(vcpu);
e9b11c17
ZX		 6398 kvm_x86_ops->vcpu_free(vcpu);
6399}
6400
6401struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6402 unsigned int id)
6403{
6755bae8
ZA		 6404 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6405 printk_once(KERN_WARNING
6406 "kvm: SMP vm created on host with unstable TSC; "
6407 "guest TSC will not be reliable\n");
26e5215f
AK		 6408 return kvm_x86_ops->vcpu_create(kvm, id);
6409}
e9b11c17 6410
26e5215f
AK		 6411int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6412{
6413 int r;
e9b11c17 6414
0bed3b56 6415 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 6416 vcpu_load(vcpu);
6417 r = kvm_arch_vcpu_reset(vcpu);
6418 if (r == 0)
6419 r = kvm_mmu_setup(vcpu);
6420 vcpu_put(vcpu);
e9b11c17 6421
26e5215f 6422 return r;
e9b11c17
ZX		 6423}
6424
d40ccc62 6425void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6426{
344d9588
GN		 6427 vcpu->arch.apf.msr_val = 0;
6428
e9b11c17
ZX		 6429 vcpu_load(vcpu);
6430 kvm_mmu_unload(vcpu);
6431 vcpu_put(vcpu);
6432
98918833 6433 fx_free(vcpu);
e9b11c17
ZX		 6434 kvm_x86_ops->vcpu_free(vcpu);
6435}
6436
6437int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
6438{
7460fb4a
AK		 6439 atomic_set(&vcpu->arch.nmi_queued, 0);
6440 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6441 vcpu->arch.nmi_injected = false;
6442
42dbaa5a
JK		 6443 vcpu->arch.switch_db_regs = 0;
6444 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6445 vcpu->arch.dr6 = DR6_FIXED_1;
6446 vcpu->arch.dr7 = DR7_FIXED_1;
6447
3842d135 6448 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6449 vcpu->arch.apf.msr_val = 0;
c9aaa895 6450 vcpu->arch.st.msr_val = 0;
3842d135 6451
12f9a48f
GC		 6452 kvmclock_reset(vcpu);
6453
af585b92
GN		 6454 kvm_clear_async_pf_completion_queue(vcpu);
6455 kvm_async_pf_hash_reset(vcpu);
6456 vcpu->arch.apf.halted = false;
3842d135 6457
e9b11c17
ZX		 6458 return kvm_x86_ops->vcpu_reset(vcpu);
6459}
6460
10474ae8 6461int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6462{
ca84d1a2
ZA		 6463 struct kvm *kvm;
6464 struct kvm_vcpu *vcpu;
6465 int i;
18863bdd
AK		 6466
6467 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 6468 list_for_each_entry(kvm, &vm_list, vm_list)
6469 kvm_for_each_vcpu(i, vcpu, kvm)
6470 if (vcpu->cpu == smp_processor_id())
c285545f 6471 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10474ae8 6472 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 6473}
6474
6475void kvm_arch_hardware_disable(void *garbage)
6476{
6477 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6478 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6479}
6480
6481int kvm_arch_hardware_setup(void)
6482{
6483 return kvm_x86_ops->hardware_setup();
6484}
6485
6486void kvm_arch_hardware_unsetup(void)
6487{
6488 kvm_x86_ops->hardware_unsetup();
6489}
6490
6491void kvm_arch_check_processor_compat(void *rtn)
6492{
6493 kvm_x86_ops->check_processor_compatibility(rtn);
6494}
6495
6496int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6497{
6498 struct page *page;
6499 struct kvm *kvm;
6500 int r;
6501
6502 BUG_ON(vcpu->kvm == NULL);
6503 kvm = vcpu->kvm;
6504
9aabc88f 6505 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
14dfe855 6506 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
ad312c7c 6507 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c30a358d 6508 vcpu->arch.mmu.translate_gpa = translate_gpa;
02f59dc9 6509 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
c5af89b6 6510 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6511 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6512 else
a4535290 6513 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6514
6515 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6516 if (!page) {
6517 r = -ENOMEM;
6518 goto fail;
6519 }
ad312c7c 6520 vcpu->arch.pio_data = page_address(page);
e9b11c17 6521
1e993611 6522 kvm_init_tsc_catchup(vcpu, max_tsc_khz);
c285545f 6523
e9b11c17
ZX		 6524 r = kvm_mmu_create(vcpu);
6525 if (r < 0)
6526 goto fail_free_pio_data;
6527
6528 if (irqchip_in_kernel(kvm)) {
6529 r = kvm_create_lapic(vcpu);
6530 if (r < 0)
6531 goto fail_mmu_destroy;
6532 }
6533
890ca9ae
HY		 6534 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6535 GFP_KERNEL);
6536 if (!vcpu->arch.mce_banks) {
6537 r = -ENOMEM;
443c39bc 6538 goto fail_free_lapic;
890ca9ae
HY		 6539 }
6540 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6541
f5f48ee1
SY		 6542 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6543 goto fail_free_mce_banks;
6544
af585b92
GN		 6545 kvm_async_pf_hash_reset(vcpu);
6546
e9b11c17 6547 return 0;
f5f48ee1
SY		 6548fail_free_mce_banks:
6549 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6550fail_free_lapic:
6551 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6552fail_mmu_destroy:
6553 kvm_mmu_destroy(vcpu);
6554fail_free_pio_data:
ad312c7c 6555 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6556fail:
6557 return r;
6558}
6559
6560void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6561{
f656ce01
MT		 6562 int idx;
6563
36cb93fd 6564 kfree(vcpu->arch.mce_banks);
e9b11c17 6565 kvm_free_lapic(vcpu);
f656ce01 6566 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6567 kvm_mmu_destroy(vcpu);
f656ce01 6568 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6569 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 6570}
d19a9cd2 6571
d89f5eff 6572int kvm_arch_init_vm(struct kvm *kvm)
d19a9cd2 6573{
f05e70ac 6574 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6575 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6576
5550af4d
SY		 6577 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6578 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6579
038f8c11 6580 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 6581
d89f5eff 6582 return 0;
d19a9cd2
ZX		 6583}
6584
6585static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6586{
6587 vcpu_load(vcpu);
6588 kvm_mmu_unload(vcpu);
6589 vcpu_put(vcpu);
6590}
6591
6592static void kvm_free_vcpus(struct kvm *kvm)
6593{
6594 unsigned int i;
988a2cae 6595 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6596
6597 /*
6598 * Unpin any mmu pages first.
6599 */
af585b92
GN		 6600 kvm_for_each_vcpu(i, vcpu, kvm) {
6601 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6602 kvm_unload_vcpu_mmu(vcpu);
af585b92 6603 }
988a2cae
GN		 6604 kvm_for_each_vcpu(i, vcpu, kvm)
6605 kvm_arch_vcpu_free(vcpu);
6606
6607 mutex_lock(&kvm->lock);
6608 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6609 kvm->vcpus[i] = NULL;
d19a9cd2 6610
988a2cae
GN		 6611 atomic_set(&kvm->online_vcpus, 0);
6612 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6613}
6614
ad8ba2cd
SY		 6615void kvm_arch_sync_events(struct kvm *kvm)
6616{
ba4cef31 6617 kvm_free_all_assigned_devices(kvm);
aea924f6 6618 kvm_free_pit(kvm);
ad8ba2cd
SY		 6619}
6620
d19a9cd2
ZX		 6621void kvm_arch_destroy_vm(struct kvm *kvm)
6622{
6eb55818 6623 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6624 kfree(kvm->arch.vpic);
6625 kfree(kvm->arch.vioapic);
d19a9cd2 6626 kvm_free_vcpus(kvm);
3d45830c
AK		 6627 if (kvm->arch.apic_access_page)
6628 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6629 if (kvm->arch.ept_identity_pagetable)
6630 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2 6631}
0de10343 6632
f7784b8e
MT		 6633int kvm_arch_prepare_memory_region(struct kvm *kvm,
6634 struct kvm_memory_slot *memslot,
0de10343 6635 struct kvm_memory_slot old,
f7784b8e 6636 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6637 int user_alloc)
6638{
f7784b8e 6639 int npages = memslot->npages;
7ac77099
AK		 6640 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6641
6642 /* Prevent internal slot pages from being moved by fork()/COW. */
6643 if (memslot->id >= KVM_MEMORY_SLOTS)
6644 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6645
6646 /*To keep backward compatibility with older userspace,
6647 *x86 needs to hanlde !user_alloc case.
6648 */
6649 if (!user_alloc) {
6650 if (npages && !old.rmap) {
604b38ac
AA		 6651 unsigned long userspace_addr;
6652
72dc67a6 6653 down_write(&current->mm->mmap_sem);
604b38ac
AA		 6654 userspace_addr = do_mmap(NULL, 0,
6655 npages * PAGE_SIZE,
6656 PROT_READ | PROT_WRITE,
7ac77099 6657 map_flags,
604b38ac 6658 0);
72dc67a6 6659 up_write(&current->mm->mmap_sem);
0de10343 6660
604b38ac
AA		 6661 if (IS_ERR((void *)userspace_addr))
6662 return PTR_ERR((void *)userspace_addr);
6663
604b38ac 6664 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6665 }
6666 }
6667
f7784b8e
MT		 6668
6669 return 0;
6670}
6671
6672void kvm_arch_commit_memory_region(struct kvm *kvm,
6673 struct kvm_userspace_memory_region *mem,
6674 struct kvm_memory_slot old,
6675 int user_alloc)
6676{
6677
48c0e4e9 6678 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
f7784b8e
MT		 6679
6680 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6681 int ret;
6682
6683 down_write(&current->mm->mmap_sem);
6684 ret = do_munmap(current->mm, old.userspace_addr,
6685 old.npages * PAGE_SIZE);
6686 up_write(&current->mm->mmap_sem);
6687 if (ret < 0)
6688 printk(KERN_WARNING
6689 "kvm_vm_ioctl_set_memory_region: "
6690 "failed to munmap memory\n");
6691 }
6692
48c0e4e9
XG		 6693 if (!kvm->arch.n_requested_mmu_pages)
6694 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6695
7c8a83b7 6696 spin_lock(&kvm->mmu_lock);
48c0e4e9 6697 if (nr_mmu_pages)
0de10343 6698 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
0de10343 6699 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6700 spin_unlock(&kvm->mmu_lock);
0de10343 6701}
1d737c8a 6702
34d4cb8f
MT		 6703void kvm_arch_flush_shadow(struct kvm *kvm)
6704{
6705 kvm_mmu_zap_all(kvm);
8986ecc0 6706 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6707}
6708
1d737c8a
ZX		 6709int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6710{
af585b92
GN		 6711 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6712 !vcpu->arch.apf.halted)
6713 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100 6714 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
7460fb4a 6715 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 6716 (kvm_arch_interrupt_allowed(vcpu) &&
6717 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6718}
5736199a 6719
5736199a
ZX		 6720void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6721{
32f88400
MT		 6722 int me;
6723 int cpu = vcpu->cpu;
5736199a
ZX		 6724
6725 if (waitqueue_active(&vcpu->wq)) {
6726 wake_up_interruptible(&vcpu->wq);
6727 ++vcpu->stat.halt_wakeup;
6728 }
32f88400
MT		 6729
6730 me = get_cpu();
6731 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
6b7e2d09 6732 if (kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE)
32f88400 6733 smp_send_reschedule(cpu);
e9571ed5 6734 put_cpu();
5736199a 6735}
78646121
GN		 6736
6737int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6738{
6739 return kvm_x86_ops->interrupt_allowed(vcpu);
6740}
229456fc 6741
f92653ee
JK		 6742bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6743{
6744 unsigned long current_rip = kvm_rip_read(vcpu) +
6745 get_segment_base(vcpu, VCPU_SREG_CS);
6746
6747 return current_rip == linear_rip;
6748}
6749EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6750
94fe45da
JK		 6751unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6752{
6753 unsigned long rflags;
6754
6755 rflags = kvm_x86_ops->get_rflags(vcpu);
6756 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6757 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6758 return rflags;
6759}
6760EXPORT_SYMBOL_GPL(kvm_get_rflags);
6761
6762void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6763{
6764 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6765 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6766 rflags |= X86_EFLAGS_TF;
94fe45da 6767 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6768 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6769}
6770EXPORT_SYMBOL_GPL(kvm_set_rflags);
6771
56028d08
GN		 6772void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6773{
6774 int r;
6775
fb67e14f 6776 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6777 is_error_page(work->page))
56028d08
GN		 6778 return;
6779
6780 r = kvm_mmu_reload(vcpu);
6781 if (unlikely(r))
6782 return;
6783
fb67e14f
XG		 6784 if (!vcpu->arch.mmu.direct_map &&
6785 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6786 return;
6787
56028d08
GN		 6788 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6789}
6790
af585b92
GN		 6791static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6792{
6793 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6794}
6795
6796static inline u32 kvm_async_pf_next_probe(u32 key)
6797{
6798 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6799}
6800
6801static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6802{
6803 u32 key = kvm_async_pf_hash_fn(gfn);
6804
6805 while (vcpu->arch.apf.gfns[key] != ~0)
6806 key = kvm_async_pf_next_probe(key);
6807
6808 vcpu->arch.apf.gfns[key] = gfn;
6809}
6810
6811static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6812{
6813 int i;
6814 u32 key = kvm_async_pf_hash_fn(gfn);
6815
6816 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6817 (vcpu->arch.apf.gfns[key] != gfn &&
6818 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6819 key = kvm_async_pf_next_probe(key);
6820
6821 return key;
6822}
6823
6824bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6825{
6826 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6827}
6828
6829static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6830{
6831 u32 i, j, k;
6832
6833 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6834 while (true) {
6835 vcpu->arch.apf.gfns[i] = ~0;
6836 do {
6837 j = kvm_async_pf_next_probe(j);
6838 if (vcpu->arch.apf.gfns[j] == ~0)
6839 return;
6840 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6841 /*
6842 * k lies cyclically in ]i,j]
6843 * | i.k.j |
6844 * |....j i.k.| or |.k..j i...|
6845 */
6846 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6847 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6848 i = j;
6849 }
6850}
6851
7c90705b
GN		 6852static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6853{
6854
6855 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6856 sizeof(val));
6857}
6858
af585b92
GN		 6859void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6860 struct kvm_async_pf *work)
6861{
6389ee94
AK		 6862 struct x86_exception fault;
6863
7c90705b 6864 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6865 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6866
6867 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6868 (vcpu->arch.apf.send_user_only &&
6869 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6870 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6871 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6872 fault.vector = PF_VECTOR;
6873 fault.error_code_valid = true;
6874 fault.error_code = 0;
6875 fault.nested_page_fault = false;
6876 fault.address = work->arch.token;
6877 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6878 }
af585b92
GN		 6879}
6880
6881void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6882 struct kvm_async_pf *work)
6883{
6389ee94
AK		 6884 struct x86_exception fault;
6885
7c90705b
GN		 6886 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6887 if (is_error_page(work->page))
6888 work->arch.token = ~0; /* broadcast wakeup */
6889 else
6890 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6891
6892 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6893 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6894 fault.vector = PF_VECTOR;
6895 fault.error_code_valid = true;
6896 fault.error_code = 0;
6897 fault.nested_page_fault = false;
6898 fault.address = work->arch.token;
6899 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6900 }
e6d53e3b 6901 vcpu->arch.apf.halted = false;
7c90705b
GN		 6902}
6903
6904bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6905{
6906 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6907 return true;
6908 else
6909 return !kvm_event_needs_reinjection(vcpu) &&
6910 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6911}
6912
229456fc
MT		 6913EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6914EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6915EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6916EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6917EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6918EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6919EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6920EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6921EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6922EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6923EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6924EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
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