]> git.proxmox.com Git - mirror_ubuntu-focal-kernel.git/blame - arch/x86/kvm/x86.c
projects / mirror_ubuntu-focal-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: x86: introduce linear_{read,write}_system
[mirror_ubuntu-focal-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
b0c39dc6 70#include <asm/mshyperv.h>
0092e434 71#include <asm/hypervisor.h>
043405e1 72
d1898b73
DH		 73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
313a3dc7 76#define MAX_IO_MSRS 256
890ca9ae 77#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 80
0f65dd70
AK		 81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
50a37eb4
JR		 84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
1260edbe
LJ		 89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 91#else
1260edbe 92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 93#endif
313a3dc7 94
ba1389b7
AK		 95#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 97
c519265f
RK		 98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 100
cb142eb7 101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 102static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 103static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 105static void store_regs(struct kvm_vcpu *vcpu);
106static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 107
893590c7 108struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 109EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 110
893590c7 111static bool __read_mostly ignore_msrs = 0;
476bc001 112module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 113
fab0aa3b
EM		 114static bool __read_mostly report_ignored_msrs = true;
115module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
116
4c27625b 117unsigned int min_timer_period_us = 200;
9ed96e87
MT		 118module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
119
630994b3
MT		 120static bool __read_mostly kvmclock_periodic_sync = true;
121module_param(kvmclock_periodic_sync, bool, S_IRUGO);
122
893590c7 123bool __read_mostly kvm_has_tsc_control;
92a1f12d 124EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 125u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 126EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 127u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129u64 __read_mostly kvm_max_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 131u64 __read_mostly kvm_default_tsc_scaling_ratio;
132EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 133
cc578287 134/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 135static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 136module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
137
d0659d94 138/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 139unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94 140module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
c5ce8235 141EXPORT_SYMBOL_GPL(lapic_timer_advance_ns);
d0659d94 142
52004014
FW		 143static bool __read_mostly vector_hashing = true;
144module_param(vector_hashing, bool, S_IRUGO);
145
c4ae60e4
LA		 146bool __read_mostly enable_vmware_backdoor = false;
147module_param(enable_vmware_backdoor, bool, S_IRUGO);
148EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
149
6c86eedc
WL		 150static bool __read_mostly force_emulation_prefix = false;
151module_param(force_emulation_prefix, bool, S_IRUGO);
152
18863bdd
AK		 153#define KVM_NR_SHARED_MSRS 16
154
155struct kvm_shared_msrs_global {
156 int nr;
2bf78fa7 157 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 158};
159
160struct kvm_shared_msrs {
161 struct user_return_notifier urn;
162 bool registered;
2bf78fa7
SY		 163 struct kvm_shared_msr_values {
164 u64 host;
165 u64 curr;
166 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 167};
168
169static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 170static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 171
417bc304 172struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 173 { "pf_fixed", VCPU_STAT(pf_fixed) },
174 { "pf_guest", VCPU_STAT(pf_guest) },
175 { "tlb_flush", VCPU_STAT(tlb_flush) },
176 { "invlpg", VCPU_STAT(invlpg) },
177 { "exits", VCPU_STAT(exits) },
178 { "io_exits", VCPU_STAT(io_exits) },
179 { "mmio_exits", VCPU_STAT(mmio_exits) },
180 { "signal_exits", VCPU_STAT(signal_exits) },
181 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 182 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 183 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 184 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 185 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 186 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 187 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 188 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 189 { "request_irq", VCPU_STAT(request_irq_exits) },
190 { "irq_exits", VCPU_STAT(irq_exits) },
191 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 192 { "fpu_reload", VCPU_STAT(fpu_reload) },
193 { "insn_emulation", VCPU_STAT(insn_emulation) },
194 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 195 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 196 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 197 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 198 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
199 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
200 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
201 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
202 { "mmu_flooded", VM_STAT(mmu_flooded) },
203 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 204 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 205 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 206 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 207 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 208 { "max_mmu_page_hash_collisions",
209 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 210 { NULL }
211};
212
2acf923e
DC		 213u64 __read_mostly host_xcr0;
214
b6785def 215static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 216
af585b92
GN		 217static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
218{
219 int i;
220 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
221 vcpu->arch.apf.gfns[i] = ~0;
222}
223
18863bdd
AK		 224static void kvm_on_user_return(struct user_return_notifier *urn)
225{
226 unsigned slot;
18863bdd
AK		 227 struct kvm_shared_msrs *locals
228 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 229 struct kvm_shared_msr_values *values;
1650b4eb
IA		 230 unsigned long flags;
231
232 /*
233 * Disabling irqs at this point since the following code could be
234 * interrupted and executed through kvm_arch_hardware_disable()
235 */
236 local_irq_save(flags);
237 if (locals->registered) {
238 locals->registered = false;
239 user_return_notifier_unregister(urn);
240 }
241 local_irq_restore(flags);
18863bdd 242 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 243 values = &locals->values[slot];
244 if (values->host != values->curr) {
245 wrmsrl(shared_msrs_global.msrs[slot], values->host);
246 values->curr = values->host;
18863bdd
AK		 247 }
248 }
18863bdd
AK		 249}
250
2bf78fa7 251static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 252{
18863bdd 253 u64 value;
013f6a5d
MT		 254 unsigned int cpu = smp_processor_id();
255 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 256
2bf78fa7
SY		 257 /* only read, and nobody should modify it at this time,
258 * so don't need lock */
259 if (slot >= shared_msrs_global.nr) {
260 printk(KERN_ERR "kvm: invalid MSR slot!");
261 return;
262 }
263 rdmsrl_safe(msr, &value);
264 smsr->values[slot].host = value;
265 smsr->values[slot].curr = value;
266}
267
268void kvm_define_shared_msr(unsigned slot, u32 msr)
269{
0123be42 270 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 271 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 272 if (slot >= shared_msrs_global.nr)
273 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 274}
275EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
276
277static void kvm_shared_msr_cpu_online(void)
278{
279 unsigned i;
18863bdd
AK		 280
281 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 282 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 283}
284
8b3c3104 285int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 286{
013f6a5d
MT		 287 unsigned int cpu = smp_processor_id();
288 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 289 int err;
18863bdd 290
2bf78fa7 291 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 292 return 0;
2bf78fa7 293 smsr->values[slot].curr = value;
8b3c3104
AH		 294 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
295 if (err)
296 return 1;
297
18863bdd
AK		 298 if (!smsr->registered) {
299 smsr->urn.on_user_return = kvm_on_user_return;
300 user_return_notifier_register(&smsr->urn);
301 smsr->registered = true;
302 }
8b3c3104 303 return 0;
18863bdd
AK		 304}
305EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
306
13a34e06 307static void drop_user_return_notifiers(void)
3548bab5 308{
013f6a5d
MT		 309 unsigned int cpu = smp_processor_id();
310 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 311
312 if (smsr->registered)
313 kvm_on_user_return(&smsr->urn);
314}
315
6866b83e
CO		 316u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
317{
8a5a87d9 318 return vcpu->arch.apic_base;
6866b83e
CO		 319}
320EXPORT_SYMBOL_GPL(kvm_get_apic_base);
321
58871649
JM		 322enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
323{
324 return kvm_apic_mode(kvm_get_apic_base(vcpu));
325}
326EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
327
58cb628d
JK		 328int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
329{
58871649
JM		 330 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
331 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
d6321d49
RK		 332 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
333 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 334
58871649 335 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
58cb628d 336 return 1;
58871649
JM		 337 if (!msr_info->host_initiated) {
338 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
339 return 1;
340 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
341 return 1;
342 }
58cb628d
JK		 343
344 kvm_lapic_set_base(vcpu, msr_info->data);
345 return 0;
6866b83e
CO		 346}
347EXPORT_SYMBOL_GPL(kvm_set_apic_base);
348
2605fc21 349asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 350{
351 /* Fault while not rebooting. We want the trace. */
352 BUG();
353}
354EXPORT_SYMBOL_GPL(kvm_spurious_fault);
355
3fd28fce
ED		 356#define EXCPT_BENIGN 0
357#define EXCPT_CONTRIBUTORY 1
358#define EXCPT_PF 2
359
360static int exception_class(int vector)
361{
362 switch (vector) {
363 case PF_VECTOR:
364 return EXCPT_PF;
365 case DE_VECTOR:
366 case TS_VECTOR:
367 case NP_VECTOR:
368 case SS_VECTOR:
369 case GP_VECTOR:
370 return EXCPT_CONTRIBUTORY;
371 default:
372 break;
373 }
374 return EXCPT_BENIGN;
375}
376
d6e8c854
NA		 377#define EXCPT_FAULT 0
378#define EXCPT_TRAP 1
379#define EXCPT_ABORT 2
380#define EXCPT_INTERRUPT 3
381
382static int exception_type(int vector)
383{
384 unsigned int mask;
385
386 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
387 return EXCPT_INTERRUPT;
388
389 mask = 1 << vector;
390
391 /* #DB is trap, as instruction watchpoints are handled elsewhere */
392 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
393 return EXCPT_TRAP;
394
395 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
396 return EXCPT_ABORT;
397
398 /* Reserved exceptions will result in fault */
399 return EXCPT_FAULT;
400}
401
3fd28fce 402static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 403 unsigned nr, bool has_error, u32 error_code,
404 bool reinject)
3fd28fce
ED		 405{
406 u32 prev_nr;
407 int class1, class2;
408
3842d135
AK		 409 kvm_make_request(KVM_REQ_EVENT, vcpu);
410
664f8e26 411 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 412 queue:
3ffb2468
NA		 413 if (has_error && !is_protmode(vcpu))
414 has_error = false;
664f8e26
WL		 415 if (reinject) {
416 /*
417 * On vmentry, vcpu->arch.exception.pending is only
418 * true if an event injection was blocked by
419 * nested_run_pending. In that case, however,
420 * vcpu_enter_guest requests an immediate exit,
421 * and the guest shouldn't proceed far enough to
422 * need reinjection.
423 */
424 WARN_ON_ONCE(vcpu->arch.exception.pending);
425 vcpu->arch.exception.injected = true;
426 } else {
427 vcpu->arch.exception.pending = true;
428 vcpu->arch.exception.injected = false;
429 }
3fd28fce
ED		 430 vcpu->arch.exception.has_error_code = has_error;
431 vcpu->arch.exception.nr = nr;
432 vcpu->arch.exception.error_code = error_code;
433 return;
434 }
435
436 /* to check exception */
437 prev_nr = vcpu->arch.exception.nr;
438 if (prev_nr == DF_VECTOR) {
439 /* triple fault -> shutdown */
a8eeb04a 440 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 441 return;
442 }
443 class1 = exception_class(prev_nr);
444 class2 = exception_class(nr);
445 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
446 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 447 /*
448 * Generate double fault per SDM Table 5-5. Set
449 * exception.pending = true so that the double fault
450 * can trigger a nested vmexit.
451 */
3fd28fce 452 vcpu->arch.exception.pending = true;
664f8e26 453 vcpu->arch.exception.injected = false;
3fd28fce
ED		 454 vcpu->arch.exception.has_error_code = true;
455 vcpu->arch.exception.nr = DF_VECTOR;
456 vcpu->arch.exception.error_code = 0;
457 } else
458 /* replace previous exception with a new one in a hope
459 that instruction re-execution will regenerate lost
460 exception */
461 goto queue;
462}
463
298101da
AK		 464void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
465{
ce7ddec4 466 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 467}
468EXPORT_SYMBOL_GPL(kvm_queue_exception);
469
ce7ddec4
JR		 470void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
471{
472 kvm_multiple_exception(vcpu, nr, false, 0, true);
473}
474EXPORT_SYMBOL_GPL(kvm_requeue_exception);
475
6affcbed 476int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 477{
db8fcefa
AP		 478 if (err)
479 kvm_inject_gp(vcpu, 0);
480 else
6affcbed
KH		 481 return kvm_skip_emulated_instruction(vcpu);
482
483 return 1;
db8fcefa
AP		 484}
485EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 486
6389ee94 487void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 488{
489 ++vcpu->stat.pf_guest;
adfe20fb
WL		 490 vcpu->arch.exception.nested_apf =
491 is_guest_mode(vcpu) && fault->async_page_fault;
492 if (vcpu->arch.exception.nested_apf)
493 vcpu->arch.apf.nested_apf_token = fault->address;
494 else
495 vcpu->arch.cr2 = fault->address;
6389ee94 496 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 497}
27d6c865 498EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 499
ef54bcfe 500static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 501{
6389ee94
AK		 502 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
503 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 504 else
6389ee94 505 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 506
507 return fault->nested_page_fault;
d4f8cf66
JR		 508}
509
3419ffc8
SY		 510void kvm_inject_nmi(struct kvm_vcpu *vcpu)
511{
7460fb4a
AK		 512 atomic_inc(&vcpu->arch.nmi_queued);
513 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 514}
515EXPORT_SYMBOL_GPL(kvm_inject_nmi);
516
298101da
AK		 517void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
518{
ce7ddec4 519 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 520}
521EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
522
ce7ddec4
JR		 523void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
524{
525 kvm_multiple_exception(vcpu, nr, true, error_code, true);
526}
527EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
528
0a79b009
AK		 529/*
530 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
531 * a #GP and return false.
532 */
533bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 534{
0a79b009
AK		 535 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
536 return true;
537 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
538 return false;
298101da 539}
0a79b009 540EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 541
16f8a6f9
NA		 542bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
543{
544 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
545 return true;
546
547 kvm_queue_exception(vcpu, UD_VECTOR);
548 return false;
549}
550EXPORT_SYMBOL_GPL(kvm_require_dr);
551
ec92fe44
JR		 552/*
553 * This function will be used to read from the physical memory of the currently
54bf36aa 554 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 555 * can read from guest physical or from the guest's guest physical memory.
556 */
557int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
558 gfn_t ngfn, void *data, int offset, int len,
559 u32 access)
560{
54987b7a 561 struct x86_exception exception;
ec92fe44
JR		 562 gfn_t real_gfn;
563 gpa_t ngpa;
564
565 ngpa = gfn_to_gpa(ngfn);
54987b7a 566 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 567 if (real_gfn == UNMAPPED_GVA)
568 return -EFAULT;
569
570 real_gfn = gpa_to_gfn(real_gfn);
571
54bf36aa 572 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 573}
574EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
575
69b0049a 576static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 577 void *data, int offset, int len, u32 access)
578{
579 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
580 data, offset, len, access);
581}
582
a03490ed
CO		 583/*
584 * Load the pae pdptrs. Return true is they are all valid.
585 */
ff03a073 586int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 587{
588 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
589 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
590 int i;
591 int ret;
ff03a073 592 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 593
ff03a073
JR		 594 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
595 offset * sizeof(u64), sizeof(pdpte),
596 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 597 if (ret < 0) {
598 ret = 0;
599 goto out;
600 }
601 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 602 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 603 (pdpte[i] &
604 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 605 ret = 0;
606 goto out;
607 }
608 }
609 ret = 1;
610
ff03a073 611 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 612 __set_bit(VCPU_EXREG_PDPTR,
613 (unsigned long *)&vcpu->arch.regs_avail);
614 __set_bit(VCPU_EXREG_PDPTR,
615 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 616out:
a03490ed
CO		 617
618 return ret;
619}
cc4b6871 620EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 621
9ed38ffa 622bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 623{
ff03a073 624 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 625 bool changed = true;
3d06b8bf
JR		 626 int offset;
627 gfn_t gfn;
d835dfec
AK		 628 int r;
629
630 if (is_long_mode(vcpu) || !is_pae(vcpu))
631 return false;
632
6de4f3ad
AK		 633 if (!test_bit(VCPU_EXREG_PDPTR,
634 (unsigned long *)&vcpu->arch.regs_avail))
635 return true;
636
a512177e
PB		 637 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
638 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 639 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
640 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 641 if (r < 0)
642 goto out;
ff03a073 643 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 644out:
d835dfec
AK		 645
646 return changed;
647}
9ed38ffa 648EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 649
49a9b07e 650int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 651{
aad82703 652 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 653 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 654
f9a48e6a
AK		 655 cr0 |= X86_CR0_ET;
656
ab344828 657#ifdef CONFIG_X86_64
0f12244f
GN		 658 if (cr0 & 0xffffffff00000000UL)
659 return 1;
ab344828
GN		 660#endif
661
662 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 663
0f12244f
GN		 664 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
665 return 1;
a03490ed 666
0f12244f
GN		 667 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
668 return 1;
a03490ed
CO		 669
670 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
671#ifdef CONFIG_X86_64
f6801dff 672 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 673 int cs_db, cs_l;
674
0f12244f
GN		 675 if (!is_pae(vcpu))
676 return 1;
a03490ed 677 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 678 if (cs_l)
679 return 1;
a03490ed
CO		 680 } else
681#endif
ff03a073 682 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 683 kvm_read_cr3(vcpu)))
0f12244f 684 return 1;
a03490ed
CO		 685 }
686
ad756a16
MJ		 687 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
688 return 1;
689
a03490ed 690 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 691
d170c419 692 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 693 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 694 kvm_async_pf_hash_reset(vcpu);
695 }
e5f3f027 696
aad82703
SY		 697 if ((cr0 ^ old_cr0) & update_bits)
698 kvm_mmu_reset_context(vcpu);
b18d5431 699
879ae188
LE		 700 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
701 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
702 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 703 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
704
0f12244f
GN		 705 return 0;
706}
2d3ad1f4 707EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 708
2d3ad1f4 709void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 710{
49a9b07e 711 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 712}
2d3ad1f4 713EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 714
42bdf991
MT		 715static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
716{
717 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
718 !vcpu->guest_xcr0_loaded) {
719 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 720 if (vcpu->arch.xcr0 != host_xcr0)
721 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 722 vcpu->guest_xcr0_loaded = 1;
723 }
724}
725
726static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
727{
728 if (vcpu->guest_xcr0_loaded) {
729 if (vcpu->arch.xcr0 != host_xcr0)
730 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
731 vcpu->guest_xcr0_loaded = 0;
732 }
733}
734
69b0049a 735static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 736{
56c103ec
LJ		 737 u64 xcr0 = xcr;
738 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 739 u64 valid_bits;
2acf923e
DC		 740
741 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
742 if (index != XCR_XFEATURE_ENABLED_MASK)
743 return 1;
d91cab78 744 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 745 return 1;
d91cab78 746 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 747 return 1;
46c34cb0
PB		 748
749 /*
750 * Do not allow the guest to set bits that we do not support
751 * saving. However, xcr0 bit 0 is always set, even if the
752 * emulated CPU does not support XSAVE (see fx_init).
753 */
d91cab78 754 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 755 if (xcr0 & ~valid_bits)
2acf923e 756 return 1;
46c34cb0 757
d91cab78
DH		 758 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
759 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 760 return 1;
761
d91cab78
DH		 762 if (xcr0 & XFEATURE_MASK_AVX512) {
763 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 764 return 1;
d91cab78 765 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 766 return 1;
767 }
2acf923e 768 vcpu->arch.xcr0 = xcr0;
56c103ec 769
d91cab78 770 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 771 kvm_update_cpuid(vcpu);
2acf923e
DC		 772 return 0;
773}
774
775int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
776{
764bcbc5
Z		 777 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
778 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 779 kvm_inject_gp(vcpu, 0);
780 return 1;
781 }
782 return 0;
783}
784EXPORT_SYMBOL_GPL(kvm_set_xcr);
785
a83b29c6 786int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 787{
fc78f519 788 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 789 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 790 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 791
0f12244f
GN		 792 if (cr4 & CR4_RESERVED_BITS)
793 return 1;
a03490ed 794
d6321d49 795 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 796 return 1;
797
d6321d49 798 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 799 return 1;
800
d6321d49 801 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 802 return 1;
803
d6321d49 804 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 805 return 1;
806
d6321d49 807 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 808 return 1;
809
fd8cb433 810 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 811 return 1;
812
ae3e61e1
PB		 813 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
814 return 1;
815
a03490ed 816 if (is_long_mode(vcpu)) {
0f12244f
GN		 817 if (!(cr4 & X86_CR4_PAE))
818 return 1;
a2edf57f
AK		 819 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
820 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 821 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
822 kvm_read_cr3(vcpu)))
0f12244f
GN		 823 return 1;
824
ad756a16 825 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 826 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 827 return 1;
828
829 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
830 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
831 return 1;
832 }
833
5e1746d6 834 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 835 return 1;
a03490ed 836
ad756a16
MJ		 837 if (((cr4 ^ old_cr4) & pdptr_bits) ||
838 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 839 kvm_mmu_reset_context(vcpu);
0f12244f 840
b9baba86 841 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 842 kvm_update_cpuid(vcpu);
2acf923e 843
0f12244f
GN		 844 return 0;
845}
2d3ad1f4 846EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 847
2390218b 848int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 849{
ac146235 850#ifdef CONFIG_X86_64
c19986fe
JS		 851 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
852
853 if (pcid_enabled)
854 cr3 &= ~CR3_PCID_INVD;
ac146235 855#endif
9d88fca7 856
9f8fe504 857 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 858 kvm_mmu_sync_roots(vcpu);
77c3913b 859 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 860 return 0;
d835dfec
AK		 861 }
862
d1cd3ce9 863 if (is_long_mode(vcpu) &&
a780a3ea 864 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
d1cd3ce9
YZ		 865 return 1;
866 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 867 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 868 return 1;
a03490ed 869
0f12244f 870 vcpu->arch.cr3 = cr3;
aff48baa 871 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 872 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 873 return 0;
874}
2d3ad1f4 875EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 876
eea1cff9 877int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 878{
0f12244f
GN		 879 if (cr8 & CR8_RESERVED_BITS)
880 return 1;
35754c98 881 if (lapic_in_kernel(vcpu))
a03490ed
CO		 882 kvm_lapic_set_tpr(vcpu, cr8);
883 else
ad312c7c 884 vcpu->arch.cr8 = cr8;
0f12244f
GN		 885 return 0;
886}
2d3ad1f4 887EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 888
2d3ad1f4 889unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 890{
35754c98 891 if (lapic_in_kernel(vcpu))
a03490ed
CO		 892 return kvm_lapic_get_cr8(vcpu);
893 else
ad312c7c 894 return vcpu->arch.cr8;
a03490ed 895}
2d3ad1f4 896EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 897
ae561ede
NA		 898static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
899{
900 int i;
901
902 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
903 for (i = 0; i < KVM_NR_DB_REGS; i++)
904 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
905 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
906 }
907}
908
73aaf249
JK		 909static void kvm_update_dr6(struct kvm_vcpu *vcpu)
910{
911 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
912 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
913}
914
c8639010
JK		 915static void kvm_update_dr7(struct kvm_vcpu *vcpu)
916{
917 unsigned long dr7;
918
919 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
920 dr7 = vcpu->arch.guest_debug_dr7;
921 else
922 dr7 = vcpu->arch.dr7;
923 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 924 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
925 if (dr7 & DR7_BP_EN_MASK)
926 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 927}
928
6f43ed01
NA		 929static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
930{
931 u64 fixed = DR6_FIXED_1;
932
d6321d49 933 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 934 fixed |= DR6_RTM;
935 return fixed;
936}
937
338dbc97 938static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 939{
940 switch (dr) {
941 case 0 ... 3:
942 vcpu->arch.db[dr] = val;
943 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
944 vcpu->arch.eff_db[dr] = val;
945 break;
946 case 4:
020df079
GN		 947 /* fall through */
948 case 6:
338dbc97
GN		 949 if (val & 0xffffffff00000000ULL)
950 return -1; /* #GP */
6f43ed01 951 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 952 kvm_update_dr6(vcpu);
020df079
GN		 953 break;
954 case 5:
020df079
GN		 955 /* fall through */
956 default: /* 7 */
338dbc97
GN		 957 if (val & 0xffffffff00000000ULL)
958 return -1; /* #GP */
020df079 959 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 960 kvm_update_dr7(vcpu);
020df079
GN		 961 break;
962 }
963
964 return 0;
965}
338dbc97
GN		 966
967int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
968{
16f8a6f9 969 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 970 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 971 return 1;
972 }
973 return 0;
338dbc97 974}
020df079
GN		 975EXPORT_SYMBOL_GPL(kvm_set_dr);
976
16f8a6f9 977int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 978{
979 switch (dr) {
980 case 0 ... 3:
981 *val = vcpu->arch.db[dr];
982 break;
983 case 4:
020df079
GN		 984 /* fall through */
985 case 6:
73aaf249
JK		 986 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
987 *val = vcpu->arch.dr6;
988 else
989 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 990 break;
991 case 5:
020df079
GN		 992 /* fall through */
993 default: /* 7 */
994 *val = vcpu->arch.dr7;
995 break;
996 }
338dbc97
GN		 997 return 0;
998}
020df079
GN		 999EXPORT_SYMBOL_GPL(kvm_get_dr);
1000
022cd0e8
AK		 1001bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1002{
1003 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
1004 u64 data;
1005 int err;
1006
c6702c9d 1007 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 1008 if (err)
1009 return err;
1010 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
1011 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
1012 return err;
1013}
1014EXPORT_SYMBOL_GPL(kvm_rdpmc);
1015
043405e1
CO		 1016/*
1017 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1018 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1019 *
1020 * This list is modified at module load time to reflect the
e3267cbb 1021 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1022 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1023 * may depend on host virtualization features rather than host cpu features.
043405e1 1024 */
e3267cbb 1025
043405e1
CO		 1026static u32 msrs_to_save[] = {
1027 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1028 MSR_STAR,
043405e1
CO		 1029#ifdef CONFIG_X86_64
1030 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1031#endif
b3897a49 1032 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1033 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
d28b387f 1034 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
043405e1
CO		 1035};
1036
1037static unsigned num_msrs_to_save;
1038
62ef68bb
PB		 1039static u32 emulated_msrs[] = {
1040 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1041 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1042 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1043 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1044 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1045 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1046 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1047 HV_X64_MSR_RESET,
11c4b1ca 1048 HV_X64_MSR_VP_INDEX,
9eec50b8 1049 HV_X64_MSR_VP_RUNTIME,
5c919412 1050 HV_X64_MSR_SCONTROL,
1f4b34f8 1051 HV_X64_MSR_STIMER0_CONFIG,
d4abc577 1052 HV_X64_MSR_VP_ASSIST_PAGE,
a2e164e7
VK		 1053 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1054 HV_X64_MSR_TSC_EMULATION_STATUS,
1055
1056 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1057 MSR_KVM_PV_EOI_EN,
1058
ba904635 1059 MSR_IA32_TSC_ADJUST,
a3e06bbe 1060 MSR_IA32_TSCDEADLINE,
043405e1 1061 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1062 MSR_IA32_MCG_STATUS,
1063 MSR_IA32_MCG_CTL,
c45dcc71 1064 MSR_IA32_MCG_EXT_CTL,
64d60670 1065 MSR_IA32_SMBASE,
52797bf9 1066 MSR_SMI_COUNT,
db2336a8
KH		 1067 MSR_PLATFORM_INFO,
1068 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1069};
1070
62ef68bb
PB		 1071static unsigned num_emulated_msrs;
1072
801e459a
TL		 1073/*
1074 * List of msr numbers which are used to expose MSR-based features that
1075 * can be used by a hypervisor to validate requested CPU features.
1076 */
1077static u32 msr_based_features[] = {
1389309c
PB		 1078 MSR_IA32_VMX_BASIC,
1079 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1080 MSR_IA32_VMX_PINBASED_CTLS,
1081 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1082 MSR_IA32_VMX_PROCBASED_CTLS,
1083 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1084 MSR_IA32_VMX_EXIT_CTLS,
1085 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1086 MSR_IA32_VMX_ENTRY_CTLS,
1087 MSR_IA32_VMX_MISC,
1088 MSR_IA32_VMX_CR0_FIXED0,
1089 MSR_IA32_VMX_CR0_FIXED1,
1090 MSR_IA32_VMX_CR4_FIXED0,
1091 MSR_IA32_VMX_CR4_FIXED1,
1092 MSR_IA32_VMX_VMCS_ENUM,
1093 MSR_IA32_VMX_PROCBASED_CTLS2,
1094 MSR_IA32_VMX_EPT_VPID_CAP,
1095 MSR_IA32_VMX_VMFUNC,
1096
d1d93fa9 1097 MSR_F10H_DECFG,
518e7b94 1098 MSR_IA32_UCODE_REV,
801e459a
TL		 1099};
1100
1101static unsigned int num_msr_based_features;
1102
66421c1e
WL		 1103static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1104{
1105 switch (msr->index) {
518e7b94
WL		 1106 case MSR_IA32_UCODE_REV:
1107 rdmsrl(msr->index, msr->data);
1108 break;
66421c1e
WL		 1109 default:
1110 if (kvm_x86_ops->get_msr_feature(msr))
1111 return 1;
1112 }
1113 return 0;
1114}
1115
801e459a
TL		 1116static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1117{
1118 struct kvm_msr_entry msr;
66421c1e 1119 int r;
801e459a
TL		 1120
1121 msr.index = index;
66421c1e
WL		 1122 r = kvm_get_msr_feature(&msr);
1123 if (r)
1124 return r;
801e459a
TL		 1125
1126 *data = msr.data;
1127
1128 return 0;
1129}
1130
384bb783 1131bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1132{
b69e8cae 1133 if (efer & efer_reserved_bits)
384bb783 1134 return false;
15c4a640 1135
1b4d56b8 1136 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1137 return false;
1b2fd70c 1138
1b4d56b8 1139 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1140 return false;
d8017474 1141
384bb783
JK		 1142 return true;
1143}
1144EXPORT_SYMBOL_GPL(kvm_valid_efer);
1145
1146static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1147{
1148 u64 old_efer = vcpu->arch.efer;
1149
1150 if (!kvm_valid_efer(vcpu, efer))
1151 return 1;
1152
1153 if (is_paging(vcpu)
1154 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1155 return 1;
1156
15c4a640 1157 efer &= ~EFER_LMA;
f6801dff 1158 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1159
a3d204e2
SY		 1160 kvm_x86_ops->set_efer(vcpu, efer);
1161
aad82703
SY		 1162 /* Update reserved bits */
1163 if ((efer ^ old_efer) & EFER_NX)
1164 kvm_mmu_reset_context(vcpu);
1165
b69e8cae 1166 return 0;
15c4a640
CO		 1167}
1168
f2b4b7dd
JR		 1169void kvm_enable_efer_bits(u64 mask)
1170{
1171 efer_reserved_bits &= ~mask;
1172}
1173EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1174
15c4a640
CO		 1175/*
1176 * Writes msr value into into the appropriate "register".
1177 * Returns 0 on success, non-0 otherwise.
1178 * Assumes vcpu_load() was already called.
1179 */
8fe8ab46 1180int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1181{
854e8bb1
NA		 1182 switch (msr->index) {
1183 case MSR_FS_BASE:
1184 case MSR_GS_BASE:
1185 case MSR_KERNEL_GS_BASE:
1186 case MSR_CSTAR:
1187 case MSR_LSTAR:
fd8cb433 1188 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1189 return 1;
1190 break;
1191 case MSR_IA32_SYSENTER_EIP:
1192 case MSR_IA32_SYSENTER_ESP:
1193 /*
1194 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1195 * non-canonical address is written on Intel but not on
1196 * AMD (which ignores the top 32-bits, because it does
1197 * not implement 64-bit SYSENTER).
1198 *
1199 * 64-bit code should hence be able to write a non-canonical
1200 * value on AMD. Making the address canonical ensures that
1201 * vmentry does not fail on Intel after writing a non-canonical
1202 * value, and that something deterministic happens if the guest
1203 * invokes 64-bit SYSENTER.
1204 */
fd8cb433 1205 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1206 }
8fe8ab46 1207 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1208}
854e8bb1 1209EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1210
313a3dc7
CO		 1211/*
1212 * Adapt set_msr() to msr_io()'s calling convention
1213 */
609e36d3
PB		 1214static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1215{
1216 struct msr_data msr;
1217 int r;
1218
1219 msr.index = index;
1220 msr.host_initiated = true;
1221 r = kvm_get_msr(vcpu, &msr);
1222 if (r)
1223 return r;
1224
1225 *data = msr.data;
1226 return 0;
1227}
1228
313a3dc7
CO		 1229static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1230{
8fe8ab46
WA		 1231 struct msr_data msr;
1232
1233 msr.data = *data;
1234 msr.index = index;
1235 msr.host_initiated = true;
1236 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1237}
1238
16e8d74d
MT		 1239#ifdef CONFIG_X86_64
1240struct pvclock_gtod_data {
1241 seqcount_t seq;
1242
1243 struct { /* extract of a clocksource struct */
1244 int vclock_mode;
a5a1d1c2
TG		 1245 u64 cycle_last;
1246 u64 mask;
16e8d74d
MT		 1247 u32 mult;
1248 u32 shift;
1249 } clock;
1250
cbcf2dd3
TG		 1251 u64 boot_ns;
1252 u64 nsec_base;
55dd00a7 1253 u64 wall_time_sec;
16e8d74d
MT		 1254};
1255
1256static struct pvclock_gtod_data pvclock_gtod_data;
1257
1258static void update_pvclock_gtod(struct timekeeper *tk)
1259{
1260 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1261 u64 boot_ns;
1262
876e7881 1263 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1264
1265 write_seqcount_begin(&vdata->seq);
1266
1267 /* copy pvclock gtod data */
876e7881
PZ		 1268 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1269 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1270 vdata->clock.mask = tk->tkr_mono.mask;
1271 vdata->clock.mult = tk->tkr_mono.mult;
1272 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1273
cbcf2dd3 1274 vdata->boot_ns = boot_ns;
876e7881 1275 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1276
55dd00a7
MT		 1277 vdata->wall_time_sec = tk->xtime_sec;
1278
16e8d74d
MT		 1279 write_seqcount_end(&vdata->seq);
1280}
1281#endif
1282
bab5bb39
NK		 1283void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1284{
1285 /*
1286 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1287 * vcpu_enter_guest. This function is only called from
1288 * the physical CPU that is running vcpu.
1289 */
1290 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1291}
16e8d74d 1292
18068523
GOC		 1293static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1294{
9ed3c444
AK		 1295 int version;
1296 int r;
50d0a0f9 1297 struct pvclock_wall_clock wc;
87aeb54f 1298 struct timespec64 boot;
18068523
GOC		 1299
1300 if (!wall_clock)
1301 return;
1302
9ed3c444
AK		 1303 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1304 if (r)
1305 return;
1306
1307 if (version & 1)
1308 ++version; /* first time write, random junk */
1309
1310 ++version;
18068523 1311
1dab1345
NK		 1312 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1313 return;
18068523 1314
50d0a0f9
GH		 1315 /*
1316 * The guest calculates current wall clock time by adding
34c238a1 1317 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1318 * wall clock specified here. guest system time equals host
1319 * system time for us, thus we must fill in host boot time here.
1320 */
87aeb54f 1321 getboottime64(&boot);
50d0a0f9 1322
4b648665 1323 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1324 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1325 boot = timespec64_sub(boot, ts);
4b648665 1326 }
87aeb54f 1327 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1328 wc.nsec = boot.tv_nsec;
1329 wc.version = version;
18068523
GOC		 1330
1331 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1332
1333 version++;
1334 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1335}
1336
50d0a0f9
GH		 1337static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1338{
b51012de
PB		 1339 do_shl32_div32(dividend, divisor);
1340 return dividend;
50d0a0f9
GH		 1341}
1342
3ae13faa 1343static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1344 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1345{
5f4e3f88 1346 uint64_t scaled64;
50d0a0f9
GH		 1347 int32_t shift = 0;
1348 uint64_t tps64;
1349 uint32_t tps32;
1350
3ae13faa
PB		 1351 tps64 = base_hz;
1352 scaled64 = scaled_hz;
50933623 1353 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1354 tps64 >>= 1;
1355 shift--;
1356 }
1357
1358 tps32 = (uint32_t)tps64;
50933623
JK		 1359 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1360 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1361 scaled64 >>= 1;
1362 else
1363 tps32 <<= 1;
50d0a0f9
GH		 1364 shift++;
1365 }
1366
5f4e3f88
ZA		 1367 *pshift = shift;
1368 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1369
3ae13faa
PB		 1370 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1371 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1372}
1373
d828199e 1374#ifdef CONFIG_X86_64
16e8d74d 1375static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1376#endif
16e8d74d 1377
c8076604 1378static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1379static unsigned long max_tsc_khz;
c8076604 1380
cc578287 1381static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1382{
cc578287
ZA		 1383 u64 v = (u64)khz * (1000000 + ppm);
1384 do_div(v, 1000000);
1385 return v;
1e993611
JR		 1386}
1387
381d585c
HZ		 1388static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1389{
1390 u64 ratio;
1391
1392 /* Guest TSC same frequency as host TSC? */
1393 if (!scale) {
1394 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1395 return 0;
1396 }
1397
1398 /* TSC scaling supported? */
1399 if (!kvm_has_tsc_control) {
1400 if (user_tsc_khz > tsc_khz) {
1401 vcpu->arch.tsc_catchup = 1;
1402 vcpu->arch.tsc_always_catchup = 1;
1403 return 0;
1404 } else {
1405 WARN(1, "user requested TSC rate below hardware speed\n");
1406 return -1;
1407 }
1408 }
1409
1410 /* TSC scaling required - calculate ratio */
1411 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1412 user_tsc_khz, tsc_khz);
1413
1414 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1415 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1416 user_tsc_khz);
1417 return -1;
1418 }
1419
1420 vcpu->arch.tsc_scaling_ratio = ratio;
1421 return 0;
1422}
1423
4941b8cb 1424static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1425{
cc578287
ZA		 1426 u32 thresh_lo, thresh_hi;
1427 int use_scaling = 0;
217fc9cf 1428
03ba32ca 1429 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1430 if (user_tsc_khz == 0) {
ad721883
HZ		 1431 /* set tsc_scaling_ratio to a safe value */
1432 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1433 return -1;
ad721883 1434 }
03ba32ca 1435
c285545f 1436 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1437 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1438 &vcpu->arch.virtual_tsc_shift,
1439 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1440 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1441
1442 /*
1443 * Compute the variation in TSC rate which is acceptable
1444 * within the range of tolerance and decide if the
1445 * rate being applied is within that bounds of the hardware
1446 * rate. If so, no scaling or compensation need be done.
1447 */
1448 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1449 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1450 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1451 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1452 use_scaling = 1;
1453 }
4941b8cb 1454 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1455}
1456
1457static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1458{
e26101b1 1459 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1460 vcpu->arch.virtual_tsc_mult,
1461 vcpu->arch.virtual_tsc_shift);
e26101b1 1462 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1463 return tsc;
1464}
1465
b0c39dc6
VK		 1466static inline int gtod_is_based_on_tsc(int mode)
1467{
1468 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1469}
1470
69b0049a 1471static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1472{
1473#ifdef CONFIG_X86_64
1474 bool vcpus_matched;
b48aa97e
MT		 1475 struct kvm_arch *ka = &vcpu->kvm->arch;
1476 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1477
1478 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1479 atomic_read(&vcpu->kvm->online_vcpus));
1480
7f187922
MT		 1481 /*
1482 * Once the masterclock is enabled, always perform request in
1483 * order to update it.
1484 *
1485 * In order to enable masterclock, the host clocksource must be TSC
1486 * and the vcpus need to have matched TSCs. When that happens,
1487 * perform request to enable masterclock.
1488 */
1489 if (ka->use_master_clock ||
b0c39dc6 1490 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1491 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1492
1493 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1494 atomic_read(&vcpu->kvm->online_vcpus),
1495 ka->use_master_clock, gtod->clock.vclock_mode);
1496#endif
1497}
1498
ba904635
WA		 1499static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1500{
e79f245d 1501 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
ba904635
WA		 1502 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1503}
1504
35181e86
HZ		 1505/*
1506 * Multiply tsc by a fixed point number represented by ratio.
1507 *
1508 * The most significant 64-N bits (mult) of ratio represent the
1509 * integral part of the fixed point number; the remaining N bits
1510 * (frac) represent the fractional part, ie. ratio represents a fixed
1511 * point number (mult + frac * 2^(-N)).
1512 *
1513 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1514 */
1515static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1516{
1517 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1518}
1519
1520u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1521{
1522 u64 _tsc = tsc;
1523 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1524
1525 if (ratio != kvm_default_tsc_scaling_ratio)
1526 _tsc = __scale_tsc(ratio, tsc);
1527
1528 return _tsc;
1529}
1530EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1531
07c1419a
HZ		 1532static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1533{
1534 u64 tsc;
1535
1536 tsc = kvm_scale_tsc(vcpu, rdtsc());
1537
1538 return target_tsc - tsc;
1539}
1540
4ba76538
HZ		 1541u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1542{
e79f245d
KA		 1543 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1544
1545 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1546}
1547EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1548
a545ab6a
LC		 1549static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1550{
1551 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1552 vcpu->arch.tsc_offset = offset;
1553}
1554
b0c39dc6
VK		 1555static inline bool kvm_check_tsc_unstable(void)
1556{
1557#ifdef CONFIG_X86_64
1558 /*
1559 * TSC is marked unstable when we're running on Hyper-V,
1560 * 'TSC page' clocksource is good.
1561 */
1562 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1563 return false;
1564#endif
1565 return check_tsc_unstable();
1566}
1567
8fe8ab46 1568void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1569{
1570 struct kvm *kvm = vcpu->kvm;
f38e098f 1571 u64 offset, ns, elapsed;
99e3e30a 1572 unsigned long flags;
b48aa97e 1573 bool matched;
0d3da0d2 1574 bool already_matched;
8fe8ab46 1575 u64 data = msr->data;
c5e8ec8e 1576 bool synchronizing = false;
99e3e30a 1577
038f8c11 1578 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1579 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1580 ns = ktime_get_boot_ns();
f38e098f 1581 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1582
03ba32ca 1583 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1584 if (data == 0 && msr->host_initiated) {
1585 /*
1586 * detection of vcpu initialization -- need to sync
1587 * with other vCPUs. This particularly helps to keep
1588 * kvm_clock stable after CPU hotplug
1589 */
1590 synchronizing = true;
1591 } else {
1592 u64 tsc_exp = kvm->arch.last_tsc_write +
1593 nsec_to_cycles(vcpu, elapsed);
1594 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1595 /*
1596 * Special case: TSC write with a small delta (1 second)
1597 * of virtual cycle time against real time is
1598 * interpreted as an attempt to synchronize the CPU.
1599 */
1600 synchronizing = data < tsc_exp + tsc_hz &&
1601 data + tsc_hz > tsc_exp;
1602 }
c5e8ec8e 1603 }
f38e098f
ZA		 1604
1605 /*
5d3cb0f6
ZA		 1606 * For a reliable TSC, we can match TSC offsets, and for an unstable
1607 * TSC, we add elapsed time in this computation. We could let the
1608 * compensation code attempt to catch up if we fall behind, but
1609 * it's better to try to match offsets from the beginning.
1610 */
c5e8ec8e 1611 if (synchronizing &&
5d3cb0f6 1612 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1613 if (!kvm_check_tsc_unstable()) {
e26101b1 1614 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1615 pr_debug("kvm: matched tsc offset for %llu\n", data);
1616 } else {
857e4099 1617 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1618 data += delta;
07c1419a 1619 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1620 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1621 }
b48aa97e 1622 matched = true;
0d3da0d2 1623 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1624 } else {
1625 /*
1626 * We split periods of matched TSC writes into generations.
1627 * For each generation, we track the original measured
1628 * nanosecond time, offset, and write, so if TSCs are in
1629 * sync, we can match exact offset, and if not, we can match
4a969980 1630 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1631 *
1632 * These values are tracked in kvm->arch.cur_xxx variables.
1633 */
1634 kvm->arch.cur_tsc_generation++;
1635 kvm->arch.cur_tsc_nsec = ns;
1636 kvm->arch.cur_tsc_write = data;
1637 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1638 matched = false;
0d3da0d2 1639 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1640 kvm->arch.cur_tsc_generation, data);
f38e098f 1641 }
e26101b1
ZA		 1642
1643 /*
1644 * We also track th most recent recorded KHZ, write and time to
1645 * allow the matching interval to be extended at each write.
1646 */
f38e098f
ZA		 1647 kvm->arch.last_tsc_nsec = ns;
1648 kvm->arch.last_tsc_write = data;
5d3cb0f6 1649 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1650
b183aa58 1651 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1652
1653 /* Keep track of which generation this VCPU has synchronized to */
1654 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1655 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1656 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1657
d6321d49 1658 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1659 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1660
a545ab6a 1661 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1662 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1663
1664 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1665 if (!matched) {
b48aa97e 1666 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1667 } else if (!already_matched) {
1668 kvm->arch.nr_vcpus_matched_tsc++;
1669 }
b48aa97e
MT		 1670
1671 kvm_track_tsc_matching(vcpu);
1672 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1673}
e26101b1 1674
99e3e30a
ZA		 1675EXPORT_SYMBOL_GPL(kvm_write_tsc);
1676
58ea6767
HZ		 1677static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1678 s64 adjustment)
1679{
ea26e4ec 1680 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1681}
1682
1683static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1684{
1685 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1686 WARN_ON(adjustment < 0);
1687 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1688 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1689}
1690
d828199e
MT		 1691#ifdef CONFIG_X86_64
1692
a5a1d1c2 1693static u64 read_tsc(void)
d828199e 1694{
a5a1d1c2 1695 u64 ret = (u64)rdtsc_ordered();
03b9730b 1696 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1697
1698 if (likely(ret >= last))
1699 return ret;
1700
1701 /*
1702 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1703 * predictable (it's just a function of time and the likely is
d828199e
MT		 1704 * very likely) and there's a data dependence, so force GCC
1705 * to generate a branch instead. I don't barrier() because
1706 * we don't actually need a barrier, and if this function
1707 * ever gets inlined it will generate worse code.
1708 */
1709 asm volatile ("");
1710 return last;
1711}
1712
b0c39dc6 1713static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1714{
1715 long v;
1716 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1717 u64 tsc_pg_val;
1718
1719 switch (gtod->clock.vclock_mode) {
1720 case VCLOCK_HVCLOCK:
1721 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1722 tsc_timestamp);
1723 if (tsc_pg_val != U64_MAX) {
1724 /* TSC page valid */
1725 *mode = VCLOCK_HVCLOCK;
1726 v = (tsc_pg_val - gtod->clock.cycle_last) &
1727 gtod->clock.mask;
1728 } else {
1729 /* TSC page invalid */
1730 *mode = VCLOCK_NONE;
1731 }
1732 break;
1733 case VCLOCK_TSC:
1734 *mode = VCLOCK_TSC;
1735 *tsc_timestamp = read_tsc();
1736 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1737 gtod->clock.mask;
1738 break;
1739 default:
1740 *mode = VCLOCK_NONE;
1741 }
d828199e 1742
b0c39dc6
VK		 1743 if (*mode == VCLOCK_NONE)
1744 *tsc_timestamp = v = 0;
d828199e 1745
d828199e
MT		 1746 return v * gtod->clock.mult;
1747}
1748
b0c39dc6 1749static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1750{
cbcf2dd3 1751 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1752 unsigned long seq;
d828199e 1753 int mode;
cbcf2dd3 1754 u64 ns;
d828199e 1755
d828199e
MT		 1756 do {
1757 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1758 ns = gtod->nsec_base;
b0c39dc6 1759 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1760 ns >>= gtod->clock.shift;
cbcf2dd3 1761 ns += gtod->boot_ns;
d828199e 1762 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1763 *t = ns;
d828199e
MT		 1764
1765 return mode;
1766}
1767
899a31f5 1768static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1769{
1770 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1771 unsigned long seq;
1772 int mode;
1773 u64 ns;
1774
1775 do {
1776 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1777 ts->tv_sec = gtod->wall_time_sec;
1778 ns = gtod->nsec_base;
b0c39dc6 1779 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1780 ns >>= gtod->clock.shift;
1781 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1782
1783 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1784 ts->tv_nsec = ns;
1785
1786 return mode;
1787}
1788
b0c39dc6
VK		 1789/* returns true if host is using TSC based clocksource */
1790static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1791{
d828199e 1792 /* checked again under seqlock below */
b0c39dc6 1793 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1794 return false;
1795
b0c39dc6
VK		 1796 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1797 tsc_timestamp));
d828199e 1798}
55dd00a7 1799
b0c39dc6 1800/* returns true if host is using TSC based clocksource */
899a31f5 1801static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
b0c39dc6 1802 u64 *tsc_timestamp)
55dd00a7
MT		 1803{
1804 /* checked again under seqlock below */
b0c39dc6 1805 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1806 return false;
1807
b0c39dc6 1808 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1809}
d828199e
MT		 1810#endif
1811
1812/*
1813 *
b48aa97e
MT		 1814 * Assuming a stable TSC across physical CPUS, and a stable TSC
1815 * across virtual CPUs, the following condition is possible.
1816 * Each numbered line represents an event visible to both
d828199e
MT		 1817 * CPUs at the next numbered event.
1818 *
1819 * "timespecX" represents host monotonic time. "tscX" represents
1820 * RDTSC value.
1821 *
1822 * VCPU0 on CPU0 | VCPU1 on CPU1
1823 *
1824 * 1. read timespec0,tsc0
1825 * 2. | timespec1 = timespec0 + N
1826 * | tsc1 = tsc0 + M
1827 * 3. transition to guest | transition to guest
1828 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1829 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1830 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1831 *
1832 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1833 *
1834 * - ret0 < ret1
1835 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1836 * ...
1837 * - 0 < N - M => M < N
1838 *
1839 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1840 * always the case (the difference between two distinct xtime instances
1841 * might be smaller then the difference between corresponding TSC reads,
1842 * when updating guest vcpus pvclock areas).
1843 *
1844 * To avoid that problem, do not allow visibility of distinct
1845 * system_timestamp/tsc_timestamp values simultaneously: use a master
1846 * copy of host monotonic time values. Update that master copy
1847 * in lockstep.
1848 *
b48aa97e 1849 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1850 *
1851 */
1852
1853static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1854{
1855#ifdef CONFIG_X86_64
1856 struct kvm_arch *ka = &kvm->arch;
1857 int vclock_mode;
b48aa97e
MT		 1858 bool host_tsc_clocksource, vcpus_matched;
1859
1860 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1861 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1862
1863 /*
1864 * If the host uses TSC clock, then passthrough TSC as stable
1865 * to the guest.
1866 */
b48aa97e 1867 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1868 &ka->master_kernel_ns,
1869 &ka->master_cycle_now);
1870
16a96021 1871 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1872 && !ka->backwards_tsc_observed
54750f2c 1873 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1874
d828199e
MT		 1875 if (ka->use_master_clock)
1876 atomic_set(&kvm_guest_has_master_clock, 1);
1877
1878 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1879 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1880 vcpus_matched);
d828199e
MT		 1881#endif
1882}
1883
2860c4b1
PB		 1884void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1885{
1886 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1887}
1888
2e762ff7
MT		 1889static void kvm_gen_update_masterclock(struct kvm *kvm)
1890{
1891#ifdef CONFIG_X86_64
1892 int i;
1893 struct kvm_vcpu *vcpu;
1894 struct kvm_arch *ka = &kvm->arch;
1895
1896 spin_lock(&ka->pvclock_gtod_sync_lock);
1897 kvm_make_mclock_inprogress_request(kvm);
1898 /* no guest entries from this point */
1899 pvclock_update_vm_gtod_copy(kvm);
1900
1901 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1902 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1903
1904 /* guest entries allowed */
1905 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1906 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1907
1908 spin_unlock(&ka->pvclock_gtod_sync_lock);
1909#endif
1910}
1911
e891a32e 1912u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1913{
108b249c 1914 struct kvm_arch *ka = &kvm->arch;
8b953440 1915 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1916 u64 ret;
108b249c 1917
8b953440
PB		 1918 spin_lock(&ka->pvclock_gtod_sync_lock);
1919 if (!ka->use_master_clock) {
1920 spin_unlock(&ka->pvclock_gtod_sync_lock);
1921 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1922 }
1923
8b953440
PB		 1924 hv_clock.tsc_timestamp = ka->master_cycle_now;
1925 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1926 spin_unlock(&ka->pvclock_gtod_sync_lock);
1927
e2c2206a
WL		 1928 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1929 get_cpu();
1930
e70b57a6
WL		 1931 if (__this_cpu_read(cpu_tsc_khz)) {
1932 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1933 &hv_clock.tsc_shift,
1934 &hv_clock.tsc_to_system_mul);
1935 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1936 } else
1937 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 1938
1939 put_cpu();
1940
1941 return ret;
108b249c
PB		 1942}
1943
0d6dd2ff
PB		 1944static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1945{
1946 struct kvm_vcpu_arch *vcpu = &v->arch;
1947 struct pvclock_vcpu_time_info guest_hv_clock;
1948
4e335d9e 1949 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1950 &guest_hv_clock, sizeof(guest_hv_clock))))
1951 return;
1952
1953 /* This VCPU is paused, but it's legal for a guest to read another
1954 * VCPU's kvmclock, so we really have to follow the specification where
1955 * it says that version is odd if data is being modified, and even after
1956 * it is consistent.
1957 *
1958 * Version field updates must be kept separate. This is because
1959 * kvm_write_guest_cached might use a "rep movs" instruction, and
1960 * writes within a string instruction are weakly ordered. So there
1961 * are three writes overall.
1962 *
1963 * As a small optimization, only write the version field in the first
1964 * and third write. The vcpu->pv_time cache is still valid, because the
1965 * version field is the first in the struct.
1966 */
1967 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1968
51c4b8bb
LA		 1969 if (guest_hv_clock.version & 1)
1970 ++guest_hv_clock.version; /* first time write, random junk */
1971
0d6dd2ff 1972 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1973 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1974 &vcpu->hv_clock,
1975 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1976
1977 smp_wmb();
1978
1979 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1980 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1981
1982 if (vcpu->pvclock_set_guest_stopped_request) {
1983 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1984 vcpu->pvclock_set_guest_stopped_request = false;
1985 }
1986
1987 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1988
4e335d9e
PB		 1989 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1990 &vcpu->hv_clock,
1991 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1992
1993 smp_wmb();
1994
1995 vcpu->hv_clock.version++;
4e335d9e
PB		 1996 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1997 &vcpu->hv_clock,
1998 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1999}
2000
34c238a1 2001static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 2002{
78db6a50 2003 unsigned long flags, tgt_tsc_khz;
18068523 2004 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 2005 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 2006 s64 kernel_ns;
d828199e 2007 u64 tsc_timestamp, host_tsc;
51d59c6b 2008 u8 pvclock_flags;
d828199e
MT		 2009 bool use_master_clock;
2010
2011 kernel_ns = 0;
2012 host_tsc = 0;
18068523 2013
d828199e
MT		 2014 /*
2015 * If the host uses TSC clock, then passthrough TSC as stable
2016 * to the guest.
2017 */
2018 spin_lock(&ka->pvclock_gtod_sync_lock);
2019 use_master_clock = ka->use_master_clock;
2020 if (use_master_clock) {
2021 host_tsc = ka->master_cycle_now;
2022 kernel_ns = ka->master_kernel_ns;
2023 }
2024 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2025
2026 /* Keep irq disabled to prevent changes to the clock */
2027 local_irq_save(flags);
78db6a50
PB		 2028 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2029 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2030 local_irq_restore(flags);
2031 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2032 return 1;
2033 }
d828199e 2034 if (!use_master_clock) {
4ea1636b 2035 host_tsc = rdtsc();
108b249c 2036 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 2037 }
2038
4ba76538 2039 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2040
c285545f
ZA		 2041 /*
2042 * We may have to catch up the TSC to match elapsed wall clock
2043 * time for two reasons, even if kvmclock is used.
2044 * 1) CPU could have been running below the maximum TSC rate
2045 * 2) Broken TSC compensation resets the base at each VCPU
2046 * entry to avoid unknown leaps of TSC even when running
2047 * again on the same CPU. This may cause apparent elapsed
2048 * time to disappear, and the guest to stand still or run
2049 * very slowly.
2050 */
2051 if (vcpu->tsc_catchup) {
2052 u64 tsc = compute_guest_tsc(v, kernel_ns);
2053 if (tsc > tsc_timestamp) {
f1e2b260 2054 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2055 tsc_timestamp = tsc;
2056 }
50d0a0f9
GH		 2057 }
2058
18068523
GOC		 2059 local_irq_restore(flags);
2060
0d6dd2ff 2061 /* With all the info we got, fill in the values */
18068523 2062
78db6a50
PB		 2063 if (kvm_has_tsc_control)
2064 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2065
2066 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2067 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2068 &vcpu->hv_clock.tsc_shift,
2069 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2070 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2071 }
2072
1d5f066e 2073 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2074 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2075 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2076
d828199e 2077 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2078 pvclock_flags = 0;
d828199e
MT		 2079 if (use_master_clock)
2080 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2081
78c0337a
MT		 2082 vcpu->hv_clock.flags = pvclock_flags;
2083
095cf55d
PB		 2084 if (vcpu->pv_time_enabled)
2085 kvm_setup_pvclock_page(v);
2086 if (v == kvm_get_vcpu(v->kvm, 0))
2087 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2088 return 0;
c8076604
GH		 2089}
2090
0061d53d
MT		 2091/*
2092 * kvmclock updates which are isolated to a given vcpu, such as
2093 * vcpu->cpu migration, should not allow system_timestamp from
2094 * the rest of the vcpus to remain static. Otherwise ntp frequency
2095 * correction applies to one vcpu's system_timestamp but not
2096 * the others.
2097 *
2098 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2099 * We need to rate-limit these requests though, as they can
2100 * considerably slow guests that have a large number of vcpus.
2101 * The time for a remote vcpu to update its kvmclock is bound
2102 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2103 */
2104
7e44e449
AJ		 2105#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2106
2107static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2108{
2109 int i;
7e44e449
AJ		 2110 struct delayed_work *dwork = to_delayed_work(work);
2111 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2112 kvmclock_update_work);
2113 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2114 struct kvm_vcpu *vcpu;
2115
2116 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2117 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2118 kvm_vcpu_kick(vcpu);
2119 }
2120}
2121
7e44e449
AJ		 2122static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2123{
2124 struct kvm *kvm = v->kvm;
2125
105b21bb 2126 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2127 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2128 KVMCLOCK_UPDATE_DELAY);
2129}
2130
332967a3
AJ		 2131#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2132
2133static void kvmclock_sync_fn(struct work_struct *work)
2134{
2135 struct delayed_work *dwork = to_delayed_work(work);
2136 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2137 kvmclock_sync_work);
2138 struct kvm *kvm = container_of(ka, struct kvm, arch);
2139
630994b3
MT		 2140 if (!kvmclock_periodic_sync)
2141 return;
2142
332967a3
AJ		 2143 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2144 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2145 KVMCLOCK_SYNC_PERIOD);
2146}
2147
9ffd986c 2148static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2149{
890ca9ae
HY		 2150 u64 mcg_cap = vcpu->arch.mcg_cap;
2151 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2152 u32 msr = msr_info->index;
2153 u64 data = msr_info->data;
890ca9ae 2154
15c4a640 2155 switch (msr) {
15c4a640 2156 case MSR_IA32_MCG_STATUS:
890ca9ae 2157 vcpu->arch.mcg_status = data;
15c4a640 2158 break;
c7ac679c 2159 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2160 if (!(mcg_cap & MCG_CTL_P))
2161 return 1;
2162 if (data != 0 && data != ~(u64)0)
2163 return -1;
2164 vcpu->arch.mcg_ctl = data;
2165 break;
2166 default:
2167 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2168 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2169 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2170 /* only 0 or all 1s can be written to IA32_MCi_CTL
2171 * some Linux kernels though clear bit 10 in bank 4 to
2172 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2173 * this to avoid an uncatched #GP in the guest
2174 */
890ca9ae 2175 if ((offset & 0x3) == 0 &&
114be429 2176 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2177 return -1;
9ffd986c
WL		 2178 if (!msr_info->host_initiated &&
2179 (offset & 0x3) == 1 && data != 0)
2180 return -1;
890ca9ae
HY		 2181 vcpu->arch.mce_banks[offset] = data;
2182 break;
2183 }
2184 return 1;
2185 }
2186 return 0;
2187}
2188
ffde22ac
ES		 2189static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2190{
2191 struct kvm *kvm = vcpu->kvm;
2192 int lm = is_long_mode(vcpu);
2193 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2194 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2195 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2196 : kvm->arch.xen_hvm_config.blob_size_32;
2197 u32 page_num = data & ~PAGE_MASK;
2198 u64 page_addr = data & PAGE_MASK;
2199 u8 *page;
2200 int r;
2201
2202 r = -E2BIG;
2203 if (page_num >= blob_size)
2204 goto out;
2205 r = -ENOMEM;
ff5c2c03
SL		 2206 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2207 if (IS_ERR(page)) {
2208 r = PTR_ERR(page);
ffde22ac 2209 goto out;
ff5c2c03 2210 }
54bf36aa 2211 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2212 goto out_free;
2213 r = 0;
2214out_free:
2215 kfree(page);
2216out:
2217 return r;
2218}
2219
344d9588
GN		 2220static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2221{
2222 gpa_t gpa = data & ~0x3f;
2223
52a5c155
WL		 2224 /* Bits 3:5 are reserved, Should be zero */
2225 if (data & 0x38)
344d9588
GN		 2226 return 1;
2227
2228 vcpu->arch.apf.msr_val = data;
2229
2230 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2231 kvm_clear_async_pf_completion_queue(vcpu);
2232 kvm_async_pf_hash_reset(vcpu);
2233 return 0;
2234 }
2235
4e335d9e 2236 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2237 sizeof(u32)))
344d9588
GN		 2238 return 1;
2239
6adba527 2240 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2241 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2242 kvm_async_pf_wakeup_all(vcpu);
2243 return 0;
2244}
2245
12f9a48f
GC		 2246static void kvmclock_reset(struct kvm_vcpu *vcpu)
2247{
0b79459b 2248 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2249}
2250
f38a7b75
WL		 2251static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2252{
2253 ++vcpu->stat.tlb_flush;
2254 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2255}
2256
c9aaa895
GC		 2257static void record_steal_time(struct kvm_vcpu *vcpu)
2258{
2259 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2260 return;
2261
4e335d9e 2262 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2263 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2264 return;
2265
f38a7b75
WL		 2266 /*
2267 * Doing a TLB flush here, on the guest's behalf, can avoid
2268 * expensive IPIs.
2269 */
2270 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2271 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2272
35f3fae1
WL		 2273 if (vcpu->arch.st.steal.version & 1)
2274 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2275
2276 vcpu->arch.st.steal.version += 1;
2277
4e335d9e 2278 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2279 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2280
2281 smp_wmb();
2282
c54cdf14
LC		 2283 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2284 vcpu->arch.st.last_steal;
2285 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2286
4e335d9e 2287 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2288 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2289
2290 smp_wmb();
2291
2292 vcpu->arch.st.steal.version += 1;
c9aaa895 2293
4e335d9e 2294 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2295 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2296}
2297
8fe8ab46 2298int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2299{
5753785f 2300 bool pr = false;
8fe8ab46
WA		 2301 u32 msr = msr_info->index;
2302 u64 data = msr_info->data;
5753785f 2303
15c4a640 2304 switch (msr) {
2e32b719 2305 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2306 case MSR_IA32_UCODE_WRITE:
2307 case MSR_VM_HSAVE_PA:
2308 case MSR_AMD64_PATCH_LOADER:
2309 case MSR_AMD64_BU_CFG2:
405a353a 2310 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2311 break;
2312
518e7b94
WL		 2313 case MSR_IA32_UCODE_REV:
2314 if (msr_info->host_initiated)
2315 vcpu->arch.microcode_version = data;
2316 break;
15c4a640 2317 case MSR_EFER:
b69e8cae 2318 return set_efer(vcpu, data);
8f1589d9
AP		 2319 case MSR_K7_HWCR:
2320 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2321 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2322 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2323 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2324 if (data != 0) {
a737f256
CD		 2325 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2326 data);
8f1589d9
AP		 2327 return 1;
2328 }
15c4a640 2329 break;
f7c6d140
AP		 2330 case MSR_FAM10H_MMIO_CONF_BASE:
2331 if (data != 0) {
a737f256
CD		 2332 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2333 "0x%llx\n", data);
f7c6d140
AP		 2334 return 1;
2335 }
15c4a640 2336 break;
b5e2fec0
AG		 2337 case MSR_IA32_DEBUGCTLMSR:
2338 if (!data) {
2339 /* We support the non-activated case already */
2340 break;
2341 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2342 /* Values other than LBR and BTF are vendor-specific,
2343 thus reserved and should throw a #GP */
2344 return 1;
2345 }
a737f256
CD		 2346 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2347 __func__, data);
b5e2fec0 2348 break;
9ba075a6 2349 case 0x200 ... 0x2ff:
ff53604b 2350 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2351 case MSR_IA32_APICBASE:
58cb628d 2352 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2353 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2354 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2355 case MSR_IA32_TSCDEADLINE:
2356 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2357 break;
ba904635 2358 case MSR_IA32_TSC_ADJUST:
d6321d49 2359 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2360 if (!msr_info->host_initiated) {
d913b904 2361 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2362 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2363 }
2364 vcpu->arch.ia32_tsc_adjust_msr = data;
2365 }
2366 break;
15c4a640 2367 case MSR_IA32_MISC_ENABLE:
ad312c7c 2368 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2369 break;
64d60670
PB		 2370 case MSR_IA32_SMBASE:
2371 if (!msr_info->host_initiated)
2372 return 1;
2373 vcpu->arch.smbase = data;
2374 break;
dd259935
PB		 2375 case MSR_IA32_TSC:
2376 kvm_write_tsc(vcpu, msr_info);
2377 break;
52797bf9
LA		 2378 case MSR_SMI_COUNT:
2379 if (!msr_info->host_initiated)
2380 return 1;
2381 vcpu->arch.smi_count = data;
2382 break;
11c6bffa 2383 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2384 case MSR_KVM_WALL_CLOCK:
2385 vcpu->kvm->arch.wall_clock = data;
2386 kvm_write_wall_clock(vcpu->kvm, data);
2387 break;
11c6bffa 2388 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2389 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2390 struct kvm_arch *ka = &vcpu->kvm->arch;
2391
12f9a48f 2392 kvmclock_reset(vcpu);
18068523 2393
54750f2c
MT		 2394 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2395 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2396
2397 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2398 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2399
2400 ka->boot_vcpu_runs_old_kvmclock = tmp;
2401 }
2402
18068523 2403 vcpu->arch.time = data;
0061d53d 2404 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2405
2406 /* we verify if the enable bit is set... */
2407 if (!(data & 1))
2408 break;
2409
4e335d9e 2410 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2411 &vcpu->arch.pv_time, data & ~1ULL,
2412 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2413 vcpu->arch.pv_time_enabled = false;
2414 else
2415 vcpu->arch.pv_time_enabled = true;
32cad84f 2416
18068523
GOC		 2417 break;
2418 }
344d9588
GN		 2419 case MSR_KVM_ASYNC_PF_EN:
2420 if (kvm_pv_enable_async_pf(vcpu, data))
2421 return 1;
2422 break;
c9aaa895
GC		 2423 case MSR_KVM_STEAL_TIME:
2424
2425 if (unlikely(!sched_info_on()))
2426 return 1;
2427
2428 if (data & KVM_STEAL_RESERVED_MASK)
2429 return 1;
2430
4e335d9e 2431 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2432 data & KVM_STEAL_VALID_BITS,
2433 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2434 return 1;
2435
2436 vcpu->arch.st.msr_val = data;
2437
2438 if (!(data & KVM_MSR_ENABLED))
2439 break;
2440
c9aaa895
GC		 2441 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2442
2443 break;
ae7a2a3f
MT		 2444 case MSR_KVM_PV_EOI_EN:
2445 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2446 return 1;
2447 break;
c9aaa895 2448
890ca9ae
HY		 2449 case MSR_IA32_MCG_CTL:
2450 case MSR_IA32_MCG_STATUS:
81760dcc 2451 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2452 return set_msr_mce(vcpu, msr_info);
71db6023 2453
6912ac32
WH		 2454 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2455 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2456 pr = true; /* fall through */
2457 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2458 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2459 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2460 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2461
2462 if (pr || data != 0)
a737f256
CD		 2463 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2464 "0x%x data 0x%llx\n", msr, data);
5753785f 2465 break;
84e0cefa
JS		 2466 case MSR_K7_CLK_CTL:
2467 /*
2468 * Ignore all writes to this no longer documented MSR.
2469 * Writes are only relevant for old K7 processors,
2470 * all pre-dating SVM, but a recommended workaround from
4a969980 2471 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2472 * affected processor models on the command line, hence
2473 * the need to ignore the workaround.
2474 */
2475 break;
55cd8e5a 2476 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2477 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2478 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2479 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2480 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2481 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2482 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2483 return kvm_hv_set_msr_common(vcpu, msr, data,
2484 msr_info->host_initiated);
91c9c3ed 2485 case MSR_IA32_BBL_CR_CTL3:
2486 /* Drop writes to this legacy MSR -- see rdmsr
2487 * counterpart for further detail.
2488 */
fab0aa3b
EM		 2489 if (report_ignored_msrs)
2490 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2491 msr, data);
91c9c3ed 2492 break;
2b036c6b 2493 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2494 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2495 return 1;
2496 vcpu->arch.osvw.length = data;
2497 break;
2498 case MSR_AMD64_OSVW_STATUS:
d6321d49 2499 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2500 return 1;
2501 vcpu->arch.osvw.status = data;
2502 break;
db2336a8
KH		 2503 case MSR_PLATFORM_INFO:
2504 if (!msr_info->host_initiated ||
2505 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2506 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2507 cpuid_fault_enabled(vcpu)))
2508 return 1;
2509 vcpu->arch.msr_platform_info = data;
2510 break;
2511 case MSR_MISC_FEATURES_ENABLES:
2512 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2513 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2514 !supports_cpuid_fault(vcpu)))
2515 return 1;
2516 vcpu->arch.msr_misc_features_enables = data;
2517 break;
15c4a640 2518 default:
ffde22ac
ES		 2519 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2520 return xen_hvm_config(vcpu, data);
c6702c9d 2521 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2522 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2523 if (!ignore_msrs) {
ae0f5499 2524 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2525 msr, data);
ed85c068
AP		 2526 return 1;
2527 } else {
fab0aa3b
EM		 2528 if (report_ignored_msrs)
2529 vcpu_unimpl(vcpu,
2530 "ignored wrmsr: 0x%x data 0x%llx\n",
2531 msr, data);
ed85c068
AP		 2532 break;
2533 }
15c4a640
CO		 2534 }
2535 return 0;
2536}
2537EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2538
2539
2540/*
2541 * Reads an msr value (of 'msr_index') into 'pdata'.
2542 * Returns 0 on success, non-0 otherwise.
2543 * Assumes vcpu_load() was already called.
2544 */
609e36d3 2545int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2546{
609e36d3 2547 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2548}
ff651cb6 2549EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2550
890ca9ae 2551static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2552{
2553 u64 data;
890ca9ae
HY		 2554 u64 mcg_cap = vcpu->arch.mcg_cap;
2555 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2556
2557 switch (msr) {
15c4a640
CO		 2558 case MSR_IA32_P5_MC_ADDR:
2559 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2560 data = 0;
2561 break;
15c4a640 2562 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2563 data = vcpu->arch.mcg_cap;
2564 break;
c7ac679c 2565 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2566 if (!(mcg_cap & MCG_CTL_P))
2567 return 1;
2568 data = vcpu->arch.mcg_ctl;
2569 break;
2570 case MSR_IA32_MCG_STATUS:
2571 data = vcpu->arch.mcg_status;
2572 break;
2573 default:
2574 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2575 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2576 u32 offset = msr - MSR_IA32_MC0_CTL;
2577 data = vcpu->arch.mce_banks[offset];
2578 break;
2579 }
2580 return 1;
2581 }
2582 *pdata = data;
2583 return 0;
2584}
2585
609e36d3 2586int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2587{
609e36d3 2588 switch (msr_info->index) {
890ca9ae 2589 case MSR_IA32_PLATFORM_ID:
15c4a640 2590 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2591 case MSR_IA32_DEBUGCTLMSR:
2592 case MSR_IA32_LASTBRANCHFROMIP:
2593 case MSR_IA32_LASTBRANCHTOIP:
2594 case MSR_IA32_LASTINTFROMIP:
2595 case MSR_IA32_LASTINTTOIP:
60af2ecd 2596 case MSR_K8_SYSCFG:
3afb1121
PB		 2597 case MSR_K8_TSEG_ADDR:
2598 case MSR_K8_TSEG_MASK:
60af2ecd 2599 case MSR_K7_HWCR:
61a6bd67 2600 case MSR_VM_HSAVE_PA:
1fdbd48c 2601 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2602 case MSR_AMD64_NB_CFG:
f7c6d140 2603 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2604 case MSR_AMD64_BU_CFG2:
0c2df2a1 2605 case MSR_IA32_PERF_CTL:
405a353a 2606 case MSR_AMD64_DC_CFG:
609e36d3 2607 msr_info->data = 0;
15c4a640 2608 break;
c51eb52b 2609 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2610 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2611 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2612 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2613 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2614 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2615 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2616 msr_info->data = 0;
5753785f 2617 break;
742bc670 2618 case MSR_IA32_UCODE_REV:
518e7b94 2619 msr_info->data = vcpu->arch.microcode_version;
742bc670 2620 break;
dd259935
PB		 2621 case MSR_IA32_TSC:
2622 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2623 break;
9ba075a6 2624 case MSR_MTRRcap:
9ba075a6 2625 case 0x200 ... 0x2ff:
ff53604b 2626 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2627 case 0xcd: /* fsb frequency */
609e36d3 2628 msr_info->data = 3;
15c4a640 2629 break;
7b914098
JS		 2630 /*
2631 * MSR_EBC_FREQUENCY_ID
2632 * Conservative value valid for even the basic CPU models.
2633 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2634 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2635 * and 266MHz for model 3, or 4. Set Core Clock
2636 * Frequency to System Bus Frequency Ratio to 1 (bits
2637 * 31:24) even though these are only valid for CPU
2638 * models > 2, however guests may end up dividing or
2639 * multiplying by zero otherwise.
2640 */
2641 case MSR_EBC_FREQUENCY_ID:
609e36d3 2642 msr_info->data = 1 << 24;
7b914098 2643 break;
15c4a640 2644 case MSR_IA32_APICBASE:
609e36d3 2645 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2646 break;
0105d1a5 2647 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2648 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2649 break;
a3e06bbe 2650 case MSR_IA32_TSCDEADLINE:
609e36d3 2651 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2652 break;
ba904635 2653 case MSR_IA32_TSC_ADJUST:
609e36d3 2654 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2655 break;
15c4a640 2656 case MSR_IA32_MISC_ENABLE:
609e36d3 2657 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2658 break;
64d60670
PB		 2659 case MSR_IA32_SMBASE:
2660 if (!msr_info->host_initiated)
2661 return 1;
2662 msr_info->data = vcpu->arch.smbase;
15c4a640 2663 break;
52797bf9
LA		 2664 case MSR_SMI_COUNT:
2665 msr_info->data = vcpu->arch.smi_count;
2666 break;
847f0ad8
AG		 2667 case MSR_IA32_PERF_STATUS:
2668 /* TSC increment by tick */
609e36d3 2669 msr_info->data = 1000ULL;
847f0ad8 2670 /* CPU multiplier */
b0996ae4 2671 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2672 break;
15c4a640 2673 case MSR_EFER:
609e36d3 2674 msr_info->data = vcpu->arch.efer;
15c4a640 2675 break;
18068523 2676 case MSR_KVM_WALL_CLOCK:
11c6bffa 2677 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2678 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2679 break;
2680 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2681 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2682 msr_info->data = vcpu->arch.time;
18068523 2683 break;
344d9588 2684 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2685 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2686 break;
c9aaa895 2687 case MSR_KVM_STEAL_TIME:
609e36d3 2688 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2689 break;
1d92128f 2690 case MSR_KVM_PV_EOI_EN:
609e36d3 2691 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2692 break;
890ca9ae
HY		 2693 case MSR_IA32_P5_MC_ADDR:
2694 case MSR_IA32_P5_MC_TYPE:
2695 case MSR_IA32_MCG_CAP:
2696 case MSR_IA32_MCG_CTL:
2697 case MSR_IA32_MCG_STATUS:
81760dcc 2698 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2699 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2700 case MSR_K7_CLK_CTL:
2701 /*
2702 * Provide expected ramp-up count for K7. All other
2703 * are set to zero, indicating minimum divisors for
2704 * every field.
2705 *
2706 * This prevents guest kernels on AMD host with CPU
2707 * type 6, model 8 and higher from exploding due to
2708 * the rdmsr failing.
2709 */
609e36d3 2710 msr_info->data = 0x20000000;
84e0cefa 2711 break;
55cd8e5a 2712 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2713 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2714 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2715 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2716 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2717 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2718 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887
AS		 2719 return kvm_hv_get_msr_common(vcpu,
2720 msr_info->index, &msr_info->data);
55cd8e5a 2721 break;
91c9c3ed 2722 case MSR_IA32_BBL_CR_CTL3:
2723 /* This legacy MSR exists but isn't fully documented in current
2724 * silicon. It is however accessed by winxp in very narrow
2725 * scenarios where it sets bit #19, itself documented as
2726 * a "reserved" bit. Best effort attempt to source coherent
2727 * read data here should the balance of the register be
2728 * interpreted by the guest:
2729 *
2730 * L2 cache control register 3: 64GB range, 256KB size,
2731 * enabled, latency 0x1, configured
2732 */
609e36d3 2733 msr_info->data = 0xbe702111;
91c9c3ed 2734 break;
2b036c6b 2735 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2736 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2737 return 1;
609e36d3 2738 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2739 break;
2740 case MSR_AMD64_OSVW_STATUS:
d6321d49 2741 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2742 return 1;
609e36d3 2743 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2744 break;
db2336a8
KH		 2745 case MSR_PLATFORM_INFO:
2746 msr_info->data = vcpu->arch.msr_platform_info;
2747 break;
2748 case MSR_MISC_FEATURES_ENABLES:
2749 msr_info->data = vcpu->arch.msr_misc_features_enables;
2750 break;
15c4a640 2751 default:
c6702c9d 2752 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2753 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2754 if (!ignore_msrs) {
ae0f5499
BD		 2755 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2756 msr_info->index);
ed85c068
AP		 2757 return 1;
2758 } else {
fab0aa3b
EM		 2759 if (report_ignored_msrs)
2760 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2761 msr_info->index);
609e36d3 2762 msr_info->data = 0;
ed85c068
AP		 2763 }
2764 break;
15c4a640 2765 }
15c4a640
CO		 2766 return 0;
2767}
2768EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2769
313a3dc7
CO		 2770/*
2771 * Read or write a bunch of msrs. All parameters are kernel addresses.
2772 *
2773 * @return number of msrs set successfully.
2774 */
2775static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2776 struct kvm_msr_entry *entries,
2777 int (*do_msr)(struct kvm_vcpu *vcpu,
2778 unsigned index, u64 *data))
2779{
801e459a 2780 int i;
313a3dc7 2781
313a3dc7
CO		 2782 for (i = 0; i < msrs->nmsrs; ++i)
2783 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2784 break;
2785
313a3dc7
CO		 2786 return i;
2787}
2788
2789/*
2790 * Read or write a bunch of msrs. Parameters are user addresses.
2791 *
2792 * @return number of msrs set successfully.
2793 */
2794static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2795 int (*do_msr)(struct kvm_vcpu *vcpu,
2796 unsigned index, u64 *data),
2797 int writeback)
2798{
2799 struct kvm_msrs msrs;
2800 struct kvm_msr_entry *entries;
2801 int r, n;
2802 unsigned size;
2803
2804 r = -EFAULT;
2805 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2806 goto out;
2807
2808 r = -E2BIG;
2809 if (msrs.nmsrs >= MAX_IO_MSRS)
2810 goto out;
2811
313a3dc7 2812 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2813 entries = memdup_user(user_msrs->entries, size);
2814 if (IS_ERR(entries)) {
2815 r = PTR_ERR(entries);
313a3dc7 2816 goto out;
ff5c2c03 2817 }
313a3dc7
CO		 2818
2819 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2820 if (r < 0)
2821 goto out_free;
2822
2823 r = -EFAULT;
2824 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2825 goto out_free;
2826
2827 r = n;
2828
2829out_free:
7a73c028 2830 kfree(entries);
313a3dc7
CO		 2831out:
2832 return r;
2833}
2834
4d5422ce
WL		 2835static inline bool kvm_can_mwait_in_guest(void)
2836{
2837 return boot_cpu_has(X86_FEATURE_MWAIT) &&
8e9b29b6
KA		 2838 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
2839 boot_cpu_has(X86_FEATURE_ARAT);
4d5422ce
WL		 2840}
2841
784aa3d7 2842int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2 2843{
4d5422ce 2844 int r = 0;
018d00d2
ZX		 2845
2846 switch (ext) {
2847 case KVM_CAP_IRQCHIP:
2848 case KVM_CAP_HLT:
2849 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2850 case KVM_CAP_SET_TSS_ADDR:
07716717 2851 case KVM_CAP_EXT_CPUID:
9c15bb1d 2852 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2853 case KVM_CAP_CLOCKSOURCE:
7837699f 2854 case KVM_CAP_PIT:
a28e4f5a 2855 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2856 case KVM_CAP_MP_STATE:
ed848624 2857 case KVM_CAP_SYNC_MMU:
a355c85c 2858 case KVM_CAP_USER_NMI:
52d939a0 2859 case KVM_CAP_REINJECT_CONTROL:
4925663a 2860 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2861 case KVM_CAP_IOEVENTFD:
f848a5a8 2862 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2863 case KVM_CAP_PIT2:
e9f42757 2864 case KVM_CAP_PIT_STATE2:
b927a3ce 2865 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2866 case KVM_CAP_XEN_HVM:
3cfc3092 2867 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2868 case KVM_CAP_HYPERV:
10388a07 2869 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2870 case KVM_CAP_HYPERV_SPIN:
5c919412 2871 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2872 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2873 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 2874 case KVM_CAP_HYPERV_EVENTFD:
c1aea919 2875 case KVM_CAP_HYPERV_TLBFLUSH:
ab9f4ecb 2876 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2877 case KVM_CAP_DEBUGREGS:
d2be1651 2878 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2879 case KVM_CAP_XSAVE:
344d9588 2880 case KVM_CAP_ASYNC_PF:
92a1f12d 2881 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2882 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2883 case KVM_CAP_READONLY_MEM:
5f66b620 2884 case KVM_CAP_HYPERV_TIME:
100943c5 2885 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2886 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2887 case KVM_CAP_ENABLE_CAP_VM:
2888 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2889 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2890 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2891 case KVM_CAP_IMMEDIATE_EXIT:
801e459a 2892 case KVM_CAP_GET_MSR_FEATURES:
018d00d2
ZX		 2893 r = 1;
2894 break;
01643c51
KH		 2895 case KVM_CAP_SYNC_REGS:
2896 r = KVM_SYNC_X86_VALID_FIELDS;
2897 break;
e3fd9a93
PB		 2898 case KVM_CAP_ADJUST_CLOCK:
2899 r = KVM_CLOCK_TSC_STABLE;
2900 break;
4d5422ce 2901 case KVM_CAP_X86_DISABLE_EXITS:
b31c114b 2902 r |= KVM_X86_DISABLE_EXITS_HTL | KVM_X86_DISABLE_EXITS_PAUSE;
4d5422ce
WL		 2903 if(kvm_can_mwait_in_guest())
2904 r |= KVM_X86_DISABLE_EXITS_MWAIT;
668fffa3 2905 break;
6d396b55
PB		 2906 case KVM_CAP_X86_SMM:
2907 /* SMBASE is usually relocated above 1M on modern chipsets,
2908 * and SMM handlers might indeed rely on 4G segment limits,
2909 * so do not report SMM to be available if real mode is
2910 * emulated via vm86 mode. Still, do not go to great lengths
2911 * to avoid userspace's usage of the feature, because it is a
2912 * fringe case that is not enabled except via specific settings
2913 * of the module parameters.
2914 */
2915 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2916 break;
774ead3a
AK		 2917 case KVM_CAP_VAPIC:
2918 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2919 break;
f725230a 2920 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2921 r = KVM_SOFT_MAX_VCPUS;
2922 break;
2923 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2924 r = KVM_MAX_VCPUS;
2925 break;
a988b910 2926 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2927 r = KVM_USER_MEM_SLOTS;
a988b910 2928 break;
a68a6a72
MT		 2929 case KVM_CAP_PV_MMU: /* obsolete */
2930 r = 0;
2f333bcb 2931 break;
890ca9ae
HY		 2932 case KVM_CAP_MCE:
2933 r = KVM_MAX_MCE_BANKS;
2934 break;
2d5b5a66 2935 case KVM_CAP_XCRS:
d366bf7e 2936 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2937 break;
92a1f12d
JR		 2938 case KVM_CAP_TSC_CONTROL:
2939 r = kvm_has_tsc_control;
2940 break;
37131313
RK		 2941 case KVM_CAP_X2APIC_API:
2942 r = KVM_X2APIC_API_VALID_FLAGS;
2943 break;
018d00d2 2944 default:
018d00d2
ZX		 2945 break;
2946 }
2947 return r;
2948
2949}
2950
043405e1
CO		 2951long kvm_arch_dev_ioctl(struct file *filp,
2952 unsigned int ioctl, unsigned long arg)
2953{
2954 void __user *argp = (void __user *)arg;
2955 long r;
2956
2957 switch (ioctl) {
2958 case KVM_GET_MSR_INDEX_LIST: {
2959 struct kvm_msr_list __user *user_msr_list = argp;
2960 struct kvm_msr_list msr_list;
2961 unsigned n;
2962
2963 r = -EFAULT;
2964 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2965 goto out;
2966 n = msr_list.nmsrs;
62ef68bb 2967 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2968 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2969 goto out;
2970 r = -E2BIG;
e125e7b6 2971 if (n < msr_list.nmsrs)
043405e1
CO		 2972 goto out;
2973 r = -EFAULT;
2974 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2975 num_msrs_to_save * sizeof(u32)))
2976 goto out;
e125e7b6 2977 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2978 &emulated_msrs,
62ef68bb 2979 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2980 goto out;
2981 r = 0;
2982 break;
2983 }
9c15bb1d
BP		 2984 case KVM_GET_SUPPORTED_CPUID:
2985 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2986 struct kvm_cpuid2 __user *cpuid_arg = argp;
2987 struct kvm_cpuid2 cpuid;
2988
2989 r = -EFAULT;
2990 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2991 goto out;
9c15bb1d
BP		 2992
2993 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2994 ioctl);
674eea0f
AK		 2995 if (r)
2996 goto out;
2997
2998 r = -EFAULT;
2999 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3000 goto out;
3001 r = 0;
3002 break;
3003 }
890ca9ae 3004 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 3005 r = -EFAULT;
c45dcc71
AR		 3006 if (copy_to_user(argp, &kvm_mce_cap_supported,
3007 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 3008 goto out;
3009 r = 0;
3010 break;
801e459a
TL		 3011 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3012 struct kvm_msr_list __user *user_msr_list = argp;
3013 struct kvm_msr_list msr_list;
3014 unsigned int n;
3015
3016 r = -EFAULT;
3017 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3018 goto out;
3019 n = msr_list.nmsrs;
3020 msr_list.nmsrs = num_msr_based_features;
3021 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3022 goto out;
3023 r = -E2BIG;
3024 if (n < msr_list.nmsrs)
3025 goto out;
3026 r = -EFAULT;
3027 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3028 num_msr_based_features * sizeof(u32)))
3029 goto out;
3030 r = 0;
3031 break;
3032 }
3033 case KVM_GET_MSRS:
3034 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3035 break;
890ca9ae 3036 }
043405e1
CO		 3037 default:
3038 r = -EINVAL;
3039 }
3040out:
3041 return r;
3042}
3043
f5f48ee1
SY		 3044static void wbinvd_ipi(void *garbage)
3045{
3046 wbinvd();
3047}
3048
3049static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3050{
e0f0bbc5 3051 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3052}
3053
313a3dc7
CO		 3054void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3055{
f5f48ee1
SY		 3056 /* Address WBINVD may be executed by guest */
3057 if (need_emulate_wbinvd(vcpu)) {
3058 if (kvm_x86_ops->has_wbinvd_exit())
3059 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3060 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3061 smp_call_function_single(vcpu->cpu,
3062 wbinvd_ipi, NULL, 1);
3063 }
3064
313a3dc7 3065 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3066
0dd6a6ed
ZA		 3067 /* Apply any externally detected TSC adjustments (due to suspend) */
3068 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3069 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3070 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3071 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3072 }
8f6055cb 3073
b0c39dc6 3074 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3075 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3076 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3077 if (tsc_delta < 0)
3078 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3079
b0c39dc6 3080 if (kvm_check_tsc_unstable()) {
07c1419a 3081 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3082 vcpu->arch.last_guest_tsc);
a545ab6a 3083 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3084 vcpu->arch.tsc_catchup = 1;
c285545f 3085 }
a749e247
PB		 3086
3087 if (kvm_lapic_hv_timer_in_use(vcpu))
3088 kvm_lapic_restart_hv_timer(vcpu);
3089
d98d07ca
MT		 3090 /*
3091 * On a host with synchronized TSC, there is no need to update
3092 * kvmclock on vcpu->cpu migration
3093 */
3094 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3095 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3096 if (vcpu->cpu != cpu)
1bd2009e 3097 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3098 vcpu->cpu = cpu;
6b7d7e76 3099 }
c9aaa895 3100
c9aaa895 3101 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3102}
3103
0b9f6c46
PX		 3104static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3105{
3106 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3107 return;
3108
fa55eedd 3109 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3110
4e335d9e 3111 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3112 &vcpu->arch.st.steal.preempted,
3113 offsetof(struct kvm_steal_time, preempted),
3114 sizeof(vcpu->arch.st.steal.preempted));
3115}
3116
313a3dc7
CO		 3117void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3118{
cc0d907c 3119 int idx;
de63ad4c
LM		 3120
3121 if (vcpu->preempted)
3122 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3123
931f261b
AA		 3124 /*
3125 * Disable page faults because we're in atomic context here.
3126 * kvm_write_guest_offset_cached() would call might_fault()
3127 * that relies on pagefault_disable() to tell if there's a
3128 * bug. NOTE: the write to guest memory may not go through if
3129 * during postcopy live migration or if there's heavy guest
3130 * paging.
3131 */
3132 pagefault_disable();
cc0d907c
AA		 3133 /*
3134 * kvm_memslots() will be called by
3135 * kvm_write_guest_offset_cached() so take the srcu lock.
3136 */
3137 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3138 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3139 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3140 pagefault_enable();
02daab21 3141 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3142 vcpu->arch.last_host_tsc = rdtsc();
efdab992
WL		 3143 /*
3144 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3145 * on every vmexit, but if not, we might have a stale dr6 from the
3146 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3147 */
3148 set_debugreg(0, 6);
313a3dc7
CO		 3149}
3150
313a3dc7
CO		 3151static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3152 struct kvm_lapic_state *s)
3153{
fa59cc00 3154 if (vcpu->arch.apicv_active)
d62caabb
AS		 3155 kvm_x86_ops->sync_pir_to_irr(vcpu);
3156
a92e2543 3157 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3158}
3159
3160static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3161 struct kvm_lapic_state *s)
3162{
a92e2543
RK		 3163 int r;
3164
3165 r = kvm_apic_set_state(vcpu, s);
3166 if (r)
3167 return r;
cb142eb7 3168 update_cr8_intercept(vcpu);
313a3dc7
CO		 3169
3170 return 0;
3171}
3172
127a457a
MG		 3173static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3174{
3175 return (!lapic_in_kernel(vcpu) ||
3176 kvm_apic_accept_pic_intr(vcpu));
3177}
3178
782d422b
MG		 3179/*
3180 * if userspace requested an interrupt window, check that the
3181 * interrupt window is open.
3182 *
3183 * No need to exit to userspace if we already have an interrupt queued.
3184 */
3185static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3186{
3187 return kvm_arch_interrupt_allowed(vcpu) &&
3188 !kvm_cpu_has_interrupt(vcpu) &&
3189 !kvm_event_needs_reinjection(vcpu) &&
3190 kvm_cpu_accept_dm_intr(vcpu);
3191}
3192
f77bc6a4
ZX		 3193static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3194 struct kvm_interrupt *irq)
3195{
02cdb50f 3196 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3197 return -EINVAL;
1c1a9ce9
SR		 3198
3199 if (!irqchip_in_kernel(vcpu->kvm)) {
3200 kvm_queue_interrupt(vcpu, irq->irq, false);
3201 kvm_make_request(KVM_REQ_EVENT, vcpu);
3202 return 0;
3203 }
3204
3205 /*
3206 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3207 * fail for in-kernel 8259.
3208 */
3209 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3210 return -ENXIO;
f77bc6a4 3211
1c1a9ce9
SR		 3212 if (vcpu->arch.pending_external_vector != -1)
3213 return -EEXIST;
f77bc6a4 3214
1c1a9ce9 3215 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3216 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3217 return 0;
3218}
3219
c4abb7c9
JK		 3220static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3221{
c4abb7c9 3222 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3223
3224 return 0;
3225}
3226
f077825a
PB		 3227static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3228{
64d60670
PB		 3229 kvm_make_request(KVM_REQ_SMI, vcpu);
3230
f077825a
PB		 3231 return 0;
3232}
3233
b209749f
AK		 3234static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3235 struct kvm_tpr_access_ctl *tac)
3236{
3237 if (tac->flags)
3238 return -EINVAL;
3239 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3240 return 0;
3241}
3242
890ca9ae
HY		 3243static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3244 u64 mcg_cap)
3245{
3246 int r;
3247 unsigned bank_num = mcg_cap & 0xff, bank;
3248
3249 r = -EINVAL;
a9e38c3e 3250 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3251 goto out;
c45dcc71 3252 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3253 goto out;
3254 r = 0;
3255 vcpu->arch.mcg_cap = mcg_cap;
3256 /* Init IA32_MCG_CTL to all 1s */
3257 if (mcg_cap & MCG_CTL_P)
3258 vcpu->arch.mcg_ctl = ~(u64)0;
3259 /* Init IA32_MCi_CTL to all 1s */
3260 for (bank = 0; bank < bank_num; bank++)
3261 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3262
3263 if (kvm_x86_ops->setup_mce)
3264 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3265out:
3266 return r;
3267}
3268
3269static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3270 struct kvm_x86_mce *mce)
3271{
3272 u64 mcg_cap = vcpu->arch.mcg_cap;
3273 unsigned bank_num = mcg_cap & 0xff;
3274 u64 *banks = vcpu->arch.mce_banks;
3275
3276 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3277 return -EINVAL;
3278 /*
3279 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3280 * reporting is disabled
3281 */
3282 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3283 vcpu->arch.mcg_ctl != ~(u64)0)
3284 return 0;
3285 banks += 4 * mce->bank;
3286 /*
3287 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3288 * reporting is disabled for the bank
3289 */
3290 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3291 return 0;
3292 if (mce->status & MCI_STATUS_UC) {
3293 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3294 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3295 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3296 return 0;
3297 }
3298 if (banks[1] & MCI_STATUS_VAL)
3299 mce->status |= MCI_STATUS_OVER;
3300 banks[2] = mce->addr;
3301 banks[3] = mce->misc;
3302 vcpu->arch.mcg_status = mce->mcg_status;
3303 banks[1] = mce->status;
3304 kvm_queue_exception(vcpu, MC_VECTOR);
3305 } else if (!(banks[1] & MCI_STATUS_VAL)
3306 || !(banks[1] & MCI_STATUS_UC)) {
3307 if (banks[1] & MCI_STATUS_VAL)
3308 mce->status |= MCI_STATUS_OVER;
3309 banks[2] = mce->addr;
3310 banks[3] = mce->misc;
3311 banks[1] = mce->status;
3312 } else
3313 banks[1] |= MCI_STATUS_OVER;
3314 return 0;
3315}
3316
3cfc3092
JK		 3317static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3318 struct kvm_vcpu_events *events)
3319{
7460fb4a 3320 process_nmi(vcpu);
664f8e26
WL		 3321 /*
3322 * FIXME: pass injected and pending separately. This is only
3323 * needed for nested virtualization, whose state cannot be
3324 * migrated yet. For now we can combine them.
3325 */
03b82a30 3326 events->exception.injected =
664f8e26
WL		 3327 (vcpu->arch.exception.pending ||
3328 vcpu->arch.exception.injected) &&
03b82a30 3329 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3330 events->exception.nr = vcpu->arch.exception.nr;
3331 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3332 events->exception.pad = 0;
3cfc3092
JK		 3333 events->exception.error_code = vcpu->arch.exception.error_code;
3334
03b82a30 3335 events->interrupt.injected =
04140b41 3336 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3cfc3092 3337 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3338 events->interrupt.soft = 0;
37ccdcbe 3339 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3340
3341 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3342 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3343 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3344 events->nmi.pad = 0;
3cfc3092 3345
66450a21 3346 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3347
f077825a
PB		 3348 events->smi.smm = is_smm(vcpu);
3349 events->smi.pending = vcpu->arch.smi_pending;
3350 events->smi.smm_inside_nmi =
3351 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3352 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3353
dab4b911 3354 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3355 | KVM_VCPUEVENT_VALID_SHADOW
3356 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3357 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3358}
3359
6ef4e07e
XG		 3360static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3361
3cfc3092
JK		 3362static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3363 struct kvm_vcpu_events *events)
3364{
dab4b911 3365 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3366 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3367 | KVM_VCPUEVENT_VALID_SHADOW
3368 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3369 return -EINVAL;
3370
78e546c8 3371 if (events->exception.injected &&
28d06353
JM		 3372 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3373 is_guest_mode(vcpu)))
78e546c8
PB		 3374 return -EINVAL;
3375
28bf2888
DH		 3376 /* INITs are latched while in SMM */
3377 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3378 (events->smi.smm || events->smi.pending) &&
3379 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3380 return -EINVAL;
3381
7460fb4a 3382 process_nmi(vcpu);
664f8e26 3383 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3384 vcpu->arch.exception.pending = events->exception.injected;
3385 vcpu->arch.exception.nr = events->exception.nr;
3386 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3387 vcpu->arch.exception.error_code = events->exception.error_code;
3388
04140b41 3389 vcpu->arch.interrupt.injected = events->interrupt.injected;
3cfc3092
JK		 3390 vcpu->arch.interrupt.nr = events->interrupt.nr;
3391 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3392 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3393 kvm_x86_ops->set_interrupt_shadow(vcpu,
3394 events->interrupt.shadow);
3cfc3092
JK		 3395
3396 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3397 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3398 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3399 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3400
66450a21 3401 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3402 lapic_in_kernel(vcpu))
66450a21 3403 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3404
f077825a 3405 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3406 u32 hflags = vcpu->arch.hflags;
f077825a 3407 if (events->smi.smm)
6ef4e07e 3408 hflags |= HF_SMM_MASK;
f077825a 3409 else
6ef4e07e
XG		 3410 hflags &= ~HF_SMM_MASK;
3411 kvm_set_hflags(vcpu, hflags);
3412
f077825a 3413 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3414
3415 if (events->smi.smm) {
3416 if (events->smi.smm_inside_nmi)
3417 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3418 else
f4ef1910
WL		 3419 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3420 if (lapic_in_kernel(vcpu)) {
3421 if (events->smi.latched_init)
3422 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3423 else
3424 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3425 }
f077825a
PB		 3426 }
3427 }
3428
3842d135
AK		 3429 kvm_make_request(KVM_REQ_EVENT, vcpu);
3430
3cfc3092
JK		 3431 return 0;
3432}
3433
a1efbe77
JK		 3434static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3435 struct kvm_debugregs *dbgregs)
3436{
73aaf249
JK		 3437 unsigned long val;
3438
a1efbe77 3439 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3440 kvm_get_dr(vcpu, 6, &val);
73aaf249 3441 dbgregs->dr6 = val;
a1efbe77
JK		 3442 dbgregs->dr7 = vcpu->arch.dr7;
3443 dbgregs->flags = 0;
97e69aa6 3444 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3445}
3446
3447static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3448 struct kvm_debugregs *dbgregs)
3449{
3450 if (dbgregs->flags)
3451 return -EINVAL;
3452
d14bdb55
PB		 3453 if (dbgregs->dr6 & ~0xffffffffull)
3454 return -EINVAL;
3455 if (dbgregs->dr7 & ~0xffffffffull)
3456 return -EINVAL;
3457
a1efbe77 3458 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3459 kvm_update_dr0123(vcpu);
a1efbe77 3460 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3461 kvm_update_dr6(vcpu);
a1efbe77 3462 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3463 kvm_update_dr7(vcpu);
a1efbe77 3464
a1efbe77
JK		 3465 return 0;
3466}
3467
df1daba7
PB		 3468#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3469
3470static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3471{
c47ada30 3472 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3473 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3474 u64 valid;
3475
3476 /*
3477 * Copy legacy XSAVE area, to avoid complications with CPUID
3478 * leaves 0 and 1 in the loop below.
3479 */
3480 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3481
3482 /* Set XSTATE_BV */
00c87e9a 3483 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3484 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3485
3486 /*
3487 * Copy each region from the possibly compacted offset to the
3488 * non-compacted offset.
3489 */
d91cab78 3490 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3491 while (valid) {
3492 u64 feature = valid & -valid;
3493 int index = fls64(feature) - 1;
3494 void *src = get_xsave_addr(xsave, feature);
3495
3496 if (src) {
3497 u32 size, offset, ecx, edx;
3498 cpuid_count(XSTATE_CPUID, index,
3499 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3500 if (feature == XFEATURE_MASK_PKRU)
3501 memcpy(dest + offset, &vcpu->arch.pkru,
3502 sizeof(vcpu->arch.pkru));
3503 else
3504 memcpy(dest + offset, src, size);
3505
df1daba7
PB		 3506 }
3507
3508 valid -= feature;
3509 }
3510}
3511
3512static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3513{
c47ada30 3514 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3515 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3516 u64 valid;
3517
3518 /*
3519 * Copy legacy XSAVE area, to avoid complications with CPUID
3520 * leaves 0 and 1 in the loop below.
3521 */
3522 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3523
3524 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3525 xsave->header.xfeatures = xstate_bv;
782511b0 3526 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3527 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3528
3529 /*
3530 * Copy each region from the non-compacted offset to the
3531 * possibly compacted offset.
3532 */
d91cab78 3533 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3534 while (valid) {
3535 u64 feature = valid & -valid;
3536 int index = fls64(feature) - 1;
3537 void *dest = get_xsave_addr(xsave, feature);
3538
3539 if (dest) {
3540 u32 size, offset, ecx, edx;
3541 cpuid_count(XSTATE_CPUID, index,
3542 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3543 if (feature == XFEATURE_MASK_PKRU)
3544 memcpy(&vcpu->arch.pkru, src + offset,
3545 sizeof(vcpu->arch.pkru));
3546 else
3547 memcpy(dest, src + offset, size);
ee4100da 3548 }
df1daba7
PB		 3549
3550 valid -= feature;
3551 }
3552}
3553
2d5b5a66
SY		 3554static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3555 struct kvm_xsave *guest_xsave)
3556{
d366bf7e 3557 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3558 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3559 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3560 } else {
2d5b5a66 3561 memcpy(guest_xsave->region,
7366ed77 3562 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3563 sizeof(struct fxregs_state));
2d5b5a66 3564 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3565 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3566 }
3567}
3568
a575813b
WL		 3569#define XSAVE_MXCSR_OFFSET 24
3570
2d5b5a66
SY		 3571static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3572 struct kvm_xsave *guest_xsave)
3573{
3574 u64 xstate_bv =
3575 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3576 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3577
d366bf7e 3578 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3579 /*
3580 * Here we allow setting states that are not present in
3581 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3582 * with old userspace.
3583 */
a575813b
WL		 3584 if (xstate_bv & ~kvm_supported_xcr0() ||
3585 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3586 return -EINVAL;
df1daba7 3587 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3588 } else {
a575813b
WL		 3589 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3590 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3591 return -EINVAL;
7366ed77 3592 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3593 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3594 }
3595 return 0;
3596}
3597
3598static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3599 struct kvm_xcrs *guest_xcrs)
3600{
d366bf7e 3601 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3602 guest_xcrs->nr_xcrs = 0;
3603 return;
3604 }
3605
3606 guest_xcrs->nr_xcrs = 1;
3607 guest_xcrs->flags = 0;
3608 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3609 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3610}
3611
3612static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3613 struct kvm_xcrs *guest_xcrs)
3614{
3615 int i, r = 0;
3616
d366bf7e 3617 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3618 return -EINVAL;
3619
3620 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3621 return -EINVAL;
3622
3623 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3624 /* Only support XCR0 currently */
c67a04cb 3625 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3626 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3627 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3628 break;
3629 }
3630 if (r)
3631 r = -EINVAL;
3632 return r;
3633}
3634
1c0b28c2
EM		 3635/*
3636 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3637 * stopped by the hypervisor. This function will be called from the host only.
3638 * EINVAL is returned when the host attempts to set the flag for a guest that
3639 * does not support pv clocks.
3640 */
3641static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3642{
0b79459b 3643 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3644 return -EINVAL;
51d59c6b 3645 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3646 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3647 return 0;
3648}
3649
5c919412
AS		 3650static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3651 struct kvm_enable_cap *cap)
3652{
3653 if (cap->flags)
3654 return -EINVAL;
3655
3656 switch (cap->cap) {
efc479e6
RK		 3657 case KVM_CAP_HYPERV_SYNIC2:
3658 if (cap->args[0])
3659 return -EINVAL;
5c919412 3660 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3661 if (!irqchip_in_kernel(vcpu->kvm))
3662 return -EINVAL;
efc479e6
RK		 3663 return kvm_hv_activate_synic(vcpu, cap->cap ==
3664 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3665 default:
3666 return -EINVAL;
3667 }
3668}
3669
313a3dc7
CO		 3670long kvm_arch_vcpu_ioctl(struct file *filp,
3671 unsigned int ioctl, unsigned long arg)
3672{
3673 struct kvm_vcpu *vcpu = filp->private_data;
3674 void __user *argp = (void __user *)arg;
3675 int r;
d1ac91d8
AK		 3676 union {
3677 struct kvm_lapic_state *lapic;
3678 struct kvm_xsave *xsave;
3679 struct kvm_xcrs *xcrs;
3680 void *buffer;
3681 } u;
3682
9b062471
CD		 3683 vcpu_load(vcpu);
3684
d1ac91d8 3685 u.buffer = NULL;
313a3dc7
CO		 3686 switch (ioctl) {
3687 case KVM_GET_LAPIC: {
2204ae3c 3688 r = -EINVAL;
bce87cce 3689 if (!lapic_in_kernel(vcpu))
2204ae3c 3690 goto out;
d1ac91d8 3691 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3692
b772ff36 3693 r = -ENOMEM;
d1ac91d8 3694 if (!u.lapic)
b772ff36 3695 goto out;
d1ac91d8 3696 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3697 if (r)
3698 goto out;
3699 r = -EFAULT;
d1ac91d8 3700 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3701 goto out;
3702 r = 0;
3703 break;
3704 }
3705 case KVM_SET_LAPIC: {
2204ae3c 3706 r = -EINVAL;
bce87cce 3707 if (!lapic_in_kernel(vcpu))
2204ae3c 3708 goto out;
ff5c2c03 3709 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3710 if (IS_ERR(u.lapic)) {
3711 r = PTR_ERR(u.lapic);
3712 goto out_nofree;
3713 }
ff5c2c03 3714
d1ac91d8 3715 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3716 break;
3717 }
f77bc6a4
ZX		 3718 case KVM_INTERRUPT: {
3719 struct kvm_interrupt irq;
3720
3721 r = -EFAULT;
3722 if (copy_from_user(&irq, argp, sizeof irq))
3723 goto out;
3724 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3725 break;
3726 }
c4abb7c9
JK		 3727 case KVM_NMI: {
3728 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3729 break;
3730 }
f077825a
PB		 3731 case KVM_SMI: {
3732 r = kvm_vcpu_ioctl_smi(vcpu);
3733 break;
3734 }
313a3dc7
CO		 3735 case KVM_SET_CPUID: {
3736 struct kvm_cpuid __user *cpuid_arg = argp;
3737 struct kvm_cpuid cpuid;
3738
3739 r = -EFAULT;
3740 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3741 goto out;
3742 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3743 break;
3744 }
07716717
DK		 3745 case KVM_SET_CPUID2: {
3746 struct kvm_cpuid2 __user *cpuid_arg = argp;
3747 struct kvm_cpuid2 cpuid;
3748
3749 r = -EFAULT;
3750 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3751 goto out;
3752 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3753 cpuid_arg->entries);
07716717
DK		 3754 break;
3755 }
3756 case KVM_GET_CPUID2: {
3757 struct kvm_cpuid2 __user *cpuid_arg = argp;
3758 struct kvm_cpuid2 cpuid;
3759
3760 r = -EFAULT;
3761 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3762 goto out;
3763 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3764 cpuid_arg->entries);
07716717
DK		 3765 if (r)
3766 goto out;
3767 r = -EFAULT;
3768 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3769 goto out;
3770 r = 0;
3771 break;
3772 }
801e459a
TL		 3773 case KVM_GET_MSRS: {
3774 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 3775 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 3776 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3777 break;
801e459a
TL		 3778 }
3779 case KVM_SET_MSRS: {
3780 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 3781 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 3782 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3783 break;
801e459a 3784 }
b209749f
AK		 3785 case KVM_TPR_ACCESS_REPORTING: {
3786 struct kvm_tpr_access_ctl tac;
3787
3788 r = -EFAULT;
3789 if (copy_from_user(&tac, argp, sizeof tac))
3790 goto out;
3791 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3792 if (r)
3793 goto out;
3794 r = -EFAULT;
3795 if (copy_to_user(argp, &tac, sizeof tac))
3796 goto out;
3797 r = 0;
3798 break;
3799 };
b93463aa
AK		 3800 case KVM_SET_VAPIC_ADDR: {
3801 struct kvm_vapic_addr va;
7301d6ab 3802 int idx;
b93463aa
AK		 3803
3804 r = -EINVAL;
35754c98 3805 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3806 goto out;
3807 r = -EFAULT;
3808 if (copy_from_user(&va, argp, sizeof va))
3809 goto out;
7301d6ab 3810 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3811 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3812 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3813 break;
3814 }
890ca9ae
HY		 3815 case KVM_X86_SETUP_MCE: {
3816 u64 mcg_cap;
3817
3818 r = -EFAULT;
3819 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3820 goto out;
3821 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3822 break;
3823 }
3824 case KVM_X86_SET_MCE: {
3825 struct kvm_x86_mce mce;
3826
3827 r = -EFAULT;
3828 if (copy_from_user(&mce, argp, sizeof mce))
3829 goto out;
3830 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3831 break;
3832 }
3cfc3092
JK		 3833 case KVM_GET_VCPU_EVENTS: {
3834 struct kvm_vcpu_events events;
3835
3836 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3837
3838 r = -EFAULT;
3839 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3840 break;
3841 r = 0;
3842 break;
3843 }
3844 case KVM_SET_VCPU_EVENTS: {
3845 struct kvm_vcpu_events events;
3846
3847 r = -EFAULT;
3848 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3849 break;
3850
3851 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3852 break;
3853 }
a1efbe77
JK		 3854 case KVM_GET_DEBUGREGS: {
3855 struct kvm_debugregs dbgregs;
3856
3857 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3858
3859 r = -EFAULT;
3860 if (copy_to_user(argp, &dbgregs,
3861 sizeof(struct kvm_debugregs)))
3862 break;
3863 r = 0;
3864 break;
3865 }
3866 case KVM_SET_DEBUGREGS: {
3867 struct kvm_debugregs dbgregs;
3868
3869 r = -EFAULT;
3870 if (copy_from_user(&dbgregs, argp,
3871 sizeof(struct kvm_debugregs)))
3872 break;
3873
3874 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3875 break;
3876 }
2d5b5a66 3877 case KVM_GET_XSAVE: {
d1ac91d8 3878 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3879 r = -ENOMEM;
d1ac91d8 3880 if (!u.xsave)
2d5b5a66
SY		 3881 break;
3882
d1ac91d8 3883 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3884
3885 r = -EFAULT;
d1ac91d8 3886 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3887 break;
3888 r = 0;
3889 break;
3890 }
3891 case KVM_SET_XSAVE: {
ff5c2c03 3892 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 3893 if (IS_ERR(u.xsave)) {
3894 r = PTR_ERR(u.xsave);
3895 goto out_nofree;
3896 }
2d5b5a66 3897
d1ac91d8 3898 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3899 break;
3900 }
3901 case KVM_GET_XCRS: {
d1ac91d8 3902 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3903 r = -ENOMEM;
d1ac91d8 3904 if (!u.xcrs)
2d5b5a66
SY		 3905 break;
3906
d1ac91d8 3907 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3908
3909 r = -EFAULT;
d1ac91d8 3910 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3911 sizeof(struct kvm_xcrs)))
3912 break;
3913 r = 0;
3914 break;
3915 }
3916 case KVM_SET_XCRS: {
ff5c2c03 3917 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 3918 if (IS_ERR(u.xcrs)) {
3919 r = PTR_ERR(u.xcrs);
3920 goto out_nofree;
3921 }
2d5b5a66 3922
d1ac91d8 3923 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3924 break;
3925 }
92a1f12d
JR		 3926 case KVM_SET_TSC_KHZ: {
3927 u32 user_tsc_khz;
3928
3929 r = -EINVAL;
92a1f12d
JR		 3930 user_tsc_khz = (u32)arg;
3931
3932 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3933 goto out;
3934
cc578287
ZA		 3935 if (user_tsc_khz == 0)
3936 user_tsc_khz = tsc_khz;
3937
381d585c
HZ		 3938 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3939 r = 0;
92a1f12d 3940
92a1f12d
JR		 3941 goto out;
3942 }
3943 case KVM_GET_TSC_KHZ: {
cc578287 3944 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3945 goto out;
3946 }
1c0b28c2
EM		 3947 case KVM_KVMCLOCK_CTRL: {
3948 r = kvm_set_guest_paused(vcpu);
3949 goto out;
3950 }
5c919412
AS		 3951 case KVM_ENABLE_CAP: {
3952 struct kvm_enable_cap cap;
3953
3954 r = -EFAULT;
3955 if (copy_from_user(&cap, argp, sizeof(cap)))
3956 goto out;
3957 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3958 break;
3959 }
313a3dc7
CO		 3960 default:
3961 r = -EINVAL;
3962 }
3963out:
d1ac91d8 3964 kfree(u.buffer);
9b062471
CD		 3965out_nofree:
3966 vcpu_put(vcpu);
313a3dc7
CO		 3967 return r;
3968}
3969
1499fa80 3970vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5b1c1493
CO		 3971{
3972 return VM_FAULT_SIGBUS;
3973}
3974
1fe779f8
CO		 3975static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3976{
3977 int ret;
3978
3979 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3980 return -EINVAL;
1fe779f8
CO		 3981 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3982 return ret;
3983}
3984
b927a3ce
SY		 3985static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3986 u64 ident_addr)
3987{
2ac52ab8 3988 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3989}
3990
1fe779f8
CO		 3991static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3992 u32 kvm_nr_mmu_pages)
3993{
3994 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3995 return -EINVAL;
3996
79fac95e 3997 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3998
3999 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 4000 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 4001
79fac95e 4002 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 4003 return 0;
4004}
4005
4006static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4007{
39de71ec 4008 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 4009}
4010
1fe779f8
CO		 4011static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4012{
90bca052 4013 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4014 int r;
4015
4016 r = 0;
4017 switch (chip->chip_id) {
4018 case KVM_IRQCHIP_PIC_MASTER:
90bca052 4019 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 4020 sizeof(struct kvm_pic_state));
4021 break;
4022 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 4023 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 4024 sizeof(struct kvm_pic_state));
4025 break;
4026 case KVM_IRQCHIP_IOAPIC:
33392b49 4027 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4028 break;
4029 default:
4030 r = -EINVAL;
4031 break;
4032 }
4033 return r;
4034}
4035
4036static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4037{
90bca052 4038 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4039 int r;
4040
4041 r = 0;
4042 switch (chip->chip_id) {
4043 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4044 spin_lock(&pic->lock);
4045 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4046 sizeof(struct kvm_pic_state));
90bca052 4047 spin_unlock(&pic->lock);
1fe779f8
CO		 4048 break;
4049 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4050 spin_lock(&pic->lock);
4051 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4052 sizeof(struct kvm_pic_state));
90bca052 4053 spin_unlock(&pic->lock);
1fe779f8
CO		 4054 break;
4055 case KVM_IRQCHIP_IOAPIC:
33392b49 4056 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4057 break;
4058 default:
4059 r = -EINVAL;
4060 break;
4061 }
90bca052 4062 kvm_pic_update_irq(pic);
1fe779f8
CO		 4063 return r;
4064}
4065
e0f63cb9
SY		 4066static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4067{
34f3941c
RK		 4068 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4069
4070 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4071
4072 mutex_lock(&kps->lock);
4073 memcpy(ps, &kps->channels, sizeof(*ps));
4074 mutex_unlock(&kps->lock);
2da29bcc 4075 return 0;
e0f63cb9
SY		 4076}
4077
4078static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4079{
0185604c 4080 int i;
09edea72
RK		 4081 struct kvm_pit *pit = kvm->arch.vpit;
4082
4083 mutex_lock(&pit->pit_state.lock);
34f3941c 4084 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4085 for (i = 0; i < 3; i++)
09edea72
RK		 4086 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4087 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4088 return 0;
e9f42757
BK		 4089}
4090
4091static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4092{
e9f42757
BK		 4093 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4094 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4095 sizeof(ps->channels));
4096 ps->flags = kvm->arch.vpit->pit_state.flags;
4097 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4098 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4099 return 0;
e9f42757
BK		 4100}
4101
4102static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4103{
2da29bcc 4104 int start = 0;
0185604c 4105 int i;
e9f42757 4106 u32 prev_legacy, cur_legacy;
09edea72
RK		 4107 struct kvm_pit *pit = kvm->arch.vpit;
4108
4109 mutex_lock(&pit->pit_state.lock);
4110 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4111 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4112 if (!prev_legacy && cur_legacy)
4113 start = 1;
09edea72
RK		 4114 memcpy(&pit->pit_state.channels, &ps->channels,
4115 sizeof(pit->pit_state.channels));
4116 pit->pit_state.flags = ps->flags;
0185604c 4117 for (i = 0; i < 3; i++)
09edea72 4118 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4119 start && i == 0);
09edea72 4120 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4121 return 0;
e0f63cb9
SY		 4122}
4123
52d939a0
MT		 4124static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4125 struct kvm_reinject_control *control)
4126{
71474e2f
RK		 4127 struct kvm_pit *pit = kvm->arch.vpit;
4128
4129 if (!pit)
52d939a0 4130 return -ENXIO;
b39c90b6 4131
71474e2f
RK		 4132 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4133 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4134 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4135 */
4136 mutex_lock(&pit->pit_state.lock);
4137 kvm_pit_set_reinject(pit, control->pit_reinject);
4138 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4139
52d939a0
MT		 4140 return 0;
4141}
4142
95d4c16c 4143/**
60c34612
TY		 4144 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4145 * @kvm: kvm instance
4146 * @log: slot id and address to which we copy the log
95d4c16c 4147 *
e108ff2f
PB		 4148 * Steps 1-4 below provide general overview of dirty page logging. See
4149 * kvm_get_dirty_log_protect() function description for additional details.
4150 *
4151 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4152 * always flush the TLB (step 4) even if previous step failed and the dirty
4153 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4154 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4155 * writes will be marked dirty for next log read.
95d4c16c 4156 *
60c34612
TY		 4157 * 1. Take a snapshot of the bit and clear it if needed.
4158 * 2. Write protect the corresponding page.
e108ff2f
PB		 4159 * 3. Copy the snapshot to the userspace.
4160 * 4. Flush TLB's if needed.
5bb064dc 4161 */
60c34612 4162int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4163{
60c34612 4164 bool is_dirty = false;
e108ff2f 4165 int r;
5bb064dc 4166
79fac95e 4167 mutex_lock(&kvm->slots_lock);
5bb064dc 4168
88178fd4
KH		 4169 /*
4170 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4171 */
4172 if (kvm_x86_ops->flush_log_dirty)
4173 kvm_x86_ops->flush_log_dirty(kvm);
4174
e108ff2f 4175 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 4176
4177 /*
4178 * All the TLBs can be flushed out of mmu lock, see the comments in
4179 * kvm_mmu_slot_remove_write_access().
4180 */
e108ff2f 4181 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 4182 if (is_dirty)
4183 kvm_flush_remote_tlbs(kvm);
4184
79fac95e 4185 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4186 return r;
4187}
4188
aa2fbe6d
YZ		 4189int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4190 bool line_status)
23d43cf9
CD		 4191{
4192 if (!irqchip_in_kernel(kvm))
4193 return -ENXIO;
4194
4195 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4196 irq_event->irq, irq_event->level,
4197 line_status);
23d43cf9
CD		 4198 return 0;
4199}
4200
90de4a18
NA		 4201static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4202 struct kvm_enable_cap *cap)
4203{
4204 int r;
4205
4206 if (cap->flags)
4207 return -EINVAL;
4208
4209 switch (cap->cap) {
4210 case KVM_CAP_DISABLE_QUIRKS:
4211 kvm->arch.disabled_quirks = cap->args[0];
4212 r = 0;
4213 break;
49df6397
SR		 4214 case KVM_CAP_SPLIT_IRQCHIP: {
4215 mutex_lock(&kvm->lock);
b053b2ae
SR		 4216 r = -EINVAL;
4217 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4218 goto split_irqchip_unlock;
49df6397
SR		 4219 r = -EEXIST;
4220 if (irqchip_in_kernel(kvm))
4221 goto split_irqchip_unlock;
557abc40 4222 if (kvm->created_vcpus)
49df6397
SR		 4223 goto split_irqchip_unlock;
4224 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4225 if (r)
49df6397
SR		 4226 goto split_irqchip_unlock;
4227 /* Pairs with irqchip_in_kernel. */
4228 smp_wmb();
49776faf 4229 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4230 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4231 r = 0;
4232split_irqchip_unlock:
4233 mutex_unlock(&kvm->lock);
4234 break;
4235 }
37131313
RK		 4236 case KVM_CAP_X2APIC_API:
4237 r = -EINVAL;
4238 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4239 break;
4240
4241 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4242 kvm->arch.x2apic_format = true;
c519265f
RK		 4243 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4244 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4245
4246 r = 0;
4247 break;
4d5422ce
WL		 4248 case KVM_CAP_X86_DISABLE_EXITS:
4249 r = -EINVAL;
4250 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4251 break;
4252
4253 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4254 kvm_can_mwait_in_guest())
4255 kvm->arch.mwait_in_guest = true;
caa057a2
WL		 4256 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HTL)
4257 kvm->arch.hlt_in_guest = true;
b31c114b
WL		 4258 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4259 kvm->arch.pause_in_guest = true;
4d5422ce
WL		 4260 r = 0;
4261 break;
90de4a18
NA		 4262 default:
4263 r = -EINVAL;
4264 break;
4265 }
4266 return r;
4267}
4268
1fe779f8
CO		 4269long kvm_arch_vm_ioctl(struct file *filp,
4270 unsigned int ioctl, unsigned long arg)
4271{
4272 struct kvm *kvm = filp->private_data;
4273 void __user *argp = (void __user *)arg;
367e1319 4274 int r = -ENOTTY;
f0d66275
DH		 4275 /*
4276 * This union makes it completely explicit to gcc-3.x
4277 * that these two variables' stack usage should be
4278 * combined, not added together.
4279 */
4280 union {
4281 struct kvm_pit_state ps;
e9f42757 4282 struct kvm_pit_state2 ps2;
c5ff41ce 4283 struct kvm_pit_config pit_config;
f0d66275 4284 } u;
1fe779f8
CO		 4285
4286 switch (ioctl) {
4287 case KVM_SET_TSS_ADDR:
4288 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4289 break;
b927a3ce
SY		 4290 case KVM_SET_IDENTITY_MAP_ADDR: {
4291 u64 ident_addr;
4292
1af1ac91
DH		 4293 mutex_lock(&kvm->lock);
4294 r = -EINVAL;
4295 if (kvm->created_vcpus)
4296 goto set_identity_unlock;
b927a3ce
SY		 4297 r = -EFAULT;
4298 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4299 goto set_identity_unlock;
b927a3ce 4300 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4301set_identity_unlock:
4302 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4303 break;
4304 }
1fe779f8
CO		 4305 case KVM_SET_NR_MMU_PAGES:
4306 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4307 break;
4308 case KVM_GET_NR_MMU_PAGES:
4309 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4310 break;
3ddea128 4311 case KVM_CREATE_IRQCHIP: {
3ddea128 4312 mutex_lock(&kvm->lock);
09941366 4313
3ddea128 4314 r = -EEXIST;
35e6eaa3 4315 if (irqchip_in_kernel(kvm))
3ddea128 4316 goto create_irqchip_unlock;
09941366 4317
3e515705 4318 r = -EINVAL;
557abc40 4319 if (kvm->created_vcpus)
3e515705 4320 goto create_irqchip_unlock;
09941366
RK		 4321
4322 r = kvm_pic_init(kvm);
4323 if (r)
3ddea128 4324 goto create_irqchip_unlock;
09941366
RK		 4325
4326 r = kvm_ioapic_init(kvm);
4327 if (r) {
09941366 4328 kvm_pic_destroy(kvm);
3ddea128 4329 goto create_irqchip_unlock;
09941366
RK		 4330 }
4331
399ec807
AK		 4332 r = kvm_setup_default_irq_routing(kvm);
4333 if (r) {
72bb2fcd 4334 kvm_ioapic_destroy(kvm);
09941366 4335 kvm_pic_destroy(kvm);
71ba994c 4336 goto create_irqchip_unlock;
399ec807 4337 }
49776faf 4338 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4339 smp_wmb();
49776faf 4340 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4341 create_irqchip_unlock:
4342 mutex_unlock(&kvm->lock);
1fe779f8 4343 break;
3ddea128 4344 }
7837699f 4345 case KVM_CREATE_PIT:
c5ff41ce
JK		 4346 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4347 goto create_pit;
4348 case KVM_CREATE_PIT2:
4349 r = -EFAULT;
4350 if (copy_from_user(&u.pit_config, argp,
4351 sizeof(struct kvm_pit_config)))
4352 goto out;
4353 create_pit:
250715a6 4354 mutex_lock(&kvm->lock);
269e05e4
AK		 4355 r = -EEXIST;
4356 if (kvm->arch.vpit)
4357 goto create_pit_unlock;
7837699f 4358 r = -ENOMEM;
c5ff41ce 4359 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4360 if (kvm->arch.vpit)
4361 r = 0;
269e05e4 4362 create_pit_unlock:
250715a6 4363 mutex_unlock(&kvm->lock);
7837699f 4364 break;
1fe779f8
CO		 4365 case KVM_GET_IRQCHIP: {
4366 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4367 struct kvm_irqchip *chip;
1fe779f8 4368
ff5c2c03
SL		 4369 chip = memdup_user(argp, sizeof(*chip));
4370 if (IS_ERR(chip)) {
4371 r = PTR_ERR(chip);
1fe779f8 4372 goto out;
ff5c2c03
SL		 4373 }
4374
1fe779f8 4375 r = -ENXIO;
826da321 4376 if (!irqchip_kernel(kvm))
f0d66275
DH		 4377 goto get_irqchip_out;
4378 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4379 if (r)
f0d66275 4380 goto get_irqchip_out;
1fe779f8 4381 r = -EFAULT;
f0d66275
DH		 4382 if (copy_to_user(argp, chip, sizeof *chip))
4383 goto get_irqchip_out;
1fe779f8 4384 r = 0;
f0d66275
DH		 4385 get_irqchip_out:
4386 kfree(chip);
1fe779f8
CO		 4387 break;
4388 }
4389 case KVM_SET_IRQCHIP: {
4390 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4391 struct kvm_irqchip *chip;
1fe779f8 4392
ff5c2c03
SL		 4393 chip = memdup_user(argp, sizeof(*chip));
4394 if (IS_ERR(chip)) {
4395 r = PTR_ERR(chip);
1fe779f8 4396 goto out;
ff5c2c03
SL		 4397 }
4398
1fe779f8 4399 r = -ENXIO;
826da321 4400 if (!irqchip_kernel(kvm))
f0d66275
DH		 4401 goto set_irqchip_out;
4402 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4403 if (r)
f0d66275 4404 goto set_irqchip_out;
1fe779f8 4405 r = 0;
f0d66275
DH		 4406 set_irqchip_out:
4407 kfree(chip);
1fe779f8
CO		 4408 break;
4409 }
e0f63cb9 4410 case KVM_GET_PIT: {
e0f63cb9 4411 r = -EFAULT;
f0d66275 4412 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4413 goto out;
4414 r = -ENXIO;
4415 if (!kvm->arch.vpit)
4416 goto out;
f0d66275 4417 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4418 if (r)
4419 goto out;
4420 r = -EFAULT;
f0d66275 4421 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4422 goto out;
4423 r = 0;
4424 break;
4425 }
4426 case KVM_SET_PIT: {
e0f63cb9 4427 r = -EFAULT;
f0d66275 4428 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4429 goto out;
4430 r = -ENXIO;
4431 if (!kvm->arch.vpit)
4432 goto out;
f0d66275 4433 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4434 break;
4435 }
e9f42757
BK		 4436 case KVM_GET_PIT2: {
4437 r = -ENXIO;
4438 if (!kvm->arch.vpit)
4439 goto out;
4440 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4441 if (r)
4442 goto out;
4443 r = -EFAULT;
4444 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4445 goto out;
4446 r = 0;
4447 break;
4448 }
4449 case KVM_SET_PIT2: {
4450 r = -EFAULT;
4451 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4452 goto out;
4453 r = -ENXIO;
4454 if (!kvm->arch.vpit)
4455 goto out;
4456 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4457 break;
4458 }
52d939a0
MT		 4459 case KVM_REINJECT_CONTROL: {
4460 struct kvm_reinject_control control;
4461 r = -EFAULT;
4462 if (copy_from_user(&control, argp, sizeof(control)))
4463 goto out;
4464 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4465 break;
4466 }
d71ba788
PB		 4467 case KVM_SET_BOOT_CPU_ID:
4468 r = 0;
4469 mutex_lock(&kvm->lock);
557abc40 4470 if (kvm->created_vcpus)
d71ba788
PB		 4471 r = -EBUSY;
4472 else
4473 kvm->arch.bsp_vcpu_id = arg;
4474 mutex_unlock(&kvm->lock);
4475 break;
ffde22ac 4476 case KVM_XEN_HVM_CONFIG: {
51776043 4477 struct kvm_xen_hvm_config xhc;
ffde22ac 4478 r = -EFAULT;
51776043 4479 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4480 goto out;
4481 r = -EINVAL;
51776043 4482 if (xhc.flags)
ffde22ac 4483 goto out;
51776043 4484 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4485 r = 0;
4486 break;
4487 }
afbcf7ab 4488 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4489 struct kvm_clock_data user_ns;
4490 u64 now_ns;
afbcf7ab
GC		 4491
4492 r = -EFAULT;
4493 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4494 goto out;
4495
4496 r = -EINVAL;
4497 if (user_ns.flags)
4498 goto out;
4499
4500 r = 0;
0bc48bea
RK		 4501 /*
4502 * TODO: userspace has to take care of races with VCPU_RUN, so
4503 * kvm_gen_update_masterclock() can be cut down to locked
4504 * pvclock_update_vm_gtod_copy().
4505 */
4506 kvm_gen_update_masterclock(kvm);
e891a32e 4507 now_ns = get_kvmclock_ns(kvm);
108b249c 4508 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4509 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4510 break;
4511 }
4512 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4513 struct kvm_clock_data user_ns;
4514 u64 now_ns;
4515
e891a32e 4516 now_ns = get_kvmclock_ns(kvm);
108b249c 4517 user_ns.clock = now_ns;
e3fd9a93 4518 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4519 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4520
4521 r = -EFAULT;
4522 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4523 goto out;
4524 r = 0;
4525 break;
4526 }
90de4a18
NA		 4527 case KVM_ENABLE_CAP: {
4528 struct kvm_enable_cap cap;
afbcf7ab 4529
90de4a18
NA		 4530 r = -EFAULT;
4531 if (copy_from_user(&cap, argp, sizeof(cap)))
4532 goto out;
4533 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4534 break;
4535 }
5acc5c06
BS		 4536 case KVM_MEMORY_ENCRYPT_OP: {
4537 r = -ENOTTY;
4538 if (kvm_x86_ops->mem_enc_op)
4539 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4540 break;
4541 }
69eaedee
BS		 4542 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4543 struct kvm_enc_region region;
4544
4545 r = -EFAULT;
4546 if (copy_from_user(&region, argp, sizeof(region)))
4547 goto out;
4548
4549 r = -ENOTTY;
4550 if (kvm_x86_ops->mem_enc_reg_region)
4551 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4552 break;
4553 }
4554 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4555 struct kvm_enc_region region;
4556
4557 r = -EFAULT;
4558 if (copy_from_user(&region, argp, sizeof(region)))
4559 goto out;
4560
4561 r = -ENOTTY;
4562 if (kvm_x86_ops->mem_enc_unreg_region)
4563 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4564 break;
4565 }
faeb7833
RK		 4566 case KVM_HYPERV_EVENTFD: {
4567 struct kvm_hyperv_eventfd hvevfd;
4568
4569 r = -EFAULT;
4570 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4571 goto out;
4572 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4573 break;
4574 }
1fe779f8 4575 default:
ad6260da 4576 r = -ENOTTY;
1fe779f8
CO		 4577 }
4578out:
4579 return r;
4580}
4581
a16b043c 4582static void kvm_init_msr_list(void)
043405e1
CO		 4583{
4584 u32 dummy[2];
4585 unsigned i, j;
4586
62ef68bb 4587 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4588 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4589 continue;
93c4adc7
PB		 4590
4591 /*
4592 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4593 * to the guests in some cases.
93c4adc7
PB		 4594 */
4595 switch (msrs_to_save[i]) {
4596 case MSR_IA32_BNDCFGS:
4597 if (!kvm_x86_ops->mpx_supported())
4598 continue;
4599 break;
9dbe6cf9
PB		 4600 case MSR_TSC_AUX:
4601 if (!kvm_x86_ops->rdtscp_supported())
4602 continue;
4603 break;
93c4adc7
PB		 4604 default:
4605 break;
4606 }
4607
043405e1
CO		 4608 if (j < i)
4609 msrs_to_save[j] = msrs_to_save[i];
4610 j++;
4611 }
4612 num_msrs_to_save = j;
62ef68bb
PB		 4613
4614 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4615 switch (emulated_msrs[i]) {
6d396b55
PB		 4616 case MSR_IA32_SMBASE:
4617 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4618 continue;
4619 break;
62ef68bb
PB		 4620 default:
4621 break;
4622 }
4623
4624 if (j < i)
4625 emulated_msrs[j] = emulated_msrs[i];
4626 j++;
4627 }
4628 num_emulated_msrs = j;
801e459a
TL		 4629
4630 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4631 struct kvm_msr_entry msr;
4632
4633 msr.index = msr_based_features[i];
66421c1e 4634 if (kvm_get_msr_feature(&msr))
801e459a
TL		 4635 continue;
4636
4637 if (j < i)
4638 msr_based_features[j] = msr_based_features[i];
4639 j++;
4640 }
4641 num_msr_based_features = j;
043405e1
CO		 4642}
4643
bda9020e
MT		 4644static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4645 const void *v)
bbd9b64e 4646{
70252a10
AK		 4647 int handled = 0;
4648 int n;
4649
4650 do {
4651 n = min(len, 8);
bce87cce 4652 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4653 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4654 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4655 break;
4656 handled += n;
4657 addr += n;
4658 len -= n;
4659 v += n;
4660 } while (len);
bbd9b64e 4661
70252a10 4662 return handled;
bbd9b64e
CO		 4663}
4664
bda9020e 4665static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4666{
70252a10
AK		 4667 int handled = 0;
4668 int n;
4669
4670 do {
4671 n = min(len, 8);
bce87cce 4672 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4673 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4674 addr, n, v))
4675 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 4676 break;
e39d200f 4677 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 4678 handled += n;
4679 addr += n;
4680 len -= n;
4681 v += n;
4682 } while (len);
bbd9b64e 4683
70252a10 4684 return handled;
bbd9b64e
CO		 4685}
4686
2dafc6c2
GN		 4687static void kvm_set_segment(struct kvm_vcpu *vcpu,
4688 struct kvm_segment *var, int seg)
4689{
4690 kvm_x86_ops->set_segment(vcpu, var, seg);
4691}
4692
4693void kvm_get_segment(struct kvm_vcpu *vcpu,
4694 struct kvm_segment *var, int seg)
4695{
4696 kvm_x86_ops->get_segment(vcpu, var, seg);
4697}
4698
54987b7a
PB		 4699gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4700 struct x86_exception *exception)
02f59dc9
JR		 4701{
4702 gpa_t t_gpa;
02f59dc9
JR		 4703
4704 BUG_ON(!mmu_is_nested(vcpu));
4705
4706 /* NPT walks are always user-walks */
4707 access |= PFERR_USER_MASK;
54987b7a 4708 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4709
4710 return t_gpa;
4711}
4712
ab9ae313
AK		 4713gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4714 struct x86_exception *exception)
1871c602
GN		 4715{
4716 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4717 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4718}
4719
ab9ae313
AK		 4720 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4721 struct x86_exception *exception)
1871c602
GN		 4722{
4723 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4724 access |= PFERR_FETCH_MASK;
ab9ae313 4725 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4726}
4727
ab9ae313
AK		 4728gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4729 struct x86_exception *exception)
1871c602
GN		 4730{
4731 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4732 access |= PFERR_WRITE_MASK;
ab9ae313 4733 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4734}
4735
4736/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4737gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4738 struct x86_exception *exception)
1871c602 4739{
ab9ae313 4740 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4741}
4742
4743static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4744 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4745 struct x86_exception *exception)
bbd9b64e
CO		 4746{
4747 void *data = val;
10589a46 4748 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4749
4750 while (bytes) {
14dfe855 4751 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4752 exception);
bbd9b64e 4753 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4754 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4755 int ret;
4756
bcc55cba 4757 if (gpa == UNMAPPED_GVA)
ab9ae313 4758 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4759 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4760 offset, toread);
10589a46 4761 if (ret < 0) {
c3cd7ffa 4762 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4763 goto out;
4764 }
bbd9b64e 4765
77c2002e
IE		 4766 bytes -= toread;
4767 data += toread;
4768 addr += toread;
bbd9b64e 4769 }
10589a46 4770out:
10589a46 4771 return r;
bbd9b64e 4772}
77c2002e 4773
1871c602 4774/* used for instruction fetching */
0f65dd70
AK		 4775static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4776 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4777 struct x86_exception *exception)
1871c602 4778{
0f65dd70 4779 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4780 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4781 unsigned offset;
4782 int ret;
0f65dd70 4783
44583cba
PB		 4784 /* Inline kvm_read_guest_virt_helper for speed. */
4785 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4786 exception);
4787 if (unlikely(gpa == UNMAPPED_GVA))
4788 return X86EMUL_PROPAGATE_FAULT;
4789
4790 offset = addr & (PAGE_SIZE-1);
4791 if (WARN_ON(offset + bytes > PAGE_SIZE))
4792 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4793 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4794 offset, bytes);
44583cba
PB		 4795 if (unlikely(ret < 0))
4796 return X86EMUL_IO_NEEDED;
4797
4798 return X86EMUL_CONTINUE;
1871c602
GN		 4799}
4800
064aea77 4801int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4802 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4803 struct x86_exception *exception)
1871c602 4804{
0f65dd70 4805 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4806 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4807
1871c602 4808 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4809 exception);
1871c602 4810}
064aea77 4811EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4812
0f65dd70
AK		 4813static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4814 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4815 struct x86_exception *exception)
1871c602 4816{
0f65dd70 4817 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4818 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4819}
4820
7a036a6f
RK		 4821static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4822 unsigned long addr, void *val, unsigned int bytes)
4823{
4824 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4825 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4826
4827 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4828}
4829
6a4d7550 4830int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4831 gva_t addr, void *val,
2dafc6c2 4832 unsigned int bytes,
bcc55cba 4833 struct x86_exception *exception)
77c2002e 4834{
0f65dd70 4835 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4836 void *data = val;
4837 int r = X86EMUL_CONTINUE;
4838
4839 while (bytes) {
14dfe855
JR		 4840 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4841 PFERR_WRITE_MASK,
ab9ae313 4842 exception);
77c2002e
IE		 4843 unsigned offset = addr & (PAGE_SIZE-1);
4844 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4845 int ret;
4846
bcc55cba 4847 if (gpa == UNMAPPED_GVA)
ab9ae313 4848 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4849 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4850 if (ret < 0) {
c3cd7ffa 4851 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4852 goto out;
4853 }
4854
4855 bytes -= towrite;
4856 data += towrite;
4857 addr += towrite;
4858 }
4859out:
4860 return r;
4861}
6a4d7550 4862EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4863
082d06ed
WL		 4864int handle_ud(struct kvm_vcpu *vcpu)
4865{
6c86eedc 4866 int emul_type = EMULTYPE_TRAP_UD;
082d06ed 4867 enum emulation_result er;
6c86eedc
WL		 4868 char sig[5]; /* ud2; .ascii "kvm" */
4869 struct x86_exception e;
4870
4871 if (force_emulation_prefix &&
4872 kvm_read_guest_virt(&vcpu->arch.emulate_ctxt,
4873 kvm_get_linear_rip(vcpu), sig, sizeof(sig), &e) == 0 &&
4874 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
4875 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
4876 emul_type = 0;
4877 }
082d06ed 4878
6c86eedc 4879 er = emulate_instruction(vcpu, emul_type);
082d06ed
WL		 4880 if (er == EMULATE_USER_EXIT)
4881 return 0;
4882 if (er != EMULATE_DONE)
4883 kvm_queue_exception(vcpu, UD_VECTOR);
4884 return 1;
4885}
4886EXPORT_SYMBOL_GPL(handle_ud);
4887
0f89b207
TL		 4888static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4889 gpa_t gpa, bool write)
4890{
4891 /* For APIC access vmexit */
4892 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4893 return 1;
4894
4895 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4896 trace_vcpu_match_mmio(gva, gpa, write, true);
4897 return 1;
4898 }
4899
4900 return 0;
4901}
4902
af7cc7d1
XG		 4903static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4904 gpa_t *gpa, struct x86_exception *exception,
4905 bool write)
4906{
97d64b78
AK		 4907 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4908 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4909
be94f6b7
HH		 4910 /*
4911 * currently PKRU is only applied to ept enabled guest so
4912 * there is no pkey in EPT page table for L1 guest or EPT
4913 * shadow page table for L2 guest.
4914 */
97d64b78 4915 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4916 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4917 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4918 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4919 (gva & (PAGE_SIZE - 1));
4f022648 4920 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4921 return 1;
4922 }
4923
af7cc7d1
XG		 4924 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4925
4926 if (*gpa == UNMAPPED_GVA)
4927 return -1;
4928
0f89b207 4929 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4930}
4931
3200f405 4932int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4933 const void *val, int bytes)
bbd9b64e
CO		 4934{
4935 int ret;
4936
54bf36aa 4937 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4938 if (ret < 0)
bbd9b64e 4939 return 0;
0eb05bf2 4940 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4941 return 1;
4942}
4943
77d197b2
XG		 4944struct read_write_emulator_ops {
4945 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4946 int bytes);
4947 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4948 void *val, int bytes);
4949 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4950 int bytes, void *val);
4951 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4952 void *val, int bytes);
4953 bool write;
4954};
4955
4956static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4957{
4958 if (vcpu->mmio_read_completed) {
77d197b2 4959 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 4960 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 4961 vcpu->mmio_read_completed = 0;
4962 return 1;
4963 }
4964
4965 return 0;
4966}
4967
4968static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4969 void *val, int bytes)
4970{
54bf36aa 4971 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4972}
4973
4974static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4975 void *val, int bytes)
4976{
4977 return emulator_write_phys(vcpu, gpa, val, bytes);
4978}
4979
4980static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4981{
e39d200f 4982 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 4983 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4984}
4985
4986static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4987 void *val, int bytes)
4988{
e39d200f 4989 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 4990 return X86EMUL_IO_NEEDED;
4991}
4992
4993static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4994 void *val, int bytes)
4995{
f78146b0
AK		 4996 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4997
87da7e66 4998 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4999 return X86EMUL_CONTINUE;
5000}
5001
0fbe9b0b 5002static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 5003 .read_write_prepare = read_prepare,
5004 .read_write_emulate = read_emulate,
5005 .read_write_mmio = vcpu_mmio_read,
5006 .read_write_exit_mmio = read_exit_mmio,
5007};
5008
0fbe9b0b 5009static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 5010 .read_write_emulate = write_emulate,
5011 .read_write_mmio = write_mmio,
5012 .read_write_exit_mmio = write_exit_mmio,
5013 .write = true,
5014};
5015
22388a3c
XG		 5016static int emulator_read_write_onepage(unsigned long addr, void *val,
5017 unsigned int bytes,
5018 struct x86_exception *exception,
5019 struct kvm_vcpu *vcpu,
0fbe9b0b 5020 const struct read_write_emulator_ops *ops)
bbd9b64e 5021{
af7cc7d1
XG		 5022 gpa_t gpa;
5023 int handled, ret;
22388a3c 5024 bool write = ops->write;
f78146b0 5025 struct kvm_mmio_fragment *frag;
0f89b207
TL		 5026 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5027
5028 /*
5029 * If the exit was due to a NPF we may already have a GPA.
5030 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5031 * Note, this cannot be used on string operations since string
5032 * operation using rep will only have the initial GPA from the NPF
5033 * occurred.
5034 */
5035 if (vcpu->arch.gpa_available &&
5036 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 5037 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5038 gpa = vcpu->arch.gpa_val;
5039 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5040 } else {
5041 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5042 if (ret < 0)
5043 return X86EMUL_PROPAGATE_FAULT;
0f89b207 5044 }
10589a46 5045
618232e2 5046 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 5047 return X86EMUL_CONTINUE;
5048
bbd9b64e
CO		 5049 /*
5050 * Is this MMIO handled locally?
5051 */
22388a3c 5052 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 5053 if (handled == bytes)
bbd9b64e 5054 return X86EMUL_CONTINUE;
bbd9b64e 5055
70252a10
AK		 5056 gpa += handled;
5057 bytes -= handled;
5058 val += handled;
5059
87da7e66
XG		 5060 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5061 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5062 frag->gpa = gpa;
5063 frag->data = val;
5064 frag->len = bytes;
f78146b0 5065 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5066}
5067
52eb5a6d
XL		 5068static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5069 unsigned long addr,
22388a3c
XG		 5070 void *val, unsigned int bytes,
5071 struct x86_exception *exception,
0fbe9b0b 5072 const struct read_write_emulator_ops *ops)
bbd9b64e 5073{
0f65dd70 5074 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5075 gpa_t gpa;
5076 int rc;
5077
5078 if (ops->read_write_prepare &&
5079 ops->read_write_prepare(vcpu, val, bytes))
5080 return X86EMUL_CONTINUE;
5081
5082 vcpu->mmio_nr_fragments = 0;
0f65dd70 5083
bbd9b64e
CO		 5084 /* Crossing a page boundary? */
5085 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5086 int now;
bbd9b64e
CO		 5087
5088 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5089 rc = emulator_read_write_onepage(addr, val, now, exception,
5090 vcpu, ops);
5091
bbd9b64e
CO		 5092 if (rc != X86EMUL_CONTINUE)
5093 return rc;
5094 addr += now;
bac15531
NA		 5095 if (ctxt->mode != X86EMUL_MODE_PROT64)
5096 addr = (u32)addr;
bbd9b64e
CO		 5097 val += now;
5098 bytes -= now;
5099 }
22388a3c 5100
f78146b0
AK		 5101 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5102 vcpu, ops);
5103 if (rc != X86EMUL_CONTINUE)
5104 return rc;
5105
5106 if (!vcpu->mmio_nr_fragments)
5107 return rc;
5108
5109 gpa = vcpu->mmio_fragments[0].gpa;
5110
5111 vcpu->mmio_needed = 1;
5112 vcpu->mmio_cur_fragment = 0;
5113
87da7e66 5114 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5115 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5116 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5117 vcpu->run->mmio.phys_addr = gpa;
5118
5119 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5120}
5121
5122static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5123 unsigned long addr,
5124 void *val,
5125 unsigned int bytes,
5126 struct x86_exception *exception)
5127{
5128 return emulator_read_write(ctxt, addr, val, bytes,
5129 exception, &read_emultor);
5130}
5131
52eb5a6d 5132static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5133 unsigned long addr,
5134 const void *val,
5135 unsigned int bytes,
5136 struct x86_exception *exception)
5137{
5138 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5139 exception, &write_emultor);
bbd9b64e 5140}
bbd9b64e 5141
daea3e73
AK		 5142#define CMPXCHG_TYPE(t, ptr, old, new) \
5143 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5144
5145#ifdef CONFIG_X86_64
5146# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5147#else
5148# define CMPXCHG64(ptr, old, new) \
9749a6c0 5149 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5150#endif
5151
0f65dd70
AK		 5152static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5153 unsigned long addr,
bbd9b64e
CO		 5154 const void *old,
5155 const void *new,
5156 unsigned int bytes,
0f65dd70 5157 struct x86_exception *exception)
bbd9b64e 5158{
0f65dd70 5159 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 5160 gpa_t gpa;
5161 struct page *page;
5162 char *kaddr;
5163 bool exchanged;
2bacc55c 5164
daea3e73
AK		 5165 /* guests cmpxchg8b have to be emulated atomically */
5166 if (bytes > 8 || (bytes & (bytes - 1)))
5167 goto emul_write;
10589a46 5168
daea3e73 5169 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5170
daea3e73
AK		 5171 if (gpa == UNMAPPED_GVA ||
5172 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5173 goto emul_write;
2bacc55c 5174
daea3e73
AK		 5175 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5176 goto emul_write;
72dc67a6 5177
54bf36aa 5178 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 5179 if (is_error_page(page))
c19b8bd6 5180 goto emul_write;
72dc67a6 5181
8fd75e12 5182 kaddr = kmap_atomic(page);
daea3e73
AK		 5183 kaddr += offset_in_page(gpa);
5184 switch (bytes) {
5185 case 1:
5186 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5187 break;
5188 case 2:
5189 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5190 break;
5191 case 4:
5192 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5193 break;
5194 case 8:
5195 exchanged = CMPXCHG64(kaddr, old, new);
5196 break;
5197 default:
5198 BUG();
2bacc55c 5199 }
8fd75e12 5200 kunmap_atomic(kaddr);
daea3e73
AK		 5201 kvm_release_page_dirty(page);
5202
5203 if (!exchanged)
5204 return X86EMUL_CMPXCHG_FAILED;
5205
54bf36aa 5206 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 5207 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5208
5209 return X86EMUL_CONTINUE;
4a5f48f6 5210
3200f405 5211emul_write:
daea3e73 5212 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5213
0f65dd70 5214 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5215}
5216
cf8f70bf
GN		 5217static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5218{
cbfc6c91 5219 int r = 0, i;
cf8f70bf 5220
cbfc6c91
WL		 5221 for (i = 0; i < vcpu->arch.pio.count; i++) {
5222 if (vcpu->arch.pio.in)
5223 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5224 vcpu->arch.pio.size, pd);
5225 else
5226 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5227 vcpu->arch.pio.port, vcpu->arch.pio.size,
5228 pd);
5229 if (r)
5230 break;
5231 pd += vcpu->arch.pio.size;
5232 }
cf8f70bf
GN		 5233 return r;
5234}
5235
6f6fbe98
XG		 5236static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5237 unsigned short port, void *val,
5238 unsigned int count, bool in)
cf8f70bf 5239{
cf8f70bf 5240 vcpu->arch.pio.port = port;
6f6fbe98 5241 vcpu->arch.pio.in = in;
7972995b 5242 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5243 vcpu->arch.pio.size = size;
5244
5245 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5246 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5247 return 1;
5248 }
5249
5250 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5251 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5252 vcpu->run->io.size = size;
5253 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5254 vcpu->run->io.count = count;
5255 vcpu->run->io.port = port;
5256
5257 return 0;
5258}
5259
6f6fbe98
XG		 5260static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5261 int size, unsigned short port, void *val,
5262 unsigned int count)
cf8f70bf 5263{
ca1d4a9e 5264 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5265 int ret;
ca1d4a9e 5266
6f6fbe98
XG		 5267 if (vcpu->arch.pio.count)
5268 goto data_avail;
cf8f70bf 5269
cbfc6c91
WL		 5270 memset(vcpu->arch.pio_data, 0, size * count);
5271
6f6fbe98
XG		 5272 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5273 if (ret) {
5274data_avail:
5275 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5276 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5277 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5278 return 1;
5279 }
5280
cf8f70bf
GN		 5281 return 0;
5282}
5283
6f6fbe98
XG		 5284static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5285 int size, unsigned short port,
5286 const void *val, unsigned int count)
5287{
5288 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5289
5290 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5291 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5292 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5293}
5294
bbd9b64e
CO		 5295static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5296{
5297 return kvm_x86_ops->get_segment_base(vcpu, seg);
5298}
5299
3cb16fe7 5300static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5301{
3cb16fe7 5302 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5303}
5304
ae6a2375 5305static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5306{
5307 if (!need_emulate_wbinvd(vcpu))
5308 return X86EMUL_CONTINUE;
5309
5310 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5311 int cpu = get_cpu();
5312
5313 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5314 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5315 wbinvd_ipi, NULL, 1);
2eec7343 5316 put_cpu();
f5f48ee1 5317 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5318 } else
5319 wbinvd();
f5f48ee1
SY		 5320 return X86EMUL_CONTINUE;
5321}
5cb56059
JS		 5322
5323int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5324{
6affcbed
KH		 5325 kvm_emulate_wbinvd_noskip(vcpu);
5326 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5327}
f5f48ee1
SY		 5328EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5329
5cb56059
JS		 5330
5331
bcaf5cc5
AK		 5332static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5333{
5cb56059 5334 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5335}
5336
52eb5a6d
XL		 5337static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5338 unsigned long *dest)
bbd9b64e 5339{
16f8a6f9 5340 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5341}
5342
52eb5a6d
XL		 5343static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5344 unsigned long value)
bbd9b64e 5345{
338dbc97 5346
717746e3 5347 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5348}
5349
52a46617 5350static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5351{
52a46617 5352 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5353}
5354
717746e3 5355static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5356{
717746e3 5357 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5358 unsigned long value;
5359
5360 switch (cr) {
5361 case 0:
5362 value = kvm_read_cr0(vcpu);
5363 break;
5364 case 2:
5365 value = vcpu->arch.cr2;
5366 break;
5367 case 3:
9f8fe504 5368 value = kvm_read_cr3(vcpu);
52a46617
GN		 5369 break;
5370 case 4:
5371 value = kvm_read_cr4(vcpu);
5372 break;
5373 case 8:
5374 value = kvm_get_cr8(vcpu);
5375 break;
5376 default:
a737f256 5377 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5378 return 0;
5379 }
5380
5381 return value;
5382}
5383
717746e3 5384static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5385{
717746e3 5386 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5387 int res = 0;
5388
52a46617
GN		 5389 switch (cr) {
5390 case 0:
49a9b07e 5391 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5392 break;
5393 case 2:
5394 vcpu->arch.cr2 = val;
5395 break;
5396 case 3:
2390218b 5397 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5398 break;
5399 case 4:
a83b29c6 5400 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5401 break;
5402 case 8:
eea1cff9 5403 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5404 break;
5405 default:
a737f256 5406 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5407 res = -1;
52a46617 5408 }
0f12244f
GN		 5409
5410 return res;
52a46617
GN		 5411}
5412
717746e3 5413static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5414{
717746e3 5415 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5416}
5417
4bff1e86 5418static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5419{
4bff1e86 5420 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5421}
5422
4bff1e86 5423static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5424{
4bff1e86 5425 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5426}
5427
1ac9d0cf
AK		 5428static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5429{
5430 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5431}
5432
5433static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5434{
5435 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5436}
5437
4bff1e86
AK		 5438static unsigned long emulator_get_cached_segment_base(
5439 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5440{
4bff1e86 5441 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5442}
5443
1aa36616
AK		 5444static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5445 struct desc_struct *desc, u32 *base3,
5446 int seg)
2dafc6c2
GN		 5447{
5448 struct kvm_segment var;
5449
4bff1e86 5450 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5451 *selector = var.selector;
2dafc6c2 5452
378a8b09
GN		 5453 if (var.unusable) {
5454 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5455 if (base3)
5456 *base3 = 0;
2dafc6c2 5457 return false;
378a8b09 5458 }
2dafc6c2
GN		 5459
5460 if (var.g)
5461 var.limit >>= 12;
5462 set_desc_limit(desc, var.limit);
5463 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5464#ifdef CONFIG_X86_64
5465 if (base3)
5466 *base3 = var.base >> 32;
5467#endif
2dafc6c2
GN		 5468 desc->type = var.type;
5469 desc->s = var.s;
5470 desc->dpl = var.dpl;
5471 desc->p = var.present;
5472 desc->avl = var.avl;
5473 desc->l = var.l;
5474 desc->d = var.db;
5475 desc->g = var.g;
5476
5477 return true;
5478}
5479
1aa36616
AK		 5480static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5481 struct desc_struct *desc, u32 base3,
5482 int seg)
2dafc6c2 5483{
4bff1e86 5484 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5485 struct kvm_segment var;
5486
1aa36616 5487 var.selector = selector;
2dafc6c2 5488 var.base = get_desc_base(desc);
5601d05b
GN		 5489#ifdef CONFIG_X86_64
5490 var.base |= ((u64)base3) << 32;
5491#endif
2dafc6c2
GN		 5492 var.limit = get_desc_limit(desc);
5493 if (desc->g)
5494 var.limit = (var.limit << 12) | 0xfff;
5495 var.type = desc->type;
2dafc6c2
GN		 5496 var.dpl = desc->dpl;
5497 var.db = desc->d;
5498 var.s = desc->s;
5499 var.l = desc->l;
5500 var.g = desc->g;
5501 var.avl = desc->avl;
5502 var.present = desc->p;
5503 var.unusable = !var.present;
5504 var.padding = 0;
5505
5506 kvm_set_segment(vcpu, &var, seg);
5507 return;
5508}
5509
717746e3
AK		 5510static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5511 u32 msr_index, u64 *pdata)
5512{
609e36d3
PB		 5513 struct msr_data msr;
5514 int r;
5515
5516 msr.index = msr_index;
5517 msr.host_initiated = false;
5518 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5519 if (r)
5520 return r;
5521
5522 *pdata = msr.data;
5523 return 0;
717746e3
AK		 5524}
5525
5526static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5527 u32 msr_index, u64 data)
5528{
8fe8ab46
WA		 5529 struct msr_data msr;
5530
5531 msr.data = data;
5532 msr.index = msr_index;
5533 msr.host_initiated = false;
5534 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5535}
5536
64d60670
PB		 5537static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5538{
5539 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5540
5541 return vcpu->arch.smbase;
5542}
5543
5544static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5545{
5546 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5547
5548 vcpu->arch.smbase = smbase;
5549}
5550
67f4d428
NA		 5551static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5552 u32 pmc)
5553{
c6702c9d 5554 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5555}
5556
222d21aa
AK		 5557static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5558 u32 pmc, u64 *pdata)
5559{
c6702c9d 5560 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5561}
5562
6c3287f7
AK		 5563static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5564{
5565 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5566}
5567
2953538e 5568static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5569 struct x86_instruction_info *info,
c4f035c6
AK		 5570 enum x86_intercept_stage stage)
5571{
2953538e 5572 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5573}
5574
e911eb3b
YZ		 5575static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5576 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5577{
e911eb3b 5578 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5579}
5580
dd856efa
AK		 5581static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5582{
5583 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5584}
5585
5586static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5587{
5588 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5589}
5590
801806d9
NA		 5591static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5592{
5593 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5594}
5595
6ed071f0
LP		 5596static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5597{
5598 return emul_to_vcpu(ctxt)->arch.hflags;
5599}
5600
5601static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5602{
5603 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5604}
5605
0234bf88
LP		 5606static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5607{
5608 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5609}
5610
0225fb50 5611static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5612 .read_gpr = emulator_read_gpr,
5613 .write_gpr = emulator_write_gpr,
1871c602 5614 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5615 .write_std = kvm_write_guest_virt_system,
7a036a6f 5616 .read_phys = kvm_read_guest_phys_system,
1871c602 5617 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5618 .read_emulated = emulator_read_emulated,
5619 .write_emulated = emulator_write_emulated,
5620 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5621 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5622 .pio_in_emulated = emulator_pio_in_emulated,
5623 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5624 .get_segment = emulator_get_segment,
5625 .set_segment = emulator_set_segment,
5951c442 5626 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5627 .get_gdt = emulator_get_gdt,
160ce1f1 5628 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5629 .set_gdt = emulator_set_gdt,
5630 .set_idt = emulator_set_idt,
52a46617
GN		 5631 .get_cr = emulator_get_cr,
5632 .set_cr = emulator_set_cr,
9c537244 5633 .cpl = emulator_get_cpl,
35aa5375
GN		 5634 .get_dr = emulator_get_dr,
5635 .set_dr = emulator_set_dr,
64d60670
PB		 5636 .get_smbase = emulator_get_smbase,
5637 .set_smbase = emulator_set_smbase,
717746e3
AK		 5638 .set_msr = emulator_set_msr,
5639 .get_msr = emulator_get_msr,
67f4d428 5640 .check_pmc = emulator_check_pmc,
222d21aa 5641 .read_pmc = emulator_read_pmc,
6c3287f7 5642 .halt = emulator_halt,
bcaf5cc5 5643 .wbinvd = emulator_wbinvd,
d6aa1000 5644 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5645 .intercept = emulator_intercept,
bdb42f5a 5646 .get_cpuid = emulator_get_cpuid,
801806d9 5647 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5648 .get_hflags = emulator_get_hflags,
5649 .set_hflags = emulator_set_hflags,
0234bf88 5650 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5651};
5652
95cb2295
GN		 5653static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5654{
37ccdcbe 5655 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5656 /*
5657 * an sti; sti; sequence only disable interrupts for the first
5658 * instruction. So, if the last instruction, be it emulated or
5659 * not, left the system with the INT_STI flag enabled, it
5660 * means that the last instruction is an sti. We should not
5661 * leave the flag on in this case. The same goes for mov ss
5662 */
37ccdcbe
PB		 5663 if (int_shadow & mask)
5664 mask = 0;
6addfc42 5665 if (unlikely(int_shadow || mask)) {
95cb2295 5666 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5667 if (!mask)
5668 kvm_make_request(KVM_REQ_EVENT, vcpu);
5669 }
95cb2295
GN		 5670}
5671
ef54bcfe 5672static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5673{
5674 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5675 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5676 return kvm_propagate_fault(vcpu, &ctxt->exception);
5677
5678 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5679 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5680 ctxt->exception.error_code);
54b8486f 5681 else
da9cb575 5682 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5683 return false;
54b8486f
GN		 5684}
5685
8ec4722d
MG		 5686static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5687{
adf52235 5688 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5689 int cs_db, cs_l;
5690
8ec4722d
MG		 5691 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5692
adf52235 5693 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5694 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5695
adf52235
TY		 5696 ctxt->eip = kvm_rip_read(vcpu);
5697 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5698 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5699 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5700 cs_db ? X86EMUL_MODE_PROT32 :
5701 X86EMUL_MODE_PROT16;
a584539b 5702 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5703 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5704 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5705
dd856efa 5706 init_decode_cache(ctxt);
7ae441ea 5707 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5708}
5709
71f9833b 5710int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5711{
9d74191a 5712 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5713 int ret;
5714
5715 init_emulate_ctxt(vcpu);
5716
9dac77fa
AK		 5717 ctxt->op_bytes = 2;
5718 ctxt->ad_bytes = 2;
5719 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5720 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5721
5722 if (ret != X86EMUL_CONTINUE)
5723 return EMULATE_FAIL;
5724
9dac77fa 5725 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5726 kvm_rip_write(vcpu, ctxt->eip);
5727 kvm_set_rflags(vcpu, ctxt->eflags);
63995653 5728
63995653
MG		 5729 return EMULATE_DONE;
5730}
5731EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5732
e2366171 5733static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 5734{
fc3a9157
JR		 5735 int r = EMULATE_DONE;
5736
6d77dbfc
GN		 5737 ++vcpu->stat.insn_emulation_fail;
5738 trace_kvm_emulate_insn_failed(vcpu);
e2366171
LA		 5739
5740 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
5741 return EMULATE_FAIL;
5742
a2b9e6c1 5743 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5744 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5745 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5746 vcpu->run->internal.ndata = 0;
1f4dcb3b 5747 r = EMULATE_USER_EXIT;
fc3a9157 5748 }
e2366171 5749
6d77dbfc 5750 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5751
5752 return r;
6d77dbfc
GN		 5753}
5754
93c05d3e 5755static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5756 bool write_fault_to_shadow_pgtable,
5757 int emulation_type)
a6f177ef 5758{
95b3cf69 5759 gpa_t gpa = cr2;
ba049e93 5760 kvm_pfn_t pfn;
a6f177ef 5761
991eebf9
GN		 5762 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5763 return false;
5764
95b3cf69
XG		 5765 if (!vcpu->arch.mmu.direct_map) {
5766 /*
5767 * Write permission should be allowed since only
5768 * write access need to be emulated.
5769 */
5770 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5771
95b3cf69
XG		 5772 /*
5773 * If the mapping is invalid in guest, let cpu retry
5774 * it to generate fault.
5775 */
5776 if (gpa == UNMAPPED_GVA)
5777 return true;
5778 }
a6f177ef 5779
8e3d9d06
XG		 5780 /*
5781 * Do not retry the unhandleable instruction if it faults on the
5782 * readonly host memory, otherwise it will goto a infinite loop:
5783 * retry instruction -> write #PF -> emulation fail -> retry
5784 * instruction -> ...
5785 */
5786 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5787
5788 /*
5789 * If the instruction failed on the error pfn, it can not be fixed,
5790 * report the error to userspace.
5791 */
5792 if (is_error_noslot_pfn(pfn))
5793 return false;
5794
5795 kvm_release_pfn_clean(pfn);
5796
5797 /* The instructions are well-emulated on direct mmu. */
5798 if (vcpu->arch.mmu.direct_map) {
5799 unsigned int indirect_shadow_pages;
5800
5801 spin_lock(&vcpu->kvm->mmu_lock);
5802 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5803 spin_unlock(&vcpu->kvm->mmu_lock);
5804
5805 if (indirect_shadow_pages)
5806 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5807
a6f177ef 5808 return true;
8e3d9d06 5809 }
a6f177ef 5810
95b3cf69
XG		 5811 /*
5812 * if emulation was due to access to shadowed page table
5813 * and it failed try to unshadow page and re-enter the
5814 * guest to let CPU execute the instruction.
5815 */
5816 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5817
5818 /*
5819 * If the access faults on its page table, it can not
5820 * be fixed by unprotecting shadow page and it should
5821 * be reported to userspace.
5822 */
5823 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5824}
5825
1cb3f3ae
XG		 5826static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5827 unsigned long cr2, int emulation_type)
5828{
5829 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5830 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5831
5832 last_retry_eip = vcpu->arch.last_retry_eip;
5833 last_retry_addr = vcpu->arch.last_retry_addr;
5834
5835 /*
5836 * If the emulation is caused by #PF and it is non-page_table
5837 * writing instruction, it means the VM-EXIT is caused by shadow
5838 * page protected, we can zap the shadow page and retry this
5839 * instruction directly.
5840 *
5841 * Note: if the guest uses a non-page-table modifying instruction
5842 * on the PDE that points to the instruction, then we will unmap
5843 * the instruction and go to an infinite loop. So, we cache the
5844 * last retried eip and the last fault address, if we meet the eip
5845 * and the address again, we can break out of the potential infinite
5846 * loop.
5847 */
5848 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5849
5850 if (!(emulation_type & EMULTYPE_RETRY))
5851 return false;
5852
5853 if (x86_page_table_writing_insn(ctxt))
5854 return false;
5855
5856 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5857 return false;
5858
5859 vcpu->arch.last_retry_eip = ctxt->eip;
5860 vcpu->arch.last_retry_addr = cr2;
5861
5862 if (!vcpu->arch.mmu.direct_map)
5863 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5864
22368028 5865 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5866
5867 return true;
5868}
5869
716d51ab
GN		 5870static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5871static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5872
64d60670 5873static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5874{
64d60670 5875 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5876 /* This is a good place to trace that we are exiting SMM. */
5877 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5878
c43203ca
PB		 5879 /* Process a latched INIT or SMI, if any. */
5880 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5881 }
699023e2
PB		 5882
5883 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5884}
5885
5886static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5887{
5888 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5889
a584539b 5890 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5891
5892 if (changed & HF_SMM_MASK)
5893 kvm_smm_changed(vcpu);
a584539b
PB		 5894}
5895
4a1e10d5
PB		 5896static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5897 unsigned long *db)
5898{
5899 u32 dr6 = 0;
5900 int i;
5901 u32 enable, rwlen;
5902
5903 enable = dr7;
5904 rwlen = dr7 >> 16;
5905 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5906 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5907 dr6 |= (1 << i);
5908 return dr6;
5909}
5910
c8401dda 5911static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5912{
5913 struct kvm_run *kvm_run = vcpu->run;
5914
c8401dda
PB		 5915 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5916 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5917 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5918 kvm_run->debug.arch.exception = DB_VECTOR;
5919 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5920 *r = EMULATE_USER_EXIT;
5921 } else {
5922 /*
5923 * "Certain debug exceptions may clear bit 0-3. The
5924 * remaining contents of the DR6 register are never
5925 * cleared by the processor".
5926 */
5927 vcpu->arch.dr6 &= ~15;
5928 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5929 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5930 }
5931}
5932
6affcbed
KH		 5933int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5934{
5935 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5936 int r = EMULATE_DONE;
5937
5938 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5939
5940 /*
5941 * rflags is the old, "raw" value of the flags. The new value has
5942 * not been saved yet.
5943 *
5944 * This is correct even for TF set by the guest, because "the
5945 * processor will not generate this exception after the instruction
5946 * that sets the TF flag".
5947 */
5948 if (unlikely(rflags & X86_EFLAGS_TF))
5949 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5950 return r == EMULATE_DONE;
5951}
5952EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5953
4a1e10d5
PB		 5954static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5955{
4a1e10d5
PB		 5956 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5957 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5958 struct kvm_run *kvm_run = vcpu->run;
5959 unsigned long eip = kvm_get_linear_rip(vcpu);
5960 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5961 vcpu->arch.guest_debug_dr7,
5962 vcpu->arch.eff_db);
5963
5964 if (dr6 != 0) {
6f43ed01 5965 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5966 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5967 kvm_run->debug.arch.exception = DB_VECTOR;
5968 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5969 *r = EMULATE_USER_EXIT;
5970 return true;
5971 }
5972 }
5973
4161a569
NA		 5974 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5975 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5976 unsigned long eip = kvm_get_linear_rip(vcpu);
5977 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5978 vcpu->arch.dr7,
5979 vcpu->arch.db);
5980
5981 if (dr6 != 0) {
5982 vcpu->arch.dr6 &= ~15;
6f43ed01 5983 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5984 kvm_queue_exception(vcpu, DB_VECTOR);
5985 *r = EMULATE_DONE;
5986 return true;
5987 }
5988 }
5989
5990 return false;
5991}
5992
04789b66
LA		 5993static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
5994{
2d7921c4
AM		 5995 switch (ctxt->opcode_len) {
5996 case 1:
5997 switch (ctxt->b) {
5998 case 0xe4: /* IN */
5999 case 0xe5:
6000 case 0xec:
6001 case 0xed:
6002 case 0xe6: /* OUT */
6003 case 0xe7:
6004 case 0xee:
6005 case 0xef:
6006 case 0x6c: /* INS */
6007 case 0x6d:
6008 case 0x6e: /* OUTS */
6009 case 0x6f:
6010 return true;
6011 }
6012 break;
6013 case 2:
6014 switch (ctxt->b) {
6015 case 0x33: /* RDPMC */
6016 return true;
6017 }
6018 break;
04789b66
LA		 6019 }
6020
6021 return false;
6022}
6023
51d8b661
AP		 6024int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6025 unsigned long cr2,
dc25e89e
AP		 6026 int emulation_type,
6027 void *insn,
6028 int insn_len)
bbd9b64e 6029{
95cb2295 6030 int r;
9d74191a 6031 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 6032 bool writeback = true;
93c05d3e 6033 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 6034
93c05d3e
XG		 6035 /*
6036 * Clear write_fault_to_shadow_pgtable here to ensure it is
6037 * never reused.
6038 */
6039 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 6040 kvm_clear_exception_queue(vcpu);
8d7d8102 6041
571008da 6042 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 6043 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 6044
6045 /*
6046 * We will reenter on the same instruction since
6047 * we do not set complete_userspace_io. This does not
6048 * handle watchpoints yet, those would be handled in
6049 * the emulate_ops.
6050 */
d391f120
VK		 6051 if (!(emulation_type & EMULTYPE_SKIP) &&
6052 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 6053 return r;
6054
9d74191a
TY		 6055 ctxt->interruptibility = 0;
6056 ctxt->have_exception = false;
e0ad0b47 6057 ctxt->exception.vector = -1;
9d74191a 6058 ctxt->perm_ok = false;
bbd9b64e 6059
b51e974f 6060 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 6061
9d74191a 6062 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 6063
e46479f8 6064 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 6065 ++vcpu->stat.insn_emulation;
1d2887e2 6066 if (r != EMULATION_OK) {
4005996e
AK		 6067 if (emulation_type & EMULTYPE_TRAP_UD)
6068 return EMULATE_FAIL;
991eebf9
GN		 6069 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6070 emulation_type))
bbd9b64e 6071 return EMULATE_DONE;
6ea6e843
PB		 6072 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6073 return EMULATE_DONE;
6d77dbfc
GN		 6074 if (emulation_type & EMULTYPE_SKIP)
6075 return EMULATE_FAIL;
e2366171 6076 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6077 }
6078 }
6079
04789b66
LA		 6080 if ((emulation_type & EMULTYPE_VMWARE) &&
6081 !is_vmware_backdoor_opcode(ctxt))
6082 return EMULATE_FAIL;
6083
ba8afb6b 6084 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6085 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6086 if (ctxt->eflags & X86_EFLAGS_RF)
6087 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 6088 return EMULATE_DONE;
6089 }
6090
1cb3f3ae
XG		 6091 if (retry_instruction(ctxt, cr2, emulation_type))
6092 return EMULATE_DONE;
6093
7ae441ea 6094 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6095 changes registers values during IO operation */
7ae441ea
GN		 6096 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6097 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6098 emulator_invalidate_register_cache(ctxt);
7ae441ea 6099 }
4d2179e1 6100
5cd21917 6101restart:
0f89b207
TL		 6102 /* Save the faulting GPA (cr2) in the address field */
6103 ctxt->exception.address = cr2;
6104
9d74191a 6105 r = x86_emulate_insn(ctxt);
bbd9b64e 6106
775fde86
JR		 6107 if (r == EMULATION_INTERCEPTED)
6108 return EMULATE_DONE;
6109
d2ddd1c4 6110 if (r == EMULATION_FAILED) {
991eebf9
GN		 6111 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6112 emulation_type))
c3cd7ffa
GN		 6113 return EMULATE_DONE;
6114
e2366171 6115 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6116 }
6117
9d74191a 6118 if (ctxt->have_exception) {
d2ddd1c4 6119 r = EMULATE_DONE;
ef54bcfe
PB		 6120 if (inject_emulated_exception(vcpu))
6121 return r;
d2ddd1c4 6122 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6123 if (!vcpu->arch.pio.in) {
6124 /* FIXME: return into emulator if single-stepping. */
3457e419 6125 vcpu->arch.pio.count = 0;
0912c977 6126 } else {
7ae441ea 6127 writeback = false;
716d51ab
GN		 6128 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6129 }
ac0a48c3 6130 r = EMULATE_USER_EXIT;
7ae441ea
GN		 6131 } else if (vcpu->mmio_needed) {
6132 if (!vcpu->mmio_is_write)
6133 writeback = false;
ac0a48c3 6134 r = EMULATE_USER_EXIT;
716d51ab 6135 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6136 } else if (r == EMULATION_RESTART)
5cd21917 6137 goto restart;
d2ddd1c4
GN		 6138 else
6139 r = EMULATE_DONE;
f850e2e6 6140
7ae441ea 6141 if (writeback) {
6addfc42 6142 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6143 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6144 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 6145 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 6146 if (r == EMULATE_DONE &&
6147 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
6148 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 6149 if (!ctxt->have_exception ||
6150 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6151 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 6152
6153 /*
6154 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6155 * do nothing, and it will be requested again as soon as
6156 * the shadow expires. But we still need to check here,
6157 * because POPF has no interrupt shadow.
6158 */
6159 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6160 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6161 } else
6162 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6163
6164 return r;
de7d789a 6165}
51d8b661 6166EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 6167
dca7f128
SC		 6168static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6169 unsigned short port)
de7d789a 6170{
cf8f70bf 6171 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 6172 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6173 size, port, &val, 1);
cf8f70bf 6174 /* do not return to emulator after return from userspace */
7972995b 6175 vcpu->arch.pio.count = 0;
de7d789a
CO		 6176 return ret;
6177}
de7d789a 6178
8370c3d0
TL		 6179static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6180{
6181 unsigned long val;
6182
6183 /* We should only ever be called with arch.pio.count equal to 1 */
6184 BUG_ON(vcpu->arch.pio.count != 1);
6185
6186 /* For size less than 4 we merge, else we zero extend */
6187 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6188 : 0;
6189
6190 /*
6191 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6192 * the copy and tracing
6193 */
6194 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6195 vcpu->arch.pio.port, &val, 1);
6196 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6197
6198 return 1;
6199}
6200
dca7f128
SC		 6201static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6202 unsigned short port)
8370c3d0
TL		 6203{
6204 unsigned long val;
6205 int ret;
6206
6207 /* For size less than 4 we merge, else we zero extend */
6208 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6209
6210 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6211 &val, 1);
6212 if (ret) {
6213 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6214 return ret;
6215 }
6216
6217 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6218
6219 return 0;
6220}
dca7f128
SC		 6221
6222int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6223{
6224 int ret = kvm_skip_emulated_instruction(vcpu);
6225
6226 /*
6227 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6228 * KVM_EXIT_DEBUG here.
6229 */
6230 if (in)
6231 return kvm_fast_pio_in(vcpu, size, port) && ret;
6232 else
6233 return kvm_fast_pio_out(vcpu, size, port) && ret;
6234}
6235EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 6236
251a5fd6 6237static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6238{
0a3aee0d 6239 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6240 return 0;
8cfdc000
ZA		 6241}
6242
6243static void tsc_khz_changed(void *data)
c8076604 6244{
8cfdc000
ZA		 6245 struct cpufreq_freqs *freq = data;
6246 unsigned long khz = 0;
6247
6248 if (data)
6249 khz = freq->new;
6250 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6251 khz = cpufreq_quick_get(raw_smp_processor_id());
6252 if (!khz)
6253 khz = tsc_khz;
0a3aee0d 6254 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6255}
6256
5fa4ec9c 6257#ifdef CONFIG_X86_64
0092e434
VK		 6258static void kvm_hyperv_tsc_notifier(void)
6259{
0092e434
VK		 6260 struct kvm *kvm;
6261 struct kvm_vcpu *vcpu;
6262 int cpu;
6263
6264 spin_lock(&kvm_lock);
6265 list_for_each_entry(kvm, &vm_list, vm_list)
6266 kvm_make_mclock_inprogress_request(kvm);
6267
6268 hyperv_stop_tsc_emulation();
6269
6270 /* TSC frequency always matches when on Hyper-V */
6271 for_each_present_cpu(cpu)
6272 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6273 kvm_max_guest_tsc_khz = tsc_khz;
6274
6275 list_for_each_entry(kvm, &vm_list, vm_list) {
6276 struct kvm_arch *ka = &kvm->arch;
6277
6278 spin_lock(&ka->pvclock_gtod_sync_lock);
6279
6280 pvclock_update_vm_gtod_copy(kvm);
6281
6282 kvm_for_each_vcpu(cpu, vcpu, kvm)
6283 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6284
6285 kvm_for_each_vcpu(cpu, vcpu, kvm)
6286 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6287
6288 spin_unlock(&ka->pvclock_gtod_sync_lock);
6289 }
6290 spin_unlock(&kvm_lock);
0092e434 6291}
5fa4ec9c 6292#endif
0092e434 6293
c8076604
GH		 6294static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6295 void *data)
6296{
6297 struct cpufreq_freqs *freq = data;
6298 struct kvm *kvm;
6299 struct kvm_vcpu *vcpu;
6300 int i, send_ipi = 0;
6301
8cfdc000
ZA		 6302 /*
6303 * We allow guests to temporarily run on slowing clocks,
6304 * provided we notify them after, or to run on accelerating
6305 * clocks, provided we notify them before. Thus time never
6306 * goes backwards.
6307 *
6308 * However, we have a problem. We can't atomically update
6309 * the frequency of a given CPU from this function; it is
6310 * merely a notifier, which can be called from any CPU.
6311 * Changing the TSC frequency at arbitrary points in time
6312 * requires a recomputation of local variables related to
6313 * the TSC for each VCPU. We must flag these local variables
6314 * to be updated and be sure the update takes place with the
6315 * new frequency before any guests proceed.
6316 *
6317 * Unfortunately, the combination of hotplug CPU and frequency
6318 * change creates an intractable locking scenario; the order
6319 * of when these callouts happen is undefined with respect to
6320 * CPU hotplug, and they can race with each other. As such,
6321 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6322 * undefined; you can actually have a CPU frequency change take
6323 * place in between the computation of X and the setting of the
6324 * variable. To protect against this problem, all updates of
6325 * the per_cpu tsc_khz variable are done in an interrupt
6326 * protected IPI, and all callers wishing to update the value
6327 * must wait for a synchronous IPI to complete (which is trivial
6328 * if the caller is on the CPU already). This establishes the
6329 * necessary total order on variable updates.
6330 *
6331 * Note that because a guest time update may take place
6332 * anytime after the setting of the VCPU's request bit, the
6333 * correct TSC value must be set before the request. However,
6334 * to ensure the update actually makes it to any guest which
6335 * starts running in hardware virtualization between the set
6336 * and the acquisition of the spinlock, we must also ping the
6337 * CPU after setting the request bit.
6338 *
6339 */
6340
c8076604
GH		 6341 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6342 return 0;
6343 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6344 return 0;
8cfdc000
ZA		 6345
6346 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 6347
2f303b74 6348 spin_lock(&kvm_lock);
c8076604 6349 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6350 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 6351 if (vcpu->cpu != freq->cpu)
6352 continue;
c285545f 6353 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 6354 if (vcpu->cpu != smp_processor_id())
8cfdc000 6355 send_ipi = 1;
c8076604
GH		 6356 }
6357 }
2f303b74 6358 spin_unlock(&kvm_lock);
c8076604
GH		 6359
6360 if (freq->old < freq->new && send_ipi) {
6361 /*
6362 * We upscale the frequency. Must make the guest
6363 * doesn't see old kvmclock values while running with
6364 * the new frequency, otherwise we risk the guest sees
6365 * time go backwards.
6366 *
6367 * In case we update the frequency for another cpu
6368 * (which might be in guest context) send an interrupt
6369 * to kick the cpu out of guest context. Next time
6370 * guest context is entered kvmclock will be updated,
6371 * so the guest will not see stale values.
6372 */
8cfdc000 6373 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 6374 }
6375 return 0;
6376}
6377
6378static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6379 .notifier_call = kvmclock_cpufreq_notifier
6380};
6381
251a5fd6 6382static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6383{
251a5fd6
SAS		 6384 tsc_khz_changed(NULL);
6385 return 0;
8cfdc000
ZA		 6386}
6387
b820cc0c
ZA		 6388static void kvm_timer_init(void)
6389{
c285545f 6390 max_tsc_khz = tsc_khz;
460dd42e 6391
b820cc0c 6392 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6393#ifdef CONFIG_CPU_FREQ
6394 struct cpufreq_policy policy;
758f588d
BP		 6395 int cpu;
6396
c285545f 6397 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6398 cpu = get_cpu();
6399 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6400 if (policy.cpuinfo.max_freq)
6401 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6402 put_cpu();
c285545f 6403#endif
b820cc0c
ZA		 6404 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6405 CPUFREQ_TRANSITION_NOTIFIER);
6406 }
c285545f 6407 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6408
73c1b41e 6409 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6410 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6411}
6412
dd60d217
AK		 6413DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6414EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
ff9d07a0 6415
f5132b01 6416int kvm_is_in_guest(void)
ff9d07a0 6417{
086c9855 6418 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6419}
6420
6421static int kvm_is_user_mode(void)
6422{
6423 int user_mode = 3;
dcf46b94 6424
086c9855
AS		 6425 if (__this_cpu_read(current_vcpu))
6426 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6427
ff9d07a0
ZY		 6428 return user_mode != 0;
6429}
6430
6431static unsigned long kvm_get_guest_ip(void)
6432{
6433 unsigned long ip = 0;
dcf46b94 6434
086c9855
AS		 6435 if (__this_cpu_read(current_vcpu))
6436 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6437
ff9d07a0
ZY		 6438 return ip;
6439}
6440
6441static struct perf_guest_info_callbacks kvm_guest_cbs = {
6442 .is_in_guest = kvm_is_in_guest,
6443 .is_user_mode = kvm_is_user_mode,
6444 .get_guest_ip = kvm_get_guest_ip,
6445};
6446
ce88decf
XG		 6447static void kvm_set_mmio_spte_mask(void)
6448{
6449 u64 mask;
6450 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6451
6452 /*
6453 * Set the reserved bits and the present bit of an paging-structure
6454 * entry to generate page fault with PFER.RSV = 1.
6455 */
885032b9 6456 /* Mask the reserved physical address bits. */
d1431483 6457 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6458
885032b9 6459 /* Set the present bit. */
ce88decf
XG		 6460 mask |= 1ull;
6461
6462#ifdef CONFIG_X86_64
6463 /*
6464 * If reserved bit is not supported, clear the present bit to disable
6465 * mmio page fault.
6466 */
6467 if (maxphyaddr == 52)
6468 mask &= ~1ull;
6469#endif
6470
dcdca5fe 6471 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6472}
6473
16e8d74d
MT		 6474#ifdef CONFIG_X86_64
6475static void pvclock_gtod_update_fn(struct work_struct *work)
6476{
d828199e
MT		 6477 struct kvm *kvm;
6478
6479 struct kvm_vcpu *vcpu;
6480 int i;
6481
2f303b74 6482 spin_lock(&kvm_lock);
d828199e
MT		 6483 list_for_each_entry(kvm, &vm_list, vm_list)
6484 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6485 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6486 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6487 spin_unlock(&kvm_lock);
16e8d74d
MT		 6488}
6489
6490static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6491
6492/*
6493 * Notification about pvclock gtod data update.
6494 */
6495static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6496 void *priv)
6497{
6498 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6499 struct timekeeper *tk = priv;
6500
6501 update_pvclock_gtod(tk);
6502
6503 /* disable master clock if host does not trust, or does not
b0c39dc6 6504 * use, TSC based clocksource.
16e8d74d 6505 */
b0c39dc6 6506 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6507 atomic_read(&kvm_guest_has_master_clock) != 0)
6508 queue_work(system_long_wq, &pvclock_gtod_work);
6509
6510 return 0;
6511}
6512
6513static struct notifier_block pvclock_gtod_notifier = {
6514 .notifier_call = pvclock_gtod_notify,
6515};
6516#endif
6517
f8c16bba 6518int kvm_arch_init(void *opaque)
043405e1 6519{
b820cc0c 6520 int r;
6b61edf7 6521 struct kvm_x86_ops *ops = opaque;
f8c16bba 6522
f8c16bba
ZX		 6523 if (kvm_x86_ops) {
6524 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6525 r = -EEXIST;
6526 goto out;
f8c16bba
ZX		 6527 }
6528
6529 if (!ops->cpu_has_kvm_support()) {
6530 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6531 r = -EOPNOTSUPP;
6532 goto out;
f8c16bba
ZX		 6533 }
6534 if (ops->disabled_by_bios()) {
6535 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6536 r = -EOPNOTSUPP;
6537 goto out;
f8c16bba
ZX		 6538 }
6539
013f6a5d
MT		 6540 r = -ENOMEM;
6541 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6542 if (!shared_msrs) {
6543 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6544 goto out;
6545 }
6546
97db56ce
AK		 6547 r = kvm_mmu_module_init();
6548 if (r)
013f6a5d 6549 goto out_free_percpu;
97db56ce 6550
ce88decf 6551 kvm_set_mmio_spte_mask();
97db56ce 6552
f8c16bba 6553 kvm_x86_ops = ops;
920c8377 6554
7b52345e 6555 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6556 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6557 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6558 kvm_timer_init();
c8076604 6559
ff9d07a0
ZY		 6560 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6561
d366bf7e 6562 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6563 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6564
c5cc421b 6565 kvm_lapic_init();
16e8d74d
MT		 6566#ifdef CONFIG_X86_64
6567 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 6568
5fa4ec9c 6569 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 6570 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 6571#endif
6572
f8c16bba 6573 return 0;
56c6d28a 6574
013f6a5d
MT		 6575out_free_percpu:
6576 free_percpu(shared_msrs);
56c6d28a 6577out:
56c6d28a 6578 return r;
043405e1 6579}
8776e519 6580
f8c16bba
ZX		 6581void kvm_arch_exit(void)
6582{
0092e434 6583#ifdef CONFIG_X86_64
5fa4ec9c 6584 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 6585 clear_hv_tscchange_cb();
6586#endif
cef84c30 6587 kvm_lapic_exit();
ff9d07a0
ZY		 6588 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6589
888d256e
JK		 6590 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6591 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6592 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6593 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6594#ifdef CONFIG_X86_64
6595 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6596#endif
f8c16bba 6597 kvm_x86_ops = NULL;
56c6d28a 6598 kvm_mmu_module_exit();
013f6a5d 6599 free_percpu(shared_msrs);
56c6d28a 6600}
f8c16bba 6601
5cb56059 6602int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6603{
6604 ++vcpu->stat.halt_exits;
35754c98 6605 if (lapic_in_kernel(vcpu)) {
a4535290 6606 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6607 return 1;
6608 } else {
6609 vcpu->run->exit_reason = KVM_EXIT_HLT;
6610 return 0;
6611 }
6612}
5cb56059
JS		 6613EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6614
6615int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6616{
6affcbed
KH		 6617 int ret = kvm_skip_emulated_instruction(vcpu);
6618 /*
6619 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6620 * KVM_EXIT_DEBUG here.
6621 */
6622 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6623}
8776e519
HB		 6624EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6625
8ef81a9a 6626#ifdef CONFIG_X86_64
55dd00a7
MT		 6627static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6628 unsigned long clock_type)
6629{
6630 struct kvm_clock_pairing clock_pairing;
899a31f5 6631 struct timespec64 ts;
80fbd89c 6632 u64 cycle;
55dd00a7
MT		 6633 int ret;
6634
6635 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6636 return -KVM_EOPNOTSUPP;
6637
6638 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6639 return -KVM_EOPNOTSUPP;
6640
6641 clock_pairing.sec = ts.tv_sec;
6642 clock_pairing.nsec = ts.tv_nsec;
6643 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6644 clock_pairing.flags = 0;
6645
6646 ret = 0;
6647 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6648 sizeof(struct kvm_clock_pairing)))
6649 ret = -KVM_EFAULT;
6650
6651 return ret;
6652}
8ef81a9a 6653#endif
55dd00a7 6654
6aef266c
SV		 6655/*
6656 * kvm_pv_kick_cpu_op: Kick a vcpu.
6657 *
6658 * @apicid - apicid of vcpu to be kicked.
6659 */
6660static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6661{
24d2166b 6662 struct kvm_lapic_irq lapic_irq;
6aef266c 6663
24d2166b
R		 6664 lapic_irq.shorthand = 0;
6665 lapic_irq.dest_mode = 0;
ebd28fcb 6666 lapic_irq.level = 0;
24d2166b 6667 lapic_irq.dest_id = apicid;
93bbf0b8 6668 lapic_irq.msi_redir_hint = false;
6aef266c 6669
24d2166b 6670 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6671 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6672}
6673
d62caabb
AS		 6674void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6675{
6676 vcpu->arch.apicv_active = false;
6677 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6678}
6679
8776e519
HB		 6680int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6681{
6682 unsigned long nr, a0, a1, a2, a3, ret;
6356ee0c 6683 int op_64_bit;
8776e519 6684
6356ee0c
MR		 6685 if (kvm_hv_hypercall_enabled(vcpu->kvm)) {
6686 if (!kvm_hv_hypercall(vcpu))
6687 return 0;
6688 goto out;
6689 }
55cd8e5a 6690
5fdbf976
MT		 6691 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6692 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6693 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6694 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6695 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6696
229456fc 6697 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6698
a449c7aa
NA		 6699 op_64_bit = is_64_bit_mode(vcpu);
6700 if (!op_64_bit) {
8776e519
HB		 6701 nr &= 0xFFFFFFFF;
6702 a0 &= 0xFFFFFFFF;
6703 a1 &= 0xFFFFFFFF;
6704 a2 &= 0xFFFFFFFF;
6705 a3 &= 0xFFFFFFFF;
6706 }
6707
07708c4a
JK		 6708 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6709 ret = -KVM_EPERM;
6356ee0c 6710 goto out_error;
07708c4a
JK		 6711 }
6712
8776e519 6713 switch (nr) {
b93463aa
AK		 6714 case KVM_HC_VAPIC_POLL_IRQ:
6715 ret = 0;
6716 break;
6aef266c
SV		 6717 case KVM_HC_KICK_CPU:
6718 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6719 ret = 0;
6720 break;
8ef81a9a 6721#ifdef CONFIG_X86_64
55dd00a7
MT		 6722 case KVM_HC_CLOCK_PAIRING:
6723 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6724 break;
8ef81a9a 6725#endif
8776e519
HB		 6726 default:
6727 ret = -KVM_ENOSYS;
6728 break;
6729 }
6356ee0c 6730out_error:
a449c7aa
NA		 6731 if (!op_64_bit)
6732 ret = (u32)ret;
5fdbf976 6733 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6356ee0c
MR		 6734
6735out:
f11c3a8d 6736 ++vcpu->stat.hypercalls;
6356ee0c 6737 return kvm_skip_emulated_instruction(vcpu);
8776e519
HB		 6738}
6739EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6740
b6785def 6741static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6742{
d6aa1000 6743 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6744 char instruction[3];
5fdbf976 6745 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6746
8776e519 6747 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6748
ce2e852e
DV		 6749 return emulator_write_emulated(ctxt, rip, instruction, 3,
6750 &ctxt->exception);
8776e519
HB		 6751}
6752
851ba692 6753static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6754{
782d422b
MG		 6755 return vcpu->run->request_interrupt_window &&
6756 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6757}
6758
851ba692 6759static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6760{
851ba692
AK		 6761 struct kvm_run *kvm_run = vcpu->run;
6762
91586a3b 6763 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6764 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6765 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6766 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6767 kvm_run->ready_for_interrupt_injection =
6768 pic_in_kernel(vcpu->kvm) ||
782d422b 6769 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6770}
6771
95ba8273
GN		 6772static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6773{
6774 int max_irr, tpr;
6775
6776 if (!kvm_x86_ops->update_cr8_intercept)
6777 return;
6778
bce87cce 6779 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6780 return;
6781
d62caabb
AS		 6782 if (vcpu->arch.apicv_active)
6783 return;
6784
8db3baa2
GN		 6785 if (!vcpu->arch.apic->vapic_addr)
6786 max_irr = kvm_lapic_find_highest_irr(vcpu);
6787 else
6788 max_irr = -1;
95ba8273
GN		 6789
6790 if (max_irr != -1)
6791 max_irr >>= 4;
6792
6793 tpr = kvm_lapic_get_cr8(vcpu);
6794
6795 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6796}
6797
b6b8a145 6798static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6799{
b6b8a145
JK		 6800 int r;
6801
95ba8273 6802 /* try to reinject previous events if any */
664f8e26 6803
1a680e35
LA		 6804 if (vcpu->arch.exception.injected)
6805 kvm_x86_ops->queue_exception(vcpu);
664f8e26 6806 /*
a042c26f
LA		 6807 * Do not inject an NMI or interrupt if there is a pending
6808 * exception. Exceptions and interrupts are recognized at
6809 * instruction boundaries, i.e. the start of an instruction.
6810 * Trap-like exceptions, e.g. #DB, have higher priority than
6811 * NMIs and interrupts, i.e. traps are recognized before an
6812 * NMI/interrupt that's pending on the same instruction.
6813 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
6814 * priority, but are only generated (pended) during instruction
6815 * execution, i.e. a pending fault-like exception means the
6816 * fault occurred on the *previous* instruction and must be
6817 * serviced prior to recognizing any new events in order to
6818 * fully complete the previous instruction.
664f8e26 6819 */
1a680e35
LA		 6820 else if (!vcpu->arch.exception.pending) {
6821 if (vcpu->arch.nmi_injected)
664f8e26 6822 kvm_x86_ops->set_nmi(vcpu);
1a680e35 6823 else if (vcpu->arch.interrupt.injected)
664f8e26 6824 kvm_x86_ops->set_irq(vcpu);
664f8e26
WL		 6825 }
6826
1a680e35
LA		 6827 /*
6828 * Call check_nested_events() even if we reinjected a previous event
6829 * in order for caller to determine if it should require immediate-exit
6830 * from L2 to L1 due to pending L1 events which require exit
6831 * from L2 to L1.
6832 */
664f8e26
WL		 6833 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6834 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6835 if (r != 0)
6836 return r;
6837 }
6838
6839 /* try to inject new event if pending */
b59bb7bd 6840 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6841 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6842 vcpu->arch.exception.has_error_code,
6843 vcpu->arch.exception.error_code);
d6e8c854 6844
1a680e35 6845 WARN_ON_ONCE(vcpu->arch.exception.injected);
664f8e26
WL		 6846 vcpu->arch.exception.pending = false;
6847 vcpu->arch.exception.injected = true;
6848
d6e8c854
NA		 6849 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6850 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6851 X86_EFLAGS_RF);
6852
6bdf0662
NA		 6853 if (vcpu->arch.exception.nr == DB_VECTOR &&
6854 (vcpu->arch.dr7 & DR7_GD)) {
6855 vcpu->arch.dr7 &= ~DR7_GD;
6856 kvm_update_dr7(vcpu);
6857 }
6858
cfcd20e5 6859 kvm_x86_ops->queue_exception(vcpu);
1a680e35
LA		 6860 }
6861
6862 /* Don't consider new event if we re-injected an event */
6863 if (kvm_event_needs_reinjection(vcpu))
6864 return 0;
6865
6866 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
6867 kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 6868 vcpu->arch.smi_pending = false;
52797bf9 6869 ++vcpu->arch.smi_count;
ee2cd4b7 6870 enter_smm(vcpu);
c43203ca 6871 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6872 --vcpu->arch.nmi_pending;
6873 vcpu->arch.nmi_injected = true;
6874 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6875 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6876 /*
6877 * Because interrupts can be injected asynchronously, we are
6878 * calling check_nested_events again here to avoid a race condition.
6879 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6880 * proposal and current concerns. Perhaps we should be setting
6881 * KVM_REQ_EVENT only on certain events and not unconditionally?
6882 */
6883 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6884 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6885 if (r != 0)
6886 return r;
6887 }
95ba8273 6888 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6889 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6890 false);
6891 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6892 }
6893 }
ee2cd4b7 6894
b6b8a145 6895 return 0;
95ba8273
GN		 6896}
6897
7460fb4a
AK		 6898static void process_nmi(struct kvm_vcpu *vcpu)
6899{
6900 unsigned limit = 2;
6901
6902 /*
6903 * x86 is limited to one NMI running, and one NMI pending after it.
6904 * If an NMI is already in progress, limit further NMIs to just one.
6905 * Otherwise, allow two (and we'll inject the first one immediately).
6906 */
6907 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6908 limit = 1;
6909
6910 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6911 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6912 kvm_make_request(KVM_REQ_EVENT, vcpu);
6913}
6914
ee2cd4b7 6915static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6916{
6917 u32 flags = 0;
6918 flags |= seg->g << 23;
6919 flags |= seg->db << 22;
6920 flags |= seg->l << 21;
6921 flags |= seg->avl << 20;
6922 flags |= seg->present << 15;
6923 flags |= seg->dpl << 13;
6924 flags |= seg->s << 12;
6925 flags |= seg->type << 8;
6926 return flags;
6927}
6928
ee2cd4b7 6929static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6930{
6931 struct kvm_segment seg;
6932 int offset;
6933
6934 kvm_get_segment(vcpu, &seg, n);
6935 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6936
6937 if (n < 3)
6938 offset = 0x7f84 + n * 12;
6939 else
6940 offset = 0x7f2c + (n - 3) * 12;
6941
6942 put_smstate(u32, buf, offset + 8, seg.base);
6943 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6944 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6945}
6946
efbb288a 6947#ifdef CONFIG_X86_64
ee2cd4b7 6948static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6949{
6950 struct kvm_segment seg;
6951 int offset;
6952 u16 flags;
6953
6954 kvm_get_segment(vcpu, &seg, n);
6955 offset = 0x7e00 + n * 16;
6956
ee2cd4b7 6957 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6958 put_smstate(u16, buf, offset, seg.selector);
6959 put_smstate(u16, buf, offset + 2, flags);
6960 put_smstate(u32, buf, offset + 4, seg.limit);
6961 put_smstate(u64, buf, offset + 8, seg.base);
6962}
efbb288a 6963#endif
660a5d51 6964
ee2cd4b7 6965static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6966{
6967 struct desc_ptr dt;
6968 struct kvm_segment seg;
6969 unsigned long val;
6970 int i;
6971
6972 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6973 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6974 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6975 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6976
6977 for (i = 0; i < 8; i++)
6978 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6979
6980 kvm_get_dr(vcpu, 6, &val);
6981 put_smstate(u32, buf, 0x7fcc, (u32)val);
6982 kvm_get_dr(vcpu, 7, &val);
6983 put_smstate(u32, buf, 0x7fc8, (u32)val);
6984
6985 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6986 put_smstate(u32, buf, 0x7fc4, seg.selector);
6987 put_smstate(u32, buf, 0x7f64, seg.base);
6988 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6989 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6990
6991 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6992 put_smstate(u32, buf, 0x7fc0, seg.selector);
6993 put_smstate(u32, buf, 0x7f80, seg.base);
6994 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6995 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6996
6997 kvm_x86_ops->get_gdt(vcpu, &dt);
6998 put_smstate(u32, buf, 0x7f74, dt.address);
6999 put_smstate(u32, buf, 0x7f70, dt.size);
7000
7001 kvm_x86_ops->get_idt(vcpu, &dt);
7002 put_smstate(u32, buf, 0x7f58, dt.address);
7003 put_smstate(u32, buf, 0x7f54, dt.size);
7004
7005 for (i = 0; i < 6; i++)
ee2cd4b7 7006 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 7007
7008 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7009
7010 /* revision id */
7011 put_smstate(u32, buf, 0x7efc, 0x00020000);
7012 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7013}
7014
ee2cd4b7 7015static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7016{
7017#ifdef CONFIG_X86_64
7018 struct desc_ptr dt;
7019 struct kvm_segment seg;
7020 unsigned long val;
7021 int i;
7022
7023 for (i = 0; i < 16; i++)
7024 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7025
7026 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7027 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7028
7029 kvm_get_dr(vcpu, 6, &val);
7030 put_smstate(u64, buf, 0x7f68, val);
7031 kvm_get_dr(vcpu, 7, &val);
7032 put_smstate(u64, buf, 0x7f60, val);
7033
7034 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7035 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7036 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7037
7038 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7039
7040 /* revision id */
7041 put_smstate(u32, buf, 0x7efc, 0x00020064);
7042
7043 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7044
7045 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7046 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 7047 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7048 put_smstate(u32, buf, 0x7e94, seg.limit);
7049 put_smstate(u64, buf, 0x7e98, seg.base);
7050
7051 kvm_x86_ops->get_idt(vcpu, &dt);
7052 put_smstate(u32, buf, 0x7e84, dt.size);
7053 put_smstate(u64, buf, 0x7e88, dt.address);
7054
7055 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7056 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 7057 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7058 put_smstate(u32, buf, 0x7e74, seg.limit);
7059 put_smstate(u64, buf, 0x7e78, seg.base);
7060
7061 kvm_x86_ops->get_gdt(vcpu, &dt);
7062 put_smstate(u32, buf, 0x7e64, dt.size);
7063 put_smstate(u64, buf, 0x7e68, dt.address);
7064
7065 for (i = 0; i < 6; i++)
ee2cd4b7 7066 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 7067#else
7068 WARN_ON_ONCE(1);
7069#endif
7070}
7071
ee2cd4b7 7072static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 7073{
660a5d51 7074 struct kvm_segment cs, ds;
18c3626e 7075 struct desc_ptr dt;
660a5d51
PB		 7076 char buf[512];
7077 u32 cr0;
7078
660a5d51 7079 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7080 memset(buf, 0, 512);
d6321d49 7081 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7082 enter_smm_save_state_64(vcpu, buf);
660a5d51 7083 else
ee2cd4b7 7084 enter_smm_save_state_32(vcpu, buf);
660a5d51 7085
0234bf88
LP		 7086 /*
7087 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7088 * vCPU state (e.g. leave guest mode) after we've saved the state into
7089 * the SMM state-save area.
7090 */
7091 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7092
7093 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7094 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7095
7096 if (kvm_x86_ops->get_nmi_mask(vcpu))
7097 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7098 else
7099 kvm_x86_ops->set_nmi_mask(vcpu, true);
7100
7101 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7102 kvm_rip_write(vcpu, 0x8000);
7103
7104 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7105 kvm_x86_ops->set_cr0(vcpu, cr0);
7106 vcpu->arch.cr0 = cr0;
7107
7108 kvm_x86_ops->set_cr4(vcpu, 0);
7109
18c3626e
PB		 7110 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7111 dt.address = dt.size = 0;
7112 kvm_x86_ops->set_idt(vcpu, &dt);
7113
660a5d51
PB		 7114 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7115
7116 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7117 cs.base = vcpu->arch.smbase;
7118
7119 ds.selector = 0;
7120 ds.base = 0;
7121
7122 cs.limit = ds.limit = 0xffffffff;
7123 cs.type = ds.type = 0x3;
7124 cs.dpl = ds.dpl = 0;
7125 cs.db = ds.db = 0;
7126 cs.s = ds.s = 1;
7127 cs.l = ds.l = 0;
7128 cs.g = ds.g = 1;
7129 cs.avl = ds.avl = 0;
7130 cs.present = ds.present = 1;
7131 cs.unusable = ds.unusable = 0;
7132 cs.padding = ds.padding = 0;
7133
7134 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7135 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7136 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7137 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7138 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7139 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7140
d6321d49 7141 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 7142 kvm_x86_ops->set_efer(vcpu, 0);
7143
7144 kvm_update_cpuid(vcpu);
7145 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7146}
7147
ee2cd4b7 7148static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7149{
7150 vcpu->arch.smi_pending = true;
7151 kvm_make_request(KVM_REQ_EVENT, vcpu);
7152}
7153
2860c4b1
PB		 7154void kvm_make_scan_ioapic_request(struct kvm *kvm)
7155{
7156 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7157}
7158
3d81bc7e 7159static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7160{
3d81bc7e
YZ		 7161 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7162 return;
c7c9c56c 7163
6308630b 7164 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7165
b053b2ae 7166 if (irqchip_split(vcpu->kvm))
6308630b 7167 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7168 else {
fa59cc00 7169 if (vcpu->arch.apicv_active)
d62caabb 7170 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 7171 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7172 }
e40ff1d6
LA		 7173
7174 if (is_guest_mode(vcpu))
7175 vcpu->arch.load_eoi_exitmap_pending = true;
7176 else
7177 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7178}
7179
7180static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7181{
7182 u64 eoi_exit_bitmap[4];
7183
7184 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7185 return;
7186
5c919412
AS		 7187 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7188 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7189 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7190}
7191
b1394e74
RK		 7192void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7193 unsigned long start, unsigned long end)
7194{
7195 unsigned long apic_address;
7196
7197 /*
7198 * The physical address of apic access page is stored in the VMCS.
7199 * Update it when it becomes invalid.
7200 */
7201 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7202 if (start <= apic_address && apic_address < end)
7203 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
7204}
7205
4256f43f
TC		 7206void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7207{
c24ae0dc
TC		 7208 struct page *page = NULL;
7209
35754c98 7210 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7211 return;
7212
4256f43f
TC		 7213 if (!kvm_x86_ops->set_apic_access_page_addr)
7214 return;
7215
c24ae0dc 7216 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7217 if (is_error_page(page))
7218 return;
c24ae0dc
TC		 7219 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7220
7221 /*
7222 * Do not pin apic access page in memory, the MMU notifier
7223 * will call us again if it is migrated or swapped out.
7224 */
7225 put_page(page);
4256f43f
TC		 7226}
7227EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7228
9357d939 7229/*
362c698f 7230 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7231 * exiting to the userspace. Otherwise, the value will be returned to the
7232 * userspace.
7233 */
851ba692 7234static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7235{
7236 int r;
62a193ed
MG		 7237 bool req_int_win =
7238 dm_request_for_irq_injection(vcpu) &&
7239 kvm_cpu_accept_dm_intr(vcpu);
7240
730dca42 7241 bool req_immediate_exit = false;
b6c7a5dc 7242
2fa6e1e1 7243 if (kvm_request_pending(vcpu)) {
a8eeb04a 7244 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7245 kvm_mmu_unload(vcpu);
a8eeb04a 7246 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7247 __kvm_migrate_timers(vcpu);
d828199e
MT		 7248 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7249 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7250 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7251 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7252 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7253 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7254 if (unlikely(r))
7255 goto out;
7256 }
a8eeb04a 7257 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7258 kvm_mmu_sync_roots(vcpu);
a8eeb04a 7259 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7260 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7261 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7262 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7263 r = 0;
7264 goto out;
7265 }
a8eeb04a 7266 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7267 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7268 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7269 r = 0;
7270 goto out;
7271 }
af585b92
GN		 7272 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7273 /* Page is swapped out. Do synthetic halt */
7274 vcpu->arch.apf.halted = true;
7275 r = 1;
7276 goto out;
7277 }
c9aaa895
GC		 7278 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7279 record_steal_time(vcpu);
64d60670
PB		 7280 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7281 process_smi(vcpu);
7460fb4a
AK		 7282 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7283 process_nmi(vcpu);
f5132b01 7284 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7285 kvm_pmu_handle_event(vcpu);
f5132b01 7286 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7287 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7288 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7289 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7290 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7291 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7292 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7293 vcpu->run->eoi.vector =
7294 vcpu->arch.pending_ioapic_eoi;
7295 r = 0;
7296 goto out;
7297 }
7298 }
3d81bc7e
YZ		 7299 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7300 vcpu_scan_ioapic(vcpu);
e40ff1d6
LA		 7301 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7302 vcpu_load_eoi_exitmap(vcpu);
4256f43f
TC		 7303 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7304 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7305 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7306 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7307 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7308 r = 0;
7309 goto out;
7310 }
e516cebb
AS		 7311 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7312 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7313 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7314 r = 0;
7315 goto out;
7316 }
db397571
AS		 7317 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7318 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7319 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7320 r = 0;
7321 goto out;
7322 }
f3b138c5
AS		 7323
7324 /*
7325 * KVM_REQ_HV_STIMER has to be processed after
7326 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7327 * depend on the guest clock being up-to-date
7328 */
1f4b34f8
AS		 7329 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7330 kvm_hv_process_stimers(vcpu);
2f52d58c 7331 }
b93463aa 7332
b463a6f7 7333 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7334 ++vcpu->stat.req_event;
66450a21
JK		 7335 kvm_apic_accept_events(vcpu);
7336 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7337 r = 1;
7338 goto out;
7339 }
7340
b6b8a145
JK		 7341 if (inject_pending_event(vcpu, req_int_win) != 0)
7342 req_immediate_exit = true;
321c5658 7343 else {
cc3d967f 7344 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7345 *
cc3d967f
LP		 7346 * SMIs have three cases:
7347 * 1) They can be nested, and then there is nothing to
7348 * do here because RSM will cause a vmexit anyway.
7349 * 2) There is an ISA-specific reason why SMI cannot be
7350 * injected, and the moment when this changes can be
7351 * intercepted.
7352 * 3) Or the SMI can be pending because
7353 * inject_pending_event has completed the injection
7354 * of an IRQ or NMI from the previous vmexit, and
7355 * then we request an immediate exit to inject the
7356 * SMI.
c43203ca
PB		 7357 */
7358 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7359 if (!kvm_x86_ops->enable_smi_window(vcpu))
7360 req_immediate_exit = true;
321c5658
YS		 7361 if (vcpu->arch.nmi_pending)
7362 kvm_x86_ops->enable_nmi_window(vcpu);
7363 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7364 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7365 WARN_ON(vcpu->arch.exception.pending);
321c5658 7366 }
b463a6f7
AK		 7367
7368 if (kvm_lapic_enabled(vcpu)) {
7369 update_cr8_intercept(vcpu);
7370 kvm_lapic_sync_to_vapic(vcpu);
7371 }
7372 }
7373
d8368af8
AK		 7374 r = kvm_mmu_reload(vcpu);
7375 if (unlikely(r)) {
d905c069 7376 goto cancel_injection;
d8368af8
AK		 7377 }
7378
b6c7a5dc
HB		 7379 preempt_disable();
7380
7381 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7382
7383 /*
7384 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7385 * IPI are then delayed after guest entry, which ensures that they
7386 * result in virtual interrupt delivery.
7387 */
7388 local_irq_disable();
6b7e2d09
XG		 7389 vcpu->mode = IN_GUEST_MODE;
7390
01b71917
MT		 7391 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7392
0f127d12 7393 /*
b95234c8 7394 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7395 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 7396 *
7397 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7398 * pairs with the memory barrier implicit in pi_test_and_set_on
7399 * (see vmx_deliver_posted_interrupt).
7400 *
7401 * 3) This also orders the write to mode from any reads to the page
7402 * tables done while the VCPU is running. Please see the comment
7403 * in kvm_flush_remote_tlbs.
6b7e2d09 7404 */
01b71917 7405 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7406
b95234c8
PB		 7407 /*
7408 * This handles the case where a posted interrupt was
7409 * notified with kvm_vcpu_kick.
7410 */
fa59cc00
LA		 7411 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7412 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7413
2fa6e1e1 7414 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7415 || need_resched() || signal_pending(current)) {
6b7e2d09 7416 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7417 smp_wmb();
6c142801
AK		 7418 local_irq_enable();
7419 preempt_enable();
01b71917 7420 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7421 r = 1;
d905c069 7422 goto cancel_injection;
6c142801
AK		 7423 }
7424
fc5b7f3b
DM		 7425 kvm_load_guest_xcr0(vcpu);
7426
c43203ca
PB		 7427 if (req_immediate_exit) {
7428 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 7429 smp_send_reschedule(vcpu->cpu);
c43203ca 7430 }
d6185f20 7431
8b89fe1f 7432 trace_kvm_entry(vcpu->vcpu_id);
9c48d517
WL		 7433 if (lapic_timer_advance_ns)
7434 wait_lapic_expire(vcpu);
6edaa530 7435 guest_enter_irqoff();
b6c7a5dc 7436
42dbaa5a 7437 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7438 set_debugreg(0, 7);
7439 set_debugreg(vcpu->arch.eff_db[0], 0);
7440 set_debugreg(vcpu->arch.eff_db[1], 1);
7441 set_debugreg(vcpu->arch.eff_db[2], 2);
7442 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7443 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7444 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7445 }
b6c7a5dc 7446
851ba692 7447 kvm_x86_ops->run(vcpu);
b6c7a5dc 7448
c77fb5fe
PB		 7449 /*
7450 * Do this here before restoring debug registers on the host. And
7451 * since we do this before handling the vmexit, a DR access vmexit
7452 * can (a) read the correct value of the debug registers, (b) set
7453 * KVM_DEBUGREG_WONT_EXIT again.
7454 */
7455 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7456 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7457 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7458 kvm_update_dr0123(vcpu);
7459 kvm_update_dr6(vcpu);
7460 kvm_update_dr7(vcpu);
7461 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7462 }
7463
24f1e32c
FW		 7464 /*
7465 * If the guest has used debug registers, at least dr7
7466 * will be disabled while returning to the host.
7467 * If we don't have active breakpoints in the host, we don't
7468 * care about the messed up debug address registers. But if
7469 * we have some of them active, restore the old state.
7470 */
59d8eb53 7471 if (hw_breakpoint_active())
24f1e32c 7472 hw_breakpoint_restore();
42dbaa5a 7473
4ba76538 7474 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7475
6b7e2d09 7476 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7477 smp_wmb();
a547c6db 7478
fc5b7f3b
DM		 7479 kvm_put_guest_xcr0(vcpu);
7480
dd60d217 7481 kvm_before_interrupt(vcpu);
a547c6db 7482 kvm_x86_ops->handle_external_intr(vcpu);
dd60d217 7483 kvm_after_interrupt(vcpu);
b6c7a5dc
HB		 7484
7485 ++vcpu->stat.exits;
7486
f2485b3e 7487 guest_exit_irqoff();
b6c7a5dc 7488
f2485b3e 7489 local_irq_enable();
b6c7a5dc
HB		 7490 preempt_enable();
7491
f656ce01 7492 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7493
b6c7a5dc
HB		 7494 /*
7495 * Profile KVM exit RIPs:
7496 */
7497 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7498 unsigned long rip = kvm_rip_read(vcpu);
7499 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7500 }
7501
cc578287
ZA		 7502 if (unlikely(vcpu->arch.tsc_always_catchup))
7503 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7504
5cfb1d5a
MT		 7505 if (vcpu->arch.apic_attention)
7506 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7507
618232e2 7508 vcpu->arch.gpa_available = false;
851ba692 7509 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7510 return r;
7511
7512cancel_injection:
7513 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7514 if (unlikely(vcpu->arch.apic_attention))
7515 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7516out:
7517 return r;
7518}
b6c7a5dc 7519
362c698f
PB		 7520static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7521{
bf9f6ac8
FW		 7522 if (!kvm_arch_vcpu_runnable(vcpu) &&
7523 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7524 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7525 kvm_vcpu_block(vcpu);
7526 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7527
7528 if (kvm_x86_ops->post_block)
7529 kvm_x86_ops->post_block(vcpu);
7530
9c8fd1ba
PB		 7531 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7532 return 1;
7533 }
362c698f
PB		 7534
7535 kvm_apic_accept_events(vcpu);
7536 switch(vcpu->arch.mp_state) {
7537 case KVM_MP_STATE_HALTED:
7538 vcpu->arch.pv.pv_unhalted = false;
7539 vcpu->arch.mp_state =
7540 KVM_MP_STATE_RUNNABLE;
7541 case KVM_MP_STATE_RUNNABLE:
7542 vcpu->arch.apf.halted = false;
7543 break;
7544 case KVM_MP_STATE_INIT_RECEIVED:
7545 break;
7546 default:
7547 return -EINTR;
7548 break;
7549 }
7550 return 1;
7551}
09cec754 7552
5d9bc648
PB		 7553static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7554{
0ad3bed6
PB		 7555 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7556 kvm_x86_ops->check_nested_events(vcpu, false);
7557
5d9bc648
PB		 7558 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7559 !vcpu->arch.apf.halted);
7560}
7561
362c698f 7562static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7563{
7564 int r;
f656ce01 7565 struct kvm *kvm = vcpu->kvm;
d7690175 7566
f656ce01 7567 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7568
362c698f 7569 for (;;) {
58f800d5 7570 if (kvm_vcpu_running(vcpu)) {
851ba692 7571 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7572 } else {
362c698f 7573 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7574 }
7575
09cec754
GN		 7576 if (r <= 0)
7577 break;
7578
72875d8a 7579 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7580 if (kvm_cpu_has_pending_timer(vcpu))
7581 kvm_inject_pending_timer_irqs(vcpu);
7582
782d422b
MG		 7583 if (dm_request_for_irq_injection(vcpu) &&
7584 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7585 r = 0;
7586 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7587 ++vcpu->stat.request_irq_exits;
362c698f 7588 break;
09cec754 7589 }
af585b92
GN		 7590
7591 kvm_check_async_pf_completion(vcpu);
7592
09cec754
GN		 7593 if (signal_pending(current)) {
7594 r = -EINTR;
851ba692 7595 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7596 ++vcpu->stat.signal_exits;
362c698f 7597 break;
09cec754
GN		 7598 }
7599 if (need_resched()) {
f656ce01 7600 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7601 cond_resched();
f656ce01 7602 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7603 }
b6c7a5dc
HB		 7604 }
7605
f656ce01 7606 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7607
7608 return r;
7609}
7610
716d51ab
GN		 7611static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7612{
7613 int r;
7614 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7615 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7616 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7617 if (r != EMULATE_DONE)
7618 return 0;
7619 return 1;
7620}
7621
7622static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7623{
7624 BUG_ON(!vcpu->arch.pio.count);
7625
7626 return complete_emulated_io(vcpu);
7627}
7628
f78146b0
AK		 7629/*
7630 * Implements the following, as a state machine:
7631 *
7632 * read:
7633 * for each fragment
87da7e66
XG		 7634 * for each mmio piece in the fragment
7635 * write gpa, len
7636 * exit
7637 * copy data
f78146b0
AK		 7638 * execute insn
7639 *
7640 * write:
7641 * for each fragment
87da7e66
XG		 7642 * for each mmio piece in the fragment
7643 * write gpa, len
7644 * copy data
7645 * exit
f78146b0 7646 */
716d51ab 7647static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7648{
7649 struct kvm_run *run = vcpu->run;
f78146b0 7650 struct kvm_mmio_fragment *frag;
87da7e66 7651 unsigned len;
5287f194 7652
716d51ab 7653 BUG_ON(!vcpu->mmio_needed);
5287f194 7654
716d51ab 7655 /* Complete previous fragment */
87da7e66
XG		 7656 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7657 len = min(8u, frag->len);
716d51ab 7658 if (!vcpu->mmio_is_write)
87da7e66
XG		 7659 memcpy(frag->data, run->mmio.data, len);
7660
7661 if (frag->len <= 8) {
7662 /* Switch to the next fragment. */
7663 frag++;
7664 vcpu->mmio_cur_fragment++;
7665 } else {
7666 /* Go forward to the next mmio piece. */
7667 frag->data += len;
7668 frag->gpa += len;
7669 frag->len -= len;
7670 }
7671
a08d3b3b 7672 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7673 vcpu->mmio_needed = 0;
0912c977
PB		 7674
7675 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7676 if (vcpu->mmio_is_write)
716d51ab
GN		 7677 return 1;
7678 vcpu->mmio_read_completed = 1;
7679 return complete_emulated_io(vcpu);
7680 }
87da7e66 7681
716d51ab
GN		 7682 run->exit_reason = KVM_EXIT_MMIO;
7683 run->mmio.phys_addr = frag->gpa;
7684 if (vcpu->mmio_is_write)
87da7e66
XG		 7685 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7686 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7687 run->mmio.is_write = vcpu->mmio_is_write;
7688 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7689 return 0;
5287f194
AK		 7690}
7691
b6c7a5dc
HB		 7692int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7693{
7694 int r;
b6c7a5dc 7695
accb757d 7696 vcpu_load(vcpu);
20b7035c 7697 kvm_sigset_activate(vcpu);
5663d8f9
PX		 7698 kvm_load_guest_fpu(vcpu);
7699
a4535290 7700 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7701 if (kvm_run->immediate_exit) {
7702 r = -EINTR;
7703 goto out;
7704 }
b6c7a5dc 7705 kvm_vcpu_block(vcpu);
66450a21 7706 kvm_apic_accept_events(vcpu);
72875d8a 7707 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7708 r = -EAGAIN;
a0595000
JS		 7709 if (signal_pending(current)) {
7710 r = -EINTR;
7711 vcpu->run->exit_reason = KVM_EXIT_INTR;
7712 ++vcpu->stat.signal_exits;
7713 }
ac9f6dc0 7714 goto out;
b6c7a5dc
HB		 7715 }
7716
01643c51
KH		 7717 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
7718 r = -EINVAL;
7719 goto out;
7720 }
7721
7722 if (vcpu->run->kvm_dirty_regs) {
7723 r = sync_regs(vcpu);
7724 if (r != 0)
7725 goto out;
7726 }
7727
b6c7a5dc 7728 /* re-sync apic's tpr */
35754c98 7729 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7730 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7731 r = -EINVAL;
7732 goto out;
7733 }
7734 }
b6c7a5dc 7735
716d51ab
GN		 7736 if (unlikely(vcpu->arch.complete_userspace_io)) {
7737 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7738 vcpu->arch.complete_userspace_io = NULL;
7739 r = cui(vcpu);
7740 if (r <= 0)
5663d8f9 7741 goto out;
716d51ab
GN		 7742 } else
7743 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7744
460df4c1
PB		 7745 if (kvm_run->immediate_exit)
7746 r = -EINTR;
7747 else
7748 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7749
7750out:
5663d8f9 7751 kvm_put_guest_fpu(vcpu);
01643c51
KH		 7752 if (vcpu->run->kvm_valid_regs)
7753 store_regs(vcpu);
f1d86e46 7754 post_kvm_run_save(vcpu);
20b7035c 7755 kvm_sigset_deactivate(vcpu);
b6c7a5dc 7756
accb757d 7757 vcpu_put(vcpu);
b6c7a5dc
HB		 7758 return r;
7759}
7760
01643c51 7761static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7762{
7ae441ea
GN		 7763 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7764 /*
7765 * We are here if userspace calls get_regs() in the middle of
7766 * instruction emulation. Registers state needs to be copied
4a969980 7767 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7768 * that usually, but some bad designed PV devices (vmware
7769 * backdoor interface) need this to work
7770 */
dd856efa 7771 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7772 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7773 }
5fdbf976
MT		 7774 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7775 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7776 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7777 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7778 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7779 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7780 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7781 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7782#ifdef CONFIG_X86_64
5fdbf976
MT		 7783 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7784 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7785 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7786 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7787 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7788 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7789 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7790 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7791#endif
7792
5fdbf976 7793 regs->rip = kvm_rip_read(vcpu);
91586a3b 7794 regs->rflags = kvm_get_rflags(vcpu);
01643c51 7795}
b6c7a5dc 7796
01643c51
KH		 7797int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7798{
7799 vcpu_load(vcpu);
7800 __get_regs(vcpu, regs);
1fc9b76b 7801 vcpu_put(vcpu);
b6c7a5dc
HB		 7802 return 0;
7803}
7804
01643c51 7805static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7806{
7ae441ea
GN		 7807 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7808 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7809
5fdbf976
MT		 7810 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7811 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7812 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7813 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7814 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7815 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7816 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7817 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7818#ifdef CONFIG_X86_64
5fdbf976
MT		 7819 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7820 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7821 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7822 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7823 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7824 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7825 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7826 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7827#endif
7828
5fdbf976 7829 kvm_rip_write(vcpu, regs->rip);
d73235d1 7830 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 7831
b4f14abd
JK		 7832 vcpu->arch.exception.pending = false;
7833
3842d135 7834 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 7835}
3842d135 7836
01643c51
KH		 7837int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7838{
7839 vcpu_load(vcpu);
7840 __set_regs(vcpu, regs);
875656fe 7841 vcpu_put(vcpu);
b6c7a5dc
HB		 7842 return 0;
7843}
7844
b6c7a5dc
HB		 7845void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7846{
7847 struct kvm_segment cs;
7848
3e6e0aab 7849 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7850 *db = cs.db;
7851 *l = cs.l;
7852}
7853EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7854
01643c51 7855static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 7856{
89a27f4d 7857 struct desc_ptr dt;
b6c7a5dc 7858
3e6e0aab
GT		 7859 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7860 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7861 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7862 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7863 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7864 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7865
3e6e0aab
GT		 7866 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7867 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7868
7869 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7870 sregs->idt.limit = dt.size;
7871 sregs->idt.base = dt.address;
b6c7a5dc 7872 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7873 sregs->gdt.limit = dt.size;
7874 sregs->gdt.base = dt.address;
b6c7a5dc 7875
4d4ec087 7876 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7877 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7878 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7879 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7880 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7881 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7882 sregs->apic_base = kvm_get_apic_base(vcpu);
7883
923c61bb 7884 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7885
04140b41 7886 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7887 set_bit(vcpu->arch.interrupt.nr,
7888 (unsigned long *)sregs->interrupt_bitmap);
01643c51 7889}
16d7a191 7890
01643c51
KH		 7891int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7892 struct kvm_sregs *sregs)
7893{
7894 vcpu_load(vcpu);
7895 __get_sregs(vcpu, sregs);
bcdec41c 7896 vcpu_put(vcpu);
b6c7a5dc
HB		 7897 return 0;
7898}
7899
62d9f0db
MT		 7900int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7901 struct kvm_mp_state *mp_state)
7902{
fd232561
CD		 7903 vcpu_load(vcpu);
7904
66450a21 7905 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7906 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7907 vcpu->arch.pv.pv_unhalted)
7908 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7909 else
7910 mp_state->mp_state = vcpu->arch.mp_state;
7911
fd232561 7912 vcpu_put(vcpu);
62d9f0db
MT		 7913 return 0;
7914}
7915
7916int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7917 struct kvm_mp_state *mp_state)
7918{
e83dff5e
CD		 7919 int ret = -EINVAL;
7920
7921 vcpu_load(vcpu);
7922
bce87cce 7923 if (!lapic_in_kernel(vcpu) &&
66450a21 7924 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 7925 goto out;
66450a21 7926
28bf2888
DH		 7927 /* INITs are latched while in SMM */
7928 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7929 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7930 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 7931 goto out;
28bf2888 7932
66450a21
JK		 7933 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7934 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7935 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7936 } else
7937 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7938 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 7939
7940 ret = 0;
7941out:
7942 vcpu_put(vcpu);
7943 return ret;
62d9f0db
MT		 7944}
7945
7f3d35fd
KW		 7946int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7947 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7948{
9d74191a 7949 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7950 int ret;
e01c2426 7951
8ec4722d 7952 init_emulate_ctxt(vcpu);
c697518a 7953
7f3d35fd 7954 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7955 has_error_code, error_code);
c697518a 7956
c697518a 7957 if (ret)
19d04437 7958 return EMULATE_FAIL;
37817f29 7959
9d74191a
TY		 7960 kvm_rip_write(vcpu, ctxt->eip);
7961 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7962 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7963 return EMULATE_DONE;
37817f29
IE		 7964}
7965EXPORT_SYMBOL_GPL(kvm_task_switch);
7966
3140c156 7967static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
f2981033 7968{
37b95951 7969 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 7970 /*
7971 * When EFER.LME and CR0.PG are set, the processor is in
7972 * 64-bit mode (though maybe in a 32-bit code segment).
7973 * CR4.PAE and EFER.LMA must be set.
7974 */
37b95951 7975 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 7976 || !(sregs->efer & EFER_LMA))
7977 return -EINVAL;
7978 } else {
7979 /*
7980 * Not in 64-bit mode: EFER.LMA is clear and the code
7981 * segment cannot be 64-bit.
7982 */
7983 if (sregs->efer & EFER_LMA || sregs->cs.l)
7984 return -EINVAL;
7985 }
7986
7987 return 0;
7988}
7989
01643c51 7990static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 7991{
58cb628d 7992 struct msr_data apic_base_msr;
b6c7a5dc 7993 int mmu_reset_needed = 0;
63f42e02 7994 int pending_vec, max_bits, idx;
89a27f4d 7995 struct desc_ptr dt;
b4ef9d4e
CD		 7996 int ret = -EINVAL;
7997
d6321d49
RK		 7998 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7999 (sregs->cr4 & X86_CR4_OSXSAVE))
b4ef9d4e 8000 goto out;
6d1068b3 8001
f2981033 8002 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 8003 goto out;
f2981033 8004
d3802286
JM		 8005 apic_base_msr.data = sregs->apic_base;
8006 apic_base_msr.host_initiated = true;
8007 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 8008 goto out;
6d1068b3 8009
89a27f4d
GN		 8010 dt.size = sregs->idt.limit;
8011 dt.address = sregs->idt.base;
b6c7a5dc 8012 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 8013 dt.size = sregs->gdt.limit;
8014 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 8015 kvm_x86_ops->set_gdt(vcpu, &dt);
8016
ad312c7c 8017 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 8018 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 8019 vcpu->arch.cr3 = sregs->cr3;
aff48baa 8020 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 8021
2d3ad1f4 8022 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 8023
f6801dff 8024 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 8025 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 8026
4d4ec087 8027 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 8028 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 8029 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 8030
fc78f519 8031 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 8032 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 8033 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 8034 kvm_update_cpuid(vcpu);
63f42e02
XG		 8035
8036 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 8037 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 8038 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 8039 mmu_reset_needed = 1;
8040 }
63f42e02 8041 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 8042
8043 if (mmu_reset_needed)
8044 kvm_mmu_reset_context(vcpu);
8045
a50abc3b 8046 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 8047 pending_vec = find_first_bit(
8048 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8049 if (pending_vec < max_bits) {
66fd3f7f 8050 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 8051 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 8052 }
8053
3e6e0aab
GT		 8054 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8055 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8056 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8057 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8058 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8059 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8060
3e6e0aab
GT		 8061 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8062 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 8063
5f0269f5
ME		 8064 update_cr8_intercept(vcpu);
8065
9c3e4aab 8066 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 8067 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 8068 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 8069 !is_protmode(vcpu))
9c3e4aab
MT		 8070 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8071
3842d135
AK		 8072 kvm_make_request(KVM_REQ_EVENT, vcpu);
8073
b4ef9d4e
CD		 8074 ret = 0;
8075out:
01643c51
KH		 8076 return ret;
8077}
8078
8079int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8080 struct kvm_sregs *sregs)
8081{
8082 int ret;
8083
8084 vcpu_load(vcpu);
8085 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 8086 vcpu_put(vcpu);
8087 return ret;
b6c7a5dc
HB		 8088}
8089
d0bfb940
JK		 8090int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8091 struct kvm_guest_debug *dbg)
b6c7a5dc 8092{
355be0b9 8093 unsigned long rflags;
ae675ef0 8094 int i, r;
b6c7a5dc 8095
66b56562
CD		 8096 vcpu_load(vcpu);
8097
4f926bf2
JK		 8098 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8099 r = -EBUSY;
8100 if (vcpu->arch.exception.pending)
2122ff5e 8101 goto out;
4f926bf2
JK		 8102 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8103 kvm_queue_exception(vcpu, DB_VECTOR);
8104 else
8105 kvm_queue_exception(vcpu, BP_VECTOR);
8106 }
8107
91586a3b
JK		 8108 /*
8109 * Read rflags as long as potentially injected trace flags are still
8110 * filtered out.
8111 */
8112 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 8113
8114 vcpu->guest_debug = dbg->control;
8115 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8116 vcpu->guest_debug = 0;
8117
8118 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 8119 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8120 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 8121 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 8122 } else {
8123 for (i = 0; i < KVM_NR_DB_REGS; i++)
8124 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 8125 }
c8639010 8126 kvm_update_dr7(vcpu);
ae675ef0 8127
f92653ee
JK		 8128 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8129 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8130 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 8131
91586a3b
JK		 8132 /*
8133 * Trigger an rflags update that will inject or remove the trace
8134 * flags.
8135 */
8136 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 8137
a96036b8 8138 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 8139
4f926bf2 8140 r = 0;
d0bfb940 8141
2122ff5e 8142out:
66b56562 8143 vcpu_put(vcpu);
b6c7a5dc
HB		 8144 return r;
8145}
8146
8b006791
ZX		 8147/*
8148 * Translate a guest virtual address to a guest physical address.
8149 */
8150int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8151 struct kvm_translation *tr)
8152{
8153 unsigned long vaddr = tr->linear_address;
8154 gpa_t gpa;
f656ce01 8155 int idx;
8b006791 8156
1da5b61d
CD		 8157 vcpu_load(vcpu);
8158
f656ce01 8159 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8160 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8161 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8162 tr->physical_address = gpa;
8163 tr->valid = gpa != UNMAPPED_GVA;
8164 tr->writeable = 1;
8165 tr->usermode = 0;
8b006791 8166
1da5b61d 8167 vcpu_put(vcpu);
8b006791
ZX		 8168 return 0;
8169}
8170
d0752060
HB		 8171int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8172{
1393123e 8173 struct fxregs_state *fxsave;
d0752060 8174
1393123e 8175 vcpu_load(vcpu);
d0752060 8176
1393123e 8177 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060
HB		 8178 memcpy(fpu->fpr, fxsave->st_space, 128);
8179 fpu->fcw = fxsave->cwd;
8180 fpu->fsw = fxsave->swd;
8181 fpu->ftwx = fxsave->twd;
8182 fpu->last_opcode = fxsave->fop;
8183 fpu->last_ip = fxsave->rip;
8184 fpu->last_dp = fxsave->rdp;
8185 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
8186
1393123e 8187 vcpu_put(vcpu);
d0752060
HB		 8188 return 0;
8189}
8190
8191int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8192{
6a96bc7f
CD		 8193 struct fxregs_state *fxsave;
8194
8195 vcpu_load(vcpu);
8196
8197 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060 8198
d0752060
HB		 8199 memcpy(fxsave->st_space, fpu->fpr, 128);
8200 fxsave->cwd = fpu->fcw;
8201 fxsave->swd = fpu->fsw;
8202 fxsave->twd = fpu->ftwx;
8203 fxsave->fop = fpu->last_opcode;
8204 fxsave->rip = fpu->last_ip;
8205 fxsave->rdp = fpu->last_dp;
8206 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
8207
6a96bc7f 8208 vcpu_put(vcpu);
d0752060
HB		 8209 return 0;
8210}
8211
01643c51
KH		 8212static void store_regs(struct kvm_vcpu *vcpu)
8213{
8214 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8215
8216 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8217 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8218
8219 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8220 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8221
8222 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8223 kvm_vcpu_ioctl_x86_get_vcpu_events(
8224 vcpu, &vcpu->run->s.regs.events);
8225}
8226
8227static int sync_regs(struct kvm_vcpu *vcpu)
8228{
8229 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8230 return -EINVAL;
8231
8232 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8233 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8234 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8235 }
8236 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8237 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8238 return -EINVAL;
8239 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8240 }
8241 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8242 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8243 vcpu, &vcpu->run->s.regs.events))
8244 return -EINVAL;
8245 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8246 }
8247
8248 return 0;
8249}
8250
0ee6a517 8251static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8252{
bf935b0b 8253 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 8254 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 8255 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 8256 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 8257
2acf923e
DC		 8258 /*
8259 * Ensure guest xcr0 is valid for loading
8260 */
d91cab78 8261 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 8262
ad312c7c 8263 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 8264}
d0752060 8265
f775b13e 8266/* Swap (qemu) user FPU context for the guest FPU context. */
d0752060
HB		 8267void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8268{
f775b13e
RR		 8269 preempt_disable();
8270 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
38cfd5e3
PB		 8271 /* PKRU is separately restored in kvm_x86_ops->run. */
8272 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
8273 ~XFEATURE_MASK_PKRU);
f775b13e 8274 preempt_enable();
0c04851c 8275 trace_kvm_fpu(1);
d0752060 8276}
d0752060 8277
f775b13e 8278/* When vcpu_run ends, restore user space FPU context. */
d0752060
HB		 8279void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8280{
f775b13e 8281 preempt_disable();
4f836347 8282 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
f775b13e
RR		 8283 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
8284 preempt_enable();
f096ed85 8285 ++vcpu->stat.fpu_reload;
0c04851c 8286 trace_kvm_fpu(0);
d0752060 8287}
e9b11c17
ZX		 8288
8289void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8290{
bd768e14
IY		 8291 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8292
12f9a48f 8293 kvmclock_reset(vcpu);
7f1ea208 8294
e9b11c17 8295 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 8296 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 8297}
8298
8299struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8300 unsigned int id)
8301{
c447e76b
LL		 8302 struct kvm_vcpu *vcpu;
8303
b0c39dc6 8304 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 8305 printk_once(KERN_WARNING
8306 "kvm: SMP vm created on host with unstable TSC; "
8307 "guest TSC will not be reliable\n");
c447e76b
LL		 8308
8309 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8310
c447e76b 8311 return vcpu;
26e5215f 8312}
e9b11c17 8313
26e5215f
AK		 8314int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8315{
19efffa2 8316 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 8317 vcpu_load(vcpu);
d28bc9dd 8318 kvm_vcpu_reset(vcpu, false);
8a3c1a33 8319 kvm_mmu_setup(vcpu);
e9b11c17 8320 vcpu_put(vcpu);
ec7660cc 8321 return 0;
e9b11c17
ZX		 8322}
8323
31928aa5 8324void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 8325{
8fe8ab46 8326 struct msr_data msr;
332967a3 8327 struct kvm *kvm = vcpu->kvm;
42897d86 8328
d3457c87
RK		 8329 kvm_hv_vcpu_postcreate(vcpu);
8330
ec7660cc 8331 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 8332 return;
ec7660cc 8333 vcpu_load(vcpu);
8fe8ab46
WA		 8334 msr.data = 0x0;
8335 msr.index = MSR_IA32_TSC;
8336 msr.host_initiated = true;
8337 kvm_write_tsc(vcpu, &msr);
42897d86 8338 vcpu_put(vcpu);
ec7660cc 8339 mutex_unlock(&vcpu->mutex);
42897d86 8340
630994b3
MT		 8341 if (!kvmclock_periodic_sync)
8342 return;
8343
332967a3
AJ		 8344 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8345 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8346}
8347
d40ccc62 8348void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8349{
344d9588
GN		 8350 vcpu->arch.apf.msr_val = 0;
8351
ec7660cc 8352 vcpu_load(vcpu);
e9b11c17
ZX		 8353 kvm_mmu_unload(vcpu);
8354 vcpu_put(vcpu);
8355
8356 kvm_x86_ops->vcpu_free(vcpu);
8357}
8358
d28bc9dd 8359void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8360{
b7e31be3
RK		 8361 kvm_lapic_reset(vcpu, init_event);
8362
e69fab5d
PB		 8363 vcpu->arch.hflags = 0;
8364
c43203ca 8365 vcpu->arch.smi_pending = 0;
52797bf9 8366 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8367 atomic_set(&vcpu->arch.nmi_queued, 0);
8368 vcpu->arch.nmi_pending = 0;
448fa4a9 8369 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8370 kvm_clear_interrupt_queue(vcpu);
8371 kvm_clear_exception_queue(vcpu);
664f8e26 8372 vcpu->arch.exception.pending = false;
448fa4a9 8373
42dbaa5a 8374 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8375 kvm_update_dr0123(vcpu);
6f43ed01 8376 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8377 kvm_update_dr6(vcpu);
42dbaa5a 8378 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8379 kvm_update_dr7(vcpu);
42dbaa5a 8380
1119022c
NA		 8381 vcpu->arch.cr2 = 0;
8382
3842d135 8383 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8384 vcpu->arch.apf.msr_val = 0;
c9aaa895 8385 vcpu->arch.st.msr_val = 0;
3842d135 8386
12f9a48f
GC		 8387 kvmclock_reset(vcpu);
8388
af585b92
GN		 8389 kvm_clear_async_pf_completion_queue(vcpu);
8390 kvm_async_pf_hash_reset(vcpu);
8391 vcpu->arch.apf.halted = false;
3842d135 8392
a554d207
WL		 8393 if (kvm_mpx_supported()) {
8394 void *mpx_state_buffer;
8395
8396 /*
8397 * To avoid have the INIT path from kvm_apic_has_events() that be
8398 * called with loaded FPU and does not let userspace fix the state.
8399 */
f775b13e
RR		 8400 if (init_event)
8401 kvm_put_guest_fpu(vcpu);
a554d207
WL		 8402 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8403 XFEATURE_MASK_BNDREGS);
8404 if (mpx_state_buffer)
8405 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8406 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8407 XFEATURE_MASK_BNDCSR);
8408 if (mpx_state_buffer)
8409 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 8410 if (init_event)
8411 kvm_load_guest_fpu(vcpu);
a554d207
WL		 8412 }
8413
64d60670 8414 if (!init_event) {
d28bc9dd 8415 kvm_pmu_reset(vcpu);
64d60670 8416 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 8417
8418 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8419 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 8420
8421 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 8422 }
f5132b01 8423
66f7b72e
JS		 8424 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8425 vcpu->arch.regs_avail = ~0;
8426 vcpu->arch.regs_dirty = ~0;
8427
a554d207
WL		 8428 vcpu->arch.ia32_xss = 0;
8429
d28bc9dd 8430 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 8431}
8432
2b4a273b 8433void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 8434{
8435 struct kvm_segment cs;
8436
8437 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8438 cs.selector = vector << 8;
8439 cs.base = vector << 12;
8440 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8441 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 8442}
8443
13a34e06 8444int kvm_arch_hardware_enable(void)
e9b11c17 8445{
ca84d1a2
ZA		 8446 struct kvm *kvm;
8447 struct kvm_vcpu *vcpu;
8448 int i;
0dd6a6ed
ZA		 8449 int ret;
8450 u64 local_tsc;
8451 u64 max_tsc = 0;
8452 bool stable, backwards_tsc = false;
18863bdd
AK		 8453
8454 kvm_shared_msr_cpu_online();
13a34e06 8455 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 8456 if (ret != 0)
8457 return ret;
8458
4ea1636b 8459 local_tsc = rdtsc();
b0c39dc6 8460 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 8461 list_for_each_entry(kvm, &vm_list, vm_list) {
8462 kvm_for_each_vcpu(i, vcpu, kvm) {
8463 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 8464 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8465 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8466 backwards_tsc = true;
8467 if (vcpu->arch.last_host_tsc > max_tsc)
8468 max_tsc = vcpu->arch.last_host_tsc;
8469 }
8470 }
8471 }
8472
8473 /*
8474 * Sometimes, even reliable TSCs go backwards. This happens on
8475 * platforms that reset TSC during suspend or hibernate actions, but
8476 * maintain synchronization. We must compensate. Fortunately, we can
8477 * detect that condition here, which happens early in CPU bringup,
8478 * before any KVM threads can be running. Unfortunately, we can't
8479 * bring the TSCs fully up to date with real time, as we aren't yet far
8480 * enough into CPU bringup that we know how much real time has actually
108b249c 8481 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 8482 * variables that haven't been updated yet.
8483 *
8484 * So we simply find the maximum observed TSC above, then record the
8485 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8486 * the adjustment will be applied. Note that we accumulate
8487 * adjustments, in case multiple suspend cycles happen before some VCPU
8488 * gets a chance to run again. In the event that no KVM threads get a
8489 * chance to run, we will miss the entire elapsed period, as we'll have
8490 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8491 * loose cycle time. This isn't too big a deal, since the loss will be
8492 * uniform across all VCPUs (not to mention the scenario is extremely
8493 * unlikely). It is possible that a second hibernate recovery happens
8494 * much faster than a first, causing the observed TSC here to be
8495 * smaller; this would require additional padding adjustment, which is
8496 * why we set last_host_tsc to the local tsc observed here.
8497 *
8498 * N.B. - this code below runs only on platforms with reliable TSC,
8499 * as that is the only way backwards_tsc is set above. Also note
8500 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8501 * have the same delta_cyc adjustment applied if backwards_tsc
8502 * is detected. Note further, this adjustment is only done once,
8503 * as we reset last_host_tsc on all VCPUs to stop this from being
8504 * called multiple times (one for each physical CPU bringup).
8505 *
4a969980 8506 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 8507 * will be compensated by the logic in vcpu_load, which sets the TSC to
8508 * catchup mode. This will catchup all VCPUs to real time, but cannot
8509 * guarantee that they stay in perfect synchronization.
8510 */
8511 if (backwards_tsc) {
8512 u64 delta_cyc = max_tsc - local_tsc;
8513 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8514 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 8515 kvm_for_each_vcpu(i, vcpu, kvm) {
8516 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8517 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8518 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8519 }
8520
8521 /*
8522 * We have to disable TSC offset matching.. if you were
8523 * booting a VM while issuing an S4 host suspend....
8524 * you may have some problem. Solving this issue is
8525 * left as an exercise to the reader.
8526 */
8527 kvm->arch.last_tsc_nsec = 0;
8528 kvm->arch.last_tsc_write = 0;
8529 }
8530
8531 }
8532 return 0;
e9b11c17
ZX		 8533}
8534
13a34e06 8535void kvm_arch_hardware_disable(void)
e9b11c17 8536{
13a34e06
RK		 8537 kvm_x86_ops->hardware_disable();
8538 drop_user_return_notifiers();
e9b11c17
ZX		 8539}
8540
8541int kvm_arch_hardware_setup(void)
8542{
9e9c3fe4
NA		 8543 int r;
8544
8545 r = kvm_x86_ops->hardware_setup();
8546 if (r != 0)
8547 return r;
8548
35181e86
HZ		 8549 if (kvm_has_tsc_control) {
8550 /*
8551 * Make sure the user can only configure tsc_khz values that
8552 * fit into a signed integer.
8553 * A min value is not calculated needed because it will always
8554 * be 1 on all machines.
8555 */
8556 u64 max = min(0x7fffffffULL,
8557 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8558 kvm_max_guest_tsc_khz = max;
8559
ad721883 8560 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8561 }
ad721883 8562
9e9c3fe4
NA		 8563 kvm_init_msr_list();
8564 return 0;
e9b11c17
ZX		 8565}
8566
8567void kvm_arch_hardware_unsetup(void)
8568{
8569 kvm_x86_ops->hardware_unsetup();
8570}
8571
8572void kvm_arch_check_processor_compat(void *rtn)
8573{
8574 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8575}
8576
8577bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8578{
8579 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8580}
8581EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8582
8583bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8584{
8585 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8586}
8587
54e9818f 8588struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8589EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8590
e9b11c17
ZX		 8591int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8592{
8593 struct page *page;
e9b11c17
ZX		 8594 int r;
8595
b2a05fef 8596 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8597 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8598 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8599 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8600 else
a4535290 8601 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8602
8603 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8604 if (!page) {
8605 r = -ENOMEM;
8606 goto fail;
8607 }
ad312c7c 8608 vcpu->arch.pio_data = page_address(page);
e9b11c17 8609
cc578287 8610 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8611
e9b11c17
ZX		 8612 r = kvm_mmu_create(vcpu);
8613 if (r < 0)
8614 goto fail_free_pio_data;
8615
26de7988 8616 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8617 r = kvm_create_lapic(vcpu);
8618 if (r < 0)
8619 goto fail_mmu_destroy;
54e9818f
GN		 8620 } else
8621 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8622
890ca9ae
HY		 8623 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8624 GFP_KERNEL);
8625 if (!vcpu->arch.mce_banks) {
8626 r = -ENOMEM;
443c39bc 8627 goto fail_free_lapic;
890ca9ae
HY		 8628 }
8629 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8630
f1797359
WY		 8631 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8632 r = -ENOMEM;
f5f48ee1 8633 goto fail_free_mce_banks;
f1797359 8634 }
f5f48ee1 8635
0ee6a517 8636 fx_init(vcpu);
66f7b72e 8637
4344ee98 8638 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8639
5a4f55cd
EK		 8640 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8641
74545705
RK		 8642 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8643
af585b92 8644 kvm_async_pf_hash_reset(vcpu);
f5132b01 8645 kvm_pmu_init(vcpu);
af585b92 8646
1c1a9ce9 8647 vcpu->arch.pending_external_vector = -1;
de63ad4c 8648 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8649
5c919412
AS		 8650 kvm_hv_vcpu_init(vcpu);
8651
e9b11c17 8652 return 0;
0ee6a517 8653
f5f48ee1
SY		 8654fail_free_mce_banks:
8655 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8656fail_free_lapic:
8657 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8658fail_mmu_destroy:
8659 kvm_mmu_destroy(vcpu);
8660fail_free_pio_data:
ad312c7c 8661 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8662fail:
8663 return r;
8664}
8665
8666void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8667{
f656ce01
MT		 8668 int idx;
8669
1f4b34f8 8670 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8671 kvm_pmu_destroy(vcpu);
36cb93fd 8672 kfree(vcpu->arch.mce_banks);
e9b11c17 8673 kvm_free_lapic(vcpu);
f656ce01 8674 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8675 kvm_mmu_destroy(vcpu);
f656ce01 8676 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8677 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8678 if (!lapic_in_kernel(vcpu))
54e9818f 8679 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8680}
d19a9cd2 8681
e790d9ef
RK		 8682void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8683{
ae97a3b8 8684 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8685}
8686
e08b9637 8687int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8688{
e08b9637
CO		 8689 if (type)
8690 return -EINVAL;
8691
6ef768fa 8692 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8693 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8694 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8695 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8696 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8697
5550af4d
SY		 8698 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8699 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8700 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8701 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8702 &kvm->arch.irq_sources_bitmap);
5550af4d 8703
038f8c11 8704 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8705 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 8706 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8707
108b249c 8708 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8709 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8710
7e44e449 8711 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8712 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8713
cbc0236a 8714 kvm_hv_init_vm(kvm);
0eb05bf2 8715 kvm_page_track_init(kvm);
13d268ca 8716 kvm_mmu_init_vm(kvm);
0eb05bf2 8717
03543133
SS		 8718 if (kvm_x86_ops->vm_init)
8719 return kvm_x86_ops->vm_init(kvm);
8720
d89f5eff 8721 return 0;
d19a9cd2
ZX		 8722}
8723
8724static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8725{
ec7660cc 8726 vcpu_load(vcpu);
d19a9cd2
ZX		 8727 kvm_mmu_unload(vcpu);
8728 vcpu_put(vcpu);
8729}
8730
8731static void kvm_free_vcpus(struct kvm *kvm)
8732{
8733 unsigned int i;
988a2cae 8734 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8735
8736 /*
8737 * Unpin any mmu pages first.
8738 */
af585b92
GN		 8739 kvm_for_each_vcpu(i, vcpu, kvm) {
8740 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8741 kvm_unload_vcpu_mmu(vcpu);
af585b92 8742 }
988a2cae
GN		 8743 kvm_for_each_vcpu(i, vcpu, kvm)
8744 kvm_arch_vcpu_free(vcpu);
8745
8746 mutex_lock(&kvm->lock);
8747 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8748 kvm->vcpus[i] = NULL;
d19a9cd2 8749
988a2cae
GN		 8750 atomic_set(&kvm->online_vcpus, 0);
8751 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8752}
8753
ad8ba2cd
SY		 8754void kvm_arch_sync_events(struct kvm *kvm)
8755{
332967a3 8756 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8757 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8758 kvm_free_pit(kvm);
ad8ba2cd
SY		 8759}
8760
1d8007bd 8761int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8762{
8763 int i, r;
25188b99 8764 unsigned long hva;
f0d648bd
PB		 8765 struct kvm_memslots *slots = kvm_memslots(kvm);
8766 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8767
8768 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8769 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8770 return -EINVAL;
9da0e4d5 8771
f0d648bd
PB		 8772 slot = id_to_memslot(slots, id);
8773 if (size) {
b21629da 8774 if (slot->npages)
f0d648bd
PB		 8775 return -EEXIST;
8776
8777 /*
8778 * MAP_SHARED to prevent internal slot pages from being moved
8779 * by fork()/COW.
8780 */
8781 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8782 MAP_SHARED | MAP_ANONYMOUS, 0);
8783 if (IS_ERR((void *)hva))
8784 return PTR_ERR((void *)hva);
8785 } else {
8786 if (!slot->npages)
8787 return 0;
8788
8789 hva = 0;
8790 }
8791
8792 old = *slot;
9da0e4d5 8793 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8794 struct kvm_userspace_memory_region m;
9da0e4d5 8795
1d8007bd
PB		 8796 m.slot = id | (i << 16);
8797 m.flags = 0;
8798 m.guest_phys_addr = gpa;
f0d648bd 8799 m.userspace_addr = hva;
1d8007bd 8800 m.memory_size = size;
9da0e4d5
PB		 8801 r = __kvm_set_memory_region(kvm, &m);
8802 if (r < 0)
8803 return r;
8804 }
8805
103c763c
EB		 8806 if (!size)
8807 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 8808
9da0e4d5
PB		 8809 return 0;
8810}
8811EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8812
1d8007bd 8813int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8814{
8815 int r;
8816
8817 mutex_lock(&kvm->slots_lock);
1d8007bd 8818 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8819 mutex_unlock(&kvm->slots_lock);
8820
8821 return r;
8822}
8823EXPORT_SYMBOL_GPL(x86_set_memory_region);
8824
d19a9cd2
ZX		 8825void kvm_arch_destroy_vm(struct kvm *kvm)
8826{
27469d29
AH		 8827 if (current->mm == kvm->mm) {
8828 /*
8829 * Free memory regions allocated on behalf of userspace,
8830 * unless the the memory map has changed due to process exit
8831 * or fd copying.
8832 */
1d8007bd
PB		 8833 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8834 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8835 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8836 }
03543133
SS		 8837 if (kvm_x86_ops->vm_destroy)
8838 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8839 kvm_pic_destroy(kvm);
8840 kvm_ioapic_destroy(kvm);
d19a9cd2 8841 kvm_free_vcpus(kvm);
af1bae54 8842 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8843 kvm_mmu_uninit_vm(kvm);
2beb6dad 8844 kvm_page_track_cleanup(kvm);
cbc0236a 8845 kvm_hv_destroy_vm(kvm);
d19a9cd2 8846}
0de10343 8847
5587027c 8848void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8849 struct kvm_memory_slot *dont)
8850{
8851 int i;
8852
d89cc617
TY		 8853 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8854 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8855 kvfree(free->arch.rmap[i]);
d89cc617 8856 free->arch.rmap[i] = NULL;
77d11309 8857 }
d89cc617
TY		 8858 if (i == 0)
8859 continue;
8860
8861 if (!dont || free->arch.lpage_info[i - 1] !=
8862 dont->arch.lpage_info[i - 1]) {
548ef284 8863 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8864 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8865 }
8866 }
21ebbeda
XG		 8867
8868 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8869}
8870
5587027c
AK		 8871int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8872 unsigned long npages)
db3fe4eb
TY		 8873{
8874 int i;
8875
d89cc617 8876 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8877 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8878 unsigned long ugfn;
8879 int lpages;
d89cc617 8880 int level = i + 1;
db3fe4eb
TY		 8881
8882 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8883 slot->base_gfn, level) + 1;
8884
d89cc617 8885 slot->arch.rmap[i] =
a7c3e901 8886 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8887 if (!slot->arch.rmap[i])
77d11309 8888 goto out_free;
d89cc617
TY		 8889 if (i == 0)
8890 continue;
77d11309 8891
a7c3e901 8892 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8893 if (!linfo)
db3fe4eb
TY		 8894 goto out_free;
8895
92f94f1e
XG		 8896 slot->arch.lpage_info[i - 1] = linfo;
8897
db3fe4eb 8898 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8899 linfo[0].disallow_lpage = 1;
db3fe4eb 8900 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8901 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8902 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8903 /*
8904 * If the gfn and userspace address are not aligned wrt each
8905 * other, or if explicitly asked to, disable large page
8906 * support for this slot
8907 */
8908 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8909 !kvm_largepages_enabled()) {
8910 unsigned long j;
8911
8912 for (j = 0; j < lpages; ++j)
92f94f1e 8913 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8914 }
8915 }
8916
21ebbeda
XG		 8917 if (kvm_page_track_create_memslot(slot, npages))
8918 goto out_free;
8919
db3fe4eb
TY		 8920 return 0;
8921
8922out_free:
d89cc617 8923 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8924 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8925 slot->arch.rmap[i] = NULL;
8926 if (i == 0)
8927 continue;
8928
548ef284 8929 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8930 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8931 }
8932 return -ENOMEM;
8933}
8934
15f46015 8935void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8936{
e6dff7d1
TY		 8937 /*
8938 * memslots->generation has been incremented.
8939 * mmio generation may have reached its maximum value.
8940 */
54bf36aa 8941 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8942}
8943
f7784b8e
MT		 8944int kvm_arch_prepare_memory_region(struct kvm *kvm,
8945 struct kvm_memory_slot *memslot,
09170a49 8946 const struct kvm_userspace_memory_region *mem,
7b6195a9 8947 enum kvm_mr_change change)
0de10343 8948{
f7784b8e
MT		 8949 return 0;
8950}
8951
88178fd4
KH		 8952static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8953 struct kvm_memory_slot *new)
8954{
8955 /* Still write protect RO slot */
8956 if (new->flags & KVM_MEM_READONLY) {
8957 kvm_mmu_slot_remove_write_access(kvm, new);
8958 return;
8959 }
8960
8961 /*
8962 * Call kvm_x86_ops dirty logging hooks when they are valid.
8963 *
8964 * kvm_x86_ops->slot_disable_log_dirty is called when:
8965 *
8966 * - KVM_MR_CREATE with dirty logging is disabled
8967 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8968 *
8969 * The reason is, in case of PML, we need to set D-bit for any slots
8970 * with dirty logging disabled in order to eliminate unnecessary GPA
8971 * logging in PML buffer (and potential PML buffer full VMEXT). This
8972 * guarantees leaving PML enabled during guest's lifetime won't have
8973 * any additonal overhead from PML when guest is running with dirty
8974 * logging disabled for memory slots.
8975 *
8976 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8977 * to dirty logging mode.
8978 *
8979 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8980 *
8981 * In case of write protect:
8982 *
8983 * Write protect all pages for dirty logging.
8984 *
8985 * All the sptes including the large sptes which point to this
8986 * slot are set to readonly. We can not create any new large
8987 * spte on this slot until the end of the logging.
8988 *
8989 * See the comments in fast_page_fault().
8990 */
8991 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8992 if (kvm_x86_ops->slot_enable_log_dirty)
8993 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8994 else
8995 kvm_mmu_slot_remove_write_access(kvm, new);
8996 } else {
8997 if (kvm_x86_ops->slot_disable_log_dirty)
8998 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8999 }
9000}
9001
f7784b8e 9002void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 9003 const struct kvm_userspace_memory_region *mem,
8482644a 9004 const struct kvm_memory_slot *old,
f36f3f28 9005 const struct kvm_memory_slot *new,
8482644a 9006 enum kvm_mr_change change)
f7784b8e 9007{
8482644a 9008 int nr_mmu_pages = 0;
f7784b8e 9009
48c0e4e9
XG		 9010 if (!kvm->arch.n_requested_mmu_pages)
9011 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
9012
48c0e4e9 9013 if (nr_mmu_pages)
0de10343 9014 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 9015
3ea3b7fa
WL		 9016 /*
9017 * Dirty logging tracks sptes in 4k granularity, meaning that large
9018 * sptes have to be split. If live migration is successful, the guest
9019 * in the source machine will be destroyed and large sptes will be
9020 * created in the destination. However, if the guest continues to run
9021 * in the source machine (for example if live migration fails), small
9022 * sptes will remain around and cause bad performance.
9023 *
9024 * Scan sptes if dirty logging has been stopped, dropping those
9025 * which can be collapsed into a single large-page spte. Later
9026 * page faults will create the large-page sptes.
9027 */
9028 if ((change != KVM_MR_DELETE) &&
9029 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9030 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9031 kvm_mmu_zap_collapsible_sptes(kvm, new);
9032
c972f3b1 9033 /*
88178fd4 9034 * Set up write protection and/or dirty logging for the new slot.
c126d94f 9035 *
88178fd4
KH		 9036 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9037 * been zapped so no dirty logging staff is needed for old slot. For
9038 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9039 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 9040 *
9041 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 9042 */
88178fd4 9043 if (change != KVM_MR_DELETE)
f36f3f28 9044 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 9045}
1d737c8a 9046
2df72e9b 9047void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 9048{
6ca18b69 9049 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 9050}
9051
2df72e9b
MT		 9052void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9053 struct kvm_memory_slot *slot)
9054{
ae7cd873 9055 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 9056}
9057
5d9bc648
PB		 9058static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9059{
9060 if (!list_empty_careful(&vcpu->async_pf.done))
9061 return true;
9062
9063 if (kvm_apic_has_events(vcpu))
9064 return true;
9065
9066 if (vcpu->arch.pv.pv_unhalted)
9067 return true;
9068
a5f01f8e
WL		 9069 if (vcpu->arch.exception.pending)
9070 return true;
9071
47a66eed
Z		 9072 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9073 (vcpu->arch.nmi_pending &&
9074 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 9075 return true;
9076
47a66eed
Z		 9077 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9078 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 9079 return true;
9080
5d9bc648
PB		 9081 if (kvm_arch_interrupt_allowed(vcpu) &&
9082 kvm_cpu_has_interrupt(vcpu))
9083 return true;
9084
1f4b34f8
AS		 9085 if (kvm_hv_has_stimer_pending(vcpu))
9086 return true;
9087
5d9bc648
PB		 9088 return false;
9089}
9090
1d737c8a
ZX		 9091int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9092{
5d9bc648 9093 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 9094}
5736199a 9095
199b5763
LM		 9096bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9097{
de63ad4c 9098 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 9099}
9100
b6d33834 9101int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 9102{
b6d33834 9103 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 9104}
78646121
GN		 9105
9106int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9107{
9108 return kvm_x86_ops->interrupt_allowed(vcpu);
9109}
229456fc 9110
82b32774 9111unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 9112{
82b32774
NA		 9113 if (is_64_bit_mode(vcpu))
9114 return kvm_rip_read(vcpu);
9115 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9116 kvm_rip_read(vcpu));
9117}
9118EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 9119
82b32774
NA		 9120bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9121{
9122 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 9123}
9124EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9125
94fe45da
JK		 9126unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9127{
9128 unsigned long rflags;
9129
9130 rflags = kvm_x86_ops->get_rflags(vcpu);
9131 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 9132 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 9133 return rflags;
9134}
9135EXPORT_SYMBOL_GPL(kvm_get_rflags);
9136
6addfc42 9137static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 9138{
9139 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 9140 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 9141 rflags |= X86_EFLAGS_TF;
94fe45da 9142 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 9143}
9144
9145void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9146{
9147 __kvm_set_rflags(vcpu, rflags);
3842d135 9148 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 9149}
9150EXPORT_SYMBOL_GPL(kvm_set_rflags);
9151
56028d08
GN		 9152void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9153{
9154 int r;
9155
fb67e14f 9156 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 9157 work->wakeup_all)
56028d08
GN		 9158 return;
9159
9160 r = kvm_mmu_reload(vcpu);
9161 if (unlikely(r))
9162 return;
9163
fb67e14f
XG		 9164 if (!vcpu->arch.mmu.direct_map &&
9165 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
9166 return;
9167
56028d08
GN		 9168 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
9169}
9170
af585b92
GN		 9171static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9172{
9173 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9174}
9175
9176static inline u32 kvm_async_pf_next_probe(u32 key)
9177{
9178 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9179}
9180
9181static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9182{
9183 u32 key = kvm_async_pf_hash_fn(gfn);
9184
9185 while (vcpu->arch.apf.gfns[key] != ~0)
9186 key = kvm_async_pf_next_probe(key);
9187
9188 vcpu->arch.apf.gfns[key] = gfn;
9189}
9190
9191static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9192{
9193 int i;
9194 u32 key = kvm_async_pf_hash_fn(gfn);
9195
9196 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9197 (vcpu->arch.apf.gfns[key] != gfn &&
9198 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9199 key = kvm_async_pf_next_probe(key);
9200
9201 return key;
9202}
9203
9204bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9205{
9206 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9207}
9208
9209static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9210{
9211 u32 i, j, k;
9212
9213 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9214 while (true) {
9215 vcpu->arch.apf.gfns[i] = ~0;
9216 do {
9217 j = kvm_async_pf_next_probe(j);
9218 if (vcpu->arch.apf.gfns[j] == ~0)
9219 return;
9220 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9221 /*
9222 * k lies cyclically in ]i,j]
9223 * | i.k.j |
9224 * |....j i.k.| or |.k..j i...|
9225 */
9226 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9227 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9228 i = j;
9229 }
9230}
9231
7c90705b
GN		 9232static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9233{
4e335d9e
PB		 9234
9235 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9236 sizeof(val));
7c90705b
GN		 9237}
9238
9a6e7c39
WL		 9239static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9240{
9241
9242 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9243 sizeof(u32));
9244}
9245
af585b92
GN		 9246void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9247 struct kvm_async_pf *work)
9248{
6389ee94
AK		 9249 struct x86_exception fault;
9250
7c90705b 9251 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 9252 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 9253
9254 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 9255 (vcpu->arch.apf.send_user_only &&
9256 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 9257 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9258 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 9259 fault.vector = PF_VECTOR;
9260 fault.error_code_valid = true;
9261 fault.error_code = 0;
9262 fault.nested_page_fault = false;
9263 fault.address = work->arch.token;
adfe20fb 9264 fault.async_page_fault = true;
6389ee94 9265 kvm_inject_page_fault(vcpu, &fault);
7c90705b 9266 }
af585b92
GN		 9267}
9268
9269void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9270 struct kvm_async_pf *work)
9271{
6389ee94 9272 struct x86_exception fault;
9a6e7c39 9273 u32 val;
6389ee94 9274
f2e10669 9275 if (work->wakeup_all)
7c90705b
GN		 9276 work->arch.token = ~0; /* broadcast wakeup */
9277 else
9278 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 9279 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 9280
9a6e7c39
WL		 9281 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9282 !apf_get_user(vcpu, &val)) {
9283 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9284 vcpu->arch.exception.pending &&
9285 vcpu->arch.exception.nr == PF_VECTOR &&
9286 !apf_put_user(vcpu, 0)) {
9287 vcpu->arch.exception.injected = false;
9288 vcpu->arch.exception.pending = false;
9289 vcpu->arch.exception.nr = 0;
9290 vcpu->arch.exception.has_error_code = false;
9291 vcpu->arch.exception.error_code = 0;
9292 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9293 fault.vector = PF_VECTOR;
9294 fault.error_code_valid = true;
9295 fault.error_code = 0;
9296 fault.nested_page_fault = false;
9297 fault.address = work->arch.token;
9298 fault.async_page_fault = true;
9299 kvm_inject_page_fault(vcpu, &fault);
9300 }
7c90705b 9301 }
e6d53e3b 9302 vcpu->arch.apf.halted = false;
a4fa1635 9303 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 9304}
9305
9306bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9307{
9308 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9309 return true;
9310 else
9bc1f09f 9311 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 9312}
9313
5544eb9b
PB		 9314void kvm_arch_start_assignment(struct kvm *kvm)
9315{
9316 atomic_inc(&kvm->arch.assigned_device_count);
9317}
9318EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9319
9320void kvm_arch_end_assignment(struct kvm *kvm)
9321{
9322 atomic_dec(&kvm->arch.assigned_device_count);
9323}
9324EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9325
9326bool kvm_arch_has_assigned_device(struct kvm *kvm)
9327{
9328 return atomic_read(&kvm->arch.assigned_device_count);
9329}
9330EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9331
e0f0bbc5
AW		 9332void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9333{
9334 atomic_inc(&kvm->arch.noncoherent_dma_count);
9335}
9336EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9337
9338void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9339{
9340 atomic_dec(&kvm->arch.noncoherent_dma_count);
9341}
9342EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9343
9344bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9345{
9346 return atomic_read(&kvm->arch.noncoherent_dma_count);
9347}
9348EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9349
14717e20
AW		 9350bool kvm_arch_has_irq_bypass(void)
9351{
9352 return kvm_x86_ops->update_pi_irte != NULL;
9353}
9354
87276880
FW		 9355int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9356 struct irq_bypass_producer *prod)
9357{
9358 struct kvm_kernel_irqfd *irqfd =
9359 container_of(cons, struct kvm_kernel_irqfd, consumer);
9360
14717e20 9361 irqfd->producer = prod;
87276880 9362
14717e20
AW		 9363 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9364 prod->irq, irqfd->gsi, 1);
87276880
FW		 9365}
9366
9367void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9368 struct irq_bypass_producer *prod)
9369{
9370 int ret;
9371 struct kvm_kernel_irqfd *irqfd =
9372 container_of(cons, struct kvm_kernel_irqfd, consumer);
9373
87276880
FW		 9374 WARN_ON(irqfd->producer != prod);
9375 irqfd->producer = NULL;
9376
9377 /*
9378 * When producer of consumer is unregistered, we change back to
9379 * remapped mode, so we can re-use the current implementation
bb3541f1 9380 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 9381 * int this case doesn't want to receive the interrupts.
9382 */
9383 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9384 if (ret)
9385 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9386 " fails: %d\n", irqfd->consumer.token, ret);
9387}
9388
9389int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9390 uint32_t guest_irq, bool set)
9391{
9392 if (!kvm_x86_ops->update_pi_irte)
9393 return -EINVAL;
9394
9395 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9396}
9397
52004014
FW		 9398bool kvm_vector_hashing_enabled(void)
9399{
9400 return vector_hashing;
9401}
9402EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9403
229456fc 9404EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 9405EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 9406EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9407EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9408EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9409EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 9410EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 9411EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 9412EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 9413EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 9414EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 9415EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 9416EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 9417EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 9418EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 9419EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 9420EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 9421EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9422EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Ubuntu Focal Linux kernel mirror