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20c8ccb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
043405e1 CO |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * | |
5 | * derived from drivers/kvm/kvm_main.c | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
8 | * Copyright (C) 2008 Qumranet, Inc. |
9 | * Copyright IBM Corporation, 2008 | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
043405e1 CO |
11 | * |
12 | * Authors: | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
15 | * Amit Shah <amit.shah@qumranet.com> |
16 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
17 | */ |
18 | ||
edf88417 | 19 | #include <linux/kvm_host.h> |
313a3dc7 | 20 | #include "irq.h" |
1d737c8a | 21 | #include "mmu.h" |
7837699f | 22 | #include "i8254.h" |
37817f29 | 23 | #include "tss.h" |
5fdbf976 | 24 | #include "kvm_cache_regs.h" |
26eef70c | 25 | #include "x86.h" |
00b27a3e | 26 | #include "cpuid.h" |
474a5bb9 | 27 | #include "pmu.h" |
e83d5887 | 28 | #include "hyperv.h" |
313a3dc7 | 29 | |
18068523 | 30 | #include <linux/clocksource.h> |
4d5c5d0f | 31 | #include <linux/interrupt.h> |
313a3dc7 CO |
32 | #include <linux/kvm.h> |
33 | #include <linux/fs.h> | |
34 | #include <linux/vmalloc.h> | |
1767e931 PG |
35 | #include <linux/export.h> |
36 | #include <linux/moduleparam.h> | |
0de10343 | 37 | #include <linux/mman.h> |
2bacc55c | 38 | #include <linux/highmem.h> |
19de40a8 | 39 | #include <linux/iommu.h> |
62c476c7 | 40 | #include <linux/intel-iommu.h> |
c8076604 | 41 | #include <linux/cpufreq.h> |
18863bdd | 42 | #include <linux/user-return-notifier.h> |
a983fb23 | 43 | #include <linux/srcu.h> |
5a0e3ad6 | 44 | #include <linux/slab.h> |
ff9d07a0 | 45 | #include <linux/perf_event.h> |
7bee342a | 46 | #include <linux/uaccess.h> |
af585b92 | 47 | #include <linux/hash.h> |
a1b60c1c | 48 | #include <linux/pci.h> |
16e8d74d MT |
49 | #include <linux/timekeeper_internal.h> |
50 | #include <linux/pvclock_gtod.h> | |
87276880 FW |
51 | #include <linux/kvm_irqfd.h> |
52 | #include <linux/irqbypass.h> | |
3905f9ad | 53 | #include <linux/sched/stat.h> |
0c5f81da | 54 | #include <linux/sched/isolation.h> |
d0ec49d4 | 55 | #include <linux/mem_encrypt.h> |
3905f9ad | 56 | |
aec51dc4 | 57 | #include <trace/events/kvm.h> |
2ed152af | 58 | |
24f1e32c | 59 | #include <asm/debugreg.h> |
d825ed0a | 60 | #include <asm/msr.h> |
a5f61300 | 61 | #include <asm/desc.h> |
890ca9ae | 62 | #include <asm/mce.h> |
f89e32e0 | 63 | #include <linux/kernel_stat.h> |
78f7f1e5 | 64 | #include <asm/fpu/internal.h> /* Ugh! */ |
1d5f066e | 65 | #include <asm/pvclock.h> |
217fc9cf | 66 | #include <asm/div64.h> |
efc64404 | 67 | #include <asm/irq_remapping.h> |
b0c39dc6 | 68 | #include <asm/mshyperv.h> |
0092e434 | 69 | #include <asm/hypervisor.h> |
bf8c55d8 | 70 | #include <asm/intel_pt.h> |
dd2cb348 | 71 | #include <clocksource/hyperv_timer.h> |
043405e1 | 72 | |
d1898b73 DH |
73 | #define CREATE_TRACE_POINTS |
74 | #include "trace.h" | |
75 | ||
313a3dc7 | 76 | #define MAX_IO_MSRS 256 |
890ca9ae | 77 | #define KVM_MAX_MCE_BANKS 32 |
c45dcc71 AR |
78 | u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; |
79 | EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); | |
890ca9ae | 80 | |
0f65dd70 AK |
81 | #define emul_to_vcpu(ctxt) \ |
82 | container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) | |
83 | ||
50a37eb4 JR |
84 | /* EFER defaults: |
85 | * - enable syscall per default because its emulated by KVM | |
86 | * - enable LME and LMA per default on 64 bit KVM | |
87 | */ | |
88 | #ifdef CONFIG_X86_64 | |
1260edbe LJ |
89 | static |
90 | u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); | |
50a37eb4 | 91 | #else |
1260edbe | 92 | static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); |
50a37eb4 | 93 | #endif |
313a3dc7 | 94 | |
ba1389b7 AK |
95 | #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM |
96 | #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU | |
417bc304 | 97 | |
c519265f RK |
98 | #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ |
99 | KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) | |
37131313 | 100 | |
cb142eb7 | 101 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
7460fb4a | 102 | static void process_nmi(struct kvm_vcpu *vcpu); |
ee2cd4b7 | 103 | static void enter_smm(struct kvm_vcpu *vcpu); |
6addfc42 | 104 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); |
01643c51 KH |
105 | static void store_regs(struct kvm_vcpu *vcpu); |
106 | static int sync_regs(struct kvm_vcpu *vcpu); | |
674eea0f | 107 | |
893590c7 | 108 | struct kvm_x86_ops *kvm_x86_ops __read_mostly; |
5fdbf976 | 109 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 110 | |
893590c7 | 111 | static bool __read_mostly ignore_msrs = 0; |
476bc001 | 112 | module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); |
ed85c068 | 113 | |
fab0aa3b EM |
114 | static bool __read_mostly report_ignored_msrs = true; |
115 | module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); | |
116 | ||
4c27625b | 117 | unsigned int min_timer_period_us = 200; |
9ed96e87 MT |
118 | module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); |
119 | ||
630994b3 MT |
120 | static bool __read_mostly kvmclock_periodic_sync = true; |
121 | module_param(kvmclock_periodic_sync, bool, S_IRUGO); | |
122 | ||
893590c7 | 123 | bool __read_mostly kvm_has_tsc_control; |
92a1f12d | 124 | EXPORT_SYMBOL_GPL(kvm_has_tsc_control); |
893590c7 | 125 | u32 __read_mostly kvm_max_guest_tsc_khz; |
92a1f12d | 126 | EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); |
bc9b961b HZ |
127 | u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; |
128 | EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); | |
129 | u64 __read_mostly kvm_max_tsc_scaling_ratio; | |
130 | EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); | |
64672c95 YJ |
131 | u64 __read_mostly kvm_default_tsc_scaling_ratio; |
132 | EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); | |
92a1f12d | 133 | |
cc578287 | 134 | /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ |
893590c7 | 135 | static u32 __read_mostly tsc_tolerance_ppm = 250; |
cc578287 ZA |
136 | module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); |
137 | ||
c3941d9e SC |
138 | /* |
139 | * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables | |
140 | * adaptive tuning starting from default advancment of 1000ns. '0' disables | |
141 | * advancement entirely. Any other value is used as-is and disables adaptive | |
142 | * tuning, i.e. allows priveleged userspace to set an exact advancement time. | |
143 | */ | |
144 | static int __read_mostly lapic_timer_advance_ns = -1; | |
0e6edceb | 145 | module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR); |
d0659d94 | 146 | |
52004014 FW |
147 | static bool __read_mostly vector_hashing = true; |
148 | module_param(vector_hashing, bool, S_IRUGO); | |
149 | ||
c4ae60e4 LA |
150 | bool __read_mostly enable_vmware_backdoor = false; |
151 | module_param(enable_vmware_backdoor, bool, S_IRUGO); | |
152 | EXPORT_SYMBOL_GPL(enable_vmware_backdoor); | |
153 | ||
6c86eedc WL |
154 | static bool __read_mostly force_emulation_prefix = false; |
155 | module_param(force_emulation_prefix, bool, S_IRUGO); | |
156 | ||
0c5f81da WL |
157 | int __read_mostly pi_inject_timer = -1; |
158 | module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); | |
159 | ||
18863bdd AK |
160 | #define KVM_NR_SHARED_MSRS 16 |
161 | ||
162 | struct kvm_shared_msrs_global { | |
163 | int nr; | |
2bf78fa7 | 164 | u32 msrs[KVM_NR_SHARED_MSRS]; |
18863bdd AK |
165 | }; |
166 | ||
167 | struct kvm_shared_msrs { | |
168 | struct user_return_notifier urn; | |
169 | bool registered; | |
2bf78fa7 SY |
170 | struct kvm_shared_msr_values { |
171 | u64 host; | |
172 | u64 curr; | |
173 | } values[KVM_NR_SHARED_MSRS]; | |
18863bdd AK |
174 | }; |
175 | ||
176 | static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; | |
013f6a5d | 177 | static struct kvm_shared_msrs __percpu *shared_msrs; |
18863bdd | 178 | |
417bc304 | 179 | struct kvm_stats_debugfs_item debugfs_entries[] = { |
ba1389b7 AK |
180 | { "pf_fixed", VCPU_STAT(pf_fixed) }, |
181 | { "pf_guest", VCPU_STAT(pf_guest) }, | |
182 | { "tlb_flush", VCPU_STAT(tlb_flush) }, | |
183 | { "invlpg", VCPU_STAT(invlpg) }, | |
184 | { "exits", VCPU_STAT(exits) }, | |
185 | { "io_exits", VCPU_STAT(io_exits) }, | |
186 | { "mmio_exits", VCPU_STAT(mmio_exits) }, | |
187 | { "signal_exits", VCPU_STAT(signal_exits) }, | |
188 | { "irq_window", VCPU_STAT(irq_window_exits) }, | |
f08864b4 | 189 | { "nmi_window", VCPU_STAT(nmi_window_exits) }, |
ba1389b7 | 190 | { "halt_exits", VCPU_STAT(halt_exits) }, |
f7819512 | 191 | { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, |
62bea5bf | 192 | { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) }, |
3491caf2 | 193 | { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) }, |
ba1389b7 | 194 | { "halt_wakeup", VCPU_STAT(halt_wakeup) }, |
f11c3a8d | 195 | { "hypercalls", VCPU_STAT(hypercalls) }, |
ba1389b7 AK |
196 | { "request_irq", VCPU_STAT(request_irq_exits) }, |
197 | { "irq_exits", VCPU_STAT(irq_exits) }, | |
198 | { "host_state_reload", VCPU_STAT(host_state_reload) }, | |
ba1389b7 AK |
199 | { "fpu_reload", VCPU_STAT(fpu_reload) }, |
200 | { "insn_emulation", VCPU_STAT(insn_emulation) }, | |
201 | { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, | |
fa89a817 | 202 | { "irq_injections", VCPU_STAT(irq_injections) }, |
c4abb7c9 | 203 | { "nmi_injections", VCPU_STAT(nmi_injections) }, |
0f1e261e | 204 | { "req_event", VCPU_STAT(req_event) }, |
c595ceee | 205 | { "l1d_flush", VCPU_STAT(l1d_flush) }, |
4cee5764 AK |
206 | { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, |
207 | { "mmu_pte_write", VM_STAT(mmu_pte_write) }, | |
208 | { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, | |
209 | { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, | |
210 | { "mmu_flooded", VM_STAT(mmu_flooded) }, | |
211 | { "mmu_recycled", VM_STAT(mmu_recycled) }, | |
dfc5aa00 | 212 | { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, |
4731d4c7 | 213 | { "mmu_unsync", VM_STAT(mmu_unsync) }, |
0f74a24c | 214 | { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, |
05da4558 | 215 | { "largepages", VM_STAT(lpages) }, |
f3414bc7 DM |
216 | { "max_mmu_page_hash_collisions", |
217 | VM_STAT(max_mmu_page_hash_collisions) }, | |
417bc304 HB |
218 | { NULL } |
219 | }; | |
220 | ||
2acf923e DC |
221 | u64 __read_mostly host_xcr0; |
222 | ||
b666a4b6 MO |
223 | struct kmem_cache *x86_fpu_cache; |
224 | EXPORT_SYMBOL_GPL(x86_fpu_cache); | |
225 | ||
b6785def | 226 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); |
d6aa1000 | 227 | |
af585b92 GN |
228 | static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) |
229 | { | |
230 | int i; | |
231 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) | |
232 | vcpu->arch.apf.gfns[i] = ~0; | |
233 | } | |
234 | ||
18863bdd AK |
235 | static void kvm_on_user_return(struct user_return_notifier *urn) |
236 | { | |
237 | unsigned slot; | |
18863bdd AK |
238 | struct kvm_shared_msrs *locals |
239 | = container_of(urn, struct kvm_shared_msrs, urn); | |
2bf78fa7 | 240 | struct kvm_shared_msr_values *values; |
1650b4eb IA |
241 | unsigned long flags; |
242 | ||
243 | /* | |
244 | * Disabling irqs at this point since the following code could be | |
245 | * interrupted and executed through kvm_arch_hardware_disable() | |
246 | */ | |
247 | local_irq_save(flags); | |
248 | if (locals->registered) { | |
249 | locals->registered = false; | |
250 | user_return_notifier_unregister(urn); | |
251 | } | |
252 | local_irq_restore(flags); | |
18863bdd | 253 | for (slot = 0; slot < shared_msrs_global.nr; ++slot) { |
2bf78fa7 SY |
254 | values = &locals->values[slot]; |
255 | if (values->host != values->curr) { | |
256 | wrmsrl(shared_msrs_global.msrs[slot], values->host); | |
257 | values->curr = values->host; | |
18863bdd AK |
258 | } |
259 | } | |
18863bdd AK |
260 | } |
261 | ||
2bf78fa7 | 262 | static void shared_msr_update(unsigned slot, u32 msr) |
18863bdd | 263 | { |
18863bdd | 264 | u64 value; |
013f6a5d MT |
265 | unsigned int cpu = smp_processor_id(); |
266 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
18863bdd | 267 | |
2bf78fa7 SY |
268 | /* only read, and nobody should modify it at this time, |
269 | * so don't need lock */ | |
270 | if (slot >= shared_msrs_global.nr) { | |
271 | printk(KERN_ERR "kvm: invalid MSR slot!"); | |
272 | return; | |
273 | } | |
274 | rdmsrl_safe(msr, &value); | |
275 | smsr->values[slot].host = value; | |
276 | smsr->values[slot].curr = value; | |
277 | } | |
278 | ||
279 | void kvm_define_shared_msr(unsigned slot, u32 msr) | |
280 | { | |
0123be42 | 281 | BUG_ON(slot >= KVM_NR_SHARED_MSRS); |
c847fe88 | 282 | shared_msrs_global.msrs[slot] = msr; |
18863bdd AK |
283 | if (slot >= shared_msrs_global.nr) |
284 | shared_msrs_global.nr = slot + 1; | |
18863bdd AK |
285 | } |
286 | EXPORT_SYMBOL_GPL(kvm_define_shared_msr); | |
287 | ||
288 | static void kvm_shared_msr_cpu_online(void) | |
289 | { | |
290 | unsigned i; | |
18863bdd AK |
291 | |
292 | for (i = 0; i < shared_msrs_global.nr; ++i) | |
2bf78fa7 | 293 | shared_msr_update(i, shared_msrs_global.msrs[i]); |
18863bdd AK |
294 | } |
295 | ||
8b3c3104 | 296 | int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) |
18863bdd | 297 | { |
013f6a5d MT |
298 | unsigned int cpu = smp_processor_id(); |
299 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
8b3c3104 | 300 | int err; |
18863bdd | 301 | |
2bf78fa7 | 302 | if (((value ^ smsr->values[slot].curr) & mask) == 0) |
8b3c3104 | 303 | return 0; |
2bf78fa7 | 304 | smsr->values[slot].curr = value; |
8b3c3104 AH |
305 | err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); |
306 | if (err) | |
307 | return 1; | |
308 | ||
18863bdd AK |
309 | if (!smsr->registered) { |
310 | smsr->urn.on_user_return = kvm_on_user_return; | |
311 | user_return_notifier_register(&smsr->urn); | |
312 | smsr->registered = true; | |
313 | } | |
8b3c3104 | 314 | return 0; |
18863bdd AK |
315 | } |
316 | EXPORT_SYMBOL_GPL(kvm_set_shared_msr); | |
317 | ||
13a34e06 | 318 | static void drop_user_return_notifiers(void) |
3548bab5 | 319 | { |
013f6a5d MT |
320 | unsigned int cpu = smp_processor_id(); |
321 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
3548bab5 AK |
322 | |
323 | if (smsr->registered) | |
324 | kvm_on_user_return(&smsr->urn); | |
325 | } | |
326 | ||
6866b83e CO |
327 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
328 | { | |
8a5a87d9 | 329 | return vcpu->arch.apic_base; |
6866b83e CO |
330 | } |
331 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
332 | ||
58871649 JM |
333 | enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) |
334 | { | |
335 | return kvm_apic_mode(kvm_get_apic_base(vcpu)); | |
336 | } | |
337 | EXPORT_SYMBOL_GPL(kvm_get_apic_mode); | |
338 | ||
58cb628d JK |
339 | int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
340 | { | |
58871649 JM |
341 | enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); |
342 | enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); | |
d6321d49 RK |
343 | u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff | |
344 | (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); | |
58cb628d | 345 | |
58871649 | 346 | if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) |
58cb628d | 347 | return 1; |
58871649 JM |
348 | if (!msr_info->host_initiated) { |
349 | if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) | |
350 | return 1; | |
351 | if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) | |
352 | return 1; | |
353 | } | |
58cb628d JK |
354 | |
355 | kvm_lapic_set_base(vcpu, msr_info->data); | |
356 | return 0; | |
6866b83e CO |
357 | } |
358 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
359 | ||
2605fc21 | 360 | asmlinkage __visible void kvm_spurious_fault(void) |
e3ba45b8 GL |
361 | { |
362 | /* Fault while not rebooting. We want the trace. */ | |
363 | BUG(); | |
364 | } | |
365 | EXPORT_SYMBOL_GPL(kvm_spurious_fault); | |
366 | ||
3fd28fce ED |
367 | #define EXCPT_BENIGN 0 |
368 | #define EXCPT_CONTRIBUTORY 1 | |
369 | #define EXCPT_PF 2 | |
370 | ||
371 | static int exception_class(int vector) | |
372 | { | |
373 | switch (vector) { | |
374 | case PF_VECTOR: | |
375 | return EXCPT_PF; | |
376 | case DE_VECTOR: | |
377 | case TS_VECTOR: | |
378 | case NP_VECTOR: | |
379 | case SS_VECTOR: | |
380 | case GP_VECTOR: | |
381 | return EXCPT_CONTRIBUTORY; | |
382 | default: | |
383 | break; | |
384 | } | |
385 | return EXCPT_BENIGN; | |
386 | } | |
387 | ||
d6e8c854 NA |
388 | #define EXCPT_FAULT 0 |
389 | #define EXCPT_TRAP 1 | |
390 | #define EXCPT_ABORT 2 | |
391 | #define EXCPT_INTERRUPT 3 | |
392 | ||
393 | static int exception_type(int vector) | |
394 | { | |
395 | unsigned int mask; | |
396 | ||
397 | if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) | |
398 | return EXCPT_INTERRUPT; | |
399 | ||
400 | mask = 1 << vector; | |
401 | ||
402 | /* #DB is trap, as instruction watchpoints are handled elsewhere */ | |
403 | if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) | |
404 | return EXCPT_TRAP; | |
405 | ||
406 | if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) | |
407 | return EXCPT_ABORT; | |
408 | ||
409 | /* Reserved exceptions will result in fault */ | |
410 | return EXCPT_FAULT; | |
411 | } | |
412 | ||
da998b46 JM |
413 | void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) |
414 | { | |
415 | unsigned nr = vcpu->arch.exception.nr; | |
416 | bool has_payload = vcpu->arch.exception.has_payload; | |
417 | unsigned long payload = vcpu->arch.exception.payload; | |
418 | ||
419 | if (!has_payload) | |
420 | return; | |
421 | ||
422 | switch (nr) { | |
f10c729f JM |
423 | case DB_VECTOR: |
424 | /* | |
425 | * "Certain debug exceptions may clear bit 0-3. The | |
426 | * remaining contents of the DR6 register are never | |
427 | * cleared by the processor". | |
428 | */ | |
429 | vcpu->arch.dr6 &= ~DR_TRAP_BITS; | |
430 | /* | |
431 | * DR6.RTM is set by all #DB exceptions that don't clear it. | |
432 | */ | |
433 | vcpu->arch.dr6 |= DR6_RTM; | |
434 | vcpu->arch.dr6 |= payload; | |
435 | /* | |
436 | * Bit 16 should be set in the payload whenever the #DB | |
437 | * exception should clear DR6.RTM. This makes the payload | |
438 | * compatible with the pending debug exceptions under VMX. | |
439 | * Though not currently documented in the SDM, this also | |
440 | * makes the payload compatible with the exit qualification | |
441 | * for #DB exceptions under VMX. | |
442 | */ | |
443 | vcpu->arch.dr6 ^= payload & DR6_RTM; | |
444 | break; | |
da998b46 JM |
445 | case PF_VECTOR: |
446 | vcpu->arch.cr2 = payload; | |
447 | break; | |
448 | } | |
449 | ||
450 | vcpu->arch.exception.has_payload = false; | |
451 | vcpu->arch.exception.payload = 0; | |
452 | } | |
453 | EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); | |
454 | ||
3fd28fce | 455 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, |
ce7ddec4 | 456 | unsigned nr, bool has_error, u32 error_code, |
91e86d22 | 457 | bool has_payload, unsigned long payload, bool reinject) |
3fd28fce ED |
458 | { |
459 | u32 prev_nr; | |
460 | int class1, class2; | |
461 | ||
3842d135 AK |
462 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
463 | ||
664f8e26 | 464 | if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { |
3fd28fce | 465 | queue: |
3ffb2468 NA |
466 | if (has_error && !is_protmode(vcpu)) |
467 | has_error = false; | |
664f8e26 WL |
468 | if (reinject) { |
469 | /* | |
470 | * On vmentry, vcpu->arch.exception.pending is only | |
471 | * true if an event injection was blocked by | |
472 | * nested_run_pending. In that case, however, | |
473 | * vcpu_enter_guest requests an immediate exit, | |
474 | * and the guest shouldn't proceed far enough to | |
475 | * need reinjection. | |
476 | */ | |
477 | WARN_ON_ONCE(vcpu->arch.exception.pending); | |
478 | vcpu->arch.exception.injected = true; | |
91e86d22 JM |
479 | if (WARN_ON_ONCE(has_payload)) { |
480 | /* | |
481 | * A reinjected event has already | |
482 | * delivered its payload. | |
483 | */ | |
484 | has_payload = false; | |
485 | payload = 0; | |
486 | } | |
664f8e26 WL |
487 | } else { |
488 | vcpu->arch.exception.pending = true; | |
489 | vcpu->arch.exception.injected = false; | |
490 | } | |
3fd28fce ED |
491 | vcpu->arch.exception.has_error_code = has_error; |
492 | vcpu->arch.exception.nr = nr; | |
493 | vcpu->arch.exception.error_code = error_code; | |
91e86d22 JM |
494 | vcpu->arch.exception.has_payload = has_payload; |
495 | vcpu->arch.exception.payload = payload; | |
da998b46 JM |
496 | /* |
497 | * In guest mode, payload delivery should be deferred, | |
498 | * so that the L1 hypervisor can intercept #PF before | |
f10c729f JM |
499 | * CR2 is modified (or intercept #DB before DR6 is |
500 | * modified under nVMX). However, for ABI | |
501 | * compatibility with KVM_GET_VCPU_EVENTS and | |
502 | * KVM_SET_VCPU_EVENTS, we can't delay payload | |
503 | * delivery unless userspace has enabled this | |
504 | * functionality via the per-VM capability, | |
505 | * KVM_CAP_EXCEPTION_PAYLOAD. | |
da998b46 JM |
506 | */ |
507 | if (!vcpu->kvm->arch.exception_payload_enabled || | |
508 | !is_guest_mode(vcpu)) | |
509 | kvm_deliver_exception_payload(vcpu); | |
3fd28fce ED |
510 | return; |
511 | } | |
512 | ||
513 | /* to check exception */ | |
514 | prev_nr = vcpu->arch.exception.nr; | |
515 | if (prev_nr == DF_VECTOR) { | |
516 | /* triple fault -> shutdown */ | |
a8eeb04a | 517 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
3fd28fce ED |
518 | return; |
519 | } | |
520 | class1 = exception_class(prev_nr); | |
521 | class2 = exception_class(nr); | |
522 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) | |
523 | || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
664f8e26 WL |
524 | /* |
525 | * Generate double fault per SDM Table 5-5. Set | |
526 | * exception.pending = true so that the double fault | |
527 | * can trigger a nested vmexit. | |
528 | */ | |
3fd28fce | 529 | vcpu->arch.exception.pending = true; |
664f8e26 | 530 | vcpu->arch.exception.injected = false; |
3fd28fce ED |
531 | vcpu->arch.exception.has_error_code = true; |
532 | vcpu->arch.exception.nr = DF_VECTOR; | |
533 | vcpu->arch.exception.error_code = 0; | |
c851436a JM |
534 | vcpu->arch.exception.has_payload = false; |
535 | vcpu->arch.exception.payload = 0; | |
3fd28fce ED |
536 | } else |
537 | /* replace previous exception with a new one in a hope | |
538 | that instruction re-execution will regenerate lost | |
539 | exception */ | |
540 | goto queue; | |
541 | } | |
542 | ||
298101da AK |
543 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
544 | { | |
91e86d22 | 545 | kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); |
298101da AK |
546 | } |
547 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
548 | ||
ce7ddec4 JR |
549 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
550 | { | |
91e86d22 | 551 | kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); |
ce7ddec4 JR |
552 | } |
553 | EXPORT_SYMBOL_GPL(kvm_requeue_exception); | |
554 | ||
f10c729f JM |
555 | static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, |
556 | unsigned long payload) | |
557 | { | |
558 | kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); | |
559 | } | |
560 | ||
da998b46 JM |
561 | static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, |
562 | u32 error_code, unsigned long payload) | |
563 | { | |
564 | kvm_multiple_exception(vcpu, nr, true, error_code, | |
565 | true, payload, false); | |
566 | } | |
567 | ||
6affcbed | 568 | int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) |
c3c91fee | 569 | { |
db8fcefa AP |
570 | if (err) |
571 | kvm_inject_gp(vcpu, 0); | |
572 | else | |
6affcbed KH |
573 | return kvm_skip_emulated_instruction(vcpu); |
574 | ||
575 | return 1; | |
db8fcefa AP |
576 | } |
577 | EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); | |
8df25a32 | 578 | |
6389ee94 | 579 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
c3c91fee AK |
580 | { |
581 | ++vcpu->stat.pf_guest; | |
adfe20fb WL |
582 | vcpu->arch.exception.nested_apf = |
583 | is_guest_mode(vcpu) && fault->async_page_fault; | |
da998b46 | 584 | if (vcpu->arch.exception.nested_apf) { |
adfe20fb | 585 | vcpu->arch.apf.nested_apf_token = fault->address; |
da998b46 JM |
586 | kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); |
587 | } else { | |
588 | kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, | |
589 | fault->address); | |
590 | } | |
c3c91fee | 591 | } |
27d6c865 | 592 | EXPORT_SYMBOL_GPL(kvm_inject_page_fault); |
c3c91fee | 593 | |
ef54bcfe | 594 | static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
d4f8cf66 | 595 | { |
6389ee94 AK |
596 | if (mmu_is_nested(vcpu) && !fault->nested_page_fault) |
597 | vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); | |
d4f8cf66 | 598 | else |
44dd3ffa | 599 | vcpu->arch.mmu->inject_page_fault(vcpu, fault); |
ef54bcfe PB |
600 | |
601 | return fault->nested_page_fault; | |
d4f8cf66 JR |
602 | } |
603 | ||
3419ffc8 SY |
604 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
605 | { | |
7460fb4a AK |
606 | atomic_inc(&vcpu->arch.nmi_queued); |
607 | kvm_make_request(KVM_REQ_NMI, vcpu); | |
3419ffc8 SY |
608 | } |
609 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
610 | ||
298101da AK |
611 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
612 | { | |
91e86d22 | 613 | kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); |
298101da AK |
614 | } |
615 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
616 | ||
ce7ddec4 JR |
617 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
618 | { | |
91e86d22 | 619 | kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); |
ce7ddec4 JR |
620 | } |
621 | EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); | |
622 | ||
0a79b009 AK |
623 | /* |
624 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
625 | * a #GP and return false. | |
626 | */ | |
627 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 628 | { |
0a79b009 AK |
629 | if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) |
630 | return true; | |
631 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
632 | return false; | |
298101da | 633 | } |
0a79b009 | 634 | EXPORT_SYMBOL_GPL(kvm_require_cpl); |
298101da | 635 | |
16f8a6f9 NA |
636 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) |
637 | { | |
638 | if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
639 | return true; | |
640 | ||
641 | kvm_queue_exception(vcpu, UD_VECTOR); | |
642 | return false; | |
643 | } | |
644 | EXPORT_SYMBOL_GPL(kvm_require_dr); | |
645 | ||
ec92fe44 JR |
646 | /* |
647 | * This function will be used to read from the physical memory of the currently | |
54bf36aa | 648 | * running guest. The difference to kvm_vcpu_read_guest_page is that this function |
ec92fe44 JR |
649 | * can read from guest physical or from the guest's guest physical memory. |
650 | */ | |
651 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
652 | gfn_t ngfn, void *data, int offset, int len, | |
653 | u32 access) | |
654 | { | |
54987b7a | 655 | struct x86_exception exception; |
ec92fe44 JR |
656 | gfn_t real_gfn; |
657 | gpa_t ngpa; | |
658 | ||
659 | ngpa = gfn_to_gpa(ngfn); | |
54987b7a | 660 | real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); |
ec92fe44 JR |
661 | if (real_gfn == UNMAPPED_GVA) |
662 | return -EFAULT; | |
663 | ||
664 | real_gfn = gpa_to_gfn(real_gfn); | |
665 | ||
54bf36aa | 666 | return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); |
ec92fe44 JR |
667 | } |
668 | EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); | |
669 | ||
69b0049a | 670 | static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, |
3d06b8bf JR |
671 | void *data, int offset, int len, u32 access) |
672 | { | |
673 | return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, | |
674 | data, offset, len, access); | |
675 | } | |
676 | ||
16cfacc8 SC |
677 | static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) |
678 | { | |
679 | return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) | | |
680 | rsvd_bits(1, 2); | |
681 | } | |
682 | ||
a03490ed | 683 | /* |
16cfacc8 | 684 | * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. |
a03490ed | 685 | */ |
ff03a073 | 686 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) |
a03490ed CO |
687 | { |
688 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
689 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
690 | int i; | |
691 | int ret; | |
ff03a073 | 692 | u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; |
a03490ed | 693 | |
ff03a073 JR |
694 | ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, |
695 | offset * sizeof(u64), sizeof(pdpte), | |
696 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
a03490ed CO |
697 | if (ret < 0) { |
698 | ret = 0; | |
699 | goto out; | |
700 | } | |
701 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
812f30b2 | 702 | if ((pdpte[i] & PT_PRESENT_MASK) && |
16cfacc8 | 703 | (pdpte[i] & pdptr_rsvd_bits(vcpu))) { |
a03490ed CO |
704 | ret = 0; |
705 | goto out; | |
706 | } | |
707 | } | |
708 | ret = 1; | |
709 | ||
ff03a073 | 710 | memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); |
6de4f3ad AK |
711 | __set_bit(VCPU_EXREG_PDPTR, |
712 | (unsigned long *)&vcpu->arch.regs_avail); | |
713 | __set_bit(VCPU_EXREG_PDPTR, | |
714 | (unsigned long *)&vcpu->arch.regs_dirty); | |
a03490ed | 715 | out: |
a03490ed CO |
716 | |
717 | return ret; | |
718 | } | |
cc4b6871 | 719 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 720 | |
9ed38ffa | 721 | bool pdptrs_changed(struct kvm_vcpu *vcpu) |
d835dfec | 722 | { |
ff03a073 | 723 | u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; |
d835dfec | 724 | bool changed = true; |
3d06b8bf JR |
725 | int offset; |
726 | gfn_t gfn; | |
d835dfec AK |
727 | int r; |
728 | ||
bf03d4f9 | 729 | if (!is_pae_paging(vcpu)) |
d835dfec AK |
730 | return false; |
731 | ||
6de4f3ad AK |
732 | if (!test_bit(VCPU_EXREG_PDPTR, |
733 | (unsigned long *)&vcpu->arch.regs_avail)) | |
734 | return true; | |
735 | ||
a512177e PB |
736 | gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT; |
737 | offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1); | |
3d06b8bf JR |
738 | r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), |
739 | PFERR_USER_MASK | PFERR_WRITE_MASK); | |
d835dfec AK |
740 | if (r < 0) |
741 | goto out; | |
ff03a073 | 742 | changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; |
d835dfec | 743 | out: |
d835dfec AK |
744 | |
745 | return changed; | |
746 | } | |
9ed38ffa | 747 | EXPORT_SYMBOL_GPL(pdptrs_changed); |
d835dfec | 748 | |
49a9b07e | 749 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 750 | { |
aad82703 | 751 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
d81135a5 | 752 | unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; |
aad82703 | 753 | |
f9a48e6a AK |
754 | cr0 |= X86_CR0_ET; |
755 | ||
ab344828 | 756 | #ifdef CONFIG_X86_64 |
0f12244f GN |
757 | if (cr0 & 0xffffffff00000000UL) |
758 | return 1; | |
ab344828 GN |
759 | #endif |
760 | ||
761 | cr0 &= ~CR0_RESERVED_BITS; | |
a03490ed | 762 | |
0f12244f GN |
763 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) |
764 | return 1; | |
a03490ed | 765 | |
0f12244f GN |
766 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) |
767 | return 1; | |
a03490ed CO |
768 | |
769 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { | |
770 | #ifdef CONFIG_X86_64 | |
f6801dff | 771 | if ((vcpu->arch.efer & EFER_LME)) { |
a03490ed CO |
772 | int cs_db, cs_l; |
773 | ||
0f12244f GN |
774 | if (!is_pae(vcpu)) |
775 | return 1; | |
a03490ed | 776 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
0f12244f GN |
777 | if (cs_l) |
778 | return 1; | |
a03490ed CO |
779 | } else |
780 | #endif | |
ff03a073 | 781 | if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
9f8fe504 | 782 | kvm_read_cr3(vcpu))) |
0f12244f | 783 | return 1; |
a03490ed CO |
784 | } |
785 | ||
ad756a16 MJ |
786 | if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) |
787 | return 1; | |
788 | ||
a03490ed | 789 | kvm_x86_ops->set_cr0(vcpu, cr0); |
a03490ed | 790 | |
d170c419 | 791 | if ((cr0 ^ old_cr0) & X86_CR0_PG) { |
e5f3f027 | 792 | kvm_clear_async_pf_completion_queue(vcpu); |
d170c419 LJ |
793 | kvm_async_pf_hash_reset(vcpu); |
794 | } | |
e5f3f027 | 795 | |
aad82703 SY |
796 | if ((cr0 ^ old_cr0) & update_bits) |
797 | kvm_mmu_reset_context(vcpu); | |
b18d5431 | 798 | |
879ae188 LE |
799 | if (((cr0 ^ old_cr0) & X86_CR0_CD) && |
800 | kvm_arch_has_noncoherent_dma(vcpu->kvm) && | |
801 | !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) | |
b18d5431 XG |
802 | kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); |
803 | ||
0f12244f GN |
804 | return 0; |
805 | } | |
2d3ad1f4 | 806 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 807 | |
2d3ad1f4 | 808 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 809 | { |
49a9b07e | 810 | (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); |
a03490ed | 811 | } |
2d3ad1f4 | 812 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 813 | |
1811d979 | 814 | void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) |
42bdf991 MT |
815 | { |
816 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && | |
817 | !vcpu->guest_xcr0_loaded) { | |
818 | /* kvm_set_xcr() also depends on this */ | |
476b7ada PB |
819 | if (vcpu->arch.xcr0 != host_xcr0) |
820 | xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); | |
42bdf991 MT |
821 | vcpu->guest_xcr0_loaded = 1; |
822 | } | |
823 | } | |
1811d979 | 824 | EXPORT_SYMBOL_GPL(kvm_load_guest_xcr0); |
42bdf991 | 825 | |
1811d979 | 826 | void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) |
42bdf991 MT |
827 | { |
828 | if (vcpu->guest_xcr0_loaded) { | |
829 | if (vcpu->arch.xcr0 != host_xcr0) | |
830 | xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); | |
831 | vcpu->guest_xcr0_loaded = 0; | |
832 | } | |
833 | } | |
1811d979 | 834 | EXPORT_SYMBOL_GPL(kvm_put_guest_xcr0); |
42bdf991 | 835 | |
69b0049a | 836 | static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) |
2acf923e | 837 | { |
56c103ec LJ |
838 | u64 xcr0 = xcr; |
839 | u64 old_xcr0 = vcpu->arch.xcr0; | |
46c34cb0 | 840 | u64 valid_bits; |
2acf923e DC |
841 | |
842 | /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ | |
843 | if (index != XCR_XFEATURE_ENABLED_MASK) | |
844 | return 1; | |
d91cab78 | 845 | if (!(xcr0 & XFEATURE_MASK_FP)) |
2acf923e | 846 | return 1; |
d91cab78 | 847 | if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) |
2acf923e | 848 | return 1; |
46c34cb0 PB |
849 | |
850 | /* | |
851 | * Do not allow the guest to set bits that we do not support | |
852 | * saving. However, xcr0 bit 0 is always set, even if the | |
853 | * emulated CPU does not support XSAVE (see fx_init). | |
854 | */ | |
d91cab78 | 855 | valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; |
46c34cb0 | 856 | if (xcr0 & ~valid_bits) |
2acf923e | 857 | return 1; |
46c34cb0 | 858 | |
d91cab78 DH |
859 | if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != |
860 | (!(xcr0 & XFEATURE_MASK_BNDCSR))) | |
390bd528 LJ |
861 | return 1; |
862 | ||
d91cab78 DH |
863 | if (xcr0 & XFEATURE_MASK_AVX512) { |
864 | if (!(xcr0 & XFEATURE_MASK_YMM)) | |
612263b3 | 865 | return 1; |
d91cab78 | 866 | if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) |
612263b3 CP |
867 | return 1; |
868 | } | |
2acf923e | 869 | vcpu->arch.xcr0 = xcr0; |
56c103ec | 870 | |
d91cab78 | 871 | if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) |
56c103ec | 872 | kvm_update_cpuid(vcpu); |
2acf923e DC |
873 | return 0; |
874 | } | |
875 | ||
876 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) | |
877 | { | |
764bcbc5 Z |
878 | if (kvm_x86_ops->get_cpl(vcpu) != 0 || |
879 | __kvm_set_xcr(vcpu, index, xcr)) { | |
2acf923e DC |
880 | kvm_inject_gp(vcpu, 0); |
881 | return 1; | |
882 | } | |
883 | return 0; | |
884 | } | |
885 | EXPORT_SYMBOL_GPL(kvm_set_xcr); | |
886 | ||
a83b29c6 | 887 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 888 | { |
fc78f519 | 889 | unsigned long old_cr4 = kvm_read_cr4(vcpu); |
0be0226f | 890 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | |
b9baba86 | 891 | X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE; |
0be0226f | 892 | |
0f12244f GN |
893 | if (cr4 & CR4_RESERVED_BITS) |
894 | return 1; | |
a03490ed | 895 | |
d6321d49 | 896 | if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE)) |
2acf923e DC |
897 | return 1; |
898 | ||
d6321d49 | 899 | if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP)) |
2acf923e DC |
900 | return 1; |
901 | ||
d6321d49 | 902 | if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP)) |
c68b734f YW |
903 | return 1; |
904 | ||
d6321d49 | 905 | if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE)) |
97ec8c06 FW |
906 | return 1; |
907 | ||
d6321d49 | 908 | if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE)) |
74dc2b4f YW |
909 | return 1; |
910 | ||
fd8cb433 | 911 | if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57)) |
b9baba86 HH |
912 | return 1; |
913 | ||
ae3e61e1 PB |
914 | if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP)) |
915 | return 1; | |
916 | ||
a03490ed | 917 | if (is_long_mode(vcpu)) { |
0f12244f GN |
918 | if (!(cr4 & X86_CR4_PAE)) |
919 | return 1; | |
a2edf57f AK |
920 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
921 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
9f8fe504 AK |
922 | && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
923 | kvm_read_cr3(vcpu))) | |
0f12244f GN |
924 | return 1; |
925 | ||
ad756a16 | 926 | if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { |
d6321d49 | 927 | if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) |
ad756a16 MJ |
928 | return 1; |
929 | ||
930 | /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ | |
931 | if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) | |
932 | return 1; | |
933 | } | |
934 | ||
5e1746d6 | 935 | if (kvm_x86_ops->set_cr4(vcpu, cr4)) |
0f12244f | 936 | return 1; |
a03490ed | 937 | |
ad756a16 MJ |
938 | if (((cr4 ^ old_cr4) & pdptr_bits) || |
939 | (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) | |
aad82703 | 940 | kvm_mmu_reset_context(vcpu); |
0f12244f | 941 | |
b9baba86 | 942 | if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE)) |
00b27a3e | 943 | kvm_update_cpuid(vcpu); |
2acf923e | 944 | |
0f12244f GN |
945 | return 0; |
946 | } | |
2d3ad1f4 | 947 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 948 | |
2390218b | 949 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 950 | { |
ade61e28 | 951 | bool skip_tlb_flush = false; |
ac146235 | 952 | #ifdef CONFIG_X86_64 |
c19986fe JS |
953 | bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); |
954 | ||
ade61e28 | 955 | if (pcid_enabled) { |
208320ba JS |
956 | skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; |
957 | cr3 &= ~X86_CR3_PCID_NOFLUSH; | |
ade61e28 | 958 | } |
ac146235 | 959 | #endif |
9d88fca7 | 960 | |
9f8fe504 | 961 | if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { |
956bf353 JS |
962 | if (!skip_tlb_flush) { |
963 | kvm_mmu_sync_roots(vcpu); | |
ade61e28 | 964 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
956bf353 | 965 | } |
0f12244f | 966 | return 0; |
d835dfec AK |
967 | } |
968 | ||
d1cd3ce9 | 969 | if (is_long_mode(vcpu) && |
a780a3ea | 970 | (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63))) |
d1cd3ce9 | 971 | return 1; |
bf03d4f9 PB |
972 | else if (is_pae_paging(vcpu) && |
973 | !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) | |
346874c9 | 974 | return 1; |
a03490ed | 975 | |
ade61e28 | 976 | kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush); |
0f12244f | 977 | vcpu->arch.cr3 = cr3; |
aff48baa | 978 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); |
7c390d35 | 979 | |
0f12244f GN |
980 | return 0; |
981 | } | |
2d3ad1f4 | 982 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 983 | |
eea1cff9 | 984 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed | 985 | { |
0f12244f GN |
986 | if (cr8 & CR8_RESERVED_BITS) |
987 | return 1; | |
35754c98 | 988 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
989 | kvm_lapic_set_tpr(vcpu, cr8); |
990 | else | |
ad312c7c | 991 | vcpu->arch.cr8 = cr8; |
0f12244f GN |
992 | return 0; |
993 | } | |
2d3ad1f4 | 994 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 995 | |
2d3ad1f4 | 996 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed | 997 | { |
35754c98 | 998 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
999 | return kvm_lapic_get_cr8(vcpu); |
1000 | else | |
ad312c7c | 1001 | return vcpu->arch.cr8; |
a03490ed | 1002 | } |
2d3ad1f4 | 1003 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 1004 | |
ae561ede NA |
1005 | static void kvm_update_dr0123(struct kvm_vcpu *vcpu) |
1006 | { | |
1007 | int i; | |
1008 | ||
1009 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
1010 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
1011 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
1012 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; | |
1013 | } | |
1014 | } | |
1015 | ||
73aaf249 JK |
1016 | static void kvm_update_dr6(struct kvm_vcpu *vcpu) |
1017 | { | |
1018 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
1019 | kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); | |
1020 | } | |
1021 | ||
c8639010 JK |
1022 | static void kvm_update_dr7(struct kvm_vcpu *vcpu) |
1023 | { | |
1024 | unsigned long dr7; | |
1025 | ||
1026 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
1027 | dr7 = vcpu->arch.guest_debug_dr7; | |
1028 | else | |
1029 | dr7 = vcpu->arch.dr7; | |
1030 | kvm_x86_ops->set_dr7(vcpu, dr7); | |
360b948d PB |
1031 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; |
1032 | if (dr7 & DR7_BP_EN_MASK) | |
1033 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; | |
c8639010 JK |
1034 | } |
1035 | ||
6f43ed01 NA |
1036 | static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) |
1037 | { | |
1038 | u64 fixed = DR6_FIXED_1; | |
1039 | ||
d6321d49 | 1040 | if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) |
6f43ed01 NA |
1041 | fixed |= DR6_RTM; |
1042 | return fixed; | |
1043 | } | |
1044 | ||
338dbc97 | 1045 | static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) |
020df079 GN |
1046 | { |
1047 | switch (dr) { | |
1048 | case 0 ... 3: | |
1049 | vcpu->arch.db[dr] = val; | |
1050 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
1051 | vcpu->arch.eff_db[dr] = val; | |
1052 | break; | |
1053 | case 4: | |
020df079 GN |
1054 | /* fall through */ |
1055 | case 6: | |
338dbc97 GN |
1056 | if (val & 0xffffffff00000000ULL) |
1057 | return -1; /* #GP */ | |
6f43ed01 | 1058 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); |
73aaf249 | 1059 | kvm_update_dr6(vcpu); |
020df079 GN |
1060 | break; |
1061 | case 5: | |
020df079 GN |
1062 | /* fall through */ |
1063 | default: /* 7 */ | |
338dbc97 GN |
1064 | if (val & 0xffffffff00000000ULL) |
1065 | return -1; /* #GP */ | |
020df079 | 1066 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; |
c8639010 | 1067 | kvm_update_dr7(vcpu); |
020df079 GN |
1068 | break; |
1069 | } | |
1070 | ||
1071 | return 0; | |
1072 | } | |
338dbc97 GN |
1073 | |
1074 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) | |
1075 | { | |
16f8a6f9 | 1076 | if (__kvm_set_dr(vcpu, dr, val)) { |
338dbc97 | 1077 | kvm_inject_gp(vcpu, 0); |
16f8a6f9 NA |
1078 | return 1; |
1079 | } | |
1080 | return 0; | |
338dbc97 | 1081 | } |
020df079 GN |
1082 | EXPORT_SYMBOL_GPL(kvm_set_dr); |
1083 | ||
16f8a6f9 | 1084 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) |
020df079 GN |
1085 | { |
1086 | switch (dr) { | |
1087 | case 0 ... 3: | |
1088 | *val = vcpu->arch.db[dr]; | |
1089 | break; | |
1090 | case 4: | |
020df079 GN |
1091 | /* fall through */ |
1092 | case 6: | |
73aaf249 JK |
1093 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) |
1094 | *val = vcpu->arch.dr6; | |
1095 | else | |
1096 | *val = kvm_x86_ops->get_dr6(vcpu); | |
020df079 GN |
1097 | break; |
1098 | case 5: | |
020df079 GN |
1099 | /* fall through */ |
1100 | default: /* 7 */ | |
1101 | *val = vcpu->arch.dr7; | |
1102 | break; | |
1103 | } | |
338dbc97 GN |
1104 | return 0; |
1105 | } | |
020df079 GN |
1106 | EXPORT_SYMBOL_GPL(kvm_get_dr); |
1107 | ||
022cd0e8 AK |
1108 | bool kvm_rdpmc(struct kvm_vcpu *vcpu) |
1109 | { | |
de3cd117 | 1110 | u32 ecx = kvm_rcx_read(vcpu); |
022cd0e8 AK |
1111 | u64 data; |
1112 | int err; | |
1113 | ||
c6702c9d | 1114 | err = kvm_pmu_rdpmc(vcpu, ecx, &data); |
022cd0e8 AK |
1115 | if (err) |
1116 | return err; | |
de3cd117 SC |
1117 | kvm_rax_write(vcpu, (u32)data); |
1118 | kvm_rdx_write(vcpu, data >> 32); | |
022cd0e8 AK |
1119 | return err; |
1120 | } | |
1121 | EXPORT_SYMBOL_GPL(kvm_rdpmc); | |
1122 | ||
043405e1 CO |
1123 | /* |
1124 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
1125 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
1126 | * | |
1127 | * This list is modified at module load time to reflect the | |
e3267cbb | 1128 | * capabilities of the host cpu. This capabilities test skips MSRs that are |
62ef68bb PB |
1129 | * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs |
1130 | * may depend on host virtualization features rather than host cpu features. | |
043405e1 | 1131 | */ |
e3267cbb | 1132 | |
043405e1 CO |
1133 | static u32 msrs_to_save[] = { |
1134 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
8c06585d | 1135 | MSR_STAR, |
043405e1 CO |
1136 | #ifdef CONFIG_X86_64 |
1137 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
1138 | #endif | |
b3897a49 | 1139 | MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, |
9dbe6cf9 | 1140 | MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, |
2bdb76c0 | 1141 | MSR_IA32_SPEC_CTRL, |
bf8c55d8 CP |
1142 | MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, |
1143 | MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, | |
1144 | MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, | |
1145 | MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, | |
1146 | MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, | |
1147 | MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, | |
e2ada66e JM |
1148 | MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, |
1149 | MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3, | |
1150 | MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, | |
1151 | MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, | |
1152 | MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, | |
1153 | MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, | |
1154 | MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, | |
1155 | MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, | |
1156 | MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9, | |
1157 | MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11, | |
1158 | MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13, | |
1159 | MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15, | |
1160 | MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17, | |
1161 | MSR_ARCH_PERFMON_PERFCTR0 + 18, MSR_ARCH_PERFMON_PERFCTR0 + 19, | |
1162 | MSR_ARCH_PERFMON_PERFCTR0 + 20, MSR_ARCH_PERFMON_PERFCTR0 + 21, | |
1163 | MSR_ARCH_PERFMON_PERFCTR0 + 22, MSR_ARCH_PERFMON_PERFCTR0 + 23, | |
1164 | MSR_ARCH_PERFMON_PERFCTR0 + 24, MSR_ARCH_PERFMON_PERFCTR0 + 25, | |
1165 | MSR_ARCH_PERFMON_PERFCTR0 + 26, MSR_ARCH_PERFMON_PERFCTR0 + 27, | |
1166 | MSR_ARCH_PERFMON_PERFCTR0 + 28, MSR_ARCH_PERFMON_PERFCTR0 + 29, | |
1167 | MSR_ARCH_PERFMON_PERFCTR0 + 30, MSR_ARCH_PERFMON_PERFCTR0 + 31, | |
1168 | MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, | |
1169 | MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, | |
1170 | MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, | |
1171 | MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, | |
1172 | MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9, | |
1173 | MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11, | |
1174 | MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13, | |
1175 | MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15, | |
1176 | MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17, | |
1177 | MSR_ARCH_PERFMON_EVENTSEL0 + 18, MSR_ARCH_PERFMON_EVENTSEL0 + 19, | |
1178 | MSR_ARCH_PERFMON_EVENTSEL0 + 20, MSR_ARCH_PERFMON_EVENTSEL0 + 21, | |
1179 | MSR_ARCH_PERFMON_EVENTSEL0 + 22, MSR_ARCH_PERFMON_EVENTSEL0 + 23, | |
1180 | MSR_ARCH_PERFMON_EVENTSEL0 + 24, MSR_ARCH_PERFMON_EVENTSEL0 + 25, | |
1181 | MSR_ARCH_PERFMON_EVENTSEL0 + 26, MSR_ARCH_PERFMON_EVENTSEL0 + 27, | |
1182 | MSR_ARCH_PERFMON_EVENTSEL0 + 28, MSR_ARCH_PERFMON_EVENTSEL0 + 29, | |
1183 | MSR_ARCH_PERFMON_EVENTSEL0 + 30, MSR_ARCH_PERFMON_EVENTSEL0 + 31, | |
043405e1 CO |
1184 | }; |
1185 | ||
1186 | static unsigned num_msrs_to_save; | |
1187 | ||
62ef68bb PB |
1188 | static u32 emulated_msrs[] = { |
1189 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, | |
1190 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, | |
1191 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, | |
1192 | HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, | |
72c139ba | 1193 | HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, |
e7d9513b AS |
1194 | HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, |
1195 | HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, | |
e516cebb | 1196 | HV_X64_MSR_RESET, |
11c4b1ca | 1197 | HV_X64_MSR_VP_INDEX, |
9eec50b8 | 1198 | HV_X64_MSR_VP_RUNTIME, |
5c919412 | 1199 | HV_X64_MSR_SCONTROL, |
1f4b34f8 | 1200 | HV_X64_MSR_STIMER0_CONFIG, |
d4abc577 | 1201 | HV_X64_MSR_VP_ASSIST_PAGE, |
a2e164e7 VK |
1202 | HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, |
1203 | HV_X64_MSR_TSC_EMULATION_STATUS, | |
1204 | ||
1205 | MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, | |
62ef68bb PB |
1206 | MSR_KVM_PV_EOI_EN, |
1207 | ||
ba904635 | 1208 | MSR_IA32_TSC_ADJUST, |
a3e06bbe | 1209 | MSR_IA32_TSCDEADLINE, |
2bdb76c0 | 1210 | MSR_IA32_ARCH_CAPABILITIES, |
043405e1 | 1211 | MSR_IA32_MISC_ENABLE, |
908e75f3 AK |
1212 | MSR_IA32_MCG_STATUS, |
1213 | MSR_IA32_MCG_CTL, | |
c45dcc71 | 1214 | MSR_IA32_MCG_EXT_CTL, |
64d60670 | 1215 | MSR_IA32_SMBASE, |
52797bf9 | 1216 | MSR_SMI_COUNT, |
db2336a8 KH |
1217 | MSR_PLATFORM_INFO, |
1218 | MSR_MISC_FEATURES_ENABLES, | |
bc226f07 | 1219 | MSR_AMD64_VIRT_SPEC_CTRL, |
6c6a2ab9 | 1220 | MSR_IA32_POWER_CTL, |
191c8137 | 1221 | |
95c5c7c7 PB |
1222 | /* |
1223 | * The following list leaves out MSRs whose values are determined | |
1224 | * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs. | |
1225 | * We always support the "true" VMX control MSRs, even if the host | |
1226 | * processor does not, so I am putting these registers here rather | |
1227 | * than in msrs_to_save. | |
1228 | */ | |
1229 | MSR_IA32_VMX_BASIC, | |
1230 | MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
1231 | MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
1232 | MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
1233 | MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
1234 | MSR_IA32_VMX_MISC, | |
1235 | MSR_IA32_VMX_CR0_FIXED0, | |
1236 | MSR_IA32_VMX_CR4_FIXED0, | |
1237 | MSR_IA32_VMX_VMCS_ENUM, | |
1238 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
1239 | MSR_IA32_VMX_EPT_VPID_CAP, | |
1240 | MSR_IA32_VMX_VMFUNC, | |
1241 | ||
191c8137 | 1242 | MSR_K7_HWCR, |
2d5ba19b | 1243 | MSR_KVM_POLL_CONTROL, |
043405e1 CO |
1244 | }; |
1245 | ||
62ef68bb PB |
1246 | static unsigned num_emulated_msrs; |
1247 | ||
801e459a TL |
1248 | /* |
1249 | * List of msr numbers which are used to expose MSR-based features that | |
1250 | * can be used by a hypervisor to validate requested CPU features. | |
1251 | */ | |
1252 | static u32 msr_based_features[] = { | |
1389309c PB |
1253 | MSR_IA32_VMX_BASIC, |
1254 | MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
1255 | MSR_IA32_VMX_PINBASED_CTLS, | |
1256 | MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
1257 | MSR_IA32_VMX_PROCBASED_CTLS, | |
1258 | MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
1259 | MSR_IA32_VMX_EXIT_CTLS, | |
1260 | MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
1261 | MSR_IA32_VMX_ENTRY_CTLS, | |
1262 | MSR_IA32_VMX_MISC, | |
1263 | MSR_IA32_VMX_CR0_FIXED0, | |
1264 | MSR_IA32_VMX_CR0_FIXED1, | |
1265 | MSR_IA32_VMX_CR4_FIXED0, | |
1266 | MSR_IA32_VMX_CR4_FIXED1, | |
1267 | MSR_IA32_VMX_VMCS_ENUM, | |
1268 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
1269 | MSR_IA32_VMX_EPT_VPID_CAP, | |
1270 | MSR_IA32_VMX_VMFUNC, | |
1271 | ||
d1d93fa9 | 1272 | MSR_F10H_DECFG, |
518e7b94 | 1273 | MSR_IA32_UCODE_REV, |
cd283252 | 1274 | MSR_IA32_ARCH_CAPABILITIES, |
801e459a TL |
1275 | }; |
1276 | ||
1277 | static unsigned int num_msr_based_features; | |
1278 | ||
4d22c17c | 1279 | static u64 kvm_get_arch_capabilities(void) |
5b76a3cf | 1280 | { |
4d22c17c | 1281 | u64 data = 0; |
5b76a3cf | 1282 | |
4d22c17c XL |
1283 | if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) |
1284 | rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data); | |
5b76a3cf PB |
1285 | |
1286 | /* | |
1287 | * If we're doing cache flushes (either "always" or "cond") | |
1288 | * we will do one whenever the guest does a vmlaunch/vmresume. | |
1289 | * If an outer hypervisor is doing the cache flush for us | |
1290 | * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that | |
1291 | * capability to the guest too, and if EPT is disabled we're not | |
1292 | * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will | |
1293 | * require a nested hypervisor to do a flush of its own. | |
1294 | */ | |
1295 | if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) | |
1296 | data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; | |
1297 | ||
0c54914d PB |
1298 | if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) |
1299 | data |= ARCH_CAP_RDCL_NO; | |
1300 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
1301 | data |= ARCH_CAP_SSB_NO; | |
1302 | if (!boot_cpu_has_bug(X86_BUG_MDS)) | |
1303 | data |= ARCH_CAP_MDS_NO; | |
1304 | ||
5b76a3cf PB |
1305 | return data; |
1306 | } | |
5b76a3cf | 1307 | |
66421c1e WL |
1308 | static int kvm_get_msr_feature(struct kvm_msr_entry *msr) |
1309 | { | |
1310 | switch (msr->index) { | |
cd283252 | 1311 | case MSR_IA32_ARCH_CAPABILITIES: |
5b76a3cf PB |
1312 | msr->data = kvm_get_arch_capabilities(); |
1313 | break; | |
1314 | case MSR_IA32_UCODE_REV: | |
cd283252 | 1315 | rdmsrl_safe(msr->index, &msr->data); |
518e7b94 | 1316 | break; |
66421c1e WL |
1317 | default: |
1318 | if (kvm_x86_ops->get_msr_feature(msr)) | |
1319 | return 1; | |
1320 | } | |
1321 | return 0; | |
1322 | } | |
1323 | ||
801e459a TL |
1324 | static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) |
1325 | { | |
1326 | struct kvm_msr_entry msr; | |
66421c1e | 1327 | int r; |
801e459a TL |
1328 | |
1329 | msr.index = index; | |
66421c1e WL |
1330 | r = kvm_get_msr_feature(&msr); |
1331 | if (r) | |
1332 | return r; | |
801e459a TL |
1333 | |
1334 | *data = msr.data; | |
1335 | ||
1336 | return 0; | |
1337 | } | |
1338 | ||
11988499 | 1339 | static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) |
15c4a640 | 1340 | { |
1b4d56b8 | 1341 | if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) |
11988499 | 1342 | return false; |
1b2fd70c | 1343 | |
1b4d56b8 | 1344 | if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) |
11988499 | 1345 | return false; |
d8017474 | 1346 | |
0a629563 SC |
1347 | if (efer & (EFER_LME | EFER_LMA) && |
1348 | !guest_cpuid_has(vcpu, X86_FEATURE_LM)) | |
1349 | return false; | |
1350 | ||
1351 | if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) | |
1352 | return false; | |
d8017474 | 1353 | |
384bb783 | 1354 | return true; |
11988499 SC |
1355 | |
1356 | } | |
1357 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) | |
1358 | { | |
1359 | if (efer & efer_reserved_bits) | |
1360 | return false; | |
1361 | ||
1362 | return __kvm_valid_efer(vcpu, efer); | |
384bb783 JK |
1363 | } |
1364 | EXPORT_SYMBOL_GPL(kvm_valid_efer); | |
1365 | ||
11988499 | 1366 | static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
384bb783 JK |
1367 | { |
1368 | u64 old_efer = vcpu->arch.efer; | |
11988499 | 1369 | u64 efer = msr_info->data; |
384bb783 | 1370 | |
11988499 | 1371 | if (efer & efer_reserved_bits) |
66f61c92 | 1372 | return 1; |
384bb783 | 1373 | |
11988499 SC |
1374 | if (!msr_info->host_initiated) { |
1375 | if (!__kvm_valid_efer(vcpu, efer)) | |
1376 | return 1; | |
1377 | ||
1378 | if (is_paging(vcpu) && | |
1379 | (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) | |
1380 | return 1; | |
1381 | } | |
384bb783 | 1382 | |
15c4a640 | 1383 | efer &= ~EFER_LMA; |
f6801dff | 1384 | efer |= vcpu->arch.efer & EFER_LMA; |
15c4a640 | 1385 | |
a3d204e2 SY |
1386 | kvm_x86_ops->set_efer(vcpu, efer); |
1387 | ||
aad82703 SY |
1388 | /* Update reserved bits */ |
1389 | if ((efer ^ old_efer) & EFER_NX) | |
1390 | kvm_mmu_reset_context(vcpu); | |
1391 | ||
b69e8cae | 1392 | return 0; |
15c4a640 CO |
1393 | } |
1394 | ||
f2b4b7dd JR |
1395 | void kvm_enable_efer_bits(u64 mask) |
1396 | { | |
1397 | efer_reserved_bits &= ~mask; | |
1398 | } | |
1399 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
1400 | ||
15c4a640 | 1401 | /* |
f20935d8 SC |
1402 | * Write @data into the MSR specified by @index. Select MSR specific fault |
1403 | * checks are bypassed if @host_initiated is %true. | |
15c4a640 CO |
1404 | * Returns 0 on success, non-0 otherwise. |
1405 | * Assumes vcpu_load() was already called. | |
1406 | */ | |
f20935d8 SC |
1407 | static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, |
1408 | bool host_initiated) | |
15c4a640 | 1409 | { |
f20935d8 SC |
1410 | struct msr_data msr; |
1411 | ||
1412 | switch (index) { | |
854e8bb1 NA |
1413 | case MSR_FS_BASE: |
1414 | case MSR_GS_BASE: | |
1415 | case MSR_KERNEL_GS_BASE: | |
1416 | case MSR_CSTAR: | |
1417 | case MSR_LSTAR: | |
f20935d8 | 1418 | if (is_noncanonical_address(data, vcpu)) |
854e8bb1 NA |
1419 | return 1; |
1420 | break; | |
1421 | case MSR_IA32_SYSENTER_EIP: | |
1422 | case MSR_IA32_SYSENTER_ESP: | |
1423 | /* | |
1424 | * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if | |
1425 | * non-canonical address is written on Intel but not on | |
1426 | * AMD (which ignores the top 32-bits, because it does | |
1427 | * not implement 64-bit SYSENTER). | |
1428 | * | |
1429 | * 64-bit code should hence be able to write a non-canonical | |
1430 | * value on AMD. Making the address canonical ensures that | |
1431 | * vmentry does not fail on Intel after writing a non-canonical | |
1432 | * value, and that something deterministic happens if the guest | |
1433 | * invokes 64-bit SYSENTER. | |
1434 | */ | |
f20935d8 | 1435 | data = get_canonical(data, vcpu_virt_addr_bits(vcpu)); |
854e8bb1 | 1436 | } |
f20935d8 SC |
1437 | |
1438 | msr.data = data; | |
1439 | msr.index = index; | |
1440 | msr.host_initiated = host_initiated; | |
1441 | ||
1442 | return kvm_x86_ops->set_msr(vcpu, &msr); | |
15c4a640 CO |
1443 | } |
1444 | ||
313a3dc7 | 1445 | /* |
f20935d8 SC |
1446 | * Read the MSR specified by @index into @data. Select MSR specific fault |
1447 | * checks are bypassed if @host_initiated is %true. | |
1448 | * Returns 0 on success, non-0 otherwise. | |
1449 | * Assumes vcpu_load() was already called. | |
313a3dc7 | 1450 | */ |
f20935d8 SC |
1451 | static int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, |
1452 | bool host_initiated) | |
609e36d3 PB |
1453 | { |
1454 | struct msr_data msr; | |
f20935d8 | 1455 | int ret; |
609e36d3 PB |
1456 | |
1457 | msr.index = index; | |
f20935d8 | 1458 | msr.host_initiated = host_initiated; |
609e36d3 | 1459 | |
f20935d8 SC |
1460 | ret = kvm_x86_ops->get_msr(vcpu, &msr); |
1461 | if (!ret) | |
1462 | *data = msr.data; | |
1463 | return ret; | |
609e36d3 PB |
1464 | } |
1465 | ||
f20935d8 | 1466 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) |
313a3dc7 | 1467 | { |
f20935d8 SC |
1468 | return __kvm_get_msr(vcpu, index, data, false); |
1469 | } | |
1470 | EXPORT_SYMBOL_GPL(kvm_get_msr); | |
8fe8ab46 | 1471 | |
f20935d8 SC |
1472 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) |
1473 | { | |
1474 | return __kvm_set_msr(vcpu, index, data, false); | |
1475 | } | |
1476 | EXPORT_SYMBOL_GPL(kvm_set_msr); | |
1477 | ||
1edce0a9 SC |
1478 | int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) |
1479 | { | |
1480 | u32 ecx = kvm_rcx_read(vcpu); | |
1481 | u64 data; | |
1482 | ||
1483 | if (kvm_get_msr(vcpu, ecx, &data)) { | |
1484 | trace_kvm_msr_read_ex(ecx); | |
1485 | kvm_inject_gp(vcpu, 0); | |
1486 | return 1; | |
1487 | } | |
1488 | ||
1489 | trace_kvm_msr_read(ecx, data); | |
1490 | ||
1491 | kvm_rax_write(vcpu, data & -1u); | |
1492 | kvm_rdx_write(vcpu, (data >> 32) & -1u); | |
1493 | return kvm_skip_emulated_instruction(vcpu); | |
1494 | } | |
1495 | EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); | |
1496 | ||
1497 | int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) | |
1498 | { | |
1499 | u32 ecx = kvm_rcx_read(vcpu); | |
1500 | u64 data = kvm_read_edx_eax(vcpu); | |
1501 | ||
1502 | if (kvm_set_msr(vcpu, ecx, data)) { | |
1503 | trace_kvm_msr_write_ex(ecx, data); | |
1504 | kvm_inject_gp(vcpu, 0); | |
1505 | return 1; | |
1506 | } | |
1507 | ||
1508 | trace_kvm_msr_write(ecx, data); | |
1509 | return kvm_skip_emulated_instruction(vcpu); | |
1510 | } | |
1511 | EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); | |
1512 | ||
f20935d8 SC |
1513 | /* |
1514 | * Adapt set_msr() to msr_io()'s calling convention | |
1515 | */ | |
1516 | static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
1517 | { | |
1518 | return __kvm_get_msr(vcpu, index, data, true); | |
1519 | } | |
1520 | ||
1521 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
1522 | { | |
1523 | return __kvm_set_msr(vcpu, index, *data, true); | |
313a3dc7 CO |
1524 | } |
1525 | ||
16e8d74d MT |
1526 | #ifdef CONFIG_X86_64 |
1527 | struct pvclock_gtod_data { | |
1528 | seqcount_t seq; | |
1529 | ||
1530 | struct { /* extract of a clocksource struct */ | |
1531 | int vclock_mode; | |
a5a1d1c2 TG |
1532 | u64 cycle_last; |
1533 | u64 mask; | |
16e8d74d MT |
1534 | u32 mult; |
1535 | u32 shift; | |
1536 | } clock; | |
1537 | ||
cbcf2dd3 TG |
1538 | u64 boot_ns; |
1539 | u64 nsec_base; | |
55dd00a7 | 1540 | u64 wall_time_sec; |
16e8d74d MT |
1541 | }; |
1542 | ||
1543 | static struct pvclock_gtod_data pvclock_gtod_data; | |
1544 | ||
1545 | static void update_pvclock_gtod(struct timekeeper *tk) | |
1546 | { | |
1547 | struct pvclock_gtod_data *vdata = &pvclock_gtod_data; | |
cbcf2dd3 TG |
1548 | u64 boot_ns; |
1549 | ||
876e7881 | 1550 | boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot)); |
16e8d74d MT |
1551 | |
1552 | write_seqcount_begin(&vdata->seq); | |
1553 | ||
1554 | /* copy pvclock gtod data */ | |
876e7881 PZ |
1555 | vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode; |
1556 | vdata->clock.cycle_last = tk->tkr_mono.cycle_last; | |
1557 | vdata->clock.mask = tk->tkr_mono.mask; | |
1558 | vdata->clock.mult = tk->tkr_mono.mult; | |
1559 | vdata->clock.shift = tk->tkr_mono.shift; | |
16e8d74d | 1560 | |
cbcf2dd3 | 1561 | vdata->boot_ns = boot_ns; |
876e7881 | 1562 | vdata->nsec_base = tk->tkr_mono.xtime_nsec; |
16e8d74d | 1563 | |
55dd00a7 MT |
1564 | vdata->wall_time_sec = tk->xtime_sec; |
1565 | ||
16e8d74d MT |
1566 | write_seqcount_end(&vdata->seq); |
1567 | } | |
1568 | #endif | |
1569 | ||
bab5bb39 NK |
1570 | void kvm_set_pending_timer(struct kvm_vcpu *vcpu) |
1571 | { | |
bab5bb39 | 1572 | kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); |
4d151bf3 | 1573 | kvm_vcpu_kick(vcpu); |
bab5bb39 | 1574 | } |
16e8d74d | 1575 | |
18068523 GOC |
1576 | static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) |
1577 | { | |
9ed3c444 AK |
1578 | int version; |
1579 | int r; | |
50d0a0f9 | 1580 | struct pvclock_wall_clock wc; |
87aeb54f | 1581 | struct timespec64 boot; |
18068523 GOC |
1582 | |
1583 | if (!wall_clock) | |
1584 | return; | |
1585 | ||
9ed3c444 AK |
1586 | r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); |
1587 | if (r) | |
1588 | return; | |
1589 | ||
1590 | if (version & 1) | |
1591 | ++version; /* first time write, random junk */ | |
1592 | ||
1593 | ++version; | |
18068523 | 1594 | |
1dab1345 NK |
1595 | if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) |
1596 | return; | |
18068523 | 1597 | |
50d0a0f9 GH |
1598 | /* |
1599 | * The guest calculates current wall clock time by adding | |
34c238a1 | 1600 | * system time (updated by kvm_guest_time_update below) to the |
50d0a0f9 GH |
1601 | * wall clock specified here. guest system time equals host |
1602 | * system time for us, thus we must fill in host boot time here. | |
1603 | */ | |
87aeb54f | 1604 | getboottime64(&boot); |
50d0a0f9 | 1605 | |
4b648665 | 1606 | if (kvm->arch.kvmclock_offset) { |
87aeb54f AB |
1607 | struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset); |
1608 | boot = timespec64_sub(boot, ts); | |
4b648665 | 1609 | } |
87aeb54f | 1610 | wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */ |
50d0a0f9 GH |
1611 | wc.nsec = boot.tv_nsec; |
1612 | wc.version = version; | |
18068523 GOC |
1613 | |
1614 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
1615 | ||
1616 | version++; | |
1617 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
1618 | } |
1619 | ||
50d0a0f9 GH |
1620 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
1621 | { | |
b51012de PB |
1622 | do_shl32_div32(dividend, divisor); |
1623 | return dividend; | |
50d0a0f9 GH |
1624 | } |
1625 | ||
3ae13faa | 1626 | static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, |
5f4e3f88 | 1627 | s8 *pshift, u32 *pmultiplier) |
50d0a0f9 | 1628 | { |
5f4e3f88 | 1629 | uint64_t scaled64; |
50d0a0f9 GH |
1630 | int32_t shift = 0; |
1631 | uint64_t tps64; | |
1632 | uint32_t tps32; | |
1633 | ||
3ae13faa PB |
1634 | tps64 = base_hz; |
1635 | scaled64 = scaled_hz; | |
50933623 | 1636 | while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { |
50d0a0f9 GH |
1637 | tps64 >>= 1; |
1638 | shift--; | |
1639 | } | |
1640 | ||
1641 | tps32 = (uint32_t)tps64; | |
50933623 JK |
1642 | while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { |
1643 | if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) | |
5f4e3f88 ZA |
1644 | scaled64 >>= 1; |
1645 | else | |
1646 | tps32 <<= 1; | |
50d0a0f9 GH |
1647 | shift++; |
1648 | } | |
1649 | ||
5f4e3f88 ZA |
1650 | *pshift = shift; |
1651 | *pmultiplier = div_frac(scaled64, tps32); | |
50d0a0f9 GH |
1652 | } |
1653 | ||
d828199e | 1654 | #ifdef CONFIG_X86_64 |
16e8d74d | 1655 | static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); |
d828199e | 1656 | #endif |
16e8d74d | 1657 | |
c8076604 | 1658 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
69b0049a | 1659 | static unsigned long max_tsc_khz; |
c8076604 | 1660 | |
cc578287 | 1661 | static u32 adjust_tsc_khz(u32 khz, s32 ppm) |
1e993611 | 1662 | { |
cc578287 ZA |
1663 | u64 v = (u64)khz * (1000000 + ppm); |
1664 | do_div(v, 1000000); | |
1665 | return v; | |
1e993611 JR |
1666 | } |
1667 | ||
381d585c HZ |
1668 | static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) |
1669 | { | |
1670 | u64 ratio; | |
1671 | ||
1672 | /* Guest TSC same frequency as host TSC? */ | |
1673 | if (!scale) { | |
1674 | vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; | |
1675 | return 0; | |
1676 | } | |
1677 | ||
1678 | /* TSC scaling supported? */ | |
1679 | if (!kvm_has_tsc_control) { | |
1680 | if (user_tsc_khz > tsc_khz) { | |
1681 | vcpu->arch.tsc_catchup = 1; | |
1682 | vcpu->arch.tsc_always_catchup = 1; | |
1683 | return 0; | |
1684 | } else { | |
3f16a5c3 | 1685 | pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); |
381d585c HZ |
1686 | return -1; |
1687 | } | |
1688 | } | |
1689 | ||
1690 | /* TSC scaling required - calculate ratio */ | |
1691 | ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, | |
1692 | user_tsc_khz, tsc_khz); | |
1693 | ||
1694 | if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { | |
3f16a5c3 PB |
1695 | pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", |
1696 | user_tsc_khz); | |
381d585c HZ |
1697 | return -1; |
1698 | } | |
1699 | ||
1700 | vcpu->arch.tsc_scaling_ratio = ratio; | |
1701 | return 0; | |
1702 | } | |
1703 | ||
4941b8cb | 1704 | static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) |
759379dd | 1705 | { |
cc578287 ZA |
1706 | u32 thresh_lo, thresh_hi; |
1707 | int use_scaling = 0; | |
217fc9cf | 1708 | |
03ba32ca | 1709 | /* tsc_khz can be zero if TSC calibration fails */ |
4941b8cb | 1710 | if (user_tsc_khz == 0) { |
ad721883 HZ |
1711 | /* set tsc_scaling_ratio to a safe value */ |
1712 | vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; | |
381d585c | 1713 | return -1; |
ad721883 | 1714 | } |
03ba32ca | 1715 | |
c285545f | 1716 | /* Compute a scale to convert nanoseconds in TSC cycles */ |
3ae13faa | 1717 | kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, |
cc578287 ZA |
1718 | &vcpu->arch.virtual_tsc_shift, |
1719 | &vcpu->arch.virtual_tsc_mult); | |
4941b8cb | 1720 | vcpu->arch.virtual_tsc_khz = user_tsc_khz; |
cc578287 ZA |
1721 | |
1722 | /* | |
1723 | * Compute the variation in TSC rate which is acceptable | |
1724 | * within the range of tolerance and decide if the | |
1725 | * rate being applied is within that bounds of the hardware | |
1726 | * rate. If so, no scaling or compensation need be done. | |
1727 | */ | |
1728 | thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); | |
1729 | thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); | |
4941b8cb PB |
1730 | if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { |
1731 | pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); | |
cc578287 ZA |
1732 | use_scaling = 1; |
1733 | } | |
4941b8cb | 1734 | return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); |
c285545f ZA |
1735 | } |
1736 | ||
1737 | static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) | |
1738 | { | |
e26101b1 | 1739 | u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, |
cc578287 ZA |
1740 | vcpu->arch.virtual_tsc_mult, |
1741 | vcpu->arch.virtual_tsc_shift); | |
e26101b1 | 1742 | tsc += vcpu->arch.this_tsc_write; |
c285545f ZA |
1743 | return tsc; |
1744 | } | |
1745 | ||
b0c39dc6 VK |
1746 | static inline int gtod_is_based_on_tsc(int mode) |
1747 | { | |
1748 | return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK; | |
1749 | } | |
1750 | ||
69b0049a | 1751 | static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) |
b48aa97e MT |
1752 | { |
1753 | #ifdef CONFIG_X86_64 | |
1754 | bool vcpus_matched; | |
b48aa97e MT |
1755 | struct kvm_arch *ka = &vcpu->kvm->arch; |
1756 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
1757 | ||
1758 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
1759 | atomic_read(&vcpu->kvm->online_vcpus)); | |
1760 | ||
7f187922 MT |
1761 | /* |
1762 | * Once the masterclock is enabled, always perform request in | |
1763 | * order to update it. | |
1764 | * | |
1765 | * In order to enable masterclock, the host clocksource must be TSC | |
1766 | * and the vcpus need to have matched TSCs. When that happens, | |
1767 | * perform request to enable masterclock. | |
1768 | */ | |
1769 | if (ka->use_master_clock || | |
b0c39dc6 | 1770 | (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) |
b48aa97e MT |
1771 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
1772 | ||
1773 | trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, | |
1774 | atomic_read(&vcpu->kvm->online_vcpus), | |
1775 | ka->use_master_clock, gtod->clock.vclock_mode); | |
1776 | #endif | |
1777 | } | |
1778 | ||
ba904635 WA |
1779 | static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) |
1780 | { | |
e79f245d | 1781 | u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu); |
ba904635 WA |
1782 | vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; |
1783 | } | |
1784 | ||
35181e86 HZ |
1785 | /* |
1786 | * Multiply tsc by a fixed point number represented by ratio. | |
1787 | * | |
1788 | * The most significant 64-N bits (mult) of ratio represent the | |
1789 | * integral part of the fixed point number; the remaining N bits | |
1790 | * (frac) represent the fractional part, ie. ratio represents a fixed | |
1791 | * point number (mult + frac * 2^(-N)). | |
1792 | * | |
1793 | * N equals to kvm_tsc_scaling_ratio_frac_bits. | |
1794 | */ | |
1795 | static inline u64 __scale_tsc(u64 ratio, u64 tsc) | |
1796 | { | |
1797 | return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); | |
1798 | } | |
1799 | ||
1800 | u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) | |
1801 | { | |
1802 | u64 _tsc = tsc; | |
1803 | u64 ratio = vcpu->arch.tsc_scaling_ratio; | |
1804 | ||
1805 | if (ratio != kvm_default_tsc_scaling_ratio) | |
1806 | _tsc = __scale_tsc(ratio, tsc); | |
1807 | ||
1808 | return _tsc; | |
1809 | } | |
1810 | EXPORT_SYMBOL_GPL(kvm_scale_tsc); | |
1811 | ||
07c1419a HZ |
1812 | static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) |
1813 | { | |
1814 | u64 tsc; | |
1815 | ||
1816 | tsc = kvm_scale_tsc(vcpu, rdtsc()); | |
1817 | ||
1818 | return target_tsc - tsc; | |
1819 | } | |
1820 | ||
4ba76538 HZ |
1821 | u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) |
1822 | { | |
e79f245d KA |
1823 | u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu); |
1824 | ||
1825 | return tsc_offset + kvm_scale_tsc(vcpu, host_tsc); | |
4ba76538 HZ |
1826 | } |
1827 | EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); | |
1828 | ||
a545ab6a LC |
1829 | static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
1830 | { | |
326e7425 | 1831 | vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset); |
a545ab6a LC |
1832 | } |
1833 | ||
b0c39dc6 VK |
1834 | static inline bool kvm_check_tsc_unstable(void) |
1835 | { | |
1836 | #ifdef CONFIG_X86_64 | |
1837 | /* | |
1838 | * TSC is marked unstable when we're running on Hyper-V, | |
1839 | * 'TSC page' clocksource is good. | |
1840 | */ | |
1841 | if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK) | |
1842 | return false; | |
1843 | #endif | |
1844 | return check_tsc_unstable(); | |
1845 | } | |
1846 | ||
8fe8ab46 | 1847 | void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) |
99e3e30a ZA |
1848 | { |
1849 | struct kvm *kvm = vcpu->kvm; | |
f38e098f | 1850 | u64 offset, ns, elapsed; |
99e3e30a | 1851 | unsigned long flags; |
b48aa97e | 1852 | bool matched; |
0d3da0d2 | 1853 | bool already_matched; |
8fe8ab46 | 1854 | u64 data = msr->data; |
c5e8ec8e | 1855 | bool synchronizing = false; |
99e3e30a | 1856 | |
038f8c11 | 1857 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); |
07c1419a | 1858 | offset = kvm_compute_tsc_offset(vcpu, data); |
9285ec4c | 1859 | ns = ktime_get_boottime_ns(); |
f38e098f | 1860 | elapsed = ns - kvm->arch.last_tsc_nsec; |
5d3cb0f6 | 1861 | |
03ba32ca | 1862 | if (vcpu->arch.virtual_tsc_khz) { |
bd8fab39 DP |
1863 | if (data == 0 && msr->host_initiated) { |
1864 | /* | |
1865 | * detection of vcpu initialization -- need to sync | |
1866 | * with other vCPUs. This particularly helps to keep | |
1867 | * kvm_clock stable after CPU hotplug | |
1868 | */ | |
1869 | synchronizing = true; | |
1870 | } else { | |
1871 | u64 tsc_exp = kvm->arch.last_tsc_write + | |
1872 | nsec_to_cycles(vcpu, elapsed); | |
1873 | u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; | |
1874 | /* | |
1875 | * Special case: TSC write with a small delta (1 second) | |
1876 | * of virtual cycle time against real time is | |
1877 | * interpreted as an attempt to synchronize the CPU. | |
1878 | */ | |
1879 | synchronizing = data < tsc_exp + tsc_hz && | |
1880 | data + tsc_hz > tsc_exp; | |
1881 | } | |
c5e8ec8e | 1882 | } |
f38e098f ZA |
1883 | |
1884 | /* | |
5d3cb0f6 ZA |
1885 | * For a reliable TSC, we can match TSC offsets, and for an unstable |
1886 | * TSC, we add elapsed time in this computation. We could let the | |
1887 | * compensation code attempt to catch up if we fall behind, but | |
1888 | * it's better to try to match offsets from the beginning. | |
1889 | */ | |
c5e8ec8e | 1890 | if (synchronizing && |
5d3cb0f6 | 1891 | vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { |
b0c39dc6 | 1892 | if (!kvm_check_tsc_unstable()) { |
e26101b1 | 1893 | offset = kvm->arch.cur_tsc_offset; |
f38e098f | 1894 | } else { |
857e4099 | 1895 | u64 delta = nsec_to_cycles(vcpu, elapsed); |
5d3cb0f6 | 1896 | data += delta; |
07c1419a | 1897 | offset = kvm_compute_tsc_offset(vcpu, data); |
f38e098f | 1898 | } |
b48aa97e | 1899 | matched = true; |
0d3da0d2 | 1900 | already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); |
e26101b1 ZA |
1901 | } else { |
1902 | /* | |
1903 | * We split periods of matched TSC writes into generations. | |
1904 | * For each generation, we track the original measured | |
1905 | * nanosecond time, offset, and write, so if TSCs are in | |
1906 | * sync, we can match exact offset, and if not, we can match | |
4a969980 | 1907 | * exact software computation in compute_guest_tsc() |
e26101b1 ZA |
1908 | * |
1909 | * These values are tracked in kvm->arch.cur_xxx variables. | |
1910 | */ | |
1911 | kvm->arch.cur_tsc_generation++; | |
1912 | kvm->arch.cur_tsc_nsec = ns; | |
1913 | kvm->arch.cur_tsc_write = data; | |
1914 | kvm->arch.cur_tsc_offset = offset; | |
b48aa97e | 1915 | matched = false; |
f38e098f | 1916 | } |
e26101b1 ZA |
1917 | |
1918 | /* | |
1919 | * We also track th most recent recorded KHZ, write and time to | |
1920 | * allow the matching interval to be extended at each write. | |
1921 | */ | |
f38e098f ZA |
1922 | kvm->arch.last_tsc_nsec = ns; |
1923 | kvm->arch.last_tsc_write = data; | |
5d3cb0f6 | 1924 | kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; |
99e3e30a | 1925 | |
b183aa58 | 1926 | vcpu->arch.last_guest_tsc = data; |
e26101b1 ZA |
1927 | |
1928 | /* Keep track of which generation this VCPU has synchronized to */ | |
1929 | vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; | |
1930 | vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; | |
1931 | vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; | |
1932 | ||
d6321d49 | 1933 | if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) |
ba904635 | 1934 | update_ia32_tsc_adjust_msr(vcpu, offset); |
d6321d49 | 1935 | |
a545ab6a | 1936 | kvm_vcpu_write_tsc_offset(vcpu, offset); |
e26101b1 | 1937 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); |
b48aa97e MT |
1938 | |
1939 | spin_lock(&kvm->arch.pvclock_gtod_sync_lock); | |
0d3da0d2 | 1940 | if (!matched) { |
b48aa97e | 1941 | kvm->arch.nr_vcpus_matched_tsc = 0; |
0d3da0d2 TG |
1942 | } else if (!already_matched) { |
1943 | kvm->arch.nr_vcpus_matched_tsc++; | |
1944 | } | |
b48aa97e MT |
1945 | |
1946 | kvm_track_tsc_matching(vcpu); | |
1947 | spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); | |
99e3e30a | 1948 | } |
e26101b1 | 1949 | |
99e3e30a ZA |
1950 | EXPORT_SYMBOL_GPL(kvm_write_tsc); |
1951 | ||
58ea6767 HZ |
1952 | static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, |
1953 | s64 adjustment) | |
1954 | { | |
326e7425 LS |
1955 | u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu); |
1956 | kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); | |
58ea6767 HZ |
1957 | } |
1958 | ||
1959 | static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) | |
1960 | { | |
1961 | if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) | |
1962 | WARN_ON(adjustment < 0); | |
1963 | adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); | |
ea26e4ec | 1964 | adjust_tsc_offset_guest(vcpu, adjustment); |
58ea6767 HZ |
1965 | } |
1966 | ||
d828199e MT |
1967 | #ifdef CONFIG_X86_64 |
1968 | ||
a5a1d1c2 | 1969 | static u64 read_tsc(void) |
d828199e | 1970 | { |
a5a1d1c2 | 1971 | u64 ret = (u64)rdtsc_ordered(); |
03b9730b | 1972 | u64 last = pvclock_gtod_data.clock.cycle_last; |
d828199e MT |
1973 | |
1974 | if (likely(ret >= last)) | |
1975 | return ret; | |
1976 | ||
1977 | /* | |
1978 | * GCC likes to generate cmov here, but this branch is extremely | |
6a6256f9 | 1979 | * predictable (it's just a function of time and the likely is |
d828199e MT |
1980 | * very likely) and there's a data dependence, so force GCC |
1981 | * to generate a branch instead. I don't barrier() because | |
1982 | * we don't actually need a barrier, and if this function | |
1983 | * ever gets inlined it will generate worse code. | |
1984 | */ | |
1985 | asm volatile (""); | |
1986 | return last; | |
1987 | } | |
1988 | ||
b0c39dc6 | 1989 | static inline u64 vgettsc(u64 *tsc_timestamp, int *mode) |
d828199e MT |
1990 | { |
1991 | long v; | |
1992 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
b0c39dc6 VK |
1993 | u64 tsc_pg_val; |
1994 | ||
1995 | switch (gtod->clock.vclock_mode) { | |
1996 | case VCLOCK_HVCLOCK: | |
1997 | tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), | |
1998 | tsc_timestamp); | |
1999 | if (tsc_pg_val != U64_MAX) { | |
2000 | /* TSC page valid */ | |
2001 | *mode = VCLOCK_HVCLOCK; | |
2002 | v = (tsc_pg_val - gtod->clock.cycle_last) & | |
2003 | gtod->clock.mask; | |
2004 | } else { | |
2005 | /* TSC page invalid */ | |
2006 | *mode = VCLOCK_NONE; | |
2007 | } | |
2008 | break; | |
2009 | case VCLOCK_TSC: | |
2010 | *mode = VCLOCK_TSC; | |
2011 | *tsc_timestamp = read_tsc(); | |
2012 | v = (*tsc_timestamp - gtod->clock.cycle_last) & | |
2013 | gtod->clock.mask; | |
2014 | break; | |
2015 | default: | |
2016 | *mode = VCLOCK_NONE; | |
2017 | } | |
d828199e | 2018 | |
b0c39dc6 VK |
2019 | if (*mode == VCLOCK_NONE) |
2020 | *tsc_timestamp = v = 0; | |
d828199e | 2021 | |
d828199e MT |
2022 | return v * gtod->clock.mult; |
2023 | } | |
2024 | ||
b0c39dc6 | 2025 | static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp) |
d828199e | 2026 | { |
cbcf2dd3 | 2027 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; |
d828199e | 2028 | unsigned long seq; |
d828199e | 2029 | int mode; |
cbcf2dd3 | 2030 | u64 ns; |
d828199e | 2031 | |
d828199e MT |
2032 | do { |
2033 | seq = read_seqcount_begin(>od->seq); | |
cbcf2dd3 | 2034 | ns = gtod->nsec_base; |
b0c39dc6 | 2035 | ns += vgettsc(tsc_timestamp, &mode); |
d828199e | 2036 | ns >>= gtod->clock.shift; |
cbcf2dd3 | 2037 | ns += gtod->boot_ns; |
d828199e | 2038 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); |
cbcf2dd3 | 2039 | *t = ns; |
d828199e MT |
2040 | |
2041 | return mode; | |
2042 | } | |
2043 | ||
899a31f5 | 2044 | static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) |
55dd00a7 MT |
2045 | { |
2046 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
2047 | unsigned long seq; | |
2048 | int mode; | |
2049 | u64 ns; | |
2050 | ||
2051 | do { | |
2052 | seq = read_seqcount_begin(>od->seq); | |
55dd00a7 MT |
2053 | ts->tv_sec = gtod->wall_time_sec; |
2054 | ns = gtod->nsec_base; | |
b0c39dc6 | 2055 | ns += vgettsc(tsc_timestamp, &mode); |
55dd00a7 MT |
2056 | ns >>= gtod->clock.shift; |
2057 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); | |
2058 | ||
2059 | ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); | |
2060 | ts->tv_nsec = ns; | |
2061 | ||
2062 | return mode; | |
2063 | } | |
2064 | ||
b0c39dc6 VK |
2065 | /* returns true if host is using TSC based clocksource */ |
2066 | static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) | |
d828199e | 2067 | { |
d828199e | 2068 | /* checked again under seqlock below */ |
b0c39dc6 | 2069 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
d828199e MT |
2070 | return false; |
2071 | ||
b0c39dc6 VK |
2072 | return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns, |
2073 | tsc_timestamp)); | |
d828199e | 2074 | } |
55dd00a7 | 2075 | |
b0c39dc6 | 2076 | /* returns true if host is using TSC based clocksource */ |
899a31f5 | 2077 | static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, |
b0c39dc6 | 2078 | u64 *tsc_timestamp) |
55dd00a7 MT |
2079 | { |
2080 | /* checked again under seqlock below */ | |
b0c39dc6 | 2081 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
55dd00a7 MT |
2082 | return false; |
2083 | ||
b0c39dc6 | 2084 | return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); |
55dd00a7 | 2085 | } |
d828199e MT |
2086 | #endif |
2087 | ||
2088 | /* | |
2089 | * | |
b48aa97e MT |
2090 | * Assuming a stable TSC across physical CPUS, and a stable TSC |
2091 | * across virtual CPUs, the following condition is possible. | |
2092 | * Each numbered line represents an event visible to both | |
d828199e MT |
2093 | * CPUs at the next numbered event. |
2094 | * | |
2095 | * "timespecX" represents host monotonic time. "tscX" represents | |
2096 | * RDTSC value. | |
2097 | * | |
2098 | * VCPU0 on CPU0 | VCPU1 on CPU1 | |
2099 | * | |
2100 | * 1. read timespec0,tsc0 | |
2101 | * 2. | timespec1 = timespec0 + N | |
2102 | * | tsc1 = tsc0 + M | |
2103 | * 3. transition to guest | transition to guest | |
2104 | * 4. ret0 = timespec0 + (rdtsc - tsc0) | | |
2105 | * 5. | ret1 = timespec1 + (rdtsc - tsc1) | |
2106 | * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) | |
2107 | * | |
2108 | * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: | |
2109 | * | |
2110 | * - ret0 < ret1 | |
2111 | * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) | |
2112 | * ... | |
2113 | * - 0 < N - M => M < N | |
2114 | * | |
2115 | * That is, when timespec0 != timespec1, M < N. Unfortunately that is not | |
2116 | * always the case (the difference between two distinct xtime instances | |
2117 | * might be smaller then the difference between corresponding TSC reads, | |
2118 | * when updating guest vcpus pvclock areas). | |
2119 | * | |
2120 | * To avoid that problem, do not allow visibility of distinct | |
2121 | * system_timestamp/tsc_timestamp values simultaneously: use a master | |
2122 | * copy of host monotonic time values. Update that master copy | |
2123 | * in lockstep. | |
2124 | * | |
b48aa97e | 2125 | * Rely on synchronization of host TSCs and guest TSCs for monotonicity. |
d828199e MT |
2126 | * |
2127 | */ | |
2128 | ||
2129 | static void pvclock_update_vm_gtod_copy(struct kvm *kvm) | |
2130 | { | |
2131 | #ifdef CONFIG_X86_64 | |
2132 | struct kvm_arch *ka = &kvm->arch; | |
2133 | int vclock_mode; | |
b48aa97e MT |
2134 | bool host_tsc_clocksource, vcpus_matched; |
2135 | ||
2136 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
2137 | atomic_read(&kvm->online_vcpus)); | |
d828199e MT |
2138 | |
2139 | /* | |
2140 | * If the host uses TSC clock, then passthrough TSC as stable | |
2141 | * to the guest. | |
2142 | */ | |
b48aa97e | 2143 | host_tsc_clocksource = kvm_get_time_and_clockread( |
d828199e MT |
2144 | &ka->master_kernel_ns, |
2145 | &ka->master_cycle_now); | |
2146 | ||
16a96021 | 2147 | ka->use_master_clock = host_tsc_clocksource && vcpus_matched |
a826faf1 | 2148 | && !ka->backwards_tsc_observed |
54750f2c | 2149 | && !ka->boot_vcpu_runs_old_kvmclock; |
b48aa97e | 2150 | |
d828199e MT |
2151 | if (ka->use_master_clock) |
2152 | atomic_set(&kvm_guest_has_master_clock, 1); | |
2153 | ||
2154 | vclock_mode = pvclock_gtod_data.clock.vclock_mode; | |
b48aa97e MT |
2155 | trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, |
2156 | vcpus_matched); | |
d828199e MT |
2157 | #endif |
2158 | } | |
2159 | ||
2860c4b1 PB |
2160 | void kvm_make_mclock_inprogress_request(struct kvm *kvm) |
2161 | { | |
2162 | kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); | |
2163 | } | |
2164 | ||
2e762ff7 MT |
2165 | static void kvm_gen_update_masterclock(struct kvm *kvm) |
2166 | { | |
2167 | #ifdef CONFIG_X86_64 | |
2168 | int i; | |
2169 | struct kvm_vcpu *vcpu; | |
2170 | struct kvm_arch *ka = &kvm->arch; | |
2171 | ||
2172 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
2173 | kvm_make_mclock_inprogress_request(kvm); | |
2174 | /* no guest entries from this point */ | |
2175 | pvclock_update_vm_gtod_copy(kvm); | |
2176 | ||
2177 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 2178 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
2e762ff7 MT |
2179 | |
2180 | /* guest entries allowed */ | |
2181 | kvm_for_each_vcpu(i, vcpu, kvm) | |
72875d8a | 2182 | kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); |
2e762ff7 MT |
2183 | |
2184 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
2185 | #endif | |
2186 | } | |
2187 | ||
e891a32e | 2188 | u64 get_kvmclock_ns(struct kvm *kvm) |
108b249c | 2189 | { |
108b249c | 2190 | struct kvm_arch *ka = &kvm->arch; |
8b953440 | 2191 | struct pvclock_vcpu_time_info hv_clock; |
e2c2206a | 2192 | u64 ret; |
108b249c | 2193 | |
8b953440 PB |
2194 | spin_lock(&ka->pvclock_gtod_sync_lock); |
2195 | if (!ka->use_master_clock) { | |
2196 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
9285ec4c | 2197 | return ktime_get_boottime_ns() + ka->kvmclock_offset; |
108b249c PB |
2198 | } |
2199 | ||
8b953440 PB |
2200 | hv_clock.tsc_timestamp = ka->master_cycle_now; |
2201 | hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; | |
2202 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
2203 | ||
e2c2206a WL |
2204 | /* both __this_cpu_read() and rdtsc() should be on the same cpu */ |
2205 | get_cpu(); | |
2206 | ||
e70b57a6 WL |
2207 | if (__this_cpu_read(cpu_tsc_khz)) { |
2208 | kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, | |
2209 | &hv_clock.tsc_shift, | |
2210 | &hv_clock.tsc_to_system_mul); | |
2211 | ret = __pvclock_read_cycles(&hv_clock, rdtsc()); | |
2212 | } else | |
9285ec4c | 2213 | ret = ktime_get_boottime_ns() + ka->kvmclock_offset; |
e2c2206a WL |
2214 | |
2215 | put_cpu(); | |
2216 | ||
2217 | return ret; | |
108b249c PB |
2218 | } |
2219 | ||
0d6dd2ff PB |
2220 | static void kvm_setup_pvclock_page(struct kvm_vcpu *v) |
2221 | { | |
2222 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
2223 | struct pvclock_vcpu_time_info guest_hv_clock; | |
2224 | ||
4e335d9e | 2225 | if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, |
0d6dd2ff PB |
2226 | &guest_hv_clock, sizeof(guest_hv_clock)))) |
2227 | return; | |
2228 | ||
2229 | /* This VCPU is paused, but it's legal for a guest to read another | |
2230 | * VCPU's kvmclock, so we really have to follow the specification where | |
2231 | * it says that version is odd if data is being modified, and even after | |
2232 | * it is consistent. | |
2233 | * | |
2234 | * Version field updates must be kept separate. This is because | |
2235 | * kvm_write_guest_cached might use a "rep movs" instruction, and | |
2236 | * writes within a string instruction are weakly ordered. So there | |
2237 | * are three writes overall. | |
2238 | * | |
2239 | * As a small optimization, only write the version field in the first | |
2240 | * and third write. The vcpu->pv_time cache is still valid, because the | |
2241 | * version field is the first in the struct. | |
2242 | */ | |
2243 | BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); | |
2244 | ||
51c4b8bb LA |
2245 | if (guest_hv_clock.version & 1) |
2246 | ++guest_hv_clock.version; /* first time write, random junk */ | |
2247 | ||
0d6dd2ff | 2248 | vcpu->hv_clock.version = guest_hv_clock.version + 1; |
4e335d9e PB |
2249 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
2250 | &vcpu->hv_clock, | |
2251 | sizeof(vcpu->hv_clock.version)); | |
0d6dd2ff PB |
2252 | |
2253 | smp_wmb(); | |
2254 | ||
2255 | /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ | |
2256 | vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); | |
2257 | ||
2258 | if (vcpu->pvclock_set_guest_stopped_request) { | |
2259 | vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; | |
2260 | vcpu->pvclock_set_guest_stopped_request = false; | |
2261 | } | |
2262 | ||
2263 | trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); | |
2264 | ||
4e335d9e PB |
2265 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
2266 | &vcpu->hv_clock, | |
2267 | sizeof(vcpu->hv_clock)); | |
0d6dd2ff PB |
2268 | |
2269 | smp_wmb(); | |
2270 | ||
2271 | vcpu->hv_clock.version++; | |
4e335d9e PB |
2272 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
2273 | &vcpu->hv_clock, | |
2274 | sizeof(vcpu->hv_clock.version)); | |
0d6dd2ff PB |
2275 | } |
2276 | ||
34c238a1 | 2277 | static int kvm_guest_time_update(struct kvm_vcpu *v) |
18068523 | 2278 | { |
78db6a50 | 2279 | unsigned long flags, tgt_tsc_khz; |
18068523 | 2280 | struct kvm_vcpu_arch *vcpu = &v->arch; |
d828199e | 2281 | struct kvm_arch *ka = &v->kvm->arch; |
f25e656d | 2282 | s64 kernel_ns; |
d828199e | 2283 | u64 tsc_timestamp, host_tsc; |
51d59c6b | 2284 | u8 pvclock_flags; |
d828199e MT |
2285 | bool use_master_clock; |
2286 | ||
2287 | kernel_ns = 0; | |
2288 | host_tsc = 0; | |
18068523 | 2289 | |
d828199e MT |
2290 | /* |
2291 | * If the host uses TSC clock, then passthrough TSC as stable | |
2292 | * to the guest. | |
2293 | */ | |
2294 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
2295 | use_master_clock = ka->use_master_clock; | |
2296 | if (use_master_clock) { | |
2297 | host_tsc = ka->master_cycle_now; | |
2298 | kernel_ns = ka->master_kernel_ns; | |
2299 | } | |
2300 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
c09664bb MT |
2301 | |
2302 | /* Keep irq disabled to prevent changes to the clock */ | |
2303 | local_irq_save(flags); | |
78db6a50 PB |
2304 | tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); |
2305 | if (unlikely(tgt_tsc_khz == 0)) { | |
c09664bb MT |
2306 | local_irq_restore(flags); |
2307 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); | |
2308 | return 1; | |
2309 | } | |
d828199e | 2310 | if (!use_master_clock) { |
4ea1636b | 2311 | host_tsc = rdtsc(); |
9285ec4c | 2312 | kernel_ns = ktime_get_boottime_ns(); |
d828199e MT |
2313 | } |
2314 | ||
4ba76538 | 2315 | tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); |
d828199e | 2316 | |
c285545f ZA |
2317 | /* |
2318 | * We may have to catch up the TSC to match elapsed wall clock | |
2319 | * time for two reasons, even if kvmclock is used. | |
2320 | * 1) CPU could have been running below the maximum TSC rate | |
2321 | * 2) Broken TSC compensation resets the base at each VCPU | |
2322 | * entry to avoid unknown leaps of TSC even when running | |
2323 | * again on the same CPU. This may cause apparent elapsed | |
2324 | * time to disappear, and the guest to stand still or run | |
2325 | * very slowly. | |
2326 | */ | |
2327 | if (vcpu->tsc_catchup) { | |
2328 | u64 tsc = compute_guest_tsc(v, kernel_ns); | |
2329 | if (tsc > tsc_timestamp) { | |
f1e2b260 | 2330 | adjust_tsc_offset_guest(v, tsc - tsc_timestamp); |
c285545f ZA |
2331 | tsc_timestamp = tsc; |
2332 | } | |
50d0a0f9 GH |
2333 | } |
2334 | ||
18068523 GOC |
2335 | local_irq_restore(flags); |
2336 | ||
0d6dd2ff | 2337 | /* With all the info we got, fill in the values */ |
18068523 | 2338 | |
78db6a50 PB |
2339 | if (kvm_has_tsc_control) |
2340 | tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz); | |
2341 | ||
2342 | if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { | |
3ae13faa | 2343 | kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, |
5f4e3f88 ZA |
2344 | &vcpu->hv_clock.tsc_shift, |
2345 | &vcpu->hv_clock.tsc_to_system_mul); | |
78db6a50 | 2346 | vcpu->hw_tsc_khz = tgt_tsc_khz; |
8cfdc000 ZA |
2347 | } |
2348 | ||
1d5f066e | 2349 | vcpu->hv_clock.tsc_timestamp = tsc_timestamp; |
759379dd | 2350 | vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; |
28e4639a | 2351 | vcpu->last_guest_tsc = tsc_timestamp; |
51d59c6b | 2352 | |
d828199e | 2353 | /* If the host uses TSC clocksource, then it is stable */ |
0d6dd2ff | 2354 | pvclock_flags = 0; |
d828199e MT |
2355 | if (use_master_clock) |
2356 | pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; | |
2357 | ||
78c0337a MT |
2358 | vcpu->hv_clock.flags = pvclock_flags; |
2359 | ||
095cf55d PB |
2360 | if (vcpu->pv_time_enabled) |
2361 | kvm_setup_pvclock_page(v); | |
2362 | if (v == kvm_get_vcpu(v->kvm, 0)) | |
2363 | kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); | |
8cfdc000 | 2364 | return 0; |
c8076604 GH |
2365 | } |
2366 | ||
0061d53d MT |
2367 | /* |
2368 | * kvmclock updates which are isolated to a given vcpu, such as | |
2369 | * vcpu->cpu migration, should not allow system_timestamp from | |
2370 | * the rest of the vcpus to remain static. Otherwise ntp frequency | |
2371 | * correction applies to one vcpu's system_timestamp but not | |
2372 | * the others. | |
2373 | * | |
2374 | * So in those cases, request a kvmclock update for all vcpus. | |
7e44e449 AJ |
2375 | * We need to rate-limit these requests though, as they can |
2376 | * considerably slow guests that have a large number of vcpus. | |
2377 | * The time for a remote vcpu to update its kvmclock is bound | |
2378 | * by the delay we use to rate-limit the updates. | |
0061d53d MT |
2379 | */ |
2380 | ||
7e44e449 AJ |
2381 | #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) |
2382 | ||
2383 | static void kvmclock_update_fn(struct work_struct *work) | |
0061d53d MT |
2384 | { |
2385 | int i; | |
7e44e449 AJ |
2386 | struct delayed_work *dwork = to_delayed_work(work); |
2387 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
2388 | kvmclock_update_work); | |
2389 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
0061d53d MT |
2390 | struct kvm_vcpu *vcpu; |
2391 | ||
2392 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
105b21bb | 2393 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0061d53d MT |
2394 | kvm_vcpu_kick(vcpu); |
2395 | } | |
2396 | } | |
2397 | ||
7e44e449 AJ |
2398 | static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) |
2399 | { | |
2400 | struct kvm *kvm = v->kvm; | |
2401 | ||
105b21bb | 2402 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); |
7e44e449 AJ |
2403 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, |
2404 | KVMCLOCK_UPDATE_DELAY); | |
2405 | } | |
2406 | ||
332967a3 AJ |
2407 | #define KVMCLOCK_SYNC_PERIOD (300 * HZ) |
2408 | ||
2409 | static void kvmclock_sync_fn(struct work_struct *work) | |
2410 | { | |
2411 | struct delayed_work *dwork = to_delayed_work(work); | |
2412 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
2413 | kvmclock_sync_work); | |
2414 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
2415 | ||
630994b3 MT |
2416 | if (!kvmclock_periodic_sync) |
2417 | return; | |
2418 | ||
332967a3 AJ |
2419 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); |
2420 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
2421 | KVMCLOCK_SYNC_PERIOD); | |
2422 | } | |
2423 | ||
191c8137 BP |
2424 | /* |
2425 | * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. | |
2426 | */ | |
2427 | static bool can_set_mci_status(struct kvm_vcpu *vcpu) | |
2428 | { | |
2429 | /* McStatusWrEn enabled? */ | |
2430 | if (guest_cpuid_is_amd(vcpu)) | |
2431 | return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); | |
2432 | ||
2433 | return false; | |
2434 | } | |
2435 | ||
9ffd986c | 2436 | static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 2437 | { |
890ca9ae HY |
2438 | u64 mcg_cap = vcpu->arch.mcg_cap; |
2439 | unsigned bank_num = mcg_cap & 0xff; | |
9ffd986c WL |
2440 | u32 msr = msr_info->index; |
2441 | u64 data = msr_info->data; | |
890ca9ae | 2442 | |
15c4a640 | 2443 | switch (msr) { |
15c4a640 | 2444 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 2445 | vcpu->arch.mcg_status = data; |
15c4a640 | 2446 | break; |
c7ac679c | 2447 | case MSR_IA32_MCG_CTL: |
44883f01 PB |
2448 | if (!(mcg_cap & MCG_CTL_P) && |
2449 | (data || !msr_info->host_initiated)) | |
890ca9ae HY |
2450 | return 1; |
2451 | if (data != 0 && data != ~(u64)0) | |
44883f01 | 2452 | return 1; |
890ca9ae HY |
2453 | vcpu->arch.mcg_ctl = data; |
2454 | break; | |
2455 | default: | |
2456 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 2457 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
890ca9ae | 2458 | u32 offset = msr - MSR_IA32_MC0_CTL; |
114be429 AP |
2459 | /* only 0 or all 1s can be written to IA32_MCi_CTL |
2460 | * some Linux kernels though clear bit 10 in bank 4 to | |
2461 | * workaround a BIOS/GART TBL issue on AMD K8s, ignore | |
2462 | * this to avoid an uncatched #GP in the guest | |
2463 | */ | |
890ca9ae | 2464 | if ((offset & 0x3) == 0 && |
114be429 | 2465 | data != 0 && (data | (1 << 10)) != ~(u64)0) |
890ca9ae | 2466 | return -1; |
191c8137 BP |
2467 | |
2468 | /* MCi_STATUS */ | |
9ffd986c | 2469 | if (!msr_info->host_initiated && |
191c8137 BP |
2470 | (offset & 0x3) == 1 && data != 0) { |
2471 | if (!can_set_mci_status(vcpu)) | |
2472 | return -1; | |
2473 | } | |
2474 | ||
890ca9ae HY |
2475 | vcpu->arch.mce_banks[offset] = data; |
2476 | break; | |
2477 | } | |
2478 | return 1; | |
2479 | } | |
2480 | return 0; | |
2481 | } | |
2482 | ||
ffde22ac ES |
2483 | static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) |
2484 | { | |
2485 | struct kvm *kvm = vcpu->kvm; | |
2486 | int lm = is_long_mode(vcpu); | |
2487 | u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 | |
2488 | : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; | |
2489 | u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 | |
2490 | : kvm->arch.xen_hvm_config.blob_size_32; | |
2491 | u32 page_num = data & ~PAGE_MASK; | |
2492 | u64 page_addr = data & PAGE_MASK; | |
2493 | u8 *page; | |
2494 | int r; | |
2495 | ||
2496 | r = -E2BIG; | |
2497 | if (page_num >= blob_size) | |
2498 | goto out; | |
2499 | r = -ENOMEM; | |
ff5c2c03 SL |
2500 | page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); |
2501 | if (IS_ERR(page)) { | |
2502 | r = PTR_ERR(page); | |
ffde22ac | 2503 | goto out; |
ff5c2c03 | 2504 | } |
54bf36aa | 2505 | if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) |
ffde22ac ES |
2506 | goto out_free; |
2507 | r = 0; | |
2508 | out_free: | |
2509 | kfree(page); | |
2510 | out: | |
2511 | return r; | |
2512 | } | |
2513 | ||
344d9588 GN |
2514 | static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) |
2515 | { | |
2516 | gpa_t gpa = data & ~0x3f; | |
2517 | ||
52a5c155 WL |
2518 | /* Bits 3:5 are reserved, Should be zero */ |
2519 | if (data & 0x38) | |
344d9588 GN |
2520 | return 1; |
2521 | ||
2522 | vcpu->arch.apf.msr_val = data; | |
2523 | ||
2524 | if (!(data & KVM_ASYNC_PF_ENABLED)) { | |
2525 | kvm_clear_async_pf_completion_queue(vcpu); | |
2526 | kvm_async_pf_hash_reset(vcpu); | |
2527 | return 0; | |
2528 | } | |
2529 | ||
4e335d9e | 2530 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, |
8f964525 | 2531 | sizeof(u32))) |
344d9588 GN |
2532 | return 1; |
2533 | ||
6adba527 | 2534 | vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); |
52a5c155 | 2535 | vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; |
344d9588 GN |
2536 | kvm_async_pf_wakeup_all(vcpu); |
2537 | return 0; | |
2538 | } | |
2539 | ||
12f9a48f GC |
2540 | static void kvmclock_reset(struct kvm_vcpu *vcpu) |
2541 | { | |
0b79459b | 2542 | vcpu->arch.pv_time_enabled = false; |
12f9a48f GC |
2543 | } |
2544 | ||
f38a7b75 WL |
2545 | static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa) |
2546 | { | |
2547 | ++vcpu->stat.tlb_flush; | |
2548 | kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa); | |
2549 | } | |
2550 | ||
c9aaa895 GC |
2551 | static void record_steal_time(struct kvm_vcpu *vcpu) |
2552 | { | |
2553 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) | |
2554 | return; | |
2555 | ||
4e335d9e | 2556 | if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, |
c9aaa895 GC |
2557 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) |
2558 | return; | |
2559 | ||
f38a7b75 WL |
2560 | /* |
2561 | * Doing a TLB flush here, on the guest's behalf, can avoid | |
2562 | * expensive IPIs. | |
2563 | */ | |
b382f44e WL |
2564 | trace_kvm_pv_tlb_flush(vcpu->vcpu_id, |
2565 | vcpu->arch.st.steal.preempted & KVM_VCPU_FLUSH_TLB); | |
f38a7b75 WL |
2566 | if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB) |
2567 | kvm_vcpu_flush_tlb(vcpu, false); | |
0b9f6c46 | 2568 | |
35f3fae1 WL |
2569 | if (vcpu->arch.st.steal.version & 1) |
2570 | vcpu->arch.st.steal.version += 1; /* first time write, random junk */ | |
2571 | ||
2572 | vcpu->arch.st.steal.version += 1; | |
2573 | ||
4e335d9e | 2574 | kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, |
35f3fae1 WL |
2575 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); |
2576 | ||
2577 | smp_wmb(); | |
2578 | ||
c54cdf14 LC |
2579 | vcpu->arch.st.steal.steal += current->sched_info.run_delay - |
2580 | vcpu->arch.st.last_steal; | |
2581 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
35f3fae1 | 2582 | |
4e335d9e | 2583 | kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, |
35f3fae1 WL |
2584 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); |
2585 | ||
2586 | smp_wmb(); | |
2587 | ||
2588 | vcpu->arch.st.steal.version += 1; | |
c9aaa895 | 2589 | |
4e335d9e | 2590 | kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, |
c9aaa895 GC |
2591 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); |
2592 | } | |
2593 | ||
8fe8ab46 | 2594 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 2595 | { |
5753785f | 2596 | bool pr = false; |
8fe8ab46 WA |
2597 | u32 msr = msr_info->index; |
2598 | u64 data = msr_info->data; | |
5753785f | 2599 | |
15c4a640 | 2600 | switch (msr) { |
2e32b719 | 2601 | case MSR_AMD64_NB_CFG: |
2e32b719 BP |
2602 | case MSR_IA32_UCODE_WRITE: |
2603 | case MSR_VM_HSAVE_PA: | |
2604 | case MSR_AMD64_PATCH_LOADER: | |
2605 | case MSR_AMD64_BU_CFG2: | |
405a353a | 2606 | case MSR_AMD64_DC_CFG: |
0e1b869f | 2607 | case MSR_F15H_EX_CFG: |
2e32b719 BP |
2608 | break; |
2609 | ||
518e7b94 WL |
2610 | case MSR_IA32_UCODE_REV: |
2611 | if (msr_info->host_initiated) | |
2612 | vcpu->arch.microcode_version = data; | |
2613 | break; | |
0cf9135b SC |
2614 | case MSR_IA32_ARCH_CAPABILITIES: |
2615 | if (!msr_info->host_initiated) | |
2616 | return 1; | |
2617 | vcpu->arch.arch_capabilities = data; | |
2618 | break; | |
15c4a640 | 2619 | case MSR_EFER: |
11988499 | 2620 | return set_efer(vcpu, msr_info); |
8f1589d9 AP |
2621 | case MSR_K7_HWCR: |
2622 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
82494028 | 2623 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ |
a223c313 | 2624 | data &= ~(u64)0x8; /* ignore TLB cache disable */ |
191c8137 BP |
2625 | |
2626 | /* Handle McStatusWrEn */ | |
2627 | if (data == BIT_ULL(18)) { | |
2628 | vcpu->arch.msr_hwcr = data; | |
2629 | } else if (data != 0) { | |
a737f256 CD |
2630 | vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", |
2631 | data); | |
8f1589d9 AP |
2632 | return 1; |
2633 | } | |
15c4a640 | 2634 | break; |
f7c6d140 AP |
2635 | case MSR_FAM10H_MMIO_CONF_BASE: |
2636 | if (data != 0) { | |
a737f256 CD |
2637 | vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " |
2638 | "0x%llx\n", data); | |
f7c6d140 AP |
2639 | return 1; |
2640 | } | |
15c4a640 | 2641 | break; |
b5e2fec0 AG |
2642 | case MSR_IA32_DEBUGCTLMSR: |
2643 | if (!data) { | |
2644 | /* We support the non-activated case already */ | |
2645 | break; | |
2646 | } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { | |
2647 | /* Values other than LBR and BTF are vendor-specific, | |
2648 | thus reserved and should throw a #GP */ | |
2649 | return 1; | |
2650 | } | |
a737f256 CD |
2651 | vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", |
2652 | __func__, data); | |
b5e2fec0 | 2653 | break; |
9ba075a6 | 2654 | case 0x200 ... 0x2ff: |
ff53604b | 2655 | return kvm_mtrr_set_msr(vcpu, msr, data); |
15c4a640 | 2656 | case MSR_IA32_APICBASE: |
58cb628d | 2657 | return kvm_set_apic_base(vcpu, msr_info); |
0105d1a5 GN |
2658 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
2659 | return kvm_x2apic_msr_write(vcpu, msr, data); | |
a3e06bbe LJ |
2660 | case MSR_IA32_TSCDEADLINE: |
2661 | kvm_set_lapic_tscdeadline_msr(vcpu, data); | |
2662 | break; | |
ba904635 | 2663 | case MSR_IA32_TSC_ADJUST: |
d6321d49 | 2664 | if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { |
ba904635 | 2665 | if (!msr_info->host_initiated) { |
d913b904 | 2666 | s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; |
d7add054 | 2667 | adjust_tsc_offset_guest(vcpu, adj); |
ba904635 WA |
2668 | } |
2669 | vcpu->arch.ia32_tsc_adjust_msr = data; | |
2670 | } | |
2671 | break; | |
15c4a640 | 2672 | case MSR_IA32_MISC_ENABLE: |
511a8556 WL |
2673 | if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && |
2674 | ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { | |
2675 | if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) | |
2676 | return 1; | |
2677 | vcpu->arch.ia32_misc_enable_msr = data; | |
2678 | kvm_update_cpuid(vcpu); | |
2679 | } else { | |
2680 | vcpu->arch.ia32_misc_enable_msr = data; | |
2681 | } | |
15c4a640 | 2682 | break; |
64d60670 PB |
2683 | case MSR_IA32_SMBASE: |
2684 | if (!msr_info->host_initiated) | |
2685 | return 1; | |
2686 | vcpu->arch.smbase = data; | |
2687 | break; | |
73f624f4 PB |
2688 | case MSR_IA32_POWER_CTL: |
2689 | vcpu->arch.msr_ia32_power_ctl = data; | |
2690 | break; | |
dd259935 PB |
2691 | case MSR_IA32_TSC: |
2692 | kvm_write_tsc(vcpu, msr_info); | |
2693 | break; | |
52797bf9 LA |
2694 | case MSR_SMI_COUNT: |
2695 | if (!msr_info->host_initiated) | |
2696 | return 1; | |
2697 | vcpu->arch.smi_count = data; | |
2698 | break; | |
11c6bffa | 2699 | case MSR_KVM_WALL_CLOCK_NEW: |
18068523 GOC |
2700 | case MSR_KVM_WALL_CLOCK: |
2701 | vcpu->kvm->arch.wall_clock = data; | |
2702 | kvm_write_wall_clock(vcpu->kvm, data); | |
2703 | break; | |
11c6bffa | 2704 | case MSR_KVM_SYSTEM_TIME_NEW: |
18068523 | 2705 | case MSR_KVM_SYSTEM_TIME: { |
54750f2c MT |
2706 | struct kvm_arch *ka = &vcpu->kvm->arch; |
2707 | ||
12f9a48f | 2708 | kvmclock_reset(vcpu); |
18068523 | 2709 | |
54750f2c MT |
2710 | if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { |
2711 | bool tmp = (msr == MSR_KVM_SYSTEM_TIME); | |
2712 | ||
2713 | if (ka->boot_vcpu_runs_old_kvmclock != tmp) | |
1bd2009e | 2714 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
54750f2c MT |
2715 | |
2716 | ka->boot_vcpu_runs_old_kvmclock = tmp; | |
2717 | } | |
2718 | ||
18068523 | 2719 | vcpu->arch.time = data; |
0061d53d | 2720 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
18068523 GOC |
2721 | |
2722 | /* we verify if the enable bit is set... */ | |
2723 | if (!(data & 1)) | |
2724 | break; | |
2725 | ||
4e335d9e | 2726 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, |
8f964525 AH |
2727 | &vcpu->arch.pv_time, data & ~1ULL, |
2728 | sizeof(struct pvclock_vcpu_time_info))) | |
0b79459b AH |
2729 | vcpu->arch.pv_time_enabled = false; |
2730 | else | |
2731 | vcpu->arch.pv_time_enabled = true; | |
32cad84f | 2732 | |
18068523 GOC |
2733 | break; |
2734 | } | |
344d9588 GN |
2735 | case MSR_KVM_ASYNC_PF_EN: |
2736 | if (kvm_pv_enable_async_pf(vcpu, data)) | |
2737 | return 1; | |
2738 | break; | |
c9aaa895 GC |
2739 | case MSR_KVM_STEAL_TIME: |
2740 | ||
2741 | if (unlikely(!sched_info_on())) | |
2742 | return 1; | |
2743 | ||
2744 | if (data & KVM_STEAL_RESERVED_MASK) | |
2745 | return 1; | |
2746 | ||
4e335d9e | 2747 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, |
8f964525 AH |
2748 | data & KVM_STEAL_VALID_BITS, |
2749 | sizeof(struct kvm_steal_time))) | |
c9aaa895 GC |
2750 | return 1; |
2751 | ||
2752 | vcpu->arch.st.msr_val = data; | |
2753 | ||
2754 | if (!(data & KVM_MSR_ENABLED)) | |
2755 | break; | |
2756 | ||
c9aaa895 GC |
2757 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
2758 | ||
2759 | break; | |
ae7a2a3f | 2760 | case MSR_KVM_PV_EOI_EN: |
72bbf935 | 2761 | if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8))) |
ae7a2a3f MT |
2762 | return 1; |
2763 | break; | |
c9aaa895 | 2764 | |
2d5ba19b MT |
2765 | case MSR_KVM_POLL_CONTROL: |
2766 | /* only enable bit supported */ | |
2767 | if (data & (-1ULL << 1)) | |
2768 | return 1; | |
2769 | ||
2770 | vcpu->arch.msr_kvm_poll_control = data; | |
2771 | break; | |
2772 | ||
890ca9ae HY |
2773 | case MSR_IA32_MCG_CTL: |
2774 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 2775 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
9ffd986c | 2776 | return set_msr_mce(vcpu, msr_info); |
71db6023 | 2777 | |
6912ac32 WH |
2778 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: |
2779 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
2780 | pr = true; /* fall through */ | |
2781 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: | |
2782 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 2783 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 2784 | return kvm_pmu_set_msr(vcpu, msr_info); |
5753785f GN |
2785 | |
2786 | if (pr || data != 0) | |
a737f256 CD |
2787 | vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " |
2788 | "0x%x data 0x%llx\n", msr, data); | |
5753785f | 2789 | break; |
84e0cefa JS |
2790 | case MSR_K7_CLK_CTL: |
2791 | /* | |
2792 | * Ignore all writes to this no longer documented MSR. | |
2793 | * Writes are only relevant for old K7 processors, | |
2794 | * all pre-dating SVM, but a recommended workaround from | |
4a969980 | 2795 | * AMD for these chips. It is possible to specify the |
84e0cefa JS |
2796 | * affected processor models on the command line, hence |
2797 | * the need to ignore the workaround. | |
2798 | */ | |
2799 | break; | |
55cd8e5a | 2800 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
e7d9513b AS |
2801 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
2802 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 2803 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
2804 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
2805 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
2806 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
e7d9513b AS |
2807 | return kvm_hv_set_msr_common(vcpu, msr, data, |
2808 | msr_info->host_initiated); | |
91c9c3ed | 2809 | case MSR_IA32_BBL_CR_CTL3: |
2810 | /* Drop writes to this legacy MSR -- see rdmsr | |
2811 | * counterpart for further detail. | |
2812 | */ | |
fab0aa3b EM |
2813 | if (report_ignored_msrs) |
2814 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", | |
2815 | msr, data); | |
91c9c3ed | 2816 | break; |
2b036c6b | 2817 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 2818 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
2819 | return 1; |
2820 | vcpu->arch.osvw.length = data; | |
2821 | break; | |
2822 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 2823 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
2824 | return 1; |
2825 | vcpu->arch.osvw.status = data; | |
2826 | break; | |
db2336a8 KH |
2827 | case MSR_PLATFORM_INFO: |
2828 | if (!msr_info->host_initiated || | |
db2336a8 KH |
2829 | (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && |
2830 | cpuid_fault_enabled(vcpu))) | |
2831 | return 1; | |
2832 | vcpu->arch.msr_platform_info = data; | |
2833 | break; | |
2834 | case MSR_MISC_FEATURES_ENABLES: | |
2835 | if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || | |
2836 | (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && | |
2837 | !supports_cpuid_fault(vcpu))) | |
2838 | return 1; | |
2839 | vcpu->arch.msr_misc_features_enables = data; | |
2840 | break; | |
15c4a640 | 2841 | default: |
ffde22ac ES |
2842 | if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) |
2843 | return xen_hvm_config(vcpu, data); | |
c6702c9d | 2844 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 2845 | return kvm_pmu_set_msr(vcpu, msr_info); |
ed85c068 | 2846 | if (!ignore_msrs) { |
ae0f5499 | 2847 | vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n", |
a737f256 | 2848 | msr, data); |
ed85c068 AP |
2849 | return 1; |
2850 | } else { | |
fab0aa3b EM |
2851 | if (report_ignored_msrs) |
2852 | vcpu_unimpl(vcpu, | |
2853 | "ignored wrmsr: 0x%x data 0x%llx\n", | |
2854 | msr, data); | |
ed85c068 AP |
2855 | break; |
2856 | } | |
15c4a640 CO |
2857 | } |
2858 | return 0; | |
2859 | } | |
2860 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
2861 | ||
44883f01 | 2862 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) |
15c4a640 CO |
2863 | { |
2864 | u64 data; | |
890ca9ae HY |
2865 | u64 mcg_cap = vcpu->arch.mcg_cap; |
2866 | unsigned bank_num = mcg_cap & 0xff; | |
15c4a640 CO |
2867 | |
2868 | switch (msr) { | |
15c4a640 CO |
2869 | case MSR_IA32_P5_MC_ADDR: |
2870 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
2871 | data = 0; |
2872 | break; | |
15c4a640 | 2873 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
2874 | data = vcpu->arch.mcg_cap; |
2875 | break; | |
c7ac679c | 2876 | case MSR_IA32_MCG_CTL: |
44883f01 | 2877 | if (!(mcg_cap & MCG_CTL_P) && !host) |
890ca9ae HY |
2878 | return 1; |
2879 | data = vcpu->arch.mcg_ctl; | |
2880 | break; | |
2881 | case MSR_IA32_MCG_STATUS: | |
2882 | data = vcpu->arch.mcg_status; | |
2883 | break; | |
2884 | default: | |
2885 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 2886 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
890ca9ae HY |
2887 | u32 offset = msr - MSR_IA32_MC0_CTL; |
2888 | data = vcpu->arch.mce_banks[offset]; | |
2889 | break; | |
2890 | } | |
2891 | return 1; | |
2892 | } | |
2893 | *pdata = data; | |
2894 | return 0; | |
2895 | } | |
2896 | ||
609e36d3 | 2897 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
890ca9ae | 2898 | { |
609e36d3 | 2899 | switch (msr_info->index) { |
890ca9ae | 2900 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 2901 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
2902 | case MSR_IA32_DEBUGCTLMSR: |
2903 | case MSR_IA32_LASTBRANCHFROMIP: | |
2904 | case MSR_IA32_LASTBRANCHTOIP: | |
2905 | case MSR_IA32_LASTINTFROMIP: | |
2906 | case MSR_IA32_LASTINTTOIP: | |
60af2ecd | 2907 | case MSR_K8_SYSCFG: |
3afb1121 PB |
2908 | case MSR_K8_TSEG_ADDR: |
2909 | case MSR_K8_TSEG_MASK: | |
61a6bd67 | 2910 | case MSR_VM_HSAVE_PA: |
1fdbd48c | 2911 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 2912 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 2913 | case MSR_FAM10H_MMIO_CONF_BASE: |
2e32b719 | 2914 | case MSR_AMD64_BU_CFG2: |
0c2df2a1 | 2915 | case MSR_IA32_PERF_CTL: |
405a353a | 2916 | case MSR_AMD64_DC_CFG: |
0e1b869f | 2917 | case MSR_F15H_EX_CFG: |
609e36d3 | 2918 | msr_info->data = 0; |
15c4a640 | 2919 | break; |
c51eb52b | 2920 | case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: |
6912ac32 WH |
2921 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: |
2922 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: | |
2923 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
2924 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 2925 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
609e36d3 PB |
2926 | return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); |
2927 | msr_info->data = 0; | |
5753785f | 2928 | break; |
742bc670 | 2929 | case MSR_IA32_UCODE_REV: |
518e7b94 | 2930 | msr_info->data = vcpu->arch.microcode_version; |
742bc670 | 2931 | break; |
0cf9135b SC |
2932 | case MSR_IA32_ARCH_CAPABILITIES: |
2933 | if (!msr_info->host_initiated && | |
2934 | !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) | |
2935 | return 1; | |
2936 | msr_info->data = vcpu->arch.arch_capabilities; | |
2937 | break; | |
73f624f4 PB |
2938 | case MSR_IA32_POWER_CTL: |
2939 | msr_info->data = vcpu->arch.msr_ia32_power_ctl; | |
2940 | break; | |
dd259935 PB |
2941 | case MSR_IA32_TSC: |
2942 | msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset; | |
2943 | break; | |
9ba075a6 | 2944 | case MSR_MTRRcap: |
9ba075a6 | 2945 | case 0x200 ... 0x2ff: |
ff53604b | 2946 | return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); |
15c4a640 | 2947 | case 0xcd: /* fsb frequency */ |
609e36d3 | 2948 | msr_info->data = 3; |
15c4a640 | 2949 | break; |
7b914098 JS |
2950 | /* |
2951 | * MSR_EBC_FREQUENCY_ID | |
2952 | * Conservative value valid for even the basic CPU models. | |
2953 | * Models 0,1: 000 in bits 23:21 indicating a bus speed of | |
2954 | * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, | |
2955 | * and 266MHz for model 3, or 4. Set Core Clock | |
2956 | * Frequency to System Bus Frequency Ratio to 1 (bits | |
2957 | * 31:24) even though these are only valid for CPU | |
2958 | * models > 2, however guests may end up dividing or | |
2959 | * multiplying by zero otherwise. | |
2960 | */ | |
2961 | case MSR_EBC_FREQUENCY_ID: | |
609e36d3 | 2962 | msr_info->data = 1 << 24; |
7b914098 | 2963 | break; |
15c4a640 | 2964 | case MSR_IA32_APICBASE: |
609e36d3 | 2965 | msr_info->data = kvm_get_apic_base(vcpu); |
15c4a640 | 2966 | break; |
0105d1a5 | 2967 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
609e36d3 | 2968 | return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); |
0105d1a5 | 2969 | break; |
a3e06bbe | 2970 | case MSR_IA32_TSCDEADLINE: |
609e36d3 | 2971 | msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); |
a3e06bbe | 2972 | break; |
ba904635 | 2973 | case MSR_IA32_TSC_ADJUST: |
609e36d3 | 2974 | msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; |
ba904635 | 2975 | break; |
15c4a640 | 2976 | case MSR_IA32_MISC_ENABLE: |
609e36d3 | 2977 | msr_info->data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 2978 | break; |
64d60670 PB |
2979 | case MSR_IA32_SMBASE: |
2980 | if (!msr_info->host_initiated) | |
2981 | return 1; | |
2982 | msr_info->data = vcpu->arch.smbase; | |
15c4a640 | 2983 | break; |
52797bf9 LA |
2984 | case MSR_SMI_COUNT: |
2985 | msr_info->data = vcpu->arch.smi_count; | |
2986 | break; | |
847f0ad8 AG |
2987 | case MSR_IA32_PERF_STATUS: |
2988 | /* TSC increment by tick */ | |
609e36d3 | 2989 | msr_info->data = 1000ULL; |
847f0ad8 | 2990 | /* CPU multiplier */ |
b0996ae4 | 2991 | msr_info->data |= (((uint64_t)4ULL) << 40); |
847f0ad8 | 2992 | break; |
15c4a640 | 2993 | case MSR_EFER: |
609e36d3 | 2994 | msr_info->data = vcpu->arch.efer; |
15c4a640 | 2995 | break; |
18068523 | 2996 | case MSR_KVM_WALL_CLOCK: |
11c6bffa | 2997 | case MSR_KVM_WALL_CLOCK_NEW: |
609e36d3 | 2998 | msr_info->data = vcpu->kvm->arch.wall_clock; |
18068523 GOC |
2999 | break; |
3000 | case MSR_KVM_SYSTEM_TIME: | |
11c6bffa | 3001 | case MSR_KVM_SYSTEM_TIME_NEW: |
609e36d3 | 3002 | msr_info->data = vcpu->arch.time; |
18068523 | 3003 | break; |
344d9588 | 3004 | case MSR_KVM_ASYNC_PF_EN: |
609e36d3 | 3005 | msr_info->data = vcpu->arch.apf.msr_val; |
344d9588 | 3006 | break; |
c9aaa895 | 3007 | case MSR_KVM_STEAL_TIME: |
609e36d3 | 3008 | msr_info->data = vcpu->arch.st.msr_val; |
c9aaa895 | 3009 | break; |
1d92128f | 3010 | case MSR_KVM_PV_EOI_EN: |
609e36d3 | 3011 | msr_info->data = vcpu->arch.pv_eoi.msr_val; |
1d92128f | 3012 | break; |
2d5ba19b MT |
3013 | case MSR_KVM_POLL_CONTROL: |
3014 | msr_info->data = vcpu->arch.msr_kvm_poll_control; | |
3015 | break; | |
890ca9ae HY |
3016 | case MSR_IA32_P5_MC_ADDR: |
3017 | case MSR_IA32_P5_MC_TYPE: | |
3018 | case MSR_IA32_MCG_CAP: | |
3019 | case MSR_IA32_MCG_CTL: | |
3020 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 3021 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
44883f01 PB |
3022 | return get_msr_mce(vcpu, msr_info->index, &msr_info->data, |
3023 | msr_info->host_initiated); | |
84e0cefa JS |
3024 | case MSR_K7_CLK_CTL: |
3025 | /* | |
3026 | * Provide expected ramp-up count for K7. All other | |
3027 | * are set to zero, indicating minimum divisors for | |
3028 | * every field. | |
3029 | * | |
3030 | * This prevents guest kernels on AMD host with CPU | |
3031 | * type 6, model 8 and higher from exploding due to | |
3032 | * the rdmsr failing. | |
3033 | */ | |
609e36d3 | 3034 | msr_info->data = 0x20000000; |
84e0cefa | 3035 | break; |
55cd8e5a | 3036 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
e7d9513b AS |
3037 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
3038 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 3039 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
3040 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
3041 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
3042 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
e83d5887 | 3043 | return kvm_hv_get_msr_common(vcpu, |
44883f01 PB |
3044 | msr_info->index, &msr_info->data, |
3045 | msr_info->host_initiated); | |
55cd8e5a | 3046 | break; |
91c9c3ed | 3047 | case MSR_IA32_BBL_CR_CTL3: |
3048 | /* This legacy MSR exists but isn't fully documented in current | |
3049 | * silicon. It is however accessed by winxp in very narrow | |
3050 | * scenarios where it sets bit #19, itself documented as | |
3051 | * a "reserved" bit. Best effort attempt to source coherent | |
3052 | * read data here should the balance of the register be | |
3053 | * interpreted by the guest: | |
3054 | * | |
3055 | * L2 cache control register 3: 64GB range, 256KB size, | |
3056 | * enabled, latency 0x1, configured | |
3057 | */ | |
609e36d3 | 3058 | msr_info->data = 0xbe702111; |
91c9c3ed | 3059 | break; |
2b036c6b | 3060 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 3061 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 3062 | return 1; |
609e36d3 | 3063 | msr_info->data = vcpu->arch.osvw.length; |
2b036c6b BO |
3064 | break; |
3065 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 3066 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 3067 | return 1; |
609e36d3 | 3068 | msr_info->data = vcpu->arch.osvw.status; |
2b036c6b | 3069 | break; |
db2336a8 | 3070 | case MSR_PLATFORM_INFO: |
6fbbde9a DS |
3071 | if (!msr_info->host_initiated && |
3072 | !vcpu->kvm->arch.guest_can_read_msr_platform_info) | |
3073 | return 1; | |
db2336a8 KH |
3074 | msr_info->data = vcpu->arch.msr_platform_info; |
3075 | break; | |
3076 | case MSR_MISC_FEATURES_ENABLES: | |
3077 | msr_info->data = vcpu->arch.msr_misc_features_enables; | |
3078 | break; | |
191c8137 BP |
3079 | case MSR_K7_HWCR: |
3080 | msr_info->data = vcpu->arch.msr_hwcr; | |
3081 | break; | |
15c4a640 | 3082 | default: |
c6702c9d | 3083 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
609e36d3 | 3084 | return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); |
ed85c068 | 3085 | if (!ignore_msrs) { |
ae0f5499 BD |
3086 | vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n", |
3087 | msr_info->index); | |
ed85c068 AP |
3088 | return 1; |
3089 | } else { | |
fab0aa3b EM |
3090 | if (report_ignored_msrs) |
3091 | vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", | |
3092 | msr_info->index); | |
609e36d3 | 3093 | msr_info->data = 0; |
ed85c068 AP |
3094 | } |
3095 | break; | |
15c4a640 | 3096 | } |
15c4a640 CO |
3097 | return 0; |
3098 | } | |
3099 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
3100 | ||
313a3dc7 CO |
3101 | /* |
3102 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
3103 | * | |
3104 | * @return number of msrs set successfully. | |
3105 | */ | |
3106 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
3107 | struct kvm_msr_entry *entries, | |
3108 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
3109 | unsigned index, u64 *data)) | |
3110 | { | |
801e459a | 3111 | int i; |
313a3dc7 | 3112 | |
313a3dc7 CO |
3113 | for (i = 0; i < msrs->nmsrs; ++i) |
3114 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
3115 | break; | |
3116 | ||
313a3dc7 CO |
3117 | return i; |
3118 | } | |
3119 | ||
3120 | /* | |
3121 | * Read or write a bunch of msrs. Parameters are user addresses. | |
3122 | * | |
3123 | * @return number of msrs set successfully. | |
3124 | */ | |
3125 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
3126 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
3127 | unsigned index, u64 *data), | |
3128 | int writeback) | |
3129 | { | |
3130 | struct kvm_msrs msrs; | |
3131 | struct kvm_msr_entry *entries; | |
3132 | int r, n; | |
3133 | unsigned size; | |
3134 | ||
3135 | r = -EFAULT; | |
0e96f31e | 3136 | if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) |
313a3dc7 CO |
3137 | goto out; |
3138 | ||
3139 | r = -E2BIG; | |
3140 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
3141 | goto out; | |
3142 | ||
313a3dc7 | 3143 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; |
ff5c2c03 SL |
3144 | entries = memdup_user(user_msrs->entries, size); |
3145 | if (IS_ERR(entries)) { | |
3146 | r = PTR_ERR(entries); | |
313a3dc7 | 3147 | goto out; |
ff5c2c03 | 3148 | } |
313a3dc7 CO |
3149 | |
3150 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
3151 | if (r < 0) | |
3152 | goto out_free; | |
3153 | ||
3154 | r = -EFAULT; | |
3155 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
3156 | goto out_free; | |
3157 | ||
3158 | r = n; | |
3159 | ||
3160 | out_free: | |
7a73c028 | 3161 | kfree(entries); |
313a3dc7 CO |
3162 | out: |
3163 | return r; | |
3164 | } | |
3165 | ||
4d5422ce WL |
3166 | static inline bool kvm_can_mwait_in_guest(void) |
3167 | { | |
3168 | return boot_cpu_has(X86_FEATURE_MWAIT) && | |
8e9b29b6 KA |
3169 | !boot_cpu_has_bug(X86_BUG_MONITOR) && |
3170 | boot_cpu_has(X86_FEATURE_ARAT); | |
4d5422ce WL |
3171 | } |
3172 | ||
784aa3d7 | 3173 | int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) |
018d00d2 | 3174 | { |
4d5422ce | 3175 | int r = 0; |
018d00d2 ZX |
3176 | |
3177 | switch (ext) { | |
3178 | case KVM_CAP_IRQCHIP: | |
3179 | case KVM_CAP_HLT: | |
3180 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 3181 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 3182 | case KVM_CAP_EXT_CPUID: |
9c15bb1d | 3183 | case KVM_CAP_EXT_EMUL_CPUID: |
c8076604 | 3184 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 3185 | case KVM_CAP_PIT: |
a28e4f5a | 3186 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 3187 | case KVM_CAP_MP_STATE: |
ed848624 | 3188 | case KVM_CAP_SYNC_MMU: |
a355c85c | 3189 | case KVM_CAP_USER_NMI: |
52d939a0 | 3190 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 3191 | case KVM_CAP_IRQ_INJECT_STATUS: |
d34e6b17 | 3192 | case KVM_CAP_IOEVENTFD: |
f848a5a8 | 3193 | case KVM_CAP_IOEVENTFD_NO_LENGTH: |
c5ff41ce | 3194 | case KVM_CAP_PIT2: |
e9f42757 | 3195 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 3196 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
ffde22ac | 3197 | case KVM_CAP_XEN_HVM: |
3cfc3092 | 3198 | case KVM_CAP_VCPU_EVENTS: |
55cd8e5a | 3199 | case KVM_CAP_HYPERV: |
10388a07 | 3200 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 3201 | case KVM_CAP_HYPERV_SPIN: |
5c919412 | 3202 | case KVM_CAP_HYPERV_SYNIC: |
efc479e6 | 3203 | case KVM_CAP_HYPERV_SYNIC2: |
d3457c87 | 3204 | case KVM_CAP_HYPERV_VP_INDEX: |
faeb7833 | 3205 | case KVM_CAP_HYPERV_EVENTFD: |
c1aea919 | 3206 | case KVM_CAP_HYPERV_TLBFLUSH: |
214ff83d | 3207 | case KVM_CAP_HYPERV_SEND_IPI: |
57b119da | 3208 | case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: |
2bc39970 | 3209 | case KVM_CAP_HYPERV_CPUID: |
ab9f4ecb | 3210 | case KVM_CAP_PCI_SEGMENT: |
a1efbe77 | 3211 | case KVM_CAP_DEBUGREGS: |
d2be1651 | 3212 | case KVM_CAP_X86_ROBUST_SINGLESTEP: |
2d5b5a66 | 3213 | case KVM_CAP_XSAVE: |
344d9588 | 3214 | case KVM_CAP_ASYNC_PF: |
92a1f12d | 3215 | case KVM_CAP_GET_TSC_KHZ: |
1c0b28c2 | 3216 | case KVM_CAP_KVMCLOCK_CTRL: |
4d8b81ab | 3217 | case KVM_CAP_READONLY_MEM: |
5f66b620 | 3218 | case KVM_CAP_HYPERV_TIME: |
100943c5 | 3219 | case KVM_CAP_IOAPIC_POLARITY_IGNORED: |
defcf51f | 3220 | case KVM_CAP_TSC_DEADLINE_TIMER: |
90de4a18 | 3221 | case KVM_CAP_DISABLE_QUIRKS: |
d71ba788 | 3222 | case KVM_CAP_SET_BOOT_CPU_ID: |
49df6397 | 3223 | case KVM_CAP_SPLIT_IRQCHIP: |
460df4c1 | 3224 | case KVM_CAP_IMMEDIATE_EXIT: |
66bb8a06 | 3225 | case KVM_CAP_PMU_EVENT_FILTER: |
801e459a | 3226 | case KVM_CAP_GET_MSR_FEATURES: |
6fbbde9a | 3227 | case KVM_CAP_MSR_PLATFORM_INFO: |
c4f55198 | 3228 | case KVM_CAP_EXCEPTION_PAYLOAD: |
018d00d2 ZX |
3229 | r = 1; |
3230 | break; | |
01643c51 KH |
3231 | case KVM_CAP_SYNC_REGS: |
3232 | r = KVM_SYNC_X86_VALID_FIELDS; | |
3233 | break; | |
e3fd9a93 PB |
3234 | case KVM_CAP_ADJUST_CLOCK: |
3235 | r = KVM_CLOCK_TSC_STABLE; | |
3236 | break; | |
4d5422ce | 3237 | case KVM_CAP_X86_DISABLE_EXITS: |
b5170063 WL |
3238 | r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE | |
3239 | KVM_X86_DISABLE_EXITS_CSTATE; | |
4d5422ce WL |
3240 | if(kvm_can_mwait_in_guest()) |
3241 | r |= KVM_X86_DISABLE_EXITS_MWAIT; | |
668fffa3 | 3242 | break; |
6d396b55 PB |
3243 | case KVM_CAP_X86_SMM: |
3244 | /* SMBASE is usually relocated above 1M on modern chipsets, | |
3245 | * and SMM handlers might indeed rely on 4G segment limits, | |
3246 | * so do not report SMM to be available if real mode is | |
3247 | * emulated via vm86 mode. Still, do not go to great lengths | |
3248 | * to avoid userspace's usage of the feature, because it is a | |
3249 | * fringe case that is not enabled except via specific settings | |
3250 | * of the module parameters. | |
3251 | */ | |
bc226f07 | 3252 | r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE); |
6d396b55 | 3253 | break; |
774ead3a AK |
3254 | case KVM_CAP_VAPIC: |
3255 | r = !kvm_x86_ops->cpu_has_accelerated_tpr(); | |
3256 | break; | |
f725230a | 3257 | case KVM_CAP_NR_VCPUS: |
8c3ba334 SL |
3258 | r = KVM_SOFT_MAX_VCPUS; |
3259 | break; | |
3260 | case KVM_CAP_MAX_VCPUS: | |
f725230a AK |
3261 | r = KVM_MAX_VCPUS; |
3262 | break; | |
a86cb413 TH |
3263 | case KVM_CAP_MAX_VCPU_ID: |
3264 | r = KVM_MAX_VCPU_ID; | |
3265 | break; | |
a68a6a72 MT |
3266 | case KVM_CAP_PV_MMU: /* obsolete */ |
3267 | r = 0; | |
2f333bcb | 3268 | break; |
890ca9ae HY |
3269 | case KVM_CAP_MCE: |
3270 | r = KVM_MAX_MCE_BANKS; | |
3271 | break; | |
2d5b5a66 | 3272 | case KVM_CAP_XCRS: |
d366bf7e | 3273 | r = boot_cpu_has(X86_FEATURE_XSAVE); |
2d5b5a66 | 3274 | break; |
92a1f12d JR |
3275 | case KVM_CAP_TSC_CONTROL: |
3276 | r = kvm_has_tsc_control; | |
3277 | break; | |
37131313 RK |
3278 | case KVM_CAP_X2APIC_API: |
3279 | r = KVM_X2APIC_API_VALID_FLAGS; | |
3280 | break; | |
8fcc4b59 JM |
3281 | case KVM_CAP_NESTED_STATE: |
3282 | r = kvm_x86_ops->get_nested_state ? | |
be43c440 | 3283 | kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0; |
8fcc4b59 | 3284 | break; |
018d00d2 | 3285 | default: |
018d00d2 ZX |
3286 | break; |
3287 | } | |
3288 | return r; | |
3289 | ||
3290 | } | |
3291 | ||
043405e1 CO |
3292 | long kvm_arch_dev_ioctl(struct file *filp, |
3293 | unsigned int ioctl, unsigned long arg) | |
3294 | { | |
3295 | void __user *argp = (void __user *)arg; | |
3296 | long r; | |
3297 | ||
3298 | switch (ioctl) { | |
3299 | case KVM_GET_MSR_INDEX_LIST: { | |
3300 | struct kvm_msr_list __user *user_msr_list = argp; | |
3301 | struct kvm_msr_list msr_list; | |
3302 | unsigned n; | |
3303 | ||
3304 | r = -EFAULT; | |
0e96f31e | 3305 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) |
043405e1 CO |
3306 | goto out; |
3307 | n = msr_list.nmsrs; | |
62ef68bb | 3308 | msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; |
0e96f31e | 3309 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) |
043405e1 CO |
3310 | goto out; |
3311 | r = -E2BIG; | |
e125e7b6 | 3312 | if (n < msr_list.nmsrs) |
043405e1 CO |
3313 | goto out; |
3314 | r = -EFAULT; | |
3315 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
3316 | num_msrs_to_save * sizeof(u32))) | |
3317 | goto out; | |
e125e7b6 | 3318 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 | 3319 | &emulated_msrs, |
62ef68bb | 3320 | num_emulated_msrs * sizeof(u32))) |
043405e1 CO |
3321 | goto out; |
3322 | r = 0; | |
3323 | break; | |
3324 | } | |
9c15bb1d BP |
3325 | case KVM_GET_SUPPORTED_CPUID: |
3326 | case KVM_GET_EMULATED_CPUID: { | |
674eea0f AK |
3327 | struct kvm_cpuid2 __user *cpuid_arg = argp; |
3328 | struct kvm_cpuid2 cpuid; | |
3329 | ||
3330 | r = -EFAULT; | |
0e96f31e | 3331 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
674eea0f | 3332 | goto out; |
9c15bb1d BP |
3333 | |
3334 | r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, | |
3335 | ioctl); | |
674eea0f AK |
3336 | if (r) |
3337 | goto out; | |
3338 | ||
3339 | r = -EFAULT; | |
0e96f31e | 3340 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) |
674eea0f AK |
3341 | goto out; |
3342 | r = 0; | |
3343 | break; | |
3344 | } | |
890ca9ae | 3345 | case KVM_X86_GET_MCE_CAP_SUPPORTED: { |
890ca9ae | 3346 | r = -EFAULT; |
c45dcc71 AR |
3347 | if (copy_to_user(argp, &kvm_mce_cap_supported, |
3348 | sizeof(kvm_mce_cap_supported))) | |
890ca9ae HY |
3349 | goto out; |
3350 | r = 0; | |
3351 | break; | |
801e459a TL |
3352 | case KVM_GET_MSR_FEATURE_INDEX_LIST: { |
3353 | struct kvm_msr_list __user *user_msr_list = argp; | |
3354 | struct kvm_msr_list msr_list; | |
3355 | unsigned int n; | |
3356 | ||
3357 | r = -EFAULT; | |
3358 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) | |
3359 | goto out; | |
3360 | n = msr_list.nmsrs; | |
3361 | msr_list.nmsrs = num_msr_based_features; | |
3362 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) | |
3363 | goto out; | |
3364 | r = -E2BIG; | |
3365 | if (n < msr_list.nmsrs) | |
3366 | goto out; | |
3367 | r = -EFAULT; | |
3368 | if (copy_to_user(user_msr_list->indices, &msr_based_features, | |
3369 | num_msr_based_features * sizeof(u32))) | |
3370 | goto out; | |
3371 | r = 0; | |
3372 | break; | |
3373 | } | |
3374 | case KVM_GET_MSRS: | |
3375 | r = msr_io(NULL, argp, do_get_msr_feature, 1); | |
3376 | break; | |
890ca9ae | 3377 | } |
043405e1 CO |
3378 | default: |
3379 | r = -EINVAL; | |
3380 | } | |
3381 | out: | |
3382 | return r; | |
3383 | } | |
3384 | ||
f5f48ee1 SY |
3385 | static void wbinvd_ipi(void *garbage) |
3386 | { | |
3387 | wbinvd(); | |
3388 | } | |
3389 | ||
3390 | static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
3391 | { | |
e0f0bbc5 | 3392 | return kvm_arch_has_noncoherent_dma(vcpu->kvm); |
f5f48ee1 SY |
3393 | } |
3394 | ||
313a3dc7 CO |
3395 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
3396 | { | |
f5f48ee1 SY |
3397 | /* Address WBINVD may be executed by guest */ |
3398 | if (need_emulate_wbinvd(vcpu)) { | |
3399 | if (kvm_x86_ops->has_wbinvd_exit()) | |
3400 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
3401 | else if (vcpu->cpu != -1 && vcpu->cpu != cpu) | |
3402 | smp_call_function_single(vcpu->cpu, | |
3403 | wbinvd_ipi, NULL, 1); | |
3404 | } | |
3405 | ||
313a3dc7 | 3406 | kvm_x86_ops->vcpu_load(vcpu, cpu); |
8f6055cb | 3407 | |
e7517324 WL |
3408 | fpregs_assert_state_consistent(); |
3409 | if (test_thread_flag(TIF_NEED_FPU_LOAD)) | |
3410 | switch_fpu_return(); | |
3411 | ||
0dd6a6ed ZA |
3412 | /* Apply any externally detected TSC adjustments (due to suspend) */ |
3413 | if (unlikely(vcpu->arch.tsc_offset_adjustment)) { | |
3414 | adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); | |
3415 | vcpu->arch.tsc_offset_adjustment = 0; | |
105b21bb | 3416 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed | 3417 | } |
8f6055cb | 3418 | |
b0c39dc6 | 3419 | if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { |
6f526ec5 | 3420 | s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : |
4ea1636b | 3421 | rdtsc() - vcpu->arch.last_host_tsc; |
e48672fa ZA |
3422 | if (tsc_delta < 0) |
3423 | mark_tsc_unstable("KVM discovered backwards TSC"); | |
ce7a058a | 3424 | |
b0c39dc6 | 3425 | if (kvm_check_tsc_unstable()) { |
07c1419a | 3426 | u64 offset = kvm_compute_tsc_offset(vcpu, |
b183aa58 | 3427 | vcpu->arch.last_guest_tsc); |
a545ab6a | 3428 | kvm_vcpu_write_tsc_offset(vcpu, offset); |
c285545f | 3429 | vcpu->arch.tsc_catchup = 1; |
c285545f | 3430 | } |
a749e247 PB |
3431 | |
3432 | if (kvm_lapic_hv_timer_in_use(vcpu)) | |
3433 | kvm_lapic_restart_hv_timer(vcpu); | |
3434 | ||
d98d07ca MT |
3435 | /* |
3436 | * On a host with synchronized TSC, there is no need to update | |
3437 | * kvmclock on vcpu->cpu migration | |
3438 | */ | |
3439 | if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) | |
0061d53d | 3440 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
c285545f | 3441 | if (vcpu->cpu != cpu) |
1bd2009e | 3442 | kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); |
e48672fa | 3443 | vcpu->cpu = cpu; |
6b7d7e76 | 3444 | } |
c9aaa895 | 3445 | |
c9aaa895 | 3446 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
313a3dc7 CO |
3447 | } |
3448 | ||
0b9f6c46 PX |
3449 | static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) |
3450 | { | |
3451 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) | |
3452 | return; | |
3453 | ||
fa55eedd | 3454 | vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED; |
0b9f6c46 | 3455 | |
4e335d9e | 3456 | kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime, |
0b9f6c46 PX |
3457 | &vcpu->arch.st.steal.preempted, |
3458 | offsetof(struct kvm_steal_time, preempted), | |
3459 | sizeof(vcpu->arch.st.steal.preempted)); | |
3460 | } | |
3461 | ||
313a3dc7 CO |
3462 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) |
3463 | { | |
cc0d907c | 3464 | int idx; |
de63ad4c LM |
3465 | |
3466 | if (vcpu->preempted) | |
3467 | vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu); | |
3468 | ||
931f261b AA |
3469 | /* |
3470 | * Disable page faults because we're in atomic context here. | |
3471 | * kvm_write_guest_offset_cached() would call might_fault() | |
3472 | * that relies on pagefault_disable() to tell if there's a | |
3473 | * bug. NOTE: the write to guest memory may not go through if | |
3474 | * during postcopy live migration or if there's heavy guest | |
3475 | * paging. | |
3476 | */ | |
3477 | pagefault_disable(); | |
cc0d907c AA |
3478 | /* |
3479 | * kvm_memslots() will be called by | |
3480 | * kvm_write_guest_offset_cached() so take the srcu lock. | |
3481 | */ | |
3482 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
0b9f6c46 | 3483 | kvm_steal_time_set_preempted(vcpu); |
cc0d907c | 3484 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
931f261b | 3485 | pagefault_enable(); |
02daab21 | 3486 | kvm_x86_ops->vcpu_put(vcpu); |
4ea1636b | 3487 | vcpu->arch.last_host_tsc = rdtsc(); |
efdab992 | 3488 | /* |
f9dcf08e RK |
3489 | * If userspace has set any breakpoints or watchpoints, dr6 is restored |
3490 | * on every vmexit, but if not, we might have a stale dr6 from the | |
3491 | * guest. do_debug expects dr6 to be cleared after it runs, do the same. | |
efdab992 | 3492 | */ |
f9dcf08e | 3493 | set_debugreg(0, 6); |
313a3dc7 CO |
3494 | } |
3495 | ||
313a3dc7 CO |
3496 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
3497 | struct kvm_lapic_state *s) | |
3498 | { | |
fa59cc00 | 3499 | if (vcpu->arch.apicv_active) |
d62caabb AS |
3500 | kvm_x86_ops->sync_pir_to_irr(vcpu); |
3501 | ||
a92e2543 | 3502 | return kvm_apic_get_state(vcpu, s); |
313a3dc7 CO |
3503 | } |
3504 | ||
3505 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
3506 | struct kvm_lapic_state *s) | |
3507 | { | |
a92e2543 RK |
3508 | int r; |
3509 | ||
3510 | r = kvm_apic_set_state(vcpu, s); | |
3511 | if (r) | |
3512 | return r; | |
cb142eb7 | 3513 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
3514 | |
3515 | return 0; | |
3516 | } | |
3517 | ||
127a457a MG |
3518 | static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) |
3519 | { | |
3520 | return (!lapic_in_kernel(vcpu) || | |
3521 | kvm_apic_accept_pic_intr(vcpu)); | |
3522 | } | |
3523 | ||
782d422b MG |
3524 | /* |
3525 | * if userspace requested an interrupt window, check that the | |
3526 | * interrupt window is open. | |
3527 | * | |
3528 | * No need to exit to userspace if we already have an interrupt queued. | |
3529 | */ | |
3530 | static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) | |
3531 | { | |
3532 | return kvm_arch_interrupt_allowed(vcpu) && | |
3533 | !kvm_cpu_has_interrupt(vcpu) && | |
3534 | !kvm_event_needs_reinjection(vcpu) && | |
3535 | kvm_cpu_accept_dm_intr(vcpu); | |
3536 | } | |
3537 | ||
f77bc6a4 ZX |
3538 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
3539 | struct kvm_interrupt *irq) | |
3540 | { | |
02cdb50f | 3541 | if (irq->irq >= KVM_NR_INTERRUPTS) |
f77bc6a4 | 3542 | return -EINVAL; |
1c1a9ce9 SR |
3543 | |
3544 | if (!irqchip_in_kernel(vcpu->kvm)) { | |
3545 | kvm_queue_interrupt(vcpu, irq->irq, false); | |
3546 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
3547 | return 0; | |
3548 | } | |
3549 | ||
3550 | /* | |
3551 | * With in-kernel LAPIC, we only use this to inject EXTINT, so | |
3552 | * fail for in-kernel 8259. | |
3553 | */ | |
3554 | if (pic_in_kernel(vcpu->kvm)) | |
f77bc6a4 | 3555 | return -ENXIO; |
f77bc6a4 | 3556 | |
1c1a9ce9 SR |
3557 | if (vcpu->arch.pending_external_vector != -1) |
3558 | return -EEXIST; | |
f77bc6a4 | 3559 | |
1c1a9ce9 | 3560 | vcpu->arch.pending_external_vector = irq->irq; |
934bf653 | 3561 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f77bc6a4 ZX |
3562 | return 0; |
3563 | } | |
3564 | ||
c4abb7c9 JK |
3565 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
3566 | { | |
c4abb7c9 | 3567 | kvm_inject_nmi(vcpu); |
c4abb7c9 JK |
3568 | |
3569 | return 0; | |
3570 | } | |
3571 | ||
f077825a PB |
3572 | static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) |
3573 | { | |
64d60670 PB |
3574 | kvm_make_request(KVM_REQ_SMI, vcpu); |
3575 | ||
f077825a PB |
3576 | return 0; |
3577 | } | |
3578 | ||
b209749f AK |
3579 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
3580 | struct kvm_tpr_access_ctl *tac) | |
3581 | { | |
3582 | if (tac->flags) | |
3583 | return -EINVAL; | |
3584 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
3585 | return 0; | |
3586 | } | |
3587 | ||
890ca9ae HY |
3588 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
3589 | u64 mcg_cap) | |
3590 | { | |
3591 | int r; | |
3592 | unsigned bank_num = mcg_cap & 0xff, bank; | |
3593 | ||
3594 | r = -EINVAL; | |
a9e38c3e | 3595 | if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) |
890ca9ae | 3596 | goto out; |
c45dcc71 | 3597 | if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) |
890ca9ae HY |
3598 | goto out; |
3599 | r = 0; | |
3600 | vcpu->arch.mcg_cap = mcg_cap; | |
3601 | /* Init IA32_MCG_CTL to all 1s */ | |
3602 | if (mcg_cap & MCG_CTL_P) | |
3603 | vcpu->arch.mcg_ctl = ~(u64)0; | |
3604 | /* Init IA32_MCi_CTL to all 1s */ | |
3605 | for (bank = 0; bank < bank_num; bank++) | |
3606 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
c45dcc71 | 3607 | |
92735b1b | 3608 | kvm_x86_ops->setup_mce(vcpu); |
890ca9ae HY |
3609 | out: |
3610 | return r; | |
3611 | } | |
3612 | ||
3613 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
3614 | struct kvm_x86_mce *mce) | |
3615 | { | |
3616 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
3617 | unsigned bank_num = mcg_cap & 0xff; | |
3618 | u64 *banks = vcpu->arch.mce_banks; | |
3619 | ||
3620 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
3621 | return -EINVAL; | |
3622 | /* | |
3623 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
3624 | * reporting is disabled | |
3625 | */ | |
3626 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
3627 | vcpu->arch.mcg_ctl != ~(u64)0) | |
3628 | return 0; | |
3629 | banks += 4 * mce->bank; | |
3630 | /* | |
3631 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
3632 | * reporting is disabled for the bank | |
3633 | */ | |
3634 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
3635 | return 0; | |
3636 | if (mce->status & MCI_STATUS_UC) { | |
3637 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
fc78f519 | 3638 | !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { |
a8eeb04a | 3639 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
890ca9ae HY |
3640 | return 0; |
3641 | } | |
3642 | if (banks[1] & MCI_STATUS_VAL) | |
3643 | mce->status |= MCI_STATUS_OVER; | |
3644 | banks[2] = mce->addr; | |
3645 | banks[3] = mce->misc; | |
3646 | vcpu->arch.mcg_status = mce->mcg_status; | |
3647 | banks[1] = mce->status; | |
3648 | kvm_queue_exception(vcpu, MC_VECTOR); | |
3649 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
3650 | || !(banks[1] & MCI_STATUS_UC)) { | |
3651 | if (banks[1] & MCI_STATUS_VAL) | |
3652 | mce->status |= MCI_STATUS_OVER; | |
3653 | banks[2] = mce->addr; | |
3654 | banks[3] = mce->misc; | |
3655 | banks[1] = mce->status; | |
3656 | } else | |
3657 | banks[1] |= MCI_STATUS_OVER; | |
3658 | return 0; | |
3659 | } | |
3660 | ||
3cfc3092 JK |
3661 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
3662 | struct kvm_vcpu_events *events) | |
3663 | { | |
7460fb4a | 3664 | process_nmi(vcpu); |
59073aaf | 3665 | |
664f8e26 | 3666 | /* |
59073aaf JM |
3667 | * The API doesn't provide the instruction length for software |
3668 | * exceptions, so don't report them. As long as the guest RIP | |
3669 | * isn't advanced, we should expect to encounter the exception | |
3670 | * again. | |
664f8e26 | 3671 | */ |
59073aaf JM |
3672 | if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { |
3673 | events->exception.injected = 0; | |
3674 | events->exception.pending = 0; | |
3675 | } else { | |
3676 | events->exception.injected = vcpu->arch.exception.injected; | |
3677 | events->exception.pending = vcpu->arch.exception.pending; | |
3678 | /* | |
3679 | * For ABI compatibility, deliberately conflate | |
3680 | * pending and injected exceptions when | |
3681 | * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. | |
3682 | */ | |
3683 | if (!vcpu->kvm->arch.exception_payload_enabled) | |
3684 | events->exception.injected |= | |
3685 | vcpu->arch.exception.pending; | |
3686 | } | |
3cfc3092 JK |
3687 | events->exception.nr = vcpu->arch.exception.nr; |
3688 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
3689 | events->exception.error_code = vcpu->arch.exception.error_code; | |
59073aaf JM |
3690 | events->exception_has_payload = vcpu->arch.exception.has_payload; |
3691 | events->exception_payload = vcpu->arch.exception.payload; | |
3cfc3092 | 3692 | |
03b82a30 | 3693 | events->interrupt.injected = |
04140b41 | 3694 | vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; |
3cfc3092 | 3695 | events->interrupt.nr = vcpu->arch.interrupt.nr; |
03b82a30 | 3696 | events->interrupt.soft = 0; |
37ccdcbe | 3697 | events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); |
3cfc3092 JK |
3698 | |
3699 | events->nmi.injected = vcpu->arch.nmi_injected; | |
7460fb4a | 3700 | events->nmi.pending = vcpu->arch.nmi_pending != 0; |
3cfc3092 | 3701 | events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); |
97e69aa6 | 3702 | events->nmi.pad = 0; |
3cfc3092 | 3703 | |
66450a21 | 3704 | events->sipi_vector = 0; /* never valid when reporting to user space */ |
3cfc3092 | 3705 | |
f077825a PB |
3706 | events->smi.smm = is_smm(vcpu); |
3707 | events->smi.pending = vcpu->arch.smi_pending; | |
3708 | events->smi.smm_inside_nmi = | |
3709 | !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); | |
3710 | events->smi.latched_init = kvm_lapic_latched_init(vcpu); | |
3711 | ||
dab4b911 | 3712 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
f077825a PB |
3713 | | KVM_VCPUEVENT_VALID_SHADOW |
3714 | | KVM_VCPUEVENT_VALID_SMM); | |
59073aaf JM |
3715 | if (vcpu->kvm->arch.exception_payload_enabled) |
3716 | events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; | |
3717 | ||
97e69aa6 | 3718 | memset(&events->reserved, 0, sizeof(events->reserved)); |
3cfc3092 JK |
3719 | } |
3720 | ||
c5833c7a | 3721 | static void kvm_smm_changed(struct kvm_vcpu *vcpu); |
6ef4e07e | 3722 | |
3cfc3092 JK |
3723 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, |
3724 | struct kvm_vcpu_events *events) | |
3725 | { | |
dab4b911 | 3726 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 | 3727 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
f077825a | 3728 | | KVM_VCPUEVENT_VALID_SHADOW |
59073aaf JM |
3729 | | KVM_VCPUEVENT_VALID_SMM |
3730 | | KVM_VCPUEVENT_VALID_PAYLOAD)) | |
3cfc3092 JK |
3731 | return -EINVAL; |
3732 | ||
59073aaf JM |
3733 | if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { |
3734 | if (!vcpu->kvm->arch.exception_payload_enabled) | |
3735 | return -EINVAL; | |
3736 | if (events->exception.pending) | |
3737 | events->exception.injected = 0; | |
3738 | else | |
3739 | events->exception_has_payload = 0; | |
3740 | } else { | |
3741 | events->exception.pending = 0; | |
3742 | events->exception_has_payload = 0; | |
3743 | } | |
3744 | ||
3745 | if ((events->exception.injected || events->exception.pending) && | |
3746 | (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) | |
78e546c8 PB |
3747 | return -EINVAL; |
3748 | ||
28bf2888 DH |
3749 | /* INITs are latched while in SMM */ |
3750 | if (events->flags & KVM_VCPUEVENT_VALID_SMM && | |
3751 | (events->smi.smm || events->smi.pending) && | |
3752 | vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) | |
3753 | return -EINVAL; | |
3754 | ||
7460fb4a | 3755 | process_nmi(vcpu); |
59073aaf JM |
3756 | vcpu->arch.exception.injected = events->exception.injected; |
3757 | vcpu->arch.exception.pending = events->exception.pending; | |
3cfc3092 JK |
3758 | vcpu->arch.exception.nr = events->exception.nr; |
3759 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
3760 | vcpu->arch.exception.error_code = events->exception.error_code; | |
59073aaf JM |
3761 | vcpu->arch.exception.has_payload = events->exception_has_payload; |
3762 | vcpu->arch.exception.payload = events->exception_payload; | |
3cfc3092 | 3763 | |
04140b41 | 3764 | vcpu->arch.interrupt.injected = events->interrupt.injected; |
3cfc3092 JK |
3765 | vcpu->arch.interrupt.nr = events->interrupt.nr; |
3766 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
48005f64 JK |
3767 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) |
3768 | kvm_x86_ops->set_interrupt_shadow(vcpu, | |
3769 | events->interrupt.shadow); | |
3cfc3092 JK |
3770 | |
3771 | vcpu->arch.nmi_injected = events->nmi.injected; | |
dab4b911 JK |
3772 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) |
3773 | vcpu->arch.nmi_pending = events->nmi.pending; | |
3cfc3092 JK |
3774 | kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); |
3775 | ||
66450a21 | 3776 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && |
bce87cce | 3777 | lapic_in_kernel(vcpu)) |
66450a21 | 3778 | vcpu->arch.apic->sipi_vector = events->sipi_vector; |
3cfc3092 | 3779 | |
f077825a | 3780 | if (events->flags & KVM_VCPUEVENT_VALID_SMM) { |
c5833c7a SC |
3781 | if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) { |
3782 | if (events->smi.smm) | |
3783 | vcpu->arch.hflags |= HF_SMM_MASK; | |
3784 | else | |
3785 | vcpu->arch.hflags &= ~HF_SMM_MASK; | |
3786 | kvm_smm_changed(vcpu); | |
3787 | } | |
6ef4e07e | 3788 | |
f077825a | 3789 | vcpu->arch.smi_pending = events->smi.pending; |
f4ef1910 WL |
3790 | |
3791 | if (events->smi.smm) { | |
3792 | if (events->smi.smm_inside_nmi) | |
3793 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; | |
f077825a | 3794 | else |
f4ef1910 WL |
3795 | vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; |
3796 | if (lapic_in_kernel(vcpu)) { | |
3797 | if (events->smi.latched_init) | |
3798 | set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
3799 | else | |
3800 | clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
3801 | } | |
f077825a PB |
3802 | } |
3803 | } | |
3804 | ||
3842d135 AK |
3805 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
3806 | ||
3cfc3092 JK |
3807 | return 0; |
3808 | } | |
3809 | ||
a1efbe77 JK |
3810 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, |
3811 | struct kvm_debugregs *dbgregs) | |
3812 | { | |
73aaf249 JK |
3813 | unsigned long val; |
3814 | ||
a1efbe77 | 3815 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); |
16f8a6f9 | 3816 | kvm_get_dr(vcpu, 6, &val); |
73aaf249 | 3817 | dbgregs->dr6 = val; |
a1efbe77 JK |
3818 | dbgregs->dr7 = vcpu->arch.dr7; |
3819 | dbgregs->flags = 0; | |
97e69aa6 | 3820 | memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); |
a1efbe77 JK |
3821 | } |
3822 | ||
3823 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
3824 | struct kvm_debugregs *dbgregs) | |
3825 | { | |
3826 | if (dbgregs->flags) | |
3827 | return -EINVAL; | |
3828 | ||
d14bdb55 PB |
3829 | if (dbgregs->dr6 & ~0xffffffffull) |
3830 | return -EINVAL; | |
3831 | if (dbgregs->dr7 & ~0xffffffffull) | |
3832 | return -EINVAL; | |
3833 | ||
a1efbe77 | 3834 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); |
ae561ede | 3835 | kvm_update_dr0123(vcpu); |
a1efbe77 | 3836 | vcpu->arch.dr6 = dbgregs->dr6; |
73aaf249 | 3837 | kvm_update_dr6(vcpu); |
a1efbe77 | 3838 | vcpu->arch.dr7 = dbgregs->dr7; |
9926c9fd | 3839 | kvm_update_dr7(vcpu); |
a1efbe77 | 3840 | |
a1efbe77 JK |
3841 | return 0; |
3842 | } | |
3843 | ||
df1daba7 PB |
3844 | #define XSTATE_COMPACTION_ENABLED (1ULL << 63) |
3845 | ||
3846 | static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) | |
3847 | { | |
b666a4b6 | 3848 | struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; |
400e4b20 | 3849 | u64 xstate_bv = xsave->header.xfeatures; |
df1daba7 PB |
3850 | u64 valid; |
3851 | ||
3852 | /* | |
3853 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
3854 | * leaves 0 and 1 in the loop below. | |
3855 | */ | |
3856 | memcpy(dest, xsave, XSAVE_HDR_OFFSET); | |
3857 | ||
3858 | /* Set XSTATE_BV */ | |
00c87e9a | 3859 | xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE; |
df1daba7 PB |
3860 | *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; |
3861 | ||
3862 | /* | |
3863 | * Copy each region from the possibly compacted offset to the | |
3864 | * non-compacted offset. | |
3865 | */ | |
d91cab78 | 3866 | valid = xstate_bv & ~XFEATURE_MASK_FPSSE; |
df1daba7 | 3867 | while (valid) { |
abd16d68 SAS |
3868 | u64 xfeature_mask = valid & -valid; |
3869 | int xfeature_nr = fls64(xfeature_mask) - 1; | |
3870 | void *src = get_xsave_addr(xsave, xfeature_nr); | |
df1daba7 PB |
3871 | |
3872 | if (src) { | |
3873 | u32 size, offset, ecx, edx; | |
abd16d68 | 3874 | cpuid_count(XSTATE_CPUID, xfeature_nr, |
df1daba7 | 3875 | &size, &offset, &ecx, &edx); |
abd16d68 | 3876 | if (xfeature_nr == XFEATURE_PKRU) |
38cfd5e3 PB |
3877 | memcpy(dest + offset, &vcpu->arch.pkru, |
3878 | sizeof(vcpu->arch.pkru)); | |
3879 | else | |
3880 | memcpy(dest + offset, src, size); | |
3881 | ||
df1daba7 PB |
3882 | } |
3883 | ||
abd16d68 | 3884 | valid -= xfeature_mask; |
df1daba7 PB |
3885 | } |
3886 | } | |
3887 | ||
3888 | static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) | |
3889 | { | |
b666a4b6 | 3890 | struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; |
df1daba7 PB |
3891 | u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); |
3892 | u64 valid; | |
3893 | ||
3894 | /* | |
3895 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
3896 | * leaves 0 and 1 in the loop below. | |
3897 | */ | |
3898 | memcpy(xsave, src, XSAVE_HDR_OFFSET); | |
3899 | ||
3900 | /* Set XSTATE_BV and possibly XCOMP_BV. */ | |
400e4b20 | 3901 | xsave->header.xfeatures = xstate_bv; |
782511b0 | 3902 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
3a54450b | 3903 | xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; |
df1daba7 PB |
3904 | |
3905 | /* | |
3906 | * Copy each region from the non-compacted offset to the | |
3907 | * possibly compacted offset. | |
3908 | */ | |
d91cab78 | 3909 | valid = xstate_bv & ~XFEATURE_MASK_FPSSE; |
df1daba7 | 3910 | while (valid) { |
abd16d68 SAS |
3911 | u64 xfeature_mask = valid & -valid; |
3912 | int xfeature_nr = fls64(xfeature_mask) - 1; | |
3913 | void *dest = get_xsave_addr(xsave, xfeature_nr); | |
df1daba7 PB |
3914 | |
3915 | if (dest) { | |
3916 | u32 size, offset, ecx, edx; | |
abd16d68 | 3917 | cpuid_count(XSTATE_CPUID, xfeature_nr, |
df1daba7 | 3918 | &size, &offset, &ecx, &edx); |
abd16d68 | 3919 | if (xfeature_nr == XFEATURE_PKRU) |
38cfd5e3 PB |
3920 | memcpy(&vcpu->arch.pkru, src + offset, |
3921 | sizeof(vcpu->arch.pkru)); | |
3922 | else | |
3923 | memcpy(dest, src + offset, size); | |
ee4100da | 3924 | } |
df1daba7 | 3925 | |
abd16d68 | 3926 | valid -= xfeature_mask; |
df1daba7 PB |
3927 | } |
3928 | } | |
3929 | ||
2d5b5a66 SY |
3930 | static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, |
3931 | struct kvm_xsave *guest_xsave) | |
3932 | { | |
d366bf7e | 3933 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
df1daba7 PB |
3934 | memset(guest_xsave, 0, sizeof(struct kvm_xsave)); |
3935 | fill_xsave((u8 *) guest_xsave->region, vcpu); | |
4344ee98 | 3936 | } else { |
2d5b5a66 | 3937 | memcpy(guest_xsave->region, |
b666a4b6 | 3938 | &vcpu->arch.guest_fpu->state.fxsave, |
c47ada30 | 3939 | sizeof(struct fxregs_state)); |
2d5b5a66 | 3940 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = |
d91cab78 | 3941 | XFEATURE_MASK_FPSSE; |
2d5b5a66 SY |
3942 | } |
3943 | } | |
3944 | ||
a575813b WL |
3945 | #define XSAVE_MXCSR_OFFSET 24 |
3946 | ||
2d5b5a66 SY |
3947 | static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, |
3948 | struct kvm_xsave *guest_xsave) | |
3949 | { | |
3950 | u64 xstate_bv = | |
3951 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; | |
a575813b | 3952 | u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)]; |
2d5b5a66 | 3953 | |
d366bf7e | 3954 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
d7876f1b PB |
3955 | /* |
3956 | * Here we allow setting states that are not present in | |
3957 | * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility | |
3958 | * with old userspace. | |
3959 | */ | |
a575813b WL |
3960 | if (xstate_bv & ~kvm_supported_xcr0() || |
3961 | mxcsr & ~mxcsr_feature_mask) | |
d7876f1b | 3962 | return -EINVAL; |
df1daba7 | 3963 | load_xsave(vcpu, (u8 *)guest_xsave->region); |
d7876f1b | 3964 | } else { |
a575813b WL |
3965 | if (xstate_bv & ~XFEATURE_MASK_FPSSE || |
3966 | mxcsr & ~mxcsr_feature_mask) | |
2d5b5a66 | 3967 | return -EINVAL; |
b666a4b6 | 3968 | memcpy(&vcpu->arch.guest_fpu->state.fxsave, |
c47ada30 | 3969 | guest_xsave->region, sizeof(struct fxregs_state)); |
2d5b5a66 SY |
3970 | } |
3971 | return 0; | |
3972 | } | |
3973 | ||
3974 | static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, | |
3975 | struct kvm_xcrs *guest_xcrs) | |
3976 | { | |
d366bf7e | 3977 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) { |
2d5b5a66 SY |
3978 | guest_xcrs->nr_xcrs = 0; |
3979 | return; | |
3980 | } | |
3981 | ||
3982 | guest_xcrs->nr_xcrs = 1; | |
3983 | guest_xcrs->flags = 0; | |
3984 | guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; | |
3985 | guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; | |
3986 | } | |
3987 | ||
3988 | static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, | |
3989 | struct kvm_xcrs *guest_xcrs) | |
3990 | { | |
3991 | int i, r = 0; | |
3992 | ||
d366bf7e | 3993 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) |
2d5b5a66 SY |
3994 | return -EINVAL; |
3995 | ||
3996 | if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) | |
3997 | return -EINVAL; | |
3998 | ||
3999 | for (i = 0; i < guest_xcrs->nr_xcrs; i++) | |
4000 | /* Only support XCR0 currently */ | |
c67a04cb | 4001 | if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { |
2d5b5a66 | 4002 | r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, |
c67a04cb | 4003 | guest_xcrs->xcrs[i].value); |
2d5b5a66 SY |
4004 | break; |
4005 | } | |
4006 | if (r) | |
4007 | r = -EINVAL; | |
4008 | return r; | |
4009 | } | |
4010 | ||
1c0b28c2 EM |
4011 | /* |
4012 | * kvm_set_guest_paused() indicates to the guest kernel that it has been | |
4013 | * stopped by the hypervisor. This function will be called from the host only. | |
4014 | * EINVAL is returned when the host attempts to set the flag for a guest that | |
4015 | * does not support pv clocks. | |
4016 | */ | |
4017 | static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) | |
4018 | { | |
0b79459b | 4019 | if (!vcpu->arch.pv_time_enabled) |
1c0b28c2 | 4020 | return -EINVAL; |
51d59c6b | 4021 | vcpu->arch.pvclock_set_guest_stopped_request = true; |
1c0b28c2 EM |
4022 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
4023 | return 0; | |
4024 | } | |
4025 | ||
5c919412 AS |
4026 | static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, |
4027 | struct kvm_enable_cap *cap) | |
4028 | { | |
57b119da VK |
4029 | int r; |
4030 | uint16_t vmcs_version; | |
4031 | void __user *user_ptr; | |
4032 | ||
5c919412 AS |
4033 | if (cap->flags) |
4034 | return -EINVAL; | |
4035 | ||
4036 | switch (cap->cap) { | |
efc479e6 RK |
4037 | case KVM_CAP_HYPERV_SYNIC2: |
4038 | if (cap->args[0]) | |
4039 | return -EINVAL; | |
b2869f28 GS |
4040 | /* fall through */ |
4041 | ||
5c919412 | 4042 | case KVM_CAP_HYPERV_SYNIC: |
546d87e5 WL |
4043 | if (!irqchip_in_kernel(vcpu->kvm)) |
4044 | return -EINVAL; | |
efc479e6 RK |
4045 | return kvm_hv_activate_synic(vcpu, cap->cap == |
4046 | KVM_CAP_HYPERV_SYNIC2); | |
57b119da | 4047 | case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: |
5158917c SC |
4048 | if (!kvm_x86_ops->nested_enable_evmcs) |
4049 | return -ENOTTY; | |
57b119da VK |
4050 | r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version); |
4051 | if (!r) { | |
4052 | user_ptr = (void __user *)(uintptr_t)cap->args[0]; | |
4053 | if (copy_to_user(user_ptr, &vmcs_version, | |
4054 | sizeof(vmcs_version))) | |
4055 | r = -EFAULT; | |
4056 | } | |
4057 | return r; | |
4058 | ||
5c919412 AS |
4059 | default: |
4060 | return -EINVAL; | |
4061 | } | |
4062 | } | |
4063 | ||
313a3dc7 CO |
4064 | long kvm_arch_vcpu_ioctl(struct file *filp, |
4065 | unsigned int ioctl, unsigned long arg) | |
4066 | { | |
4067 | struct kvm_vcpu *vcpu = filp->private_data; | |
4068 | void __user *argp = (void __user *)arg; | |
4069 | int r; | |
d1ac91d8 AK |
4070 | union { |
4071 | struct kvm_lapic_state *lapic; | |
4072 | struct kvm_xsave *xsave; | |
4073 | struct kvm_xcrs *xcrs; | |
4074 | void *buffer; | |
4075 | } u; | |
4076 | ||
9b062471 CD |
4077 | vcpu_load(vcpu); |
4078 | ||
d1ac91d8 | 4079 | u.buffer = NULL; |
313a3dc7 CO |
4080 | switch (ioctl) { |
4081 | case KVM_GET_LAPIC: { | |
2204ae3c | 4082 | r = -EINVAL; |
bce87cce | 4083 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 4084 | goto out; |
254272ce BG |
4085 | u.lapic = kzalloc(sizeof(struct kvm_lapic_state), |
4086 | GFP_KERNEL_ACCOUNT); | |
313a3dc7 | 4087 | |
b772ff36 | 4088 | r = -ENOMEM; |
d1ac91d8 | 4089 | if (!u.lapic) |
b772ff36 | 4090 | goto out; |
d1ac91d8 | 4091 | r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); |
313a3dc7 CO |
4092 | if (r) |
4093 | goto out; | |
4094 | r = -EFAULT; | |
d1ac91d8 | 4095 | if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
4096 | goto out; |
4097 | r = 0; | |
4098 | break; | |
4099 | } | |
4100 | case KVM_SET_LAPIC: { | |
2204ae3c | 4101 | r = -EINVAL; |
bce87cce | 4102 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 4103 | goto out; |
ff5c2c03 | 4104 | u.lapic = memdup_user(argp, sizeof(*u.lapic)); |
9b062471 CD |
4105 | if (IS_ERR(u.lapic)) { |
4106 | r = PTR_ERR(u.lapic); | |
4107 | goto out_nofree; | |
4108 | } | |
ff5c2c03 | 4109 | |
d1ac91d8 | 4110 | r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); |
313a3dc7 CO |
4111 | break; |
4112 | } | |
f77bc6a4 ZX |
4113 | case KVM_INTERRUPT: { |
4114 | struct kvm_interrupt irq; | |
4115 | ||
4116 | r = -EFAULT; | |
0e96f31e | 4117 | if (copy_from_user(&irq, argp, sizeof(irq))) |
f77bc6a4 ZX |
4118 | goto out; |
4119 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
f77bc6a4 ZX |
4120 | break; |
4121 | } | |
c4abb7c9 JK |
4122 | case KVM_NMI: { |
4123 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
c4abb7c9 JK |
4124 | break; |
4125 | } | |
f077825a PB |
4126 | case KVM_SMI: { |
4127 | r = kvm_vcpu_ioctl_smi(vcpu); | |
4128 | break; | |
4129 | } | |
313a3dc7 CO |
4130 | case KVM_SET_CPUID: { |
4131 | struct kvm_cpuid __user *cpuid_arg = argp; | |
4132 | struct kvm_cpuid cpuid; | |
4133 | ||
4134 | r = -EFAULT; | |
0e96f31e | 4135 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
313a3dc7 CO |
4136 | goto out; |
4137 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
313a3dc7 CO |
4138 | break; |
4139 | } | |
07716717 DK |
4140 | case KVM_SET_CPUID2: { |
4141 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
4142 | struct kvm_cpuid2 cpuid; | |
4143 | ||
4144 | r = -EFAULT; | |
0e96f31e | 4145 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
07716717 DK |
4146 | goto out; |
4147 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 4148 | cpuid_arg->entries); |
07716717 DK |
4149 | break; |
4150 | } | |
4151 | case KVM_GET_CPUID2: { | |
4152 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
4153 | struct kvm_cpuid2 cpuid; | |
4154 | ||
4155 | r = -EFAULT; | |
0e96f31e | 4156 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
07716717 DK |
4157 | goto out; |
4158 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 4159 | cpuid_arg->entries); |
07716717 DK |
4160 | if (r) |
4161 | goto out; | |
4162 | r = -EFAULT; | |
0e96f31e | 4163 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) |
07716717 DK |
4164 | goto out; |
4165 | r = 0; | |
4166 | break; | |
4167 | } | |
801e459a TL |
4168 | case KVM_GET_MSRS: { |
4169 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
609e36d3 | 4170 | r = msr_io(vcpu, argp, do_get_msr, 1); |
801e459a | 4171 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 4172 | break; |
801e459a TL |
4173 | } |
4174 | case KVM_SET_MSRS: { | |
4175 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
313a3dc7 | 4176 | r = msr_io(vcpu, argp, do_set_msr, 0); |
801e459a | 4177 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 4178 | break; |
801e459a | 4179 | } |
b209749f AK |
4180 | case KVM_TPR_ACCESS_REPORTING: { |
4181 | struct kvm_tpr_access_ctl tac; | |
4182 | ||
4183 | r = -EFAULT; | |
0e96f31e | 4184 | if (copy_from_user(&tac, argp, sizeof(tac))) |
b209749f AK |
4185 | goto out; |
4186 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
4187 | if (r) | |
4188 | goto out; | |
4189 | r = -EFAULT; | |
0e96f31e | 4190 | if (copy_to_user(argp, &tac, sizeof(tac))) |
b209749f AK |
4191 | goto out; |
4192 | r = 0; | |
4193 | break; | |
4194 | }; | |
b93463aa AK |
4195 | case KVM_SET_VAPIC_ADDR: { |
4196 | struct kvm_vapic_addr va; | |
7301d6ab | 4197 | int idx; |
b93463aa AK |
4198 | |
4199 | r = -EINVAL; | |
35754c98 | 4200 | if (!lapic_in_kernel(vcpu)) |
b93463aa AK |
4201 | goto out; |
4202 | r = -EFAULT; | |
0e96f31e | 4203 | if (copy_from_user(&va, argp, sizeof(va))) |
b93463aa | 4204 | goto out; |
7301d6ab | 4205 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
fda4e2e8 | 4206 | r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); |
7301d6ab | 4207 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b93463aa AK |
4208 | break; |
4209 | } | |
890ca9ae HY |
4210 | case KVM_X86_SETUP_MCE: { |
4211 | u64 mcg_cap; | |
4212 | ||
4213 | r = -EFAULT; | |
0e96f31e | 4214 | if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) |
890ca9ae HY |
4215 | goto out; |
4216 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
4217 | break; | |
4218 | } | |
4219 | case KVM_X86_SET_MCE: { | |
4220 | struct kvm_x86_mce mce; | |
4221 | ||
4222 | r = -EFAULT; | |
0e96f31e | 4223 | if (copy_from_user(&mce, argp, sizeof(mce))) |
890ca9ae HY |
4224 | goto out; |
4225 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
4226 | break; | |
4227 | } | |
3cfc3092 JK |
4228 | case KVM_GET_VCPU_EVENTS: { |
4229 | struct kvm_vcpu_events events; | |
4230 | ||
4231 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
4232 | ||
4233 | r = -EFAULT; | |
4234 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
4235 | break; | |
4236 | r = 0; | |
4237 | break; | |
4238 | } | |
4239 | case KVM_SET_VCPU_EVENTS: { | |
4240 | struct kvm_vcpu_events events; | |
4241 | ||
4242 | r = -EFAULT; | |
4243 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
4244 | break; | |
4245 | ||
4246 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
4247 | break; | |
4248 | } | |
a1efbe77 JK |
4249 | case KVM_GET_DEBUGREGS: { |
4250 | struct kvm_debugregs dbgregs; | |
4251 | ||
4252 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
4253 | ||
4254 | r = -EFAULT; | |
4255 | if (copy_to_user(argp, &dbgregs, | |
4256 | sizeof(struct kvm_debugregs))) | |
4257 | break; | |
4258 | r = 0; | |
4259 | break; | |
4260 | } | |
4261 | case KVM_SET_DEBUGREGS: { | |
4262 | struct kvm_debugregs dbgregs; | |
4263 | ||
4264 | r = -EFAULT; | |
4265 | if (copy_from_user(&dbgregs, argp, | |
4266 | sizeof(struct kvm_debugregs))) | |
4267 | break; | |
4268 | ||
4269 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
4270 | break; | |
4271 | } | |
2d5b5a66 | 4272 | case KVM_GET_XSAVE: { |
254272ce | 4273 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); |
2d5b5a66 | 4274 | r = -ENOMEM; |
d1ac91d8 | 4275 | if (!u.xsave) |
2d5b5a66 SY |
4276 | break; |
4277 | ||
d1ac91d8 | 4278 | kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
4279 | |
4280 | r = -EFAULT; | |
d1ac91d8 | 4281 | if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
4282 | break; |
4283 | r = 0; | |
4284 | break; | |
4285 | } | |
4286 | case KVM_SET_XSAVE: { | |
ff5c2c03 | 4287 | u.xsave = memdup_user(argp, sizeof(*u.xsave)); |
9b062471 CD |
4288 | if (IS_ERR(u.xsave)) { |
4289 | r = PTR_ERR(u.xsave); | |
4290 | goto out_nofree; | |
4291 | } | |
2d5b5a66 | 4292 | |
d1ac91d8 | 4293 | r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
4294 | break; |
4295 | } | |
4296 | case KVM_GET_XCRS: { | |
254272ce | 4297 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); |
2d5b5a66 | 4298 | r = -ENOMEM; |
d1ac91d8 | 4299 | if (!u.xcrs) |
2d5b5a66 SY |
4300 | break; |
4301 | ||
d1ac91d8 | 4302 | kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
4303 | |
4304 | r = -EFAULT; | |
d1ac91d8 | 4305 | if (copy_to_user(argp, u.xcrs, |
2d5b5a66 SY |
4306 | sizeof(struct kvm_xcrs))) |
4307 | break; | |
4308 | r = 0; | |
4309 | break; | |
4310 | } | |
4311 | case KVM_SET_XCRS: { | |
ff5c2c03 | 4312 | u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); |
9b062471 CD |
4313 | if (IS_ERR(u.xcrs)) { |
4314 | r = PTR_ERR(u.xcrs); | |
4315 | goto out_nofree; | |
4316 | } | |
2d5b5a66 | 4317 | |
d1ac91d8 | 4318 | r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
4319 | break; |
4320 | } | |
92a1f12d JR |
4321 | case KVM_SET_TSC_KHZ: { |
4322 | u32 user_tsc_khz; | |
4323 | ||
4324 | r = -EINVAL; | |
92a1f12d JR |
4325 | user_tsc_khz = (u32)arg; |
4326 | ||
4327 | if (user_tsc_khz >= kvm_max_guest_tsc_khz) | |
4328 | goto out; | |
4329 | ||
cc578287 ZA |
4330 | if (user_tsc_khz == 0) |
4331 | user_tsc_khz = tsc_khz; | |
4332 | ||
381d585c HZ |
4333 | if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) |
4334 | r = 0; | |
92a1f12d | 4335 | |
92a1f12d JR |
4336 | goto out; |
4337 | } | |
4338 | case KVM_GET_TSC_KHZ: { | |
cc578287 | 4339 | r = vcpu->arch.virtual_tsc_khz; |
92a1f12d JR |
4340 | goto out; |
4341 | } | |
1c0b28c2 EM |
4342 | case KVM_KVMCLOCK_CTRL: { |
4343 | r = kvm_set_guest_paused(vcpu); | |
4344 | goto out; | |
4345 | } | |
5c919412 AS |
4346 | case KVM_ENABLE_CAP: { |
4347 | struct kvm_enable_cap cap; | |
4348 | ||
4349 | r = -EFAULT; | |
4350 | if (copy_from_user(&cap, argp, sizeof(cap))) | |
4351 | goto out; | |
4352 | r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); | |
4353 | break; | |
4354 | } | |
8fcc4b59 JM |
4355 | case KVM_GET_NESTED_STATE: { |
4356 | struct kvm_nested_state __user *user_kvm_nested_state = argp; | |
4357 | u32 user_data_size; | |
4358 | ||
4359 | r = -EINVAL; | |
4360 | if (!kvm_x86_ops->get_nested_state) | |
4361 | break; | |
4362 | ||
4363 | BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); | |
26b471c7 | 4364 | r = -EFAULT; |
8fcc4b59 | 4365 | if (get_user(user_data_size, &user_kvm_nested_state->size)) |
26b471c7 | 4366 | break; |
8fcc4b59 JM |
4367 | |
4368 | r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state, | |
4369 | user_data_size); | |
4370 | if (r < 0) | |
26b471c7 | 4371 | break; |
8fcc4b59 JM |
4372 | |
4373 | if (r > user_data_size) { | |
4374 | if (put_user(r, &user_kvm_nested_state->size)) | |
26b471c7 LA |
4375 | r = -EFAULT; |
4376 | else | |
4377 | r = -E2BIG; | |
4378 | break; | |
8fcc4b59 | 4379 | } |
26b471c7 | 4380 | |
8fcc4b59 JM |
4381 | r = 0; |
4382 | break; | |
4383 | } | |
4384 | case KVM_SET_NESTED_STATE: { | |
4385 | struct kvm_nested_state __user *user_kvm_nested_state = argp; | |
4386 | struct kvm_nested_state kvm_state; | |
4387 | ||
4388 | r = -EINVAL; | |
4389 | if (!kvm_x86_ops->set_nested_state) | |
4390 | break; | |
4391 | ||
26b471c7 | 4392 | r = -EFAULT; |
8fcc4b59 | 4393 | if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) |
26b471c7 | 4394 | break; |
8fcc4b59 | 4395 | |
26b471c7 | 4396 | r = -EINVAL; |
8fcc4b59 | 4397 | if (kvm_state.size < sizeof(kvm_state)) |
26b471c7 | 4398 | break; |
8fcc4b59 JM |
4399 | |
4400 | if (kvm_state.flags & | |
8cab6507 VK |
4401 | ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE |
4402 | | KVM_STATE_NESTED_EVMCS)) | |
26b471c7 | 4403 | break; |
8fcc4b59 JM |
4404 | |
4405 | /* nested_run_pending implies guest_mode. */ | |
8cab6507 VK |
4406 | if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) |
4407 | && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) | |
26b471c7 | 4408 | break; |
8fcc4b59 JM |
4409 | |
4410 | r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state); | |
4411 | break; | |
4412 | } | |
2bc39970 VK |
4413 | case KVM_GET_SUPPORTED_HV_CPUID: { |
4414 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
4415 | struct kvm_cpuid2 cpuid; | |
4416 | ||
4417 | r = -EFAULT; | |
4418 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) | |
4419 | goto out; | |
4420 | ||
4421 | r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid, | |
4422 | cpuid_arg->entries); | |
4423 | if (r) | |
4424 | goto out; | |
4425 | ||
4426 | r = -EFAULT; | |
4427 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) | |
4428 | goto out; | |
4429 | r = 0; | |
4430 | break; | |
4431 | } | |
313a3dc7 CO |
4432 | default: |
4433 | r = -EINVAL; | |
4434 | } | |
4435 | out: | |
d1ac91d8 | 4436 | kfree(u.buffer); |
9b062471 CD |
4437 | out_nofree: |
4438 | vcpu_put(vcpu); | |
313a3dc7 CO |
4439 | return r; |
4440 | } | |
4441 | ||
1499fa80 | 4442 | vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) |
5b1c1493 CO |
4443 | { |
4444 | return VM_FAULT_SIGBUS; | |
4445 | } | |
4446 | ||
1fe779f8 CO |
4447 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
4448 | { | |
4449 | int ret; | |
4450 | ||
4451 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
951179ce | 4452 | return -EINVAL; |
1fe779f8 CO |
4453 | ret = kvm_x86_ops->set_tss_addr(kvm, addr); |
4454 | return ret; | |
4455 | } | |
4456 | ||
b927a3ce SY |
4457 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
4458 | u64 ident_addr) | |
4459 | { | |
2ac52ab8 | 4460 | return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr); |
b927a3ce SY |
4461 | } |
4462 | ||
1fe779f8 | 4463 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
bc8a3d89 | 4464 | unsigned long kvm_nr_mmu_pages) |
1fe779f8 CO |
4465 | { |
4466 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
4467 | return -EINVAL; | |
4468 | ||
79fac95e | 4469 | mutex_lock(&kvm->slots_lock); |
1fe779f8 CO |
4470 | |
4471 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 4472 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 4473 | |
79fac95e | 4474 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
4475 | return 0; |
4476 | } | |
4477 | ||
bc8a3d89 | 4478 | static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) |
1fe779f8 | 4479 | { |
39de71ec | 4480 | return kvm->arch.n_max_mmu_pages; |
1fe779f8 CO |
4481 | } |
4482 | ||
1fe779f8 CO |
4483 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) |
4484 | { | |
90bca052 | 4485 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
4486 | int r; |
4487 | ||
4488 | r = 0; | |
4489 | switch (chip->chip_id) { | |
4490 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 | 4491 | memcpy(&chip->chip.pic, &pic->pics[0], |
1fe779f8 CO |
4492 | sizeof(struct kvm_pic_state)); |
4493 | break; | |
4494 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 | 4495 | memcpy(&chip->chip.pic, &pic->pics[1], |
1fe779f8 CO |
4496 | sizeof(struct kvm_pic_state)); |
4497 | break; | |
4498 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 4499 | kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
4500 | break; |
4501 | default: | |
4502 | r = -EINVAL; | |
4503 | break; | |
4504 | } | |
4505 | return r; | |
4506 | } | |
4507 | ||
4508 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
4509 | { | |
90bca052 | 4510 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
4511 | int r; |
4512 | ||
4513 | r = 0; | |
4514 | switch (chip->chip_id) { | |
4515 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 DH |
4516 | spin_lock(&pic->lock); |
4517 | memcpy(&pic->pics[0], &chip->chip.pic, | |
1fe779f8 | 4518 | sizeof(struct kvm_pic_state)); |
90bca052 | 4519 | spin_unlock(&pic->lock); |
1fe779f8 CO |
4520 | break; |
4521 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 DH |
4522 | spin_lock(&pic->lock); |
4523 | memcpy(&pic->pics[1], &chip->chip.pic, | |
1fe779f8 | 4524 | sizeof(struct kvm_pic_state)); |
90bca052 | 4525 | spin_unlock(&pic->lock); |
1fe779f8 CO |
4526 | break; |
4527 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 4528 | kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
4529 | break; |
4530 | default: | |
4531 | r = -EINVAL; | |
4532 | break; | |
4533 | } | |
90bca052 | 4534 | kvm_pic_update_irq(pic); |
1fe779f8 CO |
4535 | return r; |
4536 | } | |
4537 | ||
e0f63cb9 SY |
4538 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
4539 | { | |
34f3941c RK |
4540 | struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; |
4541 | ||
4542 | BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); | |
4543 | ||
4544 | mutex_lock(&kps->lock); | |
4545 | memcpy(ps, &kps->channels, sizeof(*ps)); | |
4546 | mutex_unlock(&kps->lock); | |
2da29bcc | 4547 | return 0; |
e0f63cb9 SY |
4548 | } |
4549 | ||
4550 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
4551 | { | |
0185604c | 4552 | int i; |
09edea72 RK |
4553 | struct kvm_pit *pit = kvm->arch.vpit; |
4554 | ||
4555 | mutex_lock(&pit->pit_state.lock); | |
34f3941c | 4556 | memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); |
0185604c | 4557 | for (i = 0; i < 3; i++) |
09edea72 RK |
4558 | kvm_pit_load_count(pit, i, ps->channels[i].count, 0); |
4559 | mutex_unlock(&pit->pit_state.lock); | |
2da29bcc | 4560 | return 0; |
e9f42757 BK |
4561 | } |
4562 | ||
4563 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
4564 | { | |
e9f42757 BK |
4565 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
4566 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
4567 | sizeof(ps->channels)); | |
4568 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
4569 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
97e69aa6 | 4570 | memset(&ps->reserved, 0, sizeof(ps->reserved)); |
2da29bcc | 4571 | return 0; |
e9f42757 BK |
4572 | } |
4573 | ||
4574 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
4575 | { | |
2da29bcc | 4576 | int start = 0; |
0185604c | 4577 | int i; |
e9f42757 | 4578 | u32 prev_legacy, cur_legacy; |
09edea72 RK |
4579 | struct kvm_pit *pit = kvm->arch.vpit; |
4580 | ||
4581 | mutex_lock(&pit->pit_state.lock); | |
4582 | prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
e9f42757 BK |
4583 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; |
4584 | if (!prev_legacy && cur_legacy) | |
4585 | start = 1; | |
09edea72 RK |
4586 | memcpy(&pit->pit_state.channels, &ps->channels, |
4587 | sizeof(pit->pit_state.channels)); | |
4588 | pit->pit_state.flags = ps->flags; | |
0185604c | 4589 | for (i = 0; i < 3; i++) |
09edea72 | 4590 | kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, |
e5e57e7a | 4591 | start && i == 0); |
09edea72 | 4592 | mutex_unlock(&pit->pit_state.lock); |
2da29bcc | 4593 | return 0; |
e0f63cb9 SY |
4594 | } |
4595 | ||
52d939a0 MT |
4596 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
4597 | struct kvm_reinject_control *control) | |
4598 | { | |
71474e2f RK |
4599 | struct kvm_pit *pit = kvm->arch.vpit; |
4600 | ||
4601 | if (!pit) | |
52d939a0 | 4602 | return -ENXIO; |
b39c90b6 | 4603 | |
71474e2f RK |
4604 | /* pit->pit_state.lock was overloaded to prevent userspace from getting |
4605 | * an inconsistent state after running multiple KVM_REINJECT_CONTROL | |
4606 | * ioctls in parallel. Use a separate lock if that ioctl isn't rare. | |
4607 | */ | |
4608 | mutex_lock(&pit->pit_state.lock); | |
4609 | kvm_pit_set_reinject(pit, control->pit_reinject); | |
4610 | mutex_unlock(&pit->pit_state.lock); | |
b39c90b6 | 4611 | |
52d939a0 MT |
4612 | return 0; |
4613 | } | |
4614 | ||
95d4c16c | 4615 | /** |
60c34612 TY |
4616 | * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot |
4617 | * @kvm: kvm instance | |
4618 | * @log: slot id and address to which we copy the log | |
95d4c16c | 4619 | * |
e108ff2f PB |
4620 | * Steps 1-4 below provide general overview of dirty page logging. See |
4621 | * kvm_get_dirty_log_protect() function description for additional details. | |
4622 | * | |
4623 | * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we | |
4624 | * always flush the TLB (step 4) even if previous step failed and the dirty | |
4625 | * bitmap may be corrupt. Regardless of previous outcome the KVM logging API | |
4626 | * does not preclude user space subsequent dirty log read. Flushing TLB ensures | |
4627 | * writes will be marked dirty for next log read. | |
95d4c16c | 4628 | * |
60c34612 TY |
4629 | * 1. Take a snapshot of the bit and clear it if needed. |
4630 | * 2. Write protect the corresponding page. | |
e108ff2f PB |
4631 | * 3. Copy the snapshot to the userspace. |
4632 | * 4. Flush TLB's if needed. | |
5bb064dc | 4633 | */ |
60c34612 | 4634 | int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) |
5bb064dc | 4635 | { |
8fe65a82 | 4636 | bool flush = false; |
e108ff2f | 4637 | int r; |
5bb064dc | 4638 | |
79fac95e | 4639 | mutex_lock(&kvm->slots_lock); |
5bb064dc | 4640 | |
88178fd4 KH |
4641 | /* |
4642 | * Flush potentially hardware-cached dirty pages to dirty_bitmap. | |
4643 | */ | |
4644 | if (kvm_x86_ops->flush_log_dirty) | |
4645 | kvm_x86_ops->flush_log_dirty(kvm); | |
4646 | ||
8fe65a82 | 4647 | r = kvm_get_dirty_log_protect(kvm, log, &flush); |
198c74f4 XG |
4648 | |
4649 | /* | |
4650 | * All the TLBs can be flushed out of mmu lock, see the comments in | |
4651 | * kvm_mmu_slot_remove_write_access(). | |
4652 | */ | |
e108ff2f | 4653 | lockdep_assert_held(&kvm->slots_lock); |
8fe65a82 | 4654 | if (flush) |
2a31b9db PB |
4655 | kvm_flush_remote_tlbs(kvm); |
4656 | ||
4657 | mutex_unlock(&kvm->slots_lock); | |
4658 | return r; | |
4659 | } | |
4660 | ||
4661 | int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log) | |
4662 | { | |
4663 | bool flush = false; | |
4664 | int r; | |
4665 | ||
4666 | mutex_lock(&kvm->slots_lock); | |
4667 | ||
4668 | /* | |
4669 | * Flush potentially hardware-cached dirty pages to dirty_bitmap. | |
4670 | */ | |
4671 | if (kvm_x86_ops->flush_log_dirty) | |
4672 | kvm_x86_ops->flush_log_dirty(kvm); | |
4673 | ||
4674 | r = kvm_clear_dirty_log_protect(kvm, log, &flush); | |
4675 | ||
4676 | /* | |
4677 | * All the TLBs can be flushed out of mmu lock, see the comments in | |
4678 | * kvm_mmu_slot_remove_write_access(). | |
4679 | */ | |
4680 | lockdep_assert_held(&kvm->slots_lock); | |
4681 | if (flush) | |
198c74f4 XG |
4682 | kvm_flush_remote_tlbs(kvm); |
4683 | ||
79fac95e | 4684 | mutex_unlock(&kvm->slots_lock); |
5bb064dc ZX |
4685 | return r; |
4686 | } | |
4687 | ||
aa2fbe6d YZ |
4688 | int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, |
4689 | bool line_status) | |
23d43cf9 CD |
4690 | { |
4691 | if (!irqchip_in_kernel(kvm)) | |
4692 | return -ENXIO; | |
4693 | ||
4694 | irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, | |
aa2fbe6d YZ |
4695 | irq_event->irq, irq_event->level, |
4696 | line_status); | |
23d43cf9 CD |
4697 | return 0; |
4698 | } | |
4699 | ||
e5d83c74 PB |
4700 | int kvm_vm_ioctl_enable_cap(struct kvm *kvm, |
4701 | struct kvm_enable_cap *cap) | |
90de4a18 NA |
4702 | { |
4703 | int r; | |
4704 | ||
4705 | if (cap->flags) | |
4706 | return -EINVAL; | |
4707 | ||
4708 | switch (cap->cap) { | |
4709 | case KVM_CAP_DISABLE_QUIRKS: | |
4710 | kvm->arch.disabled_quirks = cap->args[0]; | |
4711 | r = 0; | |
4712 | break; | |
49df6397 SR |
4713 | case KVM_CAP_SPLIT_IRQCHIP: { |
4714 | mutex_lock(&kvm->lock); | |
b053b2ae SR |
4715 | r = -EINVAL; |
4716 | if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) | |
4717 | goto split_irqchip_unlock; | |
49df6397 SR |
4718 | r = -EEXIST; |
4719 | if (irqchip_in_kernel(kvm)) | |
4720 | goto split_irqchip_unlock; | |
557abc40 | 4721 | if (kvm->created_vcpus) |
49df6397 SR |
4722 | goto split_irqchip_unlock; |
4723 | r = kvm_setup_empty_irq_routing(kvm); | |
5c0aea0e | 4724 | if (r) |
49df6397 SR |
4725 | goto split_irqchip_unlock; |
4726 | /* Pairs with irqchip_in_kernel. */ | |
4727 | smp_wmb(); | |
49776faf | 4728 | kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; |
b053b2ae | 4729 | kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; |
49df6397 SR |
4730 | r = 0; |
4731 | split_irqchip_unlock: | |
4732 | mutex_unlock(&kvm->lock); | |
4733 | break; | |
4734 | } | |
37131313 RK |
4735 | case KVM_CAP_X2APIC_API: |
4736 | r = -EINVAL; | |
4737 | if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) | |
4738 | break; | |
4739 | ||
4740 | if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) | |
4741 | kvm->arch.x2apic_format = true; | |
c519265f RK |
4742 | if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) |
4743 | kvm->arch.x2apic_broadcast_quirk_disabled = true; | |
37131313 RK |
4744 | |
4745 | r = 0; | |
4746 | break; | |
4d5422ce WL |
4747 | case KVM_CAP_X86_DISABLE_EXITS: |
4748 | r = -EINVAL; | |
4749 | if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) | |
4750 | break; | |
4751 | ||
4752 | if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && | |
4753 | kvm_can_mwait_in_guest()) | |
4754 | kvm->arch.mwait_in_guest = true; | |
766d3571 | 4755 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) |
caa057a2 | 4756 | kvm->arch.hlt_in_guest = true; |
b31c114b WL |
4757 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) |
4758 | kvm->arch.pause_in_guest = true; | |
b5170063 WL |
4759 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) |
4760 | kvm->arch.cstate_in_guest = true; | |
4d5422ce WL |
4761 | r = 0; |
4762 | break; | |
6fbbde9a DS |
4763 | case KVM_CAP_MSR_PLATFORM_INFO: |
4764 | kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; | |
4765 | r = 0; | |
c4f55198 JM |
4766 | break; |
4767 | case KVM_CAP_EXCEPTION_PAYLOAD: | |
4768 | kvm->arch.exception_payload_enabled = cap->args[0]; | |
4769 | r = 0; | |
6fbbde9a | 4770 | break; |
90de4a18 NA |
4771 | default: |
4772 | r = -EINVAL; | |
4773 | break; | |
4774 | } | |
4775 | return r; | |
4776 | } | |
4777 | ||
1fe779f8 CO |
4778 | long kvm_arch_vm_ioctl(struct file *filp, |
4779 | unsigned int ioctl, unsigned long arg) | |
4780 | { | |
4781 | struct kvm *kvm = filp->private_data; | |
4782 | void __user *argp = (void __user *)arg; | |
367e1319 | 4783 | int r = -ENOTTY; |
f0d66275 DH |
4784 | /* |
4785 | * This union makes it completely explicit to gcc-3.x | |
4786 | * that these two variables' stack usage should be | |
4787 | * combined, not added together. | |
4788 | */ | |
4789 | union { | |
4790 | struct kvm_pit_state ps; | |
e9f42757 | 4791 | struct kvm_pit_state2 ps2; |
c5ff41ce | 4792 | struct kvm_pit_config pit_config; |
f0d66275 | 4793 | } u; |
1fe779f8 CO |
4794 | |
4795 | switch (ioctl) { | |
4796 | case KVM_SET_TSS_ADDR: | |
4797 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
1fe779f8 | 4798 | break; |
b927a3ce SY |
4799 | case KVM_SET_IDENTITY_MAP_ADDR: { |
4800 | u64 ident_addr; | |
4801 | ||
1af1ac91 DH |
4802 | mutex_lock(&kvm->lock); |
4803 | r = -EINVAL; | |
4804 | if (kvm->created_vcpus) | |
4805 | goto set_identity_unlock; | |
b927a3ce | 4806 | r = -EFAULT; |
0e96f31e | 4807 | if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) |
1af1ac91 | 4808 | goto set_identity_unlock; |
b927a3ce | 4809 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); |
1af1ac91 DH |
4810 | set_identity_unlock: |
4811 | mutex_unlock(&kvm->lock); | |
b927a3ce SY |
4812 | break; |
4813 | } | |
1fe779f8 CO |
4814 | case KVM_SET_NR_MMU_PAGES: |
4815 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
1fe779f8 CO |
4816 | break; |
4817 | case KVM_GET_NR_MMU_PAGES: | |
4818 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
4819 | break; | |
3ddea128 | 4820 | case KVM_CREATE_IRQCHIP: { |
3ddea128 | 4821 | mutex_lock(&kvm->lock); |
09941366 | 4822 | |
3ddea128 | 4823 | r = -EEXIST; |
35e6eaa3 | 4824 | if (irqchip_in_kernel(kvm)) |
3ddea128 | 4825 | goto create_irqchip_unlock; |
09941366 | 4826 | |
3e515705 | 4827 | r = -EINVAL; |
557abc40 | 4828 | if (kvm->created_vcpus) |
3e515705 | 4829 | goto create_irqchip_unlock; |
09941366 RK |
4830 | |
4831 | r = kvm_pic_init(kvm); | |
4832 | if (r) | |
3ddea128 | 4833 | goto create_irqchip_unlock; |
09941366 RK |
4834 | |
4835 | r = kvm_ioapic_init(kvm); | |
4836 | if (r) { | |
09941366 | 4837 | kvm_pic_destroy(kvm); |
3ddea128 | 4838 | goto create_irqchip_unlock; |
09941366 RK |
4839 | } |
4840 | ||
399ec807 AK |
4841 | r = kvm_setup_default_irq_routing(kvm); |
4842 | if (r) { | |
72bb2fcd | 4843 | kvm_ioapic_destroy(kvm); |
09941366 | 4844 | kvm_pic_destroy(kvm); |
71ba994c | 4845 | goto create_irqchip_unlock; |
399ec807 | 4846 | } |
49776faf | 4847 | /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ |
71ba994c | 4848 | smp_wmb(); |
49776faf | 4849 | kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; |
3ddea128 MT |
4850 | create_irqchip_unlock: |
4851 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 4852 | break; |
3ddea128 | 4853 | } |
7837699f | 4854 | case KVM_CREATE_PIT: |
c5ff41ce JK |
4855 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
4856 | goto create_pit; | |
4857 | case KVM_CREATE_PIT2: | |
4858 | r = -EFAULT; | |
4859 | if (copy_from_user(&u.pit_config, argp, | |
4860 | sizeof(struct kvm_pit_config))) | |
4861 | goto out; | |
4862 | create_pit: | |
250715a6 | 4863 | mutex_lock(&kvm->lock); |
269e05e4 AK |
4864 | r = -EEXIST; |
4865 | if (kvm->arch.vpit) | |
4866 | goto create_pit_unlock; | |
7837699f | 4867 | r = -ENOMEM; |
c5ff41ce | 4868 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
4869 | if (kvm->arch.vpit) |
4870 | r = 0; | |
269e05e4 | 4871 | create_pit_unlock: |
250715a6 | 4872 | mutex_unlock(&kvm->lock); |
7837699f | 4873 | break; |
1fe779f8 CO |
4874 | case KVM_GET_IRQCHIP: { |
4875 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 4876 | struct kvm_irqchip *chip; |
1fe779f8 | 4877 | |
ff5c2c03 SL |
4878 | chip = memdup_user(argp, sizeof(*chip)); |
4879 | if (IS_ERR(chip)) { | |
4880 | r = PTR_ERR(chip); | |
1fe779f8 | 4881 | goto out; |
ff5c2c03 SL |
4882 | } |
4883 | ||
1fe779f8 | 4884 | r = -ENXIO; |
826da321 | 4885 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
4886 | goto get_irqchip_out; |
4887 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 4888 | if (r) |
f0d66275 | 4889 | goto get_irqchip_out; |
1fe779f8 | 4890 | r = -EFAULT; |
0e96f31e | 4891 | if (copy_to_user(argp, chip, sizeof(*chip))) |
f0d66275 | 4892 | goto get_irqchip_out; |
1fe779f8 | 4893 | r = 0; |
f0d66275 DH |
4894 | get_irqchip_out: |
4895 | kfree(chip); | |
1fe779f8 CO |
4896 | break; |
4897 | } | |
4898 | case KVM_SET_IRQCHIP: { | |
4899 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 4900 | struct kvm_irqchip *chip; |
1fe779f8 | 4901 | |
ff5c2c03 SL |
4902 | chip = memdup_user(argp, sizeof(*chip)); |
4903 | if (IS_ERR(chip)) { | |
4904 | r = PTR_ERR(chip); | |
1fe779f8 | 4905 | goto out; |
ff5c2c03 SL |
4906 | } |
4907 | ||
1fe779f8 | 4908 | r = -ENXIO; |
826da321 | 4909 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
4910 | goto set_irqchip_out; |
4911 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
1fe779f8 | 4912 | if (r) |
f0d66275 | 4913 | goto set_irqchip_out; |
1fe779f8 | 4914 | r = 0; |
f0d66275 DH |
4915 | set_irqchip_out: |
4916 | kfree(chip); | |
1fe779f8 CO |
4917 | break; |
4918 | } | |
e0f63cb9 | 4919 | case KVM_GET_PIT: { |
e0f63cb9 | 4920 | r = -EFAULT; |
f0d66275 | 4921 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
4922 | goto out; |
4923 | r = -ENXIO; | |
4924 | if (!kvm->arch.vpit) | |
4925 | goto out; | |
f0d66275 | 4926 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
4927 | if (r) |
4928 | goto out; | |
4929 | r = -EFAULT; | |
f0d66275 | 4930 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
4931 | goto out; |
4932 | r = 0; | |
4933 | break; | |
4934 | } | |
4935 | case KVM_SET_PIT: { | |
e0f63cb9 | 4936 | r = -EFAULT; |
0e96f31e | 4937 | if (copy_from_user(&u.ps, argp, sizeof(u.ps))) |
e0f63cb9 SY |
4938 | goto out; |
4939 | r = -ENXIO; | |
4940 | if (!kvm->arch.vpit) | |
4941 | goto out; | |
f0d66275 | 4942 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
e0f63cb9 SY |
4943 | break; |
4944 | } | |
e9f42757 BK |
4945 | case KVM_GET_PIT2: { |
4946 | r = -ENXIO; | |
4947 | if (!kvm->arch.vpit) | |
4948 | goto out; | |
4949 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
4950 | if (r) | |
4951 | goto out; | |
4952 | r = -EFAULT; | |
4953 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
4954 | goto out; | |
4955 | r = 0; | |
4956 | break; | |
4957 | } | |
4958 | case KVM_SET_PIT2: { | |
4959 | r = -EFAULT; | |
4960 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
4961 | goto out; | |
4962 | r = -ENXIO; | |
4963 | if (!kvm->arch.vpit) | |
4964 | goto out; | |
4965 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); | |
e9f42757 BK |
4966 | break; |
4967 | } | |
52d939a0 MT |
4968 | case KVM_REINJECT_CONTROL: { |
4969 | struct kvm_reinject_control control; | |
4970 | r = -EFAULT; | |
4971 | if (copy_from_user(&control, argp, sizeof(control))) | |
4972 | goto out; | |
4973 | r = kvm_vm_ioctl_reinject(kvm, &control); | |
52d939a0 MT |
4974 | break; |
4975 | } | |
d71ba788 PB |
4976 | case KVM_SET_BOOT_CPU_ID: |
4977 | r = 0; | |
4978 | mutex_lock(&kvm->lock); | |
557abc40 | 4979 | if (kvm->created_vcpus) |
d71ba788 PB |
4980 | r = -EBUSY; |
4981 | else | |
4982 | kvm->arch.bsp_vcpu_id = arg; | |
4983 | mutex_unlock(&kvm->lock); | |
4984 | break; | |
ffde22ac | 4985 | case KVM_XEN_HVM_CONFIG: { |
51776043 | 4986 | struct kvm_xen_hvm_config xhc; |
ffde22ac | 4987 | r = -EFAULT; |
51776043 | 4988 | if (copy_from_user(&xhc, argp, sizeof(xhc))) |
ffde22ac ES |
4989 | goto out; |
4990 | r = -EINVAL; | |
51776043 | 4991 | if (xhc.flags) |
ffde22ac | 4992 | goto out; |
51776043 | 4993 | memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc)); |
ffde22ac ES |
4994 | r = 0; |
4995 | break; | |
4996 | } | |
afbcf7ab | 4997 | case KVM_SET_CLOCK: { |
afbcf7ab GC |
4998 | struct kvm_clock_data user_ns; |
4999 | u64 now_ns; | |
afbcf7ab GC |
5000 | |
5001 | r = -EFAULT; | |
5002 | if (copy_from_user(&user_ns, argp, sizeof(user_ns))) | |
5003 | goto out; | |
5004 | ||
5005 | r = -EINVAL; | |
5006 | if (user_ns.flags) | |
5007 | goto out; | |
5008 | ||
5009 | r = 0; | |
0bc48bea RK |
5010 | /* |
5011 | * TODO: userspace has to take care of races with VCPU_RUN, so | |
5012 | * kvm_gen_update_masterclock() can be cut down to locked | |
5013 | * pvclock_update_vm_gtod_copy(). | |
5014 | */ | |
5015 | kvm_gen_update_masterclock(kvm); | |
e891a32e | 5016 | now_ns = get_kvmclock_ns(kvm); |
108b249c | 5017 | kvm->arch.kvmclock_offset += user_ns.clock - now_ns; |
0bc48bea | 5018 | kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE); |
afbcf7ab GC |
5019 | break; |
5020 | } | |
5021 | case KVM_GET_CLOCK: { | |
afbcf7ab GC |
5022 | struct kvm_clock_data user_ns; |
5023 | u64 now_ns; | |
5024 | ||
e891a32e | 5025 | now_ns = get_kvmclock_ns(kvm); |
108b249c | 5026 | user_ns.clock = now_ns; |
e3fd9a93 | 5027 | user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; |
97e69aa6 | 5028 | memset(&user_ns.pad, 0, sizeof(user_ns.pad)); |
afbcf7ab GC |
5029 | |
5030 | r = -EFAULT; | |
5031 | if (copy_to_user(argp, &user_ns, sizeof(user_ns))) | |
5032 | goto out; | |
5033 | r = 0; | |
5034 | break; | |
5035 | } | |
5acc5c06 BS |
5036 | case KVM_MEMORY_ENCRYPT_OP: { |
5037 | r = -ENOTTY; | |
5038 | if (kvm_x86_ops->mem_enc_op) | |
5039 | r = kvm_x86_ops->mem_enc_op(kvm, argp); | |
5040 | break; | |
5041 | } | |
69eaedee BS |
5042 | case KVM_MEMORY_ENCRYPT_REG_REGION: { |
5043 | struct kvm_enc_region region; | |
5044 | ||
5045 | r = -EFAULT; | |
5046 | if (copy_from_user(®ion, argp, sizeof(region))) | |
5047 | goto out; | |
5048 | ||
5049 | r = -ENOTTY; | |
5050 | if (kvm_x86_ops->mem_enc_reg_region) | |
5051 | r = kvm_x86_ops->mem_enc_reg_region(kvm, ®ion); | |
5052 | break; | |
5053 | } | |
5054 | case KVM_MEMORY_ENCRYPT_UNREG_REGION: { | |
5055 | struct kvm_enc_region region; | |
5056 | ||
5057 | r = -EFAULT; | |
5058 | if (copy_from_user(®ion, argp, sizeof(region))) | |
5059 | goto out; | |
5060 | ||
5061 | r = -ENOTTY; | |
5062 | if (kvm_x86_ops->mem_enc_unreg_region) | |
5063 | r = kvm_x86_ops->mem_enc_unreg_region(kvm, ®ion); | |
5064 | break; | |
5065 | } | |
faeb7833 RK |
5066 | case KVM_HYPERV_EVENTFD: { |
5067 | struct kvm_hyperv_eventfd hvevfd; | |
5068 | ||
5069 | r = -EFAULT; | |
5070 | if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) | |
5071 | goto out; | |
5072 | r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); | |
5073 | break; | |
5074 | } | |
66bb8a06 EH |
5075 | case KVM_SET_PMU_EVENT_FILTER: |
5076 | r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); | |
5077 | break; | |
1fe779f8 | 5078 | default: |
ad6260da | 5079 | r = -ENOTTY; |
1fe779f8 CO |
5080 | } |
5081 | out: | |
5082 | return r; | |
5083 | } | |
5084 | ||
a16b043c | 5085 | static void kvm_init_msr_list(void) |
043405e1 CO |
5086 | { |
5087 | u32 dummy[2]; | |
5088 | unsigned i, j; | |
5089 | ||
e2ada66e JM |
5090 | BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4, |
5091 | "Please update the fixed PMCs in msrs_to_save[]"); | |
5092 | BUILD_BUG_ON_MSG(INTEL_PMC_MAX_GENERIC != 32, | |
5093 | "Please update the generic perfctr/eventsel MSRs in msrs_to_save[]"); | |
5094 | ||
62ef68bb | 5095 | for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) { |
043405e1 CO |
5096 | if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) |
5097 | continue; | |
93c4adc7 PB |
5098 | |
5099 | /* | |
5100 | * Even MSRs that are valid in the host may not be exposed | |
9dbe6cf9 | 5101 | * to the guests in some cases. |
93c4adc7 PB |
5102 | */ |
5103 | switch (msrs_to_save[i]) { | |
5104 | case MSR_IA32_BNDCFGS: | |
503234b3 | 5105 | if (!kvm_mpx_supported()) |
93c4adc7 PB |
5106 | continue; |
5107 | break; | |
9dbe6cf9 PB |
5108 | case MSR_TSC_AUX: |
5109 | if (!kvm_x86_ops->rdtscp_supported()) | |
5110 | continue; | |
5111 | break; | |
bf8c55d8 CP |
5112 | case MSR_IA32_RTIT_CTL: |
5113 | case MSR_IA32_RTIT_STATUS: | |
5114 | if (!kvm_x86_ops->pt_supported()) | |
5115 | continue; | |
5116 | break; | |
5117 | case MSR_IA32_RTIT_CR3_MATCH: | |
5118 | if (!kvm_x86_ops->pt_supported() || | |
5119 | !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) | |
5120 | continue; | |
5121 | break; | |
5122 | case MSR_IA32_RTIT_OUTPUT_BASE: | |
5123 | case MSR_IA32_RTIT_OUTPUT_MASK: | |
5124 | if (!kvm_x86_ops->pt_supported() || | |
5125 | (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && | |
5126 | !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) | |
5127 | continue; | |
5128 | break; | |
5129 | case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: { | |
5130 | if (!kvm_x86_ops->pt_supported() || | |
5131 | msrs_to_save[i] - MSR_IA32_RTIT_ADDR0_A >= | |
5132 | intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) | |
5133 | continue; | |
5134 | break; | |
5135 | } | |
93c4adc7 PB |
5136 | default: |
5137 | break; | |
5138 | } | |
5139 | ||
043405e1 CO |
5140 | if (j < i) |
5141 | msrs_to_save[j] = msrs_to_save[i]; | |
5142 | j++; | |
5143 | } | |
5144 | num_msrs_to_save = j; | |
62ef68bb PB |
5145 | |
5146 | for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) { | |
bc226f07 TL |
5147 | if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i])) |
5148 | continue; | |
62ef68bb PB |
5149 | |
5150 | if (j < i) | |
5151 | emulated_msrs[j] = emulated_msrs[i]; | |
5152 | j++; | |
5153 | } | |
5154 | num_emulated_msrs = j; | |
801e459a TL |
5155 | |
5156 | for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) { | |
5157 | struct kvm_msr_entry msr; | |
5158 | ||
5159 | msr.index = msr_based_features[i]; | |
66421c1e | 5160 | if (kvm_get_msr_feature(&msr)) |
801e459a TL |
5161 | continue; |
5162 | ||
5163 | if (j < i) | |
5164 | msr_based_features[j] = msr_based_features[i]; | |
5165 | j++; | |
5166 | } | |
5167 | num_msr_based_features = j; | |
043405e1 CO |
5168 | } |
5169 | ||
bda9020e MT |
5170 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
5171 | const void *v) | |
bbd9b64e | 5172 | { |
70252a10 AK |
5173 | int handled = 0; |
5174 | int n; | |
5175 | ||
5176 | do { | |
5177 | n = min(len, 8); | |
bce87cce | 5178 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
5179 | !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) |
5180 | && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 AK |
5181 | break; |
5182 | handled += n; | |
5183 | addr += n; | |
5184 | len -= n; | |
5185 | v += n; | |
5186 | } while (len); | |
bbd9b64e | 5187 | |
70252a10 | 5188 | return handled; |
bbd9b64e CO |
5189 | } |
5190 | ||
bda9020e | 5191 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 5192 | { |
70252a10 AK |
5193 | int handled = 0; |
5194 | int n; | |
5195 | ||
5196 | do { | |
5197 | n = min(len, 8); | |
bce87cce | 5198 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
5199 | !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, |
5200 | addr, n, v)) | |
5201 | && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 | 5202 | break; |
e39d200f | 5203 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); |
70252a10 AK |
5204 | handled += n; |
5205 | addr += n; | |
5206 | len -= n; | |
5207 | v += n; | |
5208 | } while (len); | |
bbd9b64e | 5209 | |
70252a10 | 5210 | return handled; |
bbd9b64e CO |
5211 | } |
5212 | ||
2dafc6c2 GN |
5213 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
5214 | struct kvm_segment *var, int seg) | |
5215 | { | |
5216 | kvm_x86_ops->set_segment(vcpu, var, seg); | |
5217 | } | |
5218 | ||
5219 | void kvm_get_segment(struct kvm_vcpu *vcpu, | |
5220 | struct kvm_segment *var, int seg) | |
5221 | { | |
5222 | kvm_x86_ops->get_segment(vcpu, var, seg); | |
5223 | } | |
5224 | ||
54987b7a PB |
5225 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
5226 | struct x86_exception *exception) | |
02f59dc9 JR |
5227 | { |
5228 | gpa_t t_gpa; | |
02f59dc9 JR |
5229 | |
5230 | BUG_ON(!mmu_is_nested(vcpu)); | |
5231 | ||
5232 | /* NPT walks are always user-walks */ | |
5233 | access |= PFERR_USER_MASK; | |
44dd3ffa | 5234 | t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception); |
02f59dc9 JR |
5235 | |
5236 | return t_gpa; | |
5237 | } | |
5238 | ||
ab9ae313 AK |
5239 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
5240 | struct x86_exception *exception) | |
1871c602 GN |
5241 | { |
5242 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
ab9ae313 | 5243 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
5244 | } |
5245 | ||
ab9ae313 AK |
5246 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, |
5247 | struct x86_exception *exception) | |
1871c602 GN |
5248 | { |
5249 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
5250 | access |= PFERR_FETCH_MASK; | |
ab9ae313 | 5251 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
5252 | } |
5253 | ||
ab9ae313 AK |
5254 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, |
5255 | struct x86_exception *exception) | |
1871c602 GN |
5256 | { |
5257 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
5258 | access |= PFERR_WRITE_MASK; | |
ab9ae313 | 5259 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
5260 | } |
5261 | ||
5262 | /* uses this to access any guest's mapped memory without checking CPL */ | |
ab9ae313 AK |
5263 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, |
5264 | struct x86_exception *exception) | |
1871c602 | 5265 | { |
ab9ae313 | 5266 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); |
1871c602 GN |
5267 | } |
5268 | ||
5269 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
5270 | struct kvm_vcpu *vcpu, u32 access, | |
bcc55cba | 5271 | struct x86_exception *exception) |
bbd9b64e CO |
5272 | { |
5273 | void *data = val; | |
10589a46 | 5274 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
5275 | |
5276 | while (bytes) { | |
14dfe855 | 5277 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, |
ab9ae313 | 5278 | exception); |
bbd9b64e | 5279 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 5280 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
5281 | int ret; |
5282 | ||
bcc55cba | 5283 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 5284 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa PB |
5285 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, |
5286 | offset, toread); | |
10589a46 | 5287 | if (ret < 0) { |
c3cd7ffa | 5288 | r = X86EMUL_IO_NEEDED; |
10589a46 MT |
5289 | goto out; |
5290 | } | |
bbd9b64e | 5291 | |
77c2002e IE |
5292 | bytes -= toread; |
5293 | data += toread; | |
5294 | addr += toread; | |
bbd9b64e | 5295 | } |
10589a46 | 5296 | out: |
10589a46 | 5297 | return r; |
bbd9b64e | 5298 | } |
77c2002e | 5299 | |
1871c602 | 5300 | /* used for instruction fetching */ |
0f65dd70 AK |
5301 | static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, |
5302 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 5303 | struct x86_exception *exception) |
1871c602 | 5304 | { |
0f65dd70 | 5305 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
1871c602 | 5306 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
44583cba PB |
5307 | unsigned offset; |
5308 | int ret; | |
0f65dd70 | 5309 | |
44583cba PB |
5310 | /* Inline kvm_read_guest_virt_helper for speed. */ |
5311 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, | |
5312 | exception); | |
5313 | if (unlikely(gpa == UNMAPPED_GVA)) | |
5314 | return X86EMUL_PROPAGATE_FAULT; | |
5315 | ||
5316 | offset = addr & (PAGE_SIZE-1); | |
5317 | if (WARN_ON(offset + bytes > PAGE_SIZE)) | |
5318 | bytes = (unsigned)PAGE_SIZE - offset; | |
54bf36aa PB |
5319 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, |
5320 | offset, bytes); | |
44583cba PB |
5321 | if (unlikely(ret < 0)) |
5322 | return X86EMUL_IO_NEEDED; | |
5323 | ||
5324 | return X86EMUL_CONTINUE; | |
1871c602 GN |
5325 | } |
5326 | ||
ce14e868 | 5327 | int kvm_read_guest_virt(struct kvm_vcpu *vcpu, |
0f65dd70 | 5328 | gva_t addr, void *val, unsigned int bytes, |
bcc55cba | 5329 | struct x86_exception *exception) |
1871c602 GN |
5330 | { |
5331 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
0f65dd70 | 5332 | |
353c0956 PB |
5333 | /* |
5334 | * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED | |
5335 | * is returned, but our callers are not ready for that and they blindly | |
5336 | * call kvm_inject_page_fault. Ensure that they at least do not leak | |
5337 | * uninitialized kernel stack memory into cr2 and error code. | |
5338 | */ | |
5339 | memset(exception, 0, sizeof(*exception)); | |
1871c602 | 5340 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, |
bcc55cba | 5341 | exception); |
1871c602 | 5342 | } |
064aea77 | 5343 | EXPORT_SYMBOL_GPL(kvm_read_guest_virt); |
1871c602 | 5344 | |
ce14e868 PB |
5345 | static int emulator_read_std(struct x86_emulate_ctxt *ctxt, |
5346 | gva_t addr, void *val, unsigned int bytes, | |
3c9fa24c | 5347 | struct x86_exception *exception, bool system) |
1871c602 | 5348 | { |
0f65dd70 | 5349 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
3c9fa24c PB |
5350 | u32 access = 0; |
5351 | ||
5352 | if (!system && kvm_x86_ops->get_cpl(vcpu) == 3) | |
5353 | access |= PFERR_USER_MASK; | |
5354 | ||
5355 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); | |
1871c602 GN |
5356 | } |
5357 | ||
7a036a6f RK |
5358 | static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, |
5359 | unsigned long addr, void *val, unsigned int bytes) | |
5360 | { | |
5361 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
5362 | int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); | |
5363 | ||
5364 | return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; | |
5365 | } | |
5366 | ||
ce14e868 PB |
5367 | static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, |
5368 | struct kvm_vcpu *vcpu, u32 access, | |
5369 | struct x86_exception *exception) | |
77c2002e IE |
5370 | { |
5371 | void *data = val; | |
5372 | int r = X86EMUL_CONTINUE; | |
5373 | ||
5374 | while (bytes) { | |
14dfe855 | 5375 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, |
ce14e868 | 5376 | access, |
ab9ae313 | 5377 | exception); |
77c2002e IE |
5378 | unsigned offset = addr & (PAGE_SIZE-1); |
5379 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
5380 | int ret; | |
5381 | ||
bcc55cba | 5382 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 5383 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa | 5384 | ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); |
77c2002e | 5385 | if (ret < 0) { |
c3cd7ffa | 5386 | r = X86EMUL_IO_NEEDED; |
77c2002e IE |
5387 | goto out; |
5388 | } | |
5389 | ||
5390 | bytes -= towrite; | |
5391 | data += towrite; | |
5392 | addr += towrite; | |
5393 | } | |
5394 | out: | |
5395 | return r; | |
5396 | } | |
ce14e868 PB |
5397 | |
5398 | static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, | |
3c9fa24c PB |
5399 | unsigned int bytes, struct x86_exception *exception, |
5400 | bool system) | |
ce14e868 PB |
5401 | { |
5402 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
3c9fa24c PB |
5403 | u32 access = PFERR_WRITE_MASK; |
5404 | ||
5405 | if (!system && kvm_x86_ops->get_cpl(vcpu) == 3) | |
5406 | access |= PFERR_USER_MASK; | |
ce14e868 PB |
5407 | |
5408 | return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, | |
3c9fa24c | 5409 | access, exception); |
ce14e868 PB |
5410 | } |
5411 | ||
5412 | int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, | |
5413 | unsigned int bytes, struct x86_exception *exception) | |
5414 | { | |
c595ceee PB |
5415 | /* kvm_write_guest_virt_system can pull in tons of pages. */ |
5416 | vcpu->arch.l1tf_flush_l1d = true; | |
5417 | ||
541ab2ae FH |
5418 | /* |
5419 | * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED | |
5420 | * is returned, but our callers are not ready for that and they blindly | |
5421 | * call kvm_inject_page_fault. Ensure that they at least do not leak | |
5422 | * uninitialized kernel stack memory into cr2 and error code. | |
5423 | */ | |
5424 | memset(exception, 0, sizeof(*exception)); | |
ce14e868 PB |
5425 | return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, |
5426 | PFERR_WRITE_MASK, exception); | |
5427 | } | |
6a4d7550 | 5428 | EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); |
77c2002e | 5429 | |
082d06ed WL |
5430 | int handle_ud(struct kvm_vcpu *vcpu) |
5431 | { | |
6c86eedc | 5432 | int emul_type = EMULTYPE_TRAP_UD; |
082d06ed | 5433 | enum emulation_result er; |
6c86eedc WL |
5434 | char sig[5]; /* ud2; .ascii "kvm" */ |
5435 | struct x86_exception e; | |
5436 | ||
5437 | if (force_emulation_prefix && | |
3c9fa24c PB |
5438 | kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), |
5439 | sig, sizeof(sig), &e) == 0 && | |
6c86eedc WL |
5440 | memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) { |
5441 | kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); | |
5442 | emul_type = 0; | |
5443 | } | |
082d06ed | 5444 | |
0ce97a2b | 5445 | er = kvm_emulate_instruction(vcpu, emul_type); |
082d06ed WL |
5446 | if (er == EMULATE_USER_EXIT) |
5447 | return 0; | |
5448 | if (er != EMULATE_DONE) | |
5449 | kvm_queue_exception(vcpu, UD_VECTOR); | |
5450 | return 1; | |
5451 | } | |
5452 | EXPORT_SYMBOL_GPL(handle_ud); | |
5453 | ||
0f89b207 TL |
5454 | static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
5455 | gpa_t gpa, bool write) | |
5456 | { | |
5457 | /* For APIC access vmexit */ | |
5458 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
5459 | return 1; | |
5460 | ||
5461 | if (vcpu_match_mmio_gpa(vcpu, gpa)) { | |
5462 | trace_vcpu_match_mmio(gva, gpa, write, true); | |
5463 | return 1; | |
5464 | } | |
5465 | ||
5466 | return 0; | |
5467 | } | |
5468 | ||
af7cc7d1 XG |
5469 | static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
5470 | gpa_t *gpa, struct x86_exception *exception, | |
5471 | bool write) | |
5472 | { | |
97d64b78 AK |
5473 | u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) |
5474 | | (write ? PFERR_WRITE_MASK : 0); | |
af7cc7d1 | 5475 | |
be94f6b7 HH |
5476 | /* |
5477 | * currently PKRU is only applied to ept enabled guest so | |
5478 | * there is no pkey in EPT page table for L1 guest or EPT | |
5479 | * shadow page table for L2 guest. | |
5480 | */ | |
97d64b78 | 5481 | if (vcpu_match_mmio_gva(vcpu, gva) |
97ec8c06 | 5482 | && !permission_fault(vcpu, vcpu->arch.walk_mmu, |
871bd034 | 5483 | vcpu->arch.mmio_access, 0, access)) { |
bebb106a XG |
5484 | *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | |
5485 | (gva & (PAGE_SIZE - 1)); | |
4f022648 | 5486 | trace_vcpu_match_mmio(gva, *gpa, write, false); |
bebb106a XG |
5487 | return 1; |
5488 | } | |
5489 | ||
af7cc7d1 XG |
5490 | *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
5491 | ||
5492 | if (*gpa == UNMAPPED_GVA) | |
5493 | return -1; | |
5494 | ||
0f89b207 | 5495 | return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); |
af7cc7d1 XG |
5496 | } |
5497 | ||
3200f405 | 5498 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
bcc55cba | 5499 | const void *val, int bytes) |
bbd9b64e CO |
5500 | { |
5501 | int ret; | |
5502 | ||
54bf36aa | 5503 | ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); |
9f811285 | 5504 | if (ret < 0) |
bbd9b64e | 5505 | return 0; |
0eb05bf2 | 5506 | kvm_page_track_write(vcpu, gpa, val, bytes); |
bbd9b64e CO |
5507 | return 1; |
5508 | } | |
5509 | ||
77d197b2 XG |
5510 | struct read_write_emulator_ops { |
5511 | int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, | |
5512 | int bytes); | |
5513 | int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
5514 | void *val, int bytes); | |
5515 | int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
5516 | int bytes, void *val); | |
5517 | int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
5518 | void *val, int bytes); | |
5519 | bool write; | |
5520 | }; | |
5521 | ||
5522 | static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) | |
5523 | { | |
5524 | if (vcpu->mmio_read_completed) { | |
77d197b2 | 5525 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
e39d200f | 5526 | vcpu->mmio_fragments[0].gpa, val); |
77d197b2 XG |
5527 | vcpu->mmio_read_completed = 0; |
5528 | return 1; | |
5529 | } | |
5530 | ||
5531 | return 0; | |
5532 | } | |
5533 | ||
5534 | static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
5535 | void *val, int bytes) | |
5536 | { | |
54bf36aa | 5537 | return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); |
77d197b2 XG |
5538 | } |
5539 | ||
5540 | static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
5541 | void *val, int bytes) | |
5542 | { | |
5543 | return emulator_write_phys(vcpu, gpa, val, bytes); | |
5544 | } | |
5545 | ||
5546 | static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) | |
5547 | { | |
e39d200f | 5548 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); |
77d197b2 XG |
5549 | return vcpu_mmio_write(vcpu, gpa, bytes, val); |
5550 | } | |
5551 | ||
5552 | static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
5553 | void *val, int bytes) | |
5554 | { | |
e39d200f | 5555 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); |
77d197b2 XG |
5556 | return X86EMUL_IO_NEEDED; |
5557 | } | |
5558 | ||
5559 | static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
5560 | void *val, int bytes) | |
5561 | { | |
f78146b0 AK |
5562 | struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; |
5563 | ||
87da7e66 | 5564 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); |
77d197b2 XG |
5565 | return X86EMUL_CONTINUE; |
5566 | } | |
5567 | ||
0fbe9b0b | 5568 | static const struct read_write_emulator_ops read_emultor = { |
77d197b2 XG |
5569 | .read_write_prepare = read_prepare, |
5570 | .read_write_emulate = read_emulate, | |
5571 | .read_write_mmio = vcpu_mmio_read, | |
5572 | .read_write_exit_mmio = read_exit_mmio, | |
5573 | }; | |
5574 | ||
0fbe9b0b | 5575 | static const struct read_write_emulator_ops write_emultor = { |
77d197b2 XG |
5576 | .read_write_emulate = write_emulate, |
5577 | .read_write_mmio = write_mmio, | |
5578 | .read_write_exit_mmio = write_exit_mmio, | |
5579 | .write = true, | |
5580 | }; | |
5581 | ||
22388a3c XG |
5582 | static int emulator_read_write_onepage(unsigned long addr, void *val, |
5583 | unsigned int bytes, | |
5584 | struct x86_exception *exception, | |
5585 | struct kvm_vcpu *vcpu, | |
0fbe9b0b | 5586 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 5587 | { |
af7cc7d1 XG |
5588 | gpa_t gpa; |
5589 | int handled, ret; | |
22388a3c | 5590 | bool write = ops->write; |
f78146b0 | 5591 | struct kvm_mmio_fragment *frag; |
0f89b207 TL |
5592 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
5593 | ||
5594 | /* | |
5595 | * If the exit was due to a NPF we may already have a GPA. | |
5596 | * If the GPA is present, use it to avoid the GVA to GPA table walk. | |
5597 | * Note, this cannot be used on string operations since string | |
5598 | * operation using rep will only have the initial GPA from the NPF | |
5599 | * occurred. | |
5600 | */ | |
5601 | if (vcpu->arch.gpa_available && | |
5602 | emulator_can_use_gpa(ctxt) && | |
618232e2 BS |
5603 | (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) { |
5604 | gpa = vcpu->arch.gpa_val; | |
5605 | ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); | |
5606 | } else { | |
5607 | ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); | |
5608 | if (ret < 0) | |
5609 | return X86EMUL_PROPAGATE_FAULT; | |
0f89b207 | 5610 | } |
10589a46 | 5611 | |
618232e2 | 5612 | if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) |
bbd9b64e CO |
5613 | return X86EMUL_CONTINUE; |
5614 | ||
bbd9b64e CO |
5615 | /* |
5616 | * Is this MMIO handled locally? | |
5617 | */ | |
22388a3c | 5618 | handled = ops->read_write_mmio(vcpu, gpa, bytes, val); |
70252a10 | 5619 | if (handled == bytes) |
bbd9b64e | 5620 | return X86EMUL_CONTINUE; |
bbd9b64e | 5621 | |
70252a10 AK |
5622 | gpa += handled; |
5623 | bytes -= handled; | |
5624 | val += handled; | |
5625 | ||
87da7e66 XG |
5626 | WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); |
5627 | frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; | |
5628 | frag->gpa = gpa; | |
5629 | frag->data = val; | |
5630 | frag->len = bytes; | |
f78146b0 | 5631 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
5632 | } |
5633 | ||
52eb5a6d XL |
5634 | static int emulator_read_write(struct x86_emulate_ctxt *ctxt, |
5635 | unsigned long addr, | |
22388a3c XG |
5636 | void *val, unsigned int bytes, |
5637 | struct x86_exception *exception, | |
0fbe9b0b | 5638 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 5639 | { |
0f65dd70 | 5640 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
f78146b0 AK |
5641 | gpa_t gpa; |
5642 | int rc; | |
5643 | ||
5644 | if (ops->read_write_prepare && | |
5645 | ops->read_write_prepare(vcpu, val, bytes)) | |
5646 | return X86EMUL_CONTINUE; | |
5647 | ||
5648 | vcpu->mmio_nr_fragments = 0; | |
0f65dd70 | 5649 | |
bbd9b64e CO |
5650 | /* Crossing a page boundary? */ |
5651 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
f78146b0 | 5652 | int now; |
bbd9b64e CO |
5653 | |
5654 | now = -addr & ~PAGE_MASK; | |
22388a3c XG |
5655 | rc = emulator_read_write_onepage(addr, val, now, exception, |
5656 | vcpu, ops); | |
5657 | ||
bbd9b64e CO |
5658 | if (rc != X86EMUL_CONTINUE) |
5659 | return rc; | |
5660 | addr += now; | |
bac15531 NA |
5661 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
5662 | addr = (u32)addr; | |
bbd9b64e CO |
5663 | val += now; |
5664 | bytes -= now; | |
5665 | } | |
22388a3c | 5666 | |
f78146b0 AK |
5667 | rc = emulator_read_write_onepage(addr, val, bytes, exception, |
5668 | vcpu, ops); | |
5669 | if (rc != X86EMUL_CONTINUE) | |
5670 | return rc; | |
5671 | ||
5672 | if (!vcpu->mmio_nr_fragments) | |
5673 | return rc; | |
5674 | ||
5675 | gpa = vcpu->mmio_fragments[0].gpa; | |
5676 | ||
5677 | vcpu->mmio_needed = 1; | |
5678 | vcpu->mmio_cur_fragment = 0; | |
5679 | ||
87da7e66 | 5680 | vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); |
f78146b0 AK |
5681 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; |
5682 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
5683 | vcpu->run->mmio.phys_addr = gpa; | |
5684 | ||
5685 | return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); | |
22388a3c XG |
5686 | } |
5687 | ||
5688 | static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, | |
5689 | unsigned long addr, | |
5690 | void *val, | |
5691 | unsigned int bytes, | |
5692 | struct x86_exception *exception) | |
5693 | { | |
5694 | return emulator_read_write(ctxt, addr, val, bytes, | |
5695 | exception, &read_emultor); | |
5696 | } | |
5697 | ||
52eb5a6d | 5698 | static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, |
22388a3c XG |
5699 | unsigned long addr, |
5700 | const void *val, | |
5701 | unsigned int bytes, | |
5702 | struct x86_exception *exception) | |
5703 | { | |
5704 | return emulator_read_write(ctxt, addr, (void *)val, bytes, | |
5705 | exception, &write_emultor); | |
bbd9b64e | 5706 | } |
bbd9b64e | 5707 | |
daea3e73 AK |
5708 | #define CMPXCHG_TYPE(t, ptr, old, new) \ |
5709 | (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) | |
5710 | ||
5711 | #ifdef CONFIG_X86_64 | |
5712 | # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) | |
5713 | #else | |
5714 | # define CMPXCHG64(ptr, old, new) \ | |
9749a6c0 | 5715 | (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) |
daea3e73 AK |
5716 | #endif |
5717 | ||
0f65dd70 AK |
5718 | static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, |
5719 | unsigned long addr, | |
bbd9b64e CO |
5720 | const void *old, |
5721 | const void *new, | |
5722 | unsigned int bytes, | |
0f65dd70 | 5723 | struct x86_exception *exception) |
bbd9b64e | 5724 | { |
42e35f80 | 5725 | struct kvm_host_map map; |
0f65dd70 | 5726 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
daea3e73 | 5727 | gpa_t gpa; |
daea3e73 AK |
5728 | char *kaddr; |
5729 | bool exchanged; | |
2bacc55c | 5730 | |
daea3e73 AK |
5731 | /* guests cmpxchg8b have to be emulated atomically */ |
5732 | if (bytes > 8 || (bytes & (bytes - 1))) | |
5733 | goto emul_write; | |
10589a46 | 5734 | |
daea3e73 | 5735 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); |
2bacc55c | 5736 | |
daea3e73 AK |
5737 | if (gpa == UNMAPPED_GVA || |
5738 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
5739 | goto emul_write; | |
2bacc55c | 5740 | |
daea3e73 AK |
5741 | if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) |
5742 | goto emul_write; | |
72dc67a6 | 5743 | |
42e35f80 | 5744 | if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map)) |
c19b8bd6 | 5745 | goto emul_write; |
72dc67a6 | 5746 | |
42e35f80 KA |
5747 | kaddr = map.hva + offset_in_page(gpa); |
5748 | ||
daea3e73 AK |
5749 | switch (bytes) { |
5750 | case 1: | |
5751 | exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); | |
5752 | break; | |
5753 | case 2: | |
5754 | exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); | |
5755 | break; | |
5756 | case 4: | |
5757 | exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); | |
5758 | break; | |
5759 | case 8: | |
5760 | exchanged = CMPXCHG64(kaddr, old, new); | |
5761 | break; | |
5762 | default: | |
5763 | BUG(); | |
2bacc55c | 5764 | } |
42e35f80 KA |
5765 | |
5766 | kvm_vcpu_unmap(vcpu, &map, true); | |
daea3e73 AK |
5767 | |
5768 | if (!exchanged) | |
5769 | return X86EMUL_CMPXCHG_FAILED; | |
5770 | ||
0eb05bf2 | 5771 | kvm_page_track_write(vcpu, gpa, new, bytes); |
8f6abd06 GN |
5772 | |
5773 | return X86EMUL_CONTINUE; | |
4a5f48f6 | 5774 | |
3200f405 | 5775 | emul_write: |
daea3e73 | 5776 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); |
2bacc55c | 5777 | |
0f65dd70 | 5778 | return emulator_write_emulated(ctxt, addr, new, bytes, exception); |
bbd9b64e CO |
5779 | } |
5780 | ||
cf8f70bf GN |
5781 | static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) |
5782 | { | |
cbfc6c91 | 5783 | int r = 0, i; |
cf8f70bf | 5784 | |
cbfc6c91 WL |
5785 | for (i = 0; i < vcpu->arch.pio.count; i++) { |
5786 | if (vcpu->arch.pio.in) | |
5787 | r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, | |
5788 | vcpu->arch.pio.size, pd); | |
5789 | else | |
5790 | r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, | |
5791 | vcpu->arch.pio.port, vcpu->arch.pio.size, | |
5792 | pd); | |
5793 | if (r) | |
5794 | break; | |
5795 | pd += vcpu->arch.pio.size; | |
5796 | } | |
cf8f70bf GN |
5797 | return r; |
5798 | } | |
5799 | ||
6f6fbe98 XG |
5800 | static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, |
5801 | unsigned short port, void *val, | |
5802 | unsigned int count, bool in) | |
cf8f70bf | 5803 | { |
cf8f70bf | 5804 | vcpu->arch.pio.port = port; |
6f6fbe98 | 5805 | vcpu->arch.pio.in = in; |
7972995b | 5806 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
5807 | vcpu->arch.pio.size = size; |
5808 | ||
5809 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
7972995b | 5810 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
5811 | return 1; |
5812 | } | |
5813 | ||
5814 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
6f6fbe98 | 5815 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; |
cf8f70bf GN |
5816 | vcpu->run->io.size = size; |
5817 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
5818 | vcpu->run->io.count = count; | |
5819 | vcpu->run->io.port = port; | |
5820 | ||
5821 | return 0; | |
5822 | } | |
5823 | ||
6f6fbe98 XG |
5824 | static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
5825 | int size, unsigned short port, void *val, | |
5826 | unsigned int count) | |
cf8f70bf | 5827 | { |
ca1d4a9e | 5828 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
6f6fbe98 | 5829 | int ret; |
ca1d4a9e | 5830 | |
6f6fbe98 XG |
5831 | if (vcpu->arch.pio.count) |
5832 | goto data_avail; | |
cf8f70bf | 5833 | |
cbfc6c91 WL |
5834 | memset(vcpu->arch.pio_data, 0, size * count); |
5835 | ||
6f6fbe98 XG |
5836 | ret = emulator_pio_in_out(vcpu, size, port, val, count, true); |
5837 | if (ret) { | |
5838 | data_avail: | |
5839 | memcpy(val, vcpu->arch.pio_data, size * count); | |
1171903d | 5840 | trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); |
7972995b | 5841 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
5842 | return 1; |
5843 | } | |
5844 | ||
cf8f70bf GN |
5845 | return 0; |
5846 | } | |
5847 | ||
6f6fbe98 XG |
5848 | static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, |
5849 | int size, unsigned short port, | |
5850 | const void *val, unsigned int count) | |
5851 | { | |
5852 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
5853 | ||
5854 | memcpy(vcpu->arch.pio_data, val, size * count); | |
1171903d | 5855 | trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); |
6f6fbe98 XG |
5856 | return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); |
5857 | } | |
5858 | ||
bbd9b64e CO |
5859 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) |
5860 | { | |
5861 | return kvm_x86_ops->get_segment_base(vcpu, seg); | |
5862 | } | |
5863 | ||
3cb16fe7 | 5864 | static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) |
bbd9b64e | 5865 | { |
3cb16fe7 | 5866 | kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); |
bbd9b64e CO |
5867 | } |
5868 | ||
ae6a2375 | 5869 | static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) |
f5f48ee1 SY |
5870 | { |
5871 | if (!need_emulate_wbinvd(vcpu)) | |
5872 | return X86EMUL_CONTINUE; | |
5873 | ||
5874 | if (kvm_x86_ops->has_wbinvd_exit()) { | |
2eec7343 JK |
5875 | int cpu = get_cpu(); |
5876 | ||
5877 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
f5f48ee1 SY |
5878 | smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, |
5879 | wbinvd_ipi, NULL, 1); | |
2eec7343 | 5880 | put_cpu(); |
f5f48ee1 | 5881 | cpumask_clear(vcpu->arch.wbinvd_dirty_mask); |
2eec7343 JK |
5882 | } else |
5883 | wbinvd(); | |
f5f48ee1 SY |
5884 | return X86EMUL_CONTINUE; |
5885 | } | |
5cb56059 JS |
5886 | |
5887 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
5888 | { | |
6affcbed KH |
5889 | kvm_emulate_wbinvd_noskip(vcpu); |
5890 | return kvm_skip_emulated_instruction(vcpu); | |
5cb56059 | 5891 | } |
f5f48ee1 SY |
5892 | EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); |
5893 | ||
5cb56059 JS |
5894 | |
5895 | ||
bcaf5cc5 AK |
5896 | static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) |
5897 | { | |
5cb56059 | 5898 | kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); |
bcaf5cc5 AK |
5899 | } |
5900 | ||
52eb5a6d XL |
5901 | static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, |
5902 | unsigned long *dest) | |
bbd9b64e | 5903 | { |
16f8a6f9 | 5904 | return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); |
bbd9b64e CO |
5905 | } |
5906 | ||
52eb5a6d XL |
5907 | static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, |
5908 | unsigned long value) | |
bbd9b64e | 5909 | { |
338dbc97 | 5910 | |
717746e3 | 5911 | return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); |
bbd9b64e CO |
5912 | } |
5913 | ||
52a46617 | 5914 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) |
5fdbf976 | 5915 | { |
52a46617 | 5916 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; |
5fdbf976 MT |
5917 | } |
5918 | ||
717746e3 | 5919 | static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) |
bbd9b64e | 5920 | { |
717746e3 | 5921 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
52a46617 GN |
5922 | unsigned long value; |
5923 | ||
5924 | switch (cr) { | |
5925 | case 0: | |
5926 | value = kvm_read_cr0(vcpu); | |
5927 | break; | |
5928 | case 2: | |
5929 | value = vcpu->arch.cr2; | |
5930 | break; | |
5931 | case 3: | |
9f8fe504 | 5932 | value = kvm_read_cr3(vcpu); |
52a46617 GN |
5933 | break; |
5934 | case 4: | |
5935 | value = kvm_read_cr4(vcpu); | |
5936 | break; | |
5937 | case 8: | |
5938 | value = kvm_get_cr8(vcpu); | |
5939 | break; | |
5940 | default: | |
a737f256 | 5941 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
52a46617 GN |
5942 | return 0; |
5943 | } | |
5944 | ||
5945 | return value; | |
5946 | } | |
5947 | ||
717746e3 | 5948 | static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) |
52a46617 | 5949 | { |
717746e3 | 5950 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
0f12244f GN |
5951 | int res = 0; |
5952 | ||
52a46617 GN |
5953 | switch (cr) { |
5954 | case 0: | |
49a9b07e | 5955 | res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
52a46617 GN |
5956 | break; |
5957 | case 2: | |
5958 | vcpu->arch.cr2 = val; | |
5959 | break; | |
5960 | case 3: | |
2390218b | 5961 | res = kvm_set_cr3(vcpu, val); |
52a46617 GN |
5962 | break; |
5963 | case 4: | |
a83b29c6 | 5964 | res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
52a46617 GN |
5965 | break; |
5966 | case 8: | |
eea1cff9 | 5967 | res = kvm_set_cr8(vcpu, val); |
52a46617 GN |
5968 | break; |
5969 | default: | |
a737f256 | 5970 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
0f12244f | 5971 | res = -1; |
52a46617 | 5972 | } |
0f12244f GN |
5973 | |
5974 | return res; | |
52a46617 GN |
5975 | } |
5976 | ||
717746e3 | 5977 | static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) |
9c537244 | 5978 | { |
717746e3 | 5979 | return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); |
9c537244 GN |
5980 | } |
5981 | ||
4bff1e86 | 5982 | static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
2dafc6c2 | 5983 | { |
4bff1e86 | 5984 | kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); |
2dafc6c2 GN |
5985 | } |
5986 | ||
4bff1e86 | 5987 | static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
160ce1f1 | 5988 | { |
4bff1e86 | 5989 | kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); |
160ce1f1 MG |
5990 | } |
5991 | ||
1ac9d0cf AK |
5992 | static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
5993 | { | |
5994 | kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); | |
5995 | } | |
5996 | ||
5997 | static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) | |
5998 | { | |
5999 | kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); | |
6000 | } | |
6001 | ||
4bff1e86 AK |
6002 | static unsigned long emulator_get_cached_segment_base( |
6003 | struct x86_emulate_ctxt *ctxt, int seg) | |
5951c442 | 6004 | { |
4bff1e86 | 6005 | return get_segment_base(emul_to_vcpu(ctxt), seg); |
5951c442 GN |
6006 | } |
6007 | ||
1aa36616 AK |
6008 | static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, |
6009 | struct desc_struct *desc, u32 *base3, | |
6010 | int seg) | |
2dafc6c2 GN |
6011 | { |
6012 | struct kvm_segment var; | |
6013 | ||
4bff1e86 | 6014 | kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); |
1aa36616 | 6015 | *selector = var.selector; |
2dafc6c2 | 6016 | |
378a8b09 GN |
6017 | if (var.unusable) { |
6018 | memset(desc, 0, sizeof(*desc)); | |
f0367ee1 RK |
6019 | if (base3) |
6020 | *base3 = 0; | |
2dafc6c2 | 6021 | return false; |
378a8b09 | 6022 | } |
2dafc6c2 GN |
6023 | |
6024 | if (var.g) | |
6025 | var.limit >>= 12; | |
6026 | set_desc_limit(desc, var.limit); | |
6027 | set_desc_base(desc, (unsigned long)var.base); | |
5601d05b GN |
6028 | #ifdef CONFIG_X86_64 |
6029 | if (base3) | |
6030 | *base3 = var.base >> 32; | |
6031 | #endif | |
2dafc6c2 GN |
6032 | desc->type = var.type; |
6033 | desc->s = var.s; | |
6034 | desc->dpl = var.dpl; | |
6035 | desc->p = var.present; | |
6036 | desc->avl = var.avl; | |
6037 | desc->l = var.l; | |
6038 | desc->d = var.db; | |
6039 | desc->g = var.g; | |
6040 | ||
6041 | return true; | |
6042 | } | |
6043 | ||
1aa36616 AK |
6044 | static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, |
6045 | struct desc_struct *desc, u32 base3, | |
6046 | int seg) | |
2dafc6c2 | 6047 | { |
4bff1e86 | 6048 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
2dafc6c2 GN |
6049 | struct kvm_segment var; |
6050 | ||
1aa36616 | 6051 | var.selector = selector; |
2dafc6c2 | 6052 | var.base = get_desc_base(desc); |
5601d05b GN |
6053 | #ifdef CONFIG_X86_64 |
6054 | var.base |= ((u64)base3) << 32; | |
6055 | #endif | |
2dafc6c2 GN |
6056 | var.limit = get_desc_limit(desc); |
6057 | if (desc->g) | |
6058 | var.limit = (var.limit << 12) | 0xfff; | |
6059 | var.type = desc->type; | |
2dafc6c2 GN |
6060 | var.dpl = desc->dpl; |
6061 | var.db = desc->d; | |
6062 | var.s = desc->s; | |
6063 | var.l = desc->l; | |
6064 | var.g = desc->g; | |
6065 | var.avl = desc->avl; | |
6066 | var.present = desc->p; | |
6067 | var.unusable = !var.present; | |
6068 | var.padding = 0; | |
6069 | ||
6070 | kvm_set_segment(vcpu, &var, seg); | |
6071 | return; | |
6072 | } | |
6073 | ||
717746e3 AK |
6074 | static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, |
6075 | u32 msr_index, u64 *pdata) | |
6076 | { | |
f20935d8 | 6077 | return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata); |
717746e3 AK |
6078 | } |
6079 | ||
6080 | static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, | |
6081 | u32 msr_index, u64 data) | |
6082 | { | |
f20935d8 | 6083 | return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data); |
717746e3 AK |
6084 | } |
6085 | ||
64d60670 PB |
6086 | static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) |
6087 | { | |
6088 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
6089 | ||
6090 | return vcpu->arch.smbase; | |
6091 | } | |
6092 | ||
6093 | static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) | |
6094 | { | |
6095 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
6096 | ||
6097 | vcpu->arch.smbase = smbase; | |
6098 | } | |
6099 | ||
67f4d428 NA |
6100 | static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, |
6101 | u32 pmc) | |
6102 | { | |
c6702c9d | 6103 | return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc); |
67f4d428 NA |
6104 | } |
6105 | ||
222d21aa AK |
6106 | static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, |
6107 | u32 pmc, u64 *pdata) | |
6108 | { | |
c6702c9d | 6109 | return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); |
222d21aa AK |
6110 | } |
6111 | ||
6c3287f7 AK |
6112 | static void emulator_halt(struct x86_emulate_ctxt *ctxt) |
6113 | { | |
6114 | emul_to_vcpu(ctxt)->arch.halt_request = 1; | |
6115 | } | |
6116 | ||
2953538e | 6117 | static int emulator_intercept(struct x86_emulate_ctxt *ctxt, |
8a76d7f2 | 6118 | struct x86_instruction_info *info, |
c4f035c6 AK |
6119 | enum x86_intercept_stage stage) |
6120 | { | |
2953538e | 6121 | return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); |
c4f035c6 AK |
6122 | } |
6123 | ||
e911eb3b YZ |
6124 | static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, |
6125 | u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit) | |
bdb42f5a | 6126 | { |
e911eb3b | 6127 | return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit); |
bdb42f5a SB |
6128 | } |
6129 | ||
dd856efa AK |
6130 | static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) |
6131 | { | |
6132 | return kvm_register_read(emul_to_vcpu(ctxt), reg); | |
6133 | } | |
6134 | ||
6135 | static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) | |
6136 | { | |
6137 | kvm_register_write(emul_to_vcpu(ctxt), reg, val); | |
6138 | } | |
6139 | ||
801806d9 NA |
6140 | static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) |
6141 | { | |
6142 | kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked); | |
6143 | } | |
6144 | ||
6ed071f0 LP |
6145 | static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) |
6146 | { | |
6147 | return emul_to_vcpu(ctxt)->arch.hflags; | |
6148 | } | |
6149 | ||
6150 | static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags) | |
6151 | { | |
c5833c7a | 6152 | emul_to_vcpu(ctxt)->arch.hflags = emul_flags; |
6ed071f0 LP |
6153 | } |
6154 | ||
ed19321f SC |
6155 | static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, |
6156 | const char *smstate) | |
0234bf88 | 6157 | { |
ed19321f | 6158 | return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate); |
0234bf88 LP |
6159 | } |
6160 | ||
c5833c7a SC |
6161 | static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt) |
6162 | { | |
6163 | kvm_smm_changed(emul_to_vcpu(ctxt)); | |
6164 | } | |
6165 | ||
02d4160f VK |
6166 | static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) |
6167 | { | |
6168 | return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); | |
6169 | } | |
6170 | ||
0225fb50 | 6171 | static const struct x86_emulate_ops emulate_ops = { |
dd856efa AK |
6172 | .read_gpr = emulator_read_gpr, |
6173 | .write_gpr = emulator_write_gpr, | |
ce14e868 PB |
6174 | .read_std = emulator_read_std, |
6175 | .write_std = emulator_write_std, | |
7a036a6f | 6176 | .read_phys = kvm_read_guest_phys_system, |
1871c602 | 6177 | .fetch = kvm_fetch_guest_virt, |
bbd9b64e CO |
6178 | .read_emulated = emulator_read_emulated, |
6179 | .write_emulated = emulator_write_emulated, | |
6180 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
3cb16fe7 | 6181 | .invlpg = emulator_invlpg, |
cf8f70bf GN |
6182 | .pio_in_emulated = emulator_pio_in_emulated, |
6183 | .pio_out_emulated = emulator_pio_out_emulated, | |
1aa36616 AK |
6184 | .get_segment = emulator_get_segment, |
6185 | .set_segment = emulator_set_segment, | |
5951c442 | 6186 | .get_cached_segment_base = emulator_get_cached_segment_base, |
2dafc6c2 | 6187 | .get_gdt = emulator_get_gdt, |
160ce1f1 | 6188 | .get_idt = emulator_get_idt, |
1ac9d0cf AK |
6189 | .set_gdt = emulator_set_gdt, |
6190 | .set_idt = emulator_set_idt, | |
52a46617 GN |
6191 | .get_cr = emulator_get_cr, |
6192 | .set_cr = emulator_set_cr, | |
9c537244 | 6193 | .cpl = emulator_get_cpl, |
35aa5375 GN |
6194 | .get_dr = emulator_get_dr, |
6195 | .set_dr = emulator_set_dr, | |
64d60670 PB |
6196 | .get_smbase = emulator_get_smbase, |
6197 | .set_smbase = emulator_set_smbase, | |
717746e3 AK |
6198 | .set_msr = emulator_set_msr, |
6199 | .get_msr = emulator_get_msr, | |
67f4d428 | 6200 | .check_pmc = emulator_check_pmc, |
222d21aa | 6201 | .read_pmc = emulator_read_pmc, |
6c3287f7 | 6202 | .halt = emulator_halt, |
bcaf5cc5 | 6203 | .wbinvd = emulator_wbinvd, |
d6aa1000 | 6204 | .fix_hypercall = emulator_fix_hypercall, |
c4f035c6 | 6205 | .intercept = emulator_intercept, |
bdb42f5a | 6206 | .get_cpuid = emulator_get_cpuid, |
801806d9 | 6207 | .set_nmi_mask = emulator_set_nmi_mask, |
6ed071f0 LP |
6208 | .get_hflags = emulator_get_hflags, |
6209 | .set_hflags = emulator_set_hflags, | |
0234bf88 | 6210 | .pre_leave_smm = emulator_pre_leave_smm, |
c5833c7a | 6211 | .post_leave_smm = emulator_post_leave_smm, |
02d4160f | 6212 | .set_xcr = emulator_set_xcr, |
bbd9b64e CO |
6213 | }; |
6214 | ||
95cb2295 GN |
6215 | static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) |
6216 | { | |
37ccdcbe | 6217 | u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); |
95cb2295 GN |
6218 | /* |
6219 | * an sti; sti; sequence only disable interrupts for the first | |
6220 | * instruction. So, if the last instruction, be it emulated or | |
6221 | * not, left the system with the INT_STI flag enabled, it | |
6222 | * means that the last instruction is an sti. We should not | |
6223 | * leave the flag on in this case. The same goes for mov ss | |
6224 | */ | |
37ccdcbe PB |
6225 | if (int_shadow & mask) |
6226 | mask = 0; | |
6addfc42 | 6227 | if (unlikely(int_shadow || mask)) { |
95cb2295 | 6228 | kvm_x86_ops->set_interrupt_shadow(vcpu, mask); |
6addfc42 PB |
6229 | if (!mask) |
6230 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
6231 | } | |
95cb2295 GN |
6232 | } |
6233 | ||
ef54bcfe | 6234 | static bool inject_emulated_exception(struct kvm_vcpu *vcpu) |
54b8486f GN |
6235 | { |
6236 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; | |
da9cb575 | 6237 | if (ctxt->exception.vector == PF_VECTOR) |
ef54bcfe PB |
6238 | return kvm_propagate_fault(vcpu, &ctxt->exception); |
6239 | ||
6240 | if (ctxt->exception.error_code_valid) | |
da9cb575 AK |
6241 | kvm_queue_exception_e(vcpu, ctxt->exception.vector, |
6242 | ctxt->exception.error_code); | |
54b8486f | 6243 | else |
da9cb575 | 6244 | kvm_queue_exception(vcpu, ctxt->exception.vector); |
ef54bcfe | 6245 | return false; |
54b8486f GN |
6246 | } |
6247 | ||
8ec4722d MG |
6248 | static void init_emulate_ctxt(struct kvm_vcpu *vcpu) |
6249 | { | |
adf52235 | 6250 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
8ec4722d MG |
6251 | int cs_db, cs_l; |
6252 | ||
8ec4722d MG |
6253 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
6254 | ||
adf52235 | 6255 | ctxt->eflags = kvm_get_rflags(vcpu); |
c8401dda PB |
6256 | ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; |
6257 | ||
adf52235 TY |
6258 | ctxt->eip = kvm_rip_read(vcpu); |
6259 | ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : | |
6260 | (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : | |
42bf549f | 6261 | (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : |
adf52235 TY |
6262 | cs_db ? X86EMUL_MODE_PROT32 : |
6263 | X86EMUL_MODE_PROT16; | |
a584539b | 6264 | BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); |
64d60670 PB |
6265 | BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); |
6266 | BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); | |
adf52235 | 6267 | |
dd856efa | 6268 | init_decode_cache(ctxt); |
7ae441ea | 6269 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; |
8ec4722d MG |
6270 | } |
6271 | ||
71f9833b | 6272 | int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) |
63995653 | 6273 | { |
9d74191a | 6274 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
63995653 MG |
6275 | int ret; |
6276 | ||
6277 | init_emulate_ctxt(vcpu); | |
6278 | ||
9dac77fa AK |
6279 | ctxt->op_bytes = 2; |
6280 | ctxt->ad_bytes = 2; | |
6281 | ctxt->_eip = ctxt->eip + inc_eip; | |
9d74191a | 6282 | ret = emulate_int_real(ctxt, irq); |
63995653 MG |
6283 | |
6284 | if (ret != X86EMUL_CONTINUE) | |
6285 | return EMULATE_FAIL; | |
6286 | ||
9dac77fa | 6287 | ctxt->eip = ctxt->_eip; |
9d74191a TY |
6288 | kvm_rip_write(vcpu, ctxt->eip); |
6289 | kvm_set_rflags(vcpu, ctxt->eflags); | |
63995653 | 6290 | |
63995653 MG |
6291 | return EMULATE_DONE; |
6292 | } | |
6293 | EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); | |
6294 | ||
e2366171 | 6295 | static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) |
6d77dbfc | 6296 | { |
fc3a9157 JR |
6297 | int r = EMULATE_DONE; |
6298 | ||
6d77dbfc GN |
6299 | ++vcpu->stat.insn_emulation_fail; |
6300 | trace_kvm_emulate_insn_failed(vcpu); | |
e2366171 LA |
6301 | |
6302 | if (emulation_type & EMULTYPE_NO_UD_ON_FAIL) | |
6303 | return EMULATE_FAIL; | |
6304 | ||
a2b9e6c1 | 6305 | if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) { |
fc3a9157 JR |
6306 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
6307 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
6308 | vcpu->run->internal.ndata = 0; | |
1f4dcb3b | 6309 | r = EMULATE_USER_EXIT; |
fc3a9157 | 6310 | } |
e2366171 | 6311 | |
6d77dbfc | 6312 | kvm_queue_exception(vcpu, UD_VECTOR); |
fc3a9157 JR |
6313 | |
6314 | return r; | |
6d77dbfc GN |
6315 | } |
6316 | ||
93c05d3e | 6317 | static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, |
991eebf9 GN |
6318 | bool write_fault_to_shadow_pgtable, |
6319 | int emulation_type) | |
a6f177ef | 6320 | { |
95b3cf69 | 6321 | gpa_t gpa = cr2; |
ba049e93 | 6322 | kvm_pfn_t pfn; |
a6f177ef | 6323 | |
384bf221 | 6324 | if (!(emulation_type & EMULTYPE_ALLOW_RETRY)) |
991eebf9 GN |
6325 | return false; |
6326 | ||
6c3dfeb6 SC |
6327 | if (WARN_ON_ONCE(is_guest_mode(vcpu))) |
6328 | return false; | |
6329 | ||
44dd3ffa | 6330 | if (!vcpu->arch.mmu->direct_map) { |
95b3cf69 XG |
6331 | /* |
6332 | * Write permission should be allowed since only | |
6333 | * write access need to be emulated. | |
6334 | */ | |
6335 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); | |
a6f177ef | 6336 | |
95b3cf69 XG |
6337 | /* |
6338 | * If the mapping is invalid in guest, let cpu retry | |
6339 | * it to generate fault. | |
6340 | */ | |
6341 | if (gpa == UNMAPPED_GVA) | |
6342 | return true; | |
6343 | } | |
a6f177ef | 6344 | |
8e3d9d06 XG |
6345 | /* |
6346 | * Do not retry the unhandleable instruction if it faults on the | |
6347 | * readonly host memory, otherwise it will goto a infinite loop: | |
6348 | * retry instruction -> write #PF -> emulation fail -> retry | |
6349 | * instruction -> ... | |
6350 | */ | |
6351 | pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); | |
95b3cf69 XG |
6352 | |
6353 | /* | |
6354 | * If the instruction failed on the error pfn, it can not be fixed, | |
6355 | * report the error to userspace. | |
6356 | */ | |
6357 | if (is_error_noslot_pfn(pfn)) | |
6358 | return false; | |
6359 | ||
6360 | kvm_release_pfn_clean(pfn); | |
6361 | ||
6362 | /* The instructions are well-emulated on direct mmu. */ | |
44dd3ffa | 6363 | if (vcpu->arch.mmu->direct_map) { |
95b3cf69 XG |
6364 | unsigned int indirect_shadow_pages; |
6365 | ||
6366 | spin_lock(&vcpu->kvm->mmu_lock); | |
6367 | indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; | |
6368 | spin_unlock(&vcpu->kvm->mmu_lock); | |
6369 | ||
6370 | if (indirect_shadow_pages) | |
6371 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
6372 | ||
a6f177ef | 6373 | return true; |
8e3d9d06 | 6374 | } |
a6f177ef | 6375 | |
95b3cf69 XG |
6376 | /* |
6377 | * if emulation was due to access to shadowed page table | |
6378 | * and it failed try to unshadow page and re-enter the | |
6379 | * guest to let CPU execute the instruction. | |
6380 | */ | |
6381 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
93c05d3e XG |
6382 | |
6383 | /* | |
6384 | * If the access faults on its page table, it can not | |
6385 | * be fixed by unprotecting shadow page and it should | |
6386 | * be reported to userspace. | |
6387 | */ | |
6388 | return !write_fault_to_shadow_pgtable; | |
a6f177ef GN |
6389 | } |
6390 | ||
1cb3f3ae XG |
6391 | static bool retry_instruction(struct x86_emulate_ctxt *ctxt, |
6392 | unsigned long cr2, int emulation_type) | |
6393 | { | |
6394 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
6395 | unsigned long last_retry_eip, last_retry_addr, gpa = cr2; | |
6396 | ||
6397 | last_retry_eip = vcpu->arch.last_retry_eip; | |
6398 | last_retry_addr = vcpu->arch.last_retry_addr; | |
6399 | ||
6400 | /* | |
6401 | * If the emulation is caused by #PF and it is non-page_table | |
6402 | * writing instruction, it means the VM-EXIT is caused by shadow | |
6403 | * page protected, we can zap the shadow page and retry this | |
6404 | * instruction directly. | |
6405 | * | |
6406 | * Note: if the guest uses a non-page-table modifying instruction | |
6407 | * on the PDE that points to the instruction, then we will unmap | |
6408 | * the instruction and go to an infinite loop. So, we cache the | |
6409 | * last retried eip and the last fault address, if we meet the eip | |
6410 | * and the address again, we can break out of the potential infinite | |
6411 | * loop. | |
6412 | */ | |
6413 | vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; | |
6414 | ||
384bf221 | 6415 | if (!(emulation_type & EMULTYPE_ALLOW_RETRY)) |
1cb3f3ae XG |
6416 | return false; |
6417 | ||
6c3dfeb6 SC |
6418 | if (WARN_ON_ONCE(is_guest_mode(vcpu))) |
6419 | return false; | |
6420 | ||
1cb3f3ae XG |
6421 | if (x86_page_table_writing_insn(ctxt)) |
6422 | return false; | |
6423 | ||
6424 | if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) | |
6425 | return false; | |
6426 | ||
6427 | vcpu->arch.last_retry_eip = ctxt->eip; | |
6428 | vcpu->arch.last_retry_addr = cr2; | |
6429 | ||
44dd3ffa | 6430 | if (!vcpu->arch.mmu->direct_map) |
1cb3f3ae XG |
6431 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); |
6432 | ||
22368028 | 6433 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); |
1cb3f3ae XG |
6434 | |
6435 | return true; | |
6436 | } | |
6437 | ||
716d51ab GN |
6438 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu); |
6439 | static int complete_emulated_pio(struct kvm_vcpu *vcpu); | |
6440 | ||
64d60670 | 6441 | static void kvm_smm_changed(struct kvm_vcpu *vcpu) |
a584539b | 6442 | { |
64d60670 | 6443 | if (!(vcpu->arch.hflags & HF_SMM_MASK)) { |
660a5d51 PB |
6444 | /* This is a good place to trace that we are exiting SMM. */ |
6445 | trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); | |
6446 | ||
c43203ca PB |
6447 | /* Process a latched INIT or SMI, if any. */ |
6448 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
64d60670 | 6449 | } |
699023e2 PB |
6450 | |
6451 | kvm_mmu_reset_context(vcpu); | |
64d60670 PB |
6452 | } |
6453 | ||
4a1e10d5 PB |
6454 | static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, |
6455 | unsigned long *db) | |
6456 | { | |
6457 | u32 dr6 = 0; | |
6458 | int i; | |
6459 | u32 enable, rwlen; | |
6460 | ||
6461 | enable = dr7; | |
6462 | rwlen = dr7 >> 16; | |
6463 | for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) | |
6464 | if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) | |
6465 | dr6 |= (1 << i); | |
6466 | return dr6; | |
6467 | } | |
6468 | ||
c8401dda | 6469 | static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r) |
663f4c61 PB |
6470 | { |
6471 | struct kvm_run *kvm_run = vcpu->run; | |
6472 | ||
c8401dda PB |
6473 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { |
6474 | kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM; | |
6475 | kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; | |
6476 | kvm_run->debug.arch.exception = DB_VECTOR; | |
6477 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
6478 | *r = EMULATE_USER_EXIT; | |
6479 | } else { | |
f10c729f | 6480 | kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); |
663f4c61 PB |
6481 | } |
6482 | } | |
6483 | ||
6affcbed KH |
6484 | int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) |
6485 | { | |
6486 | unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); | |
f8ea7c60 | 6487 | int r; |
6affcbed | 6488 | |
f8ea7c60 VK |
6489 | r = kvm_x86_ops->skip_emulated_instruction(vcpu); |
6490 | if (unlikely(r != EMULATE_DONE)) | |
6491 | return 0; | |
c8401dda PB |
6492 | |
6493 | /* | |
6494 | * rflags is the old, "raw" value of the flags. The new value has | |
6495 | * not been saved yet. | |
6496 | * | |
6497 | * This is correct even for TF set by the guest, because "the | |
6498 | * processor will not generate this exception after the instruction | |
6499 | * that sets the TF flag". | |
6500 | */ | |
6501 | if (unlikely(rflags & X86_EFLAGS_TF)) | |
6502 | kvm_vcpu_do_singlestep(vcpu, &r); | |
6affcbed KH |
6503 | return r == EMULATE_DONE; |
6504 | } | |
6505 | EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); | |
6506 | ||
4a1e10d5 PB |
6507 | static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) |
6508 | { | |
4a1e10d5 PB |
6509 | if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && |
6510 | (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { | |
82b32774 NA |
6511 | struct kvm_run *kvm_run = vcpu->run; |
6512 | unsigned long eip = kvm_get_linear_rip(vcpu); | |
6513 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
6514 | vcpu->arch.guest_debug_dr7, |
6515 | vcpu->arch.eff_db); | |
6516 | ||
6517 | if (dr6 != 0) { | |
6f43ed01 | 6518 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; |
82b32774 | 6519 | kvm_run->debug.arch.pc = eip; |
4a1e10d5 PB |
6520 | kvm_run->debug.arch.exception = DB_VECTOR; |
6521 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
6522 | *r = EMULATE_USER_EXIT; | |
6523 | return true; | |
6524 | } | |
6525 | } | |
6526 | ||
4161a569 NA |
6527 | if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && |
6528 | !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { | |
82b32774 NA |
6529 | unsigned long eip = kvm_get_linear_rip(vcpu); |
6530 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
6531 | vcpu->arch.dr7, |
6532 | vcpu->arch.db); | |
6533 | ||
6534 | if (dr6 != 0) { | |
1fc5d194 | 6535 | vcpu->arch.dr6 &= ~DR_TRAP_BITS; |
6f43ed01 | 6536 | vcpu->arch.dr6 |= dr6 | DR6_RTM; |
4a1e10d5 PB |
6537 | kvm_queue_exception(vcpu, DB_VECTOR); |
6538 | *r = EMULATE_DONE; | |
6539 | return true; | |
6540 | } | |
6541 | } | |
6542 | ||
6543 | return false; | |
6544 | } | |
6545 | ||
04789b66 LA |
6546 | static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) |
6547 | { | |
2d7921c4 AM |
6548 | switch (ctxt->opcode_len) { |
6549 | case 1: | |
6550 | switch (ctxt->b) { | |
6551 | case 0xe4: /* IN */ | |
6552 | case 0xe5: | |
6553 | case 0xec: | |
6554 | case 0xed: | |
6555 | case 0xe6: /* OUT */ | |
6556 | case 0xe7: | |
6557 | case 0xee: | |
6558 | case 0xef: | |
6559 | case 0x6c: /* INS */ | |
6560 | case 0x6d: | |
6561 | case 0x6e: /* OUTS */ | |
6562 | case 0x6f: | |
6563 | return true; | |
6564 | } | |
6565 | break; | |
6566 | case 2: | |
6567 | switch (ctxt->b) { | |
6568 | case 0x33: /* RDPMC */ | |
6569 | return true; | |
6570 | } | |
6571 | break; | |
04789b66 LA |
6572 | } |
6573 | ||
6574 | return false; | |
6575 | } | |
6576 | ||
51d8b661 AP |
6577 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, |
6578 | unsigned long cr2, | |
dc25e89e AP |
6579 | int emulation_type, |
6580 | void *insn, | |
6581 | int insn_len) | |
bbd9b64e | 6582 | { |
95cb2295 | 6583 | int r; |
9d74191a | 6584 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
7ae441ea | 6585 | bool writeback = true; |
93c05d3e | 6586 | bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; |
bbd9b64e | 6587 | |
c595ceee PB |
6588 | vcpu->arch.l1tf_flush_l1d = true; |
6589 | ||
93c05d3e XG |
6590 | /* |
6591 | * Clear write_fault_to_shadow_pgtable here to ensure it is | |
6592 | * never reused. | |
6593 | */ | |
6594 | vcpu->arch.write_fault_to_shadow_pgtable = false; | |
26eef70c | 6595 | kvm_clear_exception_queue(vcpu); |
8d7d8102 | 6596 | |
571008da | 6597 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
8ec4722d | 6598 | init_emulate_ctxt(vcpu); |
4a1e10d5 PB |
6599 | |
6600 | /* | |
6601 | * We will reenter on the same instruction since | |
6602 | * we do not set complete_userspace_io. This does not | |
6603 | * handle watchpoints yet, those would be handled in | |
6604 | * the emulate_ops. | |
6605 | */ | |
d391f120 VK |
6606 | if (!(emulation_type & EMULTYPE_SKIP) && |
6607 | kvm_vcpu_check_breakpoint(vcpu, &r)) | |
4a1e10d5 PB |
6608 | return r; |
6609 | ||
9d74191a TY |
6610 | ctxt->interruptibility = 0; |
6611 | ctxt->have_exception = false; | |
e0ad0b47 | 6612 | ctxt->exception.vector = -1; |
9d74191a | 6613 | ctxt->perm_ok = false; |
bbd9b64e | 6614 | |
b51e974f | 6615 | ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; |
4005996e | 6616 | |
9d74191a | 6617 | r = x86_decode_insn(ctxt, insn, insn_len); |
bbd9b64e | 6618 | |
e46479f8 | 6619 | trace_kvm_emulate_insn_start(vcpu); |
f2b5756b | 6620 | ++vcpu->stat.insn_emulation; |
1d2887e2 | 6621 | if (r != EMULATION_OK) { |
4005996e AK |
6622 | if (emulation_type & EMULTYPE_TRAP_UD) |
6623 | return EMULATE_FAIL; | |
991eebf9 GN |
6624 | if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, |
6625 | emulation_type)) | |
bbd9b64e | 6626 | return EMULATE_DONE; |
8530a79c | 6627 | if (ctxt->have_exception) { |
c8848cee JD |
6628 | /* |
6629 | * #UD should result in just EMULATION_FAILED, and trap-like | |
6630 | * exception should not be encountered during decode. | |
6631 | */ | |
6632 | WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || | |
6633 | exception_type(ctxt->exception.vector) == EXCPT_TRAP); | |
8530a79c | 6634 | inject_emulated_exception(vcpu); |
6ea6e843 | 6635 | return EMULATE_DONE; |
8530a79c | 6636 | } |
6d77dbfc GN |
6637 | if (emulation_type & EMULTYPE_SKIP) |
6638 | return EMULATE_FAIL; | |
e2366171 | 6639 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
6640 | } |
6641 | } | |
6642 | ||
04789b66 LA |
6643 | if ((emulation_type & EMULTYPE_VMWARE) && |
6644 | !is_vmware_backdoor_opcode(ctxt)) | |
6645 | return EMULATE_FAIL; | |
6646 | ||
ba8afb6b | 6647 | if (emulation_type & EMULTYPE_SKIP) { |
9dac77fa | 6648 | kvm_rip_write(vcpu, ctxt->_eip); |
bb663c7a NA |
6649 | if (ctxt->eflags & X86_EFLAGS_RF) |
6650 | kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); | |
97413d29 | 6651 | kvm_x86_ops->set_interrupt_shadow(vcpu, 0); |
ba8afb6b GN |
6652 | return EMULATE_DONE; |
6653 | } | |
6654 | ||
1cb3f3ae XG |
6655 | if (retry_instruction(ctxt, cr2, emulation_type)) |
6656 | return EMULATE_DONE; | |
6657 | ||
7ae441ea | 6658 | /* this is needed for vmware backdoor interface to work since it |
4d2179e1 | 6659 | changes registers values during IO operation */ |
7ae441ea GN |
6660 | if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { |
6661 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; | |
dd856efa | 6662 | emulator_invalidate_register_cache(ctxt); |
7ae441ea | 6663 | } |
4d2179e1 | 6664 | |
5cd21917 | 6665 | restart: |
0f89b207 TL |
6666 | /* Save the faulting GPA (cr2) in the address field */ |
6667 | ctxt->exception.address = cr2; | |
6668 | ||
9d74191a | 6669 | r = x86_emulate_insn(ctxt); |
bbd9b64e | 6670 | |
775fde86 JR |
6671 | if (r == EMULATION_INTERCEPTED) |
6672 | return EMULATE_DONE; | |
6673 | ||
d2ddd1c4 | 6674 | if (r == EMULATION_FAILED) { |
991eebf9 GN |
6675 | if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, |
6676 | emulation_type)) | |
c3cd7ffa GN |
6677 | return EMULATE_DONE; |
6678 | ||
e2366171 | 6679 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
6680 | } |
6681 | ||
9d74191a | 6682 | if (ctxt->have_exception) { |
d2ddd1c4 | 6683 | r = EMULATE_DONE; |
ef54bcfe PB |
6684 | if (inject_emulated_exception(vcpu)) |
6685 | return r; | |
d2ddd1c4 | 6686 | } else if (vcpu->arch.pio.count) { |
0912c977 PB |
6687 | if (!vcpu->arch.pio.in) { |
6688 | /* FIXME: return into emulator if single-stepping. */ | |
3457e419 | 6689 | vcpu->arch.pio.count = 0; |
0912c977 | 6690 | } else { |
7ae441ea | 6691 | writeback = false; |
716d51ab GN |
6692 | vcpu->arch.complete_userspace_io = complete_emulated_pio; |
6693 | } | |
ac0a48c3 | 6694 | r = EMULATE_USER_EXIT; |
7ae441ea GN |
6695 | } else if (vcpu->mmio_needed) { |
6696 | if (!vcpu->mmio_is_write) | |
6697 | writeback = false; | |
ac0a48c3 | 6698 | r = EMULATE_USER_EXIT; |
716d51ab | 6699 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; |
7ae441ea | 6700 | } else if (r == EMULATION_RESTART) |
5cd21917 | 6701 | goto restart; |
d2ddd1c4 GN |
6702 | else |
6703 | r = EMULATE_DONE; | |
f850e2e6 | 6704 | |
7ae441ea | 6705 | if (writeback) { |
6addfc42 | 6706 | unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); |
9d74191a | 6707 | toggle_interruptibility(vcpu, ctxt->interruptibility); |
7ae441ea | 6708 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
38827dbd | 6709 | if (!ctxt->have_exception || |
75ee23b3 SC |
6710 | exception_type(ctxt->exception.vector) == EXCPT_TRAP) { |
6711 | kvm_rip_write(vcpu, ctxt->eip); | |
6712 | if (r == EMULATE_DONE && ctxt->tf) | |
6713 | kvm_vcpu_do_singlestep(vcpu, &r); | |
38827dbd | 6714 | __kvm_set_rflags(vcpu, ctxt->eflags); |
75ee23b3 | 6715 | } |
6addfc42 PB |
6716 | |
6717 | /* | |
6718 | * For STI, interrupts are shadowed; so KVM_REQ_EVENT will | |
6719 | * do nothing, and it will be requested again as soon as | |
6720 | * the shadow expires. But we still need to check here, | |
6721 | * because POPF has no interrupt shadow. | |
6722 | */ | |
6723 | if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) | |
6724 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7ae441ea GN |
6725 | } else |
6726 | vcpu->arch.emulate_regs_need_sync_to_vcpu = true; | |
e85d28f8 GN |
6727 | |
6728 | return r; | |
de7d789a | 6729 | } |
c60658d1 SC |
6730 | |
6731 | int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) | |
6732 | { | |
6733 | return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); | |
6734 | } | |
6735 | EXPORT_SYMBOL_GPL(kvm_emulate_instruction); | |
6736 | ||
6737 | int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, | |
6738 | void *insn, int insn_len) | |
6739 | { | |
6740 | return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); | |
6741 | } | |
6742 | EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); | |
de7d789a | 6743 | |
8764ed55 SC |
6744 | static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) |
6745 | { | |
6746 | vcpu->arch.pio.count = 0; | |
6747 | return 1; | |
6748 | } | |
6749 | ||
45def77e SC |
6750 | static int complete_fast_pio_out(struct kvm_vcpu *vcpu) |
6751 | { | |
6752 | vcpu->arch.pio.count = 0; | |
6753 | ||
6754 | if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) | |
6755 | return 1; | |
6756 | ||
6757 | return kvm_skip_emulated_instruction(vcpu); | |
6758 | } | |
6759 | ||
dca7f128 SC |
6760 | static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, |
6761 | unsigned short port) | |
de7d789a | 6762 | { |
de3cd117 | 6763 | unsigned long val = kvm_rax_read(vcpu); |
ca1d4a9e AK |
6764 | int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, |
6765 | size, port, &val, 1); | |
8764ed55 SC |
6766 | if (ret) |
6767 | return ret; | |
45def77e | 6768 | |
8764ed55 SC |
6769 | /* |
6770 | * Workaround userspace that relies on old KVM behavior of %rip being | |
6771 | * incremented prior to exiting to userspace to handle "OUT 0x7e". | |
6772 | */ | |
6773 | if (port == 0x7e && | |
6774 | kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { | |
6775 | vcpu->arch.complete_userspace_io = | |
6776 | complete_fast_pio_out_port_0x7e; | |
6777 | kvm_skip_emulated_instruction(vcpu); | |
6778 | } else { | |
45def77e SC |
6779 | vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); |
6780 | vcpu->arch.complete_userspace_io = complete_fast_pio_out; | |
6781 | } | |
8764ed55 | 6782 | return 0; |
de7d789a | 6783 | } |
de7d789a | 6784 | |
8370c3d0 TL |
6785 | static int complete_fast_pio_in(struct kvm_vcpu *vcpu) |
6786 | { | |
6787 | unsigned long val; | |
6788 | ||
6789 | /* We should only ever be called with arch.pio.count equal to 1 */ | |
6790 | BUG_ON(vcpu->arch.pio.count != 1); | |
6791 | ||
45def77e SC |
6792 | if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { |
6793 | vcpu->arch.pio.count = 0; | |
6794 | return 1; | |
6795 | } | |
6796 | ||
8370c3d0 | 6797 | /* For size less than 4 we merge, else we zero extend */ |
de3cd117 | 6798 | val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; |
8370c3d0 TL |
6799 | |
6800 | /* | |
6801 | * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform | |
6802 | * the copy and tracing | |
6803 | */ | |
6804 | emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size, | |
6805 | vcpu->arch.pio.port, &val, 1); | |
de3cd117 | 6806 | kvm_rax_write(vcpu, val); |
8370c3d0 | 6807 | |
45def77e | 6808 | return kvm_skip_emulated_instruction(vcpu); |
8370c3d0 TL |
6809 | } |
6810 | ||
dca7f128 SC |
6811 | static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, |
6812 | unsigned short port) | |
8370c3d0 TL |
6813 | { |
6814 | unsigned long val; | |
6815 | int ret; | |
6816 | ||
6817 | /* For size less than 4 we merge, else we zero extend */ | |
de3cd117 | 6818 | val = (size < 4) ? kvm_rax_read(vcpu) : 0; |
8370c3d0 TL |
6819 | |
6820 | ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port, | |
6821 | &val, 1); | |
6822 | if (ret) { | |
de3cd117 | 6823 | kvm_rax_write(vcpu, val); |
8370c3d0 TL |
6824 | return ret; |
6825 | } | |
6826 | ||
45def77e | 6827 | vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); |
8370c3d0 TL |
6828 | vcpu->arch.complete_userspace_io = complete_fast_pio_in; |
6829 | ||
6830 | return 0; | |
6831 | } | |
dca7f128 SC |
6832 | |
6833 | int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) | |
6834 | { | |
45def77e | 6835 | int ret; |
dca7f128 | 6836 | |
dca7f128 | 6837 | if (in) |
45def77e | 6838 | ret = kvm_fast_pio_in(vcpu, size, port); |
dca7f128 | 6839 | else |
45def77e SC |
6840 | ret = kvm_fast_pio_out(vcpu, size, port); |
6841 | return ret && kvm_skip_emulated_instruction(vcpu); | |
dca7f128 SC |
6842 | } |
6843 | EXPORT_SYMBOL_GPL(kvm_fast_pio); | |
8370c3d0 | 6844 | |
251a5fd6 | 6845 | static int kvmclock_cpu_down_prep(unsigned int cpu) |
8cfdc000 | 6846 | { |
0a3aee0d | 6847 | __this_cpu_write(cpu_tsc_khz, 0); |
251a5fd6 | 6848 | return 0; |
8cfdc000 ZA |
6849 | } |
6850 | ||
6851 | static void tsc_khz_changed(void *data) | |
c8076604 | 6852 | { |
8cfdc000 ZA |
6853 | struct cpufreq_freqs *freq = data; |
6854 | unsigned long khz = 0; | |
6855 | ||
6856 | if (data) | |
6857 | khz = freq->new; | |
6858 | else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
6859 | khz = cpufreq_quick_get(raw_smp_processor_id()); | |
6860 | if (!khz) | |
6861 | khz = tsc_khz; | |
0a3aee0d | 6862 | __this_cpu_write(cpu_tsc_khz, khz); |
c8076604 GH |
6863 | } |
6864 | ||
5fa4ec9c | 6865 | #ifdef CONFIG_X86_64 |
0092e434 VK |
6866 | static void kvm_hyperv_tsc_notifier(void) |
6867 | { | |
0092e434 VK |
6868 | struct kvm *kvm; |
6869 | struct kvm_vcpu *vcpu; | |
6870 | int cpu; | |
6871 | ||
0d9ce162 | 6872 | mutex_lock(&kvm_lock); |
0092e434 VK |
6873 | list_for_each_entry(kvm, &vm_list, vm_list) |
6874 | kvm_make_mclock_inprogress_request(kvm); | |
6875 | ||
6876 | hyperv_stop_tsc_emulation(); | |
6877 | ||
6878 | /* TSC frequency always matches when on Hyper-V */ | |
6879 | for_each_present_cpu(cpu) | |
6880 | per_cpu(cpu_tsc_khz, cpu) = tsc_khz; | |
6881 | kvm_max_guest_tsc_khz = tsc_khz; | |
6882 | ||
6883 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
6884 | struct kvm_arch *ka = &kvm->arch; | |
6885 | ||
6886 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
6887 | ||
6888 | pvclock_update_vm_gtod_copy(kvm); | |
6889 | ||
6890 | kvm_for_each_vcpu(cpu, vcpu, kvm) | |
6891 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
6892 | ||
6893 | kvm_for_each_vcpu(cpu, vcpu, kvm) | |
6894 | kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); | |
6895 | ||
6896 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
6897 | } | |
0d9ce162 | 6898 | mutex_unlock(&kvm_lock); |
0092e434 | 6899 | } |
5fa4ec9c | 6900 | #endif |
0092e434 | 6901 | |
df24014a | 6902 | static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) |
c8076604 | 6903 | { |
c8076604 GH |
6904 | struct kvm *kvm; |
6905 | struct kvm_vcpu *vcpu; | |
6906 | int i, send_ipi = 0; | |
6907 | ||
8cfdc000 ZA |
6908 | /* |
6909 | * We allow guests to temporarily run on slowing clocks, | |
6910 | * provided we notify them after, or to run on accelerating | |
6911 | * clocks, provided we notify them before. Thus time never | |
6912 | * goes backwards. | |
6913 | * | |
6914 | * However, we have a problem. We can't atomically update | |
6915 | * the frequency of a given CPU from this function; it is | |
6916 | * merely a notifier, which can be called from any CPU. | |
6917 | * Changing the TSC frequency at arbitrary points in time | |
6918 | * requires a recomputation of local variables related to | |
6919 | * the TSC for each VCPU. We must flag these local variables | |
6920 | * to be updated and be sure the update takes place with the | |
6921 | * new frequency before any guests proceed. | |
6922 | * | |
6923 | * Unfortunately, the combination of hotplug CPU and frequency | |
6924 | * change creates an intractable locking scenario; the order | |
6925 | * of when these callouts happen is undefined with respect to | |
6926 | * CPU hotplug, and they can race with each other. As such, | |
6927 | * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is | |
6928 | * undefined; you can actually have a CPU frequency change take | |
6929 | * place in between the computation of X and the setting of the | |
6930 | * variable. To protect against this problem, all updates of | |
6931 | * the per_cpu tsc_khz variable are done in an interrupt | |
6932 | * protected IPI, and all callers wishing to update the value | |
6933 | * must wait for a synchronous IPI to complete (which is trivial | |
6934 | * if the caller is on the CPU already). This establishes the | |
6935 | * necessary total order on variable updates. | |
6936 | * | |
6937 | * Note that because a guest time update may take place | |
6938 | * anytime after the setting of the VCPU's request bit, the | |
6939 | * correct TSC value must be set before the request. However, | |
6940 | * to ensure the update actually makes it to any guest which | |
6941 | * starts running in hardware virtualization between the set | |
6942 | * and the acquisition of the spinlock, we must also ping the | |
6943 | * CPU after setting the request bit. | |
6944 | * | |
6945 | */ | |
6946 | ||
df24014a | 6947 | smp_call_function_single(cpu, tsc_khz_changed, freq, 1); |
c8076604 | 6948 | |
0d9ce162 | 6949 | mutex_lock(&kvm_lock); |
c8076604 | 6950 | list_for_each_entry(kvm, &vm_list, vm_list) { |
988a2cae | 6951 | kvm_for_each_vcpu(i, vcpu, kvm) { |
df24014a | 6952 | if (vcpu->cpu != cpu) |
c8076604 | 6953 | continue; |
c285545f | 6954 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0d9ce162 | 6955 | if (vcpu->cpu != raw_smp_processor_id()) |
8cfdc000 | 6956 | send_ipi = 1; |
c8076604 GH |
6957 | } |
6958 | } | |
0d9ce162 | 6959 | mutex_unlock(&kvm_lock); |
c8076604 GH |
6960 | |
6961 | if (freq->old < freq->new && send_ipi) { | |
6962 | /* | |
6963 | * We upscale the frequency. Must make the guest | |
6964 | * doesn't see old kvmclock values while running with | |
6965 | * the new frequency, otherwise we risk the guest sees | |
6966 | * time go backwards. | |
6967 | * | |
6968 | * In case we update the frequency for another cpu | |
6969 | * (which might be in guest context) send an interrupt | |
6970 | * to kick the cpu out of guest context. Next time | |
6971 | * guest context is entered kvmclock will be updated, | |
6972 | * so the guest will not see stale values. | |
6973 | */ | |
df24014a | 6974 | smp_call_function_single(cpu, tsc_khz_changed, freq, 1); |
c8076604 | 6975 | } |
df24014a VK |
6976 | } |
6977 | ||
6978 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, | |
6979 | void *data) | |
6980 | { | |
6981 | struct cpufreq_freqs *freq = data; | |
6982 | int cpu; | |
6983 | ||
6984 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) | |
6985 | return 0; | |
6986 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
6987 | return 0; | |
6988 | ||
6989 | for_each_cpu(cpu, freq->policy->cpus) | |
6990 | __kvmclock_cpufreq_notifier(freq, cpu); | |
6991 | ||
c8076604 GH |
6992 | return 0; |
6993 | } | |
6994 | ||
6995 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
8cfdc000 ZA |
6996 | .notifier_call = kvmclock_cpufreq_notifier |
6997 | }; | |
6998 | ||
251a5fd6 | 6999 | static int kvmclock_cpu_online(unsigned int cpu) |
8cfdc000 | 7000 | { |
251a5fd6 SAS |
7001 | tsc_khz_changed(NULL); |
7002 | return 0; | |
8cfdc000 ZA |
7003 | } |
7004 | ||
b820cc0c ZA |
7005 | static void kvm_timer_init(void) |
7006 | { | |
c285545f | 7007 | max_tsc_khz = tsc_khz; |
460dd42e | 7008 | |
b820cc0c | 7009 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
c285545f ZA |
7010 | #ifdef CONFIG_CPU_FREQ |
7011 | struct cpufreq_policy policy; | |
758f588d BP |
7012 | int cpu; |
7013 | ||
c285545f | 7014 | memset(&policy, 0, sizeof(policy)); |
3e26f230 AK |
7015 | cpu = get_cpu(); |
7016 | cpufreq_get_policy(&policy, cpu); | |
c285545f ZA |
7017 | if (policy.cpuinfo.max_freq) |
7018 | max_tsc_khz = policy.cpuinfo.max_freq; | |
3e26f230 | 7019 | put_cpu(); |
c285545f | 7020 | #endif |
b820cc0c ZA |
7021 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
7022 | CPUFREQ_TRANSITION_NOTIFIER); | |
7023 | } | |
460dd42e | 7024 | |
73c1b41e | 7025 | cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", |
251a5fd6 | 7026 | kvmclock_cpu_online, kvmclock_cpu_down_prep); |
b820cc0c ZA |
7027 | } |
7028 | ||
dd60d217 AK |
7029 | DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); |
7030 | EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu); | |
ff9d07a0 | 7031 | |
f5132b01 | 7032 | int kvm_is_in_guest(void) |
ff9d07a0 | 7033 | { |
086c9855 | 7034 | return __this_cpu_read(current_vcpu) != NULL; |
ff9d07a0 ZY |
7035 | } |
7036 | ||
7037 | static int kvm_is_user_mode(void) | |
7038 | { | |
7039 | int user_mode = 3; | |
dcf46b94 | 7040 | |
086c9855 AS |
7041 | if (__this_cpu_read(current_vcpu)) |
7042 | user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 7043 | |
ff9d07a0 ZY |
7044 | return user_mode != 0; |
7045 | } | |
7046 | ||
7047 | static unsigned long kvm_get_guest_ip(void) | |
7048 | { | |
7049 | unsigned long ip = 0; | |
dcf46b94 | 7050 | |
086c9855 AS |
7051 | if (__this_cpu_read(current_vcpu)) |
7052 | ip = kvm_rip_read(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 7053 | |
ff9d07a0 ZY |
7054 | return ip; |
7055 | } | |
7056 | ||
8479e04e LK |
7057 | static void kvm_handle_intel_pt_intr(void) |
7058 | { | |
7059 | struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu); | |
7060 | ||
7061 | kvm_make_request(KVM_REQ_PMI, vcpu); | |
7062 | __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT, | |
7063 | (unsigned long *)&vcpu->arch.pmu.global_status); | |
7064 | } | |
7065 | ||
ff9d07a0 ZY |
7066 | static struct perf_guest_info_callbacks kvm_guest_cbs = { |
7067 | .is_in_guest = kvm_is_in_guest, | |
7068 | .is_user_mode = kvm_is_user_mode, | |
7069 | .get_guest_ip = kvm_get_guest_ip, | |
8479e04e | 7070 | .handle_intel_pt_intr = kvm_handle_intel_pt_intr, |
ff9d07a0 ZY |
7071 | }; |
7072 | ||
16e8d74d MT |
7073 | #ifdef CONFIG_X86_64 |
7074 | static void pvclock_gtod_update_fn(struct work_struct *work) | |
7075 | { | |
d828199e MT |
7076 | struct kvm *kvm; |
7077 | ||
7078 | struct kvm_vcpu *vcpu; | |
7079 | int i; | |
7080 | ||
0d9ce162 | 7081 | mutex_lock(&kvm_lock); |
d828199e MT |
7082 | list_for_each_entry(kvm, &vm_list, vm_list) |
7083 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 7084 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
d828199e | 7085 | atomic_set(&kvm_guest_has_master_clock, 0); |
0d9ce162 | 7086 | mutex_unlock(&kvm_lock); |
16e8d74d MT |
7087 | } |
7088 | ||
7089 | static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); | |
7090 | ||
7091 | /* | |
7092 | * Notification about pvclock gtod data update. | |
7093 | */ | |
7094 | static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, | |
7095 | void *priv) | |
7096 | { | |
7097 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
7098 | struct timekeeper *tk = priv; | |
7099 | ||
7100 | update_pvclock_gtod(tk); | |
7101 | ||
7102 | /* disable master clock if host does not trust, or does not | |
b0c39dc6 | 7103 | * use, TSC based clocksource. |
16e8d74d | 7104 | */ |
b0c39dc6 | 7105 | if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && |
16e8d74d MT |
7106 | atomic_read(&kvm_guest_has_master_clock) != 0) |
7107 | queue_work(system_long_wq, &pvclock_gtod_work); | |
7108 | ||
7109 | return 0; | |
7110 | } | |
7111 | ||
7112 | static struct notifier_block pvclock_gtod_notifier = { | |
7113 | .notifier_call = pvclock_gtod_notify, | |
7114 | }; | |
7115 | #endif | |
7116 | ||
f8c16bba | 7117 | int kvm_arch_init(void *opaque) |
043405e1 | 7118 | { |
b820cc0c | 7119 | int r; |
6b61edf7 | 7120 | struct kvm_x86_ops *ops = opaque; |
f8c16bba | 7121 | |
f8c16bba ZX |
7122 | if (kvm_x86_ops) { |
7123 | printk(KERN_ERR "kvm: already loaded the other module\n"); | |
56c6d28a ZX |
7124 | r = -EEXIST; |
7125 | goto out; | |
f8c16bba ZX |
7126 | } |
7127 | ||
7128 | if (!ops->cpu_has_kvm_support()) { | |
7129 | printk(KERN_ERR "kvm: no hardware support\n"); | |
56c6d28a ZX |
7130 | r = -EOPNOTSUPP; |
7131 | goto out; | |
f8c16bba ZX |
7132 | } |
7133 | if (ops->disabled_by_bios()) { | |
7134 | printk(KERN_ERR "kvm: disabled by bios\n"); | |
56c6d28a ZX |
7135 | r = -EOPNOTSUPP; |
7136 | goto out; | |
f8c16bba ZX |
7137 | } |
7138 | ||
b666a4b6 MO |
7139 | /* |
7140 | * KVM explicitly assumes that the guest has an FPU and | |
7141 | * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the | |
7142 | * vCPU's FPU state as a fxregs_state struct. | |
7143 | */ | |
7144 | if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { | |
7145 | printk(KERN_ERR "kvm: inadequate fpu\n"); | |
7146 | r = -EOPNOTSUPP; | |
7147 | goto out; | |
7148 | } | |
7149 | ||
013f6a5d | 7150 | r = -ENOMEM; |
ed8e4812 | 7151 | x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu), |
b666a4b6 MO |
7152 | __alignof__(struct fpu), SLAB_ACCOUNT, |
7153 | NULL); | |
7154 | if (!x86_fpu_cache) { | |
7155 | printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n"); | |
7156 | goto out; | |
7157 | } | |
7158 | ||
013f6a5d MT |
7159 | shared_msrs = alloc_percpu(struct kvm_shared_msrs); |
7160 | if (!shared_msrs) { | |
7161 | printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); | |
b666a4b6 | 7162 | goto out_free_x86_fpu_cache; |
013f6a5d MT |
7163 | } |
7164 | ||
97db56ce AK |
7165 | r = kvm_mmu_module_init(); |
7166 | if (r) | |
013f6a5d | 7167 | goto out_free_percpu; |
97db56ce | 7168 | |
f8c16bba | 7169 | kvm_x86_ops = ops; |
920c8377 | 7170 | |
7b52345e | 7171 | kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, |
ffb128c8 | 7172 | PT_DIRTY_MASK, PT64_NX_MASK, 0, |
d0ec49d4 | 7173 | PT_PRESENT_MASK, 0, sme_me_mask); |
b820cc0c | 7174 | kvm_timer_init(); |
c8076604 | 7175 | |
ff9d07a0 ZY |
7176 | perf_register_guest_info_callbacks(&kvm_guest_cbs); |
7177 | ||
d366bf7e | 7178 | if (boot_cpu_has(X86_FEATURE_XSAVE)) |
2acf923e DC |
7179 | host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); |
7180 | ||
c5cc421b | 7181 | kvm_lapic_init(); |
0c5f81da WL |
7182 | if (pi_inject_timer == -1) |
7183 | pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER); | |
16e8d74d MT |
7184 | #ifdef CONFIG_X86_64 |
7185 | pvclock_gtod_register_notifier(&pvclock_gtod_notifier); | |
0092e434 | 7186 | |
5fa4ec9c | 7187 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 | 7188 | set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); |
16e8d74d MT |
7189 | #endif |
7190 | ||
f8c16bba | 7191 | return 0; |
56c6d28a | 7192 | |
013f6a5d MT |
7193 | out_free_percpu: |
7194 | free_percpu(shared_msrs); | |
b666a4b6 MO |
7195 | out_free_x86_fpu_cache: |
7196 | kmem_cache_destroy(x86_fpu_cache); | |
56c6d28a | 7197 | out: |
56c6d28a | 7198 | return r; |
043405e1 | 7199 | } |
8776e519 | 7200 | |
f8c16bba ZX |
7201 | void kvm_arch_exit(void) |
7202 | { | |
0092e434 | 7203 | #ifdef CONFIG_X86_64 |
5fa4ec9c | 7204 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 VK |
7205 | clear_hv_tscchange_cb(); |
7206 | #endif | |
cef84c30 | 7207 | kvm_lapic_exit(); |
ff9d07a0 ZY |
7208 | perf_unregister_guest_info_callbacks(&kvm_guest_cbs); |
7209 | ||
888d256e JK |
7210 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
7211 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
7212 | CPUFREQ_TRANSITION_NOTIFIER); | |
251a5fd6 | 7213 | cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); |
16e8d74d MT |
7214 | #ifdef CONFIG_X86_64 |
7215 | pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); | |
7216 | #endif | |
f8c16bba | 7217 | kvm_x86_ops = NULL; |
56c6d28a | 7218 | kvm_mmu_module_exit(); |
013f6a5d | 7219 | free_percpu(shared_msrs); |
b666a4b6 | 7220 | kmem_cache_destroy(x86_fpu_cache); |
56c6d28a | 7221 | } |
f8c16bba | 7222 | |
5cb56059 | 7223 | int kvm_vcpu_halt(struct kvm_vcpu *vcpu) |
8776e519 HB |
7224 | { |
7225 | ++vcpu->stat.halt_exits; | |
35754c98 | 7226 | if (lapic_in_kernel(vcpu)) { |
a4535290 | 7227 | vcpu->arch.mp_state = KVM_MP_STATE_HALTED; |
8776e519 HB |
7228 | return 1; |
7229 | } else { | |
7230 | vcpu->run->exit_reason = KVM_EXIT_HLT; | |
7231 | return 0; | |
7232 | } | |
7233 | } | |
5cb56059 JS |
7234 | EXPORT_SYMBOL_GPL(kvm_vcpu_halt); |
7235 | ||
7236 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) | |
7237 | { | |
6affcbed KH |
7238 | int ret = kvm_skip_emulated_instruction(vcpu); |
7239 | /* | |
7240 | * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered | |
7241 | * KVM_EXIT_DEBUG here. | |
7242 | */ | |
7243 | return kvm_vcpu_halt(vcpu) && ret; | |
5cb56059 | 7244 | } |
8776e519 HB |
7245 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); |
7246 | ||
8ef81a9a | 7247 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
7248 | static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, |
7249 | unsigned long clock_type) | |
7250 | { | |
7251 | struct kvm_clock_pairing clock_pairing; | |
899a31f5 | 7252 | struct timespec64 ts; |
80fbd89c | 7253 | u64 cycle; |
55dd00a7 MT |
7254 | int ret; |
7255 | ||
7256 | if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) | |
7257 | return -KVM_EOPNOTSUPP; | |
7258 | ||
7259 | if (kvm_get_walltime_and_clockread(&ts, &cycle) == false) | |
7260 | return -KVM_EOPNOTSUPP; | |
7261 | ||
7262 | clock_pairing.sec = ts.tv_sec; | |
7263 | clock_pairing.nsec = ts.tv_nsec; | |
7264 | clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); | |
7265 | clock_pairing.flags = 0; | |
bcbfbd8e | 7266 | memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); |
55dd00a7 MT |
7267 | |
7268 | ret = 0; | |
7269 | if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, | |
7270 | sizeof(struct kvm_clock_pairing))) | |
7271 | ret = -KVM_EFAULT; | |
7272 | ||
7273 | return ret; | |
7274 | } | |
8ef81a9a | 7275 | #endif |
55dd00a7 | 7276 | |
6aef266c SV |
7277 | /* |
7278 | * kvm_pv_kick_cpu_op: Kick a vcpu. | |
7279 | * | |
7280 | * @apicid - apicid of vcpu to be kicked. | |
7281 | */ | |
7282 | static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) | |
7283 | { | |
24d2166b | 7284 | struct kvm_lapic_irq lapic_irq; |
6aef266c | 7285 | |
24d2166b R |
7286 | lapic_irq.shorthand = 0; |
7287 | lapic_irq.dest_mode = 0; | |
ebd28fcb | 7288 | lapic_irq.level = 0; |
24d2166b | 7289 | lapic_irq.dest_id = apicid; |
93bbf0b8 | 7290 | lapic_irq.msi_redir_hint = false; |
6aef266c | 7291 | |
24d2166b | 7292 | lapic_irq.delivery_mode = APIC_DM_REMRD; |
795a149e | 7293 | kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); |
6aef266c SV |
7294 | } |
7295 | ||
d62caabb AS |
7296 | void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu) |
7297 | { | |
f7589cca PB |
7298 | if (!lapic_in_kernel(vcpu)) { |
7299 | WARN_ON_ONCE(vcpu->arch.apicv_active); | |
7300 | return; | |
7301 | } | |
7302 | if (!vcpu->arch.apicv_active) | |
7303 | return; | |
7304 | ||
d62caabb AS |
7305 | vcpu->arch.apicv_active = false; |
7306 | kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu); | |
7307 | } | |
7308 | ||
71506297 WL |
7309 | static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id) |
7310 | { | |
7311 | struct kvm_vcpu *target = NULL; | |
7312 | struct kvm_apic_map *map; | |
7313 | ||
7314 | rcu_read_lock(); | |
7315 | map = rcu_dereference(kvm->arch.apic_map); | |
7316 | ||
7317 | if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) | |
7318 | target = map->phys_map[dest_id]->vcpu; | |
7319 | ||
7320 | rcu_read_unlock(); | |
7321 | ||
266e85a5 | 7322 | if (target && READ_ONCE(target->ready)) |
71506297 WL |
7323 | kvm_vcpu_yield_to(target); |
7324 | } | |
7325 | ||
8776e519 HB |
7326 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
7327 | { | |
7328 | unsigned long nr, a0, a1, a2, a3, ret; | |
6356ee0c | 7329 | int op_64_bit; |
8776e519 | 7330 | |
696ca779 RK |
7331 | if (kvm_hv_hypercall_enabled(vcpu->kvm)) |
7332 | return kvm_hv_hypercall(vcpu); | |
55cd8e5a | 7333 | |
de3cd117 SC |
7334 | nr = kvm_rax_read(vcpu); |
7335 | a0 = kvm_rbx_read(vcpu); | |
7336 | a1 = kvm_rcx_read(vcpu); | |
7337 | a2 = kvm_rdx_read(vcpu); | |
7338 | a3 = kvm_rsi_read(vcpu); | |
8776e519 | 7339 | |
229456fc | 7340 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 7341 | |
a449c7aa NA |
7342 | op_64_bit = is_64_bit_mode(vcpu); |
7343 | if (!op_64_bit) { | |
8776e519 HB |
7344 | nr &= 0xFFFFFFFF; |
7345 | a0 &= 0xFFFFFFFF; | |
7346 | a1 &= 0xFFFFFFFF; | |
7347 | a2 &= 0xFFFFFFFF; | |
7348 | a3 &= 0xFFFFFFFF; | |
7349 | } | |
7350 | ||
07708c4a JK |
7351 | if (kvm_x86_ops->get_cpl(vcpu) != 0) { |
7352 | ret = -KVM_EPERM; | |
696ca779 | 7353 | goto out; |
07708c4a JK |
7354 | } |
7355 | ||
8776e519 | 7356 | switch (nr) { |
b93463aa AK |
7357 | case KVM_HC_VAPIC_POLL_IRQ: |
7358 | ret = 0; | |
7359 | break; | |
6aef266c SV |
7360 | case KVM_HC_KICK_CPU: |
7361 | kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); | |
266e85a5 | 7362 | kvm_sched_yield(vcpu->kvm, a1); |
6aef266c SV |
7363 | ret = 0; |
7364 | break; | |
8ef81a9a | 7365 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
7366 | case KVM_HC_CLOCK_PAIRING: |
7367 | ret = kvm_pv_clock_pairing(vcpu, a0, a1); | |
7368 | break; | |
1ed199a4 | 7369 | #endif |
4180bf1b WL |
7370 | case KVM_HC_SEND_IPI: |
7371 | ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); | |
7372 | break; | |
71506297 WL |
7373 | case KVM_HC_SCHED_YIELD: |
7374 | kvm_sched_yield(vcpu->kvm, a0); | |
7375 | ret = 0; | |
7376 | break; | |
8776e519 HB |
7377 | default: |
7378 | ret = -KVM_ENOSYS; | |
7379 | break; | |
7380 | } | |
696ca779 | 7381 | out: |
a449c7aa NA |
7382 | if (!op_64_bit) |
7383 | ret = (u32)ret; | |
de3cd117 | 7384 | kvm_rax_write(vcpu, ret); |
6356ee0c | 7385 | |
f11c3a8d | 7386 | ++vcpu->stat.hypercalls; |
6356ee0c | 7387 | return kvm_skip_emulated_instruction(vcpu); |
8776e519 HB |
7388 | } |
7389 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
7390 | ||
b6785def | 7391 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) |
8776e519 | 7392 | { |
d6aa1000 | 7393 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
8776e519 | 7394 | char instruction[3]; |
5fdbf976 | 7395 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 7396 | |
8776e519 | 7397 | kvm_x86_ops->patch_hypercall(vcpu, instruction); |
8776e519 | 7398 | |
ce2e852e DV |
7399 | return emulator_write_emulated(ctxt, rip, instruction, 3, |
7400 | &ctxt->exception); | |
8776e519 HB |
7401 | } |
7402 | ||
851ba692 | 7403 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 7404 | { |
782d422b MG |
7405 | return vcpu->run->request_interrupt_window && |
7406 | likely(!pic_in_kernel(vcpu->kvm)); | |
b6c7a5dc HB |
7407 | } |
7408 | ||
851ba692 | 7409 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 7410 | { |
851ba692 AK |
7411 | struct kvm_run *kvm_run = vcpu->run; |
7412 | ||
91586a3b | 7413 | kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; |
f077825a | 7414 | kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0; |
2d3ad1f4 | 7415 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 7416 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
127a457a MG |
7417 | kvm_run->ready_for_interrupt_injection = |
7418 | pic_in_kernel(vcpu->kvm) || | |
782d422b | 7419 | kvm_vcpu_ready_for_interrupt_injection(vcpu); |
b6c7a5dc HB |
7420 | } |
7421 | ||
95ba8273 GN |
7422 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
7423 | { | |
7424 | int max_irr, tpr; | |
7425 | ||
7426 | if (!kvm_x86_ops->update_cr8_intercept) | |
7427 | return; | |
7428 | ||
bce87cce | 7429 | if (!lapic_in_kernel(vcpu)) |
88c808fd AK |
7430 | return; |
7431 | ||
d62caabb AS |
7432 | if (vcpu->arch.apicv_active) |
7433 | return; | |
7434 | ||
8db3baa2 GN |
7435 | if (!vcpu->arch.apic->vapic_addr) |
7436 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
7437 | else | |
7438 | max_irr = -1; | |
95ba8273 GN |
7439 | |
7440 | if (max_irr != -1) | |
7441 | max_irr >>= 4; | |
7442 | ||
7443 | tpr = kvm_lapic_get_cr8(vcpu); | |
7444 | ||
7445 | kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); | |
7446 | } | |
7447 | ||
b6b8a145 | 7448 | static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) |
95ba8273 | 7449 | { |
b6b8a145 JK |
7450 | int r; |
7451 | ||
95ba8273 | 7452 | /* try to reinject previous events if any */ |
664f8e26 | 7453 | |
1a680e35 LA |
7454 | if (vcpu->arch.exception.injected) |
7455 | kvm_x86_ops->queue_exception(vcpu); | |
664f8e26 | 7456 | /* |
a042c26f LA |
7457 | * Do not inject an NMI or interrupt if there is a pending |
7458 | * exception. Exceptions and interrupts are recognized at | |
7459 | * instruction boundaries, i.e. the start of an instruction. | |
7460 | * Trap-like exceptions, e.g. #DB, have higher priority than | |
7461 | * NMIs and interrupts, i.e. traps are recognized before an | |
7462 | * NMI/interrupt that's pending on the same instruction. | |
7463 | * Fault-like exceptions, e.g. #GP and #PF, are the lowest | |
7464 | * priority, but are only generated (pended) during instruction | |
7465 | * execution, i.e. a pending fault-like exception means the | |
7466 | * fault occurred on the *previous* instruction and must be | |
7467 | * serviced prior to recognizing any new events in order to | |
7468 | * fully complete the previous instruction. | |
664f8e26 | 7469 | */ |
1a680e35 LA |
7470 | else if (!vcpu->arch.exception.pending) { |
7471 | if (vcpu->arch.nmi_injected) | |
664f8e26 | 7472 | kvm_x86_ops->set_nmi(vcpu); |
1a680e35 | 7473 | else if (vcpu->arch.interrupt.injected) |
664f8e26 | 7474 | kvm_x86_ops->set_irq(vcpu); |
664f8e26 WL |
7475 | } |
7476 | ||
1a680e35 LA |
7477 | /* |
7478 | * Call check_nested_events() even if we reinjected a previous event | |
7479 | * in order for caller to determine if it should require immediate-exit | |
7480 | * from L2 to L1 due to pending L1 events which require exit | |
7481 | * from L2 to L1. | |
7482 | */ | |
664f8e26 WL |
7483 | if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { |
7484 | r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); | |
7485 | if (r != 0) | |
7486 | return r; | |
7487 | } | |
7488 | ||
7489 | /* try to inject new event if pending */ | |
b59bb7bd | 7490 | if (vcpu->arch.exception.pending) { |
5c1c85d0 AK |
7491 | trace_kvm_inj_exception(vcpu->arch.exception.nr, |
7492 | vcpu->arch.exception.has_error_code, | |
7493 | vcpu->arch.exception.error_code); | |
d6e8c854 | 7494 | |
1a680e35 | 7495 | WARN_ON_ONCE(vcpu->arch.exception.injected); |
664f8e26 WL |
7496 | vcpu->arch.exception.pending = false; |
7497 | vcpu->arch.exception.injected = true; | |
7498 | ||
d6e8c854 NA |
7499 | if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) |
7500 | __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | | |
7501 | X86_EFLAGS_RF); | |
7502 | ||
f10c729f JM |
7503 | if (vcpu->arch.exception.nr == DB_VECTOR) { |
7504 | /* | |
7505 | * This code assumes that nSVM doesn't use | |
7506 | * check_nested_events(). If it does, the | |
7507 | * DR6/DR7 changes should happen before L1 | |
7508 | * gets a #VMEXIT for an intercepted #DB in | |
7509 | * L2. (Under VMX, on the other hand, the | |
7510 | * DR6/DR7 changes should not happen in the | |
7511 | * event of a VM-exit to L1 for an intercepted | |
7512 | * #DB in L2.) | |
7513 | */ | |
7514 | kvm_deliver_exception_payload(vcpu); | |
7515 | if (vcpu->arch.dr7 & DR7_GD) { | |
7516 | vcpu->arch.dr7 &= ~DR7_GD; | |
7517 | kvm_update_dr7(vcpu); | |
7518 | } | |
6bdf0662 NA |
7519 | } |
7520 | ||
cfcd20e5 | 7521 | kvm_x86_ops->queue_exception(vcpu); |
1a680e35 LA |
7522 | } |
7523 | ||
7524 | /* Don't consider new event if we re-injected an event */ | |
7525 | if (kvm_event_needs_reinjection(vcpu)) | |
7526 | return 0; | |
7527 | ||
7528 | if (vcpu->arch.smi_pending && !is_smm(vcpu) && | |
7529 | kvm_x86_ops->smi_allowed(vcpu)) { | |
c43203ca | 7530 | vcpu->arch.smi_pending = false; |
52797bf9 | 7531 | ++vcpu->arch.smi_count; |
ee2cd4b7 | 7532 | enter_smm(vcpu); |
c43203ca | 7533 | } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) { |
321c5658 YS |
7534 | --vcpu->arch.nmi_pending; |
7535 | vcpu->arch.nmi_injected = true; | |
7536 | kvm_x86_ops->set_nmi(vcpu); | |
c7c9c56c | 7537 | } else if (kvm_cpu_has_injectable_intr(vcpu)) { |
9242b5b6 BD |
7538 | /* |
7539 | * Because interrupts can be injected asynchronously, we are | |
7540 | * calling check_nested_events again here to avoid a race condition. | |
7541 | * See https://lkml.org/lkml/2014/7/2/60 for discussion about this | |
7542 | * proposal and current concerns. Perhaps we should be setting | |
7543 | * KVM_REQ_EVENT only on certain events and not unconditionally? | |
7544 | */ | |
7545 | if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { | |
7546 | r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); | |
7547 | if (r != 0) | |
7548 | return r; | |
7549 | } | |
95ba8273 | 7550 | if (kvm_x86_ops->interrupt_allowed(vcpu)) { |
66fd3f7f GN |
7551 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), |
7552 | false); | |
7553 | kvm_x86_ops->set_irq(vcpu); | |
95ba8273 GN |
7554 | } |
7555 | } | |
ee2cd4b7 | 7556 | |
b6b8a145 | 7557 | return 0; |
95ba8273 GN |
7558 | } |
7559 | ||
7460fb4a AK |
7560 | static void process_nmi(struct kvm_vcpu *vcpu) |
7561 | { | |
7562 | unsigned limit = 2; | |
7563 | ||
7564 | /* | |
7565 | * x86 is limited to one NMI running, and one NMI pending after it. | |
7566 | * If an NMI is already in progress, limit further NMIs to just one. | |
7567 | * Otherwise, allow two (and we'll inject the first one immediately). | |
7568 | */ | |
7569 | if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) | |
7570 | limit = 1; | |
7571 | ||
7572 | vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); | |
7573 | vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); | |
7574 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7575 | } | |
7576 | ||
ee2cd4b7 | 7577 | static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) |
660a5d51 PB |
7578 | { |
7579 | u32 flags = 0; | |
7580 | flags |= seg->g << 23; | |
7581 | flags |= seg->db << 22; | |
7582 | flags |= seg->l << 21; | |
7583 | flags |= seg->avl << 20; | |
7584 | flags |= seg->present << 15; | |
7585 | flags |= seg->dpl << 13; | |
7586 | flags |= seg->s << 12; | |
7587 | flags |= seg->type << 8; | |
7588 | return flags; | |
7589 | } | |
7590 | ||
ee2cd4b7 | 7591 | static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) |
660a5d51 PB |
7592 | { |
7593 | struct kvm_segment seg; | |
7594 | int offset; | |
7595 | ||
7596 | kvm_get_segment(vcpu, &seg, n); | |
7597 | put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); | |
7598 | ||
7599 | if (n < 3) | |
7600 | offset = 0x7f84 + n * 12; | |
7601 | else | |
7602 | offset = 0x7f2c + (n - 3) * 12; | |
7603 | ||
7604 | put_smstate(u32, buf, offset + 8, seg.base); | |
7605 | put_smstate(u32, buf, offset + 4, seg.limit); | |
ee2cd4b7 | 7606 | put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
7607 | } |
7608 | ||
efbb288a | 7609 | #ifdef CONFIG_X86_64 |
ee2cd4b7 | 7610 | static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) |
660a5d51 PB |
7611 | { |
7612 | struct kvm_segment seg; | |
7613 | int offset; | |
7614 | u16 flags; | |
7615 | ||
7616 | kvm_get_segment(vcpu, &seg, n); | |
7617 | offset = 0x7e00 + n * 16; | |
7618 | ||
ee2cd4b7 | 7619 | flags = enter_smm_get_segment_flags(&seg) >> 8; |
660a5d51 PB |
7620 | put_smstate(u16, buf, offset, seg.selector); |
7621 | put_smstate(u16, buf, offset + 2, flags); | |
7622 | put_smstate(u32, buf, offset + 4, seg.limit); | |
7623 | put_smstate(u64, buf, offset + 8, seg.base); | |
7624 | } | |
efbb288a | 7625 | #endif |
660a5d51 | 7626 | |
ee2cd4b7 | 7627 | static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) |
660a5d51 PB |
7628 | { |
7629 | struct desc_ptr dt; | |
7630 | struct kvm_segment seg; | |
7631 | unsigned long val; | |
7632 | int i; | |
7633 | ||
7634 | put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); | |
7635 | put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); | |
7636 | put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); | |
7637 | put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); | |
7638 | ||
7639 | for (i = 0; i < 8; i++) | |
7640 | put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); | |
7641 | ||
7642 | kvm_get_dr(vcpu, 6, &val); | |
7643 | put_smstate(u32, buf, 0x7fcc, (u32)val); | |
7644 | kvm_get_dr(vcpu, 7, &val); | |
7645 | put_smstate(u32, buf, 0x7fc8, (u32)val); | |
7646 | ||
7647 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
7648 | put_smstate(u32, buf, 0x7fc4, seg.selector); | |
7649 | put_smstate(u32, buf, 0x7f64, seg.base); | |
7650 | put_smstate(u32, buf, 0x7f60, seg.limit); | |
ee2cd4b7 | 7651 | put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
7652 | |
7653 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
7654 | put_smstate(u32, buf, 0x7fc0, seg.selector); | |
7655 | put_smstate(u32, buf, 0x7f80, seg.base); | |
7656 | put_smstate(u32, buf, 0x7f7c, seg.limit); | |
ee2cd4b7 | 7657 | put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
7658 | |
7659 | kvm_x86_ops->get_gdt(vcpu, &dt); | |
7660 | put_smstate(u32, buf, 0x7f74, dt.address); | |
7661 | put_smstate(u32, buf, 0x7f70, dt.size); | |
7662 | ||
7663 | kvm_x86_ops->get_idt(vcpu, &dt); | |
7664 | put_smstate(u32, buf, 0x7f58, dt.address); | |
7665 | put_smstate(u32, buf, 0x7f54, dt.size); | |
7666 | ||
7667 | for (i = 0; i < 6; i++) | |
ee2cd4b7 | 7668 | enter_smm_save_seg_32(vcpu, buf, i); |
660a5d51 PB |
7669 | |
7670 | put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); | |
7671 | ||
7672 | /* revision id */ | |
7673 | put_smstate(u32, buf, 0x7efc, 0x00020000); | |
7674 | put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); | |
7675 | } | |
7676 | ||
b68f3cc7 | 7677 | #ifdef CONFIG_X86_64 |
ee2cd4b7 | 7678 | static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) |
660a5d51 | 7679 | { |
660a5d51 PB |
7680 | struct desc_ptr dt; |
7681 | struct kvm_segment seg; | |
7682 | unsigned long val; | |
7683 | int i; | |
7684 | ||
7685 | for (i = 0; i < 16; i++) | |
7686 | put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); | |
7687 | ||
7688 | put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); | |
7689 | put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); | |
7690 | ||
7691 | kvm_get_dr(vcpu, 6, &val); | |
7692 | put_smstate(u64, buf, 0x7f68, val); | |
7693 | kvm_get_dr(vcpu, 7, &val); | |
7694 | put_smstate(u64, buf, 0x7f60, val); | |
7695 | ||
7696 | put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); | |
7697 | put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); | |
7698 | put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); | |
7699 | ||
7700 | put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); | |
7701 | ||
7702 | /* revision id */ | |
7703 | put_smstate(u32, buf, 0x7efc, 0x00020064); | |
7704 | ||
7705 | put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); | |
7706 | ||
7707 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
7708 | put_smstate(u16, buf, 0x7e90, seg.selector); | |
ee2cd4b7 | 7709 | put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); |
660a5d51 PB |
7710 | put_smstate(u32, buf, 0x7e94, seg.limit); |
7711 | put_smstate(u64, buf, 0x7e98, seg.base); | |
7712 | ||
7713 | kvm_x86_ops->get_idt(vcpu, &dt); | |
7714 | put_smstate(u32, buf, 0x7e84, dt.size); | |
7715 | put_smstate(u64, buf, 0x7e88, dt.address); | |
7716 | ||
7717 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
7718 | put_smstate(u16, buf, 0x7e70, seg.selector); | |
ee2cd4b7 | 7719 | put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); |
660a5d51 PB |
7720 | put_smstate(u32, buf, 0x7e74, seg.limit); |
7721 | put_smstate(u64, buf, 0x7e78, seg.base); | |
7722 | ||
7723 | kvm_x86_ops->get_gdt(vcpu, &dt); | |
7724 | put_smstate(u32, buf, 0x7e64, dt.size); | |
7725 | put_smstate(u64, buf, 0x7e68, dt.address); | |
7726 | ||
7727 | for (i = 0; i < 6; i++) | |
ee2cd4b7 | 7728 | enter_smm_save_seg_64(vcpu, buf, i); |
660a5d51 | 7729 | } |
b68f3cc7 | 7730 | #endif |
660a5d51 | 7731 | |
ee2cd4b7 | 7732 | static void enter_smm(struct kvm_vcpu *vcpu) |
64d60670 | 7733 | { |
660a5d51 | 7734 | struct kvm_segment cs, ds; |
18c3626e | 7735 | struct desc_ptr dt; |
660a5d51 PB |
7736 | char buf[512]; |
7737 | u32 cr0; | |
7738 | ||
660a5d51 | 7739 | trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); |
660a5d51 | 7740 | memset(buf, 0, 512); |
b68f3cc7 | 7741 | #ifdef CONFIG_X86_64 |
d6321d49 | 7742 | if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) |
ee2cd4b7 | 7743 | enter_smm_save_state_64(vcpu, buf); |
660a5d51 | 7744 | else |
b68f3cc7 | 7745 | #endif |
ee2cd4b7 | 7746 | enter_smm_save_state_32(vcpu, buf); |
660a5d51 | 7747 | |
0234bf88 LP |
7748 | /* |
7749 | * Give pre_enter_smm() a chance to make ISA-specific changes to the | |
7750 | * vCPU state (e.g. leave guest mode) after we've saved the state into | |
7751 | * the SMM state-save area. | |
7752 | */ | |
7753 | kvm_x86_ops->pre_enter_smm(vcpu, buf); | |
7754 | ||
7755 | vcpu->arch.hflags |= HF_SMM_MASK; | |
54bf36aa | 7756 | kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); |
660a5d51 PB |
7757 | |
7758 | if (kvm_x86_ops->get_nmi_mask(vcpu)) | |
7759 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; | |
7760 | else | |
7761 | kvm_x86_ops->set_nmi_mask(vcpu, true); | |
7762 | ||
7763 | kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); | |
7764 | kvm_rip_write(vcpu, 0x8000); | |
7765 | ||
7766 | cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); | |
7767 | kvm_x86_ops->set_cr0(vcpu, cr0); | |
7768 | vcpu->arch.cr0 = cr0; | |
7769 | ||
7770 | kvm_x86_ops->set_cr4(vcpu, 0); | |
7771 | ||
18c3626e PB |
7772 | /* Undocumented: IDT limit is set to zero on entry to SMM. */ |
7773 | dt.address = dt.size = 0; | |
7774 | kvm_x86_ops->set_idt(vcpu, &dt); | |
7775 | ||
660a5d51 PB |
7776 | __kvm_set_dr(vcpu, 7, DR7_FIXED_1); |
7777 | ||
7778 | cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; | |
7779 | cs.base = vcpu->arch.smbase; | |
7780 | ||
7781 | ds.selector = 0; | |
7782 | ds.base = 0; | |
7783 | ||
7784 | cs.limit = ds.limit = 0xffffffff; | |
7785 | cs.type = ds.type = 0x3; | |
7786 | cs.dpl = ds.dpl = 0; | |
7787 | cs.db = ds.db = 0; | |
7788 | cs.s = ds.s = 1; | |
7789 | cs.l = ds.l = 0; | |
7790 | cs.g = ds.g = 1; | |
7791 | cs.avl = ds.avl = 0; | |
7792 | cs.present = ds.present = 1; | |
7793 | cs.unusable = ds.unusable = 0; | |
7794 | cs.padding = ds.padding = 0; | |
7795 | ||
7796 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
7797 | kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); | |
7798 | kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); | |
7799 | kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); | |
7800 | kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); | |
7801 | kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); | |
7802 | ||
b68f3cc7 | 7803 | #ifdef CONFIG_X86_64 |
d6321d49 | 7804 | if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) |
660a5d51 | 7805 | kvm_x86_ops->set_efer(vcpu, 0); |
b68f3cc7 | 7806 | #endif |
660a5d51 PB |
7807 | |
7808 | kvm_update_cpuid(vcpu); | |
7809 | kvm_mmu_reset_context(vcpu); | |
64d60670 PB |
7810 | } |
7811 | ||
ee2cd4b7 | 7812 | static void process_smi(struct kvm_vcpu *vcpu) |
c43203ca PB |
7813 | { |
7814 | vcpu->arch.smi_pending = true; | |
7815 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7816 | } | |
7817 | ||
2860c4b1 PB |
7818 | void kvm_make_scan_ioapic_request(struct kvm *kvm) |
7819 | { | |
7820 | kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); | |
7821 | } | |
7822 | ||
3d81bc7e | 7823 | static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) |
c7c9c56c | 7824 | { |
dcbd3e49 | 7825 | if (!kvm_apic_present(vcpu)) |
3d81bc7e | 7826 | return; |
c7c9c56c | 7827 | |
6308630b | 7828 | bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); |
c7c9c56c | 7829 | |
b053b2ae | 7830 | if (irqchip_split(vcpu->kvm)) |
6308630b | 7831 | kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); |
db2bdcbb | 7832 | else { |
fa59cc00 | 7833 | if (vcpu->arch.apicv_active) |
d62caabb | 7834 | kvm_x86_ops->sync_pir_to_irr(vcpu); |
e97f852f WL |
7835 | if (ioapic_in_kernel(vcpu->kvm)) |
7836 | kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); | |
db2bdcbb | 7837 | } |
e40ff1d6 LA |
7838 | |
7839 | if (is_guest_mode(vcpu)) | |
7840 | vcpu->arch.load_eoi_exitmap_pending = true; | |
7841 | else | |
7842 | kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); | |
7843 | } | |
7844 | ||
7845 | static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) | |
7846 | { | |
7847 | u64 eoi_exit_bitmap[4]; | |
7848 | ||
7849 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) | |
7850 | return; | |
7851 | ||
5c919412 AS |
7852 | bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors, |
7853 | vcpu_to_synic(vcpu)->vec_bitmap, 256); | |
7854 | kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); | |
c7c9c56c YZ |
7855 | } |
7856 | ||
93065ac7 MH |
7857 | int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, |
7858 | unsigned long start, unsigned long end, | |
7859 | bool blockable) | |
b1394e74 RK |
7860 | { |
7861 | unsigned long apic_address; | |
7862 | ||
7863 | /* | |
7864 | * The physical address of apic access page is stored in the VMCS. | |
7865 | * Update it when it becomes invalid. | |
7866 | */ | |
7867 | apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); | |
7868 | if (start <= apic_address && apic_address < end) | |
7869 | kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); | |
93065ac7 MH |
7870 | |
7871 | return 0; | |
b1394e74 RK |
7872 | } |
7873 | ||
4256f43f TC |
7874 | void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) |
7875 | { | |
c24ae0dc TC |
7876 | struct page *page = NULL; |
7877 | ||
35754c98 | 7878 | if (!lapic_in_kernel(vcpu)) |
f439ed27 PB |
7879 | return; |
7880 | ||
4256f43f TC |
7881 | if (!kvm_x86_ops->set_apic_access_page_addr) |
7882 | return; | |
7883 | ||
c24ae0dc | 7884 | page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); |
e8fd5e9e AA |
7885 | if (is_error_page(page)) |
7886 | return; | |
c24ae0dc TC |
7887 | kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page)); |
7888 | ||
7889 | /* | |
7890 | * Do not pin apic access page in memory, the MMU notifier | |
7891 | * will call us again if it is migrated or swapped out. | |
7892 | */ | |
7893 | put_page(page); | |
4256f43f TC |
7894 | } |
7895 | EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page); | |
7896 | ||
d264ee0c SC |
7897 | void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) |
7898 | { | |
7899 | smp_send_reschedule(vcpu->cpu); | |
7900 | } | |
7901 | EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); | |
7902 | ||
9357d939 | 7903 | /* |
362c698f | 7904 | * Returns 1 to let vcpu_run() continue the guest execution loop without |
9357d939 TY |
7905 | * exiting to the userspace. Otherwise, the value will be returned to the |
7906 | * userspace. | |
7907 | */ | |
851ba692 | 7908 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
7909 | { |
7910 | int r; | |
62a193ed MG |
7911 | bool req_int_win = |
7912 | dm_request_for_irq_injection(vcpu) && | |
7913 | kvm_cpu_accept_dm_intr(vcpu); | |
7914 | ||
730dca42 | 7915 | bool req_immediate_exit = false; |
b6c7a5dc | 7916 | |
2fa6e1e1 | 7917 | if (kvm_request_pending(vcpu)) { |
7f7f1ba3 PB |
7918 | if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu)) |
7919 | kvm_x86_ops->get_vmcs12_pages(vcpu); | |
a8eeb04a | 7920 | if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) |
2e53d63a | 7921 | kvm_mmu_unload(vcpu); |
a8eeb04a | 7922 | if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) |
2f599714 | 7923 | __kvm_migrate_timers(vcpu); |
d828199e MT |
7924 | if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) |
7925 | kvm_gen_update_masterclock(vcpu->kvm); | |
0061d53d MT |
7926 | if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) |
7927 | kvm_gen_kvmclock_update(vcpu); | |
34c238a1 ZA |
7928 | if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { |
7929 | r = kvm_guest_time_update(vcpu); | |
8cfdc000 ZA |
7930 | if (unlikely(r)) |
7931 | goto out; | |
7932 | } | |
a8eeb04a | 7933 | if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) |
4731d4c7 | 7934 | kvm_mmu_sync_roots(vcpu); |
6e42782f JS |
7935 | if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu)) |
7936 | kvm_mmu_load_cr3(vcpu); | |
a8eeb04a | 7937 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) |
c2ba05cc | 7938 | kvm_vcpu_flush_tlb(vcpu, true); |
a8eeb04a | 7939 | if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { |
851ba692 | 7940 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
7941 | r = 0; |
7942 | goto out; | |
7943 | } | |
a8eeb04a | 7944 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
851ba692 | 7945 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
bbeac283 | 7946 | vcpu->mmio_needed = 0; |
71c4dfaf JR |
7947 | r = 0; |
7948 | goto out; | |
7949 | } | |
af585b92 GN |
7950 | if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { |
7951 | /* Page is swapped out. Do synthetic halt */ | |
7952 | vcpu->arch.apf.halted = true; | |
7953 | r = 1; | |
7954 | goto out; | |
7955 | } | |
c9aaa895 GC |
7956 | if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) |
7957 | record_steal_time(vcpu); | |
64d60670 PB |
7958 | if (kvm_check_request(KVM_REQ_SMI, vcpu)) |
7959 | process_smi(vcpu); | |
7460fb4a AK |
7960 | if (kvm_check_request(KVM_REQ_NMI, vcpu)) |
7961 | process_nmi(vcpu); | |
f5132b01 | 7962 | if (kvm_check_request(KVM_REQ_PMU, vcpu)) |
c6702c9d | 7963 | kvm_pmu_handle_event(vcpu); |
f5132b01 | 7964 | if (kvm_check_request(KVM_REQ_PMI, vcpu)) |
c6702c9d | 7965 | kvm_pmu_deliver_pmi(vcpu); |
7543a635 SR |
7966 | if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { |
7967 | BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); | |
7968 | if (test_bit(vcpu->arch.pending_ioapic_eoi, | |
6308630b | 7969 | vcpu->arch.ioapic_handled_vectors)) { |
7543a635 SR |
7970 | vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; |
7971 | vcpu->run->eoi.vector = | |
7972 | vcpu->arch.pending_ioapic_eoi; | |
7973 | r = 0; | |
7974 | goto out; | |
7975 | } | |
7976 | } | |
3d81bc7e YZ |
7977 | if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) |
7978 | vcpu_scan_ioapic(vcpu); | |
e40ff1d6 LA |
7979 | if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) |
7980 | vcpu_load_eoi_exitmap(vcpu); | |
4256f43f TC |
7981 | if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) |
7982 | kvm_vcpu_reload_apic_access_page(vcpu); | |
2ce79189 AS |
7983 | if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { |
7984 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
7985 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; | |
7986 | r = 0; | |
7987 | goto out; | |
7988 | } | |
e516cebb AS |
7989 | if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { |
7990 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
7991 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; | |
7992 | r = 0; | |
7993 | goto out; | |
7994 | } | |
db397571 AS |
7995 | if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { |
7996 | vcpu->run->exit_reason = KVM_EXIT_HYPERV; | |
7997 | vcpu->run->hyperv = vcpu->arch.hyperv.exit; | |
7998 | r = 0; | |
7999 | goto out; | |
8000 | } | |
f3b138c5 AS |
8001 | |
8002 | /* | |
8003 | * KVM_REQ_HV_STIMER has to be processed after | |
8004 | * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers | |
8005 | * depend on the guest clock being up-to-date | |
8006 | */ | |
1f4b34f8 AS |
8007 | if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) |
8008 | kvm_hv_process_stimers(vcpu); | |
2f52d58c | 8009 | } |
b93463aa | 8010 | |
b463a6f7 | 8011 | if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { |
0f1e261e | 8012 | ++vcpu->stat.req_event; |
66450a21 JK |
8013 | kvm_apic_accept_events(vcpu); |
8014 | if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { | |
8015 | r = 1; | |
8016 | goto out; | |
8017 | } | |
8018 | ||
b6b8a145 JK |
8019 | if (inject_pending_event(vcpu, req_int_win) != 0) |
8020 | req_immediate_exit = true; | |
321c5658 | 8021 | else { |
cc3d967f | 8022 | /* Enable SMI/NMI/IRQ window open exits if needed. |
c43203ca | 8023 | * |
cc3d967f LP |
8024 | * SMIs have three cases: |
8025 | * 1) They can be nested, and then there is nothing to | |
8026 | * do here because RSM will cause a vmexit anyway. | |
8027 | * 2) There is an ISA-specific reason why SMI cannot be | |
8028 | * injected, and the moment when this changes can be | |
8029 | * intercepted. | |
8030 | * 3) Or the SMI can be pending because | |
8031 | * inject_pending_event has completed the injection | |
8032 | * of an IRQ or NMI from the previous vmexit, and | |
8033 | * then we request an immediate exit to inject the | |
8034 | * SMI. | |
c43203ca PB |
8035 | */ |
8036 | if (vcpu->arch.smi_pending && !is_smm(vcpu)) | |
cc3d967f LP |
8037 | if (!kvm_x86_ops->enable_smi_window(vcpu)) |
8038 | req_immediate_exit = true; | |
321c5658 YS |
8039 | if (vcpu->arch.nmi_pending) |
8040 | kvm_x86_ops->enable_nmi_window(vcpu); | |
8041 | if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) | |
8042 | kvm_x86_ops->enable_irq_window(vcpu); | |
664f8e26 | 8043 | WARN_ON(vcpu->arch.exception.pending); |
321c5658 | 8044 | } |
b463a6f7 AK |
8045 | |
8046 | if (kvm_lapic_enabled(vcpu)) { | |
8047 | update_cr8_intercept(vcpu); | |
8048 | kvm_lapic_sync_to_vapic(vcpu); | |
8049 | } | |
8050 | } | |
8051 | ||
d8368af8 AK |
8052 | r = kvm_mmu_reload(vcpu); |
8053 | if (unlikely(r)) { | |
d905c069 | 8054 | goto cancel_injection; |
d8368af8 AK |
8055 | } |
8056 | ||
b6c7a5dc HB |
8057 | preempt_disable(); |
8058 | ||
8059 | kvm_x86_ops->prepare_guest_switch(vcpu); | |
b95234c8 PB |
8060 | |
8061 | /* | |
8062 | * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt | |
8063 | * IPI are then delayed after guest entry, which ensures that they | |
8064 | * result in virtual interrupt delivery. | |
8065 | */ | |
8066 | local_irq_disable(); | |
6b7e2d09 XG |
8067 | vcpu->mode = IN_GUEST_MODE; |
8068 | ||
01b71917 MT |
8069 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
8070 | ||
0f127d12 | 8071 | /* |
b95234c8 | 8072 | * 1) We should set ->mode before checking ->requests. Please see |
cde9af6e | 8073 | * the comment in kvm_vcpu_exiting_guest_mode(). |
b95234c8 | 8074 | * |
81b01667 | 8075 | * 2) For APICv, we should set ->mode before checking PID.ON. This |
b95234c8 PB |
8076 | * pairs with the memory barrier implicit in pi_test_and_set_on |
8077 | * (see vmx_deliver_posted_interrupt). | |
8078 | * | |
8079 | * 3) This also orders the write to mode from any reads to the page | |
8080 | * tables done while the VCPU is running. Please see the comment | |
8081 | * in kvm_flush_remote_tlbs. | |
6b7e2d09 | 8082 | */ |
01b71917 | 8083 | smp_mb__after_srcu_read_unlock(); |
b6c7a5dc | 8084 | |
b95234c8 PB |
8085 | /* |
8086 | * This handles the case where a posted interrupt was | |
8087 | * notified with kvm_vcpu_kick. | |
8088 | */ | |
fa59cc00 LA |
8089 | if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active) |
8090 | kvm_x86_ops->sync_pir_to_irr(vcpu); | |
32f88400 | 8091 | |
2fa6e1e1 | 8092 | if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) |
d94e1dc9 | 8093 | || need_resched() || signal_pending(current)) { |
6b7e2d09 | 8094 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 8095 | smp_wmb(); |
6c142801 AK |
8096 | local_irq_enable(); |
8097 | preempt_enable(); | |
01b71917 | 8098 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
6c142801 | 8099 | r = 1; |
d905c069 | 8100 | goto cancel_injection; |
6c142801 AK |
8101 | } |
8102 | ||
c43203ca PB |
8103 | if (req_immediate_exit) { |
8104 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
d264ee0c | 8105 | kvm_x86_ops->request_immediate_exit(vcpu); |
c43203ca | 8106 | } |
d6185f20 | 8107 | |
8b89fe1f | 8108 | trace_kvm_entry(vcpu->vcpu_id); |
6edaa530 | 8109 | guest_enter_irqoff(); |
b6c7a5dc | 8110 | |
e7517324 WL |
8111 | /* The preempt notifier should have taken care of the FPU already. */ |
8112 | WARN_ON_ONCE(test_thread_flag(TIF_NEED_FPU_LOAD)); | |
5f409e20 | 8113 | |
42dbaa5a | 8114 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
8115 | set_debugreg(0, 7); |
8116 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
8117 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
8118 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
8119 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
c77fb5fe | 8120 | set_debugreg(vcpu->arch.dr6, 6); |
ae561ede | 8121 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; |
42dbaa5a | 8122 | } |
b6c7a5dc | 8123 | |
851ba692 | 8124 | kvm_x86_ops->run(vcpu); |
b6c7a5dc | 8125 | |
c77fb5fe PB |
8126 | /* |
8127 | * Do this here before restoring debug registers on the host. And | |
8128 | * since we do this before handling the vmexit, a DR access vmexit | |
8129 | * can (a) read the correct value of the debug registers, (b) set | |
8130 | * KVM_DEBUGREG_WONT_EXIT again. | |
8131 | */ | |
8132 | if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { | |
c77fb5fe PB |
8133 | WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); |
8134 | kvm_x86_ops->sync_dirty_debug_regs(vcpu); | |
70e4da7a PB |
8135 | kvm_update_dr0123(vcpu); |
8136 | kvm_update_dr6(vcpu); | |
8137 | kvm_update_dr7(vcpu); | |
8138 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; | |
c77fb5fe PB |
8139 | } |
8140 | ||
24f1e32c FW |
8141 | /* |
8142 | * If the guest has used debug registers, at least dr7 | |
8143 | * will be disabled while returning to the host. | |
8144 | * If we don't have active breakpoints in the host, we don't | |
8145 | * care about the messed up debug address registers. But if | |
8146 | * we have some of them active, restore the old state. | |
8147 | */ | |
59d8eb53 | 8148 | if (hw_breakpoint_active()) |
24f1e32c | 8149 | hw_breakpoint_restore(); |
42dbaa5a | 8150 | |
4ba76538 | 8151 | vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); |
1d5f066e | 8152 | |
6b7e2d09 | 8153 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 8154 | smp_wmb(); |
a547c6db | 8155 | |
95b5a48c | 8156 | kvm_x86_ops->handle_exit_irqoff(vcpu); |
b6c7a5dc | 8157 | |
d7a08882 SC |
8158 | /* |
8159 | * Consume any pending interrupts, including the possible source of | |
8160 | * VM-Exit on SVM and any ticks that occur between VM-Exit and now. | |
8161 | * An instruction is required after local_irq_enable() to fully unblock | |
8162 | * interrupts on processors that implement an interrupt shadow, the | |
8163 | * stat.exits increment will do nicely. | |
8164 | */ | |
8165 | kvm_before_interrupt(vcpu); | |
8166 | local_irq_enable(); | |
b6c7a5dc | 8167 | ++vcpu->stat.exits; |
d7a08882 SC |
8168 | local_irq_disable(); |
8169 | kvm_after_interrupt(vcpu); | |
b6c7a5dc | 8170 | |
f2485b3e | 8171 | guest_exit_irqoff(); |
ec0671d5 WL |
8172 | if (lapic_in_kernel(vcpu)) { |
8173 | s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta; | |
8174 | if (delta != S64_MIN) { | |
8175 | trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta); | |
8176 | vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN; | |
8177 | } | |
8178 | } | |
b6c7a5dc | 8179 | |
f2485b3e | 8180 | local_irq_enable(); |
b6c7a5dc HB |
8181 | preempt_enable(); |
8182 | ||
f656ce01 | 8183 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
3200f405 | 8184 | |
b6c7a5dc HB |
8185 | /* |
8186 | * Profile KVM exit RIPs: | |
8187 | */ | |
8188 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
8189 | unsigned long rip = kvm_rip_read(vcpu); |
8190 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
8191 | } |
8192 | ||
cc578287 ZA |
8193 | if (unlikely(vcpu->arch.tsc_always_catchup)) |
8194 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
298101da | 8195 | |
5cfb1d5a MT |
8196 | if (vcpu->arch.apic_attention) |
8197 | kvm_lapic_sync_from_vapic(vcpu); | |
b93463aa | 8198 | |
618232e2 | 8199 | vcpu->arch.gpa_available = false; |
851ba692 | 8200 | r = kvm_x86_ops->handle_exit(vcpu); |
d905c069 MT |
8201 | return r; |
8202 | ||
8203 | cancel_injection: | |
8204 | kvm_x86_ops->cancel_injection(vcpu); | |
ae7a2a3f MT |
8205 | if (unlikely(vcpu->arch.apic_attention)) |
8206 | kvm_lapic_sync_from_vapic(vcpu); | |
d7690175 MT |
8207 | out: |
8208 | return r; | |
8209 | } | |
b6c7a5dc | 8210 | |
362c698f PB |
8211 | static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) |
8212 | { | |
bf9f6ac8 FW |
8213 | if (!kvm_arch_vcpu_runnable(vcpu) && |
8214 | (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) { | |
9c8fd1ba PB |
8215 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
8216 | kvm_vcpu_block(vcpu); | |
8217 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); | |
bf9f6ac8 FW |
8218 | |
8219 | if (kvm_x86_ops->post_block) | |
8220 | kvm_x86_ops->post_block(vcpu); | |
8221 | ||
9c8fd1ba PB |
8222 | if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) |
8223 | return 1; | |
8224 | } | |
362c698f PB |
8225 | |
8226 | kvm_apic_accept_events(vcpu); | |
8227 | switch(vcpu->arch.mp_state) { | |
8228 | case KVM_MP_STATE_HALTED: | |
8229 | vcpu->arch.pv.pv_unhalted = false; | |
8230 | vcpu->arch.mp_state = | |
8231 | KVM_MP_STATE_RUNNABLE; | |
b2869f28 | 8232 | /* fall through */ |
362c698f PB |
8233 | case KVM_MP_STATE_RUNNABLE: |
8234 | vcpu->arch.apf.halted = false; | |
8235 | break; | |
8236 | case KVM_MP_STATE_INIT_RECEIVED: | |
8237 | break; | |
8238 | default: | |
8239 | return -EINTR; | |
8240 | break; | |
8241 | } | |
8242 | return 1; | |
8243 | } | |
09cec754 | 8244 | |
5d9bc648 PB |
8245 | static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) |
8246 | { | |
0ad3bed6 PB |
8247 | if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) |
8248 | kvm_x86_ops->check_nested_events(vcpu, false); | |
8249 | ||
5d9bc648 PB |
8250 | return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
8251 | !vcpu->arch.apf.halted); | |
8252 | } | |
8253 | ||
362c698f | 8254 | static int vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
8255 | { |
8256 | int r; | |
f656ce01 | 8257 | struct kvm *kvm = vcpu->kvm; |
d7690175 | 8258 | |
f656ce01 | 8259 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
c595ceee | 8260 | vcpu->arch.l1tf_flush_l1d = true; |
d7690175 | 8261 | |
362c698f | 8262 | for (;;) { |
58f800d5 | 8263 | if (kvm_vcpu_running(vcpu)) { |
851ba692 | 8264 | r = vcpu_enter_guest(vcpu); |
bf9f6ac8 | 8265 | } else { |
362c698f | 8266 | r = vcpu_block(kvm, vcpu); |
bf9f6ac8 FW |
8267 | } |
8268 | ||
09cec754 GN |
8269 | if (r <= 0) |
8270 | break; | |
8271 | ||
72875d8a | 8272 | kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu); |
09cec754 GN |
8273 | if (kvm_cpu_has_pending_timer(vcpu)) |
8274 | kvm_inject_pending_timer_irqs(vcpu); | |
8275 | ||
782d422b MG |
8276 | if (dm_request_for_irq_injection(vcpu) && |
8277 | kvm_vcpu_ready_for_interrupt_injection(vcpu)) { | |
4ca7dd8c PB |
8278 | r = 0; |
8279 | vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; | |
09cec754 | 8280 | ++vcpu->stat.request_irq_exits; |
362c698f | 8281 | break; |
09cec754 | 8282 | } |
af585b92 GN |
8283 | |
8284 | kvm_check_async_pf_completion(vcpu); | |
8285 | ||
09cec754 GN |
8286 | if (signal_pending(current)) { |
8287 | r = -EINTR; | |
851ba692 | 8288 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 | 8289 | ++vcpu->stat.signal_exits; |
362c698f | 8290 | break; |
09cec754 GN |
8291 | } |
8292 | if (need_resched()) { | |
f656ce01 | 8293 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
c08ac06a | 8294 | cond_resched(); |
f656ce01 | 8295 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 8296 | } |
b6c7a5dc HB |
8297 | } |
8298 | ||
f656ce01 | 8299 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
b6c7a5dc HB |
8300 | |
8301 | return r; | |
8302 | } | |
8303 | ||
716d51ab GN |
8304 | static inline int complete_emulated_io(struct kvm_vcpu *vcpu) |
8305 | { | |
8306 | int r; | |
8307 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); | |
0ce97a2b | 8308 | r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); |
716d51ab GN |
8309 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
8310 | if (r != EMULATE_DONE) | |
8311 | return 0; | |
8312 | return 1; | |
8313 | } | |
8314 | ||
8315 | static int complete_emulated_pio(struct kvm_vcpu *vcpu) | |
8316 | { | |
8317 | BUG_ON(!vcpu->arch.pio.count); | |
8318 | ||
8319 | return complete_emulated_io(vcpu); | |
8320 | } | |
8321 | ||
f78146b0 AK |
8322 | /* |
8323 | * Implements the following, as a state machine: | |
8324 | * | |
8325 | * read: | |
8326 | * for each fragment | |
87da7e66 XG |
8327 | * for each mmio piece in the fragment |
8328 | * write gpa, len | |
8329 | * exit | |
8330 | * copy data | |
f78146b0 AK |
8331 | * execute insn |
8332 | * | |
8333 | * write: | |
8334 | * for each fragment | |
87da7e66 XG |
8335 | * for each mmio piece in the fragment |
8336 | * write gpa, len | |
8337 | * copy data | |
8338 | * exit | |
f78146b0 | 8339 | */ |
716d51ab | 8340 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu) |
5287f194 AK |
8341 | { |
8342 | struct kvm_run *run = vcpu->run; | |
f78146b0 | 8343 | struct kvm_mmio_fragment *frag; |
87da7e66 | 8344 | unsigned len; |
5287f194 | 8345 | |
716d51ab | 8346 | BUG_ON(!vcpu->mmio_needed); |
5287f194 | 8347 | |
716d51ab | 8348 | /* Complete previous fragment */ |
87da7e66 XG |
8349 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; |
8350 | len = min(8u, frag->len); | |
716d51ab | 8351 | if (!vcpu->mmio_is_write) |
87da7e66 XG |
8352 | memcpy(frag->data, run->mmio.data, len); |
8353 | ||
8354 | if (frag->len <= 8) { | |
8355 | /* Switch to the next fragment. */ | |
8356 | frag++; | |
8357 | vcpu->mmio_cur_fragment++; | |
8358 | } else { | |
8359 | /* Go forward to the next mmio piece. */ | |
8360 | frag->data += len; | |
8361 | frag->gpa += len; | |
8362 | frag->len -= len; | |
8363 | } | |
8364 | ||
a08d3b3b | 8365 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { |
716d51ab | 8366 | vcpu->mmio_needed = 0; |
0912c977 PB |
8367 | |
8368 | /* FIXME: return into emulator if single-stepping. */ | |
cef4dea0 | 8369 | if (vcpu->mmio_is_write) |
716d51ab GN |
8370 | return 1; |
8371 | vcpu->mmio_read_completed = 1; | |
8372 | return complete_emulated_io(vcpu); | |
8373 | } | |
87da7e66 | 8374 | |
716d51ab GN |
8375 | run->exit_reason = KVM_EXIT_MMIO; |
8376 | run->mmio.phys_addr = frag->gpa; | |
8377 | if (vcpu->mmio_is_write) | |
87da7e66 XG |
8378 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); |
8379 | run->mmio.len = min(8u, frag->len); | |
716d51ab GN |
8380 | run->mmio.is_write = vcpu->mmio_is_write; |
8381 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; | |
8382 | return 0; | |
5287f194 AK |
8383 | } |
8384 | ||
822f312d SAS |
8385 | /* Swap (qemu) user FPU context for the guest FPU context. */ |
8386 | static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) | |
8387 | { | |
5f409e20 RR |
8388 | fpregs_lock(); |
8389 | ||
d9a710e5 | 8390 | copy_fpregs_to_fpstate(vcpu->arch.user_fpu); |
822f312d | 8391 | /* PKRU is separately restored in kvm_x86_ops->run. */ |
b666a4b6 | 8392 | __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state, |
822f312d | 8393 | ~XFEATURE_MASK_PKRU); |
5f409e20 RR |
8394 | |
8395 | fpregs_mark_activate(); | |
8396 | fpregs_unlock(); | |
8397 | ||
822f312d SAS |
8398 | trace_kvm_fpu(1); |
8399 | } | |
8400 | ||
8401 | /* When vcpu_run ends, restore user space FPU context. */ | |
8402 | static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
8403 | { | |
5f409e20 RR |
8404 | fpregs_lock(); |
8405 | ||
b666a4b6 | 8406 | copy_fpregs_to_fpstate(vcpu->arch.guest_fpu); |
d9a710e5 | 8407 | copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state); |
5f409e20 RR |
8408 | |
8409 | fpregs_mark_activate(); | |
8410 | fpregs_unlock(); | |
8411 | ||
822f312d SAS |
8412 | ++vcpu->stat.fpu_reload; |
8413 | trace_kvm_fpu(0); | |
8414 | } | |
8415 | ||
b6c7a5dc HB |
8416 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
8417 | { | |
8418 | int r; | |
b6c7a5dc | 8419 | |
accb757d | 8420 | vcpu_load(vcpu); |
20b7035c | 8421 | kvm_sigset_activate(vcpu); |
5663d8f9 PX |
8422 | kvm_load_guest_fpu(vcpu); |
8423 | ||
a4535290 | 8424 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
2f173d26 JS |
8425 | if (kvm_run->immediate_exit) { |
8426 | r = -EINTR; | |
8427 | goto out; | |
8428 | } | |
b6c7a5dc | 8429 | kvm_vcpu_block(vcpu); |
66450a21 | 8430 | kvm_apic_accept_events(vcpu); |
72875d8a | 8431 | kvm_clear_request(KVM_REQ_UNHALT, vcpu); |
ac9f6dc0 | 8432 | r = -EAGAIN; |
a0595000 JS |
8433 | if (signal_pending(current)) { |
8434 | r = -EINTR; | |
8435 | vcpu->run->exit_reason = KVM_EXIT_INTR; | |
8436 | ++vcpu->stat.signal_exits; | |
8437 | } | |
ac9f6dc0 | 8438 | goto out; |
b6c7a5dc HB |
8439 | } |
8440 | ||
01643c51 KH |
8441 | if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) { |
8442 | r = -EINVAL; | |
8443 | goto out; | |
8444 | } | |
8445 | ||
8446 | if (vcpu->run->kvm_dirty_regs) { | |
8447 | r = sync_regs(vcpu); | |
8448 | if (r != 0) | |
8449 | goto out; | |
8450 | } | |
8451 | ||
b6c7a5dc | 8452 | /* re-sync apic's tpr */ |
35754c98 | 8453 | if (!lapic_in_kernel(vcpu)) { |
eea1cff9 AP |
8454 | if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { |
8455 | r = -EINVAL; | |
8456 | goto out; | |
8457 | } | |
8458 | } | |
b6c7a5dc | 8459 | |
716d51ab GN |
8460 | if (unlikely(vcpu->arch.complete_userspace_io)) { |
8461 | int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; | |
8462 | vcpu->arch.complete_userspace_io = NULL; | |
8463 | r = cui(vcpu); | |
8464 | if (r <= 0) | |
5663d8f9 | 8465 | goto out; |
716d51ab GN |
8466 | } else |
8467 | WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); | |
5287f194 | 8468 | |
460df4c1 PB |
8469 | if (kvm_run->immediate_exit) |
8470 | r = -EINTR; | |
8471 | else | |
8472 | r = vcpu_run(vcpu); | |
b6c7a5dc HB |
8473 | |
8474 | out: | |
5663d8f9 | 8475 | kvm_put_guest_fpu(vcpu); |
01643c51 KH |
8476 | if (vcpu->run->kvm_valid_regs) |
8477 | store_regs(vcpu); | |
f1d86e46 | 8478 | post_kvm_run_save(vcpu); |
20b7035c | 8479 | kvm_sigset_deactivate(vcpu); |
b6c7a5dc | 8480 | |
accb757d | 8481 | vcpu_put(vcpu); |
b6c7a5dc HB |
8482 | return r; |
8483 | } | |
8484 | ||
01643c51 | 8485 | static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 8486 | { |
7ae441ea GN |
8487 | if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { |
8488 | /* | |
8489 | * We are here if userspace calls get_regs() in the middle of | |
8490 | * instruction emulation. Registers state needs to be copied | |
4a969980 | 8491 | * back from emulation context to vcpu. Userspace shouldn't do |
7ae441ea GN |
8492 | * that usually, but some bad designed PV devices (vmware |
8493 | * backdoor interface) need this to work | |
8494 | */ | |
dd856efa | 8495 | emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); |
7ae441ea GN |
8496 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
8497 | } | |
de3cd117 SC |
8498 | regs->rax = kvm_rax_read(vcpu); |
8499 | regs->rbx = kvm_rbx_read(vcpu); | |
8500 | regs->rcx = kvm_rcx_read(vcpu); | |
8501 | regs->rdx = kvm_rdx_read(vcpu); | |
8502 | regs->rsi = kvm_rsi_read(vcpu); | |
8503 | regs->rdi = kvm_rdi_read(vcpu); | |
e9c16c78 | 8504 | regs->rsp = kvm_rsp_read(vcpu); |
de3cd117 | 8505 | regs->rbp = kvm_rbp_read(vcpu); |
b6c7a5dc | 8506 | #ifdef CONFIG_X86_64 |
de3cd117 SC |
8507 | regs->r8 = kvm_r8_read(vcpu); |
8508 | regs->r9 = kvm_r9_read(vcpu); | |
8509 | regs->r10 = kvm_r10_read(vcpu); | |
8510 | regs->r11 = kvm_r11_read(vcpu); | |
8511 | regs->r12 = kvm_r12_read(vcpu); | |
8512 | regs->r13 = kvm_r13_read(vcpu); | |
8513 | regs->r14 = kvm_r14_read(vcpu); | |
8514 | regs->r15 = kvm_r15_read(vcpu); | |
b6c7a5dc HB |
8515 | #endif |
8516 | ||
5fdbf976 | 8517 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 8518 | regs->rflags = kvm_get_rflags(vcpu); |
01643c51 | 8519 | } |
b6c7a5dc | 8520 | |
01643c51 KH |
8521 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
8522 | { | |
8523 | vcpu_load(vcpu); | |
8524 | __get_regs(vcpu, regs); | |
1fc9b76b | 8525 | vcpu_put(vcpu); |
b6c7a5dc HB |
8526 | return 0; |
8527 | } | |
8528 | ||
01643c51 | 8529 | static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 8530 | { |
7ae441ea GN |
8531 | vcpu->arch.emulate_regs_need_sync_from_vcpu = true; |
8532 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; | |
8533 | ||
de3cd117 SC |
8534 | kvm_rax_write(vcpu, regs->rax); |
8535 | kvm_rbx_write(vcpu, regs->rbx); | |
8536 | kvm_rcx_write(vcpu, regs->rcx); | |
8537 | kvm_rdx_write(vcpu, regs->rdx); | |
8538 | kvm_rsi_write(vcpu, regs->rsi); | |
8539 | kvm_rdi_write(vcpu, regs->rdi); | |
e9c16c78 | 8540 | kvm_rsp_write(vcpu, regs->rsp); |
de3cd117 | 8541 | kvm_rbp_write(vcpu, regs->rbp); |
b6c7a5dc | 8542 | #ifdef CONFIG_X86_64 |
de3cd117 SC |
8543 | kvm_r8_write(vcpu, regs->r8); |
8544 | kvm_r9_write(vcpu, regs->r9); | |
8545 | kvm_r10_write(vcpu, regs->r10); | |
8546 | kvm_r11_write(vcpu, regs->r11); | |
8547 | kvm_r12_write(vcpu, regs->r12); | |
8548 | kvm_r13_write(vcpu, regs->r13); | |
8549 | kvm_r14_write(vcpu, regs->r14); | |
8550 | kvm_r15_write(vcpu, regs->r15); | |
b6c7a5dc HB |
8551 | #endif |
8552 | ||
5fdbf976 | 8553 | kvm_rip_write(vcpu, regs->rip); |
d73235d1 | 8554 | kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); |
b6c7a5dc | 8555 | |
b4f14abd JK |
8556 | vcpu->arch.exception.pending = false; |
8557 | ||
3842d135 | 8558 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
01643c51 | 8559 | } |
3842d135 | 8560 | |
01643c51 KH |
8561 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
8562 | { | |
8563 | vcpu_load(vcpu); | |
8564 | __set_regs(vcpu, regs); | |
875656fe | 8565 | vcpu_put(vcpu); |
b6c7a5dc HB |
8566 | return 0; |
8567 | } | |
8568 | ||
b6c7a5dc HB |
8569 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
8570 | { | |
8571 | struct kvm_segment cs; | |
8572 | ||
3e6e0aab | 8573 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
8574 | *db = cs.db; |
8575 | *l = cs.l; | |
8576 | } | |
8577 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
8578 | ||
01643c51 | 8579 | static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
b6c7a5dc | 8580 | { |
89a27f4d | 8581 | struct desc_ptr dt; |
b6c7a5dc | 8582 | |
3e6e0aab GT |
8583 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
8584 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
8585 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
8586 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
8587 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
8588 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 8589 | |
3e6e0aab GT |
8590 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
8591 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc HB |
8592 | |
8593 | kvm_x86_ops->get_idt(vcpu, &dt); | |
89a27f4d GN |
8594 | sregs->idt.limit = dt.size; |
8595 | sregs->idt.base = dt.address; | |
b6c7a5dc | 8596 | kvm_x86_ops->get_gdt(vcpu, &dt); |
89a27f4d GN |
8597 | sregs->gdt.limit = dt.size; |
8598 | sregs->gdt.base = dt.address; | |
b6c7a5dc | 8599 | |
4d4ec087 | 8600 | sregs->cr0 = kvm_read_cr0(vcpu); |
ad312c7c | 8601 | sregs->cr2 = vcpu->arch.cr2; |
9f8fe504 | 8602 | sregs->cr3 = kvm_read_cr3(vcpu); |
fc78f519 | 8603 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 8604 | sregs->cr8 = kvm_get_cr8(vcpu); |
f6801dff | 8605 | sregs->efer = vcpu->arch.efer; |
b6c7a5dc HB |
8606 | sregs->apic_base = kvm_get_apic_base(vcpu); |
8607 | ||
0e96f31e | 8608 | memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap)); |
b6c7a5dc | 8609 | |
04140b41 | 8610 | if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
8611 | set_bit(vcpu->arch.interrupt.nr, |
8612 | (unsigned long *)sregs->interrupt_bitmap); | |
01643c51 | 8613 | } |
16d7a191 | 8614 | |
01643c51 KH |
8615 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, |
8616 | struct kvm_sregs *sregs) | |
8617 | { | |
8618 | vcpu_load(vcpu); | |
8619 | __get_sregs(vcpu, sregs); | |
bcdec41c | 8620 | vcpu_put(vcpu); |
b6c7a5dc HB |
8621 | return 0; |
8622 | } | |
8623 | ||
62d9f0db MT |
8624 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
8625 | struct kvm_mp_state *mp_state) | |
8626 | { | |
fd232561 CD |
8627 | vcpu_load(vcpu); |
8628 | ||
66450a21 | 8629 | kvm_apic_accept_events(vcpu); |
6aef266c SV |
8630 | if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && |
8631 | vcpu->arch.pv.pv_unhalted) | |
8632 | mp_state->mp_state = KVM_MP_STATE_RUNNABLE; | |
8633 | else | |
8634 | mp_state->mp_state = vcpu->arch.mp_state; | |
8635 | ||
fd232561 | 8636 | vcpu_put(vcpu); |
62d9f0db MT |
8637 | return 0; |
8638 | } | |
8639 | ||
8640 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
8641 | struct kvm_mp_state *mp_state) | |
8642 | { | |
e83dff5e CD |
8643 | int ret = -EINVAL; |
8644 | ||
8645 | vcpu_load(vcpu); | |
8646 | ||
bce87cce | 8647 | if (!lapic_in_kernel(vcpu) && |
66450a21 | 8648 | mp_state->mp_state != KVM_MP_STATE_RUNNABLE) |
e83dff5e | 8649 | goto out; |
66450a21 | 8650 | |
28bf2888 DH |
8651 | /* INITs are latched while in SMM */ |
8652 | if ((is_smm(vcpu) || vcpu->arch.smi_pending) && | |
8653 | (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || | |
8654 | mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) | |
e83dff5e | 8655 | goto out; |
28bf2888 | 8656 | |
66450a21 JK |
8657 | if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { |
8658 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
8659 | set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); | |
8660 | } else | |
8661 | vcpu->arch.mp_state = mp_state->mp_state; | |
3842d135 | 8662 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
e83dff5e CD |
8663 | |
8664 | ret = 0; | |
8665 | out: | |
8666 | vcpu_put(vcpu); | |
8667 | return ret; | |
62d9f0db MT |
8668 | } |
8669 | ||
7f3d35fd KW |
8670 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
8671 | int reason, bool has_error_code, u32 error_code) | |
b6c7a5dc | 8672 | { |
9d74191a | 8673 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
8ec4722d | 8674 | int ret; |
e01c2426 | 8675 | |
8ec4722d | 8676 | init_emulate_ctxt(vcpu); |
c697518a | 8677 | |
7f3d35fd | 8678 | ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, |
9d74191a | 8679 | has_error_code, error_code); |
c697518a | 8680 | |
c697518a | 8681 | if (ret) |
19d04437 | 8682 | return EMULATE_FAIL; |
37817f29 | 8683 | |
9d74191a TY |
8684 | kvm_rip_write(vcpu, ctxt->eip); |
8685 | kvm_set_rflags(vcpu, ctxt->eflags); | |
3842d135 | 8686 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
19d04437 | 8687 | return EMULATE_DONE; |
37817f29 IE |
8688 | } |
8689 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
8690 | ||
3140c156 | 8691 | static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
f2981033 | 8692 | { |
74fec5b9 TL |
8693 | if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && |
8694 | (sregs->cr4 & X86_CR4_OSXSAVE)) | |
8695 | return -EINVAL; | |
8696 | ||
37b95951 | 8697 | if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { |
f2981033 LT |
8698 | /* |
8699 | * When EFER.LME and CR0.PG are set, the processor is in | |
8700 | * 64-bit mode (though maybe in a 32-bit code segment). | |
8701 | * CR4.PAE and EFER.LMA must be set. | |
8702 | */ | |
37b95951 | 8703 | if (!(sregs->cr4 & X86_CR4_PAE) |
f2981033 LT |
8704 | || !(sregs->efer & EFER_LMA)) |
8705 | return -EINVAL; | |
8706 | } else { | |
8707 | /* | |
8708 | * Not in 64-bit mode: EFER.LMA is clear and the code | |
8709 | * segment cannot be 64-bit. | |
8710 | */ | |
8711 | if (sregs->efer & EFER_LMA || sregs->cs.l) | |
8712 | return -EINVAL; | |
8713 | } | |
8714 | ||
8715 | return 0; | |
8716 | } | |
8717 | ||
01643c51 | 8718 | static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
b6c7a5dc | 8719 | { |
58cb628d | 8720 | struct msr_data apic_base_msr; |
b6c7a5dc | 8721 | int mmu_reset_needed = 0; |
c4d21882 | 8722 | int cpuid_update_needed = 0; |
63f42e02 | 8723 | int pending_vec, max_bits, idx; |
89a27f4d | 8724 | struct desc_ptr dt; |
b4ef9d4e CD |
8725 | int ret = -EINVAL; |
8726 | ||
f2981033 | 8727 | if (kvm_valid_sregs(vcpu, sregs)) |
8dbfb2bf | 8728 | goto out; |
f2981033 | 8729 | |
d3802286 JM |
8730 | apic_base_msr.data = sregs->apic_base; |
8731 | apic_base_msr.host_initiated = true; | |
8732 | if (kvm_set_apic_base(vcpu, &apic_base_msr)) | |
b4ef9d4e | 8733 | goto out; |
6d1068b3 | 8734 | |
89a27f4d GN |
8735 | dt.size = sregs->idt.limit; |
8736 | dt.address = sregs->idt.base; | |
b6c7a5dc | 8737 | kvm_x86_ops->set_idt(vcpu, &dt); |
89a27f4d GN |
8738 | dt.size = sregs->gdt.limit; |
8739 | dt.address = sregs->gdt.base; | |
b6c7a5dc HB |
8740 | kvm_x86_ops->set_gdt(vcpu, &dt); |
8741 | ||
ad312c7c | 8742 | vcpu->arch.cr2 = sregs->cr2; |
9f8fe504 | 8743 | mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; |
dc7e795e | 8744 | vcpu->arch.cr3 = sregs->cr3; |
aff48baa | 8745 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); |
b6c7a5dc | 8746 | |
2d3ad1f4 | 8747 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 8748 | |
f6801dff | 8749 | mmu_reset_needed |= vcpu->arch.efer != sregs->efer; |
b6c7a5dc | 8750 | kvm_x86_ops->set_efer(vcpu, sregs->efer); |
b6c7a5dc | 8751 | |
4d4ec087 | 8752 | mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
b6c7a5dc | 8753 | kvm_x86_ops->set_cr0(vcpu, sregs->cr0); |
d7306163 | 8754 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 8755 | |
fc78f519 | 8756 | mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
c4d21882 WH |
8757 | cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) & |
8758 | (X86_CR4_OSXSAVE | X86_CR4_PKE)); | |
b6c7a5dc | 8759 | kvm_x86_ops->set_cr4(vcpu, sregs->cr4); |
c4d21882 | 8760 | if (cpuid_update_needed) |
00b27a3e | 8761 | kvm_update_cpuid(vcpu); |
63f42e02 XG |
8762 | |
8763 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
bf03d4f9 | 8764 | if (is_pae_paging(vcpu)) { |
9f8fe504 | 8765 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
7c93be44 MT |
8766 | mmu_reset_needed = 1; |
8767 | } | |
63f42e02 | 8768 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b6c7a5dc HB |
8769 | |
8770 | if (mmu_reset_needed) | |
8771 | kvm_mmu_reset_context(vcpu); | |
8772 | ||
a50abc3b | 8773 | max_bits = KVM_NR_INTERRUPTS; |
923c61bb GN |
8774 | pending_vec = find_first_bit( |
8775 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
8776 | if (pending_vec < max_bits) { | |
66fd3f7f | 8777 | kvm_queue_interrupt(vcpu, pending_vec, false); |
923c61bb | 8778 | pr_debug("Set back pending irq %d\n", pending_vec); |
b6c7a5dc HB |
8779 | } |
8780 | ||
3e6e0aab GT |
8781 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
8782 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
8783 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
8784 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
8785 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
8786 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 8787 | |
3e6e0aab GT |
8788 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
8789 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 8790 | |
5f0269f5 ME |
8791 | update_cr8_intercept(vcpu); |
8792 | ||
9c3e4aab | 8793 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 8794 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 8795 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
3eeb3288 | 8796 | !is_protmode(vcpu)) |
9c3e4aab MT |
8797 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
8798 | ||
3842d135 AK |
8799 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
8800 | ||
b4ef9d4e CD |
8801 | ret = 0; |
8802 | out: | |
01643c51 KH |
8803 | return ret; |
8804 | } | |
8805 | ||
8806 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, | |
8807 | struct kvm_sregs *sregs) | |
8808 | { | |
8809 | int ret; | |
8810 | ||
8811 | vcpu_load(vcpu); | |
8812 | ret = __set_sregs(vcpu, sregs); | |
b4ef9d4e CD |
8813 | vcpu_put(vcpu); |
8814 | return ret; | |
b6c7a5dc HB |
8815 | } |
8816 | ||
d0bfb940 JK |
8817 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
8818 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 8819 | { |
355be0b9 | 8820 | unsigned long rflags; |
ae675ef0 | 8821 | int i, r; |
b6c7a5dc | 8822 | |
66b56562 CD |
8823 | vcpu_load(vcpu); |
8824 | ||
4f926bf2 JK |
8825 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
8826 | r = -EBUSY; | |
8827 | if (vcpu->arch.exception.pending) | |
2122ff5e | 8828 | goto out; |
4f926bf2 JK |
8829 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
8830 | kvm_queue_exception(vcpu, DB_VECTOR); | |
8831 | else | |
8832 | kvm_queue_exception(vcpu, BP_VECTOR); | |
8833 | } | |
8834 | ||
91586a3b JK |
8835 | /* |
8836 | * Read rflags as long as potentially injected trace flags are still | |
8837 | * filtered out. | |
8838 | */ | |
8839 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
8840 | |
8841 | vcpu->guest_debug = dbg->control; | |
8842 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
8843 | vcpu->guest_debug = 0; | |
8844 | ||
8845 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
8846 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
8847 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
c8639010 | 8848 | vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; |
ae675ef0 JK |
8849 | } else { |
8850 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
8851 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
ae675ef0 | 8852 | } |
c8639010 | 8853 | kvm_update_dr7(vcpu); |
ae675ef0 | 8854 | |
f92653ee JK |
8855 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
8856 | vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + | |
8857 | get_segment_base(vcpu, VCPU_SREG_CS); | |
94fe45da | 8858 | |
91586a3b JK |
8859 | /* |
8860 | * Trigger an rflags update that will inject or remove the trace | |
8861 | * flags. | |
8862 | */ | |
8863 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 8864 | |
a96036b8 | 8865 | kvm_x86_ops->update_bp_intercept(vcpu); |
b6c7a5dc | 8866 | |
4f926bf2 | 8867 | r = 0; |
d0bfb940 | 8868 | |
2122ff5e | 8869 | out: |
66b56562 | 8870 | vcpu_put(vcpu); |
b6c7a5dc HB |
8871 | return r; |
8872 | } | |
8873 | ||
8b006791 ZX |
8874 | /* |
8875 | * Translate a guest virtual address to a guest physical address. | |
8876 | */ | |
8877 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
8878 | struct kvm_translation *tr) | |
8879 | { | |
8880 | unsigned long vaddr = tr->linear_address; | |
8881 | gpa_t gpa; | |
f656ce01 | 8882 | int idx; |
8b006791 | 8883 | |
1da5b61d CD |
8884 | vcpu_load(vcpu); |
8885 | ||
f656ce01 | 8886 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1871c602 | 8887 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); |
f656ce01 | 8888 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 ZX |
8889 | tr->physical_address = gpa; |
8890 | tr->valid = gpa != UNMAPPED_GVA; | |
8891 | tr->writeable = 1; | |
8892 | tr->usermode = 0; | |
8b006791 | 8893 | |
1da5b61d | 8894 | vcpu_put(vcpu); |
8b006791 ZX |
8895 | return 0; |
8896 | } | |
8897 | ||
d0752060 HB |
8898 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
8899 | { | |
1393123e | 8900 | struct fxregs_state *fxsave; |
d0752060 | 8901 | |
1393123e | 8902 | vcpu_load(vcpu); |
d0752060 | 8903 | |
b666a4b6 | 8904 | fxsave = &vcpu->arch.guest_fpu->state.fxsave; |
d0752060 HB |
8905 | memcpy(fpu->fpr, fxsave->st_space, 128); |
8906 | fpu->fcw = fxsave->cwd; | |
8907 | fpu->fsw = fxsave->swd; | |
8908 | fpu->ftwx = fxsave->twd; | |
8909 | fpu->last_opcode = fxsave->fop; | |
8910 | fpu->last_ip = fxsave->rip; | |
8911 | fpu->last_dp = fxsave->rdp; | |
0e96f31e | 8912 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); |
d0752060 | 8913 | |
1393123e | 8914 | vcpu_put(vcpu); |
d0752060 HB |
8915 | return 0; |
8916 | } | |
8917 | ||
8918 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
8919 | { | |
6a96bc7f CD |
8920 | struct fxregs_state *fxsave; |
8921 | ||
8922 | vcpu_load(vcpu); | |
8923 | ||
b666a4b6 | 8924 | fxsave = &vcpu->arch.guest_fpu->state.fxsave; |
d0752060 | 8925 | |
d0752060 HB |
8926 | memcpy(fxsave->st_space, fpu->fpr, 128); |
8927 | fxsave->cwd = fpu->fcw; | |
8928 | fxsave->swd = fpu->fsw; | |
8929 | fxsave->twd = fpu->ftwx; | |
8930 | fxsave->fop = fpu->last_opcode; | |
8931 | fxsave->rip = fpu->last_ip; | |
8932 | fxsave->rdp = fpu->last_dp; | |
0e96f31e | 8933 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); |
d0752060 | 8934 | |
6a96bc7f | 8935 | vcpu_put(vcpu); |
d0752060 HB |
8936 | return 0; |
8937 | } | |
8938 | ||
01643c51 KH |
8939 | static void store_regs(struct kvm_vcpu *vcpu) |
8940 | { | |
8941 | BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); | |
8942 | ||
8943 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) | |
8944 | __get_regs(vcpu, &vcpu->run->s.regs.regs); | |
8945 | ||
8946 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) | |
8947 | __get_sregs(vcpu, &vcpu->run->s.regs.sregs); | |
8948 | ||
8949 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) | |
8950 | kvm_vcpu_ioctl_x86_get_vcpu_events( | |
8951 | vcpu, &vcpu->run->s.regs.events); | |
8952 | } | |
8953 | ||
8954 | static int sync_regs(struct kvm_vcpu *vcpu) | |
8955 | { | |
8956 | if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS) | |
8957 | return -EINVAL; | |
8958 | ||
8959 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { | |
8960 | __set_regs(vcpu, &vcpu->run->s.regs.regs); | |
8961 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; | |
8962 | } | |
8963 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { | |
8964 | if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) | |
8965 | return -EINVAL; | |
8966 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; | |
8967 | } | |
8968 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { | |
8969 | if (kvm_vcpu_ioctl_x86_set_vcpu_events( | |
8970 | vcpu, &vcpu->run->s.regs.events)) | |
8971 | return -EINVAL; | |
8972 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; | |
8973 | } | |
8974 | ||
8975 | return 0; | |
8976 | } | |
8977 | ||
0ee6a517 | 8978 | static void fx_init(struct kvm_vcpu *vcpu) |
d0752060 | 8979 | { |
b666a4b6 | 8980 | fpstate_init(&vcpu->arch.guest_fpu->state); |
782511b0 | 8981 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
b666a4b6 | 8982 | vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv = |
df1daba7 | 8983 | host_xcr0 | XSTATE_COMPACTION_ENABLED; |
d0752060 | 8984 | |
2acf923e DC |
8985 | /* |
8986 | * Ensure guest xcr0 is valid for loading | |
8987 | */ | |
d91cab78 | 8988 | vcpu->arch.xcr0 = XFEATURE_MASK_FP; |
2acf923e | 8989 | |
ad312c7c | 8990 | vcpu->arch.cr0 |= X86_CR0_ET; |
d0752060 | 8991 | } |
d0752060 | 8992 | |
e9b11c17 ZX |
8993 | void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) |
8994 | { | |
bd768e14 IY |
8995 | void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask; |
8996 | ||
12f9a48f | 8997 | kvmclock_reset(vcpu); |
7f1ea208 | 8998 | |
e9b11c17 | 8999 | kvm_x86_ops->vcpu_free(vcpu); |
bd768e14 | 9000 | free_cpumask_var(wbinvd_dirty_mask); |
e9b11c17 ZX |
9001 | } |
9002 | ||
9003 | struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, | |
9004 | unsigned int id) | |
9005 | { | |
c447e76b LL |
9006 | struct kvm_vcpu *vcpu; |
9007 | ||
b0c39dc6 | 9008 | if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) |
6755bae8 ZA |
9009 | printk_once(KERN_WARNING |
9010 | "kvm: SMP vm created on host with unstable TSC; " | |
9011 | "guest TSC will not be reliable\n"); | |
c447e76b LL |
9012 | |
9013 | vcpu = kvm_x86_ops->vcpu_create(kvm, id); | |
9014 | ||
c447e76b | 9015 | return vcpu; |
26e5215f | 9016 | } |
e9b11c17 | 9017 | |
26e5215f AK |
9018 | int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) |
9019 | { | |
0cf9135b | 9020 | vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); |
e53d88af | 9021 | vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; |
19efffa2 | 9022 | kvm_vcpu_mtrr_init(vcpu); |
ec7660cc | 9023 | vcpu_load(vcpu); |
d28bc9dd | 9024 | kvm_vcpu_reset(vcpu, false); |
e1732991 | 9025 | kvm_init_mmu(vcpu, false); |
e9b11c17 | 9026 | vcpu_put(vcpu); |
ec7660cc | 9027 | return 0; |
e9b11c17 ZX |
9028 | } |
9029 | ||
31928aa5 | 9030 | void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) |
42897d86 | 9031 | { |
8fe8ab46 | 9032 | struct msr_data msr; |
332967a3 | 9033 | struct kvm *kvm = vcpu->kvm; |
42897d86 | 9034 | |
d3457c87 RK |
9035 | kvm_hv_vcpu_postcreate(vcpu); |
9036 | ||
ec7660cc | 9037 | if (mutex_lock_killable(&vcpu->mutex)) |
31928aa5 | 9038 | return; |
ec7660cc | 9039 | vcpu_load(vcpu); |
8fe8ab46 WA |
9040 | msr.data = 0x0; |
9041 | msr.index = MSR_IA32_TSC; | |
9042 | msr.host_initiated = true; | |
9043 | kvm_write_tsc(vcpu, &msr); | |
42897d86 | 9044 | vcpu_put(vcpu); |
2d5ba19b MT |
9045 | |
9046 | /* poll control enabled by default */ | |
9047 | vcpu->arch.msr_kvm_poll_control = 1; | |
9048 | ||
ec7660cc | 9049 | mutex_unlock(&vcpu->mutex); |
42897d86 | 9050 | |
630994b3 MT |
9051 | if (!kvmclock_periodic_sync) |
9052 | return; | |
9053 | ||
332967a3 AJ |
9054 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, |
9055 | KVMCLOCK_SYNC_PERIOD); | |
42897d86 MT |
9056 | } |
9057 | ||
d40ccc62 | 9058 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 | 9059 | { |
344d9588 GN |
9060 | vcpu->arch.apf.msr_val = 0; |
9061 | ||
ec7660cc | 9062 | vcpu_load(vcpu); |
e9b11c17 ZX |
9063 | kvm_mmu_unload(vcpu); |
9064 | vcpu_put(vcpu); | |
9065 | ||
9066 | kvm_x86_ops->vcpu_free(vcpu); | |
9067 | } | |
9068 | ||
d28bc9dd | 9069 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
e9b11c17 | 9070 | { |
b7e31be3 RK |
9071 | kvm_lapic_reset(vcpu, init_event); |
9072 | ||
e69fab5d PB |
9073 | vcpu->arch.hflags = 0; |
9074 | ||
c43203ca | 9075 | vcpu->arch.smi_pending = 0; |
52797bf9 | 9076 | vcpu->arch.smi_count = 0; |
7460fb4a AK |
9077 | atomic_set(&vcpu->arch.nmi_queued, 0); |
9078 | vcpu->arch.nmi_pending = 0; | |
448fa4a9 | 9079 | vcpu->arch.nmi_injected = false; |
5f7552d4 NA |
9080 | kvm_clear_interrupt_queue(vcpu); |
9081 | kvm_clear_exception_queue(vcpu); | |
664f8e26 | 9082 | vcpu->arch.exception.pending = false; |
448fa4a9 | 9083 | |
42dbaa5a | 9084 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); |
ae561ede | 9085 | kvm_update_dr0123(vcpu); |
6f43ed01 | 9086 | vcpu->arch.dr6 = DR6_INIT; |
73aaf249 | 9087 | kvm_update_dr6(vcpu); |
42dbaa5a | 9088 | vcpu->arch.dr7 = DR7_FIXED_1; |
c8639010 | 9089 | kvm_update_dr7(vcpu); |
42dbaa5a | 9090 | |
1119022c NA |
9091 | vcpu->arch.cr2 = 0; |
9092 | ||
3842d135 | 9093 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
344d9588 | 9094 | vcpu->arch.apf.msr_val = 0; |
c9aaa895 | 9095 | vcpu->arch.st.msr_val = 0; |
3842d135 | 9096 | |
12f9a48f GC |
9097 | kvmclock_reset(vcpu); |
9098 | ||
af585b92 GN |
9099 | kvm_clear_async_pf_completion_queue(vcpu); |
9100 | kvm_async_pf_hash_reset(vcpu); | |
9101 | vcpu->arch.apf.halted = false; | |
3842d135 | 9102 | |
a554d207 WL |
9103 | if (kvm_mpx_supported()) { |
9104 | void *mpx_state_buffer; | |
9105 | ||
9106 | /* | |
9107 | * To avoid have the INIT path from kvm_apic_has_events() that be | |
9108 | * called with loaded FPU and does not let userspace fix the state. | |
9109 | */ | |
f775b13e RR |
9110 | if (init_event) |
9111 | kvm_put_guest_fpu(vcpu); | |
b666a4b6 | 9112 | mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, |
abd16d68 | 9113 | XFEATURE_BNDREGS); |
a554d207 WL |
9114 | if (mpx_state_buffer) |
9115 | memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state)); | |
b666a4b6 | 9116 | mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, |
abd16d68 | 9117 | XFEATURE_BNDCSR); |
a554d207 WL |
9118 | if (mpx_state_buffer) |
9119 | memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr)); | |
f775b13e RR |
9120 | if (init_event) |
9121 | kvm_load_guest_fpu(vcpu); | |
a554d207 WL |
9122 | } |
9123 | ||
64d60670 | 9124 | if (!init_event) { |
d28bc9dd | 9125 | kvm_pmu_reset(vcpu); |
64d60670 | 9126 | vcpu->arch.smbase = 0x30000; |
db2336a8 | 9127 | |
db2336a8 | 9128 | vcpu->arch.msr_misc_features_enables = 0; |
a554d207 WL |
9129 | |
9130 | vcpu->arch.xcr0 = XFEATURE_MASK_FP; | |
64d60670 | 9131 | } |
f5132b01 | 9132 | |
66f7b72e JS |
9133 | memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); |
9134 | vcpu->arch.regs_avail = ~0; | |
9135 | vcpu->arch.regs_dirty = ~0; | |
9136 | ||
a554d207 WL |
9137 | vcpu->arch.ia32_xss = 0; |
9138 | ||
d28bc9dd | 9139 | kvm_x86_ops->vcpu_reset(vcpu, init_event); |
e9b11c17 ZX |
9140 | } |
9141 | ||
2b4a273b | 9142 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) |
66450a21 JK |
9143 | { |
9144 | struct kvm_segment cs; | |
9145 | ||
9146 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
9147 | cs.selector = vector << 8; | |
9148 | cs.base = vector << 12; | |
9149 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
9150 | kvm_rip_write(vcpu, 0); | |
e9b11c17 ZX |
9151 | } |
9152 | ||
13a34e06 | 9153 | int kvm_arch_hardware_enable(void) |
e9b11c17 | 9154 | { |
ca84d1a2 ZA |
9155 | struct kvm *kvm; |
9156 | struct kvm_vcpu *vcpu; | |
9157 | int i; | |
0dd6a6ed ZA |
9158 | int ret; |
9159 | u64 local_tsc; | |
9160 | u64 max_tsc = 0; | |
9161 | bool stable, backwards_tsc = false; | |
18863bdd AK |
9162 | |
9163 | kvm_shared_msr_cpu_online(); | |
13a34e06 | 9164 | ret = kvm_x86_ops->hardware_enable(); |
0dd6a6ed ZA |
9165 | if (ret != 0) |
9166 | return ret; | |
9167 | ||
4ea1636b | 9168 | local_tsc = rdtsc(); |
b0c39dc6 | 9169 | stable = !kvm_check_tsc_unstable(); |
0dd6a6ed ZA |
9170 | list_for_each_entry(kvm, &vm_list, vm_list) { |
9171 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
9172 | if (!stable && vcpu->cpu == smp_processor_id()) | |
105b21bb | 9173 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
9174 | if (stable && vcpu->arch.last_host_tsc > local_tsc) { |
9175 | backwards_tsc = true; | |
9176 | if (vcpu->arch.last_host_tsc > max_tsc) | |
9177 | max_tsc = vcpu->arch.last_host_tsc; | |
9178 | } | |
9179 | } | |
9180 | } | |
9181 | ||
9182 | /* | |
9183 | * Sometimes, even reliable TSCs go backwards. This happens on | |
9184 | * platforms that reset TSC during suspend or hibernate actions, but | |
9185 | * maintain synchronization. We must compensate. Fortunately, we can | |
9186 | * detect that condition here, which happens early in CPU bringup, | |
9187 | * before any KVM threads can be running. Unfortunately, we can't | |
9188 | * bring the TSCs fully up to date with real time, as we aren't yet far | |
9189 | * enough into CPU bringup that we know how much real time has actually | |
9285ec4c | 9190 | * elapsed; our helper function, ktime_get_boottime_ns() will be using boot |
0dd6a6ed ZA |
9191 | * variables that haven't been updated yet. |
9192 | * | |
9193 | * So we simply find the maximum observed TSC above, then record the | |
9194 | * adjustment to TSC in each VCPU. When the VCPU later gets loaded, | |
9195 | * the adjustment will be applied. Note that we accumulate | |
9196 | * adjustments, in case multiple suspend cycles happen before some VCPU | |
9197 | * gets a chance to run again. In the event that no KVM threads get a | |
9198 | * chance to run, we will miss the entire elapsed period, as we'll have | |
9199 | * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may | |
9200 | * loose cycle time. This isn't too big a deal, since the loss will be | |
9201 | * uniform across all VCPUs (not to mention the scenario is extremely | |
9202 | * unlikely). It is possible that a second hibernate recovery happens | |
9203 | * much faster than a first, causing the observed TSC here to be | |
9204 | * smaller; this would require additional padding adjustment, which is | |
9205 | * why we set last_host_tsc to the local tsc observed here. | |
9206 | * | |
9207 | * N.B. - this code below runs only on platforms with reliable TSC, | |
9208 | * as that is the only way backwards_tsc is set above. Also note | |
9209 | * that this runs for ALL vcpus, which is not a bug; all VCPUs should | |
9210 | * have the same delta_cyc adjustment applied if backwards_tsc | |
9211 | * is detected. Note further, this adjustment is only done once, | |
9212 | * as we reset last_host_tsc on all VCPUs to stop this from being | |
9213 | * called multiple times (one for each physical CPU bringup). | |
9214 | * | |
4a969980 | 9215 | * Platforms with unreliable TSCs don't have to deal with this, they |
0dd6a6ed ZA |
9216 | * will be compensated by the logic in vcpu_load, which sets the TSC to |
9217 | * catchup mode. This will catchup all VCPUs to real time, but cannot | |
9218 | * guarantee that they stay in perfect synchronization. | |
9219 | */ | |
9220 | if (backwards_tsc) { | |
9221 | u64 delta_cyc = max_tsc - local_tsc; | |
9222 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
a826faf1 | 9223 | kvm->arch.backwards_tsc_observed = true; |
0dd6a6ed ZA |
9224 | kvm_for_each_vcpu(i, vcpu, kvm) { |
9225 | vcpu->arch.tsc_offset_adjustment += delta_cyc; | |
9226 | vcpu->arch.last_host_tsc = local_tsc; | |
105b21bb | 9227 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
9228 | } |
9229 | ||
9230 | /* | |
9231 | * We have to disable TSC offset matching.. if you were | |
9232 | * booting a VM while issuing an S4 host suspend.... | |
9233 | * you may have some problem. Solving this issue is | |
9234 | * left as an exercise to the reader. | |
9235 | */ | |
9236 | kvm->arch.last_tsc_nsec = 0; | |
9237 | kvm->arch.last_tsc_write = 0; | |
9238 | } | |
9239 | ||
9240 | } | |
9241 | return 0; | |
e9b11c17 ZX |
9242 | } |
9243 | ||
13a34e06 | 9244 | void kvm_arch_hardware_disable(void) |
e9b11c17 | 9245 | { |
13a34e06 RK |
9246 | kvm_x86_ops->hardware_disable(); |
9247 | drop_user_return_notifiers(); | |
e9b11c17 ZX |
9248 | } |
9249 | ||
9250 | int kvm_arch_hardware_setup(void) | |
9251 | { | |
9e9c3fe4 NA |
9252 | int r; |
9253 | ||
9254 | r = kvm_x86_ops->hardware_setup(); | |
9255 | if (r != 0) | |
9256 | return r; | |
9257 | ||
35181e86 HZ |
9258 | if (kvm_has_tsc_control) { |
9259 | /* | |
9260 | * Make sure the user can only configure tsc_khz values that | |
9261 | * fit into a signed integer. | |
273ba457 | 9262 | * A min value is not calculated because it will always |
35181e86 HZ |
9263 | * be 1 on all machines. |
9264 | */ | |
9265 | u64 max = min(0x7fffffffULL, | |
9266 | __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); | |
9267 | kvm_max_guest_tsc_khz = max; | |
9268 | ||
ad721883 | 9269 | kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; |
35181e86 | 9270 | } |
ad721883 | 9271 | |
9e9c3fe4 NA |
9272 | kvm_init_msr_list(); |
9273 | return 0; | |
e9b11c17 ZX |
9274 | } |
9275 | ||
9276 | void kvm_arch_hardware_unsetup(void) | |
9277 | { | |
9278 | kvm_x86_ops->hardware_unsetup(); | |
9279 | } | |
9280 | ||
f257d6dc | 9281 | int kvm_arch_check_processor_compat(void) |
e9b11c17 | 9282 | { |
f257d6dc | 9283 | return kvm_x86_ops->check_processor_compatibility(); |
d71ba788 PB |
9284 | } |
9285 | ||
9286 | bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) | |
9287 | { | |
9288 | return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; | |
9289 | } | |
9290 | EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); | |
9291 | ||
9292 | bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) | |
9293 | { | |
9294 | return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; | |
e9b11c17 ZX |
9295 | } |
9296 | ||
54e9818f | 9297 | struct static_key kvm_no_apic_vcpu __read_mostly; |
bce87cce | 9298 | EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu); |
54e9818f | 9299 | |
e9b11c17 ZX |
9300 | int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) |
9301 | { | |
9302 | struct page *page; | |
e9b11c17 ZX |
9303 | int r; |
9304 | ||
9aabc88f | 9305 | vcpu->arch.emulate_ctxt.ops = &emulate_ops; |
26de7988 | 9306 | if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) |
a4535290 | 9307 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
e9b11c17 | 9308 | else |
a4535290 | 9309 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; |
e9b11c17 ZX |
9310 | |
9311 | page = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
9312 | if (!page) { | |
9313 | r = -ENOMEM; | |
9314 | goto fail; | |
9315 | } | |
ad312c7c | 9316 | vcpu->arch.pio_data = page_address(page); |
e9b11c17 | 9317 | |
cc578287 | 9318 | kvm_set_tsc_khz(vcpu, max_tsc_khz); |
c285545f | 9319 | |
e9b11c17 ZX |
9320 | r = kvm_mmu_create(vcpu); |
9321 | if (r < 0) | |
9322 | goto fail_free_pio_data; | |
9323 | ||
26de7988 | 9324 | if (irqchip_in_kernel(vcpu->kvm)) { |
f7589cca | 9325 | vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu); |
39497d76 | 9326 | r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); |
e9b11c17 ZX |
9327 | if (r < 0) |
9328 | goto fail_mmu_destroy; | |
54e9818f GN |
9329 | } else |
9330 | static_key_slow_inc(&kvm_no_apic_vcpu); | |
e9b11c17 | 9331 | |
890ca9ae | 9332 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, |
254272ce | 9333 | GFP_KERNEL_ACCOUNT); |
890ca9ae HY |
9334 | if (!vcpu->arch.mce_banks) { |
9335 | r = -ENOMEM; | |
443c39bc | 9336 | goto fail_free_lapic; |
890ca9ae HY |
9337 | } |
9338 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
9339 | ||
254272ce BG |
9340 | if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, |
9341 | GFP_KERNEL_ACCOUNT)) { | |
f1797359 | 9342 | r = -ENOMEM; |
f5f48ee1 | 9343 | goto fail_free_mce_banks; |
f1797359 | 9344 | } |
f5f48ee1 | 9345 | |
0ee6a517 | 9346 | fx_init(vcpu); |
66f7b72e | 9347 | |
4344ee98 | 9348 | vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; |
d7876f1b | 9349 | |
5a4f55cd EK |
9350 | vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); |
9351 | ||
74545705 RK |
9352 | vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; |
9353 | ||
af585b92 | 9354 | kvm_async_pf_hash_reset(vcpu); |
f5132b01 | 9355 | kvm_pmu_init(vcpu); |
af585b92 | 9356 | |
1c1a9ce9 | 9357 | vcpu->arch.pending_external_vector = -1; |
de63ad4c | 9358 | vcpu->arch.preempted_in_kernel = false; |
1c1a9ce9 | 9359 | |
5c919412 AS |
9360 | kvm_hv_vcpu_init(vcpu); |
9361 | ||
e9b11c17 | 9362 | return 0; |
0ee6a517 | 9363 | |
f5f48ee1 SY |
9364 | fail_free_mce_banks: |
9365 | kfree(vcpu->arch.mce_banks); | |
443c39bc WY |
9366 | fail_free_lapic: |
9367 | kvm_free_lapic(vcpu); | |
e9b11c17 ZX |
9368 | fail_mmu_destroy: |
9369 | kvm_mmu_destroy(vcpu); | |
9370 | fail_free_pio_data: | |
ad312c7c | 9371 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 ZX |
9372 | fail: |
9373 | return r; | |
9374 | } | |
9375 | ||
9376 | void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) | |
9377 | { | |
f656ce01 MT |
9378 | int idx; |
9379 | ||
1f4b34f8 | 9380 | kvm_hv_vcpu_uninit(vcpu); |
f5132b01 | 9381 | kvm_pmu_destroy(vcpu); |
36cb93fd | 9382 | kfree(vcpu->arch.mce_banks); |
e9b11c17 | 9383 | kvm_free_lapic(vcpu); |
f656ce01 | 9384 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
e9b11c17 | 9385 | kvm_mmu_destroy(vcpu); |
f656ce01 | 9386 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
ad312c7c | 9387 | free_page((unsigned long)vcpu->arch.pio_data); |
35754c98 | 9388 | if (!lapic_in_kernel(vcpu)) |
54e9818f | 9389 | static_key_slow_dec(&kvm_no_apic_vcpu); |
e9b11c17 | 9390 | } |
d19a9cd2 | 9391 | |
e790d9ef RK |
9392 | void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) |
9393 | { | |
c595ceee | 9394 | vcpu->arch.l1tf_flush_l1d = true; |
ae97a3b8 | 9395 | kvm_x86_ops->sched_in(vcpu, cpu); |
e790d9ef RK |
9396 | } |
9397 | ||
e08b9637 | 9398 | int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) |
d19a9cd2 | 9399 | { |
e08b9637 CO |
9400 | if (type) |
9401 | return -EINVAL; | |
9402 | ||
6ef768fa | 9403 | INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); |
f05e70ac | 9404 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
4d5c5d0f | 9405 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
e0f0bbc5 | 9406 | atomic_set(&kvm->arch.noncoherent_dma_count, 0); |
d19a9cd2 | 9407 | |
5550af4d SY |
9408 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
9409 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
7a84428a AW |
9410 | /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ |
9411 | set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, | |
9412 | &kvm->arch.irq_sources_bitmap); | |
5550af4d | 9413 | |
038f8c11 | 9414 | raw_spin_lock_init(&kvm->arch.tsc_write_lock); |
1e08ec4a | 9415 | mutex_init(&kvm->arch.apic_map_lock); |
d828199e MT |
9416 | spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); |
9417 | ||
9285ec4c | 9418 | kvm->arch.kvmclock_offset = -ktime_get_boottime_ns(); |
d828199e | 9419 | pvclock_update_vm_gtod_copy(kvm); |
53f658b3 | 9420 | |
6fbbde9a DS |
9421 | kvm->arch.guest_can_read_msr_platform_info = true; |
9422 | ||
7e44e449 | 9423 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); |
332967a3 | 9424 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); |
7e44e449 | 9425 | |
cbc0236a | 9426 | kvm_hv_init_vm(kvm); |
0eb05bf2 | 9427 | kvm_page_track_init(kvm); |
13d268ca | 9428 | kvm_mmu_init_vm(kvm); |
0eb05bf2 | 9429 | |
92735b1b | 9430 | return kvm_x86_ops->vm_init(kvm); |
d19a9cd2 ZX |
9431 | } |
9432 | ||
9433 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) | |
9434 | { | |
ec7660cc | 9435 | vcpu_load(vcpu); |
d19a9cd2 ZX |
9436 | kvm_mmu_unload(vcpu); |
9437 | vcpu_put(vcpu); | |
9438 | } | |
9439 | ||
9440 | static void kvm_free_vcpus(struct kvm *kvm) | |
9441 | { | |
9442 | unsigned int i; | |
988a2cae | 9443 | struct kvm_vcpu *vcpu; |
d19a9cd2 ZX |
9444 | |
9445 | /* | |
9446 | * Unpin any mmu pages first. | |
9447 | */ | |
af585b92 GN |
9448 | kvm_for_each_vcpu(i, vcpu, kvm) { |
9449 | kvm_clear_async_pf_completion_queue(vcpu); | |
988a2cae | 9450 | kvm_unload_vcpu_mmu(vcpu); |
af585b92 | 9451 | } |
988a2cae GN |
9452 | kvm_for_each_vcpu(i, vcpu, kvm) |
9453 | kvm_arch_vcpu_free(vcpu); | |
9454 | ||
9455 | mutex_lock(&kvm->lock); | |
9456 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
9457 | kvm->vcpus[i] = NULL; | |
d19a9cd2 | 9458 | |
988a2cae GN |
9459 | atomic_set(&kvm->online_vcpus, 0); |
9460 | mutex_unlock(&kvm->lock); | |
d19a9cd2 ZX |
9461 | } |
9462 | ||
ad8ba2cd SY |
9463 | void kvm_arch_sync_events(struct kvm *kvm) |
9464 | { | |
332967a3 | 9465 | cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); |
7e44e449 | 9466 | cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); |
aea924f6 | 9467 | kvm_free_pit(kvm); |
ad8ba2cd SY |
9468 | } |
9469 | ||
1d8007bd | 9470 | int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) |
9da0e4d5 PB |
9471 | { |
9472 | int i, r; | |
25188b99 | 9473 | unsigned long hva; |
f0d648bd PB |
9474 | struct kvm_memslots *slots = kvm_memslots(kvm); |
9475 | struct kvm_memory_slot *slot, old; | |
9da0e4d5 PB |
9476 | |
9477 | /* Called with kvm->slots_lock held. */ | |
1d8007bd PB |
9478 | if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) |
9479 | return -EINVAL; | |
9da0e4d5 | 9480 | |
f0d648bd PB |
9481 | slot = id_to_memslot(slots, id); |
9482 | if (size) { | |
b21629da | 9483 | if (slot->npages) |
f0d648bd PB |
9484 | return -EEXIST; |
9485 | ||
9486 | /* | |
9487 | * MAP_SHARED to prevent internal slot pages from being moved | |
9488 | * by fork()/COW. | |
9489 | */ | |
9490 | hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, | |
9491 | MAP_SHARED | MAP_ANONYMOUS, 0); | |
9492 | if (IS_ERR((void *)hva)) | |
9493 | return PTR_ERR((void *)hva); | |
9494 | } else { | |
9495 | if (!slot->npages) | |
9496 | return 0; | |
9497 | ||
9498 | hva = 0; | |
9499 | } | |
9500 | ||
9501 | old = *slot; | |
9da0e4d5 | 9502 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
1d8007bd | 9503 | struct kvm_userspace_memory_region m; |
9da0e4d5 | 9504 | |
1d8007bd PB |
9505 | m.slot = id | (i << 16); |
9506 | m.flags = 0; | |
9507 | m.guest_phys_addr = gpa; | |
f0d648bd | 9508 | m.userspace_addr = hva; |
1d8007bd | 9509 | m.memory_size = size; |
9da0e4d5 PB |
9510 | r = __kvm_set_memory_region(kvm, &m); |
9511 | if (r < 0) | |
9512 | return r; | |
9513 | } | |
9514 | ||
103c763c EB |
9515 | if (!size) |
9516 | vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE); | |
f0d648bd | 9517 | |
9da0e4d5 PB |
9518 | return 0; |
9519 | } | |
9520 | EXPORT_SYMBOL_GPL(__x86_set_memory_region); | |
9521 | ||
1d8007bd | 9522 | int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) |
9da0e4d5 PB |
9523 | { |
9524 | int r; | |
9525 | ||
9526 | mutex_lock(&kvm->slots_lock); | |
1d8007bd | 9527 | r = __x86_set_memory_region(kvm, id, gpa, size); |
9da0e4d5 PB |
9528 | mutex_unlock(&kvm->slots_lock); |
9529 | ||
9530 | return r; | |
9531 | } | |
9532 | EXPORT_SYMBOL_GPL(x86_set_memory_region); | |
9533 | ||
d19a9cd2 ZX |
9534 | void kvm_arch_destroy_vm(struct kvm *kvm) |
9535 | { | |
27469d29 AH |
9536 | if (current->mm == kvm->mm) { |
9537 | /* | |
9538 | * Free memory regions allocated on behalf of userspace, | |
9539 | * unless the the memory map has changed due to process exit | |
9540 | * or fd copying. | |
9541 | */ | |
1d8007bd PB |
9542 | x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0); |
9543 | x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0); | |
9544 | x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); | |
27469d29 | 9545 | } |
03543133 SS |
9546 | if (kvm_x86_ops->vm_destroy) |
9547 | kvm_x86_ops->vm_destroy(kvm); | |
c761159c PX |
9548 | kvm_pic_destroy(kvm); |
9549 | kvm_ioapic_destroy(kvm); | |
d19a9cd2 | 9550 | kvm_free_vcpus(kvm); |
af1bae54 | 9551 | kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); |
66bb8a06 | 9552 | kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); |
13d268ca | 9553 | kvm_mmu_uninit_vm(kvm); |
2beb6dad | 9554 | kvm_page_track_cleanup(kvm); |
cbc0236a | 9555 | kvm_hv_destroy_vm(kvm); |
d19a9cd2 | 9556 | } |
0de10343 | 9557 | |
5587027c | 9558 | void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, |
db3fe4eb TY |
9559 | struct kvm_memory_slot *dont) |
9560 | { | |
9561 | int i; | |
9562 | ||
d89cc617 TY |
9563 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
9564 | if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { | |
548ef284 | 9565 | kvfree(free->arch.rmap[i]); |
d89cc617 | 9566 | free->arch.rmap[i] = NULL; |
77d11309 | 9567 | } |
d89cc617 TY |
9568 | if (i == 0) |
9569 | continue; | |
9570 | ||
9571 | if (!dont || free->arch.lpage_info[i - 1] != | |
9572 | dont->arch.lpage_info[i - 1]) { | |
548ef284 | 9573 | kvfree(free->arch.lpage_info[i - 1]); |
d89cc617 | 9574 | free->arch.lpage_info[i - 1] = NULL; |
db3fe4eb TY |
9575 | } |
9576 | } | |
21ebbeda XG |
9577 | |
9578 | kvm_page_track_free_memslot(free, dont); | |
db3fe4eb TY |
9579 | } |
9580 | ||
5587027c AK |
9581 | int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, |
9582 | unsigned long npages) | |
db3fe4eb TY |
9583 | { |
9584 | int i; | |
9585 | ||
d89cc617 | 9586 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
92f94f1e | 9587 | struct kvm_lpage_info *linfo; |
db3fe4eb TY |
9588 | unsigned long ugfn; |
9589 | int lpages; | |
d89cc617 | 9590 | int level = i + 1; |
db3fe4eb TY |
9591 | |
9592 | lpages = gfn_to_index(slot->base_gfn + npages - 1, | |
9593 | slot->base_gfn, level) + 1; | |
9594 | ||
d89cc617 | 9595 | slot->arch.rmap[i] = |
778e1cdd | 9596 | kvcalloc(lpages, sizeof(*slot->arch.rmap[i]), |
254272ce | 9597 | GFP_KERNEL_ACCOUNT); |
d89cc617 | 9598 | if (!slot->arch.rmap[i]) |
77d11309 | 9599 | goto out_free; |
d89cc617 TY |
9600 | if (i == 0) |
9601 | continue; | |
77d11309 | 9602 | |
254272ce | 9603 | linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); |
92f94f1e | 9604 | if (!linfo) |
db3fe4eb TY |
9605 | goto out_free; |
9606 | ||
92f94f1e XG |
9607 | slot->arch.lpage_info[i - 1] = linfo; |
9608 | ||
db3fe4eb | 9609 | if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 9610 | linfo[0].disallow_lpage = 1; |
db3fe4eb | 9611 | if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 9612 | linfo[lpages - 1].disallow_lpage = 1; |
db3fe4eb TY |
9613 | ugfn = slot->userspace_addr >> PAGE_SHIFT; |
9614 | /* | |
9615 | * If the gfn and userspace address are not aligned wrt each | |
9616 | * other, or if explicitly asked to, disable large page | |
9617 | * support for this slot | |
9618 | */ | |
9619 | if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || | |
9620 | !kvm_largepages_enabled()) { | |
9621 | unsigned long j; | |
9622 | ||
9623 | for (j = 0; j < lpages; ++j) | |
92f94f1e | 9624 | linfo[j].disallow_lpage = 1; |
db3fe4eb TY |
9625 | } |
9626 | } | |
9627 | ||
21ebbeda XG |
9628 | if (kvm_page_track_create_memslot(slot, npages)) |
9629 | goto out_free; | |
9630 | ||
db3fe4eb TY |
9631 | return 0; |
9632 | ||
9633 | out_free: | |
d89cc617 | 9634 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
548ef284 | 9635 | kvfree(slot->arch.rmap[i]); |
d89cc617 TY |
9636 | slot->arch.rmap[i] = NULL; |
9637 | if (i == 0) | |
9638 | continue; | |
9639 | ||
548ef284 | 9640 | kvfree(slot->arch.lpage_info[i - 1]); |
d89cc617 | 9641 | slot->arch.lpage_info[i - 1] = NULL; |
db3fe4eb TY |
9642 | } |
9643 | return -ENOMEM; | |
9644 | } | |
9645 | ||
15248258 | 9646 | void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) |
e59dbe09 | 9647 | { |
e6dff7d1 TY |
9648 | /* |
9649 | * memslots->generation has been incremented. | |
9650 | * mmio generation may have reached its maximum value. | |
9651 | */ | |
15248258 | 9652 | kvm_mmu_invalidate_mmio_sptes(kvm, gen); |
e59dbe09 TY |
9653 | } |
9654 | ||
f7784b8e MT |
9655 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
9656 | struct kvm_memory_slot *memslot, | |
09170a49 | 9657 | const struct kvm_userspace_memory_region *mem, |
7b6195a9 | 9658 | enum kvm_mr_change change) |
0de10343 | 9659 | { |
f7784b8e MT |
9660 | return 0; |
9661 | } | |
9662 | ||
88178fd4 KH |
9663 | static void kvm_mmu_slot_apply_flags(struct kvm *kvm, |
9664 | struct kvm_memory_slot *new) | |
9665 | { | |
9666 | /* Still write protect RO slot */ | |
9667 | if (new->flags & KVM_MEM_READONLY) { | |
9668 | kvm_mmu_slot_remove_write_access(kvm, new); | |
9669 | return; | |
9670 | } | |
9671 | ||
9672 | /* | |
9673 | * Call kvm_x86_ops dirty logging hooks when they are valid. | |
9674 | * | |
9675 | * kvm_x86_ops->slot_disable_log_dirty is called when: | |
9676 | * | |
9677 | * - KVM_MR_CREATE with dirty logging is disabled | |
9678 | * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag | |
9679 | * | |
9680 | * The reason is, in case of PML, we need to set D-bit for any slots | |
9681 | * with dirty logging disabled in order to eliminate unnecessary GPA | |
9682 | * logging in PML buffer (and potential PML buffer full VMEXT). This | |
9683 | * guarantees leaving PML enabled during guest's lifetime won't have | |
bdd303cb | 9684 | * any additional overhead from PML when guest is running with dirty |
88178fd4 KH |
9685 | * logging disabled for memory slots. |
9686 | * | |
9687 | * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot | |
9688 | * to dirty logging mode. | |
9689 | * | |
9690 | * If kvm_x86_ops dirty logging hooks are invalid, use write protect. | |
9691 | * | |
9692 | * In case of write protect: | |
9693 | * | |
9694 | * Write protect all pages for dirty logging. | |
9695 | * | |
9696 | * All the sptes including the large sptes which point to this | |
9697 | * slot are set to readonly. We can not create any new large | |
9698 | * spte on this slot until the end of the logging. | |
9699 | * | |
9700 | * See the comments in fast_page_fault(). | |
9701 | */ | |
9702 | if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { | |
9703 | if (kvm_x86_ops->slot_enable_log_dirty) | |
9704 | kvm_x86_ops->slot_enable_log_dirty(kvm, new); | |
9705 | else | |
9706 | kvm_mmu_slot_remove_write_access(kvm, new); | |
9707 | } else { | |
9708 | if (kvm_x86_ops->slot_disable_log_dirty) | |
9709 | kvm_x86_ops->slot_disable_log_dirty(kvm, new); | |
9710 | } | |
9711 | } | |
9712 | ||
f7784b8e | 9713 | void kvm_arch_commit_memory_region(struct kvm *kvm, |
09170a49 | 9714 | const struct kvm_userspace_memory_region *mem, |
8482644a | 9715 | const struct kvm_memory_slot *old, |
f36f3f28 | 9716 | const struct kvm_memory_slot *new, |
8482644a | 9717 | enum kvm_mr_change change) |
f7784b8e | 9718 | { |
48c0e4e9 | 9719 | if (!kvm->arch.n_requested_mmu_pages) |
4d66623c WY |
9720 | kvm_mmu_change_mmu_pages(kvm, |
9721 | kvm_mmu_calculate_default_mmu_pages(kvm)); | |
1c91cad4 | 9722 | |
3ea3b7fa WL |
9723 | /* |
9724 | * Dirty logging tracks sptes in 4k granularity, meaning that large | |
9725 | * sptes have to be split. If live migration is successful, the guest | |
9726 | * in the source machine will be destroyed and large sptes will be | |
9727 | * created in the destination. However, if the guest continues to run | |
9728 | * in the source machine (for example if live migration fails), small | |
9729 | * sptes will remain around and cause bad performance. | |
9730 | * | |
9731 | * Scan sptes if dirty logging has been stopped, dropping those | |
9732 | * which can be collapsed into a single large-page spte. Later | |
9733 | * page faults will create the large-page sptes. | |
9734 | */ | |
9735 | if ((change != KVM_MR_DELETE) && | |
9736 | (old->flags & KVM_MEM_LOG_DIRTY_PAGES) && | |
9737 | !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) | |
9738 | kvm_mmu_zap_collapsible_sptes(kvm, new); | |
9739 | ||
c972f3b1 | 9740 | /* |
88178fd4 | 9741 | * Set up write protection and/or dirty logging for the new slot. |
c126d94f | 9742 | * |
88178fd4 KH |
9743 | * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have |
9744 | * been zapped so no dirty logging staff is needed for old slot. For | |
9745 | * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the | |
9746 | * new and it's also covered when dealing with the new slot. | |
f36f3f28 PB |
9747 | * |
9748 | * FIXME: const-ify all uses of struct kvm_memory_slot. | |
c972f3b1 | 9749 | */ |
88178fd4 | 9750 | if (change != KVM_MR_DELETE) |
f36f3f28 | 9751 | kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new); |
0de10343 | 9752 | } |
1d737c8a | 9753 | |
2df72e9b | 9754 | void kvm_arch_flush_shadow_all(struct kvm *kvm) |
34d4cb8f | 9755 | { |
7390de1e | 9756 | kvm_mmu_zap_all(kvm); |
34d4cb8f MT |
9757 | } |
9758 | ||
2df72e9b MT |
9759 | void kvm_arch_flush_shadow_memslot(struct kvm *kvm, |
9760 | struct kvm_memory_slot *slot) | |
9761 | { | |
ae7cd873 | 9762 | kvm_page_track_flush_slot(kvm, slot); |
2df72e9b MT |
9763 | } |
9764 | ||
e6c67d8c LA |
9765 | static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) |
9766 | { | |
9767 | return (is_guest_mode(vcpu) && | |
9768 | kvm_x86_ops->guest_apic_has_interrupt && | |
9769 | kvm_x86_ops->guest_apic_has_interrupt(vcpu)); | |
9770 | } | |
9771 | ||
5d9bc648 PB |
9772 | static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) |
9773 | { | |
9774 | if (!list_empty_careful(&vcpu->async_pf.done)) | |
9775 | return true; | |
9776 | ||
9777 | if (kvm_apic_has_events(vcpu)) | |
9778 | return true; | |
9779 | ||
9780 | if (vcpu->arch.pv.pv_unhalted) | |
9781 | return true; | |
9782 | ||
a5f01f8e WL |
9783 | if (vcpu->arch.exception.pending) |
9784 | return true; | |
9785 | ||
47a66eed Z |
9786 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || |
9787 | (vcpu->arch.nmi_pending && | |
9788 | kvm_x86_ops->nmi_allowed(vcpu))) | |
5d9bc648 PB |
9789 | return true; |
9790 | ||
47a66eed Z |
9791 | if (kvm_test_request(KVM_REQ_SMI, vcpu) || |
9792 | (vcpu->arch.smi_pending && !is_smm(vcpu))) | |
73917739 PB |
9793 | return true; |
9794 | ||
5d9bc648 | 9795 | if (kvm_arch_interrupt_allowed(vcpu) && |
e6c67d8c LA |
9796 | (kvm_cpu_has_interrupt(vcpu) || |
9797 | kvm_guest_apic_has_interrupt(vcpu))) | |
5d9bc648 PB |
9798 | return true; |
9799 | ||
1f4b34f8 AS |
9800 | if (kvm_hv_has_stimer_pending(vcpu)) |
9801 | return true; | |
9802 | ||
5d9bc648 PB |
9803 | return false; |
9804 | } | |
9805 | ||
1d737c8a ZX |
9806 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
9807 | { | |
5d9bc648 | 9808 | return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); |
1d737c8a | 9809 | } |
5736199a | 9810 | |
17e433b5 WL |
9811 | bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) |
9812 | { | |
9813 | if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) | |
9814 | return true; | |
9815 | ||
9816 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || | |
9817 | kvm_test_request(KVM_REQ_SMI, vcpu) || | |
9818 | kvm_test_request(KVM_REQ_EVENT, vcpu)) | |
9819 | return true; | |
9820 | ||
9821 | if (vcpu->arch.apicv_active && kvm_x86_ops->dy_apicv_has_pending_interrupt(vcpu)) | |
9822 | return true; | |
9823 | ||
9824 | return false; | |
9825 | } | |
9826 | ||
199b5763 LM |
9827 | bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) |
9828 | { | |
de63ad4c | 9829 | return vcpu->arch.preempted_in_kernel; |
199b5763 LM |
9830 | } |
9831 | ||
b6d33834 | 9832 | int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) |
5736199a | 9833 | { |
b6d33834 | 9834 | return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; |
5736199a | 9835 | } |
78646121 GN |
9836 | |
9837 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
9838 | { | |
9839 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
9840 | } | |
229456fc | 9841 | |
82b32774 | 9842 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) |
f92653ee | 9843 | { |
82b32774 NA |
9844 | if (is_64_bit_mode(vcpu)) |
9845 | return kvm_rip_read(vcpu); | |
9846 | return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + | |
9847 | kvm_rip_read(vcpu)); | |
9848 | } | |
9849 | EXPORT_SYMBOL_GPL(kvm_get_linear_rip); | |
f92653ee | 9850 | |
82b32774 NA |
9851 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) |
9852 | { | |
9853 | return kvm_get_linear_rip(vcpu) == linear_rip; | |
f92653ee JK |
9854 | } |
9855 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
9856 | ||
94fe45da JK |
9857 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
9858 | { | |
9859 | unsigned long rflags; | |
9860 | ||
9861 | rflags = kvm_x86_ops->get_rflags(vcpu); | |
9862 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
c310bac5 | 9863 | rflags &= ~X86_EFLAGS_TF; |
94fe45da JK |
9864 | return rflags; |
9865 | } | |
9866 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
9867 | ||
6addfc42 | 9868 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) |
94fe45da JK |
9869 | { |
9870 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
f92653ee | 9871 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) |
c310bac5 | 9872 | rflags |= X86_EFLAGS_TF; |
94fe45da | 9873 | kvm_x86_ops->set_rflags(vcpu, rflags); |
6addfc42 PB |
9874 | } |
9875 | ||
9876 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
9877 | { | |
9878 | __kvm_set_rflags(vcpu, rflags); | |
3842d135 | 9879 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
94fe45da JK |
9880 | } |
9881 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
9882 | ||
56028d08 GN |
9883 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) |
9884 | { | |
9885 | int r; | |
9886 | ||
44dd3ffa | 9887 | if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) || |
f2e10669 | 9888 | work->wakeup_all) |
56028d08 GN |
9889 | return; |
9890 | ||
9891 | r = kvm_mmu_reload(vcpu); | |
9892 | if (unlikely(r)) | |
9893 | return; | |
9894 | ||
44dd3ffa VK |
9895 | if (!vcpu->arch.mmu->direct_map && |
9896 | work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu)) | |
fb67e14f XG |
9897 | return; |
9898 | ||
44dd3ffa | 9899 | vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true); |
56028d08 GN |
9900 | } |
9901 | ||
af585b92 GN |
9902 | static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) |
9903 | { | |
9904 | return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); | |
9905 | } | |
9906 | ||
9907 | static inline u32 kvm_async_pf_next_probe(u32 key) | |
9908 | { | |
9909 | return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); | |
9910 | } | |
9911 | ||
9912 | static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
9913 | { | |
9914 | u32 key = kvm_async_pf_hash_fn(gfn); | |
9915 | ||
9916 | while (vcpu->arch.apf.gfns[key] != ~0) | |
9917 | key = kvm_async_pf_next_probe(key); | |
9918 | ||
9919 | vcpu->arch.apf.gfns[key] = gfn; | |
9920 | } | |
9921 | ||
9922 | static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) | |
9923 | { | |
9924 | int i; | |
9925 | u32 key = kvm_async_pf_hash_fn(gfn); | |
9926 | ||
9927 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && | |
c7d28c24 XG |
9928 | (vcpu->arch.apf.gfns[key] != gfn && |
9929 | vcpu->arch.apf.gfns[key] != ~0); i++) | |
af585b92 GN |
9930 | key = kvm_async_pf_next_probe(key); |
9931 | ||
9932 | return key; | |
9933 | } | |
9934 | ||
9935 | bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
9936 | { | |
9937 | return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; | |
9938 | } | |
9939 | ||
9940 | static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
9941 | { | |
9942 | u32 i, j, k; | |
9943 | ||
9944 | i = j = kvm_async_pf_gfn_slot(vcpu, gfn); | |
9945 | while (true) { | |
9946 | vcpu->arch.apf.gfns[i] = ~0; | |
9947 | do { | |
9948 | j = kvm_async_pf_next_probe(j); | |
9949 | if (vcpu->arch.apf.gfns[j] == ~0) | |
9950 | return; | |
9951 | k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); | |
9952 | /* | |
9953 | * k lies cyclically in ]i,j] | |
9954 | * | i.k.j | | |
9955 | * |....j i.k.| or |.k..j i...| | |
9956 | */ | |
9957 | } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); | |
9958 | vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; | |
9959 | i = j; | |
9960 | } | |
9961 | } | |
9962 | ||
7c90705b GN |
9963 | static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) |
9964 | { | |
4e335d9e PB |
9965 | |
9966 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, | |
9967 | sizeof(val)); | |
7c90705b GN |
9968 | } |
9969 | ||
9a6e7c39 WL |
9970 | static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val) |
9971 | { | |
9972 | ||
9973 | return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val, | |
9974 | sizeof(u32)); | |
9975 | } | |
9976 | ||
1dfdb45e PB |
9977 | static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) |
9978 | { | |
9979 | if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu)) | |
9980 | return false; | |
9981 | ||
9982 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || | |
9983 | (vcpu->arch.apf.send_user_only && | |
9984 | kvm_x86_ops->get_cpl(vcpu) == 0)) | |
9985 | return false; | |
9986 | ||
9987 | return true; | |
9988 | } | |
9989 | ||
9990 | bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) | |
9991 | { | |
9992 | if (unlikely(!lapic_in_kernel(vcpu) || | |
9993 | kvm_event_needs_reinjection(vcpu) || | |
9994 | vcpu->arch.exception.pending)) | |
9995 | return false; | |
9996 | ||
9997 | if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) | |
9998 | return false; | |
9999 | ||
10000 | /* | |
10001 | * If interrupts are off we cannot even use an artificial | |
10002 | * halt state. | |
10003 | */ | |
10004 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
10005 | } | |
10006 | ||
af585b92 GN |
10007 | void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
10008 | struct kvm_async_pf *work) | |
10009 | { | |
6389ee94 AK |
10010 | struct x86_exception fault; |
10011 | ||
7c90705b | 10012 | trace_kvm_async_pf_not_present(work->arch.token, work->gva); |
af585b92 | 10013 | kvm_add_async_pf_gfn(vcpu, work->arch.gfn); |
7c90705b | 10014 | |
1dfdb45e PB |
10015 | if (kvm_can_deliver_async_pf(vcpu) && |
10016 | !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { | |
6389ee94 AK |
10017 | fault.vector = PF_VECTOR; |
10018 | fault.error_code_valid = true; | |
10019 | fault.error_code = 0; | |
10020 | fault.nested_page_fault = false; | |
10021 | fault.address = work->arch.token; | |
adfe20fb | 10022 | fault.async_page_fault = true; |
6389ee94 | 10023 | kvm_inject_page_fault(vcpu, &fault); |
1dfdb45e PB |
10024 | } else { |
10025 | /* | |
10026 | * It is not possible to deliver a paravirtualized asynchronous | |
10027 | * page fault, but putting the guest in an artificial halt state | |
10028 | * can be beneficial nevertheless: if an interrupt arrives, we | |
10029 | * can deliver it timely and perhaps the guest will schedule | |
10030 | * another process. When the instruction that triggered a page | |
10031 | * fault is retried, hopefully the page will be ready in the host. | |
10032 | */ | |
10033 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
7c90705b | 10034 | } |
af585b92 GN |
10035 | } |
10036 | ||
10037 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
10038 | struct kvm_async_pf *work) | |
10039 | { | |
6389ee94 | 10040 | struct x86_exception fault; |
9a6e7c39 | 10041 | u32 val; |
6389ee94 | 10042 | |
f2e10669 | 10043 | if (work->wakeup_all) |
7c90705b GN |
10044 | work->arch.token = ~0; /* broadcast wakeup */ |
10045 | else | |
10046 | kvm_del_async_pf_gfn(vcpu, work->arch.gfn); | |
24dccf83 | 10047 | trace_kvm_async_pf_ready(work->arch.token, work->gva); |
7c90705b | 10048 | |
9a6e7c39 WL |
10049 | if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED && |
10050 | !apf_get_user(vcpu, &val)) { | |
10051 | if (val == KVM_PV_REASON_PAGE_NOT_PRESENT && | |
10052 | vcpu->arch.exception.pending && | |
10053 | vcpu->arch.exception.nr == PF_VECTOR && | |
10054 | !apf_put_user(vcpu, 0)) { | |
10055 | vcpu->arch.exception.injected = false; | |
10056 | vcpu->arch.exception.pending = false; | |
10057 | vcpu->arch.exception.nr = 0; | |
10058 | vcpu->arch.exception.has_error_code = false; | |
10059 | vcpu->arch.exception.error_code = 0; | |
c851436a JM |
10060 | vcpu->arch.exception.has_payload = false; |
10061 | vcpu->arch.exception.payload = 0; | |
9a6e7c39 WL |
10062 | } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { |
10063 | fault.vector = PF_VECTOR; | |
10064 | fault.error_code_valid = true; | |
10065 | fault.error_code = 0; | |
10066 | fault.nested_page_fault = false; | |
10067 | fault.address = work->arch.token; | |
10068 | fault.async_page_fault = true; | |
10069 | kvm_inject_page_fault(vcpu, &fault); | |
10070 | } | |
7c90705b | 10071 | } |
e6d53e3b | 10072 | vcpu->arch.apf.halted = false; |
a4fa1635 | 10073 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
7c90705b GN |
10074 | } |
10075 | ||
10076 | bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) | |
10077 | { | |
10078 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) | |
10079 | return true; | |
10080 | else | |
9bc1f09f | 10081 | return kvm_can_do_async_pf(vcpu); |
af585b92 GN |
10082 | } |
10083 | ||
5544eb9b PB |
10084 | void kvm_arch_start_assignment(struct kvm *kvm) |
10085 | { | |
10086 | atomic_inc(&kvm->arch.assigned_device_count); | |
10087 | } | |
10088 | EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); | |
10089 | ||
10090 | void kvm_arch_end_assignment(struct kvm *kvm) | |
10091 | { | |
10092 | atomic_dec(&kvm->arch.assigned_device_count); | |
10093 | } | |
10094 | EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); | |
10095 | ||
10096 | bool kvm_arch_has_assigned_device(struct kvm *kvm) | |
10097 | { | |
10098 | return atomic_read(&kvm->arch.assigned_device_count); | |
10099 | } | |
10100 | EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); | |
10101 | ||
e0f0bbc5 AW |
10102 | void kvm_arch_register_noncoherent_dma(struct kvm *kvm) |
10103 | { | |
10104 | atomic_inc(&kvm->arch.noncoherent_dma_count); | |
10105 | } | |
10106 | EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); | |
10107 | ||
10108 | void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) | |
10109 | { | |
10110 | atomic_dec(&kvm->arch.noncoherent_dma_count); | |
10111 | } | |
10112 | EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); | |
10113 | ||
10114 | bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) | |
10115 | { | |
10116 | return atomic_read(&kvm->arch.noncoherent_dma_count); | |
10117 | } | |
10118 | EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); | |
10119 | ||
14717e20 AW |
10120 | bool kvm_arch_has_irq_bypass(void) |
10121 | { | |
92735b1b | 10122 | return true; |
14717e20 AW |
10123 | } |
10124 | ||
87276880 FW |
10125 | int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, |
10126 | struct irq_bypass_producer *prod) | |
10127 | { | |
10128 | struct kvm_kernel_irqfd *irqfd = | |
10129 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
10130 | ||
14717e20 | 10131 | irqfd->producer = prod; |
87276880 | 10132 | |
14717e20 AW |
10133 | return kvm_x86_ops->update_pi_irte(irqfd->kvm, |
10134 | prod->irq, irqfd->gsi, 1); | |
87276880 FW |
10135 | } |
10136 | ||
10137 | void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, | |
10138 | struct irq_bypass_producer *prod) | |
10139 | { | |
10140 | int ret; | |
10141 | struct kvm_kernel_irqfd *irqfd = | |
10142 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
10143 | ||
87276880 FW |
10144 | WARN_ON(irqfd->producer != prod); |
10145 | irqfd->producer = NULL; | |
10146 | ||
10147 | /* | |
10148 | * When producer of consumer is unregistered, we change back to | |
10149 | * remapped mode, so we can re-use the current implementation | |
bb3541f1 | 10150 | * when the irq is masked/disabled or the consumer side (KVM |
87276880 FW |
10151 | * int this case doesn't want to receive the interrupts. |
10152 | */ | |
10153 | ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0); | |
10154 | if (ret) | |
10155 | printk(KERN_INFO "irq bypass consumer (token %p) unregistration" | |
10156 | " fails: %d\n", irqfd->consumer.token, ret); | |
10157 | } | |
10158 | ||
10159 | int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, | |
10160 | uint32_t guest_irq, bool set) | |
10161 | { | |
87276880 FW |
10162 | return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set); |
10163 | } | |
10164 | ||
52004014 FW |
10165 | bool kvm_vector_hashing_enabled(void) |
10166 | { | |
10167 | return vector_hashing; | |
10168 | } | |
10169 | EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled); | |
10170 | ||
2d5ba19b MT |
10171 | bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) |
10172 | { | |
10173 | return (vcpu->arch.msr_kvm_poll_control & 1) == 0; | |
10174 | } | |
10175 | EXPORT_SYMBOL_GPL(kvm_arch_no_poll); | |
10176 | ||
10177 | ||
229456fc | 10178 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
931c33b1 | 10179 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); |
229456fc MT |
10180 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); |
10181 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
10182 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
10183 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
0ac406de | 10184 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); |
d8cabddf | 10185 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 10186 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 10187 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
5497b955 | 10188 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); |
ec1ff790 | 10189 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 10190 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |
2e554e8d | 10191 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); |
489223ed | 10192 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); |
4f75bcc3 | 10193 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); |
843e4330 | 10194 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); |
efc64404 | 10195 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); |
18f40c53 SS |
10196 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); |
10197 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); |