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Commit | Line | Data |
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043405e1 CO |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * derived from drivers/kvm/kvm_main.c | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
7 | * Copyright (C) 2008 Qumranet, Inc. |
8 | * Copyright IBM Corporation, 2008 | |
9611c187 | 9 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
043405e1 CO |
10 | * |
11 | * Authors: | |
12 | * Avi Kivity <avi@qumranet.com> | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
14 | * Amit Shah <amit.shah@qumranet.com> |
15 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
16 | * |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | * | |
20 | */ | |
21 | ||
edf88417 | 22 | #include <linux/kvm_host.h> |
313a3dc7 | 23 | #include "irq.h" |
1d737c8a | 24 | #include "mmu.h" |
7837699f | 25 | #include "i8254.h" |
37817f29 | 26 | #include "tss.h" |
5fdbf976 | 27 | #include "kvm_cache_regs.h" |
26eef70c | 28 | #include "x86.h" |
00b27a3e | 29 | #include "cpuid.h" |
474a5bb9 | 30 | #include "pmu.h" |
e83d5887 | 31 | #include "hyperv.h" |
313a3dc7 | 32 | |
18068523 | 33 | #include <linux/clocksource.h> |
4d5c5d0f | 34 | #include <linux/interrupt.h> |
313a3dc7 CO |
35 | #include <linux/kvm.h> |
36 | #include <linux/fs.h> | |
37 | #include <linux/vmalloc.h> | |
1767e931 PG |
38 | #include <linux/export.h> |
39 | #include <linux/moduleparam.h> | |
0de10343 | 40 | #include <linux/mman.h> |
2bacc55c | 41 | #include <linux/highmem.h> |
19de40a8 | 42 | #include <linux/iommu.h> |
62c476c7 | 43 | #include <linux/intel-iommu.h> |
c8076604 | 44 | #include <linux/cpufreq.h> |
18863bdd | 45 | #include <linux/user-return-notifier.h> |
a983fb23 | 46 | #include <linux/srcu.h> |
5a0e3ad6 | 47 | #include <linux/slab.h> |
ff9d07a0 | 48 | #include <linux/perf_event.h> |
7bee342a | 49 | #include <linux/uaccess.h> |
af585b92 | 50 | #include <linux/hash.h> |
a1b60c1c | 51 | #include <linux/pci.h> |
16e8d74d MT |
52 | #include <linux/timekeeper_internal.h> |
53 | #include <linux/pvclock_gtod.h> | |
87276880 FW |
54 | #include <linux/kvm_irqfd.h> |
55 | #include <linux/irqbypass.h> | |
3905f9ad | 56 | #include <linux/sched/stat.h> |
d0ec49d4 | 57 | #include <linux/mem_encrypt.h> |
3905f9ad | 58 | |
aec51dc4 | 59 | #include <trace/events/kvm.h> |
2ed152af | 60 | |
24f1e32c | 61 | #include <asm/debugreg.h> |
d825ed0a | 62 | #include <asm/msr.h> |
a5f61300 | 63 | #include <asm/desc.h> |
890ca9ae | 64 | #include <asm/mce.h> |
f89e32e0 | 65 | #include <linux/kernel_stat.h> |
78f7f1e5 | 66 | #include <asm/fpu/internal.h> /* Ugh! */ |
1d5f066e | 67 | #include <asm/pvclock.h> |
217fc9cf | 68 | #include <asm/div64.h> |
efc64404 | 69 | #include <asm/irq_remapping.h> |
b0c39dc6 | 70 | #include <asm/mshyperv.h> |
0092e434 | 71 | #include <asm/hypervisor.h> |
043405e1 | 72 | |
d1898b73 DH |
73 | #define CREATE_TRACE_POINTS |
74 | #include "trace.h" | |
75 | ||
313a3dc7 | 76 | #define MAX_IO_MSRS 256 |
890ca9ae | 77 | #define KVM_MAX_MCE_BANKS 32 |
c45dcc71 AR |
78 | u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; |
79 | EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); | |
890ca9ae | 80 | |
0f65dd70 AK |
81 | #define emul_to_vcpu(ctxt) \ |
82 | container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) | |
83 | ||
50a37eb4 JR |
84 | /* EFER defaults: |
85 | * - enable syscall per default because its emulated by KVM | |
86 | * - enable LME and LMA per default on 64 bit KVM | |
87 | */ | |
88 | #ifdef CONFIG_X86_64 | |
1260edbe LJ |
89 | static |
90 | u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); | |
50a37eb4 | 91 | #else |
1260edbe | 92 | static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); |
50a37eb4 | 93 | #endif |
313a3dc7 | 94 | |
ba1389b7 AK |
95 | #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM |
96 | #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU | |
417bc304 | 97 | |
c519265f RK |
98 | #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ |
99 | KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) | |
37131313 | 100 | |
cb142eb7 | 101 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
7460fb4a | 102 | static void process_nmi(struct kvm_vcpu *vcpu); |
ee2cd4b7 | 103 | static void enter_smm(struct kvm_vcpu *vcpu); |
6addfc42 | 104 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); |
01643c51 KH |
105 | static void store_regs(struct kvm_vcpu *vcpu); |
106 | static int sync_regs(struct kvm_vcpu *vcpu); | |
674eea0f | 107 | |
893590c7 | 108 | struct kvm_x86_ops *kvm_x86_ops __read_mostly; |
5fdbf976 | 109 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 110 | |
893590c7 | 111 | static bool __read_mostly ignore_msrs = 0; |
476bc001 | 112 | module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); |
ed85c068 | 113 | |
fab0aa3b EM |
114 | static bool __read_mostly report_ignored_msrs = true; |
115 | module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); | |
116 | ||
9ed96e87 MT |
117 | unsigned int min_timer_period_us = 500; |
118 | module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); | |
119 | ||
630994b3 MT |
120 | static bool __read_mostly kvmclock_periodic_sync = true; |
121 | module_param(kvmclock_periodic_sync, bool, S_IRUGO); | |
122 | ||
893590c7 | 123 | bool __read_mostly kvm_has_tsc_control; |
92a1f12d | 124 | EXPORT_SYMBOL_GPL(kvm_has_tsc_control); |
893590c7 | 125 | u32 __read_mostly kvm_max_guest_tsc_khz; |
92a1f12d | 126 | EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); |
bc9b961b HZ |
127 | u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; |
128 | EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); | |
129 | u64 __read_mostly kvm_max_tsc_scaling_ratio; | |
130 | EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); | |
64672c95 YJ |
131 | u64 __read_mostly kvm_default_tsc_scaling_ratio; |
132 | EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); | |
92a1f12d | 133 | |
cc578287 | 134 | /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ |
893590c7 | 135 | static u32 __read_mostly tsc_tolerance_ppm = 250; |
cc578287 ZA |
136 | module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); |
137 | ||
d0659d94 | 138 | /* lapic timer advance (tscdeadline mode only) in nanoseconds */ |
893590c7 | 139 | unsigned int __read_mostly lapic_timer_advance_ns = 0; |
d0659d94 MT |
140 | module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR); |
141 | ||
52004014 FW |
142 | static bool __read_mostly vector_hashing = true; |
143 | module_param(vector_hashing, bool, S_IRUGO); | |
144 | ||
c4ae60e4 LA |
145 | bool __read_mostly enable_vmware_backdoor = false; |
146 | module_param(enable_vmware_backdoor, bool, S_IRUGO); | |
147 | EXPORT_SYMBOL_GPL(enable_vmware_backdoor); | |
148 | ||
18863bdd AK |
149 | #define KVM_NR_SHARED_MSRS 16 |
150 | ||
151 | struct kvm_shared_msrs_global { | |
152 | int nr; | |
2bf78fa7 | 153 | u32 msrs[KVM_NR_SHARED_MSRS]; |
18863bdd AK |
154 | }; |
155 | ||
156 | struct kvm_shared_msrs { | |
157 | struct user_return_notifier urn; | |
158 | bool registered; | |
2bf78fa7 SY |
159 | struct kvm_shared_msr_values { |
160 | u64 host; | |
161 | u64 curr; | |
162 | } values[KVM_NR_SHARED_MSRS]; | |
18863bdd AK |
163 | }; |
164 | ||
165 | static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; | |
013f6a5d | 166 | static struct kvm_shared_msrs __percpu *shared_msrs; |
18863bdd | 167 | |
417bc304 | 168 | struct kvm_stats_debugfs_item debugfs_entries[] = { |
ba1389b7 AK |
169 | { "pf_fixed", VCPU_STAT(pf_fixed) }, |
170 | { "pf_guest", VCPU_STAT(pf_guest) }, | |
171 | { "tlb_flush", VCPU_STAT(tlb_flush) }, | |
172 | { "invlpg", VCPU_STAT(invlpg) }, | |
173 | { "exits", VCPU_STAT(exits) }, | |
174 | { "io_exits", VCPU_STAT(io_exits) }, | |
175 | { "mmio_exits", VCPU_STAT(mmio_exits) }, | |
176 | { "signal_exits", VCPU_STAT(signal_exits) }, | |
177 | { "irq_window", VCPU_STAT(irq_window_exits) }, | |
f08864b4 | 178 | { "nmi_window", VCPU_STAT(nmi_window_exits) }, |
ba1389b7 | 179 | { "halt_exits", VCPU_STAT(halt_exits) }, |
f7819512 | 180 | { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, |
62bea5bf | 181 | { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) }, |
3491caf2 | 182 | { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) }, |
ba1389b7 | 183 | { "halt_wakeup", VCPU_STAT(halt_wakeup) }, |
f11c3a8d | 184 | { "hypercalls", VCPU_STAT(hypercalls) }, |
ba1389b7 AK |
185 | { "request_irq", VCPU_STAT(request_irq_exits) }, |
186 | { "irq_exits", VCPU_STAT(irq_exits) }, | |
187 | { "host_state_reload", VCPU_STAT(host_state_reload) }, | |
ba1389b7 AK |
188 | { "fpu_reload", VCPU_STAT(fpu_reload) }, |
189 | { "insn_emulation", VCPU_STAT(insn_emulation) }, | |
190 | { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, | |
fa89a817 | 191 | { "irq_injections", VCPU_STAT(irq_injections) }, |
c4abb7c9 | 192 | { "nmi_injections", VCPU_STAT(nmi_injections) }, |
0f1e261e | 193 | { "req_event", VCPU_STAT(req_event) }, |
4cee5764 AK |
194 | { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, |
195 | { "mmu_pte_write", VM_STAT(mmu_pte_write) }, | |
196 | { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, | |
197 | { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, | |
198 | { "mmu_flooded", VM_STAT(mmu_flooded) }, | |
199 | { "mmu_recycled", VM_STAT(mmu_recycled) }, | |
dfc5aa00 | 200 | { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, |
4731d4c7 | 201 | { "mmu_unsync", VM_STAT(mmu_unsync) }, |
0f74a24c | 202 | { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, |
05da4558 | 203 | { "largepages", VM_STAT(lpages) }, |
f3414bc7 DM |
204 | { "max_mmu_page_hash_collisions", |
205 | VM_STAT(max_mmu_page_hash_collisions) }, | |
417bc304 HB |
206 | { NULL } |
207 | }; | |
208 | ||
2acf923e DC |
209 | u64 __read_mostly host_xcr0; |
210 | ||
b6785def | 211 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); |
d6aa1000 | 212 | |
af585b92 GN |
213 | static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) |
214 | { | |
215 | int i; | |
216 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) | |
217 | vcpu->arch.apf.gfns[i] = ~0; | |
218 | } | |
219 | ||
18863bdd AK |
220 | static void kvm_on_user_return(struct user_return_notifier *urn) |
221 | { | |
222 | unsigned slot; | |
18863bdd AK |
223 | struct kvm_shared_msrs *locals |
224 | = container_of(urn, struct kvm_shared_msrs, urn); | |
2bf78fa7 | 225 | struct kvm_shared_msr_values *values; |
1650b4eb IA |
226 | unsigned long flags; |
227 | ||
228 | /* | |
229 | * Disabling irqs at this point since the following code could be | |
230 | * interrupted and executed through kvm_arch_hardware_disable() | |
231 | */ | |
232 | local_irq_save(flags); | |
233 | if (locals->registered) { | |
234 | locals->registered = false; | |
235 | user_return_notifier_unregister(urn); | |
236 | } | |
237 | local_irq_restore(flags); | |
18863bdd | 238 | for (slot = 0; slot < shared_msrs_global.nr; ++slot) { |
2bf78fa7 SY |
239 | values = &locals->values[slot]; |
240 | if (values->host != values->curr) { | |
241 | wrmsrl(shared_msrs_global.msrs[slot], values->host); | |
242 | values->curr = values->host; | |
18863bdd AK |
243 | } |
244 | } | |
18863bdd AK |
245 | } |
246 | ||
2bf78fa7 | 247 | static void shared_msr_update(unsigned slot, u32 msr) |
18863bdd | 248 | { |
18863bdd | 249 | u64 value; |
013f6a5d MT |
250 | unsigned int cpu = smp_processor_id(); |
251 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
18863bdd | 252 | |
2bf78fa7 SY |
253 | /* only read, and nobody should modify it at this time, |
254 | * so don't need lock */ | |
255 | if (slot >= shared_msrs_global.nr) { | |
256 | printk(KERN_ERR "kvm: invalid MSR slot!"); | |
257 | return; | |
258 | } | |
259 | rdmsrl_safe(msr, &value); | |
260 | smsr->values[slot].host = value; | |
261 | smsr->values[slot].curr = value; | |
262 | } | |
263 | ||
264 | void kvm_define_shared_msr(unsigned slot, u32 msr) | |
265 | { | |
0123be42 | 266 | BUG_ON(slot >= KVM_NR_SHARED_MSRS); |
c847fe88 | 267 | shared_msrs_global.msrs[slot] = msr; |
18863bdd AK |
268 | if (slot >= shared_msrs_global.nr) |
269 | shared_msrs_global.nr = slot + 1; | |
18863bdd AK |
270 | } |
271 | EXPORT_SYMBOL_GPL(kvm_define_shared_msr); | |
272 | ||
273 | static void kvm_shared_msr_cpu_online(void) | |
274 | { | |
275 | unsigned i; | |
18863bdd AK |
276 | |
277 | for (i = 0; i < shared_msrs_global.nr; ++i) | |
2bf78fa7 | 278 | shared_msr_update(i, shared_msrs_global.msrs[i]); |
18863bdd AK |
279 | } |
280 | ||
8b3c3104 | 281 | int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) |
18863bdd | 282 | { |
013f6a5d MT |
283 | unsigned int cpu = smp_processor_id(); |
284 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
8b3c3104 | 285 | int err; |
18863bdd | 286 | |
2bf78fa7 | 287 | if (((value ^ smsr->values[slot].curr) & mask) == 0) |
8b3c3104 | 288 | return 0; |
2bf78fa7 | 289 | smsr->values[slot].curr = value; |
8b3c3104 AH |
290 | err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); |
291 | if (err) | |
292 | return 1; | |
293 | ||
18863bdd AK |
294 | if (!smsr->registered) { |
295 | smsr->urn.on_user_return = kvm_on_user_return; | |
296 | user_return_notifier_register(&smsr->urn); | |
297 | smsr->registered = true; | |
298 | } | |
8b3c3104 | 299 | return 0; |
18863bdd AK |
300 | } |
301 | EXPORT_SYMBOL_GPL(kvm_set_shared_msr); | |
302 | ||
13a34e06 | 303 | static void drop_user_return_notifiers(void) |
3548bab5 | 304 | { |
013f6a5d MT |
305 | unsigned int cpu = smp_processor_id(); |
306 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
3548bab5 AK |
307 | |
308 | if (smsr->registered) | |
309 | kvm_on_user_return(&smsr->urn); | |
310 | } | |
311 | ||
6866b83e CO |
312 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
313 | { | |
8a5a87d9 | 314 | return vcpu->arch.apic_base; |
6866b83e CO |
315 | } |
316 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
317 | ||
58cb628d JK |
318 | int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
319 | { | |
320 | u64 old_state = vcpu->arch.apic_base & | |
321 | (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); | |
322 | u64 new_state = msr_info->data & | |
323 | (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); | |
d6321d49 RK |
324 | u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff | |
325 | (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); | |
58cb628d | 326 | |
d3802286 JM |
327 | if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE) |
328 | return 1; | |
58cb628d | 329 | if (!msr_info->host_initiated && |
d3802286 | 330 | ((new_state == MSR_IA32_APICBASE_ENABLE && |
58cb628d JK |
331 | old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) || |
332 | (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) && | |
333 | old_state == 0))) | |
334 | return 1; | |
335 | ||
336 | kvm_lapic_set_base(vcpu, msr_info->data); | |
337 | return 0; | |
6866b83e CO |
338 | } |
339 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
340 | ||
2605fc21 | 341 | asmlinkage __visible void kvm_spurious_fault(void) |
e3ba45b8 GL |
342 | { |
343 | /* Fault while not rebooting. We want the trace. */ | |
344 | BUG(); | |
345 | } | |
346 | EXPORT_SYMBOL_GPL(kvm_spurious_fault); | |
347 | ||
3fd28fce ED |
348 | #define EXCPT_BENIGN 0 |
349 | #define EXCPT_CONTRIBUTORY 1 | |
350 | #define EXCPT_PF 2 | |
351 | ||
352 | static int exception_class(int vector) | |
353 | { | |
354 | switch (vector) { | |
355 | case PF_VECTOR: | |
356 | return EXCPT_PF; | |
357 | case DE_VECTOR: | |
358 | case TS_VECTOR: | |
359 | case NP_VECTOR: | |
360 | case SS_VECTOR: | |
361 | case GP_VECTOR: | |
362 | return EXCPT_CONTRIBUTORY; | |
363 | default: | |
364 | break; | |
365 | } | |
366 | return EXCPT_BENIGN; | |
367 | } | |
368 | ||
d6e8c854 NA |
369 | #define EXCPT_FAULT 0 |
370 | #define EXCPT_TRAP 1 | |
371 | #define EXCPT_ABORT 2 | |
372 | #define EXCPT_INTERRUPT 3 | |
373 | ||
374 | static int exception_type(int vector) | |
375 | { | |
376 | unsigned int mask; | |
377 | ||
378 | if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) | |
379 | return EXCPT_INTERRUPT; | |
380 | ||
381 | mask = 1 << vector; | |
382 | ||
383 | /* #DB is trap, as instruction watchpoints are handled elsewhere */ | |
384 | if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) | |
385 | return EXCPT_TRAP; | |
386 | ||
387 | if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) | |
388 | return EXCPT_ABORT; | |
389 | ||
390 | /* Reserved exceptions will result in fault */ | |
391 | return EXCPT_FAULT; | |
392 | } | |
393 | ||
3fd28fce | 394 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, |
ce7ddec4 JR |
395 | unsigned nr, bool has_error, u32 error_code, |
396 | bool reinject) | |
3fd28fce ED |
397 | { |
398 | u32 prev_nr; | |
399 | int class1, class2; | |
400 | ||
3842d135 AK |
401 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
402 | ||
664f8e26 | 403 | if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { |
3fd28fce | 404 | queue: |
3ffb2468 NA |
405 | if (has_error && !is_protmode(vcpu)) |
406 | has_error = false; | |
664f8e26 WL |
407 | if (reinject) { |
408 | /* | |
409 | * On vmentry, vcpu->arch.exception.pending is only | |
410 | * true if an event injection was blocked by | |
411 | * nested_run_pending. In that case, however, | |
412 | * vcpu_enter_guest requests an immediate exit, | |
413 | * and the guest shouldn't proceed far enough to | |
414 | * need reinjection. | |
415 | */ | |
416 | WARN_ON_ONCE(vcpu->arch.exception.pending); | |
417 | vcpu->arch.exception.injected = true; | |
418 | } else { | |
419 | vcpu->arch.exception.pending = true; | |
420 | vcpu->arch.exception.injected = false; | |
421 | } | |
3fd28fce ED |
422 | vcpu->arch.exception.has_error_code = has_error; |
423 | vcpu->arch.exception.nr = nr; | |
424 | vcpu->arch.exception.error_code = error_code; | |
425 | return; | |
426 | } | |
427 | ||
428 | /* to check exception */ | |
429 | prev_nr = vcpu->arch.exception.nr; | |
430 | if (prev_nr == DF_VECTOR) { | |
431 | /* triple fault -> shutdown */ | |
a8eeb04a | 432 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
3fd28fce ED |
433 | return; |
434 | } | |
435 | class1 = exception_class(prev_nr); | |
436 | class2 = exception_class(nr); | |
437 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) | |
438 | || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
664f8e26 WL |
439 | /* |
440 | * Generate double fault per SDM Table 5-5. Set | |
441 | * exception.pending = true so that the double fault | |
442 | * can trigger a nested vmexit. | |
443 | */ | |
3fd28fce | 444 | vcpu->arch.exception.pending = true; |
664f8e26 | 445 | vcpu->arch.exception.injected = false; |
3fd28fce ED |
446 | vcpu->arch.exception.has_error_code = true; |
447 | vcpu->arch.exception.nr = DF_VECTOR; | |
448 | vcpu->arch.exception.error_code = 0; | |
449 | } else | |
450 | /* replace previous exception with a new one in a hope | |
451 | that instruction re-execution will regenerate lost | |
452 | exception */ | |
453 | goto queue; | |
454 | } | |
455 | ||
298101da AK |
456 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
457 | { | |
ce7ddec4 | 458 | kvm_multiple_exception(vcpu, nr, false, 0, false); |
298101da AK |
459 | } |
460 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
461 | ||
ce7ddec4 JR |
462 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
463 | { | |
464 | kvm_multiple_exception(vcpu, nr, false, 0, true); | |
465 | } | |
466 | EXPORT_SYMBOL_GPL(kvm_requeue_exception); | |
467 | ||
6affcbed | 468 | int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) |
c3c91fee | 469 | { |
db8fcefa AP |
470 | if (err) |
471 | kvm_inject_gp(vcpu, 0); | |
472 | else | |
6affcbed KH |
473 | return kvm_skip_emulated_instruction(vcpu); |
474 | ||
475 | return 1; | |
db8fcefa AP |
476 | } |
477 | EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); | |
8df25a32 | 478 | |
6389ee94 | 479 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
c3c91fee AK |
480 | { |
481 | ++vcpu->stat.pf_guest; | |
adfe20fb WL |
482 | vcpu->arch.exception.nested_apf = |
483 | is_guest_mode(vcpu) && fault->async_page_fault; | |
484 | if (vcpu->arch.exception.nested_apf) | |
485 | vcpu->arch.apf.nested_apf_token = fault->address; | |
486 | else | |
487 | vcpu->arch.cr2 = fault->address; | |
6389ee94 | 488 | kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); |
c3c91fee | 489 | } |
27d6c865 | 490 | EXPORT_SYMBOL_GPL(kvm_inject_page_fault); |
c3c91fee | 491 | |
ef54bcfe | 492 | static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
d4f8cf66 | 493 | { |
6389ee94 AK |
494 | if (mmu_is_nested(vcpu) && !fault->nested_page_fault) |
495 | vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); | |
d4f8cf66 | 496 | else |
6389ee94 | 497 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
ef54bcfe PB |
498 | |
499 | return fault->nested_page_fault; | |
d4f8cf66 JR |
500 | } |
501 | ||
3419ffc8 SY |
502 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
503 | { | |
7460fb4a AK |
504 | atomic_inc(&vcpu->arch.nmi_queued); |
505 | kvm_make_request(KVM_REQ_NMI, vcpu); | |
3419ffc8 SY |
506 | } |
507 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
508 | ||
298101da AK |
509 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
510 | { | |
ce7ddec4 | 511 | kvm_multiple_exception(vcpu, nr, true, error_code, false); |
298101da AK |
512 | } |
513 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
514 | ||
ce7ddec4 JR |
515 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
516 | { | |
517 | kvm_multiple_exception(vcpu, nr, true, error_code, true); | |
518 | } | |
519 | EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); | |
520 | ||
0a79b009 AK |
521 | /* |
522 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
523 | * a #GP and return false. | |
524 | */ | |
525 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 526 | { |
0a79b009 AK |
527 | if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) |
528 | return true; | |
529 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
530 | return false; | |
298101da | 531 | } |
0a79b009 | 532 | EXPORT_SYMBOL_GPL(kvm_require_cpl); |
298101da | 533 | |
16f8a6f9 NA |
534 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) |
535 | { | |
536 | if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
537 | return true; | |
538 | ||
539 | kvm_queue_exception(vcpu, UD_VECTOR); | |
540 | return false; | |
541 | } | |
542 | EXPORT_SYMBOL_GPL(kvm_require_dr); | |
543 | ||
ec92fe44 JR |
544 | /* |
545 | * This function will be used to read from the physical memory of the currently | |
54bf36aa | 546 | * running guest. The difference to kvm_vcpu_read_guest_page is that this function |
ec92fe44 JR |
547 | * can read from guest physical or from the guest's guest physical memory. |
548 | */ | |
549 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
550 | gfn_t ngfn, void *data, int offset, int len, | |
551 | u32 access) | |
552 | { | |
54987b7a | 553 | struct x86_exception exception; |
ec92fe44 JR |
554 | gfn_t real_gfn; |
555 | gpa_t ngpa; | |
556 | ||
557 | ngpa = gfn_to_gpa(ngfn); | |
54987b7a | 558 | real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); |
ec92fe44 JR |
559 | if (real_gfn == UNMAPPED_GVA) |
560 | return -EFAULT; | |
561 | ||
562 | real_gfn = gpa_to_gfn(real_gfn); | |
563 | ||
54bf36aa | 564 | return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); |
ec92fe44 JR |
565 | } |
566 | EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); | |
567 | ||
69b0049a | 568 | static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, |
3d06b8bf JR |
569 | void *data, int offset, int len, u32 access) |
570 | { | |
571 | return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, | |
572 | data, offset, len, access); | |
573 | } | |
574 | ||
a03490ed CO |
575 | /* |
576 | * Load the pae pdptrs. Return true is they are all valid. | |
577 | */ | |
ff03a073 | 578 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) |
a03490ed CO |
579 | { |
580 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
581 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
582 | int i; | |
583 | int ret; | |
ff03a073 | 584 | u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; |
a03490ed | 585 | |
ff03a073 JR |
586 | ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, |
587 | offset * sizeof(u64), sizeof(pdpte), | |
588 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
a03490ed CO |
589 | if (ret < 0) { |
590 | ret = 0; | |
591 | goto out; | |
592 | } | |
593 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
812f30b2 | 594 | if ((pdpte[i] & PT_PRESENT_MASK) && |
a0a64f50 XG |
595 | (pdpte[i] & |
596 | vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) { | |
a03490ed CO |
597 | ret = 0; |
598 | goto out; | |
599 | } | |
600 | } | |
601 | ret = 1; | |
602 | ||
ff03a073 | 603 | memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); |
6de4f3ad AK |
604 | __set_bit(VCPU_EXREG_PDPTR, |
605 | (unsigned long *)&vcpu->arch.regs_avail); | |
606 | __set_bit(VCPU_EXREG_PDPTR, | |
607 | (unsigned long *)&vcpu->arch.regs_dirty); | |
a03490ed | 608 | out: |
a03490ed CO |
609 | |
610 | return ret; | |
611 | } | |
cc4b6871 | 612 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 613 | |
9ed38ffa | 614 | bool pdptrs_changed(struct kvm_vcpu *vcpu) |
d835dfec | 615 | { |
ff03a073 | 616 | u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; |
d835dfec | 617 | bool changed = true; |
3d06b8bf JR |
618 | int offset; |
619 | gfn_t gfn; | |
d835dfec AK |
620 | int r; |
621 | ||
622 | if (is_long_mode(vcpu) || !is_pae(vcpu)) | |
623 | return false; | |
624 | ||
6de4f3ad AK |
625 | if (!test_bit(VCPU_EXREG_PDPTR, |
626 | (unsigned long *)&vcpu->arch.regs_avail)) | |
627 | return true; | |
628 | ||
a512177e PB |
629 | gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT; |
630 | offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1); | |
3d06b8bf JR |
631 | r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), |
632 | PFERR_USER_MASK | PFERR_WRITE_MASK); | |
d835dfec AK |
633 | if (r < 0) |
634 | goto out; | |
ff03a073 | 635 | changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; |
d835dfec | 636 | out: |
d835dfec AK |
637 | |
638 | return changed; | |
639 | } | |
9ed38ffa | 640 | EXPORT_SYMBOL_GPL(pdptrs_changed); |
d835dfec | 641 | |
49a9b07e | 642 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 643 | { |
aad82703 | 644 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
d81135a5 | 645 | unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; |
aad82703 | 646 | |
f9a48e6a AK |
647 | cr0 |= X86_CR0_ET; |
648 | ||
ab344828 | 649 | #ifdef CONFIG_X86_64 |
0f12244f GN |
650 | if (cr0 & 0xffffffff00000000UL) |
651 | return 1; | |
ab344828 GN |
652 | #endif |
653 | ||
654 | cr0 &= ~CR0_RESERVED_BITS; | |
a03490ed | 655 | |
0f12244f GN |
656 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) |
657 | return 1; | |
a03490ed | 658 | |
0f12244f GN |
659 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) |
660 | return 1; | |
a03490ed CO |
661 | |
662 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { | |
663 | #ifdef CONFIG_X86_64 | |
f6801dff | 664 | if ((vcpu->arch.efer & EFER_LME)) { |
a03490ed CO |
665 | int cs_db, cs_l; |
666 | ||
0f12244f GN |
667 | if (!is_pae(vcpu)) |
668 | return 1; | |
a03490ed | 669 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
0f12244f GN |
670 | if (cs_l) |
671 | return 1; | |
a03490ed CO |
672 | } else |
673 | #endif | |
ff03a073 | 674 | if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
9f8fe504 | 675 | kvm_read_cr3(vcpu))) |
0f12244f | 676 | return 1; |
a03490ed CO |
677 | } |
678 | ||
ad756a16 MJ |
679 | if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) |
680 | return 1; | |
681 | ||
a03490ed | 682 | kvm_x86_ops->set_cr0(vcpu, cr0); |
a03490ed | 683 | |
d170c419 | 684 | if ((cr0 ^ old_cr0) & X86_CR0_PG) { |
e5f3f027 | 685 | kvm_clear_async_pf_completion_queue(vcpu); |
d170c419 LJ |
686 | kvm_async_pf_hash_reset(vcpu); |
687 | } | |
e5f3f027 | 688 | |
aad82703 SY |
689 | if ((cr0 ^ old_cr0) & update_bits) |
690 | kvm_mmu_reset_context(vcpu); | |
b18d5431 | 691 | |
879ae188 LE |
692 | if (((cr0 ^ old_cr0) & X86_CR0_CD) && |
693 | kvm_arch_has_noncoherent_dma(vcpu->kvm) && | |
694 | !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) | |
b18d5431 XG |
695 | kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); |
696 | ||
0f12244f GN |
697 | return 0; |
698 | } | |
2d3ad1f4 | 699 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 700 | |
2d3ad1f4 | 701 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 702 | { |
49a9b07e | 703 | (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); |
a03490ed | 704 | } |
2d3ad1f4 | 705 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 706 | |
42bdf991 MT |
707 | static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) |
708 | { | |
709 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && | |
710 | !vcpu->guest_xcr0_loaded) { | |
711 | /* kvm_set_xcr() also depends on this */ | |
476b7ada PB |
712 | if (vcpu->arch.xcr0 != host_xcr0) |
713 | xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); | |
42bdf991 MT |
714 | vcpu->guest_xcr0_loaded = 1; |
715 | } | |
716 | } | |
717 | ||
718 | static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) | |
719 | { | |
720 | if (vcpu->guest_xcr0_loaded) { | |
721 | if (vcpu->arch.xcr0 != host_xcr0) | |
722 | xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); | |
723 | vcpu->guest_xcr0_loaded = 0; | |
724 | } | |
725 | } | |
726 | ||
69b0049a | 727 | static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) |
2acf923e | 728 | { |
56c103ec LJ |
729 | u64 xcr0 = xcr; |
730 | u64 old_xcr0 = vcpu->arch.xcr0; | |
46c34cb0 | 731 | u64 valid_bits; |
2acf923e DC |
732 | |
733 | /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ | |
734 | if (index != XCR_XFEATURE_ENABLED_MASK) | |
735 | return 1; | |
d91cab78 | 736 | if (!(xcr0 & XFEATURE_MASK_FP)) |
2acf923e | 737 | return 1; |
d91cab78 | 738 | if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) |
2acf923e | 739 | return 1; |
46c34cb0 PB |
740 | |
741 | /* | |
742 | * Do not allow the guest to set bits that we do not support | |
743 | * saving. However, xcr0 bit 0 is always set, even if the | |
744 | * emulated CPU does not support XSAVE (see fx_init). | |
745 | */ | |
d91cab78 | 746 | valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; |
46c34cb0 | 747 | if (xcr0 & ~valid_bits) |
2acf923e | 748 | return 1; |
46c34cb0 | 749 | |
d91cab78 DH |
750 | if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != |
751 | (!(xcr0 & XFEATURE_MASK_BNDCSR))) | |
390bd528 LJ |
752 | return 1; |
753 | ||
d91cab78 DH |
754 | if (xcr0 & XFEATURE_MASK_AVX512) { |
755 | if (!(xcr0 & XFEATURE_MASK_YMM)) | |
612263b3 | 756 | return 1; |
d91cab78 | 757 | if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) |
612263b3 CP |
758 | return 1; |
759 | } | |
2acf923e | 760 | vcpu->arch.xcr0 = xcr0; |
56c103ec | 761 | |
d91cab78 | 762 | if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) |
56c103ec | 763 | kvm_update_cpuid(vcpu); |
2acf923e DC |
764 | return 0; |
765 | } | |
766 | ||
767 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) | |
768 | { | |
764bcbc5 Z |
769 | if (kvm_x86_ops->get_cpl(vcpu) != 0 || |
770 | __kvm_set_xcr(vcpu, index, xcr)) { | |
2acf923e DC |
771 | kvm_inject_gp(vcpu, 0); |
772 | return 1; | |
773 | } | |
774 | return 0; | |
775 | } | |
776 | EXPORT_SYMBOL_GPL(kvm_set_xcr); | |
777 | ||
a83b29c6 | 778 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 779 | { |
fc78f519 | 780 | unsigned long old_cr4 = kvm_read_cr4(vcpu); |
0be0226f | 781 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | |
b9baba86 | 782 | X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE; |
0be0226f | 783 | |
0f12244f GN |
784 | if (cr4 & CR4_RESERVED_BITS) |
785 | return 1; | |
a03490ed | 786 | |
d6321d49 | 787 | if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE)) |
2acf923e DC |
788 | return 1; |
789 | ||
d6321d49 | 790 | if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP)) |
2acf923e DC |
791 | return 1; |
792 | ||
d6321d49 | 793 | if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP)) |
c68b734f YW |
794 | return 1; |
795 | ||
d6321d49 | 796 | if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE)) |
97ec8c06 FW |
797 | return 1; |
798 | ||
d6321d49 | 799 | if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE)) |
74dc2b4f YW |
800 | return 1; |
801 | ||
fd8cb433 | 802 | if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57)) |
b9baba86 HH |
803 | return 1; |
804 | ||
ae3e61e1 PB |
805 | if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP)) |
806 | return 1; | |
807 | ||
a03490ed | 808 | if (is_long_mode(vcpu)) { |
0f12244f GN |
809 | if (!(cr4 & X86_CR4_PAE)) |
810 | return 1; | |
a2edf57f AK |
811 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
812 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
9f8fe504 AK |
813 | && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
814 | kvm_read_cr3(vcpu))) | |
0f12244f GN |
815 | return 1; |
816 | ||
ad756a16 | 817 | if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { |
d6321d49 | 818 | if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) |
ad756a16 MJ |
819 | return 1; |
820 | ||
821 | /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ | |
822 | if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) | |
823 | return 1; | |
824 | } | |
825 | ||
5e1746d6 | 826 | if (kvm_x86_ops->set_cr4(vcpu, cr4)) |
0f12244f | 827 | return 1; |
a03490ed | 828 | |
ad756a16 MJ |
829 | if (((cr4 ^ old_cr4) & pdptr_bits) || |
830 | (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) | |
aad82703 | 831 | kvm_mmu_reset_context(vcpu); |
0f12244f | 832 | |
b9baba86 | 833 | if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE)) |
00b27a3e | 834 | kvm_update_cpuid(vcpu); |
2acf923e | 835 | |
0f12244f GN |
836 | return 0; |
837 | } | |
2d3ad1f4 | 838 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 839 | |
2390218b | 840 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 841 | { |
ac146235 | 842 | #ifdef CONFIG_X86_64 |
9d88fca7 | 843 | cr3 &= ~CR3_PCID_INVD; |
ac146235 | 844 | #endif |
9d88fca7 | 845 | |
9f8fe504 | 846 | if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { |
0ba73cda | 847 | kvm_mmu_sync_roots(vcpu); |
77c3913b | 848 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
0f12244f | 849 | return 0; |
d835dfec AK |
850 | } |
851 | ||
d1cd3ce9 YZ |
852 | if (is_long_mode(vcpu) && |
853 | (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62))) | |
854 | return 1; | |
855 | else if (is_pae(vcpu) && is_paging(vcpu) && | |
d9f89b88 | 856 | !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) |
346874c9 | 857 | return 1; |
a03490ed | 858 | |
0f12244f | 859 | vcpu->arch.cr3 = cr3; |
aff48baa | 860 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); |
d8d173da | 861 | kvm_mmu_new_cr3(vcpu); |
0f12244f GN |
862 | return 0; |
863 | } | |
2d3ad1f4 | 864 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 865 | |
eea1cff9 | 866 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed | 867 | { |
0f12244f GN |
868 | if (cr8 & CR8_RESERVED_BITS) |
869 | return 1; | |
35754c98 | 870 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
871 | kvm_lapic_set_tpr(vcpu, cr8); |
872 | else | |
ad312c7c | 873 | vcpu->arch.cr8 = cr8; |
0f12244f GN |
874 | return 0; |
875 | } | |
2d3ad1f4 | 876 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 877 | |
2d3ad1f4 | 878 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed | 879 | { |
35754c98 | 880 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
881 | return kvm_lapic_get_cr8(vcpu); |
882 | else | |
ad312c7c | 883 | return vcpu->arch.cr8; |
a03490ed | 884 | } |
2d3ad1f4 | 885 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 886 | |
ae561ede NA |
887 | static void kvm_update_dr0123(struct kvm_vcpu *vcpu) |
888 | { | |
889 | int i; | |
890 | ||
891 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
892 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
893 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
894 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; | |
895 | } | |
896 | } | |
897 | ||
73aaf249 JK |
898 | static void kvm_update_dr6(struct kvm_vcpu *vcpu) |
899 | { | |
900 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
901 | kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); | |
902 | } | |
903 | ||
c8639010 JK |
904 | static void kvm_update_dr7(struct kvm_vcpu *vcpu) |
905 | { | |
906 | unsigned long dr7; | |
907 | ||
908 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
909 | dr7 = vcpu->arch.guest_debug_dr7; | |
910 | else | |
911 | dr7 = vcpu->arch.dr7; | |
912 | kvm_x86_ops->set_dr7(vcpu, dr7); | |
360b948d PB |
913 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; |
914 | if (dr7 & DR7_BP_EN_MASK) | |
915 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; | |
c8639010 JK |
916 | } |
917 | ||
6f43ed01 NA |
918 | static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) |
919 | { | |
920 | u64 fixed = DR6_FIXED_1; | |
921 | ||
d6321d49 | 922 | if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) |
6f43ed01 NA |
923 | fixed |= DR6_RTM; |
924 | return fixed; | |
925 | } | |
926 | ||
338dbc97 | 927 | static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) |
020df079 GN |
928 | { |
929 | switch (dr) { | |
930 | case 0 ... 3: | |
931 | vcpu->arch.db[dr] = val; | |
932 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
933 | vcpu->arch.eff_db[dr] = val; | |
934 | break; | |
935 | case 4: | |
020df079 GN |
936 | /* fall through */ |
937 | case 6: | |
338dbc97 GN |
938 | if (val & 0xffffffff00000000ULL) |
939 | return -1; /* #GP */ | |
6f43ed01 | 940 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); |
73aaf249 | 941 | kvm_update_dr6(vcpu); |
020df079 GN |
942 | break; |
943 | case 5: | |
020df079 GN |
944 | /* fall through */ |
945 | default: /* 7 */ | |
338dbc97 GN |
946 | if (val & 0xffffffff00000000ULL) |
947 | return -1; /* #GP */ | |
020df079 | 948 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; |
c8639010 | 949 | kvm_update_dr7(vcpu); |
020df079 GN |
950 | break; |
951 | } | |
952 | ||
953 | return 0; | |
954 | } | |
338dbc97 GN |
955 | |
956 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) | |
957 | { | |
16f8a6f9 | 958 | if (__kvm_set_dr(vcpu, dr, val)) { |
338dbc97 | 959 | kvm_inject_gp(vcpu, 0); |
16f8a6f9 NA |
960 | return 1; |
961 | } | |
962 | return 0; | |
338dbc97 | 963 | } |
020df079 GN |
964 | EXPORT_SYMBOL_GPL(kvm_set_dr); |
965 | ||
16f8a6f9 | 966 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) |
020df079 GN |
967 | { |
968 | switch (dr) { | |
969 | case 0 ... 3: | |
970 | *val = vcpu->arch.db[dr]; | |
971 | break; | |
972 | case 4: | |
020df079 GN |
973 | /* fall through */ |
974 | case 6: | |
73aaf249 JK |
975 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) |
976 | *val = vcpu->arch.dr6; | |
977 | else | |
978 | *val = kvm_x86_ops->get_dr6(vcpu); | |
020df079 GN |
979 | break; |
980 | case 5: | |
020df079 GN |
981 | /* fall through */ |
982 | default: /* 7 */ | |
983 | *val = vcpu->arch.dr7; | |
984 | break; | |
985 | } | |
338dbc97 GN |
986 | return 0; |
987 | } | |
020df079 GN |
988 | EXPORT_SYMBOL_GPL(kvm_get_dr); |
989 | ||
022cd0e8 AK |
990 | bool kvm_rdpmc(struct kvm_vcpu *vcpu) |
991 | { | |
992 | u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
993 | u64 data; | |
994 | int err; | |
995 | ||
c6702c9d | 996 | err = kvm_pmu_rdpmc(vcpu, ecx, &data); |
022cd0e8 AK |
997 | if (err) |
998 | return err; | |
999 | kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data); | |
1000 | kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32); | |
1001 | return err; | |
1002 | } | |
1003 | EXPORT_SYMBOL_GPL(kvm_rdpmc); | |
1004 | ||
043405e1 CO |
1005 | /* |
1006 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
1007 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
1008 | * | |
1009 | * This list is modified at module load time to reflect the | |
e3267cbb | 1010 | * capabilities of the host cpu. This capabilities test skips MSRs that are |
62ef68bb PB |
1011 | * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs |
1012 | * may depend on host virtualization features rather than host cpu features. | |
043405e1 | 1013 | */ |
e3267cbb | 1014 | |
043405e1 CO |
1015 | static u32 msrs_to_save[] = { |
1016 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
8c06585d | 1017 | MSR_STAR, |
043405e1 CO |
1018 | #ifdef CONFIG_X86_64 |
1019 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
1020 | #endif | |
b3897a49 | 1021 | MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, |
9dbe6cf9 | 1022 | MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, |
d28b387f | 1023 | MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES |
043405e1 CO |
1024 | }; |
1025 | ||
1026 | static unsigned num_msrs_to_save; | |
1027 | ||
62ef68bb PB |
1028 | static u32 emulated_msrs[] = { |
1029 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, | |
1030 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, | |
1031 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, | |
1032 | HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, | |
72c139ba | 1033 | HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, |
e7d9513b AS |
1034 | HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, |
1035 | HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, | |
e516cebb | 1036 | HV_X64_MSR_RESET, |
11c4b1ca | 1037 | HV_X64_MSR_VP_INDEX, |
9eec50b8 | 1038 | HV_X64_MSR_VP_RUNTIME, |
5c919412 | 1039 | HV_X64_MSR_SCONTROL, |
1f4b34f8 | 1040 | HV_X64_MSR_STIMER0_CONFIG, |
d4abc577 | 1041 | HV_X64_MSR_VP_ASSIST_PAGE, |
a2e164e7 VK |
1042 | HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, |
1043 | HV_X64_MSR_TSC_EMULATION_STATUS, | |
1044 | ||
1045 | MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, | |
62ef68bb PB |
1046 | MSR_KVM_PV_EOI_EN, |
1047 | ||
ba904635 | 1048 | MSR_IA32_TSC_ADJUST, |
a3e06bbe | 1049 | MSR_IA32_TSCDEADLINE, |
043405e1 | 1050 | MSR_IA32_MISC_ENABLE, |
908e75f3 AK |
1051 | MSR_IA32_MCG_STATUS, |
1052 | MSR_IA32_MCG_CTL, | |
c45dcc71 | 1053 | MSR_IA32_MCG_EXT_CTL, |
64d60670 | 1054 | MSR_IA32_SMBASE, |
52797bf9 | 1055 | MSR_SMI_COUNT, |
db2336a8 KH |
1056 | MSR_PLATFORM_INFO, |
1057 | MSR_MISC_FEATURES_ENABLES, | |
043405e1 CO |
1058 | }; |
1059 | ||
62ef68bb PB |
1060 | static unsigned num_emulated_msrs; |
1061 | ||
801e459a TL |
1062 | /* |
1063 | * List of msr numbers which are used to expose MSR-based features that | |
1064 | * can be used by a hypervisor to validate requested CPU features. | |
1065 | */ | |
1066 | static u32 msr_based_features[] = { | |
1389309c PB |
1067 | MSR_IA32_VMX_BASIC, |
1068 | MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
1069 | MSR_IA32_VMX_PINBASED_CTLS, | |
1070 | MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
1071 | MSR_IA32_VMX_PROCBASED_CTLS, | |
1072 | MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
1073 | MSR_IA32_VMX_EXIT_CTLS, | |
1074 | MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
1075 | MSR_IA32_VMX_ENTRY_CTLS, | |
1076 | MSR_IA32_VMX_MISC, | |
1077 | MSR_IA32_VMX_CR0_FIXED0, | |
1078 | MSR_IA32_VMX_CR0_FIXED1, | |
1079 | MSR_IA32_VMX_CR4_FIXED0, | |
1080 | MSR_IA32_VMX_CR4_FIXED1, | |
1081 | MSR_IA32_VMX_VMCS_ENUM, | |
1082 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
1083 | MSR_IA32_VMX_EPT_VPID_CAP, | |
1084 | MSR_IA32_VMX_VMFUNC, | |
1085 | ||
d1d93fa9 | 1086 | MSR_F10H_DECFG, |
518e7b94 | 1087 | MSR_IA32_UCODE_REV, |
801e459a TL |
1088 | }; |
1089 | ||
1090 | static unsigned int num_msr_based_features; | |
1091 | ||
66421c1e WL |
1092 | static int kvm_get_msr_feature(struct kvm_msr_entry *msr) |
1093 | { | |
1094 | switch (msr->index) { | |
518e7b94 WL |
1095 | case MSR_IA32_UCODE_REV: |
1096 | rdmsrl(msr->index, msr->data); | |
1097 | break; | |
66421c1e WL |
1098 | default: |
1099 | if (kvm_x86_ops->get_msr_feature(msr)) | |
1100 | return 1; | |
1101 | } | |
1102 | return 0; | |
1103 | } | |
1104 | ||
801e459a TL |
1105 | static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) |
1106 | { | |
1107 | struct kvm_msr_entry msr; | |
66421c1e | 1108 | int r; |
801e459a TL |
1109 | |
1110 | msr.index = index; | |
66421c1e WL |
1111 | r = kvm_get_msr_feature(&msr); |
1112 | if (r) | |
1113 | return r; | |
801e459a TL |
1114 | |
1115 | *data = msr.data; | |
1116 | ||
1117 | return 0; | |
1118 | } | |
1119 | ||
384bb783 | 1120 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) |
15c4a640 | 1121 | { |
b69e8cae | 1122 | if (efer & efer_reserved_bits) |
384bb783 | 1123 | return false; |
15c4a640 | 1124 | |
1b4d56b8 | 1125 | if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) |
384bb783 | 1126 | return false; |
1b2fd70c | 1127 | |
1b4d56b8 | 1128 | if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) |
384bb783 | 1129 | return false; |
d8017474 | 1130 | |
384bb783 JK |
1131 | return true; |
1132 | } | |
1133 | EXPORT_SYMBOL_GPL(kvm_valid_efer); | |
1134 | ||
1135 | static int set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
1136 | { | |
1137 | u64 old_efer = vcpu->arch.efer; | |
1138 | ||
1139 | if (!kvm_valid_efer(vcpu, efer)) | |
1140 | return 1; | |
1141 | ||
1142 | if (is_paging(vcpu) | |
1143 | && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) | |
1144 | return 1; | |
1145 | ||
15c4a640 | 1146 | efer &= ~EFER_LMA; |
f6801dff | 1147 | efer |= vcpu->arch.efer & EFER_LMA; |
15c4a640 | 1148 | |
a3d204e2 SY |
1149 | kvm_x86_ops->set_efer(vcpu, efer); |
1150 | ||
aad82703 SY |
1151 | /* Update reserved bits */ |
1152 | if ((efer ^ old_efer) & EFER_NX) | |
1153 | kvm_mmu_reset_context(vcpu); | |
1154 | ||
b69e8cae | 1155 | return 0; |
15c4a640 CO |
1156 | } |
1157 | ||
f2b4b7dd JR |
1158 | void kvm_enable_efer_bits(u64 mask) |
1159 | { | |
1160 | efer_reserved_bits &= ~mask; | |
1161 | } | |
1162 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
1163 | ||
15c4a640 CO |
1164 | /* |
1165 | * Writes msr value into into the appropriate "register". | |
1166 | * Returns 0 on success, non-0 otherwise. | |
1167 | * Assumes vcpu_load() was already called. | |
1168 | */ | |
8fe8ab46 | 1169 | int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) |
15c4a640 | 1170 | { |
854e8bb1 NA |
1171 | switch (msr->index) { |
1172 | case MSR_FS_BASE: | |
1173 | case MSR_GS_BASE: | |
1174 | case MSR_KERNEL_GS_BASE: | |
1175 | case MSR_CSTAR: | |
1176 | case MSR_LSTAR: | |
fd8cb433 | 1177 | if (is_noncanonical_address(msr->data, vcpu)) |
854e8bb1 NA |
1178 | return 1; |
1179 | break; | |
1180 | case MSR_IA32_SYSENTER_EIP: | |
1181 | case MSR_IA32_SYSENTER_ESP: | |
1182 | /* | |
1183 | * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if | |
1184 | * non-canonical address is written on Intel but not on | |
1185 | * AMD (which ignores the top 32-bits, because it does | |
1186 | * not implement 64-bit SYSENTER). | |
1187 | * | |
1188 | * 64-bit code should hence be able to write a non-canonical | |
1189 | * value on AMD. Making the address canonical ensures that | |
1190 | * vmentry does not fail on Intel after writing a non-canonical | |
1191 | * value, and that something deterministic happens if the guest | |
1192 | * invokes 64-bit SYSENTER. | |
1193 | */ | |
fd8cb433 | 1194 | msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu)); |
854e8bb1 | 1195 | } |
8fe8ab46 | 1196 | return kvm_x86_ops->set_msr(vcpu, msr); |
15c4a640 | 1197 | } |
854e8bb1 | 1198 | EXPORT_SYMBOL_GPL(kvm_set_msr); |
15c4a640 | 1199 | |
313a3dc7 CO |
1200 | /* |
1201 | * Adapt set_msr() to msr_io()'s calling convention | |
1202 | */ | |
609e36d3 PB |
1203 | static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) |
1204 | { | |
1205 | struct msr_data msr; | |
1206 | int r; | |
1207 | ||
1208 | msr.index = index; | |
1209 | msr.host_initiated = true; | |
1210 | r = kvm_get_msr(vcpu, &msr); | |
1211 | if (r) | |
1212 | return r; | |
1213 | ||
1214 | *data = msr.data; | |
1215 | return 0; | |
1216 | } | |
1217 | ||
313a3dc7 CO |
1218 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) |
1219 | { | |
8fe8ab46 WA |
1220 | struct msr_data msr; |
1221 | ||
1222 | msr.data = *data; | |
1223 | msr.index = index; | |
1224 | msr.host_initiated = true; | |
1225 | return kvm_set_msr(vcpu, &msr); | |
313a3dc7 CO |
1226 | } |
1227 | ||
16e8d74d MT |
1228 | #ifdef CONFIG_X86_64 |
1229 | struct pvclock_gtod_data { | |
1230 | seqcount_t seq; | |
1231 | ||
1232 | struct { /* extract of a clocksource struct */ | |
1233 | int vclock_mode; | |
a5a1d1c2 TG |
1234 | u64 cycle_last; |
1235 | u64 mask; | |
16e8d74d MT |
1236 | u32 mult; |
1237 | u32 shift; | |
1238 | } clock; | |
1239 | ||
cbcf2dd3 TG |
1240 | u64 boot_ns; |
1241 | u64 nsec_base; | |
55dd00a7 | 1242 | u64 wall_time_sec; |
16e8d74d MT |
1243 | }; |
1244 | ||
1245 | static struct pvclock_gtod_data pvclock_gtod_data; | |
1246 | ||
1247 | static void update_pvclock_gtod(struct timekeeper *tk) | |
1248 | { | |
1249 | struct pvclock_gtod_data *vdata = &pvclock_gtod_data; | |
cbcf2dd3 TG |
1250 | u64 boot_ns; |
1251 | ||
876e7881 | 1252 | boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot)); |
16e8d74d MT |
1253 | |
1254 | write_seqcount_begin(&vdata->seq); | |
1255 | ||
1256 | /* copy pvclock gtod data */ | |
876e7881 PZ |
1257 | vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode; |
1258 | vdata->clock.cycle_last = tk->tkr_mono.cycle_last; | |
1259 | vdata->clock.mask = tk->tkr_mono.mask; | |
1260 | vdata->clock.mult = tk->tkr_mono.mult; | |
1261 | vdata->clock.shift = tk->tkr_mono.shift; | |
16e8d74d | 1262 | |
cbcf2dd3 | 1263 | vdata->boot_ns = boot_ns; |
876e7881 | 1264 | vdata->nsec_base = tk->tkr_mono.xtime_nsec; |
16e8d74d | 1265 | |
55dd00a7 MT |
1266 | vdata->wall_time_sec = tk->xtime_sec; |
1267 | ||
16e8d74d MT |
1268 | write_seqcount_end(&vdata->seq); |
1269 | } | |
1270 | #endif | |
1271 | ||
bab5bb39 NK |
1272 | void kvm_set_pending_timer(struct kvm_vcpu *vcpu) |
1273 | { | |
1274 | /* | |
1275 | * Note: KVM_REQ_PENDING_TIMER is implicitly checked in | |
1276 | * vcpu_enter_guest. This function is only called from | |
1277 | * the physical CPU that is running vcpu. | |
1278 | */ | |
1279 | kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); | |
1280 | } | |
16e8d74d | 1281 | |
18068523 GOC |
1282 | static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) |
1283 | { | |
9ed3c444 AK |
1284 | int version; |
1285 | int r; | |
50d0a0f9 | 1286 | struct pvclock_wall_clock wc; |
87aeb54f | 1287 | struct timespec64 boot; |
18068523 GOC |
1288 | |
1289 | if (!wall_clock) | |
1290 | return; | |
1291 | ||
9ed3c444 AK |
1292 | r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); |
1293 | if (r) | |
1294 | return; | |
1295 | ||
1296 | if (version & 1) | |
1297 | ++version; /* first time write, random junk */ | |
1298 | ||
1299 | ++version; | |
18068523 | 1300 | |
1dab1345 NK |
1301 | if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) |
1302 | return; | |
18068523 | 1303 | |
50d0a0f9 GH |
1304 | /* |
1305 | * The guest calculates current wall clock time by adding | |
34c238a1 | 1306 | * system time (updated by kvm_guest_time_update below) to the |
50d0a0f9 GH |
1307 | * wall clock specified here. guest system time equals host |
1308 | * system time for us, thus we must fill in host boot time here. | |
1309 | */ | |
87aeb54f | 1310 | getboottime64(&boot); |
50d0a0f9 | 1311 | |
4b648665 | 1312 | if (kvm->arch.kvmclock_offset) { |
87aeb54f AB |
1313 | struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset); |
1314 | boot = timespec64_sub(boot, ts); | |
4b648665 | 1315 | } |
87aeb54f | 1316 | wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */ |
50d0a0f9 GH |
1317 | wc.nsec = boot.tv_nsec; |
1318 | wc.version = version; | |
18068523 GOC |
1319 | |
1320 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
1321 | ||
1322 | version++; | |
1323 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
1324 | } |
1325 | ||
50d0a0f9 GH |
1326 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
1327 | { | |
b51012de PB |
1328 | do_shl32_div32(dividend, divisor); |
1329 | return dividend; | |
50d0a0f9 GH |
1330 | } |
1331 | ||
3ae13faa | 1332 | static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, |
5f4e3f88 | 1333 | s8 *pshift, u32 *pmultiplier) |
50d0a0f9 | 1334 | { |
5f4e3f88 | 1335 | uint64_t scaled64; |
50d0a0f9 GH |
1336 | int32_t shift = 0; |
1337 | uint64_t tps64; | |
1338 | uint32_t tps32; | |
1339 | ||
3ae13faa PB |
1340 | tps64 = base_hz; |
1341 | scaled64 = scaled_hz; | |
50933623 | 1342 | while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { |
50d0a0f9 GH |
1343 | tps64 >>= 1; |
1344 | shift--; | |
1345 | } | |
1346 | ||
1347 | tps32 = (uint32_t)tps64; | |
50933623 JK |
1348 | while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { |
1349 | if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) | |
5f4e3f88 ZA |
1350 | scaled64 >>= 1; |
1351 | else | |
1352 | tps32 <<= 1; | |
50d0a0f9 GH |
1353 | shift++; |
1354 | } | |
1355 | ||
5f4e3f88 ZA |
1356 | *pshift = shift; |
1357 | *pmultiplier = div_frac(scaled64, tps32); | |
50d0a0f9 | 1358 | |
3ae13faa PB |
1359 | pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n", |
1360 | __func__, base_hz, scaled_hz, shift, *pmultiplier); | |
50d0a0f9 GH |
1361 | } |
1362 | ||
d828199e | 1363 | #ifdef CONFIG_X86_64 |
16e8d74d | 1364 | static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); |
d828199e | 1365 | #endif |
16e8d74d | 1366 | |
c8076604 | 1367 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
69b0049a | 1368 | static unsigned long max_tsc_khz; |
c8076604 | 1369 | |
cc578287 | 1370 | static u32 adjust_tsc_khz(u32 khz, s32 ppm) |
1e993611 | 1371 | { |
cc578287 ZA |
1372 | u64 v = (u64)khz * (1000000 + ppm); |
1373 | do_div(v, 1000000); | |
1374 | return v; | |
1e993611 JR |
1375 | } |
1376 | ||
381d585c HZ |
1377 | static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) |
1378 | { | |
1379 | u64 ratio; | |
1380 | ||
1381 | /* Guest TSC same frequency as host TSC? */ | |
1382 | if (!scale) { | |
1383 | vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; | |
1384 | return 0; | |
1385 | } | |
1386 | ||
1387 | /* TSC scaling supported? */ | |
1388 | if (!kvm_has_tsc_control) { | |
1389 | if (user_tsc_khz > tsc_khz) { | |
1390 | vcpu->arch.tsc_catchup = 1; | |
1391 | vcpu->arch.tsc_always_catchup = 1; | |
1392 | return 0; | |
1393 | } else { | |
1394 | WARN(1, "user requested TSC rate below hardware speed\n"); | |
1395 | return -1; | |
1396 | } | |
1397 | } | |
1398 | ||
1399 | /* TSC scaling required - calculate ratio */ | |
1400 | ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, | |
1401 | user_tsc_khz, tsc_khz); | |
1402 | ||
1403 | if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { | |
1404 | WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", | |
1405 | user_tsc_khz); | |
1406 | return -1; | |
1407 | } | |
1408 | ||
1409 | vcpu->arch.tsc_scaling_ratio = ratio; | |
1410 | return 0; | |
1411 | } | |
1412 | ||
4941b8cb | 1413 | static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) |
759379dd | 1414 | { |
cc578287 ZA |
1415 | u32 thresh_lo, thresh_hi; |
1416 | int use_scaling = 0; | |
217fc9cf | 1417 | |
03ba32ca | 1418 | /* tsc_khz can be zero if TSC calibration fails */ |
4941b8cb | 1419 | if (user_tsc_khz == 0) { |
ad721883 HZ |
1420 | /* set tsc_scaling_ratio to a safe value */ |
1421 | vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; | |
381d585c | 1422 | return -1; |
ad721883 | 1423 | } |
03ba32ca | 1424 | |
c285545f | 1425 | /* Compute a scale to convert nanoseconds in TSC cycles */ |
3ae13faa | 1426 | kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, |
cc578287 ZA |
1427 | &vcpu->arch.virtual_tsc_shift, |
1428 | &vcpu->arch.virtual_tsc_mult); | |
4941b8cb | 1429 | vcpu->arch.virtual_tsc_khz = user_tsc_khz; |
cc578287 ZA |
1430 | |
1431 | /* | |
1432 | * Compute the variation in TSC rate which is acceptable | |
1433 | * within the range of tolerance and decide if the | |
1434 | * rate being applied is within that bounds of the hardware | |
1435 | * rate. If so, no scaling or compensation need be done. | |
1436 | */ | |
1437 | thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); | |
1438 | thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); | |
4941b8cb PB |
1439 | if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { |
1440 | pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); | |
cc578287 ZA |
1441 | use_scaling = 1; |
1442 | } | |
4941b8cb | 1443 | return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); |
c285545f ZA |
1444 | } |
1445 | ||
1446 | static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) | |
1447 | { | |
e26101b1 | 1448 | u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, |
cc578287 ZA |
1449 | vcpu->arch.virtual_tsc_mult, |
1450 | vcpu->arch.virtual_tsc_shift); | |
e26101b1 | 1451 | tsc += vcpu->arch.this_tsc_write; |
c285545f ZA |
1452 | return tsc; |
1453 | } | |
1454 | ||
b0c39dc6 VK |
1455 | static inline int gtod_is_based_on_tsc(int mode) |
1456 | { | |
1457 | return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK; | |
1458 | } | |
1459 | ||
69b0049a | 1460 | static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) |
b48aa97e MT |
1461 | { |
1462 | #ifdef CONFIG_X86_64 | |
1463 | bool vcpus_matched; | |
b48aa97e MT |
1464 | struct kvm_arch *ka = &vcpu->kvm->arch; |
1465 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
1466 | ||
1467 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
1468 | atomic_read(&vcpu->kvm->online_vcpus)); | |
1469 | ||
7f187922 MT |
1470 | /* |
1471 | * Once the masterclock is enabled, always perform request in | |
1472 | * order to update it. | |
1473 | * | |
1474 | * In order to enable masterclock, the host clocksource must be TSC | |
1475 | * and the vcpus need to have matched TSCs. When that happens, | |
1476 | * perform request to enable masterclock. | |
1477 | */ | |
1478 | if (ka->use_master_clock || | |
b0c39dc6 | 1479 | (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) |
b48aa97e MT |
1480 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
1481 | ||
1482 | trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, | |
1483 | atomic_read(&vcpu->kvm->online_vcpus), | |
1484 | ka->use_master_clock, gtod->clock.vclock_mode); | |
1485 | #endif | |
1486 | } | |
1487 | ||
ba904635 WA |
1488 | static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) |
1489 | { | |
3e3f5026 | 1490 | u64 curr_offset = vcpu->arch.tsc_offset; |
ba904635 WA |
1491 | vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; |
1492 | } | |
1493 | ||
35181e86 HZ |
1494 | /* |
1495 | * Multiply tsc by a fixed point number represented by ratio. | |
1496 | * | |
1497 | * The most significant 64-N bits (mult) of ratio represent the | |
1498 | * integral part of the fixed point number; the remaining N bits | |
1499 | * (frac) represent the fractional part, ie. ratio represents a fixed | |
1500 | * point number (mult + frac * 2^(-N)). | |
1501 | * | |
1502 | * N equals to kvm_tsc_scaling_ratio_frac_bits. | |
1503 | */ | |
1504 | static inline u64 __scale_tsc(u64 ratio, u64 tsc) | |
1505 | { | |
1506 | return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); | |
1507 | } | |
1508 | ||
1509 | u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) | |
1510 | { | |
1511 | u64 _tsc = tsc; | |
1512 | u64 ratio = vcpu->arch.tsc_scaling_ratio; | |
1513 | ||
1514 | if (ratio != kvm_default_tsc_scaling_ratio) | |
1515 | _tsc = __scale_tsc(ratio, tsc); | |
1516 | ||
1517 | return _tsc; | |
1518 | } | |
1519 | EXPORT_SYMBOL_GPL(kvm_scale_tsc); | |
1520 | ||
07c1419a HZ |
1521 | static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) |
1522 | { | |
1523 | u64 tsc; | |
1524 | ||
1525 | tsc = kvm_scale_tsc(vcpu, rdtsc()); | |
1526 | ||
1527 | return target_tsc - tsc; | |
1528 | } | |
1529 | ||
4ba76538 HZ |
1530 | u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) |
1531 | { | |
ea26e4ec | 1532 | return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc); |
4ba76538 HZ |
1533 | } |
1534 | EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); | |
1535 | ||
a545ab6a LC |
1536 | static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
1537 | { | |
1538 | kvm_x86_ops->write_tsc_offset(vcpu, offset); | |
1539 | vcpu->arch.tsc_offset = offset; | |
1540 | } | |
1541 | ||
b0c39dc6 VK |
1542 | static inline bool kvm_check_tsc_unstable(void) |
1543 | { | |
1544 | #ifdef CONFIG_X86_64 | |
1545 | /* | |
1546 | * TSC is marked unstable when we're running on Hyper-V, | |
1547 | * 'TSC page' clocksource is good. | |
1548 | */ | |
1549 | if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK) | |
1550 | return false; | |
1551 | #endif | |
1552 | return check_tsc_unstable(); | |
1553 | } | |
1554 | ||
8fe8ab46 | 1555 | void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) |
99e3e30a ZA |
1556 | { |
1557 | struct kvm *kvm = vcpu->kvm; | |
f38e098f | 1558 | u64 offset, ns, elapsed; |
99e3e30a | 1559 | unsigned long flags; |
b48aa97e | 1560 | bool matched; |
0d3da0d2 | 1561 | bool already_matched; |
8fe8ab46 | 1562 | u64 data = msr->data; |
c5e8ec8e | 1563 | bool synchronizing = false; |
99e3e30a | 1564 | |
038f8c11 | 1565 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); |
07c1419a | 1566 | offset = kvm_compute_tsc_offset(vcpu, data); |
108b249c | 1567 | ns = ktime_get_boot_ns(); |
f38e098f | 1568 | elapsed = ns - kvm->arch.last_tsc_nsec; |
5d3cb0f6 | 1569 | |
03ba32ca | 1570 | if (vcpu->arch.virtual_tsc_khz) { |
bd8fab39 DP |
1571 | if (data == 0 && msr->host_initiated) { |
1572 | /* | |
1573 | * detection of vcpu initialization -- need to sync | |
1574 | * with other vCPUs. This particularly helps to keep | |
1575 | * kvm_clock stable after CPU hotplug | |
1576 | */ | |
1577 | synchronizing = true; | |
1578 | } else { | |
1579 | u64 tsc_exp = kvm->arch.last_tsc_write + | |
1580 | nsec_to_cycles(vcpu, elapsed); | |
1581 | u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; | |
1582 | /* | |
1583 | * Special case: TSC write with a small delta (1 second) | |
1584 | * of virtual cycle time against real time is | |
1585 | * interpreted as an attempt to synchronize the CPU. | |
1586 | */ | |
1587 | synchronizing = data < tsc_exp + tsc_hz && | |
1588 | data + tsc_hz > tsc_exp; | |
1589 | } | |
c5e8ec8e | 1590 | } |
f38e098f ZA |
1591 | |
1592 | /* | |
5d3cb0f6 ZA |
1593 | * For a reliable TSC, we can match TSC offsets, and for an unstable |
1594 | * TSC, we add elapsed time in this computation. We could let the | |
1595 | * compensation code attempt to catch up if we fall behind, but | |
1596 | * it's better to try to match offsets from the beginning. | |
1597 | */ | |
c5e8ec8e | 1598 | if (synchronizing && |
5d3cb0f6 | 1599 | vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { |
b0c39dc6 | 1600 | if (!kvm_check_tsc_unstable()) { |
e26101b1 | 1601 | offset = kvm->arch.cur_tsc_offset; |
f38e098f ZA |
1602 | pr_debug("kvm: matched tsc offset for %llu\n", data); |
1603 | } else { | |
857e4099 | 1604 | u64 delta = nsec_to_cycles(vcpu, elapsed); |
5d3cb0f6 | 1605 | data += delta; |
07c1419a | 1606 | offset = kvm_compute_tsc_offset(vcpu, data); |
759379dd | 1607 | pr_debug("kvm: adjusted tsc offset by %llu\n", delta); |
f38e098f | 1608 | } |
b48aa97e | 1609 | matched = true; |
0d3da0d2 | 1610 | already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); |
e26101b1 ZA |
1611 | } else { |
1612 | /* | |
1613 | * We split periods of matched TSC writes into generations. | |
1614 | * For each generation, we track the original measured | |
1615 | * nanosecond time, offset, and write, so if TSCs are in | |
1616 | * sync, we can match exact offset, and if not, we can match | |
4a969980 | 1617 | * exact software computation in compute_guest_tsc() |
e26101b1 ZA |
1618 | * |
1619 | * These values are tracked in kvm->arch.cur_xxx variables. | |
1620 | */ | |
1621 | kvm->arch.cur_tsc_generation++; | |
1622 | kvm->arch.cur_tsc_nsec = ns; | |
1623 | kvm->arch.cur_tsc_write = data; | |
1624 | kvm->arch.cur_tsc_offset = offset; | |
b48aa97e | 1625 | matched = false; |
0d3da0d2 | 1626 | pr_debug("kvm: new tsc generation %llu, clock %llu\n", |
e26101b1 | 1627 | kvm->arch.cur_tsc_generation, data); |
f38e098f | 1628 | } |
e26101b1 ZA |
1629 | |
1630 | /* | |
1631 | * We also track th most recent recorded KHZ, write and time to | |
1632 | * allow the matching interval to be extended at each write. | |
1633 | */ | |
f38e098f ZA |
1634 | kvm->arch.last_tsc_nsec = ns; |
1635 | kvm->arch.last_tsc_write = data; | |
5d3cb0f6 | 1636 | kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; |
99e3e30a | 1637 | |
b183aa58 | 1638 | vcpu->arch.last_guest_tsc = data; |
e26101b1 ZA |
1639 | |
1640 | /* Keep track of which generation this VCPU has synchronized to */ | |
1641 | vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; | |
1642 | vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; | |
1643 | vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; | |
1644 | ||
d6321d49 | 1645 | if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) |
ba904635 | 1646 | update_ia32_tsc_adjust_msr(vcpu, offset); |
d6321d49 | 1647 | |
a545ab6a | 1648 | kvm_vcpu_write_tsc_offset(vcpu, offset); |
e26101b1 | 1649 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); |
b48aa97e MT |
1650 | |
1651 | spin_lock(&kvm->arch.pvclock_gtod_sync_lock); | |
0d3da0d2 | 1652 | if (!matched) { |
b48aa97e | 1653 | kvm->arch.nr_vcpus_matched_tsc = 0; |
0d3da0d2 TG |
1654 | } else if (!already_matched) { |
1655 | kvm->arch.nr_vcpus_matched_tsc++; | |
1656 | } | |
b48aa97e MT |
1657 | |
1658 | kvm_track_tsc_matching(vcpu); | |
1659 | spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); | |
99e3e30a | 1660 | } |
e26101b1 | 1661 | |
99e3e30a ZA |
1662 | EXPORT_SYMBOL_GPL(kvm_write_tsc); |
1663 | ||
58ea6767 HZ |
1664 | static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, |
1665 | s64 adjustment) | |
1666 | { | |
ea26e4ec | 1667 | kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment); |
58ea6767 HZ |
1668 | } |
1669 | ||
1670 | static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) | |
1671 | { | |
1672 | if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) | |
1673 | WARN_ON(adjustment < 0); | |
1674 | adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); | |
ea26e4ec | 1675 | adjust_tsc_offset_guest(vcpu, adjustment); |
58ea6767 HZ |
1676 | } |
1677 | ||
d828199e MT |
1678 | #ifdef CONFIG_X86_64 |
1679 | ||
a5a1d1c2 | 1680 | static u64 read_tsc(void) |
d828199e | 1681 | { |
a5a1d1c2 | 1682 | u64 ret = (u64)rdtsc_ordered(); |
03b9730b | 1683 | u64 last = pvclock_gtod_data.clock.cycle_last; |
d828199e MT |
1684 | |
1685 | if (likely(ret >= last)) | |
1686 | return ret; | |
1687 | ||
1688 | /* | |
1689 | * GCC likes to generate cmov here, but this branch is extremely | |
6a6256f9 | 1690 | * predictable (it's just a function of time and the likely is |
d828199e MT |
1691 | * very likely) and there's a data dependence, so force GCC |
1692 | * to generate a branch instead. I don't barrier() because | |
1693 | * we don't actually need a barrier, and if this function | |
1694 | * ever gets inlined it will generate worse code. | |
1695 | */ | |
1696 | asm volatile (""); | |
1697 | return last; | |
1698 | } | |
1699 | ||
b0c39dc6 | 1700 | static inline u64 vgettsc(u64 *tsc_timestamp, int *mode) |
d828199e MT |
1701 | { |
1702 | long v; | |
1703 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
b0c39dc6 VK |
1704 | u64 tsc_pg_val; |
1705 | ||
1706 | switch (gtod->clock.vclock_mode) { | |
1707 | case VCLOCK_HVCLOCK: | |
1708 | tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), | |
1709 | tsc_timestamp); | |
1710 | if (tsc_pg_val != U64_MAX) { | |
1711 | /* TSC page valid */ | |
1712 | *mode = VCLOCK_HVCLOCK; | |
1713 | v = (tsc_pg_val - gtod->clock.cycle_last) & | |
1714 | gtod->clock.mask; | |
1715 | } else { | |
1716 | /* TSC page invalid */ | |
1717 | *mode = VCLOCK_NONE; | |
1718 | } | |
1719 | break; | |
1720 | case VCLOCK_TSC: | |
1721 | *mode = VCLOCK_TSC; | |
1722 | *tsc_timestamp = read_tsc(); | |
1723 | v = (*tsc_timestamp - gtod->clock.cycle_last) & | |
1724 | gtod->clock.mask; | |
1725 | break; | |
1726 | default: | |
1727 | *mode = VCLOCK_NONE; | |
1728 | } | |
d828199e | 1729 | |
b0c39dc6 VK |
1730 | if (*mode == VCLOCK_NONE) |
1731 | *tsc_timestamp = v = 0; | |
d828199e | 1732 | |
d828199e MT |
1733 | return v * gtod->clock.mult; |
1734 | } | |
1735 | ||
b0c39dc6 | 1736 | static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp) |
d828199e | 1737 | { |
cbcf2dd3 | 1738 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; |
d828199e | 1739 | unsigned long seq; |
d828199e | 1740 | int mode; |
cbcf2dd3 | 1741 | u64 ns; |
d828199e | 1742 | |
d828199e MT |
1743 | do { |
1744 | seq = read_seqcount_begin(>od->seq); | |
cbcf2dd3 | 1745 | ns = gtod->nsec_base; |
b0c39dc6 | 1746 | ns += vgettsc(tsc_timestamp, &mode); |
d828199e | 1747 | ns >>= gtod->clock.shift; |
cbcf2dd3 | 1748 | ns += gtod->boot_ns; |
d828199e | 1749 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); |
cbcf2dd3 | 1750 | *t = ns; |
d828199e MT |
1751 | |
1752 | return mode; | |
1753 | } | |
1754 | ||
b0c39dc6 | 1755 | static int do_realtime(struct timespec *ts, u64 *tsc_timestamp) |
55dd00a7 MT |
1756 | { |
1757 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
1758 | unsigned long seq; | |
1759 | int mode; | |
1760 | u64 ns; | |
1761 | ||
1762 | do { | |
1763 | seq = read_seqcount_begin(>od->seq); | |
55dd00a7 MT |
1764 | ts->tv_sec = gtod->wall_time_sec; |
1765 | ns = gtod->nsec_base; | |
b0c39dc6 | 1766 | ns += vgettsc(tsc_timestamp, &mode); |
55dd00a7 MT |
1767 | ns >>= gtod->clock.shift; |
1768 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); | |
1769 | ||
1770 | ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); | |
1771 | ts->tv_nsec = ns; | |
1772 | ||
1773 | return mode; | |
1774 | } | |
1775 | ||
b0c39dc6 VK |
1776 | /* returns true if host is using TSC based clocksource */ |
1777 | static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) | |
d828199e | 1778 | { |
d828199e | 1779 | /* checked again under seqlock below */ |
b0c39dc6 | 1780 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
d828199e MT |
1781 | return false; |
1782 | ||
b0c39dc6 VK |
1783 | return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns, |
1784 | tsc_timestamp)); | |
d828199e | 1785 | } |
55dd00a7 | 1786 | |
b0c39dc6 | 1787 | /* returns true if host is using TSC based clocksource */ |
55dd00a7 | 1788 | static bool kvm_get_walltime_and_clockread(struct timespec *ts, |
b0c39dc6 | 1789 | u64 *tsc_timestamp) |
55dd00a7 MT |
1790 | { |
1791 | /* checked again under seqlock below */ | |
b0c39dc6 | 1792 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
55dd00a7 MT |
1793 | return false; |
1794 | ||
b0c39dc6 | 1795 | return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); |
55dd00a7 | 1796 | } |
d828199e MT |
1797 | #endif |
1798 | ||
1799 | /* | |
1800 | * | |
b48aa97e MT |
1801 | * Assuming a stable TSC across physical CPUS, and a stable TSC |
1802 | * across virtual CPUs, the following condition is possible. | |
1803 | * Each numbered line represents an event visible to both | |
d828199e MT |
1804 | * CPUs at the next numbered event. |
1805 | * | |
1806 | * "timespecX" represents host monotonic time. "tscX" represents | |
1807 | * RDTSC value. | |
1808 | * | |
1809 | * VCPU0 on CPU0 | VCPU1 on CPU1 | |
1810 | * | |
1811 | * 1. read timespec0,tsc0 | |
1812 | * 2. | timespec1 = timespec0 + N | |
1813 | * | tsc1 = tsc0 + M | |
1814 | * 3. transition to guest | transition to guest | |
1815 | * 4. ret0 = timespec0 + (rdtsc - tsc0) | | |
1816 | * 5. | ret1 = timespec1 + (rdtsc - tsc1) | |
1817 | * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) | |
1818 | * | |
1819 | * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: | |
1820 | * | |
1821 | * - ret0 < ret1 | |
1822 | * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) | |
1823 | * ... | |
1824 | * - 0 < N - M => M < N | |
1825 | * | |
1826 | * That is, when timespec0 != timespec1, M < N. Unfortunately that is not | |
1827 | * always the case (the difference between two distinct xtime instances | |
1828 | * might be smaller then the difference between corresponding TSC reads, | |
1829 | * when updating guest vcpus pvclock areas). | |
1830 | * | |
1831 | * To avoid that problem, do not allow visibility of distinct | |
1832 | * system_timestamp/tsc_timestamp values simultaneously: use a master | |
1833 | * copy of host monotonic time values. Update that master copy | |
1834 | * in lockstep. | |
1835 | * | |
b48aa97e | 1836 | * Rely on synchronization of host TSCs and guest TSCs for monotonicity. |
d828199e MT |
1837 | * |
1838 | */ | |
1839 | ||
1840 | static void pvclock_update_vm_gtod_copy(struct kvm *kvm) | |
1841 | { | |
1842 | #ifdef CONFIG_X86_64 | |
1843 | struct kvm_arch *ka = &kvm->arch; | |
1844 | int vclock_mode; | |
b48aa97e MT |
1845 | bool host_tsc_clocksource, vcpus_matched; |
1846 | ||
1847 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
1848 | atomic_read(&kvm->online_vcpus)); | |
d828199e MT |
1849 | |
1850 | /* | |
1851 | * If the host uses TSC clock, then passthrough TSC as stable | |
1852 | * to the guest. | |
1853 | */ | |
b48aa97e | 1854 | host_tsc_clocksource = kvm_get_time_and_clockread( |
d828199e MT |
1855 | &ka->master_kernel_ns, |
1856 | &ka->master_cycle_now); | |
1857 | ||
16a96021 | 1858 | ka->use_master_clock = host_tsc_clocksource && vcpus_matched |
a826faf1 | 1859 | && !ka->backwards_tsc_observed |
54750f2c | 1860 | && !ka->boot_vcpu_runs_old_kvmclock; |
b48aa97e | 1861 | |
d828199e MT |
1862 | if (ka->use_master_clock) |
1863 | atomic_set(&kvm_guest_has_master_clock, 1); | |
1864 | ||
1865 | vclock_mode = pvclock_gtod_data.clock.vclock_mode; | |
b48aa97e MT |
1866 | trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, |
1867 | vcpus_matched); | |
d828199e MT |
1868 | #endif |
1869 | } | |
1870 | ||
2860c4b1 PB |
1871 | void kvm_make_mclock_inprogress_request(struct kvm *kvm) |
1872 | { | |
1873 | kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); | |
1874 | } | |
1875 | ||
2e762ff7 MT |
1876 | static void kvm_gen_update_masterclock(struct kvm *kvm) |
1877 | { | |
1878 | #ifdef CONFIG_X86_64 | |
1879 | int i; | |
1880 | struct kvm_vcpu *vcpu; | |
1881 | struct kvm_arch *ka = &kvm->arch; | |
1882 | ||
1883 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
1884 | kvm_make_mclock_inprogress_request(kvm); | |
1885 | /* no guest entries from this point */ | |
1886 | pvclock_update_vm_gtod_copy(kvm); | |
1887 | ||
1888 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 1889 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
2e762ff7 MT |
1890 | |
1891 | /* guest entries allowed */ | |
1892 | kvm_for_each_vcpu(i, vcpu, kvm) | |
72875d8a | 1893 | kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); |
2e762ff7 MT |
1894 | |
1895 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
1896 | #endif | |
1897 | } | |
1898 | ||
e891a32e | 1899 | u64 get_kvmclock_ns(struct kvm *kvm) |
108b249c | 1900 | { |
108b249c | 1901 | struct kvm_arch *ka = &kvm->arch; |
8b953440 | 1902 | struct pvclock_vcpu_time_info hv_clock; |
e2c2206a | 1903 | u64 ret; |
108b249c | 1904 | |
8b953440 PB |
1905 | spin_lock(&ka->pvclock_gtod_sync_lock); |
1906 | if (!ka->use_master_clock) { | |
1907 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
1908 | return ktime_get_boot_ns() + ka->kvmclock_offset; | |
108b249c PB |
1909 | } |
1910 | ||
8b953440 PB |
1911 | hv_clock.tsc_timestamp = ka->master_cycle_now; |
1912 | hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; | |
1913 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
1914 | ||
e2c2206a WL |
1915 | /* both __this_cpu_read() and rdtsc() should be on the same cpu */ |
1916 | get_cpu(); | |
1917 | ||
e70b57a6 WL |
1918 | if (__this_cpu_read(cpu_tsc_khz)) { |
1919 | kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, | |
1920 | &hv_clock.tsc_shift, | |
1921 | &hv_clock.tsc_to_system_mul); | |
1922 | ret = __pvclock_read_cycles(&hv_clock, rdtsc()); | |
1923 | } else | |
1924 | ret = ktime_get_boot_ns() + ka->kvmclock_offset; | |
e2c2206a WL |
1925 | |
1926 | put_cpu(); | |
1927 | ||
1928 | return ret; | |
108b249c PB |
1929 | } |
1930 | ||
0d6dd2ff PB |
1931 | static void kvm_setup_pvclock_page(struct kvm_vcpu *v) |
1932 | { | |
1933 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
1934 | struct pvclock_vcpu_time_info guest_hv_clock; | |
1935 | ||
4e335d9e | 1936 | if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, |
0d6dd2ff PB |
1937 | &guest_hv_clock, sizeof(guest_hv_clock)))) |
1938 | return; | |
1939 | ||
1940 | /* This VCPU is paused, but it's legal for a guest to read another | |
1941 | * VCPU's kvmclock, so we really have to follow the specification where | |
1942 | * it says that version is odd if data is being modified, and even after | |
1943 | * it is consistent. | |
1944 | * | |
1945 | * Version field updates must be kept separate. This is because | |
1946 | * kvm_write_guest_cached might use a "rep movs" instruction, and | |
1947 | * writes within a string instruction are weakly ordered. So there | |
1948 | * are three writes overall. | |
1949 | * | |
1950 | * As a small optimization, only write the version field in the first | |
1951 | * and third write. The vcpu->pv_time cache is still valid, because the | |
1952 | * version field is the first in the struct. | |
1953 | */ | |
1954 | BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); | |
1955 | ||
51c4b8bb LA |
1956 | if (guest_hv_clock.version & 1) |
1957 | ++guest_hv_clock.version; /* first time write, random junk */ | |
1958 | ||
0d6dd2ff | 1959 | vcpu->hv_clock.version = guest_hv_clock.version + 1; |
4e335d9e PB |
1960 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
1961 | &vcpu->hv_clock, | |
1962 | sizeof(vcpu->hv_clock.version)); | |
0d6dd2ff PB |
1963 | |
1964 | smp_wmb(); | |
1965 | ||
1966 | /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ | |
1967 | vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); | |
1968 | ||
1969 | if (vcpu->pvclock_set_guest_stopped_request) { | |
1970 | vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; | |
1971 | vcpu->pvclock_set_guest_stopped_request = false; | |
1972 | } | |
1973 | ||
1974 | trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); | |
1975 | ||
4e335d9e PB |
1976 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
1977 | &vcpu->hv_clock, | |
1978 | sizeof(vcpu->hv_clock)); | |
0d6dd2ff PB |
1979 | |
1980 | smp_wmb(); | |
1981 | ||
1982 | vcpu->hv_clock.version++; | |
4e335d9e PB |
1983 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
1984 | &vcpu->hv_clock, | |
1985 | sizeof(vcpu->hv_clock.version)); | |
0d6dd2ff PB |
1986 | } |
1987 | ||
34c238a1 | 1988 | static int kvm_guest_time_update(struct kvm_vcpu *v) |
18068523 | 1989 | { |
78db6a50 | 1990 | unsigned long flags, tgt_tsc_khz; |
18068523 | 1991 | struct kvm_vcpu_arch *vcpu = &v->arch; |
d828199e | 1992 | struct kvm_arch *ka = &v->kvm->arch; |
f25e656d | 1993 | s64 kernel_ns; |
d828199e | 1994 | u64 tsc_timestamp, host_tsc; |
51d59c6b | 1995 | u8 pvclock_flags; |
d828199e MT |
1996 | bool use_master_clock; |
1997 | ||
1998 | kernel_ns = 0; | |
1999 | host_tsc = 0; | |
18068523 | 2000 | |
d828199e MT |
2001 | /* |
2002 | * If the host uses TSC clock, then passthrough TSC as stable | |
2003 | * to the guest. | |
2004 | */ | |
2005 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
2006 | use_master_clock = ka->use_master_clock; | |
2007 | if (use_master_clock) { | |
2008 | host_tsc = ka->master_cycle_now; | |
2009 | kernel_ns = ka->master_kernel_ns; | |
2010 | } | |
2011 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
c09664bb MT |
2012 | |
2013 | /* Keep irq disabled to prevent changes to the clock */ | |
2014 | local_irq_save(flags); | |
78db6a50 PB |
2015 | tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); |
2016 | if (unlikely(tgt_tsc_khz == 0)) { | |
c09664bb MT |
2017 | local_irq_restore(flags); |
2018 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); | |
2019 | return 1; | |
2020 | } | |
d828199e | 2021 | if (!use_master_clock) { |
4ea1636b | 2022 | host_tsc = rdtsc(); |
108b249c | 2023 | kernel_ns = ktime_get_boot_ns(); |
d828199e MT |
2024 | } |
2025 | ||
4ba76538 | 2026 | tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); |
d828199e | 2027 | |
c285545f ZA |
2028 | /* |
2029 | * We may have to catch up the TSC to match elapsed wall clock | |
2030 | * time for two reasons, even if kvmclock is used. | |
2031 | * 1) CPU could have been running below the maximum TSC rate | |
2032 | * 2) Broken TSC compensation resets the base at each VCPU | |
2033 | * entry to avoid unknown leaps of TSC even when running | |
2034 | * again on the same CPU. This may cause apparent elapsed | |
2035 | * time to disappear, and the guest to stand still or run | |
2036 | * very slowly. | |
2037 | */ | |
2038 | if (vcpu->tsc_catchup) { | |
2039 | u64 tsc = compute_guest_tsc(v, kernel_ns); | |
2040 | if (tsc > tsc_timestamp) { | |
f1e2b260 | 2041 | adjust_tsc_offset_guest(v, tsc - tsc_timestamp); |
c285545f ZA |
2042 | tsc_timestamp = tsc; |
2043 | } | |
50d0a0f9 GH |
2044 | } |
2045 | ||
18068523 GOC |
2046 | local_irq_restore(flags); |
2047 | ||
0d6dd2ff | 2048 | /* With all the info we got, fill in the values */ |
18068523 | 2049 | |
78db6a50 PB |
2050 | if (kvm_has_tsc_control) |
2051 | tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz); | |
2052 | ||
2053 | if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { | |
3ae13faa | 2054 | kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, |
5f4e3f88 ZA |
2055 | &vcpu->hv_clock.tsc_shift, |
2056 | &vcpu->hv_clock.tsc_to_system_mul); | |
78db6a50 | 2057 | vcpu->hw_tsc_khz = tgt_tsc_khz; |
8cfdc000 ZA |
2058 | } |
2059 | ||
1d5f066e | 2060 | vcpu->hv_clock.tsc_timestamp = tsc_timestamp; |
759379dd | 2061 | vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; |
28e4639a | 2062 | vcpu->last_guest_tsc = tsc_timestamp; |
51d59c6b | 2063 | |
d828199e | 2064 | /* If the host uses TSC clocksource, then it is stable */ |
0d6dd2ff | 2065 | pvclock_flags = 0; |
d828199e MT |
2066 | if (use_master_clock) |
2067 | pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; | |
2068 | ||
78c0337a MT |
2069 | vcpu->hv_clock.flags = pvclock_flags; |
2070 | ||
095cf55d PB |
2071 | if (vcpu->pv_time_enabled) |
2072 | kvm_setup_pvclock_page(v); | |
2073 | if (v == kvm_get_vcpu(v->kvm, 0)) | |
2074 | kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); | |
8cfdc000 | 2075 | return 0; |
c8076604 GH |
2076 | } |
2077 | ||
0061d53d MT |
2078 | /* |
2079 | * kvmclock updates which are isolated to a given vcpu, such as | |
2080 | * vcpu->cpu migration, should not allow system_timestamp from | |
2081 | * the rest of the vcpus to remain static. Otherwise ntp frequency | |
2082 | * correction applies to one vcpu's system_timestamp but not | |
2083 | * the others. | |
2084 | * | |
2085 | * So in those cases, request a kvmclock update for all vcpus. | |
7e44e449 AJ |
2086 | * We need to rate-limit these requests though, as they can |
2087 | * considerably slow guests that have a large number of vcpus. | |
2088 | * The time for a remote vcpu to update its kvmclock is bound | |
2089 | * by the delay we use to rate-limit the updates. | |
0061d53d MT |
2090 | */ |
2091 | ||
7e44e449 AJ |
2092 | #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) |
2093 | ||
2094 | static void kvmclock_update_fn(struct work_struct *work) | |
0061d53d MT |
2095 | { |
2096 | int i; | |
7e44e449 AJ |
2097 | struct delayed_work *dwork = to_delayed_work(work); |
2098 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
2099 | kvmclock_update_work); | |
2100 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
0061d53d MT |
2101 | struct kvm_vcpu *vcpu; |
2102 | ||
2103 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
105b21bb | 2104 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0061d53d MT |
2105 | kvm_vcpu_kick(vcpu); |
2106 | } | |
2107 | } | |
2108 | ||
7e44e449 AJ |
2109 | static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) |
2110 | { | |
2111 | struct kvm *kvm = v->kvm; | |
2112 | ||
105b21bb | 2113 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); |
7e44e449 AJ |
2114 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, |
2115 | KVMCLOCK_UPDATE_DELAY); | |
2116 | } | |
2117 | ||
332967a3 AJ |
2118 | #define KVMCLOCK_SYNC_PERIOD (300 * HZ) |
2119 | ||
2120 | static void kvmclock_sync_fn(struct work_struct *work) | |
2121 | { | |
2122 | struct delayed_work *dwork = to_delayed_work(work); | |
2123 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
2124 | kvmclock_sync_work); | |
2125 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
2126 | ||
630994b3 MT |
2127 | if (!kvmclock_periodic_sync) |
2128 | return; | |
2129 | ||
332967a3 AJ |
2130 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); |
2131 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
2132 | KVMCLOCK_SYNC_PERIOD); | |
2133 | } | |
2134 | ||
9ffd986c | 2135 | static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 2136 | { |
890ca9ae HY |
2137 | u64 mcg_cap = vcpu->arch.mcg_cap; |
2138 | unsigned bank_num = mcg_cap & 0xff; | |
9ffd986c WL |
2139 | u32 msr = msr_info->index; |
2140 | u64 data = msr_info->data; | |
890ca9ae | 2141 | |
15c4a640 | 2142 | switch (msr) { |
15c4a640 | 2143 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 2144 | vcpu->arch.mcg_status = data; |
15c4a640 | 2145 | break; |
c7ac679c | 2146 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
2147 | if (!(mcg_cap & MCG_CTL_P)) |
2148 | return 1; | |
2149 | if (data != 0 && data != ~(u64)0) | |
2150 | return -1; | |
2151 | vcpu->arch.mcg_ctl = data; | |
2152 | break; | |
2153 | default: | |
2154 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 2155 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
890ca9ae | 2156 | u32 offset = msr - MSR_IA32_MC0_CTL; |
114be429 AP |
2157 | /* only 0 or all 1s can be written to IA32_MCi_CTL |
2158 | * some Linux kernels though clear bit 10 in bank 4 to | |
2159 | * workaround a BIOS/GART TBL issue on AMD K8s, ignore | |
2160 | * this to avoid an uncatched #GP in the guest | |
2161 | */ | |
890ca9ae | 2162 | if ((offset & 0x3) == 0 && |
114be429 | 2163 | data != 0 && (data | (1 << 10)) != ~(u64)0) |
890ca9ae | 2164 | return -1; |
9ffd986c WL |
2165 | if (!msr_info->host_initiated && |
2166 | (offset & 0x3) == 1 && data != 0) | |
2167 | return -1; | |
890ca9ae HY |
2168 | vcpu->arch.mce_banks[offset] = data; |
2169 | break; | |
2170 | } | |
2171 | return 1; | |
2172 | } | |
2173 | return 0; | |
2174 | } | |
2175 | ||
ffde22ac ES |
2176 | static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) |
2177 | { | |
2178 | struct kvm *kvm = vcpu->kvm; | |
2179 | int lm = is_long_mode(vcpu); | |
2180 | u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 | |
2181 | : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; | |
2182 | u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 | |
2183 | : kvm->arch.xen_hvm_config.blob_size_32; | |
2184 | u32 page_num = data & ~PAGE_MASK; | |
2185 | u64 page_addr = data & PAGE_MASK; | |
2186 | u8 *page; | |
2187 | int r; | |
2188 | ||
2189 | r = -E2BIG; | |
2190 | if (page_num >= blob_size) | |
2191 | goto out; | |
2192 | r = -ENOMEM; | |
ff5c2c03 SL |
2193 | page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); |
2194 | if (IS_ERR(page)) { | |
2195 | r = PTR_ERR(page); | |
ffde22ac | 2196 | goto out; |
ff5c2c03 | 2197 | } |
54bf36aa | 2198 | if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) |
ffde22ac ES |
2199 | goto out_free; |
2200 | r = 0; | |
2201 | out_free: | |
2202 | kfree(page); | |
2203 | out: | |
2204 | return r; | |
2205 | } | |
2206 | ||
344d9588 GN |
2207 | static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) |
2208 | { | |
2209 | gpa_t gpa = data & ~0x3f; | |
2210 | ||
52a5c155 WL |
2211 | /* Bits 3:5 are reserved, Should be zero */ |
2212 | if (data & 0x38) | |
344d9588 GN |
2213 | return 1; |
2214 | ||
2215 | vcpu->arch.apf.msr_val = data; | |
2216 | ||
2217 | if (!(data & KVM_ASYNC_PF_ENABLED)) { | |
2218 | kvm_clear_async_pf_completion_queue(vcpu); | |
2219 | kvm_async_pf_hash_reset(vcpu); | |
2220 | return 0; | |
2221 | } | |
2222 | ||
4e335d9e | 2223 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, |
8f964525 | 2224 | sizeof(u32))) |
344d9588 GN |
2225 | return 1; |
2226 | ||
6adba527 | 2227 | vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); |
52a5c155 | 2228 | vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; |
344d9588 GN |
2229 | kvm_async_pf_wakeup_all(vcpu); |
2230 | return 0; | |
2231 | } | |
2232 | ||
12f9a48f GC |
2233 | static void kvmclock_reset(struct kvm_vcpu *vcpu) |
2234 | { | |
0b79459b | 2235 | vcpu->arch.pv_time_enabled = false; |
12f9a48f GC |
2236 | } |
2237 | ||
f38a7b75 WL |
2238 | static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa) |
2239 | { | |
2240 | ++vcpu->stat.tlb_flush; | |
2241 | kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa); | |
2242 | } | |
2243 | ||
c9aaa895 GC |
2244 | static void record_steal_time(struct kvm_vcpu *vcpu) |
2245 | { | |
2246 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) | |
2247 | return; | |
2248 | ||
4e335d9e | 2249 | if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, |
c9aaa895 GC |
2250 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) |
2251 | return; | |
2252 | ||
f38a7b75 WL |
2253 | /* |
2254 | * Doing a TLB flush here, on the guest's behalf, can avoid | |
2255 | * expensive IPIs. | |
2256 | */ | |
2257 | if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB) | |
2258 | kvm_vcpu_flush_tlb(vcpu, false); | |
0b9f6c46 | 2259 | |
35f3fae1 WL |
2260 | if (vcpu->arch.st.steal.version & 1) |
2261 | vcpu->arch.st.steal.version += 1; /* first time write, random junk */ | |
2262 | ||
2263 | vcpu->arch.st.steal.version += 1; | |
2264 | ||
4e335d9e | 2265 | kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, |
35f3fae1 WL |
2266 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); |
2267 | ||
2268 | smp_wmb(); | |
2269 | ||
c54cdf14 LC |
2270 | vcpu->arch.st.steal.steal += current->sched_info.run_delay - |
2271 | vcpu->arch.st.last_steal; | |
2272 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
35f3fae1 | 2273 | |
4e335d9e | 2274 | kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, |
35f3fae1 WL |
2275 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); |
2276 | ||
2277 | smp_wmb(); | |
2278 | ||
2279 | vcpu->arch.st.steal.version += 1; | |
c9aaa895 | 2280 | |
4e335d9e | 2281 | kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, |
c9aaa895 GC |
2282 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); |
2283 | } | |
2284 | ||
8fe8ab46 | 2285 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 2286 | { |
5753785f | 2287 | bool pr = false; |
8fe8ab46 WA |
2288 | u32 msr = msr_info->index; |
2289 | u64 data = msr_info->data; | |
5753785f | 2290 | |
15c4a640 | 2291 | switch (msr) { |
2e32b719 | 2292 | case MSR_AMD64_NB_CFG: |
2e32b719 BP |
2293 | case MSR_IA32_UCODE_WRITE: |
2294 | case MSR_VM_HSAVE_PA: | |
2295 | case MSR_AMD64_PATCH_LOADER: | |
2296 | case MSR_AMD64_BU_CFG2: | |
405a353a | 2297 | case MSR_AMD64_DC_CFG: |
2e32b719 BP |
2298 | break; |
2299 | ||
518e7b94 WL |
2300 | case MSR_IA32_UCODE_REV: |
2301 | if (msr_info->host_initiated) | |
2302 | vcpu->arch.microcode_version = data; | |
2303 | break; | |
15c4a640 | 2304 | case MSR_EFER: |
b69e8cae | 2305 | return set_efer(vcpu, data); |
8f1589d9 AP |
2306 | case MSR_K7_HWCR: |
2307 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
82494028 | 2308 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ |
a223c313 | 2309 | data &= ~(u64)0x8; /* ignore TLB cache disable */ |
22d48b2d | 2310 | data &= ~(u64)0x40000; /* ignore Mc status write enable */ |
8f1589d9 | 2311 | if (data != 0) { |
a737f256 CD |
2312 | vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", |
2313 | data); | |
8f1589d9 AP |
2314 | return 1; |
2315 | } | |
15c4a640 | 2316 | break; |
f7c6d140 AP |
2317 | case MSR_FAM10H_MMIO_CONF_BASE: |
2318 | if (data != 0) { | |
a737f256 CD |
2319 | vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " |
2320 | "0x%llx\n", data); | |
f7c6d140 AP |
2321 | return 1; |
2322 | } | |
15c4a640 | 2323 | break; |
b5e2fec0 AG |
2324 | case MSR_IA32_DEBUGCTLMSR: |
2325 | if (!data) { | |
2326 | /* We support the non-activated case already */ | |
2327 | break; | |
2328 | } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { | |
2329 | /* Values other than LBR and BTF are vendor-specific, | |
2330 | thus reserved and should throw a #GP */ | |
2331 | return 1; | |
2332 | } | |
a737f256 CD |
2333 | vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", |
2334 | __func__, data); | |
b5e2fec0 | 2335 | break; |
9ba075a6 | 2336 | case 0x200 ... 0x2ff: |
ff53604b | 2337 | return kvm_mtrr_set_msr(vcpu, msr, data); |
15c4a640 | 2338 | case MSR_IA32_APICBASE: |
58cb628d | 2339 | return kvm_set_apic_base(vcpu, msr_info); |
0105d1a5 GN |
2340 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
2341 | return kvm_x2apic_msr_write(vcpu, msr, data); | |
a3e06bbe LJ |
2342 | case MSR_IA32_TSCDEADLINE: |
2343 | kvm_set_lapic_tscdeadline_msr(vcpu, data); | |
2344 | break; | |
ba904635 | 2345 | case MSR_IA32_TSC_ADJUST: |
d6321d49 | 2346 | if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { |
ba904635 | 2347 | if (!msr_info->host_initiated) { |
d913b904 | 2348 | s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; |
d7add054 | 2349 | adjust_tsc_offset_guest(vcpu, adj); |
ba904635 WA |
2350 | } |
2351 | vcpu->arch.ia32_tsc_adjust_msr = data; | |
2352 | } | |
2353 | break; | |
15c4a640 | 2354 | case MSR_IA32_MISC_ENABLE: |
ad312c7c | 2355 | vcpu->arch.ia32_misc_enable_msr = data; |
15c4a640 | 2356 | break; |
64d60670 PB |
2357 | case MSR_IA32_SMBASE: |
2358 | if (!msr_info->host_initiated) | |
2359 | return 1; | |
2360 | vcpu->arch.smbase = data; | |
2361 | break; | |
52797bf9 LA |
2362 | case MSR_SMI_COUNT: |
2363 | if (!msr_info->host_initiated) | |
2364 | return 1; | |
2365 | vcpu->arch.smi_count = data; | |
2366 | break; | |
11c6bffa | 2367 | case MSR_KVM_WALL_CLOCK_NEW: |
18068523 GOC |
2368 | case MSR_KVM_WALL_CLOCK: |
2369 | vcpu->kvm->arch.wall_clock = data; | |
2370 | kvm_write_wall_clock(vcpu->kvm, data); | |
2371 | break; | |
11c6bffa | 2372 | case MSR_KVM_SYSTEM_TIME_NEW: |
18068523 | 2373 | case MSR_KVM_SYSTEM_TIME: { |
54750f2c MT |
2374 | struct kvm_arch *ka = &vcpu->kvm->arch; |
2375 | ||
12f9a48f | 2376 | kvmclock_reset(vcpu); |
18068523 | 2377 | |
54750f2c MT |
2378 | if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { |
2379 | bool tmp = (msr == MSR_KVM_SYSTEM_TIME); | |
2380 | ||
2381 | if (ka->boot_vcpu_runs_old_kvmclock != tmp) | |
1bd2009e | 2382 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
54750f2c MT |
2383 | |
2384 | ka->boot_vcpu_runs_old_kvmclock = tmp; | |
2385 | } | |
2386 | ||
18068523 | 2387 | vcpu->arch.time = data; |
0061d53d | 2388 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
18068523 GOC |
2389 | |
2390 | /* we verify if the enable bit is set... */ | |
2391 | if (!(data & 1)) | |
2392 | break; | |
2393 | ||
4e335d9e | 2394 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, |
8f964525 AH |
2395 | &vcpu->arch.pv_time, data & ~1ULL, |
2396 | sizeof(struct pvclock_vcpu_time_info))) | |
0b79459b AH |
2397 | vcpu->arch.pv_time_enabled = false; |
2398 | else | |
2399 | vcpu->arch.pv_time_enabled = true; | |
32cad84f | 2400 | |
18068523 GOC |
2401 | break; |
2402 | } | |
344d9588 GN |
2403 | case MSR_KVM_ASYNC_PF_EN: |
2404 | if (kvm_pv_enable_async_pf(vcpu, data)) | |
2405 | return 1; | |
2406 | break; | |
c9aaa895 GC |
2407 | case MSR_KVM_STEAL_TIME: |
2408 | ||
2409 | if (unlikely(!sched_info_on())) | |
2410 | return 1; | |
2411 | ||
2412 | if (data & KVM_STEAL_RESERVED_MASK) | |
2413 | return 1; | |
2414 | ||
4e335d9e | 2415 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, |
8f964525 AH |
2416 | data & KVM_STEAL_VALID_BITS, |
2417 | sizeof(struct kvm_steal_time))) | |
c9aaa895 GC |
2418 | return 1; |
2419 | ||
2420 | vcpu->arch.st.msr_val = data; | |
2421 | ||
2422 | if (!(data & KVM_MSR_ENABLED)) | |
2423 | break; | |
2424 | ||
c9aaa895 GC |
2425 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
2426 | ||
2427 | break; | |
ae7a2a3f MT |
2428 | case MSR_KVM_PV_EOI_EN: |
2429 | if (kvm_lapic_enable_pv_eoi(vcpu, data)) | |
2430 | return 1; | |
2431 | break; | |
c9aaa895 | 2432 | |
890ca9ae HY |
2433 | case MSR_IA32_MCG_CTL: |
2434 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 2435 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
9ffd986c | 2436 | return set_msr_mce(vcpu, msr_info); |
71db6023 | 2437 | |
6912ac32 WH |
2438 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: |
2439 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
2440 | pr = true; /* fall through */ | |
2441 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: | |
2442 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 2443 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 2444 | return kvm_pmu_set_msr(vcpu, msr_info); |
5753785f GN |
2445 | |
2446 | if (pr || data != 0) | |
a737f256 CD |
2447 | vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " |
2448 | "0x%x data 0x%llx\n", msr, data); | |
5753785f | 2449 | break; |
84e0cefa JS |
2450 | case MSR_K7_CLK_CTL: |
2451 | /* | |
2452 | * Ignore all writes to this no longer documented MSR. | |
2453 | * Writes are only relevant for old K7 processors, | |
2454 | * all pre-dating SVM, but a recommended workaround from | |
4a969980 | 2455 | * AMD for these chips. It is possible to specify the |
84e0cefa JS |
2456 | * affected processor models on the command line, hence |
2457 | * the need to ignore the workaround. | |
2458 | */ | |
2459 | break; | |
55cd8e5a | 2460 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
e7d9513b AS |
2461 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
2462 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 2463 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
2464 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
2465 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
2466 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
e7d9513b AS |
2467 | return kvm_hv_set_msr_common(vcpu, msr, data, |
2468 | msr_info->host_initiated); | |
91c9c3ed | 2469 | case MSR_IA32_BBL_CR_CTL3: |
2470 | /* Drop writes to this legacy MSR -- see rdmsr | |
2471 | * counterpart for further detail. | |
2472 | */ | |
fab0aa3b EM |
2473 | if (report_ignored_msrs) |
2474 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", | |
2475 | msr, data); | |
91c9c3ed | 2476 | break; |
2b036c6b | 2477 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 2478 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
2479 | return 1; |
2480 | vcpu->arch.osvw.length = data; | |
2481 | break; | |
2482 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 2483 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
2484 | return 1; |
2485 | vcpu->arch.osvw.status = data; | |
2486 | break; | |
db2336a8 KH |
2487 | case MSR_PLATFORM_INFO: |
2488 | if (!msr_info->host_initiated || | |
2489 | data & ~MSR_PLATFORM_INFO_CPUID_FAULT || | |
2490 | (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && | |
2491 | cpuid_fault_enabled(vcpu))) | |
2492 | return 1; | |
2493 | vcpu->arch.msr_platform_info = data; | |
2494 | break; | |
2495 | case MSR_MISC_FEATURES_ENABLES: | |
2496 | if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || | |
2497 | (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && | |
2498 | !supports_cpuid_fault(vcpu))) | |
2499 | return 1; | |
2500 | vcpu->arch.msr_misc_features_enables = data; | |
2501 | break; | |
15c4a640 | 2502 | default: |
ffde22ac ES |
2503 | if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) |
2504 | return xen_hvm_config(vcpu, data); | |
c6702c9d | 2505 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 2506 | return kvm_pmu_set_msr(vcpu, msr_info); |
ed85c068 | 2507 | if (!ignore_msrs) { |
ae0f5499 | 2508 | vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n", |
a737f256 | 2509 | msr, data); |
ed85c068 AP |
2510 | return 1; |
2511 | } else { | |
fab0aa3b EM |
2512 | if (report_ignored_msrs) |
2513 | vcpu_unimpl(vcpu, | |
2514 | "ignored wrmsr: 0x%x data 0x%llx\n", | |
2515 | msr, data); | |
ed85c068 AP |
2516 | break; |
2517 | } | |
15c4a640 CO |
2518 | } |
2519 | return 0; | |
2520 | } | |
2521 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
2522 | ||
2523 | ||
2524 | /* | |
2525 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
2526 | * Returns 0 on success, non-0 otherwise. | |
2527 | * Assumes vcpu_load() was already called. | |
2528 | */ | |
609e36d3 | 2529 | int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) |
15c4a640 | 2530 | { |
609e36d3 | 2531 | return kvm_x86_ops->get_msr(vcpu, msr); |
15c4a640 | 2532 | } |
ff651cb6 | 2533 | EXPORT_SYMBOL_GPL(kvm_get_msr); |
15c4a640 | 2534 | |
890ca9ae | 2535 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
15c4a640 CO |
2536 | { |
2537 | u64 data; | |
890ca9ae HY |
2538 | u64 mcg_cap = vcpu->arch.mcg_cap; |
2539 | unsigned bank_num = mcg_cap & 0xff; | |
15c4a640 CO |
2540 | |
2541 | switch (msr) { | |
15c4a640 CO |
2542 | case MSR_IA32_P5_MC_ADDR: |
2543 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
2544 | data = 0; |
2545 | break; | |
15c4a640 | 2546 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
2547 | data = vcpu->arch.mcg_cap; |
2548 | break; | |
c7ac679c | 2549 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
2550 | if (!(mcg_cap & MCG_CTL_P)) |
2551 | return 1; | |
2552 | data = vcpu->arch.mcg_ctl; | |
2553 | break; | |
2554 | case MSR_IA32_MCG_STATUS: | |
2555 | data = vcpu->arch.mcg_status; | |
2556 | break; | |
2557 | default: | |
2558 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 2559 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
890ca9ae HY |
2560 | u32 offset = msr - MSR_IA32_MC0_CTL; |
2561 | data = vcpu->arch.mce_banks[offset]; | |
2562 | break; | |
2563 | } | |
2564 | return 1; | |
2565 | } | |
2566 | *pdata = data; | |
2567 | return 0; | |
2568 | } | |
2569 | ||
609e36d3 | 2570 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
890ca9ae | 2571 | { |
609e36d3 | 2572 | switch (msr_info->index) { |
890ca9ae | 2573 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 2574 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
2575 | case MSR_IA32_DEBUGCTLMSR: |
2576 | case MSR_IA32_LASTBRANCHFROMIP: | |
2577 | case MSR_IA32_LASTBRANCHTOIP: | |
2578 | case MSR_IA32_LASTINTFROMIP: | |
2579 | case MSR_IA32_LASTINTTOIP: | |
60af2ecd | 2580 | case MSR_K8_SYSCFG: |
3afb1121 PB |
2581 | case MSR_K8_TSEG_ADDR: |
2582 | case MSR_K8_TSEG_MASK: | |
60af2ecd | 2583 | case MSR_K7_HWCR: |
61a6bd67 | 2584 | case MSR_VM_HSAVE_PA: |
1fdbd48c | 2585 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 2586 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 2587 | case MSR_FAM10H_MMIO_CONF_BASE: |
2e32b719 | 2588 | case MSR_AMD64_BU_CFG2: |
0c2df2a1 | 2589 | case MSR_IA32_PERF_CTL: |
405a353a | 2590 | case MSR_AMD64_DC_CFG: |
609e36d3 | 2591 | msr_info->data = 0; |
15c4a640 | 2592 | break; |
c51eb52b | 2593 | case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: |
6912ac32 WH |
2594 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: |
2595 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: | |
2596 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
2597 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 2598 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
609e36d3 PB |
2599 | return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); |
2600 | msr_info->data = 0; | |
5753785f | 2601 | break; |
742bc670 | 2602 | case MSR_IA32_UCODE_REV: |
518e7b94 | 2603 | msr_info->data = vcpu->arch.microcode_version; |
742bc670 | 2604 | break; |
9ba075a6 | 2605 | case MSR_MTRRcap: |
9ba075a6 | 2606 | case 0x200 ... 0x2ff: |
ff53604b | 2607 | return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); |
15c4a640 | 2608 | case 0xcd: /* fsb frequency */ |
609e36d3 | 2609 | msr_info->data = 3; |
15c4a640 | 2610 | break; |
7b914098 JS |
2611 | /* |
2612 | * MSR_EBC_FREQUENCY_ID | |
2613 | * Conservative value valid for even the basic CPU models. | |
2614 | * Models 0,1: 000 in bits 23:21 indicating a bus speed of | |
2615 | * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, | |
2616 | * and 266MHz for model 3, or 4. Set Core Clock | |
2617 | * Frequency to System Bus Frequency Ratio to 1 (bits | |
2618 | * 31:24) even though these are only valid for CPU | |
2619 | * models > 2, however guests may end up dividing or | |
2620 | * multiplying by zero otherwise. | |
2621 | */ | |
2622 | case MSR_EBC_FREQUENCY_ID: | |
609e36d3 | 2623 | msr_info->data = 1 << 24; |
7b914098 | 2624 | break; |
15c4a640 | 2625 | case MSR_IA32_APICBASE: |
609e36d3 | 2626 | msr_info->data = kvm_get_apic_base(vcpu); |
15c4a640 | 2627 | break; |
0105d1a5 | 2628 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
609e36d3 | 2629 | return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); |
0105d1a5 | 2630 | break; |
a3e06bbe | 2631 | case MSR_IA32_TSCDEADLINE: |
609e36d3 | 2632 | msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); |
a3e06bbe | 2633 | break; |
ba904635 | 2634 | case MSR_IA32_TSC_ADJUST: |
609e36d3 | 2635 | msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; |
ba904635 | 2636 | break; |
15c4a640 | 2637 | case MSR_IA32_MISC_ENABLE: |
609e36d3 | 2638 | msr_info->data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 2639 | break; |
64d60670 PB |
2640 | case MSR_IA32_SMBASE: |
2641 | if (!msr_info->host_initiated) | |
2642 | return 1; | |
2643 | msr_info->data = vcpu->arch.smbase; | |
15c4a640 | 2644 | break; |
52797bf9 LA |
2645 | case MSR_SMI_COUNT: |
2646 | msr_info->data = vcpu->arch.smi_count; | |
2647 | break; | |
847f0ad8 AG |
2648 | case MSR_IA32_PERF_STATUS: |
2649 | /* TSC increment by tick */ | |
609e36d3 | 2650 | msr_info->data = 1000ULL; |
847f0ad8 | 2651 | /* CPU multiplier */ |
b0996ae4 | 2652 | msr_info->data |= (((uint64_t)4ULL) << 40); |
847f0ad8 | 2653 | break; |
15c4a640 | 2654 | case MSR_EFER: |
609e36d3 | 2655 | msr_info->data = vcpu->arch.efer; |
15c4a640 | 2656 | break; |
18068523 | 2657 | case MSR_KVM_WALL_CLOCK: |
11c6bffa | 2658 | case MSR_KVM_WALL_CLOCK_NEW: |
609e36d3 | 2659 | msr_info->data = vcpu->kvm->arch.wall_clock; |
18068523 GOC |
2660 | break; |
2661 | case MSR_KVM_SYSTEM_TIME: | |
11c6bffa | 2662 | case MSR_KVM_SYSTEM_TIME_NEW: |
609e36d3 | 2663 | msr_info->data = vcpu->arch.time; |
18068523 | 2664 | break; |
344d9588 | 2665 | case MSR_KVM_ASYNC_PF_EN: |
609e36d3 | 2666 | msr_info->data = vcpu->arch.apf.msr_val; |
344d9588 | 2667 | break; |
c9aaa895 | 2668 | case MSR_KVM_STEAL_TIME: |
609e36d3 | 2669 | msr_info->data = vcpu->arch.st.msr_val; |
c9aaa895 | 2670 | break; |
1d92128f | 2671 | case MSR_KVM_PV_EOI_EN: |
609e36d3 | 2672 | msr_info->data = vcpu->arch.pv_eoi.msr_val; |
1d92128f | 2673 | break; |
890ca9ae HY |
2674 | case MSR_IA32_P5_MC_ADDR: |
2675 | case MSR_IA32_P5_MC_TYPE: | |
2676 | case MSR_IA32_MCG_CAP: | |
2677 | case MSR_IA32_MCG_CTL: | |
2678 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 2679 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
609e36d3 | 2680 | return get_msr_mce(vcpu, msr_info->index, &msr_info->data); |
84e0cefa JS |
2681 | case MSR_K7_CLK_CTL: |
2682 | /* | |
2683 | * Provide expected ramp-up count for K7. All other | |
2684 | * are set to zero, indicating minimum divisors for | |
2685 | * every field. | |
2686 | * | |
2687 | * This prevents guest kernels on AMD host with CPU | |
2688 | * type 6, model 8 and higher from exploding due to | |
2689 | * the rdmsr failing. | |
2690 | */ | |
609e36d3 | 2691 | msr_info->data = 0x20000000; |
84e0cefa | 2692 | break; |
55cd8e5a | 2693 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
e7d9513b AS |
2694 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
2695 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 2696 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
2697 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
2698 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
2699 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
e83d5887 AS |
2700 | return kvm_hv_get_msr_common(vcpu, |
2701 | msr_info->index, &msr_info->data); | |
55cd8e5a | 2702 | break; |
91c9c3ed | 2703 | case MSR_IA32_BBL_CR_CTL3: |
2704 | /* This legacy MSR exists but isn't fully documented in current | |
2705 | * silicon. It is however accessed by winxp in very narrow | |
2706 | * scenarios where it sets bit #19, itself documented as | |
2707 | * a "reserved" bit. Best effort attempt to source coherent | |
2708 | * read data here should the balance of the register be | |
2709 | * interpreted by the guest: | |
2710 | * | |
2711 | * L2 cache control register 3: 64GB range, 256KB size, | |
2712 | * enabled, latency 0x1, configured | |
2713 | */ | |
609e36d3 | 2714 | msr_info->data = 0xbe702111; |
91c9c3ed | 2715 | break; |
2b036c6b | 2716 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 2717 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 2718 | return 1; |
609e36d3 | 2719 | msr_info->data = vcpu->arch.osvw.length; |
2b036c6b BO |
2720 | break; |
2721 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 2722 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 2723 | return 1; |
609e36d3 | 2724 | msr_info->data = vcpu->arch.osvw.status; |
2b036c6b | 2725 | break; |
db2336a8 KH |
2726 | case MSR_PLATFORM_INFO: |
2727 | msr_info->data = vcpu->arch.msr_platform_info; | |
2728 | break; | |
2729 | case MSR_MISC_FEATURES_ENABLES: | |
2730 | msr_info->data = vcpu->arch.msr_misc_features_enables; | |
2731 | break; | |
15c4a640 | 2732 | default: |
c6702c9d | 2733 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
609e36d3 | 2734 | return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); |
ed85c068 | 2735 | if (!ignore_msrs) { |
ae0f5499 BD |
2736 | vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n", |
2737 | msr_info->index); | |
ed85c068 AP |
2738 | return 1; |
2739 | } else { | |
fab0aa3b EM |
2740 | if (report_ignored_msrs) |
2741 | vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", | |
2742 | msr_info->index); | |
609e36d3 | 2743 | msr_info->data = 0; |
ed85c068 AP |
2744 | } |
2745 | break; | |
15c4a640 | 2746 | } |
15c4a640 CO |
2747 | return 0; |
2748 | } | |
2749 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
2750 | ||
313a3dc7 CO |
2751 | /* |
2752 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
2753 | * | |
2754 | * @return number of msrs set successfully. | |
2755 | */ | |
2756 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
2757 | struct kvm_msr_entry *entries, | |
2758 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
2759 | unsigned index, u64 *data)) | |
2760 | { | |
801e459a | 2761 | int i; |
313a3dc7 | 2762 | |
313a3dc7 CO |
2763 | for (i = 0; i < msrs->nmsrs; ++i) |
2764 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
2765 | break; | |
2766 | ||
313a3dc7 CO |
2767 | return i; |
2768 | } | |
2769 | ||
2770 | /* | |
2771 | * Read or write a bunch of msrs. Parameters are user addresses. | |
2772 | * | |
2773 | * @return number of msrs set successfully. | |
2774 | */ | |
2775 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
2776 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
2777 | unsigned index, u64 *data), | |
2778 | int writeback) | |
2779 | { | |
2780 | struct kvm_msrs msrs; | |
2781 | struct kvm_msr_entry *entries; | |
2782 | int r, n; | |
2783 | unsigned size; | |
2784 | ||
2785 | r = -EFAULT; | |
2786 | if (copy_from_user(&msrs, user_msrs, sizeof msrs)) | |
2787 | goto out; | |
2788 | ||
2789 | r = -E2BIG; | |
2790 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
2791 | goto out; | |
2792 | ||
313a3dc7 | 2793 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; |
ff5c2c03 SL |
2794 | entries = memdup_user(user_msrs->entries, size); |
2795 | if (IS_ERR(entries)) { | |
2796 | r = PTR_ERR(entries); | |
313a3dc7 | 2797 | goto out; |
ff5c2c03 | 2798 | } |
313a3dc7 CO |
2799 | |
2800 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
2801 | if (r < 0) | |
2802 | goto out_free; | |
2803 | ||
2804 | r = -EFAULT; | |
2805 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
2806 | goto out_free; | |
2807 | ||
2808 | r = n; | |
2809 | ||
2810 | out_free: | |
7a73c028 | 2811 | kfree(entries); |
313a3dc7 CO |
2812 | out: |
2813 | return r; | |
2814 | } | |
2815 | ||
4d5422ce WL |
2816 | static inline bool kvm_can_mwait_in_guest(void) |
2817 | { | |
2818 | return boot_cpu_has(X86_FEATURE_MWAIT) && | |
2819 | !boot_cpu_has_bug(X86_BUG_MONITOR); | |
2820 | } | |
2821 | ||
784aa3d7 | 2822 | int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) |
018d00d2 | 2823 | { |
4d5422ce | 2824 | int r = 0; |
018d00d2 ZX |
2825 | |
2826 | switch (ext) { | |
2827 | case KVM_CAP_IRQCHIP: | |
2828 | case KVM_CAP_HLT: | |
2829 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 2830 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 2831 | case KVM_CAP_EXT_CPUID: |
9c15bb1d | 2832 | case KVM_CAP_EXT_EMUL_CPUID: |
c8076604 | 2833 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 2834 | case KVM_CAP_PIT: |
a28e4f5a | 2835 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 2836 | case KVM_CAP_MP_STATE: |
ed848624 | 2837 | case KVM_CAP_SYNC_MMU: |
a355c85c | 2838 | case KVM_CAP_USER_NMI: |
52d939a0 | 2839 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 2840 | case KVM_CAP_IRQ_INJECT_STATUS: |
d34e6b17 | 2841 | case KVM_CAP_IOEVENTFD: |
f848a5a8 | 2842 | case KVM_CAP_IOEVENTFD_NO_LENGTH: |
c5ff41ce | 2843 | case KVM_CAP_PIT2: |
e9f42757 | 2844 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 2845 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
ffde22ac | 2846 | case KVM_CAP_XEN_HVM: |
3cfc3092 | 2847 | case KVM_CAP_VCPU_EVENTS: |
55cd8e5a | 2848 | case KVM_CAP_HYPERV: |
10388a07 | 2849 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 2850 | case KVM_CAP_HYPERV_SPIN: |
5c919412 | 2851 | case KVM_CAP_HYPERV_SYNIC: |
efc479e6 | 2852 | case KVM_CAP_HYPERV_SYNIC2: |
d3457c87 | 2853 | case KVM_CAP_HYPERV_VP_INDEX: |
faeb7833 | 2854 | case KVM_CAP_HYPERV_EVENTFD: |
ab9f4ecb | 2855 | case KVM_CAP_PCI_SEGMENT: |
a1efbe77 | 2856 | case KVM_CAP_DEBUGREGS: |
d2be1651 | 2857 | case KVM_CAP_X86_ROBUST_SINGLESTEP: |
2d5b5a66 | 2858 | case KVM_CAP_XSAVE: |
344d9588 | 2859 | case KVM_CAP_ASYNC_PF: |
92a1f12d | 2860 | case KVM_CAP_GET_TSC_KHZ: |
1c0b28c2 | 2861 | case KVM_CAP_KVMCLOCK_CTRL: |
4d8b81ab | 2862 | case KVM_CAP_READONLY_MEM: |
5f66b620 | 2863 | case KVM_CAP_HYPERV_TIME: |
100943c5 | 2864 | case KVM_CAP_IOAPIC_POLARITY_IGNORED: |
defcf51f | 2865 | case KVM_CAP_TSC_DEADLINE_TIMER: |
90de4a18 NA |
2866 | case KVM_CAP_ENABLE_CAP_VM: |
2867 | case KVM_CAP_DISABLE_QUIRKS: | |
d71ba788 | 2868 | case KVM_CAP_SET_BOOT_CPU_ID: |
49df6397 | 2869 | case KVM_CAP_SPLIT_IRQCHIP: |
460df4c1 | 2870 | case KVM_CAP_IMMEDIATE_EXIT: |
801e459a | 2871 | case KVM_CAP_GET_MSR_FEATURES: |
018d00d2 ZX |
2872 | r = 1; |
2873 | break; | |
01643c51 KH |
2874 | case KVM_CAP_SYNC_REGS: |
2875 | r = KVM_SYNC_X86_VALID_FIELDS; | |
2876 | break; | |
e3fd9a93 PB |
2877 | case KVM_CAP_ADJUST_CLOCK: |
2878 | r = KVM_CLOCK_TSC_STABLE; | |
2879 | break; | |
4d5422ce | 2880 | case KVM_CAP_X86_DISABLE_EXITS: |
b31c114b | 2881 | r |= KVM_X86_DISABLE_EXITS_HTL | KVM_X86_DISABLE_EXITS_PAUSE; |
4d5422ce WL |
2882 | if(kvm_can_mwait_in_guest()) |
2883 | r |= KVM_X86_DISABLE_EXITS_MWAIT; | |
668fffa3 | 2884 | break; |
6d396b55 PB |
2885 | case KVM_CAP_X86_SMM: |
2886 | /* SMBASE is usually relocated above 1M on modern chipsets, | |
2887 | * and SMM handlers might indeed rely on 4G segment limits, | |
2888 | * so do not report SMM to be available if real mode is | |
2889 | * emulated via vm86 mode. Still, do not go to great lengths | |
2890 | * to avoid userspace's usage of the feature, because it is a | |
2891 | * fringe case that is not enabled except via specific settings | |
2892 | * of the module parameters. | |
2893 | */ | |
2894 | r = kvm_x86_ops->cpu_has_high_real_mode_segbase(); | |
2895 | break; | |
774ead3a AK |
2896 | case KVM_CAP_VAPIC: |
2897 | r = !kvm_x86_ops->cpu_has_accelerated_tpr(); | |
2898 | break; | |
f725230a | 2899 | case KVM_CAP_NR_VCPUS: |
8c3ba334 SL |
2900 | r = KVM_SOFT_MAX_VCPUS; |
2901 | break; | |
2902 | case KVM_CAP_MAX_VCPUS: | |
f725230a AK |
2903 | r = KVM_MAX_VCPUS; |
2904 | break; | |
a988b910 | 2905 | case KVM_CAP_NR_MEMSLOTS: |
bbacc0c1 | 2906 | r = KVM_USER_MEM_SLOTS; |
a988b910 | 2907 | break; |
a68a6a72 MT |
2908 | case KVM_CAP_PV_MMU: /* obsolete */ |
2909 | r = 0; | |
2f333bcb | 2910 | break; |
890ca9ae HY |
2911 | case KVM_CAP_MCE: |
2912 | r = KVM_MAX_MCE_BANKS; | |
2913 | break; | |
2d5b5a66 | 2914 | case KVM_CAP_XCRS: |
d366bf7e | 2915 | r = boot_cpu_has(X86_FEATURE_XSAVE); |
2d5b5a66 | 2916 | break; |
92a1f12d JR |
2917 | case KVM_CAP_TSC_CONTROL: |
2918 | r = kvm_has_tsc_control; | |
2919 | break; | |
37131313 RK |
2920 | case KVM_CAP_X2APIC_API: |
2921 | r = KVM_X2APIC_API_VALID_FLAGS; | |
2922 | break; | |
018d00d2 | 2923 | default: |
018d00d2 ZX |
2924 | break; |
2925 | } | |
2926 | return r; | |
2927 | ||
2928 | } | |
2929 | ||
043405e1 CO |
2930 | long kvm_arch_dev_ioctl(struct file *filp, |
2931 | unsigned int ioctl, unsigned long arg) | |
2932 | { | |
2933 | void __user *argp = (void __user *)arg; | |
2934 | long r; | |
2935 | ||
2936 | switch (ioctl) { | |
2937 | case KVM_GET_MSR_INDEX_LIST: { | |
2938 | struct kvm_msr_list __user *user_msr_list = argp; | |
2939 | struct kvm_msr_list msr_list; | |
2940 | unsigned n; | |
2941 | ||
2942 | r = -EFAULT; | |
2943 | if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) | |
2944 | goto out; | |
2945 | n = msr_list.nmsrs; | |
62ef68bb | 2946 | msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; |
043405e1 CO |
2947 | if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) |
2948 | goto out; | |
2949 | r = -E2BIG; | |
e125e7b6 | 2950 | if (n < msr_list.nmsrs) |
043405e1 CO |
2951 | goto out; |
2952 | r = -EFAULT; | |
2953 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
2954 | num_msrs_to_save * sizeof(u32))) | |
2955 | goto out; | |
e125e7b6 | 2956 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 | 2957 | &emulated_msrs, |
62ef68bb | 2958 | num_emulated_msrs * sizeof(u32))) |
043405e1 CO |
2959 | goto out; |
2960 | r = 0; | |
2961 | break; | |
2962 | } | |
9c15bb1d BP |
2963 | case KVM_GET_SUPPORTED_CPUID: |
2964 | case KVM_GET_EMULATED_CPUID: { | |
674eea0f AK |
2965 | struct kvm_cpuid2 __user *cpuid_arg = argp; |
2966 | struct kvm_cpuid2 cpuid; | |
2967 | ||
2968 | r = -EFAULT; | |
2969 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2970 | goto out; | |
9c15bb1d BP |
2971 | |
2972 | r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, | |
2973 | ioctl); | |
674eea0f AK |
2974 | if (r) |
2975 | goto out; | |
2976 | ||
2977 | r = -EFAULT; | |
2978 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
2979 | goto out; | |
2980 | r = 0; | |
2981 | break; | |
2982 | } | |
890ca9ae | 2983 | case KVM_X86_GET_MCE_CAP_SUPPORTED: { |
890ca9ae | 2984 | r = -EFAULT; |
c45dcc71 AR |
2985 | if (copy_to_user(argp, &kvm_mce_cap_supported, |
2986 | sizeof(kvm_mce_cap_supported))) | |
890ca9ae HY |
2987 | goto out; |
2988 | r = 0; | |
2989 | break; | |
801e459a TL |
2990 | case KVM_GET_MSR_FEATURE_INDEX_LIST: { |
2991 | struct kvm_msr_list __user *user_msr_list = argp; | |
2992 | struct kvm_msr_list msr_list; | |
2993 | unsigned int n; | |
2994 | ||
2995 | r = -EFAULT; | |
2996 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) | |
2997 | goto out; | |
2998 | n = msr_list.nmsrs; | |
2999 | msr_list.nmsrs = num_msr_based_features; | |
3000 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) | |
3001 | goto out; | |
3002 | r = -E2BIG; | |
3003 | if (n < msr_list.nmsrs) | |
3004 | goto out; | |
3005 | r = -EFAULT; | |
3006 | if (copy_to_user(user_msr_list->indices, &msr_based_features, | |
3007 | num_msr_based_features * sizeof(u32))) | |
3008 | goto out; | |
3009 | r = 0; | |
3010 | break; | |
3011 | } | |
3012 | case KVM_GET_MSRS: | |
3013 | r = msr_io(NULL, argp, do_get_msr_feature, 1); | |
3014 | break; | |
890ca9ae | 3015 | } |
043405e1 CO |
3016 | default: |
3017 | r = -EINVAL; | |
3018 | } | |
3019 | out: | |
3020 | return r; | |
3021 | } | |
3022 | ||
f5f48ee1 SY |
3023 | static void wbinvd_ipi(void *garbage) |
3024 | { | |
3025 | wbinvd(); | |
3026 | } | |
3027 | ||
3028 | static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
3029 | { | |
e0f0bbc5 | 3030 | return kvm_arch_has_noncoherent_dma(vcpu->kvm); |
f5f48ee1 SY |
3031 | } |
3032 | ||
313a3dc7 CO |
3033 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
3034 | { | |
f5f48ee1 SY |
3035 | /* Address WBINVD may be executed by guest */ |
3036 | if (need_emulate_wbinvd(vcpu)) { | |
3037 | if (kvm_x86_ops->has_wbinvd_exit()) | |
3038 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
3039 | else if (vcpu->cpu != -1 && vcpu->cpu != cpu) | |
3040 | smp_call_function_single(vcpu->cpu, | |
3041 | wbinvd_ipi, NULL, 1); | |
3042 | } | |
3043 | ||
313a3dc7 | 3044 | kvm_x86_ops->vcpu_load(vcpu, cpu); |
8f6055cb | 3045 | |
0dd6a6ed ZA |
3046 | /* Apply any externally detected TSC adjustments (due to suspend) */ |
3047 | if (unlikely(vcpu->arch.tsc_offset_adjustment)) { | |
3048 | adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); | |
3049 | vcpu->arch.tsc_offset_adjustment = 0; | |
105b21bb | 3050 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed | 3051 | } |
8f6055cb | 3052 | |
b0c39dc6 | 3053 | if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { |
6f526ec5 | 3054 | s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : |
4ea1636b | 3055 | rdtsc() - vcpu->arch.last_host_tsc; |
e48672fa ZA |
3056 | if (tsc_delta < 0) |
3057 | mark_tsc_unstable("KVM discovered backwards TSC"); | |
ce7a058a | 3058 | |
b0c39dc6 | 3059 | if (kvm_check_tsc_unstable()) { |
07c1419a | 3060 | u64 offset = kvm_compute_tsc_offset(vcpu, |
b183aa58 | 3061 | vcpu->arch.last_guest_tsc); |
a545ab6a | 3062 | kvm_vcpu_write_tsc_offset(vcpu, offset); |
c285545f | 3063 | vcpu->arch.tsc_catchup = 1; |
c285545f | 3064 | } |
a749e247 PB |
3065 | |
3066 | if (kvm_lapic_hv_timer_in_use(vcpu)) | |
3067 | kvm_lapic_restart_hv_timer(vcpu); | |
3068 | ||
d98d07ca MT |
3069 | /* |
3070 | * On a host with synchronized TSC, there is no need to update | |
3071 | * kvmclock on vcpu->cpu migration | |
3072 | */ | |
3073 | if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) | |
0061d53d | 3074 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
c285545f | 3075 | if (vcpu->cpu != cpu) |
1bd2009e | 3076 | kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); |
e48672fa | 3077 | vcpu->cpu = cpu; |
6b7d7e76 | 3078 | } |
c9aaa895 | 3079 | |
c9aaa895 | 3080 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
313a3dc7 CO |
3081 | } |
3082 | ||
0b9f6c46 PX |
3083 | static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) |
3084 | { | |
3085 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) | |
3086 | return; | |
3087 | ||
fa55eedd | 3088 | vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED; |
0b9f6c46 | 3089 | |
4e335d9e | 3090 | kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime, |
0b9f6c46 PX |
3091 | &vcpu->arch.st.steal.preempted, |
3092 | offsetof(struct kvm_steal_time, preempted), | |
3093 | sizeof(vcpu->arch.st.steal.preempted)); | |
3094 | } | |
3095 | ||
313a3dc7 CO |
3096 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) |
3097 | { | |
cc0d907c | 3098 | int idx; |
de63ad4c LM |
3099 | |
3100 | if (vcpu->preempted) | |
3101 | vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu); | |
3102 | ||
931f261b AA |
3103 | /* |
3104 | * Disable page faults because we're in atomic context here. | |
3105 | * kvm_write_guest_offset_cached() would call might_fault() | |
3106 | * that relies on pagefault_disable() to tell if there's a | |
3107 | * bug. NOTE: the write to guest memory may not go through if | |
3108 | * during postcopy live migration or if there's heavy guest | |
3109 | * paging. | |
3110 | */ | |
3111 | pagefault_disable(); | |
cc0d907c AA |
3112 | /* |
3113 | * kvm_memslots() will be called by | |
3114 | * kvm_write_guest_offset_cached() so take the srcu lock. | |
3115 | */ | |
3116 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
0b9f6c46 | 3117 | kvm_steal_time_set_preempted(vcpu); |
cc0d907c | 3118 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
931f261b | 3119 | pagefault_enable(); |
02daab21 | 3120 | kvm_x86_ops->vcpu_put(vcpu); |
4ea1636b | 3121 | vcpu->arch.last_host_tsc = rdtsc(); |
efdab992 WL |
3122 | /* |
3123 | * If userspace has set any breakpoints or watchpoints, dr6 is restored | |
3124 | * on every vmexit, but if not, we might have a stale dr6 from the | |
3125 | * guest. do_debug expects dr6 to be cleared after it runs, do the same. | |
3126 | */ | |
3127 | set_debugreg(0, 6); | |
313a3dc7 CO |
3128 | } |
3129 | ||
313a3dc7 CO |
3130 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
3131 | struct kvm_lapic_state *s) | |
3132 | { | |
fa59cc00 | 3133 | if (vcpu->arch.apicv_active) |
d62caabb AS |
3134 | kvm_x86_ops->sync_pir_to_irr(vcpu); |
3135 | ||
a92e2543 | 3136 | return kvm_apic_get_state(vcpu, s); |
313a3dc7 CO |
3137 | } |
3138 | ||
3139 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
3140 | struct kvm_lapic_state *s) | |
3141 | { | |
a92e2543 RK |
3142 | int r; |
3143 | ||
3144 | r = kvm_apic_set_state(vcpu, s); | |
3145 | if (r) | |
3146 | return r; | |
cb142eb7 | 3147 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
3148 | |
3149 | return 0; | |
3150 | } | |
3151 | ||
127a457a MG |
3152 | static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) |
3153 | { | |
3154 | return (!lapic_in_kernel(vcpu) || | |
3155 | kvm_apic_accept_pic_intr(vcpu)); | |
3156 | } | |
3157 | ||
782d422b MG |
3158 | /* |
3159 | * if userspace requested an interrupt window, check that the | |
3160 | * interrupt window is open. | |
3161 | * | |
3162 | * No need to exit to userspace if we already have an interrupt queued. | |
3163 | */ | |
3164 | static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) | |
3165 | { | |
3166 | return kvm_arch_interrupt_allowed(vcpu) && | |
3167 | !kvm_cpu_has_interrupt(vcpu) && | |
3168 | !kvm_event_needs_reinjection(vcpu) && | |
3169 | kvm_cpu_accept_dm_intr(vcpu); | |
3170 | } | |
3171 | ||
f77bc6a4 ZX |
3172 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
3173 | struct kvm_interrupt *irq) | |
3174 | { | |
02cdb50f | 3175 | if (irq->irq >= KVM_NR_INTERRUPTS) |
f77bc6a4 | 3176 | return -EINVAL; |
1c1a9ce9 SR |
3177 | |
3178 | if (!irqchip_in_kernel(vcpu->kvm)) { | |
3179 | kvm_queue_interrupt(vcpu, irq->irq, false); | |
3180 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
3181 | return 0; | |
3182 | } | |
3183 | ||
3184 | /* | |
3185 | * With in-kernel LAPIC, we only use this to inject EXTINT, so | |
3186 | * fail for in-kernel 8259. | |
3187 | */ | |
3188 | if (pic_in_kernel(vcpu->kvm)) | |
f77bc6a4 | 3189 | return -ENXIO; |
f77bc6a4 | 3190 | |
1c1a9ce9 SR |
3191 | if (vcpu->arch.pending_external_vector != -1) |
3192 | return -EEXIST; | |
f77bc6a4 | 3193 | |
1c1a9ce9 | 3194 | vcpu->arch.pending_external_vector = irq->irq; |
934bf653 | 3195 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f77bc6a4 ZX |
3196 | return 0; |
3197 | } | |
3198 | ||
c4abb7c9 JK |
3199 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
3200 | { | |
c4abb7c9 | 3201 | kvm_inject_nmi(vcpu); |
c4abb7c9 JK |
3202 | |
3203 | return 0; | |
3204 | } | |
3205 | ||
f077825a PB |
3206 | static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) |
3207 | { | |
64d60670 PB |
3208 | kvm_make_request(KVM_REQ_SMI, vcpu); |
3209 | ||
f077825a PB |
3210 | return 0; |
3211 | } | |
3212 | ||
b209749f AK |
3213 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
3214 | struct kvm_tpr_access_ctl *tac) | |
3215 | { | |
3216 | if (tac->flags) | |
3217 | return -EINVAL; | |
3218 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
3219 | return 0; | |
3220 | } | |
3221 | ||
890ca9ae HY |
3222 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
3223 | u64 mcg_cap) | |
3224 | { | |
3225 | int r; | |
3226 | unsigned bank_num = mcg_cap & 0xff, bank; | |
3227 | ||
3228 | r = -EINVAL; | |
a9e38c3e | 3229 | if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) |
890ca9ae | 3230 | goto out; |
c45dcc71 | 3231 | if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) |
890ca9ae HY |
3232 | goto out; |
3233 | r = 0; | |
3234 | vcpu->arch.mcg_cap = mcg_cap; | |
3235 | /* Init IA32_MCG_CTL to all 1s */ | |
3236 | if (mcg_cap & MCG_CTL_P) | |
3237 | vcpu->arch.mcg_ctl = ~(u64)0; | |
3238 | /* Init IA32_MCi_CTL to all 1s */ | |
3239 | for (bank = 0; bank < bank_num; bank++) | |
3240 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
c45dcc71 AR |
3241 | |
3242 | if (kvm_x86_ops->setup_mce) | |
3243 | kvm_x86_ops->setup_mce(vcpu); | |
890ca9ae HY |
3244 | out: |
3245 | return r; | |
3246 | } | |
3247 | ||
3248 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
3249 | struct kvm_x86_mce *mce) | |
3250 | { | |
3251 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
3252 | unsigned bank_num = mcg_cap & 0xff; | |
3253 | u64 *banks = vcpu->arch.mce_banks; | |
3254 | ||
3255 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
3256 | return -EINVAL; | |
3257 | /* | |
3258 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
3259 | * reporting is disabled | |
3260 | */ | |
3261 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
3262 | vcpu->arch.mcg_ctl != ~(u64)0) | |
3263 | return 0; | |
3264 | banks += 4 * mce->bank; | |
3265 | /* | |
3266 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
3267 | * reporting is disabled for the bank | |
3268 | */ | |
3269 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
3270 | return 0; | |
3271 | if (mce->status & MCI_STATUS_UC) { | |
3272 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
fc78f519 | 3273 | !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { |
a8eeb04a | 3274 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
890ca9ae HY |
3275 | return 0; |
3276 | } | |
3277 | if (banks[1] & MCI_STATUS_VAL) | |
3278 | mce->status |= MCI_STATUS_OVER; | |
3279 | banks[2] = mce->addr; | |
3280 | banks[3] = mce->misc; | |
3281 | vcpu->arch.mcg_status = mce->mcg_status; | |
3282 | banks[1] = mce->status; | |
3283 | kvm_queue_exception(vcpu, MC_VECTOR); | |
3284 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
3285 | || !(banks[1] & MCI_STATUS_UC)) { | |
3286 | if (banks[1] & MCI_STATUS_VAL) | |
3287 | mce->status |= MCI_STATUS_OVER; | |
3288 | banks[2] = mce->addr; | |
3289 | banks[3] = mce->misc; | |
3290 | banks[1] = mce->status; | |
3291 | } else | |
3292 | banks[1] |= MCI_STATUS_OVER; | |
3293 | return 0; | |
3294 | } | |
3295 | ||
3cfc3092 JK |
3296 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
3297 | struct kvm_vcpu_events *events) | |
3298 | { | |
7460fb4a | 3299 | process_nmi(vcpu); |
664f8e26 WL |
3300 | /* |
3301 | * FIXME: pass injected and pending separately. This is only | |
3302 | * needed for nested virtualization, whose state cannot be | |
3303 | * migrated yet. For now we can combine them. | |
3304 | */ | |
03b82a30 | 3305 | events->exception.injected = |
664f8e26 WL |
3306 | (vcpu->arch.exception.pending || |
3307 | vcpu->arch.exception.injected) && | |
03b82a30 | 3308 | !kvm_exception_is_soft(vcpu->arch.exception.nr); |
3cfc3092 JK |
3309 | events->exception.nr = vcpu->arch.exception.nr; |
3310 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
97e69aa6 | 3311 | events->exception.pad = 0; |
3cfc3092 JK |
3312 | events->exception.error_code = vcpu->arch.exception.error_code; |
3313 | ||
03b82a30 JK |
3314 | events->interrupt.injected = |
3315 | vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; | |
3cfc3092 | 3316 | events->interrupt.nr = vcpu->arch.interrupt.nr; |
03b82a30 | 3317 | events->interrupt.soft = 0; |
37ccdcbe | 3318 | events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); |
3cfc3092 JK |
3319 | |
3320 | events->nmi.injected = vcpu->arch.nmi_injected; | |
7460fb4a | 3321 | events->nmi.pending = vcpu->arch.nmi_pending != 0; |
3cfc3092 | 3322 | events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); |
97e69aa6 | 3323 | events->nmi.pad = 0; |
3cfc3092 | 3324 | |
66450a21 | 3325 | events->sipi_vector = 0; /* never valid when reporting to user space */ |
3cfc3092 | 3326 | |
f077825a PB |
3327 | events->smi.smm = is_smm(vcpu); |
3328 | events->smi.pending = vcpu->arch.smi_pending; | |
3329 | events->smi.smm_inside_nmi = | |
3330 | !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); | |
3331 | events->smi.latched_init = kvm_lapic_latched_init(vcpu); | |
3332 | ||
dab4b911 | 3333 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
f077825a PB |
3334 | | KVM_VCPUEVENT_VALID_SHADOW |
3335 | | KVM_VCPUEVENT_VALID_SMM); | |
97e69aa6 | 3336 | memset(&events->reserved, 0, sizeof(events->reserved)); |
3cfc3092 JK |
3337 | } |
3338 | ||
6ef4e07e XG |
3339 | static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags); |
3340 | ||
3cfc3092 JK |
3341 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, |
3342 | struct kvm_vcpu_events *events) | |
3343 | { | |
dab4b911 | 3344 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 | 3345 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
f077825a PB |
3346 | | KVM_VCPUEVENT_VALID_SHADOW |
3347 | | KVM_VCPUEVENT_VALID_SMM)) | |
3cfc3092 JK |
3348 | return -EINVAL; |
3349 | ||
78e546c8 | 3350 | if (events->exception.injected && |
28d06353 JM |
3351 | (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR || |
3352 | is_guest_mode(vcpu))) | |
78e546c8 PB |
3353 | return -EINVAL; |
3354 | ||
28bf2888 DH |
3355 | /* INITs are latched while in SMM */ |
3356 | if (events->flags & KVM_VCPUEVENT_VALID_SMM && | |
3357 | (events->smi.smm || events->smi.pending) && | |
3358 | vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) | |
3359 | return -EINVAL; | |
3360 | ||
7460fb4a | 3361 | process_nmi(vcpu); |
664f8e26 | 3362 | vcpu->arch.exception.injected = false; |
3cfc3092 JK |
3363 | vcpu->arch.exception.pending = events->exception.injected; |
3364 | vcpu->arch.exception.nr = events->exception.nr; | |
3365 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
3366 | vcpu->arch.exception.error_code = events->exception.error_code; | |
3367 | ||
3368 | vcpu->arch.interrupt.pending = events->interrupt.injected; | |
3369 | vcpu->arch.interrupt.nr = events->interrupt.nr; | |
3370 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
48005f64 JK |
3371 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) |
3372 | kvm_x86_ops->set_interrupt_shadow(vcpu, | |
3373 | events->interrupt.shadow); | |
3cfc3092 JK |
3374 | |
3375 | vcpu->arch.nmi_injected = events->nmi.injected; | |
dab4b911 JK |
3376 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) |
3377 | vcpu->arch.nmi_pending = events->nmi.pending; | |
3cfc3092 JK |
3378 | kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); |
3379 | ||
66450a21 | 3380 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && |
bce87cce | 3381 | lapic_in_kernel(vcpu)) |
66450a21 | 3382 | vcpu->arch.apic->sipi_vector = events->sipi_vector; |
3cfc3092 | 3383 | |
f077825a | 3384 | if (events->flags & KVM_VCPUEVENT_VALID_SMM) { |
6ef4e07e | 3385 | u32 hflags = vcpu->arch.hflags; |
f077825a | 3386 | if (events->smi.smm) |
6ef4e07e | 3387 | hflags |= HF_SMM_MASK; |
f077825a | 3388 | else |
6ef4e07e XG |
3389 | hflags &= ~HF_SMM_MASK; |
3390 | kvm_set_hflags(vcpu, hflags); | |
3391 | ||
f077825a | 3392 | vcpu->arch.smi_pending = events->smi.pending; |
f4ef1910 WL |
3393 | |
3394 | if (events->smi.smm) { | |
3395 | if (events->smi.smm_inside_nmi) | |
3396 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; | |
f077825a | 3397 | else |
f4ef1910 WL |
3398 | vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; |
3399 | if (lapic_in_kernel(vcpu)) { | |
3400 | if (events->smi.latched_init) | |
3401 | set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
3402 | else | |
3403 | clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
3404 | } | |
f077825a PB |
3405 | } |
3406 | } | |
3407 | ||
3842d135 AK |
3408 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
3409 | ||
3cfc3092 JK |
3410 | return 0; |
3411 | } | |
3412 | ||
a1efbe77 JK |
3413 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, |
3414 | struct kvm_debugregs *dbgregs) | |
3415 | { | |
73aaf249 JK |
3416 | unsigned long val; |
3417 | ||
a1efbe77 | 3418 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); |
16f8a6f9 | 3419 | kvm_get_dr(vcpu, 6, &val); |
73aaf249 | 3420 | dbgregs->dr6 = val; |
a1efbe77 JK |
3421 | dbgregs->dr7 = vcpu->arch.dr7; |
3422 | dbgregs->flags = 0; | |
97e69aa6 | 3423 | memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); |
a1efbe77 JK |
3424 | } |
3425 | ||
3426 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
3427 | struct kvm_debugregs *dbgregs) | |
3428 | { | |
3429 | if (dbgregs->flags) | |
3430 | return -EINVAL; | |
3431 | ||
d14bdb55 PB |
3432 | if (dbgregs->dr6 & ~0xffffffffull) |
3433 | return -EINVAL; | |
3434 | if (dbgregs->dr7 & ~0xffffffffull) | |
3435 | return -EINVAL; | |
3436 | ||
a1efbe77 | 3437 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); |
ae561ede | 3438 | kvm_update_dr0123(vcpu); |
a1efbe77 | 3439 | vcpu->arch.dr6 = dbgregs->dr6; |
73aaf249 | 3440 | kvm_update_dr6(vcpu); |
a1efbe77 | 3441 | vcpu->arch.dr7 = dbgregs->dr7; |
9926c9fd | 3442 | kvm_update_dr7(vcpu); |
a1efbe77 | 3443 | |
a1efbe77 JK |
3444 | return 0; |
3445 | } | |
3446 | ||
df1daba7 PB |
3447 | #define XSTATE_COMPACTION_ENABLED (1ULL << 63) |
3448 | ||
3449 | static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) | |
3450 | { | |
c47ada30 | 3451 | struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave; |
400e4b20 | 3452 | u64 xstate_bv = xsave->header.xfeatures; |
df1daba7 PB |
3453 | u64 valid; |
3454 | ||
3455 | /* | |
3456 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
3457 | * leaves 0 and 1 in the loop below. | |
3458 | */ | |
3459 | memcpy(dest, xsave, XSAVE_HDR_OFFSET); | |
3460 | ||
3461 | /* Set XSTATE_BV */ | |
00c87e9a | 3462 | xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE; |
df1daba7 PB |
3463 | *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; |
3464 | ||
3465 | /* | |
3466 | * Copy each region from the possibly compacted offset to the | |
3467 | * non-compacted offset. | |
3468 | */ | |
d91cab78 | 3469 | valid = xstate_bv & ~XFEATURE_MASK_FPSSE; |
df1daba7 PB |
3470 | while (valid) { |
3471 | u64 feature = valid & -valid; | |
3472 | int index = fls64(feature) - 1; | |
3473 | void *src = get_xsave_addr(xsave, feature); | |
3474 | ||
3475 | if (src) { | |
3476 | u32 size, offset, ecx, edx; | |
3477 | cpuid_count(XSTATE_CPUID, index, | |
3478 | &size, &offset, &ecx, &edx); | |
38cfd5e3 PB |
3479 | if (feature == XFEATURE_MASK_PKRU) |
3480 | memcpy(dest + offset, &vcpu->arch.pkru, | |
3481 | sizeof(vcpu->arch.pkru)); | |
3482 | else | |
3483 | memcpy(dest + offset, src, size); | |
3484 | ||
df1daba7 PB |
3485 | } |
3486 | ||
3487 | valid -= feature; | |
3488 | } | |
3489 | } | |
3490 | ||
3491 | static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) | |
3492 | { | |
c47ada30 | 3493 | struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave; |
df1daba7 PB |
3494 | u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); |
3495 | u64 valid; | |
3496 | ||
3497 | /* | |
3498 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
3499 | * leaves 0 and 1 in the loop below. | |
3500 | */ | |
3501 | memcpy(xsave, src, XSAVE_HDR_OFFSET); | |
3502 | ||
3503 | /* Set XSTATE_BV and possibly XCOMP_BV. */ | |
400e4b20 | 3504 | xsave->header.xfeatures = xstate_bv; |
782511b0 | 3505 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
3a54450b | 3506 | xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; |
df1daba7 PB |
3507 | |
3508 | /* | |
3509 | * Copy each region from the non-compacted offset to the | |
3510 | * possibly compacted offset. | |
3511 | */ | |
d91cab78 | 3512 | valid = xstate_bv & ~XFEATURE_MASK_FPSSE; |
df1daba7 PB |
3513 | while (valid) { |
3514 | u64 feature = valid & -valid; | |
3515 | int index = fls64(feature) - 1; | |
3516 | void *dest = get_xsave_addr(xsave, feature); | |
3517 | ||
3518 | if (dest) { | |
3519 | u32 size, offset, ecx, edx; | |
3520 | cpuid_count(XSTATE_CPUID, index, | |
3521 | &size, &offset, &ecx, &edx); | |
38cfd5e3 PB |
3522 | if (feature == XFEATURE_MASK_PKRU) |
3523 | memcpy(&vcpu->arch.pkru, src + offset, | |
3524 | sizeof(vcpu->arch.pkru)); | |
3525 | else | |
3526 | memcpy(dest, src + offset, size); | |
ee4100da | 3527 | } |
df1daba7 PB |
3528 | |
3529 | valid -= feature; | |
3530 | } | |
3531 | } | |
3532 | ||
2d5b5a66 SY |
3533 | static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, |
3534 | struct kvm_xsave *guest_xsave) | |
3535 | { | |
d366bf7e | 3536 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
df1daba7 PB |
3537 | memset(guest_xsave, 0, sizeof(struct kvm_xsave)); |
3538 | fill_xsave((u8 *) guest_xsave->region, vcpu); | |
4344ee98 | 3539 | } else { |
2d5b5a66 | 3540 | memcpy(guest_xsave->region, |
7366ed77 | 3541 | &vcpu->arch.guest_fpu.state.fxsave, |
c47ada30 | 3542 | sizeof(struct fxregs_state)); |
2d5b5a66 | 3543 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = |
d91cab78 | 3544 | XFEATURE_MASK_FPSSE; |
2d5b5a66 SY |
3545 | } |
3546 | } | |
3547 | ||
a575813b WL |
3548 | #define XSAVE_MXCSR_OFFSET 24 |
3549 | ||
2d5b5a66 SY |
3550 | static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, |
3551 | struct kvm_xsave *guest_xsave) | |
3552 | { | |
3553 | u64 xstate_bv = | |
3554 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; | |
a575813b | 3555 | u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)]; |
2d5b5a66 | 3556 | |
d366bf7e | 3557 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
d7876f1b PB |
3558 | /* |
3559 | * Here we allow setting states that are not present in | |
3560 | * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility | |
3561 | * with old userspace. | |
3562 | */ | |
a575813b WL |
3563 | if (xstate_bv & ~kvm_supported_xcr0() || |
3564 | mxcsr & ~mxcsr_feature_mask) | |
d7876f1b | 3565 | return -EINVAL; |
df1daba7 | 3566 | load_xsave(vcpu, (u8 *)guest_xsave->region); |
d7876f1b | 3567 | } else { |
a575813b WL |
3568 | if (xstate_bv & ~XFEATURE_MASK_FPSSE || |
3569 | mxcsr & ~mxcsr_feature_mask) | |
2d5b5a66 | 3570 | return -EINVAL; |
7366ed77 | 3571 | memcpy(&vcpu->arch.guest_fpu.state.fxsave, |
c47ada30 | 3572 | guest_xsave->region, sizeof(struct fxregs_state)); |
2d5b5a66 SY |
3573 | } |
3574 | return 0; | |
3575 | } | |
3576 | ||
3577 | static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, | |
3578 | struct kvm_xcrs *guest_xcrs) | |
3579 | { | |
d366bf7e | 3580 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) { |
2d5b5a66 SY |
3581 | guest_xcrs->nr_xcrs = 0; |
3582 | return; | |
3583 | } | |
3584 | ||
3585 | guest_xcrs->nr_xcrs = 1; | |
3586 | guest_xcrs->flags = 0; | |
3587 | guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; | |
3588 | guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; | |
3589 | } | |
3590 | ||
3591 | static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, | |
3592 | struct kvm_xcrs *guest_xcrs) | |
3593 | { | |
3594 | int i, r = 0; | |
3595 | ||
d366bf7e | 3596 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) |
2d5b5a66 SY |
3597 | return -EINVAL; |
3598 | ||
3599 | if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) | |
3600 | return -EINVAL; | |
3601 | ||
3602 | for (i = 0; i < guest_xcrs->nr_xcrs; i++) | |
3603 | /* Only support XCR0 currently */ | |
c67a04cb | 3604 | if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { |
2d5b5a66 | 3605 | r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, |
c67a04cb | 3606 | guest_xcrs->xcrs[i].value); |
2d5b5a66 SY |
3607 | break; |
3608 | } | |
3609 | if (r) | |
3610 | r = -EINVAL; | |
3611 | return r; | |
3612 | } | |
3613 | ||
1c0b28c2 EM |
3614 | /* |
3615 | * kvm_set_guest_paused() indicates to the guest kernel that it has been | |
3616 | * stopped by the hypervisor. This function will be called from the host only. | |
3617 | * EINVAL is returned when the host attempts to set the flag for a guest that | |
3618 | * does not support pv clocks. | |
3619 | */ | |
3620 | static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) | |
3621 | { | |
0b79459b | 3622 | if (!vcpu->arch.pv_time_enabled) |
1c0b28c2 | 3623 | return -EINVAL; |
51d59c6b | 3624 | vcpu->arch.pvclock_set_guest_stopped_request = true; |
1c0b28c2 EM |
3625 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
3626 | return 0; | |
3627 | } | |
3628 | ||
5c919412 AS |
3629 | static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, |
3630 | struct kvm_enable_cap *cap) | |
3631 | { | |
3632 | if (cap->flags) | |
3633 | return -EINVAL; | |
3634 | ||
3635 | switch (cap->cap) { | |
efc479e6 RK |
3636 | case KVM_CAP_HYPERV_SYNIC2: |
3637 | if (cap->args[0]) | |
3638 | return -EINVAL; | |
5c919412 | 3639 | case KVM_CAP_HYPERV_SYNIC: |
546d87e5 WL |
3640 | if (!irqchip_in_kernel(vcpu->kvm)) |
3641 | return -EINVAL; | |
efc479e6 RK |
3642 | return kvm_hv_activate_synic(vcpu, cap->cap == |
3643 | KVM_CAP_HYPERV_SYNIC2); | |
5c919412 AS |
3644 | default: |
3645 | return -EINVAL; | |
3646 | } | |
3647 | } | |
3648 | ||
313a3dc7 CO |
3649 | long kvm_arch_vcpu_ioctl(struct file *filp, |
3650 | unsigned int ioctl, unsigned long arg) | |
3651 | { | |
3652 | struct kvm_vcpu *vcpu = filp->private_data; | |
3653 | void __user *argp = (void __user *)arg; | |
3654 | int r; | |
d1ac91d8 AK |
3655 | union { |
3656 | struct kvm_lapic_state *lapic; | |
3657 | struct kvm_xsave *xsave; | |
3658 | struct kvm_xcrs *xcrs; | |
3659 | void *buffer; | |
3660 | } u; | |
3661 | ||
9b062471 CD |
3662 | vcpu_load(vcpu); |
3663 | ||
d1ac91d8 | 3664 | u.buffer = NULL; |
313a3dc7 CO |
3665 | switch (ioctl) { |
3666 | case KVM_GET_LAPIC: { | |
2204ae3c | 3667 | r = -EINVAL; |
bce87cce | 3668 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 3669 | goto out; |
d1ac91d8 | 3670 | u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); |
313a3dc7 | 3671 | |
b772ff36 | 3672 | r = -ENOMEM; |
d1ac91d8 | 3673 | if (!u.lapic) |
b772ff36 | 3674 | goto out; |
d1ac91d8 | 3675 | r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); |
313a3dc7 CO |
3676 | if (r) |
3677 | goto out; | |
3678 | r = -EFAULT; | |
d1ac91d8 | 3679 | if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
3680 | goto out; |
3681 | r = 0; | |
3682 | break; | |
3683 | } | |
3684 | case KVM_SET_LAPIC: { | |
2204ae3c | 3685 | r = -EINVAL; |
bce87cce | 3686 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 3687 | goto out; |
ff5c2c03 | 3688 | u.lapic = memdup_user(argp, sizeof(*u.lapic)); |
9b062471 CD |
3689 | if (IS_ERR(u.lapic)) { |
3690 | r = PTR_ERR(u.lapic); | |
3691 | goto out_nofree; | |
3692 | } | |
ff5c2c03 | 3693 | |
d1ac91d8 | 3694 | r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); |
313a3dc7 CO |
3695 | break; |
3696 | } | |
f77bc6a4 ZX |
3697 | case KVM_INTERRUPT: { |
3698 | struct kvm_interrupt irq; | |
3699 | ||
3700 | r = -EFAULT; | |
3701 | if (copy_from_user(&irq, argp, sizeof irq)) | |
3702 | goto out; | |
3703 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
f77bc6a4 ZX |
3704 | break; |
3705 | } | |
c4abb7c9 JK |
3706 | case KVM_NMI: { |
3707 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
c4abb7c9 JK |
3708 | break; |
3709 | } | |
f077825a PB |
3710 | case KVM_SMI: { |
3711 | r = kvm_vcpu_ioctl_smi(vcpu); | |
3712 | break; | |
3713 | } | |
313a3dc7 CO |
3714 | case KVM_SET_CPUID: { |
3715 | struct kvm_cpuid __user *cpuid_arg = argp; | |
3716 | struct kvm_cpuid cpuid; | |
3717 | ||
3718 | r = -EFAULT; | |
3719 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
3720 | goto out; | |
3721 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
313a3dc7 CO |
3722 | break; |
3723 | } | |
07716717 DK |
3724 | case KVM_SET_CPUID2: { |
3725 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
3726 | struct kvm_cpuid2 cpuid; | |
3727 | ||
3728 | r = -EFAULT; | |
3729 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
3730 | goto out; | |
3731 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 3732 | cpuid_arg->entries); |
07716717 DK |
3733 | break; |
3734 | } | |
3735 | case KVM_GET_CPUID2: { | |
3736 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
3737 | struct kvm_cpuid2 cpuid; | |
3738 | ||
3739 | r = -EFAULT; | |
3740 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
3741 | goto out; | |
3742 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 3743 | cpuid_arg->entries); |
07716717 DK |
3744 | if (r) |
3745 | goto out; | |
3746 | r = -EFAULT; | |
3747 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
3748 | goto out; | |
3749 | r = 0; | |
3750 | break; | |
3751 | } | |
801e459a TL |
3752 | case KVM_GET_MSRS: { |
3753 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
609e36d3 | 3754 | r = msr_io(vcpu, argp, do_get_msr, 1); |
801e459a | 3755 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 3756 | break; |
801e459a TL |
3757 | } |
3758 | case KVM_SET_MSRS: { | |
3759 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
313a3dc7 | 3760 | r = msr_io(vcpu, argp, do_set_msr, 0); |
801e459a | 3761 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 3762 | break; |
801e459a | 3763 | } |
b209749f AK |
3764 | case KVM_TPR_ACCESS_REPORTING: { |
3765 | struct kvm_tpr_access_ctl tac; | |
3766 | ||
3767 | r = -EFAULT; | |
3768 | if (copy_from_user(&tac, argp, sizeof tac)) | |
3769 | goto out; | |
3770 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
3771 | if (r) | |
3772 | goto out; | |
3773 | r = -EFAULT; | |
3774 | if (copy_to_user(argp, &tac, sizeof tac)) | |
3775 | goto out; | |
3776 | r = 0; | |
3777 | break; | |
3778 | }; | |
b93463aa AK |
3779 | case KVM_SET_VAPIC_ADDR: { |
3780 | struct kvm_vapic_addr va; | |
7301d6ab | 3781 | int idx; |
b93463aa AK |
3782 | |
3783 | r = -EINVAL; | |
35754c98 | 3784 | if (!lapic_in_kernel(vcpu)) |
b93463aa AK |
3785 | goto out; |
3786 | r = -EFAULT; | |
3787 | if (copy_from_user(&va, argp, sizeof va)) | |
3788 | goto out; | |
7301d6ab | 3789 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
fda4e2e8 | 3790 | r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); |
7301d6ab | 3791 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b93463aa AK |
3792 | break; |
3793 | } | |
890ca9ae HY |
3794 | case KVM_X86_SETUP_MCE: { |
3795 | u64 mcg_cap; | |
3796 | ||
3797 | r = -EFAULT; | |
3798 | if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) | |
3799 | goto out; | |
3800 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
3801 | break; | |
3802 | } | |
3803 | case KVM_X86_SET_MCE: { | |
3804 | struct kvm_x86_mce mce; | |
3805 | ||
3806 | r = -EFAULT; | |
3807 | if (copy_from_user(&mce, argp, sizeof mce)) | |
3808 | goto out; | |
3809 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
3810 | break; | |
3811 | } | |
3cfc3092 JK |
3812 | case KVM_GET_VCPU_EVENTS: { |
3813 | struct kvm_vcpu_events events; | |
3814 | ||
3815 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
3816 | ||
3817 | r = -EFAULT; | |
3818 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
3819 | break; | |
3820 | r = 0; | |
3821 | break; | |
3822 | } | |
3823 | case KVM_SET_VCPU_EVENTS: { | |
3824 | struct kvm_vcpu_events events; | |
3825 | ||
3826 | r = -EFAULT; | |
3827 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
3828 | break; | |
3829 | ||
3830 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
3831 | break; | |
3832 | } | |
a1efbe77 JK |
3833 | case KVM_GET_DEBUGREGS: { |
3834 | struct kvm_debugregs dbgregs; | |
3835 | ||
3836 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
3837 | ||
3838 | r = -EFAULT; | |
3839 | if (copy_to_user(argp, &dbgregs, | |
3840 | sizeof(struct kvm_debugregs))) | |
3841 | break; | |
3842 | r = 0; | |
3843 | break; | |
3844 | } | |
3845 | case KVM_SET_DEBUGREGS: { | |
3846 | struct kvm_debugregs dbgregs; | |
3847 | ||
3848 | r = -EFAULT; | |
3849 | if (copy_from_user(&dbgregs, argp, | |
3850 | sizeof(struct kvm_debugregs))) | |
3851 | break; | |
3852 | ||
3853 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
3854 | break; | |
3855 | } | |
2d5b5a66 | 3856 | case KVM_GET_XSAVE: { |
d1ac91d8 | 3857 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); |
2d5b5a66 | 3858 | r = -ENOMEM; |
d1ac91d8 | 3859 | if (!u.xsave) |
2d5b5a66 SY |
3860 | break; |
3861 | ||
d1ac91d8 | 3862 | kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
3863 | |
3864 | r = -EFAULT; | |
d1ac91d8 | 3865 | if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
3866 | break; |
3867 | r = 0; | |
3868 | break; | |
3869 | } | |
3870 | case KVM_SET_XSAVE: { | |
ff5c2c03 | 3871 | u.xsave = memdup_user(argp, sizeof(*u.xsave)); |
9b062471 CD |
3872 | if (IS_ERR(u.xsave)) { |
3873 | r = PTR_ERR(u.xsave); | |
3874 | goto out_nofree; | |
3875 | } | |
2d5b5a66 | 3876 | |
d1ac91d8 | 3877 | r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
3878 | break; |
3879 | } | |
3880 | case KVM_GET_XCRS: { | |
d1ac91d8 | 3881 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); |
2d5b5a66 | 3882 | r = -ENOMEM; |
d1ac91d8 | 3883 | if (!u.xcrs) |
2d5b5a66 SY |
3884 | break; |
3885 | ||
d1ac91d8 | 3886 | kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
3887 | |
3888 | r = -EFAULT; | |
d1ac91d8 | 3889 | if (copy_to_user(argp, u.xcrs, |
2d5b5a66 SY |
3890 | sizeof(struct kvm_xcrs))) |
3891 | break; | |
3892 | r = 0; | |
3893 | break; | |
3894 | } | |
3895 | case KVM_SET_XCRS: { | |
ff5c2c03 | 3896 | u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); |
9b062471 CD |
3897 | if (IS_ERR(u.xcrs)) { |
3898 | r = PTR_ERR(u.xcrs); | |
3899 | goto out_nofree; | |
3900 | } | |
2d5b5a66 | 3901 | |
d1ac91d8 | 3902 | r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
3903 | break; |
3904 | } | |
92a1f12d JR |
3905 | case KVM_SET_TSC_KHZ: { |
3906 | u32 user_tsc_khz; | |
3907 | ||
3908 | r = -EINVAL; | |
92a1f12d JR |
3909 | user_tsc_khz = (u32)arg; |
3910 | ||
3911 | if (user_tsc_khz >= kvm_max_guest_tsc_khz) | |
3912 | goto out; | |
3913 | ||
cc578287 ZA |
3914 | if (user_tsc_khz == 0) |
3915 | user_tsc_khz = tsc_khz; | |
3916 | ||
381d585c HZ |
3917 | if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) |
3918 | r = 0; | |
92a1f12d | 3919 | |
92a1f12d JR |
3920 | goto out; |
3921 | } | |
3922 | case KVM_GET_TSC_KHZ: { | |
cc578287 | 3923 | r = vcpu->arch.virtual_tsc_khz; |
92a1f12d JR |
3924 | goto out; |
3925 | } | |
1c0b28c2 EM |
3926 | case KVM_KVMCLOCK_CTRL: { |
3927 | r = kvm_set_guest_paused(vcpu); | |
3928 | goto out; | |
3929 | } | |
5c919412 AS |
3930 | case KVM_ENABLE_CAP: { |
3931 | struct kvm_enable_cap cap; | |
3932 | ||
3933 | r = -EFAULT; | |
3934 | if (copy_from_user(&cap, argp, sizeof(cap))) | |
3935 | goto out; | |
3936 | r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); | |
3937 | break; | |
3938 | } | |
313a3dc7 CO |
3939 | default: |
3940 | r = -EINVAL; | |
3941 | } | |
3942 | out: | |
d1ac91d8 | 3943 | kfree(u.buffer); |
9b062471 CD |
3944 | out_nofree: |
3945 | vcpu_put(vcpu); | |
313a3dc7 CO |
3946 | return r; |
3947 | } | |
3948 | ||
5b1c1493 CO |
3949 | int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) |
3950 | { | |
3951 | return VM_FAULT_SIGBUS; | |
3952 | } | |
3953 | ||
1fe779f8 CO |
3954 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
3955 | { | |
3956 | int ret; | |
3957 | ||
3958 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
951179ce | 3959 | return -EINVAL; |
1fe779f8 CO |
3960 | ret = kvm_x86_ops->set_tss_addr(kvm, addr); |
3961 | return ret; | |
3962 | } | |
3963 | ||
b927a3ce SY |
3964 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
3965 | u64 ident_addr) | |
3966 | { | |
2ac52ab8 | 3967 | return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr); |
b927a3ce SY |
3968 | } |
3969 | ||
1fe779f8 CO |
3970 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
3971 | u32 kvm_nr_mmu_pages) | |
3972 | { | |
3973 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
3974 | return -EINVAL; | |
3975 | ||
79fac95e | 3976 | mutex_lock(&kvm->slots_lock); |
1fe779f8 CO |
3977 | |
3978 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 3979 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 3980 | |
79fac95e | 3981 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
3982 | return 0; |
3983 | } | |
3984 | ||
3985 | static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) | |
3986 | { | |
39de71ec | 3987 | return kvm->arch.n_max_mmu_pages; |
1fe779f8 CO |
3988 | } |
3989 | ||
1fe779f8 CO |
3990 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) |
3991 | { | |
90bca052 | 3992 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
3993 | int r; |
3994 | ||
3995 | r = 0; | |
3996 | switch (chip->chip_id) { | |
3997 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 | 3998 | memcpy(&chip->chip.pic, &pic->pics[0], |
1fe779f8 CO |
3999 | sizeof(struct kvm_pic_state)); |
4000 | break; | |
4001 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 | 4002 | memcpy(&chip->chip.pic, &pic->pics[1], |
1fe779f8 CO |
4003 | sizeof(struct kvm_pic_state)); |
4004 | break; | |
4005 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 4006 | kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
4007 | break; |
4008 | default: | |
4009 | r = -EINVAL; | |
4010 | break; | |
4011 | } | |
4012 | return r; | |
4013 | } | |
4014 | ||
4015 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
4016 | { | |
90bca052 | 4017 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
4018 | int r; |
4019 | ||
4020 | r = 0; | |
4021 | switch (chip->chip_id) { | |
4022 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 DH |
4023 | spin_lock(&pic->lock); |
4024 | memcpy(&pic->pics[0], &chip->chip.pic, | |
1fe779f8 | 4025 | sizeof(struct kvm_pic_state)); |
90bca052 | 4026 | spin_unlock(&pic->lock); |
1fe779f8 CO |
4027 | break; |
4028 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 DH |
4029 | spin_lock(&pic->lock); |
4030 | memcpy(&pic->pics[1], &chip->chip.pic, | |
1fe779f8 | 4031 | sizeof(struct kvm_pic_state)); |
90bca052 | 4032 | spin_unlock(&pic->lock); |
1fe779f8 CO |
4033 | break; |
4034 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 4035 | kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
4036 | break; |
4037 | default: | |
4038 | r = -EINVAL; | |
4039 | break; | |
4040 | } | |
90bca052 | 4041 | kvm_pic_update_irq(pic); |
1fe779f8 CO |
4042 | return r; |
4043 | } | |
4044 | ||
e0f63cb9 SY |
4045 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
4046 | { | |
34f3941c RK |
4047 | struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; |
4048 | ||
4049 | BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); | |
4050 | ||
4051 | mutex_lock(&kps->lock); | |
4052 | memcpy(ps, &kps->channels, sizeof(*ps)); | |
4053 | mutex_unlock(&kps->lock); | |
2da29bcc | 4054 | return 0; |
e0f63cb9 SY |
4055 | } |
4056 | ||
4057 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
4058 | { | |
0185604c | 4059 | int i; |
09edea72 RK |
4060 | struct kvm_pit *pit = kvm->arch.vpit; |
4061 | ||
4062 | mutex_lock(&pit->pit_state.lock); | |
34f3941c | 4063 | memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); |
0185604c | 4064 | for (i = 0; i < 3; i++) |
09edea72 RK |
4065 | kvm_pit_load_count(pit, i, ps->channels[i].count, 0); |
4066 | mutex_unlock(&pit->pit_state.lock); | |
2da29bcc | 4067 | return 0; |
e9f42757 BK |
4068 | } |
4069 | ||
4070 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
4071 | { | |
e9f42757 BK |
4072 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
4073 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
4074 | sizeof(ps->channels)); | |
4075 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
4076 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
97e69aa6 | 4077 | memset(&ps->reserved, 0, sizeof(ps->reserved)); |
2da29bcc | 4078 | return 0; |
e9f42757 BK |
4079 | } |
4080 | ||
4081 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
4082 | { | |
2da29bcc | 4083 | int start = 0; |
0185604c | 4084 | int i; |
e9f42757 | 4085 | u32 prev_legacy, cur_legacy; |
09edea72 RK |
4086 | struct kvm_pit *pit = kvm->arch.vpit; |
4087 | ||
4088 | mutex_lock(&pit->pit_state.lock); | |
4089 | prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
e9f42757 BK |
4090 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; |
4091 | if (!prev_legacy && cur_legacy) | |
4092 | start = 1; | |
09edea72 RK |
4093 | memcpy(&pit->pit_state.channels, &ps->channels, |
4094 | sizeof(pit->pit_state.channels)); | |
4095 | pit->pit_state.flags = ps->flags; | |
0185604c | 4096 | for (i = 0; i < 3; i++) |
09edea72 | 4097 | kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, |
e5e57e7a | 4098 | start && i == 0); |
09edea72 | 4099 | mutex_unlock(&pit->pit_state.lock); |
2da29bcc | 4100 | return 0; |
e0f63cb9 SY |
4101 | } |
4102 | ||
52d939a0 MT |
4103 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
4104 | struct kvm_reinject_control *control) | |
4105 | { | |
71474e2f RK |
4106 | struct kvm_pit *pit = kvm->arch.vpit; |
4107 | ||
4108 | if (!pit) | |
52d939a0 | 4109 | return -ENXIO; |
b39c90b6 | 4110 | |
71474e2f RK |
4111 | /* pit->pit_state.lock was overloaded to prevent userspace from getting |
4112 | * an inconsistent state after running multiple KVM_REINJECT_CONTROL | |
4113 | * ioctls in parallel. Use a separate lock if that ioctl isn't rare. | |
4114 | */ | |
4115 | mutex_lock(&pit->pit_state.lock); | |
4116 | kvm_pit_set_reinject(pit, control->pit_reinject); | |
4117 | mutex_unlock(&pit->pit_state.lock); | |
b39c90b6 | 4118 | |
52d939a0 MT |
4119 | return 0; |
4120 | } | |
4121 | ||
95d4c16c | 4122 | /** |
60c34612 TY |
4123 | * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot |
4124 | * @kvm: kvm instance | |
4125 | * @log: slot id and address to which we copy the log | |
95d4c16c | 4126 | * |
e108ff2f PB |
4127 | * Steps 1-4 below provide general overview of dirty page logging. See |
4128 | * kvm_get_dirty_log_protect() function description for additional details. | |
4129 | * | |
4130 | * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we | |
4131 | * always flush the TLB (step 4) even if previous step failed and the dirty | |
4132 | * bitmap may be corrupt. Regardless of previous outcome the KVM logging API | |
4133 | * does not preclude user space subsequent dirty log read. Flushing TLB ensures | |
4134 | * writes will be marked dirty for next log read. | |
95d4c16c | 4135 | * |
60c34612 TY |
4136 | * 1. Take a snapshot of the bit and clear it if needed. |
4137 | * 2. Write protect the corresponding page. | |
e108ff2f PB |
4138 | * 3. Copy the snapshot to the userspace. |
4139 | * 4. Flush TLB's if needed. | |
5bb064dc | 4140 | */ |
60c34612 | 4141 | int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) |
5bb064dc | 4142 | { |
60c34612 | 4143 | bool is_dirty = false; |
e108ff2f | 4144 | int r; |
5bb064dc | 4145 | |
79fac95e | 4146 | mutex_lock(&kvm->slots_lock); |
5bb064dc | 4147 | |
88178fd4 KH |
4148 | /* |
4149 | * Flush potentially hardware-cached dirty pages to dirty_bitmap. | |
4150 | */ | |
4151 | if (kvm_x86_ops->flush_log_dirty) | |
4152 | kvm_x86_ops->flush_log_dirty(kvm); | |
4153 | ||
e108ff2f | 4154 | r = kvm_get_dirty_log_protect(kvm, log, &is_dirty); |
198c74f4 XG |
4155 | |
4156 | /* | |
4157 | * All the TLBs can be flushed out of mmu lock, see the comments in | |
4158 | * kvm_mmu_slot_remove_write_access(). | |
4159 | */ | |
e108ff2f | 4160 | lockdep_assert_held(&kvm->slots_lock); |
198c74f4 XG |
4161 | if (is_dirty) |
4162 | kvm_flush_remote_tlbs(kvm); | |
4163 | ||
79fac95e | 4164 | mutex_unlock(&kvm->slots_lock); |
5bb064dc ZX |
4165 | return r; |
4166 | } | |
4167 | ||
aa2fbe6d YZ |
4168 | int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, |
4169 | bool line_status) | |
23d43cf9 CD |
4170 | { |
4171 | if (!irqchip_in_kernel(kvm)) | |
4172 | return -ENXIO; | |
4173 | ||
4174 | irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, | |
aa2fbe6d YZ |
4175 | irq_event->irq, irq_event->level, |
4176 | line_status); | |
23d43cf9 CD |
4177 | return 0; |
4178 | } | |
4179 | ||
90de4a18 NA |
4180 | static int kvm_vm_ioctl_enable_cap(struct kvm *kvm, |
4181 | struct kvm_enable_cap *cap) | |
4182 | { | |
4183 | int r; | |
4184 | ||
4185 | if (cap->flags) | |
4186 | return -EINVAL; | |
4187 | ||
4188 | switch (cap->cap) { | |
4189 | case KVM_CAP_DISABLE_QUIRKS: | |
4190 | kvm->arch.disabled_quirks = cap->args[0]; | |
4191 | r = 0; | |
4192 | break; | |
49df6397 SR |
4193 | case KVM_CAP_SPLIT_IRQCHIP: { |
4194 | mutex_lock(&kvm->lock); | |
b053b2ae SR |
4195 | r = -EINVAL; |
4196 | if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) | |
4197 | goto split_irqchip_unlock; | |
49df6397 SR |
4198 | r = -EEXIST; |
4199 | if (irqchip_in_kernel(kvm)) | |
4200 | goto split_irqchip_unlock; | |
557abc40 | 4201 | if (kvm->created_vcpus) |
49df6397 SR |
4202 | goto split_irqchip_unlock; |
4203 | r = kvm_setup_empty_irq_routing(kvm); | |
5c0aea0e | 4204 | if (r) |
49df6397 SR |
4205 | goto split_irqchip_unlock; |
4206 | /* Pairs with irqchip_in_kernel. */ | |
4207 | smp_wmb(); | |
49776faf | 4208 | kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; |
b053b2ae | 4209 | kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; |
49df6397 SR |
4210 | r = 0; |
4211 | split_irqchip_unlock: | |
4212 | mutex_unlock(&kvm->lock); | |
4213 | break; | |
4214 | } | |
37131313 RK |
4215 | case KVM_CAP_X2APIC_API: |
4216 | r = -EINVAL; | |
4217 | if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) | |
4218 | break; | |
4219 | ||
4220 | if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) | |
4221 | kvm->arch.x2apic_format = true; | |
c519265f RK |
4222 | if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) |
4223 | kvm->arch.x2apic_broadcast_quirk_disabled = true; | |
37131313 RK |
4224 | |
4225 | r = 0; | |
4226 | break; | |
4d5422ce WL |
4227 | case KVM_CAP_X86_DISABLE_EXITS: |
4228 | r = -EINVAL; | |
4229 | if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) | |
4230 | break; | |
4231 | ||
4232 | if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && | |
4233 | kvm_can_mwait_in_guest()) | |
4234 | kvm->arch.mwait_in_guest = true; | |
caa057a2 WL |
4235 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_HTL) |
4236 | kvm->arch.hlt_in_guest = true; | |
b31c114b WL |
4237 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) |
4238 | kvm->arch.pause_in_guest = true; | |
4d5422ce WL |
4239 | r = 0; |
4240 | break; | |
90de4a18 NA |
4241 | default: |
4242 | r = -EINVAL; | |
4243 | break; | |
4244 | } | |
4245 | return r; | |
4246 | } | |
4247 | ||
1fe779f8 CO |
4248 | long kvm_arch_vm_ioctl(struct file *filp, |
4249 | unsigned int ioctl, unsigned long arg) | |
4250 | { | |
4251 | struct kvm *kvm = filp->private_data; | |
4252 | void __user *argp = (void __user *)arg; | |
367e1319 | 4253 | int r = -ENOTTY; |
f0d66275 DH |
4254 | /* |
4255 | * This union makes it completely explicit to gcc-3.x | |
4256 | * that these two variables' stack usage should be | |
4257 | * combined, not added together. | |
4258 | */ | |
4259 | union { | |
4260 | struct kvm_pit_state ps; | |
e9f42757 | 4261 | struct kvm_pit_state2 ps2; |
c5ff41ce | 4262 | struct kvm_pit_config pit_config; |
f0d66275 | 4263 | } u; |
1fe779f8 CO |
4264 | |
4265 | switch (ioctl) { | |
4266 | case KVM_SET_TSS_ADDR: | |
4267 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
1fe779f8 | 4268 | break; |
b927a3ce SY |
4269 | case KVM_SET_IDENTITY_MAP_ADDR: { |
4270 | u64 ident_addr; | |
4271 | ||
1af1ac91 DH |
4272 | mutex_lock(&kvm->lock); |
4273 | r = -EINVAL; | |
4274 | if (kvm->created_vcpus) | |
4275 | goto set_identity_unlock; | |
b927a3ce SY |
4276 | r = -EFAULT; |
4277 | if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) | |
1af1ac91 | 4278 | goto set_identity_unlock; |
b927a3ce | 4279 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); |
1af1ac91 DH |
4280 | set_identity_unlock: |
4281 | mutex_unlock(&kvm->lock); | |
b927a3ce SY |
4282 | break; |
4283 | } | |
1fe779f8 CO |
4284 | case KVM_SET_NR_MMU_PAGES: |
4285 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
1fe779f8 CO |
4286 | break; |
4287 | case KVM_GET_NR_MMU_PAGES: | |
4288 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
4289 | break; | |
3ddea128 | 4290 | case KVM_CREATE_IRQCHIP: { |
3ddea128 | 4291 | mutex_lock(&kvm->lock); |
09941366 | 4292 | |
3ddea128 | 4293 | r = -EEXIST; |
35e6eaa3 | 4294 | if (irqchip_in_kernel(kvm)) |
3ddea128 | 4295 | goto create_irqchip_unlock; |
09941366 | 4296 | |
3e515705 | 4297 | r = -EINVAL; |
557abc40 | 4298 | if (kvm->created_vcpus) |
3e515705 | 4299 | goto create_irqchip_unlock; |
09941366 RK |
4300 | |
4301 | r = kvm_pic_init(kvm); | |
4302 | if (r) | |
3ddea128 | 4303 | goto create_irqchip_unlock; |
09941366 RK |
4304 | |
4305 | r = kvm_ioapic_init(kvm); | |
4306 | if (r) { | |
09941366 | 4307 | kvm_pic_destroy(kvm); |
3ddea128 | 4308 | goto create_irqchip_unlock; |
09941366 RK |
4309 | } |
4310 | ||
399ec807 AK |
4311 | r = kvm_setup_default_irq_routing(kvm); |
4312 | if (r) { | |
72bb2fcd | 4313 | kvm_ioapic_destroy(kvm); |
09941366 | 4314 | kvm_pic_destroy(kvm); |
71ba994c | 4315 | goto create_irqchip_unlock; |
399ec807 | 4316 | } |
49776faf | 4317 | /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ |
71ba994c | 4318 | smp_wmb(); |
49776faf | 4319 | kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; |
3ddea128 MT |
4320 | create_irqchip_unlock: |
4321 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 4322 | break; |
3ddea128 | 4323 | } |
7837699f | 4324 | case KVM_CREATE_PIT: |
c5ff41ce JK |
4325 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
4326 | goto create_pit; | |
4327 | case KVM_CREATE_PIT2: | |
4328 | r = -EFAULT; | |
4329 | if (copy_from_user(&u.pit_config, argp, | |
4330 | sizeof(struct kvm_pit_config))) | |
4331 | goto out; | |
4332 | create_pit: | |
250715a6 | 4333 | mutex_lock(&kvm->lock); |
269e05e4 AK |
4334 | r = -EEXIST; |
4335 | if (kvm->arch.vpit) | |
4336 | goto create_pit_unlock; | |
7837699f | 4337 | r = -ENOMEM; |
c5ff41ce | 4338 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
4339 | if (kvm->arch.vpit) |
4340 | r = 0; | |
269e05e4 | 4341 | create_pit_unlock: |
250715a6 | 4342 | mutex_unlock(&kvm->lock); |
7837699f | 4343 | break; |
1fe779f8 CO |
4344 | case KVM_GET_IRQCHIP: { |
4345 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 4346 | struct kvm_irqchip *chip; |
1fe779f8 | 4347 | |
ff5c2c03 SL |
4348 | chip = memdup_user(argp, sizeof(*chip)); |
4349 | if (IS_ERR(chip)) { | |
4350 | r = PTR_ERR(chip); | |
1fe779f8 | 4351 | goto out; |
ff5c2c03 SL |
4352 | } |
4353 | ||
1fe779f8 | 4354 | r = -ENXIO; |
826da321 | 4355 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
4356 | goto get_irqchip_out; |
4357 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 4358 | if (r) |
f0d66275 | 4359 | goto get_irqchip_out; |
1fe779f8 | 4360 | r = -EFAULT; |
f0d66275 DH |
4361 | if (copy_to_user(argp, chip, sizeof *chip)) |
4362 | goto get_irqchip_out; | |
1fe779f8 | 4363 | r = 0; |
f0d66275 DH |
4364 | get_irqchip_out: |
4365 | kfree(chip); | |
1fe779f8 CO |
4366 | break; |
4367 | } | |
4368 | case KVM_SET_IRQCHIP: { | |
4369 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 4370 | struct kvm_irqchip *chip; |
1fe779f8 | 4371 | |
ff5c2c03 SL |
4372 | chip = memdup_user(argp, sizeof(*chip)); |
4373 | if (IS_ERR(chip)) { | |
4374 | r = PTR_ERR(chip); | |
1fe779f8 | 4375 | goto out; |
ff5c2c03 SL |
4376 | } |
4377 | ||
1fe779f8 | 4378 | r = -ENXIO; |
826da321 | 4379 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
4380 | goto set_irqchip_out; |
4381 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
1fe779f8 | 4382 | if (r) |
f0d66275 | 4383 | goto set_irqchip_out; |
1fe779f8 | 4384 | r = 0; |
f0d66275 DH |
4385 | set_irqchip_out: |
4386 | kfree(chip); | |
1fe779f8 CO |
4387 | break; |
4388 | } | |
e0f63cb9 | 4389 | case KVM_GET_PIT: { |
e0f63cb9 | 4390 | r = -EFAULT; |
f0d66275 | 4391 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
4392 | goto out; |
4393 | r = -ENXIO; | |
4394 | if (!kvm->arch.vpit) | |
4395 | goto out; | |
f0d66275 | 4396 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
4397 | if (r) |
4398 | goto out; | |
4399 | r = -EFAULT; | |
f0d66275 | 4400 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
4401 | goto out; |
4402 | r = 0; | |
4403 | break; | |
4404 | } | |
4405 | case KVM_SET_PIT: { | |
e0f63cb9 | 4406 | r = -EFAULT; |
f0d66275 | 4407 | if (copy_from_user(&u.ps, argp, sizeof u.ps)) |
e0f63cb9 SY |
4408 | goto out; |
4409 | r = -ENXIO; | |
4410 | if (!kvm->arch.vpit) | |
4411 | goto out; | |
f0d66275 | 4412 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
e0f63cb9 SY |
4413 | break; |
4414 | } | |
e9f42757 BK |
4415 | case KVM_GET_PIT2: { |
4416 | r = -ENXIO; | |
4417 | if (!kvm->arch.vpit) | |
4418 | goto out; | |
4419 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
4420 | if (r) | |
4421 | goto out; | |
4422 | r = -EFAULT; | |
4423 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
4424 | goto out; | |
4425 | r = 0; | |
4426 | break; | |
4427 | } | |
4428 | case KVM_SET_PIT2: { | |
4429 | r = -EFAULT; | |
4430 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
4431 | goto out; | |
4432 | r = -ENXIO; | |
4433 | if (!kvm->arch.vpit) | |
4434 | goto out; | |
4435 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); | |
e9f42757 BK |
4436 | break; |
4437 | } | |
52d939a0 MT |
4438 | case KVM_REINJECT_CONTROL: { |
4439 | struct kvm_reinject_control control; | |
4440 | r = -EFAULT; | |
4441 | if (copy_from_user(&control, argp, sizeof(control))) | |
4442 | goto out; | |
4443 | r = kvm_vm_ioctl_reinject(kvm, &control); | |
52d939a0 MT |
4444 | break; |
4445 | } | |
d71ba788 PB |
4446 | case KVM_SET_BOOT_CPU_ID: |
4447 | r = 0; | |
4448 | mutex_lock(&kvm->lock); | |
557abc40 | 4449 | if (kvm->created_vcpus) |
d71ba788 PB |
4450 | r = -EBUSY; |
4451 | else | |
4452 | kvm->arch.bsp_vcpu_id = arg; | |
4453 | mutex_unlock(&kvm->lock); | |
4454 | break; | |
ffde22ac | 4455 | case KVM_XEN_HVM_CONFIG: { |
51776043 | 4456 | struct kvm_xen_hvm_config xhc; |
ffde22ac | 4457 | r = -EFAULT; |
51776043 | 4458 | if (copy_from_user(&xhc, argp, sizeof(xhc))) |
ffde22ac ES |
4459 | goto out; |
4460 | r = -EINVAL; | |
51776043 | 4461 | if (xhc.flags) |
ffde22ac | 4462 | goto out; |
51776043 | 4463 | memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc)); |
ffde22ac ES |
4464 | r = 0; |
4465 | break; | |
4466 | } | |
afbcf7ab | 4467 | case KVM_SET_CLOCK: { |
afbcf7ab GC |
4468 | struct kvm_clock_data user_ns; |
4469 | u64 now_ns; | |
afbcf7ab GC |
4470 | |
4471 | r = -EFAULT; | |
4472 | if (copy_from_user(&user_ns, argp, sizeof(user_ns))) | |
4473 | goto out; | |
4474 | ||
4475 | r = -EINVAL; | |
4476 | if (user_ns.flags) | |
4477 | goto out; | |
4478 | ||
4479 | r = 0; | |
0bc48bea RK |
4480 | /* |
4481 | * TODO: userspace has to take care of races with VCPU_RUN, so | |
4482 | * kvm_gen_update_masterclock() can be cut down to locked | |
4483 | * pvclock_update_vm_gtod_copy(). | |
4484 | */ | |
4485 | kvm_gen_update_masterclock(kvm); | |
e891a32e | 4486 | now_ns = get_kvmclock_ns(kvm); |
108b249c | 4487 | kvm->arch.kvmclock_offset += user_ns.clock - now_ns; |
0bc48bea | 4488 | kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE); |
afbcf7ab GC |
4489 | break; |
4490 | } | |
4491 | case KVM_GET_CLOCK: { | |
afbcf7ab GC |
4492 | struct kvm_clock_data user_ns; |
4493 | u64 now_ns; | |
4494 | ||
e891a32e | 4495 | now_ns = get_kvmclock_ns(kvm); |
108b249c | 4496 | user_ns.clock = now_ns; |
e3fd9a93 | 4497 | user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; |
97e69aa6 | 4498 | memset(&user_ns.pad, 0, sizeof(user_ns.pad)); |
afbcf7ab GC |
4499 | |
4500 | r = -EFAULT; | |
4501 | if (copy_to_user(argp, &user_ns, sizeof(user_ns))) | |
4502 | goto out; | |
4503 | r = 0; | |
4504 | break; | |
4505 | } | |
90de4a18 NA |
4506 | case KVM_ENABLE_CAP: { |
4507 | struct kvm_enable_cap cap; | |
afbcf7ab | 4508 | |
90de4a18 NA |
4509 | r = -EFAULT; |
4510 | if (copy_from_user(&cap, argp, sizeof(cap))) | |
4511 | goto out; | |
4512 | r = kvm_vm_ioctl_enable_cap(kvm, &cap); | |
4513 | break; | |
4514 | } | |
5acc5c06 BS |
4515 | case KVM_MEMORY_ENCRYPT_OP: { |
4516 | r = -ENOTTY; | |
4517 | if (kvm_x86_ops->mem_enc_op) | |
4518 | r = kvm_x86_ops->mem_enc_op(kvm, argp); | |
4519 | break; | |
4520 | } | |
69eaedee BS |
4521 | case KVM_MEMORY_ENCRYPT_REG_REGION: { |
4522 | struct kvm_enc_region region; | |
4523 | ||
4524 | r = -EFAULT; | |
4525 | if (copy_from_user(®ion, argp, sizeof(region))) | |
4526 | goto out; | |
4527 | ||
4528 | r = -ENOTTY; | |
4529 | if (kvm_x86_ops->mem_enc_reg_region) | |
4530 | r = kvm_x86_ops->mem_enc_reg_region(kvm, ®ion); | |
4531 | break; | |
4532 | } | |
4533 | case KVM_MEMORY_ENCRYPT_UNREG_REGION: { | |
4534 | struct kvm_enc_region region; | |
4535 | ||
4536 | r = -EFAULT; | |
4537 | if (copy_from_user(®ion, argp, sizeof(region))) | |
4538 | goto out; | |
4539 | ||
4540 | r = -ENOTTY; | |
4541 | if (kvm_x86_ops->mem_enc_unreg_region) | |
4542 | r = kvm_x86_ops->mem_enc_unreg_region(kvm, ®ion); | |
4543 | break; | |
4544 | } | |
faeb7833 RK |
4545 | case KVM_HYPERV_EVENTFD: { |
4546 | struct kvm_hyperv_eventfd hvevfd; | |
4547 | ||
4548 | r = -EFAULT; | |
4549 | if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) | |
4550 | goto out; | |
4551 | r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); | |
4552 | break; | |
4553 | } | |
1fe779f8 | 4554 | default: |
ad6260da | 4555 | r = -ENOTTY; |
1fe779f8 CO |
4556 | } |
4557 | out: | |
4558 | return r; | |
4559 | } | |
4560 | ||
a16b043c | 4561 | static void kvm_init_msr_list(void) |
043405e1 CO |
4562 | { |
4563 | u32 dummy[2]; | |
4564 | unsigned i, j; | |
4565 | ||
62ef68bb | 4566 | for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) { |
043405e1 CO |
4567 | if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) |
4568 | continue; | |
93c4adc7 PB |
4569 | |
4570 | /* | |
4571 | * Even MSRs that are valid in the host may not be exposed | |
9dbe6cf9 | 4572 | * to the guests in some cases. |
93c4adc7 PB |
4573 | */ |
4574 | switch (msrs_to_save[i]) { | |
4575 | case MSR_IA32_BNDCFGS: | |
4576 | if (!kvm_x86_ops->mpx_supported()) | |
4577 | continue; | |
4578 | break; | |
9dbe6cf9 PB |
4579 | case MSR_TSC_AUX: |
4580 | if (!kvm_x86_ops->rdtscp_supported()) | |
4581 | continue; | |
4582 | break; | |
93c4adc7 PB |
4583 | default: |
4584 | break; | |
4585 | } | |
4586 | ||
043405e1 CO |
4587 | if (j < i) |
4588 | msrs_to_save[j] = msrs_to_save[i]; | |
4589 | j++; | |
4590 | } | |
4591 | num_msrs_to_save = j; | |
62ef68bb PB |
4592 | |
4593 | for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) { | |
4594 | switch (emulated_msrs[i]) { | |
6d396b55 PB |
4595 | case MSR_IA32_SMBASE: |
4596 | if (!kvm_x86_ops->cpu_has_high_real_mode_segbase()) | |
4597 | continue; | |
4598 | break; | |
62ef68bb PB |
4599 | default: |
4600 | break; | |
4601 | } | |
4602 | ||
4603 | if (j < i) | |
4604 | emulated_msrs[j] = emulated_msrs[i]; | |
4605 | j++; | |
4606 | } | |
4607 | num_emulated_msrs = j; | |
801e459a TL |
4608 | |
4609 | for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) { | |
4610 | struct kvm_msr_entry msr; | |
4611 | ||
4612 | msr.index = msr_based_features[i]; | |
66421c1e | 4613 | if (kvm_get_msr_feature(&msr)) |
801e459a TL |
4614 | continue; |
4615 | ||
4616 | if (j < i) | |
4617 | msr_based_features[j] = msr_based_features[i]; | |
4618 | j++; | |
4619 | } | |
4620 | num_msr_based_features = j; | |
043405e1 CO |
4621 | } |
4622 | ||
bda9020e MT |
4623 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
4624 | const void *v) | |
bbd9b64e | 4625 | { |
70252a10 AK |
4626 | int handled = 0; |
4627 | int n; | |
4628 | ||
4629 | do { | |
4630 | n = min(len, 8); | |
bce87cce | 4631 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
4632 | !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) |
4633 | && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 AK |
4634 | break; |
4635 | handled += n; | |
4636 | addr += n; | |
4637 | len -= n; | |
4638 | v += n; | |
4639 | } while (len); | |
bbd9b64e | 4640 | |
70252a10 | 4641 | return handled; |
bbd9b64e CO |
4642 | } |
4643 | ||
bda9020e | 4644 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 4645 | { |
70252a10 AK |
4646 | int handled = 0; |
4647 | int n; | |
4648 | ||
4649 | do { | |
4650 | n = min(len, 8); | |
bce87cce | 4651 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
4652 | !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, |
4653 | addr, n, v)) | |
4654 | && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 | 4655 | break; |
e39d200f | 4656 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); |
70252a10 AK |
4657 | handled += n; |
4658 | addr += n; | |
4659 | len -= n; | |
4660 | v += n; | |
4661 | } while (len); | |
bbd9b64e | 4662 | |
70252a10 | 4663 | return handled; |
bbd9b64e CO |
4664 | } |
4665 | ||
2dafc6c2 GN |
4666 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
4667 | struct kvm_segment *var, int seg) | |
4668 | { | |
4669 | kvm_x86_ops->set_segment(vcpu, var, seg); | |
4670 | } | |
4671 | ||
4672 | void kvm_get_segment(struct kvm_vcpu *vcpu, | |
4673 | struct kvm_segment *var, int seg) | |
4674 | { | |
4675 | kvm_x86_ops->get_segment(vcpu, var, seg); | |
4676 | } | |
4677 | ||
54987b7a PB |
4678 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
4679 | struct x86_exception *exception) | |
02f59dc9 JR |
4680 | { |
4681 | gpa_t t_gpa; | |
02f59dc9 JR |
4682 | |
4683 | BUG_ON(!mmu_is_nested(vcpu)); | |
4684 | ||
4685 | /* NPT walks are always user-walks */ | |
4686 | access |= PFERR_USER_MASK; | |
54987b7a | 4687 | t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception); |
02f59dc9 JR |
4688 | |
4689 | return t_gpa; | |
4690 | } | |
4691 | ||
ab9ae313 AK |
4692 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
4693 | struct x86_exception *exception) | |
1871c602 GN |
4694 | { |
4695 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
ab9ae313 | 4696 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
4697 | } |
4698 | ||
ab9ae313 AK |
4699 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, |
4700 | struct x86_exception *exception) | |
1871c602 GN |
4701 | { |
4702 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
4703 | access |= PFERR_FETCH_MASK; | |
ab9ae313 | 4704 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
4705 | } |
4706 | ||
ab9ae313 AK |
4707 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, |
4708 | struct x86_exception *exception) | |
1871c602 GN |
4709 | { |
4710 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
4711 | access |= PFERR_WRITE_MASK; | |
ab9ae313 | 4712 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
4713 | } |
4714 | ||
4715 | /* uses this to access any guest's mapped memory without checking CPL */ | |
ab9ae313 AK |
4716 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, |
4717 | struct x86_exception *exception) | |
1871c602 | 4718 | { |
ab9ae313 | 4719 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); |
1871c602 GN |
4720 | } |
4721 | ||
4722 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
4723 | struct kvm_vcpu *vcpu, u32 access, | |
bcc55cba | 4724 | struct x86_exception *exception) |
bbd9b64e CO |
4725 | { |
4726 | void *data = val; | |
10589a46 | 4727 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
4728 | |
4729 | while (bytes) { | |
14dfe855 | 4730 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, |
ab9ae313 | 4731 | exception); |
bbd9b64e | 4732 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 4733 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
4734 | int ret; |
4735 | ||
bcc55cba | 4736 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 4737 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa PB |
4738 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, |
4739 | offset, toread); | |
10589a46 | 4740 | if (ret < 0) { |
c3cd7ffa | 4741 | r = X86EMUL_IO_NEEDED; |
10589a46 MT |
4742 | goto out; |
4743 | } | |
bbd9b64e | 4744 | |
77c2002e IE |
4745 | bytes -= toread; |
4746 | data += toread; | |
4747 | addr += toread; | |
bbd9b64e | 4748 | } |
10589a46 | 4749 | out: |
10589a46 | 4750 | return r; |
bbd9b64e | 4751 | } |
77c2002e | 4752 | |
1871c602 | 4753 | /* used for instruction fetching */ |
0f65dd70 AK |
4754 | static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, |
4755 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 4756 | struct x86_exception *exception) |
1871c602 | 4757 | { |
0f65dd70 | 4758 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
1871c602 | 4759 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
44583cba PB |
4760 | unsigned offset; |
4761 | int ret; | |
0f65dd70 | 4762 | |
44583cba PB |
4763 | /* Inline kvm_read_guest_virt_helper for speed. */ |
4764 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, | |
4765 | exception); | |
4766 | if (unlikely(gpa == UNMAPPED_GVA)) | |
4767 | return X86EMUL_PROPAGATE_FAULT; | |
4768 | ||
4769 | offset = addr & (PAGE_SIZE-1); | |
4770 | if (WARN_ON(offset + bytes > PAGE_SIZE)) | |
4771 | bytes = (unsigned)PAGE_SIZE - offset; | |
54bf36aa PB |
4772 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, |
4773 | offset, bytes); | |
44583cba PB |
4774 | if (unlikely(ret < 0)) |
4775 | return X86EMUL_IO_NEEDED; | |
4776 | ||
4777 | return X86EMUL_CONTINUE; | |
1871c602 GN |
4778 | } |
4779 | ||
064aea77 | 4780 | int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt, |
0f65dd70 | 4781 | gva_t addr, void *val, unsigned int bytes, |
bcc55cba | 4782 | struct x86_exception *exception) |
1871c602 | 4783 | { |
0f65dd70 | 4784 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
1871c602 | 4785 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
0f65dd70 | 4786 | |
1871c602 | 4787 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, |
bcc55cba | 4788 | exception); |
1871c602 | 4789 | } |
064aea77 | 4790 | EXPORT_SYMBOL_GPL(kvm_read_guest_virt); |
1871c602 | 4791 | |
0f65dd70 AK |
4792 | static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt, |
4793 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 4794 | struct x86_exception *exception) |
1871c602 | 4795 | { |
0f65dd70 | 4796 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
bcc55cba | 4797 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception); |
1871c602 GN |
4798 | } |
4799 | ||
7a036a6f RK |
4800 | static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, |
4801 | unsigned long addr, void *val, unsigned int bytes) | |
4802 | { | |
4803 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
4804 | int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); | |
4805 | ||
4806 | return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; | |
4807 | } | |
4808 | ||
6a4d7550 | 4809 | int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt, |
0f65dd70 | 4810 | gva_t addr, void *val, |
2dafc6c2 | 4811 | unsigned int bytes, |
bcc55cba | 4812 | struct x86_exception *exception) |
77c2002e | 4813 | { |
0f65dd70 | 4814 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
77c2002e IE |
4815 | void *data = val; |
4816 | int r = X86EMUL_CONTINUE; | |
4817 | ||
4818 | while (bytes) { | |
14dfe855 JR |
4819 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, |
4820 | PFERR_WRITE_MASK, | |
ab9ae313 | 4821 | exception); |
77c2002e IE |
4822 | unsigned offset = addr & (PAGE_SIZE-1); |
4823 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
4824 | int ret; | |
4825 | ||
bcc55cba | 4826 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 4827 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa | 4828 | ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); |
77c2002e | 4829 | if (ret < 0) { |
c3cd7ffa | 4830 | r = X86EMUL_IO_NEEDED; |
77c2002e IE |
4831 | goto out; |
4832 | } | |
4833 | ||
4834 | bytes -= towrite; | |
4835 | data += towrite; | |
4836 | addr += towrite; | |
4837 | } | |
4838 | out: | |
4839 | return r; | |
4840 | } | |
6a4d7550 | 4841 | EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); |
77c2002e | 4842 | |
0f89b207 TL |
4843 | static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
4844 | gpa_t gpa, bool write) | |
4845 | { | |
4846 | /* For APIC access vmexit */ | |
4847 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
4848 | return 1; | |
4849 | ||
4850 | if (vcpu_match_mmio_gpa(vcpu, gpa)) { | |
4851 | trace_vcpu_match_mmio(gva, gpa, write, true); | |
4852 | return 1; | |
4853 | } | |
4854 | ||
4855 | return 0; | |
4856 | } | |
4857 | ||
af7cc7d1 XG |
4858 | static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
4859 | gpa_t *gpa, struct x86_exception *exception, | |
4860 | bool write) | |
4861 | { | |
97d64b78 AK |
4862 | u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) |
4863 | | (write ? PFERR_WRITE_MASK : 0); | |
af7cc7d1 | 4864 | |
be94f6b7 HH |
4865 | /* |
4866 | * currently PKRU is only applied to ept enabled guest so | |
4867 | * there is no pkey in EPT page table for L1 guest or EPT | |
4868 | * shadow page table for L2 guest. | |
4869 | */ | |
97d64b78 | 4870 | if (vcpu_match_mmio_gva(vcpu, gva) |
97ec8c06 | 4871 | && !permission_fault(vcpu, vcpu->arch.walk_mmu, |
be94f6b7 | 4872 | vcpu->arch.access, 0, access)) { |
bebb106a XG |
4873 | *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | |
4874 | (gva & (PAGE_SIZE - 1)); | |
4f022648 | 4875 | trace_vcpu_match_mmio(gva, *gpa, write, false); |
bebb106a XG |
4876 | return 1; |
4877 | } | |
4878 | ||
af7cc7d1 XG |
4879 | *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
4880 | ||
4881 | if (*gpa == UNMAPPED_GVA) | |
4882 | return -1; | |
4883 | ||
0f89b207 | 4884 | return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); |
af7cc7d1 XG |
4885 | } |
4886 | ||
3200f405 | 4887 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
bcc55cba | 4888 | const void *val, int bytes) |
bbd9b64e CO |
4889 | { |
4890 | int ret; | |
4891 | ||
54bf36aa | 4892 | ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); |
9f811285 | 4893 | if (ret < 0) |
bbd9b64e | 4894 | return 0; |
0eb05bf2 | 4895 | kvm_page_track_write(vcpu, gpa, val, bytes); |
bbd9b64e CO |
4896 | return 1; |
4897 | } | |
4898 | ||
77d197b2 XG |
4899 | struct read_write_emulator_ops { |
4900 | int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, | |
4901 | int bytes); | |
4902 | int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4903 | void *val, int bytes); | |
4904 | int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4905 | int bytes, void *val); | |
4906 | int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4907 | void *val, int bytes); | |
4908 | bool write; | |
4909 | }; | |
4910 | ||
4911 | static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) | |
4912 | { | |
4913 | if (vcpu->mmio_read_completed) { | |
77d197b2 | 4914 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
e39d200f | 4915 | vcpu->mmio_fragments[0].gpa, val); |
77d197b2 XG |
4916 | vcpu->mmio_read_completed = 0; |
4917 | return 1; | |
4918 | } | |
4919 | ||
4920 | return 0; | |
4921 | } | |
4922 | ||
4923 | static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4924 | void *val, int bytes) | |
4925 | { | |
54bf36aa | 4926 | return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); |
77d197b2 XG |
4927 | } |
4928 | ||
4929 | static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4930 | void *val, int bytes) | |
4931 | { | |
4932 | return emulator_write_phys(vcpu, gpa, val, bytes); | |
4933 | } | |
4934 | ||
4935 | static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) | |
4936 | { | |
e39d200f | 4937 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); |
77d197b2 XG |
4938 | return vcpu_mmio_write(vcpu, gpa, bytes, val); |
4939 | } | |
4940 | ||
4941 | static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4942 | void *val, int bytes) | |
4943 | { | |
e39d200f | 4944 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); |
77d197b2 XG |
4945 | return X86EMUL_IO_NEEDED; |
4946 | } | |
4947 | ||
4948 | static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4949 | void *val, int bytes) | |
4950 | { | |
f78146b0 AK |
4951 | struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; |
4952 | ||
87da7e66 | 4953 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); |
77d197b2 XG |
4954 | return X86EMUL_CONTINUE; |
4955 | } | |
4956 | ||
0fbe9b0b | 4957 | static const struct read_write_emulator_ops read_emultor = { |
77d197b2 XG |
4958 | .read_write_prepare = read_prepare, |
4959 | .read_write_emulate = read_emulate, | |
4960 | .read_write_mmio = vcpu_mmio_read, | |
4961 | .read_write_exit_mmio = read_exit_mmio, | |
4962 | }; | |
4963 | ||
0fbe9b0b | 4964 | static const struct read_write_emulator_ops write_emultor = { |
77d197b2 XG |
4965 | .read_write_emulate = write_emulate, |
4966 | .read_write_mmio = write_mmio, | |
4967 | .read_write_exit_mmio = write_exit_mmio, | |
4968 | .write = true, | |
4969 | }; | |
4970 | ||
22388a3c XG |
4971 | static int emulator_read_write_onepage(unsigned long addr, void *val, |
4972 | unsigned int bytes, | |
4973 | struct x86_exception *exception, | |
4974 | struct kvm_vcpu *vcpu, | |
0fbe9b0b | 4975 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 4976 | { |
af7cc7d1 XG |
4977 | gpa_t gpa; |
4978 | int handled, ret; | |
22388a3c | 4979 | bool write = ops->write; |
f78146b0 | 4980 | struct kvm_mmio_fragment *frag; |
0f89b207 TL |
4981 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
4982 | ||
4983 | /* | |
4984 | * If the exit was due to a NPF we may already have a GPA. | |
4985 | * If the GPA is present, use it to avoid the GVA to GPA table walk. | |
4986 | * Note, this cannot be used on string operations since string | |
4987 | * operation using rep will only have the initial GPA from the NPF | |
4988 | * occurred. | |
4989 | */ | |
4990 | if (vcpu->arch.gpa_available && | |
4991 | emulator_can_use_gpa(ctxt) && | |
618232e2 BS |
4992 | (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) { |
4993 | gpa = vcpu->arch.gpa_val; | |
4994 | ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); | |
4995 | } else { | |
4996 | ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); | |
4997 | if (ret < 0) | |
4998 | return X86EMUL_PROPAGATE_FAULT; | |
0f89b207 | 4999 | } |
10589a46 | 5000 | |
618232e2 | 5001 | if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) |
bbd9b64e CO |
5002 | return X86EMUL_CONTINUE; |
5003 | ||
bbd9b64e CO |
5004 | /* |
5005 | * Is this MMIO handled locally? | |
5006 | */ | |
22388a3c | 5007 | handled = ops->read_write_mmio(vcpu, gpa, bytes, val); |
70252a10 | 5008 | if (handled == bytes) |
bbd9b64e | 5009 | return X86EMUL_CONTINUE; |
bbd9b64e | 5010 | |
70252a10 AK |
5011 | gpa += handled; |
5012 | bytes -= handled; | |
5013 | val += handled; | |
5014 | ||
87da7e66 XG |
5015 | WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); |
5016 | frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; | |
5017 | frag->gpa = gpa; | |
5018 | frag->data = val; | |
5019 | frag->len = bytes; | |
f78146b0 | 5020 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
5021 | } |
5022 | ||
52eb5a6d XL |
5023 | static int emulator_read_write(struct x86_emulate_ctxt *ctxt, |
5024 | unsigned long addr, | |
22388a3c XG |
5025 | void *val, unsigned int bytes, |
5026 | struct x86_exception *exception, | |
0fbe9b0b | 5027 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 5028 | { |
0f65dd70 | 5029 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
f78146b0 AK |
5030 | gpa_t gpa; |
5031 | int rc; | |
5032 | ||
5033 | if (ops->read_write_prepare && | |
5034 | ops->read_write_prepare(vcpu, val, bytes)) | |
5035 | return X86EMUL_CONTINUE; | |
5036 | ||
5037 | vcpu->mmio_nr_fragments = 0; | |
0f65dd70 | 5038 | |
bbd9b64e CO |
5039 | /* Crossing a page boundary? */ |
5040 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
f78146b0 | 5041 | int now; |
bbd9b64e CO |
5042 | |
5043 | now = -addr & ~PAGE_MASK; | |
22388a3c XG |
5044 | rc = emulator_read_write_onepage(addr, val, now, exception, |
5045 | vcpu, ops); | |
5046 | ||
bbd9b64e CO |
5047 | if (rc != X86EMUL_CONTINUE) |
5048 | return rc; | |
5049 | addr += now; | |
bac15531 NA |
5050 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
5051 | addr = (u32)addr; | |
bbd9b64e CO |
5052 | val += now; |
5053 | bytes -= now; | |
5054 | } | |
22388a3c | 5055 | |
f78146b0 AK |
5056 | rc = emulator_read_write_onepage(addr, val, bytes, exception, |
5057 | vcpu, ops); | |
5058 | if (rc != X86EMUL_CONTINUE) | |
5059 | return rc; | |
5060 | ||
5061 | if (!vcpu->mmio_nr_fragments) | |
5062 | return rc; | |
5063 | ||
5064 | gpa = vcpu->mmio_fragments[0].gpa; | |
5065 | ||
5066 | vcpu->mmio_needed = 1; | |
5067 | vcpu->mmio_cur_fragment = 0; | |
5068 | ||
87da7e66 | 5069 | vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); |
f78146b0 AK |
5070 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; |
5071 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
5072 | vcpu->run->mmio.phys_addr = gpa; | |
5073 | ||
5074 | return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); | |
22388a3c XG |
5075 | } |
5076 | ||
5077 | static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, | |
5078 | unsigned long addr, | |
5079 | void *val, | |
5080 | unsigned int bytes, | |
5081 | struct x86_exception *exception) | |
5082 | { | |
5083 | return emulator_read_write(ctxt, addr, val, bytes, | |
5084 | exception, &read_emultor); | |
5085 | } | |
5086 | ||
52eb5a6d | 5087 | static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, |
22388a3c XG |
5088 | unsigned long addr, |
5089 | const void *val, | |
5090 | unsigned int bytes, | |
5091 | struct x86_exception *exception) | |
5092 | { | |
5093 | return emulator_read_write(ctxt, addr, (void *)val, bytes, | |
5094 | exception, &write_emultor); | |
bbd9b64e | 5095 | } |
bbd9b64e | 5096 | |
daea3e73 AK |
5097 | #define CMPXCHG_TYPE(t, ptr, old, new) \ |
5098 | (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) | |
5099 | ||
5100 | #ifdef CONFIG_X86_64 | |
5101 | # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) | |
5102 | #else | |
5103 | # define CMPXCHG64(ptr, old, new) \ | |
9749a6c0 | 5104 | (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) |
daea3e73 AK |
5105 | #endif |
5106 | ||
0f65dd70 AK |
5107 | static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, |
5108 | unsigned long addr, | |
bbd9b64e CO |
5109 | const void *old, |
5110 | const void *new, | |
5111 | unsigned int bytes, | |
0f65dd70 | 5112 | struct x86_exception *exception) |
bbd9b64e | 5113 | { |
0f65dd70 | 5114 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
daea3e73 AK |
5115 | gpa_t gpa; |
5116 | struct page *page; | |
5117 | char *kaddr; | |
5118 | bool exchanged; | |
2bacc55c | 5119 | |
daea3e73 AK |
5120 | /* guests cmpxchg8b have to be emulated atomically */ |
5121 | if (bytes > 8 || (bytes & (bytes - 1))) | |
5122 | goto emul_write; | |
10589a46 | 5123 | |
daea3e73 | 5124 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); |
2bacc55c | 5125 | |
daea3e73 AK |
5126 | if (gpa == UNMAPPED_GVA || |
5127 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
5128 | goto emul_write; | |
2bacc55c | 5129 | |
daea3e73 AK |
5130 | if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) |
5131 | goto emul_write; | |
72dc67a6 | 5132 | |
54bf36aa | 5133 | page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT); |
32cad84f | 5134 | if (is_error_page(page)) |
c19b8bd6 | 5135 | goto emul_write; |
72dc67a6 | 5136 | |
8fd75e12 | 5137 | kaddr = kmap_atomic(page); |
daea3e73 AK |
5138 | kaddr += offset_in_page(gpa); |
5139 | switch (bytes) { | |
5140 | case 1: | |
5141 | exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); | |
5142 | break; | |
5143 | case 2: | |
5144 | exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); | |
5145 | break; | |
5146 | case 4: | |
5147 | exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); | |
5148 | break; | |
5149 | case 8: | |
5150 | exchanged = CMPXCHG64(kaddr, old, new); | |
5151 | break; | |
5152 | default: | |
5153 | BUG(); | |
2bacc55c | 5154 | } |
8fd75e12 | 5155 | kunmap_atomic(kaddr); |
daea3e73 AK |
5156 | kvm_release_page_dirty(page); |
5157 | ||
5158 | if (!exchanged) | |
5159 | return X86EMUL_CMPXCHG_FAILED; | |
5160 | ||
54bf36aa | 5161 | kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); |
0eb05bf2 | 5162 | kvm_page_track_write(vcpu, gpa, new, bytes); |
8f6abd06 GN |
5163 | |
5164 | return X86EMUL_CONTINUE; | |
4a5f48f6 | 5165 | |
3200f405 | 5166 | emul_write: |
daea3e73 | 5167 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); |
2bacc55c | 5168 | |
0f65dd70 | 5169 | return emulator_write_emulated(ctxt, addr, new, bytes, exception); |
bbd9b64e CO |
5170 | } |
5171 | ||
cf8f70bf GN |
5172 | static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) |
5173 | { | |
cbfc6c91 | 5174 | int r = 0, i; |
cf8f70bf | 5175 | |
cbfc6c91 WL |
5176 | for (i = 0; i < vcpu->arch.pio.count; i++) { |
5177 | if (vcpu->arch.pio.in) | |
5178 | r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, | |
5179 | vcpu->arch.pio.size, pd); | |
5180 | else | |
5181 | r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, | |
5182 | vcpu->arch.pio.port, vcpu->arch.pio.size, | |
5183 | pd); | |
5184 | if (r) | |
5185 | break; | |
5186 | pd += vcpu->arch.pio.size; | |
5187 | } | |
cf8f70bf GN |
5188 | return r; |
5189 | } | |
5190 | ||
6f6fbe98 XG |
5191 | static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, |
5192 | unsigned short port, void *val, | |
5193 | unsigned int count, bool in) | |
cf8f70bf | 5194 | { |
cf8f70bf | 5195 | vcpu->arch.pio.port = port; |
6f6fbe98 | 5196 | vcpu->arch.pio.in = in; |
7972995b | 5197 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
5198 | vcpu->arch.pio.size = size; |
5199 | ||
5200 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
7972995b | 5201 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
5202 | return 1; |
5203 | } | |
5204 | ||
5205 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
6f6fbe98 | 5206 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; |
cf8f70bf GN |
5207 | vcpu->run->io.size = size; |
5208 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
5209 | vcpu->run->io.count = count; | |
5210 | vcpu->run->io.port = port; | |
5211 | ||
5212 | return 0; | |
5213 | } | |
5214 | ||
6f6fbe98 XG |
5215 | static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
5216 | int size, unsigned short port, void *val, | |
5217 | unsigned int count) | |
cf8f70bf | 5218 | { |
ca1d4a9e | 5219 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
6f6fbe98 | 5220 | int ret; |
ca1d4a9e | 5221 | |
6f6fbe98 XG |
5222 | if (vcpu->arch.pio.count) |
5223 | goto data_avail; | |
cf8f70bf | 5224 | |
cbfc6c91 WL |
5225 | memset(vcpu->arch.pio_data, 0, size * count); |
5226 | ||
6f6fbe98 XG |
5227 | ret = emulator_pio_in_out(vcpu, size, port, val, count, true); |
5228 | if (ret) { | |
5229 | data_avail: | |
5230 | memcpy(val, vcpu->arch.pio_data, size * count); | |
1171903d | 5231 | trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); |
7972995b | 5232 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
5233 | return 1; |
5234 | } | |
5235 | ||
cf8f70bf GN |
5236 | return 0; |
5237 | } | |
5238 | ||
6f6fbe98 XG |
5239 | static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, |
5240 | int size, unsigned short port, | |
5241 | const void *val, unsigned int count) | |
5242 | { | |
5243 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
5244 | ||
5245 | memcpy(vcpu->arch.pio_data, val, size * count); | |
1171903d | 5246 | trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); |
6f6fbe98 XG |
5247 | return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); |
5248 | } | |
5249 | ||
bbd9b64e CO |
5250 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) |
5251 | { | |
5252 | return kvm_x86_ops->get_segment_base(vcpu, seg); | |
5253 | } | |
5254 | ||
3cb16fe7 | 5255 | static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) |
bbd9b64e | 5256 | { |
3cb16fe7 | 5257 | kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); |
bbd9b64e CO |
5258 | } |
5259 | ||
ae6a2375 | 5260 | static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) |
f5f48ee1 SY |
5261 | { |
5262 | if (!need_emulate_wbinvd(vcpu)) | |
5263 | return X86EMUL_CONTINUE; | |
5264 | ||
5265 | if (kvm_x86_ops->has_wbinvd_exit()) { | |
2eec7343 JK |
5266 | int cpu = get_cpu(); |
5267 | ||
5268 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
f5f48ee1 SY |
5269 | smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, |
5270 | wbinvd_ipi, NULL, 1); | |
2eec7343 | 5271 | put_cpu(); |
f5f48ee1 | 5272 | cpumask_clear(vcpu->arch.wbinvd_dirty_mask); |
2eec7343 JK |
5273 | } else |
5274 | wbinvd(); | |
f5f48ee1 SY |
5275 | return X86EMUL_CONTINUE; |
5276 | } | |
5cb56059 JS |
5277 | |
5278 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
5279 | { | |
6affcbed KH |
5280 | kvm_emulate_wbinvd_noskip(vcpu); |
5281 | return kvm_skip_emulated_instruction(vcpu); | |
5cb56059 | 5282 | } |
f5f48ee1 SY |
5283 | EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); |
5284 | ||
5cb56059 JS |
5285 | |
5286 | ||
bcaf5cc5 AK |
5287 | static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) |
5288 | { | |
5cb56059 | 5289 | kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); |
bcaf5cc5 AK |
5290 | } |
5291 | ||
52eb5a6d XL |
5292 | static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, |
5293 | unsigned long *dest) | |
bbd9b64e | 5294 | { |
16f8a6f9 | 5295 | return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); |
bbd9b64e CO |
5296 | } |
5297 | ||
52eb5a6d XL |
5298 | static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, |
5299 | unsigned long value) | |
bbd9b64e | 5300 | { |
338dbc97 | 5301 | |
717746e3 | 5302 | return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); |
bbd9b64e CO |
5303 | } |
5304 | ||
52a46617 | 5305 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) |
5fdbf976 | 5306 | { |
52a46617 | 5307 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; |
5fdbf976 MT |
5308 | } |
5309 | ||
717746e3 | 5310 | static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) |
bbd9b64e | 5311 | { |
717746e3 | 5312 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
52a46617 GN |
5313 | unsigned long value; |
5314 | ||
5315 | switch (cr) { | |
5316 | case 0: | |
5317 | value = kvm_read_cr0(vcpu); | |
5318 | break; | |
5319 | case 2: | |
5320 | value = vcpu->arch.cr2; | |
5321 | break; | |
5322 | case 3: | |
9f8fe504 | 5323 | value = kvm_read_cr3(vcpu); |
52a46617 GN |
5324 | break; |
5325 | case 4: | |
5326 | value = kvm_read_cr4(vcpu); | |
5327 | break; | |
5328 | case 8: | |
5329 | value = kvm_get_cr8(vcpu); | |
5330 | break; | |
5331 | default: | |
a737f256 | 5332 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
52a46617 GN |
5333 | return 0; |
5334 | } | |
5335 | ||
5336 | return value; | |
5337 | } | |
5338 | ||
717746e3 | 5339 | static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) |
52a46617 | 5340 | { |
717746e3 | 5341 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
0f12244f GN |
5342 | int res = 0; |
5343 | ||
52a46617 GN |
5344 | switch (cr) { |
5345 | case 0: | |
49a9b07e | 5346 | res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
52a46617 GN |
5347 | break; |
5348 | case 2: | |
5349 | vcpu->arch.cr2 = val; | |
5350 | break; | |
5351 | case 3: | |
2390218b | 5352 | res = kvm_set_cr3(vcpu, val); |
52a46617 GN |
5353 | break; |
5354 | case 4: | |
a83b29c6 | 5355 | res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
52a46617 GN |
5356 | break; |
5357 | case 8: | |
eea1cff9 | 5358 | res = kvm_set_cr8(vcpu, val); |
52a46617 GN |
5359 | break; |
5360 | default: | |
a737f256 | 5361 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
0f12244f | 5362 | res = -1; |
52a46617 | 5363 | } |
0f12244f GN |
5364 | |
5365 | return res; | |
52a46617 GN |
5366 | } |
5367 | ||
717746e3 | 5368 | static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) |
9c537244 | 5369 | { |
717746e3 | 5370 | return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); |
9c537244 GN |
5371 | } |
5372 | ||
4bff1e86 | 5373 | static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
2dafc6c2 | 5374 | { |
4bff1e86 | 5375 | kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); |
2dafc6c2 GN |
5376 | } |
5377 | ||
4bff1e86 | 5378 | static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
160ce1f1 | 5379 | { |
4bff1e86 | 5380 | kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); |
160ce1f1 MG |
5381 | } |
5382 | ||
1ac9d0cf AK |
5383 | static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
5384 | { | |
5385 | kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); | |
5386 | } | |
5387 | ||
5388 | static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) | |
5389 | { | |
5390 | kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); | |
5391 | } | |
5392 | ||
4bff1e86 AK |
5393 | static unsigned long emulator_get_cached_segment_base( |
5394 | struct x86_emulate_ctxt *ctxt, int seg) | |
5951c442 | 5395 | { |
4bff1e86 | 5396 | return get_segment_base(emul_to_vcpu(ctxt), seg); |
5951c442 GN |
5397 | } |
5398 | ||
1aa36616 AK |
5399 | static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, |
5400 | struct desc_struct *desc, u32 *base3, | |
5401 | int seg) | |
2dafc6c2 GN |
5402 | { |
5403 | struct kvm_segment var; | |
5404 | ||
4bff1e86 | 5405 | kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); |
1aa36616 | 5406 | *selector = var.selector; |
2dafc6c2 | 5407 | |
378a8b09 GN |
5408 | if (var.unusable) { |
5409 | memset(desc, 0, sizeof(*desc)); | |
f0367ee1 RK |
5410 | if (base3) |
5411 | *base3 = 0; | |
2dafc6c2 | 5412 | return false; |
378a8b09 | 5413 | } |
2dafc6c2 GN |
5414 | |
5415 | if (var.g) | |
5416 | var.limit >>= 12; | |
5417 | set_desc_limit(desc, var.limit); | |
5418 | set_desc_base(desc, (unsigned long)var.base); | |
5601d05b GN |
5419 | #ifdef CONFIG_X86_64 |
5420 | if (base3) | |
5421 | *base3 = var.base >> 32; | |
5422 | #endif | |
2dafc6c2 GN |
5423 | desc->type = var.type; |
5424 | desc->s = var.s; | |
5425 | desc->dpl = var.dpl; | |
5426 | desc->p = var.present; | |
5427 | desc->avl = var.avl; | |
5428 | desc->l = var.l; | |
5429 | desc->d = var.db; | |
5430 | desc->g = var.g; | |
5431 | ||
5432 | return true; | |
5433 | } | |
5434 | ||
1aa36616 AK |
5435 | static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, |
5436 | struct desc_struct *desc, u32 base3, | |
5437 | int seg) | |
2dafc6c2 | 5438 | { |
4bff1e86 | 5439 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
2dafc6c2 GN |
5440 | struct kvm_segment var; |
5441 | ||
1aa36616 | 5442 | var.selector = selector; |
2dafc6c2 | 5443 | var.base = get_desc_base(desc); |
5601d05b GN |
5444 | #ifdef CONFIG_X86_64 |
5445 | var.base |= ((u64)base3) << 32; | |
5446 | #endif | |
2dafc6c2 GN |
5447 | var.limit = get_desc_limit(desc); |
5448 | if (desc->g) | |
5449 | var.limit = (var.limit << 12) | 0xfff; | |
5450 | var.type = desc->type; | |
2dafc6c2 GN |
5451 | var.dpl = desc->dpl; |
5452 | var.db = desc->d; | |
5453 | var.s = desc->s; | |
5454 | var.l = desc->l; | |
5455 | var.g = desc->g; | |
5456 | var.avl = desc->avl; | |
5457 | var.present = desc->p; | |
5458 | var.unusable = !var.present; | |
5459 | var.padding = 0; | |
5460 | ||
5461 | kvm_set_segment(vcpu, &var, seg); | |
5462 | return; | |
5463 | } | |
5464 | ||
717746e3 AK |
5465 | static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, |
5466 | u32 msr_index, u64 *pdata) | |
5467 | { | |
609e36d3 PB |
5468 | struct msr_data msr; |
5469 | int r; | |
5470 | ||
5471 | msr.index = msr_index; | |
5472 | msr.host_initiated = false; | |
5473 | r = kvm_get_msr(emul_to_vcpu(ctxt), &msr); | |
5474 | if (r) | |
5475 | return r; | |
5476 | ||
5477 | *pdata = msr.data; | |
5478 | return 0; | |
717746e3 AK |
5479 | } |
5480 | ||
5481 | static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, | |
5482 | u32 msr_index, u64 data) | |
5483 | { | |
8fe8ab46 WA |
5484 | struct msr_data msr; |
5485 | ||
5486 | msr.data = data; | |
5487 | msr.index = msr_index; | |
5488 | msr.host_initiated = false; | |
5489 | return kvm_set_msr(emul_to_vcpu(ctxt), &msr); | |
717746e3 AK |
5490 | } |
5491 | ||
64d60670 PB |
5492 | static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) |
5493 | { | |
5494 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
5495 | ||
5496 | return vcpu->arch.smbase; | |
5497 | } | |
5498 | ||
5499 | static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) | |
5500 | { | |
5501 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
5502 | ||
5503 | vcpu->arch.smbase = smbase; | |
5504 | } | |
5505 | ||
67f4d428 NA |
5506 | static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, |
5507 | u32 pmc) | |
5508 | { | |
c6702c9d | 5509 | return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc); |
67f4d428 NA |
5510 | } |
5511 | ||
222d21aa AK |
5512 | static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, |
5513 | u32 pmc, u64 *pdata) | |
5514 | { | |
c6702c9d | 5515 | return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); |
222d21aa AK |
5516 | } |
5517 | ||
6c3287f7 AK |
5518 | static void emulator_halt(struct x86_emulate_ctxt *ctxt) |
5519 | { | |
5520 | emul_to_vcpu(ctxt)->arch.halt_request = 1; | |
5521 | } | |
5522 | ||
2953538e | 5523 | static int emulator_intercept(struct x86_emulate_ctxt *ctxt, |
8a76d7f2 | 5524 | struct x86_instruction_info *info, |
c4f035c6 AK |
5525 | enum x86_intercept_stage stage) |
5526 | { | |
2953538e | 5527 | return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); |
c4f035c6 AK |
5528 | } |
5529 | ||
e911eb3b YZ |
5530 | static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, |
5531 | u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit) | |
bdb42f5a | 5532 | { |
e911eb3b | 5533 | return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit); |
bdb42f5a SB |
5534 | } |
5535 | ||
dd856efa AK |
5536 | static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) |
5537 | { | |
5538 | return kvm_register_read(emul_to_vcpu(ctxt), reg); | |
5539 | } | |
5540 | ||
5541 | static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) | |
5542 | { | |
5543 | kvm_register_write(emul_to_vcpu(ctxt), reg, val); | |
5544 | } | |
5545 | ||
801806d9 NA |
5546 | static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) |
5547 | { | |
5548 | kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked); | |
5549 | } | |
5550 | ||
6ed071f0 LP |
5551 | static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) |
5552 | { | |
5553 | return emul_to_vcpu(ctxt)->arch.hflags; | |
5554 | } | |
5555 | ||
5556 | static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags) | |
5557 | { | |
5558 | kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags); | |
5559 | } | |
5560 | ||
0234bf88 LP |
5561 | static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase) |
5562 | { | |
5563 | return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase); | |
5564 | } | |
5565 | ||
0225fb50 | 5566 | static const struct x86_emulate_ops emulate_ops = { |
dd856efa AK |
5567 | .read_gpr = emulator_read_gpr, |
5568 | .write_gpr = emulator_write_gpr, | |
1871c602 | 5569 | .read_std = kvm_read_guest_virt_system, |
2dafc6c2 | 5570 | .write_std = kvm_write_guest_virt_system, |
7a036a6f | 5571 | .read_phys = kvm_read_guest_phys_system, |
1871c602 | 5572 | .fetch = kvm_fetch_guest_virt, |
bbd9b64e CO |
5573 | .read_emulated = emulator_read_emulated, |
5574 | .write_emulated = emulator_write_emulated, | |
5575 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
3cb16fe7 | 5576 | .invlpg = emulator_invlpg, |
cf8f70bf GN |
5577 | .pio_in_emulated = emulator_pio_in_emulated, |
5578 | .pio_out_emulated = emulator_pio_out_emulated, | |
1aa36616 AK |
5579 | .get_segment = emulator_get_segment, |
5580 | .set_segment = emulator_set_segment, | |
5951c442 | 5581 | .get_cached_segment_base = emulator_get_cached_segment_base, |
2dafc6c2 | 5582 | .get_gdt = emulator_get_gdt, |
160ce1f1 | 5583 | .get_idt = emulator_get_idt, |
1ac9d0cf AK |
5584 | .set_gdt = emulator_set_gdt, |
5585 | .set_idt = emulator_set_idt, | |
52a46617 GN |
5586 | .get_cr = emulator_get_cr, |
5587 | .set_cr = emulator_set_cr, | |
9c537244 | 5588 | .cpl = emulator_get_cpl, |
35aa5375 GN |
5589 | .get_dr = emulator_get_dr, |
5590 | .set_dr = emulator_set_dr, | |
64d60670 PB |
5591 | .get_smbase = emulator_get_smbase, |
5592 | .set_smbase = emulator_set_smbase, | |
717746e3 AK |
5593 | .set_msr = emulator_set_msr, |
5594 | .get_msr = emulator_get_msr, | |
67f4d428 | 5595 | .check_pmc = emulator_check_pmc, |
222d21aa | 5596 | .read_pmc = emulator_read_pmc, |
6c3287f7 | 5597 | .halt = emulator_halt, |
bcaf5cc5 | 5598 | .wbinvd = emulator_wbinvd, |
d6aa1000 | 5599 | .fix_hypercall = emulator_fix_hypercall, |
c4f035c6 | 5600 | .intercept = emulator_intercept, |
bdb42f5a | 5601 | .get_cpuid = emulator_get_cpuid, |
801806d9 | 5602 | .set_nmi_mask = emulator_set_nmi_mask, |
6ed071f0 LP |
5603 | .get_hflags = emulator_get_hflags, |
5604 | .set_hflags = emulator_set_hflags, | |
0234bf88 | 5605 | .pre_leave_smm = emulator_pre_leave_smm, |
bbd9b64e CO |
5606 | }; |
5607 | ||
95cb2295 GN |
5608 | static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) |
5609 | { | |
37ccdcbe | 5610 | u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); |
95cb2295 GN |
5611 | /* |
5612 | * an sti; sti; sequence only disable interrupts for the first | |
5613 | * instruction. So, if the last instruction, be it emulated or | |
5614 | * not, left the system with the INT_STI flag enabled, it | |
5615 | * means that the last instruction is an sti. We should not | |
5616 | * leave the flag on in this case. The same goes for mov ss | |
5617 | */ | |
37ccdcbe PB |
5618 | if (int_shadow & mask) |
5619 | mask = 0; | |
6addfc42 | 5620 | if (unlikely(int_shadow || mask)) { |
95cb2295 | 5621 | kvm_x86_ops->set_interrupt_shadow(vcpu, mask); |
6addfc42 PB |
5622 | if (!mask) |
5623 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
5624 | } | |
95cb2295 GN |
5625 | } |
5626 | ||
ef54bcfe | 5627 | static bool inject_emulated_exception(struct kvm_vcpu *vcpu) |
54b8486f GN |
5628 | { |
5629 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; | |
da9cb575 | 5630 | if (ctxt->exception.vector == PF_VECTOR) |
ef54bcfe PB |
5631 | return kvm_propagate_fault(vcpu, &ctxt->exception); |
5632 | ||
5633 | if (ctxt->exception.error_code_valid) | |
da9cb575 AK |
5634 | kvm_queue_exception_e(vcpu, ctxt->exception.vector, |
5635 | ctxt->exception.error_code); | |
54b8486f | 5636 | else |
da9cb575 | 5637 | kvm_queue_exception(vcpu, ctxt->exception.vector); |
ef54bcfe | 5638 | return false; |
54b8486f GN |
5639 | } |
5640 | ||
8ec4722d MG |
5641 | static void init_emulate_ctxt(struct kvm_vcpu *vcpu) |
5642 | { | |
adf52235 | 5643 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
8ec4722d MG |
5644 | int cs_db, cs_l; |
5645 | ||
8ec4722d MG |
5646 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
5647 | ||
adf52235 | 5648 | ctxt->eflags = kvm_get_rflags(vcpu); |
c8401dda PB |
5649 | ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; |
5650 | ||
adf52235 TY |
5651 | ctxt->eip = kvm_rip_read(vcpu); |
5652 | ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : | |
5653 | (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : | |
42bf549f | 5654 | (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : |
adf52235 TY |
5655 | cs_db ? X86EMUL_MODE_PROT32 : |
5656 | X86EMUL_MODE_PROT16; | |
a584539b | 5657 | BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); |
64d60670 PB |
5658 | BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); |
5659 | BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); | |
adf52235 | 5660 | |
dd856efa | 5661 | init_decode_cache(ctxt); |
7ae441ea | 5662 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; |
8ec4722d MG |
5663 | } |
5664 | ||
71f9833b | 5665 | int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) |
63995653 | 5666 | { |
9d74191a | 5667 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
63995653 MG |
5668 | int ret; |
5669 | ||
5670 | init_emulate_ctxt(vcpu); | |
5671 | ||
9dac77fa AK |
5672 | ctxt->op_bytes = 2; |
5673 | ctxt->ad_bytes = 2; | |
5674 | ctxt->_eip = ctxt->eip + inc_eip; | |
9d74191a | 5675 | ret = emulate_int_real(ctxt, irq); |
63995653 MG |
5676 | |
5677 | if (ret != X86EMUL_CONTINUE) | |
5678 | return EMULATE_FAIL; | |
5679 | ||
9dac77fa | 5680 | ctxt->eip = ctxt->_eip; |
9d74191a TY |
5681 | kvm_rip_write(vcpu, ctxt->eip); |
5682 | kvm_set_rflags(vcpu, ctxt->eflags); | |
63995653 | 5683 | |
63995653 MG |
5684 | return EMULATE_DONE; |
5685 | } | |
5686 | EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); | |
5687 | ||
e2366171 | 5688 | static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) |
6d77dbfc | 5689 | { |
fc3a9157 JR |
5690 | int r = EMULATE_DONE; |
5691 | ||
6d77dbfc GN |
5692 | ++vcpu->stat.insn_emulation_fail; |
5693 | trace_kvm_emulate_insn_failed(vcpu); | |
e2366171 LA |
5694 | |
5695 | if (emulation_type & EMULTYPE_NO_UD_ON_FAIL) | |
5696 | return EMULATE_FAIL; | |
5697 | ||
a2b9e6c1 | 5698 | if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) { |
fc3a9157 JR |
5699 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
5700 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
5701 | vcpu->run->internal.ndata = 0; | |
1f4dcb3b | 5702 | r = EMULATE_USER_EXIT; |
fc3a9157 | 5703 | } |
e2366171 | 5704 | |
6d77dbfc | 5705 | kvm_queue_exception(vcpu, UD_VECTOR); |
fc3a9157 JR |
5706 | |
5707 | return r; | |
6d77dbfc GN |
5708 | } |
5709 | ||
93c05d3e | 5710 | static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, |
991eebf9 GN |
5711 | bool write_fault_to_shadow_pgtable, |
5712 | int emulation_type) | |
a6f177ef | 5713 | { |
95b3cf69 | 5714 | gpa_t gpa = cr2; |
ba049e93 | 5715 | kvm_pfn_t pfn; |
a6f177ef | 5716 | |
991eebf9 GN |
5717 | if (emulation_type & EMULTYPE_NO_REEXECUTE) |
5718 | return false; | |
5719 | ||
95b3cf69 XG |
5720 | if (!vcpu->arch.mmu.direct_map) { |
5721 | /* | |
5722 | * Write permission should be allowed since only | |
5723 | * write access need to be emulated. | |
5724 | */ | |
5725 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); | |
a6f177ef | 5726 | |
95b3cf69 XG |
5727 | /* |
5728 | * If the mapping is invalid in guest, let cpu retry | |
5729 | * it to generate fault. | |
5730 | */ | |
5731 | if (gpa == UNMAPPED_GVA) | |
5732 | return true; | |
5733 | } | |
a6f177ef | 5734 | |
8e3d9d06 XG |
5735 | /* |
5736 | * Do not retry the unhandleable instruction if it faults on the | |
5737 | * readonly host memory, otherwise it will goto a infinite loop: | |
5738 | * retry instruction -> write #PF -> emulation fail -> retry | |
5739 | * instruction -> ... | |
5740 | */ | |
5741 | pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); | |
95b3cf69 XG |
5742 | |
5743 | /* | |
5744 | * If the instruction failed on the error pfn, it can not be fixed, | |
5745 | * report the error to userspace. | |
5746 | */ | |
5747 | if (is_error_noslot_pfn(pfn)) | |
5748 | return false; | |
5749 | ||
5750 | kvm_release_pfn_clean(pfn); | |
5751 | ||
5752 | /* The instructions are well-emulated on direct mmu. */ | |
5753 | if (vcpu->arch.mmu.direct_map) { | |
5754 | unsigned int indirect_shadow_pages; | |
5755 | ||
5756 | spin_lock(&vcpu->kvm->mmu_lock); | |
5757 | indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; | |
5758 | spin_unlock(&vcpu->kvm->mmu_lock); | |
5759 | ||
5760 | if (indirect_shadow_pages) | |
5761 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
5762 | ||
a6f177ef | 5763 | return true; |
8e3d9d06 | 5764 | } |
a6f177ef | 5765 | |
95b3cf69 XG |
5766 | /* |
5767 | * if emulation was due to access to shadowed page table | |
5768 | * and it failed try to unshadow page and re-enter the | |
5769 | * guest to let CPU execute the instruction. | |
5770 | */ | |
5771 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
93c05d3e XG |
5772 | |
5773 | /* | |
5774 | * If the access faults on its page table, it can not | |
5775 | * be fixed by unprotecting shadow page and it should | |
5776 | * be reported to userspace. | |
5777 | */ | |
5778 | return !write_fault_to_shadow_pgtable; | |
a6f177ef GN |
5779 | } |
5780 | ||
1cb3f3ae XG |
5781 | static bool retry_instruction(struct x86_emulate_ctxt *ctxt, |
5782 | unsigned long cr2, int emulation_type) | |
5783 | { | |
5784 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
5785 | unsigned long last_retry_eip, last_retry_addr, gpa = cr2; | |
5786 | ||
5787 | last_retry_eip = vcpu->arch.last_retry_eip; | |
5788 | last_retry_addr = vcpu->arch.last_retry_addr; | |
5789 | ||
5790 | /* | |
5791 | * If the emulation is caused by #PF and it is non-page_table | |
5792 | * writing instruction, it means the VM-EXIT is caused by shadow | |
5793 | * page protected, we can zap the shadow page and retry this | |
5794 | * instruction directly. | |
5795 | * | |
5796 | * Note: if the guest uses a non-page-table modifying instruction | |
5797 | * on the PDE that points to the instruction, then we will unmap | |
5798 | * the instruction and go to an infinite loop. So, we cache the | |
5799 | * last retried eip and the last fault address, if we meet the eip | |
5800 | * and the address again, we can break out of the potential infinite | |
5801 | * loop. | |
5802 | */ | |
5803 | vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; | |
5804 | ||
5805 | if (!(emulation_type & EMULTYPE_RETRY)) | |
5806 | return false; | |
5807 | ||
5808 | if (x86_page_table_writing_insn(ctxt)) | |
5809 | return false; | |
5810 | ||
5811 | if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) | |
5812 | return false; | |
5813 | ||
5814 | vcpu->arch.last_retry_eip = ctxt->eip; | |
5815 | vcpu->arch.last_retry_addr = cr2; | |
5816 | ||
5817 | if (!vcpu->arch.mmu.direct_map) | |
5818 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); | |
5819 | ||
22368028 | 5820 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); |
1cb3f3ae XG |
5821 | |
5822 | return true; | |
5823 | } | |
5824 | ||
716d51ab GN |
5825 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu); |
5826 | static int complete_emulated_pio(struct kvm_vcpu *vcpu); | |
5827 | ||
64d60670 | 5828 | static void kvm_smm_changed(struct kvm_vcpu *vcpu) |
a584539b | 5829 | { |
64d60670 | 5830 | if (!(vcpu->arch.hflags & HF_SMM_MASK)) { |
660a5d51 PB |
5831 | /* This is a good place to trace that we are exiting SMM. */ |
5832 | trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); | |
5833 | ||
c43203ca PB |
5834 | /* Process a latched INIT or SMI, if any. */ |
5835 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
64d60670 | 5836 | } |
699023e2 PB |
5837 | |
5838 | kvm_mmu_reset_context(vcpu); | |
64d60670 PB |
5839 | } |
5840 | ||
5841 | static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags) | |
5842 | { | |
5843 | unsigned changed = vcpu->arch.hflags ^ emul_flags; | |
5844 | ||
a584539b | 5845 | vcpu->arch.hflags = emul_flags; |
64d60670 PB |
5846 | |
5847 | if (changed & HF_SMM_MASK) | |
5848 | kvm_smm_changed(vcpu); | |
a584539b PB |
5849 | } |
5850 | ||
4a1e10d5 PB |
5851 | static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, |
5852 | unsigned long *db) | |
5853 | { | |
5854 | u32 dr6 = 0; | |
5855 | int i; | |
5856 | u32 enable, rwlen; | |
5857 | ||
5858 | enable = dr7; | |
5859 | rwlen = dr7 >> 16; | |
5860 | for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) | |
5861 | if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) | |
5862 | dr6 |= (1 << i); | |
5863 | return dr6; | |
5864 | } | |
5865 | ||
c8401dda | 5866 | static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r) |
663f4c61 PB |
5867 | { |
5868 | struct kvm_run *kvm_run = vcpu->run; | |
5869 | ||
c8401dda PB |
5870 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { |
5871 | kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM; | |
5872 | kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; | |
5873 | kvm_run->debug.arch.exception = DB_VECTOR; | |
5874 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
5875 | *r = EMULATE_USER_EXIT; | |
5876 | } else { | |
5877 | /* | |
5878 | * "Certain debug exceptions may clear bit 0-3. The | |
5879 | * remaining contents of the DR6 register are never | |
5880 | * cleared by the processor". | |
5881 | */ | |
5882 | vcpu->arch.dr6 &= ~15; | |
5883 | vcpu->arch.dr6 |= DR6_BS | DR6_RTM; | |
5884 | kvm_queue_exception(vcpu, DB_VECTOR); | |
663f4c61 PB |
5885 | } |
5886 | } | |
5887 | ||
6affcbed KH |
5888 | int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) |
5889 | { | |
5890 | unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); | |
5891 | int r = EMULATE_DONE; | |
5892 | ||
5893 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
c8401dda PB |
5894 | |
5895 | /* | |
5896 | * rflags is the old, "raw" value of the flags. The new value has | |
5897 | * not been saved yet. | |
5898 | * | |
5899 | * This is correct even for TF set by the guest, because "the | |
5900 | * processor will not generate this exception after the instruction | |
5901 | * that sets the TF flag". | |
5902 | */ | |
5903 | if (unlikely(rflags & X86_EFLAGS_TF)) | |
5904 | kvm_vcpu_do_singlestep(vcpu, &r); | |
6affcbed KH |
5905 | return r == EMULATE_DONE; |
5906 | } | |
5907 | EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); | |
5908 | ||
4a1e10d5 PB |
5909 | static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) |
5910 | { | |
4a1e10d5 PB |
5911 | if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && |
5912 | (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { | |
82b32774 NA |
5913 | struct kvm_run *kvm_run = vcpu->run; |
5914 | unsigned long eip = kvm_get_linear_rip(vcpu); | |
5915 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
5916 | vcpu->arch.guest_debug_dr7, |
5917 | vcpu->arch.eff_db); | |
5918 | ||
5919 | if (dr6 != 0) { | |
6f43ed01 | 5920 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; |
82b32774 | 5921 | kvm_run->debug.arch.pc = eip; |
4a1e10d5 PB |
5922 | kvm_run->debug.arch.exception = DB_VECTOR; |
5923 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
5924 | *r = EMULATE_USER_EXIT; | |
5925 | return true; | |
5926 | } | |
5927 | } | |
5928 | ||
4161a569 NA |
5929 | if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && |
5930 | !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { | |
82b32774 NA |
5931 | unsigned long eip = kvm_get_linear_rip(vcpu); |
5932 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
5933 | vcpu->arch.dr7, |
5934 | vcpu->arch.db); | |
5935 | ||
5936 | if (dr6 != 0) { | |
5937 | vcpu->arch.dr6 &= ~15; | |
6f43ed01 | 5938 | vcpu->arch.dr6 |= dr6 | DR6_RTM; |
4a1e10d5 PB |
5939 | kvm_queue_exception(vcpu, DB_VECTOR); |
5940 | *r = EMULATE_DONE; | |
5941 | return true; | |
5942 | } | |
5943 | } | |
5944 | ||
5945 | return false; | |
5946 | } | |
5947 | ||
04789b66 LA |
5948 | static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) |
5949 | { | |
2d7921c4 AM |
5950 | switch (ctxt->opcode_len) { |
5951 | case 1: | |
5952 | switch (ctxt->b) { | |
5953 | case 0xe4: /* IN */ | |
5954 | case 0xe5: | |
5955 | case 0xec: | |
5956 | case 0xed: | |
5957 | case 0xe6: /* OUT */ | |
5958 | case 0xe7: | |
5959 | case 0xee: | |
5960 | case 0xef: | |
5961 | case 0x6c: /* INS */ | |
5962 | case 0x6d: | |
5963 | case 0x6e: /* OUTS */ | |
5964 | case 0x6f: | |
5965 | return true; | |
5966 | } | |
5967 | break; | |
5968 | case 2: | |
5969 | switch (ctxt->b) { | |
5970 | case 0x33: /* RDPMC */ | |
5971 | return true; | |
5972 | } | |
5973 | break; | |
04789b66 LA |
5974 | } |
5975 | ||
5976 | return false; | |
5977 | } | |
5978 | ||
51d8b661 AP |
5979 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, |
5980 | unsigned long cr2, | |
dc25e89e AP |
5981 | int emulation_type, |
5982 | void *insn, | |
5983 | int insn_len) | |
bbd9b64e | 5984 | { |
95cb2295 | 5985 | int r; |
9d74191a | 5986 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
7ae441ea | 5987 | bool writeback = true; |
93c05d3e | 5988 | bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; |
bbd9b64e | 5989 | |
93c05d3e XG |
5990 | /* |
5991 | * Clear write_fault_to_shadow_pgtable here to ensure it is | |
5992 | * never reused. | |
5993 | */ | |
5994 | vcpu->arch.write_fault_to_shadow_pgtable = false; | |
26eef70c | 5995 | kvm_clear_exception_queue(vcpu); |
8d7d8102 | 5996 | |
571008da | 5997 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
8ec4722d | 5998 | init_emulate_ctxt(vcpu); |
4a1e10d5 PB |
5999 | |
6000 | /* | |
6001 | * We will reenter on the same instruction since | |
6002 | * we do not set complete_userspace_io. This does not | |
6003 | * handle watchpoints yet, those would be handled in | |
6004 | * the emulate_ops. | |
6005 | */ | |
d391f120 VK |
6006 | if (!(emulation_type & EMULTYPE_SKIP) && |
6007 | kvm_vcpu_check_breakpoint(vcpu, &r)) | |
4a1e10d5 PB |
6008 | return r; |
6009 | ||
9d74191a TY |
6010 | ctxt->interruptibility = 0; |
6011 | ctxt->have_exception = false; | |
e0ad0b47 | 6012 | ctxt->exception.vector = -1; |
9d74191a | 6013 | ctxt->perm_ok = false; |
bbd9b64e | 6014 | |
b51e974f | 6015 | ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; |
4005996e | 6016 | |
9d74191a | 6017 | r = x86_decode_insn(ctxt, insn, insn_len); |
bbd9b64e | 6018 | |
e46479f8 | 6019 | trace_kvm_emulate_insn_start(vcpu); |
f2b5756b | 6020 | ++vcpu->stat.insn_emulation; |
1d2887e2 | 6021 | if (r != EMULATION_OK) { |
4005996e AK |
6022 | if (emulation_type & EMULTYPE_TRAP_UD) |
6023 | return EMULATE_FAIL; | |
991eebf9 GN |
6024 | if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, |
6025 | emulation_type)) | |
bbd9b64e | 6026 | return EMULATE_DONE; |
6ea6e843 PB |
6027 | if (ctxt->have_exception && inject_emulated_exception(vcpu)) |
6028 | return EMULATE_DONE; | |
6d77dbfc GN |
6029 | if (emulation_type & EMULTYPE_SKIP) |
6030 | return EMULATE_FAIL; | |
e2366171 | 6031 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
6032 | } |
6033 | } | |
6034 | ||
04789b66 LA |
6035 | if ((emulation_type & EMULTYPE_VMWARE) && |
6036 | !is_vmware_backdoor_opcode(ctxt)) | |
6037 | return EMULATE_FAIL; | |
6038 | ||
ba8afb6b | 6039 | if (emulation_type & EMULTYPE_SKIP) { |
9dac77fa | 6040 | kvm_rip_write(vcpu, ctxt->_eip); |
bb663c7a NA |
6041 | if (ctxt->eflags & X86_EFLAGS_RF) |
6042 | kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); | |
ba8afb6b GN |
6043 | return EMULATE_DONE; |
6044 | } | |
6045 | ||
1cb3f3ae XG |
6046 | if (retry_instruction(ctxt, cr2, emulation_type)) |
6047 | return EMULATE_DONE; | |
6048 | ||
7ae441ea | 6049 | /* this is needed for vmware backdoor interface to work since it |
4d2179e1 | 6050 | changes registers values during IO operation */ |
7ae441ea GN |
6051 | if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { |
6052 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; | |
dd856efa | 6053 | emulator_invalidate_register_cache(ctxt); |
7ae441ea | 6054 | } |
4d2179e1 | 6055 | |
5cd21917 | 6056 | restart: |
0f89b207 TL |
6057 | /* Save the faulting GPA (cr2) in the address field */ |
6058 | ctxt->exception.address = cr2; | |
6059 | ||
9d74191a | 6060 | r = x86_emulate_insn(ctxt); |
bbd9b64e | 6061 | |
775fde86 JR |
6062 | if (r == EMULATION_INTERCEPTED) |
6063 | return EMULATE_DONE; | |
6064 | ||
d2ddd1c4 | 6065 | if (r == EMULATION_FAILED) { |
991eebf9 GN |
6066 | if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, |
6067 | emulation_type)) | |
c3cd7ffa GN |
6068 | return EMULATE_DONE; |
6069 | ||
e2366171 | 6070 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
6071 | } |
6072 | ||
9d74191a | 6073 | if (ctxt->have_exception) { |
d2ddd1c4 | 6074 | r = EMULATE_DONE; |
ef54bcfe PB |
6075 | if (inject_emulated_exception(vcpu)) |
6076 | return r; | |
d2ddd1c4 | 6077 | } else if (vcpu->arch.pio.count) { |
0912c977 PB |
6078 | if (!vcpu->arch.pio.in) { |
6079 | /* FIXME: return into emulator if single-stepping. */ | |
3457e419 | 6080 | vcpu->arch.pio.count = 0; |
0912c977 | 6081 | } else { |
7ae441ea | 6082 | writeback = false; |
716d51ab GN |
6083 | vcpu->arch.complete_userspace_io = complete_emulated_pio; |
6084 | } | |
ac0a48c3 | 6085 | r = EMULATE_USER_EXIT; |
7ae441ea GN |
6086 | } else if (vcpu->mmio_needed) { |
6087 | if (!vcpu->mmio_is_write) | |
6088 | writeback = false; | |
ac0a48c3 | 6089 | r = EMULATE_USER_EXIT; |
716d51ab | 6090 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; |
7ae441ea | 6091 | } else if (r == EMULATION_RESTART) |
5cd21917 | 6092 | goto restart; |
d2ddd1c4 GN |
6093 | else |
6094 | r = EMULATE_DONE; | |
f850e2e6 | 6095 | |
7ae441ea | 6096 | if (writeback) { |
6addfc42 | 6097 | unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); |
9d74191a | 6098 | toggle_interruptibility(vcpu, ctxt->interruptibility); |
7ae441ea | 6099 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
9d74191a | 6100 | kvm_rip_write(vcpu, ctxt->eip); |
c8401dda PB |
6101 | if (r == EMULATE_DONE && |
6102 | (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) | |
6103 | kvm_vcpu_do_singlestep(vcpu, &r); | |
38827dbd NA |
6104 | if (!ctxt->have_exception || |
6105 | exception_type(ctxt->exception.vector) == EXCPT_TRAP) | |
6106 | __kvm_set_rflags(vcpu, ctxt->eflags); | |
6addfc42 PB |
6107 | |
6108 | /* | |
6109 | * For STI, interrupts are shadowed; so KVM_REQ_EVENT will | |
6110 | * do nothing, and it will be requested again as soon as | |
6111 | * the shadow expires. But we still need to check here, | |
6112 | * because POPF has no interrupt shadow. | |
6113 | */ | |
6114 | if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) | |
6115 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7ae441ea GN |
6116 | } else |
6117 | vcpu->arch.emulate_regs_need_sync_to_vcpu = true; | |
e85d28f8 GN |
6118 | |
6119 | return r; | |
de7d789a | 6120 | } |
51d8b661 | 6121 | EXPORT_SYMBOL_GPL(x86_emulate_instruction); |
de7d789a | 6122 | |
dca7f128 SC |
6123 | static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, |
6124 | unsigned short port) | |
de7d789a | 6125 | { |
cf8f70bf | 6126 | unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); |
ca1d4a9e AK |
6127 | int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, |
6128 | size, port, &val, 1); | |
cf8f70bf | 6129 | /* do not return to emulator after return from userspace */ |
7972995b | 6130 | vcpu->arch.pio.count = 0; |
de7d789a CO |
6131 | return ret; |
6132 | } | |
de7d789a | 6133 | |
8370c3d0 TL |
6134 | static int complete_fast_pio_in(struct kvm_vcpu *vcpu) |
6135 | { | |
6136 | unsigned long val; | |
6137 | ||
6138 | /* We should only ever be called with arch.pio.count equal to 1 */ | |
6139 | BUG_ON(vcpu->arch.pio.count != 1); | |
6140 | ||
6141 | /* For size less than 4 we merge, else we zero extend */ | |
6142 | val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) | |
6143 | : 0; | |
6144 | ||
6145 | /* | |
6146 | * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform | |
6147 | * the copy and tracing | |
6148 | */ | |
6149 | emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size, | |
6150 | vcpu->arch.pio.port, &val, 1); | |
6151 | kvm_register_write(vcpu, VCPU_REGS_RAX, val); | |
6152 | ||
6153 | return 1; | |
6154 | } | |
6155 | ||
dca7f128 SC |
6156 | static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, |
6157 | unsigned short port) | |
8370c3d0 TL |
6158 | { |
6159 | unsigned long val; | |
6160 | int ret; | |
6161 | ||
6162 | /* For size less than 4 we merge, else we zero extend */ | |
6163 | val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0; | |
6164 | ||
6165 | ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port, | |
6166 | &val, 1); | |
6167 | if (ret) { | |
6168 | kvm_register_write(vcpu, VCPU_REGS_RAX, val); | |
6169 | return ret; | |
6170 | } | |
6171 | ||
6172 | vcpu->arch.complete_userspace_io = complete_fast_pio_in; | |
6173 | ||
6174 | return 0; | |
6175 | } | |
dca7f128 SC |
6176 | |
6177 | int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) | |
6178 | { | |
6179 | int ret = kvm_skip_emulated_instruction(vcpu); | |
6180 | ||
6181 | /* | |
6182 | * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered | |
6183 | * KVM_EXIT_DEBUG here. | |
6184 | */ | |
6185 | if (in) | |
6186 | return kvm_fast_pio_in(vcpu, size, port) && ret; | |
6187 | else | |
6188 | return kvm_fast_pio_out(vcpu, size, port) && ret; | |
6189 | } | |
6190 | EXPORT_SYMBOL_GPL(kvm_fast_pio); | |
8370c3d0 | 6191 | |
251a5fd6 | 6192 | static int kvmclock_cpu_down_prep(unsigned int cpu) |
8cfdc000 | 6193 | { |
0a3aee0d | 6194 | __this_cpu_write(cpu_tsc_khz, 0); |
251a5fd6 | 6195 | return 0; |
8cfdc000 ZA |
6196 | } |
6197 | ||
6198 | static void tsc_khz_changed(void *data) | |
c8076604 | 6199 | { |
8cfdc000 ZA |
6200 | struct cpufreq_freqs *freq = data; |
6201 | unsigned long khz = 0; | |
6202 | ||
6203 | if (data) | |
6204 | khz = freq->new; | |
6205 | else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
6206 | khz = cpufreq_quick_get(raw_smp_processor_id()); | |
6207 | if (!khz) | |
6208 | khz = tsc_khz; | |
0a3aee0d | 6209 | __this_cpu_write(cpu_tsc_khz, khz); |
c8076604 GH |
6210 | } |
6211 | ||
5fa4ec9c | 6212 | #ifdef CONFIG_X86_64 |
0092e434 VK |
6213 | static void kvm_hyperv_tsc_notifier(void) |
6214 | { | |
0092e434 VK |
6215 | struct kvm *kvm; |
6216 | struct kvm_vcpu *vcpu; | |
6217 | int cpu; | |
6218 | ||
6219 | spin_lock(&kvm_lock); | |
6220 | list_for_each_entry(kvm, &vm_list, vm_list) | |
6221 | kvm_make_mclock_inprogress_request(kvm); | |
6222 | ||
6223 | hyperv_stop_tsc_emulation(); | |
6224 | ||
6225 | /* TSC frequency always matches when on Hyper-V */ | |
6226 | for_each_present_cpu(cpu) | |
6227 | per_cpu(cpu_tsc_khz, cpu) = tsc_khz; | |
6228 | kvm_max_guest_tsc_khz = tsc_khz; | |
6229 | ||
6230 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
6231 | struct kvm_arch *ka = &kvm->arch; | |
6232 | ||
6233 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
6234 | ||
6235 | pvclock_update_vm_gtod_copy(kvm); | |
6236 | ||
6237 | kvm_for_each_vcpu(cpu, vcpu, kvm) | |
6238 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
6239 | ||
6240 | kvm_for_each_vcpu(cpu, vcpu, kvm) | |
6241 | kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); | |
6242 | ||
6243 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
6244 | } | |
6245 | spin_unlock(&kvm_lock); | |
0092e434 | 6246 | } |
5fa4ec9c | 6247 | #endif |
0092e434 | 6248 | |
c8076604 GH |
6249 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, |
6250 | void *data) | |
6251 | { | |
6252 | struct cpufreq_freqs *freq = data; | |
6253 | struct kvm *kvm; | |
6254 | struct kvm_vcpu *vcpu; | |
6255 | int i, send_ipi = 0; | |
6256 | ||
8cfdc000 ZA |
6257 | /* |
6258 | * We allow guests to temporarily run on slowing clocks, | |
6259 | * provided we notify them after, or to run on accelerating | |
6260 | * clocks, provided we notify them before. Thus time never | |
6261 | * goes backwards. | |
6262 | * | |
6263 | * However, we have a problem. We can't atomically update | |
6264 | * the frequency of a given CPU from this function; it is | |
6265 | * merely a notifier, which can be called from any CPU. | |
6266 | * Changing the TSC frequency at arbitrary points in time | |
6267 | * requires a recomputation of local variables related to | |
6268 | * the TSC for each VCPU. We must flag these local variables | |
6269 | * to be updated and be sure the update takes place with the | |
6270 | * new frequency before any guests proceed. | |
6271 | * | |
6272 | * Unfortunately, the combination of hotplug CPU and frequency | |
6273 | * change creates an intractable locking scenario; the order | |
6274 | * of when these callouts happen is undefined with respect to | |
6275 | * CPU hotplug, and they can race with each other. As such, | |
6276 | * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is | |
6277 | * undefined; you can actually have a CPU frequency change take | |
6278 | * place in between the computation of X and the setting of the | |
6279 | * variable. To protect against this problem, all updates of | |
6280 | * the per_cpu tsc_khz variable are done in an interrupt | |
6281 | * protected IPI, and all callers wishing to update the value | |
6282 | * must wait for a synchronous IPI to complete (which is trivial | |
6283 | * if the caller is on the CPU already). This establishes the | |
6284 | * necessary total order on variable updates. | |
6285 | * | |
6286 | * Note that because a guest time update may take place | |
6287 | * anytime after the setting of the VCPU's request bit, the | |
6288 | * correct TSC value must be set before the request. However, | |
6289 | * to ensure the update actually makes it to any guest which | |
6290 | * starts running in hardware virtualization between the set | |
6291 | * and the acquisition of the spinlock, we must also ping the | |
6292 | * CPU after setting the request bit. | |
6293 | * | |
6294 | */ | |
6295 | ||
c8076604 GH |
6296 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) |
6297 | return 0; | |
6298 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
6299 | return 0; | |
8cfdc000 ZA |
6300 | |
6301 | smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); | |
c8076604 | 6302 | |
2f303b74 | 6303 | spin_lock(&kvm_lock); |
c8076604 | 6304 | list_for_each_entry(kvm, &vm_list, vm_list) { |
988a2cae | 6305 | kvm_for_each_vcpu(i, vcpu, kvm) { |
c8076604 GH |
6306 | if (vcpu->cpu != freq->cpu) |
6307 | continue; | |
c285545f | 6308 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
c8076604 | 6309 | if (vcpu->cpu != smp_processor_id()) |
8cfdc000 | 6310 | send_ipi = 1; |
c8076604 GH |
6311 | } |
6312 | } | |
2f303b74 | 6313 | spin_unlock(&kvm_lock); |
c8076604 GH |
6314 | |
6315 | if (freq->old < freq->new && send_ipi) { | |
6316 | /* | |
6317 | * We upscale the frequency. Must make the guest | |
6318 | * doesn't see old kvmclock values while running with | |
6319 | * the new frequency, otherwise we risk the guest sees | |
6320 | * time go backwards. | |
6321 | * | |
6322 | * In case we update the frequency for another cpu | |
6323 | * (which might be in guest context) send an interrupt | |
6324 | * to kick the cpu out of guest context. Next time | |
6325 | * guest context is entered kvmclock will be updated, | |
6326 | * so the guest will not see stale values. | |
6327 | */ | |
8cfdc000 | 6328 | smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); |
c8076604 GH |
6329 | } |
6330 | return 0; | |
6331 | } | |
6332 | ||
6333 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
8cfdc000 ZA |
6334 | .notifier_call = kvmclock_cpufreq_notifier |
6335 | }; | |
6336 | ||
251a5fd6 | 6337 | static int kvmclock_cpu_online(unsigned int cpu) |
8cfdc000 | 6338 | { |
251a5fd6 SAS |
6339 | tsc_khz_changed(NULL); |
6340 | return 0; | |
8cfdc000 ZA |
6341 | } |
6342 | ||
b820cc0c ZA |
6343 | static void kvm_timer_init(void) |
6344 | { | |
c285545f | 6345 | max_tsc_khz = tsc_khz; |
460dd42e | 6346 | |
b820cc0c | 6347 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
c285545f ZA |
6348 | #ifdef CONFIG_CPU_FREQ |
6349 | struct cpufreq_policy policy; | |
758f588d BP |
6350 | int cpu; |
6351 | ||
c285545f | 6352 | memset(&policy, 0, sizeof(policy)); |
3e26f230 AK |
6353 | cpu = get_cpu(); |
6354 | cpufreq_get_policy(&policy, cpu); | |
c285545f ZA |
6355 | if (policy.cpuinfo.max_freq) |
6356 | max_tsc_khz = policy.cpuinfo.max_freq; | |
3e26f230 | 6357 | put_cpu(); |
c285545f | 6358 | #endif |
b820cc0c ZA |
6359 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
6360 | CPUFREQ_TRANSITION_NOTIFIER); | |
6361 | } | |
c285545f | 6362 | pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); |
460dd42e | 6363 | |
73c1b41e | 6364 | cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", |
251a5fd6 | 6365 | kvmclock_cpu_online, kvmclock_cpu_down_prep); |
b820cc0c ZA |
6366 | } |
6367 | ||
dd60d217 AK |
6368 | DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); |
6369 | EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu); | |
ff9d07a0 | 6370 | |
f5132b01 | 6371 | int kvm_is_in_guest(void) |
ff9d07a0 | 6372 | { |
086c9855 | 6373 | return __this_cpu_read(current_vcpu) != NULL; |
ff9d07a0 ZY |
6374 | } |
6375 | ||
6376 | static int kvm_is_user_mode(void) | |
6377 | { | |
6378 | int user_mode = 3; | |
dcf46b94 | 6379 | |
086c9855 AS |
6380 | if (__this_cpu_read(current_vcpu)) |
6381 | user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 6382 | |
ff9d07a0 ZY |
6383 | return user_mode != 0; |
6384 | } | |
6385 | ||
6386 | static unsigned long kvm_get_guest_ip(void) | |
6387 | { | |
6388 | unsigned long ip = 0; | |
dcf46b94 | 6389 | |
086c9855 AS |
6390 | if (__this_cpu_read(current_vcpu)) |
6391 | ip = kvm_rip_read(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 6392 | |
ff9d07a0 ZY |
6393 | return ip; |
6394 | } | |
6395 | ||
6396 | static struct perf_guest_info_callbacks kvm_guest_cbs = { | |
6397 | .is_in_guest = kvm_is_in_guest, | |
6398 | .is_user_mode = kvm_is_user_mode, | |
6399 | .get_guest_ip = kvm_get_guest_ip, | |
6400 | }; | |
6401 | ||
ce88decf XG |
6402 | static void kvm_set_mmio_spte_mask(void) |
6403 | { | |
6404 | u64 mask; | |
6405 | int maxphyaddr = boot_cpu_data.x86_phys_bits; | |
6406 | ||
6407 | /* | |
6408 | * Set the reserved bits and the present bit of an paging-structure | |
6409 | * entry to generate page fault with PFER.RSV = 1. | |
6410 | */ | |
885032b9 | 6411 | /* Mask the reserved physical address bits. */ |
d1431483 | 6412 | mask = rsvd_bits(maxphyaddr, 51); |
885032b9 | 6413 | |
885032b9 | 6414 | /* Set the present bit. */ |
ce88decf XG |
6415 | mask |= 1ull; |
6416 | ||
6417 | #ifdef CONFIG_X86_64 | |
6418 | /* | |
6419 | * If reserved bit is not supported, clear the present bit to disable | |
6420 | * mmio page fault. | |
6421 | */ | |
6422 | if (maxphyaddr == 52) | |
6423 | mask &= ~1ull; | |
6424 | #endif | |
6425 | ||
dcdca5fe | 6426 | kvm_mmu_set_mmio_spte_mask(mask, mask); |
ce88decf XG |
6427 | } |
6428 | ||
16e8d74d MT |
6429 | #ifdef CONFIG_X86_64 |
6430 | static void pvclock_gtod_update_fn(struct work_struct *work) | |
6431 | { | |
d828199e MT |
6432 | struct kvm *kvm; |
6433 | ||
6434 | struct kvm_vcpu *vcpu; | |
6435 | int i; | |
6436 | ||
2f303b74 | 6437 | spin_lock(&kvm_lock); |
d828199e MT |
6438 | list_for_each_entry(kvm, &vm_list, vm_list) |
6439 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 6440 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
d828199e | 6441 | atomic_set(&kvm_guest_has_master_clock, 0); |
2f303b74 | 6442 | spin_unlock(&kvm_lock); |
16e8d74d MT |
6443 | } |
6444 | ||
6445 | static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); | |
6446 | ||
6447 | /* | |
6448 | * Notification about pvclock gtod data update. | |
6449 | */ | |
6450 | static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, | |
6451 | void *priv) | |
6452 | { | |
6453 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
6454 | struct timekeeper *tk = priv; | |
6455 | ||
6456 | update_pvclock_gtod(tk); | |
6457 | ||
6458 | /* disable master clock if host does not trust, or does not | |
b0c39dc6 | 6459 | * use, TSC based clocksource. |
16e8d74d | 6460 | */ |
b0c39dc6 | 6461 | if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && |
16e8d74d MT |
6462 | atomic_read(&kvm_guest_has_master_clock) != 0) |
6463 | queue_work(system_long_wq, &pvclock_gtod_work); | |
6464 | ||
6465 | return 0; | |
6466 | } | |
6467 | ||
6468 | static struct notifier_block pvclock_gtod_notifier = { | |
6469 | .notifier_call = pvclock_gtod_notify, | |
6470 | }; | |
6471 | #endif | |
6472 | ||
f8c16bba | 6473 | int kvm_arch_init(void *opaque) |
043405e1 | 6474 | { |
b820cc0c | 6475 | int r; |
6b61edf7 | 6476 | struct kvm_x86_ops *ops = opaque; |
f8c16bba | 6477 | |
f8c16bba ZX |
6478 | if (kvm_x86_ops) { |
6479 | printk(KERN_ERR "kvm: already loaded the other module\n"); | |
56c6d28a ZX |
6480 | r = -EEXIST; |
6481 | goto out; | |
f8c16bba ZX |
6482 | } |
6483 | ||
6484 | if (!ops->cpu_has_kvm_support()) { | |
6485 | printk(KERN_ERR "kvm: no hardware support\n"); | |
56c6d28a ZX |
6486 | r = -EOPNOTSUPP; |
6487 | goto out; | |
f8c16bba ZX |
6488 | } |
6489 | if (ops->disabled_by_bios()) { | |
6490 | printk(KERN_ERR "kvm: disabled by bios\n"); | |
56c6d28a ZX |
6491 | r = -EOPNOTSUPP; |
6492 | goto out; | |
f8c16bba ZX |
6493 | } |
6494 | ||
013f6a5d MT |
6495 | r = -ENOMEM; |
6496 | shared_msrs = alloc_percpu(struct kvm_shared_msrs); | |
6497 | if (!shared_msrs) { | |
6498 | printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); | |
6499 | goto out; | |
6500 | } | |
6501 | ||
97db56ce AK |
6502 | r = kvm_mmu_module_init(); |
6503 | if (r) | |
013f6a5d | 6504 | goto out_free_percpu; |
97db56ce | 6505 | |
ce88decf | 6506 | kvm_set_mmio_spte_mask(); |
97db56ce | 6507 | |
f8c16bba | 6508 | kvm_x86_ops = ops; |
920c8377 | 6509 | |
7b52345e | 6510 | kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, |
ffb128c8 | 6511 | PT_DIRTY_MASK, PT64_NX_MASK, 0, |
d0ec49d4 | 6512 | PT_PRESENT_MASK, 0, sme_me_mask); |
b820cc0c | 6513 | kvm_timer_init(); |
c8076604 | 6514 | |
ff9d07a0 ZY |
6515 | perf_register_guest_info_callbacks(&kvm_guest_cbs); |
6516 | ||
d366bf7e | 6517 | if (boot_cpu_has(X86_FEATURE_XSAVE)) |
2acf923e DC |
6518 | host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); |
6519 | ||
c5cc421b | 6520 | kvm_lapic_init(); |
16e8d74d MT |
6521 | #ifdef CONFIG_X86_64 |
6522 | pvclock_gtod_register_notifier(&pvclock_gtod_notifier); | |
0092e434 | 6523 | |
5fa4ec9c | 6524 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 | 6525 | set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); |
16e8d74d MT |
6526 | #endif |
6527 | ||
f8c16bba | 6528 | return 0; |
56c6d28a | 6529 | |
013f6a5d MT |
6530 | out_free_percpu: |
6531 | free_percpu(shared_msrs); | |
56c6d28a | 6532 | out: |
56c6d28a | 6533 | return r; |
043405e1 | 6534 | } |
8776e519 | 6535 | |
f8c16bba ZX |
6536 | void kvm_arch_exit(void) |
6537 | { | |
0092e434 | 6538 | #ifdef CONFIG_X86_64 |
5fa4ec9c | 6539 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 VK |
6540 | clear_hv_tscchange_cb(); |
6541 | #endif | |
cef84c30 | 6542 | kvm_lapic_exit(); |
ff9d07a0 ZY |
6543 | perf_unregister_guest_info_callbacks(&kvm_guest_cbs); |
6544 | ||
888d256e JK |
6545 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
6546 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
6547 | CPUFREQ_TRANSITION_NOTIFIER); | |
251a5fd6 | 6548 | cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); |
16e8d74d MT |
6549 | #ifdef CONFIG_X86_64 |
6550 | pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); | |
6551 | #endif | |
f8c16bba | 6552 | kvm_x86_ops = NULL; |
56c6d28a | 6553 | kvm_mmu_module_exit(); |
013f6a5d | 6554 | free_percpu(shared_msrs); |
56c6d28a | 6555 | } |
f8c16bba | 6556 | |
5cb56059 | 6557 | int kvm_vcpu_halt(struct kvm_vcpu *vcpu) |
8776e519 HB |
6558 | { |
6559 | ++vcpu->stat.halt_exits; | |
35754c98 | 6560 | if (lapic_in_kernel(vcpu)) { |
a4535290 | 6561 | vcpu->arch.mp_state = KVM_MP_STATE_HALTED; |
8776e519 HB |
6562 | return 1; |
6563 | } else { | |
6564 | vcpu->run->exit_reason = KVM_EXIT_HLT; | |
6565 | return 0; | |
6566 | } | |
6567 | } | |
5cb56059 JS |
6568 | EXPORT_SYMBOL_GPL(kvm_vcpu_halt); |
6569 | ||
6570 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) | |
6571 | { | |
6affcbed KH |
6572 | int ret = kvm_skip_emulated_instruction(vcpu); |
6573 | /* | |
6574 | * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered | |
6575 | * KVM_EXIT_DEBUG here. | |
6576 | */ | |
6577 | return kvm_vcpu_halt(vcpu) && ret; | |
5cb56059 | 6578 | } |
8776e519 HB |
6579 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); |
6580 | ||
8ef81a9a | 6581 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
6582 | static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, |
6583 | unsigned long clock_type) | |
6584 | { | |
6585 | struct kvm_clock_pairing clock_pairing; | |
6586 | struct timespec ts; | |
80fbd89c | 6587 | u64 cycle; |
55dd00a7 MT |
6588 | int ret; |
6589 | ||
6590 | if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) | |
6591 | return -KVM_EOPNOTSUPP; | |
6592 | ||
6593 | if (kvm_get_walltime_and_clockread(&ts, &cycle) == false) | |
6594 | return -KVM_EOPNOTSUPP; | |
6595 | ||
6596 | clock_pairing.sec = ts.tv_sec; | |
6597 | clock_pairing.nsec = ts.tv_nsec; | |
6598 | clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); | |
6599 | clock_pairing.flags = 0; | |
6600 | ||
6601 | ret = 0; | |
6602 | if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, | |
6603 | sizeof(struct kvm_clock_pairing))) | |
6604 | ret = -KVM_EFAULT; | |
6605 | ||
6606 | return ret; | |
6607 | } | |
8ef81a9a | 6608 | #endif |
55dd00a7 | 6609 | |
6aef266c SV |
6610 | /* |
6611 | * kvm_pv_kick_cpu_op: Kick a vcpu. | |
6612 | * | |
6613 | * @apicid - apicid of vcpu to be kicked. | |
6614 | */ | |
6615 | static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) | |
6616 | { | |
24d2166b | 6617 | struct kvm_lapic_irq lapic_irq; |
6aef266c | 6618 | |
24d2166b R |
6619 | lapic_irq.shorthand = 0; |
6620 | lapic_irq.dest_mode = 0; | |
ebd28fcb | 6621 | lapic_irq.level = 0; |
24d2166b | 6622 | lapic_irq.dest_id = apicid; |
93bbf0b8 | 6623 | lapic_irq.msi_redir_hint = false; |
6aef266c | 6624 | |
24d2166b | 6625 | lapic_irq.delivery_mode = APIC_DM_REMRD; |
795a149e | 6626 | kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); |
6aef266c SV |
6627 | } |
6628 | ||
d62caabb AS |
6629 | void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu) |
6630 | { | |
6631 | vcpu->arch.apicv_active = false; | |
6632 | kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu); | |
6633 | } | |
6634 | ||
8776e519 HB |
6635 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
6636 | { | |
6637 | unsigned long nr, a0, a1, a2, a3, ret; | |
6affcbed | 6638 | int op_64_bit, r; |
8776e519 | 6639 | |
6affcbed | 6640 | r = kvm_skip_emulated_instruction(vcpu); |
5cb56059 | 6641 | |
55cd8e5a GN |
6642 | if (kvm_hv_hypercall_enabled(vcpu->kvm)) |
6643 | return kvm_hv_hypercall(vcpu); | |
6644 | ||
5fdbf976 MT |
6645 | nr = kvm_register_read(vcpu, VCPU_REGS_RAX); |
6646 | a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
6647 | a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
6648 | a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
6649 | a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
8776e519 | 6650 | |
229456fc | 6651 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 6652 | |
a449c7aa NA |
6653 | op_64_bit = is_64_bit_mode(vcpu); |
6654 | if (!op_64_bit) { | |
8776e519 HB |
6655 | nr &= 0xFFFFFFFF; |
6656 | a0 &= 0xFFFFFFFF; | |
6657 | a1 &= 0xFFFFFFFF; | |
6658 | a2 &= 0xFFFFFFFF; | |
6659 | a3 &= 0xFFFFFFFF; | |
6660 | } | |
6661 | ||
07708c4a JK |
6662 | if (kvm_x86_ops->get_cpl(vcpu) != 0) { |
6663 | ret = -KVM_EPERM; | |
6664 | goto out; | |
6665 | } | |
6666 | ||
8776e519 | 6667 | switch (nr) { |
b93463aa AK |
6668 | case KVM_HC_VAPIC_POLL_IRQ: |
6669 | ret = 0; | |
6670 | break; | |
6aef266c SV |
6671 | case KVM_HC_KICK_CPU: |
6672 | kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); | |
6673 | ret = 0; | |
6674 | break; | |
8ef81a9a | 6675 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
6676 | case KVM_HC_CLOCK_PAIRING: |
6677 | ret = kvm_pv_clock_pairing(vcpu, a0, a1); | |
6678 | break; | |
8ef81a9a | 6679 | #endif |
8776e519 HB |
6680 | default: |
6681 | ret = -KVM_ENOSYS; | |
6682 | break; | |
6683 | } | |
07708c4a | 6684 | out: |
a449c7aa NA |
6685 | if (!op_64_bit) |
6686 | ret = (u32)ret; | |
5fdbf976 | 6687 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); |
f11c3a8d | 6688 | ++vcpu->stat.hypercalls; |
2f333bcb | 6689 | return r; |
8776e519 HB |
6690 | } |
6691 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
6692 | ||
b6785def | 6693 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) |
8776e519 | 6694 | { |
d6aa1000 | 6695 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
8776e519 | 6696 | char instruction[3]; |
5fdbf976 | 6697 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 6698 | |
8776e519 | 6699 | kvm_x86_ops->patch_hypercall(vcpu, instruction); |
8776e519 | 6700 | |
ce2e852e DV |
6701 | return emulator_write_emulated(ctxt, rip, instruction, 3, |
6702 | &ctxt->exception); | |
8776e519 HB |
6703 | } |
6704 | ||
851ba692 | 6705 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 6706 | { |
782d422b MG |
6707 | return vcpu->run->request_interrupt_window && |
6708 | likely(!pic_in_kernel(vcpu->kvm)); | |
b6c7a5dc HB |
6709 | } |
6710 | ||
851ba692 | 6711 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 6712 | { |
851ba692 AK |
6713 | struct kvm_run *kvm_run = vcpu->run; |
6714 | ||
91586a3b | 6715 | kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; |
f077825a | 6716 | kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0; |
2d3ad1f4 | 6717 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 6718 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
127a457a MG |
6719 | kvm_run->ready_for_interrupt_injection = |
6720 | pic_in_kernel(vcpu->kvm) || | |
782d422b | 6721 | kvm_vcpu_ready_for_interrupt_injection(vcpu); |
b6c7a5dc HB |
6722 | } |
6723 | ||
95ba8273 GN |
6724 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
6725 | { | |
6726 | int max_irr, tpr; | |
6727 | ||
6728 | if (!kvm_x86_ops->update_cr8_intercept) | |
6729 | return; | |
6730 | ||
bce87cce | 6731 | if (!lapic_in_kernel(vcpu)) |
88c808fd AK |
6732 | return; |
6733 | ||
d62caabb AS |
6734 | if (vcpu->arch.apicv_active) |
6735 | return; | |
6736 | ||
8db3baa2 GN |
6737 | if (!vcpu->arch.apic->vapic_addr) |
6738 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
6739 | else | |
6740 | max_irr = -1; | |
95ba8273 GN |
6741 | |
6742 | if (max_irr != -1) | |
6743 | max_irr >>= 4; | |
6744 | ||
6745 | tpr = kvm_lapic_get_cr8(vcpu); | |
6746 | ||
6747 | kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); | |
6748 | } | |
6749 | ||
b6b8a145 | 6750 | static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) |
95ba8273 | 6751 | { |
b6b8a145 JK |
6752 | int r; |
6753 | ||
95ba8273 | 6754 | /* try to reinject previous events if any */ |
664f8e26 WL |
6755 | if (vcpu->arch.exception.injected) { |
6756 | kvm_x86_ops->queue_exception(vcpu); | |
6757 | return 0; | |
6758 | } | |
6759 | ||
6760 | /* | |
6761 | * Exceptions must be injected immediately, or the exception | |
6762 | * frame will have the address of the NMI or interrupt handler. | |
6763 | */ | |
6764 | if (!vcpu->arch.exception.pending) { | |
6765 | if (vcpu->arch.nmi_injected) { | |
6766 | kvm_x86_ops->set_nmi(vcpu); | |
6767 | return 0; | |
6768 | } | |
6769 | ||
6770 | if (vcpu->arch.interrupt.pending) { | |
6771 | kvm_x86_ops->set_irq(vcpu); | |
6772 | return 0; | |
6773 | } | |
6774 | } | |
6775 | ||
6776 | if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { | |
6777 | r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); | |
6778 | if (r != 0) | |
6779 | return r; | |
6780 | } | |
6781 | ||
6782 | /* try to inject new event if pending */ | |
b59bb7bd | 6783 | if (vcpu->arch.exception.pending) { |
5c1c85d0 AK |
6784 | trace_kvm_inj_exception(vcpu->arch.exception.nr, |
6785 | vcpu->arch.exception.has_error_code, | |
6786 | vcpu->arch.exception.error_code); | |
d6e8c854 | 6787 | |
664f8e26 WL |
6788 | vcpu->arch.exception.pending = false; |
6789 | vcpu->arch.exception.injected = true; | |
6790 | ||
d6e8c854 NA |
6791 | if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) |
6792 | __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | | |
6793 | X86_EFLAGS_RF); | |
6794 | ||
6bdf0662 NA |
6795 | if (vcpu->arch.exception.nr == DB_VECTOR && |
6796 | (vcpu->arch.dr7 & DR7_GD)) { | |
6797 | vcpu->arch.dr7 &= ~DR7_GD; | |
6798 | kvm_update_dr7(vcpu); | |
6799 | } | |
6800 | ||
cfcd20e5 | 6801 | kvm_x86_ops->queue_exception(vcpu); |
72d7b374 | 6802 | } else if (vcpu->arch.smi_pending && !is_smm(vcpu) && kvm_x86_ops->smi_allowed(vcpu)) { |
c43203ca | 6803 | vcpu->arch.smi_pending = false; |
52797bf9 | 6804 | ++vcpu->arch.smi_count; |
ee2cd4b7 | 6805 | enter_smm(vcpu); |
c43203ca | 6806 | } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) { |
321c5658 YS |
6807 | --vcpu->arch.nmi_pending; |
6808 | vcpu->arch.nmi_injected = true; | |
6809 | kvm_x86_ops->set_nmi(vcpu); | |
c7c9c56c | 6810 | } else if (kvm_cpu_has_injectable_intr(vcpu)) { |
9242b5b6 BD |
6811 | /* |
6812 | * Because interrupts can be injected asynchronously, we are | |
6813 | * calling check_nested_events again here to avoid a race condition. | |
6814 | * See https://lkml.org/lkml/2014/7/2/60 for discussion about this | |
6815 | * proposal and current concerns. Perhaps we should be setting | |
6816 | * KVM_REQ_EVENT only on certain events and not unconditionally? | |
6817 | */ | |
6818 | if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { | |
6819 | r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); | |
6820 | if (r != 0) | |
6821 | return r; | |
6822 | } | |
95ba8273 | 6823 | if (kvm_x86_ops->interrupt_allowed(vcpu)) { |
66fd3f7f GN |
6824 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), |
6825 | false); | |
6826 | kvm_x86_ops->set_irq(vcpu); | |
95ba8273 GN |
6827 | } |
6828 | } | |
ee2cd4b7 | 6829 | |
b6b8a145 | 6830 | return 0; |
95ba8273 GN |
6831 | } |
6832 | ||
7460fb4a AK |
6833 | static void process_nmi(struct kvm_vcpu *vcpu) |
6834 | { | |
6835 | unsigned limit = 2; | |
6836 | ||
6837 | /* | |
6838 | * x86 is limited to one NMI running, and one NMI pending after it. | |
6839 | * If an NMI is already in progress, limit further NMIs to just one. | |
6840 | * Otherwise, allow two (and we'll inject the first one immediately). | |
6841 | */ | |
6842 | if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) | |
6843 | limit = 1; | |
6844 | ||
6845 | vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); | |
6846 | vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); | |
6847 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
6848 | } | |
6849 | ||
ee2cd4b7 | 6850 | static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) |
660a5d51 PB |
6851 | { |
6852 | u32 flags = 0; | |
6853 | flags |= seg->g << 23; | |
6854 | flags |= seg->db << 22; | |
6855 | flags |= seg->l << 21; | |
6856 | flags |= seg->avl << 20; | |
6857 | flags |= seg->present << 15; | |
6858 | flags |= seg->dpl << 13; | |
6859 | flags |= seg->s << 12; | |
6860 | flags |= seg->type << 8; | |
6861 | return flags; | |
6862 | } | |
6863 | ||
ee2cd4b7 | 6864 | static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) |
660a5d51 PB |
6865 | { |
6866 | struct kvm_segment seg; | |
6867 | int offset; | |
6868 | ||
6869 | kvm_get_segment(vcpu, &seg, n); | |
6870 | put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); | |
6871 | ||
6872 | if (n < 3) | |
6873 | offset = 0x7f84 + n * 12; | |
6874 | else | |
6875 | offset = 0x7f2c + (n - 3) * 12; | |
6876 | ||
6877 | put_smstate(u32, buf, offset + 8, seg.base); | |
6878 | put_smstate(u32, buf, offset + 4, seg.limit); | |
ee2cd4b7 | 6879 | put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
6880 | } |
6881 | ||
efbb288a | 6882 | #ifdef CONFIG_X86_64 |
ee2cd4b7 | 6883 | static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) |
660a5d51 PB |
6884 | { |
6885 | struct kvm_segment seg; | |
6886 | int offset; | |
6887 | u16 flags; | |
6888 | ||
6889 | kvm_get_segment(vcpu, &seg, n); | |
6890 | offset = 0x7e00 + n * 16; | |
6891 | ||
ee2cd4b7 | 6892 | flags = enter_smm_get_segment_flags(&seg) >> 8; |
660a5d51 PB |
6893 | put_smstate(u16, buf, offset, seg.selector); |
6894 | put_smstate(u16, buf, offset + 2, flags); | |
6895 | put_smstate(u32, buf, offset + 4, seg.limit); | |
6896 | put_smstate(u64, buf, offset + 8, seg.base); | |
6897 | } | |
efbb288a | 6898 | #endif |
660a5d51 | 6899 | |
ee2cd4b7 | 6900 | static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) |
660a5d51 PB |
6901 | { |
6902 | struct desc_ptr dt; | |
6903 | struct kvm_segment seg; | |
6904 | unsigned long val; | |
6905 | int i; | |
6906 | ||
6907 | put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); | |
6908 | put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); | |
6909 | put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); | |
6910 | put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); | |
6911 | ||
6912 | for (i = 0; i < 8; i++) | |
6913 | put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); | |
6914 | ||
6915 | kvm_get_dr(vcpu, 6, &val); | |
6916 | put_smstate(u32, buf, 0x7fcc, (u32)val); | |
6917 | kvm_get_dr(vcpu, 7, &val); | |
6918 | put_smstate(u32, buf, 0x7fc8, (u32)val); | |
6919 | ||
6920 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
6921 | put_smstate(u32, buf, 0x7fc4, seg.selector); | |
6922 | put_smstate(u32, buf, 0x7f64, seg.base); | |
6923 | put_smstate(u32, buf, 0x7f60, seg.limit); | |
ee2cd4b7 | 6924 | put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
6925 | |
6926 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
6927 | put_smstate(u32, buf, 0x7fc0, seg.selector); | |
6928 | put_smstate(u32, buf, 0x7f80, seg.base); | |
6929 | put_smstate(u32, buf, 0x7f7c, seg.limit); | |
ee2cd4b7 | 6930 | put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
6931 | |
6932 | kvm_x86_ops->get_gdt(vcpu, &dt); | |
6933 | put_smstate(u32, buf, 0x7f74, dt.address); | |
6934 | put_smstate(u32, buf, 0x7f70, dt.size); | |
6935 | ||
6936 | kvm_x86_ops->get_idt(vcpu, &dt); | |
6937 | put_smstate(u32, buf, 0x7f58, dt.address); | |
6938 | put_smstate(u32, buf, 0x7f54, dt.size); | |
6939 | ||
6940 | for (i = 0; i < 6; i++) | |
ee2cd4b7 | 6941 | enter_smm_save_seg_32(vcpu, buf, i); |
660a5d51 PB |
6942 | |
6943 | put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); | |
6944 | ||
6945 | /* revision id */ | |
6946 | put_smstate(u32, buf, 0x7efc, 0x00020000); | |
6947 | put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); | |
6948 | } | |
6949 | ||
ee2cd4b7 | 6950 | static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) |
660a5d51 PB |
6951 | { |
6952 | #ifdef CONFIG_X86_64 | |
6953 | struct desc_ptr dt; | |
6954 | struct kvm_segment seg; | |
6955 | unsigned long val; | |
6956 | int i; | |
6957 | ||
6958 | for (i = 0; i < 16; i++) | |
6959 | put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); | |
6960 | ||
6961 | put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); | |
6962 | put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); | |
6963 | ||
6964 | kvm_get_dr(vcpu, 6, &val); | |
6965 | put_smstate(u64, buf, 0x7f68, val); | |
6966 | kvm_get_dr(vcpu, 7, &val); | |
6967 | put_smstate(u64, buf, 0x7f60, val); | |
6968 | ||
6969 | put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); | |
6970 | put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); | |
6971 | put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); | |
6972 | ||
6973 | put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); | |
6974 | ||
6975 | /* revision id */ | |
6976 | put_smstate(u32, buf, 0x7efc, 0x00020064); | |
6977 | ||
6978 | put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); | |
6979 | ||
6980 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
6981 | put_smstate(u16, buf, 0x7e90, seg.selector); | |
ee2cd4b7 | 6982 | put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); |
660a5d51 PB |
6983 | put_smstate(u32, buf, 0x7e94, seg.limit); |
6984 | put_smstate(u64, buf, 0x7e98, seg.base); | |
6985 | ||
6986 | kvm_x86_ops->get_idt(vcpu, &dt); | |
6987 | put_smstate(u32, buf, 0x7e84, dt.size); | |
6988 | put_smstate(u64, buf, 0x7e88, dt.address); | |
6989 | ||
6990 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
6991 | put_smstate(u16, buf, 0x7e70, seg.selector); | |
ee2cd4b7 | 6992 | put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); |
660a5d51 PB |
6993 | put_smstate(u32, buf, 0x7e74, seg.limit); |
6994 | put_smstate(u64, buf, 0x7e78, seg.base); | |
6995 | ||
6996 | kvm_x86_ops->get_gdt(vcpu, &dt); | |
6997 | put_smstate(u32, buf, 0x7e64, dt.size); | |
6998 | put_smstate(u64, buf, 0x7e68, dt.address); | |
6999 | ||
7000 | for (i = 0; i < 6; i++) | |
ee2cd4b7 | 7001 | enter_smm_save_seg_64(vcpu, buf, i); |
660a5d51 PB |
7002 | #else |
7003 | WARN_ON_ONCE(1); | |
7004 | #endif | |
7005 | } | |
7006 | ||
ee2cd4b7 | 7007 | static void enter_smm(struct kvm_vcpu *vcpu) |
64d60670 | 7008 | { |
660a5d51 | 7009 | struct kvm_segment cs, ds; |
18c3626e | 7010 | struct desc_ptr dt; |
660a5d51 PB |
7011 | char buf[512]; |
7012 | u32 cr0; | |
7013 | ||
660a5d51 | 7014 | trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); |
660a5d51 | 7015 | memset(buf, 0, 512); |
d6321d49 | 7016 | if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) |
ee2cd4b7 | 7017 | enter_smm_save_state_64(vcpu, buf); |
660a5d51 | 7018 | else |
ee2cd4b7 | 7019 | enter_smm_save_state_32(vcpu, buf); |
660a5d51 | 7020 | |
0234bf88 LP |
7021 | /* |
7022 | * Give pre_enter_smm() a chance to make ISA-specific changes to the | |
7023 | * vCPU state (e.g. leave guest mode) after we've saved the state into | |
7024 | * the SMM state-save area. | |
7025 | */ | |
7026 | kvm_x86_ops->pre_enter_smm(vcpu, buf); | |
7027 | ||
7028 | vcpu->arch.hflags |= HF_SMM_MASK; | |
54bf36aa | 7029 | kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); |
660a5d51 PB |
7030 | |
7031 | if (kvm_x86_ops->get_nmi_mask(vcpu)) | |
7032 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; | |
7033 | else | |
7034 | kvm_x86_ops->set_nmi_mask(vcpu, true); | |
7035 | ||
7036 | kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); | |
7037 | kvm_rip_write(vcpu, 0x8000); | |
7038 | ||
7039 | cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); | |
7040 | kvm_x86_ops->set_cr0(vcpu, cr0); | |
7041 | vcpu->arch.cr0 = cr0; | |
7042 | ||
7043 | kvm_x86_ops->set_cr4(vcpu, 0); | |
7044 | ||
18c3626e PB |
7045 | /* Undocumented: IDT limit is set to zero on entry to SMM. */ |
7046 | dt.address = dt.size = 0; | |
7047 | kvm_x86_ops->set_idt(vcpu, &dt); | |
7048 | ||
660a5d51 PB |
7049 | __kvm_set_dr(vcpu, 7, DR7_FIXED_1); |
7050 | ||
7051 | cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; | |
7052 | cs.base = vcpu->arch.smbase; | |
7053 | ||
7054 | ds.selector = 0; | |
7055 | ds.base = 0; | |
7056 | ||
7057 | cs.limit = ds.limit = 0xffffffff; | |
7058 | cs.type = ds.type = 0x3; | |
7059 | cs.dpl = ds.dpl = 0; | |
7060 | cs.db = ds.db = 0; | |
7061 | cs.s = ds.s = 1; | |
7062 | cs.l = ds.l = 0; | |
7063 | cs.g = ds.g = 1; | |
7064 | cs.avl = ds.avl = 0; | |
7065 | cs.present = ds.present = 1; | |
7066 | cs.unusable = ds.unusable = 0; | |
7067 | cs.padding = ds.padding = 0; | |
7068 | ||
7069 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
7070 | kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); | |
7071 | kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); | |
7072 | kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); | |
7073 | kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); | |
7074 | kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); | |
7075 | ||
d6321d49 | 7076 | if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) |
660a5d51 PB |
7077 | kvm_x86_ops->set_efer(vcpu, 0); |
7078 | ||
7079 | kvm_update_cpuid(vcpu); | |
7080 | kvm_mmu_reset_context(vcpu); | |
64d60670 PB |
7081 | } |
7082 | ||
ee2cd4b7 | 7083 | static void process_smi(struct kvm_vcpu *vcpu) |
c43203ca PB |
7084 | { |
7085 | vcpu->arch.smi_pending = true; | |
7086 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7087 | } | |
7088 | ||
2860c4b1 PB |
7089 | void kvm_make_scan_ioapic_request(struct kvm *kvm) |
7090 | { | |
7091 | kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); | |
7092 | } | |
7093 | ||
3d81bc7e | 7094 | static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) |
c7c9c56c | 7095 | { |
3d81bc7e YZ |
7096 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) |
7097 | return; | |
c7c9c56c | 7098 | |
6308630b | 7099 | bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); |
c7c9c56c | 7100 | |
b053b2ae | 7101 | if (irqchip_split(vcpu->kvm)) |
6308630b | 7102 | kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); |
db2bdcbb | 7103 | else { |
fa59cc00 | 7104 | if (vcpu->arch.apicv_active) |
d62caabb | 7105 | kvm_x86_ops->sync_pir_to_irr(vcpu); |
6308630b | 7106 | kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); |
db2bdcbb | 7107 | } |
e40ff1d6 LA |
7108 | |
7109 | if (is_guest_mode(vcpu)) | |
7110 | vcpu->arch.load_eoi_exitmap_pending = true; | |
7111 | else | |
7112 | kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); | |
7113 | } | |
7114 | ||
7115 | static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) | |
7116 | { | |
7117 | u64 eoi_exit_bitmap[4]; | |
7118 | ||
7119 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) | |
7120 | return; | |
7121 | ||
5c919412 AS |
7122 | bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors, |
7123 | vcpu_to_synic(vcpu)->vec_bitmap, 256); | |
7124 | kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); | |
c7c9c56c YZ |
7125 | } |
7126 | ||
b1394e74 RK |
7127 | void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, |
7128 | unsigned long start, unsigned long end) | |
7129 | { | |
7130 | unsigned long apic_address; | |
7131 | ||
7132 | /* | |
7133 | * The physical address of apic access page is stored in the VMCS. | |
7134 | * Update it when it becomes invalid. | |
7135 | */ | |
7136 | apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); | |
7137 | if (start <= apic_address && apic_address < end) | |
7138 | kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); | |
7139 | } | |
7140 | ||
4256f43f TC |
7141 | void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) |
7142 | { | |
c24ae0dc TC |
7143 | struct page *page = NULL; |
7144 | ||
35754c98 | 7145 | if (!lapic_in_kernel(vcpu)) |
f439ed27 PB |
7146 | return; |
7147 | ||
4256f43f TC |
7148 | if (!kvm_x86_ops->set_apic_access_page_addr) |
7149 | return; | |
7150 | ||
c24ae0dc | 7151 | page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); |
e8fd5e9e AA |
7152 | if (is_error_page(page)) |
7153 | return; | |
c24ae0dc TC |
7154 | kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page)); |
7155 | ||
7156 | /* | |
7157 | * Do not pin apic access page in memory, the MMU notifier | |
7158 | * will call us again if it is migrated or swapped out. | |
7159 | */ | |
7160 | put_page(page); | |
4256f43f TC |
7161 | } |
7162 | EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page); | |
7163 | ||
9357d939 | 7164 | /* |
362c698f | 7165 | * Returns 1 to let vcpu_run() continue the guest execution loop without |
9357d939 TY |
7166 | * exiting to the userspace. Otherwise, the value will be returned to the |
7167 | * userspace. | |
7168 | */ | |
851ba692 | 7169 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
7170 | { |
7171 | int r; | |
62a193ed MG |
7172 | bool req_int_win = |
7173 | dm_request_for_irq_injection(vcpu) && | |
7174 | kvm_cpu_accept_dm_intr(vcpu); | |
7175 | ||
730dca42 | 7176 | bool req_immediate_exit = false; |
b6c7a5dc | 7177 | |
2fa6e1e1 | 7178 | if (kvm_request_pending(vcpu)) { |
a8eeb04a | 7179 | if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) |
2e53d63a | 7180 | kvm_mmu_unload(vcpu); |
a8eeb04a | 7181 | if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) |
2f599714 | 7182 | __kvm_migrate_timers(vcpu); |
d828199e MT |
7183 | if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) |
7184 | kvm_gen_update_masterclock(vcpu->kvm); | |
0061d53d MT |
7185 | if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) |
7186 | kvm_gen_kvmclock_update(vcpu); | |
34c238a1 ZA |
7187 | if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { |
7188 | r = kvm_guest_time_update(vcpu); | |
8cfdc000 ZA |
7189 | if (unlikely(r)) |
7190 | goto out; | |
7191 | } | |
a8eeb04a | 7192 | if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) |
4731d4c7 | 7193 | kvm_mmu_sync_roots(vcpu); |
a8eeb04a | 7194 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) |
c2ba05cc | 7195 | kvm_vcpu_flush_tlb(vcpu, true); |
a8eeb04a | 7196 | if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { |
851ba692 | 7197 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
7198 | r = 0; |
7199 | goto out; | |
7200 | } | |
a8eeb04a | 7201 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
851ba692 | 7202 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
bbeac283 | 7203 | vcpu->mmio_needed = 0; |
71c4dfaf JR |
7204 | r = 0; |
7205 | goto out; | |
7206 | } | |
af585b92 GN |
7207 | if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { |
7208 | /* Page is swapped out. Do synthetic halt */ | |
7209 | vcpu->arch.apf.halted = true; | |
7210 | r = 1; | |
7211 | goto out; | |
7212 | } | |
c9aaa895 GC |
7213 | if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) |
7214 | record_steal_time(vcpu); | |
64d60670 PB |
7215 | if (kvm_check_request(KVM_REQ_SMI, vcpu)) |
7216 | process_smi(vcpu); | |
7460fb4a AK |
7217 | if (kvm_check_request(KVM_REQ_NMI, vcpu)) |
7218 | process_nmi(vcpu); | |
f5132b01 | 7219 | if (kvm_check_request(KVM_REQ_PMU, vcpu)) |
c6702c9d | 7220 | kvm_pmu_handle_event(vcpu); |
f5132b01 | 7221 | if (kvm_check_request(KVM_REQ_PMI, vcpu)) |
c6702c9d | 7222 | kvm_pmu_deliver_pmi(vcpu); |
7543a635 SR |
7223 | if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { |
7224 | BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); | |
7225 | if (test_bit(vcpu->arch.pending_ioapic_eoi, | |
6308630b | 7226 | vcpu->arch.ioapic_handled_vectors)) { |
7543a635 SR |
7227 | vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; |
7228 | vcpu->run->eoi.vector = | |
7229 | vcpu->arch.pending_ioapic_eoi; | |
7230 | r = 0; | |
7231 | goto out; | |
7232 | } | |
7233 | } | |
3d81bc7e YZ |
7234 | if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) |
7235 | vcpu_scan_ioapic(vcpu); | |
e40ff1d6 LA |
7236 | if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) |
7237 | vcpu_load_eoi_exitmap(vcpu); | |
4256f43f TC |
7238 | if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) |
7239 | kvm_vcpu_reload_apic_access_page(vcpu); | |
2ce79189 AS |
7240 | if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { |
7241 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
7242 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; | |
7243 | r = 0; | |
7244 | goto out; | |
7245 | } | |
e516cebb AS |
7246 | if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { |
7247 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
7248 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; | |
7249 | r = 0; | |
7250 | goto out; | |
7251 | } | |
db397571 AS |
7252 | if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { |
7253 | vcpu->run->exit_reason = KVM_EXIT_HYPERV; | |
7254 | vcpu->run->hyperv = vcpu->arch.hyperv.exit; | |
7255 | r = 0; | |
7256 | goto out; | |
7257 | } | |
f3b138c5 AS |
7258 | |
7259 | /* | |
7260 | * KVM_REQ_HV_STIMER has to be processed after | |
7261 | * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers | |
7262 | * depend on the guest clock being up-to-date | |
7263 | */ | |
1f4b34f8 AS |
7264 | if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) |
7265 | kvm_hv_process_stimers(vcpu); | |
2f52d58c | 7266 | } |
b93463aa | 7267 | |
b463a6f7 | 7268 | if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { |
0f1e261e | 7269 | ++vcpu->stat.req_event; |
66450a21 JK |
7270 | kvm_apic_accept_events(vcpu); |
7271 | if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { | |
7272 | r = 1; | |
7273 | goto out; | |
7274 | } | |
7275 | ||
b6b8a145 JK |
7276 | if (inject_pending_event(vcpu, req_int_win) != 0) |
7277 | req_immediate_exit = true; | |
321c5658 | 7278 | else { |
cc3d967f | 7279 | /* Enable SMI/NMI/IRQ window open exits if needed. |
c43203ca | 7280 | * |
cc3d967f LP |
7281 | * SMIs have three cases: |
7282 | * 1) They can be nested, and then there is nothing to | |
7283 | * do here because RSM will cause a vmexit anyway. | |
7284 | * 2) There is an ISA-specific reason why SMI cannot be | |
7285 | * injected, and the moment when this changes can be | |
7286 | * intercepted. | |
7287 | * 3) Or the SMI can be pending because | |
7288 | * inject_pending_event has completed the injection | |
7289 | * of an IRQ or NMI from the previous vmexit, and | |
7290 | * then we request an immediate exit to inject the | |
7291 | * SMI. | |
c43203ca PB |
7292 | */ |
7293 | if (vcpu->arch.smi_pending && !is_smm(vcpu)) | |
cc3d967f LP |
7294 | if (!kvm_x86_ops->enable_smi_window(vcpu)) |
7295 | req_immediate_exit = true; | |
321c5658 YS |
7296 | if (vcpu->arch.nmi_pending) |
7297 | kvm_x86_ops->enable_nmi_window(vcpu); | |
7298 | if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) | |
7299 | kvm_x86_ops->enable_irq_window(vcpu); | |
664f8e26 | 7300 | WARN_ON(vcpu->arch.exception.pending); |
321c5658 | 7301 | } |
b463a6f7 AK |
7302 | |
7303 | if (kvm_lapic_enabled(vcpu)) { | |
7304 | update_cr8_intercept(vcpu); | |
7305 | kvm_lapic_sync_to_vapic(vcpu); | |
7306 | } | |
7307 | } | |
7308 | ||
d8368af8 AK |
7309 | r = kvm_mmu_reload(vcpu); |
7310 | if (unlikely(r)) { | |
d905c069 | 7311 | goto cancel_injection; |
d8368af8 AK |
7312 | } |
7313 | ||
b6c7a5dc HB |
7314 | preempt_disable(); |
7315 | ||
7316 | kvm_x86_ops->prepare_guest_switch(vcpu); | |
b95234c8 PB |
7317 | |
7318 | /* | |
7319 | * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt | |
7320 | * IPI are then delayed after guest entry, which ensures that they | |
7321 | * result in virtual interrupt delivery. | |
7322 | */ | |
7323 | local_irq_disable(); | |
6b7e2d09 XG |
7324 | vcpu->mode = IN_GUEST_MODE; |
7325 | ||
01b71917 MT |
7326 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
7327 | ||
0f127d12 | 7328 | /* |
b95234c8 | 7329 | * 1) We should set ->mode before checking ->requests. Please see |
cde9af6e | 7330 | * the comment in kvm_vcpu_exiting_guest_mode(). |
b95234c8 PB |
7331 | * |
7332 | * 2) For APICv, we should set ->mode before checking PIR.ON. This | |
7333 | * pairs with the memory barrier implicit in pi_test_and_set_on | |
7334 | * (see vmx_deliver_posted_interrupt). | |
7335 | * | |
7336 | * 3) This also orders the write to mode from any reads to the page | |
7337 | * tables done while the VCPU is running. Please see the comment | |
7338 | * in kvm_flush_remote_tlbs. | |
6b7e2d09 | 7339 | */ |
01b71917 | 7340 | smp_mb__after_srcu_read_unlock(); |
b6c7a5dc | 7341 | |
b95234c8 PB |
7342 | /* |
7343 | * This handles the case where a posted interrupt was | |
7344 | * notified with kvm_vcpu_kick. | |
7345 | */ | |
fa59cc00 LA |
7346 | if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active) |
7347 | kvm_x86_ops->sync_pir_to_irr(vcpu); | |
32f88400 | 7348 | |
2fa6e1e1 | 7349 | if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) |
d94e1dc9 | 7350 | || need_resched() || signal_pending(current)) { |
6b7e2d09 | 7351 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 7352 | smp_wmb(); |
6c142801 AK |
7353 | local_irq_enable(); |
7354 | preempt_enable(); | |
01b71917 | 7355 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
6c142801 | 7356 | r = 1; |
d905c069 | 7357 | goto cancel_injection; |
6c142801 AK |
7358 | } |
7359 | ||
fc5b7f3b DM |
7360 | kvm_load_guest_xcr0(vcpu); |
7361 | ||
c43203ca PB |
7362 | if (req_immediate_exit) { |
7363 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
d6185f20 | 7364 | smp_send_reschedule(vcpu->cpu); |
c43203ca | 7365 | } |
d6185f20 | 7366 | |
8b89fe1f | 7367 | trace_kvm_entry(vcpu->vcpu_id); |
9c48d517 WL |
7368 | if (lapic_timer_advance_ns) |
7369 | wait_lapic_expire(vcpu); | |
6edaa530 | 7370 | guest_enter_irqoff(); |
b6c7a5dc | 7371 | |
42dbaa5a | 7372 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
7373 | set_debugreg(0, 7); |
7374 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
7375 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
7376 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
7377 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
c77fb5fe | 7378 | set_debugreg(vcpu->arch.dr6, 6); |
ae561ede | 7379 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; |
42dbaa5a | 7380 | } |
b6c7a5dc | 7381 | |
851ba692 | 7382 | kvm_x86_ops->run(vcpu); |
b6c7a5dc | 7383 | |
c77fb5fe PB |
7384 | /* |
7385 | * Do this here before restoring debug registers on the host. And | |
7386 | * since we do this before handling the vmexit, a DR access vmexit | |
7387 | * can (a) read the correct value of the debug registers, (b) set | |
7388 | * KVM_DEBUGREG_WONT_EXIT again. | |
7389 | */ | |
7390 | if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { | |
c77fb5fe PB |
7391 | WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); |
7392 | kvm_x86_ops->sync_dirty_debug_regs(vcpu); | |
70e4da7a PB |
7393 | kvm_update_dr0123(vcpu); |
7394 | kvm_update_dr6(vcpu); | |
7395 | kvm_update_dr7(vcpu); | |
7396 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; | |
c77fb5fe PB |
7397 | } |
7398 | ||
24f1e32c FW |
7399 | /* |
7400 | * If the guest has used debug registers, at least dr7 | |
7401 | * will be disabled while returning to the host. | |
7402 | * If we don't have active breakpoints in the host, we don't | |
7403 | * care about the messed up debug address registers. But if | |
7404 | * we have some of them active, restore the old state. | |
7405 | */ | |
59d8eb53 | 7406 | if (hw_breakpoint_active()) |
24f1e32c | 7407 | hw_breakpoint_restore(); |
42dbaa5a | 7408 | |
4ba76538 | 7409 | vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); |
1d5f066e | 7410 | |
6b7e2d09 | 7411 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 7412 | smp_wmb(); |
a547c6db | 7413 | |
fc5b7f3b DM |
7414 | kvm_put_guest_xcr0(vcpu); |
7415 | ||
dd60d217 | 7416 | kvm_before_interrupt(vcpu); |
a547c6db | 7417 | kvm_x86_ops->handle_external_intr(vcpu); |
dd60d217 | 7418 | kvm_after_interrupt(vcpu); |
b6c7a5dc HB |
7419 | |
7420 | ++vcpu->stat.exits; | |
7421 | ||
f2485b3e | 7422 | guest_exit_irqoff(); |
b6c7a5dc | 7423 | |
f2485b3e | 7424 | local_irq_enable(); |
b6c7a5dc HB |
7425 | preempt_enable(); |
7426 | ||
f656ce01 | 7427 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
3200f405 | 7428 | |
b6c7a5dc HB |
7429 | /* |
7430 | * Profile KVM exit RIPs: | |
7431 | */ | |
7432 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
7433 | unsigned long rip = kvm_rip_read(vcpu); |
7434 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
7435 | } |
7436 | ||
cc578287 ZA |
7437 | if (unlikely(vcpu->arch.tsc_always_catchup)) |
7438 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
298101da | 7439 | |
5cfb1d5a MT |
7440 | if (vcpu->arch.apic_attention) |
7441 | kvm_lapic_sync_from_vapic(vcpu); | |
b93463aa | 7442 | |
618232e2 | 7443 | vcpu->arch.gpa_available = false; |
851ba692 | 7444 | r = kvm_x86_ops->handle_exit(vcpu); |
d905c069 MT |
7445 | return r; |
7446 | ||
7447 | cancel_injection: | |
7448 | kvm_x86_ops->cancel_injection(vcpu); | |
ae7a2a3f MT |
7449 | if (unlikely(vcpu->arch.apic_attention)) |
7450 | kvm_lapic_sync_from_vapic(vcpu); | |
d7690175 MT |
7451 | out: |
7452 | return r; | |
7453 | } | |
b6c7a5dc | 7454 | |
362c698f PB |
7455 | static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) |
7456 | { | |
bf9f6ac8 FW |
7457 | if (!kvm_arch_vcpu_runnable(vcpu) && |
7458 | (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) { | |
9c8fd1ba PB |
7459 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
7460 | kvm_vcpu_block(vcpu); | |
7461 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); | |
bf9f6ac8 FW |
7462 | |
7463 | if (kvm_x86_ops->post_block) | |
7464 | kvm_x86_ops->post_block(vcpu); | |
7465 | ||
9c8fd1ba PB |
7466 | if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) |
7467 | return 1; | |
7468 | } | |
362c698f PB |
7469 | |
7470 | kvm_apic_accept_events(vcpu); | |
7471 | switch(vcpu->arch.mp_state) { | |
7472 | case KVM_MP_STATE_HALTED: | |
7473 | vcpu->arch.pv.pv_unhalted = false; | |
7474 | vcpu->arch.mp_state = | |
7475 | KVM_MP_STATE_RUNNABLE; | |
7476 | case KVM_MP_STATE_RUNNABLE: | |
7477 | vcpu->arch.apf.halted = false; | |
7478 | break; | |
7479 | case KVM_MP_STATE_INIT_RECEIVED: | |
7480 | break; | |
7481 | default: | |
7482 | return -EINTR; | |
7483 | break; | |
7484 | } | |
7485 | return 1; | |
7486 | } | |
09cec754 | 7487 | |
5d9bc648 PB |
7488 | static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) |
7489 | { | |
0ad3bed6 PB |
7490 | if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) |
7491 | kvm_x86_ops->check_nested_events(vcpu, false); | |
7492 | ||
5d9bc648 PB |
7493 | return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
7494 | !vcpu->arch.apf.halted); | |
7495 | } | |
7496 | ||
362c698f | 7497 | static int vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
7498 | { |
7499 | int r; | |
f656ce01 | 7500 | struct kvm *kvm = vcpu->kvm; |
d7690175 | 7501 | |
f656ce01 | 7502 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 7503 | |
362c698f | 7504 | for (;;) { |
58f800d5 | 7505 | if (kvm_vcpu_running(vcpu)) { |
851ba692 | 7506 | r = vcpu_enter_guest(vcpu); |
bf9f6ac8 | 7507 | } else { |
362c698f | 7508 | r = vcpu_block(kvm, vcpu); |
bf9f6ac8 FW |
7509 | } |
7510 | ||
09cec754 GN |
7511 | if (r <= 0) |
7512 | break; | |
7513 | ||
72875d8a | 7514 | kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu); |
09cec754 GN |
7515 | if (kvm_cpu_has_pending_timer(vcpu)) |
7516 | kvm_inject_pending_timer_irqs(vcpu); | |
7517 | ||
782d422b MG |
7518 | if (dm_request_for_irq_injection(vcpu) && |
7519 | kvm_vcpu_ready_for_interrupt_injection(vcpu)) { | |
4ca7dd8c PB |
7520 | r = 0; |
7521 | vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; | |
09cec754 | 7522 | ++vcpu->stat.request_irq_exits; |
362c698f | 7523 | break; |
09cec754 | 7524 | } |
af585b92 GN |
7525 | |
7526 | kvm_check_async_pf_completion(vcpu); | |
7527 | ||
09cec754 GN |
7528 | if (signal_pending(current)) { |
7529 | r = -EINTR; | |
851ba692 | 7530 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 | 7531 | ++vcpu->stat.signal_exits; |
362c698f | 7532 | break; |
09cec754 GN |
7533 | } |
7534 | if (need_resched()) { | |
f656ce01 | 7535 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
c08ac06a | 7536 | cond_resched(); |
f656ce01 | 7537 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 7538 | } |
b6c7a5dc HB |
7539 | } |
7540 | ||
f656ce01 | 7541 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
b6c7a5dc HB |
7542 | |
7543 | return r; | |
7544 | } | |
7545 | ||
716d51ab GN |
7546 | static inline int complete_emulated_io(struct kvm_vcpu *vcpu) |
7547 | { | |
7548 | int r; | |
7549 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); | |
7550 | r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE); | |
7551 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); | |
7552 | if (r != EMULATE_DONE) | |
7553 | return 0; | |
7554 | return 1; | |
7555 | } | |
7556 | ||
7557 | static int complete_emulated_pio(struct kvm_vcpu *vcpu) | |
7558 | { | |
7559 | BUG_ON(!vcpu->arch.pio.count); | |
7560 | ||
7561 | return complete_emulated_io(vcpu); | |
7562 | } | |
7563 | ||
f78146b0 AK |
7564 | /* |
7565 | * Implements the following, as a state machine: | |
7566 | * | |
7567 | * read: | |
7568 | * for each fragment | |
87da7e66 XG |
7569 | * for each mmio piece in the fragment |
7570 | * write gpa, len | |
7571 | * exit | |
7572 | * copy data | |
f78146b0 AK |
7573 | * execute insn |
7574 | * | |
7575 | * write: | |
7576 | * for each fragment | |
87da7e66 XG |
7577 | * for each mmio piece in the fragment |
7578 | * write gpa, len | |
7579 | * copy data | |
7580 | * exit | |
f78146b0 | 7581 | */ |
716d51ab | 7582 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu) |
5287f194 AK |
7583 | { |
7584 | struct kvm_run *run = vcpu->run; | |
f78146b0 | 7585 | struct kvm_mmio_fragment *frag; |
87da7e66 | 7586 | unsigned len; |
5287f194 | 7587 | |
716d51ab | 7588 | BUG_ON(!vcpu->mmio_needed); |
5287f194 | 7589 | |
716d51ab | 7590 | /* Complete previous fragment */ |
87da7e66 XG |
7591 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; |
7592 | len = min(8u, frag->len); | |
716d51ab | 7593 | if (!vcpu->mmio_is_write) |
87da7e66 XG |
7594 | memcpy(frag->data, run->mmio.data, len); |
7595 | ||
7596 | if (frag->len <= 8) { | |
7597 | /* Switch to the next fragment. */ | |
7598 | frag++; | |
7599 | vcpu->mmio_cur_fragment++; | |
7600 | } else { | |
7601 | /* Go forward to the next mmio piece. */ | |
7602 | frag->data += len; | |
7603 | frag->gpa += len; | |
7604 | frag->len -= len; | |
7605 | } | |
7606 | ||
a08d3b3b | 7607 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { |
716d51ab | 7608 | vcpu->mmio_needed = 0; |
0912c977 PB |
7609 | |
7610 | /* FIXME: return into emulator if single-stepping. */ | |
cef4dea0 | 7611 | if (vcpu->mmio_is_write) |
716d51ab GN |
7612 | return 1; |
7613 | vcpu->mmio_read_completed = 1; | |
7614 | return complete_emulated_io(vcpu); | |
7615 | } | |
87da7e66 | 7616 | |
716d51ab GN |
7617 | run->exit_reason = KVM_EXIT_MMIO; |
7618 | run->mmio.phys_addr = frag->gpa; | |
7619 | if (vcpu->mmio_is_write) | |
87da7e66 XG |
7620 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); |
7621 | run->mmio.len = min(8u, frag->len); | |
716d51ab GN |
7622 | run->mmio.is_write = vcpu->mmio_is_write; |
7623 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; | |
7624 | return 0; | |
5287f194 AK |
7625 | } |
7626 | ||
b6c7a5dc HB |
7627 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
7628 | { | |
7629 | int r; | |
b6c7a5dc | 7630 | |
accb757d | 7631 | vcpu_load(vcpu); |
20b7035c | 7632 | kvm_sigset_activate(vcpu); |
5663d8f9 PX |
7633 | kvm_load_guest_fpu(vcpu); |
7634 | ||
a4535290 | 7635 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
2f173d26 JS |
7636 | if (kvm_run->immediate_exit) { |
7637 | r = -EINTR; | |
7638 | goto out; | |
7639 | } | |
b6c7a5dc | 7640 | kvm_vcpu_block(vcpu); |
66450a21 | 7641 | kvm_apic_accept_events(vcpu); |
72875d8a | 7642 | kvm_clear_request(KVM_REQ_UNHALT, vcpu); |
ac9f6dc0 | 7643 | r = -EAGAIN; |
a0595000 JS |
7644 | if (signal_pending(current)) { |
7645 | r = -EINTR; | |
7646 | vcpu->run->exit_reason = KVM_EXIT_INTR; | |
7647 | ++vcpu->stat.signal_exits; | |
7648 | } | |
ac9f6dc0 | 7649 | goto out; |
b6c7a5dc HB |
7650 | } |
7651 | ||
01643c51 KH |
7652 | if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) { |
7653 | r = -EINVAL; | |
7654 | goto out; | |
7655 | } | |
7656 | ||
7657 | if (vcpu->run->kvm_dirty_regs) { | |
7658 | r = sync_regs(vcpu); | |
7659 | if (r != 0) | |
7660 | goto out; | |
7661 | } | |
7662 | ||
b6c7a5dc | 7663 | /* re-sync apic's tpr */ |
35754c98 | 7664 | if (!lapic_in_kernel(vcpu)) { |
eea1cff9 AP |
7665 | if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { |
7666 | r = -EINVAL; | |
7667 | goto out; | |
7668 | } | |
7669 | } | |
b6c7a5dc | 7670 | |
716d51ab GN |
7671 | if (unlikely(vcpu->arch.complete_userspace_io)) { |
7672 | int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; | |
7673 | vcpu->arch.complete_userspace_io = NULL; | |
7674 | r = cui(vcpu); | |
7675 | if (r <= 0) | |
5663d8f9 | 7676 | goto out; |
716d51ab GN |
7677 | } else |
7678 | WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); | |
5287f194 | 7679 | |
460df4c1 PB |
7680 | if (kvm_run->immediate_exit) |
7681 | r = -EINTR; | |
7682 | else | |
7683 | r = vcpu_run(vcpu); | |
b6c7a5dc HB |
7684 | |
7685 | out: | |
5663d8f9 | 7686 | kvm_put_guest_fpu(vcpu); |
01643c51 KH |
7687 | if (vcpu->run->kvm_valid_regs) |
7688 | store_regs(vcpu); | |
f1d86e46 | 7689 | post_kvm_run_save(vcpu); |
20b7035c | 7690 | kvm_sigset_deactivate(vcpu); |
b6c7a5dc | 7691 | |
accb757d | 7692 | vcpu_put(vcpu); |
b6c7a5dc HB |
7693 | return r; |
7694 | } | |
7695 | ||
01643c51 | 7696 | static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 7697 | { |
7ae441ea GN |
7698 | if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { |
7699 | /* | |
7700 | * We are here if userspace calls get_regs() in the middle of | |
7701 | * instruction emulation. Registers state needs to be copied | |
4a969980 | 7702 | * back from emulation context to vcpu. Userspace shouldn't do |
7ae441ea GN |
7703 | * that usually, but some bad designed PV devices (vmware |
7704 | * backdoor interface) need this to work | |
7705 | */ | |
dd856efa | 7706 | emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); |
7ae441ea GN |
7707 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
7708 | } | |
5fdbf976 MT |
7709 | regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); |
7710 | regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
7711 | regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
7712 | regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
7713 | regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
7714 | regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
7715 | regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
7716 | regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); | |
b6c7a5dc | 7717 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
7718 | regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); |
7719 | regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); | |
7720 | regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); | |
7721 | regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); | |
7722 | regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); | |
7723 | regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); | |
7724 | regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); | |
7725 | regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); | |
b6c7a5dc HB |
7726 | #endif |
7727 | ||
5fdbf976 | 7728 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 7729 | regs->rflags = kvm_get_rflags(vcpu); |
01643c51 | 7730 | } |
b6c7a5dc | 7731 | |
01643c51 KH |
7732 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
7733 | { | |
7734 | vcpu_load(vcpu); | |
7735 | __get_regs(vcpu, regs); | |
1fc9b76b | 7736 | vcpu_put(vcpu); |
b6c7a5dc HB |
7737 | return 0; |
7738 | } | |
7739 | ||
01643c51 | 7740 | static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 7741 | { |
7ae441ea GN |
7742 | vcpu->arch.emulate_regs_need_sync_from_vcpu = true; |
7743 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; | |
7744 | ||
5fdbf976 MT |
7745 | kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); |
7746 | kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); | |
7747 | kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); | |
7748 | kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); | |
7749 | kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); | |
7750 | kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); | |
7751 | kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); | |
7752 | kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); | |
b6c7a5dc | 7753 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
7754 | kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); |
7755 | kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); | |
7756 | kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); | |
7757 | kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); | |
7758 | kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); | |
7759 | kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); | |
7760 | kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); | |
7761 | kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); | |
b6c7a5dc HB |
7762 | #endif |
7763 | ||
5fdbf976 | 7764 | kvm_rip_write(vcpu, regs->rip); |
d73235d1 | 7765 | kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); |
b6c7a5dc | 7766 | |
b4f14abd JK |
7767 | vcpu->arch.exception.pending = false; |
7768 | ||
3842d135 | 7769 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
01643c51 | 7770 | } |
3842d135 | 7771 | |
01643c51 KH |
7772 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
7773 | { | |
7774 | vcpu_load(vcpu); | |
7775 | __set_regs(vcpu, regs); | |
875656fe | 7776 | vcpu_put(vcpu); |
b6c7a5dc HB |
7777 | return 0; |
7778 | } | |
7779 | ||
b6c7a5dc HB |
7780 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
7781 | { | |
7782 | struct kvm_segment cs; | |
7783 | ||
3e6e0aab | 7784 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
7785 | *db = cs.db; |
7786 | *l = cs.l; | |
7787 | } | |
7788 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
7789 | ||
01643c51 | 7790 | static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
b6c7a5dc | 7791 | { |
89a27f4d | 7792 | struct desc_ptr dt; |
b6c7a5dc | 7793 | |
3e6e0aab GT |
7794 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
7795 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
7796 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
7797 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
7798 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
7799 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 7800 | |
3e6e0aab GT |
7801 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
7802 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc HB |
7803 | |
7804 | kvm_x86_ops->get_idt(vcpu, &dt); | |
89a27f4d GN |
7805 | sregs->idt.limit = dt.size; |
7806 | sregs->idt.base = dt.address; | |
b6c7a5dc | 7807 | kvm_x86_ops->get_gdt(vcpu, &dt); |
89a27f4d GN |
7808 | sregs->gdt.limit = dt.size; |
7809 | sregs->gdt.base = dt.address; | |
b6c7a5dc | 7810 | |
4d4ec087 | 7811 | sregs->cr0 = kvm_read_cr0(vcpu); |
ad312c7c | 7812 | sregs->cr2 = vcpu->arch.cr2; |
9f8fe504 | 7813 | sregs->cr3 = kvm_read_cr3(vcpu); |
fc78f519 | 7814 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 7815 | sregs->cr8 = kvm_get_cr8(vcpu); |
f6801dff | 7816 | sregs->efer = vcpu->arch.efer; |
b6c7a5dc HB |
7817 | sregs->apic_base = kvm_get_apic_base(vcpu); |
7818 | ||
923c61bb | 7819 | memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); |
b6c7a5dc | 7820 | |
36752c9b | 7821 | if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
7822 | set_bit(vcpu->arch.interrupt.nr, |
7823 | (unsigned long *)sregs->interrupt_bitmap); | |
01643c51 | 7824 | } |
16d7a191 | 7825 | |
01643c51 KH |
7826 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, |
7827 | struct kvm_sregs *sregs) | |
7828 | { | |
7829 | vcpu_load(vcpu); | |
7830 | __get_sregs(vcpu, sregs); | |
bcdec41c | 7831 | vcpu_put(vcpu); |
b6c7a5dc HB |
7832 | return 0; |
7833 | } | |
7834 | ||
62d9f0db MT |
7835 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
7836 | struct kvm_mp_state *mp_state) | |
7837 | { | |
fd232561 CD |
7838 | vcpu_load(vcpu); |
7839 | ||
66450a21 | 7840 | kvm_apic_accept_events(vcpu); |
6aef266c SV |
7841 | if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && |
7842 | vcpu->arch.pv.pv_unhalted) | |
7843 | mp_state->mp_state = KVM_MP_STATE_RUNNABLE; | |
7844 | else | |
7845 | mp_state->mp_state = vcpu->arch.mp_state; | |
7846 | ||
fd232561 | 7847 | vcpu_put(vcpu); |
62d9f0db MT |
7848 | return 0; |
7849 | } | |
7850 | ||
7851 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
7852 | struct kvm_mp_state *mp_state) | |
7853 | { | |
e83dff5e CD |
7854 | int ret = -EINVAL; |
7855 | ||
7856 | vcpu_load(vcpu); | |
7857 | ||
bce87cce | 7858 | if (!lapic_in_kernel(vcpu) && |
66450a21 | 7859 | mp_state->mp_state != KVM_MP_STATE_RUNNABLE) |
e83dff5e | 7860 | goto out; |
66450a21 | 7861 | |
28bf2888 DH |
7862 | /* INITs are latched while in SMM */ |
7863 | if ((is_smm(vcpu) || vcpu->arch.smi_pending) && | |
7864 | (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || | |
7865 | mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) | |
e83dff5e | 7866 | goto out; |
28bf2888 | 7867 | |
66450a21 JK |
7868 | if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { |
7869 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
7870 | set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); | |
7871 | } else | |
7872 | vcpu->arch.mp_state = mp_state->mp_state; | |
3842d135 | 7873 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
e83dff5e CD |
7874 | |
7875 | ret = 0; | |
7876 | out: | |
7877 | vcpu_put(vcpu); | |
7878 | return ret; | |
62d9f0db MT |
7879 | } |
7880 | ||
7f3d35fd KW |
7881 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
7882 | int reason, bool has_error_code, u32 error_code) | |
b6c7a5dc | 7883 | { |
9d74191a | 7884 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
8ec4722d | 7885 | int ret; |
e01c2426 | 7886 | |
8ec4722d | 7887 | init_emulate_ctxt(vcpu); |
c697518a | 7888 | |
7f3d35fd | 7889 | ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, |
9d74191a | 7890 | has_error_code, error_code); |
c697518a | 7891 | |
c697518a | 7892 | if (ret) |
19d04437 | 7893 | return EMULATE_FAIL; |
37817f29 | 7894 | |
9d74191a TY |
7895 | kvm_rip_write(vcpu, ctxt->eip); |
7896 | kvm_set_rflags(vcpu, ctxt->eflags); | |
3842d135 | 7897 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
19d04437 | 7898 | return EMULATE_DONE; |
37817f29 IE |
7899 | } |
7900 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
7901 | ||
f2981033 LT |
7902 | int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
7903 | { | |
37b95951 | 7904 | if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { |
f2981033 LT |
7905 | /* |
7906 | * When EFER.LME and CR0.PG are set, the processor is in | |
7907 | * 64-bit mode (though maybe in a 32-bit code segment). | |
7908 | * CR4.PAE and EFER.LMA must be set. | |
7909 | */ | |
37b95951 | 7910 | if (!(sregs->cr4 & X86_CR4_PAE) |
f2981033 LT |
7911 | || !(sregs->efer & EFER_LMA)) |
7912 | return -EINVAL; | |
7913 | } else { | |
7914 | /* | |
7915 | * Not in 64-bit mode: EFER.LMA is clear and the code | |
7916 | * segment cannot be 64-bit. | |
7917 | */ | |
7918 | if (sregs->efer & EFER_LMA || sregs->cs.l) | |
7919 | return -EINVAL; | |
7920 | } | |
7921 | ||
7922 | return 0; | |
7923 | } | |
7924 | ||
01643c51 | 7925 | static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
b6c7a5dc | 7926 | { |
58cb628d | 7927 | struct msr_data apic_base_msr; |
b6c7a5dc | 7928 | int mmu_reset_needed = 0; |
63f42e02 | 7929 | int pending_vec, max_bits, idx; |
89a27f4d | 7930 | struct desc_ptr dt; |
b4ef9d4e CD |
7931 | int ret = -EINVAL; |
7932 | ||
d6321d49 RK |
7933 | if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && |
7934 | (sregs->cr4 & X86_CR4_OSXSAVE)) | |
b4ef9d4e | 7935 | goto out; |
6d1068b3 | 7936 | |
f2981033 | 7937 | if (kvm_valid_sregs(vcpu, sregs)) |
8dbfb2bf | 7938 | goto out; |
f2981033 | 7939 | |
d3802286 JM |
7940 | apic_base_msr.data = sregs->apic_base; |
7941 | apic_base_msr.host_initiated = true; | |
7942 | if (kvm_set_apic_base(vcpu, &apic_base_msr)) | |
b4ef9d4e | 7943 | goto out; |
6d1068b3 | 7944 | |
89a27f4d GN |
7945 | dt.size = sregs->idt.limit; |
7946 | dt.address = sregs->idt.base; | |
b6c7a5dc | 7947 | kvm_x86_ops->set_idt(vcpu, &dt); |
89a27f4d GN |
7948 | dt.size = sregs->gdt.limit; |
7949 | dt.address = sregs->gdt.base; | |
b6c7a5dc HB |
7950 | kvm_x86_ops->set_gdt(vcpu, &dt); |
7951 | ||
ad312c7c | 7952 | vcpu->arch.cr2 = sregs->cr2; |
9f8fe504 | 7953 | mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; |
dc7e795e | 7954 | vcpu->arch.cr3 = sregs->cr3; |
aff48baa | 7955 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); |
b6c7a5dc | 7956 | |
2d3ad1f4 | 7957 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 7958 | |
f6801dff | 7959 | mmu_reset_needed |= vcpu->arch.efer != sregs->efer; |
b6c7a5dc | 7960 | kvm_x86_ops->set_efer(vcpu, sregs->efer); |
b6c7a5dc | 7961 | |
4d4ec087 | 7962 | mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
b6c7a5dc | 7963 | kvm_x86_ops->set_cr0(vcpu, sregs->cr0); |
d7306163 | 7964 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 7965 | |
fc78f519 | 7966 | mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
b6c7a5dc | 7967 | kvm_x86_ops->set_cr4(vcpu, sregs->cr4); |
b9baba86 | 7968 | if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE)) |
00b27a3e | 7969 | kvm_update_cpuid(vcpu); |
63f42e02 XG |
7970 | |
7971 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
7c93be44 | 7972 | if (!is_long_mode(vcpu) && is_pae(vcpu)) { |
9f8fe504 | 7973 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
7c93be44 MT |
7974 | mmu_reset_needed = 1; |
7975 | } | |
63f42e02 | 7976 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b6c7a5dc HB |
7977 | |
7978 | if (mmu_reset_needed) | |
7979 | kvm_mmu_reset_context(vcpu); | |
7980 | ||
a50abc3b | 7981 | max_bits = KVM_NR_INTERRUPTS; |
923c61bb GN |
7982 | pending_vec = find_first_bit( |
7983 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
7984 | if (pending_vec < max_bits) { | |
66fd3f7f | 7985 | kvm_queue_interrupt(vcpu, pending_vec, false); |
923c61bb | 7986 | pr_debug("Set back pending irq %d\n", pending_vec); |
b6c7a5dc HB |
7987 | } |
7988 | ||
3e6e0aab GT |
7989 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
7990 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
7991 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
7992 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
7993 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
7994 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 7995 | |
3e6e0aab GT |
7996 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
7997 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 7998 | |
5f0269f5 ME |
7999 | update_cr8_intercept(vcpu); |
8000 | ||
9c3e4aab | 8001 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 8002 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 8003 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
3eeb3288 | 8004 | !is_protmode(vcpu)) |
9c3e4aab MT |
8005 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
8006 | ||
3842d135 AK |
8007 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
8008 | ||
b4ef9d4e CD |
8009 | ret = 0; |
8010 | out: | |
01643c51 KH |
8011 | return ret; |
8012 | } | |
8013 | ||
8014 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, | |
8015 | struct kvm_sregs *sregs) | |
8016 | { | |
8017 | int ret; | |
8018 | ||
8019 | vcpu_load(vcpu); | |
8020 | ret = __set_sregs(vcpu, sregs); | |
b4ef9d4e CD |
8021 | vcpu_put(vcpu); |
8022 | return ret; | |
b6c7a5dc HB |
8023 | } |
8024 | ||
d0bfb940 JK |
8025 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
8026 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 8027 | { |
355be0b9 | 8028 | unsigned long rflags; |
ae675ef0 | 8029 | int i, r; |
b6c7a5dc | 8030 | |
66b56562 CD |
8031 | vcpu_load(vcpu); |
8032 | ||
4f926bf2 JK |
8033 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
8034 | r = -EBUSY; | |
8035 | if (vcpu->arch.exception.pending) | |
2122ff5e | 8036 | goto out; |
4f926bf2 JK |
8037 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
8038 | kvm_queue_exception(vcpu, DB_VECTOR); | |
8039 | else | |
8040 | kvm_queue_exception(vcpu, BP_VECTOR); | |
8041 | } | |
8042 | ||
91586a3b JK |
8043 | /* |
8044 | * Read rflags as long as potentially injected trace flags are still | |
8045 | * filtered out. | |
8046 | */ | |
8047 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
8048 | |
8049 | vcpu->guest_debug = dbg->control; | |
8050 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
8051 | vcpu->guest_debug = 0; | |
8052 | ||
8053 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
8054 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
8055 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
c8639010 | 8056 | vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; |
ae675ef0 JK |
8057 | } else { |
8058 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
8059 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
ae675ef0 | 8060 | } |
c8639010 | 8061 | kvm_update_dr7(vcpu); |
ae675ef0 | 8062 | |
f92653ee JK |
8063 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
8064 | vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + | |
8065 | get_segment_base(vcpu, VCPU_SREG_CS); | |
94fe45da | 8066 | |
91586a3b JK |
8067 | /* |
8068 | * Trigger an rflags update that will inject or remove the trace | |
8069 | * flags. | |
8070 | */ | |
8071 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 8072 | |
a96036b8 | 8073 | kvm_x86_ops->update_bp_intercept(vcpu); |
b6c7a5dc | 8074 | |
4f926bf2 | 8075 | r = 0; |
d0bfb940 | 8076 | |
2122ff5e | 8077 | out: |
66b56562 | 8078 | vcpu_put(vcpu); |
b6c7a5dc HB |
8079 | return r; |
8080 | } | |
8081 | ||
8b006791 ZX |
8082 | /* |
8083 | * Translate a guest virtual address to a guest physical address. | |
8084 | */ | |
8085 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
8086 | struct kvm_translation *tr) | |
8087 | { | |
8088 | unsigned long vaddr = tr->linear_address; | |
8089 | gpa_t gpa; | |
f656ce01 | 8090 | int idx; |
8b006791 | 8091 | |
1da5b61d CD |
8092 | vcpu_load(vcpu); |
8093 | ||
f656ce01 | 8094 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1871c602 | 8095 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); |
f656ce01 | 8096 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 ZX |
8097 | tr->physical_address = gpa; |
8098 | tr->valid = gpa != UNMAPPED_GVA; | |
8099 | tr->writeable = 1; | |
8100 | tr->usermode = 0; | |
8b006791 | 8101 | |
1da5b61d | 8102 | vcpu_put(vcpu); |
8b006791 ZX |
8103 | return 0; |
8104 | } | |
8105 | ||
d0752060 HB |
8106 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
8107 | { | |
1393123e | 8108 | struct fxregs_state *fxsave; |
d0752060 | 8109 | |
1393123e | 8110 | vcpu_load(vcpu); |
d0752060 | 8111 | |
1393123e | 8112 | fxsave = &vcpu->arch.guest_fpu.state.fxsave; |
d0752060 HB |
8113 | memcpy(fpu->fpr, fxsave->st_space, 128); |
8114 | fpu->fcw = fxsave->cwd; | |
8115 | fpu->fsw = fxsave->swd; | |
8116 | fpu->ftwx = fxsave->twd; | |
8117 | fpu->last_opcode = fxsave->fop; | |
8118 | fpu->last_ip = fxsave->rip; | |
8119 | fpu->last_dp = fxsave->rdp; | |
8120 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); | |
8121 | ||
1393123e | 8122 | vcpu_put(vcpu); |
d0752060 HB |
8123 | return 0; |
8124 | } | |
8125 | ||
8126 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
8127 | { | |
6a96bc7f CD |
8128 | struct fxregs_state *fxsave; |
8129 | ||
8130 | vcpu_load(vcpu); | |
8131 | ||
8132 | fxsave = &vcpu->arch.guest_fpu.state.fxsave; | |
d0752060 | 8133 | |
d0752060 HB |
8134 | memcpy(fxsave->st_space, fpu->fpr, 128); |
8135 | fxsave->cwd = fpu->fcw; | |
8136 | fxsave->swd = fpu->fsw; | |
8137 | fxsave->twd = fpu->ftwx; | |
8138 | fxsave->fop = fpu->last_opcode; | |
8139 | fxsave->rip = fpu->last_ip; | |
8140 | fxsave->rdp = fpu->last_dp; | |
8141 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); | |
8142 | ||
6a96bc7f | 8143 | vcpu_put(vcpu); |
d0752060 HB |
8144 | return 0; |
8145 | } | |
8146 | ||
01643c51 KH |
8147 | static void store_regs(struct kvm_vcpu *vcpu) |
8148 | { | |
8149 | BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); | |
8150 | ||
8151 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) | |
8152 | __get_regs(vcpu, &vcpu->run->s.regs.regs); | |
8153 | ||
8154 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) | |
8155 | __get_sregs(vcpu, &vcpu->run->s.regs.sregs); | |
8156 | ||
8157 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) | |
8158 | kvm_vcpu_ioctl_x86_get_vcpu_events( | |
8159 | vcpu, &vcpu->run->s.regs.events); | |
8160 | } | |
8161 | ||
8162 | static int sync_regs(struct kvm_vcpu *vcpu) | |
8163 | { | |
8164 | if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS) | |
8165 | return -EINVAL; | |
8166 | ||
8167 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { | |
8168 | __set_regs(vcpu, &vcpu->run->s.regs.regs); | |
8169 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; | |
8170 | } | |
8171 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { | |
8172 | if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) | |
8173 | return -EINVAL; | |
8174 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; | |
8175 | } | |
8176 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { | |
8177 | if (kvm_vcpu_ioctl_x86_set_vcpu_events( | |
8178 | vcpu, &vcpu->run->s.regs.events)) | |
8179 | return -EINVAL; | |
8180 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; | |
8181 | } | |
8182 | ||
8183 | return 0; | |
8184 | } | |
8185 | ||
0ee6a517 | 8186 | static void fx_init(struct kvm_vcpu *vcpu) |
d0752060 | 8187 | { |
bf935b0b | 8188 | fpstate_init(&vcpu->arch.guest_fpu.state); |
782511b0 | 8189 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
7366ed77 | 8190 | vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv = |
df1daba7 | 8191 | host_xcr0 | XSTATE_COMPACTION_ENABLED; |
d0752060 | 8192 | |
2acf923e DC |
8193 | /* |
8194 | * Ensure guest xcr0 is valid for loading | |
8195 | */ | |
d91cab78 | 8196 | vcpu->arch.xcr0 = XFEATURE_MASK_FP; |
2acf923e | 8197 | |
ad312c7c | 8198 | vcpu->arch.cr0 |= X86_CR0_ET; |
d0752060 | 8199 | } |
d0752060 | 8200 | |
f775b13e | 8201 | /* Swap (qemu) user FPU context for the guest FPU context. */ |
d0752060 HB |
8202 | void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) |
8203 | { | |
f775b13e RR |
8204 | preempt_disable(); |
8205 | copy_fpregs_to_fpstate(&vcpu->arch.user_fpu); | |
38cfd5e3 PB |
8206 | /* PKRU is separately restored in kvm_x86_ops->run. */ |
8207 | __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state, | |
8208 | ~XFEATURE_MASK_PKRU); | |
f775b13e | 8209 | preempt_enable(); |
0c04851c | 8210 | trace_kvm_fpu(1); |
d0752060 | 8211 | } |
d0752060 | 8212 | |
f775b13e | 8213 | /* When vcpu_run ends, restore user space FPU context. */ |
d0752060 HB |
8214 | void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) |
8215 | { | |
f775b13e | 8216 | preempt_disable(); |
4f836347 | 8217 | copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu); |
f775b13e RR |
8218 | copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state); |
8219 | preempt_enable(); | |
f096ed85 | 8220 | ++vcpu->stat.fpu_reload; |
0c04851c | 8221 | trace_kvm_fpu(0); |
d0752060 | 8222 | } |
e9b11c17 ZX |
8223 | |
8224 | void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) | |
8225 | { | |
bd768e14 IY |
8226 | void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask; |
8227 | ||
12f9a48f | 8228 | kvmclock_reset(vcpu); |
7f1ea208 | 8229 | |
e9b11c17 | 8230 | kvm_x86_ops->vcpu_free(vcpu); |
bd768e14 | 8231 | free_cpumask_var(wbinvd_dirty_mask); |
e9b11c17 ZX |
8232 | } |
8233 | ||
8234 | struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, | |
8235 | unsigned int id) | |
8236 | { | |
c447e76b LL |
8237 | struct kvm_vcpu *vcpu; |
8238 | ||
b0c39dc6 | 8239 | if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) |
6755bae8 ZA |
8240 | printk_once(KERN_WARNING |
8241 | "kvm: SMP vm created on host with unstable TSC; " | |
8242 | "guest TSC will not be reliable\n"); | |
c447e76b LL |
8243 | |
8244 | vcpu = kvm_x86_ops->vcpu_create(kvm, id); | |
8245 | ||
c447e76b | 8246 | return vcpu; |
26e5215f | 8247 | } |
e9b11c17 | 8248 | |
26e5215f AK |
8249 | int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) |
8250 | { | |
19efffa2 | 8251 | kvm_vcpu_mtrr_init(vcpu); |
ec7660cc | 8252 | vcpu_load(vcpu); |
d28bc9dd | 8253 | kvm_vcpu_reset(vcpu, false); |
8a3c1a33 | 8254 | kvm_mmu_setup(vcpu); |
e9b11c17 | 8255 | vcpu_put(vcpu); |
ec7660cc | 8256 | return 0; |
e9b11c17 ZX |
8257 | } |
8258 | ||
31928aa5 | 8259 | void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) |
42897d86 | 8260 | { |
8fe8ab46 | 8261 | struct msr_data msr; |
332967a3 | 8262 | struct kvm *kvm = vcpu->kvm; |
42897d86 | 8263 | |
d3457c87 RK |
8264 | kvm_hv_vcpu_postcreate(vcpu); |
8265 | ||
ec7660cc | 8266 | if (mutex_lock_killable(&vcpu->mutex)) |
31928aa5 | 8267 | return; |
ec7660cc | 8268 | vcpu_load(vcpu); |
8fe8ab46 WA |
8269 | msr.data = 0x0; |
8270 | msr.index = MSR_IA32_TSC; | |
8271 | msr.host_initiated = true; | |
8272 | kvm_write_tsc(vcpu, &msr); | |
42897d86 | 8273 | vcpu_put(vcpu); |
ec7660cc | 8274 | mutex_unlock(&vcpu->mutex); |
42897d86 | 8275 | |
630994b3 MT |
8276 | if (!kvmclock_periodic_sync) |
8277 | return; | |
8278 | ||
332967a3 AJ |
8279 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, |
8280 | KVMCLOCK_SYNC_PERIOD); | |
42897d86 MT |
8281 | } |
8282 | ||
d40ccc62 | 8283 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 | 8284 | { |
344d9588 GN |
8285 | vcpu->arch.apf.msr_val = 0; |
8286 | ||
ec7660cc | 8287 | vcpu_load(vcpu); |
e9b11c17 ZX |
8288 | kvm_mmu_unload(vcpu); |
8289 | vcpu_put(vcpu); | |
8290 | ||
8291 | kvm_x86_ops->vcpu_free(vcpu); | |
8292 | } | |
8293 | ||
d28bc9dd | 8294 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
e9b11c17 | 8295 | { |
b7e31be3 RK |
8296 | kvm_lapic_reset(vcpu, init_event); |
8297 | ||
e69fab5d PB |
8298 | vcpu->arch.hflags = 0; |
8299 | ||
c43203ca | 8300 | vcpu->arch.smi_pending = 0; |
52797bf9 | 8301 | vcpu->arch.smi_count = 0; |
7460fb4a AK |
8302 | atomic_set(&vcpu->arch.nmi_queued, 0); |
8303 | vcpu->arch.nmi_pending = 0; | |
448fa4a9 | 8304 | vcpu->arch.nmi_injected = false; |
5f7552d4 NA |
8305 | kvm_clear_interrupt_queue(vcpu); |
8306 | kvm_clear_exception_queue(vcpu); | |
664f8e26 | 8307 | vcpu->arch.exception.pending = false; |
448fa4a9 | 8308 | |
42dbaa5a | 8309 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); |
ae561ede | 8310 | kvm_update_dr0123(vcpu); |
6f43ed01 | 8311 | vcpu->arch.dr6 = DR6_INIT; |
73aaf249 | 8312 | kvm_update_dr6(vcpu); |
42dbaa5a | 8313 | vcpu->arch.dr7 = DR7_FIXED_1; |
c8639010 | 8314 | kvm_update_dr7(vcpu); |
42dbaa5a | 8315 | |
1119022c NA |
8316 | vcpu->arch.cr2 = 0; |
8317 | ||
3842d135 | 8318 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
344d9588 | 8319 | vcpu->arch.apf.msr_val = 0; |
c9aaa895 | 8320 | vcpu->arch.st.msr_val = 0; |
3842d135 | 8321 | |
12f9a48f GC |
8322 | kvmclock_reset(vcpu); |
8323 | ||
af585b92 GN |
8324 | kvm_clear_async_pf_completion_queue(vcpu); |
8325 | kvm_async_pf_hash_reset(vcpu); | |
8326 | vcpu->arch.apf.halted = false; | |
3842d135 | 8327 | |
a554d207 WL |
8328 | if (kvm_mpx_supported()) { |
8329 | void *mpx_state_buffer; | |
8330 | ||
8331 | /* | |
8332 | * To avoid have the INIT path from kvm_apic_has_events() that be | |
8333 | * called with loaded FPU and does not let userspace fix the state. | |
8334 | */ | |
f775b13e RR |
8335 | if (init_event) |
8336 | kvm_put_guest_fpu(vcpu); | |
a554d207 WL |
8337 | mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave, |
8338 | XFEATURE_MASK_BNDREGS); | |
8339 | if (mpx_state_buffer) | |
8340 | memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state)); | |
8341 | mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave, | |
8342 | XFEATURE_MASK_BNDCSR); | |
8343 | if (mpx_state_buffer) | |
8344 | memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr)); | |
f775b13e RR |
8345 | if (init_event) |
8346 | kvm_load_guest_fpu(vcpu); | |
a554d207 WL |
8347 | } |
8348 | ||
64d60670 | 8349 | if (!init_event) { |
d28bc9dd | 8350 | kvm_pmu_reset(vcpu); |
64d60670 | 8351 | vcpu->arch.smbase = 0x30000; |
db2336a8 KH |
8352 | |
8353 | vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; | |
8354 | vcpu->arch.msr_misc_features_enables = 0; | |
a554d207 WL |
8355 | |
8356 | vcpu->arch.xcr0 = XFEATURE_MASK_FP; | |
64d60670 | 8357 | } |
f5132b01 | 8358 | |
66f7b72e JS |
8359 | memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); |
8360 | vcpu->arch.regs_avail = ~0; | |
8361 | vcpu->arch.regs_dirty = ~0; | |
8362 | ||
a554d207 WL |
8363 | vcpu->arch.ia32_xss = 0; |
8364 | ||
d28bc9dd | 8365 | kvm_x86_ops->vcpu_reset(vcpu, init_event); |
e9b11c17 ZX |
8366 | } |
8367 | ||
2b4a273b | 8368 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) |
66450a21 JK |
8369 | { |
8370 | struct kvm_segment cs; | |
8371 | ||
8372 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
8373 | cs.selector = vector << 8; | |
8374 | cs.base = vector << 12; | |
8375 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
8376 | kvm_rip_write(vcpu, 0); | |
e9b11c17 ZX |
8377 | } |
8378 | ||
13a34e06 | 8379 | int kvm_arch_hardware_enable(void) |
e9b11c17 | 8380 | { |
ca84d1a2 ZA |
8381 | struct kvm *kvm; |
8382 | struct kvm_vcpu *vcpu; | |
8383 | int i; | |
0dd6a6ed ZA |
8384 | int ret; |
8385 | u64 local_tsc; | |
8386 | u64 max_tsc = 0; | |
8387 | bool stable, backwards_tsc = false; | |
18863bdd AK |
8388 | |
8389 | kvm_shared_msr_cpu_online(); | |
13a34e06 | 8390 | ret = kvm_x86_ops->hardware_enable(); |
0dd6a6ed ZA |
8391 | if (ret != 0) |
8392 | return ret; | |
8393 | ||
4ea1636b | 8394 | local_tsc = rdtsc(); |
b0c39dc6 | 8395 | stable = !kvm_check_tsc_unstable(); |
0dd6a6ed ZA |
8396 | list_for_each_entry(kvm, &vm_list, vm_list) { |
8397 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
8398 | if (!stable && vcpu->cpu == smp_processor_id()) | |
105b21bb | 8399 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
8400 | if (stable && vcpu->arch.last_host_tsc > local_tsc) { |
8401 | backwards_tsc = true; | |
8402 | if (vcpu->arch.last_host_tsc > max_tsc) | |
8403 | max_tsc = vcpu->arch.last_host_tsc; | |
8404 | } | |
8405 | } | |
8406 | } | |
8407 | ||
8408 | /* | |
8409 | * Sometimes, even reliable TSCs go backwards. This happens on | |
8410 | * platforms that reset TSC during suspend or hibernate actions, but | |
8411 | * maintain synchronization. We must compensate. Fortunately, we can | |
8412 | * detect that condition here, which happens early in CPU bringup, | |
8413 | * before any KVM threads can be running. Unfortunately, we can't | |
8414 | * bring the TSCs fully up to date with real time, as we aren't yet far | |
8415 | * enough into CPU bringup that we know how much real time has actually | |
108b249c | 8416 | * elapsed; our helper function, ktime_get_boot_ns() will be using boot |
0dd6a6ed ZA |
8417 | * variables that haven't been updated yet. |
8418 | * | |
8419 | * So we simply find the maximum observed TSC above, then record the | |
8420 | * adjustment to TSC in each VCPU. When the VCPU later gets loaded, | |
8421 | * the adjustment will be applied. Note that we accumulate | |
8422 | * adjustments, in case multiple suspend cycles happen before some VCPU | |
8423 | * gets a chance to run again. In the event that no KVM threads get a | |
8424 | * chance to run, we will miss the entire elapsed period, as we'll have | |
8425 | * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may | |
8426 | * loose cycle time. This isn't too big a deal, since the loss will be | |
8427 | * uniform across all VCPUs (not to mention the scenario is extremely | |
8428 | * unlikely). It is possible that a second hibernate recovery happens | |
8429 | * much faster than a first, causing the observed TSC here to be | |
8430 | * smaller; this would require additional padding adjustment, which is | |
8431 | * why we set last_host_tsc to the local tsc observed here. | |
8432 | * | |
8433 | * N.B. - this code below runs only on platforms with reliable TSC, | |
8434 | * as that is the only way backwards_tsc is set above. Also note | |
8435 | * that this runs for ALL vcpus, which is not a bug; all VCPUs should | |
8436 | * have the same delta_cyc adjustment applied if backwards_tsc | |
8437 | * is detected. Note further, this adjustment is only done once, | |
8438 | * as we reset last_host_tsc on all VCPUs to stop this from being | |
8439 | * called multiple times (one for each physical CPU bringup). | |
8440 | * | |
4a969980 | 8441 | * Platforms with unreliable TSCs don't have to deal with this, they |
0dd6a6ed ZA |
8442 | * will be compensated by the logic in vcpu_load, which sets the TSC to |
8443 | * catchup mode. This will catchup all VCPUs to real time, but cannot | |
8444 | * guarantee that they stay in perfect synchronization. | |
8445 | */ | |
8446 | if (backwards_tsc) { | |
8447 | u64 delta_cyc = max_tsc - local_tsc; | |
8448 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
a826faf1 | 8449 | kvm->arch.backwards_tsc_observed = true; |
0dd6a6ed ZA |
8450 | kvm_for_each_vcpu(i, vcpu, kvm) { |
8451 | vcpu->arch.tsc_offset_adjustment += delta_cyc; | |
8452 | vcpu->arch.last_host_tsc = local_tsc; | |
105b21bb | 8453 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
8454 | } |
8455 | ||
8456 | /* | |
8457 | * We have to disable TSC offset matching.. if you were | |
8458 | * booting a VM while issuing an S4 host suspend.... | |
8459 | * you may have some problem. Solving this issue is | |
8460 | * left as an exercise to the reader. | |
8461 | */ | |
8462 | kvm->arch.last_tsc_nsec = 0; | |
8463 | kvm->arch.last_tsc_write = 0; | |
8464 | } | |
8465 | ||
8466 | } | |
8467 | return 0; | |
e9b11c17 ZX |
8468 | } |
8469 | ||
13a34e06 | 8470 | void kvm_arch_hardware_disable(void) |
e9b11c17 | 8471 | { |
13a34e06 RK |
8472 | kvm_x86_ops->hardware_disable(); |
8473 | drop_user_return_notifiers(); | |
e9b11c17 ZX |
8474 | } |
8475 | ||
8476 | int kvm_arch_hardware_setup(void) | |
8477 | { | |
9e9c3fe4 NA |
8478 | int r; |
8479 | ||
8480 | r = kvm_x86_ops->hardware_setup(); | |
8481 | if (r != 0) | |
8482 | return r; | |
8483 | ||
35181e86 HZ |
8484 | if (kvm_has_tsc_control) { |
8485 | /* | |
8486 | * Make sure the user can only configure tsc_khz values that | |
8487 | * fit into a signed integer. | |
8488 | * A min value is not calculated needed because it will always | |
8489 | * be 1 on all machines. | |
8490 | */ | |
8491 | u64 max = min(0x7fffffffULL, | |
8492 | __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); | |
8493 | kvm_max_guest_tsc_khz = max; | |
8494 | ||
ad721883 | 8495 | kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; |
35181e86 | 8496 | } |
ad721883 | 8497 | |
9e9c3fe4 NA |
8498 | kvm_init_msr_list(); |
8499 | return 0; | |
e9b11c17 ZX |
8500 | } |
8501 | ||
8502 | void kvm_arch_hardware_unsetup(void) | |
8503 | { | |
8504 | kvm_x86_ops->hardware_unsetup(); | |
8505 | } | |
8506 | ||
8507 | void kvm_arch_check_processor_compat(void *rtn) | |
8508 | { | |
8509 | kvm_x86_ops->check_processor_compatibility(rtn); | |
d71ba788 PB |
8510 | } |
8511 | ||
8512 | bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) | |
8513 | { | |
8514 | return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; | |
8515 | } | |
8516 | EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); | |
8517 | ||
8518 | bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) | |
8519 | { | |
8520 | return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; | |
e9b11c17 ZX |
8521 | } |
8522 | ||
54e9818f | 8523 | struct static_key kvm_no_apic_vcpu __read_mostly; |
bce87cce | 8524 | EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu); |
54e9818f | 8525 | |
e9b11c17 ZX |
8526 | int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) |
8527 | { | |
8528 | struct page *page; | |
e9b11c17 ZX |
8529 | int r; |
8530 | ||
b2a05fef | 8531 | vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu); |
9aabc88f | 8532 | vcpu->arch.emulate_ctxt.ops = &emulate_ops; |
26de7988 | 8533 | if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) |
a4535290 | 8534 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
e9b11c17 | 8535 | else |
a4535290 | 8536 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; |
e9b11c17 ZX |
8537 | |
8538 | page = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
8539 | if (!page) { | |
8540 | r = -ENOMEM; | |
8541 | goto fail; | |
8542 | } | |
ad312c7c | 8543 | vcpu->arch.pio_data = page_address(page); |
e9b11c17 | 8544 | |
cc578287 | 8545 | kvm_set_tsc_khz(vcpu, max_tsc_khz); |
c285545f | 8546 | |
e9b11c17 ZX |
8547 | r = kvm_mmu_create(vcpu); |
8548 | if (r < 0) | |
8549 | goto fail_free_pio_data; | |
8550 | ||
26de7988 | 8551 | if (irqchip_in_kernel(vcpu->kvm)) { |
e9b11c17 ZX |
8552 | r = kvm_create_lapic(vcpu); |
8553 | if (r < 0) | |
8554 | goto fail_mmu_destroy; | |
54e9818f GN |
8555 | } else |
8556 | static_key_slow_inc(&kvm_no_apic_vcpu); | |
e9b11c17 | 8557 | |
890ca9ae HY |
8558 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, |
8559 | GFP_KERNEL); | |
8560 | if (!vcpu->arch.mce_banks) { | |
8561 | r = -ENOMEM; | |
443c39bc | 8562 | goto fail_free_lapic; |
890ca9ae HY |
8563 | } |
8564 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
8565 | ||
f1797359 WY |
8566 | if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) { |
8567 | r = -ENOMEM; | |
f5f48ee1 | 8568 | goto fail_free_mce_banks; |
f1797359 | 8569 | } |
f5f48ee1 | 8570 | |
0ee6a517 | 8571 | fx_init(vcpu); |
66f7b72e | 8572 | |
4344ee98 | 8573 | vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; |
d7876f1b | 8574 | |
5a4f55cd EK |
8575 | vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); |
8576 | ||
74545705 RK |
8577 | vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; |
8578 | ||
af585b92 | 8579 | kvm_async_pf_hash_reset(vcpu); |
f5132b01 | 8580 | kvm_pmu_init(vcpu); |
af585b92 | 8581 | |
1c1a9ce9 | 8582 | vcpu->arch.pending_external_vector = -1; |
de63ad4c | 8583 | vcpu->arch.preempted_in_kernel = false; |
1c1a9ce9 | 8584 | |
5c919412 AS |
8585 | kvm_hv_vcpu_init(vcpu); |
8586 | ||
e9b11c17 | 8587 | return 0; |
0ee6a517 | 8588 | |
f5f48ee1 SY |
8589 | fail_free_mce_banks: |
8590 | kfree(vcpu->arch.mce_banks); | |
443c39bc WY |
8591 | fail_free_lapic: |
8592 | kvm_free_lapic(vcpu); | |
e9b11c17 ZX |
8593 | fail_mmu_destroy: |
8594 | kvm_mmu_destroy(vcpu); | |
8595 | fail_free_pio_data: | |
ad312c7c | 8596 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 ZX |
8597 | fail: |
8598 | return r; | |
8599 | } | |
8600 | ||
8601 | void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) | |
8602 | { | |
f656ce01 MT |
8603 | int idx; |
8604 | ||
1f4b34f8 | 8605 | kvm_hv_vcpu_uninit(vcpu); |
f5132b01 | 8606 | kvm_pmu_destroy(vcpu); |
36cb93fd | 8607 | kfree(vcpu->arch.mce_banks); |
e9b11c17 | 8608 | kvm_free_lapic(vcpu); |
f656ce01 | 8609 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
e9b11c17 | 8610 | kvm_mmu_destroy(vcpu); |
f656ce01 | 8611 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
ad312c7c | 8612 | free_page((unsigned long)vcpu->arch.pio_data); |
35754c98 | 8613 | if (!lapic_in_kernel(vcpu)) |
54e9818f | 8614 | static_key_slow_dec(&kvm_no_apic_vcpu); |
e9b11c17 | 8615 | } |
d19a9cd2 | 8616 | |
e790d9ef RK |
8617 | void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) |
8618 | { | |
ae97a3b8 | 8619 | kvm_x86_ops->sched_in(vcpu, cpu); |
e790d9ef RK |
8620 | } |
8621 | ||
e08b9637 | 8622 | int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) |
d19a9cd2 | 8623 | { |
e08b9637 CO |
8624 | if (type) |
8625 | return -EINVAL; | |
8626 | ||
6ef768fa | 8627 | INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); |
f05e70ac | 8628 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
365c8868 | 8629 | INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); |
4d5c5d0f | 8630 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
e0f0bbc5 | 8631 | atomic_set(&kvm->arch.noncoherent_dma_count, 0); |
d19a9cd2 | 8632 | |
5550af4d SY |
8633 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
8634 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
7a84428a AW |
8635 | /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ |
8636 | set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, | |
8637 | &kvm->arch.irq_sources_bitmap); | |
5550af4d | 8638 | |
038f8c11 | 8639 | raw_spin_lock_init(&kvm->arch.tsc_write_lock); |
1e08ec4a | 8640 | mutex_init(&kvm->arch.apic_map_lock); |
d828199e MT |
8641 | spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); |
8642 | ||
108b249c | 8643 | kvm->arch.kvmclock_offset = -ktime_get_boot_ns(); |
d828199e | 8644 | pvclock_update_vm_gtod_copy(kvm); |
53f658b3 | 8645 | |
7e44e449 | 8646 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); |
332967a3 | 8647 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); |
7e44e449 | 8648 | |
cbc0236a | 8649 | kvm_hv_init_vm(kvm); |
0eb05bf2 | 8650 | kvm_page_track_init(kvm); |
13d268ca | 8651 | kvm_mmu_init_vm(kvm); |
0eb05bf2 | 8652 | |
03543133 SS |
8653 | if (kvm_x86_ops->vm_init) |
8654 | return kvm_x86_ops->vm_init(kvm); | |
8655 | ||
d89f5eff | 8656 | return 0; |
d19a9cd2 ZX |
8657 | } |
8658 | ||
8659 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) | |
8660 | { | |
ec7660cc | 8661 | vcpu_load(vcpu); |
d19a9cd2 ZX |
8662 | kvm_mmu_unload(vcpu); |
8663 | vcpu_put(vcpu); | |
8664 | } | |
8665 | ||
8666 | static void kvm_free_vcpus(struct kvm *kvm) | |
8667 | { | |
8668 | unsigned int i; | |
988a2cae | 8669 | struct kvm_vcpu *vcpu; |
d19a9cd2 ZX |
8670 | |
8671 | /* | |
8672 | * Unpin any mmu pages first. | |
8673 | */ | |
af585b92 GN |
8674 | kvm_for_each_vcpu(i, vcpu, kvm) { |
8675 | kvm_clear_async_pf_completion_queue(vcpu); | |
988a2cae | 8676 | kvm_unload_vcpu_mmu(vcpu); |
af585b92 | 8677 | } |
988a2cae GN |
8678 | kvm_for_each_vcpu(i, vcpu, kvm) |
8679 | kvm_arch_vcpu_free(vcpu); | |
8680 | ||
8681 | mutex_lock(&kvm->lock); | |
8682 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
8683 | kvm->vcpus[i] = NULL; | |
d19a9cd2 | 8684 | |
988a2cae GN |
8685 | atomic_set(&kvm->online_vcpus, 0); |
8686 | mutex_unlock(&kvm->lock); | |
d19a9cd2 ZX |
8687 | } |
8688 | ||
ad8ba2cd SY |
8689 | void kvm_arch_sync_events(struct kvm *kvm) |
8690 | { | |
332967a3 | 8691 | cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); |
7e44e449 | 8692 | cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); |
aea924f6 | 8693 | kvm_free_pit(kvm); |
ad8ba2cd SY |
8694 | } |
8695 | ||
1d8007bd | 8696 | int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) |
9da0e4d5 PB |
8697 | { |
8698 | int i, r; | |
25188b99 | 8699 | unsigned long hva; |
f0d648bd PB |
8700 | struct kvm_memslots *slots = kvm_memslots(kvm); |
8701 | struct kvm_memory_slot *slot, old; | |
9da0e4d5 PB |
8702 | |
8703 | /* Called with kvm->slots_lock held. */ | |
1d8007bd PB |
8704 | if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) |
8705 | return -EINVAL; | |
9da0e4d5 | 8706 | |
f0d648bd PB |
8707 | slot = id_to_memslot(slots, id); |
8708 | if (size) { | |
b21629da | 8709 | if (slot->npages) |
f0d648bd PB |
8710 | return -EEXIST; |
8711 | ||
8712 | /* | |
8713 | * MAP_SHARED to prevent internal slot pages from being moved | |
8714 | * by fork()/COW. | |
8715 | */ | |
8716 | hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, | |
8717 | MAP_SHARED | MAP_ANONYMOUS, 0); | |
8718 | if (IS_ERR((void *)hva)) | |
8719 | return PTR_ERR((void *)hva); | |
8720 | } else { | |
8721 | if (!slot->npages) | |
8722 | return 0; | |
8723 | ||
8724 | hva = 0; | |
8725 | } | |
8726 | ||
8727 | old = *slot; | |
9da0e4d5 | 8728 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
1d8007bd | 8729 | struct kvm_userspace_memory_region m; |
9da0e4d5 | 8730 | |
1d8007bd PB |
8731 | m.slot = id | (i << 16); |
8732 | m.flags = 0; | |
8733 | m.guest_phys_addr = gpa; | |
f0d648bd | 8734 | m.userspace_addr = hva; |
1d8007bd | 8735 | m.memory_size = size; |
9da0e4d5 PB |
8736 | r = __kvm_set_memory_region(kvm, &m); |
8737 | if (r < 0) | |
8738 | return r; | |
8739 | } | |
8740 | ||
103c763c EB |
8741 | if (!size) |
8742 | vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE); | |
f0d648bd | 8743 | |
9da0e4d5 PB |
8744 | return 0; |
8745 | } | |
8746 | EXPORT_SYMBOL_GPL(__x86_set_memory_region); | |
8747 | ||
1d8007bd | 8748 | int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) |
9da0e4d5 PB |
8749 | { |
8750 | int r; | |
8751 | ||
8752 | mutex_lock(&kvm->slots_lock); | |
1d8007bd | 8753 | r = __x86_set_memory_region(kvm, id, gpa, size); |
9da0e4d5 PB |
8754 | mutex_unlock(&kvm->slots_lock); |
8755 | ||
8756 | return r; | |
8757 | } | |
8758 | EXPORT_SYMBOL_GPL(x86_set_memory_region); | |
8759 | ||
d19a9cd2 ZX |
8760 | void kvm_arch_destroy_vm(struct kvm *kvm) |
8761 | { | |
27469d29 AH |
8762 | if (current->mm == kvm->mm) { |
8763 | /* | |
8764 | * Free memory regions allocated on behalf of userspace, | |
8765 | * unless the the memory map has changed due to process exit | |
8766 | * or fd copying. | |
8767 | */ | |
1d8007bd PB |
8768 | x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0); |
8769 | x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0); | |
8770 | x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); | |
27469d29 | 8771 | } |
03543133 SS |
8772 | if (kvm_x86_ops->vm_destroy) |
8773 | kvm_x86_ops->vm_destroy(kvm); | |
c761159c PX |
8774 | kvm_pic_destroy(kvm); |
8775 | kvm_ioapic_destroy(kvm); | |
d19a9cd2 | 8776 | kvm_free_vcpus(kvm); |
af1bae54 | 8777 | kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); |
13d268ca | 8778 | kvm_mmu_uninit_vm(kvm); |
2beb6dad | 8779 | kvm_page_track_cleanup(kvm); |
cbc0236a | 8780 | kvm_hv_destroy_vm(kvm); |
d19a9cd2 | 8781 | } |
0de10343 | 8782 | |
5587027c | 8783 | void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, |
db3fe4eb TY |
8784 | struct kvm_memory_slot *dont) |
8785 | { | |
8786 | int i; | |
8787 | ||
d89cc617 TY |
8788 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
8789 | if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { | |
548ef284 | 8790 | kvfree(free->arch.rmap[i]); |
d89cc617 | 8791 | free->arch.rmap[i] = NULL; |
77d11309 | 8792 | } |
d89cc617 TY |
8793 | if (i == 0) |
8794 | continue; | |
8795 | ||
8796 | if (!dont || free->arch.lpage_info[i - 1] != | |
8797 | dont->arch.lpage_info[i - 1]) { | |
548ef284 | 8798 | kvfree(free->arch.lpage_info[i - 1]); |
d89cc617 | 8799 | free->arch.lpage_info[i - 1] = NULL; |
db3fe4eb TY |
8800 | } |
8801 | } | |
21ebbeda XG |
8802 | |
8803 | kvm_page_track_free_memslot(free, dont); | |
db3fe4eb TY |
8804 | } |
8805 | ||
5587027c AK |
8806 | int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, |
8807 | unsigned long npages) | |
db3fe4eb TY |
8808 | { |
8809 | int i; | |
8810 | ||
d89cc617 | 8811 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
92f94f1e | 8812 | struct kvm_lpage_info *linfo; |
db3fe4eb TY |
8813 | unsigned long ugfn; |
8814 | int lpages; | |
d89cc617 | 8815 | int level = i + 1; |
db3fe4eb TY |
8816 | |
8817 | lpages = gfn_to_index(slot->base_gfn + npages - 1, | |
8818 | slot->base_gfn, level) + 1; | |
8819 | ||
d89cc617 | 8820 | slot->arch.rmap[i] = |
a7c3e901 | 8821 | kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL); |
d89cc617 | 8822 | if (!slot->arch.rmap[i]) |
77d11309 | 8823 | goto out_free; |
d89cc617 TY |
8824 | if (i == 0) |
8825 | continue; | |
77d11309 | 8826 | |
a7c3e901 | 8827 | linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL); |
92f94f1e | 8828 | if (!linfo) |
db3fe4eb TY |
8829 | goto out_free; |
8830 | ||
92f94f1e XG |
8831 | slot->arch.lpage_info[i - 1] = linfo; |
8832 | ||
db3fe4eb | 8833 | if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 8834 | linfo[0].disallow_lpage = 1; |
db3fe4eb | 8835 | if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 8836 | linfo[lpages - 1].disallow_lpage = 1; |
db3fe4eb TY |
8837 | ugfn = slot->userspace_addr >> PAGE_SHIFT; |
8838 | /* | |
8839 | * If the gfn and userspace address are not aligned wrt each | |
8840 | * other, or if explicitly asked to, disable large page | |
8841 | * support for this slot | |
8842 | */ | |
8843 | if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || | |
8844 | !kvm_largepages_enabled()) { | |
8845 | unsigned long j; | |
8846 | ||
8847 | for (j = 0; j < lpages; ++j) | |
92f94f1e | 8848 | linfo[j].disallow_lpage = 1; |
db3fe4eb TY |
8849 | } |
8850 | } | |
8851 | ||
21ebbeda XG |
8852 | if (kvm_page_track_create_memslot(slot, npages)) |
8853 | goto out_free; | |
8854 | ||
db3fe4eb TY |
8855 | return 0; |
8856 | ||
8857 | out_free: | |
d89cc617 | 8858 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
548ef284 | 8859 | kvfree(slot->arch.rmap[i]); |
d89cc617 TY |
8860 | slot->arch.rmap[i] = NULL; |
8861 | if (i == 0) | |
8862 | continue; | |
8863 | ||
548ef284 | 8864 | kvfree(slot->arch.lpage_info[i - 1]); |
d89cc617 | 8865 | slot->arch.lpage_info[i - 1] = NULL; |
db3fe4eb TY |
8866 | } |
8867 | return -ENOMEM; | |
8868 | } | |
8869 | ||
15f46015 | 8870 | void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) |
e59dbe09 | 8871 | { |
e6dff7d1 TY |
8872 | /* |
8873 | * memslots->generation has been incremented. | |
8874 | * mmio generation may have reached its maximum value. | |
8875 | */ | |
54bf36aa | 8876 | kvm_mmu_invalidate_mmio_sptes(kvm, slots); |
e59dbe09 TY |
8877 | } |
8878 | ||
f7784b8e MT |
8879 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
8880 | struct kvm_memory_slot *memslot, | |
09170a49 | 8881 | const struct kvm_userspace_memory_region *mem, |
7b6195a9 | 8882 | enum kvm_mr_change change) |
0de10343 | 8883 | { |
f7784b8e MT |
8884 | return 0; |
8885 | } | |
8886 | ||
88178fd4 KH |
8887 | static void kvm_mmu_slot_apply_flags(struct kvm *kvm, |
8888 | struct kvm_memory_slot *new) | |
8889 | { | |
8890 | /* Still write protect RO slot */ | |
8891 | if (new->flags & KVM_MEM_READONLY) { | |
8892 | kvm_mmu_slot_remove_write_access(kvm, new); | |
8893 | return; | |
8894 | } | |
8895 | ||
8896 | /* | |
8897 | * Call kvm_x86_ops dirty logging hooks when they are valid. | |
8898 | * | |
8899 | * kvm_x86_ops->slot_disable_log_dirty is called when: | |
8900 | * | |
8901 | * - KVM_MR_CREATE with dirty logging is disabled | |
8902 | * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag | |
8903 | * | |
8904 | * The reason is, in case of PML, we need to set D-bit for any slots | |
8905 | * with dirty logging disabled in order to eliminate unnecessary GPA | |
8906 | * logging in PML buffer (and potential PML buffer full VMEXT). This | |
8907 | * guarantees leaving PML enabled during guest's lifetime won't have | |
8908 | * any additonal overhead from PML when guest is running with dirty | |
8909 | * logging disabled for memory slots. | |
8910 | * | |
8911 | * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot | |
8912 | * to dirty logging mode. | |
8913 | * | |
8914 | * If kvm_x86_ops dirty logging hooks are invalid, use write protect. | |
8915 | * | |
8916 | * In case of write protect: | |
8917 | * | |
8918 | * Write protect all pages for dirty logging. | |
8919 | * | |
8920 | * All the sptes including the large sptes which point to this | |
8921 | * slot are set to readonly. We can not create any new large | |
8922 | * spte on this slot until the end of the logging. | |
8923 | * | |
8924 | * See the comments in fast_page_fault(). | |
8925 | */ | |
8926 | if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { | |
8927 | if (kvm_x86_ops->slot_enable_log_dirty) | |
8928 | kvm_x86_ops->slot_enable_log_dirty(kvm, new); | |
8929 | else | |
8930 | kvm_mmu_slot_remove_write_access(kvm, new); | |
8931 | } else { | |
8932 | if (kvm_x86_ops->slot_disable_log_dirty) | |
8933 | kvm_x86_ops->slot_disable_log_dirty(kvm, new); | |
8934 | } | |
8935 | } | |
8936 | ||
f7784b8e | 8937 | void kvm_arch_commit_memory_region(struct kvm *kvm, |
09170a49 | 8938 | const struct kvm_userspace_memory_region *mem, |
8482644a | 8939 | const struct kvm_memory_slot *old, |
f36f3f28 | 8940 | const struct kvm_memory_slot *new, |
8482644a | 8941 | enum kvm_mr_change change) |
f7784b8e | 8942 | { |
8482644a | 8943 | int nr_mmu_pages = 0; |
f7784b8e | 8944 | |
48c0e4e9 XG |
8945 | if (!kvm->arch.n_requested_mmu_pages) |
8946 | nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); | |
8947 | ||
48c0e4e9 | 8948 | if (nr_mmu_pages) |
0de10343 | 8949 | kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); |
1c91cad4 | 8950 | |
3ea3b7fa WL |
8951 | /* |
8952 | * Dirty logging tracks sptes in 4k granularity, meaning that large | |
8953 | * sptes have to be split. If live migration is successful, the guest | |
8954 | * in the source machine will be destroyed and large sptes will be | |
8955 | * created in the destination. However, if the guest continues to run | |
8956 | * in the source machine (for example if live migration fails), small | |
8957 | * sptes will remain around and cause bad performance. | |
8958 | * | |
8959 | * Scan sptes if dirty logging has been stopped, dropping those | |
8960 | * which can be collapsed into a single large-page spte. Later | |
8961 | * page faults will create the large-page sptes. | |
8962 | */ | |
8963 | if ((change != KVM_MR_DELETE) && | |
8964 | (old->flags & KVM_MEM_LOG_DIRTY_PAGES) && | |
8965 | !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) | |
8966 | kvm_mmu_zap_collapsible_sptes(kvm, new); | |
8967 | ||
c972f3b1 | 8968 | /* |
88178fd4 | 8969 | * Set up write protection and/or dirty logging for the new slot. |
c126d94f | 8970 | * |
88178fd4 KH |
8971 | * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have |
8972 | * been zapped so no dirty logging staff is needed for old slot. For | |
8973 | * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the | |
8974 | * new and it's also covered when dealing with the new slot. | |
f36f3f28 PB |
8975 | * |
8976 | * FIXME: const-ify all uses of struct kvm_memory_slot. | |
c972f3b1 | 8977 | */ |
88178fd4 | 8978 | if (change != KVM_MR_DELETE) |
f36f3f28 | 8979 | kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new); |
0de10343 | 8980 | } |
1d737c8a | 8981 | |
2df72e9b | 8982 | void kvm_arch_flush_shadow_all(struct kvm *kvm) |
34d4cb8f | 8983 | { |
6ca18b69 | 8984 | kvm_mmu_invalidate_zap_all_pages(kvm); |
34d4cb8f MT |
8985 | } |
8986 | ||
2df72e9b MT |
8987 | void kvm_arch_flush_shadow_memslot(struct kvm *kvm, |
8988 | struct kvm_memory_slot *slot) | |
8989 | { | |
ae7cd873 | 8990 | kvm_page_track_flush_slot(kvm, slot); |
2df72e9b MT |
8991 | } |
8992 | ||
5d9bc648 PB |
8993 | static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) |
8994 | { | |
8995 | if (!list_empty_careful(&vcpu->async_pf.done)) | |
8996 | return true; | |
8997 | ||
8998 | if (kvm_apic_has_events(vcpu)) | |
8999 | return true; | |
9000 | ||
9001 | if (vcpu->arch.pv.pv_unhalted) | |
9002 | return true; | |
9003 | ||
a5f01f8e WL |
9004 | if (vcpu->arch.exception.pending) |
9005 | return true; | |
9006 | ||
47a66eed Z |
9007 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || |
9008 | (vcpu->arch.nmi_pending && | |
9009 | kvm_x86_ops->nmi_allowed(vcpu))) | |
5d9bc648 PB |
9010 | return true; |
9011 | ||
47a66eed Z |
9012 | if (kvm_test_request(KVM_REQ_SMI, vcpu) || |
9013 | (vcpu->arch.smi_pending && !is_smm(vcpu))) | |
73917739 PB |
9014 | return true; |
9015 | ||
5d9bc648 PB |
9016 | if (kvm_arch_interrupt_allowed(vcpu) && |
9017 | kvm_cpu_has_interrupt(vcpu)) | |
9018 | return true; | |
9019 | ||
1f4b34f8 AS |
9020 | if (kvm_hv_has_stimer_pending(vcpu)) |
9021 | return true; | |
9022 | ||
5d9bc648 PB |
9023 | return false; |
9024 | } | |
9025 | ||
1d737c8a ZX |
9026 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
9027 | { | |
5d9bc648 | 9028 | return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); |
1d737c8a | 9029 | } |
5736199a | 9030 | |
199b5763 LM |
9031 | bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) |
9032 | { | |
de63ad4c | 9033 | return vcpu->arch.preempted_in_kernel; |
199b5763 LM |
9034 | } |
9035 | ||
b6d33834 | 9036 | int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) |
5736199a | 9037 | { |
b6d33834 | 9038 | return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; |
5736199a | 9039 | } |
78646121 GN |
9040 | |
9041 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
9042 | { | |
9043 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
9044 | } | |
229456fc | 9045 | |
82b32774 | 9046 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) |
f92653ee | 9047 | { |
82b32774 NA |
9048 | if (is_64_bit_mode(vcpu)) |
9049 | return kvm_rip_read(vcpu); | |
9050 | return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + | |
9051 | kvm_rip_read(vcpu)); | |
9052 | } | |
9053 | EXPORT_SYMBOL_GPL(kvm_get_linear_rip); | |
f92653ee | 9054 | |
82b32774 NA |
9055 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) |
9056 | { | |
9057 | return kvm_get_linear_rip(vcpu) == linear_rip; | |
f92653ee JK |
9058 | } |
9059 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
9060 | ||
94fe45da JK |
9061 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
9062 | { | |
9063 | unsigned long rflags; | |
9064 | ||
9065 | rflags = kvm_x86_ops->get_rflags(vcpu); | |
9066 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
c310bac5 | 9067 | rflags &= ~X86_EFLAGS_TF; |
94fe45da JK |
9068 | return rflags; |
9069 | } | |
9070 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
9071 | ||
6addfc42 | 9072 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) |
94fe45da JK |
9073 | { |
9074 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
f92653ee | 9075 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) |
c310bac5 | 9076 | rflags |= X86_EFLAGS_TF; |
94fe45da | 9077 | kvm_x86_ops->set_rflags(vcpu, rflags); |
6addfc42 PB |
9078 | } |
9079 | ||
9080 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
9081 | { | |
9082 | __kvm_set_rflags(vcpu, rflags); | |
3842d135 | 9083 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
94fe45da JK |
9084 | } |
9085 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
9086 | ||
56028d08 GN |
9087 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) |
9088 | { | |
9089 | int r; | |
9090 | ||
fb67e14f | 9091 | if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) || |
f2e10669 | 9092 | work->wakeup_all) |
56028d08 GN |
9093 | return; |
9094 | ||
9095 | r = kvm_mmu_reload(vcpu); | |
9096 | if (unlikely(r)) | |
9097 | return; | |
9098 | ||
fb67e14f XG |
9099 | if (!vcpu->arch.mmu.direct_map && |
9100 | work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu)) | |
9101 | return; | |
9102 | ||
56028d08 GN |
9103 | vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); |
9104 | } | |
9105 | ||
af585b92 GN |
9106 | static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) |
9107 | { | |
9108 | return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); | |
9109 | } | |
9110 | ||
9111 | static inline u32 kvm_async_pf_next_probe(u32 key) | |
9112 | { | |
9113 | return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); | |
9114 | } | |
9115 | ||
9116 | static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
9117 | { | |
9118 | u32 key = kvm_async_pf_hash_fn(gfn); | |
9119 | ||
9120 | while (vcpu->arch.apf.gfns[key] != ~0) | |
9121 | key = kvm_async_pf_next_probe(key); | |
9122 | ||
9123 | vcpu->arch.apf.gfns[key] = gfn; | |
9124 | } | |
9125 | ||
9126 | static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) | |
9127 | { | |
9128 | int i; | |
9129 | u32 key = kvm_async_pf_hash_fn(gfn); | |
9130 | ||
9131 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && | |
c7d28c24 XG |
9132 | (vcpu->arch.apf.gfns[key] != gfn && |
9133 | vcpu->arch.apf.gfns[key] != ~0); i++) | |
af585b92 GN |
9134 | key = kvm_async_pf_next_probe(key); |
9135 | ||
9136 | return key; | |
9137 | } | |
9138 | ||
9139 | bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
9140 | { | |
9141 | return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; | |
9142 | } | |
9143 | ||
9144 | static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
9145 | { | |
9146 | u32 i, j, k; | |
9147 | ||
9148 | i = j = kvm_async_pf_gfn_slot(vcpu, gfn); | |
9149 | while (true) { | |
9150 | vcpu->arch.apf.gfns[i] = ~0; | |
9151 | do { | |
9152 | j = kvm_async_pf_next_probe(j); | |
9153 | if (vcpu->arch.apf.gfns[j] == ~0) | |
9154 | return; | |
9155 | k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); | |
9156 | /* | |
9157 | * k lies cyclically in ]i,j] | |
9158 | * | i.k.j | | |
9159 | * |....j i.k.| or |.k..j i...| | |
9160 | */ | |
9161 | } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); | |
9162 | vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; | |
9163 | i = j; | |
9164 | } | |
9165 | } | |
9166 | ||
7c90705b GN |
9167 | static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) |
9168 | { | |
4e335d9e PB |
9169 | |
9170 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, | |
9171 | sizeof(val)); | |
7c90705b GN |
9172 | } |
9173 | ||
9a6e7c39 WL |
9174 | static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val) |
9175 | { | |
9176 | ||
9177 | return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val, | |
9178 | sizeof(u32)); | |
9179 | } | |
9180 | ||
af585b92 GN |
9181 | void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
9182 | struct kvm_async_pf *work) | |
9183 | { | |
6389ee94 AK |
9184 | struct x86_exception fault; |
9185 | ||
7c90705b | 9186 | trace_kvm_async_pf_not_present(work->arch.token, work->gva); |
af585b92 | 9187 | kvm_add_async_pf_gfn(vcpu, work->arch.gfn); |
7c90705b GN |
9188 | |
9189 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || | |
fc5f06fa GN |
9190 | (vcpu->arch.apf.send_user_only && |
9191 | kvm_x86_ops->get_cpl(vcpu) == 0)) | |
7c90705b GN |
9192 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); |
9193 | else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { | |
6389ee94 AK |
9194 | fault.vector = PF_VECTOR; |
9195 | fault.error_code_valid = true; | |
9196 | fault.error_code = 0; | |
9197 | fault.nested_page_fault = false; | |
9198 | fault.address = work->arch.token; | |
adfe20fb | 9199 | fault.async_page_fault = true; |
6389ee94 | 9200 | kvm_inject_page_fault(vcpu, &fault); |
7c90705b | 9201 | } |
af585b92 GN |
9202 | } |
9203 | ||
9204 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
9205 | struct kvm_async_pf *work) | |
9206 | { | |
6389ee94 | 9207 | struct x86_exception fault; |
9a6e7c39 | 9208 | u32 val; |
6389ee94 | 9209 | |
f2e10669 | 9210 | if (work->wakeup_all) |
7c90705b GN |
9211 | work->arch.token = ~0; /* broadcast wakeup */ |
9212 | else | |
9213 | kvm_del_async_pf_gfn(vcpu, work->arch.gfn); | |
24dccf83 | 9214 | trace_kvm_async_pf_ready(work->arch.token, work->gva); |
7c90705b | 9215 | |
9a6e7c39 WL |
9216 | if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED && |
9217 | !apf_get_user(vcpu, &val)) { | |
9218 | if (val == KVM_PV_REASON_PAGE_NOT_PRESENT && | |
9219 | vcpu->arch.exception.pending && | |
9220 | vcpu->arch.exception.nr == PF_VECTOR && | |
9221 | !apf_put_user(vcpu, 0)) { | |
9222 | vcpu->arch.exception.injected = false; | |
9223 | vcpu->arch.exception.pending = false; | |
9224 | vcpu->arch.exception.nr = 0; | |
9225 | vcpu->arch.exception.has_error_code = false; | |
9226 | vcpu->arch.exception.error_code = 0; | |
9227 | } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { | |
9228 | fault.vector = PF_VECTOR; | |
9229 | fault.error_code_valid = true; | |
9230 | fault.error_code = 0; | |
9231 | fault.nested_page_fault = false; | |
9232 | fault.address = work->arch.token; | |
9233 | fault.async_page_fault = true; | |
9234 | kvm_inject_page_fault(vcpu, &fault); | |
9235 | } | |
7c90705b | 9236 | } |
e6d53e3b | 9237 | vcpu->arch.apf.halted = false; |
a4fa1635 | 9238 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
7c90705b GN |
9239 | } |
9240 | ||
9241 | bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) | |
9242 | { | |
9243 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) | |
9244 | return true; | |
9245 | else | |
9bc1f09f | 9246 | return kvm_can_do_async_pf(vcpu); |
af585b92 GN |
9247 | } |
9248 | ||
5544eb9b PB |
9249 | void kvm_arch_start_assignment(struct kvm *kvm) |
9250 | { | |
9251 | atomic_inc(&kvm->arch.assigned_device_count); | |
9252 | } | |
9253 | EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); | |
9254 | ||
9255 | void kvm_arch_end_assignment(struct kvm *kvm) | |
9256 | { | |
9257 | atomic_dec(&kvm->arch.assigned_device_count); | |
9258 | } | |
9259 | EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); | |
9260 | ||
9261 | bool kvm_arch_has_assigned_device(struct kvm *kvm) | |
9262 | { | |
9263 | return atomic_read(&kvm->arch.assigned_device_count); | |
9264 | } | |
9265 | EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); | |
9266 | ||
e0f0bbc5 AW |
9267 | void kvm_arch_register_noncoherent_dma(struct kvm *kvm) |
9268 | { | |
9269 | atomic_inc(&kvm->arch.noncoherent_dma_count); | |
9270 | } | |
9271 | EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); | |
9272 | ||
9273 | void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) | |
9274 | { | |
9275 | atomic_dec(&kvm->arch.noncoherent_dma_count); | |
9276 | } | |
9277 | EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); | |
9278 | ||
9279 | bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) | |
9280 | { | |
9281 | return atomic_read(&kvm->arch.noncoherent_dma_count); | |
9282 | } | |
9283 | EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); | |
9284 | ||
14717e20 AW |
9285 | bool kvm_arch_has_irq_bypass(void) |
9286 | { | |
9287 | return kvm_x86_ops->update_pi_irte != NULL; | |
9288 | } | |
9289 | ||
87276880 FW |
9290 | int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, |
9291 | struct irq_bypass_producer *prod) | |
9292 | { | |
9293 | struct kvm_kernel_irqfd *irqfd = | |
9294 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
9295 | ||
14717e20 | 9296 | irqfd->producer = prod; |
87276880 | 9297 | |
14717e20 AW |
9298 | return kvm_x86_ops->update_pi_irte(irqfd->kvm, |
9299 | prod->irq, irqfd->gsi, 1); | |
87276880 FW |
9300 | } |
9301 | ||
9302 | void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, | |
9303 | struct irq_bypass_producer *prod) | |
9304 | { | |
9305 | int ret; | |
9306 | struct kvm_kernel_irqfd *irqfd = | |
9307 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
9308 | ||
87276880 FW |
9309 | WARN_ON(irqfd->producer != prod); |
9310 | irqfd->producer = NULL; | |
9311 | ||
9312 | /* | |
9313 | * When producer of consumer is unregistered, we change back to | |
9314 | * remapped mode, so we can re-use the current implementation | |
bb3541f1 | 9315 | * when the irq is masked/disabled or the consumer side (KVM |
87276880 FW |
9316 | * int this case doesn't want to receive the interrupts. |
9317 | */ | |
9318 | ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0); | |
9319 | if (ret) | |
9320 | printk(KERN_INFO "irq bypass consumer (token %p) unregistration" | |
9321 | " fails: %d\n", irqfd->consumer.token, ret); | |
9322 | } | |
9323 | ||
9324 | int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, | |
9325 | uint32_t guest_irq, bool set) | |
9326 | { | |
9327 | if (!kvm_x86_ops->update_pi_irte) | |
9328 | return -EINVAL; | |
9329 | ||
9330 | return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set); | |
9331 | } | |
9332 | ||
52004014 FW |
9333 | bool kvm_vector_hashing_enabled(void) |
9334 | { | |
9335 | return vector_hashing; | |
9336 | } | |
9337 | EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled); | |
9338 | ||
229456fc | 9339 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
931c33b1 | 9340 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); |
229456fc MT |
9341 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); |
9342 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
9343 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
9344 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
0ac406de | 9345 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); |
d8cabddf | 9346 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 9347 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 9348 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
ec1ff790 | 9349 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 9350 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |
2e554e8d | 9351 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); |
489223ed | 9352 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); |
7b46268d | 9353 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window); |
843e4330 | 9354 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); |
efc64404 | 9355 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); |
18f40c53 SS |
9356 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); |
9357 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); |