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20c8ccb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
043405e1 CO |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * | |
5 | * derived from drivers/kvm/kvm_main.c | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
8 | * Copyright (C) 2008 Qumranet, Inc. |
9 | * Copyright IBM Corporation, 2008 | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
043405e1 CO |
11 | * |
12 | * Authors: | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
15 | * Amit Shah <amit.shah@qumranet.com> |
16 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
17 | */ |
18 | ||
edf88417 | 19 | #include <linux/kvm_host.h> |
313a3dc7 | 20 | #include "irq.h" |
88197e6a | 21 | #include "ioapic.h" |
1d737c8a | 22 | #include "mmu.h" |
7837699f | 23 | #include "i8254.h" |
37817f29 | 24 | #include "tss.h" |
5fdbf976 | 25 | #include "kvm_cache_regs.h" |
2f728d66 | 26 | #include "kvm_emulate.h" |
26eef70c | 27 | #include "x86.h" |
00b27a3e | 28 | #include "cpuid.h" |
474a5bb9 | 29 | #include "pmu.h" |
e83d5887 | 30 | #include "hyperv.h" |
8df14af4 | 31 | #include "lapic.h" |
23200b7a | 32 | #include "xen.h" |
313a3dc7 | 33 | |
18068523 | 34 | #include <linux/clocksource.h> |
4d5c5d0f | 35 | #include <linux/interrupt.h> |
313a3dc7 CO |
36 | #include <linux/kvm.h> |
37 | #include <linux/fs.h> | |
38 | #include <linux/vmalloc.h> | |
1767e931 PG |
39 | #include <linux/export.h> |
40 | #include <linux/moduleparam.h> | |
0de10343 | 41 | #include <linux/mman.h> |
2bacc55c | 42 | #include <linux/highmem.h> |
19de40a8 | 43 | #include <linux/iommu.h> |
62c476c7 | 44 | #include <linux/intel-iommu.h> |
c8076604 | 45 | #include <linux/cpufreq.h> |
18863bdd | 46 | #include <linux/user-return-notifier.h> |
a983fb23 | 47 | #include <linux/srcu.h> |
5a0e3ad6 | 48 | #include <linux/slab.h> |
ff9d07a0 | 49 | #include <linux/perf_event.h> |
7bee342a | 50 | #include <linux/uaccess.h> |
af585b92 | 51 | #include <linux/hash.h> |
a1b60c1c | 52 | #include <linux/pci.h> |
16e8d74d MT |
53 | #include <linux/timekeeper_internal.h> |
54 | #include <linux/pvclock_gtod.h> | |
87276880 FW |
55 | #include <linux/kvm_irqfd.h> |
56 | #include <linux/irqbypass.h> | |
3905f9ad | 57 | #include <linux/sched/stat.h> |
0c5f81da | 58 | #include <linux/sched/isolation.h> |
d0ec49d4 | 59 | #include <linux/mem_encrypt.h> |
72c3c0fe | 60 | #include <linux/entry-kvm.h> |
7d62874f | 61 | #include <linux/suspend.h> |
3905f9ad | 62 | |
aec51dc4 | 63 | #include <trace/events/kvm.h> |
2ed152af | 64 | |
24f1e32c | 65 | #include <asm/debugreg.h> |
d825ed0a | 66 | #include <asm/msr.h> |
a5f61300 | 67 | #include <asm/desc.h> |
890ca9ae | 68 | #include <asm/mce.h> |
784a4661 | 69 | #include <asm/pkru.h> |
f89e32e0 | 70 | #include <linux/kernel_stat.h> |
78f7f1e5 | 71 | #include <asm/fpu/internal.h> /* Ugh! */ |
1d5f066e | 72 | #include <asm/pvclock.h> |
217fc9cf | 73 | #include <asm/div64.h> |
efc64404 | 74 | #include <asm/irq_remapping.h> |
b0c39dc6 | 75 | #include <asm/mshyperv.h> |
0092e434 | 76 | #include <asm/hypervisor.h> |
9715092f | 77 | #include <asm/tlbflush.h> |
bf8c55d8 | 78 | #include <asm/intel_pt.h> |
b3dc0695 | 79 | #include <asm/emulate_prefix.h> |
fe7e9488 | 80 | #include <asm/sgx.h> |
dd2cb348 | 81 | #include <clocksource/hyperv_timer.h> |
043405e1 | 82 | |
d1898b73 DH |
83 | #define CREATE_TRACE_POINTS |
84 | #include "trace.h" | |
85 | ||
313a3dc7 | 86 | #define MAX_IO_MSRS 256 |
890ca9ae | 87 | #define KVM_MAX_MCE_BANKS 32 |
c45dcc71 AR |
88 | u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; |
89 | EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); | |
890ca9ae | 90 | |
0f65dd70 | 91 | #define emul_to_vcpu(ctxt) \ |
c9b8b07c | 92 | ((struct kvm_vcpu *)(ctxt)->vcpu) |
0f65dd70 | 93 | |
50a37eb4 JR |
94 | /* EFER defaults: |
95 | * - enable syscall per default because its emulated by KVM | |
96 | * - enable LME and LMA per default on 64 bit KVM | |
97 | */ | |
98 | #ifdef CONFIG_X86_64 | |
1260edbe LJ |
99 | static |
100 | u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); | |
50a37eb4 | 101 | #else |
1260edbe | 102 | static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); |
50a37eb4 | 103 | #endif |
313a3dc7 | 104 | |
b11306b5 SC |
105 | static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; |
106 | ||
0dbb1123 AK |
107 | #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE) |
108 | ||
c519265f RK |
109 | #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ |
110 | KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) | |
37131313 | 111 | |
cb142eb7 | 112 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
7460fb4a | 113 | static void process_nmi(struct kvm_vcpu *vcpu); |
1f7becf1 | 114 | static void process_smi(struct kvm_vcpu *vcpu); |
ee2cd4b7 | 115 | static void enter_smm(struct kvm_vcpu *vcpu); |
6addfc42 | 116 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); |
01643c51 KH |
117 | static void store_regs(struct kvm_vcpu *vcpu); |
118 | static int sync_regs(struct kvm_vcpu *vcpu); | |
674eea0f | 119 | |
6dba9403 ML |
120 | static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); |
121 | static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); | |
122 | ||
afaf0b2f | 123 | struct kvm_x86_ops kvm_x86_ops __read_mostly; |
5fdbf976 | 124 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 125 | |
9af5471b JB |
126 | #define KVM_X86_OP(func) \ |
127 | DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \ | |
128 | *(((struct kvm_x86_ops *)0)->func)); | |
129 | #define KVM_X86_OP_NULL KVM_X86_OP | |
130 | #include <asm/kvm-x86-ops.h> | |
131 | EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits); | |
132 | EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg); | |
133 | EXPORT_STATIC_CALL_GPL(kvm_x86_tlb_flush_current); | |
134 | ||
893590c7 | 135 | static bool __read_mostly ignore_msrs = 0; |
476bc001 | 136 | module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); |
ed85c068 | 137 | |
d855066f | 138 | bool __read_mostly report_ignored_msrs = true; |
fab0aa3b | 139 | module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); |
d855066f | 140 | EXPORT_SYMBOL_GPL(report_ignored_msrs); |
fab0aa3b | 141 | |
4c27625b | 142 | unsigned int min_timer_period_us = 200; |
9ed96e87 MT |
143 | module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); |
144 | ||
630994b3 MT |
145 | static bool __read_mostly kvmclock_periodic_sync = true; |
146 | module_param(kvmclock_periodic_sync, bool, S_IRUGO); | |
147 | ||
893590c7 | 148 | bool __read_mostly kvm_has_tsc_control; |
92a1f12d | 149 | EXPORT_SYMBOL_GPL(kvm_has_tsc_control); |
893590c7 | 150 | u32 __read_mostly kvm_max_guest_tsc_khz; |
92a1f12d | 151 | EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); |
bc9b961b HZ |
152 | u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; |
153 | EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); | |
154 | u64 __read_mostly kvm_max_tsc_scaling_ratio; | |
155 | EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); | |
64672c95 YJ |
156 | u64 __read_mostly kvm_default_tsc_scaling_ratio; |
157 | EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); | |
fe6b6bc8 CQ |
158 | bool __read_mostly kvm_has_bus_lock_exit; |
159 | EXPORT_SYMBOL_GPL(kvm_has_bus_lock_exit); | |
92a1f12d | 160 | |
cc578287 | 161 | /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ |
893590c7 | 162 | static u32 __read_mostly tsc_tolerance_ppm = 250; |
cc578287 ZA |
163 | module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); |
164 | ||
c3941d9e SC |
165 | /* |
166 | * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables | |
d9f6e12f | 167 | * adaptive tuning starting from default advancement of 1000ns. '0' disables |
c3941d9e | 168 | * advancement entirely. Any other value is used as-is and disables adaptive |
d9f6e12f | 169 | * tuning, i.e. allows privileged userspace to set an exact advancement time. |
c3941d9e SC |
170 | */ |
171 | static int __read_mostly lapic_timer_advance_ns = -1; | |
0e6edceb | 172 | module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR); |
d0659d94 | 173 | |
52004014 FW |
174 | static bool __read_mostly vector_hashing = true; |
175 | module_param(vector_hashing, bool, S_IRUGO); | |
176 | ||
c4ae60e4 LA |
177 | bool __read_mostly enable_vmware_backdoor = false; |
178 | module_param(enable_vmware_backdoor, bool, S_IRUGO); | |
179 | EXPORT_SYMBOL_GPL(enable_vmware_backdoor); | |
180 | ||
6c86eedc WL |
181 | static bool __read_mostly force_emulation_prefix = false; |
182 | module_param(force_emulation_prefix, bool, S_IRUGO); | |
183 | ||
0c5f81da WL |
184 | int __read_mostly pi_inject_timer = -1; |
185 | module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); | |
186 | ||
7e34fbd0 SC |
187 | /* |
188 | * Restoring the host value for MSRs that are only consumed when running in | |
189 | * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU | |
190 | * returns to userspace, i.e. the kernel can run with the guest's value. | |
191 | */ | |
192 | #define KVM_MAX_NR_USER_RETURN_MSRS 16 | |
18863bdd | 193 | |
7e34fbd0 | 194 | struct kvm_user_return_msrs { |
18863bdd AK |
195 | struct user_return_notifier urn; |
196 | bool registered; | |
7e34fbd0 | 197 | struct kvm_user_return_msr_values { |
2bf78fa7 SY |
198 | u64 host; |
199 | u64 curr; | |
7e34fbd0 | 200 | } values[KVM_MAX_NR_USER_RETURN_MSRS]; |
18863bdd AK |
201 | }; |
202 | ||
9cc39a5a SC |
203 | u32 __read_mostly kvm_nr_uret_msrs; |
204 | EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs); | |
205 | static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS]; | |
7e34fbd0 | 206 | static struct kvm_user_return_msrs __percpu *user_return_msrs; |
18863bdd | 207 | |
cfc48181 SC |
208 | #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ |
209 | | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ | |
210 | | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ | |
211 | | XFEATURE_MASK_PKRU) | |
212 | ||
91661989 SC |
213 | u64 __read_mostly host_efer; |
214 | EXPORT_SYMBOL_GPL(host_efer); | |
215 | ||
b96e6506 | 216 | bool __read_mostly allow_smaller_maxphyaddr = 0; |
3edd6839 MG |
217 | EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr); |
218 | ||
fdf513e3 VK |
219 | bool __read_mostly enable_apicv = true; |
220 | EXPORT_SYMBOL_GPL(enable_apicv); | |
221 | ||
86137773 TL |
222 | u64 __read_mostly host_xss; |
223 | EXPORT_SYMBOL_GPL(host_xss); | |
408e9a31 PB |
224 | u64 __read_mostly supported_xss; |
225 | EXPORT_SYMBOL_GPL(supported_xss); | |
139a12cf | 226 | |
fcfe1bae JZ |
227 | const struct _kvm_stats_desc kvm_vm_stats_desc[] = { |
228 | KVM_GENERIC_VM_STATS(), | |
229 | STATS_DESC_COUNTER(VM, mmu_shadow_zapped), | |
230 | STATS_DESC_COUNTER(VM, mmu_pte_write), | |
231 | STATS_DESC_COUNTER(VM, mmu_pde_zapped), | |
232 | STATS_DESC_COUNTER(VM, mmu_flooded), | |
233 | STATS_DESC_COUNTER(VM, mmu_recycled), | |
234 | STATS_DESC_COUNTER(VM, mmu_cache_miss), | |
235 | STATS_DESC_ICOUNTER(VM, mmu_unsync), | |
236 | STATS_DESC_ICOUNTER(VM, lpages), | |
237 | STATS_DESC_ICOUNTER(VM, nx_lpage_splits), | |
bc9e9e67 | 238 | STATS_DESC_PCOUNTER(VM, max_mmu_page_hash_collisions) |
fcfe1bae JZ |
239 | }; |
240 | static_assert(ARRAY_SIZE(kvm_vm_stats_desc) == | |
241 | sizeof(struct kvm_vm_stat) / sizeof(u64)); | |
242 | ||
243 | const struct kvm_stats_header kvm_vm_stats_header = { | |
244 | .name_size = KVM_STATS_NAME_SIZE, | |
245 | .num_desc = ARRAY_SIZE(kvm_vm_stats_desc), | |
246 | .id_offset = sizeof(struct kvm_stats_header), | |
247 | .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, | |
248 | .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + | |
249 | sizeof(kvm_vm_stats_desc), | |
250 | }; | |
251 | ||
ce55c049 JZ |
252 | const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = { |
253 | KVM_GENERIC_VCPU_STATS(), | |
254 | STATS_DESC_COUNTER(VCPU, pf_fixed), | |
255 | STATS_DESC_COUNTER(VCPU, pf_guest), | |
256 | STATS_DESC_COUNTER(VCPU, tlb_flush), | |
257 | STATS_DESC_COUNTER(VCPU, invlpg), | |
258 | STATS_DESC_COUNTER(VCPU, exits), | |
259 | STATS_DESC_COUNTER(VCPU, io_exits), | |
260 | STATS_DESC_COUNTER(VCPU, mmio_exits), | |
261 | STATS_DESC_COUNTER(VCPU, signal_exits), | |
262 | STATS_DESC_COUNTER(VCPU, irq_window_exits), | |
263 | STATS_DESC_COUNTER(VCPU, nmi_window_exits), | |
264 | STATS_DESC_COUNTER(VCPU, l1d_flush), | |
265 | STATS_DESC_COUNTER(VCPU, halt_exits), | |
266 | STATS_DESC_COUNTER(VCPU, request_irq_exits), | |
267 | STATS_DESC_COUNTER(VCPU, irq_exits), | |
268 | STATS_DESC_COUNTER(VCPU, host_state_reload), | |
269 | STATS_DESC_COUNTER(VCPU, fpu_reload), | |
270 | STATS_DESC_COUNTER(VCPU, insn_emulation), | |
271 | STATS_DESC_COUNTER(VCPU, insn_emulation_fail), | |
272 | STATS_DESC_COUNTER(VCPU, hypercalls), | |
273 | STATS_DESC_COUNTER(VCPU, irq_injections), | |
274 | STATS_DESC_COUNTER(VCPU, nmi_injections), | |
275 | STATS_DESC_COUNTER(VCPU, req_event), | |
276 | STATS_DESC_COUNTER(VCPU, nested_run), | |
277 | STATS_DESC_COUNTER(VCPU, directed_yield_attempted), | |
278 | STATS_DESC_COUNTER(VCPU, directed_yield_successful), | |
279 | STATS_DESC_ICOUNTER(VCPU, guest_mode) | |
280 | }; | |
281 | static_assert(ARRAY_SIZE(kvm_vcpu_stats_desc) == | |
282 | sizeof(struct kvm_vcpu_stat) / sizeof(u64)); | |
283 | ||
284 | const struct kvm_stats_header kvm_vcpu_stats_header = { | |
285 | .name_size = KVM_STATS_NAME_SIZE, | |
286 | .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc), | |
287 | .id_offset = sizeof(struct kvm_stats_header), | |
288 | .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, | |
289 | .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + | |
290 | sizeof(kvm_vcpu_stats_desc), | |
291 | }; | |
292 | ||
2acf923e | 293 | u64 __read_mostly host_xcr0; |
cfc48181 SC |
294 | u64 __read_mostly supported_xcr0; |
295 | EXPORT_SYMBOL_GPL(supported_xcr0); | |
2acf923e | 296 | |
80fbd280 | 297 | static struct kmem_cache *x86_fpu_cache; |
b666a4b6 | 298 | |
c9b8b07c SC |
299 | static struct kmem_cache *x86_emulator_cache; |
300 | ||
6abe9c13 PX |
301 | /* |
302 | * When called, it means the previous get/set msr reached an invalid msr. | |
cc4cb017 | 303 | * Return true if we want to ignore/silent this failed msr access. |
6abe9c13 | 304 | */ |
d632826f | 305 | static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write) |
6abe9c13 PX |
306 | { |
307 | const char *op = write ? "wrmsr" : "rdmsr"; | |
308 | ||
309 | if (ignore_msrs) { | |
310 | if (report_ignored_msrs) | |
d383b314 TI |
311 | kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n", |
312 | op, msr, data); | |
6abe9c13 | 313 | /* Mask the error */ |
cc4cb017 | 314 | return true; |
6abe9c13 | 315 | } else { |
d383b314 TI |
316 | kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n", |
317 | op, msr, data); | |
cc4cb017 | 318 | return false; |
6abe9c13 PX |
319 | } |
320 | } | |
321 | ||
c9b8b07c SC |
322 | static struct kmem_cache *kvm_alloc_emulator_cache(void) |
323 | { | |
06add254 SC |
324 | unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src); |
325 | unsigned int size = sizeof(struct x86_emulate_ctxt); | |
326 | ||
327 | return kmem_cache_create_usercopy("x86_emulator", size, | |
c9b8b07c | 328 | __alignof__(struct x86_emulate_ctxt), |
06add254 SC |
329 | SLAB_ACCOUNT, useroffset, |
330 | size - useroffset, NULL); | |
c9b8b07c SC |
331 | } |
332 | ||
b6785def | 333 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); |
d6aa1000 | 334 | |
af585b92 GN |
335 | static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) |
336 | { | |
337 | int i; | |
dd03bcaa | 338 | for (i = 0; i < ASYNC_PF_PER_VCPU; i++) |
af585b92 GN |
339 | vcpu->arch.apf.gfns[i] = ~0; |
340 | } | |
341 | ||
18863bdd AK |
342 | static void kvm_on_user_return(struct user_return_notifier *urn) |
343 | { | |
344 | unsigned slot; | |
7e34fbd0 SC |
345 | struct kvm_user_return_msrs *msrs |
346 | = container_of(urn, struct kvm_user_return_msrs, urn); | |
347 | struct kvm_user_return_msr_values *values; | |
1650b4eb IA |
348 | unsigned long flags; |
349 | ||
350 | /* | |
351 | * Disabling irqs at this point since the following code could be | |
352 | * interrupted and executed through kvm_arch_hardware_disable() | |
353 | */ | |
354 | local_irq_save(flags); | |
7e34fbd0 SC |
355 | if (msrs->registered) { |
356 | msrs->registered = false; | |
1650b4eb IA |
357 | user_return_notifier_unregister(urn); |
358 | } | |
359 | local_irq_restore(flags); | |
9cc39a5a | 360 | for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) { |
7e34fbd0 | 361 | values = &msrs->values[slot]; |
2bf78fa7 | 362 | if (values->host != values->curr) { |
9cc39a5a | 363 | wrmsrl(kvm_uret_msrs_list[slot], values->host); |
2bf78fa7 | 364 | values->curr = values->host; |
18863bdd AK |
365 | } |
366 | } | |
18863bdd AK |
367 | } |
368 | ||
e5fda4bb | 369 | static int kvm_probe_user_return_msr(u32 msr) |
5104d7ff SC |
370 | { |
371 | u64 val; | |
372 | int ret; | |
373 | ||
374 | preempt_disable(); | |
375 | ret = rdmsrl_safe(msr, &val); | |
376 | if (ret) | |
377 | goto out; | |
378 | ret = wrmsrl_safe(msr, val); | |
379 | out: | |
380 | preempt_enable(); | |
381 | return ret; | |
382 | } | |
5104d7ff | 383 | |
e5fda4bb | 384 | int kvm_add_user_return_msr(u32 msr) |
2bf78fa7 | 385 | { |
e5fda4bb SC |
386 | BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS); |
387 | ||
388 | if (kvm_probe_user_return_msr(msr)) | |
389 | return -1; | |
390 | ||
391 | kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr; | |
392 | return kvm_nr_uret_msrs++; | |
18863bdd | 393 | } |
e5fda4bb | 394 | EXPORT_SYMBOL_GPL(kvm_add_user_return_msr); |
18863bdd | 395 | |
8ea8b8d6 SC |
396 | int kvm_find_user_return_msr(u32 msr) |
397 | { | |
398 | int i; | |
399 | ||
9cc39a5a SC |
400 | for (i = 0; i < kvm_nr_uret_msrs; ++i) { |
401 | if (kvm_uret_msrs_list[i] == msr) | |
8ea8b8d6 SC |
402 | return i; |
403 | } | |
404 | return -1; | |
405 | } | |
406 | EXPORT_SYMBOL_GPL(kvm_find_user_return_msr); | |
407 | ||
7e34fbd0 | 408 | static void kvm_user_return_msr_cpu_online(void) |
18863bdd | 409 | { |
05c19c2f | 410 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 411 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
05c19c2f SC |
412 | u64 value; |
413 | int i; | |
18863bdd | 414 | |
9cc39a5a SC |
415 | for (i = 0; i < kvm_nr_uret_msrs; ++i) { |
416 | rdmsrl_safe(kvm_uret_msrs_list[i], &value); | |
7e34fbd0 SC |
417 | msrs->values[i].host = value; |
418 | msrs->values[i].curr = value; | |
05c19c2f | 419 | } |
18863bdd AK |
420 | } |
421 | ||
7e34fbd0 | 422 | int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask) |
18863bdd | 423 | { |
013f6a5d | 424 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 425 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
8b3c3104 | 426 | int err; |
18863bdd | 427 | |
7e34fbd0 SC |
428 | value = (value & mask) | (msrs->values[slot].host & ~mask); |
429 | if (value == msrs->values[slot].curr) | |
8b3c3104 | 430 | return 0; |
9cc39a5a | 431 | err = wrmsrl_safe(kvm_uret_msrs_list[slot], value); |
8b3c3104 AH |
432 | if (err) |
433 | return 1; | |
434 | ||
7e34fbd0 SC |
435 | msrs->values[slot].curr = value; |
436 | if (!msrs->registered) { | |
437 | msrs->urn.on_user_return = kvm_on_user_return; | |
438 | user_return_notifier_register(&msrs->urn); | |
439 | msrs->registered = true; | |
18863bdd | 440 | } |
8b3c3104 | 441 | return 0; |
18863bdd | 442 | } |
7e34fbd0 | 443 | EXPORT_SYMBOL_GPL(kvm_set_user_return_msr); |
18863bdd | 444 | |
13a34e06 | 445 | static void drop_user_return_notifiers(void) |
3548bab5 | 446 | { |
013f6a5d | 447 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 448 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
3548bab5 | 449 | |
7e34fbd0 SC |
450 | if (msrs->registered) |
451 | kvm_on_user_return(&msrs->urn); | |
3548bab5 AK |
452 | } |
453 | ||
6866b83e CO |
454 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
455 | { | |
8a5a87d9 | 456 | return vcpu->arch.apic_base; |
6866b83e CO |
457 | } |
458 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
459 | ||
58871649 JM |
460 | enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) |
461 | { | |
462 | return kvm_apic_mode(kvm_get_apic_base(vcpu)); | |
463 | } | |
464 | EXPORT_SYMBOL_GPL(kvm_get_apic_mode); | |
465 | ||
58cb628d JK |
466 | int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
467 | { | |
58871649 JM |
468 | enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); |
469 | enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); | |
a8ac864a | 470 | u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff | |
d6321d49 | 471 | (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); |
58cb628d | 472 | |
58871649 | 473 | if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) |
58cb628d | 474 | return 1; |
58871649 JM |
475 | if (!msr_info->host_initiated) { |
476 | if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) | |
477 | return 1; | |
478 | if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) | |
479 | return 1; | |
480 | } | |
58cb628d JK |
481 | |
482 | kvm_lapic_set_base(vcpu, msr_info->data); | |
4abaffce | 483 | kvm_recalculate_apic_map(vcpu->kvm); |
58cb628d | 484 | return 0; |
6866b83e CO |
485 | } |
486 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
487 | ||
3ebccdf3 | 488 | asmlinkage __visible noinstr void kvm_spurious_fault(void) |
e3ba45b8 GL |
489 | { |
490 | /* Fault while not rebooting. We want the trace. */ | |
b4fdcf60 | 491 | BUG_ON(!kvm_rebooting); |
e3ba45b8 GL |
492 | } |
493 | EXPORT_SYMBOL_GPL(kvm_spurious_fault); | |
494 | ||
3fd28fce ED |
495 | #define EXCPT_BENIGN 0 |
496 | #define EXCPT_CONTRIBUTORY 1 | |
497 | #define EXCPT_PF 2 | |
498 | ||
499 | static int exception_class(int vector) | |
500 | { | |
501 | switch (vector) { | |
502 | case PF_VECTOR: | |
503 | return EXCPT_PF; | |
504 | case DE_VECTOR: | |
505 | case TS_VECTOR: | |
506 | case NP_VECTOR: | |
507 | case SS_VECTOR: | |
508 | case GP_VECTOR: | |
509 | return EXCPT_CONTRIBUTORY; | |
510 | default: | |
511 | break; | |
512 | } | |
513 | return EXCPT_BENIGN; | |
514 | } | |
515 | ||
d6e8c854 NA |
516 | #define EXCPT_FAULT 0 |
517 | #define EXCPT_TRAP 1 | |
518 | #define EXCPT_ABORT 2 | |
519 | #define EXCPT_INTERRUPT 3 | |
520 | ||
521 | static int exception_type(int vector) | |
522 | { | |
523 | unsigned int mask; | |
524 | ||
525 | if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) | |
526 | return EXCPT_INTERRUPT; | |
527 | ||
528 | mask = 1 << vector; | |
529 | ||
530 | /* #DB is trap, as instruction watchpoints are handled elsewhere */ | |
531 | if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) | |
532 | return EXCPT_TRAP; | |
533 | ||
534 | if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) | |
535 | return EXCPT_ABORT; | |
536 | ||
537 | /* Reserved exceptions will result in fault */ | |
538 | return EXCPT_FAULT; | |
539 | } | |
540 | ||
da998b46 JM |
541 | void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) |
542 | { | |
543 | unsigned nr = vcpu->arch.exception.nr; | |
544 | bool has_payload = vcpu->arch.exception.has_payload; | |
545 | unsigned long payload = vcpu->arch.exception.payload; | |
546 | ||
547 | if (!has_payload) | |
548 | return; | |
549 | ||
550 | switch (nr) { | |
f10c729f JM |
551 | case DB_VECTOR: |
552 | /* | |
553 | * "Certain debug exceptions may clear bit 0-3. The | |
554 | * remaining contents of the DR6 register are never | |
555 | * cleared by the processor". | |
556 | */ | |
557 | vcpu->arch.dr6 &= ~DR_TRAP_BITS; | |
558 | /* | |
9a3ecd5e CQ |
559 | * In order to reflect the #DB exception payload in guest |
560 | * dr6, three components need to be considered: active low | |
561 | * bit, FIXED_1 bits and active high bits (e.g. DR6_BD, | |
562 | * DR6_BS and DR6_BT) | |
563 | * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits. | |
564 | * In the target guest dr6: | |
565 | * FIXED_1 bits should always be set. | |
566 | * Active low bits should be cleared if 1-setting in payload. | |
567 | * Active high bits should be set if 1-setting in payload. | |
568 | * | |
569 | * Note, the payload is compatible with the pending debug | |
570 | * exceptions/exit qualification under VMX, that active_low bits | |
571 | * are active high in payload. | |
572 | * So they need to be flipped for DR6. | |
f10c729f | 573 | */ |
9a3ecd5e | 574 | vcpu->arch.dr6 |= DR6_ACTIVE_LOW; |
f10c729f | 575 | vcpu->arch.dr6 |= payload; |
9a3ecd5e | 576 | vcpu->arch.dr6 ^= payload & DR6_ACTIVE_LOW; |
307f1cfa OU |
577 | |
578 | /* | |
579 | * The #DB payload is defined as compatible with the 'pending | |
580 | * debug exceptions' field under VMX, not DR6. While bit 12 is | |
581 | * defined in the 'pending debug exceptions' field (enabled | |
582 | * breakpoint), it is reserved and must be zero in DR6. | |
583 | */ | |
584 | vcpu->arch.dr6 &= ~BIT(12); | |
f10c729f | 585 | break; |
da998b46 JM |
586 | case PF_VECTOR: |
587 | vcpu->arch.cr2 = payload; | |
588 | break; | |
589 | } | |
590 | ||
591 | vcpu->arch.exception.has_payload = false; | |
592 | vcpu->arch.exception.payload = 0; | |
593 | } | |
594 | EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); | |
595 | ||
3fd28fce | 596 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, |
ce7ddec4 | 597 | unsigned nr, bool has_error, u32 error_code, |
91e86d22 | 598 | bool has_payload, unsigned long payload, bool reinject) |
3fd28fce ED |
599 | { |
600 | u32 prev_nr; | |
601 | int class1, class2; | |
602 | ||
3842d135 AK |
603 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
604 | ||
664f8e26 | 605 | if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { |
3fd28fce | 606 | queue: |
664f8e26 WL |
607 | if (reinject) { |
608 | /* | |
609 | * On vmentry, vcpu->arch.exception.pending is only | |
610 | * true if an event injection was blocked by | |
611 | * nested_run_pending. In that case, however, | |
612 | * vcpu_enter_guest requests an immediate exit, | |
613 | * and the guest shouldn't proceed far enough to | |
614 | * need reinjection. | |
615 | */ | |
616 | WARN_ON_ONCE(vcpu->arch.exception.pending); | |
617 | vcpu->arch.exception.injected = true; | |
91e86d22 JM |
618 | if (WARN_ON_ONCE(has_payload)) { |
619 | /* | |
620 | * A reinjected event has already | |
621 | * delivered its payload. | |
622 | */ | |
623 | has_payload = false; | |
624 | payload = 0; | |
625 | } | |
664f8e26 WL |
626 | } else { |
627 | vcpu->arch.exception.pending = true; | |
628 | vcpu->arch.exception.injected = false; | |
629 | } | |
3fd28fce ED |
630 | vcpu->arch.exception.has_error_code = has_error; |
631 | vcpu->arch.exception.nr = nr; | |
632 | vcpu->arch.exception.error_code = error_code; | |
91e86d22 JM |
633 | vcpu->arch.exception.has_payload = has_payload; |
634 | vcpu->arch.exception.payload = payload; | |
a06230b6 | 635 | if (!is_guest_mode(vcpu)) |
da998b46 | 636 | kvm_deliver_exception_payload(vcpu); |
3fd28fce ED |
637 | return; |
638 | } | |
639 | ||
640 | /* to check exception */ | |
641 | prev_nr = vcpu->arch.exception.nr; | |
642 | if (prev_nr == DF_VECTOR) { | |
643 | /* triple fault -> shutdown */ | |
a8eeb04a | 644 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
3fd28fce ED |
645 | return; |
646 | } | |
647 | class1 = exception_class(prev_nr); | |
648 | class2 = exception_class(nr); | |
649 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) | |
650 | || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
664f8e26 WL |
651 | /* |
652 | * Generate double fault per SDM Table 5-5. Set | |
653 | * exception.pending = true so that the double fault | |
654 | * can trigger a nested vmexit. | |
655 | */ | |
3fd28fce | 656 | vcpu->arch.exception.pending = true; |
664f8e26 | 657 | vcpu->arch.exception.injected = false; |
3fd28fce ED |
658 | vcpu->arch.exception.has_error_code = true; |
659 | vcpu->arch.exception.nr = DF_VECTOR; | |
660 | vcpu->arch.exception.error_code = 0; | |
c851436a JM |
661 | vcpu->arch.exception.has_payload = false; |
662 | vcpu->arch.exception.payload = 0; | |
3fd28fce ED |
663 | } else |
664 | /* replace previous exception with a new one in a hope | |
665 | that instruction re-execution will regenerate lost | |
666 | exception */ | |
667 | goto queue; | |
668 | } | |
669 | ||
298101da AK |
670 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
671 | { | |
91e86d22 | 672 | kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); |
298101da AK |
673 | } |
674 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
675 | ||
ce7ddec4 JR |
676 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
677 | { | |
91e86d22 | 678 | kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); |
ce7ddec4 JR |
679 | } |
680 | EXPORT_SYMBOL_GPL(kvm_requeue_exception); | |
681 | ||
4d5523cf PB |
682 | void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, |
683 | unsigned long payload) | |
f10c729f JM |
684 | { |
685 | kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); | |
686 | } | |
4d5523cf | 687 | EXPORT_SYMBOL_GPL(kvm_queue_exception_p); |
f10c729f | 688 | |
da998b46 JM |
689 | static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, |
690 | u32 error_code, unsigned long payload) | |
691 | { | |
692 | kvm_multiple_exception(vcpu, nr, true, error_code, | |
693 | true, payload, false); | |
694 | } | |
695 | ||
6affcbed | 696 | int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) |
c3c91fee | 697 | { |
db8fcefa AP |
698 | if (err) |
699 | kvm_inject_gp(vcpu, 0); | |
700 | else | |
6affcbed KH |
701 | return kvm_skip_emulated_instruction(vcpu); |
702 | ||
703 | return 1; | |
db8fcefa AP |
704 | } |
705 | EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); | |
8df25a32 | 706 | |
6389ee94 | 707 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
c3c91fee AK |
708 | { |
709 | ++vcpu->stat.pf_guest; | |
adfe20fb WL |
710 | vcpu->arch.exception.nested_apf = |
711 | is_guest_mode(vcpu) && fault->async_page_fault; | |
da998b46 | 712 | if (vcpu->arch.exception.nested_apf) { |
adfe20fb | 713 | vcpu->arch.apf.nested_apf_token = fault->address; |
da998b46 JM |
714 | kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); |
715 | } else { | |
716 | kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, | |
717 | fault->address); | |
718 | } | |
c3c91fee | 719 | } |
27d6c865 | 720 | EXPORT_SYMBOL_GPL(kvm_inject_page_fault); |
c3c91fee | 721 | |
53b3d8e9 SC |
722 | bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, |
723 | struct x86_exception *fault) | |
d4f8cf66 | 724 | { |
0cd665bd | 725 | struct kvm_mmu *fault_mmu; |
53b3d8e9 SC |
726 | WARN_ON_ONCE(fault->vector != PF_VECTOR); |
727 | ||
0cd665bd PB |
728 | fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu : |
729 | vcpu->arch.walk_mmu; | |
ef54bcfe | 730 | |
ee1fa209 JS |
731 | /* |
732 | * Invalidate the TLB entry for the faulting address, if it exists, | |
733 | * else the access will fault indefinitely (and to emulate hardware). | |
734 | */ | |
735 | if ((fault->error_code & PFERR_PRESENT_MASK) && | |
736 | !(fault->error_code & PFERR_RSVD_MASK)) | |
737 | kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address, | |
738 | fault_mmu->root_hpa); | |
739 | ||
740 | fault_mmu->inject_page_fault(vcpu, fault); | |
ef54bcfe | 741 | return fault->nested_page_fault; |
d4f8cf66 | 742 | } |
53b3d8e9 | 743 | EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault); |
d4f8cf66 | 744 | |
3419ffc8 SY |
745 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
746 | { | |
7460fb4a AK |
747 | atomic_inc(&vcpu->arch.nmi_queued); |
748 | kvm_make_request(KVM_REQ_NMI, vcpu); | |
3419ffc8 SY |
749 | } |
750 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
751 | ||
298101da AK |
752 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
753 | { | |
91e86d22 | 754 | kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); |
298101da AK |
755 | } |
756 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
757 | ||
ce7ddec4 JR |
758 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
759 | { | |
91e86d22 | 760 | kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); |
ce7ddec4 JR |
761 | } |
762 | EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); | |
763 | ||
0a79b009 AK |
764 | /* |
765 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
766 | * a #GP and return false. | |
767 | */ | |
768 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 769 | { |
b3646477 | 770 | if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl) |
0a79b009 AK |
771 | return true; |
772 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
773 | return false; | |
298101da | 774 | } |
0a79b009 | 775 | EXPORT_SYMBOL_GPL(kvm_require_cpl); |
298101da | 776 | |
16f8a6f9 NA |
777 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) |
778 | { | |
779 | if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
780 | return true; | |
781 | ||
782 | kvm_queue_exception(vcpu, UD_VECTOR); | |
783 | return false; | |
784 | } | |
785 | EXPORT_SYMBOL_GPL(kvm_require_dr); | |
786 | ||
ec92fe44 JR |
787 | /* |
788 | * This function will be used to read from the physical memory of the currently | |
54bf36aa | 789 | * running guest. The difference to kvm_vcpu_read_guest_page is that this function |
ec92fe44 JR |
790 | * can read from guest physical or from the guest's guest physical memory. |
791 | */ | |
792 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
793 | gfn_t ngfn, void *data, int offset, int len, | |
794 | u32 access) | |
795 | { | |
54987b7a | 796 | struct x86_exception exception; |
ec92fe44 JR |
797 | gfn_t real_gfn; |
798 | gpa_t ngpa; | |
799 | ||
800 | ngpa = gfn_to_gpa(ngfn); | |
54987b7a | 801 | real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); |
ec92fe44 JR |
802 | if (real_gfn == UNMAPPED_GVA) |
803 | return -EFAULT; | |
804 | ||
805 | real_gfn = gpa_to_gfn(real_gfn); | |
806 | ||
54bf36aa | 807 | return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); |
ec92fe44 JR |
808 | } |
809 | EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); | |
810 | ||
16cfacc8 SC |
811 | static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) |
812 | { | |
5b7f575c | 813 | return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2); |
16cfacc8 SC |
814 | } |
815 | ||
a03490ed | 816 | /* |
16cfacc8 | 817 | * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. |
a03490ed | 818 | */ |
ff03a073 | 819 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) |
a03490ed CO |
820 | { |
821 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
822 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
823 | int i; | |
824 | int ret; | |
ff03a073 | 825 | u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; |
a03490ed | 826 | |
ff03a073 JR |
827 | ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, |
828 | offset * sizeof(u64), sizeof(pdpte), | |
829 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
a03490ed CO |
830 | if (ret < 0) { |
831 | ret = 0; | |
832 | goto out; | |
833 | } | |
834 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
812f30b2 | 835 | if ((pdpte[i] & PT_PRESENT_MASK) && |
16cfacc8 | 836 | (pdpte[i] & pdptr_rsvd_bits(vcpu))) { |
a03490ed CO |
837 | ret = 0; |
838 | goto out; | |
839 | } | |
840 | } | |
841 | ret = 1; | |
842 | ||
ff03a073 | 843 | memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); |
cb3c1e2f | 844 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); |
158a48ec ML |
845 | vcpu->arch.pdptrs_from_userspace = false; |
846 | ||
a03490ed | 847 | out: |
a03490ed CO |
848 | |
849 | return ret; | |
850 | } | |
cc4b6871 | 851 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 852 | |
f27ad38a TL |
853 | void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0) |
854 | { | |
f27ad38a TL |
855 | if ((cr0 ^ old_cr0) & X86_CR0_PG) { |
856 | kvm_clear_async_pf_completion_queue(vcpu); | |
857 | kvm_async_pf_hash_reset(vcpu); | |
858 | } | |
859 | ||
20f632bd | 860 | if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS) |
f27ad38a TL |
861 | kvm_mmu_reset_context(vcpu); |
862 | ||
863 | if (((cr0 ^ old_cr0) & X86_CR0_CD) && | |
864 | kvm_arch_has_noncoherent_dma(vcpu->kvm) && | |
865 | !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) | |
866 | kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); | |
867 | } | |
868 | EXPORT_SYMBOL_GPL(kvm_post_set_cr0); | |
869 | ||
49a9b07e | 870 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 871 | { |
aad82703 | 872 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
d42e3fae | 873 | unsigned long pdptr_bits = X86_CR0_CD | X86_CR0_NW | X86_CR0_PG; |
aad82703 | 874 | |
f9a48e6a AK |
875 | cr0 |= X86_CR0_ET; |
876 | ||
ab344828 | 877 | #ifdef CONFIG_X86_64 |
0f12244f GN |
878 | if (cr0 & 0xffffffff00000000UL) |
879 | return 1; | |
ab344828 GN |
880 | #endif |
881 | ||
882 | cr0 &= ~CR0_RESERVED_BITS; | |
a03490ed | 883 | |
0f12244f GN |
884 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) |
885 | return 1; | |
a03490ed | 886 | |
0f12244f GN |
887 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) |
888 | return 1; | |
a03490ed | 889 | |
a03490ed | 890 | #ifdef CONFIG_X86_64 |
05487215 SC |
891 | if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) && |
892 | (cr0 & X86_CR0_PG)) { | |
893 | int cs_db, cs_l; | |
894 | ||
895 | if (!is_pae(vcpu)) | |
896 | return 1; | |
b3646477 | 897 | static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); |
05487215 | 898 | if (cs_l) |
0f12244f | 899 | return 1; |
a03490ed | 900 | } |
05487215 SC |
901 | #endif |
902 | if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) && | |
903 | is_pae(vcpu) && ((cr0 ^ old_cr0) & pdptr_bits) && | |
904 | !load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu))) | |
905 | return 1; | |
a03490ed | 906 | |
ad756a16 MJ |
907 | if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) |
908 | return 1; | |
909 | ||
b3646477 | 910 | static_call(kvm_x86_set_cr0)(vcpu, cr0); |
a03490ed | 911 | |
f27ad38a | 912 | kvm_post_set_cr0(vcpu, old_cr0, cr0); |
b18d5431 | 913 | |
0f12244f GN |
914 | return 0; |
915 | } | |
2d3ad1f4 | 916 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 917 | |
2d3ad1f4 | 918 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 919 | { |
49a9b07e | 920 | (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); |
a03490ed | 921 | } |
2d3ad1f4 | 922 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 923 | |
139a12cf | 924 | void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) |
42bdf991 | 925 | { |
16809ecd TL |
926 | if (vcpu->arch.guest_state_protected) |
927 | return; | |
928 | ||
139a12cf AL |
929 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { |
930 | ||
931 | if (vcpu->arch.xcr0 != host_xcr0) | |
932 | xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); | |
933 | ||
934 | if (vcpu->arch.xsaves_enabled && | |
935 | vcpu->arch.ia32_xss != host_xss) | |
936 | wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); | |
937 | } | |
37486135 BM |
938 | |
939 | if (static_cpu_has(X86_FEATURE_PKU) && | |
940 | (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || | |
941 | (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) && | |
942 | vcpu->arch.pkru != vcpu->arch.host_pkru) | |
72a6c08c | 943 | write_pkru(vcpu->arch.pkru); |
42bdf991 | 944 | } |
139a12cf | 945 | EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state); |
42bdf991 | 946 | |
139a12cf | 947 | void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) |
42bdf991 | 948 | { |
16809ecd TL |
949 | if (vcpu->arch.guest_state_protected) |
950 | return; | |
951 | ||
37486135 BM |
952 | if (static_cpu_has(X86_FEATURE_PKU) && |
953 | (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || | |
954 | (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) { | |
955 | vcpu->arch.pkru = rdpkru(); | |
956 | if (vcpu->arch.pkru != vcpu->arch.host_pkru) | |
72a6c08c | 957 | write_pkru(vcpu->arch.host_pkru); |
37486135 BM |
958 | } |
959 | ||
139a12cf AL |
960 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { |
961 | ||
962 | if (vcpu->arch.xcr0 != host_xcr0) | |
963 | xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); | |
964 | ||
965 | if (vcpu->arch.xsaves_enabled && | |
966 | vcpu->arch.ia32_xss != host_xss) | |
967 | wrmsrl(MSR_IA32_XSS, host_xss); | |
968 | } | |
969 | ||
42bdf991 | 970 | } |
139a12cf | 971 | EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state); |
42bdf991 | 972 | |
69b0049a | 973 | static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) |
2acf923e | 974 | { |
56c103ec LJ |
975 | u64 xcr0 = xcr; |
976 | u64 old_xcr0 = vcpu->arch.xcr0; | |
46c34cb0 | 977 | u64 valid_bits; |
2acf923e DC |
978 | |
979 | /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ | |
980 | if (index != XCR_XFEATURE_ENABLED_MASK) | |
981 | return 1; | |
d91cab78 | 982 | if (!(xcr0 & XFEATURE_MASK_FP)) |
2acf923e | 983 | return 1; |
d91cab78 | 984 | if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) |
2acf923e | 985 | return 1; |
46c34cb0 PB |
986 | |
987 | /* | |
988 | * Do not allow the guest to set bits that we do not support | |
989 | * saving. However, xcr0 bit 0 is always set, even if the | |
990 | * emulated CPU does not support XSAVE (see fx_init). | |
991 | */ | |
d91cab78 | 992 | valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; |
46c34cb0 | 993 | if (xcr0 & ~valid_bits) |
2acf923e | 994 | return 1; |
46c34cb0 | 995 | |
d91cab78 DH |
996 | if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != |
997 | (!(xcr0 & XFEATURE_MASK_BNDCSR))) | |
390bd528 LJ |
998 | return 1; |
999 | ||
d91cab78 DH |
1000 | if (xcr0 & XFEATURE_MASK_AVX512) { |
1001 | if (!(xcr0 & XFEATURE_MASK_YMM)) | |
612263b3 | 1002 | return 1; |
d91cab78 | 1003 | if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) |
612263b3 CP |
1004 | return 1; |
1005 | } | |
2acf923e | 1006 | vcpu->arch.xcr0 = xcr0; |
56c103ec | 1007 | |
d91cab78 | 1008 | if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) |
aedbaf4f | 1009 | kvm_update_cpuid_runtime(vcpu); |
2acf923e DC |
1010 | return 0; |
1011 | } | |
1012 | ||
92f9895c | 1013 | int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu) |
2acf923e | 1014 | { |
92f9895c SC |
1015 | if (static_call(kvm_x86_get_cpl)(vcpu) != 0 || |
1016 | __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) { | |
1017 | kvm_inject_gp(vcpu, 0); | |
1018 | return 1; | |
1019 | } | |
bbefd4fc | 1020 | |
92f9895c | 1021 | return kvm_skip_emulated_instruction(vcpu); |
2acf923e | 1022 | } |
92f9895c | 1023 | EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv); |
2acf923e | 1024 | |
ee69c92b | 1025 | bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 1026 | { |
b11306b5 | 1027 | if (cr4 & cr4_reserved_bits) |
ee69c92b | 1028 | return false; |
b9baba86 | 1029 | |
b899c132 | 1030 | if (cr4 & vcpu->arch.cr4_guest_rsvd_bits) |
ee69c92b | 1031 | return false; |
3ca94192 | 1032 | |
b3646477 | 1033 | return static_call(kvm_x86_is_valid_cr4)(vcpu, cr4); |
3ca94192 | 1034 | } |
ee69c92b | 1035 | EXPORT_SYMBOL_GPL(kvm_is_valid_cr4); |
3ca94192 | 1036 | |
5b51cb13 TL |
1037 | void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4) |
1038 | { | |
20f632bd | 1039 | if (((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS) || |
5b51cb13 TL |
1040 | (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) |
1041 | kvm_mmu_reset_context(vcpu); | |
3ca94192 | 1042 | } |
5b51cb13 | 1043 | EXPORT_SYMBOL_GPL(kvm_post_set_cr4); |
3ca94192 WL |
1044 | |
1045 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1046 | { | |
1047 | unsigned long old_cr4 = kvm_read_cr4(vcpu); | |
1048 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | | |
cb957adb | 1049 | X86_CR4_SMEP; |
3ca94192 | 1050 | |
ee69c92b | 1051 | if (!kvm_is_valid_cr4(vcpu, cr4)) |
ae3e61e1 PB |
1052 | return 1; |
1053 | ||
a03490ed | 1054 | if (is_long_mode(vcpu)) { |
0f12244f GN |
1055 | if (!(cr4 & X86_CR4_PAE)) |
1056 | return 1; | |
d74fcfc1 SC |
1057 | if ((cr4 ^ old_cr4) & X86_CR4_LA57) |
1058 | return 1; | |
a2edf57f AK |
1059 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
1060 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
9f8fe504 AK |
1061 | && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
1062 | kvm_read_cr3(vcpu))) | |
0f12244f GN |
1063 | return 1; |
1064 | ||
ad756a16 | 1065 | if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { |
d6321d49 | 1066 | if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) |
ad756a16 MJ |
1067 | return 1; |
1068 | ||
1069 | /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ | |
1070 | if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) | |
1071 | return 1; | |
1072 | } | |
1073 | ||
b3646477 | 1074 | static_call(kvm_x86_set_cr4)(vcpu, cr4); |
a03490ed | 1075 | |
5b51cb13 | 1076 | kvm_post_set_cr4(vcpu, old_cr4, cr4); |
2acf923e | 1077 | |
0f12244f GN |
1078 | return 0; |
1079 | } | |
2d3ad1f4 | 1080 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 1081 | |
21823fbd SC |
1082 | static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid) |
1083 | { | |
1084 | struct kvm_mmu *mmu = vcpu->arch.mmu; | |
1085 | unsigned long roots_to_free = 0; | |
1086 | int i; | |
1087 | ||
1088 | /* | |
1089 | * If neither the current CR3 nor any of the prev_roots use the given | |
1090 | * PCID, then nothing needs to be done here because a resync will | |
1091 | * happen anyway before switching to any other CR3. | |
1092 | */ | |
1093 | if (kvm_get_active_pcid(vcpu) == pcid) { | |
e62f1aa8 | 1094 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
21823fbd SC |
1095 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
1096 | } | |
1097 | ||
1098 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
1099 | if (kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd) == pcid) | |
1100 | roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); | |
1101 | ||
1102 | kvm_mmu_free_roots(vcpu, mmu, roots_to_free); | |
1103 | } | |
1104 | ||
2390218b | 1105 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 1106 | { |
ade61e28 | 1107 | bool skip_tlb_flush = false; |
21823fbd | 1108 | unsigned long pcid = 0; |
ac146235 | 1109 | #ifdef CONFIG_X86_64 |
c19986fe JS |
1110 | bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); |
1111 | ||
ade61e28 | 1112 | if (pcid_enabled) { |
208320ba JS |
1113 | skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; |
1114 | cr3 &= ~X86_CR3_PCID_NOFLUSH; | |
21823fbd | 1115 | pcid = cr3 & X86_CR3_PCID_MASK; |
ade61e28 | 1116 | } |
ac146235 | 1117 | #endif |
9d88fca7 | 1118 | |
c7313155 | 1119 | /* PDPTRs are always reloaded for PAE paging. */ |
21823fbd SC |
1120 | if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu)) |
1121 | goto handle_tlb_flush; | |
d835dfec | 1122 | |
886bbcc7 SC |
1123 | /* |
1124 | * Do not condition the GPA check on long mode, this helper is used to | |
1125 | * stuff CR3, e.g. for RSM emulation, and there is no guarantee that | |
1126 | * the current vCPU mode is accurate. | |
1127 | */ | |
1128 | if (kvm_vcpu_is_illegal_gpa(vcpu, cr3)) | |
d1cd3ce9 | 1129 | return 1; |
886bbcc7 SC |
1130 | |
1131 | if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) | |
346874c9 | 1132 | return 1; |
a03490ed | 1133 | |
21823fbd | 1134 | if (cr3 != kvm_read_cr3(vcpu)) |
b5129100 | 1135 | kvm_mmu_new_pgd(vcpu, cr3); |
21823fbd | 1136 | |
0f12244f | 1137 | vcpu->arch.cr3 = cr3; |
cb3c1e2f | 1138 | kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); |
7c390d35 | 1139 | |
21823fbd SC |
1140 | handle_tlb_flush: |
1141 | /* | |
1142 | * A load of CR3 that flushes the TLB flushes only the current PCID, | |
1143 | * even if PCID is disabled, in which case PCID=0 is flushed. It's a | |
1144 | * moot point in the end because _disabling_ PCID will flush all PCIDs, | |
1145 | * and it's impossible to use a non-zero PCID when PCID is disabled, | |
1146 | * i.e. only PCID=0 can be relevant. | |
1147 | */ | |
1148 | if (!skip_tlb_flush) | |
1149 | kvm_invalidate_pcid(vcpu, pcid); | |
1150 | ||
0f12244f GN |
1151 | return 0; |
1152 | } | |
2d3ad1f4 | 1153 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 1154 | |
eea1cff9 | 1155 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed | 1156 | { |
0f12244f GN |
1157 | if (cr8 & CR8_RESERVED_BITS) |
1158 | return 1; | |
35754c98 | 1159 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
1160 | kvm_lapic_set_tpr(vcpu, cr8); |
1161 | else | |
ad312c7c | 1162 | vcpu->arch.cr8 = cr8; |
0f12244f GN |
1163 | return 0; |
1164 | } | |
2d3ad1f4 | 1165 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 1166 | |
2d3ad1f4 | 1167 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed | 1168 | { |
35754c98 | 1169 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
1170 | return kvm_lapic_get_cr8(vcpu); |
1171 | else | |
ad312c7c | 1172 | return vcpu->arch.cr8; |
a03490ed | 1173 | } |
2d3ad1f4 | 1174 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 1175 | |
ae561ede NA |
1176 | static void kvm_update_dr0123(struct kvm_vcpu *vcpu) |
1177 | { | |
1178 | int i; | |
1179 | ||
1180 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
1181 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
1182 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
1183 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; | |
1184 | } | |
1185 | } | |
1186 | ||
7c86663b | 1187 | void kvm_update_dr7(struct kvm_vcpu *vcpu) |
c8639010 JK |
1188 | { |
1189 | unsigned long dr7; | |
1190 | ||
1191 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
1192 | dr7 = vcpu->arch.guest_debug_dr7; | |
1193 | else | |
1194 | dr7 = vcpu->arch.dr7; | |
b3646477 | 1195 | static_call(kvm_x86_set_dr7)(vcpu, dr7); |
360b948d PB |
1196 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; |
1197 | if (dr7 & DR7_BP_EN_MASK) | |
1198 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; | |
c8639010 | 1199 | } |
7c86663b | 1200 | EXPORT_SYMBOL_GPL(kvm_update_dr7); |
c8639010 | 1201 | |
6f43ed01 NA |
1202 | static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) |
1203 | { | |
1204 | u64 fixed = DR6_FIXED_1; | |
1205 | ||
d6321d49 | 1206 | if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) |
6f43ed01 | 1207 | fixed |= DR6_RTM; |
e8ea85fb CQ |
1208 | |
1209 | if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT)) | |
1210 | fixed |= DR6_BUS_LOCK; | |
6f43ed01 NA |
1211 | return fixed; |
1212 | } | |
1213 | ||
996ff542 | 1214 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) |
020df079 | 1215 | { |
ea740059 MP |
1216 | size_t size = ARRAY_SIZE(vcpu->arch.db); |
1217 | ||
020df079 GN |
1218 | switch (dr) { |
1219 | case 0 ... 3: | |
ea740059 | 1220 | vcpu->arch.db[array_index_nospec(dr, size)] = val; |
020df079 GN |
1221 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) |
1222 | vcpu->arch.eff_db[dr] = val; | |
1223 | break; | |
1224 | case 4: | |
020df079 | 1225 | case 6: |
f5f6145e | 1226 | if (!kvm_dr6_valid(val)) |
996ff542 | 1227 | return 1; /* #GP */ |
6f43ed01 | 1228 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); |
020df079 GN |
1229 | break; |
1230 | case 5: | |
020df079 | 1231 | default: /* 7 */ |
b91991bf | 1232 | if (!kvm_dr7_valid(val)) |
996ff542 | 1233 | return 1; /* #GP */ |
020df079 | 1234 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; |
c8639010 | 1235 | kvm_update_dr7(vcpu); |
020df079 GN |
1236 | break; |
1237 | } | |
1238 | ||
1239 | return 0; | |
1240 | } | |
1241 | EXPORT_SYMBOL_GPL(kvm_set_dr); | |
1242 | ||
29d6ca41 | 1243 | void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) |
020df079 | 1244 | { |
ea740059 MP |
1245 | size_t size = ARRAY_SIZE(vcpu->arch.db); |
1246 | ||
020df079 GN |
1247 | switch (dr) { |
1248 | case 0 ... 3: | |
ea740059 | 1249 | *val = vcpu->arch.db[array_index_nospec(dr, size)]; |
020df079 GN |
1250 | break; |
1251 | case 4: | |
020df079 | 1252 | case 6: |
5679b803 | 1253 | *val = vcpu->arch.dr6; |
020df079 GN |
1254 | break; |
1255 | case 5: | |
020df079 GN |
1256 | default: /* 7 */ |
1257 | *val = vcpu->arch.dr7; | |
1258 | break; | |
1259 | } | |
338dbc97 | 1260 | } |
020df079 GN |
1261 | EXPORT_SYMBOL_GPL(kvm_get_dr); |
1262 | ||
c483c454 | 1263 | int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu) |
022cd0e8 | 1264 | { |
de3cd117 | 1265 | u32 ecx = kvm_rcx_read(vcpu); |
022cd0e8 | 1266 | u64 data; |
022cd0e8 | 1267 | |
c483c454 SC |
1268 | if (kvm_pmu_rdpmc(vcpu, ecx, &data)) { |
1269 | kvm_inject_gp(vcpu, 0); | |
1270 | return 1; | |
1271 | } | |
1272 | ||
de3cd117 SC |
1273 | kvm_rax_write(vcpu, (u32)data); |
1274 | kvm_rdx_write(vcpu, data >> 32); | |
c483c454 | 1275 | return kvm_skip_emulated_instruction(vcpu); |
022cd0e8 | 1276 | } |
c483c454 | 1277 | EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc); |
022cd0e8 | 1278 | |
043405e1 CO |
1279 | /* |
1280 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
1281 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
1282 | * | |
7a5ee6ed CQ |
1283 | * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) |
1284 | * extract the supported MSRs from the related const lists. | |
1285 | * msrs_to_save is selected from the msrs_to_save_all to reflect the | |
e3267cbb | 1286 | * capabilities of the host cpu. This capabilities test skips MSRs that are |
7a5ee6ed | 1287 | * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs |
62ef68bb | 1288 | * may depend on host virtualization features rather than host cpu features. |
043405e1 | 1289 | */ |
e3267cbb | 1290 | |
7a5ee6ed | 1291 | static const u32 msrs_to_save_all[] = { |
043405e1 | 1292 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, |
8c06585d | 1293 | MSR_STAR, |
043405e1 CO |
1294 | #ifdef CONFIG_X86_64 |
1295 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
1296 | #endif | |
b3897a49 | 1297 | MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, |
32ad73db | 1298 | MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, |
2bdb76c0 | 1299 | MSR_IA32_SPEC_CTRL, |
bf8c55d8 CP |
1300 | MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, |
1301 | MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, | |
1302 | MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, | |
1303 | MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, | |
1304 | MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, | |
1305 | MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, | |
6e3ba4ab TX |
1306 | MSR_IA32_UMWAIT_CONTROL, |
1307 | ||
e2ada66e JM |
1308 | MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, |
1309 | MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3, | |
1310 | MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, | |
1311 | MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, | |
1312 | MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, | |
1313 | MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, | |
1314 | MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, | |
1315 | MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, | |
1316 | MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9, | |
1317 | MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11, | |
1318 | MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13, | |
1319 | MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15, | |
1320 | MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17, | |
e2ada66e JM |
1321 | MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, |
1322 | MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, | |
1323 | MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, | |
1324 | MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, | |
1325 | MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9, | |
1326 | MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11, | |
1327 | MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13, | |
1328 | MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15, | |
1329 | MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17, | |
043405e1 CO |
1330 | }; |
1331 | ||
7a5ee6ed | 1332 | static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)]; |
043405e1 CO |
1333 | static unsigned num_msrs_to_save; |
1334 | ||
7a5ee6ed | 1335 | static const u32 emulated_msrs_all[] = { |
62ef68bb PB |
1336 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, |
1337 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, | |
1338 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, | |
1339 | HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, | |
72c139ba | 1340 | HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, |
e7d9513b AS |
1341 | HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, |
1342 | HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, | |
e516cebb | 1343 | HV_X64_MSR_RESET, |
11c4b1ca | 1344 | HV_X64_MSR_VP_INDEX, |
9eec50b8 | 1345 | HV_X64_MSR_VP_RUNTIME, |
5c919412 | 1346 | HV_X64_MSR_SCONTROL, |
1f4b34f8 | 1347 | HV_X64_MSR_STIMER0_CONFIG, |
d4abc577 | 1348 | HV_X64_MSR_VP_ASSIST_PAGE, |
a2e164e7 VK |
1349 | HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, |
1350 | HV_X64_MSR_TSC_EMULATION_STATUS, | |
f97f5a56 JD |
1351 | HV_X64_MSR_SYNDBG_OPTIONS, |
1352 | HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS, | |
1353 | HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER, | |
1354 | HV_X64_MSR_SYNDBG_PENDING_BUFFER, | |
a2e164e7 VK |
1355 | |
1356 | MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, | |
557a961a | 1357 | MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK, |
62ef68bb | 1358 | |
ba904635 | 1359 | MSR_IA32_TSC_ADJUST, |
09141ec0 | 1360 | MSR_IA32_TSC_DEADLINE, |
2bdb76c0 | 1361 | MSR_IA32_ARCH_CAPABILITIES, |
27461da3 | 1362 | MSR_IA32_PERF_CAPABILITIES, |
043405e1 | 1363 | MSR_IA32_MISC_ENABLE, |
908e75f3 AK |
1364 | MSR_IA32_MCG_STATUS, |
1365 | MSR_IA32_MCG_CTL, | |
c45dcc71 | 1366 | MSR_IA32_MCG_EXT_CTL, |
64d60670 | 1367 | MSR_IA32_SMBASE, |
52797bf9 | 1368 | MSR_SMI_COUNT, |
db2336a8 KH |
1369 | MSR_PLATFORM_INFO, |
1370 | MSR_MISC_FEATURES_ENABLES, | |
bc226f07 | 1371 | MSR_AMD64_VIRT_SPEC_CTRL, |
6c6a2ab9 | 1372 | MSR_IA32_POWER_CTL, |
99634e3e | 1373 | MSR_IA32_UCODE_REV, |
191c8137 | 1374 | |
95c5c7c7 PB |
1375 | /* |
1376 | * The following list leaves out MSRs whose values are determined | |
1377 | * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs. | |
1378 | * We always support the "true" VMX control MSRs, even if the host | |
1379 | * processor does not, so I am putting these registers here rather | |
7a5ee6ed | 1380 | * than in msrs_to_save_all. |
95c5c7c7 PB |
1381 | */ |
1382 | MSR_IA32_VMX_BASIC, | |
1383 | MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
1384 | MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
1385 | MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
1386 | MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
1387 | MSR_IA32_VMX_MISC, | |
1388 | MSR_IA32_VMX_CR0_FIXED0, | |
1389 | MSR_IA32_VMX_CR4_FIXED0, | |
1390 | MSR_IA32_VMX_VMCS_ENUM, | |
1391 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
1392 | MSR_IA32_VMX_EPT_VPID_CAP, | |
1393 | MSR_IA32_VMX_VMFUNC, | |
1394 | ||
191c8137 | 1395 | MSR_K7_HWCR, |
2d5ba19b | 1396 | MSR_KVM_POLL_CONTROL, |
043405e1 CO |
1397 | }; |
1398 | ||
7a5ee6ed | 1399 | static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]; |
62ef68bb PB |
1400 | static unsigned num_emulated_msrs; |
1401 | ||
801e459a TL |
1402 | /* |
1403 | * List of msr numbers which are used to expose MSR-based features that | |
1404 | * can be used by a hypervisor to validate requested CPU features. | |
1405 | */ | |
7a5ee6ed | 1406 | static const u32 msr_based_features_all[] = { |
1389309c PB |
1407 | MSR_IA32_VMX_BASIC, |
1408 | MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
1409 | MSR_IA32_VMX_PINBASED_CTLS, | |
1410 | MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
1411 | MSR_IA32_VMX_PROCBASED_CTLS, | |
1412 | MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
1413 | MSR_IA32_VMX_EXIT_CTLS, | |
1414 | MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
1415 | MSR_IA32_VMX_ENTRY_CTLS, | |
1416 | MSR_IA32_VMX_MISC, | |
1417 | MSR_IA32_VMX_CR0_FIXED0, | |
1418 | MSR_IA32_VMX_CR0_FIXED1, | |
1419 | MSR_IA32_VMX_CR4_FIXED0, | |
1420 | MSR_IA32_VMX_CR4_FIXED1, | |
1421 | MSR_IA32_VMX_VMCS_ENUM, | |
1422 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
1423 | MSR_IA32_VMX_EPT_VPID_CAP, | |
1424 | MSR_IA32_VMX_VMFUNC, | |
1425 | ||
d1d93fa9 | 1426 | MSR_F10H_DECFG, |
518e7b94 | 1427 | MSR_IA32_UCODE_REV, |
cd283252 | 1428 | MSR_IA32_ARCH_CAPABILITIES, |
27461da3 | 1429 | MSR_IA32_PERF_CAPABILITIES, |
801e459a TL |
1430 | }; |
1431 | ||
7a5ee6ed | 1432 | static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)]; |
801e459a TL |
1433 | static unsigned int num_msr_based_features; |
1434 | ||
4d22c17c | 1435 | static u64 kvm_get_arch_capabilities(void) |
5b76a3cf | 1436 | { |
4d22c17c | 1437 | u64 data = 0; |
5b76a3cf | 1438 | |
4d22c17c XL |
1439 | if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) |
1440 | rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data); | |
5b76a3cf | 1441 | |
b8e8c830 PB |
1442 | /* |
1443 | * If nx_huge_pages is enabled, KVM's shadow paging will ensure that | |
1444 | * the nested hypervisor runs with NX huge pages. If it is not, | |
d9f6e12f | 1445 | * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other |
b8e8c830 PB |
1446 | * L1 guests, so it need not worry about its own (L2) guests. |
1447 | */ | |
1448 | data |= ARCH_CAP_PSCHANGE_MC_NO; | |
1449 | ||
5b76a3cf PB |
1450 | /* |
1451 | * If we're doing cache flushes (either "always" or "cond") | |
1452 | * we will do one whenever the guest does a vmlaunch/vmresume. | |
1453 | * If an outer hypervisor is doing the cache flush for us | |
1454 | * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that | |
1455 | * capability to the guest too, and if EPT is disabled we're not | |
1456 | * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will | |
1457 | * require a nested hypervisor to do a flush of its own. | |
1458 | */ | |
1459 | if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) | |
1460 | data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; | |
1461 | ||
0c54914d PB |
1462 | if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) |
1463 | data |= ARCH_CAP_RDCL_NO; | |
1464 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
1465 | data |= ARCH_CAP_SSB_NO; | |
1466 | if (!boot_cpu_has_bug(X86_BUG_MDS)) | |
1467 | data |= ARCH_CAP_MDS_NO; | |
1468 | ||
7131636e PB |
1469 | if (!boot_cpu_has(X86_FEATURE_RTM)) { |
1470 | /* | |
1471 | * If RTM=0 because the kernel has disabled TSX, the host might | |
1472 | * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0 | |
1473 | * and therefore knows that there cannot be TAA) but keep | |
1474 | * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts, | |
1475 | * and we want to allow migrating those guests to tsx=off hosts. | |
1476 | */ | |
1477 | data &= ~ARCH_CAP_TAA_NO; | |
1478 | } else if (!boot_cpu_has_bug(X86_BUG_TAA)) { | |
cbbaa272 | 1479 | data |= ARCH_CAP_TAA_NO; |
7131636e PB |
1480 | } else { |
1481 | /* | |
1482 | * Nothing to do here; we emulate TSX_CTRL if present on the | |
1483 | * host so the guest can choose between disabling TSX or | |
1484 | * using VERW to clear CPU buffers. | |
1485 | */ | |
1486 | } | |
e1d38b63 | 1487 | |
5b76a3cf PB |
1488 | return data; |
1489 | } | |
5b76a3cf | 1490 | |
66421c1e WL |
1491 | static int kvm_get_msr_feature(struct kvm_msr_entry *msr) |
1492 | { | |
1493 | switch (msr->index) { | |
cd283252 | 1494 | case MSR_IA32_ARCH_CAPABILITIES: |
5b76a3cf PB |
1495 | msr->data = kvm_get_arch_capabilities(); |
1496 | break; | |
1497 | case MSR_IA32_UCODE_REV: | |
cd283252 | 1498 | rdmsrl_safe(msr->index, &msr->data); |
518e7b94 | 1499 | break; |
66421c1e | 1500 | default: |
b3646477 | 1501 | return static_call(kvm_x86_get_msr_feature)(msr); |
66421c1e WL |
1502 | } |
1503 | return 0; | |
1504 | } | |
1505 | ||
801e459a TL |
1506 | static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) |
1507 | { | |
1508 | struct kvm_msr_entry msr; | |
66421c1e | 1509 | int r; |
801e459a TL |
1510 | |
1511 | msr.index = index; | |
66421c1e | 1512 | r = kvm_get_msr_feature(&msr); |
12bc2132 PX |
1513 | |
1514 | if (r == KVM_MSR_RET_INVALID) { | |
1515 | /* Unconditionally clear the output for simplicity */ | |
1516 | *data = 0; | |
d632826f | 1517 | if (kvm_msr_ignored_check(index, 0, false)) |
cc4cb017 | 1518 | r = 0; |
12bc2132 PX |
1519 | } |
1520 | ||
66421c1e WL |
1521 | if (r) |
1522 | return r; | |
801e459a TL |
1523 | |
1524 | *data = msr.data; | |
1525 | ||
1526 | return 0; | |
1527 | } | |
1528 | ||
11988499 | 1529 | static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) |
15c4a640 | 1530 | { |
1b4d56b8 | 1531 | if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) |
11988499 | 1532 | return false; |
1b2fd70c | 1533 | |
1b4d56b8 | 1534 | if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) |
11988499 | 1535 | return false; |
d8017474 | 1536 | |
0a629563 SC |
1537 | if (efer & (EFER_LME | EFER_LMA) && |
1538 | !guest_cpuid_has(vcpu, X86_FEATURE_LM)) | |
1539 | return false; | |
1540 | ||
1541 | if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) | |
1542 | return false; | |
d8017474 | 1543 | |
384bb783 | 1544 | return true; |
11988499 SC |
1545 | |
1546 | } | |
1547 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) | |
1548 | { | |
1549 | if (efer & efer_reserved_bits) | |
1550 | return false; | |
1551 | ||
1552 | return __kvm_valid_efer(vcpu, efer); | |
384bb783 JK |
1553 | } |
1554 | EXPORT_SYMBOL_GPL(kvm_valid_efer); | |
1555 | ||
11988499 | 1556 | static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
384bb783 JK |
1557 | { |
1558 | u64 old_efer = vcpu->arch.efer; | |
11988499 | 1559 | u64 efer = msr_info->data; |
72f211ec | 1560 | int r; |
384bb783 | 1561 | |
11988499 | 1562 | if (efer & efer_reserved_bits) |
66f61c92 | 1563 | return 1; |
384bb783 | 1564 | |
11988499 SC |
1565 | if (!msr_info->host_initiated) { |
1566 | if (!__kvm_valid_efer(vcpu, efer)) | |
1567 | return 1; | |
1568 | ||
1569 | if (is_paging(vcpu) && | |
1570 | (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) | |
1571 | return 1; | |
1572 | } | |
384bb783 | 1573 | |
15c4a640 | 1574 | efer &= ~EFER_LMA; |
f6801dff | 1575 | efer |= vcpu->arch.efer & EFER_LMA; |
15c4a640 | 1576 | |
b3646477 | 1577 | r = static_call(kvm_x86_set_efer)(vcpu, efer); |
72f211ec ML |
1578 | if (r) { |
1579 | WARN_ON(r > 0); | |
1580 | return r; | |
1581 | } | |
a3d204e2 | 1582 | |
aad82703 SY |
1583 | /* Update reserved bits */ |
1584 | if ((efer ^ old_efer) & EFER_NX) | |
1585 | kvm_mmu_reset_context(vcpu); | |
1586 | ||
b69e8cae | 1587 | return 0; |
15c4a640 CO |
1588 | } |
1589 | ||
f2b4b7dd JR |
1590 | void kvm_enable_efer_bits(u64 mask) |
1591 | { | |
1592 | efer_reserved_bits &= ~mask; | |
1593 | } | |
1594 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
1595 | ||
51de8151 AG |
1596 | bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type) |
1597 | { | |
b318e8de SC |
1598 | struct kvm_x86_msr_filter *msr_filter; |
1599 | struct msr_bitmap_range *ranges; | |
1a155254 | 1600 | struct kvm *kvm = vcpu->kvm; |
b318e8de | 1601 | bool allowed; |
1a155254 | 1602 | int idx; |
b318e8de | 1603 | u32 i; |
1a155254 | 1604 | |
b318e8de SC |
1605 | /* x2APIC MSRs do not support filtering. */ |
1606 | if (index >= 0x800 && index <= 0x8ff) | |
1a155254 AG |
1607 | return true; |
1608 | ||
1a155254 AG |
1609 | idx = srcu_read_lock(&kvm->srcu); |
1610 | ||
b318e8de SC |
1611 | msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu); |
1612 | if (!msr_filter) { | |
1613 | allowed = true; | |
1614 | goto out; | |
1615 | } | |
1616 | ||
1617 | allowed = msr_filter->default_allow; | |
1618 | ranges = msr_filter->ranges; | |
1619 | ||
1620 | for (i = 0; i < msr_filter->count; i++) { | |
1a155254 AG |
1621 | u32 start = ranges[i].base; |
1622 | u32 end = start + ranges[i].nmsrs; | |
1623 | u32 flags = ranges[i].flags; | |
1624 | unsigned long *bitmap = ranges[i].bitmap; | |
1625 | ||
1626 | if ((index >= start) && (index < end) && (flags & type)) { | |
b318e8de | 1627 | allowed = !!test_bit(index - start, bitmap); |
1a155254 AG |
1628 | break; |
1629 | } | |
1630 | } | |
1631 | ||
b318e8de | 1632 | out: |
1a155254 AG |
1633 | srcu_read_unlock(&kvm->srcu, idx); |
1634 | ||
b318e8de | 1635 | return allowed; |
51de8151 AG |
1636 | } |
1637 | EXPORT_SYMBOL_GPL(kvm_msr_allowed); | |
1638 | ||
15c4a640 | 1639 | /* |
f20935d8 SC |
1640 | * Write @data into the MSR specified by @index. Select MSR specific fault |
1641 | * checks are bypassed if @host_initiated is %true. | |
15c4a640 CO |
1642 | * Returns 0 on success, non-0 otherwise. |
1643 | * Assumes vcpu_load() was already called. | |
1644 | */ | |
f20935d8 SC |
1645 | static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, |
1646 | bool host_initiated) | |
15c4a640 | 1647 | { |
f20935d8 SC |
1648 | struct msr_data msr; |
1649 | ||
1a155254 | 1650 | if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE)) |
cc4cb017 | 1651 | return KVM_MSR_RET_FILTERED; |
1a155254 | 1652 | |
f20935d8 | 1653 | switch (index) { |
854e8bb1 NA |
1654 | case MSR_FS_BASE: |
1655 | case MSR_GS_BASE: | |
1656 | case MSR_KERNEL_GS_BASE: | |
1657 | case MSR_CSTAR: | |
1658 | case MSR_LSTAR: | |
f20935d8 | 1659 | if (is_noncanonical_address(data, vcpu)) |
854e8bb1 NA |
1660 | return 1; |
1661 | break; | |
1662 | case MSR_IA32_SYSENTER_EIP: | |
1663 | case MSR_IA32_SYSENTER_ESP: | |
1664 | /* | |
1665 | * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if | |
1666 | * non-canonical address is written on Intel but not on | |
1667 | * AMD (which ignores the top 32-bits, because it does | |
1668 | * not implement 64-bit SYSENTER). | |
1669 | * | |
1670 | * 64-bit code should hence be able to write a non-canonical | |
1671 | * value on AMD. Making the address canonical ensures that | |
1672 | * vmentry does not fail on Intel after writing a non-canonical | |
1673 | * value, and that something deterministic happens if the guest | |
1674 | * invokes 64-bit SYSENTER. | |
1675 | */ | |
f20935d8 | 1676 | data = get_canonical(data, vcpu_virt_addr_bits(vcpu)); |
61a05d44 SC |
1677 | break; |
1678 | case MSR_TSC_AUX: | |
1679 | if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) | |
1680 | return 1; | |
1681 | ||
1682 | if (!host_initiated && | |
1683 | !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && | |
1684 | !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) | |
1685 | return 1; | |
1686 | ||
1687 | /* | |
1688 | * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has | |
1689 | * incomplete and conflicting architectural behavior. Current | |
1690 | * AMD CPUs completely ignore bits 63:32, i.e. they aren't | |
1691 | * reserved and always read as zeros. Enforce Intel's reserved | |
1692 | * bits check if and only if the guest CPU is Intel, and clear | |
1693 | * the bits in all other cases. This ensures cross-vendor | |
1694 | * migration will provide consistent behavior for the guest. | |
1695 | */ | |
1696 | if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0) | |
1697 | return 1; | |
1698 | ||
1699 | data = (u32)data; | |
1700 | break; | |
854e8bb1 | 1701 | } |
f20935d8 SC |
1702 | |
1703 | msr.data = data; | |
1704 | msr.index = index; | |
1705 | msr.host_initiated = host_initiated; | |
1706 | ||
b3646477 | 1707 | return static_call(kvm_x86_set_msr)(vcpu, &msr); |
15c4a640 CO |
1708 | } |
1709 | ||
6abe9c13 PX |
1710 | static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu, |
1711 | u32 index, u64 data, bool host_initiated) | |
1712 | { | |
1713 | int ret = __kvm_set_msr(vcpu, index, data, host_initiated); | |
1714 | ||
1715 | if (ret == KVM_MSR_RET_INVALID) | |
d632826f | 1716 | if (kvm_msr_ignored_check(index, data, true)) |
cc4cb017 | 1717 | ret = 0; |
6abe9c13 PX |
1718 | |
1719 | return ret; | |
1720 | } | |
1721 | ||
313a3dc7 | 1722 | /* |
f20935d8 SC |
1723 | * Read the MSR specified by @index into @data. Select MSR specific fault |
1724 | * checks are bypassed if @host_initiated is %true. | |
1725 | * Returns 0 on success, non-0 otherwise. | |
1726 | * Assumes vcpu_load() was already called. | |
313a3dc7 | 1727 | */ |
edef5c36 PB |
1728 | int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, |
1729 | bool host_initiated) | |
609e36d3 PB |
1730 | { |
1731 | struct msr_data msr; | |
f20935d8 | 1732 | int ret; |
609e36d3 | 1733 | |
1a155254 | 1734 | if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ)) |
cc4cb017 | 1735 | return KVM_MSR_RET_FILTERED; |
1a155254 | 1736 | |
61a05d44 SC |
1737 | switch (index) { |
1738 | case MSR_TSC_AUX: | |
1739 | if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) | |
1740 | return 1; | |
1741 | ||
1742 | if (!host_initiated && | |
1743 | !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && | |
1744 | !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) | |
1745 | return 1; | |
1746 | break; | |
1747 | } | |
1748 | ||
609e36d3 | 1749 | msr.index = index; |
f20935d8 | 1750 | msr.host_initiated = host_initiated; |
609e36d3 | 1751 | |
b3646477 | 1752 | ret = static_call(kvm_x86_get_msr)(vcpu, &msr); |
f20935d8 SC |
1753 | if (!ret) |
1754 | *data = msr.data; | |
1755 | return ret; | |
609e36d3 PB |
1756 | } |
1757 | ||
6abe9c13 PX |
1758 | static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu, |
1759 | u32 index, u64 *data, bool host_initiated) | |
1760 | { | |
1761 | int ret = __kvm_get_msr(vcpu, index, data, host_initiated); | |
1762 | ||
1763 | if (ret == KVM_MSR_RET_INVALID) { | |
1764 | /* Unconditionally clear *data for simplicity */ | |
1765 | *data = 0; | |
d632826f | 1766 | if (kvm_msr_ignored_check(index, 0, false)) |
cc4cb017 | 1767 | ret = 0; |
6abe9c13 PX |
1768 | } |
1769 | ||
1770 | return ret; | |
1771 | } | |
1772 | ||
f20935d8 | 1773 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) |
313a3dc7 | 1774 | { |
6abe9c13 | 1775 | return kvm_get_msr_ignored_check(vcpu, index, data, false); |
f20935d8 SC |
1776 | } |
1777 | EXPORT_SYMBOL_GPL(kvm_get_msr); | |
8fe8ab46 | 1778 | |
f20935d8 SC |
1779 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) |
1780 | { | |
6abe9c13 | 1781 | return kvm_set_msr_ignored_check(vcpu, index, data, false); |
f20935d8 SC |
1782 | } |
1783 | EXPORT_SYMBOL_GPL(kvm_set_msr); | |
1784 | ||
8b474427 | 1785 | static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu) |
1ae09954 | 1786 | { |
8b474427 PB |
1787 | int err = vcpu->run->msr.error; |
1788 | if (!err) { | |
1ae09954 AG |
1789 | kvm_rax_write(vcpu, (u32)vcpu->run->msr.data); |
1790 | kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32); | |
1791 | } | |
1792 | ||
b3646477 | 1793 | return static_call(kvm_x86_complete_emulated_msr)(vcpu, err); |
1ae09954 AG |
1794 | } |
1795 | ||
1796 | static int complete_emulated_wrmsr(struct kvm_vcpu *vcpu) | |
1797 | { | |
b3646477 | 1798 | return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error); |
1ae09954 AG |
1799 | } |
1800 | ||
1801 | static u64 kvm_msr_reason(int r) | |
1802 | { | |
1803 | switch (r) { | |
cc4cb017 | 1804 | case KVM_MSR_RET_INVALID: |
1ae09954 | 1805 | return KVM_MSR_EXIT_REASON_UNKNOWN; |
cc4cb017 | 1806 | case KVM_MSR_RET_FILTERED: |
1a155254 | 1807 | return KVM_MSR_EXIT_REASON_FILTER; |
1ae09954 AG |
1808 | default: |
1809 | return KVM_MSR_EXIT_REASON_INVAL; | |
1810 | } | |
1811 | } | |
1812 | ||
1813 | static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index, | |
1814 | u32 exit_reason, u64 data, | |
1815 | int (*completion)(struct kvm_vcpu *vcpu), | |
1816 | int r) | |
1817 | { | |
1818 | u64 msr_reason = kvm_msr_reason(r); | |
1819 | ||
1820 | /* Check if the user wanted to know about this MSR fault */ | |
1821 | if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason)) | |
1822 | return 0; | |
1823 | ||
1824 | vcpu->run->exit_reason = exit_reason; | |
1825 | vcpu->run->msr.error = 0; | |
1826 | memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad)); | |
1827 | vcpu->run->msr.reason = msr_reason; | |
1828 | vcpu->run->msr.index = index; | |
1829 | vcpu->run->msr.data = data; | |
1830 | vcpu->arch.complete_userspace_io = completion; | |
1831 | ||
1832 | return 1; | |
1833 | } | |
1834 | ||
1835 | static int kvm_get_msr_user_space(struct kvm_vcpu *vcpu, u32 index, int r) | |
1836 | { | |
1837 | return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_RDMSR, 0, | |
1838 | complete_emulated_rdmsr, r); | |
1839 | } | |
1840 | ||
1841 | static int kvm_set_msr_user_space(struct kvm_vcpu *vcpu, u32 index, u64 data, int r) | |
1842 | { | |
1843 | return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_WRMSR, data, | |
1844 | complete_emulated_wrmsr, r); | |
1845 | } | |
1846 | ||
1edce0a9 SC |
1847 | int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) |
1848 | { | |
1849 | u32 ecx = kvm_rcx_read(vcpu); | |
1850 | u64 data; | |
1ae09954 AG |
1851 | int r; |
1852 | ||
1853 | r = kvm_get_msr(vcpu, ecx, &data); | |
1edce0a9 | 1854 | |
1ae09954 AG |
1855 | /* MSR read failed? See if we should ask user space */ |
1856 | if (r && kvm_get_msr_user_space(vcpu, ecx, r)) { | |
1857 | /* Bounce to user space */ | |
1858 | return 0; | |
1859 | } | |
1860 | ||
8b474427 PB |
1861 | if (!r) { |
1862 | trace_kvm_msr_read(ecx, data); | |
1863 | ||
1864 | kvm_rax_write(vcpu, data & -1u); | |
1865 | kvm_rdx_write(vcpu, (data >> 32) & -1u); | |
1866 | } else { | |
1edce0a9 | 1867 | trace_kvm_msr_read_ex(ecx); |
1edce0a9 SC |
1868 | } |
1869 | ||
b3646477 | 1870 | return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); |
1edce0a9 SC |
1871 | } |
1872 | EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); | |
1873 | ||
1874 | int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) | |
1875 | { | |
1876 | u32 ecx = kvm_rcx_read(vcpu); | |
1877 | u64 data = kvm_read_edx_eax(vcpu); | |
1ae09954 | 1878 | int r; |
1edce0a9 | 1879 | |
1ae09954 AG |
1880 | r = kvm_set_msr(vcpu, ecx, data); |
1881 | ||
1882 | /* MSR write failed? See if we should ask user space */ | |
7dffecaf | 1883 | if (r && kvm_set_msr_user_space(vcpu, ecx, data, r)) |
1ae09954 AG |
1884 | /* Bounce to user space */ |
1885 | return 0; | |
7dffecaf ML |
1886 | |
1887 | /* Signal all other negative errors to userspace */ | |
1888 | if (r < 0) | |
1889 | return r; | |
1ae09954 | 1890 | |
8b474427 PB |
1891 | if (!r) |
1892 | trace_kvm_msr_write(ecx, data); | |
1893 | else | |
1edce0a9 | 1894 | trace_kvm_msr_write_ex(ecx, data); |
1edce0a9 | 1895 | |
b3646477 | 1896 | return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); |
1edce0a9 SC |
1897 | } |
1898 | EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); | |
1899 | ||
5ff3a351 SC |
1900 | int kvm_emulate_as_nop(struct kvm_vcpu *vcpu) |
1901 | { | |
1902 | return kvm_skip_emulated_instruction(vcpu); | |
1903 | } | |
1904 | EXPORT_SYMBOL_GPL(kvm_emulate_as_nop); | |
1905 | ||
1906 | int kvm_emulate_invd(struct kvm_vcpu *vcpu) | |
1907 | { | |
1908 | /* Treat an INVD instruction as a NOP and just skip it. */ | |
1909 | return kvm_emulate_as_nop(vcpu); | |
1910 | } | |
1911 | EXPORT_SYMBOL_GPL(kvm_emulate_invd); | |
1912 | ||
1913 | int kvm_emulate_mwait(struct kvm_vcpu *vcpu) | |
1914 | { | |
1915 | pr_warn_once("kvm: MWAIT instruction emulated as NOP!\n"); | |
1916 | return kvm_emulate_as_nop(vcpu); | |
1917 | } | |
1918 | EXPORT_SYMBOL_GPL(kvm_emulate_mwait); | |
1919 | ||
1920 | int kvm_handle_invalid_op(struct kvm_vcpu *vcpu) | |
1921 | { | |
1922 | kvm_queue_exception(vcpu, UD_VECTOR); | |
1923 | return 1; | |
1924 | } | |
1925 | EXPORT_SYMBOL_GPL(kvm_handle_invalid_op); | |
1926 | ||
1927 | int kvm_emulate_monitor(struct kvm_vcpu *vcpu) | |
1928 | { | |
1929 | pr_warn_once("kvm: MONITOR instruction emulated as NOP!\n"); | |
1930 | return kvm_emulate_as_nop(vcpu); | |
1931 | } | |
1932 | EXPORT_SYMBOL_GPL(kvm_emulate_monitor); | |
1933 | ||
d89d04ab | 1934 | static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu) |
5a9f5443 | 1935 | { |
4ae7dc97 | 1936 | xfer_to_guest_mode_prepare(); |
5a9f5443 | 1937 | return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) || |
72c3c0fe | 1938 | xfer_to_guest_mode_work_pending(); |
5a9f5443 | 1939 | } |
5a9f5443 | 1940 | |
1e9e2622 WL |
1941 | /* |
1942 | * The fast path for frequent and performance sensitive wrmsr emulation, | |
1943 | * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces | |
1944 | * the latency of virtual IPI by avoiding the expensive bits of transitioning | |
1945 | * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the | |
1946 | * other cases which must be called after interrupts are enabled on the host. | |
1947 | */ | |
1948 | static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data) | |
1949 | { | |
e1be9ac8 WL |
1950 | if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic)) |
1951 | return 1; | |
1952 | ||
1953 | if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) && | |
1e9e2622 | 1954 | ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) && |
4064a4c6 WL |
1955 | ((data & APIC_MODE_MASK) == APIC_DM_FIXED) && |
1956 | ((u32)(data >> 32) != X2APIC_BROADCAST)) { | |
1e9e2622 | 1957 | |
d5361678 WL |
1958 | data &= ~(1 << 12); |
1959 | kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32)); | |
1e9e2622 | 1960 | kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32)); |
d5361678 WL |
1961 | kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data); |
1962 | trace_kvm_apic_write(APIC_ICR, (u32)data); | |
1963 | return 0; | |
1e9e2622 WL |
1964 | } |
1965 | ||
1966 | return 1; | |
1967 | } | |
1968 | ||
ae95f566 WL |
1969 | static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data) |
1970 | { | |
1971 | if (!kvm_can_use_hv_timer(vcpu)) | |
1972 | return 1; | |
1973 | ||
1974 | kvm_set_lapic_tscdeadline_msr(vcpu, data); | |
1975 | return 0; | |
1976 | } | |
1977 | ||
404d5d7b | 1978 | fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu) |
1e9e2622 WL |
1979 | { |
1980 | u32 msr = kvm_rcx_read(vcpu); | |
8a1038de | 1981 | u64 data; |
404d5d7b | 1982 | fastpath_t ret = EXIT_FASTPATH_NONE; |
1e9e2622 WL |
1983 | |
1984 | switch (msr) { | |
1985 | case APIC_BASE_MSR + (APIC_ICR >> 4): | |
8a1038de | 1986 | data = kvm_read_edx_eax(vcpu); |
404d5d7b WL |
1987 | if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) { |
1988 | kvm_skip_emulated_instruction(vcpu); | |
1989 | ret = EXIT_FASTPATH_EXIT_HANDLED; | |
80bc97f2 | 1990 | } |
1e9e2622 | 1991 | break; |
09141ec0 | 1992 | case MSR_IA32_TSC_DEADLINE: |
ae95f566 WL |
1993 | data = kvm_read_edx_eax(vcpu); |
1994 | if (!handle_fastpath_set_tscdeadline(vcpu, data)) { | |
1995 | kvm_skip_emulated_instruction(vcpu); | |
1996 | ret = EXIT_FASTPATH_REENTER_GUEST; | |
1997 | } | |
1998 | break; | |
1e9e2622 | 1999 | default: |
404d5d7b | 2000 | break; |
1e9e2622 WL |
2001 | } |
2002 | ||
404d5d7b | 2003 | if (ret != EXIT_FASTPATH_NONE) |
1e9e2622 | 2004 | trace_kvm_msr_write(msr, data); |
1e9e2622 | 2005 | |
404d5d7b | 2006 | return ret; |
1e9e2622 WL |
2007 | } |
2008 | EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); | |
2009 | ||
f20935d8 SC |
2010 | /* |
2011 | * Adapt set_msr() to msr_io()'s calling convention | |
2012 | */ | |
2013 | static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
2014 | { | |
6abe9c13 | 2015 | return kvm_get_msr_ignored_check(vcpu, index, data, true); |
f20935d8 SC |
2016 | } |
2017 | ||
2018 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
2019 | { | |
6abe9c13 | 2020 | return kvm_set_msr_ignored_check(vcpu, index, *data, true); |
313a3dc7 CO |
2021 | } |
2022 | ||
16e8d74d | 2023 | #ifdef CONFIG_X86_64 |
53fafdbb MT |
2024 | struct pvclock_clock { |
2025 | int vclock_mode; | |
2026 | u64 cycle_last; | |
2027 | u64 mask; | |
2028 | u32 mult; | |
2029 | u32 shift; | |
917f9475 PB |
2030 | u64 base_cycles; |
2031 | u64 offset; | |
53fafdbb MT |
2032 | }; |
2033 | ||
16e8d74d MT |
2034 | struct pvclock_gtod_data { |
2035 | seqcount_t seq; | |
2036 | ||
53fafdbb MT |
2037 | struct pvclock_clock clock; /* extract of a clocksource struct */ |
2038 | struct pvclock_clock raw_clock; /* extract of a clocksource struct */ | |
16e8d74d | 2039 | |
917f9475 | 2040 | ktime_t offs_boot; |
55dd00a7 | 2041 | u64 wall_time_sec; |
16e8d74d MT |
2042 | }; |
2043 | ||
2044 | static struct pvclock_gtod_data pvclock_gtod_data; | |
2045 | ||
2046 | static void update_pvclock_gtod(struct timekeeper *tk) | |
2047 | { | |
2048 | struct pvclock_gtod_data *vdata = &pvclock_gtod_data; | |
2049 | ||
2050 | write_seqcount_begin(&vdata->seq); | |
2051 | ||
2052 | /* copy pvclock gtod data */ | |
b95a8a27 | 2053 | vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode; |
876e7881 PZ |
2054 | vdata->clock.cycle_last = tk->tkr_mono.cycle_last; |
2055 | vdata->clock.mask = tk->tkr_mono.mask; | |
2056 | vdata->clock.mult = tk->tkr_mono.mult; | |
2057 | vdata->clock.shift = tk->tkr_mono.shift; | |
917f9475 PB |
2058 | vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec; |
2059 | vdata->clock.offset = tk->tkr_mono.base; | |
16e8d74d | 2060 | |
b95a8a27 | 2061 | vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode; |
53fafdbb MT |
2062 | vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last; |
2063 | vdata->raw_clock.mask = tk->tkr_raw.mask; | |
2064 | vdata->raw_clock.mult = tk->tkr_raw.mult; | |
2065 | vdata->raw_clock.shift = tk->tkr_raw.shift; | |
917f9475 PB |
2066 | vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec; |
2067 | vdata->raw_clock.offset = tk->tkr_raw.base; | |
16e8d74d | 2068 | |
55dd00a7 MT |
2069 | vdata->wall_time_sec = tk->xtime_sec; |
2070 | ||
917f9475 | 2071 | vdata->offs_boot = tk->offs_boot; |
53fafdbb | 2072 | |
16e8d74d MT |
2073 | write_seqcount_end(&vdata->seq); |
2074 | } | |
8171cd68 PB |
2075 | |
2076 | static s64 get_kvmclock_base_ns(void) | |
2077 | { | |
2078 | /* Count up from boot time, but with the frequency of the raw clock. */ | |
2079 | return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot)); | |
2080 | } | |
2081 | #else | |
2082 | static s64 get_kvmclock_base_ns(void) | |
2083 | { | |
2084 | /* Master clock not used, so we can just use CLOCK_BOOTTIME. */ | |
2085 | return ktime_get_boottime_ns(); | |
2086 | } | |
16e8d74d MT |
2087 | #endif |
2088 | ||
629b5348 | 2089 | void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs) |
18068523 | 2090 | { |
9ed3c444 AK |
2091 | int version; |
2092 | int r; | |
50d0a0f9 | 2093 | struct pvclock_wall_clock wc; |
629b5348 | 2094 | u32 wc_sec_hi; |
8171cd68 | 2095 | u64 wall_nsec; |
18068523 GOC |
2096 | |
2097 | if (!wall_clock) | |
2098 | return; | |
2099 | ||
9ed3c444 AK |
2100 | r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); |
2101 | if (r) | |
2102 | return; | |
2103 | ||
2104 | if (version & 1) | |
2105 | ++version; /* first time write, random junk */ | |
2106 | ||
2107 | ++version; | |
18068523 | 2108 | |
1dab1345 NK |
2109 | if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) |
2110 | return; | |
18068523 | 2111 | |
50d0a0f9 GH |
2112 | /* |
2113 | * The guest calculates current wall clock time by adding | |
34c238a1 | 2114 | * system time (updated by kvm_guest_time_update below) to the |
8171cd68 | 2115 | * wall clock specified here. We do the reverse here. |
50d0a0f9 | 2116 | */ |
8171cd68 | 2117 | wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm); |
50d0a0f9 | 2118 | |
8171cd68 PB |
2119 | wc.nsec = do_div(wall_nsec, 1000000000); |
2120 | wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */ | |
50d0a0f9 | 2121 | wc.version = version; |
18068523 GOC |
2122 | |
2123 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
2124 | ||
629b5348 JM |
2125 | if (sec_hi_ofs) { |
2126 | wc_sec_hi = wall_nsec >> 32; | |
2127 | kvm_write_guest(kvm, wall_clock + sec_hi_ofs, | |
2128 | &wc_sec_hi, sizeof(wc_sec_hi)); | |
2129 | } | |
2130 | ||
18068523 GOC |
2131 | version++; |
2132 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
2133 | } |
2134 | ||
5b9bb0eb OU |
2135 | static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time, |
2136 | bool old_msr, bool host_initiated) | |
2137 | { | |
2138 | struct kvm_arch *ka = &vcpu->kvm->arch; | |
2139 | ||
2140 | if (vcpu->vcpu_id == 0 && !host_initiated) { | |
1e293d1a | 2141 | if (ka->boot_vcpu_runs_old_kvmclock != old_msr) |
5b9bb0eb OU |
2142 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
2143 | ||
2144 | ka->boot_vcpu_runs_old_kvmclock = old_msr; | |
2145 | } | |
2146 | ||
2147 | vcpu->arch.time = system_time; | |
2148 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); | |
2149 | ||
2150 | /* we verify if the enable bit is set... */ | |
2151 | vcpu->arch.pv_time_enabled = false; | |
2152 | if (!(system_time & 1)) | |
2153 | return; | |
2154 | ||
2155 | if (!kvm_gfn_to_hva_cache_init(vcpu->kvm, | |
2156 | &vcpu->arch.pv_time, system_time & ~1ULL, | |
2157 | sizeof(struct pvclock_vcpu_time_info))) | |
2158 | vcpu->arch.pv_time_enabled = true; | |
2159 | ||
2160 | return; | |
2161 | } | |
2162 | ||
50d0a0f9 GH |
2163 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
2164 | { | |
b51012de PB |
2165 | do_shl32_div32(dividend, divisor); |
2166 | return dividend; | |
50d0a0f9 GH |
2167 | } |
2168 | ||
3ae13faa | 2169 | static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, |
5f4e3f88 | 2170 | s8 *pshift, u32 *pmultiplier) |
50d0a0f9 | 2171 | { |
5f4e3f88 | 2172 | uint64_t scaled64; |
50d0a0f9 GH |
2173 | int32_t shift = 0; |
2174 | uint64_t tps64; | |
2175 | uint32_t tps32; | |
2176 | ||
3ae13faa PB |
2177 | tps64 = base_hz; |
2178 | scaled64 = scaled_hz; | |
50933623 | 2179 | while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { |
50d0a0f9 GH |
2180 | tps64 >>= 1; |
2181 | shift--; | |
2182 | } | |
2183 | ||
2184 | tps32 = (uint32_t)tps64; | |
50933623 JK |
2185 | while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { |
2186 | if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) | |
5f4e3f88 ZA |
2187 | scaled64 >>= 1; |
2188 | else | |
2189 | tps32 <<= 1; | |
50d0a0f9 GH |
2190 | shift++; |
2191 | } | |
2192 | ||
5f4e3f88 ZA |
2193 | *pshift = shift; |
2194 | *pmultiplier = div_frac(scaled64, tps32); | |
50d0a0f9 GH |
2195 | } |
2196 | ||
d828199e | 2197 | #ifdef CONFIG_X86_64 |
16e8d74d | 2198 | static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); |
d828199e | 2199 | #endif |
16e8d74d | 2200 | |
c8076604 | 2201 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
69b0049a | 2202 | static unsigned long max_tsc_khz; |
c8076604 | 2203 | |
cc578287 | 2204 | static u32 adjust_tsc_khz(u32 khz, s32 ppm) |
1e993611 | 2205 | { |
cc578287 ZA |
2206 | u64 v = (u64)khz * (1000000 + ppm); |
2207 | do_div(v, 1000000); | |
2208 | return v; | |
1e993611 JR |
2209 | } |
2210 | ||
1ab9287a IS |
2211 | static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier); |
2212 | ||
381d585c HZ |
2213 | static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) |
2214 | { | |
2215 | u64 ratio; | |
2216 | ||
2217 | /* Guest TSC same frequency as host TSC? */ | |
2218 | if (!scale) { | |
1ab9287a | 2219 | kvm_vcpu_write_tsc_multiplier(vcpu, kvm_default_tsc_scaling_ratio); |
381d585c HZ |
2220 | return 0; |
2221 | } | |
2222 | ||
2223 | /* TSC scaling supported? */ | |
2224 | if (!kvm_has_tsc_control) { | |
2225 | if (user_tsc_khz > tsc_khz) { | |
2226 | vcpu->arch.tsc_catchup = 1; | |
2227 | vcpu->arch.tsc_always_catchup = 1; | |
2228 | return 0; | |
2229 | } else { | |
3f16a5c3 | 2230 | pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); |
381d585c HZ |
2231 | return -1; |
2232 | } | |
2233 | } | |
2234 | ||
2235 | /* TSC scaling required - calculate ratio */ | |
2236 | ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, | |
2237 | user_tsc_khz, tsc_khz); | |
2238 | ||
2239 | if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { | |
3f16a5c3 PB |
2240 | pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", |
2241 | user_tsc_khz); | |
381d585c HZ |
2242 | return -1; |
2243 | } | |
2244 | ||
1ab9287a | 2245 | kvm_vcpu_write_tsc_multiplier(vcpu, ratio); |
381d585c HZ |
2246 | return 0; |
2247 | } | |
2248 | ||
4941b8cb | 2249 | static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) |
759379dd | 2250 | { |
cc578287 ZA |
2251 | u32 thresh_lo, thresh_hi; |
2252 | int use_scaling = 0; | |
217fc9cf | 2253 | |
03ba32ca | 2254 | /* tsc_khz can be zero if TSC calibration fails */ |
4941b8cb | 2255 | if (user_tsc_khz == 0) { |
ad721883 | 2256 | /* set tsc_scaling_ratio to a safe value */ |
1ab9287a | 2257 | kvm_vcpu_write_tsc_multiplier(vcpu, kvm_default_tsc_scaling_ratio); |
381d585c | 2258 | return -1; |
ad721883 | 2259 | } |
03ba32ca | 2260 | |
c285545f | 2261 | /* Compute a scale to convert nanoseconds in TSC cycles */ |
3ae13faa | 2262 | kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, |
cc578287 ZA |
2263 | &vcpu->arch.virtual_tsc_shift, |
2264 | &vcpu->arch.virtual_tsc_mult); | |
4941b8cb | 2265 | vcpu->arch.virtual_tsc_khz = user_tsc_khz; |
cc578287 ZA |
2266 | |
2267 | /* | |
2268 | * Compute the variation in TSC rate which is acceptable | |
2269 | * within the range of tolerance and decide if the | |
2270 | * rate being applied is within that bounds of the hardware | |
2271 | * rate. If so, no scaling or compensation need be done. | |
2272 | */ | |
2273 | thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); | |
2274 | thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); | |
4941b8cb PB |
2275 | if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { |
2276 | pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); | |
cc578287 ZA |
2277 | use_scaling = 1; |
2278 | } | |
4941b8cb | 2279 | return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); |
c285545f ZA |
2280 | } |
2281 | ||
2282 | static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) | |
2283 | { | |
e26101b1 | 2284 | u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, |
cc578287 ZA |
2285 | vcpu->arch.virtual_tsc_mult, |
2286 | vcpu->arch.virtual_tsc_shift); | |
e26101b1 | 2287 | tsc += vcpu->arch.this_tsc_write; |
c285545f ZA |
2288 | return tsc; |
2289 | } | |
2290 | ||
b0c39dc6 VK |
2291 | static inline int gtod_is_based_on_tsc(int mode) |
2292 | { | |
b95a8a27 | 2293 | return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK; |
b0c39dc6 VK |
2294 | } |
2295 | ||
69b0049a | 2296 | static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) |
b48aa97e MT |
2297 | { |
2298 | #ifdef CONFIG_X86_64 | |
2299 | bool vcpus_matched; | |
b48aa97e MT |
2300 | struct kvm_arch *ka = &vcpu->kvm->arch; |
2301 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
2302 | ||
2303 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
2304 | atomic_read(&vcpu->kvm->online_vcpus)); | |
2305 | ||
7f187922 MT |
2306 | /* |
2307 | * Once the masterclock is enabled, always perform request in | |
2308 | * order to update it. | |
2309 | * | |
2310 | * In order to enable masterclock, the host clocksource must be TSC | |
2311 | * and the vcpus need to have matched TSCs. When that happens, | |
2312 | * perform request to enable masterclock. | |
2313 | */ | |
2314 | if (ka->use_master_clock || | |
b0c39dc6 | 2315 | (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) |
b48aa97e MT |
2316 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
2317 | ||
2318 | trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, | |
2319 | atomic_read(&vcpu->kvm->online_vcpus), | |
2320 | ka->use_master_clock, gtod->clock.vclock_mode); | |
2321 | #endif | |
2322 | } | |
2323 | ||
35181e86 HZ |
2324 | /* |
2325 | * Multiply tsc by a fixed point number represented by ratio. | |
2326 | * | |
2327 | * The most significant 64-N bits (mult) of ratio represent the | |
2328 | * integral part of the fixed point number; the remaining N bits | |
2329 | * (frac) represent the fractional part, ie. ratio represents a fixed | |
2330 | * point number (mult + frac * 2^(-N)). | |
2331 | * | |
2332 | * N equals to kvm_tsc_scaling_ratio_frac_bits. | |
2333 | */ | |
2334 | static inline u64 __scale_tsc(u64 ratio, u64 tsc) | |
2335 | { | |
2336 | return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); | |
2337 | } | |
2338 | ||
fe3eb504 | 2339 | u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc, u64 ratio) |
35181e86 HZ |
2340 | { |
2341 | u64 _tsc = tsc; | |
35181e86 HZ |
2342 | |
2343 | if (ratio != kvm_default_tsc_scaling_ratio) | |
2344 | _tsc = __scale_tsc(ratio, tsc); | |
2345 | ||
2346 | return _tsc; | |
2347 | } | |
2348 | EXPORT_SYMBOL_GPL(kvm_scale_tsc); | |
2349 | ||
9b399dfd | 2350 | static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) |
07c1419a HZ |
2351 | { |
2352 | u64 tsc; | |
2353 | ||
fe3eb504 | 2354 | tsc = kvm_scale_tsc(vcpu, rdtsc(), vcpu->arch.l1_tsc_scaling_ratio); |
07c1419a HZ |
2355 | |
2356 | return target_tsc - tsc; | |
2357 | } | |
2358 | ||
4ba76538 HZ |
2359 | u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) |
2360 | { | |
fe3eb504 IS |
2361 | return vcpu->arch.l1_tsc_offset + |
2362 | kvm_scale_tsc(vcpu, host_tsc, vcpu->arch.l1_tsc_scaling_ratio); | |
4ba76538 HZ |
2363 | } |
2364 | EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); | |
2365 | ||
83150f29 IS |
2366 | u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier) |
2367 | { | |
2368 | u64 nested_offset; | |
2369 | ||
2370 | if (l2_multiplier == kvm_default_tsc_scaling_ratio) | |
2371 | nested_offset = l1_offset; | |
2372 | else | |
2373 | nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier, | |
2374 | kvm_tsc_scaling_ratio_frac_bits); | |
2375 | ||
2376 | nested_offset += l2_offset; | |
2377 | return nested_offset; | |
2378 | } | |
2379 | EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset); | |
2380 | ||
2381 | u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier) | |
2382 | { | |
2383 | if (l2_multiplier != kvm_default_tsc_scaling_ratio) | |
2384 | return mul_u64_u64_shr(l1_multiplier, l2_multiplier, | |
2385 | kvm_tsc_scaling_ratio_frac_bits); | |
2386 | ||
2387 | return l1_multiplier; | |
2388 | } | |
2389 | EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier); | |
2390 | ||
edcfe540 | 2391 | static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset) |
a545ab6a | 2392 | { |
edcfe540 IS |
2393 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, |
2394 | vcpu->arch.l1_tsc_offset, | |
2395 | l1_offset); | |
2396 | ||
2397 | vcpu->arch.l1_tsc_offset = l1_offset; | |
2398 | ||
2399 | /* | |
2400 | * If we are here because L1 chose not to trap WRMSR to TSC then | |
2401 | * according to the spec this should set L1's TSC (as opposed to | |
2402 | * setting L1's offset for L2). | |
2403 | */ | |
2404 | if (is_guest_mode(vcpu)) | |
2405 | vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset( | |
2406 | l1_offset, | |
2407 | static_call(kvm_x86_get_l2_tsc_offset)(vcpu), | |
2408 | static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); | |
2409 | else | |
2410 | vcpu->arch.tsc_offset = l1_offset; | |
2411 | ||
2412 | static_call(kvm_x86_write_tsc_offset)(vcpu, vcpu->arch.tsc_offset); | |
a545ab6a LC |
2413 | } |
2414 | ||
1ab9287a IS |
2415 | static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier) |
2416 | { | |
2417 | vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier; | |
2418 | ||
2419 | /* Userspace is changing the multiplier while L2 is active */ | |
2420 | if (is_guest_mode(vcpu)) | |
2421 | vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier( | |
2422 | l1_multiplier, | |
2423 | static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); | |
2424 | else | |
2425 | vcpu->arch.tsc_scaling_ratio = l1_multiplier; | |
2426 | ||
2427 | if (kvm_has_tsc_control) | |
2428 | static_call(kvm_x86_write_tsc_multiplier)( | |
2429 | vcpu, vcpu->arch.tsc_scaling_ratio); | |
2430 | } | |
2431 | ||
b0c39dc6 VK |
2432 | static inline bool kvm_check_tsc_unstable(void) |
2433 | { | |
2434 | #ifdef CONFIG_X86_64 | |
2435 | /* | |
2436 | * TSC is marked unstable when we're running on Hyper-V, | |
2437 | * 'TSC page' clocksource is good. | |
2438 | */ | |
b95a8a27 | 2439 | if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK) |
b0c39dc6 VK |
2440 | return false; |
2441 | #endif | |
2442 | return check_tsc_unstable(); | |
2443 | } | |
2444 | ||
0c899c25 | 2445 | static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data) |
99e3e30a ZA |
2446 | { |
2447 | struct kvm *kvm = vcpu->kvm; | |
f38e098f | 2448 | u64 offset, ns, elapsed; |
99e3e30a | 2449 | unsigned long flags; |
b48aa97e | 2450 | bool matched; |
0d3da0d2 | 2451 | bool already_matched; |
c5e8ec8e | 2452 | bool synchronizing = false; |
99e3e30a | 2453 | |
038f8c11 | 2454 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); |
9b399dfd | 2455 | offset = kvm_compute_l1_tsc_offset(vcpu, data); |
8171cd68 | 2456 | ns = get_kvmclock_base_ns(); |
f38e098f | 2457 | elapsed = ns - kvm->arch.last_tsc_nsec; |
5d3cb0f6 | 2458 | |
03ba32ca | 2459 | if (vcpu->arch.virtual_tsc_khz) { |
0c899c25 | 2460 | if (data == 0) { |
bd8fab39 DP |
2461 | /* |
2462 | * detection of vcpu initialization -- need to sync | |
2463 | * with other vCPUs. This particularly helps to keep | |
2464 | * kvm_clock stable after CPU hotplug | |
2465 | */ | |
2466 | synchronizing = true; | |
2467 | } else { | |
2468 | u64 tsc_exp = kvm->arch.last_tsc_write + | |
2469 | nsec_to_cycles(vcpu, elapsed); | |
2470 | u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; | |
2471 | /* | |
2472 | * Special case: TSC write with a small delta (1 second) | |
2473 | * of virtual cycle time against real time is | |
2474 | * interpreted as an attempt to synchronize the CPU. | |
2475 | */ | |
2476 | synchronizing = data < tsc_exp + tsc_hz && | |
2477 | data + tsc_hz > tsc_exp; | |
2478 | } | |
c5e8ec8e | 2479 | } |
f38e098f ZA |
2480 | |
2481 | /* | |
5d3cb0f6 ZA |
2482 | * For a reliable TSC, we can match TSC offsets, and for an unstable |
2483 | * TSC, we add elapsed time in this computation. We could let the | |
2484 | * compensation code attempt to catch up if we fall behind, but | |
2485 | * it's better to try to match offsets from the beginning. | |
2486 | */ | |
c5e8ec8e | 2487 | if (synchronizing && |
5d3cb0f6 | 2488 | vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { |
b0c39dc6 | 2489 | if (!kvm_check_tsc_unstable()) { |
e26101b1 | 2490 | offset = kvm->arch.cur_tsc_offset; |
f38e098f | 2491 | } else { |
857e4099 | 2492 | u64 delta = nsec_to_cycles(vcpu, elapsed); |
5d3cb0f6 | 2493 | data += delta; |
9b399dfd | 2494 | offset = kvm_compute_l1_tsc_offset(vcpu, data); |
f38e098f | 2495 | } |
b48aa97e | 2496 | matched = true; |
0d3da0d2 | 2497 | already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); |
e26101b1 ZA |
2498 | } else { |
2499 | /* | |
2500 | * We split periods of matched TSC writes into generations. | |
2501 | * For each generation, we track the original measured | |
2502 | * nanosecond time, offset, and write, so if TSCs are in | |
2503 | * sync, we can match exact offset, and if not, we can match | |
4a969980 | 2504 | * exact software computation in compute_guest_tsc() |
e26101b1 ZA |
2505 | * |
2506 | * These values are tracked in kvm->arch.cur_xxx variables. | |
2507 | */ | |
2508 | kvm->arch.cur_tsc_generation++; | |
2509 | kvm->arch.cur_tsc_nsec = ns; | |
2510 | kvm->arch.cur_tsc_write = data; | |
2511 | kvm->arch.cur_tsc_offset = offset; | |
b48aa97e | 2512 | matched = false; |
f38e098f | 2513 | } |
e26101b1 ZA |
2514 | |
2515 | /* | |
2516 | * We also track th most recent recorded KHZ, write and time to | |
2517 | * allow the matching interval to be extended at each write. | |
2518 | */ | |
f38e098f ZA |
2519 | kvm->arch.last_tsc_nsec = ns; |
2520 | kvm->arch.last_tsc_write = data; | |
5d3cb0f6 | 2521 | kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; |
99e3e30a | 2522 | |
b183aa58 | 2523 | vcpu->arch.last_guest_tsc = data; |
e26101b1 ZA |
2524 | |
2525 | /* Keep track of which generation this VCPU has synchronized to */ | |
2526 | vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; | |
2527 | vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; | |
2528 | vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; | |
2529 | ||
a545ab6a | 2530 | kvm_vcpu_write_tsc_offset(vcpu, offset); |
e26101b1 | 2531 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); |
b48aa97e | 2532 | |
a83829f5 | 2533 | spin_lock_irqsave(&kvm->arch.pvclock_gtod_sync_lock, flags); |
0d3da0d2 | 2534 | if (!matched) { |
b48aa97e | 2535 | kvm->arch.nr_vcpus_matched_tsc = 0; |
0d3da0d2 TG |
2536 | } else if (!already_matched) { |
2537 | kvm->arch.nr_vcpus_matched_tsc++; | |
2538 | } | |
b48aa97e MT |
2539 | |
2540 | kvm_track_tsc_matching(vcpu); | |
a83829f5 | 2541 | spin_unlock_irqrestore(&kvm->arch.pvclock_gtod_sync_lock, flags); |
99e3e30a | 2542 | } |
e26101b1 | 2543 | |
58ea6767 HZ |
2544 | static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, |
2545 | s64 adjustment) | |
2546 | { | |
56ba77a4 | 2547 | u64 tsc_offset = vcpu->arch.l1_tsc_offset; |
326e7425 | 2548 | kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); |
58ea6767 HZ |
2549 | } |
2550 | ||
2551 | static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) | |
2552 | { | |
805d705f | 2553 | if (vcpu->arch.l1_tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) |
58ea6767 | 2554 | WARN_ON(adjustment < 0); |
fe3eb504 IS |
2555 | adjustment = kvm_scale_tsc(vcpu, (u64) adjustment, |
2556 | vcpu->arch.l1_tsc_scaling_ratio); | |
ea26e4ec | 2557 | adjust_tsc_offset_guest(vcpu, adjustment); |
58ea6767 HZ |
2558 | } |
2559 | ||
d828199e MT |
2560 | #ifdef CONFIG_X86_64 |
2561 | ||
a5a1d1c2 | 2562 | static u64 read_tsc(void) |
d828199e | 2563 | { |
a5a1d1c2 | 2564 | u64 ret = (u64)rdtsc_ordered(); |
03b9730b | 2565 | u64 last = pvclock_gtod_data.clock.cycle_last; |
d828199e MT |
2566 | |
2567 | if (likely(ret >= last)) | |
2568 | return ret; | |
2569 | ||
2570 | /* | |
2571 | * GCC likes to generate cmov here, but this branch is extremely | |
6a6256f9 | 2572 | * predictable (it's just a function of time and the likely is |
d828199e MT |
2573 | * very likely) and there's a data dependence, so force GCC |
2574 | * to generate a branch instead. I don't barrier() because | |
2575 | * we don't actually need a barrier, and if this function | |
2576 | * ever gets inlined it will generate worse code. | |
2577 | */ | |
2578 | asm volatile (""); | |
2579 | return last; | |
2580 | } | |
2581 | ||
53fafdbb MT |
2582 | static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, |
2583 | int *mode) | |
d828199e MT |
2584 | { |
2585 | long v; | |
b0c39dc6 VK |
2586 | u64 tsc_pg_val; |
2587 | ||
53fafdbb | 2588 | switch (clock->vclock_mode) { |
b95a8a27 | 2589 | case VDSO_CLOCKMODE_HVCLOCK: |
b0c39dc6 VK |
2590 | tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), |
2591 | tsc_timestamp); | |
2592 | if (tsc_pg_val != U64_MAX) { | |
2593 | /* TSC page valid */ | |
b95a8a27 | 2594 | *mode = VDSO_CLOCKMODE_HVCLOCK; |
53fafdbb MT |
2595 | v = (tsc_pg_val - clock->cycle_last) & |
2596 | clock->mask; | |
b0c39dc6 VK |
2597 | } else { |
2598 | /* TSC page invalid */ | |
b95a8a27 | 2599 | *mode = VDSO_CLOCKMODE_NONE; |
b0c39dc6 VK |
2600 | } |
2601 | break; | |
b95a8a27 TG |
2602 | case VDSO_CLOCKMODE_TSC: |
2603 | *mode = VDSO_CLOCKMODE_TSC; | |
b0c39dc6 | 2604 | *tsc_timestamp = read_tsc(); |
53fafdbb MT |
2605 | v = (*tsc_timestamp - clock->cycle_last) & |
2606 | clock->mask; | |
b0c39dc6 VK |
2607 | break; |
2608 | default: | |
b95a8a27 | 2609 | *mode = VDSO_CLOCKMODE_NONE; |
b0c39dc6 | 2610 | } |
d828199e | 2611 | |
b95a8a27 | 2612 | if (*mode == VDSO_CLOCKMODE_NONE) |
b0c39dc6 | 2613 | *tsc_timestamp = v = 0; |
d828199e | 2614 | |
53fafdbb | 2615 | return v * clock->mult; |
d828199e MT |
2616 | } |
2617 | ||
53fafdbb | 2618 | static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp) |
d828199e | 2619 | { |
cbcf2dd3 | 2620 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; |
d828199e | 2621 | unsigned long seq; |
d828199e | 2622 | int mode; |
cbcf2dd3 | 2623 | u64 ns; |
d828199e | 2624 | |
d828199e MT |
2625 | do { |
2626 | seq = read_seqcount_begin(>od->seq); | |
917f9475 | 2627 | ns = gtod->raw_clock.base_cycles; |
53fafdbb | 2628 | ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode); |
917f9475 PB |
2629 | ns >>= gtod->raw_clock.shift; |
2630 | ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot)); | |
d828199e | 2631 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); |
cbcf2dd3 | 2632 | *t = ns; |
d828199e MT |
2633 | |
2634 | return mode; | |
2635 | } | |
2636 | ||
899a31f5 | 2637 | static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) |
55dd00a7 MT |
2638 | { |
2639 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
2640 | unsigned long seq; | |
2641 | int mode; | |
2642 | u64 ns; | |
2643 | ||
2644 | do { | |
2645 | seq = read_seqcount_begin(>od->seq); | |
55dd00a7 | 2646 | ts->tv_sec = gtod->wall_time_sec; |
917f9475 | 2647 | ns = gtod->clock.base_cycles; |
53fafdbb | 2648 | ns += vgettsc(>od->clock, tsc_timestamp, &mode); |
55dd00a7 MT |
2649 | ns >>= gtod->clock.shift; |
2650 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); | |
2651 | ||
2652 | ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); | |
2653 | ts->tv_nsec = ns; | |
2654 | ||
2655 | return mode; | |
2656 | } | |
2657 | ||
b0c39dc6 VK |
2658 | /* returns true if host is using TSC based clocksource */ |
2659 | static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) | |
d828199e | 2660 | { |
d828199e | 2661 | /* checked again under seqlock below */ |
b0c39dc6 | 2662 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
d828199e MT |
2663 | return false; |
2664 | ||
53fafdbb | 2665 | return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns, |
b0c39dc6 | 2666 | tsc_timestamp)); |
d828199e | 2667 | } |
55dd00a7 | 2668 | |
b0c39dc6 | 2669 | /* returns true if host is using TSC based clocksource */ |
899a31f5 | 2670 | static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, |
b0c39dc6 | 2671 | u64 *tsc_timestamp) |
55dd00a7 MT |
2672 | { |
2673 | /* checked again under seqlock below */ | |
b0c39dc6 | 2674 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
55dd00a7 MT |
2675 | return false; |
2676 | ||
b0c39dc6 | 2677 | return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); |
55dd00a7 | 2678 | } |
d828199e MT |
2679 | #endif |
2680 | ||
2681 | /* | |
2682 | * | |
b48aa97e MT |
2683 | * Assuming a stable TSC across physical CPUS, and a stable TSC |
2684 | * across virtual CPUs, the following condition is possible. | |
2685 | * Each numbered line represents an event visible to both | |
d828199e MT |
2686 | * CPUs at the next numbered event. |
2687 | * | |
2688 | * "timespecX" represents host monotonic time. "tscX" represents | |
2689 | * RDTSC value. | |
2690 | * | |
2691 | * VCPU0 on CPU0 | VCPU1 on CPU1 | |
2692 | * | |
2693 | * 1. read timespec0,tsc0 | |
2694 | * 2. | timespec1 = timespec0 + N | |
2695 | * | tsc1 = tsc0 + M | |
2696 | * 3. transition to guest | transition to guest | |
2697 | * 4. ret0 = timespec0 + (rdtsc - tsc0) | | |
2698 | * 5. | ret1 = timespec1 + (rdtsc - tsc1) | |
2699 | * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) | |
2700 | * | |
2701 | * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: | |
2702 | * | |
2703 | * - ret0 < ret1 | |
2704 | * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) | |
2705 | * ... | |
2706 | * - 0 < N - M => M < N | |
2707 | * | |
2708 | * That is, when timespec0 != timespec1, M < N. Unfortunately that is not | |
2709 | * always the case (the difference between two distinct xtime instances | |
2710 | * might be smaller then the difference between corresponding TSC reads, | |
2711 | * when updating guest vcpus pvclock areas). | |
2712 | * | |
2713 | * To avoid that problem, do not allow visibility of distinct | |
2714 | * system_timestamp/tsc_timestamp values simultaneously: use a master | |
2715 | * copy of host monotonic time values. Update that master copy | |
2716 | * in lockstep. | |
2717 | * | |
b48aa97e | 2718 | * Rely on synchronization of host TSCs and guest TSCs for monotonicity. |
d828199e MT |
2719 | * |
2720 | */ | |
2721 | ||
2722 | static void pvclock_update_vm_gtod_copy(struct kvm *kvm) | |
2723 | { | |
2724 | #ifdef CONFIG_X86_64 | |
2725 | struct kvm_arch *ka = &kvm->arch; | |
2726 | int vclock_mode; | |
b48aa97e MT |
2727 | bool host_tsc_clocksource, vcpus_matched; |
2728 | ||
2729 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
2730 | atomic_read(&kvm->online_vcpus)); | |
d828199e MT |
2731 | |
2732 | /* | |
2733 | * If the host uses TSC clock, then passthrough TSC as stable | |
2734 | * to the guest. | |
2735 | */ | |
b48aa97e | 2736 | host_tsc_clocksource = kvm_get_time_and_clockread( |
d828199e MT |
2737 | &ka->master_kernel_ns, |
2738 | &ka->master_cycle_now); | |
2739 | ||
16a96021 | 2740 | ka->use_master_clock = host_tsc_clocksource && vcpus_matched |
a826faf1 | 2741 | && !ka->backwards_tsc_observed |
54750f2c | 2742 | && !ka->boot_vcpu_runs_old_kvmclock; |
b48aa97e | 2743 | |
d828199e MT |
2744 | if (ka->use_master_clock) |
2745 | atomic_set(&kvm_guest_has_master_clock, 1); | |
2746 | ||
2747 | vclock_mode = pvclock_gtod_data.clock.vclock_mode; | |
b48aa97e MT |
2748 | trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, |
2749 | vcpus_matched); | |
d828199e MT |
2750 | #endif |
2751 | } | |
2752 | ||
2860c4b1 PB |
2753 | void kvm_make_mclock_inprogress_request(struct kvm *kvm) |
2754 | { | |
2755 | kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); | |
2756 | } | |
2757 | ||
2e762ff7 MT |
2758 | static void kvm_gen_update_masterclock(struct kvm *kvm) |
2759 | { | |
2760 | #ifdef CONFIG_X86_64 | |
2761 | int i; | |
2762 | struct kvm_vcpu *vcpu; | |
2763 | struct kvm_arch *ka = &kvm->arch; | |
a83829f5 | 2764 | unsigned long flags; |
2e762ff7 | 2765 | |
e880c6ea VK |
2766 | kvm_hv_invalidate_tsc_page(kvm); |
2767 | ||
2e762ff7 | 2768 | kvm_make_mclock_inprogress_request(kvm); |
c2c647f9 | 2769 | |
2e762ff7 | 2770 | /* no guest entries from this point */ |
a83829f5 | 2771 | spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); |
2e762ff7 | 2772 | pvclock_update_vm_gtod_copy(kvm); |
a83829f5 | 2773 | spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); |
2e762ff7 MT |
2774 | |
2775 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 2776 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
2e762ff7 MT |
2777 | |
2778 | /* guest entries allowed */ | |
2779 | kvm_for_each_vcpu(i, vcpu, kvm) | |
72875d8a | 2780 | kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); |
2e762ff7 MT |
2781 | #endif |
2782 | } | |
2783 | ||
e891a32e | 2784 | u64 get_kvmclock_ns(struct kvm *kvm) |
108b249c | 2785 | { |
108b249c | 2786 | struct kvm_arch *ka = &kvm->arch; |
8b953440 | 2787 | struct pvclock_vcpu_time_info hv_clock; |
a83829f5 | 2788 | unsigned long flags; |
e2c2206a | 2789 | u64 ret; |
108b249c | 2790 | |
a83829f5 | 2791 | spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); |
8b953440 | 2792 | if (!ka->use_master_clock) { |
a83829f5 | 2793 | spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); |
8171cd68 | 2794 | return get_kvmclock_base_ns() + ka->kvmclock_offset; |
108b249c PB |
2795 | } |
2796 | ||
8b953440 PB |
2797 | hv_clock.tsc_timestamp = ka->master_cycle_now; |
2798 | hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; | |
a83829f5 | 2799 | spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); |
8b953440 | 2800 | |
e2c2206a WL |
2801 | /* both __this_cpu_read() and rdtsc() should be on the same cpu */ |
2802 | get_cpu(); | |
2803 | ||
e70b57a6 WL |
2804 | if (__this_cpu_read(cpu_tsc_khz)) { |
2805 | kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, | |
2806 | &hv_clock.tsc_shift, | |
2807 | &hv_clock.tsc_to_system_mul); | |
2808 | ret = __pvclock_read_cycles(&hv_clock, rdtsc()); | |
2809 | } else | |
8171cd68 | 2810 | ret = get_kvmclock_base_ns() + ka->kvmclock_offset; |
e2c2206a WL |
2811 | |
2812 | put_cpu(); | |
2813 | ||
2814 | return ret; | |
108b249c PB |
2815 | } |
2816 | ||
aa096aa0 JM |
2817 | static void kvm_setup_pvclock_page(struct kvm_vcpu *v, |
2818 | struct gfn_to_hva_cache *cache, | |
2819 | unsigned int offset) | |
0d6dd2ff PB |
2820 | { |
2821 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
2822 | struct pvclock_vcpu_time_info guest_hv_clock; | |
2823 | ||
aa096aa0 JM |
2824 | if (unlikely(kvm_read_guest_offset_cached(v->kvm, cache, |
2825 | &guest_hv_clock, offset, sizeof(guest_hv_clock)))) | |
0d6dd2ff PB |
2826 | return; |
2827 | ||
2828 | /* This VCPU is paused, but it's legal for a guest to read another | |
2829 | * VCPU's kvmclock, so we really have to follow the specification where | |
2830 | * it says that version is odd if data is being modified, and even after | |
2831 | * it is consistent. | |
2832 | * | |
2833 | * Version field updates must be kept separate. This is because | |
2834 | * kvm_write_guest_cached might use a "rep movs" instruction, and | |
2835 | * writes within a string instruction are weakly ordered. So there | |
2836 | * are three writes overall. | |
2837 | * | |
2838 | * As a small optimization, only write the version field in the first | |
2839 | * and third write. The vcpu->pv_time cache is still valid, because the | |
2840 | * version field is the first in the struct. | |
2841 | */ | |
2842 | BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); | |
2843 | ||
51c4b8bb LA |
2844 | if (guest_hv_clock.version & 1) |
2845 | ++guest_hv_clock.version; /* first time write, random junk */ | |
2846 | ||
0d6dd2ff | 2847 | vcpu->hv_clock.version = guest_hv_clock.version + 1; |
aa096aa0 JM |
2848 | kvm_write_guest_offset_cached(v->kvm, cache, |
2849 | &vcpu->hv_clock, offset, | |
2850 | sizeof(vcpu->hv_clock.version)); | |
0d6dd2ff PB |
2851 | |
2852 | smp_wmb(); | |
2853 | ||
2854 | /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ | |
2855 | vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); | |
2856 | ||
2857 | if (vcpu->pvclock_set_guest_stopped_request) { | |
2858 | vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; | |
2859 | vcpu->pvclock_set_guest_stopped_request = false; | |
2860 | } | |
2861 | ||
2862 | trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); | |
2863 | ||
aa096aa0 JM |
2864 | kvm_write_guest_offset_cached(v->kvm, cache, |
2865 | &vcpu->hv_clock, offset, | |
2866 | sizeof(vcpu->hv_clock)); | |
0d6dd2ff PB |
2867 | |
2868 | smp_wmb(); | |
2869 | ||
2870 | vcpu->hv_clock.version++; | |
aa096aa0 JM |
2871 | kvm_write_guest_offset_cached(v->kvm, cache, |
2872 | &vcpu->hv_clock, offset, | |
2873 | sizeof(vcpu->hv_clock.version)); | |
0d6dd2ff PB |
2874 | } |
2875 | ||
34c238a1 | 2876 | static int kvm_guest_time_update(struct kvm_vcpu *v) |
18068523 | 2877 | { |
78db6a50 | 2878 | unsigned long flags, tgt_tsc_khz; |
18068523 | 2879 | struct kvm_vcpu_arch *vcpu = &v->arch; |
d828199e | 2880 | struct kvm_arch *ka = &v->kvm->arch; |
f25e656d | 2881 | s64 kernel_ns; |
d828199e | 2882 | u64 tsc_timestamp, host_tsc; |
51d59c6b | 2883 | u8 pvclock_flags; |
d828199e MT |
2884 | bool use_master_clock; |
2885 | ||
2886 | kernel_ns = 0; | |
2887 | host_tsc = 0; | |
18068523 | 2888 | |
d828199e MT |
2889 | /* |
2890 | * If the host uses TSC clock, then passthrough TSC as stable | |
2891 | * to the guest. | |
2892 | */ | |
a83829f5 | 2893 | spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); |
d828199e MT |
2894 | use_master_clock = ka->use_master_clock; |
2895 | if (use_master_clock) { | |
2896 | host_tsc = ka->master_cycle_now; | |
2897 | kernel_ns = ka->master_kernel_ns; | |
2898 | } | |
a83829f5 | 2899 | spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); |
c09664bb MT |
2900 | |
2901 | /* Keep irq disabled to prevent changes to the clock */ | |
2902 | local_irq_save(flags); | |
78db6a50 PB |
2903 | tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); |
2904 | if (unlikely(tgt_tsc_khz == 0)) { | |
c09664bb MT |
2905 | local_irq_restore(flags); |
2906 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); | |
2907 | return 1; | |
2908 | } | |
d828199e | 2909 | if (!use_master_clock) { |
4ea1636b | 2910 | host_tsc = rdtsc(); |
8171cd68 | 2911 | kernel_ns = get_kvmclock_base_ns(); |
d828199e MT |
2912 | } |
2913 | ||
4ba76538 | 2914 | tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); |
d828199e | 2915 | |
c285545f ZA |
2916 | /* |
2917 | * We may have to catch up the TSC to match elapsed wall clock | |
2918 | * time for two reasons, even if kvmclock is used. | |
2919 | * 1) CPU could have been running below the maximum TSC rate | |
2920 | * 2) Broken TSC compensation resets the base at each VCPU | |
2921 | * entry to avoid unknown leaps of TSC even when running | |
2922 | * again on the same CPU. This may cause apparent elapsed | |
2923 | * time to disappear, and the guest to stand still or run | |
2924 | * very slowly. | |
2925 | */ | |
2926 | if (vcpu->tsc_catchup) { | |
2927 | u64 tsc = compute_guest_tsc(v, kernel_ns); | |
2928 | if (tsc > tsc_timestamp) { | |
f1e2b260 | 2929 | adjust_tsc_offset_guest(v, tsc - tsc_timestamp); |
c285545f ZA |
2930 | tsc_timestamp = tsc; |
2931 | } | |
50d0a0f9 GH |
2932 | } |
2933 | ||
18068523 GOC |
2934 | local_irq_restore(flags); |
2935 | ||
0d6dd2ff | 2936 | /* With all the info we got, fill in the values */ |
18068523 | 2937 | |
78db6a50 | 2938 | if (kvm_has_tsc_control) |
fe3eb504 IS |
2939 | tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz, |
2940 | v->arch.l1_tsc_scaling_ratio); | |
78db6a50 PB |
2941 | |
2942 | if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { | |
3ae13faa | 2943 | kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, |
5f4e3f88 ZA |
2944 | &vcpu->hv_clock.tsc_shift, |
2945 | &vcpu->hv_clock.tsc_to_system_mul); | |
78db6a50 | 2946 | vcpu->hw_tsc_khz = tgt_tsc_khz; |
8cfdc000 ZA |
2947 | } |
2948 | ||
1d5f066e | 2949 | vcpu->hv_clock.tsc_timestamp = tsc_timestamp; |
759379dd | 2950 | vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; |
28e4639a | 2951 | vcpu->last_guest_tsc = tsc_timestamp; |
51d59c6b | 2952 | |
d828199e | 2953 | /* If the host uses TSC clocksource, then it is stable */ |
0d6dd2ff | 2954 | pvclock_flags = 0; |
d828199e MT |
2955 | if (use_master_clock) |
2956 | pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; | |
2957 | ||
78c0337a MT |
2958 | vcpu->hv_clock.flags = pvclock_flags; |
2959 | ||
095cf55d | 2960 | if (vcpu->pv_time_enabled) |
aa096aa0 JM |
2961 | kvm_setup_pvclock_page(v, &vcpu->pv_time, 0); |
2962 | if (vcpu->xen.vcpu_info_set) | |
2963 | kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_info_cache, | |
2964 | offsetof(struct compat_vcpu_info, time)); | |
f2340cd9 JM |
2965 | if (vcpu->xen.vcpu_time_info_set) |
2966 | kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_time_info_cache, 0); | |
095cf55d PB |
2967 | if (v == kvm_get_vcpu(v->kvm, 0)) |
2968 | kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); | |
8cfdc000 | 2969 | return 0; |
c8076604 GH |
2970 | } |
2971 | ||
0061d53d MT |
2972 | /* |
2973 | * kvmclock updates which are isolated to a given vcpu, such as | |
2974 | * vcpu->cpu migration, should not allow system_timestamp from | |
2975 | * the rest of the vcpus to remain static. Otherwise ntp frequency | |
2976 | * correction applies to one vcpu's system_timestamp but not | |
2977 | * the others. | |
2978 | * | |
2979 | * So in those cases, request a kvmclock update for all vcpus. | |
7e44e449 AJ |
2980 | * We need to rate-limit these requests though, as they can |
2981 | * considerably slow guests that have a large number of vcpus. | |
2982 | * The time for a remote vcpu to update its kvmclock is bound | |
2983 | * by the delay we use to rate-limit the updates. | |
0061d53d MT |
2984 | */ |
2985 | ||
7e44e449 AJ |
2986 | #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) |
2987 | ||
2988 | static void kvmclock_update_fn(struct work_struct *work) | |
0061d53d MT |
2989 | { |
2990 | int i; | |
7e44e449 AJ |
2991 | struct delayed_work *dwork = to_delayed_work(work); |
2992 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
2993 | kvmclock_update_work); | |
2994 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
0061d53d MT |
2995 | struct kvm_vcpu *vcpu; |
2996 | ||
2997 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
105b21bb | 2998 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0061d53d MT |
2999 | kvm_vcpu_kick(vcpu); |
3000 | } | |
3001 | } | |
3002 | ||
7e44e449 AJ |
3003 | static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) |
3004 | { | |
3005 | struct kvm *kvm = v->kvm; | |
3006 | ||
105b21bb | 3007 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); |
7e44e449 AJ |
3008 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, |
3009 | KVMCLOCK_UPDATE_DELAY); | |
3010 | } | |
3011 | ||
332967a3 AJ |
3012 | #define KVMCLOCK_SYNC_PERIOD (300 * HZ) |
3013 | ||
3014 | static void kvmclock_sync_fn(struct work_struct *work) | |
3015 | { | |
3016 | struct delayed_work *dwork = to_delayed_work(work); | |
3017 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
3018 | kvmclock_sync_work); | |
3019 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
3020 | ||
630994b3 MT |
3021 | if (!kvmclock_periodic_sync) |
3022 | return; | |
3023 | ||
332967a3 AJ |
3024 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); |
3025 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
3026 | KVMCLOCK_SYNC_PERIOD); | |
3027 | } | |
3028 | ||
191c8137 BP |
3029 | /* |
3030 | * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. | |
3031 | */ | |
3032 | static bool can_set_mci_status(struct kvm_vcpu *vcpu) | |
3033 | { | |
3034 | /* McStatusWrEn enabled? */ | |
23493d0a | 3035 | if (guest_cpuid_is_amd_or_hygon(vcpu)) |
191c8137 BP |
3036 | return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); |
3037 | ||
3038 | return false; | |
3039 | } | |
3040 | ||
9ffd986c | 3041 | static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 3042 | { |
890ca9ae HY |
3043 | u64 mcg_cap = vcpu->arch.mcg_cap; |
3044 | unsigned bank_num = mcg_cap & 0xff; | |
9ffd986c WL |
3045 | u32 msr = msr_info->index; |
3046 | u64 data = msr_info->data; | |
890ca9ae | 3047 | |
15c4a640 | 3048 | switch (msr) { |
15c4a640 | 3049 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 3050 | vcpu->arch.mcg_status = data; |
15c4a640 | 3051 | break; |
c7ac679c | 3052 | case MSR_IA32_MCG_CTL: |
44883f01 PB |
3053 | if (!(mcg_cap & MCG_CTL_P) && |
3054 | (data || !msr_info->host_initiated)) | |
890ca9ae HY |
3055 | return 1; |
3056 | if (data != 0 && data != ~(u64)0) | |
44883f01 | 3057 | return 1; |
890ca9ae HY |
3058 | vcpu->arch.mcg_ctl = data; |
3059 | break; | |
3060 | default: | |
3061 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 3062 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
6ec4c5ee MP |
3063 | u32 offset = array_index_nospec( |
3064 | msr - MSR_IA32_MC0_CTL, | |
3065 | MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); | |
3066 | ||
114be429 AP |
3067 | /* only 0 or all 1s can be written to IA32_MCi_CTL |
3068 | * some Linux kernels though clear bit 10 in bank 4 to | |
3069 | * workaround a BIOS/GART TBL issue on AMD K8s, ignore | |
3070 | * this to avoid an uncatched #GP in the guest | |
3071 | */ | |
890ca9ae | 3072 | if ((offset & 0x3) == 0 && |
114be429 | 3073 | data != 0 && (data | (1 << 10)) != ~(u64)0) |
890ca9ae | 3074 | return -1; |
191c8137 BP |
3075 | |
3076 | /* MCi_STATUS */ | |
9ffd986c | 3077 | if (!msr_info->host_initiated && |
191c8137 BP |
3078 | (offset & 0x3) == 1 && data != 0) { |
3079 | if (!can_set_mci_status(vcpu)) | |
3080 | return -1; | |
3081 | } | |
3082 | ||
890ca9ae HY |
3083 | vcpu->arch.mce_banks[offset] = data; |
3084 | break; | |
3085 | } | |
3086 | return 1; | |
3087 | } | |
3088 | return 0; | |
3089 | } | |
3090 | ||
2635b5c4 VK |
3091 | static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu) |
3092 | { | |
3093 | u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT; | |
3094 | ||
3095 | return (vcpu->arch.apf.msr_en_val & mask) == mask; | |
3096 | } | |
3097 | ||
344d9588 GN |
3098 | static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) |
3099 | { | |
3100 | gpa_t gpa = data & ~0x3f; | |
3101 | ||
2635b5c4 VK |
3102 | /* Bits 4:5 are reserved, Should be zero */ |
3103 | if (data & 0x30) | |
344d9588 GN |
3104 | return 1; |
3105 | ||
66570e96 OU |
3106 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) && |
3107 | (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT)) | |
3108 | return 1; | |
3109 | ||
3110 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) && | |
3111 | (data & KVM_ASYNC_PF_DELIVERY_AS_INT)) | |
3112 | return 1; | |
3113 | ||
9d3c447c | 3114 | if (!lapic_in_kernel(vcpu)) |
d831de17 | 3115 | return data ? 1 : 0; |
9d3c447c | 3116 | |
2635b5c4 | 3117 | vcpu->arch.apf.msr_en_val = data; |
344d9588 | 3118 | |
2635b5c4 | 3119 | if (!kvm_pv_async_pf_enabled(vcpu)) { |
344d9588 GN |
3120 | kvm_clear_async_pf_completion_queue(vcpu); |
3121 | kvm_async_pf_hash_reset(vcpu); | |
3122 | return 0; | |
3123 | } | |
3124 | ||
4e335d9e | 3125 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, |
68fd66f1 | 3126 | sizeof(u64))) |
344d9588 GN |
3127 | return 1; |
3128 | ||
6adba527 | 3129 | vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); |
52a5c155 | 3130 | vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; |
2635b5c4 | 3131 | |
344d9588 | 3132 | kvm_async_pf_wakeup_all(vcpu); |
2635b5c4 VK |
3133 | |
3134 | return 0; | |
3135 | } | |
3136 | ||
3137 | static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data) | |
3138 | { | |
3139 | /* Bits 8-63 are reserved */ | |
3140 | if (data >> 8) | |
3141 | return 1; | |
3142 | ||
3143 | if (!lapic_in_kernel(vcpu)) | |
3144 | return 1; | |
3145 | ||
3146 | vcpu->arch.apf.msr_int_val = data; | |
3147 | ||
3148 | vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK; | |
3149 | ||
344d9588 GN |
3150 | return 0; |
3151 | } | |
3152 | ||
12f9a48f GC |
3153 | static void kvmclock_reset(struct kvm_vcpu *vcpu) |
3154 | { | |
0b79459b | 3155 | vcpu->arch.pv_time_enabled = false; |
49dedf0d | 3156 | vcpu->arch.time = 0; |
12f9a48f GC |
3157 | } |
3158 | ||
7780938c | 3159 | static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu) |
f38a7b75 WL |
3160 | { |
3161 | ++vcpu->stat.tlb_flush; | |
b3646477 | 3162 | static_call(kvm_x86_tlb_flush_all)(vcpu); |
f38a7b75 WL |
3163 | } |
3164 | ||
0baedd79 VK |
3165 | static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu) |
3166 | { | |
3167 | ++vcpu->stat.tlb_flush; | |
b53e84ee LJ |
3168 | |
3169 | if (!tdp_enabled) { | |
3170 | /* | |
3171 | * A TLB flush on behalf of the guest is equivalent to | |
3172 | * INVPCID(all), toggling CR4.PGE, etc., which requires | |
3173 | * a forced sync of the shadow page tables. Unload the | |
3174 | * entire MMU here and the subsequent load will sync the | |
3175 | * shadow page tables, and also flush the TLB. | |
3176 | */ | |
3177 | kvm_mmu_unload(vcpu); | |
3178 | return; | |
3179 | } | |
3180 | ||
b3646477 | 3181 | static_call(kvm_x86_tlb_flush_guest)(vcpu); |
0baedd79 VK |
3182 | } |
3183 | ||
c9aaa895 GC |
3184 | static void record_steal_time(struct kvm_vcpu *vcpu) |
3185 | { | |
b0431382 BO |
3186 | struct kvm_host_map map; |
3187 | struct kvm_steal_time *st; | |
3188 | ||
30b5c851 DW |
3189 | if (kvm_xen_msr_enabled(vcpu->kvm)) { |
3190 | kvm_xen_runstate_set_running(vcpu); | |
3191 | return; | |
3192 | } | |
3193 | ||
c9aaa895 GC |
3194 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) |
3195 | return; | |
3196 | ||
b0431382 BO |
3197 | /* -EAGAIN is returned in atomic context so we can just return. */ |
3198 | if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, | |
3199 | &map, &vcpu->arch.st.cache, false)) | |
c9aaa895 GC |
3200 | return; |
3201 | ||
b0431382 BO |
3202 | st = map.hva + |
3203 | offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); | |
3204 | ||
f38a7b75 WL |
3205 | /* |
3206 | * Doing a TLB flush here, on the guest's behalf, can avoid | |
3207 | * expensive IPIs. | |
3208 | */ | |
66570e96 | 3209 | if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) { |
af3511ff LJ |
3210 | u8 st_preempted = xchg(&st->preempted, 0); |
3211 | ||
66570e96 | 3212 | trace_kvm_pv_tlb_flush(vcpu->vcpu_id, |
af3511ff LJ |
3213 | st_preempted & KVM_VCPU_FLUSH_TLB); |
3214 | if (st_preempted & KVM_VCPU_FLUSH_TLB) | |
66570e96 | 3215 | kvm_vcpu_flush_tlb_guest(vcpu); |
1eff0ada WL |
3216 | } else { |
3217 | st->preempted = 0; | |
66570e96 | 3218 | } |
0b9f6c46 | 3219 | |
a6bd811f | 3220 | vcpu->arch.st.preempted = 0; |
35f3fae1 | 3221 | |
b0431382 BO |
3222 | if (st->version & 1) |
3223 | st->version += 1; /* first time write, random junk */ | |
35f3fae1 | 3224 | |
b0431382 | 3225 | st->version += 1; |
35f3fae1 WL |
3226 | |
3227 | smp_wmb(); | |
3228 | ||
b0431382 | 3229 | st->steal += current->sched_info.run_delay - |
c54cdf14 LC |
3230 | vcpu->arch.st.last_steal; |
3231 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
35f3fae1 | 3232 | |
35f3fae1 WL |
3233 | smp_wmb(); |
3234 | ||
b0431382 | 3235 | st->version += 1; |
c9aaa895 | 3236 | |
b0431382 | 3237 | kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false); |
c9aaa895 GC |
3238 | } |
3239 | ||
8fe8ab46 | 3240 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 3241 | { |
5753785f | 3242 | bool pr = false; |
8fe8ab46 WA |
3243 | u32 msr = msr_info->index; |
3244 | u64 data = msr_info->data; | |
5753785f | 3245 | |
1232f8e6 | 3246 | if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr) |
23200b7a | 3247 | return kvm_xen_write_hypercall_page(vcpu, data); |
1232f8e6 | 3248 | |
15c4a640 | 3249 | switch (msr) { |
2e32b719 | 3250 | case MSR_AMD64_NB_CFG: |
2e32b719 BP |
3251 | case MSR_IA32_UCODE_WRITE: |
3252 | case MSR_VM_HSAVE_PA: | |
3253 | case MSR_AMD64_PATCH_LOADER: | |
3254 | case MSR_AMD64_BU_CFG2: | |
405a353a | 3255 | case MSR_AMD64_DC_CFG: |
0e1b869f | 3256 | case MSR_F15H_EX_CFG: |
2e32b719 BP |
3257 | break; |
3258 | ||
518e7b94 WL |
3259 | case MSR_IA32_UCODE_REV: |
3260 | if (msr_info->host_initiated) | |
3261 | vcpu->arch.microcode_version = data; | |
3262 | break; | |
0cf9135b SC |
3263 | case MSR_IA32_ARCH_CAPABILITIES: |
3264 | if (!msr_info->host_initiated) | |
3265 | return 1; | |
3266 | vcpu->arch.arch_capabilities = data; | |
3267 | break; | |
d574c539 VK |
3268 | case MSR_IA32_PERF_CAPABILITIES: { |
3269 | struct kvm_msr_entry msr_ent = {.index = msr, .data = 0}; | |
3270 | ||
3271 | if (!msr_info->host_initiated) | |
3272 | return 1; | |
3273 | if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM) && kvm_get_msr_feature(&msr_ent)) | |
3274 | return 1; | |
3275 | if (data & ~msr_ent.data) | |
3276 | return 1; | |
3277 | ||
3278 | vcpu->arch.perf_capabilities = data; | |
3279 | ||
3280 | return 0; | |
3281 | } | |
15c4a640 | 3282 | case MSR_EFER: |
11988499 | 3283 | return set_efer(vcpu, msr_info); |
8f1589d9 AP |
3284 | case MSR_K7_HWCR: |
3285 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
82494028 | 3286 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ |
a223c313 | 3287 | data &= ~(u64)0x8; /* ignore TLB cache disable */ |
191c8137 BP |
3288 | |
3289 | /* Handle McStatusWrEn */ | |
3290 | if (data == BIT_ULL(18)) { | |
3291 | vcpu->arch.msr_hwcr = data; | |
3292 | } else if (data != 0) { | |
a737f256 CD |
3293 | vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", |
3294 | data); | |
8f1589d9 AP |
3295 | return 1; |
3296 | } | |
15c4a640 | 3297 | break; |
f7c6d140 AP |
3298 | case MSR_FAM10H_MMIO_CONF_BASE: |
3299 | if (data != 0) { | |
a737f256 CD |
3300 | vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " |
3301 | "0x%llx\n", data); | |
f7c6d140 AP |
3302 | return 1; |
3303 | } | |
15c4a640 | 3304 | break; |
9ba075a6 | 3305 | case 0x200 ... 0x2ff: |
ff53604b | 3306 | return kvm_mtrr_set_msr(vcpu, msr, data); |
15c4a640 | 3307 | case MSR_IA32_APICBASE: |
58cb628d | 3308 | return kvm_set_apic_base(vcpu, msr_info); |
bf10bd0b | 3309 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: |
0105d1a5 | 3310 | return kvm_x2apic_msr_write(vcpu, msr, data); |
09141ec0 | 3311 | case MSR_IA32_TSC_DEADLINE: |
a3e06bbe LJ |
3312 | kvm_set_lapic_tscdeadline_msr(vcpu, data); |
3313 | break; | |
ba904635 | 3314 | case MSR_IA32_TSC_ADJUST: |
d6321d49 | 3315 | if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { |
ba904635 | 3316 | if (!msr_info->host_initiated) { |
d913b904 | 3317 | s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; |
d7add054 | 3318 | adjust_tsc_offset_guest(vcpu, adj); |
ba904635 WA |
3319 | } |
3320 | vcpu->arch.ia32_tsc_adjust_msr = data; | |
3321 | } | |
3322 | break; | |
15c4a640 | 3323 | case MSR_IA32_MISC_ENABLE: |
511a8556 WL |
3324 | if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && |
3325 | ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { | |
3326 | if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) | |
3327 | return 1; | |
3328 | vcpu->arch.ia32_misc_enable_msr = data; | |
aedbaf4f | 3329 | kvm_update_cpuid_runtime(vcpu); |
511a8556 WL |
3330 | } else { |
3331 | vcpu->arch.ia32_misc_enable_msr = data; | |
3332 | } | |
15c4a640 | 3333 | break; |
64d60670 PB |
3334 | case MSR_IA32_SMBASE: |
3335 | if (!msr_info->host_initiated) | |
3336 | return 1; | |
3337 | vcpu->arch.smbase = data; | |
3338 | break; | |
73f624f4 PB |
3339 | case MSR_IA32_POWER_CTL: |
3340 | vcpu->arch.msr_ia32_power_ctl = data; | |
3341 | break; | |
dd259935 | 3342 | case MSR_IA32_TSC: |
0c899c25 PB |
3343 | if (msr_info->host_initiated) { |
3344 | kvm_synchronize_tsc(vcpu, data); | |
3345 | } else { | |
9b399dfd | 3346 | u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset; |
0c899c25 PB |
3347 | adjust_tsc_offset_guest(vcpu, adj); |
3348 | vcpu->arch.ia32_tsc_adjust_msr += adj; | |
3349 | } | |
dd259935 | 3350 | break; |
864e2ab2 AL |
3351 | case MSR_IA32_XSS: |
3352 | if (!msr_info->host_initiated && | |
3353 | !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) | |
3354 | return 1; | |
3355 | /* | |
a1bead2a SC |
3356 | * KVM supports exposing PT to the guest, but does not support |
3357 | * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than | |
3358 | * XSAVES/XRSTORS to save/restore PT MSRs. | |
864e2ab2 | 3359 | */ |
408e9a31 | 3360 | if (data & ~supported_xss) |
864e2ab2 AL |
3361 | return 1; |
3362 | vcpu->arch.ia32_xss = data; | |
3363 | break; | |
52797bf9 LA |
3364 | case MSR_SMI_COUNT: |
3365 | if (!msr_info->host_initiated) | |
3366 | return 1; | |
3367 | vcpu->arch.smi_count = data; | |
3368 | break; | |
11c6bffa | 3369 | case MSR_KVM_WALL_CLOCK_NEW: |
66570e96 OU |
3370 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3371 | return 1; | |
3372 | ||
629b5348 JM |
3373 | vcpu->kvm->arch.wall_clock = data; |
3374 | kvm_write_wall_clock(vcpu->kvm, data, 0); | |
66570e96 | 3375 | break; |
18068523 | 3376 | case MSR_KVM_WALL_CLOCK: |
66570e96 OU |
3377 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3378 | return 1; | |
3379 | ||
629b5348 JM |
3380 | vcpu->kvm->arch.wall_clock = data; |
3381 | kvm_write_wall_clock(vcpu->kvm, data, 0); | |
18068523 | 3382 | break; |
11c6bffa | 3383 | case MSR_KVM_SYSTEM_TIME_NEW: |
66570e96 OU |
3384 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3385 | return 1; | |
3386 | ||
5b9bb0eb OU |
3387 | kvm_write_system_time(vcpu, data, false, msr_info->host_initiated); |
3388 | break; | |
3389 | case MSR_KVM_SYSTEM_TIME: | |
66570e96 OU |
3390 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3391 | return 1; | |
3392 | ||
3393 | kvm_write_system_time(vcpu, data, true, msr_info->host_initiated); | |
18068523 | 3394 | break; |
344d9588 | 3395 | case MSR_KVM_ASYNC_PF_EN: |
66570e96 OU |
3396 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3397 | return 1; | |
3398 | ||
344d9588 GN |
3399 | if (kvm_pv_enable_async_pf(vcpu, data)) |
3400 | return 1; | |
3401 | break; | |
2635b5c4 | 3402 | case MSR_KVM_ASYNC_PF_INT: |
66570e96 OU |
3403 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
3404 | return 1; | |
3405 | ||
2635b5c4 VK |
3406 | if (kvm_pv_enable_async_pf_int(vcpu, data)) |
3407 | return 1; | |
3408 | break; | |
557a961a | 3409 | case MSR_KVM_ASYNC_PF_ACK: |
0a31df68 | 3410 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
66570e96 | 3411 | return 1; |
557a961a VK |
3412 | if (data & 0x1) { |
3413 | vcpu->arch.apf.pageready_pending = false; | |
3414 | kvm_check_async_pf_completion(vcpu); | |
3415 | } | |
3416 | break; | |
c9aaa895 | 3417 | case MSR_KVM_STEAL_TIME: |
66570e96 OU |
3418 | if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) |
3419 | return 1; | |
c9aaa895 GC |
3420 | |
3421 | if (unlikely(!sched_info_on())) | |
3422 | return 1; | |
3423 | ||
3424 | if (data & KVM_STEAL_RESERVED_MASK) | |
3425 | return 1; | |
3426 | ||
c9aaa895 GC |
3427 | vcpu->arch.st.msr_val = data; |
3428 | ||
3429 | if (!(data & KVM_MSR_ENABLED)) | |
3430 | break; | |
3431 | ||
c9aaa895 GC |
3432 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
3433 | ||
3434 | break; | |
ae7a2a3f | 3435 | case MSR_KVM_PV_EOI_EN: |
66570e96 OU |
3436 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) |
3437 | return 1; | |
3438 | ||
72bbf935 | 3439 | if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8))) |
ae7a2a3f MT |
3440 | return 1; |
3441 | break; | |
c9aaa895 | 3442 | |
2d5ba19b | 3443 | case MSR_KVM_POLL_CONTROL: |
66570e96 OU |
3444 | if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) |
3445 | return 1; | |
3446 | ||
2d5ba19b MT |
3447 | /* only enable bit supported */ |
3448 | if (data & (-1ULL << 1)) | |
3449 | return 1; | |
3450 | ||
3451 | vcpu->arch.msr_kvm_poll_control = data; | |
3452 | break; | |
3453 | ||
890ca9ae HY |
3454 | case MSR_IA32_MCG_CTL: |
3455 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 3456 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
9ffd986c | 3457 | return set_msr_mce(vcpu, msr_info); |
71db6023 | 3458 | |
6912ac32 WH |
3459 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: |
3460 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
df561f66 GS |
3461 | pr = true; |
3462 | fallthrough; | |
6912ac32 WH |
3463 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: |
3464 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 3465 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 3466 | return kvm_pmu_set_msr(vcpu, msr_info); |
5753785f GN |
3467 | |
3468 | if (pr || data != 0) | |
a737f256 CD |
3469 | vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " |
3470 | "0x%x data 0x%llx\n", msr, data); | |
5753785f | 3471 | break; |
84e0cefa JS |
3472 | case MSR_K7_CLK_CTL: |
3473 | /* | |
3474 | * Ignore all writes to this no longer documented MSR. | |
3475 | * Writes are only relevant for old K7 processors, | |
3476 | * all pre-dating SVM, but a recommended workaround from | |
4a969980 | 3477 | * AMD for these chips. It is possible to specify the |
84e0cefa JS |
3478 | * affected processor models on the command line, hence |
3479 | * the need to ignore the workaround. | |
3480 | */ | |
3481 | break; | |
55cd8e5a | 3482 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
f97f5a56 JD |
3483 | case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: |
3484 | case HV_X64_MSR_SYNDBG_OPTIONS: | |
e7d9513b AS |
3485 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
3486 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 3487 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
3488 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
3489 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
3490 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
e7d9513b AS |
3491 | return kvm_hv_set_msr_common(vcpu, msr, data, |
3492 | msr_info->host_initiated); | |
91c9c3ed | 3493 | case MSR_IA32_BBL_CR_CTL3: |
3494 | /* Drop writes to this legacy MSR -- see rdmsr | |
3495 | * counterpart for further detail. | |
3496 | */ | |
fab0aa3b EM |
3497 | if (report_ignored_msrs) |
3498 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", | |
3499 | msr, data); | |
91c9c3ed | 3500 | break; |
2b036c6b | 3501 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 3502 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
3503 | return 1; |
3504 | vcpu->arch.osvw.length = data; | |
3505 | break; | |
3506 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 3507 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
3508 | return 1; |
3509 | vcpu->arch.osvw.status = data; | |
3510 | break; | |
db2336a8 KH |
3511 | case MSR_PLATFORM_INFO: |
3512 | if (!msr_info->host_initiated || | |
db2336a8 KH |
3513 | (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && |
3514 | cpuid_fault_enabled(vcpu))) | |
3515 | return 1; | |
3516 | vcpu->arch.msr_platform_info = data; | |
3517 | break; | |
3518 | case MSR_MISC_FEATURES_ENABLES: | |
3519 | if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || | |
3520 | (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && | |
3521 | !supports_cpuid_fault(vcpu))) | |
3522 | return 1; | |
3523 | vcpu->arch.msr_misc_features_enables = data; | |
3524 | break; | |
15c4a640 | 3525 | default: |
c6702c9d | 3526 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 3527 | return kvm_pmu_set_msr(vcpu, msr_info); |
6abe9c13 | 3528 | return KVM_MSR_RET_INVALID; |
15c4a640 CO |
3529 | } |
3530 | return 0; | |
3531 | } | |
3532 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
3533 | ||
44883f01 | 3534 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) |
15c4a640 CO |
3535 | { |
3536 | u64 data; | |
890ca9ae HY |
3537 | u64 mcg_cap = vcpu->arch.mcg_cap; |
3538 | unsigned bank_num = mcg_cap & 0xff; | |
15c4a640 CO |
3539 | |
3540 | switch (msr) { | |
15c4a640 CO |
3541 | case MSR_IA32_P5_MC_ADDR: |
3542 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
3543 | data = 0; |
3544 | break; | |
15c4a640 | 3545 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
3546 | data = vcpu->arch.mcg_cap; |
3547 | break; | |
c7ac679c | 3548 | case MSR_IA32_MCG_CTL: |
44883f01 | 3549 | if (!(mcg_cap & MCG_CTL_P) && !host) |
890ca9ae HY |
3550 | return 1; |
3551 | data = vcpu->arch.mcg_ctl; | |
3552 | break; | |
3553 | case MSR_IA32_MCG_STATUS: | |
3554 | data = vcpu->arch.mcg_status; | |
3555 | break; | |
3556 | default: | |
3557 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 3558 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
6ec4c5ee MP |
3559 | u32 offset = array_index_nospec( |
3560 | msr - MSR_IA32_MC0_CTL, | |
3561 | MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); | |
3562 | ||
890ca9ae HY |
3563 | data = vcpu->arch.mce_banks[offset]; |
3564 | break; | |
3565 | } | |
3566 | return 1; | |
3567 | } | |
3568 | *pdata = data; | |
3569 | return 0; | |
3570 | } | |
3571 | ||
609e36d3 | 3572 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
890ca9ae | 3573 | { |
609e36d3 | 3574 | switch (msr_info->index) { |
890ca9ae | 3575 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 3576 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
3577 | case MSR_IA32_LASTBRANCHFROMIP: |
3578 | case MSR_IA32_LASTBRANCHTOIP: | |
3579 | case MSR_IA32_LASTINTFROMIP: | |
3580 | case MSR_IA32_LASTINTTOIP: | |
059e5c32 | 3581 | case MSR_AMD64_SYSCFG: |
3afb1121 PB |
3582 | case MSR_K8_TSEG_ADDR: |
3583 | case MSR_K8_TSEG_MASK: | |
61a6bd67 | 3584 | case MSR_VM_HSAVE_PA: |
1fdbd48c | 3585 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 3586 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 3587 | case MSR_FAM10H_MMIO_CONF_BASE: |
2e32b719 | 3588 | case MSR_AMD64_BU_CFG2: |
0c2df2a1 | 3589 | case MSR_IA32_PERF_CTL: |
405a353a | 3590 | case MSR_AMD64_DC_CFG: |
0e1b869f | 3591 | case MSR_F15H_EX_CFG: |
2ca1a06a VS |
3592 | /* |
3593 | * Intel Sandy Bridge CPUs must support the RAPL (running average power | |
3594 | * limit) MSRs. Just return 0, as we do not want to expose the host | |
3595 | * data here. Do not conditionalize this on CPUID, as KVM does not do | |
3596 | * so for existing CPU-specific MSRs. | |
3597 | */ | |
3598 | case MSR_RAPL_POWER_UNIT: | |
3599 | case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */ | |
3600 | case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */ | |
3601 | case MSR_PKG_ENERGY_STATUS: /* Total package */ | |
3602 | case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */ | |
609e36d3 | 3603 | msr_info->data = 0; |
15c4a640 | 3604 | break; |
c51eb52b | 3605 | case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: |
c28fa560 VK |
3606 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
3607 | return kvm_pmu_get_msr(vcpu, msr_info); | |
3608 | if (!msr_info->host_initiated) | |
3609 | return 1; | |
3610 | msr_info->data = 0; | |
3611 | break; | |
6912ac32 WH |
3612 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: |
3613 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: | |
3614 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
3615 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 3616 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
cbd71758 | 3617 | return kvm_pmu_get_msr(vcpu, msr_info); |
609e36d3 | 3618 | msr_info->data = 0; |
5753785f | 3619 | break; |
742bc670 | 3620 | case MSR_IA32_UCODE_REV: |
518e7b94 | 3621 | msr_info->data = vcpu->arch.microcode_version; |
742bc670 | 3622 | break; |
0cf9135b SC |
3623 | case MSR_IA32_ARCH_CAPABILITIES: |
3624 | if (!msr_info->host_initiated && | |
3625 | !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) | |
3626 | return 1; | |
3627 | msr_info->data = vcpu->arch.arch_capabilities; | |
3628 | break; | |
d574c539 VK |
3629 | case MSR_IA32_PERF_CAPABILITIES: |
3630 | if (!msr_info->host_initiated && | |
3631 | !guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) | |
3632 | return 1; | |
3633 | msr_info->data = vcpu->arch.perf_capabilities; | |
3634 | break; | |
73f624f4 PB |
3635 | case MSR_IA32_POWER_CTL: |
3636 | msr_info->data = vcpu->arch.msr_ia32_power_ctl; | |
3637 | break; | |
cc5b54dd ML |
3638 | case MSR_IA32_TSC: { |
3639 | /* | |
3640 | * Intel SDM states that MSR_IA32_TSC read adds the TSC offset | |
3641 | * even when not intercepted. AMD manual doesn't explicitly | |
3642 | * state this but appears to behave the same. | |
3643 | * | |
ee6fa053 | 3644 | * On userspace reads and writes, however, we unconditionally |
c0623f5e | 3645 | * return L1's TSC value to ensure backwards-compatible |
ee6fa053 | 3646 | * behavior for migration. |
cc5b54dd | 3647 | */ |
fe3eb504 | 3648 | u64 offset, ratio; |
cc5b54dd | 3649 | |
fe3eb504 IS |
3650 | if (msr_info->host_initiated) { |
3651 | offset = vcpu->arch.l1_tsc_offset; | |
3652 | ratio = vcpu->arch.l1_tsc_scaling_ratio; | |
3653 | } else { | |
3654 | offset = vcpu->arch.tsc_offset; | |
3655 | ratio = vcpu->arch.tsc_scaling_ratio; | |
3656 | } | |
3657 | ||
3658 | msr_info->data = kvm_scale_tsc(vcpu, rdtsc(), ratio) + offset; | |
dd259935 | 3659 | break; |
cc5b54dd | 3660 | } |
9ba075a6 | 3661 | case MSR_MTRRcap: |
9ba075a6 | 3662 | case 0x200 ... 0x2ff: |
ff53604b | 3663 | return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); |
15c4a640 | 3664 | case 0xcd: /* fsb frequency */ |
609e36d3 | 3665 | msr_info->data = 3; |
15c4a640 | 3666 | break; |
7b914098 JS |
3667 | /* |
3668 | * MSR_EBC_FREQUENCY_ID | |
3669 | * Conservative value valid for even the basic CPU models. | |
3670 | * Models 0,1: 000 in bits 23:21 indicating a bus speed of | |
3671 | * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, | |
3672 | * and 266MHz for model 3, or 4. Set Core Clock | |
3673 | * Frequency to System Bus Frequency Ratio to 1 (bits | |
3674 | * 31:24) even though these are only valid for CPU | |
3675 | * models > 2, however guests may end up dividing or | |
3676 | * multiplying by zero otherwise. | |
3677 | */ | |
3678 | case MSR_EBC_FREQUENCY_ID: | |
609e36d3 | 3679 | msr_info->data = 1 << 24; |
7b914098 | 3680 | break; |
15c4a640 | 3681 | case MSR_IA32_APICBASE: |
609e36d3 | 3682 | msr_info->data = kvm_get_apic_base(vcpu); |
15c4a640 | 3683 | break; |
bf10bd0b | 3684 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: |
609e36d3 | 3685 | return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); |
09141ec0 | 3686 | case MSR_IA32_TSC_DEADLINE: |
609e36d3 | 3687 | msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); |
a3e06bbe | 3688 | break; |
ba904635 | 3689 | case MSR_IA32_TSC_ADJUST: |
609e36d3 | 3690 | msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; |
ba904635 | 3691 | break; |
15c4a640 | 3692 | case MSR_IA32_MISC_ENABLE: |
609e36d3 | 3693 | msr_info->data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 3694 | break; |
64d60670 PB |
3695 | case MSR_IA32_SMBASE: |
3696 | if (!msr_info->host_initiated) | |
3697 | return 1; | |
3698 | msr_info->data = vcpu->arch.smbase; | |
15c4a640 | 3699 | break; |
52797bf9 LA |
3700 | case MSR_SMI_COUNT: |
3701 | msr_info->data = vcpu->arch.smi_count; | |
3702 | break; | |
847f0ad8 AG |
3703 | case MSR_IA32_PERF_STATUS: |
3704 | /* TSC increment by tick */ | |
609e36d3 | 3705 | msr_info->data = 1000ULL; |
847f0ad8 | 3706 | /* CPU multiplier */ |
b0996ae4 | 3707 | msr_info->data |= (((uint64_t)4ULL) << 40); |
847f0ad8 | 3708 | break; |
15c4a640 | 3709 | case MSR_EFER: |
609e36d3 | 3710 | msr_info->data = vcpu->arch.efer; |
15c4a640 | 3711 | break; |
18068523 | 3712 | case MSR_KVM_WALL_CLOCK: |
1930e5dd OU |
3713 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3714 | return 1; | |
3715 | ||
3716 | msr_info->data = vcpu->kvm->arch.wall_clock; | |
3717 | break; | |
11c6bffa | 3718 | case MSR_KVM_WALL_CLOCK_NEW: |
1930e5dd OU |
3719 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3720 | return 1; | |
3721 | ||
609e36d3 | 3722 | msr_info->data = vcpu->kvm->arch.wall_clock; |
18068523 GOC |
3723 | break; |
3724 | case MSR_KVM_SYSTEM_TIME: | |
1930e5dd OU |
3725 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3726 | return 1; | |
3727 | ||
3728 | msr_info->data = vcpu->arch.time; | |
3729 | break; | |
11c6bffa | 3730 | case MSR_KVM_SYSTEM_TIME_NEW: |
1930e5dd OU |
3731 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3732 | return 1; | |
3733 | ||
609e36d3 | 3734 | msr_info->data = vcpu->arch.time; |
18068523 | 3735 | break; |
344d9588 | 3736 | case MSR_KVM_ASYNC_PF_EN: |
1930e5dd OU |
3737 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3738 | return 1; | |
3739 | ||
2635b5c4 VK |
3740 | msr_info->data = vcpu->arch.apf.msr_en_val; |
3741 | break; | |
3742 | case MSR_KVM_ASYNC_PF_INT: | |
1930e5dd OU |
3743 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
3744 | return 1; | |
3745 | ||
2635b5c4 | 3746 | msr_info->data = vcpu->arch.apf.msr_int_val; |
344d9588 | 3747 | break; |
557a961a | 3748 | case MSR_KVM_ASYNC_PF_ACK: |
0a31df68 | 3749 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
1930e5dd OU |
3750 | return 1; |
3751 | ||
557a961a VK |
3752 | msr_info->data = 0; |
3753 | break; | |
c9aaa895 | 3754 | case MSR_KVM_STEAL_TIME: |
1930e5dd OU |
3755 | if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) |
3756 | return 1; | |
3757 | ||
609e36d3 | 3758 | msr_info->data = vcpu->arch.st.msr_val; |
c9aaa895 | 3759 | break; |
1d92128f | 3760 | case MSR_KVM_PV_EOI_EN: |
1930e5dd OU |
3761 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) |
3762 | return 1; | |
3763 | ||
609e36d3 | 3764 | msr_info->data = vcpu->arch.pv_eoi.msr_val; |
1d92128f | 3765 | break; |
2d5ba19b | 3766 | case MSR_KVM_POLL_CONTROL: |
1930e5dd OU |
3767 | if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) |
3768 | return 1; | |
3769 | ||
2d5ba19b MT |
3770 | msr_info->data = vcpu->arch.msr_kvm_poll_control; |
3771 | break; | |
890ca9ae HY |
3772 | case MSR_IA32_P5_MC_ADDR: |
3773 | case MSR_IA32_P5_MC_TYPE: | |
3774 | case MSR_IA32_MCG_CAP: | |
3775 | case MSR_IA32_MCG_CTL: | |
3776 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 3777 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
44883f01 PB |
3778 | return get_msr_mce(vcpu, msr_info->index, &msr_info->data, |
3779 | msr_info->host_initiated); | |
864e2ab2 AL |
3780 | case MSR_IA32_XSS: |
3781 | if (!msr_info->host_initiated && | |
3782 | !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) | |
3783 | return 1; | |
3784 | msr_info->data = vcpu->arch.ia32_xss; | |
3785 | break; | |
84e0cefa JS |
3786 | case MSR_K7_CLK_CTL: |
3787 | /* | |
3788 | * Provide expected ramp-up count for K7. All other | |
3789 | * are set to zero, indicating minimum divisors for | |
3790 | * every field. | |
3791 | * | |
3792 | * This prevents guest kernels on AMD host with CPU | |
3793 | * type 6, model 8 and higher from exploding due to | |
3794 | * the rdmsr failing. | |
3795 | */ | |
609e36d3 | 3796 | msr_info->data = 0x20000000; |
84e0cefa | 3797 | break; |
55cd8e5a | 3798 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
f97f5a56 JD |
3799 | case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: |
3800 | case HV_X64_MSR_SYNDBG_OPTIONS: | |
e7d9513b AS |
3801 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
3802 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 3803 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
3804 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
3805 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
3806 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
e83d5887 | 3807 | return kvm_hv_get_msr_common(vcpu, |
44883f01 PB |
3808 | msr_info->index, &msr_info->data, |
3809 | msr_info->host_initiated); | |
91c9c3ed | 3810 | case MSR_IA32_BBL_CR_CTL3: |
3811 | /* This legacy MSR exists but isn't fully documented in current | |
3812 | * silicon. It is however accessed by winxp in very narrow | |
3813 | * scenarios where it sets bit #19, itself documented as | |
3814 | * a "reserved" bit. Best effort attempt to source coherent | |
3815 | * read data here should the balance of the register be | |
3816 | * interpreted by the guest: | |
3817 | * | |
3818 | * L2 cache control register 3: 64GB range, 256KB size, | |
3819 | * enabled, latency 0x1, configured | |
3820 | */ | |
609e36d3 | 3821 | msr_info->data = 0xbe702111; |
91c9c3ed | 3822 | break; |
2b036c6b | 3823 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 3824 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 3825 | return 1; |
609e36d3 | 3826 | msr_info->data = vcpu->arch.osvw.length; |
2b036c6b BO |
3827 | break; |
3828 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 3829 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 3830 | return 1; |
609e36d3 | 3831 | msr_info->data = vcpu->arch.osvw.status; |
2b036c6b | 3832 | break; |
db2336a8 | 3833 | case MSR_PLATFORM_INFO: |
6fbbde9a DS |
3834 | if (!msr_info->host_initiated && |
3835 | !vcpu->kvm->arch.guest_can_read_msr_platform_info) | |
3836 | return 1; | |
db2336a8 KH |
3837 | msr_info->data = vcpu->arch.msr_platform_info; |
3838 | break; | |
3839 | case MSR_MISC_FEATURES_ENABLES: | |
3840 | msr_info->data = vcpu->arch.msr_misc_features_enables; | |
3841 | break; | |
191c8137 BP |
3842 | case MSR_K7_HWCR: |
3843 | msr_info->data = vcpu->arch.msr_hwcr; | |
3844 | break; | |
15c4a640 | 3845 | default: |
c6702c9d | 3846 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
cbd71758 | 3847 | return kvm_pmu_get_msr(vcpu, msr_info); |
6abe9c13 | 3848 | return KVM_MSR_RET_INVALID; |
15c4a640 | 3849 | } |
15c4a640 CO |
3850 | return 0; |
3851 | } | |
3852 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
3853 | ||
313a3dc7 CO |
3854 | /* |
3855 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
3856 | * | |
3857 | * @return number of msrs set successfully. | |
3858 | */ | |
3859 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
3860 | struct kvm_msr_entry *entries, | |
3861 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
3862 | unsigned index, u64 *data)) | |
3863 | { | |
801e459a | 3864 | int i; |
313a3dc7 | 3865 | |
313a3dc7 CO |
3866 | for (i = 0; i < msrs->nmsrs; ++i) |
3867 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
3868 | break; | |
3869 | ||
313a3dc7 CO |
3870 | return i; |
3871 | } | |
3872 | ||
3873 | /* | |
3874 | * Read or write a bunch of msrs. Parameters are user addresses. | |
3875 | * | |
3876 | * @return number of msrs set successfully. | |
3877 | */ | |
3878 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
3879 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
3880 | unsigned index, u64 *data), | |
3881 | int writeback) | |
3882 | { | |
3883 | struct kvm_msrs msrs; | |
3884 | struct kvm_msr_entry *entries; | |
3885 | int r, n; | |
3886 | unsigned size; | |
3887 | ||
3888 | r = -EFAULT; | |
0e96f31e | 3889 | if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) |
313a3dc7 CO |
3890 | goto out; |
3891 | ||
3892 | r = -E2BIG; | |
3893 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
3894 | goto out; | |
3895 | ||
313a3dc7 | 3896 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; |
ff5c2c03 SL |
3897 | entries = memdup_user(user_msrs->entries, size); |
3898 | if (IS_ERR(entries)) { | |
3899 | r = PTR_ERR(entries); | |
313a3dc7 | 3900 | goto out; |
ff5c2c03 | 3901 | } |
313a3dc7 CO |
3902 | |
3903 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
3904 | if (r < 0) | |
3905 | goto out_free; | |
3906 | ||
3907 | r = -EFAULT; | |
3908 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
3909 | goto out_free; | |
3910 | ||
3911 | r = n; | |
3912 | ||
3913 | out_free: | |
7a73c028 | 3914 | kfree(entries); |
313a3dc7 CO |
3915 | out: |
3916 | return r; | |
3917 | } | |
3918 | ||
4d5422ce WL |
3919 | static inline bool kvm_can_mwait_in_guest(void) |
3920 | { | |
3921 | return boot_cpu_has(X86_FEATURE_MWAIT) && | |
8e9b29b6 KA |
3922 | !boot_cpu_has_bug(X86_BUG_MONITOR) && |
3923 | boot_cpu_has(X86_FEATURE_ARAT); | |
4d5422ce WL |
3924 | } |
3925 | ||
c21d54f0 VK |
3926 | static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu, |
3927 | struct kvm_cpuid2 __user *cpuid_arg) | |
3928 | { | |
3929 | struct kvm_cpuid2 cpuid; | |
3930 | int r; | |
3931 | ||
3932 | r = -EFAULT; | |
3933 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) | |
3934 | return r; | |
3935 | ||
3936 | r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
3937 | if (r) | |
3938 | return r; | |
3939 | ||
3940 | r = -EFAULT; | |
3941 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) | |
3942 | return r; | |
3943 | ||
3944 | return 0; | |
3945 | } | |
3946 | ||
784aa3d7 | 3947 | int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) |
018d00d2 | 3948 | { |
4d5422ce | 3949 | int r = 0; |
018d00d2 ZX |
3950 | |
3951 | switch (ext) { | |
3952 | case KVM_CAP_IRQCHIP: | |
3953 | case KVM_CAP_HLT: | |
3954 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 3955 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 3956 | case KVM_CAP_EXT_CPUID: |
9c15bb1d | 3957 | case KVM_CAP_EXT_EMUL_CPUID: |
c8076604 | 3958 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 3959 | case KVM_CAP_PIT: |
a28e4f5a | 3960 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 3961 | case KVM_CAP_MP_STATE: |
ed848624 | 3962 | case KVM_CAP_SYNC_MMU: |
a355c85c | 3963 | case KVM_CAP_USER_NMI: |
52d939a0 | 3964 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 3965 | case KVM_CAP_IRQ_INJECT_STATUS: |
d34e6b17 | 3966 | case KVM_CAP_IOEVENTFD: |
f848a5a8 | 3967 | case KVM_CAP_IOEVENTFD_NO_LENGTH: |
c5ff41ce | 3968 | case KVM_CAP_PIT2: |
e9f42757 | 3969 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 3970 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
3cfc3092 | 3971 | case KVM_CAP_VCPU_EVENTS: |
55cd8e5a | 3972 | case KVM_CAP_HYPERV: |
10388a07 | 3973 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 3974 | case KVM_CAP_HYPERV_SPIN: |
5c919412 | 3975 | case KVM_CAP_HYPERV_SYNIC: |
efc479e6 | 3976 | case KVM_CAP_HYPERV_SYNIC2: |
d3457c87 | 3977 | case KVM_CAP_HYPERV_VP_INDEX: |
faeb7833 | 3978 | case KVM_CAP_HYPERV_EVENTFD: |
c1aea919 | 3979 | case KVM_CAP_HYPERV_TLBFLUSH: |
214ff83d | 3980 | case KVM_CAP_HYPERV_SEND_IPI: |
2bc39970 | 3981 | case KVM_CAP_HYPERV_CPUID: |
644f7067 | 3982 | case KVM_CAP_HYPERV_ENFORCE_CPUID: |
c21d54f0 | 3983 | case KVM_CAP_SYS_HYPERV_CPUID: |
ab9f4ecb | 3984 | case KVM_CAP_PCI_SEGMENT: |
a1efbe77 | 3985 | case KVM_CAP_DEBUGREGS: |
d2be1651 | 3986 | case KVM_CAP_X86_ROBUST_SINGLESTEP: |
2d5b5a66 | 3987 | case KVM_CAP_XSAVE: |
344d9588 | 3988 | case KVM_CAP_ASYNC_PF: |
72de5fa4 | 3989 | case KVM_CAP_ASYNC_PF_INT: |
92a1f12d | 3990 | case KVM_CAP_GET_TSC_KHZ: |
1c0b28c2 | 3991 | case KVM_CAP_KVMCLOCK_CTRL: |
4d8b81ab | 3992 | case KVM_CAP_READONLY_MEM: |
5f66b620 | 3993 | case KVM_CAP_HYPERV_TIME: |
100943c5 | 3994 | case KVM_CAP_IOAPIC_POLARITY_IGNORED: |
defcf51f | 3995 | case KVM_CAP_TSC_DEADLINE_TIMER: |
90de4a18 | 3996 | case KVM_CAP_DISABLE_QUIRKS: |
d71ba788 | 3997 | case KVM_CAP_SET_BOOT_CPU_ID: |
49df6397 | 3998 | case KVM_CAP_SPLIT_IRQCHIP: |
460df4c1 | 3999 | case KVM_CAP_IMMEDIATE_EXIT: |
66bb8a06 | 4000 | case KVM_CAP_PMU_EVENT_FILTER: |
801e459a | 4001 | case KVM_CAP_GET_MSR_FEATURES: |
6fbbde9a | 4002 | case KVM_CAP_MSR_PLATFORM_INFO: |
c4f55198 | 4003 | case KVM_CAP_EXCEPTION_PAYLOAD: |
b9b2782c | 4004 | case KVM_CAP_SET_GUEST_DEBUG: |
1aa561b1 | 4005 | case KVM_CAP_LAST_CPU: |
1ae09954 | 4006 | case KVM_CAP_X86_USER_SPACE_MSR: |
1a155254 | 4007 | case KVM_CAP_X86_MSR_FILTER: |
66570e96 | 4008 | case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: |
fe7e9488 SC |
4009 | #ifdef CONFIG_X86_SGX_KVM |
4010 | case KVM_CAP_SGX_ATTRIBUTE: | |
4011 | #endif | |
54526d1f | 4012 | case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: |
6dba9403 | 4013 | case KVM_CAP_SREGS2: |
19238e75 | 4014 | case KVM_CAP_EXIT_ON_EMULATION_FAILURE: |
018d00d2 ZX |
4015 | r = 1; |
4016 | break; | |
0dbb1123 AK |
4017 | case KVM_CAP_EXIT_HYPERCALL: |
4018 | r = KVM_EXIT_HYPERCALL_VALID_MASK; | |
4019 | break; | |
7e582ccb ML |
4020 | case KVM_CAP_SET_GUEST_DEBUG2: |
4021 | return KVM_GUESTDBG_VALID_MASK; | |
b59b153d | 4022 | #ifdef CONFIG_KVM_XEN |
23200b7a JM |
4023 | case KVM_CAP_XEN_HVM: |
4024 | r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR | | |
8d4e7e80 DW |
4025 | KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL | |
4026 | KVM_XEN_HVM_CONFIG_SHARED_INFO; | |
30b5c851 DW |
4027 | if (sched_info_on()) |
4028 | r |= KVM_XEN_HVM_CONFIG_RUNSTATE; | |
23200b7a | 4029 | break; |
b59b153d | 4030 | #endif |
01643c51 KH |
4031 | case KVM_CAP_SYNC_REGS: |
4032 | r = KVM_SYNC_X86_VALID_FIELDS; | |
4033 | break; | |
e3fd9a93 PB |
4034 | case KVM_CAP_ADJUST_CLOCK: |
4035 | r = KVM_CLOCK_TSC_STABLE; | |
4036 | break; | |
4d5422ce | 4037 | case KVM_CAP_X86_DISABLE_EXITS: |
b5170063 WL |
4038 | r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE | |
4039 | KVM_X86_DISABLE_EXITS_CSTATE; | |
4d5422ce WL |
4040 | if(kvm_can_mwait_in_guest()) |
4041 | r |= KVM_X86_DISABLE_EXITS_MWAIT; | |
668fffa3 | 4042 | break; |
6d396b55 PB |
4043 | case KVM_CAP_X86_SMM: |
4044 | /* SMBASE is usually relocated above 1M on modern chipsets, | |
4045 | * and SMM handlers might indeed rely on 4G segment limits, | |
4046 | * so do not report SMM to be available if real mode is | |
4047 | * emulated via vm86 mode. Still, do not go to great lengths | |
4048 | * to avoid userspace's usage of the feature, because it is a | |
4049 | * fringe case that is not enabled except via specific settings | |
4050 | * of the module parameters. | |
4051 | */ | |
b3646477 | 4052 | r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE); |
6d396b55 | 4053 | break; |
774ead3a | 4054 | case KVM_CAP_VAPIC: |
b3646477 | 4055 | r = !static_call(kvm_x86_cpu_has_accelerated_tpr)(); |
774ead3a | 4056 | break; |
f725230a | 4057 | case KVM_CAP_NR_VCPUS: |
8c3ba334 SL |
4058 | r = KVM_SOFT_MAX_VCPUS; |
4059 | break; | |
4060 | case KVM_CAP_MAX_VCPUS: | |
f725230a AK |
4061 | r = KVM_MAX_VCPUS; |
4062 | break; | |
a86cb413 TH |
4063 | case KVM_CAP_MAX_VCPU_ID: |
4064 | r = KVM_MAX_VCPU_ID; | |
4065 | break; | |
a68a6a72 MT |
4066 | case KVM_CAP_PV_MMU: /* obsolete */ |
4067 | r = 0; | |
2f333bcb | 4068 | break; |
890ca9ae HY |
4069 | case KVM_CAP_MCE: |
4070 | r = KVM_MAX_MCE_BANKS; | |
4071 | break; | |
2d5b5a66 | 4072 | case KVM_CAP_XCRS: |
d366bf7e | 4073 | r = boot_cpu_has(X86_FEATURE_XSAVE); |
2d5b5a66 | 4074 | break; |
92a1f12d JR |
4075 | case KVM_CAP_TSC_CONTROL: |
4076 | r = kvm_has_tsc_control; | |
4077 | break; | |
37131313 RK |
4078 | case KVM_CAP_X2APIC_API: |
4079 | r = KVM_X2APIC_API_VALID_FLAGS; | |
4080 | break; | |
8fcc4b59 | 4081 | case KVM_CAP_NESTED_STATE: |
33b22172 PB |
4082 | r = kvm_x86_ops.nested_ops->get_state ? |
4083 | kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0; | |
8fcc4b59 | 4084 | break; |
344c6c80 | 4085 | case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: |
afaf0b2f | 4086 | r = kvm_x86_ops.enable_direct_tlbflush != NULL; |
5a0165f6 VK |
4087 | break; |
4088 | case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: | |
33b22172 | 4089 | r = kvm_x86_ops.nested_ops->enable_evmcs != NULL; |
344c6c80 | 4090 | break; |
3edd6839 MG |
4091 | case KVM_CAP_SMALLER_MAXPHYADDR: |
4092 | r = (int) allow_smaller_maxphyaddr; | |
4093 | break; | |
004a0124 AJ |
4094 | case KVM_CAP_STEAL_TIME: |
4095 | r = sched_info_on(); | |
4096 | break; | |
fe6b6bc8 CQ |
4097 | case KVM_CAP_X86_BUS_LOCK_EXIT: |
4098 | if (kvm_has_bus_lock_exit) | |
4099 | r = KVM_BUS_LOCK_DETECTION_OFF | | |
4100 | KVM_BUS_LOCK_DETECTION_EXIT; | |
4101 | else | |
4102 | r = 0; | |
4103 | break; | |
018d00d2 | 4104 | default: |
018d00d2 ZX |
4105 | break; |
4106 | } | |
4107 | return r; | |
4108 | ||
4109 | } | |
4110 | ||
043405e1 CO |
4111 | long kvm_arch_dev_ioctl(struct file *filp, |
4112 | unsigned int ioctl, unsigned long arg) | |
4113 | { | |
4114 | void __user *argp = (void __user *)arg; | |
4115 | long r; | |
4116 | ||
4117 | switch (ioctl) { | |
4118 | case KVM_GET_MSR_INDEX_LIST: { | |
4119 | struct kvm_msr_list __user *user_msr_list = argp; | |
4120 | struct kvm_msr_list msr_list; | |
4121 | unsigned n; | |
4122 | ||
4123 | r = -EFAULT; | |
0e96f31e | 4124 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) |
043405e1 CO |
4125 | goto out; |
4126 | n = msr_list.nmsrs; | |
62ef68bb | 4127 | msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; |
0e96f31e | 4128 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) |
043405e1 CO |
4129 | goto out; |
4130 | r = -E2BIG; | |
e125e7b6 | 4131 | if (n < msr_list.nmsrs) |
043405e1 CO |
4132 | goto out; |
4133 | r = -EFAULT; | |
4134 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
4135 | num_msrs_to_save * sizeof(u32))) | |
4136 | goto out; | |
e125e7b6 | 4137 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 | 4138 | &emulated_msrs, |
62ef68bb | 4139 | num_emulated_msrs * sizeof(u32))) |
043405e1 CO |
4140 | goto out; |
4141 | r = 0; | |
4142 | break; | |
4143 | } | |
9c15bb1d BP |
4144 | case KVM_GET_SUPPORTED_CPUID: |
4145 | case KVM_GET_EMULATED_CPUID: { | |
674eea0f AK |
4146 | struct kvm_cpuid2 __user *cpuid_arg = argp; |
4147 | struct kvm_cpuid2 cpuid; | |
4148 | ||
4149 | r = -EFAULT; | |
0e96f31e | 4150 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
674eea0f | 4151 | goto out; |
9c15bb1d BP |
4152 | |
4153 | r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, | |
4154 | ioctl); | |
674eea0f AK |
4155 | if (r) |
4156 | goto out; | |
4157 | ||
4158 | r = -EFAULT; | |
0e96f31e | 4159 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) |
674eea0f AK |
4160 | goto out; |
4161 | r = 0; | |
4162 | break; | |
4163 | } | |
cf6c26ec | 4164 | case KVM_X86_GET_MCE_CAP_SUPPORTED: |
890ca9ae | 4165 | r = -EFAULT; |
c45dcc71 AR |
4166 | if (copy_to_user(argp, &kvm_mce_cap_supported, |
4167 | sizeof(kvm_mce_cap_supported))) | |
890ca9ae HY |
4168 | goto out; |
4169 | r = 0; | |
4170 | break; | |
801e459a TL |
4171 | case KVM_GET_MSR_FEATURE_INDEX_LIST: { |
4172 | struct kvm_msr_list __user *user_msr_list = argp; | |
4173 | struct kvm_msr_list msr_list; | |
4174 | unsigned int n; | |
4175 | ||
4176 | r = -EFAULT; | |
4177 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) | |
4178 | goto out; | |
4179 | n = msr_list.nmsrs; | |
4180 | msr_list.nmsrs = num_msr_based_features; | |
4181 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) | |
4182 | goto out; | |
4183 | r = -E2BIG; | |
4184 | if (n < msr_list.nmsrs) | |
4185 | goto out; | |
4186 | r = -EFAULT; | |
4187 | if (copy_to_user(user_msr_list->indices, &msr_based_features, | |
4188 | num_msr_based_features * sizeof(u32))) | |
4189 | goto out; | |
4190 | r = 0; | |
4191 | break; | |
4192 | } | |
4193 | case KVM_GET_MSRS: | |
4194 | r = msr_io(NULL, argp, do_get_msr_feature, 1); | |
4195 | break; | |
c21d54f0 VK |
4196 | case KVM_GET_SUPPORTED_HV_CPUID: |
4197 | r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp); | |
4198 | break; | |
043405e1 CO |
4199 | default: |
4200 | r = -EINVAL; | |
cf6c26ec | 4201 | break; |
043405e1 CO |
4202 | } |
4203 | out: | |
4204 | return r; | |
4205 | } | |
4206 | ||
f5f48ee1 SY |
4207 | static void wbinvd_ipi(void *garbage) |
4208 | { | |
4209 | wbinvd(); | |
4210 | } | |
4211 | ||
4212 | static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
4213 | { | |
e0f0bbc5 | 4214 | return kvm_arch_has_noncoherent_dma(vcpu->kvm); |
f5f48ee1 SY |
4215 | } |
4216 | ||
313a3dc7 CO |
4217 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
4218 | { | |
f5f48ee1 SY |
4219 | /* Address WBINVD may be executed by guest */ |
4220 | if (need_emulate_wbinvd(vcpu)) { | |
b3646477 | 4221 | if (static_call(kvm_x86_has_wbinvd_exit)()) |
f5f48ee1 SY |
4222 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); |
4223 | else if (vcpu->cpu != -1 && vcpu->cpu != cpu) | |
4224 | smp_call_function_single(vcpu->cpu, | |
4225 | wbinvd_ipi, NULL, 1); | |
4226 | } | |
4227 | ||
b3646477 | 4228 | static_call(kvm_x86_vcpu_load)(vcpu, cpu); |
8f6055cb | 4229 | |
37486135 BM |
4230 | /* Save host pkru register if supported */ |
4231 | vcpu->arch.host_pkru = read_pkru(); | |
4232 | ||
0dd6a6ed ZA |
4233 | /* Apply any externally detected TSC adjustments (due to suspend) */ |
4234 | if (unlikely(vcpu->arch.tsc_offset_adjustment)) { | |
4235 | adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); | |
4236 | vcpu->arch.tsc_offset_adjustment = 0; | |
105b21bb | 4237 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed | 4238 | } |
8f6055cb | 4239 | |
b0c39dc6 | 4240 | if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { |
6f526ec5 | 4241 | s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : |
4ea1636b | 4242 | rdtsc() - vcpu->arch.last_host_tsc; |
e48672fa ZA |
4243 | if (tsc_delta < 0) |
4244 | mark_tsc_unstable("KVM discovered backwards TSC"); | |
ce7a058a | 4245 | |
b0c39dc6 | 4246 | if (kvm_check_tsc_unstable()) { |
9b399dfd | 4247 | u64 offset = kvm_compute_l1_tsc_offset(vcpu, |
b183aa58 | 4248 | vcpu->arch.last_guest_tsc); |
a545ab6a | 4249 | kvm_vcpu_write_tsc_offset(vcpu, offset); |
c285545f | 4250 | vcpu->arch.tsc_catchup = 1; |
c285545f | 4251 | } |
a749e247 PB |
4252 | |
4253 | if (kvm_lapic_hv_timer_in_use(vcpu)) | |
4254 | kvm_lapic_restart_hv_timer(vcpu); | |
4255 | ||
d98d07ca MT |
4256 | /* |
4257 | * On a host with synchronized TSC, there is no need to update | |
4258 | * kvmclock on vcpu->cpu migration | |
4259 | */ | |
4260 | if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) | |
0061d53d | 4261 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
c285545f | 4262 | if (vcpu->cpu != cpu) |
1bd2009e | 4263 | kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); |
e48672fa | 4264 | vcpu->cpu = cpu; |
6b7d7e76 | 4265 | } |
c9aaa895 | 4266 | |
c9aaa895 | 4267 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
313a3dc7 CO |
4268 | } |
4269 | ||
0b9f6c46 PX |
4270 | static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) |
4271 | { | |
b0431382 BO |
4272 | struct kvm_host_map map; |
4273 | struct kvm_steal_time *st; | |
4274 | ||
0b9f6c46 PX |
4275 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) |
4276 | return; | |
4277 | ||
a6bd811f | 4278 | if (vcpu->arch.st.preempted) |
8c6de56a BO |
4279 | return; |
4280 | ||
b0431382 BO |
4281 | if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map, |
4282 | &vcpu->arch.st.cache, true)) | |
9c1a0744 | 4283 | return; |
b0431382 BO |
4284 | |
4285 | st = map.hva + | |
4286 | offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); | |
0b9f6c46 | 4287 | |
a6bd811f | 4288 | st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; |
0b9f6c46 | 4289 | |
b0431382 | 4290 | kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true); |
0b9f6c46 PX |
4291 | } |
4292 | ||
313a3dc7 CO |
4293 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) |
4294 | { | |
9c1a0744 WL |
4295 | int idx; |
4296 | ||
f1c6366e | 4297 | if (vcpu->preempted && !vcpu->arch.guest_state_protected) |
b3646477 | 4298 | vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu); |
de63ad4c | 4299 | |
9c1a0744 WL |
4300 | /* |
4301 | * Take the srcu lock as memslots will be accessed to check the gfn | |
4302 | * cache generation against the memslots generation. | |
4303 | */ | |
4304 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
30b5c851 DW |
4305 | if (kvm_xen_msr_enabled(vcpu->kvm)) |
4306 | kvm_xen_runstate_set_preempted(vcpu); | |
4307 | else | |
4308 | kvm_steal_time_set_preempted(vcpu); | |
9c1a0744 | 4309 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
30b5c851 | 4310 | |
b3646477 | 4311 | static_call(kvm_x86_vcpu_put)(vcpu); |
4ea1636b | 4312 | vcpu->arch.last_host_tsc = rdtsc(); |
efdab992 | 4313 | /* |
f9dcf08e RK |
4314 | * If userspace has set any breakpoints or watchpoints, dr6 is restored |
4315 | * on every vmexit, but if not, we might have a stale dr6 from the | |
4316 | * guest. do_debug expects dr6 to be cleared after it runs, do the same. | |
efdab992 | 4317 | */ |
f9dcf08e | 4318 | set_debugreg(0, 6); |
313a3dc7 CO |
4319 | } |
4320 | ||
313a3dc7 CO |
4321 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
4322 | struct kvm_lapic_state *s) | |
4323 | { | |
fa59cc00 | 4324 | if (vcpu->arch.apicv_active) |
b3646477 | 4325 | static_call(kvm_x86_sync_pir_to_irr)(vcpu); |
d62caabb | 4326 | |
a92e2543 | 4327 | return kvm_apic_get_state(vcpu, s); |
313a3dc7 CO |
4328 | } |
4329 | ||
4330 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
4331 | struct kvm_lapic_state *s) | |
4332 | { | |
a92e2543 RK |
4333 | int r; |
4334 | ||
4335 | r = kvm_apic_set_state(vcpu, s); | |
4336 | if (r) | |
4337 | return r; | |
cb142eb7 | 4338 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
4339 | |
4340 | return 0; | |
4341 | } | |
4342 | ||
127a457a MG |
4343 | static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) |
4344 | { | |
71cc849b PB |
4345 | /* |
4346 | * We can accept userspace's request for interrupt injection | |
4347 | * as long as we have a place to store the interrupt number. | |
4348 | * The actual injection will happen when the CPU is able to | |
4349 | * deliver the interrupt. | |
4350 | */ | |
4351 | if (kvm_cpu_has_extint(vcpu)) | |
4352 | return false; | |
4353 | ||
4354 | /* Acknowledging ExtINT does not happen if LINT0 is masked. */ | |
127a457a MG |
4355 | return (!lapic_in_kernel(vcpu) || |
4356 | kvm_apic_accept_pic_intr(vcpu)); | |
4357 | } | |
4358 | ||
782d422b MG |
4359 | static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) |
4360 | { | |
4361 | return kvm_arch_interrupt_allowed(vcpu) && | |
782d422b MG |
4362 | kvm_cpu_accept_dm_intr(vcpu); |
4363 | } | |
4364 | ||
f77bc6a4 ZX |
4365 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
4366 | struct kvm_interrupt *irq) | |
4367 | { | |
02cdb50f | 4368 | if (irq->irq >= KVM_NR_INTERRUPTS) |
f77bc6a4 | 4369 | return -EINVAL; |
1c1a9ce9 SR |
4370 | |
4371 | if (!irqchip_in_kernel(vcpu->kvm)) { | |
4372 | kvm_queue_interrupt(vcpu, irq->irq, false); | |
4373 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
4374 | return 0; | |
4375 | } | |
4376 | ||
4377 | /* | |
4378 | * With in-kernel LAPIC, we only use this to inject EXTINT, so | |
4379 | * fail for in-kernel 8259. | |
4380 | */ | |
4381 | if (pic_in_kernel(vcpu->kvm)) | |
f77bc6a4 | 4382 | return -ENXIO; |
f77bc6a4 | 4383 | |
1c1a9ce9 SR |
4384 | if (vcpu->arch.pending_external_vector != -1) |
4385 | return -EEXIST; | |
f77bc6a4 | 4386 | |
1c1a9ce9 | 4387 | vcpu->arch.pending_external_vector = irq->irq; |
934bf653 | 4388 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f77bc6a4 ZX |
4389 | return 0; |
4390 | } | |
4391 | ||
c4abb7c9 JK |
4392 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
4393 | { | |
c4abb7c9 | 4394 | kvm_inject_nmi(vcpu); |
c4abb7c9 JK |
4395 | |
4396 | return 0; | |
4397 | } | |
4398 | ||
f077825a PB |
4399 | static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) |
4400 | { | |
64d60670 PB |
4401 | kvm_make_request(KVM_REQ_SMI, vcpu); |
4402 | ||
f077825a PB |
4403 | return 0; |
4404 | } | |
4405 | ||
b209749f AK |
4406 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
4407 | struct kvm_tpr_access_ctl *tac) | |
4408 | { | |
4409 | if (tac->flags) | |
4410 | return -EINVAL; | |
4411 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
4412 | return 0; | |
4413 | } | |
4414 | ||
890ca9ae HY |
4415 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
4416 | u64 mcg_cap) | |
4417 | { | |
4418 | int r; | |
4419 | unsigned bank_num = mcg_cap & 0xff, bank; | |
4420 | ||
4421 | r = -EINVAL; | |
c4e0e4ab | 4422 | if (!bank_num || bank_num > KVM_MAX_MCE_BANKS) |
890ca9ae | 4423 | goto out; |
c45dcc71 | 4424 | if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) |
890ca9ae HY |
4425 | goto out; |
4426 | r = 0; | |
4427 | vcpu->arch.mcg_cap = mcg_cap; | |
4428 | /* Init IA32_MCG_CTL to all 1s */ | |
4429 | if (mcg_cap & MCG_CTL_P) | |
4430 | vcpu->arch.mcg_ctl = ~(u64)0; | |
4431 | /* Init IA32_MCi_CTL to all 1s */ | |
4432 | for (bank = 0; bank < bank_num; bank++) | |
4433 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
c45dcc71 | 4434 | |
b3646477 | 4435 | static_call(kvm_x86_setup_mce)(vcpu); |
890ca9ae HY |
4436 | out: |
4437 | return r; | |
4438 | } | |
4439 | ||
4440 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
4441 | struct kvm_x86_mce *mce) | |
4442 | { | |
4443 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
4444 | unsigned bank_num = mcg_cap & 0xff; | |
4445 | u64 *banks = vcpu->arch.mce_banks; | |
4446 | ||
4447 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
4448 | return -EINVAL; | |
4449 | /* | |
4450 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
4451 | * reporting is disabled | |
4452 | */ | |
4453 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
4454 | vcpu->arch.mcg_ctl != ~(u64)0) | |
4455 | return 0; | |
4456 | banks += 4 * mce->bank; | |
4457 | /* | |
4458 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
4459 | * reporting is disabled for the bank | |
4460 | */ | |
4461 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
4462 | return 0; | |
4463 | if (mce->status & MCI_STATUS_UC) { | |
4464 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
fc78f519 | 4465 | !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { |
a8eeb04a | 4466 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
890ca9ae HY |
4467 | return 0; |
4468 | } | |
4469 | if (banks[1] & MCI_STATUS_VAL) | |
4470 | mce->status |= MCI_STATUS_OVER; | |
4471 | banks[2] = mce->addr; | |
4472 | banks[3] = mce->misc; | |
4473 | vcpu->arch.mcg_status = mce->mcg_status; | |
4474 | banks[1] = mce->status; | |
4475 | kvm_queue_exception(vcpu, MC_VECTOR); | |
4476 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
4477 | || !(banks[1] & MCI_STATUS_UC)) { | |
4478 | if (banks[1] & MCI_STATUS_VAL) | |
4479 | mce->status |= MCI_STATUS_OVER; | |
4480 | banks[2] = mce->addr; | |
4481 | banks[3] = mce->misc; | |
4482 | banks[1] = mce->status; | |
4483 | } else | |
4484 | banks[1] |= MCI_STATUS_OVER; | |
4485 | return 0; | |
4486 | } | |
4487 | ||
3cfc3092 JK |
4488 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
4489 | struct kvm_vcpu_events *events) | |
4490 | { | |
7460fb4a | 4491 | process_nmi(vcpu); |
59073aaf | 4492 | |
1f7becf1 JZ |
4493 | if (kvm_check_request(KVM_REQ_SMI, vcpu)) |
4494 | process_smi(vcpu); | |
4495 | ||
a06230b6 OU |
4496 | /* |
4497 | * In guest mode, payload delivery should be deferred, | |
4498 | * so that the L1 hypervisor can intercept #PF before | |
4499 | * CR2 is modified (or intercept #DB before DR6 is | |
4500 | * modified under nVMX). Unless the per-VM capability, | |
4501 | * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of | |
4502 | * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we | |
4503 | * opportunistically defer the exception payload, deliver it if the | |
4504 | * capability hasn't been requested before processing a | |
4505 | * KVM_GET_VCPU_EVENTS. | |
4506 | */ | |
4507 | if (!vcpu->kvm->arch.exception_payload_enabled && | |
4508 | vcpu->arch.exception.pending && vcpu->arch.exception.has_payload) | |
4509 | kvm_deliver_exception_payload(vcpu); | |
4510 | ||
664f8e26 | 4511 | /* |
59073aaf JM |
4512 | * The API doesn't provide the instruction length for software |
4513 | * exceptions, so don't report them. As long as the guest RIP | |
4514 | * isn't advanced, we should expect to encounter the exception | |
4515 | * again. | |
664f8e26 | 4516 | */ |
59073aaf JM |
4517 | if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { |
4518 | events->exception.injected = 0; | |
4519 | events->exception.pending = 0; | |
4520 | } else { | |
4521 | events->exception.injected = vcpu->arch.exception.injected; | |
4522 | events->exception.pending = vcpu->arch.exception.pending; | |
4523 | /* | |
4524 | * For ABI compatibility, deliberately conflate | |
4525 | * pending and injected exceptions when | |
4526 | * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. | |
4527 | */ | |
4528 | if (!vcpu->kvm->arch.exception_payload_enabled) | |
4529 | events->exception.injected |= | |
4530 | vcpu->arch.exception.pending; | |
4531 | } | |
3cfc3092 JK |
4532 | events->exception.nr = vcpu->arch.exception.nr; |
4533 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
4534 | events->exception.error_code = vcpu->arch.exception.error_code; | |
59073aaf JM |
4535 | events->exception_has_payload = vcpu->arch.exception.has_payload; |
4536 | events->exception_payload = vcpu->arch.exception.payload; | |
3cfc3092 | 4537 | |
03b82a30 | 4538 | events->interrupt.injected = |
04140b41 | 4539 | vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; |
3cfc3092 | 4540 | events->interrupt.nr = vcpu->arch.interrupt.nr; |
03b82a30 | 4541 | events->interrupt.soft = 0; |
b3646477 | 4542 | events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); |
3cfc3092 JK |
4543 | |
4544 | events->nmi.injected = vcpu->arch.nmi_injected; | |
7460fb4a | 4545 | events->nmi.pending = vcpu->arch.nmi_pending != 0; |
b3646477 | 4546 | events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu); |
97e69aa6 | 4547 | events->nmi.pad = 0; |
3cfc3092 | 4548 | |
66450a21 | 4549 | events->sipi_vector = 0; /* never valid when reporting to user space */ |
3cfc3092 | 4550 | |
f077825a PB |
4551 | events->smi.smm = is_smm(vcpu); |
4552 | events->smi.pending = vcpu->arch.smi_pending; | |
4553 | events->smi.smm_inside_nmi = | |
4554 | !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); | |
4555 | events->smi.latched_init = kvm_lapic_latched_init(vcpu); | |
4556 | ||
dab4b911 | 4557 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
f077825a PB |
4558 | | KVM_VCPUEVENT_VALID_SHADOW |
4559 | | KVM_VCPUEVENT_VALID_SMM); | |
59073aaf JM |
4560 | if (vcpu->kvm->arch.exception_payload_enabled) |
4561 | events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; | |
4562 | ||
97e69aa6 | 4563 | memset(&events->reserved, 0, sizeof(events->reserved)); |
3cfc3092 JK |
4564 | } |
4565 | ||
dc87275f | 4566 | static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm); |
6ef4e07e | 4567 | |
3cfc3092 JK |
4568 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, |
4569 | struct kvm_vcpu_events *events) | |
4570 | { | |
dab4b911 | 4571 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 | 4572 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
f077825a | 4573 | | KVM_VCPUEVENT_VALID_SHADOW |
59073aaf JM |
4574 | | KVM_VCPUEVENT_VALID_SMM |
4575 | | KVM_VCPUEVENT_VALID_PAYLOAD)) | |
3cfc3092 JK |
4576 | return -EINVAL; |
4577 | ||
59073aaf JM |
4578 | if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { |
4579 | if (!vcpu->kvm->arch.exception_payload_enabled) | |
4580 | return -EINVAL; | |
4581 | if (events->exception.pending) | |
4582 | events->exception.injected = 0; | |
4583 | else | |
4584 | events->exception_has_payload = 0; | |
4585 | } else { | |
4586 | events->exception.pending = 0; | |
4587 | events->exception_has_payload = 0; | |
4588 | } | |
4589 | ||
4590 | if ((events->exception.injected || events->exception.pending) && | |
4591 | (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) | |
78e546c8 PB |
4592 | return -EINVAL; |
4593 | ||
28bf2888 DH |
4594 | /* INITs are latched while in SMM */ |
4595 | if (events->flags & KVM_VCPUEVENT_VALID_SMM && | |
4596 | (events->smi.smm || events->smi.pending) && | |
4597 | vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) | |
4598 | return -EINVAL; | |
4599 | ||
7460fb4a | 4600 | process_nmi(vcpu); |
59073aaf JM |
4601 | vcpu->arch.exception.injected = events->exception.injected; |
4602 | vcpu->arch.exception.pending = events->exception.pending; | |
3cfc3092 JK |
4603 | vcpu->arch.exception.nr = events->exception.nr; |
4604 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
4605 | vcpu->arch.exception.error_code = events->exception.error_code; | |
59073aaf JM |
4606 | vcpu->arch.exception.has_payload = events->exception_has_payload; |
4607 | vcpu->arch.exception.payload = events->exception_payload; | |
3cfc3092 | 4608 | |
04140b41 | 4609 | vcpu->arch.interrupt.injected = events->interrupt.injected; |
3cfc3092 JK |
4610 | vcpu->arch.interrupt.nr = events->interrupt.nr; |
4611 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
48005f64 | 4612 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) |
b3646477 JB |
4613 | static_call(kvm_x86_set_interrupt_shadow)(vcpu, |
4614 | events->interrupt.shadow); | |
3cfc3092 JK |
4615 | |
4616 | vcpu->arch.nmi_injected = events->nmi.injected; | |
dab4b911 JK |
4617 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) |
4618 | vcpu->arch.nmi_pending = events->nmi.pending; | |
b3646477 | 4619 | static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked); |
3cfc3092 | 4620 | |
66450a21 | 4621 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && |
bce87cce | 4622 | lapic_in_kernel(vcpu)) |
66450a21 | 4623 | vcpu->arch.apic->sipi_vector = events->sipi_vector; |
3cfc3092 | 4624 | |
f077825a | 4625 | if (events->flags & KVM_VCPUEVENT_VALID_SMM) { |
dc87275f SC |
4626 | if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) |
4627 | kvm_smm_changed(vcpu, events->smi.smm); | |
6ef4e07e | 4628 | |
f077825a | 4629 | vcpu->arch.smi_pending = events->smi.pending; |
f4ef1910 WL |
4630 | |
4631 | if (events->smi.smm) { | |
4632 | if (events->smi.smm_inside_nmi) | |
4633 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; | |
f077825a | 4634 | else |
f4ef1910 | 4635 | vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; |
ff90afa7 LA |
4636 | } |
4637 | ||
4638 | if (lapic_in_kernel(vcpu)) { | |
4639 | if (events->smi.latched_init) | |
4640 | set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
4641 | else | |
4642 | clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
f077825a PB |
4643 | } |
4644 | } | |
4645 | ||
3842d135 AK |
4646 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
4647 | ||
3cfc3092 JK |
4648 | return 0; |
4649 | } | |
4650 | ||
a1efbe77 JK |
4651 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, |
4652 | struct kvm_debugregs *dbgregs) | |
4653 | { | |
73aaf249 JK |
4654 | unsigned long val; |
4655 | ||
a1efbe77 | 4656 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); |
16f8a6f9 | 4657 | kvm_get_dr(vcpu, 6, &val); |
73aaf249 | 4658 | dbgregs->dr6 = val; |
a1efbe77 JK |
4659 | dbgregs->dr7 = vcpu->arch.dr7; |
4660 | dbgregs->flags = 0; | |
97e69aa6 | 4661 | memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); |
a1efbe77 JK |
4662 | } |
4663 | ||
4664 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
4665 | struct kvm_debugregs *dbgregs) | |
4666 | { | |
4667 | if (dbgregs->flags) | |
4668 | return -EINVAL; | |
4669 | ||
fd238002 | 4670 | if (!kvm_dr6_valid(dbgregs->dr6)) |
d14bdb55 | 4671 | return -EINVAL; |
fd238002 | 4672 | if (!kvm_dr7_valid(dbgregs->dr7)) |
d14bdb55 PB |
4673 | return -EINVAL; |
4674 | ||
a1efbe77 | 4675 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); |
ae561ede | 4676 | kvm_update_dr0123(vcpu); |
a1efbe77 JK |
4677 | vcpu->arch.dr6 = dbgregs->dr6; |
4678 | vcpu->arch.dr7 = dbgregs->dr7; | |
9926c9fd | 4679 | kvm_update_dr7(vcpu); |
a1efbe77 | 4680 | |
a1efbe77 JK |
4681 | return 0; |
4682 | } | |
4683 | ||
df1daba7 PB |
4684 | #define XSTATE_COMPACTION_ENABLED (1ULL << 63) |
4685 | ||
4686 | static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) | |
4687 | { | |
b666a4b6 | 4688 | struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; |
400e4b20 | 4689 | u64 xstate_bv = xsave->header.xfeatures; |
df1daba7 PB |
4690 | u64 valid; |
4691 | ||
4692 | /* | |
4693 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
4694 | * leaves 0 and 1 in the loop below. | |
4695 | */ | |
4696 | memcpy(dest, xsave, XSAVE_HDR_OFFSET); | |
4697 | ||
4698 | /* Set XSTATE_BV */ | |
00c87e9a | 4699 | xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE; |
df1daba7 PB |
4700 | *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; |
4701 | ||
4702 | /* | |
4703 | * Copy each region from the possibly compacted offset to the | |
4704 | * non-compacted offset. | |
4705 | */ | |
d91cab78 | 4706 | valid = xstate_bv & ~XFEATURE_MASK_FPSSE; |
df1daba7 | 4707 | while (valid) { |
71ef4533 | 4708 | u32 size, offset, ecx, edx; |
abd16d68 SAS |
4709 | u64 xfeature_mask = valid & -valid; |
4710 | int xfeature_nr = fls64(xfeature_mask) - 1; | |
71ef4533 DH |
4711 | void *src; |
4712 | ||
4713 | cpuid_count(XSTATE_CPUID, xfeature_nr, | |
4714 | &size, &offset, &ecx, &edx); | |
38cfd5e3 | 4715 | |
71ef4533 DH |
4716 | if (xfeature_nr == XFEATURE_PKRU) { |
4717 | memcpy(dest + offset, &vcpu->arch.pkru, | |
4718 | sizeof(vcpu->arch.pkru)); | |
4719 | } else { | |
4720 | src = get_xsave_addr(xsave, xfeature_nr); | |
4721 | if (src) | |
4722 | memcpy(dest + offset, src, size); | |
df1daba7 PB |
4723 | } |
4724 | ||
abd16d68 | 4725 | valid -= xfeature_mask; |
df1daba7 PB |
4726 | } |
4727 | } | |
4728 | ||
4729 | static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) | |
4730 | { | |
b666a4b6 | 4731 | struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; |
df1daba7 PB |
4732 | u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); |
4733 | u64 valid; | |
4734 | ||
4735 | /* | |
4736 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
4737 | * leaves 0 and 1 in the loop below. | |
4738 | */ | |
4739 | memcpy(xsave, src, XSAVE_HDR_OFFSET); | |
4740 | ||
4741 | /* Set XSTATE_BV and possibly XCOMP_BV. */ | |
400e4b20 | 4742 | xsave->header.xfeatures = xstate_bv; |
782511b0 | 4743 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
3a54450b | 4744 | xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; |
df1daba7 PB |
4745 | |
4746 | /* | |
4747 | * Copy each region from the non-compacted offset to the | |
4748 | * possibly compacted offset. | |
4749 | */ | |
d91cab78 | 4750 | valid = xstate_bv & ~XFEATURE_MASK_FPSSE; |
df1daba7 | 4751 | while (valid) { |
71ef4533 | 4752 | u32 size, offset, ecx, edx; |
abd16d68 SAS |
4753 | u64 xfeature_mask = valid & -valid; |
4754 | int xfeature_nr = fls64(xfeature_mask) - 1; | |
71ef4533 DH |
4755 | |
4756 | cpuid_count(XSTATE_CPUID, xfeature_nr, | |
4757 | &size, &offset, &ecx, &edx); | |
4758 | ||
4759 | if (xfeature_nr == XFEATURE_PKRU) { | |
4760 | memcpy(&vcpu->arch.pkru, src + offset, | |
4761 | sizeof(vcpu->arch.pkru)); | |
4762 | } else { | |
4763 | void *dest = get_xsave_addr(xsave, xfeature_nr); | |
4764 | ||
4765 | if (dest) | |
38cfd5e3 | 4766 | memcpy(dest, src + offset, size); |
ee4100da | 4767 | } |
df1daba7 | 4768 | |
abd16d68 | 4769 | valid -= xfeature_mask; |
df1daba7 PB |
4770 | } |
4771 | } | |
4772 | ||
2d5b5a66 SY |
4773 | static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, |
4774 | struct kvm_xsave *guest_xsave) | |
4775 | { | |
ed02b213 TL |
4776 | if (!vcpu->arch.guest_fpu) |
4777 | return; | |
4778 | ||
d366bf7e | 4779 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
df1daba7 PB |
4780 | memset(guest_xsave, 0, sizeof(struct kvm_xsave)); |
4781 | fill_xsave((u8 *) guest_xsave->region, vcpu); | |
4344ee98 | 4782 | } else { |
2d5b5a66 | 4783 | memcpy(guest_xsave->region, |
b666a4b6 | 4784 | &vcpu->arch.guest_fpu->state.fxsave, |
c47ada30 | 4785 | sizeof(struct fxregs_state)); |
2d5b5a66 | 4786 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = |
d91cab78 | 4787 | XFEATURE_MASK_FPSSE; |
2d5b5a66 SY |
4788 | } |
4789 | } | |
4790 | ||
a575813b WL |
4791 | #define XSAVE_MXCSR_OFFSET 24 |
4792 | ||
2d5b5a66 SY |
4793 | static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, |
4794 | struct kvm_xsave *guest_xsave) | |
4795 | { | |
ed02b213 TL |
4796 | u64 xstate_bv; |
4797 | u32 mxcsr; | |
4798 | ||
4799 | if (!vcpu->arch.guest_fpu) | |
4800 | return 0; | |
4801 | ||
4802 | xstate_bv = *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; | |
4803 | mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)]; | |
2d5b5a66 | 4804 | |
d366bf7e | 4805 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
d7876f1b PB |
4806 | /* |
4807 | * Here we allow setting states that are not present in | |
4808 | * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility | |
4809 | * with old userspace. | |
4810 | */ | |
cfc48181 | 4811 | if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask) |
d7876f1b | 4812 | return -EINVAL; |
df1daba7 | 4813 | load_xsave(vcpu, (u8 *)guest_xsave->region); |
d7876f1b | 4814 | } else { |
a575813b WL |
4815 | if (xstate_bv & ~XFEATURE_MASK_FPSSE || |
4816 | mxcsr & ~mxcsr_feature_mask) | |
2d5b5a66 | 4817 | return -EINVAL; |
b666a4b6 | 4818 | memcpy(&vcpu->arch.guest_fpu->state.fxsave, |
c47ada30 | 4819 | guest_xsave->region, sizeof(struct fxregs_state)); |
2d5b5a66 SY |
4820 | } |
4821 | return 0; | |
4822 | } | |
4823 | ||
4824 | static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, | |
4825 | struct kvm_xcrs *guest_xcrs) | |
4826 | { | |
d366bf7e | 4827 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) { |
2d5b5a66 SY |
4828 | guest_xcrs->nr_xcrs = 0; |
4829 | return; | |
4830 | } | |
4831 | ||
4832 | guest_xcrs->nr_xcrs = 1; | |
4833 | guest_xcrs->flags = 0; | |
4834 | guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; | |
4835 | guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; | |
4836 | } | |
4837 | ||
4838 | static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, | |
4839 | struct kvm_xcrs *guest_xcrs) | |
4840 | { | |
4841 | int i, r = 0; | |
4842 | ||
d366bf7e | 4843 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) |
2d5b5a66 SY |
4844 | return -EINVAL; |
4845 | ||
4846 | if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) | |
4847 | return -EINVAL; | |
4848 | ||
4849 | for (i = 0; i < guest_xcrs->nr_xcrs; i++) | |
4850 | /* Only support XCR0 currently */ | |
c67a04cb | 4851 | if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { |
2d5b5a66 | 4852 | r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, |
c67a04cb | 4853 | guest_xcrs->xcrs[i].value); |
2d5b5a66 SY |
4854 | break; |
4855 | } | |
4856 | if (r) | |
4857 | r = -EINVAL; | |
4858 | return r; | |
4859 | } | |
4860 | ||
1c0b28c2 EM |
4861 | /* |
4862 | * kvm_set_guest_paused() indicates to the guest kernel that it has been | |
4863 | * stopped by the hypervisor. This function will be called from the host only. | |
4864 | * EINVAL is returned when the host attempts to set the flag for a guest that | |
4865 | * does not support pv clocks. | |
4866 | */ | |
4867 | static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) | |
4868 | { | |
0b79459b | 4869 | if (!vcpu->arch.pv_time_enabled) |
1c0b28c2 | 4870 | return -EINVAL; |
51d59c6b | 4871 | vcpu->arch.pvclock_set_guest_stopped_request = true; |
1c0b28c2 EM |
4872 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
4873 | return 0; | |
4874 | } | |
4875 | ||
5c919412 AS |
4876 | static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, |
4877 | struct kvm_enable_cap *cap) | |
4878 | { | |
57b119da VK |
4879 | int r; |
4880 | uint16_t vmcs_version; | |
4881 | void __user *user_ptr; | |
4882 | ||
5c919412 AS |
4883 | if (cap->flags) |
4884 | return -EINVAL; | |
4885 | ||
4886 | switch (cap->cap) { | |
efc479e6 RK |
4887 | case KVM_CAP_HYPERV_SYNIC2: |
4888 | if (cap->args[0]) | |
4889 | return -EINVAL; | |
df561f66 | 4890 | fallthrough; |
b2869f28 | 4891 | |
5c919412 | 4892 | case KVM_CAP_HYPERV_SYNIC: |
546d87e5 WL |
4893 | if (!irqchip_in_kernel(vcpu->kvm)) |
4894 | return -EINVAL; | |
efc479e6 RK |
4895 | return kvm_hv_activate_synic(vcpu, cap->cap == |
4896 | KVM_CAP_HYPERV_SYNIC2); | |
57b119da | 4897 | case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: |
33b22172 | 4898 | if (!kvm_x86_ops.nested_ops->enable_evmcs) |
5158917c | 4899 | return -ENOTTY; |
33b22172 | 4900 | r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version); |
57b119da VK |
4901 | if (!r) { |
4902 | user_ptr = (void __user *)(uintptr_t)cap->args[0]; | |
4903 | if (copy_to_user(user_ptr, &vmcs_version, | |
4904 | sizeof(vmcs_version))) | |
4905 | r = -EFAULT; | |
4906 | } | |
4907 | return r; | |
344c6c80 | 4908 | case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: |
afaf0b2f | 4909 | if (!kvm_x86_ops.enable_direct_tlbflush) |
344c6c80 TL |
4910 | return -ENOTTY; |
4911 | ||
b3646477 | 4912 | return static_call(kvm_x86_enable_direct_tlbflush)(vcpu); |
57b119da | 4913 | |
644f7067 VK |
4914 | case KVM_CAP_HYPERV_ENFORCE_CPUID: |
4915 | return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]); | |
4916 | ||
66570e96 OU |
4917 | case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: |
4918 | vcpu->arch.pv_cpuid.enforce = cap->args[0]; | |
01b4f510 OU |
4919 | if (vcpu->arch.pv_cpuid.enforce) |
4920 | kvm_update_pv_runtime(vcpu); | |
66570e96 OU |
4921 | |
4922 | return 0; | |
5c919412 AS |
4923 | default: |
4924 | return -EINVAL; | |
4925 | } | |
4926 | } | |
4927 | ||
313a3dc7 CO |
4928 | long kvm_arch_vcpu_ioctl(struct file *filp, |
4929 | unsigned int ioctl, unsigned long arg) | |
4930 | { | |
4931 | struct kvm_vcpu *vcpu = filp->private_data; | |
4932 | void __user *argp = (void __user *)arg; | |
4933 | int r; | |
d1ac91d8 | 4934 | union { |
6dba9403 | 4935 | struct kvm_sregs2 *sregs2; |
d1ac91d8 AK |
4936 | struct kvm_lapic_state *lapic; |
4937 | struct kvm_xsave *xsave; | |
4938 | struct kvm_xcrs *xcrs; | |
4939 | void *buffer; | |
4940 | } u; | |
4941 | ||
9b062471 CD |
4942 | vcpu_load(vcpu); |
4943 | ||
d1ac91d8 | 4944 | u.buffer = NULL; |
313a3dc7 CO |
4945 | switch (ioctl) { |
4946 | case KVM_GET_LAPIC: { | |
2204ae3c | 4947 | r = -EINVAL; |
bce87cce | 4948 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 4949 | goto out; |
254272ce BG |
4950 | u.lapic = kzalloc(sizeof(struct kvm_lapic_state), |
4951 | GFP_KERNEL_ACCOUNT); | |
313a3dc7 | 4952 | |
b772ff36 | 4953 | r = -ENOMEM; |
d1ac91d8 | 4954 | if (!u.lapic) |
b772ff36 | 4955 | goto out; |
d1ac91d8 | 4956 | r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); |
313a3dc7 CO |
4957 | if (r) |
4958 | goto out; | |
4959 | r = -EFAULT; | |
d1ac91d8 | 4960 | if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
4961 | goto out; |
4962 | r = 0; | |
4963 | break; | |
4964 | } | |
4965 | case KVM_SET_LAPIC: { | |
2204ae3c | 4966 | r = -EINVAL; |
bce87cce | 4967 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 4968 | goto out; |
ff5c2c03 | 4969 | u.lapic = memdup_user(argp, sizeof(*u.lapic)); |
9b062471 CD |
4970 | if (IS_ERR(u.lapic)) { |
4971 | r = PTR_ERR(u.lapic); | |
4972 | goto out_nofree; | |
4973 | } | |
ff5c2c03 | 4974 | |
d1ac91d8 | 4975 | r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); |
313a3dc7 CO |
4976 | break; |
4977 | } | |
f77bc6a4 ZX |
4978 | case KVM_INTERRUPT: { |
4979 | struct kvm_interrupt irq; | |
4980 | ||
4981 | r = -EFAULT; | |
0e96f31e | 4982 | if (copy_from_user(&irq, argp, sizeof(irq))) |
f77bc6a4 ZX |
4983 | goto out; |
4984 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
f77bc6a4 ZX |
4985 | break; |
4986 | } | |
c4abb7c9 JK |
4987 | case KVM_NMI: { |
4988 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
c4abb7c9 JK |
4989 | break; |
4990 | } | |
f077825a PB |
4991 | case KVM_SMI: { |
4992 | r = kvm_vcpu_ioctl_smi(vcpu); | |
4993 | break; | |
4994 | } | |
313a3dc7 CO |
4995 | case KVM_SET_CPUID: { |
4996 | struct kvm_cpuid __user *cpuid_arg = argp; | |
4997 | struct kvm_cpuid cpuid; | |
4998 | ||
4999 | r = -EFAULT; | |
0e96f31e | 5000 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
313a3dc7 CO |
5001 | goto out; |
5002 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
313a3dc7 CO |
5003 | break; |
5004 | } | |
07716717 DK |
5005 | case KVM_SET_CPUID2: { |
5006 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
5007 | struct kvm_cpuid2 cpuid; | |
5008 | ||
5009 | r = -EFAULT; | |
0e96f31e | 5010 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
07716717 DK |
5011 | goto out; |
5012 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 5013 | cpuid_arg->entries); |
07716717 DK |
5014 | break; |
5015 | } | |
5016 | case KVM_GET_CPUID2: { | |
5017 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
5018 | struct kvm_cpuid2 cpuid; | |
5019 | ||
5020 | r = -EFAULT; | |
0e96f31e | 5021 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
07716717 DK |
5022 | goto out; |
5023 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 5024 | cpuid_arg->entries); |
07716717 DK |
5025 | if (r) |
5026 | goto out; | |
5027 | r = -EFAULT; | |
0e96f31e | 5028 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) |
07716717 DK |
5029 | goto out; |
5030 | r = 0; | |
5031 | break; | |
5032 | } | |
801e459a TL |
5033 | case KVM_GET_MSRS: { |
5034 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
609e36d3 | 5035 | r = msr_io(vcpu, argp, do_get_msr, 1); |
801e459a | 5036 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 5037 | break; |
801e459a TL |
5038 | } |
5039 | case KVM_SET_MSRS: { | |
5040 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
313a3dc7 | 5041 | r = msr_io(vcpu, argp, do_set_msr, 0); |
801e459a | 5042 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 5043 | break; |
801e459a | 5044 | } |
b209749f AK |
5045 | case KVM_TPR_ACCESS_REPORTING: { |
5046 | struct kvm_tpr_access_ctl tac; | |
5047 | ||
5048 | r = -EFAULT; | |
0e96f31e | 5049 | if (copy_from_user(&tac, argp, sizeof(tac))) |
b209749f AK |
5050 | goto out; |
5051 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
5052 | if (r) | |
5053 | goto out; | |
5054 | r = -EFAULT; | |
0e96f31e | 5055 | if (copy_to_user(argp, &tac, sizeof(tac))) |
b209749f AK |
5056 | goto out; |
5057 | r = 0; | |
5058 | break; | |
5059 | }; | |
b93463aa AK |
5060 | case KVM_SET_VAPIC_ADDR: { |
5061 | struct kvm_vapic_addr va; | |
7301d6ab | 5062 | int idx; |
b93463aa AK |
5063 | |
5064 | r = -EINVAL; | |
35754c98 | 5065 | if (!lapic_in_kernel(vcpu)) |
b93463aa AK |
5066 | goto out; |
5067 | r = -EFAULT; | |
0e96f31e | 5068 | if (copy_from_user(&va, argp, sizeof(va))) |
b93463aa | 5069 | goto out; |
7301d6ab | 5070 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
fda4e2e8 | 5071 | r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); |
7301d6ab | 5072 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b93463aa AK |
5073 | break; |
5074 | } | |
890ca9ae HY |
5075 | case KVM_X86_SETUP_MCE: { |
5076 | u64 mcg_cap; | |
5077 | ||
5078 | r = -EFAULT; | |
0e96f31e | 5079 | if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) |
890ca9ae HY |
5080 | goto out; |
5081 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
5082 | break; | |
5083 | } | |
5084 | case KVM_X86_SET_MCE: { | |
5085 | struct kvm_x86_mce mce; | |
5086 | ||
5087 | r = -EFAULT; | |
0e96f31e | 5088 | if (copy_from_user(&mce, argp, sizeof(mce))) |
890ca9ae HY |
5089 | goto out; |
5090 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
5091 | break; | |
5092 | } | |
3cfc3092 JK |
5093 | case KVM_GET_VCPU_EVENTS: { |
5094 | struct kvm_vcpu_events events; | |
5095 | ||
5096 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
5097 | ||
5098 | r = -EFAULT; | |
5099 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
5100 | break; | |
5101 | r = 0; | |
5102 | break; | |
5103 | } | |
5104 | case KVM_SET_VCPU_EVENTS: { | |
5105 | struct kvm_vcpu_events events; | |
5106 | ||
5107 | r = -EFAULT; | |
5108 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
5109 | break; | |
5110 | ||
5111 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
5112 | break; | |
5113 | } | |
a1efbe77 JK |
5114 | case KVM_GET_DEBUGREGS: { |
5115 | struct kvm_debugregs dbgregs; | |
5116 | ||
5117 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
5118 | ||
5119 | r = -EFAULT; | |
5120 | if (copy_to_user(argp, &dbgregs, | |
5121 | sizeof(struct kvm_debugregs))) | |
5122 | break; | |
5123 | r = 0; | |
5124 | break; | |
5125 | } | |
5126 | case KVM_SET_DEBUGREGS: { | |
5127 | struct kvm_debugregs dbgregs; | |
5128 | ||
5129 | r = -EFAULT; | |
5130 | if (copy_from_user(&dbgregs, argp, | |
5131 | sizeof(struct kvm_debugregs))) | |
5132 | break; | |
5133 | ||
5134 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
5135 | break; | |
5136 | } | |
2d5b5a66 | 5137 | case KVM_GET_XSAVE: { |
254272ce | 5138 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); |
2d5b5a66 | 5139 | r = -ENOMEM; |
d1ac91d8 | 5140 | if (!u.xsave) |
2d5b5a66 SY |
5141 | break; |
5142 | ||
d1ac91d8 | 5143 | kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
5144 | |
5145 | r = -EFAULT; | |
d1ac91d8 | 5146 | if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
5147 | break; |
5148 | r = 0; | |
5149 | break; | |
5150 | } | |
5151 | case KVM_SET_XSAVE: { | |
ff5c2c03 | 5152 | u.xsave = memdup_user(argp, sizeof(*u.xsave)); |
9b062471 CD |
5153 | if (IS_ERR(u.xsave)) { |
5154 | r = PTR_ERR(u.xsave); | |
5155 | goto out_nofree; | |
5156 | } | |
2d5b5a66 | 5157 | |
d1ac91d8 | 5158 | r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
5159 | break; |
5160 | } | |
5161 | case KVM_GET_XCRS: { | |
254272ce | 5162 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); |
2d5b5a66 | 5163 | r = -ENOMEM; |
d1ac91d8 | 5164 | if (!u.xcrs) |
2d5b5a66 SY |
5165 | break; |
5166 | ||
d1ac91d8 | 5167 | kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
5168 | |
5169 | r = -EFAULT; | |
d1ac91d8 | 5170 | if (copy_to_user(argp, u.xcrs, |
2d5b5a66 SY |
5171 | sizeof(struct kvm_xcrs))) |
5172 | break; | |
5173 | r = 0; | |
5174 | break; | |
5175 | } | |
5176 | case KVM_SET_XCRS: { | |
ff5c2c03 | 5177 | u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); |
9b062471 CD |
5178 | if (IS_ERR(u.xcrs)) { |
5179 | r = PTR_ERR(u.xcrs); | |
5180 | goto out_nofree; | |
5181 | } | |
2d5b5a66 | 5182 | |
d1ac91d8 | 5183 | r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
5184 | break; |
5185 | } | |
92a1f12d JR |
5186 | case KVM_SET_TSC_KHZ: { |
5187 | u32 user_tsc_khz; | |
5188 | ||
5189 | r = -EINVAL; | |
92a1f12d JR |
5190 | user_tsc_khz = (u32)arg; |
5191 | ||
26769f96 MT |
5192 | if (kvm_has_tsc_control && |
5193 | user_tsc_khz >= kvm_max_guest_tsc_khz) | |
92a1f12d JR |
5194 | goto out; |
5195 | ||
cc578287 ZA |
5196 | if (user_tsc_khz == 0) |
5197 | user_tsc_khz = tsc_khz; | |
5198 | ||
381d585c HZ |
5199 | if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) |
5200 | r = 0; | |
92a1f12d | 5201 | |
92a1f12d JR |
5202 | goto out; |
5203 | } | |
5204 | case KVM_GET_TSC_KHZ: { | |
cc578287 | 5205 | r = vcpu->arch.virtual_tsc_khz; |
92a1f12d JR |
5206 | goto out; |
5207 | } | |
1c0b28c2 EM |
5208 | case KVM_KVMCLOCK_CTRL: { |
5209 | r = kvm_set_guest_paused(vcpu); | |
5210 | goto out; | |
5211 | } | |
5c919412 AS |
5212 | case KVM_ENABLE_CAP: { |
5213 | struct kvm_enable_cap cap; | |
5214 | ||
5215 | r = -EFAULT; | |
5216 | if (copy_from_user(&cap, argp, sizeof(cap))) | |
5217 | goto out; | |
5218 | r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); | |
5219 | break; | |
5220 | } | |
8fcc4b59 JM |
5221 | case KVM_GET_NESTED_STATE: { |
5222 | struct kvm_nested_state __user *user_kvm_nested_state = argp; | |
5223 | u32 user_data_size; | |
5224 | ||
5225 | r = -EINVAL; | |
33b22172 | 5226 | if (!kvm_x86_ops.nested_ops->get_state) |
8fcc4b59 JM |
5227 | break; |
5228 | ||
5229 | BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); | |
26b471c7 | 5230 | r = -EFAULT; |
8fcc4b59 | 5231 | if (get_user(user_data_size, &user_kvm_nested_state->size)) |
26b471c7 | 5232 | break; |
8fcc4b59 | 5233 | |
33b22172 PB |
5234 | r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state, |
5235 | user_data_size); | |
8fcc4b59 | 5236 | if (r < 0) |
26b471c7 | 5237 | break; |
8fcc4b59 JM |
5238 | |
5239 | if (r > user_data_size) { | |
5240 | if (put_user(r, &user_kvm_nested_state->size)) | |
26b471c7 LA |
5241 | r = -EFAULT; |
5242 | else | |
5243 | r = -E2BIG; | |
5244 | break; | |
8fcc4b59 | 5245 | } |
26b471c7 | 5246 | |
8fcc4b59 JM |
5247 | r = 0; |
5248 | break; | |
5249 | } | |
5250 | case KVM_SET_NESTED_STATE: { | |
5251 | struct kvm_nested_state __user *user_kvm_nested_state = argp; | |
5252 | struct kvm_nested_state kvm_state; | |
ad5996d9 | 5253 | int idx; |
8fcc4b59 JM |
5254 | |
5255 | r = -EINVAL; | |
33b22172 | 5256 | if (!kvm_x86_ops.nested_ops->set_state) |
8fcc4b59 JM |
5257 | break; |
5258 | ||
26b471c7 | 5259 | r = -EFAULT; |
8fcc4b59 | 5260 | if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) |
26b471c7 | 5261 | break; |
8fcc4b59 | 5262 | |
26b471c7 | 5263 | r = -EINVAL; |
8fcc4b59 | 5264 | if (kvm_state.size < sizeof(kvm_state)) |
26b471c7 | 5265 | break; |
8fcc4b59 JM |
5266 | |
5267 | if (kvm_state.flags & | |
8cab6507 | 5268 | ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE |
cc440cda PB |
5269 | | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING |
5270 | | KVM_STATE_NESTED_GIF_SET)) | |
26b471c7 | 5271 | break; |
8fcc4b59 JM |
5272 | |
5273 | /* nested_run_pending implies guest_mode. */ | |
8cab6507 VK |
5274 | if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) |
5275 | && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) | |
26b471c7 | 5276 | break; |
8fcc4b59 | 5277 | |
ad5996d9 | 5278 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
33b22172 | 5279 | r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state); |
ad5996d9 | 5280 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8fcc4b59 JM |
5281 | break; |
5282 | } | |
c21d54f0 VK |
5283 | case KVM_GET_SUPPORTED_HV_CPUID: |
5284 | r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp); | |
2bc39970 | 5285 | break; |
b59b153d | 5286 | #ifdef CONFIG_KVM_XEN |
3e324615 DW |
5287 | case KVM_XEN_VCPU_GET_ATTR: { |
5288 | struct kvm_xen_vcpu_attr xva; | |
5289 | ||
5290 | r = -EFAULT; | |
5291 | if (copy_from_user(&xva, argp, sizeof(xva))) | |
5292 | goto out; | |
5293 | r = kvm_xen_vcpu_get_attr(vcpu, &xva); | |
5294 | if (!r && copy_to_user(argp, &xva, sizeof(xva))) | |
5295 | r = -EFAULT; | |
5296 | break; | |
5297 | } | |
5298 | case KVM_XEN_VCPU_SET_ATTR: { | |
5299 | struct kvm_xen_vcpu_attr xva; | |
5300 | ||
5301 | r = -EFAULT; | |
5302 | if (copy_from_user(&xva, argp, sizeof(xva))) | |
5303 | goto out; | |
5304 | r = kvm_xen_vcpu_set_attr(vcpu, &xva); | |
5305 | break; | |
5306 | } | |
b59b153d | 5307 | #endif |
6dba9403 ML |
5308 | case KVM_GET_SREGS2: { |
5309 | u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL); | |
5310 | r = -ENOMEM; | |
5311 | if (!u.sregs2) | |
5312 | goto out; | |
5313 | __get_sregs2(vcpu, u.sregs2); | |
5314 | r = -EFAULT; | |
5315 | if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2))) | |
5316 | goto out; | |
5317 | r = 0; | |
5318 | break; | |
5319 | } | |
5320 | case KVM_SET_SREGS2: { | |
5321 | u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2)); | |
5322 | if (IS_ERR(u.sregs2)) { | |
5323 | r = PTR_ERR(u.sregs2); | |
5324 | u.sregs2 = NULL; | |
5325 | goto out; | |
5326 | } | |
5327 | r = __set_sregs2(vcpu, u.sregs2); | |
5328 | break; | |
5329 | } | |
313a3dc7 CO |
5330 | default: |
5331 | r = -EINVAL; | |
5332 | } | |
5333 | out: | |
d1ac91d8 | 5334 | kfree(u.buffer); |
9b062471 CD |
5335 | out_nofree: |
5336 | vcpu_put(vcpu); | |
313a3dc7 CO |
5337 | return r; |
5338 | } | |
5339 | ||
1499fa80 | 5340 | vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) |
5b1c1493 CO |
5341 | { |
5342 | return VM_FAULT_SIGBUS; | |
5343 | } | |
5344 | ||
1fe779f8 CO |
5345 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
5346 | { | |
5347 | int ret; | |
5348 | ||
5349 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
951179ce | 5350 | return -EINVAL; |
b3646477 | 5351 | ret = static_call(kvm_x86_set_tss_addr)(kvm, addr); |
1fe779f8 CO |
5352 | return ret; |
5353 | } | |
5354 | ||
b927a3ce SY |
5355 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
5356 | u64 ident_addr) | |
5357 | { | |
b3646477 | 5358 | return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr); |
b927a3ce SY |
5359 | } |
5360 | ||
1fe779f8 | 5361 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
bc8a3d89 | 5362 | unsigned long kvm_nr_mmu_pages) |
1fe779f8 CO |
5363 | { |
5364 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
5365 | return -EINVAL; | |
5366 | ||
79fac95e | 5367 | mutex_lock(&kvm->slots_lock); |
1fe779f8 CO |
5368 | |
5369 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 5370 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 5371 | |
79fac95e | 5372 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
5373 | return 0; |
5374 | } | |
5375 | ||
bc8a3d89 | 5376 | static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) |
1fe779f8 | 5377 | { |
39de71ec | 5378 | return kvm->arch.n_max_mmu_pages; |
1fe779f8 CO |
5379 | } |
5380 | ||
1fe779f8 CO |
5381 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) |
5382 | { | |
90bca052 | 5383 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
5384 | int r; |
5385 | ||
5386 | r = 0; | |
5387 | switch (chip->chip_id) { | |
5388 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 | 5389 | memcpy(&chip->chip.pic, &pic->pics[0], |
1fe779f8 CO |
5390 | sizeof(struct kvm_pic_state)); |
5391 | break; | |
5392 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 | 5393 | memcpy(&chip->chip.pic, &pic->pics[1], |
1fe779f8 CO |
5394 | sizeof(struct kvm_pic_state)); |
5395 | break; | |
5396 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 5397 | kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
5398 | break; |
5399 | default: | |
5400 | r = -EINVAL; | |
5401 | break; | |
5402 | } | |
5403 | return r; | |
5404 | } | |
5405 | ||
5406 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
5407 | { | |
90bca052 | 5408 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
5409 | int r; |
5410 | ||
5411 | r = 0; | |
5412 | switch (chip->chip_id) { | |
5413 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 DH |
5414 | spin_lock(&pic->lock); |
5415 | memcpy(&pic->pics[0], &chip->chip.pic, | |
1fe779f8 | 5416 | sizeof(struct kvm_pic_state)); |
90bca052 | 5417 | spin_unlock(&pic->lock); |
1fe779f8 CO |
5418 | break; |
5419 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 DH |
5420 | spin_lock(&pic->lock); |
5421 | memcpy(&pic->pics[1], &chip->chip.pic, | |
1fe779f8 | 5422 | sizeof(struct kvm_pic_state)); |
90bca052 | 5423 | spin_unlock(&pic->lock); |
1fe779f8 CO |
5424 | break; |
5425 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 5426 | kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
5427 | break; |
5428 | default: | |
5429 | r = -EINVAL; | |
5430 | break; | |
5431 | } | |
90bca052 | 5432 | kvm_pic_update_irq(pic); |
1fe779f8 CO |
5433 | return r; |
5434 | } | |
5435 | ||
e0f63cb9 SY |
5436 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
5437 | { | |
34f3941c RK |
5438 | struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; |
5439 | ||
5440 | BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); | |
5441 | ||
5442 | mutex_lock(&kps->lock); | |
5443 | memcpy(ps, &kps->channels, sizeof(*ps)); | |
5444 | mutex_unlock(&kps->lock); | |
2da29bcc | 5445 | return 0; |
e0f63cb9 SY |
5446 | } |
5447 | ||
5448 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
5449 | { | |
0185604c | 5450 | int i; |
09edea72 RK |
5451 | struct kvm_pit *pit = kvm->arch.vpit; |
5452 | ||
5453 | mutex_lock(&pit->pit_state.lock); | |
34f3941c | 5454 | memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); |
0185604c | 5455 | for (i = 0; i < 3; i++) |
09edea72 RK |
5456 | kvm_pit_load_count(pit, i, ps->channels[i].count, 0); |
5457 | mutex_unlock(&pit->pit_state.lock); | |
2da29bcc | 5458 | return 0; |
e9f42757 BK |
5459 | } |
5460 | ||
5461 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
5462 | { | |
e9f42757 BK |
5463 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
5464 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
5465 | sizeof(ps->channels)); | |
5466 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
5467 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
97e69aa6 | 5468 | memset(&ps->reserved, 0, sizeof(ps->reserved)); |
2da29bcc | 5469 | return 0; |
e9f42757 BK |
5470 | } |
5471 | ||
5472 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
5473 | { | |
2da29bcc | 5474 | int start = 0; |
0185604c | 5475 | int i; |
e9f42757 | 5476 | u32 prev_legacy, cur_legacy; |
09edea72 RK |
5477 | struct kvm_pit *pit = kvm->arch.vpit; |
5478 | ||
5479 | mutex_lock(&pit->pit_state.lock); | |
5480 | prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
e9f42757 BK |
5481 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; |
5482 | if (!prev_legacy && cur_legacy) | |
5483 | start = 1; | |
09edea72 RK |
5484 | memcpy(&pit->pit_state.channels, &ps->channels, |
5485 | sizeof(pit->pit_state.channels)); | |
5486 | pit->pit_state.flags = ps->flags; | |
0185604c | 5487 | for (i = 0; i < 3; i++) |
09edea72 | 5488 | kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, |
e5e57e7a | 5489 | start && i == 0); |
09edea72 | 5490 | mutex_unlock(&pit->pit_state.lock); |
2da29bcc | 5491 | return 0; |
e0f63cb9 SY |
5492 | } |
5493 | ||
52d939a0 MT |
5494 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
5495 | struct kvm_reinject_control *control) | |
5496 | { | |
71474e2f RK |
5497 | struct kvm_pit *pit = kvm->arch.vpit; |
5498 | ||
71474e2f RK |
5499 | /* pit->pit_state.lock was overloaded to prevent userspace from getting |
5500 | * an inconsistent state after running multiple KVM_REINJECT_CONTROL | |
5501 | * ioctls in parallel. Use a separate lock if that ioctl isn't rare. | |
5502 | */ | |
5503 | mutex_lock(&pit->pit_state.lock); | |
5504 | kvm_pit_set_reinject(pit, control->pit_reinject); | |
5505 | mutex_unlock(&pit->pit_state.lock); | |
b39c90b6 | 5506 | |
52d939a0 MT |
5507 | return 0; |
5508 | } | |
5509 | ||
0dff0846 | 5510 | void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) |
5bb064dc | 5511 | { |
a018eba5 | 5512 | |
88178fd4 | 5513 | /* |
a018eba5 SC |
5514 | * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called |
5515 | * before reporting dirty_bitmap to userspace. KVM flushes the buffers | |
5516 | * on all VM-Exits, thus we only need to kick running vCPUs to force a | |
5517 | * VM-Exit. | |
88178fd4 | 5518 | */ |
a018eba5 SC |
5519 | struct kvm_vcpu *vcpu; |
5520 | int i; | |
5521 | ||
5522 | kvm_for_each_vcpu(i, vcpu, kvm) | |
5523 | kvm_vcpu_kick(vcpu); | |
5bb064dc ZX |
5524 | } |
5525 | ||
aa2fbe6d YZ |
5526 | int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, |
5527 | bool line_status) | |
23d43cf9 CD |
5528 | { |
5529 | if (!irqchip_in_kernel(kvm)) | |
5530 | return -ENXIO; | |
5531 | ||
5532 | irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, | |
aa2fbe6d YZ |
5533 | irq_event->irq, irq_event->level, |
5534 | line_status); | |
23d43cf9 CD |
5535 | return 0; |
5536 | } | |
5537 | ||
e5d83c74 PB |
5538 | int kvm_vm_ioctl_enable_cap(struct kvm *kvm, |
5539 | struct kvm_enable_cap *cap) | |
90de4a18 NA |
5540 | { |
5541 | int r; | |
5542 | ||
5543 | if (cap->flags) | |
5544 | return -EINVAL; | |
5545 | ||
5546 | switch (cap->cap) { | |
5547 | case KVM_CAP_DISABLE_QUIRKS: | |
5548 | kvm->arch.disabled_quirks = cap->args[0]; | |
5549 | r = 0; | |
5550 | break; | |
49df6397 SR |
5551 | case KVM_CAP_SPLIT_IRQCHIP: { |
5552 | mutex_lock(&kvm->lock); | |
b053b2ae SR |
5553 | r = -EINVAL; |
5554 | if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) | |
5555 | goto split_irqchip_unlock; | |
49df6397 SR |
5556 | r = -EEXIST; |
5557 | if (irqchip_in_kernel(kvm)) | |
5558 | goto split_irqchip_unlock; | |
557abc40 | 5559 | if (kvm->created_vcpus) |
49df6397 SR |
5560 | goto split_irqchip_unlock; |
5561 | r = kvm_setup_empty_irq_routing(kvm); | |
5c0aea0e | 5562 | if (r) |
49df6397 SR |
5563 | goto split_irqchip_unlock; |
5564 | /* Pairs with irqchip_in_kernel. */ | |
5565 | smp_wmb(); | |
49776faf | 5566 | kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; |
b053b2ae | 5567 | kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; |
49df6397 SR |
5568 | r = 0; |
5569 | split_irqchip_unlock: | |
5570 | mutex_unlock(&kvm->lock); | |
5571 | break; | |
5572 | } | |
37131313 RK |
5573 | case KVM_CAP_X2APIC_API: |
5574 | r = -EINVAL; | |
5575 | if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) | |
5576 | break; | |
5577 | ||
5578 | if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) | |
5579 | kvm->arch.x2apic_format = true; | |
c519265f RK |
5580 | if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) |
5581 | kvm->arch.x2apic_broadcast_quirk_disabled = true; | |
37131313 RK |
5582 | |
5583 | r = 0; | |
5584 | break; | |
4d5422ce WL |
5585 | case KVM_CAP_X86_DISABLE_EXITS: |
5586 | r = -EINVAL; | |
5587 | if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) | |
5588 | break; | |
5589 | ||
5590 | if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && | |
5591 | kvm_can_mwait_in_guest()) | |
5592 | kvm->arch.mwait_in_guest = true; | |
766d3571 | 5593 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) |
caa057a2 | 5594 | kvm->arch.hlt_in_guest = true; |
b31c114b WL |
5595 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) |
5596 | kvm->arch.pause_in_guest = true; | |
b5170063 WL |
5597 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) |
5598 | kvm->arch.cstate_in_guest = true; | |
4d5422ce WL |
5599 | r = 0; |
5600 | break; | |
6fbbde9a DS |
5601 | case KVM_CAP_MSR_PLATFORM_INFO: |
5602 | kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; | |
5603 | r = 0; | |
c4f55198 JM |
5604 | break; |
5605 | case KVM_CAP_EXCEPTION_PAYLOAD: | |
5606 | kvm->arch.exception_payload_enabled = cap->args[0]; | |
5607 | r = 0; | |
6fbbde9a | 5608 | break; |
1ae09954 AG |
5609 | case KVM_CAP_X86_USER_SPACE_MSR: |
5610 | kvm->arch.user_space_msr_mask = cap->args[0]; | |
5611 | r = 0; | |
5612 | break; | |
fe6b6bc8 CQ |
5613 | case KVM_CAP_X86_BUS_LOCK_EXIT: |
5614 | r = -EINVAL; | |
5615 | if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE) | |
5616 | break; | |
5617 | ||
5618 | if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) && | |
5619 | (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)) | |
5620 | break; | |
5621 | ||
5622 | if (kvm_has_bus_lock_exit && | |
5623 | cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT) | |
5624 | kvm->arch.bus_lock_detection_enabled = true; | |
5625 | r = 0; | |
5626 | break; | |
fe7e9488 SC |
5627 | #ifdef CONFIG_X86_SGX_KVM |
5628 | case KVM_CAP_SGX_ATTRIBUTE: { | |
5629 | unsigned long allowed_attributes = 0; | |
5630 | ||
5631 | r = sgx_set_attribute(&allowed_attributes, cap->args[0]); | |
5632 | if (r) | |
5633 | break; | |
5634 | ||
5635 | /* KVM only supports the PROVISIONKEY privileged attribute. */ | |
5636 | if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) && | |
5637 | !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY)) | |
5638 | kvm->arch.sgx_provisioning_allowed = true; | |
5639 | else | |
5640 | r = -EINVAL; | |
5641 | break; | |
5642 | } | |
5643 | #endif | |
54526d1f NT |
5644 | case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: |
5645 | r = -EINVAL; | |
5646 | if (kvm_x86_ops.vm_copy_enc_context_from) | |
5647 | r = kvm_x86_ops.vm_copy_enc_context_from(kvm, cap->args[0]); | |
5648 | return r; | |
0dbb1123 AK |
5649 | case KVM_CAP_EXIT_HYPERCALL: |
5650 | if (cap->args[0] & ~KVM_EXIT_HYPERCALL_VALID_MASK) { | |
5651 | r = -EINVAL; | |
5652 | break; | |
5653 | } | |
5654 | kvm->arch.hypercall_exit_enabled = cap->args[0]; | |
5655 | r = 0; | |
5656 | break; | |
19238e75 AL |
5657 | case KVM_CAP_EXIT_ON_EMULATION_FAILURE: |
5658 | r = -EINVAL; | |
5659 | if (cap->args[0] & ~1) | |
5660 | break; | |
5661 | kvm->arch.exit_on_emulation_error = cap->args[0]; | |
5662 | r = 0; | |
5663 | break; | |
90de4a18 NA |
5664 | default: |
5665 | r = -EINVAL; | |
5666 | break; | |
5667 | } | |
5668 | return r; | |
5669 | } | |
5670 | ||
b318e8de SC |
5671 | static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow) |
5672 | { | |
5673 | struct kvm_x86_msr_filter *msr_filter; | |
5674 | ||
5675 | msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT); | |
5676 | if (!msr_filter) | |
5677 | return NULL; | |
5678 | ||
5679 | msr_filter->default_allow = default_allow; | |
5680 | return msr_filter; | |
5681 | } | |
5682 | ||
5683 | static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter) | |
1a155254 AG |
5684 | { |
5685 | u32 i; | |
1a155254 | 5686 | |
b318e8de SC |
5687 | if (!msr_filter) |
5688 | return; | |
5689 | ||
5690 | for (i = 0; i < msr_filter->count; i++) | |
5691 | kfree(msr_filter->ranges[i].bitmap); | |
1a155254 | 5692 | |
b318e8de | 5693 | kfree(msr_filter); |
1a155254 AG |
5694 | } |
5695 | ||
b318e8de SC |
5696 | static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter, |
5697 | struct kvm_msr_filter_range *user_range) | |
1a155254 | 5698 | { |
1a155254 AG |
5699 | unsigned long *bitmap = NULL; |
5700 | size_t bitmap_size; | |
1a155254 AG |
5701 | |
5702 | if (!user_range->nmsrs) | |
5703 | return 0; | |
5704 | ||
aca35288 SC |
5705 | if (user_range->flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) |
5706 | return -EINVAL; | |
5707 | ||
5708 | if (!user_range->flags) | |
5709 | return -EINVAL; | |
5710 | ||
1a155254 AG |
5711 | bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long); |
5712 | if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE) | |
5713 | return -EINVAL; | |
5714 | ||
5715 | bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size); | |
5716 | if (IS_ERR(bitmap)) | |
5717 | return PTR_ERR(bitmap); | |
5718 | ||
aca35288 | 5719 | msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) { |
1a155254 AG |
5720 | .flags = user_range->flags, |
5721 | .base = user_range->base, | |
5722 | .nmsrs = user_range->nmsrs, | |
5723 | .bitmap = bitmap, | |
5724 | }; | |
5725 | ||
b318e8de | 5726 | msr_filter->count++; |
1a155254 | 5727 | return 0; |
1a155254 AG |
5728 | } |
5729 | ||
5730 | static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp) | |
5731 | { | |
5732 | struct kvm_msr_filter __user *user_msr_filter = argp; | |
b318e8de | 5733 | struct kvm_x86_msr_filter *new_filter, *old_filter; |
1a155254 AG |
5734 | struct kvm_msr_filter filter; |
5735 | bool default_allow; | |
043248b3 | 5736 | bool empty = true; |
b318e8de | 5737 | int r = 0; |
1a155254 AG |
5738 | u32 i; |
5739 | ||
5740 | if (copy_from_user(&filter, user_msr_filter, sizeof(filter))) | |
5741 | return -EFAULT; | |
5742 | ||
043248b3 PB |
5743 | for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) |
5744 | empty &= !filter.ranges[i].nmsrs; | |
1a155254 AG |
5745 | |
5746 | default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY); | |
043248b3 PB |
5747 | if (empty && !default_allow) |
5748 | return -EINVAL; | |
5749 | ||
b318e8de SC |
5750 | new_filter = kvm_alloc_msr_filter(default_allow); |
5751 | if (!new_filter) | |
5752 | return -ENOMEM; | |
1a155254 | 5753 | |
1a155254 | 5754 | for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) { |
b318e8de SC |
5755 | r = kvm_add_msr_filter(new_filter, &filter.ranges[i]); |
5756 | if (r) { | |
5757 | kvm_free_msr_filter(new_filter); | |
5758 | return r; | |
5759 | } | |
1a155254 AG |
5760 | } |
5761 | ||
b318e8de SC |
5762 | mutex_lock(&kvm->lock); |
5763 | ||
5764 | /* The per-VM filter is protected by kvm->lock... */ | |
5765 | old_filter = srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1); | |
5766 | ||
5767 | rcu_assign_pointer(kvm->arch.msr_filter, new_filter); | |
5768 | synchronize_srcu(&kvm->srcu); | |
5769 | ||
5770 | kvm_free_msr_filter(old_filter); | |
5771 | ||
1a155254 AG |
5772 | kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED); |
5773 | mutex_unlock(&kvm->lock); | |
5774 | ||
b318e8de | 5775 | return 0; |
1a155254 AG |
5776 | } |
5777 | ||
7d62874f SS |
5778 | #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER |
5779 | static int kvm_arch_suspend_notifier(struct kvm *kvm) | |
5780 | { | |
5781 | struct kvm_vcpu *vcpu; | |
5782 | int i, ret = 0; | |
5783 | ||
5784 | mutex_lock(&kvm->lock); | |
5785 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
5786 | if (!vcpu->arch.pv_time_enabled) | |
5787 | continue; | |
5788 | ||
5789 | ret = kvm_set_guest_paused(vcpu); | |
5790 | if (ret) { | |
5791 | kvm_err("Failed to pause guest VCPU%d: %d\n", | |
5792 | vcpu->vcpu_id, ret); | |
5793 | break; | |
5794 | } | |
5795 | } | |
5796 | mutex_unlock(&kvm->lock); | |
5797 | ||
5798 | return ret ? NOTIFY_BAD : NOTIFY_DONE; | |
5799 | } | |
5800 | ||
5801 | int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state) | |
5802 | { | |
5803 | switch (state) { | |
5804 | case PM_HIBERNATION_PREPARE: | |
5805 | case PM_SUSPEND_PREPARE: | |
5806 | return kvm_arch_suspend_notifier(kvm); | |
5807 | } | |
5808 | ||
5809 | return NOTIFY_DONE; | |
5810 | } | |
5811 | #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */ | |
5812 | ||
1fe779f8 CO |
5813 | long kvm_arch_vm_ioctl(struct file *filp, |
5814 | unsigned int ioctl, unsigned long arg) | |
5815 | { | |
5816 | struct kvm *kvm = filp->private_data; | |
5817 | void __user *argp = (void __user *)arg; | |
367e1319 | 5818 | int r = -ENOTTY; |
f0d66275 DH |
5819 | /* |
5820 | * This union makes it completely explicit to gcc-3.x | |
5821 | * that these two variables' stack usage should be | |
5822 | * combined, not added together. | |
5823 | */ | |
5824 | union { | |
5825 | struct kvm_pit_state ps; | |
e9f42757 | 5826 | struct kvm_pit_state2 ps2; |
c5ff41ce | 5827 | struct kvm_pit_config pit_config; |
f0d66275 | 5828 | } u; |
1fe779f8 CO |
5829 | |
5830 | switch (ioctl) { | |
5831 | case KVM_SET_TSS_ADDR: | |
5832 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
1fe779f8 | 5833 | break; |
b927a3ce SY |
5834 | case KVM_SET_IDENTITY_MAP_ADDR: { |
5835 | u64 ident_addr; | |
5836 | ||
1af1ac91 DH |
5837 | mutex_lock(&kvm->lock); |
5838 | r = -EINVAL; | |
5839 | if (kvm->created_vcpus) | |
5840 | goto set_identity_unlock; | |
b927a3ce | 5841 | r = -EFAULT; |
0e96f31e | 5842 | if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) |
1af1ac91 | 5843 | goto set_identity_unlock; |
b927a3ce | 5844 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); |
1af1ac91 DH |
5845 | set_identity_unlock: |
5846 | mutex_unlock(&kvm->lock); | |
b927a3ce SY |
5847 | break; |
5848 | } | |
1fe779f8 CO |
5849 | case KVM_SET_NR_MMU_PAGES: |
5850 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
1fe779f8 CO |
5851 | break; |
5852 | case KVM_GET_NR_MMU_PAGES: | |
5853 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
5854 | break; | |
3ddea128 | 5855 | case KVM_CREATE_IRQCHIP: { |
3ddea128 | 5856 | mutex_lock(&kvm->lock); |
09941366 | 5857 | |
3ddea128 | 5858 | r = -EEXIST; |
35e6eaa3 | 5859 | if (irqchip_in_kernel(kvm)) |
3ddea128 | 5860 | goto create_irqchip_unlock; |
09941366 | 5861 | |
3e515705 | 5862 | r = -EINVAL; |
557abc40 | 5863 | if (kvm->created_vcpus) |
3e515705 | 5864 | goto create_irqchip_unlock; |
09941366 RK |
5865 | |
5866 | r = kvm_pic_init(kvm); | |
5867 | if (r) | |
3ddea128 | 5868 | goto create_irqchip_unlock; |
09941366 RK |
5869 | |
5870 | r = kvm_ioapic_init(kvm); | |
5871 | if (r) { | |
09941366 | 5872 | kvm_pic_destroy(kvm); |
3ddea128 | 5873 | goto create_irqchip_unlock; |
09941366 RK |
5874 | } |
5875 | ||
399ec807 AK |
5876 | r = kvm_setup_default_irq_routing(kvm); |
5877 | if (r) { | |
72bb2fcd | 5878 | kvm_ioapic_destroy(kvm); |
09941366 | 5879 | kvm_pic_destroy(kvm); |
71ba994c | 5880 | goto create_irqchip_unlock; |
399ec807 | 5881 | } |
49776faf | 5882 | /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ |
71ba994c | 5883 | smp_wmb(); |
49776faf | 5884 | kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; |
3ddea128 MT |
5885 | create_irqchip_unlock: |
5886 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 5887 | break; |
3ddea128 | 5888 | } |
7837699f | 5889 | case KVM_CREATE_PIT: |
c5ff41ce JK |
5890 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
5891 | goto create_pit; | |
5892 | case KVM_CREATE_PIT2: | |
5893 | r = -EFAULT; | |
5894 | if (copy_from_user(&u.pit_config, argp, | |
5895 | sizeof(struct kvm_pit_config))) | |
5896 | goto out; | |
5897 | create_pit: | |
250715a6 | 5898 | mutex_lock(&kvm->lock); |
269e05e4 AK |
5899 | r = -EEXIST; |
5900 | if (kvm->arch.vpit) | |
5901 | goto create_pit_unlock; | |
7837699f | 5902 | r = -ENOMEM; |
c5ff41ce | 5903 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
5904 | if (kvm->arch.vpit) |
5905 | r = 0; | |
269e05e4 | 5906 | create_pit_unlock: |
250715a6 | 5907 | mutex_unlock(&kvm->lock); |
7837699f | 5908 | break; |
1fe779f8 CO |
5909 | case KVM_GET_IRQCHIP: { |
5910 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 5911 | struct kvm_irqchip *chip; |
1fe779f8 | 5912 | |
ff5c2c03 SL |
5913 | chip = memdup_user(argp, sizeof(*chip)); |
5914 | if (IS_ERR(chip)) { | |
5915 | r = PTR_ERR(chip); | |
1fe779f8 | 5916 | goto out; |
ff5c2c03 SL |
5917 | } |
5918 | ||
1fe779f8 | 5919 | r = -ENXIO; |
826da321 | 5920 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
5921 | goto get_irqchip_out; |
5922 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 5923 | if (r) |
f0d66275 | 5924 | goto get_irqchip_out; |
1fe779f8 | 5925 | r = -EFAULT; |
0e96f31e | 5926 | if (copy_to_user(argp, chip, sizeof(*chip))) |
f0d66275 | 5927 | goto get_irqchip_out; |
1fe779f8 | 5928 | r = 0; |
f0d66275 DH |
5929 | get_irqchip_out: |
5930 | kfree(chip); | |
1fe779f8 CO |
5931 | break; |
5932 | } | |
5933 | case KVM_SET_IRQCHIP: { | |
5934 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 5935 | struct kvm_irqchip *chip; |
1fe779f8 | 5936 | |
ff5c2c03 SL |
5937 | chip = memdup_user(argp, sizeof(*chip)); |
5938 | if (IS_ERR(chip)) { | |
5939 | r = PTR_ERR(chip); | |
1fe779f8 | 5940 | goto out; |
ff5c2c03 SL |
5941 | } |
5942 | ||
1fe779f8 | 5943 | r = -ENXIO; |
826da321 | 5944 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
5945 | goto set_irqchip_out; |
5946 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
f0d66275 DH |
5947 | set_irqchip_out: |
5948 | kfree(chip); | |
1fe779f8 CO |
5949 | break; |
5950 | } | |
e0f63cb9 | 5951 | case KVM_GET_PIT: { |
e0f63cb9 | 5952 | r = -EFAULT; |
f0d66275 | 5953 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
5954 | goto out; |
5955 | r = -ENXIO; | |
5956 | if (!kvm->arch.vpit) | |
5957 | goto out; | |
f0d66275 | 5958 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
5959 | if (r) |
5960 | goto out; | |
5961 | r = -EFAULT; | |
f0d66275 | 5962 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
5963 | goto out; |
5964 | r = 0; | |
5965 | break; | |
5966 | } | |
5967 | case KVM_SET_PIT: { | |
e0f63cb9 | 5968 | r = -EFAULT; |
0e96f31e | 5969 | if (copy_from_user(&u.ps, argp, sizeof(u.ps))) |
e0f63cb9 | 5970 | goto out; |
7289fdb5 | 5971 | mutex_lock(&kvm->lock); |
e0f63cb9 SY |
5972 | r = -ENXIO; |
5973 | if (!kvm->arch.vpit) | |
7289fdb5 | 5974 | goto set_pit_out; |
f0d66275 | 5975 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
7289fdb5 SR |
5976 | set_pit_out: |
5977 | mutex_unlock(&kvm->lock); | |
e0f63cb9 SY |
5978 | break; |
5979 | } | |
e9f42757 BK |
5980 | case KVM_GET_PIT2: { |
5981 | r = -ENXIO; | |
5982 | if (!kvm->arch.vpit) | |
5983 | goto out; | |
5984 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
5985 | if (r) | |
5986 | goto out; | |
5987 | r = -EFAULT; | |
5988 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
5989 | goto out; | |
5990 | r = 0; | |
5991 | break; | |
5992 | } | |
5993 | case KVM_SET_PIT2: { | |
5994 | r = -EFAULT; | |
5995 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
5996 | goto out; | |
7289fdb5 | 5997 | mutex_lock(&kvm->lock); |
e9f42757 BK |
5998 | r = -ENXIO; |
5999 | if (!kvm->arch.vpit) | |
7289fdb5 | 6000 | goto set_pit2_out; |
e9f42757 | 6001 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); |
7289fdb5 SR |
6002 | set_pit2_out: |
6003 | mutex_unlock(&kvm->lock); | |
e9f42757 BK |
6004 | break; |
6005 | } | |
52d939a0 MT |
6006 | case KVM_REINJECT_CONTROL: { |
6007 | struct kvm_reinject_control control; | |
6008 | r = -EFAULT; | |
6009 | if (copy_from_user(&control, argp, sizeof(control))) | |
6010 | goto out; | |
cad23e72 ML |
6011 | r = -ENXIO; |
6012 | if (!kvm->arch.vpit) | |
6013 | goto out; | |
52d939a0 | 6014 | r = kvm_vm_ioctl_reinject(kvm, &control); |
52d939a0 MT |
6015 | break; |
6016 | } | |
d71ba788 PB |
6017 | case KVM_SET_BOOT_CPU_ID: |
6018 | r = 0; | |
6019 | mutex_lock(&kvm->lock); | |
557abc40 | 6020 | if (kvm->created_vcpus) |
d71ba788 PB |
6021 | r = -EBUSY; |
6022 | else | |
6023 | kvm->arch.bsp_vcpu_id = arg; | |
6024 | mutex_unlock(&kvm->lock); | |
6025 | break; | |
b59b153d | 6026 | #ifdef CONFIG_KVM_XEN |
ffde22ac | 6027 | case KVM_XEN_HVM_CONFIG: { |
51776043 | 6028 | struct kvm_xen_hvm_config xhc; |
ffde22ac | 6029 | r = -EFAULT; |
51776043 | 6030 | if (copy_from_user(&xhc, argp, sizeof(xhc))) |
ffde22ac | 6031 | goto out; |
78e9878c | 6032 | r = kvm_xen_hvm_config(kvm, &xhc); |
ffde22ac ES |
6033 | break; |
6034 | } | |
a76b9641 JM |
6035 | case KVM_XEN_HVM_GET_ATTR: { |
6036 | struct kvm_xen_hvm_attr xha; | |
6037 | ||
6038 | r = -EFAULT; | |
6039 | if (copy_from_user(&xha, argp, sizeof(xha))) | |
ffde22ac | 6040 | goto out; |
a76b9641 JM |
6041 | r = kvm_xen_hvm_get_attr(kvm, &xha); |
6042 | if (!r && copy_to_user(argp, &xha, sizeof(xha))) | |
6043 | r = -EFAULT; | |
6044 | break; | |
6045 | } | |
6046 | case KVM_XEN_HVM_SET_ATTR: { | |
6047 | struct kvm_xen_hvm_attr xha; | |
6048 | ||
6049 | r = -EFAULT; | |
6050 | if (copy_from_user(&xha, argp, sizeof(xha))) | |
6051 | goto out; | |
6052 | r = kvm_xen_hvm_set_attr(kvm, &xha); | |
ffde22ac ES |
6053 | break; |
6054 | } | |
b59b153d | 6055 | #endif |
afbcf7ab | 6056 | case KVM_SET_CLOCK: { |
77fcbe82 | 6057 | struct kvm_arch *ka = &kvm->arch; |
afbcf7ab GC |
6058 | struct kvm_clock_data user_ns; |
6059 | u64 now_ns; | |
afbcf7ab GC |
6060 | |
6061 | r = -EFAULT; | |
6062 | if (copy_from_user(&user_ns, argp, sizeof(user_ns))) | |
6063 | goto out; | |
6064 | ||
6065 | r = -EINVAL; | |
6066 | if (user_ns.flags) | |
6067 | goto out; | |
6068 | ||
6069 | r = 0; | |
0bc48bea RK |
6070 | /* |
6071 | * TODO: userspace has to take care of races with VCPU_RUN, so | |
6072 | * kvm_gen_update_masterclock() can be cut down to locked | |
6073 | * pvclock_update_vm_gtod_copy(). | |
6074 | */ | |
6075 | kvm_gen_update_masterclock(kvm); | |
77fcbe82 VK |
6076 | |
6077 | /* | |
6078 | * This pairs with kvm_guest_time_update(): when masterclock is | |
6079 | * in use, we use master_kernel_ns + kvmclock_offset to set | |
6080 | * unsigned 'system_time' so if we use get_kvmclock_ns() (which | |
6081 | * is slightly ahead) here we risk going negative on unsigned | |
6082 | * 'system_time' when 'user_ns.clock' is very small. | |
6083 | */ | |
6084 | spin_lock_irq(&ka->pvclock_gtod_sync_lock); | |
6085 | if (kvm->arch.use_master_clock) | |
6086 | now_ns = ka->master_kernel_ns; | |
6087 | else | |
6088 | now_ns = get_kvmclock_base_ns(); | |
6089 | ka->kvmclock_offset = user_ns.clock - now_ns; | |
6090 | spin_unlock_irq(&ka->pvclock_gtod_sync_lock); | |
6091 | ||
0bc48bea | 6092 | kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE); |
afbcf7ab GC |
6093 | break; |
6094 | } | |
6095 | case KVM_GET_CLOCK: { | |
afbcf7ab GC |
6096 | struct kvm_clock_data user_ns; |
6097 | u64 now_ns; | |
6098 | ||
e891a32e | 6099 | now_ns = get_kvmclock_ns(kvm); |
108b249c | 6100 | user_ns.clock = now_ns; |
e3fd9a93 | 6101 | user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; |
97e69aa6 | 6102 | memset(&user_ns.pad, 0, sizeof(user_ns.pad)); |
afbcf7ab GC |
6103 | |
6104 | r = -EFAULT; | |
6105 | if (copy_to_user(argp, &user_ns, sizeof(user_ns))) | |
6106 | goto out; | |
6107 | r = 0; | |
6108 | break; | |
6109 | } | |
5acc5c06 BS |
6110 | case KVM_MEMORY_ENCRYPT_OP: { |
6111 | r = -ENOTTY; | |
afaf0b2f | 6112 | if (kvm_x86_ops.mem_enc_op) |
b3646477 | 6113 | r = static_call(kvm_x86_mem_enc_op)(kvm, argp); |
5acc5c06 BS |
6114 | break; |
6115 | } | |
69eaedee BS |
6116 | case KVM_MEMORY_ENCRYPT_REG_REGION: { |
6117 | struct kvm_enc_region region; | |
6118 | ||
6119 | r = -EFAULT; | |
6120 | if (copy_from_user(®ion, argp, sizeof(region))) | |
6121 | goto out; | |
6122 | ||
6123 | r = -ENOTTY; | |
afaf0b2f | 6124 | if (kvm_x86_ops.mem_enc_reg_region) |
b3646477 | 6125 | r = static_call(kvm_x86_mem_enc_reg_region)(kvm, ®ion); |
69eaedee BS |
6126 | break; |
6127 | } | |
6128 | case KVM_MEMORY_ENCRYPT_UNREG_REGION: { | |
6129 | struct kvm_enc_region region; | |
6130 | ||
6131 | r = -EFAULT; | |
6132 | if (copy_from_user(®ion, argp, sizeof(region))) | |
6133 | goto out; | |
6134 | ||
6135 | r = -ENOTTY; | |
afaf0b2f | 6136 | if (kvm_x86_ops.mem_enc_unreg_region) |
b3646477 | 6137 | r = static_call(kvm_x86_mem_enc_unreg_region)(kvm, ®ion); |
69eaedee BS |
6138 | break; |
6139 | } | |
faeb7833 RK |
6140 | case KVM_HYPERV_EVENTFD: { |
6141 | struct kvm_hyperv_eventfd hvevfd; | |
6142 | ||
6143 | r = -EFAULT; | |
6144 | if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) | |
6145 | goto out; | |
6146 | r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); | |
6147 | break; | |
6148 | } | |
66bb8a06 EH |
6149 | case KVM_SET_PMU_EVENT_FILTER: |
6150 | r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); | |
6151 | break; | |
1a155254 AG |
6152 | case KVM_X86_SET_MSR_FILTER: |
6153 | r = kvm_vm_ioctl_set_msr_filter(kvm, argp); | |
6154 | break; | |
1fe779f8 | 6155 | default: |
ad6260da | 6156 | r = -ENOTTY; |
1fe779f8 CO |
6157 | } |
6158 | out: | |
6159 | return r; | |
6160 | } | |
6161 | ||
a16b043c | 6162 | static void kvm_init_msr_list(void) |
043405e1 | 6163 | { |
24c29b7a | 6164 | struct x86_pmu_capability x86_pmu; |
043405e1 | 6165 | u32 dummy[2]; |
7a5ee6ed | 6166 | unsigned i; |
043405e1 | 6167 | |
e2ada66e | 6168 | BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4, |
7a5ee6ed | 6169 | "Please update the fixed PMCs in msrs_to_saved_all[]"); |
24c29b7a PB |
6170 | |
6171 | perf_get_x86_pmu_capability(&x86_pmu); | |
e2ada66e | 6172 | |
6cbee2b9 XL |
6173 | num_msrs_to_save = 0; |
6174 | num_emulated_msrs = 0; | |
6175 | num_msr_based_features = 0; | |
6176 | ||
7a5ee6ed CQ |
6177 | for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) { |
6178 | if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0) | |
043405e1 | 6179 | continue; |
93c4adc7 PB |
6180 | |
6181 | /* | |
6182 | * Even MSRs that are valid in the host may not be exposed | |
9dbe6cf9 | 6183 | * to the guests in some cases. |
93c4adc7 | 6184 | */ |
7a5ee6ed | 6185 | switch (msrs_to_save_all[i]) { |
93c4adc7 | 6186 | case MSR_IA32_BNDCFGS: |
503234b3 | 6187 | if (!kvm_mpx_supported()) |
93c4adc7 PB |
6188 | continue; |
6189 | break; | |
9dbe6cf9 | 6190 | case MSR_TSC_AUX: |
36fa06f9 SC |
6191 | if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) && |
6192 | !kvm_cpu_cap_has(X86_FEATURE_RDPID)) | |
9dbe6cf9 PB |
6193 | continue; |
6194 | break; | |
f4cfcd2d ML |
6195 | case MSR_IA32_UMWAIT_CONTROL: |
6196 | if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG)) | |
6197 | continue; | |
6198 | break; | |
bf8c55d8 CP |
6199 | case MSR_IA32_RTIT_CTL: |
6200 | case MSR_IA32_RTIT_STATUS: | |
7b874c26 | 6201 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) |
bf8c55d8 CP |
6202 | continue; |
6203 | break; | |
6204 | case MSR_IA32_RTIT_CR3_MATCH: | |
7b874c26 | 6205 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
bf8c55d8 CP |
6206 | !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) |
6207 | continue; | |
6208 | break; | |
6209 | case MSR_IA32_RTIT_OUTPUT_BASE: | |
6210 | case MSR_IA32_RTIT_OUTPUT_MASK: | |
7b874c26 | 6211 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
bf8c55d8 CP |
6212 | (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && |
6213 | !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) | |
6214 | continue; | |
6215 | break; | |
7cb85fc4 | 6216 | case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: |
7b874c26 | 6217 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
7a5ee6ed | 6218 | msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >= |
bf8c55d8 CP |
6219 | intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) |
6220 | continue; | |
6221 | break; | |
cf05a67b | 6222 | case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17: |
7a5ee6ed | 6223 | if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >= |
24c29b7a PB |
6224 | min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) |
6225 | continue; | |
6226 | break; | |
cf05a67b | 6227 | case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17: |
7a5ee6ed | 6228 | if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= |
24c29b7a PB |
6229 | min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) |
6230 | continue; | |
7cb85fc4 | 6231 | break; |
93c4adc7 PB |
6232 | default: |
6233 | break; | |
6234 | } | |
6235 | ||
7a5ee6ed | 6236 | msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i]; |
043405e1 | 6237 | } |
62ef68bb | 6238 | |
7a5ee6ed | 6239 | for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) { |
b3646477 | 6240 | if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i])) |
bc226f07 | 6241 | continue; |
62ef68bb | 6242 | |
7a5ee6ed | 6243 | emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i]; |
62ef68bb | 6244 | } |
801e459a | 6245 | |
7a5ee6ed | 6246 | for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) { |
801e459a TL |
6247 | struct kvm_msr_entry msr; |
6248 | ||
7a5ee6ed | 6249 | msr.index = msr_based_features_all[i]; |
66421c1e | 6250 | if (kvm_get_msr_feature(&msr)) |
801e459a TL |
6251 | continue; |
6252 | ||
7a5ee6ed | 6253 | msr_based_features[num_msr_based_features++] = msr_based_features_all[i]; |
801e459a | 6254 | } |
043405e1 CO |
6255 | } |
6256 | ||
bda9020e MT |
6257 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
6258 | const void *v) | |
bbd9b64e | 6259 | { |
70252a10 AK |
6260 | int handled = 0; |
6261 | int n; | |
6262 | ||
6263 | do { | |
6264 | n = min(len, 8); | |
bce87cce | 6265 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
6266 | !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) |
6267 | && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 AK |
6268 | break; |
6269 | handled += n; | |
6270 | addr += n; | |
6271 | len -= n; | |
6272 | v += n; | |
6273 | } while (len); | |
bbd9b64e | 6274 | |
70252a10 | 6275 | return handled; |
bbd9b64e CO |
6276 | } |
6277 | ||
bda9020e | 6278 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 6279 | { |
70252a10 AK |
6280 | int handled = 0; |
6281 | int n; | |
6282 | ||
6283 | do { | |
6284 | n = min(len, 8); | |
bce87cce | 6285 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
6286 | !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, |
6287 | addr, n, v)) | |
6288 | && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 | 6289 | break; |
e39d200f | 6290 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); |
70252a10 AK |
6291 | handled += n; |
6292 | addr += n; | |
6293 | len -= n; | |
6294 | v += n; | |
6295 | } while (len); | |
bbd9b64e | 6296 | |
70252a10 | 6297 | return handled; |
bbd9b64e CO |
6298 | } |
6299 | ||
2dafc6c2 GN |
6300 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
6301 | struct kvm_segment *var, int seg) | |
6302 | { | |
b3646477 | 6303 | static_call(kvm_x86_set_segment)(vcpu, var, seg); |
2dafc6c2 GN |
6304 | } |
6305 | ||
6306 | void kvm_get_segment(struct kvm_vcpu *vcpu, | |
6307 | struct kvm_segment *var, int seg) | |
6308 | { | |
b3646477 | 6309 | static_call(kvm_x86_get_segment)(vcpu, var, seg); |
2dafc6c2 GN |
6310 | } |
6311 | ||
54987b7a PB |
6312 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
6313 | struct x86_exception *exception) | |
02f59dc9 JR |
6314 | { |
6315 | gpa_t t_gpa; | |
02f59dc9 JR |
6316 | |
6317 | BUG_ON(!mmu_is_nested(vcpu)); | |
6318 | ||
6319 | /* NPT walks are always user-walks */ | |
6320 | access |= PFERR_USER_MASK; | |
44dd3ffa | 6321 | t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception); |
02f59dc9 JR |
6322 | |
6323 | return t_gpa; | |
6324 | } | |
6325 | ||
ab9ae313 AK |
6326 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
6327 | struct x86_exception *exception) | |
1871c602 | 6328 | { |
b3646477 | 6329 | u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
ab9ae313 | 6330 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 | 6331 | } |
54f958cd | 6332 | EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read); |
1871c602 | 6333 | |
ab9ae313 AK |
6334 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, |
6335 | struct x86_exception *exception) | |
1871c602 | 6336 | { |
b3646477 | 6337 | u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
1871c602 | 6338 | access |= PFERR_FETCH_MASK; |
ab9ae313 | 6339 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
6340 | } |
6341 | ||
ab9ae313 AK |
6342 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, |
6343 | struct x86_exception *exception) | |
1871c602 | 6344 | { |
b3646477 | 6345 | u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
1871c602 | 6346 | access |= PFERR_WRITE_MASK; |
ab9ae313 | 6347 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 | 6348 | } |
54f958cd | 6349 | EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write); |
1871c602 GN |
6350 | |
6351 | /* uses this to access any guest's mapped memory without checking CPL */ | |
ab9ae313 AK |
6352 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, |
6353 | struct x86_exception *exception) | |
1871c602 | 6354 | { |
ab9ae313 | 6355 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); |
1871c602 GN |
6356 | } |
6357 | ||
6358 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
6359 | struct kvm_vcpu *vcpu, u32 access, | |
bcc55cba | 6360 | struct x86_exception *exception) |
bbd9b64e CO |
6361 | { |
6362 | void *data = val; | |
10589a46 | 6363 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
6364 | |
6365 | while (bytes) { | |
14dfe855 | 6366 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, |
ab9ae313 | 6367 | exception); |
bbd9b64e | 6368 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 6369 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
6370 | int ret; |
6371 | ||
bcc55cba | 6372 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 6373 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa PB |
6374 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, |
6375 | offset, toread); | |
10589a46 | 6376 | if (ret < 0) { |
c3cd7ffa | 6377 | r = X86EMUL_IO_NEEDED; |
10589a46 MT |
6378 | goto out; |
6379 | } | |
bbd9b64e | 6380 | |
77c2002e IE |
6381 | bytes -= toread; |
6382 | data += toread; | |
6383 | addr += toread; | |
bbd9b64e | 6384 | } |
10589a46 | 6385 | out: |
10589a46 | 6386 | return r; |
bbd9b64e | 6387 | } |
77c2002e | 6388 | |
1871c602 | 6389 | /* used for instruction fetching */ |
0f65dd70 AK |
6390 | static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, |
6391 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 6392 | struct x86_exception *exception) |
1871c602 | 6393 | { |
0f65dd70 | 6394 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
b3646477 | 6395 | u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
44583cba PB |
6396 | unsigned offset; |
6397 | int ret; | |
0f65dd70 | 6398 | |
44583cba PB |
6399 | /* Inline kvm_read_guest_virt_helper for speed. */ |
6400 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, | |
6401 | exception); | |
6402 | if (unlikely(gpa == UNMAPPED_GVA)) | |
6403 | return X86EMUL_PROPAGATE_FAULT; | |
6404 | ||
6405 | offset = addr & (PAGE_SIZE-1); | |
6406 | if (WARN_ON(offset + bytes > PAGE_SIZE)) | |
6407 | bytes = (unsigned)PAGE_SIZE - offset; | |
54bf36aa PB |
6408 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, |
6409 | offset, bytes); | |
44583cba PB |
6410 | if (unlikely(ret < 0)) |
6411 | return X86EMUL_IO_NEEDED; | |
6412 | ||
6413 | return X86EMUL_CONTINUE; | |
1871c602 GN |
6414 | } |
6415 | ||
ce14e868 | 6416 | int kvm_read_guest_virt(struct kvm_vcpu *vcpu, |
0f65dd70 | 6417 | gva_t addr, void *val, unsigned int bytes, |
bcc55cba | 6418 | struct x86_exception *exception) |
1871c602 | 6419 | { |
b3646477 | 6420 | u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
0f65dd70 | 6421 | |
353c0956 PB |
6422 | /* |
6423 | * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED | |
6424 | * is returned, but our callers are not ready for that and they blindly | |
6425 | * call kvm_inject_page_fault. Ensure that they at least do not leak | |
6426 | * uninitialized kernel stack memory into cr2 and error code. | |
6427 | */ | |
6428 | memset(exception, 0, sizeof(*exception)); | |
1871c602 | 6429 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, |
bcc55cba | 6430 | exception); |
1871c602 | 6431 | } |
064aea77 | 6432 | EXPORT_SYMBOL_GPL(kvm_read_guest_virt); |
1871c602 | 6433 | |
ce14e868 PB |
6434 | static int emulator_read_std(struct x86_emulate_ctxt *ctxt, |
6435 | gva_t addr, void *val, unsigned int bytes, | |
3c9fa24c | 6436 | struct x86_exception *exception, bool system) |
1871c602 | 6437 | { |
0f65dd70 | 6438 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
3c9fa24c PB |
6439 | u32 access = 0; |
6440 | ||
b3646477 | 6441 | if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3) |
3c9fa24c PB |
6442 | access |= PFERR_USER_MASK; |
6443 | ||
6444 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); | |
1871c602 GN |
6445 | } |
6446 | ||
7a036a6f RK |
6447 | static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, |
6448 | unsigned long addr, void *val, unsigned int bytes) | |
6449 | { | |
6450 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
6451 | int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); | |
6452 | ||
6453 | return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; | |
6454 | } | |
6455 | ||
ce14e868 PB |
6456 | static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, |
6457 | struct kvm_vcpu *vcpu, u32 access, | |
6458 | struct x86_exception *exception) | |
77c2002e IE |
6459 | { |
6460 | void *data = val; | |
6461 | int r = X86EMUL_CONTINUE; | |
6462 | ||
6463 | while (bytes) { | |
14dfe855 | 6464 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, |
ce14e868 | 6465 | access, |
ab9ae313 | 6466 | exception); |
77c2002e IE |
6467 | unsigned offset = addr & (PAGE_SIZE-1); |
6468 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
6469 | int ret; | |
6470 | ||
bcc55cba | 6471 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 6472 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa | 6473 | ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); |
77c2002e | 6474 | if (ret < 0) { |
c3cd7ffa | 6475 | r = X86EMUL_IO_NEEDED; |
77c2002e IE |
6476 | goto out; |
6477 | } | |
6478 | ||
6479 | bytes -= towrite; | |
6480 | data += towrite; | |
6481 | addr += towrite; | |
6482 | } | |
6483 | out: | |
6484 | return r; | |
6485 | } | |
ce14e868 PB |
6486 | |
6487 | static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, | |
3c9fa24c PB |
6488 | unsigned int bytes, struct x86_exception *exception, |
6489 | bool system) | |
ce14e868 PB |
6490 | { |
6491 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
3c9fa24c PB |
6492 | u32 access = PFERR_WRITE_MASK; |
6493 | ||
b3646477 | 6494 | if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3) |
3c9fa24c | 6495 | access |= PFERR_USER_MASK; |
ce14e868 PB |
6496 | |
6497 | return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, | |
3c9fa24c | 6498 | access, exception); |
ce14e868 PB |
6499 | } |
6500 | ||
6501 | int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, | |
6502 | unsigned int bytes, struct x86_exception *exception) | |
6503 | { | |
c595ceee PB |
6504 | /* kvm_write_guest_virt_system can pull in tons of pages. */ |
6505 | vcpu->arch.l1tf_flush_l1d = true; | |
6506 | ||
ce14e868 PB |
6507 | return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, |
6508 | PFERR_WRITE_MASK, exception); | |
6509 | } | |
6a4d7550 | 6510 | EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); |
77c2002e | 6511 | |
082d06ed WL |
6512 | int handle_ud(struct kvm_vcpu *vcpu) |
6513 | { | |
b3dc0695 | 6514 | static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX }; |
6c86eedc | 6515 | int emul_type = EMULTYPE_TRAP_UD; |
6c86eedc WL |
6516 | char sig[5]; /* ud2; .ascii "kvm" */ |
6517 | struct x86_exception e; | |
6518 | ||
b3646477 | 6519 | if (unlikely(!static_call(kvm_x86_can_emulate_instruction)(vcpu, NULL, 0))) |
09e3e2a1 SC |
6520 | return 1; |
6521 | ||
6c86eedc | 6522 | if (force_emulation_prefix && |
3c9fa24c PB |
6523 | kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), |
6524 | sig, sizeof(sig), &e) == 0 && | |
b3dc0695 | 6525 | memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) { |
6c86eedc | 6526 | kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); |
b4000606 | 6527 | emul_type = EMULTYPE_TRAP_UD_FORCED; |
6c86eedc | 6528 | } |
082d06ed | 6529 | |
60fc3d02 | 6530 | return kvm_emulate_instruction(vcpu, emul_type); |
082d06ed WL |
6531 | } |
6532 | EXPORT_SYMBOL_GPL(handle_ud); | |
6533 | ||
0f89b207 TL |
6534 | static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
6535 | gpa_t gpa, bool write) | |
6536 | { | |
6537 | /* For APIC access vmexit */ | |
6538 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
6539 | return 1; | |
6540 | ||
6541 | if (vcpu_match_mmio_gpa(vcpu, gpa)) { | |
6542 | trace_vcpu_match_mmio(gva, gpa, write, true); | |
6543 | return 1; | |
6544 | } | |
6545 | ||
6546 | return 0; | |
6547 | } | |
6548 | ||
af7cc7d1 XG |
6549 | static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
6550 | gpa_t *gpa, struct x86_exception *exception, | |
6551 | bool write) | |
6552 | { | |
b3646477 | 6553 | u32 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0) |
97d64b78 | 6554 | | (write ? PFERR_WRITE_MASK : 0); |
af7cc7d1 | 6555 | |
be94f6b7 HH |
6556 | /* |
6557 | * currently PKRU is only applied to ept enabled guest so | |
6558 | * there is no pkey in EPT page table for L1 guest or EPT | |
6559 | * shadow page table for L2 guest. | |
6560 | */ | |
97d64b78 | 6561 | if (vcpu_match_mmio_gva(vcpu, gva) |
97ec8c06 | 6562 | && !permission_fault(vcpu, vcpu->arch.walk_mmu, |
871bd034 | 6563 | vcpu->arch.mmio_access, 0, access)) { |
bebb106a XG |
6564 | *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | |
6565 | (gva & (PAGE_SIZE - 1)); | |
4f022648 | 6566 | trace_vcpu_match_mmio(gva, *gpa, write, false); |
bebb106a XG |
6567 | return 1; |
6568 | } | |
6569 | ||
af7cc7d1 XG |
6570 | *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
6571 | ||
6572 | if (*gpa == UNMAPPED_GVA) | |
6573 | return -1; | |
6574 | ||
0f89b207 | 6575 | return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); |
af7cc7d1 XG |
6576 | } |
6577 | ||
3200f405 | 6578 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
bcc55cba | 6579 | const void *val, int bytes) |
bbd9b64e CO |
6580 | { |
6581 | int ret; | |
6582 | ||
54bf36aa | 6583 | ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); |
9f811285 | 6584 | if (ret < 0) |
bbd9b64e | 6585 | return 0; |
0eb05bf2 | 6586 | kvm_page_track_write(vcpu, gpa, val, bytes); |
bbd9b64e CO |
6587 | return 1; |
6588 | } | |
6589 | ||
77d197b2 XG |
6590 | struct read_write_emulator_ops { |
6591 | int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, | |
6592 | int bytes); | |
6593 | int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6594 | void *val, int bytes); | |
6595 | int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6596 | int bytes, void *val); | |
6597 | int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6598 | void *val, int bytes); | |
6599 | bool write; | |
6600 | }; | |
6601 | ||
6602 | static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) | |
6603 | { | |
6604 | if (vcpu->mmio_read_completed) { | |
77d197b2 | 6605 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
e39d200f | 6606 | vcpu->mmio_fragments[0].gpa, val); |
77d197b2 XG |
6607 | vcpu->mmio_read_completed = 0; |
6608 | return 1; | |
6609 | } | |
6610 | ||
6611 | return 0; | |
6612 | } | |
6613 | ||
6614 | static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6615 | void *val, int bytes) | |
6616 | { | |
54bf36aa | 6617 | return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); |
77d197b2 XG |
6618 | } |
6619 | ||
6620 | static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6621 | void *val, int bytes) | |
6622 | { | |
6623 | return emulator_write_phys(vcpu, gpa, val, bytes); | |
6624 | } | |
6625 | ||
6626 | static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) | |
6627 | { | |
e39d200f | 6628 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); |
77d197b2 XG |
6629 | return vcpu_mmio_write(vcpu, gpa, bytes, val); |
6630 | } | |
6631 | ||
6632 | static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6633 | void *val, int bytes) | |
6634 | { | |
e39d200f | 6635 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); |
77d197b2 XG |
6636 | return X86EMUL_IO_NEEDED; |
6637 | } | |
6638 | ||
6639 | static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6640 | void *val, int bytes) | |
6641 | { | |
f78146b0 AK |
6642 | struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; |
6643 | ||
87da7e66 | 6644 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); |
77d197b2 XG |
6645 | return X86EMUL_CONTINUE; |
6646 | } | |
6647 | ||
0fbe9b0b | 6648 | static const struct read_write_emulator_ops read_emultor = { |
77d197b2 XG |
6649 | .read_write_prepare = read_prepare, |
6650 | .read_write_emulate = read_emulate, | |
6651 | .read_write_mmio = vcpu_mmio_read, | |
6652 | .read_write_exit_mmio = read_exit_mmio, | |
6653 | }; | |
6654 | ||
0fbe9b0b | 6655 | static const struct read_write_emulator_ops write_emultor = { |
77d197b2 XG |
6656 | .read_write_emulate = write_emulate, |
6657 | .read_write_mmio = write_mmio, | |
6658 | .read_write_exit_mmio = write_exit_mmio, | |
6659 | .write = true, | |
6660 | }; | |
6661 | ||
22388a3c XG |
6662 | static int emulator_read_write_onepage(unsigned long addr, void *val, |
6663 | unsigned int bytes, | |
6664 | struct x86_exception *exception, | |
6665 | struct kvm_vcpu *vcpu, | |
0fbe9b0b | 6666 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 6667 | { |
af7cc7d1 XG |
6668 | gpa_t gpa; |
6669 | int handled, ret; | |
22388a3c | 6670 | bool write = ops->write; |
f78146b0 | 6671 | struct kvm_mmio_fragment *frag; |
c9b8b07c | 6672 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
0f89b207 TL |
6673 | |
6674 | /* | |
6675 | * If the exit was due to a NPF we may already have a GPA. | |
6676 | * If the GPA is present, use it to avoid the GVA to GPA table walk. | |
6677 | * Note, this cannot be used on string operations since string | |
6678 | * operation using rep will only have the initial GPA from the NPF | |
6679 | * occurred. | |
6680 | */ | |
744e699c SC |
6681 | if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) && |
6682 | (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) { | |
6683 | gpa = ctxt->gpa_val; | |
618232e2 BS |
6684 | ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); |
6685 | } else { | |
6686 | ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); | |
6687 | if (ret < 0) | |
6688 | return X86EMUL_PROPAGATE_FAULT; | |
0f89b207 | 6689 | } |
10589a46 | 6690 | |
618232e2 | 6691 | if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) |
bbd9b64e CO |
6692 | return X86EMUL_CONTINUE; |
6693 | ||
bbd9b64e CO |
6694 | /* |
6695 | * Is this MMIO handled locally? | |
6696 | */ | |
22388a3c | 6697 | handled = ops->read_write_mmio(vcpu, gpa, bytes, val); |
70252a10 | 6698 | if (handled == bytes) |
bbd9b64e | 6699 | return X86EMUL_CONTINUE; |
bbd9b64e | 6700 | |
70252a10 AK |
6701 | gpa += handled; |
6702 | bytes -= handled; | |
6703 | val += handled; | |
6704 | ||
87da7e66 XG |
6705 | WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); |
6706 | frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; | |
6707 | frag->gpa = gpa; | |
6708 | frag->data = val; | |
6709 | frag->len = bytes; | |
f78146b0 | 6710 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
6711 | } |
6712 | ||
52eb5a6d XL |
6713 | static int emulator_read_write(struct x86_emulate_ctxt *ctxt, |
6714 | unsigned long addr, | |
22388a3c XG |
6715 | void *val, unsigned int bytes, |
6716 | struct x86_exception *exception, | |
0fbe9b0b | 6717 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 6718 | { |
0f65dd70 | 6719 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
f78146b0 AK |
6720 | gpa_t gpa; |
6721 | int rc; | |
6722 | ||
6723 | if (ops->read_write_prepare && | |
6724 | ops->read_write_prepare(vcpu, val, bytes)) | |
6725 | return X86EMUL_CONTINUE; | |
6726 | ||
6727 | vcpu->mmio_nr_fragments = 0; | |
0f65dd70 | 6728 | |
bbd9b64e CO |
6729 | /* Crossing a page boundary? */ |
6730 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
f78146b0 | 6731 | int now; |
bbd9b64e CO |
6732 | |
6733 | now = -addr & ~PAGE_MASK; | |
22388a3c XG |
6734 | rc = emulator_read_write_onepage(addr, val, now, exception, |
6735 | vcpu, ops); | |
6736 | ||
bbd9b64e CO |
6737 | if (rc != X86EMUL_CONTINUE) |
6738 | return rc; | |
6739 | addr += now; | |
bac15531 NA |
6740 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
6741 | addr = (u32)addr; | |
bbd9b64e CO |
6742 | val += now; |
6743 | bytes -= now; | |
6744 | } | |
22388a3c | 6745 | |
f78146b0 AK |
6746 | rc = emulator_read_write_onepage(addr, val, bytes, exception, |
6747 | vcpu, ops); | |
6748 | if (rc != X86EMUL_CONTINUE) | |
6749 | return rc; | |
6750 | ||
6751 | if (!vcpu->mmio_nr_fragments) | |
6752 | return rc; | |
6753 | ||
6754 | gpa = vcpu->mmio_fragments[0].gpa; | |
6755 | ||
6756 | vcpu->mmio_needed = 1; | |
6757 | vcpu->mmio_cur_fragment = 0; | |
6758 | ||
87da7e66 | 6759 | vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); |
f78146b0 AK |
6760 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; |
6761 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
6762 | vcpu->run->mmio.phys_addr = gpa; | |
6763 | ||
6764 | return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); | |
22388a3c XG |
6765 | } |
6766 | ||
6767 | static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, | |
6768 | unsigned long addr, | |
6769 | void *val, | |
6770 | unsigned int bytes, | |
6771 | struct x86_exception *exception) | |
6772 | { | |
6773 | return emulator_read_write(ctxt, addr, val, bytes, | |
6774 | exception, &read_emultor); | |
6775 | } | |
6776 | ||
52eb5a6d | 6777 | static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, |
22388a3c XG |
6778 | unsigned long addr, |
6779 | const void *val, | |
6780 | unsigned int bytes, | |
6781 | struct x86_exception *exception) | |
6782 | { | |
6783 | return emulator_read_write(ctxt, addr, (void *)val, bytes, | |
6784 | exception, &write_emultor); | |
bbd9b64e | 6785 | } |
bbd9b64e | 6786 | |
daea3e73 AK |
6787 | #define CMPXCHG_TYPE(t, ptr, old, new) \ |
6788 | (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) | |
6789 | ||
6790 | #ifdef CONFIG_X86_64 | |
6791 | # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) | |
6792 | #else | |
6793 | # define CMPXCHG64(ptr, old, new) \ | |
9749a6c0 | 6794 | (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) |
daea3e73 AK |
6795 | #endif |
6796 | ||
0f65dd70 AK |
6797 | static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, |
6798 | unsigned long addr, | |
bbd9b64e CO |
6799 | const void *old, |
6800 | const void *new, | |
6801 | unsigned int bytes, | |
0f65dd70 | 6802 | struct x86_exception *exception) |
bbd9b64e | 6803 | { |
42e35f80 | 6804 | struct kvm_host_map map; |
0f65dd70 | 6805 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
9de6fe3c | 6806 | u64 page_line_mask; |
daea3e73 | 6807 | gpa_t gpa; |
daea3e73 AK |
6808 | char *kaddr; |
6809 | bool exchanged; | |
2bacc55c | 6810 | |
daea3e73 AK |
6811 | /* guests cmpxchg8b have to be emulated atomically */ |
6812 | if (bytes > 8 || (bytes & (bytes - 1))) | |
6813 | goto emul_write; | |
10589a46 | 6814 | |
daea3e73 | 6815 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); |
2bacc55c | 6816 | |
daea3e73 AK |
6817 | if (gpa == UNMAPPED_GVA || |
6818 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
6819 | goto emul_write; | |
2bacc55c | 6820 | |
9de6fe3c XL |
6821 | /* |
6822 | * Emulate the atomic as a straight write to avoid #AC if SLD is | |
6823 | * enabled in the host and the access splits a cache line. | |
6824 | */ | |
6825 | if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) | |
6826 | page_line_mask = ~(cache_line_size() - 1); | |
6827 | else | |
6828 | page_line_mask = PAGE_MASK; | |
6829 | ||
6830 | if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask)) | |
daea3e73 | 6831 | goto emul_write; |
72dc67a6 | 6832 | |
42e35f80 | 6833 | if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map)) |
c19b8bd6 | 6834 | goto emul_write; |
72dc67a6 | 6835 | |
42e35f80 KA |
6836 | kaddr = map.hva + offset_in_page(gpa); |
6837 | ||
daea3e73 AK |
6838 | switch (bytes) { |
6839 | case 1: | |
6840 | exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); | |
6841 | break; | |
6842 | case 2: | |
6843 | exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); | |
6844 | break; | |
6845 | case 4: | |
6846 | exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); | |
6847 | break; | |
6848 | case 8: | |
6849 | exchanged = CMPXCHG64(kaddr, old, new); | |
6850 | break; | |
6851 | default: | |
6852 | BUG(); | |
2bacc55c | 6853 | } |
42e35f80 KA |
6854 | |
6855 | kvm_vcpu_unmap(vcpu, &map, true); | |
daea3e73 AK |
6856 | |
6857 | if (!exchanged) | |
6858 | return X86EMUL_CMPXCHG_FAILED; | |
6859 | ||
0eb05bf2 | 6860 | kvm_page_track_write(vcpu, gpa, new, bytes); |
8f6abd06 GN |
6861 | |
6862 | return X86EMUL_CONTINUE; | |
4a5f48f6 | 6863 | |
3200f405 | 6864 | emul_write: |
daea3e73 | 6865 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); |
2bacc55c | 6866 | |
0f65dd70 | 6867 | return emulator_write_emulated(ctxt, addr, new, bytes, exception); |
bbd9b64e CO |
6868 | } |
6869 | ||
cf8f70bf GN |
6870 | static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) |
6871 | { | |
cbfc6c91 | 6872 | int r = 0, i; |
cf8f70bf | 6873 | |
cbfc6c91 WL |
6874 | for (i = 0; i < vcpu->arch.pio.count; i++) { |
6875 | if (vcpu->arch.pio.in) | |
6876 | r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, | |
6877 | vcpu->arch.pio.size, pd); | |
6878 | else | |
6879 | r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, | |
6880 | vcpu->arch.pio.port, vcpu->arch.pio.size, | |
6881 | pd); | |
6882 | if (r) | |
6883 | break; | |
6884 | pd += vcpu->arch.pio.size; | |
6885 | } | |
cf8f70bf GN |
6886 | return r; |
6887 | } | |
6888 | ||
6f6fbe98 XG |
6889 | static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, |
6890 | unsigned short port, void *val, | |
6891 | unsigned int count, bool in) | |
cf8f70bf | 6892 | { |
cf8f70bf | 6893 | vcpu->arch.pio.port = port; |
6f6fbe98 | 6894 | vcpu->arch.pio.in = in; |
7972995b | 6895 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
6896 | vcpu->arch.pio.size = size; |
6897 | ||
6898 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
7972995b | 6899 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
6900 | return 1; |
6901 | } | |
6902 | ||
6903 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
6f6fbe98 | 6904 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; |
cf8f70bf GN |
6905 | vcpu->run->io.size = size; |
6906 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
6907 | vcpu->run->io.count = count; | |
6908 | vcpu->run->io.port = port; | |
6909 | ||
6910 | return 0; | |
6911 | } | |
6912 | ||
2e3bb4d8 SC |
6913 | static int emulator_pio_in(struct kvm_vcpu *vcpu, int size, |
6914 | unsigned short port, void *val, unsigned int count) | |
cf8f70bf | 6915 | { |
6f6fbe98 | 6916 | int ret; |
ca1d4a9e | 6917 | |
6f6fbe98 XG |
6918 | if (vcpu->arch.pio.count) |
6919 | goto data_avail; | |
cf8f70bf | 6920 | |
cbfc6c91 WL |
6921 | memset(vcpu->arch.pio_data, 0, size * count); |
6922 | ||
6f6fbe98 XG |
6923 | ret = emulator_pio_in_out(vcpu, size, port, val, count, true); |
6924 | if (ret) { | |
6925 | data_avail: | |
6926 | memcpy(val, vcpu->arch.pio_data, size * count); | |
1171903d | 6927 | trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); |
7972995b | 6928 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
6929 | return 1; |
6930 | } | |
6931 | ||
cf8f70bf GN |
6932 | return 0; |
6933 | } | |
6934 | ||
2e3bb4d8 SC |
6935 | static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
6936 | int size, unsigned short port, void *val, | |
6937 | unsigned int count) | |
6f6fbe98 | 6938 | { |
2e3bb4d8 | 6939 | return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count); |
6f6fbe98 | 6940 | |
2e3bb4d8 | 6941 | } |
6f6fbe98 | 6942 | |
2e3bb4d8 SC |
6943 | static int emulator_pio_out(struct kvm_vcpu *vcpu, int size, |
6944 | unsigned short port, const void *val, | |
6945 | unsigned int count) | |
6946 | { | |
6f6fbe98 | 6947 | memcpy(vcpu->arch.pio_data, val, size * count); |
1171903d | 6948 | trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); |
6f6fbe98 XG |
6949 | return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); |
6950 | } | |
6951 | ||
2e3bb4d8 SC |
6952 | static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, |
6953 | int size, unsigned short port, | |
6954 | const void *val, unsigned int count) | |
6955 | { | |
6956 | return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count); | |
6957 | } | |
6958 | ||
bbd9b64e CO |
6959 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) |
6960 | { | |
b3646477 | 6961 | return static_call(kvm_x86_get_segment_base)(vcpu, seg); |
bbd9b64e CO |
6962 | } |
6963 | ||
3cb16fe7 | 6964 | static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) |
bbd9b64e | 6965 | { |
3cb16fe7 | 6966 | kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); |
bbd9b64e CO |
6967 | } |
6968 | ||
ae6a2375 | 6969 | static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) |
f5f48ee1 SY |
6970 | { |
6971 | if (!need_emulate_wbinvd(vcpu)) | |
6972 | return X86EMUL_CONTINUE; | |
6973 | ||
b3646477 | 6974 | if (static_call(kvm_x86_has_wbinvd_exit)()) { |
2eec7343 JK |
6975 | int cpu = get_cpu(); |
6976 | ||
6977 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
c2162e13 | 6978 | on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask, |
f5f48ee1 | 6979 | wbinvd_ipi, NULL, 1); |
2eec7343 | 6980 | put_cpu(); |
f5f48ee1 | 6981 | cpumask_clear(vcpu->arch.wbinvd_dirty_mask); |
2eec7343 JK |
6982 | } else |
6983 | wbinvd(); | |
f5f48ee1 SY |
6984 | return X86EMUL_CONTINUE; |
6985 | } | |
5cb56059 JS |
6986 | |
6987 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
6988 | { | |
6affcbed KH |
6989 | kvm_emulate_wbinvd_noskip(vcpu); |
6990 | return kvm_skip_emulated_instruction(vcpu); | |
5cb56059 | 6991 | } |
f5f48ee1 SY |
6992 | EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); |
6993 | ||
5cb56059 JS |
6994 | |
6995 | ||
bcaf5cc5 AK |
6996 | static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) |
6997 | { | |
5cb56059 | 6998 | kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); |
bcaf5cc5 AK |
6999 | } |
7000 | ||
29d6ca41 PB |
7001 | static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, |
7002 | unsigned long *dest) | |
bbd9b64e | 7003 | { |
29d6ca41 | 7004 | kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); |
bbd9b64e CO |
7005 | } |
7006 | ||
52eb5a6d XL |
7007 | static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, |
7008 | unsigned long value) | |
bbd9b64e | 7009 | { |
338dbc97 | 7010 | |
996ff542 | 7011 | return kvm_set_dr(emul_to_vcpu(ctxt), dr, value); |
bbd9b64e CO |
7012 | } |
7013 | ||
52a46617 | 7014 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) |
5fdbf976 | 7015 | { |
52a46617 | 7016 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; |
5fdbf976 MT |
7017 | } |
7018 | ||
717746e3 | 7019 | static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) |
bbd9b64e | 7020 | { |
717746e3 | 7021 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
52a46617 GN |
7022 | unsigned long value; |
7023 | ||
7024 | switch (cr) { | |
7025 | case 0: | |
7026 | value = kvm_read_cr0(vcpu); | |
7027 | break; | |
7028 | case 2: | |
7029 | value = vcpu->arch.cr2; | |
7030 | break; | |
7031 | case 3: | |
9f8fe504 | 7032 | value = kvm_read_cr3(vcpu); |
52a46617 GN |
7033 | break; |
7034 | case 4: | |
7035 | value = kvm_read_cr4(vcpu); | |
7036 | break; | |
7037 | case 8: | |
7038 | value = kvm_get_cr8(vcpu); | |
7039 | break; | |
7040 | default: | |
a737f256 | 7041 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
52a46617 GN |
7042 | return 0; |
7043 | } | |
7044 | ||
7045 | return value; | |
7046 | } | |
7047 | ||
717746e3 | 7048 | static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) |
52a46617 | 7049 | { |
717746e3 | 7050 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
0f12244f GN |
7051 | int res = 0; |
7052 | ||
52a46617 GN |
7053 | switch (cr) { |
7054 | case 0: | |
49a9b07e | 7055 | res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
52a46617 GN |
7056 | break; |
7057 | case 2: | |
7058 | vcpu->arch.cr2 = val; | |
7059 | break; | |
7060 | case 3: | |
2390218b | 7061 | res = kvm_set_cr3(vcpu, val); |
52a46617 GN |
7062 | break; |
7063 | case 4: | |
a83b29c6 | 7064 | res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
52a46617 GN |
7065 | break; |
7066 | case 8: | |
eea1cff9 | 7067 | res = kvm_set_cr8(vcpu, val); |
52a46617 GN |
7068 | break; |
7069 | default: | |
a737f256 | 7070 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
0f12244f | 7071 | res = -1; |
52a46617 | 7072 | } |
0f12244f GN |
7073 | |
7074 | return res; | |
52a46617 GN |
7075 | } |
7076 | ||
717746e3 | 7077 | static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) |
9c537244 | 7078 | { |
b3646477 | 7079 | return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt)); |
9c537244 GN |
7080 | } |
7081 | ||
4bff1e86 | 7082 | static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
2dafc6c2 | 7083 | { |
b3646477 | 7084 | static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt); |
2dafc6c2 GN |
7085 | } |
7086 | ||
4bff1e86 | 7087 | static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
160ce1f1 | 7088 | { |
b3646477 | 7089 | static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt); |
160ce1f1 MG |
7090 | } |
7091 | ||
1ac9d0cf AK |
7092 | static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
7093 | { | |
b3646477 | 7094 | static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt); |
1ac9d0cf AK |
7095 | } |
7096 | ||
7097 | static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) | |
7098 | { | |
b3646477 | 7099 | static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt); |
1ac9d0cf AK |
7100 | } |
7101 | ||
4bff1e86 AK |
7102 | static unsigned long emulator_get_cached_segment_base( |
7103 | struct x86_emulate_ctxt *ctxt, int seg) | |
5951c442 | 7104 | { |
4bff1e86 | 7105 | return get_segment_base(emul_to_vcpu(ctxt), seg); |
5951c442 GN |
7106 | } |
7107 | ||
1aa36616 AK |
7108 | static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, |
7109 | struct desc_struct *desc, u32 *base3, | |
7110 | int seg) | |
2dafc6c2 GN |
7111 | { |
7112 | struct kvm_segment var; | |
7113 | ||
4bff1e86 | 7114 | kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); |
1aa36616 | 7115 | *selector = var.selector; |
2dafc6c2 | 7116 | |
378a8b09 GN |
7117 | if (var.unusable) { |
7118 | memset(desc, 0, sizeof(*desc)); | |
f0367ee1 RK |
7119 | if (base3) |
7120 | *base3 = 0; | |
2dafc6c2 | 7121 | return false; |
378a8b09 | 7122 | } |
2dafc6c2 GN |
7123 | |
7124 | if (var.g) | |
7125 | var.limit >>= 12; | |
7126 | set_desc_limit(desc, var.limit); | |
7127 | set_desc_base(desc, (unsigned long)var.base); | |
5601d05b GN |
7128 | #ifdef CONFIG_X86_64 |
7129 | if (base3) | |
7130 | *base3 = var.base >> 32; | |
7131 | #endif | |
2dafc6c2 GN |
7132 | desc->type = var.type; |
7133 | desc->s = var.s; | |
7134 | desc->dpl = var.dpl; | |
7135 | desc->p = var.present; | |
7136 | desc->avl = var.avl; | |
7137 | desc->l = var.l; | |
7138 | desc->d = var.db; | |
7139 | desc->g = var.g; | |
7140 | ||
7141 | return true; | |
7142 | } | |
7143 | ||
1aa36616 AK |
7144 | static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, |
7145 | struct desc_struct *desc, u32 base3, | |
7146 | int seg) | |
2dafc6c2 | 7147 | { |
4bff1e86 | 7148 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
2dafc6c2 GN |
7149 | struct kvm_segment var; |
7150 | ||
1aa36616 | 7151 | var.selector = selector; |
2dafc6c2 | 7152 | var.base = get_desc_base(desc); |
5601d05b GN |
7153 | #ifdef CONFIG_X86_64 |
7154 | var.base |= ((u64)base3) << 32; | |
7155 | #endif | |
2dafc6c2 GN |
7156 | var.limit = get_desc_limit(desc); |
7157 | if (desc->g) | |
7158 | var.limit = (var.limit << 12) | 0xfff; | |
7159 | var.type = desc->type; | |
2dafc6c2 GN |
7160 | var.dpl = desc->dpl; |
7161 | var.db = desc->d; | |
7162 | var.s = desc->s; | |
7163 | var.l = desc->l; | |
7164 | var.g = desc->g; | |
7165 | var.avl = desc->avl; | |
7166 | var.present = desc->p; | |
7167 | var.unusable = !var.present; | |
7168 | var.padding = 0; | |
7169 | ||
7170 | kvm_set_segment(vcpu, &var, seg); | |
7171 | return; | |
7172 | } | |
7173 | ||
717746e3 AK |
7174 | static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, |
7175 | u32 msr_index, u64 *pdata) | |
7176 | { | |
1ae09954 AG |
7177 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
7178 | int r; | |
7179 | ||
7180 | r = kvm_get_msr(vcpu, msr_index, pdata); | |
7181 | ||
7182 | if (r && kvm_get_msr_user_space(vcpu, msr_index, r)) { | |
7183 | /* Bounce to user space */ | |
7184 | return X86EMUL_IO_NEEDED; | |
7185 | } | |
7186 | ||
7187 | return r; | |
717746e3 AK |
7188 | } |
7189 | ||
7190 | static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, | |
7191 | u32 msr_index, u64 data) | |
7192 | { | |
1ae09954 AG |
7193 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
7194 | int r; | |
7195 | ||
7196 | r = kvm_set_msr(vcpu, msr_index, data); | |
7197 | ||
7198 | if (r && kvm_set_msr_user_space(vcpu, msr_index, data, r)) { | |
7199 | /* Bounce to user space */ | |
7200 | return X86EMUL_IO_NEEDED; | |
7201 | } | |
7202 | ||
7203 | return r; | |
717746e3 AK |
7204 | } |
7205 | ||
64d60670 PB |
7206 | static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) |
7207 | { | |
7208 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
7209 | ||
7210 | return vcpu->arch.smbase; | |
7211 | } | |
7212 | ||
7213 | static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) | |
7214 | { | |
7215 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
7216 | ||
7217 | vcpu->arch.smbase = smbase; | |
7218 | } | |
7219 | ||
67f4d428 NA |
7220 | static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, |
7221 | u32 pmc) | |
7222 | { | |
98ff80f5 | 7223 | return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc); |
67f4d428 NA |
7224 | } |
7225 | ||
222d21aa AK |
7226 | static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, |
7227 | u32 pmc, u64 *pdata) | |
7228 | { | |
c6702c9d | 7229 | return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); |
222d21aa AK |
7230 | } |
7231 | ||
6c3287f7 AK |
7232 | static void emulator_halt(struct x86_emulate_ctxt *ctxt) |
7233 | { | |
7234 | emul_to_vcpu(ctxt)->arch.halt_request = 1; | |
7235 | } | |
7236 | ||
2953538e | 7237 | static int emulator_intercept(struct x86_emulate_ctxt *ctxt, |
8a76d7f2 | 7238 | struct x86_instruction_info *info, |
c4f035c6 AK |
7239 | enum x86_intercept_stage stage) |
7240 | { | |
b3646477 | 7241 | return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage, |
21f1b8f2 | 7242 | &ctxt->exception); |
c4f035c6 AK |
7243 | } |
7244 | ||
e911eb3b | 7245 | static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, |
f91af517 SC |
7246 | u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, |
7247 | bool exact_only) | |
bdb42f5a | 7248 | { |
f91af517 | 7249 | return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only); |
bdb42f5a SB |
7250 | } |
7251 | ||
5ae78e95 SC |
7252 | static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt) |
7253 | { | |
7254 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM); | |
7255 | } | |
7256 | ||
7257 | static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt) | |
7258 | { | |
7259 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE); | |
7260 | } | |
7261 | ||
7262 | static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt) | |
7263 | { | |
7264 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR); | |
7265 | } | |
7266 | ||
dd856efa AK |
7267 | static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) |
7268 | { | |
27b4a9c4 | 7269 | return kvm_register_read_raw(emul_to_vcpu(ctxt), reg); |
dd856efa AK |
7270 | } |
7271 | ||
7272 | static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) | |
7273 | { | |
27b4a9c4 | 7274 | kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val); |
dd856efa AK |
7275 | } |
7276 | ||
801806d9 NA |
7277 | static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) |
7278 | { | |
b3646477 | 7279 | static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked); |
801806d9 NA |
7280 | } |
7281 | ||
6ed071f0 LP |
7282 | static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) |
7283 | { | |
7284 | return emul_to_vcpu(ctxt)->arch.hflags; | |
7285 | } | |
7286 | ||
edce4654 | 7287 | static void emulator_exiting_smm(struct x86_emulate_ctxt *ctxt) |
6ed071f0 | 7288 | { |
78fcb2c9 SC |
7289 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
7290 | ||
dc87275f | 7291 | kvm_smm_changed(vcpu, false); |
6ed071f0 LP |
7292 | } |
7293 | ||
ecc513e5 | 7294 | static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt, |
ed19321f | 7295 | const char *smstate) |
0234bf88 | 7296 | { |
ecc513e5 | 7297 | return static_call(kvm_x86_leave_smm)(emul_to_vcpu(ctxt), smstate); |
0234bf88 LP |
7298 | } |
7299 | ||
25b17226 SC |
7300 | static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt) |
7301 | { | |
7302 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt)); | |
7303 | } | |
7304 | ||
02d4160f VK |
7305 | static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) |
7306 | { | |
7307 | return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); | |
7308 | } | |
7309 | ||
0225fb50 | 7310 | static const struct x86_emulate_ops emulate_ops = { |
dd856efa AK |
7311 | .read_gpr = emulator_read_gpr, |
7312 | .write_gpr = emulator_write_gpr, | |
ce14e868 PB |
7313 | .read_std = emulator_read_std, |
7314 | .write_std = emulator_write_std, | |
7a036a6f | 7315 | .read_phys = kvm_read_guest_phys_system, |
1871c602 | 7316 | .fetch = kvm_fetch_guest_virt, |
bbd9b64e CO |
7317 | .read_emulated = emulator_read_emulated, |
7318 | .write_emulated = emulator_write_emulated, | |
7319 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
3cb16fe7 | 7320 | .invlpg = emulator_invlpg, |
cf8f70bf GN |
7321 | .pio_in_emulated = emulator_pio_in_emulated, |
7322 | .pio_out_emulated = emulator_pio_out_emulated, | |
1aa36616 AK |
7323 | .get_segment = emulator_get_segment, |
7324 | .set_segment = emulator_set_segment, | |
5951c442 | 7325 | .get_cached_segment_base = emulator_get_cached_segment_base, |
2dafc6c2 | 7326 | .get_gdt = emulator_get_gdt, |
160ce1f1 | 7327 | .get_idt = emulator_get_idt, |
1ac9d0cf AK |
7328 | .set_gdt = emulator_set_gdt, |
7329 | .set_idt = emulator_set_idt, | |
52a46617 GN |
7330 | .get_cr = emulator_get_cr, |
7331 | .set_cr = emulator_set_cr, | |
9c537244 | 7332 | .cpl = emulator_get_cpl, |
35aa5375 GN |
7333 | .get_dr = emulator_get_dr, |
7334 | .set_dr = emulator_set_dr, | |
64d60670 PB |
7335 | .get_smbase = emulator_get_smbase, |
7336 | .set_smbase = emulator_set_smbase, | |
717746e3 AK |
7337 | .set_msr = emulator_set_msr, |
7338 | .get_msr = emulator_get_msr, | |
67f4d428 | 7339 | .check_pmc = emulator_check_pmc, |
222d21aa | 7340 | .read_pmc = emulator_read_pmc, |
6c3287f7 | 7341 | .halt = emulator_halt, |
bcaf5cc5 | 7342 | .wbinvd = emulator_wbinvd, |
d6aa1000 | 7343 | .fix_hypercall = emulator_fix_hypercall, |
c4f035c6 | 7344 | .intercept = emulator_intercept, |
bdb42f5a | 7345 | .get_cpuid = emulator_get_cpuid, |
5ae78e95 SC |
7346 | .guest_has_long_mode = emulator_guest_has_long_mode, |
7347 | .guest_has_movbe = emulator_guest_has_movbe, | |
7348 | .guest_has_fxsr = emulator_guest_has_fxsr, | |
801806d9 | 7349 | .set_nmi_mask = emulator_set_nmi_mask, |
6ed071f0 | 7350 | .get_hflags = emulator_get_hflags, |
edce4654 | 7351 | .exiting_smm = emulator_exiting_smm, |
ecc513e5 | 7352 | .leave_smm = emulator_leave_smm, |
25b17226 | 7353 | .triple_fault = emulator_triple_fault, |
02d4160f | 7354 | .set_xcr = emulator_set_xcr, |
bbd9b64e CO |
7355 | }; |
7356 | ||
95cb2295 GN |
7357 | static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) |
7358 | { | |
b3646477 | 7359 | u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); |
95cb2295 GN |
7360 | /* |
7361 | * an sti; sti; sequence only disable interrupts for the first | |
7362 | * instruction. So, if the last instruction, be it emulated or | |
7363 | * not, left the system with the INT_STI flag enabled, it | |
7364 | * means that the last instruction is an sti. We should not | |
7365 | * leave the flag on in this case. The same goes for mov ss | |
7366 | */ | |
37ccdcbe PB |
7367 | if (int_shadow & mask) |
7368 | mask = 0; | |
6addfc42 | 7369 | if (unlikely(int_shadow || mask)) { |
b3646477 | 7370 | static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask); |
6addfc42 PB |
7371 | if (!mask) |
7372 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7373 | } | |
95cb2295 GN |
7374 | } |
7375 | ||
ef54bcfe | 7376 | static bool inject_emulated_exception(struct kvm_vcpu *vcpu) |
54b8486f | 7377 | { |
c9b8b07c | 7378 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
da9cb575 | 7379 | if (ctxt->exception.vector == PF_VECTOR) |
53b3d8e9 | 7380 | return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception); |
ef54bcfe PB |
7381 | |
7382 | if (ctxt->exception.error_code_valid) | |
da9cb575 AK |
7383 | kvm_queue_exception_e(vcpu, ctxt->exception.vector, |
7384 | ctxt->exception.error_code); | |
54b8486f | 7385 | else |
da9cb575 | 7386 | kvm_queue_exception(vcpu, ctxt->exception.vector); |
ef54bcfe | 7387 | return false; |
54b8486f GN |
7388 | } |
7389 | ||
c9b8b07c SC |
7390 | static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu) |
7391 | { | |
7392 | struct x86_emulate_ctxt *ctxt; | |
7393 | ||
7394 | ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT); | |
7395 | if (!ctxt) { | |
7396 | pr_err("kvm: failed to allocate vcpu's emulator\n"); | |
7397 | return NULL; | |
7398 | } | |
7399 | ||
7400 | ctxt->vcpu = vcpu; | |
7401 | ctxt->ops = &emulate_ops; | |
7402 | vcpu->arch.emulate_ctxt = ctxt; | |
7403 | ||
7404 | return ctxt; | |
7405 | } | |
7406 | ||
8ec4722d MG |
7407 | static void init_emulate_ctxt(struct kvm_vcpu *vcpu) |
7408 | { | |
c9b8b07c | 7409 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
8ec4722d MG |
7410 | int cs_db, cs_l; |
7411 | ||
b3646477 | 7412 | static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); |
8ec4722d | 7413 | |
744e699c | 7414 | ctxt->gpa_available = false; |
adf52235 | 7415 | ctxt->eflags = kvm_get_rflags(vcpu); |
c8401dda PB |
7416 | ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; |
7417 | ||
adf52235 TY |
7418 | ctxt->eip = kvm_rip_read(vcpu); |
7419 | ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : | |
7420 | (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : | |
42bf549f | 7421 | (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : |
adf52235 TY |
7422 | cs_db ? X86EMUL_MODE_PROT32 : |
7423 | X86EMUL_MODE_PROT16; | |
a584539b | 7424 | BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); |
64d60670 PB |
7425 | BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); |
7426 | BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); | |
adf52235 | 7427 | |
da6393cd WL |
7428 | ctxt->interruptibility = 0; |
7429 | ctxt->have_exception = false; | |
7430 | ctxt->exception.vector = -1; | |
7431 | ctxt->perm_ok = false; | |
7432 | ||
dd856efa | 7433 | init_decode_cache(ctxt); |
7ae441ea | 7434 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; |
8ec4722d MG |
7435 | } |
7436 | ||
9497e1f2 | 7437 | void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) |
63995653 | 7438 | { |
c9b8b07c | 7439 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
63995653 MG |
7440 | int ret; |
7441 | ||
7442 | init_emulate_ctxt(vcpu); | |
7443 | ||
9dac77fa AK |
7444 | ctxt->op_bytes = 2; |
7445 | ctxt->ad_bytes = 2; | |
7446 | ctxt->_eip = ctxt->eip + inc_eip; | |
9d74191a | 7447 | ret = emulate_int_real(ctxt, irq); |
63995653 | 7448 | |
9497e1f2 SC |
7449 | if (ret != X86EMUL_CONTINUE) { |
7450 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
7451 | } else { | |
7452 | ctxt->eip = ctxt->_eip; | |
7453 | kvm_rip_write(vcpu, ctxt->eip); | |
7454 | kvm_set_rflags(vcpu, ctxt->eflags); | |
7455 | } | |
63995653 MG |
7456 | } |
7457 | EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); | |
7458 | ||
19238e75 AL |
7459 | static void prepare_emulation_failure_exit(struct kvm_vcpu *vcpu) |
7460 | { | |
7461 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; | |
7462 | u32 insn_size = ctxt->fetch.end - ctxt->fetch.data; | |
7463 | struct kvm_run *run = vcpu->run; | |
7464 | ||
7465 | run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
7466 | run->emulation_failure.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
7467 | run->emulation_failure.ndata = 0; | |
7468 | run->emulation_failure.flags = 0; | |
7469 | ||
7470 | if (insn_size) { | |
7471 | run->emulation_failure.ndata = 3; | |
7472 | run->emulation_failure.flags |= | |
7473 | KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES; | |
7474 | run->emulation_failure.insn_size = insn_size; | |
7475 | memset(run->emulation_failure.insn_bytes, 0x90, | |
7476 | sizeof(run->emulation_failure.insn_bytes)); | |
7477 | memcpy(run->emulation_failure.insn_bytes, | |
7478 | ctxt->fetch.data, insn_size); | |
7479 | } | |
7480 | } | |
7481 | ||
e2366171 | 7482 | static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) |
6d77dbfc | 7483 | { |
19238e75 AL |
7484 | struct kvm *kvm = vcpu->kvm; |
7485 | ||
6d77dbfc GN |
7486 | ++vcpu->stat.insn_emulation_fail; |
7487 | trace_kvm_emulate_insn_failed(vcpu); | |
e2366171 | 7488 | |
42cbf068 SC |
7489 | if (emulation_type & EMULTYPE_VMWARE_GP) { |
7490 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
60fc3d02 | 7491 | return 1; |
42cbf068 | 7492 | } |
e2366171 | 7493 | |
19238e75 AL |
7494 | if (kvm->arch.exit_on_emulation_error || |
7495 | (emulation_type & EMULTYPE_SKIP)) { | |
7496 | prepare_emulation_failure_exit(vcpu); | |
60fc3d02 | 7497 | return 0; |
738fece4 SC |
7498 | } |
7499 | ||
22da61c9 SC |
7500 | kvm_queue_exception(vcpu, UD_VECTOR); |
7501 | ||
b3646477 | 7502 | if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) { |
fc3a9157 JR |
7503 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
7504 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
7505 | vcpu->run->internal.ndata = 0; | |
60fc3d02 | 7506 | return 0; |
fc3a9157 | 7507 | } |
e2366171 | 7508 | |
60fc3d02 | 7509 | return 1; |
6d77dbfc GN |
7510 | } |
7511 | ||
736c291c | 7512 | static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
991eebf9 GN |
7513 | bool write_fault_to_shadow_pgtable, |
7514 | int emulation_type) | |
a6f177ef | 7515 | { |
736c291c | 7516 | gpa_t gpa = cr2_or_gpa; |
ba049e93 | 7517 | kvm_pfn_t pfn; |
a6f177ef | 7518 | |
92daa48b | 7519 | if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) |
991eebf9 GN |
7520 | return false; |
7521 | ||
92daa48b SC |
7522 | if (WARN_ON_ONCE(is_guest_mode(vcpu)) || |
7523 | WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) | |
6c3dfeb6 SC |
7524 | return false; |
7525 | ||
44dd3ffa | 7526 | if (!vcpu->arch.mmu->direct_map) { |
95b3cf69 XG |
7527 | /* |
7528 | * Write permission should be allowed since only | |
7529 | * write access need to be emulated. | |
7530 | */ | |
736c291c | 7531 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); |
a6f177ef | 7532 | |
95b3cf69 XG |
7533 | /* |
7534 | * If the mapping is invalid in guest, let cpu retry | |
7535 | * it to generate fault. | |
7536 | */ | |
7537 | if (gpa == UNMAPPED_GVA) | |
7538 | return true; | |
7539 | } | |
a6f177ef | 7540 | |
8e3d9d06 XG |
7541 | /* |
7542 | * Do not retry the unhandleable instruction if it faults on the | |
7543 | * readonly host memory, otherwise it will goto a infinite loop: | |
7544 | * retry instruction -> write #PF -> emulation fail -> retry | |
7545 | * instruction -> ... | |
7546 | */ | |
7547 | pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); | |
95b3cf69 XG |
7548 | |
7549 | /* | |
7550 | * If the instruction failed on the error pfn, it can not be fixed, | |
7551 | * report the error to userspace. | |
7552 | */ | |
7553 | if (is_error_noslot_pfn(pfn)) | |
7554 | return false; | |
7555 | ||
7556 | kvm_release_pfn_clean(pfn); | |
7557 | ||
7558 | /* The instructions are well-emulated on direct mmu. */ | |
44dd3ffa | 7559 | if (vcpu->arch.mmu->direct_map) { |
95b3cf69 XG |
7560 | unsigned int indirect_shadow_pages; |
7561 | ||
531810ca | 7562 | write_lock(&vcpu->kvm->mmu_lock); |
95b3cf69 | 7563 | indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; |
531810ca | 7564 | write_unlock(&vcpu->kvm->mmu_lock); |
95b3cf69 XG |
7565 | |
7566 | if (indirect_shadow_pages) | |
7567 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
7568 | ||
a6f177ef | 7569 | return true; |
8e3d9d06 | 7570 | } |
a6f177ef | 7571 | |
95b3cf69 XG |
7572 | /* |
7573 | * if emulation was due to access to shadowed page table | |
7574 | * and it failed try to unshadow page and re-enter the | |
7575 | * guest to let CPU execute the instruction. | |
7576 | */ | |
7577 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
93c05d3e XG |
7578 | |
7579 | /* | |
7580 | * If the access faults on its page table, it can not | |
7581 | * be fixed by unprotecting shadow page and it should | |
7582 | * be reported to userspace. | |
7583 | */ | |
7584 | return !write_fault_to_shadow_pgtable; | |
a6f177ef GN |
7585 | } |
7586 | ||
1cb3f3ae | 7587 | static bool retry_instruction(struct x86_emulate_ctxt *ctxt, |
736c291c | 7588 | gpa_t cr2_or_gpa, int emulation_type) |
1cb3f3ae XG |
7589 | { |
7590 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
736c291c | 7591 | unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa; |
1cb3f3ae XG |
7592 | |
7593 | last_retry_eip = vcpu->arch.last_retry_eip; | |
7594 | last_retry_addr = vcpu->arch.last_retry_addr; | |
7595 | ||
7596 | /* | |
7597 | * If the emulation is caused by #PF and it is non-page_table | |
7598 | * writing instruction, it means the VM-EXIT is caused by shadow | |
7599 | * page protected, we can zap the shadow page and retry this | |
7600 | * instruction directly. | |
7601 | * | |
7602 | * Note: if the guest uses a non-page-table modifying instruction | |
7603 | * on the PDE that points to the instruction, then we will unmap | |
7604 | * the instruction and go to an infinite loop. So, we cache the | |
7605 | * last retried eip and the last fault address, if we meet the eip | |
7606 | * and the address again, we can break out of the potential infinite | |
7607 | * loop. | |
7608 | */ | |
7609 | vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; | |
7610 | ||
92daa48b | 7611 | if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) |
1cb3f3ae XG |
7612 | return false; |
7613 | ||
92daa48b SC |
7614 | if (WARN_ON_ONCE(is_guest_mode(vcpu)) || |
7615 | WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) | |
6c3dfeb6 SC |
7616 | return false; |
7617 | ||
1cb3f3ae XG |
7618 | if (x86_page_table_writing_insn(ctxt)) |
7619 | return false; | |
7620 | ||
736c291c | 7621 | if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa) |
1cb3f3ae XG |
7622 | return false; |
7623 | ||
7624 | vcpu->arch.last_retry_eip = ctxt->eip; | |
736c291c | 7625 | vcpu->arch.last_retry_addr = cr2_or_gpa; |
1cb3f3ae | 7626 | |
44dd3ffa | 7627 | if (!vcpu->arch.mmu->direct_map) |
736c291c | 7628 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); |
1cb3f3ae | 7629 | |
22368028 | 7630 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); |
1cb3f3ae XG |
7631 | |
7632 | return true; | |
7633 | } | |
7634 | ||
716d51ab GN |
7635 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu); |
7636 | static int complete_emulated_pio(struct kvm_vcpu *vcpu); | |
7637 | ||
dc87275f | 7638 | static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm) |
a584539b | 7639 | { |
1270e647 | 7640 | trace_kvm_smm_transition(vcpu->vcpu_id, vcpu->arch.smbase, entering_smm); |
0d7ee6f4 | 7641 | |
dc87275f SC |
7642 | if (entering_smm) { |
7643 | vcpu->arch.hflags |= HF_SMM_MASK; | |
7644 | } else { | |
7645 | vcpu->arch.hflags &= ~(HF_SMM_MASK | HF_SMM_INSIDE_NMI_MASK); | |
7646 | ||
c43203ca PB |
7647 | /* Process a latched INIT or SMI, if any. */ |
7648 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
64d60670 | 7649 | } |
699023e2 PB |
7650 | |
7651 | kvm_mmu_reset_context(vcpu); | |
64d60670 PB |
7652 | } |
7653 | ||
4a1e10d5 PB |
7654 | static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, |
7655 | unsigned long *db) | |
7656 | { | |
7657 | u32 dr6 = 0; | |
7658 | int i; | |
7659 | u32 enable, rwlen; | |
7660 | ||
7661 | enable = dr7; | |
7662 | rwlen = dr7 >> 16; | |
7663 | for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) | |
7664 | if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) | |
7665 | dr6 |= (1 << i); | |
7666 | return dr6; | |
7667 | } | |
7668 | ||
120c2c4f | 7669 | static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu) |
663f4c61 PB |
7670 | { |
7671 | struct kvm_run *kvm_run = vcpu->run; | |
7672 | ||
c8401dda | 7673 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { |
9a3ecd5e | 7674 | kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW; |
d5d260c5 | 7675 | kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu); |
c8401dda PB |
7676 | kvm_run->debug.arch.exception = DB_VECTOR; |
7677 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
60fc3d02 | 7678 | return 0; |
663f4c61 | 7679 | } |
120c2c4f | 7680 | kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); |
60fc3d02 | 7681 | return 1; |
663f4c61 PB |
7682 | } |
7683 | ||
6affcbed KH |
7684 | int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) |
7685 | { | |
b3646477 | 7686 | unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); |
f8ea7c60 | 7687 | int r; |
6affcbed | 7688 | |
b3646477 | 7689 | r = static_call(kvm_x86_skip_emulated_instruction)(vcpu); |
60fc3d02 | 7690 | if (unlikely(!r)) |
f8ea7c60 | 7691 | return 0; |
c8401dda PB |
7692 | |
7693 | /* | |
7694 | * rflags is the old, "raw" value of the flags. The new value has | |
7695 | * not been saved yet. | |
7696 | * | |
7697 | * This is correct even for TF set by the guest, because "the | |
7698 | * processor will not generate this exception after the instruction | |
7699 | * that sets the TF flag". | |
7700 | */ | |
7701 | if (unlikely(rflags & X86_EFLAGS_TF)) | |
120c2c4f | 7702 | r = kvm_vcpu_do_singlestep(vcpu); |
60fc3d02 | 7703 | return r; |
6affcbed KH |
7704 | } |
7705 | EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); | |
7706 | ||
4a1e10d5 PB |
7707 | static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) |
7708 | { | |
4a1e10d5 PB |
7709 | if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && |
7710 | (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { | |
82b32774 NA |
7711 | struct kvm_run *kvm_run = vcpu->run; |
7712 | unsigned long eip = kvm_get_linear_rip(vcpu); | |
7713 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
7714 | vcpu->arch.guest_debug_dr7, |
7715 | vcpu->arch.eff_db); | |
7716 | ||
7717 | if (dr6 != 0) { | |
9a3ecd5e | 7718 | kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW; |
82b32774 | 7719 | kvm_run->debug.arch.pc = eip; |
4a1e10d5 PB |
7720 | kvm_run->debug.arch.exception = DB_VECTOR; |
7721 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
60fc3d02 | 7722 | *r = 0; |
4a1e10d5 PB |
7723 | return true; |
7724 | } | |
7725 | } | |
7726 | ||
4161a569 NA |
7727 | if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && |
7728 | !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { | |
82b32774 NA |
7729 | unsigned long eip = kvm_get_linear_rip(vcpu); |
7730 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
7731 | vcpu->arch.dr7, |
7732 | vcpu->arch.db); | |
7733 | ||
7734 | if (dr6 != 0) { | |
4d5523cf | 7735 | kvm_queue_exception_p(vcpu, DB_VECTOR, dr6); |
60fc3d02 | 7736 | *r = 1; |
4a1e10d5 PB |
7737 | return true; |
7738 | } | |
7739 | } | |
7740 | ||
7741 | return false; | |
7742 | } | |
7743 | ||
04789b66 LA |
7744 | static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) |
7745 | { | |
2d7921c4 AM |
7746 | switch (ctxt->opcode_len) { |
7747 | case 1: | |
7748 | switch (ctxt->b) { | |
7749 | case 0xe4: /* IN */ | |
7750 | case 0xe5: | |
7751 | case 0xec: | |
7752 | case 0xed: | |
7753 | case 0xe6: /* OUT */ | |
7754 | case 0xe7: | |
7755 | case 0xee: | |
7756 | case 0xef: | |
7757 | case 0x6c: /* INS */ | |
7758 | case 0x6d: | |
7759 | case 0x6e: /* OUTS */ | |
7760 | case 0x6f: | |
7761 | return true; | |
7762 | } | |
7763 | break; | |
7764 | case 2: | |
7765 | switch (ctxt->b) { | |
7766 | case 0x33: /* RDPMC */ | |
7767 | return true; | |
7768 | } | |
7769 | break; | |
04789b66 LA |
7770 | } |
7771 | ||
7772 | return false; | |
7773 | } | |
7774 | ||
4aa2691d WH |
7775 | /* |
7776 | * Decode to be emulated instruction. Return EMULATION_OK if success. | |
7777 | */ | |
7778 | int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type, | |
7779 | void *insn, int insn_len) | |
7780 | { | |
7781 | int r = EMULATION_OK; | |
7782 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; | |
7783 | ||
7784 | init_emulate_ctxt(vcpu); | |
7785 | ||
7786 | /* | |
7787 | * We will reenter on the same instruction since we do not set | |
7788 | * complete_userspace_io. This does not handle watchpoints yet, | |
7789 | * those would be handled in the emulate_ops. | |
7790 | */ | |
7791 | if (!(emulation_type & EMULTYPE_SKIP) && | |
7792 | kvm_vcpu_check_breakpoint(vcpu, &r)) | |
7793 | return r; | |
7794 | ||
b35491e6 | 7795 | r = x86_decode_insn(ctxt, insn, insn_len, emulation_type); |
4aa2691d WH |
7796 | |
7797 | trace_kvm_emulate_insn_start(vcpu); | |
7798 | ++vcpu->stat.insn_emulation; | |
7799 | ||
7800 | return r; | |
7801 | } | |
7802 | EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction); | |
7803 | ||
736c291c SC |
7804 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
7805 | int emulation_type, void *insn, int insn_len) | |
bbd9b64e | 7806 | { |
95cb2295 | 7807 | int r; |
c9b8b07c | 7808 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
7ae441ea | 7809 | bool writeback = true; |
09e3e2a1 SC |
7810 | bool write_fault_to_spt; |
7811 | ||
b3646477 | 7812 | if (unlikely(!static_call(kvm_x86_can_emulate_instruction)(vcpu, insn, insn_len))) |
09e3e2a1 | 7813 | return 1; |
bbd9b64e | 7814 | |
c595ceee PB |
7815 | vcpu->arch.l1tf_flush_l1d = true; |
7816 | ||
93c05d3e XG |
7817 | /* |
7818 | * Clear write_fault_to_shadow_pgtable here to ensure it is | |
7819 | * never reused. | |
7820 | */ | |
09e3e2a1 | 7821 | write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; |
93c05d3e | 7822 | vcpu->arch.write_fault_to_shadow_pgtable = false; |
8d7d8102 | 7823 | |
571008da | 7824 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
4aa2691d | 7825 | kvm_clear_exception_queue(vcpu); |
4a1e10d5 | 7826 | |
4aa2691d WH |
7827 | r = x86_decode_emulated_instruction(vcpu, emulation_type, |
7828 | insn, insn_len); | |
1d2887e2 | 7829 | if (r != EMULATION_OK) { |
b4000606 | 7830 | if ((emulation_type & EMULTYPE_TRAP_UD) || |
c83fad65 SC |
7831 | (emulation_type & EMULTYPE_TRAP_UD_FORCED)) { |
7832 | kvm_queue_exception(vcpu, UD_VECTOR); | |
60fc3d02 | 7833 | return 1; |
c83fad65 | 7834 | } |
736c291c SC |
7835 | if (reexecute_instruction(vcpu, cr2_or_gpa, |
7836 | write_fault_to_spt, | |
7837 | emulation_type)) | |
60fc3d02 | 7838 | return 1; |
8530a79c | 7839 | if (ctxt->have_exception) { |
c8848cee JD |
7840 | /* |
7841 | * #UD should result in just EMULATION_FAILED, and trap-like | |
7842 | * exception should not be encountered during decode. | |
7843 | */ | |
7844 | WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || | |
7845 | exception_type(ctxt->exception.vector) == EXCPT_TRAP); | |
8530a79c | 7846 | inject_emulated_exception(vcpu); |
60fc3d02 | 7847 | return 1; |
8530a79c | 7848 | } |
e2366171 | 7849 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
7850 | } |
7851 | } | |
7852 | ||
42cbf068 SC |
7853 | if ((emulation_type & EMULTYPE_VMWARE_GP) && |
7854 | !is_vmware_backdoor_opcode(ctxt)) { | |
7855 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
60fc3d02 | 7856 | return 1; |
42cbf068 | 7857 | } |
04789b66 | 7858 | |
1957aa63 SC |
7859 | /* |
7860 | * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks | |
7861 | * for kvm_skip_emulated_instruction(). The caller is responsible for | |
7862 | * updating interruptibility state and injecting single-step #DBs. | |
7863 | */ | |
ba8afb6b | 7864 | if (emulation_type & EMULTYPE_SKIP) { |
9dac77fa | 7865 | kvm_rip_write(vcpu, ctxt->_eip); |
bb663c7a NA |
7866 | if (ctxt->eflags & X86_EFLAGS_RF) |
7867 | kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); | |
60fc3d02 | 7868 | return 1; |
ba8afb6b GN |
7869 | } |
7870 | ||
736c291c | 7871 | if (retry_instruction(ctxt, cr2_or_gpa, emulation_type)) |
60fc3d02 | 7872 | return 1; |
1cb3f3ae | 7873 | |
7ae441ea | 7874 | /* this is needed for vmware backdoor interface to work since it |
4d2179e1 | 7875 | changes registers values during IO operation */ |
7ae441ea GN |
7876 | if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { |
7877 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; | |
dd856efa | 7878 | emulator_invalidate_register_cache(ctxt); |
7ae441ea | 7879 | } |
4d2179e1 | 7880 | |
5cd21917 | 7881 | restart: |
92daa48b SC |
7882 | if (emulation_type & EMULTYPE_PF) { |
7883 | /* Save the faulting GPA (cr2) in the address field */ | |
7884 | ctxt->exception.address = cr2_or_gpa; | |
7885 | ||
7886 | /* With shadow page tables, cr2 contains a GVA or nGPA. */ | |
7887 | if (vcpu->arch.mmu->direct_map) { | |
744e699c SC |
7888 | ctxt->gpa_available = true; |
7889 | ctxt->gpa_val = cr2_or_gpa; | |
92daa48b SC |
7890 | } |
7891 | } else { | |
7892 | /* Sanitize the address out of an abundance of paranoia. */ | |
7893 | ctxt->exception.address = 0; | |
7894 | } | |
0f89b207 | 7895 | |
9d74191a | 7896 | r = x86_emulate_insn(ctxt); |
bbd9b64e | 7897 | |
775fde86 | 7898 | if (r == EMULATION_INTERCEPTED) |
60fc3d02 | 7899 | return 1; |
775fde86 | 7900 | |
d2ddd1c4 | 7901 | if (r == EMULATION_FAILED) { |
736c291c | 7902 | if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt, |
991eebf9 | 7903 | emulation_type)) |
60fc3d02 | 7904 | return 1; |
c3cd7ffa | 7905 | |
e2366171 | 7906 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
7907 | } |
7908 | ||
9d74191a | 7909 | if (ctxt->have_exception) { |
60fc3d02 | 7910 | r = 1; |
ef54bcfe PB |
7911 | if (inject_emulated_exception(vcpu)) |
7912 | return r; | |
d2ddd1c4 | 7913 | } else if (vcpu->arch.pio.count) { |
0912c977 PB |
7914 | if (!vcpu->arch.pio.in) { |
7915 | /* FIXME: return into emulator if single-stepping. */ | |
3457e419 | 7916 | vcpu->arch.pio.count = 0; |
0912c977 | 7917 | } else { |
7ae441ea | 7918 | writeback = false; |
716d51ab GN |
7919 | vcpu->arch.complete_userspace_io = complete_emulated_pio; |
7920 | } | |
60fc3d02 | 7921 | r = 0; |
7ae441ea | 7922 | } else if (vcpu->mmio_needed) { |
bc8a0aaf SC |
7923 | ++vcpu->stat.mmio_exits; |
7924 | ||
7ae441ea GN |
7925 | if (!vcpu->mmio_is_write) |
7926 | writeback = false; | |
60fc3d02 | 7927 | r = 0; |
716d51ab | 7928 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; |
7ae441ea | 7929 | } else if (r == EMULATION_RESTART) |
5cd21917 | 7930 | goto restart; |
d2ddd1c4 | 7931 | else |
60fc3d02 | 7932 | r = 1; |
f850e2e6 | 7933 | |
7ae441ea | 7934 | if (writeback) { |
b3646477 | 7935 | unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); |
9d74191a | 7936 | toggle_interruptibility(vcpu, ctxt->interruptibility); |
7ae441ea | 7937 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
38827dbd | 7938 | if (!ctxt->have_exception || |
75ee23b3 SC |
7939 | exception_type(ctxt->exception.vector) == EXCPT_TRAP) { |
7940 | kvm_rip_write(vcpu, ctxt->eip); | |
384dea1c | 7941 | if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) |
120c2c4f | 7942 | r = kvm_vcpu_do_singlestep(vcpu); |
afaf0b2f | 7943 | if (kvm_x86_ops.update_emulated_instruction) |
b3646477 | 7944 | static_call(kvm_x86_update_emulated_instruction)(vcpu); |
38827dbd | 7945 | __kvm_set_rflags(vcpu, ctxt->eflags); |
75ee23b3 | 7946 | } |
6addfc42 PB |
7947 | |
7948 | /* | |
7949 | * For STI, interrupts are shadowed; so KVM_REQ_EVENT will | |
7950 | * do nothing, and it will be requested again as soon as | |
7951 | * the shadow expires. But we still need to check here, | |
7952 | * because POPF has no interrupt shadow. | |
7953 | */ | |
7954 | if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) | |
7955 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7ae441ea GN |
7956 | } else |
7957 | vcpu->arch.emulate_regs_need_sync_to_vcpu = true; | |
e85d28f8 GN |
7958 | |
7959 | return r; | |
de7d789a | 7960 | } |
c60658d1 SC |
7961 | |
7962 | int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) | |
7963 | { | |
7964 | return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); | |
7965 | } | |
7966 | EXPORT_SYMBOL_GPL(kvm_emulate_instruction); | |
7967 | ||
7968 | int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, | |
7969 | void *insn, int insn_len) | |
7970 | { | |
7971 | return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); | |
7972 | } | |
7973 | EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); | |
de7d789a | 7974 | |
8764ed55 SC |
7975 | static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) |
7976 | { | |
7977 | vcpu->arch.pio.count = 0; | |
7978 | return 1; | |
7979 | } | |
7980 | ||
45def77e SC |
7981 | static int complete_fast_pio_out(struct kvm_vcpu *vcpu) |
7982 | { | |
7983 | vcpu->arch.pio.count = 0; | |
7984 | ||
7985 | if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) | |
7986 | return 1; | |
7987 | ||
7988 | return kvm_skip_emulated_instruction(vcpu); | |
7989 | } | |
7990 | ||
dca7f128 SC |
7991 | static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, |
7992 | unsigned short port) | |
de7d789a | 7993 | { |
de3cd117 | 7994 | unsigned long val = kvm_rax_read(vcpu); |
2e3bb4d8 SC |
7995 | int ret = emulator_pio_out(vcpu, size, port, &val, 1); |
7996 | ||
8764ed55 SC |
7997 | if (ret) |
7998 | return ret; | |
45def77e | 7999 | |
8764ed55 SC |
8000 | /* |
8001 | * Workaround userspace that relies on old KVM behavior of %rip being | |
8002 | * incremented prior to exiting to userspace to handle "OUT 0x7e". | |
8003 | */ | |
8004 | if (port == 0x7e && | |
8005 | kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { | |
8006 | vcpu->arch.complete_userspace_io = | |
8007 | complete_fast_pio_out_port_0x7e; | |
8008 | kvm_skip_emulated_instruction(vcpu); | |
8009 | } else { | |
45def77e SC |
8010 | vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); |
8011 | vcpu->arch.complete_userspace_io = complete_fast_pio_out; | |
8012 | } | |
8764ed55 | 8013 | return 0; |
de7d789a | 8014 | } |
de7d789a | 8015 | |
8370c3d0 TL |
8016 | static int complete_fast_pio_in(struct kvm_vcpu *vcpu) |
8017 | { | |
8018 | unsigned long val; | |
8019 | ||
8020 | /* We should only ever be called with arch.pio.count equal to 1 */ | |
8021 | BUG_ON(vcpu->arch.pio.count != 1); | |
8022 | ||
45def77e SC |
8023 | if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { |
8024 | vcpu->arch.pio.count = 0; | |
8025 | return 1; | |
8026 | } | |
8027 | ||
8370c3d0 | 8028 | /* For size less than 4 we merge, else we zero extend */ |
de3cd117 | 8029 | val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; |
8370c3d0 TL |
8030 | |
8031 | /* | |
2e3bb4d8 | 8032 | * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform |
8370c3d0 TL |
8033 | * the copy and tracing |
8034 | */ | |
2e3bb4d8 | 8035 | emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1); |
de3cd117 | 8036 | kvm_rax_write(vcpu, val); |
8370c3d0 | 8037 | |
45def77e | 8038 | return kvm_skip_emulated_instruction(vcpu); |
8370c3d0 TL |
8039 | } |
8040 | ||
dca7f128 SC |
8041 | static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, |
8042 | unsigned short port) | |
8370c3d0 TL |
8043 | { |
8044 | unsigned long val; | |
8045 | int ret; | |
8046 | ||
8047 | /* For size less than 4 we merge, else we zero extend */ | |
de3cd117 | 8048 | val = (size < 4) ? kvm_rax_read(vcpu) : 0; |
8370c3d0 | 8049 | |
2e3bb4d8 | 8050 | ret = emulator_pio_in(vcpu, size, port, &val, 1); |
8370c3d0 | 8051 | if (ret) { |
de3cd117 | 8052 | kvm_rax_write(vcpu, val); |
8370c3d0 TL |
8053 | return ret; |
8054 | } | |
8055 | ||
45def77e | 8056 | vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); |
8370c3d0 TL |
8057 | vcpu->arch.complete_userspace_io = complete_fast_pio_in; |
8058 | ||
8059 | return 0; | |
8060 | } | |
dca7f128 SC |
8061 | |
8062 | int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) | |
8063 | { | |
45def77e | 8064 | int ret; |
dca7f128 | 8065 | |
dca7f128 | 8066 | if (in) |
45def77e | 8067 | ret = kvm_fast_pio_in(vcpu, size, port); |
dca7f128 | 8068 | else |
45def77e SC |
8069 | ret = kvm_fast_pio_out(vcpu, size, port); |
8070 | return ret && kvm_skip_emulated_instruction(vcpu); | |
dca7f128 SC |
8071 | } |
8072 | EXPORT_SYMBOL_GPL(kvm_fast_pio); | |
8370c3d0 | 8073 | |
251a5fd6 | 8074 | static int kvmclock_cpu_down_prep(unsigned int cpu) |
8cfdc000 | 8075 | { |
0a3aee0d | 8076 | __this_cpu_write(cpu_tsc_khz, 0); |
251a5fd6 | 8077 | return 0; |
8cfdc000 ZA |
8078 | } |
8079 | ||
8080 | static void tsc_khz_changed(void *data) | |
c8076604 | 8081 | { |
8cfdc000 ZA |
8082 | struct cpufreq_freqs *freq = data; |
8083 | unsigned long khz = 0; | |
8084 | ||
8085 | if (data) | |
8086 | khz = freq->new; | |
8087 | else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
8088 | khz = cpufreq_quick_get(raw_smp_processor_id()); | |
8089 | if (!khz) | |
8090 | khz = tsc_khz; | |
0a3aee0d | 8091 | __this_cpu_write(cpu_tsc_khz, khz); |
c8076604 GH |
8092 | } |
8093 | ||
5fa4ec9c | 8094 | #ifdef CONFIG_X86_64 |
0092e434 VK |
8095 | static void kvm_hyperv_tsc_notifier(void) |
8096 | { | |
0092e434 VK |
8097 | struct kvm *kvm; |
8098 | struct kvm_vcpu *vcpu; | |
8099 | int cpu; | |
a83829f5 | 8100 | unsigned long flags; |
0092e434 | 8101 | |
0d9ce162 | 8102 | mutex_lock(&kvm_lock); |
0092e434 VK |
8103 | list_for_each_entry(kvm, &vm_list, vm_list) |
8104 | kvm_make_mclock_inprogress_request(kvm); | |
8105 | ||
8106 | hyperv_stop_tsc_emulation(); | |
8107 | ||
8108 | /* TSC frequency always matches when on Hyper-V */ | |
8109 | for_each_present_cpu(cpu) | |
8110 | per_cpu(cpu_tsc_khz, cpu) = tsc_khz; | |
8111 | kvm_max_guest_tsc_khz = tsc_khz; | |
8112 | ||
8113 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
8114 | struct kvm_arch *ka = &kvm->arch; | |
8115 | ||
a83829f5 | 8116 | spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); |
0092e434 | 8117 | pvclock_update_vm_gtod_copy(kvm); |
a83829f5 | 8118 | spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); |
0092e434 VK |
8119 | |
8120 | kvm_for_each_vcpu(cpu, vcpu, kvm) | |
8121 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
8122 | ||
8123 | kvm_for_each_vcpu(cpu, vcpu, kvm) | |
8124 | kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); | |
0092e434 | 8125 | } |
0d9ce162 | 8126 | mutex_unlock(&kvm_lock); |
0092e434 | 8127 | } |
5fa4ec9c | 8128 | #endif |
0092e434 | 8129 | |
df24014a | 8130 | static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) |
c8076604 | 8131 | { |
c8076604 GH |
8132 | struct kvm *kvm; |
8133 | struct kvm_vcpu *vcpu; | |
8134 | int i, send_ipi = 0; | |
8135 | ||
8cfdc000 ZA |
8136 | /* |
8137 | * We allow guests to temporarily run on slowing clocks, | |
8138 | * provided we notify them after, or to run on accelerating | |
8139 | * clocks, provided we notify them before. Thus time never | |
8140 | * goes backwards. | |
8141 | * | |
8142 | * However, we have a problem. We can't atomically update | |
8143 | * the frequency of a given CPU from this function; it is | |
8144 | * merely a notifier, which can be called from any CPU. | |
8145 | * Changing the TSC frequency at arbitrary points in time | |
8146 | * requires a recomputation of local variables related to | |
8147 | * the TSC for each VCPU. We must flag these local variables | |
8148 | * to be updated and be sure the update takes place with the | |
8149 | * new frequency before any guests proceed. | |
8150 | * | |
8151 | * Unfortunately, the combination of hotplug CPU and frequency | |
8152 | * change creates an intractable locking scenario; the order | |
8153 | * of when these callouts happen is undefined with respect to | |
8154 | * CPU hotplug, and they can race with each other. As such, | |
8155 | * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is | |
8156 | * undefined; you can actually have a CPU frequency change take | |
8157 | * place in between the computation of X and the setting of the | |
8158 | * variable. To protect against this problem, all updates of | |
8159 | * the per_cpu tsc_khz variable are done in an interrupt | |
8160 | * protected IPI, and all callers wishing to update the value | |
8161 | * must wait for a synchronous IPI to complete (which is trivial | |
8162 | * if the caller is on the CPU already). This establishes the | |
8163 | * necessary total order on variable updates. | |
8164 | * | |
8165 | * Note that because a guest time update may take place | |
8166 | * anytime after the setting of the VCPU's request bit, the | |
8167 | * correct TSC value must be set before the request. However, | |
8168 | * to ensure the update actually makes it to any guest which | |
8169 | * starts running in hardware virtualization between the set | |
8170 | * and the acquisition of the spinlock, we must also ping the | |
8171 | * CPU after setting the request bit. | |
8172 | * | |
8173 | */ | |
8174 | ||
df24014a | 8175 | smp_call_function_single(cpu, tsc_khz_changed, freq, 1); |
c8076604 | 8176 | |
0d9ce162 | 8177 | mutex_lock(&kvm_lock); |
c8076604 | 8178 | list_for_each_entry(kvm, &vm_list, vm_list) { |
988a2cae | 8179 | kvm_for_each_vcpu(i, vcpu, kvm) { |
df24014a | 8180 | if (vcpu->cpu != cpu) |
c8076604 | 8181 | continue; |
c285545f | 8182 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0d9ce162 | 8183 | if (vcpu->cpu != raw_smp_processor_id()) |
8cfdc000 | 8184 | send_ipi = 1; |
c8076604 GH |
8185 | } |
8186 | } | |
0d9ce162 | 8187 | mutex_unlock(&kvm_lock); |
c8076604 GH |
8188 | |
8189 | if (freq->old < freq->new && send_ipi) { | |
8190 | /* | |
8191 | * We upscale the frequency. Must make the guest | |
8192 | * doesn't see old kvmclock values while running with | |
8193 | * the new frequency, otherwise we risk the guest sees | |
8194 | * time go backwards. | |
8195 | * | |
8196 | * In case we update the frequency for another cpu | |
8197 | * (which might be in guest context) send an interrupt | |
8198 | * to kick the cpu out of guest context. Next time | |
8199 | * guest context is entered kvmclock will be updated, | |
8200 | * so the guest will not see stale values. | |
8201 | */ | |
df24014a | 8202 | smp_call_function_single(cpu, tsc_khz_changed, freq, 1); |
c8076604 | 8203 | } |
df24014a VK |
8204 | } |
8205 | ||
8206 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, | |
8207 | void *data) | |
8208 | { | |
8209 | struct cpufreq_freqs *freq = data; | |
8210 | int cpu; | |
8211 | ||
8212 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) | |
8213 | return 0; | |
8214 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
8215 | return 0; | |
8216 | ||
8217 | for_each_cpu(cpu, freq->policy->cpus) | |
8218 | __kvmclock_cpufreq_notifier(freq, cpu); | |
8219 | ||
c8076604 GH |
8220 | return 0; |
8221 | } | |
8222 | ||
8223 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
8cfdc000 ZA |
8224 | .notifier_call = kvmclock_cpufreq_notifier |
8225 | }; | |
8226 | ||
251a5fd6 | 8227 | static int kvmclock_cpu_online(unsigned int cpu) |
8cfdc000 | 8228 | { |
251a5fd6 SAS |
8229 | tsc_khz_changed(NULL); |
8230 | return 0; | |
8cfdc000 ZA |
8231 | } |
8232 | ||
b820cc0c ZA |
8233 | static void kvm_timer_init(void) |
8234 | { | |
c285545f | 8235 | max_tsc_khz = tsc_khz; |
460dd42e | 8236 | |
b820cc0c | 8237 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
c285545f | 8238 | #ifdef CONFIG_CPU_FREQ |
aaec7c03 | 8239 | struct cpufreq_policy *policy; |
758f588d BP |
8240 | int cpu; |
8241 | ||
3e26f230 | 8242 | cpu = get_cpu(); |
aaec7c03 | 8243 | policy = cpufreq_cpu_get(cpu); |
9a11997e WL |
8244 | if (policy) { |
8245 | if (policy->cpuinfo.max_freq) | |
8246 | max_tsc_khz = policy->cpuinfo.max_freq; | |
8247 | cpufreq_cpu_put(policy); | |
8248 | } | |
3e26f230 | 8249 | put_cpu(); |
c285545f | 8250 | #endif |
b820cc0c ZA |
8251 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
8252 | CPUFREQ_TRANSITION_NOTIFIER); | |
8253 | } | |
460dd42e | 8254 | |
73c1b41e | 8255 | cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", |
251a5fd6 | 8256 | kvmclock_cpu_online, kvmclock_cpu_down_prep); |
b820cc0c ZA |
8257 | } |
8258 | ||
dd60d217 AK |
8259 | DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); |
8260 | EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu); | |
ff9d07a0 | 8261 | |
f5132b01 | 8262 | int kvm_is_in_guest(void) |
ff9d07a0 | 8263 | { |
086c9855 | 8264 | return __this_cpu_read(current_vcpu) != NULL; |
ff9d07a0 ZY |
8265 | } |
8266 | ||
8267 | static int kvm_is_user_mode(void) | |
8268 | { | |
8269 | int user_mode = 3; | |
dcf46b94 | 8270 | |
086c9855 | 8271 | if (__this_cpu_read(current_vcpu)) |
b3646477 | 8272 | user_mode = static_call(kvm_x86_get_cpl)(__this_cpu_read(current_vcpu)); |
dcf46b94 | 8273 | |
ff9d07a0 ZY |
8274 | return user_mode != 0; |
8275 | } | |
8276 | ||
8277 | static unsigned long kvm_get_guest_ip(void) | |
8278 | { | |
8279 | unsigned long ip = 0; | |
dcf46b94 | 8280 | |
086c9855 AS |
8281 | if (__this_cpu_read(current_vcpu)) |
8282 | ip = kvm_rip_read(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 8283 | |
ff9d07a0 ZY |
8284 | return ip; |
8285 | } | |
8286 | ||
8479e04e LK |
8287 | static void kvm_handle_intel_pt_intr(void) |
8288 | { | |
8289 | struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu); | |
8290 | ||
8291 | kvm_make_request(KVM_REQ_PMI, vcpu); | |
8292 | __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT, | |
8293 | (unsigned long *)&vcpu->arch.pmu.global_status); | |
8294 | } | |
8295 | ||
ff9d07a0 ZY |
8296 | static struct perf_guest_info_callbacks kvm_guest_cbs = { |
8297 | .is_in_guest = kvm_is_in_guest, | |
8298 | .is_user_mode = kvm_is_user_mode, | |
8299 | .get_guest_ip = kvm_get_guest_ip, | |
8479e04e | 8300 | .handle_intel_pt_intr = kvm_handle_intel_pt_intr, |
ff9d07a0 ZY |
8301 | }; |
8302 | ||
16e8d74d MT |
8303 | #ifdef CONFIG_X86_64 |
8304 | static void pvclock_gtod_update_fn(struct work_struct *work) | |
8305 | { | |
d828199e MT |
8306 | struct kvm *kvm; |
8307 | ||
8308 | struct kvm_vcpu *vcpu; | |
8309 | int i; | |
8310 | ||
0d9ce162 | 8311 | mutex_lock(&kvm_lock); |
d828199e MT |
8312 | list_for_each_entry(kvm, &vm_list, vm_list) |
8313 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 8314 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
d828199e | 8315 | atomic_set(&kvm_guest_has_master_clock, 0); |
0d9ce162 | 8316 | mutex_unlock(&kvm_lock); |
16e8d74d MT |
8317 | } |
8318 | ||
8319 | static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); | |
8320 | ||
3f804f6d TG |
8321 | /* |
8322 | * Indirection to move queue_work() out of the tk_core.seq write held | |
8323 | * region to prevent possible deadlocks against time accessors which | |
8324 | * are invoked with work related locks held. | |
8325 | */ | |
8326 | static void pvclock_irq_work_fn(struct irq_work *w) | |
8327 | { | |
8328 | queue_work(system_long_wq, &pvclock_gtod_work); | |
8329 | } | |
8330 | ||
8331 | static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn); | |
8332 | ||
16e8d74d MT |
8333 | /* |
8334 | * Notification about pvclock gtod data update. | |
8335 | */ | |
8336 | static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, | |
8337 | void *priv) | |
8338 | { | |
8339 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
8340 | struct timekeeper *tk = priv; | |
8341 | ||
8342 | update_pvclock_gtod(tk); | |
8343 | ||
3f804f6d TG |
8344 | /* |
8345 | * Disable master clock if host does not trust, or does not use, | |
8346 | * TSC based clocksource. Delegate queue_work() to irq_work as | |
8347 | * this is invoked with tk_core.seq write held. | |
16e8d74d | 8348 | */ |
b0c39dc6 | 8349 | if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && |
16e8d74d | 8350 | atomic_read(&kvm_guest_has_master_clock) != 0) |
3f804f6d | 8351 | irq_work_queue(&pvclock_irq_work); |
16e8d74d MT |
8352 | return 0; |
8353 | } | |
8354 | ||
8355 | static struct notifier_block pvclock_gtod_notifier = { | |
8356 | .notifier_call = pvclock_gtod_notify, | |
8357 | }; | |
8358 | #endif | |
8359 | ||
f8c16bba | 8360 | int kvm_arch_init(void *opaque) |
043405e1 | 8361 | { |
d008dfdb | 8362 | struct kvm_x86_init_ops *ops = opaque; |
b820cc0c | 8363 | int r; |
f8c16bba | 8364 | |
afaf0b2f | 8365 | if (kvm_x86_ops.hardware_enable) { |
f8c16bba | 8366 | printk(KERN_ERR "kvm: already loaded the other module\n"); |
56c6d28a ZX |
8367 | r = -EEXIST; |
8368 | goto out; | |
f8c16bba ZX |
8369 | } |
8370 | ||
8371 | if (!ops->cpu_has_kvm_support()) { | |
ef935c25 | 8372 | pr_err_ratelimited("kvm: no hardware support\n"); |
56c6d28a ZX |
8373 | r = -EOPNOTSUPP; |
8374 | goto out; | |
f8c16bba ZX |
8375 | } |
8376 | if (ops->disabled_by_bios()) { | |
ef935c25 | 8377 | pr_err_ratelimited("kvm: disabled by bios\n"); |
56c6d28a ZX |
8378 | r = -EOPNOTSUPP; |
8379 | goto out; | |
f8c16bba ZX |
8380 | } |
8381 | ||
b666a4b6 MO |
8382 | /* |
8383 | * KVM explicitly assumes that the guest has an FPU and | |
8384 | * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the | |
8385 | * vCPU's FPU state as a fxregs_state struct. | |
8386 | */ | |
8387 | if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { | |
8388 | printk(KERN_ERR "kvm: inadequate fpu\n"); | |
8389 | r = -EOPNOTSUPP; | |
8390 | goto out; | |
8391 | } | |
8392 | ||
013f6a5d | 8393 | r = -ENOMEM; |
ed8e4812 | 8394 | x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu), |
b666a4b6 MO |
8395 | __alignof__(struct fpu), SLAB_ACCOUNT, |
8396 | NULL); | |
8397 | if (!x86_fpu_cache) { | |
8398 | printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n"); | |
8399 | goto out; | |
8400 | } | |
8401 | ||
c9b8b07c SC |
8402 | x86_emulator_cache = kvm_alloc_emulator_cache(); |
8403 | if (!x86_emulator_cache) { | |
8404 | pr_err("kvm: failed to allocate cache for x86 emulator\n"); | |
8405 | goto out_free_x86_fpu_cache; | |
8406 | } | |
8407 | ||
7e34fbd0 SC |
8408 | user_return_msrs = alloc_percpu(struct kvm_user_return_msrs); |
8409 | if (!user_return_msrs) { | |
8410 | printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n"); | |
c9b8b07c | 8411 | goto out_free_x86_emulator_cache; |
013f6a5d | 8412 | } |
e5fda4bb | 8413 | kvm_nr_uret_msrs = 0; |
013f6a5d | 8414 | |
97db56ce AK |
8415 | r = kvm_mmu_module_init(); |
8416 | if (r) | |
013f6a5d | 8417 | goto out_free_percpu; |
97db56ce | 8418 | |
b820cc0c | 8419 | kvm_timer_init(); |
c8076604 | 8420 | |
ff9d07a0 ZY |
8421 | perf_register_guest_info_callbacks(&kvm_guest_cbs); |
8422 | ||
cfc48181 | 8423 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
2acf923e | 8424 | host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); |
cfc48181 SC |
8425 | supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0; |
8426 | } | |
2acf923e | 8427 | |
0c5f81da WL |
8428 | if (pi_inject_timer == -1) |
8429 | pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER); | |
16e8d74d MT |
8430 | #ifdef CONFIG_X86_64 |
8431 | pvclock_gtod_register_notifier(&pvclock_gtod_notifier); | |
0092e434 | 8432 | |
5fa4ec9c | 8433 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 | 8434 | set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); |
16e8d74d MT |
8435 | #endif |
8436 | ||
f8c16bba | 8437 | return 0; |
56c6d28a | 8438 | |
013f6a5d | 8439 | out_free_percpu: |
7e34fbd0 | 8440 | free_percpu(user_return_msrs); |
c9b8b07c SC |
8441 | out_free_x86_emulator_cache: |
8442 | kmem_cache_destroy(x86_emulator_cache); | |
b666a4b6 MO |
8443 | out_free_x86_fpu_cache: |
8444 | kmem_cache_destroy(x86_fpu_cache); | |
56c6d28a | 8445 | out: |
56c6d28a | 8446 | return r; |
043405e1 | 8447 | } |
8776e519 | 8448 | |
f8c16bba ZX |
8449 | void kvm_arch_exit(void) |
8450 | { | |
0092e434 | 8451 | #ifdef CONFIG_X86_64 |
5fa4ec9c | 8452 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 VK |
8453 | clear_hv_tscchange_cb(); |
8454 | #endif | |
cef84c30 | 8455 | kvm_lapic_exit(); |
ff9d07a0 ZY |
8456 | perf_unregister_guest_info_callbacks(&kvm_guest_cbs); |
8457 | ||
888d256e JK |
8458 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
8459 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
8460 | CPUFREQ_TRANSITION_NOTIFIER); | |
251a5fd6 | 8461 | cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); |
16e8d74d MT |
8462 | #ifdef CONFIG_X86_64 |
8463 | pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); | |
3f804f6d | 8464 | irq_work_sync(&pvclock_irq_work); |
594b27e6 | 8465 | cancel_work_sync(&pvclock_gtod_work); |
16e8d74d | 8466 | #endif |
afaf0b2f | 8467 | kvm_x86_ops.hardware_enable = NULL; |
56c6d28a | 8468 | kvm_mmu_module_exit(); |
7e34fbd0 | 8469 | free_percpu(user_return_msrs); |
dfdc0a71 | 8470 | kmem_cache_destroy(x86_emulator_cache); |
b666a4b6 | 8471 | kmem_cache_destroy(x86_fpu_cache); |
b59b153d | 8472 | #ifdef CONFIG_KVM_XEN |
c462f859 | 8473 | static_key_deferred_flush(&kvm_xen_enabled); |
7d6bbebb | 8474 | WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key)); |
b59b153d | 8475 | #endif |
56c6d28a | 8476 | } |
f8c16bba | 8477 | |
872f36eb | 8478 | static int __kvm_vcpu_halt(struct kvm_vcpu *vcpu, int state, int reason) |
8776e519 HB |
8479 | { |
8480 | ++vcpu->stat.halt_exits; | |
35754c98 | 8481 | if (lapic_in_kernel(vcpu)) { |
647daca2 | 8482 | vcpu->arch.mp_state = state; |
8776e519 HB |
8483 | return 1; |
8484 | } else { | |
647daca2 | 8485 | vcpu->run->exit_reason = reason; |
8776e519 HB |
8486 | return 0; |
8487 | } | |
8488 | } | |
647daca2 TL |
8489 | |
8490 | int kvm_vcpu_halt(struct kvm_vcpu *vcpu) | |
8491 | { | |
8492 | return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT); | |
8493 | } | |
5cb56059 JS |
8494 | EXPORT_SYMBOL_GPL(kvm_vcpu_halt); |
8495 | ||
8496 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) | |
8497 | { | |
6affcbed KH |
8498 | int ret = kvm_skip_emulated_instruction(vcpu); |
8499 | /* | |
8500 | * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered | |
8501 | * KVM_EXIT_DEBUG here. | |
8502 | */ | |
8503 | return kvm_vcpu_halt(vcpu) && ret; | |
5cb56059 | 8504 | } |
8776e519 HB |
8505 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); |
8506 | ||
647daca2 TL |
8507 | int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu) |
8508 | { | |
8509 | int ret = kvm_skip_emulated_instruction(vcpu); | |
8510 | ||
8511 | return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, KVM_EXIT_AP_RESET_HOLD) && ret; | |
8512 | } | |
8513 | EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold); | |
8514 | ||
8ef81a9a | 8515 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
8516 | static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, |
8517 | unsigned long clock_type) | |
8518 | { | |
8519 | struct kvm_clock_pairing clock_pairing; | |
899a31f5 | 8520 | struct timespec64 ts; |
80fbd89c | 8521 | u64 cycle; |
55dd00a7 MT |
8522 | int ret; |
8523 | ||
8524 | if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) | |
8525 | return -KVM_EOPNOTSUPP; | |
8526 | ||
7ca7f3b9 | 8527 | if (!kvm_get_walltime_and_clockread(&ts, &cycle)) |
55dd00a7 MT |
8528 | return -KVM_EOPNOTSUPP; |
8529 | ||
8530 | clock_pairing.sec = ts.tv_sec; | |
8531 | clock_pairing.nsec = ts.tv_nsec; | |
8532 | clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); | |
8533 | clock_pairing.flags = 0; | |
bcbfbd8e | 8534 | memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); |
55dd00a7 MT |
8535 | |
8536 | ret = 0; | |
8537 | if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, | |
8538 | sizeof(struct kvm_clock_pairing))) | |
8539 | ret = -KVM_EFAULT; | |
8540 | ||
8541 | return ret; | |
8542 | } | |
8ef81a9a | 8543 | #endif |
55dd00a7 | 8544 | |
6aef266c SV |
8545 | /* |
8546 | * kvm_pv_kick_cpu_op: Kick a vcpu. | |
8547 | * | |
8548 | * @apicid - apicid of vcpu to be kicked. | |
8549 | */ | |
8550 | static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) | |
8551 | { | |
24d2166b | 8552 | struct kvm_lapic_irq lapic_irq; |
6aef266c | 8553 | |
150a84fe | 8554 | lapic_irq.shorthand = APIC_DEST_NOSHORT; |
c96001c5 | 8555 | lapic_irq.dest_mode = APIC_DEST_PHYSICAL; |
ebd28fcb | 8556 | lapic_irq.level = 0; |
24d2166b | 8557 | lapic_irq.dest_id = apicid; |
93bbf0b8 | 8558 | lapic_irq.msi_redir_hint = false; |
6aef266c | 8559 | |
24d2166b | 8560 | lapic_irq.delivery_mode = APIC_DM_REMRD; |
795a149e | 8561 | kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); |
6aef266c SV |
8562 | } |
8563 | ||
4e19c36f SS |
8564 | bool kvm_apicv_activated(struct kvm *kvm) |
8565 | { | |
8566 | return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0); | |
8567 | } | |
8568 | EXPORT_SYMBOL_GPL(kvm_apicv_activated); | |
8569 | ||
4651fc56 | 8570 | static void kvm_apicv_init(struct kvm *kvm) |
4e19c36f | 8571 | { |
4651fc56 | 8572 | if (enable_apicv) |
4e19c36f SS |
8573 | clear_bit(APICV_INHIBIT_REASON_DISABLE, |
8574 | &kvm->arch.apicv_inhibit_reasons); | |
8575 | else | |
8576 | set_bit(APICV_INHIBIT_REASON_DISABLE, | |
8577 | &kvm->arch.apicv_inhibit_reasons); | |
8578 | } | |
4e19c36f | 8579 | |
4a7132ef | 8580 | static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id) |
71506297 WL |
8581 | { |
8582 | struct kvm_vcpu *target = NULL; | |
8583 | struct kvm_apic_map *map; | |
8584 | ||
4a7132ef WL |
8585 | vcpu->stat.directed_yield_attempted++; |
8586 | ||
72b268a8 WL |
8587 | if (single_task_running()) |
8588 | goto no_yield; | |
8589 | ||
71506297 | 8590 | rcu_read_lock(); |
4a7132ef | 8591 | map = rcu_dereference(vcpu->kvm->arch.apic_map); |
71506297 WL |
8592 | |
8593 | if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) | |
8594 | target = map->phys_map[dest_id]->vcpu; | |
8595 | ||
8596 | rcu_read_unlock(); | |
8597 | ||
4a7132ef WL |
8598 | if (!target || !READ_ONCE(target->ready)) |
8599 | goto no_yield; | |
8600 | ||
a1fa4cbd WL |
8601 | /* Ignore requests to yield to self */ |
8602 | if (vcpu == target) | |
8603 | goto no_yield; | |
8604 | ||
4a7132ef WL |
8605 | if (kvm_vcpu_yield_to(target) <= 0) |
8606 | goto no_yield; | |
8607 | ||
8608 | vcpu->stat.directed_yield_successful++; | |
8609 | ||
8610 | no_yield: | |
8611 | return; | |
71506297 WL |
8612 | } |
8613 | ||
0dbb1123 AK |
8614 | static int complete_hypercall_exit(struct kvm_vcpu *vcpu) |
8615 | { | |
8616 | u64 ret = vcpu->run->hypercall.ret; | |
8617 | ||
8618 | if (!is_64_bit_mode(vcpu)) | |
8619 | ret = (u32)ret; | |
8620 | kvm_rax_write(vcpu, ret); | |
8621 | ++vcpu->stat.hypercalls; | |
8622 | return kvm_skip_emulated_instruction(vcpu); | |
8623 | } | |
8624 | ||
8776e519 HB |
8625 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
8626 | { | |
8627 | unsigned long nr, a0, a1, a2, a3, ret; | |
6356ee0c | 8628 | int op_64_bit; |
8776e519 | 8629 | |
23200b7a JM |
8630 | if (kvm_xen_hypercall_enabled(vcpu->kvm)) |
8631 | return kvm_xen_hypercall(vcpu); | |
8632 | ||
8f014550 | 8633 | if (kvm_hv_hypercall_enabled(vcpu)) |
696ca779 | 8634 | return kvm_hv_hypercall(vcpu); |
55cd8e5a | 8635 | |
de3cd117 SC |
8636 | nr = kvm_rax_read(vcpu); |
8637 | a0 = kvm_rbx_read(vcpu); | |
8638 | a1 = kvm_rcx_read(vcpu); | |
8639 | a2 = kvm_rdx_read(vcpu); | |
8640 | a3 = kvm_rsi_read(vcpu); | |
8776e519 | 8641 | |
229456fc | 8642 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 8643 | |
a449c7aa NA |
8644 | op_64_bit = is_64_bit_mode(vcpu); |
8645 | if (!op_64_bit) { | |
8776e519 HB |
8646 | nr &= 0xFFFFFFFF; |
8647 | a0 &= 0xFFFFFFFF; | |
8648 | a1 &= 0xFFFFFFFF; | |
8649 | a2 &= 0xFFFFFFFF; | |
8650 | a3 &= 0xFFFFFFFF; | |
8651 | } | |
8652 | ||
b3646477 | 8653 | if (static_call(kvm_x86_get_cpl)(vcpu) != 0) { |
07708c4a | 8654 | ret = -KVM_EPERM; |
696ca779 | 8655 | goto out; |
07708c4a JK |
8656 | } |
8657 | ||
66570e96 OU |
8658 | ret = -KVM_ENOSYS; |
8659 | ||
8776e519 | 8660 | switch (nr) { |
b93463aa AK |
8661 | case KVM_HC_VAPIC_POLL_IRQ: |
8662 | ret = 0; | |
8663 | break; | |
6aef266c | 8664 | case KVM_HC_KICK_CPU: |
66570e96 OU |
8665 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT)) |
8666 | break; | |
8667 | ||
6aef266c | 8668 | kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); |
4a7132ef | 8669 | kvm_sched_yield(vcpu, a1); |
6aef266c SV |
8670 | ret = 0; |
8671 | break; | |
8ef81a9a | 8672 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
8673 | case KVM_HC_CLOCK_PAIRING: |
8674 | ret = kvm_pv_clock_pairing(vcpu, a0, a1); | |
8675 | break; | |
1ed199a4 | 8676 | #endif |
4180bf1b | 8677 | case KVM_HC_SEND_IPI: |
66570e96 OU |
8678 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI)) |
8679 | break; | |
8680 | ||
4180bf1b WL |
8681 | ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); |
8682 | break; | |
71506297 | 8683 | case KVM_HC_SCHED_YIELD: |
66570e96 OU |
8684 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD)) |
8685 | break; | |
8686 | ||
4a7132ef | 8687 | kvm_sched_yield(vcpu, a0); |
71506297 WL |
8688 | ret = 0; |
8689 | break; | |
0dbb1123 AK |
8690 | case KVM_HC_MAP_GPA_RANGE: { |
8691 | u64 gpa = a0, npages = a1, attrs = a2; | |
8692 | ||
8693 | ret = -KVM_ENOSYS; | |
8694 | if (!(vcpu->kvm->arch.hypercall_exit_enabled & (1 << KVM_HC_MAP_GPA_RANGE))) | |
8695 | break; | |
8696 | ||
8697 | if (!PAGE_ALIGNED(gpa) || !npages || | |
8698 | gpa_to_gfn(gpa) + npages <= gpa_to_gfn(gpa)) { | |
8699 | ret = -KVM_EINVAL; | |
8700 | break; | |
8701 | } | |
8702 | ||
8703 | vcpu->run->exit_reason = KVM_EXIT_HYPERCALL; | |
8704 | vcpu->run->hypercall.nr = KVM_HC_MAP_GPA_RANGE; | |
8705 | vcpu->run->hypercall.args[0] = gpa; | |
8706 | vcpu->run->hypercall.args[1] = npages; | |
8707 | vcpu->run->hypercall.args[2] = attrs; | |
8708 | vcpu->run->hypercall.longmode = op_64_bit; | |
8709 | vcpu->arch.complete_userspace_io = complete_hypercall_exit; | |
8710 | return 0; | |
8711 | } | |
8776e519 HB |
8712 | default: |
8713 | ret = -KVM_ENOSYS; | |
8714 | break; | |
8715 | } | |
696ca779 | 8716 | out: |
a449c7aa NA |
8717 | if (!op_64_bit) |
8718 | ret = (u32)ret; | |
de3cd117 | 8719 | kvm_rax_write(vcpu, ret); |
6356ee0c | 8720 | |
f11c3a8d | 8721 | ++vcpu->stat.hypercalls; |
6356ee0c | 8722 | return kvm_skip_emulated_instruction(vcpu); |
8776e519 HB |
8723 | } |
8724 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
8725 | ||
b6785def | 8726 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) |
8776e519 | 8727 | { |
d6aa1000 | 8728 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
8776e519 | 8729 | char instruction[3]; |
5fdbf976 | 8730 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 8731 | |
b3646477 | 8732 | static_call(kvm_x86_patch_hypercall)(vcpu, instruction); |
8776e519 | 8733 | |
ce2e852e DV |
8734 | return emulator_write_emulated(ctxt, rip, instruction, 3, |
8735 | &ctxt->exception); | |
8776e519 HB |
8736 | } |
8737 | ||
851ba692 | 8738 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 8739 | { |
782d422b MG |
8740 | return vcpu->run->request_interrupt_window && |
8741 | likely(!pic_in_kernel(vcpu->kvm)); | |
b6c7a5dc HB |
8742 | } |
8743 | ||
851ba692 | 8744 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 8745 | { |
851ba692 AK |
8746 | struct kvm_run *kvm_run = vcpu->run; |
8747 | ||
f1c6366e TL |
8748 | /* |
8749 | * if_flag is obsolete and useless, so do not bother | |
8750 | * setting it for SEV-ES guests. Userspace can just | |
8751 | * use kvm_run->ready_for_interrupt_injection. | |
8752 | */ | |
8753 | kvm_run->if_flag = !vcpu->arch.guest_state_protected | |
8754 | && (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; | |
8755 | ||
2d3ad1f4 | 8756 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 8757 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
127a457a MG |
8758 | kvm_run->ready_for_interrupt_injection = |
8759 | pic_in_kernel(vcpu->kvm) || | |
782d422b | 8760 | kvm_vcpu_ready_for_interrupt_injection(vcpu); |
15aad3be CQ |
8761 | |
8762 | if (is_smm(vcpu)) | |
8763 | kvm_run->flags |= KVM_RUN_X86_SMM; | |
b6c7a5dc HB |
8764 | } |
8765 | ||
95ba8273 GN |
8766 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
8767 | { | |
8768 | int max_irr, tpr; | |
8769 | ||
afaf0b2f | 8770 | if (!kvm_x86_ops.update_cr8_intercept) |
95ba8273 GN |
8771 | return; |
8772 | ||
bce87cce | 8773 | if (!lapic_in_kernel(vcpu)) |
88c808fd AK |
8774 | return; |
8775 | ||
d62caabb AS |
8776 | if (vcpu->arch.apicv_active) |
8777 | return; | |
8778 | ||
8db3baa2 GN |
8779 | if (!vcpu->arch.apic->vapic_addr) |
8780 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
8781 | else | |
8782 | max_irr = -1; | |
95ba8273 GN |
8783 | |
8784 | if (max_irr != -1) | |
8785 | max_irr >>= 4; | |
8786 | ||
8787 | tpr = kvm_lapic_get_cr8(vcpu); | |
8788 | ||
b3646477 | 8789 | static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr); |
95ba8273 GN |
8790 | } |
8791 | ||
b97f0745 | 8792 | |
cb6a32c2 SC |
8793 | int kvm_check_nested_events(struct kvm_vcpu *vcpu) |
8794 | { | |
cb6a32c2 SC |
8795 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
8796 | kvm_x86_ops.nested_ops->triple_fault(vcpu); | |
8797 | return 1; | |
8798 | } | |
8799 | ||
8800 | return kvm_x86_ops.nested_ops->check_events(vcpu); | |
8801 | } | |
8802 | ||
b97f0745 ML |
8803 | static void kvm_inject_exception(struct kvm_vcpu *vcpu) |
8804 | { | |
8805 | if (vcpu->arch.exception.error_code && !is_protmode(vcpu)) | |
8806 | vcpu->arch.exception.error_code = false; | |
8807 | static_call(kvm_x86_queue_exception)(vcpu); | |
8808 | } | |
8809 | ||
a5f6909a | 8810 | static int inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit) |
95ba8273 | 8811 | { |
b6b8a145 | 8812 | int r; |
c6b22f59 | 8813 | bool can_inject = true; |
b6b8a145 | 8814 | |
95ba8273 | 8815 | /* try to reinject previous events if any */ |
664f8e26 | 8816 | |
c6b22f59 | 8817 | if (vcpu->arch.exception.injected) { |
b97f0745 | 8818 | kvm_inject_exception(vcpu); |
c6b22f59 PB |
8819 | can_inject = false; |
8820 | } | |
664f8e26 | 8821 | /* |
a042c26f LA |
8822 | * Do not inject an NMI or interrupt if there is a pending |
8823 | * exception. Exceptions and interrupts are recognized at | |
8824 | * instruction boundaries, i.e. the start of an instruction. | |
8825 | * Trap-like exceptions, e.g. #DB, have higher priority than | |
8826 | * NMIs and interrupts, i.e. traps are recognized before an | |
8827 | * NMI/interrupt that's pending on the same instruction. | |
8828 | * Fault-like exceptions, e.g. #GP and #PF, are the lowest | |
8829 | * priority, but are only generated (pended) during instruction | |
8830 | * execution, i.e. a pending fault-like exception means the | |
8831 | * fault occurred on the *previous* instruction and must be | |
8832 | * serviced prior to recognizing any new events in order to | |
8833 | * fully complete the previous instruction. | |
664f8e26 | 8834 | */ |
1a680e35 | 8835 | else if (!vcpu->arch.exception.pending) { |
c6b22f59 | 8836 | if (vcpu->arch.nmi_injected) { |
b3646477 | 8837 | static_call(kvm_x86_set_nmi)(vcpu); |
c6b22f59 PB |
8838 | can_inject = false; |
8839 | } else if (vcpu->arch.interrupt.injected) { | |
b3646477 | 8840 | static_call(kvm_x86_set_irq)(vcpu); |
c6b22f59 PB |
8841 | can_inject = false; |
8842 | } | |
664f8e26 WL |
8843 | } |
8844 | ||
3b82b8d7 SC |
8845 | WARN_ON_ONCE(vcpu->arch.exception.injected && |
8846 | vcpu->arch.exception.pending); | |
8847 | ||
1a680e35 LA |
8848 | /* |
8849 | * Call check_nested_events() even if we reinjected a previous event | |
8850 | * in order for caller to determine if it should require immediate-exit | |
8851 | * from L2 to L1 due to pending L1 events which require exit | |
8852 | * from L2 to L1. | |
8853 | */ | |
56083bdf | 8854 | if (is_guest_mode(vcpu)) { |
cb6a32c2 | 8855 | r = kvm_check_nested_events(vcpu); |
c9d40913 | 8856 | if (r < 0) |
a5f6909a | 8857 | goto out; |
664f8e26 WL |
8858 | } |
8859 | ||
8860 | /* try to inject new event if pending */ | |
b59bb7bd | 8861 | if (vcpu->arch.exception.pending) { |
5c1c85d0 AK |
8862 | trace_kvm_inj_exception(vcpu->arch.exception.nr, |
8863 | vcpu->arch.exception.has_error_code, | |
8864 | vcpu->arch.exception.error_code); | |
d6e8c854 | 8865 | |
664f8e26 WL |
8866 | vcpu->arch.exception.pending = false; |
8867 | vcpu->arch.exception.injected = true; | |
8868 | ||
d6e8c854 NA |
8869 | if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) |
8870 | __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | | |
8871 | X86_EFLAGS_RF); | |
8872 | ||
f10c729f | 8873 | if (vcpu->arch.exception.nr == DB_VECTOR) { |
f10c729f JM |
8874 | kvm_deliver_exception_payload(vcpu); |
8875 | if (vcpu->arch.dr7 & DR7_GD) { | |
8876 | vcpu->arch.dr7 &= ~DR7_GD; | |
8877 | kvm_update_dr7(vcpu); | |
8878 | } | |
6bdf0662 NA |
8879 | } |
8880 | ||
b97f0745 | 8881 | kvm_inject_exception(vcpu); |
c6b22f59 | 8882 | can_inject = false; |
1a680e35 LA |
8883 | } |
8884 | ||
c9d40913 PB |
8885 | /* |
8886 | * Finally, inject interrupt events. If an event cannot be injected | |
8887 | * due to architectural conditions (e.g. IF=0) a window-open exit | |
8888 | * will re-request KVM_REQ_EVENT. Sometimes however an event is pending | |
8889 | * and can architecturally be injected, but we cannot do it right now: | |
8890 | * an interrupt could have arrived just now and we have to inject it | |
8891 | * as a vmexit, or there could already an event in the queue, which is | |
8892 | * indicated by can_inject. In that case we request an immediate exit | |
8893 | * in order to make progress and get back here for another iteration. | |
8894 | * The kvm_x86_ops hooks communicate this by returning -EBUSY. | |
8895 | */ | |
8896 | if (vcpu->arch.smi_pending) { | |
b3646477 | 8897 | r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY; |
c9d40913 | 8898 | if (r < 0) |
a5f6909a | 8899 | goto out; |
c9d40913 PB |
8900 | if (r) { |
8901 | vcpu->arch.smi_pending = false; | |
8902 | ++vcpu->arch.smi_count; | |
8903 | enter_smm(vcpu); | |
8904 | can_inject = false; | |
8905 | } else | |
b3646477 | 8906 | static_call(kvm_x86_enable_smi_window)(vcpu); |
c9d40913 PB |
8907 | } |
8908 | ||
8909 | if (vcpu->arch.nmi_pending) { | |
b3646477 | 8910 | r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY; |
c9d40913 | 8911 | if (r < 0) |
a5f6909a | 8912 | goto out; |
c9d40913 PB |
8913 | if (r) { |
8914 | --vcpu->arch.nmi_pending; | |
8915 | vcpu->arch.nmi_injected = true; | |
b3646477 | 8916 | static_call(kvm_x86_set_nmi)(vcpu); |
c9d40913 | 8917 | can_inject = false; |
b3646477 | 8918 | WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0); |
c9d40913 PB |
8919 | } |
8920 | if (vcpu->arch.nmi_pending) | |
b3646477 | 8921 | static_call(kvm_x86_enable_nmi_window)(vcpu); |
c9d40913 | 8922 | } |
1a680e35 | 8923 | |
c9d40913 | 8924 | if (kvm_cpu_has_injectable_intr(vcpu)) { |
b3646477 | 8925 | r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY; |
c9d40913 | 8926 | if (r < 0) |
a5f6909a | 8927 | goto out; |
c9d40913 PB |
8928 | if (r) { |
8929 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false); | |
b3646477 JB |
8930 | static_call(kvm_x86_set_irq)(vcpu); |
8931 | WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0); | |
c9d40913 PB |
8932 | } |
8933 | if (kvm_cpu_has_injectable_intr(vcpu)) | |
b3646477 | 8934 | static_call(kvm_x86_enable_irq_window)(vcpu); |
95ba8273 | 8935 | } |
ee2cd4b7 | 8936 | |
c9d40913 PB |
8937 | if (is_guest_mode(vcpu) && |
8938 | kvm_x86_ops.nested_ops->hv_timer_pending && | |
8939 | kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) | |
8940 | *req_immediate_exit = true; | |
8941 | ||
8942 | WARN_ON(vcpu->arch.exception.pending); | |
a5f6909a | 8943 | return 0; |
c9d40913 | 8944 | |
a5f6909a JM |
8945 | out: |
8946 | if (r == -EBUSY) { | |
8947 | *req_immediate_exit = true; | |
8948 | r = 0; | |
8949 | } | |
8950 | return r; | |
95ba8273 GN |
8951 | } |
8952 | ||
7460fb4a AK |
8953 | static void process_nmi(struct kvm_vcpu *vcpu) |
8954 | { | |
8955 | unsigned limit = 2; | |
8956 | ||
8957 | /* | |
8958 | * x86 is limited to one NMI running, and one NMI pending after it. | |
8959 | * If an NMI is already in progress, limit further NMIs to just one. | |
8960 | * Otherwise, allow two (and we'll inject the first one immediately). | |
8961 | */ | |
b3646477 | 8962 | if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected) |
7460fb4a AK |
8963 | limit = 1; |
8964 | ||
8965 | vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); | |
8966 | vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); | |
8967 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
8968 | } | |
8969 | ||
ee2cd4b7 | 8970 | static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) |
660a5d51 PB |
8971 | { |
8972 | u32 flags = 0; | |
8973 | flags |= seg->g << 23; | |
8974 | flags |= seg->db << 22; | |
8975 | flags |= seg->l << 21; | |
8976 | flags |= seg->avl << 20; | |
8977 | flags |= seg->present << 15; | |
8978 | flags |= seg->dpl << 13; | |
8979 | flags |= seg->s << 12; | |
8980 | flags |= seg->type << 8; | |
8981 | return flags; | |
8982 | } | |
8983 | ||
ee2cd4b7 | 8984 | static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) |
660a5d51 PB |
8985 | { |
8986 | struct kvm_segment seg; | |
8987 | int offset; | |
8988 | ||
8989 | kvm_get_segment(vcpu, &seg, n); | |
8990 | put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); | |
8991 | ||
8992 | if (n < 3) | |
8993 | offset = 0x7f84 + n * 12; | |
8994 | else | |
8995 | offset = 0x7f2c + (n - 3) * 12; | |
8996 | ||
8997 | put_smstate(u32, buf, offset + 8, seg.base); | |
8998 | put_smstate(u32, buf, offset + 4, seg.limit); | |
ee2cd4b7 | 8999 | put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
9000 | } |
9001 | ||
efbb288a | 9002 | #ifdef CONFIG_X86_64 |
ee2cd4b7 | 9003 | static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) |
660a5d51 PB |
9004 | { |
9005 | struct kvm_segment seg; | |
9006 | int offset; | |
9007 | u16 flags; | |
9008 | ||
9009 | kvm_get_segment(vcpu, &seg, n); | |
9010 | offset = 0x7e00 + n * 16; | |
9011 | ||
ee2cd4b7 | 9012 | flags = enter_smm_get_segment_flags(&seg) >> 8; |
660a5d51 PB |
9013 | put_smstate(u16, buf, offset, seg.selector); |
9014 | put_smstate(u16, buf, offset + 2, flags); | |
9015 | put_smstate(u32, buf, offset + 4, seg.limit); | |
9016 | put_smstate(u64, buf, offset + 8, seg.base); | |
9017 | } | |
efbb288a | 9018 | #endif |
660a5d51 | 9019 | |
ee2cd4b7 | 9020 | static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) |
660a5d51 PB |
9021 | { |
9022 | struct desc_ptr dt; | |
9023 | struct kvm_segment seg; | |
9024 | unsigned long val; | |
9025 | int i; | |
9026 | ||
9027 | put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); | |
9028 | put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); | |
9029 | put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); | |
9030 | put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); | |
9031 | ||
9032 | for (i = 0; i < 8; i++) | |
27b4a9c4 | 9033 | put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read_raw(vcpu, i)); |
660a5d51 PB |
9034 | |
9035 | kvm_get_dr(vcpu, 6, &val); | |
9036 | put_smstate(u32, buf, 0x7fcc, (u32)val); | |
9037 | kvm_get_dr(vcpu, 7, &val); | |
9038 | put_smstate(u32, buf, 0x7fc8, (u32)val); | |
9039 | ||
9040 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
9041 | put_smstate(u32, buf, 0x7fc4, seg.selector); | |
9042 | put_smstate(u32, buf, 0x7f64, seg.base); | |
9043 | put_smstate(u32, buf, 0x7f60, seg.limit); | |
ee2cd4b7 | 9044 | put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
9045 | |
9046 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
9047 | put_smstate(u32, buf, 0x7fc0, seg.selector); | |
9048 | put_smstate(u32, buf, 0x7f80, seg.base); | |
9049 | put_smstate(u32, buf, 0x7f7c, seg.limit); | |
ee2cd4b7 | 9050 | put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); |
660a5d51 | 9051 | |
b3646477 | 9052 | static_call(kvm_x86_get_gdt)(vcpu, &dt); |
660a5d51 PB |
9053 | put_smstate(u32, buf, 0x7f74, dt.address); |
9054 | put_smstate(u32, buf, 0x7f70, dt.size); | |
9055 | ||
b3646477 | 9056 | static_call(kvm_x86_get_idt)(vcpu, &dt); |
660a5d51 PB |
9057 | put_smstate(u32, buf, 0x7f58, dt.address); |
9058 | put_smstate(u32, buf, 0x7f54, dt.size); | |
9059 | ||
9060 | for (i = 0; i < 6; i++) | |
ee2cd4b7 | 9061 | enter_smm_save_seg_32(vcpu, buf, i); |
660a5d51 PB |
9062 | |
9063 | put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); | |
9064 | ||
9065 | /* revision id */ | |
9066 | put_smstate(u32, buf, 0x7efc, 0x00020000); | |
9067 | put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); | |
9068 | } | |
9069 | ||
b68f3cc7 | 9070 | #ifdef CONFIG_X86_64 |
ee2cd4b7 | 9071 | static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) |
660a5d51 | 9072 | { |
660a5d51 PB |
9073 | struct desc_ptr dt; |
9074 | struct kvm_segment seg; | |
9075 | unsigned long val; | |
9076 | int i; | |
9077 | ||
9078 | for (i = 0; i < 16; i++) | |
27b4a9c4 | 9079 | put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read_raw(vcpu, i)); |
660a5d51 PB |
9080 | |
9081 | put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); | |
9082 | put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); | |
9083 | ||
9084 | kvm_get_dr(vcpu, 6, &val); | |
9085 | put_smstate(u64, buf, 0x7f68, val); | |
9086 | kvm_get_dr(vcpu, 7, &val); | |
9087 | put_smstate(u64, buf, 0x7f60, val); | |
9088 | ||
9089 | put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); | |
9090 | put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); | |
9091 | put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); | |
9092 | ||
9093 | put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); | |
9094 | ||
9095 | /* revision id */ | |
9096 | put_smstate(u32, buf, 0x7efc, 0x00020064); | |
9097 | ||
9098 | put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); | |
9099 | ||
9100 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
9101 | put_smstate(u16, buf, 0x7e90, seg.selector); | |
ee2cd4b7 | 9102 | put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); |
660a5d51 PB |
9103 | put_smstate(u32, buf, 0x7e94, seg.limit); |
9104 | put_smstate(u64, buf, 0x7e98, seg.base); | |
9105 | ||
b3646477 | 9106 | static_call(kvm_x86_get_idt)(vcpu, &dt); |
660a5d51 PB |
9107 | put_smstate(u32, buf, 0x7e84, dt.size); |
9108 | put_smstate(u64, buf, 0x7e88, dt.address); | |
9109 | ||
9110 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
9111 | put_smstate(u16, buf, 0x7e70, seg.selector); | |
ee2cd4b7 | 9112 | put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); |
660a5d51 PB |
9113 | put_smstate(u32, buf, 0x7e74, seg.limit); |
9114 | put_smstate(u64, buf, 0x7e78, seg.base); | |
9115 | ||
b3646477 | 9116 | static_call(kvm_x86_get_gdt)(vcpu, &dt); |
660a5d51 PB |
9117 | put_smstate(u32, buf, 0x7e64, dt.size); |
9118 | put_smstate(u64, buf, 0x7e68, dt.address); | |
9119 | ||
9120 | for (i = 0; i < 6; i++) | |
ee2cd4b7 | 9121 | enter_smm_save_seg_64(vcpu, buf, i); |
660a5d51 | 9122 | } |
b68f3cc7 | 9123 | #endif |
660a5d51 | 9124 | |
ee2cd4b7 | 9125 | static void enter_smm(struct kvm_vcpu *vcpu) |
64d60670 | 9126 | { |
660a5d51 | 9127 | struct kvm_segment cs, ds; |
18c3626e | 9128 | struct desc_ptr dt; |
dbc4739b | 9129 | unsigned long cr0; |
660a5d51 | 9130 | char buf[512]; |
660a5d51 | 9131 | |
660a5d51 | 9132 | memset(buf, 0, 512); |
b68f3cc7 | 9133 | #ifdef CONFIG_X86_64 |
d6321d49 | 9134 | if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) |
ee2cd4b7 | 9135 | enter_smm_save_state_64(vcpu, buf); |
660a5d51 | 9136 | else |
b68f3cc7 | 9137 | #endif |
ee2cd4b7 | 9138 | enter_smm_save_state_32(vcpu, buf); |
660a5d51 | 9139 | |
0234bf88 | 9140 | /* |
ecc513e5 SC |
9141 | * Give enter_smm() a chance to make ISA-specific changes to the vCPU |
9142 | * state (e.g. leave guest mode) after we've saved the state into the | |
9143 | * SMM state-save area. | |
0234bf88 | 9144 | */ |
ecc513e5 | 9145 | static_call(kvm_x86_enter_smm)(vcpu, buf); |
0234bf88 | 9146 | |
dc87275f | 9147 | kvm_smm_changed(vcpu, true); |
54bf36aa | 9148 | kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); |
660a5d51 | 9149 | |
b3646477 | 9150 | if (static_call(kvm_x86_get_nmi_mask)(vcpu)) |
660a5d51 PB |
9151 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; |
9152 | else | |
b3646477 | 9153 | static_call(kvm_x86_set_nmi_mask)(vcpu, true); |
660a5d51 PB |
9154 | |
9155 | kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); | |
9156 | kvm_rip_write(vcpu, 0x8000); | |
9157 | ||
9158 | cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); | |
b3646477 | 9159 | static_call(kvm_x86_set_cr0)(vcpu, cr0); |
660a5d51 PB |
9160 | vcpu->arch.cr0 = cr0; |
9161 | ||
b3646477 | 9162 | static_call(kvm_x86_set_cr4)(vcpu, 0); |
660a5d51 | 9163 | |
18c3626e PB |
9164 | /* Undocumented: IDT limit is set to zero on entry to SMM. */ |
9165 | dt.address = dt.size = 0; | |
b3646477 | 9166 | static_call(kvm_x86_set_idt)(vcpu, &dt); |
18c3626e | 9167 | |
996ff542 | 9168 | kvm_set_dr(vcpu, 7, DR7_FIXED_1); |
660a5d51 PB |
9169 | |
9170 | cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; | |
9171 | cs.base = vcpu->arch.smbase; | |
9172 | ||
9173 | ds.selector = 0; | |
9174 | ds.base = 0; | |
9175 | ||
9176 | cs.limit = ds.limit = 0xffffffff; | |
9177 | cs.type = ds.type = 0x3; | |
9178 | cs.dpl = ds.dpl = 0; | |
9179 | cs.db = ds.db = 0; | |
9180 | cs.s = ds.s = 1; | |
9181 | cs.l = ds.l = 0; | |
9182 | cs.g = ds.g = 1; | |
9183 | cs.avl = ds.avl = 0; | |
9184 | cs.present = ds.present = 1; | |
9185 | cs.unusable = ds.unusable = 0; | |
9186 | cs.padding = ds.padding = 0; | |
9187 | ||
9188 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
9189 | kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); | |
9190 | kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); | |
9191 | kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); | |
9192 | kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); | |
9193 | kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); | |
9194 | ||
b68f3cc7 | 9195 | #ifdef CONFIG_X86_64 |
d6321d49 | 9196 | if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) |
b3646477 | 9197 | static_call(kvm_x86_set_efer)(vcpu, 0); |
b68f3cc7 | 9198 | #endif |
660a5d51 | 9199 | |
aedbaf4f | 9200 | kvm_update_cpuid_runtime(vcpu); |
660a5d51 | 9201 | kvm_mmu_reset_context(vcpu); |
64d60670 PB |
9202 | } |
9203 | ||
ee2cd4b7 | 9204 | static void process_smi(struct kvm_vcpu *vcpu) |
c43203ca PB |
9205 | { |
9206 | vcpu->arch.smi_pending = true; | |
9207 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
9208 | } | |
9209 | ||
7ee30bc1 NNL |
9210 | void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, |
9211 | unsigned long *vcpu_bitmap) | |
9212 | { | |
9213 | cpumask_var_t cpus; | |
7ee30bc1 NNL |
9214 | |
9215 | zalloc_cpumask_var(&cpus, GFP_ATOMIC); | |
9216 | ||
db5a95ec | 9217 | kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, |
54163a34 | 9218 | NULL, vcpu_bitmap, cpus); |
7ee30bc1 NNL |
9219 | |
9220 | free_cpumask_var(cpus); | |
9221 | } | |
9222 | ||
2860c4b1 PB |
9223 | void kvm_make_scan_ioapic_request(struct kvm *kvm) |
9224 | { | |
9225 | kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); | |
9226 | } | |
9227 | ||
8df14af4 SS |
9228 | void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) |
9229 | { | |
9230 | if (!lapic_in_kernel(vcpu)) | |
9231 | return; | |
9232 | ||
9233 | vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm); | |
9234 | kvm_apic_update_apicv(vcpu); | |
b3646477 | 9235 | static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu); |
bca66dbc VK |
9236 | |
9237 | /* | |
9238 | * When APICv gets disabled, we may still have injected interrupts | |
9239 | * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was | |
9240 | * still active when the interrupt got accepted. Make sure | |
9241 | * inject_pending_event() is called to check for that. | |
9242 | */ | |
9243 | if (!vcpu->arch.apicv_active) | |
9244 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
8df14af4 SS |
9245 | } |
9246 | EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv); | |
9247 | ||
9248 | /* | |
9249 | * NOTE: Do not hold any lock prior to calling this. | |
9250 | * | |
9251 | * In particular, kvm_request_apicv_update() expects kvm->srcu not to be | |
9252 | * locked, because it calls __x86_set_memory_region() which does | |
9253 | * synchronize_srcu(&kvm->srcu). | |
9254 | */ | |
9255 | void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit) | |
9256 | { | |
7d611233 | 9257 | struct kvm_vcpu *except; |
8e205a6b PB |
9258 | unsigned long old, new, expected; |
9259 | ||
afaf0b2f | 9260 | if (!kvm_x86_ops.check_apicv_inhibit_reasons || |
b3646477 | 9261 | !static_call(kvm_x86_check_apicv_inhibit_reasons)(bit)) |
ef8efd7a SS |
9262 | return; |
9263 | ||
8e205a6b PB |
9264 | old = READ_ONCE(kvm->arch.apicv_inhibit_reasons); |
9265 | do { | |
9266 | expected = new = old; | |
9267 | if (activate) | |
9268 | __clear_bit(bit, &new); | |
9269 | else | |
9270 | __set_bit(bit, &new); | |
9271 | if (new == old) | |
9272 | break; | |
9273 | old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new); | |
9274 | } while (old != expected); | |
9275 | ||
9276 | if (!!old == !!new) | |
9277 | return; | |
8df14af4 | 9278 | |
24bbf74c | 9279 | trace_kvm_apicv_update_request(activate, bit); |
afaf0b2f | 9280 | if (kvm_x86_ops.pre_update_apicv_exec_ctrl) |
b3646477 | 9281 | static_call(kvm_x86_pre_update_apicv_exec_ctrl)(kvm, activate); |
7d611233 SS |
9282 | |
9283 | /* | |
9284 | * Sending request to update APICV for all other vcpus, | |
9285 | * while update the calling vcpu immediately instead of | |
9286 | * waiting for another #VMEXIT to handle the request. | |
9287 | */ | |
9288 | except = kvm_get_running_vcpu(); | |
9289 | kvm_make_all_cpus_request_except(kvm, KVM_REQ_APICV_UPDATE, | |
9290 | except); | |
9291 | if (except) | |
9292 | kvm_vcpu_update_apicv(except); | |
8df14af4 SS |
9293 | } |
9294 | EXPORT_SYMBOL_GPL(kvm_request_apicv_update); | |
9295 | ||
3d81bc7e | 9296 | static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) |
c7c9c56c | 9297 | { |
dcbd3e49 | 9298 | if (!kvm_apic_present(vcpu)) |
3d81bc7e | 9299 | return; |
c7c9c56c | 9300 | |
6308630b | 9301 | bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); |
c7c9c56c | 9302 | |
b053b2ae | 9303 | if (irqchip_split(vcpu->kvm)) |
6308630b | 9304 | kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); |
db2bdcbb | 9305 | else { |
fa59cc00 | 9306 | if (vcpu->arch.apicv_active) |
b3646477 | 9307 | static_call(kvm_x86_sync_pir_to_irr)(vcpu); |
e97f852f WL |
9308 | if (ioapic_in_kernel(vcpu->kvm)) |
9309 | kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); | |
db2bdcbb | 9310 | } |
e40ff1d6 LA |
9311 | |
9312 | if (is_guest_mode(vcpu)) | |
9313 | vcpu->arch.load_eoi_exitmap_pending = true; | |
9314 | else | |
9315 | kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); | |
9316 | } | |
9317 | ||
9318 | static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) | |
9319 | { | |
9320 | u64 eoi_exit_bitmap[4]; | |
9321 | ||
9322 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) | |
9323 | return; | |
9324 | ||
f2bc14b6 VK |
9325 | if (to_hv_vcpu(vcpu)) |
9326 | bitmap_or((ulong *)eoi_exit_bitmap, | |
9327 | vcpu->arch.ioapic_handled_vectors, | |
9328 | to_hv_synic(vcpu)->vec_bitmap, 256); | |
9329 | ||
b3646477 | 9330 | static_call(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap); |
c7c9c56c YZ |
9331 | } |
9332 | ||
e649b3f0 ET |
9333 | void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, |
9334 | unsigned long start, unsigned long end) | |
b1394e74 RK |
9335 | { |
9336 | unsigned long apic_address; | |
9337 | ||
9338 | /* | |
9339 | * The physical address of apic access page is stored in the VMCS. | |
9340 | * Update it when it becomes invalid. | |
9341 | */ | |
9342 | apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); | |
9343 | if (start <= apic_address && apic_address < end) | |
9344 | kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); | |
9345 | } | |
9346 | ||
4256f43f TC |
9347 | void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) |
9348 | { | |
35754c98 | 9349 | if (!lapic_in_kernel(vcpu)) |
f439ed27 PB |
9350 | return; |
9351 | ||
afaf0b2f | 9352 | if (!kvm_x86_ops.set_apic_access_page_addr) |
4256f43f TC |
9353 | return; |
9354 | ||
b3646477 | 9355 | static_call(kvm_x86_set_apic_access_page_addr)(vcpu); |
4256f43f | 9356 | } |
4256f43f | 9357 | |
d264ee0c SC |
9358 | void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) |
9359 | { | |
9360 | smp_send_reschedule(vcpu->cpu); | |
9361 | } | |
9362 | EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); | |
9363 | ||
9357d939 | 9364 | /* |
362c698f | 9365 | * Returns 1 to let vcpu_run() continue the guest execution loop without |
9357d939 TY |
9366 | * exiting to the userspace. Otherwise, the value will be returned to the |
9367 | * userspace. | |
9368 | */ | |
851ba692 | 9369 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
9370 | { |
9371 | int r; | |
62a193ed MG |
9372 | bool req_int_win = |
9373 | dm_request_for_irq_injection(vcpu) && | |
9374 | kvm_cpu_accept_dm_intr(vcpu); | |
404d5d7b | 9375 | fastpath_t exit_fastpath; |
62a193ed | 9376 | |
730dca42 | 9377 | bool req_immediate_exit = false; |
b6c7a5dc | 9378 | |
fb04a1ed PX |
9379 | /* Forbid vmenter if vcpu dirty ring is soft-full */ |
9380 | if (unlikely(vcpu->kvm->dirty_ring_size && | |
9381 | kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) { | |
9382 | vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL; | |
9383 | trace_kvm_dirty_ring_exit(vcpu); | |
9384 | r = 0; | |
9385 | goto out; | |
9386 | } | |
9387 | ||
2fa6e1e1 | 9388 | if (kvm_request_pending(vcpu)) { |
729c15c2 | 9389 | if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) { |
9a78e158 | 9390 | if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) { |
671ddc70 JM |
9391 | r = 0; |
9392 | goto out; | |
9393 | } | |
9394 | } | |
a8eeb04a | 9395 | if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) |
2e53d63a | 9396 | kvm_mmu_unload(vcpu); |
a8eeb04a | 9397 | if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) |
2f599714 | 9398 | __kvm_migrate_timers(vcpu); |
d828199e MT |
9399 | if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) |
9400 | kvm_gen_update_masterclock(vcpu->kvm); | |
0061d53d MT |
9401 | if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) |
9402 | kvm_gen_kvmclock_update(vcpu); | |
34c238a1 ZA |
9403 | if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { |
9404 | r = kvm_guest_time_update(vcpu); | |
8cfdc000 ZA |
9405 | if (unlikely(r)) |
9406 | goto out; | |
9407 | } | |
a8eeb04a | 9408 | if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) |
4731d4c7 | 9409 | kvm_mmu_sync_roots(vcpu); |
727a7e27 PB |
9410 | if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu)) |
9411 | kvm_mmu_load_pgd(vcpu); | |
eeeb4f67 | 9412 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) { |
7780938c | 9413 | kvm_vcpu_flush_tlb_all(vcpu); |
eeeb4f67 SC |
9414 | |
9415 | /* Flushing all ASIDs flushes the current ASID... */ | |
9416 | kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); | |
9417 | } | |
9418 | if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu)) | |
9419 | kvm_vcpu_flush_tlb_current(vcpu); | |
07ffaf34 | 9420 | if (kvm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu)) |
0baedd79 | 9421 | kvm_vcpu_flush_tlb_guest(vcpu); |
eeeb4f67 | 9422 | |
a8eeb04a | 9423 | if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { |
851ba692 | 9424 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
9425 | r = 0; |
9426 | goto out; | |
9427 | } | |
a8eeb04a | 9428 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
cb6a32c2 SC |
9429 | if (is_guest_mode(vcpu)) { |
9430 | kvm_x86_ops.nested_ops->triple_fault(vcpu); | |
9431 | } else { | |
9432 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; | |
9433 | vcpu->mmio_needed = 0; | |
9434 | r = 0; | |
9435 | goto out; | |
9436 | } | |
71c4dfaf | 9437 | } |
af585b92 GN |
9438 | if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { |
9439 | /* Page is swapped out. Do synthetic halt */ | |
9440 | vcpu->arch.apf.halted = true; | |
9441 | r = 1; | |
9442 | goto out; | |
9443 | } | |
c9aaa895 GC |
9444 | if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) |
9445 | record_steal_time(vcpu); | |
64d60670 PB |
9446 | if (kvm_check_request(KVM_REQ_SMI, vcpu)) |
9447 | process_smi(vcpu); | |
7460fb4a AK |
9448 | if (kvm_check_request(KVM_REQ_NMI, vcpu)) |
9449 | process_nmi(vcpu); | |
f5132b01 | 9450 | if (kvm_check_request(KVM_REQ_PMU, vcpu)) |
c6702c9d | 9451 | kvm_pmu_handle_event(vcpu); |
f5132b01 | 9452 | if (kvm_check_request(KVM_REQ_PMI, vcpu)) |
c6702c9d | 9453 | kvm_pmu_deliver_pmi(vcpu); |
7543a635 SR |
9454 | if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { |
9455 | BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); | |
9456 | if (test_bit(vcpu->arch.pending_ioapic_eoi, | |
6308630b | 9457 | vcpu->arch.ioapic_handled_vectors)) { |
7543a635 SR |
9458 | vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; |
9459 | vcpu->run->eoi.vector = | |
9460 | vcpu->arch.pending_ioapic_eoi; | |
9461 | r = 0; | |
9462 | goto out; | |
9463 | } | |
9464 | } | |
3d81bc7e YZ |
9465 | if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) |
9466 | vcpu_scan_ioapic(vcpu); | |
e40ff1d6 LA |
9467 | if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) |
9468 | vcpu_load_eoi_exitmap(vcpu); | |
4256f43f TC |
9469 | if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) |
9470 | kvm_vcpu_reload_apic_access_page(vcpu); | |
2ce79189 AS |
9471 | if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { |
9472 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
9473 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; | |
9474 | r = 0; | |
9475 | goto out; | |
9476 | } | |
e516cebb AS |
9477 | if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { |
9478 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
9479 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; | |
9480 | r = 0; | |
9481 | goto out; | |
9482 | } | |
db397571 | 9483 | if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { |
9ff5e030 VK |
9484 | struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu); |
9485 | ||
db397571 | 9486 | vcpu->run->exit_reason = KVM_EXIT_HYPERV; |
9ff5e030 | 9487 | vcpu->run->hyperv = hv_vcpu->exit; |
db397571 AS |
9488 | r = 0; |
9489 | goto out; | |
9490 | } | |
f3b138c5 AS |
9491 | |
9492 | /* | |
9493 | * KVM_REQ_HV_STIMER has to be processed after | |
9494 | * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers | |
9495 | * depend on the guest clock being up-to-date | |
9496 | */ | |
1f4b34f8 AS |
9497 | if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) |
9498 | kvm_hv_process_stimers(vcpu); | |
8df14af4 SS |
9499 | if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) |
9500 | kvm_vcpu_update_apicv(vcpu); | |
557a961a VK |
9501 | if (kvm_check_request(KVM_REQ_APF_READY, vcpu)) |
9502 | kvm_check_async_pf_completion(vcpu); | |
1a155254 | 9503 | if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu)) |
b3646477 | 9504 | static_call(kvm_x86_msr_filter_changed)(vcpu); |
a85863c2 MS |
9505 | |
9506 | if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu)) | |
9507 | static_call(kvm_x86_update_cpu_dirty_logging)(vcpu); | |
2f52d58c | 9508 | } |
b93463aa | 9509 | |
40da8ccd DW |
9510 | if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win || |
9511 | kvm_xen_has_interrupt(vcpu)) { | |
0f1e261e | 9512 | ++vcpu->stat.req_event; |
4fe09bcf JM |
9513 | r = kvm_apic_accept_events(vcpu); |
9514 | if (r < 0) { | |
9515 | r = 0; | |
9516 | goto out; | |
9517 | } | |
66450a21 JK |
9518 | if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { |
9519 | r = 1; | |
9520 | goto out; | |
9521 | } | |
9522 | ||
a5f6909a JM |
9523 | r = inject_pending_event(vcpu, &req_immediate_exit); |
9524 | if (r < 0) { | |
9525 | r = 0; | |
9526 | goto out; | |
9527 | } | |
c9d40913 | 9528 | if (req_int_win) |
b3646477 | 9529 | static_call(kvm_x86_enable_irq_window)(vcpu); |
b463a6f7 AK |
9530 | |
9531 | if (kvm_lapic_enabled(vcpu)) { | |
9532 | update_cr8_intercept(vcpu); | |
9533 | kvm_lapic_sync_to_vapic(vcpu); | |
9534 | } | |
9535 | } | |
9536 | ||
d8368af8 AK |
9537 | r = kvm_mmu_reload(vcpu); |
9538 | if (unlikely(r)) { | |
d905c069 | 9539 | goto cancel_injection; |
d8368af8 AK |
9540 | } |
9541 | ||
b6c7a5dc HB |
9542 | preempt_disable(); |
9543 | ||
b3646477 | 9544 | static_call(kvm_x86_prepare_guest_switch)(vcpu); |
b95234c8 PB |
9545 | |
9546 | /* | |
9547 | * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt | |
9548 | * IPI are then delayed after guest entry, which ensures that they | |
9549 | * result in virtual interrupt delivery. | |
9550 | */ | |
9551 | local_irq_disable(); | |
6b7e2d09 XG |
9552 | vcpu->mode = IN_GUEST_MODE; |
9553 | ||
01b71917 MT |
9554 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
9555 | ||
0f127d12 | 9556 | /* |
b95234c8 | 9557 | * 1) We should set ->mode before checking ->requests. Please see |
cde9af6e | 9558 | * the comment in kvm_vcpu_exiting_guest_mode(). |
b95234c8 | 9559 | * |
81b01667 | 9560 | * 2) For APICv, we should set ->mode before checking PID.ON. This |
b95234c8 PB |
9561 | * pairs with the memory barrier implicit in pi_test_and_set_on |
9562 | * (see vmx_deliver_posted_interrupt). | |
9563 | * | |
9564 | * 3) This also orders the write to mode from any reads to the page | |
9565 | * tables done while the VCPU is running. Please see the comment | |
9566 | * in kvm_flush_remote_tlbs. | |
6b7e2d09 | 9567 | */ |
01b71917 | 9568 | smp_mb__after_srcu_read_unlock(); |
b6c7a5dc | 9569 | |
b95234c8 PB |
9570 | /* |
9571 | * This handles the case where a posted interrupt was | |
9572 | * notified with kvm_vcpu_kick. | |
9573 | */ | |
fa59cc00 | 9574 | if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active) |
b3646477 | 9575 | static_call(kvm_x86_sync_pir_to_irr)(vcpu); |
32f88400 | 9576 | |
5a9f5443 | 9577 | if (kvm_vcpu_exit_request(vcpu)) { |
6b7e2d09 | 9578 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 9579 | smp_wmb(); |
6c142801 AK |
9580 | local_irq_enable(); |
9581 | preempt_enable(); | |
01b71917 | 9582 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
6c142801 | 9583 | r = 1; |
d905c069 | 9584 | goto cancel_injection; |
6c142801 AK |
9585 | } |
9586 | ||
c43203ca PB |
9587 | if (req_immediate_exit) { |
9588 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
b3646477 | 9589 | static_call(kvm_x86_request_immediate_exit)(vcpu); |
c43203ca | 9590 | } |
d6185f20 | 9591 | |
2620fe26 SC |
9592 | fpregs_assert_state_consistent(); |
9593 | if (test_thread_flag(TIF_NEED_FPU_LOAD)) | |
9594 | switch_fpu_return(); | |
5f409e20 | 9595 | |
42dbaa5a | 9596 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
9597 | set_debugreg(0, 7); |
9598 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
9599 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
9600 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
9601 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
c77fb5fe | 9602 | set_debugreg(vcpu->arch.dr6, 6); |
ae561ede | 9603 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; |
f85d4016 LJ |
9604 | } else if (unlikely(hw_breakpoint_active())) { |
9605 | set_debugreg(0, 7); | |
42dbaa5a | 9606 | } |
b6c7a5dc | 9607 | |
d89d04ab PB |
9608 | for (;;) { |
9609 | exit_fastpath = static_call(kvm_x86_run)(vcpu); | |
9610 | if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST)) | |
9611 | break; | |
9612 | ||
9613 | if (unlikely(kvm_vcpu_exit_request(vcpu))) { | |
9614 | exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED; | |
9615 | break; | |
9616 | } | |
9617 | ||
9618 | if (vcpu->arch.apicv_active) | |
9619 | static_call(kvm_x86_sync_pir_to_irr)(vcpu); | |
9620 | } | |
b6c7a5dc | 9621 | |
c77fb5fe PB |
9622 | /* |
9623 | * Do this here before restoring debug registers on the host. And | |
9624 | * since we do this before handling the vmexit, a DR access vmexit | |
9625 | * can (a) read the correct value of the debug registers, (b) set | |
9626 | * KVM_DEBUGREG_WONT_EXIT again. | |
9627 | */ | |
9628 | if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { | |
c77fb5fe | 9629 | WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); |
b3646477 | 9630 | static_call(kvm_x86_sync_dirty_debug_regs)(vcpu); |
70e4da7a | 9631 | kvm_update_dr0123(vcpu); |
70e4da7a PB |
9632 | kvm_update_dr7(vcpu); |
9633 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; | |
c77fb5fe PB |
9634 | } |
9635 | ||
24f1e32c FW |
9636 | /* |
9637 | * If the guest has used debug registers, at least dr7 | |
9638 | * will be disabled while returning to the host. | |
9639 | * If we don't have active breakpoints in the host, we don't | |
9640 | * care about the messed up debug address registers. But if | |
9641 | * we have some of them active, restore the old state. | |
9642 | */ | |
59d8eb53 | 9643 | if (hw_breakpoint_active()) |
24f1e32c | 9644 | hw_breakpoint_restore(); |
42dbaa5a | 9645 | |
c967118d | 9646 | vcpu->arch.last_vmentry_cpu = vcpu->cpu; |
4ba76538 | 9647 | vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); |
1d5f066e | 9648 | |
6b7e2d09 | 9649 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 9650 | smp_wmb(); |
a547c6db | 9651 | |
b3646477 | 9652 | static_call(kvm_x86_handle_exit_irqoff)(vcpu); |
b6c7a5dc | 9653 | |
d7a08882 SC |
9654 | /* |
9655 | * Consume any pending interrupts, including the possible source of | |
9656 | * VM-Exit on SVM and any ticks that occur between VM-Exit and now. | |
9657 | * An instruction is required after local_irq_enable() to fully unblock | |
9658 | * interrupts on processors that implement an interrupt shadow, the | |
9659 | * stat.exits increment will do nicely. | |
9660 | */ | |
9661 | kvm_before_interrupt(vcpu); | |
9662 | local_irq_enable(); | |
b6c7a5dc | 9663 | ++vcpu->stat.exits; |
d7a08882 SC |
9664 | local_irq_disable(); |
9665 | kvm_after_interrupt(vcpu); | |
b6c7a5dc | 9666 | |
16045714 WL |
9667 | /* |
9668 | * Wait until after servicing IRQs to account guest time so that any | |
9669 | * ticks that occurred while running the guest are properly accounted | |
9670 | * to the guest. Waiting until IRQs are enabled degrades the accuracy | |
9671 | * of accounting via context tracking, but the loss of accuracy is | |
9672 | * acceptable for all known use cases. | |
9673 | */ | |
9674 | vtime_account_guest_exit(); | |
9675 | ||
ec0671d5 WL |
9676 | if (lapic_in_kernel(vcpu)) { |
9677 | s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta; | |
9678 | if (delta != S64_MIN) { | |
9679 | trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta); | |
9680 | vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN; | |
9681 | } | |
9682 | } | |
b6c7a5dc | 9683 | |
f2485b3e | 9684 | local_irq_enable(); |
b6c7a5dc HB |
9685 | preempt_enable(); |
9686 | ||
f656ce01 | 9687 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
3200f405 | 9688 | |
b6c7a5dc HB |
9689 | /* |
9690 | * Profile KVM exit RIPs: | |
9691 | */ | |
9692 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
9693 | unsigned long rip = kvm_rip_read(vcpu); |
9694 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
9695 | } |
9696 | ||
cc578287 ZA |
9697 | if (unlikely(vcpu->arch.tsc_always_catchup)) |
9698 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
298101da | 9699 | |
5cfb1d5a MT |
9700 | if (vcpu->arch.apic_attention) |
9701 | kvm_lapic_sync_from_vapic(vcpu); | |
b93463aa | 9702 | |
b3646477 | 9703 | r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath); |
d905c069 MT |
9704 | return r; |
9705 | ||
9706 | cancel_injection: | |
8081ad06 SC |
9707 | if (req_immediate_exit) |
9708 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
b3646477 | 9709 | static_call(kvm_x86_cancel_injection)(vcpu); |
ae7a2a3f MT |
9710 | if (unlikely(vcpu->arch.apic_attention)) |
9711 | kvm_lapic_sync_from_vapic(vcpu); | |
d7690175 MT |
9712 | out: |
9713 | return r; | |
9714 | } | |
b6c7a5dc | 9715 | |
362c698f PB |
9716 | static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) |
9717 | { | |
bf9f6ac8 | 9718 | if (!kvm_arch_vcpu_runnable(vcpu) && |
b3646477 | 9719 | (!kvm_x86_ops.pre_block || static_call(kvm_x86_pre_block)(vcpu) == 0)) { |
9c8fd1ba PB |
9720 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
9721 | kvm_vcpu_block(vcpu); | |
9722 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); | |
bf9f6ac8 | 9723 | |
afaf0b2f | 9724 | if (kvm_x86_ops.post_block) |
b3646477 | 9725 | static_call(kvm_x86_post_block)(vcpu); |
bf9f6ac8 | 9726 | |
9c8fd1ba PB |
9727 | if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) |
9728 | return 1; | |
9729 | } | |
362c698f | 9730 | |
4fe09bcf JM |
9731 | if (kvm_apic_accept_events(vcpu) < 0) |
9732 | return 0; | |
362c698f PB |
9733 | switch(vcpu->arch.mp_state) { |
9734 | case KVM_MP_STATE_HALTED: | |
647daca2 | 9735 | case KVM_MP_STATE_AP_RESET_HOLD: |
362c698f PB |
9736 | vcpu->arch.pv.pv_unhalted = false; |
9737 | vcpu->arch.mp_state = | |
9738 | KVM_MP_STATE_RUNNABLE; | |
df561f66 | 9739 | fallthrough; |
362c698f PB |
9740 | case KVM_MP_STATE_RUNNABLE: |
9741 | vcpu->arch.apf.halted = false; | |
9742 | break; | |
9743 | case KVM_MP_STATE_INIT_RECEIVED: | |
9744 | break; | |
9745 | default: | |
9746 | return -EINTR; | |
362c698f PB |
9747 | } |
9748 | return 1; | |
9749 | } | |
09cec754 | 9750 | |
5d9bc648 PB |
9751 | static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) |
9752 | { | |
56083bdf | 9753 | if (is_guest_mode(vcpu)) |
cb6a32c2 | 9754 | kvm_check_nested_events(vcpu); |
0ad3bed6 | 9755 | |
5d9bc648 PB |
9756 | return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
9757 | !vcpu->arch.apf.halted); | |
9758 | } | |
9759 | ||
362c698f | 9760 | static int vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
9761 | { |
9762 | int r; | |
f656ce01 | 9763 | struct kvm *kvm = vcpu->kvm; |
d7690175 | 9764 | |
f656ce01 | 9765 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
c595ceee | 9766 | vcpu->arch.l1tf_flush_l1d = true; |
d7690175 | 9767 | |
362c698f | 9768 | for (;;) { |
58f800d5 | 9769 | if (kvm_vcpu_running(vcpu)) { |
851ba692 | 9770 | r = vcpu_enter_guest(vcpu); |
bf9f6ac8 | 9771 | } else { |
362c698f | 9772 | r = vcpu_block(kvm, vcpu); |
bf9f6ac8 FW |
9773 | } |
9774 | ||
09cec754 GN |
9775 | if (r <= 0) |
9776 | break; | |
9777 | ||
084071d5 | 9778 | kvm_clear_request(KVM_REQ_UNBLOCK, vcpu); |
09cec754 GN |
9779 | if (kvm_cpu_has_pending_timer(vcpu)) |
9780 | kvm_inject_pending_timer_irqs(vcpu); | |
9781 | ||
782d422b MG |
9782 | if (dm_request_for_irq_injection(vcpu) && |
9783 | kvm_vcpu_ready_for_interrupt_injection(vcpu)) { | |
4ca7dd8c PB |
9784 | r = 0; |
9785 | vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; | |
09cec754 | 9786 | ++vcpu->stat.request_irq_exits; |
362c698f | 9787 | break; |
09cec754 | 9788 | } |
af585b92 | 9789 | |
f3020b88 | 9790 | if (__xfer_to_guest_mode_work_pending()) { |
f656ce01 | 9791 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
72c3c0fe TG |
9792 | r = xfer_to_guest_mode_handle_work(vcpu); |
9793 | if (r) | |
9794 | return r; | |
f656ce01 | 9795 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 9796 | } |
b6c7a5dc HB |
9797 | } |
9798 | ||
f656ce01 | 9799 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
b6c7a5dc HB |
9800 | |
9801 | return r; | |
9802 | } | |
9803 | ||
716d51ab GN |
9804 | static inline int complete_emulated_io(struct kvm_vcpu *vcpu) |
9805 | { | |
9806 | int r; | |
60fc3d02 | 9807 | |
716d51ab | 9808 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
0ce97a2b | 9809 | r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); |
716d51ab | 9810 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
60fc3d02 | 9811 | return r; |
716d51ab GN |
9812 | } |
9813 | ||
9814 | static int complete_emulated_pio(struct kvm_vcpu *vcpu) | |
9815 | { | |
9816 | BUG_ON(!vcpu->arch.pio.count); | |
9817 | ||
9818 | return complete_emulated_io(vcpu); | |
9819 | } | |
9820 | ||
f78146b0 AK |
9821 | /* |
9822 | * Implements the following, as a state machine: | |
9823 | * | |
9824 | * read: | |
9825 | * for each fragment | |
87da7e66 XG |
9826 | * for each mmio piece in the fragment |
9827 | * write gpa, len | |
9828 | * exit | |
9829 | * copy data | |
f78146b0 AK |
9830 | * execute insn |
9831 | * | |
9832 | * write: | |
9833 | * for each fragment | |
87da7e66 XG |
9834 | * for each mmio piece in the fragment |
9835 | * write gpa, len | |
9836 | * copy data | |
9837 | * exit | |
f78146b0 | 9838 | */ |
716d51ab | 9839 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu) |
5287f194 AK |
9840 | { |
9841 | struct kvm_run *run = vcpu->run; | |
f78146b0 | 9842 | struct kvm_mmio_fragment *frag; |
87da7e66 | 9843 | unsigned len; |
5287f194 | 9844 | |
716d51ab | 9845 | BUG_ON(!vcpu->mmio_needed); |
5287f194 | 9846 | |
716d51ab | 9847 | /* Complete previous fragment */ |
87da7e66 XG |
9848 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; |
9849 | len = min(8u, frag->len); | |
716d51ab | 9850 | if (!vcpu->mmio_is_write) |
87da7e66 XG |
9851 | memcpy(frag->data, run->mmio.data, len); |
9852 | ||
9853 | if (frag->len <= 8) { | |
9854 | /* Switch to the next fragment. */ | |
9855 | frag++; | |
9856 | vcpu->mmio_cur_fragment++; | |
9857 | } else { | |
9858 | /* Go forward to the next mmio piece. */ | |
9859 | frag->data += len; | |
9860 | frag->gpa += len; | |
9861 | frag->len -= len; | |
9862 | } | |
9863 | ||
a08d3b3b | 9864 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { |
716d51ab | 9865 | vcpu->mmio_needed = 0; |
0912c977 PB |
9866 | |
9867 | /* FIXME: return into emulator if single-stepping. */ | |
cef4dea0 | 9868 | if (vcpu->mmio_is_write) |
716d51ab GN |
9869 | return 1; |
9870 | vcpu->mmio_read_completed = 1; | |
9871 | return complete_emulated_io(vcpu); | |
9872 | } | |
87da7e66 | 9873 | |
716d51ab GN |
9874 | run->exit_reason = KVM_EXIT_MMIO; |
9875 | run->mmio.phys_addr = frag->gpa; | |
9876 | if (vcpu->mmio_is_write) | |
87da7e66 XG |
9877 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); |
9878 | run->mmio.len = min(8u, frag->len); | |
716d51ab GN |
9879 | run->mmio.is_write = vcpu->mmio_is_write; |
9880 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; | |
9881 | return 0; | |
5287f194 AK |
9882 | } |
9883 | ||
c9aef3b8 SC |
9884 | static void kvm_save_current_fpu(struct fpu *fpu) |
9885 | { | |
9886 | /* | |
9887 | * If the target FPU state is not resident in the CPU registers, just | |
9888 | * memcpy() from current, else save CPU state directly to the target. | |
9889 | */ | |
9890 | if (test_thread_flag(TIF_NEED_FPU_LOAD)) | |
9891 | memcpy(&fpu->state, ¤t->thread.fpu.state, | |
9892 | fpu_kernel_xstate_size); | |
9893 | else | |
ebe7234b | 9894 | save_fpregs_to_fpstate(fpu); |
c9aef3b8 SC |
9895 | } |
9896 | ||
822f312d SAS |
9897 | /* Swap (qemu) user FPU context for the guest FPU context. */ |
9898 | static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) | |
9899 | { | |
5f409e20 RR |
9900 | fpregs_lock(); |
9901 | ||
c9aef3b8 SC |
9902 | kvm_save_current_fpu(vcpu->arch.user_fpu); |
9903 | ||
ed02b213 TL |
9904 | /* |
9905 | * Guests with protected state can't have it set by the hypervisor, | |
9906 | * so skip trying to set it. | |
9907 | */ | |
9908 | if (vcpu->arch.guest_fpu) | |
9909 | /* PKRU is separately restored in kvm_x86_ops.run. */ | |
1c61fada | 9910 | __restore_fpregs_from_fpstate(&vcpu->arch.guest_fpu->state, |
ed02b213 | 9911 | ~XFEATURE_MASK_PKRU); |
5f409e20 RR |
9912 | |
9913 | fpregs_mark_activate(); | |
9914 | fpregs_unlock(); | |
9915 | ||
822f312d SAS |
9916 | trace_kvm_fpu(1); |
9917 | } | |
9918 | ||
9919 | /* When vcpu_run ends, restore user space FPU context. */ | |
9920 | static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
9921 | { | |
5f409e20 RR |
9922 | fpregs_lock(); |
9923 | ||
ed02b213 TL |
9924 | /* |
9925 | * Guests with protected state can't have it read by the hypervisor, | |
9926 | * so skip trying to save it. | |
9927 | */ | |
9928 | if (vcpu->arch.guest_fpu) | |
9929 | kvm_save_current_fpu(vcpu->arch.guest_fpu); | |
c9aef3b8 | 9930 | |
1c61fada | 9931 | restore_fpregs_from_fpstate(&vcpu->arch.user_fpu->state); |
5f409e20 RR |
9932 | |
9933 | fpregs_mark_activate(); | |
9934 | fpregs_unlock(); | |
9935 | ||
822f312d SAS |
9936 | ++vcpu->stat.fpu_reload; |
9937 | trace_kvm_fpu(0); | |
9938 | } | |
9939 | ||
1b94f6f8 | 9940 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) |
b6c7a5dc | 9941 | { |
1b94f6f8 | 9942 | struct kvm_run *kvm_run = vcpu->run; |
b6c7a5dc | 9943 | int r; |
b6c7a5dc | 9944 | |
accb757d | 9945 | vcpu_load(vcpu); |
20b7035c | 9946 | kvm_sigset_activate(vcpu); |
15aad3be | 9947 | kvm_run->flags = 0; |
5663d8f9 PX |
9948 | kvm_load_guest_fpu(vcpu); |
9949 | ||
a4535290 | 9950 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
2f173d26 JS |
9951 | if (kvm_run->immediate_exit) { |
9952 | r = -EINTR; | |
9953 | goto out; | |
9954 | } | |
b6c7a5dc | 9955 | kvm_vcpu_block(vcpu); |
4fe09bcf JM |
9956 | if (kvm_apic_accept_events(vcpu) < 0) { |
9957 | r = 0; | |
9958 | goto out; | |
9959 | } | |
72875d8a | 9960 | kvm_clear_request(KVM_REQ_UNHALT, vcpu); |
ac9f6dc0 | 9961 | r = -EAGAIN; |
a0595000 JS |
9962 | if (signal_pending(current)) { |
9963 | r = -EINTR; | |
1b94f6f8 | 9964 | kvm_run->exit_reason = KVM_EXIT_INTR; |
a0595000 JS |
9965 | ++vcpu->stat.signal_exits; |
9966 | } | |
ac9f6dc0 | 9967 | goto out; |
b6c7a5dc HB |
9968 | } |
9969 | ||
1b94f6f8 | 9970 | if (kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) { |
01643c51 KH |
9971 | r = -EINVAL; |
9972 | goto out; | |
9973 | } | |
9974 | ||
1b94f6f8 | 9975 | if (kvm_run->kvm_dirty_regs) { |
01643c51 KH |
9976 | r = sync_regs(vcpu); |
9977 | if (r != 0) | |
9978 | goto out; | |
9979 | } | |
9980 | ||
b6c7a5dc | 9981 | /* re-sync apic's tpr */ |
35754c98 | 9982 | if (!lapic_in_kernel(vcpu)) { |
eea1cff9 AP |
9983 | if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { |
9984 | r = -EINVAL; | |
9985 | goto out; | |
9986 | } | |
9987 | } | |
b6c7a5dc | 9988 | |
716d51ab GN |
9989 | if (unlikely(vcpu->arch.complete_userspace_io)) { |
9990 | int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; | |
9991 | vcpu->arch.complete_userspace_io = NULL; | |
9992 | r = cui(vcpu); | |
9993 | if (r <= 0) | |
5663d8f9 | 9994 | goto out; |
716d51ab GN |
9995 | } else |
9996 | WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); | |
5287f194 | 9997 | |
460df4c1 PB |
9998 | if (kvm_run->immediate_exit) |
9999 | r = -EINTR; | |
10000 | else | |
10001 | r = vcpu_run(vcpu); | |
b6c7a5dc HB |
10002 | |
10003 | out: | |
5663d8f9 | 10004 | kvm_put_guest_fpu(vcpu); |
1b94f6f8 | 10005 | if (kvm_run->kvm_valid_regs) |
01643c51 | 10006 | store_regs(vcpu); |
f1d86e46 | 10007 | post_kvm_run_save(vcpu); |
20b7035c | 10008 | kvm_sigset_deactivate(vcpu); |
b6c7a5dc | 10009 | |
accb757d | 10010 | vcpu_put(vcpu); |
b6c7a5dc HB |
10011 | return r; |
10012 | } | |
10013 | ||
01643c51 | 10014 | static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 10015 | { |
7ae441ea GN |
10016 | if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { |
10017 | /* | |
10018 | * We are here if userspace calls get_regs() in the middle of | |
10019 | * instruction emulation. Registers state needs to be copied | |
4a969980 | 10020 | * back from emulation context to vcpu. Userspace shouldn't do |
7ae441ea GN |
10021 | * that usually, but some bad designed PV devices (vmware |
10022 | * backdoor interface) need this to work | |
10023 | */ | |
c9b8b07c | 10024 | emulator_writeback_register_cache(vcpu->arch.emulate_ctxt); |
7ae441ea GN |
10025 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
10026 | } | |
de3cd117 SC |
10027 | regs->rax = kvm_rax_read(vcpu); |
10028 | regs->rbx = kvm_rbx_read(vcpu); | |
10029 | regs->rcx = kvm_rcx_read(vcpu); | |
10030 | regs->rdx = kvm_rdx_read(vcpu); | |
10031 | regs->rsi = kvm_rsi_read(vcpu); | |
10032 | regs->rdi = kvm_rdi_read(vcpu); | |
e9c16c78 | 10033 | regs->rsp = kvm_rsp_read(vcpu); |
de3cd117 | 10034 | regs->rbp = kvm_rbp_read(vcpu); |
b6c7a5dc | 10035 | #ifdef CONFIG_X86_64 |
de3cd117 SC |
10036 | regs->r8 = kvm_r8_read(vcpu); |
10037 | regs->r9 = kvm_r9_read(vcpu); | |
10038 | regs->r10 = kvm_r10_read(vcpu); | |
10039 | regs->r11 = kvm_r11_read(vcpu); | |
10040 | regs->r12 = kvm_r12_read(vcpu); | |
10041 | regs->r13 = kvm_r13_read(vcpu); | |
10042 | regs->r14 = kvm_r14_read(vcpu); | |
10043 | regs->r15 = kvm_r15_read(vcpu); | |
b6c7a5dc HB |
10044 | #endif |
10045 | ||
5fdbf976 | 10046 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 10047 | regs->rflags = kvm_get_rflags(vcpu); |
01643c51 | 10048 | } |
b6c7a5dc | 10049 | |
01643c51 KH |
10050 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
10051 | { | |
10052 | vcpu_load(vcpu); | |
10053 | __get_regs(vcpu, regs); | |
1fc9b76b | 10054 | vcpu_put(vcpu); |
b6c7a5dc HB |
10055 | return 0; |
10056 | } | |
10057 | ||
01643c51 | 10058 | static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 10059 | { |
7ae441ea GN |
10060 | vcpu->arch.emulate_regs_need_sync_from_vcpu = true; |
10061 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; | |
10062 | ||
de3cd117 SC |
10063 | kvm_rax_write(vcpu, regs->rax); |
10064 | kvm_rbx_write(vcpu, regs->rbx); | |
10065 | kvm_rcx_write(vcpu, regs->rcx); | |
10066 | kvm_rdx_write(vcpu, regs->rdx); | |
10067 | kvm_rsi_write(vcpu, regs->rsi); | |
10068 | kvm_rdi_write(vcpu, regs->rdi); | |
e9c16c78 | 10069 | kvm_rsp_write(vcpu, regs->rsp); |
de3cd117 | 10070 | kvm_rbp_write(vcpu, regs->rbp); |
b6c7a5dc | 10071 | #ifdef CONFIG_X86_64 |
de3cd117 SC |
10072 | kvm_r8_write(vcpu, regs->r8); |
10073 | kvm_r9_write(vcpu, regs->r9); | |
10074 | kvm_r10_write(vcpu, regs->r10); | |
10075 | kvm_r11_write(vcpu, regs->r11); | |
10076 | kvm_r12_write(vcpu, regs->r12); | |
10077 | kvm_r13_write(vcpu, regs->r13); | |
10078 | kvm_r14_write(vcpu, regs->r14); | |
10079 | kvm_r15_write(vcpu, regs->r15); | |
b6c7a5dc HB |
10080 | #endif |
10081 | ||
5fdbf976 | 10082 | kvm_rip_write(vcpu, regs->rip); |
d73235d1 | 10083 | kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); |
b6c7a5dc | 10084 | |
b4f14abd JK |
10085 | vcpu->arch.exception.pending = false; |
10086 | ||
3842d135 | 10087 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
01643c51 | 10088 | } |
3842d135 | 10089 | |
01643c51 KH |
10090 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
10091 | { | |
10092 | vcpu_load(vcpu); | |
10093 | __set_regs(vcpu, regs); | |
875656fe | 10094 | vcpu_put(vcpu); |
b6c7a5dc HB |
10095 | return 0; |
10096 | } | |
10097 | ||
b6c7a5dc HB |
10098 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
10099 | { | |
10100 | struct kvm_segment cs; | |
10101 | ||
3e6e0aab | 10102 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
10103 | *db = cs.db; |
10104 | *l = cs.l; | |
10105 | } | |
10106 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
10107 | ||
6dba9403 | 10108 | static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
b6c7a5dc | 10109 | { |
89a27f4d | 10110 | struct desc_ptr dt; |
b6c7a5dc | 10111 | |
5265713a TL |
10112 | if (vcpu->arch.guest_state_protected) |
10113 | goto skip_protected_regs; | |
10114 | ||
3e6e0aab GT |
10115 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
10116 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
10117 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
10118 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
10119 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
10120 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 10121 | |
3e6e0aab GT |
10122 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
10123 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 10124 | |
b3646477 | 10125 | static_call(kvm_x86_get_idt)(vcpu, &dt); |
89a27f4d GN |
10126 | sregs->idt.limit = dt.size; |
10127 | sregs->idt.base = dt.address; | |
b3646477 | 10128 | static_call(kvm_x86_get_gdt)(vcpu, &dt); |
89a27f4d GN |
10129 | sregs->gdt.limit = dt.size; |
10130 | sregs->gdt.base = dt.address; | |
b6c7a5dc | 10131 | |
ad312c7c | 10132 | sregs->cr2 = vcpu->arch.cr2; |
9f8fe504 | 10133 | sregs->cr3 = kvm_read_cr3(vcpu); |
5265713a TL |
10134 | |
10135 | skip_protected_regs: | |
10136 | sregs->cr0 = kvm_read_cr0(vcpu); | |
fc78f519 | 10137 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 10138 | sregs->cr8 = kvm_get_cr8(vcpu); |
f6801dff | 10139 | sregs->efer = vcpu->arch.efer; |
b6c7a5dc | 10140 | sregs->apic_base = kvm_get_apic_base(vcpu); |
6dba9403 | 10141 | } |
b6c7a5dc | 10142 | |
6dba9403 ML |
10143 | static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
10144 | { | |
10145 | __get_sregs_common(vcpu, sregs); | |
10146 | ||
10147 | if (vcpu->arch.guest_state_protected) | |
10148 | return; | |
b6c7a5dc | 10149 | |
04140b41 | 10150 | if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
10151 | set_bit(vcpu->arch.interrupt.nr, |
10152 | (unsigned long *)sregs->interrupt_bitmap); | |
01643c51 | 10153 | } |
16d7a191 | 10154 | |
6dba9403 ML |
10155 | static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) |
10156 | { | |
10157 | int i; | |
10158 | ||
10159 | __get_sregs_common(vcpu, (struct kvm_sregs *)sregs2); | |
10160 | ||
10161 | if (vcpu->arch.guest_state_protected) | |
10162 | return; | |
10163 | ||
10164 | if (is_pae_paging(vcpu)) { | |
10165 | for (i = 0 ; i < 4 ; i++) | |
10166 | sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i); | |
10167 | sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID; | |
10168 | } | |
10169 | } | |
10170 | ||
01643c51 KH |
10171 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, |
10172 | struct kvm_sregs *sregs) | |
10173 | { | |
10174 | vcpu_load(vcpu); | |
10175 | __get_sregs(vcpu, sregs); | |
bcdec41c | 10176 | vcpu_put(vcpu); |
b6c7a5dc HB |
10177 | return 0; |
10178 | } | |
10179 | ||
62d9f0db MT |
10180 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
10181 | struct kvm_mp_state *mp_state) | |
10182 | { | |
4fe09bcf JM |
10183 | int r; |
10184 | ||
fd232561 | 10185 | vcpu_load(vcpu); |
f958bd23 SC |
10186 | if (kvm_mpx_supported()) |
10187 | kvm_load_guest_fpu(vcpu); | |
fd232561 | 10188 | |
4fe09bcf JM |
10189 | r = kvm_apic_accept_events(vcpu); |
10190 | if (r < 0) | |
10191 | goto out; | |
10192 | r = 0; | |
10193 | ||
647daca2 TL |
10194 | if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED || |
10195 | vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) && | |
10196 | vcpu->arch.pv.pv_unhalted) | |
6aef266c SV |
10197 | mp_state->mp_state = KVM_MP_STATE_RUNNABLE; |
10198 | else | |
10199 | mp_state->mp_state = vcpu->arch.mp_state; | |
10200 | ||
4fe09bcf | 10201 | out: |
f958bd23 SC |
10202 | if (kvm_mpx_supported()) |
10203 | kvm_put_guest_fpu(vcpu); | |
fd232561 | 10204 | vcpu_put(vcpu); |
4fe09bcf | 10205 | return r; |
62d9f0db MT |
10206 | } |
10207 | ||
10208 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
10209 | struct kvm_mp_state *mp_state) | |
10210 | { | |
e83dff5e CD |
10211 | int ret = -EINVAL; |
10212 | ||
10213 | vcpu_load(vcpu); | |
10214 | ||
bce87cce | 10215 | if (!lapic_in_kernel(vcpu) && |
66450a21 | 10216 | mp_state->mp_state != KVM_MP_STATE_RUNNABLE) |
e83dff5e | 10217 | goto out; |
66450a21 | 10218 | |
27cbe7d6 LA |
10219 | /* |
10220 | * KVM_MP_STATE_INIT_RECEIVED means the processor is in | |
10221 | * INIT state; latched init should be reported using | |
10222 | * KVM_SET_VCPU_EVENTS, so reject it here. | |
10223 | */ | |
10224 | if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) && | |
28bf2888 DH |
10225 | (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || |
10226 | mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) | |
e83dff5e | 10227 | goto out; |
28bf2888 | 10228 | |
66450a21 JK |
10229 | if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { |
10230 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
10231 | set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); | |
10232 | } else | |
10233 | vcpu->arch.mp_state = mp_state->mp_state; | |
3842d135 | 10234 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
e83dff5e CD |
10235 | |
10236 | ret = 0; | |
10237 | out: | |
10238 | vcpu_put(vcpu); | |
10239 | return ret; | |
62d9f0db MT |
10240 | } |
10241 | ||
7f3d35fd KW |
10242 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
10243 | int reason, bool has_error_code, u32 error_code) | |
b6c7a5dc | 10244 | { |
c9b8b07c | 10245 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
8ec4722d | 10246 | int ret; |
e01c2426 | 10247 | |
8ec4722d | 10248 | init_emulate_ctxt(vcpu); |
c697518a | 10249 | |
7f3d35fd | 10250 | ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, |
9d74191a | 10251 | has_error_code, error_code); |
1051778f SC |
10252 | if (ret) { |
10253 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
10254 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
10255 | vcpu->run->internal.ndata = 0; | |
60fc3d02 | 10256 | return 0; |
1051778f | 10257 | } |
37817f29 | 10258 | |
9d74191a TY |
10259 | kvm_rip_write(vcpu, ctxt->eip); |
10260 | kvm_set_rflags(vcpu, ctxt->eflags); | |
60fc3d02 | 10261 | return 1; |
37817f29 IE |
10262 | } |
10263 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
10264 | ||
ee69c92b | 10265 | static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
f2981033 | 10266 | { |
37b95951 | 10267 | if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { |
f2981033 LT |
10268 | /* |
10269 | * When EFER.LME and CR0.PG are set, the processor is in | |
10270 | * 64-bit mode (though maybe in a 32-bit code segment). | |
10271 | * CR4.PAE and EFER.LMA must be set. | |
10272 | */ | |
ee69c92b SC |
10273 | if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA)) |
10274 | return false; | |
ca29e145 | 10275 | if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3)) |
c1c35cf7 | 10276 | return false; |
f2981033 LT |
10277 | } else { |
10278 | /* | |
10279 | * Not in 64-bit mode: EFER.LMA is clear and the code | |
10280 | * segment cannot be 64-bit. | |
10281 | */ | |
10282 | if (sregs->efer & EFER_LMA || sregs->cs.l) | |
ee69c92b | 10283 | return false; |
f2981033 LT |
10284 | } |
10285 | ||
ee69c92b | 10286 | return kvm_is_valid_cr4(vcpu, sregs->cr4); |
f2981033 LT |
10287 | } |
10288 | ||
6dba9403 ML |
10289 | static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs, |
10290 | int *mmu_reset_needed, bool update_pdptrs) | |
b6c7a5dc | 10291 | { |
58cb628d | 10292 | struct msr_data apic_base_msr; |
6dba9403 | 10293 | int idx; |
89a27f4d | 10294 | struct desc_ptr dt; |
b4ef9d4e | 10295 | |
ee69c92b | 10296 | if (!kvm_is_valid_sregs(vcpu, sregs)) |
6dba9403 | 10297 | return -EINVAL; |
f2981033 | 10298 | |
d3802286 JM |
10299 | apic_base_msr.data = sregs->apic_base; |
10300 | apic_base_msr.host_initiated = true; | |
10301 | if (kvm_set_apic_base(vcpu, &apic_base_msr)) | |
6dba9403 | 10302 | return -EINVAL; |
6d1068b3 | 10303 | |
5265713a | 10304 | if (vcpu->arch.guest_state_protected) |
6dba9403 | 10305 | return 0; |
5265713a | 10306 | |
89a27f4d GN |
10307 | dt.size = sregs->idt.limit; |
10308 | dt.address = sregs->idt.base; | |
b3646477 | 10309 | static_call(kvm_x86_set_idt)(vcpu, &dt); |
89a27f4d GN |
10310 | dt.size = sregs->gdt.limit; |
10311 | dt.address = sregs->gdt.base; | |
b3646477 | 10312 | static_call(kvm_x86_set_gdt)(vcpu, &dt); |
b6c7a5dc | 10313 | |
ad312c7c | 10314 | vcpu->arch.cr2 = sregs->cr2; |
6dba9403 | 10315 | *mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; |
dc7e795e | 10316 | vcpu->arch.cr3 = sregs->cr3; |
cb3c1e2f | 10317 | kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); |
b6c7a5dc | 10318 | |
2d3ad1f4 | 10319 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 10320 | |
6dba9403 | 10321 | *mmu_reset_needed |= vcpu->arch.efer != sregs->efer; |
b3646477 | 10322 | static_call(kvm_x86_set_efer)(vcpu, sregs->efer); |
b6c7a5dc | 10323 | |
6dba9403 | 10324 | *mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
b3646477 | 10325 | static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0); |
d7306163 | 10326 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 10327 | |
6dba9403 | 10328 | *mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
b3646477 | 10329 | static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4); |
63f42e02 | 10330 | |
6dba9403 ML |
10331 | if (update_pdptrs) { |
10332 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
10333 | if (is_pae_paging(vcpu)) { | |
10334 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); | |
10335 | *mmu_reset_needed = 1; | |
10336 | } | |
10337 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
7c93be44 | 10338 | } |
b6c7a5dc | 10339 | |
3e6e0aab GT |
10340 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
10341 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
10342 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
10343 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
10344 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
10345 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 10346 | |
3e6e0aab GT |
10347 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
10348 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 10349 | |
5f0269f5 ME |
10350 | update_cr8_intercept(vcpu); |
10351 | ||
9c3e4aab | 10352 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 10353 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 10354 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
3eeb3288 | 10355 | !is_protmode(vcpu)) |
9c3e4aab MT |
10356 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
10357 | ||
6dba9403 ML |
10358 | return 0; |
10359 | } | |
10360 | ||
10361 | static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) | |
10362 | { | |
10363 | int pending_vec, max_bits; | |
10364 | int mmu_reset_needed = 0; | |
10365 | int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true); | |
10366 | ||
10367 | if (ret) | |
10368 | return ret; | |
10369 | ||
10370 | if (mmu_reset_needed) | |
10371 | kvm_mmu_reset_context(vcpu); | |
10372 | ||
5265713a TL |
10373 | max_bits = KVM_NR_INTERRUPTS; |
10374 | pending_vec = find_first_bit( | |
10375 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
6dba9403 | 10376 | |
5265713a TL |
10377 | if (pending_vec < max_bits) { |
10378 | kvm_queue_interrupt(vcpu, pending_vec, false); | |
10379 | pr_debug("Set back pending irq %d\n", pending_vec); | |
6dba9403 | 10380 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
5265713a | 10381 | } |
6dba9403 ML |
10382 | return 0; |
10383 | } | |
5265713a | 10384 | |
6dba9403 ML |
10385 | static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) |
10386 | { | |
10387 | int mmu_reset_needed = 0; | |
10388 | bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID; | |
10389 | bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) && | |
10390 | !(sregs2->efer & EFER_LMA); | |
10391 | int i, ret; | |
3842d135 | 10392 | |
6dba9403 ML |
10393 | if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID) |
10394 | return -EINVAL; | |
10395 | ||
10396 | if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected)) | |
10397 | return -EINVAL; | |
10398 | ||
10399 | ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2, | |
10400 | &mmu_reset_needed, !valid_pdptrs); | |
10401 | if (ret) | |
10402 | return ret; | |
10403 | ||
10404 | if (valid_pdptrs) { | |
10405 | for (i = 0; i < 4 ; i++) | |
10406 | kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]); | |
10407 | ||
10408 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); | |
10409 | mmu_reset_needed = 1; | |
158a48ec | 10410 | vcpu->arch.pdptrs_from_userspace = true; |
6dba9403 ML |
10411 | } |
10412 | if (mmu_reset_needed) | |
10413 | kvm_mmu_reset_context(vcpu); | |
10414 | return 0; | |
01643c51 KH |
10415 | } |
10416 | ||
10417 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, | |
10418 | struct kvm_sregs *sregs) | |
10419 | { | |
10420 | int ret; | |
10421 | ||
10422 | vcpu_load(vcpu); | |
10423 | ret = __set_sregs(vcpu, sregs); | |
b4ef9d4e CD |
10424 | vcpu_put(vcpu); |
10425 | return ret; | |
b6c7a5dc HB |
10426 | } |
10427 | ||
d0bfb940 JK |
10428 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
10429 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 10430 | { |
355be0b9 | 10431 | unsigned long rflags; |
ae675ef0 | 10432 | int i, r; |
b6c7a5dc | 10433 | |
8d4846b9 TL |
10434 | if (vcpu->arch.guest_state_protected) |
10435 | return -EINVAL; | |
10436 | ||
66b56562 CD |
10437 | vcpu_load(vcpu); |
10438 | ||
4f926bf2 JK |
10439 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
10440 | r = -EBUSY; | |
10441 | if (vcpu->arch.exception.pending) | |
2122ff5e | 10442 | goto out; |
4f926bf2 JK |
10443 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
10444 | kvm_queue_exception(vcpu, DB_VECTOR); | |
10445 | else | |
10446 | kvm_queue_exception(vcpu, BP_VECTOR); | |
10447 | } | |
10448 | ||
91586a3b JK |
10449 | /* |
10450 | * Read rflags as long as potentially injected trace flags are still | |
10451 | * filtered out. | |
10452 | */ | |
10453 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
10454 | |
10455 | vcpu->guest_debug = dbg->control; | |
10456 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
10457 | vcpu->guest_debug = 0; | |
10458 | ||
10459 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
10460 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
10461 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
c8639010 | 10462 | vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; |
ae675ef0 JK |
10463 | } else { |
10464 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
10465 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
ae675ef0 | 10466 | } |
c8639010 | 10467 | kvm_update_dr7(vcpu); |
ae675ef0 | 10468 | |
f92653ee | 10469 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
e87e46d5 | 10470 | vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu); |
94fe45da | 10471 | |
91586a3b JK |
10472 | /* |
10473 | * Trigger an rflags update that will inject or remove the trace | |
10474 | * flags. | |
10475 | */ | |
10476 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 10477 | |
b3646477 | 10478 | static_call(kvm_x86_update_exception_bitmap)(vcpu); |
b6c7a5dc | 10479 | |
4f926bf2 | 10480 | r = 0; |
d0bfb940 | 10481 | |
2122ff5e | 10482 | out: |
66b56562 | 10483 | vcpu_put(vcpu); |
b6c7a5dc HB |
10484 | return r; |
10485 | } | |
10486 | ||
8b006791 ZX |
10487 | /* |
10488 | * Translate a guest virtual address to a guest physical address. | |
10489 | */ | |
10490 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
10491 | struct kvm_translation *tr) | |
10492 | { | |
10493 | unsigned long vaddr = tr->linear_address; | |
10494 | gpa_t gpa; | |
f656ce01 | 10495 | int idx; |
8b006791 | 10496 | |
1da5b61d CD |
10497 | vcpu_load(vcpu); |
10498 | ||
f656ce01 | 10499 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1871c602 | 10500 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); |
f656ce01 | 10501 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 ZX |
10502 | tr->physical_address = gpa; |
10503 | tr->valid = gpa != UNMAPPED_GVA; | |
10504 | tr->writeable = 1; | |
10505 | tr->usermode = 0; | |
8b006791 | 10506 | |
1da5b61d | 10507 | vcpu_put(vcpu); |
8b006791 ZX |
10508 | return 0; |
10509 | } | |
10510 | ||
d0752060 HB |
10511 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
10512 | { | |
1393123e | 10513 | struct fxregs_state *fxsave; |
d0752060 | 10514 | |
ed02b213 TL |
10515 | if (!vcpu->arch.guest_fpu) |
10516 | return 0; | |
10517 | ||
1393123e | 10518 | vcpu_load(vcpu); |
d0752060 | 10519 | |
b666a4b6 | 10520 | fxsave = &vcpu->arch.guest_fpu->state.fxsave; |
d0752060 HB |
10521 | memcpy(fpu->fpr, fxsave->st_space, 128); |
10522 | fpu->fcw = fxsave->cwd; | |
10523 | fpu->fsw = fxsave->swd; | |
10524 | fpu->ftwx = fxsave->twd; | |
10525 | fpu->last_opcode = fxsave->fop; | |
10526 | fpu->last_ip = fxsave->rip; | |
10527 | fpu->last_dp = fxsave->rdp; | |
0e96f31e | 10528 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); |
d0752060 | 10529 | |
1393123e | 10530 | vcpu_put(vcpu); |
d0752060 HB |
10531 | return 0; |
10532 | } | |
10533 | ||
10534 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
10535 | { | |
6a96bc7f CD |
10536 | struct fxregs_state *fxsave; |
10537 | ||
ed02b213 TL |
10538 | if (!vcpu->arch.guest_fpu) |
10539 | return 0; | |
10540 | ||
6a96bc7f CD |
10541 | vcpu_load(vcpu); |
10542 | ||
b666a4b6 | 10543 | fxsave = &vcpu->arch.guest_fpu->state.fxsave; |
d0752060 | 10544 | |
d0752060 HB |
10545 | memcpy(fxsave->st_space, fpu->fpr, 128); |
10546 | fxsave->cwd = fpu->fcw; | |
10547 | fxsave->swd = fpu->fsw; | |
10548 | fxsave->twd = fpu->ftwx; | |
10549 | fxsave->fop = fpu->last_opcode; | |
10550 | fxsave->rip = fpu->last_ip; | |
10551 | fxsave->rdp = fpu->last_dp; | |
0e96f31e | 10552 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); |
d0752060 | 10553 | |
6a96bc7f | 10554 | vcpu_put(vcpu); |
d0752060 HB |
10555 | return 0; |
10556 | } | |
10557 | ||
01643c51 KH |
10558 | static void store_regs(struct kvm_vcpu *vcpu) |
10559 | { | |
10560 | BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); | |
10561 | ||
10562 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) | |
10563 | __get_regs(vcpu, &vcpu->run->s.regs.regs); | |
10564 | ||
10565 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) | |
10566 | __get_sregs(vcpu, &vcpu->run->s.regs.sregs); | |
10567 | ||
10568 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) | |
10569 | kvm_vcpu_ioctl_x86_get_vcpu_events( | |
10570 | vcpu, &vcpu->run->s.regs.events); | |
10571 | } | |
10572 | ||
10573 | static int sync_regs(struct kvm_vcpu *vcpu) | |
10574 | { | |
10575 | if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS) | |
10576 | return -EINVAL; | |
10577 | ||
10578 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { | |
10579 | __set_regs(vcpu, &vcpu->run->s.regs.regs); | |
10580 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; | |
10581 | } | |
10582 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { | |
10583 | if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) | |
10584 | return -EINVAL; | |
10585 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; | |
10586 | } | |
10587 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { | |
10588 | if (kvm_vcpu_ioctl_x86_set_vcpu_events( | |
10589 | vcpu, &vcpu->run->s.regs.events)) | |
10590 | return -EINVAL; | |
10591 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; | |
10592 | } | |
10593 | ||
10594 | return 0; | |
10595 | } | |
10596 | ||
0ee6a517 | 10597 | static void fx_init(struct kvm_vcpu *vcpu) |
d0752060 | 10598 | { |
ed02b213 TL |
10599 | if (!vcpu->arch.guest_fpu) |
10600 | return; | |
10601 | ||
b666a4b6 | 10602 | fpstate_init(&vcpu->arch.guest_fpu->state); |
782511b0 | 10603 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
b666a4b6 | 10604 | vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv = |
df1daba7 | 10605 | host_xcr0 | XSTATE_COMPACTION_ENABLED; |
d0752060 | 10606 | |
2acf923e DC |
10607 | /* |
10608 | * Ensure guest xcr0 is valid for loading | |
10609 | */ | |
d91cab78 | 10610 | vcpu->arch.xcr0 = XFEATURE_MASK_FP; |
2acf923e | 10611 | |
ad312c7c | 10612 | vcpu->arch.cr0 |= X86_CR0_ET; |
d0752060 | 10613 | } |
d0752060 | 10614 | |
ed02b213 TL |
10615 | void kvm_free_guest_fpu(struct kvm_vcpu *vcpu) |
10616 | { | |
10617 | if (vcpu->arch.guest_fpu) { | |
10618 | kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu); | |
10619 | vcpu->arch.guest_fpu = NULL; | |
10620 | } | |
10621 | } | |
10622 | EXPORT_SYMBOL_GPL(kvm_free_guest_fpu); | |
10623 | ||
897cc38e | 10624 | int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) |
e9b11c17 | 10625 | { |
897cc38e SC |
10626 | if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) |
10627 | pr_warn_once("kvm: SMP vm created on host with unstable TSC; " | |
10628 | "guest TSC will not be reliable\n"); | |
7f1ea208 | 10629 | |
897cc38e | 10630 | return 0; |
e9b11c17 ZX |
10631 | } |
10632 | ||
e529ef66 | 10633 | int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) |
e9b11c17 | 10634 | { |
95a0d01e SC |
10635 | struct page *page; |
10636 | int r; | |
c447e76b | 10637 | |
63f5a190 SC |
10638 | vcpu->arch.last_vmentry_cpu = -1; |
10639 | ||
95a0d01e SC |
10640 | if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) |
10641 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
10642 | else | |
10643 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; | |
c447e76b | 10644 | |
95a0d01e SC |
10645 | r = kvm_mmu_create(vcpu); |
10646 | if (r < 0) | |
10647 | return r; | |
10648 | ||
10649 | if (irqchip_in_kernel(vcpu->kvm)) { | |
95a0d01e SC |
10650 | r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); |
10651 | if (r < 0) | |
10652 | goto fail_mmu_destroy; | |
4e19c36f SS |
10653 | if (kvm_apicv_activated(vcpu->kvm)) |
10654 | vcpu->arch.apicv_active = true; | |
95a0d01e | 10655 | } else |
6e4e3b4d | 10656 | static_branch_inc(&kvm_has_noapic_vcpu); |
95a0d01e SC |
10657 | |
10658 | r = -ENOMEM; | |
10659 | ||
93bb59ca | 10660 | page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); |
95a0d01e SC |
10661 | if (!page) |
10662 | goto fail_free_lapic; | |
10663 | vcpu->arch.pio_data = page_address(page); | |
10664 | ||
10665 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, | |
10666 | GFP_KERNEL_ACCOUNT); | |
10667 | if (!vcpu->arch.mce_banks) | |
10668 | goto fail_free_pio_data; | |
10669 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
10670 | ||
10671 | if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, | |
10672 | GFP_KERNEL_ACCOUNT)) | |
10673 | goto fail_free_mce_banks; | |
10674 | ||
c9b8b07c SC |
10675 | if (!alloc_emulate_ctxt(vcpu)) |
10676 | goto free_wbinvd_dirty_mask; | |
10677 | ||
95a0d01e SC |
10678 | vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache, |
10679 | GFP_KERNEL_ACCOUNT); | |
10680 | if (!vcpu->arch.user_fpu) { | |
10681 | pr_err("kvm: failed to allocate userspace's fpu\n"); | |
c9b8b07c | 10682 | goto free_emulate_ctxt; |
95a0d01e SC |
10683 | } |
10684 | ||
10685 | vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, | |
10686 | GFP_KERNEL_ACCOUNT); | |
10687 | if (!vcpu->arch.guest_fpu) { | |
10688 | pr_err("kvm: failed to allocate vcpu's fpu\n"); | |
10689 | goto free_user_fpu; | |
10690 | } | |
10691 | fx_init(vcpu); | |
10692 | ||
95a0d01e | 10693 | vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); |
a8ac864a | 10694 | vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); |
95a0d01e SC |
10695 | |
10696 | vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; | |
10697 | ||
10698 | kvm_async_pf_hash_reset(vcpu); | |
10699 | kvm_pmu_init(vcpu); | |
10700 | ||
10701 | vcpu->arch.pending_external_vector = -1; | |
10702 | vcpu->arch.preempted_in_kernel = false; | |
10703 | ||
3c86c0d3 VP |
10704 | #if IS_ENABLED(CONFIG_HYPERV) |
10705 | vcpu->arch.hv_root_tdp = INVALID_PAGE; | |
10706 | #endif | |
10707 | ||
b3646477 | 10708 | r = static_call(kvm_x86_vcpu_create)(vcpu); |
95a0d01e SC |
10709 | if (r) |
10710 | goto free_guest_fpu; | |
e9b11c17 | 10711 | |
0cf9135b | 10712 | vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); |
e53d88af | 10713 | vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; |
19efffa2 | 10714 | kvm_vcpu_mtrr_init(vcpu); |
ec7660cc | 10715 | vcpu_load(vcpu); |
1ab9287a | 10716 | kvm_set_tsc_khz(vcpu, max_tsc_khz); |
d28bc9dd | 10717 | kvm_vcpu_reset(vcpu, false); |
c9060662 | 10718 | kvm_init_mmu(vcpu); |
e9b11c17 | 10719 | vcpu_put(vcpu); |
ec7660cc | 10720 | return 0; |
95a0d01e SC |
10721 | |
10722 | free_guest_fpu: | |
ed02b213 | 10723 | kvm_free_guest_fpu(vcpu); |
95a0d01e SC |
10724 | free_user_fpu: |
10725 | kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); | |
c9b8b07c SC |
10726 | free_emulate_ctxt: |
10727 | kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); | |
95a0d01e SC |
10728 | free_wbinvd_dirty_mask: |
10729 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); | |
10730 | fail_free_mce_banks: | |
10731 | kfree(vcpu->arch.mce_banks); | |
10732 | fail_free_pio_data: | |
10733 | free_page((unsigned long)vcpu->arch.pio_data); | |
10734 | fail_free_lapic: | |
10735 | kvm_free_lapic(vcpu); | |
10736 | fail_mmu_destroy: | |
10737 | kvm_mmu_destroy(vcpu); | |
10738 | return r; | |
e9b11c17 ZX |
10739 | } |
10740 | ||
31928aa5 | 10741 | void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) |
42897d86 | 10742 | { |
332967a3 | 10743 | struct kvm *kvm = vcpu->kvm; |
42897d86 | 10744 | |
ec7660cc | 10745 | if (mutex_lock_killable(&vcpu->mutex)) |
31928aa5 | 10746 | return; |
ec7660cc | 10747 | vcpu_load(vcpu); |
0c899c25 | 10748 | kvm_synchronize_tsc(vcpu, 0); |
42897d86 | 10749 | vcpu_put(vcpu); |
2d5ba19b MT |
10750 | |
10751 | /* poll control enabled by default */ | |
10752 | vcpu->arch.msr_kvm_poll_control = 1; | |
10753 | ||
ec7660cc | 10754 | mutex_unlock(&vcpu->mutex); |
42897d86 | 10755 | |
b34de572 WL |
10756 | if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0) |
10757 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
10758 | KVMCLOCK_SYNC_PERIOD); | |
42897d86 MT |
10759 | } |
10760 | ||
d40ccc62 | 10761 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 | 10762 | { |
4cbc418a | 10763 | struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache; |
95a0d01e | 10764 | int idx; |
344d9588 | 10765 | |
4cbc418a PB |
10766 | kvm_release_pfn(cache->pfn, cache->dirty, cache); |
10767 | ||
50b143e1 | 10768 | kvmclock_reset(vcpu); |
e9b11c17 | 10769 | |
b3646477 | 10770 | static_call(kvm_x86_vcpu_free)(vcpu); |
50b143e1 | 10771 | |
c9b8b07c | 10772 | kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); |
50b143e1 SC |
10773 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); |
10774 | kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); | |
ed02b213 | 10775 | kvm_free_guest_fpu(vcpu); |
95a0d01e SC |
10776 | |
10777 | kvm_hv_vcpu_uninit(vcpu); | |
10778 | kvm_pmu_destroy(vcpu); | |
10779 | kfree(vcpu->arch.mce_banks); | |
10780 | kvm_free_lapic(vcpu); | |
10781 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
10782 | kvm_mmu_destroy(vcpu); | |
10783 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
10784 | free_page((unsigned long)vcpu->arch.pio_data); | |
255cbecf | 10785 | kvfree(vcpu->arch.cpuid_entries); |
95a0d01e | 10786 | if (!lapic_in_kernel(vcpu)) |
6e4e3b4d | 10787 | static_branch_dec(&kvm_has_noapic_vcpu); |
e9b11c17 ZX |
10788 | } |
10789 | ||
d28bc9dd | 10790 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
e9b11c17 | 10791 | { |
0aa18375 SC |
10792 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
10793 | ||
b7e31be3 RK |
10794 | kvm_lapic_reset(vcpu, init_event); |
10795 | ||
e69fab5d PB |
10796 | vcpu->arch.hflags = 0; |
10797 | ||
c43203ca | 10798 | vcpu->arch.smi_pending = 0; |
52797bf9 | 10799 | vcpu->arch.smi_count = 0; |
7460fb4a AK |
10800 | atomic_set(&vcpu->arch.nmi_queued, 0); |
10801 | vcpu->arch.nmi_pending = 0; | |
448fa4a9 | 10802 | vcpu->arch.nmi_injected = false; |
5f7552d4 NA |
10803 | kvm_clear_interrupt_queue(vcpu); |
10804 | kvm_clear_exception_queue(vcpu); | |
448fa4a9 | 10805 | |
42dbaa5a | 10806 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); |
ae561ede | 10807 | kvm_update_dr0123(vcpu); |
9a3ecd5e | 10808 | vcpu->arch.dr6 = DR6_ACTIVE_LOW; |
42dbaa5a | 10809 | vcpu->arch.dr7 = DR7_FIXED_1; |
c8639010 | 10810 | kvm_update_dr7(vcpu); |
42dbaa5a | 10811 | |
1119022c NA |
10812 | vcpu->arch.cr2 = 0; |
10813 | ||
3842d135 | 10814 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
2635b5c4 VK |
10815 | vcpu->arch.apf.msr_en_val = 0; |
10816 | vcpu->arch.apf.msr_int_val = 0; | |
c9aaa895 | 10817 | vcpu->arch.st.msr_val = 0; |
3842d135 | 10818 | |
12f9a48f GC |
10819 | kvmclock_reset(vcpu); |
10820 | ||
af585b92 GN |
10821 | kvm_clear_async_pf_completion_queue(vcpu); |
10822 | kvm_async_pf_hash_reset(vcpu); | |
10823 | vcpu->arch.apf.halted = false; | |
3842d135 | 10824 | |
ed02b213 | 10825 | if (vcpu->arch.guest_fpu && kvm_mpx_supported()) { |
a554d207 WL |
10826 | void *mpx_state_buffer; |
10827 | ||
10828 | /* | |
10829 | * To avoid have the INIT path from kvm_apic_has_events() that be | |
10830 | * called with loaded FPU and does not let userspace fix the state. | |
10831 | */ | |
f775b13e RR |
10832 | if (init_event) |
10833 | kvm_put_guest_fpu(vcpu); | |
b666a4b6 | 10834 | mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, |
abd16d68 | 10835 | XFEATURE_BNDREGS); |
a554d207 WL |
10836 | if (mpx_state_buffer) |
10837 | memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state)); | |
b666a4b6 | 10838 | mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, |
abd16d68 | 10839 | XFEATURE_BNDCSR); |
a554d207 WL |
10840 | if (mpx_state_buffer) |
10841 | memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr)); | |
f775b13e RR |
10842 | if (init_event) |
10843 | kvm_load_guest_fpu(vcpu); | |
a554d207 WL |
10844 | } |
10845 | ||
64d60670 | 10846 | if (!init_event) { |
d28bc9dd | 10847 | kvm_pmu_reset(vcpu); |
64d60670 | 10848 | vcpu->arch.smbase = 0x30000; |
db2336a8 | 10849 | |
db2336a8 | 10850 | vcpu->arch.msr_misc_features_enables = 0; |
a554d207 WL |
10851 | |
10852 | vcpu->arch.xcr0 = XFEATURE_MASK_FP; | |
64d60670 | 10853 | } |
f5132b01 | 10854 | |
66f7b72e JS |
10855 | memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); |
10856 | vcpu->arch.regs_avail = ~0; | |
10857 | vcpu->arch.regs_dirty = ~0; | |
10858 | ||
a554d207 WL |
10859 | vcpu->arch.ia32_xss = 0; |
10860 | ||
b3646477 | 10861 | static_call(kvm_x86_vcpu_reset)(vcpu, init_event); |
0aa18375 SC |
10862 | |
10863 | /* | |
10864 | * Reset the MMU context if paging was enabled prior to INIT (which is | |
10865 | * implied if CR0.PG=1 as CR0 will be '0' prior to RESET). Unlike the | |
10866 | * standard CR0/CR4/EFER modification paths, only CR0.PG needs to be | |
10867 | * checked because it is unconditionally cleared on INIT and all other | |
10868 | * paging related bits are ignored if paging is disabled, i.e. CR0.WP, | |
10869 | * CR4, and EFER changes are all irrelevant if CR0.PG was '0'. | |
10870 | */ | |
10871 | if (old_cr0 & X86_CR0_PG) | |
10872 | kvm_mmu_reset_context(vcpu); | |
e9b11c17 ZX |
10873 | } |
10874 | ||
2b4a273b | 10875 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) |
66450a21 JK |
10876 | { |
10877 | struct kvm_segment cs; | |
10878 | ||
10879 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
10880 | cs.selector = vector << 8; | |
10881 | cs.base = vector << 12; | |
10882 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
10883 | kvm_rip_write(vcpu, 0); | |
e9b11c17 | 10884 | } |
647daca2 | 10885 | EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector); |
e9b11c17 | 10886 | |
13a34e06 | 10887 | int kvm_arch_hardware_enable(void) |
e9b11c17 | 10888 | { |
ca84d1a2 ZA |
10889 | struct kvm *kvm; |
10890 | struct kvm_vcpu *vcpu; | |
10891 | int i; | |
0dd6a6ed ZA |
10892 | int ret; |
10893 | u64 local_tsc; | |
10894 | u64 max_tsc = 0; | |
10895 | bool stable, backwards_tsc = false; | |
18863bdd | 10896 | |
7e34fbd0 | 10897 | kvm_user_return_msr_cpu_online(); |
b3646477 | 10898 | ret = static_call(kvm_x86_hardware_enable)(); |
0dd6a6ed ZA |
10899 | if (ret != 0) |
10900 | return ret; | |
10901 | ||
4ea1636b | 10902 | local_tsc = rdtsc(); |
b0c39dc6 | 10903 | stable = !kvm_check_tsc_unstable(); |
0dd6a6ed ZA |
10904 | list_for_each_entry(kvm, &vm_list, vm_list) { |
10905 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
10906 | if (!stable && vcpu->cpu == smp_processor_id()) | |
105b21bb | 10907 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
10908 | if (stable && vcpu->arch.last_host_tsc > local_tsc) { |
10909 | backwards_tsc = true; | |
10910 | if (vcpu->arch.last_host_tsc > max_tsc) | |
10911 | max_tsc = vcpu->arch.last_host_tsc; | |
10912 | } | |
10913 | } | |
10914 | } | |
10915 | ||
10916 | /* | |
10917 | * Sometimes, even reliable TSCs go backwards. This happens on | |
10918 | * platforms that reset TSC during suspend or hibernate actions, but | |
10919 | * maintain synchronization. We must compensate. Fortunately, we can | |
10920 | * detect that condition here, which happens early in CPU bringup, | |
10921 | * before any KVM threads can be running. Unfortunately, we can't | |
10922 | * bring the TSCs fully up to date with real time, as we aren't yet far | |
10923 | * enough into CPU bringup that we know how much real time has actually | |
9285ec4c | 10924 | * elapsed; our helper function, ktime_get_boottime_ns() will be using boot |
0dd6a6ed ZA |
10925 | * variables that haven't been updated yet. |
10926 | * | |
10927 | * So we simply find the maximum observed TSC above, then record the | |
10928 | * adjustment to TSC in each VCPU. When the VCPU later gets loaded, | |
10929 | * the adjustment will be applied. Note that we accumulate | |
10930 | * adjustments, in case multiple suspend cycles happen before some VCPU | |
10931 | * gets a chance to run again. In the event that no KVM threads get a | |
10932 | * chance to run, we will miss the entire elapsed period, as we'll have | |
10933 | * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may | |
10934 | * loose cycle time. This isn't too big a deal, since the loss will be | |
10935 | * uniform across all VCPUs (not to mention the scenario is extremely | |
10936 | * unlikely). It is possible that a second hibernate recovery happens | |
10937 | * much faster than a first, causing the observed TSC here to be | |
10938 | * smaller; this would require additional padding adjustment, which is | |
10939 | * why we set last_host_tsc to the local tsc observed here. | |
10940 | * | |
10941 | * N.B. - this code below runs only on platforms with reliable TSC, | |
10942 | * as that is the only way backwards_tsc is set above. Also note | |
10943 | * that this runs for ALL vcpus, which is not a bug; all VCPUs should | |
10944 | * have the same delta_cyc adjustment applied if backwards_tsc | |
10945 | * is detected. Note further, this adjustment is only done once, | |
10946 | * as we reset last_host_tsc on all VCPUs to stop this from being | |
10947 | * called multiple times (one for each physical CPU bringup). | |
10948 | * | |
4a969980 | 10949 | * Platforms with unreliable TSCs don't have to deal with this, they |
0dd6a6ed ZA |
10950 | * will be compensated by the logic in vcpu_load, which sets the TSC to |
10951 | * catchup mode. This will catchup all VCPUs to real time, but cannot | |
10952 | * guarantee that they stay in perfect synchronization. | |
10953 | */ | |
10954 | if (backwards_tsc) { | |
10955 | u64 delta_cyc = max_tsc - local_tsc; | |
10956 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
a826faf1 | 10957 | kvm->arch.backwards_tsc_observed = true; |
0dd6a6ed ZA |
10958 | kvm_for_each_vcpu(i, vcpu, kvm) { |
10959 | vcpu->arch.tsc_offset_adjustment += delta_cyc; | |
10960 | vcpu->arch.last_host_tsc = local_tsc; | |
105b21bb | 10961 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
10962 | } |
10963 | ||
10964 | /* | |
10965 | * We have to disable TSC offset matching.. if you were | |
10966 | * booting a VM while issuing an S4 host suspend.... | |
10967 | * you may have some problem. Solving this issue is | |
10968 | * left as an exercise to the reader. | |
10969 | */ | |
10970 | kvm->arch.last_tsc_nsec = 0; | |
10971 | kvm->arch.last_tsc_write = 0; | |
10972 | } | |
10973 | ||
10974 | } | |
10975 | return 0; | |
e9b11c17 ZX |
10976 | } |
10977 | ||
13a34e06 | 10978 | void kvm_arch_hardware_disable(void) |
e9b11c17 | 10979 | { |
b3646477 | 10980 | static_call(kvm_x86_hardware_disable)(); |
13a34e06 | 10981 | drop_user_return_notifiers(); |
e9b11c17 ZX |
10982 | } |
10983 | ||
b9904085 | 10984 | int kvm_arch_hardware_setup(void *opaque) |
e9b11c17 | 10985 | { |
d008dfdb | 10986 | struct kvm_x86_init_ops *ops = opaque; |
9e9c3fe4 NA |
10987 | int r; |
10988 | ||
91661989 SC |
10989 | rdmsrl_safe(MSR_EFER, &host_efer); |
10990 | ||
408e9a31 PB |
10991 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
10992 | rdmsrl(MSR_IA32_XSS, host_xss); | |
10993 | ||
d008dfdb | 10994 | r = ops->hardware_setup(); |
9e9c3fe4 NA |
10995 | if (r != 0) |
10996 | return r; | |
10997 | ||
afaf0b2f | 10998 | memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops)); |
b3646477 | 10999 | kvm_ops_static_call_update(); |
69c6f69a | 11000 | |
408e9a31 PB |
11001 | if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES)) |
11002 | supported_xss = 0; | |
11003 | ||
139f7425 PB |
11004 | #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f) |
11005 | cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_); | |
11006 | #undef __kvm_cpu_cap_has | |
b11306b5 | 11007 | |
35181e86 HZ |
11008 | if (kvm_has_tsc_control) { |
11009 | /* | |
11010 | * Make sure the user can only configure tsc_khz values that | |
11011 | * fit into a signed integer. | |
273ba457 | 11012 | * A min value is not calculated because it will always |
35181e86 HZ |
11013 | * be 1 on all machines. |
11014 | */ | |
11015 | u64 max = min(0x7fffffffULL, | |
11016 | __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); | |
11017 | kvm_max_guest_tsc_khz = max; | |
11018 | ||
ad721883 | 11019 | kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; |
35181e86 | 11020 | } |
ad721883 | 11021 | |
9e9c3fe4 NA |
11022 | kvm_init_msr_list(); |
11023 | return 0; | |
e9b11c17 ZX |
11024 | } |
11025 | ||
11026 | void kvm_arch_hardware_unsetup(void) | |
11027 | { | |
b3646477 | 11028 | static_call(kvm_x86_hardware_unsetup)(); |
e9b11c17 ZX |
11029 | } |
11030 | ||
b9904085 | 11031 | int kvm_arch_check_processor_compat(void *opaque) |
e9b11c17 | 11032 | { |
f1cdecf5 | 11033 | struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); |
d008dfdb | 11034 | struct kvm_x86_init_ops *ops = opaque; |
f1cdecf5 SC |
11035 | |
11036 | WARN_ON(!irqs_disabled()); | |
11037 | ||
139f7425 PB |
11038 | if (__cr4_reserved_bits(cpu_has, c) != |
11039 | __cr4_reserved_bits(cpu_has, &boot_cpu_data)) | |
f1cdecf5 SC |
11040 | return -EIO; |
11041 | ||
d008dfdb | 11042 | return ops->check_processor_compatibility(); |
d71ba788 PB |
11043 | } |
11044 | ||
11045 | bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) | |
11046 | { | |
11047 | return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; | |
11048 | } | |
11049 | EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); | |
11050 | ||
11051 | bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) | |
11052 | { | |
11053 | return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; | |
e9b11c17 ZX |
11054 | } |
11055 | ||
6e4e3b4d CL |
11056 | __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu); |
11057 | EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu); | |
54e9818f | 11058 | |
e790d9ef RK |
11059 | void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) |
11060 | { | |
b35e5548 LX |
11061 | struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); |
11062 | ||
c595ceee | 11063 | vcpu->arch.l1tf_flush_l1d = true; |
b35e5548 LX |
11064 | if (pmu->version && unlikely(pmu->event_count)) { |
11065 | pmu->need_cleanup = true; | |
11066 | kvm_make_request(KVM_REQ_PMU, vcpu); | |
11067 | } | |
b3646477 | 11068 | static_call(kvm_x86_sched_in)(vcpu, cpu); |
e790d9ef RK |
11069 | } |
11070 | ||
562b6b08 SC |
11071 | void kvm_arch_free_vm(struct kvm *kvm) |
11072 | { | |
05f04ae4 | 11073 | kfree(to_kvm_hv(kvm)->hv_pa_pg); |
562b6b08 | 11074 | vfree(kvm); |
e790d9ef RK |
11075 | } |
11076 | ||
562b6b08 | 11077 | |
e08b9637 | 11078 | int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) |
d19a9cd2 | 11079 | { |
e08b9637 CO |
11080 | if (type) |
11081 | return -EINVAL; | |
11082 | ||
6ef768fa | 11083 | INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); |
f05e70ac | 11084 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
10605204 | 11085 | INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); |
1aa9b957 | 11086 | INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages); |
4d5c5d0f | 11087 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
e0f0bbc5 | 11088 | atomic_set(&kvm->arch.noncoherent_dma_count, 0); |
d19a9cd2 | 11089 | |
5550af4d SY |
11090 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
11091 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
7a84428a AW |
11092 | /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ |
11093 | set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, | |
11094 | &kvm->arch.irq_sources_bitmap); | |
5550af4d | 11095 | |
038f8c11 | 11096 | raw_spin_lock_init(&kvm->arch.tsc_write_lock); |
1e08ec4a | 11097 | mutex_init(&kvm->arch.apic_map_lock); |
d828199e MT |
11098 | spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); |
11099 | ||
8171cd68 | 11100 | kvm->arch.kvmclock_offset = -get_kvmclock_base_ns(); |
d828199e | 11101 | pvclock_update_vm_gtod_copy(kvm); |
53f658b3 | 11102 | |
6fbbde9a DS |
11103 | kvm->arch.guest_can_read_msr_platform_info = true; |
11104 | ||
3c86c0d3 VP |
11105 | #if IS_ENABLED(CONFIG_HYPERV) |
11106 | spin_lock_init(&kvm->arch.hv_root_tdp_lock); | |
11107 | kvm->arch.hv_root_tdp = INVALID_PAGE; | |
11108 | #endif | |
11109 | ||
7e44e449 | 11110 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); |
332967a3 | 11111 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); |
7e44e449 | 11112 | |
4651fc56 | 11113 | kvm_apicv_init(kvm); |
cbc0236a | 11114 | kvm_hv_init_vm(kvm); |
0eb05bf2 | 11115 | kvm_page_track_init(kvm); |
13d268ca | 11116 | kvm_mmu_init_vm(kvm); |
0eb05bf2 | 11117 | |
b3646477 | 11118 | return static_call(kvm_x86_vm_init)(kvm); |
d19a9cd2 ZX |
11119 | } |
11120 | ||
1aa9b957 JS |
11121 | int kvm_arch_post_init_vm(struct kvm *kvm) |
11122 | { | |
11123 | return kvm_mmu_post_init_vm(kvm); | |
11124 | } | |
11125 | ||
d19a9cd2 ZX |
11126 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) |
11127 | { | |
ec7660cc | 11128 | vcpu_load(vcpu); |
d19a9cd2 ZX |
11129 | kvm_mmu_unload(vcpu); |
11130 | vcpu_put(vcpu); | |
11131 | } | |
11132 | ||
11133 | static void kvm_free_vcpus(struct kvm *kvm) | |
11134 | { | |
11135 | unsigned int i; | |
988a2cae | 11136 | struct kvm_vcpu *vcpu; |
d19a9cd2 ZX |
11137 | |
11138 | /* | |
11139 | * Unpin any mmu pages first. | |
11140 | */ | |
af585b92 GN |
11141 | kvm_for_each_vcpu(i, vcpu, kvm) { |
11142 | kvm_clear_async_pf_completion_queue(vcpu); | |
988a2cae | 11143 | kvm_unload_vcpu_mmu(vcpu); |
af585b92 | 11144 | } |
988a2cae | 11145 | kvm_for_each_vcpu(i, vcpu, kvm) |
4543bdc0 | 11146 | kvm_vcpu_destroy(vcpu); |
988a2cae GN |
11147 | |
11148 | mutex_lock(&kvm->lock); | |
11149 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
11150 | kvm->vcpus[i] = NULL; | |
d19a9cd2 | 11151 | |
988a2cae GN |
11152 | atomic_set(&kvm->online_vcpus, 0); |
11153 | mutex_unlock(&kvm->lock); | |
d19a9cd2 ZX |
11154 | } |
11155 | ||
ad8ba2cd SY |
11156 | void kvm_arch_sync_events(struct kvm *kvm) |
11157 | { | |
332967a3 | 11158 | cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); |
7e44e449 | 11159 | cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); |
aea924f6 | 11160 | kvm_free_pit(kvm); |
ad8ba2cd SY |
11161 | } |
11162 | ||
ff5a983c PX |
11163 | #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e)) |
11164 | ||
11165 | /** | |
11166 | * __x86_set_memory_region: Setup KVM internal memory slot | |
11167 | * | |
11168 | * @kvm: the kvm pointer to the VM. | |
11169 | * @id: the slot ID to setup. | |
11170 | * @gpa: the GPA to install the slot (unused when @size == 0). | |
11171 | * @size: the size of the slot. Set to zero to uninstall a slot. | |
11172 | * | |
11173 | * This function helps to setup a KVM internal memory slot. Specify | |
11174 | * @size > 0 to install a new slot, while @size == 0 to uninstall a | |
11175 | * slot. The return code can be one of the following: | |
11176 | * | |
11177 | * HVA: on success (uninstall will return a bogus HVA) | |
11178 | * -errno: on error | |
11179 | * | |
11180 | * The caller should always use IS_ERR() to check the return value | |
11181 | * before use. Note, the KVM internal memory slots are guaranteed to | |
11182 | * remain valid and unchanged until the VM is destroyed, i.e., the | |
11183 | * GPA->HVA translation will not change. However, the HVA is a user | |
11184 | * address, i.e. its accessibility is not guaranteed, and must be | |
11185 | * accessed via __copy_{to,from}_user(). | |
11186 | */ | |
11187 | void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, | |
11188 | u32 size) | |
9da0e4d5 PB |
11189 | { |
11190 | int i, r; | |
3f649ab7 | 11191 | unsigned long hva, old_npages; |
f0d648bd | 11192 | struct kvm_memslots *slots = kvm_memslots(kvm); |
0577d1ab | 11193 | struct kvm_memory_slot *slot; |
9da0e4d5 PB |
11194 | |
11195 | /* Called with kvm->slots_lock held. */ | |
1d8007bd | 11196 | if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) |
ff5a983c | 11197 | return ERR_PTR_USR(-EINVAL); |
9da0e4d5 | 11198 | |
f0d648bd PB |
11199 | slot = id_to_memslot(slots, id); |
11200 | if (size) { | |
0577d1ab | 11201 | if (slot && slot->npages) |
ff5a983c | 11202 | return ERR_PTR_USR(-EEXIST); |
f0d648bd PB |
11203 | |
11204 | /* | |
11205 | * MAP_SHARED to prevent internal slot pages from being moved | |
11206 | * by fork()/COW. | |
11207 | */ | |
11208 | hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, | |
11209 | MAP_SHARED | MAP_ANONYMOUS, 0); | |
11210 | if (IS_ERR((void *)hva)) | |
ff5a983c | 11211 | return (void __user *)hva; |
f0d648bd | 11212 | } else { |
0577d1ab | 11213 | if (!slot || !slot->npages) |
46914534 | 11214 | return NULL; |
f0d648bd | 11215 | |
0577d1ab | 11216 | old_npages = slot->npages; |
b66f9bab | 11217 | hva = slot->userspace_addr; |
f0d648bd PB |
11218 | } |
11219 | ||
9da0e4d5 | 11220 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
1d8007bd | 11221 | struct kvm_userspace_memory_region m; |
9da0e4d5 | 11222 | |
1d8007bd PB |
11223 | m.slot = id | (i << 16); |
11224 | m.flags = 0; | |
11225 | m.guest_phys_addr = gpa; | |
f0d648bd | 11226 | m.userspace_addr = hva; |
1d8007bd | 11227 | m.memory_size = size; |
9da0e4d5 PB |
11228 | r = __kvm_set_memory_region(kvm, &m); |
11229 | if (r < 0) | |
ff5a983c | 11230 | return ERR_PTR_USR(r); |
9da0e4d5 PB |
11231 | } |
11232 | ||
103c763c | 11233 | if (!size) |
0577d1ab | 11234 | vm_munmap(hva, old_npages * PAGE_SIZE); |
f0d648bd | 11235 | |
ff5a983c | 11236 | return (void __user *)hva; |
9da0e4d5 PB |
11237 | } |
11238 | EXPORT_SYMBOL_GPL(__x86_set_memory_region); | |
11239 | ||
1aa9b957 JS |
11240 | void kvm_arch_pre_destroy_vm(struct kvm *kvm) |
11241 | { | |
11242 | kvm_mmu_pre_destroy_vm(kvm); | |
11243 | } | |
11244 | ||
d19a9cd2 ZX |
11245 | void kvm_arch_destroy_vm(struct kvm *kvm) |
11246 | { | |
27469d29 AH |
11247 | if (current->mm == kvm->mm) { |
11248 | /* | |
11249 | * Free memory regions allocated on behalf of userspace, | |
11250 | * unless the the memory map has changed due to process exit | |
11251 | * or fd copying. | |
11252 | */ | |
6a3c623b PX |
11253 | mutex_lock(&kvm->slots_lock); |
11254 | __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, | |
11255 | 0, 0); | |
11256 | __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, | |
11257 | 0, 0); | |
11258 | __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); | |
11259 | mutex_unlock(&kvm->slots_lock); | |
27469d29 | 11260 | } |
b3646477 | 11261 | static_call_cond(kvm_x86_vm_destroy)(kvm); |
b318e8de | 11262 | kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1)); |
c761159c PX |
11263 | kvm_pic_destroy(kvm); |
11264 | kvm_ioapic_destroy(kvm); | |
d19a9cd2 | 11265 | kvm_free_vcpus(kvm); |
af1bae54 | 11266 | kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); |
66bb8a06 | 11267 | kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); |
13d268ca | 11268 | kvm_mmu_uninit_vm(kvm); |
2beb6dad | 11269 | kvm_page_track_cleanup(kvm); |
7d6bbebb | 11270 | kvm_xen_destroy_vm(kvm); |
cbc0236a | 11271 | kvm_hv_destroy_vm(kvm); |
d19a9cd2 | 11272 | } |
0de10343 | 11273 | |
c9b929b3 | 11274 | static void memslot_rmap_free(struct kvm_memory_slot *slot) |
db3fe4eb TY |
11275 | { |
11276 | int i; | |
11277 | ||
d89cc617 | 11278 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
e96c81ee SC |
11279 | kvfree(slot->arch.rmap[i]); |
11280 | slot->arch.rmap[i] = NULL; | |
c9b929b3 BG |
11281 | } |
11282 | } | |
e96c81ee | 11283 | |
c9b929b3 BG |
11284 | void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) |
11285 | { | |
11286 | int i; | |
11287 | ||
11288 | memslot_rmap_free(slot); | |
d89cc617 | 11289 | |
c9b929b3 | 11290 | for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { |
e96c81ee SC |
11291 | kvfree(slot->arch.lpage_info[i - 1]); |
11292 | slot->arch.lpage_info[i - 1] = NULL; | |
db3fe4eb | 11293 | } |
21ebbeda | 11294 | |
e96c81ee | 11295 | kvm_page_track_free_memslot(slot); |
db3fe4eb TY |
11296 | } |
11297 | ||
56dd1019 BG |
11298 | static int memslot_rmap_alloc(struct kvm_memory_slot *slot, |
11299 | unsigned long npages) | |
11300 | { | |
11301 | const int sz = sizeof(*slot->arch.rmap[0]); | |
11302 | int i; | |
11303 | ||
11304 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { | |
11305 | int level = i + 1; | |
11306 | int lpages = gfn_to_index(slot->base_gfn + npages - 1, | |
11307 | slot->base_gfn, level) + 1; | |
11308 | ||
d501f747 BG |
11309 | WARN_ON(slot->arch.rmap[i]); |
11310 | ||
56dd1019 BG |
11311 | slot->arch.rmap[i] = kvcalloc(lpages, sz, GFP_KERNEL_ACCOUNT); |
11312 | if (!slot->arch.rmap[i]) { | |
11313 | memslot_rmap_free(slot); | |
11314 | return -ENOMEM; | |
11315 | } | |
11316 | } | |
11317 | ||
11318 | return 0; | |
11319 | } | |
11320 | ||
d501f747 BG |
11321 | int alloc_all_memslots_rmaps(struct kvm *kvm) |
11322 | { | |
11323 | struct kvm_memslots *slots; | |
11324 | struct kvm_memory_slot *slot; | |
11325 | int r, i; | |
11326 | ||
11327 | /* | |
11328 | * Check if memslots alreday have rmaps early before acquiring | |
11329 | * the slots_arch_lock below. | |
11330 | */ | |
11331 | if (kvm_memslots_have_rmaps(kvm)) | |
11332 | return 0; | |
11333 | ||
11334 | mutex_lock(&kvm->slots_arch_lock); | |
11335 | ||
11336 | /* | |
11337 | * Read memslots_have_rmaps again, under the slots arch lock, | |
11338 | * before allocating the rmaps | |
11339 | */ | |
11340 | if (kvm_memslots_have_rmaps(kvm)) { | |
11341 | mutex_unlock(&kvm->slots_arch_lock); | |
11342 | return 0; | |
11343 | } | |
11344 | ||
11345 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { | |
11346 | slots = __kvm_memslots(kvm, i); | |
11347 | kvm_for_each_memslot(slot, slots) { | |
11348 | r = memslot_rmap_alloc(slot, slot->npages); | |
11349 | if (r) { | |
11350 | mutex_unlock(&kvm->slots_arch_lock); | |
11351 | return r; | |
11352 | } | |
11353 | } | |
11354 | } | |
11355 | ||
11356 | /* | |
11357 | * Ensure that memslots_have_rmaps becomes true strictly after | |
11358 | * all the rmap pointers are set. | |
11359 | */ | |
11360 | smp_store_release(&kvm->arch.memslots_have_rmaps, true); | |
11361 | mutex_unlock(&kvm->slots_arch_lock); | |
11362 | return 0; | |
11363 | } | |
11364 | ||
a2557408 BG |
11365 | static int kvm_alloc_memslot_metadata(struct kvm *kvm, |
11366 | struct kvm_memory_slot *slot, | |
0dab98b7 | 11367 | unsigned long npages) |
db3fe4eb | 11368 | { |
56dd1019 | 11369 | int i, r; |
db3fe4eb | 11370 | |
edd4fa37 SC |
11371 | /* |
11372 | * Clear out the previous array pointers for the KVM_MR_MOVE case. The | |
11373 | * old arrays will be freed by __kvm_set_memory_region() if installing | |
11374 | * the new memslot is successful. | |
11375 | */ | |
11376 | memset(&slot->arch, 0, sizeof(slot->arch)); | |
11377 | ||
e2209710 | 11378 | if (kvm_memslots_have_rmaps(kvm)) { |
a2557408 BG |
11379 | r = memslot_rmap_alloc(slot, npages); |
11380 | if (r) | |
11381 | return r; | |
11382 | } | |
56dd1019 BG |
11383 | |
11384 | for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { | |
92f94f1e | 11385 | struct kvm_lpage_info *linfo; |
db3fe4eb TY |
11386 | unsigned long ugfn; |
11387 | int lpages; | |
d89cc617 | 11388 | int level = i + 1; |
db3fe4eb TY |
11389 | |
11390 | lpages = gfn_to_index(slot->base_gfn + npages - 1, | |
11391 | slot->base_gfn, level) + 1; | |
11392 | ||
254272ce | 11393 | linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); |
92f94f1e | 11394 | if (!linfo) |
db3fe4eb TY |
11395 | goto out_free; |
11396 | ||
92f94f1e XG |
11397 | slot->arch.lpage_info[i - 1] = linfo; |
11398 | ||
db3fe4eb | 11399 | if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 11400 | linfo[0].disallow_lpage = 1; |
db3fe4eb | 11401 | if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 11402 | linfo[lpages - 1].disallow_lpage = 1; |
db3fe4eb TY |
11403 | ugfn = slot->userspace_addr >> PAGE_SHIFT; |
11404 | /* | |
11405 | * If the gfn and userspace address are not aligned wrt each | |
600087b6 | 11406 | * other, disable large page support for this slot. |
db3fe4eb | 11407 | */ |
600087b6 | 11408 | if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) { |
db3fe4eb TY |
11409 | unsigned long j; |
11410 | ||
11411 | for (j = 0; j < lpages; ++j) | |
92f94f1e | 11412 | linfo[j].disallow_lpage = 1; |
db3fe4eb TY |
11413 | } |
11414 | } | |
11415 | ||
21ebbeda XG |
11416 | if (kvm_page_track_create_memslot(slot, npages)) |
11417 | goto out_free; | |
11418 | ||
db3fe4eb TY |
11419 | return 0; |
11420 | ||
11421 | out_free: | |
c9b929b3 | 11422 | memslot_rmap_free(slot); |
d89cc617 | 11423 | |
c9b929b3 | 11424 | for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { |
548ef284 | 11425 | kvfree(slot->arch.lpage_info[i - 1]); |
d89cc617 | 11426 | slot->arch.lpage_info[i - 1] = NULL; |
db3fe4eb TY |
11427 | } |
11428 | return -ENOMEM; | |
11429 | } | |
11430 | ||
15248258 | 11431 | void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) |
e59dbe09 | 11432 | { |
91724814 BO |
11433 | struct kvm_vcpu *vcpu; |
11434 | int i; | |
11435 | ||
e6dff7d1 TY |
11436 | /* |
11437 | * memslots->generation has been incremented. | |
11438 | * mmio generation may have reached its maximum value. | |
11439 | */ | |
15248258 | 11440 | kvm_mmu_invalidate_mmio_sptes(kvm, gen); |
91724814 BO |
11441 | |
11442 | /* Force re-initialization of steal_time cache */ | |
11443 | kvm_for_each_vcpu(i, vcpu, kvm) | |
11444 | kvm_vcpu_kick(vcpu); | |
e59dbe09 TY |
11445 | } |
11446 | ||
f7784b8e MT |
11447 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
11448 | struct kvm_memory_slot *memslot, | |
09170a49 | 11449 | const struct kvm_userspace_memory_region *mem, |
7b6195a9 | 11450 | enum kvm_mr_change change) |
0de10343 | 11451 | { |
0dab98b7 | 11452 | if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) |
a2557408 | 11453 | return kvm_alloc_memslot_metadata(kvm, memslot, |
0dab98b7 | 11454 | mem->memory_size >> PAGE_SHIFT); |
f7784b8e MT |
11455 | return 0; |
11456 | } | |
11457 | ||
a85863c2 MS |
11458 | |
11459 | static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable) | |
11460 | { | |
11461 | struct kvm_arch *ka = &kvm->arch; | |
11462 | ||
11463 | if (!kvm_x86_ops.cpu_dirty_log_size) | |
11464 | return; | |
11465 | ||
11466 | if ((enable && ++ka->cpu_dirty_logging_count == 1) || | |
11467 | (!enable && --ka->cpu_dirty_logging_count == 0)) | |
11468 | kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING); | |
11469 | ||
11470 | WARN_ON_ONCE(ka->cpu_dirty_logging_count < 0); | |
11471 | } | |
11472 | ||
88178fd4 | 11473 | static void kvm_mmu_slot_apply_flags(struct kvm *kvm, |
3741679b AY |
11474 | struct kvm_memory_slot *old, |
11475 | struct kvm_memory_slot *new, | |
11476 | enum kvm_mr_change change) | |
88178fd4 | 11477 | { |
a85863c2 MS |
11478 | bool log_dirty_pages = new->flags & KVM_MEM_LOG_DIRTY_PAGES; |
11479 | ||
3741679b | 11480 | /* |
a85863c2 MS |
11481 | * Update CPU dirty logging if dirty logging is being toggled. This |
11482 | * applies to all operations. | |
3741679b | 11483 | */ |
a85863c2 MS |
11484 | if ((old->flags ^ new->flags) & KVM_MEM_LOG_DIRTY_PAGES) |
11485 | kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages); | |
88178fd4 KH |
11486 | |
11487 | /* | |
a85863c2 | 11488 | * Nothing more to do for RO slots (which can't be dirtied and can't be |
b6e16ae5 | 11489 | * made writable) or CREATE/MOVE/DELETE of a slot. |
88178fd4 | 11490 | * |
b6e16ae5 | 11491 | * For a memslot with dirty logging disabled: |
3741679b AY |
11492 | * CREATE: No dirty mappings will already exist. |
11493 | * MOVE/DELETE: The old mappings will already have been cleaned up by | |
11494 | * kvm_arch_flush_shadow_memslot() | |
b6e16ae5 SC |
11495 | * |
11496 | * For a memslot with dirty logging enabled: | |
11497 | * CREATE: No shadow pages exist, thus nothing to write-protect | |
11498 | * and no dirty bits to clear. | |
11499 | * MOVE/DELETE: The old mappings will already have been cleaned up by | |
11500 | * kvm_arch_flush_shadow_memslot(). | |
3741679b | 11501 | */ |
3741679b | 11502 | if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY)) |
88178fd4 | 11503 | return; |
3741679b AY |
11504 | |
11505 | /* | |
52f46079 SC |
11506 | * READONLY and non-flags changes were filtered out above, and the only |
11507 | * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty | |
11508 | * logging isn't being toggled on or off. | |
88178fd4 | 11509 | */ |
52f46079 SC |
11510 | if (WARN_ON_ONCE(!((old->flags ^ new->flags) & KVM_MEM_LOG_DIRTY_PAGES))) |
11511 | return; | |
11512 | ||
b6e16ae5 SC |
11513 | if (!log_dirty_pages) { |
11514 | /* | |
11515 | * Dirty logging tracks sptes in 4k granularity, meaning that | |
11516 | * large sptes have to be split. If live migration succeeds, | |
11517 | * the guest in the source machine will be destroyed and large | |
11518 | * sptes will be created in the destination. However, if the | |
11519 | * guest continues to run in the source machine (for example if | |
11520 | * live migration fails), small sptes will remain around and | |
11521 | * cause bad performance. | |
11522 | * | |
11523 | * Scan sptes if dirty logging has been stopped, dropping those | |
11524 | * which can be collapsed into a single large-page spte. Later | |
11525 | * page faults will create the large-page sptes. | |
11526 | */ | |
3741679b | 11527 | kvm_mmu_zap_collapsible_sptes(kvm, new); |
b6e16ae5 | 11528 | } else { |
89212919 KZ |
11529 | /* |
11530 | * Initially-all-set does not require write protecting any page, | |
11531 | * because they're all assumed to be dirty. | |
11532 | */ | |
11533 | if (kvm_dirty_log_manual_protect_and_init_set(kvm)) | |
11534 | return; | |
a1419f8b | 11535 | |
a018eba5 | 11536 | if (kvm_x86_ops.cpu_dirty_log_size) { |
89212919 KZ |
11537 | kvm_mmu_slot_leaf_clear_dirty(kvm, new); |
11538 | kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M); | |
11539 | } else { | |
11540 | kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K); | |
3c9bd400 | 11541 | } |
88178fd4 KH |
11542 | } |
11543 | } | |
11544 | ||
f7784b8e | 11545 | void kvm_arch_commit_memory_region(struct kvm *kvm, |
09170a49 | 11546 | const struct kvm_userspace_memory_region *mem, |
9d4c197c | 11547 | struct kvm_memory_slot *old, |
f36f3f28 | 11548 | const struct kvm_memory_slot *new, |
8482644a | 11549 | enum kvm_mr_change change) |
f7784b8e | 11550 | { |
48c0e4e9 | 11551 | if (!kvm->arch.n_requested_mmu_pages) |
4d66623c WY |
11552 | kvm_mmu_change_mmu_pages(kvm, |
11553 | kvm_mmu_calculate_default_mmu_pages(kvm)); | |
1c91cad4 | 11554 | |
3ea3b7fa | 11555 | /* |
f36f3f28 | 11556 | * FIXME: const-ify all uses of struct kvm_memory_slot. |
c972f3b1 | 11557 | */ |
3741679b | 11558 | kvm_mmu_slot_apply_flags(kvm, old, (struct kvm_memory_slot *) new, change); |
21198846 SC |
11559 | |
11560 | /* Free the arrays associated with the old memslot. */ | |
11561 | if (change == KVM_MR_MOVE) | |
e96c81ee | 11562 | kvm_arch_free_memslot(kvm, old); |
0de10343 | 11563 | } |
1d737c8a | 11564 | |
2df72e9b | 11565 | void kvm_arch_flush_shadow_all(struct kvm *kvm) |
34d4cb8f | 11566 | { |
7390de1e | 11567 | kvm_mmu_zap_all(kvm); |
34d4cb8f MT |
11568 | } |
11569 | ||
2df72e9b MT |
11570 | void kvm_arch_flush_shadow_memslot(struct kvm *kvm, |
11571 | struct kvm_memory_slot *slot) | |
11572 | { | |
ae7cd873 | 11573 | kvm_page_track_flush_slot(kvm, slot); |
2df72e9b MT |
11574 | } |
11575 | ||
e6c67d8c LA |
11576 | static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) |
11577 | { | |
11578 | return (is_guest_mode(vcpu) && | |
afaf0b2f | 11579 | kvm_x86_ops.guest_apic_has_interrupt && |
b3646477 | 11580 | static_call(kvm_x86_guest_apic_has_interrupt)(vcpu)); |
e6c67d8c LA |
11581 | } |
11582 | ||
5d9bc648 PB |
11583 | static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) |
11584 | { | |
11585 | if (!list_empty_careful(&vcpu->async_pf.done)) | |
11586 | return true; | |
11587 | ||
11588 | if (kvm_apic_has_events(vcpu)) | |
11589 | return true; | |
11590 | ||
11591 | if (vcpu->arch.pv.pv_unhalted) | |
11592 | return true; | |
11593 | ||
a5f01f8e WL |
11594 | if (vcpu->arch.exception.pending) |
11595 | return true; | |
11596 | ||
47a66eed Z |
11597 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || |
11598 | (vcpu->arch.nmi_pending && | |
b3646477 | 11599 | static_call(kvm_x86_nmi_allowed)(vcpu, false))) |
5d9bc648 PB |
11600 | return true; |
11601 | ||
47a66eed | 11602 | if (kvm_test_request(KVM_REQ_SMI, vcpu) || |
a9fa7cb6 | 11603 | (vcpu->arch.smi_pending && |
b3646477 | 11604 | static_call(kvm_x86_smi_allowed)(vcpu, false))) |
73917739 PB |
11605 | return true; |
11606 | ||
5d9bc648 | 11607 | if (kvm_arch_interrupt_allowed(vcpu) && |
e6c67d8c LA |
11608 | (kvm_cpu_has_interrupt(vcpu) || |
11609 | kvm_guest_apic_has_interrupt(vcpu))) | |
5d9bc648 PB |
11610 | return true; |
11611 | ||
1f4b34f8 AS |
11612 | if (kvm_hv_has_stimer_pending(vcpu)) |
11613 | return true; | |
11614 | ||
d2060bd4 SC |
11615 | if (is_guest_mode(vcpu) && |
11616 | kvm_x86_ops.nested_ops->hv_timer_pending && | |
11617 | kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) | |
11618 | return true; | |
11619 | ||
5d9bc648 PB |
11620 | return false; |
11621 | } | |
11622 | ||
1d737c8a ZX |
11623 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
11624 | { | |
5d9bc648 | 11625 | return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); |
1d737c8a | 11626 | } |
5736199a | 11627 | |
10dbdf98 | 11628 | bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu) |
17e433b5 | 11629 | { |
b3646477 | 11630 | if (vcpu->arch.apicv_active && static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu)) |
52acd22f WL |
11631 | return true; |
11632 | ||
11633 | return false; | |
11634 | } | |
11635 | ||
17e433b5 WL |
11636 | bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) |
11637 | { | |
11638 | if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) | |
11639 | return true; | |
11640 | ||
11641 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || | |
11642 | kvm_test_request(KVM_REQ_SMI, vcpu) || | |
11643 | kvm_test_request(KVM_REQ_EVENT, vcpu)) | |
11644 | return true; | |
11645 | ||
10dbdf98 | 11646 | return kvm_arch_dy_has_pending_interrupt(vcpu); |
17e433b5 WL |
11647 | } |
11648 | ||
199b5763 LM |
11649 | bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) |
11650 | { | |
b86bb11e WL |
11651 | if (vcpu->arch.guest_state_protected) |
11652 | return true; | |
11653 | ||
de63ad4c | 11654 | return vcpu->arch.preempted_in_kernel; |
199b5763 LM |
11655 | } |
11656 | ||
b6d33834 | 11657 | int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) |
5736199a | 11658 | { |
b6d33834 | 11659 | return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; |
5736199a | 11660 | } |
78646121 GN |
11661 | |
11662 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
11663 | { | |
b3646477 | 11664 | return static_call(kvm_x86_interrupt_allowed)(vcpu, false); |
78646121 | 11665 | } |
229456fc | 11666 | |
82b32774 | 11667 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) |
f92653ee | 11668 | { |
7ed9abfe TL |
11669 | /* Can't read the RIP when guest state is protected, just return 0 */ |
11670 | if (vcpu->arch.guest_state_protected) | |
11671 | return 0; | |
11672 | ||
82b32774 NA |
11673 | if (is_64_bit_mode(vcpu)) |
11674 | return kvm_rip_read(vcpu); | |
11675 | return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + | |
11676 | kvm_rip_read(vcpu)); | |
11677 | } | |
11678 | EXPORT_SYMBOL_GPL(kvm_get_linear_rip); | |
f92653ee | 11679 | |
82b32774 NA |
11680 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) |
11681 | { | |
11682 | return kvm_get_linear_rip(vcpu) == linear_rip; | |
f92653ee JK |
11683 | } |
11684 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
11685 | ||
94fe45da JK |
11686 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
11687 | { | |
11688 | unsigned long rflags; | |
11689 | ||
b3646477 | 11690 | rflags = static_call(kvm_x86_get_rflags)(vcpu); |
94fe45da | 11691 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
c310bac5 | 11692 | rflags &= ~X86_EFLAGS_TF; |
94fe45da JK |
11693 | return rflags; |
11694 | } | |
11695 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
11696 | ||
6addfc42 | 11697 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) |
94fe45da JK |
11698 | { |
11699 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
f92653ee | 11700 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) |
c310bac5 | 11701 | rflags |= X86_EFLAGS_TF; |
b3646477 | 11702 | static_call(kvm_x86_set_rflags)(vcpu, rflags); |
6addfc42 PB |
11703 | } |
11704 | ||
11705 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
11706 | { | |
11707 | __kvm_set_rflags(vcpu, rflags); | |
3842d135 | 11708 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
94fe45da JK |
11709 | } |
11710 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
11711 | ||
56028d08 GN |
11712 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) |
11713 | { | |
11714 | int r; | |
11715 | ||
44dd3ffa | 11716 | if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) || |
f2e10669 | 11717 | work->wakeup_all) |
56028d08 GN |
11718 | return; |
11719 | ||
11720 | r = kvm_mmu_reload(vcpu); | |
11721 | if (unlikely(r)) | |
11722 | return; | |
11723 | ||
44dd3ffa | 11724 | if (!vcpu->arch.mmu->direct_map && |
d8dd54e0 | 11725 | work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu)) |
fb67e14f XG |
11726 | return; |
11727 | ||
7a02674d | 11728 | kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true); |
56028d08 GN |
11729 | } |
11730 | ||
af585b92 GN |
11731 | static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) |
11732 | { | |
dd03bcaa PX |
11733 | BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU)); |
11734 | ||
af585b92 GN |
11735 | return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); |
11736 | } | |
11737 | ||
11738 | static inline u32 kvm_async_pf_next_probe(u32 key) | |
11739 | { | |
dd03bcaa | 11740 | return (key + 1) & (ASYNC_PF_PER_VCPU - 1); |
af585b92 GN |
11741 | } |
11742 | ||
11743 | static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
11744 | { | |
11745 | u32 key = kvm_async_pf_hash_fn(gfn); | |
11746 | ||
11747 | while (vcpu->arch.apf.gfns[key] != ~0) | |
11748 | key = kvm_async_pf_next_probe(key); | |
11749 | ||
11750 | vcpu->arch.apf.gfns[key] = gfn; | |
11751 | } | |
11752 | ||
11753 | static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) | |
11754 | { | |
11755 | int i; | |
11756 | u32 key = kvm_async_pf_hash_fn(gfn); | |
11757 | ||
dd03bcaa | 11758 | for (i = 0; i < ASYNC_PF_PER_VCPU && |
c7d28c24 XG |
11759 | (vcpu->arch.apf.gfns[key] != gfn && |
11760 | vcpu->arch.apf.gfns[key] != ~0); i++) | |
af585b92 GN |
11761 | key = kvm_async_pf_next_probe(key); |
11762 | ||
11763 | return key; | |
11764 | } | |
11765 | ||
11766 | bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
11767 | { | |
11768 | return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; | |
11769 | } | |
11770 | ||
11771 | static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
11772 | { | |
11773 | u32 i, j, k; | |
11774 | ||
11775 | i = j = kvm_async_pf_gfn_slot(vcpu, gfn); | |
0fd46044 PX |
11776 | |
11777 | if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn)) | |
11778 | return; | |
11779 | ||
af585b92 GN |
11780 | while (true) { |
11781 | vcpu->arch.apf.gfns[i] = ~0; | |
11782 | do { | |
11783 | j = kvm_async_pf_next_probe(j); | |
11784 | if (vcpu->arch.apf.gfns[j] == ~0) | |
11785 | return; | |
11786 | k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); | |
11787 | /* | |
11788 | * k lies cyclically in ]i,j] | |
11789 | * | i.k.j | | |
11790 | * |....j i.k.| or |.k..j i...| | |
11791 | */ | |
11792 | } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); | |
11793 | vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; | |
11794 | i = j; | |
11795 | } | |
11796 | } | |
11797 | ||
68fd66f1 | 11798 | static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu) |
7c90705b | 11799 | { |
68fd66f1 VK |
11800 | u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT; |
11801 | ||
11802 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason, | |
11803 | sizeof(reason)); | |
11804 | } | |
11805 | ||
11806 | static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token) | |
11807 | { | |
2635b5c4 | 11808 | unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); |
4e335d9e | 11809 | |
2635b5c4 VK |
11810 | return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, |
11811 | &token, offset, sizeof(token)); | |
11812 | } | |
11813 | ||
11814 | static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu) | |
11815 | { | |
11816 | unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); | |
11817 | u32 val; | |
11818 | ||
11819 | if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, | |
11820 | &val, offset, sizeof(val))) | |
11821 | return false; | |
11822 | ||
11823 | return !val; | |
7c90705b GN |
11824 | } |
11825 | ||
1dfdb45e PB |
11826 | static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) |
11827 | { | |
11828 | if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu)) | |
11829 | return false; | |
11830 | ||
2635b5c4 | 11831 | if (!kvm_pv_async_pf_enabled(vcpu) || |
b3646477 | 11832 | (vcpu->arch.apf.send_user_only && static_call(kvm_x86_get_cpl)(vcpu) == 0)) |
1dfdb45e PB |
11833 | return false; |
11834 | ||
11835 | return true; | |
11836 | } | |
11837 | ||
11838 | bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) | |
11839 | { | |
11840 | if (unlikely(!lapic_in_kernel(vcpu) || | |
11841 | kvm_event_needs_reinjection(vcpu) || | |
11842 | vcpu->arch.exception.pending)) | |
11843 | return false; | |
11844 | ||
11845 | if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) | |
11846 | return false; | |
11847 | ||
11848 | /* | |
11849 | * If interrupts are off we cannot even use an artificial | |
11850 | * halt state. | |
11851 | */ | |
c300ab9f | 11852 | return kvm_arch_interrupt_allowed(vcpu); |
1dfdb45e PB |
11853 | } |
11854 | ||
2a18b7e7 | 11855 | bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
af585b92 GN |
11856 | struct kvm_async_pf *work) |
11857 | { | |
6389ee94 AK |
11858 | struct x86_exception fault; |
11859 | ||
736c291c | 11860 | trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa); |
af585b92 | 11861 | kvm_add_async_pf_gfn(vcpu, work->arch.gfn); |
7c90705b | 11862 | |
1dfdb45e | 11863 | if (kvm_can_deliver_async_pf(vcpu) && |
68fd66f1 | 11864 | !apf_put_user_notpresent(vcpu)) { |
6389ee94 AK |
11865 | fault.vector = PF_VECTOR; |
11866 | fault.error_code_valid = true; | |
11867 | fault.error_code = 0; | |
11868 | fault.nested_page_fault = false; | |
11869 | fault.address = work->arch.token; | |
adfe20fb | 11870 | fault.async_page_fault = true; |
6389ee94 | 11871 | kvm_inject_page_fault(vcpu, &fault); |
2a18b7e7 | 11872 | return true; |
1dfdb45e PB |
11873 | } else { |
11874 | /* | |
11875 | * It is not possible to deliver a paravirtualized asynchronous | |
11876 | * page fault, but putting the guest in an artificial halt state | |
11877 | * can be beneficial nevertheless: if an interrupt arrives, we | |
11878 | * can deliver it timely and perhaps the guest will schedule | |
11879 | * another process. When the instruction that triggered a page | |
11880 | * fault is retried, hopefully the page will be ready in the host. | |
11881 | */ | |
11882 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
2a18b7e7 | 11883 | return false; |
7c90705b | 11884 | } |
af585b92 GN |
11885 | } |
11886 | ||
11887 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
11888 | struct kvm_async_pf *work) | |
11889 | { | |
2635b5c4 VK |
11890 | struct kvm_lapic_irq irq = { |
11891 | .delivery_mode = APIC_DM_FIXED, | |
11892 | .vector = vcpu->arch.apf.vec | |
11893 | }; | |
6389ee94 | 11894 | |
f2e10669 | 11895 | if (work->wakeup_all) |
7c90705b GN |
11896 | work->arch.token = ~0; /* broadcast wakeup */ |
11897 | else | |
11898 | kvm_del_async_pf_gfn(vcpu, work->arch.gfn); | |
736c291c | 11899 | trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa); |
7c90705b | 11900 | |
2a18b7e7 VK |
11901 | if ((work->wakeup_all || work->notpresent_injected) && |
11902 | kvm_pv_async_pf_enabled(vcpu) && | |
557a961a VK |
11903 | !apf_put_user_ready(vcpu, work->arch.token)) { |
11904 | vcpu->arch.apf.pageready_pending = true; | |
2635b5c4 | 11905 | kvm_apic_set_irq(vcpu, &irq, NULL); |
557a961a | 11906 | } |
2635b5c4 | 11907 | |
e6d53e3b | 11908 | vcpu->arch.apf.halted = false; |
a4fa1635 | 11909 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
7c90705b GN |
11910 | } |
11911 | ||
557a961a VK |
11912 | void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu) |
11913 | { | |
11914 | kvm_make_request(KVM_REQ_APF_READY, vcpu); | |
11915 | if (!vcpu->arch.apf.pageready_pending) | |
11916 | kvm_vcpu_kick(vcpu); | |
11917 | } | |
11918 | ||
7c0ade6c | 11919 | bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu) |
7c90705b | 11920 | { |
2635b5c4 | 11921 | if (!kvm_pv_async_pf_enabled(vcpu)) |
7c90705b GN |
11922 | return true; |
11923 | else | |
2f15d027 | 11924 | return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu); |
af585b92 GN |
11925 | } |
11926 | ||
5544eb9b PB |
11927 | void kvm_arch_start_assignment(struct kvm *kvm) |
11928 | { | |
57ab8794 MT |
11929 | if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1) |
11930 | static_call_cond(kvm_x86_start_assignment)(kvm); | |
5544eb9b PB |
11931 | } |
11932 | EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); | |
11933 | ||
11934 | void kvm_arch_end_assignment(struct kvm *kvm) | |
11935 | { | |
11936 | atomic_dec(&kvm->arch.assigned_device_count); | |
11937 | } | |
11938 | EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); | |
11939 | ||
11940 | bool kvm_arch_has_assigned_device(struct kvm *kvm) | |
11941 | { | |
11942 | return atomic_read(&kvm->arch.assigned_device_count); | |
11943 | } | |
11944 | EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); | |
11945 | ||
e0f0bbc5 AW |
11946 | void kvm_arch_register_noncoherent_dma(struct kvm *kvm) |
11947 | { | |
11948 | atomic_inc(&kvm->arch.noncoherent_dma_count); | |
11949 | } | |
11950 | EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); | |
11951 | ||
11952 | void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) | |
11953 | { | |
11954 | atomic_dec(&kvm->arch.noncoherent_dma_count); | |
11955 | } | |
11956 | EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); | |
11957 | ||
11958 | bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) | |
11959 | { | |
11960 | return atomic_read(&kvm->arch.noncoherent_dma_count); | |
11961 | } | |
11962 | EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); | |
11963 | ||
14717e20 AW |
11964 | bool kvm_arch_has_irq_bypass(void) |
11965 | { | |
92735b1b | 11966 | return true; |
14717e20 AW |
11967 | } |
11968 | ||
87276880 FW |
11969 | int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, |
11970 | struct irq_bypass_producer *prod) | |
11971 | { | |
11972 | struct kvm_kernel_irqfd *irqfd = | |
11973 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
2edd9cb7 | 11974 | int ret; |
87276880 | 11975 | |
14717e20 | 11976 | irqfd->producer = prod; |
2edd9cb7 | 11977 | kvm_arch_start_assignment(irqfd->kvm); |
b3646477 | 11978 | ret = static_call(kvm_x86_update_pi_irte)(irqfd->kvm, |
2edd9cb7 ZL |
11979 | prod->irq, irqfd->gsi, 1); |
11980 | ||
11981 | if (ret) | |
11982 | kvm_arch_end_assignment(irqfd->kvm); | |
87276880 | 11983 | |
2edd9cb7 | 11984 | return ret; |
87276880 FW |
11985 | } |
11986 | ||
11987 | void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, | |
11988 | struct irq_bypass_producer *prod) | |
11989 | { | |
11990 | int ret; | |
11991 | struct kvm_kernel_irqfd *irqfd = | |
11992 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
11993 | ||
87276880 FW |
11994 | WARN_ON(irqfd->producer != prod); |
11995 | irqfd->producer = NULL; | |
11996 | ||
11997 | /* | |
11998 | * When producer of consumer is unregistered, we change back to | |
11999 | * remapped mode, so we can re-use the current implementation | |
bb3541f1 | 12000 | * when the irq is masked/disabled or the consumer side (KVM |
87276880 FW |
12001 | * int this case doesn't want to receive the interrupts. |
12002 | */ | |
b3646477 | 12003 | ret = static_call(kvm_x86_update_pi_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0); |
87276880 FW |
12004 | if (ret) |
12005 | printk(KERN_INFO "irq bypass consumer (token %p) unregistration" | |
12006 | " fails: %d\n", irqfd->consumer.token, ret); | |
2edd9cb7 ZL |
12007 | |
12008 | kvm_arch_end_assignment(irqfd->kvm); | |
87276880 FW |
12009 | } |
12010 | ||
12011 | int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, | |
12012 | uint32_t guest_irq, bool set) | |
12013 | { | |
b3646477 | 12014 | return static_call(kvm_x86_update_pi_irte)(kvm, host_irq, guest_irq, set); |
87276880 FW |
12015 | } |
12016 | ||
52004014 FW |
12017 | bool kvm_vector_hashing_enabled(void) |
12018 | { | |
12019 | return vector_hashing; | |
12020 | } | |
52004014 | 12021 | |
2d5ba19b MT |
12022 | bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) |
12023 | { | |
12024 | return (vcpu->arch.msr_kvm_poll_control & 1) == 0; | |
12025 | } | |
12026 | EXPORT_SYMBOL_GPL(kvm_arch_no_poll); | |
12027 | ||
841c2be0 ML |
12028 | |
12029 | int kvm_spec_ctrl_test_value(u64 value) | |
6441fa61 | 12030 | { |
841c2be0 ML |
12031 | /* |
12032 | * test that setting IA32_SPEC_CTRL to given value | |
12033 | * is allowed by the host processor | |
12034 | */ | |
6441fa61 | 12035 | |
841c2be0 ML |
12036 | u64 saved_value; |
12037 | unsigned long flags; | |
12038 | int ret = 0; | |
6441fa61 | 12039 | |
841c2be0 | 12040 | local_irq_save(flags); |
6441fa61 | 12041 | |
841c2be0 ML |
12042 | if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value)) |
12043 | ret = 1; | |
12044 | else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value)) | |
12045 | ret = 1; | |
12046 | else | |
12047 | wrmsrl(MSR_IA32_SPEC_CTRL, saved_value); | |
6441fa61 | 12048 | |
841c2be0 | 12049 | local_irq_restore(flags); |
6441fa61 | 12050 | |
841c2be0 | 12051 | return ret; |
6441fa61 | 12052 | } |
841c2be0 | 12053 | EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value); |
2d5ba19b | 12054 | |
89786147 MG |
12055 | void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code) |
12056 | { | |
12057 | struct x86_exception fault; | |
19cf4b7e PB |
12058 | u32 access = error_code & |
12059 | (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK); | |
89786147 MG |
12060 | |
12061 | if (!(error_code & PFERR_PRESENT_MASK) || | |
19cf4b7e | 12062 | vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, &fault) != UNMAPPED_GVA) { |
89786147 MG |
12063 | /* |
12064 | * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page | |
12065 | * tables probably do not match the TLB. Just proceed | |
12066 | * with the error code that the processor gave. | |
12067 | */ | |
12068 | fault.vector = PF_VECTOR; | |
12069 | fault.error_code_valid = true; | |
12070 | fault.error_code = error_code; | |
12071 | fault.nested_page_fault = false; | |
12072 | fault.address = gva; | |
12073 | } | |
12074 | vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault); | |
6441fa61 | 12075 | } |
89786147 | 12076 | EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error); |
2d5ba19b | 12077 | |
3f3393b3 BM |
12078 | /* |
12079 | * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns | |
12080 | * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value | |
12081 | * indicates whether exit to userspace is needed. | |
12082 | */ | |
12083 | int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, | |
12084 | struct x86_exception *e) | |
12085 | { | |
12086 | if (r == X86EMUL_PROPAGATE_FAULT) { | |
12087 | kvm_inject_emulated_page_fault(vcpu, e); | |
12088 | return 1; | |
12089 | } | |
12090 | ||
12091 | /* | |
12092 | * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED | |
12093 | * while handling a VMX instruction KVM could've handled the request | |
12094 | * correctly by exiting to userspace and performing I/O but there | |
12095 | * doesn't seem to be a real use-case behind such requests, just return | |
12096 | * KVM_EXIT_INTERNAL_ERROR for now. | |
12097 | */ | |
12098 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
12099 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
12100 | vcpu->run->internal.ndata = 0; | |
12101 | ||
12102 | return 0; | |
12103 | } | |
12104 | EXPORT_SYMBOL_GPL(kvm_handle_memory_failure); | |
12105 | ||
9715092f BM |
12106 | int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva) |
12107 | { | |
12108 | bool pcid_enabled; | |
12109 | struct x86_exception e; | |
9715092f BM |
12110 | struct { |
12111 | u64 pcid; | |
12112 | u64 gla; | |
12113 | } operand; | |
12114 | int r; | |
12115 | ||
12116 | r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); | |
12117 | if (r != X86EMUL_CONTINUE) | |
12118 | return kvm_handle_memory_failure(vcpu, r, &e); | |
12119 | ||
12120 | if (operand.pcid >> 12 != 0) { | |
12121 | kvm_inject_gp(vcpu, 0); | |
12122 | return 1; | |
12123 | } | |
12124 | ||
12125 | pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); | |
12126 | ||
12127 | switch (type) { | |
12128 | case INVPCID_TYPE_INDIV_ADDR: | |
12129 | if ((!pcid_enabled && (operand.pcid != 0)) || | |
12130 | is_noncanonical_address(operand.gla, vcpu)) { | |
12131 | kvm_inject_gp(vcpu, 0); | |
12132 | return 1; | |
12133 | } | |
12134 | kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); | |
12135 | return kvm_skip_emulated_instruction(vcpu); | |
12136 | ||
12137 | case INVPCID_TYPE_SINGLE_CTXT: | |
12138 | if (!pcid_enabled && (operand.pcid != 0)) { | |
12139 | kvm_inject_gp(vcpu, 0); | |
12140 | return 1; | |
12141 | } | |
12142 | ||
21823fbd | 12143 | kvm_invalidate_pcid(vcpu, operand.pcid); |
9715092f BM |
12144 | return kvm_skip_emulated_instruction(vcpu); |
12145 | ||
12146 | case INVPCID_TYPE_ALL_NON_GLOBAL: | |
12147 | /* | |
12148 | * Currently, KVM doesn't mark global entries in the shadow | |
12149 | * page tables, so a non-global flush just degenerates to a | |
12150 | * global flush. If needed, we could optimize this later by | |
12151 | * keeping track of global entries in shadow page tables. | |
12152 | */ | |
12153 | ||
12154 | fallthrough; | |
12155 | case INVPCID_TYPE_ALL_INCL_GLOBAL: | |
28f28d45 | 12156 | kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); |
9715092f BM |
12157 | return kvm_skip_emulated_instruction(vcpu); |
12158 | ||
12159 | default: | |
12160 | BUG(); /* We have already checked above that type <= 3 */ | |
12161 | } | |
12162 | } | |
12163 | EXPORT_SYMBOL_GPL(kvm_handle_invpcid); | |
12164 | ||
8f423a80 TL |
12165 | static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu) |
12166 | { | |
12167 | struct kvm_run *run = vcpu->run; | |
12168 | struct kvm_mmio_fragment *frag; | |
12169 | unsigned int len; | |
12170 | ||
12171 | BUG_ON(!vcpu->mmio_needed); | |
12172 | ||
12173 | /* Complete previous fragment */ | |
12174 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; | |
12175 | len = min(8u, frag->len); | |
12176 | if (!vcpu->mmio_is_write) | |
12177 | memcpy(frag->data, run->mmio.data, len); | |
12178 | ||
12179 | if (frag->len <= 8) { | |
12180 | /* Switch to the next fragment. */ | |
12181 | frag++; | |
12182 | vcpu->mmio_cur_fragment++; | |
12183 | } else { | |
12184 | /* Go forward to the next mmio piece. */ | |
12185 | frag->data += len; | |
12186 | frag->gpa += len; | |
12187 | frag->len -= len; | |
12188 | } | |
12189 | ||
12190 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { | |
12191 | vcpu->mmio_needed = 0; | |
12192 | ||
12193 | // VMG change, at this point, we're always done | |
12194 | // RIP has already been advanced | |
12195 | return 1; | |
12196 | } | |
12197 | ||
12198 | // More MMIO is needed | |
12199 | run->mmio.phys_addr = frag->gpa; | |
12200 | run->mmio.len = min(8u, frag->len); | |
12201 | run->mmio.is_write = vcpu->mmio_is_write; | |
12202 | if (run->mmio.is_write) | |
12203 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); | |
12204 | run->exit_reason = KVM_EXIT_MMIO; | |
12205 | ||
12206 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
12207 | ||
12208 | return 0; | |
12209 | } | |
12210 | ||
12211 | int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, | |
12212 | void *data) | |
12213 | { | |
12214 | int handled; | |
12215 | struct kvm_mmio_fragment *frag; | |
12216 | ||
12217 | if (!data) | |
12218 | return -EINVAL; | |
12219 | ||
12220 | handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data); | |
12221 | if (handled == bytes) | |
12222 | return 1; | |
12223 | ||
12224 | bytes -= handled; | |
12225 | gpa += handled; | |
12226 | data += handled; | |
12227 | ||
12228 | /*TODO: Check if need to increment number of frags */ | |
12229 | frag = vcpu->mmio_fragments; | |
12230 | vcpu->mmio_nr_fragments = 1; | |
12231 | frag->len = bytes; | |
12232 | frag->gpa = gpa; | |
12233 | frag->data = data; | |
12234 | ||
12235 | vcpu->mmio_needed = 1; | |
12236 | vcpu->mmio_cur_fragment = 0; | |
12237 | ||
12238 | vcpu->run->mmio.phys_addr = gpa; | |
12239 | vcpu->run->mmio.len = min(8u, frag->len); | |
12240 | vcpu->run->mmio.is_write = 1; | |
12241 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); | |
12242 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
12243 | ||
12244 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
12245 | ||
12246 | return 0; | |
12247 | } | |
12248 | EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write); | |
12249 | ||
12250 | int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, | |
12251 | void *data) | |
12252 | { | |
12253 | int handled; | |
12254 | struct kvm_mmio_fragment *frag; | |
12255 | ||
12256 | if (!data) | |
12257 | return -EINVAL; | |
12258 | ||
12259 | handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data); | |
12260 | if (handled == bytes) | |
12261 | return 1; | |
12262 | ||
12263 | bytes -= handled; | |
12264 | gpa += handled; | |
12265 | data += handled; | |
12266 | ||
12267 | /*TODO: Check if need to increment number of frags */ | |
12268 | frag = vcpu->mmio_fragments; | |
12269 | vcpu->mmio_nr_fragments = 1; | |
12270 | frag->len = bytes; | |
12271 | frag->gpa = gpa; | |
12272 | frag->data = data; | |
12273 | ||
12274 | vcpu->mmio_needed = 1; | |
12275 | vcpu->mmio_cur_fragment = 0; | |
12276 | ||
12277 | vcpu->run->mmio.phys_addr = gpa; | |
12278 | vcpu->run->mmio.len = min(8u, frag->len); | |
12279 | vcpu->run->mmio.is_write = 0; | |
12280 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
12281 | ||
12282 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
12283 | ||
12284 | return 0; | |
12285 | } | |
12286 | EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read); | |
12287 | ||
7ed9abfe TL |
12288 | static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu) |
12289 | { | |
12290 | memcpy(vcpu->arch.guest_ins_data, vcpu->arch.pio_data, | |
12291 | vcpu->arch.pio.count * vcpu->arch.pio.size); | |
12292 | vcpu->arch.pio.count = 0; | |
12293 | ||
12294 | return 1; | |
12295 | } | |
12296 | ||
12297 | static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, | |
12298 | unsigned int port, void *data, unsigned int count) | |
12299 | { | |
12300 | int ret; | |
12301 | ||
12302 | ret = emulator_pio_out_emulated(vcpu->arch.emulate_ctxt, size, port, | |
12303 | data, count); | |
12304 | if (ret) | |
12305 | return ret; | |
12306 | ||
12307 | vcpu->arch.pio.count = 0; | |
12308 | ||
12309 | return 0; | |
12310 | } | |
12311 | ||
12312 | static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, | |
12313 | unsigned int port, void *data, unsigned int count) | |
12314 | { | |
12315 | int ret; | |
12316 | ||
12317 | ret = emulator_pio_in_emulated(vcpu->arch.emulate_ctxt, size, port, | |
12318 | data, count); | |
12319 | if (ret) { | |
12320 | vcpu->arch.pio.count = 0; | |
12321 | } else { | |
12322 | vcpu->arch.guest_ins_data = data; | |
12323 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins; | |
12324 | } | |
12325 | ||
12326 | return 0; | |
12327 | } | |
12328 | ||
12329 | int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size, | |
12330 | unsigned int port, void *data, unsigned int count, | |
12331 | int in) | |
12332 | { | |
12333 | return in ? kvm_sev_es_ins(vcpu, size, port, data, count) | |
12334 | : kvm_sev_es_outs(vcpu, size, port, data, count); | |
12335 | } | |
12336 | EXPORT_SYMBOL_GPL(kvm_sev_es_string_io); | |
12337 | ||
d95df951 | 12338 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry); |
229456fc | 12339 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
931c33b1 | 12340 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); |
229456fc MT |
12341 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); |
12342 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
12343 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
12344 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
0ac406de | 12345 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); |
d8cabddf | 12346 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 12347 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 12348 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
5497b955 | 12349 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); |
ec1ff790 | 12350 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 12351 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |
2e554e8d | 12352 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); |
489223ed | 12353 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); |
4f75bcc3 | 12354 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); |
843e4330 | 12355 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); |
efc64404 | 12356 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); |
18f40c53 SS |
12357 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); |
12358 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); | |
ab56f8e6 | 12359 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log); |
24bbf74c | 12360 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request); |
d523ab6b TL |
12361 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter); |
12362 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit); | |
59e38b58 TL |
12363 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter); |
12364 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit); |