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Commit | Line | Data |
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043405e1 CO |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * derived from drivers/kvm/kvm_main.c | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
7 | * Copyright (C) 2008 Qumranet, Inc. |
8 | * Copyright IBM Corporation, 2008 | |
043405e1 CO |
9 | * |
10 | * Authors: | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
13 | * Amit Shah <amit.shah@qumranet.com> |
14 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
15 | * |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
20 | ||
edf88417 | 21 | #include <linux/kvm_host.h> |
313a3dc7 | 22 | #include "irq.h" |
1d737c8a | 23 | #include "mmu.h" |
7837699f | 24 | #include "i8254.h" |
37817f29 | 25 | #include "tss.h" |
5fdbf976 | 26 | #include "kvm_cache_regs.h" |
26eef70c | 27 | #include "x86.h" |
313a3dc7 | 28 | |
18068523 | 29 | #include <linux/clocksource.h> |
4d5c5d0f | 30 | #include <linux/interrupt.h> |
313a3dc7 CO |
31 | #include <linux/kvm.h> |
32 | #include <linux/fs.h> | |
33 | #include <linux/vmalloc.h> | |
5fb76f9b | 34 | #include <linux/module.h> |
0de10343 | 35 | #include <linux/mman.h> |
2bacc55c | 36 | #include <linux/highmem.h> |
19de40a8 | 37 | #include <linux/iommu.h> |
62c476c7 | 38 | #include <linux/intel-iommu.h> |
c8076604 | 39 | #include <linux/cpufreq.h> |
043405e1 CO |
40 | |
41 | #include <asm/uaccess.h> | |
d825ed0a | 42 | #include <asm/msr.h> |
a5f61300 | 43 | #include <asm/desc.h> |
0bed3b56 | 44 | #include <asm/mtrr.h> |
890ca9ae | 45 | #include <asm/mce.h> |
043405e1 | 46 | |
313a3dc7 | 47 | #define MAX_IO_MSRS 256 |
a03490ed CO |
48 | #define CR0_RESERVED_BITS \ |
49 | (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ | |
50 | | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ | |
51 | | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) | |
52 | #define CR4_RESERVED_BITS \ | |
53 | (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ | |
54 | | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ | |
55 | | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \ | |
56 | | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE)) | |
57 | ||
58 | #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) | |
890ca9ae HY |
59 | |
60 | #define KVM_MAX_MCE_BANKS 32 | |
61 | #define KVM_MCE_CAP_SUPPORTED MCG_CTL_P | |
62 | ||
50a37eb4 JR |
63 | /* EFER defaults: |
64 | * - enable syscall per default because its emulated by KVM | |
65 | * - enable LME and LMA per default on 64 bit KVM | |
66 | */ | |
67 | #ifdef CONFIG_X86_64 | |
68 | static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL; | |
69 | #else | |
70 | static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL; | |
71 | #endif | |
313a3dc7 | 72 | |
ba1389b7 AK |
73 | #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM |
74 | #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU | |
417bc304 | 75 | |
674eea0f AK |
76 | static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid, |
77 | struct kvm_cpuid_entry2 __user *entries); | |
d8017474 AG |
78 | struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu, |
79 | u32 function, u32 index); | |
674eea0f | 80 | |
97896d04 | 81 | struct kvm_x86_ops *kvm_x86_ops; |
5fdbf976 | 82 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 83 | |
417bc304 | 84 | struct kvm_stats_debugfs_item debugfs_entries[] = { |
ba1389b7 AK |
85 | { "pf_fixed", VCPU_STAT(pf_fixed) }, |
86 | { "pf_guest", VCPU_STAT(pf_guest) }, | |
87 | { "tlb_flush", VCPU_STAT(tlb_flush) }, | |
88 | { "invlpg", VCPU_STAT(invlpg) }, | |
89 | { "exits", VCPU_STAT(exits) }, | |
90 | { "io_exits", VCPU_STAT(io_exits) }, | |
91 | { "mmio_exits", VCPU_STAT(mmio_exits) }, | |
92 | { "signal_exits", VCPU_STAT(signal_exits) }, | |
93 | { "irq_window", VCPU_STAT(irq_window_exits) }, | |
f08864b4 | 94 | { "nmi_window", VCPU_STAT(nmi_window_exits) }, |
ba1389b7 AK |
95 | { "halt_exits", VCPU_STAT(halt_exits) }, |
96 | { "halt_wakeup", VCPU_STAT(halt_wakeup) }, | |
f11c3a8d | 97 | { "hypercalls", VCPU_STAT(hypercalls) }, |
ba1389b7 AK |
98 | { "request_irq", VCPU_STAT(request_irq_exits) }, |
99 | { "irq_exits", VCPU_STAT(irq_exits) }, | |
100 | { "host_state_reload", VCPU_STAT(host_state_reload) }, | |
101 | { "efer_reload", VCPU_STAT(efer_reload) }, | |
102 | { "fpu_reload", VCPU_STAT(fpu_reload) }, | |
103 | { "insn_emulation", VCPU_STAT(insn_emulation) }, | |
104 | { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, | |
fa89a817 | 105 | { "irq_injections", VCPU_STAT(irq_injections) }, |
c4abb7c9 | 106 | { "nmi_injections", VCPU_STAT(nmi_injections) }, |
4cee5764 AK |
107 | { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, |
108 | { "mmu_pte_write", VM_STAT(mmu_pte_write) }, | |
109 | { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, | |
110 | { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, | |
111 | { "mmu_flooded", VM_STAT(mmu_flooded) }, | |
112 | { "mmu_recycled", VM_STAT(mmu_recycled) }, | |
dfc5aa00 | 113 | { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, |
4731d4c7 | 114 | { "mmu_unsync", VM_STAT(mmu_unsync) }, |
0f74a24c | 115 | { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, |
05da4558 | 116 | { "largepages", VM_STAT(lpages) }, |
417bc304 HB |
117 | { NULL } |
118 | }; | |
119 | ||
5fb76f9b CO |
120 | unsigned long segment_base(u16 selector) |
121 | { | |
122 | struct descriptor_table gdt; | |
a5f61300 | 123 | struct desc_struct *d; |
5fb76f9b CO |
124 | unsigned long table_base; |
125 | unsigned long v; | |
126 | ||
127 | if (selector == 0) | |
128 | return 0; | |
129 | ||
130 | asm("sgdt %0" : "=m"(gdt)); | |
131 | table_base = gdt.base; | |
132 | ||
133 | if (selector & 4) { /* from ldt */ | |
134 | u16 ldt_selector; | |
135 | ||
136 | asm("sldt %0" : "=g"(ldt_selector)); | |
137 | table_base = segment_base(ldt_selector); | |
138 | } | |
a5f61300 AK |
139 | d = (struct desc_struct *)(table_base + (selector & ~7)); |
140 | v = d->base0 | ((unsigned long)d->base1 << 16) | | |
141 | ((unsigned long)d->base2 << 24); | |
5fb76f9b | 142 | #ifdef CONFIG_X86_64 |
a5f61300 AK |
143 | if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11)) |
144 | v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32; | |
5fb76f9b CO |
145 | #endif |
146 | return v; | |
147 | } | |
148 | EXPORT_SYMBOL_GPL(segment_base); | |
149 | ||
6866b83e CO |
150 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
151 | { | |
152 | if (irqchip_in_kernel(vcpu->kvm)) | |
ad312c7c | 153 | return vcpu->arch.apic_base; |
6866b83e | 154 | else |
ad312c7c | 155 | return vcpu->arch.apic_base; |
6866b83e CO |
156 | } |
157 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
158 | ||
159 | void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data) | |
160 | { | |
161 | /* TODO: reserve bits check */ | |
162 | if (irqchip_in_kernel(vcpu->kvm)) | |
163 | kvm_lapic_set_base(vcpu, data); | |
164 | else | |
ad312c7c | 165 | vcpu->arch.apic_base = data; |
6866b83e CO |
166 | } |
167 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
168 | ||
298101da AK |
169 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
170 | { | |
ad312c7c ZX |
171 | WARN_ON(vcpu->arch.exception.pending); |
172 | vcpu->arch.exception.pending = true; | |
173 | vcpu->arch.exception.has_error_code = false; | |
174 | vcpu->arch.exception.nr = nr; | |
298101da AK |
175 | } |
176 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
177 | ||
c3c91fee AK |
178 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr, |
179 | u32 error_code) | |
180 | { | |
181 | ++vcpu->stat.pf_guest; | |
d8017474 | 182 | |
71c4dfaf JR |
183 | if (vcpu->arch.exception.pending) { |
184 | if (vcpu->arch.exception.nr == PF_VECTOR) { | |
185 | printk(KERN_DEBUG "kvm: inject_page_fault:" | |
186 | " double fault 0x%lx\n", addr); | |
187 | vcpu->arch.exception.nr = DF_VECTOR; | |
188 | vcpu->arch.exception.error_code = 0; | |
189 | } else if (vcpu->arch.exception.nr == DF_VECTOR) { | |
190 | /* triple fault -> shutdown */ | |
191 | set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests); | |
192 | } | |
c3c91fee AK |
193 | return; |
194 | } | |
ad312c7c | 195 | vcpu->arch.cr2 = addr; |
c3c91fee AK |
196 | kvm_queue_exception_e(vcpu, PF_VECTOR, error_code); |
197 | } | |
198 | ||
3419ffc8 SY |
199 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
200 | { | |
201 | vcpu->arch.nmi_pending = 1; | |
202 | } | |
203 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
204 | ||
298101da AK |
205 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
206 | { | |
ad312c7c ZX |
207 | WARN_ON(vcpu->arch.exception.pending); |
208 | vcpu->arch.exception.pending = true; | |
209 | vcpu->arch.exception.has_error_code = true; | |
210 | vcpu->arch.exception.nr = nr; | |
211 | vcpu->arch.exception.error_code = error_code; | |
298101da AK |
212 | } |
213 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
214 | ||
215 | static void __queue_exception(struct kvm_vcpu *vcpu) | |
216 | { | |
ad312c7c ZX |
217 | kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, |
218 | vcpu->arch.exception.has_error_code, | |
219 | vcpu->arch.exception.error_code); | |
298101da AK |
220 | } |
221 | ||
a03490ed CO |
222 | /* |
223 | * Load the pae pdptrs. Return true is they are all valid. | |
224 | */ | |
225 | int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3) | |
226 | { | |
227 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
228 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
229 | int i; | |
230 | int ret; | |
ad312c7c | 231 | u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)]; |
a03490ed | 232 | |
a03490ed CO |
233 | ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte, |
234 | offset * sizeof(u64), sizeof(pdpte)); | |
235 | if (ret < 0) { | |
236 | ret = 0; | |
237 | goto out; | |
238 | } | |
239 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
20c466b5 DE |
240 | if (is_present_pte(pdpte[i]) && |
241 | (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) { | |
a03490ed CO |
242 | ret = 0; |
243 | goto out; | |
244 | } | |
245 | } | |
246 | ret = 1; | |
247 | ||
ad312c7c | 248 | memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs)); |
a03490ed | 249 | out: |
a03490ed CO |
250 | |
251 | return ret; | |
252 | } | |
cc4b6871 | 253 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 254 | |
d835dfec AK |
255 | static bool pdptrs_changed(struct kvm_vcpu *vcpu) |
256 | { | |
ad312c7c | 257 | u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)]; |
d835dfec AK |
258 | bool changed = true; |
259 | int r; | |
260 | ||
261 | if (is_long_mode(vcpu) || !is_pae(vcpu)) | |
262 | return false; | |
263 | ||
ad312c7c | 264 | r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte)); |
d835dfec AK |
265 | if (r < 0) |
266 | goto out; | |
ad312c7c | 267 | changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0; |
d835dfec | 268 | out: |
d835dfec AK |
269 | |
270 | return changed; | |
271 | } | |
272 | ||
2d3ad1f4 | 273 | void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed CO |
274 | { |
275 | if (cr0 & CR0_RESERVED_BITS) { | |
276 | printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n", | |
ad312c7c | 277 | cr0, vcpu->arch.cr0); |
c1a5d4f9 | 278 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
279 | return; |
280 | } | |
281 | ||
282 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) { | |
283 | printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n"); | |
c1a5d4f9 | 284 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
285 | return; |
286 | } | |
287 | ||
288 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) { | |
289 | printk(KERN_DEBUG "set_cr0: #GP, set PG flag " | |
290 | "and a clear PE flag\n"); | |
c1a5d4f9 | 291 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
292 | return; |
293 | } | |
294 | ||
295 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { | |
296 | #ifdef CONFIG_X86_64 | |
ad312c7c | 297 | if ((vcpu->arch.shadow_efer & EFER_LME)) { |
a03490ed CO |
298 | int cs_db, cs_l; |
299 | ||
300 | if (!is_pae(vcpu)) { | |
301 | printk(KERN_DEBUG "set_cr0: #GP, start paging " | |
302 | "in long mode while PAE is disabled\n"); | |
c1a5d4f9 | 303 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
304 | return; |
305 | } | |
306 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
307 | if (cs_l) { | |
308 | printk(KERN_DEBUG "set_cr0: #GP, start paging " | |
309 | "in long mode while CS.L == 1\n"); | |
c1a5d4f9 | 310 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
311 | return; |
312 | ||
313 | } | |
314 | } else | |
315 | #endif | |
ad312c7c | 316 | if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) { |
a03490ed CO |
317 | printk(KERN_DEBUG "set_cr0: #GP, pdptrs " |
318 | "reserved bits\n"); | |
c1a5d4f9 | 319 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
320 | return; |
321 | } | |
322 | ||
323 | } | |
324 | ||
325 | kvm_x86_ops->set_cr0(vcpu, cr0); | |
ad312c7c | 326 | vcpu->arch.cr0 = cr0; |
a03490ed | 327 | |
a03490ed | 328 | kvm_mmu_reset_context(vcpu); |
a03490ed CO |
329 | return; |
330 | } | |
2d3ad1f4 | 331 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 332 | |
2d3ad1f4 | 333 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 334 | { |
2d3ad1f4 | 335 | kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f)); |
2714d1d3 FEL |
336 | KVMTRACE_1D(LMSW, vcpu, |
337 | (u32)((vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f)), | |
338 | handler); | |
a03490ed | 339 | } |
2d3ad1f4 | 340 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 341 | |
2d3ad1f4 | 342 | void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 343 | { |
a2edf57f AK |
344 | unsigned long old_cr4 = vcpu->arch.cr4; |
345 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE; | |
346 | ||
a03490ed CO |
347 | if (cr4 & CR4_RESERVED_BITS) { |
348 | printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n"); | |
c1a5d4f9 | 349 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
350 | return; |
351 | } | |
352 | ||
353 | if (is_long_mode(vcpu)) { | |
354 | if (!(cr4 & X86_CR4_PAE)) { | |
355 | printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while " | |
356 | "in long mode\n"); | |
c1a5d4f9 | 357 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
358 | return; |
359 | } | |
a2edf57f AK |
360 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
361 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
ad312c7c | 362 | && !load_pdptrs(vcpu, vcpu->arch.cr3)) { |
a03490ed | 363 | printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n"); |
c1a5d4f9 | 364 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
365 | return; |
366 | } | |
367 | ||
368 | if (cr4 & X86_CR4_VMXE) { | |
369 | printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n"); | |
c1a5d4f9 | 370 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
371 | return; |
372 | } | |
373 | kvm_x86_ops->set_cr4(vcpu, cr4); | |
ad312c7c | 374 | vcpu->arch.cr4 = cr4; |
5a41accd | 375 | vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled; |
a03490ed | 376 | kvm_mmu_reset_context(vcpu); |
a03490ed | 377 | } |
2d3ad1f4 | 378 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 379 | |
2d3ad1f4 | 380 | void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 381 | { |
ad312c7c | 382 | if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) { |
0ba73cda | 383 | kvm_mmu_sync_roots(vcpu); |
d835dfec AK |
384 | kvm_mmu_flush_tlb(vcpu); |
385 | return; | |
386 | } | |
387 | ||
a03490ed CO |
388 | if (is_long_mode(vcpu)) { |
389 | if (cr3 & CR3_L_MODE_RESERVED_BITS) { | |
390 | printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n"); | |
c1a5d4f9 | 391 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
392 | return; |
393 | } | |
394 | } else { | |
395 | if (is_pae(vcpu)) { | |
396 | if (cr3 & CR3_PAE_RESERVED_BITS) { | |
397 | printk(KERN_DEBUG | |
398 | "set_cr3: #GP, reserved bits\n"); | |
c1a5d4f9 | 399 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
400 | return; |
401 | } | |
402 | if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) { | |
403 | printk(KERN_DEBUG "set_cr3: #GP, pdptrs " | |
404 | "reserved bits\n"); | |
c1a5d4f9 | 405 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
406 | return; |
407 | } | |
408 | } | |
409 | /* | |
410 | * We don't check reserved bits in nonpae mode, because | |
411 | * this isn't enforced, and VMware depends on this. | |
412 | */ | |
413 | } | |
414 | ||
a03490ed CO |
415 | /* |
416 | * Does the new cr3 value map to physical memory? (Note, we | |
417 | * catch an invalid cr3 even in real-mode, because it would | |
418 | * cause trouble later on when we turn on paging anyway.) | |
419 | * | |
420 | * A real CPU would silently accept an invalid cr3 and would | |
421 | * attempt to use it - with largely undefined (and often hard | |
422 | * to debug) behavior on the guest side. | |
423 | */ | |
424 | if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT))) | |
c1a5d4f9 | 425 | kvm_inject_gp(vcpu, 0); |
a03490ed | 426 | else { |
ad312c7c ZX |
427 | vcpu->arch.cr3 = cr3; |
428 | vcpu->arch.mmu.new_cr3(vcpu); | |
a03490ed | 429 | } |
a03490ed | 430 | } |
2d3ad1f4 | 431 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 432 | |
2d3ad1f4 | 433 | void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed CO |
434 | { |
435 | if (cr8 & CR8_RESERVED_BITS) { | |
436 | printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8); | |
c1a5d4f9 | 437 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
438 | return; |
439 | } | |
440 | if (irqchip_in_kernel(vcpu->kvm)) | |
441 | kvm_lapic_set_tpr(vcpu, cr8); | |
442 | else | |
ad312c7c | 443 | vcpu->arch.cr8 = cr8; |
a03490ed | 444 | } |
2d3ad1f4 | 445 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 446 | |
2d3ad1f4 | 447 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed CO |
448 | { |
449 | if (irqchip_in_kernel(vcpu->kvm)) | |
450 | return kvm_lapic_get_cr8(vcpu); | |
451 | else | |
ad312c7c | 452 | return vcpu->arch.cr8; |
a03490ed | 453 | } |
2d3ad1f4 | 454 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 455 | |
d8017474 AG |
456 | static inline u32 bit(int bitno) |
457 | { | |
458 | return 1 << (bitno & 31); | |
459 | } | |
460 | ||
043405e1 CO |
461 | /* |
462 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
463 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
464 | * | |
465 | * This list is modified at module load time to reflect the | |
466 | * capabilities of the host cpu. | |
467 | */ | |
468 | static u32 msrs_to_save[] = { | |
469 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
470 | MSR_K6_STAR, | |
471 | #ifdef CONFIG_X86_64 | |
472 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
473 | #endif | |
af24a4e4 | 474 | MSR_IA32_TSC, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, |
b286d5d8 | 475 | MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA |
043405e1 CO |
476 | }; |
477 | ||
478 | static unsigned num_msrs_to_save; | |
479 | ||
480 | static u32 emulated_msrs[] = { | |
481 | MSR_IA32_MISC_ENABLE, | |
482 | }; | |
483 | ||
15c4a640 CO |
484 | static void set_efer(struct kvm_vcpu *vcpu, u64 efer) |
485 | { | |
f2b4b7dd | 486 | if (efer & efer_reserved_bits) { |
15c4a640 CO |
487 | printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n", |
488 | efer); | |
c1a5d4f9 | 489 | kvm_inject_gp(vcpu, 0); |
15c4a640 CO |
490 | return; |
491 | } | |
492 | ||
493 | if (is_paging(vcpu) | |
ad312c7c | 494 | && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) { |
15c4a640 | 495 | printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n"); |
c1a5d4f9 | 496 | kvm_inject_gp(vcpu, 0); |
15c4a640 CO |
497 | return; |
498 | } | |
499 | ||
1b2fd70c AG |
500 | if (efer & EFER_FFXSR) { |
501 | struct kvm_cpuid_entry2 *feat; | |
502 | ||
503 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
504 | if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) { | |
505 | printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n"); | |
506 | kvm_inject_gp(vcpu, 0); | |
507 | return; | |
508 | } | |
509 | } | |
510 | ||
d8017474 AG |
511 | if (efer & EFER_SVME) { |
512 | struct kvm_cpuid_entry2 *feat; | |
513 | ||
514 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
515 | if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) { | |
516 | printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n"); | |
517 | kvm_inject_gp(vcpu, 0); | |
518 | return; | |
519 | } | |
520 | } | |
521 | ||
15c4a640 CO |
522 | kvm_x86_ops->set_efer(vcpu, efer); |
523 | ||
524 | efer &= ~EFER_LMA; | |
ad312c7c | 525 | efer |= vcpu->arch.shadow_efer & EFER_LMA; |
15c4a640 | 526 | |
ad312c7c | 527 | vcpu->arch.shadow_efer = efer; |
9645bb56 AK |
528 | |
529 | vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled; | |
530 | kvm_mmu_reset_context(vcpu); | |
15c4a640 CO |
531 | } |
532 | ||
f2b4b7dd JR |
533 | void kvm_enable_efer_bits(u64 mask) |
534 | { | |
535 | efer_reserved_bits &= ~mask; | |
536 | } | |
537 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
538 | ||
539 | ||
15c4a640 CO |
540 | /* |
541 | * Writes msr value into into the appropriate "register". | |
542 | * Returns 0 on success, non-0 otherwise. | |
543 | * Assumes vcpu_load() was already called. | |
544 | */ | |
545 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
546 | { | |
547 | return kvm_x86_ops->set_msr(vcpu, msr_index, data); | |
548 | } | |
549 | ||
313a3dc7 CO |
550 | /* |
551 | * Adapt set_msr() to msr_io()'s calling convention | |
552 | */ | |
553 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
554 | { | |
555 | return kvm_set_msr(vcpu, index, *data); | |
556 | } | |
557 | ||
18068523 GOC |
558 | static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) |
559 | { | |
560 | static int version; | |
50d0a0f9 GH |
561 | struct pvclock_wall_clock wc; |
562 | struct timespec now, sys, boot; | |
18068523 GOC |
563 | |
564 | if (!wall_clock) | |
565 | return; | |
566 | ||
567 | version++; | |
568 | ||
18068523 GOC |
569 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); |
570 | ||
50d0a0f9 GH |
571 | /* |
572 | * The guest calculates current wall clock time by adding | |
573 | * system time (updated by kvm_write_guest_time below) to the | |
574 | * wall clock specified here. guest system time equals host | |
575 | * system time for us, thus we must fill in host boot time here. | |
576 | */ | |
577 | now = current_kernel_time(); | |
578 | ktime_get_ts(&sys); | |
579 | boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys)); | |
580 | ||
581 | wc.sec = boot.tv_sec; | |
582 | wc.nsec = boot.tv_nsec; | |
583 | wc.version = version; | |
18068523 GOC |
584 | |
585 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
586 | ||
587 | version++; | |
588 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
589 | } |
590 | ||
50d0a0f9 GH |
591 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
592 | { | |
593 | uint32_t quotient, remainder; | |
594 | ||
595 | /* Don't try to replace with do_div(), this one calculates | |
596 | * "(dividend << 32) / divisor" */ | |
597 | __asm__ ( "divl %4" | |
598 | : "=a" (quotient), "=d" (remainder) | |
599 | : "0" (0), "1" (dividend), "r" (divisor) ); | |
600 | return quotient; | |
601 | } | |
602 | ||
603 | static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock) | |
604 | { | |
605 | uint64_t nsecs = 1000000000LL; | |
606 | int32_t shift = 0; | |
607 | uint64_t tps64; | |
608 | uint32_t tps32; | |
609 | ||
610 | tps64 = tsc_khz * 1000LL; | |
611 | while (tps64 > nsecs*2) { | |
612 | tps64 >>= 1; | |
613 | shift--; | |
614 | } | |
615 | ||
616 | tps32 = (uint32_t)tps64; | |
617 | while (tps32 <= (uint32_t)nsecs) { | |
618 | tps32 <<= 1; | |
619 | shift++; | |
620 | } | |
621 | ||
622 | hv_clock->tsc_shift = shift; | |
623 | hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32); | |
624 | ||
625 | pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n", | |
80a914dc | 626 | __func__, tsc_khz, hv_clock->tsc_shift, |
50d0a0f9 GH |
627 | hv_clock->tsc_to_system_mul); |
628 | } | |
629 | ||
c8076604 GH |
630 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
631 | ||
18068523 GOC |
632 | static void kvm_write_guest_time(struct kvm_vcpu *v) |
633 | { | |
634 | struct timespec ts; | |
635 | unsigned long flags; | |
636 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
637 | void *shared_kaddr; | |
463656c0 | 638 | unsigned long this_tsc_khz; |
18068523 GOC |
639 | |
640 | if ((!vcpu->time_page)) | |
641 | return; | |
642 | ||
463656c0 AK |
643 | this_tsc_khz = get_cpu_var(cpu_tsc_khz); |
644 | if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) { | |
645 | kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock); | |
646 | vcpu->hv_clock_tsc_khz = this_tsc_khz; | |
50d0a0f9 | 647 | } |
463656c0 | 648 | put_cpu_var(cpu_tsc_khz); |
50d0a0f9 | 649 | |
18068523 GOC |
650 | /* Keep irq disabled to prevent changes to the clock */ |
651 | local_irq_save(flags); | |
af24a4e4 | 652 | kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp); |
18068523 GOC |
653 | ktime_get_ts(&ts); |
654 | local_irq_restore(flags); | |
655 | ||
656 | /* With all the info we got, fill in the values */ | |
657 | ||
658 | vcpu->hv_clock.system_time = ts.tv_nsec + | |
659 | (NSEC_PER_SEC * (u64)ts.tv_sec); | |
660 | /* | |
661 | * The interface expects us to write an even number signaling that the | |
662 | * update is finished. Since the guest won't see the intermediate | |
50d0a0f9 | 663 | * state, we just increase by 2 at the end. |
18068523 | 664 | */ |
50d0a0f9 | 665 | vcpu->hv_clock.version += 2; |
18068523 GOC |
666 | |
667 | shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0); | |
668 | ||
669 | memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock, | |
50d0a0f9 | 670 | sizeof(vcpu->hv_clock)); |
18068523 GOC |
671 | |
672 | kunmap_atomic(shared_kaddr, KM_USER0); | |
673 | ||
674 | mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT); | |
675 | } | |
676 | ||
c8076604 GH |
677 | static int kvm_request_guest_time_update(struct kvm_vcpu *v) |
678 | { | |
679 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
680 | ||
681 | if (!vcpu->time_page) | |
682 | return 0; | |
683 | set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests); | |
684 | return 1; | |
685 | } | |
686 | ||
9ba075a6 AK |
687 | static bool msr_mtrr_valid(unsigned msr) |
688 | { | |
689 | switch (msr) { | |
690 | case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1: | |
691 | case MSR_MTRRfix64K_00000: | |
692 | case MSR_MTRRfix16K_80000: | |
693 | case MSR_MTRRfix16K_A0000: | |
694 | case MSR_MTRRfix4K_C0000: | |
695 | case MSR_MTRRfix4K_C8000: | |
696 | case MSR_MTRRfix4K_D0000: | |
697 | case MSR_MTRRfix4K_D8000: | |
698 | case MSR_MTRRfix4K_E0000: | |
699 | case MSR_MTRRfix4K_E8000: | |
700 | case MSR_MTRRfix4K_F0000: | |
701 | case MSR_MTRRfix4K_F8000: | |
702 | case MSR_MTRRdefType: | |
703 | case MSR_IA32_CR_PAT: | |
704 | return true; | |
705 | case 0x2f8: | |
706 | return true; | |
707 | } | |
708 | return false; | |
709 | } | |
710 | ||
d6289b93 MT |
711 | static bool valid_pat_type(unsigned t) |
712 | { | |
713 | return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */ | |
714 | } | |
715 | ||
716 | static bool valid_mtrr_type(unsigned t) | |
717 | { | |
718 | return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */ | |
719 | } | |
720 | ||
721 | static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
722 | { | |
723 | int i; | |
724 | ||
725 | if (!msr_mtrr_valid(msr)) | |
726 | return false; | |
727 | ||
728 | if (msr == MSR_IA32_CR_PAT) { | |
729 | for (i = 0; i < 8; i++) | |
730 | if (!valid_pat_type((data >> (i * 8)) & 0xff)) | |
731 | return false; | |
732 | return true; | |
733 | } else if (msr == MSR_MTRRdefType) { | |
734 | if (data & ~0xcff) | |
735 | return false; | |
736 | return valid_mtrr_type(data & 0xff); | |
737 | } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) { | |
738 | for (i = 0; i < 8 ; i++) | |
739 | if (!valid_mtrr_type((data >> (i * 8)) & 0xff)) | |
740 | return false; | |
741 | return true; | |
742 | } | |
743 | ||
744 | /* variable MTRRs */ | |
745 | return valid_mtrr_type(data & 0xff); | |
746 | } | |
747 | ||
9ba075a6 AK |
748 | static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
749 | { | |
0bed3b56 SY |
750 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; |
751 | ||
d6289b93 | 752 | if (!mtrr_valid(vcpu, msr, data)) |
9ba075a6 AK |
753 | return 1; |
754 | ||
0bed3b56 SY |
755 | if (msr == MSR_MTRRdefType) { |
756 | vcpu->arch.mtrr_state.def_type = data; | |
757 | vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10; | |
758 | } else if (msr == MSR_MTRRfix64K_00000) | |
759 | p[0] = data; | |
760 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
761 | p[1 + msr - MSR_MTRRfix16K_80000] = data; | |
762 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
763 | p[3 + msr - MSR_MTRRfix4K_C0000] = data; | |
764 | else if (msr == MSR_IA32_CR_PAT) | |
765 | vcpu->arch.pat = data; | |
766 | else { /* Variable MTRRs */ | |
767 | int idx, is_mtrr_mask; | |
768 | u64 *pt; | |
769 | ||
770 | idx = (msr - 0x200) / 2; | |
771 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
772 | if (!is_mtrr_mask) | |
773 | pt = | |
774 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
775 | else | |
776 | pt = | |
777 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
778 | *pt = data; | |
779 | } | |
780 | ||
781 | kvm_mmu_reset_context(vcpu); | |
9ba075a6 AK |
782 | return 0; |
783 | } | |
15c4a640 | 784 | |
890ca9ae | 785 | static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
15c4a640 | 786 | { |
890ca9ae HY |
787 | u64 mcg_cap = vcpu->arch.mcg_cap; |
788 | unsigned bank_num = mcg_cap & 0xff; | |
789 | ||
15c4a640 | 790 | switch (msr) { |
15c4a640 | 791 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 792 | vcpu->arch.mcg_status = data; |
15c4a640 | 793 | break; |
c7ac679c | 794 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
795 | if (!(mcg_cap & MCG_CTL_P)) |
796 | return 1; | |
797 | if (data != 0 && data != ~(u64)0) | |
798 | return -1; | |
799 | vcpu->arch.mcg_ctl = data; | |
800 | break; | |
801 | default: | |
802 | if (msr >= MSR_IA32_MC0_CTL && | |
803 | msr < MSR_IA32_MC0_CTL + 4 * bank_num) { | |
804 | u32 offset = msr - MSR_IA32_MC0_CTL; | |
805 | /* only 0 or all 1s can be written to IA32_MCi_CTL */ | |
806 | if ((offset & 0x3) == 0 && | |
807 | data != 0 && data != ~(u64)0) | |
808 | return -1; | |
809 | vcpu->arch.mce_banks[offset] = data; | |
810 | break; | |
811 | } | |
812 | return 1; | |
813 | } | |
814 | return 0; | |
815 | } | |
816 | ||
817 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
818 | { | |
819 | switch (msr) { | |
820 | case MSR_EFER: | |
821 | set_efer(vcpu, data); | |
c7ac679c | 822 | break; |
b5e2fec0 AG |
823 | case MSR_IA32_DEBUGCTLMSR: |
824 | if (!data) { | |
825 | /* We support the non-activated case already */ | |
826 | break; | |
827 | } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { | |
828 | /* Values other than LBR and BTF are vendor-specific, | |
829 | thus reserved and should throw a #GP */ | |
830 | return 1; | |
831 | } | |
832 | pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", | |
833 | __func__, data); | |
834 | break; | |
15c4a640 CO |
835 | case MSR_IA32_UCODE_REV: |
836 | case MSR_IA32_UCODE_WRITE: | |
61a6bd67 | 837 | case MSR_VM_HSAVE_PA: |
15c4a640 | 838 | break; |
9ba075a6 AK |
839 | case 0x200 ... 0x2ff: |
840 | return set_msr_mtrr(vcpu, msr, data); | |
15c4a640 CO |
841 | case MSR_IA32_APICBASE: |
842 | kvm_set_apic_base(vcpu, data); | |
843 | break; | |
844 | case MSR_IA32_MISC_ENABLE: | |
ad312c7c | 845 | vcpu->arch.ia32_misc_enable_msr = data; |
15c4a640 | 846 | break; |
18068523 GOC |
847 | case MSR_KVM_WALL_CLOCK: |
848 | vcpu->kvm->arch.wall_clock = data; | |
849 | kvm_write_wall_clock(vcpu->kvm, data); | |
850 | break; | |
851 | case MSR_KVM_SYSTEM_TIME: { | |
852 | if (vcpu->arch.time_page) { | |
853 | kvm_release_page_dirty(vcpu->arch.time_page); | |
854 | vcpu->arch.time_page = NULL; | |
855 | } | |
856 | ||
857 | vcpu->arch.time = data; | |
858 | ||
859 | /* we verify if the enable bit is set... */ | |
860 | if (!(data & 1)) | |
861 | break; | |
862 | ||
863 | /* ...but clean it before doing the actual write */ | |
864 | vcpu->arch.time_offset = data & ~(PAGE_MASK | 1); | |
865 | ||
18068523 GOC |
866 | vcpu->arch.time_page = |
867 | gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT); | |
18068523 GOC |
868 | |
869 | if (is_error_page(vcpu->arch.time_page)) { | |
870 | kvm_release_page_clean(vcpu->arch.time_page); | |
871 | vcpu->arch.time_page = NULL; | |
872 | } | |
873 | ||
c8076604 | 874 | kvm_request_guest_time_update(vcpu); |
18068523 GOC |
875 | break; |
876 | } | |
890ca9ae HY |
877 | case MSR_IA32_MCG_CTL: |
878 | case MSR_IA32_MCG_STATUS: | |
879 | case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1: | |
880 | return set_msr_mce(vcpu, msr, data); | |
15c4a640 | 881 | default: |
565f1fbd | 882 | pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", msr, data); |
15c4a640 CO |
883 | return 1; |
884 | } | |
885 | return 0; | |
886 | } | |
887 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
888 | ||
889 | ||
890 | /* | |
891 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
892 | * Returns 0 on success, non-0 otherwise. | |
893 | * Assumes vcpu_load() was already called. | |
894 | */ | |
895 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
896 | { | |
897 | return kvm_x86_ops->get_msr(vcpu, msr_index, pdata); | |
898 | } | |
899 | ||
9ba075a6 AK |
900 | static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
901 | { | |
0bed3b56 SY |
902 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; |
903 | ||
9ba075a6 AK |
904 | if (!msr_mtrr_valid(msr)) |
905 | return 1; | |
906 | ||
0bed3b56 SY |
907 | if (msr == MSR_MTRRdefType) |
908 | *pdata = vcpu->arch.mtrr_state.def_type + | |
909 | (vcpu->arch.mtrr_state.enabled << 10); | |
910 | else if (msr == MSR_MTRRfix64K_00000) | |
911 | *pdata = p[0]; | |
912 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
913 | *pdata = p[1 + msr - MSR_MTRRfix16K_80000]; | |
914 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
915 | *pdata = p[3 + msr - MSR_MTRRfix4K_C0000]; | |
916 | else if (msr == MSR_IA32_CR_PAT) | |
917 | *pdata = vcpu->arch.pat; | |
918 | else { /* Variable MTRRs */ | |
919 | int idx, is_mtrr_mask; | |
920 | u64 *pt; | |
921 | ||
922 | idx = (msr - 0x200) / 2; | |
923 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
924 | if (!is_mtrr_mask) | |
925 | pt = | |
926 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
927 | else | |
928 | pt = | |
929 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
930 | *pdata = *pt; | |
931 | } | |
932 | ||
9ba075a6 AK |
933 | return 0; |
934 | } | |
935 | ||
890ca9ae | 936 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
15c4a640 CO |
937 | { |
938 | u64 data; | |
890ca9ae HY |
939 | u64 mcg_cap = vcpu->arch.mcg_cap; |
940 | unsigned bank_num = mcg_cap & 0xff; | |
15c4a640 CO |
941 | |
942 | switch (msr) { | |
15c4a640 CO |
943 | case MSR_IA32_P5_MC_ADDR: |
944 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
945 | data = 0; |
946 | break; | |
15c4a640 | 947 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
948 | data = vcpu->arch.mcg_cap; |
949 | break; | |
c7ac679c | 950 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
951 | if (!(mcg_cap & MCG_CTL_P)) |
952 | return 1; | |
953 | data = vcpu->arch.mcg_ctl; | |
954 | break; | |
955 | case MSR_IA32_MCG_STATUS: | |
956 | data = vcpu->arch.mcg_status; | |
957 | break; | |
958 | default: | |
959 | if (msr >= MSR_IA32_MC0_CTL && | |
960 | msr < MSR_IA32_MC0_CTL + 4 * bank_num) { | |
961 | u32 offset = msr - MSR_IA32_MC0_CTL; | |
962 | data = vcpu->arch.mce_banks[offset]; | |
963 | break; | |
964 | } | |
965 | return 1; | |
966 | } | |
967 | *pdata = data; | |
968 | return 0; | |
969 | } | |
970 | ||
971 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) | |
972 | { | |
973 | u64 data; | |
974 | ||
975 | switch (msr) { | |
976 | case 0xc0010010: /* SYSCFG */ | |
977 | case 0xc0010015: /* HWCR */ | |
978 | case MSR_IA32_PLATFORM_ID: | |
15c4a640 | 979 | case MSR_IA32_UCODE_REV: |
15c4a640 | 980 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
981 | case MSR_IA32_DEBUGCTLMSR: |
982 | case MSR_IA32_LASTBRANCHFROMIP: | |
983 | case MSR_IA32_LASTBRANCHTOIP: | |
984 | case MSR_IA32_LASTINTFROMIP: | |
985 | case MSR_IA32_LASTINTTOIP: | |
61a6bd67 | 986 | case MSR_VM_HSAVE_PA: |
7fe29e0f AS |
987 | case MSR_P6_EVNTSEL0: |
988 | case MSR_P6_EVNTSEL1: | |
9e699624 | 989 | case MSR_K7_EVNTSEL0: |
15c4a640 CO |
990 | data = 0; |
991 | break; | |
9ba075a6 AK |
992 | case MSR_MTRRcap: |
993 | data = 0x500 | KVM_NR_VAR_MTRR; | |
994 | break; | |
995 | case 0x200 ... 0x2ff: | |
996 | return get_msr_mtrr(vcpu, msr, pdata); | |
15c4a640 CO |
997 | case 0xcd: /* fsb frequency */ |
998 | data = 3; | |
999 | break; | |
1000 | case MSR_IA32_APICBASE: | |
1001 | data = kvm_get_apic_base(vcpu); | |
1002 | break; | |
1003 | case MSR_IA32_MISC_ENABLE: | |
ad312c7c | 1004 | data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 1005 | break; |
847f0ad8 AG |
1006 | case MSR_IA32_PERF_STATUS: |
1007 | /* TSC increment by tick */ | |
1008 | data = 1000ULL; | |
1009 | /* CPU multiplier */ | |
1010 | data |= (((uint64_t)4ULL) << 40); | |
1011 | break; | |
15c4a640 | 1012 | case MSR_EFER: |
ad312c7c | 1013 | data = vcpu->arch.shadow_efer; |
15c4a640 | 1014 | break; |
18068523 GOC |
1015 | case MSR_KVM_WALL_CLOCK: |
1016 | data = vcpu->kvm->arch.wall_clock; | |
1017 | break; | |
1018 | case MSR_KVM_SYSTEM_TIME: | |
1019 | data = vcpu->arch.time; | |
1020 | break; | |
890ca9ae HY |
1021 | case MSR_IA32_P5_MC_ADDR: |
1022 | case MSR_IA32_P5_MC_TYPE: | |
1023 | case MSR_IA32_MCG_CAP: | |
1024 | case MSR_IA32_MCG_CTL: | |
1025 | case MSR_IA32_MCG_STATUS: | |
1026 | case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1: | |
1027 | return get_msr_mce(vcpu, msr, pdata); | |
15c4a640 CO |
1028 | default: |
1029 | pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr); | |
1030 | return 1; | |
1031 | } | |
1032 | *pdata = data; | |
1033 | return 0; | |
1034 | } | |
1035 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
1036 | ||
313a3dc7 CO |
1037 | /* |
1038 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
1039 | * | |
1040 | * @return number of msrs set successfully. | |
1041 | */ | |
1042 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
1043 | struct kvm_msr_entry *entries, | |
1044 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
1045 | unsigned index, u64 *data)) | |
1046 | { | |
1047 | int i; | |
1048 | ||
1049 | vcpu_load(vcpu); | |
1050 | ||
3200f405 | 1051 | down_read(&vcpu->kvm->slots_lock); |
313a3dc7 CO |
1052 | for (i = 0; i < msrs->nmsrs; ++i) |
1053 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
1054 | break; | |
3200f405 | 1055 | up_read(&vcpu->kvm->slots_lock); |
313a3dc7 CO |
1056 | |
1057 | vcpu_put(vcpu); | |
1058 | ||
1059 | return i; | |
1060 | } | |
1061 | ||
1062 | /* | |
1063 | * Read or write a bunch of msrs. Parameters are user addresses. | |
1064 | * | |
1065 | * @return number of msrs set successfully. | |
1066 | */ | |
1067 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
1068 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
1069 | unsigned index, u64 *data), | |
1070 | int writeback) | |
1071 | { | |
1072 | struct kvm_msrs msrs; | |
1073 | struct kvm_msr_entry *entries; | |
1074 | int r, n; | |
1075 | unsigned size; | |
1076 | ||
1077 | r = -EFAULT; | |
1078 | if (copy_from_user(&msrs, user_msrs, sizeof msrs)) | |
1079 | goto out; | |
1080 | ||
1081 | r = -E2BIG; | |
1082 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
1083 | goto out; | |
1084 | ||
1085 | r = -ENOMEM; | |
1086 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; | |
1087 | entries = vmalloc(size); | |
1088 | if (!entries) | |
1089 | goto out; | |
1090 | ||
1091 | r = -EFAULT; | |
1092 | if (copy_from_user(entries, user_msrs->entries, size)) | |
1093 | goto out_free; | |
1094 | ||
1095 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
1096 | if (r < 0) | |
1097 | goto out_free; | |
1098 | ||
1099 | r = -EFAULT; | |
1100 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
1101 | goto out_free; | |
1102 | ||
1103 | r = n; | |
1104 | ||
1105 | out_free: | |
1106 | vfree(entries); | |
1107 | out: | |
1108 | return r; | |
1109 | } | |
1110 | ||
018d00d2 ZX |
1111 | int kvm_dev_ioctl_check_extension(long ext) |
1112 | { | |
1113 | int r; | |
1114 | ||
1115 | switch (ext) { | |
1116 | case KVM_CAP_IRQCHIP: | |
1117 | case KVM_CAP_HLT: | |
1118 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 1119 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 1120 | case KVM_CAP_EXT_CPUID: |
c8076604 | 1121 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 1122 | case KVM_CAP_PIT: |
a28e4f5a | 1123 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 1124 | case KVM_CAP_MP_STATE: |
ed848624 | 1125 | case KVM_CAP_SYNC_MMU: |
52d939a0 | 1126 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 1127 | case KVM_CAP_IRQ_INJECT_STATUS: |
e56d532f | 1128 | case KVM_CAP_ASSIGN_DEV_IRQ: |
018d00d2 ZX |
1129 | r = 1; |
1130 | break; | |
542472b5 LV |
1131 | case KVM_CAP_COALESCED_MMIO: |
1132 | r = KVM_COALESCED_MMIO_PAGE_OFFSET; | |
1133 | break; | |
774ead3a AK |
1134 | case KVM_CAP_VAPIC: |
1135 | r = !kvm_x86_ops->cpu_has_accelerated_tpr(); | |
1136 | break; | |
f725230a AK |
1137 | case KVM_CAP_NR_VCPUS: |
1138 | r = KVM_MAX_VCPUS; | |
1139 | break; | |
a988b910 AK |
1140 | case KVM_CAP_NR_MEMSLOTS: |
1141 | r = KVM_MEMORY_SLOTS; | |
1142 | break; | |
2f333bcb MT |
1143 | case KVM_CAP_PV_MMU: |
1144 | r = !tdp_enabled; | |
1145 | break; | |
62c476c7 | 1146 | case KVM_CAP_IOMMU: |
19de40a8 | 1147 | r = iommu_found(); |
62c476c7 | 1148 | break; |
890ca9ae HY |
1149 | case KVM_CAP_MCE: |
1150 | r = KVM_MAX_MCE_BANKS; | |
1151 | break; | |
018d00d2 ZX |
1152 | default: |
1153 | r = 0; | |
1154 | break; | |
1155 | } | |
1156 | return r; | |
1157 | ||
1158 | } | |
1159 | ||
043405e1 CO |
1160 | long kvm_arch_dev_ioctl(struct file *filp, |
1161 | unsigned int ioctl, unsigned long arg) | |
1162 | { | |
1163 | void __user *argp = (void __user *)arg; | |
1164 | long r; | |
1165 | ||
1166 | switch (ioctl) { | |
1167 | case KVM_GET_MSR_INDEX_LIST: { | |
1168 | struct kvm_msr_list __user *user_msr_list = argp; | |
1169 | struct kvm_msr_list msr_list; | |
1170 | unsigned n; | |
1171 | ||
1172 | r = -EFAULT; | |
1173 | if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) | |
1174 | goto out; | |
1175 | n = msr_list.nmsrs; | |
1176 | msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs); | |
1177 | if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) | |
1178 | goto out; | |
1179 | r = -E2BIG; | |
e125e7b6 | 1180 | if (n < msr_list.nmsrs) |
043405e1 CO |
1181 | goto out; |
1182 | r = -EFAULT; | |
1183 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
1184 | num_msrs_to_save * sizeof(u32))) | |
1185 | goto out; | |
e125e7b6 | 1186 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 CO |
1187 | &emulated_msrs, |
1188 | ARRAY_SIZE(emulated_msrs) * sizeof(u32))) | |
1189 | goto out; | |
1190 | r = 0; | |
1191 | break; | |
1192 | } | |
674eea0f AK |
1193 | case KVM_GET_SUPPORTED_CPUID: { |
1194 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
1195 | struct kvm_cpuid2 cpuid; | |
1196 | ||
1197 | r = -EFAULT; | |
1198 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
1199 | goto out; | |
1200 | r = kvm_dev_ioctl_get_supported_cpuid(&cpuid, | |
19355475 | 1201 | cpuid_arg->entries); |
674eea0f AK |
1202 | if (r) |
1203 | goto out; | |
1204 | ||
1205 | r = -EFAULT; | |
1206 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
1207 | goto out; | |
1208 | r = 0; | |
1209 | break; | |
1210 | } | |
890ca9ae HY |
1211 | case KVM_X86_GET_MCE_CAP_SUPPORTED: { |
1212 | u64 mce_cap; | |
1213 | ||
1214 | mce_cap = KVM_MCE_CAP_SUPPORTED; | |
1215 | r = -EFAULT; | |
1216 | if (copy_to_user(argp, &mce_cap, sizeof mce_cap)) | |
1217 | goto out; | |
1218 | r = 0; | |
1219 | break; | |
1220 | } | |
043405e1 CO |
1221 | default: |
1222 | r = -EINVAL; | |
1223 | } | |
1224 | out: | |
1225 | return r; | |
1226 | } | |
1227 | ||
313a3dc7 CO |
1228 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
1229 | { | |
1230 | kvm_x86_ops->vcpu_load(vcpu, cpu); | |
c8076604 | 1231 | kvm_request_guest_time_update(vcpu); |
313a3dc7 CO |
1232 | } |
1233 | ||
1234 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) | |
1235 | { | |
1236 | kvm_x86_ops->vcpu_put(vcpu); | |
9327fd11 | 1237 | kvm_put_guest_fpu(vcpu); |
313a3dc7 CO |
1238 | } |
1239 | ||
07716717 | 1240 | static int is_efer_nx(void) |
313a3dc7 | 1241 | { |
e286e86e | 1242 | unsigned long long efer = 0; |
313a3dc7 | 1243 | |
e286e86e | 1244 | rdmsrl_safe(MSR_EFER, &efer); |
07716717 DK |
1245 | return efer & EFER_NX; |
1246 | } | |
1247 | ||
1248 | static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu) | |
1249 | { | |
1250 | int i; | |
1251 | struct kvm_cpuid_entry2 *e, *entry; | |
1252 | ||
313a3dc7 | 1253 | entry = NULL; |
ad312c7c ZX |
1254 | for (i = 0; i < vcpu->arch.cpuid_nent; ++i) { |
1255 | e = &vcpu->arch.cpuid_entries[i]; | |
313a3dc7 CO |
1256 | if (e->function == 0x80000001) { |
1257 | entry = e; | |
1258 | break; | |
1259 | } | |
1260 | } | |
07716717 | 1261 | if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) { |
313a3dc7 CO |
1262 | entry->edx &= ~(1 << 20); |
1263 | printk(KERN_INFO "kvm: guest NX capability removed\n"); | |
1264 | } | |
1265 | } | |
1266 | ||
07716717 | 1267 | /* when an old userspace process fills a new kernel module */ |
313a3dc7 CO |
1268 | static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu, |
1269 | struct kvm_cpuid *cpuid, | |
1270 | struct kvm_cpuid_entry __user *entries) | |
07716717 DK |
1271 | { |
1272 | int r, i; | |
1273 | struct kvm_cpuid_entry *cpuid_entries; | |
1274 | ||
1275 | r = -E2BIG; | |
1276 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) | |
1277 | goto out; | |
1278 | r = -ENOMEM; | |
1279 | cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent); | |
1280 | if (!cpuid_entries) | |
1281 | goto out; | |
1282 | r = -EFAULT; | |
1283 | if (copy_from_user(cpuid_entries, entries, | |
1284 | cpuid->nent * sizeof(struct kvm_cpuid_entry))) | |
1285 | goto out_free; | |
1286 | for (i = 0; i < cpuid->nent; i++) { | |
ad312c7c ZX |
1287 | vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function; |
1288 | vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax; | |
1289 | vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx; | |
1290 | vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx; | |
1291 | vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx; | |
1292 | vcpu->arch.cpuid_entries[i].index = 0; | |
1293 | vcpu->arch.cpuid_entries[i].flags = 0; | |
1294 | vcpu->arch.cpuid_entries[i].padding[0] = 0; | |
1295 | vcpu->arch.cpuid_entries[i].padding[1] = 0; | |
1296 | vcpu->arch.cpuid_entries[i].padding[2] = 0; | |
1297 | } | |
1298 | vcpu->arch.cpuid_nent = cpuid->nent; | |
07716717 DK |
1299 | cpuid_fix_nx_cap(vcpu); |
1300 | r = 0; | |
1301 | ||
1302 | out_free: | |
1303 | vfree(cpuid_entries); | |
1304 | out: | |
1305 | return r; | |
1306 | } | |
1307 | ||
1308 | static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu, | |
19355475 AS |
1309 | struct kvm_cpuid2 *cpuid, |
1310 | struct kvm_cpuid_entry2 __user *entries) | |
313a3dc7 CO |
1311 | { |
1312 | int r; | |
1313 | ||
1314 | r = -E2BIG; | |
1315 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) | |
1316 | goto out; | |
1317 | r = -EFAULT; | |
ad312c7c | 1318 | if (copy_from_user(&vcpu->arch.cpuid_entries, entries, |
07716717 | 1319 | cpuid->nent * sizeof(struct kvm_cpuid_entry2))) |
313a3dc7 | 1320 | goto out; |
ad312c7c | 1321 | vcpu->arch.cpuid_nent = cpuid->nent; |
313a3dc7 CO |
1322 | return 0; |
1323 | ||
1324 | out: | |
1325 | return r; | |
1326 | } | |
1327 | ||
07716717 | 1328 | static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu, |
19355475 AS |
1329 | struct kvm_cpuid2 *cpuid, |
1330 | struct kvm_cpuid_entry2 __user *entries) | |
07716717 DK |
1331 | { |
1332 | int r; | |
1333 | ||
1334 | r = -E2BIG; | |
ad312c7c | 1335 | if (cpuid->nent < vcpu->arch.cpuid_nent) |
07716717 DK |
1336 | goto out; |
1337 | r = -EFAULT; | |
ad312c7c | 1338 | if (copy_to_user(entries, &vcpu->arch.cpuid_entries, |
19355475 | 1339 | vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2))) |
07716717 DK |
1340 | goto out; |
1341 | return 0; | |
1342 | ||
1343 | out: | |
ad312c7c | 1344 | cpuid->nent = vcpu->arch.cpuid_nent; |
07716717 DK |
1345 | return r; |
1346 | } | |
1347 | ||
07716717 | 1348 | static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function, |
19355475 | 1349 | u32 index) |
07716717 DK |
1350 | { |
1351 | entry->function = function; | |
1352 | entry->index = index; | |
1353 | cpuid_count(entry->function, entry->index, | |
19355475 | 1354 | &entry->eax, &entry->ebx, &entry->ecx, &entry->edx); |
07716717 DK |
1355 | entry->flags = 0; |
1356 | } | |
1357 | ||
7faa4ee1 AK |
1358 | #define F(x) bit(X86_FEATURE_##x) |
1359 | ||
07716717 DK |
1360 | static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, |
1361 | u32 index, int *nent, int maxnent) | |
1362 | { | |
7faa4ee1 | 1363 | unsigned f_nx = is_efer_nx() ? F(NX) : 0; |
07716717 | 1364 | #ifdef CONFIG_X86_64 |
7faa4ee1 AK |
1365 | unsigned f_lm = F(LM); |
1366 | #else | |
1367 | unsigned f_lm = 0; | |
07716717 | 1368 | #endif |
7faa4ee1 AK |
1369 | |
1370 | /* cpuid 1.edx */ | |
1371 | const u32 kvm_supported_word0_x86_features = | |
1372 | F(FPU) | F(VME) | F(DE) | F(PSE) | | |
1373 | F(TSC) | F(MSR) | F(PAE) | F(MCE) | | |
1374 | F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) | | |
1375 | F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | | |
1376 | F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) | | |
1377 | 0 /* Reserved, DS, ACPI */ | F(MMX) | | |
1378 | F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) | | |
1379 | 0 /* HTT, TM, Reserved, PBE */; | |
1380 | /* cpuid 0x80000001.edx */ | |
1381 | const u32 kvm_supported_word1_x86_features = | |
1382 | F(FPU) | F(VME) | F(DE) | F(PSE) | | |
1383 | F(TSC) | F(MSR) | F(PAE) | F(MCE) | | |
1384 | F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) | | |
1385 | F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | | |
1386 | F(PAT) | F(PSE36) | 0 /* Reserved */ | | |
1387 | f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) | | |
1388 | F(FXSR) | F(FXSR_OPT) | 0 /* GBPAGES */ | 0 /* RDTSCP */ | | |
1389 | 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW); | |
1390 | /* cpuid 1.ecx */ | |
1391 | const u32 kvm_supported_word4_x86_features = | |
d149c731 AK |
1392 | F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ | |
1393 | 0 /* DS-CPL, VMX, SMX, EST */ | | |
1394 | 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ | | |
1395 | 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ | | |
1396 | 0 /* Reserved, DCA */ | F(XMM4_1) | | |
1397 | F(XMM4_2) | 0 /* x2APIC */ | F(MOVBE) | F(POPCNT) | | |
1398 | 0 /* Reserved, XSAVE, OSXSAVE */; | |
7faa4ee1 | 1399 | /* cpuid 0x80000001.ecx */ |
07716717 | 1400 | const u32 kvm_supported_word6_x86_features = |
7faa4ee1 AK |
1401 | F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ | |
1402 | F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) | | |
1403 | F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) | | |
1404 | 0 /* SKINIT */ | 0 /* WDT */; | |
07716717 | 1405 | |
19355475 | 1406 | /* all calls to cpuid_count() should be made on the same cpu */ |
07716717 DK |
1407 | get_cpu(); |
1408 | do_cpuid_1_ent(entry, function, index); | |
1409 | ++*nent; | |
1410 | ||
1411 | switch (function) { | |
1412 | case 0: | |
1413 | entry->eax = min(entry->eax, (u32)0xb); | |
1414 | break; | |
1415 | case 1: | |
1416 | entry->edx &= kvm_supported_word0_x86_features; | |
7faa4ee1 | 1417 | entry->ecx &= kvm_supported_word4_x86_features; |
07716717 DK |
1418 | break; |
1419 | /* function 2 entries are STATEFUL. That is, repeated cpuid commands | |
1420 | * may return different values. This forces us to get_cpu() before | |
1421 | * issuing the first command, and also to emulate this annoying behavior | |
1422 | * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */ | |
1423 | case 2: { | |
1424 | int t, times = entry->eax & 0xff; | |
1425 | ||
1426 | entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC; | |
0fdf8e59 | 1427 | entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT; |
07716717 DK |
1428 | for (t = 1; t < times && *nent < maxnent; ++t) { |
1429 | do_cpuid_1_ent(&entry[t], function, 0); | |
1430 | entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC; | |
1431 | ++*nent; | |
1432 | } | |
1433 | break; | |
1434 | } | |
1435 | /* function 4 and 0xb have additional index. */ | |
1436 | case 4: { | |
14af3f3c | 1437 | int i, cache_type; |
07716717 DK |
1438 | |
1439 | entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
1440 | /* read more entries until cache_type is zero */ | |
14af3f3c HH |
1441 | for (i = 1; *nent < maxnent; ++i) { |
1442 | cache_type = entry[i - 1].eax & 0x1f; | |
07716717 DK |
1443 | if (!cache_type) |
1444 | break; | |
14af3f3c HH |
1445 | do_cpuid_1_ent(&entry[i], function, i); |
1446 | entry[i].flags |= | |
07716717 DK |
1447 | KVM_CPUID_FLAG_SIGNIFCANT_INDEX; |
1448 | ++*nent; | |
1449 | } | |
1450 | break; | |
1451 | } | |
1452 | case 0xb: { | |
14af3f3c | 1453 | int i, level_type; |
07716717 DK |
1454 | |
1455 | entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
1456 | /* read more entries until level_type is zero */ | |
14af3f3c | 1457 | for (i = 1; *nent < maxnent; ++i) { |
0853d2c1 | 1458 | level_type = entry[i - 1].ecx & 0xff00; |
07716717 DK |
1459 | if (!level_type) |
1460 | break; | |
14af3f3c HH |
1461 | do_cpuid_1_ent(&entry[i], function, i); |
1462 | entry[i].flags |= | |
07716717 DK |
1463 | KVM_CPUID_FLAG_SIGNIFCANT_INDEX; |
1464 | ++*nent; | |
1465 | } | |
1466 | break; | |
1467 | } | |
1468 | case 0x80000000: | |
1469 | entry->eax = min(entry->eax, 0x8000001a); | |
1470 | break; | |
1471 | case 0x80000001: | |
1472 | entry->edx &= kvm_supported_word1_x86_features; | |
1473 | entry->ecx &= kvm_supported_word6_x86_features; | |
1474 | break; | |
1475 | } | |
1476 | put_cpu(); | |
1477 | } | |
1478 | ||
7faa4ee1 AK |
1479 | #undef F |
1480 | ||
674eea0f | 1481 | static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid, |
19355475 | 1482 | struct kvm_cpuid_entry2 __user *entries) |
07716717 DK |
1483 | { |
1484 | struct kvm_cpuid_entry2 *cpuid_entries; | |
1485 | int limit, nent = 0, r = -E2BIG; | |
1486 | u32 func; | |
1487 | ||
1488 | if (cpuid->nent < 1) | |
1489 | goto out; | |
1490 | r = -ENOMEM; | |
1491 | cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent); | |
1492 | if (!cpuid_entries) | |
1493 | goto out; | |
1494 | ||
1495 | do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent); | |
1496 | limit = cpuid_entries[0].eax; | |
1497 | for (func = 1; func <= limit && nent < cpuid->nent; ++func) | |
1498 | do_cpuid_ent(&cpuid_entries[nent], func, 0, | |
19355475 | 1499 | &nent, cpuid->nent); |
07716717 DK |
1500 | r = -E2BIG; |
1501 | if (nent >= cpuid->nent) | |
1502 | goto out_free; | |
1503 | ||
1504 | do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent); | |
1505 | limit = cpuid_entries[nent - 1].eax; | |
1506 | for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func) | |
1507 | do_cpuid_ent(&cpuid_entries[nent], func, 0, | |
19355475 | 1508 | &nent, cpuid->nent); |
07716717 DK |
1509 | r = -EFAULT; |
1510 | if (copy_to_user(entries, cpuid_entries, | |
19355475 | 1511 | nent * sizeof(struct kvm_cpuid_entry2))) |
07716717 DK |
1512 | goto out_free; |
1513 | cpuid->nent = nent; | |
1514 | r = 0; | |
1515 | ||
1516 | out_free: | |
1517 | vfree(cpuid_entries); | |
1518 | out: | |
1519 | return r; | |
1520 | } | |
1521 | ||
313a3dc7 CO |
1522 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
1523 | struct kvm_lapic_state *s) | |
1524 | { | |
1525 | vcpu_load(vcpu); | |
ad312c7c | 1526 | memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s); |
313a3dc7 CO |
1527 | vcpu_put(vcpu); |
1528 | ||
1529 | return 0; | |
1530 | } | |
1531 | ||
1532 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
1533 | struct kvm_lapic_state *s) | |
1534 | { | |
1535 | vcpu_load(vcpu); | |
ad312c7c | 1536 | memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s); |
313a3dc7 CO |
1537 | kvm_apic_post_state_restore(vcpu); |
1538 | vcpu_put(vcpu); | |
1539 | ||
1540 | return 0; | |
1541 | } | |
1542 | ||
f77bc6a4 ZX |
1543 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
1544 | struct kvm_interrupt *irq) | |
1545 | { | |
1546 | if (irq->irq < 0 || irq->irq >= 256) | |
1547 | return -EINVAL; | |
1548 | if (irqchip_in_kernel(vcpu->kvm)) | |
1549 | return -ENXIO; | |
1550 | vcpu_load(vcpu); | |
1551 | ||
66fd3f7f | 1552 | kvm_queue_interrupt(vcpu, irq->irq, false); |
f77bc6a4 ZX |
1553 | |
1554 | vcpu_put(vcpu); | |
1555 | ||
1556 | return 0; | |
1557 | } | |
1558 | ||
c4abb7c9 JK |
1559 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
1560 | { | |
1561 | vcpu_load(vcpu); | |
1562 | kvm_inject_nmi(vcpu); | |
1563 | vcpu_put(vcpu); | |
1564 | ||
1565 | return 0; | |
1566 | } | |
1567 | ||
b209749f AK |
1568 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
1569 | struct kvm_tpr_access_ctl *tac) | |
1570 | { | |
1571 | if (tac->flags) | |
1572 | return -EINVAL; | |
1573 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
1574 | return 0; | |
1575 | } | |
1576 | ||
890ca9ae HY |
1577 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
1578 | u64 mcg_cap) | |
1579 | { | |
1580 | int r; | |
1581 | unsigned bank_num = mcg_cap & 0xff, bank; | |
1582 | ||
1583 | r = -EINVAL; | |
1584 | if (!bank_num) | |
1585 | goto out; | |
1586 | if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000)) | |
1587 | goto out; | |
1588 | r = 0; | |
1589 | vcpu->arch.mcg_cap = mcg_cap; | |
1590 | /* Init IA32_MCG_CTL to all 1s */ | |
1591 | if (mcg_cap & MCG_CTL_P) | |
1592 | vcpu->arch.mcg_ctl = ~(u64)0; | |
1593 | /* Init IA32_MCi_CTL to all 1s */ | |
1594 | for (bank = 0; bank < bank_num; bank++) | |
1595 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
1596 | out: | |
1597 | return r; | |
1598 | } | |
1599 | ||
1600 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
1601 | struct kvm_x86_mce *mce) | |
1602 | { | |
1603 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
1604 | unsigned bank_num = mcg_cap & 0xff; | |
1605 | u64 *banks = vcpu->arch.mce_banks; | |
1606 | ||
1607 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
1608 | return -EINVAL; | |
1609 | /* | |
1610 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
1611 | * reporting is disabled | |
1612 | */ | |
1613 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
1614 | vcpu->arch.mcg_ctl != ~(u64)0) | |
1615 | return 0; | |
1616 | banks += 4 * mce->bank; | |
1617 | /* | |
1618 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
1619 | * reporting is disabled for the bank | |
1620 | */ | |
1621 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
1622 | return 0; | |
1623 | if (mce->status & MCI_STATUS_UC) { | |
1624 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
1625 | !(vcpu->arch.cr4 & X86_CR4_MCE)) { | |
1626 | printk(KERN_DEBUG "kvm: set_mce: " | |
1627 | "injects mce exception while " | |
1628 | "previous one is in progress!\n"); | |
1629 | set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests); | |
1630 | return 0; | |
1631 | } | |
1632 | if (banks[1] & MCI_STATUS_VAL) | |
1633 | mce->status |= MCI_STATUS_OVER; | |
1634 | banks[2] = mce->addr; | |
1635 | banks[3] = mce->misc; | |
1636 | vcpu->arch.mcg_status = mce->mcg_status; | |
1637 | banks[1] = mce->status; | |
1638 | kvm_queue_exception(vcpu, MC_VECTOR); | |
1639 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
1640 | || !(banks[1] & MCI_STATUS_UC)) { | |
1641 | if (banks[1] & MCI_STATUS_VAL) | |
1642 | mce->status |= MCI_STATUS_OVER; | |
1643 | banks[2] = mce->addr; | |
1644 | banks[3] = mce->misc; | |
1645 | banks[1] = mce->status; | |
1646 | } else | |
1647 | banks[1] |= MCI_STATUS_OVER; | |
1648 | return 0; | |
1649 | } | |
1650 | ||
313a3dc7 CO |
1651 | long kvm_arch_vcpu_ioctl(struct file *filp, |
1652 | unsigned int ioctl, unsigned long arg) | |
1653 | { | |
1654 | struct kvm_vcpu *vcpu = filp->private_data; | |
1655 | void __user *argp = (void __user *)arg; | |
1656 | int r; | |
b772ff36 | 1657 | struct kvm_lapic_state *lapic = NULL; |
313a3dc7 CO |
1658 | |
1659 | switch (ioctl) { | |
1660 | case KVM_GET_LAPIC: { | |
b772ff36 | 1661 | lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); |
313a3dc7 | 1662 | |
b772ff36 DH |
1663 | r = -ENOMEM; |
1664 | if (!lapic) | |
1665 | goto out; | |
1666 | r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic); | |
313a3dc7 CO |
1667 | if (r) |
1668 | goto out; | |
1669 | r = -EFAULT; | |
b772ff36 | 1670 | if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
1671 | goto out; |
1672 | r = 0; | |
1673 | break; | |
1674 | } | |
1675 | case KVM_SET_LAPIC: { | |
b772ff36 DH |
1676 | lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); |
1677 | r = -ENOMEM; | |
1678 | if (!lapic) | |
1679 | goto out; | |
313a3dc7 | 1680 | r = -EFAULT; |
b772ff36 | 1681 | if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state))) |
313a3dc7 | 1682 | goto out; |
b772ff36 | 1683 | r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic); |
313a3dc7 CO |
1684 | if (r) |
1685 | goto out; | |
1686 | r = 0; | |
1687 | break; | |
1688 | } | |
f77bc6a4 ZX |
1689 | case KVM_INTERRUPT: { |
1690 | struct kvm_interrupt irq; | |
1691 | ||
1692 | r = -EFAULT; | |
1693 | if (copy_from_user(&irq, argp, sizeof irq)) | |
1694 | goto out; | |
1695 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
1696 | if (r) | |
1697 | goto out; | |
1698 | r = 0; | |
1699 | break; | |
1700 | } | |
c4abb7c9 JK |
1701 | case KVM_NMI: { |
1702 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
1703 | if (r) | |
1704 | goto out; | |
1705 | r = 0; | |
1706 | break; | |
1707 | } | |
313a3dc7 CO |
1708 | case KVM_SET_CPUID: { |
1709 | struct kvm_cpuid __user *cpuid_arg = argp; | |
1710 | struct kvm_cpuid cpuid; | |
1711 | ||
1712 | r = -EFAULT; | |
1713 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
1714 | goto out; | |
1715 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
1716 | if (r) | |
1717 | goto out; | |
1718 | break; | |
1719 | } | |
07716717 DK |
1720 | case KVM_SET_CPUID2: { |
1721 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
1722 | struct kvm_cpuid2 cpuid; | |
1723 | ||
1724 | r = -EFAULT; | |
1725 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
1726 | goto out; | |
1727 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 1728 | cpuid_arg->entries); |
07716717 DK |
1729 | if (r) |
1730 | goto out; | |
1731 | break; | |
1732 | } | |
1733 | case KVM_GET_CPUID2: { | |
1734 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
1735 | struct kvm_cpuid2 cpuid; | |
1736 | ||
1737 | r = -EFAULT; | |
1738 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
1739 | goto out; | |
1740 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 1741 | cpuid_arg->entries); |
07716717 DK |
1742 | if (r) |
1743 | goto out; | |
1744 | r = -EFAULT; | |
1745 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
1746 | goto out; | |
1747 | r = 0; | |
1748 | break; | |
1749 | } | |
313a3dc7 CO |
1750 | case KVM_GET_MSRS: |
1751 | r = msr_io(vcpu, argp, kvm_get_msr, 1); | |
1752 | break; | |
1753 | case KVM_SET_MSRS: | |
1754 | r = msr_io(vcpu, argp, do_set_msr, 0); | |
1755 | break; | |
b209749f AK |
1756 | case KVM_TPR_ACCESS_REPORTING: { |
1757 | struct kvm_tpr_access_ctl tac; | |
1758 | ||
1759 | r = -EFAULT; | |
1760 | if (copy_from_user(&tac, argp, sizeof tac)) | |
1761 | goto out; | |
1762 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
1763 | if (r) | |
1764 | goto out; | |
1765 | r = -EFAULT; | |
1766 | if (copy_to_user(argp, &tac, sizeof tac)) | |
1767 | goto out; | |
1768 | r = 0; | |
1769 | break; | |
1770 | }; | |
b93463aa AK |
1771 | case KVM_SET_VAPIC_ADDR: { |
1772 | struct kvm_vapic_addr va; | |
1773 | ||
1774 | r = -EINVAL; | |
1775 | if (!irqchip_in_kernel(vcpu->kvm)) | |
1776 | goto out; | |
1777 | r = -EFAULT; | |
1778 | if (copy_from_user(&va, argp, sizeof va)) | |
1779 | goto out; | |
1780 | r = 0; | |
1781 | kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); | |
1782 | break; | |
1783 | } | |
890ca9ae HY |
1784 | case KVM_X86_SETUP_MCE: { |
1785 | u64 mcg_cap; | |
1786 | ||
1787 | r = -EFAULT; | |
1788 | if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) | |
1789 | goto out; | |
1790 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
1791 | break; | |
1792 | } | |
1793 | case KVM_X86_SET_MCE: { | |
1794 | struct kvm_x86_mce mce; | |
1795 | ||
1796 | r = -EFAULT; | |
1797 | if (copy_from_user(&mce, argp, sizeof mce)) | |
1798 | goto out; | |
1799 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
1800 | break; | |
1801 | } | |
313a3dc7 CO |
1802 | default: |
1803 | r = -EINVAL; | |
1804 | } | |
1805 | out: | |
7a6ce84c | 1806 | kfree(lapic); |
313a3dc7 CO |
1807 | return r; |
1808 | } | |
1809 | ||
1fe779f8 CO |
1810 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
1811 | { | |
1812 | int ret; | |
1813 | ||
1814 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
1815 | return -1; | |
1816 | ret = kvm_x86_ops->set_tss_addr(kvm, addr); | |
1817 | return ret; | |
1818 | } | |
1819 | ||
1820 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, | |
1821 | u32 kvm_nr_mmu_pages) | |
1822 | { | |
1823 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
1824 | return -EINVAL; | |
1825 | ||
72dc67a6 | 1826 | down_write(&kvm->slots_lock); |
7c8a83b7 | 1827 | spin_lock(&kvm->mmu_lock); |
1fe779f8 CO |
1828 | |
1829 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 1830 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 1831 | |
7c8a83b7 | 1832 | spin_unlock(&kvm->mmu_lock); |
72dc67a6 | 1833 | up_write(&kvm->slots_lock); |
1fe779f8 CO |
1834 | return 0; |
1835 | } | |
1836 | ||
1837 | static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) | |
1838 | { | |
f05e70ac | 1839 | return kvm->arch.n_alloc_mmu_pages; |
1fe779f8 CO |
1840 | } |
1841 | ||
e9f85cde ZX |
1842 | gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn) |
1843 | { | |
1844 | int i; | |
1845 | struct kvm_mem_alias *alias; | |
1846 | ||
d69fb81f ZX |
1847 | for (i = 0; i < kvm->arch.naliases; ++i) { |
1848 | alias = &kvm->arch.aliases[i]; | |
e9f85cde ZX |
1849 | if (gfn >= alias->base_gfn |
1850 | && gfn < alias->base_gfn + alias->npages) | |
1851 | return alias->target_gfn + gfn - alias->base_gfn; | |
1852 | } | |
1853 | return gfn; | |
1854 | } | |
1855 | ||
1fe779f8 CO |
1856 | /* |
1857 | * Set a new alias region. Aliases map a portion of physical memory into | |
1858 | * another portion. This is useful for memory windows, for example the PC | |
1859 | * VGA region. | |
1860 | */ | |
1861 | static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm, | |
1862 | struct kvm_memory_alias *alias) | |
1863 | { | |
1864 | int r, n; | |
1865 | struct kvm_mem_alias *p; | |
1866 | ||
1867 | r = -EINVAL; | |
1868 | /* General sanity checks */ | |
1869 | if (alias->memory_size & (PAGE_SIZE - 1)) | |
1870 | goto out; | |
1871 | if (alias->guest_phys_addr & (PAGE_SIZE - 1)) | |
1872 | goto out; | |
1873 | if (alias->slot >= KVM_ALIAS_SLOTS) | |
1874 | goto out; | |
1875 | if (alias->guest_phys_addr + alias->memory_size | |
1876 | < alias->guest_phys_addr) | |
1877 | goto out; | |
1878 | if (alias->target_phys_addr + alias->memory_size | |
1879 | < alias->target_phys_addr) | |
1880 | goto out; | |
1881 | ||
72dc67a6 | 1882 | down_write(&kvm->slots_lock); |
a1708ce8 | 1883 | spin_lock(&kvm->mmu_lock); |
1fe779f8 | 1884 | |
d69fb81f | 1885 | p = &kvm->arch.aliases[alias->slot]; |
1fe779f8 CO |
1886 | p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT; |
1887 | p->npages = alias->memory_size >> PAGE_SHIFT; | |
1888 | p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT; | |
1889 | ||
1890 | for (n = KVM_ALIAS_SLOTS; n > 0; --n) | |
d69fb81f | 1891 | if (kvm->arch.aliases[n - 1].npages) |
1fe779f8 | 1892 | break; |
d69fb81f | 1893 | kvm->arch.naliases = n; |
1fe779f8 | 1894 | |
a1708ce8 | 1895 | spin_unlock(&kvm->mmu_lock); |
1fe779f8 CO |
1896 | kvm_mmu_zap_all(kvm); |
1897 | ||
72dc67a6 | 1898 | up_write(&kvm->slots_lock); |
1fe779f8 CO |
1899 | |
1900 | return 0; | |
1901 | ||
1902 | out: | |
1903 | return r; | |
1904 | } | |
1905 | ||
1906 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
1907 | { | |
1908 | int r; | |
1909 | ||
1910 | r = 0; | |
1911 | switch (chip->chip_id) { | |
1912 | case KVM_IRQCHIP_PIC_MASTER: | |
1913 | memcpy(&chip->chip.pic, | |
1914 | &pic_irqchip(kvm)->pics[0], | |
1915 | sizeof(struct kvm_pic_state)); | |
1916 | break; | |
1917 | case KVM_IRQCHIP_PIC_SLAVE: | |
1918 | memcpy(&chip->chip.pic, | |
1919 | &pic_irqchip(kvm)->pics[1], | |
1920 | sizeof(struct kvm_pic_state)); | |
1921 | break; | |
1922 | case KVM_IRQCHIP_IOAPIC: | |
1923 | memcpy(&chip->chip.ioapic, | |
1924 | ioapic_irqchip(kvm), | |
1925 | sizeof(struct kvm_ioapic_state)); | |
1926 | break; | |
1927 | default: | |
1928 | r = -EINVAL; | |
1929 | break; | |
1930 | } | |
1931 | return r; | |
1932 | } | |
1933 | ||
1934 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
1935 | { | |
1936 | int r; | |
1937 | ||
1938 | r = 0; | |
1939 | switch (chip->chip_id) { | |
1940 | case KVM_IRQCHIP_PIC_MASTER: | |
1941 | memcpy(&pic_irqchip(kvm)->pics[0], | |
1942 | &chip->chip.pic, | |
1943 | sizeof(struct kvm_pic_state)); | |
1944 | break; | |
1945 | case KVM_IRQCHIP_PIC_SLAVE: | |
1946 | memcpy(&pic_irqchip(kvm)->pics[1], | |
1947 | &chip->chip.pic, | |
1948 | sizeof(struct kvm_pic_state)); | |
1949 | break; | |
1950 | case KVM_IRQCHIP_IOAPIC: | |
1951 | memcpy(ioapic_irqchip(kvm), | |
1952 | &chip->chip.ioapic, | |
1953 | sizeof(struct kvm_ioapic_state)); | |
1954 | break; | |
1955 | default: | |
1956 | r = -EINVAL; | |
1957 | break; | |
1958 | } | |
1959 | kvm_pic_update_irq(pic_irqchip(kvm)); | |
1960 | return r; | |
1961 | } | |
1962 | ||
e0f63cb9 SY |
1963 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
1964 | { | |
1965 | int r = 0; | |
1966 | ||
1967 | memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state)); | |
1968 | return r; | |
1969 | } | |
1970 | ||
1971 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
1972 | { | |
1973 | int r = 0; | |
1974 | ||
1975 | memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state)); | |
1976 | kvm_pit_load_count(kvm, 0, ps->channels[0].count); | |
1977 | return r; | |
1978 | } | |
1979 | ||
52d939a0 MT |
1980 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
1981 | struct kvm_reinject_control *control) | |
1982 | { | |
1983 | if (!kvm->arch.vpit) | |
1984 | return -ENXIO; | |
1985 | kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject; | |
1986 | return 0; | |
1987 | } | |
1988 | ||
5bb064dc ZX |
1989 | /* |
1990 | * Get (and clear) the dirty memory log for a memory slot. | |
1991 | */ | |
1992 | int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, | |
1993 | struct kvm_dirty_log *log) | |
1994 | { | |
1995 | int r; | |
1996 | int n; | |
1997 | struct kvm_memory_slot *memslot; | |
1998 | int is_dirty = 0; | |
1999 | ||
72dc67a6 | 2000 | down_write(&kvm->slots_lock); |
5bb064dc ZX |
2001 | |
2002 | r = kvm_get_dirty_log(kvm, log, &is_dirty); | |
2003 | if (r) | |
2004 | goto out; | |
2005 | ||
2006 | /* If nothing is dirty, don't bother messing with page tables. */ | |
2007 | if (is_dirty) { | |
7c8a83b7 | 2008 | spin_lock(&kvm->mmu_lock); |
5bb064dc | 2009 | kvm_mmu_slot_remove_write_access(kvm, log->slot); |
7c8a83b7 | 2010 | spin_unlock(&kvm->mmu_lock); |
5bb064dc ZX |
2011 | kvm_flush_remote_tlbs(kvm); |
2012 | memslot = &kvm->memslots[log->slot]; | |
2013 | n = ALIGN(memslot->npages, BITS_PER_LONG) / 8; | |
2014 | memset(memslot->dirty_bitmap, 0, n); | |
2015 | } | |
2016 | r = 0; | |
2017 | out: | |
72dc67a6 | 2018 | up_write(&kvm->slots_lock); |
5bb064dc ZX |
2019 | return r; |
2020 | } | |
2021 | ||
1fe779f8 CO |
2022 | long kvm_arch_vm_ioctl(struct file *filp, |
2023 | unsigned int ioctl, unsigned long arg) | |
2024 | { | |
2025 | struct kvm *kvm = filp->private_data; | |
2026 | void __user *argp = (void __user *)arg; | |
2027 | int r = -EINVAL; | |
f0d66275 DH |
2028 | /* |
2029 | * This union makes it completely explicit to gcc-3.x | |
2030 | * that these two variables' stack usage should be | |
2031 | * combined, not added together. | |
2032 | */ | |
2033 | union { | |
2034 | struct kvm_pit_state ps; | |
2035 | struct kvm_memory_alias alias; | |
2036 | } u; | |
1fe779f8 CO |
2037 | |
2038 | switch (ioctl) { | |
2039 | case KVM_SET_TSS_ADDR: | |
2040 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
2041 | if (r < 0) | |
2042 | goto out; | |
2043 | break; | |
2044 | case KVM_SET_MEMORY_REGION: { | |
2045 | struct kvm_memory_region kvm_mem; | |
2046 | struct kvm_userspace_memory_region kvm_userspace_mem; | |
2047 | ||
2048 | r = -EFAULT; | |
2049 | if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem)) | |
2050 | goto out; | |
2051 | kvm_userspace_mem.slot = kvm_mem.slot; | |
2052 | kvm_userspace_mem.flags = kvm_mem.flags; | |
2053 | kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr; | |
2054 | kvm_userspace_mem.memory_size = kvm_mem.memory_size; | |
2055 | r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0); | |
2056 | if (r) | |
2057 | goto out; | |
2058 | break; | |
2059 | } | |
2060 | case KVM_SET_NR_MMU_PAGES: | |
2061 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
2062 | if (r) | |
2063 | goto out; | |
2064 | break; | |
2065 | case KVM_GET_NR_MMU_PAGES: | |
2066 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
2067 | break; | |
f0d66275 | 2068 | case KVM_SET_MEMORY_ALIAS: |
1fe779f8 | 2069 | r = -EFAULT; |
f0d66275 | 2070 | if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias))) |
1fe779f8 | 2071 | goto out; |
f0d66275 | 2072 | r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias); |
1fe779f8 CO |
2073 | if (r) |
2074 | goto out; | |
2075 | break; | |
1fe779f8 CO |
2076 | case KVM_CREATE_IRQCHIP: |
2077 | r = -ENOMEM; | |
d7deeeb0 ZX |
2078 | kvm->arch.vpic = kvm_create_pic(kvm); |
2079 | if (kvm->arch.vpic) { | |
1fe779f8 CO |
2080 | r = kvm_ioapic_init(kvm); |
2081 | if (r) { | |
d7deeeb0 ZX |
2082 | kfree(kvm->arch.vpic); |
2083 | kvm->arch.vpic = NULL; | |
1fe779f8 CO |
2084 | goto out; |
2085 | } | |
2086 | } else | |
2087 | goto out; | |
399ec807 AK |
2088 | r = kvm_setup_default_irq_routing(kvm); |
2089 | if (r) { | |
2090 | kfree(kvm->arch.vpic); | |
2091 | kfree(kvm->arch.vioapic); | |
2092 | goto out; | |
2093 | } | |
1fe779f8 | 2094 | break; |
7837699f | 2095 | case KVM_CREATE_PIT: |
269e05e4 AK |
2096 | mutex_lock(&kvm->lock); |
2097 | r = -EEXIST; | |
2098 | if (kvm->arch.vpit) | |
2099 | goto create_pit_unlock; | |
7837699f SY |
2100 | r = -ENOMEM; |
2101 | kvm->arch.vpit = kvm_create_pit(kvm); | |
2102 | if (kvm->arch.vpit) | |
2103 | r = 0; | |
269e05e4 AK |
2104 | create_pit_unlock: |
2105 | mutex_unlock(&kvm->lock); | |
7837699f | 2106 | break; |
4925663a | 2107 | case KVM_IRQ_LINE_STATUS: |
1fe779f8 CO |
2108 | case KVM_IRQ_LINE: { |
2109 | struct kvm_irq_level irq_event; | |
2110 | ||
2111 | r = -EFAULT; | |
2112 | if (copy_from_user(&irq_event, argp, sizeof irq_event)) | |
2113 | goto out; | |
2114 | if (irqchip_in_kernel(kvm)) { | |
4925663a | 2115 | __s32 status; |
1fe779f8 | 2116 | mutex_lock(&kvm->lock); |
4925663a GN |
2117 | status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, |
2118 | irq_event.irq, irq_event.level); | |
1fe779f8 | 2119 | mutex_unlock(&kvm->lock); |
4925663a GN |
2120 | if (ioctl == KVM_IRQ_LINE_STATUS) { |
2121 | irq_event.status = status; | |
2122 | if (copy_to_user(argp, &irq_event, | |
2123 | sizeof irq_event)) | |
2124 | goto out; | |
2125 | } | |
1fe779f8 CO |
2126 | r = 0; |
2127 | } | |
2128 | break; | |
2129 | } | |
2130 | case KVM_GET_IRQCHIP: { | |
2131 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
f0d66275 | 2132 | struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL); |
1fe779f8 | 2133 | |
f0d66275 DH |
2134 | r = -ENOMEM; |
2135 | if (!chip) | |
1fe779f8 | 2136 | goto out; |
f0d66275 DH |
2137 | r = -EFAULT; |
2138 | if (copy_from_user(chip, argp, sizeof *chip)) | |
2139 | goto get_irqchip_out; | |
1fe779f8 CO |
2140 | r = -ENXIO; |
2141 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
2142 | goto get_irqchip_out; |
2143 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 2144 | if (r) |
f0d66275 | 2145 | goto get_irqchip_out; |
1fe779f8 | 2146 | r = -EFAULT; |
f0d66275 DH |
2147 | if (copy_to_user(argp, chip, sizeof *chip)) |
2148 | goto get_irqchip_out; | |
1fe779f8 | 2149 | r = 0; |
f0d66275 DH |
2150 | get_irqchip_out: |
2151 | kfree(chip); | |
2152 | if (r) | |
2153 | goto out; | |
1fe779f8 CO |
2154 | break; |
2155 | } | |
2156 | case KVM_SET_IRQCHIP: { | |
2157 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
f0d66275 | 2158 | struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL); |
1fe779f8 | 2159 | |
f0d66275 DH |
2160 | r = -ENOMEM; |
2161 | if (!chip) | |
1fe779f8 | 2162 | goto out; |
f0d66275 DH |
2163 | r = -EFAULT; |
2164 | if (copy_from_user(chip, argp, sizeof *chip)) | |
2165 | goto set_irqchip_out; | |
1fe779f8 CO |
2166 | r = -ENXIO; |
2167 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
2168 | goto set_irqchip_out; |
2169 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
1fe779f8 | 2170 | if (r) |
f0d66275 | 2171 | goto set_irqchip_out; |
1fe779f8 | 2172 | r = 0; |
f0d66275 DH |
2173 | set_irqchip_out: |
2174 | kfree(chip); | |
2175 | if (r) | |
2176 | goto out; | |
1fe779f8 CO |
2177 | break; |
2178 | } | |
e0f63cb9 | 2179 | case KVM_GET_PIT: { |
e0f63cb9 | 2180 | r = -EFAULT; |
f0d66275 | 2181 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
2182 | goto out; |
2183 | r = -ENXIO; | |
2184 | if (!kvm->arch.vpit) | |
2185 | goto out; | |
f0d66275 | 2186 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
2187 | if (r) |
2188 | goto out; | |
2189 | r = -EFAULT; | |
f0d66275 | 2190 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
2191 | goto out; |
2192 | r = 0; | |
2193 | break; | |
2194 | } | |
2195 | case KVM_SET_PIT: { | |
e0f63cb9 | 2196 | r = -EFAULT; |
f0d66275 | 2197 | if (copy_from_user(&u.ps, argp, sizeof u.ps)) |
e0f63cb9 SY |
2198 | goto out; |
2199 | r = -ENXIO; | |
2200 | if (!kvm->arch.vpit) | |
2201 | goto out; | |
f0d66275 | 2202 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
e0f63cb9 SY |
2203 | if (r) |
2204 | goto out; | |
2205 | r = 0; | |
2206 | break; | |
2207 | } | |
52d939a0 MT |
2208 | case KVM_REINJECT_CONTROL: { |
2209 | struct kvm_reinject_control control; | |
2210 | r = -EFAULT; | |
2211 | if (copy_from_user(&control, argp, sizeof(control))) | |
2212 | goto out; | |
2213 | r = kvm_vm_ioctl_reinject(kvm, &control); | |
2214 | if (r) | |
2215 | goto out; | |
2216 | r = 0; | |
2217 | break; | |
2218 | } | |
1fe779f8 CO |
2219 | default: |
2220 | ; | |
2221 | } | |
2222 | out: | |
2223 | return r; | |
2224 | } | |
2225 | ||
a16b043c | 2226 | static void kvm_init_msr_list(void) |
043405e1 CO |
2227 | { |
2228 | u32 dummy[2]; | |
2229 | unsigned i, j; | |
2230 | ||
2231 | for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) { | |
2232 | if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) | |
2233 | continue; | |
2234 | if (j < i) | |
2235 | msrs_to_save[j] = msrs_to_save[i]; | |
2236 | j++; | |
2237 | } | |
2238 | num_msrs_to_save = j; | |
2239 | } | |
2240 | ||
bbd9b64e CO |
2241 | /* |
2242 | * Only apic need an MMIO device hook, so shortcut now.. | |
2243 | */ | |
2244 | static struct kvm_io_device *vcpu_find_pervcpu_dev(struct kvm_vcpu *vcpu, | |
92760499 LV |
2245 | gpa_t addr, int len, |
2246 | int is_write) | |
bbd9b64e CO |
2247 | { |
2248 | struct kvm_io_device *dev; | |
2249 | ||
ad312c7c ZX |
2250 | if (vcpu->arch.apic) { |
2251 | dev = &vcpu->arch.apic->dev; | |
92760499 | 2252 | if (dev->in_range(dev, addr, len, is_write)) |
bbd9b64e CO |
2253 | return dev; |
2254 | } | |
2255 | return NULL; | |
2256 | } | |
2257 | ||
2258 | ||
2259 | static struct kvm_io_device *vcpu_find_mmio_dev(struct kvm_vcpu *vcpu, | |
92760499 LV |
2260 | gpa_t addr, int len, |
2261 | int is_write) | |
bbd9b64e CO |
2262 | { |
2263 | struct kvm_io_device *dev; | |
2264 | ||
92760499 | 2265 | dev = vcpu_find_pervcpu_dev(vcpu, addr, len, is_write); |
bbd9b64e | 2266 | if (dev == NULL) |
92760499 LV |
2267 | dev = kvm_io_bus_find_dev(&vcpu->kvm->mmio_bus, addr, len, |
2268 | is_write); | |
bbd9b64e CO |
2269 | return dev; |
2270 | } | |
2271 | ||
cded19f3 HE |
2272 | static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes, |
2273 | struct kvm_vcpu *vcpu) | |
bbd9b64e CO |
2274 | { |
2275 | void *data = val; | |
10589a46 | 2276 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
2277 | |
2278 | while (bytes) { | |
ad312c7c | 2279 | gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr); |
bbd9b64e | 2280 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 2281 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
2282 | int ret; |
2283 | ||
10589a46 MT |
2284 | if (gpa == UNMAPPED_GVA) { |
2285 | r = X86EMUL_PROPAGATE_FAULT; | |
2286 | goto out; | |
2287 | } | |
77c2002e | 2288 | ret = kvm_read_guest(vcpu->kvm, gpa, data, toread); |
10589a46 MT |
2289 | if (ret < 0) { |
2290 | r = X86EMUL_UNHANDLEABLE; | |
2291 | goto out; | |
2292 | } | |
bbd9b64e | 2293 | |
77c2002e IE |
2294 | bytes -= toread; |
2295 | data += toread; | |
2296 | addr += toread; | |
bbd9b64e | 2297 | } |
10589a46 | 2298 | out: |
10589a46 | 2299 | return r; |
bbd9b64e | 2300 | } |
77c2002e | 2301 | |
cded19f3 HE |
2302 | static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes, |
2303 | struct kvm_vcpu *vcpu) | |
77c2002e IE |
2304 | { |
2305 | void *data = val; | |
2306 | int r = X86EMUL_CONTINUE; | |
2307 | ||
2308 | while (bytes) { | |
2309 | gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr); | |
2310 | unsigned offset = addr & (PAGE_SIZE-1); | |
2311 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
2312 | int ret; | |
2313 | ||
2314 | if (gpa == UNMAPPED_GVA) { | |
2315 | r = X86EMUL_PROPAGATE_FAULT; | |
2316 | goto out; | |
2317 | } | |
2318 | ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite); | |
2319 | if (ret < 0) { | |
2320 | r = X86EMUL_UNHANDLEABLE; | |
2321 | goto out; | |
2322 | } | |
2323 | ||
2324 | bytes -= towrite; | |
2325 | data += towrite; | |
2326 | addr += towrite; | |
2327 | } | |
2328 | out: | |
2329 | return r; | |
2330 | } | |
2331 | ||
bbd9b64e | 2332 | |
bbd9b64e CO |
2333 | static int emulator_read_emulated(unsigned long addr, |
2334 | void *val, | |
2335 | unsigned int bytes, | |
2336 | struct kvm_vcpu *vcpu) | |
2337 | { | |
2338 | struct kvm_io_device *mmio_dev; | |
2339 | gpa_t gpa; | |
2340 | ||
2341 | if (vcpu->mmio_read_completed) { | |
2342 | memcpy(val, vcpu->mmio_data, bytes); | |
2343 | vcpu->mmio_read_completed = 0; | |
2344 | return X86EMUL_CONTINUE; | |
2345 | } | |
2346 | ||
ad312c7c | 2347 | gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr); |
bbd9b64e CO |
2348 | |
2349 | /* For APIC access vmexit */ | |
2350 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
2351 | goto mmio; | |
2352 | ||
77c2002e IE |
2353 | if (kvm_read_guest_virt(addr, val, bytes, vcpu) |
2354 | == X86EMUL_CONTINUE) | |
bbd9b64e CO |
2355 | return X86EMUL_CONTINUE; |
2356 | if (gpa == UNMAPPED_GVA) | |
2357 | return X86EMUL_PROPAGATE_FAULT; | |
2358 | ||
2359 | mmio: | |
2360 | /* | |
2361 | * Is this MMIO handled locally? | |
2362 | */ | |
10589a46 | 2363 | mutex_lock(&vcpu->kvm->lock); |
92760499 | 2364 | mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 0); |
bbd9b64e CO |
2365 | if (mmio_dev) { |
2366 | kvm_iodevice_read(mmio_dev, gpa, bytes, val); | |
10589a46 | 2367 | mutex_unlock(&vcpu->kvm->lock); |
bbd9b64e CO |
2368 | return X86EMUL_CONTINUE; |
2369 | } | |
10589a46 | 2370 | mutex_unlock(&vcpu->kvm->lock); |
bbd9b64e CO |
2371 | |
2372 | vcpu->mmio_needed = 1; | |
2373 | vcpu->mmio_phys_addr = gpa; | |
2374 | vcpu->mmio_size = bytes; | |
2375 | vcpu->mmio_is_write = 0; | |
2376 | ||
2377 | return X86EMUL_UNHANDLEABLE; | |
2378 | } | |
2379 | ||
3200f405 | 2380 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
9f811285 | 2381 | const void *val, int bytes) |
bbd9b64e CO |
2382 | { |
2383 | int ret; | |
2384 | ||
2385 | ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes); | |
9f811285 | 2386 | if (ret < 0) |
bbd9b64e | 2387 | return 0; |
ad218f85 | 2388 | kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1); |
bbd9b64e CO |
2389 | return 1; |
2390 | } | |
2391 | ||
2392 | static int emulator_write_emulated_onepage(unsigned long addr, | |
2393 | const void *val, | |
2394 | unsigned int bytes, | |
2395 | struct kvm_vcpu *vcpu) | |
2396 | { | |
2397 | struct kvm_io_device *mmio_dev; | |
10589a46 MT |
2398 | gpa_t gpa; |
2399 | ||
10589a46 | 2400 | gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr); |
bbd9b64e CO |
2401 | |
2402 | if (gpa == UNMAPPED_GVA) { | |
c3c91fee | 2403 | kvm_inject_page_fault(vcpu, addr, 2); |
bbd9b64e CO |
2404 | return X86EMUL_PROPAGATE_FAULT; |
2405 | } | |
2406 | ||
2407 | /* For APIC access vmexit */ | |
2408 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
2409 | goto mmio; | |
2410 | ||
2411 | if (emulator_write_phys(vcpu, gpa, val, bytes)) | |
2412 | return X86EMUL_CONTINUE; | |
2413 | ||
2414 | mmio: | |
2415 | /* | |
2416 | * Is this MMIO handled locally? | |
2417 | */ | |
10589a46 | 2418 | mutex_lock(&vcpu->kvm->lock); |
92760499 | 2419 | mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 1); |
bbd9b64e CO |
2420 | if (mmio_dev) { |
2421 | kvm_iodevice_write(mmio_dev, gpa, bytes, val); | |
10589a46 | 2422 | mutex_unlock(&vcpu->kvm->lock); |
bbd9b64e CO |
2423 | return X86EMUL_CONTINUE; |
2424 | } | |
10589a46 | 2425 | mutex_unlock(&vcpu->kvm->lock); |
bbd9b64e CO |
2426 | |
2427 | vcpu->mmio_needed = 1; | |
2428 | vcpu->mmio_phys_addr = gpa; | |
2429 | vcpu->mmio_size = bytes; | |
2430 | vcpu->mmio_is_write = 1; | |
2431 | memcpy(vcpu->mmio_data, val, bytes); | |
2432 | ||
2433 | return X86EMUL_CONTINUE; | |
2434 | } | |
2435 | ||
2436 | int emulator_write_emulated(unsigned long addr, | |
2437 | const void *val, | |
2438 | unsigned int bytes, | |
2439 | struct kvm_vcpu *vcpu) | |
2440 | { | |
2441 | /* Crossing a page boundary? */ | |
2442 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
2443 | int rc, now; | |
2444 | ||
2445 | now = -addr & ~PAGE_MASK; | |
2446 | rc = emulator_write_emulated_onepage(addr, val, now, vcpu); | |
2447 | if (rc != X86EMUL_CONTINUE) | |
2448 | return rc; | |
2449 | addr += now; | |
2450 | val += now; | |
2451 | bytes -= now; | |
2452 | } | |
2453 | return emulator_write_emulated_onepage(addr, val, bytes, vcpu); | |
2454 | } | |
2455 | EXPORT_SYMBOL_GPL(emulator_write_emulated); | |
2456 | ||
2457 | static int emulator_cmpxchg_emulated(unsigned long addr, | |
2458 | const void *old, | |
2459 | const void *new, | |
2460 | unsigned int bytes, | |
2461 | struct kvm_vcpu *vcpu) | |
2462 | { | |
2463 | static int reported; | |
2464 | ||
2465 | if (!reported) { | |
2466 | reported = 1; | |
2467 | printk(KERN_WARNING "kvm: emulating exchange as write\n"); | |
2468 | } | |
2bacc55c MT |
2469 | #ifndef CONFIG_X86_64 |
2470 | /* guests cmpxchg8b have to be emulated atomically */ | |
2471 | if (bytes == 8) { | |
10589a46 | 2472 | gpa_t gpa; |
2bacc55c | 2473 | struct page *page; |
c0b49b0d | 2474 | char *kaddr; |
2bacc55c MT |
2475 | u64 val; |
2476 | ||
10589a46 MT |
2477 | gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr); |
2478 | ||
2bacc55c MT |
2479 | if (gpa == UNMAPPED_GVA || |
2480 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
2481 | goto emul_write; | |
2482 | ||
2483 | if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) | |
2484 | goto emul_write; | |
2485 | ||
2486 | val = *(u64 *)new; | |
72dc67a6 | 2487 | |
2bacc55c | 2488 | page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
72dc67a6 | 2489 | |
c0b49b0d AM |
2490 | kaddr = kmap_atomic(page, KM_USER0); |
2491 | set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val); | |
2492 | kunmap_atomic(kaddr, KM_USER0); | |
2bacc55c MT |
2493 | kvm_release_page_dirty(page); |
2494 | } | |
3200f405 | 2495 | emul_write: |
2bacc55c MT |
2496 | #endif |
2497 | ||
bbd9b64e CO |
2498 | return emulator_write_emulated(addr, new, bytes, vcpu); |
2499 | } | |
2500 | ||
2501 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
2502 | { | |
2503 | return kvm_x86_ops->get_segment_base(vcpu, seg); | |
2504 | } | |
2505 | ||
2506 | int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address) | |
2507 | { | |
a7052897 | 2508 | kvm_mmu_invlpg(vcpu, address); |
bbd9b64e CO |
2509 | return X86EMUL_CONTINUE; |
2510 | } | |
2511 | ||
2512 | int emulate_clts(struct kvm_vcpu *vcpu) | |
2513 | { | |
54e445ca | 2514 | KVMTRACE_0D(CLTS, vcpu, handler); |
ad312c7c | 2515 | kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS); |
bbd9b64e CO |
2516 | return X86EMUL_CONTINUE; |
2517 | } | |
2518 | ||
2519 | int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest) | |
2520 | { | |
2521 | struct kvm_vcpu *vcpu = ctxt->vcpu; | |
2522 | ||
2523 | switch (dr) { | |
2524 | case 0 ... 3: | |
2525 | *dest = kvm_x86_ops->get_dr(vcpu, dr); | |
2526 | return X86EMUL_CONTINUE; | |
2527 | default: | |
b8688d51 | 2528 | pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr); |
bbd9b64e CO |
2529 | return X86EMUL_UNHANDLEABLE; |
2530 | } | |
2531 | } | |
2532 | ||
2533 | int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value) | |
2534 | { | |
2535 | unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U; | |
2536 | int exception; | |
2537 | ||
2538 | kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception); | |
2539 | if (exception) { | |
2540 | /* FIXME: better handling */ | |
2541 | return X86EMUL_UNHANDLEABLE; | |
2542 | } | |
2543 | return X86EMUL_CONTINUE; | |
2544 | } | |
2545 | ||
2546 | void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context) | |
2547 | { | |
bbd9b64e | 2548 | u8 opcodes[4]; |
5fdbf976 | 2549 | unsigned long rip = kvm_rip_read(vcpu); |
bbd9b64e CO |
2550 | unsigned long rip_linear; |
2551 | ||
f76c710d | 2552 | if (!printk_ratelimit()) |
bbd9b64e CO |
2553 | return; |
2554 | ||
25be4608 GC |
2555 | rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS); |
2556 | ||
77c2002e | 2557 | kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu); |
bbd9b64e CO |
2558 | |
2559 | printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n", | |
2560 | context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]); | |
bbd9b64e CO |
2561 | } |
2562 | EXPORT_SYMBOL_GPL(kvm_report_emulation_failure); | |
2563 | ||
14af3f3c | 2564 | static struct x86_emulate_ops emulate_ops = { |
77c2002e | 2565 | .read_std = kvm_read_guest_virt, |
bbd9b64e CO |
2566 | .read_emulated = emulator_read_emulated, |
2567 | .write_emulated = emulator_write_emulated, | |
2568 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
2569 | }; | |
2570 | ||
5fdbf976 MT |
2571 | static void cache_all_regs(struct kvm_vcpu *vcpu) |
2572 | { | |
2573 | kvm_register_read(vcpu, VCPU_REGS_RAX); | |
2574 | kvm_register_read(vcpu, VCPU_REGS_RSP); | |
2575 | kvm_register_read(vcpu, VCPU_REGS_RIP); | |
2576 | vcpu->arch.regs_dirty = ~0; | |
2577 | } | |
2578 | ||
bbd9b64e CO |
2579 | int emulate_instruction(struct kvm_vcpu *vcpu, |
2580 | struct kvm_run *run, | |
2581 | unsigned long cr2, | |
2582 | u16 error_code, | |
571008da | 2583 | int emulation_type) |
bbd9b64e | 2584 | { |
310b5d30 | 2585 | int r, shadow_mask; |
571008da | 2586 | struct decode_cache *c; |
bbd9b64e | 2587 | |
26eef70c | 2588 | kvm_clear_exception_queue(vcpu); |
ad312c7c | 2589 | vcpu->arch.mmio_fault_cr2 = cr2; |
5fdbf976 MT |
2590 | /* |
2591 | * TODO: fix x86_emulate.c to use guest_read/write_register | |
2592 | * instead of direct ->regs accesses, can save hundred cycles | |
2593 | * on Intel for instructions that don't read/change RSP, for | |
2594 | * for example. | |
2595 | */ | |
2596 | cache_all_regs(vcpu); | |
bbd9b64e CO |
2597 | |
2598 | vcpu->mmio_is_write = 0; | |
ad312c7c | 2599 | vcpu->arch.pio.string = 0; |
bbd9b64e | 2600 | |
571008da | 2601 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
bbd9b64e CO |
2602 | int cs_db, cs_l; |
2603 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
2604 | ||
ad312c7c ZX |
2605 | vcpu->arch.emulate_ctxt.vcpu = vcpu; |
2606 | vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu); | |
2607 | vcpu->arch.emulate_ctxt.mode = | |
2608 | (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM) | |
bbd9b64e CO |
2609 | ? X86EMUL_MODE_REAL : cs_l |
2610 | ? X86EMUL_MODE_PROT64 : cs_db | |
2611 | ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16; | |
2612 | ||
ad312c7c | 2613 | r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops); |
571008da SY |
2614 | |
2615 | /* Reject the instructions other than VMCALL/VMMCALL when | |
2616 | * try to emulate invalid opcode */ | |
2617 | c = &vcpu->arch.emulate_ctxt.decode; | |
2618 | if ((emulation_type & EMULTYPE_TRAP_UD) && | |
2619 | (!(c->twobyte && c->b == 0x01 && | |
2620 | (c->modrm_reg == 0 || c->modrm_reg == 3) && | |
2621 | c->modrm_mod == 3 && c->modrm_rm == 1))) | |
2622 | return EMULATE_FAIL; | |
2623 | ||
f2b5756b | 2624 | ++vcpu->stat.insn_emulation; |
bbd9b64e | 2625 | if (r) { |
f2b5756b | 2626 | ++vcpu->stat.insn_emulation_fail; |
bbd9b64e CO |
2627 | if (kvm_mmu_unprotect_page_virt(vcpu, cr2)) |
2628 | return EMULATE_DONE; | |
2629 | return EMULATE_FAIL; | |
2630 | } | |
2631 | } | |
2632 | ||
ba8afb6b GN |
2633 | if (emulation_type & EMULTYPE_SKIP) { |
2634 | kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip); | |
2635 | return EMULATE_DONE; | |
2636 | } | |
2637 | ||
ad312c7c | 2638 | r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops); |
310b5d30 GC |
2639 | shadow_mask = vcpu->arch.emulate_ctxt.interruptibility; |
2640 | ||
2641 | if (r == 0) | |
2642 | kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask); | |
bbd9b64e | 2643 | |
ad312c7c | 2644 | if (vcpu->arch.pio.string) |
bbd9b64e CO |
2645 | return EMULATE_DO_MMIO; |
2646 | ||
2647 | if ((r || vcpu->mmio_is_write) && run) { | |
2648 | run->exit_reason = KVM_EXIT_MMIO; | |
2649 | run->mmio.phys_addr = vcpu->mmio_phys_addr; | |
2650 | memcpy(run->mmio.data, vcpu->mmio_data, 8); | |
2651 | run->mmio.len = vcpu->mmio_size; | |
2652 | run->mmio.is_write = vcpu->mmio_is_write; | |
2653 | } | |
2654 | ||
2655 | if (r) { | |
2656 | if (kvm_mmu_unprotect_page_virt(vcpu, cr2)) | |
2657 | return EMULATE_DONE; | |
2658 | if (!vcpu->mmio_needed) { | |
2659 | kvm_report_emulation_failure(vcpu, "mmio"); | |
2660 | return EMULATE_FAIL; | |
2661 | } | |
2662 | return EMULATE_DO_MMIO; | |
2663 | } | |
2664 | ||
ad312c7c | 2665 | kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags); |
bbd9b64e CO |
2666 | |
2667 | if (vcpu->mmio_is_write) { | |
2668 | vcpu->mmio_needed = 0; | |
2669 | return EMULATE_DO_MMIO; | |
2670 | } | |
2671 | ||
2672 | return EMULATE_DONE; | |
2673 | } | |
2674 | EXPORT_SYMBOL_GPL(emulate_instruction); | |
2675 | ||
de7d789a CO |
2676 | static int pio_copy_data(struct kvm_vcpu *vcpu) |
2677 | { | |
ad312c7c | 2678 | void *p = vcpu->arch.pio_data; |
0f346074 | 2679 | gva_t q = vcpu->arch.pio.guest_gva; |
de7d789a | 2680 | unsigned bytes; |
0f346074 | 2681 | int ret; |
de7d789a | 2682 | |
ad312c7c ZX |
2683 | bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count; |
2684 | if (vcpu->arch.pio.in) | |
0f346074 | 2685 | ret = kvm_write_guest_virt(q, p, bytes, vcpu); |
de7d789a | 2686 | else |
0f346074 IE |
2687 | ret = kvm_read_guest_virt(q, p, bytes, vcpu); |
2688 | return ret; | |
de7d789a CO |
2689 | } |
2690 | ||
2691 | int complete_pio(struct kvm_vcpu *vcpu) | |
2692 | { | |
ad312c7c | 2693 | struct kvm_pio_request *io = &vcpu->arch.pio; |
de7d789a CO |
2694 | long delta; |
2695 | int r; | |
5fdbf976 | 2696 | unsigned long val; |
de7d789a CO |
2697 | |
2698 | if (!io->string) { | |
5fdbf976 MT |
2699 | if (io->in) { |
2700 | val = kvm_register_read(vcpu, VCPU_REGS_RAX); | |
2701 | memcpy(&val, vcpu->arch.pio_data, io->size); | |
2702 | kvm_register_write(vcpu, VCPU_REGS_RAX, val); | |
2703 | } | |
de7d789a CO |
2704 | } else { |
2705 | if (io->in) { | |
2706 | r = pio_copy_data(vcpu); | |
5fdbf976 | 2707 | if (r) |
de7d789a | 2708 | return r; |
de7d789a CO |
2709 | } |
2710 | ||
2711 | delta = 1; | |
2712 | if (io->rep) { | |
2713 | delta *= io->cur_count; | |
2714 | /* | |
2715 | * The size of the register should really depend on | |
2716 | * current address size. | |
2717 | */ | |
5fdbf976 MT |
2718 | val = kvm_register_read(vcpu, VCPU_REGS_RCX); |
2719 | val -= delta; | |
2720 | kvm_register_write(vcpu, VCPU_REGS_RCX, val); | |
de7d789a CO |
2721 | } |
2722 | if (io->down) | |
2723 | delta = -delta; | |
2724 | delta *= io->size; | |
5fdbf976 MT |
2725 | if (io->in) { |
2726 | val = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
2727 | val += delta; | |
2728 | kvm_register_write(vcpu, VCPU_REGS_RDI, val); | |
2729 | } else { | |
2730 | val = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
2731 | val += delta; | |
2732 | kvm_register_write(vcpu, VCPU_REGS_RSI, val); | |
2733 | } | |
de7d789a CO |
2734 | } |
2735 | ||
de7d789a CO |
2736 | io->count -= io->cur_count; |
2737 | io->cur_count = 0; | |
2738 | ||
2739 | return 0; | |
2740 | } | |
2741 | ||
2742 | static void kernel_pio(struct kvm_io_device *pio_dev, | |
2743 | struct kvm_vcpu *vcpu, | |
2744 | void *pd) | |
2745 | { | |
2746 | /* TODO: String I/O for in kernel device */ | |
2747 | ||
2748 | mutex_lock(&vcpu->kvm->lock); | |
ad312c7c ZX |
2749 | if (vcpu->arch.pio.in) |
2750 | kvm_iodevice_read(pio_dev, vcpu->arch.pio.port, | |
2751 | vcpu->arch.pio.size, | |
de7d789a CO |
2752 | pd); |
2753 | else | |
ad312c7c ZX |
2754 | kvm_iodevice_write(pio_dev, vcpu->arch.pio.port, |
2755 | vcpu->arch.pio.size, | |
de7d789a CO |
2756 | pd); |
2757 | mutex_unlock(&vcpu->kvm->lock); | |
2758 | } | |
2759 | ||
2760 | static void pio_string_write(struct kvm_io_device *pio_dev, | |
2761 | struct kvm_vcpu *vcpu) | |
2762 | { | |
ad312c7c ZX |
2763 | struct kvm_pio_request *io = &vcpu->arch.pio; |
2764 | void *pd = vcpu->arch.pio_data; | |
de7d789a CO |
2765 | int i; |
2766 | ||
2767 | mutex_lock(&vcpu->kvm->lock); | |
2768 | for (i = 0; i < io->cur_count; i++) { | |
2769 | kvm_iodevice_write(pio_dev, io->port, | |
2770 | io->size, | |
2771 | pd); | |
2772 | pd += io->size; | |
2773 | } | |
2774 | mutex_unlock(&vcpu->kvm->lock); | |
2775 | } | |
2776 | ||
2777 | static struct kvm_io_device *vcpu_find_pio_dev(struct kvm_vcpu *vcpu, | |
92760499 LV |
2778 | gpa_t addr, int len, |
2779 | int is_write) | |
de7d789a | 2780 | { |
92760499 | 2781 | return kvm_io_bus_find_dev(&vcpu->kvm->pio_bus, addr, len, is_write); |
de7d789a CO |
2782 | } |
2783 | ||
2784 | int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in, | |
2785 | int size, unsigned port) | |
2786 | { | |
2787 | struct kvm_io_device *pio_dev; | |
5fdbf976 | 2788 | unsigned long val; |
de7d789a CO |
2789 | |
2790 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
2791 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; | |
ad312c7c | 2792 | vcpu->run->io.size = vcpu->arch.pio.size = size; |
de7d789a | 2793 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; |
ad312c7c ZX |
2794 | vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1; |
2795 | vcpu->run->io.port = vcpu->arch.pio.port = port; | |
2796 | vcpu->arch.pio.in = in; | |
2797 | vcpu->arch.pio.string = 0; | |
2798 | vcpu->arch.pio.down = 0; | |
ad312c7c | 2799 | vcpu->arch.pio.rep = 0; |
de7d789a | 2800 | |
2714d1d3 FEL |
2801 | if (vcpu->run->io.direction == KVM_EXIT_IO_IN) |
2802 | KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size, | |
2803 | handler); | |
2804 | else | |
2805 | KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size, | |
2806 | handler); | |
2807 | ||
5fdbf976 MT |
2808 | val = kvm_register_read(vcpu, VCPU_REGS_RAX); |
2809 | memcpy(vcpu->arch.pio_data, &val, 4); | |
de7d789a | 2810 | |
92760499 | 2811 | pio_dev = vcpu_find_pio_dev(vcpu, port, size, !in); |
de7d789a | 2812 | if (pio_dev) { |
ad312c7c | 2813 | kernel_pio(pio_dev, vcpu, vcpu->arch.pio_data); |
de7d789a CO |
2814 | complete_pio(vcpu); |
2815 | return 1; | |
2816 | } | |
2817 | return 0; | |
2818 | } | |
2819 | EXPORT_SYMBOL_GPL(kvm_emulate_pio); | |
2820 | ||
2821 | int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in, | |
2822 | int size, unsigned long count, int down, | |
2823 | gva_t address, int rep, unsigned port) | |
2824 | { | |
2825 | unsigned now, in_page; | |
0f346074 | 2826 | int ret = 0; |
de7d789a CO |
2827 | struct kvm_io_device *pio_dev; |
2828 | ||
2829 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
2830 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; | |
ad312c7c | 2831 | vcpu->run->io.size = vcpu->arch.pio.size = size; |
de7d789a | 2832 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; |
ad312c7c ZX |
2833 | vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count; |
2834 | vcpu->run->io.port = vcpu->arch.pio.port = port; | |
2835 | vcpu->arch.pio.in = in; | |
2836 | vcpu->arch.pio.string = 1; | |
2837 | vcpu->arch.pio.down = down; | |
ad312c7c | 2838 | vcpu->arch.pio.rep = rep; |
de7d789a | 2839 | |
2714d1d3 FEL |
2840 | if (vcpu->run->io.direction == KVM_EXIT_IO_IN) |
2841 | KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size, | |
2842 | handler); | |
2843 | else | |
2844 | KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size, | |
2845 | handler); | |
2846 | ||
de7d789a CO |
2847 | if (!count) { |
2848 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
2849 | return 1; | |
2850 | } | |
2851 | ||
2852 | if (!down) | |
2853 | in_page = PAGE_SIZE - offset_in_page(address); | |
2854 | else | |
2855 | in_page = offset_in_page(address) + size; | |
2856 | now = min(count, (unsigned long)in_page / size); | |
0f346074 | 2857 | if (!now) |
de7d789a | 2858 | now = 1; |
de7d789a CO |
2859 | if (down) { |
2860 | /* | |
2861 | * String I/O in reverse. Yuck. Kill the guest, fix later. | |
2862 | */ | |
2863 | pr_unimpl(vcpu, "guest string pio down\n"); | |
c1a5d4f9 | 2864 | kvm_inject_gp(vcpu, 0); |
de7d789a CO |
2865 | return 1; |
2866 | } | |
2867 | vcpu->run->io.count = now; | |
ad312c7c | 2868 | vcpu->arch.pio.cur_count = now; |
de7d789a | 2869 | |
ad312c7c | 2870 | if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count) |
de7d789a CO |
2871 | kvm_x86_ops->skip_emulated_instruction(vcpu); |
2872 | ||
0f346074 | 2873 | vcpu->arch.pio.guest_gva = address; |
de7d789a | 2874 | |
92760499 LV |
2875 | pio_dev = vcpu_find_pio_dev(vcpu, port, |
2876 | vcpu->arch.pio.cur_count, | |
2877 | !vcpu->arch.pio.in); | |
ad312c7c | 2878 | if (!vcpu->arch.pio.in) { |
de7d789a CO |
2879 | /* string PIO write */ |
2880 | ret = pio_copy_data(vcpu); | |
0f346074 IE |
2881 | if (ret == X86EMUL_PROPAGATE_FAULT) { |
2882 | kvm_inject_gp(vcpu, 0); | |
2883 | return 1; | |
2884 | } | |
2885 | if (ret == 0 && pio_dev) { | |
de7d789a CO |
2886 | pio_string_write(pio_dev, vcpu); |
2887 | complete_pio(vcpu); | |
ad312c7c | 2888 | if (vcpu->arch.pio.count == 0) |
de7d789a CO |
2889 | ret = 1; |
2890 | } | |
2891 | } else if (pio_dev) | |
2892 | pr_unimpl(vcpu, "no string pio read support yet, " | |
2893 | "port %x size %d count %ld\n", | |
2894 | port, size, count); | |
2895 | ||
2896 | return ret; | |
2897 | } | |
2898 | EXPORT_SYMBOL_GPL(kvm_emulate_pio_string); | |
2899 | ||
c8076604 GH |
2900 | static void bounce_off(void *info) |
2901 | { | |
2902 | /* nothing */ | |
2903 | } | |
2904 | ||
2905 | static unsigned int ref_freq; | |
2906 | static unsigned long tsc_khz_ref; | |
2907 | ||
2908 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, | |
2909 | void *data) | |
2910 | { | |
2911 | struct cpufreq_freqs *freq = data; | |
2912 | struct kvm *kvm; | |
2913 | struct kvm_vcpu *vcpu; | |
2914 | int i, send_ipi = 0; | |
2915 | ||
2916 | if (!ref_freq) | |
2917 | ref_freq = freq->old; | |
2918 | ||
2919 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) | |
2920 | return 0; | |
2921 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
2922 | return 0; | |
2923 | per_cpu(cpu_tsc_khz, freq->cpu) = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new); | |
2924 | ||
2925 | spin_lock(&kvm_lock); | |
2926 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
2927 | for (i = 0; i < KVM_MAX_VCPUS; ++i) { | |
2928 | vcpu = kvm->vcpus[i]; | |
2929 | if (!vcpu) | |
2930 | continue; | |
2931 | if (vcpu->cpu != freq->cpu) | |
2932 | continue; | |
2933 | if (!kvm_request_guest_time_update(vcpu)) | |
2934 | continue; | |
2935 | if (vcpu->cpu != smp_processor_id()) | |
2936 | send_ipi++; | |
2937 | } | |
2938 | } | |
2939 | spin_unlock(&kvm_lock); | |
2940 | ||
2941 | if (freq->old < freq->new && send_ipi) { | |
2942 | /* | |
2943 | * We upscale the frequency. Must make the guest | |
2944 | * doesn't see old kvmclock values while running with | |
2945 | * the new frequency, otherwise we risk the guest sees | |
2946 | * time go backwards. | |
2947 | * | |
2948 | * In case we update the frequency for another cpu | |
2949 | * (which might be in guest context) send an interrupt | |
2950 | * to kick the cpu out of guest context. Next time | |
2951 | * guest context is entered kvmclock will be updated, | |
2952 | * so the guest will not see stale values. | |
2953 | */ | |
2954 | smp_call_function_single(freq->cpu, bounce_off, NULL, 1); | |
2955 | } | |
2956 | return 0; | |
2957 | } | |
2958 | ||
2959 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
2960 | .notifier_call = kvmclock_cpufreq_notifier | |
2961 | }; | |
2962 | ||
f8c16bba | 2963 | int kvm_arch_init(void *opaque) |
043405e1 | 2964 | { |
c8076604 | 2965 | int r, cpu; |
f8c16bba ZX |
2966 | struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque; |
2967 | ||
f8c16bba ZX |
2968 | if (kvm_x86_ops) { |
2969 | printk(KERN_ERR "kvm: already loaded the other module\n"); | |
56c6d28a ZX |
2970 | r = -EEXIST; |
2971 | goto out; | |
f8c16bba ZX |
2972 | } |
2973 | ||
2974 | if (!ops->cpu_has_kvm_support()) { | |
2975 | printk(KERN_ERR "kvm: no hardware support\n"); | |
56c6d28a ZX |
2976 | r = -EOPNOTSUPP; |
2977 | goto out; | |
f8c16bba ZX |
2978 | } |
2979 | if (ops->disabled_by_bios()) { | |
2980 | printk(KERN_ERR "kvm: disabled by bios\n"); | |
56c6d28a ZX |
2981 | r = -EOPNOTSUPP; |
2982 | goto out; | |
f8c16bba ZX |
2983 | } |
2984 | ||
97db56ce AK |
2985 | r = kvm_mmu_module_init(); |
2986 | if (r) | |
2987 | goto out; | |
2988 | ||
2989 | kvm_init_msr_list(); | |
2990 | ||
f8c16bba | 2991 | kvm_x86_ops = ops; |
56c6d28a | 2992 | kvm_mmu_set_nonpresent_ptes(0ull, 0ull); |
7b52345e SY |
2993 | kvm_mmu_set_base_ptes(PT_PRESENT_MASK); |
2994 | kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, | |
4b12f0de | 2995 | PT_DIRTY_MASK, PT64_NX_MASK, 0); |
c8076604 GH |
2996 | |
2997 | for_each_possible_cpu(cpu) | |
2998 | per_cpu(cpu_tsc_khz, cpu) = tsc_khz; | |
2999 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { | |
3000 | tsc_khz_ref = tsc_khz; | |
3001 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, | |
3002 | CPUFREQ_TRANSITION_NOTIFIER); | |
3003 | } | |
3004 | ||
f8c16bba | 3005 | return 0; |
56c6d28a ZX |
3006 | |
3007 | out: | |
56c6d28a | 3008 | return r; |
043405e1 | 3009 | } |
8776e519 | 3010 | |
f8c16bba ZX |
3011 | void kvm_arch_exit(void) |
3012 | { | |
888d256e JK |
3013 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
3014 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
3015 | CPUFREQ_TRANSITION_NOTIFIER); | |
f8c16bba | 3016 | kvm_x86_ops = NULL; |
56c6d28a ZX |
3017 | kvm_mmu_module_exit(); |
3018 | } | |
f8c16bba | 3019 | |
8776e519 HB |
3020 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) |
3021 | { | |
3022 | ++vcpu->stat.halt_exits; | |
2714d1d3 | 3023 | KVMTRACE_0D(HLT, vcpu, handler); |
8776e519 | 3024 | if (irqchip_in_kernel(vcpu->kvm)) { |
a4535290 | 3025 | vcpu->arch.mp_state = KVM_MP_STATE_HALTED; |
8776e519 HB |
3026 | return 1; |
3027 | } else { | |
3028 | vcpu->run->exit_reason = KVM_EXIT_HLT; | |
3029 | return 0; | |
3030 | } | |
3031 | } | |
3032 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); | |
3033 | ||
2f333bcb MT |
3034 | static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0, |
3035 | unsigned long a1) | |
3036 | { | |
3037 | if (is_long_mode(vcpu)) | |
3038 | return a0; | |
3039 | else | |
3040 | return a0 | ((gpa_t)a1 << 32); | |
3041 | } | |
3042 | ||
8776e519 HB |
3043 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
3044 | { | |
3045 | unsigned long nr, a0, a1, a2, a3, ret; | |
2f333bcb | 3046 | int r = 1; |
8776e519 | 3047 | |
5fdbf976 MT |
3048 | nr = kvm_register_read(vcpu, VCPU_REGS_RAX); |
3049 | a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
3050 | a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
3051 | a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
3052 | a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
8776e519 | 3053 | |
2714d1d3 FEL |
3054 | KVMTRACE_1D(VMMCALL, vcpu, (u32)nr, handler); |
3055 | ||
8776e519 HB |
3056 | if (!is_long_mode(vcpu)) { |
3057 | nr &= 0xFFFFFFFF; | |
3058 | a0 &= 0xFFFFFFFF; | |
3059 | a1 &= 0xFFFFFFFF; | |
3060 | a2 &= 0xFFFFFFFF; | |
3061 | a3 &= 0xFFFFFFFF; | |
3062 | } | |
3063 | ||
3064 | switch (nr) { | |
b93463aa AK |
3065 | case KVM_HC_VAPIC_POLL_IRQ: |
3066 | ret = 0; | |
3067 | break; | |
2f333bcb MT |
3068 | case KVM_HC_MMU_OP: |
3069 | r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret); | |
3070 | break; | |
8776e519 HB |
3071 | default: |
3072 | ret = -KVM_ENOSYS; | |
3073 | break; | |
3074 | } | |
5fdbf976 | 3075 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); |
f11c3a8d | 3076 | ++vcpu->stat.hypercalls; |
2f333bcb | 3077 | return r; |
8776e519 HB |
3078 | } |
3079 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
3080 | ||
3081 | int kvm_fix_hypercall(struct kvm_vcpu *vcpu) | |
3082 | { | |
3083 | char instruction[3]; | |
3084 | int ret = 0; | |
5fdbf976 | 3085 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 3086 | |
8776e519 HB |
3087 | |
3088 | /* | |
3089 | * Blow out the MMU to ensure that no other VCPU has an active mapping | |
3090 | * to ensure that the updated hypercall appears atomically across all | |
3091 | * VCPUs. | |
3092 | */ | |
3093 | kvm_mmu_zap_all(vcpu->kvm); | |
3094 | ||
8776e519 | 3095 | kvm_x86_ops->patch_hypercall(vcpu, instruction); |
5fdbf976 | 3096 | if (emulator_write_emulated(rip, instruction, 3, vcpu) |
8776e519 HB |
3097 | != X86EMUL_CONTINUE) |
3098 | ret = -EFAULT; | |
3099 | ||
8776e519 HB |
3100 | return ret; |
3101 | } | |
3102 | ||
3103 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) | |
3104 | { | |
3105 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; | |
3106 | } | |
3107 | ||
3108 | void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base) | |
3109 | { | |
3110 | struct descriptor_table dt = { limit, base }; | |
3111 | ||
3112 | kvm_x86_ops->set_gdt(vcpu, &dt); | |
3113 | } | |
3114 | ||
3115 | void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base) | |
3116 | { | |
3117 | struct descriptor_table dt = { limit, base }; | |
3118 | ||
3119 | kvm_x86_ops->set_idt(vcpu, &dt); | |
3120 | } | |
3121 | ||
3122 | void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw, | |
3123 | unsigned long *rflags) | |
3124 | { | |
2d3ad1f4 | 3125 | kvm_lmsw(vcpu, msw); |
8776e519 HB |
3126 | *rflags = kvm_x86_ops->get_rflags(vcpu); |
3127 | } | |
3128 | ||
3129 | unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr) | |
3130 | { | |
54e445ca JR |
3131 | unsigned long value; |
3132 | ||
8776e519 HB |
3133 | kvm_x86_ops->decache_cr4_guest_bits(vcpu); |
3134 | switch (cr) { | |
3135 | case 0: | |
54e445ca JR |
3136 | value = vcpu->arch.cr0; |
3137 | break; | |
8776e519 | 3138 | case 2: |
54e445ca JR |
3139 | value = vcpu->arch.cr2; |
3140 | break; | |
8776e519 | 3141 | case 3: |
54e445ca JR |
3142 | value = vcpu->arch.cr3; |
3143 | break; | |
8776e519 | 3144 | case 4: |
54e445ca JR |
3145 | value = vcpu->arch.cr4; |
3146 | break; | |
152ff9be | 3147 | case 8: |
54e445ca JR |
3148 | value = kvm_get_cr8(vcpu); |
3149 | break; | |
8776e519 | 3150 | default: |
b8688d51 | 3151 | vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr); |
8776e519 HB |
3152 | return 0; |
3153 | } | |
54e445ca JR |
3154 | KVMTRACE_3D(CR_READ, vcpu, (u32)cr, (u32)value, |
3155 | (u32)((u64)value >> 32), handler); | |
3156 | ||
3157 | return value; | |
8776e519 HB |
3158 | } |
3159 | ||
3160 | void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val, | |
3161 | unsigned long *rflags) | |
3162 | { | |
54e445ca JR |
3163 | KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)val, |
3164 | (u32)((u64)val >> 32), handler); | |
3165 | ||
8776e519 HB |
3166 | switch (cr) { |
3167 | case 0: | |
2d3ad1f4 | 3168 | kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val)); |
8776e519 HB |
3169 | *rflags = kvm_x86_ops->get_rflags(vcpu); |
3170 | break; | |
3171 | case 2: | |
ad312c7c | 3172 | vcpu->arch.cr2 = val; |
8776e519 HB |
3173 | break; |
3174 | case 3: | |
2d3ad1f4 | 3175 | kvm_set_cr3(vcpu, val); |
8776e519 HB |
3176 | break; |
3177 | case 4: | |
2d3ad1f4 | 3178 | kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val)); |
8776e519 | 3179 | break; |
152ff9be | 3180 | case 8: |
2d3ad1f4 | 3181 | kvm_set_cr8(vcpu, val & 0xfUL); |
152ff9be | 3182 | break; |
8776e519 | 3183 | default: |
b8688d51 | 3184 | vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr); |
8776e519 HB |
3185 | } |
3186 | } | |
3187 | ||
07716717 DK |
3188 | static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i) |
3189 | { | |
ad312c7c ZX |
3190 | struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i]; |
3191 | int j, nent = vcpu->arch.cpuid_nent; | |
07716717 DK |
3192 | |
3193 | e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT; | |
3194 | /* when no next entry is found, the current entry[i] is reselected */ | |
0fdf8e59 | 3195 | for (j = i + 1; ; j = (j + 1) % nent) { |
ad312c7c | 3196 | struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j]; |
07716717 DK |
3197 | if (ej->function == e->function) { |
3198 | ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT; | |
3199 | return j; | |
3200 | } | |
3201 | } | |
3202 | return 0; /* silence gcc, even though control never reaches here */ | |
3203 | } | |
3204 | ||
3205 | /* find an entry with matching function, matching index (if needed), and that | |
3206 | * should be read next (if it's stateful) */ | |
3207 | static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e, | |
3208 | u32 function, u32 index) | |
3209 | { | |
3210 | if (e->function != function) | |
3211 | return 0; | |
3212 | if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index) | |
3213 | return 0; | |
3214 | if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) && | |
19355475 | 3215 | !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT)) |
07716717 DK |
3216 | return 0; |
3217 | return 1; | |
3218 | } | |
3219 | ||
d8017474 AG |
3220 | struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu, |
3221 | u32 function, u32 index) | |
8776e519 HB |
3222 | { |
3223 | int i; | |
d8017474 | 3224 | struct kvm_cpuid_entry2 *best = NULL; |
8776e519 | 3225 | |
ad312c7c | 3226 | for (i = 0; i < vcpu->arch.cpuid_nent; ++i) { |
d8017474 AG |
3227 | struct kvm_cpuid_entry2 *e; |
3228 | ||
ad312c7c | 3229 | e = &vcpu->arch.cpuid_entries[i]; |
07716717 DK |
3230 | if (is_matching_cpuid_entry(e, function, index)) { |
3231 | if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) | |
3232 | move_to_next_stateful_cpuid_entry(vcpu, i); | |
8776e519 HB |
3233 | best = e; |
3234 | break; | |
3235 | } | |
3236 | /* | |
3237 | * Both basic or both extended? | |
3238 | */ | |
3239 | if (((e->function ^ function) & 0x80000000) == 0) | |
3240 | if (!best || e->function > best->function) | |
3241 | best = e; | |
3242 | } | |
d8017474 AG |
3243 | return best; |
3244 | } | |
3245 | ||
82725b20 DE |
3246 | int cpuid_maxphyaddr(struct kvm_vcpu *vcpu) |
3247 | { | |
3248 | struct kvm_cpuid_entry2 *best; | |
3249 | ||
3250 | best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0); | |
3251 | if (best) | |
3252 | return best->eax & 0xff; | |
3253 | return 36; | |
3254 | } | |
3255 | ||
d8017474 AG |
3256 | void kvm_emulate_cpuid(struct kvm_vcpu *vcpu) |
3257 | { | |
3258 | u32 function, index; | |
3259 | struct kvm_cpuid_entry2 *best; | |
3260 | ||
3261 | function = kvm_register_read(vcpu, VCPU_REGS_RAX); | |
3262 | index = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
3263 | kvm_register_write(vcpu, VCPU_REGS_RAX, 0); | |
3264 | kvm_register_write(vcpu, VCPU_REGS_RBX, 0); | |
3265 | kvm_register_write(vcpu, VCPU_REGS_RCX, 0); | |
3266 | kvm_register_write(vcpu, VCPU_REGS_RDX, 0); | |
3267 | best = kvm_find_cpuid_entry(vcpu, function, index); | |
8776e519 | 3268 | if (best) { |
5fdbf976 MT |
3269 | kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax); |
3270 | kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx); | |
3271 | kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx); | |
3272 | kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx); | |
8776e519 | 3273 | } |
8776e519 | 3274 | kvm_x86_ops->skip_emulated_instruction(vcpu); |
2714d1d3 | 3275 | KVMTRACE_5D(CPUID, vcpu, function, |
5fdbf976 MT |
3276 | (u32)kvm_register_read(vcpu, VCPU_REGS_RAX), |
3277 | (u32)kvm_register_read(vcpu, VCPU_REGS_RBX), | |
3278 | (u32)kvm_register_read(vcpu, VCPU_REGS_RCX), | |
3279 | (u32)kvm_register_read(vcpu, VCPU_REGS_RDX), handler); | |
8776e519 HB |
3280 | } |
3281 | EXPORT_SYMBOL_GPL(kvm_emulate_cpuid); | |
d0752060 | 3282 | |
b6c7a5dc HB |
3283 | /* |
3284 | * Check if userspace requested an interrupt window, and that the | |
3285 | * interrupt window is open. | |
3286 | * | |
3287 | * No need to exit to userspace if we already have an interrupt queued. | |
3288 | */ | |
3289 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu, | |
3290 | struct kvm_run *kvm_run) | |
3291 | { | |
8061823a | 3292 | return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) && |
b6c7a5dc | 3293 | kvm_run->request_interrupt_window && |
5df56646 | 3294 | kvm_arch_interrupt_allowed(vcpu)); |
b6c7a5dc HB |
3295 | } |
3296 | ||
3297 | static void post_kvm_run_save(struct kvm_vcpu *vcpu, | |
3298 | struct kvm_run *kvm_run) | |
3299 | { | |
3300 | kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0; | |
2d3ad1f4 | 3301 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 3302 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
4531220b | 3303 | if (irqchip_in_kernel(vcpu->kvm)) |
b6c7a5dc | 3304 | kvm_run->ready_for_interrupt_injection = 1; |
4531220b | 3305 | else |
b6c7a5dc | 3306 | kvm_run->ready_for_interrupt_injection = |
fa9726b0 GN |
3307 | kvm_arch_interrupt_allowed(vcpu) && |
3308 | !kvm_cpu_has_interrupt(vcpu) && | |
3309 | !kvm_event_needs_reinjection(vcpu); | |
b6c7a5dc HB |
3310 | } |
3311 | ||
b93463aa AK |
3312 | static void vapic_enter(struct kvm_vcpu *vcpu) |
3313 | { | |
3314 | struct kvm_lapic *apic = vcpu->arch.apic; | |
3315 | struct page *page; | |
3316 | ||
3317 | if (!apic || !apic->vapic_addr) | |
3318 | return; | |
3319 | ||
3320 | page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT); | |
72dc67a6 IE |
3321 | |
3322 | vcpu->arch.apic->vapic_page = page; | |
b93463aa AK |
3323 | } |
3324 | ||
3325 | static void vapic_exit(struct kvm_vcpu *vcpu) | |
3326 | { | |
3327 | struct kvm_lapic *apic = vcpu->arch.apic; | |
3328 | ||
3329 | if (!apic || !apic->vapic_addr) | |
3330 | return; | |
3331 | ||
f8b78fa3 | 3332 | down_read(&vcpu->kvm->slots_lock); |
b93463aa AK |
3333 | kvm_release_page_dirty(apic->vapic_page); |
3334 | mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT); | |
f8b78fa3 | 3335 | up_read(&vcpu->kvm->slots_lock); |
b93463aa AK |
3336 | } |
3337 | ||
95ba8273 GN |
3338 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
3339 | { | |
3340 | int max_irr, tpr; | |
3341 | ||
3342 | if (!kvm_x86_ops->update_cr8_intercept) | |
3343 | return; | |
3344 | ||
8db3baa2 GN |
3345 | if (!vcpu->arch.apic->vapic_addr) |
3346 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
3347 | else | |
3348 | max_irr = -1; | |
95ba8273 GN |
3349 | |
3350 | if (max_irr != -1) | |
3351 | max_irr >>= 4; | |
3352 | ||
3353 | tpr = kvm_lapic_get_cr8(vcpu); | |
3354 | ||
3355 | kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); | |
3356 | } | |
3357 | ||
6a8b1d13 | 3358 | static void inject_pending_irq(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
95ba8273 | 3359 | { |
6a8b1d13 GN |
3360 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
3361 | kvm_x86_ops->set_interrupt_shadow(vcpu, 0); | |
3362 | ||
95ba8273 GN |
3363 | /* try to reinject previous events if any */ |
3364 | if (vcpu->arch.nmi_injected) { | |
3365 | kvm_x86_ops->set_nmi(vcpu); | |
3366 | return; | |
3367 | } | |
3368 | ||
3369 | if (vcpu->arch.interrupt.pending) { | |
66fd3f7f | 3370 | kvm_x86_ops->set_irq(vcpu); |
95ba8273 GN |
3371 | return; |
3372 | } | |
3373 | ||
3374 | /* try to inject new event if pending */ | |
3375 | if (vcpu->arch.nmi_pending) { | |
3376 | if (kvm_x86_ops->nmi_allowed(vcpu)) { | |
3377 | vcpu->arch.nmi_pending = false; | |
3378 | vcpu->arch.nmi_injected = true; | |
3379 | kvm_x86_ops->set_nmi(vcpu); | |
3380 | } | |
3381 | } else if (kvm_cpu_has_interrupt(vcpu)) { | |
3382 | if (kvm_x86_ops->interrupt_allowed(vcpu)) { | |
66fd3f7f GN |
3383 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), |
3384 | false); | |
3385 | kvm_x86_ops->set_irq(vcpu); | |
95ba8273 GN |
3386 | } |
3387 | } | |
3388 | } | |
3389 | ||
d7690175 | 3390 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
b6c7a5dc HB |
3391 | { |
3392 | int r; | |
6a8b1d13 GN |
3393 | bool req_int_win = !irqchip_in_kernel(vcpu->kvm) && |
3394 | kvm_run->request_interrupt_window; | |
b6c7a5dc | 3395 | |
2e53d63a MT |
3396 | if (vcpu->requests) |
3397 | if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests)) | |
3398 | kvm_mmu_unload(vcpu); | |
3399 | ||
b6c7a5dc HB |
3400 | r = kvm_mmu_reload(vcpu); |
3401 | if (unlikely(r)) | |
3402 | goto out; | |
3403 | ||
2f52d58c AK |
3404 | if (vcpu->requests) { |
3405 | if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests)) | |
2f599714 | 3406 | __kvm_migrate_timers(vcpu); |
c8076604 GH |
3407 | if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests)) |
3408 | kvm_write_guest_time(vcpu); | |
4731d4c7 MT |
3409 | if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests)) |
3410 | kvm_mmu_sync_roots(vcpu); | |
d4acf7e7 MT |
3411 | if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests)) |
3412 | kvm_x86_ops->tlb_flush(vcpu); | |
b93463aa AK |
3413 | if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS, |
3414 | &vcpu->requests)) { | |
3415 | kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS; | |
3416 | r = 0; | |
3417 | goto out; | |
3418 | } | |
71c4dfaf JR |
3419 | if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) { |
3420 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
3421 | r = 0; | |
3422 | goto out; | |
3423 | } | |
2f52d58c | 3424 | } |
b93463aa | 3425 | |
b6c7a5dc HB |
3426 | preempt_disable(); |
3427 | ||
3428 | kvm_x86_ops->prepare_guest_switch(vcpu); | |
3429 | kvm_load_guest_fpu(vcpu); | |
3430 | ||
3431 | local_irq_disable(); | |
3432 | ||
32f88400 MT |
3433 | clear_bit(KVM_REQ_KICK, &vcpu->requests); |
3434 | smp_mb__after_clear_bit(); | |
3435 | ||
d7690175 | 3436 | if (vcpu->requests || need_resched() || signal_pending(current)) { |
6c142801 AK |
3437 | local_irq_enable(); |
3438 | preempt_enable(); | |
3439 | r = 1; | |
3440 | goto out; | |
3441 | } | |
3442 | ||
ad312c7c | 3443 | if (vcpu->arch.exception.pending) |
298101da | 3444 | __queue_exception(vcpu); |
eb9774f0 | 3445 | else |
95ba8273 | 3446 | inject_pending_irq(vcpu, kvm_run); |
b6c7a5dc | 3447 | |
6a8b1d13 GN |
3448 | /* enable NMI/IRQ window open exits if needed */ |
3449 | if (vcpu->arch.nmi_pending) | |
3450 | kvm_x86_ops->enable_nmi_window(vcpu); | |
3451 | else if (kvm_cpu_has_interrupt(vcpu) || req_int_win) | |
3452 | kvm_x86_ops->enable_irq_window(vcpu); | |
3453 | ||
95ba8273 | 3454 | if (kvm_lapic_enabled(vcpu)) { |
8db3baa2 GN |
3455 | update_cr8_intercept(vcpu); |
3456 | kvm_lapic_sync_to_vapic(vcpu); | |
95ba8273 | 3457 | } |
b93463aa | 3458 | |
3200f405 MT |
3459 | up_read(&vcpu->kvm->slots_lock); |
3460 | ||
b6c7a5dc HB |
3461 | kvm_guest_enter(); |
3462 | ||
42dbaa5a JK |
3463 | get_debugreg(vcpu->arch.host_dr6, 6); |
3464 | get_debugreg(vcpu->arch.host_dr7, 7); | |
3465 | if (unlikely(vcpu->arch.switch_db_regs)) { | |
3466 | get_debugreg(vcpu->arch.host_db[0], 0); | |
3467 | get_debugreg(vcpu->arch.host_db[1], 1); | |
3468 | get_debugreg(vcpu->arch.host_db[2], 2); | |
3469 | get_debugreg(vcpu->arch.host_db[3], 3); | |
3470 | ||
3471 | set_debugreg(0, 7); | |
3472 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
3473 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
3474 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
3475 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
3476 | } | |
b6c7a5dc | 3477 | |
2714d1d3 | 3478 | KVMTRACE_0D(VMENTRY, vcpu, entryexit); |
b6c7a5dc HB |
3479 | kvm_x86_ops->run(vcpu, kvm_run); |
3480 | ||
42dbaa5a JK |
3481 | if (unlikely(vcpu->arch.switch_db_regs)) { |
3482 | set_debugreg(0, 7); | |
3483 | set_debugreg(vcpu->arch.host_db[0], 0); | |
3484 | set_debugreg(vcpu->arch.host_db[1], 1); | |
3485 | set_debugreg(vcpu->arch.host_db[2], 2); | |
3486 | set_debugreg(vcpu->arch.host_db[3], 3); | |
3487 | } | |
3488 | set_debugreg(vcpu->arch.host_dr6, 6); | |
3489 | set_debugreg(vcpu->arch.host_dr7, 7); | |
3490 | ||
32f88400 | 3491 | set_bit(KVM_REQ_KICK, &vcpu->requests); |
b6c7a5dc HB |
3492 | local_irq_enable(); |
3493 | ||
3494 | ++vcpu->stat.exits; | |
3495 | ||
3496 | /* | |
3497 | * We must have an instruction between local_irq_enable() and | |
3498 | * kvm_guest_exit(), so the timer interrupt isn't delayed by | |
3499 | * the interrupt shadow. The stat.exits increment will do nicely. | |
3500 | * But we need to prevent reordering, hence this barrier(): | |
3501 | */ | |
3502 | barrier(); | |
3503 | ||
3504 | kvm_guest_exit(); | |
3505 | ||
3506 | preempt_enable(); | |
3507 | ||
3200f405 MT |
3508 | down_read(&vcpu->kvm->slots_lock); |
3509 | ||
b6c7a5dc HB |
3510 | /* |
3511 | * Profile KVM exit RIPs: | |
3512 | */ | |
3513 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
3514 | unsigned long rip = kvm_rip_read(vcpu); |
3515 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
3516 | } |
3517 | ||
298101da | 3518 | |
b93463aa AK |
3519 | kvm_lapic_sync_from_vapic(vcpu); |
3520 | ||
b6c7a5dc | 3521 | r = kvm_x86_ops->handle_exit(kvm_run, vcpu); |
d7690175 MT |
3522 | out: |
3523 | return r; | |
3524 | } | |
b6c7a5dc | 3525 | |
09cec754 | 3526 | |
d7690175 MT |
3527 | static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
3528 | { | |
3529 | int r; | |
3530 | ||
3531 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) { | |
1b10bf31 JK |
3532 | pr_debug("vcpu %d received sipi with vector # %x\n", |
3533 | vcpu->vcpu_id, vcpu->arch.sipi_vector); | |
d7690175 | 3534 | kvm_lapic_reset(vcpu); |
5f179287 | 3535 | r = kvm_arch_vcpu_reset(vcpu); |
d7690175 MT |
3536 | if (r) |
3537 | return r; | |
3538 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
b6c7a5dc HB |
3539 | } |
3540 | ||
d7690175 MT |
3541 | down_read(&vcpu->kvm->slots_lock); |
3542 | vapic_enter(vcpu); | |
3543 | ||
3544 | r = 1; | |
3545 | while (r > 0) { | |
af2152f5 | 3546 | if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE) |
d7690175 MT |
3547 | r = vcpu_enter_guest(vcpu, kvm_run); |
3548 | else { | |
3549 | up_read(&vcpu->kvm->slots_lock); | |
3550 | kvm_vcpu_block(vcpu); | |
3551 | down_read(&vcpu->kvm->slots_lock); | |
3552 | if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests)) | |
09cec754 GN |
3553 | { |
3554 | switch(vcpu->arch.mp_state) { | |
3555 | case KVM_MP_STATE_HALTED: | |
d7690175 | 3556 | vcpu->arch.mp_state = |
09cec754 GN |
3557 | KVM_MP_STATE_RUNNABLE; |
3558 | case KVM_MP_STATE_RUNNABLE: | |
3559 | break; | |
3560 | case KVM_MP_STATE_SIPI_RECEIVED: | |
3561 | default: | |
3562 | r = -EINTR; | |
3563 | break; | |
3564 | } | |
3565 | } | |
d7690175 MT |
3566 | } |
3567 | ||
09cec754 GN |
3568 | if (r <= 0) |
3569 | break; | |
3570 | ||
3571 | clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); | |
3572 | if (kvm_cpu_has_pending_timer(vcpu)) | |
3573 | kvm_inject_pending_timer_irqs(vcpu); | |
3574 | ||
3575 | if (dm_request_for_irq_injection(vcpu, kvm_run)) { | |
3576 | r = -EINTR; | |
3577 | kvm_run->exit_reason = KVM_EXIT_INTR; | |
3578 | ++vcpu->stat.request_irq_exits; | |
3579 | } | |
3580 | if (signal_pending(current)) { | |
3581 | r = -EINTR; | |
3582 | kvm_run->exit_reason = KVM_EXIT_INTR; | |
3583 | ++vcpu->stat.signal_exits; | |
3584 | } | |
3585 | if (need_resched()) { | |
3586 | up_read(&vcpu->kvm->slots_lock); | |
3587 | kvm_resched(vcpu); | |
3588 | down_read(&vcpu->kvm->slots_lock); | |
d7690175 | 3589 | } |
b6c7a5dc HB |
3590 | } |
3591 | ||
d7690175 | 3592 | up_read(&vcpu->kvm->slots_lock); |
b6c7a5dc HB |
3593 | post_kvm_run_save(vcpu, kvm_run); |
3594 | ||
b93463aa AK |
3595 | vapic_exit(vcpu); |
3596 | ||
b6c7a5dc HB |
3597 | return r; |
3598 | } | |
3599 | ||
3600 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
3601 | { | |
3602 | int r; | |
3603 | sigset_t sigsaved; | |
3604 | ||
3605 | vcpu_load(vcpu); | |
3606 | ||
ac9f6dc0 AK |
3607 | if (vcpu->sigset_active) |
3608 | sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); | |
3609 | ||
a4535290 | 3610 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
b6c7a5dc | 3611 | kvm_vcpu_block(vcpu); |
d7690175 | 3612 | clear_bit(KVM_REQ_UNHALT, &vcpu->requests); |
ac9f6dc0 AK |
3613 | r = -EAGAIN; |
3614 | goto out; | |
b6c7a5dc HB |
3615 | } |
3616 | ||
b6c7a5dc HB |
3617 | /* re-sync apic's tpr */ |
3618 | if (!irqchip_in_kernel(vcpu->kvm)) | |
2d3ad1f4 | 3619 | kvm_set_cr8(vcpu, kvm_run->cr8); |
b6c7a5dc | 3620 | |
ad312c7c | 3621 | if (vcpu->arch.pio.cur_count) { |
b6c7a5dc HB |
3622 | r = complete_pio(vcpu); |
3623 | if (r) | |
3624 | goto out; | |
3625 | } | |
3626 | #if CONFIG_HAS_IOMEM | |
3627 | if (vcpu->mmio_needed) { | |
3628 | memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8); | |
3629 | vcpu->mmio_read_completed = 1; | |
3630 | vcpu->mmio_needed = 0; | |
3200f405 MT |
3631 | |
3632 | down_read(&vcpu->kvm->slots_lock); | |
b6c7a5dc | 3633 | r = emulate_instruction(vcpu, kvm_run, |
571008da SY |
3634 | vcpu->arch.mmio_fault_cr2, 0, |
3635 | EMULTYPE_NO_DECODE); | |
3200f405 | 3636 | up_read(&vcpu->kvm->slots_lock); |
b6c7a5dc HB |
3637 | if (r == EMULATE_DO_MMIO) { |
3638 | /* | |
3639 | * Read-modify-write. Back to userspace. | |
3640 | */ | |
3641 | r = 0; | |
3642 | goto out; | |
3643 | } | |
3644 | } | |
3645 | #endif | |
5fdbf976 MT |
3646 | if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL) |
3647 | kvm_register_write(vcpu, VCPU_REGS_RAX, | |
3648 | kvm_run->hypercall.ret); | |
b6c7a5dc HB |
3649 | |
3650 | r = __vcpu_run(vcpu, kvm_run); | |
3651 | ||
3652 | out: | |
3653 | if (vcpu->sigset_active) | |
3654 | sigprocmask(SIG_SETMASK, &sigsaved, NULL); | |
3655 | ||
3656 | vcpu_put(vcpu); | |
3657 | return r; | |
3658 | } | |
3659 | ||
3660 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
3661 | { | |
3662 | vcpu_load(vcpu); | |
3663 | ||
5fdbf976 MT |
3664 | regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); |
3665 | regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
3666 | regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
3667 | regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
3668 | regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
3669 | regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
3670 | regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
3671 | regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); | |
b6c7a5dc | 3672 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
3673 | regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); |
3674 | regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); | |
3675 | regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); | |
3676 | regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); | |
3677 | regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); | |
3678 | regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); | |
3679 | regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); | |
3680 | regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); | |
b6c7a5dc HB |
3681 | #endif |
3682 | ||
5fdbf976 | 3683 | regs->rip = kvm_rip_read(vcpu); |
b6c7a5dc HB |
3684 | regs->rflags = kvm_x86_ops->get_rflags(vcpu); |
3685 | ||
3686 | /* | |
3687 | * Don't leak debug flags in case they were set for guest debugging | |
3688 | */ | |
d0bfb940 | 3689 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
b6c7a5dc HB |
3690 | regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF); |
3691 | ||
3692 | vcpu_put(vcpu); | |
3693 | ||
3694 | return 0; | |
3695 | } | |
3696 | ||
3697 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
3698 | { | |
3699 | vcpu_load(vcpu); | |
3700 | ||
5fdbf976 MT |
3701 | kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); |
3702 | kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); | |
3703 | kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); | |
3704 | kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); | |
3705 | kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); | |
3706 | kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); | |
3707 | kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); | |
3708 | kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); | |
b6c7a5dc | 3709 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
3710 | kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); |
3711 | kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); | |
3712 | kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); | |
3713 | kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); | |
3714 | kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); | |
3715 | kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); | |
3716 | kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); | |
3717 | kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); | |
3718 | ||
b6c7a5dc HB |
3719 | #endif |
3720 | ||
5fdbf976 | 3721 | kvm_rip_write(vcpu, regs->rip); |
b6c7a5dc HB |
3722 | kvm_x86_ops->set_rflags(vcpu, regs->rflags); |
3723 | ||
b6c7a5dc | 3724 | |
b4f14abd JK |
3725 | vcpu->arch.exception.pending = false; |
3726 | ||
b6c7a5dc HB |
3727 | vcpu_put(vcpu); |
3728 | ||
3729 | return 0; | |
3730 | } | |
3731 | ||
3e6e0aab GT |
3732 | void kvm_get_segment(struct kvm_vcpu *vcpu, |
3733 | struct kvm_segment *var, int seg) | |
b6c7a5dc | 3734 | { |
14af3f3c | 3735 | kvm_x86_ops->get_segment(vcpu, var, seg); |
b6c7a5dc HB |
3736 | } |
3737 | ||
3738 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) | |
3739 | { | |
3740 | struct kvm_segment cs; | |
3741 | ||
3e6e0aab | 3742 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
3743 | *db = cs.db; |
3744 | *l = cs.l; | |
3745 | } | |
3746 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
3747 | ||
3748 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, | |
3749 | struct kvm_sregs *sregs) | |
3750 | { | |
3751 | struct descriptor_table dt; | |
b6c7a5dc HB |
3752 | |
3753 | vcpu_load(vcpu); | |
3754 | ||
3e6e0aab GT |
3755 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
3756 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
3757 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
3758 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
3759 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
3760 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 3761 | |
3e6e0aab GT |
3762 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
3763 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc HB |
3764 | |
3765 | kvm_x86_ops->get_idt(vcpu, &dt); | |
3766 | sregs->idt.limit = dt.limit; | |
3767 | sregs->idt.base = dt.base; | |
3768 | kvm_x86_ops->get_gdt(vcpu, &dt); | |
3769 | sregs->gdt.limit = dt.limit; | |
3770 | sregs->gdt.base = dt.base; | |
3771 | ||
3772 | kvm_x86_ops->decache_cr4_guest_bits(vcpu); | |
ad312c7c ZX |
3773 | sregs->cr0 = vcpu->arch.cr0; |
3774 | sregs->cr2 = vcpu->arch.cr2; | |
3775 | sregs->cr3 = vcpu->arch.cr3; | |
3776 | sregs->cr4 = vcpu->arch.cr4; | |
2d3ad1f4 | 3777 | sregs->cr8 = kvm_get_cr8(vcpu); |
ad312c7c | 3778 | sregs->efer = vcpu->arch.shadow_efer; |
b6c7a5dc HB |
3779 | sregs->apic_base = kvm_get_apic_base(vcpu); |
3780 | ||
923c61bb | 3781 | memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); |
b6c7a5dc | 3782 | |
36752c9b | 3783 | if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
3784 | set_bit(vcpu->arch.interrupt.nr, |
3785 | (unsigned long *)sregs->interrupt_bitmap); | |
16d7a191 | 3786 | |
b6c7a5dc HB |
3787 | vcpu_put(vcpu); |
3788 | ||
3789 | return 0; | |
3790 | } | |
3791 | ||
62d9f0db MT |
3792 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
3793 | struct kvm_mp_state *mp_state) | |
3794 | { | |
3795 | vcpu_load(vcpu); | |
3796 | mp_state->mp_state = vcpu->arch.mp_state; | |
3797 | vcpu_put(vcpu); | |
3798 | return 0; | |
3799 | } | |
3800 | ||
3801 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
3802 | struct kvm_mp_state *mp_state) | |
3803 | { | |
3804 | vcpu_load(vcpu); | |
3805 | vcpu->arch.mp_state = mp_state->mp_state; | |
3806 | vcpu_put(vcpu); | |
3807 | return 0; | |
3808 | } | |
3809 | ||
3e6e0aab | 3810 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
b6c7a5dc HB |
3811 | struct kvm_segment *var, int seg) |
3812 | { | |
14af3f3c | 3813 | kvm_x86_ops->set_segment(vcpu, var, seg); |
b6c7a5dc HB |
3814 | } |
3815 | ||
37817f29 IE |
3816 | static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector, |
3817 | struct kvm_segment *kvm_desct) | |
3818 | { | |
3819 | kvm_desct->base = seg_desc->base0; | |
3820 | kvm_desct->base |= seg_desc->base1 << 16; | |
3821 | kvm_desct->base |= seg_desc->base2 << 24; | |
3822 | kvm_desct->limit = seg_desc->limit0; | |
3823 | kvm_desct->limit |= seg_desc->limit << 16; | |
c93cd3a5 MT |
3824 | if (seg_desc->g) { |
3825 | kvm_desct->limit <<= 12; | |
3826 | kvm_desct->limit |= 0xfff; | |
3827 | } | |
37817f29 IE |
3828 | kvm_desct->selector = selector; |
3829 | kvm_desct->type = seg_desc->type; | |
3830 | kvm_desct->present = seg_desc->p; | |
3831 | kvm_desct->dpl = seg_desc->dpl; | |
3832 | kvm_desct->db = seg_desc->d; | |
3833 | kvm_desct->s = seg_desc->s; | |
3834 | kvm_desct->l = seg_desc->l; | |
3835 | kvm_desct->g = seg_desc->g; | |
3836 | kvm_desct->avl = seg_desc->avl; | |
3837 | if (!selector) | |
3838 | kvm_desct->unusable = 1; | |
3839 | else | |
3840 | kvm_desct->unusable = 0; | |
3841 | kvm_desct->padding = 0; | |
3842 | } | |
3843 | ||
b8222ad2 AS |
3844 | static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu, |
3845 | u16 selector, | |
3846 | struct descriptor_table *dtable) | |
37817f29 IE |
3847 | { |
3848 | if (selector & 1 << 2) { | |
3849 | struct kvm_segment kvm_seg; | |
3850 | ||
3e6e0aab | 3851 | kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR); |
37817f29 IE |
3852 | |
3853 | if (kvm_seg.unusable) | |
3854 | dtable->limit = 0; | |
3855 | else | |
3856 | dtable->limit = kvm_seg.limit; | |
3857 | dtable->base = kvm_seg.base; | |
3858 | } | |
3859 | else | |
3860 | kvm_x86_ops->get_gdt(vcpu, dtable); | |
3861 | } | |
3862 | ||
3863 | /* allowed just for 8 bytes segments */ | |
3864 | static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, | |
3865 | struct desc_struct *seg_desc) | |
3866 | { | |
98899aa0 | 3867 | gpa_t gpa; |
37817f29 IE |
3868 | struct descriptor_table dtable; |
3869 | u16 index = selector >> 3; | |
3870 | ||
b8222ad2 | 3871 | get_segment_descriptor_dtable(vcpu, selector, &dtable); |
37817f29 IE |
3872 | |
3873 | if (dtable.limit < index * 8 + 7) { | |
3874 | kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc); | |
3875 | return 1; | |
3876 | } | |
98899aa0 MT |
3877 | gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base); |
3878 | gpa += index * 8; | |
3879 | return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8); | |
37817f29 IE |
3880 | } |
3881 | ||
3882 | /* allowed just for 8 bytes segments */ | |
3883 | static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, | |
3884 | struct desc_struct *seg_desc) | |
3885 | { | |
98899aa0 | 3886 | gpa_t gpa; |
37817f29 IE |
3887 | struct descriptor_table dtable; |
3888 | u16 index = selector >> 3; | |
3889 | ||
b8222ad2 | 3890 | get_segment_descriptor_dtable(vcpu, selector, &dtable); |
37817f29 IE |
3891 | |
3892 | if (dtable.limit < index * 8 + 7) | |
3893 | return 1; | |
98899aa0 MT |
3894 | gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base); |
3895 | gpa += index * 8; | |
3896 | return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8); | |
37817f29 IE |
3897 | } |
3898 | ||
3899 | static u32 get_tss_base_addr(struct kvm_vcpu *vcpu, | |
3900 | struct desc_struct *seg_desc) | |
3901 | { | |
3902 | u32 base_addr; | |
3903 | ||
3904 | base_addr = seg_desc->base0; | |
3905 | base_addr |= (seg_desc->base1 << 16); | |
3906 | base_addr |= (seg_desc->base2 << 24); | |
3907 | ||
98899aa0 | 3908 | return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr); |
37817f29 IE |
3909 | } |
3910 | ||
37817f29 IE |
3911 | static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg) |
3912 | { | |
3913 | struct kvm_segment kvm_seg; | |
3914 | ||
3e6e0aab | 3915 | kvm_get_segment(vcpu, &kvm_seg, seg); |
37817f29 IE |
3916 | return kvm_seg.selector; |
3917 | } | |
3918 | ||
3919 | static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu, | |
3920 | u16 selector, | |
3921 | struct kvm_segment *kvm_seg) | |
3922 | { | |
3923 | struct desc_struct seg_desc; | |
3924 | ||
3925 | if (load_guest_segment_descriptor(vcpu, selector, &seg_desc)) | |
3926 | return 1; | |
3927 | seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg); | |
3928 | return 0; | |
3929 | } | |
3930 | ||
2259e3a7 | 3931 | static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg) |
f4bbd9aa AK |
3932 | { |
3933 | struct kvm_segment segvar = { | |
3934 | .base = selector << 4, | |
3935 | .limit = 0xffff, | |
3936 | .selector = selector, | |
3937 | .type = 3, | |
3938 | .present = 1, | |
3939 | .dpl = 3, | |
3940 | .db = 0, | |
3941 | .s = 1, | |
3942 | .l = 0, | |
3943 | .g = 0, | |
3944 | .avl = 0, | |
3945 | .unusable = 0, | |
3946 | }; | |
3947 | kvm_x86_ops->set_segment(vcpu, &segvar, seg); | |
3948 | return 0; | |
3949 | } | |
3950 | ||
3e6e0aab GT |
3951 | int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, |
3952 | int type_bits, int seg) | |
37817f29 IE |
3953 | { |
3954 | struct kvm_segment kvm_seg; | |
3955 | ||
f4bbd9aa AK |
3956 | if (!(vcpu->arch.cr0 & X86_CR0_PE)) |
3957 | return kvm_load_realmode_segment(vcpu, selector, seg); | |
37817f29 IE |
3958 | if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg)) |
3959 | return 1; | |
3960 | kvm_seg.type |= type_bits; | |
3961 | ||
3962 | if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS && | |
3963 | seg != VCPU_SREG_LDTR) | |
3964 | if (!kvm_seg.s) | |
3965 | kvm_seg.unusable = 1; | |
3966 | ||
3e6e0aab | 3967 | kvm_set_segment(vcpu, &kvm_seg, seg); |
37817f29 IE |
3968 | return 0; |
3969 | } | |
3970 | ||
3971 | static void save_state_to_tss32(struct kvm_vcpu *vcpu, | |
3972 | struct tss_segment_32 *tss) | |
3973 | { | |
3974 | tss->cr3 = vcpu->arch.cr3; | |
5fdbf976 | 3975 | tss->eip = kvm_rip_read(vcpu); |
37817f29 | 3976 | tss->eflags = kvm_x86_ops->get_rflags(vcpu); |
5fdbf976 MT |
3977 | tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX); |
3978 | tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
3979 | tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
3980 | tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
3981 | tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
3982 | tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP); | |
3983 | tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
3984 | tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
37817f29 IE |
3985 | tss->es = get_segment_selector(vcpu, VCPU_SREG_ES); |
3986 | tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS); | |
3987 | tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS); | |
3988 | tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS); | |
3989 | tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS); | |
3990 | tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS); | |
3991 | tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR); | |
37817f29 IE |
3992 | } |
3993 | ||
3994 | static int load_state_from_tss32(struct kvm_vcpu *vcpu, | |
3995 | struct tss_segment_32 *tss) | |
3996 | { | |
3997 | kvm_set_cr3(vcpu, tss->cr3); | |
3998 | ||
5fdbf976 | 3999 | kvm_rip_write(vcpu, tss->eip); |
37817f29 IE |
4000 | kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2); |
4001 | ||
5fdbf976 MT |
4002 | kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax); |
4003 | kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx); | |
4004 | kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx); | |
4005 | kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx); | |
4006 | kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp); | |
4007 | kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp); | |
4008 | kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi); | |
4009 | kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi); | |
37817f29 | 4010 | |
3e6e0aab | 4011 | if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR)) |
37817f29 IE |
4012 | return 1; |
4013 | ||
3e6e0aab | 4014 | if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES)) |
37817f29 IE |
4015 | return 1; |
4016 | ||
3e6e0aab | 4017 | if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS)) |
37817f29 IE |
4018 | return 1; |
4019 | ||
3e6e0aab | 4020 | if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS)) |
37817f29 IE |
4021 | return 1; |
4022 | ||
3e6e0aab | 4023 | if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS)) |
37817f29 IE |
4024 | return 1; |
4025 | ||
3e6e0aab | 4026 | if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS)) |
37817f29 IE |
4027 | return 1; |
4028 | ||
3e6e0aab | 4029 | if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS)) |
37817f29 IE |
4030 | return 1; |
4031 | return 0; | |
4032 | } | |
4033 | ||
4034 | static void save_state_to_tss16(struct kvm_vcpu *vcpu, | |
4035 | struct tss_segment_16 *tss) | |
4036 | { | |
5fdbf976 | 4037 | tss->ip = kvm_rip_read(vcpu); |
37817f29 | 4038 | tss->flag = kvm_x86_ops->get_rflags(vcpu); |
5fdbf976 MT |
4039 | tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX); |
4040 | tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
4041 | tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
4042 | tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
4043 | tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
4044 | tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP); | |
4045 | tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
4046 | tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
37817f29 IE |
4047 | |
4048 | tss->es = get_segment_selector(vcpu, VCPU_SREG_ES); | |
4049 | tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS); | |
4050 | tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS); | |
4051 | tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS); | |
4052 | tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR); | |
4053 | tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR); | |
4054 | } | |
4055 | ||
4056 | static int load_state_from_tss16(struct kvm_vcpu *vcpu, | |
4057 | struct tss_segment_16 *tss) | |
4058 | { | |
5fdbf976 | 4059 | kvm_rip_write(vcpu, tss->ip); |
37817f29 | 4060 | kvm_x86_ops->set_rflags(vcpu, tss->flag | 2); |
5fdbf976 MT |
4061 | kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax); |
4062 | kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx); | |
4063 | kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx); | |
4064 | kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx); | |
4065 | kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp); | |
4066 | kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp); | |
4067 | kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si); | |
4068 | kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di); | |
37817f29 | 4069 | |
3e6e0aab | 4070 | if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR)) |
37817f29 IE |
4071 | return 1; |
4072 | ||
3e6e0aab | 4073 | if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES)) |
37817f29 IE |
4074 | return 1; |
4075 | ||
3e6e0aab | 4076 | if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS)) |
37817f29 IE |
4077 | return 1; |
4078 | ||
3e6e0aab | 4079 | if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS)) |
37817f29 IE |
4080 | return 1; |
4081 | ||
3e6e0aab | 4082 | if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS)) |
37817f29 IE |
4083 | return 1; |
4084 | return 0; | |
4085 | } | |
4086 | ||
8b2cf73c | 4087 | static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector, |
b237ac37 GN |
4088 | u16 old_tss_sel, u32 old_tss_base, |
4089 | struct desc_struct *nseg_desc) | |
37817f29 IE |
4090 | { |
4091 | struct tss_segment_16 tss_segment_16; | |
4092 | int ret = 0; | |
4093 | ||
34198bf8 MT |
4094 | if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16, |
4095 | sizeof tss_segment_16)) | |
37817f29 IE |
4096 | goto out; |
4097 | ||
4098 | save_state_to_tss16(vcpu, &tss_segment_16); | |
37817f29 | 4099 | |
34198bf8 MT |
4100 | if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16, |
4101 | sizeof tss_segment_16)) | |
37817f29 | 4102 | goto out; |
34198bf8 MT |
4103 | |
4104 | if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc), | |
4105 | &tss_segment_16, sizeof tss_segment_16)) | |
4106 | goto out; | |
4107 | ||
b237ac37 GN |
4108 | if (old_tss_sel != 0xffff) { |
4109 | tss_segment_16.prev_task_link = old_tss_sel; | |
4110 | ||
4111 | if (kvm_write_guest(vcpu->kvm, | |
4112 | get_tss_base_addr(vcpu, nseg_desc), | |
4113 | &tss_segment_16.prev_task_link, | |
4114 | sizeof tss_segment_16.prev_task_link)) | |
4115 | goto out; | |
4116 | } | |
4117 | ||
37817f29 IE |
4118 | if (load_state_from_tss16(vcpu, &tss_segment_16)) |
4119 | goto out; | |
4120 | ||
4121 | ret = 1; | |
4122 | out: | |
4123 | return ret; | |
4124 | } | |
4125 | ||
8b2cf73c | 4126 | static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector, |
b237ac37 | 4127 | u16 old_tss_sel, u32 old_tss_base, |
37817f29 IE |
4128 | struct desc_struct *nseg_desc) |
4129 | { | |
4130 | struct tss_segment_32 tss_segment_32; | |
4131 | int ret = 0; | |
4132 | ||
34198bf8 MT |
4133 | if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32, |
4134 | sizeof tss_segment_32)) | |
37817f29 IE |
4135 | goto out; |
4136 | ||
4137 | save_state_to_tss32(vcpu, &tss_segment_32); | |
37817f29 | 4138 | |
34198bf8 MT |
4139 | if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32, |
4140 | sizeof tss_segment_32)) | |
4141 | goto out; | |
4142 | ||
4143 | if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc), | |
4144 | &tss_segment_32, sizeof tss_segment_32)) | |
37817f29 | 4145 | goto out; |
34198bf8 | 4146 | |
b237ac37 GN |
4147 | if (old_tss_sel != 0xffff) { |
4148 | tss_segment_32.prev_task_link = old_tss_sel; | |
4149 | ||
4150 | if (kvm_write_guest(vcpu->kvm, | |
4151 | get_tss_base_addr(vcpu, nseg_desc), | |
4152 | &tss_segment_32.prev_task_link, | |
4153 | sizeof tss_segment_32.prev_task_link)) | |
4154 | goto out; | |
4155 | } | |
4156 | ||
37817f29 IE |
4157 | if (load_state_from_tss32(vcpu, &tss_segment_32)) |
4158 | goto out; | |
4159 | ||
4160 | ret = 1; | |
4161 | out: | |
4162 | return ret; | |
4163 | } | |
4164 | ||
4165 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason) | |
4166 | { | |
4167 | struct kvm_segment tr_seg; | |
4168 | struct desc_struct cseg_desc; | |
4169 | struct desc_struct nseg_desc; | |
4170 | int ret = 0; | |
34198bf8 MT |
4171 | u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR); |
4172 | u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR); | |
37817f29 | 4173 | |
34198bf8 | 4174 | old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base); |
37817f29 | 4175 | |
34198bf8 MT |
4176 | /* FIXME: Handle errors. Failure to read either TSS or their |
4177 | * descriptors should generate a pagefault. | |
4178 | */ | |
37817f29 IE |
4179 | if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc)) |
4180 | goto out; | |
4181 | ||
34198bf8 | 4182 | if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc)) |
37817f29 IE |
4183 | goto out; |
4184 | ||
37817f29 IE |
4185 | if (reason != TASK_SWITCH_IRET) { |
4186 | int cpl; | |
4187 | ||
4188 | cpl = kvm_x86_ops->get_cpl(vcpu); | |
4189 | if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) { | |
4190 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
4191 | return 1; | |
4192 | } | |
4193 | } | |
4194 | ||
4195 | if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) { | |
4196 | kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc); | |
4197 | return 1; | |
4198 | } | |
4199 | ||
4200 | if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { | |
3fe913e7 | 4201 | cseg_desc.type &= ~(1 << 1); //clear the B flag |
34198bf8 | 4202 | save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc); |
37817f29 IE |
4203 | } |
4204 | ||
4205 | if (reason == TASK_SWITCH_IRET) { | |
4206 | u32 eflags = kvm_x86_ops->get_rflags(vcpu); | |
4207 | kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT); | |
4208 | } | |
4209 | ||
64a7ec06 GN |
4210 | /* set back link to prev task only if NT bit is set in eflags |
4211 | note that old_tss_sel is not used afetr this point */ | |
4212 | if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) | |
4213 | old_tss_sel = 0xffff; | |
37817f29 | 4214 | |
b237ac37 GN |
4215 | /* set back link to prev task only if NT bit is set in eflags |
4216 | note that old_tss_sel is not used afetr this point */ | |
4217 | if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) | |
4218 | old_tss_sel = 0xffff; | |
4219 | ||
37817f29 | 4220 | if (nseg_desc.type & 8) |
b237ac37 GN |
4221 | ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel, |
4222 | old_tss_base, &nseg_desc); | |
37817f29 | 4223 | else |
b237ac37 GN |
4224 | ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel, |
4225 | old_tss_base, &nseg_desc); | |
37817f29 IE |
4226 | |
4227 | if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) { | |
4228 | u32 eflags = kvm_x86_ops->get_rflags(vcpu); | |
4229 | kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT); | |
4230 | } | |
4231 | ||
4232 | if (reason != TASK_SWITCH_IRET) { | |
3fe913e7 | 4233 | nseg_desc.type |= (1 << 1); |
37817f29 IE |
4234 | save_guest_segment_descriptor(vcpu, tss_selector, |
4235 | &nseg_desc); | |
4236 | } | |
4237 | ||
4238 | kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS); | |
4239 | seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg); | |
4240 | tr_seg.type = 11; | |
3e6e0aab | 4241 | kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR); |
37817f29 | 4242 | out: |
37817f29 IE |
4243 | return ret; |
4244 | } | |
4245 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
4246 | ||
b6c7a5dc HB |
4247 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, |
4248 | struct kvm_sregs *sregs) | |
4249 | { | |
4250 | int mmu_reset_needed = 0; | |
923c61bb | 4251 | int pending_vec, max_bits; |
b6c7a5dc HB |
4252 | struct descriptor_table dt; |
4253 | ||
4254 | vcpu_load(vcpu); | |
4255 | ||
4256 | dt.limit = sregs->idt.limit; | |
4257 | dt.base = sregs->idt.base; | |
4258 | kvm_x86_ops->set_idt(vcpu, &dt); | |
4259 | dt.limit = sregs->gdt.limit; | |
4260 | dt.base = sregs->gdt.base; | |
4261 | kvm_x86_ops->set_gdt(vcpu, &dt); | |
4262 | ||
ad312c7c ZX |
4263 | vcpu->arch.cr2 = sregs->cr2; |
4264 | mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3; | |
59839dff MT |
4265 | |
4266 | down_read(&vcpu->kvm->slots_lock); | |
4267 | if (gfn_to_memslot(vcpu->kvm, sregs->cr3 >> PAGE_SHIFT)) | |
4268 | vcpu->arch.cr3 = sregs->cr3; | |
4269 | else | |
4270 | set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests); | |
4271 | up_read(&vcpu->kvm->slots_lock); | |
b6c7a5dc | 4272 | |
2d3ad1f4 | 4273 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 4274 | |
ad312c7c | 4275 | mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer; |
b6c7a5dc | 4276 | kvm_x86_ops->set_efer(vcpu, sregs->efer); |
b6c7a5dc HB |
4277 | kvm_set_apic_base(vcpu, sregs->apic_base); |
4278 | ||
4279 | kvm_x86_ops->decache_cr4_guest_bits(vcpu); | |
4280 | ||
ad312c7c | 4281 | mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0; |
b6c7a5dc | 4282 | kvm_x86_ops->set_cr0(vcpu, sregs->cr0); |
d7306163 | 4283 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 4284 | |
ad312c7c | 4285 | mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4; |
b6c7a5dc HB |
4286 | kvm_x86_ops->set_cr4(vcpu, sregs->cr4); |
4287 | if (!is_long_mode(vcpu) && is_pae(vcpu)) | |
ad312c7c | 4288 | load_pdptrs(vcpu, vcpu->arch.cr3); |
b6c7a5dc HB |
4289 | |
4290 | if (mmu_reset_needed) | |
4291 | kvm_mmu_reset_context(vcpu); | |
4292 | ||
923c61bb GN |
4293 | max_bits = (sizeof sregs->interrupt_bitmap) << 3; |
4294 | pending_vec = find_first_bit( | |
4295 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
4296 | if (pending_vec < max_bits) { | |
66fd3f7f | 4297 | kvm_queue_interrupt(vcpu, pending_vec, false); |
923c61bb GN |
4298 | pr_debug("Set back pending irq %d\n", pending_vec); |
4299 | if (irqchip_in_kernel(vcpu->kvm)) | |
4300 | kvm_pic_clear_isr_ack(vcpu->kvm); | |
b6c7a5dc HB |
4301 | } |
4302 | ||
3e6e0aab GT |
4303 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
4304 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
4305 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
4306 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
4307 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
4308 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 4309 | |
3e6e0aab GT |
4310 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
4311 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 4312 | |
9c3e4aab MT |
4313 | /* Older userspace won't unhalt the vcpu on reset. */ |
4314 | if (vcpu->vcpu_id == 0 && kvm_rip_read(vcpu) == 0xfff0 && | |
4315 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && | |
4316 | !(vcpu->arch.cr0 & X86_CR0_PE)) | |
4317 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
4318 | ||
b6c7a5dc HB |
4319 | vcpu_put(vcpu); |
4320 | ||
4321 | return 0; | |
4322 | } | |
4323 | ||
d0bfb940 JK |
4324 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
4325 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 4326 | { |
ae675ef0 | 4327 | int i, r; |
b6c7a5dc HB |
4328 | |
4329 | vcpu_load(vcpu); | |
4330 | ||
ae675ef0 JK |
4331 | if ((dbg->control & (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) == |
4332 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) { | |
4333 | for (i = 0; i < KVM_NR_DB_REGS; ++i) | |
4334 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
4335 | vcpu->arch.switch_db_regs = | |
4336 | (dbg->arch.debugreg[7] & DR7_BP_EN_MASK); | |
4337 | } else { | |
4338 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
4339 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
4340 | vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK); | |
4341 | } | |
4342 | ||
b6c7a5dc HB |
4343 | r = kvm_x86_ops->set_guest_debug(vcpu, dbg); |
4344 | ||
d0bfb940 JK |
4345 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
4346 | kvm_queue_exception(vcpu, DB_VECTOR); | |
4347 | else if (dbg->control & KVM_GUESTDBG_INJECT_BP) | |
4348 | kvm_queue_exception(vcpu, BP_VECTOR); | |
4349 | ||
b6c7a5dc HB |
4350 | vcpu_put(vcpu); |
4351 | ||
4352 | return r; | |
4353 | } | |
4354 | ||
d0752060 HB |
4355 | /* |
4356 | * fxsave fpu state. Taken from x86_64/processor.h. To be killed when | |
4357 | * we have asm/x86/processor.h | |
4358 | */ | |
4359 | struct fxsave { | |
4360 | u16 cwd; | |
4361 | u16 swd; | |
4362 | u16 twd; | |
4363 | u16 fop; | |
4364 | u64 rip; | |
4365 | u64 rdp; | |
4366 | u32 mxcsr; | |
4367 | u32 mxcsr_mask; | |
4368 | u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */ | |
4369 | #ifdef CONFIG_X86_64 | |
4370 | u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */ | |
4371 | #else | |
4372 | u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */ | |
4373 | #endif | |
4374 | }; | |
4375 | ||
8b006791 ZX |
4376 | /* |
4377 | * Translate a guest virtual address to a guest physical address. | |
4378 | */ | |
4379 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
4380 | struct kvm_translation *tr) | |
4381 | { | |
4382 | unsigned long vaddr = tr->linear_address; | |
4383 | gpa_t gpa; | |
4384 | ||
4385 | vcpu_load(vcpu); | |
72dc67a6 | 4386 | down_read(&vcpu->kvm->slots_lock); |
ad312c7c | 4387 | gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr); |
72dc67a6 | 4388 | up_read(&vcpu->kvm->slots_lock); |
8b006791 ZX |
4389 | tr->physical_address = gpa; |
4390 | tr->valid = gpa != UNMAPPED_GVA; | |
4391 | tr->writeable = 1; | |
4392 | tr->usermode = 0; | |
8b006791 ZX |
4393 | vcpu_put(vcpu); |
4394 | ||
4395 | return 0; | |
4396 | } | |
4397 | ||
d0752060 HB |
4398 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
4399 | { | |
ad312c7c | 4400 | struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image; |
d0752060 HB |
4401 | |
4402 | vcpu_load(vcpu); | |
4403 | ||
4404 | memcpy(fpu->fpr, fxsave->st_space, 128); | |
4405 | fpu->fcw = fxsave->cwd; | |
4406 | fpu->fsw = fxsave->swd; | |
4407 | fpu->ftwx = fxsave->twd; | |
4408 | fpu->last_opcode = fxsave->fop; | |
4409 | fpu->last_ip = fxsave->rip; | |
4410 | fpu->last_dp = fxsave->rdp; | |
4411 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); | |
4412 | ||
4413 | vcpu_put(vcpu); | |
4414 | ||
4415 | return 0; | |
4416 | } | |
4417 | ||
4418 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
4419 | { | |
ad312c7c | 4420 | struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image; |
d0752060 HB |
4421 | |
4422 | vcpu_load(vcpu); | |
4423 | ||
4424 | memcpy(fxsave->st_space, fpu->fpr, 128); | |
4425 | fxsave->cwd = fpu->fcw; | |
4426 | fxsave->swd = fpu->fsw; | |
4427 | fxsave->twd = fpu->ftwx; | |
4428 | fxsave->fop = fpu->last_opcode; | |
4429 | fxsave->rip = fpu->last_ip; | |
4430 | fxsave->rdp = fpu->last_dp; | |
4431 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); | |
4432 | ||
4433 | vcpu_put(vcpu); | |
4434 | ||
4435 | return 0; | |
4436 | } | |
4437 | ||
4438 | void fx_init(struct kvm_vcpu *vcpu) | |
4439 | { | |
4440 | unsigned after_mxcsr_mask; | |
4441 | ||
bc1a34f1 AA |
4442 | /* |
4443 | * Touch the fpu the first time in non atomic context as if | |
4444 | * this is the first fpu instruction the exception handler | |
4445 | * will fire before the instruction returns and it'll have to | |
4446 | * allocate ram with GFP_KERNEL. | |
4447 | */ | |
4448 | if (!used_math()) | |
d6e88aec | 4449 | kvm_fx_save(&vcpu->arch.host_fx_image); |
bc1a34f1 | 4450 | |
d0752060 HB |
4451 | /* Initialize guest FPU by resetting ours and saving into guest's */ |
4452 | preempt_disable(); | |
d6e88aec AK |
4453 | kvm_fx_save(&vcpu->arch.host_fx_image); |
4454 | kvm_fx_finit(); | |
4455 | kvm_fx_save(&vcpu->arch.guest_fx_image); | |
4456 | kvm_fx_restore(&vcpu->arch.host_fx_image); | |
d0752060 HB |
4457 | preempt_enable(); |
4458 | ||
ad312c7c | 4459 | vcpu->arch.cr0 |= X86_CR0_ET; |
d0752060 | 4460 | after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space); |
ad312c7c ZX |
4461 | vcpu->arch.guest_fx_image.mxcsr = 0x1f80; |
4462 | memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask, | |
d0752060 HB |
4463 | 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask); |
4464 | } | |
4465 | EXPORT_SYMBOL_GPL(fx_init); | |
4466 | ||
4467 | void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) | |
4468 | { | |
4469 | if (!vcpu->fpu_active || vcpu->guest_fpu_loaded) | |
4470 | return; | |
4471 | ||
4472 | vcpu->guest_fpu_loaded = 1; | |
d6e88aec AK |
4473 | kvm_fx_save(&vcpu->arch.host_fx_image); |
4474 | kvm_fx_restore(&vcpu->arch.guest_fx_image); | |
d0752060 HB |
4475 | } |
4476 | EXPORT_SYMBOL_GPL(kvm_load_guest_fpu); | |
4477 | ||
4478 | void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
4479 | { | |
4480 | if (!vcpu->guest_fpu_loaded) | |
4481 | return; | |
4482 | ||
4483 | vcpu->guest_fpu_loaded = 0; | |
d6e88aec AK |
4484 | kvm_fx_save(&vcpu->arch.guest_fx_image); |
4485 | kvm_fx_restore(&vcpu->arch.host_fx_image); | |
f096ed85 | 4486 | ++vcpu->stat.fpu_reload; |
d0752060 HB |
4487 | } |
4488 | EXPORT_SYMBOL_GPL(kvm_put_guest_fpu); | |
e9b11c17 ZX |
4489 | |
4490 | void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) | |
4491 | { | |
7f1ea208 JR |
4492 | if (vcpu->arch.time_page) { |
4493 | kvm_release_page_dirty(vcpu->arch.time_page); | |
4494 | vcpu->arch.time_page = NULL; | |
4495 | } | |
4496 | ||
e9b11c17 ZX |
4497 | kvm_x86_ops->vcpu_free(vcpu); |
4498 | } | |
4499 | ||
4500 | struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, | |
4501 | unsigned int id) | |
4502 | { | |
26e5215f AK |
4503 | return kvm_x86_ops->vcpu_create(kvm, id); |
4504 | } | |
e9b11c17 | 4505 | |
26e5215f AK |
4506 | int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) |
4507 | { | |
4508 | int r; | |
e9b11c17 ZX |
4509 | |
4510 | /* We do fxsave: this must be aligned. */ | |
ad312c7c | 4511 | BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF); |
e9b11c17 | 4512 | |
0bed3b56 | 4513 | vcpu->arch.mtrr_state.have_fixed = 1; |
e9b11c17 ZX |
4514 | vcpu_load(vcpu); |
4515 | r = kvm_arch_vcpu_reset(vcpu); | |
4516 | if (r == 0) | |
4517 | r = kvm_mmu_setup(vcpu); | |
4518 | vcpu_put(vcpu); | |
4519 | if (r < 0) | |
4520 | goto free_vcpu; | |
4521 | ||
26e5215f | 4522 | return 0; |
e9b11c17 ZX |
4523 | free_vcpu: |
4524 | kvm_x86_ops->vcpu_free(vcpu); | |
26e5215f | 4525 | return r; |
e9b11c17 ZX |
4526 | } |
4527 | ||
d40ccc62 | 4528 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 ZX |
4529 | { |
4530 | vcpu_load(vcpu); | |
4531 | kvm_mmu_unload(vcpu); | |
4532 | vcpu_put(vcpu); | |
4533 | ||
4534 | kvm_x86_ops->vcpu_free(vcpu); | |
4535 | } | |
4536 | ||
4537 | int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu) | |
4538 | { | |
448fa4a9 JK |
4539 | vcpu->arch.nmi_pending = false; |
4540 | vcpu->arch.nmi_injected = false; | |
4541 | ||
42dbaa5a JK |
4542 | vcpu->arch.switch_db_regs = 0; |
4543 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); | |
4544 | vcpu->arch.dr6 = DR6_FIXED_1; | |
4545 | vcpu->arch.dr7 = DR7_FIXED_1; | |
4546 | ||
e9b11c17 ZX |
4547 | return kvm_x86_ops->vcpu_reset(vcpu); |
4548 | } | |
4549 | ||
4550 | void kvm_arch_hardware_enable(void *garbage) | |
4551 | { | |
4552 | kvm_x86_ops->hardware_enable(garbage); | |
4553 | } | |
4554 | ||
4555 | void kvm_arch_hardware_disable(void *garbage) | |
4556 | { | |
4557 | kvm_x86_ops->hardware_disable(garbage); | |
4558 | } | |
4559 | ||
4560 | int kvm_arch_hardware_setup(void) | |
4561 | { | |
4562 | return kvm_x86_ops->hardware_setup(); | |
4563 | } | |
4564 | ||
4565 | void kvm_arch_hardware_unsetup(void) | |
4566 | { | |
4567 | kvm_x86_ops->hardware_unsetup(); | |
4568 | } | |
4569 | ||
4570 | void kvm_arch_check_processor_compat(void *rtn) | |
4571 | { | |
4572 | kvm_x86_ops->check_processor_compatibility(rtn); | |
4573 | } | |
4574 | ||
4575 | int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) | |
4576 | { | |
4577 | struct page *page; | |
4578 | struct kvm *kvm; | |
4579 | int r; | |
4580 | ||
4581 | BUG_ON(vcpu->kvm == NULL); | |
4582 | kvm = vcpu->kvm; | |
4583 | ||
ad312c7c | 4584 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
e9b11c17 | 4585 | if (!irqchip_in_kernel(kvm) || vcpu->vcpu_id == 0) |
a4535290 | 4586 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
e9b11c17 | 4587 | else |
a4535290 | 4588 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; |
e9b11c17 ZX |
4589 | |
4590 | page = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
4591 | if (!page) { | |
4592 | r = -ENOMEM; | |
4593 | goto fail; | |
4594 | } | |
ad312c7c | 4595 | vcpu->arch.pio_data = page_address(page); |
e9b11c17 ZX |
4596 | |
4597 | r = kvm_mmu_create(vcpu); | |
4598 | if (r < 0) | |
4599 | goto fail_free_pio_data; | |
4600 | ||
4601 | if (irqchip_in_kernel(kvm)) { | |
4602 | r = kvm_create_lapic(vcpu); | |
4603 | if (r < 0) | |
4604 | goto fail_mmu_destroy; | |
4605 | } | |
4606 | ||
890ca9ae HY |
4607 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, |
4608 | GFP_KERNEL); | |
4609 | if (!vcpu->arch.mce_banks) { | |
4610 | r = -ENOMEM; | |
4611 | goto fail_mmu_destroy; | |
4612 | } | |
4613 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
4614 | ||
e9b11c17 ZX |
4615 | return 0; |
4616 | ||
4617 | fail_mmu_destroy: | |
4618 | kvm_mmu_destroy(vcpu); | |
4619 | fail_free_pio_data: | |
ad312c7c | 4620 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 ZX |
4621 | fail: |
4622 | return r; | |
4623 | } | |
4624 | ||
4625 | void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) | |
4626 | { | |
4627 | kvm_free_lapic(vcpu); | |
3200f405 | 4628 | down_read(&vcpu->kvm->slots_lock); |
e9b11c17 | 4629 | kvm_mmu_destroy(vcpu); |
3200f405 | 4630 | up_read(&vcpu->kvm->slots_lock); |
ad312c7c | 4631 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 | 4632 | } |
d19a9cd2 ZX |
4633 | |
4634 | struct kvm *kvm_arch_create_vm(void) | |
4635 | { | |
4636 | struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL); | |
4637 | ||
4638 | if (!kvm) | |
4639 | return ERR_PTR(-ENOMEM); | |
4640 | ||
f05e70ac | 4641 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
4d5c5d0f | 4642 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
d19a9cd2 | 4643 | |
5550af4d SY |
4644 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
4645 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
4646 | ||
53f658b3 MT |
4647 | rdtscll(kvm->arch.vm_init_tsc); |
4648 | ||
d19a9cd2 ZX |
4649 | return kvm; |
4650 | } | |
4651 | ||
4652 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) | |
4653 | { | |
4654 | vcpu_load(vcpu); | |
4655 | kvm_mmu_unload(vcpu); | |
4656 | vcpu_put(vcpu); | |
4657 | } | |
4658 | ||
4659 | static void kvm_free_vcpus(struct kvm *kvm) | |
4660 | { | |
4661 | unsigned int i; | |
4662 | ||
4663 | /* | |
4664 | * Unpin any mmu pages first. | |
4665 | */ | |
4666 | for (i = 0; i < KVM_MAX_VCPUS; ++i) | |
4667 | if (kvm->vcpus[i]) | |
4668 | kvm_unload_vcpu_mmu(kvm->vcpus[i]); | |
4669 | for (i = 0; i < KVM_MAX_VCPUS; ++i) { | |
4670 | if (kvm->vcpus[i]) { | |
4671 | kvm_arch_vcpu_free(kvm->vcpus[i]); | |
4672 | kvm->vcpus[i] = NULL; | |
4673 | } | |
4674 | } | |
4675 | ||
4676 | } | |
4677 | ||
ad8ba2cd SY |
4678 | void kvm_arch_sync_events(struct kvm *kvm) |
4679 | { | |
ba4cef31 | 4680 | kvm_free_all_assigned_devices(kvm); |
ad8ba2cd SY |
4681 | } |
4682 | ||
d19a9cd2 ZX |
4683 | void kvm_arch_destroy_vm(struct kvm *kvm) |
4684 | { | |
6eb55818 | 4685 | kvm_iommu_unmap_guest(kvm); |
7837699f | 4686 | kvm_free_pit(kvm); |
d7deeeb0 ZX |
4687 | kfree(kvm->arch.vpic); |
4688 | kfree(kvm->arch.vioapic); | |
d19a9cd2 ZX |
4689 | kvm_free_vcpus(kvm); |
4690 | kvm_free_physmem(kvm); | |
3d45830c AK |
4691 | if (kvm->arch.apic_access_page) |
4692 | put_page(kvm->arch.apic_access_page); | |
b7ebfb05 SY |
4693 | if (kvm->arch.ept_identity_pagetable) |
4694 | put_page(kvm->arch.ept_identity_pagetable); | |
d19a9cd2 ZX |
4695 | kfree(kvm); |
4696 | } | |
0de10343 ZX |
4697 | |
4698 | int kvm_arch_set_memory_region(struct kvm *kvm, | |
4699 | struct kvm_userspace_memory_region *mem, | |
4700 | struct kvm_memory_slot old, | |
4701 | int user_alloc) | |
4702 | { | |
4703 | int npages = mem->memory_size >> PAGE_SHIFT; | |
4704 | struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot]; | |
4705 | ||
4706 | /*To keep backward compatibility with older userspace, | |
4707 | *x86 needs to hanlde !user_alloc case. | |
4708 | */ | |
4709 | if (!user_alloc) { | |
4710 | if (npages && !old.rmap) { | |
604b38ac AA |
4711 | unsigned long userspace_addr; |
4712 | ||
72dc67a6 | 4713 | down_write(¤t->mm->mmap_sem); |
604b38ac AA |
4714 | userspace_addr = do_mmap(NULL, 0, |
4715 | npages * PAGE_SIZE, | |
4716 | PROT_READ | PROT_WRITE, | |
acee3c04 | 4717 | MAP_PRIVATE | MAP_ANONYMOUS, |
604b38ac | 4718 | 0); |
72dc67a6 | 4719 | up_write(¤t->mm->mmap_sem); |
0de10343 | 4720 | |
604b38ac AA |
4721 | if (IS_ERR((void *)userspace_addr)) |
4722 | return PTR_ERR((void *)userspace_addr); | |
4723 | ||
4724 | /* set userspace_addr atomically for kvm_hva_to_rmapp */ | |
4725 | spin_lock(&kvm->mmu_lock); | |
4726 | memslot->userspace_addr = userspace_addr; | |
4727 | spin_unlock(&kvm->mmu_lock); | |
0de10343 ZX |
4728 | } else { |
4729 | if (!old.user_alloc && old.rmap) { | |
4730 | int ret; | |
4731 | ||
72dc67a6 | 4732 | down_write(¤t->mm->mmap_sem); |
0de10343 ZX |
4733 | ret = do_munmap(current->mm, old.userspace_addr, |
4734 | old.npages * PAGE_SIZE); | |
72dc67a6 | 4735 | up_write(¤t->mm->mmap_sem); |
0de10343 ZX |
4736 | if (ret < 0) |
4737 | printk(KERN_WARNING | |
4738 | "kvm_vm_ioctl_set_memory_region: " | |
4739 | "failed to munmap memory\n"); | |
4740 | } | |
4741 | } | |
4742 | } | |
4743 | ||
7c8a83b7 | 4744 | spin_lock(&kvm->mmu_lock); |
f05e70ac | 4745 | if (!kvm->arch.n_requested_mmu_pages) { |
0de10343 ZX |
4746 | unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); |
4747 | kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); | |
4748 | } | |
4749 | ||
4750 | kvm_mmu_slot_remove_write_access(kvm, mem->slot); | |
7c8a83b7 | 4751 | spin_unlock(&kvm->mmu_lock); |
0de10343 ZX |
4752 | kvm_flush_remote_tlbs(kvm); |
4753 | ||
4754 | return 0; | |
4755 | } | |
1d737c8a | 4756 | |
34d4cb8f MT |
4757 | void kvm_arch_flush_shadow(struct kvm *kvm) |
4758 | { | |
4759 | kvm_mmu_zap_all(kvm); | |
8986ecc0 | 4760 | kvm_reload_remote_mmus(kvm); |
34d4cb8f MT |
4761 | } |
4762 | ||
1d737c8a ZX |
4763 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
4764 | { | |
a4535290 | 4765 | return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE |
0496fbb9 JK |
4766 | || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED |
4767 | || vcpu->arch.nmi_pending; | |
1d737c8a | 4768 | } |
5736199a | 4769 | |
5736199a ZX |
4770 | void kvm_vcpu_kick(struct kvm_vcpu *vcpu) |
4771 | { | |
32f88400 MT |
4772 | int me; |
4773 | int cpu = vcpu->cpu; | |
5736199a ZX |
4774 | |
4775 | if (waitqueue_active(&vcpu->wq)) { | |
4776 | wake_up_interruptible(&vcpu->wq); | |
4777 | ++vcpu->stat.halt_wakeup; | |
4778 | } | |
32f88400 MT |
4779 | |
4780 | me = get_cpu(); | |
4781 | if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu)) | |
4782 | if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests)) | |
4783 | smp_send_reschedule(cpu); | |
e9571ed5 | 4784 | put_cpu(); |
5736199a | 4785 | } |
78646121 GN |
4786 | |
4787 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
4788 | { | |
4789 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
4790 | } |