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KVM: x86: allow RSM from 64-bit mode
[mirror_ubuntu-jammy-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
5fb76f9b 39#include <linux/module.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
aec51dc4 56#include <trace/events/kvm.h>
2ed152af 57
229456fc
MT		 58#define CREATE_TRACE_POINTS
59#include "trace.h"
043405e1 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
313a3dc7 71#define MAX_IO_MSRS 256
890ca9ae 72#define KVM_MAX_MCE_BANKS 32
5854dbca 73#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 74
0f65dd70
AK		 75#define emul_to_vcpu(ctxt) \
76 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
77
50a37eb4
JR		 78/* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82#ifdef CONFIG_X86_64
1260edbe
LJ		 83static
84u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 85#else
1260edbe 86static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 87#endif
313a3dc7 88
ba1389b7
AK		 89#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 91
cb142eb7 92static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 93static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 94static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 95
97896d04 96struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 97EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 98
476bc001
RR		 99static bool ignore_msrs = 0;
100module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 101
9ed96e87
MT		 102unsigned int min_timer_period_us = 500;
103module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
104
630994b3
MT		 105static bool __read_mostly kvmclock_periodic_sync = true;
106module_param(kvmclock_periodic_sync, bool, S_IRUGO);
107
92a1f12d
JR		 108bool kvm_has_tsc_control;
109EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
110u32 kvm_max_guest_tsc_khz;
111EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
112
cc578287
ZA		 113/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
114static u32 tsc_tolerance_ppm = 250;
115module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
116
d0659d94
MT		 117/* lapic timer advance (tscdeadline mode only) in nanoseconds */
118unsigned int lapic_timer_advance_ns = 0;
119module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
120
16a96021
MT		 121static bool backwards_tsc_observed = false;
122
18863bdd
AK		 123#define KVM_NR_SHARED_MSRS 16
124
125struct kvm_shared_msrs_global {
126 int nr;
2bf78fa7 127 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 128};
129
130struct kvm_shared_msrs {
131 struct user_return_notifier urn;
132 bool registered;
2bf78fa7
SY		 133 struct kvm_shared_msr_values {
134 u64 host;
135 u64 curr;
136 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 137};
138
139static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 140static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 141
417bc304 142struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 143 { "pf_fixed", VCPU_STAT(pf_fixed) },
144 { "pf_guest", VCPU_STAT(pf_guest) },
145 { "tlb_flush", VCPU_STAT(tlb_flush) },
146 { "invlpg", VCPU_STAT(invlpg) },
147 { "exits", VCPU_STAT(exits) },
148 { "io_exits", VCPU_STAT(io_exits) },
149 { "mmio_exits", VCPU_STAT(mmio_exits) },
150 { "signal_exits", VCPU_STAT(signal_exits) },
151 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 152 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 153 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 154 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 155 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
ba1389b7 156 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 157 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 158 { "request_irq", VCPU_STAT(request_irq_exits) },
159 { "irq_exits", VCPU_STAT(irq_exits) },
160 { "host_state_reload", VCPU_STAT(host_state_reload) },
161 { "efer_reload", VCPU_STAT(efer_reload) },
162 { "fpu_reload", VCPU_STAT(fpu_reload) },
163 { "insn_emulation", VCPU_STAT(insn_emulation) },
164 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 165 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 166 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 167 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
168 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
169 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
170 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
171 { "mmu_flooded", VM_STAT(mmu_flooded) },
172 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 173 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 174 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 175 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 176 { "largepages", VM_STAT(lpages) },
417bc304
HB		 177 { NULL }
178};
179
2acf923e
DC		 180u64 __read_mostly host_xcr0;
181
b6785def 182static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 183
af585b92
GN		 184static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
185{
186 int i;
187 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
188 vcpu->arch.apf.gfns[i] = ~0;
189}
190
18863bdd
AK		 191static void kvm_on_user_return(struct user_return_notifier *urn)
192{
193 unsigned slot;
18863bdd
AK		 194 struct kvm_shared_msrs *locals
195 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 196 struct kvm_shared_msr_values *values;
18863bdd
AK		 197
198 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 199 values = &locals->values[slot];
200 if (values->host != values->curr) {
201 wrmsrl(shared_msrs_global.msrs[slot], values->host);
202 values->curr = values->host;
18863bdd
AK		 203 }
204 }
205 locals->registered = false;
206 user_return_notifier_unregister(urn);
207}
208
2bf78fa7 209static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 210{
18863bdd 211 u64 value;
013f6a5d
MT		 212 unsigned int cpu = smp_processor_id();
213 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 214
2bf78fa7
SY		 215 /* only read, and nobody should modify it at this time,
216 * so don't need lock */
217 if (slot >= shared_msrs_global.nr) {
218 printk(KERN_ERR "kvm: invalid MSR slot!");
219 return;
220 }
221 rdmsrl_safe(msr, &value);
222 smsr->values[slot].host = value;
223 smsr->values[slot].curr = value;
224}
225
226void kvm_define_shared_msr(unsigned slot, u32 msr)
227{
0123be42 228 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 229 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 230 if (slot >= shared_msrs_global.nr)
231 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 232}
233EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
234
235static void kvm_shared_msr_cpu_online(void)
236{
237 unsigned i;
18863bdd
AK		 238
239 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 240 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 241}
242
8b3c3104 243int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 244{
013f6a5d
MT		 245 unsigned int cpu = smp_processor_id();
246 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 247 int err;
18863bdd 248
2bf78fa7 249 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 250 return 0;
2bf78fa7 251 smsr->values[slot].curr = value;
8b3c3104
AH		 252 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
253 if (err)
254 return 1;
255
18863bdd
AK		 256 if (!smsr->registered) {
257 smsr->urn.on_user_return = kvm_on_user_return;
258 user_return_notifier_register(&smsr->urn);
259 smsr->registered = true;
260 }
8b3c3104 261 return 0;
18863bdd
AK		 262}
263EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
264
13a34e06 265static void drop_user_return_notifiers(void)
3548bab5 266{
013f6a5d
MT		 267 unsigned int cpu = smp_processor_id();
268 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 269
270 if (smsr->registered)
271 kvm_on_user_return(&smsr->urn);
272}
273
6866b83e
CO		 274u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
275{
8a5a87d9 276 return vcpu->arch.apic_base;
6866b83e
CO		 277}
278EXPORT_SYMBOL_GPL(kvm_get_apic_base);
279
58cb628d
JK		 280int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
281{
282 u64 old_state = vcpu->arch.apic_base &
283 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
284 u64 new_state = msr_info->data &
285 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
286 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
287 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
288
289 if (!msr_info->host_initiated &&
290 ((msr_info->data & reserved_bits) != 0 ||
291 new_state == X2APIC_ENABLE ||
292 (new_state == MSR_IA32_APICBASE_ENABLE &&
293 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
294 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
295 old_state == 0)))
296 return 1;
297
298 kvm_lapic_set_base(vcpu, msr_info->data);
299 return 0;
6866b83e
CO		 300}
301EXPORT_SYMBOL_GPL(kvm_set_apic_base);
302
2605fc21 303asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 304{
305 /* Fault while not rebooting. We want the trace. */
306 BUG();
307}
308EXPORT_SYMBOL_GPL(kvm_spurious_fault);
309
3fd28fce
ED		 310#define EXCPT_BENIGN 0
311#define EXCPT_CONTRIBUTORY 1
312#define EXCPT_PF 2
313
314static int exception_class(int vector)
315{
316 switch (vector) {
317 case PF_VECTOR:
318 return EXCPT_PF;
319 case DE_VECTOR:
320 case TS_VECTOR:
321 case NP_VECTOR:
322 case SS_VECTOR:
323 case GP_VECTOR:
324 return EXCPT_CONTRIBUTORY;
325 default:
326 break;
327 }
328 return EXCPT_BENIGN;
329}
330
d6e8c854
NA		 331#define EXCPT_FAULT 0
332#define EXCPT_TRAP 1
333#define EXCPT_ABORT 2
334#define EXCPT_INTERRUPT 3
335
336static int exception_type(int vector)
337{
338 unsigned int mask;
339
340 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
341 return EXCPT_INTERRUPT;
342
343 mask = 1 << vector;
344
345 /* #DB is trap, as instruction watchpoints are handled elsewhere */
346 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
347 return EXCPT_TRAP;
348
349 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
350 return EXCPT_ABORT;
351
352 /* Reserved exceptions will result in fault */
353 return EXCPT_FAULT;
354}
355
3fd28fce 356static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 357 unsigned nr, bool has_error, u32 error_code,
358 bool reinject)
3fd28fce
ED		 359{
360 u32 prev_nr;
361 int class1, class2;
362
3842d135
AK		 363 kvm_make_request(KVM_REQ_EVENT, vcpu);
364
3fd28fce
ED		 365 if (!vcpu->arch.exception.pending) {
366 queue:
3ffb2468
NA		 367 if (has_error && !is_protmode(vcpu))
368 has_error = false;
3fd28fce
ED		 369 vcpu->arch.exception.pending = true;
370 vcpu->arch.exception.has_error_code = has_error;
371 vcpu->arch.exception.nr = nr;
372 vcpu->arch.exception.error_code = error_code;
3f0fd292 373 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 374 return;
375 }
376
377 /* to check exception */
378 prev_nr = vcpu->arch.exception.nr;
379 if (prev_nr == DF_VECTOR) {
380 /* triple fault -> shutdown */
a8eeb04a 381 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 382 return;
383 }
384 class1 = exception_class(prev_nr);
385 class2 = exception_class(nr);
386 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
387 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
388 /* generate double fault per SDM Table 5-5 */
389 vcpu->arch.exception.pending = true;
390 vcpu->arch.exception.has_error_code = true;
391 vcpu->arch.exception.nr = DF_VECTOR;
392 vcpu->arch.exception.error_code = 0;
393 } else
394 /* replace previous exception with a new one in a hope
395 that instruction re-execution will regenerate lost
396 exception */
397 goto queue;
398}
399
298101da
AK		 400void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
401{
ce7ddec4 402 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 403}
404EXPORT_SYMBOL_GPL(kvm_queue_exception);
405
ce7ddec4
JR		 406void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
407{
408 kvm_multiple_exception(vcpu, nr, false, 0, true);
409}
410EXPORT_SYMBOL_GPL(kvm_requeue_exception);
411
db8fcefa 412void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 413{
db8fcefa
AP		 414 if (err)
415 kvm_inject_gp(vcpu, 0);
416 else
417 kvm_x86_ops->skip_emulated_instruction(vcpu);
418}
419EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 420
6389ee94 421void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 422{
423 ++vcpu->stat.pf_guest;
6389ee94
AK		 424 vcpu->arch.cr2 = fault->address;
425 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 426}
27d6c865 427EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 428
ef54bcfe 429static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 430{
6389ee94
AK		 431 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
432 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 433 else
6389ee94 434 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 435
436 return fault->nested_page_fault;
d4f8cf66
JR		 437}
438
3419ffc8
SY		 439void kvm_inject_nmi(struct kvm_vcpu *vcpu)
440{
7460fb4a
AK		 441 atomic_inc(&vcpu->arch.nmi_queued);
442 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 443}
444EXPORT_SYMBOL_GPL(kvm_inject_nmi);
445
298101da
AK		 446void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
447{
ce7ddec4 448 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 449}
450EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
451
ce7ddec4
JR		 452void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
453{
454 kvm_multiple_exception(vcpu, nr, true, error_code, true);
455}
456EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
457
0a79b009
AK		 458/*
459 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
460 * a #GP and return false.
461 */
462bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 463{
0a79b009
AK		 464 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
465 return true;
466 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
467 return false;
298101da 468}
0a79b009 469EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 470
16f8a6f9
NA		 471bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
472{
473 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
474 return true;
475
476 kvm_queue_exception(vcpu, UD_VECTOR);
477 return false;
478}
479EXPORT_SYMBOL_GPL(kvm_require_dr);
480
ec92fe44
JR		 481/*
482 * This function will be used to read from the physical memory of the currently
54bf36aa 483 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 484 * can read from guest physical or from the guest's guest physical memory.
485 */
486int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
487 gfn_t ngfn, void *data, int offset, int len,
488 u32 access)
489{
54987b7a 490 struct x86_exception exception;
ec92fe44
JR		 491 gfn_t real_gfn;
492 gpa_t ngpa;
493
494 ngpa = gfn_to_gpa(ngfn);
54987b7a 495 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 496 if (real_gfn == UNMAPPED_GVA)
497 return -EFAULT;
498
499 real_gfn = gpa_to_gfn(real_gfn);
500
54bf36aa 501 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 502}
503EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
504
69b0049a 505static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 506 void *data, int offset, int len, u32 access)
507{
508 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
509 data, offset, len, access);
510}
511
a03490ed
CO		 512/*
513 * Load the pae pdptrs. Return true is they are all valid.
514 */
ff03a073 515int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 516{
517 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
518 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
519 int i;
520 int ret;
ff03a073 521 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 522
ff03a073
JR		 523 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
524 offset * sizeof(u64), sizeof(pdpte),
525 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 526 if (ret < 0) {
527 ret = 0;
528 goto out;
529 }
530 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 531 if (is_present_gpte(pdpte[i]) &&
a0a64f50
XG		 532 (pdpte[i] &
533 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 534 ret = 0;
535 goto out;
536 }
537 }
538 ret = 1;
539
ff03a073 540 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 541 __set_bit(VCPU_EXREG_PDPTR,
542 (unsigned long *)&vcpu->arch.regs_avail);
543 __set_bit(VCPU_EXREG_PDPTR,
544 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 545out:
a03490ed
CO		 546
547 return ret;
548}
cc4b6871 549EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 550
d835dfec
AK		 551static bool pdptrs_changed(struct kvm_vcpu *vcpu)
552{
ff03a073 553 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 554 bool changed = true;
3d06b8bf
JR		 555 int offset;
556 gfn_t gfn;
d835dfec
AK		 557 int r;
558
559 if (is_long_mode(vcpu) || !is_pae(vcpu))
560 return false;
561
6de4f3ad
AK		 562 if (!test_bit(VCPU_EXREG_PDPTR,
563 (unsigned long *)&vcpu->arch.regs_avail))
564 return true;
565
9f8fe504
AK		 566 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
567 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 568 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
569 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 570 if (r < 0)
571 goto out;
ff03a073 572 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 573out:
d835dfec
AK		 574
575 return changed;
576}
577
49a9b07e 578int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 579{
aad82703 580 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 581 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 582
f9a48e6a
AK		 583 cr0 |= X86_CR0_ET;
584
ab344828 585#ifdef CONFIG_X86_64
0f12244f
GN		 586 if (cr0 & 0xffffffff00000000UL)
587 return 1;
ab344828
GN		 588#endif
589
590 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 591
0f12244f
GN		 592 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
593 return 1;
a03490ed 594
0f12244f
GN		 595 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
596 return 1;
a03490ed
CO		 597
598 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
599#ifdef CONFIG_X86_64
f6801dff 600 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 601 int cs_db, cs_l;
602
0f12244f
GN		 603 if (!is_pae(vcpu))
604 return 1;
a03490ed 605 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 606 if (cs_l)
607 return 1;
a03490ed
CO		 608 } else
609#endif
ff03a073 610 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 611 kvm_read_cr3(vcpu)))
0f12244f 612 return 1;
a03490ed
CO		 613 }
614
ad756a16
MJ		 615 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
616 return 1;
617
a03490ed 618 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 619
d170c419 620 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 621 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 622 kvm_async_pf_hash_reset(vcpu);
623 }
e5f3f027 624
aad82703
SY		 625 if ((cr0 ^ old_cr0) & update_bits)
626 kvm_mmu_reset_context(vcpu);
b18d5431
XG		 627
628 if ((cr0 ^ old_cr0) & X86_CR0_CD)
629 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
630
0f12244f
GN		 631 return 0;
632}
2d3ad1f4 633EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 634
2d3ad1f4 635void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 636{
49a9b07e 637 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 638}
2d3ad1f4 639EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 640
42bdf991
MT		 641static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
642{
643 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
644 !vcpu->guest_xcr0_loaded) {
645 /* kvm_set_xcr() also depends on this */
646 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
647 vcpu->guest_xcr0_loaded = 1;
648 }
649}
650
651static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
652{
653 if (vcpu->guest_xcr0_loaded) {
654 if (vcpu->arch.xcr0 != host_xcr0)
655 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
656 vcpu->guest_xcr0_loaded = 0;
657 }
658}
659
69b0049a 660static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 661{
56c103ec
LJ		 662 u64 xcr0 = xcr;
663 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 664 u64 valid_bits;
2acf923e
DC		 665
666 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
667 if (index != XCR_XFEATURE_ENABLED_MASK)
668 return 1;
2acf923e
DC		 669 if (!(xcr0 & XSTATE_FP))
670 return 1;
671 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
672 return 1;
46c34cb0
PB		 673
674 /*
675 * Do not allow the guest to set bits that we do not support
676 * saving. However, xcr0 bit 0 is always set, even if the
677 * emulated CPU does not support XSAVE (see fx_init).
678 */
679 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
680 if (xcr0 & ~valid_bits)
2acf923e 681 return 1;
46c34cb0 682
390bd528
LJ		 683 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
684 return 1;
685
612263b3
CP		 686 if (xcr0 & XSTATE_AVX512) {
687 if (!(xcr0 & XSTATE_YMM))
688 return 1;
689 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
690 return 1;
691 }
42bdf991 692 kvm_put_guest_xcr0(vcpu);
2acf923e 693 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 694
695 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
696 kvm_update_cpuid(vcpu);
2acf923e
DC		 697 return 0;
698}
699
700int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
701{
764bcbc5
Z		 702 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
703 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 704 kvm_inject_gp(vcpu, 0);
705 return 1;
706 }
707 return 0;
708}
709EXPORT_SYMBOL_GPL(kvm_set_xcr);
710
a83b29c6 711int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 712{
fc78f519 713 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f
XG		 714 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
715 X86_CR4_SMEP | X86_CR4_SMAP;
716
0f12244f
GN		 717 if (cr4 & CR4_RESERVED_BITS)
718 return 1;
a03490ed 719
2acf923e
DC		 720 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
721 return 1;
722
c68b734f
YW		 723 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
724 return 1;
725
97ec8c06
FW		 726 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
727 return 1;
728
afcbf13f 729 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 730 return 1;
731
a03490ed 732 if (is_long_mode(vcpu)) {
0f12244f
GN		 733 if (!(cr4 & X86_CR4_PAE))
734 return 1;
a2edf57f
AK		 735 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
736 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 737 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
738 kvm_read_cr3(vcpu)))
0f12244f
GN		 739 return 1;
740
ad756a16
MJ		 741 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
742 if (!guest_cpuid_has_pcid(vcpu))
743 return 1;
744
745 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
746 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
747 return 1;
748 }
749
5e1746d6 750 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 751 return 1;
a03490ed 752
ad756a16
MJ		 753 if (((cr4 ^ old_cr4) & pdptr_bits) ||
754 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 755 kvm_mmu_reset_context(vcpu);
0f12244f 756
2acf923e 757 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 758 kvm_update_cpuid(vcpu);
2acf923e 759
0f12244f
GN		 760 return 0;
761}
2d3ad1f4 762EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 763
2390218b 764int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 765{
ac146235 766#ifdef CONFIG_X86_64
9d88fca7 767 cr3 &= ~CR3_PCID_INVD;
ac146235 768#endif
9d88fca7 769
9f8fe504 770 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 771 kvm_mmu_sync_roots(vcpu);
77c3913b 772 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 773 return 0;
d835dfec
AK		 774 }
775
a03490ed 776 if (is_long_mode(vcpu)) {
d9f89b88
JK		 777 if (cr3 & CR3_L_MODE_RESERVED_BITS)
778 return 1;
779 } else if (is_pae(vcpu) && is_paging(vcpu) &&
780 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 781 return 1;
a03490ed 782
0f12244f 783 vcpu->arch.cr3 = cr3;
aff48baa 784 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 785 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 786 return 0;
787}
2d3ad1f4 788EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 789
eea1cff9 790int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 791{
0f12244f
GN		 792 if (cr8 & CR8_RESERVED_BITS)
793 return 1;
35754c98 794 if (lapic_in_kernel(vcpu))
a03490ed
CO		 795 kvm_lapic_set_tpr(vcpu, cr8);
796 else
ad312c7c 797 vcpu->arch.cr8 = cr8;
0f12244f
GN		 798 return 0;
799}
2d3ad1f4 800EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 801
2d3ad1f4 802unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 803{
35754c98 804 if (lapic_in_kernel(vcpu))
a03490ed
CO		 805 return kvm_lapic_get_cr8(vcpu);
806 else
ad312c7c 807 return vcpu->arch.cr8;
a03490ed 808}
2d3ad1f4 809EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 810
ae561ede
NA		 811static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
812{
813 int i;
814
815 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
816 for (i = 0; i < KVM_NR_DB_REGS; i++)
817 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
818 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
819 }
820}
821
73aaf249
JK		 822static void kvm_update_dr6(struct kvm_vcpu *vcpu)
823{
824 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
825 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
826}
827
c8639010
JK		 828static void kvm_update_dr7(struct kvm_vcpu *vcpu)
829{
830 unsigned long dr7;
831
832 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
833 dr7 = vcpu->arch.guest_debug_dr7;
834 else
835 dr7 = vcpu->arch.dr7;
836 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 837 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
838 if (dr7 & DR7_BP_EN_MASK)
839 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 840}
841
6f43ed01
NA		 842static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
843{
844 u64 fixed = DR6_FIXED_1;
845
846 if (!guest_cpuid_has_rtm(vcpu))
847 fixed |= DR6_RTM;
848 return fixed;
849}
850
338dbc97 851static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 852{
853 switch (dr) {
854 case 0 ... 3:
855 vcpu->arch.db[dr] = val;
856 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
857 vcpu->arch.eff_db[dr] = val;
858 break;
859 case 4:
020df079
GN		 860 /* fall through */
861 case 6:
338dbc97
GN		 862 if (val & 0xffffffff00000000ULL)
863 return -1; /* #GP */
6f43ed01 864 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 865 kvm_update_dr6(vcpu);
020df079
GN		 866 break;
867 case 5:
020df079
GN		 868 /* fall through */
869 default: /* 7 */
338dbc97
GN		 870 if (val & 0xffffffff00000000ULL)
871 return -1; /* #GP */
020df079 872 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 873 kvm_update_dr7(vcpu);
020df079
GN		 874 break;
875 }
876
877 return 0;
878}
338dbc97
GN		 879
880int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
881{
16f8a6f9 882 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 883 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 884 return 1;
885 }
886 return 0;
338dbc97 887}
020df079
GN		 888EXPORT_SYMBOL_GPL(kvm_set_dr);
889
16f8a6f9 890int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 891{
892 switch (dr) {
893 case 0 ... 3:
894 *val = vcpu->arch.db[dr];
895 break;
896 case 4:
020df079
GN		 897 /* fall through */
898 case 6:
73aaf249
JK		 899 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
900 *val = vcpu->arch.dr6;
901 else
902 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 903 break;
904 case 5:
020df079
GN		 905 /* fall through */
906 default: /* 7 */
907 *val = vcpu->arch.dr7;
908 break;
909 }
338dbc97
GN		 910 return 0;
911}
020df079
GN		 912EXPORT_SYMBOL_GPL(kvm_get_dr);
913
022cd0e8
AK		 914bool kvm_rdpmc(struct kvm_vcpu *vcpu)
915{
916 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
917 u64 data;
918 int err;
919
c6702c9d 920 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 921 if (err)
922 return err;
923 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
924 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
925 return err;
926}
927EXPORT_SYMBOL_GPL(kvm_rdpmc);
928
043405e1
CO		 929/*
930 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
931 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
932 *
933 * This list is modified at module load time to reflect the
e3267cbb 934 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 935 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
936 * may depend on host virtualization features rather than host cpu features.
043405e1 937 */
e3267cbb 938
043405e1
CO		 939static u32 msrs_to_save[] = {
940 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 941 MSR_STAR,
043405e1
CO		 942#ifdef CONFIG_X86_64
943 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
944#endif
b3897a49 945 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 946 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 947};
948
949static unsigned num_msrs_to_save;
950
62ef68bb
PB		 951static u32 emulated_msrs[] = {
952 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
953 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
954 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
955 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 956 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
957 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 958 HV_X64_MSR_RESET,
11c4b1ca 959 HV_X64_MSR_VP_INDEX,
9eec50b8 960 HV_X64_MSR_VP_RUNTIME,
62ef68bb
PB		 961 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
962 MSR_KVM_PV_EOI_EN,
963
ba904635 964 MSR_IA32_TSC_ADJUST,
a3e06bbe 965 MSR_IA32_TSCDEADLINE,
043405e1 966 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 967 MSR_IA32_MCG_STATUS,
968 MSR_IA32_MCG_CTL,
64d60670 969 MSR_IA32_SMBASE,
043405e1
CO		 970};
971
62ef68bb
PB		 972static unsigned num_emulated_msrs;
973
384bb783 974bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 975{
b69e8cae 976 if (efer & efer_reserved_bits)
384bb783 977 return false;
15c4a640 978
1b2fd70c
AG		 979 if (efer & EFER_FFXSR) {
980 struct kvm_cpuid_entry2 *feat;
981
982 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 983 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 984 return false;
1b2fd70c
AG		 985 }
986
d8017474
AG		 987 if (efer & EFER_SVME) {
988 struct kvm_cpuid_entry2 *feat;
989
990 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 991 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 992 return false;
d8017474
AG		 993 }
994
384bb783
JK		 995 return true;
996}
997EXPORT_SYMBOL_GPL(kvm_valid_efer);
998
999static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1000{
1001 u64 old_efer = vcpu->arch.efer;
1002
1003 if (!kvm_valid_efer(vcpu, efer))
1004 return 1;
1005
1006 if (is_paging(vcpu)
1007 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1008 return 1;
1009
15c4a640 1010 efer &= ~EFER_LMA;
f6801dff 1011 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1012
a3d204e2
SY		 1013 kvm_x86_ops->set_efer(vcpu, efer);
1014
aad82703
SY		 1015 /* Update reserved bits */
1016 if ((efer ^ old_efer) & EFER_NX)
1017 kvm_mmu_reset_context(vcpu);
1018
b69e8cae 1019 return 0;
15c4a640
CO		 1020}
1021
f2b4b7dd
JR		 1022void kvm_enable_efer_bits(u64 mask)
1023{
1024 efer_reserved_bits &= ~mask;
1025}
1026EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1027
15c4a640
CO		 1028/*
1029 * Writes msr value into into the appropriate "register".
1030 * Returns 0 on success, non-0 otherwise.
1031 * Assumes vcpu_load() was already called.
1032 */
8fe8ab46 1033int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1034{
854e8bb1
NA		 1035 switch (msr->index) {
1036 case MSR_FS_BASE:
1037 case MSR_GS_BASE:
1038 case MSR_KERNEL_GS_BASE:
1039 case MSR_CSTAR:
1040 case MSR_LSTAR:
1041 if (is_noncanonical_address(msr->data))
1042 return 1;
1043 break;
1044 case MSR_IA32_SYSENTER_EIP:
1045 case MSR_IA32_SYSENTER_ESP:
1046 /*
1047 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1048 * non-canonical address is written on Intel but not on
1049 * AMD (which ignores the top 32-bits, because it does
1050 * not implement 64-bit SYSENTER).
1051 *
1052 * 64-bit code should hence be able to write a non-canonical
1053 * value on AMD. Making the address canonical ensures that
1054 * vmentry does not fail on Intel after writing a non-canonical
1055 * value, and that something deterministic happens if the guest
1056 * invokes 64-bit SYSENTER.
1057 */
1058 msr->data = get_canonical(msr->data);
1059 }
8fe8ab46 1060 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1061}
854e8bb1 1062EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1063
313a3dc7
CO		 1064/*
1065 * Adapt set_msr() to msr_io()'s calling convention
1066 */
609e36d3
PB		 1067static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1068{
1069 struct msr_data msr;
1070 int r;
1071
1072 msr.index = index;
1073 msr.host_initiated = true;
1074 r = kvm_get_msr(vcpu, &msr);
1075 if (r)
1076 return r;
1077
1078 *data = msr.data;
1079 return 0;
1080}
1081
313a3dc7
CO		 1082static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1083{
8fe8ab46
WA		 1084 struct msr_data msr;
1085
1086 msr.data = *data;
1087 msr.index = index;
1088 msr.host_initiated = true;
1089 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1090}
1091
16e8d74d
MT		 1092#ifdef CONFIG_X86_64
1093struct pvclock_gtod_data {
1094 seqcount_t seq;
1095
1096 struct { /* extract of a clocksource struct */
1097 int vclock_mode;
1098 cycle_t cycle_last;
1099 cycle_t mask;
1100 u32 mult;
1101 u32 shift;
1102 } clock;
1103
cbcf2dd3
TG		 1104 u64 boot_ns;
1105 u64 nsec_base;
16e8d74d
MT		 1106};
1107
1108static struct pvclock_gtod_data pvclock_gtod_data;
1109
1110static void update_pvclock_gtod(struct timekeeper *tk)
1111{
1112 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1113 u64 boot_ns;
1114
876e7881 1115 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1116
1117 write_seqcount_begin(&vdata->seq);
1118
1119 /* copy pvclock gtod data */
876e7881
PZ		 1120 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1121 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1122 vdata->clock.mask = tk->tkr_mono.mask;
1123 vdata->clock.mult = tk->tkr_mono.mult;
1124 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1125
cbcf2dd3 1126 vdata->boot_ns = boot_ns;
876e7881 1127 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1128
1129 write_seqcount_end(&vdata->seq);
1130}
1131#endif
1132
bab5bb39
NK		 1133void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1134{
1135 /*
1136 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1137 * vcpu_enter_guest. This function is only called from
1138 * the physical CPU that is running vcpu.
1139 */
1140 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1141}
16e8d74d 1142
18068523
GOC		 1143static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1144{
9ed3c444
AK		 1145 int version;
1146 int r;
50d0a0f9 1147 struct pvclock_wall_clock wc;
923de3cf 1148 struct timespec boot;
18068523
GOC		 1149
1150 if (!wall_clock)
1151 return;
1152
9ed3c444
AK		 1153 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1154 if (r)
1155 return;
1156
1157 if (version & 1)
1158 ++version; /* first time write, random junk */
1159
1160 ++version;
18068523 1161
18068523
GOC		 1162 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1163
50d0a0f9
GH		 1164 /*
1165 * The guest calculates current wall clock time by adding
34c238a1 1166 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1167 * wall clock specified here. guest system time equals host
1168 * system time for us, thus we must fill in host boot time here.
1169 */
923de3cf 1170 getboottime(&boot);
50d0a0f9 1171
4b648665
BR		 1172 if (kvm->arch.kvmclock_offset) {
1173 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1174 boot = timespec_sub(boot, ts);
1175 }
50d0a0f9
GH		 1176 wc.sec = boot.tv_sec;
1177 wc.nsec = boot.tv_nsec;
1178 wc.version = version;
18068523
GOC		 1179
1180 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1181
1182 version++;
1183 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1184}
1185
50d0a0f9
GH		 1186static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1187{
1188 uint32_t quotient, remainder;
1189
1190 /* Don't try to replace with do_div(), this one calculates
1191 * "(dividend << 32) / divisor" */
1192 __asm__ ( "divl %4"
1193 : "=a" (quotient), "=d" (remainder)
1194 : "0" (0), "1" (dividend), "r" (divisor) );
1195 return quotient;
1196}
1197
5f4e3f88
ZA		 1198static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1199 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1200{
5f4e3f88 1201 uint64_t scaled64;
50d0a0f9
GH		 1202 int32_t shift = 0;
1203 uint64_t tps64;
1204 uint32_t tps32;
1205
5f4e3f88
ZA		 1206 tps64 = base_khz * 1000LL;
1207 scaled64 = scaled_khz * 1000LL;
50933623 1208 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1209 tps64 >>= 1;
1210 shift--;
1211 }
1212
1213 tps32 = (uint32_t)tps64;
50933623
JK		 1214 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1215 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1216 scaled64 >>= 1;
1217 else
1218 tps32 <<= 1;
50d0a0f9
GH		 1219 shift++;
1220 }
1221
5f4e3f88
ZA		 1222 *pshift = shift;
1223 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1224
5f4e3f88
ZA		 1225 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1226 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1227}
1228
d828199e 1229#ifdef CONFIG_X86_64
16e8d74d 1230static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1231#endif
16e8d74d 1232
c8076604 1233static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1234static unsigned long max_tsc_khz;
c8076604 1235
cc578287 1236static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1237{
cc578287
ZA		 1238 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1239 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1240}
1241
cc578287 1242static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1243{
cc578287
ZA		 1244 u64 v = (u64)khz * (1000000 + ppm);
1245 do_div(v, 1000000);
1246 return v;
1e993611
JR		 1247}
1248
cc578287 1249static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1250{
cc578287
ZA		 1251 u32 thresh_lo, thresh_hi;
1252 int use_scaling = 0;
217fc9cf 1253
03ba32ca
MT		 1254 /* tsc_khz can be zero if TSC calibration fails */
1255 if (this_tsc_khz == 0)
1256 return;
1257
c285545f
ZA		 1258 /* Compute a scale to convert nanoseconds in TSC cycles */
1259 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1260 &vcpu->arch.virtual_tsc_shift,
1261 &vcpu->arch.virtual_tsc_mult);
1262 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1263
1264 /*
1265 * Compute the variation in TSC rate which is acceptable
1266 * within the range of tolerance and decide if the
1267 * rate being applied is within that bounds of the hardware
1268 * rate. If so, no scaling or compensation need be done.
1269 */
1270 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1271 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1272 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1273 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1274 use_scaling = 1;
1275 }
1276 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1277}
1278
1279static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1280{
e26101b1 1281 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1282 vcpu->arch.virtual_tsc_mult,
1283 vcpu->arch.virtual_tsc_shift);
e26101b1 1284 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1285 return tsc;
1286}
1287
69b0049a 1288static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1289{
1290#ifdef CONFIG_X86_64
1291 bool vcpus_matched;
b48aa97e
MT		 1292 struct kvm_arch *ka = &vcpu->kvm->arch;
1293 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1294
1295 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1296 atomic_read(&vcpu->kvm->online_vcpus));
1297
7f187922
MT		 1298 /*
1299 * Once the masterclock is enabled, always perform request in
1300 * order to update it.
1301 *
1302 * In order to enable masterclock, the host clocksource must be TSC
1303 * and the vcpus need to have matched TSCs. When that happens,
1304 * perform request to enable masterclock.
1305 */
1306 if (ka->use_master_clock ||
1307 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1308 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1309
1310 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1311 atomic_read(&vcpu->kvm->online_vcpus),
1312 ka->use_master_clock, gtod->clock.vclock_mode);
1313#endif
1314}
1315
ba904635
WA		 1316static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1317{
1318 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1319 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1320}
1321
8fe8ab46 1322void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1323{
1324 struct kvm *kvm = vcpu->kvm;
f38e098f 1325 u64 offset, ns, elapsed;
99e3e30a 1326 unsigned long flags;
02626b6a 1327 s64 usdiff;
b48aa97e 1328 bool matched;
0d3da0d2 1329 bool already_matched;
8fe8ab46 1330 u64 data = msr->data;
99e3e30a 1331
038f8c11 1332 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1333 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1334 ns = get_kernel_ns();
f38e098f 1335 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1336
03ba32ca 1337 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1338 int faulted = 0;
1339
03ba32ca
MT		 1340 /* n.b - signed multiplication and division required */
1341 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1342#ifdef CONFIG_X86_64
03ba32ca 1343 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1344#else
03ba32ca 1345 /* do_div() only does unsigned */
8915aa27
MT		 1346 asm("1: idivl %[divisor]\n"
1347 "2: xor %%edx, %%edx\n"
1348 " movl $0, %[faulted]\n"
1349 "3:\n"
1350 ".section .fixup,\"ax\"\n"
1351 "4: movl $1, %[faulted]\n"
1352 " jmp 3b\n"
1353 ".previous\n"
1354
1355 _ASM_EXTABLE(1b, 4b)
1356
1357 : "=A"(usdiff), [faulted] "=r" (faulted)
1358 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1359
5d3cb0f6 1360#endif
03ba32ca
MT		 1361 do_div(elapsed, 1000);
1362 usdiff -= elapsed;
1363 if (usdiff < 0)
1364 usdiff = -usdiff;
8915aa27
MT		 1365
1366 /* idivl overflow => difference is larger than USEC_PER_SEC */
1367 if (faulted)
1368 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1369 } else
1370 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1371
1372 /*
5d3cb0f6
ZA		 1373 * Special case: TSC write with a small delta (1 second) of virtual
1374 * cycle time against real time is interpreted as an attempt to
1375 * synchronize the CPU.
1376 *
1377 * For a reliable TSC, we can match TSC offsets, and for an unstable
1378 * TSC, we add elapsed time in this computation. We could let the
1379 * compensation code attempt to catch up if we fall behind, but
1380 * it's better to try to match offsets from the beginning.
1381 */
02626b6a 1382 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1383 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1384 if (!check_tsc_unstable()) {
e26101b1 1385 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1386 pr_debug("kvm: matched tsc offset for %llu\n", data);
1387 } else {
857e4099 1388 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1389 data += delta;
1390 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1391 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1392 }
b48aa97e 1393 matched = true;
0d3da0d2 1394 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1395 } else {
1396 /*
1397 * We split periods of matched TSC writes into generations.
1398 * For each generation, we track the original measured
1399 * nanosecond time, offset, and write, so if TSCs are in
1400 * sync, we can match exact offset, and if not, we can match
4a969980 1401 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1402 *
1403 * These values are tracked in kvm->arch.cur_xxx variables.
1404 */
1405 kvm->arch.cur_tsc_generation++;
1406 kvm->arch.cur_tsc_nsec = ns;
1407 kvm->arch.cur_tsc_write = data;
1408 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1409 matched = false;
0d3da0d2 1410 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1411 kvm->arch.cur_tsc_generation, data);
f38e098f 1412 }
e26101b1
ZA		 1413
1414 /*
1415 * We also track th most recent recorded KHZ, write and time to
1416 * allow the matching interval to be extended at each write.
1417 */
f38e098f
ZA		 1418 kvm->arch.last_tsc_nsec = ns;
1419 kvm->arch.last_tsc_write = data;
5d3cb0f6 1420 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1421
b183aa58 1422 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1423
1424 /* Keep track of which generation this VCPU has synchronized to */
1425 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1426 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1427 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1428
ba904635
WA		 1429 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1430 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1431 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1432 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1433
1434 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1435 if (!matched) {
b48aa97e 1436 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1437 } else if (!already_matched) {
1438 kvm->arch.nr_vcpus_matched_tsc++;
1439 }
b48aa97e
MT		 1440
1441 kvm_track_tsc_matching(vcpu);
1442 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1443}
e26101b1 1444
99e3e30a
ZA		 1445EXPORT_SYMBOL_GPL(kvm_write_tsc);
1446
d828199e
MT		 1447#ifdef CONFIG_X86_64
1448
1449static cycle_t read_tsc(void)
1450{
03b9730b
AL		 1451 cycle_t ret = (cycle_t)rdtsc_ordered();
1452 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1453
1454 if (likely(ret >= last))
1455 return ret;
1456
1457 /*
1458 * GCC likes to generate cmov here, but this branch is extremely
1459 * predictable (it's just a funciton of time and the likely is
1460 * very likely) and there's a data dependence, so force GCC
1461 * to generate a branch instead. I don't barrier() because
1462 * we don't actually need a barrier, and if this function
1463 * ever gets inlined it will generate worse code.
1464 */
1465 asm volatile ("");
1466 return last;
1467}
1468
1469static inline u64 vgettsc(cycle_t *cycle_now)
1470{
1471 long v;
1472 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1473
1474 *cycle_now = read_tsc();
1475
1476 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1477 return v * gtod->clock.mult;
1478}
1479
cbcf2dd3 1480static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1481{
cbcf2dd3 1482 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1483 unsigned long seq;
d828199e 1484 int mode;
cbcf2dd3 1485 u64 ns;
d828199e 1486
d828199e
MT		 1487 do {
1488 seq = read_seqcount_begin(&gtod->seq);
1489 mode = gtod->clock.vclock_mode;
cbcf2dd3 1490 ns = gtod->nsec_base;
d828199e
MT		 1491 ns += vgettsc(cycle_now);
1492 ns >>= gtod->clock.shift;
cbcf2dd3 1493 ns += gtod->boot_ns;
d828199e 1494 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1495 *t = ns;
d828199e
MT		 1496
1497 return mode;
1498}
1499
1500/* returns true if host is using tsc clocksource */
1501static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1502{
d828199e
MT		 1503 /* checked again under seqlock below */
1504 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1505 return false;
1506
cbcf2dd3 1507 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1508}
1509#endif
1510
1511/*
1512 *
b48aa97e
MT		 1513 * Assuming a stable TSC across physical CPUS, and a stable TSC
1514 * across virtual CPUs, the following condition is possible.
1515 * Each numbered line represents an event visible to both
d828199e
MT		 1516 * CPUs at the next numbered event.
1517 *
1518 * "timespecX" represents host monotonic time. "tscX" represents
1519 * RDTSC value.
1520 *
1521 * VCPU0 on CPU0 | VCPU1 on CPU1
1522 *
1523 * 1. read timespec0,tsc0
1524 * 2. | timespec1 = timespec0 + N
1525 * | tsc1 = tsc0 + M
1526 * 3. transition to guest | transition to guest
1527 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1528 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1529 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1530 *
1531 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1532 *
1533 * - ret0 < ret1
1534 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1535 * ...
1536 * - 0 < N - M => M < N
1537 *
1538 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1539 * always the case (the difference between two distinct xtime instances
1540 * might be smaller then the difference between corresponding TSC reads,
1541 * when updating guest vcpus pvclock areas).
1542 *
1543 * To avoid that problem, do not allow visibility of distinct
1544 * system_timestamp/tsc_timestamp values simultaneously: use a master
1545 * copy of host monotonic time values. Update that master copy
1546 * in lockstep.
1547 *
b48aa97e 1548 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1549 *
1550 */
1551
1552static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1553{
1554#ifdef CONFIG_X86_64
1555 struct kvm_arch *ka = &kvm->arch;
1556 int vclock_mode;
b48aa97e
MT		 1557 bool host_tsc_clocksource, vcpus_matched;
1558
1559 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1560 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1561
1562 /*
1563 * If the host uses TSC clock, then passthrough TSC as stable
1564 * to the guest.
1565 */
b48aa97e 1566 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1567 &ka->master_kernel_ns,
1568 &ka->master_cycle_now);
1569
16a96021 1570 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1571 && !backwards_tsc_observed
1572 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1573
d828199e
MT		 1574 if (ka->use_master_clock)
1575 atomic_set(&kvm_guest_has_master_clock, 1);
1576
1577 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1578 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1579 vcpus_matched);
d828199e
MT		 1580#endif
1581}
1582
2e762ff7
MT		 1583static void kvm_gen_update_masterclock(struct kvm *kvm)
1584{
1585#ifdef CONFIG_X86_64
1586 int i;
1587 struct kvm_vcpu *vcpu;
1588 struct kvm_arch *ka = &kvm->arch;
1589
1590 spin_lock(&ka->pvclock_gtod_sync_lock);
1591 kvm_make_mclock_inprogress_request(kvm);
1592 /* no guest entries from this point */
1593 pvclock_update_vm_gtod_copy(kvm);
1594
1595 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1596 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1597
1598 /* guest entries allowed */
1599 kvm_for_each_vcpu(i, vcpu, kvm)
1600 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1601
1602 spin_unlock(&ka->pvclock_gtod_sync_lock);
1603#endif
1604}
1605
34c238a1 1606static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1607{
d828199e 1608 unsigned long flags, this_tsc_khz;
18068523 1609 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1610 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1611 s64 kernel_ns;
d828199e 1612 u64 tsc_timestamp, host_tsc;
0b79459b 1613 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1614 u8 pvclock_flags;
d828199e
MT		 1615 bool use_master_clock;
1616
1617 kernel_ns = 0;
1618 host_tsc = 0;
18068523 1619
d828199e
MT		 1620 /*
1621 * If the host uses TSC clock, then passthrough TSC as stable
1622 * to the guest.
1623 */
1624 spin_lock(&ka->pvclock_gtod_sync_lock);
1625 use_master_clock = ka->use_master_clock;
1626 if (use_master_clock) {
1627 host_tsc = ka->master_cycle_now;
1628 kernel_ns = ka->master_kernel_ns;
1629 }
1630 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1631
1632 /* Keep irq disabled to prevent changes to the clock */
1633 local_irq_save(flags);
89cbc767 1634 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1635 if (unlikely(this_tsc_khz == 0)) {
1636 local_irq_restore(flags);
1637 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1638 return 1;
1639 }
d828199e 1640 if (!use_master_clock) {
4ea1636b 1641 host_tsc = rdtsc();
d828199e
MT		 1642 kernel_ns = get_kernel_ns();
1643 }
1644
1645 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1646
c285545f
ZA		 1647 /*
1648 * We may have to catch up the TSC to match elapsed wall clock
1649 * time for two reasons, even if kvmclock is used.
1650 * 1) CPU could have been running below the maximum TSC rate
1651 * 2) Broken TSC compensation resets the base at each VCPU
1652 * entry to avoid unknown leaps of TSC even when running
1653 * again on the same CPU. This may cause apparent elapsed
1654 * time to disappear, and the guest to stand still or run
1655 * very slowly.
1656 */
1657 if (vcpu->tsc_catchup) {
1658 u64 tsc = compute_guest_tsc(v, kernel_ns);
1659 if (tsc > tsc_timestamp) {
f1e2b260 1660 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1661 tsc_timestamp = tsc;
1662 }
50d0a0f9
GH		 1663 }
1664
18068523
GOC		 1665 local_irq_restore(flags);
1666
0b79459b 1667 if (!vcpu->pv_time_enabled)
c285545f 1668 return 0;
18068523 1669
e48672fa 1670 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1671 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1672 &vcpu->hv_clock.tsc_shift,
1673 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1674 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1675 }
1676
1677 /* With all the info we got, fill in the values */
1d5f066e 1678 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1679 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1680 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1681
09a0c3f1
OH		 1682 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1683 &guest_hv_clock, sizeof(guest_hv_clock))))
1684 return 0;
1685
5dca0d91
RK		 1686 /* This VCPU is paused, but it's legal for a guest to read another
1687 * VCPU's kvmclock, so we really have to follow the specification where
1688 * it says that version is odd if data is being modified, and even after
1689 * it is consistent.
1690 *
1691 * Version field updates must be kept separate. This is because
1692 * kvm_write_guest_cached might use a "rep movs" instruction, and
1693 * writes within a string instruction are weakly ordered. So there
1694 * are three writes overall.
1695 *
1696 * As a small optimization, only write the version field in the first
1697 * and third write. The vcpu->pv_time cache is still valid, because the
1698 * version field is the first in the struct.
18068523 1699 */
5dca0d91
RK		 1700 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1701
1702 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1703 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1704 &vcpu->hv_clock,
1705 sizeof(vcpu->hv_clock.version));
1706
1707 smp_wmb();
78c0337a
MT		 1708
1709 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1710 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1711
1712 if (vcpu->pvclock_set_guest_stopped_request) {
1713 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1714 vcpu->pvclock_set_guest_stopped_request = false;
1715 }
1716
d828199e
MT		 1717 /* If the host uses TSC clocksource, then it is stable */
1718 if (use_master_clock)
1719 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1720
78c0337a
MT		 1721 vcpu->hv_clock.flags = pvclock_flags;
1722
ce1a5e60
DM		 1723 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1724
0b79459b
AH		 1725 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1726 &vcpu->hv_clock,
1727 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1728
1729 smp_wmb();
1730
1731 vcpu->hv_clock.version++;
1732 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1733 &vcpu->hv_clock,
1734 sizeof(vcpu->hv_clock.version));
8cfdc000 1735 return 0;
c8076604
GH		 1736}
1737
0061d53d
MT		 1738/*
1739 * kvmclock updates which are isolated to a given vcpu, such as
1740 * vcpu->cpu migration, should not allow system_timestamp from
1741 * the rest of the vcpus to remain static. Otherwise ntp frequency
1742 * correction applies to one vcpu's system_timestamp but not
1743 * the others.
1744 *
1745 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1746 * We need to rate-limit these requests though, as they can
1747 * considerably slow guests that have a large number of vcpus.
1748 * The time for a remote vcpu to update its kvmclock is bound
1749 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1750 */
1751
7e44e449
AJ		 1752#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1753
1754static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1755{
1756 int i;
7e44e449
AJ		 1757 struct delayed_work *dwork = to_delayed_work(work);
1758 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1759 kvmclock_update_work);
1760 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1761 struct kvm_vcpu *vcpu;
1762
1763 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1764 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1765 kvm_vcpu_kick(vcpu);
1766 }
1767}
1768
7e44e449
AJ		 1769static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1770{
1771 struct kvm *kvm = v->kvm;
1772
105b21bb 1773 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1774 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1775 KVMCLOCK_UPDATE_DELAY);
1776}
1777
332967a3
AJ		 1778#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1779
1780static void kvmclock_sync_fn(struct work_struct *work)
1781{
1782 struct delayed_work *dwork = to_delayed_work(work);
1783 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1784 kvmclock_sync_work);
1785 struct kvm *kvm = container_of(ka, struct kvm, arch);
1786
630994b3
MT		 1787 if (!kvmclock_periodic_sync)
1788 return;
1789
332967a3
AJ		 1790 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1791 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1792 KVMCLOCK_SYNC_PERIOD);
1793}
1794
890ca9ae 1795static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1796{
890ca9ae
HY		 1797 u64 mcg_cap = vcpu->arch.mcg_cap;
1798 unsigned bank_num = mcg_cap & 0xff;
1799
15c4a640 1800 switch (msr) {
15c4a640 1801 case MSR_IA32_MCG_STATUS:
890ca9ae 1802 vcpu->arch.mcg_status = data;
15c4a640 1803 break;
c7ac679c 1804 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1805 if (!(mcg_cap & MCG_CTL_P))
1806 return 1;
1807 if (data != 0 && data != ~(u64)0)
1808 return -1;
1809 vcpu->arch.mcg_ctl = data;
1810 break;
1811 default:
1812 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1813 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1814 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1815 /* only 0 or all 1s can be written to IA32_MCi_CTL
1816 * some Linux kernels though clear bit 10 in bank 4 to
1817 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1818 * this to avoid an uncatched #GP in the guest
1819 */
890ca9ae 1820 if ((offset & 0x3) == 0 &&
114be429 1821 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1822 return -1;
1823 vcpu->arch.mce_banks[offset] = data;
1824 break;
1825 }
1826 return 1;
1827 }
1828 return 0;
1829}
1830
ffde22ac
ES		 1831static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1832{
1833 struct kvm *kvm = vcpu->kvm;
1834 int lm = is_long_mode(vcpu);
1835 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1836 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1837 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1838 : kvm->arch.xen_hvm_config.blob_size_32;
1839 u32 page_num = data & ~PAGE_MASK;
1840 u64 page_addr = data & PAGE_MASK;
1841 u8 *page;
1842 int r;
1843
1844 r = -E2BIG;
1845 if (page_num >= blob_size)
1846 goto out;
1847 r = -ENOMEM;
ff5c2c03
SL		 1848 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1849 if (IS_ERR(page)) {
1850 r = PTR_ERR(page);
ffde22ac 1851 goto out;
ff5c2c03 1852 }
54bf36aa 1853 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 1854 goto out_free;
1855 r = 0;
1856out_free:
1857 kfree(page);
1858out:
1859 return r;
1860}
1861
344d9588
GN		 1862static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1863{
1864 gpa_t gpa = data & ~0x3f;
1865
4a969980 1866 /* Bits 2:5 are reserved, Should be zero */
6adba527 1867 if (data & 0x3c)
344d9588
GN		 1868 return 1;
1869
1870 vcpu->arch.apf.msr_val = data;
1871
1872 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1873 kvm_clear_async_pf_completion_queue(vcpu);
1874 kvm_async_pf_hash_reset(vcpu);
1875 return 0;
1876 }
1877
8f964525
AH		 1878 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1879 sizeof(u32)))
344d9588
GN		 1880 return 1;
1881
6adba527 1882 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1883 kvm_async_pf_wakeup_all(vcpu);
1884 return 0;
1885}
1886
12f9a48f
GC		 1887static void kvmclock_reset(struct kvm_vcpu *vcpu)
1888{
0b79459b 1889 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1890}
1891
c9aaa895
GC		 1892static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1893{
1894 u64 delta;
1895
1896 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1897 return;
1898
1899 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1900 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1901 vcpu->arch.st.accum_steal = delta;
1902}
1903
1904static void record_steal_time(struct kvm_vcpu *vcpu)
1905{
7cae2bed
MT		 1906 accumulate_steal_time(vcpu);
1907
c9aaa895
GC		 1908 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1909 return;
1910
1911 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1912 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1913 return;
1914
1915 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1916 vcpu->arch.st.steal.version += 2;
1917 vcpu->arch.st.accum_steal = 0;
1918
1919 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1920 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1921}
1922
8fe8ab46 1923int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 1924{
5753785f 1925 bool pr = false;
8fe8ab46
WA		 1926 u32 msr = msr_info->index;
1927 u64 data = msr_info->data;
5753785f 1928
15c4a640 1929 switch (msr) {
2e32b719
BP		 1930 case MSR_AMD64_NB_CFG:
1931 case MSR_IA32_UCODE_REV:
1932 case MSR_IA32_UCODE_WRITE:
1933 case MSR_VM_HSAVE_PA:
1934 case MSR_AMD64_PATCH_LOADER:
1935 case MSR_AMD64_BU_CFG2:
1936 break;
1937
15c4a640 1938 case MSR_EFER:
b69e8cae 1939 return set_efer(vcpu, data);
8f1589d9
AP		 1940 case MSR_K7_HWCR:
1941 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1942 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1943 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 1944 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 1945 if (data != 0) {
a737f256
CD		 1946 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1947 data);
8f1589d9
AP		 1948 return 1;
1949 }
15c4a640 1950 break;
f7c6d140
AP		 1951 case MSR_FAM10H_MMIO_CONF_BASE:
1952 if (data != 0) {
a737f256
CD		 1953 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1954 "0x%llx\n", data);
f7c6d140
AP		 1955 return 1;
1956 }
15c4a640 1957 break;
b5e2fec0
AG		 1958 case MSR_IA32_DEBUGCTLMSR:
1959 if (!data) {
1960 /* We support the non-activated case already */
1961 break;
1962 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1963 /* Values other than LBR and BTF are vendor-specific,
1964 thus reserved and should throw a #GP */
1965 return 1;
1966 }
a737f256
CD		 1967 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1968 __func__, data);
b5e2fec0 1969 break;
9ba075a6 1970 case 0x200 ... 0x2ff:
ff53604b 1971 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 1972 case MSR_IA32_APICBASE:
58cb628d 1973 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 1974 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1975 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1976 case MSR_IA32_TSCDEADLINE:
1977 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1978 break;
ba904635
WA		 1979 case MSR_IA32_TSC_ADJUST:
1980 if (guest_cpuid_has_tsc_adjust(vcpu)) {
1981 if (!msr_info->host_initiated) {
d913b904 1982 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 1983 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 1984 }
1985 vcpu->arch.ia32_tsc_adjust_msr = data;
1986 }
1987 break;
15c4a640 1988 case MSR_IA32_MISC_ENABLE:
ad312c7c 1989 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1990 break;
64d60670
PB		 1991 case MSR_IA32_SMBASE:
1992 if (!msr_info->host_initiated)
1993 return 1;
1994 vcpu->arch.smbase = data;
1995 break;
11c6bffa 1996 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1997 case MSR_KVM_WALL_CLOCK:
1998 vcpu->kvm->arch.wall_clock = data;
1999 kvm_write_wall_clock(vcpu->kvm, data);
2000 break;
11c6bffa 2001 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2002 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2003 u64 gpa_offset;
54750f2c
MT		 2004 struct kvm_arch *ka = &vcpu->kvm->arch;
2005
12f9a48f 2006 kvmclock_reset(vcpu);
18068523 2007
54750f2c
MT		 2008 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2009 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2010
2011 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2012 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2013 &vcpu->requests);
2014
2015 ka->boot_vcpu_runs_old_kvmclock = tmp;
2016 }
2017
18068523 2018 vcpu->arch.time = data;
0061d53d 2019 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2020
2021 /* we verify if the enable bit is set... */
2022 if (!(data & 1))
2023 break;
2024
0b79459b 2025 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2026
0b79459b 2027 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2028 &vcpu->arch.pv_time, data & ~1ULL,
2029 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2030 vcpu->arch.pv_time_enabled = false;
2031 else
2032 vcpu->arch.pv_time_enabled = true;
32cad84f 2033
18068523
GOC		 2034 break;
2035 }
344d9588
GN		 2036 case MSR_KVM_ASYNC_PF_EN:
2037 if (kvm_pv_enable_async_pf(vcpu, data))
2038 return 1;
2039 break;
c9aaa895
GC		 2040 case MSR_KVM_STEAL_TIME:
2041
2042 if (unlikely(!sched_info_on()))
2043 return 1;
2044
2045 if (data & KVM_STEAL_RESERVED_MASK)
2046 return 1;
2047
2048 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2049 data & KVM_STEAL_VALID_BITS,
2050 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2051 return 1;
2052
2053 vcpu->arch.st.msr_val = data;
2054
2055 if (!(data & KVM_MSR_ENABLED))
2056 break;
2057
c9aaa895
GC		 2058 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2059
2060 break;
ae7a2a3f
MT		 2061 case MSR_KVM_PV_EOI_EN:
2062 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2063 return 1;
2064 break;
c9aaa895 2065
890ca9ae
HY		 2066 case MSR_IA32_MCG_CTL:
2067 case MSR_IA32_MCG_STATUS:
81760dcc 2068 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2069 return set_msr_mce(vcpu, msr, data);
71db6023 2070
6912ac32
WH		 2071 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2072 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2073 pr = true; /* fall through */
2074 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2075 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2076 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2077 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2078
2079 if (pr || data != 0)
a737f256
CD		 2080 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2081 "0x%x data 0x%llx\n", msr, data);
5753785f 2082 break;
84e0cefa
JS		 2083 case MSR_K7_CLK_CTL:
2084 /*
2085 * Ignore all writes to this no longer documented MSR.
2086 * Writes are only relevant for old K7 processors,
2087 * all pre-dating SVM, but a recommended workaround from
4a969980 2088 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2089 * affected processor models on the command line, hence
2090 * the need to ignore the workaround.
2091 */
2092 break;
55cd8e5a 2093 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2094 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2095 case HV_X64_MSR_CRASH_CTL:
2096 return kvm_hv_set_msr_common(vcpu, msr, data,
2097 msr_info->host_initiated);
91c9c3ed 2098 case MSR_IA32_BBL_CR_CTL3:
2099 /* Drop writes to this legacy MSR -- see rdmsr
2100 * counterpart for further detail.
2101 */
a737f256 2102 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2103 break;
2b036c6b
BO		 2104 case MSR_AMD64_OSVW_ID_LENGTH:
2105 if (!guest_cpuid_has_osvw(vcpu))
2106 return 1;
2107 vcpu->arch.osvw.length = data;
2108 break;
2109 case MSR_AMD64_OSVW_STATUS:
2110 if (!guest_cpuid_has_osvw(vcpu))
2111 return 1;
2112 vcpu->arch.osvw.status = data;
2113 break;
15c4a640 2114 default:
ffde22ac
ES		 2115 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2116 return xen_hvm_config(vcpu, data);
c6702c9d 2117 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2118 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2119 if (!ignore_msrs) {
a737f256
CD		 2120 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2121 msr, data);
ed85c068
AP		 2122 return 1;
2123 } else {
a737f256
CD		 2124 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2125 msr, data);
ed85c068
AP		 2126 break;
2127 }
15c4a640
CO		 2128 }
2129 return 0;
2130}
2131EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2132
2133
2134/*
2135 * Reads an msr value (of 'msr_index') into 'pdata'.
2136 * Returns 0 on success, non-0 otherwise.
2137 * Assumes vcpu_load() was already called.
2138 */
609e36d3 2139int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2140{
609e36d3 2141 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2142}
ff651cb6 2143EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2144
890ca9ae 2145static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2146{
2147 u64 data;
890ca9ae
HY		 2148 u64 mcg_cap = vcpu->arch.mcg_cap;
2149 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2150
2151 switch (msr) {
15c4a640
CO		 2152 case MSR_IA32_P5_MC_ADDR:
2153 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2154 data = 0;
2155 break;
15c4a640 2156 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2157 data = vcpu->arch.mcg_cap;
2158 break;
c7ac679c 2159 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2160 if (!(mcg_cap & MCG_CTL_P))
2161 return 1;
2162 data = vcpu->arch.mcg_ctl;
2163 break;
2164 case MSR_IA32_MCG_STATUS:
2165 data = vcpu->arch.mcg_status;
2166 break;
2167 default:
2168 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2169 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2170 u32 offset = msr - MSR_IA32_MC0_CTL;
2171 data = vcpu->arch.mce_banks[offset];
2172 break;
2173 }
2174 return 1;
2175 }
2176 *pdata = data;
2177 return 0;
2178}
2179
609e36d3 2180int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2181{
609e36d3 2182 switch (msr_info->index) {
890ca9ae 2183 case MSR_IA32_PLATFORM_ID:
15c4a640 2184 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2185 case MSR_IA32_DEBUGCTLMSR:
2186 case MSR_IA32_LASTBRANCHFROMIP:
2187 case MSR_IA32_LASTBRANCHTOIP:
2188 case MSR_IA32_LASTINTFROMIP:
2189 case MSR_IA32_LASTINTTOIP:
60af2ecd 2190 case MSR_K8_SYSCFG:
3afb1121
PB		 2191 case MSR_K8_TSEG_ADDR:
2192 case MSR_K8_TSEG_MASK:
60af2ecd 2193 case MSR_K7_HWCR:
61a6bd67 2194 case MSR_VM_HSAVE_PA:
1fdbd48c 2195 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2196 case MSR_AMD64_NB_CFG:
f7c6d140 2197 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2198 case MSR_AMD64_BU_CFG2:
609e36d3 2199 msr_info->data = 0;
15c4a640 2200 break;
6912ac32
WH		 2201 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2202 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2203 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2204 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2205 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2206 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2207 msr_info->data = 0;
5753785f 2208 break;
742bc670 2209 case MSR_IA32_UCODE_REV:
609e36d3 2210 msr_info->data = 0x100000000ULL;
742bc670 2211 break;
9ba075a6 2212 case MSR_MTRRcap:
9ba075a6 2213 case 0x200 ... 0x2ff:
ff53604b 2214 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2215 case 0xcd: /* fsb frequency */
609e36d3 2216 msr_info->data = 3;
15c4a640 2217 break;
7b914098
JS		 2218 /*
2219 * MSR_EBC_FREQUENCY_ID
2220 * Conservative value valid for even the basic CPU models.
2221 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2222 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2223 * and 266MHz for model 3, or 4. Set Core Clock
2224 * Frequency to System Bus Frequency Ratio to 1 (bits
2225 * 31:24) even though these are only valid for CPU
2226 * models > 2, however guests may end up dividing or
2227 * multiplying by zero otherwise.
2228 */
2229 case MSR_EBC_FREQUENCY_ID:
609e36d3 2230 msr_info->data = 1 << 24;
7b914098 2231 break;
15c4a640 2232 case MSR_IA32_APICBASE:
609e36d3 2233 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2234 break;
0105d1a5 2235 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2236 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2237 break;
a3e06bbe 2238 case MSR_IA32_TSCDEADLINE:
609e36d3 2239 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2240 break;
ba904635 2241 case MSR_IA32_TSC_ADJUST:
609e36d3 2242 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2243 break;
15c4a640 2244 case MSR_IA32_MISC_ENABLE:
609e36d3 2245 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2246 break;
64d60670
PB		 2247 case MSR_IA32_SMBASE:
2248 if (!msr_info->host_initiated)
2249 return 1;
2250 msr_info->data = vcpu->arch.smbase;
15c4a640 2251 break;
847f0ad8
AG		 2252 case MSR_IA32_PERF_STATUS:
2253 /* TSC increment by tick */
609e36d3 2254 msr_info->data = 1000ULL;
847f0ad8 2255 /* CPU multiplier */
b0996ae4 2256 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2257 break;
15c4a640 2258 case MSR_EFER:
609e36d3 2259 msr_info->data = vcpu->arch.efer;
15c4a640 2260 break;
18068523 2261 case MSR_KVM_WALL_CLOCK:
11c6bffa 2262 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2263 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2264 break;
2265 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2266 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2267 msr_info->data = vcpu->arch.time;
18068523 2268 break;
344d9588 2269 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2270 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2271 break;
c9aaa895 2272 case MSR_KVM_STEAL_TIME:
609e36d3 2273 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2274 break;
1d92128f 2275 case MSR_KVM_PV_EOI_EN:
609e36d3 2276 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2277 break;
890ca9ae
HY		 2278 case MSR_IA32_P5_MC_ADDR:
2279 case MSR_IA32_P5_MC_TYPE:
2280 case MSR_IA32_MCG_CAP:
2281 case MSR_IA32_MCG_CTL:
2282 case MSR_IA32_MCG_STATUS:
81760dcc 2283 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2284 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2285 case MSR_K7_CLK_CTL:
2286 /*
2287 * Provide expected ramp-up count for K7. All other
2288 * are set to zero, indicating minimum divisors for
2289 * every field.
2290 *
2291 * This prevents guest kernels on AMD host with CPU
2292 * type 6, model 8 and higher from exploding due to
2293 * the rdmsr failing.
2294 */
609e36d3 2295 msr_info->data = 0x20000000;
84e0cefa 2296 break;
55cd8e5a 2297 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2298 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2299 case HV_X64_MSR_CRASH_CTL:
e83d5887
AS		 2300 return kvm_hv_get_msr_common(vcpu,
2301 msr_info->index, &msr_info->data);
55cd8e5a 2302 break;
91c9c3ed 2303 case MSR_IA32_BBL_CR_CTL3:
2304 /* This legacy MSR exists but isn't fully documented in current
2305 * silicon. It is however accessed by winxp in very narrow
2306 * scenarios where it sets bit #19, itself documented as
2307 * a "reserved" bit. Best effort attempt to source coherent
2308 * read data here should the balance of the register be
2309 * interpreted by the guest:
2310 *
2311 * L2 cache control register 3: 64GB range, 256KB size,
2312 * enabled, latency 0x1, configured
2313 */
609e36d3 2314 msr_info->data = 0xbe702111;
91c9c3ed 2315 break;
2b036c6b
BO		 2316 case MSR_AMD64_OSVW_ID_LENGTH:
2317 if (!guest_cpuid_has_osvw(vcpu))
2318 return 1;
609e36d3 2319 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2320 break;
2321 case MSR_AMD64_OSVW_STATUS:
2322 if (!guest_cpuid_has_osvw(vcpu))
2323 return 1;
609e36d3 2324 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2325 break;
15c4a640 2326 default:
c6702c9d 2327 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2328 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2329 if (!ignore_msrs) {
609e36d3 2330 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2331 return 1;
2332 } else {
609e36d3
PB		 2333 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2334 msr_info->data = 0;
ed85c068
AP		 2335 }
2336 break;
15c4a640 2337 }
15c4a640
CO		 2338 return 0;
2339}
2340EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2341
313a3dc7
CO		 2342/*
2343 * Read or write a bunch of msrs. All parameters are kernel addresses.
2344 *
2345 * @return number of msrs set successfully.
2346 */
2347static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2348 struct kvm_msr_entry *entries,
2349 int (*do_msr)(struct kvm_vcpu *vcpu,
2350 unsigned index, u64 *data))
2351{
f656ce01 2352 int i, idx;
313a3dc7 2353
f656ce01 2354 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2355 for (i = 0; i < msrs->nmsrs; ++i)
2356 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2357 break;
f656ce01 2358 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2359
313a3dc7
CO		 2360 return i;
2361}
2362
2363/*
2364 * Read or write a bunch of msrs. Parameters are user addresses.
2365 *
2366 * @return number of msrs set successfully.
2367 */
2368static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2369 int (*do_msr)(struct kvm_vcpu *vcpu,
2370 unsigned index, u64 *data),
2371 int writeback)
2372{
2373 struct kvm_msrs msrs;
2374 struct kvm_msr_entry *entries;
2375 int r, n;
2376 unsigned size;
2377
2378 r = -EFAULT;
2379 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2380 goto out;
2381
2382 r = -E2BIG;
2383 if (msrs.nmsrs >= MAX_IO_MSRS)
2384 goto out;
2385
313a3dc7 2386 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2387 entries = memdup_user(user_msrs->entries, size);
2388 if (IS_ERR(entries)) {
2389 r = PTR_ERR(entries);
313a3dc7 2390 goto out;
ff5c2c03 2391 }
313a3dc7
CO		 2392
2393 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2394 if (r < 0)
2395 goto out_free;
2396
2397 r = -EFAULT;
2398 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2399 goto out_free;
2400
2401 r = n;
2402
2403out_free:
7a73c028 2404 kfree(entries);
313a3dc7
CO		 2405out:
2406 return r;
2407}
2408
784aa3d7 2409int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2410{
2411 int r;
2412
2413 switch (ext) {
2414 case KVM_CAP_IRQCHIP:
2415 case KVM_CAP_HLT:
2416 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2417 case KVM_CAP_SET_TSS_ADDR:
07716717 2418 case KVM_CAP_EXT_CPUID:
9c15bb1d 2419 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2420 case KVM_CAP_CLOCKSOURCE:
7837699f 2421 case KVM_CAP_PIT:
a28e4f5a 2422 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2423 case KVM_CAP_MP_STATE:
ed848624 2424 case KVM_CAP_SYNC_MMU:
a355c85c 2425 case KVM_CAP_USER_NMI:
52d939a0 2426 case KVM_CAP_REINJECT_CONTROL:
4925663a 2427 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2428 case KVM_CAP_IOEVENTFD:
f848a5a8 2429 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2430 case KVM_CAP_PIT2:
e9f42757 2431 case KVM_CAP_PIT_STATE2:
b927a3ce 2432 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2433 case KVM_CAP_XEN_HVM:
afbcf7ab 2434 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2435 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2436 case KVM_CAP_HYPERV:
10388a07 2437 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2438 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2439 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2440 case KVM_CAP_DEBUGREGS:
d2be1651 2441 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2442 case KVM_CAP_XSAVE:
344d9588 2443 case KVM_CAP_ASYNC_PF:
92a1f12d 2444 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2445 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2446 case KVM_CAP_READONLY_MEM:
5f66b620 2447 case KVM_CAP_HYPERV_TIME:
100943c5 2448 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2449 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2450 case KVM_CAP_ENABLE_CAP_VM:
2451 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2452 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2453 case KVM_CAP_SPLIT_IRQCHIP:
2a5bab10
AW		 2454#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2455 case KVM_CAP_ASSIGN_DEV_IRQ:
2456 case KVM_CAP_PCI_2_3:
2457#endif
018d00d2
ZX		 2458 r = 1;
2459 break;
6d396b55
PB		 2460 case KVM_CAP_X86_SMM:
2461 /* SMBASE is usually relocated above 1M on modern chipsets,
2462 * and SMM handlers might indeed rely on 4G segment limits,
2463 * so do not report SMM to be available if real mode is
2464 * emulated via vm86 mode. Still, do not go to great lengths
2465 * to avoid userspace's usage of the feature, because it is a
2466 * fringe case that is not enabled except via specific settings
2467 * of the module parameters.
2468 */
2469 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2470 break;
542472b5
LV		 2471 case KVM_CAP_COALESCED_MMIO:
2472 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2473 break;
774ead3a
AK		 2474 case KVM_CAP_VAPIC:
2475 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2476 break;
f725230a 2477 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2478 r = KVM_SOFT_MAX_VCPUS;
2479 break;
2480 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2481 r = KVM_MAX_VCPUS;
2482 break;
a988b910 2483 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2484 r = KVM_USER_MEM_SLOTS;
a988b910 2485 break;
a68a6a72
MT		 2486 case KVM_CAP_PV_MMU: /* obsolete */
2487 r = 0;
2f333bcb 2488 break;
4cee4b72 2489#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2490 case KVM_CAP_IOMMU:
a1b60c1c 2491 r = iommu_present(&pci_bus_type);
62c476c7 2492 break;
4cee4b72 2493#endif
890ca9ae
HY		 2494 case KVM_CAP_MCE:
2495 r = KVM_MAX_MCE_BANKS;
2496 break;
2d5b5a66
SY		 2497 case KVM_CAP_XCRS:
2498 r = cpu_has_xsave;
2499 break;
92a1f12d
JR		 2500 case KVM_CAP_TSC_CONTROL:
2501 r = kvm_has_tsc_control;
2502 break;
018d00d2
ZX		 2503 default:
2504 r = 0;
2505 break;
2506 }
2507 return r;
2508
2509}
2510
043405e1
CO		 2511long kvm_arch_dev_ioctl(struct file *filp,
2512 unsigned int ioctl, unsigned long arg)
2513{
2514 void __user *argp = (void __user *)arg;
2515 long r;
2516
2517 switch (ioctl) {
2518 case KVM_GET_MSR_INDEX_LIST: {
2519 struct kvm_msr_list __user *user_msr_list = argp;
2520 struct kvm_msr_list msr_list;
2521 unsigned n;
2522
2523 r = -EFAULT;
2524 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2525 goto out;
2526 n = msr_list.nmsrs;
62ef68bb 2527 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2528 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2529 goto out;
2530 r = -E2BIG;
e125e7b6 2531 if (n < msr_list.nmsrs)
043405e1
CO		 2532 goto out;
2533 r = -EFAULT;
2534 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2535 num_msrs_to_save * sizeof(u32)))
2536 goto out;
e125e7b6 2537 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2538 &emulated_msrs,
62ef68bb 2539 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2540 goto out;
2541 r = 0;
2542 break;
2543 }
9c15bb1d
BP		 2544 case KVM_GET_SUPPORTED_CPUID:
2545 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2546 struct kvm_cpuid2 __user *cpuid_arg = argp;
2547 struct kvm_cpuid2 cpuid;
2548
2549 r = -EFAULT;
2550 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2551 goto out;
9c15bb1d
BP		 2552
2553 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2554 ioctl);
674eea0f
AK		 2555 if (r)
2556 goto out;
2557
2558 r = -EFAULT;
2559 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2560 goto out;
2561 r = 0;
2562 break;
2563 }
890ca9ae
HY		 2564 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2565 u64 mce_cap;
2566
2567 mce_cap = KVM_MCE_CAP_SUPPORTED;
2568 r = -EFAULT;
2569 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2570 goto out;
2571 r = 0;
2572 break;
2573 }
043405e1
CO		 2574 default:
2575 r = -EINVAL;
2576 }
2577out:
2578 return r;
2579}
2580
f5f48ee1
SY		 2581static void wbinvd_ipi(void *garbage)
2582{
2583 wbinvd();
2584}
2585
2586static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2587{
e0f0bbc5 2588 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2589}
2590
313a3dc7
CO		 2591void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2592{
f5f48ee1
SY		 2593 /* Address WBINVD may be executed by guest */
2594 if (need_emulate_wbinvd(vcpu)) {
2595 if (kvm_x86_ops->has_wbinvd_exit())
2596 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2597 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2598 smp_call_function_single(vcpu->cpu,
2599 wbinvd_ipi, NULL, 1);
2600 }
2601
313a3dc7 2602 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2603
0dd6a6ed
ZA		 2604 /* Apply any externally detected TSC adjustments (due to suspend) */
2605 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2606 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2607 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2608 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2609 }
8f6055cb 2610
48434c20 2611 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2612 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2613 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2614 if (tsc_delta < 0)
2615 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2616 if (check_tsc_unstable()) {
b183aa58
ZA		 2617 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2618 vcpu->arch.last_guest_tsc);
2619 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2620 vcpu->arch.tsc_catchup = 1;
c285545f 2621 }
d98d07ca
MT		 2622 /*
2623 * On a host with synchronized TSC, there is no need to update
2624 * kvmclock on vcpu->cpu migration
2625 */
2626 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2627 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2628 if (vcpu->cpu != cpu)
2629 kvm_migrate_timers(vcpu);
e48672fa 2630 vcpu->cpu = cpu;
6b7d7e76 2631 }
c9aaa895 2632
c9aaa895 2633 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2634}
2635
2636void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2637{
02daab21 2638 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2639 kvm_put_guest_fpu(vcpu);
4ea1636b 2640 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2641}
2642
313a3dc7
CO		 2643static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2644 struct kvm_lapic_state *s)
2645{
5a71785d 2646 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2647 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2648
2649 return 0;
2650}
2651
2652static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2653 struct kvm_lapic_state *s)
2654{
64eb0620 2655 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2656 update_cr8_intercept(vcpu);
313a3dc7
CO		 2657
2658 return 0;
2659}
2660
f77bc6a4
ZX		 2661static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2662 struct kvm_interrupt *irq)
2663{
02cdb50f 2664 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2665 return -EINVAL;
1c1a9ce9
SR		 2666
2667 if (!irqchip_in_kernel(vcpu->kvm)) {
2668 kvm_queue_interrupt(vcpu, irq->irq, false);
2669 kvm_make_request(KVM_REQ_EVENT, vcpu);
2670 return 0;
2671 }
2672
2673 /*
2674 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2675 * fail for in-kernel 8259.
2676 */
2677 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2678 return -ENXIO;
f77bc6a4 2679
1c1a9ce9
SR		 2680 if (vcpu->arch.pending_external_vector != -1)
2681 return -EEXIST;
f77bc6a4 2682
1c1a9ce9 2683 vcpu->arch.pending_external_vector = irq->irq;
f77bc6a4
ZX		 2684 return 0;
2685}
2686
c4abb7c9
JK		 2687static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2688{
c4abb7c9 2689 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2690
2691 return 0;
2692}
2693
f077825a
PB		 2694static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2695{
64d60670
PB		 2696 kvm_make_request(KVM_REQ_SMI, vcpu);
2697
f077825a
PB		 2698 return 0;
2699}
2700
b209749f
AK		 2701static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2702 struct kvm_tpr_access_ctl *tac)
2703{
2704 if (tac->flags)
2705 return -EINVAL;
2706 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2707 return 0;
2708}
2709
890ca9ae
HY		 2710static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2711 u64 mcg_cap)
2712{
2713 int r;
2714 unsigned bank_num = mcg_cap & 0xff, bank;
2715
2716 r = -EINVAL;
a9e38c3e 2717 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2718 goto out;
2719 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2720 goto out;
2721 r = 0;
2722 vcpu->arch.mcg_cap = mcg_cap;
2723 /* Init IA32_MCG_CTL to all 1s */
2724 if (mcg_cap & MCG_CTL_P)
2725 vcpu->arch.mcg_ctl = ~(u64)0;
2726 /* Init IA32_MCi_CTL to all 1s */
2727 for (bank = 0; bank < bank_num; bank++)
2728 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2729out:
2730 return r;
2731}
2732
2733static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2734 struct kvm_x86_mce *mce)
2735{
2736 u64 mcg_cap = vcpu->arch.mcg_cap;
2737 unsigned bank_num = mcg_cap & 0xff;
2738 u64 *banks = vcpu->arch.mce_banks;
2739
2740 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2741 return -EINVAL;
2742 /*
2743 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2744 * reporting is disabled
2745 */
2746 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2747 vcpu->arch.mcg_ctl != ~(u64)0)
2748 return 0;
2749 banks += 4 * mce->bank;
2750 /*
2751 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2752 * reporting is disabled for the bank
2753 */
2754 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2755 return 0;
2756 if (mce->status & MCI_STATUS_UC) {
2757 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2758 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2759 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2760 return 0;
2761 }
2762 if (banks[1] & MCI_STATUS_VAL)
2763 mce->status |= MCI_STATUS_OVER;
2764 banks[2] = mce->addr;
2765 banks[3] = mce->misc;
2766 vcpu->arch.mcg_status = mce->mcg_status;
2767 banks[1] = mce->status;
2768 kvm_queue_exception(vcpu, MC_VECTOR);
2769 } else if (!(banks[1] & MCI_STATUS_VAL)
2770 || !(banks[1] & MCI_STATUS_UC)) {
2771 if (banks[1] & MCI_STATUS_VAL)
2772 mce->status |= MCI_STATUS_OVER;
2773 banks[2] = mce->addr;
2774 banks[3] = mce->misc;
2775 banks[1] = mce->status;
2776 } else
2777 banks[1] |= MCI_STATUS_OVER;
2778 return 0;
2779}
2780
3cfc3092
JK		 2781static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2782 struct kvm_vcpu_events *events)
2783{
7460fb4a 2784 process_nmi(vcpu);
03b82a30
JK		 2785 events->exception.injected =
2786 vcpu->arch.exception.pending &&
2787 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2788 events->exception.nr = vcpu->arch.exception.nr;
2789 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2790 events->exception.pad = 0;
3cfc3092
JK		 2791 events->exception.error_code = vcpu->arch.exception.error_code;
2792
03b82a30
JK		 2793 events->interrupt.injected =
2794 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2795 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2796 events->interrupt.soft = 0;
37ccdcbe 2797 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2798
2799 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2800 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2801 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2802 events->nmi.pad = 0;
3cfc3092 2803
66450a21 2804 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2805
f077825a
PB		 2806 events->smi.smm = is_smm(vcpu);
2807 events->smi.pending = vcpu->arch.smi_pending;
2808 events->smi.smm_inside_nmi =
2809 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2810 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2811
dab4b911 2812 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 2813 | KVM_VCPUEVENT_VALID_SHADOW
2814 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 2815 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2816}
2817
2818static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2819 struct kvm_vcpu_events *events)
2820{
dab4b911 2821 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2822 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 2823 | KVM_VCPUEVENT_VALID_SHADOW
2824 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 2825 return -EINVAL;
2826
7460fb4a 2827 process_nmi(vcpu);
3cfc3092
JK		 2828 vcpu->arch.exception.pending = events->exception.injected;
2829 vcpu->arch.exception.nr = events->exception.nr;
2830 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2831 vcpu->arch.exception.error_code = events->exception.error_code;
2832
2833 vcpu->arch.interrupt.pending = events->interrupt.injected;
2834 vcpu->arch.interrupt.nr = events->interrupt.nr;
2835 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2836 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2837 kvm_x86_ops->set_interrupt_shadow(vcpu,
2838 events->interrupt.shadow);
3cfc3092
JK		 2839
2840 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2841 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2842 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2843 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2844
66450a21
JK		 2845 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2846 kvm_vcpu_has_lapic(vcpu))
2847 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2848
f077825a
PB		 2849 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2850 if (events->smi.smm)
2851 vcpu->arch.hflags |= HF_SMM_MASK;
2852 else
2853 vcpu->arch.hflags &= ~HF_SMM_MASK;
2854 vcpu->arch.smi_pending = events->smi.pending;
2855 if (events->smi.smm_inside_nmi)
2856 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
2857 else
2858 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
2859 if (kvm_vcpu_has_lapic(vcpu)) {
2860 if (events->smi.latched_init)
2861 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2862 else
2863 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2864 }
2865 }
2866
3842d135
AK		 2867 kvm_make_request(KVM_REQ_EVENT, vcpu);
2868
3cfc3092
JK		 2869 return 0;
2870}
2871
a1efbe77
JK		 2872static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2873 struct kvm_debugregs *dbgregs)
2874{
73aaf249
JK		 2875 unsigned long val;
2876
a1efbe77 2877 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 2878 kvm_get_dr(vcpu, 6, &val);
73aaf249 2879 dbgregs->dr6 = val;
a1efbe77
JK		 2880 dbgregs->dr7 = vcpu->arch.dr7;
2881 dbgregs->flags = 0;
97e69aa6 2882 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2883}
2884
2885static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2886 struct kvm_debugregs *dbgregs)
2887{
2888 if (dbgregs->flags)
2889 return -EINVAL;
2890
a1efbe77 2891 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 2892 kvm_update_dr0123(vcpu);
a1efbe77 2893 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 2894 kvm_update_dr6(vcpu);
a1efbe77 2895 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 2896 kvm_update_dr7(vcpu);
a1efbe77 2897
a1efbe77
JK		 2898 return 0;
2899}
2900
df1daba7
PB		 2901#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
2902
2903static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
2904{
c47ada30 2905 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 2906 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 2907 u64 valid;
2908
2909 /*
2910 * Copy legacy XSAVE area, to avoid complications with CPUID
2911 * leaves 0 and 1 in the loop below.
2912 */
2913 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
2914
2915 /* Set XSTATE_BV */
2916 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
2917
2918 /*
2919 * Copy each region from the possibly compacted offset to the
2920 * non-compacted offset.
2921 */
2922 valid = xstate_bv & ~XSTATE_FPSSE;
2923 while (valid) {
2924 u64 feature = valid & -valid;
2925 int index = fls64(feature) - 1;
2926 void *src = get_xsave_addr(xsave, feature);
2927
2928 if (src) {
2929 u32 size, offset, ecx, edx;
2930 cpuid_count(XSTATE_CPUID, index,
2931 &size, &offset, &ecx, &edx);
2932 memcpy(dest + offset, src, size);
2933 }
2934
2935 valid -= feature;
2936 }
2937}
2938
2939static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
2940{
c47ada30 2941 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 2942 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
2943 u64 valid;
2944
2945 /*
2946 * Copy legacy XSAVE area, to avoid complications with CPUID
2947 * leaves 0 and 1 in the loop below.
2948 */
2949 memcpy(xsave, src, XSAVE_HDR_OFFSET);
2950
2951 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 2952 xsave->header.xfeatures = xstate_bv;
df1daba7 2953 if (cpu_has_xsaves)
3a54450b 2954 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 2955
2956 /*
2957 * Copy each region from the non-compacted offset to the
2958 * possibly compacted offset.
2959 */
2960 valid = xstate_bv & ~XSTATE_FPSSE;
2961 while (valid) {
2962 u64 feature = valid & -valid;
2963 int index = fls64(feature) - 1;
2964 void *dest = get_xsave_addr(xsave, feature);
2965
2966 if (dest) {
2967 u32 size, offset, ecx, edx;
2968 cpuid_count(XSTATE_CPUID, index,
2969 &size, &offset, &ecx, &edx);
2970 memcpy(dest, src + offset, size);
ee4100da 2971 }
df1daba7
PB		 2972
2973 valid -= feature;
2974 }
2975}
2976
2d5b5a66
SY		 2977static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2978 struct kvm_xsave *guest_xsave)
2979{
4344ee98 2980 if (cpu_has_xsave) {
df1daba7
PB		 2981 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
2982 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 2983 } else {
2d5b5a66 2984 memcpy(guest_xsave->region,
7366ed77 2985 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 2986 sizeof(struct fxregs_state));
2d5b5a66
SY		 2987 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2988 XSTATE_FPSSE;
2989 }
2990}
2991
2992static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2993 struct kvm_xsave *guest_xsave)
2994{
2995 u64 xstate_bv =
2996 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2997
d7876f1b
PB		 2998 if (cpu_has_xsave) {
2999 /*
3000 * Here we allow setting states that are not present in
3001 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3002 * with old userspace.
3003 */
4ff41732 3004 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3005 return -EINVAL;
df1daba7 3006 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3007 } else {
2d5b5a66
SY		 3008 if (xstate_bv & ~XSTATE_FPSSE)
3009 return -EINVAL;
7366ed77 3010 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3011 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3012 }
3013 return 0;
3014}
3015
3016static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3017 struct kvm_xcrs *guest_xcrs)
3018{
3019 if (!cpu_has_xsave) {
3020 guest_xcrs->nr_xcrs = 0;
3021 return;
3022 }
3023
3024 guest_xcrs->nr_xcrs = 1;
3025 guest_xcrs->flags = 0;
3026 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3027 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3028}
3029
3030static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3031 struct kvm_xcrs *guest_xcrs)
3032{
3033 int i, r = 0;
3034
3035 if (!cpu_has_xsave)
3036 return -EINVAL;
3037
3038 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3039 return -EINVAL;
3040
3041 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3042 /* Only support XCR0 currently */
c67a04cb 3043 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3044 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3045 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3046 break;
3047 }
3048 if (r)
3049 r = -EINVAL;
3050 return r;
3051}
3052
1c0b28c2
EM		 3053/*
3054 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3055 * stopped by the hypervisor. This function will be called from the host only.
3056 * EINVAL is returned when the host attempts to set the flag for a guest that
3057 * does not support pv clocks.
3058 */
3059static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3060{
0b79459b 3061 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3062 return -EINVAL;
51d59c6b 3063 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3064 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3065 return 0;
3066}
3067
313a3dc7
CO		 3068long kvm_arch_vcpu_ioctl(struct file *filp,
3069 unsigned int ioctl, unsigned long arg)
3070{
3071 struct kvm_vcpu *vcpu = filp->private_data;
3072 void __user *argp = (void __user *)arg;
3073 int r;
d1ac91d8
AK		 3074 union {
3075 struct kvm_lapic_state *lapic;
3076 struct kvm_xsave *xsave;
3077 struct kvm_xcrs *xcrs;
3078 void *buffer;
3079 } u;
3080
3081 u.buffer = NULL;
313a3dc7
CO		 3082 switch (ioctl) {
3083 case KVM_GET_LAPIC: {
2204ae3c
MT		 3084 r = -EINVAL;
3085 if (!vcpu->arch.apic)
3086 goto out;
d1ac91d8 3087 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3088
b772ff36 3089 r = -ENOMEM;
d1ac91d8 3090 if (!u.lapic)
b772ff36 3091 goto out;
d1ac91d8 3092 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3093 if (r)
3094 goto out;
3095 r = -EFAULT;
d1ac91d8 3096 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3097 goto out;
3098 r = 0;
3099 break;
3100 }
3101 case KVM_SET_LAPIC: {
2204ae3c
MT		 3102 r = -EINVAL;
3103 if (!vcpu->arch.apic)
3104 goto out;
ff5c2c03 3105 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3106 if (IS_ERR(u.lapic))
3107 return PTR_ERR(u.lapic);
ff5c2c03 3108
d1ac91d8 3109 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3110 break;
3111 }
f77bc6a4
ZX		 3112 case KVM_INTERRUPT: {
3113 struct kvm_interrupt irq;
3114
3115 r = -EFAULT;
3116 if (copy_from_user(&irq, argp, sizeof irq))
3117 goto out;
3118 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3119 break;
3120 }
c4abb7c9
JK		 3121 case KVM_NMI: {
3122 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3123 break;
3124 }
f077825a
PB		 3125 case KVM_SMI: {
3126 r = kvm_vcpu_ioctl_smi(vcpu);
3127 break;
3128 }
313a3dc7
CO		 3129 case KVM_SET_CPUID: {
3130 struct kvm_cpuid __user *cpuid_arg = argp;
3131 struct kvm_cpuid cpuid;
3132
3133 r = -EFAULT;
3134 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3135 goto out;
3136 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3137 break;
3138 }
07716717
DK		 3139 case KVM_SET_CPUID2: {
3140 struct kvm_cpuid2 __user *cpuid_arg = argp;
3141 struct kvm_cpuid2 cpuid;
3142
3143 r = -EFAULT;
3144 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3145 goto out;
3146 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3147 cpuid_arg->entries);
07716717
DK		 3148 break;
3149 }
3150 case KVM_GET_CPUID2: {
3151 struct kvm_cpuid2 __user *cpuid_arg = argp;
3152 struct kvm_cpuid2 cpuid;
3153
3154 r = -EFAULT;
3155 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3156 goto out;
3157 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3158 cpuid_arg->entries);
07716717
DK		 3159 if (r)
3160 goto out;
3161 r = -EFAULT;
3162 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3163 goto out;
3164 r = 0;
3165 break;
3166 }
313a3dc7 3167 case KVM_GET_MSRS:
609e36d3 3168 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3169 break;
3170 case KVM_SET_MSRS:
3171 r = msr_io(vcpu, argp, do_set_msr, 0);
3172 break;
b209749f
AK		 3173 case KVM_TPR_ACCESS_REPORTING: {
3174 struct kvm_tpr_access_ctl tac;
3175
3176 r = -EFAULT;
3177 if (copy_from_user(&tac, argp, sizeof tac))
3178 goto out;
3179 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3180 if (r)
3181 goto out;
3182 r = -EFAULT;
3183 if (copy_to_user(argp, &tac, sizeof tac))
3184 goto out;
3185 r = 0;
3186 break;
3187 };
b93463aa
AK		 3188 case KVM_SET_VAPIC_ADDR: {
3189 struct kvm_vapic_addr va;
3190
3191 r = -EINVAL;
35754c98 3192 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3193 goto out;
3194 r = -EFAULT;
3195 if (copy_from_user(&va, argp, sizeof va))
3196 goto out;
fda4e2e8 3197 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3198 break;
3199 }
890ca9ae
HY		 3200 case KVM_X86_SETUP_MCE: {
3201 u64 mcg_cap;
3202
3203 r = -EFAULT;
3204 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3205 goto out;
3206 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3207 break;
3208 }
3209 case KVM_X86_SET_MCE: {
3210 struct kvm_x86_mce mce;
3211
3212 r = -EFAULT;
3213 if (copy_from_user(&mce, argp, sizeof mce))
3214 goto out;
3215 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3216 break;
3217 }
3cfc3092
JK		 3218 case KVM_GET_VCPU_EVENTS: {
3219 struct kvm_vcpu_events events;
3220
3221 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3222
3223 r = -EFAULT;
3224 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3225 break;
3226 r = 0;
3227 break;
3228 }
3229 case KVM_SET_VCPU_EVENTS: {
3230 struct kvm_vcpu_events events;
3231
3232 r = -EFAULT;
3233 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3234 break;
3235
3236 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3237 break;
3238 }
a1efbe77
JK		 3239 case KVM_GET_DEBUGREGS: {
3240 struct kvm_debugregs dbgregs;
3241
3242 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3243
3244 r = -EFAULT;
3245 if (copy_to_user(argp, &dbgregs,
3246 sizeof(struct kvm_debugregs)))
3247 break;
3248 r = 0;
3249 break;
3250 }
3251 case KVM_SET_DEBUGREGS: {
3252 struct kvm_debugregs dbgregs;
3253
3254 r = -EFAULT;
3255 if (copy_from_user(&dbgregs, argp,
3256 sizeof(struct kvm_debugregs)))
3257 break;
3258
3259 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3260 break;
3261 }
2d5b5a66 3262 case KVM_GET_XSAVE: {
d1ac91d8 3263 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3264 r = -ENOMEM;
d1ac91d8 3265 if (!u.xsave)
2d5b5a66
SY		 3266 break;
3267
d1ac91d8 3268 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3269
3270 r = -EFAULT;
d1ac91d8 3271 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3272 break;
3273 r = 0;
3274 break;
3275 }
3276 case KVM_SET_XSAVE: {
ff5c2c03 3277 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3278 if (IS_ERR(u.xsave))
3279 return PTR_ERR(u.xsave);
2d5b5a66 3280
d1ac91d8 3281 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3282 break;
3283 }
3284 case KVM_GET_XCRS: {
d1ac91d8 3285 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3286 r = -ENOMEM;
d1ac91d8 3287 if (!u.xcrs)
2d5b5a66
SY		 3288 break;
3289
d1ac91d8 3290 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3291
3292 r = -EFAULT;
d1ac91d8 3293 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3294 sizeof(struct kvm_xcrs)))
3295 break;
3296 r = 0;
3297 break;
3298 }
3299 case KVM_SET_XCRS: {
ff5c2c03 3300 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3301 if (IS_ERR(u.xcrs))
3302 return PTR_ERR(u.xcrs);
2d5b5a66 3303
d1ac91d8 3304 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3305 break;
3306 }
92a1f12d
JR		 3307 case KVM_SET_TSC_KHZ: {
3308 u32 user_tsc_khz;
3309
3310 r = -EINVAL;
92a1f12d
JR		 3311 user_tsc_khz = (u32)arg;
3312
3313 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3314 goto out;
3315
cc578287
ZA		 3316 if (user_tsc_khz == 0)
3317 user_tsc_khz = tsc_khz;
3318
3319 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3320
3321 r = 0;
3322 goto out;
3323 }
3324 case KVM_GET_TSC_KHZ: {
cc578287 3325 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3326 goto out;
3327 }
1c0b28c2
EM		 3328 case KVM_KVMCLOCK_CTRL: {
3329 r = kvm_set_guest_paused(vcpu);
3330 goto out;
3331 }
313a3dc7
CO		 3332 default:
3333 r = -EINVAL;
3334 }
3335out:
d1ac91d8 3336 kfree(u.buffer);
313a3dc7
CO		 3337 return r;
3338}
3339
5b1c1493
CO		 3340int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3341{
3342 return VM_FAULT_SIGBUS;
3343}
3344
1fe779f8
CO		 3345static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3346{
3347 int ret;
3348
3349 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3350 return -EINVAL;
1fe779f8
CO		 3351 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3352 return ret;
3353}
3354
b927a3ce
SY		 3355static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3356 u64 ident_addr)
3357{
3358 kvm->arch.ept_identity_map_addr = ident_addr;
3359 return 0;
3360}
3361
1fe779f8
CO		 3362static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3363 u32 kvm_nr_mmu_pages)
3364{
3365 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3366 return -EINVAL;
3367
79fac95e 3368 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3369
3370 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3371 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3372
79fac95e 3373 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3374 return 0;
3375}
3376
3377static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3378{
39de71ec 3379 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3380}
3381
1fe779f8
CO		 3382static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3383{
3384 int r;
3385
3386 r = 0;
3387 switch (chip->chip_id) {
3388 case KVM_IRQCHIP_PIC_MASTER:
3389 memcpy(&chip->chip.pic,
3390 &pic_irqchip(kvm)->pics[0],
3391 sizeof(struct kvm_pic_state));
3392 break;
3393 case KVM_IRQCHIP_PIC_SLAVE:
3394 memcpy(&chip->chip.pic,
3395 &pic_irqchip(kvm)->pics[1],
3396 sizeof(struct kvm_pic_state));
3397 break;
3398 case KVM_IRQCHIP_IOAPIC:
eba0226b 3399 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3400 break;
3401 default:
3402 r = -EINVAL;
3403 break;
3404 }
3405 return r;
3406}
3407
3408static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3409{
3410 int r;
3411
3412 r = 0;
3413 switch (chip->chip_id) {
3414 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3415 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3416 memcpy(&pic_irqchip(kvm)->pics[0],
3417 &chip->chip.pic,
3418 sizeof(struct kvm_pic_state));
f4f51050 3419 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3420 break;
3421 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3422 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3423 memcpy(&pic_irqchip(kvm)->pics[1],
3424 &chip->chip.pic,
3425 sizeof(struct kvm_pic_state));
f4f51050 3426 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3427 break;
3428 case KVM_IRQCHIP_IOAPIC:
eba0226b 3429 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3430 break;
3431 default:
3432 r = -EINVAL;
3433 break;
3434 }
3435 kvm_pic_update_irq(pic_irqchip(kvm));
3436 return r;
3437}
3438
e0f63cb9
SY		 3439static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3440{
894a9c55 3441 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3442 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3443 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3444 return 0;
e0f63cb9
SY		 3445}
3446
3447static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3448{
894a9c55 3449 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3450 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3451 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3452 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3453 return 0;
e9f42757
BK		 3454}
3455
3456static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3457{
e9f42757
BK		 3458 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3459 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3460 sizeof(ps->channels));
3461 ps->flags = kvm->arch.vpit->pit_state.flags;
3462 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3463 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3464 return 0;
e9f42757
BK		 3465}
3466
3467static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3468{
2da29bcc 3469 int start = 0;
e9f42757
BK		 3470 u32 prev_legacy, cur_legacy;
3471 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3472 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3473 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3474 if (!prev_legacy && cur_legacy)
3475 start = 1;
3476 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3477 sizeof(kvm->arch.vpit->pit_state.channels));
3478 kvm->arch.vpit->pit_state.flags = ps->flags;
3479 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3480 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3481 return 0;
e0f63cb9
SY		 3482}
3483
52d939a0
MT		 3484static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3485 struct kvm_reinject_control *control)
3486{
3487 if (!kvm->arch.vpit)
3488 return -ENXIO;
894a9c55 3489 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3490 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3491 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3492 return 0;
3493}
3494
95d4c16c 3495/**
60c34612
TY		 3496 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3497 * @kvm: kvm instance
3498 * @log: slot id and address to which we copy the log
95d4c16c 3499 *
e108ff2f
PB		 3500 * Steps 1-4 below provide general overview of dirty page logging. See
3501 * kvm_get_dirty_log_protect() function description for additional details.
3502 *
3503 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3504 * always flush the TLB (step 4) even if previous step failed and the dirty
3505 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3506 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3507 * writes will be marked dirty for next log read.
95d4c16c 3508 *
60c34612
TY		 3509 * 1. Take a snapshot of the bit and clear it if needed.
3510 * 2. Write protect the corresponding page.
e108ff2f
PB		 3511 * 3. Copy the snapshot to the userspace.
3512 * 4. Flush TLB's if needed.
5bb064dc 3513 */
60c34612 3514int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3515{
60c34612 3516 bool is_dirty = false;
e108ff2f 3517 int r;
5bb064dc 3518
79fac95e 3519 mutex_lock(&kvm->slots_lock);
5bb064dc 3520
88178fd4
KH		 3521 /*
3522 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3523 */
3524 if (kvm_x86_ops->flush_log_dirty)
3525 kvm_x86_ops->flush_log_dirty(kvm);
3526
e108ff2f 3527 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3528
3529 /*
3530 * All the TLBs can be flushed out of mmu lock, see the comments in
3531 * kvm_mmu_slot_remove_write_access().
3532 */
e108ff2f 3533 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3534 if (is_dirty)
3535 kvm_flush_remote_tlbs(kvm);
3536
79fac95e 3537 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3538 return r;
3539}
3540
aa2fbe6d
YZ		 3541int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3542 bool line_status)
23d43cf9
CD		 3543{
3544 if (!irqchip_in_kernel(kvm))
3545 return -ENXIO;
3546
3547 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3548 irq_event->irq, irq_event->level,
3549 line_status);
23d43cf9
CD		 3550 return 0;
3551}
3552
90de4a18
NA		 3553static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3554 struct kvm_enable_cap *cap)
3555{
3556 int r;
3557
3558 if (cap->flags)
3559 return -EINVAL;
3560
3561 switch (cap->cap) {
3562 case KVM_CAP_DISABLE_QUIRKS:
3563 kvm->arch.disabled_quirks = cap->args[0];
3564 r = 0;
3565 break;
49df6397
SR		 3566 case KVM_CAP_SPLIT_IRQCHIP: {
3567 mutex_lock(&kvm->lock);
b053b2ae
SR		 3568 r = -EINVAL;
3569 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3570 goto split_irqchip_unlock;
49df6397
SR		 3571 r = -EEXIST;
3572 if (irqchip_in_kernel(kvm))
3573 goto split_irqchip_unlock;
3574 if (atomic_read(&kvm->online_vcpus))
3575 goto split_irqchip_unlock;
3576 r = kvm_setup_empty_irq_routing(kvm);
3577 if (r)
3578 goto split_irqchip_unlock;
3579 /* Pairs with irqchip_in_kernel. */
3580 smp_wmb();
3581 kvm->arch.irqchip_split = true;
b053b2ae 3582 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3583 r = 0;
3584split_irqchip_unlock:
3585 mutex_unlock(&kvm->lock);
3586 break;
3587 }
90de4a18
NA		 3588 default:
3589 r = -EINVAL;
3590 break;
3591 }
3592 return r;
3593}
3594
1fe779f8
CO		 3595long kvm_arch_vm_ioctl(struct file *filp,
3596 unsigned int ioctl, unsigned long arg)
3597{
3598 struct kvm *kvm = filp->private_data;
3599 void __user *argp = (void __user *)arg;
367e1319 3600 int r = -ENOTTY;
f0d66275
DH		 3601 /*
3602 * This union makes it completely explicit to gcc-3.x
3603 * that these two variables' stack usage should be
3604 * combined, not added together.
3605 */
3606 union {
3607 struct kvm_pit_state ps;
e9f42757 3608 struct kvm_pit_state2 ps2;
c5ff41ce 3609 struct kvm_pit_config pit_config;
f0d66275 3610 } u;
1fe779f8
CO		 3611
3612 switch (ioctl) {
3613 case KVM_SET_TSS_ADDR:
3614 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3615 break;
b927a3ce
SY		 3616 case KVM_SET_IDENTITY_MAP_ADDR: {
3617 u64 ident_addr;
3618
3619 r = -EFAULT;
3620 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3621 goto out;
3622 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3623 break;
3624 }
1fe779f8
CO		 3625 case KVM_SET_NR_MMU_PAGES:
3626 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3627 break;
3628 case KVM_GET_NR_MMU_PAGES:
3629 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3630 break;
3ddea128
MT		 3631 case KVM_CREATE_IRQCHIP: {
3632 struct kvm_pic *vpic;
3633
3634 mutex_lock(&kvm->lock);
3635 r = -EEXIST;
3636 if (kvm->arch.vpic)
3637 goto create_irqchip_unlock;
3e515705
AK		 3638 r = -EINVAL;
3639 if (atomic_read(&kvm->online_vcpus))
3640 goto create_irqchip_unlock;
1fe779f8 3641 r = -ENOMEM;
3ddea128
MT		 3642 vpic = kvm_create_pic(kvm);
3643 if (vpic) {
1fe779f8
CO		 3644 r = kvm_ioapic_init(kvm);
3645 if (r) {
175504cd 3646 mutex_lock(&kvm->slots_lock);
71ba994c 3647 kvm_destroy_pic(vpic);
175504cd 3648 mutex_unlock(&kvm->slots_lock);
3ddea128 3649 goto create_irqchip_unlock;
1fe779f8
CO		 3650 }
3651 } else
3ddea128 3652 goto create_irqchip_unlock;
399ec807
AK		 3653 r = kvm_setup_default_irq_routing(kvm);
3654 if (r) {
175504cd 3655 mutex_lock(&kvm->slots_lock);
3ddea128 3656 mutex_lock(&kvm->irq_lock);
72bb2fcd 3657 kvm_ioapic_destroy(kvm);
71ba994c 3658 kvm_destroy_pic(vpic);
3ddea128 3659 mutex_unlock(&kvm->irq_lock);
175504cd 3660 mutex_unlock(&kvm->slots_lock);
71ba994c 3661 goto create_irqchip_unlock;
399ec807 3662 }
71ba994c
PB		 3663 /* Write kvm->irq_routing before kvm->arch.vpic. */
3664 smp_wmb();
3665 kvm->arch.vpic = vpic;
3ddea128
MT		 3666 create_irqchip_unlock:
3667 mutex_unlock(&kvm->lock);
1fe779f8 3668 break;
3ddea128 3669 }
7837699f 3670 case KVM_CREATE_PIT:
c5ff41ce
JK		 3671 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3672 goto create_pit;
3673 case KVM_CREATE_PIT2:
3674 r = -EFAULT;
3675 if (copy_from_user(&u.pit_config, argp,
3676 sizeof(struct kvm_pit_config)))
3677 goto out;
3678 create_pit:
79fac95e 3679 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3680 r = -EEXIST;
3681 if (kvm->arch.vpit)
3682 goto create_pit_unlock;
7837699f 3683 r = -ENOMEM;
c5ff41ce 3684 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3685 if (kvm->arch.vpit)
3686 r = 0;
269e05e4 3687 create_pit_unlock:
79fac95e 3688 mutex_unlock(&kvm->slots_lock);
7837699f 3689 break;
1fe779f8
CO		 3690 case KVM_GET_IRQCHIP: {
3691 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3692 struct kvm_irqchip *chip;
1fe779f8 3693
ff5c2c03
SL		 3694 chip = memdup_user(argp, sizeof(*chip));
3695 if (IS_ERR(chip)) {
3696 r = PTR_ERR(chip);
1fe779f8 3697 goto out;
ff5c2c03
SL		 3698 }
3699
1fe779f8 3700 r = -ENXIO;
49df6397 3701 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3702 goto get_irqchip_out;
3703 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3704 if (r)
f0d66275 3705 goto get_irqchip_out;
1fe779f8 3706 r = -EFAULT;
f0d66275
DH		 3707 if (copy_to_user(argp, chip, sizeof *chip))
3708 goto get_irqchip_out;
1fe779f8 3709 r = 0;
f0d66275
DH		 3710 get_irqchip_out:
3711 kfree(chip);
1fe779f8
CO		 3712 break;
3713 }
3714 case KVM_SET_IRQCHIP: {
3715 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3716 struct kvm_irqchip *chip;
1fe779f8 3717
ff5c2c03
SL		 3718 chip = memdup_user(argp, sizeof(*chip));
3719 if (IS_ERR(chip)) {
3720 r = PTR_ERR(chip);
1fe779f8 3721 goto out;
ff5c2c03
SL		 3722 }
3723
1fe779f8 3724 r = -ENXIO;
49df6397 3725 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3726 goto set_irqchip_out;
3727 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3728 if (r)
f0d66275 3729 goto set_irqchip_out;
1fe779f8 3730 r = 0;
f0d66275
DH		 3731 set_irqchip_out:
3732 kfree(chip);
1fe779f8
CO		 3733 break;
3734 }
e0f63cb9 3735 case KVM_GET_PIT: {
e0f63cb9 3736 r = -EFAULT;
f0d66275 3737 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3738 goto out;
3739 r = -ENXIO;
3740 if (!kvm->arch.vpit)
3741 goto out;
f0d66275 3742 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3743 if (r)
3744 goto out;
3745 r = -EFAULT;
f0d66275 3746 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3747 goto out;
3748 r = 0;
3749 break;
3750 }
3751 case KVM_SET_PIT: {
e0f63cb9 3752 r = -EFAULT;
f0d66275 3753 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3754 goto out;
3755 r = -ENXIO;
3756 if (!kvm->arch.vpit)
3757 goto out;
f0d66275 3758 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3759 break;
3760 }
e9f42757
BK		 3761 case KVM_GET_PIT2: {
3762 r = -ENXIO;
3763 if (!kvm->arch.vpit)
3764 goto out;
3765 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3766 if (r)
3767 goto out;
3768 r = -EFAULT;
3769 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3770 goto out;
3771 r = 0;
3772 break;
3773 }
3774 case KVM_SET_PIT2: {
3775 r = -EFAULT;
3776 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3777 goto out;
3778 r = -ENXIO;
3779 if (!kvm->arch.vpit)
3780 goto out;
3781 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3782 break;
3783 }
52d939a0
MT		 3784 case KVM_REINJECT_CONTROL: {
3785 struct kvm_reinject_control control;
3786 r = -EFAULT;
3787 if (copy_from_user(&control, argp, sizeof(control)))
3788 goto out;
3789 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3790 break;
3791 }
d71ba788
PB		 3792 case KVM_SET_BOOT_CPU_ID:
3793 r = 0;
3794 mutex_lock(&kvm->lock);
3795 if (atomic_read(&kvm->online_vcpus) != 0)
3796 r = -EBUSY;
3797 else
3798 kvm->arch.bsp_vcpu_id = arg;
3799 mutex_unlock(&kvm->lock);
3800 break;
ffde22ac
ES		 3801 case KVM_XEN_HVM_CONFIG: {
3802 r = -EFAULT;
3803 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3804 sizeof(struct kvm_xen_hvm_config)))
3805 goto out;
3806 r = -EINVAL;
3807 if (kvm->arch.xen_hvm_config.flags)
3808 goto out;
3809 r = 0;
3810 break;
3811 }
afbcf7ab 3812 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3813 struct kvm_clock_data user_ns;
3814 u64 now_ns;
3815 s64 delta;
3816
3817 r = -EFAULT;
3818 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3819 goto out;
3820
3821 r = -EINVAL;
3822 if (user_ns.flags)
3823 goto out;
3824
3825 r = 0;
395c6b0a 3826 local_irq_disable();
759379dd 3827 now_ns = get_kernel_ns();
afbcf7ab 3828 delta = user_ns.clock - now_ns;
395c6b0a 3829 local_irq_enable();
afbcf7ab 3830 kvm->arch.kvmclock_offset = delta;
2e762ff7 3831 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3832 break;
3833 }
3834 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3835 struct kvm_clock_data user_ns;
3836 u64 now_ns;
3837
395c6b0a 3838 local_irq_disable();
759379dd 3839 now_ns = get_kernel_ns();
afbcf7ab 3840 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3841 local_irq_enable();
afbcf7ab 3842 user_ns.flags = 0;
97e69aa6 3843 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3844
3845 r = -EFAULT;
3846 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3847 goto out;
3848 r = 0;
3849 break;
3850 }
90de4a18
NA		 3851 case KVM_ENABLE_CAP: {
3852 struct kvm_enable_cap cap;
afbcf7ab 3853
90de4a18
NA		 3854 r = -EFAULT;
3855 if (copy_from_user(&cap, argp, sizeof(cap)))
3856 goto out;
3857 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
3858 break;
3859 }
1fe779f8 3860 default:
c274e03a 3861 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 3862 }
3863out:
3864 return r;
3865}
3866
a16b043c 3867static void kvm_init_msr_list(void)
043405e1
CO		 3868{
3869 u32 dummy[2];
3870 unsigned i, j;
3871
62ef68bb 3872 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3873 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3874 continue;
93c4adc7
PB		 3875
3876 /*
3877 * Even MSRs that are valid in the host may not be exposed
3878 * to the guests in some cases. We could work around this
3879 * in VMX with the generic MSR save/load machinery, but it
3880 * is not really worthwhile since it will really only
3881 * happen with nested virtualization.
3882 */
3883 switch (msrs_to_save[i]) {
3884 case MSR_IA32_BNDCFGS:
3885 if (!kvm_x86_ops->mpx_supported())
3886 continue;
3887 break;
3888 default:
3889 break;
3890 }
3891
043405e1
CO		 3892 if (j < i)
3893 msrs_to_save[j] = msrs_to_save[i];
3894 j++;
3895 }
3896 num_msrs_to_save = j;
62ef68bb
PB		 3897
3898 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
3899 switch (emulated_msrs[i]) {
6d396b55
PB		 3900 case MSR_IA32_SMBASE:
3901 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
3902 continue;
3903 break;
62ef68bb
PB		 3904 default:
3905 break;
3906 }
3907
3908 if (j < i)
3909 emulated_msrs[j] = emulated_msrs[i];
3910 j++;
3911 }
3912 num_emulated_msrs = j;
043405e1
CO		 3913}
3914
bda9020e
MT		 3915static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3916 const void *v)
bbd9b64e 3917{
70252a10
AK		 3918 int handled = 0;
3919 int n;
3920
3921 do {
3922 n = min(len, 8);
3923 if (!(vcpu->arch.apic &&
e32edf4f
NN		 3924 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
3925 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 3926 break;
3927 handled += n;
3928 addr += n;
3929 len -= n;
3930 v += n;
3931 } while (len);
bbd9b64e 3932
70252a10 3933 return handled;
bbd9b64e
CO		 3934}
3935
bda9020e 3936static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3937{
70252a10
AK		 3938 int handled = 0;
3939 int n;
3940
3941 do {
3942 n = min(len, 8);
3943 if (!(vcpu->arch.apic &&
e32edf4f
NN		 3944 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
3945 addr, n, v))
3946 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 3947 break;
3948 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3949 handled += n;
3950 addr += n;
3951 len -= n;
3952 v += n;
3953 } while (len);
bbd9b64e 3954
70252a10 3955 return handled;
bbd9b64e
CO		 3956}
3957
2dafc6c2
GN		 3958static void kvm_set_segment(struct kvm_vcpu *vcpu,
3959 struct kvm_segment *var, int seg)
3960{
3961 kvm_x86_ops->set_segment(vcpu, var, seg);
3962}
3963
3964void kvm_get_segment(struct kvm_vcpu *vcpu,
3965 struct kvm_segment *var, int seg)
3966{
3967 kvm_x86_ops->get_segment(vcpu, var, seg);
3968}
3969
54987b7a
PB		 3970gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
3971 struct x86_exception *exception)
02f59dc9
JR		 3972{
3973 gpa_t t_gpa;
02f59dc9
JR		 3974
3975 BUG_ON(!mmu_is_nested(vcpu));
3976
3977 /* NPT walks are always user-walks */
3978 access |= PFERR_USER_MASK;
54987b7a 3979 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 3980
3981 return t_gpa;
3982}
3983
ab9ae313
AK		 3984gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3985 struct x86_exception *exception)
1871c602
GN		 3986{
3987 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3988 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3989}
3990
ab9ae313
AK		 3991 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3992 struct x86_exception *exception)
1871c602
GN		 3993{
3994 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3995 access |= PFERR_FETCH_MASK;
ab9ae313 3996 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3997}
3998
ab9ae313
AK		 3999gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4000 struct x86_exception *exception)
1871c602
GN		 4001{
4002 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4003 access |= PFERR_WRITE_MASK;
ab9ae313 4004 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4005}
4006
4007/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4008gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4009 struct x86_exception *exception)
1871c602 4010{
ab9ae313 4011 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4012}
4013
4014static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4015 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4016 struct x86_exception *exception)
bbd9b64e
CO		 4017{
4018 void *data = val;
10589a46 4019 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4020
4021 while (bytes) {
14dfe855 4022 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4023 exception);
bbd9b64e 4024 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4025 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4026 int ret;
4027
bcc55cba 4028 if (gpa == UNMAPPED_GVA)
ab9ae313 4029 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4030 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4031 offset, toread);
10589a46 4032 if (ret < 0) {
c3cd7ffa 4033 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4034 goto out;
4035 }
bbd9b64e 4036
77c2002e
IE		 4037 bytes -= toread;
4038 data += toread;
4039 addr += toread;
bbd9b64e 4040 }
10589a46 4041out:
10589a46 4042 return r;
bbd9b64e 4043}
77c2002e 4044
1871c602 4045/* used for instruction fetching */
0f65dd70
AK		 4046static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4047 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4048 struct x86_exception *exception)
1871c602 4049{
0f65dd70 4050 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4051 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4052 unsigned offset;
4053 int ret;
0f65dd70 4054
44583cba
PB		 4055 /* Inline kvm_read_guest_virt_helper for speed. */
4056 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4057 exception);
4058 if (unlikely(gpa == UNMAPPED_GVA))
4059 return X86EMUL_PROPAGATE_FAULT;
4060
4061 offset = addr & (PAGE_SIZE-1);
4062 if (WARN_ON(offset + bytes > PAGE_SIZE))
4063 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4064 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4065 offset, bytes);
44583cba
PB		 4066 if (unlikely(ret < 0))
4067 return X86EMUL_IO_NEEDED;
4068
4069 return X86EMUL_CONTINUE;
1871c602
GN		 4070}
4071
064aea77 4072int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4073 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4074 struct x86_exception *exception)
1871c602 4075{
0f65dd70 4076 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4077 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4078
1871c602 4079 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4080 exception);
1871c602 4081}
064aea77 4082EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4083
0f65dd70
AK		 4084static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4085 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4086 struct x86_exception *exception)
1871c602 4087{
0f65dd70 4088 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4089 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4090}
4091
7a036a6f
RK		 4092static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4093 unsigned long addr, void *val, unsigned int bytes)
4094{
4095 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4096 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4097
4098 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4099}
4100
6a4d7550 4101int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4102 gva_t addr, void *val,
2dafc6c2 4103 unsigned int bytes,
bcc55cba 4104 struct x86_exception *exception)
77c2002e 4105{
0f65dd70 4106 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4107 void *data = val;
4108 int r = X86EMUL_CONTINUE;
4109
4110 while (bytes) {
14dfe855
JR		 4111 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4112 PFERR_WRITE_MASK,
ab9ae313 4113 exception);
77c2002e
IE		 4114 unsigned offset = addr & (PAGE_SIZE-1);
4115 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4116 int ret;
4117
bcc55cba 4118 if (gpa == UNMAPPED_GVA)
ab9ae313 4119 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4120 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4121 if (ret < 0) {
c3cd7ffa 4122 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4123 goto out;
4124 }
4125
4126 bytes -= towrite;
4127 data += towrite;
4128 addr += towrite;
4129 }
4130out:
4131 return r;
4132}
6a4d7550 4133EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4134
af7cc7d1
XG		 4135static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4136 gpa_t *gpa, struct x86_exception *exception,
4137 bool write)
4138{
97d64b78
AK		 4139 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4140 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4141
97d64b78 4142 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4143 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4144 vcpu->arch.access, access)) {
bebb106a
XG		 4145 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4146 (gva & (PAGE_SIZE - 1));
4f022648 4147 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4148 return 1;
4149 }
4150
af7cc7d1
XG		 4151 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4152
4153 if (*gpa == UNMAPPED_GVA)
4154 return -1;
4155
4156 /* For APIC access vmexit */
4157 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4158 return 1;
4159
4f022648
XG		 4160 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4161 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4162 return 1;
4f022648 4163 }
bebb106a 4164
af7cc7d1
XG		 4165 return 0;
4166}
4167
3200f405 4168int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4169 const void *val, int bytes)
bbd9b64e
CO		 4170{
4171 int ret;
4172
54bf36aa 4173 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4174 if (ret < 0)
bbd9b64e 4175 return 0;
f57f2ef5 4176 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4177 return 1;
4178}
4179
77d197b2
XG		 4180struct read_write_emulator_ops {
4181 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4182 int bytes);
4183 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4184 void *val, int bytes);
4185 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4186 int bytes, void *val);
4187 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4188 void *val, int bytes);
4189 bool write;
4190};
4191
4192static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4193{
4194 if (vcpu->mmio_read_completed) {
77d197b2 4195 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4196 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4197 vcpu->mmio_read_completed = 0;
4198 return 1;
4199 }
4200
4201 return 0;
4202}
4203
4204static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4205 void *val, int bytes)
4206{
54bf36aa 4207 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4208}
4209
4210static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4211 void *val, int bytes)
4212{
4213 return emulator_write_phys(vcpu, gpa, val, bytes);
4214}
4215
4216static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4217{
4218 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4219 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4220}
4221
4222static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4223 void *val, int bytes)
4224{
4225 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4226 return X86EMUL_IO_NEEDED;
4227}
4228
4229static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4230 void *val, int bytes)
4231{
f78146b0
AK		 4232 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4233
87da7e66 4234 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4235 return X86EMUL_CONTINUE;
4236}
4237
0fbe9b0b 4238static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4239 .read_write_prepare = read_prepare,
4240 .read_write_emulate = read_emulate,
4241 .read_write_mmio = vcpu_mmio_read,
4242 .read_write_exit_mmio = read_exit_mmio,
4243};
4244
0fbe9b0b 4245static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4246 .read_write_emulate = write_emulate,
4247 .read_write_mmio = write_mmio,
4248 .read_write_exit_mmio = write_exit_mmio,
4249 .write = true,
4250};
4251
22388a3c
XG		 4252static int emulator_read_write_onepage(unsigned long addr, void *val,
4253 unsigned int bytes,
4254 struct x86_exception *exception,
4255 struct kvm_vcpu *vcpu,
0fbe9b0b 4256 const struct read_write_emulator_ops *ops)
bbd9b64e 4257{
af7cc7d1
XG		 4258 gpa_t gpa;
4259 int handled, ret;
22388a3c 4260 bool write = ops->write;
f78146b0 4261 struct kvm_mmio_fragment *frag;
10589a46 4262
22388a3c 4263 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4264
af7cc7d1 4265 if (ret < 0)
bbd9b64e 4266 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4267
4268 /* For APIC access vmexit */
af7cc7d1 4269 if (ret)
bbd9b64e
CO		 4270 goto mmio;
4271
22388a3c 4272 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4273 return X86EMUL_CONTINUE;
4274
4275mmio:
4276 /*
4277 * Is this MMIO handled locally?
4278 */
22388a3c 4279 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4280 if (handled == bytes)
bbd9b64e 4281 return X86EMUL_CONTINUE;
bbd9b64e 4282
70252a10
AK		 4283 gpa += handled;
4284 bytes -= handled;
4285 val += handled;
4286
87da7e66
XG		 4287 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4288 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4289 frag->gpa = gpa;
4290 frag->data = val;
4291 frag->len = bytes;
f78146b0 4292 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4293}
4294
52eb5a6d
XL		 4295static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4296 unsigned long addr,
22388a3c
XG		 4297 void *val, unsigned int bytes,
4298 struct x86_exception *exception,
0fbe9b0b 4299 const struct read_write_emulator_ops *ops)
bbd9b64e 4300{
0f65dd70 4301 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4302 gpa_t gpa;
4303 int rc;
4304
4305 if (ops->read_write_prepare &&
4306 ops->read_write_prepare(vcpu, val, bytes))
4307 return X86EMUL_CONTINUE;
4308
4309 vcpu->mmio_nr_fragments = 0;
0f65dd70 4310
bbd9b64e
CO		 4311 /* Crossing a page boundary? */
4312 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4313 int now;
bbd9b64e
CO		 4314
4315 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4316 rc = emulator_read_write_onepage(addr, val, now, exception,
4317 vcpu, ops);
4318
bbd9b64e
CO		 4319 if (rc != X86EMUL_CONTINUE)
4320 return rc;
4321 addr += now;
bac15531
NA		 4322 if (ctxt->mode != X86EMUL_MODE_PROT64)
4323 addr = (u32)addr;
bbd9b64e
CO		 4324 val += now;
4325 bytes -= now;
4326 }
22388a3c 4327
f78146b0
AK		 4328 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4329 vcpu, ops);
4330 if (rc != X86EMUL_CONTINUE)
4331 return rc;
4332
4333 if (!vcpu->mmio_nr_fragments)
4334 return rc;
4335
4336 gpa = vcpu->mmio_fragments[0].gpa;
4337
4338 vcpu->mmio_needed = 1;
4339 vcpu->mmio_cur_fragment = 0;
4340
87da7e66 4341 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4342 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4343 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4344 vcpu->run->mmio.phys_addr = gpa;
4345
4346 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4347}
4348
4349static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4350 unsigned long addr,
4351 void *val,
4352 unsigned int bytes,
4353 struct x86_exception *exception)
4354{
4355 return emulator_read_write(ctxt, addr, val, bytes,
4356 exception, &read_emultor);
4357}
4358
52eb5a6d 4359static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4360 unsigned long addr,
4361 const void *val,
4362 unsigned int bytes,
4363 struct x86_exception *exception)
4364{
4365 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4366 exception, &write_emultor);
bbd9b64e 4367}
bbd9b64e 4368
daea3e73
AK		 4369#define CMPXCHG_TYPE(t, ptr, old, new) \
4370 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4371
4372#ifdef CONFIG_X86_64
4373# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4374#else
4375# define CMPXCHG64(ptr, old, new) \
9749a6c0 4376 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4377#endif
4378
0f65dd70
AK		 4379static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4380 unsigned long addr,
bbd9b64e
CO		 4381 const void *old,
4382 const void *new,
4383 unsigned int bytes,
0f65dd70 4384 struct x86_exception *exception)
bbd9b64e 4385{
0f65dd70 4386 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4387 gpa_t gpa;
4388 struct page *page;
4389 char *kaddr;
4390 bool exchanged;
2bacc55c 4391
daea3e73
AK		 4392 /* guests cmpxchg8b have to be emulated atomically */
4393 if (bytes > 8 || (bytes & (bytes - 1)))
4394 goto emul_write;
10589a46 4395
daea3e73 4396 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4397
daea3e73
AK		 4398 if (gpa == UNMAPPED_GVA ||
4399 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4400 goto emul_write;
2bacc55c 4401
daea3e73
AK		 4402 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4403 goto emul_write;
72dc67a6 4404
54bf36aa 4405 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4406 if (is_error_page(page))
c19b8bd6 4407 goto emul_write;
72dc67a6 4408
8fd75e12 4409 kaddr = kmap_atomic(page);
daea3e73
AK		 4410 kaddr += offset_in_page(gpa);
4411 switch (bytes) {
4412 case 1:
4413 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4414 break;
4415 case 2:
4416 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4417 break;
4418 case 4:
4419 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4420 break;
4421 case 8:
4422 exchanged = CMPXCHG64(kaddr, old, new);
4423 break;
4424 default:
4425 BUG();
2bacc55c 4426 }
8fd75e12 4427 kunmap_atomic(kaddr);
daea3e73
AK		 4428 kvm_release_page_dirty(page);
4429
4430 if (!exchanged)
4431 return X86EMUL_CMPXCHG_FAILED;
4432
54bf36aa 4433 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
f57f2ef5 4434 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4435
4436 return X86EMUL_CONTINUE;
4a5f48f6 4437
3200f405 4438emul_write:
daea3e73 4439 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4440
0f65dd70 4441 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4442}
4443
cf8f70bf
GN		 4444static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4445{
4446 /* TODO: String I/O for in kernel device */
4447 int r;
4448
4449 if (vcpu->arch.pio.in)
e32edf4f 4450 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4451 vcpu->arch.pio.size, pd);
4452 else
e32edf4f 4453 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4454 vcpu->arch.pio.port, vcpu->arch.pio.size,
4455 pd);
4456 return r;
4457}
4458
6f6fbe98
XG		 4459static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4460 unsigned short port, void *val,
4461 unsigned int count, bool in)
cf8f70bf 4462{
cf8f70bf 4463 vcpu->arch.pio.port = port;
6f6fbe98 4464 vcpu->arch.pio.in = in;
7972995b 4465 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4466 vcpu->arch.pio.size = size;
4467
4468 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4469 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4470 return 1;
4471 }
4472
4473 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4474 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4475 vcpu->run->io.size = size;
4476 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4477 vcpu->run->io.count = count;
4478 vcpu->run->io.port = port;
4479
4480 return 0;
4481}
4482
6f6fbe98
XG		 4483static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4484 int size, unsigned short port, void *val,
4485 unsigned int count)
cf8f70bf 4486{
ca1d4a9e 4487 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4488 int ret;
ca1d4a9e 4489
6f6fbe98
XG		 4490 if (vcpu->arch.pio.count)
4491 goto data_avail;
cf8f70bf 4492
6f6fbe98
XG		 4493 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4494 if (ret) {
4495data_avail:
4496 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4497 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4498 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4499 return 1;
4500 }
4501
cf8f70bf
GN		 4502 return 0;
4503}
4504
6f6fbe98
XG		 4505static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4506 int size, unsigned short port,
4507 const void *val, unsigned int count)
4508{
4509 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4510
4511 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4512 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4513 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4514}
4515
bbd9b64e
CO		 4516static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4517{
4518 return kvm_x86_ops->get_segment_base(vcpu, seg);
4519}
4520
3cb16fe7 4521static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4522{
3cb16fe7 4523 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4524}
4525
5cb56059 4526int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4527{
4528 if (!need_emulate_wbinvd(vcpu))
4529 return X86EMUL_CONTINUE;
4530
4531 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4532 int cpu = get_cpu();
4533
4534 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4535 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4536 wbinvd_ipi, NULL, 1);
2eec7343 4537 put_cpu();
f5f48ee1 4538 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4539 } else
4540 wbinvd();
f5f48ee1
SY		 4541 return X86EMUL_CONTINUE;
4542}
5cb56059
JS		 4543
4544int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4545{
4546 kvm_x86_ops->skip_emulated_instruction(vcpu);
4547 return kvm_emulate_wbinvd_noskip(vcpu);
4548}
f5f48ee1
SY		 4549EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4550
5cb56059
JS		 4551
4552
bcaf5cc5
AK		 4553static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4554{
5cb56059 4555 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4556}
4557
52eb5a6d
XL		 4558static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4559 unsigned long *dest)
bbd9b64e 4560{
16f8a6f9 4561 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4562}
4563
52eb5a6d
XL		 4564static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4565 unsigned long value)
bbd9b64e 4566{
338dbc97 4567
717746e3 4568 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4569}
4570
52a46617 4571static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4572{
52a46617 4573 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4574}
4575
717746e3 4576static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4577{
717746e3 4578 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4579 unsigned long value;
4580
4581 switch (cr) {
4582 case 0:
4583 value = kvm_read_cr0(vcpu);
4584 break;
4585 case 2:
4586 value = vcpu->arch.cr2;
4587 break;
4588 case 3:
9f8fe504 4589 value = kvm_read_cr3(vcpu);
52a46617
GN		 4590 break;
4591 case 4:
4592 value = kvm_read_cr4(vcpu);
4593 break;
4594 case 8:
4595 value = kvm_get_cr8(vcpu);
4596 break;
4597 default:
a737f256 4598 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4599 return 0;
4600 }
4601
4602 return value;
4603}
4604
717746e3 4605static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4606{
717746e3 4607 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4608 int res = 0;
4609
52a46617
GN		 4610 switch (cr) {
4611 case 0:
49a9b07e 4612 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4613 break;
4614 case 2:
4615 vcpu->arch.cr2 = val;
4616 break;
4617 case 3:
2390218b 4618 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4619 break;
4620 case 4:
a83b29c6 4621 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4622 break;
4623 case 8:
eea1cff9 4624 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4625 break;
4626 default:
a737f256 4627 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4628 res = -1;
52a46617 4629 }
0f12244f
GN		 4630
4631 return res;
52a46617
GN		 4632}
4633
717746e3 4634static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4635{
717746e3 4636 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4637}
4638
4bff1e86 4639static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4640{
4bff1e86 4641 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4642}
4643
4bff1e86 4644static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4645{
4bff1e86 4646 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4647}
4648
1ac9d0cf
AK		 4649static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4650{
4651 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4652}
4653
4654static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4655{
4656 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4657}
4658
4bff1e86
AK		 4659static unsigned long emulator_get_cached_segment_base(
4660 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4661{
4bff1e86 4662 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4663}
4664
1aa36616
AK		 4665static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4666 struct desc_struct *desc, u32 *base3,
4667 int seg)
2dafc6c2
GN		 4668{
4669 struct kvm_segment var;
4670
4bff1e86 4671 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4672 *selector = var.selector;
2dafc6c2 4673
378a8b09
GN		 4674 if (var.unusable) {
4675 memset(desc, 0, sizeof(*desc));
2dafc6c2 4676 return false;
378a8b09 4677 }
2dafc6c2
GN		 4678
4679 if (var.g)
4680 var.limit >>= 12;
4681 set_desc_limit(desc, var.limit);
4682 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4683#ifdef CONFIG_X86_64
4684 if (base3)
4685 *base3 = var.base >> 32;
4686#endif
2dafc6c2
GN		 4687 desc->type = var.type;
4688 desc->s = var.s;
4689 desc->dpl = var.dpl;
4690 desc->p = var.present;
4691 desc->avl = var.avl;
4692 desc->l = var.l;
4693 desc->d = var.db;
4694 desc->g = var.g;
4695
4696 return true;
4697}
4698
1aa36616
AK		 4699static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4700 struct desc_struct *desc, u32 base3,
4701 int seg)
2dafc6c2 4702{
4bff1e86 4703 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4704 struct kvm_segment var;
4705
1aa36616 4706 var.selector = selector;
2dafc6c2 4707 var.base = get_desc_base(desc);
5601d05b
GN		 4708#ifdef CONFIG_X86_64
4709 var.base |= ((u64)base3) << 32;
4710#endif
2dafc6c2
GN		 4711 var.limit = get_desc_limit(desc);
4712 if (desc->g)
4713 var.limit = (var.limit << 12) | 0xfff;
4714 var.type = desc->type;
2dafc6c2
GN		 4715 var.dpl = desc->dpl;
4716 var.db = desc->d;
4717 var.s = desc->s;
4718 var.l = desc->l;
4719 var.g = desc->g;
4720 var.avl = desc->avl;
4721 var.present = desc->p;
4722 var.unusable = !var.present;
4723 var.padding = 0;
4724
4725 kvm_set_segment(vcpu, &var, seg);
4726 return;
4727}
4728
717746e3
AK		 4729static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4730 u32 msr_index, u64 *pdata)
4731{
609e36d3
PB		 4732 struct msr_data msr;
4733 int r;
4734
4735 msr.index = msr_index;
4736 msr.host_initiated = false;
4737 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4738 if (r)
4739 return r;
4740
4741 *pdata = msr.data;
4742 return 0;
717746e3
AK		 4743}
4744
4745static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4746 u32 msr_index, u64 data)
4747{
8fe8ab46
WA		 4748 struct msr_data msr;
4749
4750 msr.data = data;
4751 msr.index = msr_index;
4752 msr.host_initiated = false;
4753 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4754}
4755
64d60670
PB		 4756static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4757{
4758 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4759
4760 return vcpu->arch.smbase;
4761}
4762
4763static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4764{
4765 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4766
4767 vcpu->arch.smbase = smbase;
4768}
4769
67f4d428
NA		 4770static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4771 u32 pmc)
4772{
c6702c9d 4773 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 4774}
4775
222d21aa
AK		 4776static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4777 u32 pmc, u64 *pdata)
4778{
c6702c9d 4779 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 4780}
4781
6c3287f7
AK		 4782static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4783{
4784 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4785}
4786
5037f6f3
AK		 4787static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4788{
4789 preempt_disable();
5197b808 4790 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4791 /*
4792 * CR0.TS may reference the host fpu state, not the guest fpu state,
4793 * so it may be clear at this point.
4794 */
4795 clts();
4796}
4797
4798static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4799{
4800 preempt_enable();
4801}
4802
2953538e 4803static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4804 struct x86_instruction_info *info,
c4f035c6
AK		 4805 enum x86_intercept_stage stage)
4806{
2953538e 4807 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4808}
4809
0017f93a 4810static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4811 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4812{
0017f93a 4813 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4814}
4815
dd856efa
AK		 4816static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4817{
4818 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4819}
4820
4821static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4822{
4823 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4824}
4825
801806d9
NA		 4826static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
4827{
4828 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
4829}
4830
0225fb50 4831static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4832 .read_gpr = emulator_read_gpr,
4833 .write_gpr = emulator_write_gpr,
1871c602 4834 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4835 .write_std = kvm_write_guest_virt_system,
7a036a6f 4836 .read_phys = kvm_read_guest_phys_system,
1871c602 4837 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4838 .read_emulated = emulator_read_emulated,
4839 .write_emulated = emulator_write_emulated,
4840 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4841 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4842 .pio_in_emulated = emulator_pio_in_emulated,
4843 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4844 .get_segment = emulator_get_segment,
4845 .set_segment = emulator_set_segment,
5951c442 4846 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4847 .get_gdt = emulator_get_gdt,
160ce1f1 4848 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4849 .set_gdt = emulator_set_gdt,
4850 .set_idt = emulator_set_idt,
52a46617
GN		 4851 .get_cr = emulator_get_cr,
4852 .set_cr = emulator_set_cr,
9c537244 4853 .cpl = emulator_get_cpl,
35aa5375
GN		 4854 .get_dr = emulator_get_dr,
4855 .set_dr = emulator_set_dr,
64d60670
PB		 4856 .get_smbase = emulator_get_smbase,
4857 .set_smbase = emulator_set_smbase,
717746e3
AK		 4858 .set_msr = emulator_set_msr,
4859 .get_msr = emulator_get_msr,
67f4d428 4860 .check_pmc = emulator_check_pmc,
222d21aa 4861 .read_pmc = emulator_read_pmc,
6c3287f7 4862 .halt = emulator_halt,
bcaf5cc5 4863 .wbinvd = emulator_wbinvd,
d6aa1000 4864 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4865 .get_fpu = emulator_get_fpu,
4866 .put_fpu = emulator_put_fpu,
c4f035c6 4867 .intercept = emulator_intercept,
bdb42f5a 4868 .get_cpuid = emulator_get_cpuid,
801806d9 4869 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 4870};
4871
95cb2295
GN		 4872static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4873{
37ccdcbe 4874 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 4875 /*
4876 * an sti; sti; sequence only disable interrupts for the first
4877 * instruction. So, if the last instruction, be it emulated or
4878 * not, left the system with the INT_STI flag enabled, it
4879 * means that the last instruction is an sti. We should not
4880 * leave the flag on in this case. The same goes for mov ss
4881 */
37ccdcbe
PB		 4882 if (int_shadow & mask)
4883 mask = 0;
6addfc42 4884 if (unlikely(int_shadow || mask)) {
95cb2295 4885 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 4886 if (!mask)
4887 kvm_make_request(KVM_REQ_EVENT, vcpu);
4888 }
95cb2295
GN		 4889}
4890
ef54bcfe 4891static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 4892{
4893 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4894 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 4895 return kvm_propagate_fault(vcpu, &ctxt->exception);
4896
4897 if (ctxt->exception.error_code_valid)
da9cb575
AK		 4898 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4899 ctxt->exception.error_code);
54b8486f 4900 else
da9cb575 4901 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 4902 return false;
54b8486f
GN		 4903}
4904
8ec4722d
MG		 4905static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4906{
adf52235 4907 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4908 int cs_db, cs_l;
4909
8ec4722d
MG		 4910 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4911
adf52235
TY		 4912 ctxt->eflags = kvm_get_rflags(vcpu);
4913 ctxt->eip = kvm_rip_read(vcpu);
4914 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4915 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 4916 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 4917 cs_db ? X86EMUL_MODE_PROT32 :
4918 X86EMUL_MODE_PROT16;
a584539b 4919 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 4920 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
4921 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 4922 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 4923
dd856efa 4924 init_decode_cache(ctxt);
7ae441ea 4925 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4926}
4927
71f9833b 4928int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4929{
9d74191a 4930 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4931 int ret;
4932
4933 init_emulate_ctxt(vcpu);
4934
9dac77fa
AK		 4935 ctxt->op_bytes = 2;
4936 ctxt->ad_bytes = 2;
4937 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4938 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4939
4940 if (ret != X86EMUL_CONTINUE)
4941 return EMULATE_FAIL;
4942
9dac77fa 4943 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4944 kvm_rip_write(vcpu, ctxt->eip);
4945 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4946
4947 if (irq == NMI_VECTOR)
7460fb4a 4948 vcpu->arch.nmi_pending = 0;
63995653
MG		 4949 else
4950 vcpu->arch.interrupt.pending = false;
4951
4952 return EMULATE_DONE;
4953}
4954EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4955
6d77dbfc
GN		 4956static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4957{
fc3a9157
JR		 4958 int r = EMULATE_DONE;
4959
6d77dbfc
GN		 4960 ++vcpu->stat.insn_emulation_fail;
4961 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 4962 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 4963 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4964 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4965 vcpu->run->internal.ndata = 0;
4966 r = EMULATE_FAIL;
4967 }
6d77dbfc 4968 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4969
4970 return r;
6d77dbfc
GN		 4971}
4972
93c05d3e 4973static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4974 bool write_fault_to_shadow_pgtable,
4975 int emulation_type)
a6f177ef 4976{
95b3cf69 4977 gpa_t gpa = cr2;
8e3d9d06 4978 pfn_t pfn;
a6f177ef 4979
991eebf9
GN		 4980 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4981 return false;
4982
95b3cf69
XG		 4983 if (!vcpu->arch.mmu.direct_map) {
4984 /*
4985 * Write permission should be allowed since only
4986 * write access need to be emulated.
4987 */
4988 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 4989
95b3cf69
XG		 4990 /*
4991 * If the mapping is invalid in guest, let cpu retry
4992 * it to generate fault.
4993 */
4994 if (gpa == UNMAPPED_GVA)
4995 return true;
4996 }
a6f177ef 4997
8e3d9d06
XG		 4998 /*
4999 * Do not retry the unhandleable instruction if it faults on the
5000 * readonly host memory, otherwise it will goto a infinite loop:
5001 * retry instruction -> write #PF -> emulation fail -> retry
5002 * instruction -> ...
5003 */
5004 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5005
5006 /*
5007 * If the instruction failed on the error pfn, it can not be fixed,
5008 * report the error to userspace.
5009 */
5010 if (is_error_noslot_pfn(pfn))
5011 return false;
5012
5013 kvm_release_pfn_clean(pfn);
5014
5015 /* The instructions are well-emulated on direct mmu. */
5016 if (vcpu->arch.mmu.direct_map) {
5017 unsigned int indirect_shadow_pages;
5018
5019 spin_lock(&vcpu->kvm->mmu_lock);
5020 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5021 spin_unlock(&vcpu->kvm->mmu_lock);
5022
5023 if (indirect_shadow_pages)
5024 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5025
a6f177ef 5026 return true;
8e3d9d06 5027 }
a6f177ef 5028
95b3cf69
XG		 5029 /*
5030 * if emulation was due to access to shadowed page table
5031 * and it failed try to unshadow page and re-enter the
5032 * guest to let CPU execute the instruction.
5033 */
5034 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5035
5036 /*
5037 * If the access faults on its page table, it can not
5038 * be fixed by unprotecting shadow page and it should
5039 * be reported to userspace.
5040 */
5041 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5042}
5043
1cb3f3ae
XG		 5044static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5045 unsigned long cr2, int emulation_type)
5046{
5047 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5048 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5049
5050 last_retry_eip = vcpu->arch.last_retry_eip;
5051 last_retry_addr = vcpu->arch.last_retry_addr;
5052
5053 /*
5054 * If the emulation is caused by #PF and it is non-page_table
5055 * writing instruction, it means the VM-EXIT is caused by shadow
5056 * page protected, we can zap the shadow page and retry this
5057 * instruction directly.
5058 *
5059 * Note: if the guest uses a non-page-table modifying instruction
5060 * on the PDE that points to the instruction, then we will unmap
5061 * the instruction and go to an infinite loop. So, we cache the
5062 * last retried eip and the last fault address, if we meet the eip
5063 * and the address again, we can break out of the potential infinite
5064 * loop.
5065 */
5066 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5067
5068 if (!(emulation_type & EMULTYPE_RETRY))
5069 return false;
5070
5071 if (x86_page_table_writing_insn(ctxt))
5072 return false;
5073
5074 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5075 return false;
5076
5077 vcpu->arch.last_retry_eip = ctxt->eip;
5078 vcpu->arch.last_retry_addr = cr2;
5079
5080 if (!vcpu->arch.mmu.direct_map)
5081 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5082
22368028 5083 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5084
5085 return true;
5086}
5087
716d51ab
GN		 5088static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5089static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5090
64d60670 5091static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5092{
64d60670 5093 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5094 /* This is a good place to trace that we are exiting SMM. */
5095 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5096
64d60670
PB		 5097 if (unlikely(vcpu->arch.smi_pending)) {
5098 kvm_make_request(KVM_REQ_SMI, vcpu);
5099 vcpu->arch.smi_pending = 0;
cd7764fe
PB		 5100 } else {
5101 /* Process a latched INIT, if any. */
5102 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670
PB		 5103 }
5104 }
699023e2
PB		 5105
5106 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5107}
5108
5109static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5110{
5111 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5112
a584539b 5113 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5114
5115 if (changed & HF_SMM_MASK)
5116 kvm_smm_changed(vcpu);
a584539b
PB		 5117}
5118
4a1e10d5
PB		 5119static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5120 unsigned long *db)
5121{
5122 u32 dr6 = 0;
5123 int i;
5124 u32 enable, rwlen;
5125
5126 enable = dr7;
5127 rwlen = dr7 >> 16;
5128 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5129 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5130 dr6 |= (1 << i);
5131 return dr6;
5132}
5133
6addfc42 5134static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5135{
5136 struct kvm_run *kvm_run = vcpu->run;
5137
5138 /*
6addfc42
PB		 5139 * rflags is the old, "raw" value of the flags. The new value has
5140 * not been saved yet.
663f4c61
PB		 5141 *
5142 * This is correct even for TF set by the guest, because "the
5143 * processor will not generate this exception after the instruction
5144 * that sets the TF flag".
5145 */
663f4c61
PB		 5146 if (unlikely(rflags & X86_EFLAGS_TF)) {
5147 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5148 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5149 DR6_RTM;
663f4c61
PB		 5150 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5151 kvm_run->debug.arch.exception = DB_VECTOR;
5152 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5153 *r = EMULATE_USER_EXIT;
5154 } else {
5155 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5156 /*
5157 * "Certain debug exceptions may clear bit 0-3. The
5158 * remaining contents of the DR6 register are never
5159 * cleared by the processor".
5160 */
5161 vcpu->arch.dr6 &= ~15;
6f43ed01 5162 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5163 kvm_queue_exception(vcpu, DB_VECTOR);
5164 }
5165 }
5166}
5167
4a1e10d5
PB		 5168static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5169{
4a1e10d5
PB		 5170 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5171 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5172 struct kvm_run *kvm_run = vcpu->run;
5173 unsigned long eip = kvm_get_linear_rip(vcpu);
5174 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5175 vcpu->arch.guest_debug_dr7,
5176 vcpu->arch.eff_db);
5177
5178 if (dr6 != 0) {
6f43ed01 5179 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5180 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5181 kvm_run->debug.arch.exception = DB_VECTOR;
5182 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5183 *r = EMULATE_USER_EXIT;
5184 return true;
5185 }
5186 }
5187
4161a569
NA		 5188 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5189 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5190 unsigned long eip = kvm_get_linear_rip(vcpu);
5191 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5192 vcpu->arch.dr7,
5193 vcpu->arch.db);
5194
5195 if (dr6 != 0) {
5196 vcpu->arch.dr6 &= ~15;
6f43ed01 5197 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5198 kvm_queue_exception(vcpu, DB_VECTOR);
5199 *r = EMULATE_DONE;
5200 return true;
5201 }
5202 }
5203
5204 return false;
5205}
5206
51d8b661
AP		 5207int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5208 unsigned long cr2,
dc25e89e
AP		 5209 int emulation_type,
5210 void *insn,
5211 int insn_len)
bbd9b64e 5212{
95cb2295 5213 int r;
9d74191a 5214 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5215 bool writeback = true;
93c05d3e 5216 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5217
93c05d3e
XG		 5218 /*
5219 * Clear write_fault_to_shadow_pgtable here to ensure it is
5220 * never reused.
5221 */
5222 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5223 kvm_clear_exception_queue(vcpu);
8d7d8102 5224
571008da 5225 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5226 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5227
5228 /*
5229 * We will reenter on the same instruction since
5230 * we do not set complete_userspace_io. This does not
5231 * handle watchpoints yet, those would be handled in
5232 * the emulate_ops.
5233 */
5234 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5235 return r;
5236
9d74191a
TY		 5237 ctxt->interruptibility = 0;
5238 ctxt->have_exception = false;
e0ad0b47 5239 ctxt->exception.vector = -1;
9d74191a 5240 ctxt->perm_ok = false;
bbd9b64e 5241
b51e974f 5242 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5243
9d74191a 5244 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5245
e46479f8 5246 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5247 ++vcpu->stat.insn_emulation;
1d2887e2 5248 if (r != EMULATION_OK) {
4005996e
AK		 5249 if (emulation_type & EMULTYPE_TRAP_UD)
5250 return EMULATE_FAIL;
991eebf9
GN		 5251 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5252 emulation_type))
bbd9b64e 5253 return EMULATE_DONE;
6d77dbfc
GN		 5254 if (emulation_type & EMULTYPE_SKIP)
5255 return EMULATE_FAIL;
5256 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5257 }
5258 }
5259
ba8afb6b 5260 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5261 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5262 if (ctxt->eflags & X86_EFLAGS_RF)
5263 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5264 return EMULATE_DONE;
5265 }
5266
1cb3f3ae
XG		 5267 if (retry_instruction(ctxt, cr2, emulation_type))
5268 return EMULATE_DONE;
5269
7ae441ea 5270 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5271 changes registers values during IO operation */
7ae441ea
GN		 5272 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5273 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5274 emulator_invalidate_register_cache(ctxt);
7ae441ea 5275 }
4d2179e1 5276
5cd21917 5277restart:
9d74191a 5278 r = x86_emulate_insn(ctxt);
bbd9b64e 5279
775fde86
JR		 5280 if (r == EMULATION_INTERCEPTED)
5281 return EMULATE_DONE;
5282
d2ddd1c4 5283 if (r == EMULATION_FAILED) {
991eebf9
GN		 5284 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5285 emulation_type))
c3cd7ffa
GN		 5286 return EMULATE_DONE;
5287
6d77dbfc 5288 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5289 }
5290
9d74191a 5291 if (ctxt->have_exception) {
d2ddd1c4 5292 r = EMULATE_DONE;
ef54bcfe
PB		 5293 if (inject_emulated_exception(vcpu))
5294 return r;
d2ddd1c4 5295 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5296 if (!vcpu->arch.pio.in) {
5297 /* FIXME: return into emulator if single-stepping. */
3457e419 5298 vcpu->arch.pio.count = 0;
0912c977 5299 } else {
7ae441ea 5300 writeback = false;
716d51ab
GN		 5301 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5302 }
ac0a48c3 5303 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5304 } else if (vcpu->mmio_needed) {
5305 if (!vcpu->mmio_is_write)
5306 writeback = false;
ac0a48c3 5307 r = EMULATE_USER_EXIT;
716d51ab 5308 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5309 } else if (r == EMULATION_RESTART)
5cd21917 5310 goto restart;
d2ddd1c4
GN		 5311 else
5312 r = EMULATE_DONE;
f850e2e6 5313
7ae441ea 5314 if (writeback) {
6addfc42 5315 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5316 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5317 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5318 if (vcpu->arch.hflags != ctxt->emul_flags)
5319 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5320 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5321 if (r == EMULATE_DONE)
6addfc42 5322 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5323 if (!ctxt->have_exception ||
5324 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5325 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5326
5327 /*
5328 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5329 * do nothing, and it will be requested again as soon as
5330 * the shadow expires. But we still need to check here,
5331 * because POPF has no interrupt shadow.
5332 */
5333 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5334 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5335 } else
5336 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5337
5338 return r;
de7d789a 5339}
51d8b661 5340EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5341
cf8f70bf 5342int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5343{
cf8f70bf 5344 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5345 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5346 size, port, &val, 1);
cf8f70bf 5347 /* do not return to emulator after return from userspace */
7972995b 5348 vcpu->arch.pio.count = 0;
de7d789a
CO		 5349 return ret;
5350}
cf8f70bf 5351EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5352
8cfdc000
ZA		 5353static void tsc_bad(void *info)
5354{
0a3aee0d 5355 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5356}
5357
5358static void tsc_khz_changed(void *data)
c8076604 5359{
8cfdc000
ZA		 5360 struct cpufreq_freqs *freq = data;
5361 unsigned long khz = 0;
5362
5363 if (data)
5364 khz = freq->new;
5365 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5366 khz = cpufreq_quick_get(raw_smp_processor_id());
5367 if (!khz)
5368 khz = tsc_khz;
0a3aee0d 5369 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5370}
5371
c8076604
GH		 5372static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5373 void *data)
5374{
5375 struct cpufreq_freqs *freq = data;
5376 struct kvm *kvm;
5377 struct kvm_vcpu *vcpu;
5378 int i, send_ipi = 0;
5379
8cfdc000
ZA		 5380 /*
5381 * We allow guests to temporarily run on slowing clocks,
5382 * provided we notify them after, or to run on accelerating
5383 * clocks, provided we notify them before. Thus time never
5384 * goes backwards.
5385 *
5386 * However, we have a problem. We can't atomically update
5387 * the frequency of a given CPU from this function; it is
5388 * merely a notifier, which can be called from any CPU.
5389 * Changing the TSC frequency at arbitrary points in time
5390 * requires a recomputation of local variables related to
5391 * the TSC for each VCPU. We must flag these local variables
5392 * to be updated and be sure the update takes place with the
5393 * new frequency before any guests proceed.
5394 *
5395 * Unfortunately, the combination of hotplug CPU and frequency
5396 * change creates an intractable locking scenario; the order
5397 * of when these callouts happen is undefined with respect to
5398 * CPU hotplug, and they can race with each other. As such,
5399 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5400 * undefined; you can actually have a CPU frequency change take
5401 * place in between the computation of X and the setting of the
5402 * variable. To protect against this problem, all updates of
5403 * the per_cpu tsc_khz variable are done in an interrupt
5404 * protected IPI, and all callers wishing to update the value
5405 * must wait for a synchronous IPI to complete (which is trivial
5406 * if the caller is on the CPU already). This establishes the
5407 * necessary total order on variable updates.
5408 *
5409 * Note that because a guest time update may take place
5410 * anytime after the setting of the VCPU's request bit, the
5411 * correct TSC value must be set before the request. However,
5412 * to ensure the update actually makes it to any guest which
5413 * starts running in hardware virtualization between the set
5414 * and the acquisition of the spinlock, we must also ping the
5415 * CPU after setting the request bit.
5416 *
5417 */
5418
c8076604
GH		 5419 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5420 return 0;
5421 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5422 return 0;
8cfdc000
ZA		 5423
5424 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5425
2f303b74 5426 spin_lock(&kvm_lock);
c8076604 5427 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5428 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5429 if (vcpu->cpu != freq->cpu)
5430 continue;
c285545f 5431 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5432 if (vcpu->cpu != smp_processor_id())
8cfdc000 5433 send_ipi = 1;
c8076604
GH		 5434 }
5435 }
2f303b74 5436 spin_unlock(&kvm_lock);
c8076604
GH		 5437
5438 if (freq->old < freq->new && send_ipi) {
5439 /*
5440 * We upscale the frequency. Must make the guest
5441 * doesn't see old kvmclock values while running with
5442 * the new frequency, otherwise we risk the guest sees
5443 * time go backwards.
5444 *
5445 * In case we update the frequency for another cpu
5446 * (which might be in guest context) send an interrupt
5447 * to kick the cpu out of guest context. Next time
5448 * guest context is entered kvmclock will be updated,
5449 * so the guest will not see stale values.
5450 */
8cfdc000 5451 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5452 }
5453 return 0;
5454}
5455
5456static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5457 .notifier_call = kvmclock_cpufreq_notifier
5458};
5459
5460static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5461 unsigned long action, void *hcpu)
5462{
5463 unsigned int cpu = (unsigned long)hcpu;
5464
5465 switch (action) {
5466 case CPU_ONLINE:
5467 case CPU_DOWN_FAILED:
5468 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5469 break;
5470 case CPU_DOWN_PREPARE:
5471 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5472 break;
5473 }
5474 return NOTIFY_OK;
5475}
5476
5477static struct notifier_block kvmclock_cpu_notifier_block = {
5478 .notifier_call = kvmclock_cpu_notifier,
5479 .priority = -INT_MAX
c8076604
GH		 5480};
5481
b820cc0c
ZA		 5482static void kvm_timer_init(void)
5483{
5484 int cpu;
5485
c285545f 5486 max_tsc_khz = tsc_khz;
460dd42e
SB		 5487
5488 cpu_notifier_register_begin();
b820cc0c 5489 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5490#ifdef CONFIG_CPU_FREQ
5491 struct cpufreq_policy policy;
5492 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5493 cpu = get_cpu();
5494 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5495 if (policy.cpuinfo.max_freq)
5496 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5497 put_cpu();
c285545f 5498#endif
b820cc0c
ZA		 5499 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5500 CPUFREQ_TRANSITION_NOTIFIER);
5501 }
c285545f 5502 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5503 for_each_online_cpu(cpu)
5504 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5505
5506 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5507 cpu_notifier_register_done();
5508
b820cc0c
ZA		 5509}
5510
ff9d07a0
ZY		 5511static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5512
f5132b01 5513int kvm_is_in_guest(void)
ff9d07a0 5514{
086c9855 5515 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5516}
5517
5518static int kvm_is_user_mode(void)
5519{
5520 int user_mode = 3;
dcf46b94 5521
086c9855
AS		 5522 if (__this_cpu_read(current_vcpu))
5523 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5524
ff9d07a0
ZY		 5525 return user_mode != 0;
5526}
5527
5528static unsigned long kvm_get_guest_ip(void)
5529{
5530 unsigned long ip = 0;
dcf46b94 5531
086c9855
AS		 5532 if (__this_cpu_read(current_vcpu))
5533 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5534
ff9d07a0
ZY		 5535 return ip;
5536}
5537
5538static struct perf_guest_info_callbacks kvm_guest_cbs = {
5539 .is_in_guest = kvm_is_in_guest,
5540 .is_user_mode = kvm_is_user_mode,
5541 .get_guest_ip = kvm_get_guest_ip,
5542};
5543
5544void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5545{
086c9855 5546 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5547}
5548EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5549
5550void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5551{
086c9855 5552 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5553}
5554EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5555
ce88decf
XG		 5556static void kvm_set_mmio_spte_mask(void)
5557{
5558 u64 mask;
5559 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5560
5561 /*
5562 * Set the reserved bits and the present bit of an paging-structure
5563 * entry to generate page fault with PFER.RSV = 1.
5564 */
885032b9 5565 /* Mask the reserved physical address bits. */
d1431483 5566 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5567
5568 /* Bit 62 is always reserved for 32bit host. */
5569 mask |= 0x3ull << 62;
5570
5571 /* Set the present bit. */
ce88decf
XG		 5572 mask |= 1ull;
5573
5574#ifdef CONFIG_X86_64
5575 /*
5576 * If reserved bit is not supported, clear the present bit to disable
5577 * mmio page fault.
5578 */
5579 if (maxphyaddr == 52)
5580 mask &= ~1ull;
5581#endif
5582
5583 kvm_mmu_set_mmio_spte_mask(mask);
5584}
5585
16e8d74d
MT		 5586#ifdef CONFIG_X86_64
5587static void pvclock_gtod_update_fn(struct work_struct *work)
5588{
d828199e
MT		 5589 struct kvm *kvm;
5590
5591 struct kvm_vcpu *vcpu;
5592 int i;
5593
2f303b74 5594 spin_lock(&kvm_lock);
d828199e
MT		 5595 list_for_each_entry(kvm, &vm_list, vm_list)
5596 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5597 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5598 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5599 spin_unlock(&kvm_lock);
16e8d74d
MT		 5600}
5601
5602static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5603
5604/*
5605 * Notification about pvclock gtod data update.
5606 */
5607static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5608 void *priv)
5609{
5610 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5611 struct timekeeper *tk = priv;
5612
5613 update_pvclock_gtod(tk);
5614
5615 /* disable master clock if host does not trust, or does not
5616 * use, TSC clocksource
5617 */
5618 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5619 atomic_read(&kvm_guest_has_master_clock) != 0)
5620 queue_work(system_long_wq, &pvclock_gtod_work);
5621
5622 return 0;
5623}
5624
5625static struct notifier_block pvclock_gtod_notifier = {
5626 .notifier_call = pvclock_gtod_notify,
5627};
5628#endif
5629
f8c16bba 5630int kvm_arch_init(void *opaque)
043405e1 5631{
b820cc0c 5632 int r;
6b61edf7 5633 struct kvm_x86_ops *ops = opaque;
f8c16bba 5634
f8c16bba
ZX		 5635 if (kvm_x86_ops) {
5636 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5637 r = -EEXIST;
5638 goto out;
f8c16bba
ZX		 5639 }
5640
5641 if (!ops->cpu_has_kvm_support()) {
5642 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5643 r = -EOPNOTSUPP;
5644 goto out;
f8c16bba
ZX		 5645 }
5646 if (ops->disabled_by_bios()) {
5647 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5648 r = -EOPNOTSUPP;
5649 goto out;
f8c16bba
ZX		 5650 }
5651
013f6a5d
MT		 5652 r = -ENOMEM;
5653 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5654 if (!shared_msrs) {
5655 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5656 goto out;
5657 }
5658
97db56ce
AK		 5659 r = kvm_mmu_module_init();
5660 if (r)
013f6a5d 5661 goto out_free_percpu;
97db56ce 5662
ce88decf 5663 kvm_set_mmio_spte_mask();
97db56ce 5664
f8c16bba 5665 kvm_x86_ops = ops;
920c8377 5666
7b52345e 5667 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5668 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5669
b820cc0c 5670 kvm_timer_init();
c8076604 5671
ff9d07a0
ZY		 5672 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5673
2acf923e
DC		 5674 if (cpu_has_xsave)
5675 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5676
c5cc421b 5677 kvm_lapic_init();
16e8d74d
MT		 5678#ifdef CONFIG_X86_64
5679 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5680#endif
5681
f8c16bba 5682 return 0;
56c6d28a 5683
013f6a5d
MT		 5684out_free_percpu:
5685 free_percpu(shared_msrs);
56c6d28a 5686out:
56c6d28a 5687 return r;
043405e1 5688}
8776e519 5689
f8c16bba
ZX		 5690void kvm_arch_exit(void)
5691{
ff9d07a0
ZY		 5692 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5693
888d256e
JK		 5694 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5695 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5696 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5697 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5698#ifdef CONFIG_X86_64
5699 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5700#endif
f8c16bba 5701 kvm_x86_ops = NULL;
56c6d28a 5702 kvm_mmu_module_exit();
013f6a5d 5703 free_percpu(shared_msrs);
56c6d28a 5704}
f8c16bba 5705
5cb56059 5706int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5707{
5708 ++vcpu->stat.halt_exits;
35754c98 5709 if (lapic_in_kernel(vcpu)) {
a4535290 5710 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5711 return 1;
5712 } else {
5713 vcpu->run->exit_reason = KVM_EXIT_HLT;
5714 return 0;
5715 }
5716}
5cb56059
JS		 5717EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5718
5719int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5720{
5721 kvm_x86_ops->skip_emulated_instruction(vcpu);
5722 return kvm_vcpu_halt(vcpu);
5723}
8776e519
HB		 5724EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5725
6aef266c
SV		 5726/*
5727 * kvm_pv_kick_cpu_op: Kick a vcpu.
5728 *
5729 * @apicid - apicid of vcpu to be kicked.
5730 */
5731static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5732{
24d2166b 5733 struct kvm_lapic_irq lapic_irq;
6aef266c 5734
24d2166b
R		 5735 lapic_irq.shorthand = 0;
5736 lapic_irq.dest_mode = 0;
5737 lapic_irq.dest_id = apicid;
93bbf0b8 5738 lapic_irq.msi_redir_hint = false;
6aef266c 5739
24d2166b 5740 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5741 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5742}
5743
8776e519
HB		 5744int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5745{
5746 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5747 int op_64_bit, r = 1;
8776e519 5748
5cb56059
JS		 5749 kvm_x86_ops->skip_emulated_instruction(vcpu);
5750
55cd8e5a
GN		 5751 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5752 return kvm_hv_hypercall(vcpu);
5753
5fdbf976
MT		 5754 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5755 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5756 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5757 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5758 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5759
229456fc 5760 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5761
a449c7aa
NA		 5762 op_64_bit = is_64_bit_mode(vcpu);
5763 if (!op_64_bit) {
8776e519
HB		 5764 nr &= 0xFFFFFFFF;
5765 a0 &= 0xFFFFFFFF;
5766 a1 &= 0xFFFFFFFF;
5767 a2 &= 0xFFFFFFFF;
5768 a3 &= 0xFFFFFFFF;
5769 }
5770
07708c4a
JK		 5771 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5772 ret = -KVM_EPERM;
5773 goto out;
5774 }
5775
8776e519 5776 switch (nr) {
b93463aa
AK		 5777 case KVM_HC_VAPIC_POLL_IRQ:
5778 ret = 0;
5779 break;
6aef266c
SV		 5780 case KVM_HC_KICK_CPU:
5781 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5782 ret = 0;
5783 break;
8776e519
HB		 5784 default:
5785 ret = -KVM_ENOSYS;
5786 break;
5787 }
07708c4a 5788out:
a449c7aa
NA		 5789 if (!op_64_bit)
5790 ret = (u32)ret;
5fdbf976 5791 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5792 ++vcpu->stat.hypercalls;
2f333bcb 5793 return r;
8776e519
HB		 5794}
5795EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5796
b6785def 5797static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5798{
d6aa1000 5799 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5800 char instruction[3];
5fdbf976 5801 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5802
8776e519 5803 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5804
9d74191a 5805 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5806}
5807
b6c7a5dc
HB		 5808/*
5809 * Check if userspace requested an interrupt window, and that the
5810 * interrupt window is open.
5811 *
5812 * No need to exit to userspace if we already have an interrupt queued.
5813 */
851ba692 5814static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5815{
1c1a9ce9
SR		 5816 if (!vcpu->run->request_interrupt_window || pic_in_kernel(vcpu->kvm))
5817 return false;
5818
5819 if (kvm_cpu_has_interrupt(vcpu))
5820 return false;
5821
5822 return (irqchip_split(vcpu->kvm)
5823 ? kvm_apic_accept_pic_intr(vcpu)
5824 : kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5825}
5826
851ba692 5827static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5828{
851ba692
AK		 5829 struct kvm_run *kvm_run = vcpu->run;
5830
91586a3b 5831 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 5832 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 5833 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5834 kvm_run->apic_base = kvm_get_apic_base(vcpu);
1c1a9ce9 5835 if (!irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5836 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5837 kvm_arch_interrupt_allowed(vcpu) &&
5838 !kvm_cpu_has_interrupt(vcpu) &&
5839 !kvm_event_needs_reinjection(vcpu);
1c1a9ce9
SR		 5840 else if (!pic_in_kernel(vcpu->kvm))
5841 kvm_run->ready_for_interrupt_injection =
5842 kvm_apic_accept_pic_intr(vcpu) &&
5843 !kvm_cpu_has_interrupt(vcpu);
5844 else
5845 kvm_run->ready_for_interrupt_injection = 1;
b6c7a5dc
HB		 5846}
5847
95ba8273
GN		 5848static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5849{
5850 int max_irr, tpr;
5851
5852 if (!kvm_x86_ops->update_cr8_intercept)
5853 return;
5854
88c808fd
AK		 5855 if (!vcpu->arch.apic)
5856 return;
5857
8db3baa2
GN		 5858 if (!vcpu->arch.apic->vapic_addr)
5859 max_irr = kvm_lapic_find_highest_irr(vcpu);
5860 else
5861 max_irr = -1;
95ba8273
GN		 5862
5863 if (max_irr != -1)
5864 max_irr >>= 4;
5865
5866 tpr = kvm_lapic_get_cr8(vcpu);
5867
5868 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5869}
5870
b6b8a145 5871static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 5872{
b6b8a145
JK		 5873 int r;
5874
95ba8273 5875 /* try to reinject previous events if any */
b59bb7bd 5876 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5877 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5878 vcpu->arch.exception.has_error_code,
5879 vcpu->arch.exception.error_code);
d6e8c854
NA		 5880
5881 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
5882 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
5883 X86_EFLAGS_RF);
5884
6bdf0662
NA		 5885 if (vcpu->arch.exception.nr == DB_VECTOR &&
5886 (vcpu->arch.dr7 & DR7_GD)) {
5887 vcpu->arch.dr7 &= ~DR7_GD;
5888 kvm_update_dr7(vcpu);
5889 }
5890
b59bb7bd
GN		 5891 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5892 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5893 vcpu->arch.exception.error_code,
5894 vcpu->arch.exception.reinject);
b6b8a145 5895 return 0;
b59bb7bd
GN		 5896 }
5897
95ba8273
GN		 5898 if (vcpu->arch.nmi_injected) {
5899 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 5900 return 0;
95ba8273
GN		 5901 }
5902
5903 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5904 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 5905 return 0;
5906 }
5907
5908 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5909 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5910 if (r != 0)
5911 return r;
95ba8273
GN		 5912 }
5913
5914 /* try to inject new event if pending */
5915 if (vcpu->arch.nmi_pending) {
5916 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5917 --vcpu->arch.nmi_pending;
95ba8273
GN		 5918 vcpu->arch.nmi_injected = true;
5919 kvm_x86_ops->set_nmi(vcpu);
5920 }
c7c9c56c 5921 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 5922 /*
5923 * Because interrupts can be injected asynchronously, we are
5924 * calling check_nested_events again here to avoid a race condition.
5925 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
5926 * proposal and current concerns. Perhaps we should be setting
5927 * KVM_REQ_EVENT only on certain events and not unconditionally?
5928 */
5929 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5930 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5931 if (r != 0)
5932 return r;
5933 }
95ba8273 5934 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5935 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5936 false);
5937 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5938 }
5939 }
b6b8a145 5940 return 0;
95ba8273
GN		 5941}
5942
7460fb4a
AK		 5943static void process_nmi(struct kvm_vcpu *vcpu)
5944{
5945 unsigned limit = 2;
5946
5947 /*
5948 * x86 is limited to one NMI running, and one NMI pending after it.
5949 * If an NMI is already in progress, limit further NMIs to just one.
5950 * Otherwise, allow two (and we'll inject the first one immediately).
5951 */
5952 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5953 limit = 1;
5954
5955 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5956 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5957 kvm_make_request(KVM_REQ_EVENT, vcpu);
5958}
5959
660a5d51
PB		 5960#define put_smstate(type, buf, offset, val) \
5961 *(type *)((buf) + (offset) - 0x7e00) = val
5962
5963static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
5964{
5965 u32 flags = 0;
5966 flags |= seg->g << 23;
5967 flags |= seg->db << 22;
5968 flags |= seg->l << 21;
5969 flags |= seg->avl << 20;
5970 flags |= seg->present << 15;
5971 flags |= seg->dpl << 13;
5972 flags |= seg->s << 12;
5973 flags |= seg->type << 8;
5974 return flags;
5975}
5976
5977static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
5978{
5979 struct kvm_segment seg;
5980 int offset;
5981
5982 kvm_get_segment(vcpu, &seg, n);
5983 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
5984
5985 if (n < 3)
5986 offset = 0x7f84 + n * 12;
5987 else
5988 offset = 0x7f2c + (n - 3) * 12;
5989
5990 put_smstate(u32, buf, offset + 8, seg.base);
5991 put_smstate(u32, buf, offset + 4, seg.limit);
5992 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
5993}
5994
efbb288a 5995#ifdef CONFIG_X86_64
660a5d51
PB		 5996static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
5997{
5998 struct kvm_segment seg;
5999 int offset;
6000 u16 flags;
6001
6002 kvm_get_segment(vcpu, &seg, n);
6003 offset = 0x7e00 + n * 16;
6004
6005 flags = process_smi_get_segment_flags(&seg) >> 8;
6006 put_smstate(u16, buf, offset, seg.selector);
6007 put_smstate(u16, buf, offset + 2, flags);
6008 put_smstate(u32, buf, offset + 4, seg.limit);
6009 put_smstate(u64, buf, offset + 8, seg.base);
6010}
efbb288a 6011#endif
660a5d51
PB		 6012
6013static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6014{
6015 struct desc_ptr dt;
6016 struct kvm_segment seg;
6017 unsigned long val;
6018 int i;
6019
6020 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6021 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6022 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6023 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6024
6025 for (i = 0; i < 8; i++)
6026 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6027
6028 kvm_get_dr(vcpu, 6, &val);
6029 put_smstate(u32, buf, 0x7fcc, (u32)val);
6030 kvm_get_dr(vcpu, 7, &val);
6031 put_smstate(u32, buf, 0x7fc8, (u32)val);
6032
6033 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6034 put_smstate(u32, buf, 0x7fc4, seg.selector);
6035 put_smstate(u32, buf, 0x7f64, seg.base);
6036 put_smstate(u32, buf, 0x7f60, seg.limit);
6037 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6038
6039 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6040 put_smstate(u32, buf, 0x7fc0, seg.selector);
6041 put_smstate(u32, buf, 0x7f80, seg.base);
6042 put_smstate(u32, buf, 0x7f7c, seg.limit);
6043 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6044
6045 kvm_x86_ops->get_gdt(vcpu, &dt);
6046 put_smstate(u32, buf, 0x7f74, dt.address);
6047 put_smstate(u32, buf, 0x7f70, dt.size);
6048
6049 kvm_x86_ops->get_idt(vcpu, &dt);
6050 put_smstate(u32, buf, 0x7f58, dt.address);
6051 put_smstate(u32, buf, 0x7f54, dt.size);
6052
6053 for (i = 0; i < 6; i++)
6054 process_smi_save_seg_32(vcpu, buf, i);
6055
6056 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6057
6058 /* revision id */
6059 put_smstate(u32, buf, 0x7efc, 0x00020000);
6060 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6061}
6062
6063static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6064{
6065#ifdef CONFIG_X86_64
6066 struct desc_ptr dt;
6067 struct kvm_segment seg;
6068 unsigned long val;
6069 int i;
6070
6071 for (i = 0; i < 16; i++)
6072 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6073
6074 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6075 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6076
6077 kvm_get_dr(vcpu, 6, &val);
6078 put_smstate(u64, buf, 0x7f68, val);
6079 kvm_get_dr(vcpu, 7, &val);
6080 put_smstate(u64, buf, 0x7f60, val);
6081
6082 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6083 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6084 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6085
6086 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6087
6088 /* revision id */
6089 put_smstate(u32, buf, 0x7efc, 0x00020064);
6090
6091 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6092
6093 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6094 put_smstate(u16, buf, 0x7e90, seg.selector);
6095 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6096 put_smstate(u32, buf, 0x7e94, seg.limit);
6097 put_smstate(u64, buf, 0x7e98, seg.base);
6098
6099 kvm_x86_ops->get_idt(vcpu, &dt);
6100 put_smstate(u32, buf, 0x7e84, dt.size);
6101 put_smstate(u64, buf, 0x7e88, dt.address);
6102
6103 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6104 put_smstate(u16, buf, 0x7e70, seg.selector);
6105 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6106 put_smstate(u32, buf, 0x7e74, seg.limit);
6107 put_smstate(u64, buf, 0x7e78, seg.base);
6108
6109 kvm_x86_ops->get_gdt(vcpu, &dt);
6110 put_smstate(u32, buf, 0x7e64, dt.size);
6111 put_smstate(u64, buf, 0x7e68, dt.address);
6112
6113 for (i = 0; i < 6; i++)
6114 process_smi_save_seg_64(vcpu, buf, i);
6115#else
6116 WARN_ON_ONCE(1);
6117#endif
6118}
6119
64d60670
PB		 6120static void process_smi(struct kvm_vcpu *vcpu)
6121{
660a5d51 6122 struct kvm_segment cs, ds;
18c3626e 6123 struct desc_ptr dt;
660a5d51
PB		 6124 char buf[512];
6125 u32 cr0;
6126
64d60670
PB		 6127 if (is_smm(vcpu)) {
6128 vcpu->arch.smi_pending = true;
6129 return;
6130 }
6131
660a5d51
PB		 6132 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6133 vcpu->arch.hflags |= HF_SMM_MASK;
6134 memset(buf, 0, 512);
6135 if (guest_cpuid_has_longmode(vcpu))
6136 process_smi_save_state_64(vcpu, buf);
6137 else
6138 process_smi_save_state_32(vcpu, buf);
6139
54bf36aa 6140 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6141
6142 if (kvm_x86_ops->get_nmi_mask(vcpu))
6143 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6144 else
6145 kvm_x86_ops->set_nmi_mask(vcpu, true);
6146
6147 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6148 kvm_rip_write(vcpu, 0x8000);
6149
6150 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6151 kvm_x86_ops->set_cr0(vcpu, cr0);
6152 vcpu->arch.cr0 = cr0;
6153
6154 kvm_x86_ops->set_cr4(vcpu, 0);
6155
18c3626e
PB		 6156 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6157 dt.address = dt.size = 0;
6158 kvm_x86_ops->set_idt(vcpu, &dt);
6159
660a5d51
PB		 6160 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6161
6162 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6163 cs.base = vcpu->arch.smbase;
6164
6165 ds.selector = 0;
6166 ds.base = 0;
6167
6168 cs.limit = ds.limit = 0xffffffff;
6169 cs.type = ds.type = 0x3;
6170 cs.dpl = ds.dpl = 0;
6171 cs.db = ds.db = 0;
6172 cs.s = ds.s = 1;
6173 cs.l = ds.l = 0;
6174 cs.g = ds.g = 1;
6175 cs.avl = ds.avl = 0;
6176 cs.present = ds.present = 1;
6177 cs.unusable = ds.unusable = 0;
6178 cs.padding = ds.padding = 0;
6179
6180 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6181 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6182 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6183 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6184 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6185 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6186
6187 if (guest_cpuid_has_longmode(vcpu))
6188 kvm_x86_ops->set_efer(vcpu, 0);
6189
6190 kvm_update_cpuid(vcpu);
6191 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6192}
6193
3d81bc7e 6194static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6195{
3d81bc7e
YZ		 6196 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6197 return;
c7c9c56c 6198
3bb345f3 6199 memset(vcpu->arch.eoi_exit_bitmap, 0, 256 / 8);
c7c9c56c 6200
b053b2ae
SR		 6201 if (irqchip_split(vcpu->kvm))
6202 kvm_scan_ioapic_routes(vcpu, vcpu->arch.eoi_exit_bitmap);
db2bdcbb
RK		 6203 else {
6204 kvm_x86_ops->sync_pir_to_irr(vcpu);
b053b2ae 6205 kvm_ioapic_scan_entry(vcpu, vcpu->arch.eoi_exit_bitmap);
db2bdcbb 6206 }
3bb345f3 6207 kvm_x86_ops->load_eoi_exitmap(vcpu);
c7c9c56c
YZ		 6208}
6209
a70656b6
RK		 6210static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6211{
6212 ++vcpu->stat.tlb_flush;
6213 kvm_x86_ops->tlb_flush(vcpu);
6214}
6215
4256f43f
TC		 6216void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6217{
c24ae0dc
TC		 6218 struct page *page = NULL;
6219
35754c98 6220 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6221 return;
6222
4256f43f
TC		 6223 if (!kvm_x86_ops->set_apic_access_page_addr)
6224 return;
6225
c24ae0dc 6226 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6227 if (is_error_page(page))
6228 return;
c24ae0dc
TC		 6229 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6230
6231 /*
6232 * Do not pin apic access page in memory, the MMU notifier
6233 * will call us again if it is migrated or swapped out.
6234 */
6235 put_page(page);
4256f43f
TC		 6236}
6237EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6238
fe71557a
TC		 6239void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6240 unsigned long address)
6241{
c24ae0dc
TC		 6242 /*
6243 * The physical address of apic access page is stored in the VMCS.
6244 * Update it when it becomes invalid.
6245 */
6246 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6247 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6248}
6249
9357d939 6250/*
362c698f 6251 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6252 * exiting to the userspace. Otherwise, the value will be returned to the
6253 * userspace.
6254 */
851ba692 6255static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6256{
6257 int r;
35754c98 6258 bool req_int_win = !lapic_in_kernel(vcpu) &&
851ba692 6259 vcpu->run->request_interrupt_window;
730dca42 6260 bool req_immediate_exit = false;
b6c7a5dc 6261
3e007509 6262 if (vcpu->requests) {
a8eeb04a 6263 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6264 kvm_mmu_unload(vcpu);
a8eeb04a 6265 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6266 __kvm_migrate_timers(vcpu);
d828199e
MT		 6267 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6268 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6269 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6270 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6271 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6272 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6273 if (unlikely(r))
6274 goto out;
6275 }
a8eeb04a 6276 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6277 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6278 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6279 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6280 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6281 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6282 r = 0;
6283 goto out;
6284 }
a8eeb04a 6285 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6286 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6287 r = 0;
6288 goto out;
6289 }
a8eeb04a 6290 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6291 vcpu->fpu_active = 0;
6292 kvm_x86_ops->fpu_deactivate(vcpu);
6293 }
af585b92
GN		 6294 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6295 /* Page is swapped out. Do synthetic halt */
6296 vcpu->arch.apf.halted = true;
6297 r = 1;
6298 goto out;
6299 }
c9aaa895
GC		 6300 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6301 record_steal_time(vcpu);
64d60670
PB		 6302 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6303 process_smi(vcpu);
7460fb4a
AK		 6304 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6305 process_nmi(vcpu);
f5132b01 6306 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6307 kvm_pmu_handle_event(vcpu);
f5132b01 6308 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6309 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6310 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6311 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6312 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6313 (void *) vcpu->arch.eoi_exit_bitmap)) {
6314 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6315 vcpu->run->eoi.vector =
6316 vcpu->arch.pending_ioapic_eoi;
6317 r = 0;
6318 goto out;
6319 }
6320 }
3d81bc7e
YZ		 6321 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6322 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6323 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6324 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6325 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6326 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6327 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6328 r = 0;
6329 goto out;
6330 }
e516cebb
AS		 6331 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6332 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6333 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6334 r = 0;
6335 goto out;
6336 }
2f52d58c 6337 }
b93463aa 6338
bf9f6ac8
FW		 6339 /*
6340 * KVM_REQ_EVENT is not set when posted interrupts are set by
6341 * VT-d hardware, so we have to update RVI unconditionally.
6342 */
6343 if (kvm_lapic_enabled(vcpu)) {
6344 /*
6345 * Update architecture specific hints for APIC
6346 * virtual interrupt delivery.
6347 */
6348 if (kvm_x86_ops->hwapic_irr_update)
6349 kvm_x86_ops->hwapic_irr_update(vcpu,
6350 kvm_lapic_find_highest_irr(vcpu));
6351 }
6352
b463a6f7 6353 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6354 kvm_apic_accept_events(vcpu);
6355 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6356 r = 1;
6357 goto out;
6358 }
6359
b6b8a145
JK		 6360 if (inject_pending_event(vcpu, req_int_win) != 0)
6361 req_immediate_exit = true;
b463a6f7 6362 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6363 else if (vcpu->arch.nmi_pending)
c9a7953f 6364 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6365 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6366 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6367
6368 if (kvm_lapic_enabled(vcpu)) {
6369 update_cr8_intercept(vcpu);
6370 kvm_lapic_sync_to_vapic(vcpu);
6371 }
6372 }
6373
d8368af8
AK		 6374 r = kvm_mmu_reload(vcpu);
6375 if (unlikely(r)) {
d905c069 6376 goto cancel_injection;
d8368af8
AK		 6377 }
6378
b6c7a5dc
HB		 6379 preempt_disable();
6380
6381 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6382 if (vcpu->fpu_active)
6383 kvm_load_guest_fpu(vcpu);
2acf923e 6384 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6385
6b7e2d09
XG		 6386 vcpu->mode = IN_GUEST_MODE;
6387
01b71917
MT		 6388 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6389
6b7e2d09
XG		 6390 /* We should set ->mode before check ->requests,
6391 * see the comment in make_all_cpus_request.
6392 */
01b71917 6393 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6394
d94e1dc9 6395 local_irq_disable();
32f88400 6396
6b7e2d09 6397 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6398 || need_resched() || signal_pending(current)) {
6b7e2d09 6399 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6400 smp_wmb();
6c142801
AK		 6401 local_irq_enable();
6402 preempt_enable();
01b71917 6403 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6404 r = 1;
d905c069 6405 goto cancel_injection;
6c142801
AK		 6406 }
6407
d6185f20
NHE		 6408 if (req_immediate_exit)
6409 smp_send_reschedule(vcpu->cpu);
6410
ccf73aaf 6411 __kvm_guest_enter();
b6c7a5dc 6412
42dbaa5a 6413 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6414 set_debugreg(0, 7);
6415 set_debugreg(vcpu->arch.eff_db[0], 0);
6416 set_debugreg(vcpu->arch.eff_db[1], 1);
6417 set_debugreg(vcpu->arch.eff_db[2], 2);
6418 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6419 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6420 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6421 }
b6c7a5dc 6422
229456fc 6423 trace_kvm_entry(vcpu->vcpu_id);
d0659d94 6424 wait_lapic_expire(vcpu);
851ba692 6425 kvm_x86_ops->run(vcpu);
b6c7a5dc 6426
c77fb5fe
PB		 6427 /*
6428 * Do this here before restoring debug registers on the host. And
6429 * since we do this before handling the vmexit, a DR access vmexit
6430 * can (a) read the correct value of the debug registers, (b) set
6431 * KVM_DEBUGREG_WONT_EXIT again.
6432 */
6433 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6434 int i;
6435
6436 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6437 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6438 for (i = 0; i < KVM_NR_DB_REGS; i++)
6439 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6440 }
6441
24f1e32c
FW		 6442 /*
6443 * If the guest has used debug registers, at least dr7
6444 * will be disabled while returning to the host.
6445 * If we don't have active breakpoints in the host, we don't
6446 * care about the messed up debug address registers. But if
6447 * we have some of them active, restore the old state.
6448 */
59d8eb53 6449 if (hw_breakpoint_active())
24f1e32c 6450 hw_breakpoint_restore();
42dbaa5a 6451
886b470c 6452 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
4ea1636b 6453 rdtsc());
1d5f066e 6454
6b7e2d09 6455 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6456 smp_wmb();
a547c6db
YZ		 6457
6458 /* Interrupt is enabled by handle_external_intr() */
6459 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6460
6461 ++vcpu->stat.exits;
6462
6463 /*
6464 * We must have an instruction between local_irq_enable() and
6465 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6466 * the interrupt shadow. The stat.exits increment will do nicely.
6467 * But we need to prevent reordering, hence this barrier():
6468 */
6469 barrier();
6470
6471 kvm_guest_exit();
6472
6473 preempt_enable();
6474
f656ce01 6475 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6476
b6c7a5dc
HB		 6477 /*
6478 * Profile KVM exit RIPs:
6479 */
6480 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6481 unsigned long rip = kvm_rip_read(vcpu);
6482 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6483 }
6484
cc578287
ZA		 6485 if (unlikely(vcpu->arch.tsc_always_catchup))
6486 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6487
5cfb1d5a
MT		 6488 if (vcpu->arch.apic_attention)
6489 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6490
851ba692 6491 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6492 return r;
6493
6494cancel_injection:
6495 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6496 if (unlikely(vcpu->arch.apic_attention))
6497 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6498out:
6499 return r;
6500}
b6c7a5dc 6501
362c698f
PB		 6502static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6503{
bf9f6ac8
FW		 6504 if (!kvm_arch_vcpu_runnable(vcpu) &&
6505 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6506 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6507 kvm_vcpu_block(vcpu);
6508 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6509
6510 if (kvm_x86_ops->post_block)
6511 kvm_x86_ops->post_block(vcpu);
6512
9c8fd1ba
PB		 6513 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6514 return 1;
6515 }
362c698f
PB		 6516
6517 kvm_apic_accept_events(vcpu);
6518 switch(vcpu->arch.mp_state) {
6519 case KVM_MP_STATE_HALTED:
6520 vcpu->arch.pv.pv_unhalted = false;
6521 vcpu->arch.mp_state =
6522 KVM_MP_STATE_RUNNABLE;
6523 case KVM_MP_STATE_RUNNABLE:
6524 vcpu->arch.apf.halted = false;
6525 break;
6526 case KVM_MP_STATE_INIT_RECEIVED:
6527 break;
6528 default:
6529 return -EINTR;
6530 break;
6531 }
6532 return 1;
6533}
09cec754 6534
5d9bc648
PB		 6535static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6536{
6537 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6538 !vcpu->arch.apf.halted);
6539}
6540
362c698f 6541static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6542{
6543 int r;
f656ce01 6544 struct kvm *kvm = vcpu->kvm;
d7690175 6545
f656ce01 6546 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6547
362c698f 6548 for (;;) {
58f800d5 6549 if (kvm_vcpu_running(vcpu)) {
851ba692 6550 r = vcpu_enter_guest(vcpu);
bf9f6ac8 6551 } else {
362c698f 6552 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 6553 }
6554
09cec754
GN		 6555 if (r <= 0)
6556 break;
6557
6558 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6559 if (kvm_cpu_has_pending_timer(vcpu))
6560 kvm_inject_pending_timer_irqs(vcpu);
6561
851ba692 6562 if (dm_request_for_irq_injection(vcpu)) {
4ca7dd8c
PB		 6563 r = 0;
6564 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 6565 ++vcpu->stat.request_irq_exits;
362c698f 6566 break;
09cec754 6567 }
af585b92
GN		 6568
6569 kvm_check_async_pf_completion(vcpu);
6570
09cec754
GN		 6571 if (signal_pending(current)) {
6572 r = -EINTR;
851ba692 6573 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6574 ++vcpu->stat.signal_exits;
362c698f 6575 break;
09cec754
GN		 6576 }
6577 if (need_resched()) {
f656ce01 6578 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6579 cond_resched();
f656ce01 6580 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6581 }
b6c7a5dc
HB		 6582 }
6583
f656ce01 6584 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6585
6586 return r;
6587}
6588
716d51ab
GN		 6589static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6590{
6591 int r;
6592 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6593 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6594 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6595 if (r != EMULATE_DONE)
6596 return 0;
6597 return 1;
6598}
6599
6600static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6601{
6602 BUG_ON(!vcpu->arch.pio.count);
6603
6604 return complete_emulated_io(vcpu);
6605}
6606
f78146b0
AK		 6607/*
6608 * Implements the following, as a state machine:
6609 *
6610 * read:
6611 * for each fragment
87da7e66
XG		 6612 * for each mmio piece in the fragment
6613 * write gpa, len
6614 * exit
6615 * copy data
f78146b0
AK		 6616 * execute insn
6617 *
6618 * write:
6619 * for each fragment
87da7e66
XG		 6620 * for each mmio piece in the fragment
6621 * write gpa, len
6622 * copy data
6623 * exit
f78146b0 6624 */
716d51ab 6625static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6626{
6627 struct kvm_run *run = vcpu->run;
f78146b0 6628 struct kvm_mmio_fragment *frag;
87da7e66 6629 unsigned len;
5287f194 6630
716d51ab 6631 BUG_ON(!vcpu->mmio_needed);
5287f194 6632
716d51ab 6633 /* Complete previous fragment */
87da7e66
XG		 6634 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6635 len = min(8u, frag->len);
716d51ab 6636 if (!vcpu->mmio_is_write)
87da7e66
XG		 6637 memcpy(frag->data, run->mmio.data, len);
6638
6639 if (frag->len <= 8) {
6640 /* Switch to the next fragment. */
6641 frag++;
6642 vcpu->mmio_cur_fragment++;
6643 } else {
6644 /* Go forward to the next mmio piece. */
6645 frag->data += len;
6646 frag->gpa += len;
6647 frag->len -= len;
6648 }
6649
a08d3b3b 6650 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6651 vcpu->mmio_needed = 0;
0912c977
PB		 6652
6653 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6654 if (vcpu->mmio_is_write)
716d51ab
GN		 6655 return 1;
6656 vcpu->mmio_read_completed = 1;
6657 return complete_emulated_io(vcpu);
6658 }
87da7e66 6659
716d51ab
GN		 6660 run->exit_reason = KVM_EXIT_MMIO;
6661 run->mmio.phys_addr = frag->gpa;
6662 if (vcpu->mmio_is_write)
87da7e66
XG		 6663 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6664 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6665 run->mmio.is_write = vcpu->mmio_is_write;
6666 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6667 return 0;
5287f194
AK		 6668}
6669
716d51ab 6670
b6c7a5dc
HB		 6671int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6672{
c5bedc68 6673 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6674 int r;
6675 sigset_t sigsaved;
6676
c4d72e2d 6677 fpu__activate_curr(fpu);
e5c30142 6678
ac9f6dc0
AK		 6679 if (vcpu->sigset_active)
6680 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6681
a4535290 6682 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6683 kvm_vcpu_block(vcpu);
66450a21 6684 kvm_apic_accept_events(vcpu);
d7690175 6685 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6686 r = -EAGAIN;
6687 goto out;
b6c7a5dc
HB		 6688 }
6689
b6c7a5dc 6690 /* re-sync apic's tpr */
35754c98 6691 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 6692 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6693 r = -EINVAL;
6694 goto out;
6695 }
6696 }
b6c7a5dc 6697
716d51ab
GN		 6698 if (unlikely(vcpu->arch.complete_userspace_io)) {
6699 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6700 vcpu->arch.complete_userspace_io = NULL;
6701 r = cui(vcpu);
6702 if (r <= 0)
6703 goto out;
6704 } else
6705 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6706
362c698f 6707 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6708
6709out:
f1d86e46 6710 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6711 if (vcpu->sigset_active)
6712 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6713
b6c7a5dc
HB		 6714 return r;
6715}
6716
6717int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6718{
7ae441ea
GN		 6719 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6720 /*
6721 * We are here if userspace calls get_regs() in the middle of
6722 * instruction emulation. Registers state needs to be copied
4a969980 6723 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6724 * that usually, but some bad designed PV devices (vmware
6725 * backdoor interface) need this to work
6726 */
dd856efa 6727 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6728 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6729 }
5fdbf976
MT		 6730 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6731 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6732 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6733 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6734 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6735 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6736 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6737 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6738#ifdef CONFIG_X86_64
5fdbf976
MT		 6739 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6740 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6741 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6742 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6743 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6744 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6745 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6746 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6747#endif
6748
5fdbf976 6749 regs->rip = kvm_rip_read(vcpu);
91586a3b 6750 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6751
b6c7a5dc
HB		 6752 return 0;
6753}
6754
6755int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6756{
7ae441ea
GN		 6757 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6758 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6759
5fdbf976
MT		 6760 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6761 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6762 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6763 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6764 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6765 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6766 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6767 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6768#ifdef CONFIG_X86_64
5fdbf976
MT		 6769 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6770 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6771 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6772 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6773 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6774 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6775 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6776 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6777#endif
6778
5fdbf976 6779 kvm_rip_write(vcpu, regs->rip);
91586a3b 6780 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6781
b4f14abd
JK		 6782 vcpu->arch.exception.pending = false;
6783
3842d135
AK		 6784 kvm_make_request(KVM_REQ_EVENT, vcpu);
6785
b6c7a5dc
HB		 6786 return 0;
6787}
6788
b6c7a5dc
HB		 6789void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6790{
6791 struct kvm_segment cs;
6792
3e6e0aab 6793 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6794 *db = cs.db;
6795 *l = cs.l;
6796}
6797EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6798
6799int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6800 struct kvm_sregs *sregs)
6801{
89a27f4d 6802 struct desc_ptr dt;
b6c7a5dc 6803
3e6e0aab
GT		 6804 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6805 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6806 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6807 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6808 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6809 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6810
3e6e0aab
GT		 6811 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6812 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6813
6814 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6815 sregs->idt.limit = dt.size;
6816 sregs->idt.base = dt.address;
b6c7a5dc 6817 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6818 sregs->gdt.limit = dt.size;
6819 sregs->gdt.base = dt.address;
b6c7a5dc 6820
4d4ec087 6821 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6822 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6823 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6824 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6825 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6826 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6827 sregs->apic_base = kvm_get_apic_base(vcpu);
6828
923c61bb 6829 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6830
36752c9b 6831 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6832 set_bit(vcpu->arch.interrupt.nr,
6833 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6834
b6c7a5dc
HB		 6835 return 0;
6836}
6837
62d9f0db
MT		 6838int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6839 struct kvm_mp_state *mp_state)
6840{
66450a21 6841 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6842 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6843 vcpu->arch.pv.pv_unhalted)
6844 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6845 else
6846 mp_state->mp_state = vcpu->arch.mp_state;
6847
62d9f0db
MT		 6848 return 0;
6849}
6850
6851int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6852 struct kvm_mp_state *mp_state)
6853{
66450a21
JK		 6854 if (!kvm_vcpu_has_lapic(vcpu) &&
6855 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6856 return -EINVAL;
6857
6858 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6859 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6860 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6861 } else
6862 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6863 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6864 return 0;
6865}
6866
7f3d35fd
KW		 6867int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6868 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6869{
9d74191a 6870 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6871 int ret;
e01c2426 6872
8ec4722d 6873 init_emulate_ctxt(vcpu);
c697518a 6874
7f3d35fd 6875 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6876 has_error_code, error_code);
c697518a 6877
c697518a 6878 if (ret)
19d04437 6879 return EMULATE_FAIL;
37817f29 6880
9d74191a
TY		 6881 kvm_rip_write(vcpu, ctxt->eip);
6882 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6883 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6884 return EMULATE_DONE;
37817f29
IE		 6885}
6886EXPORT_SYMBOL_GPL(kvm_task_switch);
6887
b6c7a5dc
HB		 6888int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6889 struct kvm_sregs *sregs)
6890{
58cb628d 6891 struct msr_data apic_base_msr;
b6c7a5dc 6892 int mmu_reset_needed = 0;
63f42e02 6893 int pending_vec, max_bits, idx;
89a27f4d 6894 struct desc_ptr dt;
b6c7a5dc 6895
6d1068b3
PM		 6896 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6897 return -EINVAL;
6898
89a27f4d
GN		 6899 dt.size = sregs->idt.limit;
6900 dt.address = sregs->idt.base;
b6c7a5dc 6901 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6902 dt.size = sregs->gdt.limit;
6903 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6904 kvm_x86_ops->set_gdt(vcpu, &dt);
6905
ad312c7c 6906 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6907 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6908 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6909 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6910
2d3ad1f4 6911 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6912
f6801dff 6913 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6914 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6915 apic_base_msr.data = sregs->apic_base;
6916 apic_base_msr.host_initiated = true;
6917 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6918
4d4ec087 6919 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6920 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6921 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6922
fc78f519 6923 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6924 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6925 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6926 kvm_update_cpuid(vcpu);
63f42e02
XG		 6927
6928 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6929 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6930 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6931 mmu_reset_needed = 1;
6932 }
63f42e02 6933 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6934
6935 if (mmu_reset_needed)
6936 kvm_mmu_reset_context(vcpu);
6937
a50abc3b 6938 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6939 pending_vec = find_first_bit(
6940 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6941 if (pending_vec < max_bits) {
66fd3f7f 6942 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6943 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6944 }
6945
3e6e0aab
GT		 6946 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6947 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6948 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6949 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6950 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6951 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6952
3e6e0aab
GT		 6953 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6954 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6955
5f0269f5
ME		 6956 update_cr8_intercept(vcpu);
6957
9c3e4aab 6958 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6959 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6960 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6961 !is_protmode(vcpu))
9c3e4aab
MT		 6962 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6963
3842d135
AK		 6964 kvm_make_request(KVM_REQ_EVENT, vcpu);
6965
b6c7a5dc
HB		 6966 return 0;
6967}
6968
d0bfb940
JK		 6969int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6970 struct kvm_guest_debug *dbg)
b6c7a5dc 6971{
355be0b9 6972 unsigned long rflags;
ae675ef0 6973 int i, r;
b6c7a5dc 6974
4f926bf2
JK		 6975 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6976 r = -EBUSY;
6977 if (vcpu->arch.exception.pending)
2122ff5e 6978 goto out;
4f926bf2
JK		 6979 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6980 kvm_queue_exception(vcpu, DB_VECTOR);
6981 else
6982 kvm_queue_exception(vcpu, BP_VECTOR);
6983 }
6984
91586a3b
JK		 6985 /*
6986 * Read rflags as long as potentially injected trace flags are still
6987 * filtered out.
6988 */
6989 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6990
6991 vcpu->guest_debug = dbg->control;
6992 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6993 vcpu->guest_debug = 0;
6994
6995 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6996 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6997 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6998 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6999 } else {
7000 for (i = 0; i < KVM_NR_DB_REGS; i++)
7001 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7002 }
c8639010 7003 kvm_update_dr7(vcpu);
ae675ef0 7004
f92653ee
JK		 7005 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7006 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7007 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7008
91586a3b
JK		 7009 /*
7010 * Trigger an rflags update that will inject or remove the trace
7011 * flags.
7012 */
7013 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7014
c8639010 7015 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 7016
4f926bf2 7017 r = 0;
d0bfb940 7018
2122ff5e 7019out:
b6c7a5dc
HB		 7020
7021 return r;
7022}
7023
8b006791
ZX		 7024/*
7025 * Translate a guest virtual address to a guest physical address.
7026 */
7027int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7028 struct kvm_translation *tr)
7029{
7030 unsigned long vaddr = tr->linear_address;
7031 gpa_t gpa;
f656ce01 7032 int idx;
8b006791 7033
f656ce01 7034 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7035 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7036 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7037 tr->physical_address = gpa;
7038 tr->valid = gpa != UNMAPPED_GVA;
7039 tr->writeable = 1;
7040 tr->usermode = 0;
8b006791
ZX		 7041
7042 return 0;
7043}
7044
d0752060
HB		 7045int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7046{
c47ada30 7047 struct fxregs_state *fxsave =
7366ed77 7048 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7049
d0752060
HB		 7050 memcpy(fpu->fpr, fxsave->st_space, 128);
7051 fpu->fcw = fxsave->cwd;
7052 fpu->fsw = fxsave->swd;
7053 fpu->ftwx = fxsave->twd;
7054 fpu->last_opcode = fxsave->fop;
7055 fpu->last_ip = fxsave->rip;
7056 fpu->last_dp = fxsave->rdp;
7057 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7058
d0752060
HB		 7059 return 0;
7060}
7061
7062int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7063{
c47ada30 7064 struct fxregs_state *fxsave =
7366ed77 7065 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7066
d0752060
HB		 7067 memcpy(fxsave->st_space, fpu->fpr, 128);
7068 fxsave->cwd = fpu->fcw;
7069 fxsave->swd = fpu->fsw;
7070 fxsave->twd = fpu->ftwx;
7071 fxsave->fop = fpu->last_opcode;
7072 fxsave->rip = fpu->last_ip;
7073 fxsave->rdp = fpu->last_dp;
7074 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7075
d0752060
HB		 7076 return 0;
7077}
7078
0ee6a517 7079static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7080{
bf935b0b 7081 fpstate_init(&vcpu->arch.guest_fpu.state);
df1daba7 7082 if (cpu_has_xsaves)
7366ed77 7083 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7084 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7085
2acf923e
DC		 7086 /*
7087 * Ensure guest xcr0 is valid for loading
7088 */
7089 vcpu->arch.xcr0 = XSTATE_FP;
7090
ad312c7c 7091 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7092}
d0752060
HB		 7093
7094void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7095{
2608d7a1 7096 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7097 return;
7098
2acf923e
DC		 7099 /*
7100 * Restore all possible states in the guest,
7101 * and assume host would use all available bits.
7102 * Guest xcr0 would be loaded later.
7103 */
7104 kvm_put_guest_xcr0(vcpu);
d0752060 7105 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7106 __kernel_fpu_begin();
003e2e8b 7107 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7108 trace_kvm_fpu(1);
d0752060 7109}
d0752060
HB		 7110
7111void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7112{
2acf923e
DC		 7113 kvm_put_guest_xcr0(vcpu);
7114
653f52c3
RR		 7115 if (!vcpu->guest_fpu_loaded) {
7116 vcpu->fpu_counter = 0;
d0752060 7117 return;
653f52c3 7118 }
d0752060
HB		 7119
7120 vcpu->guest_fpu_loaded = 0;
4f836347 7121 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7122 __kernel_fpu_end();
f096ed85 7123 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7124 /*
7125 * If using eager FPU mode, or if the guest is a frequent user
7126 * of the FPU, just leave the FPU active for next time.
7127 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7128 * the FPU in bursts will revert to loading it on demand.
7129 */
a9b4fb7e 7130 if (!vcpu->arch.eager_fpu) {
653f52c3
RR		 7131 if (++vcpu->fpu_counter < 5)
7132 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7133 }
0c04851c 7134 trace_kvm_fpu(0);
d0752060 7135}
e9b11c17
ZX		 7136
7137void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7138{
12f9a48f 7139 kvmclock_reset(vcpu);
7f1ea208 7140
f5f48ee1 7141 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7142 kvm_x86_ops->vcpu_free(vcpu);
7143}
7144
7145struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7146 unsigned int id)
7147{
c447e76b
LL		 7148 struct kvm_vcpu *vcpu;
7149
6755bae8
ZA		 7150 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7151 printk_once(KERN_WARNING
7152 "kvm: SMP vm created on host with unstable TSC; "
7153 "guest TSC will not be reliable\n");
c447e76b
LL		 7154
7155 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7156
c447e76b 7157 return vcpu;
26e5215f 7158}
e9b11c17 7159
26e5215f
AK		 7160int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7161{
7162 int r;
e9b11c17 7163
19efffa2 7164 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7165 r = vcpu_load(vcpu);
7166 if (r)
7167 return r;
d28bc9dd 7168 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7169 kvm_mmu_setup(vcpu);
e9b11c17 7170 vcpu_put(vcpu);
26e5215f 7171 return r;
e9b11c17
ZX		 7172}
7173
31928aa5 7174void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7175{
8fe8ab46 7176 struct msr_data msr;
332967a3 7177 struct kvm *kvm = vcpu->kvm;
42897d86 7178
31928aa5
DD		 7179 if (vcpu_load(vcpu))
7180 return;
8fe8ab46
WA		 7181 msr.data = 0x0;
7182 msr.index = MSR_IA32_TSC;
7183 msr.host_initiated = true;
7184 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7185 vcpu_put(vcpu);
7186
630994b3
MT		 7187 if (!kvmclock_periodic_sync)
7188 return;
7189
332967a3
AJ		 7190 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7191 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7192}
7193
d40ccc62 7194void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7195{
9fc77441 7196 int r;
344d9588
GN		 7197 vcpu->arch.apf.msr_val = 0;
7198
9fc77441
MT		 7199 r = vcpu_load(vcpu);
7200 BUG_ON(r);
e9b11c17
ZX		 7201 kvm_mmu_unload(vcpu);
7202 vcpu_put(vcpu);
7203
7204 kvm_x86_ops->vcpu_free(vcpu);
7205}
7206
d28bc9dd 7207void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7208{
e69fab5d
PB		 7209 vcpu->arch.hflags = 0;
7210
7460fb4a
AK		 7211 atomic_set(&vcpu->arch.nmi_queued, 0);
7212 vcpu->arch.nmi_pending = 0;
448fa4a9 7213 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7214 kvm_clear_interrupt_queue(vcpu);
7215 kvm_clear_exception_queue(vcpu);
448fa4a9 7216
42dbaa5a 7217 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7218 kvm_update_dr0123(vcpu);
6f43ed01 7219 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7220 kvm_update_dr6(vcpu);
42dbaa5a 7221 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7222 kvm_update_dr7(vcpu);
42dbaa5a 7223
1119022c
NA		 7224 vcpu->arch.cr2 = 0;
7225
3842d135 7226 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7227 vcpu->arch.apf.msr_val = 0;
c9aaa895 7228 vcpu->arch.st.msr_val = 0;
3842d135 7229
12f9a48f
GC		 7230 kvmclock_reset(vcpu);
7231
af585b92
GN		 7232 kvm_clear_async_pf_completion_queue(vcpu);
7233 kvm_async_pf_hash_reset(vcpu);
7234 vcpu->arch.apf.halted = false;
3842d135 7235
64d60670 7236 if (!init_event) {
d28bc9dd 7237 kvm_pmu_reset(vcpu);
64d60670
PB		 7238 vcpu->arch.smbase = 0x30000;
7239 }
f5132b01 7240
66f7b72e
JS		 7241 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7242 vcpu->arch.regs_avail = ~0;
7243 vcpu->arch.regs_dirty = ~0;
7244
d28bc9dd 7245 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7246}
7247
2b4a273b 7248void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7249{
7250 struct kvm_segment cs;
7251
7252 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7253 cs.selector = vector << 8;
7254 cs.base = vector << 12;
7255 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7256 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7257}
7258
13a34e06 7259int kvm_arch_hardware_enable(void)
e9b11c17 7260{
ca84d1a2
ZA		 7261 struct kvm *kvm;
7262 struct kvm_vcpu *vcpu;
7263 int i;
0dd6a6ed
ZA		 7264 int ret;
7265 u64 local_tsc;
7266 u64 max_tsc = 0;
7267 bool stable, backwards_tsc = false;
18863bdd
AK		 7268
7269 kvm_shared_msr_cpu_online();
13a34e06 7270 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7271 if (ret != 0)
7272 return ret;
7273
4ea1636b 7274 local_tsc = rdtsc();
0dd6a6ed
ZA		 7275 stable = !check_tsc_unstable();
7276 list_for_each_entry(kvm, &vm_list, vm_list) {
7277 kvm_for_each_vcpu(i, vcpu, kvm) {
7278 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7279 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7280 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7281 backwards_tsc = true;
7282 if (vcpu->arch.last_host_tsc > max_tsc)
7283 max_tsc = vcpu->arch.last_host_tsc;
7284 }
7285 }
7286 }
7287
7288 /*
7289 * Sometimes, even reliable TSCs go backwards. This happens on
7290 * platforms that reset TSC during suspend or hibernate actions, but
7291 * maintain synchronization. We must compensate. Fortunately, we can
7292 * detect that condition here, which happens early in CPU bringup,
7293 * before any KVM threads can be running. Unfortunately, we can't
7294 * bring the TSCs fully up to date with real time, as we aren't yet far
7295 * enough into CPU bringup that we know how much real time has actually
7296 * elapsed; our helper function, get_kernel_ns() will be using boot
7297 * variables that haven't been updated yet.
7298 *
7299 * So we simply find the maximum observed TSC above, then record the
7300 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7301 * the adjustment will be applied. Note that we accumulate
7302 * adjustments, in case multiple suspend cycles happen before some VCPU
7303 * gets a chance to run again. In the event that no KVM threads get a
7304 * chance to run, we will miss the entire elapsed period, as we'll have
7305 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7306 * loose cycle time. This isn't too big a deal, since the loss will be
7307 * uniform across all VCPUs (not to mention the scenario is extremely
7308 * unlikely). It is possible that a second hibernate recovery happens
7309 * much faster than a first, causing the observed TSC here to be
7310 * smaller; this would require additional padding adjustment, which is
7311 * why we set last_host_tsc to the local tsc observed here.
7312 *
7313 * N.B. - this code below runs only on platforms with reliable TSC,
7314 * as that is the only way backwards_tsc is set above. Also note
7315 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7316 * have the same delta_cyc adjustment applied if backwards_tsc
7317 * is detected. Note further, this adjustment is only done once,
7318 * as we reset last_host_tsc on all VCPUs to stop this from being
7319 * called multiple times (one for each physical CPU bringup).
7320 *
4a969980 7321 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7322 * will be compensated by the logic in vcpu_load, which sets the TSC to
7323 * catchup mode. This will catchup all VCPUs to real time, but cannot
7324 * guarantee that they stay in perfect synchronization.
7325 */
7326 if (backwards_tsc) {
7327 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7328 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7329 list_for_each_entry(kvm, &vm_list, vm_list) {
7330 kvm_for_each_vcpu(i, vcpu, kvm) {
7331 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7332 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7333 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7334 }
7335
7336 /*
7337 * We have to disable TSC offset matching.. if you were
7338 * booting a VM while issuing an S4 host suspend....
7339 * you may have some problem. Solving this issue is
7340 * left as an exercise to the reader.
7341 */
7342 kvm->arch.last_tsc_nsec = 0;
7343 kvm->arch.last_tsc_write = 0;
7344 }
7345
7346 }
7347 return 0;
e9b11c17
ZX		 7348}
7349
13a34e06 7350void kvm_arch_hardware_disable(void)
e9b11c17 7351{
13a34e06
RK		 7352 kvm_x86_ops->hardware_disable();
7353 drop_user_return_notifiers();
e9b11c17
ZX		 7354}
7355
7356int kvm_arch_hardware_setup(void)
7357{
9e9c3fe4
NA		 7358 int r;
7359
7360 r = kvm_x86_ops->hardware_setup();
7361 if (r != 0)
7362 return r;
7363
7364 kvm_init_msr_list();
7365 return 0;
e9b11c17
ZX		 7366}
7367
7368void kvm_arch_hardware_unsetup(void)
7369{
7370 kvm_x86_ops->hardware_unsetup();
7371}
7372
7373void kvm_arch_check_processor_compat(void *rtn)
7374{
7375 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7376}
7377
7378bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7379{
7380 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7381}
7382EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7383
7384bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7385{
7386 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7387}
7388
3e515705
AK		 7389bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7390{
35754c98 7391 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
3e515705
AK		 7392}
7393
54e9818f
GN		 7394struct static_key kvm_no_apic_vcpu __read_mostly;
7395
e9b11c17
ZX		 7396int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7397{
7398 struct page *page;
7399 struct kvm *kvm;
7400 int r;
7401
7402 BUG_ON(vcpu->kvm == NULL);
7403 kvm = vcpu->kvm;
7404
6aef266c 7405 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7406 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7407 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7408 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7409 else
a4535290 7410 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7411
7412 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7413 if (!page) {
7414 r = -ENOMEM;
7415 goto fail;
7416 }
ad312c7c 7417 vcpu->arch.pio_data = page_address(page);
e9b11c17 7418
cc578287 7419 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7420
e9b11c17
ZX		 7421 r = kvm_mmu_create(vcpu);
7422 if (r < 0)
7423 goto fail_free_pio_data;
7424
7425 if (irqchip_in_kernel(kvm)) {
7426 r = kvm_create_lapic(vcpu);
7427 if (r < 0)
7428 goto fail_mmu_destroy;
54e9818f
GN		 7429 } else
7430 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7431
890ca9ae
HY		 7432 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7433 GFP_KERNEL);
7434 if (!vcpu->arch.mce_banks) {
7435 r = -ENOMEM;
443c39bc 7436 goto fail_free_lapic;
890ca9ae
HY		 7437 }
7438 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7439
f1797359
WY		 7440 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7441 r = -ENOMEM;
f5f48ee1 7442 goto fail_free_mce_banks;
f1797359 7443 }
f5f48ee1 7444
0ee6a517 7445 fx_init(vcpu);
66f7b72e 7446
ba904635 7447 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7448 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7449
7450 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7451 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7452
5a4f55cd
EK		 7453 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7454
74545705
RK		 7455 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7456
af585b92 7457 kvm_async_pf_hash_reset(vcpu);
f5132b01 7458 kvm_pmu_init(vcpu);
af585b92 7459
1c1a9ce9
SR		 7460 vcpu->arch.pending_external_vector = -1;
7461
e9b11c17 7462 return 0;
0ee6a517 7463
f5f48ee1
SY		 7464fail_free_mce_banks:
7465 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7466fail_free_lapic:
7467 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7468fail_mmu_destroy:
7469 kvm_mmu_destroy(vcpu);
7470fail_free_pio_data:
ad312c7c 7471 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7472fail:
7473 return r;
7474}
7475
7476void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7477{
f656ce01
MT		 7478 int idx;
7479
f5132b01 7480 kvm_pmu_destroy(vcpu);
36cb93fd 7481 kfree(vcpu->arch.mce_banks);
e9b11c17 7482 kvm_free_lapic(vcpu);
f656ce01 7483 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7484 kvm_mmu_destroy(vcpu);
f656ce01 7485 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7486 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7487 if (!lapic_in_kernel(vcpu))
54e9818f 7488 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7489}
d19a9cd2 7490
e790d9ef
RK		 7491void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7492{
ae97a3b8 7493 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7494}
7495
e08b9637 7496int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7497{
e08b9637
CO		 7498 if (type)
7499 return -EINVAL;
7500
6ef768fa 7501 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7502 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7503 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7504 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7505 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7506
5550af4d
SY		 7507 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7508 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7509 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7510 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7511 &kvm->arch.irq_sources_bitmap);
5550af4d 7512
038f8c11 7513 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7514 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7515 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7516
7517 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7518
7e44e449 7519 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7520 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7521
d89f5eff 7522 return 0;
d19a9cd2
ZX		 7523}
7524
7525static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7526{
9fc77441
MT		 7527 int r;
7528 r = vcpu_load(vcpu);
7529 BUG_ON(r);
d19a9cd2
ZX		 7530 kvm_mmu_unload(vcpu);
7531 vcpu_put(vcpu);
7532}
7533
7534static void kvm_free_vcpus(struct kvm *kvm)
7535{
7536 unsigned int i;
988a2cae 7537 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7538
7539 /*
7540 * Unpin any mmu pages first.
7541 */
af585b92
GN		 7542 kvm_for_each_vcpu(i, vcpu, kvm) {
7543 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7544 kvm_unload_vcpu_mmu(vcpu);
af585b92 7545 }
988a2cae
GN		 7546 kvm_for_each_vcpu(i, vcpu, kvm)
7547 kvm_arch_vcpu_free(vcpu);
7548
7549 mutex_lock(&kvm->lock);
7550 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7551 kvm->vcpus[i] = NULL;
d19a9cd2 7552
988a2cae
GN		 7553 atomic_set(&kvm->online_vcpus, 0);
7554 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7555}
7556
ad8ba2cd
SY		 7557void kvm_arch_sync_events(struct kvm *kvm)
7558{
332967a3 7559 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7560 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7561 kvm_free_all_assigned_devices(kvm);
aea924f6 7562 kvm_free_pit(kvm);
ad8ba2cd
SY		 7563}
7564
1d8007bd 7565int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7566{
7567 int i, r;
25188b99 7568 unsigned long hva;
f0d648bd
PB		 7569 struct kvm_memslots *slots = kvm_memslots(kvm);
7570 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 7571
7572 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 7573 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7574 return -EINVAL;
9da0e4d5 7575
f0d648bd
PB		 7576 slot = id_to_memslot(slots, id);
7577 if (size) {
7578 if (WARN_ON(slot->npages))
7579 return -EEXIST;
7580
7581 /*
7582 * MAP_SHARED to prevent internal slot pages from being moved
7583 * by fork()/COW.
7584 */
7585 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7586 MAP_SHARED | MAP_ANONYMOUS, 0);
7587 if (IS_ERR((void *)hva))
7588 return PTR_ERR((void *)hva);
7589 } else {
7590 if (!slot->npages)
7591 return 0;
9da0e4d5 7592
f0d648bd
PB		 7593 hva = 0;
7594 }
7595
7596 old = *slot;
9da0e4d5 7597 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 7598 struct kvm_userspace_memory_region m;
9da0e4d5 7599
1d8007bd
PB		 7600 m.slot = id | (i << 16);
7601 m.flags = 0;
7602 m.guest_phys_addr = gpa;
f0d648bd 7603 m.userspace_addr = hva;
1d8007bd 7604 m.memory_size = size;
9da0e4d5
PB		 7605 r = __kvm_set_memory_region(kvm, &m);
7606 if (r < 0)
7607 return r;
7608 }
7609
f0d648bd
PB		 7610 if (!size) {
7611 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7612 WARN_ON(r < 0);
7613 }
7614
9da0e4d5
PB		 7615 return 0;
7616}
7617EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7618
1d8007bd 7619int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7620{
7621 int r;
7622
7623 mutex_lock(&kvm->slots_lock);
1d8007bd 7624 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 7625 mutex_unlock(&kvm->slots_lock);
7626
7627 return r;
7628}
7629EXPORT_SYMBOL_GPL(x86_set_memory_region);
7630
d19a9cd2
ZX		 7631void kvm_arch_destroy_vm(struct kvm *kvm)
7632{
27469d29
AH		 7633 if (current->mm == kvm->mm) {
7634 /*
7635 * Free memory regions allocated on behalf of userspace,
7636 * unless the the memory map has changed due to process exit
7637 * or fd copying.
7638 */
1d8007bd
PB		 7639 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7640 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7641 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 7642 }
6eb55818 7643 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7644 kfree(kvm->arch.vpic);
7645 kfree(kvm->arch.vioapic);
d19a9cd2 7646 kvm_free_vcpus(kvm);
1e08ec4a 7647 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7648}
0de10343 7649
5587027c 7650void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7651 struct kvm_memory_slot *dont)
7652{
7653 int i;
7654
d89cc617
TY		 7655 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7656 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7657 kvfree(free->arch.rmap[i]);
d89cc617 7658 free->arch.rmap[i] = NULL;
77d11309 7659 }
d89cc617
TY		 7660 if (i == 0)
7661 continue;
7662
7663 if (!dont || free->arch.lpage_info[i - 1] !=
7664 dont->arch.lpage_info[i - 1]) {
548ef284 7665 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7666 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7667 }
7668 }
7669}
7670
5587027c
AK		 7671int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7672 unsigned long npages)
db3fe4eb
TY		 7673{
7674 int i;
7675
d89cc617 7676 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7677 unsigned long ugfn;
7678 int lpages;
d89cc617 7679 int level = i + 1;
db3fe4eb
TY		 7680
7681 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7682 slot->base_gfn, level) + 1;
7683
d89cc617
TY		 7684 slot->arch.rmap[i] =
7685 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7686 if (!slot->arch.rmap[i])
77d11309 7687 goto out_free;
d89cc617
TY		 7688 if (i == 0)
7689 continue;
77d11309 7690
d89cc617
TY		 7691 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7692 sizeof(*slot->arch.lpage_info[i - 1]));
7693 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7694 goto out_free;
7695
7696 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7697 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7698 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7699 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7700 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7701 /*
7702 * If the gfn and userspace address are not aligned wrt each
7703 * other, or if explicitly asked to, disable large page
7704 * support for this slot
7705 */
7706 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7707 !kvm_largepages_enabled()) {
7708 unsigned long j;
7709
7710 for (j = 0; j < lpages; ++j)
d89cc617 7711 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7712 }
7713 }
7714
7715 return 0;
7716
7717out_free:
d89cc617 7718 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7719 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7720 slot->arch.rmap[i] = NULL;
7721 if (i == 0)
7722 continue;
7723
548ef284 7724 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7725 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7726 }
7727 return -ENOMEM;
7728}
7729
15f46015 7730void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7731{
e6dff7d1
TY		 7732 /*
7733 * memslots->generation has been incremented.
7734 * mmio generation may have reached its maximum value.
7735 */
54bf36aa 7736 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 7737}
7738
f7784b8e
MT		 7739int kvm_arch_prepare_memory_region(struct kvm *kvm,
7740 struct kvm_memory_slot *memslot,
09170a49 7741 const struct kvm_userspace_memory_region *mem,
7b6195a9 7742 enum kvm_mr_change change)
0de10343 7743{
f7784b8e
MT		 7744 return 0;
7745}
7746
88178fd4
KH		 7747static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7748 struct kvm_memory_slot *new)
7749{
7750 /* Still write protect RO slot */
7751 if (new->flags & KVM_MEM_READONLY) {
7752 kvm_mmu_slot_remove_write_access(kvm, new);
7753 return;
7754 }
7755
7756 /*
7757 * Call kvm_x86_ops dirty logging hooks when they are valid.
7758 *
7759 * kvm_x86_ops->slot_disable_log_dirty is called when:
7760 *
7761 * - KVM_MR_CREATE with dirty logging is disabled
7762 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7763 *
7764 * The reason is, in case of PML, we need to set D-bit for any slots
7765 * with dirty logging disabled in order to eliminate unnecessary GPA
7766 * logging in PML buffer (and potential PML buffer full VMEXT). This
7767 * guarantees leaving PML enabled during guest's lifetime won't have
7768 * any additonal overhead from PML when guest is running with dirty
7769 * logging disabled for memory slots.
7770 *
7771 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7772 * to dirty logging mode.
7773 *
7774 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7775 *
7776 * In case of write protect:
7777 *
7778 * Write protect all pages for dirty logging.
7779 *
7780 * All the sptes including the large sptes which point to this
7781 * slot are set to readonly. We can not create any new large
7782 * spte on this slot until the end of the logging.
7783 *
7784 * See the comments in fast_page_fault().
7785 */
7786 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7787 if (kvm_x86_ops->slot_enable_log_dirty)
7788 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7789 else
7790 kvm_mmu_slot_remove_write_access(kvm, new);
7791 } else {
7792 if (kvm_x86_ops->slot_disable_log_dirty)
7793 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7794 }
7795}
7796
f7784b8e 7797void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 7798 const struct kvm_userspace_memory_region *mem,
8482644a 7799 const struct kvm_memory_slot *old,
f36f3f28 7800 const struct kvm_memory_slot *new,
8482644a 7801 enum kvm_mr_change change)
f7784b8e 7802{
8482644a 7803 int nr_mmu_pages = 0;
f7784b8e 7804
48c0e4e9
XG		 7805 if (!kvm->arch.n_requested_mmu_pages)
7806 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7807
48c0e4e9 7808 if (nr_mmu_pages)
0de10343 7809 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 7810
3ea3b7fa
WL		 7811 /*
7812 * Dirty logging tracks sptes in 4k granularity, meaning that large
7813 * sptes have to be split. If live migration is successful, the guest
7814 * in the source machine will be destroyed and large sptes will be
7815 * created in the destination. However, if the guest continues to run
7816 * in the source machine (for example if live migration fails), small
7817 * sptes will remain around and cause bad performance.
7818 *
7819 * Scan sptes if dirty logging has been stopped, dropping those
7820 * which can be collapsed into a single large-page spte. Later
7821 * page faults will create the large-page sptes.
7822 */
7823 if ((change != KVM_MR_DELETE) &&
7824 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
7825 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
7826 kvm_mmu_zap_collapsible_sptes(kvm, new);
7827
c972f3b1 7828 /*
88178fd4 7829 * Set up write protection and/or dirty logging for the new slot.
c126d94f 7830 *
88178fd4
KH		 7831 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7832 * been zapped so no dirty logging staff is needed for old slot. For
7833 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7834 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 7835 *
7836 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 7837 */
88178fd4 7838 if (change != KVM_MR_DELETE)
f36f3f28 7839 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 7840}
1d737c8a 7841
2df72e9b 7842void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7843{
6ca18b69 7844 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7845}
7846
2df72e9b
MT		 7847void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7848 struct kvm_memory_slot *slot)
7849{
6ca18b69 7850 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7851}
7852
5d9bc648
PB		 7853static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
7854{
7855 if (!list_empty_careful(&vcpu->async_pf.done))
7856 return true;
7857
7858 if (kvm_apic_has_events(vcpu))
7859 return true;
7860
7861 if (vcpu->arch.pv.pv_unhalted)
7862 return true;
7863
7864 if (atomic_read(&vcpu->arch.nmi_queued))
7865 return true;
7866
73917739
PB		 7867 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
7868 return true;
7869
5d9bc648
PB		 7870 if (kvm_arch_interrupt_allowed(vcpu) &&
7871 kvm_cpu_has_interrupt(vcpu))
7872 return true;
7873
7874 return false;
7875}
7876
1d737c8a
ZX		 7877int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7878{
b6b8a145
JK		 7879 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7880 kvm_x86_ops->check_nested_events(vcpu, false);
7881
5d9bc648 7882 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 7883}
5736199a 7884
b6d33834 7885int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7886{
b6d33834 7887 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7888}
78646121
GN		 7889
7890int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7891{
7892 return kvm_x86_ops->interrupt_allowed(vcpu);
7893}
229456fc 7894
82b32774 7895unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 7896{
82b32774
NA		 7897 if (is_64_bit_mode(vcpu))
7898 return kvm_rip_read(vcpu);
7899 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7900 kvm_rip_read(vcpu));
7901}
7902EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 7903
82b32774
NA		 7904bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7905{
7906 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 7907}
7908EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7909
94fe45da
JK		 7910unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7911{
7912 unsigned long rflags;
7913
7914 rflags = kvm_x86_ops->get_rflags(vcpu);
7915 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7916 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7917 return rflags;
7918}
7919EXPORT_SYMBOL_GPL(kvm_get_rflags);
7920
6addfc42 7921static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7922{
7923 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7924 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7925 rflags |= X86_EFLAGS_TF;
94fe45da 7926 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 7927}
7928
7929void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7930{
7931 __kvm_set_rflags(vcpu, rflags);
3842d135 7932 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7933}
7934EXPORT_SYMBOL_GPL(kvm_set_rflags);
7935
56028d08
GN		 7936void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7937{
7938 int r;
7939
fb67e14f 7940 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7941 work->wakeup_all)
56028d08
GN		 7942 return;
7943
7944 r = kvm_mmu_reload(vcpu);
7945 if (unlikely(r))
7946 return;
7947
fb67e14f
XG		 7948 if (!vcpu->arch.mmu.direct_map &&
7949 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7950 return;
7951
56028d08
GN		 7952 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7953}
7954
af585b92
GN		 7955static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7956{
7957 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7958}
7959
7960static inline u32 kvm_async_pf_next_probe(u32 key)
7961{
7962 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7963}
7964
7965static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7966{
7967 u32 key = kvm_async_pf_hash_fn(gfn);
7968
7969 while (vcpu->arch.apf.gfns[key] != ~0)
7970 key = kvm_async_pf_next_probe(key);
7971
7972 vcpu->arch.apf.gfns[key] = gfn;
7973}
7974
7975static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7976{
7977 int i;
7978 u32 key = kvm_async_pf_hash_fn(gfn);
7979
7980 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7981 (vcpu->arch.apf.gfns[key] != gfn &&
7982 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7983 key = kvm_async_pf_next_probe(key);
7984
7985 return key;
7986}
7987
7988bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7989{
7990 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7991}
7992
7993static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7994{
7995 u32 i, j, k;
7996
7997 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7998 while (true) {
7999 vcpu->arch.apf.gfns[i] = ~0;
8000 do {
8001 j = kvm_async_pf_next_probe(j);
8002 if (vcpu->arch.apf.gfns[j] == ~0)
8003 return;
8004 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8005 /*
8006 * k lies cyclically in ]i,j]
8007 * | i.k.j |
8008 * |....j i.k.| or |.k..j i...|
8009 */
8010 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8011 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8012 i = j;
8013 }
8014}
8015
7c90705b
GN		 8016static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8017{
8018
8019 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8020 sizeof(val));
8021}
8022
af585b92
GN		 8023void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8024 struct kvm_async_pf *work)
8025{
6389ee94
AK		 8026 struct x86_exception fault;
8027
7c90705b 8028 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8029 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8030
8031 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8032 (vcpu->arch.apf.send_user_only &&
8033 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8034 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8035 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8036 fault.vector = PF_VECTOR;
8037 fault.error_code_valid = true;
8038 fault.error_code = 0;
8039 fault.nested_page_fault = false;
8040 fault.address = work->arch.token;
8041 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8042 }
af585b92
GN		 8043}
8044
8045void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8046 struct kvm_async_pf *work)
8047{
6389ee94
AK		 8048 struct x86_exception fault;
8049
7c90705b 8050 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8051 if (work->wakeup_all)
7c90705b
GN		 8052 work->arch.token = ~0; /* broadcast wakeup */
8053 else
8054 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8055
8056 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8057 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8058 fault.vector = PF_VECTOR;
8059 fault.error_code_valid = true;
8060 fault.error_code = 0;
8061 fault.nested_page_fault = false;
8062 fault.address = work->arch.token;
8063 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8064 }
e6d53e3b 8065 vcpu->arch.apf.halted = false;
a4fa1635 8066 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8067}
8068
8069bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8070{
8071 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8072 return true;
8073 else
8074 return !kvm_event_needs_reinjection(vcpu) &&
8075 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8076}
8077
5544eb9b
PB		 8078void kvm_arch_start_assignment(struct kvm *kvm)
8079{
8080 atomic_inc(&kvm->arch.assigned_device_count);
8081}
8082EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8083
8084void kvm_arch_end_assignment(struct kvm *kvm)
8085{
8086 atomic_dec(&kvm->arch.assigned_device_count);
8087}
8088EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8089
8090bool kvm_arch_has_assigned_device(struct kvm *kvm)
8091{
8092 return atomic_read(&kvm->arch.assigned_device_count);
8093}
8094EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8095
e0f0bbc5
AW		 8096void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8097{
8098 atomic_inc(&kvm->arch.noncoherent_dma_count);
8099}
8100EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8101
8102void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8103{
8104 atomic_dec(&kvm->arch.noncoherent_dma_count);
8105}
8106EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8107
8108bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8109{
8110 return atomic_read(&kvm->arch.noncoherent_dma_count);
8111}
8112EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8113
87276880
FW		 8114int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8115 struct irq_bypass_producer *prod)
8116{
8117 struct kvm_kernel_irqfd *irqfd =
8118 container_of(cons, struct kvm_kernel_irqfd, consumer);
8119
8120 if (kvm_x86_ops->update_pi_irte) {
8121 irqfd->producer = prod;
8122 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8123 prod->irq, irqfd->gsi, 1);
8124 }
8125
8126 return -EINVAL;
8127}
8128
8129void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8130 struct irq_bypass_producer *prod)
8131{
8132 int ret;
8133 struct kvm_kernel_irqfd *irqfd =
8134 container_of(cons, struct kvm_kernel_irqfd, consumer);
8135
8136 if (!kvm_x86_ops->update_pi_irte) {
8137 WARN_ON(irqfd->producer != NULL);
8138 return;
8139 }
8140
8141 WARN_ON(irqfd->producer != prod);
8142 irqfd->producer = NULL;
8143
8144 /*
8145 * When producer of consumer is unregistered, we change back to
8146 * remapped mode, so we can re-use the current implementation
8147 * when the irq is masked/disabed or the consumer side (KVM
8148 * int this case doesn't want to receive the interrupts.
8149 */
8150 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8151 if (ret)
8152 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8153 " fails: %d\n", irqfd->consumer.token, ret);
8154}
8155
8156int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8157 uint32_t guest_irq, bool set)
8158{
8159 if (!kvm_x86_ops->update_pi_irte)
8160 return -EINVAL;
8161
8162 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8163}
8164
229456fc 8165EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8166EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8167EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8168EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8169EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8170EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8171EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8172EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8173EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8174EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8175EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8176EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8177EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8178EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8179EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8180EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8181EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
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