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KVM: x86: use irqchip_kernel() to check for pic+ioapic
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad
IM		 56#include <linux/sched/stat.h>
57
aec51dc4 58#include <trace/events/kvm.h>
2ed152af 59
24f1e32c 60#include <asm/debugreg.h>
d825ed0a 61#include <asm/msr.h>
a5f61300 62#include <asm/desc.h>
890ca9ae 63#include <asm/mce.h>
f89e32e0 64#include <linux/kernel_stat.h>
78f7f1e5 65#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 66#include <asm/pvclock.h>
217fc9cf 67#include <asm/div64.h>
efc64404 68#include <asm/irq_remapping.h>
043405e1 69
d1898b73
DH		 70#define CREATE_TRACE_POINTS
71#include "trace.h"
72
313a3dc7 73#define MAX_IO_MSRS 256
890ca9ae 74#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 75u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
76EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 77
0f65dd70
AK		 78#define emul_to_vcpu(ctxt) \
79 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
80
50a37eb4
JR		 81/* EFER defaults:
82 * - enable syscall per default because its emulated by KVM
83 * - enable LME and LMA per default on 64 bit KVM
84 */
85#ifdef CONFIG_X86_64
1260edbe
LJ		 86static
87u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 88#else
1260edbe 89static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 90#endif
313a3dc7 91
ba1389b7
AK		 92#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
93#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 94
c519265f
RK		 95#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
96 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 97
cb142eb7 98static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 99static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 100static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 101static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 102
893590c7 103struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 104EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 105
893590c7 106static bool __read_mostly ignore_msrs = 0;
476bc001 107module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 108
9ed96e87
MT		 109unsigned int min_timer_period_us = 500;
110module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
111
630994b3
MT		 112static bool __read_mostly kvmclock_periodic_sync = true;
113module_param(kvmclock_periodic_sync, bool, S_IRUGO);
114
893590c7 115bool __read_mostly kvm_has_tsc_control;
92a1f12d 116EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 117u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 118EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 119u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
120EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
121u64 __read_mostly kvm_max_tsc_scaling_ratio;
122EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 123u64 __read_mostly kvm_default_tsc_scaling_ratio;
124EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 125
cc578287 126/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 127static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 128module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
129
d0659d94 130/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 131unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 132module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
133
52004014
FW		 134static bool __read_mostly vector_hashing = true;
135module_param(vector_hashing, bool, S_IRUGO);
136
893590c7 137static bool __read_mostly backwards_tsc_observed = false;
16a96021 138
18863bdd
AK		 139#define KVM_NR_SHARED_MSRS 16
140
141struct kvm_shared_msrs_global {
142 int nr;
2bf78fa7 143 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 144};
145
146struct kvm_shared_msrs {
147 struct user_return_notifier urn;
148 bool registered;
2bf78fa7
SY		 149 struct kvm_shared_msr_values {
150 u64 host;
151 u64 curr;
152 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 153};
154
155static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 156static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 157
417bc304 158struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 159 { "pf_fixed", VCPU_STAT(pf_fixed) },
160 { "pf_guest", VCPU_STAT(pf_guest) },
161 { "tlb_flush", VCPU_STAT(tlb_flush) },
162 { "invlpg", VCPU_STAT(invlpg) },
163 { "exits", VCPU_STAT(exits) },
164 { "io_exits", VCPU_STAT(io_exits) },
165 { "mmio_exits", VCPU_STAT(mmio_exits) },
166 { "signal_exits", VCPU_STAT(signal_exits) },
167 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 168 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 169 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 170 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 171 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 172 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 173 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 174 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 175 { "request_irq", VCPU_STAT(request_irq_exits) },
176 { "irq_exits", VCPU_STAT(irq_exits) },
177 { "host_state_reload", VCPU_STAT(host_state_reload) },
178 { "efer_reload", VCPU_STAT(efer_reload) },
179 { "fpu_reload", VCPU_STAT(fpu_reload) },
180 { "insn_emulation", VCPU_STAT(insn_emulation) },
181 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 182 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 183 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 184 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 185 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
186 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
187 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
188 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
189 { "mmu_flooded", VM_STAT(mmu_flooded) },
190 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 191 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 192 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 193 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 194 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 195 { "max_mmu_page_hash_collisions",
196 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 197 { NULL }
198};
199
2acf923e
DC		 200u64 __read_mostly host_xcr0;
201
b6785def 202static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 203
af585b92
GN		 204static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
205{
206 int i;
207 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
208 vcpu->arch.apf.gfns[i] = ~0;
209}
210
18863bdd
AK		 211static void kvm_on_user_return(struct user_return_notifier *urn)
212{
213 unsigned slot;
18863bdd
AK		 214 struct kvm_shared_msrs *locals
215 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 216 struct kvm_shared_msr_values *values;
1650b4eb
IA		 217 unsigned long flags;
218
219 /*
220 * Disabling irqs at this point since the following code could be
221 * interrupted and executed through kvm_arch_hardware_disable()
222 */
223 local_irq_save(flags);
224 if (locals->registered) {
225 locals->registered = false;
226 user_return_notifier_unregister(urn);
227 }
228 local_irq_restore(flags);
18863bdd 229 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 230 values = &locals->values[slot];
231 if (values->host != values->curr) {
232 wrmsrl(shared_msrs_global.msrs[slot], values->host);
233 values->curr = values->host;
18863bdd
AK		 234 }
235 }
18863bdd
AK		 236}
237
2bf78fa7 238static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 239{
18863bdd 240 u64 value;
013f6a5d
MT		 241 unsigned int cpu = smp_processor_id();
242 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 243
2bf78fa7
SY		 244 /* only read, and nobody should modify it at this time,
245 * so don't need lock */
246 if (slot >= shared_msrs_global.nr) {
247 printk(KERN_ERR "kvm: invalid MSR slot!");
248 return;
249 }
250 rdmsrl_safe(msr, &value);
251 smsr->values[slot].host = value;
252 smsr->values[slot].curr = value;
253}
254
255void kvm_define_shared_msr(unsigned slot, u32 msr)
256{
0123be42 257 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 258 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 259 if (slot >= shared_msrs_global.nr)
260 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 261}
262EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
263
264static void kvm_shared_msr_cpu_online(void)
265{
266 unsigned i;
18863bdd
AK		 267
268 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 269 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 270}
271
8b3c3104 272int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 273{
013f6a5d
MT		 274 unsigned int cpu = smp_processor_id();
275 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 276 int err;
18863bdd 277
2bf78fa7 278 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 279 return 0;
2bf78fa7 280 smsr->values[slot].curr = value;
8b3c3104
AH		 281 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
282 if (err)
283 return 1;
284
18863bdd
AK		 285 if (!smsr->registered) {
286 smsr->urn.on_user_return = kvm_on_user_return;
287 user_return_notifier_register(&smsr->urn);
288 smsr->registered = true;
289 }
8b3c3104 290 return 0;
18863bdd
AK		 291}
292EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
293
13a34e06 294static void drop_user_return_notifiers(void)
3548bab5 295{
013f6a5d
MT		 296 unsigned int cpu = smp_processor_id();
297 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 298
299 if (smsr->registered)
300 kvm_on_user_return(&smsr->urn);
301}
302
6866b83e
CO		 303u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
304{
8a5a87d9 305 return vcpu->arch.apic_base;
6866b83e
CO		 306}
307EXPORT_SYMBOL_GPL(kvm_get_apic_base);
308
58cb628d
JK		 309int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
310{
311 u64 old_state = vcpu->arch.apic_base &
312 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
313 u64 new_state = msr_info->data &
314 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
315 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
316 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
317
318 if (!msr_info->host_initiated &&
319 ((msr_info->data & reserved_bits) != 0 ||
320 new_state == X2APIC_ENABLE ||
321 (new_state == MSR_IA32_APICBASE_ENABLE &&
322 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
323 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
324 old_state == 0)))
325 return 1;
326
327 kvm_lapic_set_base(vcpu, msr_info->data);
328 return 0;
6866b83e
CO		 329}
330EXPORT_SYMBOL_GPL(kvm_set_apic_base);
331
2605fc21 332asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 333{
334 /* Fault while not rebooting. We want the trace. */
335 BUG();
336}
337EXPORT_SYMBOL_GPL(kvm_spurious_fault);
338
3fd28fce
ED		 339#define EXCPT_BENIGN 0
340#define EXCPT_CONTRIBUTORY 1
341#define EXCPT_PF 2
342
343static int exception_class(int vector)
344{
345 switch (vector) {
346 case PF_VECTOR:
347 return EXCPT_PF;
348 case DE_VECTOR:
349 case TS_VECTOR:
350 case NP_VECTOR:
351 case SS_VECTOR:
352 case GP_VECTOR:
353 return EXCPT_CONTRIBUTORY;
354 default:
355 break;
356 }
357 return EXCPT_BENIGN;
358}
359
d6e8c854
NA		 360#define EXCPT_FAULT 0
361#define EXCPT_TRAP 1
362#define EXCPT_ABORT 2
363#define EXCPT_INTERRUPT 3
364
365static int exception_type(int vector)
366{
367 unsigned int mask;
368
369 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
370 return EXCPT_INTERRUPT;
371
372 mask = 1 << vector;
373
374 /* #DB is trap, as instruction watchpoints are handled elsewhere */
375 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
376 return EXCPT_TRAP;
377
378 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
379 return EXCPT_ABORT;
380
381 /* Reserved exceptions will result in fault */
382 return EXCPT_FAULT;
383}
384
3fd28fce 385static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 386 unsigned nr, bool has_error, u32 error_code,
387 bool reinject)
3fd28fce
ED		 388{
389 u32 prev_nr;
390 int class1, class2;
391
3842d135
AK		 392 kvm_make_request(KVM_REQ_EVENT, vcpu);
393
3fd28fce
ED		 394 if (!vcpu->arch.exception.pending) {
395 queue:
3ffb2468
NA		 396 if (has_error && !is_protmode(vcpu))
397 has_error = false;
3fd28fce
ED		 398 vcpu->arch.exception.pending = true;
399 vcpu->arch.exception.has_error_code = has_error;
400 vcpu->arch.exception.nr = nr;
401 vcpu->arch.exception.error_code = error_code;
3f0fd292 402 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 403 return;
404 }
405
406 /* to check exception */
407 prev_nr = vcpu->arch.exception.nr;
408 if (prev_nr == DF_VECTOR) {
409 /* triple fault -> shutdown */
a8eeb04a 410 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 411 return;
412 }
413 class1 = exception_class(prev_nr);
414 class2 = exception_class(nr);
415 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
416 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
417 /* generate double fault per SDM Table 5-5 */
418 vcpu->arch.exception.pending = true;
419 vcpu->arch.exception.has_error_code = true;
420 vcpu->arch.exception.nr = DF_VECTOR;
421 vcpu->arch.exception.error_code = 0;
422 } else
423 /* replace previous exception with a new one in a hope
424 that instruction re-execution will regenerate lost
425 exception */
426 goto queue;
427}
428
298101da
AK		 429void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
430{
ce7ddec4 431 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 432}
433EXPORT_SYMBOL_GPL(kvm_queue_exception);
434
ce7ddec4
JR		 435void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
436{
437 kvm_multiple_exception(vcpu, nr, false, 0, true);
438}
439EXPORT_SYMBOL_GPL(kvm_requeue_exception);
440
6affcbed 441int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 442{
db8fcefa
AP		 443 if (err)
444 kvm_inject_gp(vcpu, 0);
445 else
6affcbed
KH		 446 return kvm_skip_emulated_instruction(vcpu);
447
448 return 1;
db8fcefa
AP		 449}
450EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 451
6389ee94 452void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 453{
454 ++vcpu->stat.pf_guest;
6389ee94
AK		 455 vcpu->arch.cr2 = fault->address;
456 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 457}
27d6c865 458EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 459
ef54bcfe 460static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 461{
6389ee94
AK		 462 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
463 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 464 else
6389ee94 465 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 466
467 return fault->nested_page_fault;
d4f8cf66
JR		 468}
469
3419ffc8
SY		 470void kvm_inject_nmi(struct kvm_vcpu *vcpu)
471{
7460fb4a
AK		 472 atomic_inc(&vcpu->arch.nmi_queued);
473 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 474}
475EXPORT_SYMBOL_GPL(kvm_inject_nmi);
476
298101da
AK		 477void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
478{
ce7ddec4 479 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 480}
481EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
482
ce7ddec4
JR		 483void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
484{
485 kvm_multiple_exception(vcpu, nr, true, error_code, true);
486}
487EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
488
0a79b009
AK		 489/*
490 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
491 * a #GP and return false.
492 */
493bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 494{
0a79b009
AK		 495 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
496 return true;
497 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
498 return false;
298101da 499}
0a79b009 500EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 501
16f8a6f9
NA		 502bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
503{
504 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
505 return true;
506
507 kvm_queue_exception(vcpu, UD_VECTOR);
508 return false;
509}
510EXPORT_SYMBOL_GPL(kvm_require_dr);
511
ec92fe44
JR		 512/*
513 * This function will be used to read from the physical memory of the currently
54bf36aa 514 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 515 * can read from guest physical or from the guest's guest physical memory.
516 */
517int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
518 gfn_t ngfn, void *data, int offset, int len,
519 u32 access)
520{
54987b7a 521 struct x86_exception exception;
ec92fe44
JR		 522 gfn_t real_gfn;
523 gpa_t ngpa;
524
525 ngpa = gfn_to_gpa(ngfn);
54987b7a 526 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 527 if (real_gfn == UNMAPPED_GVA)
528 return -EFAULT;
529
530 real_gfn = gpa_to_gfn(real_gfn);
531
54bf36aa 532 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 533}
534EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
535
69b0049a 536static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 537 void *data, int offset, int len, u32 access)
538{
539 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
540 data, offset, len, access);
541}
542
a03490ed
CO		 543/*
544 * Load the pae pdptrs. Return true is they are all valid.
545 */
ff03a073 546int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 547{
548 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
549 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
550 int i;
551 int ret;
ff03a073 552 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 553
ff03a073
JR		 554 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
555 offset * sizeof(u64), sizeof(pdpte),
556 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 557 if (ret < 0) {
558 ret = 0;
559 goto out;
560 }
561 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 562 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 563 (pdpte[i] &
564 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 565 ret = 0;
566 goto out;
567 }
568 }
569 ret = 1;
570
ff03a073 571 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 572 __set_bit(VCPU_EXREG_PDPTR,
573 (unsigned long *)&vcpu->arch.regs_avail);
574 __set_bit(VCPU_EXREG_PDPTR,
575 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 576out:
a03490ed
CO		 577
578 return ret;
579}
cc4b6871 580EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 581
9ed38ffa 582bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 583{
ff03a073 584 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 585 bool changed = true;
3d06b8bf
JR		 586 int offset;
587 gfn_t gfn;
d835dfec
AK		 588 int r;
589
590 if (is_long_mode(vcpu) || !is_pae(vcpu))
591 return false;
592
6de4f3ad
AK		 593 if (!test_bit(VCPU_EXREG_PDPTR,
594 (unsigned long *)&vcpu->arch.regs_avail))
595 return true;
596
9f8fe504
AK		 597 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
598 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 599 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
600 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 601 if (r < 0)
602 goto out;
ff03a073 603 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 604out:
d835dfec
AK		 605
606 return changed;
607}
9ed38ffa 608EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 609
49a9b07e 610int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 611{
aad82703 612 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 613 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 614
f9a48e6a
AK		 615 cr0 |= X86_CR0_ET;
616
ab344828 617#ifdef CONFIG_X86_64
0f12244f
GN		 618 if (cr0 & 0xffffffff00000000UL)
619 return 1;
ab344828
GN		 620#endif
621
622 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 623
0f12244f
GN		 624 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
625 return 1;
a03490ed 626
0f12244f
GN		 627 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
628 return 1;
a03490ed
CO		 629
630 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
631#ifdef CONFIG_X86_64
f6801dff 632 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 633 int cs_db, cs_l;
634
0f12244f
GN		 635 if (!is_pae(vcpu))
636 return 1;
a03490ed 637 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 638 if (cs_l)
639 return 1;
a03490ed
CO		 640 } else
641#endif
ff03a073 642 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 643 kvm_read_cr3(vcpu)))
0f12244f 644 return 1;
a03490ed
CO		 645 }
646
ad756a16
MJ		 647 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
648 return 1;
649
a03490ed 650 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 651
d170c419 652 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 653 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 654 kvm_async_pf_hash_reset(vcpu);
655 }
e5f3f027 656
aad82703
SY		 657 if ((cr0 ^ old_cr0) & update_bits)
658 kvm_mmu_reset_context(vcpu);
b18d5431 659
879ae188
LE		 660 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
661 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
662 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 663 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
664
0f12244f
GN		 665 return 0;
666}
2d3ad1f4 667EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 668
2d3ad1f4 669void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 670{
49a9b07e 671 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 672}
2d3ad1f4 673EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 674
42bdf991
MT		 675static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
676{
677 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
678 !vcpu->guest_xcr0_loaded) {
679 /* kvm_set_xcr() also depends on this */
680 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
681 vcpu->guest_xcr0_loaded = 1;
682 }
683}
684
685static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
686{
687 if (vcpu->guest_xcr0_loaded) {
688 if (vcpu->arch.xcr0 != host_xcr0)
689 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
690 vcpu->guest_xcr0_loaded = 0;
691 }
692}
693
69b0049a 694static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 695{
56c103ec
LJ		 696 u64 xcr0 = xcr;
697 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 698 u64 valid_bits;
2acf923e
DC		 699
700 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
701 if (index != XCR_XFEATURE_ENABLED_MASK)
702 return 1;
d91cab78 703 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 704 return 1;
d91cab78 705 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 706 return 1;
46c34cb0
PB		 707
708 /*
709 * Do not allow the guest to set bits that we do not support
710 * saving. However, xcr0 bit 0 is always set, even if the
711 * emulated CPU does not support XSAVE (see fx_init).
712 */
d91cab78 713 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 714 if (xcr0 & ~valid_bits)
2acf923e 715 return 1;
46c34cb0 716
d91cab78
DH		 717 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
718 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 719 return 1;
720
d91cab78
DH		 721 if (xcr0 & XFEATURE_MASK_AVX512) {
722 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 723 return 1;
d91cab78 724 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 725 return 1;
726 }
2acf923e 727 vcpu->arch.xcr0 = xcr0;
56c103ec 728
d91cab78 729 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 730 kvm_update_cpuid(vcpu);
2acf923e
DC		 731 return 0;
732}
733
734int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
735{
764bcbc5
Z		 736 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
737 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 738 kvm_inject_gp(vcpu, 0);
739 return 1;
740 }
741 return 0;
742}
743EXPORT_SYMBOL_GPL(kvm_set_xcr);
744
a83b29c6 745int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 746{
fc78f519 747 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 748 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 749 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 750
0f12244f
GN		 751 if (cr4 & CR4_RESERVED_BITS)
752 return 1;
a03490ed 753
2acf923e
DC		 754 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
755 return 1;
756
c68b734f
YW		 757 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
758 return 1;
759
97ec8c06
FW		 760 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
761 return 1;
762
afcbf13f 763 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 764 return 1;
765
b9baba86
HH		 766 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
767 return 1;
768
a03490ed 769 if (is_long_mode(vcpu)) {
0f12244f
GN		 770 if (!(cr4 & X86_CR4_PAE))
771 return 1;
a2edf57f
AK		 772 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
773 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 774 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
775 kvm_read_cr3(vcpu)))
0f12244f
GN		 776 return 1;
777
ad756a16
MJ		 778 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
779 if (!guest_cpuid_has_pcid(vcpu))
780 return 1;
781
782 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
783 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
784 return 1;
785 }
786
5e1746d6 787 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 788 return 1;
a03490ed 789
ad756a16
MJ		 790 if (((cr4 ^ old_cr4) & pdptr_bits) ||
791 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 792 kvm_mmu_reset_context(vcpu);
0f12244f 793
b9baba86 794 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 795 kvm_update_cpuid(vcpu);
2acf923e 796
0f12244f
GN		 797 return 0;
798}
2d3ad1f4 799EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 800
2390218b 801int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 802{
ac146235 803#ifdef CONFIG_X86_64
9d88fca7 804 cr3 &= ~CR3_PCID_INVD;
ac146235 805#endif
9d88fca7 806
9f8fe504 807 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 808 kvm_mmu_sync_roots(vcpu);
77c3913b 809 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 810 return 0;
d835dfec
AK		 811 }
812
a03490ed 813 if (is_long_mode(vcpu)) {
d9f89b88
JK		 814 if (cr3 & CR3_L_MODE_RESERVED_BITS)
815 return 1;
816 } else if (is_pae(vcpu) && is_paging(vcpu) &&
817 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 818 return 1;
a03490ed 819
0f12244f 820 vcpu->arch.cr3 = cr3;
aff48baa 821 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 822 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 823 return 0;
824}
2d3ad1f4 825EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 826
eea1cff9 827int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 828{
0f12244f
GN		 829 if (cr8 & CR8_RESERVED_BITS)
830 return 1;
35754c98 831 if (lapic_in_kernel(vcpu))
a03490ed
CO		 832 kvm_lapic_set_tpr(vcpu, cr8);
833 else
ad312c7c 834 vcpu->arch.cr8 = cr8;
0f12244f
GN		 835 return 0;
836}
2d3ad1f4 837EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 838
2d3ad1f4 839unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 840{
35754c98 841 if (lapic_in_kernel(vcpu))
a03490ed
CO		 842 return kvm_lapic_get_cr8(vcpu);
843 else
ad312c7c 844 return vcpu->arch.cr8;
a03490ed 845}
2d3ad1f4 846EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 847
ae561ede
NA		 848static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
849{
850 int i;
851
852 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
853 for (i = 0; i < KVM_NR_DB_REGS; i++)
854 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
855 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
856 }
857}
858
73aaf249
JK		 859static void kvm_update_dr6(struct kvm_vcpu *vcpu)
860{
861 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
862 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
863}
864
c8639010
JK		 865static void kvm_update_dr7(struct kvm_vcpu *vcpu)
866{
867 unsigned long dr7;
868
869 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
870 dr7 = vcpu->arch.guest_debug_dr7;
871 else
872 dr7 = vcpu->arch.dr7;
873 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 874 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
875 if (dr7 & DR7_BP_EN_MASK)
876 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 877}
878
6f43ed01
NA		 879static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
880{
881 u64 fixed = DR6_FIXED_1;
882
883 if (!guest_cpuid_has_rtm(vcpu))
884 fixed |= DR6_RTM;
885 return fixed;
886}
887
338dbc97 888static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 889{
890 switch (dr) {
891 case 0 ... 3:
892 vcpu->arch.db[dr] = val;
893 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
894 vcpu->arch.eff_db[dr] = val;
895 break;
896 case 4:
020df079
GN		 897 /* fall through */
898 case 6:
338dbc97
GN		 899 if (val & 0xffffffff00000000ULL)
900 return -1; /* #GP */
6f43ed01 901 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 902 kvm_update_dr6(vcpu);
020df079
GN		 903 break;
904 case 5:
020df079
GN		 905 /* fall through */
906 default: /* 7 */
338dbc97
GN		 907 if (val & 0xffffffff00000000ULL)
908 return -1; /* #GP */
020df079 909 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 910 kvm_update_dr7(vcpu);
020df079
GN		 911 break;
912 }
913
914 return 0;
915}
338dbc97
GN		 916
917int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
918{
16f8a6f9 919 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 920 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 921 return 1;
922 }
923 return 0;
338dbc97 924}
020df079
GN		 925EXPORT_SYMBOL_GPL(kvm_set_dr);
926
16f8a6f9 927int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 928{
929 switch (dr) {
930 case 0 ... 3:
931 *val = vcpu->arch.db[dr];
932 break;
933 case 4:
020df079
GN		 934 /* fall through */
935 case 6:
73aaf249
JK		 936 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
937 *val = vcpu->arch.dr6;
938 else
939 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 940 break;
941 case 5:
020df079
GN		 942 /* fall through */
943 default: /* 7 */
944 *val = vcpu->arch.dr7;
945 break;
946 }
338dbc97
GN		 947 return 0;
948}
020df079
GN		 949EXPORT_SYMBOL_GPL(kvm_get_dr);
950
022cd0e8
AK		 951bool kvm_rdpmc(struct kvm_vcpu *vcpu)
952{
953 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
954 u64 data;
955 int err;
956
c6702c9d 957 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 958 if (err)
959 return err;
960 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
961 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
962 return err;
963}
964EXPORT_SYMBOL_GPL(kvm_rdpmc);
965
043405e1
CO		 966/*
967 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
968 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
969 *
970 * This list is modified at module load time to reflect the
e3267cbb 971 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 972 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
973 * may depend on host virtualization features rather than host cpu features.
043405e1 974 */
e3267cbb 975
043405e1
CO		 976static u32 msrs_to_save[] = {
977 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 978 MSR_STAR,
043405e1
CO		 979#ifdef CONFIG_X86_64
980 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
981#endif
b3897a49 982 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 983 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 984};
985
986static unsigned num_msrs_to_save;
987
62ef68bb
PB		 988static u32 emulated_msrs[] = {
989 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
990 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
991 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
992 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 993 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
994 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 995 HV_X64_MSR_RESET,
11c4b1ca 996 HV_X64_MSR_VP_INDEX,
9eec50b8 997 HV_X64_MSR_VP_RUNTIME,
5c919412 998 HV_X64_MSR_SCONTROL,
1f4b34f8 999 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 1000 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1001 MSR_KVM_PV_EOI_EN,
1002
ba904635 1003 MSR_IA32_TSC_ADJUST,
a3e06bbe 1004 MSR_IA32_TSCDEADLINE,
043405e1 1005 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1006 MSR_IA32_MCG_STATUS,
1007 MSR_IA32_MCG_CTL,
c45dcc71 1008 MSR_IA32_MCG_EXT_CTL,
64d60670 1009 MSR_IA32_SMBASE,
043405e1
CO		 1010};
1011
62ef68bb
PB		 1012static unsigned num_emulated_msrs;
1013
384bb783 1014bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1015{
b69e8cae 1016 if (efer & efer_reserved_bits)
384bb783 1017 return false;
15c4a640 1018
1b2fd70c
AG		 1019 if (efer & EFER_FFXSR) {
1020 struct kvm_cpuid_entry2 *feat;
1021
1022 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1023 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 1024 return false;
1b2fd70c
AG		 1025 }
1026
d8017474
AG		 1027 if (efer & EFER_SVME) {
1028 struct kvm_cpuid_entry2 *feat;
1029
1030 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1031 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1032 return false;
d8017474
AG		 1033 }
1034
384bb783
JK		 1035 return true;
1036}
1037EXPORT_SYMBOL_GPL(kvm_valid_efer);
1038
1039static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1040{
1041 u64 old_efer = vcpu->arch.efer;
1042
1043 if (!kvm_valid_efer(vcpu, efer))
1044 return 1;
1045
1046 if (is_paging(vcpu)
1047 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1048 return 1;
1049
15c4a640 1050 efer &= ~EFER_LMA;
f6801dff 1051 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1052
a3d204e2
SY		 1053 kvm_x86_ops->set_efer(vcpu, efer);
1054
aad82703
SY		 1055 /* Update reserved bits */
1056 if ((efer ^ old_efer) & EFER_NX)
1057 kvm_mmu_reset_context(vcpu);
1058
b69e8cae 1059 return 0;
15c4a640
CO		 1060}
1061
f2b4b7dd
JR		 1062void kvm_enable_efer_bits(u64 mask)
1063{
1064 efer_reserved_bits &= ~mask;
1065}
1066EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1067
15c4a640
CO		 1068/*
1069 * Writes msr value into into the appropriate "register".
1070 * Returns 0 on success, non-0 otherwise.
1071 * Assumes vcpu_load() was already called.
1072 */
8fe8ab46 1073int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1074{
854e8bb1
NA		 1075 switch (msr->index) {
1076 case MSR_FS_BASE:
1077 case MSR_GS_BASE:
1078 case MSR_KERNEL_GS_BASE:
1079 case MSR_CSTAR:
1080 case MSR_LSTAR:
1081 if (is_noncanonical_address(msr->data))
1082 return 1;
1083 break;
1084 case MSR_IA32_SYSENTER_EIP:
1085 case MSR_IA32_SYSENTER_ESP:
1086 /*
1087 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1088 * non-canonical address is written on Intel but not on
1089 * AMD (which ignores the top 32-bits, because it does
1090 * not implement 64-bit SYSENTER).
1091 *
1092 * 64-bit code should hence be able to write a non-canonical
1093 * value on AMD. Making the address canonical ensures that
1094 * vmentry does not fail on Intel after writing a non-canonical
1095 * value, and that something deterministic happens if the guest
1096 * invokes 64-bit SYSENTER.
1097 */
1098 msr->data = get_canonical(msr->data);
1099 }
8fe8ab46 1100 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1101}
854e8bb1 1102EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1103
313a3dc7
CO		 1104/*
1105 * Adapt set_msr() to msr_io()'s calling convention
1106 */
609e36d3
PB		 1107static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1108{
1109 struct msr_data msr;
1110 int r;
1111
1112 msr.index = index;
1113 msr.host_initiated = true;
1114 r = kvm_get_msr(vcpu, &msr);
1115 if (r)
1116 return r;
1117
1118 *data = msr.data;
1119 return 0;
1120}
1121
313a3dc7
CO		 1122static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1123{
8fe8ab46
WA		 1124 struct msr_data msr;
1125
1126 msr.data = *data;
1127 msr.index = index;
1128 msr.host_initiated = true;
1129 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1130}
1131
16e8d74d
MT		 1132#ifdef CONFIG_X86_64
1133struct pvclock_gtod_data {
1134 seqcount_t seq;
1135
1136 struct { /* extract of a clocksource struct */
1137 int vclock_mode;
a5a1d1c2
TG		 1138 u64 cycle_last;
1139 u64 mask;
16e8d74d
MT		 1140 u32 mult;
1141 u32 shift;
1142 } clock;
1143
cbcf2dd3
TG		 1144 u64 boot_ns;
1145 u64 nsec_base;
55dd00a7 1146 u64 wall_time_sec;
16e8d74d
MT		 1147};
1148
1149static struct pvclock_gtod_data pvclock_gtod_data;
1150
1151static void update_pvclock_gtod(struct timekeeper *tk)
1152{
1153 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1154 u64 boot_ns;
1155
876e7881 1156 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1157
1158 write_seqcount_begin(&vdata->seq);
1159
1160 /* copy pvclock gtod data */
876e7881
PZ		 1161 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1162 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1163 vdata->clock.mask = tk->tkr_mono.mask;
1164 vdata->clock.mult = tk->tkr_mono.mult;
1165 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1166
cbcf2dd3 1167 vdata->boot_ns = boot_ns;
876e7881 1168 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1169
55dd00a7
MT		 1170 vdata->wall_time_sec = tk->xtime_sec;
1171
16e8d74d
MT		 1172 write_seqcount_end(&vdata->seq);
1173}
1174#endif
1175
bab5bb39
NK		 1176void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1177{
1178 /*
1179 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1180 * vcpu_enter_guest. This function is only called from
1181 * the physical CPU that is running vcpu.
1182 */
1183 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1184}
16e8d74d 1185
18068523
GOC		 1186static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1187{
9ed3c444
AK		 1188 int version;
1189 int r;
50d0a0f9 1190 struct pvclock_wall_clock wc;
87aeb54f 1191 struct timespec64 boot;
18068523
GOC		 1192
1193 if (!wall_clock)
1194 return;
1195
9ed3c444
AK		 1196 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1197 if (r)
1198 return;
1199
1200 if (version & 1)
1201 ++version; /* first time write, random junk */
1202
1203 ++version;
18068523 1204
1dab1345
NK		 1205 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1206 return;
18068523 1207
50d0a0f9
GH		 1208 /*
1209 * The guest calculates current wall clock time by adding
34c238a1 1210 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1211 * wall clock specified here. guest system time equals host
1212 * system time for us, thus we must fill in host boot time here.
1213 */
87aeb54f 1214 getboottime64(&boot);
50d0a0f9 1215
4b648665 1216 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1217 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1218 boot = timespec64_sub(boot, ts);
4b648665 1219 }
87aeb54f 1220 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1221 wc.nsec = boot.tv_nsec;
1222 wc.version = version;
18068523
GOC		 1223
1224 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1225
1226 version++;
1227 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1228}
1229
50d0a0f9
GH		 1230static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1231{
b51012de
PB		 1232 do_shl32_div32(dividend, divisor);
1233 return dividend;
50d0a0f9
GH		 1234}
1235
3ae13faa 1236static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1237 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1238{
5f4e3f88 1239 uint64_t scaled64;
50d0a0f9
GH		 1240 int32_t shift = 0;
1241 uint64_t tps64;
1242 uint32_t tps32;
1243
3ae13faa
PB		 1244 tps64 = base_hz;
1245 scaled64 = scaled_hz;
50933623 1246 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1247 tps64 >>= 1;
1248 shift--;
1249 }
1250
1251 tps32 = (uint32_t)tps64;
50933623
JK		 1252 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1253 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1254 scaled64 >>= 1;
1255 else
1256 tps32 <<= 1;
50d0a0f9
GH		 1257 shift++;
1258 }
1259
5f4e3f88
ZA		 1260 *pshift = shift;
1261 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1262
3ae13faa
PB		 1263 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1264 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1265}
1266
d828199e 1267#ifdef CONFIG_X86_64
16e8d74d 1268static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1269#endif
16e8d74d 1270
c8076604 1271static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1272static unsigned long max_tsc_khz;
c8076604 1273
cc578287 1274static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1275{
cc578287
ZA		 1276 u64 v = (u64)khz * (1000000 + ppm);
1277 do_div(v, 1000000);
1278 return v;
1e993611
JR		 1279}
1280
381d585c
HZ		 1281static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1282{
1283 u64 ratio;
1284
1285 /* Guest TSC same frequency as host TSC? */
1286 if (!scale) {
1287 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1288 return 0;
1289 }
1290
1291 /* TSC scaling supported? */
1292 if (!kvm_has_tsc_control) {
1293 if (user_tsc_khz > tsc_khz) {
1294 vcpu->arch.tsc_catchup = 1;
1295 vcpu->arch.tsc_always_catchup = 1;
1296 return 0;
1297 } else {
1298 WARN(1, "user requested TSC rate below hardware speed\n");
1299 return -1;
1300 }
1301 }
1302
1303 /* TSC scaling required - calculate ratio */
1304 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1305 user_tsc_khz, tsc_khz);
1306
1307 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1308 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1309 user_tsc_khz);
1310 return -1;
1311 }
1312
1313 vcpu->arch.tsc_scaling_ratio = ratio;
1314 return 0;
1315}
1316
4941b8cb 1317static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1318{
cc578287
ZA		 1319 u32 thresh_lo, thresh_hi;
1320 int use_scaling = 0;
217fc9cf 1321
03ba32ca 1322 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1323 if (user_tsc_khz == 0) {
ad721883
HZ		 1324 /* set tsc_scaling_ratio to a safe value */
1325 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1326 return -1;
ad721883 1327 }
03ba32ca 1328
c285545f 1329 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1330 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1331 &vcpu->arch.virtual_tsc_shift,
1332 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1333 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1334
1335 /*
1336 * Compute the variation in TSC rate which is acceptable
1337 * within the range of tolerance and decide if the
1338 * rate being applied is within that bounds of the hardware
1339 * rate. If so, no scaling or compensation need be done.
1340 */
1341 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1342 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1343 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1344 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1345 use_scaling = 1;
1346 }
4941b8cb 1347 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1348}
1349
1350static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1351{
e26101b1 1352 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1353 vcpu->arch.virtual_tsc_mult,
1354 vcpu->arch.virtual_tsc_shift);
e26101b1 1355 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1356 return tsc;
1357}
1358
69b0049a 1359static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1360{
1361#ifdef CONFIG_X86_64
1362 bool vcpus_matched;
b48aa97e
MT		 1363 struct kvm_arch *ka = &vcpu->kvm->arch;
1364 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1365
1366 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1367 atomic_read(&vcpu->kvm->online_vcpus));
1368
7f187922
MT		 1369 /*
1370 * Once the masterclock is enabled, always perform request in
1371 * order to update it.
1372 *
1373 * In order to enable masterclock, the host clocksource must be TSC
1374 * and the vcpus need to have matched TSCs. When that happens,
1375 * perform request to enable masterclock.
1376 */
1377 if (ka->use_master_clock ||
1378 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1379 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1380
1381 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1382 atomic_read(&vcpu->kvm->online_vcpus),
1383 ka->use_master_clock, gtod->clock.vclock_mode);
1384#endif
1385}
1386
ba904635
WA		 1387static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1388{
3e3f5026 1389 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1390 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1391}
1392
35181e86
HZ		 1393/*
1394 * Multiply tsc by a fixed point number represented by ratio.
1395 *
1396 * The most significant 64-N bits (mult) of ratio represent the
1397 * integral part of the fixed point number; the remaining N bits
1398 * (frac) represent the fractional part, ie. ratio represents a fixed
1399 * point number (mult + frac * 2^(-N)).
1400 *
1401 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1402 */
1403static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1404{
1405 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1406}
1407
1408u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1409{
1410 u64 _tsc = tsc;
1411 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1412
1413 if (ratio != kvm_default_tsc_scaling_ratio)
1414 _tsc = __scale_tsc(ratio, tsc);
1415
1416 return _tsc;
1417}
1418EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1419
07c1419a
HZ		 1420static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1421{
1422 u64 tsc;
1423
1424 tsc = kvm_scale_tsc(vcpu, rdtsc());
1425
1426 return target_tsc - tsc;
1427}
1428
4ba76538
HZ		 1429u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1430{
ea26e4ec 1431 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1432}
1433EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1434
a545ab6a
LC		 1435static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1436{
1437 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1438 vcpu->arch.tsc_offset = offset;
1439}
1440
8fe8ab46 1441void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1442{
1443 struct kvm *kvm = vcpu->kvm;
f38e098f 1444 u64 offset, ns, elapsed;
99e3e30a 1445 unsigned long flags;
02626b6a 1446 s64 usdiff;
b48aa97e 1447 bool matched;
0d3da0d2 1448 bool already_matched;
8fe8ab46 1449 u64 data = msr->data;
99e3e30a 1450
038f8c11 1451 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1452 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1453 ns = ktime_get_boot_ns();
f38e098f 1454 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1455
03ba32ca 1456 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1457 int faulted = 0;
1458
03ba32ca
MT		 1459 /* n.b - signed multiplication and division required */
1460 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1461#ifdef CONFIG_X86_64
03ba32ca 1462 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1463#else
03ba32ca 1464 /* do_div() only does unsigned */
8915aa27
MT		 1465 asm("1: idivl %[divisor]\n"
1466 "2: xor %%edx, %%edx\n"
1467 " movl $0, %[faulted]\n"
1468 "3:\n"
1469 ".section .fixup,\"ax\"\n"
1470 "4: movl $1, %[faulted]\n"
1471 " jmp 3b\n"
1472 ".previous\n"
1473
1474 _ASM_EXTABLE(1b, 4b)
1475
1476 : "=A"(usdiff), [faulted] "=r" (faulted)
1477 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1478
5d3cb0f6 1479#endif
03ba32ca
MT		 1480 do_div(elapsed, 1000);
1481 usdiff -= elapsed;
1482 if (usdiff < 0)
1483 usdiff = -usdiff;
8915aa27
MT		 1484
1485 /* idivl overflow => difference is larger than USEC_PER_SEC */
1486 if (faulted)
1487 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1488 } else
1489 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1490
1491 /*
5d3cb0f6
ZA		 1492 * Special case: TSC write with a small delta (1 second) of virtual
1493 * cycle time against real time is interpreted as an attempt to
1494 * synchronize the CPU.
1495 *
1496 * For a reliable TSC, we can match TSC offsets, and for an unstable
1497 * TSC, we add elapsed time in this computation. We could let the
1498 * compensation code attempt to catch up if we fall behind, but
1499 * it's better to try to match offsets from the beginning.
1500 */
02626b6a 1501 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1502 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1503 if (!check_tsc_unstable()) {
e26101b1 1504 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1505 pr_debug("kvm: matched tsc offset for %llu\n", data);
1506 } else {
857e4099 1507 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1508 data += delta;
07c1419a 1509 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1510 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1511 }
b48aa97e 1512 matched = true;
0d3da0d2 1513 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1514 } else {
1515 /*
1516 * We split periods of matched TSC writes into generations.
1517 * For each generation, we track the original measured
1518 * nanosecond time, offset, and write, so if TSCs are in
1519 * sync, we can match exact offset, and if not, we can match
4a969980 1520 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1521 *
1522 * These values are tracked in kvm->arch.cur_xxx variables.
1523 */
1524 kvm->arch.cur_tsc_generation++;
1525 kvm->arch.cur_tsc_nsec = ns;
1526 kvm->arch.cur_tsc_write = data;
1527 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1528 matched = false;
0d3da0d2 1529 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1530 kvm->arch.cur_tsc_generation, data);
f38e098f 1531 }
e26101b1
ZA		 1532
1533 /*
1534 * We also track th most recent recorded KHZ, write and time to
1535 * allow the matching interval to be extended at each write.
1536 */
f38e098f
ZA		 1537 kvm->arch.last_tsc_nsec = ns;
1538 kvm->arch.last_tsc_write = data;
5d3cb0f6 1539 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1540
b183aa58 1541 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1542
1543 /* Keep track of which generation this VCPU has synchronized to */
1544 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1545 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1546 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1547
ba904635
WA		 1548 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1549 update_ia32_tsc_adjust_msr(vcpu, offset);
a545ab6a 1550 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1551 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1552
1553 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1554 if (!matched) {
b48aa97e 1555 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1556 } else if (!already_matched) {
1557 kvm->arch.nr_vcpus_matched_tsc++;
1558 }
b48aa97e
MT		 1559
1560 kvm_track_tsc_matching(vcpu);
1561 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1562}
e26101b1 1563
99e3e30a
ZA		 1564EXPORT_SYMBOL_GPL(kvm_write_tsc);
1565
58ea6767
HZ		 1566static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1567 s64 adjustment)
1568{
ea26e4ec 1569 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1570}
1571
1572static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1573{
1574 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1575 WARN_ON(adjustment < 0);
1576 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1577 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1578}
1579
d828199e
MT		 1580#ifdef CONFIG_X86_64
1581
a5a1d1c2 1582static u64 read_tsc(void)
d828199e 1583{
a5a1d1c2 1584 u64 ret = (u64)rdtsc_ordered();
03b9730b 1585 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1586
1587 if (likely(ret >= last))
1588 return ret;
1589
1590 /*
1591 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1592 * predictable (it's just a function of time and the likely is
d828199e
MT		 1593 * very likely) and there's a data dependence, so force GCC
1594 * to generate a branch instead. I don't barrier() because
1595 * we don't actually need a barrier, and if this function
1596 * ever gets inlined it will generate worse code.
1597 */
1598 asm volatile ("");
1599 return last;
1600}
1601
a5a1d1c2 1602static inline u64 vgettsc(u64 *cycle_now)
d828199e
MT		 1603{
1604 long v;
1605 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1606
1607 *cycle_now = read_tsc();
1608
1609 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1610 return v * gtod->clock.mult;
1611}
1612
a5a1d1c2 1613static int do_monotonic_boot(s64 *t, u64 *cycle_now)
d828199e 1614{
cbcf2dd3 1615 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1616 unsigned long seq;
d828199e 1617 int mode;
cbcf2dd3 1618 u64 ns;
d828199e 1619
d828199e
MT		 1620 do {
1621 seq = read_seqcount_begin(&gtod->seq);
1622 mode = gtod->clock.vclock_mode;
cbcf2dd3 1623 ns = gtod->nsec_base;
d828199e
MT		 1624 ns += vgettsc(cycle_now);
1625 ns >>= gtod->clock.shift;
cbcf2dd3 1626 ns += gtod->boot_ns;
d828199e 1627 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1628 *t = ns;
d828199e
MT		 1629
1630 return mode;
1631}
1632
55dd00a7
MT		 1633static int do_realtime(struct timespec *ts, u64 *cycle_now)
1634{
1635 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1636 unsigned long seq;
1637 int mode;
1638 u64 ns;
1639
1640 do {
1641 seq = read_seqcount_begin(&gtod->seq);
1642 mode = gtod->clock.vclock_mode;
1643 ts->tv_sec = gtod->wall_time_sec;
1644 ns = gtod->nsec_base;
1645 ns += vgettsc(cycle_now);
1646 ns >>= gtod->clock.shift;
1647 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1648
1649 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1650 ts->tv_nsec = ns;
1651
1652 return mode;
1653}
1654
d828199e 1655/* returns true if host is using tsc clocksource */
a5a1d1c2 1656static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
d828199e 1657{
d828199e
MT		 1658 /* checked again under seqlock below */
1659 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1660 return false;
1661
cbcf2dd3 1662 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e 1663}
55dd00a7
MT		 1664
1665/* returns true if host is using tsc clocksource */
1666static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1667 u64 *cycle_now)
1668{
1669 /* checked again under seqlock below */
1670 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1671 return false;
1672
1673 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1674}
d828199e
MT		 1675#endif
1676
1677/*
1678 *
b48aa97e
MT		 1679 * Assuming a stable TSC across physical CPUS, and a stable TSC
1680 * across virtual CPUs, the following condition is possible.
1681 * Each numbered line represents an event visible to both
d828199e
MT		 1682 * CPUs at the next numbered event.
1683 *
1684 * "timespecX" represents host monotonic time. "tscX" represents
1685 * RDTSC value.
1686 *
1687 * VCPU0 on CPU0 | VCPU1 on CPU1
1688 *
1689 * 1. read timespec0,tsc0
1690 * 2. | timespec1 = timespec0 + N
1691 * | tsc1 = tsc0 + M
1692 * 3. transition to guest | transition to guest
1693 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1694 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1695 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1696 *
1697 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1698 *
1699 * - ret0 < ret1
1700 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1701 * ...
1702 * - 0 < N - M => M < N
1703 *
1704 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1705 * always the case (the difference between two distinct xtime instances
1706 * might be smaller then the difference between corresponding TSC reads,
1707 * when updating guest vcpus pvclock areas).
1708 *
1709 * To avoid that problem, do not allow visibility of distinct
1710 * system_timestamp/tsc_timestamp values simultaneously: use a master
1711 * copy of host monotonic time values. Update that master copy
1712 * in lockstep.
1713 *
b48aa97e 1714 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1715 *
1716 */
1717
1718static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1719{
1720#ifdef CONFIG_X86_64
1721 struct kvm_arch *ka = &kvm->arch;
1722 int vclock_mode;
b48aa97e
MT		 1723 bool host_tsc_clocksource, vcpus_matched;
1724
1725 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1726 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1727
1728 /*
1729 * If the host uses TSC clock, then passthrough TSC as stable
1730 * to the guest.
1731 */
b48aa97e 1732 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1733 &ka->master_kernel_ns,
1734 &ka->master_cycle_now);
1735
16a96021 1736 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1737 && !backwards_tsc_observed
1738 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1739
d828199e
MT		 1740 if (ka->use_master_clock)
1741 atomic_set(&kvm_guest_has_master_clock, 1);
1742
1743 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1744 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1745 vcpus_matched);
d828199e
MT		 1746#endif
1747}
1748
2860c4b1
PB		 1749void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1750{
1751 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1752}
1753
2e762ff7
MT		 1754static void kvm_gen_update_masterclock(struct kvm *kvm)
1755{
1756#ifdef CONFIG_X86_64
1757 int i;
1758 struct kvm_vcpu *vcpu;
1759 struct kvm_arch *ka = &kvm->arch;
1760
1761 spin_lock(&ka->pvclock_gtod_sync_lock);
1762 kvm_make_mclock_inprogress_request(kvm);
1763 /* no guest entries from this point */
1764 pvclock_update_vm_gtod_copy(kvm);
1765
1766 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1767 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1768
1769 /* guest entries allowed */
1770 kvm_for_each_vcpu(i, vcpu, kvm)
1771 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1772
1773 spin_unlock(&ka->pvclock_gtod_sync_lock);
1774#endif
1775}
1776
108b249c
PB		 1777static u64 __get_kvmclock_ns(struct kvm *kvm)
1778{
108b249c 1779 struct kvm_arch *ka = &kvm->arch;
8b953440 1780 struct pvclock_vcpu_time_info hv_clock;
108b249c 1781
8b953440
PB		 1782 spin_lock(&ka->pvclock_gtod_sync_lock);
1783 if (!ka->use_master_clock) {
1784 spin_unlock(&ka->pvclock_gtod_sync_lock);
1785 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1786 }
1787
8b953440
PB		 1788 hv_clock.tsc_timestamp = ka->master_cycle_now;
1789 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1790 spin_unlock(&ka->pvclock_gtod_sync_lock);
1791
1792 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1793 &hv_clock.tsc_shift,
1794 &hv_clock.tsc_to_system_mul);
1795 return __pvclock_read_cycles(&hv_clock, rdtsc());
108b249c
PB		 1796}
1797
1798u64 get_kvmclock_ns(struct kvm *kvm)
1799{
1800 unsigned long flags;
1801 s64 ns;
1802
1803 local_irq_save(flags);
1804 ns = __get_kvmclock_ns(kvm);
1805 local_irq_restore(flags);
1806
1807 return ns;
1808}
1809
0d6dd2ff
PB		 1810static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1811{
1812 struct kvm_vcpu_arch *vcpu = &v->arch;
1813 struct pvclock_vcpu_time_info guest_hv_clock;
1814
bbd64115 1815 if (unlikely(kvm_vcpu_read_guest_cached(v, &vcpu->pv_time,
0d6dd2ff
PB		 1816 &guest_hv_clock, sizeof(guest_hv_clock))))
1817 return;
1818
1819 /* This VCPU is paused, but it's legal for a guest to read another
1820 * VCPU's kvmclock, so we really have to follow the specification where
1821 * it says that version is odd if data is being modified, and even after
1822 * it is consistent.
1823 *
1824 * Version field updates must be kept separate. This is because
1825 * kvm_write_guest_cached might use a "rep movs" instruction, and
1826 * writes within a string instruction are weakly ordered. So there
1827 * are three writes overall.
1828 *
1829 * As a small optimization, only write the version field in the first
1830 * and third write. The vcpu->pv_time cache is still valid, because the
1831 * version field is the first in the struct.
1832 */
1833 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1834
1835 vcpu->hv_clock.version = guest_hv_clock.version + 1;
bbd64115
CL		 1836 kvm_vcpu_write_guest_cached(v, &vcpu->pv_time,
1837 &vcpu->hv_clock,
1838 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1839
1840 smp_wmb();
1841
1842 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1843 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1844
1845 if (vcpu->pvclock_set_guest_stopped_request) {
1846 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1847 vcpu->pvclock_set_guest_stopped_request = false;
1848 }
1849
1850 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1851
bbd64115
CL		 1852 kvm_vcpu_write_guest_cached(v, &vcpu->pv_time,
1853 &vcpu->hv_clock,
1854 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1855
1856 smp_wmb();
1857
1858 vcpu->hv_clock.version++;
bbd64115
CL		 1859 kvm_vcpu_write_guest_cached(v, &vcpu->pv_time,
1860 &vcpu->hv_clock,
1861 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1862}
1863
34c238a1 1864static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1865{
78db6a50 1866 unsigned long flags, tgt_tsc_khz;
18068523 1867 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1868 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1869 s64 kernel_ns;
d828199e 1870 u64 tsc_timestamp, host_tsc;
51d59c6b 1871 u8 pvclock_flags;
d828199e
MT		 1872 bool use_master_clock;
1873
1874 kernel_ns = 0;
1875 host_tsc = 0;
18068523 1876
d828199e
MT		 1877 /*
1878 * If the host uses TSC clock, then passthrough TSC as stable
1879 * to the guest.
1880 */
1881 spin_lock(&ka->pvclock_gtod_sync_lock);
1882 use_master_clock = ka->use_master_clock;
1883 if (use_master_clock) {
1884 host_tsc = ka->master_cycle_now;
1885 kernel_ns = ka->master_kernel_ns;
1886 }
1887 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1888
1889 /* Keep irq disabled to prevent changes to the clock */
1890 local_irq_save(flags);
78db6a50
PB		 1891 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1892 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1893 local_irq_restore(flags);
1894 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1895 return 1;
1896 }
d828199e 1897 if (!use_master_clock) {
4ea1636b 1898 host_tsc = rdtsc();
108b249c 1899 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1900 }
1901
4ba76538 1902 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1903
c285545f
ZA		 1904 /*
1905 * We may have to catch up the TSC to match elapsed wall clock
1906 * time for two reasons, even if kvmclock is used.
1907 * 1) CPU could have been running below the maximum TSC rate
1908 * 2) Broken TSC compensation resets the base at each VCPU
1909 * entry to avoid unknown leaps of TSC even when running
1910 * again on the same CPU. This may cause apparent elapsed
1911 * time to disappear, and the guest to stand still or run
1912 * very slowly.
1913 */
1914 if (vcpu->tsc_catchup) {
1915 u64 tsc = compute_guest_tsc(v, kernel_ns);
1916 if (tsc > tsc_timestamp) {
f1e2b260 1917 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1918 tsc_timestamp = tsc;
1919 }
50d0a0f9
GH		 1920 }
1921
18068523
GOC		 1922 local_irq_restore(flags);
1923
0d6dd2ff 1924 /* With all the info we got, fill in the values */
18068523 1925
78db6a50
PB		 1926 if (kvm_has_tsc_control)
1927 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1928
1929 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1930 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1931 &vcpu->hv_clock.tsc_shift,
1932 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1933 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1934 }
1935
1d5f066e 1936 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1937 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1938 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1939
d828199e 1940 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 1941 pvclock_flags = 0;
d828199e
MT		 1942 if (use_master_clock)
1943 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1944
78c0337a
MT		 1945 vcpu->hv_clock.flags = pvclock_flags;
1946
095cf55d
PB		 1947 if (vcpu->pv_time_enabled)
1948 kvm_setup_pvclock_page(v);
1949 if (v == kvm_get_vcpu(v->kvm, 0))
1950 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 1951 return 0;
c8076604
GH		 1952}
1953
0061d53d
MT		 1954/*
1955 * kvmclock updates which are isolated to a given vcpu, such as
1956 * vcpu->cpu migration, should not allow system_timestamp from
1957 * the rest of the vcpus to remain static. Otherwise ntp frequency
1958 * correction applies to one vcpu's system_timestamp but not
1959 * the others.
1960 *
1961 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1962 * We need to rate-limit these requests though, as they can
1963 * considerably slow guests that have a large number of vcpus.
1964 * The time for a remote vcpu to update its kvmclock is bound
1965 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1966 */
1967
7e44e449
AJ		 1968#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1969
1970static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1971{
1972 int i;
7e44e449
AJ		 1973 struct delayed_work *dwork = to_delayed_work(work);
1974 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1975 kvmclock_update_work);
1976 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1977 struct kvm_vcpu *vcpu;
1978
1979 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1980 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1981 kvm_vcpu_kick(vcpu);
1982 }
1983}
1984
7e44e449
AJ		 1985static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1986{
1987 struct kvm *kvm = v->kvm;
1988
105b21bb 1989 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1990 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1991 KVMCLOCK_UPDATE_DELAY);
1992}
1993
332967a3
AJ		 1994#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1995
1996static void kvmclock_sync_fn(struct work_struct *work)
1997{
1998 struct delayed_work *dwork = to_delayed_work(work);
1999 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2000 kvmclock_sync_work);
2001 struct kvm *kvm = container_of(ka, struct kvm, arch);
2002
630994b3
MT		 2003 if (!kvmclock_periodic_sync)
2004 return;
2005
332967a3
AJ		 2006 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2007 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2008 KVMCLOCK_SYNC_PERIOD);
2009}
2010
890ca9ae 2011static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 2012{
890ca9ae
HY		 2013 u64 mcg_cap = vcpu->arch.mcg_cap;
2014 unsigned bank_num = mcg_cap & 0xff;
2015
15c4a640 2016 switch (msr) {
15c4a640 2017 case MSR_IA32_MCG_STATUS:
890ca9ae 2018 vcpu->arch.mcg_status = data;
15c4a640 2019 break;
c7ac679c 2020 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2021 if (!(mcg_cap & MCG_CTL_P))
2022 return 1;
2023 if (data != 0 && data != ~(u64)0)
2024 return -1;
2025 vcpu->arch.mcg_ctl = data;
2026 break;
2027 default:
2028 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2029 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2030 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2031 /* only 0 or all 1s can be written to IA32_MCi_CTL
2032 * some Linux kernels though clear bit 10 in bank 4 to
2033 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2034 * this to avoid an uncatched #GP in the guest
2035 */
890ca9ae 2036 if ((offset & 0x3) == 0 &&
114be429 2037 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 2038 return -1;
2039 vcpu->arch.mce_banks[offset] = data;
2040 break;
2041 }
2042 return 1;
2043 }
2044 return 0;
2045}
2046
ffde22ac
ES		 2047static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2048{
2049 struct kvm *kvm = vcpu->kvm;
2050 int lm = is_long_mode(vcpu);
2051 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2052 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2053 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2054 : kvm->arch.xen_hvm_config.blob_size_32;
2055 u32 page_num = data & ~PAGE_MASK;
2056 u64 page_addr = data & PAGE_MASK;
2057 u8 *page;
2058 int r;
2059
2060 r = -E2BIG;
2061 if (page_num >= blob_size)
2062 goto out;
2063 r = -ENOMEM;
ff5c2c03
SL		 2064 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2065 if (IS_ERR(page)) {
2066 r = PTR_ERR(page);
ffde22ac 2067 goto out;
ff5c2c03 2068 }
54bf36aa 2069 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2070 goto out_free;
2071 r = 0;
2072out_free:
2073 kfree(page);
2074out:
2075 return r;
2076}
2077
344d9588
GN		 2078static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2079{
2080 gpa_t gpa = data & ~0x3f;
2081
4a969980 2082 /* Bits 2:5 are reserved, Should be zero */
6adba527 2083 if (data & 0x3c)
344d9588
GN		 2084 return 1;
2085
2086 vcpu->arch.apf.msr_val = data;
2087
2088 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2089 kvm_clear_async_pf_completion_queue(vcpu);
2090 kvm_async_pf_hash_reset(vcpu);
2091 return 0;
2092 }
2093
bbd64115 2094 if (kvm_vcpu_gfn_to_hva_cache_init(vcpu, &vcpu->arch.apf.data, gpa,
8f964525 2095 sizeof(u32)))
344d9588
GN		 2096 return 1;
2097
6adba527 2098 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2099 kvm_async_pf_wakeup_all(vcpu);
2100 return 0;
2101}
2102
12f9a48f
GC		 2103static void kvmclock_reset(struct kvm_vcpu *vcpu)
2104{
0b79459b 2105 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2106}
2107
c9aaa895
GC		 2108static void record_steal_time(struct kvm_vcpu *vcpu)
2109{
2110 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2111 return;
2112
bbd64115 2113 if (unlikely(kvm_vcpu_read_guest_cached(vcpu, &vcpu->arch.st.stime,
c9aaa895
GC		 2114 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2115 return;
2116
0b9f6c46
PX		 2117 vcpu->arch.st.steal.preempted = 0;
2118
35f3fae1
WL		 2119 if (vcpu->arch.st.steal.version & 1)
2120 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2121
2122 vcpu->arch.st.steal.version += 1;
2123
bbd64115 2124 kvm_vcpu_write_guest_cached(vcpu, &vcpu->arch.st.stime,
35f3fae1
WL		 2125 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2126
2127 smp_wmb();
2128
c54cdf14
LC		 2129 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2130 vcpu->arch.st.last_steal;
2131 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2132
bbd64115 2133 kvm_vcpu_write_guest_cached(vcpu, &vcpu->arch.st.stime,
35f3fae1
WL		 2134 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2135
2136 smp_wmb();
2137
2138 vcpu->arch.st.steal.version += 1;
c9aaa895 2139
bbd64115 2140 kvm_vcpu_write_guest_cached(vcpu, &vcpu->arch.st.stime,
c9aaa895
GC		 2141 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2142}
2143
8fe8ab46 2144int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2145{
5753785f 2146 bool pr = false;
8fe8ab46
WA		 2147 u32 msr = msr_info->index;
2148 u64 data = msr_info->data;
5753785f 2149
15c4a640 2150 switch (msr) {
2e32b719
BP		 2151 case MSR_AMD64_NB_CFG:
2152 case MSR_IA32_UCODE_REV:
2153 case MSR_IA32_UCODE_WRITE:
2154 case MSR_VM_HSAVE_PA:
2155 case MSR_AMD64_PATCH_LOADER:
2156 case MSR_AMD64_BU_CFG2:
2157 break;
2158
15c4a640 2159 case MSR_EFER:
b69e8cae 2160 return set_efer(vcpu, data);
8f1589d9
AP		 2161 case MSR_K7_HWCR:
2162 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2163 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2164 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2165 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2166 if (data != 0) {
a737f256
CD		 2167 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2168 data);
8f1589d9
AP		 2169 return 1;
2170 }
15c4a640 2171 break;
f7c6d140
AP		 2172 case MSR_FAM10H_MMIO_CONF_BASE:
2173 if (data != 0) {
a737f256
CD		 2174 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2175 "0x%llx\n", data);
f7c6d140
AP		 2176 return 1;
2177 }
15c4a640 2178 break;
b5e2fec0
AG		 2179 case MSR_IA32_DEBUGCTLMSR:
2180 if (!data) {
2181 /* We support the non-activated case already */
2182 break;
2183 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2184 /* Values other than LBR and BTF are vendor-specific,
2185 thus reserved and should throw a #GP */
2186 return 1;
2187 }
a737f256
CD		 2188 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2189 __func__, data);
b5e2fec0 2190 break;
9ba075a6 2191 case 0x200 ... 0x2ff:
ff53604b 2192 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2193 case MSR_IA32_APICBASE:
58cb628d 2194 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2195 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2196 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2197 case MSR_IA32_TSCDEADLINE:
2198 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2199 break;
ba904635
WA		 2200 case MSR_IA32_TSC_ADJUST:
2201 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2202 if (!msr_info->host_initiated) {
d913b904 2203 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2204 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2205 }
2206 vcpu->arch.ia32_tsc_adjust_msr = data;
2207 }
2208 break;
15c4a640 2209 case MSR_IA32_MISC_ENABLE:
ad312c7c 2210 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2211 break;
64d60670
PB		 2212 case MSR_IA32_SMBASE:
2213 if (!msr_info->host_initiated)
2214 return 1;
2215 vcpu->arch.smbase = data;
2216 break;
11c6bffa 2217 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2218 case MSR_KVM_WALL_CLOCK:
2219 vcpu->kvm->arch.wall_clock = data;
2220 kvm_write_wall_clock(vcpu->kvm, data);
2221 break;
11c6bffa 2222 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2223 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2224 struct kvm_arch *ka = &vcpu->kvm->arch;
2225
12f9a48f 2226 kvmclock_reset(vcpu);
18068523 2227
54750f2c
MT		 2228 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2229 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2230
2231 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2232 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2233 &vcpu->requests);
2234
2235 ka->boot_vcpu_runs_old_kvmclock = tmp;
2236 }
2237
18068523 2238 vcpu->arch.time = data;
0061d53d 2239 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2240
2241 /* we verify if the enable bit is set... */
2242 if (!(data & 1))
2243 break;
2244
bbd64115 2245 if (kvm_vcpu_gfn_to_hva_cache_init(vcpu,
8f964525
AH		 2246 &vcpu->arch.pv_time, data & ~1ULL,
2247 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2248 vcpu->arch.pv_time_enabled = false;
2249 else
2250 vcpu->arch.pv_time_enabled = true;
32cad84f 2251
18068523
GOC		 2252 break;
2253 }
344d9588
GN		 2254 case MSR_KVM_ASYNC_PF_EN:
2255 if (kvm_pv_enable_async_pf(vcpu, data))
2256 return 1;
2257 break;
c9aaa895
GC		 2258 case MSR_KVM_STEAL_TIME:
2259
2260 if (unlikely(!sched_info_on()))
2261 return 1;
2262
2263 if (data & KVM_STEAL_RESERVED_MASK)
2264 return 1;
2265
bbd64115 2266 if (kvm_vcpu_gfn_to_hva_cache_init(vcpu, &vcpu->arch.st.stime,
8f964525
AH		 2267 data & KVM_STEAL_VALID_BITS,
2268 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2269 return 1;
2270
2271 vcpu->arch.st.msr_val = data;
2272
2273 if (!(data & KVM_MSR_ENABLED))
2274 break;
2275
c9aaa895
GC		 2276 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2277
2278 break;
ae7a2a3f
MT		 2279 case MSR_KVM_PV_EOI_EN:
2280 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2281 return 1;
2282 break;
c9aaa895 2283
890ca9ae
HY		 2284 case MSR_IA32_MCG_CTL:
2285 case MSR_IA32_MCG_STATUS:
81760dcc 2286 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2287 return set_msr_mce(vcpu, msr, data);
71db6023 2288
6912ac32
WH		 2289 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2290 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2291 pr = true; /* fall through */
2292 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2293 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2294 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2295 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2296
2297 if (pr || data != 0)
a737f256
CD		 2298 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2299 "0x%x data 0x%llx\n", msr, data);
5753785f 2300 break;
84e0cefa
JS		 2301 case MSR_K7_CLK_CTL:
2302 /*
2303 * Ignore all writes to this no longer documented MSR.
2304 * Writes are only relevant for old K7 processors,
2305 * all pre-dating SVM, but a recommended workaround from
4a969980 2306 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2307 * affected processor models on the command line, hence
2308 * the need to ignore the workaround.
2309 */
2310 break;
55cd8e5a 2311 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2312 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2313 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2314 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2315 return kvm_hv_set_msr_common(vcpu, msr, data,
2316 msr_info->host_initiated);
91c9c3ed 2317 case MSR_IA32_BBL_CR_CTL3:
2318 /* Drop writes to this legacy MSR -- see rdmsr
2319 * counterpart for further detail.
2320 */
796f4687 2321 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", msr, data);
91c9c3ed 2322 break;
2b036c6b
BO		 2323 case MSR_AMD64_OSVW_ID_LENGTH:
2324 if (!guest_cpuid_has_osvw(vcpu))
2325 return 1;
2326 vcpu->arch.osvw.length = data;
2327 break;
2328 case MSR_AMD64_OSVW_STATUS:
2329 if (!guest_cpuid_has_osvw(vcpu))
2330 return 1;
2331 vcpu->arch.osvw.status = data;
2332 break;
15c4a640 2333 default:
ffde22ac
ES		 2334 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2335 return xen_hvm_config(vcpu, data);
c6702c9d 2336 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2337 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2338 if (!ignore_msrs) {
ae0f5499 2339 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2340 msr, data);
ed85c068
AP		 2341 return 1;
2342 } else {
796f4687 2343 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
a737f256 2344 msr, data);
ed85c068
AP		 2345 break;
2346 }
15c4a640
CO		 2347 }
2348 return 0;
2349}
2350EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2351
2352
2353/*
2354 * Reads an msr value (of 'msr_index') into 'pdata'.
2355 * Returns 0 on success, non-0 otherwise.
2356 * Assumes vcpu_load() was already called.
2357 */
609e36d3 2358int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2359{
609e36d3 2360 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2361}
ff651cb6 2362EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2363
890ca9ae 2364static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2365{
2366 u64 data;
890ca9ae
HY		 2367 u64 mcg_cap = vcpu->arch.mcg_cap;
2368 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2369
2370 switch (msr) {
15c4a640
CO		 2371 case MSR_IA32_P5_MC_ADDR:
2372 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2373 data = 0;
2374 break;
15c4a640 2375 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2376 data = vcpu->arch.mcg_cap;
2377 break;
c7ac679c 2378 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2379 if (!(mcg_cap & MCG_CTL_P))
2380 return 1;
2381 data = vcpu->arch.mcg_ctl;
2382 break;
2383 case MSR_IA32_MCG_STATUS:
2384 data = vcpu->arch.mcg_status;
2385 break;
2386 default:
2387 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2388 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2389 u32 offset = msr - MSR_IA32_MC0_CTL;
2390 data = vcpu->arch.mce_banks[offset];
2391 break;
2392 }
2393 return 1;
2394 }
2395 *pdata = data;
2396 return 0;
2397}
2398
609e36d3 2399int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2400{
609e36d3 2401 switch (msr_info->index) {
890ca9ae 2402 case MSR_IA32_PLATFORM_ID:
15c4a640 2403 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2404 case MSR_IA32_DEBUGCTLMSR:
2405 case MSR_IA32_LASTBRANCHFROMIP:
2406 case MSR_IA32_LASTBRANCHTOIP:
2407 case MSR_IA32_LASTINTFROMIP:
2408 case MSR_IA32_LASTINTTOIP:
60af2ecd 2409 case MSR_K8_SYSCFG:
3afb1121
PB		 2410 case MSR_K8_TSEG_ADDR:
2411 case MSR_K8_TSEG_MASK:
60af2ecd 2412 case MSR_K7_HWCR:
61a6bd67 2413 case MSR_VM_HSAVE_PA:
1fdbd48c 2414 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2415 case MSR_AMD64_NB_CFG:
f7c6d140 2416 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2417 case MSR_AMD64_BU_CFG2:
0c2df2a1 2418 case MSR_IA32_PERF_CTL:
609e36d3 2419 msr_info->data = 0;
15c4a640 2420 break;
6912ac32
WH		 2421 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2422 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2423 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2424 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2425 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2426 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2427 msr_info->data = 0;
5753785f 2428 break;
742bc670 2429 case MSR_IA32_UCODE_REV:
609e36d3 2430 msr_info->data = 0x100000000ULL;
742bc670 2431 break;
9ba075a6 2432 case MSR_MTRRcap:
9ba075a6 2433 case 0x200 ... 0x2ff:
ff53604b 2434 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2435 case 0xcd: /* fsb frequency */
609e36d3 2436 msr_info->data = 3;
15c4a640 2437 break;
7b914098
JS		 2438 /*
2439 * MSR_EBC_FREQUENCY_ID
2440 * Conservative value valid for even the basic CPU models.
2441 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2442 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2443 * and 266MHz for model 3, or 4. Set Core Clock
2444 * Frequency to System Bus Frequency Ratio to 1 (bits
2445 * 31:24) even though these are only valid for CPU
2446 * models > 2, however guests may end up dividing or
2447 * multiplying by zero otherwise.
2448 */
2449 case MSR_EBC_FREQUENCY_ID:
609e36d3 2450 msr_info->data = 1 << 24;
7b914098 2451 break;
15c4a640 2452 case MSR_IA32_APICBASE:
609e36d3 2453 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2454 break;
0105d1a5 2455 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2456 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2457 break;
a3e06bbe 2458 case MSR_IA32_TSCDEADLINE:
609e36d3 2459 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2460 break;
ba904635 2461 case MSR_IA32_TSC_ADJUST:
609e36d3 2462 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2463 break;
15c4a640 2464 case MSR_IA32_MISC_ENABLE:
609e36d3 2465 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2466 break;
64d60670
PB		 2467 case MSR_IA32_SMBASE:
2468 if (!msr_info->host_initiated)
2469 return 1;
2470 msr_info->data = vcpu->arch.smbase;
15c4a640 2471 break;
847f0ad8
AG		 2472 case MSR_IA32_PERF_STATUS:
2473 /* TSC increment by tick */
609e36d3 2474 msr_info->data = 1000ULL;
847f0ad8 2475 /* CPU multiplier */
b0996ae4 2476 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2477 break;
15c4a640 2478 case MSR_EFER:
609e36d3 2479 msr_info->data = vcpu->arch.efer;
15c4a640 2480 break;
18068523 2481 case MSR_KVM_WALL_CLOCK:
11c6bffa 2482 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2483 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2484 break;
2485 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2486 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2487 msr_info->data = vcpu->arch.time;
18068523 2488 break;
344d9588 2489 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2490 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2491 break;
c9aaa895 2492 case MSR_KVM_STEAL_TIME:
609e36d3 2493 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2494 break;
1d92128f 2495 case MSR_KVM_PV_EOI_EN:
609e36d3 2496 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2497 break;
890ca9ae
HY		 2498 case MSR_IA32_P5_MC_ADDR:
2499 case MSR_IA32_P5_MC_TYPE:
2500 case MSR_IA32_MCG_CAP:
2501 case MSR_IA32_MCG_CTL:
2502 case MSR_IA32_MCG_STATUS:
81760dcc 2503 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2504 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2505 case MSR_K7_CLK_CTL:
2506 /*
2507 * Provide expected ramp-up count for K7. All other
2508 * are set to zero, indicating minimum divisors for
2509 * every field.
2510 *
2511 * This prevents guest kernels on AMD host with CPU
2512 * type 6, model 8 and higher from exploding due to
2513 * the rdmsr failing.
2514 */
609e36d3 2515 msr_info->data = 0x20000000;
84e0cefa 2516 break;
55cd8e5a 2517 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2518 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2519 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2520 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2521 return kvm_hv_get_msr_common(vcpu,
2522 msr_info->index, &msr_info->data);
55cd8e5a 2523 break;
91c9c3ed 2524 case MSR_IA32_BBL_CR_CTL3:
2525 /* This legacy MSR exists but isn't fully documented in current
2526 * silicon. It is however accessed by winxp in very narrow
2527 * scenarios where it sets bit #19, itself documented as
2528 * a "reserved" bit. Best effort attempt to source coherent
2529 * read data here should the balance of the register be
2530 * interpreted by the guest:
2531 *
2532 * L2 cache control register 3: 64GB range, 256KB size,
2533 * enabled, latency 0x1, configured
2534 */
609e36d3 2535 msr_info->data = 0xbe702111;
91c9c3ed 2536 break;
2b036c6b
BO		 2537 case MSR_AMD64_OSVW_ID_LENGTH:
2538 if (!guest_cpuid_has_osvw(vcpu))
2539 return 1;
609e36d3 2540 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2541 break;
2542 case MSR_AMD64_OSVW_STATUS:
2543 if (!guest_cpuid_has_osvw(vcpu))
2544 return 1;
609e36d3 2545 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2546 break;
15c4a640 2547 default:
c6702c9d 2548 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2549 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2550 if (!ignore_msrs) {
ae0f5499
BD		 2551 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2552 msr_info->index);
ed85c068
AP		 2553 return 1;
2554 } else {
609e36d3
PB		 2555 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2556 msr_info->data = 0;
ed85c068
AP		 2557 }
2558 break;
15c4a640 2559 }
15c4a640
CO		 2560 return 0;
2561}
2562EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2563
313a3dc7
CO		 2564/*
2565 * Read or write a bunch of msrs. All parameters are kernel addresses.
2566 *
2567 * @return number of msrs set successfully.
2568 */
2569static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2570 struct kvm_msr_entry *entries,
2571 int (*do_msr)(struct kvm_vcpu *vcpu,
2572 unsigned index, u64 *data))
2573{
f656ce01 2574 int i, idx;
313a3dc7 2575
f656ce01 2576 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2577 for (i = 0; i < msrs->nmsrs; ++i)
2578 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2579 break;
f656ce01 2580 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2581
313a3dc7
CO		 2582 return i;
2583}
2584
2585/*
2586 * Read or write a bunch of msrs. Parameters are user addresses.
2587 *
2588 * @return number of msrs set successfully.
2589 */
2590static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2591 int (*do_msr)(struct kvm_vcpu *vcpu,
2592 unsigned index, u64 *data),
2593 int writeback)
2594{
2595 struct kvm_msrs msrs;
2596 struct kvm_msr_entry *entries;
2597 int r, n;
2598 unsigned size;
2599
2600 r = -EFAULT;
2601 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2602 goto out;
2603
2604 r = -E2BIG;
2605 if (msrs.nmsrs >= MAX_IO_MSRS)
2606 goto out;
2607
313a3dc7 2608 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2609 entries = memdup_user(user_msrs->entries, size);
2610 if (IS_ERR(entries)) {
2611 r = PTR_ERR(entries);
313a3dc7 2612 goto out;
ff5c2c03 2613 }
313a3dc7
CO		 2614
2615 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2616 if (r < 0)
2617 goto out_free;
2618
2619 r = -EFAULT;
2620 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2621 goto out_free;
2622
2623 r = n;
2624
2625out_free:
7a73c028 2626 kfree(entries);
313a3dc7
CO		 2627out:
2628 return r;
2629}
2630
784aa3d7 2631int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2632{
2633 int r;
2634
2635 switch (ext) {
2636 case KVM_CAP_IRQCHIP:
2637 case KVM_CAP_HLT:
2638 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2639 case KVM_CAP_SET_TSS_ADDR:
07716717 2640 case KVM_CAP_EXT_CPUID:
9c15bb1d 2641 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2642 case KVM_CAP_CLOCKSOURCE:
7837699f 2643 case KVM_CAP_PIT:
a28e4f5a 2644 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2645 case KVM_CAP_MP_STATE:
ed848624 2646 case KVM_CAP_SYNC_MMU:
a355c85c 2647 case KVM_CAP_USER_NMI:
52d939a0 2648 case KVM_CAP_REINJECT_CONTROL:
4925663a 2649 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2650 case KVM_CAP_IOEVENTFD:
f848a5a8 2651 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2652 case KVM_CAP_PIT2:
e9f42757 2653 case KVM_CAP_PIT_STATE2:
b927a3ce 2654 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2655 case KVM_CAP_XEN_HVM:
3cfc3092 2656 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2657 case KVM_CAP_HYPERV:
10388a07 2658 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2659 case KVM_CAP_HYPERV_SPIN:
5c919412 2660 case KVM_CAP_HYPERV_SYNIC:
ab9f4ecb 2661 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2662 case KVM_CAP_DEBUGREGS:
d2be1651 2663 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2664 case KVM_CAP_XSAVE:
344d9588 2665 case KVM_CAP_ASYNC_PF:
92a1f12d 2666 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2667 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2668 case KVM_CAP_READONLY_MEM:
5f66b620 2669 case KVM_CAP_HYPERV_TIME:
100943c5 2670 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2671 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2672 case KVM_CAP_ENABLE_CAP_VM:
2673 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2674 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2675 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2676 case KVM_CAP_IMMEDIATE_EXIT:
018d00d2
ZX		 2677 r = 1;
2678 break;
e3fd9a93
PB		 2679 case KVM_CAP_ADJUST_CLOCK:
2680 r = KVM_CLOCK_TSC_STABLE;
2681 break;
6d396b55
PB		 2682 case KVM_CAP_X86_SMM:
2683 /* SMBASE is usually relocated above 1M on modern chipsets,
2684 * and SMM handlers might indeed rely on 4G segment limits,
2685 * so do not report SMM to be available if real mode is
2686 * emulated via vm86 mode. Still, do not go to great lengths
2687 * to avoid userspace's usage of the feature, because it is a
2688 * fringe case that is not enabled except via specific settings
2689 * of the module parameters.
2690 */
2691 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2692 break;
774ead3a
AK		 2693 case KVM_CAP_VAPIC:
2694 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2695 break;
f725230a 2696 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2697 r = KVM_SOFT_MAX_VCPUS;
2698 break;
2699 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2700 r = KVM_MAX_VCPUS;
2701 break;
a988b910 2702 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2703 r = KVM_USER_MEM_SLOTS;
a988b910 2704 break;
a68a6a72
MT		 2705 case KVM_CAP_PV_MMU: /* obsolete */
2706 r = 0;
2f333bcb 2707 break;
890ca9ae
HY		 2708 case KVM_CAP_MCE:
2709 r = KVM_MAX_MCE_BANKS;
2710 break;
2d5b5a66 2711 case KVM_CAP_XCRS:
d366bf7e 2712 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2713 break;
92a1f12d
JR		 2714 case KVM_CAP_TSC_CONTROL:
2715 r = kvm_has_tsc_control;
2716 break;
37131313
RK		 2717 case KVM_CAP_X2APIC_API:
2718 r = KVM_X2APIC_API_VALID_FLAGS;
2719 break;
018d00d2
ZX		 2720 default:
2721 r = 0;
2722 break;
2723 }
2724 return r;
2725
2726}
2727
043405e1
CO		 2728long kvm_arch_dev_ioctl(struct file *filp,
2729 unsigned int ioctl, unsigned long arg)
2730{
2731 void __user *argp = (void __user *)arg;
2732 long r;
2733
2734 switch (ioctl) {
2735 case KVM_GET_MSR_INDEX_LIST: {
2736 struct kvm_msr_list __user *user_msr_list = argp;
2737 struct kvm_msr_list msr_list;
2738 unsigned n;
2739
2740 r = -EFAULT;
2741 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2742 goto out;
2743 n = msr_list.nmsrs;
62ef68bb 2744 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2745 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2746 goto out;
2747 r = -E2BIG;
e125e7b6 2748 if (n < msr_list.nmsrs)
043405e1
CO		 2749 goto out;
2750 r = -EFAULT;
2751 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2752 num_msrs_to_save * sizeof(u32)))
2753 goto out;
e125e7b6 2754 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2755 &emulated_msrs,
62ef68bb 2756 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2757 goto out;
2758 r = 0;
2759 break;
2760 }
9c15bb1d
BP		 2761 case KVM_GET_SUPPORTED_CPUID:
2762 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2763 struct kvm_cpuid2 __user *cpuid_arg = argp;
2764 struct kvm_cpuid2 cpuid;
2765
2766 r = -EFAULT;
2767 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2768 goto out;
9c15bb1d
BP		 2769
2770 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2771 ioctl);
674eea0f
AK		 2772 if (r)
2773 goto out;
2774
2775 r = -EFAULT;
2776 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2777 goto out;
2778 r = 0;
2779 break;
2780 }
890ca9ae 2781 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2782 r = -EFAULT;
c45dcc71
AR		 2783 if (copy_to_user(argp, &kvm_mce_cap_supported,
2784 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2785 goto out;
2786 r = 0;
2787 break;
2788 }
043405e1
CO		 2789 default:
2790 r = -EINVAL;
2791 }
2792out:
2793 return r;
2794}
2795
f5f48ee1
SY		 2796static void wbinvd_ipi(void *garbage)
2797{
2798 wbinvd();
2799}
2800
2801static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2802{
e0f0bbc5 2803 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2804}
2805
2860c4b1
PB		 2806static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2807{
2808 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2809}
2810
313a3dc7
CO		 2811void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2812{
f5f48ee1
SY		 2813 /* Address WBINVD may be executed by guest */
2814 if (need_emulate_wbinvd(vcpu)) {
2815 if (kvm_x86_ops->has_wbinvd_exit())
2816 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2817 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2818 smp_call_function_single(vcpu->cpu,
2819 wbinvd_ipi, NULL, 1);
2820 }
2821
313a3dc7 2822 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2823
0dd6a6ed
ZA		 2824 /* Apply any externally detected TSC adjustments (due to suspend) */
2825 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2826 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2827 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2828 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2829 }
8f6055cb 2830
48434c20 2831 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2832 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2833 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2834 if (tsc_delta < 0)
2835 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2836
c285545f 2837 if (check_tsc_unstable()) {
07c1419a 2838 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2839 vcpu->arch.last_guest_tsc);
a545ab6a 2840 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2841 vcpu->arch.tsc_catchup = 1;
c285545f 2842 }
e12c8f36
WL		 2843 if (kvm_lapic_hv_timer_in_use(vcpu) &&
2844 kvm_x86_ops->set_hv_timer(vcpu,
498f8162 2845 kvm_get_lapic_target_expiration_tsc(vcpu)))
e12c8f36 2846 kvm_lapic_switch_to_sw_timer(vcpu);
d98d07ca
MT		 2847 /*
2848 * On a host with synchronized TSC, there is no need to update
2849 * kvmclock on vcpu->cpu migration
2850 */
2851 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2852 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2853 if (vcpu->cpu != cpu)
2854 kvm_migrate_timers(vcpu);
e48672fa 2855 vcpu->cpu = cpu;
6b7d7e76 2856 }
c9aaa895 2857
c9aaa895 2858 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2859}
2860
0b9f6c46
PX		 2861static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2862{
2863 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2864 return;
2865
2866 vcpu->arch.st.steal.preempted = 1;
2867
bbd64115 2868 kvm_vcpu_write_guest_offset_cached(vcpu, &vcpu->arch.st.stime,
0b9f6c46
PX		 2869 &vcpu->arch.st.steal.preempted,
2870 offsetof(struct kvm_steal_time, preempted),
2871 sizeof(vcpu->arch.st.steal.preempted));
2872}
2873
313a3dc7
CO		 2874void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2875{
cc0d907c 2876 int idx;
931f261b
AA		 2877 /*
2878 * Disable page faults because we're in atomic context here.
2879 * kvm_write_guest_offset_cached() would call might_fault()
2880 * that relies on pagefault_disable() to tell if there's a
2881 * bug. NOTE: the write to guest memory may not go through if
2882 * during postcopy live migration or if there's heavy guest
2883 * paging.
2884 */
2885 pagefault_disable();
cc0d907c
AA		 2886 /*
2887 * kvm_memslots() will be called by
2888 * kvm_write_guest_offset_cached() so take the srcu lock.
2889 */
2890 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 2891 kvm_steal_time_set_preempted(vcpu);
cc0d907c 2892 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 2893 pagefault_enable();
02daab21 2894 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2895 kvm_put_guest_fpu(vcpu);
4ea1636b 2896 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2897}
2898
313a3dc7
CO		 2899static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2900 struct kvm_lapic_state *s)
2901{
76dfafd5 2902 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb
AS		 2903 kvm_x86_ops->sync_pir_to_irr(vcpu);
2904
a92e2543 2905 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 2906}
2907
2908static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2909 struct kvm_lapic_state *s)
2910{
a92e2543
RK		 2911 int r;
2912
2913 r = kvm_apic_set_state(vcpu, s);
2914 if (r)
2915 return r;
cb142eb7 2916 update_cr8_intercept(vcpu);
313a3dc7
CO		 2917
2918 return 0;
2919}
2920
127a457a
MG		 2921static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2922{
2923 return (!lapic_in_kernel(vcpu) ||
2924 kvm_apic_accept_pic_intr(vcpu));
2925}
2926
782d422b
MG		 2927/*
2928 * if userspace requested an interrupt window, check that the
2929 * interrupt window is open.
2930 *
2931 * No need to exit to userspace if we already have an interrupt queued.
2932 */
2933static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2934{
2935 return kvm_arch_interrupt_allowed(vcpu) &&
2936 !kvm_cpu_has_interrupt(vcpu) &&
2937 !kvm_event_needs_reinjection(vcpu) &&
2938 kvm_cpu_accept_dm_intr(vcpu);
2939}
2940
f77bc6a4
ZX		 2941static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2942 struct kvm_interrupt *irq)
2943{
02cdb50f 2944 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2945 return -EINVAL;
1c1a9ce9
SR		 2946
2947 if (!irqchip_in_kernel(vcpu->kvm)) {
2948 kvm_queue_interrupt(vcpu, irq->irq, false);
2949 kvm_make_request(KVM_REQ_EVENT, vcpu);
2950 return 0;
2951 }
2952
2953 /*
2954 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2955 * fail for in-kernel 8259.
2956 */
2957 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2958 return -ENXIO;
f77bc6a4 2959
1c1a9ce9
SR		 2960 if (vcpu->arch.pending_external_vector != -1)
2961 return -EEXIST;
f77bc6a4 2962
1c1a9ce9 2963 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2964 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2965 return 0;
2966}
2967
c4abb7c9
JK		 2968static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2969{
c4abb7c9 2970 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2971
2972 return 0;
2973}
2974
f077825a
PB		 2975static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2976{
64d60670
PB		 2977 kvm_make_request(KVM_REQ_SMI, vcpu);
2978
f077825a
PB		 2979 return 0;
2980}
2981
b209749f
AK		 2982static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2983 struct kvm_tpr_access_ctl *tac)
2984{
2985 if (tac->flags)
2986 return -EINVAL;
2987 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2988 return 0;
2989}
2990
890ca9ae
HY		 2991static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2992 u64 mcg_cap)
2993{
2994 int r;
2995 unsigned bank_num = mcg_cap & 0xff, bank;
2996
2997 r = -EINVAL;
a9e38c3e 2998 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 2999 goto out;
c45dcc71 3000 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3001 goto out;
3002 r = 0;
3003 vcpu->arch.mcg_cap = mcg_cap;
3004 /* Init IA32_MCG_CTL to all 1s */
3005 if (mcg_cap & MCG_CTL_P)
3006 vcpu->arch.mcg_ctl = ~(u64)0;
3007 /* Init IA32_MCi_CTL to all 1s */
3008 for (bank = 0; bank < bank_num; bank++)
3009 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3010
3011 if (kvm_x86_ops->setup_mce)
3012 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3013out:
3014 return r;
3015}
3016
3017static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3018 struct kvm_x86_mce *mce)
3019{
3020 u64 mcg_cap = vcpu->arch.mcg_cap;
3021 unsigned bank_num = mcg_cap & 0xff;
3022 u64 *banks = vcpu->arch.mce_banks;
3023
3024 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3025 return -EINVAL;
3026 /*
3027 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3028 * reporting is disabled
3029 */
3030 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3031 vcpu->arch.mcg_ctl != ~(u64)0)
3032 return 0;
3033 banks += 4 * mce->bank;
3034 /*
3035 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3036 * reporting is disabled for the bank
3037 */
3038 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3039 return 0;
3040 if (mce->status & MCI_STATUS_UC) {
3041 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3042 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3043 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3044 return 0;
3045 }
3046 if (banks[1] & MCI_STATUS_VAL)
3047 mce->status |= MCI_STATUS_OVER;
3048 banks[2] = mce->addr;
3049 banks[3] = mce->misc;
3050 vcpu->arch.mcg_status = mce->mcg_status;
3051 banks[1] = mce->status;
3052 kvm_queue_exception(vcpu, MC_VECTOR);
3053 } else if (!(banks[1] & MCI_STATUS_VAL)
3054 || !(banks[1] & MCI_STATUS_UC)) {
3055 if (banks[1] & MCI_STATUS_VAL)
3056 mce->status |= MCI_STATUS_OVER;
3057 banks[2] = mce->addr;
3058 banks[3] = mce->misc;
3059 banks[1] = mce->status;
3060 } else
3061 banks[1] |= MCI_STATUS_OVER;
3062 return 0;
3063}
3064
3cfc3092
JK		 3065static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3066 struct kvm_vcpu_events *events)
3067{
7460fb4a 3068 process_nmi(vcpu);
03b82a30
JK		 3069 events->exception.injected =
3070 vcpu->arch.exception.pending &&
3071 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3072 events->exception.nr = vcpu->arch.exception.nr;
3073 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3074 events->exception.pad = 0;
3cfc3092
JK		 3075 events->exception.error_code = vcpu->arch.exception.error_code;
3076
03b82a30
JK		 3077 events->interrupt.injected =
3078 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3079 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3080 events->interrupt.soft = 0;
37ccdcbe 3081 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3082
3083 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3084 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3085 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3086 events->nmi.pad = 0;
3cfc3092 3087
66450a21 3088 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3089
f077825a
PB		 3090 events->smi.smm = is_smm(vcpu);
3091 events->smi.pending = vcpu->arch.smi_pending;
3092 events->smi.smm_inside_nmi =
3093 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3094 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3095
dab4b911 3096 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3097 | KVM_VCPUEVENT_VALID_SHADOW
3098 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3099 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3100}
3101
6ef4e07e
XG		 3102static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3103
3cfc3092
JK		 3104static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3105 struct kvm_vcpu_events *events)
3106{
dab4b911 3107 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3108 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3109 | KVM_VCPUEVENT_VALID_SHADOW
3110 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3111 return -EINVAL;
3112
78e546c8 3113 if (events->exception.injected &&
28d06353
JM		 3114 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3115 is_guest_mode(vcpu)))
78e546c8
PB		 3116 return -EINVAL;
3117
28bf2888
DH		 3118 /* INITs are latched while in SMM */
3119 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3120 (events->smi.smm || events->smi.pending) &&
3121 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3122 return -EINVAL;
3123
7460fb4a 3124 process_nmi(vcpu);
3cfc3092
JK		 3125 vcpu->arch.exception.pending = events->exception.injected;
3126 vcpu->arch.exception.nr = events->exception.nr;
3127 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3128 vcpu->arch.exception.error_code = events->exception.error_code;
3129
3130 vcpu->arch.interrupt.pending = events->interrupt.injected;
3131 vcpu->arch.interrupt.nr = events->interrupt.nr;
3132 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3133 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3134 kvm_x86_ops->set_interrupt_shadow(vcpu,
3135 events->interrupt.shadow);
3cfc3092
JK		 3136
3137 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3138 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3139 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3140 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3141
66450a21 3142 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3143 lapic_in_kernel(vcpu))
66450a21 3144 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3145
f077825a 3146 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3147 u32 hflags = vcpu->arch.hflags;
f077825a 3148 if (events->smi.smm)
6ef4e07e 3149 hflags |= HF_SMM_MASK;
f077825a 3150 else
6ef4e07e
XG		 3151 hflags &= ~HF_SMM_MASK;
3152 kvm_set_hflags(vcpu, hflags);
3153
f077825a
PB		 3154 vcpu->arch.smi_pending = events->smi.pending;
3155 if (events->smi.smm_inside_nmi)
3156 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3157 else
3158 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
bce87cce 3159 if (lapic_in_kernel(vcpu)) {
f077825a
PB		 3160 if (events->smi.latched_init)
3161 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3162 else
3163 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3164 }
3165 }
3166
3842d135
AK		 3167 kvm_make_request(KVM_REQ_EVENT, vcpu);
3168
3cfc3092
JK		 3169 return 0;
3170}
3171
a1efbe77
JK		 3172static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3173 struct kvm_debugregs *dbgregs)
3174{
73aaf249
JK		 3175 unsigned long val;
3176
a1efbe77 3177 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3178 kvm_get_dr(vcpu, 6, &val);
73aaf249 3179 dbgregs->dr6 = val;
a1efbe77
JK		 3180 dbgregs->dr7 = vcpu->arch.dr7;
3181 dbgregs->flags = 0;
97e69aa6 3182 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3183}
3184
3185static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3186 struct kvm_debugregs *dbgregs)
3187{
3188 if (dbgregs->flags)
3189 return -EINVAL;
3190
d14bdb55
PB		 3191 if (dbgregs->dr6 & ~0xffffffffull)
3192 return -EINVAL;
3193 if (dbgregs->dr7 & ~0xffffffffull)
3194 return -EINVAL;
3195
a1efbe77 3196 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3197 kvm_update_dr0123(vcpu);
a1efbe77 3198 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3199 kvm_update_dr6(vcpu);
a1efbe77 3200 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3201 kvm_update_dr7(vcpu);
a1efbe77 3202
a1efbe77
JK		 3203 return 0;
3204}
3205
df1daba7
PB		 3206#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3207
3208static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3209{
c47ada30 3210 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3211 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3212 u64 valid;
3213
3214 /*
3215 * Copy legacy XSAVE area, to avoid complications with CPUID
3216 * leaves 0 and 1 in the loop below.
3217 */
3218 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3219
3220 /* Set XSTATE_BV */
00c87e9a 3221 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3222 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3223
3224 /*
3225 * Copy each region from the possibly compacted offset to the
3226 * non-compacted offset.
3227 */
d91cab78 3228 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3229 while (valid) {
3230 u64 feature = valid & -valid;
3231 int index = fls64(feature) - 1;
3232 void *src = get_xsave_addr(xsave, feature);
3233
3234 if (src) {
3235 u32 size, offset, ecx, edx;
3236 cpuid_count(XSTATE_CPUID, index,
3237 &size, &offset, &ecx, &edx);
3238 memcpy(dest + offset, src, size);
3239 }
3240
3241 valid -= feature;
3242 }
3243}
3244
3245static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3246{
c47ada30 3247 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3248 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3249 u64 valid;
3250
3251 /*
3252 * Copy legacy XSAVE area, to avoid complications with CPUID
3253 * leaves 0 and 1 in the loop below.
3254 */
3255 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3256
3257 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3258 xsave->header.xfeatures = xstate_bv;
782511b0 3259 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3260 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3261
3262 /*
3263 * Copy each region from the non-compacted offset to the
3264 * possibly compacted offset.
3265 */
d91cab78 3266 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3267 while (valid) {
3268 u64 feature = valid & -valid;
3269 int index = fls64(feature) - 1;
3270 void *dest = get_xsave_addr(xsave, feature);
3271
3272 if (dest) {
3273 u32 size, offset, ecx, edx;
3274 cpuid_count(XSTATE_CPUID, index,
3275 &size, &offset, &ecx, &edx);
3276 memcpy(dest, src + offset, size);
ee4100da 3277 }
df1daba7
PB		 3278
3279 valid -= feature;
3280 }
3281}
3282
2d5b5a66
SY		 3283static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3284 struct kvm_xsave *guest_xsave)
3285{
d366bf7e 3286 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3287 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3288 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3289 } else {
2d5b5a66 3290 memcpy(guest_xsave->region,
7366ed77 3291 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3292 sizeof(struct fxregs_state));
2d5b5a66 3293 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3294 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3295 }
3296}
3297
3298static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3299 struct kvm_xsave *guest_xsave)
3300{
3301 u64 xstate_bv =
3302 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3303
d366bf7e 3304 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3305 /*
3306 * Here we allow setting states that are not present in
3307 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3308 * with old userspace.
3309 */
4ff41732 3310 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3311 return -EINVAL;
df1daba7 3312 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3313 } else {
d91cab78 3314 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
2d5b5a66 3315 return -EINVAL;
7366ed77 3316 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3317 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3318 }
3319 return 0;
3320}
3321
3322static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3323 struct kvm_xcrs *guest_xcrs)
3324{
d366bf7e 3325 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3326 guest_xcrs->nr_xcrs = 0;
3327 return;
3328 }
3329
3330 guest_xcrs->nr_xcrs = 1;
3331 guest_xcrs->flags = 0;
3332 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3333 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3334}
3335
3336static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3337 struct kvm_xcrs *guest_xcrs)
3338{
3339 int i, r = 0;
3340
d366bf7e 3341 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3342 return -EINVAL;
3343
3344 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3345 return -EINVAL;
3346
3347 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3348 /* Only support XCR0 currently */
c67a04cb 3349 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3350 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3351 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3352 break;
3353 }
3354 if (r)
3355 r = -EINVAL;
3356 return r;
3357}
3358
1c0b28c2
EM		 3359/*
3360 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3361 * stopped by the hypervisor. This function will be called from the host only.
3362 * EINVAL is returned when the host attempts to set the flag for a guest that
3363 * does not support pv clocks.
3364 */
3365static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3366{
0b79459b 3367 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3368 return -EINVAL;
51d59c6b 3369 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3370 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3371 return 0;
3372}
3373
5c919412
AS		 3374static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3375 struct kvm_enable_cap *cap)
3376{
3377 if (cap->flags)
3378 return -EINVAL;
3379
3380 switch (cap->cap) {
3381 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3382 if (!irqchip_in_kernel(vcpu->kvm))
3383 return -EINVAL;
5c919412
AS		 3384 return kvm_hv_activate_synic(vcpu);
3385 default:
3386 return -EINVAL;
3387 }
3388}
3389
313a3dc7
CO		 3390long kvm_arch_vcpu_ioctl(struct file *filp,
3391 unsigned int ioctl, unsigned long arg)
3392{
3393 struct kvm_vcpu *vcpu = filp->private_data;
3394 void __user *argp = (void __user *)arg;
3395 int r;
d1ac91d8
AK		 3396 union {
3397 struct kvm_lapic_state *lapic;
3398 struct kvm_xsave *xsave;
3399 struct kvm_xcrs *xcrs;
3400 void *buffer;
3401 } u;
3402
3403 u.buffer = NULL;
313a3dc7
CO		 3404 switch (ioctl) {
3405 case KVM_GET_LAPIC: {
2204ae3c 3406 r = -EINVAL;
bce87cce 3407 if (!lapic_in_kernel(vcpu))
2204ae3c 3408 goto out;
d1ac91d8 3409 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3410
b772ff36 3411 r = -ENOMEM;
d1ac91d8 3412 if (!u.lapic)
b772ff36 3413 goto out;
d1ac91d8 3414 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3415 if (r)
3416 goto out;
3417 r = -EFAULT;
d1ac91d8 3418 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3419 goto out;
3420 r = 0;
3421 break;
3422 }
3423 case KVM_SET_LAPIC: {
2204ae3c 3424 r = -EINVAL;
bce87cce 3425 if (!lapic_in_kernel(vcpu))
2204ae3c 3426 goto out;
ff5c2c03 3427 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3428 if (IS_ERR(u.lapic))
3429 return PTR_ERR(u.lapic);
ff5c2c03 3430
d1ac91d8 3431 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3432 break;
3433 }
f77bc6a4
ZX		 3434 case KVM_INTERRUPT: {
3435 struct kvm_interrupt irq;
3436
3437 r = -EFAULT;
3438 if (copy_from_user(&irq, argp, sizeof irq))
3439 goto out;
3440 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3441 break;
3442 }
c4abb7c9
JK		 3443 case KVM_NMI: {
3444 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3445 break;
3446 }
f077825a
PB		 3447 case KVM_SMI: {
3448 r = kvm_vcpu_ioctl_smi(vcpu);
3449 break;
3450 }
313a3dc7
CO		 3451 case KVM_SET_CPUID: {
3452 struct kvm_cpuid __user *cpuid_arg = argp;
3453 struct kvm_cpuid cpuid;
3454
3455 r = -EFAULT;
3456 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3457 goto out;
3458 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3459 break;
3460 }
07716717
DK		 3461 case KVM_SET_CPUID2: {
3462 struct kvm_cpuid2 __user *cpuid_arg = argp;
3463 struct kvm_cpuid2 cpuid;
3464
3465 r = -EFAULT;
3466 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3467 goto out;
3468 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3469 cpuid_arg->entries);
07716717
DK		 3470 break;
3471 }
3472 case KVM_GET_CPUID2: {
3473 struct kvm_cpuid2 __user *cpuid_arg = argp;
3474 struct kvm_cpuid2 cpuid;
3475
3476 r = -EFAULT;
3477 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3478 goto out;
3479 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3480 cpuid_arg->entries);
07716717
DK		 3481 if (r)
3482 goto out;
3483 r = -EFAULT;
3484 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3485 goto out;
3486 r = 0;
3487 break;
3488 }
313a3dc7 3489 case KVM_GET_MSRS:
609e36d3 3490 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3491 break;
3492 case KVM_SET_MSRS:
3493 r = msr_io(vcpu, argp, do_set_msr, 0);
3494 break;
b209749f
AK		 3495 case KVM_TPR_ACCESS_REPORTING: {
3496 struct kvm_tpr_access_ctl tac;
3497
3498 r = -EFAULT;
3499 if (copy_from_user(&tac, argp, sizeof tac))
3500 goto out;
3501 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3502 if (r)
3503 goto out;
3504 r = -EFAULT;
3505 if (copy_to_user(argp, &tac, sizeof tac))
3506 goto out;
3507 r = 0;
3508 break;
3509 };
b93463aa
AK		 3510 case KVM_SET_VAPIC_ADDR: {
3511 struct kvm_vapic_addr va;
7301d6ab 3512 int idx;
b93463aa
AK		 3513
3514 r = -EINVAL;
35754c98 3515 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3516 goto out;
3517 r = -EFAULT;
3518 if (copy_from_user(&va, argp, sizeof va))
3519 goto out;
7301d6ab 3520 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3521 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3522 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3523 break;
3524 }
890ca9ae
HY		 3525 case KVM_X86_SETUP_MCE: {
3526 u64 mcg_cap;
3527
3528 r = -EFAULT;
3529 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3530 goto out;
3531 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3532 break;
3533 }
3534 case KVM_X86_SET_MCE: {
3535 struct kvm_x86_mce mce;
3536
3537 r = -EFAULT;
3538 if (copy_from_user(&mce, argp, sizeof mce))
3539 goto out;
3540 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3541 break;
3542 }
3cfc3092
JK		 3543 case KVM_GET_VCPU_EVENTS: {
3544 struct kvm_vcpu_events events;
3545
3546 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3547
3548 r = -EFAULT;
3549 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3550 break;
3551 r = 0;
3552 break;
3553 }
3554 case KVM_SET_VCPU_EVENTS: {
3555 struct kvm_vcpu_events events;
3556
3557 r = -EFAULT;
3558 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3559 break;
3560
3561 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3562 break;
3563 }
a1efbe77
JK		 3564 case KVM_GET_DEBUGREGS: {
3565 struct kvm_debugregs dbgregs;
3566
3567 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3568
3569 r = -EFAULT;
3570 if (copy_to_user(argp, &dbgregs,
3571 sizeof(struct kvm_debugregs)))
3572 break;
3573 r = 0;
3574 break;
3575 }
3576 case KVM_SET_DEBUGREGS: {
3577 struct kvm_debugregs dbgregs;
3578
3579 r = -EFAULT;
3580 if (copy_from_user(&dbgregs, argp,
3581 sizeof(struct kvm_debugregs)))
3582 break;
3583
3584 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3585 break;
3586 }
2d5b5a66 3587 case KVM_GET_XSAVE: {
d1ac91d8 3588 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3589 r = -ENOMEM;
d1ac91d8 3590 if (!u.xsave)
2d5b5a66
SY		 3591 break;
3592
d1ac91d8 3593 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3594
3595 r = -EFAULT;
d1ac91d8 3596 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3597 break;
3598 r = 0;
3599 break;
3600 }
3601 case KVM_SET_XSAVE: {
ff5c2c03 3602 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3603 if (IS_ERR(u.xsave))
3604 return PTR_ERR(u.xsave);
2d5b5a66 3605
d1ac91d8 3606 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3607 break;
3608 }
3609 case KVM_GET_XCRS: {
d1ac91d8 3610 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3611 r = -ENOMEM;
d1ac91d8 3612 if (!u.xcrs)
2d5b5a66
SY		 3613 break;
3614
d1ac91d8 3615 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3616
3617 r = -EFAULT;
d1ac91d8 3618 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3619 sizeof(struct kvm_xcrs)))
3620 break;
3621 r = 0;
3622 break;
3623 }
3624 case KVM_SET_XCRS: {
ff5c2c03 3625 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3626 if (IS_ERR(u.xcrs))
3627 return PTR_ERR(u.xcrs);
2d5b5a66 3628
d1ac91d8 3629 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3630 break;
3631 }
92a1f12d
JR		 3632 case KVM_SET_TSC_KHZ: {
3633 u32 user_tsc_khz;
3634
3635 r = -EINVAL;
92a1f12d
JR		 3636 user_tsc_khz = (u32)arg;
3637
3638 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3639 goto out;
3640
cc578287
ZA		 3641 if (user_tsc_khz == 0)
3642 user_tsc_khz = tsc_khz;
3643
381d585c
HZ		 3644 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3645 r = 0;
92a1f12d 3646
92a1f12d
JR		 3647 goto out;
3648 }
3649 case KVM_GET_TSC_KHZ: {
cc578287 3650 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3651 goto out;
3652 }
1c0b28c2
EM		 3653 case KVM_KVMCLOCK_CTRL: {
3654 r = kvm_set_guest_paused(vcpu);
3655 goto out;
3656 }
5c919412
AS		 3657 case KVM_ENABLE_CAP: {
3658 struct kvm_enable_cap cap;
3659
3660 r = -EFAULT;
3661 if (copy_from_user(&cap, argp, sizeof(cap)))
3662 goto out;
3663 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3664 break;
3665 }
313a3dc7
CO		 3666 default:
3667 r = -EINVAL;
3668 }
3669out:
d1ac91d8 3670 kfree(u.buffer);
313a3dc7
CO		 3671 return r;
3672}
3673
5b1c1493
CO		 3674int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3675{
3676 return VM_FAULT_SIGBUS;
3677}
3678
1fe779f8
CO		 3679static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3680{
3681 int ret;
3682
3683 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3684 return -EINVAL;
1fe779f8
CO		 3685 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3686 return ret;
3687}
3688
b927a3ce
SY		 3689static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3690 u64 ident_addr)
3691{
3692 kvm->arch.ept_identity_map_addr = ident_addr;
3693 return 0;
3694}
3695
1fe779f8
CO		 3696static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3697 u32 kvm_nr_mmu_pages)
3698{
3699 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3700 return -EINVAL;
3701
79fac95e 3702 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3703
3704 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3705 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3706
79fac95e 3707 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3708 return 0;
3709}
3710
3711static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3712{
39de71ec 3713 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3714}
3715
1fe779f8
CO		 3716static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3717{
90bca052 3718 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3719 int r;
3720
3721 r = 0;
3722 switch (chip->chip_id) {
3723 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3724 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3725 sizeof(struct kvm_pic_state));
3726 break;
3727 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3728 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 3729 sizeof(struct kvm_pic_state));
3730 break;
3731 case KVM_IRQCHIP_IOAPIC:
33392b49 3732 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3733 break;
3734 default:
3735 r = -EINVAL;
3736 break;
3737 }
3738 return r;
3739}
3740
3741static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3742{
90bca052 3743 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3744 int r;
3745
3746 r = 0;
3747 switch (chip->chip_id) {
3748 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 3749 spin_lock(&pic->lock);
3750 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 3751 sizeof(struct kvm_pic_state));
90bca052 3752 spin_unlock(&pic->lock);
1fe779f8
CO		 3753 break;
3754 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 3755 spin_lock(&pic->lock);
3756 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 3757 sizeof(struct kvm_pic_state));
90bca052 3758 spin_unlock(&pic->lock);
1fe779f8
CO		 3759 break;
3760 case KVM_IRQCHIP_IOAPIC:
33392b49 3761 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3762 break;
3763 default:
3764 r = -EINVAL;
3765 break;
3766 }
90bca052 3767 kvm_pic_update_irq(pic);
1fe779f8
CO		 3768 return r;
3769}
3770
e0f63cb9
SY		 3771static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3772{
34f3941c
RK		 3773 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3774
3775 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3776
3777 mutex_lock(&kps->lock);
3778 memcpy(ps, &kps->channels, sizeof(*ps));
3779 mutex_unlock(&kps->lock);
2da29bcc 3780 return 0;
e0f63cb9
SY		 3781}
3782
3783static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3784{
0185604c 3785 int i;
09edea72
RK		 3786 struct kvm_pit *pit = kvm->arch.vpit;
3787
3788 mutex_lock(&pit->pit_state.lock);
34f3941c 3789 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3790 for (i = 0; i < 3; i++)
09edea72
RK		 3791 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3792 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3793 return 0;
e9f42757
BK		 3794}
3795
3796static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3797{
e9f42757
BK		 3798 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3799 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3800 sizeof(ps->channels));
3801 ps->flags = kvm->arch.vpit->pit_state.flags;
3802 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3803 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3804 return 0;
e9f42757
BK		 3805}
3806
3807static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3808{
2da29bcc 3809 int start = 0;
0185604c 3810 int i;
e9f42757 3811 u32 prev_legacy, cur_legacy;
09edea72
RK		 3812 struct kvm_pit *pit = kvm->arch.vpit;
3813
3814 mutex_lock(&pit->pit_state.lock);
3815 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3816 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3817 if (!prev_legacy && cur_legacy)
3818 start = 1;
09edea72
RK		 3819 memcpy(&pit->pit_state.channels, &ps->channels,
3820 sizeof(pit->pit_state.channels));
3821 pit->pit_state.flags = ps->flags;
0185604c 3822 for (i = 0; i < 3; i++)
09edea72 3823 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3824 start && i == 0);
09edea72 3825 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3826 return 0;
e0f63cb9
SY		 3827}
3828
52d939a0
MT		 3829static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3830 struct kvm_reinject_control *control)
3831{
71474e2f
RK		 3832 struct kvm_pit *pit = kvm->arch.vpit;
3833
3834 if (!pit)
52d939a0 3835 return -ENXIO;
b39c90b6 3836
71474e2f
RK		 3837 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3838 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3839 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3840 */
3841 mutex_lock(&pit->pit_state.lock);
3842 kvm_pit_set_reinject(pit, control->pit_reinject);
3843 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3844
52d939a0
MT		 3845 return 0;
3846}
3847
95d4c16c 3848/**
60c34612
TY		 3849 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3850 * @kvm: kvm instance
3851 * @log: slot id and address to which we copy the log
95d4c16c 3852 *
e108ff2f
PB		 3853 * Steps 1-4 below provide general overview of dirty page logging. See
3854 * kvm_get_dirty_log_protect() function description for additional details.
3855 *
3856 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3857 * always flush the TLB (step 4) even if previous step failed and the dirty
3858 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3859 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3860 * writes will be marked dirty for next log read.
95d4c16c 3861 *
60c34612
TY		 3862 * 1. Take a snapshot of the bit and clear it if needed.
3863 * 2. Write protect the corresponding page.
e108ff2f
PB		 3864 * 3. Copy the snapshot to the userspace.
3865 * 4. Flush TLB's if needed.
5bb064dc 3866 */
60c34612 3867int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3868{
60c34612 3869 bool is_dirty = false;
e108ff2f 3870 int r;
5bb064dc 3871
79fac95e 3872 mutex_lock(&kvm->slots_lock);
5bb064dc 3873
88178fd4
KH		 3874 /*
3875 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3876 */
3877 if (kvm_x86_ops->flush_log_dirty)
3878 kvm_x86_ops->flush_log_dirty(kvm);
3879
e108ff2f 3880 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3881
3882 /*
3883 * All the TLBs can be flushed out of mmu lock, see the comments in
3884 * kvm_mmu_slot_remove_write_access().
3885 */
e108ff2f 3886 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3887 if (is_dirty)
3888 kvm_flush_remote_tlbs(kvm);
3889
79fac95e 3890 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3891 return r;
3892}
3893
aa2fbe6d
YZ		 3894int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3895 bool line_status)
23d43cf9
CD		 3896{
3897 if (!irqchip_in_kernel(kvm))
3898 return -ENXIO;
3899
3900 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3901 irq_event->irq, irq_event->level,
3902 line_status);
23d43cf9
CD		 3903 return 0;
3904}
3905
90de4a18
NA		 3906static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3907 struct kvm_enable_cap *cap)
3908{
3909 int r;
3910
3911 if (cap->flags)
3912 return -EINVAL;
3913
3914 switch (cap->cap) {
3915 case KVM_CAP_DISABLE_QUIRKS:
3916 kvm->arch.disabled_quirks = cap->args[0];
3917 r = 0;
3918 break;
49df6397
SR		 3919 case KVM_CAP_SPLIT_IRQCHIP: {
3920 mutex_lock(&kvm->lock);
b053b2ae
SR		 3921 r = -EINVAL;
3922 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3923 goto split_irqchip_unlock;
49df6397
SR		 3924 r = -EEXIST;
3925 if (irqchip_in_kernel(kvm))
3926 goto split_irqchip_unlock;
557abc40 3927 if (kvm->created_vcpus)
49df6397 3928 goto split_irqchip_unlock;
637e3f86 3929 kvm->arch.irqchip_mode = KVM_IRQCHIP_INIT_IN_PROGRESS;
49df6397 3930 r = kvm_setup_empty_irq_routing(kvm);
637e3f86
DH		 3931 if (r) {
3932 kvm->arch.irqchip_mode = KVM_IRQCHIP_NONE;
3933 /* Pairs with smp_rmb() when reading irqchip_mode */
3934 smp_wmb();
49df6397 3935 goto split_irqchip_unlock;
637e3f86 3936 }
49df6397
SR		 3937 /* Pairs with irqchip_in_kernel. */
3938 smp_wmb();
49776faf 3939 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 3940 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3941 r = 0;
3942split_irqchip_unlock:
3943 mutex_unlock(&kvm->lock);
3944 break;
3945 }
37131313
RK		 3946 case KVM_CAP_X2APIC_API:
3947 r = -EINVAL;
3948 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
3949 break;
3950
3951 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
3952 kvm->arch.x2apic_format = true;
c519265f
RK		 3953 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
3954 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 3955
3956 r = 0;
3957 break;
90de4a18
NA		 3958 default:
3959 r = -EINVAL;
3960 break;
3961 }
3962 return r;
3963}
3964
1fe779f8
CO		 3965long kvm_arch_vm_ioctl(struct file *filp,
3966 unsigned int ioctl, unsigned long arg)
3967{
3968 struct kvm *kvm = filp->private_data;
3969 void __user *argp = (void __user *)arg;
367e1319 3970 int r = -ENOTTY;
f0d66275
DH		 3971 /*
3972 * This union makes it completely explicit to gcc-3.x
3973 * that these two variables' stack usage should be
3974 * combined, not added together.
3975 */
3976 union {
3977 struct kvm_pit_state ps;
e9f42757 3978 struct kvm_pit_state2 ps2;
c5ff41ce 3979 struct kvm_pit_config pit_config;
f0d66275 3980 } u;
1fe779f8
CO		 3981
3982 switch (ioctl) {
3983 case KVM_SET_TSS_ADDR:
3984 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3985 break;
b927a3ce
SY		 3986 case KVM_SET_IDENTITY_MAP_ADDR: {
3987 u64 ident_addr;
3988
3989 r = -EFAULT;
3990 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3991 goto out;
3992 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3993 break;
3994 }
1fe779f8
CO		 3995 case KVM_SET_NR_MMU_PAGES:
3996 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3997 break;
3998 case KVM_GET_NR_MMU_PAGES:
3999 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4000 break;
3ddea128 4001 case KVM_CREATE_IRQCHIP: {
3ddea128 4002 mutex_lock(&kvm->lock);
09941366 4003
3ddea128 4004 r = -EEXIST;
35e6eaa3 4005 if (irqchip_in_kernel(kvm))
3ddea128 4006 goto create_irqchip_unlock;
09941366 4007
3e515705 4008 r = -EINVAL;
557abc40 4009 if (kvm->created_vcpus)
3e515705 4010 goto create_irqchip_unlock;
09941366
RK		 4011
4012 r = kvm_pic_init(kvm);
4013 if (r)
3ddea128 4014 goto create_irqchip_unlock;
09941366
RK		 4015
4016 r = kvm_ioapic_init(kvm);
4017 if (r) {
09941366 4018 kvm_pic_destroy(kvm);
3ddea128 4019 goto create_irqchip_unlock;
09941366
RK		 4020 }
4021
637e3f86 4022 kvm->arch.irqchip_mode = KVM_IRQCHIP_INIT_IN_PROGRESS;
399ec807
AK		 4023 r = kvm_setup_default_irq_routing(kvm);
4024 if (r) {
637e3f86
DH		 4025 kvm->arch.irqchip_mode = KVM_IRQCHIP_NONE;
4026 /* Pairs with smp_rmb() when reading irqchip_mode */
4027 smp_wmb();
72bb2fcd 4028 kvm_ioapic_destroy(kvm);
09941366 4029 kvm_pic_destroy(kvm);
71ba994c 4030 goto create_irqchip_unlock;
399ec807 4031 }
49776faf 4032 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4033 smp_wmb();
49776faf 4034 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4035 create_irqchip_unlock:
4036 mutex_unlock(&kvm->lock);
1fe779f8 4037 break;
3ddea128 4038 }
7837699f 4039 case KVM_CREATE_PIT:
c5ff41ce
JK		 4040 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4041 goto create_pit;
4042 case KVM_CREATE_PIT2:
4043 r = -EFAULT;
4044 if (copy_from_user(&u.pit_config, argp,
4045 sizeof(struct kvm_pit_config)))
4046 goto out;
4047 create_pit:
250715a6 4048 mutex_lock(&kvm->lock);
269e05e4
AK		 4049 r = -EEXIST;
4050 if (kvm->arch.vpit)
4051 goto create_pit_unlock;
7837699f 4052 r = -ENOMEM;
c5ff41ce 4053 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4054 if (kvm->arch.vpit)
4055 r = 0;
269e05e4 4056 create_pit_unlock:
250715a6 4057 mutex_unlock(&kvm->lock);
7837699f 4058 break;
1fe779f8
CO		 4059 case KVM_GET_IRQCHIP: {
4060 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4061 struct kvm_irqchip *chip;
1fe779f8 4062
ff5c2c03
SL		 4063 chip = memdup_user(argp, sizeof(*chip));
4064 if (IS_ERR(chip)) {
4065 r = PTR_ERR(chip);
1fe779f8 4066 goto out;
ff5c2c03
SL		 4067 }
4068
1fe779f8 4069 r = -ENXIO;
826da321 4070 if (!irqchip_kernel(kvm))
f0d66275
DH		 4071 goto get_irqchip_out;
4072 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4073 if (r)
f0d66275 4074 goto get_irqchip_out;
1fe779f8 4075 r = -EFAULT;
f0d66275
DH		 4076 if (copy_to_user(argp, chip, sizeof *chip))
4077 goto get_irqchip_out;
1fe779f8 4078 r = 0;
f0d66275
DH		 4079 get_irqchip_out:
4080 kfree(chip);
1fe779f8
CO		 4081 break;
4082 }
4083 case KVM_SET_IRQCHIP: {
4084 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4085 struct kvm_irqchip *chip;
1fe779f8 4086
ff5c2c03
SL		 4087 chip = memdup_user(argp, sizeof(*chip));
4088 if (IS_ERR(chip)) {
4089 r = PTR_ERR(chip);
1fe779f8 4090 goto out;
ff5c2c03
SL		 4091 }
4092
1fe779f8 4093 r = -ENXIO;
826da321 4094 if (!irqchip_kernel(kvm))
f0d66275
DH		 4095 goto set_irqchip_out;
4096 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4097 if (r)
f0d66275 4098 goto set_irqchip_out;
1fe779f8 4099 r = 0;
f0d66275
DH		 4100 set_irqchip_out:
4101 kfree(chip);
1fe779f8
CO		 4102 break;
4103 }
e0f63cb9 4104 case KVM_GET_PIT: {
e0f63cb9 4105 r = -EFAULT;
f0d66275 4106 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4107 goto out;
4108 r = -ENXIO;
4109 if (!kvm->arch.vpit)
4110 goto out;
f0d66275 4111 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4112 if (r)
4113 goto out;
4114 r = -EFAULT;
f0d66275 4115 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4116 goto out;
4117 r = 0;
4118 break;
4119 }
4120 case KVM_SET_PIT: {
e0f63cb9 4121 r = -EFAULT;
f0d66275 4122 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4123 goto out;
4124 r = -ENXIO;
4125 if (!kvm->arch.vpit)
4126 goto out;
f0d66275 4127 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4128 break;
4129 }
e9f42757
BK		 4130 case KVM_GET_PIT2: {
4131 r = -ENXIO;
4132 if (!kvm->arch.vpit)
4133 goto out;
4134 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4135 if (r)
4136 goto out;
4137 r = -EFAULT;
4138 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4139 goto out;
4140 r = 0;
4141 break;
4142 }
4143 case KVM_SET_PIT2: {
4144 r = -EFAULT;
4145 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4146 goto out;
4147 r = -ENXIO;
4148 if (!kvm->arch.vpit)
4149 goto out;
4150 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4151 break;
4152 }
52d939a0
MT		 4153 case KVM_REINJECT_CONTROL: {
4154 struct kvm_reinject_control control;
4155 r = -EFAULT;
4156 if (copy_from_user(&control, argp, sizeof(control)))
4157 goto out;
4158 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4159 break;
4160 }
d71ba788
PB		 4161 case KVM_SET_BOOT_CPU_ID:
4162 r = 0;
4163 mutex_lock(&kvm->lock);
557abc40 4164 if (kvm->created_vcpus)
d71ba788
PB		 4165 r = -EBUSY;
4166 else
4167 kvm->arch.bsp_vcpu_id = arg;
4168 mutex_unlock(&kvm->lock);
4169 break;
ffde22ac
ES		 4170 case KVM_XEN_HVM_CONFIG: {
4171 r = -EFAULT;
4172 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4173 sizeof(struct kvm_xen_hvm_config)))
4174 goto out;
4175 r = -EINVAL;
4176 if (kvm->arch.xen_hvm_config.flags)
4177 goto out;
4178 r = 0;
4179 break;
4180 }
afbcf7ab 4181 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4182 struct kvm_clock_data user_ns;
4183 u64 now_ns;
afbcf7ab
GC		 4184
4185 r = -EFAULT;
4186 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4187 goto out;
4188
4189 r = -EINVAL;
4190 if (user_ns.flags)
4191 goto out;
4192
4193 r = 0;
395c6b0a 4194 local_irq_disable();
108b249c
PB		 4195 now_ns = __get_kvmclock_ns(kvm);
4196 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
395c6b0a 4197 local_irq_enable();
2e762ff7 4198 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4199 break;
4200 }
4201 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4202 struct kvm_clock_data user_ns;
4203 u64 now_ns;
4204
e3fd9a93
PB		 4205 local_irq_disable();
4206 now_ns = __get_kvmclock_ns(kvm);
108b249c 4207 user_ns.clock = now_ns;
e3fd9a93
PB		 4208 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
4209 local_irq_enable();
97e69aa6 4210 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4211
4212 r = -EFAULT;
4213 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4214 goto out;
4215 r = 0;
4216 break;
4217 }
90de4a18
NA		 4218 case KVM_ENABLE_CAP: {
4219 struct kvm_enable_cap cap;
afbcf7ab 4220
90de4a18
NA		 4221 r = -EFAULT;
4222 if (copy_from_user(&cap, argp, sizeof(cap)))
4223 goto out;
4224 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4225 break;
4226 }
1fe779f8 4227 default:
ad6260da 4228 r = -ENOTTY;
1fe779f8
CO		 4229 }
4230out:
4231 return r;
4232}
4233
a16b043c 4234static void kvm_init_msr_list(void)
043405e1
CO		 4235{
4236 u32 dummy[2];
4237 unsigned i, j;
4238
62ef68bb 4239 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4240 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4241 continue;
93c4adc7
PB		 4242
4243 /*
4244 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4245 * to the guests in some cases.
93c4adc7
PB		 4246 */
4247 switch (msrs_to_save[i]) {
4248 case MSR_IA32_BNDCFGS:
4249 if (!kvm_x86_ops->mpx_supported())
4250 continue;
4251 break;
9dbe6cf9
PB		 4252 case MSR_TSC_AUX:
4253 if (!kvm_x86_ops->rdtscp_supported())
4254 continue;
4255 break;
93c4adc7
PB		 4256 default:
4257 break;
4258 }
4259
043405e1
CO		 4260 if (j < i)
4261 msrs_to_save[j] = msrs_to_save[i];
4262 j++;
4263 }
4264 num_msrs_to_save = j;
62ef68bb
PB		 4265
4266 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4267 switch (emulated_msrs[i]) {
6d396b55
PB		 4268 case MSR_IA32_SMBASE:
4269 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4270 continue;
4271 break;
62ef68bb
PB		 4272 default:
4273 break;
4274 }
4275
4276 if (j < i)
4277 emulated_msrs[j] = emulated_msrs[i];
4278 j++;
4279 }
4280 num_emulated_msrs = j;
043405e1
CO		 4281}
4282
bda9020e
MT		 4283static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4284 const void *v)
bbd9b64e 4285{
70252a10
AK		 4286 int handled = 0;
4287 int n;
4288
4289 do {
4290 n = min(len, 8);
bce87cce 4291 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4292 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4293 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4294 break;
4295 handled += n;
4296 addr += n;
4297 len -= n;
4298 v += n;
4299 } while (len);
bbd9b64e 4300
70252a10 4301 return handled;
bbd9b64e
CO		 4302}
4303
bda9020e 4304static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4305{
70252a10
AK		 4306 int handled = 0;
4307 int n;
4308
4309 do {
4310 n = min(len, 8);
bce87cce 4311 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4312 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4313 addr, n, v))
4314 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4315 break;
4316 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4317 handled += n;
4318 addr += n;
4319 len -= n;
4320 v += n;
4321 } while (len);
bbd9b64e 4322
70252a10 4323 return handled;
bbd9b64e
CO		 4324}
4325
2dafc6c2
GN		 4326static void kvm_set_segment(struct kvm_vcpu *vcpu,
4327 struct kvm_segment *var, int seg)
4328{
4329 kvm_x86_ops->set_segment(vcpu, var, seg);
4330}
4331
4332void kvm_get_segment(struct kvm_vcpu *vcpu,
4333 struct kvm_segment *var, int seg)
4334{
4335 kvm_x86_ops->get_segment(vcpu, var, seg);
4336}
4337
54987b7a
PB		 4338gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4339 struct x86_exception *exception)
02f59dc9
JR		 4340{
4341 gpa_t t_gpa;
02f59dc9
JR		 4342
4343 BUG_ON(!mmu_is_nested(vcpu));
4344
4345 /* NPT walks are always user-walks */
4346 access |= PFERR_USER_MASK;
54987b7a 4347 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4348
4349 return t_gpa;
4350}
4351
ab9ae313
AK		 4352gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4353 struct x86_exception *exception)
1871c602
GN		 4354{
4355 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4356 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4357}
4358
ab9ae313
AK		 4359 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4360 struct x86_exception *exception)
1871c602
GN		 4361{
4362 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4363 access |= PFERR_FETCH_MASK;
ab9ae313 4364 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4365}
4366
ab9ae313
AK		 4367gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4368 struct x86_exception *exception)
1871c602
GN		 4369{
4370 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4371 access |= PFERR_WRITE_MASK;
ab9ae313 4372 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4373}
4374
4375/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4376gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4377 struct x86_exception *exception)
1871c602 4378{
ab9ae313 4379 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4380}
4381
4382static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4383 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4384 struct x86_exception *exception)
bbd9b64e
CO		 4385{
4386 void *data = val;
10589a46 4387 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4388
4389 while (bytes) {
14dfe855 4390 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4391 exception);
bbd9b64e 4392 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4393 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4394 int ret;
4395
bcc55cba 4396 if (gpa == UNMAPPED_GVA)
ab9ae313 4397 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4398 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4399 offset, toread);
10589a46 4400 if (ret < 0) {
c3cd7ffa 4401 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4402 goto out;
4403 }
bbd9b64e 4404
77c2002e
IE		 4405 bytes -= toread;
4406 data += toread;
4407 addr += toread;
bbd9b64e 4408 }
10589a46 4409out:
10589a46 4410 return r;
bbd9b64e 4411}
77c2002e 4412
1871c602 4413/* used for instruction fetching */
0f65dd70
AK		 4414static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4415 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4416 struct x86_exception *exception)
1871c602 4417{
0f65dd70 4418 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4419 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4420 unsigned offset;
4421 int ret;
0f65dd70 4422
44583cba
PB		 4423 /* Inline kvm_read_guest_virt_helper for speed. */
4424 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4425 exception);
4426 if (unlikely(gpa == UNMAPPED_GVA))
4427 return X86EMUL_PROPAGATE_FAULT;
4428
4429 offset = addr & (PAGE_SIZE-1);
4430 if (WARN_ON(offset + bytes > PAGE_SIZE))
4431 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4432 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4433 offset, bytes);
44583cba
PB		 4434 if (unlikely(ret < 0))
4435 return X86EMUL_IO_NEEDED;
4436
4437 return X86EMUL_CONTINUE;
1871c602
GN		 4438}
4439
064aea77 4440int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4441 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4442 struct x86_exception *exception)
1871c602 4443{
0f65dd70 4444 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4445 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4446
1871c602 4447 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4448 exception);
1871c602 4449}
064aea77 4450EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4451
0f65dd70
AK		 4452static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4453 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4454 struct x86_exception *exception)
1871c602 4455{
0f65dd70 4456 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4457 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4458}
4459
7a036a6f
RK		 4460static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4461 unsigned long addr, void *val, unsigned int bytes)
4462{
4463 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4464 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4465
4466 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4467}
4468
6a4d7550 4469int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4470 gva_t addr, void *val,
2dafc6c2 4471 unsigned int bytes,
bcc55cba 4472 struct x86_exception *exception)
77c2002e 4473{
0f65dd70 4474 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4475 void *data = val;
4476 int r = X86EMUL_CONTINUE;
4477
4478 while (bytes) {
14dfe855
JR		 4479 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4480 PFERR_WRITE_MASK,
ab9ae313 4481 exception);
77c2002e
IE		 4482 unsigned offset = addr & (PAGE_SIZE-1);
4483 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4484 int ret;
4485
bcc55cba 4486 if (gpa == UNMAPPED_GVA)
ab9ae313 4487 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4488 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4489 if (ret < 0) {
c3cd7ffa 4490 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4491 goto out;
4492 }
4493
4494 bytes -= towrite;
4495 data += towrite;
4496 addr += towrite;
4497 }
4498out:
4499 return r;
4500}
6a4d7550 4501EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4502
0f89b207
TL		 4503static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4504 gpa_t gpa, bool write)
4505{
4506 /* For APIC access vmexit */
4507 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4508 return 1;
4509
4510 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4511 trace_vcpu_match_mmio(gva, gpa, write, true);
4512 return 1;
4513 }
4514
4515 return 0;
4516}
4517
af7cc7d1
XG		 4518static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4519 gpa_t *gpa, struct x86_exception *exception,
4520 bool write)
4521{
97d64b78
AK		 4522 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4523 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4524
be94f6b7
HH		 4525 /*
4526 * currently PKRU is only applied to ept enabled guest so
4527 * there is no pkey in EPT page table for L1 guest or EPT
4528 * shadow page table for L2 guest.
4529 */
97d64b78 4530 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4531 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4532 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4533 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4534 (gva & (PAGE_SIZE - 1));
4f022648 4535 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4536 return 1;
4537 }
4538
af7cc7d1
XG		 4539 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4540
4541 if (*gpa == UNMAPPED_GVA)
4542 return -1;
4543
0f89b207 4544 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4545}
4546
3200f405 4547int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4548 const void *val, int bytes)
bbd9b64e
CO		 4549{
4550 int ret;
4551
54bf36aa 4552 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4553 if (ret < 0)
bbd9b64e 4554 return 0;
0eb05bf2 4555 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4556 return 1;
4557}
4558
77d197b2
XG		 4559struct read_write_emulator_ops {
4560 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4561 int bytes);
4562 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4563 void *val, int bytes);
4564 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4565 int bytes, void *val);
4566 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4567 void *val, int bytes);
4568 bool write;
4569};
4570
4571static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4572{
4573 if (vcpu->mmio_read_completed) {
77d197b2 4574 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4575 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4576 vcpu->mmio_read_completed = 0;
4577 return 1;
4578 }
4579
4580 return 0;
4581}
4582
4583static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4584 void *val, int bytes)
4585{
54bf36aa 4586 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4587}
4588
4589static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4590 void *val, int bytes)
4591{
4592 return emulator_write_phys(vcpu, gpa, val, bytes);
4593}
4594
4595static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4596{
4597 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4598 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4599}
4600
4601static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4602 void *val, int bytes)
4603{
4604 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4605 return X86EMUL_IO_NEEDED;
4606}
4607
4608static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4609 void *val, int bytes)
4610{
f78146b0
AK		 4611 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4612
87da7e66 4613 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4614 return X86EMUL_CONTINUE;
4615}
4616
0fbe9b0b 4617static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4618 .read_write_prepare = read_prepare,
4619 .read_write_emulate = read_emulate,
4620 .read_write_mmio = vcpu_mmio_read,
4621 .read_write_exit_mmio = read_exit_mmio,
4622};
4623
0fbe9b0b 4624static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4625 .read_write_emulate = write_emulate,
4626 .read_write_mmio = write_mmio,
4627 .read_write_exit_mmio = write_exit_mmio,
4628 .write = true,
4629};
4630
22388a3c
XG		 4631static int emulator_read_write_onepage(unsigned long addr, void *val,
4632 unsigned int bytes,
4633 struct x86_exception *exception,
4634 struct kvm_vcpu *vcpu,
0fbe9b0b 4635 const struct read_write_emulator_ops *ops)
bbd9b64e 4636{
af7cc7d1
XG		 4637 gpa_t gpa;
4638 int handled, ret;
22388a3c 4639 bool write = ops->write;
f78146b0 4640 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4641 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4642
4643 /*
4644 * If the exit was due to a NPF we may already have a GPA.
4645 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4646 * Note, this cannot be used on string operations since string
4647 * operation using rep will only have the initial GPA from the NPF
4648 * occurred.
4649 */
4650 if (vcpu->arch.gpa_available &&
4651 emulator_can_use_gpa(ctxt) &&
4652 vcpu_is_mmio_gpa(vcpu, addr, exception->address, write) &&
4653 (addr & ~PAGE_MASK) == (exception->address & ~PAGE_MASK)) {
4654 gpa = exception->address;
4655 goto mmio;
4656 }
10589a46 4657
22388a3c 4658 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4659
af7cc7d1 4660 if (ret < 0)
bbd9b64e 4661 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4662
4663 /* For APIC access vmexit */
af7cc7d1 4664 if (ret)
bbd9b64e
CO		 4665 goto mmio;
4666
22388a3c 4667 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4668 return X86EMUL_CONTINUE;
4669
4670mmio:
4671 /*
4672 * Is this MMIO handled locally?
4673 */
22388a3c 4674 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4675 if (handled == bytes)
bbd9b64e 4676 return X86EMUL_CONTINUE;
bbd9b64e 4677
70252a10
AK		 4678 gpa += handled;
4679 bytes -= handled;
4680 val += handled;
4681
87da7e66
XG		 4682 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4683 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4684 frag->gpa = gpa;
4685 frag->data = val;
4686 frag->len = bytes;
f78146b0 4687 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4688}
4689
52eb5a6d
XL		 4690static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4691 unsigned long addr,
22388a3c
XG		 4692 void *val, unsigned int bytes,
4693 struct x86_exception *exception,
0fbe9b0b 4694 const struct read_write_emulator_ops *ops)
bbd9b64e 4695{
0f65dd70 4696 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4697 gpa_t gpa;
4698 int rc;
4699
4700 if (ops->read_write_prepare &&
4701 ops->read_write_prepare(vcpu, val, bytes))
4702 return X86EMUL_CONTINUE;
4703
4704 vcpu->mmio_nr_fragments = 0;
0f65dd70 4705
bbd9b64e
CO		 4706 /* Crossing a page boundary? */
4707 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4708 int now;
bbd9b64e
CO		 4709
4710 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4711 rc = emulator_read_write_onepage(addr, val, now, exception,
4712 vcpu, ops);
4713
bbd9b64e
CO		 4714 if (rc != X86EMUL_CONTINUE)
4715 return rc;
4716 addr += now;
bac15531
NA		 4717 if (ctxt->mode != X86EMUL_MODE_PROT64)
4718 addr = (u32)addr;
bbd9b64e
CO		 4719 val += now;
4720 bytes -= now;
4721 }
22388a3c 4722
f78146b0
AK		 4723 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4724 vcpu, ops);
4725 if (rc != X86EMUL_CONTINUE)
4726 return rc;
4727
4728 if (!vcpu->mmio_nr_fragments)
4729 return rc;
4730
4731 gpa = vcpu->mmio_fragments[0].gpa;
4732
4733 vcpu->mmio_needed = 1;
4734 vcpu->mmio_cur_fragment = 0;
4735
87da7e66 4736 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4737 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4738 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4739 vcpu->run->mmio.phys_addr = gpa;
4740
4741 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4742}
4743
4744static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4745 unsigned long addr,
4746 void *val,
4747 unsigned int bytes,
4748 struct x86_exception *exception)
4749{
4750 return emulator_read_write(ctxt, addr, val, bytes,
4751 exception, &read_emultor);
4752}
4753
52eb5a6d 4754static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4755 unsigned long addr,
4756 const void *val,
4757 unsigned int bytes,
4758 struct x86_exception *exception)
4759{
4760 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4761 exception, &write_emultor);
bbd9b64e 4762}
bbd9b64e 4763
daea3e73
AK		 4764#define CMPXCHG_TYPE(t, ptr, old, new) \
4765 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4766
4767#ifdef CONFIG_X86_64
4768# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4769#else
4770# define CMPXCHG64(ptr, old, new) \
9749a6c0 4771 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4772#endif
4773
0f65dd70
AK		 4774static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4775 unsigned long addr,
bbd9b64e
CO		 4776 const void *old,
4777 const void *new,
4778 unsigned int bytes,
0f65dd70 4779 struct x86_exception *exception)
bbd9b64e 4780{
0f65dd70 4781 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4782 gpa_t gpa;
4783 struct page *page;
4784 char *kaddr;
4785 bool exchanged;
2bacc55c 4786
daea3e73
AK		 4787 /* guests cmpxchg8b have to be emulated atomically */
4788 if (bytes > 8 || (bytes & (bytes - 1)))
4789 goto emul_write;
10589a46 4790
daea3e73 4791 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4792
daea3e73
AK		 4793 if (gpa == UNMAPPED_GVA ||
4794 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4795 goto emul_write;
2bacc55c 4796
daea3e73
AK		 4797 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4798 goto emul_write;
72dc67a6 4799
54bf36aa 4800 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4801 if (is_error_page(page))
c19b8bd6 4802 goto emul_write;
72dc67a6 4803
8fd75e12 4804 kaddr = kmap_atomic(page);
daea3e73
AK		 4805 kaddr += offset_in_page(gpa);
4806 switch (bytes) {
4807 case 1:
4808 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4809 break;
4810 case 2:
4811 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4812 break;
4813 case 4:
4814 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4815 break;
4816 case 8:
4817 exchanged = CMPXCHG64(kaddr, old, new);
4818 break;
4819 default:
4820 BUG();
2bacc55c 4821 }
8fd75e12 4822 kunmap_atomic(kaddr);
daea3e73
AK		 4823 kvm_release_page_dirty(page);
4824
4825 if (!exchanged)
4826 return X86EMUL_CMPXCHG_FAILED;
4827
54bf36aa 4828 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4829 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4830
4831 return X86EMUL_CONTINUE;
4a5f48f6 4832
3200f405 4833emul_write:
daea3e73 4834 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4835
0f65dd70 4836 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4837}
4838
cf8f70bf
GN		 4839static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4840{
4841 /* TODO: String I/O for in kernel device */
4842 int r;
4843
4844 if (vcpu->arch.pio.in)
e32edf4f 4845 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4846 vcpu->arch.pio.size, pd);
4847 else
e32edf4f 4848 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4849 vcpu->arch.pio.port, vcpu->arch.pio.size,
4850 pd);
4851 return r;
4852}
4853
6f6fbe98
XG		 4854static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4855 unsigned short port, void *val,
4856 unsigned int count, bool in)
cf8f70bf 4857{
cf8f70bf 4858 vcpu->arch.pio.port = port;
6f6fbe98 4859 vcpu->arch.pio.in = in;
7972995b 4860 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4861 vcpu->arch.pio.size = size;
4862
4863 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4864 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4865 return 1;
4866 }
4867
4868 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4869 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4870 vcpu->run->io.size = size;
4871 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4872 vcpu->run->io.count = count;
4873 vcpu->run->io.port = port;
4874
4875 return 0;
4876}
4877
6f6fbe98
XG		 4878static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4879 int size, unsigned short port, void *val,
4880 unsigned int count)
cf8f70bf 4881{
ca1d4a9e 4882 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4883 int ret;
ca1d4a9e 4884
6f6fbe98
XG		 4885 if (vcpu->arch.pio.count)
4886 goto data_avail;
cf8f70bf 4887
6f6fbe98
XG		 4888 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4889 if (ret) {
4890data_avail:
4891 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4892 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4893 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4894 return 1;
4895 }
4896
cf8f70bf
GN		 4897 return 0;
4898}
4899
6f6fbe98
XG		 4900static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4901 int size, unsigned short port,
4902 const void *val, unsigned int count)
4903{
4904 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4905
4906 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4907 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4908 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4909}
4910
bbd9b64e
CO		 4911static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4912{
4913 return kvm_x86_ops->get_segment_base(vcpu, seg);
4914}
4915
3cb16fe7 4916static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4917{
3cb16fe7 4918 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4919}
4920
ae6a2375 4921static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4922{
4923 if (!need_emulate_wbinvd(vcpu))
4924 return X86EMUL_CONTINUE;
4925
4926 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4927 int cpu = get_cpu();
4928
4929 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4930 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4931 wbinvd_ipi, NULL, 1);
2eec7343 4932 put_cpu();
f5f48ee1 4933 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4934 } else
4935 wbinvd();
f5f48ee1
SY		 4936 return X86EMUL_CONTINUE;
4937}
5cb56059
JS		 4938
4939int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4940{
6affcbed
KH		 4941 kvm_emulate_wbinvd_noskip(vcpu);
4942 return kvm_skip_emulated_instruction(vcpu);
5cb56059 4943}
f5f48ee1
SY		 4944EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4945
5cb56059
JS		 4946
4947
bcaf5cc5
AK		 4948static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4949{
5cb56059 4950 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4951}
4952
52eb5a6d
XL		 4953static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4954 unsigned long *dest)
bbd9b64e 4955{
16f8a6f9 4956 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4957}
4958
52eb5a6d
XL		 4959static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4960 unsigned long value)
bbd9b64e 4961{
338dbc97 4962
717746e3 4963 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4964}
4965
52a46617 4966static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4967{
52a46617 4968 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4969}
4970
717746e3 4971static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4972{
717746e3 4973 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4974 unsigned long value;
4975
4976 switch (cr) {
4977 case 0:
4978 value = kvm_read_cr0(vcpu);
4979 break;
4980 case 2:
4981 value = vcpu->arch.cr2;
4982 break;
4983 case 3:
9f8fe504 4984 value = kvm_read_cr3(vcpu);
52a46617
GN		 4985 break;
4986 case 4:
4987 value = kvm_read_cr4(vcpu);
4988 break;
4989 case 8:
4990 value = kvm_get_cr8(vcpu);
4991 break;
4992 default:
a737f256 4993 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4994 return 0;
4995 }
4996
4997 return value;
4998}
4999
717746e3 5000static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5001{
717746e3 5002 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5003 int res = 0;
5004
52a46617
GN		 5005 switch (cr) {
5006 case 0:
49a9b07e 5007 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5008 break;
5009 case 2:
5010 vcpu->arch.cr2 = val;
5011 break;
5012 case 3:
2390218b 5013 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5014 break;
5015 case 4:
a83b29c6 5016 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5017 break;
5018 case 8:
eea1cff9 5019 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5020 break;
5021 default:
a737f256 5022 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5023 res = -1;
52a46617 5024 }
0f12244f
GN		 5025
5026 return res;
52a46617
GN		 5027}
5028
717746e3 5029static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5030{
717746e3 5031 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5032}
5033
4bff1e86 5034static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5035{
4bff1e86 5036 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5037}
5038
4bff1e86 5039static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5040{
4bff1e86 5041 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5042}
5043
1ac9d0cf
AK		 5044static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5045{
5046 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5047}
5048
5049static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5050{
5051 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5052}
5053
4bff1e86
AK		 5054static unsigned long emulator_get_cached_segment_base(
5055 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5056{
4bff1e86 5057 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5058}
5059
1aa36616
AK		 5060static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5061 struct desc_struct *desc, u32 *base3,
5062 int seg)
2dafc6c2
GN		 5063{
5064 struct kvm_segment var;
5065
4bff1e86 5066 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5067 *selector = var.selector;
2dafc6c2 5068
378a8b09
GN		 5069 if (var.unusable) {
5070 memset(desc, 0, sizeof(*desc));
2dafc6c2 5071 return false;
378a8b09 5072 }
2dafc6c2
GN		 5073
5074 if (var.g)
5075 var.limit >>= 12;
5076 set_desc_limit(desc, var.limit);
5077 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5078#ifdef CONFIG_X86_64
5079 if (base3)
5080 *base3 = var.base >> 32;
5081#endif
2dafc6c2
GN		 5082 desc->type = var.type;
5083 desc->s = var.s;
5084 desc->dpl = var.dpl;
5085 desc->p = var.present;
5086 desc->avl = var.avl;
5087 desc->l = var.l;
5088 desc->d = var.db;
5089 desc->g = var.g;
5090
5091 return true;
5092}
5093
1aa36616
AK		 5094static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5095 struct desc_struct *desc, u32 base3,
5096 int seg)
2dafc6c2 5097{
4bff1e86 5098 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5099 struct kvm_segment var;
5100
1aa36616 5101 var.selector = selector;
2dafc6c2 5102 var.base = get_desc_base(desc);
5601d05b
GN		 5103#ifdef CONFIG_X86_64
5104 var.base |= ((u64)base3) << 32;
5105#endif
2dafc6c2
GN		 5106 var.limit = get_desc_limit(desc);
5107 if (desc->g)
5108 var.limit = (var.limit << 12) | 0xfff;
5109 var.type = desc->type;
2dafc6c2
GN		 5110 var.dpl = desc->dpl;
5111 var.db = desc->d;
5112 var.s = desc->s;
5113 var.l = desc->l;
5114 var.g = desc->g;
5115 var.avl = desc->avl;
5116 var.present = desc->p;
5117 var.unusable = !var.present;
5118 var.padding = 0;
5119
5120 kvm_set_segment(vcpu, &var, seg);
5121 return;
5122}
5123
717746e3
AK		 5124static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5125 u32 msr_index, u64 *pdata)
5126{
609e36d3
PB		 5127 struct msr_data msr;
5128 int r;
5129
5130 msr.index = msr_index;
5131 msr.host_initiated = false;
5132 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5133 if (r)
5134 return r;
5135
5136 *pdata = msr.data;
5137 return 0;
717746e3
AK		 5138}
5139
5140static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5141 u32 msr_index, u64 data)
5142{
8fe8ab46
WA		 5143 struct msr_data msr;
5144
5145 msr.data = data;
5146 msr.index = msr_index;
5147 msr.host_initiated = false;
5148 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5149}
5150
64d60670
PB		 5151static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5152{
5153 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5154
5155 return vcpu->arch.smbase;
5156}
5157
5158static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5159{
5160 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5161
5162 vcpu->arch.smbase = smbase;
5163}
5164
67f4d428
NA		 5165static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5166 u32 pmc)
5167{
c6702c9d 5168 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5169}
5170
222d21aa
AK		 5171static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5172 u32 pmc, u64 *pdata)
5173{
c6702c9d 5174 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5175}
5176
6c3287f7
AK		 5177static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5178{
5179 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5180}
5181
5037f6f3
AK		 5182static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5183{
5184 preempt_disable();
5197b808 5185 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5186}
5187
5188static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5189{
5190 preempt_enable();
5191}
5192
2953538e 5193static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5194 struct x86_instruction_info *info,
c4f035c6
AK		 5195 enum x86_intercept_stage stage)
5196{
2953538e 5197 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5198}
5199
0017f93a 5200static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5201 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5202{
0017f93a 5203 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5204}
5205
dd856efa
AK		 5206static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5207{
5208 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5209}
5210
5211static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5212{
5213 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5214}
5215
801806d9
NA		 5216static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5217{
5218 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5219}
5220
0225fb50 5221static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5222 .read_gpr = emulator_read_gpr,
5223 .write_gpr = emulator_write_gpr,
1871c602 5224 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5225 .write_std = kvm_write_guest_virt_system,
7a036a6f 5226 .read_phys = kvm_read_guest_phys_system,
1871c602 5227 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5228 .read_emulated = emulator_read_emulated,
5229 .write_emulated = emulator_write_emulated,
5230 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5231 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5232 .pio_in_emulated = emulator_pio_in_emulated,
5233 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5234 .get_segment = emulator_get_segment,
5235 .set_segment = emulator_set_segment,
5951c442 5236 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5237 .get_gdt = emulator_get_gdt,
160ce1f1 5238 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5239 .set_gdt = emulator_set_gdt,
5240 .set_idt = emulator_set_idt,
52a46617
GN		 5241 .get_cr = emulator_get_cr,
5242 .set_cr = emulator_set_cr,
9c537244 5243 .cpl = emulator_get_cpl,
35aa5375
GN		 5244 .get_dr = emulator_get_dr,
5245 .set_dr = emulator_set_dr,
64d60670
PB		 5246 .get_smbase = emulator_get_smbase,
5247 .set_smbase = emulator_set_smbase,
717746e3
AK		 5248 .set_msr = emulator_set_msr,
5249 .get_msr = emulator_get_msr,
67f4d428 5250 .check_pmc = emulator_check_pmc,
222d21aa 5251 .read_pmc = emulator_read_pmc,
6c3287f7 5252 .halt = emulator_halt,
bcaf5cc5 5253 .wbinvd = emulator_wbinvd,
d6aa1000 5254 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5255 .get_fpu = emulator_get_fpu,
5256 .put_fpu = emulator_put_fpu,
c4f035c6 5257 .intercept = emulator_intercept,
bdb42f5a 5258 .get_cpuid = emulator_get_cpuid,
801806d9 5259 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5260};
5261
95cb2295
GN		 5262static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5263{
37ccdcbe 5264 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5265 /*
5266 * an sti; sti; sequence only disable interrupts for the first
5267 * instruction. So, if the last instruction, be it emulated or
5268 * not, left the system with the INT_STI flag enabled, it
5269 * means that the last instruction is an sti. We should not
5270 * leave the flag on in this case. The same goes for mov ss
5271 */
37ccdcbe
PB		 5272 if (int_shadow & mask)
5273 mask = 0;
6addfc42 5274 if (unlikely(int_shadow || mask)) {
95cb2295 5275 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5276 if (!mask)
5277 kvm_make_request(KVM_REQ_EVENT, vcpu);
5278 }
95cb2295
GN		 5279}
5280
ef54bcfe 5281static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5282{
5283 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5284 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5285 return kvm_propagate_fault(vcpu, &ctxt->exception);
5286
5287 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5288 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5289 ctxt->exception.error_code);
54b8486f 5290 else
da9cb575 5291 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5292 return false;
54b8486f
GN		 5293}
5294
8ec4722d
MG		 5295static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5296{
adf52235 5297 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5298 int cs_db, cs_l;
5299
8ec4722d
MG		 5300 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5301
adf52235
TY		 5302 ctxt->eflags = kvm_get_rflags(vcpu);
5303 ctxt->eip = kvm_rip_read(vcpu);
5304 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5305 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5306 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5307 cs_db ? X86EMUL_MODE_PROT32 :
5308 X86EMUL_MODE_PROT16;
a584539b 5309 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5310 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5311 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 5312 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 5313
dd856efa 5314 init_decode_cache(ctxt);
7ae441ea 5315 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5316}
5317
71f9833b 5318int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5319{
9d74191a 5320 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5321 int ret;
5322
5323 init_emulate_ctxt(vcpu);
5324
9dac77fa
AK		 5325 ctxt->op_bytes = 2;
5326 ctxt->ad_bytes = 2;
5327 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5328 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5329
5330 if (ret != X86EMUL_CONTINUE)
5331 return EMULATE_FAIL;
5332
9dac77fa 5333 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5334 kvm_rip_write(vcpu, ctxt->eip);
5335 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5336
5337 if (irq == NMI_VECTOR)
7460fb4a 5338 vcpu->arch.nmi_pending = 0;
63995653
MG		 5339 else
5340 vcpu->arch.interrupt.pending = false;
5341
5342 return EMULATE_DONE;
5343}
5344EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5345
6d77dbfc
GN		 5346static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5347{
fc3a9157
JR		 5348 int r = EMULATE_DONE;
5349
6d77dbfc
GN		 5350 ++vcpu->stat.insn_emulation_fail;
5351 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5352 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5353 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5354 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5355 vcpu->run->internal.ndata = 0;
5356 r = EMULATE_FAIL;
5357 }
6d77dbfc 5358 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5359
5360 return r;
6d77dbfc
GN		 5361}
5362
93c05d3e 5363static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5364 bool write_fault_to_shadow_pgtable,
5365 int emulation_type)
a6f177ef 5366{
95b3cf69 5367 gpa_t gpa = cr2;
ba049e93 5368 kvm_pfn_t pfn;
a6f177ef 5369
991eebf9
GN		 5370 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5371 return false;
5372
95b3cf69
XG		 5373 if (!vcpu->arch.mmu.direct_map) {
5374 /*
5375 * Write permission should be allowed since only
5376 * write access need to be emulated.
5377 */
5378 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5379
95b3cf69
XG		 5380 /*
5381 * If the mapping is invalid in guest, let cpu retry
5382 * it to generate fault.
5383 */
5384 if (gpa == UNMAPPED_GVA)
5385 return true;
5386 }
a6f177ef 5387
8e3d9d06
XG		 5388 /*
5389 * Do not retry the unhandleable instruction if it faults on the
5390 * readonly host memory, otherwise it will goto a infinite loop:
5391 * retry instruction -> write #PF -> emulation fail -> retry
5392 * instruction -> ...
5393 */
5394 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5395
5396 /*
5397 * If the instruction failed on the error pfn, it can not be fixed,
5398 * report the error to userspace.
5399 */
5400 if (is_error_noslot_pfn(pfn))
5401 return false;
5402
5403 kvm_release_pfn_clean(pfn);
5404
5405 /* The instructions are well-emulated on direct mmu. */
5406 if (vcpu->arch.mmu.direct_map) {
5407 unsigned int indirect_shadow_pages;
5408
5409 spin_lock(&vcpu->kvm->mmu_lock);
5410 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5411 spin_unlock(&vcpu->kvm->mmu_lock);
5412
5413 if (indirect_shadow_pages)
5414 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5415
a6f177ef 5416 return true;
8e3d9d06 5417 }
a6f177ef 5418
95b3cf69
XG		 5419 /*
5420 * if emulation was due to access to shadowed page table
5421 * and it failed try to unshadow page and re-enter the
5422 * guest to let CPU execute the instruction.
5423 */
5424 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5425
5426 /*
5427 * If the access faults on its page table, it can not
5428 * be fixed by unprotecting shadow page and it should
5429 * be reported to userspace.
5430 */
5431 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5432}
5433
1cb3f3ae
XG		 5434static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5435 unsigned long cr2, int emulation_type)
5436{
5437 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5438 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5439
5440 last_retry_eip = vcpu->arch.last_retry_eip;
5441 last_retry_addr = vcpu->arch.last_retry_addr;
5442
5443 /*
5444 * If the emulation is caused by #PF and it is non-page_table
5445 * writing instruction, it means the VM-EXIT is caused by shadow
5446 * page protected, we can zap the shadow page and retry this
5447 * instruction directly.
5448 *
5449 * Note: if the guest uses a non-page-table modifying instruction
5450 * on the PDE that points to the instruction, then we will unmap
5451 * the instruction and go to an infinite loop. So, we cache the
5452 * last retried eip and the last fault address, if we meet the eip
5453 * and the address again, we can break out of the potential infinite
5454 * loop.
5455 */
5456 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5457
5458 if (!(emulation_type & EMULTYPE_RETRY))
5459 return false;
5460
5461 if (x86_page_table_writing_insn(ctxt))
5462 return false;
5463
5464 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5465 return false;
5466
5467 vcpu->arch.last_retry_eip = ctxt->eip;
5468 vcpu->arch.last_retry_addr = cr2;
5469
5470 if (!vcpu->arch.mmu.direct_map)
5471 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5472
22368028 5473 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5474
5475 return true;
5476}
5477
716d51ab
GN		 5478static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5479static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5480
64d60670 5481static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5482{
64d60670 5483 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5484 /* This is a good place to trace that we are exiting SMM. */
5485 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5486
c43203ca
PB		 5487 /* Process a latched INIT or SMI, if any. */
5488 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5489 }
699023e2
PB		 5490
5491 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5492}
5493
5494static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5495{
5496 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5497
a584539b 5498 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5499
5500 if (changed & HF_SMM_MASK)
5501 kvm_smm_changed(vcpu);
a584539b
PB		 5502}
5503
4a1e10d5
PB		 5504static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5505 unsigned long *db)
5506{
5507 u32 dr6 = 0;
5508 int i;
5509 u32 enable, rwlen;
5510
5511 enable = dr7;
5512 rwlen = dr7 >> 16;
5513 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5514 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5515 dr6 |= (1 << i);
5516 return dr6;
5517}
5518
6addfc42 5519static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5520{
5521 struct kvm_run *kvm_run = vcpu->run;
5522
5523 /*
6addfc42
PB		 5524 * rflags is the old, "raw" value of the flags. The new value has
5525 * not been saved yet.
663f4c61
PB		 5526 *
5527 * This is correct even for TF set by the guest, because "the
5528 * processor will not generate this exception after the instruction
5529 * that sets the TF flag".
5530 */
663f4c61
PB		 5531 if (unlikely(rflags & X86_EFLAGS_TF)) {
5532 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5533 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5534 DR6_RTM;
663f4c61
PB		 5535 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5536 kvm_run->debug.arch.exception = DB_VECTOR;
5537 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5538 *r = EMULATE_USER_EXIT;
5539 } else {
663f4c61
PB		 5540 /*
5541 * "Certain debug exceptions may clear bit 0-3. The
5542 * remaining contents of the DR6 register are never
5543 * cleared by the processor".
5544 */
5545 vcpu->arch.dr6 &= ~15;
6f43ed01 5546 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5547 kvm_queue_exception(vcpu, DB_VECTOR);
5548 }
5549 }
5550}
5551
6affcbed
KH		 5552int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5553{
5554 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5555 int r = EMULATE_DONE;
5556
5557 kvm_x86_ops->skip_emulated_instruction(vcpu);
5558 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5559 return r == EMULATE_DONE;
5560}
5561EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5562
4a1e10d5
PB		 5563static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5564{
4a1e10d5
PB		 5565 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5566 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5567 struct kvm_run *kvm_run = vcpu->run;
5568 unsigned long eip = kvm_get_linear_rip(vcpu);
5569 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5570 vcpu->arch.guest_debug_dr7,
5571 vcpu->arch.eff_db);
5572
5573 if (dr6 != 0) {
6f43ed01 5574 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5575 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5576 kvm_run->debug.arch.exception = DB_VECTOR;
5577 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5578 *r = EMULATE_USER_EXIT;
5579 return true;
5580 }
5581 }
5582
4161a569
NA		 5583 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5584 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5585 unsigned long eip = kvm_get_linear_rip(vcpu);
5586 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5587 vcpu->arch.dr7,
5588 vcpu->arch.db);
5589
5590 if (dr6 != 0) {
5591 vcpu->arch.dr6 &= ~15;
6f43ed01 5592 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5593 kvm_queue_exception(vcpu, DB_VECTOR);
5594 *r = EMULATE_DONE;
5595 return true;
5596 }
5597 }
5598
5599 return false;
5600}
5601
51d8b661
AP		 5602int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5603 unsigned long cr2,
dc25e89e
AP		 5604 int emulation_type,
5605 void *insn,
5606 int insn_len)
bbd9b64e 5607{
95cb2295 5608 int r;
9d74191a 5609 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5610 bool writeback = true;
93c05d3e 5611 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5612
93c05d3e
XG		 5613 /*
5614 * Clear write_fault_to_shadow_pgtable here to ensure it is
5615 * never reused.
5616 */
5617 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5618 kvm_clear_exception_queue(vcpu);
8d7d8102 5619
571008da 5620 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5621 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5622
5623 /*
5624 * We will reenter on the same instruction since
5625 * we do not set complete_userspace_io. This does not
5626 * handle watchpoints yet, those would be handled in
5627 * the emulate_ops.
5628 */
5629 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5630 return r;
5631
9d74191a
TY		 5632 ctxt->interruptibility = 0;
5633 ctxt->have_exception = false;
e0ad0b47 5634 ctxt->exception.vector = -1;
9d74191a 5635 ctxt->perm_ok = false;
bbd9b64e 5636
b51e974f 5637 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5638
9d74191a 5639 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5640
e46479f8 5641 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5642 ++vcpu->stat.insn_emulation;
1d2887e2 5643 if (r != EMULATION_OK) {
4005996e
AK		 5644 if (emulation_type & EMULTYPE_TRAP_UD)
5645 return EMULATE_FAIL;
991eebf9
GN		 5646 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5647 emulation_type))
bbd9b64e 5648 return EMULATE_DONE;
6d77dbfc
GN		 5649 if (emulation_type & EMULTYPE_SKIP)
5650 return EMULATE_FAIL;
5651 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5652 }
5653 }
5654
ba8afb6b 5655 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5656 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5657 if (ctxt->eflags & X86_EFLAGS_RF)
5658 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5659 return EMULATE_DONE;
5660 }
5661
1cb3f3ae
XG		 5662 if (retry_instruction(ctxt, cr2, emulation_type))
5663 return EMULATE_DONE;
5664
7ae441ea 5665 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5666 changes registers values during IO operation */
7ae441ea
GN		 5667 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5668 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5669 emulator_invalidate_register_cache(ctxt);
7ae441ea 5670 }
4d2179e1 5671
5cd21917 5672restart:
0f89b207
TL		 5673 /* Save the faulting GPA (cr2) in the address field */
5674 ctxt->exception.address = cr2;
5675
9d74191a 5676 r = x86_emulate_insn(ctxt);
bbd9b64e 5677
775fde86
JR		 5678 if (r == EMULATION_INTERCEPTED)
5679 return EMULATE_DONE;
5680
d2ddd1c4 5681 if (r == EMULATION_FAILED) {
991eebf9
GN		 5682 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5683 emulation_type))
c3cd7ffa
GN		 5684 return EMULATE_DONE;
5685
6d77dbfc 5686 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5687 }
5688
9d74191a 5689 if (ctxt->have_exception) {
d2ddd1c4 5690 r = EMULATE_DONE;
ef54bcfe
PB		 5691 if (inject_emulated_exception(vcpu))
5692 return r;
d2ddd1c4 5693 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5694 if (!vcpu->arch.pio.in) {
5695 /* FIXME: return into emulator if single-stepping. */
3457e419 5696 vcpu->arch.pio.count = 0;
0912c977 5697 } else {
7ae441ea 5698 writeback = false;
716d51ab
GN		 5699 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5700 }
ac0a48c3 5701 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5702 } else if (vcpu->mmio_needed) {
5703 if (!vcpu->mmio_is_write)
5704 writeback = false;
ac0a48c3 5705 r = EMULATE_USER_EXIT;
716d51ab 5706 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5707 } else if (r == EMULATION_RESTART)
5cd21917 5708 goto restart;
d2ddd1c4
GN		 5709 else
5710 r = EMULATE_DONE;
f850e2e6 5711
7ae441ea 5712 if (writeback) {
6addfc42 5713 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5714 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5715 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5716 if (vcpu->arch.hflags != ctxt->emul_flags)
5717 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5718 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5719 if (r == EMULATE_DONE)
6addfc42 5720 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5721 if (!ctxt->have_exception ||
5722 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5723 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5724
5725 /*
5726 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5727 * do nothing, and it will be requested again as soon as
5728 * the shadow expires. But we still need to check here,
5729 * because POPF has no interrupt shadow.
5730 */
5731 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5732 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5733 } else
5734 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5735
5736 return r;
de7d789a 5737}
51d8b661 5738EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5739
cf8f70bf 5740int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5741{
cf8f70bf 5742 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5743 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5744 size, port, &val, 1);
cf8f70bf 5745 /* do not return to emulator after return from userspace */
7972995b 5746 vcpu->arch.pio.count = 0;
de7d789a
CO		 5747 return ret;
5748}
cf8f70bf 5749EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5750
8370c3d0
TL		 5751static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5752{
5753 unsigned long val;
5754
5755 /* We should only ever be called with arch.pio.count equal to 1 */
5756 BUG_ON(vcpu->arch.pio.count != 1);
5757
5758 /* For size less than 4 we merge, else we zero extend */
5759 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5760 : 0;
5761
5762 /*
5763 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5764 * the copy and tracing
5765 */
5766 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5767 vcpu->arch.pio.port, &val, 1);
5768 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5769
5770 return 1;
5771}
5772
5773int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5774{
5775 unsigned long val;
5776 int ret;
5777
5778 /* For size less than 4 we merge, else we zero extend */
5779 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5780
5781 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5782 &val, 1);
5783 if (ret) {
5784 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5785 return ret;
5786 }
5787
5788 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5789
5790 return 0;
5791}
5792EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5793
251a5fd6 5794static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5795{
0a3aee0d 5796 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5797 return 0;
8cfdc000
ZA		 5798}
5799
5800static void tsc_khz_changed(void *data)
c8076604 5801{
8cfdc000
ZA		 5802 struct cpufreq_freqs *freq = data;
5803 unsigned long khz = 0;
5804
5805 if (data)
5806 khz = freq->new;
5807 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5808 khz = cpufreq_quick_get(raw_smp_processor_id());
5809 if (!khz)
5810 khz = tsc_khz;
0a3aee0d 5811 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5812}
5813
c8076604
GH		 5814static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5815 void *data)
5816{
5817 struct cpufreq_freqs *freq = data;
5818 struct kvm *kvm;
5819 struct kvm_vcpu *vcpu;
5820 int i, send_ipi = 0;
5821
8cfdc000
ZA		 5822 /*
5823 * We allow guests to temporarily run on slowing clocks,
5824 * provided we notify them after, or to run on accelerating
5825 * clocks, provided we notify them before. Thus time never
5826 * goes backwards.
5827 *
5828 * However, we have a problem. We can't atomically update
5829 * the frequency of a given CPU from this function; it is
5830 * merely a notifier, which can be called from any CPU.
5831 * Changing the TSC frequency at arbitrary points in time
5832 * requires a recomputation of local variables related to
5833 * the TSC for each VCPU. We must flag these local variables
5834 * to be updated and be sure the update takes place with the
5835 * new frequency before any guests proceed.
5836 *
5837 * Unfortunately, the combination of hotplug CPU and frequency
5838 * change creates an intractable locking scenario; the order
5839 * of when these callouts happen is undefined with respect to
5840 * CPU hotplug, and they can race with each other. As such,
5841 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5842 * undefined; you can actually have a CPU frequency change take
5843 * place in between the computation of X and the setting of the
5844 * variable. To protect against this problem, all updates of
5845 * the per_cpu tsc_khz variable are done in an interrupt
5846 * protected IPI, and all callers wishing to update the value
5847 * must wait for a synchronous IPI to complete (which is trivial
5848 * if the caller is on the CPU already). This establishes the
5849 * necessary total order on variable updates.
5850 *
5851 * Note that because a guest time update may take place
5852 * anytime after the setting of the VCPU's request bit, the
5853 * correct TSC value must be set before the request. However,
5854 * to ensure the update actually makes it to any guest which
5855 * starts running in hardware virtualization between the set
5856 * and the acquisition of the spinlock, we must also ping the
5857 * CPU after setting the request bit.
5858 *
5859 */
5860
c8076604
GH		 5861 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5862 return 0;
5863 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5864 return 0;
8cfdc000
ZA		 5865
5866 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5867
2f303b74 5868 spin_lock(&kvm_lock);
c8076604 5869 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5870 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5871 if (vcpu->cpu != freq->cpu)
5872 continue;
c285545f 5873 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5874 if (vcpu->cpu != smp_processor_id())
8cfdc000 5875 send_ipi = 1;
c8076604
GH		 5876 }
5877 }
2f303b74 5878 spin_unlock(&kvm_lock);
c8076604
GH		 5879
5880 if (freq->old < freq->new && send_ipi) {
5881 /*
5882 * We upscale the frequency. Must make the guest
5883 * doesn't see old kvmclock values while running with
5884 * the new frequency, otherwise we risk the guest sees
5885 * time go backwards.
5886 *
5887 * In case we update the frequency for another cpu
5888 * (which might be in guest context) send an interrupt
5889 * to kick the cpu out of guest context. Next time
5890 * guest context is entered kvmclock will be updated,
5891 * so the guest will not see stale values.
5892 */
8cfdc000 5893 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5894 }
5895 return 0;
5896}
5897
5898static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5899 .notifier_call = kvmclock_cpufreq_notifier
5900};
5901
251a5fd6 5902static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 5903{
251a5fd6
SAS		 5904 tsc_khz_changed(NULL);
5905 return 0;
8cfdc000
ZA		 5906}
5907
b820cc0c
ZA		 5908static void kvm_timer_init(void)
5909{
c285545f 5910 max_tsc_khz = tsc_khz;
460dd42e 5911
b820cc0c 5912 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5913#ifdef CONFIG_CPU_FREQ
5914 struct cpufreq_policy policy;
758f588d
BP		 5915 int cpu;
5916
c285545f 5917 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5918 cpu = get_cpu();
5919 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5920 if (policy.cpuinfo.max_freq)
5921 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5922 put_cpu();
c285545f 5923#endif
b820cc0c
ZA		 5924 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5925 CPUFREQ_TRANSITION_NOTIFIER);
5926 }
c285545f 5927 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 5928
73c1b41e 5929 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 5930 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 5931}
5932
ff9d07a0
ZY		 5933static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5934
f5132b01 5935int kvm_is_in_guest(void)
ff9d07a0 5936{
086c9855 5937 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5938}
5939
5940static int kvm_is_user_mode(void)
5941{
5942 int user_mode = 3;
dcf46b94 5943
086c9855
AS		 5944 if (__this_cpu_read(current_vcpu))
5945 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5946
ff9d07a0
ZY		 5947 return user_mode != 0;
5948}
5949
5950static unsigned long kvm_get_guest_ip(void)
5951{
5952 unsigned long ip = 0;
dcf46b94 5953
086c9855
AS		 5954 if (__this_cpu_read(current_vcpu))
5955 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5956
ff9d07a0
ZY		 5957 return ip;
5958}
5959
5960static struct perf_guest_info_callbacks kvm_guest_cbs = {
5961 .is_in_guest = kvm_is_in_guest,
5962 .is_user_mode = kvm_is_user_mode,
5963 .get_guest_ip = kvm_get_guest_ip,
5964};
5965
5966void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5967{
086c9855 5968 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5969}
5970EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5971
5972void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5973{
086c9855 5974 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5975}
5976EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5977
ce88decf
XG		 5978static void kvm_set_mmio_spte_mask(void)
5979{
5980 u64 mask;
5981 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5982
5983 /*
5984 * Set the reserved bits and the present bit of an paging-structure
5985 * entry to generate page fault with PFER.RSV = 1.
5986 */
885032b9 5987 /* Mask the reserved physical address bits. */
d1431483 5988 mask = rsvd_bits(maxphyaddr, 51);
885032b9 5989
885032b9 5990 /* Set the present bit. */
ce88decf
XG		 5991 mask |= 1ull;
5992
5993#ifdef CONFIG_X86_64
5994 /*
5995 * If reserved bit is not supported, clear the present bit to disable
5996 * mmio page fault.
5997 */
5998 if (maxphyaddr == 52)
5999 mask &= ~1ull;
6000#endif
6001
6002 kvm_mmu_set_mmio_spte_mask(mask);
6003}
6004
16e8d74d
MT		 6005#ifdef CONFIG_X86_64
6006static void pvclock_gtod_update_fn(struct work_struct *work)
6007{
d828199e
MT		 6008 struct kvm *kvm;
6009
6010 struct kvm_vcpu *vcpu;
6011 int i;
6012
2f303b74 6013 spin_lock(&kvm_lock);
d828199e
MT		 6014 list_for_each_entry(kvm, &vm_list, vm_list)
6015 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6016 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6017 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6018 spin_unlock(&kvm_lock);
16e8d74d
MT		 6019}
6020
6021static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6022
6023/*
6024 * Notification about pvclock gtod data update.
6025 */
6026static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6027 void *priv)
6028{
6029 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6030 struct timekeeper *tk = priv;
6031
6032 update_pvclock_gtod(tk);
6033
6034 /* disable master clock if host does not trust, or does not
6035 * use, TSC clocksource
6036 */
6037 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6038 atomic_read(&kvm_guest_has_master_clock) != 0)
6039 queue_work(system_long_wq, &pvclock_gtod_work);
6040
6041 return 0;
6042}
6043
6044static struct notifier_block pvclock_gtod_notifier = {
6045 .notifier_call = pvclock_gtod_notify,
6046};
6047#endif
6048
f8c16bba 6049int kvm_arch_init(void *opaque)
043405e1 6050{
b820cc0c 6051 int r;
6b61edf7 6052 struct kvm_x86_ops *ops = opaque;
f8c16bba 6053
f8c16bba
ZX		 6054 if (kvm_x86_ops) {
6055 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6056 r = -EEXIST;
6057 goto out;
f8c16bba
ZX		 6058 }
6059
6060 if (!ops->cpu_has_kvm_support()) {
6061 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6062 r = -EOPNOTSUPP;
6063 goto out;
f8c16bba
ZX		 6064 }
6065 if (ops->disabled_by_bios()) {
6066 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6067 r = -EOPNOTSUPP;
6068 goto out;
f8c16bba
ZX		 6069 }
6070
013f6a5d
MT		 6071 r = -ENOMEM;
6072 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6073 if (!shared_msrs) {
6074 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6075 goto out;
6076 }
6077
97db56ce
AK		 6078 r = kvm_mmu_module_init();
6079 if (r)
013f6a5d 6080 goto out_free_percpu;
97db56ce 6081
ce88decf 6082 kvm_set_mmio_spte_mask();
97db56ce 6083
f8c16bba 6084 kvm_x86_ops = ops;
920c8377 6085
7b52345e 6086 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6087 PT_DIRTY_MASK, PT64_NX_MASK, 0,
f160c7b7 6088 PT_PRESENT_MASK, 0);
b820cc0c 6089 kvm_timer_init();
c8076604 6090
ff9d07a0
ZY		 6091 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6092
d366bf7e 6093 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6094 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6095
c5cc421b 6096 kvm_lapic_init();
16e8d74d
MT		 6097#ifdef CONFIG_X86_64
6098 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6099#endif
6100
f8c16bba 6101 return 0;
56c6d28a 6102
013f6a5d
MT		 6103out_free_percpu:
6104 free_percpu(shared_msrs);
56c6d28a 6105out:
56c6d28a 6106 return r;
043405e1 6107}
8776e519 6108
f8c16bba
ZX		 6109void kvm_arch_exit(void)
6110{
cef84c30 6111 kvm_lapic_exit();
ff9d07a0
ZY		 6112 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6113
888d256e
JK		 6114 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6115 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6116 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6117 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6118#ifdef CONFIG_X86_64
6119 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6120#endif
f8c16bba 6121 kvm_x86_ops = NULL;
56c6d28a 6122 kvm_mmu_module_exit();
013f6a5d 6123 free_percpu(shared_msrs);
56c6d28a 6124}
f8c16bba 6125
5cb56059 6126int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6127{
6128 ++vcpu->stat.halt_exits;
35754c98 6129 if (lapic_in_kernel(vcpu)) {
a4535290 6130 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6131 return 1;
6132 } else {
6133 vcpu->run->exit_reason = KVM_EXIT_HLT;
6134 return 0;
6135 }
6136}
5cb56059
JS		 6137EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6138
6139int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6140{
6affcbed
KH		 6141 int ret = kvm_skip_emulated_instruction(vcpu);
6142 /*
6143 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6144 * KVM_EXIT_DEBUG here.
6145 */
6146 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6147}
8776e519
HB		 6148EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6149
8ef81a9a 6150#ifdef CONFIG_X86_64
55dd00a7
MT		 6151static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6152 unsigned long clock_type)
6153{
6154 struct kvm_clock_pairing clock_pairing;
6155 struct timespec ts;
80fbd89c 6156 u64 cycle;
55dd00a7
MT		 6157 int ret;
6158
6159 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6160 return -KVM_EOPNOTSUPP;
6161
6162 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6163 return -KVM_EOPNOTSUPP;
6164
6165 clock_pairing.sec = ts.tv_sec;
6166 clock_pairing.nsec = ts.tv_nsec;
6167 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6168 clock_pairing.flags = 0;
6169
6170 ret = 0;
6171 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6172 sizeof(struct kvm_clock_pairing)))
6173 ret = -KVM_EFAULT;
6174
6175 return ret;
6176}
8ef81a9a 6177#endif
55dd00a7 6178
6aef266c
SV		 6179/*
6180 * kvm_pv_kick_cpu_op: Kick a vcpu.
6181 *
6182 * @apicid - apicid of vcpu to be kicked.
6183 */
6184static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6185{
24d2166b 6186 struct kvm_lapic_irq lapic_irq;
6aef266c 6187
24d2166b
R		 6188 lapic_irq.shorthand = 0;
6189 lapic_irq.dest_mode = 0;
6190 lapic_irq.dest_id = apicid;
93bbf0b8 6191 lapic_irq.msi_redir_hint = false;
6aef266c 6192
24d2166b 6193 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6194 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6195}
6196
d62caabb
AS		 6197void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6198{
6199 vcpu->arch.apicv_active = false;
6200 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6201}
6202
8776e519
HB		 6203int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6204{
6205 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6206 int op_64_bit, r;
8776e519 6207
6affcbed 6208 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6209
55cd8e5a
GN		 6210 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6211 return kvm_hv_hypercall(vcpu);
6212
5fdbf976
MT		 6213 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6214 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6215 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6216 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6217 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6218
229456fc 6219 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6220
a449c7aa
NA		 6221 op_64_bit = is_64_bit_mode(vcpu);
6222 if (!op_64_bit) {
8776e519
HB		 6223 nr &= 0xFFFFFFFF;
6224 a0 &= 0xFFFFFFFF;
6225 a1 &= 0xFFFFFFFF;
6226 a2 &= 0xFFFFFFFF;
6227 a3 &= 0xFFFFFFFF;
6228 }
6229
07708c4a
JK		 6230 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6231 ret = -KVM_EPERM;
6232 goto out;
6233 }
6234
8776e519 6235 switch (nr) {
b93463aa
AK		 6236 case KVM_HC_VAPIC_POLL_IRQ:
6237 ret = 0;
6238 break;
6aef266c
SV		 6239 case KVM_HC_KICK_CPU:
6240 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6241 ret = 0;
6242 break;
8ef81a9a 6243#ifdef CONFIG_X86_64
55dd00a7
MT		 6244 case KVM_HC_CLOCK_PAIRING:
6245 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6246 break;
8ef81a9a 6247#endif
8776e519
HB		 6248 default:
6249 ret = -KVM_ENOSYS;
6250 break;
6251 }
07708c4a 6252out:
a449c7aa
NA		 6253 if (!op_64_bit)
6254 ret = (u32)ret;
5fdbf976 6255 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6256 ++vcpu->stat.hypercalls;
2f333bcb 6257 return r;
8776e519
HB		 6258}
6259EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6260
b6785def 6261static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6262{
d6aa1000 6263 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6264 char instruction[3];
5fdbf976 6265 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6266
8776e519 6267 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6268
ce2e852e
DV		 6269 return emulator_write_emulated(ctxt, rip, instruction, 3,
6270 &ctxt->exception);
8776e519
HB		 6271}
6272
851ba692 6273static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6274{
782d422b
MG		 6275 return vcpu->run->request_interrupt_window &&
6276 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6277}
6278
851ba692 6279static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6280{
851ba692
AK		 6281 struct kvm_run *kvm_run = vcpu->run;
6282
91586a3b 6283 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6284 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6285 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6286 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6287 kvm_run->ready_for_interrupt_injection =
6288 pic_in_kernel(vcpu->kvm) ||
782d422b 6289 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6290}
6291
95ba8273
GN		 6292static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6293{
6294 int max_irr, tpr;
6295
6296 if (!kvm_x86_ops->update_cr8_intercept)
6297 return;
6298
bce87cce 6299 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6300 return;
6301
d62caabb
AS		 6302 if (vcpu->arch.apicv_active)
6303 return;
6304
8db3baa2
GN		 6305 if (!vcpu->arch.apic->vapic_addr)
6306 max_irr = kvm_lapic_find_highest_irr(vcpu);
6307 else
6308 max_irr = -1;
95ba8273
GN		 6309
6310 if (max_irr != -1)
6311 max_irr >>= 4;
6312
6313 tpr = kvm_lapic_get_cr8(vcpu);
6314
6315 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6316}
6317
b6b8a145 6318static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6319{
b6b8a145
JK		 6320 int r;
6321
95ba8273 6322 /* try to reinject previous events if any */
b59bb7bd 6323 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6324 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6325 vcpu->arch.exception.has_error_code,
6326 vcpu->arch.exception.error_code);
d6e8c854
NA		 6327
6328 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6329 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6330 X86_EFLAGS_RF);
6331
6bdf0662
NA		 6332 if (vcpu->arch.exception.nr == DB_VECTOR &&
6333 (vcpu->arch.dr7 & DR7_GD)) {
6334 vcpu->arch.dr7 &= ~DR7_GD;
6335 kvm_update_dr7(vcpu);
6336 }
6337
b59bb7bd
GN		 6338 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6339 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6340 vcpu->arch.exception.error_code,
6341 vcpu->arch.exception.reinject);
b6b8a145 6342 return 0;
b59bb7bd
GN		 6343 }
6344
95ba8273
GN		 6345 if (vcpu->arch.nmi_injected) {
6346 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6347 return 0;
95ba8273
GN		 6348 }
6349
6350 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6351 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6352 return 0;
6353 }
6354
6355 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6356 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6357 if (r != 0)
6358 return r;
95ba8273
GN		 6359 }
6360
6361 /* try to inject new event if pending */
c43203ca
PB		 6362 if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
6363 vcpu->arch.smi_pending = false;
ee2cd4b7 6364 enter_smm(vcpu);
c43203ca 6365 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6366 --vcpu->arch.nmi_pending;
6367 vcpu->arch.nmi_injected = true;
6368 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6369 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6370 /*
6371 * Because interrupts can be injected asynchronously, we are
6372 * calling check_nested_events again here to avoid a race condition.
6373 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6374 * proposal and current concerns. Perhaps we should be setting
6375 * KVM_REQ_EVENT only on certain events and not unconditionally?
6376 */
6377 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6378 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6379 if (r != 0)
6380 return r;
6381 }
95ba8273 6382 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6383 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6384 false);
6385 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6386 }
6387 }
ee2cd4b7 6388
b6b8a145 6389 return 0;
95ba8273
GN		 6390}
6391
7460fb4a
AK		 6392static void process_nmi(struct kvm_vcpu *vcpu)
6393{
6394 unsigned limit = 2;
6395
6396 /*
6397 * x86 is limited to one NMI running, and one NMI pending after it.
6398 * If an NMI is already in progress, limit further NMIs to just one.
6399 * Otherwise, allow two (and we'll inject the first one immediately).
6400 */
6401 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6402 limit = 1;
6403
6404 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6405 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6406 kvm_make_request(KVM_REQ_EVENT, vcpu);
6407}
6408
660a5d51
PB		 6409#define put_smstate(type, buf, offset, val) \
6410 *(type *)((buf) + (offset) - 0x7e00) = val
6411
ee2cd4b7 6412static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6413{
6414 u32 flags = 0;
6415 flags |= seg->g << 23;
6416 flags |= seg->db << 22;
6417 flags |= seg->l << 21;
6418 flags |= seg->avl << 20;
6419 flags |= seg->present << 15;
6420 flags |= seg->dpl << 13;
6421 flags |= seg->s << 12;
6422 flags |= seg->type << 8;
6423 return flags;
6424}
6425
ee2cd4b7 6426static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6427{
6428 struct kvm_segment seg;
6429 int offset;
6430
6431 kvm_get_segment(vcpu, &seg, n);
6432 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6433
6434 if (n < 3)
6435 offset = 0x7f84 + n * 12;
6436 else
6437 offset = 0x7f2c + (n - 3) * 12;
6438
6439 put_smstate(u32, buf, offset + 8, seg.base);
6440 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6441 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6442}
6443
efbb288a 6444#ifdef CONFIG_X86_64
ee2cd4b7 6445static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6446{
6447 struct kvm_segment seg;
6448 int offset;
6449 u16 flags;
6450
6451 kvm_get_segment(vcpu, &seg, n);
6452 offset = 0x7e00 + n * 16;
6453
ee2cd4b7 6454 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6455 put_smstate(u16, buf, offset, seg.selector);
6456 put_smstate(u16, buf, offset + 2, flags);
6457 put_smstate(u32, buf, offset + 4, seg.limit);
6458 put_smstate(u64, buf, offset + 8, seg.base);
6459}
efbb288a 6460#endif
660a5d51 6461
ee2cd4b7 6462static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6463{
6464 struct desc_ptr dt;
6465 struct kvm_segment seg;
6466 unsigned long val;
6467 int i;
6468
6469 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6470 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6471 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6472 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6473
6474 for (i = 0; i < 8; i++)
6475 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6476
6477 kvm_get_dr(vcpu, 6, &val);
6478 put_smstate(u32, buf, 0x7fcc, (u32)val);
6479 kvm_get_dr(vcpu, 7, &val);
6480 put_smstate(u32, buf, 0x7fc8, (u32)val);
6481
6482 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6483 put_smstate(u32, buf, 0x7fc4, seg.selector);
6484 put_smstate(u32, buf, 0x7f64, seg.base);
6485 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6486 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6487
6488 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6489 put_smstate(u32, buf, 0x7fc0, seg.selector);
6490 put_smstate(u32, buf, 0x7f80, seg.base);
6491 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6492 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6493
6494 kvm_x86_ops->get_gdt(vcpu, &dt);
6495 put_smstate(u32, buf, 0x7f74, dt.address);
6496 put_smstate(u32, buf, 0x7f70, dt.size);
6497
6498 kvm_x86_ops->get_idt(vcpu, &dt);
6499 put_smstate(u32, buf, 0x7f58, dt.address);
6500 put_smstate(u32, buf, 0x7f54, dt.size);
6501
6502 for (i = 0; i < 6; i++)
ee2cd4b7 6503 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6504
6505 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6506
6507 /* revision id */
6508 put_smstate(u32, buf, 0x7efc, 0x00020000);
6509 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6510}
6511
ee2cd4b7 6512static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6513{
6514#ifdef CONFIG_X86_64
6515 struct desc_ptr dt;
6516 struct kvm_segment seg;
6517 unsigned long val;
6518 int i;
6519
6520 for (i = 0; i < 16; i++)
6521 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6522
6523 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6524 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6525
6526 kvm_get_dr(vcpu, 6, &val);
6527 put_smstate(u64, buf, 0x7f68, val);
6528 kvm_get_dr(vcpu, 7, &val);
6529 put_smstate(u64, buf, 0x7f60, val);
6530
6531 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6532 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6533 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6534
6535 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6536
6537 /* revision id */
6538 put_smstate(u32, buf, 0x7efc, 0x00020064);
6539
6540 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6541
6542 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6543 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6544 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6545 put_smstate(u32, buf, 0x7e94, seg.limit);
6546 put_smstate(u64, buf, 0x7e98, seg.base);
6547
6548 kvm_x86_ops->get_idt(vcpu, &dt);
6549 put_smstate(u32, buf, 0x7e84, dt.size);
6550 put_smstate(u64, buf, 0x7e88, dt.address);
6551
6552 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6553 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6554 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6555 put_smstate(u32, buf, 0x7e74, seg.limit);
6556 put_smstate(u64, buf, 0x7e78, seg.base);
6557
6558 kvm_x86_ops->get_gdt(vcpu, &dt);
6559 put_smstate(u32, buf, 0x7e64, dt.size);
6560 put_smstate(u64, buf, 0x7e68, dt.address);
6561
6562 for (i = 0; i < 6; i++)
ee2cd4b7 6563 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6564#else
6565 WARN_ON_ONCE(1);
6566#endif
6567}
6568
ee2cd4b7 6569static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6570{
660a5d51 6571 struct kvm_segment cs, ds;
18c3626e 6572 struct desc_ptr dt;
660a5d51
PB		 6573 char buf[512];
6574 u32 cr0;
6575
660a5d51
PB		 6576 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6577 vcpu->arch.hflags |= HF_SMM_MASK;
6578 memset(buf, 0, 512);
6579 if (guest_cpuid_has_longmode(vcpu))
ee2cd4b7 6580 enter_smm_save_state_64(vcpu, buf);
660a5d51 6581 else
ee2cd4b7 6582 enter_smm_save_state_32(vcpu, buf);
660a5d51 6583
54bf36aa 6584 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6585
6586 if (kvm_x86_ops->get_nmi_mask(vcpu))
6587 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6588 else
6589 kvm_x86_ops->set_nmi_mask(vcpu, true);
6590
6591 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6592 kvm_rip_write(vcpu, 0x8000);
6593
6594 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6595 kvm_x86_ops->set_cr0(vcpu, cr0);
6596 vcpu->arch.cr0 = cr0;
6597
6598 kvm_x86_ops->set_cr4(vcpu, 0);
6599
18c3626e
PB		 6600 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6601 dt.address = dt.size = 0;
6602 kvm_x86_ops->set_idt(vcpu, &dt);
6603
660a5d51
PB		 6604 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6605
6606 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6607 cs.base = vcpu->arch.smbase;
6608
6609 ds.selector = 0;
6610 ds.base = 0;
6611
6612 cs.limit = ds.limit = 0xffffffff;
6613 cs.type = ds.type = 0x3;
6614 cs.dpl = ds.dpl = 0;
6615 cs.db = ds.db = 0;
6616 cs.s = ds.s = 1;
6617 cs.l = ds.l = 0;
6618 cs.g = ds.g = 1;
6619 cs.avl = ds.avl = 0;
6620 cs.present = ds.present = 1;
6621 cs.unusable = ds.unusable = 0;
6622 cs.padding = ds.padding = 0;
6623
6624 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6625 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6626 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6627 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6628 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6629 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6630
6631 if (guest_cpuid_has_longmode(vcpu))
6632 kvm_x86_ops->set_efer(vcpu, 0);
6633
6634 kvm_update_cpuid(vcpu);
6635 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6636}
6637
ee2cd4b7 6638static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6639{
6640 vcpu->arch.smi_pending = true;
6641 kvm_make_request(KVM_REQ_EVENT, vcpu);
6642}
6643
2860c4b1
PB		 6644void kvm_make_scan_ioapic_request(struct kvm *kvm)
6645{
6646 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6647}
6648
3d81bc7e 6649static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6650{
5c919412
AS		 6651 u64 eoi_exit_bitmap[4];
6652
3d81bc7e
YZ		 6653 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6654 return;
c7c9c56c 6655
6308630b 6656 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6657
b053b2ae 6658 if (irqchip_split(vcpu->kvm))
6308630b 6659 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6660 else {
76dfafd5 6661 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb 6662 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6663 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6664 }
5c919412
AS		 6665 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6666 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6667 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6668}
6669
a70656b6
RK		 6670static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6671{
6672 ++vcpu->stat.tlb_flush;
6673 kvm_x86_ops->tlb_flush(vcpu);
6674}
6675
4256f43f
TC		 6676void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6677{
c24ae0dc
TC		 6678 struct page *page = NULL;
6679
35754c98 6680 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6681 return;
6682
4256f43f
TC		 6683 if (!kvm_x86_ops->set_apic_access_page_addr)
6684 return;
6685
c24ae0dc 6686 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6687 if (is_error_page(page))
6688 return;
c24ae0dc
TC		 6689 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6690
6691 /*
6692 * Do not pin apic access page in memory, the MMU notifier
6693 * will call us again if it is migrated or swapped out.
6694 */
6695 put_page(page);
4256f43f
TC		 6696}
6697EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6698
fe71557a
TC		 6699void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6700 unsigned long address)
6701{
c24ae0dc
TC		 6702 /*
6703 * The physical address of apic access page is stored in the VMCS.
6704 * Update it when it becomes invalid.
6705 */
6706 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6707 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6708}
6709
9357d939 6710/*
362c698f 6711 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6712 * exiting to the userspace. Otherwise, the value will be returned to the
6713 * userspace.
6714 */
851ba692 6715static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6716{
6717 int r;
62a193ed
MG		 6718 bool req_int_win =
6719 dm_request_for_irq_injection(vcpu) &&
6720 kvm_cpu_accept_dm_intr(vcpu);
6721
730dca42 6722 bool req_immediate_exit = false;
b6c7a5dc 6723
3e007509 6724 if (vcpu->requests) {
a8eeb04a 6725 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6726 kvm_mmu_unload(vcpu);
a8eeb04a 6727 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6728 __kvm_migrate_timers(vcpu);
d828199e
MT		 6729 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6730 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6731 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6732 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6733 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6734 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6735 if (unlikely(r))
6736 goto out;
6737 }
a8eeb04a 6738 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6739 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6740 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6741 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6742 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6743 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6744 r = 0;
6745 goto out;
6746 }
a8eeb04a 6747 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6748 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6749 r = 0;
6750 goto out;
6751 }
af585b92
GN		 6752 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6753 /* Page is swapped out. Do synthetic halt */
6754 vcpu->arch.apf.halted = true;
6755 r = 1;
6756 goto out;
6757 }
c9aaa895
GC		 6758 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6759 record_steal_time(vcpu);
64d60670
PB		 6760 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6761 process_smi(vcpu);
7460fb4a
AK		 6762 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6763 process_nmi(vcpu);
f5132b01 6764 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6765 kvm_pmu_handle_event(vcpu);
f5132b01 6766 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6767 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6768 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6769 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6770 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6771 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6772 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6773 vcpu->run->eoi.vector =
6774 vcpu->arch.pending_ioapic_eoi;
6775 r = 0;
6776 goto out;
6777 }
6778 }
3d81bc7e
YZ		 6779 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6780 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6781 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6782 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6783 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6784 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6785 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6786 r = 0;
6787 goto out;
6788 }
e516cebb
AS		 6789 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6790 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6791 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6792 r = 0;
6793 goto out;
6794 }
db397571
AS		 6795 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6796 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6797 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6798 r = 0;
6799 goto out;
6800 }
f3b138c5
AS		 6801
6802 /*
6803 * KVM_REQ_HV_STIMER has to be processed after
6804 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6805 * depend on the guest clock being up-to-date
6806 */
1f4b34f8
AS		 6807 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6808 kvm_hv_process_stimers(vcpu);
2f52d58c 6809 }
b93463aa 6810
b463a6f7 6811 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 6812 ++vcpu->stat.req_event;
66450a21
JK		 6813 kvm_apic_accept_events(vcpu);
6814 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6815 r = 1;
6816 goto out;
6817 }
6818
b6b8a145
JK		 6819 if (inject_pending_event(vcpu, req_int_win) != 0)
6820 req_immediate_exit = true;
321c5658 6821 else {
c43203ca
PB		 6822 /* Enable NMI/IRQ window open exits if needed.
6823 *
6824 * SMIs have two cases: 1) they can be nested, and
6825 * then there is nothing to do here because RSM will
6826 * cause a vmexit anyway; 2) or the SMI can be pending
6827 * because inject_pending_event has completed the
6828 * injection of an IRQ or NMI from the previous vmexit,
6829 * and then we request an immediate exit to inject the SMI.
6830 */
6831 if (vcpu->arch.smi_pending && !is_smm(vcpu))
6832 req_immediate_exit = true;
321c5658
YS		 6833 if (vcpu->arch.nmi_pending)
6834 kvm_x86_ops->enable_nmi_window(vcpu);
6835 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6836 kvm_x86_ops->enable_irq_window(vcpu);
6837 }
b463a6f7
AK		 6838
6839 if (kvm_lapic_enabled(vcpu)) {
6840 update_cr8_intercept(vcpu);
6841 kvm_lapic_sync_to_vapic(vcpu);
6842 }
6843 }
6844
d8368af8
AK		 6845 r = kvm_mmu_reload(vcpu);
6846 if (unlikely(r)) {
d905c069 6847 goto cancel_injection;
d8368af8
AK		 6848 }
6849
b6c7a5dc
HB		 6850 preempt_disable();
6851
6852 kvm_x86_ops->prepare_guest_switch(vcpu);
bd7e5b08 6853 kvm_load_guest_fpu(vcpu);
b95234c8
PB		 6854
6855 /*
6856 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
6857 * IPI are then delayed after guest entry, which ensures that they
6858 * result in virtual interrupt delivery.
6859 */
6860 local_irq_disable();
6b7e2d09
XG		 6861 vcpu->mode = IN_GUEST_MODE;
6862
01b71917
MT		 6863 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6864
0f127d12 6865 /*
b95234c8
PB		 6866 * 1) We should set ->mode before checking ->requests. Please see
6867 * the comment in kvm_make_all_cpus_request.
6868 *
6869 * 2) For APICv, we should set ->mode before checking PIR.ON. This
6870 * pairs with the memory barrier implicit in pi_test_and_set_on
6871 * (see vmx_deliver_posted_interrupt).
6872 *
6873 * 3) This also orders the write to mode from any reads to the page
6874 * tables done while the VCPU is running. Please see the comment
6875 * in kvm_flush_remote_tlbs.
6b7e2d09 6876 */
01b71917 6877 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6878
b95234c8
PB		 6879 /*
6880 * This handles the case where a posted interrupt was
6881 * notified with kvm_vcpu_kick.
6882 */
6883 if (kvm_lapic_enabled(vcpu)) {
6884 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6885 kvm_x86_ops->sync_pir_to_irr(vcpu);
6886 }
32f88400 6887
6b7e2d09 6888 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6889 || need_resched() || signal_pending(current)) {
6b7e2d09 6890 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6891 smp_wmb();
6c142801
AK		 6892 local_irq_enable();
6893 preempt_enable();
01b71917 6894 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6895 r = 1;
d905c069 6896 goto cancel_injection;
6c142801
AK		 6897 }
6898
fc5b7f3b
DM		 6899 kvm_load_guest_xcr0(vcpu);
6900
c43203ca
PB		 6901 if (req_immediate_exit) {
6902 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 6903 smp_send_reschedule(vcpu->cpu);
c43203ca 6904 }
d6185f20 6905
8b89fe1f
PB		 6906 trace_kvm_entry(vcpu->vcpu_id);
6907 wait_lapic_expire(vcpu);
6edaa530 6908 guest_enter_irqoff();
b6c7a5dc 6909
42dbaa5a 6910 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6911 set_debugreg(0, 7);
6912 set_debugreg(vcpu->arch.eff_db[0], 0);
6913 set_debugreg(vcpu->arch.eff_db[1], 1);
6914 set_debugreg(vcpu->arch.eff_db[2], 2);
6915 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6916 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6917 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6918 }
b6c7a5dc 6919
851ba692 6920 kvm_x86_ops->run(vcpu);
b6c7a5dc 6921
c77fb5fe
PB		 6922 /*
6923 * Do this here before restoring debug registers on the host. And
6924 * since we do this before handling the vmexit, a DR access vmexit
6925 * can (a) read the correct value of the debug registers, (b) set
6926 * KVM_DEBUGREG_WONT_EXIT again.
6927 */
6928 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 6929 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6930 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 6931 kvm_update_dr0123(vcpu);
6932 kvm_update_dr6(vcpu);
6933 kvm_update_dr7(vcpu);
6934 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 6935 }
6936
24f1e32c
FW		 6937 /*
6938 * If the guest has used debug registers, at least dr7
6939 * will be disabled while returning to the host.
6940 * If we don't have active breakpoints in the host, we don't
6941 * care about the messed up debug address registers. But if
6942 * we have some of them active, restore the old state.
6943 */
59d8eb53 6944 if (hw_breakpoint_active())
24f1e32c 6945 hw_breakpoint_restore();
42dbaa5a 6946
4ba76538 6947 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6948
6b7e2d09 6949 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6950 smp_wmb();
a547c6db 6951
fc5b7f3b
DM		 6952 kvm_put_guest_xcr0(vcpu);
6953
a547c6db 6954 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6955
6956 ++vcpu->stat.exits;
6957
f2485b3e 6958 guest_exit_irqoff();
b6c7a5dc 6959
f2485b3e 6960 local_irq_enable();
b6c7a5dc
HB		 6961 preempt_enable();
6962
f656ce01 6963 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6964
b6c7a5dc
HB		 6965 /*
6966 * Profile KVM exit RIPs:
6967 */
6968 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6969 unsigned long rip = kvm_rip_read(vcpu);
6970 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6971 }
6972
cc578287
ZA		 6973 if (unlikely(vcpu->arch.tsc_always_catchup))
6974 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6975
5cfb1d5a
MT		 6976 if (vcpu->arch.apic_attention)
6977 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6978
851ba692 6979 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6980 return r;
6981
6982cancel_injection:
6983 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6984 if (unlikely(vcpu->arch.apic_attention))
6985 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6986out:
6987 return r;
6988}
b6c7a5dc 6989
362c698f
PB		 6990static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6991{
bf9f6ac8
FW		 6992 if (!kvm_arch_vcpu_runnable(vcpu) &&
6993 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6994 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6995 kvm_vcpu_block(vcpu);
6996 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6997
6998 if (kvm_x86_ops->post_block)
6999 kvm_x86_ops->post_block(vcpu);
7000
9c8fd1ba
PB		 7001 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7002 return 1;
7003 }
362c698f
PB		 7004
7005 kvm_apic_accept_events(vcpu);
7006 switch(vcpu->arch.mp_state) {
7007 case KVM_MP_STATE_HALTED:
7008 vcpu->arch.pv.pv_unhalted = false;
7009 vcpu->arch.mp_state =
7010 KVM_MP_STATE_RUNNABLE;
7011 case KVM_MP_STATE_RUNNABLE:
7012 vcpu->arch.apf.halted = false;
7013 break;
7014 case KVM_MP_STATE_INIT_RECEIVED:
7015 break;
7016 default:
7017 return -EINTR;
7018 break;
7019 }
7020 return 1;
7021}
09cec754 7022
5d9bc648
PB		 7023static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7024{
0ad3bed6
PB		 7025 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7026 kvm_x86_ops->check_nested_events(vcpu, false);
7027
5d9bc648
PB		 7028 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7029 !vcpu->arch.apf.halted);
7030}
7031
362c698f 7032static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7033{
7034 int r;
f656ce01 7035 struct kvm *kvm = vcpu->kvm;
d7690175 7036
f656ce01 7037 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7038
362c698f 7039 for (;;) {
58f800d5 7040 if (kvm_vcpu_running(vcpu)) {
851ba692 7041 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7042 } else {
362c698f 7043 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7044 }
7045
09cec754
GN		 7046 if (r <= 0)
7047 break;
7048
7049 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
7050 if (kvm_cpu_has_pending_timer(vcpu))
7051 kvm_inject_pending_timer_irqs(vcpu);
7052
782d422b
MG		 7053 if (dm_request_for_irq_injection(vcpu) &&
7054 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7055 r = 0;
7056 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7057 ++vcpu->stat.request_irq_exits;
362c698f 7058 break;
09cec754 7059 }
af585b92
GN		 7060
7061 kvm_check_async_pf_completion(vcpu);
7062
09cec754
GN		 7063 if (signal_pending(current)) {
7064 r = -EINTR;
851ba692 7065 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7066 ++vcpu->stat.signal_exits;
362c698f 7067 break;
09cec754
GN		 7068 }
7069 if (need_resched()) {
f656ce01 7070 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7071 cond_resched();
f656ce01 7072 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7073 }
b6c7a5dc
HB		 7074 }
7075
f656ce01 7076 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7077
7078 return r;
7079}
7080
716d51ab
GN		 7081static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7082{
7083 int r;
7084 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7085 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7086 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7087 if (r != EMULATE_DONE)
7088 return 0;
7089 return 1;
7090}
7091
7092static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7093{
7094 BUG_ON(!vcpu->arch.pio.count);
7095
7096 return complete_emulated_io(vcpu);
7097}
7098
f78146b0
AK		 7099/*
7100 * Implements the following, as a state machine:
7101 *
7102 * read:
7103 * for each fragment
87da7e66
XG		 7104 * for each mmio piece in the fragment
7105 * write gpa, len
7106 * exit
7107 * copy data
f78146b0
AK		 7108 * execute insn
7109 *
7110 * write:
7111 * for each fragment
87da7e66
XG		 7112 * for each mmio piece in the fragment
7113 * write gpa, len
7114 * copy data
7115 * exit
f78146b0 7116 */
716d51ab 7117static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7118{
7119 struct kvm_run *run = vcpu->run;
f78146b0 7120 struct kvm_mmio_fragment *frag;
87da7e66 7121 unsigned len;
5287f194 7122
716d51ab 7123 BUG_ON(!vcpu->mmio_needed);
5287f194 7124
716d51ab 7125 /* Complete previous fragment */
87da7e66
XG		 7126 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7127 len = min(8u, frag->len);
716d51ab 7128 if (!vcpu->mmio_is_write)
87da7e66
XG		 7129 memcpy(frag->data, run->mmio.data, len);
7130
7131 if (frag->len <= 8) {
7132 /* Switch to the next fragment. */
7133 frag++;
7134 vcpu->mmio_cur_fragment++;
7135 } else {
7136 /* Go forward to the next mmio piece. */
7137 frag->data += len;
7138 frag->gpa += len;
7139 frag->len -= len;
7140 }
7141
a08d3b3b 7142 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7143 vcpu->mmio_needed = 0;
0912c977
PB		 7144
7145 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7146 if (vcpu->mmio_is_write)
716d51ab
GN		 7147 return 1;
7148 vcpu->mmio_read_completed = 1;
7149 return complete_emulated_io(vcpu);
7150 }
87da7e66 7151
716d51ab
GN		 7152 run->exit_reason = KVM_EXIT_MMIO;
7153 run->mmio.phys_addr = frag->gpa;
7154 if (vcpu->mmio_is_write)
87da7e66
XG		 7155 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7156 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7157 run->mmio.is_write = vcpu->mmio_is_write;
7158 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7159 return 0;
5287f194
AK		 7160}
7161
716d51ab 7162
b6c7a5dc
HB		 7163int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7164{
c5bedc68 7165 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 7166 int r;
7167 sigset_t sigsaved;
7168
c4d72e2d 7169 fpu__activate_curr(fpu);
e5c30142 7170
ac9f6dc0
AK		 7171 if (vcpu->sigset_active)
7172 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
7173
a4535290 7174 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 7175 kvm_vcpu_block(vcpu);
66450a21 7176 kvm_apic_accept_events(vcpu);
d7690175 7177 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 7178 r = -EAGAIN;
7179 goto out;
b6c7a5dc
HB		 7180 }
7181
b6c7a5dc 7182 /* re-sync apic's tpr */
35754c98 7183 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7184 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7185 r = -EINVAL;
7186 goto out;
7187 }
7188 }
b6c7a5dc 7189
716d51ab
GN		 7190 if (unlikely(vcpu->arch.complete_userspace_io)) {
7191 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7192 vcpu->arch.complete_userspace_io = NULL;
7193 r = cui(vcpu);
7194 if (r <= 0)
7195 goto out;
7196 } else
7197 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7198
460df4c1
PB		 7199 if (kvm_run->immediate_exit)
7200 r = -EINTR;
7201 else
7202 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7203
7204out:
f1d86e46 7205 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 7206 if (vcpu->sigset_active)
7207 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
7208
b6c7a5dc
HB		 7209 return r;
7210}
7211
7212int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7213{
7ae441ea
GN		 7214 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7215 /*
7216 * We are here if userspace calls get_regs() in the middle of
7217 * instruction emulation. Registers state needs to be copied
4a969980 7218 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7219 * that usually, but some bad designed PV devices (vmware
7220 * backdoor interface) need this to work
7221 */
dd856efa 7222 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7223 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7224 }
5fdbf976
MT		 7225 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7226 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7227 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7228 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7229 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7230 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7231 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7232 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7233#ifdef CONFIG_X86_64
5fdbf976
MT		 7234 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7235 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7236 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7237 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7238 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7239 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7240 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7241 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7242#endif
7243
5fdbf976 7244 regs->rip = kvm_rip_read(vcpu);
91586a3b 7245 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7246
b6c7a5dc
HB		 7247 return 0;
7248}
7249
7250int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7251{
7ae441ea
GN		 7252 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7253 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7254
5fdbf976
MT		 7255 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7256 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7257 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7258 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7259 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7260 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7261 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7262 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7263#ifdef CONFIG_X86_64
5fdbf976
MT		 7264 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7265 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7266 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7267 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7268 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7269 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7270 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7271 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7272#endif
7273
5fdbf976 7274 kvm_rip_write(vcpu, regs->rip);
91586a3b 7275 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 7276
b4f14abd
JK		 7277 vcpu->arch.exception.pending = false;
7278
3842d135
AK		 7279 kvm_make_request(KVM_REQ_EVENT, vcpu);
7280
b6c7a5dc
HB		 7281 return 0;
7282}
7283
b6c7a5dc
HB		 7284void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7285{
7286 struct kvm_segment cs;
7287
3e6e0aab 7288 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7289 *db = cs.db;
7290 *l = cs.l;
7291}
7292EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7293
7294int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7295 struct kvm_sregs *sregs)
7296{
89a27f4d 7297 struct desc_ptr dt;
b6c7a5dc 7298
3e6e0aab
GT		 7299 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7300 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7301 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7302 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7303 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7304 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7305
3e6e0aab
GT		 7306 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7307 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7308
7309 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7310 sregs->idt.limit = dt.size;
7311 sregs->idt.base = dt.address;
b6c7a5dc 7312 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7313 sregs->gdt.limit = dt.size;
7314 sregs->gdt.base = dt.address;
b6c7a5dc 7315
4d4ec087 7316 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7317 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7318 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7319 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7320 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7321 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7322 sregs->apic_base = kvm_get_apic_base(vcpu);
7323
923c61bb 7324 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7325
36752c9b 7326 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7327 set_bit(vcpu->arch.interrupt.nr,
7328 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7329
b6c7a5dc
HB		 7330 return 0;
7331}
7332
62d9f0db
MT		 7333int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7334 struct kvm_mp_state *mp_state)
7335{
66450a21 7336 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7337 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7338 vcpu->arch.pv.pv_unhalted)
7339 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7340 else
7341 mp_state->mp_state = vcpu->arch.mp_state;
7342
62d9f0db
MT		 7343 return 0;
7344}
7345
7346int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7347 struct kvm_mp_state *mp_state)
7348{
bce87cce 7349 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7350 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7351 return -EINVAL;
7352
28bf2888
DH		 7353 /* INITs are latched while in SMM */
7354 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7355 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7356 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7357 return -EINVAL;
7358
66450a21
JK		 7359 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7360 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7361 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7362 } else
7363 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7364 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7365 return 0;
7366}
7367
7f3d35fd
KW		 7368int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7369 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7370{
9d74191a 7371 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7372 int ret;
e01c2426 7373
8ec4722d 7374 init_emulate_ctxt(vcpu);
c697518a 7375
7f3d35fd 7376 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7377 has_error_code, error_code);
c697518a 7378
c697518a 7379 if (ret)
19d04437 7380 return EMULATE_FAIL;
37817f29 7381
9d74191a
TY		 7382 kvm_rip_write(vcpu, ctxt->eip);
7383 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7384 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7385 return EMULATE_DONE;
37817f29
IE		 7386}
7387EXPORT_SYMBOL_GPL(kvm_task_switch);
7388
b6c7a5dc
HB		 7389int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7390 struct kvm_sregs *sregs)
7391{
58cb628d 7392 struct msr_data apic_base_msr;
b6c7a5dc 7393 int mmu_reset_needed = 0;
63f42e02 7394 int pending_vec, max_bits, idx;
89a27f4d 7395 struct desc_ptr dt;
b6c7a5dc 7396
6d1068b3
PM		 7397 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7398 return -EINVAL;
7399
89a27f4d
GN		 7400 dt.size = sregs->idt.limit;
7401 dt.address = sregs->idt.base;
b6c7a5dc 7402 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7403 dt.size = sregs->gdt.limit;
7404 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7405 kvm_x86_ops->set_gdt(vcpu, &dt);
7406
ad312c7c 7407 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7408 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7409 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7410 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7411
2d3ad1f4 7412 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7413
f6801dff 7414 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7415 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7416 apic_base_msr.data = sregs->apic_base;
7417 apic_base_msr.host_initiated = true;
7418 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7419
4d4ec087 7420 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7421 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7422 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7423
fc78f519 7424 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7425 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7426 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7427 kvm_update_cpuid(vcpu);
63f42e02
XG		 7428
7429 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7430 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7431 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7432 mmu_reset_needed = 1;
7433 }
63f42e02 7434 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7435
7436 if (mmu_reset_needed)
7437 kvm_mmu_reset_context(vcpu);
7438
a50abc3b 7439 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7440 pending_vec = find_first_bit(
7441 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7442 if (pending_vec < max_bits) {
66fd3f7f 7443 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7444 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7445 }
7446
3e6e0aab
GT		 7447 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7448 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7449 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7450 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7451 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7452 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7453
3e6e0aab
GT		 7454 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7455 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7456
5f0269f5
ME		 7457 update_cr8_intercept(vcpu);
7458
9c3e4aab 7459 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7460 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7461 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7462 !is_protmode(vcpu))
9c3e4aab
MT		 7463 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7464
3842d135
AK		 7465 kvm_make_request(KVM_REQ_EVENT, vcpu);
7466
b6c7a5dc
HB		 7467 return 0;
7468}
7469
d0bfb940
JK		 7470int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7471 struct kvm_guest_debug *dbg)
b6c7a5dc 7472{
355be0b9 7473 unsigned long rflags;
ae675ef0 7474 int i, r;
b6c7a5dc 7475
4f926bf2
JK		 7476 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7477 r = -EBUSY;
7478 if (vcpu->arch.exception.pending)
2122ff5e 7479 goto out;
4f926bf2
JK		 7480 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7481 kvm_queue_exception(vcpu, DB_VECTOR);
7482 else
7483 kvm_queue_exception(vcpu, BP_VECTOR);
7484 }
7485
91586a3b
JK		 7486 /*
7487 * Read rflags as long as potentially injected trace flags are still
7488 * filtered out.
7489 */
7490 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7491
7492 vcpu->guest_debug = dbg->control;
7493 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7494 vcpu->guest_debug = 0;
7495
7496 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7497 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7498 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7499 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7500 } else {
7501 for (i = 0; i < KVM_NR_DB_REGS; i++)
7502 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7503 }
c8639010 7504 kvm_update_dr7(vcpu);
ae675ef0 7505
f92653ee
JK		 7506 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7507 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7508 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7509
91586a3b
JK		 7510 /*
7511 * Trigger an rflags update that will inject or remove the trace
7512 * flags.
7513 */
7514 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7515
a96036b8 7516 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7517
4f926bf2 7518 r = 0;
d0bfb940 7519
2122ff5e 7520out:
b6c7a5dc
HB		 7521
7522 return r;
7523}
7524
8b006791
ZX		 7525/*
7526 * Translate a guest virtual address to a guest physical address.
7527 */
7528int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7529 struct kvm_translation *tr)
7530{
7531 unsigned long vaddr = tr->linear_address;
7532 gpa_t gpa;
f656ce01 7533 int idx;
8b006791 7534
f656ce01 7535 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7536 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7537 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7538 tr->physical_address = gpa;
7539 tr->valid = gpa != UNMAPPED_GVA;
7540 tr->writeable = 1;
7541 tr->usermode = 0;
8b006791
ZX		 7542
7543 return 0;
7544}
7545
d0752060
HB		 7546int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7547{
c47ada30 7548 struct fxregs_state *fxsave =
7366ed77 7549 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7550
d0752060
HB		 7551 memcpy(fpu->fpr, fxsave->st_space, 128);
7552 fpu->fcw = fxsave->cwd;
7553 fpu->fsw = fxsave->swd;
7554 fpu->ftwx = fxsave->twd;
7555 fpu->last_opcode = fxsave->fop;
7556 fpu->last_ip = fxsave->rip;
7557 fpu->last_dp = fxsave->rdp;
7558 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7559
d0752060
HB		 7560 return 0;
7561}
7562
7563int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7564{
c47ada30 7565 struct fxregs_state *fxsave =
7366ed77 7566 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7567
d0752060
HB		 7568 memcpy(fxsave->st_space, fpu->fpr, 128);
7569 fxsave->cwd = fpu->fcw;
7570 fxsave->swd = fpu->fsw;
7571 fxsave->twd = fpu->ftwx;
7572 fxsave->fop = fpu->last_opcode;
7573 fxsave->rip = fpu->last_ip;
7574 fxsave->rdp = fpu->last_dp;
7575 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7576
d0752060
HB		 7577 return 0;
7578}
7579
0ee6a517 7580static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7581{
bf935b0b 7582 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7583 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7584 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7585 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7586
2acf923e
DC		 7587 /*
7588 * Ensure guest xcr0 is valid for loading
7589 */
d91cab78 7590 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7591
ad312c7c 7592 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7593}
d0752060
HB		 7594
7595void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7596{
2608d7a1 7597 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7598 return;
7599
2acf923e
DC		 7600 /*
7601 * Restore all possible states in the guest,
7602 * and assume host would use all available bits.
7603 * Guest xcr0 would be loaded later.
7604 */
d0752060 7605 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7606 __kernel_fpu_begin();
003e2e8b 7607 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7608 trace_kvm_fpu(1);
d0752060 7609}
d0752060
HB		 7610
7611void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7612{
3d42de25 7613 if (!vcpu->guest_fpu_loaded)
d0752060
HB		 7614 return;
7615
7616 vcpu->guest_fpu_loaded = 0;
4f836347 7617 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7618 __kernel_fpu_end();
f096ed85 7619 ++vcpu->stat.fpu_reload;
0c04851c 7620 trace_kvm_fpu(0);
d0752060 7621}
e9b11c17
ZX		 7622
7623void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7624{
bd768e14
IY		 7625 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7626
12f9a48f 7627 kvmclock_reset(vcpu);
7f1ea208 7628
e9b11c17 7629 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 7630 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 7631}
7632
7633struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7634 unsigned int id)
7635{
c447e76b
LL		 7636 struct kvm_vcpu *vcpu;
7637
6755bae8
ZA		 7638 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7639 printk_once(KERN_WARNING
7640 "kvm: SMP vm created on host with unstable TSC; "
7641 "guest TSC will not be reliable\n");
c447e76b
LL		 7642
7643 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7644
c447e76b 7645 return vcpu;
26e5215f 7646}
e9b11c17 7647
26e5215f
AK		 7648int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7649{
7650 int r;
e9b11c17 7651
19efffa2 7652 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7653 r = vcpu_load(vcpu);
7654 if (r)
7655 return r;
d28bc9dd 7656 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7657 kvm_mmu_setup(vcpu);
e9b11c17 7658 vcpu_put(vcpu);
26e5215f 7659 return r;
e9b11c17
ZX		 7660}
7661
31928aa5 7662void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7663{
8fe8ab46 7664 struct msr_data msr;
332967a3 7665 struct kvm *kvm = vcpu->kvm;
42897d86 7666
31928aa5
DD		 7667 if (vcpu_load(vcpu))
7668 return;
8fe8ab46
WA		 7669 msr.data = 0x0;
7670 msr.index = MSR_IA32_TSC;
7671 msr.host_initiated = true;
7672 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7673 vcpu_put(vcpu);
7674
630994b3
MT		 7675 if (!kvmclock_periodic_sync)
7676 return;
7677
332967a3
AJ		 7678 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7679 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7680}
7681
d40ccc62 7682void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7683{
9fc77441 7684 int r;
344d9588
GN		 7685 vcpu->arch.apf.msr_val = 0;
7686
9fc77441
MT		 7687 r = vcpu_load(vcpu);
7688 BUG_ON(r);
e9b11c17
ZX		 7689 kvm_mmu_unload(vcpu);
7690 vcpu_put(vcpu);
7691
7692 kvm_x86_ops->vcpu_free(vcpu);
7693}
7694
d28bc9dd 7695void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7696{
e69fab5d
PB		 7697 vcpu->arch.hflags = 0;
7698
c43203ca 7699 vcpu->arch.smi_pending = 0;
7460fb4a
AK		 7700 atomic_set(&vcpu->arch.nmi_queued, 0);
7701 vcpu->arch.nmi_pending = 0;
448fa4a9 7702 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7703 kvm_clear_interrupt_queue(vcpu);
7704 kvm_clear_exception_queue(vcpu);
448fa4a9 7705
42dbaa5a 7706 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7707 kvm_update_dr0123(vcpu);
6f43ed01 7708 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7709 kvm_update_dr6(vcpu);
42dbaa5a 7710 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7711 kvm_update_dr7(vcpu);
42dbaa5a 7712
1119022c
NA		 7713 vcpu->arch.cr2 = 0;
7714
3842d135 7715 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7716 vcpu->arch.apf.msr_val = 0;
c9aaa895 7717 vcpu->arch.st.msr_val = 0;
3842d135 7718
12f9a48f
GC		 7719 kvmclock_reset(vcpu);
7720
af585b92
GN		 7721 kvm_clear_async_pf_completion_queue(vcpu);
7722 kvm_async_pf_hash_reset(vcpu);
7723 vcpu->arch.apf.halted = false;
3842d135 7724
64d60670 7725 if (!init_event) {
d28bc9dd 7726 kvm_pmu_reset(vcpu);
64d60670
PB		 7727 vcpu->arch.smbase = 0x30000;
7728 }
f5132b01 7729
66f7b72e
JS		 7730 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7731 vcpu->arch.regs_avail = ~0;
7732 vcpu->arch.regs_dirty = ~0;
7733
d28bc9dd 7734 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7735}
7736
2b4a273b 7737void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7738{
7739 struct kvm_segment cs;
7740
7741 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7742 cs.selector = vector << 8;
7743 cs.base = vector << 12;
7744 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7745 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7746}
7747
13a34e06 7748int kvm_arch_hardware_enable(void)
e9b11c17 7749{
ca84d1a2
ZA		 7750 struct kvm *kvm;
7751 struct kvm_vcpu *vcpu;
7752 int i;
0dd6a6ed
ZA		 7753 int ret;
7754 u64 local_tsc;
7755 u64 max_tsc = 0;
7756 bool stable, backwards_tsc = false;
18863bdd
AK		 7757
7758 kvm_shared_msr_cpu_online();
13a34e06 7759 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7760 if (ret != 0)
7761 return ret;
7762
4ea1636b 7763 local_tsc = rdtsc();
0dd6a6ed
ZA		 7764 stable = !check_tsc_unstable();
7765 list_for_each_entry(kvm, &vm_list, vm_list) {
7766 kvm_for_each_vcpu(i, vcpu, kvm) {
7767 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7768 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7769 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7770 backwards_tsc = true;
7771 if (vcpu->arch.last_host_tsc > max_tsc)
7772 max_tsc = vcpu->arch.last_host_tsc;
7773 }
7774 }
7775 }
7776
7777 /*
7778 * Sometimes, even reliable TSCs go backwards. This happens on
7779 * platforms that reset TSC during suspend or hibernate actions, but
7780 * maintain synchronization. We must compensate. Fortunately, we can
7781 * detect that condition here, which happens early in CPU bringup,
7782 * before any KVM threads can be running. Unfortunately, we can't
7783 * bring the TSCs fully up to date with real time, as we aren't yet far
7784 * enough into CPU bringup that we know how much real time has actually
108b249c 7785 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 7786 * variables that haven't been updated yet.
7787 *
7788 * So we simply find the maximum observed TSC above, then record the
7789 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7790 * the adjustment will be applied. Note that we accumulate
7791 * adjustments, in case multiple suspend cycles happen before some VCPU
7792 * gets a chance to run again. In the event that no KVM threads get a
7793 * chance to run, we will miss the entire elapsed period, as we'll have
7794 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7795 * loose cycle time. This isn't too big a deal, since the loss will be
7796 * uniform across all VCPUs (not to mention the scenario is extremely
7797 * unlikely). It is possible that a second hibernate recovery happens
7798 * much faster than a first, causing the observed TSC here to be
7799 * smaller; this would require additional padding adjustment, which is
7800 * why we set last_host_tsc to the local tsc observed here.
7801 *
7802 * N.B. - this code below runs only on platforms with reliable TSC,
7803 * as that is the only way backwards_tsc is set above. Also note
7804 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7805 * have the same delta_cyc adjustment applied if backwards_tsc
7806 * is detected. Note further, this adjustment is only done once,
7807 * as we reset last_host_tsc on all VCPUs to stop this from being
7808 * called multiple times (one for each physical CPU bringup).
7809 *
4a969980 7810 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7811 * will be compensated by the logic in vcpu_load, which sets the TSC to
7812 * catchup mode. This will catchup all VCPUs to real time, but cannot
7813 * guarantee that they stay in perfect synchronization.
7814 */
7815 if (backwards_tsc) {
7816 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7817 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7818 list_for_each_entry(kvm, &vm_list, vm_list) {
7819 kvm_for_each_vcpu(i, vcpu, kvm) {
7820 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7821 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7822 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7823 }
7824
7825 /*
7826 * We have to disable TSC offset matching.. if you were
7827 * booting a VM while issuing an S4 host suspend....
7828 * you may have some problem. Solving this issue is
7829 * left as an exercise to the reader.
7830 */
7831 kvm->arch.last_tsc_nsec = 0;
7832 kvm->arch.last_tsc_write = 0;
7833 }
7834
7835 }
7836 return 0;
e9b11c17
ZX		 7837}
7838
13a34e06 7839void kvm_arch_hardware_disable(void)
e9b11c17 7840{
13a34e06
RK		 7841 kvm_x86_ops->hardware_disable();
7842 drop_user_return_notifiers();
e9b11c17
ZX		 7843}
7844
7845int kvm_arch_hardware_setup(void)
7846{
9e9c3fe4
NA		 7847 int r;
7848
7849 r = kvm_x86_ops->hardware_setup();
7850 if (r != 0)
7851 return r;
7852
35181e86
HZ		 7853 if (kvm_has_tsc_control) {
7854 /*
7855 * Make sure the user can only configure tsc_khz values that
7856 * fit into a signed integer.
7857 * A min value is not calculated needed because it will always
7858 * be 1 on all machines.
7859 */
7860 u64 max = min(0x7fffffffULL,
7861 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7862 kvm_max_guest_tsc_khz = max;
7863
ad721883 7864 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7865 }
ad721883 7866
9e9c3fe4
NA		 7867 kvm_init_msr_list();
7868 return 0;
e9b11c17
ZX		 7869}
7870
7871void kvm_arch_hardware_unsetup(void)
7872{
7873 kvm_x86_ops->hardware_unsetup();
7874}
7875
7876void kvm_arch_check_processor_compat(void *rtn)
7877{
7878 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7879}
7880
7881bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7882{
7883 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7884}
7885EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7886
7887bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7888{
7889 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7890}
7891
54e9818f 7892struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 7893EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 7894
e9b11c17
ZX		 7895int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7896{
7897 struct page *page;
7898 struct kvm *kvm;
7899 int r;
7900
7901 BUG_ON(vcpu->kvm == NULL);
7902 kvm = vcpu->kvm;
7903
d62caabb 7904 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7905 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7906 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7907 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7908 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7909 else
a4535290 7910 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7911
7912 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7913 if (!page) {
7914 r = -ENOMEM;
7915 goto fail;
7916 }
ad312c7c 7917 vcpu->arch.pio_data = page_address(page);
e9b11c17 7918
cc578287 7919 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7920
e9b11c17
ZX		 7921 r = kvm_mmu_create(vcpu);
7922 if (r < 0)
7923 goto fail_free_pio_data;
7924
7925 if (irqchip_in_kernel(kvm)) {
7926 r = kvm_create_lapic(vcpu);
7927 if (r < 0)
7928 goto fail_mmu_destroy;
54e9818f
GN		 7929 } else
7930 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7931
890ca9ae
HY		 7932 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7933 GFP_KERNEL);
7934 if (!vcpu->arch.mce_banks) {
7935 r = -ENOMEM;
443c39bc 7936 goto fail_free_lapic;
890ca9ae
HY		 7937 }
7938 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7939
f1797359
WY		 7940 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7941 r = -ENOMEM;
f5f48ee1 7942 goto fail_free_mce_banks;
f1797359 7943 }
f5f48ee1 7944
0ee6a517 7945 fx_init(vcpu);
66f7b72e 7946
ba904635 7947 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7948 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7949
7950 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7951 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7952
5a4f55cd
EK		 7953 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7954
74545705
RK		 7955 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7956
af585b92 7957 kvm_async_pf_hash_reset(vcpu);
f5132b01 7958 kvm_pmu_init(vcpu);
af585b92 7959
1c1a9ce9
SR		 7960 vcpu->arch.pending_external_vector = -1;
7961
5c919412
AS		 7962 kvm_hv_vcpu_init(vcpu);
7963
e9b11c17 7964 return 0;
0ee6a517 7965
f5f48ee1
SY		 7966fail_free_mce_banks:
7967 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7968fail_free_lapic:
7969 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7970fail_mmu_destroy:
7971 kvm_mmu_destroy(vcpu);
7972fail_free_pio_data:
ad312c7c 7973 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7974fail:
7975 return r;
7976}
7977
7978void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7979{
f656ce01
MT		 7980 int idx;
7981
1f4b34f8 7982 kvm_hv_vcpu_uninit(vcpu);
f5132b01 7983 kvm_pmu_destroy(vcpu);
36cb93fd 7984 kfree(vcpu->arch.mce_banks);
e9b11c17 7985 kvm_free_lapic(vcpu);
f656ce01 7986 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7987 kvm_mmu_destroy(vcpu);
f656ce01 7988 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7989 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7990 if (!lapic_in_kernel(vcpu))
54e9818f 7991 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7992}
d19a9cd2 7993
e790d9ef
RK		 7994void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7995{
ae97a3b8 7996 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7997}
7998
e08b9637 7999int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8000{
e08b9637
CO		 8001 if (type)
8002 return -EINVAL;
8003
6ef768fa 8004 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8005 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8006 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8007 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8008 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8009
5550af4d
SY		 8010 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8011 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8012 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8013 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8014 &kvm->arch.irq_sources_bitmap);
5550af4d 8015
038f8c11 8016 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8017 mutex_init(&kvm->arch.apic_map_lock);
3f5ad8be 8018 mutex_init(&kvm->arch.hyperv.hv_lock);
d828199e
MT		 8019 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8020
108b249c 8021 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8022 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8023
7e44e449 8024 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8025 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8026
0eb05bf2 8027 kvm_page_track_init(kvm);
13d268ca 8028 kvm_mmu_init_vm(kvm);
0eb05bf2 8029
03543133
SS		 8030 if (kvm_x86_ops->vm_init)
8031 return kvm_x86_ops->vm_init(kvm);
8032
d89f5eff 8033 return 0;
d19a9cd2
ZX		 8034}
8035
8036static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8037{
9fc77441
MT		 8038 int r;
8039 r = vcpu_load(vcpu);
8040 BUG_ON(r);
d19a9cd2
ZX		 8041 kvm_mmu_unload(vcpu);
8042 vcpu_put(vcpu);
8043}
8044
8045static void kvm_free_vcpus(struct kvm *kvm)
8046{
8047 unsigned int i;
988a2cae 8048 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8049
8050 /*
8051 * Unpin any mmu pages first.
8052 */
af585b92
GN		 8053 kvm_for_each_vcpu(i, vcpu, kvm) {
8054 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8055 kvm_unload_vcpu_mmu(vcpu);
af585b92 8056 }
988a2cae
GN		 8057 kvm_for_each_vcpu(i, vcpu, kvm)
8058 kvm_arch_vcpu_free(vcpu);
8059
8060 mutex_lock(&kvm->lock);
8061 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8062 kvm->vcpus[i] = NULL;
d19a9cd2 8063
988a2cae
GN		 8064 atomic_set(&kvm->online_vcpus, 0);
8065 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8066}
8067
ad8ba2cd
SY		 8068void kvm_arch_sync_events(struct kvm *kvm)
8069{
332967a3 8070 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8071 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8072 kvm_free_pit(kvm);
ad8ba2cd
SY		 8073}
8074
1d8007bd 8075int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8076{
8077 int i, r;
25188b99 8078 unsigned long hva;
f0d648bd
PB		 8079 struct kvm_memslots *slots = kvm_memslots(kvm);
8080 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8081
8082 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8083 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8084 return -EINVAL;
9da0e4d5 8085
f0d648bd
PB		 8086 slot = id_to_memslot(slots, id);
8087 if (size) {
b21629da 8088 if (slot->npages)
f0d648bd
PB		 8089 return -EEXIST;
8090
8091 /*
8092 * MAP_SHARED to prevent internal slot pages from being moved
8093 * by fork()/COW.
8094 */
8095 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8096 MAP_SHARED | MAP_ANONYMOUS, 0);
8097 if (IS_ERR((void *)hva))
8098 return PTR_ERR((void *)hva);
8099 } else {
8100 if (!slot->npages)
8101 return 0;
8102
8103 hva = 0;
8104 }
8105
8106 old = *slot;
9da0e4d5 8107 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8108 struct kvm_userspace_memory_region m;
9da0e4d5 8109
1d8007bd
PB		 8110 m.slot = id | (i << 16);
8111 m.flags = 0;
8112 m.guest_phys_addr = gpa;
f0d648bd 8113 m.userspace_addr = hva;
1d8007bd 8114 m.memory_size = size;
9da0e4d5
PB		 8115 r = __kvm_set_memory_region(kvm, &m);
8116 if (r < 0)
8117 return r;
8118 }
8119
f0d648bd
PB		 8120 if (!size) {
8121 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8122 WARN_ON(r < 0);
8123 }
8124
9da0e4d5
PB		 8125 return 0;
8126}
8127EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8128
1d8007bd 8129int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8130{
8131 int r;
8132
8133 mutex_lock(&kvm->slots_lock);
1d8007bd 8134 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8135 mutex_unlock(&kvm->slots_lock);
8136
8137 return r;
8138}
8139EXPORT_SYMBOL_GPL(x86_set_memory_region);
8140
d19a9cd2
ZX		 8141void kvm_arch_destroy_vm(struct kvm *kvm)
8142{
27469d29
AH		 8143 if (current->mm == kvm->mm) {
8144 /*
8145 * Free memory regions allocated on behalf of userspace,
8146 * unless the the memory map has changed due to process exit
8147 * or fd copying.
8148 */
1d8007bd
PB		 8149 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8150 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8151 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8152 }
03543133
SS		 8153 if (kvm_x86_ops->vm_destroy)
8154 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8155 kvm_pic_destroy(kvm);
8156 kvm_ioapic_destroy(kvm);
d19a9cd2 8157 kvm_free_vcpus(kvm);
af1bae54 8158 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8159 kvm_mmu_uninit_vm(kvm);
2beb6dad 8160 kvm_page_track_cleanup(kvm);
d19a9cd2 8161}
0de10343 8162
5587027c 8163void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8164 struct kvm_memory_slot *dont)
8165{
8166 int i;
8167
d89cc617
TY		 8168 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8169 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8170 kvfree(free->arch.rmap[i]);
d89cc617 8171 free->arch.rmap[i] = NULL;
77d11309 8172 }
d89cc617
TY		 8173 if (i == 0)
8174 continue;
8175
8176 if (!dont || free->arch.lpage_info[i - 1] !=
8177 dont->arch.lpage_info[i - 1]) {
548ef284 8178 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8179 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8180 }
8181 }
21ebbeda
XG		 8182
8183 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8184}
8185
5587027c
AK		 8186int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8187 unsigned long npages)
db3fe4eb
TY		 8188{
8189 int i;
8190
d89cc617 8191 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8192 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8193 unsigned long ugfn;
8194 int lpages;
d89cc617 8195 int level = i + 1;
db3fe4eb
TY		 8196
8197 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8198 slot->base_gfn, level) + 1;
8199
d89cc617
TY		 8200 slot->arch.rmap[i] =
8201 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
8202 if (!slot->arch.rmap[i])
77d11309 8203 goto out_free;
d89cc617
TY		 8204 if (i == 0)
8205 continue;
77d11309 8206
92f94f1e
XG		 8207 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
8208 if (!linfo)
db3fe4eb
TY		 8209 goto out_free;
8210
92f94f1e
XG		 8211 slot->arch.lpage_info[i - 1] = linfo;
8212
db3fe4eb 8213 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8214 linfo[0].disallow_lpage = 1;
db3fe4eb 8215 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8216 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8217 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8218 /*
8219 * If the gfn and userspace address are not aligned wrt each
8220 * other, or if explicitly asked to, disable large page
8221 * support for this slot
8222 */
8223 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8224 !kvm_largepages_enabled()) {
8225 unsigned long j;
8226
8227 for (j = 0; j < lpages; ++j)
92f94f1e 8228 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8229 }
8230 }
8231
21ebbeda
XG		 8232 if (kvm_page_track_create_memslot(slot, npages))
8233 goto out_free;
8234
db3fe4eb
TY		 8235 return 0;
8236
8237out_free:
d89cc617 8238 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8239 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8240 slot->arch.rmap[i] = NULL;
8241 if (i == 0)
8242 continue;
8243
548ef284 8244 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8245 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8246 }
8247 return -ENOMEM;
8248}
8249
15f46015 8250void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8251{
e6dff7d1
TY		 8252 /*
8253 * memslots->generation has been incremented.
8254 * mmio generation may have reached its maximum value.
8255 */
54bf36aa 8256 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8257}
8258
f7784b8e
MT		 8259int kvm_arch_prepare_memory_region(struct kvm *kvm,
8260 struct kvm_memory_slot *memslot,
09170a49 8261 const struct kvm_userspace_memory_region *mem,
7b6195a9 8262 enum kvm_mr_change change)
0de10343 8263{
f7784b8e
MT		 8264 return 0;
8265}
8266
88178fd4
KH		 8267static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8268 struct kvm_memory_slot *new)
8269{
8270 /* Still write protect RO slot */
8271 if (new->flags & KVM_MEM_READONLY) {
8272 kvm_mmu_slot_remove_write_access(kvm, new);
8273 return;
8274 }
8275
8276 /*
8277 * Call kvm_x86_ops dirty logging hooks when they are valid.
8278 *
8279 * kvm_x86_ops->slot_disable_log_dirty is called when:
8280 *
8281 * - KVM_MR_CREATE with dirty logging is disabled
8282 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8283 *
8284 * The reason is, in case of PML, we need to set D-bit for any slots
8285 * with dirty logging disabled in order to eliminate unnecessary GPA
8286 * logging in PML buffer (and potential PML buffer full VMEXT). This
8287 * guarantees leaving PML enabled during guest's lifetime won't have
8288 * any additonal overhead from PML when guest is running with dirty
8289 * logging disabled for memory slots.
8290 *
8291 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8292 * to dirty logging mode.
8293 *
8294 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8295 *
8296 * In case of write protect:
8297 *
8298 * Write protect all pages for dirty logging.
8299 *
8300 * All the sptes including the large sptes which point to this
8301 * slot are set to readonly. We can not create any new large
8302 * spte on this slot until the end of the logging.
8303 *
8304 * See the comments in fast_page_fault().
8305 */
8306 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8307 if (kvm_x86_ops->slot_enable_log_dirty)
8308 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8309 else
8310 kvm_mmu_slot_remove_write_access(kvm, new);
8311 } else {
8312 if (kvm_x86_ops->slot_disable_log_dirty)
8313 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8314 }
8315}
8316
f7784b8e 8317void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8318 const struct kvm_userspace_memory_region *mem,
8482644a 8319 const struct kvm_memory_slot *old,
f36f3f28 8320 const struct kvm_memory_slot *new,
8482644a 8321 enum kvm_mr_change change)
f7784b8e 8322{
8482644a 8323 int nr_mmu_pages = 0;
f7784b8e 8324
48c0e4e9
XG		 8325 if (!kvm->arch.n_requested_mmu_pages)
8326 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8327
48c0e4e9 8328 if (nr_mmu_pages)
0de10343 8329 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8330
3ea3b7fa
WL		 8331 /*
8332 * Dirty logging tracks sptes in 4k granularity, meaning that large
8333 * sptes have to be split. If live migration is successful, the guest
8334 * in the source machine will be destroyed and large sptes will be
8335 * created in the destination. However, if the guest continues to run
8336 * in the source machine (for example if live migration fails), small
8337 * sptes will remain around and cause bad performance.
8338 *
8339 * Scan sptes if dirty logging has been stopped, dropping those
8340 * which can be collapsed into a single large-page spte. Later
8341 * page faults will create the large-page sptes.
8342 */
8343 if ((change != KVM_MR_DELETE) &&
8344 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8345 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8346 kvm_mmu_zap_collapsible_sptes(kvm, new);
8347
c972f3b1 8348 /*
88178fd4 8349 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8350 *
88178fd4
KH		 8351 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8352 * been zapped so no dirty logging staff is needed for old slot. For
8353 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8354 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8355 *
8356 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8357 */
88178fd4 8358 if (change != KVM_MR_DELETE)
f36f3f28 8359 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8360}
1d737c8a 8361
2df72e9b 8362void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8363{
6ca18b69 8364 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8365}
8366
2df72e9b
MT		 8367void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8368 struct kvm_memory_slot *slot)
8369{
ae7cd873 8370 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8371}
8372
5d9bc648
PB		 8373static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8374{
8375 if (!list_empty_careful(&vcpu->async_pf.done))
8376 return true;
8377
8378 if (kvm_apic_has_events(vcpu))
8379 return true;
8380
8381 if (vcpu->arch.pv.pv_unhalted)
8382 return true;
8383
8384 if (atomic_read(&vcpu->arch.nmi_queued))
8385 return true;
8386
73917739
PB		 8387 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8388 return true;
8389
5d9bc648
PB		 8390 if (kvm_arch_interrupt_allowed(vcpu) &&
8391 kvm_cpu_has_interrupt(vcpu))
8392 return true;
8393
1f4b34f8
AS		 8394 if (kvm_hv_has_stimer_pending(vcpu))
8395 return true;
8396
5d9bc648
PB		 8397 return false;
8398}
8399
1d737c8a
ZX		 8400int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8401{
5d9bc648 8402 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8403}
5736199a 8404
b6d33834 8405int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8406{
b6d33834 8407 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8408}
78646121
GN		 8409
8410int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8411{
8412 return kvm_x86_ops->interrupt_allowed(vcpu);
8413}
229456fc 8414
82b32774 8415unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8416{
82b32774
NA		 8417 if (is_64_bit_mode(vcpu))
8418 return kvm_rip_read(vcpu);
8419 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8420 kvm_rip_read(vcpu));
8421}
8422EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8423
82b32774
NA		 8424bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8425{
8426 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8427}
8428EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8429
94fe45da
JK		 8430unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8431{
8432 unsigned long rflags;
8433
8434 rflags = kvm_x86_ops->get_rflags(vcpu);
8435 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8436 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8437 return rflags;
8438}
8439EXPORT_SYMBOL_GPL(kvm_get_rflags);
8440
6addfc42 8441static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8442{
8443 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8444 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8445 rflags |= X86_EFLAGS_TF;
94fe45da 8446 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8447}
8448
8449void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8450{
8451 __kvm_set_rflags(vcpu, rflags);
3842d135 8452 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8453}
8454EXPORT_SYMBOL_GPL(kvm_set_rflags);
8455
56028d08
GN		 8456void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8457{
8458 int r;
8459
fb67e14f 8460 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8461 work->wakeup_all)
56028d08
GN		 8462 return;
8463
8464 r = kvm_mmu_reload(vcpu);
8465 if (unlikely(r))
8466 return;
8467
fb67e14f
XG		 8468 if (!vcpu->arch.mmu.direct_map &&
8469 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8470 return;
8471
56028d08
GN		 8472 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8473}
8474
af585b92
GN		 8475static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8476{
8477 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8478}
8479
8480static inline u32 kvm_async_pf_next_probe(u32 key)
8481{
8482 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8483}
8484
8485static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8486{
8487 u32 key = kvm_async_pf_hash_fn(gfn);
8488
8489 while (vcpu->arch.apf.gfns[key] != ~0)
8490 key = kvm_async_pf_next_probe(key);
8491
8492 vcpu->arch.apf.gfns[key] = gfn;
8493}
8494
8495static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8496{
8497 int i;
8498 u32 key = kvm_async_pf_hash_fn(gfn);
8499
8500 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8501 (vcpu->arch.apf.gfns[key] != gfn &&
8502 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8503 key = kvm_async_pf_next_probe(key);
8504
8505 return key;
8506}
8507
8508bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8509{
8510 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8511}
8512
8513static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8514{
8515 u32 i, j, k;
8516
8517 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8518 while (true) {
8519 vcpu->arch.apf.gfns[i] = ~0;
8520 do {
8521 j = kvm_async_pf_next_probe(j);
8522 if (vcpu->arch.apf.gfns[j] == ~0)
8523 return;
8524 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8525 /*
8526 * k lies cyclically in ]i,j]
8527 * | i.k.j |
8528 * |....j i.k.| or |.k..j i...|
8529 */
8530 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8531 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8532 i = j;
8533 }
8534}
8535
7c90705b
GN		 8536static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8537{
bbd64115
CL		 8538 return kvm_vcpu_write_guest_cached(vcpu, &vcpu->arch.apf.data, &val,
8539 sizeof(val));
7c90705b
GN		 8540}
8541
af585b92
GN		 8542void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8543 struct kvm_async_pf *work)
8544{
6389ee94
AK		 8545 struct x86_exception fault;
8546
7c90705b 8547 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8548 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8549
8550 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8551 (vcpu->arch.apf.send_user_only &&
8552 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8553 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8554 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8555 fault.vector = PF_VECTOR;
8556 fault.error_code_valid = true;
8557 fault.error_code = 0;
8558 fault.nested_page_fault = false;
8559 fault.address = work->arch.token;
8560 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8561 }
af585b92
GN		 8562}
8563
8564void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8565 struct kvm_async_pf *work)
8566{
6389ee94
AK		 8567 struct x86_exception fault;
8568
f2e10669 8569 if (work->wakeup_all)
7c90705b
GN		 8570 work->arch.token = ~0; /* broadcast wakeup */
8571 else
8572 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 8573 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b
GN		 8574
8575 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8576 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8577 fault.vector = PF_VECTOR;
8578 fault.error_code_valid = true;
8579 fault.error_code = 0;
8580 fault.nested_page_fault = false;
8581 fault.address = work->arch.token;
8582 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8583 }
e6d53e3b 8584 vcpu->arch.apf.halted = false;
a4fa1635 8585 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8586}
8587
8588bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8589{
8590 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8591 return true;
8592 else
8593 return !kvm_event_needs_reinjection(vcpu) &&
8594 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8595}
8596
5544eb9b
PB		 8597void kvm_arch_start_assignment(struct kvm *kvm)
8598{
8599 atomic_inc(&kvm->arch.assigned_device_count);
8600}
8601EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8602
8603void kvm_arch_end_assignment(struct kvm *kvm)
8604{
8605 atomic_dec(&kvm->arch.assigned_device_count);
8606}
8607EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8608
8609bool kvm_arch_has_assigned_device(struct kvm *kvm)
8610{
8611 return atomic_read(&kvm->arch.assigned_device_count);
8612}
8613EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8614
e0f0bbc5
AW		 8615void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8616{
8617 atomic_inc(&kvm->arch.noncoherent_dma_count);
8618}
8619EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8620
8621void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8622{
8623 atomic_dec(&kvm->arch.noncoherent_dma_count);
8624}
8625EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8626
8627bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8628{
8629 return atomic_read(&kvm->arch.noncoherent_dma_count);
8630}
8631EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8632
14717e20
AW		 8633bool kvm_arch_has_irq_bypass(void)
8634{
8635 return kvm_x86_ops->update_pi_irte != NULL;
8636}
8637
87276880
FW		 8638int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8639 struct irq_bypass_producer *prod)
8640{
8641 struct kvm_kernel_irqfd *irqfd =
8642 container_of(cons, struct kvm_kernel_irqfd, consumer);
8643
14717e20 8644 irqfd->producer = prod;
87276880 8645
14717e20
AW		 8646 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8647 prod->irq, irqfd->gsi, 1);
87276880
FW		 8648}
8649
8650void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8651 struct irq_bypass_producer *prod)
8652{
8653 int ret;
8654 struct kvm_kernel_irqfd *irqfd =
8655 container_of(cons, struct kvm_kernel_irqfd, consumer);
8656
87276880
FW		 8657 WARN_ON(irqfd->producer != prod);
8658 irqfd->producer = NULL;
8659
8660 /*
8661 * When producer of consumer is unregistered, we change back to
8662 * remapped mode, so we can re-use the current implementation
bb3541f1 8663 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8664 * int this case doesn't want to receive the interrupts.
8665 */
8666 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8667 if (ret)
8668 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8669 " fails: %d\n", irqfd->consumer.token, ret);
8670}
8671
8672int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8673 uint32_t guest_irq, bool set)
8674{
8675 if (!kvm_x86_ops->update_pi_irte)
8676 return -EINVAL;
8677
8678 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8679}
8680
52004014
FW		 8681bool kvm_vector_hashing_enabled(void)
8682{
8683 return vector_hashing;
8684}
8685EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8686
229456fc 8687EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8688EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8689EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8690EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8691EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8692EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8693EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8694EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8695EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8696EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8697EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8698EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8699EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8700EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8701EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8702EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8703EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8704EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8705EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
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