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20c8ccb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
043405e1 CO |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * | |
5 | * derived from drivers/kvm/kvm_main.c | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
8 | * Copyright (C) 2008 Qumranet, Inc. |
9 | * Copyright IBM Corporation, 2008 | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
043405e1 CO |
11 | * |
12 | * Authors: | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
15 | * Amit Shah <amit.shah@qumranet.com> |
16 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
17 | */ |
18 | ||
edf88417 | 19 | #include <linux/kvm_host.h> |
313a3dc7 | 20 | #include "irq.h" |
88197e6a | 21 | #include "ioapic.h" |
1d737c8a | 22 | #include "mmu.h" |
7837699f | 23 | #include "i8254.h" |
37817f29 | 24 | #include "tss.h" |
5fdbf976 | 25 | #include "kvm_cache_regs.h" |
2f728d66 | 26 | #include "kvm_emulate.h" |
26eef70c | 27 | #include "x86.h" |
00b27a3e | 28 | #include "cpuid.h" |
474a5bb9 | 29 | #include "pmu.h" |
e83d5887 | 30 | #include "hyperv.h" |
8df14af4 | 31 | #include "lapic.h" |
313a3dc7 | 32 | |
18068523 | 33 | #include <linux/clocksource.h> |
4d5c5d0f | 34 | #include <linux/interrupt.h> |
313a3dc7 CO |
35 | #include <linux/kvm.h> |
36 | #include <linux/fs.h> | |
37 | #include <linux/vmalloc.h> | |
1767e931 PG |
38 | #include <linux/export.h> |
39 | #include <linux/moduleparam.h> | |
0de10343 | 40 | #include <linux/mman.h> |
2bacc55c | 41 | #include <linux/highmem.h> |
19de40a8 | 42 | #include <linux/iommu.h> |
62c476c7 | 43 | #include <linux/intel-iommu.h> |
c8076604 | 44 | #include <linux/cpufreq.h> |
18863bdd | 45 | #include <linux/user-return-notifier.h> |
a983fb23 | 46 | #include <linux/srcu.h> |
5a0e3ad6 | 47 | #include <linux/slab.h> |
ff9d07a0 | 48 | #include <linux/perf_event.h> |
7bee342a | 49 | #include <linux/uaccess.h> |
af585b92 | 50 | #include <linux/hash.h> |
a1b60c1c | 51 | #include <linux/pci.h> |
16e8d74d MT |
52 | #include <linux/timekeeper_internal.h> |
53 | #include <linux/pvclock_gtod.h> | |
87276880 FW |
54 | #include <linux/kvm_irqfd.h> |
55 | #include <linux/irqbypass.h> | |
3905f9ad | 56 | #include <linux/sched/stat.h> |
0c5f81da | 57 | #include <linux/sched/isolation.h> |
d0ec49d4 | 58 | #include <linux/mem_encrypt.h> |
72c3c0fe | 59 | #include <linux/entry-kvm.h> |
3905f9ad | 60 | |
aec51dc4 | 61 | #include <trace/events/kvm.h> |
2ed152af | 62 | |
24f1e32c | 63 | #include <asm/debugreg.h> |
d825ed0a | 64 | #include <asm/msr.h> |
a5f61300 | 65 | #include <asm/desc.h> |
890ca9ae | 66 | #include <asm/mce.h> |
f89e32e0 | 67 | #include <linux/kernel_stat.h> |
78f7f1e5 | 68 | #include <asm/fpu/internal.h> /* Ugh! */ |
1d5f066e | 69 | #include <asm/pvclock.h> |
217fc9cf | 70 | #include <asm/div64.h> |
efc64404 | 71 | #include <asm/irq_remapping.h> |
b0c39dc6 | 72 | #include <asm/mshyperv.h> |
0092e434 | 73 | #include <asm/hypervisor.h> |
9715092f | 74 | #include <asm/tlbflush.h> |
bf8c55d8 | 75 | #include <asm/intel_pt.h> |
b3dc0695 | 76 | #include <asm/emulate_prefix.h> |
dd2cb348 | 77 | #include <clocksource/hyperv_timer.h> |
043405e1 | 78 | |
d1898b73 DH |
79 | #define CREATE_TRACE_POINTS |
80 | #include "trace.h" | |
81 | ||
313a3dc7 | 82 | #define MAX_IO_MSRS 256 |
890ca9ae | 83 | #define KVM_MAX_MCE_BANKS 32 |
c45dcc71 AR |
84 | u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; |
85 | EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); | |
890ca9ae | 86 | |
0f65dd70 | 87 | #define emul_to_vcpu(ctxt) \ |
c9b8b07c | 88 | ((struct kvm_vcpu *)(ctxt)->vcpu) |
0f65dd70 | 89 | |
50a37eb4 JR |
90 | /* EFER defaults: |
91 | * - enable syscall per default because its emulated by KVM | |
92 | * - enable LME and LMA per default on 64 bit KVM | |
93 | */ | |
94 | #ifdef CONFIG_X86_64 | |
1260edbe LJ |
95 | static |
96 | u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); | |
50a37eb4 | 97 | #else |
1260edbe | 98 | static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); |
50a37eb4 | 99 | #endif |
313a3dc7 | 100 | |
b11306b5 SC |
101 | static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; |
102 | ||
c519265f RK |
103 | #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ |
104 | KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) | |
37131313 | 105 | |
cb142eb7 | 106 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
7460fb4a | 107 | static void process_nmi(struct kvm_vcpu *vcpu); |
1f7becf1 | 108 | static void process_smi(struct kvm_vcpu *vcpu); |
ee2cd4b7 | 109 | static void enter_smm(struct kvm_vcpu *vcpu); |
6addfc42 | 110 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); |
01643c51 KH |
111 | static void store_regs(struct kvm_vcpu *vcpu); |
112 | static int sync_regs(struct kvm_vcpu *vcpu); | |
674eea0f | 113 | |
afaf0b2f | 114 | struct kvm_x86_ops kvm_x86_ops __read_mostly; |
5fdbf976 | 115 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 116 | |
9af5471b JB |
117 | #define KVM_X86_OP(func) \ |
118 | DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \ | |
119 | *(((struct kvm_x86_ops *)0)->func)); | |
120 | #define KVM_X86_OP_NULL KVM_X86_OP | |
121 | #include <asm/kvm-x86-ops.h> | |
122 | EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits); | |
123 | EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg); | |
124 | EXPORT_STATIC_CALL_GPL(kvm_x86_tlb_flush_current); | |
125 | ||
893590c7 | 126 | static bool __read_mostly ignore_msrs = 0; |
476bc001 | 127 | module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); |
ed85c068 | 128 | |
d855066f | 129 | bool __read_mostly report_ignored_msrs = true; |
fab0aa3b | 130 | module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); |
d855066f | 131 | EXPORT_SYMBOL_GPL(report_ignored_msrs); |
fab0aa3b | 132 | |
4c27625b | 133 | unsigned int min_timer_period_us = 200; |
9ed96e87 MT |
134 | module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); |
135 | ||
630994b3 MT |
136 | static bool __read_mostly kvmclock_periodic_sync = true; |
137 | module_param(kvmclock_periodic_sync, bool, S_IRUGO); | |
138 | ||
893590c7 | 139 | bool __read_mostly kvm_has_tsc_control; |
92a1f12d | 140 | EXPORT_SYMBOL_GPL(kvm_has_tsc_control); |
893590c7 | 141 | u32 __read_mostly kvm_max_guest_tsc_khz; |
92a1f12d | 142 | EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); |
bc9b961b HZ |
143 | u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; |
144 | EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); | |
145 | u64 __read_mostly kvm_max_tsc_scaling_ratio; | |
146 | EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); | |
64672c95 YJ |
147 | u64 __read_mostly kvm_default_tsc_scaling_ratio; |
148 | EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); | |
fe6b6bc8 CQ |
149 | bool __read_mostly kvm_has_bus_lock_exit; |
150 | EXPORT_SYMBOL_GPL(kvm_has_bus_lock_exit); | |
92a1f12d | 151 | |
cc578287 | 152 | /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ |
893590c7 | 153 | static u32 __read_mostly tsc_tolerance_ppm = 250; |
cc578287 ZA |
154 | module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); |
155 | ||
c3941d9e SC |
156 | /* |
157 | * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables | |
158 | * adaptive tuning starting from default advancment of 1000ns. '0' disables | |
159 | * advancement entirely. Any other value is used as-is and disables adaptive | |
160 | * tuning, i.e. allows priveleged userspace to set an exact advancement time. | |
161 | */ | |
162 | static int __read_mostly lapic_timer_advance_ns = -1; | |
0e6edceb | 163 | module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR); |
d0659d94 | 164 | |
52004014 FW |
165 | static bool __read_mostly vector_hashing = true; |
166 | module_param(vector_hashing, bool, S_IRUGO); | |
167 | ||
c4ae60e4 LA |
168 | bool __read_mostly enable_vmware_backdoor = false; |
169 | module_param(enable_vmware_backdoor, bool, S_IRUGO); | |
170 | EXPORT_SYMBOL_GPL(enable_vmware_backdoor); | |
171 | ||
6c86eedc WL |
172 | static bool __read_mostly force_emulation_prefix = false; |
173 | module_param(force_emulation_prefix, bool, S_IRUGO); | |
174 | ||
0c5f81da WL |
175 | int __read_mostly pi_inject_timer = -1; |
176 | module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); | |
177 | ||
7e34fbd0 SC |
178 | /* |
179 | * Restoring the host value for MSRs that are only consumed when running in | |
180 | * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU | |
181 | * returns to userspace, i.e. the kernel can run with the guest's value. | |
182 | */ | |
183 | #define KVM_MAX_NR_USER_RETURN_MSRS 16 | |
18863bdd | 184 | |
7e34fbd0 | 185 | struct kvm_user_return_msrs_global { |
18863bdd | 186 | int nr; |
7e34fbd0 | 187 | u32 msrs[KVM_MAX_NR_USER_RETURN_MSRS]; |
18863bdd AK |
188 | }; |
189 | ||
7e34fbd0 | 190 | struct kvm_user_return_msrs { |
18863bdd AK |
191 | struct user_return_notifier urn; |
192 | bool registered; | |
7e34fbd0 | 193 | struct kvm_user_return_msr_values { |
2bf78fa7 SY |
194 | u64 host; |
195 | u64 curr; | |
7e34fbd0 | 196 | } values[KVM_MAX_NR_USER_RETURN_MSRS]; |
18863bdd AK |
197 | }; |
198 | ||
7e34fbd0 SC |
199 | static struct kvm_user_return_msrs_global __read_mostly user_return_msrs_global; |
200 | static struct kvm_user_return_msrs __percpu *user_return_msrs; | |
18863bdd | 201 | |
cfc48181 SC |
202 | #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ |
203 | | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ | |
204 | | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ | |
205 | | XFEATURE_MASK_PKRU) | |
206 | ||
91661989 SC |
207 | u64 __read_mostly host_efer; |
208 | EXPORT_SYMBOL_GPL(host_efer); | |
209 | ||
b96e6506 | 210 | bool __read_mostly allow_smaller_maxphyaddr = 0; |
3edd6839 MG |
211 | EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr); |
212 | ||
86137773 TL |
213 | u64 __read_mostly host_xss; |
214 | EXPORT_SYMBOL_GPL(host_xss); | |
408e9a31 PB |
215 | u64 __read_mostly supported_xss; |
216 | EXPORT_SYMBOL_GPL(supported_xss); | |
139a12cf | 217 | |
417bc304 | 218 | struct kvm_stats_debugfs_item debugfs_entries[] = { |
812756a8 EGE |
219 | VCPU_STAT("pf_fixed", pf_fixed), |
220 | VCPU_STAT("pf_guest", pf_guest), | |
221 | VCPU_STAT("tlb_flush", tlb_flush), | |
222 | VCPU_STAT("invlpg", invlpg), | |
223 | VCPU_STAT("exits", exits), | |
224 | VCPU_STAT("io_exits", io_exits), | |
225 | VCPU_STAT("mmio_exits", mmio_exits), | |
226 | VCPU_STAT("signal_exits", signal_exits), | |
227 | VCPU_STAT("irq_window", irq_window_exits), | |
228 | VCPU_STAT("nmi_window", nmi_window_exits), | |
229 | VCPU_STAT("halt_exits", halt_exits), | |
230 | VCPU_STAT("halt_successful_poll", halt_successful_poll), | |
231 | VCPU_STAT("halt_attempted_poll", halt_attempted_poll), | |
232 | VCPU_STAT("halt_poll_invalid", halt_poll_invalid), | |
233 | VCPU_STAT("halt_wakeup", halt_wakeup), | |
234 | VCPU_STAT("hypercalls", hypercalls), | |
235 | VCPU_STAT("request_irq", request_irq_exits), | |
236 | VCPU_STAT("irq_exits", irq_exits), | |
237 | VCPU_STAT("host_state_reload", host_state_reload), | |
238 | VCPU_STAT("fpu_reload", fpu_reload), | |
239 | VCPU_STAT("insn_emulation", insn_emulation), | |
240 | VCPU_STAT("insn_emulation_fail", insn_emulation_fail), | |
241 | VCPU_STAT("irq_injections", irq_injections), | |
242 | VCPU_STAT("nmi_injections", nmi_injections), | |
243 | VCPU_STAT("req_event", req_event), | |
244 | VCPU_STAT("l1d_flush", l1d_flush), | |
cb953129 DM |
245 | VCPU_STAT("halt_poll_success_ns", halt_poll_success_ns), |
246 | VCPU_STAT("halt_poll_fail_ns", halt_poll_fail_ns), | |
812756a8 EGE |
247 | VM_STAT("mmu_shadow_zapped", mmu_shadow_zapped), |
248 | VM_STAT("mmu_pte_write", mmu_pte_write), | |
812756a8 EGE |
249 | VM_STAT("mmu_pde_zapped", mmu_pde_zapped), |
250 | VM_STAT("mmu_flooded", mmu_flooded), | |
251 | VM_STAT("mmu_recycled", mmu_recycled), | |
252 | VM_STAT("mmu_cache_miss", mmu_cache_miss), | |
253 | VM_STAT("mmu_unsync", mmu_unsync), | |
254 | VM_STAT("remote_tlb_flush", remote_tlb_flush), | |
255 | VM_STAT("largepages", lpages, .mode = 0444), | |
256 | VM_STAT("nx_largepages_splitted", nx_lpage_splits, .mode = 0444), | |
257 | VM_STAT("max_mmu_page_hash_collisions", max_mmu_page_hash_collisions), | |
417bc304 HB |
258 | { NULL } |
259 | }; | |
260 | ||
2acf923e | 261 | u64 __read_mostly host_xcr0; |
cfc48181 SC |
262 | u64 __read_mostly supported_xcr0; |
263 | EXPORT_SYMBOL_GPL(supported_xcr0); | |
2acf923e | 264 | |
80fbd280 | 265 | static struct kmem_cache *x86_fpu_cache; |
b666a4b6 | 266 | |
c9b8b07c SC |
267 | static struct kmem_cache *x86_emulator_cache; |
268 | ||
6abe9c13 PX |
269 | /* |
270 | * When called, it means the previous get/set msr reached an invalid msr. | |
cc4cb017 | 271 | * Return true if we want to ignore/silent this failed msr access. |
6abe9c13 | 272 | */ |
cc4cb017 ML |
273 | static bool kvm_msr_ignored_check(struct kvm_vcpu *vcpu, u32 msr, |
274 | u64 data, bool write) | |
6abe9c13 PX |
275 | { |
276 | const char *op = write ? "wrmsr" : "rdmsr"; | |
277 | ||
278 | if (ignore_msrs) { | |
279 | if (report_ignored_msrs) | |
d383b314 TI |
280 | kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n", |
281 | op, msr, data); | |
6abe9c13 | 282 | /* Mask the error */ |
cc4cb017 | 283 | return true; |
6abe9c13 | 284 | } else { |
d383b314 TI |
285 | kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n", |
286 | op, msr, data); | |
cc4cb017 | 287 | return false; |
6abe9c13 PX |
288 | } |
289 | } | |
290 | ||
c9b8b07c SC |
291 | static struct kmem_cache *kvm_alloc_emulator_cache(void) |
292 | { | |
06add254 SC |
293 | unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src); |
294 | unsigned int size = sizeof(struct x86_emulate_ctxt); | |
295 | ||
296 | return kmem_cache_create_usercopy("x86_emulator", size, | |
c9b8b07c | 297 | __alignof__(struct x86_emulate_ctxt), |
06add254 SC |
298 | SLAB_ACCOUNT, useroffset, |
299 | size - useroffset, NULL); | |
c9b8b07c SC |
300 | } |
301 | ||
b6785def | 302 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); |
d6aa1000 | 303 | |
af585b92 GN |
304 | static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) |
305 | { | |
306 | int i; | |
dd03bcaa | 307 | for (i = 0; i < ASYNC_PF_PER_VCPU; i++) |
af585b92 GN |
308 | vcpu->arch.apf.gfns[i] = ~0; |
309 | } | |
310 | ||
18863bdd AK |
311 | static void kvm_on_user_return(struct user_return_notifier *urn) |
312 | { | |
313 | unsigned slot; | |
7e34fbd0 SC |
314 | struct kvm_user_return_msrs *msrs |
315 | = container_of(urn, struct kvm_user_return_msrs, urn); | |
316 | struct kvm_user_return_msr_values *values; | |
1650b4eb IA |
317 | unsigned long flags; |
318 | ||
319 | /* | |
320 | * Disabling irqs at this point since the following code could be | |
321 | * interrupted and executed through kvm_arch_hardware_disable() | |
322 | */ | |
323 | local_irq_save(flags); | |
7e34fbd0 SC |
324 | if (msrs->registered) { |
325 | msrs->registered = false; | |
1650b4eb IA |
326 | user_return_notifier_unregister(urn); |
327 | } | |
328 | local_irq_restore(flags); | |
7e34fbd0 SC |
329 | for (slot = 0; slot < user_return_msrs_global.nr; ++slot) { |
330 | values = &msrs->values[slot]; | |
2bf78fa7 | 331 | if (values->host != values->curr) { |
7e34fbd0 | 332 | wrmsrl(user_return_msrs_global.msrs[slot], values->host); |
2bf78fa7 | 333 | values->curr = values->host; |
18863bdd AK |
334 | } |
335 | } | |
18863bdd AK |
336 | } |
337 | ||
7e34fbd0 | 338 | void kvm_define_user_return_msr(unsigned slot, u32 msr) |
2bf78fa7 | 339 | { |
7e34fbd0 SC |
340 | BUG_ON(slot >= KVM_MAX_NR_USER_RETURN_MSRS); |
341 | user_return_msrs_global.msrs[slot] = msr; | |
342 | if (slot >= user_return_msrs_global.nr) | |
343 | user_return_msrs_global.nr = slot + 1; | |
18863bdd | 344 | } |
7e34fbd0 | 345 | EXPORT_SYMBOL_GPL(kvm_define_user_return_msr); |
18863bdd | 346 | |
7e34fbd0 | 347 | static void kvm_user_return_msr_cpu_online(void) |
18863bdd | 348 | { |
05c19c2f | 349 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 350 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
05c19c2f SC |
351 | u64 value; |
352 | int i; | |
18863bdd | 353 | |
7e34fbd0 SC |
354 | for (i = 0; i < user_return_msrs_global.nr; ++i) { |
355 | rdmsrl_safe(user_return_msrs_global.msrs[i], &value); | |
356 | msrs->values[i].host = value; | |
357 | msrs->values[i].curr = value; | |
05c19c2f | 358 | } |
18863bdd AK |
359 | } |
360 | ||
7e34fbd0 | 361 | int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask) |
18863bdd | 362 | { |
013f6a5d | 363 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 364 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
8b3c3104 | 365 | int err; |
18863bdd | 366 | |
7e34fbd0 SC |
367 | value = (value & mask) | (msrs->values[slot].host & ~mask); |
368 | if (value == msrs->values[slot].curr) | |
8b3c3104 | 369 | return 0; |
7e34fbd0 | 370 | err = wrmsrl_safe(user_return_msrs_global.msrs[slot], value); |
8b3c3104 AH |
371 | if (err) |
372 | return 1; | |
373 | ||
7e34fbd0 SC |
374 | msrs->values[slot].curr = value; |
375 | if (!msrs->registered) { | |
376 | msrs->urn.on_user_return = kvm_on_user_return; | |
377 | user_return_notifier_register(&msrs->urn); | |
378 | msrs->registered = true; | |
18863bdd | 379 | } |
8b3c3104 | 380 | return 0; |
18863bdd | 381 | } |
7e34fbd0 | 382 | EXPORT_SYMBOL_GPL(kvm_set_user_return_msr); |
18863bdd | 383 | |
13a34e06 | 384 | static void drop_user_return_notifiers(void) |
3548bab5 | 385 | { |
013f6a5d | 386 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 387 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
3548bab5 | 388 | |
7e34fbd0 SC |
389 | if (msrs->registered) |
390 | kvm_on_user_return(&msrs->urn); | |
3548bab5 AK |
391 | } |
392 | ||
6866b83e CO |
393 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
394 | { | |
8a5a87d9 | 395 | return vcpu->arch.apic_base; |
6866b83e CO |
396 | } |
397 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
398 | ||
58871649 JM |
399 | enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) |
400 | { | |
401 | return kvm_apic_mode(kvm_get_apic_base(vcpu)); | |
402 | } | |
403 | EXPORT_SYMBOL_GPL(kvm_get_apic_mode); | |
404 | ||
58cb628d JK |
405 | int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
406 | { | |
58871649 JM |
407 | enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); |
408 | enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); | |
d6321d49 RK |
409 | u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff | |
410 | (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); | |
58cb628d | 411 | |
58871649 | 412 | if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) |
58cb628d | 413 | return 1; |
58871649 JM |
414 | if (!msr_info->host_initiated) { |
415 | if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) | |
416 | return 1; | |
417 | if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) | |
418 | return 1; | |
419 | } | |
58cb628d JK |
420 | |
421 | kvm_lapic_set_base(vcpu, msr_info->data); | |
4abaffce | 422 | kvm_recalculate_apic_map(vcpu->kvm); |
58cb628d | 423 | return 0; |
6866b83e CO |
424 | } |
425 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
426 | ||
3ebccdf3 | 427 | asmlinkage __visible noinstr void kvm_spurious_fault(void) |
e3ba45b8 GL |
428 | { |
429 | /* Fault while not rebooting. We want the trace. */ | |
b4fdcf60 | 430 | BUG_ON(!kvm_rebooting); |
e3ba45b8 GL |
431 | } |
432 | EXPORT_SYMBOL_GPL(kvm_spurious_fault); | |
433 | ||
3fd28fce ED |
434 | #define EXCPT_BENIGN 0 |
435 | #define EXCPT_CONTRIBUTORY 1 | |
436 | #define EXCPT_PF 2 | |
437 | ||
438 | static int exception_class(int vector) | |
439 | { | |
440 | switch (vector) { | |
441 | case PF_VECTOR: | |
442 | return EXCPT_PF; | |
443 | case DE_VECTOR: | |
444 | case TS_VECTOR: | |
445 | case NP_VECTOR: | |
446 | case SS_VECTOR: | |
447 | case GP_VECTOR: | |
448 | return EXCPT_CONTRIBUTORY; | |
449 | default: | |
450 | break; | |
451 | } | |
452 | return EXCPT_BENIGN; | |
453 | } | |
454 | ||
d6e8c854 NA |
455 | #define EXCPT_FAULT 0 |
456 | #define EXCPT_TRAP 1 | |
457 | #define EXCPT_ABORT 2 | |
458 | #define EXCPT_INTERRUPT 3 | |
459 | ||
460 | static int exception_type(int vector) | |
461 | { | |
462 | unsigned int mask; | |
463 | ||
464 | if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) | |
465 | return EXCPT_INTERRUPT; | |
466 | ||
467 | mask = 1 << vector; | |
468 | ||
469 | /* #DB is trap, as instruction watchpoints are handled elsewhere */ | |
470 | if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) | |
471 | return EXCPT_TRAP; | |
472 | ||
473 | if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) | |
474 | return EXCPT_ABORT; | |
475 | ||
476 | /* Reserved exceptions will result in fault */ | |
477 | return EXCPT_FAULT; | |
478 | } | |
479 | ||
da998b46 JM |
480 | void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) |
481 | { | |
482 | unsigned nr = vcpu->arch.exception.nr; | |
483 | bool has_payload = vcpu->arch.exception.has_payload; | |
484 | unsigned long payload = vcpu->arch.exception.payload; | |
485 | ||
486 | if (!has_payload) | |
487 | return; | |
488 | ||
489 | switch (nr) { | |
f10c729f JM |
490 | case DB_VECTOR: |
491 | /* | |
492 | * "Certain debug exceptions may clear bit 0-3. The | |
493 | * remaining contents of the DR6 register are never | |
494 | * cleared by the processor". | |
495 | */ | |
496 | vcpu->arch.dr6 &= ~DR_TRAP_BITS; | |
497 | /* | |
9a3ecd5e CQ |
498 | * In order to reflect the #DB exception payload in guest |
499 | * dr6, three components need to be considered: active low | |
500 | * bit, FIXED_1 bits and active high bits (e.g. DR6_BD, | |
501 | * DR6_BS and DR6_BT) | |
502 | * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits. | |
503 | * In the target guest dr6: | |
504 | * FIXED_1 bits should always be set. | |
505 | * Active low bits should be cleared if 1-setting in payload. | |
506 | * Active high bits should be set if 1-setting in payload. | |
507 | * | |
508 | * Note, the payload is compatible with the pending debug | |
509 | * exceptions/exit qualification under VMX, that active_low bits | |
510 | * are active high in payload. | |
511 | * So they need to be flipped for DR6. | |
f10c729f | 512 | */ |
9a3ecd5e | 513 | vcpu->arch.dr6 |= DR6_ACTIVE_LOW; |
f10c729f | 514 | vcpu->arch.dr6 |= payload; |
9a3ecd5e | 515 | vcpu->arch.dr6 ^= payload & DR6_ACTIVE_LOW; |
307f1cfa OU |
516 | |
517 | /* | |
518 | * The #DB payload is defined as compatible with the 'pending | |
519 | * debug exceptions' field under VMX, not DR6. While bit 12 is | |
520 | * defined in the 'pending debug exceptions' field (enabled | |
521 | * breakpoint), it is reserved and must be zero in DR6. | |
522 | */ | |
523 | vcpu->arch.dr6 &= ~BIT(12); | |
f10c729f | 524 | break; |
da998b46 JM |
525 | case PF_VECTOR: |
526 | vcpu->arch.cr2 = payload; | |
527 | break; | |
528 | } | |
529 | ||
530 | vcpu->arch.exception.has_payload = false; | |
531 | vcpu->arch.exception.payload = 0; | |
532 | } | |
533 | EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); | |
534 | ||
3fd28fce | 535 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, |
ce7ddec4 | 536 | unsigned nr, bool has_error, u32 error_code, |
91e86d22 | 537 | bool has_payload, unsigned long payload, bool reinject) |
3fd28fce ED |
538 | { |
539 | u32 prev_nr; | |
540 | int class1, class2; | |
541 | ||
3842d135 AK |
542 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
543 | ||
664f8e26 | 544 | if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { |
3fd28fce | 545 | queue: |
3ffb2468 NA |
546 | if (has_error && !is_protmode(vcpu)) |
547 | has_error = false; | |
664f8e26 WL |
548 | if (reinject) { |
549 | /* | |
550 | * On vmentry, vcpu->arch.exception.pending is only | |
551 | * true if an event injection was blocked by | |
552 | * nested_run_pending. In that case, however, | |
553 | * vcpu_enter_guest requests an immediate exit, | |
554 | * and the guest shouldn't proceed far enough to | |
555 | * need reinjection. | |
556 | */ | |
557 | WARN_ON_ONCE(vcpu->arch.exception.pending); | |
558 | vcpu->arch.exception.injected = true; | |
91e86d22 JM |
559 | if (WARN_ON_ONCE(has_payload)) { |
560 | /* | |
561 | * A reinjected event has already | |
562 | * delivered its payload. | |
563 | */ | |
564 | has_payload = false; | |
565 | payload = 0; | |
566 | } | |
664f8e26 WL |
567 | } else { |
568 | vcpu->arch.exception.pending = true; | |
569 | vcpu->arch.exception.injected = false; | |
570 | } | |
3fd28fce ED |
571 | vcpu->arch.exception.has_error_code = has_error; |
572 | vcpu->arch.exception.nr = nr; | |
573 | vcpu->arch.exception.error_code = error_code; | |
91e86d22 JM |
574 | vcpu->arch.exception.has_payload = has_payload; |
575 | vcpu->arch.exception.payload = payload; | |
a06230b6 | 576 | if (!is_guest_mode(vcpu)) |
da998b46 | 577 | kvm_deliver_exception_payload(vcpu); |
3fd28fce ED |
578 | return; |
579 | } | |
580 | ||
581 | /* to check exception */ | |
582 | prev_nr = vcpu->arch.exception.nr; | |
583 | if (prev_nr == DF_VECTOR) { | |
584 | /* triple fault -> shutdown */ | |
a8eeb04a | 585 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
3fd28fce ED |
586 | return; |
587 | } | |
588 | class1 = exception_class(prev_nr); | |
589 | class2 = exception_class(nr); | |
590 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) | |
591 | || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
664f8e26 WL |
592 | /* |
593 | * Generate double fault per SDM Table 5-5. Set | |
594 | * exception.pending = true so that the double fault | |
595 | * can trigger a nested vmexit. | |
596 | */ | |
3fd28fce | 597 | vcpu->arch.exception.pending = true; |
664f8e26 | 598 | vcpu->arch.exception.injected = false; |
3fd28fce ED |
599 | vcpu->arch.exception.has_error_code = true; |
600 | vcpu->arch.exception.nr = DF_VECTOR; | |
601 | vcpu->arch.exception.error_code = 0; | |
c851436a JM |
602 | vcpu->arch.exception.has_payload = false; |
603 | vcpu->arch.exception.payload = 0; | |
3fd28fce ED |
604 | } else |
605 | /* replace previous exception with a new one in a hope | |
606 | that instruction re-execution will regenerate lost | |
607 | exception */ | |
608 | goto queue; | |
609 | } | |
610 | ||
298101da AK |
611 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
612 | { | |
91e86d22 | 613 | kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); |
298101da AK |
614 | } |
615 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
616 | ||
ce7ddec4 JR |
617 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
618 | { | |
91e86d22 | 619 | kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); |
ce7ddec4 JR |
620 | } |
621 | EXPORT_SYMBOL_GPL(kvm_requeue_exception); | |
622 | ||
4d5523cf PB |
623 | void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, |
624 | unsigned long payload) | |
f10c729f JM |
625 | { |
626 | kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); | |
627 | } | |
4d5523cf | 628 | EXPORT_SYMBOL_GPL(kvm_queue_exception_p); |
f10c729f | 629 | |
da998b46 JM |
630 | static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, |
631 | u32 error_code, unsigned long payload) | |
632 | { | |
633 | kvm_multiple_exception(vcpu, nr, true, error_code, | |
634 | true, payload, false); | |
635 | } | |
636 | ||
6affcbed | 637 | int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) |
c3c91fee | 638 | { |
db8fcefa AP |
639 | if (err) |
640 | kvm_inject_gp(vcpu, 0); | |
641 | else | |
6affcbed KH |
642 | return kvm_skip_emulated_instruction(vcpu); |
643 | ||
644 | return 1; | |
db8fcefa AP |
645 | } |
646 | EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); | |
8df25a32 | 647 | |
6389ee94 | 648 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
c3c91fee AK |
649 | { |
650 | ++vcpu->stat.pf_guest; | |
adfe20fb WL |
651 | vcpu->arch.exception.nested_apf = |
652 | is_guest_mode(vcpu) && fault->async_page_fault; | |
da998b46 | 653 | if (vcpu->arch.exception.nested_apf) { |
adfe20fb | 654 | vcpu->arch.apf.nested_apf_token = fault->address; |
da998b46 JM |
655 | kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); |
656 | } else { | |
657 | kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, | |
658 | fault->address); | |
659 | } | |
c3c91fee | 660 | } |
27d6c865 | 661 | EXPORT_SYMBOL_GPL(kvm_inject_page_fault); |
c3c91fee | 662 | |
53b3d8e9 SC |
663 | bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, |
664 | struct x86_exception *fault) | |
d4f8cf66 | 665 | { |
0cd665bd | 666 | struct kvm_mmu *fault_mmu; |
53b3d8e9 SC |
667 | WARN_ON_ONCE(fault->vector != PF_VECTOR); |
668 | ||
0cd665bd PB |
669 | fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu : |
670 | vcpu->arch.walk_mmu; | |
ef54bcfe | 671 | |
ee1fa209 JS |
672 | /* |
673 | * Invalidate the TLB entry for the faulting address, if it exists, | |
674 | * else the access will fault indefinitely (and to emulate hardware). | |
675 | */ | |
676 | if ((fault->error_code & PFERR_PRESENT_MASK) && | |
677 | !(fault->error_code & PFERR_RSVD_MASK)) | |
678 | kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address, | |
679 | fault_mmu->root_hpa); | |
680 | ||
681 | fault_mmu->inject_page_fault(vcpu, fault); | |
ef54bcfe | 682 | return fault->nested_page_fault; |
d4f8cf66 | 683 | } |
53b3d8e9 | 684 | EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault); |
d4f8cf66 | 685 | |
3419ffc8 SY |
686 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
687 | { | |
7460fb4a AK |
688 | atomic_inc(&vcpu->arch.nmi_queued); |
689 | kvm_make_request(KVM_REQ_NMI, vcpu); | |
3419ffc8 SY |
690 | } |
691 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
692 | ||
298101da AK |
693 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
694 | { | |
91e86d22 | 695 | kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); |
298101da AK |
696 | } |
697 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
698 | ||
ce7ddec4 JR |
699 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
700 | { | |
91e86d22 | 701 | kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); |
ce7ddec4 JR |
702 | } |
703 | EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); | |
704 | ||
0a79b009 AK |
705 | /* |
706 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
707 | * a #GP and return false. | |
708 | */ | |
709 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 710 | { |
afaf0b2f | 711 | if (kvm_x86_ops.get_cpl(vcpu) <= required_cpl) |
0a79b009 AK |
712 | return true; |
713 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
714 | return false; | |
298101da | 715 | } |
0a79b009 | 716 | EXPORT_SYMBOL_GPL(kvm_require_cpl); |
298101da | 717 | |
16f8a6f9 NA |
718 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) |
719 | { | |
720 | if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
721 | return true; | |
722 | ||
723 | kvm_queue_exception(vcpu, UD_VECTOR); | |
724 | return false; | |
725 | } | |
726 | EXPORT_SYMBOL_GPL(kvm_require_dr); | |
727 | ||
ec92fe44 JR |
728 | /* |
729 | * This function will be used to read from the physical memory of the currently | |
54bf36aa | 730 | * running guest. The difference to kvm_vcpu_read_guest_page is that this function |
ec92fe44 JR |
731 | * can read from guest physical or from the guest's guest physical memory. |
732 | */ | |
733 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
734 | gfn_t ngfn, void *data, int offset, int len, | |
735 | u32 access) | |
736 | { | |
54987b7a | 737 | struct x86_exception exception; |
ec92fe44 JR |
738 | gfn_t real_gfn; |
739 | gpa_t ngpa; | |
740 | ||
741 | ngpa = gfn_to_gpa(ngfn); | |
54987b7a | 742 | real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); |
ec92fe44 JR |
743 | if (real_gfn == UNMAPPED_GVA) |
744 | return -EFAULT; | |
745 | ||
746 | real_gfn = gpa_to_gfn(real_gfn); | |
747 | ||
54bf36aa | 748 | return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); |
ec92fe44 JR |
749 | } |
750 | EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); | |
751 | ||
69b0049a | 752 | static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, |
3d06b8bf JR |
753 | void *data, int offset, int len, u32 access) |
754 | { | |
755 | return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, | |
756 | data, offset, len, access); | |
757 | } | |
758 | ||
16cfacc8 SC |
759 | static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) |
760 | { | |
761 | return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) | | |
762 | rsvd_bits(1, 2); | |
763 | } | |
764 | ||
a03490ed | 765 | /* |
16cfacc8 | 766 | * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. |
a03490ed | 767 | */ |
ff03a073 | 768 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) |
a03490ed CO |
769 | { |
770 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
771 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
772 | int i; | |
773 | int ret; | |
ff03a073 | 774 | u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; |
a03490ed | 775 | |
ff03a073 JR |
776 | ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, |
777 | offset * sizeof(u64), sizeof(pdpte), | |
778 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
a03490ed CO |
779 | if (ret < 0) { |
780 | ret = 0; | |
781 | goto out; | |
782 | } | |
783 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
812f30b2 | 784 | if ((pdpte[i] & PT_PRESENT_MASK) && |
16cfacc8 | 785 | (pdpte[i] & pdptr_rsvd_bits(vcpu))) { |
a03490ed CO |
786 | ret = 0; |
787 | goto out; | |
788 | } | |
789 | } | |
790 | ret = 1; | |
791 | ||
ff03a073 | 792 | memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); |
cb3c1e2f SC |
793 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); |
794 | ||
a03490ed | 795 | out: |
a03490ed CO |
796 | |
797 | return ret; | |
798 | } | |
cc4b6871 | 799 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 800 | |
9ed38ffa | 801 | bool pdptrs_changed(struct kvm_vcpu *vcpu) |
d835dfec | 802 | { |
ff03a073 | 803 | u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; |
3d06b8bf JR |
804 | int offset; |
805 | gfn_t gfn; | |
d835dfec AK |
806 | int r; |
807 | ||
bf03d4f9 | 808 | if (!is_pae_paging(vcpu)) |
d835dfec AK |
809 | return false; |
810 | ||
cb3c1e2f | 811 | if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR)) |
6de4f3ad AK |
812 | return true; |
813 | ||
a512177e PB |
814 | gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT; |
815 | offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1); | |
3d06b8bf JR |
816 | r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), |
817 | PFERR_USER_MASK | PFERR_WRITE_MASK); | |
d835dfec | 818 | if (r < 0) |
7f7f0d9c | 819 | return true; |
d835dfec | 820 | |
7f7f0d9c | 821 | return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; |
d835dfec | 822 | } |
9ed38ffa | 823 | EXPORT_SYMBOL_GPL(pdptrs_changed); |
d835dfec | 824 | |
f27ad38a TL |
825 | void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0) |
826 | { | |
827 | unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; | |
828 | ||
829 | if ((cr0 ^ old_cr0) & X86_CR0_PG) { | |
830 | kvm_clear_async_pf_completion_queue(vcpu); | |
831 | kvm_async_pf_hash_reset(vcpu); | |
832 | } | |
833 | ||
834 | if ((cr0 ^ old_cr0) & update_bits) | |
835 | kvm_mmu_reset_context(vcpu); | |
836 | ||
837 | if (((cr0 ^ old_cr0) & X86_CR0_CD) && | |
838 | kvm_arch_has_noncoherent_dma(vcpu->kvm) && | |
839 | !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) | |
840 | kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); | |
841 | } | |
842 | EXPORT_SYMBOL_GPL(kvm_post_set_cr0); | |
843 | ||
49a9b07e | 844 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 845 | { |
aad82703 | 846 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
d42e3fae | 847 | unsigned long pdptr_bits = X86_CR0_CD | X86_CR0_NW | X86_CR0_PG; |
aad82703 | 848 | |
f9a48e6a AK |
849 | cr0 |= X86_CR0_ET; |
850 | ||
ab344828 | 851 | #ifdef CONFIG_X86_64 |
0f12244f GN |
852 | if (cr0 & 0xffffffff00000000UL) |
853 | return 1; | |
ab344828 GN |
854 | #endif |
855 | ||
856 | cr0 &= ~CR0_RESERVED_BITS; | |
a03490ed | 857 | |
0f12244f GN |
858 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) |
859 | return 1; | |
a03490ed | 860 | |
0f12244f GN |
861 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) |
862 | return 1; | |
a03490ed | 863 | |
a03490ed | 864 | #ifdef CONFIG_X86_64 |
05487215 SC |
865 | if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) && |
866 | (cr0 & X86_CR0_PG)) { | |
867 | int cs_db, cs_l; | |
868 | ||
869 | if (!is_pae(vcpu)) | |
870 | return 1; | |
871 | kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
872 | if (cs_l) | |
0f12244f | 873 | return 1; |
a03490ed | 874 | } |
05487215 SC |
875 | #endif |
876 | if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) && | |
877 | is_pae(vcpu) && ((cr0 ^ old_cr0) & pdptr_bits) && | |
878 | !load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu))) | |
879 | return 1; | |
a03490ed | 880 | |
ad756a16 MJ |
881 | if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) |
882 | return 1; | |
883 | ||
afaf0b2f | 884 | kvm_x86_ops.set_cr0(vcpu, cr0); |
a03490ed | 885 | |
f27ad38a | 886 | kvm_post_set_cr0(vcpu, old_cr0, cr0); |
b18d5431 | 887 | |
0f12244f GN |
888 | return 0; |
889 | } | |
2d3ad1f4 | 890 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 891 | |
2d3ad1f4 | 892 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 893 | { |
49a9b07e | 894 | (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); |
a03490ed | 895 | } |
2d3ad1f4 | 896 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 897 | |
139a12cf | 898 | void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) |
42bdf991 | 899 | { |
16809ecd TL |
900 | if (vcpu->arch.guest_state_protected) |
901 | return; | |
902 | ||
139a12cf AL |
903 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { |
904 | ||
905 | if (vcpu->arch.xcr0 != host_xcr0) | |
906 | xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); | |
907 | ||
908 | if (vcpu->arch.xsaves_enabled && | |
909 | vcpu->arch.ia32_xss != host_xss) | |
910 | wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); | |
911 | } | |
37486135 BM |
912 | |
913 | if (static_cpu_has(X86_FEATURE_PKU) && | |
914 | (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || | |
915 | (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) && | |
916 | vcpu->arch.pkru != vcpu->arch.host_pkru) | |
917 | __write_pkru(vcpu->arch.pkru); | |
42bdf991 | 918 | } |
139a12cf | 919 | EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state); |
42bdf991 | 920 | |
139a12cf | 921 | void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) |
42bdf991 | 922 | { |
16809ecd TL |
923 | if (vcpu->arch.guest_state_protected) |
924 | return; | |
925 | ||
37486135 BM |
926 | if (static_cpu_has(X86_FEATURE_PKU) && |
927 | (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || | |
928 | (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) { | |
929 | vcpu->arch.pkru = rdpkru(); | |
930 | if (vcpu->arch.pkru != vcpu->arch.host_pkru) | |
931 | __write_pkru(vcpu->arch.host_pkru); | |
932 | } | |
933 | ||
139a12cf AL |
934 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { |
935 | ||
936 | if (vcpu->arch.xcr0 != host_xcr0) | |
937 | xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); | |
938 | ||
939 | if (vcpu->arch.xsaves_enabled && | |
940 | vcpu->arch.ia32_xss != host_xss) | |
941 | wrmsrl(MSR_IA32_XSS, host_xss); | |
942 | } | |
943 | ||
42bdf991 | 944 | } |
139a12cf | 945 | EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state); |
42bdf991 | 946 | |
69b0049a | 947 | static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) |
2acf923e | 948 | { |
56c103ec LJ |
949 | u64 xcr0 = xcr; |
950 | u64 old_xcr0 = vcpu->arch.xcr0; | |
46c34cb0 | 951 | u64 valid_bits; |
2acf923e DC |
952 | |
953 | /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ | |
954 | if (index != XCR_XFEATURE_ENABLED_MASK) | |
955 | return 1; | |
d91cab78 | 956 | if (!(xcr0 & XFEATURE_MASK_FP)) |
2acf923e | 957 | return 1; |
d91cab78 | 958 | if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) |
2acf923e | 959 | return 1; |
46c34cb0 PB |
960 | |
961 | /* | |
962 | * Do not allow the guest to set bits that we do not support | |
963 | * saving. However, xcr0 bit 0 is always set, even if the | |
964 | * emulated CPU does not support XSAVE (see fx_init). | |
965 | */ | |
d91cab78 | 966 | valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; |
46c34cb0 | 967 | if (xcr0 & ~valid_bits) |
2acf923e | 968 | return 1; |
46c34cb0 | 969 | |
d91cab78 DH |
970 | if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != |
971 | (!(xcr0 & XFEATURE_MASK_BNDCSR))) | |
390bd528 LJ |
972 | return 1; |
973 | ||
d91cab78 DH |
974 | if (xcr0 & XFEATURE_MASK_AVX512) { |
975 | if (!(xcr0 & XFEATURE_MASK_YMM)) | |
612263b3 | 976 | return 1; |
d91cab78 | 977 | if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) |
612263b3 CP |
978 | return 1; |
979 | } | |
2acf923e | 980 | vcpu->arch.xcr0 = xcr0; |
56c103ec | 981 | |
d91cab78 | 982 | if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) |
aedbaf4f | 983 | kvm_update_cpuid_runtime(vcpu); |
2acf923e DC |
984 | return 0; |
985 | } | |
986 | ||
987 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) | |
988 | { | |
afaf0b2f | 989 | if (kvm_x86_ops.get_cpl(vcpu) != 0 || |
764bcbc5 | 990 | __kvm_set_xcr(vcpu, index, xcr)) { |
2acf923e DC |
991 | kvm_inject_gp(vcpu, 0); |
992 | return 1; | |
993 | } | |
994 | return 0; | |
995 | } | |
996 | EXPORT_SYMBOL_GPL(kvm_set_xcr); | |
997 | ||
ee69c92b | 998 | bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 999 | { |
b11306b5 | 1000 | if (cr4 & cr4_reserved_bits) |
ee69c92b | 1001 | return false; |
b9baba86 | 1002 | |
b899c132 | 1003 | if (cr4 & vcpu->arch.cr4_guest_rsvd_bits) |
ee69c92b | 1004 | return false; |
3ca94192 | 1005 | |
ee69c92b | 1006 | return kvm_x86_ops.is_valid_cr4(vcpu, cr4); |
3ca94192 | 1007 | } |
ee69c92b | 1008 | EXPORT_SYMBOL_GPL(kvm_is_valid_cr4); |
3ca94192 | 1009 | |
5b51cb13 TL |
1010 | void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4) |
1011 | { | |
1012 | unsigned long mmu_role_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | | |
1013 | X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE; | |
1014 | ||
1015 | if (((cr4 ^ old_cr4) & mmu_role_bits) || | |
1016 | (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) | |
1017 | kvm_mmu_reset_context(vcpu); | |
3ca94192 | 1018 | } |
5b51cb13 | 1019 | EXPORT_SYMBOL_GPL(kvm_post_set_cr4); |
3ca94192 WL |
1020 | |
1021 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1022 | { | |
1023 | unsigned long old_cr4 = kvm_read_cr4(vcpu); | |
1024 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | | |
cb957adb | 1025 | X86_CR4_SMEP; |
3ca94192 | 1026 | |
ee69c92b | 1027 | if (!kvm_is_valid_cr4(vcpu, cr4)) |
ae3e61e1 PB |
1028 | return 1; |
1029 | ||
a03490ed | 1030 | if (is_long_mode(vcpu)) { |
0f12244f GN |
1031 | if (!(cr4 & X86_CR4_PAE)) |
1032 | return 1; | |
d74fcfc1 SC |
1033 | if ((cr4 ^ old_cr4) & X86_CR4_LA57) |
1034 | return 1; | |
a2edf57f AK |
1035 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
1036 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
9f8fe504 AK |
1037 | && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
1038 | kvm_read_cr3(vcpu))) | |
0f12244f GN |
1039 | return 1; |
1040 | ||
ad756a16 | 1041 | if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { |
d6321d49 | 1042 | if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) |
ad756a16 MJ |
1043 | return 1; |
1044 | ||
1045 | /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ | |
1046 | if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) | |
1047 | return 1; | |
1048 | } | |
1049 | ||
c2fe3cd4 | 1050 | kvm_x86_ops.set_cr4(vcpu, cr4); |
a03490ed | 1051 | |
5b51cb13 | 1052 | kvm_post_set_cr4(vcpu, old_cr4, cr4); |
2acf923e | 1053 | |
0f12244f GN |
1054 | return 0; |
1055 | } | |
2d3ad1f4 | 1056 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 1057 | |
2390218b | 1058 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 1059 | { |
ade61e28 | 1060 | bool skip_tlb_flush = false; |
ac146235 | 1061 | #ifdef CONFIG_X86_64 |
c19986fe JS |
1062 | bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); |
1063 | ||
ade61e28 | 1064 | if (pcid_enabled) { |
208320ba JS |
1065 | skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; |
1066 | cr3 &= ~X86_CR3_PCID_NOFLUSH; | |
ade61e28 | 1067 | } |
ac146235 | 1068 | #endif |
9d88fca7 | 1069 | |
9f8fe504 | 1070 | if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { |
956bf353 JS |
1071 | if (!skip_tlb_flush) { |
1072 | kvm_mmu_sync_roots(vcpu); | |
eeeb4f67 | 1073 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
956bf353 | 1074 | } |
0f12244f | 1075 | return 0; |
d835dfec AK |
1076 | } |
1077 | ||
d1cd3ce9 | 1078 | if (is_long_mode(vcpu) && |
0107973a | 1079 | (cr3 & vcpu->arch.cr3_lm_rsvd_bits)) |
d1cd3ce9 | 1080 | return 1; |
bf03d4f9 PB |
1081 | else if (is_pae_paging(vcpu) && |
1082 | !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) | |
346874c9 | 1083 | return 1; |
a03490ed | 1084 | |
be01e8e2 | 1085 | kvm_mmu_new_pgd(vcpu, cr3, skip_tlb_flush, skip_tlb_flush); |
0f12244f | 1086 | vcpu->arch.cr3 = cr3; |
cb3c1e2f | 1087 | kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); |
7c390d35 | 1088 | |
0f12244f GN |
1089 | return 0; |
1090 | } | |
2d3ad1f4 | 1091 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 1092 | |
eea1cff9 | 1093 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed | 1094 | { |
0f12244f GN |
1095 | if (cr8 & CR8_RESERVED_BITS) |
1096 | return 1; | |
35754c98 | 1097 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
1098 | kvm_lapic_set_tpr(vcpu, cr8); |
1099 | else | |
ad312c7c | 1100 | vcpu->arch.cr8 = cr8; |
0f12244f GN |
1101 | return 0; |
1102 | } | |
2d3ad1f4 | 1103 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 1104 | |
2d3ad1f4 | 1105 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed | 1106 | { |
35754c98 | 1107 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
1108 | return kvm_lapic_get_cr8(vcpu); |
1109 | else | |
ad312c7c | 1110 | return vcpu->arch.cr8; |
a03490ed | 1111 | } |
2d3ad1f4 | 1112 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 1113 | |
ae561ede NA |
1114 | static void kvm_update_dr0123(struct kvm_vcpu *vcpu) |
1115 | { | |
1116 | int i; | |
1117 | ||
1118 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
1119 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
1120 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
1121 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; | |
1122 | } | |
1123 | } | |
1124 | ||
7c86663b | 1125 | void kvm_update_dr7(struct kvm_vcpu *vcpu) |
c8639010 JK |
1126 | { |
1127 | unsigned long dr7; | |
1128 | ||
1129 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
1130 | dr7 = vcpu->arch.guest_debug_dr7; | |
1131 | else | |
1132 | dr7 = vcpu->arch.dr7; | |
afaf0b2f | 1133 | kvm_x86_ops.set_dr7(vcpu, dr7); |
360b948d PB |
1134 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; |
1135 | if (dr7 & DR7_BP_EN_MASK) | |
1136 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; | |
c8639010 | 1137 | } |
7c86663b | 1138 | EXPORT_SYMBOL_GPL(kvm_update_dr7); |
c8639010 | 1139 | |
6f43ed01 NA |
1140 | static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) |
1141 | { | |
1142 | u64 fixed = DR6_FIXED_1; | |
1143 | ||
d6321d49 | 1144 | if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) |
6f43ed01 NA |
1145 | fixed |= DR6_RTM; |
1146 | return fixed; | |
1147 | } | |
1148 | ||
338dbc97 | 1149 | static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) |
020df079 | 1150 | { |
ea740059 MP |
1151 | size_t size = ARRAY_SIZE(vcpu->arch.db); |
1152 | ||
020df079 GN |
1153 | switch (dr) { |
1154 | case 0 ... 3: | |
ea740059 | 1155 | vcpu->arch.db[array_index_nospec(dr, size)] = val; |
020df079 GN |
1156 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) |
1157 | vcpu->arch.eff_db[dr] = val; | |
1158 | break; | |
1159 | case 4: | |
020df079 | 1160 | case 6: |
f5f6145e | 1161 | if (!kvm_dr6_valid(val)) |
338dbc97 | 1162 | return -1; /* #GP */ |
6f43ed01 | 1163 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); |
020df079 GN |
1164 | break; |
1165 | case 5: | |
020df079 | 1166 | default: /* 7 */ |
b91991bf | 1167 | if (!kvm_dr7_valid(val)) |
338dbc97 | 1168 | return -1; /* #GP */ |
020df079 | 1169 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; |
c8639010 | 1170 | kvm_update_dr7(vcpu); |
020df079 GN |
1171 | break; |
1172 | } | |
1173 | ||
1174 | return 0; | |
1175 | } | |
338dbc97 GN |
1176 | |
1177 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) | |
1178 | { | |
16f8a6f9 | 1179 | if (__kvm_set_dr(vcpu, dr, val)) { |
338dbc97 | 1180 | kvm_inject_gp(vcpu, 0); |
16f8a6f9 NA |
1181 | return 1; |
1182 | } | |
1183 | return 0; | |
338dbc97 | 1184 | } |
020df079 GN |
1185 | EXPORT_SYMBOL_GPL(kvm_set_dr); |
1186 | ||
16f8a6f9 | 1187 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) |
020df079 | 1188 | { |
ea740059 MP |
1189 | size_t size = ARRAY_SIZE(vcpu->arch.db); |
1190 | ||
020df079 GN |
1191 | switch (dr) { |
1192 | case 0 ... 3: | |
ea740059 | 1193 | *val = vcpu->arch.db[array_index_nospec(dr, size)]; |
020df079 GN |
1194 | break; |
1195 | case 4: | |
020df079 | 1196 | case 6: |
5679b803 | 1197 | *val = vcpu->arch.dr6; |
020df079 GN |
1198 | break; |
1199 | case 5: | |
020df079 GN |
1200 | default: /* 7 */ |
1201 | *val = vcpu->arch.dr7; | |
1202 | break; | |
1203 | } | |
338dbc97 GN |
1204 | return 0; |
1205 | } | |
020df079 GN |
1206 | EXPORT_SYMBOL_GPL(kvm_get_dr); |
1207 | ||
022cd0e8 AK |
1208 | bool kvm_rdpmc(struct kvm_vcpu *vcpu) |
1209 | { | |
de3cd117 | 1210 | u32 ecx = kvm_rcx_read(vcpu); |
022cd0e8 AK |
1211 | u64 data; |
1212 | int err; | |
1213 | ||
c6702c9d | 1214 | err = kvm_pmu_rdpmc(vcpu, ecx, &data); |
022cd0e8 AK |
1215 | if (err) |
1216 | return err; | |
de3cd117 SC |
1217 | kvm_rax_write(vcpu, (u32)data); |
1218 | kvm_rdx_write(vcpu, data >> 32); | |
022cd0e8 AK |
1219 | return err; |
1220 | } | |
1221 | EXPORT_SYMBOL_GPL(kvm_rdpmc); | |
1222 | ||
043405e1 CO |
1223 | /* |
1224 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
1225 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
1226 | * | |
7a5ee6ed CQ |
1227 | * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) |
1228 | * extract the supported MSRs from the related const lists. | |
1229 | * msrs_to_save is selected from the msrs_to_save_all to reflect the | |
e3267cbb | 1230 | * capabilities of the host cpu. This capabilities test skips MSRs that are |
7a5ee6ed | 1231 | * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs |
62ef68bb | 1232 | * may depend on host virtualization features rather than host cpu features. |
043405e1 | 1233 | */ |
e3267cbb | 1234 | |
7a5ee6ed | 1235 | static const u32 msrs_to_save_all[] = { |
043405e1 | 1236 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, |
8c06585d | 1237 | MSR_STAR, |
043405e1 CO |
1238 | #ifdef CONFIG_X86_64 |
1239 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
1240 | #endif | |
b3897a49 | 1241 | MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, |
32ad73db | 1242 | MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, |
2bdb76c0 | 1243 | MSR_IA32_SPEC_CTRL, |
bf8c55d8 CP |
1244 | MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, |
1245 | MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, | |
1246 | MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, | |
1247 | MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, | |
1248 | MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, | |
1249 | MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, | |
6e3ba4ab TX |
1250 | MSR_IA32_UMWAIT_CONTROL, |
1251 | ||
e2ada66e JM |
1252 | MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, |
1253 | MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3, | |
1254 | MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, | |
1255 | MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, | |
1256 | MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, | |
1257 | MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, | |
1258 | MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, | |
1259 | MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, | |
1260 | MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9, | |
1261 | MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11, | |
1262 | MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13, | |
1263 | MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15, | |
1264 | MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17, | |
e2ada66e JM |
1265 | MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, |
1266 | MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, | |
1267 | MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, | |
1268 | MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, | |
1269 | MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9, | |
1270 | MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11, | |
1271 | MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13, | |
1272 | MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15, | |
1273 | MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17, | |
043405e1 CO |
1274 | }; |
1275 | ||
7a5ee6ed | 1276 | static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)]; |
043405e1 CO |
1277 | static unsigned num_msrs_to_save; |
1278 | ||
7a5ee6ed | 1279 | static const u32 emulated_msrs_all[] = { |
62ef68bb PB |
1280 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, |
1281 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, | |
1282 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, | |
1283 | HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, | |
72c139ba | 1284 | HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, |
e7d9513b AS |
1285 | HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, |
1286 | HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, | |
e516cebb | 1287 | HV_X64_MSR_RESET, |
11c4b1ca | 1288 | HV_X64_MSR_VP_INDEX, |
9eec50b8 | 1289 | HV_X64_MSR_VP_RUNTIME, |
5c919412 | 1290 | HV_X64_MSR_SCONTROL, |
1f4b34f8 | 1291 | HV_X64_MSR_STIMER0_CONFIG, |
d4abc577 | 1292 | HV_X64_MSR_VP_ASSIST_PAGE, |
a2e164e7 VK |
1293 | HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, |
1294 | HV_X64_MSR_TSC_EMULATION_STATUS, | |
f97f5a56 JD |
1295 | HV_X64_MSR_SYNDBG_OPTIONS, |
1296 | HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS, | |
1297 | HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER, | |
1298 | HV_X64_MSR_SYNDBG_PENDING_BUFFER, | |
a2e164e7 VK |
1299 | |
1300 | MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, | |
557a961a | 1301 | MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK, |
62ef68bb | 1302 | |
ba904635 | 1303 | MSR_IA32_TSC_ADJUST, |
a3e06bbe | 1304 | MSR_IA32_TSCDEADLINE, |
2bdb76c0 | 1305 | MSR_IA32_ARCH_CAPABILITIES, |
27461da3 | 1306 | MSR_IA32_PERF_CAPABILITIES, |
043405e1 | 1307 | MSR_IA32_MISC_ENABLE, |
908e75f3 AK |
1308 | MSR_IA32_MCG_STATUS, |
1309 | MSR_IA32_MCG_CTL, | |
c45dcc71 | 1310 | MSR_IA32_MCG_EXT_CTL, |
64d60670 | 1311 | MSR_IA32_SMBASE, |
52797bf9 | 1312 | MSR_SMI_COUNT, |
db2336a8 KH |
1313 | MSR_PLATFORM_INFO, |
1314 | MSR_MISC_FEATURES_ENABLES, | |
bc226f07 | 1315 | MSR_AMD64_VIRT_SPEC_CTRL, |
6c6a2ab9 | 1316 | MSR_IA32_POWER_CTL, |
99634e3e | 1317 | MSR_IA32_UCODE_REV, |
191c8137 | 1318 | |
95c5c7c7 PB |
1319 | /* |
1320 | * The following list leaves out MSRs whose values are determined | |
1321 | * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs. | |
1322 | * We always support the "true" VMX control MSRs, even if the host | |
1323 | * processor does not, so I am putting these registers here rather | |
7a5ee6ed | 1324 | * than in msrs_to_save_all. |
95c5c7c7 PB |
1325 | */ |
1326 | MSR_IA32_VMX_BASIC, | |
1327 | MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
1328 | MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
1329 | MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
1330 | MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
1331 | MSR_IA32_VMX_MISC, | |
1332 | MSR_IA32_VMX_CR0_FIXED0, | |
1333 | MSR_IA32_VMX_CR4_FIXED0, | |
1334 | MSR_IA32_VMX_VMCS_ENUM, | |
1335 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
1336 | MSR_IA32_VMX_EPT_VPID_CAP, | |
1337 | MSR_IA32_VMX_VMFUNC, | |
1338 | ||
191c8137 | 1339 | MSR_K7_HWCR, |
2d5ba19b | 1340 | MSR_KVM_POLL_CONTROL, |
043405e1 CO |
1341 | }; |
1342 | ||
7a5ee6ed | 1343 | static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]; |
62ef68bb PB |
1344 | static unsigned num_emulated_msrs; |
1345 | ||
801e459a TL |
1346 | /* |
1347 | * List of msr numbers which are used to expose MSR-based features that | |
1348 | * can be used by a hypervisor to validate requested CPU features. | |
1349 | */ | |
7a5ee6ed | 1350 | static const u32 msr_based_features_all[] = { |
1389309c PB |
1351 | MSR_IA32_VMX_BASIC, |
1352 | MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
1353 | MSR_IA32_VMX_PINBASED_CTLS, | |
1354 | MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
1355 | MSR_IA32_VMX_PROCBASED_CTLS, | |
1356 | MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
1357 | MSR_IA32_VMX_EXIT_CTLS, | |
1358 | MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
1359 | MSR_IA32_VMX_ENTRY_CTLS, | |
1360 | MSR_IA32_VMX_MISC, | |
1361 | MSR_IA32_VMX_CR0_FIXED0, | |
1362 | MSR_IA32_VMX_CR0_FIXED1, | |
1363 | MSR_IA32_VMX_CR4_FIXED0, | |
1364 | MSR_IA32_VMX_CR4_FIXED1, | |
1365 | MSR_IA32_VMX_VMCS_ENUM, | |
1366 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
1367 | MSR_IA32_VMX_EPT_VPID_CAP, | |
1368 | MSR_IA32_VMX_VMFUNC, | |
1369 | ||
d1d93fa9 | 1370 | MSR_F10H_DECFG, |
518e7b94 | 1371 | MSR_IA32_UCODE_REV, |
cd283252 | 1372 | MSR_IA32_ARCH_CAPABILITIES, |
27461da3 | 1373 | MSR_IA32_PERF_CAPABILITIES, |
801e459a TL |
1374 | }; |
1375 | ||
7a5ee6ed | 1376 | static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)]; |
801e459a TL |
1377 | static unsigned int num_msr_based_features; |
1378 | ||
4d22c17c | 1379 | static u64 kvm_get_arch_capabilities(void) |
5b76a3cf | 1380 | { |
4d22c17c | 1381 | u64 data = 0; |
5b76a3cf | 1382 | |
4d22c17c XL |
1383 | if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) |
1384 | rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data); | |
5b76a3cf | 1385 | |
b8e8c830 PB |
1386 | /* |
1387 | * If nx_huge_pages is enabled, KVM's shadow paging will ensure that | |
1388 | * the nested hypervisor runs with NX huge pages. If it is not, | |
1389 | * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other | |
1390 | * L1 guests, so it need not worry about its own (L2) guests. | |
1391 | */ | |
1392 | data |= ARCH_CAP_PSCHANGE_MC_NO; | |
1393 | ||
5b76a3cf PB |
1394 | /* |
1395 | * If we're doing cache flushes (either "always" or "cond") | |
1396 | * we will do one whenever the guest does a vmlaunch/vmresume. | |
1397 | * If an outer hypervisor is doing the cache flush for us | |
1398 | * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that | |
1399 | * capability to the guest too, and if EPT is disabled we're not | |
1400 | * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will | |
1401 | * require a nested hypervisor to do a flush of its own. | |
1402 | */ | |
1403 | if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) | |
1404 | data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; | |
1405 | ||
0c54914d PB |
1406 | if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) |
1407 | data |= ARCH_CAP_RDCL_NO; | |
1408 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
1409 | data |= ARCH_CAP_SSB_NO; | |
1410 | if (!boot_cpu_has_bug(X86_BUG_MDS)) | |
1411 | data |= ARCH_CAP_MDS_NO; | |
1412 | ||
7131636e PB |
1413 | if (!boot_cpu_has(X86_FEATURE_RTM)) { |
1414 | /* | |
1415 | * If RTM=0 because the kernel has disabled TSX, the host might | |
1416 | * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0 | |
1417 | * and therefore knows that there cannot be TAA) but keep | |
1418 | * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts, | |
1419 | * and we want to allow migrating those guests to tsx=off hosts. | |
1420 | */ | |
1421 | data &= ~ARCH_CAP_TAA_NO; | |
1422 | } else if (!boot_cpu_has_bug(X86_BUG_TAA)) { | |
cbbaa272 | 1423 | data |= ARCH_CAP_TAA_NO; |
7131636e PB |
1424 | } else { |
1425 | /* | |
1426 | * Nothing to do here; we emulate TSX_CTRL if present on the | |
1427 | * host so the guest can choose between disabling TSX or | |
1428 | * using VERW to clear CPU buffers. | |
1429 | */ | |
1430 | } | |
e1d38b63 | 1431 | |
5b76a3cf PB |
1432 | return data; |
1433 | } | |
5b76a3cf | 1434 | |
66421c1e WL |
1435 | static int kvm_get_msr_feature(struct kvm_msr_entry *msr) |
1436 | { | |
1437 | switch (msr->index) { | |
cd283252 | 1438 | case MSR_IA32_ARCH_CAPABILITIES: |
5b76a3cf PB |
1439 | msr->data = kvm_get_arch_capabilities(); |
1440 | break; | |
1441 | case MSR_IA32_UCODE_REV: | |
cd283252 | 1442 | rdmsrl_safe(msr->index, &msr->data); |
518e7b94 | 1443 | break; |
66421c1e | 1444 | default: |
12bc2132 | 1445 | return kvm_x86_ops.get_msr_feature(msr); |
66421c1e WL |
1446 | } |
1447 | return 0; | |
1448 | } | |
1449 | ||
801e459a TL |
1450 | static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) |
1451 | { | |
1452 | struct kvm_msr_entry msr; | |
66421c1e | 1453 | int r; |
801e459a TL |
1454 | |
1455 | msr.index = index; | |
66421c1e | 1456 | r = kvm_get_msr_feature(&msr); |
12bc2132 PX |
1457 | |
1458 | if (r == KVM_MSR_RET_INVALID) { | |
1459 | /* Unconditionally clear the output for simplicity */ | |
1460 | *data = 0; | |
cc4cb017 ML |
1461 | if (kvm_msr_ignored_check(vcpu, index, 0, false)) |
1462 | r = 0; | |
12bc2132 PX |
1463 | } |
1464 | ||
66421c1e WL |
1465 | if (r) |
1466 | return r; | |
801e459a TL |
1467 | |
1468 | *data = msr.data; | |
1469 | ||
1470 | return 0; | |
1471 | } | |
1472 | ||
11988499 | 1473 | static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) |
15c4a640 | 1474 | { |
1b4d56b8 | 1475 | if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) |
11988499 | 1476 | return false; |
1b2fd70c | 1477 | |
1b4d56b8 | 1478 | if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) |
11988499 | 1479 | return false; |
d8017474 | 1480 | |
0a629563 SC |
1481 | if (efer & (EFER_LME | EFER_LMA) && |
1482 | !guest_cpuid_has(vcpu, X86_FEATURE_LM)) | |
1483 | return false; | |
1484 | ||
1485 | if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) | |
1486 | return false; | |
d8017474 | 1487 | |
384bb783 | 1488 | return true; |
11988499 SC |
1489 | |
1490 | } | |
1491 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) | |
1492 | { | |
1493 | if (efer & efer_reserved_bits) | |
1494 | return false; | |
1495 | ||
1496 | return __kvm_valid_efer(vcpu, efer); | |
384bb783 JK |
1497 | } |
1498 | EXPORT_SYMBOL_GPL(kvm_valid_efer); | |
1499 | ||
11988499 | 1500 | static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
384bb783 JK |
1501 | { |
1502 | u64 old_efer = vcpu->arch.efer; | |
11988499 | 1503 | u64 efer = msr_info->data; |
72f211ec | 1504 | int r; |
384bb783 | 1505 | |
11988499 | 1506 | if (efer & efer_reserved_bits) |
66f61c92 | 1507 | return 1; |
384bb783 | 1508 | |
11988499 SC |
1509 | if (!msr_info->host_initiated) { |
1510 | if (!__kvm_valid_efer(vcpu, efer)) | |
1511 | return 1; | |
1512 | ||
1513 | if (is_paging(vcpu) && | |
1514 | (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) | |
1515 | return 1; | |
1516 | } | |
384bb783 | 1517 | |
15c4a640 | 1518 | efer &= ~EFER_LMA; |
f6801dff | 1519 | efer |= vcpu->arch.efer & EFER_LMA; |
15c4a640 | 1520 | |
72f211ec ML |
1521 | r = kvm_x86_ops.set_efer(vcpu, efer); |
1522 | if (r) { | |
1523 | WARN_ON(r > 0); | |
1524 | return r; | |
1525 | } | |
a3d204e2 | 1526 | |
aad82703 SY |
1527 | /* Update reserved bits */ |
1528 | if ((efer ^ old_efer) & EFER_NX) | |
1529 | kvm_mmu_reset_context(vcpu); | |
1530 | ||
b69e8cae | 1531 | return 0; |
15c4a640 CO |
1532 | } |
1533 | ||
f2b4b7dd JR |
1534 | void kvm_enable_efer_bits(u64 mask) |
1535 | { | |
1536 | efer_reserved_bits &= ~mask; | |
1537 | } | |
1538 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
1539 | ||
51de8151 AG |
1540 | bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type) |
1541 | { | |
1a155254 AG |
1542 | struct kvm *kvm = vcpu->kvm; |
1543 | struct msr_bitmap_range *ranges = kvm->arch.msr_filter.ranges; | |
1544 | u32 count = kvm->arch.msr_filter.count; | |
1545 | u32 i; | |
1546 | bool r = kvm->arch.msr_filter.default_allow; | |
1547 | int idx; | |
1548 | ||
9389b9d5 SC |
1549 | /* MSR filtering not set up or x2APIC enabled, allow everything */ |
1550 | if (!count || (index >= 0x800 && index <= 0x8ff)) | |
1a155254 AG |
1551 | return true; |
1552 | ||
1553 | /* Prevent collision with set_msr_filter */ | |
1554 | idx = srcu_read_lock(&kvm->srcu); | |
1555 | ||
1556 | for (i = 0; i < count; i++) { | |
1557 | u32 start = ranges[i].base; | |
1558 | u32 end = start + ranges[i].nmsrs; | |
1559 | u32 flags = ranges[i].flags; | |
1560 | unsigned long *bitmap = ranges[i].bitmap; | |
1561 | ||
1562 | if ((index >= start) && (index < end) && (flags & type)) { | |
1563 | r = !!test_bit(index - start, bitmap); | |
1564 | break; | |
1565 | } | |
1566 | } | |
1567 | ||
1568 | srcu_read_unlock(&kvm->srcu, idx); | |
1569 | ||
1570 | return r; | |
51de8151 AG |
1571 | } |
1572 | EXPORT_SYMBOL_GPL(kvm_msr_allowed); | |
1573 | ||
15c4a640 | 1574 | /* |
f20935d8 SC |
1575 | * Write @data into the MSR specified by @index. Select MSR specific fault |
1576 | * checks are bypassed if @host_initiated is %true. | |
15c4a640 CO |
1577 | * Returns 0 on success, non-0 otherwise. |
1578 | * Assumes vcpu_load() was already called. | |
1579 | */ | |
f20935d8 SC |
1580 | static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, |
1581 | bool host_initiated) | |
15c4a640 | 1582 | { |
f20935d8 SC |
1583 | struct msr_data msr; |
1584 | ||
1a155254 | 1585 | if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE)) |
cc4cb017 | 1586 | return KVM_MSR_RET_FILTERED; |
1a155254 | 1587 | |
f20935d8 | 1588 | switch (index) { |
854e8bb1 NA |
1589 | case MSR_FS_BASE: |
1590 | case MSR_GS_BASE: | |
1591 | case MSR_KERNEL_GS_BASE: | |
1592 | case MSR_CSTAR: | |
1593 | case MSR_LSTAR: | |
f20935d8 | 1594 | if (is_noncanonical_address(data, vcpu)) |
854e8bb1 NA |
1595 | return 1; |
1596 | break; | |
1597 | case MSR_IA32_SYSENTER_EIP: | |
1598 | case MSR_IA32_SYSENTER_ESP: | |
1599 | /* | |
1600 | * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if | |
1601 | * non-canonical address is written on Intel but not on | |
1602 | * AMD (which ignores the top 32-bits, because it does | |
1603 | * not implement 64-bit SYSENTER). | |
1604 | * | |
1605 | * 64-bit code should hence be able to write a non-canonical | |
1606 | * value on AMD. Making the address canonical ensures that | |
1607 | * vmentry does not fail on Intel after writing a non-canonical | |
1608 | * value, and that something deterministic happens if the guest | |
1609 | * invokes 64-bit SYSENTER. | |
1610 | */ | |
f20935d8 | 1611 | data = get_canonical(data, vcpu_virt_addr_bits(vcpu)); |
854e8bb1 | 1612 | } |
f20935d8 SC |
1613 | |
1614 | msr.data = data; | |
1615 | msr.index = index; | |
1616 | msr.host_initiated = host_initiated; | |
1617 | ||
afaf0b2f | 1618 | return kvm_x86_ops.set_msr(vcpu, &msr); |
15c4a640 CO |
1619 | } |
1620 | ||
6abe9c13 PX |
1621 | static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu, |
1622 | u32 index, u64 data, bool host_initiated) | |
1623 | { | |
1624 | int ret = __kvm_set_msr(vcpu, index, data, host_initiated); | |
1625 | ||
1626 | if (ret == KVM_MSR_RET_INVALID) | |
cc4cb017 ML |
1627 | if (kvm_msr_ignored_check(vcpu, index, data, true)) |
1628 | ret = 0; | |
6abe9c13 PX |
1629 | |
1630 | return ret; | |
1631 | } | |
1632 | ||
313a3dc7 | 1633 | /* |
f20935d8 SC |
1634 | * Read the MSR specified by @index into @data. Select MSR specific fault |
1635 | * checks are bypassed if @host_initiated is %true. | |
1636 | * Returns 0 on success, non-0 otherwise. | |
1637 | * Assumes vcpu_load() was already called. | |
313a3dc7 | 1638 | */ |
edef5c36 PB |
1639 | int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, |
1640 | bool host_initiated) | |
609e36d3 PB |
1641 | { |
1642 | struct msr_data msr; | |
f20935d8 | 1643 | int ret; |
609e36d3 | 1644 | |
1a155254 | 1645 | if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ)) |
cc4cb017 | 1646 | return KVM_MSR_RET_FILTERED; |
1a155254 | 1647 | |
609e36d3 | 1648 | msr.index = index; |
f20935d8 | 1649 | msr.host_initiated = host_initiated; |
609e36d3 | 1650 | |
afaf0b2f | 1651 | ret = kvm_x86_ops.get_msr(vcpu, &msr); |
f20935d8 SC |
1652 | if (!ret) |
1653 | *data = msr.data; | |
1654 | return ret; | |
609e36d3 PB |
1655 | } |
1656 | ||
6abe9c13 PX |
1657 | static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu, |
1658 | u32 index, u64 *data, bool host_initiated) | |
1659 | { | |
1660 | int ret = __kvm_get_msr(vcpu, index, data, host_initiated); | |
1661 | ||
1662 | if (ret == KVM_MSR_RET_INVALID) { | |
1663 | /* Unconditionally clear *data for simplicity */ | |
1664 | *data = 0; | |
cc4cb017 ML |
1665 | if (kvm_msr_ignored_check(vcpu, index, 0, false)) |
1666 | ret = 0; | |
6abe9c13 PX |
1667 | } |
1668 | ||
1669 | return ret; | |
1670 | } | |
1671 | ||
f20935d8 | 1672 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) |
313a3dc7 | 1673 | { |
6abe9c13 | 1674 | return kvm_get_msr_ignored_check(vcpu, index, data, false); |
f20935d8 SC |
1675 | } |
1676 | EXPORT_SYMBOL_GPL(kvm_get_msr); | |
8fe8ab46 | 1677 | |
f20935d8 SC |
1678 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) |
1679 | { | |
6abe9c13 | 1680 | return kvm_set_msr_ignored_check(vcpu, index, data, false); |
f20935d8 SC |
1681 | } |
1682 | EXPORT_SYMBOL_GPL(kvm_set_msr); | |
1683 | ||
8b474427 | 1684 | static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu) |
1ae09954 | 1685 | { |
8b474427 PB |
1686 | int err = vcpu->run->msr.error; |
1687 | if (!err) { | |
1ae09954 AG |
1688 | kvm_rax_write(vcpu, (u32)vcpu->run->msr.data); |
1689 | kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32); | |
1690 | } | |
1691 | ||
f9a4d621 | 1692 | return kvm_x86_ops.complete_emulated_msr(vcpu, err); |
1ae09954 AG |
1693 | } |
1694 | ||
1695 | static int complete_emulated_wrmsr(struct kvm_vcpu *vcpu) | |
1696 | { | |
f9a4d621 | 1697 | return kvm_x86_ops.complete_emulated_msr(vcpu, vcpu->run->msr.error); |
1ae09954 AG |
1698 | } |
1699 | ||
1700 | static u64 kvm_msr_reason(int r) | |
1701 | { | |
1702 | switch (r) { | |
cc4cb017 | 1703 | case KVM_MSR_RET_INVALID: |
1ae09954 | 1704 | return KVM_MSR_EXIT_REASON_UNKNOWN; |
cc4cb017 | 1705 | case KVM_MSR_RET_FILTERED: |
1a155254 | 1706 | return KVM_MSR_EXIT_REASON_FILTER; |
1ae09954 AG |
1707 | default: |
1708 | return KVM_MSR_EXIT_REASON_INVAL; | |
1709 | } | |
1710 | } | |
1711 | ||
1712 | static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index, | |
1713 | u32 exit_reason, u64 data, | |
1714 | int (*completion)(struct kvm_vcpu *vcpu), | |
1715 | int r) | |
1716 | { | |
1717 | u64 msr_reason = kvm_msr_reason(r); | |
1718 | ||
1719 | /* Check if the user wanted to know about this MSR fault */ | |
1720 | if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason)) | |
1721 | return 0; | |
1722 | ||
1723 | vcpu->run->exit_reason = exit_reason; | |
1724 | vcpu->run->msr.error = 0; | |
1725 | memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad)); | |
1726 | vcpu->run->msr.reason = msr_reason; | |
1727 | vcpu->run->msr.index = index; | |
1728 | vcpu->run->msr.data = data; | |
1729 | vcpu->arch.complete_userspace_io = completion; | |
1730 | ||
1731 | return 1; | |
1732 | } | |
1733 | ||
1734 | static int kvm_get_msr_user_space(struct kvm_vcpu *vcpu, u32 index, int r) | |
1735 | { | |
1736 | return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_RDMSR, 0, | |
1737 | complete_emulated_rdmsr, r); | |
1738 | } | |
1739 | ||
1740 | static int kvm_set_msr_user_space(struct kvm_vcpu *vcpu, u32 index, u64 data, int r) | |
1741 | { | |
1742 | return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_WRMSR, data, | |
1743 | complete_emulated_wrmsr, r); | |
1744 | } | |
1745 | ||
1edce0a9 SC |
1746 | int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) |
1747 | { | |
1748 | u32 ecx = kvm_rcx_read(vcpu); | |
1749 | u64 data; | |
1ae09954 AG |
1750 | int r; |
1751 | ||
1752 | r = kvm_get_msr(vcpu, ecx, &data); | |
1edce0a9 | 1753 | |
1ae09954 AG |
1754 | /* MSR read failed? See if we should ask user space */ |
1755 | if (r && kvm_get_msr_user_space(vcpu, ecx, r)) { | |
1756 | /* Bounce to user space */ | |
1757 | return 0; | |
1758 | } | |
1759 | ||
8b474427 PB |
1760 | if (!r) { |
1761 | trace_kvm_msr_read(ecx, data); | |
1762 | ||
1763 | kvm_rax_write(vcpu, data & -1u); | |
1764 | kvm_rdx_write(vcpu, (data >> 32) & -1u); | |
1765 | } else { | |
1edce0a9 | 1766 | trace_kvm_msr_read_ex(ecx); |
1edce0a9 SC |
1767 | } |
1768 | ||
f9a4d621 | 1769 | return kvm_x86_ops.complete_emulated_msr(vcpu, r); |
1edce0a9 SC |
1770 | } |
1771 | EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); | |
1772 | ||
1773 | int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) | |
1774 | { | |
1775 | u32 ecx = kvm_rcx_read(vcpu); | |
1776 | u64 data = kvm_read_edx_eax(vcpu); | |
1ae09954 | 1777 | int r; |
1edce0a9 | 1778 | |
1ae09954 AG |
1779 | r = kvm_set_msr(vcpu, ecx, data); |
1780 | ||
1781 | /* MSR write failed? See if we should ask user space */ | |
7dffecaf | 1782 | if (r && kvm_set_msr_user_space(vcpu, ecx, data, r)) |
1ae09954 AG |
1783 | /* Bounce to user space */ |
1784 | return 0; | |
7dffecaf ML |
1785 | |
1786 | /* Signal all other negative errors to userspace */ | |
1787 | if (r < 0) | |
1788 | return r; | |
1ae09954 | 1789 | |
8b474427 PB |
1790 | if (!r) |
1791 | trace_kvm_msr_write(ecx, data); | |
1792 | else | |
1edce0a9 | 1793 | trace_kvm_msr_write_ex(ecx, data); |
1edce0a9 | 1794 | |
f9a4d621 | 1795 | return kvm_x86_ops.complete_emulated_msr(vcpu, r); |
1edce0a9 SC |
1796 | } |
1797 | EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); | |
1798 | ||
5a9f5443 WL |
1799 | bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu) |
1800 | { | |
1801 | return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) || | |
72c3c0fe | 1802 | xfer_to_guest_mode_work_pending(); |
5a9f5443 WL |
1803 | } |
1804 | EXPORT_SYMBOL_GPL(kvm_vcpu_exit_request); | |
1805 | ||
1e9e2622 WL |
1806 | /* |
1807 | * The fast path for frequent and performance sensitive wrmsr emulation, | |
1808 | * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces | |
1809 | * the latency of virtual IPI by avoiding the expensive bits of transitioning | |
1810 | * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the | |
1811 | * other cases which must be called after interrupts are enabled on the host. | |
1812 | */ | |
1813 | static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data) | |
1814 | { | |
e1be9ac8 WL |
1815 | if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic)) |
1816 | return 1; | |
1817 | ||
1818 | if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) && | |
1e9e2622 | 1819 | ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) && |
4064a4c6 WL |
1820 | ((data & APIC_MODE_MASK) == APIC_DM_FIXED) && |
1821 | ((u32)(data >> 32) != X2APIC_BROADCAST)) { | |
1e9e2622 | 1822 | |
d5361678 WL |
1823 | data &= ~(1 << 12); |
1824 | kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32)); | |
1e9e2622 | 1825 | kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32)); |
d5361678 WL |
1826 | kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data); |
1827 | trace_kvm_apic_write(APIC_ICR, (u32)data); | |
1828 | return 0; | |
1e9e2622 WL |
1829 | } |
1830 | ||
1831 | return 1; | |
1832 | } | |
1833 | ||
ae95f566 WL |
1834 | static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data) |
1835 | { | |
1836 | if (!kvm_can_use_hv_timer(vcpu)) | |
1837 | return 1; | |
1838 | ||
1839 | kvm_set_lapic_tscdeadline_msr(vcpu, data); | |
1840 | return 0; | |
1841 | } | |
1842 | ||
404d5d7b | 1843 | fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu) |
1e9e2622 WL |
1844 | { |
1845 | u32 msr = kvm_rcx_read(vcpu); | |
8a1038de | 1846 | u64 data; |
404d5d7b | 1847 | fastpath_t ret = EXIT_FASTPATH_NONE; |
1e9e2622 WL |
1848 | |
1849 | switch (msr) { | |
1850 | case APIC_BASE_MSR + (APIC_ICR >> 4): | |
8a1038de | 1851 | data = kvm_read_edx_eax(vcpu); |
404d5d7b WL |
1852 | if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) { |
1853 | kvm_skip_emulated_instruction(vcpu); | |
1854 | ret = EXIT_FASTPATH_EXIT_HANDLED; | |
80bc97f2 | 1855 | } |
1e9e2622 | 1856 | break; |
ae95f566 WL |
1857 | case MSR_IA32_TSCDEADLINE: |
1858 | data = kvm_read_edx_eax(vcpu); | |
1859 | if (!handle_fastpath_set_tscdeadline(vcpu, data)) { | |
1860 | kvm_skip_emulated_instruction(vcpu); | |
1861 | ret = EXIT_FASTPATH_REENTER_GUEST; | |
1862 | } | |
1863 | break; | |
1e9e2622 | 1864 | default: |
404d5d7b | 1865 | break; |
1e9e2622 WL |
1866 | } |
1867 | ||
404d5d7b | 1868 | if (ret != EXIT_FASTPATH_NONE) |
1e9e2622 | 1869 | trace_kvm_msr_write(msr, data); |
1e9e2622 | 1870 | |
404d5d7b | 1871 | return ret; |
1e9e2622 WL |
1872 | } |
1873 | EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); | |
1874 | ||
f20935d8 SC |
1875 | /* |
1876 | * Adapt set_msr() to msr_io()'s calling convention | |
1877 | */ | |
1878 | static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
1879 | { | |
6abe9c13 | 1880 | return kvm_get_msr_ignored_check(vcpu, index, data, true); |
f20935d8 SC |
1881 | } |
1882 | ||
1883 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
1884 | { | |
6abe9c13 | 1885 | return kvm_set_msr_ignored_check(vcpu, index, *data, true); |
313a3dc7 CO |
1886 | } |
1887 | ||
16e8d74d | 1888 | #ifdef CONFIG_X86_64 |
53fafdbb MT |
1889 | struct pvclock_clock { |
1890 | int vclock_mode; | |
1891 | u64 cycle_last; | |
1892 | u64 mask; | |
1893 | u32 mult; | |
1894 | u32 shift; | |
917f9475 PB |
1895 | u64 base_cycles; |
1896 | u64 offset; | |
53fafdbb MT |
1897 | }; |
1898 | ||
16e8d74d MT |
1899 | struct pvclock_gtod_data { |
1900 | seqcount_t seq; | |
1901 | ||
53fafdbb MT |
1902 | struct pvclock_clock clock; /* extract of a clocksource struct */ |
1903 | struct pvclock_clock raw_clock; /* extract of a clocksource struct */ | |
16e8d74d | 1904 | |
917f9475 | 1905 | ktime_t offs_boot; |
55dd00a7 | 1906 | u64 wall_time_sec; |
16e8d74d MT |
1907 | }; |
1908 | ||
1909 | static struct pvclock_gtod_data pvclock_gtod_data; | |
1910 | ||
1911 | static void update_pvclock_gtod(struct timekeeper *tk) | |
1912 | { | |
1913 | struct pvclock_gtod_data *vdata = &pvclock_gtod_data; | |
1914 | ||
1915 | write_seqcount_begin(&vdata->seq); | |
1916 | ||
1917 | /* copy pvclock gtod data */ | |
b95a8a27 | 1918 | vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode; |
876e7881 PZ |
1919 | vdata->clock.cycle_last = tk->tkr_mono.cycle_last; |
1920 | vdata->clock.mask = tk->tkr_mono.mask; | |
1921 | vdata->clock.mult = tk->tkr_mono.mult; | |
1922 | vdata->clock.shift = tk->tkr_mono.shift; | |
917f9475 PB |
1923 | vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec; |
1924 | vdata->clock.offset = tk->tkr_mono.base; | |
16e8d74d | 1925 | |
b95a8a27 | 1926 | vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode; |
53fafdbb MT |
1927 | vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last; |
1928 | vdata->raw_clock.mask = tk->tkr_raw.mask; | |
1929 | vdata->raw_clock.mult = tk->tkr_raw.mult; | |
1930 | vdata->raw_clock.shift = tk->tkr_raw.shift; | |
917f9475 PB |
1931 | vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec; |
1932 | vdata->raw_clock.offset = tk->tkr_raw.base; | |
16e8d74d | 1933 | |
55dd00a7 MT |
1934 | vdata->wall_time_sec = tk->xtime_sec; |
1935 | ||
917f9475 | 1936 | vdata->offs_boot = tk->offs_boot; |
53fafdbb | 1937 | |
16e8d74d MT |
1938 | write_seqcount_end(&vdata->seq); |
1939 | } | |
8171cd68 PB |
1940 | |
1941 | static s64 get_kvmclock_base_ns(void) | |
1942 | { | |
1943 | /* Count up from boot time, but with the frequency of the raw clock. */ | |
1944 | return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot)); | |
1945 | } | |
1946 | #else | |
1947 | static s64 get_kvmclock_base_ns(void) | |
1948 | { | |
1949 | /* Master clock not used, so we can just use CLOCK_BOOTTIME. */ | |
1950 | return ktime_get_boottime_ns(); | |
1951 | } | |
16e8d74d MT |
1952 | #endif |
1953 | ||
18068523 GOC |
1954 | static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) |
1955 | { | |
9ed3c444 AK |
1956 | int version; |
1957 | int r; | |
50d0a0f9 | 1958 | struct pvclock_wall_clock wc; |
8171cd68 | 1959 | u64 wall_nsec; |
18068523 | 1960 | |
210dfd93 OU |
1961 | kvm->arch.wall_clock = wall_clock; |
1962 | ||
18068523 GOC |
1963 | if (!wall_clock) |
1964 | return; | |
1965 | ||
9ed3c444 AK |
1966 | r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); |
1967 | if (r) | |
1968 | return; | |
1969 | ||
1970 | if (version & 1) | |
1971 | ++version; /* first time write, random junk */ | |
1972 | ||
1973 | ++version; | |
18068523 | 1974 | |
1dab1345 NK |
1975 | if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) |
1976 | return; | |
18068523 | 1977 | |
50d0a0f9 GH |
1978 | /* |
1979 | * The guest calculates current wall clock time by adding | |
34c238a1 | 1980 | * system time (updated by kvm_guest_time_update below) to the |
8171cd68 | 1981 | * wall clock specified here. We do the reverse here. |
50d0a0f9 | 1982 | */ |
8171cd68 | 1983 | wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm); |
50d0a0f9 | 1984 | |
8171cd68 PB |
1985 | wc.nsec = do_div(wall_nsec, 1000000000); |
1986 | wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */ | |
50d0a0f9 | 1987 | wc.version = version; |
18068523 GOC |
1988 | |
1989 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
1990 | ||
1991 | version++; | |
1992 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
1993 | } |
1994 | ||
5b9bb0eb OU |
1995 | static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time, |
1996 | bool old_msr, bool host_initiated) | |
1997 | { | |
1998 | struct kvm_arch *ka = &vcpu->kvm->arch; | |
1999 | ||
2000 | if (vcpu->vcpu_id == 0 && !host_initiated) { | |
1e293d1a | 2001 | if (ka->boot_vcpu_runs_old_kvmclock != old_msr) |
5b9bb0eb OU |
2002 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
2003 | ||
2004 | ka->boot_vcpu_runs_old_kvmclock = old_msr; | |
2005 | } | |
2006 | ||
2007 | vcpu->arch.time = system_time; | |
2008 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); | |
2009 | ||
2010 | /* we verify if the enable bit is set... */ | |
2011 | vcpu->arch.pv_time_enabled = false; | |
2012 | if (!(system_time & 1)) | |
2013 | return; | |
2014 | ||
2015 | if (!kvm_gfn_to_hva_cache_init(vcpu->kvm, | |
2016 | &vcpu->arch.pv_time, system_time & ~1ULL, | |
2017 | sizeof(struct pvclock_vcpu_time_info))) | |
2018 | vcpu->arch.pv_time_enabled = true; | |
2019 | ||
2020 | return; | |
2021 | } | |
2022 | ||
50d0a0f9 GH |
2023 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
2024 | { | |
b51012de PB |
2025 | do_shl32_div32(dividend, divisor); |
2026 | return dividend; | |
50d0a0f9 GH |
2027 | } |
2028 | ||
3ae13faa | 2029 | static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, |
5f4e3f88 | 2030 | s8 *pshift, u32 *pmultiplier) |
50d0a0f9 | 2031 | { |
5f4e3f88 | 2032 | uint64_t scaled64; |
50d0a0f9 GH |
2033 | int32_t shift = 0; |
2034 | uint64_t tps64; | |
2035 | uint32_t tps32; | |
2036 | ||
3ae13faa PB |
2037 | tps64 = base_hz; |
2038 | scaled64 = scaled_hz; | |
50933623 | 2039 | while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { |
50d0a0f9 GH |
2040 | tps64 >>= 1; |
2041 | shift--; | |
2042 | } | |
2043 | ||
2044 | tps32 = (uint32_t)tps64; | |
50933623 JK |
2045 | while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { |
2046 | if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) | |
5f4e3f88 ZA |
2047 | scaled64 >>= 1; |
2048 | else | |
2049 | tps32 <<= 1; | |
50d0a0f9 GH |
2050 | shift++; |
2051 | } | |
2052 | ||
5f4e3f88 ZA |
2053 | *pshift = shift; |
2054 | *pmultiplier = div_frac(scaled64, tps32); | |
50d0a0f9 GH |
2055 | } |
2056 | ||
d828199e | 2057 | #ifdef CONFIG_X86_64 |
16e8d74d | 2058 | static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); |
d828199e | 2059 | #endif |
16e8d74d | 2060 | |
c8076604 | 2061 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
69b0049a | 2062 | static unsigned long max_tsc_khz; |
c8076604 | 2063 | |
cc578287 | 2064 | static u32 adjust_tsc_khz(u32 khz, s32 ppm) |
1e993611 | 2065 | { |
cc578287 ZA |
2066 | u64 v = (u64)khz * (1000000 + ppm); |
2067 | do_div(v, 1000000); | |
2068 | return v; | |
1e993611 JR |
2069 | } |
2070 | ||
381d585c HZ |
2071 | static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) |
2072 | { | |
2073 | u64 ratio; | |
2074 | ||
2075 | /* Guest TSC same frequency as host TSC? */ | |
2076 | if (!scale) { | |
2077 | vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; | |
2078 | return 0; | |
2079 | } | |
2080 | ||
2081 | /* TSC scaling supported? */ | |
2082 | if (!kvm_has_tsc_control) { | |
2083 | if (user_tsc_khz > tsc_khz) { | |
2084 | vcpu->arch.tsc_catchup = 1; | |
2085 | vcpu->arch.tsc_always_catchup = 1; | |
2086 | return 0; | |
2087 | } else { | |
3f16a5c3 | 2088 | pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); |
381d585c HZ |
2089 | return -1; |
2090 | } | |
2091 | } | |
2092 | ||
2093 | /* TSC scaling required - calculate ratio */ | |
2094 | ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, | |
2095 | user_tsc_khz, tsc_khz); | |
2096 | ||
2097 | if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { | |
3f16a5c3 PB |
2098 | pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", |
2099 | user_tsc_khz); | |
381d585c HZ |
2100 | return -1; |
2101 | } | |
2102 | ||
2103 | vcpu->arch.tsc_scaling_ratio = ratio; | |
2104 | return 0; | |
2105 | } | |
2106 | ||
4941b8cb | 2107 | static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) |
759379dd | 2108 | { |
cc578287 ZA |
2109 | u32 thresh_lo, thresh_hi; |
2110 | int use_scaling = 0; | |
217fc9cf | 2111 | |
03ba32ca | 2112 | /* tsc_khz can be zero if TSC calibration fails */ |
4941b8cb | 2113 | if (user_tsc_khz == 0) { |
ad721883 HZ |
2114 | /* set tsc_scaling_ratio to a safe value */ |
2115 | vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; | |
381d585c | 2116 | return -1; |
ad721883 | 2117 | } |
03ba32ca | 2118 | |
c285545f | 2119 | /* Compute a scale to convert nanoseconds in TSC cycles */ |
3ae13faa | 2120 | kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, |
cc578287 ZA |
2121 | &vcpu->arch.virtual_tsc_shift, |
2122 | &vcpu->arch.virtual_tsc_mult); | |
4941b8cb | 2123 | vcpu->arch.virtual_tsc_khz = user_tsc_khz; |
cc578287 ZA |
2124 | |
2125 | /* | |
2126 | * Compute the variation in TSC rate which is acceptable | |
2127 | * within the range of tolerance and decide if the | |
2128 | * rate being applied is within that bounds of the hardware | |
2129 | * rate. If so, no scaling or compensation need be done. | |
2130 | */ | |
2131 | thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); | |
2132 | thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); | |
4941b8cb PB |
2133 | if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { |
2134 | pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); | |
cc578287 ZA |
2135 | use_scaling = 1; |
2136 | } | |
4941b8cb | 2137 | return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); |
c285545f ZA |
2138 | } |
2139 | ||
2140 | static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) | |
2141 | { | |
e26101b1 | 2142 | u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, |
cc578287 ZA |
2143 | vcpu->arch.virtual_tsc_mult, |
2144 | vcpu->arch.virtual_tsc_shift); | |
e26101b1 | 2145 | tsc += vcpu->arch.this_tsc_write; |
c285545f ZA |
2146 | return tsc; |
2147 | } | |
2148 | ||
b0c39dc6 VK |
2149 | static inline int gtod_is_based_on_tsc(int mode) |
2150 | { | |
b95a8a27 | 2151 | return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK; |
b0c39dc6 VK |
2152 | } |
2153 | ||
69b0049a | 2154 | static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) |
b48aa97e MT |
2155 | { |
2156 | #ifdef CONFIG_X86_64 | |
2157 | bool vcpus_matched; | |
b48aa97e MT |
2158 | struct kvm_arch *ka = &vcpu->kvm->arch; |
2159 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
2160 | ||
2161 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
2162 | atomic_read(&vcpu->kvm->online_vcpus)); | |
2163 | ||
7f187922 MT |
2164 | /* |
2165 | * Once the masterclock is enabled, always perform request in | |
2166 | * order to update it. | |
2167 | * | |
2168 | * In order to enable masterclock, the host clocksource must be TSC | |
2169 | * and the vcpus need to have matched TSCs. When that happens, | |
2170 | * perform request to enable masterclock. | |
2171 | */ | |
2172 | if (ka->use_master_clock || | |
b0c39dc6 | 2173 | (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) |
b48aa97e MT |
2174 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
2175 | ||
2176 | trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, | |
2177 | atomic_read(&vcpu->kvm->online_vcpus), | |
2178 | ka->use_master_clock, gtod->clock.vclock_mode); | |
2179 | #endif | |
2180 | } | |
2181 | ||
35181e86 HZ |
2182 | /* |
2183 | * Multiply tsc by a fixed point number represented by ratio. | |
2184 | * | |
2185 | * The most significant 64-N bits (mult) of ratio represent the | |
2186 | * integral part of the fixed point number; the remaining N bits | |
2187 | * (frac) represent the fractional part, ie. ratio represents a fixed | |
2188 | * point number (mult + frac * 2^(-N)). | |
2189 | * | |
2190 | * N equals to kvm_tsc_scaling_ratio_frac_bits. | |
2191 | */ | |
2192 | static inline u64 __scale_tsc(u64 ratio, u64 tsc) | |
2193 | { | |
2194 | return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); | |
2195 | } | |
2196 | ||
2197 | u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) | |
2198 | { | |
2199 | u64 _tsc = tsc; | |
2200 | u64 ratio = vcpu->arch.tsc_scaling_ratio; | |
2201 | ||
2202 | if (ratio != kvm_default_tsc_scaling_ratio) | |
2203 | _tsc = __scale_tsc(ratio, tsc); | |
2204 | ||
2205 | return _tsc; | |
2206 | } | |
2207 | EXPORT_SYMBOL_GPL(kvm_scale_tsc); | |
2208 | ||
07c1419a HZ |
2209 | static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) |
2210 | { | |
2211 | u64 tsc; | |
2212 | ||
2213 | tsc = kvm_scale_tsc(vcpu, rdtsc()); | |
2214 | ||
2215 | return target_tsc - tsc; | |
2216 | } | |
2217 | ||
4ba76538 HZ |
2218 | u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) |
2219 | { | |
56ba77a4 | 2220 | return vcpu->arch.l1_tsc_offset + kvm_scale_tsc(vcpu, host_tsc); |
4ba76538 HZ |
2221 | } |
2222 | EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); | |
2223 | ||
a545ab6a LC |
2224 | static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
2225 | { | |
56ba77a4 | 2226 | vcpu->arch.l1_tsc_offset = offset; |
afaf0b2f | 2227 | vcpu->arch.tsc_offset = kvm_x86_ops.write_l1_tsc_offset(vcpu, offset); |
a545ab6a LC |
2228 | } |
2229 | ||
b0c39dc6 VK |
2230 | static inline bool kvm_check_tsc_unstable(void) |
2231 | { | |
2232 | #ifdef CONFIG_X86_64 | |
2233 | /* | |
2234 | * TSC is marked unstable when we're running on Hyper-V, | |
2235 | * 'TSC page' clocksource is good. | |
2236 | */ | |
b95a8a27 | 2237 | if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK) |
b0c39dc6 VK |
2238 | return false; |
2239 | #endif | |
2240 | return check_tsc_unstable(); | |
2241 | } | |
2242 | ||
0c899c25 | 2243 | static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data) |
99e3e30a ZA |
2244 | { |
2245 | struct kvm *kvm = vcpu->kvm; | |
f38e098f | 2246 | u64 offset, ns, elapsed; |
99e3e30a | 2247 | unsigned long flags; |
b48aa97e | 2248 | bool matched; |
0d3da0d2 | 2249 | bool already_matched; |
c5e8ec8e | 2250 | bool synchronizing = false; |
99e3e30a | 2251 | |
038f8c11 | 2252 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); |
07c1419a | 2253 | offset = kvm_compute_tsc_offset(vcpu, data); |
8171cd68 | 2254 | ns = get_kvmclock_base_ns(); |
f38e098f | 2255 | elapsed = ns - kvm->arch.last_tsc_nsec; |
5d3cb0f6 | 2256 | |
03ba32ca | 2257 | if (vcpu->arch.virtual_tsc_khz) { |
0c899c25 | 2258 | if (data == 0) { |
bd8fab39 DP |
2259 | /* |
2260 | * detection of vcpu initialization -- need to sync | |
2261 | * with other vCPUs. This particularly helps to keep | |
2262 | * kvm_clock stable after CPU hotplug | |
2263 | */ | |
2264 | synchronizing = true; | |
2265 | } else { | |
2266 | u64 tsc_exp = kvm->arch.last_tsc_write + | |
2267 | nsec_to_cycles(vcpu, elapsed); | |
2268 | u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; | |
2269 | /* | |
2270 | * Special case: TSC write with a small delta (1 second) | |
2271 | * of virtual cycle time against real time is | |
2272 | * interpreted as an attempt to synchronize the CPU. | |
2273 | */ | |
2274 | synchronizing = data < tsc_exp + tsc_hz && | |
2275 | data + tsc_hz > tsc_exp; | |
2276 | } | |
c5e8ec8e | 2277 | } |
f38e098f ZA |
2278 | |
2279 | /* | |
5d3cb0f6 ZA |
2280 | * For a reliable TSC, we can match TSC offsets, and for an unstable |
2281 | * TSC, we add elapsed time in this computation. We could let the | |
2282 | * compensation code attempt to catch up if we fall behind, but | |
2283 | * it's better to try to match offsets from the beginning. | |
2284 | */ | |
c5e8ec8e | 2285 | if (synchronizing && |
5d3cb0f6 | 2286 | vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { |
b0c39dc6 | 2287 | if (!kvm_check_tsc_unstable()) { |
e26101b1 | 2288 | offset = kvm->arch.cur_tsc_offset; |
f38e098f | 2289 | } else { |
857e4099 | 2290 | u64 delta = nsec_to_cycles(vcpu, elapsed); |
5d3cb0f6 | 2291 | data += delta; |
07c1419a | 2292 | offset = kvm_compute_tsc_offset(vcpu, data); |
f38e098f | 2293 | } |
b48aa97e | 2294 | matched = true; |
0d3da0d2 | 2295 | already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); |
e26101b1 ZA |
2296 | } else { |
2297 | /* | |
2298 | * We split periods of matched TSC writes into generations. | |
2299 | * For each generation, we track the original measured | |
2300 | * nanosecond time, offset, and write, so if TSCs are in | |
2301 | * sync, we can match exact offset, and if not, we can match | |
4a969980 | 2302 | * exact software computation in compute_guest_tsc() |
e26101b1 ZA |
2303 | * |
2304 | * These values are tracked in kvm->arch.cur_xxx variables. | |
2305 | */ | |
2306 | kvm->arch.cur_tsc_generation++; | |
2307 | kvm->arch.cur_tsc_nsec = ns; | |
2308 | kvm->arch.cur_tsc_write = data; | |
2309 | kvm->arch.cur_tsc_offset = offset; | |
b48aa97e | 2310 | matched = false; |
f38e098f | 2311 | } |
e26101b1 ZA |
2312 | |
2313 | /* | |
2314 | * We also track th most recent recorded KHZ, write and time to | |
2315 | * allow the matching interval to be extended at each write. | |
2316 | */ | |
f38e098f ZA |
2317 | kvm->arch.last_tsc_nsec = ns; |
2318 | kvm->arch.last_tsc_write = data; | |
5d3cb0f6 | 2319 | kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; |
99e3e30a | 2320 | |
b183aa58 | 2321 | vcpu->arch.last_guest_tsc = data; |
e26101b1 ZA |
2322 | |
2323 | /* Keep track of which generation this VCPU has synchronized to */ | |
2324 | vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; | |
2325 | vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; | |
2326 | vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; | |
2327 | ||
a545ab6a | 2328 | kvm_vcpu_write_tsc_offset(vcpu, offset); |
e26101b1 | 2329 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); |
b48aa97e MT |
2330 | |
2331 | spin_lock(&kvm->arch.pvclock_gtod_sync_lock); | |
0d3da0d2 | 2332 | if (!matched) { |
b48aa97e | 2333 | kvm->arch.nr_vcpus_matched_tsc = 0; |
0d3da0d2 TG |
2334 | } else if (!already_matched) { |
2335 | kvm->arch.nr_vcpus_matched_tsc++; | |
2336 | } | |
b48aa97e MT |
2337 | |
2338 | kvm_track_tsc_matching(vcpu); | |
2339 | spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); | |
99e3e30a | 2340 | } |
e26101b1 | 2341 | |
58ea6767 HZ |
2342 | static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, |
2343 | s64 adjustment) | |
2344 | { | |
56ba77a4 | 2345 | u64 tsc_offset = vcpu->arch.l1_tsc_offset; |
326e7425 | 2346 | kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); |
58ea6767 HZ |
2347 | } |
2348 | ||
2349 | static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) | |
2350 | { | |
2351 | if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) | |
2352 | WARN_ON(adjustment < 0); | |
2353 | adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); | |
ea26e4ec | 2354 | adjust_tsc_offset_guest(vcpu, adjustment); |
58ea6767 HZ |
2355 | } |
2356 | ||
d828199e MT |
2357 | #ifdef CONFIG_X86_64 |
2358 | ||
a5a1d1c2 | 2359 | static u64 read_tsc(void) |
d828199e | 2360 | { |
a5a1d1c2 | 2361 | u64 ret = (u64)rdtsc_ordered(); |
03b9730b | 2362 | u64 last = pvclock_gtod_data.clock.cycle_last; |
d828199e MT |
2363 | |
2364 | if (likely(ret >= last)) | |
2365 | return ret; | |
2366 | ||
2367 | /* | |
2368 | * GCC likes to generate cmov here, but this branch is extremely | |
6a6256f9 | 2369 | * predictable (it's just a function of time and the likely is |
d828199e MT |
2370 | * very likely) and there's a data dependence, so force GCC |
2371 | * to generate a branch instead. I don't barrier() because | |
2372 | * we don't actually need a barrier, and if this function | |
2373 | * ever gets inlined it will generate worse code. | |
2374 | */ | |
2375 | asm volatile (""); | |
2376 | return last; | |
2377 | } | |
2378 | ||
53fafdbb MT |
2379 | static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, |
2380 | int *mode) | |
d828199e MT |
2381 | { |
2382 | long v; | |
b0c39dc6 VK |
2383 | u64 tsc_pg_val; |
2384 | ||
53fafdbb | 2385 | switch (clock->vclock_mode) { |
b95a8a27 | 2386 | case VDSO_CLOCKMODE_HVCLOCK: |
b0c39dc6 VK |
2387 | tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), |
2388 | tsc_timestamp); | |
2389 | if (tsc_pg_val != U64_MAX) { | |
2390 | /* TSC page valid */ | |
b95a8a27 | 2391 | *mode = VDSO_CLOCKMODE_HVCLOCK; |
53fafdbb MT |
2392 | v = (tsc_pg_val - clock->cycle_last) & |
2393 | clock->mask; | |
b0c39dc6 VK |
2394 | } else { |
2395 | /* TSC page invalid */ | |
b95a8a27 | 2396 | *mode = VDSO_CLOCKMODE_NONE; |
b0c39dc6 VK |
2397 | } |
2398 | break; | |
b95a8a27 TG |
2399 | case VDSO_CLOCKMODE_TSC: |
2400 | *mode = VDSO_CLOCKMODE_TSC; | |
b0c39dc6 | 2401 | *tsc_timestamp = read_tsc(); |
53fafdbb MT |
2402 | v = (*tsc_timestamp - clock->cycle_last) & |
2403 | clock->mask; | |
b0c39dc6 VK |
2404 | break; |
2405 | default: | |
b95a8a27 | 2406 | *mode = VDSO_CLOCKMODE_NONE; |
b0c39dc6 | 2407 | } |
d828199e | 2408 | |
b95a8a27 | 2409 | if (*mode == VDSO_CLOCKMODE_NONE) |
b0c39dc6 | 2410 | *tsc_timestamp = v = 0; |
d828199e | 2411 | |
53fafdbb | 2412 | return v * clock->mult; |
d828199e MT |
2413 | } |
2414 | ||
53fafdbb | 2415 | static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp) |
d828199e | 2416 | { |
cbcf2dd3 | 2417 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; |
d828199e | 2418 | unsigned long seq; |
d828199e | 2419 | int mode; |
cbcf2dd3 | 2420 | u64 ns; |
d828199e | 2421 | |
d828199e MT |
2422 | do { |
2423 | seq = read_seqcount_begin(>od->seq); | |
917f9475 | 2424 | ns = gtod->raw_clock.base_cycles; |
53fafdbb | 2425 | ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode); |
917f9475 PB |
2426 | ns >>= gtod->raw_clock.shift; |
2427 | ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot)); | |
d828199e | 2428 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); |
cbcf2dd3 | 2429 | *t = ns; |
d828199e MT |
2430 | |
2431 | return mode; | |
2432 | } | |
2433 | ||
899a31f5 | 2434 | static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) |
55dd00a7 MT |
2435 | { |
2436 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
2437 | unsigned long seq; | |
2438 | int mode; | |
2439 | u64 ns; | |
2440 | ||
2441 | do { | |
2442 | seq = read_seqcount_begin(>od->seq); | |
55dd00a7 | 2443 | ts->tv_sec = gtod->wall_time_sec; |
917f9475 | 2444 | ns = gtod->clock.base_cycles; |
53fafdbb | 2445 | ns += vgettsc(>od->clock, tsc_timestamp, &mode); |
55dd00a7 MT |
2446 | ns >>= gtod->clock.shift; |
2447 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); | |
2448 | ||
2449 | ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); | |
2450 | ts->tv_nsec = ns; | |
2451 | ||
2452 | return mode; | |
2453 | } | |
2454 | ||
b0c39dc6 VK |
2455 | /* returns true if host is using TSC based clocksource */ |
2456 | static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) | |
d828199e | 2457 | { |
d828199e | 2458 | /* checked again under seqlock below */ |
b0c39dc6 | 2459 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
d828199e MT |
2460 | return false; |
2461 | ||
53fafdbb | 2462 | return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns, |
b0c39dc6 | 2463 | tsc_timestamp)); |
d828199e | 2464 | } |
55dd00a7 | 2465 | |
b0c39dc6 | 2466 | /* returns true if host is using TSC based clocksource */ |
899a31f5 | 2467 | static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, |
b0c39dc6 | 2468 | u64 *tsc_timestamp) |
55dd00a7 MT |
2469 | { |
2470 | /* checked again under seqlock below */ | |
b0c39dc6 | 2471 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
55dd00a7 MT |
2472 | return false; |
2473 | ||
b0c39dc6 | 2474 | return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); |
55dd00a7 | 2475 | } |
d828199e MT |
2476 | #endif |
2477 | ||
2478 | /* | |
2479 | * | |
b48aa97e MT |
2480 | * Assuming a stable TSC across physical CPUS, and a stable TSC |
2481 | * across virtual CPUs, the following condition is possible. | |
2482 | * Each numbered line represents an event visible to both | |
d828199e MT |
2483 | * CPUs at the next numbered event. |
2484 | * | |
2485 | * "timespecX" represents host monotonic time. "tscX" represents | |
2486 | * RDTSC value. | |
2487 | * | |
2488 | * VCPU0 on CPU0 | VCPU1 on CPU1 | |
2489 | * | |
2490 | * 1. read timespec0,tsc0 | |
2491 | * 2. | timespec1 = timespec0 + N | |
2492 | * | tsc1 = tsc0 + M | |
2493 | * 3. transition to guest | transition to guest | |
2494 | * 4. ret0 = timespec0 + (rdtsc - tsc0) | | |
2495 | * 5. | ret1 = timespec1 + (rdtsc - tsc1) | |
2496 | * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) | |
2497 | * | |
2498 | * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: | |
2499 | * | |
2500 | * - ret0 < ret1 | |
2501 | * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) | |
2502 | * ... | |
2503 | * - 0 < N - M => M < N | |
2504 | * | |
2505 | * That is, when timespec0 != timespec1, M < N. Unfortunately that is not | |
2506 | * always the case (the difference between two distinct xtime instances | |
2507 | * might be smaller then the difference between corresponding TSC reads, | |
2508 | * when updating guest vcpus pvclock areas). | |
2509 | * | |
2510 | * To avoid that problem, do not allow visibility of distinct | |
2511 | * system_timestamp/tsc_timestamp values simultaneously: use a master | |
2512 | * copy of host monotonic time values. Update that master copy | |
2513 | * in lockstep. | |
2514 | * | |
b48aa97e | 2515 | * Rely on synchronization of host TSCs and guest TSCs for monotonicity. |
d828199e MT |
2516 | * |
2517 | */ | |
2518 | ||
2519 | static void pvclock_update_vm_gtod_copy(struct kvm *kvm) | |
2520 | { | |
2521 | #ifdef CONFIG_X86_64 | |
2522 | struct kvm_arch *ka = &kvm->arch; | |
2523 | int vclock_mode; | |
b48aa97e MT |
2524 | bool host_tsc_clocksource, vcpus_matched; |
2525 | ||
2526 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
2527 | atomic_read(&kvm->online_vcpus)); | |
d828199e MT |
2528 | |
2529 | /* | |
2530 | * If the host uses TSC clock, then passthrough TSC as stable | |
2531 | * to the guest. | |
2532 | */ | |
b48aa97e | 2533 | host_tsc_clocksource = kvm_get_time_and_clockread( |
d828199e MT |
2534 | &ka->master_kernel_ns, |
2535 | &ka->master_cycle_now); | |
2536 | ||
16a96021 | 2537 | ka->use_master_clock = host_tsc_clocksource && vcpus_matched |
a826faf1 | 2538 | && !ka->backwards_tsc_observed |
54750f2c | 2539 | && !ka->boot_vcpu_runs_old_kvmclock; |
b48aa97e | 2540 | |
d828199e MT |
2541 | if (ka->use_master_clock) |
2542 | atomic_set(&kvm_guest_has_master_clock, 1); | |
2543 | ||
2544 | vclock_mode = pvclock_gtod_data.clock.vclock_mode; | |
b48aa97e MT |
2545 | trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, |
2546 | vcpus_matched); | |
d828199e MT |
2547 | #endif |
2548 | } | |
2549 | ||
2860c4b1 PB |
2550 | void kvm_make_mclock_inprogress_request(struct kvm *kvm) |
2551 | { | |
2552 | kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); | |
2553 | } | |
2554 | ||
2e762ff7 MT |
2555 | static void kvm_gen_update_masterclock(struct kvm *kvm) |
2556 | { | |
2557 | #ifdef CONFIG_X86_64 | |
2558 | int i; | |
2559 | struct kvm_vcpu *vcpu; | |
2560 | struct kvm_arch *ka = &kvm->arch; | |
2561 | ||
2562 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
2563 | kvm_make_mclock_inprogress_request(kvm); | |
2564 | /* no guest entries from this point */ | |
2565 | pvclock_update_vm_gtod_copy(kvm); | |
2566 | ||
2567 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 2568 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
2e762ff7 MT |
2569 | |
2570 | /* guest entries allowed */ | |
2571 | kvm_for_each_vcpu(i, vcpu, kvm) | |
72875d8a | 2572 | kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); |
2e762ff7 MT |
2573 | |
2574 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
2575 | #endif | |
2576 | } | |
2577 | ||
e891a32e | 2578 | u64 get_kvmclock_ns(struct kvm *kvm) |
108b249c | 2579 | { |
108b249c | 2580 | struct kvm_arch *ka = &kvm->arch; |
8b953440 | 2581 | struct pvclock_vcpu_time_info hv_clock; |
e2c2206a | 2582 | u64 ret; |
108b249c | 2583 | |
8b953440 PB |
2584 | spin_lock(&ka->pvclock_gtod_sync_lock); |
2585 | if (!ka->use_master_clock) { | |
2586 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
8171cd68 | 2587 | return get_kvmclock_base_ns() + ka->kvmclock_offset; |
108b249c PB |
2588 | } |
2589 | ||
8b953440 PB |
2590 | hv_clock.tsc_timestamp = ka->master_cycle_now; |
2591 | hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; | |
2592 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
2593 | ||
e2c2206a WL |
2594 | /* both __this_cpu_read() and rdtsc() should be on the same cpu */ |
2595 | get_cpu(); | |
2596 | ||
e70b57a6 WL |
2597 | if (__this_cpu_read(cpu_tsc_khz)) { |
2598 | kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, | |
2599 | &hv_clock.tsc_shift, | |
2600 | &hv_clock.tsc_to_system_mul); | |
2601 | ret = __pvclock_read_cycles(&hv_clock, rdtsc()); | |
2602 | } else | |
8171cd68 | 2603 | ret = get_kvmclock_base_ns() + ka->kvmclock_offset; |
e2c2206a WL |
2604 | |
2605 | put_cpu(); | |
2606 | ||
2607 | return ret; | |
108b249c PB |
2608 | } |
2609 | ||
0d6dd2ff PB |
2610 | static void kvm_setup_pvclock_page(struct kvm_vcpu *v) |
2611 | { | |
2612 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
2613 | struct pvclock_vcpu_time_info guest_hv_clock; | |
2614 | ||
4e335d9e | 2615 | if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, |
0d6dd2ff PB |
2616 | &guest_hv_clock, sizeof(guest_hv_clock)))) |
2617 | return; | |
2618 | ||
2619 | /* This VCPU is paused, but it's legal for a guest to read another | |
2620 | * VCPU's kvmclock, so we really have to follow the specification where | |
2621 | * it says that version is odd if data is being modified, and even after | |
2622 | * it is consistent. | |
2623 | * | |
2624 | * Version field updates must be kept separate. This is because | |
2625 | * kvm_write_guest_cached might use a "rep movs" instruction, and | |
2626 | * writes within a string instruction are weakly ordered. So there | |
2627 | * are three writes overall. | |
2628 | * | |
2629 | * As a small optimization, only write the version field in the first | |
2630 | * and third write. The vcpu->pv_time cache is still valid, because the | |
2631 | * version field is the first in the struct. | |
2632 | */ | |
2633 | BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); | |
2634 | ||
51c4b8bb LA |
2635 | if (guest_hv_clock.version & 1) |
2636 | ++guest_hv_clock.version; /* first time write, random junk */ | |
2637 | ||
0d6dd2ff | 2638 | vcpu->hv_clock.version = guest_hv_clock.version + 1; |
4e335d9e PB |
2639 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
2640 | &vcpu->hv_clock, | |
2641 | sizeof(vcpu->hv_clock.version)); | |
0d6dd2ff PB |
2642 | |
2643 | smp_wmb(); | |
2644 | ||
2645 | /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ | |
2646 | vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); | |
2647 | ||
2648 | if (vcpu->pvclock_set_guest_stopped_request) { | |
2649 | vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; | |
2650 | vcpu->pvclock_set_guest_stopped_request = false; | |
2651 | } | |
2652 | ||
2653 | trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); | |
2654 | ||
4e335d9e PB |
2655 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
2656 | &vcpu->hv_clock, | |
2657 | sizeof(vcpu->hv_clock)); | |
0d6dd2ff PB |
2658 | |
2659 | smp_wmb(); | |
2660 | ||
2661 | vcpu->hv_clock.version++; | |
4e335d9e PB |
2662 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
2663 | &vcpu->hv_clock, | |
2664 | sizeof(vcpu->hv_clock.version)); | |
0d6dd2ff PB |
2665 | } |
2666 | ||
34c238a1 | 2667 | static int kvm_guest_time_update(struct kvm_vcpu *v) |
18068523 | 2668 | { |
78db6a50 | 2669 | unsigned long flags, tgt_tsc_khz; |
18068523 | 2670 | struct kvm_vcpu_arch *vcpu = &v->arch; |
d828199e | 2671 | struct kvm_arch *ka = &v->kvm->arch; |
f25e656d | 2672 | s64 kernel_ns; |
d828199e | 2673 | u64 tsc_timestamp, host_tsc; |
51d59c6b | 2674 | u8 pvclock_flags; |
d828199e MT |
2675 | bool use_master_clock; |
2676 | ||
2677 | kernel_ns = 0; | |
2678 | host_tsc = 0; | |
18068523 | 2679 | |
d828199e MT |
2680 | /* |
2681 | * If the host uses TSC clock, then passthrough TSC as stable | |
2682 | * to the guest. | |
2683 | */ | |
2684 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
2685 | use_master_clock = ka->use_master_clock; | |
2686 | if (use_master_clock) { | |
2687 | host_tsc = ka->master_cycle_now; | |
2688 | kernel_ns = ka->master_kernel_ns; | |
2689 | } | |
2690 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
c09664bb MT |
2691 | |
2692 | /* Keep irq disabled to prevent changes to the clock */ | |
2693 | local_irq_save(flags); | |
78db6a50 PB |
2694 | tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); |
2695 | if (unlikely(tgt_tsc_khz == 0)) { | |
c09664bb MT |
2696 | local_irq_restore(flags); |
2697 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); | |
2698 | return 1; | |
2699 | } | |
d828199e | 2700 | if (!use_master_clock) { |
4ea1636b | 2701 | host_tsc = rdtsc(); |
8171cd68 | 2702 | kernel_ns = get_kvmclock_base_ns(); |
d828199e MT |
2703 | } |
2704 | ||
4ba76538 | 2705 | tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); |
d828199e | 2706 | |
c285545f ZA |
2707 | /* |
2708 | * We may have to catch up the TSC to match elapsed wall clock | |
2709 | * time for two reasons, even if kvmclock is used. | |
2710 | * 1) CPU could have been running below the maximum TSC rate | |
2711 | * 2) Broken TSC compensation resets the base at each VCPU | |
2712 | * entry to avoid unknown leaps of TSC even when running | |
2713 | * again on the same CPU. This may cause apparent elapsed | |
2714 | * time to disappear, and the guest to stand still or run | |
2715 | * very slowly. | |
2716 | */ | |
2717 | if (vcpu->tsc_catchup) { | |
2718 | u64 tsc = compute_guest_tsc(v, kernel_ns); | |
2719 | if (tsc > tsc_timestamp) { | |
f1e2b260 | 2720 | adjust_tsc_offset_guest(v, tsc - tsc_timestamp); |
c285545f ZA |
2721 | tsc_timestamp = tsc; |
2722 | } | |
50d0a0f9 GH |
2723 | } |
2724 | ||
18068523 GOC |
2725 | local_irq_restore(flags); |
2726 | ||
0d6dd2ff | 2727 | /* With all the info we got, fill in the values */ |
18068523 | 2728 | |
78db6a50 PB |
2729 | if (kvm_has_tsc_control) |
2730 | tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz); | |
2731 | ||
2732 | if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { | |
3ae13faa | 2733 | kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, |
5f4e3f88 ZA |
2734 | &vcpu->hv_clock.tsc_shift, |
2735 | &vcpu->hv_clock.tsc_to_system_mul); | |
78db6a50 | 2736 | vcpu->hw_tsc_khz = tgt_tsc_khz; |
8cfdc000 ZA |
2737 | } |
2738 | ||
1d5f066e | 2739 | vcpu->hv_clock.tsc_timestamp = tsc_timestamp; |
759379dd | 2740 | vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; |
28e4639a | 2741 | vcpu->last_guest_tsc = tsc_timestamp; |
51d59c6b | 2742 | |
d828199e | 2743 | /* If the host uses TSC clocksource, then it is stable */ |
0d6dd2ff | 2744 | pvclock_flags = 0; |
d828199e MT |
2745 | if (use_master_clock) |
2746 | pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; | |
2747 | ||
78c0337a MT |
2748 | vcpu->hv_clock.flags = pvclock_flags; |
2749 | ||
095cf55d PB |
2750 | if (vcpu->pv_time_enabled) |
2751 | kvm_setup_pvclock_page(v); | |
2752 | if (v == kvm_get_vcpu(v->kvm, 0)) | |
2753 | kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); | |
8cfdc000 | 2754 | return 0; |
c8076604 GH |
2755 | } |
2756 | ||
0061d53d MT |
2757 | /* |
2758 | * kvmclock updates which are isolated to a given vcpu, such as | |
2759 | * vcpu->cpu migration, should not allow system_timestamp from | |
2760 | * the rest of the vcpus to remain static. Otherwise ntp frequency | |
2761 | * correction applies to one vcpu's system_timestamp but not | |
2762 | * the others. | |
2763 | * | |
2764 | * So in those cases, request a kvmclock update for all vcpus. | |
7e44e449 AJ |
2765 | * We need to rate-limit these requests though, as they can |
2766 | * considerably slow guests that have a large number of vcpus. | |
2767 | * The time for a remote vcpu to update its kvmclock is bound | |
2768 | * by the delay we use to rate-limit the updates. | |
0061d53d MT |
2769 | */ |
2770 | ||
7e44e449 AJ |
2771 | #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) |
2772 | ||
2773 | static void kvmclock_update_fn(struct work_struct *work) | |
0061d53d MT |
2774 | { |
2775 | int i; | |
7e44e449 AJ |
2776 | struct delayed_work *dwork = to_delayed_work(work); |
2777 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
2778 | kvmclock_update_work); | |
2779 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
0061d53d MT |
2780 | struct kvm_vcpu *vcpu; |
2781 | ||
2782 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
105b21bb | 2783 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0061d53d MT |
2784 | kvm_vcpu_kick(vcpu); |
2785 | } | |
2786 | } | |
2787 | ||
7e44e449 AJ |
2788 | static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) |
2789 | { | |
2790 | struct kvm *kvm = v->kvm; | |
2791 | ||
105b21bb | 2792 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); |
7e44e449 AJ |
2793 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, |
2794 | KVMCLOCK_UPDATE_DELAY); | |
2795 | } | |
2796 | ||
332967a3 AJ |
2797 | #define KVMCLOCK_SYNC_PERIOD (300 * HZ) |
2798 | ||
2799 | static void kvmclock_sync_fn(struct work_struct *work) | |
2800 | { | |
2801 | struct delayed_work *dwork = to_delayed_work(work); | |
2802 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
2803 | kvmclock_sync_work); | |
2804 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
2805 | ||
630994b3 MT |
2806 | if (!kvmclock_periodic_sync) |
2807 | return; | |
2808 | ||
332967a3 AJ |
2809 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); |
2810 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
2811 | KVMCLOCK_SYNC_PERIOD); | |
2812 | } | |
2813 | ||
191c8137 BP |
2814 | /* |
2815 | * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. | |
2816 | */ | |
2817 | static bool can_set_mci_status(struct kvm_vcpu *vcpu) | |
2818 | { | |
2819 | /* McStatusWrEn enabled? */ | |
23493d0a | 2820 | if (guest_cpuid_is_amd_or_hygon(vcpu)) |
191c8137 BP |
2821 | return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); |
2822 | ||
2823 | return false; | |
2824 | } | |
2825 | ||
9ffd986c | 2826 | static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 2827 | { |
890ca9ae HY |
2828 | u64 mcg_cap = vcpu->arch.mcg_cap; |
2829 | unsigned bank_num = mcg_cap & 0xff; | |
9ffd986c WL |
2830 | u32 msr = msr_info->index; |
2831 | u64 data = msr_info->data; | |
890ca9ae | 2832 | |
15c4a640 | 2833 | switch (msr) { |
15c4a640 | 2834 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 2835 | vcpu->arch.mcg_status = data; |
15c4a640 | 2836 | break; |
c7ac679c | 2837 | case MSR_IA32_MCG_CTL: |
44883f01 PB |
2838 | if (!(mcg_cap & MCG_CTL_P) && |
2839 | (data || !msr_info->host_initiated)) | |
890ca9ae HY |
2840 | return 1; |
2841 | if (data != 0 && data != ~(u64)0) | |
44883f01 | 2842 | return 1; |
890ca9ae HY |
2843 | vcpu->arch.mcg_ctl = data; |
2844 | break; | |
2845 | default: | |
2846 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 2847 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
6ec4c5ee MP |
2848 | u32 offset = array_index_nospec( |
2849 | msr - MSR_IA32_MC0_CTL, | |
2850 | MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); | |
2851 | ||
114be429 AP |
2852 | /* only 0 or all 1s can be written to IA32_MCi_CTL |
2853 | * some Linux kernels though clear bit 10 in bank 4 to | |
2854 | * workaround a BIOS/GART TBL issue on AMD K8s, ignore | |
2855 | * this to avoid an uncatched #GP in the guest | |
2856 | */ | |
890ca9ae | 2857 | if ((offset & 0x3) == 0 && |
114be429 | 2858 | data != 0 && (data | (1 << 10)) != ~(u64)0) |
890ca9ae | 2859 | return -1; |
191c8137 BP |
2860 | |
2861 | /* MCi_STATUS */ | |
9ffd986c | 2862 | if (!msr_info->host_initiated && |
191c8137 BP |
2863 | (offset & 0x3) == 1 && data != 0) { |
2864 | if (!can_set_mci_status(vcpu)) | |
2865 | return -1; | |
2866 | } | |
2867 | ||
890ca9ae HY |
2868 | vcpu->arch.mce_banks[offset] = data; |
2869 | break; | |
2870 | } | |
2871 | return 1; | |
2872 | } | |
2873 | return 0; | |
2874 | } | |
2875 | ||
ffde22ac ES |
2876 | static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) |
2877 | { | |
2878 | struct kvm *kvm = vcpu->kvm; | |
2879 | int lm = is_long_mode(vcpu); | |
2880 | u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 | |
2881 | : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; | |
2882 | u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 | |
2883 | : kvm->arch.xen_hvm_config.blob_size_32; | |
2884 | u32 page_num = data & ~PAGE_MASK; | |
2885 | u64 page_addr = data & PAGE_MASK; | |
2886 | u8 *page; | |
ffde22ac | 2887 | |
ffde22ac | 2888 | if (page_num >= blob_size) |
36385ccc ML |
2889 | return 1; |
2890 | ||
ff5c2c03 | 2891 | page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); |
36385ccc ML |
2892 | if (IS_ERR(page)) |
2893 | return PTR_ERR(page); | |
2894 | ||
2895 | if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) { | |
2896 | kfree(page); | |
2897 | return 1; | |
ff5c2c03 | 2898 | } |
36385ccc | 2899 | return 0; |
ffde22ac ES |
2900 | } |
2901 | ||
2635b5c4 VK |
2902 | static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu) |
2903 | { | |
2904 | u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT; | |
2905 | ||
2906 | return (vcpu->arch.apf.msr_en_val & mask) == mask; | |
2907 | } | |
2908 | ||
344d9588 GN |
2909 | static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) |
2910 | { | |
2911 | gpa_t gpa = data & ~0x3f; | |
2912 | ||
2635b5c4 VK |
2913 | /* Bits 4:5 are reserved, Should be zero */ |
2914 | if (data & 0x30) | |
344d9588 GN |
2915 | return 1; |
2916 | ||
66570e96 OU |
2917 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) && |
2918 | (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT)) | |
2919 | return 1; | |
2920 | ||
2921 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) && | |
2922 | (data & KVM_ASYNC_PF_DELIVERY_AS_INT)) | |
2923 | return 1; | |
2924 | ||
9d3c447c | 2925 | if (!lapic_in_kernel(vcpu)) |
d831de17 | 2926 | return data ? 1 : 0; |
9d3c447c | 2927 | |
2635b5c4 | 2928 | vcpu->arch.apf.msr_en_val = data; |
344d9588 | 2929 | |
2635b5c4 | 2930 | if (!kvm_pv_async_pf_enabled(vcpu)) { |
344d9588 GN |
2931 | kvm_clear_async_pf_completion_queue(vcpu); |
2932 | kvm_async_pf_hash_reset(vcpu); | |
2933 | return 0; | |
2934 | } | |
2935 | ||
4e335d9e | 2936 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, |
68fd66f1 | 2937 | sizeof(u64))) |
344d9588 GN |
2938 | return 1; |
2939 | ||
6adba527 | 2940 | vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); |
52a5c155 | 2941 | vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; |
2635b5c4 | 2942 | |
344d9588 | 2943 | kvm_async_pf_wakeup_all(vcpu); |
2635b5c4 VK |
2944 | |
2945 | return 0; | |
2946 | } | |
2947 | ||
2948 | static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data) | |
2949 | { | |
2950 | /* Bits 8-63 are reserved */ | |
2951 | if (data >> 8) | |
2952 | return 1; | |
2953 | ||
2954 | if (!lapic_in_kernel(vcpu)) | |
2955 | return 1; | |
2956 | ||
2957 | vcpu->arch.apf.msr_int_val = data; | |
2958 | ||
2959 | vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK; | |
2960 | ||
344d9588 GN |
2961 | return 0; |
2962 | } | |
2963 | ||
12f9a48f GC |
2964 | static void kvmclock_reset(struct kvm_vcpu *vcpu) |
2965 | { | |
0b79459b | 2966 | vcpu->arch.pv_time_enabled = false; |
49dedf0d | 2967 | vcpu->arch.time = 0; |
12f9a48f GC |
2968 | } |
2969 | ||
7780938c | 2970 | static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu) |
f38a7b75 WL |
2971 | { |
2972 | ++vcpu->stat.tlb_flush; | |
7780938c | 2973 | kvm_x86_ops.tlb_flush_all(vcpu); |
f38a7b75 WL |
2974 | } |
2975 | ||
0baedd79 VK |
2976 | static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu) |
2977 | { | |
2978 | ++vcpu->stat.tlb_flush; | |
2979 | kvm_x86_ops.tlb_flush_guest(vcpu); | |
2980 | } | |
2981 | ||
c9aaa895 GC |
2982 | static void record_steal_time(struct kvm_vcpu *vcpu) |
2983 | { | |
b0431382 BO |
2984 | struct kvm_host_map map; |
2985 | struct kvm_steal_time *st; | |
2986 | ||
c9aaa895 GC |
2987 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) |
2988 | return; | |
2989 | ||
b0431382 BO |
2990 | /* -EAGAIN is returned in atomic context so we can just return. */ |
2991 | if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, | |
2992 | &map, &vcpu->arch.st.cache, false)) | |
c9aaa895 GC |
2993 | return; |
2994 | ||
b0431382 BO |
2995 | st = map.hva + |
2996 | offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); | |
2997 | ||
f38a7b75 WL |
2998 | /* |
2999 | * Doing a TLB flush here, on the guest's behalf, can avoid | |
3000 | * expensive IPIs. | |
3001 | */ | |
66570e96 OU |
3002 | if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) { |
3003 | trace_kvm_pv_tlb_flush(vcpu->vcpu_id, | |
3004 | st->preempted & KVM_VCPU_FLUSH_TLB); | |
3005 | if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB) | |
3006 | kvm_vcpu_flush_tlb_guest(vcpu); | |
3007 | } | |
0b9f6c46 | 3008 | |
a6bd811f | 3009 | vcpu->arch.st.preempted = 0; |
35f3fae1 | 3010 | |
b0431382 BO |
3011 | if (st->version & 1) |
3012 | st->version += 1; /* first time write, random junk */ | |
35f3fae1 | 3013 | |
b0431382 | 3014 | st->version += 1; |
35f3fae1 WL |
3015 | |
3016 | smp_wmb(); | |
3017 | ||
b0431382 | 3018 | st->steal += current->sched_info.run_delay - |
c54cdf14 LC |
3019 | vcpu->arch.st.last_steal; |
3020 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
35f3fae1 | 3021 | |
35f3fae1 WL |
3022 | smp_wmb(); |
3023 | ||
b0431382 | 3024 | st->version += 1; |
c9aaa895 | 3025 | |
b0431382 | 3026 | kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false); |
c9aaa895 GC |
3027 | } |
3028 | ||
8fe8ab46 | 3029 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 3030 | { |
5753785f | 3031 | bool pr = false; |
8fe8ab46 WA |
3032 | u32 msr = msr_info->index; |
3033 | u64 data = msr_info->data; | |
5753785f | 3034 | |
15c4a640 | 3035 | switch (msr) { |
2e32b719 | 3036 | case MSR_AMD64_NB_CFG: |
2e32b719 BP |
3037 | case MSR_IA32_UCODE_WRITE: |
3038 | case MSR_VM_HSAVE_PA: | |
3039 | case MSR_AMD64_PATCH_LOADER: | |
3040 | case MSR_AMD64_BU_CFG2: | |
405a353a | 3041 | case MSR_AMD64_DC_CFG: |
0e1b869f | 3042 | case MSR_F15H_EX_CFG: |
2e32b719 BP |
3043 | break; |
3044 | ||
518e7b94 WL |
3045 | case MSR_IA32_UCODE_REV: |
3046 | if (msr_info->host_initiated) | |
3047 | vcpu->arch.microcode_version = data; | |
3048 | break; | |
0cf9135b SC |
3049 | case MSR_IA32_ARCH_CAPABILITIES: |
3050 | if (!msr_info->host_initiated) | |
3051 | return 1; | |
3052 | vcpu->arch.arch_capabilities = data; | |
3053 | break; | |
d574c539 VK |
3054 | case MSR_IA32_PERF_CAPABILITIES: { |
3055 | struct kvm_msr_entry msr_ent = {.index = msr, .data = 0}; | |
3056 | ||
3057 | if (!msr_info->host_initiated) | |
3058 | return 1; | |
3059 | if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM) && kvm_get_msr_feature(&msr_ent)) | |
3060 | return 1; | |
3061 | if (data & ~msr_ent.data) | |
3062 | return 1; | |
3063 | ||
3064 | vcpu->arch.perf_capabilities = data; | |
3065 | ||
3066 | return 0; | |
3067 | } | |
15c4a640 | 3068 | case MSR_EFER: |
11988499 | 3069 | return set_efer(vcpu, msr_info); |
8f1589d9 AP |
3070 | case MSR_K7_HWCR: |
3071 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
82494028 | 3072 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ |
a223c313 | 3073 | data &= ~(u64)0x8; /* ignore TLB cache disable */ |
191c8137 BP |
3074 | |
3075 | /* Handle McStatusWrEn */ | |
3076 | if (data == BIT_ULL(18)) { | |
3077 | vcpu->arch.msr_hwcr = data; | |
3078 | } else if (data != 0) { | |
a737f256 CD |
3079 | vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", |
3080 | data); | |
8f1589d9 AP |
3081 | return 1; |
3082 | } | |
15c4a640 | 3083 | break; |
f7c6d140 AP |
3084 | case MSR_FAM10H_MMIO_CONF_BASE: |
3085 | if (data != 0) { | |
a737f256 CD |
3086 | vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " |
3087 | "0x%llx\n", data); | |
f7c6d140 AP |
3088 | return 1; |
3089 | } | |
15c4a640 | 3090 | break; |
9ba075a6 | 3091 | case 0x200 ... 0x2ff: |
ff53604b | 3092 | return kvm_mtrr_set_msr(vcpu, msr, data); |
15c4a640 | 3093 | case MSR_IA32_APICBASE: |
58cb628d | 3094 | return kvm_set_apic_base(vcpu, msr_info); |
bf10bd0b | 3095 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: |
0105d1a5 | 3096 | return kvm_x2apic_msr_write(vcpu, msr, data); |
a3e06bbe LJ |
3097 | case MSR_IA32_TSCDEADLINE: |
3098 | kvm_set_lapic_tscdeadline_msr(vcpu, data); | |
3099 | break; | |
ba904635 | 3100 | case MSR_IA32_TSC_ADJUST: |
d6321d49 | 3101 | if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { |
ba904635 | 3102 | if (!msr_info->host_initiated) { |
d913b904 | 3103 | s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; |
d7add054 | 3104 | adjust_tsc_offset_guest(vcpu, adj); |
ba904635 WA |
3105 | } |
3106 | vcpu->arch.ia32_tsc_adjust_msr = data; | |
3107 | } | |
3108 | break; | |
15c4a640 | 3109 | case MSR_IA32_MISC_ENABLE: |
511a8556 WL |
3110 | if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && |
3111 | ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { | |
3112 | if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) | |
3113 | return 1; | |
3114 | vcpu->arch.ia32_misc_enable_msr = data; | |
aedbaf4f | 3115 | kvm_update_cpuid_runtime(vcpu); |
511a8556 WL |
3116 | } else { |
3117 | vcpu->arch.ia32_misc_enable_msr = data; | |
3118 | } | |
15c4a640 | 3119 | break; |
64d60670 PB |
3120 | case MSR_IA32_SMBASE: |
3121 | if (!msr_info->host_initiated) | |
3122 | return 1; | |
3123 | vcpu->arch.smbase = data; | |
3124 | break; | |
73f624f4 PB |
3125 | case MSR_IA32_POWER_CTL: |
3126 | vcpu->arch.msr_ia32_power_ctl = data; | |
3127 | break; | |
dd259935 | 3128 | case MSR_IA32_TSC: |
0c899c25 PB |
3129 | if (msr_info->host_initiated) { |
3130 | kvm_synchronize_tsc(vcpu, data); | |
3131 | } else { | |
3132 | u64 adj = kvm_compute_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset; | |
3133 | adjust_tsc_offset_guest(vcpu, adj); | |
3134 | vcpu->arch.ia32_tsc_adjust_msr += adj; | |
3135 | } | |
dd259935 | 3136 | break; |
864e2ab2 AL |
3137 | case MSR_IA32_XSS: |
3138 | if (!msr_info->host_initiated && | |
3139 | !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) | |
3140 | return 1; | |
3141 | /* | |
a1bead2a SC |
3142 | * KVM supports exposing PT to the guest, but does not support |
3143 | * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than | |
3144 | * XSAVES/XRSTORS to save/restore PT MSRs. | |
864e2ab2 | 3145 | */ |
408e9a31 | 3146 | if (data & ~supported_xss) |
864e2ab2 AL |
3147 | return 1; |
3148 | vcpu->arch.ia32_xss = data; | |
3149 | break; | |
52797bf9 LA |
3150 | case MSR_SMI_COUNT: |
3151 | if (!msr_info->host_initiated) | |
3152 | return 1; | |
3153 | vcpu->arch.smi_count = data; | |
3154 | break; | |
11c6bffa | 3155 | case MSR_KVM_WALL_CLOCK_NEW: |
66570e96 OU |
3156 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3157 | return 1; | |
3158 | ||
3159 | kvm_write_wall_clock(vcpu->kvm, data); | |
3160 | break; | |
18068523 | 3161 | case MSR_KVM_WALL_CLOCK: |
66570e96 OU |
3162 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3163 | return 1; | |
3164 | ||
18068523 GOC |
3165 | kvm_write_wall_clock(vcpu->kvm, data); |
3166 | break; | |
11c6bffa | 3167 | case MSR_KVM_SYSTEM_TIME_NEW: |
66570e96 OU |
3168 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3169 | return 1; | |
3170 | ||
5b9bb0eb OU |
3171 | kvm_write_system_time(vcpu, data, false, msr_info->host_initiated); |
3172 | break; | |
3173 | case MSR_KVM_SYSTEM_TIME: | |
66570e96 OU |
3174 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3175 | return 1; | |
3176 | ||
3177 | kvm_write_system_time(vcpu, data, true, msr_info->host_initiated); | |
18068523 | 3178 | break; |
344d9588 | 3179 | case MSR_KVM_ASYNC_PF_EN: |
66570e96 OU |
3180 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3181 | return 1; | |
3182 | ||
344d9588 GN |
3183 | if (kvm_pv_enable_async_pf(vcpu, data)) |
3184 | return 1; | |
3185 | break; | |
2635b5c4 | 3186 | case MSR_KVM_ASYNC_PF_INT: |
66570e96 OU |
3187 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
3188 | return 1; | |
3189 | ||
2635b5c4 VK |
3190 | if (kvm_pv_enable_async_pf_int(vcpu, data)) |
3191 | return 1; | |
3192 | break; | |
557a961a | 3193 | case MSR_KVM_ASYNC_PF_ACK: |
66570e96 OU |
3194 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3195 | return 1; | |
557a961a VK |
3196 | if (data & 0x1) { |
3197 | vcpu->arch.apf.pageready_pending = false; | |
3198 | kvm_check_async_pf_completion(vcpu); | |
3199 | } | |
3200 | break; | |
c9aaa895 | 3201 | case MSR_KVM_STEAL_TIME: |
66570e96 OU |
3202 | if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) |
3203 | return 1; | |
c9aaa895 GC |
3204 | |
3205 | if (unlikely(!sched_info_on())) | |
3206 | return 1; | |
3207 | ||
3208 | if (data & KVM_STEAL_RESERVED_MASK) | |
3209 | return 1; | |
3210 | ||
c9aaa895 GC |
3211 | vcpu->arch.st.msr_val = data; |
3212 | ||
3213 | if (!(data & KVM_MSR_ENABLED)) | |
3214 | break; | |
3215 | ||
c9aaa895 GC |
3216 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
3217 | ||
3218 | break; | |
ae7a2a3f | 3219 | case MSR_KVM_PV_EOI_EN: |
66570e96 OU |
3220 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) |
3221 | return 1; | |
3222 | ||
72bbf935 | 3223 | if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8))) |
ae7a2a3f MT |
3224 | return 1; |
3225 | break; | |
c9aaa895 | 3226 | |
2d5ba19b | 3227 | case MSR_KVM_POLL_CONTROL: |
66570e96 OU |
3228 | if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) |
3229 | return 1; | |
3230 | ||
2d5ba19b MT |
3231 | /* only enable bit supported */ |
3232 | if (data & (-1ULL << 1)) | |
3233 | return 1; | |
3234 | ||
3235 | vcpu->arch.msr_kvm_poll_control = data; | |
3236 | break; | |
3237 | ||
890ca9ae HY |
3238 | case MSR_IA32_MCG_CTL: |
3239 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 3240 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
9ffd986c | 3241 | return set_msr_mce(vcpu, msr_info); |
71db6023 | 3242 | |
6912ac32 WH |
3243 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: |
3244 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
df561f66 GS |
3245 | pr = true; |
3246 | fallthrough; | |
6912ac32 WH |
3247 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: |
3248 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 3249 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 3250 | return kvm_pmu_set_msr(vcpu, msr_info); |
5753785f GN |
3251 | |
3252 | if (pr || data != 0) | |
a737f256 CD |
3253 | vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " |
3254 | "0x%x data 0x%llx\n", msr, data); | |
5753785f | 3255 | break; |
84e0cefa JS |
3256 | case MSR_K7_CLK_CTL: |
3257 | /* | |
3258 | * Ignore all writes to this no longer documented MSR. | |
3259 | * Writes are only relevant for old K7 processors, | |
3260 | * all pre-dating SVM, but a recommended workaround from | |
4a969980 | 3261 | * AMD for these chips. It is possible to specify the |
84e0cefa JS |
3262 | * affected processor models on the command line, hence |
3263 | * the need to ignore the workaround. | |
3264 | */ | |
3265 | break; | |
55cd8e5a | 3266 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
f97f5a56 JD |
3267 | case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: |
3268 | case HV_X64_MSR_SYNDBG_OPTIONS: | |
e7d9513b AS |
3269 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
3270 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 3271 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
3272 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
3273 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
3274 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
e7d9513b AS |
3275 | return kvm_hv_set_msr_common(vcpu, msr, data, |
3276 | msr_info->host_initiated); | |
91c9c3ed | 3277 | case MSR_IA32_BBL_CR_CTL3: |
3278 | /* Drop writes to this legacy MSR -- see rdmsr | |
3279 | * counterpart for further detail. | |
3280 | */ | |
fab0aa3b EM |
3281 | if (report_ignored_msrs) |
3282 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", | |
3283 | msr, data); | |
91c9c3ed | 3284 | break; |
2b036c6b | 3285 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 3286 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
3287 | return 1; |
3288 | vcpu->arch.osvw.length = data; | |
3289 | break; | |
3290 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 3291 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
3292 | return 1; |
3293 | vcpu->arch.osvw.status = data; | |
3294 | break; | |
db2336a8 KH |
3295 | case MSR_PLATFORM_INFO: |
3296 | if (!msr_info->host_initiated || | |
db2336a8 KH |
3297 | (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && |
3298 | cpuid_fault_enabled(vcpu))) | |
3299 | return 1; | |
3300 | vcpu->arch.msr_platform_info = data; | |
3301 | break; | |
3302 | case MSR_MISC_FEATURES_ENABLES: | |
3303 | if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || | |
3304 | (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && | |
3305 | !supports_cpuid_fault(vcpu))) | |
3306 | return 1; | |
3307 | vcpu->arch.msr_misc_features_enables = data; | |
3308 | break; | |
15c4a640 | 3309 | default: |
ffde22ac ES |
3310 | if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) |
3311 | return xen_hvm_config(vcpu, data); | |
c6702c9d | 3312 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 3313 | return kvm_pmu_set_msr(vcpu, msr_info); |
6abe9c13 | 3314 | return KVM_MSR_RET_INVALID; |
15c4a640 CO |
3315 | } |
3316 | return 0; | |
3317 | } | |
3318 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
3319 | ||
44883f01 | 3320 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) |
15c4a640 CO |
3321 | { |
3322 | u64 data; | |
890ca9ae HY |
3323 | u64 mcg_cap = vcpu->arch.mcg_cap; |
3324 | unsigned bank_num = mcg_cap & 0xff; | |
15c4a640 CO |
3325 | |
3326 | switch (msr) { | |
15c4a640 CO |
3327 | case MSR_IA32_P5_MC_ADDR: |
3328 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
3329 | data = 0; |
3330 | break; | |
15c4a640 | 3331 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
3332 | data = vcpu->arch.mcg_cap; |
3333 | break; | |
c7ac679c | 3334 | case MSR_IA32_MCG_CTL: |
44883f01 | 3335 | if (!(mcg_cap & MCG_CTL_P) && !host) |
890ca9ae HY |
3336 | return 1; |
3337 | data = vcpu->arch.mcg_ctl; | |
3338 | break; | |
3339 | case MSR_IA32_MCG_STATUS: | |
3340 | data = vcpu->arch.mcg_status; | |
3341 | break; | |
3342 | default: | |
3343 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 3344 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
6ec4c5ee MP |
3345 | u32 offset = array_index_nospec( |
3346 | msr - MSR_IA32_MC0_CTL, | |
3347 | MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); | |
3348 | ||
890ca9ae HY |
3349 | data = vcpu->arch.mce_banks[offset]; |
3350 | break; | |
3351 | } | |
3352 | return 1; | |
3353 | } | |
3354 | *pdata = data; | |
3355 | return 0; | |
3356 | } | |
3357 | ||
609e36d3 | 3358 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
890ca9ae | 3359 | { |
609e36d3 | 3360 | switch (msr_info->index) { |
890ca9ae | 3361 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 3362 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
3363 | case MSR_IA32_LASTBRANCHFROMIP: |
3364 | case MSR_IA32_LASTBRANCHTOIP: | |
3365 | case MSR_IA32_LASTINTFROMIP: | |
3366 | case MSR_IA32_LASTINTTOIP: | |
60af2ecd | 3367 | case MSR_K8_SYSCFG: |
3afb1121 PB |
3368 | case MSR_K8_TSEG_ADDR: |
3369 | case MSR_K8_TSEG_MASK: | |
61a6bd67 | 3370 | case MSR_VM_HSAVE_PA: |
1fdbd48c | 3371 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 3372 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 3373 | case MSR_FAM10H_MMIO_CONF_BASE: |
2e32b719 | 3374 | case MSR_AMD64_BU_CFG2: |
0c2df2a1 | 3375 | case MSR_IA32_PERF_CTL: |
405a353a | 3376 | case MSR_AMD64_DC_CFG: |
0e1b869f | 3377 | case MSR_F15H_EX_CFG: |
2ca1a06a VS |
3378 | /* |
3379 | * Intel Sandy Bridge CPUs must support the RAPL (running average power | |
3380 | * limit) MSRs. Just return 0, as we do not want to expose the host | |
3381 | * data here. Do not conditionalize this on CPUID, as KVM does not do | |
3382 | * so for existing CPU-specific MSRs. | |
3383 | */ | |
3384 | case MSR_RAPL_POWER_UNIT: | |
3385 | case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */ | |
3386 | case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */ | |
3387 | case MSR_PKG_ENERGY_STATUS: /* Total package */ | |
3388 | case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */ | |
609e36d3 | 3389 | msr_info->data = 0; |
15c4a640 | 3390 | break; |
c51eb52b | 3391 | case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: |
6912ac32 WH |
3392 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: |
3393 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: | |
3394 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
3395 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 3396 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
cbd71758 | 3397 | return kvm_pmu_get_msr(vcpu, msr_info); |
609e36d3 | 3398 | msr_info->data = 0; |
5753785f | 3399 | break; |
742bc670 | 3400 | case MSR_IA32_UCODE_REV: |
518e7b94 | 3401 | msr_info->data = vcpu->arch.microcode_version; |
742bc670 | 3402 | break; |
0cf9135b SC |
3403 | case MSR_IA32_ARCH_CAPABILITIES: |
3404 | if (!msr_info->host_initiated && | |
3405 | !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) | |
3406 | return 1; | |
3407 | msr_info->data = vcpu->arch.arch_capabilities; | |
3408 | break; | |
d574c539 VK |
3409 | case MSR_IA32_PERF_CAPABILITIES: |
3410 | if (!msr_info->host_initiated && | |
3411 | !guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) | |
3412 | return 1; | |
3413 | msr_info->data = vcpu->arch.perf_capabilities; | |
3414 | break; | |
73f624f4 PB |
3415 | case MSR_IA32_POWER_CTL: |
3416 | msr_info->data = vcpu->arch.msr_ia32_power_ctl; | |
3417 | break; | |
cc5b54dd ML |
3418 | case MSR_IA32_TSC: { |
3419 | /* | |
3420 | * Intel SDM states that MSR_IA32_TSC read adds the TSC offset | |
3421 | * even when not intercepted. AMD manual doesn't explicitly | |
3422 | * state this but appears to behave the same. | |
3423 | * | |
ee6fa053 | 3424 | * On userspace reads and writes, however, we unconditionally |
c0623f5e | 3425 | * return L1's TSC value to ensure backwards-compatible |
ee6fa053 | 3426 | * behavior for migration. |
cc5b54dd ML |
3427 | */ |
3428 | u64 tsc_offset = msr_info->host_initiated ? vcpu->arch.l1_tsc_offset : | |
3429 | vcpu->arch.tsc_offset; | |
3430 | ||
3431 | msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + tsc_offset; | |
dd259935 | 3432 | break; |
cc5b54dd | 3433 | } |
9ba075a6 | 3434 | case MSR_MTRRcap: |
9ba075a6 | 3435 | case 0x200 ... 0x2ff: |
ff53604b | 3436 | return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); |
15c4a640 | 3437 | case 0xcd: /* fsb frequency */ |
609e36d3 | 3438 | msr_info->data = 3; |
15c4a640 | 3439 | break; |
7b914098 JS |
3440 | /* |
3441 | * MSR_EBC_FREQUENCY_ID | |
3442 | * Conservative value valid for even the basic CPU models. | |
3443 | * Models 0,1: 000 in bits 23:21 indicating a bus speed of | |
3444 | * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, | |
3445 | * and 266MHz for model 3, or 4. Set Core Clock | |
3446 | * Frequency to System Bus Frequency Ratio to 1 (bits | |
3447 | * 31:24) even though these are only valid for CPU | |
3448 | * models > 2, however guests may end up dividing or | |
3449 | * multiplying by zero otherwise. | |
3450 | */ | |
3451 | case MSR_EBC_FREQUENCY_ID: | |
609e36d3 | 3452 | msr_info->data = 1 << 24; |
7b914098 | 3453 | break; |
15c4a640 | 3454 | case MSR_IA32_APICBASE: |
609e36d3 | 3455 | msr_info->data = kvm_get_apic_base(vcpu); |
15c4a640 | 3456 | break; |
bf10bd0b | 3457 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: |
609e36d3 | 3458 | return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); |
a3e06bbe | 3459 | case MSR_IA32_TSCDEADLINE: |
609e36d3 | 3460 | msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); |
a3e06bbe | 3461 | break; |
ba904635 | 3462 | case MSR_IA32_TSC_ADJUST: |
609e36d3 | 3463 | msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; |
ba904635 | 3464 | break; |
15c4a640 | 3465 | case MSR_IA32_MISC_ENABLE: |
609e36d3 | 3466 | msr_info->data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 3467 | break; |
64d60670 PB |
3468 | case MSR_IA32_SMBASE: |
3469 | if (!msr_info->host_initiated) | |
3470 | return 1; | |
3471 | msr_info->data = vcpu->arch.smbase; | |
15c4a640 | 3472 | break; |
52797bf9 LA |
3473 | case MSR_SMI_COUNT: |
3474 | msr_info->data = vcpu->arch.smi_count; | |
3475 | break; | |
847f0ad8 AG |
3476 | case MSR_IA32_PERF_STATUS: |
3477 | /* TSC increment by tick */ | |
609e36d3 | 3478 | msr_info->data = 1000ULL; |
847f0ad8 | 3479 | /* CPU multiplier */ |
b0996ae4 | 3480 | msr_info->data |= (((uint64_t)4ULL) << 40); |
847f0ad8 | 3481 | break; |
15c4a640 | 3482 | case MSR_EFER: |
609e36d3 | 3483 | msr_info->data = vcpu->arch.efer; |
15c4a640 | 3484 | break; |
18068523 | 3485 | case MSR_KVM_WALL_CLOCK: |
1930e5dd OU |
3486 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3487 | return 1; | |
3488 | ||
3489 | msr_info->data = vcpu->kvm->arch.wall_clock; | |
3490 | break; | |
11c6bffa | 3491 | case MSR_KVM_WALL_CLOCK_NEW: |
1930e5dd OU |
3492 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3493 | return 1; | |
3494 | ||
609e36d3 | 3495 | msr_info->data = vcpu->kvm->arch.wall_clock; |
18068523 GOC |
3496 | break; |
3497 | case MSR_KVM_SYSTEM_TIME: | |
1930e5dd OU |
3498 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3499 | return 1; | |
3500 | ||
3501 | msr_info->data = vcpu->arch.time; | |
3502 | break; | |
11c6bffa | 3503 | case MSR_KVM_SYSTEM_TIME_NEW: |
1930e5dd OU |
3504 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3505 | return 1; | |
3506 | ||
609e36d3 | 3507 | msr_info->data = vcpu->arch.time; |
18068523 | 3508 | break; |
344d9588 | 3509 | case MSR_KVM_ASYNC_PF_EN: |
1930e5dd OU |
3510 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3511 | return 1; | |
3512 | ||
2635b5c4 VK |
3513 | msr_info->data = vcpu->arch.apf.msr_en_val; |
3514 | break; | |
3515 | case MSR_KVM_ASYNC_PF_INT: | |
1930e5dd OU |
3516 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
3517 | return 1; | |
3518 | ||
2635b5c4 | 3519 | msr_info->data = vcpu->arch.apf.msr_int_val; |
344d9588 | 3520 | break; |
557a961a | 3521 | case MSR_KVM_ASYNC_PF_ACK: |
1930e5dd OU |
3522 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3523 | return 1; | |
3524 | ||
557a961a VK |
3525 | msr_info->data = 0; |
3526 | break; | |
c9aaa895 | 3527 | case MSR_KVM_STEAL_TIME: |
1930e5dd OU |
3528 | if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) |
3529 | return 1; | |
3530 | ||
609e36d3 | 3531 | msr_info->data = vcpu->arch.st.msr_val; |
c9aaa895 | 3532 | break; |
1d92128f | 3533 | case MSR_KVM_PV_EOI_EN: |
1930e5dd OU |
3534 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) |
3535 | return 1; | |
3536 | ||
609e36d3 | 3537 | msr_info->data = vcpu->arch.pv_eoi.msr_val; |
1d92128f | 3538 | break; |
2d5ba19b | 3539 | case MSR_KVM_POLL_CONTROL: |
1930e5dd OU |
3540 | if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) |
3541 | return 1; | |
3542 | ||
2d5ba19b MT |
3543 | msr_info->data = vcpu->arch.msr_kvm_poll_control; |
3544 | break; | |
890ca9ae HY |
3545 | case MSR_IA32_P5_MC_ADDR: |
3546 | case MSR_IA32_P5_MC_TYPE: | |
3547 | case MSR_IA32_MCG_CAP: | |
3548 | case MSR_IA32_MCG_CTL: | |
3549 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 3550 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
44883f01 PB |
3551 | return get_msr_mce(vcpu, msr_info->index, &msr_info->data, |
3552 | msr_info->host_initiated); | |
864e2ab2 AL |
3553 | case MSR_IA32_XSS: |
3554 | if (!msr_info->host_initiated && | |
3555 | !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) | |
3556 | return 1; | |
3557 | msr_info->data = vcpu->arch.ia32_xss; | |
3558 | break; | |
84e0cefa JS |
3559 | case MSR_K7_CLK_CTL: |
3560 | /* | |
3561 | * Provide expected ramp-up count for K7. All other | |
3562 | * are set to zero, indicating minimum divisors for | |
3563 | * every field. | |
3564 | * | |
3565 | * This prevents guest kernels on AMD host with CPU | |
3566 | * type 6, model 8 and higher from exploding due to | |
3567 | * the rdmsr failing. | |
3568 | */ | |
609e36d3 | 3569 | msr_info->data = 0x20000000; |
84e0cefa | 3570 | break; |
55cd8e5a | 3571 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
f97f5a56 JD |
3572 | case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: |
3573 | case HV_X64_MSR_SYNDBG_OPTIONS: | |
e7d9513b AS |
3574 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
3575 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 3576 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
3577 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
3578 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
3579 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
e83d5887 | 3580 | return kvm_hv_get_msr_common(vcpu, |
44883f01 PB |
3581 | msr_info->index, &msr_info->data, |
3582 | msr_info->host_initiated); | |
91c9c3ed | 3583 | case MSR_IA32_BBL_CR_CTL3: |
3584 | /* This legacy MSR exists but isn't fully documented in current | |
3585 | * silicon. It is however accessed by winxp in very narrow | |
3586 | * scenarios where it sets bit #19, itself documented as | |
3587 | * a "reserved" bit. Best effort attempt to source coherent | |
3588 | * read data here should the balance of the register be | |
3589 | * interpreted by the guest: | |
3590 | * | |
3591 | * L2 cache control register 3: 64GB range, 256KB size, | |
3592 | * enabled, latency 0x1, configured | |
3593 | */ | |
609e36d3 | 3594 | msr_info->data = 0xbe702111; |
91c9c3ed | 3595 | break; |
2b036c6b | 3596 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 3597 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 3598 | return 1; |
609e36d3 | 3599 | msr_info->data = vcpu->arch.osvw.length; |
2b036c6b BO |
3600 | break; |
3601 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 3602 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 3603 | return 1; |
609e36d3 | 3604 | msr_info->data = vcpu->arch.osvw.status; |
2b036c6b | 3605 | break; |
db2336a8 | 3606 | case MSR_PLATFORM_INFO: |
6fbbde9a DS |
3607 | if (!msr_info->host_initiated && |
3608 | !vcpu->kvm->arch.guest_can_read_msr_platform_info) | |
3609 | return 1; | |
db2336a8 KH |
3610 | msr_info->data = vcpu->arch.msr_platform_info; |
3611 | break; | |
3612 | case MSR_MISC_FEATURES_ENABLES: | |
3613 | msr_info->data = vcpu->arch.msr_misc_features_enables; | |
3614 | break; | |
191c8137 BP |
3615 | case MSR_K7_HWCR: |
3616 | msr_info->data = vcpu->arch.msr_hwcr; | |
3617 | break; | |
15c4a640 | 3618 | default: |
c6702c9d | 3619 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
cbd71758 | 3620 | return kvm_pmu_get_msr(vcpu, msr_info); |
6abe9c13 | 3621 | return KVM_MSR_RET_INVALID; |
15c4a640 | 3622 | } |
15c4a640 CO |
3623 | return 0; |
3624 | } | |
3625 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
3626 | ||
313a3dc7 CO |
3627 | /* |
3628 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
3629 | * | |
3630 | * @return number of msrs set successfully. | |
3631 | */ | |
3632 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
3633 | struct kvm_msr_entry *entries, | |
3634 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
3635 | unsigned index, u64 *data)) | |
3636 | { | |
801e459a | 3637 | int i; |
313a3dc7 | 3638 | |
313a3dc7 CO |
3639 | for (i = 0; i < msrs->nmsrs; ++i) |
3640 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
3641 | break; | |
3642 | ||
313a3dc7 CO |
3643 | return i; |
3644 | } | |
3645 | ||
3646 | /* | |
3647 | * Read or write a bunch of msrs. Parameters are user addresses. | |
3648 | * | |
3649 | * @return number of msrs set successfully. | |
3650 | */ | |
3651 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
3652 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
3653 | unsigned index, u64 *data), | |
3654 | int writeback) | |
3655 | { | |
3656 | struct kvm_msrs msrs; | |
3657 | struct kvm_msr_entry *entries; | |
3658 | int r, n; | |
3659 | unsigned size; | |
3660 | ||
3661 | r = -EFAULT; | |
0e96f31e | 3662 | if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) |
313a3dc7 CO |
3663 | goto out; |
3664 | ||
3665 | r = -E2BIG; | |
3666 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
3667 | goto out; | |
3668 | ||
313a3dc7 | 3669 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; |
ff5c2c03 SL |
3670 | entries = memdup_user(user_msrs->entries, size); |
3671 | if (IS_ERR(entries)) { | |
3672 | r = PTR_ERR(entries); | |
313a3dc7 | 3673 | goto out; |
ff5c2c03 | 3674 | } |
313a3dc7 CO |
3675 | |
3676 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
3677 | if (r < 0) | |
3678 | goto out_free; | |
3679 | ||
3680 | r = -EFAULT; | |
3681 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
3682 | goto out_free; | |
3683 | ||
3684 | r = n; | |
3685 | ||
3686 | out_free: | |
7a73c028 | 3687 | kfree(entries); |
313a3dc7 CO |
3688 | out: |
3689 | return r; | |
3690 | } | |
3691 | ||
4d5422ce WL |
3692 | static inline bool kvm_can_mwait_in_guest(void) |
3693 | { | |
3694 | return boot_cpu_has(X86_FEATURE_MWAIT) && | |
8e9b29b6 KA |
3695 | !boot_cpu_has_bug(X86_BUG_MONITOR) && |
3696 | boot_cpu_has(X86_FEATURE_ARAT); | |
4d5422ce WL |
3697 | } |
3698 | ||
c21d54f0 VK |
3699 | static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu, |
3700 | struct kvm_cpuid2 __user *cpuid_arg) | |
3701 | { | |
3702 | struct kvm_cpuid2 cpuid; | |
3703 | int r; | |
3704 | ||
3705 | r = -EFAULT; | |
3706 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) | |
3707 | return r; | |
3708 | ||
3709 | r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
3710 | if (r) | |
3711 | return r; | |
3712 | ||
3713 | r = -EFAULT; | |
3714 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) | |
3715 | return r; | |
3716 | ||
3717 | return 0; | |
3718 | } | |
3719 | ||
784aa3d7 | 3720 | int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) |
018d00d2 | 3721 | { |
4d5422ce | 3722 | int r = 0; |
018d00d2 ZX |
3723 | |
3724 | switch (ext) { | |
3725 | case KVM_CAP_IRQCHIP: | |
3726 | case KVM_CAP_HLT: | |
3727 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 3728 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 3729 | case KVM_CAP_EXT_CPUID: |
9c15bb1d | 3730 | case KVM_CAP_EXT_EMUL_CPUID: |
c8076604 | 3731 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 3732 | case KVM_CAP_PIT: |
a28e4f5a | 3733 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 3734 | case KVM_CAP_MP_STATE: |
ed848624 | 3735 | case KVM_CAP_SYNC_MMU: |
a355c85c | 3736 | case KVM_CAP_USER_NMI: |
52d939a0 | 3737 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 3738 | case KVM_CAP_IRQ_INJECT_STATUS: |
d34e6b17 | 3739 | case KVM_CAP_IOEVENTFD: |
f848a5a8 | 3740 | case KVM_CAP_IOEVENTFD_NO_LENGTH: |
c5ff41ce | 3741 | case KVM_CAP_PIT2: |
e9f42757 | 3742 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 3743 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
ffde22ac | 3744 | case KVM_CAP_XEN_HVM: |
3cfc3092 | 3745 | case KVM_CAP_VCPU_EVENTS: |
55cd8e5a | 3746 | case KVM_CAP_HYPERV: |
10388a07 | 3747 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 3748 | case KVM_CAP_HYPERV_SPIN: |
5c919412 | 3749 | case KVM_CAP_HYPERV_SYNIC: |
efc479e6 | 3750 | case KVM_CAP_HYPERV_SYNIC2: |
d3457c87 | 3751 | case KVM_CAP_HYPERV_VP_INDEX: |
faeb7833 | 3752 | case KVM_CAP_HYPERV_EVENTFD: |
c1aea919 | 3753 | case KVM_CAP_HYPERV_TLBFLUSH: |
214ff83d | 3754 | case KVM_CAP_HYPERV_SEND_IPI: |
2bc39970 | 3755 | case KVM_CAP_HYPERV_CPUID: |
c21d54f0 | 3756 | case KVM_CAP_SYS_HYPERV_CPUID: |
ab9f4ecb | 3757 | case KVM_CAP_PCI_SEGMENT: |
a1efbe77 | 3758 | case KVM_CAP_DEBUGREGS: |
d2be1651 | 3759 | case KVM_CAP_X86_ROBUST_SINGLESTEP: |
2d5b5a66 | 3760 | case KVM_CAP_XSAVE: |
344d9588 | 3761 | case KVM_CAP_ASYNC_PF: |
72de5fa4 | 3762 | case KVM_CAP_ASYNC_PF_INT: |
92a1f12d | 3763 | case KVM_CAP_GET_TSC_KHZ: |
1c0b28c2 | 3764 | case KVM_CAP_KVMCLOCK_CTRL: |
4d8b81ab | 3765 | case KVM_CAP_READONLY_MEM: |
5f66b620 | 3766 | case KVM_CAP_HYPERV_TIME: |
100943c5 | 3767 | case KVM_CAP_IOAPIC_POLARITY_IGNORED: |
defcf51f | 3768 | case KVM_CAP_TSC_DEADLINE_TIMER: |
90de4a18 | 3769 | case KVM_CAP_DISABLE_QUIRKS: |
d71ba788 | 3770 | case KVM_CAP_SET_BOOT_CPU_ID: |
49df6397 | 3771 | case KVM_CAP_SPLIT_IRQCHIP: |
460df4c1 | 3772 | case KVM_CAP_IMMEDIATE_EXIT: |
66bb8a06 | 3773 | case KVM_CAP_PMU_EVENT_FILTER: |
801e459a | 3774 | case KVM_CAP_GET_MSR_FEATURES: |
6fbbde9a | 3775 | case KVM_CAP_MSR_PLATFORM_INFO: |
c4f55198 | 3776 | case KVM_CAP_EXCEPTION_PAYLOAD: |
b9b2782c | 3777 | case KVM_CAP_SET_GUEST_DEBUG: |
1aa561b1 | 3778 | case KVM_CAP_LAST_CPU: |
1ae09954 | 3779 | case KVM_CAP_X86_USER_SPACE_MSR: |
1a155254 | 3780 | case KVM_CAP_X86_MSR_FILTER: |
66570e96 | 3781 | case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: |
018d00d2 ZX |
3782 | r = 1; |
3783 | break; | |
01643c51 KH |
3784 | case KVM_CAP_SYNC_REGS: |
3785 | r = KVM_SYNC_X86_VALID_FIELDS; | |
3786 | break; | |
e3fd9a93 PB |
3787 | case KVM_CAP_ADJUST_CLOCK: |
3788 | r = KVM_CLOCK_TSC_STABLE; | |
3789 | break; | |
4d5422ce | 3790 | case KVM_CAP_X86_DISABLE_EXITS: |
b5170063 WL |
3791 | r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE | |
3792 | KVM_X86_DISABLE_EXITS_CSTATE; | |
4d5422ce WL |
3793 | if(kvm_can_mwait_in_guest()) |
3794 | r |= KVM_X86_DISABLE_EXITS_MWAIT; | |
668fffa3 | 3795 | break; |
6d396b55 PB |
3796 | case KVM_CAP_X86_SMM: |
3797 | /* SMBASE is usually relocated above 1M on modern chipsets, | |
3798 | * and SMM handlers might indeed rely on 4G segment limits, | |
3799 | * so do not report SMM to be available if real mode is | |
3800 | * emulated via vm86 mode. Still, do not go to great lengths | |
3801 | * to avoid userspace's usage of the feature, because it is a | |
3802 | * fringe case that is not enabled except via specific settings | |
3803 | * of the module parameters. | |
3804 | */ | |
5719455f | 3805 | r = kvm_x86_ops.has_emulated_msr(kvm, MSR_IA32_SMBASE); |
6d396b55 | 3806 | break; |
774ead3a | 3807 | case KVM_CAP_VAPIC: |
afaf0b2f | 3808 | r = !kvm_x86_ops.cpu_has_accelerated_tpr(); |
774ead3a | 3809 | break; |
f725230a | 3810 | case KVM_CAP_NR_VCPUS: |
8c3ba334 SL |
3811 | r = KVM_SOFT_MAX_VCPUS; |
3812 | break; | |
3813 | case KVM_CAP_MAX_VCPUS: | |
f725230a AK |
3814 | r = KVM_MAX_VCPUS; |
3815 | break; | |
a86cb413 TH |
3816 | case KVM_CAP_MAX_VCPU_ID: |
3817 | r = KVM_MAX_VCPU_ID; | |
3818 | break; | |
a68a6a72 MT |
3819 | case KVM_CAP_PV_MMU: /* obsolete */ |
3820 | r = 0; | |
2f333bcb | 3821 | break; |
890ca9ae HY |
3822 | case KVM_CAP_MCE: |
3823 | r = KVM_MAX_MCE_BANKS; | |
3824 | break; | |
2d5b5a66 | 3825 | case KVM_CAP_XCRS: |
d366bf7e | 3826 | r = boot_cpu_has(X86_FEATURE_XSAVE); |
2d5b5a66 | 3827 | break; |
92a1f12d JR |
3828 | case KVM_CAP_TSC_CONTROL: |
3829 | r = kvm_has_tsc_control; | |
3830 | break; | |
37131313 RK |
3831 | case KVM_CAP_X2APIC_API: |
3832 | r = KVM_X2APIC_API_VALID_FLAGS; | |
3833 | break; | |
8fcc4b59 | 3834 | case KVM_CAP_NESTED_STATE: |
33b22172 PB |
3835 | r = kvm_x86_ops.nested_ops->get_state ? |
3836 | kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0; | |
8fcc4b59 | 3837 | break; |
344c6c80 | 3838 | case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: |
afaf0b2f | 3839 | r = kvm_x86_ops.enable_direct_tlbflush != NULL; |
5a0165f6 VK |
3840 | break; |
3841 | case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: | |
33b22172 | 3842 | r = kvm_x86_ops.nested_ops->enable_evmcs != NULL; |
344c6c80 | 3843 | break; |
3edd6839 MG |
3844 | case KVM_CAP_SMALLER_MAXPHYADDR: |
3845 | r = (int) allow_smaller_maxphyaddr; | |
3846 | break; | |
004a0124 AJ |
3847 | case KVM_CAP_STEAL_TIME: |
3848 | r = sched_info_on(); | |
3849 | break; | |
fe6b6bc8 CQ |
3850 | case KVM_CAP_X86_BUS_LOCK_EXIT: |
3851 | if (kvm_has_bus_lock_exit) | |
3852 | r = KVM_BUS_LOCK_DETECTION_OFF | | |
3853 | KVM_BUS_LOCK_DETECTION_EXIT; | |
3854 | else | |
3855 | r = 0; | |
3856 | break; | |
018d00d2 | 3857 | default: |
018d00d2 ZX |
3858 | break; |
3859 | } | |
3860 | return r; | |
3861 | ||
3862 | } | |
3863 | ||
043405e1 CO |
3864 | long kvm_arch_dev_ioctl(struct file *filp, |
3865 | unsigned int ioctl, unsigned long arg) | |
3866 | { | |
3867 | void __user *argp = (void __user *)arg; | |
3868 | long r; | |
3869 | ||
3870 | switch (ioctl) { | |
3871 | case KVM_GET_MSR_INDEX_LIST: { | |
3872 | struct kvm_msr_list __user *user_msr_list = argp; | |
3873 | struct kvm_msr_list msr_list; | |
3874 | unsigned n; | |
3875 | ||
3876 | r = -EFAULT; | |
0e96f31e | 3877 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) |
043405e1 CO |
3878 | goto out; |
3879 | n = msr_list.nmsrs; | |
62ef68bb | 3880 | msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; |
0e96f31e | 3881 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) |
043405e1 CO |
3882 | goto out; |
3883 | r = -E2BIG; | |
e125e7b6 | 3884 | if (n < msr_list.nmsrs) |
043405e1 CO |
3885 | goto out; |
3886 | r = -EFAULT; | |
3887 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
3888 | num_msrs_to_save * sizeof(u32))) | |
3889 | goto out; | |
e125e7b6 | 3890 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 | 3891 | &emulated_msrs, |
62ef68bb | 3892 | num_emulated_msrs * sizeof(u32))) |
043405e1 CO |
3893 | goto out; |
3894 | r = 0; | |
3895 | break; | |
3896 | } | |
9c15bb1d BP |
3897 | case KVM_GET_SUPPORTED_CPUID: |
3898 | case KVM_GET_EMULATED_CPUID: { | |
674eea0f AK |
3899 | struct kvm_cpuid2 __user *cpuid_arg = argp; |
3900 | struct kvm_cpuid2 cpuid; | |
3901 | ||
3902 | r = -EFAULT; | |
0e96f31e | 3903 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
674eea0f | 3904 | goto out; |
9c15bb1d BP |
3905 | |
3906 | r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, | |
3907 | ioctl); | |
674eea0f AK |
3908 | if (r) |
3909 | goto out; | |
3910 | ||
3911 | r = -EFAULT; | |
0e96f31e | 3912 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) |
674eea0f AK |
3913 | goto out; |
3914 | r = 0; | |
3915 | break; | |
3916 | } | |
cf6c26ec | 3917 | case KVM_X86_GET_MCE_CAP_SUPPORTED: |
890ca9ae | 3918 | r = -EFAULT; |
c45dcc71 AR |
3919 | if (copy_to_user(argp, &kvm_mce_cap_supported, |
3920 | sizeof(kvm_mce_cap_supported))) | |
890ca9ae HY |
3921 | goto out; |
3922 | r = 0; | |
3923 | break; | |
801e459a TL |
3924 | case KVM_GET_MSR_FEATURE_INDEX_LIST: { |
3925 | struct kvm_msr_list __user *user_msr_list = argp; | |
3926 | struct kvm_msr_list msr_list; | |
3927 | unsigned int n; | |
3928 | ||
3929 | r = -EFAULT; | |
3930 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) | |
3931 | goto out; | |
3932 | n = msr_list.nmsrs; | |
3933 | msr_list.nmsrs = num_msr_based_features; | |
3934 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) | |
3935 | goto out; | |
3936 | r = -E2BIG; | |
3937 | if (n < msr_list.nmsrs) | |
3938 | goto out; | |
3939 | r = -EFAULT; | |
3940 | if (copy_to_user(user_msr_list->indices, &msr_based_features, | |
3941 | num_msr_based_features * sizeof(u32))) | |
3942 | goto out; | |
3943 | r = 0; | |
3944 | break; | |
3945 | } | |
3946 | case KVM_GET_MSRS: | |
3947 | r = msr_io(NULL, argp, do_get_msr_feature, 1); | |
3948 | break; | |
c21d54f0 VK |
3949 | case KVM_GET_SUPPORTED_HV_CPUID: |
3950 | r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp); | |
3951 | break; | |
043405e1 CO |
3952 | default: |
3953 | r = -EINVAL; | |
cf6c26ec | 3954 | break; |
043405e1 CO |
3955 | } |
3956 | out: | |
3957 | return r; | |
3958 | } | |
3959 | ||
f5f48ee1 SY |
3960 | static void wbinvd_ipi(void *garbage) |
3961 | { | |
3962 | wbinvd(); | |
3963 | } | |
3964 | ||
3965 | static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
3966 | { | |
e0f0bbc5 | 3967 | return kvm_arch_has_noncoherent_dma(vcpu->kvm); |
f5f48ee1 SY |
3968 | } |
3969 | ||
313a3dc7 CO |
3970 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
3971 | { | |
f5f48ee1 SY |
3972 | /* Address WBINVD may be executed by guest */ |
3973 | if (need_emulate_wbinvd(vcpu)) { | |
afaf0b2f | 3974 | if (kvm_x86_ops.has_wbinvd_exit()) |
f5f48ee1 SY |
3975 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); |
3976 | else if (vcpu->cpu != -1 && vcpu->cpu != cpu) | |
3977 | smp_call_function_single(vcpu->cpu, | |
3978 | wbinvd_ipi, NULL, 1); | |
3979 | } | |
3980 | ||
afaf0b2f | 3981 | kvm_x86_ops.vcpu_load(vcpu, cpu); |
8f6055cb | 3982 | |
37486135 BM |
3983 | /* Save host pkru register if supported */ |
3984 | vcpu->arch.host_pkru = read_pkru(); | |
3985 | ||
0dd6a6ed ZA |
3986 | /* Apply any externally detected TSC adjustments (due to suspend) */ |
3987 | if (unlikely(vcpu->arch.tsc_offset_adjustment)) { | |
3988 | adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); | |
3989 | vcpu->arch.tsc_offset_adjustment = 0; | |
105b21bb | 3990 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed | 3991 | } |
8f6055cb | 3992 | |
b0c39dc6 | 3993 | if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { |
6f526ec5 | 3994 | s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : |
4ea1636b | 3995 | rdtsc() - vcpu->arch.last_host_tsc; |
e48672fa ZA |
3996 | if (tsc_delta < 0) |
3997 | mark_tsc_unstable("KVM discovered backwards TSC"); | |
ce7a058a | 3998 | |
b0c39dc6 | 3999 | if (kvm_check_tsc_unstable()) { |
07c1419a | 4000 | u64 offset = kvm_compute_tsc_offset(vcpu, |
b183aa58 | 4001 | vcpu->arch.last_guest_tsc); |
a545ab6a | 4002 | kvm_vcpu_write_tsc_offset(vcpu, offset); |
c285545f | 4003 | vcpu->arch.tsc_catchup = 1; |
c285545f | 4004 | } |
a749e247 PB |
4005 | |
4006 | if (kvm_lapic_hv_timer_in_use(vcpu)) | |
4007 | kvm_lapic_restart_hv_timer(vcpu); | |
4008 | ||
d98d07ca MT |
4009 | /* |
4010 | * On a host with synchronized TSC, there is no need to update | |
4011 | * kvmclock on vcpu->cpu migration | |
4012 | */ | |
4013 | if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) | |
0061d53d | 4014 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
c285545f | 4015 | if (vcpu->cpu != cpu) |
1bd2009e | 4016 | kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); |
e48672fa | 4017 | vcpu->cpu = cpu; |
6b7d7e76 | 4018 | } |
c9aaa895 | 4019 | |
c9aaa895 | 4020 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
313a3dc7 CO |
4021 | } |
4022 | ||
0b9f6c46 PX |
4023 | static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) |
4024 | { | |
b0431382 BO |
4025 | struct kvm_host_map map; |
4026 | struct kvm_steal_time *st; | |
15b51dc0 | 4027 | int idx; |
b0431382 | 4028 | |
0b9f6c46 PX |
4029 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) |
4030 | return; | |
4031 | ||
a6bd811f | 4032 | if (vcpu->arch.st.preempted) |
8c6de56a BO |
4033 | return; |
4034 | ||
15b51dc0 SC |
4035 | /* |
4036 | * Take the srcu lock as memslots will be accessed to check the gfn | |
4037 | * cache generation against the memslots generation. | |
4038 | */ | |
4039 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
4040 | ||
b0431382 BO |
4041 | if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map, |
4042 | &vcpu->arch.st.cache, true)) | |
15b51dc0 | 4043 | goto out; |
b0431382 BO |
4044 | |
4045 | st = map.hva + | |
4046 | offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); | |
0b9f6c46 | 4047 | |
a6bd811f | 4048 | st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; |
0b9f6c46 | 4049 | |
b0431382 | 4050 | kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true); |
15b51dc0 SC |
4051 | |
4052 | out: | |
4053 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
0b9f6c46 PX |
4054 | } |
4055 | ||
313a3dc7 CO |
4056 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) |
4057 | { | |
f1c6366e | 4058 | if (vcpu->preempted && !vcpu->arch.guest_state_protected) |
afaf0b2f | 4059 | vcpu->arch.preempted_in_kernel = !kvm_x86_ops.get_cpl(vcpu); |
de63ad4c | 4060 | |
0b9f6c46 | 4061 | kvm_steal_time_set_preempted(vcpu); |
afaf0b2f | 4062 | kvm_x86_ops.vcpu_put(vcpu); |
4ea1636b | 4063 | vcpu->arch.last_host_tsc = rdtsc(); |
efdab992 | 4064 | /* |
f9dcf08e RK |
4065 | * If userspace has set any breakpoints or watchpoints, dr6 is restored |
4066 | * on every vmexit, but if not, we might have a stale dr6 from the | |
4067 | * guest. do_debug expects dr6 to be cleared after it runs, do the same. | |
efdab992 | 4068 | */ |
f9dcf08e | 4069 | set_debugreg(0, 6); |
313a3dc7 CO |
4070 | } |
4071 | ||
313a3dc7 CO |
4072 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
4073 | struct kvm_lapic_state *s) | |
4074 | { | |
fa59cc00 | 4075 | if (vcpu->arch.apicv_active) |
afaf0b2f | 4076 | kvm_x86_ops.sync_pir_to_irr(vcpu); |
d62caabb | 4077 | |
a92e2543 | 4078 | return kvm_apic_get_state(vcpu, s); |
313a3dc7 CO |
4079 | } |
4080 | ||
4081 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
4082 | struct kvm_lapic_state *s) | |
4083 | { | |
a92e2543 RK |
4084 | int r; |
4085 | ||
4086 | r = kvm_apic_set_state(vcpu, s); | |
4087 | if (r) | |
4088 | return r; | |
cb142eb7 | 4089 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
4090 | |
4091 | return 0; | |
4092 | } | |
4093 | ||
127a457a MG |
4094 | static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) |
4095 | { | |
71cc849b PB |
4096 | /* |
4097 | * We can accept userspace's request for interrupt injection | |
4098 | * as long as we have a place to store the interrupt number. | |
4099 | * The actual injection will happen when the CPU is able to | |
4100 | * deliver the interrupt. | |
4101 | */ | |
4102 | if (kvm_cpu_has_extint(vcpu)) | |
4103 | return false; | |
4104 | ||
4105 | /* Acknowledging ExtINT does not happen if LINT0 is masked. */ | |
127a457a MG |
4106 | return (!lapic_in_kernel(vcpu) || |
4107 | kvm_apic_accept_pic_intr(vcpu)); | |
4108 | } | |
4109 | ||
782d422b MG |
4110 | static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) |
4111 | { | |
4112 | return kvm_arch_interrupt_allowed(vcpu) && | |
782d422b MG |
4113 | kvm_cpu_accept_dm_intr(vcpu); |
4114 | } | |
4115 | ||
f77bc6a4 ZX |
4116 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
4117 | struct kvm_interrupt *irq) | |
4118 | { | |
02cdb50f | 4119 | if (irq->irq >= KVM_NR_INTERRUPTS) |
f77bc6a4 | 4120 | return -EINVAL; |
1c1a9ce9 SR |
4121 | |
4122 | if (!irqchip_in_kernel(vcpu->kvm)) { | |
4123 | kvm_queue_interrupt(vcpu, irq->irq, false); | |
4124 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
4125 | return 0; | |
4126 | } | |
4127 | ||
4128 | /* | |
4129 | * With in-kernel LAPIC, we only use this to inject EXTINT, so | |
4130 | * fail for in-kernel 8259. | |
4131 | */ | |
4132 | if (pic_in_kernel(vcpu->kvm)) | |
f77bc6a4 | 4133 | return -ENXIO; |
f77bc6a4 | 4134 | |
1c1a9ce9 SR |
4135 | if (vcpu->arch.pending_external_vector != -1) |
4136 | return -EEXIST; | |
f77bc6a4 | 4137 | |
1c1a9ce9 | 4138 | vcpu->arch.pending_external_vector = irq->irq; |
934bf653 | 4139 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f77bc6a4 ZX |
4140 | return 0; |
4141 | } | |
4142 | ||
c4abb7c9 JK |
4143 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
4144 | { | |
c4abb7c9 | 4145 | kvm_inject_nmi(vcpu); |
c4abb7c9 JK |
4146 | |
4147 | return 0; | |
4148 | } | |
4149 | ||
f077825a PB |
4150 | static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) |
4151 | { | |
64d60670 PB |
4152 | kvm_make_request(KVM_REQ_SMI, vcpu); |
4153 | ||
f077825a PB |
4154 | return 0; |
4155 | } | |
4156 | ||
b209749f AK |
4157 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
4158 | struct kvm_tpr_access_ctl *tac) | |
4159 | { | |
4160 | if (tac->flags) | |
4161 | return -EINVAL; | |
4162 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
4163 | return 0; | |
4164 | } | |
4165 | ||
890ca9ae HY |
4166 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
4167 | u64 mcg_cap) | |
4168 | { | |
4169 | int r; | |
4170 | unsigned bank_num = mcg_cap & 0xff, bank; | |
4171 | ||
4172 | r = -EINVAL; | |
c4e0e4ab | 4173 | if (!bank_num || bank_num > KVM_MAX_MCE_BANKS) |
890ca9ae | 4174 | goto out; |
c45dcc71 | 4175 | if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) |
890ca9ae HY |
4176 | goto out; |
4177 | r = 0; | |
4178 | vcpu->arch.mcg_cap = mcg_cap; | |
4179 | /* Init IA32_MCG_CTL to all 1s */ | |
4180 | if (mcg_cap & MCG_CTL_P) | |
4181 | vcpu->arch.mcg_ctl = ~(u64)0; | |
4182 | /* Init IA32_MCi_CTL to all 1s */ | |
4183 | for (bank = 0; bank < bank_num; bank++) | |
4184 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
c45dcc71 | 4185 | |
afaf0b2f | 4186 | kvm_x86_ops.setup_mce(vcpu); |
890ca9ae HY |
4187 | out: |
4188 | return r; | |
4189 | } | |
4190 | ||
4191 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
4192 | struct kvm_x86_mce *mce) | |
4193 | { | |
4194 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
4195 | unsigned bank_num = mcg_cap & 0xff; | |
4196 | u64 *banks = vcpu->arch.mce_banks; | |
4197 | ||
4198 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
4199 | return -EINVAL; | |
4200 | /* | |
4201 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
4202 | * reporting is disabled | |
4203 | */ | |
4204 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
4205 | vcpu->arch.mcg_ctl != ~(u64)0) | |
4206 | return 0; | |
4207 | banks += 4 * mce->bank; | |
4208 | /* | |
4209 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
4210 | * reporting is disabled for the bank | |
4211 | */ | |
4212 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
4213 | return 0; | |
4214 | if (mce->status & MCI_STATUS_UC) { | |
4215 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
fc78f519 | 4216 | !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { |
a8eeb04a | 4217 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
890ca9ae HY |
4218 | return 0; |
4219 | } | |
4220 | if (banks[1] & MCI_STATUS_VAL) | |
4221 | mce->status |= MCI_STATUS_OVER; | |
4222 | banks[2] = mce->addr; | |
4223 | banks[3] = mce->misc; | |
4224 | vcpu->arch.mcg_status = mce->mcg_status; | |
4225 | banks[1] = mce->status; | |
4226 | kvm_queue_exception(vcpu, MC_VECTOR); | |
4227 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
4228 | || !(banks[1] & MCI_STATUS_UC)) { | |
4229 | if (banks[1] & MCI_STATUS_VAL) | |
4230 | mce->status |= MCI_STATUS_OVER; | |
4231 | banks[2] = mce->addr; | |
4232 | banks[3] = mce->misc; | |
4233 | banks[1] = mce->status; | |
4234 | } else | |
4235 | banks[1] |= MCI_STATUS_OVER; | |
4236 | return 0; | |
4237 | } | |
4238 | ||
3cfc3092 JK |
4239 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
4240 | struct kvm_vcpu_events *events) | |
4241 | { | |
7460fb4a | 4242 | process_nmi(vcpu); |
59073aaf | 4243 | |
1f7becf1 JZ |
4244 | if (kvm_check_request(KVM_REQ_SMI, vcpu)) |
4245 | process_smi(vcpu); | |
4246 | ||
a06230b6 OU |
4247 | /* |
4248 | * In guest mode, payload delivery should be deferred, | |
4249 | * so that the L1 hypervisor can intercept #PF before | |
4250 | * CR2 is modified (or intercept #DB before DR6 is | |
4251 | * modified under nVMX). Unless the per-VM capability, | |
4252 | * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of | |
4253 | * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we | |
4254 | * opportunistically defer the exception payload, deliver it if the | |
4255 | * capability hasn't been requested before processing a | |
4256 | * KVM_GET_VCPU_EVENTS. | |
4257 | */ | |
4258 | if (!vcpu->kvm->arch.exception_payload_enabled && | |
4259 | vcpu->arch.exception.pending && vcpu->arch.exception.has_payload) | |
4260 | kvm_deliver_exception_payload(vcpu); | |
4261 | ||
664f8e26 | 4262 | /* |
59073aaf JM |
4263 | * The API doesn't provide the instruction length for software |
4264 | * exceptions, so don't report them. As long as the guest RIP | |
4265 | * isn't advanced, we should expect to encounter the exception | |
4266 | * again. | |
664f8e26 | 4267 | */ |
59073aaf JM |
4268 | if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { |
4269 | events->exception.injected = 0; | |
4270 | events->exception.pending = 0; | |
4271 | } else { | |
4272 | events->exception.injected = vcpu->arch.exception.injected; | |
4273 | events->exception.pending = vcpu->arch.exception.pending; | |
4274 | /* | |
4275 | * For ABI compatibility, deliberately conflate | |
4276 | * pending and injected exceptions when | |
4277 | * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. | |
4278 | */ | |
4279 | if (!vcpu->kvm->arch.exception_payload_enabled) | |
4280 | events->exception.injected |= | |
4281 | vcpu->arch.exception.pending; | |
4282 | } | |
3cfc3092 JK |
4283 | events->exception.nr = vcpu->arch.exception.nr; |
4284 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
4285 | events->exception.error_code = vcpu->arch.exception.error_code; | |
59073aaf JM |
4286 | events->exception_has_payload = vcpu->arch.exception.has_payload; |
4287 | events->exception_payload = vcpu->arch.exception.payload; | |
3cfc3092 | 4288 | |
03b82a30 | 4289 | events->interrupt.injected = |
04140b41 | 4290 | vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; |
3cfc3092 | 4291 | events->interrupt.nr = vcpu->arch.interrupt.nr; |
03b82a30 | 4292 | events->interrupt.soft = 0; |
afaf0b2f | 4293 | events->interrupt.shadow = kvm_x86_ops.get_interrupt_shadow(vcpu); |
3cfc3092 JK |
4294 | |
4295 | events->nmi.injected = vcpu->arch.nmi_injected; | |
7460fb4a | 4296 | events->nmi.pending = vcpu->arch.nmi_pending != 0; |
afaf0b2f | 4297 | events->nmi.masked = kvm_x86_ops.get_nmi_mask(vcpu); |
97e69aa6 | 4298 | events->nmi.pad = 0; |
3cfc3092 | 4299 | |
66450a21 | 4300 | events->sipi_vector = 0; /* never valid when reporting to user space */ |
3cfc3092 | 4301 | |
f077825a PB |
4302 | events->smi.smm = is_smm(vcpu); |
4303 | events->smi.pending = vcpu->arch.smi_pending; | |
4304 | events->smi.smm_inside_nmi = | |
4305 | !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); | |
4306 | events->smi.latched_init = kvm_lapic_latched_init(vcpu); | |
4307 | ||
dab4b911 | 4308 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
f077825a PB |
4309 | | KVM_VCPUEVENT_VALID_SHADOW |
4310 | | KVM_VCPUEVENT_VALID_SMM); | |
59073aaf JM |
4311 | if (vcpu->kvm->arch.exception_payload_enabled) |
4312 | events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; | |
4313 | ||
97e69aa6 | 4314 | memset(&events->reserved, 0, sizeof(events->reserved)); |
3cfc3092 JK |
4315 | } |
4316 | ||
c5833c7a | 4317 | static void kvm_smm_changed(struct kvm_vcpu *vcpu); |
6ef4e07e | 4318 | |
3cfc3092 JK |
4319 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, |
4320 | struct kvm_vcpu_events *events) | |
4321 | { | |
dab4b911 | 4322 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 | 4323 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
f077825a | 4324 | | KVM_VCPUEVENT_VALID_SHADOW |
59073aaf JM |
4325 | | KVM_VCPUEVENT_VALID_SMM |
4326 | | KVM_VCPUEVENT_VALID_PAYLOAD)) | |
3cfc3092 JK |
4327 | return -EINVAL; |
4328 | ||
59073aaf JM |
4329 | if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { |
4330 | if (!vcpu->kvm->arch.exception_payload_enabled) | |
4331 | return -EINVAL; | |
4332 | if (events->exception.pending) | |
4333 | events->exception.injected = 0; | |
4334 | else | |
4335 | events->exception_has_payload = 0; | |
4336 | } else { | |
4337 | events->exception.pending = 0; | |
4338 | events->exception_has_payload = 0; | |
4339 | } | |
4340 | ||
4341 | if ((events->exception.injected || events->exception.pending) && | |
4342 | (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) | |
78e546c8 PB |
4343 | return -EINVAL; |
4344 | ||
28bf2888 DH |
4345 | /* INITs are latched while in SMM */ |
4346 | if (events->flags & KVM_VCPUEVENT_VALID_SMM && | |
4347 | (events->smi.smm || events->smi.pending) && | |
4348 | vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) | |
4349 | return -EINVAL; | |
4350 | ||
7460fb4a | 4351 | process_nmi(vcpu); |
59073aaf JM |
4352 | vcpu->arch.exception.injected = events->exception.injected; |
4353 | vcpu->arch.exception.pending = events->exception.pending; | |
3cfc3092 JK |
4354 | vcpu->arch.exception.nr = events->exception.nr; |
4355 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
4356 | vcpu->arch.exception.error_code = events->exception.error_code; | |
59073aaf JM |
4357 | vcpu->arch.exception.has_payload = events->exception_has_payload; |
4358 | vcpu->arch.exception.payload = events->exception_payload; | |
3cfc3092 | 4359 | |
04140b41 | 4360 | vcpu->arch.interrupt.injected = events->interrupt.injected; |
3cfc3092 JK |
4361 | vcpu->arch.interrupt.nr = events->interrupt.nr; |
4362 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
48005f64 | 4363 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) |
afaf0b2f | 4364 | kvm_x86_ops.set_interrupt_shadow(vcpu, |
48005f64 | 4365 | events->interrupt.shadow); |
3cfc3092 JK |
4366 | |
4367 | vcpu->arch.nmi_injected = events->nmi.injected; | |
dab4b911 JK |
4368 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) |
4369 | vcpu->arch.nmi_pending = events->nmi.pending; | |
afaf0b2f | 4370 | kvm_x86_ops.set_nmi_mask(vcpu, events->nmi.masked); |
3cfc3092 | 4371 | |
66450a21 | 4372 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && |
bce87cce | 4373 | lapic_in_kernel(vcpu)) |
66450a21 | 4374 | vcpu->arch.apic->sipi_vector = events->sipi_vector; |
3cfc3092 | 4375 | |
f077825a | 4376 | if (events->flags & KVM_VCPUEVENT_VALID_SMM) { |
c5833c7a SC |
4377 | if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) { |
4378 | if (events->smi.smm) | |
4379 | vcpu->arch.hflags |= HF_SMM_MASK; | |
4380 | else | |
4381 | vcpu->arch.hflags &= ~HF_SMM_MASK; | |
4382 | kvm_smm_changed(vcpu); | |
4383 | } | |
6ef4e07e | 4384 | |
f077825a | 4385 | vcpu->arch.smi_pending = events->smi.pending; |
f4ef1910 WL |
4386 | |
4387 | if (events->smi.smm) { | |
4388 | if (events->smi.smm_inside_nmi) | |
4389 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; | |
f077825a | 4390 | else |
f4ef1910 | 4391 | vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; |
ff90afa7 LA |
4392 | } |
4393 | ||
4394 | if (lapic_in_kernel(vcpu)) { | |
4395 | if (events->smi.latched_init) | |
4396 | set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
4397 | else | |
4398 | clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
f077825a PB |
4399 | } |
4400 | } | |
4401 | ||
3842d135 AK |
4402 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
4403 | ||
3cfc3092 JK |
4404 | return 0; |
4405 | } | |
4406 | ||
a1efbe77 JK |
4407 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, |
4408 | struct kvm_debugregs *dbgregs) | |
4409 | { | |
73aaf249 JK |
4410 | unsigned long val; |
4411 | ||
a1efbe77 | 4412 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); |
16f8a6f9 | 4413 | kvm_get_dr(vcpu, 6, &val); |
73aaf249 | 4414 | dbgregs->dr6 = val; |
a1efbe77 JK |
4415 | dbgregs->dr7 = vcpu->arch.dr7; |
4416 | dbgregs->flags = 0; | |
97e69aa6 | 4417 | memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); |
a1efbe77 JK |
4418 | } |
4419 | ||
4420 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
4421 | struct kvm_debugregs *dbgregs) | |
4422 | { | |
4423 | if (dbgregs->flags) | |
4424 | return -EINVAL; | |
4425 | ||
d14bdb55 PB |
4426 | if (dbgregs->dr6 & ~0xffffffffull) |
4427 | return -EINVAL; | |
4428 | if (dbgregs->dr7 & ~0xffffffffull) | |
4429 | return -EINVAL; | |
4430 | ||
a1efbe77 | 4431 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); |
ae561ede | 4432 | kvm_update_dr0123(vcpu); |
a1efbe77 JK |
4433 | vcpu->arch.dr6 = dbgregs->dr6; |
4434 | vcpu->arch.dr7 = dbgregs->dr7; | |
9926c9fd | 4435 | kvm_update_dr7(vcpu); |
a1efbe77 | 4436 | |
a1efbe77 JK |
4437 | return 0; |
4438 | } | |
4439 | ||
df1daba7 PB |
4440 | #define XSTATE_COMPACTION_ENABLED (1ULL << 63) |
4441 | ||
4442 | static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) | |
4443 | { | |
b666a4b6 | 4444 | struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; |
400e4b20 | 4445 | u64 xstate_bv = xsave->header.xfeatures; |
df1daba7 PB |
4446 | u64 valid; |
4447 | ||
4448 | /* | |
4449 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
4450 | * leaves 0 and 1 in the loop below. | |
4451 | */ | |
4452 | memcpy(dest, xsave, XSAVE_HDR_OFFSET); | |
4453 | ||
4454 | /* Set XSTATE_BV */ | |
00c87e9a | 4455 | xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE; |
df1daba7 PB |
4456 | *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; |
4457 | ||
4458 | /* | |
4459 | * Copy each region from the possibly compacted offset to the | |
4460 | * non-compacted offset. | |
4461 | */ | |
d91cab78 | 4462 | valid = xstate_bv & ~XFEATURE_MASK_FPSSE; |
df1daba7 | 4463 | while (valid) { |
abd16d68 SAS |
4464 | u64 xfeature_mask = valid & -valid; |
4465 | int xfeature_nr = fls64(xfeature_mask) - 1; | |
4466 | void *src = get_xsave_addr(xsave, xfeature_nr); | |
df1daba7 PB |
4467 | |
4468 | if (src) { | |
4469 | u32 size, offset, ecx, edx; | |
abd16d68 | 4470 | cpuid_count(XSTATE_CPUID, xfeature_nr, |
df1daba7 | 4471 | &size, &offset, &ecx, &edx); |
abd16d68 | 4472 | if (xfeature_nr == XFEATURE_PKRU) |
38cfd5e3 PB |
4473 | memcpy(dest + offset, &vcpu->arch.pkru, |
4474 | sizeof(vcpu->arch.pkru)); | |
4475 | else | |
4476 | memcpy(dest + offset, src, size); | |
4477 | ||
df1daba7 PB |
4478 | } |
4479 | ||
abd16d68 | 4480 | valid -= xfeature_mask; |
df1daba7 PB |
4481 | } |
4482 | } | |
4483 | ||
4484 | static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) | |
4485 | { | |
b666a4b6 | 4486 | struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; |
df1daba7 PB |
4487 | u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); |
4488 | u64 valid; | |
4489 | ||
4490 | /* | |
4491 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
4492 | * leaves 0 and 1 in the loop below. | |
4493 | */ | |
4494 | memcpy(xsave, src, XSAVE_HDR_OFFSET); | |
4495 | ||
4496 | /* Set XSTATE_BV and possibly XCOMP_BV. */ | |
400e4b20 | 4497 | xsave->header.xfeatures = xstate_bv; |
782511b0 | 4498 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
3a54450b | 4499 | xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; |
df1daba7 PB |
4500 | |
4501 | /* | |
4502 | * Copy each region from the non-compacted offset to the | |
4503 | * possibly compacted offset. | |
4504 | */ | |
d91cab78 | 4505 | valid = xstate_bv & ~XFEATURE_MASK_FPSSE; |
df1daba7 | 4506 | while (valid) { |
abd16d68 SAS |
4507 | u64 xfeature_mask = valid & -valid; |
4508 | int xfeature_nr = fls64(xfeature_mask) - 1; | |
4509 | void *dest = get_xsave_addr(xsave, xfeature_nr); | |
df1daba7 PB |
4510 | |
4511 | if (dest) { | |
4512 | u32 size, offset, ecx, edx; | |
abd16d68 | 4513 | cpuid_count(XSTATE_CPUID, xfeature_nr, |
df1daba7 | 4514 | &size, &offset, &ecx, &edx); |
abd16d68 | 4515 | if (xfeature_nr == XFEATURE_PKRU) |
38cfd5e3 PB |
4516 | memcpy(&vcpu->arch.pkru, src + offset, |
4517 | sizeof(vcpu->arch.pkru)); | |
4518 | else | |
4519 | memcpy(dest, src + offset, size); | |
ee4100da | 4520 | } |
df1daba7 | 4521 | |
abd16d68 | 4522 | valid -= xfeature_mask; |
df1daba7 PB |
4523 | } |
4524 | } | |
4525 | ||
2d5b5a66 SY |
4526 | static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, |
4527 | struct kvm_xsave *guest_xsave) | |
4528 | { | |
ed02b213 TL |
4529 | if (!vcpu->arch.guest_fpu) |
4530 | return; | |
4531 | ||
d366bf7e | 4532 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
df1daba7 PB |
4533 | memset(guest_xsave, 0, sizeof(struct kvm_xsave)); |
4534 | fill_xsave((u8 *) guest_xsave->region, vcpu); | |
4344ee98 | 4535 | } else { |
2d5b5a66 | 4536 | memcpy(guest_xsave->region, |
b666a4b6 | 4537 | &vcpu->arch.guest_fpu->state.fxsave, |
c47ada30 | 4538 | sizeof(struct fxregs_state)); |
2d5b5a66 | 4539 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = |
d91cab78 | 4540 | XFEATURE_MASK_FPSSE; |
2d5b5a66 SY |
4541 | } |
4542 | } | |
4543 | ||
a575813b WL |
4544 | #define XSAVE_MXCSR_OFFSET 24 |
4545 | ||
2d5b5a66 SY |
4546 | static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, |
4547 | struct kvm_xsave *guest_xsave) | |
4548 | { | |
ed02b213 TL |
4549 | u64 xstate_bv; |
4550 | u32 mxcsr; | |
4551 | ||
4552 | if (!vcpu->arch.guest_fpu) | |
4553 | return 0; | |
4554 | ||
4555 | xstate_bv = *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; | |
4556 | mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)]; | |
2d5b5a66 | 4557 | |
d366bf7e | 4558 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
d7876f1b PB |
4559 | /* |
4560 | * Here we allow setting states that are not present in | |
4561 | * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility | |
4562 | * with old userspace. | |
4563 | */ | |
cfc48181 | 4564 | if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask) |
d7876f1b | 4565 | return -EINVAL; |
df1daba7 | 4566 | load_xsave(vcpu, (u8 *)guest_xsave->region); |
d7876f1b | 4567 | } else { |
a575813b WL |
4568 | if (xstate_bv & ~XFEATURE_MASK_FPSSE || |
4569 | mxcsr & ~mxcsr_feature_mask) | |
2d5b5a66 | 4570 | return -EINVAL; |
b666a4b6 | 4571 | memcpy(&vcpu->arch.guest_fpu->state.fxsave, |
c47ada30 | 4572 | guest_xsave->region, sizeof(struct fxregs_state)); |
2d5b5a66 SY |
4573 | } |
4574 | return 0; | |
4575 | } | |
4576 | ||
4577 | static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, | |
4578 | struct kvm_xcrs *guest_xcrs) | |
4579 | { | |
d366bf7e | 4580 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) { |
2d5b5a66 SY |
4581 | guest_xcrs->nr_xcrs = 0; |
4582 | return; | |
4583 | } | |
4584 | ||
4585 | guest_xcrs->nr_xcrs = 1; | |
4586 | guest_xcrs->flags = 0; | |
4587 | guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; | |
4588 | guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; | |
4589 | } | |
4590 | ||
4591 | static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, | |
4592 | struct kvm_xcrs *guest_xcrs) | |
4593 | { | |
4594 | int i, r = 0; | |
4595 | ||
d366bf7e | 4596 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) |
2d5b5a66 SY |
4597 | return -EINVAL; |
4598 | ||
4599 | if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) | |
4600 | return -EINVAL; | |
4601 | ||
4602 | for (i = 0; i < guest_xcrs->nr_xcrs; i++) | |
4603 | /* Only support XCR0 currently */ | |
c67a04cb | 4604 | if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { |
2d5b5a66 | 4605 | r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, |
c67a04cb | 4606 | guest_xcrs->xcrs[i].value); |
2d5b5a66 SY |
4607 | break; |
4608 | } | |
4609 | if (r) | |
4610 | r = -EINVAL; | |
4611 | return r; | |
4612 | } | |
4613 | ||
1c0b28c2 EM |
4614 | /* |
4615 | * kvm_set_guest_paused() indicates to the guest kernel that it has been | |
4616 | * stopped by the hypervisor. This function will be called from the host only. | |
4617 | * EINVAL is returned when the host attempts to set the flag for a guest that | |
4618 | * does not support pv clocks. | |
4619 | */ | |
4620 | static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) | |
4621 | { | |
0b79459b | 4622 | if (!vcpu->arch.pv_time_enabled) |
1c0b28c2 | 4623 | return -EINVAL; |
51d59c6b | 4624 | vcpu->arch.pvclock_set_guest_stopped_request = true; |
1c0b28c2 EM |
4625 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
4626 | return 0; | |
4627 | } | |
4628 | ||
5c919412 AS |
4629 | static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, |
4630 | struct kvm_enable_cap *cap) | |
4631 | { | |
57b119da VK |
4632 | int r; |
4633 | uint16_t vmcs_version; | |
4634 | void __user *user_ptr; | |
4635 | ||
5c919412 AS |
4636 | if (cap->flags) |
4637 | return -EINVAL; | |
4638 | ||
4639 | switch (cap->cap) { | |
efc479e6 RK |
4640 | case KVM_CAP_HYPERV_SYNIC2: |
4641 | if (cap->args[0]) | |
4642 | return -EINVAL; | |
df561f66 | 4643 | fallthrough; |
b2869f28 | 4644 | |
5c919412 | 4645 | case KVM_CAP_HYPERV_SYNIC: |
546d87e5 WL |
4646 | if (!irqchip_in_kernel(vcpu->kvm)) |
4647 | return -EINVAL; | |
efc479e6 RK |
4648 | return kvm_hv_activate_synic(vcpu, cap->cap == |
4649 | KVM_CAP_HYPERV_SYNIC2); | |
57b119da | 4650 | case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: |
33b22172 | 4651 | if (!kvm_x86_ops.nested_ops->enable_evmcs) |
5158917c | 4652 | return -ENOTTY; |
33b22172 | 4653 | r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version); |
57b119da VK |
4654 | if (!r) { |
4655 | user_ptr = (void __user *)(uintptr_t)cap->args[0]; | |
4656 | if (copy_to_user(user_ptr, &vmcs_version, | |
4657 | sizeof(vmcs_version))) | |
4658 | r = -EFAULT; | |
4659 | } | |
4660 | return r; | |
344c6c80 | 4661 | case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: |
afaf0b2f | 4662 | if (!kvm_x86_ops.enable_direct_tlbflush) |
344c6c80 TL |
4663 | return -ENOTTY; |
4664 | ||
afaf0b2f | 4665 | return kvm_x86_ops.enable_direct_tlbflush(vcpu); |
57b119da | 4666 | |
66570e96 OU |
4667 | case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: |
4668 | vcpu->arch.pv_cpuid.enforce = cap->args[0]; | |
01b4f510 OU |
4669 | if (vcpu->arch.pv_cpuid.enforce) |
4670 | kvm_update_pv_runtime(vcpu); | |
66570e96 OU |
4671 | |
4672 | return 0; | |
4673 | ||
5c919412 AS |
4674 | default: |
4675 | return -EINVAL; | |
4676 | } | |
4677 | } | |
4678 | ||
313a3dc7 CO |
4679 | long kvm_arch_vcpu_ioctl(struct file *filp, |
4680 | unsigned int ioctl, unsigned long arg) | |
4681 | { | |
4682 | struct kvm_vcpu *vcpu = filp->private_data; | |
4683 | void __user *argp = (void __user *)arg; | |
4684 | int r; | |
d1ac91d8 AK |
4685 | union { |
4686 | struct kvm_lapic_state *lapic; | |
4687 | struct kvm_xsave *xsave; | |
4688 | struct kvm_xcrs *xcrs; | |
4689 | void *buffer; | |
4690 | } u; | |
4691 | ||
9b062471 CD |
4692 | vcpu_load(vcpu); |
4693 | ||
d1ac91d8 | 4694 | u.buffer = NULL; |
313a3dc7 CO |
4695 | switch (ioctl) { |
4696 | case KVM_GET_LAPIC: { | |
2204ae3c | 4697 | r = -EINVAL; |
bce87cce | 4698 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 4699 | goto out; |
254272ce BG |
4700 | u.lapic = kzalloc(sizeof(struct kvm_lapic_state), |
4701 | GFP_KERNEL_ACCOUNT); | |
313a3dc7 | 4702 | |
b772ff36 | 4703 | r = -ENOMEM; |
d1ac91d8 | 4704 | if (!u.lapic) |
b772ff36 | 4705 | goto out; |
d1ac91d8 | 4706 | r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); |
313a3dc7 CO |
4707 | if (r) |
4708 | goto out; | |
4709 | r = -EFAULT; | |
d1ac91d8 | 4710 | if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
4711 | goto out; |
4712 | r = 0; | |
4713 | break; | |
4714 | } | |
4715 | case KVM_SET_LAPIC: { | |
2204ae3c | 4716 | r = -EINVAL; |
bce87cce | 4717 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 4718 | goto out; |
ff5c2c03 | 4719 | u.lapic = memdup_user(argp, sizeof(*u.lapic)); |
9b062471 CD |
4720 | if (IS_ERR(u.lapic)) { |
4721 | r = PTR_ERR(u.lapic); | |
4722 | goto out_nofree; | |
4723 | } | |
ff5c2c03 | 4724 | |
d1ac91d8 | 4725 | r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); |
313a3dc7 CO |
4726 | break; |
4727 | } | |
f77bc6a4 ZX |
4728 | case KVM_INTERRUPT: { |
4729 | struct kvm_interrupt irq; | |
4730 | ||
4731 | r = -EFAULT; | |
0e96f31e | 4732 | if (copy_from_user(&irq, argp, sizeof(irq))) |
f77bc6a4 ZX |
4733 | goto out; |
4734 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
f77bc6a4 ZX |
4735 | break; |
4736 | } | |
c4abb7c9 JK |
4737 | case KVM_NMI: { |
4738 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
c4abb7c9 JK |
4739 | break; |
4740 | } | |
f077825a PB |
4741 | case KVM_SMI: { |
4742 | r = kvm_vcpu_ioctl_smi(vcpu); | |
4743 | break; | |
4744 | } | |
313a3dc7 CO |
4745 | case KVM_SET_CPUID: { |
4746 | struct kvm_cpuid __user *cpuid_arg = argp; | |
4747 | struct kvm_cpuid cpuid; | |
4748 | ||
4749 | r = -EFAULT; | |
0e96f31e | 4750 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
313a3dc7 CO |
4751 | goto out; |
4752 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
313a3dc7 CO |
4753 | break; |
4754 | } | |
07716717 DK |
4755 | case KVM_SET_CPUID2: { |
4756 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
4757 | struct kvm_cpuid2 cpuid; | |
4758 | ||
4759 | r = -EFAULT; | |
0e96f31e | 4760 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
07716717 DK |
4761 | goto out; |
4762 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 4763 | cpuid_arg->entries); |
07716717 DK |
4764 | break; |
4765 | } | |
4766 | case KVM_GET_CPUID2: { | |
4767 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
4768 | struct kvm_cpuid2 cpuid; | |
4769 | ||
4770 | r = -EFAULT; | |
0e96f31e | 4771 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
07716717 DK |
4772 | goto out; |
4773 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 4774 | cpuid_arg->entries); |
07716717 DK |
4775 | if (r) |
4776 | goto out; | |
4777 | r = -EFAULT; | |
0e96f31e | 4778 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) |
07716717 DK |
4779 | goto out; |
4780 | r = 0; | |
4781 | break; | |
4782 | } | |
801e459a TL |
4783 | case KVM_GET_MSRS: { |
4784 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
609e36d3 | 4785 | r = msr_io(vcpu, argp, do_get_msr, 1); |
801e459a | 4786 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 4787 | break; |
801e459a TL |
4788 | } |
4789 | case KVM_SET_MSRS: { | |
4790 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
313a3dc7 | 4791 | r = msr_io(vcpu, argp, do_set_msr, 0); |
801e459a | 4792 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 4793 | break; |
801e459a | 4794 | } |
b209749f AK |
4795 | case KVM_TPR_ACCESS_REPORTING: { |
4796 | struct kvm_tpr_access_ctl tac; | |
4797 | ||
4798 | r = -EFAULT; | |
0e96f31e | 4799 | if (copy_from_user(&tac, argp, sizeof(tac))) |
b209749f AK |
4800 | goto out; |
4801 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
4802 | if (r) | |
4803 | goto out; | |
4804 | r = -EFAULT; | |
0e96f31e | 4805 | if (copy_to_user(argp, &tac, sizeof(tac))) |
b209749f AK |
4806 | goto out; |
4807 | r = 0; | |
4808 | break; | |
4809 | }; | |
b93463aa AK |
4810 | case KVM_SET_VAPIC_ADDR: { |
4811 | struct kvm_vapic_addr va; | |
7301d6ab | 4812 | int idx; |
b93463aa AK |
4813 | |
4814 | r = -EINVAL; | |
35754c98 | 4815 | if (!lapic_in_kernel(vcpu)) |
b93463aa AK |
4816 | goto out; |
4817 | r = -EFAULT; | |
0e96f31e | 4818 | if (copy_from_user(&va, argp, sizeof(va))) |
b93463aa | 4819 | goto out; |
7301d6ab | 4820 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
fda4e2e8 | 4821 | r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); |
7301d6ab | 4822 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b93463aa AK |
4823 | break; |
4824 | } | |
890ca9ae HY |
4825 | case KVM_X86_SETUP_MCE: { |
4826 | u64 mcg_cap; | |
4827 | ||
4828 | r = -EFAULT; | |
0e96f31e | 4829 | if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) |
890ca9ae HY |
4830 | goto out; |
4831 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
4832 | break; | |
4833 | } | |
4834 | case KVM_X86_SET_MCE: { | |
4835 | struct kvm_x86_mce mce; | |
4836 | ||
4837 | r = -EFAULT; | |
0e96f31e | 4838 | if (copy_from_user(&mce, argp, sizeof(mce))) |
890ca9ae HY |
4839 | goto out; |
4840 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
4841 | break; | |
4842 | } | |
3cfc3092 JK |
4843 | case KVM_GET_VCPU_EVENTS: { |
4844 | struct kvm_vcpu_events events; | |
4845 | ||
4846 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
4847 | ||
4848 | r = -EFAULT; | |
4849 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
4850 | break; | |
4851 | r = 0; | |
4852 | break; | |
4853 | } | |
4854 | case KVM_SET_VCPU_EVENTS: { | |
4855 | struct kvm_vcpu_events events; | |
4856 | ||
4857 | r = -EFAULT; | |
4858 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
4859 | break; | |
4860 | ||
4861 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
4862 | break; | |
4863 | } | |
a1efbe77 JK |
4864 | case KVM_GET_DEBUGREGS: { |
4865 | struct kvm_debugregs dbgregs; | |
4866 | ||
4867 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
4868 | ||
4869 | r = -EFAULT; | |
4870 | if (copy_to_user(argp, &dbgregs, | |
4871 | sizeof(struct kvm_debugregs))) | |
4872 | break; | |
4873 | r = 0; | |
4874 | break; | |
4875 | } | |
4876 | case KVM_SET_DEBUGREGS: { | |
4877 | struct kvm_debugregs dbgregs; | |
4878 | ||
4879 | r = -EFAULT; | |
4880 | if (copy_from_user(&dbgregs, argp, | |
4881 | sizeof(struct kvm_debugregs))) | |
4882 | break; | |
4883 | ||
4884 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
4885 | break; | |
4886 | } | |
2d5b5a66 | 4887 | case KVM_GET_XSAVE: { |
254272ce | 4888 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); |
2d5b5a66 | 4889 | r = -ENOMEM; |
d1ac91d8 | 4890 | if (!u.xsave) |
2d5b5a66 SY |
4891 | break; |
4892 | ||
d1ac91d8 | 4893 | kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
4894 | |
4895 | r = -EFAULT; | |
d1ac91d8 | 4896 | if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
4897 | break; |
4898 | r = 0; | |
4899 | break; | |
4900 | } | |
4901 | case KVM_SET_XSAVE: { | |
ff5c2c03 | 4902 | u.xsave = memdup_user(argp, sizeof(*u.xsave)); |
9b062471 CD |
4903 | if (IS_ERR(u.xsave)) { |
4904 | r = PTR_ERR(u.xsave); | |
4905 | goto out_nofree; | |
4906 | } | |
2d5b5a66 | 4907 | |
d1ac91d8 | 4908 | r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
4909 | break; |
4910 | } | |
4911 | case KVM_GET_XCRS: { | |
254272ce | 4912 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); |
2d5b5a66 | 4913 | r = -ENOMEM; |
d1ac91d8 | 4914 | if (!u.xcrs) |
2d5b5a66 SY |
4915 | break; |
4916 | ||
d1ac91d8 | 4917 | kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
4918 | |
4919 | r = -EFAULT; | |
d1ac91d8 | 4920 | if (copy_to_user(argp, u.xcrs, |
2d5b5a66 SY |
4921 | sizeof(struct kvm_xcrs))) |
4922 | break; | |
4923 | r = 0; | |
4924 | break; | |
4925 | } | |
4926 | case KVM_SET_XCRS: { | |
ff5c2c03 | 4927 | u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); |
9b062471 CD |
4928 | if (IS_ERR(u.xcrs)) { |
4929 | r = PTR_ERR(u.xcrs); | |
4930 | goto out_nofree; | |
4931 | } | |
2d5b5a66 | 4932 | |
d1ac91d8 | 4933 | r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
4934 | break; |
4935 | } | |
92a1f12d JR |
4936 | case KVM_SET_TSC_KHZ: { |
4937 | u32 user_tsc_khz; | |
4938 | ||
4939 | r = -EINVAL; | |
92a1f12d JR |
4940 | user_tsc_khz = (u32)arg; |
4941 | ||
26769f96 MT |
4942 | if (kvm_has_tsc_control && |
4943 | user_tsc_khz >= kvm_max_guest_tsc_khz) | |
92a1f12d JR |
4944 | goto out; |
4945 | ||
cc578287 ZA |
4946 | if (user_tsc_khz == 0) |
4947 | user_tsc_khz = tsc_khz; | |
4948 | ||
381d585c HZ |
4949 | if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) |
4950 | r = 0; | |
92a1f12d | 4951 | |
92a1f12d JR |
4952 | goto out; |
4953 | } | |
4954 | case KVM_GET_TSC_KHZ: { | |
cc578287 | 4955 | r = vcpu->arch.virtual_tsc_khz; |
92a1f12d JR |
4956 | goto out; |
4957 | } | |
1c0b28c2 EM |
4958 | case KVM_KVMCLOCK_CTRL: { |
4959 | r = kvm_set_guest_paused(vcpu); | |
4960 | goto out; | |
4961 | } | |
5c919412 AS |
4962 | case KVM_ENABLE_CAP: { |
4963 | struct kvm_enable_cap cap; | |
4964 | ||
4965 | r = -EFAULT; | |
4966 | if (copy_from_user(&cap, argp, sizeof(cap))) | |
4967 | goto out; | |
4968 | r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); | |
4969 | break; | |
4970 | } | |
8fcc4b59 JM |
4971 | case KVM_GET_NESTED_STATE: { |
4972 | struct kvm_nested_state __user *user_kvm_nested_state = argp; | |
4973 | u32 user_data_size; | |
4974 | ||
4975 | r = -EINVAL; | |
33b22172 | 4976 | if (!kvm_x86_ops.nested_ops->get_state) |
8fcc4b59 JM |
4977 | break; |
4978 | ||
4979 | BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); | |
26b471c7 | 4980 | r = -EFAULT; |
8fcc4b59 | 4981 | if (get_user(user_data_size, &user_kvm_nested_state->size)) |
26b471c7 | 4982 | break; |
8fcc4b59 | 4983 | |
33b22172 PB |
4984 | r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state, |
4985 | user_data_size); | |
8fcc4b59 | 4986 | if (r < 0) |
26b471c7 | 4987 | break; |
8fcc4b59 JM |
4988 | |
4989 | if (r > user_data_size) { | |
4990 | if (put_user(r, &user_kvm_nested_state->size)) | |
26b471c7 LA |
4991 | r = -EFAULT; |
4992 | else | |
4993 | r = -E2BIG; | |
4994 | break; | |
8fcc4b59 | 4995 | } |
26b471c7 | 4996 | |
8fcc4b59 JM |
4997 | r = 0; |
4998 | break; | |
4999 | } | |
5000 | case KVM_SET_NESTED_STATE: { | |
5001 | struct kvm_nested_state __user *user_kvm_nested_state = argp; | |
5002 | struct kvm_nested_state kvm_state; | |
ad5996d9 | 5003 | int idx; |
8fcc4b59 JM |
5004 | |
5005 | r = -EINVAL; | |
33b22172 | 5006 | if (!kvm_x86_ops.nested_ops->set_state) |
8fcc4b59 JM |
5007 | break; |
5008 | ||
26b471c7 | 5009 | r = -EFAULT; |
8fcc4b59 | 5010 | if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) |
26b471c7 | 5011 | break; |
8fcc4b59 | 5012 | |
26b471c7 | 5013 | r = -EINVAL; |
8fcc4b59 | 5014 | if (kvm_state.size < sizeof(kvm_state)) |
26b471c7 | 5015 | break; |
8fcc4b59 JM |
5016 | |
5017 | if (kvm_state.flags & | |
8cab6507 | 5018 | ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE |
cc440cda PB |
5019 | | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING |
5020 | | KVM_STATE_NESTED_GIF_SET)) | |
26b471c7 | 5021 | break; |
8fcc4b59 JM |
5022 | |
5023 | /* nested_run_pending implies guest_mode. */ | |
8cab6507 VK |
5024 | if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) |
5025 | && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) | |
26b471c7 | 5026 | break; |
8fcc4b59 | 5027 | |
ad5996d9 | 5028 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
33b22172 | 5029 | r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state); |
ad5996d9 | 5030 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8fcc4b59 JM |
5031 | break; |
5032 | } | |
c21d54f0 VK |
5033 | case KVM_GET_SUPPORTED_HV_CPUID: |
5034 | r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp); | |
2bc39970 | 5035 | break; |
313a3dc7 CO |
5036 | default: |
5037 | r = -EINVAL; | |
5038 | } | |
5039 | out: | |
d1ac91d8 | 5040 | kfree(u.buffer); |
9b062471 CD |
5041 | out_nofree: |
5042 | vcpu_put(vcpu); | |
313a3dc7 CO |
5043 | return r; |
5044 | } | |
5045 | ||
1499fa80 | 5046 | vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) |
5b1c1493 CO |
5047 | { |
5048 | return VM_FAULT_SIGBUS; | |
5049 | } | |
5050 | ||
1fe779f8 CO |
5051 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
5052 | { | |
5053 | int ret; | |
5054 | ||
5055 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
951179ce | 5056 | return -EINVAL; |
afaf0b2f | 5057 | ret = kvm_x86_ops.set_tss_addr(kvm, addr); |
1fe779f8 CO |
5058 | return ret; |
5059 | } | |
5060 | ||
b927a3ce SY |
5061 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
5062 | u64 ident_addr) | |
5063 | { | |
afaf0b2f | 5064 | return kvm_x86_ops.set_identity_map_addr(kvm, ident_addr); |
b927a3ce SY |
5065 | } |
5066 | ||
1fe779f8 | 5067 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
bc8a3d89 | 5068 | unsigned long kvm_nr_mmu_pages) |
1fe779f8 CO |
5069 | { |
5070 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
5071 | return -EINVAL; | |
5072 | ||
79fac95e | 5073 | mutex_lock(&kvm->slots_lock); |
1fe779f8 CO |
5074 | |
5075 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 5076 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 5077 | |
79fac95e | 5078 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
5079 | return 0; |
5080 | } | |
5081 | ||
bc8a3d89 | 5082 | static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) |
1fe779f8 | 5083 | { |
39de71ec | 5084 | return kvm->arch.n_max_mmu_pages; |
1fe779f8 CO |
5085 | } |
5086 | ||
1fe779f8 CO |
5087 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) |
5088 | { | |
90bca052 | 5089 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
5090 | int r; |
5091 | ||
5092 | r = 0; | |
5093 | switch (chip->chip_id) { | |
5094 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 | 5095 | memcpy(&chip->chip.pic, &pic->pics[0], |
1fe779f8 CO |
5096 | sizeof(struct kvm_pic_state)); |
5097 | break; | |
5098 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 | 5099 | memcpy(&chip->chip.pic, &pic->pics[1], |
1fe779f8 CO |
5100 | sizeof(struct kvm_pic_state)); |
5101 | break; | |
5102 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 5103 | kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
5104 | break; |
5105 | default: | |
5106 | r = -EINVAL; | |
5107 | break; | |
5108 | } | |
5109 | return r; | |
5110 | } | |
5111 | ||
5112 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
5113 | { | |
90bca052 | 5114 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
5115 | int r; |
5116 | ||
5117 | r = 0; | |
5118 | switch (chip->chip_id) { | |
5119 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 DH |
5120 | spin_lock(&pic->lock); |
5121 | memcpy(&pic->pics[0], &chip->chip.pic, | |
1fe779f8 | 5122 | sizeof(struct kvm_pic_state)); |
90bca052 | 5123 | spin_unlock(&pic->lock); |
1fe779f8 CO |
5124 | break; |
5125 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 DH |
5126 | spin_lock(&pic->lock); |
5127 | memcpy(&pic->pics[1], &chip->chip.pic, | |
1fe779f8 | 5128 | sizeof(struct kvm_pic_state)); |
90bca052 | 5129 | spin_unlock(&pic->lock); |
1fe779f8 CO |
5130 | break; |
5131 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 5132 | kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
5133 | break; |
5134 | default: | |
5135 | r = -EINVAL; | |
5136 | break; | |
5137 | } | |
90bca052 | 5138 | kvm_pic_update_irq(pic); |
1fe779f8 CO |
5139 | return r; |
5140 | } | |
5141 | ||
e0f63cb9 SY |
5142 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
5143 | { | |
34f3941c RK |
5144 | struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; |
5145 | ||
5146 | BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); | |
5147 | ||
5148 | mutex_lock(&kps->lock); | |
5149 | memcpy(ps, &kps->channels, sizeof(*ps)); | |
5150 | mutex_unlock(&kps->lock); | |
2da29bcc | 5151 | return 0; |
e0f63cb9 SY |
5152 | } |
5153 | ||
5154 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
5155 | { | |
0185604c | 5156 | int i; |
09edea72 RK |
5157 | struct kvm_pit *pit = kvm->arch.vpit; |
5158 | ||
5159 | mutex_lock(&pit->pit_state.lock); | |
34f3941c | 5160 | memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); |
0185604c | 5161 | for (i = 0; i < 3; i++) |
09edea72 RK |
5162 | kvm_pit_load_count(pit, i, ps->channels[i].count, 0); |
5163 | mutex_unlock(&pit->pit_state.lock); | |
2da29bcc | 5164 | return 0; |
e9f42757 BK |
5165 | } |
5166 | ||
5167 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
5168 | { | |
e9f42757 BK |
5169 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
5170 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
5171 | sizeof(ps->channels)); | |
5172 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
5173 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
97e69aa6 | 5174 | memset(&ps->reserved, 0, sizeof(ps->reserved)); |
2da29bcc | 5175 | return 0; |
e9f42757 BK |
5176 | } |
5177 | ||
5178 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
5179 | { | |
2da29bcc | 5180 | int start = 0; |
0185604c | 5181 | int i; |
e9f42757 | 5182 | u32 prev_legacy, cur_legacy; |
09edea72 RK |
5183 | struct kvm_pit *pit = kvm->arch.vpit; |
5184 | ||
5185 | mutex_lock(&pit->pit_state.lock); | |
5186 | prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
e9f42757 BK |
5187 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; |
5188 | if (!prev_legacy && cur_legacy) | |
5189 | start = 1; | |
09edea72 RK |
5190 | memcpy(&pit->pit_state.channels, &ps->channels, |
5191 | sizeof(pit->pit_state.channels)); | |
5192 | pit->pit_state.flags = ps->flags; | |
0185604c | 5193 | for (i = 0; i < 3; i++) |
09edea72 | 5194 | kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, |
e5e57e7a | 5195 | start && i == 0); |
09edea72 | 5196 | mutex_unlock(&pit->pit_state.lock); |
2da29bcc | 5197 | return 0; |
e0f63cb9 SY |
5198 | } |
5199 | ||
52d939a0 MT |
5200 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
5201 | struct kvm_reinject_control *control) | |
5202 | { | |
71474e2f RK |
5203 | struct kvm_pit *pit = kvm->arch.vpit; |
5204 | ||
71474e2f RK |
5205 | /* pit->pit_state.lock was overloaded to prevent userspace from getting |
5206 | * an inconsistent state after running multiple KVM_REINJECT_CONTROL | |
5207 | * ioctls in parallel. Use a separate lock if that ioctl isn't rare. | |
5208 | */ | |
5209 | mutex_lock(&pit->pit_state.lock); | |
5210 | kvm_pit_set_reinject(pit, control->pit_reinject); | |
5211 | mutex_unlock(&pit->pit_state.lock); | |
b39c90b6 | 5212 | |
52d939a0 MT |
5213 | return 0; |
5214 | } | |
5215 | ||
0dff0846 | 5216 | void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) |
5bb064dc | 5217 | { |
88178fd4 KH |
5218 | /* |
5219 | * Flush potentially hardware-cached dirty pages to dirty_bitmap. | |
5220 | */ | |
afaf0b2f SC |
5221 | if (kvm_x86_ops.flush_log_dirty) |
5222 | kvm_x86_ops.flush_log_dirty(kvm); | |
5bb064dc ZX |
5223 | } |
5224 | ||
aa2fbe6d YZ |
5225 | int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, |
5226 | bool line_status) | |
23d43cf9 CD |
5227 | { |
5228 | if (!irqchip_in_kernel(kvm)) | |
5229 | return -ENXIO; | |
5230 | ||
5231 | irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, | |
aa2fbe6d YZ |
5232 | irq_event->irq, irq_event->level, |
5233 | line_status); | |
23d43cf9 CD |
5234 | return 0; |
5235 | } | |
5236 | ||
e5d83c74 PB |
5237 | int kvm_vm_ioctl_enable_cap(struct kvm *kvm, |
5238 | struct kvm_enable_cap *cap) | |
90de4a18 NA |
5239 | { |
5240 | int r; | |
5241 | ||
5242 | if (cap->flags) | |
5243 | return -EINVAL; | |
5244 | ||
5245 | switch (cap->cap) { | |
5246 | case KVM_CAP_DISABLE_QUIRKS: | |
5247 | kvm->arch.disabled_quirks = cap->args[0]; | |
5248 | r = 0; | |
5249 | break; | |
49df6397 SR |
5250 | case KVM_CAP_SPLIT_IRQCHIP: { |
5251 | mutex_lock(&kvm->lock); | |
b053b2ae SR |
5252 | r = -EINVAL; |
5253 | if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) | |
5254 | goto split_irqchip_unlock; | |
49df6397 SR |
5255 | r = -EEXIST; |
5256 | if (irqchip_in_kernel(kvm)) | |
5257 | goto split_irqchip_unlock; | |
557abc40 | 5258 | if (kvm->created_vcpus) |
49df6397 SR |
5259 | goto split_irqchip_unlock; |
5260 | r = kvm_setup_empty_irq_routing(kvm); | |
5c0aea0e | 5261 | if (r) |
49df6397 SR |
5262 | goto split_irqchip_unlock; |
5263 | /* Pairs with irqchip_in_kernel. */ | |
5264 | smp_wmb(); | |
49776faf | 5265 | kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; |
b053b2ae | 5266 | kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; |
49df6397 SR |
5267 | r = 0; |
5268 | split_irqchip_unlock: | |
5269 | mutex_unlock(&kvm->lock); | |
5270 | break; | |
5271 | } | |
37131313 RK |
5272 | case KVM_CAP_X2APIC_API: |
5273 | r = -EINVAL; | |
5274 | if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) | |
5275 | break; | |
5276 | ||
5277 | if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) | |
5278 | kvm->arch.x2apic_format = true; | |
c519265f RK |
5279 | if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) |
5280 | kvm->arch.x2apic_broadcast_quirk_disabled = true; | |
37131313 RK |
5281 | |
5282 | r = 0; | |
5283 | break; | |
4d5422ce WL |
5284 | case KVM_CAP_X86_DISABLE_EXITS: |
5285 | r = -EINVAL; | |
5286 | if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) | |
5287 | break; | |
5288 | ||
5289 | if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && | |
5290 | kvm_can_mwait_in_guest()) | |
5291 | kvm->arch.mwait_in_guest = true; | |
766d3571 | 5292 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) |
caa057a2 | 5293 | kvm->arch.hlt_in_guest = true; |
b31c114b WL |
5294 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) |
5295 | kvm->arch.pause_in_guest = true; | |
b5170063 WL |
5296 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) |
5297 | kvm->arch.cstate_in_guest = true; | |
4d5422ce WL |
5298 | r = 0; |
5299 | break; | |
6fbbde9a DS |
5300 | case KVM_CAP_MSR_PLATFORM_INFO: |
5301 | kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; | |
5302 | r = 0; | |
c4f55198 JM |
5303 | break; |
5304 | case KVM_CAP_EXCEPTION_PAYLOAD: | |
5305 | kvm->arch.exception_payload_enabled = cap->args[0]; | |
5306 | r = 0; | |
6fbbde9a | 5307 | break; |
1ae09954 AG |
5308 | case KVM_CAP_X86_USER_SPACE_MSR: |
5309 | kvm->arch.user_space_msr_mask = cap->args[0]; | |
5310 | r = 0; | |
5311 | break; | |
fe6b6bc8 CQ |
5312 | case KVM_CAP_X86_BUS_LOCK_EXIT: |
5313 | r = -EINVAL; | |
5314 | if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE) | |
5315 | break; | |
5316 | ||
5317 | if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) && | |
5318 | (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)) | |
5319 | break; | |
5320 | ||
5321 | if (kvm_has_bus_lock_exit && | |
5322 | cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT) | |
5323 | kvm->arch.bus_lock_detection_enabled = true; | |
5324 | r = 0; | |
5325 | break; | |
90de4a18 NA |
5326 | default: |
5327 | r = -EINVAL; | |
5328 | break; | |
5329 | } | |
5330 | return r; | |
5331 | } | |
5332 | ||
1a155254 AG |
5333 | static void kvm_clear_msr_filter(struct kvm *kvm) |
5334 | { | |
5335 | u32 i; | |
5336 | u32 count = kvm->arch.msr_filter.count; | |
5337 | struct msr_bitmap_range ranges[16]; | |
5338 | ||
5339 | mutex_lock(&kvm->lock); | |
5340 | kvm->arch.msr_filter.count = 0; | |
5341 | memcpy(ranges, kvm->arch.msr_filter.ranges, count * sizeof(ranges[0])); | |
5342 | mutex_unlock(&kvm->lock); | |
5343 | synchronize_srcu(&kvm->srcu); | |
5344 | ||
5345 | for (i = 0; i < count; i++) | |
5346 | kfree(ranges[i].bitmap); | |
5347 | } | |
5348 | ||
5349 | static int kvm_add_msr_filter(struct kvm *kvm, struct kvm_msr_filter_range *user_range) | |
5350 | { | |
5351 | struct msr_bitmap_range *ranges = kvm->arch.msr_filter.ranges; | |
5352 | struct msr_bitmap_range range; | |
5353 | unsigned long *bitmap = NULL; | |
5354 | size_t bitmap_size; | |
5355 | int r; | |
5356 | ||
5357 | if (!user_range->nmsrs) | |
5358 | return 0; | |
5359 | ||
5360 | bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long); | |
5361 | if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE) | |
5362 | return -EINVAL; | |
5363 | ||
5364 | bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size); | |
5365 | if (IS_ERR(bitmap)) | |
5366 | return PTR_ERR(bitmap); | |
5367 | ||
5368 | range = (struct msr_bitmap_range) { | |
5369 | .flags = user_range->flags, | |
5370 | .base = user_range->base, | |
5371 | .nmsrs = user_range->nmsrs, | |
5372 | .bitmap = bitmap, | |
5373 | }; | |
5374 | ||
5375 | if (range.flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) { | |
5376 | r = -EINVAL; | |
5377 | goto err; | |
5378 | } | |
5379 | ||
5380 | if (!range.flags) { | |
5381 | r = -EINVAL; | |
5382 | goto err; | |
5383 | } | |
5384 | ||
5385 | /* Everything ok, add this range identifier to our global pool */ | |
5386 | ranges[kvm->arch.msr_filter.count] = range; | |
5387 | /* Make sure we filled the array before we tell anyone to walk it */ | |
5388 | smp_wmb(); | |
5389 | kvm->arch.msr_filter.count++; | |
5390 | ||
5391 | return 0; | |
5392 | err: | |
5393 | kfree(bitmap); | |
5394 | return r; | |
5395 | } | |
5396 | ||
5397 | static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp) | |
5398 | { | |
5399 | struct kvm_msr_filter __user *user_msr_filter = argp; | |
5400 | struct kvm_msr_filter filter; | |
5401 | bool default_allow; | |
5402 | int r = 0; | |
043248b3 | 5403 | bool empty = true; |
1a155254 AG |
5404 | u32 i; |
5405 | ||
5406 | if (copy_from_user(&filter, user_msr_filter, sizeof(filter))) | |
5407 | return -EFAULT; | |
5408 | ||
043248b3 PB |
5409 | for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) |
5410 | empty &= !filter.ranges[i].nmsrs; | |
1a155254 AG |
5411 | |
5412 | default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY); | |
043248b3 PB |
5413 | if (empty && !default_allow) |
5414 | return -EINVAL; | |
5415 | ||
5416 | kvm_clear_msr_filter(kvm); | |
5417 | ||
1a155254 AG |
5418 | kvm->arch.msr_filter.default_allow = default_allow; |
5419 | ||
5420 | /* | |
5421 | * Protect from concurrent calls to this function that could trigger | |
5422 | * a TOCTOU violation on kvm->arch.msr_filter.count. | |
5423 | */ | |
5424 | mutex_lock(&kvm->lock); | |
5425 | for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) { | |
5426 | r = kvm_add_msr_filter(kvm, &filter.ranges[i]); | |
5427 | if (r) | |
5428 | break; | |
5429 | } | |
5430 | ||
5431 | kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED); | |
5432 | mutex_unlock(&kvm->lock); | |
5433 | ||
5434 | return r; | |
5435 | } | |
5436 | ||
1fe779f8 CO |
5437 | long kvm_arch_vm_ioctl(struct file *filp, |
5438 | unsigned int ioctl, unsigned long arg) | |
5439 | { | |
5440 | struct kvm *kvm = filp->private_data; | |
5441 | void __user *argp = (void __user *)arg; | |
367e1319 | 5442 | int r = -ENOTTY; |
f0d66275 DH |
5443 | /* |
5444 | * This union makes it completely explicit to gcc-3.x | |
5445 | * that these two variables' stack usage should be | |
5446 | * combined, not added together. | |
5447 | */ | |
5448 | union { | |
5449 | struct kvm_pit_state ps; | |
e9f42757 | 5450 | struct kvm_pit_state2 ps2; |
c5ff41ce | 5451 | struct kvm_pit_config pit_config; |
f0d66275 | 5452 | } u; |
1fe779f8 CO |
5453 | |
5454 | switch (ioctl) { | |
5455 | case KVM_SET_TSS_ADDR: | |
5456 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
1fe779f8 | 5457 | break; |
b927a3ce SY |
5458 | case KVM_SET_IDENTITY_MAP_ADDR: { |
5459 | u64 ident_addr; | |
5460 | ||
1af1ac91 DH |
5461 | mutex_lock(&kvm->lock); |
5462 | r = -EINVAL; | |
5463 | if (kvm->created_vcpus) | |
5464 | goto set_identity_unlock; | |
b927a3ce | 5465 | r = -EFAULT; |
0e96f31e | 5466 | if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) |
1af1ac91 | 5467 | goto set_identity_unlock; |
b927a3ce | 5468 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); |
1af1ac91 DH |
5469 | set_identity_unlock: |
5470 | mutex_unlock(&kvm->lock); | |
b927a3ce SY |
5471 | break; |
5472 | } | |
1fe779f8 CO |
5473 | case KVM_SET_NR_MMU_PAGES: |
5474 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
1fe779f8 CO |
5475 | break; |
5476 | case KVM_GET_NR_MMU_PAGES: | |
5477 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
5478 | break; | |
3ddea128 | 5479 | case KVM_CREATE_IRQCHIP: { |
3ddea128 | 5480 | mutex_lock(&kvm->lock); |
09941366 | 5481 | |
3ddea128 | 5482 | r = -EEXIST; |
35e6eaa3 | 5483 | if (irqchip_in_kernel(kvm)) |
3ddea128 | 5484 | goto create_irqchip_unlock; |
09941366 | 5485 | |
3e515705 | 5486 | r = -EINVAL; |
557abc40 | 5487 | if (kvm->created_vcpus) |
3e515705 | 5488 | goto create_irqchip_unlock; |
09941366 RK |
5489 | |
5490 | r = kvm_pic_init(kvm); | |
5491 | if (r) | |
3ddea128 | 5492 | goto create_irqchip_unlock; |
09941366 RK |
5493 | |
5494 | r = kvm_ioapic_init(kvm); | |
5495 | if (r) { | |
09941366 | 5496 | kvm_pic_destroy(kvm); |
3ddea128 | 5497 | goto create_irqchip_unlock; |
09941366 RK |
5498 | } |
5499 | ||
399ec807 AK |
5500 | r = kvm_setup_default_irq_routing(kvm); |
5501 | if (r) { | |
72bb2fcd | 5502 | kvm_ioapic_destroy(kvm); |
09941366 | 5503 | kvm_pic_destroy(kvm); |
71ba994c | 5504 | goto create_irqchip_unlock; |
399ec807 | 5505 | } |
49776faf | 5506 | /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ |
71ba994c | 5507 | smp_wmb(); |
49776faf | 5508 | kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; |
3ddea128 MT |
5509 | create_irqchip_unlock: |
5510 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 5511 | break; |
3ddea128 | 5512 | } |
7837699f | 5513 | case KVM_CREATE_PIT: |
c5ff41ce JK |
5514 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
5515 | goto create_pit; | |
5516 | case KVM_CREATE_PIT2: | |
5517 | r = -EFAULT; | |
5518 | if (copy_from_user(&u.pit_config, argp, | |
5519 | sizeof(struct kvm_pit_config))) | |
5520 | goto out; | |
5521 | create_pit: | |
250715a6 | 5522 | mutex_lock(&kvm->lock); |
269e05e4 AK |
5523 | r = -EEXIST; |
5524 | if (kvm->arch.vpit) | |
5525 | goto create_pit_unlock; | |
7837699f | 5526 | r = -ENOMEM; |
c5ff41ce | 5527 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
5528 | if (kvm->arch.vpit) |
5529 | r = 0; | |
269e05e4 | 5530 | create_pit_unlock: |
250715a6 | 5531 | mutex_unlock(&kvm->lock); |
7837699f | 5532 | break; |
1fe779f8 CO |
5533 | case KVM_GET_IRQCHIP: { |
5534 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 5535 | struct kvm_irqchip *chip; |
1fe779f8 | 5536 | |
ff5c2c03 SL |
5537 | chip = memdup_user(argp, sizeof(*chip)); |
5538 | if (IS_ERR(chip)) { | |
5539 | r = PTR_ERR(chip); | |
1fe779f8 | 5540 | goto out; |
ff5c2c03 SL |
5541 | } |
5542 | ||
1fe779f8 | 5543 | r = -ENXIO; |
826da321 | 5544 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
5545 | goto get_irqchip_out; |
5546 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 5547 | if (r) |
f0d66275 | 5548 | goto get_irqchip_out; |
1fe779f8 | 5549 | r = -EFAULT; |
0e96f31e | 5550 | if (copy_to_user(argp, chip, sizeof(*chip))) |
f0d66275 | 5551 | goto get_irqchip_out; |
1fe779f8 | 5552 | r = 0; |
f0d66275 DH |
5553 | get_irqchip_out: |
5554 | kfree(chip); | |
1fe779f8 CO |
5555 | break; |
5556 | } | |
5557 | case KVM_SET_IRQCHIP: { | |
5558 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 5559 | struct kvm_irqchip *chip; |
1fe779f8 | 5560 | |
ff5c2c03 SL |
5561 | chip = memdup_user(argp, sizeof(*chip)); |
5562 | if (IS_ERR(chip)) { | |
5563 | r = PTR_ERR(chip); | |
1fe779f8 | 5564 | goto out; |
ff5c2c03 SL |
5565 | } |
5566 | ||
1fe779f8 | 5567 | r = -ENXIO; |
826da321 | 5568 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
5569 | goto set_irqchip_out; |
5570 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
f0d66275 DH |
5571 | set_irqchip_out: |
5572 | kfree(chip); | |
1fe779f8 CO |
5573 | break; |
5574 | } | |
e0f63cb9 | 5575 | case KVM_GET_PIT: { |
e0f63cb9 | 5576 | r = -EFAULT; |
f0d66275 | 5577 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
5578 | goto out; |
5579 | r = -ENXIO; | |
5580 | if (!kvm->arch.vpit) | |
5581 | goto out; | |
f0d66275 | 5582 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
5583 | if (r) |
5584 | goto out; | |
5585 | r = -EFAULT; | |
f0d66275 | 5586 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
5587 | goto out; |
5588 | r = 0; | |
5589 | break; | |
5590 | } | |
5591 | case KVM_SET_PIT: { | |
e0f63cb9 | 5592 | r = -EFAULT; |
0e96f31e | 5593 | if (copy_from_user(&u.ps, argp, sizeof(u.ps))) |
e0f63cb9 | 5594 | goto out; |
7289fdb5 | 5595 | mutex_lock(&kvm->lock); |
e0f63cb9 SY |
5596 | r = -ENXIO; |
5597 | if (!kvm->arch.vpit) | |
7289fdb5 | 5598 | goto set_pit_out; |
f0d66275 | 5599 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
7289fdb5 SR |
5600 | set_pit_out: |
5601 | mutex_unlock(&kvm->lock); | |
e0f63cb9 SY |
5602 | break; |
5603 | } | |
e9f42757 BK |
5604 | case KVM_GET_PIT2: { |
5605 | r = -ENXIO; | |
5606 | if (!kvm->arch.vpit) | |
5607 | goto out; | |
5608 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
5609 | if (r) | |
5610 | goto out; | |
5611 | r = -EFAULT; | |
5612 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
5613 | goto out; | |
5614 | r = 0; | |
5615 | break; | |
5616 | } | |
5617 | case KVM_SET_PIT2: { | |
5618 | r = -EFAULT; | |
5619 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
5620 | goto out; | |
7289fdb5 | 5621 | mutex_lock(&kvm->lock); |
e9f42757 BK |
5622 | r = -ENXIO; |
5623 | if (!kvm->arch.vpit) | |
7289fdb5 | 5624 | goto set_pit2_out; |
e9f42757 | 5625 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); |
7289fdb5 SR |
5626 | set_pit2_out: |
5627 | mutex_unlock(&kvm->lock); | |
e9f42757 BK |
5628 | break; |
5629 | } | |
52d939a0 MT |
5630 | case KVM_REINJECT_CONTROL: { |
5631 | struct kvm_reinject_control control; | |
5632 | r = -EFAULT; | |
5633 | if (copy_from_user(&control, argp, sizeof(control))) | |
5634 | goto out; | |
cad23e72 ML |
5635 | r = -ENXIO; |
5636 | if (!kvm->arch.vpit) | |
5637 | goto out; | |
52d939a0 | 5638 | r = kvm_vm_ioctl_reinject(kvm, &control); |
52d939a0 MT |
5639 | break; |
5640 | } | |
d71ba788 PB |
5641 | case KVM_SET_BOOT_CPU_ID: |
5642 | r = 0; | |
5643 | mutex_lock(&kvm->lock); | |
557abc40 | 5644 | if (kvm->created_vcpus) |
d71ba788 PB |
5645 | r = -EBUSY; |
5646 | else | |
5647 | kvm->arch.bsp_vcpu_id = arg; | |
5648 | mutex_unlock(&kvm->lock); | |
5649 | break; | |
ffde22ac | 5650 | case KVM_XEN_HVM_CONFIG: { |
51776043 | 5651 | struct kvm_xen_hvm_config xhc; |
ffde22ac | 5652 | r = -EFAULT; |
51776043 | 5653 | if (copy_from_user(&xhc, argp, sizeof(xhc))) |
ffde22ac ES |
5654 | goto out; |
5655 | r = -EINVAL; | |
51776043 | 5656 | if (xhc.flags) |
ffde22ac | 5657 | goto out; |
51776043 | 5658 | memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc)); |
ffde22ac ES |
5659 | r = 0; |
5660 | break; | |
5661 | } | |
afbcf7ab | 5662 | case KVM_SET_CLOCK: { |
afbcf7ab GC |
5663 | struct kvm_clock_data user_ns; |
5664 | u64 now_ns; | |
afbcf7ab GC |
5665 | |
5666 | r = -EFAULT; | |
5667 | if (copy_from_user(&user_ns, argp, sizeof(user_ns))) | |
5668 | goto out; | |
5669 | ||
5670 | r = -EINVAL; | |
5671 | if (user_ns.flags) | |
5672 | goto out; | |
5673 | ||
5674 | r = 0; | |
0bc48bea RK |
5675 | /* |
5676 | * TODO: userspace has to take care of races with VCPU_RUN, so | |
5677 | * kvm_gen_update_masterclock() can be cut down to locked | |
5678 | * pvclock_update_vm_gtod_copy(). | |
5679 | */ | |
5680 | kvm_gen_update_masterclock(kvm); | |
e891a32e | 5681 | now_ns = get_kvmclock_ns(kvm); |
108b249c | 5682 | kvm->arch.kvmclock_offset += user_ns.clock - now_ns; |
0bc48bea | 5683 | kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE); |
afbcf7ab GC |
5684 | break; |
5685 | } | |
5686 | case KVM_GET_CLOCK: { | |
afbcf7ab GC |
5687 | struct kvm_clock_data user_ns; |
5688 | u64 now_ns; | |
5689 | ||
e891a32e | 5690 | now_ns = get_kvmclock_ns(kvm); |
108b249c | 5691 | user_ns.clock = now_ns; |
e3fd9a93 | 5692 | user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; |
97e69aa6 | 5693 | memset(&user_ns.pad, 0, sizeof(user_ns.pad)); |
afbcf7ab GC |
5694 | |
5695 | r = -EFAULT; | |
5696 | if (copy_to_user(argp, &user_ns, sizeof(user_ns))) | |
5697 | goto out; | |
5698 | r = 0; | |
5699 | break; | |
5700 | } | |
5acc5c06 BS |
5701 | case KVM_MEMORY_ENCRYPT_OP: { |
5702 | r = -ENOTTY; | |
afaf0b2f SC |
5703 | if (kvm_x86_ops.mem_enc_op) |
5704 | r = kvm_x86_ops.mem_enc_op(kvm, argp); | |
5acc5c06 BS |
5705 | break; |
5706 | } | |
69eaedee BS |
5707 | case KVM_MEMORY_ENCRYPT_REG_REGION: { |
5708 | struct kvm_enc_region region; | |
5709 | ||
5710 | r = -EFAULT; | |
5711 | if (copy_from_user(®ion, argp, sizeof(region))) | |
5712 | goto out; | |
5713 | ||
5714 | r = -ENOTTY; | |
afaf0b2f SC |
5715 | if (kvm_x86_ops.mem_enc_reg_region) |
5716 | r = kvm_x86_ops.mem_enc_reg_region(kvm, ®ion); | |
69eaedee BS |
5717 | break; |
5718 | } | |
5719 | case KVM_MEMORY_ENCRYPT_UNREG_REGION: { | |
5720 | struct kvm_enc_region region; | |
5721 | ||
5722 | r = -EFAULT; | |
5723 | if (copy_from_user(®ion, argp, sizeof(region))) | |
5724 | goto out; | |
5725 | ||
5726 | r = -ENOTTY; | |
afaf0b2f SC |
5727 | if (kvm_x86_ops.mem_enc_unreg_region) |
5728 | r = kvm_x86_ops.mem_enc_unreg_region(kvm, ®ion); | |
69eaedee BS |
5729 | break; |
5730 | } | |
faeb7833 RK |
5731 | case KVM_HYPERV_EVENTFD: { |
5732 | struct kvm_hyperv_eventfd hvevfd; | |
5733 | ||
5734 | r = -EFAULT; | |
5735 | if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) | |
5736 | goto out; | |
5737 | r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); | |
5738 | break; | |
5739 | } | |
66bb8a06 EH |
5740 | case KVM_SET_PMU_EVENT_FILTER: |
5741 | r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); | |
5742 | break; | |
1a155254 AG |
5743 | case KVM_X86_SET_MSR_FILTER: |
5744 | r = kvm_vm_ioctl_set_msr_filter(kvm, argp); | |
5745 | break; | |
1fe779f8 | 5746 | default: |
ad6260da | 5747 | r = -ENOTTY; |
1fe779f8 CO |
5748 | } |
5749 | out: | |
5750 | return r; | |
5751 | } | |
5752 | ||
a16b043c | 5753 | static void kvm_init_msr_list(void) |
043405e1 | 5754 | { |
24c29b7a | 5755 | struct x86_pmu_capability x86_pmu; |
043405e1 | 5756 | u32 dummy[2]; |
7a5ee6ed | 5757 | unsigned i; |
043405e1 | 5758 | |
e2ada66e | 5759 | BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4, |
7a5ee6ed | 5760 | "Please update the fixed PMCs in msrs_to_saved_all[]"); |
24c29b7a PB |
5761 | |
5762 | perf_get_x86_pmu_capability(&x86_pmu); | |
e2ada66e | 5763 | |
6cbee2b9 XL |
5764 | num_msrs_to_save = 0; |
5765 | num_emulated_msrs = 0; | |
5766 | num_msr_based_features = 0; | |
5767 | ||
7a5ee6ed CQ |
5768 | for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) { |
5769 | if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0) | |
043405e1 | 5770 | continue; |
93c4adc7 PB |
5771 | |
5772 | /* | |
5773 | * Even MSRs that are valid in the host may not be exposed | |
9dbe6cf9 | 5774 | * to the guests in some cases. |
93c4adc7 | 5775 | */ |
7a5ee6ed | 5776 | switch (msrs_to_save_all[i]) { |
93c4adc7 | 5777 | case MSR_IA32_BNDCFGS: |
503234b3 | 5778 | if (!kvm_mpx_supported()) |
93c4adc7 PB |
5779 | continue; |
5780 | break; | |
9dbe6cf9 | 5781 | case MSR_TSC_AUX: |
13908510 | 5782 | if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) |
9dbe6cf9 PB |
5783 | continue; |
5784 | break; | |
f4cfcd2d ML |
5785 | case MSR_IA32_UMWAIT_CONTROL: |
5786 | if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG)) | |
5787 | continue; | |
5788 | break; | |
bf8c55d8 CP |
5789 | case MSR_IA32_RTIT_CTL: |
5790 | case MSR_IA32_RTIT_STATUS: | |
7b874c26 | 5791 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) |
bf8c55d8 CP |
5792 | continue; |
5793 | break; | |
5794 | case MSR_IA32_RTIT_CR3_MATCH: | |
7b874c26 | 5795 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
bf8c55d8 CP |
5796 | !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) |
5797 | continue; | |
5798 | break; | |
5799 | case MSR_IA32_RTIT_OUTPUT_BASE: | |
5800 | case MSR_IA32_RTIT_OUTPUT_MASK: | |
7b874c26 | 5801 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
bf8c55d8 CP |
5802 | (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && |
5803 | !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) | |
5804 | continue; | |
5805 | break; | |
7cb85fc4 | 5806 | case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: |
7b874c26 | 5807 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
7a5ee6ed | 5808 | msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >= |
bf8c55d8 CP |
5809 | intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) |
5810 | continue; | |
5811 | break; | |
cf05a67b | 5812 | case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17: |
7a5ee6ed | 5813 | if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >= |
24c29b7a PB |
5814 | min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) |
5815 | continue; | |
5816 | break; | |
cf05a67b | 5817 | case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17: |
7a5ee6ed | 5818 | if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= |
24c29b7a PB |
5819 | min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) |
5820 | continue; | |
7cb85fc4 | 5821 | break; |
93c4adc7 PB |
5822 | default: |
5823 | break; | |
5824 | } | |
5825 | ||
7a5ee6ed | 5826 | msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i]; |
043405e1 | 5827 | } |
62ef68bb | 5828 | |
7a5ee6ed | 5829 | for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) { |
5719455f | 5830 | if (!kvm_x86_ops.has_emulated_msr(NULL, emulated_msrs_all[i])) |
bc226f07 | 5831 | continue; |
62ef68bb | 5832 | |
7a5ee6ed | 5833 | emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i]; |
62ef68bb | 5834 | } |
801e459a | 5835 | |
7a5ee6ed | 5836 | for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) { |
801e459a TL |
5837 | struct kvm_msr_entry msr; |
5838 | ||
7a5ee6ed | 5839 | msr.index = msr_based_features_all[i]; |
66421c1e | 5840 | if (kvm_get_msr_feature(&msr)) |
801e459a TL |
5841 | continue; |
5842 | ||
7a5ee6ed | 5843 | msr_based_features[num_msr_based_features++] = msr_based_features_all[i]; |
801e459a | 5844 | } |
043405e1 CO |
5845 | } |
5846 | ||
bda9020e MT |
5847 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
5848 | const void *v) | |
bbd9b64e | 5849 | { |
70252a10 AK |
5850 | int handled = 0; |
5851 | int n; | |
5852 | ||
5853 | do { | |
5854 | n = min(len, 8); | |
bce87cce | 5855 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
5856 | !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) |
5857 | && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 AK |
5858 | break; |
5859 | handled += n; | |
5860 | addr += n; | |
5861 | len -= n; | |
5862 | v += n; | |
5863 | } while (len); | |
bbd9b64e | 5864 | |
70252a10 | 5865 | return handled; |
bbd9b64e CO |
5866 | } |
5867 | ||
bda9020e | 5868 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 5869 | { |
70252a10 AK |
5870 | int handled = 0; |
5871 | int n; | |
5872 | ||
5873 | do { | |
5874 | n = min(len, 8); | |
bce87cce | 5875 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
5876 | !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, |
5877 | addr, n, v)) | |
5878 | && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 | 5879 | break; |
e39d200f | 5880 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); |
70252a10 AK |
5881 | handled += n; |
5882 | addr += n; | |
5883 | len -= n; | |
5884 | v += n; | |
5885 | } while (len); | |
bbd9b64e | 5886 | |
70252a10 | 5887 | return handled; |
bbd9b64e CO |
5888 | } |
5889 | ||
2dafc6c2 GN |
5890 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
5891 | struct kvm_segment *var, int seg) | |
5892 | { | |
afaf0b2f | 5893 | kvm_x86_ops.set_segment(vcpu, var, seg); |
2dafc6c2 GN |
5894 | } |
5895 | ||
5896 | void kvm_get_segment(struct kvm_vcpu *vcpu, | |
5897 | struct kvm_segment *var, int seg) | |
5898 | { | |
afaf0b2f | 5899 | kvm_x86_ops.get_segment(vcpu, var, seg); |
2dafc6c2 GN |
5900 | } |
5901 | ||
54987b7a PB |
5902 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
5903 | struct x86_exception *exception) | |
02f59dc9 JR |
5904 | { |
5905 | gpa_t t_gpa; | |
02f59dc9 JR |
5906 | |
5907 | BUG_ON(!mmu_is_nested(vcpu)); | |
5908 | ||
5909 | /* NPT walks are always user-walks */ | |
5910 | access |= PFERR_USER_MASK; | |
44dd3ffa | 5911 | t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception); |
02f59dc9 JR |
5912 | |
5913 | return t_gpa; | |
5914 | } | |
5915 | ||
ab9ae313 AK |
5916 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
5917 | struct x86_exception *exception) | |
1871c602 | 5918 | { |
afaf0b2f | 5919 | u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
ab9ae313 | 5920 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
5921 | } |
5922 | ||
ab9ae313 AK |
5923 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, |
5924 | struct x86_exception *exception) | |
1871c602 | 5925 | { |
afaf0b2f | 5926 | u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
1871c602 | 5927 | access |= PFERR_FETCH_MASK; |
ab9ae313 | 5928 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
5929 | } |
5930 | ||
ab9ae313 AK |
5931 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, |
5932 | struct x86_exception *exception) | |
1871c602 | 5933 | { |
afaf0b2f | 5934 | u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
1871c602 | 5935 | access |= PFERR_WRITE_MASK; |
ab9ae313 | 5936 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
5937 | } |
5938 | ||
5939 | /* uses this to access any guest's mapped memory without checking CPL */ | |
ab9ae313 AK |
5940 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, |
5941 | struct x86_exception *exception) | |
1871c602 | 5942 | { |
ab9ae313 | 5943 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); |
1871c602 GN |
5944 | } |
5945 | ||
5946 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
5947 | struct kvm_vcpu *vcpu, u32 access, | |
bcc55cba | 5948 | struct x86_exception *exception) |
bbd9b64e CO |
5949 | { |
5950 | void *data = val; | |
10589a46 | 5951 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
5952 | |
5953 | while (bytes) { | |
14dfe855 | 5954 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, |
ab9ae313 | 5955 | exception); |
bbd9b64e | 5956 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 5957 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
5958 | int ret; |
5959 | ||
bcc55cba | 5960 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 5961 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa PB |
5962 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, |
5963 | offset, toread); | |
10589a46 | 5964 | if (ret < 0) { |
c3cd7ffa | 5965 | r = X86EMUL_IO_NEEDED; |
10589a46 MT |
5966 | goto out; |
5967 | } | |
bbd9b64e | 5968 | |
77c2002e IE |
5969 | bytes -= toread; |
5970 | data += toread; | |
5971 | addr += toread; | |
bbd9b64e | 5972 | } |
10589a46 | 5973 | out: |
10589a46 | 5974 | return r; |
bbd9b64e | 5975 | } |
77c2002e | 5976 | |
1871c602 | 5977 | /* used for instruction fetching */ |
0f65dd70 AK |
5978 | static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, |
5979 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 5980 | struct x86_exception *exception) |
1871c602 | 5981 | { |
0f65dd70 | 5982 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
afaf0b2f | 5983 | u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
44583cba PB |
5984 | unsigned offset; |
5985 | int ret; | |
0f65dd70 | 5986 | |
44583cba PB |
5987 | /* Inline kvm_read_guest_virt_helper for speed. */ |
5988 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, | |
5989 | exception); | |
5990 | if (unlikely(gpa == UNMAPPED_GVA)) | |
5991 | return X86EMUL_PROPAGATE_FAULT; | |
5992 | ||
5993 | offset = addr & (PAGE_SIZE-1); | |
5994 | if (WARN_ON(offset + bytes > PAGE_SIZE)) | |
5995 | bytes = (unsigned)PAGE_SIZE - offset; | |
54bf36aa PB |
5996 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, |
5997 | offset, bytes); | |
44583cba PB |
5998 | if (unlikely(ret < 0)) |
5999 | return X86EMUL_IO_NEEDED; | |
6000 | ||
6001 | return X86EMUL_CONTINUE; | |
1871c602 GN |
6002 | } |
6003 | ||
ce14e868 | 6004 | int kvm_read_guest_virt(struct kvm_vcpu *vcpu, |
0f65dd70 | 6005 | gva_t addr, void *val, unsigned int bytes, |
bcc55cba | 6006 | struct x86_exception *exception) |
1871c602 | 6007 | { |
afaf0b2f | 6008 | u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
0f65dd70 | 6009 | |
353c0956 PB |
6010 | /* |
6011 | * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED | |
6012 | * is returned, but our callers are not ready for that and they blindly | |
6013 | * call kvm_inject_page_fault. Ensure that they at least do not leak | |
6014 | * uninitialized kernel stack memory into cr2 and error code. | |
6015 | */ | |
6016 | memset(exception, 0, sizeof(*exception)); | |
1871c602 | 6017 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, |
bcc55cba | 6018 | exception); |
1871c602 | 6019 | } |
064aea77 | 6020 | EXPORT_SYMBOL_GPL(kvm_read_guest_virt); |
1871c602 | 6021 | |
ce14e868 PB |
6022 | static int emulator_read_std(struct x86_emulate_ctxt *ctxt, |
6023 | gva_t addr, void *val, unsigned int bytes, | |
3c9fa24c | 6024 | struct x86_exception *exception, bool system) |
1871c602 | 6025 | { |
0f65dd70 | 6026 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
3c9fa24c PB |
6027 | u32 access = 0; |
6028 | ||
afaf0b2f | 6029 | if (!system && kvm_x86_ops.get_cpl(vcpu) == 3) |
3c9fa24c PB |
6030 | access |= PFERR_USER_MASK; |
6031 | ||
6032 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); | |
1871c602 GN |
6033 | } |
6034 | ||
7a036a6f RK |
6035 | static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, |
6036 | unsigned long addr, void *val, unsigned int bytes) | |
6037 | { | |
6038 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
6039 | int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); | |
6040 | ||
6041 | return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; | |
6042 | } | |
6043 | ||
ce14e868 PB |
6044 | static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, |
6045 | struct kvm_vcpu *vcpu, u32 access, | |
6046 | struct x86_exception *exception) | |
77c2002e IE |
6047 | { |
6048 | void *data = val; | |
6049 | int r = X86EMUL_CONTINUE; | |
6050 | ||
6051 | while (bytes) { | |
14dfe855 | 6052 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, |
ce14e868 | 6053 | access, |
ab9ae313 | 6054 | exception); |
77c2002e IE |
6055 | unsigned offset = addr & (PAGE_SIZE-1); |
6056 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
6057 | int ret; | |
6058 | ||
bcc55cba | 6059 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 6060 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa | 6061 | ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); |
77c2002e | 6062 | if (ret < 0) { |
c3cd7ffa | 6063 | r = X86EMUL_IO_NEEDED; |
77c2002e IE |
6064 | goto out; |
6065 | } | |
6066 | ||
6067 | bytes -= towrite; | |
6068 | data += towrite; | |
6069 | addr += towrite; | |
6070 | } | |
6071 | out: | |
6072 | return r; | |
6073 | } | |
ce14e868 PB |
6074 | |
6075 | static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, | |
3c9fa24c PB |
6076 | unsigned int bytes, struct x86_exception *exception, |
6077 | bool system) | |
ce14e868 PB |
6078 | { |
6079 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
3c9fa24c PB |
6080 | u32 access = PFERR_WRITE_MASK; |
6081 | ||
afaf0b2f | 6082 | if (!system && kvm_x86_ops.get_cpl(vcpu) == 3) |
3c9fa24c | 6083 | access |= PFERR_USER_MASK; |
ce14e868 PB |
6084 | |
6085 | return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, | |
3c9fa24c | 6086 | access, exception); |
ce14e868 PB |
6087 | } |
6088 | ||
6089 | int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, | |
6090 | unsigned int bytes, struct x86_exception *exception) | |
6091 | { | |
c595ceee PB |
6092 | /* kvm_write_guest_virt_system can pull in tons of pages. */ |
6093 | vcpu->arch.l1tf_flush_l1d = true; | |
6094 | ||
ce14e868 PB |
6095 | return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, |
6096 | PFERR_WRITE_MASK, exception); | |
6097 | } | |
6a4d7550 | 6098 | EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); |
77c2002e | 6099 | |
082d06ed WL |
6100 | int handle_ud(struct kvm_vcpu *vcpu) |
6101 | { | |
b3dc0695 | 6102 | static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX }; |
6c86eedc | 6103 | int emul_type = EMULTYPE_TRAP_UD; |
6c86eedc WL |
6104 | char sig[5]; /* ud2; .ascii "kvm" */ |
6105 | struct x86_exception e; | |
6106 | ||
09e3e2a1 SC |
6107 | if (unlikely(!kvm_x86_ops.can_emulate_instruction(vcpu, NULL, 0))) |
6108 | return 1; | |
6109 | ||
6c86eedc | 6110 | if (force_emulation_prefix && |
3c9fa24c PB |
6111 | kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), |
6112 | sig, sizeof(sig), &e) == 0 && | |
b3dc0695 | 6113 | memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) { |
6c86eedc | 6114 | kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); |
b4000606 | 6115 | emul_type = EMULTYPE_TRAP_UD_FORCED; |
6c86eedc | 6116 | } |
082d06ed | 6117 | |
60fc3d02 | 6118 | return kvm_emulate_instruction(vcpu, emul_type); |
082d06ed WL |
6119 | } |
6120 | EXPORT_SYMBOL_GPL(handle_ud); | |
6121 | ||
0f89b207 TL |
6122 | static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
6123 | gpa_t gpa, bool write) | |
6124 | { | |
6125 | /* For APIC access vmexit */ | |
6126 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
6127 | return 1; | |
6128 | ||
6129 | if (vcpu_match_mmio_gpa(vcpu, gpa)) { | |
6130 | trace_vcpu_match_mmio(gva, gpa, write, true); | |
6131 | return 1; | |
6132 | } | |
6133 | ||
6134 | return 0; | |
6135 | } | |
6136 | ||
af7cc7d1 XG |
6137 | static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
6138 | gpa_t *gpa, struct x86_exception *exception, | |
6139 | bool write) | |
6140 | { | |
afaf0b2f | 6141 | u32 access = ((kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) |
97d64b78 | 6142 | | (write ? PFERR_WRITE_MASK : 0); |
af7cc7d1 | 6143 | |
be94f6b7 HH |
6144 | /* |
6145 | * currently PKRU is only applied to ept enabled guest so | |
6146 | * there is no pkey in EPT page table for L1 guest or EPT | |
6147 | * shadow page table for L2 guest. | |
6148 | */ | |
97d64b78 | 6149 | if (vcpu_match_mmio_gva(vcpu, gva) |
97ec8c06 | 6150 | && !permission_fault(vcpu, vcpu->arch.walk_mmu, |
871bd034 | 6151 | vcpu->arch.mmio_access, 0, access)) { |
bebb106a XG |
6152 | *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | |
6153 | (gva & (PAGE_SIZE - 1)); | |
4f022648 | 6154 | trace_vcpu_match_mmio(gva, *gpa, write, false); |
bebb106a XG |
6155 | return 1; |
6156 | } | |
6157 | ||
af7cc7d1 XG |
6158 | *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
6159 | ||
6160 | if (*gpa == UNMAPPED_GVA) | |
6161 | return -1; | |
6162 | ||
0f89b207 | 6163 | return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); |
af7cc7d1 XG |
6164 | } |
6165 | ||
3200f405 | 6166 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
bcc55cba | 6167 | const void *val, int bytes) |
bbd9b64e CO |
6168 | { |
6169 | int ret; | |
6170 | ||
54bf36aa | 6171 | ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); |
9f811285 | 6172 | if (ret < 0) |
bbd9b64e | 6173 | return 0; |
0eb05bf2 | 6174 | kvm_page_track_write(vcpu, gpa, val, bytes); |
bbd9b64e CO |
6175 | return 1; |
6176 | } | |
6177 | ||
77d197b2 XG |
6178 | struct read_write_emulator_ops { |
6179 | int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, | |
6180 | int bytes); | |
6181 | int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6182 | void *val, int bytes); | |
6183 | int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6184 | int bytes, void *val); | |
6185 | int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6186 | void *val, int bytes); | |
6187 | bool write; | |
6188 | }; | |
6189 | ||
6190 | static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) | |
6191 | { | |
6192 | if (vcpu->mmio_read_completed) { | |
77d197b2 | 6193 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
e39d200f | 6194 | vcpu->mmio_fragments[0].gpa, val); |
77d197b2 XG |
6195 | vcpu->mmio_read_completed = 0; |
6196 | return 1; | |
6197 | } | |
6198 | ||
6199 | return 0; | |
6200 | } | |
6201 | ||
6202 | static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6203 | void *val, int bytes) | |
6204 | { | |
54bf36aa | 6205 | return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); |
77d197b2 XG |
6206 | } |
6207 | ||
6208 | static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6209 | void *val, int bytes) | |
6210 | { | |
6211 | return emulator_write_phys(vcpu, gpa, val, bytes); | |
6212 | } | |
6213 | ||
6214 | static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) | |
6215 | { | |
e39d200f | 6216 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); |
77d197b2 XG |
6217 | return vcpu_mmio_write(vcpu, gpa, bytes, val); |
6218 | } | |
6219 | ||
6220 | static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6221 | void *val, int bytes) | |
6222 | { | |
e39d200f | 6223 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); |
77d197b2 XG |
6224 | return X86EMUL_IO_NEEDED; |
6225 | } | |
6226 | ||
6227 | static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6228 | void *val, int bytes) | |
6229 | { | |
f78146b0 AK |
6230 | struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; |
6231 | ||
87da7e66 | 6232 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); |
77d197b2 XG |
6233 | return X86EMUL_CONTINUE; |
6234 | } | |
6235 | ||
0fbe9b0b | 6236 | static const struct read_write_emulator_ops read_emultor = { |
77d197b2 XG |
6237 | .read_write_prepare = read_prepare, |
6238 | .read_write_emulate = read_emulate, | |
6239 | .read_write_mmio = vcpu_mmio_read, | |
6240 | .read_write_exit_mmio = read_exit_mmio, | |
6241 | }; | |
6242 | ||
0fbe9b0b | 6243 | static const struct read_write_emulator_ops write_emultor = { |
77d197b2 XG |
6244 | .read_write_emulate = write_emulate, |
6245 | .read_write_mmio = write_mmio, | |
6246 | .read_write_exit_mmio = write_exit_mmio, | |
6247 | .write = true, | |
6248 | }; | |
6249 | ||
22388a3c XG |
6250 | static int emulator_read_write_onepage(unsigned long addr, void *val, |
6251 | unsigned int bytes, | |
6252 | struct x86_exception *exception, | |
6253 | struct kvm_vcpu *vcpu, | |
0fbe9b0b | 6254 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 6255 | { |
af7cc7d1 XG |
6256 | gpa_t gpa; |
6257 | int handled, ret; | |
22388a3c | 6258 | bool write = ops->write; |
f78146b0 | 6259 | struct kvm_mmio_fragment *frag; |
c9b8b07c | 6260 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
0f89b207 TL |
6261 | |
6262 | /* | |
6263 | * If the exit was due to a NPF we may already have a GPA. | |
6264 | * If the GPA is present, use it to avoid the GVA to GPA table walk. | |
6265 | * Note, this cannot be used on string operations since string | |
6266 | * operation using rep will only have the initial GPA from the NPF | |
6267 | * occurred. | |
6268 | */ | |
744e699c SC |
6269 | if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) && |
6270 | (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) { | |
6271 | gpa = ctxt->gpa_val; | |
618232e2 BS |
6272 | ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); |
6273 | } else { | |
6274 | ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); | |
6275 | if (ret < 0) | |
6276 | return X86EMUL_PROPAGATE_FAULT; | |
0f89b207 | 6277 | } |
10589a46 | 6278 | |
618232e2 | 6279 | if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) |
bbd9b64e CO |
6280 | return X86EMUL_CONTINUE; |
6281 | ||
bbd9b64e CO |
6282 | /* |
6283 | * Is this MMIO handled locally? | |
6284 | */ | |
22388a3c | 6285 | handled = ops->read_write_mmio(vcpu, gpa, bytes, val); |
70252a10 | 6286 | if (handled == bytes) |
bbd9b64e | 6287 | return X86EMUL_CONTINUE; |
bbd9b64e | 6288 | |
70252a10 AK |
6289 | gpa += handled; |
6290 | bytes -= handled; | |
6291 | val += handled; | |
6292 | ||
87da7e66 XG |
6293 | WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); |
6294 | frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; | |
6295 | frag->gpa = gpa; | |
6296 | frag->data = val; | |
6297 | frag->len = bytes; | |
f78146b0 | 6298 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
6299 | } |
6300 | ||
52eb5a6d XL |
6301 | static int emulator_read_write(struct x86_emulate_ctxt *ctxt, |
6302 | unsigned long addr, | |
22388a3c XG |
6303 | void *val, unsigned int bytes, |
6304 | struct x86_exception *exception, | |
0fbe9b0b | 6305 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 6306 | { |
0f65dd70 | 6307 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
f78146b0 AK |
6308 | gpa_t gpa; |
6309 | int rc; | |
6310 | ||
6311 | if (ops->read_write_prepare && | |
6312 | ops->read_write_prepare(vcpu, val, bytes)) | |
6313 | return X86EMUL_CONTINUE; | |
6314 | ||
6315 | vcpu->mmio_nr_fragments = 0; | |
0f65dd70 | 6316 | |
bbd9b64e CO |
6317 | /* Crossing a page boundary? */ |
6318 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
f78146b0 | 6319 | int now; |
bbd9b64e CO |
6320 | |
6321 | now = -addr & ~PAGE_MASK; | |
22388a3c XG |
6322 | rc = emulator_read_write_onepage(addr, val, now, exception, |
6323 | vcpu, ops); | |
6324 | ||
bbd9b64e CO |
6325 | if (rc != X86EMUL_CONTINUE) |
6326 | return rc; | |
6327 | addr += now; | |
bac15531 NA |
6328 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
6329 | addr = (u32)addr; | |
bbd9b64e CO |
6330 | val += now; |
6331 | bytes -= now; | |
6332 | } | |
22388a3c | 6333 | |
f78146b0 AK |
6334 | rc = emulator_read_write_onepage(addr, val, bytes, exception, |
6335 | vcpu, ops); | |
6336 | if (rc != X86EMUL_CONTINUE) | |
6337 | return rc; | |
6338 | ||
6339 | if (!vcpu->mmio_nr_fragments) | |
6340 | return rc; | |
6341 | ||
6342 | gpa = vcpu->mmio_fragments[0].gpa; | |
6343 | ||
6344 | vcpu->mmio_needed = 1; | |
6345 | vcpu->mmio_cur_fragment = 0; | |
6346 | ||
87da7e66 | 6347 | vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); |
f78146b0 AK |
6348 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; |
6349 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
6350 | vcpu->run->mmio.phys_addr = gpa; | |
6351 | ||
6352 | return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); | |
22388a3c XG |
6353 | } |
6354 | ||
6355 | static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, | |
6356 | unsigned long addr, | |
6357 | void *val, | |
6358 | unsigned int bytes, | |
6359 | struct x86_exception *exception) | |
6360 | { | |
6361 | return emulator_read_write(ctxt, addr, val, bytes, | |
6362 | exception, &read_emultor); | |
6363 | } | |
6364 | ||
52eb5a6d | 6365 | static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, |
22388a3c XG |
6366 | unsigned long addr, |
6367 | const void *val, | |
6368 | unsigned int bytes, | |
6369 | struct x86_exception *exception) | |
6370 | { | |
6371 | return emulator_read_write(ctxt, addr, (void *)val, bytes, | |
6372 | exception, &write_emultor); | |
bbd9b64e | 6373 | } |
bbd9b64e | 6374 | |
daea3e73 AK |
6375 | #define CMPXCHG_TYPE(t, ptr, old, new) \ |
6376 | (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) | |
6377 | ||
6378 | #ifdef CONFIG_X86_64 | |
6379 | # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) | |
6380 | #else | |
6381 | # define CMPXCHG64(ptr, old, new) \ | |
9749a6c0 | 6382 | (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) |
daea3e73 AK |
6383 | #endif |
6384 | ||
0f65dd70 AK |
6385 | static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, |
6386 | unsigned long addr, | |
bbd9b64e CO |
6387 | const void *old, |
6388 | const void *new, | |
6389 | unsigned int bytes, | |
0f65dd70 | 6390 | struct x86_exception *exception) |
bbd9b64e | 6391 | { |
42e35f80 | 6392 | struct kvm_host_map map; |
0f65dd70 | 6393 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
9de6fe3c | 6394 | u64 page_line_mask; |
daea3e73 | 6395 | gpa_t gpa; |
daea3e73 AK |
6396 | char *kaddr; |
6397 | bool exchanged; | |
2bacc55c | 6398 | |
daea3e73 AK |
6399 | /* guests cmpxchg8b have to be emulated atomically */ |
6400 | if (bytes > 8 || (bytes & (bytes - 1))) | |
6401 | goto emul_write; | |
10589a46 | 6402 | |
daea3e73 | 6403 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); |
2bacc55c | 6404 | |
daea3e73 AK |
6405 | if (gpa == UNMAPPED_GVA || |
6406 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
6407 | goto emul_write; | |
2bacc55c | 6408 | |
9de6fe3c XL |
6409 | /* |
6410 | * Emulate the atomic as a straight write to avoid #AC if SLD is | |
6411 | * enabled in the host and the access splits a cache line. | |
6412 | */ | |
6413 | if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) | |
6414 | page_line_mask = ~(cache_line_size() - 1); | |
6415 | else | |
6416 | page_line_mask = PAGE_MASK; | |
6417 | ||
6418 | if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask)) | |
daea3e73 | 6419 | goto emul_write; |
72dc67a6 | 6420 | |
42e35f80 | 6421 | if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map)) |
c19b8bd6 | 6422 | goto emul_write; |
72dc67a6 | 6423 | |
42e35f80 KA |
6424 | kaddr = map.hva + offset_in_page(gpa); |
6425 | ||
daea3e73 AK |
6426 | switch (bytes) { |
6427 | case 1: | |
6428 | exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); | |
6429 | break; | |
6430 | case 2: | |
6431 | exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); | |
6432 | break; | |
6433 | case 4: | |
6434 | exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); | |
6435 | break; | |
6436 | case 8: | |
6437 | exchanged = CMPXCHG64(kaddr, old, new); | |
6438 | break; | |
6439 | default: | |
6440 | BUG(); | |
2bacc55c | 6441 | } |
42e35f80 KA |
6442 | |
6443 | kvm_vcpu_unmap(vcpu, &map, true); | |
daea3e73 AK |
6444 | |
6445 | if (!exchanged) | |
6446 | return X86EMUL_CMPXCHG_FAILED; | |
6447 | ||
0eb05bf2 | 6448 | kvm_page_track_write(vcpu, gpa, new, bytes); |
8f6abd06 GN |
6449 | |
6450 | return X86EMUL_CONTINUE; | |
4a5f48f6 | 6451 | |
3200f405 | 6452 | emul_write: |
daea3e73 | 6453 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); |
2bacc55c | 6454 | |
0f65dd70 | 6455 | return emulator_write_emulated(ctxt, addr, new, bytes, exception); |
bbd9b64e CO |
6456 | } |
6457 | ||
cf8f70bf GN |
6458 | static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) |
6459 | { | |
cbfc6c91 | 6460 | int r = 0, i; |
cf8f70bf | 6461 | |
cbfc6c91 WL |
6462 | for (i = 0; i < vcpu->arch.pio.count; i++) { |
6463 | if (vcpu->arch.pio.in) | |
6464 | r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, | |
6465 | vcpu->arch.pio.size, pd); | |
6466 | else | |
6467 | r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, | |
6468 | vcpu->arch.pio.port, vcpu->arch.pio.size, | |
6469 | pd); | |
6470 | if (r) | |
6471 | break; | |
6472 | pd += vcpu->arch.pio.size; | |
6473 | } | |
cf8f70bf GN |
6474 | return r; |
6475 | } | |
6476 | ||
6f6fbe98 XG |
6477 | static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, |
6478 | unsigned short port, void *val, | |
6479 | unsigned int count, bool in) | |
cf8f70bf | 6480 | { |
cf8f70bf | 6481 | vcpu->arch.pio.port = port; |
6f6fbe98 | 6482 | vcpu->arch.pio.in = in; |
7972995b | 6483 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
6484 | vcpu->arch.pio.size = size; |
6485 | ||
6486 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
7972995b | 6487 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
6488 | return 1; |
6489 | } | |
6490 | ||
6491 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
6f6fbe98 | 6492 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; |
cf8f70bf GN |
6493 | vcpu->run->io.size = size; |
6494 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
6495 | vcpu->run->io.count = count; | |
6496 | vcpu->run->io.port = port; | |
6497 | ||
6498 | return 0; | |
6499 | } | |
6500 | ||
2e3bb4d8 SC |
6501 | static int emulator_pio_in(struct kvm_vcpu *vcpu, int size, |
6502 | unsigned short port, void *val, unsigned int count) | |
cf8f70bf | 6503 | { |
6f6fbe98 | 6504 | int ret; |
ca1d4a9e | 6505 | |
6f6fbe98 XG |
6506 | if (vcpu->arch.pio.count) |
6507 | goto data_avail; | |
cf8f70bf | 6508 | |
cbfc6c91 WL |
6509 | memset(vcpu->arch.pio_data, 0, size * count); |
6510 | ||
6f6fbe98 XG |
6511 | ret = emulator_pio_in_out(vcpu, size, port, val, count, true); |
6512 | if (ret) { | |
6513 | data_avail: | |
6514 | memcpy(val, vcpu->arch.pio_data, size * count); | |
1171903d | 6515 | trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); |
7972995b | 6516 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
6517 | return 1; |
6518 | } | |
6519 | ||
cf8f70bf GN |
6520 | return 0; |
6521 | } | |
6522 | ||
2e3bb4d8 SC |
6523 | static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
6524 | int size, unsigned short port, void *val, | |
6525 | unsigned int count) | |
6f6fbe98 | 6526 | { |
2e3bb4d8 | 6527 | return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count); |
6f6fbe98 | 6528 | |
2e3bb4d8 | 6529 | } |
6f6fbe98 | 6530 | |
2e3bb4d8 SC |
6531 | static int emulator_pio_out(struct kvm_vcpu *vcpu, int size, |
6532 | unsigned short port, const void *val, | |
6533 | unsigned int count) | |
6534 | { | |
6f6fbe98 | 6535 | memcpy(vcpu->arch.pio_data, val, size * count); |
1171903d | 6536 | trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); |
6f6fbe98 XG |
6537 | return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); |
6538 | } | |
6539 | ||
2e3bb4d8 SC |
6540 | static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, |
6541 | int size, unsigned short port, | |
6542 | const void *val, unsigned int count) | |
6543 | { | |
6544 | return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count); | |
6545 | } | |
6546 | ||
bbd9b64e CO |
6547 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) |
6548 | { | |
afaf0b2f | 6549 | return kvm_x86_ops.get_segment_base(vcpu, seg); |
bbd9b64e CO |
6550 | } |
6551 | ||
3cb16fe7 | 6552 | static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) |
bbd9b64e | 6553 | { |
3cb16fe7 | 6554 | kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); |
bbd9b64e CO |
6555 | } |
6556 | ||
ae6a2375 | 6557 | static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) |
f5f48ee1 SY |
6558 | { |
6559 | if (!need_emulate_wbinvd(vcpu)) | |
6560 | return X86EMUL_CONTINUE; | |
6561 | ||
afaf0b2f | 6562 | if (kvm_x86_ops.has_wbinvd_exit()) { |
2eec7343 JK |
6563 | int cpu = get_cpu(); |
6564 | ||
6565 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
f5f48ee1 SY |
6566 | smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, |
6567 | wbinvd_ipi, NULL, 1); | |
2eec7343 | 6568 | put_cpu(); |
f5f48ee1 | 6569 | cpumask_clear(vcpu->arch.wbinvd_dirty_mask); |
2eec7343 JK |
6570 | } else |
6571 | wbinvd(); | |
f5f48ee1 SY |
6572 | return X86EMUL_CONTINUE; |
6573 | } | |
5cb56059 JS |
6574 | |
6575 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
6576 | { | |
6affcbed KH |
6577 | kvm_emulate_wbinvd_noskip(vcpu); |
6578 | return kvm_skip_emulated_instruction(vcpu); | |
5cb56059 | 6579 | } |
f5f48ee1 SY |
6580 | EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); |
6581 | ||
5cb56059 JS |
6582 | |
6583 | ||
bcaf5cc5 AK |
6584 | static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) |
6585 | { | |
5cb56059 | 6586 | kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); |
bcaf5cc5 AK |
6587 | } |
6588 | ||
52eb5a6d XL |
6589 | static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, |
6590 | unsigned long *dest) | |
bbd9b64e | 6591 | { |
16f8a6f9 | 6592 | return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); |
bbd9b64e CO |
6593 | } |
6594 | ||
52eb5a6d XL |
6595 | static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, |
6596 | unsigned long value) | |
bbd9b64e | 6597 | { |
338dbc97 | 6598 | |
717746e3 | 6599 | return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); |
bbd9b64e CO |
6600 | } |
6601 | ||
52a46617 | 6602 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) |
5fdbf976 | 6603 | { |
52a46617 | 6604 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; |
5fdbf976 MT |
6605 | } |
6606 | ||
717746e3 | 6607 | static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) |
bbd9b64e | 6608 | { |
717746e3 | 6609 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
52a46617 GN |
6610 | unsigned long value; |
6611 | ||
6612 | switch (cr) { | |
6613 | case 0: | |
6614 | value = kvm_read_cr0(vcpu); | |
6615 | break; | |
6616 | case 2: | |
6617 | value = vcpu->arch.cr2; | |
6618 | break; | |
6619 | case 3: | |
9f8fe504 | 6620 | value = kvm_read_cr3(vcpu); |
52a46617 GN |
6621 | break; |
6622 | case 4: | |
6623 | value = kvm_read_cr4(vcpu); | |
6624 | break; | |
6625 | case 8: | |
6626 | value = kvm_get_cr8(vcpu); | |
6627 | break; | |
6628 | default: | |
a737f256 | 6629 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
52a46617 GN |
6630 | return 0; |
6631 | } | |
6632 | ||
6633 | return value; | |
6634 | } | |
6635 | ||
717746e3 | 6636 | static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) |
52a46617 | 6637 | { |
717746e3 | 6638 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
0f12244f GN |
6639 | int res = 0; |
6640 | ||
52a46617 GN |
6641 | switch (cr) { |
6642 | case 0: | |
49a9b07e | 6643 | res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
52a46617 GN |
6644 | break; |
6645 | case 2: | |
6646 | vcpu->arch.cr2 = val; | |
6647 | break; | |
6648 | case 3: | |
2390218b | 6649 | res = kvm_set_cr3(vcpu, val); |
52a46617 GN |
6650 | break; |
6651 | case 4: | |
a83b29c6 | 6652 | res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
52a46617 GN |
6653 | break; |
6654 | case 8: | |
eea1cff9 | 6655 | res = kvm_set_cr8(vcpu, val); |
52a46617 GN |
6656 | break; |
6657 | default: | |
a737f256 | 6658 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
0f12244f | 6659 | res = -1; |
52a46617 | 6660 | } |
0f12244f GN |
6661 | |
6662 | return res; | |
52a46617 GN |
6663 | } |
6664 | ||
717746e3 | 6665 | static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) |
9c537244 | 6666 | { |
afaf0b2f | 6667 | return kvm_x86_ops.get_cpl(emul_to_vcpu(ctxt)); |
9c537244 GN |
6668 | } |
6669 | ||
4bff1e86 | 6670 | static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
2dafc6c2 | 6671 | { |
afaf0b2f | 6672 | kvm_x86_ops.get_gdt(emul_to_vcpu(ctxt), dt); |
2dafc6c2 GN |
6673 | } |
6674 | ||
4bff1e86 | 6675 | static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
160ce1f1 | 6676 | { |
afaf0b2f | 6677 | kvm_x86_ops.get_idt(emul_to_vcpu(ctxt), dt); |
160ce1f1 MG |
6678 | } |
6679 | ||
1ac9d0cf AK |
6680 | static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
6681 | { | |
afaf0b2f | 6682 | kvm_x86_ops.set_gdt(emul_to_vcpu(ctxt), dt); |
1ac9d0cf AK |
6683 | } |
6684 | ||
6685 | static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) | |
6686 | { | |
afaf0b2f | 6687 | kvm_x86_ops.set_idt(emul_to_vcpu(ctxt), dt); |
1ac9d0cf AK |
6688 | } |
6689 | ||
4bff1e86 AK |
6690 | static unsigned long emulator_get_cached_segment_base( |
6691 | struct x86_emulate_ctxt *ctxt, int seg) | |
5951c442 | 6692 | { |
4bff1e86 | 6693 | return get_segment_base(emul_to_vcpu(ctxt), seg); |
5951c442 GN |
6694 | } |
6695 | ||
1aa36616 AK |
6696 | static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, |
6697 | struct desc_struct *desc, u32 *base3, | |
6698 | int seg) | |
2dafc6c2 GN |
6699 | { |
6700 | struct kvm_segment var; | |
6701 | ||
4bff1e86 | 6702 | kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); |
1aa36616 | 6703 | *selector = var.selector; |
2dafc6c2 | 6704 | |
378a8b09 GN |
6705 | if (var.unusable) { |
6706 | memset(desc, 0, sizeof(*desc)); | |
f0367ee1 RK |
6707 | if (base3) |
6708 | *base3 = 0; | |
2dafc6c2 | 6709 | return false; |
378a8b09 | 6710 | } |
2dafc6c2 GN |
6711 | |
6712 | if (var.g) | |
6713 | var.limit >>= 12; | |
6714 | set_desc_limit(desc, var.limit); | |
6715 | set_desc_base(desc, (unsigned long)var.base); | |
5601d05b GN |
6716 | #ifdef CONFIG_X86_64 |
6717 | if (base3) | |
6718 | *base3 = var.base >> 32; | |
6719 | #endif | |
2dafc6c2 GN |
6720 | desc->type = var.type; |
6721 | desc->s = var.s; | |
6722 | desc->dpl = var.dpl; | |
6723 | desc->p = var.present; | |
6724 | desc->avl = var.avl; | |
6725 | desc->l = var.l; | |
6726 | desc->d = var.db; | |
6727 | desc->g = var.g; | |
6728 | ||
6729 | return true; | |
6730 | } | |
6731 | ||
1aa36616 AK |
6732 | static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, |
6733 | struct desc_struct *desc, u32 base3, | |
6734 | int seg) | |
2dafc6c2 | 6735 | { |
4bff1e86 | 6736 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
2dafc6c2 GN |
6737 | struct kvm_segment var; |
6738 | ||
1aa36616 | 6739 | var.selector = selector; |
2dafc6c2 | 6740 | var.base = get_desc_base(desc); |
5601d05b GN |
6741 | #ifdef CONFIG_X86_64 |
6742 | var.base |= ((u64)base3) << 32; | |
6743 | #endif | |
2dafc6c2 GN |
6744 | var.limit = get_desc_limit(desc); |
6745 | if (desc->g) | |
6746 | var.limit = (var.limit << 12) | 0xfff; | |
6747 | var.type = desc->type; | |
2dafc6c2 GN |
6748 | var.dpl = desc->dpl; |
6749 | var.db = desc->d; | |
6750 | var.s = desc->s; | |
6751 | var.l = desc->l; | |
6752 | var.g = desc->g; | |
6753 | var.avl = desc->avl; | |
6754 | var.present = desc->p; | |
6755 | var.unusable = !var.present; | |
6756 | var.padding = 0; | |
6757 | ||
6758 | kvm_set_segment(vcpu, &var, seg); | |
6759 | return; | |
6760 | } | |
6761 | ||
717746e3 AK |
6762 | static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, |
6763 | u32 msr_index, u64 *pdata) | |
6764 | { | |
1ae09954 AG |
6765 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
6766 | int r; | |
6767 | ||
6768 | r = kvm_get_msr(vcpu, msr_index, pdata); | |
6769 | ||
6770 | if (r && kvm_get_msr_user_space(vcpu, msr_index, r)) { | |
6771 | /* Bounce to user space */ | |
6772 | return X86EMUL_IO_NEEDED; | |
6773 | } | |
6774 | ||
6775 | return r; | |
717746e3 AK |
6776 | } |
6777 | ||
6778 | static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, | |
6779 | u32 msr_index, u64 data) | |
6780 | { | |
1ae09954 AG |
6781 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
6782 | int r; | |
6783 | ||
6784 | r = kvm_set_msr(vcpu, msr_index, data); | |
6785 | ||
6786 | if (r && kvm_set_msr_user_space(vcpu, msr_index, data, r)) { | |
6787 | /* Bounce to user space */ | |
6788 | return X86EMUL_IO_NEEDED; | |
6789 | } | |
6790 | ||
6791 | return r; | |
717746e3 AK |
6792 | } |
6793 | ||
64d60670 PB |
6794 | static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) |
6795 | { | |
6796 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
6797 | ||
6798 | return vcpu->arch.smbase; | |
6799 | } | |
6800 | ||
6801 | static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) | |
6802 | { | |
6803 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
6804 | ||
6805 | vcpu->arch.smbase = smbase; | |
6806 | } | |
6807 | ||
67f4d428 NA |
6808 | static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, |
6809 | u32 pmc) | |
6810 | { | |
98ff80f5 | 6811 | return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc); |
67f4d428 NA |
6812 | } |
6813 | ||
222d21aa AK |
6814 | static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, |
6815 | u32 pmc, u64 *pdata) | |
6816 | { | |
c6702c9d | 6817 | return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); |
222d21aa AK |
6818 | } |
6819 | ||
6c3287f7 AK |
6820 | static void emulator_halt(struct x86_emulate_ctxt *ctxt) |
6821 | { | |
6822 | emul_to_vcpu(ctxt)->arch.halt_request = 1; | |
6823 | } | |
6824 | ||
2953538e | 6825 | static int emulator_intercept(struct x86_emulate_ctxt *ctxt, |
8a76d7f2 | 6826 | struct x86_instruction_info *info, |
c4f035c6 AK |
6827 | enum x86_intercept_stage stage) |
6828 | { | |
afaf0b2f | 6829 | return kvm_x86_ops.check_intercept(emul_to_vcpu(ctxt), info, stage, |
21f1b8f2 | 6830 | &ctxt->exception); |
c4f035c6 AK |
6831 | } |
6832 | ||
e911eb3b | 6833 | static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, |
f91af517 SC |
6834 | u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, |
6835 | bool exact_only) | |
bdb42f5a | 6836 | { |
f91af517 | 6837 | return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only); |
bdb42f5a SB |
6838 | } |
6839 | ||
5ae78e95 SC |
6840 | static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt) |
6841 | { | |
6842 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM); | |
6843 | } | |
6844 | ||
6845 | static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt) | |
6846 | { | |
6847 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE); | |
6848 | } | |
6849 | ||
6850 | static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt) | |
6851 | { | |
6852 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR); | |
6853 | } | |
6854 | ||
dd856efa AK |
6855 | static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) |
6856 | { | |
6857 | return kvm_register_read(emul_to_vcpu(ctxt), reg); | |
6858 | } | |
6859 | ||
6860 | static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) | |
6861 | { | |
6862 | kvm_register_write(emul_to_vcpu(ctxt), reg, val); | |
6863 | } | |
6864 | ||
801806d9 NA |
6865 | static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) |
6866 | { | |
afaf0b2f | 6867 | kvm_x86_ops.set_nmi_mask(emul_to_vcpu(ctxt), masked); |
801806d9 NA |
6868 | } |
6869 | ||
6ed071f0 LP |
6870 | static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) |
6871 | { | |
6872 | return emul_to_vcpu(ctxt)->arch.hflags; | |
6873 | } | |
6874 | ||
6875 | static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags) | |
6876 | { | |
c5833c7a | 6877 | emul_to_vcpu(ctxt)->arch.hflags = emul_flags; |
6ed071f0 LP |
6878 | } |
6879 | ||
ed19321f SC |
6880 | static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, |
6881 | const char *smstate) | |
0234bf88 | 6882 | { |
afaf0b2f | 6883 | return kvm_x86_ops.pre_leave_smm(emul_to_vcpu(ctxt), smstate); |
0234bf88 LP |
6884 | } |
6885 | ||
c5833c7a SC |
6886 | static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt) |
6887 | { | |
6888 | kvm_smm_changed(emul_to_vcpu(ctxt)); | |
6889 | } | |
6890 | ||
02d4160f VK |
6891 | static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) |
6892 | { | |
6893 | return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); | |
6894 | } | |
6895 | ||
0225fb50 | 6896 | static const struct x86_emulate_ops emulate_ops = { |
dd856efa AK |
6897 | .read_gpr = emulator_read_gpr, |
6898 | .write_gpr = emulator_write_gpr, | |
ce14e868 PB |
6899 | .read_std = emulator_read_std, |
6900 | .write_std = emulator_write_std, | |
7a036a6f | 6901 | .read_phys = kvm_read_guest_phys_system, |
1871c602 | 6902 | .fetch = kvm_fetch_guest_virt, |
bbd9b64e CO |
6903 | .read_emulated = emulator_read_emulated, |
6904 | .write_emulated = emulator_write_emulated, | |
6905 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
3cb16fe7 | 6906 | .invlpg = emulator_invlpg, |
cf8f70bf GN |
6907 | .pio_in_emulated = emulator_pio_in_emulated, |
6908 | .pio_out_emulated = emulator_pio_out_emulated, | |
1aa36616 AK |
6909 | .get_segment = emulator_get_segment, |
6910 | .set_segment = emulator_set_segment, | |
5951c442 | 6911 | .get_cached_segment_base = emulator_get_cached_segment_base, |
2dafc6c2 | 6912 | .get_gdt = emulator_get_gdt, |
160ce1f1 | 6913 | .get_idt = emulator_get_idt, |
1ac9d0cf AK |
6914 | .set_gdt = emulator_set_gdt, |
6915 | .set_idt = emulator_set_idt, | |
52a46617 GN |
6916 | .get_cr = emulator_get_cr, |
6917 | .set_cr = emulator_set_cr, | |
9c537244 | 6918 | .cpl = emulator_get_cpl, |
35aa5375 GN |
6919 | .get_dr = emulator_get_dr, |
6920 | .set_dr = emulator_set_dr, | |
64d60670 PB |
6921 | .get_smbase = emulator_get_smbase, |
6922 | .set_smbase = emulator_set_smbase, | |
717746e3 AK |
6923 | .set_msr = emulator_set_msr, |
6924 | .get_msr = emulator_get_msr, | |
67f4d428 | 6925 | .check_pmc = emulator_check_pmc, |
222d21aa | 6926 | .read_pmc = emulator_read_pmc, |
6c3287f7 | 6927 | .halt = emulator_halt, |
bcaf5cc5 | 6928 | .wbinvd = emulator_wbinvd, |
d6aa1000 | 6929 | .fix_hypercall = emulator_fix_hypercall, |
c4f035c6 | 6930 | .intercept = emulator_intercept, |
bdb42f5a | 6931 | .get_cpuid = emulator_get_cpuid, |
5ae78e95 SC |
6932 | .guest_has_long_mode = emulator_guest_has_long_mode, |
6933 | .guest_has_movbe = emulator_guest_has_movbe, | |
6934 | .guest_has_fxsr = emulator_guest_has_fxsr, | |
801806d9 | 6935 | .set_nmi_mask = emulator_set_nmi_mask, |
6ed071f0 LP |
6936 | .get_hflags = emulator_get_hflags, |
6937 | .set_hflags = emulator_set_hflags, | |
0234bf88 | 6938 | .pre_leave_smm = emulator_pre_leave_smm, |
c5833c7a | 6939 | .post_leave_smm = emulator_post_leave_smm, |
02d4160f | 6940 | .set_xcr = emulator_set_xcr, |
bbd9b64e CO |
6941 | }; |
6942 | ||
95cb2295 GN |
6943 | static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) |
6944 | { | |
afaf0b2f | 6945 | u32 int_shadow = kvm_x86_ops.get_interrupt_shadow(vcpu); |
95cb2295 GN |
6946 | /* |
6947 | * an sti; sti; sequence only disable interrupts for the first | |
6948 | * instruction. So, if the last instruction, be it emulated or | |
6949 | * not, left the system with the INT_STI flag enabled, it | |
6950 | * means that the last instruction is an sti. We should not | |
6951 | * leave the flag on in this case. The same goes for mov ss | |
6952 | */ | |
37ccdcbe PB |
6953 | if (int_shadow & mask) |
6954 | mask = 0; | |
6addfc42 | 6955 | if (unlikely(int_shadow || mask)) { |
afaf0b2f | 6956 | kvm_x86_ops.set_interrupt_shadow(vcpu, mask); |
6addfc42 PB |
6957 | if (!mask) |
6958 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
6959 | } | |
95cb2295 GN |
6960 | } |
6961 | ||
ef54bcfe | 6962 | static bool inject_emulated_exception(struct kvm_vcpu *vcpu) |
54b8486f | 6963 | { |
c9b8b07c | 6964 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
da9cb575 | 6965 | if (ctxt->exception.vector == PF_VECTOR) |
53b3d8e9 | 6966 | return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception); |
ef54bcfe PB |
6967 | |
6968 | if (ctxt->exception.error_code_valid) | |
da9cb575 AK |
6969 | kvm_queue_exception_e(vcpu, ctxt->exception.vector, |
6970 | ctxt->exception.error_code); | |
54b8486f | 6971 | else |
da9cb575 | 6972 | kvm_queue_exception(vcpu, ctxt->exception.vector); |
ef54bcfe | 6973 | return false; |
54b8486f GN |
6974 | } |
6975 | ||
c9b8b07c SC |
6976 | static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu) |
6977 | { | |
6978 | struct x86_emulate_ctxt *ctxt; | |
6979 | ||
6980 | ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT); | |
6981 | if (!ctxt) { | |
6982 | pr_err("kvm: failed to allocate vcpu's emulator\n"); | |
6983 | return NULL; | |
6984 | } | |
6985 | ||
6986 | ctxt->vcpu = vcpu; | |
6987 | ctxt->ops = &emulate_ops; | |
6988 | vcpu->arch.emulate_ctxt = ctxt; | |
6989 | ||
6990 | return ctxt; | |
6991 | } | |
6992 | ||
8ec4722d MG |
6993 | static void init_emulate_ctxt(struct kvm_vcpu *vcpu) |
6994 | { | |
c9b8b07c | 6995 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
8ec4722d MG |
6996 | int cs_db, cs_l; |
6997 | ||
afaf0b2f | 6998 | kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
8ec4722d | 6999 | |
744e699c | 7000 | ctxt->gpa_available = false; |
adf52235 | 7001 | ctxt->eflags = kvm_get_rflags(vcpu); |
c8401dda PB |
7002 | ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; |
7003 | ||
adf52235 TY |
7004 | ctxt->eip = kvm_rip_read(vcpu); |
7005 | ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : | |
7006 | (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : | |
42bf549f | 7007 | (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : |
adf52235 TY |
7008 | cs_db ? X86EMUL_MODE_PROT32 : |
7009 | X86EMUL_MODE_PROT16; | |
a584539b | 7010 | BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); |
64d60670 PB |
7011 | BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); |
7012 | BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); | |
adf52235 | 7013 | |
dd856efa | 7014 | init_decode_cache(ctxt); |
7ae441ea | 7015 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; |
8ec4722d MG |
7016 | } |
7017 | ||
9497e1f2 | 7018 | void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) |
63995653 | 7019 | { |
c9b8b07c | 7020 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
63995653 MG |
7021 | int ret; |
7022 | ||
7023 | init_emulate_ctxt(vcpu); | |
7024 | ||
9dac77fa AK |
7025 | ctxt->op_bytes = 2; |
7026 | ctxt->ad_bytes = 2; | |
7027 | ctxt->_eip = ctxt->eip + inc_eip; | |
9d74191a | 7028 | ret = emulate_int_real(ctxt, irq); |
63995653 | 7029 | |
9497e1f2 SC |
7030 | if (ret != X86EMUL_CONTINUE) { |
7031 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
7032 | } else { | |
7033 | ctxt->eip = ctxt->_eip; | |
7034 | kvm_rip_write(vcpu, ctxt->eip); | |
7035 | kvm_set_rflags(vcpu, ctxt->eflags); | |
7036 | } | |
63995653 MG |
7037 | } |
7038 | EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); | |
7039 | ||
e2366171 | 7040 | static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) |
6d77dbfc | 7041 | { |
6d77dbfc GN |
7042 | ++vcpu->stat.insn_emulation_fail; |
7043 | trace_kvm_emulate_insn_failed(vcpu); | |
e2366171 | 7044 | |
42cbf068 SC |
7045 | if (emulation_type & EMULTYPE_VMWARE_GP) { |
7046 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
60fc3d02 | 7047 | return 1; |
42cbf068 | 7048 | } |
e2366171 | 7049 | |
738fece4 SC |
7050 | if (emulation_type & EMULTYPE_SKIP) { |
7051 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
7052 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
7053 | vcpu->run->internal.ndata = 0; | |
60fc3d02 | 7054 | return 0; |
738fece4 SC |
7055 | } |
7056 | ||
22da61c9 SC |
7057 | kvm_queue_exception(vcpu, UD_VECTOR); |
7058 | ||
afaf0b2f | 7059 | if (!is_guest_mode(vcpu) && kvm_x86_ops.get_cpl(vcpu) == 0) { |
fc3a9157 JR |
7060 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
7061 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
7062 | vcpu->run->internal.ndata = 0; | |
60fc3d02 | 7063 | return 0; |
fc3a9157 | 7064 | } |
e2366171 | 7065 | |
60fc3d02 | 7066 | return 1; |
6d77dbfc GN |
7067 | } |
7068 | ||
736c291c | 7069 | static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
991eebf9 GN |
7070 | bool write_fault_to_shadow_pgtable, |
7071 | int emulation_type) | |
a6f177ef | 7072 | { |
736c291c | 7073 | gpa_t gpa = cr2_or_gpa; |
ba049e93 | 7074 | kvm_pfn_t pfn; |
a6f177ef | 7075 | |
92daa48b | 7076 | if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) |
991eebf9 GN |
7077 | return false; |
7078 | ||
92daa48b SC |
7079 | if (WARN_ON_ONCE(is_guest_mode(vcpu)) || |
7080 | WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) | |
6c3dfeb6 SC |
7081 | return false; |
7082 | ||
44dd3ffa | 7083 | if (!vcpu->arch.mmu->direct_map) { |
95b3cf69 XG |
7084 | /* |
7085 | * Write permission should be allowed since only | |
7086 | * write access need to be emulated. | |
7087 | */ | |
736c291c | 7088 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); |
a6f177ef | 7089 | |
95b3cf69 XG |
7090 | /* |
7091 | * If the mapping is invalid in guest, let cpu retry | |
7092 | * it to generate fault. | |
7093 | */ | |
7094 | if (gpa == UNMAPPED_GVA) | |
7095 | return true; | |
7096 | } | |
a6f177ef | 7097 | |
8e3d9d06 XG |
7098 | /* |
7099 | * Do not retry the unhandleable instruction if it faults on the | |
7100 | * readonly host memory, otherwise it will goto a infinite loop: | |
7101 | * retry instruction -> write #PF -> emulation fail -> retry | |
7102 | * instruction -> ... | |
7103 | */ | |
7104 | pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); | |
95b3cf69 XG |
7105 | |
7106 | /* | |
7107 | * If the instruction failed on the error pfn, it can not be fixed, | |
7108 | * report the error to userspace. | |
7109 | */ | |
7110 | if (is_error_noslot_pfn(pfn)) | |
7111 | return false; | |
7112 | ||
7113 | kvm_release_pfn_clean(pfn); | |
7114 | ||
7115 | /* The instructions are well-emulated on direct mmu. */ | |
44dd3ffa | 7116 | if (vcpu->arch.mmu->direct_map) { |
95b3cf69 XG |
7117 | unsigned int indirect_shadow_pages; |
7118 | ||
7119 | spin_lock(&vcpu->kvm->mmu_lock); | |
7120 | indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; | |
7121 | spin_unlock(&vcpu->kvm->mmu_lock); | |
7122 | ||
7123 | if (indirect_shadow_pages) | |
7124 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
7125 | ||
a6f177ef | 7126 | return true; |
8e3d9d06 | 7127 | } |
a6f177ef | 7128 | |
95b3cf69 XG |
7129 | /* |
7130 | * if emulation was due to access to shadowed page table | |
7131 | * and it failed try to unshadow page and re-enter the | |
7132 | * guest to let CPU execute the instruction. | |
7133 | */ | |
7134 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
93c05d3e XG |
7135 | |
7136 | /* | |
7137 | * If the access faults on its page table, it can not | |
7138 | * be fixed by unprotecting shadow page and it should | |
7139 | * be reported to userspace. | |
7140 | */ | |
7141 | return !write_fault_to_shadow_pgtable; | |
a6f177ef GN |
7142 | } |
7143 | ||
1cb3f3ae | 7144 | static bool retry_instruction(struct x86_emulate_ctxt *ctxt, |
736c291c | 7145 | gpa_t cr2_or_gpa, int emulation_type) |
1cb3f3ae XG |
7146 | { |
7147 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
736c291c | 7148 | unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa; |
1cb3f3ae XG |
7149 | |
7150 | last_retry_eip = vcpu->arch.last_retry_eip; | |
7151 | last_retry_addr = vcpu->arch.last_retry_addr; | |
7152 | ||
7153 | /* | |
7154 | * If the emulation is caused by #PF and it is non-page_table | |
7155 | * writing instruction, it means the VM-EXIT is caused by shadow | |
7156 | * page protected, we can zap the shadow page and retry this | |
7157 | * instruction directly. | |
7158 | * | |
7159 | * Note: if the guest uses a non-page-table modifying instruction | |
7160 | * on the PDE that points to the instruction, then we will unmap | |
7161 | * the instruction and go to an infinite loop. So, we cache the | |
7162 | * last retried eip and the last fault address, if we meet the eip | |
7163 | * and the address again, we can break out of the potential infinite | |
7164 | * loop. | |
7165 | */ | |
7166 | vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; | |
7167 | ||
92daa48b | 7168 | if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) |
1cb3f3ae XG |
7169 | return false; |
7170 | ||
92daa48b SC |
7171 | if (WARN_ON_ONCE(is_guest_mode(vcpu)) || |
7172 | WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) | |
6c3dfeb6 SC |
7173 | return false; |
7174 | ||
1cb3f3ae XG |
7175 | if (x86_page_table_writing_insn(ctxt)) |
7176 | return false; | |
7177 | ||
736c291c | 7178 | if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa) |
1cb3f3ae XG |
7179 | return false; |
7180 | ||
7181 | vcpu->arch.last_retry_eip = ctxt->eip; | |
736c291c | 7182 | vcpu->arch.last_retry_addr = cr2_or_gpa; |
1cb3f3ae | 7183 | |
44dd3ffa | 7184 | if (!vcpu->arch.mmu->direct_map) |
736c291c | 7185 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); |
1cb3f3ae | 7186 | |
22368028 | 7187 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); |
1cb3f3ae XG |
7188 | |
7189 | return true; | |
7190 | } | |
7191 | ||
716d51ab GN |
7192 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu); |
7193 | static int complete_emulated_pio(struct kvm_vcpu *vcpu); | |
7194 | ||
64d60670 | 7195 | static void kvm_smm_changed(struct kvm_vcpu *vcpu) |
a584539b | 7196 | { |
64d60670 | 7197 | if (!(vcpu->arch.hflags & HF_SMM_MASK)) { |
660a5d51 PB |
7198 | /* This is a good place to trace that we are exiting SMM. */ |
7199 | trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); | |
7200 | ||
c43203ca PB |
7201 | /* Process a latched INIT or SMI, if any. */ |
7202 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
64d60670 | 7203 | } |
699023e2 PB |
7204 | |
7205 | kvm_mmu_reset_context(vcpu); | |
64d60670 PB |
7206 | } |
7207 | ||
4a1e10d5 PB |
7208 | static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, |
7209 | unsigned long *db) | |
7210 | { | |
7211 | u32 dr6 = 0; | |
7212 | int i; | |
7213 | u32 enable, rwlen; | |
7214 | ||
7215 | enable = dr7; | |
7216 | rwlen = dr7 >> 16; | |
7217 | for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) | |
7218 | if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) | |
7219 | dr6 |= (1 << i); | |
7220 | return dr6; | |
7221 | } | |
7222 | ||
120c2c4f | 7223 | static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu) |
663f4c61 PB |
7224 | { |
7225 | struct kvm_run *kvm_run = vcpu->run; | |
7226 | ||
c8401dda | 7227 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { |
9a3ecd5e | 7228 | kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW; |
d5d260c5 | 7229 | kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu); |
c8401dda PB |
7230 | kvm_run->debug.arch.exception = DB_VECTOR; |
7231 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
60fc3d02 | 7232 | return 0; |
663f4c61 | 7233 | } |
120c2c4f | 7234 | kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); |
60fc3d02 | 7235 | return 1; |
663f4c61 PB |
7236 | } |
7237 | ||
6affcbed KH |
7238 | int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) |
7239 | { | |
afaf0b2f | 7240 | unsigned long rflags = kvm_x86_ops.get_rflags(vcpu); |
f8ea7c60 | 7241 | int r; |
6affcbed | 7242 | |
afaf0b2f | 7243 | r = kvm_x86_ops.skip_emulated_instruction(vcpu); |
60fc3d02 | 7244 | if (unlikely(!r)) |
f8ea7c60 | 7245 | return 0; |
c8401dda PB |
7246 | |
7247 | /* | |
7248 | * rflags is the old, "raw" value of the flags. The new value has | |
7249 | * not been saved yet. | |
7250 | * | |
7251 | * This is correct even for TF set by the guest, because "the | |
7252 | * processor will not generate this exception after the instruction | |
7253 | * that sets the TF flag". | |
7254 | */ | |
7255 | if (unlikely(rflags & X86_EFLAGS_TF)) | |
120c2c4f | 7256 | r = kvm_vcpu_do_singlestep(vcpu); |
60fc3d02 | 7257 | return r; |
6affcbed KH |
7258 | } |
7259 | EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); | |
7260 | ||
4a1e10d5 PB |
7261 | static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) |
7262 | { | |
4a1e10d5 PB |
7263 | if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && |
7264 | (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { | |
82b32774 NA |
7265 | struct kvm_run *kvm_run = vcpu->run; |
7266 | unsigned long eip = kvm_get_linear_rip(vcpu); | |
7267 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
7268 | vcpu->arch.guest_debug_dr7, |
7269 | vcpu->arch.eff_db); | |
7270 | ||
7271 | if (dr6 != 0) { | |
9a3ecd5e | 7272 | kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW; |
82b32774 | 7273 | kvm_run->debug.arch.pc = eip; |
4a1e10d5 PB |
7274 | kvm_run->debug.arch.exception = DB_VECTOR; |
7275 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
60fc3d02 | 7276 | *r = 0; |
4a1e10d5 PB |
7277 | return true; |
7278 | } | |
7279 | } | |
7280 | ||
4161a569 NA |
7281 | if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && |
7282 | !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { | |
82b32774 NA |
7283 | unsigned long eip = kvm_get_linear_rip(vcpu); |
7284 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
7285 | vcpu->arch.dr7, |
7286 | vcpu->arch.db); | |
7287 | ||
7288 | if (dr6 != 0) { | |
4d5523cf | 7289 | kvm_queue_exception_p(vcpu, DB_VECTOR, dr6); |
60fc3d02 | 7290 | *r = 1; |
4a1e10d5 PB |
7291 | return true; |
7292 | } | |
7293 | } | |
7294 | ||
7295 | return false; | |
7296 | } | |
7297 | ||
04789b66 LA |
7298 | static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) |
7299 | { | |
2d7921c4 AM |
7300 | switch (ctxt->opcode_len) { |
7301 | case 1: | |
7302 | switch (ctxt->b) { | |
7303 | case 0xe4: /* IN */ | |
7304 | case 0xe5: | |
7305 | case 0xec: | |
7306 | case 0xed: | |
7307 | case 0xe6: /* OUT */ | |
7308 | case 0xe7: | |
7309 | case 0xee: | |
7310 | case 0xef: | |
7311 | case 0x6c: /* INS */ | |
7312 | case 0x6d: | |
7313 | case 0x6e: /* OUTS */ | |
7314 | case 0x6f: | |
7315 | return true; | |
7316 | } | |
7317 | break; | |
7318 | case 2: | |
7319 | switch (ctxt->b) { | |
7320 | case 0x33: /* RDPMC */ | |
7321 | return true; | |
7322 | } | |
7323 | break; | |
04789b66 LA |
7324 | } |
7325 | ||
7326 | return false; | |
7327 | } | |
7328 | ||
4aa2691d WH |
7329 | /* |
7330 | * Decode to be emulated instruction. Return EMULATION_OK if success. | |
7331 | */ | |
7332 | int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type, | |
7333 | void *insn, int insn_len) | |
7334 | { | |
7335 | int r = EMULATION_OK; | |
7336 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; | |
7337 | ||
7338 | init_emulate_ctxt(vcpu); | |
7339 | ||
7340 | /* | |
7341 | * We will reenter on the same instruction since we do not set | |
7342 | * complete_userspace_io. This does not handle watchpoints yet, | |
7343 | * those would be handled in the emulate_ops. | |
7344 | */ | |
7345 | if (!(emulation_type & EMULTYPE_SKIP) && | |
7346 | kvm_vcpu_check_breakpoint(vcpu, &r)) | |
7347 | return r; | |
7348 | ||
7349 | ctxt->interruptibility = 0; | |
7350 | ctxt->have_exception = false; | |
7351 | ctxt->exception.vector = -1; | |
7352 | ctxt->perm_ok = false; | |
7353 | ||
7354 | ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; | |
7355 | ||
7356 | r = x86_decode_insn(ctxt, insn, insn_len); | |
7357 | ||
7358 | trace_kvm_emulate_insn_start(vcpu); | |
7359 | ++vcpu->stat.insn_emulation; | |
7360 | ||
7361 | return r; | |
7362 | } | |
7363 | EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction); | |
7364 | ||
736c291c SC |
7365 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
7366 | int emulation_type, void *insn, int insn_len) | |
bbd9b64e | 7367 | { |
95cb2295 | 7368 | int r; |
c9b8b07c | 7369 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
7ae441ea | 7370 | bool writeback = true; |
09e3e2a1 SC |
7371 | bool write_fault_to_spt; |
7372 | ||
7373 | if (unlikely(!kvm_x86_ops.can_emulate_instruction(vcpu, insn, insn_len))) | |
7374 | return 1; | |
bbd9b64e | 7375 | |
c595ceee PB |
7376 | vcpu->arch.l1tf_flush_l1d = true; |
7377 | ||
93c05d3e XG |
7378 | /* |
7379 | * Clear write_fault_to_shadow_pgtable here to ensure it is | |
7380 | * never reused. | |
7381 | */ | |
09e3e2a1 | 7382 | write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; |
93c05d3e | 7383 | vcpu->arch.write_fault_to_shadow_pgtable = false; |
8d7d8102 | 7384 | |
571008da | 7385 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
4aa2691d | 7386 | kvm_clear_exception_queue(vcpu); |
bbd9b64e | 7387 | |
4aa2691d WH |
7388 | r = x86_decode_emulated_instruction(vcpu, emulation_type, |
7389 | insn, insn_len); | |
1d2887e2 | 7390 | if (r != EMULATION_OK) { |
b4000606 | 7391 | if ((emulation_type & EMULTYPE_TRAP_UD) || |
c83fad65 SC |
7392 | (emulation_type & EMULTYPE_TRAP_UD_FORCED)) { |
7393 | kvm_queue_exception(vcpu, UD_VECTOR); | |
60fc3d02 | 7394 | return 1; |
c83fad65 | 7395 | } |
736c291c SC |
7396 | if (reexecute_instruction(vcpu, cr2_or_gpa, |
7397 | write_fault_to_spt, | |
7398 | emulation_type)) | |
60fc3d02 | 7399 | return 1; |
8530a79c | 7400 | if (ctxt->have_exception) { |
c8848cee JD |
7401 | /* |
7402 | * #UD should result in just EMULATION_FAILED, and trap-like | |
7403 | * exception should not be encountered during decode. | |
7404 | */ | |
7405 | WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || | |
7406 | exception_type(ctxt->exception.vector) == EXCPT_TRAP); | |
8530a79c | 7407 | inject_emulated_exception(vcpu); |
60fc3d02 | 7408 | return 1; |
8530a79c | 7409 | } |
e2366171 | 7410 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
7411 | } |
7412 | } | |
7413 | ||
42cbf068 SC |
7414 | if ((emulation_type & EMULTYPE_VMWARE_GP) && |
7415 | !is_vmware_backdoor_opcode(ctxt)) { | |
7416 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
60fc3d02 | 7417 | return 1; |
42cbf068 | 7418 | } |
04789b66 | 7419 | |
1957aa63 SC |
7420 | /* |
7421 | * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks | |
7422 | * for kvm_skip_emulated_instruction(). The caller is responsible for | |
7423 | * updating interruptibility state and injecting single-step #DBs. | |
7424 | */ | |
ba8afb6b | 7425 | if (emulation_type & EMULTYPE_SKIP) { |
9dac77fa | 7426 | kvm_rip_write(vcpu, ctxt->_eip); |
bb663c7a NA |
7427 | if (ctxt->eflags & X86_EFLAGS_RF) |
7428 | kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); | |
60fc3d02 | 7429 | return 1; |
ba8afb6b GN |
7430 | } |
7431 | ||
736c291c | 7432 | if (retry_instruction(ctxt, cr2_or_gpa, emulation_type)) |
60fc3d02 | 7433 | return 1; |
1cb3f3ae | 7434 | |
7ae441ea | 7435 | /* this is needed for vmware backdoor interface to work since it |
4d2179e1 | 7436 | changes registers values during IO operation */ |
7ae441ea GN |
7437 | if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { |
7438 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; | |
dd856efa | 7439 | emulator_invalidate_register_cache(ctxt); |
7ae441ea | 7440 | } |
4d2179e1 | 7441 | |
5cd21917 | 7442 | restart: |
92daa48b SC |
7443 | if (emulation_type & EMULTYPE_PF) { |
7444 | /* Save the faulting GPA (cr2) in the address field */ | |
7445 | ctxt->exception.address = cr2_or_gpa; | |
7446 | ||
7447 | /* With shadow page tables, cr2 contains a GVA or nGPA. */ | |
7448 | if (vcpu->arch.mmu->direct_map) { | |
744e699c SC |
7449 | ctxt->gpa_available = true; |
7450 | ctxt->gpa_val = cr2_or_gpa; | |
92daa48b SC |
7451 | } |
7452 | } else { | |
7453 | /* Sanitize the address out of an abundance of paranoia. */ | |
7454 | ctxt->exception.address = 0; | |
7455 | } | |
0f89b207 | 7456 | |
9d74191a | 7457 | r = x86_emulate_insn(ctxt); |
bbd9b64e | 7458 | |
775fde86 | 7459 | if (r == EMULATION_INTERCEPTED) |
60fc3d02 | 7460 | return 1; |
775fde86 | 7461 | |
d2ddd1c4 | 7462 | if (r == EMULATION_FAILED) { |
736c291c | 7463 | if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt, |
991eebf9 | 7464 | emulation_type)) |
60fc3d02 | 7465 | return 1; |
c3cd7ffa | 7466 | |
e2366171 | 7467 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
7468 | } |
7469 | ||
9d74191a | 7470 | if (ctxt->have_exception) { |
60fc3d02 | 7471 | r = 1; |
ef54bcfe PB |
7472 | if (inject_emulated_exception(vcpu)) |
7473 | return r; | |
d2ddd1c4 | 7474 | } else if (vcpu->arch.pio.count) { |
0912c977 PB |
7475 | if (!vcpu->arch.pio.in) { |
7476 | /* FIXME: return into emulator if single-stepping. */ | |
3457e419 | 7477 | vcpu->arch.pio.count = 0; |
0912c977 | 7478 | } else { |
7ae441ea | 7479 | writeback = false; |
716d51ab GN |
7480 | vcpu->arch.complete_userspace_io = complete_emulated_pio; |
7481 | } | |
60fc3d02 | 7482 | r = 0; |
7ae441ea | 7483 | } else if (vcpu->mmio_needed) { |
bc8a0aaf SC |
7484 | ++vcpu->stat.mmio_exits; |
7485 | ||
7ae441ea GN |
7486 | if (!vcpu->mmio_is_write) |
7487 | writeback = false; | |
60fc3d02 | 7488 | r = 0; |
716d51ab | 7489 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; |
7ae441ea | 7490 | } else if (r == EMULATION_RESTART) |
5cd21917 | 7491 | goto restart; |
d2ddd1c4 | 7492 | else |
60fc3d02 | 7493 | r = 1; |
f850e2e6 | 7494 | |
7ae441ea | 7495 | if (writeback) { |
afaf0b2f | 7496 | unsigned long rflags = kvm_x86_ops.get_rflags(vcpu); |
9d74191a | 7497 | toggle_interruptibility(vcpu, ctxt->interruptibility); |
7ae441ea | 7498 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
38827dbd | 7499 | if (!ctxt->have_exception || |
75ee23b3 SC |
7500 | exception_type(ctxt->exception.vector) == EXCPT_TRAP) { |
7501 | kvm_rip_write(vcpu, ctxt->eip); | |
384dea1c | 7502 | if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) |
120c2c4f | 7503 | r = kvm_vcpu_do_singlestep(vcpu); |
afaf0b2f SC |
7504 | if (kvm_x86_ops.update_emulated_instruction) |
7505 | kvm_x86_ops.update_emulated_instruction(vcpu); | |
38827dbd | 7506 | __kvm_set_rflags(vcpu, ctxt->eflags); |
75ee23b3 | 7507 | } |
6addfc42 PB |
7508 | |
7509 | /* | |
7510 | * For STI, interrupts are shadowed; so KVM_REQ_EVENT will | |
7511 | * do nothing, and it will be requested again as soon as | |
7512 | * the shadow expires. But we still need to check here, | |
7513 | * because POPF has no interrupt shadow. | |
7514 | */ | |
7515 | if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) | |
7516 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7ae441ea GN |
7517 | } else |
7518 | vcpu->arch.emulate_regs_need_sync_to_vcpu = true; | |
e85d28f8 GN |
7519 | |
7520 | return r; | |
de7d789a | 7521 | } |
c60658d1 SC |
7522 | |
7523 | int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) | |
7524 | { | |
7525 | return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); | |
7526 | } | |
7527 | EXPORT_SYMBOL_GPL(kvm_emulate_instruction); | |
7528 | ||
7529 | int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, | |
7530 | void *insn, int insn_len) | |
7531 | { | |
7532 | return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); | |
7533 | } | |
7534 | EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); | |
de7d789a | 7535 | |
8764ed55 SC |
7536 | static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) |
7537 | { | |
7538 | vcpu->arch.pio.count = 0; | |
7539 | return 1; | |
7540 | } | |
7541 | ||
45def77e SC |
7542 | static int complete_fast_pio_out(struct kvm_vcpu *vcpu) |
7543 | { | |
7544 | vcpu->arch.pio.count = 0; | |
7545 | ||
7546 | if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) | |
7547 | return 1; | |
7548 | ||
7549 | return kvm_skip_emulated_instruction(vcpu); | |
7550 | } | |
7551 | ||
dca7f128 SC |
7552 | static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, |
7553 | unsigned short port) | |
de7d789a | 7554 | { |
de3cd117 | 7555 | unsigned long val = kvm_rax_read(vcpu); |
2e3bb4d8 SC |
7556 | int ret = emulator_pio_out(vcpu, size, port, &val, 1); |
7557 | ||
8764ed55 SC |
7558 | if (ret) |
7559 | return ret; | |
45def77e | 7560 | |
8764ed55 SC |
7561 | /* |
7562 | * Workaround userspace that relies on old KVM behavior of %rip being | |
7563 | * incremented prior to exiting to userspace to handle "OUT 0x7e". | |
7564 | */ | |
7565 | if (port == 0x7e && | |
7566 | kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { | |
7567 | vcpu->arch.complete_userspace_io = | |
7568 | complete_fast_pio_out_port_0x7e; | |
7569 | kvm_skip_emulated_instruction(vcpu); | |
7570 | } else { | |
45def77e SC |
7571 | vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); |
7572 | vcpu->arch.complete_userspace_io = complete_fast_pio_out; | |
7573 | } | |
8764ed55 | 7574 | return 0; |
de7d789a | 7575 | } |
de7d789a | 7576 | |
8370c3d0 TL |
7577 | static int complete_fast_pio_in(struct kvm_vcpu *vcpu) |
7578 | { | |
7579 | unsigned long val; | |
7580 | ||
7581 | /* We should only ever be called with arch.pio.count equal to 1 */ | |
7582 | BUG_ON(vcpu->arch.pio.count != 1); | |
7583 | ||
45def77e SC |
7584 | if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { |
7585 | vcpu->arch.pio.count = 0; | |
7586 | return 1; | |
7587 | } | |
7588 | ||
8370c3d0 | 7589 | /* For size less than 4 we merge, else we zero extend */ |
de3cd117 | 7590 | val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; |
8370c3d0 TL |
7591 | |
7592 | /* | |
2e3bb4d8 | 7593 | * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform |
8370c3d0 TL |
7594 | * the copy and tracing |
7595 | */ | |
2e3bb4d8 | 7596 | emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1); |
de3cd117 | 7597 | kvm_rax_write(vcpu, val); |
8370c3d0 | 7598 | |
45def77e | 7599 | return kvm_skip_emulated_instruction(vcpu); |
8370c3d0 TL |
7600 | } |
7601 | ||
dca7f128 SC |
7602 | static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, |
7603 | unsigned short port) | |
8370c3d0 TL |
7604 | { |
7605 | unsigned long val; | |
7606 | int ret; | |
7607 | ||
7608 | /* For size less than 4 we merge, else we zero extend */ | |
de3cd117 | 7609 | val = (size < 4) ? kvm_rax_read(vcpu) : 0; |
8370c3d0 | 7610 | |
2e3bb4d8 | 7611 | ret = emulator_pio_in(vcpu, size, port, &val, 1); |
8370c3d0 | 7612 | if (ret) { |
de3cd117 | 7613 | kvm_rax_write(vcpu, val); |
8370c3d0 TL |
7614 | return ret; |
7615 | } | |
7616 | ||
45def77e | 7617 | vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); |
8370c3d0 TL |
7618 | vcpu->arch.complete_userspace_io = complete_fast_pio_in; |
7619 | ||
7620 | return 0; | |
7621 | } | |
dca7f128 SC |
7622 | |
7623 | int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) | |
7624 | { | |
45def77e | 7625 | int ret; |
dca7f128 | 7626 | |
dca7f128 | 7627 | if (in) |
45def77e | 7628 | ret = kvm_fast_pio_in(vcpu, size, port); |
dca7f128 | 7629 | else |
45def77e SC |
7630 | ret = kvm_fast_pio_out(vcpu, size, port); |
7631 | return ret && kvm_skip_emulated_instruction(vcpu); | |
dca7f128 SC |
7632 | } |
7633 | EXPORT_SYMBOL_GPL(kvm_fast_pio); | |
8370c3d0 | 7634 | |
251a5fd6 | 7635 | static int kvmclock_cpu_down_prep(unsigned int cpu) |
8cfdc000 | 7636 | { |
0a3aee0d | 7637 | __this_cpu_write(cpu_tsc_khz, 0); |
251a5fd6 | 7638 | return 0; |
8cfdc000 ZA |
7639 | } |
7640 | ||
7641 | static void tsc_khz_changed(void *data) | |
c8076604 | 7642 | { |
8cfdc000 ZA |
7643 | struct cpufreq_freqs *freq = data; |
7644 | unsigned long khz = 0; | |
7645 | ||
7646 | if (data) | |
7647 | khz = freq->new; | |
7648 | else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
7649 | khz = cpufreq_quick_get(raw_smp_processor_id()); | |
7650 | if (!khz) | |
7651 | khz = tsc_khz; | |
0a3aee0d | 7652 | __this_cpu_write(cpu_tsc_khz, khz); |
c8076604 GH |
7653 | } |
7654 | ||
5fa4ec9c | 7655 | #ifdef CONFIG_X86_64 |
0092e434 VK |
7656 | static void kvm_hyperv_tsc_notifier(void) |
7657 | { | |
0092e434 VK |
7658 | struct kvm *kvm; |
7659 | struct kvm_vcpu *vcpu; | |
7660 | int cpu; | |
7661 | ||
0d9ce162 | 7662 | mutex_lock(&kvm_lock); |
0092e434 VK |
7663 | list_for_each_entry(kvm, &vm_list, vm_list) |
7664 | kvm_make_mclock_inprogress_request(kvm); | |
7665 | ||
7666 | hyperv_stop_tsc_emulation(); | |
7667 | ||
7668 | /* TSC frequency always matches when on Hyper-V */ | |
7669 | for_each_present_cpu(cpu) | |
7670 | per_cpu(cpu_tsc_khz, cpu) = tsc_khz; | |
7671 | kvm_max_guest_tsc_khz = tsc_khz; | |
7672 | ||
7673 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
7674 | struct kvm_arch *ka = &kvm->arch; | |
7675 | ||
7676 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
7677 | ||
7678 | pvclock_update_vm_gtod_copy(kvm); | |
7679 | ||
7680 | kvm_for_each_vcpu(cpu, vcpu, kvm) | |
7681 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
7682 | ||
7683 | kvm_for_each_vcpu(cpu, vcpu, kvm) | |
7684 | kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); | |
7685 | ||
7686 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
7687 | } | |
0d9ce162 | 7688 | mutex_unlock(&kvm_lock); |
0092e434 | 7689 | } |
5fa4ec9c | 7690 | #endif |
0092e434 | 7691 | |
df24014a | 7692 | static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) |
c8076604 | 7693 | { |
c8076604 GH |
7694 | struct kvm *kvm; |
7695 | struct kvm_vcpu *vcpu; | |
7696 | int i, send_ipi = 0; | |
7697 | ||
8cfdc000 ZA |
7698 | /* |
7699 | * We allow guests to temporarily run on slowing clocks, | |
7700 | * provided we notify them after, or to run on accelerating | |
7701 | * clocks, provided we notify them before. Thus time never | |
7702 | * goes backwards. | |
7703 | * | |
7704 | * However, we have a problem. We can't atomically update | |
7705 | * the frequency of a given CPU from this function; it is | |
7706 | * merely a notifier, which can be called from any CPU. | |
7707 | * Changing the TSC frequency at arbitrary points in time | |
7708 | * requires a recomputation of local variables related to | |
7709 | * the TSC for each VCPU. We must flag these local variables | |
7710 | * to be updated and be sure the update takes place with the | |
7711 | * new frequency before any guests proceed. | |
7712 | * | |
7713 | * Unfortunately, the combination of hotplug CPU and frequency | |
7714 | * change creates an intractable locking scenario; the order | |
7715 | * of when these callouts happen is undefined with respect to | |
7716 | * CPU hotplug, and they can race with each other. As such, | |
7717 | * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is | |
7718 | * undefined; you can actually have a CPU frequency change take | |
7719 | * place in between the computation of X and the setting of the | |
7720 | * variable. To protect against this problem, all updates of | |
7721 | * the per_cpu tsc_khz variable are done in an interrupt | |
7722 | * protected IPI, and all callers wishing to update the value | |
7723 | * must wait for a synchronous IPI to complete (which is trivial | |
7724 | * if the caller is on the CPU already). This establishes the | |
7725 | * necessary total order on variable updates. | |
7726 | * | |
7727 | * Note that because a guest time update may take place | |
7728 | * anytime after the setting of the VCPU's request bit, the | |
7729 | * correct TSC value must be set before the request. However, | |
7730 | * to ensure the update actually makes it to any guest which | |
7731 | * starts running in hardware virtualization between the set | |
7732 | * and the acquisition of the spinlock, we must also ping the | |
7733 | * CPU after setting the request bit. | |
7734 | * | |
7735 | */ | |
7736 | ||
df24014a | 7737 | smp_call_function_single(cpu, tsc_khz_changed, freq, 1); |
c8076604 | 7738 | |
0d9ce162 | 7739 | mutex_lock(&kvm_lock); |
c8076604 | 7740 | list_for_each_entry(kvm, &vm_list, vm_list) { |
988a2cae | 7741 | kvm_for_each_vcpu(i, vcpu, kvm) { |
df24014a | 7742 | if (vcpu->cpu != cpu) |
c8076604 | 7743 | continue; |
c285545f | 7744 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0d9ce162 | 7745 | if (vcpu->cpu != raw_smp_processor_id()) |
8cfdc000 | 7746 | send_ipi = 1; |
c8076604 GH |
7747 | } |
7748 | } | |
0d9ce162 | 7749 | mutex_unlock(&kvm_lock); |
c8076604 GH |
7750 | |
7751 | if (freq->old < freq->new && send_ipi) { | |
7752 | /* | |
7753 | * We upscale the frequency. Must make the guest | |
7754 | * doesn't see old kvmclock values while running with | |
7755 | * the new frequency, otherwise we risk the guest sees | |
7756 | * time go backwards. | |
7757 | * | |
7758 | * In case we update the frequency for another cpu | |
7759 | * (which might be in guest context) send an interrupt | |
7760 | * to kick the cpu out of guest context. Next time | |
7761 | * guest context is entered kvmclock will be updated, | |
7762 | * so the guest will not see stale values. | |
7763 | */ | |
df24014a | 7764 | smp_call_function_single(cpu, tsc_khz_changed, freq, 1); |
c8076604 | 7765 | } |
df24014a VK |
7766 | } |
7767 | ||
7768 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, | |
7769 | void *data) | |
7770 | { | |
7771 | struct cpufreq_freqs *freq = data; | |
7772 | int cpu; | |
7773 | ||
7774 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) | |
7775 | return 0; | |
7776 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
7777 | return 0; | |
7778 | ||
7779 | for_each_cpu(cpu, freq->policy->cpus) | |
7780 | __kvmclock_cpufreq_notifier(freq, cpu); | |
7781 | ||
c8076604 GH |
7782 | return 0; |
7783 | } | |
7784 | ||
7785 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
8cfdc000 ZA |
7786 | .notifier_call = kvmclock_cpufreq_notifier |
7787 | }; | |
7788 | ||
251a5fd6 | 7789 | static int kvmclock_cpu_online(unsigned int cpu) |
8cfdc000 | 7790 | { |
251a5fd6 SAS |
7791 | tsc_khz_changed(NULL); |
7792 | return 0; | |
8cfdc000 ZA |
7793 | } |
7794 | ||
b820cc0c ZA |
7795 | static void kvm_timer_init(void) |
7796 | { | |
c285545f | 7797 | max_tsc_khz = tsc_khz; |
460dd42e | 7798 | |
b820cc0c | 7799 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
c285545f | 7800 | #ifdef CONFIG_CPU_FREQ |
aaec7c03 | 7801 | struct cpufreq_policy *policy; |
758f588d BP |
7802 | int cpu; |
7803 | ||
3e26f230 | 7804 | cpu = get_cpu(); |
aaec7c03 | 7805 | policy = cpufreq_cpu_get(cpu); |
9a11997e WL |
7806 | if (policy) { |
7807 | if (policy->cpuinfo.max_freq) | |
7808 | max_tsc_khz = policy->cpuinfo.max_freq; | |
7809 | cpufreq_cpu_put(policy); | |
7810 | } | |
3e26f230 | 7811 | put_cpu(); |
c285545f | 7812 | #endif |
b820cc0c ZA |
7813 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
7814 | CPUFREQ_TRANSITION_NOTIFIER); | |
7815 | } | |
460dd42e | 7816 | |
73c1b41e | 7817 | cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", |
251a5fd6 | 7818 | kvmclock_cpu_online, kvmclock_cpu_down_prep); |
b820cc0c ZA |
7819 | } |
7820 | ||
dd60d217 AK |
7821 | DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); |
7822 | EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu); | |
ff9d07a0 | 7823 | |
f5132b01 | 7824 | int kvm_is_in_guest(void) |
ff9d07a0 | 7825 | { |
086c9855 | 7826 | return __this_cpu_read(current_vcpu) != NULL; |
ff9d07a0 ZY |
7827 | } |
7828 | ||
7829 | static int kvm_is_user_mode(void) | |
7830 | { | |
7831 | int user_mode = 3; | |
dcf46b94 | 7832 | |
086c9855 | 7833 | if (__this_cpu_read(current_vcpu)) |
afaf0b2f | 7834 | user_mode = kvm_x86_ops.get_cpl(__this_cpu_read(current_vcpu)); |
dcf46b94 | 7835 | |
ff9d07a0 ZY |
7836 | return user_mode != 0; |
7837 | } | |
7838 | ||
7839 | static unsigned long kvm_get_guest_ip(void) | |
7840 | { | |
7841 | unsigned long ip = 0; | |
dcf46b94 | 7842 | |
086c9855 AS |
7843 | if (__this_cpu_read(current_vcpu)) |
7844 | ip = kvm_rip_read(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 7845 | |
ff9d07a0 ZY |
7846 | return ip; |
7847 | } | |
7848 | ||
8479e04e LK |
7849 | static void kvm_handle_intel_pt_intr(void) |
7850 | { | |
7851 | struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu); | |
7852 | ||
7853 | kvm_make_request(KVM_REQ_PMI, vcpu); | |
7854 | __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT, | |
7855 | (unsigned long *)&vcpu->arch.pmu.global_status); | |
7856 | } | |
7857 | ||
ff9d07a0 ZY |
7858 | static struct perf_guest_info_callbacks kvm_guest_cbs = { |
7859 | .is_in_guest = kvm_is_in_guest, | |
7860 | .is_user_mode = kvm_is_user_mode, | |
7861 | .get_guest_ip = kvm_get_guest_ip, | |
8479e04e | 7862 | .handle_intel_pt_intr = kvm_handle_intel_pt_intr, |
ff9d07a0 ZY |
7863 | }; |
7864 | ||
16e8d74d MT |
7865 | #ifdef CONFIG_X86_64 |
7866 | static void pvclock_gtod_update_fn(struct work_struct *work) | |
7867 | { | |
d828199e MT |
7868 | struct kvm *kvm; |
7869 | ||
7870 | struct kvm_vcpu *vcpu; | |
7871 | int i; | |
7872 | ||
0d9ce162 | 7873 | mutex_lock(&kvm_lock); |
d828199e MT |
7874 | list_for_each_entry(kvm, &vm_list, vm_list) |
7875 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 7876 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
d828199e | 7877 | atomic_set(&kvm_guest_has_master_clock, 0); |
0d9ce162 | 7878 | mutex_unlock(&kvm_lock); |
16e8d74d MT |
7879 | } |
7880 | ||
7881 | static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); | |
7882 | ||
7883 | /* | |
7884 | * Notification about pvclock gtod data update. | |
7885 | */ | |
7886 | static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, | |
7887 | void *priv) | |
7888 | { | |
7889 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
7890 | struct timekeeper *tk = priv; | |
7891 | ||
7892 | update_pvclock_gtod(tk); | |
7893 | ||
7894 | /* disable master clock if host does not trust, or does not | |
b0c39dc6 | 7895 | * use, TSC based clocksource. |
16e8d74d | 7896 | */ |
b0c39dc6 | 7897 | if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && |
16e8d74d MT |
7898 | atomic_read(&kvm_guest_has_master_clock) != 0) |
7899 | queue_work(system_long_wq, &pvclock_gtod_work); | |
7900 | ||
7901 | return 0; | |
7902 | } | |
7903 | ||
7904 | static struct notifier_block pvclock_gtod_notifier = { | |
7905 | .notifier_call = pvclock_gtod_notify, | |
7906 | }; | |
7907 | #endif | |
7908 | ||
f8c16bba | 7909 | int kvm_arch_init(void *opaque) |
043405e1 | 7910 | { |
d008dfdb | 7911 | struct kvm_x86_init_ops *ops = opaque; |
b820cc0c | 7912 | int r; |
f8c16bba | 7913 | |
afaf0b2f | 7914 | if (kvm_x86_ops.hardware_enable) { |
f8c16bba | 7915 | printk(KERN_ERR "kvm: already loaded the other module\n"); |
56c6d28a ZX |
7916 | r = -EEXIST; |
7917 | goto out; | |
f8c16bba ZX |
7918 | } |
7919 | ||
7920 | if (!ops->cpu_has_kvm_support()) { | |
ef935c25 | 7921 | pr_err_ratelimited("kvm: no hardware support\n"); |
56c6d28a ZX |
7922 | r = -EOPNOTSUPP; |
7923 | goto out; | |
f8c16bba ZX |
7924 | } |
7925 | if (ops->disabled_by_bios()) { | |
ef935c25 | 7926 | pr_err_ratelimited("kvm: disabled by bios\n"); |
56c6d28a ZX |
7927 | r = -EOPNOTSUPP; |
7928 | goto out; | |
f8c16bba ZX |
7929 | } |
7930 | ||
b666a4b6 MO |
7931 | /* |
7932 | * KVM explicitly assumes that the guest has an FPU and | |
7933 | * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the | |
7934 | * vCPU's FPU state as a fxregs_state struct. | |
7935 | */ | |
7936 | if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { | |
7937 | printk(KERN_ERR "kvm: inadequate fpu\n"); | |
7938 | r = -EOPNOTSUPP; | |
7939 | goto out; | |
7940 | } | |
7941 | ||
013f6a5d | 7942 | r = -ENOMEM; |
ed8e4812 | 7943 | x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu), |
b666a4b6 MO |
7944 | __alignof__(struct fpu), SLAB_ACCOUNT, |
7945 | NULL); | |
7946 | if (!x86_fpu_cache) { | |
7947 | printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n"); | |
7948 | goto out; | |
7949 | } | |
7950 | ||
c9b8b07c SC |
7951 | x86_emulator_cache = kvm_alloc_emulator_cache(); |
7952 | if (!x86_emulator_cache) { | |
7953 | pr_err("kvm: failed to allocate cache for x86 emulator\n"); | |
7954 | goto out_free_x86_fpu_cache; | |
7955 | } | |
7956 | ||
7e34fbd0 SC |
7957 | user_return_msrs = alloc_percpu(struct kvm_user_return_msrs); |
7958 | if (!user_return_msrs) { | |
7959 | printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n"); | |
c9b8b07c | 7960 | goto out_free_x86_emulator_cache; |
013f6a5d MT |
7961 | } |
7962 | ||
97db56ce AK |
7963 | r = kvm_mmu_module_init(); |
7964 | if (r) | |
013f6a5d | 7965 | goto out_free_percpu; |
97db56ce | 7966 | |
7b52345e | 7967 | kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, |
ffb128c8 | 7968 | PT_DIRTY_MASK, PT64_NX_MASK, 0, |
d0ec49d4 | 7969 | PT_PRESENT_MASK, 0, sme_me_mask); |
b820cc0c | 7970 | kvm_timer_init(); |
c8076604 | 7971 | |
ff9d07a0 ZY |
7972 | perf_register_guest_info_callbacks(&kvm_guest_cbs); |
7973 | ||
cfc48181 | 7974 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
2acf923e | 7975 | host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); |
cfc48181 SC |
7976 | supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0; |
7977 | } | |
2acf923e | 7978 | |
0c5f81da WL |
7979 | if (pi_inject_timer == -1) |
7980 | pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER); | |
16e8d74d MT |
7981 | #ifdef CONFIG_X86_64 |
7982 | pvclock_gtod_register_notifier(&pvclock_gtod_notifier); | |
0092e434 | 7983 | |
5fa4ec9c | 7984 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 | 7985 | set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); |
16e8d74d MT |
7986 | #endif |
7987 | ||
f8c16bba | 7988 | return 0; |
56c6d28a | 7989 | |
013f6a5d | 7990 | out_free_percpu: |
7e34fbd0 | 7991 | free_percpu(user_return_msrs); |
c9b8b07c SC |
7992 | out_free_x86_emulator_cache: |
7993 | kmem_cache_destroy(x86_emulator_cache); | |
b666a4b6 MO |
7994 | out_free_x86_fpu_cache: |
7995 | kmem_cache_destroy(x86_fpu_cache); | |
56c6d28a | 7996 | out: |
56c6d28a | 7997 | return r; |
043405e1 | 7998 | } |
8776e519 | 7999 | |
f8c16bba ZX |
8000 | void kvm_arch_exit(void) |
8001 | { | |
0092e434 | 8002 | #ifdef CONFIG_X86_64 |
5fa4ec9c | 8003 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 VK |
8004 | clear_hv_tscchange_cb(); |
8005 | #endif | |
cef84c30 | 8006 | kvm_lapic_exit(); |
ff9d07a0 ZY |
8007 | perf_unregister_guest_info_callbacks(&kvm_guest_cbs); |
8008 | ||
888d256e JK |
8009 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
8010 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
8011 | CPUFREQ_TRANSITION_NOTIFIER); | |
251a5fd6 | 8012 | cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); |
16e8d74d MT |
8013 | #ifdef CONFIG_X86_64 |
8014 | pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); | |
8015 | #endif | |
afaf0b2f | 8016 | kvm_x86_ops.hardware_enable = NULL; |
56c6d28a | 8017 | kvm_mmu_module_exit(); |
7e34fbd0 | 8018 | free_percpu(user_return_msrs); |
b666a4b6 | 8019 | kmem_cache_destroy(x86_fpu_cache); |
56c6d28a | 8020 | } |
f8c16bba | 8021 | |
872f36eb | 8022 | static int __kvm_vcpu_halt(struct kvm_vcpu *vcpu, int state, int reason) |
8776e519 HB |
8023 | { |
8024 | ++vcpu->stat.halt_exits; | |
35754c98 | 8025 | if (lapic_in_kernel(vcpu)) { |
647daca2 | 8026 | vcpu->arch.mp_state = state; |
8776e519 HB |
8027 | return 1; |
8028 | } else { | |
647daca2 | 8029 | vcpu->run->exit_reason = reason; |
8776e519 HB |
8030 | return 0; |
8031 | } | |
8032 | } | |
647daca2 TL |
8033 | |
8034 | int kvm_vcpu_halt(struct kvm_vcpu *vcpu) | |
8035 | { | |
8036 | return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT); | |
8037 | } | |
5cb56059 JS |
8038 | EXPORT_SYMBOL_GPL(kvm_vcpu_halt); |
8039 | ||
8040 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) | |
8041 | { | |
6affcbed KH |
8042 | int ret = kvm_skip_emulated_instruction(vcpu); |
8043 | /* | |
8044 | * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered | |
8045 | * KVM_EXIT_DEBUG here. | |
8046 | */ | |
8047 | return kvm_vcpu_halt(vcpu) && ret; | |
5cb56059 | 8048 | } |
8776e519 HB |
8049 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); |
8050 | ||
647daca2 TL |
8051 | int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu) |
8052 | { | |
8053 | int ret = kvm_skip_emulated_instruction(vcpu); | |
8054 | ||
8055 | return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, KVM_EXIT_AP_RESET_HOLD) && ret; | |
8056 | } | |
8057 | EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold); | |
8058 | ||
8ef81a9a | 8059 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
8060 | static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, |
8061 | unsigned long clock_type) | |
8062 | { | |
8063 | struct kvm_clock_pairing clock_pairing; | |
899a31f5 | 8064 | struct timespec64 ts; |
80fbd89c | 8065 | u64 cycle; |
55dd00a7 MT |
8066 | int ret; |
8067 | ||
8068 | if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) | |
8069 | return -KVM_EOPNOTSUPP; | |
8070 | ||
7ca7f3b9 | 8071 | if (!kvm_get_walltime_and_clockread(&ts, &cycle)) |
55dd00a7 MT |
8072 | return -KVM_EOPNOTSUPP; |
8073 | ||
8074 | clock_pairing.sec = ts.tv_sec; | |
8075 | clock_pairing.nsec = ts.tv_nsec; | |
8076 | clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); | |
8077 | clock_pairing.flags = 0; | |
bcbfbd8e | 8078 | memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); |
55dd00a7 MT |
8079 | |
8080 | ret = 0; | |
8081 | if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, | |
8082 | sizeof(struct kvm_clock_pairing))) | |
8083 | ret = -KVM_EFAULT; | |
8084 | ||
8085 | return ret; | |
8086 | } | |
8ef81a9a | 8087 | #endif |
55dd00a7 | 8088 | |
6aef266c SV |
8089 | /* |
8090 | * kvm_pv_kick_cpu_op: Kick a vcpu. | |
8091 | * | |
8092 | * @apicid - apicid of vcpu to be kicked. | |
8093 | */ | |
8094 | static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) | |
8095 | { | |
24d2166b | 8096 | struct kvm_lapic_irq lapic_irq; |
6aef266c | 8097 | |
150a84fe | 8098 | lapic_irq.shorthand = APIC_DEST_NOSHORT; |
c96001c5 | 8099 | lapic_irq.dest_mode = APIC_DEST_PHYSICAL; |
ebd28fcb | 8100 | lapic_irq.level = 0; |
24d2166b | 8101 | lapic_irq.dest_id = apicid; |
93bbf0b8 | 8102 | lapic_irq.msi_redir_hint = false; |
6aef266c | 8103 | |
24d2166b | 8104 | lapic_irq.delivery_mode = APIC_DM_REMRD; |
795a149e | 8105 | kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); |
6aef266c SV |
8106 | } |
8107 | ||
4e19c36f SS |
8108 | bool kvm_apicv_activated(struct kvm *kvm) |
8109 | { | |
8110 | return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0); | |
8111 | } | |
8112 | EXPORT_SYMBOL_GPL(kvm_apicv_activated); | |
8113 | ||
8114 | void kvm_apicv_init(struct kvm *kvm, bool enable) | |
8115 | { | |
8116 | if (enable) | |
8117 | clear_bit(APICV_INHIBIT_REASON_DISABLE, | |
8118 | &kvm->arch.apicv_inhibit_reasons); | |
8119 | else | |
8120 | set_bit(APICV_INHIBIT_REASON_DISABLE, | |
8121 | &kvm->arch.apicv_inhibit_reasons); | |
8122 | } | |
8123 | EXPORT_SYMBOL_GPL(kvm_apicv_init); | |
8124 | ||
71506297 WL |
8125 | static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id) |
8126 | { | |
8127 | struct kvm_vcpu *target = NULL; | |
8128 | struct kvm_apic_map *map; | |
8129 | ||
8130 | rcu_read_lock(); | |
8131 | map = rcu_dereference(kvm->arch.apic_map); | |
8132 | ||
8133 | if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) | |
8134 | target = map->phys_map[dest_id]->vcpu; | |
8135 | ||
8136 | rcu_read_unlock(); | |
8137 | ||
266e85a5 | 8138 | if (target && READ_ONCE(target->ready)) |
71506297 WL |
8139 | kvm_vcpu_yield_to(target); |
8140 | } | |
8141 | ||
8776e519 HB |
8142 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
8143 | { | |
8144 | unsigned long nr, a0, a1, a2, a3, ret; | |
6356ee0c | 8145 | int op_64_bit; |
8776e519 | 8146 | |
696ca779 RK |
8147 | if (kvm_hv_hypercall_enabled(vcpu->kvm)) |
8148 | return kvm_hv_hypercall(vcpu); | |
55cd8e5a | 8149 | |
de3cd117 SC |
8150 | nr = kvm_rax_read(vcpu); |
8151 | a0 = kvm_rbx_read(vcpu); | |
8152 | a1 = kvm_rcx_read(vcpu); | |
8153 | a2 = kvm_rdx_read(vcpu); | |
8154 | a3 = kvm_rsi_read(vcpu); | |
8776e519 | 8155 | |
229456fc | 8156 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 8157 | |
a449c7aa NA |
8158 | op_64_bit = is_64_bit_mode(vcpu); |
8159 | if (!op_64_bit) { | |
8776e519 HB |
8160 | nr &= 0xFFFFFFFF; |
8161 | a0 &= 0xFFFFFFFF; | |
8162 | a1 &= 0xFFFFFFFF; | |
8163 | a2 &= 0xFFFFFFFF; | |
8164 | a3 &= 0xFFFFFFFF; | |
8165 | } | |
8166 | ||
afaf0b2f | 8167 | if (kvm_x86_ops.get_cpl(vcpu) != 0) { |
07708c4a | 8168 | ret = -KVM_EPERM; |
696ca779 | 8169 | goto out; |
07708c4a JK |
8170 | } |
8171 | ||
66570e96 OU |
8172 | ret = -KVM_ENOSYS; |
8173 | ||
8776e519 | 8174 | switch (nr) { |
b93463aa AK |
8175 | case KVM_HC_VAPIC_POLL_IRQ: |
8176 | ret = 0; | |
8177 | break; | |
6aef266c | 8178 | case KVM_HC_KICK_CPU: |
66570e96 OU |
8179 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT)) |
8180 | break; | |
8181 | ||
6aef266c | 8182 | kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); |
266e85a5 | 8183 | kvm_sched_yield(vcpu->kvm, a1); |
6aef266c SV |
8184 | ret = 0; |
8185 | break; | |
8ef81a9a | 8186 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
8187 | case KVM_HC_CLOCK_PAIRING: |
8188 | ret = kvm_pv_clock_pairing(vcpu, a0, a1); | |
8189 | break; | |
1ed199a4 | 8190 | #endif |
4180bf1b | 8191 | case KVM_HC_SEND_IPI: |
66570e96 OU |
8192 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI)) |
8193 | break; | |
8194 | ||
4180bf1b WL |
8195 | ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); |
8196 | break; | |
71506297 | 8197 | case KVM_HC_SCHED_YIELD: |
66570e96 OU |
8198 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD)) |
8199 | break; | |
8200 | ||
71506297 WL |
8201 | kvm_sched_yield(vcpu->kvm, a0); |
8202 | ret = 0; | |
8203 | break; | |
8776e519 HB |
8204 | default: |
8205 | ret = -KVM_ENOSYS; | |
8206 | break; | |
8207 | } | |
696ca779 | 8208 | out: |
a449c7aa NA |
8209 | if (!op_64_bit) |
8210 | ret = (u32)ret; | |
de3cd117 | 8211 | kvm_rax_write(vcpu, ret); |
6356ee0c | 8212 | |
f11c3a8d | 8213 | ++vcpu->stat.hypercalls; |
6356ee0c | 8214 | return kvm_skip_emulated_instruction(vcpu); |
8776e519 HB |
8215 | } |
8216 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
8217 | ||
b6785def | 8218 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) |
8776e519 | 8219 | { |
d6aa1000 | 8220 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
8776e519 | 8221 | char instruction[3]; |
5fdbf976 | 8222 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 8223 | |
afaf0b2f | 8224 | kvm_x86_ops.patch_hypercall(vcpu, instruction); |
8776e519 | 8225 | |
ce2e852e DV |
8226 | return emulator_write_emulated(ctxt, rip, instruction, 3, |
8227 | &ctxt->exception); | |
8776e519 HB |
8228 | } |
8229 | ||
851ba692 | 8230 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 8231 | { |
782d422b MG |
8232 | return vcpu->run->request_interrupt_window && |
8233 | likely(!pic_in_kernel(vcpu->kvm)); | |
b6c7a5dc HB |
8234 | } |
8235 | ||
851ba692 | 8236 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 8237 | { |
851ba692 AK |
8238 | struct kvm_run *kvm_run = vcpu->run; |
8239 | ||
f1c6366e TL |
8240 | /* |
8241 | * if_flag is obsolete and useless, so do not bother | |
8242 | * setting it for SEV-ES guests. Userspace can just | |
8243 | * use kvm_run->ready_for_interrupt_injection. | |
8244 | */ | |
8245 | kvm_run->if_flag = !vcpu->arch.guest_state_protected | |
8246 | && (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; | |
8247 | ||
2d3ad1f4 | 8248 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 8249 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
127a457a MG |
8250 | kvm_run->ready_for_interrupt_injection = |
8251 | pic_in_kernel(vcpu->kvm) || | |
782d422b | 8252 | kvm_vcpu_ready_for_interrupt_injection(vcpu); |
15aad3be CQ |
8253 | |
8254 | if (is_smm(vcpu)) | |
8255 | kvm_run->flags |= KVM_RUN_X86_SMM; | |
b6c7a5dc HB |
8256 | } |
8257 | ||
95ba8273 GN |
8258 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
8259 | { | |
8260 | int max_irr, tpr; | |
8261 | ||
afaf0b2f | 8262 | if (!kvm_x86_ops.update_cr8_intercept) |
95ba8273 GN |
8263 | return; |
8264 | ||
bce87cce | 8265 | if (!lapic_in_kernel(vcpu)) |
88c808fd AK |
8266 | return; |
8267 | ||
d62caabb AS |
8268 | if (vcpu->arch.apicv_active) |
8269 | return; | |
8270 | ||
8db3baa2 GN |
8271 | if (!vcpu->arch.apic->vapic_addr) |
8272 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
8273 | else | |
8274 | max_irr = -1; | |
95ba8273 GN |
8275 | |
8276 | if (max_irr != -1) | |
8277 | max_irr >>= 4; | |
8278 | ||
8279 | tpr = kvm_lapic_get_cr8(vcpu); | |
8280 | ||
afaf0b2f | 8281 | kvm_x86_ops.update_cr8_intercept(vcpu, tpr, max_irr); |
95ba8273 GN |
8282 | } |
8283 | ||
c9d40913 | 8284 | static void inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit) |
95ba8273 | 8285 | { |
b6b8a145 | 8286 | int r; |
c6b22f59 | 8287 | bool can_inject = true; |
b6b8a145 | 8288 | |
95ba8273 | 8289 | /* try to reinject previous events if any */ |
664f8e26 | 8290 | |
c6b22f59 | 8291 | if (vcpu->arch.exception.injected) { |
afaf0b2f | 8292 | kvm_x86_ops.queue_exception(vcpu); |
c6b22f59 PB |
8293 | can_inject = false; |
8294 | } | |
664f8e26 | 8295 | /* |
a042c26f LA |
8296 | * Do not inject an NMI or interrupt if there is a pending |
8297 | * exception. Exceptions and interrupts are recognized at | |
8298 | * instruction boundaries, i.e. the start of an instruction. | |
8299 | * Trap-like exceptions, e.g. #DB, have higher priority than | |
8300 | * NMIs and interrupts, i.e. traps are recognized before an | |
8301 | * NMI/interrupt that's pending on the same instruction. | |
8302 | * Fault-like exceptions, e.g. #GP and #PF, are the lowest | |
8303 | * priority, but are only generated (pended) during instruction | |
8304 | * execution, i.e. a pending fault-like exception means the | |
8305 | * fault occurred on the *previous* instruction and must be | |
8306 | * serviced prior to recognizing any new events in order to | |
8307 | * fully complete the previous instruction. | |
664f8e26 | 8308 | */ |
1a680e35 | 8309 | else if (!vcpu->arch.exception.pending) { |
c6b22f59 | 8310 | if (vcpu->arch.nmi_injected) { |
afaf0b2f | 8311 | kvm_x86_ops.set_nmi(vcpu); |
c6b22f59 PB |
8312 | can_inject = false; |
8313 | } else if (vcpu->arch.interrupt.injected) { | |
afaf0b2f | 8314 | kvm_x86_ops.set_irq(vcpu); |
c6b22f59 PB |
8315 | can_inject = false; |
8316 | } | |
664f8e26 WL |
8317 | } |
8318 | ||
3b82b8d7 SC |
8319 | WARN_ON_ONCE(vcpu->arch.exception.injected && |
8320 | vcpu->arch.exception.pending); | |
8321 | ||
1a680e35 LA |
8322 | /* |
8323 | * Call check_nested_events() even if we reinjected a previous event | |
8324 | * in order for caller to determine if it should require immediate-exit | |
8325 | * from L2 to L1 due to pending L1 events which require exit | |
8326 | * from L2 to L1. | |
8327 | */ | |
56083bdf | 8328 | if (is_guest_mode(vcpu)) { |
33b22172 | 8329 | r = kvm_x86_ops.nested_ops->check_events(vcpu); |
c9d40913 PB |
8330 | if (r < 0) |
8331 | goto busy; | |
664f8e26 WL |
8332 | } |
8333 | ||
8334 | /* try to inject new event if pending */ | |
b59bb7bd | 8335 | if (vcpu->arch.exception.pending) { |
5c1c85d0 AK |
8336 | trace_kvm_inj_exception(vcpu->arch.exception.nr, |
8337 | vcpu->arch.exception.has_error_code, | |
8338 | vcpu->arch.exception.error_code); | |
d6e8c854 | 8339 | |
664f8e26 WL |
8340 | vcpu->arch.exception.pending = false; |
8341 | vcpu->arch.exception.injected = true; | |
8342 | ||
d6e8c854 NA |
8343 | if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) |
8344 | __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | | |
8345 | X86_EFLAGS_RF); | |
8346 | ||
f10c729f | 8347 | if (vcpu->arch.exception.nr == DB_VECTOR) { |
f10c729f JM |
8348 | kvm_deliver_exception_payload(vcpu); |
8349 | if (vcpu->arch.dr7 & DR7_GD) { | |
8350 | vcpu->arch.dr7 &= ~DR7_GD; | |
8351 | kvm_update_dr7(vcpu); | |
8352 | } | |
6bdf0662 NA |
8353 | } |
8354 | ||
afaf0b2f | 8355 | kvm_x86_ops.queue_exception(vcpu); |
c6b22f59 | 8356 | can_inject = false; |
1a680e35 LA |
8357 | } |
8358 | ||
c9d40913 PB |
8359 | /* |
8360 | * Finally, inject interrupt events. If an event cannot be injected | |
8361 | * due to architectural conditions (e.g. IF=0) a window-open exit | |
8362 | * will re-request KVM_REQ_EVENT. Sometimes however an event is pending | |
8363 | * and can architecturally be injected, but we cannot do it right now: | |
8364 | * an interrupt could have arrived just now and we have to inject it | |
8365 | * as a vmexit, or there could already an event in the queue, which is | |
8366 | * indicated by can_inject. In that case we request an immediate exit | |
8367 | * in order to make progress and get back here for another iteration. | |
8368 | * The kvm_x86_ops hooks communicate this by returning -EBUSY. | |
8369 | */ | |
8370 | if (vcpu->arch.smi_pending) { | |
8371 | r = can_inject ? kvm_x86_ops.smi_allowed(vcpu, true) : -EBUSY; | |
8372 | if (r < 0) | |
8373 | goto busy; | |
8374 | if (r) { | |
8375 | vcpu->arch.smi_pending = false; | |
8376 | ++vcpu->arch.smi_count; | |
8377 | enter_smm(vcpu); | |
8378 | can_inject = false; | |
8379 | } else | |
8380 | kvm_x86_ops.enable_smi_window(vcpu); | |
8381 | } | |
8382 | ||
8383 | if (vcpu->arch.nmi_pending) { | |
8384 | r = can_inject ? kvm_x86_ops.nmi_allowed(vcpu, true) : -EBUSY; | |
8385 | if (r < 0) | |
8386 | goto busy; | |
8387 | if (r) { | |
8388 | --vcpu->arch.nmi_pending; | |
8389 | vcpu->arch.nmi_injected = true; | |
8390 | kvm_x86_ops.set_nmi(vcpu); | |
8391 | can_inject = false; | |
8392 | WARN_ON(kvm_x86_ops.nmi_allowed(vcpu, true) < 0); | |
8393 | } | |
8394 | if (vcpu->arch.nmi_pending) | |
8395 | kvm_x86_ops.enable_nmi_window(vcpu); | |
8396 | } | |
1a680e35 | 8397 | |
c9d40913 PB |
8398 | if (kvm_cpu_has_injectable_intr(vcpu)) { |
8399 | r = can_inject ? kvm_x86_ops.interrupt_allowed(vcpu, true) : -EBUSY; | |
8400 | if (r < 0) | |
8401 | goto busy; | |
8402 | if (r) { | |
8403 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false); | |
8404 | kvm_x86_ops.set_irq(vcpu); | |
8405 | WARN_ON(kvm_x86_ops.interrupt_allowed(vcpu, true) < 0); | |
8406 | } | |
8407 | if (kvm_cpu_has_injectable_intr(vcpu)) | |
8408 | kvm_x86_ops.enable_irq_window(vcpu); | |
95ba8273 | 8409 | } |
ee2cd4b7 | 8410 | |
c9d40913 PB |
8411 | if (is_guest_mode(vcpu) && |
8412 | kvm_x86_ops.nested_ops->hv_timer_pending && | |
8413 | kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) | |
8414 | *req_immediate_exit = true; | |
8415 | ||
8416 | WARN_ON(vcpu->arch.exception.pending); | |
8417 | return; | |
8418 | ||
8419 | busy: | |
8420 | *req_immediate_exit = true; | |
8421 | return; | |
95ba8273 GN |
8422 | } |
8423 | ||
7460fb4a AK |
8424 | static void process_nmi(struct kvm_vcpu *vcpu) |
8425 | { | |
8426 | unsigned limit = 2; | |
8427 | ||
8428 | /* | |
8429 | * x86 is limited to one NMI running, and one NMI pending after it. | |
8430 | * If an NMI is already in progress, limit further NMIs to just one. | |
8431 | * Otherwise, allow two (and we'll inject the first one immediately). | |
8432 | */ | |
afaf0b2f | 8433 | if (kvm_x86_ops.get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) |
7460fb4a AK |
8434 | limit = 1; |
8435 | ||
8436 | vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); | |
8437 | vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); | |
8438 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
8439 | } | |
8440 | ||
ee2cd4b7 | 8441 | static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) |
660a5d51 PB |
8442 | { |
8443 | u32 flags = 0; | |
8444 | flags |= seg->g << 23; | |
8445 | flags |= seg->db << 22; | |
8446 | flags |= seg->l << 21; | |
8447 | flags |= seg->avl << 20; | |
8448 | flags |= seg->present << 15; | |
8449 | flags |= seg->dpl << 13; | |
8450 | flags |= seg->s << 12; | |
8451 | flags |= seg->type << 8; | |
8452 | return flags; | |
8453 | } | |
8454 | ||
ee2cd4b7 | 8455 | static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) |
660a5d51 PB |
8456 | { |
8457 | struct kvm_segment seg; | |
8458 | int offset; | |
8459 | ||
8460 | kvm_get_segment(vcpu, &seg, n); | |
8461 | put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); | |
8462 | ||
8463 | if (n < 3) | |
8464 | offset = 0x7f84 + n * 12; | |
8465 | else | |
8466 | offset = 0x7f2c + (n - 3) * 12; | |
8467 | ||
8468 | put_smstate(u32, buf, offset + 8, seg.base); | |
8469 | put_smstate(u32, buf, offset + 4, seg.limit); | |
ee2cd4b7 | 8470 | put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
8471 | } |
8472 | ||
efbb288a | 8473 | #ifdef CONFIG_X86_64 |
ee2cd4b7 | 8474 | static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) |
660a5d51 PB |
8475 | { |
8476 | struct kvm_segment seg; | |
8477 | int offset; | |
8478 | u16 flags; | |
8479 | ||
8480 | kvm_get_segment(vcpu, &seg, n); | |
8481 | offset = 0x7e00 + n * 16; | |
8482 | ||
ee2cd4b7 | 8483 | flags = enter_smm_get_segment_flags(&seg) >> 8; |
660a5d51 PB |
8484 | put_smstate(u16, buf, offset, seg.selector); |
8485 | put_smstate(u16, buf, offset + 2, flags); | |
8486 | put_smstate(u32, buf, offset + 4, seg.limit); | |
8487 | put_smstate(u64, buf, offset + 8, seg.base); | |
8488 | } | |
efbb288a | 8489 | #endif |
660a5d51 | 8490 | |
ee2cd4b7 | 8491 | static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) |
660a5d51 PB |
8492 | { |
8493 | struct desc_ptr dt; | |
8494 | struct kvm_segment seg; | |
8495 | unsigned long val; | |
8496 | int i; | |
8497 | ||
8498 | put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); | |
8499 | put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); | |
8500 | put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); | |
8501 | put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); | |
8502 | ||
8503 | for (i = 0; i < 8; i++) | |
8504 | put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); | |
8505 | ||
8506 | kvm_get_dr(vcpu, 6, &val); | |
8507 | put_smstate(u32, buf, 0x7fcc, (u32)val); | |
8508 | kvm_get_dr(vcpu, 7, &val); | |
8509 | put_smstate(u32, buf, 0x7fc8, (u32)val); | |
8510 | ||
8511 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
8512 | put_smstate(u32, buf, 0x7fc4, seg.selector); | |
8513 | put_smstate(u32, buf, 0x7f64, seg.base); | |
8514 | put_smstate(u32, buf, 0x7f60, seg.limit); | |
ee2cd4b7 | 8515 | put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
8516 | |
8517 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
8518 | put_smstate(u32, buf, 0x7fc0, seg.selector); | |
8519 | put_smstate(u32, buf, 0x7f80, seg.base); | |
8520 | put_smstate(u32, buf, 0x7f7c, seg.limit); | |
ee2cd4b7 | 8521 | put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); |
660a5d51 | 8522 | |
afaf0b2f | 8523 | kvm_x86_ops.get_gdt(vcpu, &dt); |
660a5d51 PB |
8524 | put_smstate(u32, buf, 0x7f74, dt.address); |
8525 | put_smstate(u32, buf, 0x7f70, dt.size); | |
8526 | ||
afaf0b2f | 8527 | kvm_x86_ops.get_idt(vcpu, &dt); |
660a5d51 PB |
8528 | put_smstate(u32, buf, 0x7f58, dt.address); |
8529 | put_smstate(u32, buf, 0x7f54, dt.size); | |
8530 | ||
8531 | for (i = 0; i < 6; i++) | |
ee2cd4b7 | 8532 | enter_smm_save_seg_32(vcpu, buf, i); |
660a5d51 PB |
8533 | |
8534 | put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); | |
8535 | ||
8536 | /* revision id */ | |
8537 | put_smstate(u32, buf, 0x7efc, 0x00020000); | |
8538 | put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); | |
8539 | } | |
8540 | ||
b68f3cc7 | 8541 | #ifdef CONFIG_X86_64 |
ee2cd4b7 | 8542 | static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) |
660a5d51 | 8543 | { |
660a5d51 PB |
8544 | struct desc_ptr dt; |
8545 | struct kvm_segment seg; | |
8546 | unsigned long val; | |
8547 | int i; | |
8548 | ||
8549 | for (i = 0; i < 16; i++) | |
8550 | put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); | |
8551 | ||
8552 | put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); | |
8553 | put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); | |
8554 | ||
8555 | kvm_get_dr(vcpu, 6, &val); | |
8556 | put_smstate(u64, buf, 0x7f68, val); | |
8557 | kvm_get_dr(vcpu, 7, &val); | |
8558 | put_smstate(u64, buf, 0x7f60, val); | |
8559 | ||
8560 | put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); | |
8561 | put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); | |
8562 | put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); | |
8563 | ||
8564 | put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); | |
8565 | ||
8566 | /* revision id */ | |
8567 | put_smstate(u32, buf, 0x7efc, 0x00020064); | |
8568 | ||
8569 | put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); | |
8570 | ||
8571 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
8572 | put_smstate(u16, buf, 0x7e90, seg.selector); | |
ee2cd4b7 | 8573 | put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); |
660a5d51 PB |
8574 | put_smstate(u32, buf, 0x7e94, seg.limit); |
8575 | put_smstate(u64, buf, 0x7e98, seg.base); | |
8576 | ||
afaf0b2f | 8577 | kvm_x86_ops.get_idt(vcpu, &dt); |
660a5d51 PB |
8578 | put_smstate(u32, buf, 0x7e84, dt.size); |
8579 | put_smstate(u64, buf, 0x7e88, dt.address); | |
8580 | ||
8581 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
8582 | put_smstate(u16, buf, 0x7e70, seg.selector); | |
ee2cd4b7 | 8583 | put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); |
660a5d51 PB |
8584 | put_smstate(u32, buf, 0x7e74, seg.limit); |
8585 | put_smstate(u64, buf, 0x7e78, seg.base); | |
8586 | ||
afaf0b2f | 8587 | kvm_x86_ops.get_gdt(vcpu, &dt); |
660a5d51 PB |
8588 | put_smstate(u32, buf, 0x7e64, dt.size); |
8589 | put_smstate(u64, buf, 0x7e68, dt.address); | |
8590 | ||
8591 | for (i = 0; i < 6; i++) | |
ee2cd4b7 | 8592 | enter_smm_save_seg_64(vcpu, buf, i); |
660a5d51 | 8593 | } |
b68f3cc7 | 8594 | #endif |
660a5d51 | 8595 | |
ee2cd4b7 | 8596 | static void enter_smm(struct kvm_vcpu *vcpu) |
64d60670 | 8597 | { |
660a5d51 | 8598 | struct kvm_segment cs, ds; |
18c3626e | 8599 | struct desc_ptr dt; |
660a5d51 PB |
8600 | char buf[512]; |
8601 | u32 cr0; | |
8602 | ||
660a5d51 | 8603 | trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); |
660a5d51 | 8604 | memset(buf, 0, 512); |
b68f3cc7 | 8605 | #ifdef CONFIG_X86_64 |
d6321d49 | 8606 | if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) |
ee2cd4b7 | 8607 | enter_smm_save_state_64(vcpu, buf); |
660a5d51 | 8608 | else |
b68f3cc7 | 8609 | #endif |
ee2cd4b7 | 8610 | enter_smm_save_state_32(vcpu, buf); |
660a5d51 | 8611 | |
0234bf88 LP |
8612 | /* |
8613 | * Give pre_enter_smm() a chance to make ISA-specific changes to the | |
8614 | * vCPU state (e.g. leave guest mode) after we've saved the state into | |
8615 | * the SMM state-save area. | |
8616 | */ | |
afaf0b2f | 8617 | kvm_x86_ops.pre_enter_smm(vcpu, buf); |
0234bf88 LP |
8618 | |
8619 | vcpu->arch.hflags |= HF_SMM_MASK; | |
54bf36aa | 8620 | kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); |
660a5d51 | 8621 | |
afaf0b2f | 8622 | if (kvm_x86_ops.get_nmi_mask(vcpu)) |
660a5d51 PB |
8623 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; |
8624 | else | |
afaf0b2f | 8625 | kvm_x86_ops.set_nmi_mask(vcpu, true); |
660a5d51 PB |
8626 | |
8627 | kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); | |
8628 | kvm_rip_write(vcpu, 0x8000); | |
8629 | ||
8630 | cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); | |
afaf0b2f | 8631 | kvm_x86_ops.set_cr0(vcpu, cr0); |
660a5d51 PB |
8632 | vcpu->arch.cr0 = cr0; |
8633 | ||
afaf0b2f | 8634 | kvm_x86_ops.set_cr4(vcpu, 0); |
660a5d51 | 8635 | |
18c3626e PB |
8636 | /* Undocumented: IDT limit is set to zero on entry to SMM. */ |
8637 | dt.address = dt.size = 0; | |
afaf0b2f | 8638 | kvm_x86_ops.set_idt(vcpu, &dt); |
18c3626e | 8639 | |
660a5d51 PB |
8640 | __kvm_set_dr(vcpu, 7, DR7_FIXED_1); |
8641 | ||
8642 | cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; | |
8643 | cs.base = vcpu->arch.smbase; | |
8644 | ||
8645 | ds.selector = 0; | |
8646 | ds.base = 0; | |
8647 | ||
8648 | cs.limit = ds.limit = 0xffffffff; | |
8649 | cs.type = ds.type = 0x3; | |
8650 | cs.dpl = ds.dpl = 0; | |
8651 | cs.db = ds.db = 0; | |
8652 | cs.s = ds.s = 1; | |
8653 | cs.l = ds.l = 0; | |
8654 | cs.g = ds.g = 1; | |
8655 | cs.avl = ds.avl = 0; | |
8656 | cs.present = ds.present = 1; | |
8657 | cs.unusable = ds.unusable = 0; | |
8658 | cs.padding = ds.padding = 0; | |
8659 | ||
8660 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
8661 | kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); | |
8662 | kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); | |
8663 | kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); | |
8664 | kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); | |
8665 | kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); | |
8666 | ||
b68f3cc7 | 8667 | #ifdef CONFIG_X86_64 |
d6321d49 | 8668 | if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) |
afaf0b2f | 8669 | kvm_x86_ops.set_efer(vcpu, 0); |
b68f3cc7 | 8670 | #endif |
660a5d51 | 8671 | |
aedbaf4f | 8672 | kvm_update_cpuid_runtime(vcpu); |
660a5d51 | 8673 | kvm_mmu_reset_context(vcpu); |
64d60670 PB |
8674 | } |
8675 | ||
ee2cd4b7 | 8676 | static void process_smi(struct kvm_vcpu *vcpu) |
c43203ca PB |
8677 | { |
8678 | vcpu->arch.smi_pending = true; | |
8679 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
8680 | } | |
8681 | ||
7ee30bc1 NNL |
8682 | void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, |
8683 | unsigned long *vcpu_bitmap) | |
8684 | { | |
8685 | cpumask_var_t cpus; | |
7ee30bc1 NNL |
8686 | |
8687 | zalloc_cpumask_var(&cpus, GFP_ATOMIC); | |
8688 | ||
db5a95ec | 8689 | kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, |
54163a34 | 8690 | NULL, vcpu_bitmap, cpus); |
7ee30bc1 NNL |
8691 | |
8692 | free_cpumask_var(cpus); | |
8693 | } | |
8694 | ||
2860c4b1 PB |
8695 | void kvm_make_scan_ioapic_request(struct kvm *kvm) |
8696 | { | |
8697 | kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); | |
8698 | } | |
8699 | ||
8df14af4 SS |
8700 | void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) |
8701 | { | |
8702 | if (!lapic_in_kernel(vcpu)) | |
8703 | return; | |
8704 | ||
8705 | vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm); | |
8706 | kvm_apic_update_apicv(vcpu); | |
afaf0b2f | 8707 | kvm_x86_ops.refresh_apicv_exec_ctrl(vcpu); |
8df14af4 SS |
8708 | } |
8709 | EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv); | |
8710 | ||
8711 | /* | |
8712 | * NOTE: Do not hold any lock prior to calling this. | |
8713 | * | |
8714 | * In particular, kvm_request_apicv_update() expects kvm->srcu not to be | |
8715 | * locked, because it calls __x86_set_memory_region() which does | |
8716 | * synchronize_srcu(&kvm->srcu). | |
8717 | */ | |
8718 | void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit) | |
8719 | { | |
7d611233 | 8720 | struct kvm_vcpu *except; |
8e205a6b PB |
8721 | unsigned long old, new, expected; |
8722 | ||
afaf0b2f SC |
8723 | if (!kvm_x86_ops.check_apicv_inhibit_reasons || |
8724 | !kvm_x86_ops.check_apicv_inhibit_reasons(bit)) | |
ef8efd7a SS |
8725 | return; |
8726 | ||
8e205a6b PB |
8727 | old = READ_ONCE(kvm->arch.apicv_inhibit_reasons); |
8728 | do { | |
8729 | expected = new = old; | |
8730 | if (activate) | |
8731 | __clear_bit(bit, &new); | |
8732 | else | |
8733 | __set_bit(bit, &new); | |
8734 | if (new == old) | |
8735 | break; | |
8736 | old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new); | |
8737 | } while (old != expected); | |
8738 | ||
8739 | if (!!old == !!new) | |
8740 | return; | |
8df14af4 | 8741 | |
24bbf74c | 8742 | trace_kvm_apicv_update_request(activate, bit); |
afaf0b2f SC |
8743 | if (kvm_x86_ops.pre_update_apicv_exec_ctrl) |
8744 | kvm_x86_ops.pre_update_apicv_exec_ctrl(kvm, activate); | |
7d611233 SS |
8745 | |
8746 | /* | |
8747 | * Sending request to update APICV for all other vcpus, | |
8748 | * while update the calling vcpu immediately instead of | |
8749 | * waiting for another #VMEXIT to handle the request. | |
8750 | */ | |
8751 | except = kvm_get_running_vcpu(); | |
8752 | kvm_make_all_cpus_request_except(kvm, KVM_REQ_APICV_UPDATE, | |
8753 | except); | |
8754 | if (except) | |
8755 | kvm_vcpu_update_apicv(except); | |
8df14af4 SS |
8756 | } |
8757 | EXPORT_SYMBOL_GPL(kvm_request_apicv_update); | |
8758 | ||
3d81bc7e | 8759 | static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) |
c7c9c56c | 8760 | { |
dcbd3e49 | 8761 | if (!kvm_apic_present(vcpu)) |
3d81bc7e | 8762 | return; |
c7c9c56c | 8763 | |
6308630b | 8764 | bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); |
c7c9c56c | 8765 | |
b053b2ae | 8766 | if (irqchip_split(vcpu->kvm)) |
6308630b | 8767 | kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); |
db2bdcbb | 8768 | else { |
fa59cc00 | 8769 | if (vcpu->arch.apicv_active) |
afaf0b2f | 8770 | kvm_x86_ops.sync_pir_to_irr(vcpu); |
e97f852f WL |
8771 | if (ioapic_in_kernel(vcpu->kvm)) |
8772 | kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); | |
db2bdcbb | 8773 | } |
e40ff1d6 LA |
8774 | |
8775 | if (is_guest_mode(vcpu)) | |
8776 | vcpu->arch.load_eoi_exitmap_pending = true; | |
8777 | else | |
8778 | kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); | |
8779 | } | |
8780 | ||
8781 | static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) | |
8782 | { | |
8783 | u64 eoi_exit_bitmap[4]; | |
8784 | ||
8785 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) | |
8786 | return; | |
8787 | ||
5c919412 AS |
8788 | bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors, |
8789 | vcpu_to_synic(vcpu)->vec_bitmap, 256); | |
afaf0b2f | 8790 | kvm_x86_ops.load_eoi_exitmap(vcpu, eoi_exit_bitmap); |
c7c9c56c YZ |
8791 | } |
8792 | ||
e649b3f0 ET |
8793 | void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, |
8794 | unsigned long start, unsigned long end) | |
b1394e74 RK |
8795 | { |
8796 | unsigned long apic_address; | |
8797 | ||
8798 | /* | |
8799 | * The physical address of apic access page is stored in the VMCS. | |
8800 | * Update it when it becomes invalid. | |
8801 | */ | |
8802 | apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); | |
8803 | if (start <= apic_address && apic_address < end) | |
8804 | kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); | |
8805 | } | |
8806 | ||
4256f43f TC |
8807 | void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) |
8808 | { | |
35754c98 | 8809 | if (!lapic_in_kernel(vcpu)) |
f439ed27 PB |
8810 | return; |
8811 | ||
afaf0b2f | 8812 | if (!kvm_x86_ops.set_apic_access_page_addr) |
4256f43f TC |
8813 | return; |
8814 | ||
a4148b7c | 8815 | kvm_x86_ops.set_apic_access_page_addr(vcpu); |
4256f43f | 8816 | } |
4256f43f | 8817 | |
d264ee0c SC |
8818 | void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) |
8819 | { | |
8820 | smp_send_reschedule(vcpu->cpu); | |
8821 | } | |
8822 | EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); | |
8823 | ||
9357d939 | 8824 | /* |
362c698f | 8825 | * Returns 1 to let vcpu_run() continue the guest execution loop without |
9357d939 TY |
8826 | * exiting to the userspace. Otherwise, the value will be returned to the |
8827 | * userspace. | |
8828 | */ | |
851ba692 | 8829 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
8830 | { |
8831 | int r; | |
62a193ed MG |
8832 | bool req_int_win = |
8833 | dm_request_for_irq_injection(vcpu) && | |
8834 | kvm_cpu_accept_dm_intr(vcpu); | |
404d5d7b | 8835 | fastpath_t exit_fastpath; |
62a193ed | 8836 | |
730dca42 | 8837 | bool req_immediate_exit = false; |
b6c7a5dc | 8838 | |
fb04a1ed PX |
8839 | /* Forbid vmenter if vcpu dirty ring is soft-full */ |
8840 | if (unlikely(vcpu->kvm->dirty_ring_size && | |
8841 | kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) { | |
8842 | vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL; | |
8843 | trace_kvm_dirty_ring_exit(vcpu); | |
8844 | r = 0; | |
8845 | goto out; | |
8846 | } | |
8847 | ||
2fa6e1e1 | 8848 | if (kvm_request_pending(vcpu)) { |
729c15c2 | 8849 | if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) { |
9a78e158 | 8850 | if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) { |
671ddc70 JM |
8851 | r = 0; |
8852 | goto out; | |
8853 | } | |
8854 | } | |
a8eeb04a | 8855 | if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) |
2e53d63a | 8856 | kvm_mmu_unload(vcpu); |
a8eeb04a | 8857 | if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) |
2f599714 | 8858 | __kvm_migrate_timers(vcpu); |
d828199e MT |
8859 | if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) |
8860 | kvm_gen_update_masterclock(vcpu->kvm); | |
0061d53d MT |
8861 | if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) |
8862 | kvm_gen_kvmclock_update(vcpu); | |
34c238a1 ZA |
8863 | if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { |
8864 | r = kvm_guest_time_update(vcpu); | |
8cfdc000 ZA |
8865 | if (unlikely(r)) |
8866 | goto out; | |
8867 | } | |
a8eeb04a | 8868 | if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) |
4731d4c7 | 8869 | kvm_mmu_sync_roots(vcpu); |
727a7e27 PB |
8870 | if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu)) |
8871 | kvm_mmu_load_pgd(vcpu); | |
eeeb4f67 | 8872 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) { |
7780938c | 8873 | kvm_vcpu_flush_tlb_all(vcpu); |
eeeb4f67 SC |
8874 | |
8875 | /* Flushing all ASIDs flushes the current ASID... */ | |
8876 | kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); | |
8877 | } | |
8878 | if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu)) | |
8879 | kvm_vcpu_flush_tlb_current(vcpu); | |
0baedd79 VK |
8880 | if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu)) |
8881 | kvm_vcpu_flush_tlb_guest(vcpu); | |
eeeb4f67 | 8882 | |
a8eeb04a | 8883 | if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { |
851ba692 | 8884 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
8885 | r = 0; |
8886 | goto out; | |
8887 | } | |
a8eeb04a | 8888 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
851ba692 | 8889 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
bbeac283 | 8890 | vcpu->mmio_needed = 0; |
71c4dfaf JR |
8891 | r = 0; |
8892 | goto out; | |
8893 | } | |
af585b92 GN |
8894 | if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { |
8895 | /* Page is swapped out. Do synthetic halt */ | |
8896 | vcpu->arch.apf.halted = true; | |
8897 | r = 1; | |
8898 | goto out; | |
8899 | } | |
c9aaa895 GC |
8900 | if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) |
8901 | record_steal_time(vcpu); | |
64d60670 PB |
8902 | if (kvm_check_request(KVM_REQ_SMI, vcpu)) |
8903 | process_smi(vcpu); | |
7460fb4a AK |
8904 | if (kvm_check_request(KVM_REQ_NMI, vcpu)) |
8905 | process_nmi(vcpu); | |
f5132b01 | 8906 | if (kvm_check_request(KVM_REQ_PMU, vcpu)) |
c6702c9d | 8907 | kvm_pmu_handle_event(vcpu); |
f5132b01 | 8908 | if (kvm_check_request(KVM_REQ_PMI, vcpu)) |
c6702c9d | 8909 | kvm_pmu_deliver_pmi(vcpu); |
7543a635 SR |
8910 | if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { |
8911 | BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); | |
8912 | if (test_bit(vcpu->arch.pending_ioapic_eoi, | |
6308630b | 8913 | vcpu->arch.ioapic_handled_vectors)) { |
7543a635 SR |
8914 | vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; |
8915 | vcpu->run->eoi.vector = | |
8916 | vcpu->arch.pending_ioapic_eoi; | |
8917 | r = 0; | |
8918 | goto out; | |
8919 | } | |
8920 | } | |
3d81bc7e YZ |
8921 | if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) |
8922 | vcpu_scan_ioapic(vcpu); | |
e40ff1d6 LA |
8923 | if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) |
8924 | vcpu_load_eoi_exitmap(vcpu); | |
4256f43f TC |
8925 | if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) |
8926 | kvm_vcpu_reload_apic_access_page(vcpu); | |
2ce79189 AS |
8927 | if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { |
8928 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
8929 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; | |
8930 | r = 0; | |
8931 | goto out; | |
8932 | } | |
e516cebb AS |
8933 | if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { |
8934 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
8935 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; | |
8936 | r = 0; | |
8937 | goto out; | |
8938 | } | |
db397571 AS |
8939 | if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { |
8940 | vcpu->run->exit_reason = KVM_EXIT_HYPERV; | |
8941 | vcpu->run->hyperv = vcpu->arch.hyperv.exit; | |
8942 | r = 0; | |
8943 | goto out; | |
8944 | } | |
f3b138c5 AS |
8945 | |
8946 | /* | |
8947 | * KVM_REQ_HV_STIMER has to be processed after | |
8948 | * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers | |
8949 | * depend on the guest clock being up-to-date | |
8950 | */ | |
1f4b34f8 AS |
8951 | if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) |
8952 | kvm_hv_process_stimers(vcpu); | |
8df14af4 SS |
8953 | if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) |
8954 | kvm_vcpu_update_apicv(vcpu); | |
557a961a VK |
8955 | if (kvm_check_request(KVM_REQ_APF_READY, vcpu)) |
8956 | kvm_check_async_pf_completion(vcpu); | |
1a155254 AG |
8957 | if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu)) |
8958 | kvm_x86_ops.msr_filter_changed(vcpu); | |
2f52d58c | 8959 | } |
b93463aa | 8960 | |
b463a6f7 | 8961 | if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { |
0f1e261e | 8962 | ++vcpu->stat.req_event; |
66450a21 JK |
8963 | kvm_apic_accept_events(vcpu); |
8964 | if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { | |
8965 | r = 1; | |
8966 | goto out; | |
8967 | } | |
8968 | ||
c9d40913 PB |
8969 | inject_pending_event(vcpu, &req_immediate_exit); |
8970 | if (req_int_win) | |
8971 | kvm_x86_ops.enable_irq_window(vcpu); | |
b463a6f7 AK |
8972 | |
8973 | if (kvm_lapic_enabled(vcpu)) { | |
8974 | update_cr8_intercept(vcpu); | |
8975 | kvm_lapic_sync_to_vapic(vcpu); | |
8976 | } | |
8977 | } | |
8978 | ||
d8368af8 AK |
8979 | r = kvm_mmu_reload(vcpu); |
8980 | if (unlikely(r)) { | |
d905c069 | 8981 | goto cancel_injection; |
d8368af8 AK |
8982 | } |
8983 | ||
b6c7a5dc HB |
8984 | preempt_disable(); |
8985 | ||
afaf0b2f | 8986 | kvm_x86_ops.prepare_guest_switch(vcpu); |
b95234c8 PB |
8987 | |
8988 | /* | |
8989 | * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt | |
8990 | * IPI are then delayed after guest entry, which ensures that they | |
8991 | * result in virtual interrupt delivery. | |
8992 | */ | |
8993 | local_irq_disable(); | |
6b7e2d09 XG |
8994 | vcpu->mode = IN_GUEST_MODE; |
8995 | ||
01b71917 MT |
8996 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
8997 | ||
0f127d12 | 8998 | /* |
b95234c8 | 8999 | * 1) We should set ->mode before checking ->requests. Please see |
cde9af6e | 9000 | * the comment in kvm_vcpu_exiting_guest_mode(). |
b95234c8 | 9001 | * |
81b01667 | 9002 | * 2) For APICv, we should set ->mode before checking PID.ON. This |
b95234c8 PB |
9003 | * pairs with the memory barrier implicit in pi_test_and_set_on |
9004 | * (see vmx_deliver_posted_interrupt). | |
9005 | * | |
9006 | * 3) This also orders the write to mode from any reads to the page | |
9007 | * tables done while the VCPU is running. Please see the comment | |
9008 | * in kvm_flush_remote_tlbs. | |
6b7e2d09 | 9009 | */ |
01b71917 | 9010 | smp_mb__after_srcu_read_unlock(); |
b6c7a5dc | 9011 | |
b95234c8 PB |
9012 | /* |
9013 | * This handles the case where a posted interrupt was | |
9014 | * notified with kvm_vcpu_kick. | |
9015 | */ | |
fa59cc00 | 9016 | if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active) |
afaf0b2f | 9017 | kvm_x86_ops.sync_pir_to_irr(vcpu); |
32f88400 | 9018 | |
5a9f5443 | 9019 | if (kvm_vcpu_exit_request(vcpu)) { |
6b7e2d09 | 9020 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 9021 | smp_wmb(); |
6c142801 AK |
9022 | local_irq_enable(); |
9023 | preempt_enable(); | |
01b71917 | 9024 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
6c142801 | 9025 | r = 1; |
d905c069 | 9026 | goto cancel_injection; |
6c142801 AK |
9027 | } |
9028 | ||
c43203ca PB |
9029 | if (req_immediate_exit) { |
9030 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
afaf0b2f | 9031 | kvm_x86_ops.request_immediate_exit(vcpu); |
c43203ca | 9032 | } |
d6185f20 | 9033 | |
2620fe26 SC |
9034 | fpregs_assert_state_consistent(); |
9035 | if (test_thread_flag(TIF_NEED_FPU_LOAD)) | |
9036 | switch_fpu_return(); | |
5f409e20 | 9037 | |
42dbaa5a | 9038 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
9039 | set_debugreg(0, 7); |
9040 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
9041 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
9042 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
9043 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
c77fb5fe | 9044 | set_debugreg(vcpu->arch.dr6, 6); |
ae561ede | 9045 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; |
42dbaa5a | 9046 | } |
b6c7a5dc | 9047 | |
a9ab13ff | 9048 | exit_fastpath = kvm_x86_ops.run(vcpu); |
b6c7a5dc | 9049 | |
c77fb5fe PB |
9050 | /* |
9051 | * Do this here before restoring debug registers on the host. And | |
9052 | * since we do this before handling the vmexit, a DR access vmexit | |
9053 | * can (a) read the correct value of the debug registers, (b) set | |
9054 | * KVM_DEBUGREG_WONT_EXIT again. | |
9055 | */ | |
9056 | if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { | |
c77fb5fe | 9057 | WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); |
afaf0b2f | 9058 | kvm_x86_ops.sync_dirty_debug_regs(vcpu); |
70e4da7a | 9059 | kvm_update_dr0123(vcpu); |
70e4da7a PB |
9060 | kvm_update_dr7(vcpu); |
9061 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; | |
c77fb5fe PB |
9062 | } |
9063 | ||
24f1e32c FW |
9064 | /* |
9065 | * If the guest has used debug registers, at least dr7 | |
9066 | * will be disabled while returning to the host. | |
9067 | * If we don't have active breakpoints in the host, we don't | |
9068 | * care about the messed up debug address registers. But if | |
9069 | * we have some of them active, restore the old state. | |
9070 | */ | |
59d8eb53 | 9071 | if (hw_breakpoint_active()) |
24f1e32c | 9072 | hw_breakpoint_restore(); |
42dbaa5a | 9073 | |
c967118d | 9074 | vcpu->arch.last_vmentry_cpu = vcpu->cpu; |
4ba76538 | 9075 | vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); |
1d5f066e | 9076 | |
6b7e2d09 | 9077 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 9078 | smp_wmb(); |
a547c6db | 9079 | |
a9ab13ff | 9080 | kvm_x86_ops.handle_exit_irqoff(vcpu); |
b6c7a5dc | 9081 | |
d7a08882 SC |
9082 | /* |
9083 | * Consume any pending interrupts, including the possible source of | |
9084 | * VM-Exit on SVM and any ticks that occur between VM-Exit and now. | |
9085 | * An instruction is required after local_irq_enable() to fully unblock | |
9086 | * interrupts on processors that implement an interrupt shadow, the | |
9087 | * stat.exits increment will do nicely. | |
9088 | */ | |
9089 | kvm_before_interrupt(vcpu); | |
9090 | local_irq_enable(); | |
b6c7a5dc | 9091 | ++vcpu->stat.exits; |
d7a08882 SC |
9092 | local_irq_disable(); |
9093 | kvm_after_interrupt(vcpu); | |
b6c7a5dc | 9094 | |
ec0671d5 WL |
9095 | if (lapic_in_kernel(vcpu)) { |
9096 | s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta; | |
9097 | if (delta != S64_MIN) { | |
9098 | trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta); | |
9099 | vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN; | |
9100 | } | |
9101 | } | |
b6c7a5dc | 9102 | |
f2485b3e | 9103 | local_irq_enable(); |
b6c7a5dc HB |
9104 | preempt_enable(); |
9105 | ||
f656ce01 | 9106 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
3200f405 | 9107 | |
b6c7a5dc HB |
9108 | /* |
9109 | * Profile KVM exit RIPs: | |
9110 | */ | |
9111 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
9112 | unsigned long rip = kvm_rip_read(vcpu); |
9113 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
9114 | } |
9115 | ||
cc578287 ZA |
9116 | if (unlikely(vcpu->arch.tsc_always_catchup)) |
9117 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
298101da | 9118 | |
5cfb1d5a MT |
9119 | if (vcpu->arch.apic_attention) |
9120 | kvm_lapic_sync_from_vapic(vcpu); | |
b93463aa | 9121 | |
afaf0b2f | 9122 | r = kvm_x86_ops.handle_exit(vcpu, exit_fastpath); |
d905c069 MT |
9123 | return r; |
9124 | ||
9125 | cancel_injection: | |
8081ad06 SC |
9126 | if (req_immediate_exit) |
9127 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
afaf0b2f | 9128 | kvm_x86_ops.cancel_injection(vcpu); |
ae7a2a3f MT |
9129 | if (unlikely(vcpu->arch.apic_attention)) |
9130 | kvm_lapic_sync_from_vapic(vcpu); | |
d7690175 MT |
9131 | out: |
9132 | return r; | |
9133 | } | |
b6c7a5dc | 9134 | |
362c698f PB |
9135 | static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) |
9136 | { | |
bf9f6ac8 | 9137 | if (!kvm_arch_vcpu_runnable(vcpu) && |
afaf0b2f | 9138 | (!kvm_x86_ops.pre_block || kvm_x86_ops.pre_block(vcpu) == 0)) { |
9c8fd1ba PB |
9139 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
9140 | kvm_vcpu_block(vcpu); | |
9141 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); | |
bf9f6ac8 | 9142 | |
afaf0b2f SC |
9143 | if (kvm_x86_ops.post_block) |
9144 | kvm_x86_ops.post_block(vcpu); | |
bf9f6ac8 | 9145 | |
9c8fd1ba PB |
9146 | if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) |
9147 | return 1; | |
9148 | } | |
362c698f PB |
9149 | |
9150 | kvm_apic_accept_events(vcpu); | |
9151 | switch(vcpu->arch.mp_state) { | |
9152 | case KVM_MP_STATE_HALTED: | |
647daca2 | 9153 | case KVM_MP_STATE_AP_RESET_HOLD: |
362c698f PB |
9154 | vcpu->arch.pv.pv_unhalted = false; |
9155 | vcpu->arch.mp_state = | |
9156 | KVM_MP_STATE_RUNNABLE; | |
df561f66 | 9157 | fallthrough; |
362c698f PB |
9158 | case KVM_MP_STATE_RUNNABLE: |
9159 | vcpu->arch.apf.halted = false; | |
9160 | break; | |
9161 | case KVM_MP_STATE_INIT_RECEIVED: | |
9162 | break; | |
9163 | default: | |
9164 | return -EINTR; | |
362c698f PB |
9165 | } |
9166 | return 1; | |
9167 | } | |
09cec754 | 9168 | |
5d9bc648 PB |
9169 | static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) |
9170 | { | |
56083bdf | 9171 | if (is_guest_mode(vcpu)) |
33b22172 | 9172 | kvm_x86_ops.nested_ops->check_events(vcpu); |
0ad3bed6 | 9173 | |
5d9bc648 PB |
9174 | return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
9175 | !vcpu->arch.apf.halted); | |
9176 | } | |
9177 | ||
362c698f | 9178 | static int vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
9179 | { |
9180 | int r; | |
f656ce01 | 9181 | struct kvm *kvm = vcpu->kvm; |
d7690175 | 9182 | |
f656ce01 | 9183 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
c595ceee | 9184 | vcpu->arch.l1tf_flush_l1d = true; |
d7690175 | 9185 | |
362c698f | 9186 | for (;;) { |
58f800d5 | 9187 | if (kvm_vcpu_running(vcpu)) { |
851ba692 | 9188 | r = vcpu_enter_guest(vcpu); |
bf9f6ac8 | 9189 | } else { |
362c698f | 9190 | r = vcpu_block(kvm, vcpu); |
bf9f6ac8 FW |
9191 | } |
9192 | ||
09cec754 GN |
9193 | if (r <= 0) |
9194 | break; | |
9195 | ||
72875d8a | 9196 | kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu); |
09cec754 GN |
9197 | if (kvm_cpu_has_pending_timer(vcpu)) |
9198 | kvm_inject_pending_timer_irqs(vcpu); | |
9199 | ||
782d422b MG |
9200 | if (dm_request_for_irq_injection(vcpu) && |
9201 | kvm_vcpu_ready_for_interrupt_injection(vcpu)) { | |
4ca7dd8c PB |
9202 | r = 0; |
9203 | vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; | |
09cec754 | 9204 | ++vcpu->stat.request_irq_exits; |
362c698f | 9205 | break; |
09cec754 | 9206 | } |
af585b92 | 9207 | |
f3020b88 | 9208 | if (__xfer_to_guest_mode_work_pending()) { |
f656ce01 | 9209 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
72c3c0fe TG |
9210 | r = xfer_to_guest_mode_handle_work(vcpu); |
9211 | if (r) | |
9212 | return r; | |
f656ce01 | 9213 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 9214 | } |
b6c7a5dc HB |
9215 | } |
9216 | ||
f656ce01 | 9217 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
b6c7a5dc HB |
9218 | |
9219 | return r; | |
9220 | } | |
9221 | ||
716d51ab GN |
9222 | static inline int complete_emulated_io(struct kvm_vcpu *vcpu) |
9223 | { | |
9224 | int r; | |
60fc3d02 | 9225 | |
716d51ab | 9226 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
0ce97a2b | 9227 | r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); |
716d51ab | 9228 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
60fc3d02 | 9229 | return r; |
716d51ab GN |
9230 | } |
9231 | ||
9232 | static int complete_emulated_pio(struct kvm_vcpu *vcpu) | |
9233 | { | |
9234 | BUG_ON(!vcpu->arch.pio.count); | |
9235 | ||
9236 | return complete_emulated_io(vcpu); | |
9237 | } | |
9238 | ||
f78146b0 AK |
9239 | /* |
9240 | * Implements the following, as a state machine: | |
9241 | * | |
9242 | * read: | |
9243 | * for each fragment | |
87da7e66 XG |
9244 | * for each mmio piece in the fragment |
9245 | * write gpa, len | |
9246 | * exit | |
9247 | * copy data | |
f78146b0 AK |
9248 | * execute insn |
9249 | * | |
9250 | * write: | |
9251 | * for each fragment | |
87da7e66 XG |
9252 | * for each mmio piece in the fragment |
9253 | * write gpa, len | |
9254 | * copy data | |
9255 | * exit | |
f78146b0 | 9256 | */ |
716d51ab | 9257 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu) |
5287f194 AK |
9258 | { |
9259 | struct kvm_run *run = vcpu->run; | |
f78146b0 | 9260 | struct kvm_mmio_fragment *frag; |
87da7e66 | 9261 | unsigned len; |
5287f194 | 9262 | |
716d51ab | 9263 | BUG_ON(!vcpu->mmio_needed); |
5287f194 | 9264 | |
716d51ab | 9265 | /* Complete previous fragment */ |
87da7e66 XG |
9266 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; |
9267 | len = min(8u, frag->len); | |
716d51ab | 9268 | if (!vcpu->mmio_is_write) |
87da7e66 XG |
9269 | memcpy(frag->data, run->mmio.data, len); |
9270 | ||
9271 | if (frag->len <= 8) { | |
9272 | /* Switch to the next fragment. */ | |
9273 | frag++; | |
9274 | vcpu->mmio_cur_fragment++; | |
9275 | } else { | |
9276 | /* Go forward to the next mmio piece. */ | |
9277 | frag->data += len; | |
9278 | frag->gpa += len; | |
9279 | frag->len -= len; | |
9280 | } | |
9281 | ||
a08d3b3b | 9282 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { |
716d51ab | 9283 | vcpu->mmio_needed = 0; |
0912c977 PB |
9284 | |
9285 | /* FIXME: return into emulator if single-stepping. */ | |
cef4dea0 | 9286 | if (vcpu->mmio_is_write) |
716d51ab GN |
9287 | return 1; |
9288 | vcpu->mmio_read_completed = 1; | |
9289 | return complete_emulated_io(vcpu); | |
9290 | } | |
87da7e66 | 9291 | |
716d51ab GN |
9292 | run->exit_reason = KVM_EXIT_MMIO; |
9293 | run->mmio.phys_addr = frag->gpa; | |
9294 | if (vcpu->mmio_is_write) | |
87da7e66 XG |
9295 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); |
9296 | run->mmio.len = min(8u, frag->len); | |
716d51ab GN |
9297 | run->mmio.is_write = vcpu->mmio_is_write; |
9298 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; | |
9299 | return 0; | |
5287f194 AK |
9300 | } |
9301 | ||
c9aef3b8 SC |
9302 | static void kvm_save_current_fpu(struct fpu *fpu) |
9303 | { | |
9304 | /* | |
9305 | * If the target FPU state is not resident in the CPU registers, just | |
9306 | * memcpy() from current, else save CPU state directly to the target. | |
9307 | */ | |
9308 | if (test_thread_flag(TIF_NEED_FPU_LOAD)) | |
9309 | memcpy(&fpu->state, ¤t->thread.fpu.state, | |
9310 | fpu_kernel_xstate_size); | |
9311 | else | |
9312 | copy_fpregs_to_fpstate(fpu); | |
9313 | } | |
9314 | ||
822f312d SAS |
9315 | /* Swap (qemu) user FPU context for the guest FPU context. */ |
9316 | static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) | |
9317 | { | |
5f409e20 RR |
9318 | fpregs_lock(); |
9319 | ||
c9aef3b8 SC |
9320 | kvm_save_current_fpu(vcpu->arch.user_fpu); |
9321 | ||
ed02b213 TL |
9322 | /* |
9323 | * Guests with protected state can't have it set by the hypervisor, | |
9324 | * so skip trying to set it. | |
9325 | */ | |
9326 | if (vcpu->arch.guest_fpu) | |
9327 | /* PKRU is separately restored in kvm_x86_ops.run. */ | |
9328 | __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state, | |
9329 | ~XFEATURE_MASK_PKRU); | |
5f409e20 RR |
9330 | |
9331 | fpregs_mark_activate(); | |
9332 | fpregs_unlock(); | |
9333 | ||
822f312d SAS |
9334 | trace_kvm_fpu(1); |
9335 | } | |
9336 | ||
9337 | /* When vcpu_run ends, restore user space FPU context. */ | |
9338 | static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
9339 | { | |
5f409e20 RR |
9340 | fpregs_lock(); |
9341 | ||
ed02b213 TL |
9342 | /* |
9343 | * Guests with protected state can't have it read by the hypervisor, | |
9344 | * so skip trying to save it. | |
9345 | */ | |
9346 | if (vcpu->arch.guest_fpu) | |
9347 | kvm_save_current_fpu(vcpu->arch.guest_fpu); | |
c9aef3b8 | 9348 | |
d9a710e5 | 9349 | copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state); |
5f409e20 RR |
9350 | |
9351 | fpregs_mark_activate(); | |
9352 | fpregs_unlock(); | |
9353 | ||
822f312d SAS |
9354 | ++vcpu->stat.fpu_reload; |
9355 | trace_kvm_fpu(0); | |
9356 | } | |
9357 | ||
1b94f6f8 | 9358 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) |
b6c7a5dc | 9359 | { |
1b94f6f8 | 9360 | struct kvm_run *kvm_run = vcpu->run; |
b6c7a5dc | 9361 | int r; |
b6c7a5dc | 9362 | |
accb757d | 9363 | vcpu_load(vcpu); |
20b7035c | 9364 | kvm_sigset_activate(vcpu); |
15aad3be | 9365 | kvm_run->flags = 0; |
5663d8f9 PX |
9366 | kvm_load_guest_fpu(vcpu); |
9367 | ||
a4535290 | 9368 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
2f173d26 JS |
9369 | if (kvm_run->immediate_exit) { |
9370 | r = -EINTR; | |
9371 | goto out; | |
9372 | } | |
b6c7a5dc | 9373 | kvm_vcpu_block(vcpu); |
66450a21 | 9374 | kvm_apic_accept_events(vcpu); |
72875d8a | 9375 | kvm_clear_request(KVM_REQ_UNHALT, vcpu); |
ac9f6dc0 | 9376 | r = -EAGAIN; |
a0595000 JS |
9377 | if (signal_pending(current)) { |
9378 | r = -EINTR; | |
1b94f6f8 | 9379 | kvm_run->exit_reason = KVM_EXIT_INTR; |
a0595000 JS |
9380 | ++vcpu->stat.signal_exits; |
9381 | } | |
ac9f6dc0 | 9382 | goto out; |
b6c7a5dc HB |
9383 | } |
9384 | ||
1b94f6f8 | 9385 | if (kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) { |
01643c51 KH |
9386 | r = -EINVAL; |
9387 | goto out; | |
9388 | } | |
9389 | ||
1b94f6f8 | 9390 | if (kvm_run->kvm_dirty_regs) { |
01643c51 KH |
9391 | r = sync_regs(vcpu); |
9392 | if (r != 0) | |
9393 | goto out; | |
9394 | } | |
9395 | ||
b6c7a5dc | 9396 | /* re-sync apic's tpr */ |
35754c98 | 9397 | if (!lapic_in_kernel(vcpu)) { |
eea1cff9 AP |
9398 | if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { |
9399 | r = -EINVAL; | |
9400 | goto out; | |
9401 | } | |
9402 | } | |
b6c7a5dc | 9403 | |
716d51ab GN |
9404 | if (unlikely(vcpu->arch.complete_userspace_io)) { |
9405 | int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; | |
9406 | vcpu->arch.complete_userspace_io = NULL; | |
9407 | r = cui(vcpu); | |
9408 | if (r <= 0) | |
5663d8f9 | 9409 | goto out; |
716d51ab GN |
9410 | } else |
9411 | WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); | |
5287f194 | 9412 | |
460df4c1 PB |
9413 | if (kvm_run->immediate_exit) |
9414 | r = -EINTR; | |
9415 | else | |
9416 | r = vcpu_run(vcpu); | |
b6c7a5dc HB |
9417 | |
9418 | out: | |
5663d8f9 | 9419 | kvm_put_guest_fpu(vcpu); |
1b94f6f8 | 9420 | if (kvm_run->kvm_valid_regs) |
01643c51 | 9421 | store_regs(vcpu); |
f1d86e46 | 9422 | post_kvm_run_save(vcpu); |
20b7035c | 9423 | kvm_sigset_deactivate(vcpu); |
b6c7a5dc | 9424 | |
accb757d | 9425 | vcpu_put(vcpu); |
b6c7a5dc HB |
9426 | return r; |
9427 | } | |
9428 | ||
01643c51 | 9429 | static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 9430 | { |
7ae441ea GN |
9431 | if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { |
9432 | /* | |
9433 | * We are here if userspace calls get_regs() in the middle of | |
9434 | * instruction emulation. Registers state needs to be copied | |
4a969980 | 9435 | * back from emulation context to vcpu. Userspace shouldn't do |
7ae441ea GN |
9436 | * that usually, but some bad designed PV devices (vmware |
9437 | * backdoor interface) need this to work | |
9438 | */ | |
c9b8b07c | 9439 | emulator_writeback_register_cache(vcpu->arch.emulate_ctxt); |
7ae441ea GN |
9440 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
9441 | } | |
de3cd117 SC |
9442 | regs->rax = kvm_rax_read(vcpu); |
9443 | regs->rbx = kvm_rbx_read(vcpu); | |
9444 | regs->rcx = kvm_rcx_read(vcpu); | |
9445 | regs->rdx = kvm_rdx_read(vcpu); | |
9446 | regs->rsi = kvm_rsi_read(vcpu); | |
9447 | regs->rdi = kvm_rdi_read(vcpu); | |
e9c16c78 | 9448 | regs->rsp = kvm_rsp_read(vcpu); |
de3cd117 | 9449 | regs->rbp = kvm_rbp_read(vcpu); |
b6c7a5dc | 9450 | #ifdef CONFIG_X86_64 |
de3cd117 SC |
9451 | regs->r8 = kvm_r8_read(vcpu); |
9452 | regs->r9 = kvm_r9_read(vcpu); | |
9453 | regs->r10 = kvm_r10_read(vcpu); | |
9454 | regs->r11 = kvm_r11_read(vcpu); | |
9455 | regs->r12 = kvm_r12_read(vcpu); | |
9456 | regs->r13 = kvm_r13_read(vcpu); | |
9457 | regs->r14 = kvm_r14_read(vcpu); | |
9458 | regs->r15 = kvm_r15_read(vcpu); | |
b6c7a5dc HB |
9459 | #endif |
9460 | ||
5fdbf976 | 9461 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 9462 | regs->rflags = kvm_get_rflags(vcpu); |
01643c51 | 9463 | } |
b6c7a5dc | 9464 | |
01643c51 KH |
9465 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
9466 | { | |
9467 | vcpu_load(vcpu); | |
9468 | __get_regs(vcpu, regs); | |
1fc9b76b | 9469 | vcpu_put(vcpu); |
b6c7a5dc HB |
9470 | return 0; |
9471 | } | |
9472 | ||
01643c51 | 9473 | static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 9474 | { |
7ae441ea GN |
9475 | vcpu->arch.emulate_regs_need_sync_from_vcpu = true; |
9476 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; | |
9477 | ||
de3cd117 SC |
9478 | kvm_rax_write(vcpu, regs->rax); |
9479 | kvm_rbx_write(vcpu, regs->rbx); | |
9480 | kvm_rcx_write(vcpu, regs->rcx); | |
9481 | kvm_rdx_write(vcpu, regs->rdx); | |
9482 | kvm_rsi_write(vcpu, regs->rsi); | |
9483 | kvm_rdi_write(vcpu, regs->rdi); | |
e9c16c78 | 9484 | kvm_rsp_write(vcpu, regs->rsp); |
de3cd117 | 9485 | kvm_rbp_write(vcpu, regs->rbp); |
b6c7a5dc | 9486 | #ifdef CONFIG_X86_64 |
de3cd117 SC |
9487 | kvm_r8_write(vcpu, regs->r8); |
9488 | kvm_r9_write(vcpu, regs->r9); | |
9489 | kvm_r10_write(vcpu, regs->r10); | |
9490 | kvm_r11_write(vcpu, regs->r11); | |
9491 | kvm_r12_write(vcpu, regs->r12); | |
9492 | kvm_r13_write(vcpu, regs->r13); | |
9493 | kvm_r14_write(vcpu, regs->r14); | |
9494 | kvm_r15_write(vcpu, regs->r15); | |
b6c7a5dc HB |
9495 | #endif |
9496 | ||
5fdbf976 | 9497 | kvm_rip_write(vcpu, regs->rip); |
d73235d1 | 9498 | kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); |
b6c7a5dc | 9499 | |
b4f14abd JK |
9500 | vcpu->arch.exception.pending = false; |
9501 | ||
3842d135 | 9502 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
01643c51 | 9503 | } |
3842d135 | 9504 | |
01643c51 KH |
9505 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
9506 | { | |
9507 | vcpu_load(vcpu); | |
9508 | __set_regs(vcpu, regs); | |
875656fe | 9509 | vcpu_put(vcpu); |
b6c7a5dc HB |
9510 | return 0; |
9511 | } | |
9512 | ||
b6c7a5dc HB |
9513 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
9514 | { | |
9515 | struct kvm_segment cs; | |
9516 | ||
3e6e0aab | 9517 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
9518 | *db = cs.db; |
9519 | *l = cs.l; | |
9520 | } | |
9521 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
9522 | ||
01643c51 | 9523 | static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
b6c7a5dc | 9524 | { |
89a27f4d | 9525 | struct desc_ptr dt; |
b6c7a5dc | 9526 | |
5265713a TL |
9527 | if (vcpu->arch.guest_state_protected) |
9528 | goto skip_protected_regs; | |
9529 | ||
3e6e0aab GT |
9530 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
9531 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
9532 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
9533 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
9534 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
9535 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 9536 | |
3e6e0aab GT |
9537 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
9538 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 9539 | |
afaf0b2f | 9540 | kvm_x86_ops.get_idt(vcpu, &dt); |
89a27f4d GN |
9541 | sregs->idt.limit = dt.size; |
9542 | sregs->idt.base = dt.address; | |
afaf0b2f | 9543 | kvm_x86_ops.get_gdt(vcpu, &dt); |
89a27f4d GN |
9544 | sregs->gdt.limit = dt.size; |
9545 | sregs->gdt.base = dt.address; | |
b6c7a5dc | 9546 | |
ad312c7c | 9547 | sregs->cr2 = vcpu->arch.cr2; |
9f8fe504 | 9548 | sregs->cr3 = kvm_read_cr3(vcpu); |
5265713a TL |
9549 | |
9550 | skip_protected_regs: | |
9551 | sregs->cr0 = kvm_read_cr0(vcpu); | |
fc78f519 | 9552 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 9553 | sregs->cr8 = kvm_get_cr8(vcpu); |
f6801dff | 9554 | sregs->efer = vcpu->arch.efer; |
b6c7a5dc HB |
9555 | sregs->apic_base = kvm_get_apic_base(vcpu); |
9556 | ||
0e96f31e | 9557 | memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap)); |
b6c7a5dc | 9558 | |
04140b41 | 9559 | if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
9560 | set_bit(vcpu->arch.interrupt.nr, |
9561 | (unsigned long *)sregs->interrupt_bitmap); | |
01643c51 | 9562 | } |
16d7a191 | 9563 | |
01643c51 KH |
9564 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, |
9565 | struct kvm_sregs *sregs) | |
9566 | { | |
9567 | vcpu_load(vcpu); | |
9568 | __get_sregs(vcpu, sregs); | |
bcdec41c | 9569 | vcpu_put(vcpu); |
b6c7a5dc HB |
9570 | return 0; |
9571 | } | |
9572 | ||
62d9f0db MT |
9573 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
9574 | struct kvm_mp_state *mp_state) | |
9575 | { | |
fd232561 | 9576 | vcpu_load(vcpu); |
f958bd23 SC |
9577 | if (kvm_mpx_supported()) |
9578 | kvm_load_guest_fpu(vcpu); | |
fd232561 | 9579 | |
66450a21 | 9580 | kvm_apic_accept_events(vcpu); |
647daca2 TL |
9581 | if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED || |
9582 | vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) && | |
9583 | vcpu->arch.pv.pv_unhalted) | |
6aef266c SV |
9584 | mp_state->mp_state = KVM_MP_STATE_RUNNABLE; |
9585 | else | |
9586 | mp_state->mp_state = vcpu->arch.mp_state; | |
9587 | ||
f958bd23 SC |
9588 | if (kvm_mpx_supported()) |
9589 | kvm_put_guest_fpu(vcpu); | |
fd232561 | 9590 | vcpu_put(vcpu); |
62d9f0db MT |
9591 | return 0; |
9592 | } | |
9593 | ||
9594 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
9595 | struct kvm_mp_state *mp_state) | |
9596 | { | |
e83dff5e CD |
9597 | int ret = -EINVAL; |
9598 | ||
9599 | vcpu_load(vcpu); | |
9600 | ||
bce87cce | 9601 | if (!lapic_in_kernel(vcpu) && |
66450a21 | 9602 | mp_state->mp_state != KVM_MP_STATE_RUNNABLE) |
e83dff5e | 9603 | goto out; |
66450a21 | 9604 | |
27cbe7d6 LA |
9605 | /* |
9606 | * KVM_MP_STATE_INIT_RECEIVED means the processor is in | |
9607 | * INIT state; latched init should be reported using | |
9608 | * KVM_SET_VCPU_EVENTS, so reject it here. | |
9609 | */ | |
9610 | if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) && | |
28bf2888 DH |
9611 | (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || |
9612 | mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) | |
e83dff5e | 9613 | goto out; |
28bf2888 | 9614 | |
66450a21 JK |
9615 | if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { |
9616 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
9617 | set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); | |
9618 | } else | |
9619 | vcpu->arch.mp_state = mp_state->mp_state; | |
3842d135 | 9620 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
e83dff5e CD |
9621 | |
9622 | ret = 0; | |
9623 | out: | |
9624 | vcpu_put(vcpu); | |
9625 | return ret; | |
62d9f0db MT |
9626 | } |
9627 | ||
7f3d35fd KW |
9628 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
9629 | int reason, bool has_error_code, u32 error_code) | |
b6c7a5dc | 9630 | { |
c9b8b07c | 9631 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
8ec4722d | 9632 | int ret; |
e01c2426 | 9633 | |
8ec4722d | 9634 | init_emulate_ctxt(vcpu); |
c697518a | 9635 | |
7f3d35fd | 9636 | ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, |
9d74191a | 9637 | has_error_code, error_code); |
1051778f SC |
9638 | if (ret) { |
9639 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
9640 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
9641 | vcpu->run->internal.ndata = 0; | |
60fc3d02 | 9642 | return 0; |
1051778f | 9643 | } |
37817f29 | 9644 | |
9d74191a TY |
9645 | kvm_rip_write(vcpu, ctxt->eip); |
9646 | kvm_set_rflags(vcpu, ctxt->eflags); | |
60fc3d02 | 9647 | return 1; |
37817f29 IE |
9648 | } |
9649 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
9650 | ||
ee69c92b | 9651 | static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
f2981033 | 9652 | { |
37b95951 | 9653 | if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { |
f2981033 LT |
9654 | /* |
9655 | * When EFER.LME and CR0.PG are set, the processor is in | |
9656 | * 64-bit mode (though maybe in a 32-bit code segment). | |
9657 | * CR4.PAE and EFER.LMA must be set. | |
9658 | */ | |
ee69c92b SC |
9659 | if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA)) |
9660 | return false; | |
c1c35cf7 PB |
9661 | if (sregs->cr3 & vcpu->arch.cr3_lm_rsvd_bits) |
9662 | return false; | |
f2981033 LT |
9663 | } else { |
9664 | /* | |
9665 | * Not in 64-bit mode: EFER.LMA is clear and the code | |
9666 | * segment cannot be 64-bit. | |
9667 | */ | |
9668 | if (sregs->efer & EFER_LMA || sregs->cs.l) | |
ee69c92b | 9669 | return false; |
f2981033 LT |
9670 | } |
9671 | ||
ee69c92b | 9672 | return kvm_is_valid_cr4(vcpu, sregs->cr4); |
f2981033 LT |
9673 | } |
9674 | ||
01643c51 | 9675 | static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
b6c7a5dc | 9676 | { |
58cb628d | 9677 | struct msr_data apic_base_msr; |
b6c7a5dc | 9678 | int mmu_reset_needed = 0; |
63f42e02 | 9679 | int pending_vec, max_bits, idx; |
89a27f4d | 9680 | struct desc_ptr dt; |
b4ef9d4e CD |
9681 | int ret = -EINVAL; |
9682 | ||
ee69c92b | 9683 | if (!kvm_is_valid_sregs(vcpu, sregs)) |
8dbfb2bf | 9684 | goto out; |
f2981033 | 9685 | |
d3802286 JM |
9686 | apic_base_msr.data = sregs->apic_base; |
9687 | apic_base_msr.host_initiated = true; | |
9688 | if (kvm_set_apic_base(vcpu, &apic_base_msr)) | |
b4ef9d4e | 9689 | goto out; |
6d1068b3 | 9690 | |
5265713a TL |
9691 | if (vcpu->arch.guest_state_protected) |
9692 | goto skip_protected_regs; | |
9693 | ||
89a27f4d GN |
9694 | dt.size = sregs->idt.limit; |
9695 | dt.address = sregs->idt.base; | |
afaf0b2f | 9696 | kvm_x86_ops.set_idt(vcpu, &dt); |
89a27f4d GN |
9697 | dt.size = sregs->gdt.limit; |
9698 | dt.address = sregs->gdt.base; | |
afaf0b2f | 9699 | kvm_x86_ops.set_gdt(vcpu, &dt); |
b6c7a5dc | 9700 | |
ad312c7c | 9701 | vcpu->arch.cr2 = sregs->cr2; |
9f8fe504 | 9702 | mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; |
dc7e795e | 9703 | vcpu->arch.cr3 = sregs->cr3; |
cb3c1e2f | 9704 | kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); |
b6c7a5dc | 9705 | |
2d3ad1f4 | 9706 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 9707 | |
f6801dff | 9708 | mmu_reset_needed |= vcpu->arch.efer != sregs->efer; |
afaf0b2f | 9709 | kvm_x86_ops.set_efer(vcpu, sregs->efer); |
b6c7a5dc | 9710 | |
4d4ec087 | 9711 | mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
afaf0b2f | 9712 | kvm_x86_ops.set_cr0(vcpu, sregs->cr0); |
d7306163 | 9713 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 9714 | |
fc78f519 | 9715 | mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
afaf0b2f | 9716 | kvm_x86_ops.set_cr4(vcpu, sregs->cr4); |
63f42e02 XG |
9717 | |
9718 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
bf03d4f9 | 9719 | if (is_pae_paging(vcpu)) { |
9f8fe504 | 9720 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
7c93be44 MT |
9721 | mmu_reset_needed = 1; |
9722 | } | |
63f42e02 | 9723 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b6c7a5dc HB |
9724 | |
9725 | if (mmu_reset_needed) | |
9726 | kvm_mmu_reset_context(vcpu); | |
9727 | ||
3e6e0aab GT |
9728 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
9729 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
9730 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
9731 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
9732 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
9733 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 9734 | |
3e6e0aab GT |
9735 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
9736 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 9737 | |
5f0269f5 ME |
9738 | update_cr8_intercept(vcpu); |
9739 | ||
9c3e4aab | 9740 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 9741 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 9742 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
3eeb3288 | 9743 | !is_protmode(vcpu)) |
9c3e4aab MT |
9744 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
9745 | ||
5265713a TL |
9746 | skip_protected_regs: |
9747 | max_bits = KVM_NR_INTERRUPTS; | |
9748 | pending_vec = find_first_bit( | |
9749 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
9750 | if (pending_vec < max_bits) { | |
9751 | kvm_queue_interrupt(vcpu, pending_vec, false); | |
9752 | pr_debug("Set back pending irq %d\n", pending_vec); | |
9753 | } | |
9754 | ||
3842d135 AK |
9755 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
9756 | ||
b4ef9d4e CD |
9757 | ret = 0; |
9758 | out: | |
01643c51 KH |
9759 | return ret; |
9760 | } | |
9761 | ||
9762 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, | |
9763 | struct kvm_sregs *sregs) | |
9764 | { | |
9765 | int ret; | |
9766 | ||
9767 | vcpu_load(vcpu); | |
9768 | ret = __set_sregs(vcpu, sregs); | |
b4ef9d4e CD |
9769 | vcpu_put(vcpu); |
9770 | return ret; | |
b6c7a5dc HB |
9771 | } |
9772 | ||
d0bfb940 JK |
9773 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
9774 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 9775 | { |
355be0b9 | 9776 | unsigned long rflags; |
ae675ef0 | 9777 | int i, r; |
b6c7a5dc | 9778 | |
8d4846b9 TL |
9779 | if (vcpu->arch.guest_state_protected) |
9780 | return -EINVAL; | |
9781 | ||
66b56562 CD |
9782 | vcpu_load(vcpu); |
9783 | ||
4f926bf2 JK |
9784 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
9785 | r = -EBUSY; | |
9786 | if (vcpu->arch.exception.pending) | |
2122ff5e | 9787 | goto out; |
4f926bf2 JK |
9788 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
9789 | kvm_queue_exception(vcpu, DB_VECTOR); | |
9790 | else | |
9791 | kvm_queue_exception(vcpu, BP_VECTOR); | |
9792 | } | |
9793 | ||
91586a3b JK |
9794 | /* |
9795 | * Read rflags as long as potentially injected trace flags are still | |
9796 | * filtered out. | |
9797 | */ | |
9798 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
9799 | |
9800 | vcpu->guest_debug = dbg->control; | |
9801 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
9802 | vcpu->guest_debug = 0; | |
9803 | ||
9804 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
9805 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
9806 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
c8639010 | 9807 | vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; |
ae675ef0 JK |
9808 | } else { |
9809 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
9810 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
ae675ef0 | 9811 | } |
c8639010 | 9812 | kvm_update_dr7(vcpu); |
ae675ef0 | 9813 | |
f92653ee JK |
9814 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
9815 | vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + | |
9816 | get_segment_base(vcpu, VCPU_SREG_CS); | |
94fe45da | 9817 | |
91586a3b JK |
9818 | /* |
9819 | * Trigger an rflags update that will inject or remove the trace | |
9820 | * flags. | |
9821 | */ | |
9822 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 9823 | |
6986982f | 9824 | kvm_x86_ops.update_exception_bitmap(vcpu); |
b6c7a5dc | 9825 | |
4f926bf2 | 9826 | r = 0; |
d0bfb940 | 9827 | |
2122ff5e | 9828 | out: |
66b56562 | 9829 | vcpu_put(vcpu); |
b6c7a5dc HB |
9830 | return r; |
9831 | } | |
9832 | ||
8b006791 ZX |
9833 | /* |
9834 | * Translate a guest virtual address to a guest physical address. | |
9835 | */ | |
9836 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
9837 | struct kvm_translation *tr) | |
9838 | { | |
9839 | unsigned long vaddr = tr->linear_address; | |
9840 | gpa_t gpa; | |
f656ce01 | 9841 | int idx; |
8b006791 | 9842 | |
1da5b61d CD |
9843 | vcpu_load(vcpu); |
9844 | ||
f656ce01 | 9845 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1871c602 | 9846 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); |
f656ce01 | 9847 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 ZX |
9848 | tr->physical_address = gpa; |
9849 | tr->valid = gpa != UNMAPPED_GVA; | |
9850 | tr->writeable = 1; | |
9851 | tr->usermode = 0; | |
8b006791 | 9852 | |
1da5b61d | 9853 | vcpu_put(vcpu); |
8b006791 ZX |
9854 | return 0; |
9855 | } | |
9856 | ||
d0752060 HB |
9857 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
9858 | { | |
1393123e | 9859 | struct fxregs_state *fxsave; |
d0752060 | 9860 | |
ed02b213 TL |
9861 | if (!vcpu->arch.guest_fpu) |
9862 | return 0; | |
9863 | ||
1393123e | 9864 | vcpu_load(vcpu); |
d0752060 | 9865 | |
b666a4b6 | 9866 | fxsave = &vcpu->arch.guest_fpu->state.fxsave; |
d0752060 HB |
9867 | memcpy(fpu->fpr, fxsave->st_space, 128); |
9868 | fpu->fcw = fxsave->cwd; | |
9869 | fpu->fsw = fxsave->swd; | |
9870 | fpu->ftwx = fxsave->twd; | |
9871 | fpu->last_opcode = fxsave->fop; | |
9872 | fpu->last_ip = fxsave->rip; | |
9873 | fpu->last_dp = fxsave->rdp; | |
0e96f31e | 9874 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); |
d0752060 | 9875 | |
1393123e | 9876 | vcpu_put(vcpu); |
d0752060 HB |
9877 | return 0; |
9878 | } | |
9879 | ||
9880 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
9881 | { | |
6a96bc7f CD |
9882 | struct fxregs_state *fxsave; |
9883 | ||
ed02b213 TL |
9884 | if (!vcpu->arch.guest_fpu) |
9885 | return 0; | |
9886 | ||
6a96bc7f CD |
9887 | vcpu_load(vcpu); |
9888 | ||
b666a4b6 | 9889 | fxsave = &vcpu->arch.guest_fpu->state.fxsave; |
d0752060 | 9890 | |
d0752060 HB |
9891 | memcpy(fxsave->st_space, fpu->fpr, 128); |
9892 | fxsave->cwd = fpu->fcw; | |
9893 | fxsave->swd = fpu->fsw; | |
9894 | fxsave->twd = fpu->ftwx; | |
9895 | fxsave->fop = fpu->last_opcode; | |
9896 | fxsave->rip = fpu->last_ip; | |
9897 | fxsave->rdp = fpu->last_dp; | |
0e96f31e | 9898 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); |
d0752060 | 9899 | |
6a96bc7f | 9900 | vcpu_put(vcpu); |
d0752060 HB |
9901 | return 0; |
9902 | } | |
9903 | ||
01643c51 KH |
9904 | static void store_regs(struct kvm_vcpu *vcpu) |
9905 | { | |
9906 | BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); | |
9907 | ||
9908 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) | |
9909 | __get_regs(vcpu, &vcpu->run->s.regs.regs); | |
9910 | ||
9911 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) | |
9912 | __get_sregs(vcpu, &vcpu->run->s.regs.sregs); | |
9913 | ||
9914 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) | |
9915 | kvm_vcpu_ioctl_x86_get_vcpu_events( | |
9916 | vcpu, &vcpu->run->s.regs.events); | |
9917 | } | |
9918 | ||
9919 | static int sync_regs(struct kvm_vcpu *vcpu) | |
9920 | { | |
9921 | if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS) | |
9922 | return -EINVAL; | |
9923 | ||
9924 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { | |
9925 | __set_regs(vcpu, &vcpu->run->s.regs.regs); | |
9926 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; | |
9927 | } | |
9928 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { | |
9929 | if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) | |
9930 | return -EINVAL; | |
9931 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; | |
9932 | } | |
9933 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { | |
9934 | if (kvm_vcpu_ioctl_x86_set_vcpu_events( | |
9935 | vcpu, &vcpu->run->s.regs.events)) | |
9936 | return -EINVAL; | |
9937 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; | |
9938 | } | |
9939 | ||
9940 | return 0; | |
9941 | } | |
9942 | ||
0ee6a517 | 9943 | static void fx_init(struct kvm_vcpu *vcpu) |
d0752060 | 9944 | { |
ed02b213 TL |
9945 | if (!vcpu->arch.guest_fpu) |
9946 | return; | |
9947 | ||
b666a4b6 | 9948 | fpstate_init(&vcpu->arch.guest_fpu->state); |
782511b0 | 9949 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
b666a4b6 | 9950 | vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv = |
df1daba7 | 9951 | host_xcr0 | XSTATE_COMPACTION_ENABLED; |
d0752060 | 9952 | |
2acf923e DC |
9953 | /* |
9954 | * Ensure guest xcr0 is valid for loading | |
9955 | */ | |
d91cab78 | 9956 | vcpu->arch.xcr0 = XFEATURE_MASK_FP; |
2acf923e | 9957 | |
ad312c7c | 9958 | vcpu->arch.cr0 |= X86_CR0_ET; |
d0752060 | 9959 | } |
d0752060 | 9960 | |
ed02b213 TL |
9961 | void kvm_free_guest_fpu(struct kvm_vcpu *vcpu) |
9962 | { | |
9963 | if (vcpu->arch.guest_fpu) { | |
9964 | kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu); | |
9965 | vcpu->arch.guest_fpu = NULL; | |
9966 | } | |
9967 | } | |
9968 | EXPORT_SYMBOL_GPL(kvm_free_guest_fpu); | |
9969 | ||
897cc38e | 9970 | int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) |
e9b11c17 | 9971 | { |
897cc38e SC |
9972 | if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) |
9973 | pr_warn_once("kvm: SMP vm created on host with unstable TSC; " | |
9974 | "guest TSC will not be reliable\n"); | |
7f1ea208 | 9975 | |
897cc38e | 9976 | return 0; |
e9b11c17 ZX |
9977 | } |
9978 | ||
e529ef66 | 9979 | int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) |
e9b11c17 | 9980 | { |
95a0d01e SC |
9981 | struct page *page; |
9982 | int r; | |
c447e76b | 9983 | |
95a0d01e SC |
9984 | if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) |
9985 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
9986 | else | |
9987 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; | |
c447e76b | 9988 | |
95a0d01e | 9989 | kvm_set_tsc_khz(vcpu, max_tsc_khz); |
c447e76b | 9990 | |
95a0d01e SC |
9991 | r = kvm_mmu_create(vcpu); |
9992 | if (r < 0) | |
9993 | return r; | |
9994 | ||
9995 | if (irqchip_in_kernel(vcpu->kvm)) { | |
95a0d01e SC |
9996 | r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); |
9997 | if (r < 0) | |
9998 | goto fail_mmu_destroy; | |
4e19c36f SS |
9999 | if (kvm_apicv_activated(vcpu->kvm)) |
10000 | vcpu->arch.apicv_active = true; | |
95a0d01e | 10001 | } else |
6e4e3b4d | 10002 | static_branch_inc(&kvm_has_noapic_vcpu); |
95a0d01e SC |
10003 | |
10004 | r = -ENOMEM; | |
10005 | ||
93bb59ca | 10006 | page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); |
95a0d01e SC |
10007 | if (!page) |
10008 | goto fail_free_lapic; | |
10009 | vcpu->arch.pio_data = page_address(page); | |
10010 | ||
10011 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, | |
10012 | GFP_KERNEL_ACCOUNT); | |
10013 | if (!vcpu->arch.mce_banks) | |
10014 | goto fail_free_pio_data; | |
10015 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
10016 | ||
10017 | if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, | |
10018 | GFP_KERNEL_ACCOUNT)) | |
10019 | goto fail_free_mce_banks; | |
10020 | ||
c9b8b07c SC |
10021 | if (!alloc_emulate_ctxt(vcpu)) |
10022 | goto free_wbinvd_dirty_mask; | |
10023 | ||
95a0d01e SC |
10024 | vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache, |
10025 | GFP_KERNEL_ACCOUNT); | |
10026 | if (!vcpu->arch.user_fpu) { | |
10027 | pr_err("kvm: failed to allocate userspace's fpu\n"); | |
c9b8b07c | 10028 | goto free_emulate_ctxt; |
95a0d01e SC |
10029 | } |
10030 | ||
10031 | vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, | |
10032 | GFP_KERNEL_ACCOUNT); | |
10033 | if (!vcpu->arch.guest_fpu) { | |
10034 | pr_err("kvm: failed to allocate vcpu's fpu\n"); | |
10035 | goto free_user_fpu; | |
10036 | } | |
10037 | fx_init(vcpu); | |
10038 | ||
95a0d01e SC |
10039 | vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); |
10040 | ||
10041 | vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; | |
10042 | ||
10043 | kvm_async_pf_hash_reset(vcpu); | |
10044 | kvm_pmu_init(vcpu); | |
10045 | ||
10046 | vcpu->arch.pending_external_vector = -1; | |
10047 | vcpu->arch.preempted_in_kernel = false; | |
10048 | ||
10049 | kvm_hv_vcpu_init(vcpu); | |
10050 | ||
afaf0b2f | 10051 | r = kvm_x86_ops.vcpu_create(vcpu); |
95a0d01e SC |
10052 | if (r) |
10053 | goto free_guest_fpu; | |
e9b11c17 | 10054 | |
0cf9135b | 10055 | vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); |
e53d88af | 10056 | vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; |
19efffa2 | 10057 | kvm_vcpu_mtrr_init(vcpu); |
ec7660cc | 10058 | vcpu_load(vcpu); |
d28bc9dd | 10059 | kvm_vcpu_reset(vcpu, false); |
e1732991 | 10060 | kvm_init_mmu(vcpu, false); |
e9b11c17 | 10061 | vcpu_put(vcpu); |
ec7660cc | 10062 | return 0; |
95a0d01e SC |
10063 | |
10064 | free_guest_fpu: | |
ed02b213 | 10065 | kvm_free_guest_fpu(vcpu); |
95a0d01e SC |
10066 | free_user_fpu: |
10067 | kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); | |
c9b8b07c SC |
10068 | free_emulate_ctxt: |
10069 | kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); | |
95a0d01e SC |
10070 | free_wbinvd_dirty_mask: |
10071 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); | |
10072 | fail_free_mce_banks: | |
10073 | kfree(vcpu->arch.mce_banks); | |
10074 | fail_free_pio_data: | |
10075 | free_page((unsigned long)vcpu->arch.pio_data); | |
10076 | fail_free_lapic: | |
10077 | kvm_free_lapic(vcpu); | |
10078 | fail_mmu_destroy: | |
10079 | kvm_mmu_destroy(vcpu); | |
10080 | return r; | |
e9b11c17 ZX |
10081 | } |
10082 | ||
31928aa5 | 10083 | void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) |
42897d86 | 10084 | { |
332967a3 | 10085 | struct kvm *kvm = vcpu->kvm; |
42897d86 | 10086 | |
d3457c87 RK |
10087 | kvm_hv_vcpu_postcreate(vcpu); |
10088 | ||
ec7660cc | 10089 | if (mutex_lock_killable(&vcpu->mutex)) |
31928aa5 | 10090 | return; |
ec7660cc | 10091 | vcpu_load(vcpu); |
0c899c25 | 10092 | kvm_synchronize_tsc(vcpu, 0); |
42897d86 | 10093 | vcpu_put(vcpu); |
2d5ba19b MT |
10094 | |
10095 | /* poll control enabled by default */ | |
10096 | vcpu->arch.msr_kvm_poll_control = 1; | |
10097 | ||
ec7660cc | 10098 | mutex_unlock(&vcpu->mutex); |
42897d86 | 10099 | |
b34de572 WL |
10100 | if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0) |
10101 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
10102 | KVMCLOCK_SYNC_PERIOD); | |
42897d86 MT |
10103 | } |
10104 | ||
d40ccc62 | 10105 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 | 10106 | { |
4cbc418a | 10107 | struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache; |
95a0d01e | 10108 | int idx; |
344d9588 | 10109 | |
4cbc418a PB |
10110 | kvm_release_pfn(cache->pfn, cache->dirty, cache); |
10111 | ||
50b143e1 | 10112 | kvmclock_reset(vcpu); |
e9b11c17 | 10113 | |
afaf0b2f | 10114 | kvm_x86_ops.vcpu_free(vcpu); |
50b143e1 | 10115 | |
c9b8b07c | 10116 | kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); |
50b143e1 SC |
10117 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); |
10118 | kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); | |
ed02b213 | 10119 | kvm_free_guest_fpu(vcpu); |
95a0d01e SC |
10120 | |
10121 | kvm_hv_vcpu_uninit(vcpu); | |
10122 | kvm_pmu_destroy(vcpu); | |
10123 | kfree(vcpu->arch.mce_banks); | |
10124 | kvm_free_lapic(vcpu); | |
10125 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
10126 | kvm_mmu_destroy(vcpu); | |
10127 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
10128 | free_page((unsigned long)vcpu->arch.pio_data); | |
255cbecf | 10129 | kvfree(vcpu->arch.cpuid_entries); |
95a0d01e | 10130 | if (!lapic_in_kernel(vcpu)) |
6e4e3b4d | 10131 | static_branch_dec(&kvm_has_noapic_vcpu); |
e9b11c17 ZX |
10132 | } |
10133 | ||
d28bc9dd | 10134 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
e9b11c17 | 10135 | { |
b7e31be3 RK |
10136 | kvm_lapic_reset(vcpu, init_event); |
10137 | ||
e69fab5d PB |
10138 | vcpu->arch.hflags = 0; |
10139 | ||
c43203ca | 10140 | vcpu->arch.smi_pending = 0; |
52797bf9 | 10141 | vcpu->arch.smi_count = 0; |
7460fb4a AK |
10142 | atomic_set(&vcpu->arch.nmi_queued, 0); |
10143 | vcpu->arch.nmi_pending = 0; | |
448fa4a9 | 10144 | vcpu->arch.nmi_injected = false; |
5f7552d4 NA |
10145 | kvm_clear_interrupt_queue(vcpu); |
10146 | kvm_clear_exception_queue(vcpu); | |
448fa4a9 | 10147 | |
42dbaa5a | 10148 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); |
ae561ede | 10149 | kvm_update_dr0123(vcpu); |
9a3ecd5e | 10150 | vcpu->arch.dr6 = DR6_ACTIVE_LOW; |
42dbaa5a | 10151 | vcpu->arch.dr7 = DR7_FIXED_1; |
c8639010 | 10152 | kvm_update_dr7(vcpu); |
42dbaa5a | 10153 | |
1119022c NA |
10154 | vcpu->arch.cr2 = 0; |
10155 | ||
3842d135 | 10156 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
2635b5c4 VK |
10157 | vcpu->arch.apf.msr_en_val = 0; |
10158 | vcpu->arch.apf.msr_int_val = 0; | |
c9aaa895 | 10159 | vcpu->arch.st.msr_val = 0; |
3842d135 | 10160 | |
12f9a48f GC |
10161 | kvmclock_reset(vcpu); |
10162 | ||
af585b92 GN |
10163 | kvm_clear_async_pf_completion_queue(vcpu); |
10164 | kvm_async_pf_hash_reset(vcpu); | |
10165 | vcpu->arch.apf.halted = false; | |
3842d135 | 10166 | |
ed02b213 | 10167 | if (vcpu->arch.guest_fpu && kvm_mpx_supported()) { |
a554d207 WL |
10168 | void *mpx_state_buffer; |
10169 | ||
10170 | /* | |
10171 | * To avoid have the INIT path from kvm_apic_has_events() that be | |
10172 | * called with loaded FPU and does not let userspace fix the state. | |
10173 | */ | |
f775b13e RR |
10174 | if (init_event) |
10175 | kvm_put_guest_fpu(vcpu); | |
b666a4b6 | 10176 | mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, |
abd16d68 | 10177 | XFEATURE_BNDREGS); |
a554d207 WL |
10178 | if (mpx_state_buffer) |
10179 | memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state)); | |
b666a4b6 | 10180 | mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, |
abd16d68 | 10181 | XFEATURE_BNDCSR); |
a554d207 WL |
10182 | if (mpx_state_buffer) |
10183 | memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr)); | |
f775b13e RR |
10184 | if (init_event) |
10185 | kvm_load_guest_fpu(vcpu); | |
a554d207 WL |
10186 | } |
10187 | ||
64d60670 | 10188 | if (!init_event) { |
d28bc9dd | 10189 | kvm_pmu_reset(vcpu); |
64d60670 | 10190 | vcpu->arch.smbase = 0x30000; |
db2336a8 | 10191 | |
db2336a8 | 10192 | vcpu->arch.msr_misc_features_enables = 0; |
a554d207 WL |
10193 | |
10194 | vcpu->arch.xcr0 = XFEATURE_MASK_FP; | |
64d60670 | 10195 | } |
f5132b01 | 10196 | |
66f7b72e JS |
10197 | memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); |
10198 | vcpu->arch.regs_avail = ~0; | |
10199 | vcpu->arch.regs_dirty = ~0; | |
10200 | ||
a554d207 WL |
10201 | vcpu->arch.ia32_xss = 0; |
10202 | ||
afaf0b2f | 10203 | kvm_x86_ops.vcpu_reset(vcpu, init_event); |
e9b11c17 ZX |
10204 | } |
10205 | ||
2b4a273b | 10206 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) |
66450a21 JK |
10207 | { |
10208 | struct kvm_segment cs; | |
10209 | ||
10210 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
10211 | cs.selector = vector << 8; | |
10212 | cs.base = vector << 12; | |
10213 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
10214 | kvm_rip_write(vcpu, 0); | |
e9b11c17 | 10215 | } |
647daca2 | 10216 | EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector); |
e9b11c17 | 10217 | |
13a34e06 | 10218 | int kvm_arch_hardware_enable(void) |
e9b11c17 | 10219 | { |
ca84d1a2 ZA |
10220 | struct kvm *kvm; |
10221 | struct kvm_vcpu *vcpu; | |
10222 | int i; | |
0dd6a6ed ZA |
10223 | int ret; |
10224 | u64 local_tsc; | |
10225 | u64 max_tsc = 0; | |
10226 | bool stable, backwards_tsc = false; | |
18863bdd | 10227 | |
7e34fbd0 | 10228 | kvm_user_return_msr_cpu_online(); |
afaf0b2f | 10229 | ret = kvm_x86_ops.hardware_enable(); |
0dd6a6ed ZA |
10230 | if (ret != 0) |
10231 | return ret; | |
10232 | ||
4ea1636b | 10233 | local_tsc = rdtsc(); |
b0c39dc6 | 10234 | stable = !kvm_check_tsc_unstable(); |
0dd6a6ed ZA |
10235 | list_for_each_entry(kvm, &vm_list, vm_list) { |
10236 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
10237 | if (!stable && vcpu->cpu == smp_processor_id()) | |
105b21bb | 10238 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
10239 | if (stable && vcpu->arch.last_host_tsc > local_tsc) { |
10240 | backwards_tsc = true; | |
10241 | if (vcpu->arch.last_host_tsc > max_tsc) | |
10242 | max_tsc = vcpu->arch.last_host_tsc; | |
10243 | } | |
10244 | } | |
10245 | } | |
10246 | ||
10247 | /* | |
10248 | * Sometimes, even reliable TSCs go backwards. This happens on | |
10249 | * platforms that reset TSC during suspend or hibernate actions, but | |
10250 | * maintain synchronization. We must compensate. Fortunately, we can | |
10251 | * detect that condition here, which happens early in CPU bringup, | |
10252 | * before any KVM threads can be running. Unfortunately, we can't | |
10253 | * bring the TSCs fully up to date with real time, as we aren't yet far | |
10254 | * enough into CPU bringup that we know how much real time has actually | |
9285ec4c | 10255 | * elapsed; our helper function, ktime_get_boottime_ns() will be using boot |
0dd6a6ed ZA |
10256 | * variables that haven't been updated yet. |
10257 | * | |
10258 | * So we simply find the maximum observed TSC above, then record the | |
10259 | * adjustment to TSC in each VCPU. When the VCPU later gets loaded, | |
10260 | * the adjustment will be applied. Note that we accumulate | |
10261 | * adjustments, in case multiple suspend cycles happen before some VCPU | |
10262 | * gets a chance to run again. In the event that no KVM threads get a | |
10263 | * chance to run, we will miss the entire elapsed period, as we'll have | |
10264 | * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may | |
10265 | * loose cycle time. This isn't too big a deal, since the loss will be | |
10266 | * uniform across all VCPUs (not to mention the scenario is extremely | |
10267 | * unlikely). It is possible that a second hibernate recovery happens | |
10268 | * much faster than a first, causing the observed TSC here to be | |
10269 | * smaller; this would require additional padding adjustment, which is | |
10270 | * why we set last_host_tsc to the local tsc observed here. | |
10271 | * | |
10272 | * N.B. - this code below runs only on platforms with reliable TSC, | |
10273 | * as that is the only way backwards_tsc is set above. Also note | |
10274 | * that this runs for ALL vcpus, which is not a bug; all VCPUs should | |
10275 | * have the same delta_cyc adjustment applied if backwards_tsc | |
10276 | * is detected. Note further, this adjustment is only done once, | |
10277 | * as we reset last_host_tsc on all VCPUs to stop this from being | |
10278 | * called multiple times (one for each physical CPU bringup). | |
10279 | * | |
4a969980 | 10280 | * Platforms with unreliable TSCs don't have to deal with this, they |
0dd6a6ed ZA |
10281 | * will be compensated by the logic in vcpu_load, which sets the TSC to |
10282 | * catchup mode. This will catchup all VCPUs to real time, but cannot | |
10283 | * guarantee that they stay in perfect synchronization. | |
10284 | */ | |
10285 | if (backwards_tsc) { | |
10286 | u64 delta_cyc = max_tsc - local_tsc; | |
10287 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
a826faf1 | 10288 | kvm->arch.backwards_tsc_observed = true; |
0dd6a6ed ZA |
10289 | kvm_for_each_vcpu(i, vcpu, kvm) { |
10290 | vcpu->arch.tsc_offset_adjustment += delta_cyc; | |
10291 | vcpu->arch.last_host_tsc = local_tsc; | |
105b21bb | 10292 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
10293 | } |
10294 | ||
10295 | /* | |
10296 | * We have to disable TSC offset matching.. if you were | |
10297 | * booting a VM while issuing an S4 host suspend.... | |
10298 | * you may have some problem. Solving this issue is | |
10299 | * left as an exercise to the reader. | |
10300 | */ | |
10301 | kvm->arch.last_tsc_nsec = 0; | |
10302 | kvm->arch.last_tsc_write = 0; | |
10303 | } | |
10304 | ||
10305 | } | |
10306 | return 0; | |
e9b11c17 ZX |
10307 | } |
10308 | ||
13a34e06 | 10309 | void kvm_arch_hardware_disable(void) |
e9b11c17 | 10310 | { |
afaf0b2f | 10311 | kvm_x86_ops.hardware_disable(); |
13a34e06 | 10312 | drop_user_return_notifiers(); |
e9b11c17 ZX |
10313 | } |
10314 | ||
b9904085 | 10315 | int kvm_arch_hardware_setup(void *opaque) |
e9b11c17 | 10316 | { |
d008dfdb | 10317 | struct kvm_x86_init_ops *ops = opaque; |
9e9c3fe4 NA |
10318 | int r; |
10319 | ||
91661989 SC |
10320 | rdmsrl_safe(MSR_EFER, &host_efer); |
10321 | ||
408e9a31 PB |
10322 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
10323 | rdmsrl(MSR_IA32_XSS, host_xss); | |
10324 | ||
d008dfdb | 10325 | r = ops->hardware_setup(); |
9e9c3fe4 NA |
10326 | if (r != 0) |
10327 | return r; | |
10328 | ||
afaf0b2f | 10329 | memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops)); |
69c6f69a | 10330 | |
408e9a31 PB |
10331 | if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES)) |
10332 | supported_xss = 0; | |
10333 | ||
139f7425 PB |
10334 | #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f) |
10335 | cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_); | |
10336 | #undef __kvm_cpu_cap_has | |
b11306b5 | 10337 | |
35181e86 HZ |
10338 | if (kvm_has_tsc_control) { |
10339 | /* | |
10340 | * Make sure the user can only configure tsc_khz values that | |
10341 | * fit into a signed integer. | |
273ba457 | 10342 | * A min value is not calculated because it will always |
35181e86 HZ |
10343 | * be 1 on all machines. |
10344 | */ | |
10345 | u64 max = min(0x7fffffffULL, | |
10346 | __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); | |
10347 | kvm_max_guest_tsc_khz = max; | |
10348 | ||
ad721883 | 10349 | kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; |
35181e86 | 10350 | } |
ad721883 | 10351 | |
9e9c3fe4 NA |
10352 | kvm_init_msr_list(); |
10353 | return 0; | |
e9b11c17 ZX |
10354 | } |
10355 | ||
10356 | void kvm_arch_hardware_unsetup(void) | |
10357 | { | |
afaf0b2f | 10358 | kvm_x86_ops.hardware_unsetup(); |
e9b11c17 ZX |
10359 | } |
10360 | ||
b9904085 | 10361 | int kvm_arch_check_processor_compat(void *opaque) |
e9b11c17 | 10362 | { |
f1cdecf5 | 10363 | struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); |
d008dfdb | 10364 | struct kvm_x86_init_ops *ops = opaque; |
f1cdecf5 SC |
10365 | |
10366 | WARN_ON(!irqs_disabled()); | |
10367 | ||
139f7425 PB |
10368 | if (__cr4_reserved_bits(cpu_has, c) != |
10369 | __cr4_reserved_bits(cpu_has, &boot_cpu_data)) | |
f1cdecf5 SC |
10370 | return -EIO; |
10371 | ||
d008dfdb | 10372 | return ops->check_processor_compatibility(); |
d71ba788 PB |
10373 | } |
10374 | ||
10375 | bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) | |
10376 | { | |
10377 | return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; | |
10378 | } | |
10379 | EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); | |
10380 | ||
10381 | bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) | |
10382 | { | |
10383 | return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; | |
e9b11c17 ZX |
10384 | } |
10385 | ||
6e4e3b4d CL |
10386 | __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu); |
10387 | EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu); | |
54e9818f | 10388 | |
e790d9ef RK |
10389 | void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) |
10390 | { | |
b35e5548 LX |
10391 | struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); |
10392 | ||
c595ceee | 10393 | vcpu->arch.l1tf_flush_l1d = true; |
b35e5548 LX |
10394 | if (pmu->version && unlikely(pmu->event_count)) { |
10395 | pmu->need_cleanup = true; | |
10396 | kvm_make_request(KVM_REQ_PMU, vcpu); | |
10397 | } | |
afaf0b2f | 10398 | kvm_x86_ops.sched_in(vcpu, cpu); |
e790d9ef RK |
10399 | } |
10400 | ||
562b6b08 SC |
10401 | void kvm_arch_free_vm(struct kvm *kvm) |
10402 | { | |
10403 | kfree(kvm->arch.hyperv.hv_pa_pg); | |
10404 | vfree(kvm); | |
e790d9ef RK |
10405 | } |
10406 | ||
562b6b08 | 10407 | |
e08b9637 | 10408 | int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) |
d19a9cd2 | 10409 | { |
e08b9637 CO |
10410 | if (type) |
10411 | return -EINVAL; | |
10412 | ||
6ef768fa | 10413 | INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); |
f05e70ac | 10414 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
10605204 | 10415 | INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); |
1aa9b957 | 10416 | INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages); |
4d5c5d0f | 10417 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
e0f0bbc5 | 10418 | atomic_set(&kvm->arch.noncoherent_dma_count, 0); |
d19a9cd2 | 10419 | |
5550af4d SY |
10420 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
10421 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
7a84428a AW |
10422 | /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ |
10423 | set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, | |
10424 | &kvm->arch.irq_sources_bitmap); | |
5550af4d | 10425 | |
038f8c11 | 10426 | raw_spin_lock_init(&kvm->arch.tsc_write_lock); |
1e08ec4a | 10427 | mutex_init(&kvm->arch.apic_map_lock); |
d828199e MT |
10428 | spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); |
10429 | ||
8171cd68 | 10430 | kvm->arch.kvmclock_offset = -get_kvmclock_base_ns(); |
d828199e | 10431 | pvclock_update_vm_gtod_copy(kvm); |
53f658b3 | 10432 | |
6fbbde9a DS |
10433 | kvm->arch.guest_can_read_msr_platform_info = true; |
10434 | ||
7e44e449 | 10435 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); |
332967a3 | 10436 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); |
7e44e449 | 10437 | |
cbc0236a | 10438 | kvm_hv_init_vm(kvm); |
0eb05bf2 | 10439 | kvm_page_track_init(kvm); |
13d268ca | 10440 | kvm_mmu_init_vm(kvm); |
0eb05bf2 | 10441 | |
afaf0b2f | 10442 | return kvm_x86_ops.vm_init(kvm); |
d19a9cd2 ZX |
10443 | } |
10444 | ||
1aa9b957 JS |
10445 | int kvm_arch_post_init_vm(struct kvm *kvm) |
10446 | { | |
10447 | return kvm_mmu_post_init_vm(kvm); | |
10448 | } | |
10449 | ||
d19a9cd2 ZX |
10450 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) |
10451 | { | |
ec7660cc | 10452 | vcpu_load(vcpu); |
d19a9cd2 ZX |
10453 | kvm_mmu_unload(vcpu); |
10454 | vcpu_put(vcpu); | |
10455 | } | |
10456 | ||
10457 | static void kvm_free_vcpus(struct kvm *kvm) | |
10458 | { | |
10459 | unsigned int i; | |
988a2cae | 10460 | struct kvm_vcpu *vcpu; |
d19a9cd2 ZX |
10461 | |
10462 | /* | |
10463 | * Unpin any mmu pages first. | |
10464 | */ | |
af585b92 GN |
10465 | kvm_for_each_vcpu(i, vcpu, kvm) { |
10466 | kvm_clear_async_pf_completion_queue(vcpu); | |
988a2cae | 10467 | kvm_unload_vcpu_mmu(vcpu); |
af585b92 | 10468 | } |
988a2cae | 10469 | kvm_for_each_vcpu(i, vcpu, kvm) |
4543bdc0 | 10470 | kvm_vcpu_destroy(vcpu); |
988a2cae GN |
10471 | |
10472 | mutex_lock(&kvm->lock); | |
10473 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
10474 | kvm->vcpus[i] = NULL; | |
d19a9cd2 | 10475 | |
988a2cae GN |
10476 | atomic_set(&kvm->online_vcpus, 0); |
10477 | mutex_unlock(&kvm->lock); | |
d19a9cd2 ZX |
10478 | } |
10479 | ||
ad8ba2cd SY |
10480 | void kvm_arch_sync_events(struct kvm *kvm) |
10481 | { | |
332967a3 | 10482 | cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); |
7e44e449 | 10483 | cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); |
aea924f6 | 10484 | kvm_free_pit(kvm); |
ad8ba2cd SY |
10485 | } |
10486 | ||
ff5a983c PX |
10487 | #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e)) |
10488 | ||
10489 | /** | |
10490 | * __x86_set_memory_region: Setup KVM internal memory slot | |
10491 | * | |
10492 | * @kvm: the kvm pointer to the VM. | |
10493 | * @id: the slot ID to setup. | |
10494 | * @gpa: the GPA to install the slot (unused when @size == 0). | |
10495 | * @size: the size of the slot. Set to zero to uninstall a slot. | |
10496 | * | |
10497 | * This function helps to setup a KVM internal memory slot. Specify | |
10498 | * @size > 0 to install a new slot, while @size == 0 to uninstall a | |
10499 | * slot. The return code can be one of the following: | |
10500 | * | |
10501 | * HVA: on success (uninstall will return a bogus HVA) | |
10502 | * -errno: on error | |
10503 | * | |
10504 | * The caller should always use IS_ERR() to check the return value | |
10505 | * before use. Note, the KVM internal memory slots are guaranteed to | |
10506 | * remain valid and unchanged until the VM is destroyed, i.e., the | |
10507 | * GPA->HVA translation will not change. However, the HVA is a user | |
10508 | * address, i.e. its accessibility is not guaranteed, and must be | |
10509 | * accessed via __copy_{to,from}_user(). | |
10510 | */ | |
10511 | void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, | |
10512 | u32 size) | |
9da0e4d5 PB |
10513 | { |
10514 | int i, r; | |
3f649ab7 | 10515 | unsigned long hva, old_npages; |
f0d648bd | 10516 | struct kvm_memslots *slots = kvm_memslots(kvm); |
0577d1ab | 10517 | struct kvm_memory_slot *slot; |
9da0e4d5 PB |
10518 | |
10519 | /* Called with kvm->slots_lock held. */ | |
1d8007bd | 10520 | if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) |
ff5a983c | 10521 | return ERR_PTR_USR(-EINVAL); |
9da0e4d5 | 10522 | |
f0d648bd PB |
10523 | slot = id_to_memslot(slots, id); |
10524 | if (size) { | |
0577d1ab | 10525 | if (slot && slot->npages) |
ff5a983c | 10526 | return ERR_PTR_USR(-EEXIST); |
f0d648bd PB |
10527 | |
10528 | /* | |
10529 | * MAP_SHARED to prevent internal slot pages from being moved | |
10530 | * by fork()/COW. | |
10531 | */ | |
10532 | hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, | |
10533 | MAP_SHARED | MAP_ANONYMOUS, 0); | |
10534 | if (IS_ERR((void *)hva)) | |
ff5a983c | 10535 | return (void __user *)hva; |
f0d648bd | 10536 | } else { |
0577d1ab | 10537 | if (!slot || !slot->npages) |
f0d648bd PB |
10538 | return 0; |
10539 | ||
0577d1ab | 10540 | old_npages = slot->npages; |
b66f9bab | 10541 | hva = slot->userspace_addr; |
f0d648bd PB |
10542 | } |
10543 | ||
9da0e4d5 | 10544 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
1d8007bd | 10545 | struct kvm_userspace_memory_region m; |
9da0e4d5 | 10546 | |
1d8007bd PB |
10547 | m.slot = id | (i << 16); |
10548 | m.flags = 0; | |
10549 | m.guest_phys_addr = gpa; | |
f0d648bd | 10550 | m.userspace_addr = hva; |
1d8007bd | 10551 | m.memory_size = size; |
9da0e4d5 PB |
10552 | r = __kvm_set_memory_region(kvm, &m); |
10553 | if (r < 0) | |
ff5a983c | 10554 | return ERR_PTR_USR(r); |
9da0e4d5 PB |
10555 | } |
10556 | ||
103c763c | 10557 | if (!size) |
0577d1ab | 10558 | vm_munmap(hva, old_npages * PAGE_SIZE); |
f0d648bd | 10559 | |
ff5a983c | 10560 | return (void __user *)hva; |
9da0e4d5 PB |
10561 | } |
10562 | EXPORT_SYMBOL_GPL(__x86_set_memory_region); | |
10563 | ||
1aa9b957 JS |
10564 | void kvm_arch_pre_destroy_vm(struct kvm *kvm) |
10565 | { | |
10566 | kvm_mmu_pre_destroy_vm(kvm); | |
10567 | } | |
10568 | ||
d19a9cd2 ZX |
10569 | void kvm_arch_destroy_vm(struct kvm *kvm) |
10570 | { | |
1a155254 AG |
10571 | u32 i; |
10572 | ||
27469d29 AH |
10573 | if (current->mm == kvm->mm) { |
10574 | /* | |
10575 | * Free memory regions allocated on behalf of userspace, | |
10576 | * unless the the memory map has changed due to process exit | |
10577 | * or fd copying. | |
10578 | */ | |
6a3c623b PX |
10579 | mutex_lock(&kvm->slots_lock); |
10580 | __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, | |
10581 | 0, 0); | |
10582 | __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, | |
10583 | 0, 0); | |
10584 | __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); | |
10585 | mutex_unlock(&kvm->slots_lock); | |
27469d29 | 10586 | } |
afaf0b2f SC |
10587 | if (kvm_x86_ops.vm_destroy) |
10588 | kvm_x86_ops.vm_destroy(kvm); | |
1a155254 AG |
10589 | for (i = 0; i < kvm->arch.msr_filter.count; i++) |
10590 | kfree(kvm->arch.msr_filter.ranges[i].bitmap); | |
c761159c PX |
10591 | kvm_pic_destroy(kvm); |
10592 | kvm_ioapic_destroy(kvm); | |
d19a9cd2 | 10593 | kvm_free_vcpus(kvm); |
af1bae54 | 10594 | kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); |
66bb8a06 | 10595 | kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); |
13d268ca | 10596 | kvm_mmu_uninit_vm(kvm); |
2beb6dad | 10597 | kvm_page_track_cleanup(kvm); |
cbc0236a | 10598 | kvm_hv_destroy_vm(kvm); |
d19a9cd2 | 10599 | } |
0de10343 | 10600 | |
e96c81ee | 10601 | void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) |
db3fe4eb TY |
10602 | { |
10603 | int i; | |
10604 | ||
d89cc617 | 10605 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
e96c81ee SC |
10606 | kvfree(slot->arch.rmap[i]); |
10607 | slot->arch.rmap[i] = NULL; | |
10608 | ||
d89cc617 TY |
10609 | if (i == 0) |
10610 | continue; | |
10611 | ||
e96c81ee SC |
10612 | kvfree(slot->arch.lpage_info[i - 1]); |
10613 | slot->arch.lpage_info[i - 1] = NULL; | |
db3fe4eb | 10614 | } |
21ebbeda | 10615 | |
e96c81ee | 10616 | kvm_page_track_free_memslot(slot); |
db3fe4eb TY |
10617 | } |
10618 | ||
0dab98b7 SC |
10619 | static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot, |
10620 | unsigned long npages) | |
db3fe4eb TY |
10621 | { |
10622 | int i; | |
10623 | ||
edd4fa37 SC |
10624 | /* |
10625 | * Clear out the previous array pointers for the KVM_MR_MOVE case. The | |
10626 | * old arrays will be freed by __kvm_set_memory_region() if installing | |
10627 | * the new memslot is successful. | |
10628 | */ | |
10629 | memset(&slot->arch, 0, sizeof(slot->arch)); | |
10630 | ||
d89cc617 | 10631 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
92f94f1e | 10632 | struct kvm_lpage_info *linfo; |
db3fe4eb TY |
10633 | unsigned long ugfn; |
10634 | int lpages; | |
d89cc617 | 10635 | int level = i + 1; |
db3fe4eb TY |
10636 | |
10637 | lpages = gfn_to_index(slot->base_gfn + npages - 1, | |
10638 | slot->base_gfn, level) + 1; | |
10639 | ||
d89cc617 | 10640 | slot->arch.rmap[i] = |
778e1cdd | 10641 | kvcalloc(lpages, sizeof(*slot->arch.rmap[i]), |
254272ce | 10642 | GFP_KERNEL_ACCOUNT); |
d89cc617 | 10643 | if (!slot->arch.rmap[i]) |
77d11309 | 10644 | goto out_free; |
d89cc617 TY |
10645 | if (i == 0) |
10646 | continue; | |
77d11309 | 10647 | |
254272ce | 10648 | linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); |
92f94f1e | 10649 | if (!linfo) |
db3fe4eb TY |
10650 | goto out_free; |
10651 | ||
92f94f1e XG |
10652 | slot->arch.lpage_info[i - 1] = linfo; |
10653 | ||
db3fe4eb | 10654 | if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 10655 | linfo[0].disallow_lpage = 1; |
db3fe4eb | 10656 | if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 10657 | linfo[lpages - 1].disallow_lpage = 1; |
db3fe4eb TY |
10658 | ugfn = slot->userspace_addr >> PAGE_SHIFT; |
10659 | /* | |
10660 | * If the gfn and userspace address are not aligned wrt each | |
600087b6 | 10661 | * other, disable large page support for this slot. |
db3fe4eb | 10662 | */ |
600087b6 | 10663 | if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) { |
db3fe4eb TY |
10664 | unsigned long j; |
10665 | ||
10666 | for (j = 0; j < lpages; ++j) | |
92f94f1e | 10667 | linfo[j].disallow_lpage = 1; |
db3fe4eb TY |
10668 | } |
10669 | } | |
10670 | ||
21ebbeda XG |
10671 | if (kvm_page_track_create_memslot(slot, npages)) |
10672 | goto out_free; | |
10673 | ||
db3fe4eb TY |
10674 | return 0; |
10675 | ||
10676 | out_free: | |
d89cc617 | 10677 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
548ef284 | 10678 | kvfree(slot->arch.rmap[i]); |
d89cc617 TY |
10679 | slot->arch.rmap[i] = NULL; |
10680 | if (i == 0) | |
10681 | continue; | |
10682 | ||
548ef284 | 10683 | kvfree(slot->arch.lpage_info[i - 1]); |
d89cc617 | 10684 | slot->arch.lpage_info[i - 1] = NULL; |
db3fe4eb TY |
10685 | } |
10686 | return -ENOMEM; | |
10687 | } | |
10688 | ||
15248258 | 10689 | void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) |
e59dbe09 | 10690 | { |
91724814 BO |
10691 | struct kvm_vcpu *vcpu; |
10692 | int i; | |
10693 | ||
e6dff7d1 TY |
10694 | /* |
10695 | * memslots->generation has been incremented. | |
10696 | * mmio generation may have reached its maximum value. | |
10697 | */ | |
15248258 | 10698 | kvm_mmu_invalidate_mmio_sptes(kvm, gen); |
91724814 BO |
10699 | |
10700 | /* Force re-initialization of steal_time cache */ | |
10701 | kvm_for_each_vcpu(i, vcpu, kvm) | |
10702 | kvm_vcpu_kick(vcpu); | |
e59dbe09 TY |
10703 | } |
10704 | ||
f7784b8e MT |
10705 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
10706 | struct kvm_memory_slot *memslot, | |
09170a49 | 10707 | const struct kvm_userspace_memory_region *mem, |
7b6195a9 | 10708 | enum kvm_mr_change change) |
0de10343 | 10709 | { |
0dab98b7 SC |
10710 | if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) |
10711 | return kvm_alloc_memslot_metadata(memslot, | |
10712 | mem->memory_size >> PAGE_SHIFT); | |
f7784b8e MT |
10713 | return 0; |
10714 | } | |
10715 | ||
88178fd4 | 10716 | static void kvm_mmu_slot_apply_flags(struct kvm *kvm, |
3741679b AY |
10717 | struct kvm_memory_slot *old, |
10718 | struct kvm_memory_slot *new, | |
10719 | enum kvm_mr_change change) | |
88178fd4 | 10720 | { |
3741679b AY |
10721 | /* |
10722 | * Nothing to do for RO slots or CREATE/MOVE/DELETE of a slot. | |
10723 | * See comments below. | |
10724 | */ | |
10725 | if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY)) | |
88178fd4 | 10726 | return; |
88178fd4 KH |
10727 | |
10728 | /* | |
3741679b AY |
10729 | * Dirty logging tracks sptes in 4k granularity, meaning that large |
10730 | * sptes have to be split. If live migration is successful, the guest | |
10731 | * in the source machine will be destroyed and large sptes will be | |
10732 | * created in the destination. However, if the guest continues to run | |
10733 | * in the source machine (for example if live migration fails), small | |
10734 | * sptes will remain around and cause bad performance. | |
88178fd4 | 10735 | * |
3741679b AY |
10736 | * Scan sptes if dirty logging has been stopped, dropping those |
10737 | * which can be collapsed into a single large-page spte. Later | |
10738 | * page faults will create the large-page sptes. | |
88178fd4 | 10739 | * |
3741679b AY |
10740 | * There is no need to do this in any of the following cases: |
10741 | * CREATE: No dirty mappings will already exist. | |
10742 | * MOVE/DELETE: The old mappings will already have been cleaned up by | |
10743 | * kvm_arch_flush_shadow_memslot() | |
10744 | */ | |
10745 | if ((old->flags & KVM_MEM_LOG_DIRTY_PAGES) && | |
10746 | !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) | |
10747 | kvm_mmu_zap_collapsible_sptes(kvm, new); | |
10748 | ||
10749 | /* | |
10750 | * Enable or disable dirty logging for the slot. | |
88178fd4 | 10751 | * |
3741679b AY |
10752 | * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of the old |
10753 | * slot have been zapped so no dirty logging updates are needed for | |
10754 | * the old slot. | |
10755 | * For KVM_MR_CREATE and KVM_MR_MOVE, once the new slot is visible | |
10756 | * any mappings that might be created in it will consume the | |
10757 | * properties of the new slot and do not need to be updated here. | |
88178fd4 | 10758 | * |
3741679b AY |
10759 | * When PML is enabled, the kvm_x86_ops dirty logging hooks are |
10760 | * called to enable/disable dirty logging. | |
88178fd4 | 10761 | * |
3741679b AY |
10762 | * When disabling dirty logging with PML enabled, the D-bit is set |
10763 | * for sptes in the slot in order to prevent unnecessary GPA | |
10764 | * logging in the PML buffer (and potential PML buffer full VMEXIT). | |
10765 | * This guarantees leaving PML enabled for the guest's lifetime | |
10766 | * won't have any additional overhead from PML when the guest is | |
10767 | * running with dirty logging disabled. | |
88178fd4 | 10768 | * |
3741679b AY |
10769 | * When enabling dirty logging, large sptes are write-protected |
10770 | * so they can be split on first write. New large sptes cannot | |
10771 | * be created for this slot until the end of the logging. | |
88178fd4 | 10772 | * See the comments in fast_page_fault(). |
3741679b AY |
10773 | * For small sptes, nothing is done if the dirty log is in the |
10774 | * initial-all-set state. Otherwise, depending on whether pml | |
10775 | * is enabled the D-bit or the W-bit will be cleared. | |
88178fd4 KH |
10776 | */ |
10777 | if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { | |
afaf0b2f SC |
10778 | if (kvm_x86_ops.slot_enable_log_dirty) { |
10779 | kvm_x86_ops.slot_enable_log_dirty(kvm, new); | |
3c9bd400 JZ |
10780 | } else { |
10781 | int level = | |
10782 | kvm_dirty_log_manual_protect_and_init_set(kvm) ? | |
3bae0459 | 10783 | PG_LEVEL_2M : PG_LEVEL_4K; |
3c9bd400 JZ |
10784 | |
10785 | /* | |
10786 | * If we're with initial-all-set, we don't need | |
10787 | * to write protect any small page because | |
10788 | * they're reported as dirty already. However | |
10789 | * we still need to write-protect huge pages | |
10790 | * so that the page split can happen lazily on | |
10791 | * the first write to the huge page. | |
10792 | */ | |
10793 | kvm_mmu_slot_remove_write_access(kvm, new, level); | |
10794 | } | |
88178fd4 | 10795 | } else { |
afaf0b2f SC |
10796 | if (kvm_x86_ops.slot_disable_log_dirty) |
10797 | kvm_x86_ops.slot_disable_log_dirty(kvm, new); | |
88178fd4 KH |
10798 | } |
10799 | } | |
10800 | ||
f7784b8e | 10801 | void kvm_arch_commit_memory_region(struct kvm *kvm, |
09170a49 | 10802 | const struct kvm_userspace_memory_region *mem, |
9d4c197c | 10803 | struct kvm_memory_slot *old, |
f36f3f28 | 10804 | const struct kvm_memory_slot *new, |
8482644a | 10805 | enum kvm_mr_change change) |
f7784b8e | 10806 | { |
48c0e4e9 | 10807 | if (!kvm->arch.n_requested_mmu_pages) |
4d66623c WY |
10808 | kvm_mmu_change_mmu_pages(kvm, |
10809 | kvm_mmu_calculate_default_mmu_pages(kvm)); | |
1c91cad4 | 10810 | |
3ea3b7fa | 10811 | /* |
f36f3f28 | 10812 | * FIXME: const-ify all uses of struct kvm_memory_slot. |
c972f3b1 | 10813 | */ |
3741679b | 10814 | kvm_mmu_slot_apply_flags(kvm, old, (struct kvm_memory_slot *) new, change); |
21198846 SC |
10815 | |
10816 | /* Free the arrays associated with the old memslot. */ | |
10817 | if (change == KVM_MR_MOVE) | |
e96c81ee | 10818 | kvm_arch_free_memslot(kvm, old); |
0de10343 | 10819 | } |
1d737c8a | 10820 | |
2df72e9b | 10821 | void kvm_arch_flush_shadow_all(struct kvm *kvm) |
34d4cb8f | 10822 | { |
7390de1e | 10823 | kvm_mmu_zap_all(kvm); |
34d4cb8f MT |
10824 | } |
10825 | ||
2df72e9b MT |
10826 | void kvm_arch_flush_shadow_memslot(struct kvm *kvm, |
10827 | struct kvm_memory_slot *slot) | |
10828 | { | |
ae7cd873 | 10829 | kvm_page_track_flush_slot(kvm, slot); |
2df72e9b MT |
10830 | } |
10831 | ||
e6c67d8c LA |
10832 | static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) |
10833 | { | |
10834 | return (is_guest_mode(vcpu) && | |
afaf0b2f SC |
10835 | kvm_x86_ops.guest_apic_has_interrupt && |
10836 | kvm_x86_ops.guest_apic_has_interrupt(vcpu)); | |
e6c67d8c LA |
10837 | } |
10838 | ||
5d9bc648 PB |
10839 | static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) |
10840 | { | |
10841 | if (!list_empty_careful(&vcpu->async_pf.done)) | |
10842 | return true; | |
10843 | ||
10844 | if (kvm_apic_has_events(vcpu)) | |
10845 | return true; | |
10846 | ||
10847 | if (vcpu->arch.pv.pv_unhalted) | |
10848 | return true; | |
10849 | ||
a5f01f8e WL |
10850 | if (vcpu->arch.exception.pending) |
10851 | return true; | |
10852 | ||
47a66eed Z |
10853 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || |
10854 | (vcpu->arch.nmi_pending && | |
c300ab9f | 10855 | kvm_x86_ops.nmi_allowed(vcpu, false))) |
5d9bc648 PB |
10856 | return true; |
10857 | ||
47a66eed | 10858 | if (kvm_test_request(KVM_REQ_SMI, vcpu) || |
a9fa7cb6 | 10859 | (vcpu->arch.smi_pending && |
c300ab9f | 10860 | kvm_x86_ops.smi_allowed(vcpu, false))) |
73917739 PB |
10861 | return true; |
10862 | ||
5d9bc648 | 10863 | if (kvm_arch_interrupt_allowed(vcpu) && |
e6c67d8c LA |
10864 | (kvm_cpu_has_interrupt(vcpu) || |
10865 | kvm_guest_apic_has_interrupt(vcpu))) | |
5d9bc648 PB |
10866 | return true; |
10867 | ||
1f4b34f8 AS |
10868 | if (kvm_hv_has_stimer_pending(vcpu)) |
10869 | return true; | |
10870 | ||
d2060bd4 SC |
10871 | if (is_guest_mode(vcpu) && |
10872 | kvm_x86_ops.nested_ops->hv_timer_pending && | |
10873 | kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) | |
10874 | return true; | |
10875 | ||
5d9bc648 PB |
10876 | return false; |
10877 | } | |
10878 | ||
1d737c8a ZX |
10879 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
10880 | { | |
5d9bc648 | 10881 | return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); |
1d737c8a | 10882 | } |
5736199a | 10883 | |
17e433b5 WL |
10884 | bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) |
10885 | { | |
10886 | if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) | |
10887 | return true; | |
10888 | ||
10889 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || | |
10890 | kvm_test_request(KVM_REQ_SMI, vcpu) || | |
10891 | kvm_test_request(KVM_REQ_EVENT, vcpu)) | |
10892 | return true; | |
10893 | ||
afaf0b2f | 10894 | if (vcpu->arch.apicv_active && kvm_x86_ops.dy_apicv_has_pending_interrupt(vcpu)) |
17e433b5 WL |
10895 | return true; |
10896 | ||
10897 | return false; | |
10898 | } | |
10899 | ||
199b5763 LM |
10900 | bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) |
10901 | { | |
de63ad4c | 10902 | return vcpu->arch.preempted_in_kernel; |
199b5763 LM |
10903 | } |
10904 | ||
b6d33834 | 10905 | int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) |
5736199a | 10906 | { |
b6d33834 | 10907 | return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; |
5736199a | 10908 | } |
78646121 GN |
10909 | |
10910 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
10911 | { | |
c300ab9f | 10912 | return kvm_x86_ops.interrupt_allowed(vcpu, false); |
78646121 | 10913 | } |
229456fc | 10914 | |
82b32774 | 10915 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) |
f92653ee | 10916 | { |
7ed9abfe TL |
10917 | /* Can't read the RIP when guest state is protected, just return 0 */ |
10918 | if (vcpu->arch.guest_state_protected) | |
10919 | return 0; | |
10920 | ||
82b32774 NA |
10921 | if (is_64_bit_mode(vcpu)) |
10922 | return kvm_rip_read(vcpu); | |
10923 | return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + | |
10924 | kvm_rip_read(vcpu)); | |
10925 | } | |
10926 | EXPORT_SYMBOL_GPL(kvm_get_linear_rip); | |
f92653ee | 10927 | |
82b32774 NA |
10928 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) |
10929 | { | |
10930 | return kvm_get_linear_rip(vcpu) == linear_rip; | |
f92653ee JK |
10931 | } |
10932 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
10933 | ||
94fe45da JK |
10934 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
10935 | { | |
10936 | unsigned long rflags; | |
10937 | ||
afaf0b2f | 10938 | rflags = kvm_x86_ops.get_rflags(vcpu); |
94fe45da | 10939 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
c310bac5 | 10940 | rflags &= ~X86_EFLAGS_TF; |
94fe45da JK |
10941 | return rflags; |
10942 | } | |
10943 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
10944 | ||
6addfc42 | 10945 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) |
94fe45da JK |
10946 | { |
10947 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
f92653ee | 10948 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) |
c310bac5 | 10949 | rflags |= X86_EFLAGS_TF; |
afaf0b2f | 10950 | kvm_x86_ops.set_rflags(vcpu, rflags); |
6addfc42 PB |
10951 | } |
10952 | ||
10953 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
10954 | { | |
10955 | __kvm_set_rflags(vcpu, rflags); | |
3842d135 | 10956 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
94fe45da JK |
10957 | } |
10958 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
10959 | ||
56028d08 GN |
10960 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) |
10961 | { | |
10962 | int r; | |
10963 | ||
44dd3ffa | 10964 | if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) || |
f2e10669 | 10965 | work->wakeup_all) |
56028d08 GN |
10966 | return; |
10967 | ||
10968 | r = kvm_mmu_reload(vcpu); | |
10969 | if (unlikely(r)) | |
10970 | return; | |
10971 | ||
44dd3ffa | 10972 | if (!vcpu->arch.mmu->direct_map && |
d8dd54e0 | 10973 | work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu)) |
fb67e14f XG |
10974 | return; |
10975 | ||
7a02674d | 10976 | kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true); |
56028d08 GN |
10977 | } |
10978 | ||
af585b92 GN |
10979 | static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) |
10980 | { | |
dd03bcaa PX |
10981 | BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU)); |
10982 | ||
af585b92 GN |
10983 | return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); |
10984 | } | |
10985 | ||
10986 | static inline u32 kvm_async_pf_next_probe(u32 key) | |
10987 | { | |
dd03bcaa | 10988 | return (key + 1) & (ASYNC_PF_PER_VCPU - 1); |
af585b92 GN |
10989 | } |
10990 | ||
10991 | static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
10992 | { | |
10993 | u32 key = kvm_async_pf_hash_fn(gfn); | |
10994 | ||
10995 | while (vcpu->arch.apf.gfns[key] != ~0) | |
10996 | key = kvm_async_pf_next_probe(key); | |
10997 | ||
10998 | vcpu->arch.apf.gfns[key] = gfn; | |
10999 | } | |
11000 | ||
11001 | static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) | |
11002 | { | |
11003 | int i; | |
11004 | u32 key = kvm_async_pf_hash_fn(gfn); | |
11005 | ||
dd03bcaa | 11006 | for (i = 0; i < ASYNC_PF_PER_VCPU && |
c7d28c24 XG |
11007 | (vcpu->arch.apf.gfns[key] != gfn && |
11008 | vcpu->arch.apf.gfns[key] != ~0); i++) | |
af585b92 GN |
11009 | key = kvm_async_pf_next_probe(key); |
11010 | ||
11011 | return key; | |
11012 | } | |
11013 | ||
11014 | bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
11015 | { | |
11016 | return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; | |
11017 | } | |
11018 | ||
11019 | static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
11020 | { | |
11021 | u32 i, j, k; | |
11022 | ||
11023 | i = j = kvm_async_pf_gfn_slot(vcpu, gfn); | |
0fd46044 PX |
11024 | |
11025 | if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn)) | |
11026 | return; | |
11027 | ||
af585b92 GN |
11028 | while (true) { |
11029 | vcpu->arch.apf.gfns[i] = ~0; | |
11030 | do { | |
11031 | j = kvm_async_pf_next_probe(j); | |
11032 | if (vcpu->arch.apf.gfns[j] == ~0) | |
11033 | return; | |
11034 | k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); | |
11035 | /* | |
11036 | * k lies cyclically in ]i,j] | |
11037 | * | i.k.j | | |
11038 | * |....j i.k.| or |.k..j i...| | |
11039 | */ | |
11040 | } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); | |
11041 | vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; | |
11042 | i = j; | |
11043 | } | |
11044 | } | |
11045 | ||
68fd66f1 | 11046 | static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu) |
7c90705b | 11047 | { |
68fd66f1 VK |
11048 | u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT; |
11049 | ||
11050 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason, | |
11051 | sizeof(reason)); | |
11052 | } | |
11053 | ||
11054 | static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token) | |
11055 | { | |
2635b5c4 | 11056 | unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); |
4e335d9e | 11057 | |
2635b5c4 VK |
11058 | return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, |
11059 | &token, offset, sizeof(token)); | |
11060 | } | |
11061 | ||
11062 | static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu) | |
11063 | { | |
11064 | unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); | |
11065 | u32 val; | |
11066 | ||
11067 | if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, | |
11068 | &val, offset, sizeof(val))) | |
11069 | return false; | |
11070 | ||
11071 | return !val; | |
7c90705b GN |
11072 | } |
11073 | ||
1dfdb45e PB |
11074 | static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) |
11075 | { | |
11076 | if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu)) | |
11077 | return false; | |
11078 | ||
2635b5c4 VK |
11079 | if (!kvm_pv_async_pf_enabled(vcpu) || |
11080 | (vcpu->arch.apf.send_user_only && kvm_x86_ops.get_cpl(vcpu) == 0)) | |
1dfdb45e PB |
11081 | return false; |
11082 | ||
11083 | return true; | |
11084 | } | |
11085 | ||
11086 | bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) | |
11087 | { | |
11088 | if (unlikely(!lapic_in_kernel(vcpu) || | |
11089 | kvm_event_needs_reinjection(vcpu) || | |
11090 | vcpu->arch.exception.pending)) | |
11091 | return false; | |
11092 | ||
11093 | if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) | |
11094 | return false; | |
11095 | ||
11096 | /* | |
11097 | * If interrupts are off we cannot even use an artificial | |
11098 | * halt state. | |
11099 | */ | |
c300ab9f | 11100 | return kvm_arch_interrupt_allowed(vcpu); |
1dfdb45e PB |
11101 | } |
11102 | ||
2a18b7e7 | 11103 | bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
af585b92 GN |
11104 | struct kvm_async_pf *work) |
11105 | { | |
6389ee94 AK |
11106 | struct x86_exception fault; |
11107 | ||
736c291c | 11108 | trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa); |
af585b92 | 11109 | kvm_add_async_pf_gfn(vcpu, work->arch.gfn); |
7c90705b | 11110 | |
1dfdb45e | 11111 | if (kvm_can_deliver_async_pf(vcpu) && |
68fd66f1 | 11112 | !apf_put_user_notpresent(vcpu)) { |
6389ee94 AK |
11113 | fault.vector = PF_VECTOR; |
11114 | fault.error_code_valid = true; | |
11115 | fault.error_code = 0; | |
11116 | fault.nested_page_fault = false; | |
11117 | fault.address = work->arch.token; | |
adfe20fb | 11118 | fault.async_page_fault = true; |
6389ee94 | 11119 | kvm_inject_page_fault(vcpu, &fault); |
2a18b7e7 | 11120 | return true; |
1dfdb45e PB |
11121 | } else { |
11122 | /* | |
11123 | * It is not possible to deliver a paravirtualized asynchronous | |
11124 | * page fault, but putting the guest in an artificial halt state | |
11125 | * can be beneficial nevertheless: if an interrupt arrives, we | |
11126 | * can deliver it timely and perhaps the guest will schedule | |
11127 | * another process. When the instruction that triggered a page | |
11128 | * fault is retried, hopefully the page will be ready in the host. | |
11129 | */ | |
11130 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
2a18b7e7 | 11131 | return false; |
7c90705b | 11132 | } |
af585b92 GN |
11133 | } |
11134 | ||
11135 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
11136 | struct kvm_async_pf *work) | |
11137 | { | |
2635b5c4 VK |
11138 | struct kvm_lapic_irq irq = { |
11139 | .delivery_mode = APIC_DM_FIXED, | |
11140 | .vector = vcpu->arch.apf.vec | |
11141 | }; | |
6389ee94 | 11142 | |
f2e10669 | 11143 | if (work->wakeup_all) |
7c90705b GN |
11144 | work->arch.token = ~0; /* broadcast wakeup */ |
11145 | else | |
11146 | kvm_del_async_pf_gfn(vcpu, work->arch.gfn); | |
736c291c | 11147 | trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa); |
7c90705b | 11148 | |
2a18b7e7 VK |
11149 | if ((work->wakeup_all || work->notpresent_injected) && |
11150 | kvm_pv_async_pf_enabled(vcpu) && | |
557a961a VK |
11151 | !apf_put_user_ready(vcpu, work->arch.token)) { |
11152 | vcpu->arch.apf.pageready_pending = true; | |
2635b5c4 | 11153 | kvm_apic_set_irq(vcpu, &irq, NULL); |
557a961a | 11154 | } |
2635b5c4 | 11155 | |
e6d53e3b | 11156 | vcpu->arch.apf.halted = false; |
a4fa1635 | 11157 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
7c90705b GN |
11158 | } |
11159 | ||
557a961a VK |
11160 | void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu) |
11161 | { | |
11162 | kvm_make_request(KVM_REQ_APF_READY, vcpu); | |
11163 | if (!vcpu->arch.apf.pageready_pending) | |
11164 | kvm_vcpu_kick(vcpu); | |
11165 | } | |
11166 | ||
7c0ade6c | 11167 | bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu) |
7c90705b | 11168 | { |
2635b5c4 | 11169 | if (!kvm_pv_async_pf_enabled(vcpu)) |
7c90705b GN |
11170 | return true; |
11171 | else | |
2635b5c4 | 11172 | return apf_pageready_slot_free(vcpu); |
af585b92 GN |
11173 | } |
11174 | ||
5544eb9b PB |
11175 | void kvm_arch_start_assignment(struct kvm *kvm) |
11176 | { | |
11177 | atomic_inc(&kvm->arch.assigned_device_count); | |
11178 | } | |
11179 | EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); | |
11180 | ||
11181 | void kvm_arch_end_assignment(struct kvm *kvm) | |
11182 | { | |
11183 | atomic_dec(&kvm->arch.assigned_device_count); | |
11184 | } | |
11185 | EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); | |
11186 | ||
11187 | bool kvm_arch_has_assigned_device(struct kvm *kvm) | |
11188 | { | |
11189 | return atomic_read(&kvm->arch.assigned_device_count); | |
11190 | } | |
11191 | EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); | |
11192 | ||
e0f0bbc5 AW |
11193 | void kvm_arch_register_noncoherent_dma(struct kvm *kvm) |
11194 | { | |
11195 | atomic_inc(&kvm->arch.noncoherent_dma_count); | |
11196 | } | |
11197 | EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); | |
11198 | ||
11199 | void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) | |
11200 | { | |
11201 | atomic_dec(&kvm->arch.noncoherent_dma_count); | |
11202 | } | |
11203 | EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); | |
11204 | ||
11205 | bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) | |
11206 | { | |
11207 | return atomic_read(&kvm->arch.noncoherent_dma_count); | |
11208 | } | |
11209 | EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); | |
11210 | ||
14717e20 AW |
11211 | bool kvm_arch_has_irq_bypass(void) |
11212 | { | |
92735b1b | 11213 | return true; |
14717e20 AW |
11214 | } |
11215 | ||
87276880 FW |
11216 | int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, |
11217 | struct irq_bypass_producer *prod) | |
11218 | { | |
11219 | struct kvm_kernel_irqfd *irqfd = | |
11220 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
2edd9cb7 | 11221 | int ret; |
87276880 | 11222 | |
14717e20 | 11223 | irqfd->producer = prod; |
2edd9cb7 ZL |
11224 | kvm_arch_start_assignment(irqfd->kvm); |
11225 | ret = kvm_x86_ops.update_pi_irte(irqfd->kvm, | |
11226 | prod->irq, irqfd->gsi, 1); | |
11227 | ||
11228 | if (ret) | |
11229 | kvm_arch_end_assignment(irqfd->kvm); | |
87276880 | 11230 | |
2edd9cb7 | 11231 | return ret; |
87276880 FW |
11232 | } |
11233 | ||
11234 | void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, | |
11235 | struct irq_bypass_producer *prod) | |
11236 | { | |
11237 | int ret; | |
11238 | struct kvm_kernel_irqfd *irqfd = | |
11239 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
11240 | ||
87276880 FW |
11241 | WARN_ON(irqfd->producer != prod); |
11242 | irqfd->producer = NULL; | |
11243 | ||
11244 | /* | |
11245 | * When producer of consumer is unregistered, we change back to | |
11246 | * remapped mode, so we can re-use the current implementation | |
bb3541f1 | 11247 | * when the irq is masked/disabled or the consumer side (KVM |
87276880 FW |
11248 | * int this case doesn't want to receive the interrupts. |
11249 | */ | |
afaf0b2f | 11250 | ret = kvm_x86_ops.update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0); |
87276880 FW |
11251 | if (ret) |
11252 | printk(KERN_INFO "irq bypass consumer (token %p) unregistration" | |
11253 | " fails: %d\n", irqfd->consumer.token, ret); | |
2edd9cb7 ZL |
11254 | |
11255 | kvm_arch_end_assignment(irqfd->kvm); | |
87276880 FW |
11256 | } |
11257 | ||
11258 | int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, | |
11259 | uint32_t guest_irq, bool set) | |
11260 | { | |
afaf0b2f | 11261 | return kvm_x86_ops.update_pi_irte(kvm, host_irq, guest_irq, set); |
87276880 FW |
11262 | } |
11263 | ||
52004014 FW |
11264 | bool kvm_vector_hashing_enabled(void) |
11265 | { | |
11266 | return vector_hashing; | |
11267 | } | |
52004014 | 11268 | |
2d5ba19b MT |
11269 | bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) |
11270 | { | |
11271 | return (vcpu->arch.msr_kvm_poll_control & 1) == 0; | |
11272 | } | |
11273 | EXPORT_SYMBOL_GPL(kvm_arch_no_poll); | |
11274 | ||
841c2be0 ML |
11275 | |
11276 | int kvm_spec_ctrl_test_value(u64 value) | |
6441fa61 | 11277 | { |
841c2be0 ML |
11278 | /* |
11279 | * test that setting IA32_SPEC_CTRL to given value | |
11280 | * is allowed by the host processor | |
11281 | */ | |
6441fa61 | 11282 | |
841c2be0 ML |
11283 | u64 saved_value; |
11284 | unsigned long flags; | |
11285 | int ret = 0; | |
6441fa61 | 11286 | |
841c2be0 | 11287 | local_irq_save(flags); |
6441fa61 | 11288 | |
841c2be0 ML |
11289 | if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value)) |
11290 | ret = 1; | |
11291 | else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value)) | |
11292 | ret = 1; | |
11293 | else | |
11294 | wrmsrl(MSR_IA32_SPEC_CTRL, saved_value); | |
6441fa61 | 11295 | |
841c2be0 | 11296 | local_irq_restore(flags); |
6441fa61 | 11297 | |
841c2be0 | 11298 | return ret; |
6441fa61 | 11299 | } |
841c2be0 | 11300 | EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value); |
2d5ba19b | 11301 | |
89786147 MG |
11302 | void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code) |
11303 | { | |
11304 | struct x86_exception fault; | |
19cf4b7e PB |
11305 | u32 access = error_code & |
11306 | (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK); | |
89786147 MG |
11307 | |
11308 | if (!(error_code & PFERR_PRESENT_MASK) || | |
19cf4b7e | 11309 | vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, &fault) != UNMAPPED_GVA) { |
89786147 MG |
11310 | /* |
11311 | * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page | |
11312 | * tables probably do not match the TLB. Just proceed | |
11313 | * with the error code that the processor gave. | |
11314 | */ | |
11315 | fault.vector = PF_VECTOR; | |
11316 | fault.error_code_valid = true; | |
11317 | fault.error_code = error_code; | |
11318 | fault.nested_page_fault = false; | |
11319 | fault.address = gva; | |
11320 | } | |
11321 | vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault); | |
6441fa61 | 11322 | } |
89786147 | 11323 | EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error); |
2d5ba19b | 11324 | |
3f3393b3 BM |
11325 | /* |
11326 | * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns | |
11327 | * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value | |
11328 | * indicates whether exit to userspace is needed. | |
11329 | */ | |
11330 | int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, | |
11331 | struct x86_exception *e) | |
11332 | { | |
11333 | if (r == X86EMUL_PROPAGATE_FAULT) { | |
11334 | kvm_inject_emulated_page_fault(vcpu, e); | |
11335 | return 1; | |
11336 | } | |
11337 | ||
11338 | /* | |
11339 | * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED | |
11340 | * while handling a VMX instruction KVM could've handled the request | |
11341 | * correctly by exiting to userspace and performing I/O but there | |
11342 | * doesn't seem to be a real use-case behind such requests, just return | |
11343 | * KVM_EXIT_INTERNAL_ERROR for now. | |
11344 | */ | |
11345 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
11346 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
11347 | vcpu->run->internal.ndata = 0; | |
11348 | ||
11349 | return 0; | |
11350 | } | |
11351 | EXPORT_SYMBOL_GPL(kvm_handle_memory_failure); | |
11352 | ||
9715092f BM |
11353 | int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva) |
11354 | { | |
11355 | bool pcid_enabled; | |
11356 | struct x86_exception e; | |
11357 | unsigned i; | |
11358 | unsigned long roots_to_free = 0; | |
11359 | struct { | |
11360 | u64 pcid; | |
11361 | u64 gla; | |
11362 | } operand; | |
11363 | int r; | |
11364 | ||
11365 | r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); | |
11366 | if (r != X86EMUL_CONTINUE) | |
11367 | return kvm_handle_memory_failure(vcpu, r, &e); | |
11368 | ||
11369 | if (operand.pcid >> 12 != 0) { | |
11370 | kvm_inject_gp(vcpu, 0); | |
11371 | return 1; | |
11372 | } | |
11373 | ||
11374 | pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); | |
11375 | ||
11376 | switch (type) { | |
11377 | case INVPCID_TYPE_INDIV_ADDR: | |
11378 | if ((!pcid_enabled && (operand.pcid != 0)) || | |
11379 | is_noncanonical_address(operand.gla, vcpu)) { | |
11380 | kvm_inject_gp(vcpu, 0); | |
11381 | return 1; | |
11382 | } | |
11383 | kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); | |
11384 | return kvm_skip_emulated_instruction(vcpu); | |
11385 | ||
11386 | case INVPCID_TYPE_SINGLE_CTXT: | |
11387 | if (!pcid_enabled && (operand.pcid != 0)) { | |
11388 | kvm_inject_gp(vcpu, 0); | |
11389 | return 1; | |
11390 | } | |
11391 | ||
11392 | if (kvm_get_active_pcid(vcpu) == operand.pcid) { | |
11393 | kvm_mmu_sync_roots(vcpu); | |
11394 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); | |
11395 | } | |
11396 | ||
11397 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
11398 | if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].pgd) | |
11399 | == operand.pcid) | |
11400 | roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); | |
11401 | ||
11402 | kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free); | |
11403 | /* | |
11404 | * If neither the current cr3 nor any of the prev_roots use the | |
11405 | * given PCID, then nothing needs to be done here because a | |
11406 | * resync will happen anyway before switching to any other CR3. | |
11407 | */ | |
11408 | ||
11409 | return kvm_skip_emulated_instruction(vcpu); | |
11410 | ||
11411 | case INVPCID_TYPE_ALL_NON_GLOBAL: | |
11412 | /* | |
11413 | * Currently, KVM doesn't mark global entries in the shadow | |
11414 | * page tables, so a non-global flush just degenerates to a | |
11415 | * global flush. If needed, we could optimize this later by | |
11416 | * keeping track of global entries in shadow page tables. | |
11417 | */ | |
11418 | ||
11419 | fallthrough; | |
11420 | case INVPCID_TYPE_ALL_INCL_GLOBAL: | |
11421 | kvm_mmu_unload(vcpu); | |
11422 | return kvm_skip_emulated_instruction(vcpu); | |
11423 | ||
11424 | default: | |
11425 | BUG(); /* We have already checked above that type <= 3 */ | |
11426 | } | |
11427 | } | |
11428 | EXPORT_SYMBOL_GPL(kvm_handle_invpcid); | |
11429 | ||
8f423a80 TL |
11430 | static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu) |
11431 | { | |
11432 | struct kvm_run *run = vcpu->run; | |
11433 | struct kvm_mmio_fragment *frag; | |
11434 | unsigned int len; | |
11435 | ||
11436 | BUG_ON(!vcpu->mmio_needed); | |
11437 | ||
11438 | /* Complete previous fragment */ | |
11439 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; | |
11440 | len = min(8u, frag->len); | |
11441 | if (!vcpu->mmio_is_write) | |
11442 | memcpy(frag->data, run->mmio.data, len); | |
11443 | ||
11444 | if (frag->len <= 8) { | |
11445 | /* Switch to the next fragment. */ | |
11446 | frag++; | |
11447 | vcpu->mmio_cur_fragment++; | |
11448 | } else { | |
11449 | /* Go forward to the next mmio piece. */ | |
11450 | frag->data += len; | |
11451 | frag->gpa += len; | |
11452 | frag->len -= len; | |
11453 | } | |
11454 | ||
11455 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { | |
11456 | vcpu->mmio_needed = 0; | |
11457 | ||
11458 | // VMG change, at this point, we're always done | |
11459 | // RIP has already been advanced | |
11460 | return 1; | |
11461 | } | |
11462 | ||
11463 | // More MMIO is needed | |
11464 | run->mmio.phys_addr = frag->gpa; | |
11465 | run->mmio.len = min(8u, frag->len); | |
11466 | run->mmio.is_write = vcpu->mmio_is_write; | |
11467 | if (run->mmio.is_write) | |
11468 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); | |
11469 | run->exit_reason = KVM_EXIT_MMIO; | |
11470 | ||
11471 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
11472 | ||
11473 | return 0; | |
11474 | } | |
11475 | ||
11476 | int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, | |
11477 | void *data) | |
11478 | { | |
11479 | int handled; | |
11480 | struct kvm_mmio_fragment *frag; | |
11481 | ||
11482 | if (!data) | |
11483 | return -EINVAL; | |
11484 | ||
11485 | handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data); | |
11486 | if (handled == bytes) | |
11487 | return 1; | |
11488 | ||
11489 | bytes -= handled; | |
11490 | gpa += handled; | |
11491 | data += handled; | |
11492 | ||
11493 | /*TODO: Check if need to increment number of frags */ | |
11494 | frag = vcpu->mmio_fragments; | |
11495 | vcpu->mmio_nr_fragments = 1; | |
11496 | frag->len = bytes; | |
11497 | frag->gpa = gpa; | |
11498 | frag->data = data; | |
11499 | ||
11500 | vcpu->mmio_needed = 1; | |
11501 | vcpu->mmio_cur_fragment = 0; | |
11502 | ||
11503 | vcpu->run->mmio.phys_addr = gpa; | |
11504 | vcpu->run->mmio.len = min(8u, frag->len); | |
11505 | vcpu->run->mmio.is_write = 1; | |
11506 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); | |
11507 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
11508 | ||
11509 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
11510 | ||
11511 | return 0; | |
11512 | } | |
11513 | EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write); | |
11514 | ||
11515 | int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, | |
11516 | void *data) | |
11517 | { | |
11518 | int handled; | |
11519 | struct kvm_mmio_fragment *frag; | |
11520 | ||
11521 | if (!data) | |
11522 | return -EINVAL; | |
11523 | ||
11524 | handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data); | |
11525 | if (handled == bytes) | |
11526 | return 1; | |
11527 | ||
11528 | bytes -= handled; | |
11529 | gpa += handled; | |
11530 | data += handled; | |
11531 | ||
11532 | /*TODO: Check if need to increment number of frags */ | |
11533 | frag = vcpu->mmio_fragments; | |
11534 | vcpu->mmio_nr_fragments = 1; | |
11535 | frag->len = bytes; | |
11536 | frag->gpa = gpa; | |
11537 | frag->data = data; | |
11538 | ||
11539 | vcpu->mmio_needed = 1; | |
11540 | vcpu->mmio_cur_fragment = 0; | |
11541 | ||
11542 | vcpu->run->mmio.phys_addr = gpa; | |
11543 | vcpu->run->mmio.len = min(8u, frag->len); | |
11544 | vcpu->run->mmio.is_write = 0; | |
11545 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
11546 | ||
11547 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
11548 | ||
11549 | return 0; | |
11550 | } | |
11551 | EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read); | |
11552 | ||
7ed9abfe TL |
11553 | static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu) |
11554 | { | |
11555 | memcpy(vcpu->arch.guest_ins_data, vcpu->arch.pio_data, | |
11556 | vcpu->arch.pio.count * vcpu->arch.pio.size); | |
11557 | vcpu->arch.pio.count = 0; | |
11558 | ||
11559 | return 1; | |
11560 | } | |
11561 | ||
11562 | static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, | |
11563 | unsigned int port, void *data, unsigned int count) | |
11564 | { | |
11565 | int ret; | |
11566 | ||
11567 | ret = emulator_pio_out_emulated(vcpu->arch.emulate_ctxt, size, port, | |
11568 | data, count); | |
11569 | if (ret) | |
11570 | return ret; | |
11571 | ||
11572 | vcpu->arch.pio.count = 0; | |
11573 | ||
11574 | return 0; | |
11575 | } | |
11576 | ||
11577 | static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, | |
11578 | unsigned int port, void *data, unsigned int count) | |
11579 | { | |
11580 | int ret; | |
11581 | ||
11582 | ret = emulator_pio_in_emulated(vcpu->arch.emulate_ctxt, size, port, | |
11583 | data, count); | |
11584 | if (ret) { | |
11585 | vcpu->arch.pio.count = 0; | |
11586 | } else { | |
11587 | vcpu->arch.guest_ins_data = data; | |
11588 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins; | |
11589 | } | |
11590 | ||
11591 | return 0; | |
11592 | } | |
11593 | ||
11594 | int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size, | |
11595 | unsigned int port, void *data, unsigned int count, | |
11596 | int in) | |
11597 | { | |
11598 | return in ? kvm_sev_es_ins(vcpu, size, port, data, count) | |
11599 | : kvm_sev_es_outs(vcpu, size, port, data, count); | |
11600 | } | |
11601 | EXPORT_SYMBOL_GPL(kvm_sev_es_string_io); | |
11602 | ||
d95df951 | 11603 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry); |
229456fc | 11604 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
931c33b1 | 11605 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); |
229456fc MT |
11606 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); |
11607 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
11608 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
11609 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
0ac406de | 11610 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); |
d8cabddf | 11611 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 11612 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 11613 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
5497b955 | 11614 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); |
ec1ff790 | 11615 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 11616 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |
2e554e8d | 11617 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); |
489223ed | 11618 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); |
4f75bcc3 | 11619 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); |
843e4330 | 11620 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); |
efc64404 | 11621 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); |
18f40c53 SS |
11622 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); |
11623 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); | |
ab56f8e6 | 11624 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log); |
24bbf74c | 11625 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request); |
d523ab6b TL |
11626 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter); |
11627 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit); | |
59e38b58 TL |
11628 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter); |
11629 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit); |