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KVM: SVM: implement dedicated INTR exit handler
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Avi Kivity <avi@qumranet.com>
10 * Yaniv Kamay <yaniv@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16
edf88417 17#include <linux/kvm_host.h>
313a3dc7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
7837699f 20#include "i8254.h"
37817f29 21#include "tss.h"
313a3dc7 22
18068523 23#include <linux/clocksource.h>
313a3dc7
CO		 24#include <linux/kvm.h>
25#include <linux/fs.h>
26#include <linux/vmalloc.h>
5fb76f9b 27#include <linux/module.h>
0de10343 28#include <linux/mman.h>
2bacc55c 29#include <linux/highmem.h>
043405e1
CO		 30
31#include <asm/uaccess.h>
d825ed0a 32#include <asm/msr.h>
a5f61300 33#include <asm/desc.h>
043405e1 34
313a3dc7 35#define MAX_IO_MSRS 256
a03490ed
CO		 36#define CR0_RESERVED_BITS \
37 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
38 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
39 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
40#define CR4_RESERVED_BITS \
41 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
42 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
43 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
44 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
45
46#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
50a37eb4
JR		 47/* EFER defaults:
48 * - enable syscall per default because its emulated by KVM
49 * - enable LME and LMA per default on 64 bit KVM
50 */
51#ifdef CONFIG_X86_64
52static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
53#else
54static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
55#endif
313a3dc7 56
ba1389b7
AK		 57#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
58#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 59
674eea0f
AK		 60static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
61 struct kvm_cpuid_entry2 __user *entries);
62
97896d04
ZX		 63struct kvm_x86_ops *kvm_x86_ops;
64
417bc304 65struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 66 { "pf_fixed", VCPU_STAT(pf_fixed) },
67 { "pf_guest", VCPU_STAT(pf_guest) },
68 { "tlb_flush", VCPU_STAT(tlb_flush) },
69 { "invlpg", VCPU_STAT(invlpg) },
70 { "exits", VCPU_STAT(exits) },
71 { "io_exits", VCPU_STAT(io_exits) },
72 { "mmio_exits", VCPU_STAT(mmio_exits) },
73 { "signal_exits", VCPU_STAT(signal_exits) },
74 { "irq_window", VCPU_STAT(irq_window_exits) },
75 { "halt_exits", VCPU_STAT(halt_exits) },
76 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 77 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 78 { "request_irq", VCPU_STAT(request_irq_exits) },
79 { "irq_exits", VCPU_STAT(irq_exits) },
80 { "host_state_reload", VCPU_STAT(host_state_reload) },
81 { "efer_reload", VCPU_STAT(efer_reload) },
82 { "fpu_reload", VCPU_STAT(fpu_reload) },
83 { "insn_emulation", VCPU_STAT(insn_emulation) },
84 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
4cee5764
AK		 85 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
86 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
87 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
88 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
89 { "mmu_flooded", VM_STAT(mmu_flooded) },
90 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 91 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
0f74a24c 92 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 93 { "largepages", VM_STAT(lpages) },
417bc304
HB		 94 { NULL }
95};
96
97
5fb76f9b
CO		 98unsigned long segment_base(u16 selector)
99{
100 struct descriptor_table gdt;
a5f61300 101 struct desc_struct *d;
5fb76f9b
CO		 102 unsigned long table_base;
103 unsigned long v;
104
105 if (selector == 0)
106 return 0;
107
108 asm("sgdt %0" : "=m"(gdt));
109 table_base = gdt.base;
110
111 if (selector & 4) { /* from ldt */
112 u16 ldt_selector;
113
114 asm("sldt %0" : "=g"(ldt_selector));
115 table_base = segment_base(ldt_selector);
116 }
a5f61300
AK		 117 d = (struct desc_struct *)(table_base + (selector & ~7));
118 v = d->base0 | ((unsigned long)d->base1 << 16) |
119 ((unsigned long)d->base2 << 24);
5fb76f9b 120#ifdef CONFIG_X86_64
a5f61300
AK		 121 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
122 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 123#endif
124 return v;
125}
126EXPORT_SYMBOL_GPL(segment_base);
127
6866b83e
CO		 128u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
129{
130 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 131 return vcpu->arch.apic_base;
6866b83e 132 else
ad312c7c 133 return vcpu->arch.apic_base;
6866b83e
CO		 134}
135EXPORT_SYMBOL_GPL(kvm_get_apic_base);
136
137void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
138{
139 /* TODO: reserve bits check */
140 if (irqchip_in_kernel(vcpu->kvm))
141 kvm_lapic_set_base(vcpu, data);
142 else
ad312c7c 143 vcpu->arch.apic_base = data;
6866b83e
CO		 144}
145EXPORT_SYMBOL_GPL(kvm_set_apic_base);
146
298101da
AK		 147void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
148{
ad312c7c
ZX		 149 WARN_ON(vcpu->arch.exception.pending);
150 vcpu->arch.exception.pending = true;
151 vcpu->arch.exception.has_error_code = false;
152 vcpu->arch.exception.nr = nr;
298101da
AK		 153}
154EXPORT_SYMBOL_GPL(kvm_queue_exception);
155
c3c91fee
AK		 156void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
157 u32 error_code)
158{
159 ++vcpu->stat.pf_guest;
71c4dfaf
JR		 160 if (vcpu->arch.exception.pending) {
161 if (vcpu->arch.exception.nr == PF_VECTOR) {
162 printk(KERN_DEBUG "kvm: inject_page_fault:"
163 " double fault 0x%lx\n", addr);
164 vcpu->arch.exception.nr = DF_VECTOR;
165 vcpu->arch.exception.error_code = 0;
166 } else if (vcpu->arch.exception.nr == DF_VECTOR) {
167 /* triple fault -> shutdown */
168 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
169 }
c3c91fee
AK		 170 return;
171 }
ad312c7c 172 vcpu->arch.cr2 = addr;
c3c91fee
AK		 173 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
174}
175
298101da
AK		 176void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
177{
ad312c7c
ZX		 178 WARN_ON(vcpu->arch.exception.pending);
179 vcpu->arch.exception.pending = true;
180 vcpu->arch.exception.has_error_code = true;
181 vcpu->arch.exception.nr = nr;
182 vcpu->arch.exception.error_code = error_code;
298101da
AK		 183}
184EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
185
186static void __queue_exception(struct kvm_vcpu *vcpu)
187{
ad312c7c
ZX		 188 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
189 vcpu->arch.exception.has_error_code,
190 vcpu->arch.exception.error_code);
298101da
AK		 191}
192
a03490ed
CO		 193/*
194 * Load the pae pdptrs. Return true is they are all valid.
195 */
196int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
197{
198 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
199 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
200 int i;
201 int ret;
ad312c7c 202 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 203
a03490ed
CO		 204 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
205 offset * sizeof(u64), sizeof(pdpte));
206 if (ret < 0) {
207 ret = 0;
208 goto out;
209 }
210 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
211 if ((pdpte[i] & 1) && (pdpte[i] & 0xfffffff0000001e6ull)) {
212 ret = 0;
213 goto out;
214 }
215 }
216 ret = 1;
217
ad312c7c 218 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
a03490ed 219out:
a03490ed
CO		 220
221 return ret;
222}
cc4b6871 223EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 224
d835dfec
AK		 225static bool pdptrs_changed(struct kvm_vcpu *vcpu)
226{
ad312c7c 227 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 228 bool changed = true;
229 int r;
230
231 if (is_long_mode(vcpu) || !is_pae(vcpu))
232 return false;
233
ad312c7c 234 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 235 if (r < 0)
236 goto out;
ad312c7c 237 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 238out:
d835dfec
AK		 239
240 return changed;
241}
242
2d3ad1f4 243void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 244{
245 if (cr0 & CR0_RESERVED_BITS) {
246 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 247 cr0, vcpu->arch.cr0);
c1a5d4f9 248 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 249 return;
250 }
251
252 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
253 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 254 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 255 return;
256 }
257
258 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
259 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
260 "and a clear PE flag\n");
c1a5d4f9 261 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 262 return;
263 }
264
265 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
266#ifdef CONFIG_X86_64
ad312c7c 267 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 268 int cs_db, cs_l;
269
270 if (!is_pae(vcpu)) {
271 printk(KERN_DEBUG "set_cr0: #GP, start paging "
272 "in long mode while PAE is disabled\n");
c1a5d4f9 273 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 274 return;
275 }
276 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
277 if (cs_l) {
278 printk(KERN_DEBUG "set_cr0: #GP, start paging "
279 "in long mode while CS.L == 1\n");
c1a5d4f9 280 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 281 return;
282
283 }
284 } else
285#endif
ad312c7c 286 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 287 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
288 "reserved bits\n");
c1a5d4f9 289 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 290 return;
291 }
292
293 }
294
295 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 296 vcpu->arch.cr0 = cr0;
a03490ed 297
a03490ed 298 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 299 return;
300}
2d3ad1f4 301EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 302
2d3ad1f4 303void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 304{
2d3ad1f4 305 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
2714d1d3
FEL		 306 KVMTRACE_1D(LMSW, vcpu,
307 (u32)((vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f)),
308 handler);
a03490ed 309}
2d3ad1f4 310EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 311
2d3ad1f4 312void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed
CO		 313{
314 if (cr4 & CR4_RESERVED_BITS) {
315 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 316 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 317 return;
318 }
319
320 if (is_long_mode(vcpu)) {
321 if (!(cr4 & X86_CR4_PAE)) {
322 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
323 "in long mode\n");
c1a5d4f9 324 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 325 return;
326 }
327 } else if (is_paging(vcpu) && !is_pae(vcpu) && (cr4 & X86_CR4_PAE)
ad312c7c 328 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 329 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 330 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 331 return;
332 }
333
334 if (cr4 & X86_CR4_VMXE) {
335 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 336 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 337 return;
338 }
339 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 340 vcpu->arch.cr4 = cr4;
a03490ed 341 kvm_mmu_reset_context(vcpu);
a03490ed 342}
2d3ad1f4 343EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 344
2d3ad1f4 345void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 346{
ad312c7c 347 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
d835dfec
AK		 348 kvm_mmu_flush_tlb(vcpu);
349 return;
350 }
351
a03490ed
CO		 352 if (is_long_mode(vcpu)) {
353 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
354 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 355 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 356 return;
357 }
358 } else {
359 if (is_pae(vcpu)) {
360 if (cr3 & CR3_PAE_RESERVED_BITS) {
361 printk(KERN_DEBUG
362 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 363 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 364 return;
365 }
366 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
367 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
368 "reserved bits\n");
c1a5d4f9 369 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 370 return;
371 }
372 }
373 /*
374 * We don't check reserved bits in nonpae mode, because
375 * this isn't enforced, and VMware depends on this.
376 */
377 }
378
a03490ed
CO		 379 /*
380 * Does the new cr3 value map to physical memory? (Note, we
381 * catch an invalid cr3 even in real-mode, because it would
382 * cause trouble later on when we turn on paging anyway.)
383 *
384 * A real CPU would silently accept an invalid cr3 and would
385 * attempt to use it - with largely undefined (and often hard
386 * to debug) behavior on the guest side.
387 */
388 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 389 kvm_inject_gp(vcpu, 0);
a03490ed 390 else {
ad312c7c
ZX		 391 vcpu->arch.cr3 = cr3;
392 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 393 }
a03490ed 394}
2d3ad1f4 395EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 396
2d3ad1f4 397void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 398{
399 if (cr8 & CR8_RESERVED_BITS) {
400 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 401 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 402 return;
403 }
404 if (irqchip_in_kernel(vcpu->kvm))
405 kvm_lapic_set_tpr(vcpu, cr8);
406 else
ad312c7c 407 vcpu->arch.cr8 = cr8;
a03490ed 408}
2d3ad1f4 409EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 410
2d3ad1f4 411unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 412{
413 if (irqchip_in_kernel(vcpu->kvm))
414 return kvm_lapic_get_cr8(vcpu);
415 else
ad312c7c 416 return vcpu->arch.cr8;
a03490ed 417}
2d3ad1f4 418EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 419
043405e1
CO		 420/*
421 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
422 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
423 *
424 * This list is modified at module load time to reflect the
425 * capabilities of the host cpu.
426 */
427static u32 msrs_to_save[] = {
428 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
429 MSR_K6_STAR,
430#ifdef CONFIG_X86_64
431 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
432#endif
18068523 433 MSR_IA32_TIME_STAMP_COUNTER, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
847f0ad8 434 MSR_IA32_PERF_STATUS,
043405e1
CO		 435};
436
437static unsigned num_msrs_to_save;
438
439static u32 emulated_msrs[] = {
440 MSR_IA32_MISC_ENABLE,
441};
442
15c4a640
CO		 443static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
444{
f2b4b7dd 445 if (efer & efer_reserved_bits) {
15c4a640
CO		 446 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
447 efer);
c1a5d4f9 448 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 449 return;
450 }
451
452 if (is_paging(vcpu)
ad312c7c 453 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 454 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 455 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 456 return;
457 }
458
459 kvm_x86_ops->set_efer(vcpu, efer);
460
461 efer &= ~EFER_LMA;
ad312c7c 462 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 463
ad312c7c 464 vcpu->arch.shadow_efer = efer;
15c4a640
CO		 465}
466
f2b4b7dd
JR		 467void kvm_enable_efer_bits(u64 mask)
468{
469 efer_reserved_bits &= ~mask;
470}
471EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
472
473
15c4a640
CO		 474/*
475 * Writes msr value into into the appropriate "register".
476 * Returns 0 on success, non-0 otherwise.
477 * Assumes vcpu_load() was already called.
478 */
479int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
480{
481 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
482}
483
313a3dc7
CO		 484/*
485 * Adapt set_msr() to msr_io()'s calling convention
486 */
487static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
488{
489 return kvm_set_msr(vcpu, index, *data);
490}
491
18068523
GOC		 492static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
493{
494 static int version;
50d0a0f9
GH		 495 struct pvclock_wall_clock wc;
496 struct timespec now, sys, boot;
18068523
GOC		 497
498 if (!wall_clock)
499 return;
500
501 version++;
502
18068523
GOC		 503 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
504
50d0a0f9
GH		 505 /*
506 * The guest calculates current wall clock time by adding
507 * system time (updated by kvm_write_guest_time below) to the
508 * wall clock specified here. guest system time equals host
509 * system time for us, thus we must fill in host boot time here.
510 */
511 now = current_kernel_time();
512 ktime_get_ts(&sys);
513 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
514
515 wc.sec = boot.tv_sec;
516 wc.nsec = boot.tv_nsec;
517 wc.version = version;
18068523
GOC		 518
519 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
520
521 version++;
522 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 523}
524
50d0a0f9
GH		 525static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
526{
527 uint32_t quotient, remainder;
528
529 /* Don't try to replace with do_div(), this one calculates
530 * "(dividend << 32) / divisor" */
531 __asm__ ( "divl %4"
532 : "=a" (quotient), "=d" (remainder)
533 : "0" (0), "1" (dividend), "r" (divisor) );
534 return quotient;
535}
536
537static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
538{
539 uint64_t nsecs = 1000000000LL;
540 int32_t shift = 0;
541 uint64_t tps64;
542 uint32_t tps32;
543
544 tps64 = tsc_khz * 1000LL;
545 while (tps64 > nsecs*2) {
546 tps64 >>= 1;
547 shift--;
548 }
549
550 tps32 = (uint32_t)tps64;
551 while (tps32 <= (uint32_t)nsecs) {
552 tps32 <<= 1;
553 shift++;
554 }
555
556 hv_clock->tsc_shift = shift;
557 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
558
559 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
560 __FUNCTION__, tsc_khz, hv_clock->tsc_shift,
561 hv_clock->tsc_to_system_mul);
562}
563
18068523
GOC		 564static void kvm_write_guest_time(struct kvm_vcpu *v)
565{
566 struct timespec ts;
567 unsigned long flags;
568 struct kvm_vcpu_arch *vcpu = &v->arch;
569 void *shared_kaddr;
570
571 if ((!vcpu->time_page))
572 return;
573
50d0a0f9
GH		 574 if (unlikely(vcpu->hv_clock_tsc_khz != tsc_khz)) {
575 kvm_set_time_scale(tsc_khz, &vcpu->hv_clock);
576 vcpu->hv_clock_tsc_khz = tsc_khz;
577 }
578
18068523
GOC		 579 /* Keep irq disabled to prevent changes to the clock */
580 local_irq_save(flags);
581 kvm_get_msr(v, MSR_IA32_TIME_STAMP_COUNTER,
582 &vcpu->hv_clock.tsc_timestamp);
583 ktime_get_ts(&ts);
584 local_irq_restore(flags);
585
586 /* With all the info we got, fill in the values */
587
588 vcpu->hv_clock.system_time = ts.tv_nsec +
589 (NSEC_PER_SEC * (u64)ts.tv_sec);
590 /*
591 * The interface expects us to write an even number signaling that the
592 * update is finished. Since the guest won't see the intermediate
50d0a0f9 593 * state, we just increase by 2 at the end.
18068523 594 */
50d0a0f9 595 vcpu->hv_clock.version += 2;
18068523
GOC		 596
597 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
598
599 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 600 sizeof(vcpu->hv_clock));
18068523
GOC		 601
602 kunmap_atomic(shared_kaddr, KM_USER0);
603
604 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
605}
606
15c4a640
CO		 607
608int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
609{
610 switch (msr) {
15c4a640
CO		 611 case MSR_EFER:
612 set_efer(vcpu, data);
613 break;
15c4a640
CO		 614 case MSR_IA32_MC0_STATUS:
615 pr_unimpl(vcpu, "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n",
b8688d51 616 __func__, data);
15c4a640
CO		 617 break;
618 case MSR_IA32_MCG_STATUS:
619 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_STATUS 0x%llx, nop\n",
b8688d51 620 __func__, data);
15c4a640 621 break;
c7ac679c
JR		 622 case MSR_IA32_MCG_CTL:
623 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_CTL 0x%llx, nop\n",
b8688d51 624 __func__, data);
c7ac679c 625 break;
15c4a640
CO		 626 case MSR_IA32_UCODE_REV:
627 case MSR_IA32_UCODE_WRITE:
628 case 0x200 ... 0x2ff: /* MTRRs */
629 break;
630 case MSR_IA32_APICBASE:
631 kvm_set_apic_base(vcpu, data);
632 break;
633 case MSR_IA32_MISC_ENABLE:
ad312c7c 634 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 635 break;
18068523
GOC		 636 case MSR_KVM_WALL_CLOCK:
637 vcpu->kvm->arch.wall_clock = data;
638 kvm_write_wall_clock(vcpu->kvm, data);
639 break;
640 case MSR_KVM_SYSTEM_TIME: {
641 if (vcpu->arch.time_page) {
642 kvm_release_page_dirty(vcpu->arch.time_page);
643 vcpu->arch.time_page = NULL;
644 }
645
646 vcpu->arch.time = data;
647
648 /* we verify if the enable bit is set... */
649 if (!(data & 1))
650 break;
651
652 /* ...but clean it before doing the actual write */
653 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
654
18068523 655 down_read(&current->mm->mmap_sem);
18068523
GOC		 656 vcpu->arch.time_page =
657 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 658 up_read(&current->mm->mmap_sem);
659
660 if (is_error_page(vcpu->arch.time_page)) {
661 kvm_release_page_clean(vcpu->arch.time_page);
662 vcpu->arch.time_page = NULL;
663 }
664
665 kvm_write_guest_time(vcpu);
666 break;
667 }
15c4a640 668 default:
565f1fbd 669 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", msr, data);
15c4a640
CO		 670 return 1;
671 }
672 return 0;
673}
674EXPORT_SYMBOL_GPL(kvm_set_msr_common);
675
676
677/*
678 * Reads an msr value (of 'msr_index') into 'pdata'.
679 * Returns 0 on success, non-0 otherwise.
680 * Assumes vcpu_load() was already called.
681 */
682int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
683{
684 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
685}
686
687int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
688{
689 u64 data;
690
691 switch (msr) {
692 case 0xc0010010: /* SYSCFG */
693 case 0xc0010015: /* HWCR */
694 case MSR_IA32_PLATFORM_ID:
695 case MSR_IA32_P5_MC_ADDR:
696 case MSR_IA32_P5_MC_TYPE:
697 case MSR_IA32_MC0_CTL:
698 case MSR_IA32_MCG_STATUS:
699 case MSR_IA32_MCG_CAP:
c7ac679c 700 case MSR_IA32_MCG_CTL:
15c4a640
CO		 701 case MSR_IA32_MC0_MISC:
702 case MSR_IA32_MC0_MISC+4:
703 case MSR_IA32_MC0_MISC+8:
704 case MSR_IA32_MC0_MISC+12:
705 case MSR_IA32_MC0_MISC+16:
706 case MSR_IA32_UCODE_REV:
15c4a640
CO		 707 case MSR_IA32_EBL_CR_POWERON:
708 /* MTRR registers */
709 case 0xfe:
710 case 0x200 ... 0x2ff:
711 data = 0;
712 break;
713 case 0xcd: /* fsb frequency */
714 data = 3;
715 break;
716 case MSR_IA32_APICBASE:
717 data = kvm_get_apic_base(vcpu);
718 break;
719 case MSR_IA32_MISC_ENABLE:
ad312c7c 720 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 721 break;
847f0ad8
AG		 722 case MSR_IA32_PERF_STATUS:
723 /* TSC increment by tick */
724 data = 1000ULL;
725 /* CPU multiplier */
726 data |= (((uint64_t)4ULL) << 40);
727 break;
15c4a640 728 case MSR_EFER:
ad312c7c 729 data = vcpu->arch.shadow_efer;
15c4a640 730 break;
18068523
GOC		 731 case MSR_KVM_WALL_CLOCK:
732 data = vcpu->kvm->arch.wall_clock;
733 break;
734 case MSR_KVM_SYSTEM_TIME:
735 data = vcpu->arch.time;
736 break;
15c4a640
CO		 737 default:
738 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
739 return 1;
740 }
741 *pdata = data;
742 return 0;
743}
744EXPORT_SYMBOL_GPL(kvm_get_msr_common);
745
313a3dc7
CO		 746/*
747 * Read or write a bunch of msrs. All parameters are kernel addresses.
748 *
749 * @return number of msrs set successfully.
750 */
751static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
752 struct kvm_msr_entry *entries,
753 int (*do_msr)(struct kvm_vcpu *vcpu,
754 unsigned index, u64 *data))
755{
756 int i;
757
758 vcpu_load(vcpu);
759
3200f405 760 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 761 for (i = 0; i < msrs->nmsrs; ++i)
762 if (do_msr(vcpu, entries[i].index, &entries[i].data))
763 break;
3200f405 764 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 765
766 vcpu_put(vcpu);
767
768 return i;
769}
770
771/*
772 * Read or write a bunch of msrs. Parameters are user addresses.
773 *
774 * @return number of msrs set successfully.
775 */
776static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
777 int (*do_msr)(struct kvm_vcpu *vcpu,
778 unsigned index, u64 *data),
779 int writeback)
780{
781 struct kvm_msrs msrs;
782 struct kvm_msr_entry *entries;
783 int r, n;
784 unsigned size;
785
786 r = -EFAULT;
787 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
788 goto out;
789
790 r = -E2BIG;
791 if (msrs.nmsrs >= MAX_IO_MSRS)
792 goto out;
793
794 r = -ENOMEM;
795 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
796 entries = vmalloc(size);
797 if (!entries)
798 goto out;
799
800 r = -EFAULT;
801 if (copy_from_user(entries, user_msrs->entries, size))
802 goto out_free;
803
804 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
805 if (r < 0)
806 goto out_free;
807
808 r = -EFAULT;
809 if (writeback && copy_to_user(user_msrs->entries, entries, size))
810 goto out_free;
811
812 r = n;
813
814out_free:
815 vfree(entries);
816out:
817 return r;
818}
819
e9b11c17
ZX		 820/*
821 * Make sure that a cpu that is being hot-unplugged does not have any vcpus
822 * cached on it.
823 */
824void decache_vcpus_on_cpu(int cpu)
825{
826 struct kvm *vm;
827 struct kvm_vcpu *vcpu;
828 int i;
829
830 spin_lock(&kvm_lock);
831 list_for_each_entry(vm, &vm_list, vm_list)
832 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
833 vcpu = vm->vcpus[i];
834 if (!vcpu)
835 continue;
836 /*
837 * If the vcpu is locked, then it is running on some
838 * other cpu and therefore it is not cached on the
839 * cpu in question.
840 *
841 * If it's not locked, check the last cpu it executed
842 * on.
843 */
844 if (mutex_trylock(&vcpu->mutex)) {
845 if (vcpu->cpu == cpu) {
846 kvm_x86_ops->vcpu_decache(vcpu);
847 vcpu->cpu = -1;
848 }
849 mutex_unlock(&vcpu->mutex);
850 }
851 }
852 spin_unlock(&kvm_lock);
853}
854
018d00d2
ZX		 855int kvm_dev_ioctl_check_extension(long ext)
856{
857 int r;
858
859 switch (ext) {
860 case KVM_CAP_IRQCHIP:
861 case KVM_CAP_HLT:
862 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
863 case KVM_CAP_USER_MEMORY:
864 case KVM_CAP_SET_TSS_ADDR:
07716717 865 case KVM_CAP_EXT_CPUID:
18068523 866 case KVM_CAP_CLOCKSOURCE:
7837699f 867 case KVM_CAP_PIT:
a28e4f5a 868 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 869 case KVM_CAP_MP_STATE:
018d00d2
ZX		 870 r = 1;
871 break;
774ead3a
AK		 872 case KVM_CAP_VAPIC:
873 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
874 break;
f725230a
AK		 875 case KVM_CAP_NR_VCPUS:
876 r = KVM_MAX_VCPUS;
877 break;
a988b910
AK		 878 case KVM_CAP_NR_MEMSLOTS:
879 r = KVM_MEMORY_SLOTS;
880 break;
2f333bcb
MT		 881 case KVM_CAP_PV_MMU:
882 r = !tdp_enabled;
883 break;
018d00d2
ZX		 884 default:
885 r = 0;
886 break;
887 }
888 return r;
889
890}
891
043405e1
CO		 892long kvm_arch_dev_ioctl(struct file *filp,
893 unsigned int ioctl, unsigned long arg)
894{
895 void __user *argp = (void __user *)arg;
896 long r;
897
898 switch (ioctl) {
899 case KVM_GET_MSR_INDEX_LIST: {
900 struct kvm_msr_list __user *user_msr_list = argp;
901 struct kvm_msr_list msr_list;
902 unsigned n;
903
904 r = -EFAULT;
905 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
906 goto out;
907 n = msr_list.nmsrs;
908 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
909 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
910 goto out;
911 r = -E2BIG;
912 if (n < num_msrs_to_save)
913 goto out;
914 r = -EFAULT;
915 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
916 num_msrs_to_save * sizeof(u32)))
917 goto out;
918 if (copy_to_user(user_msr_list->indices
919 + num_msrs_to_save * sizeof(u32),
920 &emulated_msrs,
921 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
922 goto out;
923 r = 0;
924 break;
925 }
674eea0f
AK		 926 case KVM_GET_SUPPORTED_CPUID: {
927 struct kvm_cpuid2 __user *cpuid_arg = argp;
928 struct kvm_cpuid2 cpuid;
929
930 r = -EFAULT;
931 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
932 goto out;
933 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
934 cpuid_arg->entries);
935 if (r)
936 goto out;
937
938 r = -EFAULT;
939 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
940 goto out;
941 r = 0;
942 break;
943 }
043405e1
CO		 944 default:
945 r = -EINVAL;
946 }
947out:
948 return r;
949}
950
313a3dc7
CO		 951void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
952{
953 kvm_x86_ops->vcpu_load(vcpu, cpu);
18068523 954 kvm_write_guest_time(vcpu);
313a3dc7
CO		 955}
956
957void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
958{
959 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 960 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 961}
962
07716717 963static int is_efer_nx(void)
313a3dc7
CO		 964{
965 u64 efer;
313a3dc7
CO		 966
967 rdmsrl(MSR_EFER, efer);
07716717
DK		 968 return efer & EFER_NX;
969}
970
971static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
972{
973 int i;
974 struct kvm_cpuid_entry2 *e, *entry;
975
313a3dc7 976 entry = NULL;
ad312c7c
ZX		 977 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
978 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 979 if (e->function == 0x80000001) {
980 entry = e;
981 break;
982 }
983 }
07716717 984 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 985 entry->edx &= ~(1 << 20);
986 printk(KERN_INFO "kvm: guest NX capability removed\n");
987 }
988}
989
07716717 990/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 991static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
992 struct kvm_cpuid *cpuid,
993 struct kvm_cpuid_entry __user *entries)
07716717
DK		 994{
995 int r, i;
996 struct kvm_cpuid_entry *cpuid_entries;
997
998 r = -E2BIG;
999 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1000 goto out;
1001 r = -ENOMEM;
1002 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1003 if (!cpuid_entries)
1004 goto out;
1005 r = -EFAULT;
1006 if (copy_from_user(cpuid_entries, entries,
1007 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1008 goto out_free;
1009 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1010 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1011 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1012 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1013 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1014 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1015 vcpu->arch.cpuid_entries[i].index = 0;
1016 vcpu->arch.cpuid_entries[i].flags = 0;
1017 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1018 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1019 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1020 }
1021 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1022 cpuid_fix_nx_cap(vcpu);
1023 r = 0;
1024
1025out_free:
1026 vfree(cpuid_entries);
1027out:
1028 return r;
1029}
1030
1031static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
1032 struct kvm_cpuid2 *cpuid,
1033 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1034{
1035 int r;
1036
1037 r = -E2BIG;
1038 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1039 goto out;
1040 r = -EFAULT;
ad312c7c 1041 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1042 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1043 goto out;
ad312c7c 1044 vcpu->arch.cpuid_nent = cpuid->nent;
313a3dc7
CO		 1045 return 0;
1046
1047out:
1048 return r;
1049}
1050
07716717
DK		 1051static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
1052 struct kvm_cpuid2 *cpuid,
1053 struct kvm_cpuid_entry2 __user *entries)
1054{
1055 int r;
1056
1057 r = -E2BIG;
ad312c7c 1058 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1059 goto out;
1060 r = -EFAULT;
ad312c7c
ZX		 1061 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
1062 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1063 goto out;
1064 return 0;
1065
1066out:
ad312c7c 1067 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1068 return r;
1069}
1070
1071static inline u32 bit(int bitno)
1072{
1073 return 1 << (bitno & 31);
1074}
1075
1076static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1077 u32 index)
1078{
1079 entry->function = function;
1080 entry->index = index;
1081 cpuid_count(entry->function, entry->index,
1082 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
1083 entry->flags = 0;
1084}
1085
1086static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1087 u32 index, int *nent, int maxnent)
1088{
1089 const u32 kvm_supported_word0_x86_features = bit(X86_FEATURE_FPU) |
1090 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1091 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1092 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1093 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1094 bit(X86_FEATURE_SEP) | bit(X86_FEATURE_PGE) |
1095 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1096 bit(X86_FEATURE_CLFLSH) | bit(X86_FEATURE_MMX) |
1097 bit(X86_FEATURE_FXSR) | bit(X86_FEATURE_XMM) |
1098 bit(X86_FEATURE_XMM2) | bit(X86_FEATURE_SELFSNOOP);
1099 const u32 kvm_supported_word1_x86_features = bit(X86_FEATURE_FPU) |
1100 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1101 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1102 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1103 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1104 bit(X86_FEATURE_PGE) |
1105 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1106 bit(X86_FEATURE_MMX) | bit(X86_FEATURE_FXSR) |
1107 bit(X86_FEATURE_SYSCALL) |
1108 (bit(X86_FEATURE_NX) && is_efer_nx()) |
1109#ifdef CONFIG_X86_64
1110 bit(X86_FEATURE_LM) |
1111#endif
1112 bit(X86_FEATURE_MMXEXT) |
1113 bit(X86_FEATURE_3DNOWEXT) |
1114 bit(X86_FEATURE_3DNOW);
1115 const u32 kvm_supported_word3_x86_features =
1116 bit(X86_FEATURE_XMM3) | bit(X86_FEATURE_CX16);
1117 const u32 kvm_supported_word6_x86_features =
1118 bit(X86_FEATURE_LAHF_LM) | bit(X86_FEATURE_CMP_LEGACY);
1119
1120 /* all func 2 cpuid_count() should be called on the same cpu */
1121 get_cpu();
1122 do_cpuid_1_ent(entry, function, index);
1123 ++*nent;
1124
1125 switch (function) {
1126 case 0:
1127 entry->eax = min(entry->eax, (u32)0xb);
1128 break;
1129 case 1:
1130 entry->edx &= kvm_supported_word0_x86_features;
1131 entry->ecx &= kvm_supported_word3_x86_features;
1132 break;
1133 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1134 * may return different values. This forces us to get_cpu() before
1135 * issuing the first command, and also to emulate this annoying behavior
1136 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1137 case 2: {
1138 int t, times = entry->eax & 0xff;
1139
1140 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1141 for (t = 1; t < times && *nent < maxnent; ++t) {
1142 do_cpuid_1_ent(&entry[t], function, 0);
1143 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1144 ++*nent;
1145 }
1146 break;
1147 }
1148 /* function 4 and 0xb have additional index. */
1149 case 4: {
14af3f3c 1150 int i, cache_type;
07716717
DK		 1151
1152 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1153 /* read more entries until cache_type is zero */
14af3f3c
HH		 1154 for (i = 1; *nent < maxnent; ++i) {
1155 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1156 if (!cache_type)
1157 break;
14af3f3c
HH		 1158 do_cpuid_1_ent(&entry[i], function, i);
1159 entry[i].flags |=
07716717
DK		 1160 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1161 ++*nent;
1162 }
1163 break;
1164 }
1165 case 0xb: {
14af3f3c 1166 int i, level_type;
07716717
DK		 1167
1168 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1169 /* read more entries until level_type is zero */
14af3f3c
HH		 1170 for (i = 1; *nent < maxnent; ++i) {
1171 level_type = entry[i - 1].ecx & 0xff;
07716717
DK		 1172 if (!level_type)
1173 break;
14af3f3c
HH		 1174 do_cpuid_1_ent(&entry[i], function, i);
1175 entry[i].flags |=
07716717
DK		 1176 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1177 ++*nent;
1178 }
1179 break;
1180 }
1181 case 0x80000000:
1182 entry->eax = min(entry->eax, 0x8000001a);
1183 break;
1184 case 0x80000001:
1185 entry->edx &= kvm_supported_word1_x86_features;
1186 entry->ecx &= kvm_supported_word6_x86_features;
1187 break;
1188 }
1189 put_cpu();
1190}
1191
674eea0f 1192static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
07716717
DK		 1193 struct kvm_cpuid_entry2 __user *entries)
1194{
1195 struct kvm_cpuid_entry2 *cpuid_entries;
1196 int limit, nent = 0, r = -E2BIG;
1197 u32 func;
1198
1199 if (cpuid->nent < 1)
1200 goto out;
1201 r = -ENOMEM;
1202 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1203 if (!cpuid_entries)
1204 goto out;
1205
1206 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1207 limit = cpuid_entries[0].eax;
1208 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1209 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1210 &nent, cpuid->nent);
1211 r = -E2BIG;
1212 if (nent >= cpuid->nent)
1213 goto out_free;
1214
1215 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1216 limit = cpuid_entries[nent - 1].eax;
1217 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1218 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1219 &nent, cpuid->nent);
1220 r = -EFAULT;
1221 if (copy_to_user(entries, cpuid_entries,
1222 nent * sizeof(struct kvm_cpuid_entry2)))
1223 goto out_free;
1224 cpuid->nent = nent;
1225 r = 0;
1226
1227out_free:
1228 vfree(cpuid_entries);
1229out:
1230 return r;
1231}
1232
313a3dc7
CO		 1233static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1234 struct kvm_lapic_state *s)
1235{
1236 vcpu_load(vcpu);
ad312c7c 1237 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1238 vcpu_put(vcpu);
1239
1240 return 0;
1241}
1242
1243static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1244 struct kvm_lapic_state *s)
1245{
1246 vcpu_load(vcpu);
ad312c7c 1247 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7
CO		 1248 kvm_apic_post_state_restore(vcpu);
1249 vcpu_put(vcpu);
1250
1251 return 0;
1252}
1253
f77bc6a4
ZX		 1254static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1255 struct kvm_interrupt *irq)
1256{
1257 if (irq->irq < 0 || irq->irq >= 256)
1258 return -EINVAL;
1259 if (irqchip_in_kernel(vcpu->kvm))
1260 return -ENXIO;
1261 vcpu_load(vcpu);
1262
ad312c7c
ZX		 1263 set_bit(irq->irq, vcpu->arch.irq_pending);
1264 set_bit(irq->irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
f77bc6a4
ZX		 1265
1266 vcpu_put(vcpu);
1267
1268 return 0;
1269}
1270
b209749f
AK		 1271static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1272 struct kvm_tpr_access_ctl *tac)
1273{
1274 if (tac->flags)
1275 return -EINVAL;
1276 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1277 return 0;
1278}
1279
313a3dc7
CO		 1280long kvm_arch_vcpu_ioctl(struct file *filp,
1281 unsigned int ioctl, unsigned long arg)
1282{
1283 struct kvm_vcpu *vcpu = filp->private_data;
1284 void __user *argp = (void __user *)arg;
1285 int r;
1286
1287 switch (ioctl) {
1288 case KVM_GET_LAPIC: {
1289 struct kvm_lapic_state lapic;
1290
1291 memset(&lapic, 0, sizeof lapic);
1292 r = kvm_vcpu_ioctl_get_lapic(vcpu, &lapic);
1293 if (r)
1294 goto out;
1295 r = -EFAULT;
1296 if (copy_to_user(argp, &lapic, sizeof lapic))
1297 goto out;
1298 r = 0;
1299 break;
1300 }
1301 case KVM_SET_LAPIC: {
1302 struct kvm_lapic_state lapic;
1303
1304 r = -EFAULT;
1305 if (copy_from_user(&lapic, argp, sizeof lapic))
1306 goto out;
1307 r = kvm_vcpu_ioctl_set_lapic(vcpu, &lapic);;
1308 if (r)
1309 goto out;
1310 r = 0;
1311 break;
1312 }
f77bc6a4
ZX		 1313 case KVM_INTERRUPT: {
1314 struct kvm_interrupt irq;
1315
1316 r = -EFAULT;
1317 if (copy_from_user(&irq, argp, sizeof irq))
1318 goto out;
1319 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1320 if (r)
1321 goto out;
1322 r = 0;
1323 break;
1324 }
313a3dc7
CO		 1325 case KVM_SET_CPUID: {
1326 struct kvm_cpuid __user *cpuid_arg = argp;
1327 struct kvm_cpuid cpuid;
1328
1329 r = -EFAULT;
1330 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1331 goto out;
1332 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1333 if (r)
1334 goto out;
1335 break;
1336 }
07716717
DK		 1337 case KVM_SET_CPUID2: {
1338 struct kvm_cpuid2 __user *cpuid_arg = argp;
1339 struct kvm_cpuid2 cpuid;
1340
1341 r = -EFAULT;
1342 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1343 goto out;
1344 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
1345 cpuid_arg->entries);
1346 if (r)
1347 goto out;
1348 break;
1349 }
1350 case KVM_GET_CPUID2: {
1351 struct kvm_cpuid2 __user *cpuid_arg = argp;
1352 struct kvm_cpuid2 cpuid;
1353
1354 r = -EFAULT;
1355 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1356 goto out;
1357 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
1358 cpuid_arg->entries);
1359 if (r)
1360 goto out;
1361 r = -EFAULT;
1362 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1363 goto out;
1364 r = 0;
1365 break;
1366 }
313a3dc7
CO		 1367 case KVM_GET_MSRS:
1368 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1369 break;
1370 case KVM_SET_MSRS:
1371 r = msr_io(vcpu, argp, do_set_msr, 0);
1372 break;
b209749f
AK		 1373 case KVM_TPR_ACCESS_REPORTING: {
1374 struct kvm_tpr_access_ctl tac;
1375
1376 r = -EFAULT;
1377 if (copy_from_user(&tac, argp, sizeof tac))
1378 goto out;
1379 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1380 if (r)
1381 goto out;
1382 r = -EFAULT;
1383 if (copy_to_user(argp, &tac, sizeof tac))
1384 goto out;
1385 r = 0;
1386 break;
1387 };
b93463aa
AK		 1388 case KVM_SET_VAPIC_ADDR: {
1389 struct kvm_vapic_addr va;
1390
1391 r = -EINVAL;
1392 if (!irqchip_in_kernel(vcpu->kvm))
1393 goto out;
1394 r = -EFAULT;
1395 if (copy_from_user(&va, argp, sizeof va))
1396 goto out;
1397 r = 0;
1398 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1399 break;
1400 }
313a3dc7
CO		 1401 default:
1402 r = -EINVAL;
1403 }
1404out:
1405 return r;
1406}
1407
1fe779f8
CO		 1408static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1409{
1410 int ret;
1411
1412 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1413 return -1;
1414 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1415 return ret;
1416}
1417
1418static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1419 u32 kvm_nr_mmu_pages)
1420{
1421 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1422 return -EINVAL;
1423
72dc67a6 1424 down_write(&kvm->slots_lock);
1fe779f8
CO		 1425
1426 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1427 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1428
72dc67a6 1429 up_write(&kvm->slots_lock);
1fe779f8
CO		 1430 return 0;
1431}
1432
1433static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1434{
f05e70ac 1435 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1436}
1437
e9f85cde
ZX		 1438gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1439{
1440 int i;
1441 struct kvm_mem_alias *alias;
1442
d69fb81f
ZX		 1443 for (i = 0; i < kvm->arch.naliases; ++i) {
1444 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1445 if (gfn >= alias->base_gfn
1446 && gfn < alias->base_gfn + alias->npages)
1447 return alias->target_gfn + gfn - alias->base_gfn;
1448 }
1449 return gfn;
1450}
1451
1fe779f8
CO		 1452/*
1453 * Set a new alias region. Aliases map a portion of physical memory into
1454 * another portion. This is useful for memory windows, for example the PC
1455 * VGA region.
1456 */
1457static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1458 struct kvm_memory_alias *alias)
1459{
1460 int r, n;
1461 struct kvm_mem_alias *p;
1462
1463 r = -EINVAL;
1464 /* General sanity checks */
1465 if (alias->memory_size & (PAGE_SIZE - 1))
1466 goto out;
1467 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1468 goto out;
1469 if (alias->slot >= KVM_ALIAS_SLOTS)
1470 goto out;
1471 if (alias->guest_phys_addr + alias->memory_size
1472 < alias->guest_phys_addr)
1473 goto out;
1474 if (alias->target_phys_addr + alias->memory_size
1475 < alias->target_phys_addr)
1476 goto out;
1477
72dc67a6 1478 down_write(&kvm->slots_lock);
1fe779f8 1479
d69fb81f 1480 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 1481 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1482 p->npages = alias->memory_size >> PAGE_SHIFT;
1483 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1484
1485 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 1486 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 1487 break;
d69fb81f 1488 kvm->arch.naliases = n;
1fe779f8
CO		 1489
1490 kvm_mmu_zap_all(kvm);
1491
72dc67a6 1492 up_write(&kvm->slots_lock);
1fe779f8
CO		 1493
1494 return 0;
1495
1496out:
1497 return r;
1498}
1499
1500static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1501{
1502 int r;
1503
1504 r = 0;
1505 switch (chip->chip_id) {
1506 case KVM_IRQCHIP_PIC_MASTER:
1507 memcpy(&chip->chip.pic,
1508 &pic_irqchip(kvm)->pics[0],
1509 sizeof(struct kvm_pic_state));
1510 break;
1511 case KVM_IRQCHIP_PIC_SLAVE:
1512 memcpy(&chip->chip.pic,
1513 &pic_irqchip(kvm)->pics[1],
1514 sizeof(struct kvm_pic_state));
1515 break;
1516 case KVM_IRQCHIP_IOAPIC:
1517 memcpy(&chip->chip.ioapic,
1518 ioapic_irqchip(kvm),
1519 sizeof(struct kvm_ioapic_state));
1520 break;
1521 default:
1522 r = -EINVAL;
1523 break;
1524 }
1525 return r;
1526}
1527
1528static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1529{
1530 int r;
1531
1532 r = 0;
1533 switch (chip->chip_id) {
1534 case KVM_IRQCHIP_PIC_MASTER:
1535 memcpy(&pic_irqchip(kvm)->pics[0],
1536 &chip->chip.pic,
1537 sizeof(struct kvm_pic_state));
1538 break;
1539 case KVM_IRQCHIP_PIC_SLAVE:
1540 memcpy(&pic_irqchip(kvm)->pics[1],
1541 &chip->chip.pic,
1542 sizeof(struct kvm_pic_state));
1543 break;
1544 case KVM_IRQCHIP_IOAPIC:
1545 memcpy(ioapic_irqchip(kvm),
1546 &chip->chip.ioapic,
1547 sizeof(struct kvm_ioapic_state));
1548 break;
1549 default:
1550 r = -EINVAL;
1551 break;
1552 }
1553 kvm_pic_update_irq(pic_irqchip(kvm));
1554 return r;
1555}
1556
e0f63cb9
SY		 1557static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1558{
1559 int r = 0;
1560
1561 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
1562 return r;
1563}
1564
1565static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1566{
1567 int r = 0;
1568
1569 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
1570 kvm_pit_load_count(kvm, 0, ps->channels[0].count);
1571 return r;
1572}
1573
5bb064dc
ZX		 1574/*
1575 * Get (and clear) the dirty memory log for a memory slot.
1576 */
1577int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
1578 struct kvm_dirty_log *log)
1579{
1580 int r;
1581 int n;
1582 struct kvm_memory_slot *memslot;
1583 int is_dirty = 0;
1584
72dc67a6 1585 down_write(&kvm->slots_lock);
5bb064dc
ZX		 1586
1587 r = kvm_get_dirty_log(kvm, log, &is_dirty);
1588 if (r)
1589 goto out;
1590
1591 /* If nothing is dirty, don't bother messing with page tables. */
1592 if (is_dirty) {
1593 kvm_mmu_slot_remove_write_access(kvm, log->slot);
1594 kvm_flush_remote_tlbs(kvm);
1595 memslot = &kvm->memslots[log->slot];
1596 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
1597 memset(memslot->dirty_bitmap, 0, n);
1598 }
1599 r = 0;
1600out:
72dc67a6 1601 up_write(&kvm->slots_lock);
5bb064dc
ZX		 1602 return r;
1603}
1604
1fe779f8
CO		 1605long kvm_arch_vm_ioctl(struct file *filp,
1606 unsigned int ioctl, unsigned long arg)
1607{
1608 struct kvm *kvm = filp->private_data;
1609 void __user *argp = (void __user *)arg;
1610 int r = -EINVAL;
1611
1612 switch (ioctl) {
1613 case KVM_SET_TSS_ADDR:
1614 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1615 if (r < 0)
1616 goto out;
1617 break;
1618 case KVM_SET_MEMORY_REGION: {
1619 struct kvm_memory_region kvm_mem;
1620 struct kvm_userspace_memory_region kvm_userspace_mem;
1621
1622 r = -EFAULT;
1623 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
1624 goto out;
1625 kvm_userspace_mem.slot = kvm_mem.slot;
1626 kvm_userspace_mem.flags = kvm_mem.flags;
1627 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
1628 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
1629 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
1630 if (r)
1631 goto out;
1632 break;
1633 }
1634 case KVM_SET_NR_MMU_PAGES:
1635 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1636 if (r)
1637 goto out;
1638 break;
1639 case KVM_GET_NR_MMU_PAGES:
1640 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
1641 break;
1642 case KVM_SET_MEMORY_ALIAS: {
1643 struct kvm_memory_alias alias;
1644
1645 r = -EFAULT;
1646 if (copy_from_user(&alias, argp, sizeof alias))
1647 goto out;
1648 r = kvm_vm_ioctl_set_memory_alias(kvm, &alias);
1649 if (r)
1650 goto out;
1651 break;
1652 }
1653 case KVM_CREATE_IRQCHIP:
1654 r = -ENOMEM;
d7deeeb0
ZX		 1655 kvm->arch.vpic = kvm_create_pic(kvm);
1656 if (kvm->arch.vpic) {
1fe779f8
CO		 1657 r = kvm_ioapic_init(kvm);
1658 if (r) {
d7deeeb0
ZX		 1659 kfree(kvm->arch.vpic);
1660 kvm->arch.vpic = NULL;
1fe779f8
CO		 1661 goto out;
1662 }
1663 } else
1664 goto out;
1665 break;
7837699f
SY		 1666 case KVM_CREATE_PIT:
1667 r = -ENOMEM;
1668 kvm->arch.vpit = kvm_create_pit(kvm);
1669 if (kvm->arch.vpit)
1670 r = 0;
1671 break;
1fe779f8
CO		 1672 case KVM_IRQ_LINE: {
1673 struct kvm_irq_level irq_event;
1674
1675 r = -EFAULT;
1676 if (copy_from_user(&irq_event, argp, sizeof irq_event))
1677 goto out;
1678 if (irqchip_in_kernel(kvm)) {
1679 mutex_lock(&kvm->lock);
1680 if (irq_event.irq < 16)
1681 kvm_pic_set_irq(pic_irqchip(kvm),
1682 irq_event.irq,
1683 irq_event.level);
d7deeeb0 1684 kvm_ioapic_set_irq(kvm->arch.vioapic,
1fe779f8
CO		 1685 irq_event.irq,
1686 irq_event.level);
1687 mutex_unlock(&kvm->lock);
1688 r = 0;
1689 }
1690 break;
1691 }
1692 case KVM_GET_IRQCHIP: {
1693 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
1694 struct kvm_irqchip chip;
1695
1696 r = -EFAULT;
1697 if (copy_from_user(&chip, argp, sizeof chip))
1698 goto out;
1699 r = -ENXIO;
1700 if (!irqchip_in_kernel(kvm))
1701 goto out;
1702 r = kvm_vm_ioctl_get_irqchip(kvm, &chip);
1703 if (r)
1704 goto out;
1705 r = -EFAULT;
1706 if (copy_to_user(argp, &chip, sizeof chip))
1707 goto out;
1708 r = 0;
1709 break;
1710 }
1711 case KVM_SET_IRQCHIP: {
1712 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
1713 struct kvm_irqchip chip;
1714
1715 r = -EFAULT;
1716 if (copy_from_user(&chip, argp, sizeof chip))
1717 goto out;
1718 r = -ENXIO;
1719 if (!irqchip_in_kernel(kvm))
1720 goto out;
1721 r = kvm_vm_ioctl_set_irqchip(kvm, &chip);
1722 if (r)
1723 goto out;
1724 r = 0;
1725 break;
1726 }
e0f63cb9
SY		 1727 case KVM_GET_PIT: {
1728 struct kvm_pit_state ps;
1729 r = -EFAULT;
1730 if (copy_from_user(&ps, argp, sizeof ps))
1731 goto out;
1732 r = -ENXIO;
1733 if (!kvm->arch.vpit)
1734 goto out;
1735 r = kvm_vm_ioctl_get_pit(kvm, &ps);
1736 if (r)
1737 goto out;
1738 r = -EFAULT;
1739 if (copy_to_user(argp, &ps, sizeof ps))
1740 goto out;
1741 r = 0;
1742 break;
1743 }
1744 case KVM_SET_PIT: {
1745 struct kvm_pit_state ps;
1746 r = -EFAULT;
1747 if (copy_from_user(&ps, argp, sizeof ps))
1748 goto out;
1749 r = -ENXIO;
1750 if (!kvm->arch.vpit)
1751 goto out;
1752 r = kvm_vm_ioctl_set_pit(kvm, &ps);
1753 if (r)
1754 goto out;
1755 r = 0;
1756 break;
1757 }
1fe779f8
CO		 1758 default:
1759 ;
1760 }
1761out:
1762 return r;
1763}
1764
a16b043c 1765static void kvm_init_msr_list(void)
043405e1
CO		 1766{
1767 u32 dummy[2];
1768 unsigned i, j;
1769
1770 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
1771 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
1772 continue;
1773 if (j < i)
1774 msrs_to_save[j] = msrs_to_save[i];
1775 j++;
1776 }
1777 num_msrs_to_save = j;
1778}
1779
bbd9b64e
CO		 1780/*
1781 * Only apic need an MMIO device hook, so shortcut now..
1782 */
1783static struct kvm_io_device *vcpu_find_pervcpu_dev(struct kvm_vcpu *vcpu,
1784 gpa_t addr)
1785{
1786 struct kvm_io_device *dev;
1787
ad312c7c
ZX		 1788 if (vcpu->arch.apic) {
1789 dev = &vcpu->arch.apic->dev;
bbd9b64e
CO		 1790 if (dev->in_range(dev, addr))
1791 return dev;
1792 }
1793 return NULL;
1794}
1795
1796
1797static struct kvm_io_device *vcpu_find_mmio_dev(struct kvm_vcpu *vcpu,
1798 gpa_t addr)
1799{
1800 struct kvm_io_device *dev;
1801
1802 dev = vcpu_find_pervcpu_dev(vcpu, addr);
1803 if (dev == NULL)
1804 dev = kvm_io_bus_find_dev(&vcpu->kvm->mmio_bus, addr);
1805 return dev;
1806}
1807
1808int emulator_read_std(unsigned long addr,
1809 void *val,
1810 unsigned int bytes,
1811 struct kvm_vcpu *vcpu)
1812{
1813 void *data = val;
10589a46 1814 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 1815
1816 while (bytes) {
ad312c7c 1817 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 1818 unsigned offset = addr & (PAGE_SIZE-1);
1819 unsigned tocopy = min(bytes, (unsigned)PAGE_SIZE - offset);
1820 int ret;
1821
10589a46
MT		 1822 if (gpa == UNMAPPED_GVA) {
1823 r = X86EMUL_PROPAGATE_FAULT;
1824 goto out;
1825 }
bbd9b64e 1826 ret = kvm_read_guest(vcpu->kvm, gpa, data, tocopy);
10589a46
MT		 1827 if (ret < 0) {
1828 r = X86EMUL_UNHANDLEABLE;
1829 goto out;
1830 }
bbd9b64e
CO		 1831
1832 bytes -= tocopy;
1833 data += tocopy;
1834 addr += tocopy;
1835 }
10589a46 1836out:
10589a46 1837 return r;
bbd9b64e
CO		 1838}
1839EXPORT_SYMBOL_GPL(emulator_read_std);
1840
bbd9b64e
CO		 1841static int emulator_read_emulated(unsigned long addr,
1842 void *val,
1843 unsigned int bytes,
1844 struct kvm_vcpu *vcpu)
1845{
1846 struct kvm_io_device *mmio_dev;
1847 gpa_t gpa;
1848
1849 if (vcpu->mmio_read_completed) {
1850 memcpy(val, vcpu->mmio_data, bytes);
1851 vcpu->mmio_read_completed = 0;
1852 return X86EMUL_CONTINUE;
1853 }
1854
ad312c7c 1855 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 1856
1857 /* For APIC access vmexit */
1858 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
1859 goto mmio;
1860
1861 if (emulator_read_std(addr, val, bytes, vcpu)
1862 == X86EMUL_CONTINUE)
1863 return X86EMUL_CONTINUE;
1864 if (gpa == UNMAPPED_GVA)
1865 return X86EMUL_PROPAGATE_FAULT;
1866
1867mmio:
1868 /*
1869 * Is this MMIO handled locally?
1870 */
10589a46 1871 mutex_lock(&vcpu->kvm->lock);
bbd9b64e
CO		 1872 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa);
1873 if (mmio_dev) {
1874 kvm_iodevice_read(mmio_dev, gpa, bytes, val);
10589a46 1875 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 1876 return X86EMUL_CONTINUE;
1877 }
10589a46 1878 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 1879
1880 vcpu->mmio_needed = 1;
1881 vcpu->mmio_phys_addr = gpa;
1882 vcpu->mmio_size = bytes;
1883 vcpu->mmio_is_write = 0;
1884
1885 return X86EMUL_UNHANDLEABLE;
1886}
1887
3200f405 1888int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 1889 const void *val, int bytes)
bbd9b64e
CO		 1890{
1891 int ret;
1892
1893 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 1894 if (ret < 0)
bbd9b64e
CO		 1895 return 0;
1896 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
1897 return 1;
1898}
1899
1900static int emulator_write_emulated_onepage(unsigned long addr,
1901 const void *val,
1902 unsigned int bytes,
1903 struct kvm_vcpu *vcpu)
1904{
1905 struct kvm_io_device *mmio_dev;
10589a46
MT		 1906 gpa_t gpa;
1907
10589a46 1908 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 1909
1910 if (gpa == UNMAPPED_GVA) {
c3c91fee 1911 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 1912 return X86EMUL_PROPAGATE_FAULT;
1913 }
1914
1915 /* For APIC access vmexit */
1916 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
1917 goto mmio;
1918
1919 if (emulator_write_phys(vcpu, gpa, val, bytes))
1920 return X86EMUL_CONTINUE;
1921
1922mmio:
1923 /*
1924 * Is this MMIO handled locally?
1925 */
10589a46 1926 mutex_lock(&vcpu->kvm->lock);
bbd9b64e
CO		 1927 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa);
1928 if (mmio_dev) {
1929 kvm_iodevice_write(mmio_dev, gpa, bytes, val);
10589a46 1930 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 1931 return X86EMUL_CONTINUE;
1932 }
10589a46 1933 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 1934
1935 vcpu->mmio_needed = 1;
1936 vcpu->mmio_phys_addr = gpa;
1937 vcpu->mmio_size = bytes;
1938 vcpu->mmio_is_write = 1;
1939 memcpy(vcpu->mmio_data, val, bytes);
1940
1941 return X86EMUL_CONTINUE;
1942}
1943
1944int emulator_write_emulated(unsigned long addr,
1945 const void *val,
1946 unsigned int bytes,
1947 struct kvm_vcpu *vcpu)
1948{
1949 /* Crossing a page boundary? */
1950 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
1951 int rc, now;
1952
1953 now = -addr & ~PAGE_MASK;
1954 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
1955 if (rc != X86EMUL_CONTINUE)
1956 return rc;
1957 addr += now;
1958 val += now;
1959 bytes -= now;
1960 }
1961 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
1962}
1963EXPORT_SYMBOL_GPL(emulator_write_emulated);
1964
1965static int emulator_cmpxchg_emulated(unsigned long addr,
1966 const void *old,
1967 const void *new,
1968 unsigned int bytes,
1969 struct kvm_vcpu *vcpu)
1970{
1971 static int reported;
1972
1973 if (!reported) {
1974 reported = 1;
1975 printk(KERN_WARNING "kvm: emulating exchange as write\n");
1976 }
2bacc55c
MT		 1977#ifndef CONFIG_X86_64
1978 /* guests cmpxchg8b have to be emulated atomically */
1979 if (bytes == 8) {
10589a46 1980 gpa_t gpa;
2bacc55c 1981 struct page *page;
c0b49b0d 1982 char *kaddr;
2bacc55c
MT		 1983 u64 val;
1984
10589a46
MT		 1985 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
1986
2bacc55c
MT		 1987 if (gpa == UNMAPPED_GVA ||
1988 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
1989 goto emul_write;
1990
1991 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
1992 goto emul_write;
1993
1994 val = *(u64 *)new;
72dc67a6
IE		 1995
1996 down_read(&current->mm->mmap_sem);
2bacc55c 1997 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6
IE		 1998 up_read(&current->mm->mmap_sem);
1999
c0b49b0d
AM		 2000 kaddr = kmap_atomic(page, KM_USER0);
2001 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2002 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 2003 kvm_release_page_dirty(page);
2004 }
3200f405 2005emul_write:
2bacc55c
MT		 2006#endif
2007
bbd9b64e
CO		 2008 return emulator_write_emulated(addr, new, bytes, vcpu);
2009}
2010
2011static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2012{
2013 return kvm_x86_ops->get_segment_base(vcpu, seg);
2014}
2015
2016int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2017{
2018 return X86EMUL_CONTINUE;
2019}
2020
2021int emulate_clts(struct kvm_vcpu *vcpu)
2022{
ad312c7c 2023 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 2024 return X86EMUL_CONTINUE;
2025}
2026
2027int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2028{
2029 struct kvm_vcpu *vcpu = ctxt->vcpu;
2030
2031 switch (dr) {
2032 case 0 ... 3:
2033 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2034 return X86EMUL_CONTINUE;
2035 default:
b8688d51 2036 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2037 return X86EMUL_UNHANDLEABLE;
2038 }
2039}
2040
2041int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2042{
2043 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2044 int exception;
2045
2046 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2047 if (exception) {
2048 /* FIXME: better handling */
2049 return X86EMUL_UNHANDLEABLE;
2050 }
2051 return X86EMUL_CONTINUE;
2052}
2053
2054void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2055{
2056 static int reported;
2057 u8 opcodes[4];
ad312c7c 2058 unsigned long rip = vcpu->arch.rip;
bbd9b64e
CO		 2059 unsigned long rip_linear;
2060
2061 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2062
2063 if (reported)
2064 return;
2065
2066 emulator_read_std(rip_linear, (void *)opcodes, 4, vcpu);
2067
2068 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2069 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
2070 reported = 1;
2071}
2072EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2073
14af3f3c 2074static struct x86_emulate_ops emulate_ops = {
bbd9b64e 2075 .read_std = emulator_read_std,
bbd9b64e
CO		 2076 .read_emulated = emulator_read_emulated,
2077 .write_emulated = emulator_write_emulated,
2078 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2079};
2080
2081int emulate_instruction(struct kvm_vcpu *vcpu,
2082 struct kvm_run *run,
2083 unsigned long cr2,
2084 u16 error_code,
571008da 2085 int emulation_type)
bbd9b64e
CO		 2086{
2087 int r;
571008da 2088 struct decode_cache *c;
bbd9b64e 2089
ad312c7c 2090 vcpu->arch.mmio_fault_cr2 = cr2;
bbd9b64e
CO		 2091 kvm_x86_ops->cache_regs(vcpu);
2092
2093 vcpu->mmio_is_write = 0;
ad312c7c 2094 vcpu->arch.pio.string = 0;
bbd9b64e 2095
571008da 2096 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2097 int cs_db, cs_l;
2098 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2099
ad312c7c
ZX		 2100 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2101 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2102 vcpu->arch.emulate_ctxt.mode =
2103 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2104 ? X86EMUL_MODE_REAL : cs_l
2105 ? X86EMUL_MODE_PROT64 : cs_db
2106 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2107
ad312c7c
ZX		 2108 if (vcpu->arch.emulate_ctxt.mode == X86EMUL_MODE_PROT64) {
2109 vcpu->arch.emulate_ctxt.cs_base = 0;
2110 vcpu->arch.emulate_ctxt.ds_base = 0;
2111 vcpu->arch.emulate_ctxt.es_base = 0;
2112 vcpu->arch.emulate_ctxt.ss_base = 0;
bbd9b64e 2113 } else {
ad312c7c 2114 vcpu->arch.emulate_ctxt.cs_base =
bbd9b64e 2115 get_segment_base(vcpu, VCPU_SREG_CS);
ad312c7c 2116 vcpu->arch.emulate_ctxt.ds_base =
bbd9b64e 2117 get_segment_base(vcpu, VCPU_SREG_DS);
ad312c7c 2118 vcpu->arch.emulate_ctxt.es_base =
bbd9b64e 2119 get_segment_base(vcpu, VCPU_SREG_ES);
ad312c7c 2120 vcpu->arch.emulate_ctxt.ss_base =
bbd9b64e
CO		 2121 get_segment_base(vcpu, VCPU_SREG_SS);
2122 }
2123
ad312c7c 2124 vcpu->arch.emulate_ctxt.gs_base =
bbd9b64e 2125 get_segment_base(vcpu, VCPU_SREG_GS);
ad312c7c 2126 vcpu->arch.emulate_ctxt.fs_base =
bbd9b64e
CO		 2127 get_segment_base(vcpu, VCPU_SREG_FS);
2128
ad312c7c 2129 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da
SY		 2130
2131 /* Reject the instructions other than VMCALL/VMMCALL when
2132 * try to emulate invalid opcode */
2133 c = &vcpu->arch.emulate_ctxt.decode;
2134 if ((emulation_type & EMULTYPE_TRAP_UD) &&
2135 (!(c->twobyte && c->b == 0x01 &&
2136 (c->modrm_reg == 0 || c->modrm_reg == 3) &&
2137 c->modrm_mod == 3 && c->modrm_rm == 1)))
2138 return EMULATE_FAIL;
2139
f2b5756b 2140 ++vcpu->stat.insn_emulation;
bbd9b64e 2141 if (r) {
f2b5756b 2142 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2143 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2144 return EMULATE_DONE;
2145 return EMULATE_FAIL;
2146 }
2147 }
2148
ad312c7c 2149 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
bbd9b64e 2150
ad312c7c 2151 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2152 return EMULATE_DO_MMIO;
2153
2154 if ((r || vcpu->mmio_is_write) && run) {
2155 run->exit_reason = KVM_EXIT_MMIO;
2156 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2157 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2158 run->mmio.len = vcpu->mmio_size;
2159 run->mmio.is_write = vcpu->mmio_is_write;
2160 }
2161
2162 if (r) {
2163 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2164 return EMULATE_DONE;
2165 if (!vcpu->mmio_needed) {
2166 kvm_report_emulation_failure(vcpu, "mmio");
2167 return EMULATE_FAIL;
2168 }
2169 return EMULATE_DO_MMIO;
2170 }
2171
2172 kvm_x86_ops->decache_regs(vcpu);
ad312c7c 2173 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2174
2175 if (vcpu->mmio_is_write) {
2176 vcpu->mmio_needed = 0;
2177 return EMULATE_DO_MMIO;
2178 }
2179
2180 return EMULATE_DONE;
2181}
2182EXPORT_SYMBOL_GPL(emulate_instruction);
2183
de7d789a
CO		 2184static void free_pio_guest_pages(struct kvm_vcpu *vcpu)
2185{
2186 int i;
2187
ad312c7c
ZX		 2188 for (i = 0; i < ARRAY_SIZE(vcpu->arch.pio.guest_pages); ++i)
2189 if (vcpu->arch.pio.guest_pages[i]) {
2190 kvm_release_page_dirty(vcpu->arch.pio.guest_pages[i]);
2191 vcpu->arch.pio.guest_pages[i] = NULL;
de7d789a
CO		 2192 }
2193}
2194
2195static int pio_copy_data(struct kvm_vcpu *vcpu)
2196{
ad312c7c 2197 void *p = vcpu->arch.pio_data;
de7d789a
CO		 2198 void *q;
2199 unsigned bytes;
ad312c7c 2200 int nr_pages = vcpu->arch.pio.guest_pages[1] ? 2 : 1;
de7d789a 2201
ad312c7c 2202 q = vmap(vcpu->arch.pio.guest_pages, nr_pages, VM_READ|VM_WRITE,
de7d789a
CO		 2203 PAGE_KERNEL);
2204 if (!q) {
2205 free_pio_guest_pages(vcpu);
2206 return -ENOMEM;
2207 }
ad312c7c
ZX		 2208 q += vcpu->arch.pio.guest_page_offset;
2209 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2210 if (vcpu->arch.pio.in)
de7d789a
CO		 2211 memcpy(q, p, bytes);
2212 else
2213 memcpy(p, q, bytes);
ad312c7c 2214 q -= vcpu->arch.pio.guest_page_offset;
de7d789a
CO		 2215 vunmap(q);
2216 free_pio_guest_pages(vcpu);
2217 return 0;
2218}
2219
2220int complete_pio(struct kvm_vcpu *vcpu)
2221{
ad312c7c 2222 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2223 long delta;
2224 int r;
2225
2226 kvm_x86_ops->cache_regs(vcpu);
2227
2228 if (!io->string) {
2229 if (io->in)
ad312c7c 2230 memcpy(&vcpu->arch.regs[VCPU_REGS_RAX], vcpu->arch.pio_data,
de7d789a
CO		 2231 io->size);
2232 } else {
2233 if (io->in) {
2234 r = pio_copy_data(vcpu);
2235 if (r) {
2236 kvm_x86_ops->cache_regs(vcpu);
2237 return r;
2238 }
2239 }
2240
2241 delta = 1;
2242 if (io->rep) {
2243 delta *= io->cur_count;
2244 /*
2245 * The size of the register should really depend on
2246 * current address size.
2247 */
ad312c7c 2248 vcpu->arch.regs[VCPU_REGS_RCX] -= delta;
de7d789a
CO		 2249 }
2250 if (io->down)
2251 delta = -delta;
2252 delta *= io->size;
2253 if (io->in)
ad312c7c 2254 vcpu->arch.regs[VCPU_REGS_RDI] += delta;
de7d789a 2255 else
ad312c7c 2256 vcpu->arch.regs[VCPU_REGS_RSI] += delta;
de7d789a
CO		 2257 }
2258
2259 kvm_x86_ops->decache_regs(vcpu);
2260
2261 io->count -= io->cur_count;
2262 io->cur_count = 0;
2263
2264 return 0;
2265}
2266
2267static void kernel_pio(struct kvm_io_device *pio_dev,
2268 struct kvm_vcpu *vcpu,
2269 void *pd)
2270{
2271 /* TODO: String I/O for in kernel device */
2272
2273 mutex_lock(&vcpu->kvm->lock);
ad312c7c
ZX		 2274 if (vcpu->arch.pio.in)
2275 kvm_iodevice_read(pio_dev, vcpu->arch.pio.port,
2276 vcpu->arch.pio.size,
de7d789a
CO		 2277 pd);
2278 else
ad312c7c
ZX		 2279 kvm_iodevice_write(pio_dev, vcpu->arch.pio.port,
2280 vcpu->arch.pio.size,
de7d789a
CO		 2281 pd);
2282 mutex_unlock(&vcpu->kvm->lock);
2283}
2284
2285static void pio_string_write(struct kvm_io_device *pio_dev,
2286 struct kvm_vcpu *vcpu)
2287{
ad312c7c
ZX		 2288 struct kvm_pio_request *io = &vcpu->arch.pio;
2289 void *pd = vcpu->arch.pio_data;
de7d789a
CO		 2290 int i;
2291
2292 mutex_lock(&vcpu->kvm->lock);
2293 for (i = 0; i < io->cur_count; i++) {
2294 kvm_iodevice_write(pio_dev, io->port,
2295 io->size,
2296 pd);
2297 pd += io->size;
2298 }
2299 mutex_unlock(&vcpu->kvm->lock);
2300}
2301
2302static struct kvm_io_device *vcpu_find_pio_dev(struct kvm_vcpu *vcpu,
2303 gpa_t addr)
2304{
2305 return kvm_io_bus_find_dev(&vcpu->kvm->pio_bus, addr);
2306}
2307
2308int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2309 int size, unsigned port)
2310{
2311 struct kvm_io_device *pio_dev;
2312
2313 vcpu->run->exit_reason = KVM_EXIT_IO;
2314 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2315 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2316 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2317 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2318 vcpu->run->io.port = vcpu->arch.pio.port = port;
2319 vcpu->arch.pio.in = in;
2320 vcpu->arch.pio.string = 0;
2321 vcpu->arch.pio.down = 0;
2322 vcpu->arch.pio.guest_page_offset = 0;
2323 vcpu->arch.pio.rep = 0;
de7d789a 2324
2714d1d3
FEL		 2325 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2326 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2327 handler);
2328 else
2329 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2330 handler);
2331
de7d789a 2332 kvm_x86_ops->cache_regs(vcpu);
ad312c7c 2333 memcpy(vcpu->arch.pio_data, &vcpu->arch.regs[VCPU_REGS_RAX], 4);
de7d789a
CO		 2334 kvm_x86_ops->decache_regs(vcpu);
2335
2336 kvm_x86_ops->skip_emulated_instruction(vcpu);
2337
2338 pio_dev = vcpu_find_pio_dev(vcpu, port);
2339 if (pio_dev) {
ad312c7c 2340 kernel_pio(pio_dev, vcpu, vcpu->arch.pio_data);
de7d789a
CO		 2341 complete_pio(vcpu);
2342 return 1;
2343 }
2344 return 0;
2345}
2346EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2347
2348int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2349 int size, unsigned long count, int down,
2350 gva_t address, int rep, unsigned port)
2351{
2352 unsigned now, in_page;
2353 int i, ret = 0;
2354 int nr_pages = 1;
2355 struct page *page;
2356 struct kvm_io_device *pio_dev;
2357
2358 vcpu->run->exit_reason = KVM_EXIT_IO;
2359 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2360 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2361 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2362 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2363 vcpu->run->io.port = vcpu->arch.pio.port = port;
2364 vcpu->arch.pio.in = in;
2365 vcpu->arch.pio.string = 1;
2366 vcpu->arch.pio.down = down;
2367 vcpu->arch.pio.guest_page_offset = offset_in_page(address);
2368 vcpu->arch.pio.rep = rep;
de7d789a 2369
2714d1d3
FEL		 2370 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2371 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2372 handler);
2373 else
2374 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2375 handler);
2376
de7d789a
CO		 2377 if (!count) {
2378 kvm_x86_ops->skip_emulated_instruction(vcpu);
2379 return 1;
2380 }
2381
2382 if (!down)
2383 in_page = PAGE_SIZE - offset_in_page(address);
2384 else
2385 in_page = offset_in_page(address) + size;
2386 now = min(count, (unsigned long)in_page / size);
2387 if (!now) {
2388 /*
2389 * String I/O straddles page boundary. Pin two guest pages
2390 * so that we satisfy atomicity constraints. Do just one
2391 * transaction to avoid complexity.
2392 */
2393 nr_pages = 2;
2394 now = 1;
2395 }
2396 if (down) {
2397 /*
2398 * String I/O in reverse. Yuck. Kill the guest, fix later.
2399 */
2400 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 2401 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2402 return 1;
2403 }
2404 vcpu->run->io.count = now;
ad312c7c 2405 vcpu->arch.pio.cur_count = now;
de7d789a 2406
ad312c7c 2407 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 2408 kvm_x86_ops->skip_emulated_instruction(vcpu);
2409
2410 for (i = 0; i < nr_pages; ++i) {
de7d789a 2411 page = gva_to_page(vcpu, address + i * PAGE_SIZE);
ad312c7c 2412 vcpu->arch.pio.guest_pages[i] = page;
de7d789a 2413 if (!page) {
c1a5d4f9 2414 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2415 free_pio_guest_pages(vcpu);
2416 return 1;
2417 }
2418 }
2419
2420 pio_dev = vcpu_find_pio_dev(vcpu, port);
ad312c7c 2421 if (!vcpu->arch.pio.in) {
de7d789a
CO		 2422 /* string PIO write */
2423 ret = pio_copy_data(vcpu);
2424 if (ret >= 0 && pio_dev) {
2425 pio_string_write(pio_dev, vcpu);
2426 complete_pio(vcpu);
ad312c7c 2427 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 2428 ret = 1;
2429 }
2430 } else if (pio_dev)
2431 pr_unimpl(vcpu, "no string pio read support yet, "
2432 "port %x size %d count %ld\n",
2433 port, size, count);
2434
2435 return ret;
2436}
2437EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
2438
f8c16bba 2439int kvm_arch_init(void *opaque)
043405e1 2440{
56c6d28a 2441 int r;
f8c16bba
ZX		 2442 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
2443
f8c16bba
ZX		 2444 if (kvm_x86_ops) {
2445 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 2446 r = -EEXIST;
2447 goto out;
f8c16bba
ZX		 2448 }
2449
2450 if (!ops->cpu_has_kvm_support()) {
2451 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 2452 r = -EOPNOTSUPP;
2453 goto out;
f8c16bba
ZX		 2454 }
2455 if (ops->disabled_by_bios()) {
2456 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 2457 r = -EOPNOTSUPP;
2458 goto out;
f8c16bba
ZX		 2459 }
2460
97db56ce
AK		 2461 r = kvm_mmu_module_init();
2462 if (r)
2463 goto out;
2464
2465 kvm_init_msr_list();
2466
f8c16bba 2467 kvm_x86_ops = ops;
56c6d28a 2468 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 2469 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
2470 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
2471 PT_DIRTY_MASK, PT64_NX_MASK, 0);
f8c16bba 2472 return 0;
56c6d28a
ZX		 2473
2474out:
56c6d28a 2475 return r;
043405e1 2476}
8776e519 2477
f8c16bba
ZX		 2478void kvm_arch_exit(void)
2479{
2480 kvm_x86_ops = NULL;
56c6d28a
ZX		 2481 kvm_mmu_module_exit();
2482}
f8c16bba 2483
8776e519
HB		 2484int kvm_emulate_halt(struct kvm_vcpu *vcpu)
2485{
2486 ++vcpu->stat.halt_exits;
2714d1d3 2487 KVMTRACE_0D(HLT, vcpu, handler);
8776e519 2488 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 2489 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
3200f405 2490 up_read(&vcpu->kvm->slots_lock);
8776e519 2491 kvm_vcpu_block(vcpu);
3200f405 2492 down_read(&vcpu->kvm->slots_lock);
a4535290 2493 if (vcpu->arch.mp_state != KVM_MP_STATE_RUNNABLE)
8776e519
HB		 2494 return -EINTR;
2495 return 1;
2496 } else {
2497 vcpu->run->exit_reason = KVM_EXIT_HLT;
2498 return 0;
2499 }
2500}
2501EXPORT_SYMBOL_GPL(kvm_emulate_halt);
2502
2f333bcb
MT		 2503static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
2504 unsigned long a1)
2505{
2506 if (is_long_mode(vcpu))
2507 return a0;
2508 else
2509 return a0 | ((gpa_t)a1 << 32);
2510}
2511
8776e519
HB		 2512int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
2513{
2514 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 2515 int r = 1;
8776e519
HB		 2516
2517 kvm_x86_ops->cache_regs(vcpu);
2518
ad312c7c
ZX		 2519 nr = vcpu->arch.regs[VCPU_REGS_RAX];
2520 a0 = vcpu->arch.regs[VCPU_REGS_RBX];
2521 a1 = vcpu->arch.regs[VCPU_REGS_RCX];
2522 a2 = vcpu->arch.regs[VCPU_REGS_RDX];
2523 a3 = vcpu->arch.regs[VCPU_REGS_RSI];
8776e519 2524
2714d1d3
FEL		 2525 KVMTRACE_1D(VMMCALL, vcpu, (u32)nr, handler);
2526
8776e519
HB		 2527 if (!is_long_mode(vcpu)) {
2528 nr &= 0xFFFFFFFF;
2529 a0 &= 0xFFFFFFFF;
2530 a1 &= 0xFFFFFFFF;
2531 a2 &= 0xFFFFFFFF;
2532 a3 &= 0xFFFFFFFF;
2533 }
2534
2535 switch (nr) {
b93463aa
AK		 2536 case KVM_HC_VAPIC_POLL_IRQ:
2537 ret = 0;
2538 break;
2f333bcb
MT		 2539 case KVM_HC_MMU_OP:
2540 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
2541 break;
8776e519
HB		 2542 default:
2543 ret = -KVM_ENOSYS;
2544 break;
2545 }
ad312c7c 2546 vcpu->arch.regs[VCPU_REGS_RAX] = ret;
8776e519 2547 kvm_x86_ops->decache_regs(vcpu);
f11c3a8d 2548 ++vcpu->stat.hypercalls;
2f333bcb 2549 return r;
8776e519
HB		 2550}
2551EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
2552
2553int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
2554{
2555 char instruction[3];
2556 int ret = 0;
2557
8776e519
HB		 2558
2559 /*
2560 * Blow out the MMU to ensure that no other VCPU has an active mapping
2561 * to ensure that the updated hypercall appears atomically across all
2562 * VCPUs.
2563 */
2564 kvm_mmu_zap_all(vcpu->kvm);
2565
2566 kvm_x86_ops->cache_regs(vcpu);
2567 kvm_x86_ops->patch_hypercall(vcpu, instruction);
ad312c7c 2568 if (emulator_write_emulated(vcpu->arch.rip, instruction, 3, vcpu)
8776e519
HB		 2569 != X86EMUL_CONTINUE)
2570 ret = -EFAULT;
2571
8776e519
HB		 2572 return ret;
2573}
2574
2575static u64 mk_cr_64(u64 curr_cr, u32 new_val)
2576{
2577 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
2578}
2579
2580void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2581{
2582 struct descriptor_table dt = { limit, base };
2583
2584 kvm_x86_ops->set_gdt(vcpu, &dt);
2585}
2586
2587void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2588{
2589 struct descriptor_table dt = { limit, base };
2590
2591 kvm_x86_ops->set_idt(vcpu, &dt);
2592}
2593
2594void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
2595 unsigned long *rflags)
2596{
2d3ad1f4 2597 kvm_lmsw(vcpu, msw);
8776e519
HB		 2598 *rflags = kvm_x86_ops->get_rflags(vcpu);
2599}
2600
2601unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
2602{
2603 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
2604 switch (cr) {
2605 case 0:
ad312c7c 2606 return vcpu->arch.cr0;
8776e519 2607 case 2:
ad312c7c 2608 return vcpu->arch.cr2;
8776e519 2609 case 3:
ad312c7c 2610 return vcpu->arch.cr3;
8776e519 2611 case 4:
ad312c7c 2612 return vcpu->arch.cr4;
152ff9be 2613 case 8:
2d3ad1f4 2614 return kvm_get_cr8(vcpu);
8776e519 2615 default:
b8688d51 2616 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2617 return 0;
2618 }
2619}
2620
2621void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
2622 unsigned long *rflags)
2623{
2624 switch (cr) {
2625 case 0:
2d3ad1f4 2626 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 2627 *rflags = kvm_x86_ops->get_rflags(vcpu);
2628 break;
2629 case 2:
ad312c7c 2630 vcpu->arch.cr2 = val;
8776e519
HB		 2631 break;
2632 case 3:
2d3ad1f4 2633 kvm_set_cr3(vcpu, val);
8776e519
HB		 2634 break;
2635 case 4:
2d3ad1f4 2636 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 2637 break;
152ff9be 2638 case 8:
2d3ad1f4 2639 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 2640 break;
8776e519 2641 default:
b8688d51 2642 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2643 }
2644}
2645
07716717
DK		 2646static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
2647{
ad312c7c
ZX		 2648 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
2649 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 2650
2651 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
2652 /* when no next entry is found, the current entry[i] is reselected */
2653 for (j = i + 1; j == i; j = (j + 1) % nent) {
ad312c7c 2654 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 2655 if (ej->function == e->function) {
2656 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
2657 return j;
2658 }
2659 }
2660 return 0; /* silence gcc, even though control never reaches here */
2661}
2662
2663/* find an entry with matching function, matching index (if needed), and that
2664 * should be read next (if it's stateful) */
2665static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
2666 u32 function, u32 index)
2667{
2668 if (e->function != function)
2669 return 0;
2670 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
2671 return 0;
2672 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
2673 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
2674 return 0;
2675 return 1;
2676}
2677
8776e519
HB		 2678void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
2679{
2680 int i;
07716717
DK		 2681 u32 function, index;
2682 struct kvm_cpuid_entry2 *e, *best;
8776e519
HB		 2683
2684 kvm_x86_ops->cache_regs(vcpu);
ad312c7c
ZX		 2685 function = vcpu->arch.regs[VCPU_REGS_RAX];
2686 index = vcpu->arch.regs[VCPU_REGS_RCX];
2687 vcpu->arch.regs[VCPU_REGS_RAX] = 0;
2688 vcpu->arch.regs[VCPU_REGS_RBX] = 0;
2689 vcpu->arch.regs[VCPU_REGS_RCX] = 0;
2690 vcpu->arch.regs[VCPU_REGS_RDX] = 0;
8776e519 2691 best = NULL;
ad312c7c
ZX		 2692 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2693 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 2694 if (is_matching_cpuid_entry(e, function, index)) {
2695 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
2696 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 2697 best = e;
2698 break;
2699 }
2700 /*
2701 * Both basic or both extended?
2702 */
2703 if (((e->function ^ function) & 0x80000000) == 0)
2704 if (!best || e->function > best->function)
2705 best = e;
2706 }
2707 if (best) {
ad312c7c
ZX		 2708 vcpu->arch.regs[VCPU_REGS_RAX] = best->eax;
2709 vcpu->arch.regs[VCPU_REGS_RBX] = best->ebx;
2710 vcpu->arch.regs[VCPU_REGS_RCX] = best->ecx;
2711 vcpu->arch.regs[VCPU_REGS_RDX] = best->edx;
8776e519
HB		 2712 }
2713 kvm_x86_ops->decache_regs(vcpu);
2714 kvm_x86_ops->skip_emulated_instruction(vcpu);
2714d1d3
FEL		 2715 KVMTRACE_5D(CPUID, vcpu, function,
2716 (u32)vcpu->arch.regs[VCPU_REGS_RAX],
2717 (u32)vcpu->arch.regs[VCPU_REGS_RBX],
2718 (u32)vcpu->arch.regs[VCPU_REGS_RCX],
2719 (u32)vcpu->arch.regs[VCPU_REGS_RDX], handler);
8776e519
HB		 2720}
2721EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 2722
b6c7a5dc
HB		 2723/*
2724 * Check if userspace requested an interrupt window, and that the
2725 * interrupt window is open.
2726 *
2727 * No need to exit to userspace if we already have an interrupt queued.
2728 */
2729static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
2730 struct kvm_run *kvm_run)
2731{
ad312c7c 2732 return (!vcpu->arch.irq_summary &&
b6c7a5dc 2733 kvm_run->request_interrupt_window &&
ad312c7c 2734 vcpu->arch.interrupt_window_open &&
b6c7a5dc
HB		 2735 (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF));
2736}
2737
2738static void post_kvm_run_save(struct kvm_vcpu *vcpu,
2739 struct kvm_run *kvm_run)
2740{
2741 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 2742 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc
HB		 2743 kvm_run->apic_base = kvm_get_apic_base(vcpu);
2744 if (irqchip_in_kernel(vcpu->kvm))
2745 kvm_run->ready_for_interrupt_injection = 1;
2746 else
2747 kvm_run->ready_for_interrupt_injection =
ad312c7c
ZX		 2748 (vcpu->arch.interrupt_window_open &&
2749 vcpu->arch.irq_summary == 0);
b6c7a5dc
HB		 2750}
2751
b93463aa
AK		 2752static void vapic_enter(struct kvm_vcpu *vcpu)
2753{
2754 struct kvm_lapic *apic = vcpu->arch.apic;
2755 struct page *page;
2756
2757 if (!apic || !apic->vapic_addr)
2758 return;
2759
10589a46 2760 down_read(&current->mm->mmap_sem);
b93463aa 2761 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
10589a46 2762 up_read(&current->mm->mmap_sem);
72dc67a6
IE		 2763
2764 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 2765}
2766
2767static void vapic_exit(struct kvm_vcpu *vcpu)
2768{
2769 struct kvm_lapic *apic = vcpu->arch.apic;
2770
2771 if (!apic || !apic->vapic_addr)
2772 return;
2773
2774 kvm_release_page_dirty(apic->vapic_page);
2775 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
2776}
2777
b6c7a5dc
HB		 2778static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2779{
2780 int r;
2781
a4535290 2782 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
b6c7a5dc 2783 pr_debug("vcpu %d received sipi with vector # %x\n",
ad312c7c 2784 vcpu->vcpu_id, vcpu->arch.sipi_vector);
b6c7a5dc
HB		 2785 kvm_lapic_reset(vcpu);
2786 r = kvm_x86_ops->vcpu_reset(vcpu);
2787 if (r)
2788 return r;
a4535290 2789 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 2790 }
2791
3200f405 2792 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 2793 vapic_enter(vcpu);
2794
b6c7a5dc
HB		 2795preempted:
2796 if (vcpu->guest_debug.enabled)
2797 kvm_x86_ops->guest_debug_pre(vcpu);
2798
2799again:
2e53d63a
MT		 2800 if (vcpu->requests)
2801 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
2802 kvm_mmu_unload(vcpu);
2803
b6c7a5dc
HB		 2804 r = kvm_mmu_reload(vcpu);
2805 if (unlikely(r))
2806 goto out;
2807
2f52d58c
AK		 2808 if (vcpu->requests) {
2809 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 2810 __kvm_migrate_timers(vcpu);
d4acf7e7
MT		 2811 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
2812 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 2813 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
2814 &vcpu->requests)) {
2815 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
2816 r = 0;
2817 goto out;
2818 }
71c4dfaf
JR		 2819 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
2820 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2821 r = 0;
2822 goto out;
2823 }
2f52d58c 2824 }
b93463aa 2825
06e05645 2826 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
b6c7a5dc
HB		 2827 kvm_inject_pending_timer_irqs(vcpu);
2828
2829 preempt_disable();
2830
2831 kvm_x86_ops->prepare_guest_switch(vcpu);
2832 kvm_load_guest_fpu(vcpu);
2833
2834 local_irq_disable();
2835
d4acf7e7 2836 if (vcpu->requests || need_resched()) {
6c142801
AK		 2837 local_irq_enable();
2838 preempt_enable();
2839 r = 1;
2840 goto out;
2841 }
2842
b6c7a5dc
HB		 2843 if (signal_pending(current)) {
2844 local_irq_enable();
2845 preempt_enable();
2846 r = -EINTR;
2847 kvm_run->exit_reason = KVM_EXIT_INTR;
2848 ++vcpu->stat.signal_exits;
2849 goto out;
2850 }
2851
e9571ed5
MT		 2852 vcpu->guest_mode = 1;
2853 /*
2854 * Make sure that guest_mode assignment won't happen after
2855 * testing the pending IRQ vector bitmap.
2856 */
2857 smp_wmb();
2858
ad312c7c 2859 if (vcpu->arch.exception.pending)
298101da
AK		 2860 __queue_exception(vcpu);
2861 else if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 2862 kvm_x86_ops->inject_pending_irq(vcpu);
eb9774f0 2863 else
b6c7a5dc
HB		 2864 kvm_x86_ops->inject_pending_vectors(vcpu, kvm_run);
2865
b93463aa
AK		 2866 kvm_lapic_sync_to_vapic(vcpu);
2867
3200f405
MT		 2868 up_read(&vcpu->kvm->slots_lock);
2869
b6c7a5dc
HB		 2870 kvm_guest_enter();
2871
b6c7a5dc 2872
2714d1d3 2873 KVMTRACE_0D(VMENTRY, vcpu, entryexit);
b6c7a5dc
HB		 2874 kvm_x86_ops->run(vcpu, kvm_run);
2875
2876 vcpu->guest_mode = 0;
2877 local_irq_enable();
2878
2879 ++vcpu->stat.exits;
2880
2881 /*
2882 * We must have an instruction between local_irq_enable() and
2883 * kvm_guest_exit(), so the timer interrupt isn't delayed by
2884 * the interrupt shadow. The stat.exits increment will do nicely.
2885 * But we need to prevent reordering, hence this barrier():
2886 */
2887 barrier();
2888
2889 kvm_guest_exit();
2890
2891 preempt_enable();
2892
3200f405
MT		 2893 down_read(&vcpu->kvm->slots_lock);
2894
b6c7a5dc
HB		 2895 /*
2896 * Profile KVM exit RIPs:
2897 */
2898 if (unlikely(prof_on == KVM_PROFILING)) {
2899 kvm_x86_ops->cache_regs(vcpu);
ad312c7c 2900 profile_hit(KVM_PROFILING, (void *)vcpu->arch.rip);
b6c7a5dc
HB		 2901 }
2902
ad312c7c
ZX		 2903 if (vcpu->arch.exception.pending && kvm_x86_ops->exception_injected(vcpu))
2904 vcpu->arch.exception.pending = false;
298101da 2905
b93463aa
AK		 2906 kvm_lapic_sync_from_vapic(vcpu);
2907
b6c7a5dc
HB		 2908 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
2909
2910 if (r > 0) {
2911 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
2912 r = -EINTR;
2913 kvm_run->exit_reason = KVM_EXIT_INTR;
2914 ++vcpu->stat.request_irq_exits;
2915 goto out;
2916 }
e1beb1d3 2917 if (!need_resched())
b6c7a5dc 2918 goto again;
b6c7a5dc
HB		 2919 }
2920
2921out:
3200f405 2922 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 2923 if (r > 0) {
2924 kvm_resched(vcpu);
3200f405 2925 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 2926 goto preempted;
2927 }
2928
2929 post_kvm_run_save(vcpu, kvm_run);
2930
3200f405 2931 down_read(&vcpu->kvm->slots_lock);
b93463aa 2932 vapic_exit(vcpu);
3200f405 2933 up_read(&vcpu->kvm->slots_lock);
b93463aa 2934
b6c7a5dc
HB		 2935 return r;
2936}
2937
2938int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2939{
2940 int r;
2941 sigset_t sigsaved;
2942
2943 vcpu_load(vcpu);
2944
a4535290 2945 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc
HB		 2946 kvm_vcpu_block(vcpu);
2947 vcpu_put(vcpu);
2948 return -EAGAIN;
2949 }
2950
2951 if (vcpu->sigset_active)
2952 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
2953
2954 /* re-sync apic's tpr */
2955 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 2956 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 2957
ad312c7c 2958 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 2959 r = complete_pio(vcpu);
2960 if (r)
2961 goto out;
2962 }
2963#if CONFIG_HAS_IOMEM
2964 if (vcpu->mmio_needed) {
2965 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
2966 vcpu->mmio_read_completed = 1;
2967 vcpu->mmio_needed = 0;
3200f405
MT		 2968
2969 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc 2970 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 2971 vcpu->arch.mmio_fault_cr2, 0,
2972 EMULTYPE_NO_DECODE);
3200f405 2973 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 2974 if (r == EMULATE_DO_MMIO) {
2975 /*
2976 * Read-modify-write. Back to userspace.
2977 */
2978 r = 0;
2979 goto out;
2980 }
2981 }
2982#endif
2983 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL) {
2984 kvm_x86_ops->cache_regs(vcpu);
ad312c7c 2985 vcpu->arch.regs[VCPU_REGS_RAX] = kvm_run->hypercall.ret;
b6c7a5dc
HB		 2986 kvm_x86_ops->decache_regs(vcpu);
2987 }
2988
2989 r = __vcpu_run(vcpu, kvm_run);
2990
2991out:
2992 if (vcpu->sigset_active)
2993 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
2994
2995 vcpu_put(vcpu);
2996 return r;
2997}
2998
2999int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3000{
3001 vcpu_load(vcpu);
3002
3003 kvm_x86_ops->cache_regs(vcpu);
3004
ad312c7c
ZX		 3005 regs->rax = vcpu->arch.regs[VCPU_REGS_RAX];
3006 regs->rbx = vcpu->arch.regs[VCPU_REGS_RBX];
3007 regs->rcx = vcpu->arch.regs[VCPU_REGS_RCX];
3008 regs->rdx = vcpu->arch.regs[VCPU_REGS_RDX];
3009 regs->rsi = vcpu->arch.regs[VCPU_REGS_RSI];
3010 regs->rdi = vcpu->arch.regs[VCPU_REGS_RDI];
3011 regs->rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3012 regs->rbp = vcpu->arch.regs[VCPU_REGS_RBP];
b6c7a5dc 3013#ifdef CONFIG_X86_64
ad312c7c
ZX		 3014 regs->r8 = vcpu->arch.regs[VCPU_REGS_R8];
3015 regs->r9 = vcpu->arch.regs[VCPU_REGS_R9];
3016 regs->r10 = vcpu->arch.regs[VCPU_REGS_R10];
3017 regs->r11 = vcpu->arch.regs[VCPU_REGS_R11];
3018 regs->r12 = vcpu->arch.regs[VCPU_REGS_R12];
3019 regs->r13 = vcpu->arch.regs[VCPU_REGS_R13];
3020 regs->r14 = vcpu->arch.regs[VCPU_REGS_R14];
3021 regs->r15 = vcpu->arch.regs[VCPU_REGS_R15];
b6c7a5dc
HB		 3022#endif
3023
ad312c7c 3024 regs->rip = vcpu->arch.rip;
b6c7a5dc
HB		 3025 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3026
3027 /*
3028 * Don't leak debug flags in case they were set for guest debugging
3029 */
3030 if (vcpu->guest_debug.enabled && vcpu->guest_debug.singlestep)
3031 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3032
3033 vcpu_put(vcpu);
3034
3035 return 0;
3036}
3037
3038int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3039{
3040 vcpu_load(vcpu);
3041
ad312c7c
ZX		 3042 vcpu->arch.regs[VCPU_REGS_RAX] = regs->rax;
3043 vcpu->arch.regs[VCPU_REGS_RBX] = regs->rbx;
3044 vcpu->arch.regs[VCPU_REGS_RCX] = regs->rcx;
3045 vcpu->arch.regs[VCPU_REGS_RDX] = regs->rdx;
3046 vcpu->arch.regs[VCPU_REGS_RSI] = regs->rsi;
3047 vcpu->arch.regs[VCPU_REGS_RDI] = regs->rdi;
3048 vcpu->arch.regs[VCPU_REGS_RSP] = regs->rsp;
3049 vcpu->arch.regs[VCPU_REGS_RBP] = regs->rbp;
b6c7a5dc 3050#ifdef CONFIG_X86_64
ad312c7c
ZX		 3051 vcpu->arch.regs[VCPU_REGS_R8] = regs->r8;
3052 vcpu->arch.regs[VCPU_REGS_R9] = regs->r9;
3053 vcpu->arch.regs[VCPU_REGS_R10] = regs->r10;
3054 vcpu->arch.regs[VCPU_REGS_R11] = regs->r11;
3055 vcpu->arch.regs[VCPU_REGS_R12] = regs->r12;
3056 vcpu->arch.regs[VCPU_REGS_R13] = regs->r13;
3057 vcpu->arch.regs[VCPU_REGS_R14] = regs->r14;
3058 vcpu->arch.regs[VCPU_REGS_R15] = regs->r15;
b6c7a5dc
HB		 3059#endif
3060
ad312c7c 3061 vcpu->arch.rip = regs->rip;
b6c7a5dc
HB		 3062 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3063
3064 kvm_x86_ops->decache_regs(vcpu);
3065
b4f14abd
JK		 3066 vcpu->arch.exception.pending = false;
3067
b6c7a5dc
HB		 3068 vcpu_put(vcpu);
3069
3070 return 0;
3071}
3072
3073static void get_segment(struct kvm_vcpu *vcpu,
3074 struct kvm_segment *var, int seg)
3075{
14af3f3c 3076 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 3077}
3078
3079void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3080{
3081 struct kvm_segment cs;
3082
3083 get_segment(vcpu, &cs, VCPU_SREG_CS);
3084 *db = cs.db;
3085 *l = cs.l;
3086}
3087EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3088
3089int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3090 struct kvm_sregs *sregs)
3091{
3092 struct descriptor_table dt;
3093 int pending_vec;
3094
3095 vcpu_load(vcpu);
3096
3097 get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3098 get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3099 get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3100 get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3101 get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3102 get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
3103
3104 get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3105 get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
3106
3107 kvm_x86_ops->get_idt(vcpu, &dt);
3108 sregs->idt.limit = dt.limit;
3109 sregs->idt.base = dt.base;
3110 kvm_x86_ops->get_gdt(vcpu, &dt);
3111 sregs->gdt.limit = dt.limit;
3112 sregs->gdt.base = dt.base;
3113
3114 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3115 sregs->cr0 = vcpu->arch.cr0;
3116 sregs->cr2 = vcpu->arch.cr2;
3117 sregs->cr3 = vcpu->arch.cr3;
3118 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3119 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3120 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3121 sregs->apic_base = kvm_get_apic_base(vcpu);
3122
3123 if (irqchip_in_kernel(vcpu->kvm)) {
3124 memset(sregs->interrupt_bitmap, 0,
3125 sizeof sregs->interrupt_bitmap);
3126 pending_vec = kvm_x86_ops->get_irq(vcpu);
3127 if (pending_vec >= 0)
3128 set_bit(pending_vec,
3129 (unsigned long *)sregs->interrupt_bitmap);
3130 } else
ad312c7c 3131 memcpy(sregs->interrupt_bitmap, vcpu->arch.irq_pending,
b6c7a5dc
HB		 3132 sizeof sregs->interrupt_bitmap);
3133
3134 vcpu_put(vcpu);
3135
3136 return 0;
3137}
3138
62d9f0db
MT		 3139int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3140 struct kvm_mp_state *mp_state)
3141{
3142 vcpu_load(vcpu);
3143 mp_state->mp_state = vcpu->arch.mp_state;
3144 vcpu_put(vcpu);
3145 return 0;
3146}
3147
3148int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3149 struct kvm_mp_state *mp_state)
3150{
3151 vcpu_load(vcpu);
3152 vcpu->arch.mp_state = mp_state->mp_state;
3153 vcpu_put(vcpu);
3154 return 0;
3155}
3156
b6c7a5dc
HB		 3157static void set_segment(struct kvm_vcpu *vcpu,
3158 struct kvm_segment *var, int seg)
3159{
14af3f3c 3160 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 3161}
3162
37817f29
IE		 3163static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3164 struct kvm_segment *kvm_desct)
3165{
3166 kvm_desct->base = seg_desc->base0;
3167 kvm_desct->base |= seg_desc->base1 << 16;
3168 kvm_desct->base |= seg_desc->base2 << 24;
3169 kvm_desct->limit = seg_desc->limit0;
3170 kvm_desct->limit |= seg_desc->limit << 16;
3171 kvm_desct->selector = selector;
3172 kvm_desct->type = seg_desc->type;
3173 kvm_desct->present = seg_desc->p;
3174 kvm_desct->dpl = seg_desc->dpl;
3175 kvm_desct->db = seg_desc->d;
3176 kvm_desct->s = seg_desc->s;
3177 kvm_desct->l = seg_desc->l;
3178 kvm_desct->g = seg_desc->g;
3179 kvm_desct->avl = seg_desc->avl;
3180 if (!selector)
3181 kvm_desct->unusable = 1;
3182 else
3183 kvm_desct->unusable = 0;
3184 kvm_desct->padding = 0;
3185}
3186
3187static void get_segment_descritptor_dtable(struct kvm_vcpu *vcpu,
3188 u16 selector,
3189 struct descriptor_table *dtable)
3190{
3191 if (selector & 1 << 2) {
3192 struct kvm_segment kvm_seg;
3193
3194 get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
3195
3196 if (kvm_seg.unusable)
3197 dtable->limit = 0;
3198 else
3199 dtable->limit = kvm_seg.limit;
3200 dtable->base = kvm_seg.base;
3201 }
3202 else
3203 kvm_x86_ops->get_gdt(vcpu, dtable);
3204}
3205
3206/* allowed just for 8 bytes segments */
3207static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3208 struct desc_struct *seg_desc)
3209{
3210 struct descriptor_table dtable;
3211 u16 index = selector >> 3;
3212
3213 get_segment_descritptor_dtable(vcpu, selector, &dtable);
3214
3215 if (dtable.limit < index * 8 + 7) {
3216 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
3217 return 1;
3218 }
3219 return kvm_read_guest(vcpu->kvm, dtable.base + index * 8, seg_desc, 8);
3220}
3221
3222/* allowed just for 8 bytes segments */
3223static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3224 struct desc_struct *seg_desc)
3225{
3226 struct descriptor_table dtable;
3227 u16 index = selector >> 3;
3228
3229 get_segment_descritptor_dtable(vcpu, selector, &dtable);
3230
3231 if (dtable.limit < index * 8 + 7)
3232 return 1;
3233 return kvm_write_guest(vcpu->kvm, dtable.base + index * 8, seg_desc, 8);
3234}
3235
3236static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
3237 struct desc_struct *seg_desc)
3238{
3239 u32 base_addr;
3240
3241 base_addr = seg_desc->base0;
3242 base_addr |= (seg_desc->base1 << 16);
3243 base_addr |= (seg_desc->base2 << 24);
3244
3245 return base_addr;
3246}
3247
3248static int load_tss_segment32(struct kvm_vcpu *vcpu,
3249 struct desc_struct *seg_desc,
3250 struct tss_segment_32 *tss)
3251{
3252 u32 base_addr;
3253
3254 base_addr = get_tss_base_addr(vcpu, seg_desc);
3255
3256 return kvm_read_guest(vcpu->kvm, base_addr, tss,
3257 sizeof(struct tss_segment_32));
3258}
3259
3260static int save_tss_segment32(struct kvm_vcpu *vcpu,
3261 struct desc_struct *seg_desc,
3262 struct tss_segment_32 *tss)
3263{
3264 u32 base_addr;
3265
3266 base_addr = get_tss_base_addr(vcpu, seg_desc);
3267
3268 return kvm_write_guest(vcpu->kvm, base_addr, tss,
3269 sizeof(struct tss_segment_32));
3270}
3271
3272static int load_tss_segment16(struct kvm_vcpu *vcpu,
3273 struct desc_struct *seg_desc,
3274 struct tss_segment_16 *tss)
3275{
3276 u32 base_addr;
3277
3278 base_addr = get_tss_base_addr(vcpu, seg_desc);
3279
3280 return kvm_read_guest(vcpu->kvm, base_addr, tss,
3281 sizeof(struct tss_segment_16));
3282}
3283
3284static int save_tss_segment16(struct kvm_vcpu *vcpu,
3285 struct desc_struct *seg_desc,
3286 struct tss_segment_16 *tss)
3287{
3288 u32 base_addr;
3289
3290 base_addr = get_tss_base_addr(vcpu, seg_desc);
3291
3292 return kvm_write_guest(vcpu->kvm, base_addr, tss,
3293 sizeof(struct tss_segment_16));
3294}
3295
3296static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
3297{
3298 struct kvm_segment kvm_seg;
3299
3300 get_segment(vcpu, &kvm_seg, seg);
3301 return kvm_seg.selector;
3302}
3303
3304static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
3305 u16 selector,
3306 struct kvm_segment *kvm_seg)
3307{
3308 struct desc_struct seg_desc;
3309
3310 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
3311 return 1;
3312 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
3313 return 0;
3314}
3315
3316static int load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3317 int type_bits, int seg)
3318{
3319 struct kvm_segment kvm_seg;
3320
3321 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
3322 return 1;
3323 kvm_seg.type |= type_bits;
3324
3325 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
3326 seg != VCPU_SREG_LDTR)
3327 if (!kvm_seg.s)
3328 kvm_seg.unusable = 1;
3329
3330 set_segment(vcpu, &kvm_seg, seg);
3331 return 0;
3332}
3333
3334static void save_state_to_tss32(struct kvm_vcpu *vcpu,
3335 struct tss_segment_32 *tss)
3336{
3337 tss->cr3 = vcpu->arch.cr3;
3338 tss->eip = vcpu->arch.rip;
3339 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
3340 tss->eax = vcpu->arch.regs[VCPU_REGS_RAX];
3341 tss->ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3342 tss->edx = vcpu->arch.regs[VCPU_REGS_RDX];
3343 tss->ebx = vcpu->arch.regs[VCPU_REGS_RBX];
3344 tss->esp = vcpu->arch.regs[VCPU_REGS_RSP];
3345 tss->ebp = vcpu->arch.regs[VCPU_REGS_RBP];
3346 tss->esi = vcpu->arch.regs[VCPU_REGS_RSI];
3347 tss->edi = vcpu->arch.regs[VCPU_REGS_RDI];
3348
3349 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3350 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3351 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3352 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3353 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
3354 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
3355 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3356 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3357}
3358
3359static int load_state_from_tss32(struct kvm_vcpu *vcpu,
3360 struct tss_segment_32 *tss)
3361{
3362 kvm_set_cr3(vcpu, tss->cr3);
3363
3364 vcpu->arch.rip = tss->eip;
3365 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
3366
3367 vcpu->arch.regs[VCPU_REGS_RAX] = tss->eax;
3368 vcpu->arch.regs[VCPU_REGS_RCX] = tss->ecx;
3369 vcpu->arch.regs[VCPU_REGS_RDX] = tss->edx;
3370 vcpu->arch.regs[VCPU_REGS_RBX] = tss->ebx;
3371 vcpu->arch.regs[VCPU_REGS_RSP] = tss->esp;
3372 vcpu->arch.regs[VCPU_REGS_RBP] = tss->ebp;
3373 vcpu->arch.regs[VCPU_REGS_RSI] = tss->esi;
3374 vcpu->arch.regs[VCPU_REGS_RDI] = tss->edi;
3375
3376 if (load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
3377 return 1;
3378
3379 if (load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
3380 return 1;
3381
3382 if (load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
3383 return 1;
3384
3385 if (load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
3386 return 1;
3387
3388 if (load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
3389 return 1;
3390
3391 if (load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
3392 return 1;
3393
3394 if (load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
3395 return 1;
3396 return 0;
3397}
3398
3399static void save_state_to_tss16(struct kvm_vcpu *vcpu,
3400 struct tss_segment_16 *tss)
3401{
3402 tss->ip = vcpu->arch.rip;
3403 tss->flag = kvm_x86_ops->get_rflags(vcpu);
3404 tss->ax = vcpu->arch.regs[VCPU_REGS_RAX];
3405 tss->cx = vcpu->arch.regs[VCPU_REGS_RCX];
3406 tss->dx = vcpu->arch.regs[VCPU_REGS_RDX];
3407 tss->bx = vcpu->arch.regs[VCPU_REGS_RBX];
3408 tss->sp = vcpu->arch.regs[VCPU_REGS_RSP];
3409 tss->bp = vcpu->arch.regs[VCPU_REGS_RBP];
3410 tss->si = vcpu->arch.regs[VCPU_REGS_RSI];
3411 tss->di = vcpu->arch.regs[VCPU_REGS_RDI];
3412
3413 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3414 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3415 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3416 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3417 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3418 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3419}
3420
3421static int load_state_from_tss16(struct kvm_vcpu *vcpu,
3422 struct tss_segment_16 *tss)
3423{
3424 vcpu->arch.rip = tss->ip;
3425 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
3426 vcpu->arch.regs[VCPU_REGS_RAX] = tss->ax;
3427 vcpu->arch.regs[VCPU_REGS_RCX] = tss->cx;
3428 vcpu->arch.regs[VCPU_REGS_RDX] = tss->dx;
3429 vcpu->arch.regs[VCPU_REGS_RBX] = tss->bx;
3430 vcpu->arch.regs[VCPU_REGS_RSP] = tss->sp;
3431 vcpu->arch.regs[VCPU_REGS_RBP] = tss->bp;
3432 vcpu->arch.regs[VCPU_REGS_RSI] = tss->si;
3433 vcpu->arch.regs[VCPU_REGS_RDI] = tss->di;
3434
3435 if (load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
3436 return 1;
3437
3438 if (load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
3439 return 1;
3440
3441 if (load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
3442 return 1;
3443
3444 if (load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
3445 return 1;
3446
3447 if (load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
3448 return 1;
3449 return 0;
3450}
3451
8b2cf73c 3452static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
37817f29
IE		 3453 struct desc_struct *cseg_desc,
3454 struct desc_struct *nseg_desc)
3455{
3456 struct tss_segment_16 tss_segment_16;
3457 int ret = 0;
3458
3459 if (load_tss_segment16(vcpu, cseg_desc, &tss_segment_16))
3460 goto out;
3461
3462 save_state_to_tss16(vcpu, &tss_segment_16);
3463 save_tss_segment16(vcpu, cseg_desc, &tss_segment_16);
3464
3465 if (load_tss_segment16(vcpu, nseg_desc, &tss_segment_16))
3466 goto out;
3467 if (load_state_from_tss16(vcpu, &tss_segment_16))
3468 goto out;
3469
3470 ret = 1;
3471out:
3472 return ret;
3473}
3474
8b2cf73c 3475static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
37817f29
IE		 3476 struct desc_struct *cseg_desc,
3477 struct desc_struct *nseg_desc)
3478{
3479 struct tss_segment_32 tss_segment_32;
3480 int ret = 0;
3481
3482 if (load_tss_segment32(vcpu, cseg_desc, &tss_segment_32))
3483 goto out;
3484
3485 save_state_to_tss32(vcpu, &tss_segment_32);
3486 save_tss_segment32(vcpu, cseg_desc, &tss_segment_32);
3487
3488 if (load_tss_segment32(vcpu, nseg_desc, &tss_segment_32))
3489 goto out;
3490 if (load_state_from_tss32(vcpu, &tss_segment_32))
3491 goto out;
3492
3493 ret = 1;
3494out:
3495 return ret;
3496}
3497
3498int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
3499{
3500 struct kvm_segment tr_seg;
3501 struct desc_struct cseg_desc;
3502 struct desc_struct nseg_desc;
3503 int ret = 0;
3504
3505 get_segment(vcpu, &tr_seg, VCPU_SREG_TR);
3506
3507 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
3508 goto out;
3509
3510 if (load_guest_segment_descriptor(vcpu, tr_seg.selector, &cseg_desc))
3511 goto out;
3512
3513
3514 if (reason != TASK_SWITCH_IRET) {
3515 int cpl;
3516
3517 cpl = kvm_x86_ops->get_cpl(vcpu);
3518 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
3519 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
3520 return 1;
3521 }
3522 }
3523
3524 if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) {
3525 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
3526 return 1;
3527 }
3528
3529 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 3530 cseg_desc.type &= ~(1 << 1); //clear the B flag
37817f29
IE		 3531 save_guest_segment_descriptor(vcpu, tr_seg.selector,
3532 &cseg_desc);
3533 }
3534
3535 if (reason == TASK_SWITCH_IRET) {
3536 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3537 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
3538 }
3539
3540 kvm_x86_ops->skip_emulated_instruction(vcpu);
3541 kvm_x86_ops->cache_regs(vcpu);
3542
3543 if (nseg_desc.type & 8)
3544 ret = kvm_task_switch_32(vcpu, tss_selector, &cseg_desc,
3545 &nseg_desc);
3546 else
3547 ret = kvm_task_switch_16(vcpu, tss_selector, &cseg_desc,
3548 &nseg_desc);
3549
3550 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
3551 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3552 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
3553 }
3554
3555 if (reason != TASK_SWITCH_IRET) {
3fe913e7 3556 nseg_desc.type |= (1 << 1);
37817f29
IE		 3557 save_guest_segment_descriptor(vcpu, tss_selector,
3558 &nseg_desc);
3559 }
3560
3561 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
3562 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
3563 tr_seg.type = 11;
3564 set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
3565out:
3566 kvm_x86_ops->decache_regs(vcpu);
3567 return ret;
3568}
3569EXPORT_SYMBOL_GPL(kvm_task_switch);
3570
b6c7a5dc
HB		 3571int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
3572 struct kvm_sregs *sregs)
3573{
3574 int mmu_reset_needed = 0;
3575 int i, pending_vec, max_bits;
3576 struct descriptor_table dt;
3577
3578 vcpu_load(vcpu);
3579
3580 dt.limit = sregs->idt.limit;
3581 dt.base = sregs->idt.base;
3582 kvm_x86_ops->set_idt(vcpu, &dt);
3583 dt.limit = sregs->gdt.limit;
3584 dt.base = sregs->gdt.base;
3585 kvm_x86_ops->set_gdt(vcpu, &dt);
3586
ad312c7c
ZX		 3587 vcpu->arch.cr2 = sregs->cr2;
3588 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
3589 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 3590
2d3ad1f4 3591 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 3592
ad312c7c 3593 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 3594 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 3595 kvm_set_apic_base(vcpu, sregs->apic_base);
3596
3597 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3598
ad312c7c 3599 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 3600 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 3601 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 3602
ad312c7c 3603 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 3604 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3605 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 3606 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 3607
3608 if (mmu_reset_needed)
3609 kvm_mmu_reset_context(vcpu);
3610
3611 if (!irqchip_in_kernel(vcpu->kvm)) {
ad312c7c
ZX		 3612 memcpy(vcpu->arch.irq_pending, sregs->interrupt_bitmap,
3613 sizeof vcpu->arch.irq_pending);
3614 vcpu->arch.irq_summary = 0;
3615 for (i = 0; i < ARRAY_SIZE(vcpu->arch.irq_pending); ++i)
3616 if (vcpu->arch.irq_pending[i])
3617 __set_bit(i, &vcpu->arch.irq_summary);
b6c7a5dc
HB		 3618 } else {
3619 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
3620 pending_vec = find_first_bit(
3621 (const unsigned long *)sregs->interrupt_bitmap,
3622 max_bits);
3623 /* Only pending external irq is handled here */
3624 if (pending_vec < max_bits) {
3625 kvm_x86_ops->set_irq(vcpu, pending_vec);
3626 pr_debug("Set back pending irq %d\n",
3627 pending_vec);
3628 }
3629 }
3630
3631 set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3632 set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3633 set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3634 set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3635 set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3636 set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
3637
3638 set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3639 set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
3640
3641 vcpu_put(vcpu);
3642
3643 return 0;
3644}
3645
3646int kvm_arch_vcpu_ioctl_debug_guest(struct kvm_vcpu *vcpu,
3647 struct kvm_debug_guest *dbg)
3648{
3649 int r;
3650
3651 vcpu_load(vcpu);
3652
3653 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
3654
3655 vcpu_put(vcpu);
3656
3657 return r;
3658}
3659
d0752060
HB		 3660/*
3661 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
3662 * we have asm/x86/processor.h
3663 */
3664struct fxsave {
3665 u16 cwd;
3666 u16 swd;
3667 u16 twd;
3668 u16 fop;
3669 u64 rip;
3670 u64 rdp;
3671 u32 mxcsr;
3672 u32 mxcsr_mask;
3673 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
3674#ifdef CONFIG_X86_64
3675 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
3676#else
3677 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
3678#endif
3679};
3680
8b006791
ZX		 3681/*
3682 * Translate a guest virtual address to a guest physical address.
3683 */
3684int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
3685 struct kvm_translation *tr)
3686{
3687 unsigned long vaddr = tr->linear_address;
3688 gpa_t gpa;
3689
3690 vcpu_load(vcpu);
72dc67a6 3691 down_read(&vcpu->kvm->slots_lock);
ad312c7c 3692 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 3693 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 3694 tr->physical_address = gpa;
3695 tr->valid = gpa != UNMAPPED_GVA;
3696 tr->writeable = 1;
3697 tr->usermode = 0;
8b006791
ZX		 3698 vcpu_put(vcpu);
3699
3700 return 0;
3701}
3702
d0752060
HB		 3703int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
3704{
ad312c7c 3705 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 3706
3707 vcpu_load(vcpu);
3708
3709 memcpy(fpu->fpr, fxsave->st_space, 128);
3710 fpu->fcw = fxsave->cwd;
3711 fpu->fsw = fxsave->swd;
3712 fpu->ftwx = fxsave->twd;
3713 fpu->last_opcode = fxsave->fop;
3714 fpu->last_ip = fxsave->rip;
3715 fpu->last_dp = fxsave->rdp;
3716 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
3717
3718 vcpu_put(vcpu);
3719
3720 return 0;
3721}
3722
3723int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
3724{
ad312c7c 3725 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 3726
3727 vcpu_load(vcpu);
3728
3729 memcpy(fxsave->st_space, fpu->fpr, 128);
3730 fxsave->cwd = fpu->fcw;
3731 fxsave->swd = fpu->fsw;
3732 fxsave->twd = fpu->ftwx;
3733 fxsave->fop = fpu->last_opcode;
3734 fxsave->rip = fpu->last_ip;
3735 fxsave->rdp = fpu->last_dp;
3736 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
3737
3738 vcpu_put(vcpu);
3739
3740 return 0;
3741}
3742
3743void fx_init(struct kvm_vcpu *vcpu)
3744{
3745 unsigned after_mxcsr_mask;
3746
bc1a34f1
AA		 3747 /*
3748 * Touch the fpu the first time in non atomic context as if
3749 * this is the first fpu instruction the exception handler
3750 * will fire before the instruction returns and it'll have to
3751 * allocate ram with GFP_KERNEL.
3752 */
3753 if (!used_math())
3754 fx_save(&vcpu->arch.host_fx_image);
3755
d0752060
HB		 3756 /* Initialize guest FPU by resetting ours and saving into guest's */
3757 preempt_disable();
ad312c7c 3758 fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 3759 fx_finit();
ad312c7c
ZX		 3760 fx_save(&vcpu->arch.guest_fx_image);
3761 fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 3762 preempt_enable();
3763
ad312c7c 3764 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 3765 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 3766 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
3767 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 3768 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
3769}
3770EXPORT_SYMBOL_GPL(fx_init);
3771
3772void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
3773{
3774 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
3775 return;
3776
3777 vcpu->guest_fpu_loaded = 1;
ad312c7c
ZX		 3778 fx_save(&vcpu->arch.host_fx_image);
3779 fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 3780}
3781EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
3782
3783void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
3784{
3785 if (!vcpu->guest_fpu_loaded)
3786 return;
3787
3788 vcpu->guest_fpu_loaded = 0;
ad312c7c
ZX		 3789 fx_save(&vcpu->arch.guest_fx_image);
3790 fx_restore(&vcpu->arch.host_fx_image);
f096ed85 3791 ++vcpu->stat.fpu_reload;
d0752060
HB		 3792}
3793EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 3794
3795void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
3796{
3797 kvm_x86_ops->vcpu_free(vcpu);
3798}
3799
3800struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
3801 unsigned int id)
3802{
26e5215f
AK		 3803 return kvm_x86_ops->vcpu_create(kvm, id);
3804}
e9b11c17 3805
26e5215f
AK		 3806int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
3807{
3808 int r;
e9b11c17
ZX		 3809
3810 /* We do fxsave: this must be aligned. */
ad312c7c 3811 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17
ZX		 3812
3813 vcpu_load(vcpu);
3814 r = kvm_arch_vcpu_reset(vcpu);
3815 if (r == 0)
3816 r = kvm_mmu_setup(vcpu);
3817 vcpu_put(vcpu);
3818 if (r < 0)
3819 goto free_vcpu;
3820
26e5215f 3821 return 0;
e9b11c17
ZX		 3822free_vcpu:
3823 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 3824 return r;
e9b11c17
ZX		 3825}
3826
d40ccc62 3827void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 3828{
3829 vcpu_load(vcpu);
3830 kvm_mmu_unload(vcpu);
3831 vcpu_put(vcpu);
3832
3833 kvm_x86_ops->vcpu_free(vcpu);
3834}
3835
3836int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
3837{
3838 return kvm_x86_ops->vcpu_reset(vcpu);
3839}
3840
3841void kvm_arch_hardware_enable(void *garbage)
3842{
3843 kvm_x86_ops->hardware_enable(garbage);
3844}
3845
3846void kvm_arch_hardware_disable(void *garbage)
3847{
3848 kvm_x86_ops->hardware_disable(garbage);
3849}
3850
3851int kvm_arch_hardware_setup(void)
3852{
3853 return kvm_x86_ops->hardware_setup();
3854}
3855
3856void kvm_arch_hardware_unsetup(void)
3857{
3858 kvm_x86_ops->hardware_unsetup();
3859}
3860
3861void kvm_arch_check_processor_compat(void *rtn)
3862{
3863 kvm_x86_ops->check_processor_compatibility(rtn);
3864}
3865
3866int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
3867{
3868 struct page *page;
3869 struct kvm *kvm;
3870 int r;
3871
3872 BUG_ON(vcpu->kvm == NULL);
3873 kvm = vcpu->kvm;
3874
ad312c7c 3875 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
e9b11c17 3876 if (!irqchip_in_kernel(kvm) || vcpu->vcpu_id == 0)
a4535290 3877 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 3878 else
a4535290 3879 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 3880
3881 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
3882 if (!page) {
3883 r = -ENOMEM;
3884 goto fail;
3885 }
ad312c7c 3886 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 3887
3888 r = kvm_mmu_create(vcpu);
3889 if (r < 0)
3890 goto fail_free_pio_data;
3891
3892 if (irqchip_in_kernel(kvm)) {
3893 r = kvm_create_lapic(vcpu);
3894 if (r < 0)
3895 goto fail_mmu_destroy;
3896 }
3897
3898 return 0;
3899
3900fail_mmu_destroy:
3901 kvm_mmu_destroy(vcpu);
3902fail_free_pio_data:
ad312c7c 3903 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 3904fail:
3905 return r;
3906}
3907
3908void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
3909{
3910 kvm_free_lapic(vcpu);
3200f405 3911 down_read(&vcpu->kvm->slots_lock);
e9b11c17 3912 kvm_mmu_destroy(vcpu);
3200f405 3913 up_read(&vcpu->kvm->slots_lock);
ad312c7c 3914 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 3915}
d19a9cd2
ZX		 3916
3917struct kvm *kvm_arch_create_vm(void)
3918{
3919 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
3920
3921 if (!kvm)
3922 return ERR_PTR(-ENOMEM);
3923
f05e70ac 3924 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
d19a9cd2
ZX		 3925
3926 return kvm;
3927}
3928
3929static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
3930{
3931 vcpu_load(vcpu);
3932 kvm_mmu_unload(vcpu);
3933 vcpu_put(vcpu);
3934}
3935
3936static void kvm_free_vcpus(struct kvm *kvm)
3937{
3938 unsigned int i;
3939
3940 /*
3941 * Unpin any mmu pages first.
3942 */
3943 for (i = 0; i < KVM_MAX_VCPUS; ++i)
3944 if (kvm->vcpus[i])
3945 kvm_unload_vcpu_mmu(kvm->vcpus[i]);
3946 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
3947 if (kvm->vcpus[i]) {
3948 kvm_arch_vcpu_free(kvm->vcpus[i]);
3949 kvm->vcpus[i] = NULL;
3950 }
3951 }
3952
3953}
3954
3955void kvm_arch_destroy_vm(struct kvm *kvm)
3956{
7837699f 3957 kvm_free_pit(kvm);
d7deeeb0
ZX		 3958 kfree(kvm->arch.vpic);
3959 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 3960 kvm_free_vcpus(kvm);
3961 kvm_free_physmem(kvm);
3d45830c
AK		 3962 if (kvm->arch.apic_access_page)
3963 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 3964 if (kvm->arch.ept_identity_pagetable)
3965 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 3966 kfree(kvm);
3967}
0de10343
ZX		 3968
3969int kvm_arch_set_memory_region(struct kvm *kvm,
3970 struct kvm_userspace_memory_region *mem,
3971 struct kvm_memory_slot old,
3972 int user_alloc)
3973{
3974 int npages = mem->memory_size >> PAGE_SHIFT;
3975 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
3976
3977 /*To keep backward compatibility with older userspace,
3978 *x86 needs to hanlde !user_alloc case.
3979 */
3980 if (!user_alloc) {
3981 if (npages && !old.rmap) {
72dc67a6 3982 down_write(&current->mm->mmap_sem);
0de10343
ZX		 3983 memslot->userspace_addr = do_mmap(NULL, 0,
3984 npages * PAGE_SIZE,
3985 PROT_READ | PROT_WRITE,
3986 MAP_SHARED | MAP_ANONYMOUS,
3987 0);
72dc67a6 3988 up_write(&current->mm->mmap_sem);
0de10343
ZX		 3989
3990 if (IS_ERR((void *)memslot->userspace_addr))
3991 return PTR_ERR((void *)memslot->userspace_addr);
3992 } else {
3993 if (!old.user_alloc && old.rmap) {
3994 int ret;
3995
72dc67a6 3996 down_write(&current->mm->mmap_sem);
0de10343
ZX		 3997 ret = do_munmap(current->mm, old.userspace_addr,
3998 old.npages * PAGE_SIZE);
72dc67a6 3999 up_write(&current->mm->mmap_sem);
0de10343
ZX		 4000 if (ret < 0)
4001 printk(KERN_WARNING
4002 "kvm_vm_ioctl_set_memory_region: "
4003 "failed to munmap memory\n");
4004 }
4005 }
4006 }
4007
f05e70ac 4008 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 4009 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4010 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4011 }
4012
4013 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
4014 kvm_flush_remote_tlbs(kvm);
4015
4016 return 0;
4017}
1d737c8a
ZX		 4018
4019int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4020{
a4535290
AK		 4021 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
4022 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED;
1d737c8a 4023}
5736199a
ZX		 4024
4025static void vcpu_kick_intr(void *info)
4026{
4027#ifdef DEBUG
4028 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)info;
4029 printk(KERN_DEBUG "vcpu_kick_intr %p \n", vcpu);
4030#endif
4031}
4032
4033void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4034{
4035 int ipi_pcpu = vcpu->cpu;
e9571ed5 4036 int cpu = get_cpu();
5736199a
ZX		 4037
4038 if (waitqueue_active(&vcpu->wq)) {
4039 wake_up_interruptible(&vcpu->wq);
4040 ++vcpu->stat.halt_wakeup;
4041 }
e9571ed5
MT		 4042 /*
4043 * We may be called synchronously with irqs disabled in guest mode,
4044 * So need not to call smp_call_function_single() in that case.
4045 */
4046 if (vcpu->guest_mode && vcpu->cpu != cpu)
8691e5a8 4047 smp_call_function_single(ipi_pcpu, vcpu_kick_intr, vcpu, 0);
e9571ed5 4048 put_cpu();
5736199a 4049}
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