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Commit | Line | Data |
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043405e1 CO |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * derived from drivers/kvm/kvm_main.c | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
7 | * Copyright (C) 2008 Qumranet, Inc. |
8 | * Copyright IBM Corporation, 2008 | |
9611c187 | 9 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
043405e1 CO |
10 | * |
11 | * Authors: | |
12 | * Avi Kivity <avi@qumranet.com> | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
14 | * Amit Shah <amit.shah@qumranet.com> |
15 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
16 | * |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | * | |
20 | */ | |
21 | ||
edf88417 | 22 | #include <linux/kvm_host.h> |
313a3dc7 | 23 | #include "irq.h" |
1d737c8a | 24 | #include "mmu.h" |
7837699f | 25 | #include "i8254.h" |
37817f29 | 26 | #include "tss.h" |
5fdbf976 | 27 | #include "kvm_cache_regs.h" |
26eef70c | 28 | #include "x86.h" |
00b27a3e | 29 | #include "cpuid.h" |
c9eab58f | 30 | #include "assigned-dev.h" |
313a3dc7 | 31 | |
18068523 | 32 | #include <linux/clocksource.h> |
4d5c5d0f | 33 | #include <linux/interrupt.h> |
313a3dc7 CO |
34 | #include <linux/kvm.h> |
35 | #include <linux/fs.h> | |
36 | #include <linux/vmalloc.h> | |
5fb76f9b | 37 | #include <linux/module.h> |
0de10343 | 38 | #include <linux/mman.h> |
2bacc55c | 39 | #include <linux/highmem.h> |
19de40a8 | 40 | #include <linux/iommu.h> |
62c476c7 | 41 | #include <linux/intel-iommu.h> |
c8076604 | 42 | #include <linux/cpufreq.h> |
18863bdd | 43 | #include <linux/user-return-notifier.h> |
a983fb23 | 44 | #include <linux/srcu.h> |
5a0e3ad6 | 45 | #include <linux/slab.h> |
ff9d07a0 | 46 | #include <linux/perf_event.h> |
7bee342a | 47 | #include <linux/uaccess.h> |
af585b92 | 48 | #include <linux/hash.h> |
a1b60c1c | 49 | #include <linux/pci.h> |
16e8d74d MT |
50 | #include <linux/timekeeper_internal.h> |
51 | #include <linux/pvclock_gtod.h> | |
aec51dc4 | 52 | #include <trace/events/kvm.h> |
2ed152af | 53 | |
229456fc MT |
54 | #define CREATE_TRACE_POINTS |
55 | #include "trace.h" | |
043405e1 | 56 | |
24f1e32c | 57 | #include <asm/debugreg.h> |
d825ed0a | 58 | #include <asm/msr.h> |
a5f61300 | 59 | #include <asm/desc.h> |
0bed3b56 | 60 | #include <asm/mtrr.h> |
890ca9ae | 61 | #include <asm/mce.h> |
f89e32e0 | 62 | #include <linux/kernel_stat.h> |
1361b83a | 63 | #include <asm/fpu-internal.h> /* Ugh! */ |
98918833 | 64 | #include <asm/xcr.h> |
1d5f066e | 65 | #include <asm/pvclock.h> |
217fc9cf | 66 | #include <asm/div64.h> |
043405e1 | 67 | |
313a3dc7 | 68 | #define MAX_IO_MSRS 256 |
890ca9ae | 69 | #define KVM_MAX_MCE_BANKS 32 |
5854dbca | 70 | #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P) |
890ca9ae | 71 | |
0f65dd70 AK |
72 | #define emul_to_vcpu(ctxt) \ |
73 | container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) | |
74 | ||
50a37eb4 JR |
75 | /* EFER defaults: |
76 | * - enable syscall per default because its emulated by KVM | |
77 | * - enable LME and LMA per default on 64 bit KVM | |
78 | */ | |
79 | #ifdef CONFIG_X86_64 | |
1260edbe LJ |
80 | static |
81 | u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); | |
50a37eb4 | 82 | #else |
1260edbe | 83 | static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); |
50a37eb4 | 84 | #endif |
313a3dc7 | 85 | |
ba1389b7 AK |
86 | #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM |
87 | #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU | |
417bc304 | 88 | |
cb142eb7 | 89 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
7460fb4a | 90 | static void process_nmi(struct kvm_vcpu *vcpu); |
6addfc42 | 91 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); |
674eea0f | 92 | |
97896d04 | 93 | struct kvm_x86_ops *kvm_x86_ops; |
5fdbf976 | 94 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 95 | |
476bc001 RR |
96 | static bool ignore_msrs = 0; |
97 | module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); | |
ed85c068 | 98 | |
9ed96e87 MT |
99 | unsigned int min_timer_period_us = 500; |
100 | module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); | |
101 | ||
92a1f12d JR |
102 | bool kvm_has_tsc_control; |
103 | EXPORT_SYMBOL_GPL(kvm_has_tsc_control); | |
104 | u32 kvm_max_guest_tsc_khz; | |
105 | EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); | |
106 | ||
cc578287 ZA |
107 | /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ |
108 | static u32 tsc_tolerance_ppm = 250; | |
109 | module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); | |
110 | ||
d0659d94 MT |
111 | /* lapic timer advance (tscdeadline mode only) in nanoseconds */ |
112 | unsigned int lapic_timer_advance_ns = 0; | |
113 | module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR); | |
114 | ||
16a96021 MT |
115 | static bool backwards_tsc_observed = false; |
116 | ||
18863bdd AK |
117 | #define KVM_NR_SHARED_MSRS 16 |
118 | ||
119 | struct kvm_shared_msrs_global { | |
120 | int nr; | |
2bf78fa7 | 121 | u32 msrs[KVM_NR_SHARED_MSRS]; |
18863bdd AK |
122 | }; |
123 | ||
124 | struct kvm_shared_msrs { | |
125 | struct user_return_notifier urn; | |
126 | bool registered; | |
2bf78fa7 SY |
127 | struct kvm_shared_msr_values { |
128 | u64 host; | |
129 | u64 curr; | |
130 | } values[KVM_NR_SHARED_MSRS]; | |
18863bdd AK |
131 | }; |
132 | ||
133 | static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; | |
013f6a5d | 134 | static struct kvm_shared_msrs __percpu *shared_msrs; |
18863bdd | 135 | |
417bc304 | 136 | struct kvm_stats_debugfs_item debugfs_entries[] = { |
ba1389b7 AK |
137 | { "pf_fixed", VCPU_STAT(pf_fixed) }, |
138 | { "pf_guest", VCPU_STAT(pf_guest) }, | |
139 | { "tlb_flush", VCPU_STAT(tlb_flush) }, | |
140 | { "invlpg", VCPU_STAT(invlpg) }, | |
141 | { "exits", VCPU_STAT(exits) }, | |
142 | { "io_exits", VCPU_STAT(io_exits) }, | |
143 | { "mmio_exits", VCPU_STAT(mmio_exits) }, | |
144 | { "signal_exits", VCPU_STAT(signal_exits) }, | |
145 | { "irq_window", VCPU_STAT(irq_window_exits) }, | |
f08864b4 | 146 | { "nmi_window", VCPU_STAT(nmi_window_exits) }, |
ba1389b7 | 147 | { "halt_exits", VCPU_STAT(halt_exits) }, |
f7819512 | 148 | { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, |
ba1389b7 | 149 | { "halt_wakeup", VCPU_STAT(halt_wakeup) }, |
f11c3a8d | 150 | { "hypercalls", VCPU_STAT(hypercalls) }, |
ba1389b7 AK |
151 | { "request_irq", VCPU_STAT(request_irq_exits) }, |
152 | { "irq_exits", VCPU_STAT(irq_exits) }, | |
153 | { "host_state_reload", VCPU_STAT(host_state_reload) }, | |
154 | { "efer_reload", VCPU_STAT(efer_reload) }, | |
155 | { "fpu_reload", VCPU_STAT(fpu_reload) }, | |
156 | { "insn_emulation", VCPU_STAT(insn_emulation) }, | |
157 | { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, | |
fa89a817 | 158 | { "irq_injections", VCPU_STAT(irq_injections) }, |
c4abb7c9 | 159 | { "nmi_injections", VCPU_STAT(nmi_injections) }, |
4cee5764 AK |
160 | { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, |
161 | { "mmu_pte_write", VM_STAT(mmu_pte_write) }, | |
162 | { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, | |
163 | { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, | |
164 | { "mmu_flooded", VM_STAT(mmu_flooded) }, | |
165 | { "mmu_recycled", VM_STAT(mmu_recycled) }, | |
dfc5aa00 | 166 | { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, |
4731d4c7 | 167 | { "mmu_unsync", VM_STAT(mmu_unsync) }, |
0f74a24c | 168 | { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, |
05da4558 | 169 | { "largepages", VM_STAT(lpages) }, |
417bc304 HB |
170 | { NULL } |
171 | }; | |
172 | ||
2acf923e DC |
173 | u64 __read_mostly host_xcr0; |
174 | ||
b6785def | 175 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); |
d6aa1000 | 176 | |
af585b92 GN |
177 | static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) |
178 | { | |
179 | int i; | |
180 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) | |
181 | vcpu->arch.apf.gfns[i] = ~0; | |
182 | } | |
183 | ||
18863bdd AK |
184 | static void kvm_on_user_return(struct user_return_notifier *urn) |
185 | { | |
186 | unsigned slot; | |
18863bdd AK |
187 | struct kvm_shared_msrs *locals |
188 | = container_of(urn, struct kvm_shared_msrs, urn); | |
2bf78fa7 | 189 | struct kvm_shared_msr_values *values; |
18863bdd AK |
190 | |
191 | for (slot = 0; slot < shared_msrs_global.nr; ++slot) { | |
2bf78fa7 SY |
192 | values = &locals->values[slot]; |
193 | if (values->host != values->curr) { | |
194 | wrmsrl(shared_msrs_global.msrs[slot], values->host); | |
195 | values->curr = values->host; | |
18863bdd AK |
196 | } |
197 | } | |
198 | locals->registered = false; | |
199 | user_return_notifier_unregister(urn); | |
200 | } | |
201 | ||
2bf78fa7 | 202 | static void shared_msr_update(unsigned slot, u32 msr) |
18863bdd | 203 | { |
18863bdd | 204 | u64 value; |
013f6a5d MT |
205 | unsigned int cpu = smp_processor_id(); |
206 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
18863bdd | 207 | |
2bf78fa7 SY |
208 | /* only read, and nobody should modify it at this time, |
209 | * so don't need lock */ | |
210 | if (slot >= shared_msrs_global.nr) { | |
211 | printk(KERN_ERR "kvm: invalid MSR slot!"); | |
212 | return; | |
213 | } | |
214 | rdmsrl_safe(msr, &value); | |
215 | smsr->values[slot].host = value; | |
216 | smsr->values[slot].curr = value; | |
217 | } | |
218 | ||
219 | void kvm_define_shared_msr(unsigned slot, u32 msr) | |
220 | { | |
0123be42 | 221 | BUG_ON(slot >= KVM_NR_SHARED_MSRS); |
18863bdd AK |
222 | if (slot >= shared_msrs_global.nr) |
223 | shared_msrs_global.nr = slot + 1; | |
2bf78fa7 SY |
224 | shared_msrs_global.msrs[slot] = msr; |
225 | /* we need ensured the shared_msr_global have been updated */ | |
226 | smp_wmb(); | |
18863bdd AK |
227 | } |
228 | EXPORT_SYMBOL_GPL(kvm_define_shared_msr); | |
229 | ||
230 | static void kvm_shared_msr_cpu_online(void) | |
231 | { | |
232 | unsigned i; | |
18863bdd AK |
233 | |
234 | for (i = 0; i < shared_msrs_global.nr; ++i) | |
2bf78fa7 | 235 | shared_msr_update(i, shared_msrs_global.msrs[i]); |
18863bdd AK |
236 | } |
237 | ||
8b3c3104 | 238 | int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) |
18863bdd | 239 | { |
013f6a5d MT |
240 | unsigned int cpu = smp_processor_id(); |
241 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
8b3c3104 | 242 | int err; |
18863bdd | 243 | |
2bf78fa7 | 244 | if (((value ^ smsr->values[slot].curr) & mask) == 0) |
8b3c3104 | 245 | return 0; |
2bf78fa7 | 246 | smsr->values[slot].curr = value; |
8b3c3104 AH |
247 | err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); |
248 | if (err) | |
249 | return 1; | |
250 | ||
18863bdd AK |
251 | if (!smsr->registered) { |
252 | smsr->urn.on_user_return = kvm_on_user_return; | |
253 | user_return_notifier_register(&smsr->urn); | |
254 | smsr->registered = true; | |
255 | } | |
8b3c3104 | 256 | return 0; |
18863bdd AK |
257 | } |
258 | EXPORT_SYMBOL_GPL(kvm_set_shared_msr); | |
259 | ||
13a34e06 | 260 | static void drop_user_return_notifiers(void) |
3548bab5 | 261 | { |
013f6a5d MT |
262 | unsigned int cpu = smp_processor_id(); |
263 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
3548bab5 AK |
264 | |
265 | if (smsr->registered) | |
266 | kvm_on_user_return(&smsr->urn); | |
267 | } | |
268 | ||
6866b83e CO |
269 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
270 | { | |
8a5a87d9 | 271 | return vcpu->arch.apic_base; |
6866b83e CO |
272 | } |
273 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
274 | ||
58cb628d JK |
275 | int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
276 | { | |
277 | u64 old_state = vcpu->arch.apic_base & | |
278 | (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); | |
279 | u64 new_state = msr_info->data & | |
280 | (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); | |
281 | u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | | |
282 | 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE); | |
283 | ||
284 | if (!msr_info->host_initiated && | |
285 | ((msr_info->data & reserved_bits) != 0 || | |
286 | new_state == X2APIC_ENABLE || | |
287 | (new_state == MSR_IA32_APICBASE_ENABLE && | |
288 | old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) || | |
289 | (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) && | |
290 | old_state == 0))) | |
291 | return 1; | |
292 | ||
293 | kvm_lapic_set_base(vcpu, msr_info->data); | |
294 | return 0; | |
6866b83e CO |
295 | } |
296 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
297 | ||
2605fc21 | 298 | asmlinkage __visible void kvm_spurious_fault(void) |
e3ba45b8 GL |
299 | { |
300 | /* Fault while not rebooting. We want the trace. */ | |
301 | BUG(); | |
302 | } | |
303 | EXPORT_SYMBOL_GPL(kvm_spurious_fault); | |
304 | ||
3fd28fce ED |
305 | #define EXCPT_BENIGN 0 |
306 | #define EXCPT_CONTRIBUTORY 1 | |
307 | #define EXCPT_PF 2 | |
308 | ||
309 | static int exception_class(int vector) | |
310 | { | |
311 | switch (vector) { | |
312 | case PF_VECTOR: | |
313 | return EXCPT_PF; | |
314 | case DE_VECTOR: | |
315 | case TS_VECTOR: | |
316 | case NP_VECTOR: | |
317 | case SS_VECTOR: | |
318 | case GP_VECTOR: | |
319 | return EXCPT_CONTRIBUTORY; | |
320 | default: | |
321 | break; | |
322 | } | |
323 | return EXCPT_BENIGN; | |
324 | } | |
325 | ||
d6e8c854 NA |
326 | #define EXCPT_FAULT 0 |
327 | #define EXCPT_TRAP 1 | |
328 | #define EXCPT_ABORT 2 | |
329 | #define EXCPT_INTERRUPT 3 | |
330 | ||
331 | static int exception_type(int vector) | |
332 | { | |
333 | unsigned int mask; | |
334 | ||
335 | if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) | |
336 | return EXCPT_INTERRUPT; | |
337 | ||
338 | mask = 1 << vector; | |
339 | ||
340 | /* #DB is trap, as instruction watchpoints are handled elsewhere */ | |
341 | if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) | |
342 | return EXCPT_TRAP; | |
343 | ||
344 | if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) | |
345 | return EXCPT_ABORT; | |
346 | ||
347 | /* Reserved exceptions will result in fault */ | |
348 | return EXCPT_FAULT; | |
349 | } | |
350 | ||
3fd28fce | 351 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, |
ce7ddec4 JR |
352 | unsigned nr, bool has_error, u32 error_code, |
353 | bool reinject) | |
3fd28fce ED |
354 | { |
355 | u32 prev_nr; | |
356 | int class1, class2; | |
357 | ||
3842d135 AK |
358 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
359 | ||
3fd28fce ED |
360 | if (!vcpu->arch.exception.pending) { |
361 | queue: | |
3ffb2468 NA |
362 | if (has_error && !is_protmode(vcpu)) |
363 | has_error = false; | |
3fd28fce ED |
364 | vcpu->arch.exception.pending = true; |
365 | vcpu->arch.exception.has_error_code = has_error; | |
366 | vcpu->arch.exception.nr = nr; | |
367 | vcpu->arch.exception.error_code = error_code; | |
3f0fd292 | 368 | vcpu->arch.exception.reinject = reinject; |
3fd28fce ED |
369 | return; |
370 | } | |
371 | ||
372 | /* to check exception */ | |
373 | prev_nr = vcpu->arch.exception.nr; | |
374 | if (prev_nr == DF_VECTOR) { | |
375 | /* triple fault -> shutdown */ | |
a8eeb04a | 376 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
3fd28fce ED |
377 | return; |
378 | } | |
379 | class1 = exception_class(prev_nr); | |
380 | class2 = exception_class(nr); | |
381 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) | |
382 | || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
383 | /* generate double fault per SDM Table 5-5 */ | |
384 | vcpu->arch.exception.pending = true; | |
385 | vcpu->arch.exception.has_error_code = true; | |
386 | vcpu->arch.exception.nr = DF_VECTOR; | |
387 | vcpu->arch.exception.error_code = 0; | |
388 | } else | |
389 | /* replace previous exception with a new one in a hope | |
390 | that instruction re-execution will regenerate lost | |
391 | exception */ | |
392 | goto queue; | |
393 | } | |
394 | ||
298101da AK |
395 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
396 | { | |
ce7ddec4 | 397 | kvm_multiple_exception(vcpu, nr, false, 0, false); |
298101da AK |
398 | } |
399 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
400 | ||
ce7ddec4 JR |
401 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
402 | { | |
403 | kvm_multiple_exception(vcpu, nr, false, 0, true); | |
404 | } | |
405 | EXPORT_SYMBOL_GPL(kvm_requeue_exception); | |
406 | ||
db8fcefa | 407 | void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) |
c3c91fee | 408 | { |
db8fcefa AP |
409 | if (err) |
410 | kvm_inject_gp(vcpu, 0); | |
411 | else | |
412 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
413 | } | |
414 | EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); | |
8df25a32 | 415 | |
6389ee94 | 416 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
c3c91fee AK |
417 | { |
418 | ++vcpu->stat.pf_guest; | |
6389ee94 AK |
419 | vcpu->arch.cr2 = fault->address; |
420 | kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); | |
c3c91fee | 421 | } |
27d6c865 | 422 | EXPORT_SYMBOL_GPL(kvm_inject_page_fault); |
c3c91fee | 423 | |
ef54bcfe | 424 | static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
d4f8cf66 | 425 | { |
6389ee94 AK |
426 | if (mmu_is_nested(vcpu) && !fault->nested_page_fault) |
427 | vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); | |
d4f8cf66 | 428 | else |
6389ee94 | 429 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
ef54bcfe PB |
430 | |
431 | return fault->nested_page_fault; | |
d4f8cf66 JR |
432 | } |
433 | ||
3419ffc8 SY |
434 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
435 | { | |
7460fb4a AK |
436 | atomic_inc(&vcpu->arch.nmi_queued); |
437 | kvm_make_request(KVM_REQ_NMI, vcpu); | |
3419ffc8 SY |
438 | } |
439 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
440 | ||
298101da AK |
441 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
442 | { | |
ce7ddec4 | 443 | kvm_multiple_exception(vcpu, nr, true, error_code, false); |
298101da AK |
444 | } |
445 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
446 | ||
ce7ddec4 JR |
447 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
448 | { | |
449 | kvm_multiple_exception(vcpu, nr, true, error_code, true); | |
450 | } | |
451 | EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); | |
452 | ||
0a79b009 AK |
453 | /* |
454 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
455 | * a #GP and return false. | |
456 | */ | |
457 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 458 | { |
0a79b009 AK |
459 | if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) |
460 | return true; | |
461 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
462 | return false; | |
298101da | 463 | } |
0a79b009 | 464 | EXPORT_SYMBOL_GPL(kvm_require_cpl); |
298101da | 465 | |
16f8a6f9 NA |
466 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) |
467 | { | |
468 | if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
469 | return true; | |
470 | ||
471 | kvm_queue_exception(vcpu, UD_VECTOR); | |
472 | return false; | |
473 | } | |
474 | EXPORT_SYMBOL_GPL(kvm_require_dr); | |
475 | ||
ec92fe44 JR |
476 | /* |
477 | * This function will be used to read from the physical memory of the currently | |
478 | * running guest. The difference to kvm_read_guest_page is that this function | |
479 | * can read from guest physical or from the guest's guest physical memory. | |
480 | */ | |
481 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
482 | gfn_t ngfn, void *data, int offset, int len, | |
483 | u32 access) | |
484 | { | |
54987b7a | 485 | struct x86_exception exception; |
ec92fe44 JR |
486 | gfn_t real_gfn; |
487 | gpa_t ngpa; | |
488 | ||
489 | ngpa = gfn_to_gpa(ngfn); | |
54987b7a | 490 | real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); |
ec92fe44 JR |
491 | if (real_gfn == UNMAPPED_GVA) |
492 | return -EFAULT; | |
493 | ||
494 | real_gfn = gpa_to_gfn(real_gfn); | |
495 | ||
496 | return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len); | |
497 | } | |
498 | EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); | |
499 | ||
69b0049a | 500 | static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, |
3d06b8bf JR |
501 | void *data, int offset, int len, u32 access) |
502 | { | |
503 | return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, | |
504 | data, offset, len, access); | |
505 | } | |
506 | ||
a03490ed CO |
507 | /* |
508 | * Load the pae pdptrs. Return true is they are all valid. | |
509 | */ | |
ff03a073 | 510 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) |
a03490ed CO |
511 | { |
512 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
513 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
514 | int i; | |
515 | int ret; | |
ff03a073 | 516 | u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; |
a03490ed | 517 | |
ff03a073 JR |
518 | ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, |
519 | offset * sizeof(u64), sizeof(pdpte), | |
520 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
a03490ed CO |
521 | if (ret < 0) { |
522 | ret = 0; | |
523 | goto out; | |
524 | } | |
525 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
43a3795a | 526 | if (is_present_gpte(pdpte[i]) && |
20c466b5 | 527 | (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) { |
a03490ed CO |
528 | ret = 0; |
529 | goto out; | |
530 | } | |
531 | } | |
532 | ret = 1; | |
533 | ||
ff03a073 | 534 | memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); |
6de4f3ad AK |
535 | __set_bit(VCPU_EXREG_PDPTR, |
536 | (unsigned long *)&vcpu->arch.regs_avail); | |
537 | __set_bit(VCPU_EXREG_PDPTR, | |
538 | (unsigned long *)&vcpu->arch.regs_dirty); | |
a03490ed | 539 | out: |
a03490ed CO |
540 | |
541 | return ret; | |
542 | } | |
cc4b6871 | 543 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 544 | |
d835dfec AK |
545 | static bool pdptrs_changed(struct kvm_vcpu *vcpu) |
546 | { | |
ff03a073 | 547 | u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; |
d835dfec | 548 | bool changed = true; |
3d06b8bf JR |
549 | int offset; |
550 | gfn_t gfn; | |
d835dfec AK |
551 | int r; |
552 | ||
553 | if (is_long_mode(vcpu) || !is_pae(vcpu)) | |
554 | return false; | |
555 | ||
6de4f3ad AK |
556 | if (!test_bit(VCPU_EXREG_PDPTR, |
557 | (unsigned long *)&vcpu->arch.regs_avail)) | |
558 | return true; | |
559 | ||
9f8fe504 AK |
560 | gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT; |
561 | offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1); | |
3d06b8bf JR |
562 | r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), |
563 | PFERR_USER_MASK | PFERR_WRITE_MASK); | |
d835dfec AK |
564 | if (r < 0) |
565 | goto out; | |
ff03a073 | 566 | changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; |
d835dfec | 567 | out: |
d835dfec AK |
568 | |
569 | return changed; | |
570 | } | |
571 | ||
49a9b07e | 572 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 573 | { |
aad82703 SY |
574 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
575 | unsigned long update_bits = X86_CR0_PG | X86_CR0_WP | | |
576 | X86_CR0_CD | X86_CR0_NW; | |
577 | ||
f9a48e6a AK |
578 | cr0 |= X86_CR0_ET; |
579 | ||
ab344828 | 580 | #ifdef CONFIG_X86_64 |
0f12244f GN |
581 | if (cr0 & 0xffffffff00000000UL) |
582 | return 1; | |
ab344828 GN |
583 | #endif |
584 | ||
585 | cr0 &= ~CR0_RESERVED_BITS; | |
a03490ed | 586 | |
0f12244f GN |
587 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) |
588 | return 1; | |
a03490ed | 589 | |
0f12244f GN |
590 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) |
591 | return 1; | |
a03490ed CO |
592 | |
593 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { | |
594 | #ifdef CONFIG_X86_64 | |
f6801dff | 595 | if ((vcpu->arch.efer & EFER_LME)) { |
a03490ed CO |
596 | int cs_db, cs_l; |
597 | ||
0f12244f GN |
598 | if (!is_pae(vcpu)) |
599 | return 1; | |
a03490ed | 600 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
0f12244f GN |
601 | if (cs_l) |
602 | return 1; | |
a03490ed CO |
603 | } else |
604 | #endif | |
ff03a073 | 605 | if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
9f8fe504 | 606 | kvm_read_cr3(vcpu))) |
0f12244f | 607 | return 1; |
a03490ed CO |
608 | } |
609 | ||
ad756a16 MJ |
610 | if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) |
611 | return 1; | |
612 | ||
a03490ed | 613 | kvm_x86_ops->set_cr0(vcpu, cr0); |
a03490ed | 614 | |
d170c419 | 615 | if ((cr0 ^ old_cr0) & X86_CR0_PG) { |
e5f3f027 | 616 | kvm_clear_async_pf_completion_queue(vcpu); |
d170c419 LJ |
617 | kvm_async_pf_hash_reset(vcpu); |
618 | } | |
e5f3f027 | 619 | |
aad82703 SY |
620 | if ((cr0 ^ old_cr0) & update_bits) |
621 | kvm_mmu_reset_context(vcpu); | |
0f12244f GN |
622 | return 0; |
623 | } | |
2d3ad1f4 | 624 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 625 | |
2d3ad1f4 | 626 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 627 | { |
49a9b07e | 628 | (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); |
a03490ed | 629 | } |
2d3ad1f4 | 630 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 631 | |
42bdf991 MT |
632 | static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) |
633 | { | |
634 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && | |
635 | !vcpu->guest_xcr0_loaded) { | |
636 | /* kvm_set_xcr() also depends on this */ | |
637 | xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); | |
638 | vcpu->guest_xcr0_loaded = 1; | |
639 | } | |
640 | } | |
641 | ||
642 | static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) | |
643 | { | |
644 | if (vcpu->guest_xcr0_loaded) { | |
645 | if (vcpu->arch.xcr0 != host_xcr0) | |
646 | xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); | |
647 | vcpu->guest_xcr0_loaded = 0; | |
648 | } | |
649 | } | |
650 | ||
69b0049a | 651 | static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) |
2acf923e | 652 | { |
56c103ec LJ |
653 | u64 xcr0 = xcr; |
654 | u64 old_xcr0 = vcpu->arch.xcr0; | |
46c34cb0 | 655 | u64 valid_bits; |
2acf923e DC |
656 | |
657 | /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ | |
658 | if (index != XCR_XFEATURE_ENABLED_MASK) | |
659 | return 1; | |
2acf923e DC |
660 | if (!(xcr0 & XSTATE_FP)) |
661 | return 1; | |
662 | if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE)) | |
663 | return 1; | |
46c34cb0 PB |
664 | |
665 | /* | |
666 | * Do not allow the guest to set bits that we do not support | |
667 | * saving. However, xcr0 bit 0 is always set, even if the | |
668 | * emulated CPU does not support XSAVE (see fx_init). | |
669 | */ | |
670 | valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP; | |
671 | if (xcr0 & ~valid_bits) | |
2acf923e | 672 | return 1; |
46c34cb0 | 673 | |
390bd528 LJ |
674 | if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR))) |
675 | return 1; | |
676 | ||
612263b3 CP |
677 | if (xcr0 & XSTATE_AVX512) { |
678 | if (!(xcr0 & XSTATE_YMM)) | |
679 | return 1; | |
680 | if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512) | |
681 | return 1; | |
682 | } | |
42bdf991 | 683 | kvm_put_guest_xcr0(vcpu); |
2acf923e | 684 | vcpu->arch.xcr0 = xcr0; |
56c103ec LJ |
685 | |
686 | if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK) | |
687 | kvm_update_cpuid(vcpu); | |
2acf923e DC |
688 | return 0; |
689 | } | |
690 | ||
691 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) | |
692 | { | |
764bcbc5 Z |
693 | if (kvm_x86_ops->get_cpl(vcpu) != 0 || |
694 | __kvm_set_xcr(vcpu, index, xcr)) { | |
2acf923e DC |
695 | kvm_inject_gp(vcpu, 0); |
696 | return 1; | |
697 | } | |
698 | return 0; | |
699 | } | |
700 | EXPORT_SYMBOL_GPL(kvm_set_xcr); | |
701 | ||
a83b29c6 | 702 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 703 | { |
fc78f519 | 704 | unsigned long old_cr4 = kvm_read_cr4(vcpu); |
c68b734f YW |
705 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | |
706 | X86_CR4_PAE | X86_CR4_SMEP; | |
0f12244f GN |
707 | if (cr4 & CR4_RESERVED_BITS) |
708 | return 1; | |
a03490ed | 709 | |
2acf923e DC |
710 | if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE)) |
711 | return 1; | |
712 | ||
c68b734f YW |
713 | if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP)) |
714 | return 1; | |
715 | ||
97ec8c06 FW |
716 | if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP)) |
717 | return 1; | |
718 | ||
afcbf13f | 719 | if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE)) |
74dc2b4f YW |
720 | return 1; |
721 | ||
a03490ed | 722 | if (is_long_mode(vcpu)) { |
0f12244f GN |
723 | if (!(cr4 & X86_CR4_PAE)) |
724 | return 1; | |
a2edf57f AK |
725 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
726 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
9f8fe504 AK |
727 | && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
728 | kvm_read_cr3(vcpu))) | |
0f12244f GN |
729 | return 1; |
730 | ||
ad756a16 MJ |
731 | if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { |
732 | if (!guest_cpuid_has_pcid(vcpu)) | |
733 | return 1; | |
734 | ||
735 | /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ | |
736 | if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) | |
737 | return 1; | |
738 | } | |
739 | ||
5e1746d6 | 740 | if (kvm_x86_ops->set_cr4(vcpu, cr4)) |
0f12244f | 741 | return 1; |
a03490ed | 742 | |
ad756a16 MJ |
743 | if (((cr4 ^ old_cr4) & pdptr_bits) || |
744 | (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) | |
aad82703 | 745 | kvm_mmu_reset_context(vcpu); |
0f12244f | 746 | |
97ec8c06 FW |
747 | if ((cr4 ^ old_cr4) & X86_CR4_SMAP) |
748 | update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false); | |
749 | ||
2acf923e | 750 | if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE) |
00b27a3e | 751 | kvm_update_cpuid(vcpu); |
2acf923e | 752 | |
0f12244f GN |
753 | return 0; |
754 | } | |
2d3ad1f4 | 755 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 756 | |
2390218b | 757 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 758 | { |
ac146235 | 759 | #ifdef CONFIG_X86_64 |
9d88fca7 | 760 | cr3 &= ~CR3_PCID_INVD; |
ac146235 | 761 | #endif |
9d88fca7 | 762 | |
9f8fe504 | 763 | if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { |
0ba73cda | 764 | kvm_mmu_sync_roots(vcpu); |
77c3913b | 765 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
0f12244f | 766 | return 0; |
d835dfec AK |
767 | } |
768 | ||
a03490ed | 769 | if (is_long_mode(vcpu)) { |
d9f89b88 JK |
770 | if (cr3 & CR3_L_MODE_RESERVED_BITS) |
771 | return 1; | |
772 | } else if (is_pae(vcpu) && is_paging(vcpu) && | |
773 | !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) | |
346874c9 | 774 | return 1; |
a03490ed | 775 | |
0f12244f | 776 | vcpu->arch.cr3 = cr3; |
aff48baa | 777 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); |
d8d173da | 778 | kvm_mmu_new_cr3(vcpu); |
0f12244f GN |
779 | return 0; |
780 | } | |
2d3ad1f4 | 781 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 782 | |
eea1cff9 | 783 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed | 784 | { |
0f12244f GN |
785 | if (cr8 & CR8_RESERVED_BITS) |
786 | return 1; | |
a03490ed CO |
787 | if (irqchip_in_kernel(vcpu->kvm)) |
788 | kvm_lapic_set_tpr(vcpu, cr8); | |
789 | else | |
ad312c7c | 790 | vcpu->arch.cr8 = cr8; |
0f12244f GN |
791 | return 0; |
792 | } | |
2d3ad1f4 | 793 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 794 | |
2d3ad1f4 | 795 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed CO |
796 | { |
797 | if (irqchip_in_kernel(vcpu->kvm)) | |
798 | return kvm_lapic_get_cr8(vcpu); | |
799 | else | |
ad312c7c | 800 | return vcpu->arch.cr8; |
a03490ed | 801 | } |
2d3ad1f4 | 802 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 803 | |
ae561ede NA |
804 | static void kvm_update_dr0123(struct kvm_vcpu *vcpu) |
805 | { | |
806 | int i; | |
807 | ||
808 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
809 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
810 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
811 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; | |
812 | } | |
813 | } | |
814 | ||
73aaf249 JK |
815 | static void kvm_update_dr6(struct kvm_vcpu *vcpu) |
816 | { | |
817 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
818 | kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); | |
819 | } | |
820 | ||
c8639010 JK |
821 | static void kvm_update_dr7(struct kvm_vcpu *vcpu) |
822 | { | |
823 | unsigned long dr7; | |
824 | ||
825 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
826 | dr7 = vcpu->arch.guest_debug_dr7; | |
827 | else | |
828 | dr7 = vcpu->arch.dr7; | |
829 | kvm_x86_ops->set_dr7(vcpu, dr7); | |
360b948d PB |
830 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; |
831 | if (dr7 & DR7_BP_EN_MASK) | |
832 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; | |
c8639010 JK |
833 | } |
834 | ||
6f43ed01 NA |
835 | static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) |
836 | { | |
837 | u64 fixed = DR6_FIXED_1; | |
838 | ||
839 | if (!guest_cpuid_has_rtm(vcpu)) | |
840 | fixed |= DR6_RTM; | |
841 | return fixed; | |
842 | } | |
843 | ||
338dbc97 | 844 | static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) |
020df079 GN |
845 | { |
846 | switch (dr) { | |
847 | case 0 ... 3: | |
848 | vcpu->arch.db[dr] = val; | |
849 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
850 | vcpu->arch.eff_db[dr] = val; | |
851 | break; | |
852 | case 4: | |
020df079 GN |
853 | /* fall through */ |
854 | case 6: | |
338dbc97 GN |
855 | if (val & 0xffffffff00000000ULL) |
856 | return -1; /* #GP */ | |
6f43ed01 | 857 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); |
73aaf249 | 858 | kvm_update_dr6(vcpu); |
020df079 GN |
859 | break; |
860 | case 5: | |
020df079 GN |
861 | /* fall through */ |
862 | default: /* 7 */ | |
338dbc97 GN |
863 | if (val & 0xffffffff00000000ULL) |
864 | return -1; /* #GP */ | |
020df079 | 865 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; |
c8639010 | 866 | kvm_update_dr7(vcpu); |
020df079 GN |
867 | break; |
868 | } | |
869 | ||
870 | return 0; | |
871 | } | |
338dbc97 GN |
872 | |
873 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) | |
874 | { | |
16f8a6f9 | 875 | if (__kvm_set_dr(vcpu, dr, val)) { |
338dbc97 | 876 | kvm_inject_gp(vcpu, 0); |
16f8a6f9 NA |
877 | return 1; |
878 | } | |
879 | return 0; | |
338dbc97 | 880 | } |
020df079 GN |
881 | EXPORT_SYMBOL_GPL(kvm_set_dr); |
882 | ||
16f8a6f9 | 883 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) |
020df079 GN |
884 | { |
885 | switch (dr) { | |
886 | case 0 ... 3: | |
887 | *val = vcpu->arch.db[dr]; | |
888 | break; | |
889 | case 4: | |
020df079 GN |
890 | /* fall through */ |
891 | case 6: | |
73aaf249 JK |
892 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) |
893 | *val = vcpu->arch.dr6; | |
894 | else | |
895 | *val = kvm_x86_ops->get_dr6(vcpu); | |
020df079 GN |
896 | break; |
897 | case 5: | |
020df079 GN |
898 | /* fall through */ |
899 | default: /* 7 */ | |
900 | *val = vcpu->arch.dr7; | |
901 | break; | |
902 | } | |
338dbc97 GN |
903 | return 0; |
904 | } | |
020df079 GN |
905 | EXPORT_SYMBOL_GPL(kvm_get_dr); |
906 | ||
022cd0e8 AK |
907 | bool kvm_rdpmc(struct kvm_vcpu *vcpu) |
908 | { | |
909 | u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
910 | u64 data; | |
911 | int err; | |
912 | ||
913 | err = kvm_pmu_read_pmc(vcpu, ecx, &data); | |
914 | if (err) | |
915 | return err; | |
916 | kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data); | |
917 | kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32); | |
918 | return err; | |
919 | } | |
920 | EXPORT_SYMBOL_GPL(kvm_rdpmc); | |
921 | ||
043405e1 CO |
922 | /* |
923 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
924 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
925 | * | |
926 | * This list is modified at module load time to reflect the | |
e3267cbb GC |
927 | * capabilities of the host cpu. This capabilities test skips MSRs that are |
928 | * kvm-specific. Those are put in the beginning of the list. | |
043405e1 | 929 | */ |
e3267cbb | 930 | |
e984097b | 931 | #define KVM_SAVE_MSRS_BEGIN 12 |
043405e1 | 932 | static u32 msrs_to_save[] = { |
e3267cbb | 933 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, |
11c6bffa | 934 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, |
55cd8e5a | 935 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, |
e984097b | 936 | HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, |
c9aaa895 | 937 | HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, |
ae7a2a3f | 938 | MSR_KVM_PV_EOI_EN, |
043405e1 | 939 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, |
8c06585d | 940 | MSR_STAR, |
043405e1 CO |
941 | #ifdef CONFIG_X86_64 |
942 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
943 | #endif | |
b3897a49 | 944 | MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, |
0dd376e7 | 945 | MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS |
043405e1 CO |
946 | }; |
947 | ||
948 | static unsigned num_msrs_to_save; | |
949 | ||
f1d24831 | 950 | static const u32 emulated_msrs[] = { |
ba904635 | 951 | MSR_IA32_TSC_ADJUST, |
a3e06bbe | 952 | MSR_IA32_TSCDEADLINE, |
043405e1 | 953 | MSR_IA32_MISC_ENABLE, |
908e75f3 AK |
954 | MSR_IA32_MCG_STATUS, |
955 | MSR_IA32_MCG_CTL, | |
043405e1 CO |
956 | }; |
957 | ||
384bb783 | 958 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) |
15c4a640 | 959 | { |
b69e8cae | 960 | if (efer & efer_reserved_bits) |
384bb783 | 961 | return false; |
15c4a640 | 962 | |
1b2fd70c AG |
963 | if (efer & EFER_FFXSR) { |
964 | struct kvm_cpuid_entry2 *feat; | |
965 | ||
966 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
b69e8cae | 967 | if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) |
384bb783 | 968 | return false; |
1b2fd70c AG |
969 | } |
970 | ||
d8017474 AG |
971 | if (efer & EFER_SVME) { |
972 | struct kvm_cpuid_entry2 *feat; | |
973 | ||
974 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
b69e8cae | 975 | if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) |
384bb783 | 976 | return false; |
d8017474 AG |
977 | } |
978 | ||
384bb783 JK |
979 | return true; |
980 | } | |
981 | EXPORT_SYMBOL_GPL(kvm_valid_efer); | |
982 | ||
983 | static int set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
984 | { | |
985 | u64 old_efer = vcpu->arch.efer; | |
986 | ||
987 | if (!kvm_valid_efer(vcpu, efer)) | |
988 | return 1; | |
989 | ||
990 | if (is_paging(vcpu) | |
991 | && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) | |
992 | return 1; | |
993 | ||
15c4a640 | 994 | efer &= ~EFER_LMA; |
f6801dff | 995 | efer |= vcpu->arch.efer & EFER_LMA; |
15c4a640 | 996 | |
a3d204e2 SY |
997 | kvm_x86_ops->set_efer(vcpu, efer); |
998 | ||
aad82703 SY |
999 | /* Update reserved bits */ |
1000 | if ((efer ^ old_efer) & EFER_NX) | |
1001 | kvm_mmu_reset_context(vcpu); | |
1002 | ||
b69e8cae | 1003 | return 0; |
15c4a640 CO |
1004 | } |
1005 | ||
f2b4b7dd JR |
1006 | void kvm_enable_efer_bits(u64 mask) |
1007 | { | |
1008 | efer_reserved_bits &= ~mask; | |
1009 | } | |
1010 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
1011 | ||
15c4a640 CO |
1012 | /* |
1013 | * Writes msr value into into the appropriate "register". | |
1014 | * Returns 0 on success, non-0 otherwise. | |
1015 | * Assumes vcpu_load() was already called. | |
1016 | */ | |
8fe8ab46 | 1017 | int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) |
15c4a640 | 1018 | { |
854e8bb1 NA |
1019 | switch (msr->index) { |
1020 | case MSR_FS_BASE: | |
1021 | case MSR_GS_BASE: | |
1022 | case MSR_KERNEL_GS_BASE: | |
1023 | case MSR_CSTAR: | |
1024 | case MSR_LSTAR: | |
1025 | if (is_noncanonical_address(msr->data)) | |
1026 | return 1; | |
1027 | break; | |
1028 | case MSR_IA32_SYSENTER_EIP: | |
1029 | case MSR_IA32_SYSENTER_ESP: | |
1030 | /* | |
1031 | * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if | |
1032 | * non-canonical address is written on Intel but not on | |
1033 | * AMD (which ignores the top 32-bits, because it does | |
1034 | * not implement 64-bit SYSENTER). | |
1035 | * | |
1036 | * 64-bit code should hence be able to write a non-canonical | |
1037 | * value on AMD. Making the address canonical ensures that | |
1038 | * vmentry does not fail on Intel after writing a non-canonical | |
1039 | * value, and that something deterministic happens if the guest | |
1040 | * invokes 64-bit SYSENTER. | |
1041 | */ | |
1042 | msr->data = get_canonical(msr->data); | |
1043 | } | |
8fe8ab46 | 1044 | return kvm_x86_ops->set_msr(vcpu, msr); |
15c4a640 | 1045 | } |
854e8bb1 | 1046 | EXPORT_SYMBOL_GPL(kvm_set_msr); |
15c4a640 | 1047 | |
313a3dc7 CO |
1048 | /* |
1049 | * Adapt set_msr() to msr_io()'s calling convention | |
1050 | */ | |
1051 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
1052 | { | |
8fe8ab46 WA |
1053 | struct msr_data msr; |
1054 | ||
1055 | msr.data = *data; | |
1056 | msr.index = index; | |
1057 | msr.host_initiated = true; | |
1058 | return kvm_set_msr(vcpu, &msr); | |
313a3dc7 CO |
1059 | } |
1060 | ||
16e8d74d MT |
1061 | #ifdef CONFIG_X86_64 |
1062 | struct pvclock_gtod_data { | |
1063 | seqcount_t seq; | |
1064 | ||
1065 | struct { /* extract of a clocksource struct */ | |
1066 | int vclock_mode; | |
1067 | cycle_t cycle_last; | |
1068 | cycle_t mask; | |
1069 | u32 mult; | |
1070 | u32 shift; | |
1071 | } clock; | |
1072 | ||
cbcf2dd3 TG |
1073 | u64 boot_ns; |
1074 | u64 nsec_base; | |
16e8d74d MT |
1075 | }; |
1076 | ||
1077 | static struct pvclock_gtod_data pvclock_gtod_data; | |
1078 | ||
1079 | static void update_pvclock_gtod(struct timekeeper *tk) | |
1080 | { | |
1081 | struct pvclock_gtod_data *vdata = &pvclock_gtod_data; | |
cbcf2dd3 TG |
1082 | u64 boot_ns; |
1083 | ||
876e7881 | 1084 | boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot)); |
16e8d74d MT |
1085 | |
1086 | write_seqcount_begin(&vdata->seq); | |
1087 | ||
1088 | /* copy pvclock gtod data */ | |
876e7881 PZ |
1089 | vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode; |
1090 | vdata->clock.cycle_last = tk->tkr_mono.cycle_last; | |
1091 | vdata->clock.mask = tk->tkr_mono.mask; | |
1092 | vdata->clock.mult = tk->tkr_mono.mult; | |
1093 | vdata->clock.shift = tk->tkr_mono.shift; | |
16e8d74d | 1094 | |
cbcf2dd3 | 1095 | vdata->boot_ns = boot_ns; |
876e7881 | 1096 | vdata->nsec_base = tk->tkr_mono.xtime_nsec; |
16e8d74d MT |
1097 | |
1098 | write_seqcount_end(&vdata->seq); | |
1099 | } | |
1100 | #endif | |
1101 | ||
bab5bb39 NK |
1102 | void kvm_set_pending_timer(struct kvm_vcpu *vcpu) |
1103 | { | |
1104 | /* | |
1105 | * Note: KVM_REQ_PENDING_TIMER is implicitly checked in | |
1106 | * vcpu_enter_guest. This function is only called from | |
1107 | * the physical CPU that is running vcpu. | |
1108 | */ | |
1109 | kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); | |
1110 | } | |
16e8d74d | 1111 | |
18068523 GOC |
1112 | static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) |
1113 | { | |
9ed3c444 AK |
1114 | int version; |
1115 | int r; | |
50d0a0f9 | 1116 | struct pvclock_wall_clock wc; |
923de3cf | 1117 | struct timespec boot; |
18068523 GOC |
1118 | |
1119 | if (!wall_clock) | |
1120 | return; | |
1121 | ||
9ed3c444 AK |
1122 | r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); |
1123 | if (r) | |
1124 | return; | |
1125 | ||
1126 | if (version & 1) | |
1127 | ++version; /* first time write, random junk */ | |
1128 | ||
1129 | ++version; | |
18068523 | 1130 | |
18068523 GOC |
1131 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); |
1132 | ||
50d0a0f9 GH |
1133 | /* |
1134 | * The guest calculates current wall clock time by adding | |
34c238a1 | 1135 | * system time (updated by kvm_guest_time_update below) to the |
50d0a0f9 GH |
1136 | * wall clock specified here. guest system time equals host |
1137 | * system time for us, thus we must fill in host boot time here. | |
1138 | */ | |
923de3cf | 1139 | getboottime(&boot); |
50d0a0f9 | 1140 | |
4b648665 BR |
1141 | if (kvm->arch.kvmclock_offset) { |
1142 | struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset); | |
1143 | boot = timespec_sub(boot, ts); | |
1144 | } | |
50d0a0f9 GH |
1145 | wc.sec = boot.tv_sec; |
1146 | wc.nsec = boot.tv_nsec; | |
1147 | wc.version = version; | |
18068523 GOC |
1148 | |
1149 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
1150 | ||
1151 | version++; | |
1152 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
1153 | } |
1154 | ||
50d0a0f9 GH |
1155 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
1156 | { | |
1157 | uint32_t quotient, remainder; | |
1158 | ||
1159 | /* Don't try to replace with do_div(), this one calculates | |
1160 | * "(dividend << 32) / divisor" */ | |
1161 | __asm__ ( "divl %4" | |
1162 | : "=a" (quotient), "=d" (remainder) | |
1163 | : "0" (0), "1" (dividend), "r" (divisor) ); | |
1164 | return quotient; | |
1165 | } | |
1166 | ||
5f4e3f88 ZA |
1167 | static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz, |
1168 | s8 *pshift, u32 *pmultiplier) | |
50d0a0f9 | 1169 | { |
5f4e3f88 | 1170 | uint64_t scaled64; |
50d0a0f9 GH |
1171 | int32_t shift = 0; |
1172 | uint64_t tps64; | |
1173 | uint32_t tps32; | |
1174 | ||
5f4e3f88 ZA |
1175 | tps64 = base_khz * 1000LL; |
1176 | scaled64 = scaled_khz * 1000LL; | |
50933623 | 1177 | while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { |
50d0a0f9 GH |
1178 | tps64 >>= 1; |
1179 | shift--; | |
1180 | } | |
1181 | ||
1182 | tps32 = (uint32_t)tps64; | |
50933623 JK |
1183 | while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { |
1184 | if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) | |
5f4e3f88 ZA |
1185 | scaled64 >>= 1; |
1186 | else | |
1187 | tps32 <<= 1; | |
50d0a0f9 GH |
1188 | shift++; |
1189 | } | |
1190 | ||
5f4e3f88 ZA |
1191 | *pshift = shift; |
1192 | *pmultiplier = div_frac(scaled64, tps32); | |
50d0a0f9 | 1193 | |
5f4e3f88 ZA |
1194 | pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n", |
1195 | __func__, base_khz, scaled_khz, shift, *pmultiplier); | |
50d0a0f9 GH |
1196 | } |
1197 | ||
759379dd ZA |
1198 | static inline u64 get_kernel_ns(void) |
1199 | { | |
bb0b5812 | 1200 | return ktime_get_boot_ns(); |
50d0a0f9 GH |
1201 | } |
1202 | ||
d828199e | 1203 | #ifdef CONFIG_X86_64 |
16e8d74d | 1204 | static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); |
d828199e | 1205 | #endif |
16e8d74d | 1206 | |
c8076604 | 1207 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
69b0049a | 1208 | static unsigned long max_tsc_khz; |
c8076604 | 1209 | |
cc578287 | 1210 | static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec) |
8cfdc000 | 1211 | { |
cc578287 ZA |
1212 | return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult, |
1213 | vcpu->arch.virtual_tsc_shift); | |
8cfdc000 ZA |
1214 | } |
1215 | ||
cc578287 | 1216 | static u32 adjust_tsc_khz(u32 khz, s32 ppm) |
1e993611 | 1217 | { |
cc578287 ZA |
1218 | u64 v = (u64)khz * (1000000 + ppm); |
1219 | do_div(v, 1000000); | |
1220 | return v; | |
1e993611 JR |
1221 | } |
1222 | ||
cc578287 | 1223 | static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz) |
759379dd | 1224 | { |
cc578287 ZA |
1225 | u32 thresh_lo, thresh_hi; |
1226 | int use_scaling = 0; | |
217fc9cf | 1227 | |
03ba32ca MT |
1228 | /* tsc_khz can be zero if TSC calibration fails */ |
1229 | if (this_tsc_khz == 0) | |
1230 | return; | |
1231 | ||
c285545f ZA |
1232 | /* Compute a scale to convert nanoseconds in TSC cycles */ |
1233 | kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000, | |
cc578287 ZA |
1234 | &vcpu->arch.virtual_tsc_shift, |
1235 | &vcpu->arch.virtual_tsc_mult); | |
1236 | vcpu->arch.virtual_tsc_khz = this_tsc_khz; | |
1237 | ||
1238 | /* | |
1239 | * Compute the variation in TSC rate which is acceptable | |
1240 | * within the range of tolerance and decide if the | |
1241 | * rate being applied is within that bounds of the hardware | |
1242 | * rate. If so, no scaling or compensation need be done. | |
1243 | */ | |
1244 | thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); | |
1245 | thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); | |
1246 | if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) { | |
1247 | pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi); | |
1248 | use_scaling = 1; | |
1249 | } | |
1250 | kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling); | |
c285545f ZA |
1251 | } |
1252 | ||
1253 | static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) | |
1254 | { | |
e26101b1 | 1255 | u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, |
cc578287 ZA |
1256 | vcpu->arch.virtual_tsc_mult, |
1257 | vcpu->arch.virtual_tsc_shift); | |
e26101b1 | 1258 | tsc += vcpu->arch.this_tsc_write; |
c285545f ZA |
1259 | return tsc; |
1260 | } | |
1261 | ||
69b0049a | 1262 | static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) |
b48aa97e MT |
1263 | { |
1264 | #ifdef CONFIG_X86_64 | |
1265 | bool vcpus_matched; | |
b48aa97e MT |
1266 | struct kvm_arch *ka = &vcpu->kvm->arch; |
1267 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
1268 | ||
1269 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
1270 | atomic_read(&vcpu->kvm->online_vcpus)); | |
1271 | ||
7f187922 MT |
1272 | /* |
1273 | * Once the masterclock is enabled, always perform request in | |
1274 | * order to update it. | |
1275 | * | |
1276 | * In order to enable masterclock, the host clocksource must be TSC | |
1277 | * and the vcpus need to have matched TSCs. When that happens, | |
1278 | * perform request to enable masterclock. | |
1279 | */ | |
1280 | if (ka->use_master_clock || | |
1281 | (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched)) | |
b48aa97e MT |
1282 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
1283 | ||
1284 | trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, | |
1285 | atomic_read(&vcpu->kvm->online_vcpus), | |
1286 | ka->use_master_clock, gtod->clock.vclock_mode); | |
1287 | #endif | |
1288 | } | |
1289 | ||
ba904635 WA |
1290 | static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) |
1291 | { | |
1292 | u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu); | |
1293 | vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; | |
1294 | } | |
1295 | ||
8fe8ab46 | 1296 | void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) |
99e3e30a ZA |
1297 | { |
1298 | struct kvm *kvm = vcpu->kvm; | |
f38e098f | 1299 | u64 offset, ns, elapsed; |
99e3e30a | 1300 | unsigned long flags; |
02626b6a | 1301 | s64 usdiff; |
b48aa97e | 1302 | bool matched; |
0d3da0d2 | 1303 | bool already_matched; |
8fe8ab46 | 1304 | u64 data = msr->data; |
99e3e30a | 1305 | |
038f8c11 | 1306 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); |
857e4099 | 1307 | offset = kvm_x86_ops->compute_tsc_offset(vcpu, data); |
759379dd | 1308 | ns = get_kernel_ns(); |
f38e098f | 1309 | elapsed = ns - kvm->arch.last_tsc_nsec; |
5d3cb0f6 | 1310 | |
03ba32ca | 1311 | if (vcpu->arch.virtual_tsc_khz) { |
8915aa27 MT |
1312 | int faulted = 0; |
1313 | ||
03ba32ca MT |
1314 | /* n.b - signed multiplication and division required */ |
1315 | usdiff = data - kvm->arch.last_tsc_write; | |
5d3cb0f6 | 1316 | #ifdef CONFIG_X86_64 |
03ba32ca | 1317 | usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz; |
5d3cb0f6 | 1318 | #else |
03ba32ca | 1319 | /* do_div() only does unsigned */ |
8915aa27 MT |
1320 | asm("1: idivl %[divisor]\n" |
1321 | "2: xor %%edx, %%edx\n" | |
1322 | " movl $0, %[faulted]\n" | |
1323 | "3:\n" | |
1324 | ".section .fixup,\"ax\"\n" | |
1325 | "4: movl $1, %[faulted]\n" | |
1326 | " jmp 3b\n" | |
1327 | ".previous\n" | |
1328 | ||
1329 | _ASM_EXTABLE(1b, 4b) | |
1330 | ||
1331 | : "=A"(usdiff), [faulted] "=r" (faulted) | |
1332 | : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz)); | |
1333 | ||
5d3cb0f6 | 1334 | #endif |
03ba32ca MT |
1335 | do_div(elapsed, 1000); |
1336 | usdiff -= elapsed; | |
1337 | if (usdiff < 0) | |
1338 | usdiff = -usdiff; | |
8915aa27 MT |
1339 | |
1340 | /* idivl overflow => difference is larger than USEC_PER_SEC */ | |
1341 | if (faulted) | |
1342 | usdiff = USEC_PER_SEC; | |
03ba32ca MT |
1343 | } else |
1344 | usdiff = USEC_PER_SEC; /* disable TSC match window below */ | |
f38e098f ZA |
1345 | |
1346 | /* | |
5d3cb0f6 ZA |
1347 | * Special case: TSC write with a small delta (1 second) of virtual |
1348 | * cycle time against real time is interpreted as an attempt to | |
1349 | * synchronize the CPU. | |
1350 | * | |
1351 | * For a reliable TSC, we can match TSC offsets, and for an unstable | |
1352 | * TSC, we add elapsed time in this computation. We could let the | |
1353 | * compensation code attempt to catch up if we fall behind, but | |
1354 | * it's better to try to match offsets from the beginning. | |
1355 | */ | |
02626b6a | 1356 | if (usdiff < USEC_PER_SEC && |
5d3cb0f6 | 1357 | vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { |
f38e098f | 1358 | if (!check_tsc_unstable()) { |
e26101b1 | 1359 | offset = kvm->arch.cur_tsc_offset; |
f38e098f ZA |
1360 | pr_debug("kvm: matched tsc offset for %llu\n", data); |
1361 | } else { | |
857e4099 | 1362 | u64 delta = nsec_to_cycles(vcpu, elapsed); |
5d3cb0f6 ZA |
1363 | data += delta; |
1364 | offset = kvm_x86_ops->compute_tsc_offset(vcpu, data); | |
759379dd | 1365 | pr_debug("kvm: adjusted tsc offset by %llu\n", delta); |
f38e098f | 1366 | } |
b48aa97e | 1367 | matched = true; |
0d3da0d2 | 1368 | already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); |
e26101b1 ZA |
1369 | } else { |
1370 | /* | |
1371 | * We split periods of matched TSC writes into generations. | |
1372 | * For each generation, we track the original measured | |
1373 | * nanosecond time, offset, and write, so if TSCs are in | |
1374 | * sync, we can match exact offset, and if not, we can match | |
4a969980 | 1375 | * exact software computation in compute_guest_tsc() |
e26101b1 ZA |
1376 | * |
1377 | * These values are tracked in kvm->arch.cur_xxx variables. | |
1378 | */ | |
1379 | kvm->arch.cur_tsc_generation++; | |
1380 | kvm->arch.cur_tsc_nsec = ns; | |
1381 | kvm->arch.cur_tsc_write = data; | |
1382 | kvm->arch.cur_tsc_offset = offset; | |
b48aa97e | 1383 | matched = false; |
0d3da0d2 | 1384 | pr_debug("kvm: new tsc generation %llu, clock %llu\n", |
e26101b1 | 1385 | kvm->arch.cur_tsc_generation, data); |
f38e098f | 1386 | } |
e26101b1 ZA |
1387 | |
1388 | /* | |
1389 | * We also track th most recent recorded KHZ, write and time to | |
1390 | * allow the matching interval to be extended at each write. | |
1391 | */ | |
f38e098f ZA |
1392 | kvm->arch.last_tsc_nsec = ns; |
1393 | kvm->arch.last_tsc_write = data; | |
5d3cb0f6 | 1394 | kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; |
99e3e30a | 1395 | |
b183aa58 | 1396 | vcpu->arch.last_guest_tsc = data; |
e26101b1 ZA |
1397 | |
1398 | /* Keep track of which generation this VCPU has synchronized to */ | |
1399 | vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; | |
1400 | vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; | |
1401 | vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; | |
1402 | ||
ba904635 WA |
1403 | if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated) |
1404 | update_ia32_tsc_adjust_msr(vcpu, offset); | |
e26101b1 ZA |
1405 | kvm_x86_ops->write_tsc_offset(vcpu, offset); |
1406 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); | |
b48aa97e MT |
1407 | |
1408 | spin_lock(&kvm->arch.pvclock_gtod_sync_lock); | |
0d3da0d2 | 1409 | if (!matched) { |
b48aa97e | 1410 | kvm->arch.nr_vcpus_matched_tsc = 0; |
0d3da0d2 TG |
1411 | } else if (!already_matched) { |
1412 | kvm->arch.nr_vcpus_matched_tsc++; | |
1413 | } | |
b48aa97e MT |
1414 | |
1415 | kvm_track_tsc_matching(vcpu); | |
1416 | spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); | |
99e3e30a | 1417 | } |
e26101b1 | 1418 | |
99e3e30a ZA |
1419 | EXPORT_SYMBOL_GPL(kvm_write_tsc); |
1420 | ||
d828199e MT |
1421 | #ifdef CONFIG_X86_64 |
1422 | ||
1423 | static cycle_t read_tsc(void) | |
1424 | { | |
1425 | cycle_t ret; | |
1426 | u64 last; | |
1427 | ||
1428 | /* | |
1429 | * Empirically, a fence (of type that depends on the CPU) | |
1430 | * before rdtsc is enough to ensure that rdtsc is ordered | |
1431 | * with respect to loads. The various CPU manuals are unclear | |
1432 | * as to whether rdtsc can be reordered with later loads, | |
1433 | * but no one has ever seen it happen. | |
1434 | */ | |
1435 | rdtsc_barrier(); | |
1436 | ret = (cycle_t)vget_cycles(); | |
1437 | ||
1438 | last = pvclock_gtod_data.clock.cycle_last; | |
1439 | ||
1440 | if (likely(ret >= last)) | |
1441 | return ret; | |
1442 | ||
1443 | /* | |
1444 | * GCC likes to generate cmov here, but this branch is extremely | |
1445 | * predictable (it's just a funciton of time and the likely is | |
1446 | * very likely) and there's a data dependence, so force GCC | |
1447 | * to generate a branch instead. I don't barrier() because | |
1448 | * we don't actually need a barrier, and if this function | |
1449 | * ever gets inlined it will generate worse code. | |
1450 | */ | |
1451 | asm volatile (""); | |
1452 | return last; | |
1453 | } | |
1454 | ||
1455 | static inline u64 vgettsc(cycle_t *cycle_now) | |
1456 | { | |
1457 | long v; | |
1458 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
1459 | ||
1460 | *cycle_now = read_tsc(); | |
1461 | ||
1462 | v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask; | |
1463 | return v * gtod->clock.mult; | |
1464 | } | |
1465 | ||
cbcf2dd3 | 1466 | static int do_monotonic_boot(s64 *t, cycle_t *cycle_now) |
d828199e | 1467 | { |
cbcf2dd3 | 1468 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; |
d828199e | 1469 | unsigned long seq; |
d828199e | 1470 | int mode; |
cbcf2dd3 | 1471 | u64 ns; |
d828199e | 1472 | |
d828199e MT |
1473 | do { |
1474 | seq = read_seqcount_begin(>od->seq); | |
1475 | mode = gtod->clock.vclock_mode; | |
cbcf2dd3 | 1476 | ns = gtod->nsec_base; |
d828199e MT |
1477 | ns += vgettsc(cycle_now); |
1478 | ns >>= gtod->clock.shift; | |
cbcf2dd3 | 1479 | ns += gtod->boot_ns; |
d828199e | 1480 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); |
cbcf2dd3 | 1481 | *t = ns; |
d828199e MT |
1482 | |
1483 | return mode; | |
1484 | } | |
1485 | ||
1486 | /* returns true if host is using tsc clocksource */ | |
1487 | static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now) | |
1488 | { | |
d828199e MT |
1489 | /* checked again under seqlock below */ |
1490 | if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC) | |
1491 | return false; | |
1492 | ||
cbcf2dd3 | 1493 | return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC; |
d828199e MT |
1494 | } |
1495 | #endif | |
1496 | ||
1497 | /* | |
1498 | * | |
b48aa97e MT |
1499 | * Assuming a stable TSC across physical CPUS, and a stable TSC |
1500 | * across virtual CPUs, the following condition is possible. | |
1501 | * Each numbered line represents an event visible to both | |
d828199e MT |
1502 | * CPUs at the next numbered event. |
1503 | * | |
1504 | * "timespecX" represents host monotonic time. "tscX" represents | |
1505 | * RDTSC value. | |
1506 | * | |
1507 | * VCPU0 on CPU0 | VCPU1 on CPU1 | |
1508 | * | |
1509 | * 1. read timespec0,tsc0 | |
1510 | * 2. | timespec1 = timespec0 + N | |
1511 | * | tsc1 = tsc0 + M | |
1512 | * 3. transition to guest | transition to guest | |
1513 | * 4. ret0 = timespec0 + (rdtsc - tsc0) | | |
1514 | * 5. | ret1 = timespec1 + (rdtsc - tsc1) | |
1515 | * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) | |
1516 | * | |
1517 | * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: | |
1518 | * | |
1519 | * - ret0 < ret1 | |
1520 | * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) | |
1521 | * ... | |
1522 | * - 0 < N - M => M < N | |
1523 | * | |
1524 | * That is, when timespec0 != timespec1, M < N. Unfortunately that is not | |
1525 | * always the case (the difference between two distinct xtime instances | |
1526 | * might be smaller then the difference between corresponding TSC reads, | |
1527 | * when updating guest vcpus pvclock areas). | |
1528 | * | |
1529 | * To avoid that problem, do not allow visibility of distinct | |
1530 | * system_timestamp/tsc_timestamp values simultaneously: use a master | |
1531 | * copy of host monotonic time values. Update that master copy | |
1532 | * in lockstep. | |
1533 | * | |
b48aa97e | 1534 | * Rely on synchronization of host TSCs and guest TSCs for monotonicity. |
d828199e MT |
1535 | * |
1536 | */ | |
1537 | ||
1538 | static void pvclock_update_vm_gtod_copy(struct kvm *kvm) | |
1539 | { | |
1540 | #ifdef CONFIG_X86_64 | |
1541 | struct kvm_arch *ka = &kvm->arch; | |
1542 | int vclock_mode; | |
b48aa97e MT |
1543 | bool host_tsc_clocksource, vcpus_matched; |
1544 | ||
1545 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
1546 | atomic_read(&kvm->online_vcpus)); | |
d828199e MT |
1547 | |
1548 | /* | |
1549 | * If the host uses TSC clock, then passthrough TSC as stable | |
1550 | * to the guest. | |
1551 | */ | |
b48aa97e | 1552 | host_tsc_clocksource = kvm_get_time_and_clockread( |
d828199e MT |
1553 | &ka->master_kernel_ns, |
1554 | &ka->master_cycle_now); | |
1555 | ||
16a96021 | 1556 | ka->use_master_clock = host_tsc_clocksource && vcpus_matched |
54750f2c MT |
1557 | && !backwards_tsc_observed |
1558 | && !ka->boot_vcpu_runs_old_kvmclock; | |
b48aa97e | 1559 | |
d828199e MT |
1560 | if (ka->use_master_clock) |
1561 | atomic_set(&kvm_guest_has_master_clock, 1); | |
1562 | ||
1563 | vclock_mode = pvclock_gtod_data.clock.vclock_mode; | |
b48aa97e MT |
1564 | trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, |
1565 | vcpus_matched); | |
d828199e MT |
1566 | #endif |
1567 | } | |
1568 | ||
2e762ff7 MT |
1569 | static void kvm_gen_update_masterclock(struct kvm *kvm) |
1570 | { | |
1571 | #ifdef CONFIG_X86_64 | |
1572 | int i; | |
1573 | struct kvm_vcpu *vcpu; | |
1574 | struct kvm_arch *ka = &kvm->arch; | |
1575 | ||
1576 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
1577 | kvm_make_mclock_inprogress_request(kvm); | |
1578 | /* no guest entries from this point */ | |
1579 | pvclock_update_vm_gtod_copy(kvm); | |
1580 | ||
1581 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 1582 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
2e762ff7 MT |
1583 | |
1584 | /* guest entries allowed */ | |
1585 | kvm_for_each_vcpu(i, vcpu, kvm) | |
1586 | clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests); | |
1587 | ||
1588 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
1589 | #endif | |
1590 | } | |
1591 | ||
34c238a1 | 1592 | static int kvm_guest_time_update(struct kvm_vcpu *v) |
18068523 | 1593 | { |
d828199e | 1594 | unsigned long flags, this_tsc_khz; |
18068523 | 1595 | struct kvm_vcpu_arch *vcpu = &v->arch; |
d828199e | 1596 | struct kvm_arch *ka = &v->kvm->arch; |
f25e656d | 1597 | s64 kernel_ns; |
d828199e | 1598 | u64 tsc_timestamp, host_tsc; |
0b79459b | 1599 | struct pvclock_vcpu_time_info guest_hv_clock; |
51d59c6b | 1600 | u8 pvclock_flags; |
d828199e MT |
1601 | bool use_master_clock; |
1602 | ||
1603 | kernel_ns = 0; | |
1604 | host_tsc = 0; | |
18068523 | 1605 | |
d828199e MT |
1606 | /* |
1607 | * If the host uses TSC clock, then passthrough TSC as stable | |
1608 | * to the guest. | |
1609 | */ | |
1610 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
1611 | use_master_clock = ka->use_master_clock; | |
1612 | if (use_master_clock) { | |
1613 | host_tsc = ka->master_cycle_now; | |
1614 | kernel_ns = ka->master_kernel_ns; | |
1615 | } | |
1616 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
c09664bb MT |
1617 | |
1618 | /* Keep irq disabled to prevent changes to the clock */ | |
1619 | local_irq_save(flags); | |
89cbc767 | 1620 | this_tsc_khz = __this_cpu_read(cpu_tsc_khz); |
c09664bb MT |
1621 | if (unlikely(this_tsc_khz == 0)) { |
1622 | local_irq_restore(flags); | |
1623 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); | |
1624 | return 1; | |
1625 | } | |
d828199e MT |
1626 | if (!use_master_clock) { |
1627 | host_tsc = native_read_tsc(); | |
1628 | kernel_ns = get_kernel_ns(); | |
1629 | } | |
1630 | ||
1631 | tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc); | |
1632 | ||
c285545f ZA |
1633 | /* |
1634 | * We may have to catch up the TSC to match elapsed wall clock | |
1635 | * time for two reasons, even if kvmclock is used. | |
1636 | * 1) CPU could have been running below the maximum TSC rate | |
1637 | * 2) Broken TSC compensation resets the base at each VCPU | |
1638 | * entry to avoid unknown leaps of TSC even when running | |
1639 | * again on the same CPU. This may cause apparent elapsed | |
1640 | * time to disappear, and the guest to stand still or run | |
1641 | * very slowly. | |
1642 | */ | |
1643 | if (vcpu->tsc_catchup) { | |
1644 | u64 tsc = compute_guest_tsc(v, kernel_ns); | |
1645 | if (tsc > tsc_timestamp) { | |
f1e2b260 | 1646 | adjust_tsc_offset_guest(v, tsc - tsc_timestamp); |
c285545f ZA |
1647 | tsc_timestamp = tsc; |
1648 | } | |
50d0a0f9 GH |
1649 | } |
1650 | ||
18068523 GOC |
1651 | local_irq_restore(flags); |
1652 | ||
0b79459b | 1653 | if (!vcpu->pv_time_enabled) |
c285545f | 1654 | return 0; |
18068523 | 1655 | |
e48672fa | 1656 | if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) { |
5f4e3f88 ZA |
1657 | kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz, |
1658 | &vcpu->hv_clock.tsc_shift, | |
1659 | &vcpu->hv_clock.tsc_to_system_mul); | |
e48672fa | 1660 | vcpu->hw_tsc_khz = this_tsc_khz; |
8cfdc000 ZA |
1661 | } |
1662 | ||
1663 | /* With all the info we got, fill in the values */ | |
1d5f066e | 1664 | vcpu->hv_clock.tsc_timestamp = tsc_timestamp; |
759379dd | 1665 | vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; |
28e4639a | 1666 | vcpu->last_guest_tsc = tsc_timestamp; |
51d59c6b | 1667 | |
09a0c3f1 OH |
1668 | if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, |
1669 | &guest_hv_clock, sizeof(guest_hv_clock)))) | |
1670 | return 0; | |
1671 | ||
5dca0d91 RK |
1672 | /* This VCPU is paused, but it's legal for a guest to read another |
1673 | * VCPU's kvmclock, so we really have to follow the specification where | |
1674 | * it says that version is odd if data is being modified, and even after | |
1675 | * it is consistent. | |
1676 | * | |
1677 | * Version field updates must be kept separate. This is because | |
1678 | * kvm_write_guest_cached might use a "rep movs" instruction, and | |
1679 | * writes within a string instruction are weakly ordered. So there | |
1680 | * are three writes overall. | |
1681 | * | |
1682 | * As a small optimization, only write the version field in the first | |
1683 | * and third write. The vcpu->pv_time cache is still valid, because the | |
1684 | * version field is the first in the struct. | |
18068523 | 1685 | */ |
5dca0d91 RK |
1686 | BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); |
1687 | ||
1688 | vcpu->hv_clock.version = guest_hv_clock.version + 1; | |
1689 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, | |
1690 | &vcpu->hv_clock, | |
1691 | sizeof(vcpu->hv_clock.version)); | |
1692 | ||
1693 | smp_wmb(); | |
78c0337a MT |
1694 | |
1695 | /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ | |
0b79459b | 1696 | pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); |
78c0337a MT |
1697 | |
1698 | if (vcpu->pvclock_set_guest_stopped_request) { | |
1699 | pvclock_flags |= PVCLOCK_GUEST_STOPPED; | |
1700 | vcpu->pvclock_set_guest_stopped_request = false; | |
1701 | } | |
1702 | ||
d828199e MT |
1703 | /* If the host uses TSC clocksource, then it is stable */ |
1704 | if (use_master_clock) | |
1705 | pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; | |
1706 | ||
78c0337a MT |
1707 | vcpu->hv_clock.flags = pvclock_flags; |
1708 | ||
ce1a5e60 DM |
1709 | trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); |
1710 | ||
0b79459b AH |
1711 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
1712 | &vcpu->hv_clock, | |
1713 | sizeof(vcpu->hv_clock)); | |
5dca0d91 RK |
1714 | |
1715 | smp_wmb(); | |
1716 | ||
1717 | vcpu->hv_clock.version++; | |
1718 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, | |
1719 | &vcpu->hv_clock, | |
1720 | sizeof(vcpu->hv_clock.version)); | |
8cfdc000 | 1721 | return 0; |
c8076604 GH |
1722 | } |
1723 | ||
0061d53d MT |
1724 | /* |
1725 | * kvmclock updates which are isolated to a given vcpu, such as | |
1726 | * vcpu->cpu migration, should not allow system_timestamp from | |
1727 | * the rest of the vcpus to remain static. Otherwise ntp frequency | |
1728 | * correction applies to one vcpu's system_timestamp but not | |
1729 | * the others. | |
1730 | * | |
1731 | * So in those cases, request a kvmclock update for all vcpus. | |
7e44e449 AJ |
1732 | * We need to rate-limit these requests though, as they can |
1733 | * considerably slow guests that have a large number of vcpus. | |
1734 | * The time for a remote vcpu to update its kvmclock is bound | |
1735 | * by the delay we use to rate-limit the updates. | |
0061d53d MT |
1736 | */ |
1737 | ||
7e44e449 AJ |
1738 | #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) |
1739 | ||
1740 | static void kvmclock_update_fn(struct work_struct *work) | |
0061d53d MT |
1741 | { |
1742 | int i; | |
7e44e449 AJ |
1743 | struct delayed_work *dwork = to_delayed_work(work); |
1744 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
1745 | kvmclock_update_work); | |
1746 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
0061d53d MT |
1747 | struct kvm_vcpu *vcpu; |
1748 | ||
1749 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
105b21bb | 1750 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0061d53d MT |
1751 | kvm_vcpu_kick(vcpu); |
1752 | } | |
1753 | } | |
1754 | ||
7e44e449 AJ |
1755 | static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) |
1756 | { | |
1757 | struct kvm *kvm = v->kvm; | |
1758 | ||
105b21bb | 1759 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); |
7e44e449 AJ |
1760 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, |
1761 | KVMCLOCK_UPDATE_DELAY); | |
1762 | } | |
1763 | ||
332967a3 AJ |
1764 | #define KVMCLOCK_SYNC_PERIOD (300 * HZ) |
1765 | ||
1766 | static void kvmclock_sync_fn(struct work_struct *work) | |
1767 | { | |
1768 | struct delayed_work *dwork = to_delayed_work(work); | |
1769 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
1770 | kvmclock_sync_work); | |
1771 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
1772 | ||
1773 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); | |
1774 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
1775 | KVMCLOCK_SYNC_PERIOD); | |
1776 | } | |
1777 | ||
9ba075a6 AK |
1778 | static bool msr_mtrr_valid(unsigned msr) |
1779 | { | |
1780 | switch (msr) { | |
1781 | case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1: | |
1782 | case MSR_MTRRfix64K_00000: | |
1783 | case MSR_MTRRfix16K_80000: | |
1784 | case MSR_MTRRfix16K_A0000: | |
1785 | case MSR_MTRRfix4K_C0000: | |
1786 | case MSR_MTRRfix4K_C8000: | |
1787 | case MSR_MTRRfix4K_D0000: | |
1788 | case MSR_MTRRfix4K_D8000: | |
1789 | case MSR_MTRRfix4K_E0000: | |
1790 | case MSR_MTRRfix4K_E8000: | |
1791 | case MSR_MTRRfix4K_F0000: | |
1792 | case MSR_MTRRfix4K_F8000: | |
1793 | case MSR_MTRRdefType: | |
1794 | case MSR_IA32_CR_PAT: | |
1795 | return true; | |
1796 | case 0x2f8: | |
1797 | return true; | |
1798 | } | |
1799 | return false; | |
1800 | } | |
1801 | ||
d6289b93 MT |
1802 | static bool valid_pat_type(unsigned t) |
1803 | { | |
1804 | return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */ | |
1805 | } | |
1806 | ||
1807 | static bool valid_mtrr_type(unsigned t) | |
1808 | { | |
1809 | return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */ | |
1810 | } | |
1811 | ||
4566654b | 1812 | bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
d6289b93 MT |
1813 | { |
1814 | int i; | |
fd275235 | 1815 | u64 mask; |
d6289b93 MT |
1816 | |
1817 | if (!msr_mtrr_valid(msr)) | |
1818 | return false; | |
1819 | ||
1820 | if (msr == MSR_IA32_CR_PAT) { | |
1821 | for (i = 0; i < 8; i++) | |
1822 | if (!valid_pat_type((data >> (i * 8)) & 0xff)) | |
1823 | return false; | |
1824 | return true; | |
1825 | } else if (msr == MSR_MTRRdefType) { | |
1826 | if (data & ~0xcff) | |
1827 | return false; | |
1828 | return valid_mtrr_type(data & 0xff); | |
1829 | } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) { | |
1830 | for (i = 0; i < 8 ; i++) | |
1831 | if (!valid_mtrr_type((data >> (i * 8)) & 0xff)) | |
1832 | return false; | |
1833 | return true; | |
1834 | } | |
1835 | ||
1836 | /* variable MTRRs */ | |
adfb5d27 WL |
1837 | WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR)); |
1838 | ||
fd275235 | 1839 | mask = (~0ULL) << cpuid_maxphyaddr(vcpu); |
d7a2a246 | 1840 | if ((msr & 1) == 0) { |
adfb5d27 | 1841 | /* MTRR base */ |
d7a2a246 WL |
1842 | if (!valid_mtrr_type(data & 0xff)) |
1843 | return false; | |
1844 | mask |= 0xf00; | |
1845 | } else | |
1846 | /* MTRR mask */ | |
1847 | mask |= 0x7ff; | |
1848 | if (data & mask) { | |
1849 | kvm_inject_gp(vcpu, 0); | |
1850 | return false; | |
1851 | } | |
1852 | ||
adfb5d27 | 1853 | return true; |
d6289b93 | 1854 | } |
4566654b | 1855 | EXPORT_SYMBOL_GPL(kvm_mtrr_valid); |
d6289b93 | 1856 | |
9ba075a6 AK |
1857 | static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
1858 | { | |
0bed3b56 SY |
1859 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; |
1860 | ||
4566654b | 1861 | if (!kvm_mtrr_valid(vcpu, msr, data)) |
9ba075a6 AK |
1862 | return 1; |
1863 | ||
0bed3b56 SY |
1864 | if (msr == MSR_MTRRdefType) { |
1865 | vcpu->arch.mtrr_state.def_type = data; | |
1866 | vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10; | |
1867 | } else if (msr == MSR_MTRRfix64K_00000) | |
1868 | p[0] = data; | |
1869 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
1870 | p[1 + msr - MSR_MTRRfix16K_80000] = data; | |
1871 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
1872 | p[3 + msr - MSR_MTRRfix4K_C0000] = data; | |
1873 | else if (msr == MSR_IA32_CR_PAT) | |
1874 | vcpu->arch.pat = data; | |
1875 | else { /* Variable MTRRs */ | |
1876 | int idx, is_mtrr_mask; | |
1877 | u64 *pt; | |
1878 | ||
1879 | idx = (msr - 0x200) / 2; | |
1880 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
1881 | if (!is_mtrr_mask) | |
1882 | pt = | |
1883 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
1884 | else | |
1885 | pt = | |
1886 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
1887 | *pt = data; | |
1888 | } | |
1889 | ||
1890 | kvm_mmu_reset_context(vcpu); | |
9ba075a6 AK |
1891 | return 0; |
1892 | } | |
15c4a640 | 1893 | |
890ca9ae | 1894 | static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
15c4a640 | 1895 | { |
890ca9ae HY |
1896 | u64 mcg_cap = vcpu->arch.mcg_cap; |
1897 | unsigned bank_num = mcg_cap & 0xff; | |
1898 | ||
15c4a640 | 1899 | switch (msr) { |
15c4a640 | 1900 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 1901 | vcpu->arch.mcg_status = data; |
15c4a640 | 1902 | break; |
c7ac679c | 1903 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
1904 | if (!(mcg_cap & MCG_CTL_P)) |
1905 | return 1; | |
1906 | if (data != 0 && data != ~(u64)0) | |
1907 | return -1; | |
1908 | vcpu->arch.mcg_ctl = data; | |
1909 | break; | |
1910 | default: | |
1911 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 1912 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
890ca9ae | 1913 | u32 offset = msr - MSR_IA32_MC0_CTL; |
114be429 AP |
1914 | /* only 0 or all 1s can be written to IA32_MCi_CTL |
1915 | * some Linux kernels though clear bit 10 in bank 4 to | |
1916 | * workaround a BIOS/GART TBL issue on AMD K8s, ignore | |
1917 | * this to avoid an uncatched #GP in the guest | |
1918 | */ | |
890ca9ae | 1919 | if ((offset & 0x3) == 0 && |
114be429 | 1920 | data != 0 && (data | (1 << 10)) != ~(u64)0) |
890ca9ae HY |
1921 | return -1; |
1922 | vcpu->arch.mce_banks[offset] = data; | |
1923 | break; | |
1924 | } | |
1925 | return 1; | |
1926 | } | |
1927 | return 0; | |
1928 | } | |
1929 | ||
ffde22ac ES |
1930 | static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) |
1931 | { | |
1932 | struct kvm *kvm = vcpu->kvm; | |
1933 | int lm = is_long_mode(vcpu); | |
1934 | u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 | |
1935 | : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; | |
1936 | u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 | |
1937 | : kvm->arch.xen_hvm_config.blob_size_32; | |
1938 | u32 page_num = data & ~PAGE_MASK; | |
1939 | u64 page_addr = data & PAGE_MASK; | |
1940 | u8 *page; | |
1941 | int r; | |
1942 | ||
1943 | r = -E2BIG; | |
1944 | if (page_num >= blob_size) | |
1945 | goto out; | |
1946 | r = -ENOMEM; | |
ff5c2c03 SL |
1947 | page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); |
1948 | if (IS_ERR(page)) { | |
1949 | r = PTR_ERR(page); | |
ffde22ac | 1950 | goto out; |
ff5c2c03 | 1951 | } |
ffde22ac ES |
1952 | if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE)) |
1953 | goto out_free; | |
1954 | r = 0; | |
1955 | out_free: | |
1956 | kfree(page); | |
1957 | out: | |
1958 | return r; | |
1959 | } | |
1960 | ||
55cd8e5a GN |
1961 | static bool kvm_hv_hypercall_enabled(struct kvm *kvm) |
1962 | { | |
1963 | return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE; | |
1964 | } | |
1965 | ||
1966 | static bool kvm_hv_msr_partition_wide(u32 msr) | |
1967 | { | |
1968 | bool r = false; | |
1969 | switch (msr) { | |
1970 | case HV_X64_MSR_GUEST_OS_ID: | |
1971 | case HV_X64_MSR_HYPERCALL: | |
e984097b VR |
1972 | case HV_X64_MSR_REFERENCE_TSC: |
1973 | case HV_X64_MSR_TIME_REF_COUNT: | |
55cd8e5a GN |
1974 | r = true; |
1975 | break; | |
1976 | } | |
1977 | ||
1978 | return r; | |
1979 | } | |
1980 | ||
1981 | static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1982 | { | |
1983 | struct kvm *kvm = vcpu->kvm; | |
1984 | ||
1985 | switch (msr) { | |
1986 | case HV_X64_MSR_GUEST_OS_ID: | |
1987 | kvm->arch.hv_guest_os_id = data; | |
1988 | /* setting guest os id to zero disables hypercall page */ | |
1989 | if (!kvm->arch.hv_guest_os_id) | |
1990 | kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE; | |
1991 | break; | |
1992 | case HV_X64_MSR_HYPERCALL: { | |
1993 | u64 gfn; | |
1994 | unsigned long addr; | |
1995 | u8 instructions[4]; | |
1996 | ||
1997 | /* if guest os id is not set hypercall should remain disabled */ | |
1998 | if (!kvm->arch.hv_guest_os_id) | |
1999 | break; | |
2000 | if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) { | |
2001 | kvm->arch.hv_hypercall = data; | |
2002 | break; | |
2003 | } | |
2004 | gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT; | |
2005 | addr = gfn_to_hva(kvm, gfn); | |
2006 | if (kvm_is_error_hva(addr)) | |
2007 | return 1; | |
2008 | kvm_x86_ops->patch_hypercall(vcpu, instructions); | |
2009 | ((unsigned char *)instructions)[3] = 0xc3; /* ret */ | |
8b0cedff | 2010 | if (__copy_to_user((void __user *)addr, instructions, 4)) |
55cd8e5a GN |
2011 | return 1; |
2012 | kvm->arch.hv_hypercall = data; | |
b94b64c9 | 2013 | mark_page_dirty(kvm, gfn); |
55cd8e5a GN |
2014 | break; |
2015 | } | |
e984097b VR |
2016 | case HV_X64_MSR_REFERENCE_TSC: { |
2017 | u64 gfn; | |
2018 | HV_REFERENCE_TSC_PAGE tsc_ref; | |
2019 | memset(&tsc_ref, 0, sizeof(tsc_ref)); | |
2020 | kvm->arch.hv_tsc_page = data; | |
2021 | if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE)) | |
2022 | break; | |
2023 | gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT; | |
e1fa108d | 2024 | if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT, |
e984097b VR |
2025 | &tsc_ref, sizeof(tsc_ref))) |
2026 | return 1; | |
2027 | mark_page_dirty(kvm, gfn); | |
2028 | break; | |
2029 | } | |
55cd8e5a | 2030 | default: |
a737f256 CD |
2031 | vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " |
2032 | "data 0x%llx\n", msr, data); | |
55cd8e5a GN |
2033 | return 1; |
2034 | } | |
2035 | return 0; | |
2036 | } | |
2037 | ||
2038 | static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
2039 | { | |
10388a07 GN |
2040 | switch (msr) { |
2041 | case HV_X64_MSR_APIC_ASSIST_PAGE: { | |
b3af1e88 | 2042 | u64 gfn; |
10388a07 | 2043 | unsigned long addr; |
55cd8e5a | 2044 | |
10388a07 GN |
2045 | if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) { |
2046 | vcpu->arch.hv_vapic = data; | |
b63cf42f MT |
2047 | if (kvm_lapic_enable_pv_eoi(vcpu, 0)) |
2048 | return 1; | |
10388a07 GN |
2049 | break; |
2050 | } | |
b3af1e88 VR |
2051 | gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT; |
2052 | addr = gfn_to_hva(vcpu->kvm, gfn); | |
10388a07 GN |
2053 | if (kvm_is_error_hva(addr)) |
2054 | return 1; | |
8b0cedff | 2055 | if (__clear_user((void __user *)addr, PAGE_SIZE)) |
10388a07 GN |
2056 | return 1; |
2057 | vcpu->arch.hv_vapic = data; | |
b3af1e88 | 2058 | mark_page_dirty(vcpu->kvm, gfn); |
b63cf42f MT |
2059 | if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED)) |
2060 | return 1; | |
10388a07 GN |
2061 | break; |
2062 | } | |
2063 | case HV_X64_MSR_EOI: | |
2064 | return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data); | |
2065 | case HV_X64_MSR_ICR: | |
2066 | return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data); | |
2067 | case HV_X64_MSR_TPR: | |
2068 | return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data); | |
2069 | default: | |
a737f256 CD |
2070 | vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " |
2071 | "data 0x%llx\n", msr, data); | |
10388a07 GN |
2072 | return 1; |
2073 | } | |
2074 | ||
2075 | return 0; | |
55cd8e5a GN |
2076 | } |
2077 | ||
344d9588 GN |
2078 | static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) |
2079 | { | |
2080 | gpa_t gpa = data & ~0x3f; | |
2081 | ||
4a969980 | 2082 | /* Bits 2:5 are reserved, Should be zero */ |
6adba527 | 2083 | if (data & 0x3c) |
344d9588 GN |
2084 | return 1; |
2085 | ||
2086 | vcpu->arch.apf.msr_val = data; | |
2087 | ||
2088 | if (!(data & KVM_ASYNC_PF_ENABLED)) { | |
2089 | kvm_clear_async_pf_completion_queue(vcpu); | |
2090 | kvm_async_pf_hash_reset(vcpu); | |
2091 | return 0; | |
2092 | } | |
2093 | ||
8f964525 AH |
2094 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, |
2095 | sizeof(u32))) | |
344d9588 GN |
2096 | return 1; |
2097 | ||
6adba527 | 2098 | vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); |
344d9588 GN |
2099 | kvm_async_pf_wakeup_all(vcpu); |
2100 | return 0; | |
2101 | } | |
2102 | ||
12f9a48f GC |
2103 | static void kvmclock_reset(struct kvm_vcpu *vcpu) |
2104 | { | |
0b79459b | 2105 | vcpu->arch.pv_time_enabled = false; |
12f9a48f GC |
2106 | } |
2107 | ||
c9aaa895 GC |
2108 | static void accumulate_steal_time(struct kvm_vcpu *vcpu) |
2109 | { | |
2110 | u64 delta; | |
2111 | ||
2112 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) | |
2113 | return; | |
2114 | ||
2115 | delta = current->sched_info.run_delay - vcpu->arch.st.last_steal; | |
2116 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
2117 | vcpu->arch.st.accum_steal = delta; | |
2118 | } | |
2119 | ||
2120 | static void record_steal_time(struct kvm_vcpu *vcpu) | |
2121 | { | |
2122 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) | |
2123 | return; | |
2124 | ||
2125 | if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, | |
2126 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) | |
2127 | return; | |
2128 | ||
2129 | vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal; | |
2130 | vcpu->arch.st.steal.version += 2; | |
2131 | vcpu->arch.st.accum_steal = 0; | |
2132 | ||
2133 | kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, | |
2134 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); | |
2135 | } | |
2136 | ||
8fe8ab46 | 2137 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 2138 | { |
5753785f | 2139 | bool pr = false; |
8fe8ab46 WA |
2140 | u32 msr = msr_info->index; |
2141 | u64 data = msr_info->data; | |
5753785f | 2142 | |
15c4a640 | 2143 | switch (msr) { |
2e32b719 BP |
2144 | case MSR_AMD64_NB_CFG: |
2145 | case MSR_IA32_UCODE_REV: | |
2146 | case MSR_IA32_UCODE_WRITE: | |
2147 | case MSR_VM_HSAVE_PA: | |
2148 | case MSR_AMD64_PATCH_LOADER: | |
2149 | case MSR_AMD64_BU_CFG2: | |
2150 | break; | |
2151 | ||
15c4a640 | 2152 | case MSR_EFER: |
b69e8cae | 2153 | return set_efer(vcpu, data); |
8f1589d9 AP |
2154 | case MSR_K7_HWCR: |
2155 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
82494028 | 2156 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ |
a223c313 | 2157 | data &= ~(u64)0x8; /* ignore TLB cache disable */ |
22d48b2d | 2158 | data &= ~(u64)0x40000; /* ignore Mc status write enable */ |
8f1589d9 | 2159 | if (data != 0) { |
a737f256 CD |
2160 | vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", |
2161 | data); | |
8f1589d9 AP |
2162 | return 1; |
2163 | } | |
15c4a640 | 2164 | break; |
f7c6d140 AP |
2165 | case MSR_FAM10H_MMIO_CONF_BASE: |
2166 | if (data != 0) { | |
a737f256 CD |
2167 | vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " |
2168 | "0x%llx\n", data); | |
f7c6d140 AP |
2169 | return 1; |
2170 | } | |
15c4a640 | 2171 | break; |
b5e2fec0 AG |
2172 | case MSR_IA32_DEBUGCTLMSR: |
2173 | if (!data) { | |
2174 | /* We support the non-activated case already */ | |
2175 | break; | |
2176 | } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { | |
2177 | /* Values other than LBR and BTF are vendor-specific, | |
2178 | thus reserved and should throw a #GP */ | |
2179 | return 1; | |
2180 | } | |
a737f256 CD |
2181 | vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", |
2182 | __func__, data); | |
b5e2fec0 | 2183 | break; |
9ba075a6 AK |
2184 | case 0x200 ... 0x2ff: |
2185 | return set_msr_mtrr(vcpu, msr, data); | |
15c4a640 | 2186 | case MSR_IA32_APICBASE: |
58cb628d | 2187 | return kvm_set_apic_base(vcpu, msr_info); |
0105d1a5 GN |
2188 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
2189 | return kvm_x2apic_msr_write(vcpu, msr, data); | |
a3e06bbe LJ |
2190 | case MSR_IA32_TSCDEADLINE: |
2191 | kvm_set_lapic_tscdeadline_msr(vcpu, data); | |
2192 | break; | |
ba904635 WA |
2193 | case MSR_IA32_TSC_ADJUST: |
2194 | if (guest_cpuid_has_tsc_adjust(vcpu)) { | |
2195 | if (!msr_info->host_initiated) { | |
d913b904 | 2196 | s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; |
ba904635 WA |
2197 | kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true); |
2198 | } | |
2199 | vcpu->arch.ia32_tsc_adjust_msr = data; | |
2200 | } | |
2201 | break; | |
15c4a640 | 2202 | case MSR_IA32_MISC_ENABLE: |
ad312c7c | 2203 | vcpu->arch.ia32_misc_enable_msr = data; |
15c4a640 | 2204 | break; |
11c6bffa | 2205 | case MSR_KVM_WALL_CLOCK_NEW: |
18068523 GOC |
2206 | case MSR_KVM_WALL_CLOCK: |
2207 | vcpu->kvm->arch.wall_clock = data; | |
2208 | kvm_write_wall_clock(vcpu->kvm, data); | |
2209 | break; | |
11c6bffa | 2210 | case MSR_KVM_SYSTEM_TIME_NEW: |
18068523 | 2211 | case MSR_KVM_SYSTEM_TIME: { |
0b79459b | 2212 | u64 gpa_offset; |
54750f2c MT |
2213 | struct kvm_arch *ka = &vcpu->kvm->arch; |
2214 | ||
12f9a48f | 2215 | kvmclock_reset(vcpu); |
18068523 | 2216 | |
54750f2c MT |
2217 | if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { |
2218 | bool tmp = (msr == MSR_KVM_SYSTEM_TIME); | |
2219 | ||
2220 | if (ka->boot_vcpu_runs_old_kvmclock != tmp) | |
2221 | set_bit(KVM_REQ_MASTERCLOCK_UPDATE, | |
2222 | &vcpu->requests); | |
2223 | ||
2224 | ka->boot_vcpu_runs_old_kvmclock = tmp; | |
2225 | } | |
2226 | ||
18068523 | 2227 | vcpu->arch.time = data; |
0061d53d | 2228 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
18068523 GOC |
2229 | |
2230 | /* we verify if the enable bit is set... */ | |
2231 | if (!(data & 1)) | |
2232 | break; | |
2233 | ||
0b79459b | 2234 | gpa_offset = data & ~(PAGE_MASK | 1); |
18068523 | 2235 | |
0b79459b | 2236 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, |
8f964525 AH |
2237 | &vcpu->arch.pv_time, data & ~1ULL, |
2238 | sizeof(struct pvclock_vcpu_time_info))) | |
0b79459b AH |
2239 | vcpu->arch.pv_time_enabled = false; |
2240 | else | |
2241 | vcpu->arch.pv_time_enabled = true; | |
32cad84f | 2242 | |
18068523 GOC |
2243 | break; |
2244 | } | |
344d9588 GN |
2245 | case MSR_KVM_ASYNC_PF_EN: |
2246 | if (kvm_pv_enable_async_pf(vcpu, data)) | |
2247 | return 1; | |
2248 | break; | |
c9aaa895 GC |
2249 | case MSR_KVM_STEAL_TIME: |
2250 | ||
2251 | if (unlikely(!sched_info_on())) | |
2252 | return 1; | |
2253 | ||
2254 | if (data & KVM_STEAL_RESERVED_MASK) | |
2255 | return 1; | |
2256 | ||
2257 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, | |
8f964525 AH |
2258 | data & KVM_STEAL_VALID_BITS, |
2259 | sizeof(struct kvm_steal_time))) | |
c9aaa895 GC |
2260 | return 1; |
2261 | ||
2262 | vcpu->arch.st.msr_val = data; | |
2263 | ||
2264 | if (!(data & KVM_MSR_ENABLED)) | |
2265 | break; | |
2266 | ||
2267 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
2268 | ||
2269 | preempt_disable(); | |
2270 | accumulate_steal_time(vcpu); | |
2271 | preempt_enable(); | |
2272 | ||
2273 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); | |
2274 | ||
2275 | break; | |
ae7a2a3f MT |
2276 | case MSR_KVM_PV_EOI_EN: |
2277 | if (kvm_lapic_enable_pv_eoi(vcpu, data)) | |
2278 | return 1; | |
2279 | break; | |
c9aaa895 | 2280 | |
890ca9ae HY |
2281 | case MSR_IA32_MCG_CTL: |
2282 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 2283 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
890ca9ae | 2284 | return set_msr_mce(vcpu, msr, data); |
71db6023 AP |
2285 | |
2286 | /* Performance counters are not protected by a CPUID bit, | |
2287 | * so we should check all of them in the generic path for the sake of | |
2288 | * cross vendor migration. | |
2289 | * Writing a zero into the event select MSRs disables them, | |
2290 | * which we perfectly emulate ;-). Any other value should be at least | |
2291 | * reported, some guests depend on them. | |
2292 | */ | |
71db6023 AP |
2293 | case MSR_K7_EVNTSEL0: |
2294 | case MSR_K7_EVNTSEL1: | |
2295 | case MSR_K7_EVNTSEL2: | |
2296 | case MSR_K7_EVNTSEL3: | |
2297 | if (data != 0) | |
a737f256 CD |
2298 | vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: " |
2299 | "0x%x data 0x%llx\n", msr, data); | |
71db6023 AP |
2300 | break; |
2301 | /* at least RHEL 4 unconditionally writes to the perfctr registers, | |
2302 | * so we ignore writes to make it happy. | |
2303 | */ | |
71db6023 AP |
2304 | case MSR_K7_PERFCTR0: |
2305 | case MSR_K7_PERFCTR1: | |
2306 | case MSR_K7_PERFCTR2: | |
2307 | case MSR_K7_PERFCTR3: | |
a737f256 CD |
2308 | vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: " |
2309 | "0x%x data 0x%llx\n", msr, data); | |
71db6023 | 2310 | break; |
5753785f GN |
2311 | case MSR_P6_PERFCTR0: |
2312 | case MSR_P6_PERFCTR1: | |
2313 | pr = true; | |
2314 | case MSR_P6_EVNTSEL0: | |
2315 | case MSR_P6_EVNTSEL1: | |
2316 | if (kvm_pmu_msr(vcpu, msr)) | |
afd80d85 | 2317 | return kvm_pmu_set_msr(vcpu, msr_info); |
5753785f GN |
2318 | |
2319 | if (pr || data != 0) | |
a737f256 CD |
2320 | vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " |
2321 | "0x%x data 0x%llx\n", msr, data); | |
5753785f | 2322 | break; |
84e0cefa JS |
2323 | case MSR_K7_CLK_CTL: |
2324 | /* | |
2325 | * Ignore all writes to this no longer documented MSR. | |
2326 | * Writes are only relevant for old K7 processors, | |
2327 | * all pre-dating SVM, but a recommended workaround from | |
4a969980 | 2328 | * AMD for these chips. It is possible to specify the |
84e0cefa JS |
2329 | * affected processor models on the command line, hence |
2330 | * the need to ignore the workaround. | |
2331 | */ | |
2332 | break; | |
55cd8e5a GN |
2333 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
2334 | if (kvm_hv_msr_partition_wide(msr)) { | |
2335 | int r; | |
2336 | mutex_lock(&vcpu->kvm->lock); | |
2337 | r = set_msr_hyperv_pw(vcpu, msr, data); | |
2338 | mutex_unlock(&vcpu->kvm->lock); | |
2339 | return r; | |
2340 | } else | |
2341 | return set_msr_hyperv(vcpu, msr, data); | |
2342 | break; | |
91c9c3ed | 2343 | case MSR_IA32_BBL_CR_CTL3: |
2344 | /* Drop writes to this legacy MSR -- see rdmsr | |
2345 | * counterpart for further detail. | |
2346 | */ | |
a737f256 | 2347 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data); |
91c9c3ed | 2348 | break; |
2b036c6b BO |
2349 | case MSR_AMD64_OSVW_ID_LENGTH: |
2350 | if (!guest_cpuid_has_osvw(vcpu)) | |
2351 | return 1; | |
2352 | vcpu->arch.osvw.length = data; | |
2353 | break; | |
2354 | case MSR_AMD64_OSVW_STATUS: | |
2355 | if (!guest_cpuid_has_osvw(vcpu)) | |
2356 | return 1; | |
2357 | vcpu->arch.osvw.status = data; | |
2358 | break; | |
15c4a640 | 2359 | default: |
ffde22ac ES |
2360 | if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) |
2361 | return xen_hvm_config(vcpu, data); | |
f5132b01 | 2362 | if (kvm_pmu_msr(vcpu, msr)) |
afd80d85 | 2363 | return kvm_pmu_set_msr(vcpu, msr_info); |
ed85c068 | 2364 | if (!ignore_msrs) { |
a737f256 CD |
2365 | vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", |
2366 | msr, data); | |
ed85c068 AP |
2367 | return 1; |
2368 | } else { | |
a737f256 CD |
2369 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", |
2370 | msr, data); | |
ed85c068 AP |
2371 | break; |
2372 | } | |
15c4a640 CO |
2373 | } |
2374 | return 0; | |
2375 | } | |
2376 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
2377 | ||
2378 | ||
2379 | /* | |
2380 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
2381 | * Returns 0 on success, non-0 otherwise. | |
2382 | * Assumes vcpu_load() was already called. | |
2383 | */ | |
2384 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
2385 | { | |
2386 | return kvm_x86_ops->get_msr(vcpu, msr_index, pdata); | |
2387 | } | |
ff651cb6 | 2388 | EXPORT_SYMBOL_GPL(kvm_get_msr); |
15c4a640 | 2389 | |
9ba075a6 AK |
2390 | static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
2391 | { | |
0bed3b56 SY |
2392 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; |
2393 | ||
9ba075a6 AK |
2394 | if (!msr_mtrr_valid(msr)) |
2395 | return 1; | |
2396 | ||
0bed3b56 SY |
2397 | if (msr == MSR_MTRRdefType) |
2398 | *pdata = vcpu->arch.mtrr_state.def_type + | |
2399 | (vcpu->arch.mtrr_state.enabled << 10); | |
2400 | else if (msr == MSR_MTRRfix64K_00000) | |
2401 | *pdata = p[0]; | |
2402 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
2403 | *pdata = p[1 + msr - MSR_MTRRfix16K_80000]; | |
2404 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
2405 | *pdata = p[3 + msr - MSR_MTRRfix4K_C0000]; | |
2406 | else if (msr == MSR_IA32_CR_PAT) | |
2407 | *pdata = vcpu->arch.pat; | |
2408 | else { /* Variable MTRRs */ | |
2409 | int idx, is_mtrr_mask; | |
2410 | u64 *pt; | |
2411 | ||
2412 | idx = (msr - 0x200) / 2; | |
2413 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
2414 | if (!is_mtrr_mask) | |
2415 | pt = | |
2416 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
2417 | else | |
2418 | pt = | |
2419 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
2420 | *pdata = *pt; | |
2421 | } | |
2422 | ||
9ba075a6 AK |
2423 | return 0; |
2424 | } | |
2425 | ||
890ca9ae | 2426 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
15c4a640 CO |
2427 | { |
2428 | u64 data; | |
890ca9ae HY |
2429 | u64 mcg_cap = vcpu->arch.mcg_cap; |
2430 | unsigned bank_num = mcg_cap & 0xff; | |
15c4a640 CO |
2431 | |
2432 | switch (msr) { | |
15c4a640 CO |
2433 | case MSR_IA32_P5_MC_ADDR: |
2434 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
2435 | data = 0; |
2436 | break; | |
15c4a640 | 2437 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
2438 | data = vcpu->arch.mcg_cap; |
2439 | break; | |
c7ac679c | 2440 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
2441 | if (!(mcg_cap & MCG_CTL_P)) |
2442 | return 1; | |
2443 | data = vcpu->arch.mcg_ctl; | |
2444 | break; | |
2445 | case MSR_IA32_MCG_STATUS: | |
2446 | data = vcpu->arch.mcg_status; | |
2447 | break; | |
2448 | default: | |
2449 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 2450 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
890ca9ae HY |
2451 | u32 offset = msr - MSR_IA32_MC0_CTL; |
2452 | data = vcpu->arch.mce_banks[offset]; | |
2453 | break; | |
2454 | } | |
2455 | return 1; | |
2456 | } | |
2457 | *pdata = data; | |
2458 | return 0; | |
2459 | } | |
2460 | ||
55cd8e5a GN |
2461 | static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
2462 | { | |
2463 | u64 data = 0; | |
2464 | struct kvm *kvm = vcpu->kvm; | |
2465 | ||
2466 | switch (msr) { | |
2467 | case HV_X64_MSR_GUEST_OS_ID: | |
2468 | data = kvm->arch.hv_guest_os_id; | |
2469 | break; | |
2470 | case HV_X64_MSR_HYPERCALL: | |
2471 | data = kvm->arch.hv_hypercall; | |
2472 | break; | |
e984097b VR |
2473 | case HV_X64_MSR_TIME_REF_COUNT: { |
2474 | data = | |
2475 | div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100); | |
2476 | break; | |
2477 | } | |
2478 | case HV_X64_MSR_REFERENCE_TSC: | |
2479 | data = kvm->arch.hv_tsc_page; | |
2480 | break; | |
55cd8e5a | 2481 | default: |
a737f256 | 2482 | vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); |
55cd8e5a GN |
2483 | return 1; |
2484 | } | |
2485 | ||
2486 | *pdata = data; | |
2487 | return 0; | |
2488 | } | |
2489 | ||
2490 | static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) | |
2491 | { | |
2492 | u64 data = 0; | |
2493 | ||
2494 | switch (msr) { | |
2495 | case HV_X64_MSR_VP_INDEX: { | |
2496 | int r; | |
2497 | struct kvm_vcpu *v; | |
684851a1 TY |
2498 | kvm_for_each_vcpu(r, v, vcpu->kvm) { |
2499 | if (v == vcpu) { | |
55cd8e5a | 2500 | data = r; |
684851a1 TY |
2501 | break; |
2502 | } | |
2503 | } | |
55cd8e5a GN |
2504 | break; |
2505 | } | |
10388a07 GN |
2506 | case HV_X64_MSR_EOI: |
2507 | return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata); | |
2508 | case HV_X64_MSR_ICR: | |
2509 | return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata); | |
2510 | case HV_X64_MSR_TPR: | |
2511 | return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata); | |
14fa67ee | 2512 | case HV_X64_MSR_APIC_ASSIST_PAGE: |
d1613ad5 MW |
2513 | data = vcpu->arch.hv_vapic; |
2514 | break; | |
55cd8e5a | 2515 | default: |
a737f256 | 2516 | vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); |
55cd8e5a GN |
2517 | return 1; |
2518 | } | |
2519 | *pdata = data; | |
2520 | return 0; | |
2521 | } | |
2522 | ||
890ca9ae HY |
2523 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
2524 | { | |
2525 | u64 data; | |
2526 | ||
2527 | switch (msr) { | |
890ca9ae | 2528 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 2529 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
2530 | case MSR_IA32_DEBUGCTLMSR: |
2531 | case MSR_IA32_LASTBRANCHFROMIP: | |
2532 | case MSR_IA32_LASTBRANCHTOIP: | |
2533 | case MSR_IA32_LASTINTFROMIP: | |
2534 | case MSR_IA32_LASTINTTOIP: | |
60af2ecd JSR |
2535 | case MSR_K8_SYSCFG: |
2536 | case MSR_K7_HWCR: | |
61a6bd67 | 2537 | case MSR_VM_HSAVE_PA: |
9e699624 | 2538 | case MSR_K7_EVNTSEL0: |
dc9b2d93 WH |
2539 | case MSR_K7_EVNTSEL1: |
2540 | case MSR_K7_EVNTSEL2: | |
2541 | case MSR_K7_EVNTSEL3: | |
1f3ee616 | 2542 | case MSR_K7_PERFCTR0: |
dc9b2d93 WH |
2543 | case MSR_K7_PERFCTR1: |
2544 | case MSR_K7_PERFCTR2: | |
2545 | case MSR_K7_PERFCTR3: | |
1fdbd48c | 2546 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 2547 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 2548 | case MSR_FAM10H_MMIO_CONF_BASE: |
2e32b719 | 2549 | case MSR_AMD64_BU_CFG2: |
15c4a640 CO |
2550 | data = 0; |
2551 | break; | |
5753785f GN |
2552 | case MSR_P6_PERFCTR0: |
2553 | case MSR_P6_PERFCTR1: | |
2554 | case MSR_P6_EVNTSEL0: | |
2555 | case MSR_P6_EVNTSEL1: | |
2556 | if (kvm_pmu_msr(vcpu, msr)) | |
2557 | return kvm_pmu_get_msr(vcpu, msr, pdata); | |
2558 | data = 0; | |
2559 | break; | |
742bc670 MT |
2560 | case MSR_IA32_UCODE_REV: |
2561 | data = 0x100000000ULL; | |
2562 | break; | |
9ba075a6 AK |
2563 | case MSR_MTRRcap: |
2564 | data = 0x500 | KVM_NR_VAR_MTRR; | |
2565 | break; | |
2566 | case 0x200 ... 0x2ff: | |
2567 | return get_msr_mtrr(vcpu, msr, pdata); | |
15c4a640 CO |
2568 | case 0xcd: /* fsb frequency */ |
2569 | data = 3; | |
2570 | break; | |
7b914098 JS |
2571 | /* |
2572 | * MSR_EBC_FREQUENCY_ID | |
2573 | * Conservative value valid for even the basic CPU models. | |
2574 | * Models 0,1: 000 in bits 23:21 indicating a bus speed of | |
2575 | * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, | |
2576 | * and 266MHz for model 3, or 4. Set Core Clock | |
2577 | * Frequency to System Bus Frequency Ratio to 1 (bits | |
2578 | * 31:24) even though these are only valid for CPU | |
2579 | * models > 2, however guests may end up dividing or | |
2580 | * multiplying by zero otherwise. | |
2581 | */ | |
2582 | case MSR_EBC_FREQUENCY_ID: | |
2583 | data = 1 << 24; | |
2584 | break; | |
15c4a640 CO |
2585 | case MSR_IA32_APICBASE: |
2586 | data = kvm_get_apic_base(vcpu); | |
2587 | break; | |
0105d1a5 GN |
2588 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
2589 | return kvm_x2apic_msr_read(vcpu, msr, pdata); | |
2590 | break; | |
a3e06bbe LJ |
2591 | case MSR_IA32_TSCDEADLINE: |
2592 | data = kvm_get_lapic_tscdeadline_msr(vcpu); | |
2593 | break; | |
ba904635 WA |
2594 | case MSR_IA32_TSC_ADJUST: |
2595 | data = (u64)vcpu->arch.ia32_tsc_adjust_msr; | |
2596 | break; | |
15c4a640 | 2597 | case MSR_IA32_MISC_ENABLE: |
ad312c7c | 2598 | data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 2599 | break; |
847f0ad8 AG |
2600 | case MSR_IA32_PERF_STATUS: |
2601 | /* TSC increment by tick */ | |
2602 | data = 1000ULL; | |
2603 | /* CPU multiplier */ | |
2604 | data |= (((uint64_t)4ULL) << 40); | |
2605 | break; | |
15c4a640 | 2606 | case MSR_EFER: |
f6801dff | 2607 | data = vcpu->arch.efer; |
15c4a640 | 2608 | break; |
18068523 | 2609 | case MSR_KVM_WALL_CLOCK: |
11c6bffa | 2610 | case MSR_KVM_WALL_CLOCK_NEW: |
18068523 GOC |
2611 | data = vcpu->kvm->arch.wall_clock; |
2612 | break; | |
2613 | case MSR_KVM_SYSTEM_TIME: | |
11c6bffa | 2614 | case MSR_KVM_SYSTEM_TIME_NEW: |
18068523 GOC |
2615 | data = vcpu->arch.time; |
2616 | break; | |
344d9588 GN |
2617 | case MSR_KVM_ASYNC_PF_EN: |
2618 | data = vcpu->arch.apf.msr_val; | |
2619 | break; | |
c9aaa895 GC |
2620 | case MSR_KVM_STEAL_TIME: |
2621 | data = vcpu->arch.st.msr_val; | |
2622 | break; | |
1d92128f MT |
2623 | case MSR_KVM_PV_EOI_EN: |
2624 | data = vcpu->arch.pv_eoi.msr_val; | |
2625 | break; | |
890ca9ae HY |
2626 | case MSR_IA32_P5_MC_ADDR: |
2627 | case MSR_IA32_P5_MC_TYPE: | |
2628 | case MSR_IA32_MCG_CAP: | |
2629 | case MSR_IA32_MCG_CTL: | |
2630 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 2631 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
890ca9ae | 2632 | return get_msr_mce(vcpu, msr, pdata); |
84e0cefa JS |
2633 | case MSR_K7_CLK_CTL: |
2634 | /* | |
2635 | * Provide expected ramp-up count for K7. All other | |
2636 | * are set to zero, indicating minimum divisors for | |
2637 | * every field. | |
2638 | * | |
2639 | * This prevents guest kernels on AMD host with CPU | |
2640 | * type 6, model 8 and higher from exploding due to | |
2641 | * the rdmsr failing. | |
2642 | */ | |
2643 | data = 0x20000000; | |
2644 | break; | |
55cd8e5a GN |
2645 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
2646 | if (kvm_hv_msr_partition_wide(msr)) { | |
2647 | int r; | |
2648 | mutex_lock(&vcpu->kvm->lock); | |
2649 | r = get_msr_hyperv_pw(vcpu, msr, pdata); | |
2650 | mutex_unlock(&vcpu->kvm->lock); | |
2651 | return r; | |
2652 | } else | |
2653 | return get_msr_hyperv(vcpu, msr, pdata); | |
2654 | break; | |
91c9c3ed | 2655 | case MSR_IA32_BBL_CR_CTL3: |
2656 | /* This legacy MSR exists but isn't fully documented in current | |
2657 | * silicon. It is however accessed by winxp in very narrow | |
2658 | * scenarios where it sets bit #19, itself documented as | |
2659 | * a "reserved" bit. Best effort attempt to source coherent | |
2660 | * read data here should the balance of the register be | |
2661 | * interpreted by the guest: | |
2662 | * | |
2663 | * L2 cache control register 3: 64GB range, 256KB size, | |
2664 | * enabled, latency 0x1, configured | |
2665 | */ | |
2666 | data = 0xbe702111; | |
2667 | break; | |
2b036c6b BO |
2668 | case MSR_AMD64_OSVW_ID_LENGTH: |
2669 | if (!guest_cpuid_has_osvw(vcpu)) | |
2670 | return 1; | |
2671 | data = vcpu->arch.osvw.length; | |
2672 | break; | |
2673 | case MSR_AMD64_OSVW_STATUS: | |
2674 | if (!guest_cpuid_has_osvw(vcpu)) | |
2675 | return 1; | |
2676 | data = vcpu->arch.osvw.status; | |
2677 | break; | |
15c4a640 | 2678 | default: |
f5132b01 GN |
2679 | if (kvm_pmu_msr(vcpu, msr)) |
2680 | return kvm_pmu_get_msr(vcpu, msr, pdata); | |
ed85c068 | 2681 | if (!ignore_msrs) { |
a737f256 | 2682 | vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr); |
ed85c068 AP |
2683 | return 1; |
2684 | } else { | |
a737f256 | 2685 | vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr); |
ed85c068 AP |
2686 | data = 0; |
2687 | } | |
2688 | break; | |
15c4a640 CO |
2689 | } |
2690 | *pdata = data; | |
2691 | return 0; | |
2692 | } | |
2693 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
2694 | ||
313a3dc7 CO |
2695 | /* |
2696 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
2697 | * | |
2698 | * @return number of msrs set successfully. | |
2699 | */ | |
2700 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
2701 | struct kvm_msr_entry *entries, | |
2702 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
2703 | unsigned index, u64 *data)) | |
2704 | { | |
f656ce01 | 2705 | int i, idx; |
313a3dc7 | 2706 | |
f656ce01 | 2707 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
313a3dc7 CO |
2708 | for (i = 0; i < msrs->nmsrs; ++i) |
2709 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
2710 | break; | |
f656ce01 | 2711 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 2712 | |
313a3dc7 CO |
2713 | return i; |
2714 | } | |
2715 | ||
2716 | /* | |
2717 | * Read or write a bunch of msrs. Parameters are user addresses. | |
2718 | * | |
2719 | * @return number of msrs set successfully. | |
2720 | */ | |
2721 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
2722 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
2723 | unsigned index, u64 *data), | |
2724 | int writeback) | |
2725 | { | |
2726 | struct kvm_msrs msrs; | |
2727 | struct kvm_msr_entry *entries; | |
2728 | int r, n; | |
2729 | unsigned size; | |
2730 | ||
2731 | r = -EFAULT; | |
2732 | if (copy_from_user(&msrs, user_msrs, sizeof msrs)) | |
2733 | goto out; | |
2734 | ||
2735 | r = -E2BIG; | |
2736 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
2737 | goto out; | |
2738 | ||
313a3dc7 | 2739 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; |
ff5c2c03 SL |
2740 | entries = memdup_user(user_msrs->entries, size); |
2741 | if (IS_ERR(entries)) { | |
2742 | r = PTR_ERR(entries); | |
313a3dc7 | 2743 | goto out; |
ff5c2c03 | 2744 | } |
313a3dc7 CO |
2745 | |
2746 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
2747 | if (r < 0) | |
2748 | goto out_free; | |
2749 | ||
2750 | r = -EFAULT; | |
2751 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
2752 | goto out_free; | |
2753 | ||
2754 | r = n; | |
2755 | ||
2756 | out_free: | |
7a73c028 | 2757 | kfree(entries); |
313a3dc7 CO |
2758 | out: |
2759 | return r; | |
2760 | } | |
2761 | ||
784aa3d7 | 2762 | int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) |
018d00d2 ZX |
2763 | { |
2764 | int r; | |
2765 | ||
2766 | switch (ext) { | |
2767 | case KVM_CAP_IRQCHIP: | |
2768 | case KVM_CAP_HLT: | |
2769 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 2770 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 2771 | case KVM_CAP_EXT_CPUID: |
9c15bb1d | 2772 | case KVM_CAP_EXT_EMUL_CPUID: |
c8076604 | 2773 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 2774 | case KVM_CAP_PIT: |
a28e4f5a | 2775 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 2776 | case KVM_CAP_MP_STATE: |
ed848624 | 2777 | case KVM_CAP_SYNC_MMU: |
a355c85c | 2778 | case KVM_CAP_USER_NMI: |
52d939a0 | 2779 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 2780 | case KVM_CAP_IRQ_INJECT_STATUS: |
d34e6b17 | 2781 | case KVM_CAP_IOEVENTFD: |
f848a5a8 | 2782 | case KVM_CAP_IOEVENTFD_NO_LENGTH: |
c5ff41ce | 2783 | case KVM_CAP_PIT2: |
e9f42757 | 2784 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 2785 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
ffde22ac | 2786 | case KVM_CAP_XEN_HVM: |
afbcf7ab | 2787 | case KVM_CAP_ADJUST_CLOCK: |
3cfc3092 | 2788 | case KVM_CAP_VCPU_EVENTS: |
55cd8e5a | 2789 | case KVM_CAP_HYPERV: |
10388a07 | 2790 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 2791 | case KVM_CAP_HYPERV_SPIN: |
ab9f4ecb | 2792 | case KVM_CAP_PCI_SEGMENT: |
a1efbe77 | 2793 | case KVM_CAP_DEBUGREGS: |
d2be1651 | 2794 | case KVM_CAP_X86_ROBUST_SINGLESTEP: |
2d5b5a66 | 2795 | case KVM_CAP_XSAVE: |
344d9588 | 2796 | case KVM_CAP_ASYNC_PF: |
92a1f12d | 2797 | case KVM_CAP_GET_TSC_KHZ: |
1c0b28c2 | 2798 | case KVM_CAP_KVMCLOCK_CTRL: |
4d8b81ab | 2799 | case KVM_CAP_READONLY_MEM: |
5f66b620 | 2800 | case KVM_CAP_HYPERV_TIME: |
100943c5 | 2801 | case KVM_CAP_IOAPIC_POLARITY_IGNORED: |
defcf51f | 2802 | case KVM_CAP_TSC_DEADLINE_TIMER: |
2a5bab10 AW |
2803 | #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT |
2804 | case KVM_CAP_ASSIGN_DEV_IRQ: | |
2805 | case KVM_CAP_PCI_2_3: | |
2806 | #endif | |
018d00d2 ZX |
2807 | r = 1; |
2808 | break; | |
542472b5 LV |
2809 | case KVM_CAP_COALESCED_MMIO: |
2810 | r = KVM_COALESCED_MMIO_PAGE_OFFSET; | |
2811 | break; | |
774ead3a AK |
2812 | case KVM_CAP_VAPIC: |
2813 | r = !kvm_x86_ops->cpu_has_accelerated_tpr(); | |
2814 | break; | |
f725230a | 2815 | case KVM_CAP_NR_VCPUS: |
8c3ba334 SL |
2816 | r = KVM_SOFT_MAX_VCPUS; |
2817 | break; | |
2818 | case KVM_CAP_MAX_VCPUS: | |
f725230a AK |
2819 | r = KVM_MAX_VCPUS; |
2820 | break; | |
a988b910 | 2821 | case KVM_CAP_NR_MEMSLOTS: |
bbacc0c1 | 2822 | r = KVM_USER_MEM_SLOTS; |
a988b910 | 2823 | break; |
a68a6a72 MT |
2824 | case KVM_CAP_PV_MMU: /* obsolete */ |
2825 | r = 0; | |
2f333bcb | 2826 | break; |
4cee4b72 | 2827 | #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT |
62c476c7 | 2828 | case KVM_CAP_IOMMU: |
a1b60c1c | 2829 | r = iommu_present(&pci_bus_type); |
62c476c7 | 2830 | break; |
4cee4b72 | 2831 | #endif |
890ca9ae HY |
2832 | case KVM_CAP_MCE: |
2833 | r = KVM_MAX_MCE_BANKS; | |
2834 | break; | |
2d5b5a66 SY |
2835 | case KVM_CAP_XCRS: |
2836 | r = cpu_has_xsave; | |
2837 | break; | |
92a1f12d JR |
2838 | case KVM_CAP_TSC_CONTROL: |
2839 | r = kvm_has_tsc_control; | |
2840 | break; | |
018d00d2 ZX |
2841 | default: |
2842 | r = 0; | |
2843 | break; | |
2844 | } | |
2845 | return r; | |
2846 | ||
2847 | } | |
2848 | ||
043405e1 CO |
2849 | long kvm_arch_dev_ioctl(struct file *filp, |
2850 | unsigned int ioctl, unsigned long arg) | |
2851 | { | |
2852 | void __user *argp = (void __user *)arg; | |
2853 | long r; | |
2854 | ||
2855 | switch (ioctl) { | |
2856 | case KVM_GET_MSR_INDEX_LIST: { | |
2857 | struct kvm_msr_list __user *user_msr_list = argp; | |
2858 | struct kvm_msr_list msr_list; | |
2859 | unsigned n; | |
2860 | ||
2861 | r = -EFAULT; | |
2862 | if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) | |
2863 | goto out; | |
2864 | n = msr_list.nmsrs; | |
2865 | msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs); | |
2866 | if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) | |
2867 | goto out; | |
2868 | r = -E2BIG; | |
e125e7b6 | 2869 | if (n < msr_list.nmsrs) |
043405e1 CO |
2870 | goto out; |
2871 | r = -EFAULT; | |
2872 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
2873 | num_msrs_to_save * sizeof(u32))) | |
2874 | goto out; | |
e125e7b6 | 2875 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 CO |
2876 | &emulated_msrs, |
2877 | ARRAY_SIZE(emulated_msrs) * sizeof(u32))) | |
2878 | goto out; | |
2879 | r = 0; | |
2880 | break; | |
2881 | } | |
9c15bb1d BP |
2882 | case KVM_GET_SUPPORTED_CPUID: |
2883 | case KVM_GET_EMULATED_CPUID: { | |
674eea0f AK |
2884 | struct kvm_cpuid2 __user *cpuid_arg = argp; |
2885 | struct kvm_cpuid2 cpuid; | |
2886 | ||
2887 | r = -EFAULT; | |
2888 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2889 | goto out; | |
9c15bb1d BP |
2890 | |
2891 | r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, | |
2892 | ioctl); | |
674eea0f AK |
2893 | if (r) |
2894 | goto out; | |
2895 | ||
2896 | r = -EFAULT; | |
2897 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
2898 | goto out; | |
2899 | r = 0; | |
2900 | break; | |
2901 | } | |
890ca9ae HY |
2902 | case KVM_X86_GET_MCE_CAP_SUPPORTED: { |
2903 | u64 mce_cap; | |
2904 | ||
2905 | mce_cap = KVM_MCE_CAP_SUPPORTED; | |
2906 | r = -EFAULT; | |
2907 | if (copy_to_user(argp, &mce_cap, sizeof mce_cap)) | |
2908 | goto out; | |
2909 | r = 0; | |
2910 | break; | |
2911 | } | |
043405e1 CO |
2912 | default: |
2913 | r = -EINVAL; | |
2914 | } | |
2915 | out: | |
2916 | return r; | |
2917 | } | |
2918 | ||
f5f48ee1 SY |
2919 | static void wbinvd_ipi(void *garbage) |
2920 | { | |
2921 | wbinvd(); | |
2922 | } | |
2923 | ||
2924 | static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
2925 | { | |
e0f0bbc5 | 2926 | return kvm_arch_has_noncoherent_dma(vcpu->kvm); |
f5f48ee1 SY |
2927 | } |
2928 | ||
313a3dc7 CO |
2929 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
2930 | { | |
f5f48ee1 SY |
2931 | /* Address WBINVD may be executed by guest */ |
2932 | if (need_emulate_wbinvd(vcpu)) { | |
2933 | if (kvm_x86_ops->has_wbinvd_exit()) | |
2934 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
2935 | else if (vcpu->cpu != -1 && vcpu->cpu != cpu) | |
2936 | smp_call_function_single(vcpu->cpu, | |
2937 | wbinvd_ipi, NULL, 1); | |
2938 | } | |
2939 | ||
313a3dc7 | 2940 | kvm_x86_ops->vcpu_load(vcpu, cpu); |
8f6055cb | 2941 | |
0dd6a6ed ZA |
2942 | /* Apply any externally detected TSC adjustments (due to suspend) */ |
2943 | if (unlikely(vcpu->arch.tsc_offset_adjustment)) { | |
2944 | adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); | |
2945 | vcpu->arch.tsc_offset_adjustment = 0; | |
105b21bb | 2946 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed | 2947 | } |
8f6055cb | 2948 | |
48434c20 | 2949 | if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) { |
6f526ec5 ZA |
2950 | s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : |
2951 | native_read_tsc() - vcpu->arch.last_host_tsc; | |
e48672fa ZA |
2952 | if (tsc_delta < 0) |
2953 | mark_tsc_unstable("KVM discovered backwards TSC"); | |
c285545f | 2954 | if (check_tsc_unstable()) { |
b183aa58 ZA |
2955 | u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu, |
2956 | vcpu->arch.last_guest_tsc); | |
2957 | kvm_x86_ops->write_tsc_offset(vcpu, offset); | |
c285545f | 2958 | vcpu->arch.tsc_catchup = 1; |
c285545f | 2959 | } |
d98d07ca MT |
2960 | /* |
2961 | * On a host with synchronized TSC, there is no need to update | |
2962 | * kvmclock on vcpu->cpu migration | |
2963 | */ | |
2964 | if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) | |
0061d53d | 2965 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
c285545f ZA |
2966 | if (vcpu->cpu != cpu) |
2967 | kvm_migrate_timers(vcpu); | |
e48672fa | 2968 | vcpu->cpu = cpu; |
6b7d7e76 | 2969 | } |
c9aaa895 GC |
2970 | |
2971 | accumulate_steal_time(vcpu); | |
2972 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); | |
313a3dc7 CO |
2973 | } |
2974 | ||
2975 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) | |
2976 | { | |
02daab21 | 2977 | kvm_x86_ops->vcpu_put(vcpu); |
1c11e713 | 2978 | kvm_put_guest_fpu(vcpu); |
6f526ec5 | 2979 | vcpu->arch.last_host_tsc = native_read_tsc(); |
313a3dc7 CO |
2980 | } |
2981 | ||
313a3dc7 CO |
2982 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
2983 | struct kvm_lapic_state *s) | |
2984 | { | |
5a71785d | 2985 | kvm_x86_ops->sync_pir_to_irr(vcpu); |
ad312c7c | 2986 | memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s); |
313a3dc7 CO |
2987 | |
2988 | return 0; | |
2989 | } | |
2990 | ||
2991 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
2992 | struct kvm_lapic_state *s) | |
2993 | { | |
64eb0620 | 2994 | kvm_apic_post_state_restore(vcpu, s); |
cb142eb7 | 2995 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
2996 | |
2997 | return 0; | |
2998 | } | |
2999 | ||
f77bc6a4 ZX |
3000 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
3001 | struct kvm_interrupt *irq) | |
3002 | { | |
02cdb50f | 3003 | if (irq->irq >= KVM_NR_INTERRUPTS) |
f77bc6a4 ZX |
3004 | return -EINVAL; |
3005 | if (irqchip_in_kernel(vcpu->kvm)) | |
3006 | return -ENXIO; | |
f77bc6a4 | 3007 | |
66fd3f7f | 3008 | kvm_queue_interrupt(vcpu, irq->irq, false); |
3842d135 | 3009 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f77bc6a4 | 3010 | |
f77bc6a4 ZX |
3011 | return 0; |
3012 | } | |
3013 | ||
c4abb7c9 JK |
3014 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
3015 | { | |
c4abb7c9 | 3016 | kvm_inject_nmi(vcpu); |
c4abb7c9 JK |
3017 | |
3018 | return 0; | |
3019 | } | |
3020 | ||
b209749f AK |
3021 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
3022 | struct kvm_tpr_access_ctl *tac) | |
3023 | { | |
3024 | if (tac->flags) | |
3025 | return -EINVAL; | |
3026 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
3027 | return 0; | |
3028 | } | |
3029 | ||
890ca9ae HY |
3030 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
3031 | u64 mcg_cap) | |
3032 | { | |
3033 | int r; | |
3034 | unsigned bank_num = mcg_cap & 0xff, bank; | |
3035 | ||
3036 | r = -EINVAL; | |
a9e38c3e | 3037 | if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) |
890ca9ae HY |
3038 | goto out; |
3039 | if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000)) | |
3040 | goto out; | |
3041 | r = 0; | |
3042 | vcpu->arch.mcg_cap = mcg_cap; | |
3043 | /* Init IA32_MCG_CTL to all 1s */ | |
3044 | if (mcg_cap & MCG_CTL_P) | |
3045 | vcpu->arch.mcg_ctl = ~(u64)0; | |
3046 | /* Init IA32_MCi_CTL to all 1s */ | |
3047 | for (bank = 0; bank < bank_num; bank++) | |
3048 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
3049 | out: | |
3050 | return r; | |
3051 | } | |
3052 | ||
3053 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
3054 | struct kvm_x86_mce *mce) | |
3055 | { | |
3056 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
3057 | unsigned bank_num = mcg_cap & 0xff; | |
3058 | u64 *banks = vcpu->arch.mce_banks; | |
3059 | ||
3060 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
3061 | return -EINVAL; | |
3062 | /* | |
3063 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
3064 | * reporting is disabled | |
3065 | */ | |
3066 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
3067 | vcpu->arch.mcg_ctl != ~(u64)0) | |
3068 | return 0; | |
3069 | banks += 4 * mce->bank; | |
3070 | /* | |
3071 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
3072 | * reporting is disabled for the bank | |
3073 | */ | |
3074 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
3075 | return 0; | |
3076 | if (mce->status & MCI_STATUS_UC) { | |
3077 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
fc78f519 | 3078 | !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { |
a8eeb04a | 3079 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
890ca9ae HY |
3080 | return 0; |
3081 | } | |
3082 | if (banks[1] & MCI_STATUS_VAL) | |
3083 | mce->status |= MCI_STATUS_OVER; | |
3084 | banks[2] = mce->addr; | |
3085 | banks[3] = mce->misc; | |
3086 | vcpu->arch.mcg_status = mce->mcg_status; | |
3087 | banks[1] = mce->status; | |
3088 | kvm_queue_exception(vcpu, MC_VECTOR); | |
3089 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
3090 | || !(banks[1] & MCI_STATUS_UC)) { | |
3091 | if (banks[1] & MCI_STATUS_VAL) | |
3092 | mce->status |= MCI_STATUS_OVER; | |
3093 | banks[2] = mce->addr; | |
3094 | banks[3] = mce->misc; | |
3095 | banks[1] = mce->status; | |
3096 | } else | |
3097 | banks[1] |= MCI_STATUS_OVER; | |
3098 | return 0; | |
3099 | } | |
3100 | ||
3cfc3092 JK |
3101 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
3102 | struct kvm_vcpu_events *events) | |
3103 | { | |
7460fb4a | 3104 | process_nmi(vcpu); |
03b82a30 JK |
3105 | events->exception.injected = |
3106 | vcpu->arch.exception.pending && | |
3107 | !kvm_exception_is_soft(vcpu->arch.exception.nr); | |
3cfc3092 JK |
3108 | events->exception.nr = vcpu->arch.exception.nr; |
3109 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
97e69aa6 | 3110 | events->exception.pad = 0; |
3cfc3092 JK |
3111 | events->exception.error_code = vcpu->arch.exception.error_code; |
3112 | ||
03b82a30 JK |
3113 | events->interrupt.injected = |
3114 | vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; | |
3cfc3092 | 3115 | events->interrupt.nr = vcpu->arch.interrupt.nr; |
03b82a30 | 3116 | events->interrupt.soft = 0; |
37ccdcbe | 3117 | events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); |
3cfc3092 JK |
3118 | |
3119 | events->nmi.injected = vcpu->arch.nmi_injected; | |
7460fb4a | 3120 | events->nmi.pending = vcpu->arch.nmi_pending != 0; |
3cfc3092 | 3121 | events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); |
97e69aa6 | 3122 | events->nmi.pad = 0; |
3cfc3092 | 3123 | |
66450a21 | 3124 | events->sipi_vector = 0; /* never valid when reporting to user space */ |
3cfc3092 | 3125 | |
dab4b911 | 3126 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 | 3127 | | KVM_VCPUEVENT_VALID_SHADOW); |
97e69aa6 | 3128 | memset(&events->reserved, 0, sizeof(events->reserved)); |
3cfc3092 JK |
3129 | } |
3130 | ||
3131 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, | |
3132 | struct kvm_vcpu_events *events) | |
3133 | { | |
dab4b911 | 3134 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 JK |
3135 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
3136 | | KVM_VCPUEVENT_VALID_SHADOW)) | |
3cfc3092 JK |
3137 | return -EINVAL; |
3138 | ||
7460fb4a | 3139 | process_nmi(vcpu); |
3cfc3092 JK |
3140 | vcpu->arch.exception.pending = events->exception.injected; |
3141 | vcpu->arch.exception.nr = events->exception.nr; | |
3142 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
3143 | vcpu->arch.exception.error_code = events->exception.error_code; | |
3144 | ||
3145 | vcpu->arch.interrupt.pending = events->interrupt.injected; | |
3146 | vcpu->arch.interrupt.nr = events->interrupt.nr; | |
3147 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
48005f64 JK |
3148 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) |
3149 | kvm_x86_ops->set_interrupt_shadow(vcpu, | |
3150 | events->interrupt.shadow); | |
3cfc3092 JK |
3151 | |
3152 | vcpu->arch.nmi_injected = events->nmi.injected; | |
dab4b911 JK |
3153 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) |
3154 | vcpu->arch.nmi_pending = events->nmi.pending; | |
3cfc3092 JK |
3155 | kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); |
3156 | ||
66450a21 JK |
3157 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && |
3158 | kvm_vcpu_has_lapic(vcpu)) | |
3159 | vcpu->arch.apic->sipi_vector = events->sipi_vector; | |
3cfc3092 | 3160 | |
3842d135 AK |
3161 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
3162 | ||
3cfc3092 JK |
3163 | return 0; |
3164 | } | |
3165 | ||
a1efbe77 JK |
3166 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, |
3167 | struct kvm_debugregs *dbgregs) | |
3168 | { | |
73aaf249 JK |
3169 | unsigned long val; |
3170 | ||
a1efbe77 | 3171 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); |
16f8a6f9 | 3172 | kvm_get_dr(vcpu, 6, &val); |
73aaf249 | 3173 | dbgregs->dr6 = val; |
a1efbe77 JK |
3174 | dbgregs->dr7 = vcpu->arch.dr7; |
3175 | dbgregs->flags = 0; | |
97e69aa6 | 3176 | memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); |
a1efbe77 JK |
3177 | } |
3178 | ||
3179 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
3180 | struct kvm_debugregs *dbgregs) | |
3181 | { | |
3182 | if (dbgregs->flags) | |
3183 | return -EINVAL; | |
3184 | ||
a1efbe77 | 3185 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); |
ae561ede | 3186 | kvm_update_dr0123(vcpu); |
a1efbe77 | 3187 | vcpu->arch.dr6 = dbgregs->dr6; |
73aaf249 | 3188 | kvm_update_dr6(vcpu); |
a1efbe77 | 3189 | vcpu->arch.dr7 = dbgregs->dr7; |
9926c9fd | 3190 | kvm_update_dr7(vcpu); |
a1efbe77 | 3191 | |
a1efbe77 JK |
3192 | return 0; |
3193 | } | |
3194 | ||
df1daba7 PB |
3195 | #define XSTATE_COMPACTION_ENABLED (1ULL << 63) |
3196 | ||
3197 | static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) | |
3198 | { | |
3199 | struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave; | |
3200 | u64 xstate_bv = xsave->xsave_hdr.xstate_bv; | |
3201 | u64 valid; | |
3202 | ||
3203 | /* | |
3204 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
3205 | * leaves 0 and 1 in the loop below. | |
3206 | */ | |
3207 | memcpy(dest, xsave, XSAVE_HDR_OFFSET); | |
3208 | ||
3209 | /* Set XSTATE_BV */ | |
3210 | *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; | |
3211 | ||
3212 | /* | |
3213 | * Copy each region from the possibly compacted offset to the | |
3214 | * non-compacted offset. | |
3215 | */ | |
3216 | valid = xstate_bv & ~XSTATE_FPSSE; | |
3217 | while (valid) { | |
3218 | u64 feature = valid & -valid; | |
3219 | int index = fls64(feature) - 1; | |
3220 | void *src = get_xsave_addr(xsave, feature); | |
3221 | ||
3222 | if (src) { | |
3223 | u32 size, offset, ecx, edx; | |
3224 | cpuid_count(XSTATE_CPUID, index, | |
3225 | &size, &offset, &ecx, &edx); | |
3226 | memcpy(dest + offset, src, size); | |
3227 | } | |
3228 | ||
3229 | valid -= feature; | |
3230 | } | |
3231 | } | |
3232 | ||
3233 | static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) | |
3234 | { | |
3235 | struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave; | |
3236 | u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); | |
3237 | u64 valid; | |
3238 | ||
3239 | /* | |
3240 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
3241 | * leaves 0 and 1 in the loop below. | |
3242 | */ | |
3243 | memcpy(xsave, src, XSAVE_HDR_OFFSET); | |
3244 | ||
3245 | /* Set XSTATE_BV and possibly XCOMP_BV. */ | |
3246 | xsave->xsave_hdr.xstate_bv = xstate_bv; | |
3247 | if (cpu_has_xsaves) | |
3248 | xsave->xsave_hdr.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; | |
3249 | ||
3250 | /* | |
3251 | * Copy each region from the non-compacted offset to the | |
3252 | * possibly compacted offset. | |
3253 | */ | |
3254 | valid = xstate_bv & ~XSTATE_FPSSE; | |
3255 | while (valid) { | |
3256 | u64 feature = valid & -valid; | |
3257 | int index = fls64(feature) - 1; | |
3258 | void *dest = get_xsave_addr(xsave, feature); | |
3259 | ||
3260 | if (dest) { | |
3261 | u32 size, offset, ecx, edx; | |
3262 | cpuid_count(XSTATE_CPUID, index, | |
3263 | &size, &offset, &ecx, &edx); | |
3264 | memcpy(dest, src + offset, size); | |
3265 | } else | |
3266 | WARN_ON_ONCE(1); | |
3267 | ||
3268 | valid -= feature; | |
3269 | } | |
3270 | } | |
3271 | ||
2d5b5a66 SY |
3272 | static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, |
3273 | struct kvm_xsave *guest_xsave) | |
3274 | { | |
4344ee98 | 3275 | if (cpu_has_xsave) { |
df1daba7 PB |
3276 | memset(guest_xsave, 0, sizeof(struct kvm_xsave)); |
3277 | fill_xsave((u8 *) guest_xsave->region, vcpu); | |
4344ee98 | 3278 | } else { |
2d5b5a66 SY |
3279 | memcpy(guest_xsave->region, |
3280 | &vcpu->arch.guest_fpu.state->fxsave, | |
3281 | sizeof(struct i387_fxsave_struct)); | |
3282 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = | |
3283 | XSTATE_FPSSE; | |
3284 | } | |
3285 | } | |
3286 | ||
3287 | static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, | |
3288 | struct kvm_xsave *guest_xsave) | |
3289 | { | |
3290 | u64 xstate_bv = | |
3291 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; | |
3292 | ||
d7876f1b PB |
3293 | if (cpu_has_xsave) { |
3294 | /* | |
3295 | * Here we allow setting states that are not present in | |
3296 | * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility | |
3297 | * with old userspace. | |
3298 | */ | |
4ff41732 | 3299 | if (xstate_bv & ~kvm_supported_xcr0()) |
d7876f1b | 3300 | return -EINVAL; |
df1daba7 | 3301 | load_xsave(vcpu, (u8 *)guest_xsave->region); |
d7876f1b | 3302 | } else { |
2d5b5a66 SY |
3303 | if (xstate_bv & ~XSTATE_FPSSE) |
3304 | return -EINVAL; | |
3305 | memcpy(&vcpu->arch.guest_fpu.state->fxsave, | |
3306 | guest_xsave->region, sizeof(struct i387_fxsave_struct)); | |
3307 | } | |
3308 | return 0; | |
3309 | } | |
3310 | ||
3311 | static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, | |
3312 | struct kvm_xcrs *guest_xcrs) | |
3313 | { | |
3314 | if (!cpu_has_xsave) { | |
3315 | guest_xcrs->nr_xcrs = 0; | |
3316 | return; | |
3317 | } | |
3318 | ||
3319 | guest_xcrs->nr_xcrs = 1; | |
3320 | guest_xcrs->flags = 0; | |
3321 | guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; | |
3322 | guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; | |
3323 | } | |
3324 | ||
3325 | static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, | |
3326 | struct kvm_xcrs *guest_xcrs) | |
3327 | { | |
3328 | int i, r = 0; | |
3329 | ||
3330 | if (!cpu_has_xsave) | |
3331 | return -EINVAL; | |
3332 | ||
3333 | if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) | |
3334 | return -EINVAL; | |
3335 | ||
3336 | for (i = 0; i < guest_xcrs->nr_xcrs; i++) | |
3337 | /* Only support XCR0 currently */ | |
c67a04cb | 3338 | if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { |
2d5b5a66 | 3339 | r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, |
c67a04cb | 3340 | guest_xcrs->xcrs[i].value); |
2d5b5a66 SY |
3341 | break; |
3342 | } | |
3343 | if (r) | |
3344 | r = -EINVAL; | |
3345 | return r; | |
3346 | } | |
3347 | ||
1c0b28c2 EM |
3348 | /* |
3349 | * kvm_set_guest_paused() indicates to the guest kernel that it has been | |
3350 | * stopped by the hypervisor. This function will be called from the host only. | |
3351 | * EINVAL is returned when the host attempts to set the flag for a guest that | |
3352 | * does not support pv clocks. | |
3353 | */ | |
3354 | static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) | |
3355 | { | |
0b79459b | 3356 | if (!vcpu->arch.pv_time_enabled) |
1c0b28c2 | 3357 | return -EINVAL; |
51d59c6b | 3358 | vcpu->arch.pvclock_set_guest_stopped_request = true; |
1c0b28c2 EM |
3359 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
3360 | return 0; | |
3361 | } | |
3362 | ||
313a3dc7 CO |
3363 | long kvm_arch_vcpu_ioctl(struct file *filp, |
3364 | unsigned int ioctl, unsigned long arg) | |
3365 | { | |
3366 | struct kvm_vcpu *vcpu = filp->private_data; | |
3367 | void __user *argp = (void __user *)arg; | |
3368 | int r; | |
d1ac91d8 AK |
3369 | union { |
3370 | struct kvm_lapic_state *lapic; | |
3371 | struct kvm_xsave *xsave; | |
3372 | struct kvm_xcrs *xcrs; | |
3373 | void *buffer; | |
3374 | } u; | |
3375 | ||
3376 | u.buffer = NULL; | |
313a3dc7 CO |
3377 | switch (ioctl) { |
3378 | case KVM_GET_LAPIC: { | |
2204ae3c MT |
3379 | r = -EINVAL; |
3380 | if (!vcpu->arch.apic) | |
3381 | goto out; | |
d1ac91d8 | 3382 | u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); |
313a3dc7 | 3383 | |
b772ff36 | 3384 | r = -ENOMEM; |
d1ac91d8 | 3385 | if (!u.lapic) |
b772ff36 | 3386 | goto out; |
d1ac91d8 | 3387 | r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); |
313a3dc7 CO |
3388 | if (r) |
3389 | goto out; | |
3390 | r = -EFAULT; | |
d1ac91d8 | 3391 | if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
3392 | goto out; |
3393 | r = 0; | |
3394 | break; | |
3395 | } | |
3396 | case KVM_SET_LAPIC: { | |
2204ae3c MT |
3397 | r = -EINVAL; |
3398 | if (!vcpu->arch.apic) | |
3399 | goto out; | |
ff5c2c03 | 3400 | u.lapic = memdup_user(argp, sizeof(*u.lapic)); |
18595411 GC |
3401 | if (IS_ERR(u.lapic)) |
3402 | return PTR_ERR(u.lapic); | |
ff5c2c03 | 3403 | |
d1ac91d8 | 3404 | r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); |
313a3dc7 CO |
3405 | break; |
3406 | } | |
f77bc6a4 ZX |
3407 | case KVM_INTERRUPT: { |
3408 | struct kvm_interrupt irq; | |
3409 | ||
3410 | r = -EFAULT; | |
3411 | if (copy_from_user(&irq, argp, sizeof irq)) | |
3412 | goto out; | |
3413 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
f77bc6a4 ZX |
3414 | break; |
3415 | } | |
c4abb7c9 JK |
3416 | case KVM_NMI: { |
3417 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
c4abb7c9 JK |
3418 | break; |
3419 | } | |
313a3dc7 CO |
3420 | case KVM_SET_CPUID: { |
3421 | struct kvm_cpuid __user *cpuid_arg = argp; | |
3422 | struct kvm_cpuid cpuid; | |
3423 | ||
3424 | r = -EFAULT; | |
3425 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
3426 | goto out; | |
3427 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
313a3dc7 CO |
3428 | break; |
3429 | } | |
07716717 DK |
3430 | case KVM_SET_CPUID2: { |
3431 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
3432 | struct kvm_cpuid2 cpuid; | |
3433 | ||
3434 | r = -EFAULT; | |
3435 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
3436 | goto out; | |
3437 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 3438 | cpuid_arg->entries); |
07716717 DK |
3439 | break; |
3440 | } | |
3441 | case KVM_GET_CPUID2: { | |
3442 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
3443 | struct kvm_cpuid2 cpuid; | |
3444 | ||
3445 | r = -EFAULT; | |
3446 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
3447 | goto out; | |
3448 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 3449 | cpuid_arg->entries); |
07716717 DK |
3450 | if (r) |
3451 | goto out; | |
3452 | r = -EFAULT; | |
3453 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
3454 | goto out; | |
3455 | r = 0; | |
3456 | break; | |
3457 | } | |
313a3dc7 CO |
3458 | case KVM_GET_MSRS: |
3459 | r = msr_io(vcpu, argp, kvm_get_msr, 1); | |
3460 | break; | |
3461 | case KVM_SET_MSRS: | |
3462 | r = msr_io(vcpu, argp, do_set_msr, 0); | |
3463 | break; | |
b209749f AK |
3464 | case KVM_TPR_ACCESS_REPORTING: { |
3465 | struct kvm_tpr_access_ctl tac; | |
3466 | ||
3467 | r = -EFAULT; | |
3468 | if (copy_from_user(&tac, argp, sizeof tac)) | |
3469 | goto out; | |
3470 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
3471 | if (r) | |
3472 | goto out; | |
3473 | r = -EFAULT; | |
3474 | if (copy_to_user(argp, &tac, sizeof tac)) | |
3475 | goto out; | |
3476 | r = 0; | |
3477 | break; | |
3478 | }; | |
b93463aa AK |
3479 | case KVM_SET_VAPIC_ADDR: { |
3480 | struct kvm_vapic_addr va; | |
3481 | ||
3482 | r = -EINVAL; | |
3483 | if (!irqchip_in_kernel(vcpu->kvm)) | |
3484 | goto out; | |
3485 | r = -EFAULT; | |
3486 | if (copy_from_user(&va, argp, sizeof va)) | |
3487 | goto out; | |
fda4e2e8 | 3488 | r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); |
b93463aa AK |
3489 | break; |
3490 | } | |
890ca9ae HY |
3491 | case KVM_X86_SETUP_MCE: { |
3492 | u64 mcg_cap; | |
3493 | ||
3494 | r = -EFAULT; | |
3495 | if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) | |
3496 | goto out; | |
3497 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
3498 | break; | |
3499 | } | |
3500 | case KVM_X86_SET_MCE: { | |
3501 | struct kvm_x86_mce mce; | |
3502 | ||
3503 | r = -EFAULT; | |
3504 | if (copy_from_user(&mce, argp, sizeof mce)) | |
3505 | goto out; | |
3506 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
3507 | break; | |
3508 | } | |
3cfc3092 JK |
3509 | case KVM_GET_VCPU_EVENTS: { |
3510 | struct kvm_vcpu_events events; | |
3511 | ||
3512 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
3513 | ||
3514 | r = -EFAULT; | |
3515 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
3516 | break; | |
3517 | r = 0; | |
3518 | break; | |
3519 | } | |
3520 | case KVM_SET_VCPU_EVENTS: { | |
3521 | struct kvm_vcpu_events events; | |
3522 | ||
3523 | r = -EFAULT; | |
3524 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
3525 | break; | |
3526 | ||
3527 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
3528 | break; | |
3529 | } | |
a1efbe77 JK |
3530 | case KVM_GET_DEBUGREGS: { |
3531 | struct kvm_debugregs dbgregs; | |
3532 | ||
3533 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
3534 | ||
3535 | r = -EFAULT; | |
3536 | if (copy_to_user(argp, &dbgregs, | |
3537 | sizeof(struct kvm_debugregs))) | |
3538 | break; | |
3539 | r = 0; | |
3540 | break; | |
3541 | } | |
3542 | case KVM_SET_DEBUGREGS: { | |
3543 | struct kvm_debugregs dbgregs; | |
3544 | ||
3545 | r = -EFAULT; | |
3546 | if (copy_from_user(&dbgregs, argp, | |
3547 | sizeof(struct kvm_debugregs))) | |
3548 | break; | |
3549 | ||
3550 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
3551 | break; | |
3552 | } | |
2d5b5a66 | 3553 | case KVM_GET_XSAVE: { |
d1ac91d8 | 3554 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); |
2d5b5a66 | 3555 | r = -ENOMEM; |
d1ac91d8 | 3556 | if (!u.xsave) |
2d5b5a66 SY |
3557 | break; |
3558 | ||
d1ac91d8 | 3559 | kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
3560 | |
3561 | r = -EFAULT; | |
d1ac91d8 | 3562 | if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
3563 | break; |
3564 | r = 0; | |
3565 | break; | |
3566 | } | |
3567 | case KVM_SET_XSAVE: { | |
ff5c2c03 | 3568 | u.xsave = memdup_user(argp, sizeof(*u.xsave)); |
18595411 GC |
3569 | if (IS_ERR(u.xsave)) |
3570 | return PTR_ERR(u.xsave); | |
2d5b5a66 | 3571 | |
d1ac91d8 | 3572 | r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
3573 | break; |
3574 | } | |
3575 | case KVM_GET_XCRS: { | |
d1ac91d8 | 3576 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); |
2d5b5a66 | 3577 | r = -ENOMEM; |
d1ac91d8 | 3578 | if (!u.xcrs) |
2d5b5a66 SY |
3579 | break; |
3580 | ||
d1ac91d8 | 3581 | kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
3582 | |
3583 | r = -EFAULT; | |
d1ac91d8 | 3584 | if (copy_to_user(argp, u.xcrs, |
2d5b5a66 SY |
3585 | sizeof(struct kvm_xcrs))) |
3586 | break; | |
3587 | r = 0; | |
3588 | break; | |
3589 | } | |
3590 | case KVM_SET_XCRS: { | |
ff5c2c03 | 3591 | u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); |
18595411 GC |
3592 | if (IS_ERR(u.xcrs)) |
3593 | return PTR_ERR(u.xcrs); | |
2d5b5a66 | 3594 | |
d1ac91d8 | 3595 | r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
3596 | break; |
3597 | } | |
92a1f12d JR |
3598 | case KVM_SET_TSC_KHZ: { |
3599 | u32 user_tsc_khz; | |
3600 | ||
3601 | r = -EINVAL; | |
92a1f12d JR |
3602 | user_tsc_khz = (u32)arg; |
3603 | ||
3604 | if (user_tsc_khz >= kvm_max_guest_tsc_khz) | |
3605 | goto out; | |
3606 | ||
cc578287 ZA |
3607 | if (user_tsc_khz == 0) |
3608 | user_tsc_khz = tsc_khz; | |
3609 | ||
3610 | kvm_set_tsc_khz(vcpu, user_tsc_khz); | |
92a1f12d JR |
3611 | |
3612 | r = 0; | |
3613 | goto out; | |
3614 | } | |
3615 | case KVM_GET_TSC_KHZ: { | |
cc578287 | 3616 | r = vcpu->arch.virtual_tsc_khz; |
92a1f12d JR |
3617 | goto out; |
3618 | } | |
1c0b28c2 EM |
3619 | case KVM_KVMCLOCK_CTRL: { |
3620 | r = kvm_set_guest_paused(vcpu); | |
3621 | goto out; | |
3622 | } | |
313a3dc7 CO |
3623 | default: |
3624 | r = -EINVAL; | |
3625 | } | |
3626 | out: | |
d1ac91d8 | 3627 | kfree(u.buffer); |
313a3dc7 CO |
3628 | return r; |
3629 | } | |
3630 | ||
5b1c1493 CO |
3631 | int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) |
3632 | { | |
3633 | return VM_FAULT_SIGBUS; | |
3634 | } | |
3635 | ||
1fe779f8 CO |
3636 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
3637 | { | |
3638 | int ret; | |
3639 | ||
3640 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
951179ce | 3641 | return -EINVAL; |
1fe779f8 CO |
3642 | ret = kvm_x86_ops->set_tss_addr(kvm, addr); |
3643 | return ret; | |
3644 | } | |
3645 | ||
b927a3ce SY |
3646 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
3647 | u64 ident_addr) | |
3648 | { | |
3649 | kvm->arch.ept_identity_map_addr = ident_addr; | |
3650 | return 0; | |
3651 | } | |
3652 | ||
1fe779f8 CO |
3653 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
3654 | u32 kvm_nr_mmu_pages) | |
3655 | { | |
3656 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
3657 | return -EINVAL; | |
3658 | ||
79fac95e | 3659 | mutex_lock(&kvm->slots_lock); |
1fe779f8 CO |
3660 | |
3661 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 3662 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 3663 | |
79fac95e | 3664 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
3665 | return 0; |
3666 | } | |
3667 | ||
3668 | static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) | |
3669 | { | |
39de71ec | 3670 | return kvm->arch.n_max_mmu_pages; |
1fe779f8 CO |
3671 | } |
3672 | ||
1fe779f8 CO |
3673 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) |
3674 | { | |
3675 | int r; | |
3676 | ||
3677 | r = 0; | |
3678 | switch (chip->chip_id) { | |
3679 | case KVM_IRQCHIP_PIC_MASTER: | |
3680 | memcpy(&chip->chip.pic, | |
3681 | &pic_irqchip(kvm)->pics[0], | |
3682 | sizeof(struct kvm_pic_state)); | |
3683 | break; | |
3684 | case KVM_IRQCHIP_PIC_SLAVE: | |
3685 | memcpy(&chip->chip.pic, | |
3686 | &pic_irqchip(kvm)->pics[1], | |
3687 | sizeof(struct kvm_pic_state)); | |
3688 | break; | |
3689 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 3690 | r = kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
3691 | break; |
3692 | default: | |
3693 | r = -EINVAL; | |
3694 | break; | |
3695 | } | |
3696 | return r; | |
3697 | } | |
3698 | ||
3699 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
3700 | { | |
3701 | int r; | |
3702 | ||
3703 | r = 0; | |
3704 | switch (chip->chip_id) { | |
3705 | case KVM_IRQCHIP_PIC_MASTER: | |
f4f51050 | 3706 | spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3707 | memcpy(&pic_irqchip(kvm)->pics[0], |
3708 | &chip->chip.pic, | |
3709 | sizeof(struct kvm_pic_state)); | |
f4f51050 | 3710 | spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3711 | break; |
3712 | case KVM_IRQCHIP_PIC_SLAVE: | |
f4f51050 | 3713 | spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3714 | memcpy(&pic_irqchip(kvm)->pics[1], |
3715 | &chip->chip.pic, | |
3716 | sizeof(struct kvm_pic_state)); | |
f4f51050 | 3717 | spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3718 | break; |
3719 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 3720 | r = kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
3721 | break; |
3722 | default: | |
3723 | r = -EINVAL; | |
3724 | break; | |
3725 | } | |
3726 | kvm_pic_update_irq(pic_irqchip(kvm)); | |
3727 | return r; | |
3728 | } | |
3729 | ||
e0f63cb9 SY |
3730 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
3731 | { | |
3732 | int r = 0; | |
3733 | ||
894a9c55 | 3734 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 | 3735 | memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state)); |
894a9c55 | 3736 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 SY |
3737 | return r; |
3738 | } | |
3739 | ||
3740 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
3741 | { | |
3742 | int r = 0; | |
3743 | ||
894a9c55 | 3744 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 | 3745 | memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state)); |
e9f42757 BK |
3746 | kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0); |
3747 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
3748 | return r; | |
3749 | } | |
3750 | ||
3751 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
3752 | { | |
3753 | int r = 0; | |
3754 | ||
3755 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
3756 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
3757 | sizeof(ps->channels)); | |
3758 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
3759 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
97e69aa6 | 3760 | memset(&ps->reserved, 0, sizeof(ps->reserved)); |
e9f42757 BK |
3761 | return r; |
3762 | } | |
3763 | ||
3764 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
3765 | { | |
3766 | int r = 0, start = 0; | |
3767 | u32 prev_legacy, cur_legacy; | |
3768 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
3769 | prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
3770 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
3771 | if (!prev_legacy && cur_legacy) | |
3772 | start = 1; | |
3773 | memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels, | |
3774 | sizeof(kvm->arch.vpit->pit_state.channels)); | |
3775 | kvm->arch.vpit->pit_state.flags = ps->flags; | |
3776 | kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start); | |
894a9c55 | 3777 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 SY |
3778 | return r; |
3779 | } | |
3780 | ||
52d939a0 MT |
3781 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
3782 | struct kvm_reinject_control *control) | |
3783 | { | |
3784 | if (!kvm->arch.vpit) | |
3785 | return -ENXIO; | |
894a9c55 | 3786 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
26ef1924 | 3787 | kvm->arch.vpit->pit_state.reinject = control->pit_reinject; |
894a9c55 | 3788 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
52d939a0 MT |
3789 | return 0; |
3790 | } | |
3791 | ||
95d4c16c | 3792 | /** |
60c34612 TY |
3793 | * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot |
3794 | * @kvm: kvm instance | |
3795 | * @log: slot id and address to which we copy the log | |
95d4c16c | 3796 | * |
e108ff2f PB |
3797 | * Steps 1-4 below provide general overview of dirty page logging. See |
3798 | * kvm_get_dirty_log_protect() function description for additional details. | |
3799 | * | |
3800 | * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we | |
3801 | * always flush the TLB (step 4) even if previous step failed and the dirty | |
3802 | * bitmap may be corrupt. Regardless of previous outcome the KVM logging API | |
3803 | * does not preclude user space subsequent dirty log read. Flushing TLB ensures | |
3804 | * writes will be marked dirty for next log read. | |
95d4c16c | 3805 | * |
60c34612 TY |
3806 | * 1. Take a snapshot of the bit and clear it if needed. |
3807 | * 2. Write protect the corresponding page. | |
e108ff2f PB |
3808 | * 3. Copy the snapshot to the userspace. |
3809 | * 4. Flush TLB's if needed. | |
5bb064dc | 3810 | */ |
60c34612 | 3811 | int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) |
5bb064dc | 3812 | { |
60c34612 | 3813 | bool is_dirty = false; |
e108ff2f | 3814 | int r; |
5bb064dc | 3815 | |
79fac95e | 3816 | mutex_lock(&kvm->slots_lock); |
5bb064dc | 3817 | |
88178fd4 KH |
3818 | /* |
3819 | * Flush potentially hardware-cached dirty pages to dirty_bitmap. | |
3820 | */ | |
3821 | if (kvm_x86_ops->flush_log_dirty) | |
3822 | kvm_x86_ops->flush_log_dirty(kvm); | |
3823 | ||
e108ff2f | 3824 | r = kvm_get_dirty_log_protect(kvm, log, &is_dirty); |
198c74f4 XG |
3825 | |
3826 | /* | |
3827 | * All the TLBs can be flushed out of mmu lock, see the comments in | |
3828 | * kvm_mmu_slot_remove_write_access(). | |
3829 | */ | |
e108ff2f | 3830 | lockdep_assert_held(&kvm->slots_lock); |
198c74f4 XG |
3831 | if (is_dirty) |
3832 | kvm_flush_remote_tlbs(kvm); | |
3833 | ||
79fac95e | 3834 | mutex_unlock(&kvm->slots_lock); |
5bb064dc ZX |
3835 | return r; |
3836 | } | |
3837 | ||
aa2fbe6d YZ |
3838 | int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, |
3839 | bool line_status) | |
23d43cf9 CD |
3840 | { |
3841 | if (!irqchip_in_kernel(kvm)) | |
3842 | return -ENXIO; | |
3843 | ||
3844 | irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, | |
aa2fbe6d YZ |
3845 | irq_event->irq, irq_event->level, |
3846 | line_status); | |
23d43cf9 CD |
3847 | return 0; |
3848 | } | |
3849 | ||
1fe779f8 CO |
3850 | long kvm_arch_vm_ioctl(struct file *filp, |
3851 | unsigned int ioctl, unsigned long arg) | |
3852 | { | |
3853 | struct kvm *kvm = filp->private_data; | |
3854 | void __user *argp = (void __user *)arg; | |
367e1319 | 3855 | int r = -ENOTTY; |
f0d66275 DH |
3856 | /* |
3857 | * This union makes it completely explicit to gcc-3.x | |
3858 | * that these two variables' stack usage should be | |
3859 | * combined, not added together. | |
3860 | */ | |
3861 | union { | |
3862 | struct kvm_pit_state ps; | |
e9f42757 | 3863 | struct kvm_pit_state2 ps2; |
c5ff41ce | 3864 | struct kvm_pit_config pit_config; |
f0d66275 | 3865 | } u; |
1fe779f8 CO |
3866 | |
3867 | switch (ioctl) { | |
3868 | case KVM_SET_TSS_ADDR: | |
3869 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
1fe779f8 | 3870 | break; |
b927a3ce SY |
3871 | case KVM_SET_IDENTITY_MAP_ADDR: { |
3872 | u64 ident_addr; | |
3873 | ||
3874 | r = -EFAULT; | |
3875 | if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) | |
3876 | goto out; | |
3877 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); | |
b927a3ce SY |
3878 | break; |
3879 | } | |
1fe779f8 CO |
3880 | case KVM_SET_NR_MMU_PAGES: |
3881 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
1fe779f8 CO |
3882 | break; |
3883 | case KVM_GET_NR_MMU_PAGES: | |
3884 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
3885 | break; | |
3ddea128 MT |
3886 | case KVM_CREATE_IRQCHIP: { |
3887 | struct kvm_pic *vpic; | |
3888 | ||
3889 | mutex_lock(&kvm->lock); | |
3890 | r = -EEXIST; | |
3891 | if (kvm->arch.vpic) | |
3892 | goto create_irqchip_unlock; | |
3e515705 AK |
3893 | r = -EINVAL; |
3894 | if (atomic_read(&kvm->online_vcpus)) | |
3895 | goto create_irqchip_unlock; | |
1fe779f8 | 3896 | r = -ENOMEM; |
3ddea128 MT |
3897 | vpic = kvm_create_pic(kvm); |
3898 | if (vpic) { | |
1fe779f8 CO |
3899 | r = kvm_ioapic_init(kvm); |
3900 | if (r) { | |
175504cd | 3901 | mutex_lock(&kvm->slots_lock); |
72bb2fcd | 3902 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, |
743eeb0b SL |
3903 | &vpic->dev_master); |
3904 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, | |
3905 | &vpic->dev_slave); | |
3906 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, | |
3907 | &vpic->dev_eclr); | |
175504cd | 3908 | mutex_unlock(&kvm->slots_lock); |
3ddea128 MT |
3909 | kfree(vpic); |
3910 | goto create_irqchip_unlock; | |
1fe779f8 CO |
3911 | } |
3912 | } else | |
3ddea128 MT |
3913 | goto create_irqchip_unlock; |
3914 | smp_wmb(); | |
3915 | kvm->arch.vpic = vpic; | |
3916 | smp_wmb(); | |
399ec807 AK |
3917 | r = kvm_setup_default_irq_routing(kvm); |
3918 | if (r) { | |
175504cd | 3919 | mutex_lock(&kvm->slots_lock); |
3ddea128 | 3920 | mutex_lock(&kvm->irq_lock); |
72bb2fcd WY |
3921 | kvm_ioapic_destroy(kvm); |
3922 | kvm_destroy_pic(kvm); | |
3ddea128 | 3923 | mutex_unlock(&kvm->irq_lock); |
175504cd | 3924 | mutex_unlock(&kvm->slots_lock); |
399ec807 | 3925 | } |
3ddea128 MT |
3926 | create_irqchip_unlock: |
3927 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 3928 | break; |
3ddea128 | 3929 | } |
7837699f | 3930 | case KVM_CREATE_PIT: |
c5ff41ce JK |
3931 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
3932 | goto create_pit; | |
3933 | case KVM_CREATE_PIT2: | |
3934 | r = -EFAULT; | |
3935 | if (copy_from_user(&u.pit_config, argp, | |
3936 | sizeof(struct kvm_pit_config))) | |
3937 | goto out; | |
3938 | create_pit: | |
79fac95e | 3939 | mutex_lock(&kvm->slots_lock); |
269e05e4 AK |
3940 | r = -EEXIST; |
3941 | if (kvm->arch.vpit) | |
3942 | goto create_pit_unlock; | |
7837699f | 3943 | r = -ENOMEM; |
c5ff41ce | 3944 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
3945 | if (kvm->arch.vpit) |
3946 | r = 0; | |
269e05e4 | 3947 | create_pit_unlock: |
79fac95e | 3948 | mutex_unlock(&kvm->slots_lock); |
7837699f | 3949 | break; |
1fe779f8 CO |
3950 | case KVM_GET_IRQCHIP: { |
3951 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 3952 | struct kvm_irqchip *chip; |
1fe779f8 | 3953 | |
ff5c2c03 SL |
3954 | chip = memdup_user(argp, sizeof(*chip)); |
3955 | if (IS_ERR(chip)) { | |
3956 | r = PTR_ERR(chip); | |
1fe779f8 | 3957 | goto out; |
ff5c2c03 SL |
3958 | } |
3959 | ||
1fe779f8 CO |
3960 | r = -ENXIO; |
3961 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
3962 | goto get_irqchip_out; |
3963 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 3964 | if (r) |
f0d66275 | 3965 | goto get_irqchip_out; |
1fe779f8 | 3966 | r = -EFAULT; |
f0d66275 DH |
3967 | if (copy_to_user(argp, chip, sizeof *chip)) |
3968 | goto get_irqchip_out; | |
1fe779f8 | 3969 | r = 0; |
f0d66275 DH |
3970 | get_irqchip_out: |
3971 | kfree(chip); | |
1fe779f8 CO |
3972 | break; |
3973 | } | |
3974 | case KVM_SET_IRQCHIP: { | |
3975 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 3976 | struct kvm_irqchip *chip; |
1fe779f8 | 3977 | |
ff5c2c03 SL |
3978 | chip = memdup_user(argp, sizeof(*chip)); |
3979 | if (IS_ERR(chip)) { | |
3980 | r = PTR_ERR(chip); | |
1fe779f8 | 3981 | goto out; |
ff5c2c03 SL |
3982 | } |
3983 | ||
1fe779f8 CO |
3984 | r = -ENXIO; |
3985 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
3986 | goto set_irqchip_out; |
3987 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
1fe779f8 | 3988 | if (r) |
f0d66275 | 3989 | goto set_irqchip_out; |
1fe779f8 | 3990 | r = 0; |
f0d66275 DH |
3991 | set_irqchip_out: |
3992 | kfree(chip); | |
1fe779f8 CO |
3993 | break; |
3994 | } | |
e0f63cb9 | 3995 | case KVM_GET_PIT: { |
e0f63cb9 | 3996 | r = -EFAULT; |
f0d66275 | 3997 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
3998 | goto out; |
3999 | r = -ENXIO; | |
4000 | if (!kvm->arch.vpit) | |
4001 | goto out; | |
f0d66275 | 4002 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
4003 | if (r) |
4004 | goto out; | |
4005 | r = -EFAULT; | |
f0d66275 | 4006 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
4007 | goto out; |
4008 | r = 0; | |
4009 | break; | |
4010 | } | |
4011 | case KVM_SET_PIT: { | |
e0f63cb9 | 4012 | r = -EFAULT; |
f0d66275 | 4013 | if (copy_from_user(&u.ps, argp, sizeof u.ps)) |
e0f63cb9 SY |
4014 | goto out; |
4015 | r = -ENXIO; | |
4016 | if (!kvm->arch.vpit) | |
4017 | goto out; | |
f0d66275 | 4018 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
e0f63cb9 SY |
4019 | break; |
4020 | } | |
e9f42757 BK |
4021 | case KVM_GET_PIT2: { |
4022 | r = -ENXIO; | |
4023 | if (!kvm->arch.vpit) | |
4024 | goto out; | |
4025 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
4026 | if (r) | |
4027 | goto out; | |
4028 | r = -EFAULT; | |
4029 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
4030 | goto out; | |
4031 | r = 0; | |
4032 | break; | |
4033 | } | |
4034 | case KVM_SET_PIT2: { | |
4035 | r = -EFAULT; | |
4036 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
4037 | goto out; | |
4038 | r = -ENXIO; | |
4039 | if (!kvm->arch.vpit) | |
4040 | goto out; | |
4041 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); | |
e9f42757 BK |
4042 | break; |
4043 | } | |
52d939a0 MT |
4044 | case KVM_REINJECT_CONTROL: { |
4045 | struct kvm_reinject_control control; | |
4046 | r = -EFAULT; | |
4047 | if (copy_from_user(&control, argp, sizeof(control))) | |
4048 | goto out; | |
4049 | r = kvm_vm_ioctl_reinject(kvm, &control); | |
52d939a0 MT |
4050 | break; |
4051 | } | |
ffde22ac ES |
4052 | case KVM_XEN_HVM_CONFIG: { |
4053 | r = -EFAULT; | |
4054 | if (copy_from_user(&kvm->arch.xen_hvm_config, argp, | |
4055 | sizeof(struct kvm_xen_hvm_config))) | |
4056 | goto out; | |
4057 | r = -EINVAL; | |
4058 | if (kvm->arch.xen_hvm_config.flags) | |
4059 | goto out; | |
4060 | r = 0; | |
4061 | break; | |
4062 | } | |
afbcf7ab | 4063 | case KVM_SET_CLOCK: { |
afbcf7ab GC |
4064 | struct kvm_clock_data user_ns; |
4065 | u64 now_ns; | |
4066 | s64 delta; | |
4067 | ||
4068 | r = -EFAULT; | |
4069 | if (copy_from_user(&user_ns, argp, sizeof(user_ns))) | |
4070 | goto out; | |
4071 | ||
4072 | r = -EINVAL; | |
4073 | if (user_ns.flags) | |
4074 | goto out; | |
4075 | ||
4076 | r = 0; | |
395c6b0a | 4077 | local_irq_disable(); |
759379dd | 4078 | now_ns = get_kernel_ns(); |
afbcf7ab | 4079 | delta = user_ns.clock - now_ns; |
395c6b0a | 4080 | local_irq_enable(); |
afbcf7ab | 4081 | kvm->arch.kvmclock_offset = delta; |
2e762ff7 | 4082 | kvm_gen_update_masterclock(kvm); |
afbcf7ab GC |
4083 | break; |
4084 | } | |
4085 | case KVM_GET_CLOCK: { | |
afbcf7ab GC |
4086 | struct kvm_clock_data user_ns; |
4087 | u64 now_ns; | |
4088 | ||
395c6b0a | 4089 | local_irq_disable(); |
759379dd | 4090 | now_ns = get_kernel_ns(); |
afbcf7ab | 4091 | user_ns.clock = kvm->arch.kvmclock_offset + now_ns; |
395c6b0a | 4092 | local_irq_enable(); |
afbcf7ab | 4093 | user_ns.flags = 0; |
97e69aa6 | 4094 | memset(&user_ns.pad, 0, sizeof(user_ns.pad)); |
afbcf7ab GC |
4095 | |
4096 | r = -EFAULT; | |
4097 | if (copy_to_user(argp, &user_ns, sizeof(user_ns))) | |
4098 | goto out; | |
4099 | r = 0; | |
4100 | break; | |
4101 | } | |
4102 | ||
1fe779f8 | 4103 | default: |
c274e03a | 4104 | r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg); |
1fe779f8 CO |
4105 | } |
4106 | out: | |
4107 | return r; | |
4108 | } | |
4109 | ||
a16b043c | 4110 | static void kvm_init_msr_list(void) |
043405e1 CO |
4111 | { |
4112 | u32 dummy[2]; | |
4113 | unsigned i, j; | |
4114 | ||
e3267cbb GC |
4115 | /* skip the first msrs in the list. KVM-specific */ |
4116 | for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) { | |
043405e1 CO |
4117 | if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) |
4118 | continue; | |
93c4adc7 PB |
4119 | |
4120 | /* | |
4121 | * Even MSRs that are valid in the host may not be exposed | |
4122 | * to the guests in some cases. We could work around this | |
4123 | * in VMX with the generic MSR save/load machinery, but it | |
4124 | * is not really worthwhile since it will really only | |
4125 | * happen with nested virtualization. | |
4126 | */ | |
4127 | switch (msrs_to_save[i]) { | |
4128 | case MSR_IA32_BNDCFGS: | |
4129 | if (!kvm_x86_ops->mpx_supported()) | |
4130 | continue; | |
4131 | break; | |
4132 | default: | |
4133 | break; | |
4134 | } | |
4135 | ||
043405e1 CO |
4136 | if (j < i) |
4137 | msrs_to_save[j] = msrs_to_save[i]; | |
4138 | j++; | |
4139 | } | |
4140 | num_msrs_to_save = j; | |
4141 | } | |
4142 | ||
bda9020e MT |
4143 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
4144 | const void *v) | |
bbd9b64e | 4145 | { |
70252a10 AK |
4146 | int handled = 0; |
4147 | int n; | |
4148 | ||
4149 | do { | |
4150 | n = min(len, 8); | |
4151 | if (!(vcpu->arch.apic && | |
e32edf4f NN |
4152 | !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) |
4153 | && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 AK |
4154 | break; |
4155 | handled += n; | |
4156 | addr += n; | |
4157 | len -= n; | |
4158 | v += n; | |
4159 | } while (len); | |
bbd9b64e | 4160 | |
70252a10 | 4161 | return handled; |
bbd9b64e CO |
4162 | } |
4163 | ||
bda9020e | 4164 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 4165 | { |
70252a10 AK |
4166 | int handled = 0; |
4167 | int n; | |
4168 | ||
4169 | do { | |
4170 | n = min(len, 8); | |
4171 | if (!(vcpu->arch.apic && | |
e32edf4f NN |
4172 | !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, |
4173 | addr, n, v)) | |
4174 | && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 AK |
4175 | break; |
4176 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v); | |
4177 | handled += n; | |
4178 | addr += n; | |
4179 | len -= n; | |
4180 | v += n; | |
4181 | } while (len); | |
bbd9b64e | 4182 | |
70252a10 | 4183 | return handled; |
bbd9b64e CO |
4184 | } |
4185 | ||
2dafc6c2 GN |
4186 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
4187 | struct kvm_segment *var, int seg) | |
4188 | { | |
4189 | kvm_x86_ops->set_segment(vcpu, var, seg); | |
4190 | } | |
4191 | ||
4192 | void kvm_get_segment(struct kvm_vcpu *vcpu, | |
4193 | struct kvm_segment *var, int seg) | |
4194 | { | |
4195 | kvm_x86_ops->get_segment(vcpu, var, seg); | |
4196 | } | |
4197 | ||
54987b7a PB |
4198 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
4199 | struct x86_exception *exception) | |
02f59dc9 JR |
4200 | { |
4201 | gpa_t t_gpa; | |
02f59dc9 JR |
4202 | |
4203 | BUG_ON(!mmu_is_nested(vcpu)); | |
4204 | ||
4205 | /* NPT walks are always user-walks */ | |
4206 | access |= PFERR_USER_MASK; | |
54987b7a | 4207 | t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception); |
02f59dc9 JR |
4208 | |
4209 | return t_gpa; | |
4210 | } | |
4211 | ||
ab9ae313 AK |
4212 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
4213 | struct x86_exception *exception) | |
1871c602 GN |
4214 | { |
4215 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
ab9ae313 | 4216 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
4217 | } |
4218 | ||
ab9ae313 AK |
4219 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, |
4220 | struct x86_exception *exception) | |
1871c602 GN |
4221 | { |
4222 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
4223 | access |= PFERR_FETCH_MASK; | |
ab9ae313 | 4224 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
4225 | } |
4226 | ||
ab9ae313 AK |
4227 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, |
4228 | struct x86_exception *exception) | |
1871c602 GN |
4229 | { |
4230 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
4231 | access |= PFERR_WRITE_MASK; | |
ab9ae313 | 4232 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
4233 | } |
4234 | ||
4235 | /* uses this to access any guest's mapped memory without checking CPL */ | |
ab9ae313 AK |
4236 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, |
4237 | struct x86_exception *exception) | |
1871c602 | 4238 | { |
ab9ae313 | 4239 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); |
1871c602 GN |
4240 | } |
4241 | ||
4242 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
4243 | struct kvm_vcpu *vcpu, u32 access, | |
bcc55cba | 4244 | struct x86_exception *exception) |
bbd9b64e CO |
4245 | { |
4246 | void *data = val; | |
10589a46 | 4247 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
4248 | |
4249 | while (bytes) { | |
14dfe855 | 4250 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, |
ab9ae313 | 4251 | exception); |
bbd9b64e | 4252 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 4253 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
4254 | int ret; |
4255 | ||
bcc55cba | 4256 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 4257 | return X86EMUL_PROPAGATE_FAULT; |
44583cba PB |
4258 | ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data, |
4259 | offset, toread); | |
10589a46 | 4260 | if (ret < 0) { |
c3cd7ffa | 4261 | r = X86EMUL_IO_NEEDED; |
10589a46 MT |
4262 | goto out; |
4263 | } | |
bbd9b64e | 4264 | |
77c2002e IE |
4265 | bytes -= toread; |
4266 | data += toread; | |
4267 | addr += toread; | |
bbd9b64e | 4268 | } |
10589a46 | 4269 | out: |
10589a46 | 4270 | return r; |
bbd9b64e | 4271 | } |
77c2002e | 4272 | |
1871c602 | 4273 | /* used for instruction fetching */ |
0f65dd70 AK |
4274 | static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, |
4275 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 4276 | struct x86_exception *exception) |
1871c602 | 4277 | { |
0f65dd70 | 4278 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
1871c602 | 4279 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
44583cba PB |
4280 | unsigned offset; |
4281 | int ret; | |
0f65dd70 | 4282 | |
44583cba PB |
4283 | /* Inline kvm_read_guest_virt_helper for speed. */ |
4284 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, | |
4285 | exception); | |
4286 | if (unlikely(gpa == UNMAPPED_GVA)) | |
4287 | return X86EMUL_PROPAGATE_FAULT; | |
4288 | ||
4289 | offset = addr & (PAGE_SIZE-1); | |
4290 | if (WARN_ON(offset + bytes > PAGE_SIZE)) | |
4291 | bytes = (unsigned)PAGE_SIZE - offset; | |
4292 | ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val, | |
4293 | offset, bytes); | |
4294 | if (unlikely(ret < 0)) | |
4295 | return X86EMUL_IO_NEEDED; | |
4296 | ||
4297 | return X86EMUL_CONTINUE; | |
1871c602 GN |
4298 | } |
4299 | ||
064aea77 | 4300 | int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt, |
0f65dd70 | 4301 | gva_t addr, void *val, unsigned int bytes, |
bcc55cba | 4302 | struct x86_exception *exception) |
1871c602 | 4303 | { |
0f65dd70 | 4304 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
1871c602 | 4305 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
0f65dd70 | 4306 | |
1871c602 | 4307 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, |
bcc55cba | 4308 | exception); |
1871c602 | 4309 | } |
064aea77 | 4310 | EXPORT_SYMBOL_GPL(kvm_read_guest_virt); |
1871c602 | 4311 | |
0f65dd70 AK |
4312 | static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt, |
4313 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 4314 | struct x86_exception *exception) |
1871c602 | 4315 | { |
0f65dd70 | 4316 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
bcc55cba | 4317 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception); |
1871c602 GN |
4318 | } |
4319 | ||
6a4d7550 | 4320 | int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt, |
0f65dd70 | 4321 | gva_t addr, void *val, |
2dafc6c2 | 4322 | unsigned int bytes, |
bcc55cba | 4323 | struct x86_exception *exception) |
77c2002e | 4324 | { |
0f65dd70 | 4325 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
77c2002e IE |
4326 | void *data = val; |
4327 | int r = X86EMUL_CONTINUE; | |
4328 | ||
4329 | while (bytes) { | |
14dfe855 JR |
4330 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, |
4331 | PFERR_WRITE_MASK, | |
ab9ae313 | 4332 | exception); |
77c2002e IE |
4333 | unsigned offset = addr & (PAGE_SIZE-1); |
4334 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
4335 | int ret; | |
4336 | ||
bcc55cba | 4337 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 4338 | return X86EMUL_PROPAGATE_FAULT; |
77c2002e IE |
4339 | ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite); |
4340 | if (ret < 0) { | |
c3cd7ffa | 4341 | r = X86EMUL_IO_NEEDED; |
77c2002e IE |
4342 | goto out; |
4343 | } | |
4344 | ||
4345 | bytes -= towrite; | |
4346 | data += towrite; | |
4347 | addr += towrite; | |
4348 | } | |
4349 | out: | |
4350 | return r; | |
4351 | } | |
6a4d7550 | 4352 | EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); |
77c2002e | 4353 | |
af7cc7d1 XG |
4354 | static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
4355 | gpa_t *gpa, struct x86_exception *exception, | |
4356 | bool write) | |
4357 | { | |
97d64b78 AK |
4358 | u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) |
4359 | | (write ? PFERR_WRITE_MASK : 0); | |
af7cc7d1 | 4360 | |
97d64b78 | 4361 | if (vcpu_match_mmio_gva(vcpu, gva) |
97ec8c06 FW |
4362 | && !permission_fault(vcpu, vcpu->arch.walk_mmu, |
4363 | vcpu->arch.access, access)) { | |
bebb106a XG |
4364 | *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | |
4365 | (gva & (PAGE_SIZE - 1)); | |
4f022648 | 4366 | trace_vcpu_match_mmio(gva, *gpa, write, false); |
bebb106a XG |
4367 | return 1; |
4368 | } | |
4369 | ||
af7cc7d1 XG |
4370 | *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
4371 | ||
4372 | if (*gpa == UNMAPPED_GVA) | |
4373 | return -1; | |
4374 | ||
4375 | /* For APIC access vmexit */ | |
4376 | if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
4377 | return 1; | |
4378 | ||
4f022648 XG |
4379 | if (vcpu_match_mmio_gpa(vcpu, *gpa)) { |
4380 | trace_vcpu_match_mmio(gva, *gpa, write, true); | |
bebb106a | 4381 | return 1; |
4f022648 | 4382 | } |
bebb106a | 4383 | |
af7cc7d1 XG |
4384 | return 0; |
4385 | } | |
4386 | ||
3200f405 | 4387 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
bcc55cba | 4388 | const void *val, int bytes) |
bbd9b64e CO |
4389 | { |
4390 | int ret; | |
4391 | ||
4392 | ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes); | |
9f811285 | 4393 | if (ret < 0) |
bbd9b64e | 4394 | return 0; |
f57f2ef5 | 4395 | kvm_mmu_pte_write(vcpu, gpa, val, bytes); |
bbd9b64e CO |
4396 | return 1; |
4397 | } | |
4398 | ||
77d197b2 XG |
4399 | struct read_write_emulator_ops { |
4400 | int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, | |
4401 | int bytes); | |
4402 | int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4403 | void *val, int bytes); | |
4404 | int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4405 | int bytes, void *val); | |
4406 | int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4407 | void *val, int bytes); | |
4408 | bool write; | |
4409 | }; | |
4410 | ||
4411 | static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) | |
4412 | { | |
4413 | if (vcpu->mmio_read_completed) { | |
77d197b2 | 4414 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
f78146b0 | 4415 | vcpu->mmio_fragments[0].gpa, *(u64 *)val); |
77d197b2 XG |
4416 | vcpu->mmio_read_completed = 0; |
4417 | return 1; | |
4418 | } | |
4419 | ||
4420 | return 0; | |
4421 | } | |
4422 | ||
4423 | static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4424 | void *val, int bytes) | |
4425 | { | |
4426 | return !kvm_read_guest(vcpu->kvm, gpa, val, bytes); | |
4427 | } | |
4428 | ||
4429 | static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4430 | void *val, int bytes) | |
4431 | { | |
4432 | return emulator_write_phys(vcpu, gpa, val, bytes); | |
4433 | } | |
4434 | ||
4435 | static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) | |
4436 | { | |
4437 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); | |
4438 | return vcpu_mmio_write(vcpu, gpa, bytes, val); | |
4439 | } | |
4440 | ||
4441 | static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4442 | void *val, int bytes) | |
4443 | { | |
4444 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); | |
4445 | return X86EMUL_IO_NEEDED; | |
4446 | } | |
4447 | ||
4448 | static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4449 | void *val, int bytes) | |
4450 | { | |
f78146b0 AK |
4451 | struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; |
4452 | ||
87da7e66 | 4453 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); |
77d197b2 XG |
4454 | return X86EMUL_CONTINUE; |
4455 | } | |
4456 | ||
0fbe9b0b | 4457 | static const struct read_write_emulator_ops read_emultor = { |
77d197b2 XG |
4458 | .read_write_prepare = read_prepare, |
4459 | .read_write_emulate = read_emulate, | |
4460 | .read_write_mmio = vcpu_mmio_read, | |
4461 | .read_write_exit_mmio = read_exit_mmio, | |
4462 | }; | |
4463 | ||
0fbe9b0b | 4464 | static const struct read_write_emulator_ops write_emultor = { |
77d197b2 XG |
4465 | .read_write_emulate = write_emulate, |
4466 | .read_write_mmio = write_mmio, | |
4467 | .read_write_exit_mmio = write_exit_mmio, | |
4468 | .write = true, | |
4469 | }; | |
4470 | ||
22388a3c XG |
4471 | static int emulator_read_write_onepage(unsigned long addr, void *val, |
4472 | unsigned int bytes, | |
4473 | struct x86_exception *exception, | |
4474 | struct kvm_vcpu *vcpu, | |
0fbe9b0b | 4475 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 4476 | { |
af7cc7d1 XG |
4477 | gpa_t gpa; |
4478 | int handled, ret; | |
22388a3c | 4479 | bool write = ops->write; |
f78146b0 | 4480 | struct kvm_mmio_fragment *frag; |
10589a46 | 4481 | |
22388a3c | 4482 | ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); |
bbd9b64e | 4483 | |
af7cc7d1 | 4484 | if (ret < 0) |
bbd9b64e | 4485 | return X86EMUL_PROPAGATE_FAULT; |
bbd9b64e CO |
4486 | |
4487 | /* For APIC access vmexit */ | |
af7cc7d1 | 4488 | if (ret) |
bbd9b64e CO |
4489 | goto mmio; |
4490 | ||
22388a3c | 4491 | if (ops->read_write_emulate(vcpu, gpa, val, bytes)) |
bbd9b64e CO |
4492 | return X86EMUL_CONTINUE; |
4493 | ||
4494 | mmio: | |
4495 | /* | |
4496 | * Is this MMIO handled locally? | |
4497 | */ | |
22388a3c | 4498 | handled = ops->read_write_mmio(vcpu, gpa, bytes, val); |
70252a10 | 4499 | if (handled == bytes) |
bbd9b64e | 4500 | return X86EMUL_CONTINUE; |
bbd9b64e | 4501 | |
70252a10 AK |
4502 | gpa += handled; |
4503 | bytes -= handled; | |
4504 | val += handled; | |
4505 | ||
87da7e66 XG |
4506 | WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); |
4507 | frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; | |
4508 | frag->gpa = gpa; | |
4509 | frag->data = val; | |
4510 | frag->len = bytes; | |
f78146b0 | 4511 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
4512 | } |
4513 | ||
52eb5a6d XL |
4514 | static int emulator_read_write(struct x86_emulate_ctxt *ctxt, |
4515 | unsigned long addr, | |
22388a3c XG |
4516 | void *val, unsigned int bytes, |
4517 | struct x86_exception *exception, | |
0fbe9b0b | 4518 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 4519 | { |
0f65dd70 | 4520 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
f78146b0 AK |
4521 | gpa_t gpa; |
4522 | int rc; | |
4523 | ||
4524 | if (ops->read_write_prepare && | |
4525 | ops->read_write_prepare(vcpu, val, bytes)) | |
4526 | return X86EMUL_CONTINUE; | |
4527 | ||
4528 | vcpu->mmio_nr_fragments = 0; | |
0f65dd70 | 4529 | |
bbd9b64e CO |
4530 | /* Crossing a page boundary? */ |
4531 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
f78146b0 | 4532 | int now; |
bbd9b64e CO |
4533 | |
4534 | now = -addr & ~PAGE_MASK; | |
22388a3c XG |
4535 | rc = emulator_read_write_onepage(addr, val, now, exception, |
4536 | vcpu, ops); | |
4537 | ||
bbd9b64e CO |
4538 | if (rc != X86EMUL_CONTINUE) |
4539 | return rc; | |
4540 | addr += now; | |
bac15531 NA |
4541 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
4542 | addr = (u32)addr; | |
bbd9b64e CO |
4543 | val += now; |
4544 | bytes -= now; | |
4545 | } | |
22388a3c | 4546 | |
f78146b0 AK |
4547 | rc = emulator_read_write_onepage(addr, val, bytes, exception, |
4548 | vcpu, ops); | |
4549 | if (rc != X86EMUL_CONTINUE) | |
4550 | return rc; | |
4551 | ||
4552 | if (!vcpu->mmio_nr_fragments) | |
4553 | return rc; | |
4554 | ||
4555 | gpa = vcpu->mmio_fragments[0].gpa; | |
4556 | ||
4557 | vcpu->mmio_needed = 1; | |
4558 | vcpu->mmio_cur_fragment = 0; | |
4559 | ||
87da7e66 | 4560 | vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); |
f78146b0 AK |
4561 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; |
4562 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
4563 | vcpu->run->mmio.phys_addr = gpa; | |
4564 | ||
4565 | return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); | |
22388a3c XG |
4566 | } |
4567 | ||
4568 | static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, | |
4569 | unsigned long addr, | |
4570 | void *val, | |
4571 | unsigned int bytes, | |
4572 | struct x86_exception *exception) | |
4573 | { | |
4574 | return emulator_read_write(ctxt, addr, val, bytes, | |
4575 | exception, &read_emultor); | |
4576 | } | |
4577 | ||
52eb5a6d | 4578 | static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, |
22388a3c XG |
4579 | unsigned long addr, |
4580 | const void *val, | |
4581 | unsigned int bytes, | |
4582 | struct x86_exception *exception) | |
4583 | { | |
4584 | return emulator_read_write(ctxt, addr, (void *)val, bytes, | |
4585 | exception, &write_emultor); | |
bbd9b64e | 4586 | } |
bbd9b64e | 4587 | |
daea3e73 AK |
4588 | #define CMPXCHG_TYPE(t, ptr, old, new) \ |
4589 | (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) | |
4590 | ||
4591 | #ifdef CONFIG_X86_64 | |
4592 | # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) | |
4593 | #else | |
4594 | # define CMPXCHG64(ptr, old, new) \ | |
9749a6c0 | 4595 | (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) |
daea3e73 AK |
4596 | #endif |
4597 | ||
0f65dd70 AK |
4598 | static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, |
4599 | unsigned long addr, | |
bbd9b64e CO |
4600 | const void *old, |
4601 | const void *new, | |
4602 | unsigned int bytes, | |
0f65dd70 | 4603 | struct x86_exception *exception) |
bbd9b64e | 4604 | { |
0f65dd70 | 4605 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
daea3e73 AK |
4606 | gpa_t gpa; |
4607 | struct page *page; | |
4608 | char *kaddr; | |
4609 | bool exchanged; | |
2bacc55c | 4610 | |
daea3e73 AK |
4611 | /* guests cmpxchg8b have to be emulated atomically */ |
4612 | if (bytes > 8 || (bytes & (bytes - 1))) | |
4613 | goto emul_write; | |
10589a46 | 4614 | |
daea3e73 | 4615 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); |
2bacc55c | 4616 | |
daea3e73 AK |
4617 | if (gpa == UNMAPPED_GVA || |
4618 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
4619 | goto emul_write; | |
2bacc55c | 4620 | |
daea3e73 AK |
4621 | if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) |
4622 | goto emul_write; | |
72dc67a6 | 4623 | |
daea3e73 | 4624 | page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
32cad84f | 4625 | if (is_error_page(page)) |
c19b8bd6 | 4626 | goto emul_write; |
72dc67a6 | 4627 | |
8fd75e12 | 4628 | kaddr = kmap_atomic(page); |
daea3e73 AK |
4629 | kaddr += offset_in_page(gpa); |
4630 | switch (bytes) { | |
4631 | case 1: | |
4632 | exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); | |
4633 | break; | |
4634 | case 2: | |
4635 | exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); | |
4636 | break; | |
4637 | case 4: | |
4638 | exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); | |
4639 | break; | |
4640 | case 8: | |
4641 | exchanged = CMPXCHG64(kaddr, old, new); | |
4642 | break; | |
4643 | default: | |
4644 | BUG(); | |
2bacc55c | 4645 | } |
8fd75e12 | 4646 | kunmap_atomic(kaddr); |
daea3e73 AK |
4647 | kvm_release_page_dirty(page); |
4648 | ||
4649 | if (!exchanged) | |
4650 | return X86EMUL_CMPXCHG_FAILED; | |
4651 | ||
d3714010 | 4652 | mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT); |
f57f2ef5 | 4653 | kvm_mmu_pte_write(vcpu, gpa, new, bytes); |
8f6abd06 GN |
4654 | |
4655 | return X86EMUL_CONTINUE; | |
4a5f48f6 | 4656 | |
3200f405 | 4657 | emul_write: |
daea3e73 | 4658 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); |
2bacc55c | 4659 | |
0f65dd70 | 4660 | return emulator_write_emulated(ctxt, addr, new, bytes, exception); |
bbd9b64e CO |
4661 | } |
4662 | ||
cf8f70bf GN |
4663 | static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) |
4664 | { | |
4665 | /* TODO: String I/O for in kernel device */ | |
4666 | int r; | |
4667 | ||
4668 | if (vcpu->arch.pio.in) | |
e32edf4f | 4669 | r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, |
cf8f70bf GN |
4670 | vcpu->arch.pio.size, pd); |
4671 | else | |
e32edf4f | 4672 | r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, |
cf8f70bf GN |
4673 | vcpu->arch.pio.port, vcpu->arch.pio.size, |
4674 | pd); | |
4675 | return r; | |
4676 | } | |
4677 | ||
6f6fbe98 XG |
4678 | static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, |
4679 | unsigned short port, void *val, | |
4680 | unsigned int count, bool in) | |
cf8f70bf | 4681 | { |
cf8f70bf | 4682 | vcpu->arch.pio.port = port; |
6f6fbe98 | 4683 | vcpu->arch.pio.in = in; |
7972995b | 4684 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
4685 | vcpu->arch.pio.size = size; |
4686 | ||
4687 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
7972995b | 4688 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
4689 | return 1; |
4690 | } | |
4691 | ||
4692 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
6f6fbe98 | 4693 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; |
cf8f70bf GN |
4694 | vcpu->run->io.size = size; |
4695 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
4696 | vcpu->run->io.count = count; | |
4697 | vcpu->run->io.port = port; | |
4698 | ||
4699 | return 0; | |
4700 | } | |
4701 | ||
6f6fbe98 XG |
4702 | static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
4703 | int size, unsigned short port, void *val, | |
4704 | unsigned int count) | |
cf8f70bf | 4705 | { |
ca1d4a9e | 4706 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
6f6fbe98 | 4707 | int ret; |
ca1d4a9e | 4708 | |
6f6fbe98 XG |
4709 | if (vcpu->arch.pio.count) |
4710 | goto data_avail; | |
cf8f70bf | 4711 | |
6f6fbe98 XG |
4712 | ret = emulator_pio_in_out(vcpu, size, port, val, count, true); |
4713 | if (ret) { | |
4714 | data_avail: | |
4715 | memcpy(val, vcpu->arch.pio_data, size * count); | |
1171903d | 4716 | trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); |
7972995b | 4717 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
4718 | return 1; |
4719 | } | |
4720 | ||
cf8f70bf GN |
4721 | return 0; |
4722 | } | |
4723 | ||
6f6fbe98 XG |
4724 | static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, |
4725 | int size, unsigned short port, | |
4726 | const void *val, unsigned int count) | |
4727 | { | |
4728 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
4729 | ||
4730 | memcpy(vcpu->arch.pio_data, val, size * count); | |
1171903d | 4731 | trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); |
6f6fbe98 XG |
4732 | return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); |
4733 | } | |
4734 | ||
bbd9b64e CO |
4735 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) |
4736 | { | |
4737 | return kvm_x86_ops->get_segment_base(vcpu, seg); | |
4738 | } | |
4739 | ||
3cb16fe7 | 4740 | static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) |
bbd9b64e | 4741 | { |
3cb16fe7 | 4742 | kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); |
bbd9b64e CO |
4743 | } |
4744 | ||
5cb56059 | 4745 | int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) |
f5f48ee1 SY |
4746 | { |
4747 | if (!need_emulate_wbinvd(vcpu)) | |
4748 | return X86EMUL_CONTINUE; | |
4749 | ||
4750 | if (kvm_x86_ops->has_wbinvd_exit()) { | |
2eec7343 JK |
4751 | int cpu = get_cpu(); |
4752 | ||
4753 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
f5f48ee1 SY |
4754 | smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, |
4755 | wbinvd_ipi, NULL, 1); | |
2eec7343 | 4756 | put_cpu(); |
f5f48ee1 | 4757 | cpumask_clear(vcpu->arch.wbinvd_dirty_mask); |
2eec7343 JK |
4758 | } else |
4759 | wbinvd(); | |
f5f48ee1 SY |
4760 | return X86EMUL_CONTINUE; |
4761 | } | |
5cb56059 JS |
4762 | |
4763 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
4764 | { | |
4765 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
4766 | return kvm_emulate_wbinvd_noskip(vcpu); | |
4767 | } | |
f5f48ee1 SY |
4768 | EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); |
4769 | ||
5cb56059 JS |
4770 | |
4771 | ||
bcaf5cc5 AK |
4772 | static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) |
4773 | { | |
5cb56059 | 4774 | kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); |
bcaf5cc5 AK |
4775 | } |
4776 | ||
52eb5a6d XL |
4777 | static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, |
4778 | unsigned long *dest) | |
bbd9b64e | 4779 | { |
16f8a6f9 | 4780 | return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); |
bbd9b64e CO |
4781 | } |
4782 | ||
52eb5a6d XL |
4783 | static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, |
4784 | unsigned long value) | |
bbd9b64e | 4785 | { |
338dbc97 | 4786 | |
717746e3 | 4787 | return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); |
bbd9b64e CO |
4788 | } |
4789 | ||
52a46617 | 4790 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) |
5fdbf976 | 4791 | { |
52a46617 | 4792 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; |
5fdbf976 MT |
4793 | } |
4794 | ||
717746e3 | 4795 | static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) |
bbd9b64e | 4796 | { |
717746e3 | 4797 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
52a46617 GN |
4798 | unsigned long value; |
4799 | ||
4800 | switch (cr) { | |
4801 | case 0: | |
4802 | value = kvm_read_cr0(vcpu); | |
4803 | break; | |
4804 | case 2: | |
4805 | value = vcpu->arch.cr2; | |
4806 | break; | |
4807 | case 3: | |
9f8fe504 | 4808 | value = kvm_read_cr3(vcpu); |
52a46617 GN |
4809 | break; |
4810 | case 4: | |
4811 | value = kvm_read_cr4(vcpu); | |
4812 | break; | |
4813 | case 8: | |
4814 | value = kvm_get_cr8(vcpu); | |
4815 | break; | |
4816 | default: | |
a737f256 | 4817 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
52a46617 GN |
4818 | return 0; |
4819 | } | |
4820 | ||
4821 | return value; | |
4822 | } | |
4823 | ||
717746e3 | 4824 | static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) |
52a46617 | 4825 | { |
717746e3 | 4826 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
0f12244f GN |
4827 | int res = 0; |
4828 | ||
52a46617 GN |
4829 | switch (cr) { |
4830 | case 0: | |
49a9b07e | 4831 | res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
52a46617 GN |
4832 | break; |
4833 | case 2: | |
4834 | vcpu->arch.cr2 = val; | |
4835 | break; | |
4836 | case 3: | |
2390218b | 4837 | res = kvm_set_cr3(vcpu, val); |
52a46617 GN |
4838 | break; |
4839 | case 4: | |
a83b29c6 | 4840 | res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
52a46617 GN |
4841 | break; |
4842 | case 8: | |
eea1cff9 | 4843 | res = kvm_set_cr8(vcpu, val); |
52a46617 GN |
4844 | break; |
4845 | default: | |
a737f256 | 4846 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
0f12244f | 4847 | res = -1; |
52a46617 | 4848 | } |
0f12244f GN |
4849 | |
4850 | return res; | |
52a46617 GN |
4851 | } |
4852 | ||
717746e3 | 4853 | static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) |
9c537244 | 4854 | { |
717746e3 | 4855 | return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); |
9c537244 GN |
4856 | } |
4857 | ||
4bff1e86 | 4858 | static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
2dafc6c2 | 4859 | { |
4bff1e86 | 4860 | kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); |
2dafc6c2 GN |
4861 | } |
4862 | ||
4bff1e86 | 4863 | static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
160ce1f1 | 4864 | { |
4bff1e86 | 4865 | kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); |
160ce1f1 MG |
4866 | } |
4867 | ||
1ac9d0cf AK |
4868 | static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
4869 | { | |
4870 | kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); | |
4871 | } | |
4872 | ||
4873 | static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) | |
4874 | { | |
4875 | kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); | |
4876 | } | |
4877 | ||
4bff1e86 AK |
4878 | static unsigned long emulator_get_cached_segment_base( |
4879 | struct x86_emulate_ctxt *ctxt, int seg) | |
5951c442 | 4880 | { |
4bff1e86 | 4881 | return get_segment_base(emul_to_vcpu(ctxt), seg); |
5951c442 GN |
4882 | } |
4883 | ||
1aa36616 AK |
4884 | static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, |
4885 | struct desc_struct *desc, u32 *base3, | |
4886 | int seg) | |
2dafc6c2 GN |
4887 | { |
4888 | struct kvm_segment var; | |
4889 | ||
4bff1e86 | 4890 | kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); |
1aa36616 | 4891 | *selector = var.selector; |
2dafc6c2 | 4892 | |
378a8b09 GN |
4893 | if (var.unusable) { |
4894 | memset(desc, 0, sizeof(*desc)); | |
2dafc6c2 | 4895 | return false; |
378a8b09 | 4896 | } |
2dafc6c2 GN |
4897 | |
4898 | if (var.g) | |
4899 | var.limit >>= 12; | |
4900 | set_desc_limit(desc, var.limit); | |
4901 | set_desc_base(desc, (unsigned long)var.base); | |
5601d05b GN |
4902 | #ifdef CONFIG_X86_64 |
4903 | if (base3) | |
4904 | *base3 = var.base >> 32; | |
4905 | #endif | |
2dafc6c2 GN |
4906 | desc->type = var.type; |
4907 | desc->s = var.s; | |
4908 | desc->dpl = var.dpl; | |
4909 | desc->p = var.present; | |
4910 | desc->avl = var.avl; | |
4911 | desc->l = var.l; | |
4912 | desc->d = var.db; | |
4913 | desc->g = var.g; | |
4914 | ||
4915 | return true; | |
4916 | } | |
4917 | ||
1aa36616 AK |
4918 | static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, |
4919 | struct desc_struct *desc, u32 base3, | |
4920 | int seg) | |
2dafc6c2 | 4921 | { |
4bff1e86 | 4922 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
2dafc6c2 GN |
4923 | struct kvm_segment var; |
4924 | ||
1aa36616 | 4925 | var.selector = selector; |
2dafc6c2 | 4926 | var.base = get_desc_base(desc); |
5601d05b GN |
4927 | #ifdef CONFIG_X86_64 |
4928 | var.base |= ((u64)base3) << 32; | |
4929 | #endif | |
2dafc6c2 GN |
4930 | var.limit = get_desc_limit(desc); |
4931 | if (desc->g) | |
4932 | var.limit = (var.limit << 12) | 0xfff; | |
4933 | var.type = desc->type; | |
2dafc6c2 GN |
4934 | var.dpl = desc->dpl; |
4935 | var.db = desc->d; | |
4936 | var.s = desc->s; | |
4937 | var.l = desc->l; | |
4938 | var.g = desc->g; | |
4939 | var.avl = desc->avl; | |
4940 | var.present = desc->p; | |
4941 | var.unusable = !var.present; | |
4942 | var.padding = 0; | |
4943 | ||
4944 | kvm_set_segment(vcpu, &var, seg); | |
4945 | return; | |
4946 | } | |
4947 | ||
717746e3 AK |
4948 | static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, |
4949 | u32 msr_index, u64 *pdata) | |
4950 | { | |
4951 | return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata); | |
4952 | } | |
4953 | ||
4954 | static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, | |
4955 | u32 msr_index, u64 data) | |
4956 | { | |
8fe8ab46 WA |
4957 | struct msr_data msr; |
4958 | ||
4959 | msr.data = data; | |
4960 | msr.index = msr_index; | |
4961 | msr.host_initiated = false; | |
4962 | return kvm_set_msr(emul_to_vcpu(ctxt), &msr); | |
717746e3 AK |
4963 | } |
4964 | ||
67f4d428 NA |
4965 | static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, |
4966 | u32 pmc) | |
4967 | { | |
4968 | return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc); | |
4969 | } | |
4970 | ||
222d21aa AK |
4971 | static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, |
4972 | u32 pmc, u64 *pdata) | |
4973 | { | |
4974 | return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata); | |
4975 | } | |
4976 | ||
6c3287f7 AK |
4977 | static void emulator_halt(struct x86_emulate_ctxt *ctxt) |
4978 | { | |
4979 | emul_to_vcpu(ctxt)->arch.halt_request = 1; | |
4980 | } | |
4981 | ||
5037f6f3 AK |
4982 | static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt) |
4983 | { | |
4984 | preempt_disable(); | |
5197b808 | 4985 | kvm_load_guest_fpu(emul_to_vcpu(ctxt)); |
5037f6f3 AK |
4986 | /* |
4987 | * CR0.TS may reference the host fpu state, not the guest fpu state, | |
4988 | * so it may be clear at this point. | |
4989 | */ | |
4990 | clts(); | |
4991 | } | |
4992 | ||
4993 | static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt) | |
4994 | { | |
4995 | preempt_enable(); | |
4996 | } | |
4997 | ||
2953538e | 4998 | static int emulator_intercept(struct x86_emulate_ctxt *ctxt, |
8a76d7f2 | 4999 | struct x86_instruction_info *info, |
c4f035c6 AK |
5000 | enum x86_intercept_stage stage) |
5001 | { | |
2953538e | 5002 | return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); |
c4f035c6 AK |
5003 | } |
5004 | ||
0017f93a | 5005 | static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, |
bdb42f5a SB |
5006 | u32 *eax, u32 *ebx, u32 *ecx, u32 *edx) |
5007 | { | |
0017f93a | 5008 | kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx); |
bdb42f5a SB |
5009 | } |
5010 | ||
dd856efa AK |
5011 | static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) |
5012 | { | |
5013 | return kvm_register_read(emul_to_vcpu(ctxt), reg); | |
5014 | } | |
5015 | ||
5016 | static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) | |
5017 | { | |
5018 | kvm_register_write(emul_to_vcpu(ctxt), reg, val); | |
5019 | } | |
5020 | ||
801806d9 NA |
5021 | static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) |
5022 | { | |
5023 | kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked); | |
5024 | } | |
5025 | ||
0225fb50 | 5026 | static const struct x86_emulate_ops emulate_ops = { |
dd856efa AK |
5027 | .read_gpr = emulator_read_gpr, |
5028 | .write_gpr = emulator_write_gpr, | |
1871c602 | 5029 | .read_std = kvm_read_guest_virt_system, |
2dafc6c2 | 5030 | .write_std = kvm_write_guest_virt_system, |
1871c602 | 5031 | .fetch = kvm_fetch_guest_virt, |
bbd9b64e CO |
5032 | .read_emulated = emulator_read_emulated, |
5033 | .write_emulated = emulator_write_emulated, | |
5034 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
3cb16fe7 | 5035 | .invlpg = emulator_invlpg, |
cf8f70bf GN |
5036 | .pio_in_emulated = emulator_pio_in_emulated, |
5037 | .pio_out_emulated = emulator_pio_out_emulated, | |
1aa36616 AK |
5038 | .get_segment = emulator_get_segment, |
5039 | .set_segment = emulator_set_segment, | |
5951c442 | 5040 | .get_cached_segment_base = emulator_get_cached_segment_base, |
2dafc6c2 | 5041 | .get_gdt = emulator_get_gdt, |
160ce1f1 | 5042 | .get_idt = emulator_get_idt, |
1ac9d0cf AK |
5043 | .set_gdt = emulator_set_gdt, |
5044 | .set_idt = emulator_set_idt, | |
52a46617 GN |
5045 | .get_cr = emulator_get_cr, |
5046 | .set_cr = emulator_set_cr, | |
9c537244 | 5047 | .cpl = emulator_get_cpl, |
35aa5375 GN |
5048 | .get_dr = emulator_get_dr, |
5049 | .set_dr = emulator_set_dr, | |
717746e3 AK |
5050 | .set_msr = emulator_set_msr, |
5051 | .get_msr = emulator_get_msr, | |
67f4d428 | 5052 | .check_pmc = emulator_check_pmc, |
222d21aa | 5053 | .read_pmc = emulator_read_pmc, |
6c3287f7 | 5054 | .halt = emulator_halt, |
bcaf5cc5 | 5055 | .wbinvd = emulator_wbinvd, |
d6aa1000 | 5056 | .fix_hypercall = emulator_fix_hypercall, |
5037f6f3 AK |
5057 | .get_fpu = emulator_get_fpu, |
5058 | .put_fpu = emulator_put_fpu, | |
c4f035c6 | 5059 | .intercept = emulator_intercept, |
bdb42f5a | 5060 | .get_cpuid = emulator_get_cpuid, |
801806d9 | 5061 | .set_nmi_mask = emulator_set_nmi_mask, |
bbd9b64e CO |
5062 | }; |
5063 | ||
95cb2295 GN |
5064 | static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) |
5065 | { | |
37ccdcbe | 5066 | u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); |
95cb2295 GN |
5067 | /* |
5068 | * an sti; sti; sequence only disable interrupts for the first | |
5069 | * instruction. So, if the last instruction, be it emulated or | |
5070 | * not, left the system with the INT_STI flag enabled, it | |
5071 | * means that the last instruction is an sti. We should not | |
5072 | * leave the flag on in this case. The same goes for mov ss | |
5073 | */ | |
37ccdcbe PB |
5074 | if (int_shadow & mask) |
5075 | mask = 0; | |
6addfc42 | 5076 | if (unlikely(int_shadow || mask)) { |
95cb2295 | 5077 | kvm_x86_ops->set_interrupt_shadow(vcpu, mask); |
6addfc42 PB |
5078 | if (!mask) |
5079 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
5080 | } | |
95cb2295 GN |
5081 | } |
5082 | ||
ef54bcfe | 5083 | static bool inject_emulated_exception(struct kvm_vcpu *vcpu) |
54b8486f GN |
5084 | { |
5085 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; | |
da9cb575 | 5086 | if (ctxt->exception.vector == PF_VECTOR) |
ef54bcfe PB |
5087 | return kvm_propagate_fault(vcpu, &ctxt->exception); |
5088 | ||
5089 | if (ctxt->exception.error_code_valid) | |
da9cb575 AK |
5090 | kvm_queue_exception_e(vcpu, ctxt->exception.vector, |
5091 | ctxt->exception.error_code); | |
54b8486f | 5092 | else |
da9cb575 | 5093 | kvm_queue_exception(vcpu, ctxt->exception.vector); |
ef54bcfe | 5094 | return false; |
54b8486f GN |
5095 | } |
5096 | ||
8ec4722d MG |
5097 | static void init_emulate_ctxt(struct kvm_vcpu *vcpu) |
5098 | { | |
adf52235 | 5099 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
8ec4722d MG |
5100 | int cs_db, cs_l; |
5101 | ||
8ec4722d MG |
5102 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
5103 | ||
adf52235 TY |
5104 | ctxt->eflags = kvm_get_rflags(vcpu); |
5105 | ctxt->eip = kvm_rip_read(vcpu); | |
5106 | ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : | |
5107 | (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : | |
42bf549f | 5108 | (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : |
adf52235 TY |
5109 | cs_db ? X86EMUL_MODE_PROT32 : |
5110 | X86EMUL_MODE_PROT16; | |
5111 | ctxt->guest_mode = is_guest_mode(vcpu); | |
5112 | ||
dd856efa | 5113 | init_decode_cache(ctxt); |
7ae441ea | 5114 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; |
8ec4722d MG |
5115 | } |
5116 | ||
71f9833b | 5117 | int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) |
63995653 | 5118 | { |
9d74191a | 5119 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
63995653 MG |
5120 | int ret; |
5121 | ||
5122 | init_emulate_ctxt(vcpu); | |
5123 | ||
9dac77fa AK |
5124 | ctxt->op_bytes = 2; |
5125 | ctxt->ad_bytes = 2; | |
5126 | ctxt->_eip = ctxt->eip + inc_eip; | |
9d74191a | 5127 | ret = emulate_int_real(ctxt, irq); |
63995653 MG |
5128 | |
5129 | if (ret != X86EMUL_CONTINUE) | |
5130 | return EMULATE_FAIL; | |
5131 | ||
9dac77fa | 5132 | ctxt->eip = ctxt->_eip; |
9d74191a TY |
5133 | kvm_rip_write(vcpu, ctxt->eip); |
5134 | kvm_set_rflags(vcpu, ctxt->eflags); | |
63995653 MG |
5135 | |
5136 | if (irq == NMI_VECTOR) | |
7460fb4a | 5137 | vcpu->arch.nmi_pending = 0; |
63995653 MG |
5138 | else |
5139 | vcpu->arch.interrupt.pending = false; | |
5140 | ||
5141 | return EMULATE_DONE; | |
5142 | } | |
5143 | EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); | |
5144 | ||
6d77dbfc GN |
5145 | static int handle_emulation_failure(struct kvm_vcpu *vcpu) |
5146 | { | |
fc3a9157 JR |
5147 | int r = EMULATE_DONE; |
5148 | ||
6d77dbfc GN |
5149 | ++vcpu->stat.insn_emulation_fail; |
5150 | trace_kvm_emulate_insn_failed(vcpu); | |
a2b9e6c1 | 5151 | if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) { |
fc3a9157 JR |
5152 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
5153 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
5154 | vcpu->run->internal.ndata = 0; | |
5155 | r = EMULATE_FAIL; | |
5156 | } | |
6d77dbfc | 5157 | kvm_queue_exception(vcpu, UD_VECTOR); |
fc3a9157 JR |
5158 | |
5159 | return r; | |
6d77dbfc GN |
5160 | } |
5161 | ||
93c05d3e | 5162 | static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, |
991eebf9 GN |
5163 | bool write_fault_to_shadow_pgtable, |
5164 | int emulation_type) | |
a6f177ef | 5165 | { |
95b3cf69 | 5166 | gpa_t gpa = cr2; |
8e3d9d06 | 5167 | pfn_t pfn; |
a6f177ef | 5168 | |
991eebf9 GN |
5169 | if (emulation_type & EMULTYPE_NO_REEXECUTE) |
5170 | return false; | |
5171 | ||
95b3cf69 XG |
5172 | if (!vcpu->arch.mmu.direct_map) { |
5173 | /* | |
5174 | * Write permission should be allowed since only | |
5175 | * write access need to be emulated. | |
5176 | */ | |
5177 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); | |
a6f177ef | 5178 | |
95b3cf69 XG |
5179 | /* |
5180 | * If the mapping is invalid in guest, let cpu retry | |
5181 | * it to generate fault. | |
5182 | */ | |
5183 | if (gpa == UNMAPPED_GVA) | |
5184 | return true; | |
5185 | } | |
a6f177ef | 5186 | |
8e3d9d06 XG |
5187 | /* |
5188 | * Do not retry the unhandleable instruction if it faults on the | |
5189 | * readonly host memory, otherwise it will goto a infinite loop: | |
5190 | * retry instruction -> write #PF -> emulation fail -> retry | |
5191 | * instruction -> ... | |
5192 | */ | |
5193 | pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); | |
95b3cf69 XG |
5194 | |
5195 | /* | |
5196 | * If the instruction failed on the error pfn, it can not be fixed, | |
5197 | * report the error to userspace. | |
5198 | */ | |
5199 | if (is_error_noslot_pfn(pfn)) | |
5200 | return false; | |
5201 | ||
5202 | kvm_release_pfn_clean(pfn); | |
5203 | ||
5204 | /* The instructions are well-emulated on direct mmu. */ | |
5205 | if (vcpu->arch.mmu.direct_map) { | |
5206 | unsigned int indirect_shadow_pages; | |
5207 | ||
5208 | spin_lock(&vcpu->kvm->mmu_lock); | |
5209 | indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; | |
5210 | spin_unlock(&vcpu->kvm->mmu_lock); | |
5211 | ||
5212 | if (indirect_shadow_pages) | |
5213 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
5214 | ||
a6f177ef | 5215 | return true; |
8e3d9d06 | 5216 | } |
a6f177ef | 5217 | |
95b3cf69 XG |
5218 | /* |
5219 | * if emulation was due to access to shadowed page table | |
5220 | * and it failed try to unshadow page and re-enter the | |
5221 | * guest to let CPU execute the instruction. | |
5222 | */ | |
5223 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
93c05d3e XG |
5224 | |
5225 | /* | |
5226 | * If the access faults on its page table, it can not | |
5227 | * be fixed by unprotecting shadow page and it should | |
5228 | * be reported to userspace. | |
5229 | */ | |
5230 | return !write_fault_to_shadow_pgtable; | |
a6f177ef GN |
5231 | } |
5232 | ||
1cb3f3ae XG |
5233 | static bool retry_instruction(struct x86_emulate_ctxt *ctxt, |
5234 | unsigned long cr2, int emulation_type) | |
5235 | { | |
5236 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
5237 | unsigned long last_retry_eip, last_retry_addr, gpa = cr2; | |
5238 | ||
5239 | last_retry_eip = vcpu->arch.last_retry_eip; | |
5240 | last_retry_addr = vcpu->arch.last_retry_addr; | |
5241 | ||
5242 | /* | |
5243 | * If the emulation is caused by #PF and it is non-page_table | |
5244 | * writing instruction, it means the VM-EXIT is caused by shadow | |
5245 | * page protected, we can zap the shadow page and retry this | |
5246 | * instruction directly. | |
5247 | * | |
5248 | * Note: if the guest uses a non-page-table modifying instruction | |
5249 | * on the PDE that points to the instruction, then we will unmap | |
5250 | * the instruction and go to an infinite loop. So, we cache the | |
5251 | * last retried eip and the last fault address, if we meet the eip | |
5252 | * and the address again, we can break out of the potential infinite | |
5253 | * loop. | |
5254 | */ | |
5255 | vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; | |
5256 | ||
5257 | if (!(emulation_type & EMULTYPE_RETRY)) | |
5258 | return false; | |
5259 | ||
5260 | if (x86_page_table_writing_insn(ctxt)) | |
5261 | return false; | |
5262 | ||
5263 | if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) | |
5264 | return false; | |
5265 | ||
5266 | vcpu->arch.last_retry_eip = ctxt->eip; | |
5267 | vcpu->arch.last_retry_addr = cr2; | |
5268 | ||
5269 | if (!vcpu->arch.mmu.direct_map) | |
5270 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); | |
5271 | ||
22368028 | 5272 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); |
1cb3f3ae XG |
5273 | |
5274 | return true; | |
5275 | } | |
5276 | ||
716d51ab GN |
5277 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu); |
5278 | static int complete_emulated_pio(struct kvm_vcpu *vcpu); | |
5279 | ||
4a1e10d5 PB |
5280 | static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, |
5281 | unsigned long *db) | |
5282 | { | |
5283 | u32 dr6 = 0; | |
5284 | int i; | |
5285 | u32 enable, rwlen; | |
5286 | ||
5287 | enable = dr7; | |
5288 | rwlen = dr7 >> 16; | |
5289 | for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) | |
5290 | if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) | |
5291 | dr6 |= (1 << i); | |
5292 | return dr6; | |
5293 | } | |
5294 | ||
6addfc42 | 5295 | static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r) |
663f4c61 PB |
5296 | { |
5297 | struct kvm_run *kvm_run = vcpu->run; | |
5298 | ||
5299 | /* | |
6addfc42 PB |
5300 | * rflags is the old, "raw" value of the flags. The new value has |
5301 | * not been saved yet. | |
663f4c61 PB |
5302 | * |
5303 | * This is correct even for TF set by the guest, because "the | |
5304 | * processor will not generate this exception after the instruction | |
5305 | * that sets the TF flag". | |
5306 | */ | |
663f4c61 PB |
5307 | if (unlikely(rflags & X86_EFLAGS_TF)) { |
5308 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { | |
6f43ed01 NA |
5309 | kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | |
5310 | DR6_RTM; | |
663f4c61 PB |
5311 | kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; |
5312 | kvm_run->debug.arch.exception = DB_VECTOR; | |
5313 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
5314 | *r = EMULATE_USER_EXIT; | |
5315 | } else { | |
5316 | vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF; | |
5317 | /* | |
5318 | * "Certain debug exceptions may clear bit 0-3. The | |
5319 | * remaining contents of the DR6 register are never | |
5320 | * cleared by the processor". | |
5321 | */ | |
5322 | vcpu->arch.dr6 &= ~15; | |
6f43ed01 | 5323 | vcpu->arch.dr6 |= DR6_BS | DR6_RTM; |
663f4c61 PB |
5324 | kvm_queue_exception(vcpu, DB_VECTOR); |
5325 | } | |
5326 | } | |
5327 | } | |
5328 | ||
4a1e10d5 PB |
5329 | static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) |
5330 | { | |
4a1e10d5 PB |
5331 | if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && |
5332 | (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { | |
82b32774 NA |
5333 | struct kvm_run *kvm_run = vcpu->run; |
5334 | unsigned long eip = kvm_get_linear_rip(vcpu); | |
5335 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
5336 | vcpu->arch.guest_debug_dr7, |
5337 | vcpu->arch.eff_db); | |
5338 | ||
5339 | if (dr6 != 0) { | |
6f43ed01 | 5340 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; |
82b32774 | 5341 | kvm_run->debug.arch.pc = eip; |
4a1e10d5 PB |
5342 | kvm_run->debug.arch.exception = DB_VECTOR; |
5343 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
5344 | *r = EMULATE_USER_EXIT; | |
5345 | return true; | |
5346 | } | |
5347 | } | |
5348 | ||
4161a569 NA |
5349 | if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && |
5350 | !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { | |
82b32774 NA |
5351 | unsigned long eip = kvm_get_linear_rip(vcpu); |
5352 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
5353 | vcpu->arch.dr7, |
5354 | vcpu->arch.db); | |
5355 | ||
5356 | if (dr6 != 0) { | |
5357 | vcpu->arch.dr6 &= ~15; | |
6f43ed01 | 5358 | vcpu->arch.dr6 |= dr6 | DR6_RTM; |
4a1e10d5 PB |
5359 | kvm_queue_exception(vcpu, DB_VECTOR); |
5360 | *r = EMULATE_DONE; | |
5361 | return true; | |
5362 | } | |
5363 | } | |
5364 | ||
5365 | return false; | |
5366 | } | |
5367 | ||
51d8b661 AP |
5368 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, |
5369 | unsigned long cr2, | |
dc25e89e AP |
5370 | int emulation_type, |
5371 | void *insn, | |
5372 | int insn_len) | |
bbd9b64e | 5373 | { |
95cb2295 | 5374 | int r; |
9d74191a | 5375 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
7ae441ea | 5376 | bool writeback = true; |
93c05d3e | 5377 | bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; |
bbd9b64e | 5378 | |
93c05d3e XG |
5379 | /* |
5380 | * Clear write_fault_to_shadow_pgtable here to ensure it is | |
5381 | * never reused. | |
5382 | */ | |
5383 | vcpu->arch.write_fault_to_shadow_pgtable = false; | |
26eef70c | 5384 | kvm_clear_exception_queue(vcpu); |
8d7d8102 | 5385 | |
571008da | 5386 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
8ec4722d | 5387 | init_emulate_ctxt(vcpu); |
4a1e10d5 PB |
5388 | |
5389 | /* | |
5390 | * We will reenter on the same instruction since | |
5391 | * we do not set complete_userspace_io. This does not | |
5392 | * handle watchpoints yet, those would be handled in | |
5393 | * the emulate_ops. | |
5394 | */ | |
5395 | if (kvm_vcpu_check_breakpoint(vcpu, &r)) | |
5396 | return r; | |
5397 | ||
9d74191a TY |
5398 | ctxt->interruptibility = 0; |
5399 | ctxt->have_exception = false; | |
e0ad0b47 | 5400 | ctxt->exception.vector = -1; |
9d74191a | 5401 | ctxt->perm_ok = false; |
bbd9b64e | 5402 | |
b51e974f | 5403 | ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; |
4005996e | 5404 | |
9d74191a | 5405 | r = x86_decode_insn(ctxt, insn, insn_len); |
bbd9b64e | 5406 | |
e46479f8 | 5407 | trace_kvm_emulate_insn_start(vcpu); |
f2b5756b | 5408 | ++vcpu->stat.insn_emulation; |
1d2887e2 | 5409 | if (r != EMULATION_OK) { |
4005996e AK |
5410 | if (emulation_type & EMULTYPE_TRAP_UD) |
5411 | return EMULATE_FAIL; | |
991eebf9 GN |
5412 | if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, |
5413 | emulation_type)) | |
bbd9b64e | 5414 | return EMULATE_DONE; |
6d77dbfc GN |
5415 | if (emulation_type & EMULTYPE_SKIP) |
5416 | return EMULATE_FAIL; | |
5417 | return handle_emulation_failure(vcpu); | |
bbd9b64e CO |
5418 | } |
5419 | } | |
5420 | ||
ba8afb6b | 5421 | if (emulation_type & EMULTYPE_SKIP) { |
9dac77fa | 5422 | kvm_rip_write(vcpu, ctxt->_eip); |
bb663c7a NA |
5423 | if (ctxt->eflags & X86_EFLAGS_RF) |
5424 | kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); | |
ba8afb6b GN |
5425 | return EMULATE_DONE; |
5426 | } | |
5427 | ||
1cb3f3ae XG |
5428 | if (retry_instruction(ctxt, cr2, emulation_type)) |
5429 | return EMULATE_DONE; | |
5430 | ||
7ae441ea | 5431 | /* this is needed for vmware backdoor interface to work since it |
4d2179e1 | 5432 | changes registers values during IO operation */ |
7ae441ea GN |
5433 | if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { |
5434 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; | |
dd856efa | 5435 | emulator_invalidate_register_cache(ctxt); |
7ae441ea | 5436 | } |
4d2179e1 | 5437 | |
5cd21917 | 5438 | restart: |
9d74191a | 5439 | r = x86_emulate_insn(ctxt); |
bbd9b64e | 5440 | |
775fde86 JR |
5441 | if (r == EMULATION_INTERCEPTED) |
5442 | return EMULATE_DONE; | |
5443 | ||
d2ddd1c4 | 5444 | if (r == EMULATION_FAILED) { |
991eebf9 GN |
5445 | if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, |
5446 | emulation_type)) | |
c3cd7ffa GN |
5447 | return EMULATE_DONE; |
5448 | ||
6d77dbfc | 5449 | return handle_emulation_failure(vcpu); |
bbd9b64e CO |
5450 | } |
5451 | ||
9d74191a | 5452 | if (ctxt->have_exception) { |
d2ddd1c4 | 5453 | r = EMULATE_DONE; |
ef54bcfe PB |
5454 | if (inject_emulated_exception(vcpu)) |
5455 | return r; | |
d2ddd1c4 | 5456 | } else if (vcpu->arch.pio.count) { |
0912c977 PB |
5457 | if (!vcpu->arch.pio.in) { |
5458 | /* FIXME: return into emulator if single-stepping. */ | |
3457e419 | 5459 | vcpu->arch.pio.count = 0; |
0912c977 | 5460 | } else { |
7ae441ea | 5461 | writeback = false; |
716d51ab GN |
5462 | vcpu->arch.complete_userspace_io = complete_emulated_pio; |
5463 | } | |
ac0a48c3 | 5464 | r = EMULATE_USER_EXIT; |
7ae441ea GN |
5465 | } else if (vcpu->mmio_needed) { |
5466 | if (!vcpu->mmio_is_write) | |
5467 | writeback = false; | |
ac0a48c3 | 5468 | r = EMULATE_USER_EXIT; |
716d51ab | 5469 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; |
7ae441ea | 5470 | } else if (r == EMULATION_RESTART) |
5cd21917 | 5471 | goto restart; |
d2ddd1c4 GN |
5472 | else |
5473 | r = EMULATE_DONE; | |
f850e2e6 | 5474 | |
7ae441ea | 5475 | if (writeback) { |
6addfc42 | 5476 | unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); |
9d74191a | 5477 | toggle_interruptibility(vcpu, ctxt->interruptibility); |
7ae441ea | 5478 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
9d74191a | 5479 | kvm_rip_write(vcpu, ctxt->eip); |
663f4c61 | 5480 | if (r == EMULATE_DONE) |
6addfc42 | 5481 | kvm_vcpu_check_singlestep(vcpu, rflags, &r); |
38827dbd NA |
5482 | if (!ctxt->have_exception || |
5483 | exception_type(ctxt->exception.vector) == EXCPT_TRAP) | |
5484 | __kvm_set_rflags(vcpu, ctxt->eflags); | |
6addfc42 PB |
5485 | |
5486 | /* | |
5487 | * For STI, interrupts are shadowed; so KVM_REQ_EVENT will | |
5488 | * do nothing, and it will be requested again as soon as | |
5489 | * the shadow expires. But we still need to check here, | |
5490 | * because POPF has no interrupt shadow. | |
5491 | */ | |
5492 | if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) | |
5493 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7ae441ea GN |
5494 | } else |
5495 | vcpu->arch.emulate_regs_need_sync_to_vcpu = true; | |
e85d28f8 GN |
5496 | |
5497 | return r; | |
de7d789a | 5498 | } |
51d8b661 | 5499 | EXPORT_SYMBOL_GPL(x86_emulate_instruction); |
de7d789a | 5500 | |
cf8f70bf | 5501 | int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port) |
de7d789a | 5502 | { |
cf8f70bf | 5503 | unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); |
ca1d4a9e AK |
5504 | int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, |
5505 | size, port, &val, 1); | |
cf8f70bf | 5506 | /* do not return to emulator after return from userspace */ |
7972995b | 5507 | vcpu->arch.pio.count = 0; |
de7d789a CO |
5508 | return ret; |
5509 | } | |
cf8f70bf | 5510 | EXPORT_SYMBOL_GPL(kvm_fast_pio_out); |
de7d789a | 5511 | |
8cfdc000 ZA |
5512 | static void tsc_bad(void *info) |
5513 | { | |
0a3aee0d | 5514 | __this_cpu_write(cpu_tsc_khz, 0); |
8cfdc000 ZA |
5515 | } |
5516 | ||
5517 | static void tsc_khz_changed(void *data) | |
c8076604 | 5518 | { |
8cfdc000 ZA |
5519 | struct cpufreq_freqs *freq = data; |
5520 | unsigned long khz = 0; | |
5521 | ||
5522 | if (data) | |
5523 | khz = freq->new; | |
5524 | else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
5525 | khz = cpufreq_quick_get(raw_smp_processor_id()); | |
5526 | if (!khz) | |
5527 | khz = tsc_khz; | |
0a3aee0d | 5528 | __this_cpu_write(cpu_tsc_khz, khz); |
c8076604 GH |
5529 | } |
5530 | ||
c8076604 GH |
5531 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, |
5532 | void *data) | |
5533 | { | |
5534 | struct cpufreq_freqs *freq = data; | |
5535 | struct kvm *kvm; | |
5536 | struct kvm_vcpu *vcpu; | |
5537 | int i, send_ipi = 0; | |
5538 | ||
8cfdc000 ZA |
5539 | /* |
5540 | * We allow guests to temporarily run on slowing clocks, | |
5541 | * provided we notify them after, or to run on accelerating | |
5542 | * clocks, provided we notify them before. Thus time never | |
5543 | * goes backwards. | |
5544 | * | |
5545 | * However, we have a problem. We can't atomically update | |
5546 | * the frequency of a given CPU from this function; it is | |
5547 | * merely a notifier, which can be called from any CPU. | |
5548 | * Changing the TSC frequency at arbitrary points in time | |
5549 | * requires a recomputation of local variables related to | |
5550 | * the TSC for each VCPU. We must flag these local variables | |
5551 | * to be updated and be sure the update takes place with the | |
5552 | * new frequency before any guests proceed. | |
5553 | * | |
5554 | * Unfortunately, the combination of hotplug CPU and frequency | |
5555 | * change creates an intractable locking scenario; the order | |
5556 | * of when these callouts happen is undefined with respect to | |
5557 | * CPU hotplug, and they can race with each other. As such, | |
5558 | * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is | |
5559 | * undefined; you can actually have a CPU frequency change take | |
5560 | * place in between the computation of X and the setting of the | |
5561 | * variable. To protect against this problem, all updates of | |
5562 | * the per_cpu tsc_khz variable are done in an interrupt | |
5563 | * protected IPI, and all callers wishing to update the value | |
5564 | * must wait for a synchronous IPI to complete (which is trivial | |
5565 | * if the caller is on the CPU already). This establishes the | |
5566 | * necessary total order on variable updates. | |
5567 | * | |
5568 | * Note that because a guest time update may take place | |
5569 | * anytime after the setting of the VCPU's request bit, the | |
5570 | * correct TSC value must be set before the request. However, | |
5571 | * to ensure the update actually makes it to any guest which | |
5572 | * starts running in hardware virtualization between the set | |
5573 | * and the acquisition of the spinlock, we must also ping the | |
5574 | * CPU after setting the request bit. | |
5575 | * | |
5576 | */ | |
5577 | ||
c8076604 GH |
5578 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) |
5579 | return 0; | |
5580 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
5581 | return 0; | |
8cfdc000 ZA |
5582 | |
5583 | smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); | |
c8076604 | 5584 | |
2f303b74 | 5585 | spin_lock(&kvm_lock); |
c8076604 | 5586 | list_for_each_entry(kvm, &vm_list, vm_list) { |
988a2cae | 5587 | kvm_for_each_vcpu(i, vcpu, kvm) { |
c8076604 GH |
5588 | if (vcpu->cpu != freq->cpu) |
5589 | continue; | |
c285545f | 5590 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
c8076604 | 5591 | if (vcpu->cpu != smp_processor_id()) |
8cfdc000 | 5592 | send_ipi = 1; |
c8076604 GH |
5593 | } |
5594 | } | |
2f303b74 | 5595 | spin_unlock(&kvm_lock); |
c8076604 GH |
5596 | |
5597 | if (freq->old < freq->new && send_ipi) { | |
5598 | /* | |
5599 | * We upscale the frequency. Must make the guest | |
5600 | * doesn't see old kvmclock values while running with | |
5601 | * the new frequency, otherwise we risk the guest sees | |
5602 | * time go backwards. | |
5603 | * | |
5604 | * In case we update the frequency for another cpu | |
5605 | * (which might be in guest context) send an interrupt | |
5606 | * to kick the cpu out of guest context. Next time | |
5607 | * guest context is entered kvmclock will be updated, | |
5608 | * so the guest will not see stale values. | |
5609 | */ | |
8cfdc000 | 5610 | smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); |
c8076604 GH |
5611 | } |
5612 | return 0; | |
5613 | } | |
5614 | ||
5615 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
8cfdc000 ZA |
5616 | .notifier_call = kvmclock_cpufreq_notifier |
5617 | }; | |
5618 | ||
5619 | static int kvmclock_cpu_notifier(struct notifier_block *nfb, | |
5620 | unsigned long action, void *hcpu) | |
5621 | { | |
5622 | unsigned int cpu = (unsigned long)hcpu; | |
5623 | ||
5624 | switch (action) { | |
5625 | case CPU_ONLINE: | |
5626 | case CPU_DOWN_FAILED: | |
5627 | smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); | |
5628 | break; | |
5629 | case CPU_DOWN_PREPARE: | |
5630 | smp_call_function_single(cpu, tsc_bad, NULL, 1); | |
5631 | break; | |
5632 | } | |
5633 | return NOTIFY_OK; | |
5634 | } | |
5635 | ||
5636 | static struct notifier_block kvmclock_cpu_notifier_block = { | |
5637 | .notifier_call = kvmclock_cpu_notifier, | |
5638 | .priority = -INT_MAX | |
c8076604 GH |
5639 | }; |
5640 | ||
b820cc0c ZA |
5641 | static void kvm_timer_init(void) |
5642 | { | |
5643 | int cpu; | |
5644 | ||
c285545f | 5645 | max_tsc_khz = tsc_khz; |
460dd42e SB |
5646 | |
5647 | cpu_notifier_register_begin(); | |
b820cc0c | 5648 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
c285545f ZA |
5649 | #ifdef CONFIG_CPU_FREQ |
5650 | struct cpufreq_policy policy; | |
5651 | memset(&policy, 0, sizeof(policy)); | |
3e26f230 AK |
5652 | cpu = get_cpu(); |
5653 | cpufreq_get_policy(&policy, cpu); | |
c285545f ZA |
5654 | if (policy.cpuinfo.max_freq) |
5655 | max_tsc_khz = policy.cpuinfo.max_freq; | |
3e26f230 | 5656 | put_cpu(); |
c285545f | 5657 | #endif |
b820cc0c ZA |
5658 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
5659 | CPUFREQ_TRANSITION_NOTIFIER); | |
5660 | } | |
c285545f | 5661 | pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); |
8cfdc000 ZA |
5662 | for_each_online_cpu(cpu) |
5663 | smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); | |
460dd42e SB |
5664 | |
5665 | __register_hotcpu_notifier(&kvmclock_cpu_notifier_block); | |
5666 | cpu_notifier_register_done(); | |
5667 | ||
b820cc0c ZA |
5668 | } |
5669 | ||
ff9d07a0 ZY |
5670 | static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); |
5671 | ||
f5132b01 | 5672 | int kvm_is_in_guest(void) |
ff9d07a0 | 5673 | { |
086c9855 | 5674 | return __this_cpu_read(current_vcpu) != NULL; |
ff9d07a0 ZY |
5675 | } |
5676 | ||
5677 | static int kvm_is_user_mode(void) | |
5678 | { | |
5679 | int user_mode = 3; | |
dcf46b94 | 5680 | |
086c9855 AS |
5681 | if (__this_cpu_read(current_vcpu)) |
5682 | user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 5683 | |
ff9d07a0 ZY |
5684 | return user_mode != 0; |
5685 | } | |
5686 | ||
5687 | static unsigned long kvm_get_guest_ip(void) | |
5688 | { | |
5689 | unsigned long ip = 0; | |
dcf46b94 | 5690 | |
086c9855 AS |
5691 | if (__this_cpu_read(current_vcpu)) |
5692 | ip = kvm_rip_read(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 5693 | |
ff9d07a0 ZY |
5694 | return ip; |
5695 | } | |
5696 | ||
5697 | static struct perf_guest_info_callbacks kvm_guest_cbs = { | |
5698 | .is_in_guest = kvm_is_in_guest, | |
5699 | .is_user_mode = kvm_is_user_mode, | |
5700 | .get_guest_ip = kvm_get_guest_ip, | |
5701 | }; | |
5702 | ||
5703 | void kvm_before_handle_nmi(struct kvm_vcpu *vcpu) | |
5704 | { | |
086c9855 | 5705 | __this_cpu_write(current_vcpu, vcpu); |
ff9d07a0 ZY |
5706 | } |
5707 | EXPORT_SYMBOL_GPL(kvm_before_handle_nmi); | |
5708 | ||
5709 | void kvm_after_handle_nmi(struct kvm_vcpu *vcpu) | |
5710 | { | |
086c9855 | 5711 | __this_cpu_write(current_vcpu, NULL); |
ff9d07a0 ZY |
5712 | } |
5713 | EXPORT_SYMBOL_GPL(kvm_after_handle_nmi); | |
5714 | ||
ce88decf XG |
5715 | static void kvm_set_mmio_spte_mask(void) |
5716 | { | |
5717 | u64 mask; | |
5718 | int maxphyaddr = boot_cpu_data.x86_phys_bits; | |
5719 | ||
5720 | /* | |
5721 | * Set the reserved bits and the present bit of an paging-structure | |
5722 | * entry to generate page fault with PFER.RSV = 1. | |
5723 | */ | |
885032b9 | 5724 | /* Mask the reserved physical address bits. */ |
d1431483 | 5725 | mask = rsvd_bits(maxphyaddr, 51); |
885032b9 XG |
5726 | |
5727 | /* Bit 62 is always reserved for 32bit host. */ | |
5728 | mask |= 0x3ull << 62; | |
5729 | ||
5730 | /* Set the present bit. */ | |
ce88decf XG |
5731 | mask |= 1ull; |
5732 | ||
5733 | #ifdef CONFIG_X86_64 | |
5734 | /* | |
5735 | * If reserved bit is not supported, clear the present bit to disable | |
5736 | * mmio page fault. | |
5737 | */ | |
5738 | if (maxphyaddr == 52) | |
5739 | mask &= ~1ull; | |
5740 | #endif | |
5741 | ||
5742 | kvm_mmu_set_mmio_spte_mask(mask); | |
5743 | } | |
5744 | ||
16e8d74d MT |
5745 | #ifdef CONFIG_X86_64 |
5746 | static void pvclock_gtod_update_fn(struct work_struct *work) | |
5747 | { | |
d828199e MT |
5748 | struct kvm *kvm; |
5749 | ||
5750 | struct kvm_vcpu *vcpu; | |
5751 | int i; | |
5752 | ||
2f303b74 | 5753 | spin_lock(&kvm_lock); |
d828199e MT |
5754 | list_for_each_entry(kvm, &vm_list, vm_list) |
5755 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 5756 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
d828199e | 5757 | atomic_set(&kvm_guest_has_master_clock, 0); |
2f303b74 | 5758 | spin_unlock(&kvm_lock); |
16e8d74d MT |
5759 | } |
5760 | ||
5761 | static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); | |
5762 | ||
5763 | /* | |
5764 | * Notification about pvclock gtod data update. | |
5765 | */ | |
5766 | static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, | |
5767 | void *priv) | |
5768 | { | |
5769 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
5770 | struct timekeeper *tk = priv; | |
5771 | ||
5772 | update_pvclock_gtod(tk); | |
5773 | ||
5774 | /* disable master clock if host does not trust, or does not | |
5775 | * use, TSC clocksource | |
5776 | */ | |
5777 | if (gtod->clock.vclock_mode != VCLOCK_TSC && | |
5778 | atomic_read(&kvm_guest_has_master_clock) != 0) | |
5779 | queue_work(system_long_wq, &pvclock_gtod_work); | |
5780 | ||
5781 | return 0; | |
5782 | } | |
5783 | ||
5784 | static struct notifier_block pvclock_gtod_notifier = { | |
5785 | .notifier_call = pvclock_gtod_notify, | |
5786 | }; | |
5787 | #endif | |
5788 | ||
f8c16bba | 5789 | int kvm_arch_init(void *opaque) |
043405e1 | 5790 | { |
b820cc0c | 5791 | int r; |
6b61edf7 | 5792 | struct kvm_x86_ops *ops = opaque; |
f8c16bba | 5793 | |
f8c16bba ZX |
5794 | if (kvm_x86_ops) { |
5795 | printk(KERN_ERR "kvm: already loaded the other module\n"); | |
56c6d28a ZX |
5796 | r = -EEXIST; |
5797 | goto out; | |
f8c16bba ZX |
5798 | } |
5799 | ||
5800 | if (!ops->cpu_has_kvm_support()) { | |
5801 | printk(KERN_ERR "kvm: no hardware support\n"); | |
56c6d28a ZX |
5802 | r = -EOPNOTSUPP; |
5803 | goto out; | |
f8c16bba ZX |
5804 | } |
5805 | if (ops->disabled_by_bios()) { | |
5806 | printk(KERN_ERR "kvm: disabled by bios\n"); | |
56c6d28a ZX |
5807 | r = -EOPNOTSUPP; |
5808 | goto out; | |
f8c16bba ZX |
5809 | } |
5810 | ||
013f6a5d MT |
5811 | r = -ENOMEM; |
5812 | shared_msrs = alloc_percpu(struct kvm_shared_msrs); | |
5813 | if (!shared_msrs) { | |
5814 | printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); | |
5815 | goto out; | |
5816 | } | |
5817 | ||
97db56ce AK |
5818 | r = kvm_mmu_module_init(); |
5819 | if (r) | |
013f6a5d | 5820 | goto out_free_percpu; |
97db56ce | 5821 | |
ce88decf | 5822 | kvm_set_mmio_spte_mask(); |
97db56ce | 5823 | |
f8c16bba | 5824 | kvm_x86_ops = ops; |
920c8377 | 5825 | |
7b52345e | 5826 | kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, |
4b12f0de | 5827 | PT_DIRTY_MASK, PT64_NX_MASK, 0); |
c8076604 | 5828 | |
b820cc0c | 5829 | kvm_timer_init(); |
c8076604 | 5830 | |
ff9d07a0 ZY |
5831 | perf_register_guest_info_callbacks(&kvm_guest_cbs); |
5832 | ||
2acf923e DC |
5833 | if (cpu_has_xsave) |
5834 | host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); | |
5835 | ||
c5cc421b | 5836 | kvm_lapic_init(); |
16e8d74d MT |
5837 | #ifdef CONFIG_X86_64 |
5838 | pvclock_gtod_register_notifier(&pvclock_gtod_notifier); | |
5839 | #endif | |
5840 | ||
f8c16bba | 5841 | return 0; |
56c6d28a | 5842 | |
013f6a5d MT |
5843 | out_free_percpu: |
5844 | free_percpu(shared_msrs); | |
56c6d28a | 5845 | out: |
56c6d28a | 5846 | return r; |
043405e1 | 5847 | } |
8776e519 | 5848 | |
f8c16bba ZX |
5849 | void kvm_arch_exit(void) |
5850 | { | |
ff9d07a0 ZY |
5851 | perf_unregister_guest_info_callbacks(&kvm_guest_cbs); |
5852 | ||
888d256e JK |
5853 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
5854 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
5855 | CPUFREQ_TRANSITION_NOTIFIER); | |
8cfdc000 | 5856 | unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block); |
16e8d74d MT |
5857 | #ifdef CONFIG_X86_64 |
5858 | pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); | |
5859 | #endif | |
f8c16bba | 5860 | kvm_x86_ops = NULL; |
56c6d28a | 5861 | kvm_mmu_module_exit(); |
013f6a5d | 5862 | free_percpu(shared_msrs); |
56c6d28a | 5863 | } |
f8c16bba | 5864 | |
5cb56059 | 5865 | int kvm_vcpu_halt(struct kvm_vcpu *vcpu) |
8776e519 HB |
5866 | { |
5867 | ++vcpu->stat.halt_exits; | |
5868 | if (irqchip_in_kernel(vcpu->kvm)) { | |
a4535290 | 5869 | vcpu->arch.mp_state = KVM_MP_STATE_HALTED; |
8776e519 HB |
5870 | return 1; |
5871 | } else { | |
5872 | vcpu->run->exit_reason = KVM_EXIT_HLT; | |
5873 | return 0; | |
5874 | } | |
5875 | } | |
5cb56059 JS |
5876 | EXPORT_SYMBOL_GPL(kvm_vcpu_halt); |
5877 | ||
5878 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) | |
5879 | { | |
5880 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
5881 | return kvm_vcpu_halt(vcpu); | |
5882 | } | |
8776e519 HB |
5883 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); |
5884 | ||
55cd8e5a GN |
5885 | int kvm_hv_hypercall(struct kvm_vcpu *vcpu) |
5886 | { | |
5887 | u64 param, ingpa, outgpa, ret; | |
5888 | uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0; | |
5889 | bool fast, longmode; | |
55cd8e5a GN |
5890 | |
5891 | /* | |
5892 | * hypercall generates UD from non zero cpl and real mode | |
5893 | * per HYPER-V spec | |
5894 | */ | |
3eeb3288 | 5895 | if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) { |
55cd8e5a GN |
5896 | kvm_queue_exception(vcpu, UD_VECTOR); |
5897 | return 0; | |
5898 | } | |
5899 | ||
a449c7aa | 5900 | longmode = is_64_bit_mode(vcpu); |
55cd8e5a GN |
5901 | |
5902 | if (!longmode) { | |
ccd46936 GN |
5903 | param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) | |
5904 | (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff); | |
5905 | ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) | | |
5906 | (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff); | |
5907 | outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) | | |
5908 | (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff); | |
55cd8e5a GN |
5909 | } |
5910 | #ifdef CONFIG_X86_64 | |
5911 | else { | |
5912 | param = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
5913 | ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
5914 | outgpa = kvm_register_read(vcpu, VCPU_REGS_R8); | |
5915 | } | |
5916 | #endif | |
5917 | ||
5918 | code = param & 0xffff; | |
5919 | fast = (param >> 16) & 0x1; | |
5920 | rep_cnt = (param >> 32) & 0xfff; | |
5921 | rep_idx = (param >> 48) & 0xfff; | |
5922 | ||
5923 | trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa); | |
5924 | ||
c25bc163 GN |
5925 | switch (code) { |
5926 | case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT: | |
5927 | kvm_vcpu_on_spin(vcpu); | |
5928 | break; | |
5929 | default: | |
5930 | res = HV_STATUS_INVALID_HYPERCALL_CODE; | |
5931 | break; | |
5932 | } | |
55cd8e5a GN |
5933 | |
5934 | ret = res | (((u64)rep_done & 0xfff) << 32); | |
5935 | if (longmode) { | |
5936 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); | |
5937 | } else { | |
5938 | kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32); | |
5939 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff); | |
5940 | } | |
5941 | ||
5942 | return 1; | |
5943 | } | |
5944 | ||
6aef266c SV |
5945 | /* |
5946 | * kvm_pv_kick_cpu_op: Kick a vcpu. | |
5947 | * | |
5948 | * @apicid - apicid of vcpu to be kicked. | |
5949 | */ | |
5950 | static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) | |
5951 | { | |
24d2166b | 5952 | struct kvm_lapic_irq lapic_irq; |
6aef266c | 5953 | |
24d2166b R |
5954 | lapic_irq.shorthand = 0; |
5955 | lapic_irq.dest_mode = 0; | |
5956 | lapic_irq.dest_id = apicid; | |
6aef266c | 5957 | |
24d2166b | 5958 | lapic_irq.delivery_mode = APIC_DM_REMRD; |
795a149e | 5959 | kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); |
6aef266c SV |
5960 | } |
5961 | ||
8776e519 HB |
5962 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
5963 | { | |
5964 | unsigned long nr, a0, a1, a2, a3, ret; | |
a449c7aa | 5965 | int op_64_bit, r = 1; |
8776e519 | 5966 | |
5cb56059 JS |
5967 | kvm_x86_ops->skip_emulated_instruction(vcpu); |
5968 | ||
55cd8e5a GN |
5969 | if (kvm_hv_hypercall_enabled(vcpu->kvm)) |
5970 | return kvm_hv_hypercall(vcpu); | |
5971 | ||
5fdbf976 MT |
5972 | nr = kvm_register_read(vcpu, VCPU_REGS_RAX); |
5973 | a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
5974 | a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
5975 | a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
5976 | a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
8776e519 | 5977 | |
229456fc | 5978 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 5979 | |
a449c7aa NA |
5980 | op_64_bit = is_64_bit_mode(vcpu); |
5981 | if (!op_64_bit) { | |
8776e519 HB |
5982 | nr &= 0xFFFFFFFF; |
5983 | a0 &= 0xFFFFFFFF; | |
5984 | a1 &= 0xFFFFFFFF; | |
5985 | a2 &= 0xFFFFFFFF; | |
5986 | a3 &= 0xFFFFFFFF; | |
5987 | } | |
5988 | ||
07708c4a JK |
5989 | if (kvm_x86_ops->get_cpl(vcpu) != 0) { |
5990 | ret = -KVM_EPERM; | |
5991 | goto out; | |
5992 | } | |
5993 | ||
8776e519 | 5994 | switch (nr) { |
b93463aa AK |
5995 | case KVM_HC_VAPIC_POLL_IRQ: |
5996 | ret = 0; | |
5997 | break; | |
6aef266c SV |
5998 | case KVM_HC_KICK_CPU: |
5999 | kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); | |
6000 | ret = 0; | |
6001 | break; | |
8776e519 HB |
6002 | default: |
6003 | ret = -KVM_ENOSYS; | |
6004 | break; | |
6005 | } | |
07708c4a | 6006 | out: |
a449c7aa NA |
6007 | if (!op_64_bit) |
6008 | ret = (u32)ret; | |
5fdbf976 | 6009 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); |
f11c3a8d | 6010 | ++vcpu->stat.hypercalls; |
2f333bcb | 6011 | return r; |
8776e519 HB |
6012 | } |
6013 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
6014 | ||
b6785def | 6015 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) |
8776e519 | 6016 | { |
d6aa1000 | 6017 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
8776e519 | 6018 | char instruction[3]; |
5fdbf976 | 6019 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 6020 | |
8776e519 | 6021 | kvm_x86_ops->patch_hypercall(vcpu, instruction); |
8776e519 | 6022 | |
9d74191a | 6023 | return emulator_write_emulated(ctxt, rip, instruction, 3, NULL); |
8776e519 HB |
6024 | } |
6025 | ||
b6c7a5dc HB |
6026 | /* |
6027 | * Check if userspace requested an interrupt window, and that the | |
6028 | * interrupt window is open. | |
6029 | * | |
6030 | * No need to exit to userspace if we already have an interrupt queued. | |
6031 | */ | |
851ba692 | 6032 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 6033 | { |
8061823a | 6034 | return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) && |
851ba692 | 6035 | vcpu->run->request_interrupt_window && |
5df56646 | 6036 | kvm_arch_interrupt_allowed(vcpu)); |
b6c7a5dc HB |
6037 | } |
6038 | ||
851ba692 | 6039 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 6040 | { |
851ba692 AK |
6041 | struct kvm_run *kvm_run = vcpu->run; |
6042 | ||
91586a3b | 6043 | kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; |
2d3ad1f4 | 6044 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 6045 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
4531220b | 6046 | if (irqchip_in_kernel(vcpu->kvm)) |
b6c7a5dc | 6047 | kvm_run->ready_for_interrupt_injection = 1; |
4531220b | 6048 | else |
b6c7a5dc | 6049 | kvm_run->ready_for_interrupt_injection = |
fa9726b0 GN |
6050 | kvm_arch_interrupt_allowed(vcpu) && |
6051 | !kvm_cpu_has_interrupt(vcpu) && | |
6052 | !kvm_event_needs_reinjection(vcpu); | |
b6c7a5dc HB |
6053 | } |
6054 | ||
95ba8273 GN |
6055 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
6056 | { | |
6057 | int max_irr, tpr; | |
6058 | ||
6059 | if (!kvm_x86_ops->update_cr8_intercept) | |
6060 | return; | |
6061 | ||
88c808fd AK |
6062 | if (!vcpu->arch.apic) |
6063 | return; | |
6064 | ||
8db3baa2 GN |
6065 | if (!vcpu->arch.apic->vapic_addr) |
6066 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
6067 | else | |
6068 | max_irr = -1; | |
95ba8273 GN |
6069 | |
6070 | if (max_irr != -1) | |
6071 | max_irr >>= 4; | |
6072 | ||
6073 | tpr = kvm_lapic_get_cr8(vcpu); | |
6074 | ||
6075 | kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); | |
6076 | } | |
6077 | ||
b6b8a145 | 6078 | static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) |
95ba8273 | 6079 | { |
b6b8a145 JK |
6080 | int r; |
6081 | ||
95ba8273 | 6082 | /* try to reinject previous events if any */ |
b59bb7bd | 6083 | if (vcpu->arch.exception.pending) { |
5c1c85d0 AK |
6084 | trace_kvm_inj_exception(vcpu->arch.exception.nr, |
6085 | vcpu->arch.exception.has_error_code, | |
6086 | vcpu->arch.exception.error_code); | |
d6e8c854 NA |
6087 | |
6088 | if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) | |
6089 | __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | | |
6090 | X86_EFLAGS_RF); | |
6091 | ||
6bdf0662 NA |
6092 | if (vcpu->arch.exception.nr == DB_VECTOR && |
6093 | (vcpu->arch.dr7 & DR7_GD)) { | |
6094 | vcpu->arch.dr7 &= ~DR7_GD; | |
6095 | kvm_update_dr7(vcpu); | |
6096 | } | |
6097 | ||
b59bb7bd GN |
6098 | kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, |
6099 | vcpu->arch.exception.has_error_code, | |
ce7ddec4 JR |
6100 | vcpu->arch.exception.error_code, |
6101 | vcpu->arch.exception.reinject); | |
b6b8a145 | 6102 | return 0; |
b59bb7bd GN |
6103 | } |
6104 | ||
95ba8273 GN |
6105 | if (vcpu->arch.nmi_injected) { |
6106 | kvm_x86_ops->set_nmi(vcpu); | |
b6b8a145 | 6107 | return 0; |
95ba8273 GN |
6108 | } |
6109 | ||
6110 | if (vcpu->arch.interrupt.pending) { | |
66fd3f7f | 6111 | kvm_x86_ops->set_irq(vcpu); |
b6b8a145 JK |
6112 | return 0; |
6113 | } | |
6114 | ||
6115 | if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { | |
6116 | r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); | |
6117 | if (r != 0) | |
6118 | return r; | |
95ba8273 GN |
6119 | } |
6120 | ||
6121 | /* try to inject new event if pending */ | |
6122 | if (vcpu->arch.nmi_pending) { | |
6123 | if (kvm_x86_ops->nmi_allowed(vcpu)) { | |
7460fb4a | 6124 | --vcpu->arch.nmi_pending; |
95ba8273 GN |
6125 | vcpu->arch.nmi_injected = true; |
6126 | kvm_x86_ops->set_nmi(vcpu); | |
6127 | } | |
c7c9c56c | 6128 | } else if (kvm_cpu_has_injectable_intr(vcpu)) { |
9242b5b6 BD |
6129 | /* |
6130 | * Because interrupts can be injected asynchronously, we are | |
6131 | * calling check_nested_events again here to avoid a race condition. | |
6132 | * See https://lkml.org/lkml/2014/7/2/60 for discussion about this | |
6133 | * proposal and current concerns. Perhaps we should be setting | |
6134 | * KVM_REQ_EVENT only on certain events and not unconditionally? | |
6135 | */ | |
6136 | if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { | |
6137 | r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); | |
6138 | if (r != 0) | |
6139 | return r; | |
6140 | } | |
95ba8273 | 6141 | if (kvm_x86_ops->interrupt_allowed(vcpu)) { |
66fd3f7f GN |
6142 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), |
6143 | false); | |
6144 | kvm_x86_ops->set_irq(vcpu); | |
95ba8273 GN |
6145 | } |
6146 | } | |
b6b8a145 | 6147 | return 0; |
95ba8273 GN |
6148 | } |
6149 | ||
7460fb4a AK |
6150 | static void process_nmi(struct kvm_vcpu *vcpu) |
6151 | { | |
6152 | unsigned limit = 2; | |
6153 | ||
6154 | /* | |
6155 | * x86 is limited to one NMI running, and one NMI pending after it. | |
6156 | * If an NMI is already in progress, limit further NMIs to just one. | |
6157 | * Otherwise, allow two (and we'll inject the first one immediately). | |
6158 | */ | |
6159 | if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) | |
6160 | limit = 1; | |
6161 | ||
6162 | vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); | |
6163 | vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); | |
6164 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
6165 | } | |
6166 | ||
3d81bc7e | 6167 | static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) |
c7c9c56c YZ |
6168 | { |
6169 | u64 eoi_exit_bitmap[4]; | |
cf9e65b7 | 6170 | u32 tmr[8]; |
c7c9c56c | 6171 | |
3d81bc7e YZ |
6172 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) |
6173 | return; | |
c7c9c56c YZ |
6174 | |
6175 | memset(eoi_exit_bitmap, 0, 32); | |
cf9e65b7 | 6176 | memset(tmr, 0, 32); |
c7c9c56c | 6177 | |
cf9e65b7 | 6178 | kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr); |
c7c9c56c | 6179 | kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); |
cf9e65b7 | 6180 | kvm_apic_update_tmr(vcpu, tmr); |
c7c9c56c YZ |
6181 | } |
6182 | ||
a70656b6 RK |
6183 | static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu) |
6184 | { | |
6185 | ++vcpu->stat.tlb_flush; | |
6186 | kvm_x86_ops->tlb_flush(vcpu); | |
6187 | } | |
6188 | ||
4256f43f TC |
6189 | void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) |
6190 | { | |
c24ae0dc TC |
6191 | struct page *page = NULL; |
6192 | ||
f439ed27 PB |
6193 | if (!irqchip_in_kernel(vcpu->kvm)) |
6194 | return; | |
6195 | ||
4256f43f TC |
6196 | if (!kvm_x86_ops->set_apic_access_page_addr) |
6197 | return; | |
6198 | ||
c24ae0dc TC |
6199 | page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); |
6200 | kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page)); | |
6201 | ||
6202 | /* | |
6203 | * Do not pin apic access page in memory, the MMU notifier | |
6204 | * will call us again if it is migrated or swapped out. | |
6205 | */ | |
6206 | put_page(page); | |
4256f43f TC |
6207 | } |
6208 | EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page); | |
6209 | ||
fe71557a TC |
6210 | void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm, |
6211 | unsigned long address) | |
6212 | { | |
c24ae0dc TC |
6213 | /* |
6214 | * The physical address of apic access page is stored in the VMCS. | |
6215 | * Update it when it becomes invalid. | |
6216 | */ | |
6217 | if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT)) | |
6218 | kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); | |
fe71557a TC |
6219 | } |
6220 | ||
9357d939 | 6221 | /* |
362c698f | 6222 | * Returns 1 to let vcpu_run() continue the guest execution loop without |
9357d939 TY |
6223 | * exiting to the userspace. Otherwise, the value will be returned to the |
6224 | * userspace. | |
6225 | */ | |
851ba692 | 6226 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
6227 | { |
6228 | int r; | |
6a8b1d13 | 6229 | bool req_int_win = !irqchip_in_kernel(vcpu->kvm) && |
851ba692 | 6230 | vcpu->run->request_interrupt_window; |
730dca42 | 6231 | bool req_immediate_exit = false; |
b6c7a5dc | 6232 | |
3e007509 | 6233 | if (vcpu->requests) { |
a8eeb04a | 6234 | if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) |
2e53d63a | 6235 | kvm_mmu_unload(vcpu); |
a8eeb04a | 6236 | if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) |
2f599714 | 6237 | __kvm_migrate_timers(vcpu); |
d828199e MT |
6238 | if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) |
6239 | kvm_gen_update_masterclock(vcpu->kvm); | |
0061d53d MT |
6240 | if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) |
6241 | kvm_gen_kvmclock_update(vcpu); | |
34c238a1 ZA |
6242 | if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { |
6243 | r = kvm_guest_time_update(vcpu); | |
8cfdc000 ZA |
6244 | if (unlikely(r)) |
6245 | goto out; | |
6246 | } | |
a8eeb04a | 6247 | if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) |
4731d4c7 | 6248 | kvm_mmu_sync_roots(vcpu); |
a8eeb04a | 6249 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) |
a70656b6 | 6250 | kvm_vcpu_flush_tlb(vcpu); |
a8eeb04a | 6251 | if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { |
851ba692 | 6252 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
6253 | r = 0; |
6254 | goto out; | |
6255 | } | |
a8eeb04a | 6256 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
851ba692 | 6257 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
71c4dfaf JR |
6258 | r = 0; |
6259 | goto out; | |
6260 | } | |
a8eeb04a | 6261 | if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) { |
02daab21 AK |
6262 | vcpu->fpu_active = 0; |
6263 | kvm_x86_ops->fpu_deactivate(vcpu); | |
6264 | } | |
af585b92 GN |
6265 | if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { |
6266 | /* Page is swapped out. Do synthetic halt */ | |
6267 | vcpu->arch.apf.halted = true; | |
6268 | r = 1; | |
6269 | goto out; | |
6270 | } | |
c9aaa895 GC |
6271 | if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) |
6272 | record_steal_time(vcpu); | |
7460fb4a AK |
6273 | if (kvm_check_request(KVM_REQ_NMI, vcpu)) |
6274 | process_nmi(vcpu); | |
f5132b01 GN |
6275 | if (kvm_check_request(KVM_REQ_PMU, vcpu)) |
6276 | kvm_handle_pmu_event(vcpu); | |
6277 | if (kvm_check_request(KVM_REQ_PMI, vcpu)) | |
6278 | kvm_deliver_pmi(vcpu); | |
3d81bc7e YZ |
6279 | if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) |
6280 | vcpu_scan_ioapic(vcpu); | |
4256f43f TC |
6281 | if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) |
6282 | kvm_vcpu_reload_apic_access_page(vcpu); | |
2f52d58c | 6283 | } |
b93463aa | 6284 | |
b463a6f7 | 6285 | if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { |
66450a21 JK |
6286 | kvm_apic_accept_events(vcpu); |
6287 | if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { | |
6288 | r = 1; | |
6289 | goto out; | |
6290 | } | |
6291 | ||
b6b8a145 JK |
6292 | if (inject_pending_event(vcpu, req_int_win) != 0) |
6293 | req_immediate_exit = true; | |
b463a6f7 | 6294 | /* enable NMI/IRQ window open exits if needed */ |
b6b8a145 | 6295 | else if (vcpu->arch.nmi_pending) |
c9a7953f | 6296 | kvm_x86_ops->enable_nmi_window(vcpu); |
c7c9c56c | 6297 | else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) |
c9a7953f | 6298 | kvm_x86_ops->enable_irq_window(vcpu); |
b463a6f7 AK |
6299 | |
6300 | if (kvm_lapic_enabled(vcpu)) { | |
c7c9c56c YZ |
6301 | /* |
6302 | * Update architecture specific hints for APIC | |
6303 | * virtual interrupt delivery. | |
6304 | */ | |
6305 | if (kvm_x86_ops->hwapic_irr_update) | |
6306 | kvm_x86_ops->hwapic_irr_update(vcpu, | |
6307 | kvm_lapic_find_highest_irr(vcpu)); | |
b463a6f7 AK |
6308 | update_cr8_intercept(vcpu); |
6309 | kvm_lapic_sync_to_vapic(vcpu); | |
6310 | } | |
6311 | } | |
6312 | ||
d8368af8 AK |
6313 | r = kvm_mmu_reload(vcpu); |
6314 | if (unlikely(r)) { | |
d905c069 | 6315 | goto cancel_injection; |
d8368af8 AK |
6316 | } |
6317 | ||
b6c7a5dc HB |
6318 | preempt_disable(); |
6319 | ||
6320 | kvm_x86_ops->prepare_guest_switch(vcpu); | |
2608d7a1 AK |
6321 | if (vcpu->fpu_active) |
6322 | kvm_load_guest_fpu(vcpu); | |
2acf923e | 6323 | kvm_load_guest_xcr0(vcpu); |
b6c7a5dc | 6324 | |
6b7e2d09 XG |
6325 | vcpu->mode = IN_GUEST_MODE; |
6326 | ||
01b71917 MT |
6327 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
6328 | ||
6b7e2d09 XG |
6329 | /* We should set ->mode before check ->requests, |
6330 | * see the comment in make_all_cpus_request. | |
6331 | */ | |
01b71917 | 6332 | smp_mb__after_srcu_read_unlock(); |
b6c7a5dc | 6333 | |
d94e1dc9 | 6334 | local_irq_disable(); |
32f88400 | 6335 | |
6b7e2d09 | 6336 | if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests |
d94e1dc9 | 6337 | || need_resched() || signal_pending(current)) { |
6b7e2d09 | 6338 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 6339 | smp_wmb(); |
6c142801 AK |
6340 | local_irq_enable(); |
6341 | preempt_enable(); | |
01b71917 | 6342 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
6c142801 | 6343 | r = 1; |
d905c069 | 6344 | goto cancel_injection; |
6c142801 AK |
6345 | } |
6346 | ||
d6185f20 NHE |
6347 | if (req_immediate_exit) |
6348 | smp_send_reschedule(vcpu->cpu); | |
6349 | ||
b6c7a5dc HB |
6350 | kvm_guest_enter(); |
6351 | ||
42dbaa5a | 6352 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
6353 | set_debugreg(0, 7); |
6354 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
6355 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
6356 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
6357 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
c77fb5fe | 6358 | set_debugreg(vcpu->arch.dr6, 6); |
ae561ede | 6359 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; |
42dbaa5a | 6360 | } |
b6c7a5dc | 6361 | |
229456fc | 6362 | trace_kvm_entry(vcpu->vcpu_id); |
d0659d94 | 6363 | wait_lapic_expire(vcpu); |
851ba692 | 6364 | kvm_x86_ops->run(vcpu); |
b6c7a5dc | 6365 | |
c77fb5fe PB |
6366 | /* |
6367 | * Do this here before restoring debug registers on the host. And | |
6368 | * since we do this before handling the vmexit, a DR access vmexit | |
6369 | * can (a) read the correct value of the debug registers, (b) set | |
6370 | * KVM_DEBUGREG_WONT_EXIT again. | |
6371 | */ | |
6372 | if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { | |
6373 | int i; | |
6374 | ||
6375 | WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); | |
6376 | kvm_x86_ops->sync_dirty_debug_regs(vcpu); | |
6377 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
6378 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
6379 | } | |
6380 | ||
24f1e32c FW |
6381 | /* |
6382 | * If the guest has used debug registers, at least dr7 | |
6383 | * will be disabled while returning to the host. | |
6384 | * If we don't have active breakpoints in the host, we don't | |
6385 | * care about the messed up debug address registers. But if | |
6386 | * we have some of them active, restore the old state. | |
6387 | */ | |
59d8eb53 | 6388 | if (hw_breakpoint_active()) |
24f1e32c | 6389 | hw_breakpoint_restore(); |
42dbaa5a | 6390 | |
886b470c MT |
6391 | vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, |
6392 | native_read_tsc()); | |
1d5f066e | 6393 | |
6b7e2d09 | 6394 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 6395 | smp_wmb(); |
a547c6db YZ |
6396 | |
6397 | /* Interrupt is enabled by handle_external_intr() */ | |
6398 | kvm_x86_ops->handle_external_intr(vcpu); | |
b6c7a5dc HB |
6399 | |
6400 | ++vcpu->stat.exits; | |
6401 | ||
6402 | /* | |
6403 | * We must have an instruction between local_irq_enable() and | |
6404 | * kvm_guest_exit(), so the timer interrupt isn't delayed by | |
6405 | * the interrupt shadow. The stat.exits increment will do nicely. | |
6406 | * But we need to prevent reordering, hence this barrier(): | |
6407 | */ | |
6408 | barrier(); | |
6409 | ||
6410 | kvm_guest_exit(); | |
6411 | ||
6412 | preempt_enable(); | |
6413 | ||
f656ce01 | 6414 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
3200f405 | 6415 | |
b6c7a5dc HB |
6416 | /* |
6417 | * Profile KVM exit RIPs: | |
6418 | */ | |
6419 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
6420 | unsigned long rip = kvm_rip_read(vcpu); |
6421 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
6422 | } |
6423 | ||
cc578287 ZA |
6424 | if (unlikely(vcpu->arch.tsc_always_catchup)) |
6425 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
298101da | 6426 | |
5cfb1d5a MT |
6427 | if (vcpu->arch.apic_attention) |
6428 | kvm_lapic_sync_from_vapic(vcpu); | |
b93463aa | 6429 | |
851ba692 | 6430 | r = kvm_x86_ops->handle_exit(vcpu); |
d905c069 MT |
6431 | return r; |
6432 | ||
6433 | cancel_injection: | |
6434 | kvm_x86_ops->cancel_injection(vcpu); | |
ae7a2a3f MT |
6435 | if (unlikely(vcpu->arch.apic_attention)) |
6436 | kvm_lapic_sync_from_vapic(vcpu); | |
d7690175 MT |
6437 | out: |
6438 | return r; | |
6439 | } | |
b6c7a5dc | 6440 | |
362c698f PB |
6441 | static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) |
6442 | { | |
9c8fd1ba PB |
6443 | if (!kvm_arch_vcpu_runnable(vcpu)) { |
6444 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); | |
6445 | kvm_vcpu_block(vcpu); | |
6446 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); | |
6447 | if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) | |
6448 | return 1; | |
6449 | } | |
362c698f PB |
6450 | |
6451 | kvm_apic_accept_events(vcpu); | |
6452 | switch(vcpu->arch.mp_state) { | |
6453 | case KVM_MP_STATE_HALTED: | |
6454 | vcpu->arch.pv.pv_unhalted = false; | |
6455 | vcpu->arch.mp_state = | |
6456 | KVM_MP_STATE_RUNNABLE; | |
6457 | case KVM_MP_STATE_RUNNABLE: | |
6458 | vcpu->arch.apf.halted = false; | |
6459 | break; | |
6460 | case KVM_MP_STATE_INIT_RECEIVED: | |
6461 | break; | |
6462 | default: | |
6463 | return -EINTR; | |
6464 | break; | |
6465 | } | |
6466 | return 1; | |
6467 | } | |
09cec754 | 6468 | |
362c698f | 6469 | static int vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
6470 | { |
6471 | int r; | |
f656ce01 | 6472 | struct kvm *kvm = vcpu->kvm; |
d7690175 | 6473 | |
f656ce01 | 6474 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 6475 | |
362c698f | 6476 | for (;;) { |
af585b92 GN |
6477 | if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
6478 | !vcpu->arch.apf.halted) | |
851ba692 | 6479 | r = vcpu_enter_guest(vcpu); |
362c698f PB |
6480 | else |
6481 | r = vcpu_block(kvm, vcpu); | |
09cec754 GN |
6482 | if (r <= 0) |
6483 | break; | |
6484 | ||
6485 | clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); | |
6486 | if (kvm_cpu_has_pending_timer(vcpu)) | |
6487 | kvm_inject_pending_timer_irqs(vcpu); | |
6488 | ||
851ba692 | 6489 | if (dm_request_for_irq_injection(vcpu)) { |
09cec754 | 6490 | r = -EINTR; |
851ba692 | 6491 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 | 6492 | ++vcpu->stat.request_irq_exits; |
362c698f | 6493 | break; |
09cec754 | 6494 | } |
af585b92 GN |
6495 | |
6496 | kvm_check_async_pf_completion(vcpu); | |
6497 | ||
09cec754 GN |
6498 | if (signal_pending(current)) { |
6499 | r = -EINTR; | |
851ba692 | 6500 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 | 6501 | ++vcpu->stat.signal_exits; |
362c698f | 6502 | break; |
09cec754 GN |
6503 | } |
6504 | if (need_resched()) { | |
f656ce01 | 6505 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
c08ac06a | 6506 | cond_resched(); |
f656ce01 | 6507 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 6508 | } |
b6c7a5dc HB |
6509 | } |
6510 | ||
f656ce01 | 6511 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
b6c7a5dc HB |
6512 | |
6513 | return r; | |
6514 | } | |
6515 | ||
716d51ab GN |
6516 | static inline int complete_emulated_io(struct kvm_vcpu *vcpu) |
6517 | { | |
6518 | int r; | |
6519 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); | |
6520 | r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE); | |
6521 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); | |
6522 | if (r != EMULATE_DONE) | |
6523 | return 0; | |
6524 | return 1; | |
6525 | } | |
6526 | ||
6527 | static int complete_emulated_pio(struct kvm_vcpu *vcpu) | |
6528 | { | |
6529 | BUG_ON(!vcpu->arch.pio.count); | |
6530 | ||
6531 | return complete_emulated_io(vcpu); | |
6532 | } | |
6533 | ||
f78146b0 AK |
6534 | /* |
6535 | * Implements the following, as a state machine: | |
6536 | * | |
6537 | * read: | |
6538 | * for each fragment | |
87da7e66 XG |
6539 | * for each mmio piece in the fragment |
6540 | * write gpa, len | |
6541 | * exit | |
6542 | * copy data | |
f78146b0 AK |
6543 | * execute insn |
6544 | * | |
6545 | * write: | |
6546 | * for each fragment | |
87da7e66 XG |
6547 | * for each mmio piece in the fragment |
6548 | * write gpa, len | |
6549 | * copy data | |
6550 | * exit | |
f78146b0 | 6551 | */ |
716d51ab | 6552 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu) |
5287f194 AK |
6553 | { |
6554 | struct kvm_run *run = vcpu->run; | |
f78146b0 | 6555 | struct kvm_mmio_fragment *frag; |
87da7e66 | 6556 | unsigned len; |
5287f194 | 6557 | |
716d51ab | 6558 | BUG_ON(!vcpu->mmio_needed); |
5287f194 | 6559 | |
716d51ab | 6560 | /* Complete previous fragment */ |
87da7e66 XG |
6561 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; |
6562 | len = min(8u, frag->len); | |
716d51ab | 6563 | if (!vcpu->mmio_is_write) |
87da7e66 XG |
6564 | memcpy(frag->data, run->mmio.data, len); |
6565 | ||
6566 | if (frag->len <= 8) { | |
6567 | /* Switch to the next fragment. */ | |
6568 | frag++; | |
6569 | vcpu->mmio_cur_fragment++; | |
6570 | } else { | |
6571 | /* Go forward to the next mmio piece. */ | |
6572 | frag->data += len; | |
6573 | frag->gpa += len; | |
6574 | frag->len -= len; | |
6575 | } | |
6576 | ||
a08d3b3b | 6577 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { |
716d51ab | 6578 | vcpu->mmio_needed = 0; |
0912c977 PB |
6579 | |
6580 | /* FIXME: return into emulator if single-stepping. */ | |
cef4dea0 | 6581 | if (vcpu->mmio_is_write) |
716d51ab GN |
6582 | return 1; |
6583 | vcpu->mmio_read_completed = 1; | |
6584 | return complete_emulated_io(vcpu); | |
6585 | } | |
87da7e66 | 6586 | |
716d51ab GN |
6587 | run->exit_reason = KVM_EXIT_MMIO; |
6588 | run->mmio.phys_addr = frag->gpa; | |
6589 | if (vcpu->mmio_is_write) | |
87da7e66 XG |
6590 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); |
6591 | run->mmio.len = min(8u, frag->len); | |
716d51ab GN |
6592 | run->mmio.is_write = vcpu->mmio_is_write; |
6593 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; | |
6594 | return 0; | |
5287f194 AK |
6595 | } |
6596 | ||
716d51ab | 6597 | |
b6c7a5dc HB |
6598 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
6599 | { | |
c5bedc68 | 6600 | struct fpu *fpu = ¤t->thread.fpu; |
b6c7a5dc HB |
6601 | int r; |
6602 | sigset_t sigsaved; | |
6603 | ||
db2b1d3a | 6604 | if (!fpu->fpstate_active && fpstate_alloc_init(fpu)) |
e5c30142 AK |
6605 | return -ENOMEM; |
6606 | ||
ac9f6dc0 AK |
6607 | if (vcpu->sigset_active) |
6608 | sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); | |
6609 | ||
a4535290 | 6610 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
b6c7a5dc | 6611 | kvm_vcpu_block(vcpu); |
66450a21 | 6612 | kvm_apic_accept_events(vcpu); |
d7690175 | 6613 | clear_bit(KVM_REQ_UNHALT, &vcpu->requests); |
ac9f6dc0 AK |
6614 | r = -EAGAIN; |
6615 | goto out; | |
b6c7a5dc HB |
6616 | } |
6617 | ||
b6c7a5dc | 6618 | /* re-sync apic's tpr */ |
eea1cff9 AP |
6619 | if (!irqchip_in_kernel(vcpu->kvm)) { |
6620 | if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { | |
6621 | r = -EINVAL; | |
6622 | goto out; | |
6623 | } | |
6624 | } | |
b6c7a5dc | 6625 | |
716d51ab GN |
6626 | if (unlikely(vcpu->arch.complete_userspace_io)) { |
6627 | int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; | |
6628 | vcpu->arch.complete_userspace_io = NULL; | |
6629 | r = cui(vcpu); | |
6630 | if (r <= 0) | |
6631 | goto out; | |
6632 | } else | |
6633 | WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); | |
5287f194 | 6634 | |
362c698f | 6635 | r = vcpu_run(vcpu); |
b6c7a5dc HB |
6636 | |
6637 | out: | |
f1d86e46 | 6638 | post_kvm_run_save(vcpu); |
b6c7a5dc HB |
6639 | if (vcpu->sigset_active) |
6640 | sigprocmask(SIG_SETMASK, &sigsaved, NULL); | |
6641 | ||
b6c7a5dc HB |
6642 | return r; |
6643 | } | |
6644 | ||
6645 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
6646 | { | |
7ae441ea GN |
6647 | if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { |
6648 | /* | |
6649 | * We are here if userspace calls get_regs() in the middle of | |
6650 | * instruction emulation. Registers state needs to be copied | |
4a969980 | 6651 | * back from emulation context to vcpu. Userspace shouldn't do |
7ae441ea GN |
6652 | * that usually, but some bad designed PV devices (vmware |
6653 | * backdoor interface) need this to work | |
6654 | */ | |
dd856efa | 6655 | emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); |
7ae441ea GN |
6656 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
6657 | } | |
5fdbf976 MT |
6658 | regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); |
6659 | regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
6660 | regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
6661 | regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
6662 | regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
6663 | regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
6664 | regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
6665 | regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); | |
b6c7a5dc | 6666 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
6667 | regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); |
6668 | regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); | |
6669 | regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); | |
6670 | regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); | |
6671 | regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); | |
6672 | regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); | |
6673 | regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); | |
6674 | regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); | |
b6c7a5dc HB |
6675 | #endif |
6676 | ||
5fdbf976 | 6677 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 6678 | regs->rflags = kvm_get_rflags(vcpu); |
b6c7a5dc | 6679 | |
b6c7a5dc HB |
6680 | return 0; |
6681 | } | |
6682 | ||
6683 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
6684 | { | |
7ae441ea GN |
6685 | vcpu->arch.emulate_regs_need_sync_from_vcpu = true; |
6686 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; | |
6687 | ||
5fdbf976 MT |
6688 | kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); |
6689 | kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); | |
6690 | kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); | |
6691 | kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); | |
6692 | kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); | |
6693 | kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); | |
6694 | kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); | |
6695 | kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); | |
b6c7a5dc | 6696 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
6697 | kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); |
6698 | kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); | |
6699 | kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); | |
6700 | kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); | |
6701 | kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); | |
6702 | kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); | |
6703 | kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); | |
6704 | kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); | |
b6c7a5dc HB |
6705 | #endif |
6706 | ||
5fdbf976 | 6707 | kvm_rip_write(vcpu, regs->rip); |
91586a3b | 6708 | kvm_set_rflags(vcpu, regs->rflags); |
b6c7a5dc | 6709 | |
b4f14abd JK |
6710 | vcpu->arch.exception.pending = false; |
6711 | ||
3842d135 AK |
6712 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
6713 | ||
b6c7a5dc HB |
6714 | return 0; |
6715 | } | |
6716 | ||
b6c7a5dc HB |
6717 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
6718 | { | |
6719 | struct kvm_segment cs; | |
6720 | ||
3e6e0aab | 6721 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
6722 | *db = cs.db; |
6723 | *l = cs.l; | |
6724 | } | |
6725 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
6726 | ||
6727 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, | |
6728 | struct kvm_sregs *sregs) | |
6729 | { | |
89a27f4d | 6730 | struct desc_ptr dt; |
b6c7a5dc | 6731 | |
3e6e0aab GT |
6732 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
6733 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
6734 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
6735 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
6736 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
6737 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 6738 | |
3e6e0aab GT |
6739 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
6740 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc HB |
6741 | |
6742 | kvm_x86_ops->get_idt(vcpu, &dt); | |
89a27f4d GN |
6743 | sregs->idt.limit = dt.size; |
6744 | sregs->idt.base = dt.address; | |
b6c7a5dc | 6745 | kvm_x86_ops->get_gdt(vcpu, &dt); |
89a27f4d GN |
6746 | sregs->gdt.limit = dt.size; |
6747 | sregs->gdt.base = dt.address; | |
b6c7a5dc | 6748 | |
4d4ec087 | 6749 | sregs->cr0 = kvm_read_cr0(vcpu); |
ad312c7c | 6750 | sregs->cr2 = vcpu->arch.cr2; |
9f8fe504 | 6751 | sregs->cr3 = kvm_read_cr3(vcpu); |
fc78f519 | 6752 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 6753 | sregs->cr8 = kvm_get_cr8(vcpu); |
f6801dff | 6754 | sregs->efer = vcpu->arch.efer; |
b6c7a5dc HB |
6755 | sregs->apic_base = kvm_get_apic_base(vcpu); |
6756 | ||
923c61bb | 6757 | memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); |
b6c7a5dc | 6758 | |
36752c9b | 6759 | if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
6760 | set_bit(vcpu->arch.interrupt.nr, |
6761 | (unsigned long *)sregs->interrupt_bitmap); | |
16d7a191 | 6762 | |
b6c7a5dc HB |
6763 | return 0; |
6764 | } | |
6765 | ||
62d9f0db MT |
6766 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
6767 | struct kvm_mp_state *mp_state) | |
6768 | { | |
66450a21 | 6769 | kvm_apic_accept_events(vcpu); |
6aef266c SV |
6770 | if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && |
6771 | vcpu->arch.pv.pv_unhalted) | |
6772 | mp_state->mp_state = KVM_MP_STATE_RUNNABLE; | |
6773 | else | |
6774 | mp_state->mp_state = vcpu->arch.mp_state; | |
6775 | ||
62d9f0db MT |
6776 | return 0; |
6777 | } | |
6778 | ||
6779 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
6780 | struct kvm_mp_state *mp_state) | |
6781 | { | |
66450a21 JK |
6782 | if (!kvm_vcpu_has_lapic(vcpu) && |
6783 | mp_state->mp_state != KVM_MP_STATE_RUNNABLE) | |
6784 | return -EINVAL; | |
6785 | ||
6786 | if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { | |
6787 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
6788 | set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); | |
6789 | } else | |
6790 | vcpu->arch.mp_state = mp_state->mp_state; | |
3842d135 | 6791 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
62d9f0db MT |
6792 | return 0; |
6793 | } | |
6794 | ||
7f3d35fd KW |
6795 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
6796 | int reason, bool has_error_code, u32 error_code) | |
b6c7a5dc | 6797 | { |
9d74191a | 6798 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
8ec4722d | 6799 | int ret; |
e01c2426 | 6800 | |
8ec4722d | 6801 | init_emulate_ctxt(vcpu); |
c697518a | 6802 | |
7f3d35fd | 6803 | ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, |
9d74191a | 6804 | has_error_code, error_code); |
c697518a | 6805 | |
c697518a | 6806 | if (ret) |
19d04437 | 6807 | return EMULATE_FAIL; |
37817f29 | 6808 | |
9d74191a TY |
6809 | kvm_rip_write(vcpu, ctxt->eip); |
6810 | kvm_set_rflags(vcpu, ctxt->eflags); | |
3842d135 | 6811 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
19d04437 | 6812 | return EMULATE_DONE; |
37817f29 IE |
6813 | } |
6814 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
6815 | ||
b6c7a5dc HB |
6816 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, |
6817 | struct kvm_sregs *sregs) | |
6818 | { | |
58cb628d | 6819 | struct msr_data apic_base_msr; |
b6c7a5dc | 6820 | int mmu_reset_needed = 0; |
63f42e02 | 6821 | int pending_vec, max_bits, idx; |
89a27f4d | 6822 | struct desc_ptr dt; |
b6c7a5dc | 6823 | |
6d1068b3 PM |
6824 | if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE)) |
6825 | return -EINVAL; | |
6826 | ||
89a27f4d GN |
6827 | dt.size = sregs->idt.limit; |
6828 | dt.address = sregs->idt.base; | |
b6c7a5dc | 6829 | kvm_x86_ops->set_idt(vcpu, &dt); |
89a27f4d GN |
6830 | dt.size = sregs->gdt.limit; |
6831 | dt.address = sregs->gdt.base; | |
b6c7a5dc HB |
6832 | kvm_x86_ops->set_gdt(vcpu, &dt); |
6833 | ||
ad312c7c | 6834 | vcpu->arch.cr2 = sregs->cr2; |
9f8fe504 | 6835 | mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; |
dc7e795e | 6836 | vcpu->arch.cr3 = sregs->cr3; |
aff48baa | 6837 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); |
b6c7a5dc | 6838 | |
2d3ad1f4 | 6839 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 6840 | |
f6801dff | 6841 | mmu_reset_needed |= vcpu->arch.efer != sregs->efer; |
b6c7a5dc | 6842 | kvm_x86_ops->set_efer(vcpu, sregs->efer); |
58cb628d JK |
6843 | apic_base_msr.data = sregs->apic_base; |
6844 | apic_base_msr.host_initiated = true; | |
6845 | kvm_set_apic_base(vcpu, &apic_base_msr); | |
b6c7a5dc | 6846 | |
4d4ec087 | 6847 | mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
b6c7a5dc | 6848 | kvm_x86_ops->set_cr0(vcpu, sregs->cr0); |
d7306163 | 6849 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 6850 | |
fc78f519 | 6851 | mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
b6c7a5dc | 6852 | kvm_x86_ops->set_cr4(vcpu, sregs->cr4); |
3ea3aa8c | 6853 | if (sregs->cr4 & X86_CR4_OSXSAVE) |
00b27a3e | 6854 | kvm_update_cpuid(vcpu); |
63f42e02 XG |
6855 | |
6856 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
7c93be44 | 6857 | if (!is_long_mode(vcpu) && is_pae(vcpu)) { |
9f8fe504 | 6858 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
7c93be44 MT |
6859 | mmu_reset_needed = 1; |
6860 | } | |
63f42e02 | 6861 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b6c7a5dc HB |
6862 | |
6863 | if (mmu_reset_needed) | |
6864 | kvm_mmu_reset_context(vcpu); | |
6865 | ||
a50abc3b | 6866 | max_bits = KVM_NR_INTERRUPTS; |
923c61bb GN |
6867 | pending_vec = find_first_bit( |
6868 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
6869 | if (pending_vec < max_bits) { | |
66fd3f7f | 6870 | kvm_queue_interrupt(vcpu, pending_vec, false); |
923c61bb | 6871 | pr_debug("Set back pending irq %d\n", pending_vec); |
b6c7a5dc HB |
6872 | } |
6873 | ||
3e6e0aab GT |
6874 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
6875 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
6876 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
6877 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
6878 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
6879 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 6880 | |
3e6e0aab GT |
6881 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
6882 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 6883 | |
5f0269f5 ME |
6884 | update_cr8_intercept(vcpu); |
6885 | ||
9c3e4aab | 6886 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 6887 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 6888 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
3eeb3288 | 6889 | !is_protmode(vcpu)) |
9c3e4aab MT |
6890 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
6891 | ||
3842d135 AK |
6892 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
6893 | ||
b6c7a5dc HB |
6894 | return 0; |
6895 | } | |
6896 | ||
d0bfb940 JK |
6897 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
6898 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 6899 | { |
355be0b9 | 6900 | unsigned long rflags; |
ae675ef0 | 6901 | int i, r; |
b6c7a5dc | 6902 | |
4f926bf2 JK |
6903 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
6904 | r = -EBUSY; | |
6905 | if (vcpu->arch.exception.pending) | |
2122ff5e | 6906 | goto out; |
4f926bf2 JK |
6907 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
6908 | kvm_queue_exception(vcpu, DB_VECTOR); | |
6909 | else | |
6910 | kvm_queue_exception(vcpu, BP_VECTOR); | |
6911 | } | |
6912 | ||
91586a3b JK |
6913 | /* |
6914 | * Read rflags as long as potentially injected trace flags are still | |
6915 | * filtered out. | |
6916 | */ | |
6917 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
6918 | |
6919 | vcpu->guest_debug = dbg->control; | |
6920 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
6921 | vcpu->guest_debug = 0; | |
6922 | ||
6923 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
6924 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
6925 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
c8639010 | 6926 | vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; |
ae675ef0 JK |
6927 | } else { |
6928 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
6929 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
ae675ef0 | 6930 | } |
c8639010 | 6931 | kvm_update_dr7(vcpu); |
ae675ef0 | 6932 | |
f92653ee JK |
6933 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
6934 | vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + | |
6935 | get_segment_base(vcpu, VCPU_SREG_CS); | |
94fe45da | 6936 | |
91586a3b JK |
6937 | /* |
6938 | * Trigger an rflags update that will inject or remove the trace | |
6939 | * flags. | |
6940 | */ | |
6941 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 6942 | |
c8639010 | 6943 | kvm_x86_ops->update_db_bp_intercept(vcpu); |
b6c7a5dc | 6944 | |
4f926bf2 | 6945 | r = 0; |
d0bfb940 | 6946 | |
2122ff5e | 6947 | out: |
b6c7a5dc HB |
6948 | |
6949 | return r; | |
6950 | } | |
6951 | ||
8b006791 ZX |
6952 | /* |
6953 | * Translate a guest virtual address to a guest physical address. | |
6954 | */ | |
6955 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
6956 | struct kvm_translation *tr) | |
6957 | { | |
6958 | unsigned long vaddr = tr->linear_address; | |
6959 | gpa_t gpa; | |
f656ce01 | 6960 | int idx; |
8b006791 | 6961 | |
f656ce01 | 6962 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1871c602 | 6963 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); |
f656ce01 | 6964 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 ZX |
6965 | tr->physical_address = gpa; |
6966 | tr->valid = gpa != UNMAPPED_GVA; | |
6967 | tr->writeable = 1; | |
6968 | tr->usermode = 0; | |
8b006791 ZX |
6969 | |
6970 | return 0; | |
6971 | } | |
6972 | ||
d0752060 HB |
6973 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
6974 | { | |
98918833 SY |
6975 | struct i387_fxsave_struct *fxsave = |
6976 | &vcpu->arch.guest_fpu.state->fxsave; | |
d0752060 | 6977 | |
d0752060 HB |
6978 | memcpy(fpu->fpr, fxsave->st_space, 128); |
6979 | fpu->fcw = fxsave->cwd; | |
6980 | fpu->fsw = fxsave->swd; | |
6981 | fpu->ftwx = fxsave->twd; | |
6982 | fpu->last_opcode = fxsave->fop; | |
6983 | fpu->last_ip = fxsave->rip; | |
6984 | fpu->last_dp = fxsave->rdp; | |
6985 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); | |
6986 | ||
d0752060 HB |
6987 | return 0; |
6988 | } | |
6989 | ||
6990 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
6991 | { | |
98918833 SY |
6992 | struct i387_fxsave_struct *fxsave = |
6993 | &vcpu->arch.guest_fpu.state->fxsave; | |
d0752060 | 6994 | |
d0752060 HB |
6995 | memcpy(fxsave->st_space, fpu->fpr, 128); |
6996 | fxsave->cwd = fpu->fcw; | |
6997 | fxsave->swd = fpu->fsw; | |
6998 | fxsave->twd = fpu->ftwx; | |
6999 | fxsave->fop = fpu->last_opcode; | |
7000 | fxsave->rip = fpu->last_ip; | |
7001 | fxsave->rdp = fpu->last_dp; | |
7002 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); | |
7003 | ||
d0752060 HB |
7004 | return 0; |
7005 | } | |
7006 | ||
10ab25cd | 7007 | int fx_init(struct kvm_vcpu *vcpu) |
d0752060 | 7008 | { |
10ab25cd JK |
7009 | int err; |
7010 | ||
ed97b085 | 7011 | err = fpstate_alloc(&vcpu->arch.guest_fpu); |
10ab25cd JK |
7012 | if (err) |
7013 | return err; | |
7014 | ||
c0ee2cf6 | 7015 | fpstate_init(&vcpu->arch.guest_fpu); |
df1daba7 PB |
7016 | if (cpu_has_xsaves) |
7017 | vcpu->arch.guest_fpu.state->xsave.xsave_hdr.xcomp_bv = | |
7018 | host_xcr0 | XSTATE_COMPACTION_ENABLED; | |
d0752060 | 7019 | |
2acf923e DC |
7020 | /* |
7021 | * Ensure guest xcr0 is valid for loading | |
7022 | */ | |
7023 | vcpu->arch.xcr0 = XSTATE_FP; | |
7024 | ||
ad312c7c | 7025 | vcpu->arch.cr0 |= X86_CR0_ET; |
10ab25cd JK |
7026 | |
7027 | return 0; | |
d0752060 HB |
7028 | } |
7029 | EXPORT_SYMBOL_GPL(fx_init); | |
7030 | ||
98918833 SY |
7031 | static void fx_free(struct kvm_vcpu *vcpu) |
7032 | { | |
a7c2a833 | 7033 | fpstate_free(&vcpu->arch.guest_fpu); |
98918833 SY |
7034 | } |
7035 | ||
d0752060 HB |
7036 | void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) |
7037 | { | |
2608d7a1 | 7038 | if (vcpu->guest_fpu_loaded) |
d0752060 HB |
7039 | return; |
7040 | ||
2acf923e DC |
7041 | /* |
7042 | * Restore all possible states in the guest, | |
7043 | * and assume host would use all available bits. | |
7044 | * Guest xcr0 would be loaded later. | |
7045 | */ | |
7046 | kvm_put_guest_xcr0(vcpu); | |
d0752060 | 7047 | vcpu->guest_fpu_loaded = 1; |
b1a74bf8 | 7048 | __kernel_fpu_begin(); |
98918833 | 7049 | fpu_restore_checking(&vcpu->arch.guest_fpu); |
0c04851c | 7050 | trace_kvm_fpu(1); |
d0752060 | 7051 | } |
d0752060 HB |
7052 | |
7053 | void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
7054 | { | |
2acf923e DC |
7055 | kvm_put_guest_xcr0(vcpu); |
7056 | ||
d0752060 HB |
7057 | if (!vcpu->guest_fpu_loaded) |
7058 | return; | |
7059 | ||
7060 | vcpu->guest_fpu_loaded = 0; | |
98918833 | 7061 | fpu_save_init(&vcpu->arch.guest_fpu); |
b1a74bf8 | 7062 | __kernel_fpu_end(); |
f096ed85 | 7063 | ++vcpu->stat.fpu_reload; |
a8eeb04a | 7064 | kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu); |
0c04851c | 7065 | trace_kvm_fpu(0); |
d0752060 | 7066 | } |
e9b11c17 ZX |
7067 | |
7068 | void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) | |
7069 | { | |
12f9a48f | 7070 | kvmclock_reset(vcpu); |
7f1ea208 | 7071 | |
f5f48ee1 | 7072 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); |
98918833 | 7073 | fx_free(vcpu); |
e9b11c17 ZX |
7074 | kvm_x86_ops->vcpu_free(vcpu); |
7075 | } | |
7076 | ||
7077 | struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, | |
7078 | unsigned int id) | |
7079 | { | |
6755bae8 ZA |
7080 | if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) |
7081 | printk_once(KERN_WARNING | |
7082 | "kvm: SMP vm created on host with unstable TSC; " | |
7083 | "guest TSC will not be reliable\n"); | |
26e5215f AK |
7084 | return kvm_x86_ops->vcpu_create(kvm, id); |
7085 | } | |
e9b11c17 | 7086 | |
26e5215f AK |
7087 | int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) |
7088 | { | |
7089 | int r; | |
e9b11c17 | 7090 | |
0bed3b56 | 7091 | vcpu->arch.mtrr_state.have_fixed = 1; |
9fc77441 MT |
7092 | r = vcpu_load(vcpu); |
7093 | if (r) | |
7094 | return r; | |
57f252f2 | 7095 | kvm_vcpu_reset(vcpu); |
8a3c1a33 | 7096 | kvm_mmu_setup(vcpu); |
e9b11c17 | 7097 | vcpu_put(vcpu); |
e9b11c17 | 7098 | |
26e5215f | 7099 | return r; |
e9b11c17 ZX |
7100 | } |
7101 | ||
31928aa5 | 7102 | void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) |
42897d86 | 7103 | { |
8fe8ab46 | 7104 | struct msr_data msr; |
332967a3 | 7105 | struct kvm *kvm = vcpu->kvm; |
42897d86 | 7106 | |
31928aa5 DD |
7107 | if (vcpu_load(vcpu)) |
7108 | return; | |
8fe8ab46 WA |
7109 | msr.data = 0x0; |
7110 | msr.index = MSR_IA32_TSC; | |
7111 | msr.host_initiated = true; | |
7112 | kvm_write_tsc(vcpu, &msr); | |
42897d86 MT |
7113 | vcpu_put(vcpu); |
7114 | ||
332967a3 AJ |
7115 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, |
7116 | KVMCLOCK_SYNC_PERIOD); | |
42897d86 MT |
7117 | } |
7118 | ||
d40ccc62 | 7119 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 | 7120 | { |
9fc77441 | 7121 | int r; |
344d9588 GN |
7122 | vcpu->arch.apf.msr_val = 0; |
7123 | ||
9fc77441 MT |
7124 | r = vcpu_load(vcpu); |
7125 | BUG_ON(r); | |
e9b11c17 ZX |
7126 | kvm_mmu_unload(vcpu); |
7127 | vcpu_put(vcpu); | |
7128 | ||
98918833 | 7129 | fx_free(vcpu); |
e9b11c17 ZX |
7130 | kvm_x86_ops->vcpu_free(vcpu); |
7131 | } | |
7132 | ||
66450a21 | 7133 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu) |
e9b11c17 | 7134 | { |
7460fb4a AK |
7135 | atomic_set(&vcpu->arch.nmi_queued, 0); |
7136 | vcpu->arch.nmi_pending = 0; | |
448fa4a9 | 7137 | vcpu->arch.nmi_injected = false; |
5f7552d4 NA |
7138 | kvm_clear_interrupt_queue(vcpu); |
7139 | kvm_clear_exception_queue(vcpu); | |
448fa4a9 | 7140 | |
42dbaa5a | 7141 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); |
ae561ede | 7142 | kvm_update_dr0123(vcpu); |
6f43ed01 | 7143 | vcpu->arch.dr6 = DR6_INIT; |
73aaf249 | 7144 | kvm_update_dr6(vcpu); |
42dbaa5a | 7145 | vcpu->arch.dr7 = DR7_FIXED_1; |
c8639010 | 7146 | kvm_update_dr7(vcpu); |
42dbaa5a | 7147 | |
1119022c NA |
7148 | vcpu->arch.cr2 = 0; |
7149 | ||
3842d135 | 7150 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
344d9588 | 7151 | vcpu->arch.apf.msr_val = 0; |
c9aaa895 | 7152 | vcpu->arch.st.msr_val = 0; |
3842d135 | 7153 | |
12f9a48f GC |
7154 | kvmclock_reset(vcpu); |
7155 | ||
af585b92 GN |
7156 | kvm_clear_async_pf_completion_queue(vcpu); |
7157 | kvm_async_pf_hash_reset(vcpu); | |
7158 | vcpu->arch.apf.halted = false; | |
3842d135 | 7159 | |
f5132b01 GN |
7160 | kvm_pmu_reset(vcpu); |
7161 | ||
66f7b72e JS |
7162 | memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); |
7163 | vcpu->arch.regs_avail = ~0; | |
7164 | vcpu->arch.regs_dirty = ~0; | |
7165 | ||
57f252f2 | 7166 | kvm_x86_ops->vcpu_reset(vcpu); |
e9b11c17 ZX |
7167 | } |
7168 | ||
2b4a273b | 7169 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) |
66450a21 JK |
7170 | { |
7171 | struct kvm_segment cs; | |
7172 | ||
7173 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
7174 | cs.selector = vector << 8; | |
7175 | cs.base = vector << 12; | |
7176 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
7177 | kvm_rip_write(vcpu, 0); | |
e9b11c17 ZX |
7178 | } |
7179 | ||
13a34e06 | 7180 | int kvm_arch_hardware_enable(void) |
e9b11c17 | 7181 | { |
ca84d1a2 ZA |
7182 | struct kvm *kvm; |
7183 | struct kvm_vcpu *vcpu; | |
7184 | int i; | |
0dd6a6ed ZA |
7185 | int ret; |
7186 | u64 local_tsc; | |
7187 | u64 max_tsc = 0; | |
7188 | bool stable, backwards_tsc = false; | |
18863bdd AK |
7189 | |
7190 | kvm_shared_msr_cpu_online(); | |
13a34e06 | 7191 | ret = kvm_x86_ops->hardware_enable(); |
0dd6a6ed ZA |
7192 | if (ret != 0) |
7193 | return ret; | |
7194 | ||
7195 | local_tsc = native_read_tsc(); | |
7196 | stable = !check_tsc_unstable(); | |
7197 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
7198 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
7199 | if (!stable && vcpu->cpu == smp_processor_id()) | |
105b21bb | 7200 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
7201 | if (stable && vcpu->arch.last_host_tsc > local_tsc) { |
7202 | backwards_tsc = true; | |
7203 | if (vcpu->arch.last_host_tsc > max_tsc) | |
7204 | max_tsc = vcpu->arch.last_host_tsc; | |
7205 | } | |
7206 | } | |
7207 | } | |
7208 | ||
7209 | /* | |
7210 | * Sometimes, even reliable TSCs go backwards. This happens on | |
7211 | * platforms that reset TSC during suspend or hibernate actions, but | |
7212 | * maintain synchronization. We must compensate. Fortunately, we can | |
7213 | * detect that condition here, which happens early in CPU bringup, | |
7214 | * before any KVM threads can be running. Unfortunately, we can't | |
7215 | * bring the TSCs fully up to date with real time, as we aren't yet far | |
7216 | * enough into CPU bringup that we know how much real time has actually | |
7217 | * elapsed; our helper function, get_kernel_ns() will be using boot | |
7218 | * variables that haven't been updated yet. | |
7219 | * | |
7220 | * So we simply find the maximum observed TSC above, then record the | |
7221 | * adjustment to TSC in each VCPU. When the VCPU later gets loaded, | |
7222 | * the adjustment will be applied. Note that we accumulate | |
7223 | * adjustments, in case multiple suspend cycles happen before some VCPU | |
7224 | * gets a chance to run again. In the event that no KVM threads get a | |
7225 | * chance to run, we will miss the entire elapsed period, as we'll have | |
7226 | * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may | |
7227 | * loose cycle time. This isn't too big a deal, since the loss will be | |
7228 | * uniform across all VCPUs (not to mention the scenario is extremely | |
7229 | * unlikely). It is possible that a second hibernate recovery happens | |
7230 | * much faster than a first, causing the observed TSC here to be | |
7231 | * smaller; this would require additional padding adjustment, which is | |
7232 | * why we set last_host_tsc to the local tsc observed here. | |
7233 | * | |
7234 | * N.B. - this code below runs only on platforms with reliable TSC, | |
7235 | * as that is the only way backwards_tsc is set above. Also note | |
7236 | * that this runs for ALL vcpus, which is not a bug; all VCPUs should | |
7237 | * have the same delta_cyc adjustment applied if backwards_tsc | |
7238 | * is detected. Note further, this adjustment is only done once, | |
7239 | * as we reset last_host_tsc on all VCPUs to stop this from being | |
7240 | * called multiple times (one for each physical CPU bringup). | |
7241 | * | |
4a969980 | 7242 | * Platforms with unreliable TSCs don't have to deal with this, they |
0dd6a6ed ZA |
7243 | * will be compensated by the logic in vcpu_load, which sets the TSC to |
7244 | * catchup mode. This will catchup all VCPUs to real time, but cannot | |
7245 | * guarantee that they stay in perfect synchronization. | |
7246 | */ | |
7247 | if (backwards_tsc) { | |
7248 | u64 delta_cyc = max_tsc - local_tsc; | |
16a96021 | 7249 | backwards_tsc_observed = true; |
0dd6a6ed ZA |
7250 | list_for_each_entry(kvm, &vm_list, vm_list) { |
7251 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
7252 | vcpu->arch.tsc_offset_adjustment += delta_cyc; | |
7253 | vcpu->arch.last_host_tsc = local_tsc; | |
105b21bb | 7254 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
7255 | } |
7256 | ||
7257 | /* | |
7258 | * We have to disable TSC offset matching.. if you were | |
7259 | * booting a VM while issuing an S4 host suspend.... | |
7260 | * you may have some problem. Solving this issue is | |
7261 | * left as an exercise to the reader. | |
7262 | */ | |
7263 | kvm->arch.last_tsc_nsec = 0; | |
7264 | kvm->arch.last_tsc_write = 0; | |
7265 | } | |
7266 | ||
7267 | } | |
7268 | return 0; | |
e9b11c17 ZX |
7269 | } |
7270 | ||
13a34e06 | 7271 | void kvm_arch_hardware_disable(void) |
e9b11c17 | 7272 | { |
13a34e06 RK |
7273 | kvm_x86_ops->hardware_disable(); |
7274 | drop_user_return_notifiers(); | |
e9b11c17 ZX |
7275 | } |
7276 | ||
7277 | int kvm_arch_hardware_setup(void) | |
7278 | { | |
9e9c3fe4 NA |
7279 | int r; |
7280 | ||
7281 | r = kvm_x86_ops->hardware_setup(); | |
7282 | if (r != 0) | |
7283 | return r; | |
7284 | ||
7285 | kvm_init_msr_list(); | |
7286 | return 0; | |
e9b11c17 ZX |
7287 | } |
7288 | ||
7289 | void kvm_arch_hardware_unsetup(void) | |
7290 | { | |
7291 | kvm_x86_ops->hardware_unsetup(); | |
7292 | } | |
7293 | ||
7294 | void kvm_arch_check_processor_compat(void *rtn) | |
7295 | { | |
7296 | kvm_x86_ops->check_processor_compatibility(rtn); | |
7297 | } | |
7298 | ||
3e515705 AK |
7299 | bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu) |
7300 | { | |
7301 | return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL); | |
7302 | } | |
7303 | ||
54e9818f GN |
7304 | struct static_key kvm_no_apic_vcpu __read_mostly; |
7305 | ||
e9b11c17 ZX |
7306 | int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) |
7307 | { | |
7308 | struct page *page; | |
7309 | struct kvm *kvm; | |
7310 | int r; | |
7311 | ||
7312 | BUG_ON(vcpu->kvm == NULL); | |
7313 | kvm = vcpu->kvm; | |
7314 | ||
6aef266c | 7315 | vcpu->arch.pv.pv_unhalted = false; |
9aabc88f | 7316 | vcpu->arch.emulate_ctxt.ops = &emulate_ops; |
58d269d8 | 7317 | if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu)) |
a4535290 | 7318 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
e9b11c17 | 7319 | else |
a4535290 | 7320 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; |
e9b11c17 ZX |
7321 | |
7322 | page = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
7323 | if (!page) { | |
7324 | r = -ENOMEM; | |
7325 | goto fail; | |
7326 | } | |
ad312c7c | 7327 | vcpu->arch.pio_data = page_address(page); |
e9b11c17 | 7328 | |
cc578287 | 7329 | kvm_set_tsc_khz(vcpu, max_tsc_khz); |
c285545f | 7330 | |
e9b11c17 ZX |
7331 | r = kvm_mmu_create(vcpu); |
7332 | if (r < 0) | |
7333 | goto fail_free_pio_data; | |
7334 | ||
7335 | if (irqchip_in_kernel(kvm)) { | |
7336 | r = kvm_create_lapic(vcpu); | |
7337 | if (r < 0) | |
7338 | goto fail_mmu_destroy; | |
54e9818f GN |
7339 | } else |
7340 | static_key_slow_inc(&kvm_no_apic_vcpu); | |
e9b11c17 | 7341 | |
890ca9ae HY |
7342 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, |
7343 | GFP_KERNEL); | |
7344 | if (!vcpu->arch.mce_banks) { | |
7345 | r = -ENOMEM; | |
443c39bc | 7346 | goto fail_free_lapic; |
890ca9ae HY |
7347 | } |
7348 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
7349 | ||
f1797359 WY |
7350 | if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) { |
7351 | r = -ENOMEM; | |
f5f48ee1 | 7352 | goto fail_free_mce_banks; |
f1797359 | 7353 | } |
f5f48ee1 | 7354 | |
66f7b72e JS |
7355 | r = fx_init(vcpu); |
7356 | if (r) | |
7357 | goto fail_free_wbinvd_dirty_mask; | |
7358 | ||
ba904635 | 7359 | vcpu->arch.ia32_tsc_adjust_msr = 0x0; |
0b79459b | 7360 | vcpu->arch.pv_time_enabled = false; |
d7876f1b PB |
7361 | |
7362 | vcpu->arch.guest_supported_xcr0 = 0; | |
4344ee98 | 7363 | vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; |
d7876f1b | 7364 | |
5a4f55cd EK |
7365 | vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); |
7366 | ||
af585b92 | 7367 | kvm_async_pf_hash_reset(vcpu); |
f5132b01 | 7368 | kvm_pmu_init(vcpu); |
af585b92 | 7369 | |
e9b11c17 | 7370 | return 0; |
66f7b72e JS |
7371 | fail_free_wbinvd_dirty_mask: |
7372 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); | |
f5f48ee1 SY |
7373 | fail_free_mce_banks: |
7374 | kfree(vcpu->arch.mce_banks); | |
443c39bc WY |
7375 | fail_free_lapic: |
7376 | kvm_free_lapic(vcpu); | |
e9b11c17 ZX |
7377 | fail_mmu_destroy: |
7378 | kvm_mmu_destroy(vcpu); | |
7379 | fail_free_pio_data: | |
ad312c7c | 7380 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 ZX |
7381 | fail: |
7382 | return r; | |
7383 | } | |
7384 | ||
7385 | void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) | |
7386 | { | |
f656ce01 MT |
7387 | int idx; |
7388 | ||
f5132b01 | 7389 | kvm_pmu_destroy(vcpu); |
36cb93fd | 7390 | kfree(vcpu->arch.mce_banks); |
e9b11c17 | 7391 | kvm_free_lapic(vcpu); |
f656ce01 | 7392 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
e9b11c17 | 7393 | kvm_mmu_destroy(vcpu); |
f656ce01 | 7394 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
ad312c7c | 7395 | free_page((unsigned long)vcpu->arch.pio_data); |
54e9818f GN |
7396 | if (!irqchip_in_kernel(vcpu->kvm)) |
7397 | static_key_slow_dec(&kvm_no_apic_vcpu); | |
e9b11c17 | 7398 | } |
d19a9cd2 | 7399 | |
e790d9ef RK |
7400 | void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) |
7401 | { | |
ae97a3b8 | 7402 | kvm_x86_ops->sched_in(vcpu, cpu); |
e790d9ef RK |
7403 | } |
7404 | ||
e08b9637 | 7405 | int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) |
d19a9cd2 | 7406 | { |
e08b9637 CO |
7407 | if (type) |
7408 | return -EINVAL; | |
7409 | ||
6ef768fa | 7410 | INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); |
f05e70ac | 7411 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
365c8868 | 7412 | INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); |
4d5c5d0f | 7413 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
e0f0bbc5 | 7414 | atomic_set(&kvm->arch.noncoherent_dma_count, 0); |
d19a9cd2 | 7415 | |
5550af4d SY |
7416 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
7417 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
7a84428a AW |
7418 | /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ |
7419 | set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, | |
7420 | &kvm->arch.irq_sources_bitmap); | |
5550af4d | 7421 | |
038f8c11 | 7422 | raw_spin_lock_init(&kvm->arch.tsc_write_lock); |
1e08ec4a | 7423 | mutex_init(&kvm->arch.apic_map_lock); |
d828199e MT |
7424 | spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); |
7425 | ||
7426 | pvclock_update_vm_gtod_copy(kvm); | |
53f658b3 | 7427 | |
7e44e449 | 7428 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); |
332967a3 | 7429 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); |
7e44e449 | 7430 | |
d89f5eff | 7431 | return 0; |
d19a9cd2 ZX |
7432 | } |
7433 | ||
7434 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) | |
7435 | { | |
9fc77441 MT |
7436 | int r; |
7437 | r = vcpu_load(vcpu); | |
7438 | BUG_ON(r); | |
d19a9cd2 ZX |
7439 | kvm_mmu_unload(vcpu); |
7440 | vcpu_put(vcpu); | |
7441 | } | |
7442 | ||
7443 | static void kvm_free_vcpus(struct kvm *kvm) | |
7444 | { | |
7445 | unsigned int i; | |
988a2cae | 7446 | struct kvm_vcpu *vcpu; |
d19a9cd2 ZX |
7447 | |
7448 | /* | |
7449 | * Unpin any mmu pages first. | |
7450 | */ | |
af585b92 GN |
7451 | kvm_for_each_vcpu(i, vcpu, kvm) { |
7452 | kvm_clear_async_pf_completion_queue(vcpu); | |
988a2cae | 7453 | kvm_unload_vcpu_mmu(vcpu); |
af585b92 | 7454 | } |
988a2cae GN |
7455 | kvm_for_each_vcpu(i, vcpu, kvm) |
7456 | kvm_arch_vcpu_free(vcpu); | |
7457 | ||
7458 | mutex_lock(&kvm->lock); | |
7459 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
7460 | kvm->vcpus[i] = NULL; | |
d19a9cd2 | 7461 | |
988a2cae GN |
7462 | atomic_set(&kvm->online_vcpus, 0); |
7463 | mutex_unlock(&kvm->lock); | |
d19a9cd2 ZX |
7464 | } |
7465 | ||
ad8ba2cd SY |
7466 | void kvm_arch_sync_events(struct kvm *kvm) |
7467 | { | |
332967a3 | 7468 | cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); |
7e44e449 | 7469 | cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); |
ba4cef31 | 7470 | kvm_free_all_assigned_devices(kvm); |
aea924f6 | 7471 | kvm_free_pit(kvm); |
ad8ba2cd SY |
7472 | } |
7473 | ||
d19a9cd2 ZX |
7474 | void kvm_arch_destroy_vm(struct kvm *kvm) |
7475 | { | |
27469d29 AH |
7476 | if (current->mm == kvm->mm) { |
7477 | /* | |
7478 | * Free memory regions allocated on behalf of userspace, | |
7479 | * unless the the memory map has changed due to process exit | |
7480 | * or fd copying. | |
7481 | */ | |
7482 | struct kvm_userspace_memory_region mem; | |
7483 | memset(&mem, 0, sizeof(mem)); | |
7484 | mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT; | |
7485 | kvm_set_memory_region(kvm, &mem); | |
7486 | ||
7487 | mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT; | |
7488 | kvm_set_memory_region(kvm, &mem); | |
7489 | ||
7490 | mem.slot = TSS_PRIVATE_MEMSLOT; | |
7491 | kvm_set_memory_region(kvm, &mem); | |
7492 | } | |
6eb55818 | 7493 | kvm_iommu_unmap_guest(kvm); |
d7deeeb0 ZX |
7494 | kfree(kvm->arch.vpic); |
7495 | kfree(kvm->arch.vioapic); | |
d19a9cd2 | 7496 | kvm_free_vcpus(kvm); |
1e08ec4a | 7497 | kfree(rcu_dereference_check(kvm->arch.apic_map, 1)); |
d19a9cd2 | 7498 | } |
0de10343 | 7499 | |
5587027c | 7500 | void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, |
db3fe4eb TY |
7501 | struct kvm_memory_slot *dont) |
7502 | { | |
7503 | int i; | |
7504 | ||
d89cc617 TY |
7505 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
7506 | if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { | |
548ef284 | 7507 | kvfree(free->arch.rmap[i]); |
d89cc617 | 7508 | free->arch.rmap[i] = NULL; |
77d11309 | 7509 | } |
d89cc617 TY |
7510 | if (i == 0) |
7511 | continue; | |
7512 | ||
7513 | if (!dont || free->arch.lpage_info[i - 1] != | |
7514 | dont->arch.lpage_info[i - 1]) { | |
548ef284 | 7515 | kvfree(free->arch.lpage_info[i - 1]); |
d89cc617 | 7516 | free->arch.lpage_info[i - 1] = NULL; |
db3fe4eb TY |
7517 | } |
7518 | } | |
7519 | } | |
7520 | ||
5587027c AK |
7521 | int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, |
7522 | unsigned long npages) | |
db3fe4eb TY |
7523 | { |
7524 | int i; | |
7525 | ||
d89cc617 | 7526 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
db3fe4eb TY |
7527 | unsigned long ugfn; |
7528 | int lpages; | |
d89cc617 | 7529 | int level = i + 1; |
db3fe4eb TY |
7530 | |
7531 | lpages = gfn_to_index(slot->base_gfn + npages - 1, | |
7532 | slot->base_gfn, level) + 1; | |
7533 | ||
d89cc617 TY |
7534 | slot->arch.rmap[i] = |
7535 | kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i])); | |
7536 | if (!slot->arch.rmap[i]) | |
77d11309 | 7537 | goto out_free; |
d89cc617 TY |
7538 | if (i == 0) |
7539 | continue; | |
77d11309 | 7540 | |
d89cc617 TY |
7541 | slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages * |
7542 | sizeof(*slot->arch.lpage_info[i - 1])); | |
7543 | if (!slot->arch.lpage_info[i - 1]) | |
db3fe4eb TY |
7544 | goto out_free; |
7545 | ||
7546 | if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) | |
d89cc617 | 7547 | slot->arch.lpage_info[i - 1][0].write_count = 1; |
db3fe4eb | 7548 | if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) |
d89cc617 | 7549 | slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1; |
db3fe4eb TY |
7550 | ugfn = slot->userspace_addr >> PAGE_SHIFT; |
7551 | /* | |
7552 | * If the gfn and userspace address are not aligned wrt each | |
7553 | * other, or if explicitly asked to, disable large page | |
7554 | * support for this slot | |
7555 | */ | |
7556 | if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || | |
7557 | !kvm_largepages_enabled()) { | |
7558 | unsigned long j; | |
7559 | ||
7560 | for (j = 0; j < lpages; ++j) | |
d89cc617 | 7561 | slot->arch.lpage_info[i - 1][j].write_count = 1; |
db3fe4eb TY |
7562 | } |
7563 | } | |
7564 | ||
7565 | return 0; | |
7566 | ||
7567 | out_free: | |
d89cc617 | 7568 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
548ef284 | 7569 | kvfree(slot->arch.rmap[i]); |
d89cc617 TY |
7570 | slot->arch.rmap[i] = NULL; |
7571 | if (i == 0) | |
7572 | continue; | |
7573 | ||
548ef284 | 7574 | kvfree(slot->arch.lpage_info[i - 1]); |
d89cc617 | 7575 | slot->arch.lpage_info[i - 1] = NULL; |
db3fe4eb TY |
7576 | } |
7577 | return -ENOMEM; | |
7578 | } | |
7579 | ||
e59dbe09 TY |
7580 | void kvm_arch_memslots_updated(struct kvm *kvm) |
7581 | { | |
e6dff7d1 TY |
7582 | /* |
7583 | * memslots->generation has been incremented. | |
7584 | * mmio generation may have reached its maximum value. | |
7585 | */ | |
7586 | kvm_mmu_invalidate_mmio_sptes(kvm); | |
e59dbe09 TY |
7587 | } |
7588 | ||
f7784b8e MT |
7589 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
7590 | struct kvm_memory_slot *memslot, | |
f7784b8e | 7591 | struct kvm_userspace_memory_region *mem, |
7b6195a9 | 7592 | enum kvm_mr_change change) |
0de10343 | 7593 | { |
7a905b14 TY |
7594 | /* |
7595 | * Only private memory slots need to be mapped here since | |
7596 | * KVM_SET_MEMORY_REGION ioctl is no longer supported. | |
0de10343 | 7597 | */ |
7b6195a9 | 7598 | if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) { |
7a905b14 | 7599 | unsigned long userspace_addr; |
604b38ac | 7600 | |
7a905b14 TY |
7601 | /* |
7602 | * MAP_SHARED to prevent internal slot pages from being moved | |
7603 | * by fork()/COW. | |
7604 | */ | |
7b6195a9 | 7605 | userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE, |
7a905b14 TY |
7606 | PROT_READ | PROT_WRITE, |
7607 | MAP_SHARED | MAP_ANONYMOUS, 0); | |
0de10343 | 7608 | |
7a905b14 TY |
7609 | if (IS_ERR((void *)userspace_addr)) |
7610 | return PTR_ERR((void *)userspace_addr); | |
604b38ac | 7611 | |
7a905b14 | 7612 | memslot->userspace_addr = userspace_addr; |
0de10343 ZX |
7613 | } |
7614 | ||
f7784b8e MT |
7615 | return 0; |
7616 | } | |
7617 | ||
88178fd4 KH |
7618 | static void kvm_mmu_slot_apply_flags(struct kvm *kvm, |
7619 | struct kvm_memory_slot *new) | |
7620 | { | |
7621 | /* Still write protect RO slot */ | |
7622 | if (new->flags & KVM_MEM_READONLY) { | |
7623 | kvm_mmu_slot_remove_write_access(kvm, new); | |
7624 | return; | |
7625 | } | |
7626 | ||
7627 | /* | |
7628 | * Call kvm_x86_ops dirty logging hooks when they are valid. | |
7629 | * | |
7630 | * kvm_x86_ops->slot_disable_log_dirty is called when: | |
7631 | * | |
7632 | * - KVM_MR_CREATE with dirty logging is disabled | |
7633 | * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag | |
7634 | * | |
7635 | * The reason is, in case of PML, we need to set D-bit for any slots | |
7636 | * with dirty logging disabled in order to eliminate unnecessary GPA | |
7637 | * logging in PML buffer (and potential PML buffer full VMEXT). This | |
7638 | * guarantees leaving PML enabled during guest's lifetime won't have | |
7639 | * any additonal overhead from PML when guest is running with dirty | |
7640 | * logging disabled for memory slots. | |
7641 | * | |
7642 | * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot | |
7643 | * to dirty logging mode. | |
7644 | * | |
7645 | * If kvm_x86_ops dirty logging hooks are invalid, use write protect. | |
7646 | * | |
7647 | * In case of write protect: | |
7648 | * | |
7649 | * Write protect all pages for dirty logging. | |
7650 | * | |
7651 | * All the sptes including the large sptes which point to this | |
7652 | * slot are set to readonly. We can not create any new large | |
7653 | * spte on this slot until the end of the logging. | |
7654 | * | |
7655 | * See the comments in fast_page_fault(). | |
7656 | */ | |
7657 | if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { | |
7658 | if (kvm_x86_ops->slot_enable_log_dirty) | |
7659 | kvm_x86_ops->slot_enable_log_dirty(kvm, new); | |
7660 | else | |
7661 | kvm_mmu_slot_remove_write_access(kvm, new); | |
7662 | } else { | |
7663 | if (kvm_x86_ops->slot_disable_log_dirty) | |
7664 | kvm_x86_ops->slot_disable_log_dirty(kvm, new); | |
7665 | } | |
7666 | } | |
7667 | ||
f7784b8e MT |
7668 | void kvm_arch_commit_memory_region(struct kvm *kvm, |
7669 | struct kvm_userspace_memory_region *mem, | |
8482644a TY |
7670 | const struct kvm_memory_slot *old, |
7671 | enum kvm_mr_change change) | |
f7784b8e | 7672 | { |
1c91cad4 | 7673 | struct kvm_memory_slot *new; |
8482644a | 7674 | int nr_mmu_pages = 0; |
f7784b8e | 7675 | |
8482644a | 7676 | if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) { |
f7784b8e MT |
7677 | int ret; |
7678 | ||
8482644a TY |
7679 | ret = vm_munmap(old->userspace_addr, |
7680 | old->npages * PAGE_SIZE); | |
f7784b8e MT |
7681 | if (ret < 0) |
7682 | printk(KERN_WARNING | |
7683 | "kvm_vm_ioctl_set_memory_region: " | |
7684 | "failed to munmap memory\n"); | |
7685 | } | |
7686 | ||
48c0e4e9 XG |
7687 | if (!kvm->arch.n_requested_mmu_pages) |
7688 | nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); | |
7689 | ||
48c0e4e9 | 7690 | if (nr_mmu_pages) |
0de10343 | 7691 | kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); |
1c91cad4 KH |
7692 | |
7693 | /* It's OK to get 'new' slot here as it has already been installed */ | |
7694 | new = id_to_memslot(kvm->memslots, mem->slot); | |
7695 | ||
3ea3b7fa WL |
7696 | /* |
7697 | * Dirty logging tracks sptes in 4k granularity, meaning that large | |
7698 | * sptes have to be split. If live migration is successful, the guest | |
7699 | * in the source machine will be destroyed and large sptes will be | |
7700 | * created in the destination. However, if the guest continues to run | |
7701 | * in the source machine (for example if live migration fails), small | |
7702 | * sptes will remain around and cause bad performance. | |
7703 | * | |
7704 | * Scan sptes if dirty logging has been stopped, dropping those | |
7705 | * which can be collapsed into a single large-page spte. Later | |
7706 | * page faults will create the large-page sptes. | |
7707 | */ | |
7708 | if ((change != KVM_MR_DELETE) && | |
7709 | (old->flags & KVM_MEM_LOG_DIRTY_PAGES) && | |
7710 | !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) | |
7711 | kvm_mmu_zap_collapsible_sptes(kvm, new); | |
7712 | ||
c972f3b1 | 7713 | /* |
88178fd4 | 7714 | * Set up write protection and/or dirty logging for the new slot. |
c126d94f | 7715 | * |
88178fd4 KH |
7716 | * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have |
7717 | * been zapped so no dirty logging staff is needed for old slot. For | |
7718 | * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the | |
7719 | * new and it's also covered when dealing with the new slot. | |
c972f3b1 | 7720 | */ |
88178fd4 KH |
7721 | if (change != KVM_MR_DELETE) |
7722 | kvm_mmu_slot_apply_flags(kvm, new); | |
0de10343 | 7723 | } |
1d737c8a | 7724 | |
2df72e9b | 7725 | void kvm_arch_flush_shadow_all(struct kvm *kvm) |
34d4cb8f | 7726 | { |
6ca18b69 | 7727 | kvm_mmu_invalidate_zap_all_pages(kvm); |
34d4cb8f MT |
7728 | } |
7729 | ||
2df72e9b MT |
7730 | void kvm_arch_flush_shadow_memslot(struct kvm *kvm, |
7731 | struct kvm_memory_slot *slot) | |
7732 | { | |
6ca18b69 | 7733 | kvm_mmu_invalidate_zap_all_pages(kvm); |
2df72e9b MT |
7734 | } |
7735 | ||
1d737c8a ZX |
7736 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
7737 | { | |
b6b8a145 JK |
7738 | if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) |
7739 | kvm_x86_ops->check_nested_events(vcpu, false); | |
7740 | ||
af585b92 GN |
7741 | return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
7742 | !vcpu->arch.apf.halted) | |
7743 | || !list_empty_careful(&vcpu->async_pf.done) | |
66450a21 | 7744 | || kvm_apic_has_events(vcpu) |
6aef266c | 7745 | || vcpu->arch.pv.pv_unhalted |
7460fb4a | 7746 | || atomic_read(&vcpu->arch.nmi_queued) || |
a1b37100 GN |
7747 | (kvm_arch_interrupt_allowed(vcpu) && |
7748 | kvm_cpu_has_interrupt(vcpu)); | |
1d737c8a | 7749 | } |
5736199a | 7750 | |
b6d33834 | 7751 | int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) |
5736199a | 7752 | { |
b6d33834 | 7753 | return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; |
5736199a | 7754 | } |
78646121 GN |
7755 | |
7756 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
7757 | { | |
7758 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
7759 | } | |
229456fc | 7760 | |
82b32774 | 7761 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) |
f92653ee | 7762 | { |
82b32774 NA |
7763 | if (is_64_bit_mode(vcpu)) |
7764 | return kvm_rip_read(vcpu); | |
7765 | return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + | |
7766 | kvm_rip_read(vcpu)); | |
7767 | } | |
7768 | EXPORT_SYMBOL_GPL(kvm_get_linear_rip); | |
f92653ee | 7769 | |
82b32774 NA |
7770 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) |
7771 | { | |
7772 | return kvm_get_linear_rip(vcpu) == linear_rip; | |
f92653ee JK |
7773 | } |
7774 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
7775 | ||
94fe45da JK |
7776 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
7777 | { | |
7778 | unsigned long rflags; | |
7779 | ||
7780 | rflags = kvm_x86_ops->get_rflags(vcpu); | |
7781 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
c310bac5 | 7782 | rflags &= ~X86_EFLAGS_TF; |
94fe45da JK |
7783 | return rflags; |
7784 | } | |
7785 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
7786 | ||
6addfc42 | 7787 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) |
94fe45da JK |
7788 | { |
7789 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
f92653ee | 7790 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) |
c310bac5 | 7791 | rflags |= X86_EFLAGS_TF; |
94fe45da | 7792 | kvm_x86_ops->set_rflags(vcpu, rflags); |
6addfc42 PB |
7793 | } |
7794 | ||
7795 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
7796 | { | |
7797 | __kvm_set_rflags(vcpu, rflags); | |
3842d135 | 7798 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
94fe45da JK |
7799 | } |
7800 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
7801 | ||
56028d08 GN |
7802 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) |
7803 | { | |
7804 | int r; | |
7805 | ||
fb67e14f | 7806 | if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) || |
f2e10669 | 7807 | work->wakeup_all) |
56028d08 GN |
7808 | return; |
7809 | ||
7810 | r = kvm_mmu_reload(vcpu); | |
7811 | if (unlikely(r)) | |
7812 | return; | |
7813 | ||
fb67e14f XG |
7814 | if (!vcpu->arch.mmu.direct_map && |
7815 | work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu)) | |
7816 | return; | |
7817 | ||
56028d08 GN |
7818 | vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); |
7819 | } | |
7820 | ||
af585b92 GN |
7821 | static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) |
7822 | { | |
7823 | return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); | |
7824 | } | |
7825 | ||
7826 | static inline u32 kvm_async_pf_next_probe(u32 key) | |
7827 | { | |
7828 | return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); | |
7829 | } | |
7830 | ||
7831 | static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
7832 | { | |
7833 | u32 key = kvm_async_pf_hash_fn(gfn); | |
7834 | ||
7835 | while (vcpu->arch.apf.gfns[key] != ~0) | |
7836 | key = kvm_async_pf_next_probe(key); | |
7837 | ||
7838 | vcpu->arch.apf.gfns[key] = gfn; | |
7839 | } | |
7840 | ||
7841 | static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) | |
7842 | { | |
7843 | int i; | |
7844 | u32 key = kvm_async_pf_hash_fn(gfn); | |
7845 | ||
7846 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && | |
c7d28c24 XG |
7847 | (vcpu->arch.apf.gfns[key] != gfn && |
7848 | vcpu->arch.apf.gfns[key] != ~0); i++) | |
af585b92 GN |
7849 | key = kvm_async_pf_next_probe(key); |
7850 | ||
7851 | return key; | |
7852 | } | |
7853 | ||
7854 | bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
7855 | { | |
7856 | return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; | |
7857 | } | |
7858 | ||
7859 | static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
7860 | { | |
7861 | u32 i, j, k; | |
7862 | ||
7863 | i = j = kvm_async_pf_gfn_slot(vcpu, gfn); | |
7864 | while (true) { | |
7865 | vcpu->arch.apf.gfns[i] = ~0; | |
7866 | do { | |
7867 | j = kvm_async_pf_next_probe(j); | |
7868 | if (vcpu->arch.apf.gfns[j] == ~0) | |
7869 | return; | |
7870 | k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); | |
7871 | /* | |
7872 | * k lies cyclically in ]i,j] | |
7873 | * | i.k.j | | |
7874 | * |....j i.k.| or |.k..j i...| | |
7875 | */ | |
7876 | } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); | |
7877 | vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; | |
7878 | i = j; | |
7879 | } | |
7880 | } | |
7881 | ||
7c90705b GN |
7882 | static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) |
7883 | { | |
7884 | ||
7885 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, | |
7886 | sizeof(val)); | |
7887 | } | |
7888 | ||
af585b92 GN |
7889 | void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
7890 | struct kvm_async_pf *work) | |
7891 | { | |
6389ee94 AK |
7892 | struct x86_exception fault; |
7893 | ||
7c90705b | 7894 | trace_kvm_async_pf_not_present(work->arch.token, work->gva); |
af585b92 | 7895 | kvm_add_async_pf_gfn(vcpu, work->arch.gfn); |
7c90705b GN |
7896 | |
7897 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || | |
fc5f06fa GN |
7898 | (vcpu->arch.apf.send_user_only && |
7899 | kvm_x86_ops->get_cpl(vcpu) == 0)) | |
7c90705b GN |
7900 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); |
7901 | else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { | |
6389ee94 AK |
7902 | fault.vector = PF_VECTOR; |
7903 | fault.error_code_valid = true; | |
7904 | fault.error_code = 0; | |
7905 | fault.nested_page_fault = false; | |
7906 | fault.address = work->arch.token; | |
7907 | kvm_inject_page_fault(vcpu, &fault); | |
7c90705b | 7908 | } |
af585b92 GN |
7909 | } |
7910 | ||
7911 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
7912 | struct kvm_async_pf *work) | |
7913 | { | |
6389ee94 AK |
7914 | struct x86_exception fault; |
7915 | ||
7c90705b | 7916 | trace_kvm_async_pf_ready(work->arch.token, work->gva); |
f2e10669 | 7917 | if (work->wakeup_all) |
7c90705b GN |
7918 | work->arch.token = ~0; /* broadcast wakeup */ |
7919 | else | |
7920 | kvm_del_async_pf_gfn(vcpu, work->arch.gfn); | |
7921 | ||
7922 | if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) && | |
7923 | !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { | |
6389ee94 AK |
7924 | fault.vector = PF_VECTOR; |
7925 | fault.error_code_valid = true; | |
7926 | fault.error_code = 0; | |
7927 | fault.nested_page_fault = false; | |
7928 | fault.address = work->arch.token; | |
7929 | kvm_inject_page_fault(vcpu, &fault); | |
7c90705b | 7930 | } |
e6d53e3b | 7931 | vcpu->arch.apf.halted = false; |
a4fa1635 | 7932 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
7c90705b GN |
7933 | } |
7934 | ||
7935 | bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) | |
7936 | { | |
7937 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) | |
7938 | return true; | |
7939 | else | |
7940 | return !kvm_event_needs_reinjection(vcpu) && | |
7941 | kvm_x86_ops->interrupt_allowed(vcpu); | |
af585b92 GN |
7942 | } |
7943 | ||
e0f0bbc5 AW |
7944 | void kvm_arch_register_noncoherent_dma(struct kvm *kvm) |
7945 | { | |
7946 | atomic_inc(&kvm->arch.noncoherent_dma_count); | |
7947 | } | |
7948 | EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); | |
7949 | ||
7950 | void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) | |
7951 | { | |
7952 | atomic_dec(&kvm->arch.noncoherent_dma_count); | |
7953 | } | |
7954 | EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); | |
7955 | ||
7956 | bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) | |
7957 | { | |
7958 | return atomic_read(&kvm->arch.noncoherent_dma_count); | |
7959 | } | |
7960 | EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); | |
7961 | ||
229456fc MT |
7962 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
7963 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); | |
7964 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
7965 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
7966 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
0ac406de | 7967 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); |
d8cabddf | 7968 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 7969 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 7970 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
ec1ff790 | 7971 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 7972 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |
2e554e8d | 7973 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); |
489223ed | 7974 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); |
7b46268d | 7975 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window); |
843e4330 | 7976 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); |