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iommu/core: Convert iommu_found to iommu_present
[mirror_ubuntu-hirsute-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
af585b92 46#include <linux/hash.h>
a1b60c1c 47#include <linux/pci.h>
aec51dc4 48#include <trace/events/kvm.h>
2ed152af 49
229456fc
MT		 50#define CREATE_TRACE_POINTS
51#include "trace.h"
043405e1 52
24f1e32c 53#include <asm/debugreg.h>
d825ed0a 54#include <asm/msr.h>
a5f61300 55#include <asm/desc.h>
0bed3b56 56#include <asm/mtrr.h>
890ca9ae 57#include <asm/mce.h>
7cf30855 58#include <asm/i387.h>
98918833 59#include <asm/xcr.h>
1d5f066e 60#include <asm/pvclock.h>
217fc9cf 61#include <asm/div64.h>
043405e1 62
313a3dc7 63#define MAX_IO_MSRS 256
890ca9ae 64#define KVM_MAX_MCE_BANKS 32
5854dbca 65#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 66
0f65dd70
AK		 67#define emul_to_vcpu(ctxt) \
68 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
69
50a37eb4
JR		 70/* EFER defaults:
71 * - enable syscall per default because its emulated by KVM
72 * - enable LME and LMA per default on 64 bit KVM
73 */
74#ifdef CONFIG_X86_64
1260edbe
LJ		 75static
76u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 77#else
1260edbe 78static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 79#endif
313a3dc7 80
ba1389b7
AK		 81#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
82#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 83
cb142eb7 84static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 85static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
86 struct kvm_cpuid_entry2 __user *entries);
87
97896d04 88struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 89EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 90
ed85c068
AP		 91int ignore_msrs = 0;
92module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
93
92a1f12d
JR		 94bool kvm_has_tsc_control;
95EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
96u32 kvm_max_guest_tsc_khz;
97EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
98
18863bdd
AK		 99#define KVM_NR_SHARED_MSRS 16
100
101struct kvm_shared_msrs_global {
102 int nr;
2bf78fa7 103 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 104};
105
106struct kvm_shared_msrs {
107 struct user_return_notifier urn;
108 bool registered;
2bf78fa7
SY		 109 struct kvm_shared_msr_values {
110 u64 host;
111 u64 curr;
112 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 113};
114
115static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
116static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
117
417bc304 118struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 119 { "pf_fixed", VCPU_STAT(pf_fixed) },
120 { "pf_guest", VCPU_STAT(pf_guest) },
121 { "tlb_flush", VCPU_STAT(tlb_flush) },
122 { "invlpg", VCPU_STAT(invlpg) },
123 { "exits", VCPU_STAT(exits) },
124 { "io_exits", VCPU_STAT(io_exits) },
125 { "mmio_exits", VCPU_STAT(mmio_exits) },
126 { "signal_exits", VCPU_STAT(signal_exits) },
127 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 128 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 129 { "halt_exits", VCPU_STAT(halt_exits) },
130 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 131 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 132 { "request_irq", VCPU_STAT(request_irq_exits) },
133 { "irq_exits", VCPU_STAT(irq_exits) },
134 { "host_state_reload", VCPU_STAT(host_state_reload) },
135 { "efer_reload", VCPU_STAT(efer_reload) },
136 { "fpu_reload", VCPU_STAT(fpu_reload) },
137 { "insn_emulation", VCPU_STAT(insn_emulation) },
138 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 139 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 140 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 141 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
142 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
143 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
144 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
145 { "mmu_flooded", VM_STAT(mmu_flooded) },
146 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 147 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 148 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 149 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 150 { "largepages", VM_STAT(lpages) },
417bc304
HB		 151 { NULL }
152};
153
2acf923e
DC		 154u64 __read_mostly host_xcr0;
155
d6aa1000
AK		 156int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
157
af585b92
GN		 158static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
159{
160 int i;
161 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
162 vcpu->arch.apf.gfns[i] = ~0;
163}
164
18863bdd
AK		 165static void kvm_on_user_return(struct user_return_notifier *urn)
166{
167 unsigned slot;
18863bdd
AK		 168 struct kvm_shared_msrs *locals
169 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 170 struct kvm_shared_msr_values *values;
18863bdd
AK		 171
172 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 173 values = &locals->values[slot];
174 if (values->host != values->curr) {
175 wrmsrl(shared_msrs_global.msrs[slot], values->host);
176 values->curr = values->host;
18863bdd
AK		 177 }
178 }
179 locals->registered = false;
180 user_return_notifier_unregister(urn);
181}
182
2bf78fa7 183static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 184{
2bf78fa7 185 struct kvm_shared_msrs *smsr;
18863bdd
AK		 186 u64 value;
187
2bf78fa7
SY		 188 smsr = &__get_cpu_var(shared_msrs);
189 /* only read, and nobody should modify it at this time,
190 * so don't need lock */
191 if (slot >= shared_msrs_global.nr) {
192 printk(KERN_ERR "kvm: invalid MSR slot!");
193 return;
194 }
195 rdmsrl_safe(msr, &value);
196 smsr->values[slot].host = value;
197 smsr->values[slot].curr = value;
198}
199
200void kvm_define_shared_msr(unsigned slot, u32 msr)
201{
18863bdd
AK		 202 if (slot >= shared_msrs_global.nr)
203 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 204 shared_msrs_global.msrs[slot] = msr;
205 /* we need ensured the shared_msr_global have been updated */
206 smp_wmb();
18863bdd
AK		 207}
208EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
209
210static void kvm_shared_msr_cpu_online(void)
211{
212 unsigned i;
18863bdd
AK		 213
214 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 215 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 216}
217
d5696725 218void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 219{
220 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
221
2bf78fa7 222 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 223 return;
2bf78fa7
SY		 224 smsr->values[slot].curr = value;
225 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 226 if (!smsr->registered) {
227 smsr->urn.on_user_return = kvm_on_user_return;
228 user_return_notifier_register(&smsr->urn);
229 smsr->registered = true;
230 }
231}
232EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
233
3548bab5
AK		 234static void drop_user_return_notifiers(void *ignore)
235{
236 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
237
238 if (smsr->registered)
239 kvm_on_user_return(&smsr->urn);
240}
241
6866b83e
CO		 242u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
243{
244 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 245 return vcpu->arch.apic_base;
6866b83e 246 else
ad312c7c 247 return vcpu->arch.apic_base;
6866b83e
CO		 248}
249EXPORT_SYMBOL_GPL(kvm_get_apic_base);
250
251void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
252{
253 /* TODO: reserve bits check */
254 if (irqchip_in_kernel(vcpu->kvm))
255 kvm_lapic_set_base(vcpu, data);
256 else
ad312c7c 257 vcpu->arch.apic_base = data;
6866b83e
CO		 258}
259EXPORT_SYMBOL_GPL(kvm_set_apic_base);
260
3fd28fce
ED		 261#define EXCPT_BENIGN 0
262#define EXCPT_CONTRIBUTORY 1
263#define EXCPT_PF 2
264
265static int exception_class(int vector)
266{
267 switch (vector) {
268 case PF_VECTOR:
269 return EXCPT_PF;
270 case DE_VECTOR:
271 case TS_VECTOR:
272 case NP_VECTOR:
273 case SS_VECTOR:
274 case GP_VECTOR:
275 return EXCPT_CONTRIBUTORY;
276 default:
277 break;
278 }
279 return EXCPT_BENIGN;
280}
281
282static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 283 unsigned nr, bool has_error, u32 error_code,
284 bool reinject)
3fd28fce
ED		 285{
286 u32 prev_nr;
287 int class1, class2;
288
3842d135
AK		 289 kvm_make_request(KVM_REQ_EVENT, vcpu);
290
3fd28fce
ED		 291 if (!vcpu->arch.exception.pending) {
292 queue:
293 vcpu->arch.exception.pending = true;
294 vcpu->arch.exception.has_error_code = has_error;
295 vcpu->arch.exception.nr = nr;
296 vcpu->arch.exception.error_code = error_code;
3f0fd292 297 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 298 return;
299 }
300
301 /* to check exception */
302 prev_nr = vcpu->arch.exception.nr;
303 if (prev_nr == DF_VECTOR) {
304 /* triple fault -> shutdown */
a8eeb04a 305 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 306 return;
307 }
308 class1 = exception_class(prev_nr);
309 class2 = exception_class(nr);
310 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
311 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
312 /* generate double fault per SDM Table 5-5 */
313 vcpu->arch.exception.pending = true;
314 vcpu->arch.exception.has_error_code = true;
315 vcpu->arch.exception.nr = DF_VECTOR;
316 vcpu->arch.exception.error_code = 0;
317 } else
318 /* replace previous exception with a new one in a hope
319 that instruction re-execution will regenerate lost
320 exception */
321 goto queue;
322}
323
298101da
AK		 324void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
325{
ce7ddec4 326 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 327}
328EXPORT_SYMBOL_GPL(kvm_queue_exception);
329
ce7ddec4
JR		 330void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
331{
332 kvm_multiple_exception(vcpu, nr, false, 0, true);
333}
334EXPORT_SYMBOL_GPL(kvm_requeue_exception);
335
db8fcefa 336void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 337{
db8fcefa
AP		 338 if (err)
339 kvm_inject_gp(vcpu, 0);
340 else
341 kvm_x86_ops->skip_emulated_instruction(vcpu);
342}
343EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 344
6389ee94 345void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 346{
347 ++vcpu->stat.pf_guest;
6389ee94
AK		 348 vcpu->arch.cr2 = fault->address;
349 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 350}
27d6c865 351EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 352
6389ee94 353void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 354{
6389ee94
AK		 355 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
356 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 357 else
6389ee94 358 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 359}
360
3419ffc8
SY		 361void kvm_inject_nmi(struct kvm_vcpu *vcpu)
362{
3842d135 363 kvm_make_request(KVM_REQ_EVENT, vcpu);
c761e586 364 vcpu->arch.nmi_pending = 1;
3419ffc8
SY		 365}
366EXPORT_SYMBOL_GPL(kvm_inject_nmi);
367
298101da
AK		 368void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
369{
ce7ddec4 370 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 371}
372EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
373
ce7ddec4
JR		 374void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
375{
376 kvm_multiple_exception(vcpu, nr, true, error_code, true);
377}
378EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
379
0a79b009
AK		 380/*
381 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
382 * a #GP and return false.
383 */
384bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 385{
0a79b009
AK		 386 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
387 return true;
388 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
389 return false;
298101da 390}
0a79b009 391EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 392
ec92fe44
JR		 393/*
394 * This function will be used to read from the physical memory of the currently
395 * running guest. The difference to kvm_read_guest_page is that this function
396 * can read from guest physical or from the guest's guest physical memory.
397 */
398int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
399 gfn_t ngfn, void *data, int offset, int len,
400 u32 access)
401{
402 gfn_t real_gfn;
403 gpa_t ngpa;
404
405 ngpa = gfn_to_gpa(ngfn);
406 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
407 if (real_gfn == UNMAPPED_GVA)
408 return -EFAULT;
409
410 real_gfn = gpa_to_gfn(real_gfn);
411
412 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
413}
414EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
415
3d06b8bf
JR		 416int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
417 void *data, int offset, int len, u32 access)
418{
419 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
420 data, offset, len, access);
421}
422
a03490ed
CO		 423/*
424 * Load the pae pdptrs. Return true is they are all valid.
425 */
ff03a073 426int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 427{
428 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
429 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
430 int i;
431 int ret;
ff03a073 432 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 433
ff03a073
JR		 434 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
435 offset * sizeof(u64), sizeof(pdpte),
436 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 437 if (ret < 0) {
438 ret = 0;
439 goto out;
440 }
441 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 442 if (is_present_gpte(pdpte[i]) &&
20c466b5 443 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 444 ret = 0;
445 goto out;
446 }
447 }
448 ret = 1;
449
ff03a073 450 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 451 __set_bit(VCPU_EXREG_PDPTR,
452 (unsigned long *)&vcpu->arch.regs_avail);
453 __set_bit(VCPU_EXREG_PDPTR,
454 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 455out:
a03490ed
CO		 456
457 return ret;
458}
cc4b6871 459EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 460
d835dfec
AK		 461static bool pdptrs_changed(struct kvm_vcpu *vcpu)
462{
ff03a073 463 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 464 bool changed = true;
3d06b8bf
JR		 465 int offset;
466 gfn_t gfn;
d835dfec
AK		 467 int r;
468
469 if (is_long_mode(vcpu) || !is_pae(vcpu))
470 return false;
471
6de4f3ad
AK		 472 if (!test_bit(VCPU_EXREG_PDPTR,
473 (unsigned long *)&vcpu->arch.regs_avail))
474 return true;
475
9f8fe504
AK		 476 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
477 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 478 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
479 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 480 if (r < 0)
481 goto out;
ff03a073 482 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 483out:
d835dfec
AK		 484
485 return changed;
486}
487
49a9b07e 488int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 489{
aad82703
SY		 490 unsigned long old_cr0 = kvm_read_cr0(vcpu);
491 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
492 X86_CR0_CD | X86_CR0_NW;
493
f9a48e6a
AK		 494 cr0 |= X86_CR0_ET;
495
ab344828 496#ifdef CONFIG_X86_64
0f12244f
GN		 497 if (cr0 & 0xffffffff00000000UL)
498 return 1;
ab344828
GN		 499#endif
500
501 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 502
0f12244f
GN		 503 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
504 return 1;
a03490ed 505
0f12244f
GN		 506 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
507 return 1;
a03490ed
CO		 508
509 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
510#ifdef CONFIG_X86_64
f6801dff 511 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 512 int cs_db, cs_l;
513
0f12244f
GN		 514 if (!is_pae(vcpu))
515 return 1;
a03490ed 516 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 517 if (cs_l)
518 return 1;
a03490ed
CO		 519 } else
520#endif
ff03a073 521 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 522 kvm_read_cr3(vcpu)))
0f12244f 523 return 1;
a03490ed
CO		 524 }
525
526 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 527
d170c419 528 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 529 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 530 kvm_async_pf_hash_reset(vcpu);
531 }
e5f3f027 532
aad82703
SY		 533 if ((cr0 ^ old_cr0) & update_bits)
534 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 535 return 0;
536}
2d3ad1f4 537EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 538
2d3ad1f4 539void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 540{
49a9b07e 541 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 542}
2d3ad1f4 543EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 544
2acf923e
DC		 545int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
546{
547 u64 xcr0;
548
549 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
550 if (index != XCR_XFEATURE_ENABLED_MASK)
551 return 1;
552 xcr0 = xcr;
553 if (kvm_x86_ops->get_cpl(vcpu) != 0)
554 return 1;
555 if (!(xcr0 & XSTATE_FP))
556 return 1;
557 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
558 return 1;
559 if (xcr0 & ~host_xcr0)
560 return 1;
561 vcpu->arch.xcr0 = xcr0;
562 vcpu->guest_xcr0_loaded = 0;
563 return 0;
564}
565
566int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
567{
568 if (__kvm_set_xcr(vcpu, index, xcr)) {
569 kvm_inject_gp(vcpu, 0);
570 return 1;
571 }
572 return 0;
573}
574EXPORT_SYMBOL_GPL(kvm_set_xcr);
575
576static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
577{
578 struct kvm_cpuid_entry2 *best;
579
580 best = kvm_find_cpuid_entry(vcpu, 1, 0);
581 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
582}
583
c68b734f
YW		 584static bool guest_cpuid_has_smep(struct kvm_vcpu *vcpu)
585{
586 struct kvm_cpuid_entry2 *best;
587
588 best = kvm_find_cpuid_entry(vcpu, 7, 0);
589 return best && (best->ebx & bit(X86_FEATURE_SMEP));
590}
591
74dc2b4f
YW		 592static bool guest_cpuid_has_fsgsbase(struct kvm_vcpu *vcpu)
593{
594 struct kvm_cpuid_entry2 *best;
595
596 best = kvm_find_cpuid_entry(vcpu, 7, 0);
597 return best && (best->ebx & bit(X86_FEATURE_FSGSBASE));
598}
599
2acf923e
DC		 600static void update_cpuid(struct kvm_vcpu *vcpu)
601{
602 struct kvm_cpuid_entry2 *best;
603
604 best = kvm_find_cpuid_entry(vcpu, 1, 0);
605 if (!best)
606 return;
607
608 /* Update OSXSAVE bit */
609 if (cpu_has_xsave && best->function == 0x1) {
610 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
611 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
612 best->ecx |= bit(X86_FEATURE_OSXSAVE);
613 }
614}
615
a83b29c6 616int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 617{
fc78f519 618 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 619 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
620 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 621 if (cr4 & CR4_RESERVED_BITS)
622 return 1;
a03490ed 623
2acf923e
DC		 624 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
625 return 1;
626
c68b734f
YW		 627 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
628 return 1;
629
74dc2b4f
YW		 630 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
631 return 1;
632
a03490ed 633 if (is_long_mode(vcpu)) {
0f12244f
GN		 634 if (!(cr4 & X86_CR4_PAE))
635 return 1;
a2edf57f
AK		 636 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
637 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 638 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
639 kvm_read_cr3(vcpu)))
0f12244f
GN		 640 return 1;
641
5e1746d6 642 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 643 return 1;
a03490ed 644
aad82703
SY		 645 if ((cr4 ^ old_cr4) & pdptr_bits)
646 kvm_mmu_reset_context(vcpu);
0f12244f 647
2acf923e
DC		 648 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
649 update_cpuid(vcpu);
650
0f12244f
GN		 651 return 0;
652}
2d3ad1f4 653EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 654
2390218b 655int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 656{
9f8fe504 657 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 658 kvm_mmu_sync_roots(vcpu);
d835dfec 659 kvm_mmu_flush_tlb(vcpu);
0f12244f 660 return 0;
d835dfec
AK		 661 }
662
a03490ed 663 if (is_long_mode(vcpu)) {
0f12244f
GN		 664 if (cr3 & CR3_L_MODE_RESERVED_BITS)
665 return 1;
a03490ed
CO		 666 } else {
667 if (is_pae(vcpu)) {
0f12244f
GN		 668 if (cr3 & CR3_PAE_RESERVED_BITS)
669 return 1;
ff03a073
JR		 670 if (is_paging(vcpu) &&
671 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 672 return 1;
a03490ed
CO		 673 }
674 /*
675 * We don't check reserved bits in nonpae mode, because
676 * this isn't enforced, and VMware depends on this.
677 */
678 }
679
a03490ed
CO		 680 /*
681 * Does the new cr3 value map to physical memory? (Note, we
682 * catch an invalid cr3 even in real-mode, because it would
683 * cause trouble later on when we turn on paging anyway.)
684 *
685 * A real CPU would silently accept an invalid cr3 and would
686 * attempt to use it - with largely undefined (and often hard
687 * to debug) behavior on the guest side.
688 */
689 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 690 return 1;
691 vcpu->arch.cr3 = cr3;
aff48baa 692 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 693 vcpu->arch.mmu.new_cr3(vcpu);
694 return 0;
695}
2d3ad1f4 696EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 697
eea1cff9 698int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 699{
0f12244f
GN		 700 if (cr8 & CR8_RESERVED_BITS)
701 return 1;
a03490ed
CO		 702 if (irqchip_in_kernel(vcpu->kvm))
703 kvm_lapic_set_tpr(vcpu, cr8);
704 else
ad312c7c 705 vcpu->arch.cr8 = cr8;
0f12244f
GN		 706 return 0;
707}
2d3ad1f4 708EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 709
2d3ad1f4 710unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 711{
712 if (irqchip_in_kernel(vcpu->kvm))
713 return kvm_lapic_get_cr8(vcpu);
714 else
ad312c7c 715 return vcpu->arch.cr8;
a03490ed 716}
2d3ad1f4 717EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 718
338dbc97 719static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 720{
721 switch (dr) {
722 case 0 ... 3:
723 vcpu->arch.db[dr] = val;
724 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
725 vcpu->arch.eff_db[dr] = val;
726 break;
727 case 4:
338dbc97
GN		 728 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
729 return 1; /* #UD */
020df079
GN		 730 /* fall through */
731 case 6:
338dbc97
GN		 732 if (val & 0xffffffff00000000ULL)
733 return -1; /* #GP */
020df079
GN		 734 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
735 break;
736 case 5:
338dbc97
GN		 737 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
738 return 1; /* #UD */
020df079
GN		 739 /* fall through */
740 default: /* 7 */
338dbc97
GN		 741 if (val & 0xffffffff00000000ULL)
742 return -1; /* #GP */
020df079
GN		 743 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
744 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
745 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
746 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
747 }
748 break;
749 }
750
751 return 0;
752}
338dbc97
GN		 753
754int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
755{
756 int res;
757
758 res = __kvm_set_dr(vcpu, dr, val);
759 if (res > 0)
760 kvm_queue_exception(vcpu, UD_VECTOR);
761 else if (res < 0)
762 kvm_inject_gp(vcpu, 0);
763
764 return res;
765}
020df079
GN		 766EXPORT_SYMBOL_GPL(kvm_set_dr);
767
338dbc97 768static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 769{
770 switch (dr) {
771 case 0 ... 3:
772 *val = vcpu->arch.db[dr];
773 break;
774 case 4:
338dbc97 775 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 776 return 1;
020df079
GN		 777 /* fall through */
778 case 6:
779 *val = vcpu->arch.dr6;
780 break;
781 case 5:
338dbc97 782 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 783 return 1;
020df079
GN		 784 /* fall through */
785 default: /* 7 */
786 *val = vcpu->arch.dr7;
787 break;
788 }
789
790 return 0;
791}
338dbc97
GN		 792
793int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
794{
795 if (_kvm_get_dr(vcpu, dr, val)) {
796 kvm_queue_exception(vcpu, UD_VECTOR);
797 return 1;
798 }
799 return 0;
800}
020df079
GN		 801EXPORT_SYMBOL_GPL(kvm_get_dr);
802
043405e1
CO		 803/*
804 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
805 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
806 *
807 * This list is modified at module load time to reflect the
e3267cbb
GC		 808 * capabilities of the host cpu. This capabilities test skips MSRs that are
809 * kvm-specific. Those are put in the beginning of the list.
043405e1 810 */
e3267cbb 811
c9aaa895 812#define KVM_SAVE_MSRS_BEGIN 9
043405e1 813static u32 msrs_to_save[] = {
e3267cbb 814 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 815 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 816 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 817 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
043405e1 818 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 819 MSR_STAR,
043405e1
CO		 820#ifdef CONFIG_X86_64
821 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
822#endif
e90aa41e 823 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 824};
825
826static unsigned num_msrs_to_save;
827
828static u32 emulated_msrs[] = {
829 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 830 MSR_IA32_MCG_STATUS,
831 MSR_IA32_MCG_CTL,
043405e1
CO		 832};
833
b69e8cae 834static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 835{
aad82703
SY		 836 u64 old_efer = vcpu->arch.efer;
837
b69e8cae
RJ		 838 if (efer & efer_reserved_bits)
839 return 1;
15c4a640
CO		 840
841 if (is_paging(vcpu)
b69e8cae
RJ		 842 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
843 return 1;
15c4a640 844
1b2fd70c
AG		 845 if (efer & EFER_FFXSR) {
846 struct kvm_cpuid_entry2 *feat;
847
848 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 849 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
850 return 1;
1b2fd70c
AG		 851 }
852
d8017474
AG		 853 if (efer & EFER_SVME) {
854 struct kvm_cpuid_entry2 *feat;
855
856 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 857 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
858 return 1;
d8017474
AG		 859 }
860
15c4a640 861 efer &= ~EFER_LMA;
f6801dff 862 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 863
a3d204e2
SY		 864 kvm_x86_ops->set_efer(vcpu, efer);
865
9645bb56 866 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 867
aad82703
SY		 868 /* Update reserved bits */
869 if ((efer ^ old_efer) & EFER_NX)
870 kvm_mmu_reset_context(vcpu);
871
b69e8cae 872 return 0;
15c4a640
CO		 873}
874
f2b4b7dd
JR		 875void kvm_enable_efer_bits(u64 mask)
876{
877 efer_reserved_bits &= ~mask;
878}
879EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
880
881
15c4a640
CO		 882/*
883 * Writes msr value into into the appropriate "register".
884 * Returns 0 on success, non-0 otherwise.
885 * Assumes vcpu_load() was already called.
886 */
887int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
888{
889 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
890}
891
313a3dc7
CO		 892/*
893 * Adapt set_msr() to msr_io()'s calling convention
894 */
895static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
896{
897 return kvm_set_msr(vcpu, index, *data);
898}
899
18068523
GOC		 900static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
901{
9ed3c444
AK		 902 int version;
903 int r;
50d0a0f9 904 struct pvclock_wall_clock wc;
923de3cf 905 struct timespec boot;
18068523
GOC		 906
907 if (!wall_clock)
908 return;
909
9ed3c444
AK		 910 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
911 if (r)
912 return;
913
914 if (version & 1)
915 ++version; /* first time write, random junk */
916
917 ++version;
18068523 918
18068523
GOC		 919 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
920
50d0a0f9
GH		 921 /*
922 * The guest calculates current wall clock time by adding
34c238a1 923 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 924 * wall clock specified here. guest system time equals host
925 * system time for us, thus we must fill in host boot time here.
926 */
923de3cf 927 getboottime(&boot);
50d0a0f9
GH		 928
929 wc.sec = boot.tv_sec;
930 wc.nsec = boot.tv_nsec;
931 wc.version = version;
18068523
GOC		 932
933 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
934
935 version++;
936 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 937}
938
50d0a0f9
GH		 939static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
940{
941 uint32_t quotient, remainder;
942
943 /* Don't try to replace with do_div(), this one calculates
944 * "(dividend << 32) / divisor" */
945 __asm__ ( "divl %4"
946 : "=a" (quotient), "=d" (remainder)
947 : "0" (0), "1" (dividend), "r" (divisor) );
948 return quotient;
949}
950
5f4e3f88
ZA		 951static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
952 s8 *pshift, u32 *pmultiplier)
50d0a0f9 953{
5f4e3f88 954 uint64_t scaled64;
50d0a0f9
GH		 955 int32_t shift = 0;
956 uint64_t tps64;
957 uint32_t tps32;
958
5f4e3f88
ZA		 959 tps64 = base_khz * 1000LL;
960 scaled64 = scaled_khz * 1000LL;
50933623 961 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 962 tps64 >>= 1;
963 shift--;
964 }
965
966 tps32 = (uint32_t)tps64;
50933623
JK		 967 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
968 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 969 scaled64 >>= 1;
970 else
971 tps32 <<= 1;
50d0a0f9
GH		 972 shift++;
973 }
974
5f4e3f88
ZA		 975 *pshift = shift;
976 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 977
5f4e3f88
ZA		 978 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
979 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 980}
981
759379dd
ZA		 982static inline u64 get_kernel_ns(void)
983{
984 struct timespec ts;
985
986 WARN_ON(preemptible());
987 ktime_get_ts(&ts);
988 monotonic_to_bootbased(&ts);
989 return timespec_to_ns(&ts);
50d0a0f9
GH		 990}
991
c8076604 992static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 993unsigned long max_tsc_khz;
c8076604 994
8cfdc000
ZA		 995static inline int kvm_tsc_changes_freq(void)
996{
997 int cpu = get_cpu();
998 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
999 cpufreq_quick_get(cpu) != 0;
1000 put_cpu();
1001 return ret;
1002}
1003
1e993611
JR		 1004static u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu)
1005{
1006 if (vcpu->arch.virtual_tsc_khz)
1007 return vcpu->arch.virtual_tsc_khz;
1008 else
1009 return __this_cpu_read(cpu_tsc_khz);
1010}
1011
857e4099 1012static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
759379dd 1013{
217fc9cf
AK		 1014 u64 ret;
1015
759379dd
ZA		 1016 WARN_ON(preemptible());
1017 if (kvm_tsc_changes_freq())
1018 printk_once(KERN_WARNING
1019 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
857e4099 1020 ret = nsec * vcpu_tsc_khz(vcpu);
217fc9cf
AK		 1021 do_div(ret, USEC_PER_SEC);
1022 return ret;
759379dd
ZA		 1023}
1024
1e993611 1025static void kvm_init_tsc_catchup(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
c285545f
ZA		 1026{
1027 /* Compute a scale to convert nanoseconds in TSC cycles */
1028 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1e993611
JR		 1029 &vcpu->arch.tsc_catchup_shift,
1030 &vcpu->arch.tsc_catchup_mult);
c285545f
ZA		 1031}
1032
1033static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1034{
1035 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
1e993611
JR		 1036 vcpu->arch.tsc_catchup_mult,
1037 vcpu->arch.tsc_catchup_shift);
c285545f
ZA		 1038 tsc += vcpu->arch.last_tsc_write;
1039 return tsc;
1040}
1041
99e3e30a
ZA		 1042void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1043{
1044 struct kvm *kvm = vcpu->kvm;
f38e098f 1045 u64 offset, ns, elapsed;
99e3e30a 1046 unsigned long flags;
46543ba4 1047 s64 sdiff;
99e3e30a 1048
038f8c11 1049 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1050 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1051 ns = get_kernel_ns();
f38e098f 1052 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 1053 sdiff = data - kvm->arch.last_tsc_write;
1054 if (sdiff < 0)
1055 sdiff = -sdiff;
f38e098f
ZA		 1056
1057 /*
46543ba4 1058 * Special case: close write to TSC within 5 seconds of
f38e098f 1059 * another CPU is interpreted as an attempt to synchronize
0d2eb44f 1060 * The 5 seconds is to accommodate host load / swapping as
46543ba4 1061 * well as any reset of TSC during the boot process.
f38e098f
ZA		 1062 *
1063 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 1064 * or make a best guest using elapsed value.
f38e098f 1065 */
857e4099 1066 if (sdiff < nsec_to_cycles(vcpu, 5ULL * NSEC_PER_SEC) &&
46543ba4 1067 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 1068 if (!check_tsc_unstable()) {
1069 offset = kvm->arch.last_tsc_offset;
1070 pr_debug("kvm: matched tsc offset for %llu\n", data);
1071 } else {
857e4099 1072 u64 delta = nsec_to_cycles(vcpu, elapsed);
759379dd
ZA		 1073 offset += delta;
1074 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1075 }
1076 ns = kvm->arch.last_tsc_nsec;
1077 }
1078 kvm->arch.last_tsc_nsec = ns;
1079 kvm->arch.last_tsc_write = data;
1080 kvm->arch.last_tsc_offset = offset;
99e3e30a 1081 kvm_x86_ops->write_tsc_offset(vcpu, offset);
038f8c11 1082 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
99e3e30a
ZA		 1083
1084 /* Reset of TSC must disable overshoot protection below */
1085 vcpu->arch.hv_clock.tsc_timestamp = 0;
c285545f
ZA		 1086 vcpu->arch.last_tsc_write = data;
1087 vcpu->arch.last_tsc_nsec = ns;
99e3e30a
ZA		 1088}
1089EXPORT_SYMBOL_GPL(kvm_write_tsc);
1090
34c238a1 1091static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1092{
18068523
GOC		 1093 unsigned long flags;
1094 struct kvm_vcpu_arch *vcpu = &v->arch;
1095 void *shared_kaddr;
463656c0 1096 unsigned long this_tsc_khz;
1d5f066e
ZA		 1097 s64 kernel_ns, max_kernel_ns;
1098 u64 tsc_timestamp;
18068523 1099
18068523
GOC		 1100 /* Keep irq disabled to prevent changes to the clock */
1101 local_irq_save(flags);
1d5f066e 1102 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
759379dd 1103 kernel_ns = get_kernel_ns();
1e993611 1104 this_tsc_khz = vcpu_tsc_khz(v);
8cfdc000 1105 if (unlikely(this_tsc_khz == 0)) {
c285545f 1106 local_irq_restore(flags);
34c238a1 1107 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1108 return 1;
1109 }
18068523 1110
c285545f
ZA		 1111 /*
1112 * We may have to catch up the TSC to match elapsed wall clock
1113 * time for two reasons, even if kvmclock is used.
1114 * 1) CPU could have been running below the maximum TSC rate
1115 * 2) Broken TSC compensation resets the base at each VCPU
1116 * entry to avoid unknown leaps of TSC even when running
1117 * again on the same CPU. This may cause apparent elapsed
1118 * time to disappear, and the guest to stand still or run
1119 * very slowly.
1120 */
1121 if (vcpu->tsc_catchup) {
1122 u64 tsc = compute_guest_tsc(v, kernel_ns);
1123 if (tsc > tsc_timestamp) {
1124 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1125 tsc_timestamp = tsc;
1126 }
50d0a0f9
GH		 1127 }
1128
18068523
GOC		 1129 local_irq_restore(flags);
1130
c285545f
ZA		 1131 if (!vcpu->time_page)
1132 return 0;
18068523 1133
1d5f066e
ZA		 1134 /*
1135 * Time as measured by the TSC may go backwards when resetting the base
1136 * tsc_timestamp. The reason for this is that the TSC resolution is
1137 * higher than the resolution of the other clock scales. Thus, many
1138 * possible measurments of the TSC correspond to one measurement of any
1139 * other clock, and so a spread of values is possible. This is not a
1140 * problem for the computation of the nanosecond clock; with TSC rates
1141 * around 1GHZ, there can only be a few cycles which correspond to one
1142 * nanosecond value, and any path through this code will inevitably
1143 * take longer than that. However, with the kernel_ns value itself,
1144 * the precision may be much lower, down to HZ granularity. If the
1145 * first sampling of TSC against kernel_ns ends in the low part of the
1146 * range, and the second in the high end of the range, we can get:
1147 *
1148 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1149 *
1150 * As the sampling errors potentially range in the thousands of cycles,
1151 * it is possible such a time value has already been observed by the
1152 * guest. To protect against this, we must compute the system time as
1153 * observed by the guest and ensure the new system time is greater.
1154 */
1155 max_kernel_ns = 0;
1156 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1157 max_kernel_ns = vcpu->last_guest_tsc -
1158 vcpu->hv_clock.tsc_timestamp;
1159 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1160 vcpu->hv_clock.tsc_to_system_mul,
1161 vcpu->hv_clock.tsc_shift);
1162 max_kernel_ns += vcpu->last_kernel_ns;
1163 }
afbcf7ab 1164
e48672fa 1165 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1166 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1167 &vcpu->hv_clock.tsc_shift,
1168 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1169 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1170 }
1171
1d5f066e
ZA		 1172 if (max_kernel_ns > kernel_ns)
1173 kernel_ns = max_kernel_ns;
1174
8cfdc000 1175 /* With all the info we got, fill in the values */
1d5f066e 1176 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1177 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1178 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1179 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1180 vcpu->hv_clock.flags = 0;
1181
18068523
GOC		 1182 /*
1183 * The interface expects us to write an even number signaling that the
1184 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1185 * state, we just increase by 2 at the end.
18068523 1186 */
50d0a0f9 1187 vcpu->hv_clock.version += 2;
18068523
GOC		 1188
1189 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1190
1191 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1192 sizeof(vcpu->hv_clock));
18068523
GOC		 1193
1194 kunmap_atomic(shared_kaddr, KM_USER0);
1195
1196 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1197 return 0;
c8076604
GH		 1198}
1199
9ba075a6
AK		 1200static bool msr_mtrr_valid(unsigned msr)
1201{
1202 switch (msr) {
1203 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1204 case MSR_MTRRfix64K_00000:
1205 case MSR_MTRRfix16K_80000:
1206 case MSR_MTRRfix16K_A0000:
1207 case MSR_MTRRfix4K_C0000:
1208 case MSR_MTRRfix4K_C8000:
1209 case MSR_MTRRfix4K_D0000:
1210 case MSR_MTRRfix4K_D8000:
1211 case MSR_MTRRfix4K_E0000:
1212 case MSR_MTRRfix4K_E8000:
1213 case MSR_MTRRfix4K_F0000:
1214 case MSR_MTRRfix4K_F8000:
1215 case MSR_MTRRdefType:
1216 case MSR_IA32_CR_PAT:
1217 return true;
1218 case 0x2f8:
1219 return true;
1220 }
1221 return false;
1222}
1223
d6289b93
MT		 1224static bool valid_pat_type(unsigned t)
1225{
1226 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1227}
1228
1229static bool valid_mtrr_type(unsigned t)
1230{
1231 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1232}
1233
1234static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1235{
1236 int i;
1237
1238 if (!msr_mtrr_valid(msr))
1239 return false;
1240
1241 if (msr == MSR_IA32_CR_PAT) {
1242 for (i = 0; i < 8; i++)
1243 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1244 return false;
1245 return true;
1246 } else if (msr == MSR_MTRRdefType) {
1247 if (data & ~0xcff)
1248 return false;
1249 return valid_mtrr_type(data & 0xff);
1250 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1251 for (i = 0; i < 8 ; i++)
1252 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1253 return false;
1254 return true;
1255 }
1256
1257 /* variable MTRRs */
1258 return valid_mtrr_type(data & 0xff);
1259}
1260
9ba075a6
AK		 1261static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1262{
0bed3b56
SY		 1263 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1264
d6289b93 1265 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1266 return 1;
1267
0bed3b56
SY		 1268 if (msr == MSR_MTRRdefType) {
1269 vcpu->arch.mtrr_state.def_type = data;
1270 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1271 } else if (msr == MSR_MTRRfix64K_00000)
1272 p[0] = data;
1273 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1274 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1275 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1276 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1277 else if (msr == MSR_IA32_CR_PAT)
1278 vcpu->arch.pat = data;
1279 else { /* Variable MTRRs */
1280 int idx, is_mtrr_mask;
1281 u64 *pt;
1282
1283 idx = (msr - 0x200) / 2;
1284 is_mtrr_mask = msr - 0x200 - 2 * idx;
1285 if (!is_mtrr_mask)
1286 pt =
1287 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1288 else
1289 pt =
1290 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1291 *pt = data;
1292 }
1293
1294 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1295 return 0;
1296}
15c4a640 1297
890ca9ae 1298static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1299{
890ca9ae
HY		 1300 u64 mcg_cap = vcpu->arch.mcg_cap;
1301 unsigned bank_num = mcg_cap & 0xff;
1302
15c4a640 1303 switch (msr) {
15c4a640 1304 case MSR_IA32_MCG_STATUS:
890ca9ae 1305 vcpu->arch.mcg_status = data;
15c4a640 1306 break;
c7ac679c 1307 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1308 if (!(mcg_cap & MCG_CTL_P))
1309 return 1;
1310 if (data != 0 && data != ~(u64)0)
1311 return -1;
1312 vcpu->arch.mcg_ctl = data;
1313 break;
1314 default:
1315 if (msr >= MSR_IA32_MC0_CTL &&
1316 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1317 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1318 /* only 0 or all 1s can be written to IA32_MCi_CTL
1319 * some Linux kernels though clear bit 10 in bank 4 to
1320 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1321 * this to avoid an uncatched #GP in the guest
1322 */
890ca9ae 1323 if ((offset & 0x3) == 0 &&
114be429 1324 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1325 return -1;
1326 vcpu->arch.mce_banks[offset] = data;
1327 break;
1328 }
1329 return 1;
1330 }
1331 return 0;
1332}
1333
ffde22ac
ES		 1334static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1335{
1336 struct kvm *kvm = vcpu->kvm;
1337 int lm = is_long_mode(vcpu);
1338 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1339 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1340 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1341 : kvm->arch.xen_hvm_config.blob_size_32;
1342 u32 page_num = data & ~PAGE_MASK;
1343 u64 page_addr = data & PAGE_MASK;
1344 u8 *page;
1345 int r;
1346
1347 r = -E2BIG;
1348 if (page_num >= blob_size)
1349 goto out;
1350 r = -ENOMEM;
1351 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1352 if (!page)
1353 goto out;
1354 r = -EFAULT;
1355 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1356 goto out_free;
1357 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1358 goto out_free;
1359 r = 0;
1360out_free:
1361 kfree(page);
1362out:
1363 return r;
1364}
1365
55cd8e5a
GN		 1366static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1367{
1368 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1369}
1370
1371static bool kvm_hv_msr_partition_wide(u32 msr)
1372{
1373 bool r = false;
1374 switch (msr) {
1375 case HV_X64_MSR_GUEST_OS_ID:
1376 case HV_X64_MSR_HYPERCALL:
1377 r = true;
1378 break;
1379 }
1380
1381 return r;
1382}
1383
1384static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1385{
1386 struct kvm *kvm = vcpu->kvm;
1387
1388 switch (msr) {
1389 case HV_X64_MSR_GUEST_OS_ID:
1390 kvm->arch.hv_guest_os_id = data;
1391 /* setting guest os id to zero disables hypercall page */
1392 if (!kvm->arch.hv_guest_os_id)
1393 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1394 break;
1395 case HV_X64_MSR_HYPERCALL: {
1396 u64 gfn;
1397 unsigned long addr;
1398 u8 instructions[4];
1399
1400 /* if guest os id is not set hypercall should remain disabled */
1401 if (!kvm->arch.hv_guest_os_id)
1402 break;
1403 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1404 kvm->arch.hv_hypercall = data;
1405 break;
1406 }
1407 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1408 addr = gfn_to_hva(kvm, gfn);
1409 if (kvm_is_error_hva(addr))
1410 return 1;
1411 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1412 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1413 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1414 return 1;
1415 kvm->arch.hv_hypercall = data;
1416 break;
1417 }
1418 default:
1419 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1420 "data 0x%llx\n", msr, data);
1421 return 1;
1422 }
1423 return 0;
1424}
1425
1426static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1427{
10388a07
GN		 1428 switch (msr) {
1429 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1430 unsigned long addr;
55cd8e5a 1431
10388a07
GN		 1432 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1433 vcpu->arch.hv_vapic = data;
1434 break;
1435 }
1436 addr = gfn_to_hva(vcpu->kvm, data >>
1437 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1438 if (kvm_is_error_hva(addr))
1439 return 1;
8b0cedff 1440 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1441 return 1;
1442 vcpu->arch.hv_vapic = data;
1443 break;
1444 }
1445 case HV_X64_MSR_EOI:
1446 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1447 case HV_X64_MSR_ICR:
1448 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1449 case HV_X64_MSR_TPR:
1450 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1451 default:
1452 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1453 "data 0x%llx\n", msr, data);
1454 return 1;
1455 }
1456
1457 return 0;
55cd8e5a
GN		 1458}
1459
344d9588
GN		 1460static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1461{
1462 gpa_t gpa = data & ~0x3f;
1463
6adba527
GN		 1464 /* Bits 2:5 are resrved, Should be zero */
1465 if (data & 0x3c)
344d9588
GN		 1466 return 1;
1467
1468 vcpu->arch.apf.msr_val = data;
1469
1470 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1471 kvm_clear_async_pf_completion_queue(vcpu);
1472 kvm_async_pf_hash_reset(vcpu);
1473 return 0;
1474 }
1475
1476 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1477 return 1;
1478
6adba527 1479 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1480 kvm_async_pf_wakeup_all(vcpu);
1481 return 0;
1482}
1483
12f9a48f
GC		 1484static void kvmclock_reset(struct kvm_vcpu *vcpu)
1485{
1486 if (vcpu->arch.time_page) {
1487 kvm_release_page_dirty(vcpu->arch.time_page);
1488 vcpu->arch.time_page = NULL;
1489 }
1490}
1491
c9aaa895
GC		 1492static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1493{
1494 u64 delta;
1495
1496 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1497 return;
1498
1499 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1500 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1501 vcpu->arch.st.accum_steal = delta;
1502}
1503
1504static void record_steal_time(struct kvm_vcpu *vcpu)
1505{
1506 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1507 return;
1508
1509 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1510 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1511 return;
1512
1513 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1514 vcpu->arch.st.steal.version += 2;
1515 vcpu->arch.st.accum_steal = 0;
1516
1517 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1518 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1519}
1520
15c4a640
CO		 1521int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1522{
1523 switch (msr) {
15c4a640 1524 case MSR_EFER:
b69e8cae 1525 return set_efer(vcpu, data);
8f1589d9
AP		 1526 case MSR_K7_HWCR:
1527 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1528 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1529 if (data != 0) {
1530 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1531 data);
1532 return 1;
1533 }
15c4a640 1534 break;
f7c6d140
AP		 1535 case MSR_FAM10H_MMIO_CONF_BASE:
1536 if (data != 0) {
1537 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1538 "0x%llx\n", data);
1539 return 1;
1540 }
15c4a640 1541 break;
c323c0e5 1542 case MSR_AMD64_NB_CFG:
c7ac679c 1543 break;
b5e2fec0
AG		 1544 case MSR_IA32_DEBUGCTLMSR:
1545 if (!data) {
1546 /* We support the non-activated case already */
1547 break;
1548 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1549 /* Values other than LBR and BTF are vendor-specific,
1550 thus reserved and should throw a #GP */
1551 return 1;
1552 }
1553 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1554 __func__, data);
1555 break;
15c4a640
CO		 1556 case MSR_IA32_UCODE_REV:
1557 case MSR_IA32_UCODE_WRITE:
61a6bd67 1558 case MSR_VM_HSAVE_PA:
6098ca93 1559 case MSR_AMD64_PATCH_LOADER:
15c4a640 1560 break;
9ba075a6
AK		 1561 case 0x200 ... 0x2ff:
1562 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1563 case MSR_IA32_APICBASE:
1564 kvm_set_apic_base(vcpu, data);
1565 break;
0105d1a5
GN		 1566 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1567 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1568 case MSR_IA32_MISC_ENABLE:
ad312c7c 1569 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1570 break;
11c6bffa 1571 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1572 case MSR_KVM_WALL_CLOCK:
1573 vcpu->kvm->arch.wall_clock = data;
1574 kvm_write_wall_clock(vcpu->kvm, data);
1575 break;
11c6bffa 1576 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1577 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1578 kvmclock_reset(vcpu);
18068523
GOC		 1579
1580 vcpu->arch.time = data;
c285545f 1581 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1582
1583 /* we verify if the enable bit is set... */
1584 if (!(data & 1))
1585 break;
1586
1587 /* ...but clean it before doing the actual write */
1588 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1589
18068523
GOC		 1590 vcpu->arch.time_page =
1591 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1592
1593 if (is_error_page(vcpu->arch.time_page)) {
1594 kvm_release_page_clean(vcpu->arch.time_page);
1595 vcpu->arch.time_page = NULL;
1596 }
18068523
GOC		 1597 break;
1598 }
344d9588
GN		 1599 case MSR_KVM_ASYNC_PF_EN:
1600 if (kvm_pv_enable_async_pf(vcpu, data))
1601 return 1;
1602 break;
c9aaa895
GC		 1603 case MSR_KVM_STEAL_TIME:
1604
1605 if (unlikely(!sched_info_on()))
1606 return 1;
1607
1608 if (data & KVM_STEAL_RESERVED_MASK)
1609 return 1;
1610
1611 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1612 data & KVM_STEAL_VALID_BITS))
1613 return 1;
1614
1615 vcpu->arch.st.msr_val = data;
1616
1617 if (!(data & KVM_MSR_ENABLED))
1618 break;
1619
1620 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1621
1622 preempt_disable();
1623 accumulate_steal_time(vcpu);
1624 preempt_enable();
1625
1626 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1627
1628 break;
1629
890ca9ae
HY		 1630 case MSR_IA32_MCG_CTL:
1631 case MSR_IA32_MCG_STATUS:
1632 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1633 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1634
1635 /* Performance counters are not protected by a CPUID bit,
1636 * so we should check all of them in the generic path for the sake of
1637 * cross vendor migration.
1638 * Writing a zero into the event select MSRs disables them,
1639 * which we perfectly emulate ;-). Any other value should be at least
1640 * reported, some guests depend on them.
1641 */
1642 case MSR_P6_EVNTSEL0:
1643 case MSR_P6_EVNTSEL1:
1644 case MSR_K7_EVNTSEL0:
1645 case MSR_K7_EVNTSEL1:
1646 case MSR_K7_EVNTSEL2:
1647 case MSR_K7_EVNTSEL3:
1648 if (data != 0)
1649 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1650 "0x%x data 0x%llx\n", msr, data);
1651 break;
1652 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1653 * so we ignore writes to make it happy.
1654 */
1655 case MSR_P6_PERFCTR0:
1656 case MSR_P6_PERFCTR1:
1657 case MSR_K7_PERFCTR0:
1658 case MSR_K7_PERFCTR1:
1659 case MSR_K7_PERFCTR2:
1660 case MSR_K7_PERFCTR3:
1661 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1662 "0x%x data 0x%llx\n", msr, data);
1663 break;
84e0cefa
JS		 1664 case MSR_K7_CLK_CTL:
1665 /*
1666 * Ignore all writes to this no longer documented MSR.
1667 * Writes are only relevant for old K7 processors,
1668 * all pre-dating SVM, but a recommended workaround from
1669 * AMD for these chips. It is possible to speicify the
1670 * affected processor models on the command line, hence
1671 * the need to ignore the workaround.
1672 */
1673 break;
55cd8e5a
GN		 1674 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1675 if (kvm_hv_msr_partition_wide(msr)) {
1676 int r;
1677 mutex_lock(&vcpu->kvm->lock);
1678 r = set_msr_hyperv_pw(vcpu, msr, data);
1679 mutex_unlock(&vcpu->kvm->lock);
1680 return r;
1681 } else
1682 return set_msr_hyperv(vcpu, msr, data);
1683 break;
91c9c3ed 1684 case MSR_IA32_BBL_CR_CTL3:
1685 /* Drop writes to this legacy MSR -- see rdmsr
1686 * counterpart for further detail.
1687 */
1688 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1689 break;
15c4a640 1690 default:
ffde22ac
ES		 1691 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1692 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1693 if (!ignore_msrs) {
1694 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1695 msr, data);
1696 return 1;
1697 } else {
1698 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1699 msr, data);
1700 break;
1701 }
15c4a640
CO		 1702 }
1703 return 0;
1704}
1705EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1706
1707
1708/*
1709 * Reads an msr value (of 'msr_index') into 'pdata'.
1710 * Returns 0 on success, non-0 otherwise.
1711 * Assumes vcpu_load() was already called.
1712 */
1713int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1714{
1715 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1716}
1717
9ba075a6
AK		 1718static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1719{
0bed3b56
SY		 1720 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1721
9ba075a6
AK		 1722 if (!msr_mtrr_valid(msr))
1723 return 1;
1724
0bed3b56
SY		 1725 if (msr == MSR_MTRRdefType)
1726 *pdata = vcpu->arch.mtrr_state.def_type +
1727 (vcpu->arch.mtrr_state.enabled << 10);
1728 else if (msr == MSR_MTRRfix64K_00000)
1729 *pdata = p[0];
1730 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1731 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1732 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1733 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1734 else if (msr == MSR_IA32_CR_PAT)
1735 *pdata = vcpu->arch.pat;
1736 else { /* Variable MTRRs */
1737 int idx, is_mtrr_mask;
1738 u64 *pt;
1739
1740 idx = (msr - 0x200) / 2;
1741 is_mtrr_mask = msr - 0x200 - 2 * idx;
1742 if (!is_mtrr_mask)
1743 pt =
1744 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1745 else
1746 pt =
1747 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1748 *pdata = *pt;
1749 }
1750
9ba075a6
AK		 1751 return 0;
1752}
1753
890ca9ae 1754static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1755{
1756 u64 data;
890ca9ae
HY		 1757 u64 mcg_cap = vcpu->arch.mcg_cap;
1758 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1759
1760 switch (msr) {
15c4a640
CO		 1761 case MSR_IA32_P5_MC_ADDR:
1762 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1763 data = 0;
1764 break;
15c4a640 1765 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1766 data = vcpu->arch.mcg_cap;
1767 break;
c7ac679c 1768 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1769 if (!(mcg_cap & MCG_CTL_P))
1770 return 1;
1771 data = vcpu->arch.mcg_ctl;
1772 break;
1773 case MSR_IA32_MCG_STATUS:
1774 data = vcpu->arch.mcg_status;
1775 break;
1776 default:
1777 if (msr >= MSR_IA32_MC0_CTL &&
1778 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1779 u32 offset = msr - MSR_IA32_MC0_CTL;
1780 data = vcpu->arch.mce_banks[offset];
1781 break;
1782 }
1783 return 1;
1784 }
1785 *pdata = data;
1786 return 0;
1787}
1788
55cd8e5a
GN		 1789static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1790{
1791 u64 data = 0;
1792 struct kvm *kvm = vcpu->kvm;
1793
1794 switch (msr) {
1795 case HV_X64_MSR_GUEST_OS_ID:
1796 data = kvm->arch.hv_guest_os_id;
1797 break;
1798 case HV_X64_MSR_HYPERCALL:
1799 data = kvm->arch.hv_hypercall;
1800 break;
1801 default:
1802 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1803 return 1;
1804 }
1805
1806 *pdata = data;
1807 return 0;
1808}
1809
1810static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1811{
1812 u64 data = 0;
1813
1814 switch (msr) {
1815 case HV_X64_MSR_VP_INDEX: {
1816 int r;
1817 struct kvm_vcpu *v;
1818 kvm_for_each_vcpu(r, v, vcpu->kvm)
1819 if (v == vcpu)
1820 data = r;
1821 break;
1822 }
10388a07
GN		 1823 case HV_X64_MSR_EOI:
1824 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1825 case HV_X64_MSR_ICR:
1826 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1827 case HV_X64_MSR_TPR:
1828 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1829 default:
1830 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1831 return 1;
1832 }
1833 *pdata = data;
1834 return 0;
1835}
1836
890ca9ae
HY		 1837int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1838{
1839 u64 data;
1840
1841 switch (msr) {
890ca9ae 1842 case MSR_IA32_PLATFORM_ID:
15c4a640 1843 case MSR_IA32_UCODE_REV:
15c4a640 1844 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1845 case MSR_IA32_DEBUGCTLMSR:
1846 case MSR_IA32_LASTBRANCHFROMIP:
1847 case MSR_IA32_LASTBRANCHTOIP:
1848 case MSR_IA32_LASTINTFROMIP:
1849 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1850 case MSR_K8_SYSCFG:
1851 case MSR_K7_HWCR:
61a6bd67 1852 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1853 case MSR_P6_PERFCTR0:
1854 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1855 case MSR_P6_EVNTSEL0:
1856 case MSR_P6_EVNTSEL1:
9e699624 1857 case MSR_K7_EVNTSEL0:
1f3ee616 1858 case MSR_K7_PERFCTR0:
1fdbd48c 1859 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1860 case MSR_AMD64_NB_CFG:
f7c6d140 1861 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1862 data = 0;
1863 break;
9ba075a6
AK		 1864 case MSR_MTRRcap:
1865 data = 0x500 | KVM_NR_VAR_MTRR;
1866 break;
1867 case 0x200 ... 0x2ff:
1868 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1869 case 0xcd: /* fsb frequency */
1870 data = 3;
1871 break;
7b914098
JS		 1872 /*
1873 * MSR_EBC_FREQUENCY_ID
1874 * Conservative value valid for even the basic CPU models.
1875 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1876 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1877 * and 266MHz for model 3, or 4. Set Core Clock
1878 * Frequency to System Bus Frequency Ratio to 1 (bits
1879 * 31:24) even though these are only valid for CPU
1880 * models > 2, however guests may end up dividing or
1881 * multiplying by zero otherwise.
1882 */
1883 case MSR_EBC_FREQUENCY_ID:
1884 data = 1 << 24;
1885 break;
15c4a640
CO		 1886 case MSR_IA32_APICBASE:
1887 data = kvm_get_apic_base(vcpu);
1888 break;
0105d1a5
GN		 1889 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1890 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1891 break;
15c4a640 1892 case MSR_IA32_MISC_ENABLE:
ad312c7c 1893 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1894 break;
847f0ad8
AG		 1895 case MSR_IA32_PERF_STATUS:
1896 /* TSC increment by tick */
1897 data = 1000ULL;
1898 /* CPU multiplier */
1899 data |= (((uint64_t)4ULL) << 40);
1900 break;
15c4a640 1901 case MSR_EFER:
f6801dff 1902 data = vcpu->arch.efer;
15c4a640 1903 break;
18068523 1904 case MSR_KVM_WALL_CLOCK:
11c6bffa 1905 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1906 data = vcpu->kvm->arch.wall_clock;
1907 break;
1908 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1909 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1910 data = vcpu->arch.time;
1911 break;
344d9588
GN		 1912 case MSR_KVM_ASYNC_PF_EN:
1913 data = vcpu->arch.apf.msr_val;
1914 break;
c9aaa895
GC		 1915 case MSR_KVM_STEAL_TIME:
1916 data = vcpu->arch.st.msr_val;
1917 break;
890ca9ae
HY		 1918 case MSR_IA32_P5_MC_ADDR:
1919 case MSR_IA32_P5_MC_TYPE:
1920 case MSR_IA32_MCG_CAP:
1921 case MSR_IA32_MCG_CTL:
1922 case MSR_IA32_MCG_STATUS:
1923 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1924 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1925 case MSR_K7_CLK_CTL:
1926 /*
1927 * Provide expected ramp-up count for K7. All other
1928 * are set to zero, indicating minimum divisors for
1929 * every field.
1930 *
1931 * This prevents guest kernels on AMD host with CPU
1932 * type 6, model 8 and higher from exploding due to
1933 * the rdmsr failing.
1934 */
1935 data = 0x20000000;
1936 break;
55cd8e5a
GN		 1937 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1938 if (kvm_hv_msr_partition_wide(msr)) {
1939 int r;
1940 mutex_lock(&vcpu->kvm->lock);
1941 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1942 mutex_unlock(&vcpu->kvm->lock);
1943 return r;
1944 } else
1945 return get_msr_hyperv(vcpu, msr, pdata);
1946 break;
91c9c3ed 1947 case MSR_IA32_BBL_CR_CTL3:
1948 /* This legacy MSR exists but isn't fully documented in current
1949 * silicon. It is however accessed by winxp in very narrow
1950 * scenarios where it sets bit #19, itself documented as
1951 * a "reserved" bit. Best effort attempt to source coherent
1952 * read data here should the balance of the register be
1953 * interpreted by the guest:
1954 *
1955 * L2 cache control register 3: 64GB range, 256KB size,
1956 * enabled, latency 0x1, configured
1957 */
1958 data = 0xbe702111;
1959 break;
15c4a640 1960 default:
ed85c068
AP		 1961 if (!ignore_msrs) {
1962 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1963 return 1;
1964 } else {
1965 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1966 data = 0;
1967 }
1968 break;
15c4a640
CO		 1969 }
1970 *pdata = data;
1971 return 0;
1972}
1973EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1974
313a3dc7
CO		 1975/*
1976 * Read or write a bunch of msrs. All parameters are kernel addresses.
1977 *
1978 * @return number of msrs set successfully.
1979 */
1980static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1981 struct kvm_msr_entry *entries,
1982 int (*do_msr)(struct kvm_vcpu *vcpu,
1983 unsigned index, u64 *data))
1984{
f656ce01 1985 int i, idx;
313a3dc7 1986
f656ce01 1987 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1988 for (i = 0; i < msrs->nmsrs; ++i)
1989 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1990 break;
f656ce01 1991 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1992
313a3dc7
CO		 1993 return i;
1994}
1995
1996/*
1997 * Read or write a bunch of msrs. Parameters are user addresses.
1998 *
1999 * @return number of msrs set successfully.
2000 */
2001static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2002 int (*do_msr)(struct kvm_vcpu *vcpu,
2003 unsigned index, u64 *data),
2004 int writeback)
2005{
2006 struct kvm_msrs msrs;
2007 struct kvm_msr_entry *entries;
2008 int r, n;
2009 unsigned size;
2010
2011 r = -EFAULT;
2012 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2013 goto out;
2014
2015 r = -E2BIG;
2016 if (msrs.nmsrs >= MAX_IO_MSRS)
2017 goto out;
2018
2019 r = -ENOMEM;
2020 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 2021 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 2022 if (!entries)
2023 goto out;
2024
2025 r = -EFAULT;
2026 if (copy_from_user(entries, user_msrs->entries, size))
2027 goto out_free;
2028
2029 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2030 if (r < 0)
2031 goto out_free;
2032
2033 r = -EFAULT;
2034 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2035 goto out_free;
2036
2037 r = n;
2038
2039out_free:
7a73c028 2040 kfree(entries);
313a3dc7
CO		 2041out:
2042 return r;
2043}
2044
018d00d2
ZX		 2045int kvm_dev_ioctl_check_extension(long ext)
2046{
2047 int r;
2048
2049 switch (ext) {
2050 case KVM_CAP_IRQCHIP:
2051 case KVM_CAP_HLT:
2052 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2053 case KVM_CAP_SET_TSS_ADDR:
07716717 2054 case KVM_CAP_EXT_CPUID:
c8076604 2055 case KVM_CAP_CLOCKSOURCE:
7837699f 2056 case KVM_CAP_PIT:
a28e4f5a 2057 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2058 case KVM_CAP_MP_STATE:
ed848624 2059 case KVM_CAP_SYNC_MMU:
a355c85c 2060 case KVM_CAP_USER_NMI:
52d939a0 2061 case KVM_CAP_REINJECT_CONTROL:
4925663a 2062 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 2063 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 2064 case KVM_CAP_IRQFD:
d34e6b17 2065 case KVM_CAP_IOEVENTFD:
c5ff41ce 2066 case KVM_CAP_PIT2:
e9f42757 2067 case KVM_CAP_PIT_STATE2:
b927a3ce 2068 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2069 case KVM_CAP_XEN_HVM:
afbcf7ab 2070 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2071 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2072 case KVM_CAP_HYPERV:
10388a07 2073 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2074 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2075 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2076 case KVM_CAP_DEBUGREGS:
d2be1651 2077 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2078 case KVM_CAP_XSAVE:
344d9588 2079 case KVM_CAP_ASYNC_PF:
92a1f12d 2080 case KVM_CAP_GET_TSC_KHZ:
018d00d2
ZX		 2081 r = 1;
2082 break;
542472b5
LV		 2083 case KVM_CAP_COALESCED_MMIO:
2084 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2085 break;
774ead3a
AK		 2086 case KVM_CAP_VAPIC:
2087 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2088 break;
f725230a
AK		 2089 case KVM_CAP_NR_VCPUS:
2090 r = KVM_MAX_VCPUS;
2091 break;
a988b910
AK		 2092 case KVM_CAP_NR_MEMSLOTS:
2093 r = KVM_MEMORY_SLOTS;
2094 break;
a68a6a72
MT		 2095 case KVM_CAP_PV_MMU: /* obsolete */
2096 r = 0;
2f333bcb 2097 break;
62c476c7 2098 case KVM_CAP_IOMMU:
a1b60c1c 2099 r = iommu_present(&pci_bus_type);
62c476c7 2100 break;
890ca9ae
HY		 2101 case KVM_CAP_MCE:
2102 r = KVM_MAX_MCE_BANKS;
2103 break;
2d5b5a66
SY		 2104 case KVM_CAP_XCRS:
2105 r = cpu_has_xsave;
2106 break;
92a1f12d
JR		 2107 case KVM_CAP_TSC_CONTROL:
2108 r = kvm_has_tsc_control;
2109 break;
018d00d2
ZX		 2110 default:
2111 r = 0;
2112 break;
2113 }
2114 return r;
2115
2116}
2117
043405e1
CO		 2118long kvm_arch_dev_ioctl(struct file *filp,
2119 unsigned int ioctl, unsigned long arg)
2120{
2121 void __user *argp = (void __user *)arg;
2122 long r;
2123
2124 switch (ioctl) {
2125 case KVM_GET_MSR_INDEX_LIST: {
2126 struct kvm_msr_list __user *user_msr_list = argp;
2127 struct kvm_msr_list msr_list;
2128 unsigned n;
2129
2130 r = -EFAULT;
2131 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2132 goto out;
2133 n = msr_list.nmsrs;
2134 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2135 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2136 goto out;
2137 r = -E2BIG;
e125e7b6 2138 if (n < msr_list.nmsrs)
043405e1
CO		 2139 goto out;
2140 r = -EFAULT;
2141 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2142 num_msrs_to_save * sizeof(u32)))
2143 goto out;
e125e7b6 2144 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2145 &emulated_msrs,
2146 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2147 goto out;
2148 r = 0;
2149 break;
2150 }
674eea0f
AK		 2151 case KVM_GET_SUPPORTED_CPUID: {
2152 struct kvm_cpuid2 __user *cpuid_arg = argp;
2153 struct kvm_cpuid2 cpuid;
2154
2155 r = -EFAULT;
2156 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2157 goto out;
2158 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2159 cpuid_arg->entries);
674eea0f
AK		 2160 if (r)
2161 goto out;
2162
2163 r = -EFAULT;
2164 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2165 goto out;
2166 r = 0;
2167 break;
2168 }
890ca9ae
HY		 2169 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2170 u64 mce_cap;
2171
2172 mce_cap = KVM_MCE_CAP_SUPPORTED;
2173 r = -EFAULT;
2174 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2175 goto out;
2176 r = 0;
2177 break;
2178 }
043405e1
CO		 2179 default:
2180 r = -EINVAL;
2181 }
2182out:
2183 return r;
2184}
2185
f5f48ee1
SY		 2186static void wbinvd_ipi(void *garbage)
2187{
2188 wbinvd();
2189}
2190
2191static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2192{
2193 return vcpu->kvm->arch.iommu_domain &&
2194 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2195}
2196
313a3dc7
CO		 2197void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2198{
f5f48ee1
SY		 2199 /* Address WBINVD may be executed by guest */
2200 if (need_emulate_wbinvd(vcpu)) {
2201 if (kvm_x86_ops->has_wbinvd_exit())
2202 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2203 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2204 smp_call_function_single(vcpu->cpu,
2205 wbinvd_ipi, NULL, 1);
2206 }
2207
313a3dc7 2208 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2209 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa 2210 /* Make sure TSC doesn't go backwards */
8f6055cb
JR		 2211 s64 tsc_delta;
2212 u64 tsc;
2213
2214 kvm_get_msr(vcpu, MSR_IA32_TSC, &tsc);
2215 tsc_delta = !vcpu->arch.last_guest_tsc ? 0 :
2216 tsc - vcpu->arch.last_guest_tsc;
2217
e48672fa
ZA		 2218 if (tsc_delta < 0)
2219 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2220 if (check_tsc_unstable()) {
e48672fa 2221 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
c285545f 2222 vcpu->arch.tsc_catchup = 1;
c285545f 2223 }
1aa8ceef 2224 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2225 if (vcpu->cpu != cpu)
2226 kvm_migrate_timers(vcpu);
e48672fa 2227 vcpu->cpu = cpu;
6b7d7e76 2228 }
c9aaa895
GC		 2229
2230 accumulate_steal_time(vcpu);
2231 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2232}
2233
2234void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2235{
02daab21 2236 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2237 kvm_put_guest_fpu(vcpu);
7c4c0f4f 2238 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
313a3dc7
CO		 2239}
2240
07716717 2241static int is_efer_nx(void)
313a3dc7 2242{
e286e86e 2243 unsigned long long efer = 0;
313a3dc7 2244
e286e86e 2245 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 2246 return efer & EFER_NX;
2247}
2248
2249static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2250{
2251 int i;
2252 struct kvm_cpuid_entry2 *e, *entry;
2253
313a3dc7 2254 entry = NULL;
ad312c7c
ZX		 2255 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2256 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 2257 if (e->function == 0x80000001) {
2258 entry = e;
2259 break;
2260 }
2261 }
07716717 2262 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 2263 entry->edx &= ~(1 << 20);
2264 printk(KERN_INFO "kvm: guest NX capability removed\n");
2265 }
2266}
2267
07716717 2268/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 2269static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2270 struct kvm_cpuid *cpuid,
2271 struct kvm_cpuid_entry __user *entries)
07716717
DK		 2272{
2273 int r, i;
2274 struct kvm_cpuid_entry *cpuid_entries;
2275
2276 r = -E2BIG;
2277 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2278 goto out;
2279 r = -ENOMEM;
2280 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2281 if (!cpuid_entries)
2282 goto out;
2283 r = -EFAULT;
2284 if (copy_from_user(cpuid_entries, entries,
2285 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2286 goto out_free;
2287 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 2288 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2289 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2290 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2291 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2292 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2293 vcpu->arch.cpuid_entries[i].index = 0;
2294 vcpu->arch.cpuid_entries[i].flags = 0;
2295 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2296 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2297 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2298 }
2299 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2300 cpuid_fix_nx_cap(vcpu);
2301 r = 0;
fc61b800 2302 kvm_apic_set_version(vcpu);
0e851880 2303 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2304 update_cpuid(vcpu);
07716717
DK		 2305
2306out_free:
2307 vfree(cpuid_entries);
2308out:
2309 return r;
2310}
2311
2312static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2313 struct kvm_cpuid2 *cpuid,
2314 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2315{
2316 int r;
2317
2318 r = -E2BIG;
2319 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2320 goto out;
2321 r = -EFAULT;
ad312c7c 2322 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2323 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2324 goto out;
ad312c7c 2325 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2326 kvm_apic_set_version(vcpu);
0e851880 2327 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2328 update_cpuid(vcpu);
313a3dc7
CO		 2329 return 0;
2330
2331out:
2332 return r;
2333}
2334
07716717 2335static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2336 struct kvm_cpuid2 *cpuid,
2337 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2338{
2339 int r;
2340
2341 r = -E2BIG;
ad312c7c 2342 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2343 goto out;
2344 r = -EFAULT;
ad312c7c 2345 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2346 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2347 goto out;
2348 return 0;
2349
2350out:
ad312c7c 2351 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2352 return r;
2353}
2354
945ee35e
AK		 2355static void cpuid_mask(u32 *word, int wordnum)
2356{
2357 *word &= boot_cpu_data.x86_capability[wordnum];
2358}
2359
07716717 2360static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2361 u32 index)
07716717
DK		 2362{
2363 entry->function = function;
2364 entry->index = index;
2365 cpuid_count(entry->function, entry->index,
19355475 2366 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2367 entry->flags = 0;
2368}
2369
24c82e57
AK		 2370static bool supported_xcr0_bit(unsigned bit)
2371{
2372 u64 mask = ((u64)1 << bit);
2373
2374 return mask & (XSTATE_FP | XSTATE_SSE | XSTATE_YMM) & host_xcr0;
2375}
2376
7faa4ee1
AK		 2377#define F(x) bit(X86_FEATURE_##x)
2378
07716717
DK		 2379static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2380 u32 index, int *nent, int maxnent)
2381{
7faa4ee1 2382 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2383#ifdef CONFIG_X86_64
17cc3935
SY		 2384 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2385 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2386 unsigned f_lm = F(LM);
2387#else
17cc3935 2388 unsigned f_gbpages = 0;
7faa4ee1 2389 unsigned f_lm = 0;
07716717 2390#endif
4e47c7a6 2391 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2392
2393 /* cpuid 1.edx */
2394 const u32 kvm_supported_word0_x86_features =
2395 F(FPU) | F(VME) | F(DE) | F(PSE) |
2396 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2397 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2398 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2399 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2400 0 /* Reserved, DS, ACPI */ | F(MMX) |
2401 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2402 0 /* HTT, TM, Reserved, PBE */;
2403 /* cpuid 0x80000001.edx */
2404 const u32 kvm_supported_word1_x86_features =
2405 F(FPU) | F(VME) | F(DE) | F(PSE) |
2406 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2407 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2408 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2409 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2410 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2411 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2412 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2413 /* cpuid 1.ecx */
2414 const u32 kvm_supported_word4_x86_features =
6c3f6041 2415 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2416 0 /* DS-CPL, VMX, SMX, EST */ |
2417 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2418 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2419 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2420 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6d886fd0 2421 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
4a00efdf 2422 F(F16C) | F(RDRAND);
7faa4ee1 2423 /* cpuid 0x80000001.ecx */
07716717 2424 const u32 kvm_supported_word6_x86_features =
4c62a2dc 2425 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
7faa4ee1 2426 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
7ef8aa72 2427 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) |
6d886fd0 2428 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM);
07716717 2429
4429d5dc
B		 2430 /* cpuid 0xC0000001.edx */
2431 const u32 kvm_supported_word5_x86_features =
2432 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |
2433 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
2434 F(PMM) | F(PMM_EN);
2435
611c120f
YW		 2436 /* cpuid 7.0.ebx */
2437 const u32 kvm_supported_word9_x86_features =
a01c8f9b 2438 F(SMEP) | F(FSGSBASE) | F(ERMS);
611c120f 2439
19355475 2440 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2441 get_cpu();
2442 do_cpuid_1_ent(entry, function, index);
2443 ++*nent;
2444
2445 switch (function) {
2446 case 0:
2acf923e 2447 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2448 break;
2449 case 1:
2450 entry->edx &= kvm_supported_word0_x86_features;
945ee35e 2451 cpuid_mask(&entry->edx, 0);
7faa4ee1 2452 entry->ecx &= kvm_supported_word4_x86_features;
945ee35e 2453 cpuid_mask(&entry->ecx, 4);
0d1de2d9
GN		 2454 /* we support x2apic emulation even if host does not support
2455 * it since we emulate x2apic in software */
2456 entry->ecx |= F(X2APIC);
07716717
DK		 2457 break;
2458 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2459 * may return different values. This forces us to get_cpu() before
2460 * issuing the first command, and also to emulate this annoying behavior
2461 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2462 case 2: {
2463 int t, times = entry->eax & 0xff;
2464
2465 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2466 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2467 for (t = 1; t < times && *nent < maxnent; ++t) {
2468 do_cpuid_1_ent(&entry[t], function, 0);
2469 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2470 ++*nent;
2471 }
2472 break;
2473 }
611c120f 2474 /* function 4 has additional index. */
07716717 2475 case 4: {
14af3f3c 2476 int i, cache_type;
07716717
DK		 2477
2478 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2479 /* read more entries until cache_type is zero */
14af3f3c
HH		 2480 for (i = 1; *nent < maxnent; ++i) {
2481 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2482 if (!cache_type)
2483 break;
14af3f3c
HH		 2484 do_cpuid_1_ent(&entry[i], function, i);
2485 entry[i].flags |=
07716717
DK		 2486 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2487 ++*nent;
2488 }
2489 break;
2490 }
611c120f
YW		 2491 case 7: {
2492 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2493 /* Mask ebx against host capbability word 9 */
2494 if (index == 0) {
2495 entry->ebx &= kvm_supported_word9_x86_features;
2496 cpuid_mask(&entry->ebx, 9);
2497 } else
2498 entry->ebx = 0;
2499 entry->eax = 0;
2500 entry->ecx = 0;
2501 entry->edx = 0;
2502 break;
2503 }
24c82e57
AK		 2504 case 9:
2505 break;
611c120f 2506 /* function 0xb has additional index. */
07716717 2507 case 0xb: {
14af3f3c 2508 int i, level_type;
07716717
DK		 2509
2510 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2511 /* read more entries until level_type is zero */
14af3f3c 2512 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2513 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2514 if (!level_type)
2515 break;
14af3f3c
HH		 2516 do_cpuid_1_ent(&entry[i], function, i);
2517 entry[i].flags |=
07716717
DK		 2518 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2519 ++*nent;
2520 }
2521 break;
2522 }
2acf923e 2523 case 0xd: {
02668b06 2524 int idx, i;
2acf923e
DC		 2525
2526 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
02668b06
AP		 2527 for (idx = 1, i = 1; *nent < maxnent && idx < 64; ++idx) {
2528 do_cpuid_1_ent(&entry[i], function, idx);
2529 if (entry[i].eax == 0 || !supported_xcr0_bit(idx))
20800bc9 2530 continue;
2acf923e
DC		 2531 entry[i].flags |=
2532 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2533 ++*nent;
02668b06 2534 ++i;
2acf923e
DC		 2535 }
2536 break;
2537 }
84478c82
GC		 2538 case KVM_CPUID_SIGNATURE: {
2539 char signature[12] = "KVMKVMKVM\0\0";
2540 u32 *sigptr = (u32 *)signature;
2541 entry->eax = 0;
2542 entry->ebx = sigptr[0];
2543 entry->ecx = sigptr[1];
2544 entry->edx = sigptr[2];
2545 break;
2546 }
2547 case KVM_CPUID_FEATURES:
2548 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2549 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64 2550 (1 << KVM_FEATURE_CLOCKSOURCE2) |
32918924 2551 (1 << KVM_FEATURE_ASYNC_PF) |
371bcf64 2552 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
c9aaa895
GC		 2553
2554 if (sched_info_on())
2555 entry->eax |= (1 << KVM_FEATURE_STEAL_TIME);
2556
84478c82
GC		 2557 entry->ebx = 0;
2558 entry->ecx = 0;
2559 entry->edx = 0;
2560 break;
07716717
DK		 2561 case 0x80000000:
2562 entry->eax = min(entry->eax, 0x8000001a);
2563 break;
2564 case 0x80000001:
2565 entry->edx &= kvm_supported_word1_x86_features;
945ee35e 2566 cpuid_mask(&entry->edx, 1);
07716717 2567 entry->ecx &= kvm_supported_word6_x86_features;
945ee35e 2568 cpuid_mask(&entry->ecx, 6);
07716717 2569 break;
24c82e57
AK		 2570 case 0x80000008: {
2571 unsigned g_phys_as = (entry->eax >> 16) & 0xff;
2572 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U);
2573 unsigned phys_as = entry->eax & 0xff;
2574
2575 if (!g_phys_as)
2576 g_phys_as = phys_as;
2577 entry->eax = g_phys_as | (virt_as << 8);
2578 entry->ebx = entry->edx = 0;
2579 break;
2580 }
2581 case 0x80000019:
2582 entry->ecx = entry->edx = 0;
2583 break;
2584 case 0x8000001a:
2585 break;
2586 case 0x8000001d:
2587 break;
4429d5dc
B		 2588 /*Add support for Centaur's CPUID instruction*/
2589 case 0xC0000000:
2590 /*Just support up to 0xC0000004 now*/
2591 entry->eax = min(entry->eax, 0xC0000004);
2592 break;
2593 case 0xC0000001:
2594 entry->edx &= kvm_supported_word5_x86_features;
2595 cpuid_mask(&entry->edx, 5);
2596 break;
24c82e57
AK		 2597 case 3: /* Processor serial number */
2598 case 5: /* MONITOR/MWAIT */
2599 case 6: /* Thermal management */
2600 case 0xA: /* Architectural Performance Monitoring */
2601 case 0x80000007: /* Advanced power management */
4429d5dc
B		 2602 case 0xC0000002:
2603 case 0xC0000003:
2604 case 0xC0000004:
24c82e57
AK		 2605 default:
2606 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
4429d5dc 2607 break;
07716717 2608 }
d4330ef2
JR		 2609
2610 kvm_x86_ops->set_supported_cpuid(function, entry);
2611
07716717
DK		 2612 put_cpu();
2613}
2614
7faa4ee1
AK		 2615#undef F
2616
674eea0f 2617static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2618 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2619{
2620 struct kvm_cpuid_entry2 *cpuid_entries;
2621 int limit, nent = 0, r = -E2BIG;
2622 u32 func;
2623
2624 if (cpuid->nent < 1)
2625 goto out;
6a544355
AK		 2626 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2627 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2628 r = -ENOMEM;
2629 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2630 if (!cpuid_entries)
2631 goto out;
2632
2633 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2634 limit = cpuid_entries[0].eax;
2635 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2636 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2637 &nent, cpuid->nent);
07716717
DK		 2638 r = -E2BIG;
2639 if (nent >= cpuid->nent)
2640 goto out_free;
2641
2642 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2643 limit = cpuid_entries[nent - 1].eax;
2644 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2645 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2646 &nent, cpuid->nent);
84478c82
GC		 2647
2648
2649
2650 r = -E2BIG;
2651 if (nent >= cpuid->nent)
2652 goto out_free;
2653
4429d5dc
B		 2654 /* Add support for Centaur's CPUID instruction. */
2655 if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR) {
2656 do_cpuid_ent(&cpuid_entries[nent], 0xC0000000, 0,
2657 &nent, cpuid->nent);
2658
2659 r = -E2BIG;
2660 if (nent >= cpuid->nent)
2661 goto out_free;
2662
2663 limit = cpuid_entries[nent - 1].eax;
2664 for (func = 0xC0000001;
2665 func <= limit && nent < cpuid->nent; ++func)
2666 do_cpuid_ent(&cpuid_entries[nent], func, 0,
2667 &nent, cpuid->nent);
2668
2669 r = -E2BIG;
2670 if (nent >= cpuid->nent)
2671 goto out_free;
2672 }
2673
84478c82
GC		 2674 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2675 cpuid->nent);
2676
2677 r = -E2BIG;
2678 if (nent >= cpuid->nent)
2679 goto out_free;
2680
2681 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2682 cpuid->nent);
2683
cb007648
MM		 2684 r = -E2BIG;
2685 if (nent >= cpuid->nent)
2686 goto out_free;
2687
07716717
DK		 2688 r = -EFAULT;
2689 if (copy_to_user(entries, cpuid_entries,
19355475 2690 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2691 goto out_free;
2692 cpuid->nent = nent;
2693 r = 0;
2694
2695out_free:
2696 vfree(cpuid_entries);
2697out:
2698 return r;
2699}
2700
313a3dc7
CO		 2701static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2702 struct kvm_lapic_state *s)
2703{
ad312c7c 2704 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2705
2706 return 0;
2707}
2708
2709static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2710 struct kvm_lapic_state *s)
2711{
ad312c7c 2712 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2713 kvm_apic_post_state_restore(vcpu);
cb142eb7 2714 update_cr8_intercept(vcpu);
313a3dc7
CO		 2715
2716 return 0;
2717}
2718
f77bc6a4
ZX		 2719static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2720 struct kvm_interrupt *irq)
2721{
2722 if (irq->irq < 0 || irq->irq >= 256)
2723 return -EINVAL;
2724 if (irqchip_in_kernel(vcpu->kvm))
2725 return -ENXIO;
f77bc6a4 2726
66fd3f7f 2727 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2728 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2729
f77bc6a4
ZX		 2730 return 0;
2731}
2732
c4abb7c9
JK		 2733static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2734{
c4abb7c9 2735 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2736
2737 return 0;
2738}
2739
b209749f
AK		 2740static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2741 struct kvm_tpr_access_ctl *tac)
2742{
2743 if (tac->flags)
2744 return -EINVAL;
2745 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2746 return 0;
2747}
2748
890ca9ae
HY		 2749static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2750 u64 mcg_cap)
2751{
2752 int r;
2753 unsigned bank_num = mcg_cap & 0xff, bank;
2754
2755 r = -EINVAL;
a9e38c3e 2756 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2757 goto out;
2758 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2759 goto out;
2760 r = 0;
2761 vcpu->arch.mcg_cap = mcg_cap;
2762 /* Init IA32_MCG_CTL to all 1s */
2763 if (mcg_cap & MCG_CTL_P)
2764 vcpu->arch.mcg_ctl = ~(u64)0;
2765 /* Init IA32_MCi_CTL to all 1s */
2766 for (bank = 0; bank < bank_num; bank++)
2767 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2768out:
2769 return r;
2770}
2771
2772static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2773 struct kvm_x86_mce *mce)
2774{
2775 u64 mcg_cap = vcpu->arch.mcg_cap;
2776 unsigned bank_num = mcg_cap & 0xff;
2777 u64 *banks = vcpu->arch.mce_banks;
2778
2779 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2780 return -EINVAL;
2781 /*
2782 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2783 * reporting is disabled
2784 */
2785 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2786 vcpu->arch.mcg_ctl != ~(u64)0)
2787 return 0;
2788 banks += 4 * mce->bank;
2789 /*
2790 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2791 * reporting is disabled for the bank
2792 */
2793 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2794 return 0;
2795 if (mce->status & MCI_STATUS_UC) {
2796 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2797 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2798 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2799 return 0;
2800 }
2801 if (banks[1] & MCI_STATUS_VAL)
2802 mce->status |= MCI_STATUS_OVER;
2803 banks[2] = mce->addr;
2804 banks[3] = mce->misc;
2805 vcpu->arch.mcg_status = mce->mcg_status;
2806 banks[1] = mce->status;
2807 kvm_queue_exception(vcpu, MC_VECTOR);
2808 } else if (!(banks[1] & MCI_STATUS_VAL)
2809 || !(banks[1] & MCI_STATUS_UC)) {
2810 if (banks[1] & MCI_STATUS_VAL)
2811 mce->status |= MCI_STATUS_OVER;
2812 banks[2] = mce->addr;
2813 banks[3] = mce->misc;
2814 banks[1] = mce->status;
2815 } else
2816 banks[1] |= MCI_STATUS_OVER;
2817 return 0;
2818}
2819
3cfc3092
JK		 2820static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2821 struct kvm_vcpu_events *events)
2822{
03b82a30
JK		 2823 events->exception.injected =
2824 vcpu->arch.exception.pending &&
2825 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2826 events->exception.nr = vcpu->arch.exception.nr;
2827 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2828 events->exception.pad = 0;
3cfc3092
JK		 2829 events->exception.error_code = vcpu->arch.exception.error_code;
2830
03b82a30
JK		 2831 events->interrupt.injected =
2832 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2833 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2834 events->interrupt.soft = 0;
48005f64
JK		 2835 events->interrupt.shadow =
2836 kvm_x86_ops->get_interrupt_shadow(vcpu,
2837 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2838
2839 events->nmi.injected = vcpu->arch.nmi_injected;
2840 events->nmi.pending = vcpu->arch.nmi_pending;
2841 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2842 events->nmi.pad = 0;
3cfc3092
JK		 2843
2844 events->sipi_vector = vcpu->arch.sipi_vector;
2845
dab4b911 2846 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2847 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2848 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2849 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2850}
2851
2852static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2853 struct kvm_vcpu_events *events)
2854{
dab4b911 2855 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2856 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2857 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2858 return -EINVAL;
2859
3cfc3092
JK		 2860 vcpu->arch.exception.pending = events->exception.injected;
2861 vcpu->arch.exception.nr = events->exception.nr;
2862 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2863 vcpu->arch.exception.error_code = events->exception.error_code;
2864
2865 vcpu->arch.interrupt.pending = events->interrupt.injected;
2866 vcpu->arch.interrupt.nr = events->interrupt.nr;
2867 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2868 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2869 kvm_x86_ops->set_interrupt_shadow(vcpu,
2870 events->interrupt.shadow);
3cfc3092
JK		 2871
2872 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2873 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2874 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2875 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2876
dab4b911
JK		 2877 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2878 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2879
3842d135
AK		 2880 kvm_make_request(KVM_REQ_EVENT, vcpu);
2881
3cfc3092
JK		 2882 return 0;
2883}
2884
a1efbe77
JK		 2885static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2886 struct kvm_debugregs *dbgregs)
2887{
a1efbe77
JK		 2888 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2889 dbgregs->dr6 = vcpu->arch.dr6;
2890 dbgregs->dr7 = vcpu->arch.dr7;
2891 dbgregs->flags = 0;
97e69aa6 2892 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2893}
2894
2895static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2896 struct kvm_debugregs *dbgregs)
2897{
2898 if (dbgregs->flags)
2899 return -EINVAL;
2900
a1efbe77
JK		 2901 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2902 vcpu->arch.dr6 = dbgregs->dr6;
2903 vcpu->arch.dr7 = dbgregs->dr7;
2904
a1efbe77
JK		 2905 return 0;
2906}
2907
2d5b5a66
SY		 2908static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2909 struct kvm_xsave *guest_xsave)
2910{
2911 if (cpu_has_xsave)
2912 memcpy(guest_xsave->region,
2913 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2914 xstate_size);
2d5b5a66
SY		 2915 else {
2916 memcpy(guest_xsave->region,
2917 &vcpu->arch.guest_fpu.state->fxsave,
2918 sizeof(struct i387_fxsave_struct));
2919 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2920 XSTATE_FPSSE;
2921 }
2922}
2923
2924static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2925 struct kvm_xsave *guest_xsave)
2926{
2927 u64 xstate_bv =
2928 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2929
2930 if (cpu_has_xsave)
2931 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2932 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2933 else {
2934 if (xstate_bv & ~XSTATE_FPSSE)
2935 return -EINVAL;
2936 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2937 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2938 }
2939 return 0;
2940}
2941
2942static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2943 struct kvm_xcrs *guest_xcrs)
2944{
2945 if (!cpu_has_xsave) {
2946 guest_xcrs->nr_xcrs = 0;
2947 return;
2948 }
2949
2950 guest_xcrs->nr_xcrs = 1;
2951 guest_xcrs->flags = 0;
2952 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2953 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2954}
2955
2956static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2957 struct kvm_xcrs *guest_xcrs)
2958{
2959 int i, r = 0;
2960
2961 if (!cpu_has_xsave)
2962 return -EINVAL;
2963
2964 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2965 return -EINVAL;
2966
2967 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2968 /* Only support XCR0 currently */
2969 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2970 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2971 guest_xcrs->xcrs[0].value);
2972 break;
2973 }
2974 if (r)
2975 r = -EINVAL;
2976 return r;
2977}
2978
313a3dc7
CO		 2979long kvm_arch_vcpu_ioctl(struct file *filp,
2980 unsigned int ioctl, unsigned long arg)
2981{
2982 struct kvm_vcpu *vcpu = filp->private_data;
2983 void __user *argp = (void __user *)arg;
2984 int r;
d1ac91d8
AK		 2985 union {
2986 struct kvm_lapic_state *lapic;
2987 struct kvm_xsave *xsave;
2988 struct kvm_xcrs *xcrs;
2989 void *buffer;
2990 } u;
2991
2992 u.buffer = NULL;
313a3dc7
CO		 2993 switch (ioctl) {
2994 case KVM_GET_LAPIC: {
2204ae3c
MT		 2995 r = -EINVAL;
2996 if (!vcpu->arch.apic)
2997 goto out;
d1ac91d8 2998 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2999
b772ff36 3000 r = -ENOMEM;
d1ac91d8 3001 if (!u.lapic)
b772ff36 3002 goto out;
d1ac91d8 3003 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3004 if (r)
3005 goto out;
3006 r = -EFAULT;
d1ac91d8 3007 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3008 goto out;
3009 r = 0;
3010 break;
3011 }
3012 case KVM_SET_LAPIC: {
2204ae3c
MT		 3013 r = -EINVAL;
3014 if (!vcpu->arch.apic)
3015 goto out;
d1ac91d8 3016 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 3017 r = -ENOMEM;
d1ac91d8 3018 if (!u.lapic)
b772ff36 3019 goto out;
313a3dc7 3020 r = -EFAULT;
d1ac91d8 3021 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 3022 goto out;
d1ac91d8 3023 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3024 if (r)
3025 goto out;
3026 r = 0;
3027 break;
3028 }
f77bc6a4
ZX		 3029 case KVM_INTERRUPT: {
3030 struct kvm_interrupt irq;
3031
3032 r = -EFAULT;
3033 if (copy_from_user(&irq, argp, sizeof irq))
3034 goto out;
3035 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3036 if (r)
3037 goto out;
3038 r = 0;
3039 break;
3040 }
c4abb7c9
JK		 3041 case KVM_NMI: {
3042 r = kvm_vcpu_ioctl_nmi(vcpu);
3043 if (r)
3044 goto out;
3045 r = 0;
3046 break;
3047 }
313a3dc7
CO		 3048 case KVM_SET_CPUID: {
3049 struct kvm_cpuid __user *cpuid_arg = argp;
3050 struct kvm_cpuid cpuid;
3051
3052 r = -EFAULT;
3053 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3054 goto out;
3055 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3056 if (r)
3057 goto out;
3058 break;
3059 }
07716717
DK		 3060 case KVM_SET_CPUID2: {
3061 struct kvm_cpuid2 __user *cpuid_arg = argp;
3062 struct kvm_cpuid2 cpuid;
3063
3064 r = -EFAULT;
3065 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3066 goto out;
3067 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3068 cpuid_arg->entries);
07716717
DK		 3069 if (r)
3070 goto out;
3071 break;
3072 }
3073 case KVM_GET_CPUID2: {
3074 struct kvm_cpuid2 __user *cpuid_arg = argp;
3075 struct kvm_cpuid2 cpuid;
3076
3077 r = -EFAULT;
3078 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3079 goto out;
3080 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3081 cpuid_arg->entries);
07716717
DK		 3082 if (r)
3083 goto out;
3084 r = -EFAULT;
3085 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3086 goto out;
3087 r = 0;
3088 break;
3089 }
313a3dc7
CO		 3090 case KVM_GET_MSRS:
3091 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3092 break;
3093 case KVM_SET_MSRS:
3094 r = msr_io(vcpu, argp, do_set_msr, 0);
3095 break;
b209749f
AK		 3096 case KVM_TPR_ACCESS_REPORTING: {
3097 struct kvm_tpr_access_ctl tac;
3098
3099 r = -EFAULT;
3100 if (copy_from_user(&tac, argp, sizeof tac))
3101 goto out;
3102 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3103 if (r)
3104 goto out;
3105 r = -EFAULT;
3106 if (copy_to_user(argp, &tac, sizeof tac))
3107 goto out;
3108 r = 0;
3109 break;
3110 };
b93463aa
AK		 3111 case KVM_SET_VAPIC_ADDR: {
3112 struct kvm_vapic_addr va;
3113
3114 r = -EINVAL;
3115 if (!irqchip_in_kernel(vcpu->kvm))
3116 goto out;
3117 r = -EFAULT;
3118 if (copy_from_user(&va, argp, sizeof va))
3119 goto out;
3120 r = 0;
3121 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3122 break;
3123 }
890ca9ae
HY		 3124 case KVM_X86_SETUP_MCE: {
3125 u64 mcg_cap;
3126
3127 r = -EFAULT;
3128 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3129 goto out;
3130 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3131 break;
3132 }
3133 case KVM_X86_SET_MCE: {
3134 struct kvm_x86_mce mce;
3135
3136 r = -EFAULT;
3137 if (copy_from_user(&mce, argp, sizeof mce))
3138 goto out;
3139 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3140 break;
3141 }
3cfc3092
JK		 3142 case KVM_GET_VCPU_EVENTS: {
3143 struct kvm_vcpu_events events;
3144
3145 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3146
3147 r = -EFAULT;
3148 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3149 break;
3150 r = 0;
3151 break;
3152 }
3153 case KVM_SET_VCPU_EVENTS: {
3154 struct kvm_vcpu_events events;
3155
3156 r = -EFAULT;
3157 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3158 break;
3159
3160 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3161 break;
3162 }
a1efbe77
JK		 3163 case KVM_GET_DEBUGREGS: {
3164 struct kvm_debugregs dbgregs;
3165
3166 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3167
3168 r = -EFAULT;
3169 if (copy_to_user(argp, &dbgregs,
3170 sizeof(struct kvm_debugregs)))
3171 break;
3172 r = 0;
3173 break;
3174 }
3175 case KVM_SET_DEBUGREGS: {
3176 struct kvm_debugregs dbgregs;
3177
3178 r = -EFAULT;
3179 if (copy_from_user(&dbgregs, argp,
3180 sizeof(struct kvm_debugregs)))
3181 break;
3182
3183 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3184 break;
3185 }
2d5b5a66 3186 case KVM_GET_XSAVE: {
d1ac91d8 3187 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3188 r = -ENOMEM;
d1ac91d8 3189 if (!u.xsave)
2d5b5a66
SY		 3190 break;
3191
d1ac91d8 3192 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3193
3194 r = -EFAULT;
d1ac91d8 3195 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3196 break;
3197 r = 0;
3198 break;
3199 }
3200 case KVM_SET_XSAVE: {
d1ac91d8 3201 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3202 r = -ENOMEM;
d1ac91d8 3203 if (!u.xsave)
2d5b5a66
SY		 3204 break;
3205
3206 r = -EFAULT;
d1ac91d8 3207 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3208 break;
3209
d1ac91d8 3210 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3211 break;
3212 }
3213 case KVM_GET_XCRS: {
d1ac91d8 3214 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3215 r = -ENOMEM;
d1ac91d8 3216 if (!u.xcrs)
2d5b5a66
SY		 3217 break;
3218
d1ac91d8 3219 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3220
3221 r = -EFAULT;
d1ac91d8 3222 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3223 sizeof(struct kvm_xcrs)))
3224 break;
3225 r = 0;
3226 break;
3227 }
3228 case KVM_SET_XCRS: {
d1ac91d8 3229 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3230 r = -ENOMEM;
d1ac91d8 3231 if (!u.xcrs)
2d5b5a66
SY		 3232 break;
3233
3234 r = -EFAULT;
d1ac91d8 3235 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 3236 sizeof(struct kvm_xcrs)))
3237 break;
3238
d1ac91d8 3239 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3240 break;
3241 }
92a1f12d
JR		 3242 case KVM_SET_TSC_KHZ: {
3243 u32 user_tsc_khz;
3244
3245 r = -EINVAL;
3246 if (!kvm_has_tsc_control)
3247 break;
3248
3249 user_tsc_khz = (u32)arg;
3250
3251 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3252 goto out;
3253
3254 kvm_x86_ops->set_tsc_khz(vcpu, user_tsc_khz);
3255
3256 r = 0;
3257 goto out;
3258 }
3259 case KVM_GET_TSC_KHZ: {
3260 r = -EIO;
3261 if (check_tsc_unstable())
3262 goto out;
3263
3264 r = vcpu_tsc_khz(vcpu);
3265
3266 goto out;
3267 }
313a3dc7
CO		 3268 default:
3269 r = -EINVAL;
3270 }
3271out:
d1ac91d8 3272 kfree(u.buffer);
313a3dc7
CO		 3273 return r;
3274}
3275
1fe779f8
CO		 3276static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3277{
3278 int ret;
3279
3280 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3281 return -1;
3282 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3283 return ret;
3284}
3285
b927a3ce
SY		 3286static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3287 u64 ident_addr)
3288{
3289 kvm->arch.ept_identity_map_addr = ident_addr;
3290 return 0;
3291}
3292
1fe779f8
CO		 3293static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3294 u32 kvm_nr_mmu_pages)
3295{
3296 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3297 return -EINVAL;
3298
79fac95e 3299 mutex_lock(&kvm->slots_lock);
7c8a83b7 3300 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 3301
3302 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3303 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3304
7c8a83b7 3305 spin_unlock(&kvm->mmu_lock);
79fac95e 3306 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3307 return 0;
3308}
3309
3310static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3311{
39de71ec 3312 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3313}
3314
1fe779f8
CO		 3315static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3316{
3317 int r;
3318
3319 r = 0;
3320 switch (chip->chip_id) {
3321 case KVM_IRQCHIP_PIC_MASTER:
3322 memcpy(&chip->chip.pic,
3323 &pic_irqchip(kvm)->pics[0],
3324 sizeof(struct kvm_pic_state));
3325 break;
3326 case KVM_IRQCHIP_PIC_SLAVE:
3327 memcpy(&chip->chip.pic,
3328 &pic_irqchip(kvm)->pics[1],
3329 sizeof(struct kvm_pic_state));
3330 break;
3331 case KVM_IRQCHIP_IOAPIC:
eba0226b 3332 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3333 break;
3334 default:
3335 r = -EINVAL;
3336 break;
3337 }
3338 return r;
3339}
3340
3341static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3342{
3343 int r;
3344
3345 r = 0;
3346 switch (chip->chip_id) {
3347 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3348 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3349 memcpy(&pic_irqchip(kvm)->pics[0],
3350 &chip->chip.pic,
3351 sizeof(struct kvm_pic_state));
f4f51050 3352 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3353 break;
3354 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3355 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3356 memcpy(&pic_irqchip(kvm)->pics[1],
3357 &chip->chip.pic,
3358 sizeof(struct kvm_pic_state));
f4f51050 3359 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3360 break;
3361 case KVM_IRQCHIP_IOAPIC:
eba0226b 3362 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3363 break;
3364 default:
3365 r = -EINVAL;
3366 break;
3367 }
3368 kvm_pic_update_irq(pic_irqchip(kvm));
3369 return r;
3370}
3371
e0f63cb9
SY		 3372static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3373{
3374 int r = 0;
3375
894a9c55 3376 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3377 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3378 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3379 return r;
3380}
3381
3382static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3383{
3384 int r = 0;
3385
894a9c55 3386 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3387 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3388 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3389 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3390 return r;
3391}
3392
3393static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3394{
3395 int r = 0;
3396
3397 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3398 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3399 sizeof(ps->channels));
3400 ps->flags = kvm->arch.vpit->pit_state.flags;
3401 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3402 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3403 return r;
3404}
3405
3406static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3407{
3408 int r = 0, start = 0;
3409 u32 prev_legacy, cur_legacy;
3410 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3411 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3412 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3413 if (!prev_legacy && cur_legacy)
3414 start = 1;
3415 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3416 sizeof(kvm->arch.vpit->pit_state.channels));
3417 kvm->arch.vpit->pit_state.flags = ps->flags;
3418 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3419 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3420 return r;
3421}
3422
52d939a0
MT		 3423static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3424 struct kvm_reinject_control *control)
3425{
3426 if (!kvm->arch.vpit)
3427 return -ENXIO;
894a9c55 3428 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3429 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3430 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3431 return 0;
3432}
3433
5bb064dc
ZX		 3434/*
3435 * Get (and clear) the dirty memory log for a memory slot.
3436 */
3437int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3438 struct kvm_dirty_log *log)
3439{
87bf6e7d 3440 int r, i;
5bb064dc 3441 struct kvm_memory_slot *memslot;
87bf6e7d 3442 unsigned long n;
b050b015 3443 unsigned long is_dirty = 0;
5bb064dc 3444
79fac95e 3445 mutex_lock(&kvm->slots_lock);
5bb064dc 3446
b050b015
MT		 3447 r = -EINVAL;
3448 if (log->slot >= KVM_MEMORY_SLOTS)
3449 goto out;
3450
3451 memslot = &kvm->memslots->memslots[log->slot];
3452 r = -ENOENT;
3453 if (!memslot->dirty_bitmap)
3454 goto out;
3455
87bf6e7d 3456 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3457
b050b015
MT		 3458 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3459 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3460
3461 /* If nothing is dirty, don't bother messing with page tables. */
3462 if (is_dirty) {
b050b015 3463 struct kvm_memslots *slots, *old_slots;
914ebccd 3464 unsigned long *dirty_bitmap;
b050b015 3465
515a0127
TY		 3466 dirty_bitmap = memslot->dirty_bitmap_head;
3467 if (memslot->dirty_bitmap == dirty_bitmap)
3468 dirty_bitmap += n / sizeof(long);
914ebccd 3469 memset(dirty_bitmap, 0, n);
b050b015 3470
914ebccd
TY		 3471 r = -ENOMEM;
3472 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
515a0127 3473 if (!slots)
914ebccd 3474 goto out;
b050b015
MT		 3475 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3476 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
49c7754c 3477 slots->generation++;
b050b015
MT		 3478
3479 old_slots = kvm->memslots;
3480 rcu_assign_pointer(kvm->memslots, slots);
3481 synchronize_srcu_expedited(&kvm->srcu);
3482 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3483 kfree(old_slots);
914ebccd 3484
edde99ce
MT		 3485 spin_lock(&kvm->mmu_lock);
3486 kvm_mmu_slot_remove_write_access(kvm, log->slot);
3487 spin_unlock(&kvm->mmu_lock);
3488
914ebccd 3489 r = -EFAULT;
515a0127 3490 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
914ebccd 3491 goto out;
914ebccd
TY		 3492 } else {
3493 r = -EFAULT;
3494 if (clear_user(log->dirty_bitmap, n))
3495 goto out;
5bb064dc 3496 }
b050b015 3497
5bb064dc
ZX		 3498 r = 0;
3499out:
79fac95e 3500 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3501 return r;
3502}
3503
1fe779f8
CO		 3504long kvm_arch_vm_ioctl(struct file *filp,
3505 unsigned int ioctl, unsigned long arg)
3506{
3507 struct kvm *kvm = filp->private_data;
3508 void __user *argp = (void __user *)arg;
367e1319 3509 int r = -ENOTTY;
f0d66275
DH		 3510 /*
3511 * This union makes it completely explicit to gcc-3.x
3512 * that these two variables' stack usage should be
3513 * combined, not added together.
3514 */
3515 union {
3516 struct kvm_pit_state ps;
e9f42757 3517 struct kvm_pit_state2 ps2;
c5ff41ce 3518 struct kvm_pit_config pit_config;
f0d66275 3519 } u;
1fe779f8
CO		 3520
3521 switch (ioctl) {
3522 case KVM_SET_TSS_ADDR:
3523 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3524 if (r < 0)
3525 goto out;
3526 break;
b927a3ce
SY		 3527 case KVM_SET_IDENTITY_MAP_ADDR: {
3528 u64 ident_addr;
3529
3530 r = -EFAULT;
3531 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3532 goto out;
3533 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3534 if (r < 0)
3535 goto out;
3536 break;
3537 }
1fe779f8
CO		 3538 case KVM_SET_NR_MMU_PAGES:
3539 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3540 if (r)
3541 goto out;
3542 break;
3543 case KVM_GET_NR_MMU_PAGES:
3544 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3545 break;
3ddea128
MT		 3546 case KVM_CREATE_IRQCHIP: {
3547 struct kvm_pic *vpic;
3548
3549 mutex_lock(&kvm->lock);
3550 r = -EEXIST;
3551 if (kvm->arch.vpic)
3552 goto create_irqchip_unlock;
1fe779f8 3553 r = -ENOMEM;
3ddea128
MT		 3554 vpic = kvm_create_pic(kvm);
3555 if (vpic) {
1fe779f8
CO		 3556 r = kvm_ioapic_init(kvm);
3557 if (r) {
175504cd 3558 mutex_lock(&kvm->slots_lock);
72bb2fcd
WY		 3559 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3560 &vpic->dev);
175504cd 3561 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3562 kfree(vpic);
3563 goto create_irqchip_unlock;
1fe779f8
CO		 3564 }
3565 } else
3ddea128
MT		 3566 goto create_irqchip_unlock;
3567 smp_wmb();
3568 kvm->arch.vpic = vpic;
3569 smp_wmb();
399ec807
AK		 3570 r = kvm_setup_default_irq_routing(kvm);
3571 if (r) {
175504cd 3572 mutex_lock(&kvm->slots_lock);
3ddea128 3573 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3574 kvm_ioapic_destroy(kvm);
3575 kvm_destroy_pic(kvm);
3ddea128 3576 mutex_unlock(&kvm->irq_lock);
175504cd 3577 mutex_unlock(&kvm->slots_lock);
399ec807 3578 }
3ddea128
MT		 3579 create_irqchip_unlock:
3580 mutex_unlock(&kvm->lock);
1fe779f8 3581 break;
3ddea128 3582 }
7837699f 3583 case KVM_CREATE_PIT:
c5ff41ce
JK		 3584 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3585 goto create_pit;
3586 case KVM_CREATE_PIT2:
3587 r = -EFAULT;
3588 if (copy_from_user(&u.pit_config, argp,
3589 sizeof(struct kvm_pit_config)))
3590 goto out;
3591 create_pit:
79fac95e 3592 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3593 r = -EEXIST;
3594 if (kvm->arch.vpit)
3595 goto create_pit_unlock;
7837699f 3596 r = -ENOMEM;
c5ff41ce 3597 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3598 if (kvm->arch.vpit)
3599 r = 0;
269e05e4 3600 create_pit_unlock:
79fac95e 3601 mutex_unlock(&kvm->slots_lock);
7837699f 3602 break;
4925663a 3603 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3604 case KVM_IRQ_LINE: {
3605 struct kvm_irq_level irq_event;
3606
3607 r = -EFAULT;
3608 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3609 goto out;
160d2f6c 3610 r = -ENXIO;
1fe779f8 3611 if (irqchip_in_kernel(kvm)) {
4925663a 3612 __s32 status;
4925663a
GN		 3613 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3614 irq_event.irq, irq_event.level);
4925663a 3615 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3616 r = -EFAULT;
4925663a
GN		 3617 irq_event.status = status;
3618 if (copy_to_user(argp, &irq_event,
3619 sizeof irq_event))
3620 goto out;
3621 }
1fe779f8
CO		 3622 r = 0;
3623 }
3624 break;
3625 }
3626 case KVM_GET_IRQCHIP: {
3627 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3628 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3629
f0d66275
DH		 3630 r = -ENOMEM;
3631 if (!chip)
1fe779f8 3632 goto out;
f0d66275
DH		 3633 r = -EFAULT;
3634 if (copy_from_user(chip, argp, sizeof *chip))
3635 goto get_irqchip_out;
1fe779f8
CO		 3636 r = -ENXIO;
3637 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3638 goto get_irqchip_out;
3639 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3640 if (r)
f0d66275 3641 goto get_irqchip_out;
1fe779f8 3642 r = -EFAULT;
f0d66275
DH		 3643 if (copy_to_user(argp, chip, sizeof *chip))
3644 goto get_irqchip_out;
1fe779f8 3645 r = 0;
f0d66275
DH		 3646 get_irqchip_out:
3647 kfree(chip);
3648 if (r)
3649 goto out;
1fe779f8
CO		 3650 break;
3651 }
3652 case KVM_SET_IRQCHIP: {
3653 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3654 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3655
f0d66275
DH		 3656 r = -ENOMEM;
3657 if (!chip)
1fe779f8 3658 goto out;
f0d66275
DH		 3659 r = -EFAULT;
3660 if (copy_from_user(chip, argp, sizeof *chip))
3661 goto set_irqchip_out;
1fe779f8
CO		 3662 r = -ENXIO;
3663 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3664 goto set_irqchip_out;
3665 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3666 if (r)
f0d66275 3667 goto set_irqchip_out;
1fe779f8 3668 r = 0;
f0d66275
DH		 3669 set_irqchip_out:
3670 kfree(chip);
3671 if (r)
3672 goto out;
1fe779f8
CO		 3673 break;
3674 }
e0f63cb9 3675 case KVM_GET_PIT: {
e0f63cb9 3676 r = -EFAULT;
f0d66275 3677 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3678 goto out;
3679 r = -ENXIO;
3680 if (!kvm->arch.vpit)
3681 goto out;
f0d66275 3682 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3683 if (r)
3684 goto out;
3685 r = -EFAULT;
f0d66275 3686 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3687 goto out;
3688 r = 0;
3689 break;
3690 }
3691 case KVM_SET_PIT: {
e0f63cb9 3692 r = -EFAULT;
f0d66275 3693 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3694 goto out;
3695 r = -ENXIO;
3696 if (!kvm->arch.vpit)
3697 goto out;
f0d66275 3698 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3699 if (r)
3700 goto out;
3701 r = 0;
3702 break;
3703 }
e9f42757
BK		 3704 case KVM_GET_PIT2: {
3705 r = -ENXIO;
3706 if (!kvm->arch.vpit)
3707 goto out;
3708 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3709 if (r)
3710 goto out;
3711 r = -EFAULT;
3712 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3713 goto out;
3714 r = 0;
3715 break;
3716 }
3717 case KVM_SET_PIT2: {
3718 r = -EFAULT;
3719 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3720 goto out;
3721 r = -ENXIO;
3722 if (!kvm->arch.vpit)
3723 goto out;
3724 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3725 if (r)
3726 goto out;
3727 r = 0;
3728 break;
3729 }
52d939a0
MT		 3730 case KVM_REINJECT_CONTROL: {
3731 struct kvm_reinject_control control;
3732 r = -EFAULT;
3733 if (copy_from_user(&control, argp, sizeof(control)))
3734 goto out;
3735 r = kvm_vm_ioctl_reinject(kvm, &control);
3736 if (r)
3737 goto out;
3738 r = 0;
3739 break;
3740 }
ffde22ac
ES		 3741 case KVM_XEN_HVM_CONFIG: {
3742 r = -EFAULT;
3743 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3744 sizeof(struct kvm_xen_hvm_config)))
3745 goto out;
3746 r = -EINVAL;
3747 if (kvm->arch.xen_hvm_config.flags)
3748 goto out;
3749 r = 0;
3750 break;
3751 }
afbcf7ab 3752 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3753 struct kvm_clock_data user_ns;
3754 u64 now_ns;
3755 s64 delta;
3756
3757 r = -EFAULT;
3758 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3759 goto out;
3760
3761 r = -EINVAL;
3762 if (user_ns.flags)
3763 goto out;
3764
3765 r = 0;
395c6b0a 3766 local_irq_disable();
759379dd 3767 now_ns = get_kernel_ns();
afbcf7ab 3768 delta = user_ns.clock - now_ns;
395c6b0a 3769 local_irq_enable();
afbcf7ab
GC		 3770 kvm->arch.kvmclock_offset = delta;
3771 break;
3772 }
3773 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3774 struct kvm_clock_data user_ns;
3775 u64 now_ns;
3776
395c6b0a 3777 local_irq_disable();
759379dd 3778 now_ns = get_kernel_ns();
afbcf7ab 3779 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3780 local_irq_enable();
afbcf7ab 3781 user_ns.flags = 0;
97e69aa6 3782 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3783
3784 r = -EFAULT;
3785 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3786 goto out;
3787 r = 0;
3788 break;
3789 }
3790
1fe779f8
CO		 3791 default:
3792 ;
3793 }
3794out:
3795 return r;
3796}
3797
a16b043c 3798static void kvm_init_msr_list(void)
043405e1
CO		 3799{
3800 u32 dummy[2];
3801 unsigned i, j;
3802
e3267cbb
GC		 3803 /* skip the first msrs in the list. KVM-specific */
3804 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3805 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3806 continue;
3807 if (j < i)
3808 msrs_to_save[j] = msrs_to_save[i];
3809 j++;
3810 }
3811 num_msrs_to_save = j;
3812}
3813
bda9020e
MT		 3814static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3815 const void *v)
bbd9b64e 3816{
70252a10
AK		 3817 int handled = 0;
3818 int n;
3819
3820 do {
3821 n = min(len, 8);
3822 if (!(vcpu->arch.apic &&
3823 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3824 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3825 break;
3826 handled += n;
3827 addr += n;
3828 len -= n;
3829 v += n;
3830 } while (len);
bbd9b64e 3831
70252a10 3832 return handled;
bbd9b64e
CO		 3833}
3834
bda9020e 3835static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3836{
70252a10
AK		 3837 int handled = 0;
3838 int n;
3839
3840 do {
3841 n = min(len, 8);
3842 if (!(vcpu->arch.apic &&
3843 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3844 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3845 break;
3846 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3847 handled += n;
3848 addr += n;
3849 len -= n;
3850 v += n;
3851 } while (len);
bbd9b64e 3852
70252a10 3853 return handled;
bbd9b64e
CO		 3854}
3855
2dafc6c2
GN		 3856static void kvm_set_segment(struct kvm_vcpu *vcpu,
3857 struct kvm_segment *var, int seg)
3858{
3859 kvm_x86_ops->set_segment(vcpu, var, seg);
3860}
3861
3862void kvm_get_segment(struct kvm_vcpu *vcpu,
3863 struct kvm_segment *var, int seg)
3864{
3865 kvm_x86_ops->get_segment(vcpu, var, seg);
3866}
3867
c30a358d
JR		 3868static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3869{
3870 return gpa;
3871}
3872
02f59dc9
JR		 3873static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3874{
3875 gpa_t t_gpa;
ab9ae313 3876 struct x86_exception exception;
02f59dc9
JR		 3877
3878 BUG_ON(!mmu_is_nested(vcpu));
3879
3880 /* NPT walks are always user-walks */
3881 access |= PFERR_USER_MASK;
ab9ae313 3882 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3883
3884 return t_gpa;
3885}
3886
ab9ae313
AK		 3887gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3888 struct x86_exception *exception)
1871c602
GN		 3889{
3890 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3891 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3892}
3893
ab9ae313
AK		 3894 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3895 struct x86_exception *exception)
1871c602
GN		 3896{
3897 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3898 access |= PFERR_FETCH_MASK;
ab9ae313 3899 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3900}
3901
ab9ae313
AK		 3902gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3903 struct x86_exception *exception)
1871c602
GN		 3904{
3905 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3906 access |= PFERR_WRITE_MASK;
ab9ae313 3907 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3908}
3909
3910/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3911gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3912 struct x86_exception *exception)
1871c602 3913{
ab9ae313 3914 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3915}
3916
3917static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3918 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3919 struct x86_exception *exception)
bbd9b64e
CO		 3920{
3921 void *data = val;
10589a46 3922 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3923
3924 while (bytes) {
14dfe855 3925 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3926 exception);
bbd9b64e 3927 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3928 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3929 int ret;
3930
bcc55cba 3931 if (gpa == UNMAPPED_GVA)
ab9ae313 3932 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3933 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3934 if (ret < 0) {
c3cd7ffa 3935 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3936 goto out;
3937 }
bbd9b64e 3938
77c2002e
IE		 3939 bytes -= toread;
3940 data += toread;
3941 addr += toread;
bbd9b64e 3942 }
10589a46 3943out:
10589a46 3944 return r;
bbd9b64e 3945}
77c2002e 3946
1871c602 3947/* used for instruction fetching */
0f65dd70
AK		 3948static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3949 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3950 struct x86_exception *exception)
1871c602 3951{
0f65dd70 3952 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3953 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3954
1871c602 3955 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3956 access | PFERR_FETCH_MASK,
3957 exception);
1871c602
GN		 3958}
3959
064aea77 3960int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3961 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3962 struct x86_exception *exception)
1871c602 3963{
0f65dd70 3964 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3965 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3966
1871c602 3967 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3968 exception);
1871c602 3969}
064aea77 3970EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 3971
0f65dd70
AK		 3972static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3973 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3974 struct x86_exception *exception)
1871c602 3975{
0f65dd70 3976 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 3977 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3978}
3979
6a4d7550 3980int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 3981 gva_t addr, void *val,
2dafc6c2 3982 unsigned int bytes,
bcc55cba 3983 struct x86_exception *exception)
77c2002e 3984{
0f65dd70 3985 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 3986 void *data = val;
3987 int r = X86EMUL_CONTINUE;
3988
3989 while (bytes) {
14dfe855
JR		 3990 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3991 PFERR_WRITE_MASK,
ab9ae313 3992 exception);
77c2002e
IE		 3993 unsigned offset = addr & (PAGE_SIZE-1);
3994 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3995 int ret;
3996
bcc55cba 3997 if (gpa == UNMAPPED_GVA)
ab9ae313 3998 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3999 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4000 if (ret < 0) {
c3cd7ffa 4001 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4002 goto out;
4003 }
4004
4005 bytes -= towrite;
4006 data += towrite;
4007 addr += towrite;
4008 }
4009out:
4010 return r;
4011}
6a4d7550 4012EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4013
af7cc7d1
XG		 4014static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4015 gpa_t *gpa, struct x86_exception *exception,
4016 bool write)
4017{
4018 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4019
bebb106a
XG		 4020 if (vcpu_match_mmio_gva(vcpu, gva) &&
4021 check_write_user_access(vcpu, write, access,
4022 vcpu->arch.access)) {
4023 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4024 (gva & (PAGE_SIZE - 1));
4f022648 4025 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4026 return 1;
4027 }
4028
af7cc7d1
XG		 4029 if (write)
4030 access |= PFERR_WRITE_MASK;
4031
4032 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4033
4034 if (*gpa == UNMAPPED_GVA)
4035 return -1;
4036
4037 /* For APIC access vmexit */
4038 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4039 return 1;
4040
4f022648
XG		 4041 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4042 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4043 return 1;
4f022648 4044 }
bebb106a 4045
af7cc7d1
XG		 4046 return 0;
4047}
4048
0f65dd70
AK		 4049static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4050 unsigned long addr,
bbd9b64e
CO		 4051 void *val,
4052 unsigned int bytes,
0f65dd70 4053 struct x86_exception *exception)
bbd9b64e 4054{
0f65dd70 4055 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
af7cc7d1
XG		 4056 gpa_t gpa;
4057 int handled, ret;
bbd9b64e
CO		 4058
4059 if (vcpu->mmio_read_completed) {
4060 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 4061 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4062 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 4063 vcpu->mmio_read_completed = 0;
4064 return X86EMUL_CONTINUE;
4065 }
4066
af7cc7d1 4067 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, false);
1871c602 4068
af7cc7d1 4069 if (ret < 0)
1871c602 4070 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e 4071
af7cc7d1 4072 if (ret)
bbd9b64e
CO		 4073 goto mmio;
4074
0f65dd70 4075 if (kvm_read_guest_virt(ctxt, addr, val, bytes, exception)
bcc55cba 4076 == X86EMUL_CONTINUE)
bbd9b64e 4077 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4078
4079mmio:
4080 /*
4081 * Is this MMIO handled locally?
4082 */
70252a10
AK		 4083 handled = vcpu_mmio_read(vcpu, gpa, bytes, val);
4084
4085 if (handled == bytes)
bbd9b64e 4086 return X86EMUL_CONTINUE;
70252a10
AK		 4087
4088 gpa += handled;
4089 bytes -= handled;
4090 val += handled;
aec51dc4
AK		 4091
4092 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 4093
4094 vcpu->mmio_needed = 1;
411c35b7
GN		 4095 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4096 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
cef4dea0
AK		 4097 vcpu->mmio_size = bytes;
4098 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
411c35b7 4099 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
cef4dea0 4100 vcpu->mmio_index = 0;
bbd9b64e 4101
c3cd7ffa 4102 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 4103}
4104
3200f405 4105int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4106 const void *val, int bytes)
bbd9b64e
CO		 4107{
4108 int ret;
4109
4110 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4111 if (ret < 0)
bbd9b64e 4112 return 0;
ad218f85 4113 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 4114 return 1;
4115}
4116
4117static int emulator_write_emulated_onepage(unsigned long addr,
4118 const void *val,
4119 unsigned int bytes,
bcc55cba 4120 struct x86_exception *exception,
bbd9b64e
CO		 4121 struct kvm_vcpu *vcpu)
4122{
af7cc7d1
XG		 4123 gpa_t gpa;
4124 int handled, ret;
10589a46 4125
af7cc7d1 4126 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, true);
bbd9b64e 4127
af7cc7d1 4128 if (ret < 0)
bbd9b64e 4129 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4130
4131 /* For APIC access vmexit */
af7cc7d1 4132 if (ret)
bbd9b64e
CO		 4133 goto mmio;
4134
4135 if (emulator_write_phys(vcpu, gpa, val, bytes))
4136 return X86EMUL_CONTINUE;
4137
4138mmio:
aec51dc4 4139 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 4140 /*
4141 * Is this MMIO handled locally?
4142 */
70252a10
AK		 4143 handled = vcpu_mmio_write(vcpu, gpa, bytes, val);
4144 if (handled == bytes)
bbd9b64e 4145 return X86EMUL_CONTINUE;
bbd9b64e 4146
70252a10
AK		 4147 gpa += handled;
4148 bytes -= handled;
4149 val += handled;
4150
bbd9b64e 4151 vcpu->mmio_needed = 1;
cef4dea0 4152 memcpy(vcpu->mmio_data, val, bytes);
411c35b7
GN		 4153 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4154 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
cef4dea0
AK		 4155 vcpu->mmio_size = bytes;
4156 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
411c35b7 4157 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
cef4dea0
AK		 4158 memcpy(vcpu->run->mmio.data, vcpu->mmio_data, 8);
4159 vcpu->mmio_index = 0;
bbd9b64e
CO		 4160
4161 return X86EMUL_CONTINUE;
4162}
4163
0f65dd70
AK		 4164int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4165 unsigned long addr,
8f6abd06
GN		 4166 const void *val,
4167 unsigned int bytes,
0f65dd70 4168 struct x86_exception *exception)
bbd9b64e 4169{
0f65dd70
AK		 4170 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4171
bbd9b64e
CO		 4172 /* Crossing a page boundary? */
4173 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4174 int rc, now;
4175
4176 now = -addr & ~PAGE_MASK;
bcc55cba 4177 rc = emulator_write_emulated_onepage(addr, val, now, exception,
8fe681e9 4178 vcpu);
bbd9b64e
CO		 4179 if (rc != X86EMUL_CONTINUE)
4180 return rc;
4181 addr += now;
4182 val += now;
4183 bytes -= now;
4184 }
bcc55cba 4185 return emulator_write_emulated_onepage(addr, val, bytes, exception,
8fe681e9 4186 vcpu);
bbd9b64e 4187}
bbd9b64e 4188
daea3e73
AK		 4189#define CMPXCHG_TYPE(t, ptr, old, new) \
4190 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4191
4192#ifdef CONFIG_X86_64
4193# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4194#else
4195# define CMPXCHG64(ptr, old, new) \
9749a6c0 4196 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4197#endif
4198
0f65dd70
AK		 4199static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4200 unsigned long addr,
bbd9b64e
CO		 4201 const void *old,
4202 const void *new,
4203 unsigned int bytes,
0f65dd70 4204 struct x86_exception *exception)
bbd9b64e 4205{
0f65dd70 4206 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4207 gpa_t gpa;
4208 struct page *page;
4209 char *kaddr;
4210 bool exchanged;
2bacc55c 4211
daea3e73
AK		 4212 /* guests cmpxchg8b have to be emulated atomically */
4213 if (bytes > 8 || (bytes & (bytes - 1)))
4214 goto emul_write;
10589a46 4215
daea3e73 4216 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4217
daea3e73
AK		 4218 if (gpa == UNMAPPED_GVA ||
4219 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4220 goto emul_write;
2bacc55c 4221
daea3e73
AK		 4222 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4223 goto emul_write;
72dc67a6 4224
daea3e73 4225 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 4226 if (is_error_page(page)) {
4227 kvm_release_page_clean(page);
4228 goto emul_write;
4229 }
72dc67a6 4230
daea3e73
AK		 4231 kaddr = kmap_atomic(page, KM_USER0);
4232 kaddr += offset_in_page(gpa);
4233 switch (bytes) {
4234 case 1:
4235 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4236 break;
4237 case 2:
4238 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4239 break;
4240 case 4:
4241 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4242 break;
4243 case 8:
4244 exchanged = CMPXCHG64(kaddr, old, new);
4245 break;
4246 default:
4247 BUG();
2bacc55c 4248 }
daea3e73
AK		 4249 kunmap_atomic(kaddr, KM_USER0);
4250 kvm_release_page_dirty(page);
4251
4252 if (!exchanged)
4253 return X86EMUL_CMPXCHG_FAILED;
4254
8f6abd06
GN		 4255 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
4256
4257 return X86EMUL_CONTINUE;
4a5f48f6 4258
3200f405 4259emul_write:
daea3e73 4260 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4261
0f65dd70 4262 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4263}
4264
cf8f70bf
GN		 4265static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4266{
4267 /* TODO: String I/O for in kernel device */
4268 int r;
4269
4270 if (vcpu->arch.pio.in)
4271 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4272 vcpu->arch.pio.size, pd);
4273 else
4274 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4275 vcpu->arch.pio.port, vcpu->arch.pio.size,
4276 pd);
4277 return r;
4278}
4279
4280
ca1d4a9e
AK		 4281static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4282 int size, unsigned short port, void *val,
4283 unsigned int count)
cf8f70bf 4284{
ca1d4a9e
AK		 4285 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4286
7972995b 4287 if (vcpu->arch.pio.count)
cf8f70bf
GN		 4288 goto data_avail;
4289
61cfab2e 4290 trace_kvm_pio(0, port, size, count);
cf8f70bf
GN		 4291
4292 vcpu->arch.pio.port = port;
4293 vcpu->arch.pio.in = 1;
7972995b 4294 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4295 vcpu->arch.pio.size = size;
4296
4297 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4298 data_avail:
4299 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4300 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4301 return 1;
4302 }
4303
4304 vcpu->run->exit_reason = KVM_EXIT_IO;
4305 vcpu->run->io.direction = KVM_EXIT_IO_IN;
4306 vcpu->run->io.size = size;
4307 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4308 vcpu->run->io.count = count;
4309 vcpu->run->io.port = port;
4310
4311 return 0;
4312}
4313
ca1d4a9e
AK		 4314static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4315 int size, unsigned short port,
4316 const void *val, unsigned int count)
cf8f70bf 4317{
ca1d4a9e
AK		 4318 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4319
61cfab2e 4320 trace_kvm_pio(1, port, size, count);
cf8f70bf
GN		 4321
4322 vcpu->arch.pio.port = port;
4323 vcpu->arch.pio.in = 0;
7972995b 4324 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4325 vcpu->arch.pio.size = size;
4326
4327 memcpy(vcpu->arch.pio_data, val, size * count);
4328
4329 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4330 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4331 return 1;
4332 }
4333
4334 vcpu->run->exit_reason = KVM_EXIT_IO;
4335 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
4336 vcpu->run->io.size = size;
4337 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4338 vcpu->run->io.count = count;
4339 vcpu->run->io.port = port;
4340
4341 return 0;
4342}
4343
bbd9b64e
CO		 4344static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4345{
4346 return kvm_x86_ops->get_segment_base(vcpu, seg);
4347}
4348
3cb16fe7 4349static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4350{
3cb16fe7 4351 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4352}
4353
f5f48ee1
SY		 4354int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4355{
4356 if (!need_emulate_wbinvd(vcpu))
4357 return X86EMUL_CONTINUE;
4358
4359 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4360 int cpu = get_cpu();
4361
4362 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4363 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4364 wbinvd_ipi, NULL, 1);
2eec7343 4365 put_cpu();
f5f48ee1 4366 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4367 } else
4368 wbinvd();
f5f48ee1
SY		 4369 return X86EMUL_CONTINUE;
4370}
4371EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4372
bcaf5cc5
AK		 4373static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4374{
4375 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4376}
4377
717746e3 4378int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4379{
717746e3 4380 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4381}
4382
717746e3 4383int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4384{
338dbc97 4385
717746e3 4386 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4387}
4388
52a46617 4389static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4390{
52a46617 4391 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4392}
4393
717746e3 4394static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4395{
717746e3 4396 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4397 unsigned long value;
4398
4399 switch (cr) {
4400 case 0:
4401 value = kvm_read_cr0(vcpu);
4402 break;
4403 case 2:
4404 value = vcpu->arch.cr2;
4405 break;
4406 case 3:
9f8fe504 4407 value = kvm_read_cr3(vcpu);
52a46617
GN		 4408 break;
4409 case 4:
4410 value = kvm_read_cr4(vcpu);
4411 break;
4412 case 8:
4413 value = kvm_get_cr8(vcpu);
4414 break;
4415 default:
4416 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4417 return 0;
4418 }
4419
4420 return value;
4421}
4422
717746e3 4423static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4424{
717746e3 4425 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4426 int res = 0;
4427
52a46617
GN		 4428 switch (cr) {
4429 case 0:
49a9b07e 4430 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4431 break;
4432 case 2:
4433 vcpu->arch.cr2 = val;
4434 break;
4435 case 3:
2390218b 4436 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4437 break;
4438 case 4:
a83b29c6 4439 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4440 break;
4441 case 8:
eea1cff9 4442 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4443 break;
4444 default:
4445 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4446 res = -1;
52a46617 4447 }
0f12244f
GN		 4448
4449 return res;
52a46617
GN		 4450}
4451
717746e3 4452static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4453{
717746e3 4454 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4455}
4456
4bff1e86 4457static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4458{
4bff1e86 4459 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4460}
4461
4bff1e86 4462static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4463{
4bff1e86 4464 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4465}
4466
1ac9d0cf
AK		 4467static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4468{
4469 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4470}
4471
4472static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4473{
4474 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4475}
4476
4bff1e86
AK		 4477static unsigned long emulator_get_cached_segment_base(
4478 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4479{
4bff1e86 4480 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4481}
4482
1aa36616
AK		 4483static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4484 struct desc_struct *desc, u32 *base3,
4485 int seg)
2dafc6c2
GN		 4486{
4487 struct kvm_segment var;
4488
4bff1e86 4489 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4490 *selector = var.selector;
2dafc6c2
GN		 4491
4492 if (var.unusable)
4493 return false;
4494
4495 if (var.g)
4496 var.limit >>= 12;
4497 set_desc_limit(desc, var.limit);
4498 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4499#ifdef CONFIG_X86_64
4500 if (base3)
4501 *base3 = var.base >> 32;
4502#endif
2dafc6c2
GN		 4503 desc->type = var.type;
4504 desc->s = var.s;
4505 desc->dpl = var.dpl;
4506 desc->p = var.present;
4507 desc->avl = var.avl;
4508 desc->l = var.l;
4509 desc->d = var.db;
4510 desc->g = var.g;
4511
4512 return true;
4513}
4514
1aa36616
AK		 4515static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4516 struct desc_struct *desc, u32 base3,
4517 int seg)
2dafc6c2 4518{
4bff1e86 4519 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4520 struct kvm_segment var;
4521
1aa36616 4522 var.selector = selector;
2dafc6c2 4523 var.base = get_desc_base(desc);
5601d05b
GN		 4524#ifdef CONFIG_X86_64
4525 var.base |= ((u64)base3) << 32;
4526#endif
2dafc6c2
GN		 4527 var.limit = get_desc_limit(desc);
4528 if (desc->g)
4529 var.limit = (var.limit << 12) | 0xfff;
4530 var.type = desc->type;
4531 var.present = desc->p;
4532 var.dpl = desc->dpl;
4533 var.db = desc->d;
4534 var.s = desc->s;
4535 var.l = desc->l;
4536 var.g = desc->g;
4537 var.avl = desc->avl;
4538 var.present = desc->p;
4539 var.unusable = !var.present;
4540 var.padding = 0;
4541
4542 kvm_set_segment(vcpu, &var, seg);
4543 return;
4544}
4545
717746e3
AK		 4546static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4547 u32 msr_index, u64 *pdata)
4548{
4549 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4550}
4551
4552static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4553 u32 msr_index, u64 data)
4554{
4555 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4556}
4557
6c3287f7
AK		 4558static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4559{
4560 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4561}
4562
5037f6f3
AK		 4563static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4564{
4565 preempt_disable();
5197b808 4566 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4567 /*
4568 * CR0.TS may reference the host fpu state, not the guest fpu state,
4569 * so it may be clear at this point.
4570 */
4571 clts();
4572}
4573
4574static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4575{
4576 preempt_enable();
4577}
4578
2953538e 4579static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4580 struct x86_instruction_info *info,
c4f035c6
AK		 4581 enum x86_intercept_stage stage)
4582{
2953538e 4583 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4584}
4585
14af3f3c 4586static struct x86_emulate_ops emulate_ops = {
1871c602 4587 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4588 .write_std = kvm_write_guest_virt_system,
1871c602 4589 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4590 .read_emulated = emulator_read_emulated,
4591 .write_emulated = emulator_write_emulated,
4592 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4593 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4594 .pio_in_emulated = emulator_pio_in_emulated,
4595 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4596 .get_segment = emulator_get_segment,
4597 .set_segment = emulator_set_segment,
5951c442 4598 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4599 .get_gdt = emulator_get_gdt,
160ce1f1 4600 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4601 .set_gdt = emulator_set_gdt,
4602 .set_idt = emulator_set_idt,
52a46617
GN		 4603 .get_cr = emulator_get_cr,
4604 .set_cr = emulator_set_cr,
9c537244 4605 .cpl = emulator_get_cpl,
35aa5375
GN		 4606 .get_dr = emulator_get_dr,
4607 .set_dr = emulator_set_dr,
717746e3
AK		 4608 .set_msr = emulator_set_msr,
4609 .get_msr = emulator_get_msr,
6c3287f7 4610 .halt = emulator_halt,
bcaf5cc5 4611 .wbinvd = emulator_wbinvd,
d6aa1000 4612 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4613 .get_fpu = emulator_get_fpu,
4614 .put_fpu = emulator_put_fpu,
c4f035c6 4615 .intercept = emulator_intercept,
bbd9b64e
CO		 4616};
4617
5fdbf976
MT		 4618static void cache_all_regs(struct kvm_vcpu *vcpu)
4619{
4620 kvm_register_read(vcpu, VCPU_REGS_RAX);
4621 kvm_register_read(vcpu, VCPU_REGS_RSP);
4622 kvm_register_read(vcpu, VCPU_REGS_RIP);
4623 vcpu->arch.regs_dirty = ~0;
4624}
4625
95cb2295
GN		 4626static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4627{
4628 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4629 /*
4630 * an sti; sti; sequence only disable interrupts for the first
4631 * instruction. So, if the last instruction, be it emulated or
4632 * not, left the system with the INT_STI flag enabled, it
4633 * means that the last instruction is an sti. We should not
4634 * leave the flag on in this case. The same goes for mov ss
4635 */
4636 if (!(int_shadow & mask))
4637 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4638}
4639
54b8486f
GN		 4640static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4641{
4642 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4643 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4644 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4645 else if (ctxt->exception.error_code_valid)
4646 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4647 ctxt->exception.error_code);
54b8486f 4648 else
da9cb575 4649 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4650}
4651
9dac77fa 4652static void init_decode_cache(struct x86_emulate_ctxt *ctxt,
b5c9ff73
TY		 4653 const unsigned long *regs)
4654{
9dac77fa
AK		 4655 memset(&ctxt->twobyte, 0,
4656 (void *)&ctxt->regs - (void *)&ctxt->twobyte);
4657 memcpy(ctxt->regs, regs, sizeof(ctxt->regs));
b5c9ff73 4658
9dac77fa
AK		 4659 ctxt->fetch.start = 0;
4660 ctxt->fetch.end = 0;
4661 ctxt->io_read.pos = 0;
4662 ctxt->io_read.end = 0;
4663 ctxt->mem_read.pos = 0;
4664 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4665}
4666
8ec4722d
MG		 4667static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4668{
adf52235 4669 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4670 int cs_db, cs_l;
4671
2aab2c5b
GN		 4672 /*
4673 * TODO: fix emulate.c to use guest_read/write_register
4674 * instead of direct ->regs accesses, can save hundred cycles
4675 * on Intel for instructions that don't read/change RSP, for
4676 * for example.
4677 */
8ec4722d
MG		 4678 cache_all_regs(vcpu);
4679
4680 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4681
adf52235
TY		 4682 ctxt->eflags = kvm_get_rflags(vcpu);
4683 ctxt->eip = kvm_rip_read(vcpu);
4684 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4685 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4686 cs_l ? X86EMUL_MODE_PROT64 :
4687 cs_db ? X86EMUL_MODE_PROT32 :
4688 X86EMUL_MODE_PROT16;
4689 ctxt->guest_mode = is_guest_mode(vcpu);
4690
9dac77fa 4691 init_decode_cache(ctxt, vcpu->arch.regs);
7ae441ea 4692 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4693}
4694
71f9833b 4695int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4696{
9d74191a 4697 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4698 int ret;
4699
4700 init_emulate_ctxt(vcpu);
4701
9dac77fa
AK		 4702 ctxt->op_bytes = 2;
4703 ctxt->ad_bytes = 2;
4704 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4705 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4706
4707 if (ret != X86EMUL_CONTINUE)
4708 return EMULATE_FAIL;
4709
9dac77fa
AK		 4710 ctxt->eip = ctxt->_eip;
4711 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 4712 kvm_rip_write(vcpu, ctxt->eip);
4713 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4714
4715 if (irq == NMI_VECTOR)
4716 vcpu->arch.nmi_pending = false;
4717 else
4718 vcpu->arch.interrupt.pending = false;
4719
4720 return EMULATE_DONE;
4721}
4722EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4723
6d77dbfc
GN		 4724static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4725{
fc3a9157
JR		 4726 int r = EMULATE_DONE;
4727
6d77dbfc
GN		 4728 ++vcpu->stat.insn_emulation_fail;
4729 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4730 if (!is_guest_mode(vcpu)) {
4731 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4732 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4733 vcpu->run->internal.ndata = 0;
4734 r = EMULATE_FAIL;
4735 }
6d77dbfc 4736 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4737
4738 return r;
6d77dbfc
GN		 4739}
4740
a6f177ef
GN		 4741static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4742{
4743 gpa_t gpa;
4744
68be0803
GN		 4745 if (tdp_enabled)
4746 return false;
4747
a6f177ef
GN		 4748 /*
4749 * if emulation was due to access to shadowed page table
4750 * and it failed try to unshadow page and re-entetr the
4751 * guest to let CPU execute the instruction.
4752 */
4753 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4754 return true;
4755
4756 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4757
4758 if (gpa == UNMAPPED_GVA)
4759 return true; /* let cpu generate fault */
4760
4761 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4762 return true;
4763
4764 return false;
4765}
4766
51d8b661
AP		 4767int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4768 unsigned long cr2,
dc25e89e
AP		 4769 int emulation_type,
4770 void *insn,
4771 int insn_len)
bbd9b64e 4772{
95cb2295 4773 int r;
9d74191a 4774 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 4775 bool writeback = true;
bbd9b64e 4776
26eef70c 4777 kvm_clear_exception_queue(vcpu);
8d7d8102 4778
571008da 4779 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4780 init_emulate_ctxt(vcpu);
9d74191a
TY		 4781 ctxt->interruptibility = 0;
4782 ctxt->have_exception = false;
4783 ctxt->perm_ok = false;
bbd9b64e 4784
9d74191a 4785 ctxt->only_vendor_specific_insn
4005996e
AK		 4786 = emulation_type & EMULTYPE_TRAP_UD;
4787
9d74191a 4788 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 4789
e46479f8 4790 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4791 ++vcpu->stat.insn_emulation;
bbd9b64e 4792 if (r) {
4005996e
AK		 4793 if (emulation_type & EMULTYPE_TRAP_UD)
4794 return EMULATE_FAIL;
a6f177ef 4795 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4796 return EMULATE_DONE;
6d77dbfc
GN		 4797 if (emulation_type & EMULTYPE_SKIP)
4798 return EMULATE_FAIL;
4799 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4800 }
4801 }
4802
ba8afb6b 4803 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 4804 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 4805 return EMULATE_DONE;
4806 }
4807
7ae441ea 4808 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4809 changes registers values during IO operation */
7ae441ea
GN		 4810 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4811 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
9dac77fa 4812 memcpy(ctxt->regs, vcpu->arch.regs, sizeof ctxt->regs);
7ae441ea 4813 }
4d2179e1 4814
5cd21917 4815restart:
9d74191a 4816 r = x86_emulate_insn(ctxt);
bbd9b64e 4817
775fde86
JR		 4818 if (r == EMULATION_INTERCEPTED)
4819 return EMULATE_DONE;
4820
d2ddd1c4 4821 if (r == EMULATION_FAILED) {
a6f177ef 4822 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4823 return EMULATE_DONE;
4824
6d77dbfc 4825 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4826 }
4827
9d74191a 4828 if (ctxt->have_exception) {
54b8486f 4829 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4830 r = EMULATE_DONE;
4831 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4832 if (!vcpu->arch.pio.in)
4833 vcpu->arch.pio.count = 0;
7ae441ea
GN		 4834 else
4835 writeback = false;
e85d28f8 4836 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4837 } else if (vcpu->mmio_needed) {
4838 if (!vcpu->mmio_is_write)
4839 writeback = false;
e85d28f8 4840 r = EMULATE_DO_MMIO;
7ae441ea 4841 } else if (r == EMULATION_RESTART)
5cd21917 4842 goto restart;
d2ddd1c4
GN		 4843 else
4844 r = EMULATE_DONE;
f850e2e6 4845
7ae441ea 4846 if (writeback) {
9d74191a
TY		 4847 toggle_interruptibility(vcpu, ctxt->interruptibility);
4848 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea 4849 kvm_make_request(KVM_REQ_EVENT, vcpu);
9dac77fa 4850 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea 4851 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 4852 kvm_rip_write(vcpu, ctxt->eip);
7ae441ea
GN		 4853 } else
4854 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4855
4856 return r;
de7d789a 4857}
51d8b661 4858EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4859
cf8f70bf 4860int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4861{
cf8f70bf 4862 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 4863 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4864 size, port, &val, 1);
cf8f70bf 4865 /* do not return to emulator after return from userspace */
7972995b 4866 vcpu->arch.pio.count = 0;
de7d789a
CO		 4867 return ret;
4868}
cf8f70bf 4869EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4870
8cfdc000
ZA		 4871static void tsc_bad(void *info)
4872{
0a3aee0d 4873 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4874}
4875
4876static void tsc_khz_changed(void *data)
c8076604 4877{
8cfdc000
ZA		 4878 struct cpufreq_freqs *freq = data;
4879 unsigned long khz = 0;
4880
4881 if (data)
4882 khz = freq->new;
4883 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4884 khz = cpufreq_quick_get(raw_smp_processor_id());
4885 if (!khz)
4886 khz = tsc_khz;
0a3aee0d 4887 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 4888}
4889
c8076604
GH		 4890static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4891 void *data)
4892{
4893 struct cpufreq_freqs *freq = data;
4894 struct kvm *kvm;
4895 struct kvm_vcpu *vcpu;
4896 int i, send_ipi = 0;
4897
8cfdc000
ZA		 4898 /*
4899 * We allow guests to temporarily run on slowing clocks,
4900 * provided we notify them after, or to run on accelerating
4901 * clocks, provided we notify them before. Thus time never
4902 * goes backwards.
4903 *
4904 * However, we have a problem. We can't atomically update
4905 * the frequency of a given CPU from this function; it is
4906 * merely a notifier, which can be called from any CPU.
4907 * Changing the TSC frequency at arbitrary points in time
4908 * requires a recomputation of local variables related to
4909 * the TSC for each VCPU. We must flag these local variables
4910 * to be updated and be sure the update takes place with the
4911 * new frequency before any guests proceed.
4912 *
4913 * Unfortunately, the combination of hotplug CPU and frequency
4914 * change creates an intractable locking scenario; the order
4915 * of when these callouts happen is undefined with respect to
4916 * CPU hotplug, and they can race with each other. As such,
4917 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4918 * undefined; you can actually have a CPU frequency change take
4919 * place in between the computation of X and the setting of the
4920 * variable. To protect against this problem, all updates of
4921 * the per_cpu tsc_khz variable are done in an interrupt
4922 * protected IPI, and all callers wishing to update the value
4923 * must wait for a synchronous IPI to complete (which is trivial
4924 * if the caller is on the CPU already). This establishes the
4925 * necessary total order on variable updates.
4926 *
4927 * Note that because a guest time update may take place
4928 * anytime after the setting of the VCPU's request bit, the
4929 * correct TSC value must be set before the request. However,
4930 * to ensure the update actually makes it to any guest which
4931 * starts running in hardware virtualization between the set
4932 * and the acquisition of the spinlock, we must also ping the
4933 * CPU after setting the request bit.
4934 *
4935 */
4936
c8076604
GH		 4937 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4938 return 0;
4939 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4940 return 0;
8cfdc000
ZA		 4941
4942 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 4943
e935b837 4944 raw_spin_lock(&kvm_lock);
c8076604 4945 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4946 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4947 if (vcpu->cpu != freq->cpu)
4948 continue;
c285545f 4949 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4950 if (vcpu->cpu != smp_processor_id())
8cfdc000 4951 send_ipi = 1;
c8076604
GH		 4952 }
4953 }
e935b837 4954 raw_spin_unlock(&kvm_lock);
c8076604
GH		 4955
4956 if (freq->old < freq->new && send_ipi) {
4957 /*
4958 * We upscale the frequency. Must make the guest
4959 * doesn't see old kvmclock values while running with
4960 * the new frequency, otherwise we risk the guest sees
4961 * time go backwards.
4962 *
4963 * In case we update the frequency for another cpu
4964 * (which might be in guest context) send an interrupt
4965 * to kick the cpu out of guest context. Next time
4966 * guest context is entered kvmclock will be updated,
4967 * so the guest will not see stale values.
4968 */
8cfdc000 4969 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4970 }
4971 return 0;
4972}
4973
4974static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4975 .notifier_call = kvmclock_cpufreq_notifier
4976};
4977
4978static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4979 unsigned long action, void *hcpu)
4980{
4981 unsigned int cpu = (unsigned long)hcpu;
4982
4983 switch (action) {
4984 case CPU_ONLINE:
4985 case CPU_DOWN_FAILED:
4986 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4987 break;
4988 case CPU_DOWN_PREPARE:
4989 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4990 break;
4991 }
4992 return NOTIFY_OK;
4993}
4994
4995static struct notifier_block kvmclock_cpu_notifier_block = {
4996 .notifier_call = kvmclock_cpu_notifier,
4997 .priority = -INT_MAX
c8076604
GH		 4998};
4999
b820cc0c
ZA		 5000static void kvm_timer_init(void)
5001{
5002 int cpu;
5003
c285545f 5004 max_tsc_khz = tsc_khz;
8cfdc000 5005 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 5006 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5007#ifdef CONFIG_CPU_FREQ
5008 struct cpufreq_policy policy;
5009 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5010 cpu = get_cpu();
5011 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5012 if (policy.cpuinfo.max_freq)
5013 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5014 put_cpu();
c285545f 5015#endif
b820cc0c
ZA		 5016 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5017 CPUFREQ_TRANSITION_NOTIFIER);
5018 }
c285545f 5019 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5020 for_each_online_cpu(cpu)
5021 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 5022}
5023
ff9d07a0
ZY		 5024static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5025
5026static int kvm_is_in_guest(void)
5027{
5028 return percpu_read(current_vcpu) != NULL;
5029}
5030
5031static int kvm_is_user_mode(void)
5032{
5033 int user_mode = 3;
dcf46b94 5034
ff9d07a0
ZY		 5035 if (percpu_read(current_vcpu))
5036 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 5037
ff9d07a0
ZY		 5038 return user_mode != 0;
5039}
5040
5041static unsigned long kvm_get_guest_ip(void)
5042{
5043 unsigned long ip = 0;
dcf46b94 5044
ff9d07a0
ZY		 5045 if (percpu_read(current_vcpu))
5046 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 5047
ff9d07a0
ZY		 5048 return ip;
5049}
5050
5051static struct perf_guest_info_callbacks kvm_guest_cbs = {
5052 .is_in_guest = kvm_is_in_guest,
5053 .is_user_mode = kvm_is_user_mode,
5054 .get_guest_ip = kvm_get_guest_ip,
5055};
5056
5057void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5058{
5059 percpu_write(current_vcpu, vcpu);
5060}
5061EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5062
5063void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5064{
5065 percpu_write(current_vcpu, NULL);
5066}
5067EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5068
ce88decf
XG		 5069static void kvm_set_mmio_spte_mask(void)
5070{
5071 u64 mask;
5072 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5073
5074 /*
5075 * Set the reserved bits and the present bit of an paging-structure
5076 * entry to generate page fault with PFER.RSV = 1.
5077 */
5078 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
5079 mask |= 1ull;
5080
5081#ifdef CONFIG_X86_64
5082 /*
5083 * If reserved bit is not supported, clear the present bit to disable
5084 * mmio page fault.
5085 */
5086 if (maxphyaddr == 52)
5087 mask &= ~1ull;
5088#endif
5089
5090 kvm_mmu_set_mmio_spte_mask(mask);
5091}
5092
f8c16bba 5093int kvm_arch_init(void *opaque)
043405e1 5094{
b820cc0c 5095 int r;
f8c16bba
ZX		 5096 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
5097
f8c16bba
ZX		 5098 if (kvm_x86_ops) {
5099 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5100 r = -EEXIST;
5101 goto out;
f8c16bba
ZX		 5102 }
5103
5104 if (!ops->cpu_has_kvm_support()) {
5105 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5106 r = -EOPNOTSUPP;
5107 goto out;
f8c16bba
ZX		 5108 }
5109 if (ops->disabled_by_bios()) {
5110 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5111 r = -EOPNOTSUPP;
5112 goto out;
f8c16bba
ZX		 5113 }
5114
97db56ce
AK		 5115 r = kvm_mmu_module_init();
5116 if (r)
5117 goto out;
5118
ce88decf 5119 kvm_set_mmio_spte_mask();
97db56ce
AK		 5120 kvm_init_msr_list();
5121
f8c16bba 5122 kvm_x86_ops = ops;
7b52345e 5123 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5124 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5125
b820cc0c 5126 kvm_timer_init();
c8076604 5127
ff9d07a0
ZY		 5128 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5129
2acf923e
DC		 5130 if (cpu_has_xsave)
5131 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5132
f8c16bba 5133 return 0;
56c6d28a
ZX		 5134
5135out:
56c6d28a 5136 return r;
043405e1 5137}
8776e519 5138
f8c16bba
ZX		 5139void kvm_arch_exit(void)
5140{
ff9d07a0
ZY		 5141 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5142
888d256e
JK		 5143 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5144 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5145 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5146 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 5147 kvm_x86_ops = NULL;
56c6d28a
ZX		 5148 kvm_mmu_module_exit();
5149}
f8c16bba 5150
8776e519
HB		 5151int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5152{
5153 ++vcpu->stat.halt_exits;
5154 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5155 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5156 return 1;
5157 } else {
5158 vcpu->run->exit_reason = KVM_EXIT_HLT;
5159 return 0;
5160 }
5161}
5162EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5163
2f333bcb
MT		 5164static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
5165 unsigned long a1)
5166{
5167 if (is_long_mode(vcpu))
5168 return a0;
5169 else
5170 return a0 | ((gpa_t)a1 << 32);
5171}
5172
55cd8e5a
GN		 5173int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5174{
5175 u64 param, ingpa, outgpa, ret;
5176 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5177 bool fast, longmode;
5178 int cs_db, cs_l;
5179
5180 /*
5181 * hypercall generates UD from non zero cpl and real mode
5182 * per HYPER-V spec
5183 */
3eeb3288 5184 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5185 kvm_queue_exception(vcpu, UD_VECTOR);
5186 return 0;
5187 }
5188
5189 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5190 longmode = is_long_mode(vcpu) && cs_l == 1;
5191
5192 if (!longmode) {
ccd46936
GN		 5193 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5194 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5195 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5196 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5197 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5198 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5199 }
5200#ifdef CONFIG_X86_64
5201 else {
5202 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5203 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5204 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5205 }
5206#endif
5207
5208 code = param & 0xffff;
5209 fast = (param >> 16) & 0x1;
5210 rep_cnt = (param >> 32) & 0xfff;
5211 rep_idx = (param >> 48) & 0xfff;
5212
5213 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5214
c25bc163
GN		 5215 switch (code) {
5216 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5217 kvm_vcpu_on_spin(vcpu);
5218 break;
5219 default:
5220 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5221 break;
5222 }
55cd8e5a
GN		 5223
5224 ret = res | (((u64)rep_done & 0xfff) << 32);
5225 if (longmode) {
5226 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5227 } else {
5228 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5229 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5230 }
5231
5232 return 1;
5233}
5234
8776e519
HB		 5235int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5236{
5237 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5238 int r = 1;
8776e519 5239
55cd8e5a
GN		 5240 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5241 return kvm_hv_hypercall(vcpu);
5242
5fdbf976
MT		 5243 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5244 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5245 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5246 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5247 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5248
229456fc 5249 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5250
8776e519
HB		 5251 if (!is_long_mode(vcpu)) {
5252 nr &= 0xFFFFFFFF;
5253 a0 &= 0xFFFFFFFF;
5254 a1 &= 0xFFFFFFFF;
5255 a2 &= 0xFFFFFFFF;
5256 a3 &= 0xFFFFFFFF;
5257 }
5258
07708c4a
JK		 5259 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5260 ret = -KVM_EPERM;
5261 goto out;
5262 }
5263
8776e519 5264 switch (nr) {
b93463aa
AK		 5265 case KVM_HC_VAPIC_POLL_IRQ:
5266 ret = 0;
5267 break;
2f333bcb
MT		 5268 case KVM_HC_MMU_OP:
5269 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
5270 break;
8776e519
HB		 5271 default:
5272 ret = -KVM_ENOSYS;
5273 break;
5274 }
07708c4a 5275out:
5fdbf976 5276 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5277 ++vcpu->stat.hypercalls;
2f333bcb 5278 return r;
8776e519
HB		 5279}
5280EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5281
d6aa1000 5282int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5283{
d6aa1000 5284 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5285 char instruction[3];
5fdbf976 5286 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5287
8776e519
HB		 5288 /*
5289 * Blow out the MMU to ensure that no other VCPU has an active mapping
5290 * to ensure that the updated hypercall appears atomically across all
5291 * VCPUs.
5292 */
5293 kvm_mmu_zap_all(vcpu->kvm);
5294
8776e519 5295 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5296
9d74191a 5297 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5298}
5299
07716717
DK		 5300static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
5301{
ad312c7c
ZX		 5302 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
5303 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 5304
5305 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
5306 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 5307 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 5308 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 5309 if (ej->function == e->function) {
5310 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
5311 return j;
5312 }
5313 }
5314 return 0; /* silence gcc, even though control never reaches here */
5315}
5316
5317/* find an entry with matching function, matching index (if needed), and that
5318 * should be read next (if it's stateful) */
5319static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
5320 u32 function, u32 index)
5321{
5322 if (e->function != function)
5323 return 0;
5324 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
5325 return 0;
5326 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 5327 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 5328 return 0;
5329 return 1;
5330}
5331
d8017474
AG		 5332struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
5333 u32 function, u32 index)
8776e519
HB		 5334{
5335 int i;
d8017474 5336 struct kvm_cpuid_entry2 *best = NULL;
8776e519 5337
ad312c7c 5338 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 5339 struct kvm_cpuid_entry2 *e;
5340
ad312c7c 5341 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 5342 if (is_matching_cpuid_entry(e, function, index)) {
5343 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
5344 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 5345 best = e;
5346 break;
5347 }
8776e519 5348 }
d8017474
AG		 5349 return best;
5350}
0e851880 5351EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 5352
82725b20
DE		 5353int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
5354{
5355 struct kvm_cpuid_entry2 *best;
5356
f7a71197
AK		 5357 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
5358 if (!best || best->eax < 0x80000008)
5359 goto not_found;
82725b20
DE		 5360 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
5361 if (best)
5362 return best->eax & 0xff;
f7a71197 5363not_found:
82725b20
DE		 5364 return 36;
5365}
5366
bd22f5cf
AP		 5367/*
5368 * If no match is found, check whether we exceed the vCPU's limit
5369 * and return the content of the highest valid _standard_ leaf instead.
5370 * This is to satisfy the CPUID specification.
5371 */
5372static struct kvm_cpuid_entry2* check_cpuid_limit(struct kvm_vcpu *vcpu,
5373 u32 function, u32 index)
5374{
5375 struct kvm_cpuid_entry2 *maxlevel;
5376
5377 maxlevel = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0);
5378 if (!maxlevel || maxlevel->eax >= function)
5379 return NULL;
5380 if (function & 0x80000000) {
5381 maxlevel = kvm_find_cpuid_entry(vcpu, 0, 0);
5382 if (!maxlevel)
5383 return NULL;
5384 }
5385 return kvm_find_cpuid_entry(vcpu, maxlevel->eax, index);
5386}
5387
d8017474
AG		 5388void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
5389{
5390 u32 function, index;
5391 struct kvm_cpuid_entry2 *best;
5392
5393 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
5394 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5395 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
5396 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
5397 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
5398 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
5399 best = kvm_find_cpuid_entry(vcpu, function, index);
bd22f5cf
AP		 5400
5401 if (!best)
5402 best = check_cpuid_limit(vcpu, function, index);
5403
8776e519 5404 if (best) {
5fdbf976
MT		 5405 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
5406 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
5407 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
5408 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 5409 }
8776e519 5410 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 5411 trace_kvm_cpuid(function,
5412 kvm_register_read(vcpu, VCPU_REGS_RAX),
5413 kvm_register_read(vcpu, VCPU_REGS_RBX),
5414 kvm_register_read(vcpu, VCPU_REGS_RCX),
5415 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 5416}
5417EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 5418
b6c7a5dc
HB		 5419/*
5420 * Check if userspace requested an interrupt window, and that the
5421 * interrupt window is open.
5422 *
5423 * No need to exit to userspace if we already have an interrupt queued.
5424 */
851ba692 5425static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5426{
8061823a 5427 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5428 vcpu->run->request_interrupt_window &&
5df56646 5429 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5430}
5431
851ba692 5432static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5433{
851ba692
AK		 5434 struct kvm_run *kvm_run = vcpu->run;
5435
91586a3b 5436 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5437 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5438 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5439 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5440 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5441 else
b6c7a5dc 5442 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5443 kvm_arch_interrupt_allowed(vcpu) &&
5444 !kvm_cpu_has_interrupt(vcpu) &&
5445 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5446}
5447
b93463aa
AK		 5448static void vapic_enter(struct kvm_vcpu *vcpu)
5449{
5450 struct kvm_lapic *apic = vcpu->arch.apic;
5451 struct page *page;
5452
5453 if (!apic || !apic->vapic_addr)
5454 return;
5455
5456 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 5457
5458 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 5459}
5460
5461static void vapic_exit(struct kvm_vcpu *vcpu)
5462{
5463 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5464 int idx;
b93463aa
AK		 5465
5466 if (!apic || !apic->vapic_addr)
5467 return;
5468
f656ce01 5469 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5470 kvm_release_page_dirty(apic->vapic_page);
5471 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5472 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5473}
5474
95ba8273
GN		 5475static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5476{
5477 int max_irr, tpr;
5478
5479 if (!kvm_x86_ops->update_cr8_intercept)
5480 return;
5481
88c808fd
AK		 5482 if (!vcpu->arch.apic)
5483 return;
5484
8db3baa2
GN		 5485 if (!vcpu->arch.apic->vapic_addr)
5486 max_irr = kvm_lapic_find_highest_irr(vcpu);
5487 else
5488 max_irr = -1;
95ba8273
GN		 5489
5490 if (max_irr != -1)
5491 max_irr >>= 4;
5492
5493 tpr = kvm_lapic_get_cr8(vcpu);
5494
5495 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5496}
5497
851ba692 5498static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5499{
5500 /* try to reinject previous events if any */
b59bb7bd 5501 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5502 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5503 vcpu->arch.exception.has_error_code,
5504 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5505 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5506 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5507 vcpu->arch.exception.error_code,
5508 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5509 return;
5510 }
5511
95ba8273
GN		 5512 if (vcpu->arch.nmi_injected) {
5513 kvm_x86_ops->set_nmi(vcpu);
5514 return;
5515 }
5516
5517 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5518 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5519 return;
5520 }
5521
5522 /* try to inject new event if pending */
5523 if (vcpu->arch.nmi_pending) {
5524 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5525 vcpu->arch.nmi_pending = false;
5526 vcpu->arch.nmi_injected = true;
5527 kvm_x86_ops->set_nmi(vcpu);
5528 }
5529 } else if (kvm_cpu_has_interrupt(vcpu)) {
5530 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5531 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5532 false);
5533 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5534 }
5535 }
5536}
5537
2acf923e
DC		 5538static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5539{
5540 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5541 !vcpu->guest_xcr0_loaded) {
5542 /* kvm_set_xcr() also depends on this */
5543 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5544 vcpu->guest_xcr0_loaded = 1;
5545 }
5546}
5547
5548static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5549{
5550 if (vcpu->guest_xcr0_loaded) {
5551 if (vcpu->arch.xcr0 != host_xcr0)
5552 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5553 vcpu->guest_xcr0_loaded = 0;
5554 }
5555}
5556
851ba692 5557static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5558{
5559 int r;
1499e54a 5560 bool nmi_pending;
6a8b1d13 5561 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5562 vcpu->run->request_interrupt_window;
b6c7a5dc 5563
3e007509 5564 if (vcpu->requests) {
a8eeb04a 5565 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5566 kvm_mmu_unload(vcpu);
a8eeb04a 5567 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5568 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5569 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5570 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5571 if (unlikely(r))
5572 goto out;
5573 }
a8eeb04a 5574 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5575 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5576 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5577 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5578 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5579 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5580 r = 0;
5581 goto out;
5582 }
a8eeb04a 5583 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5584 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5585 r = 0;
5586 goto out;
5587 }
a8eeb04a 5588 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5589 vcpu->fpu_active = 0;
5590 kvm_x86_ops->fpu_deactivate(vcpu);
5591 }
af585b92
GN		 5592 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5593 /* Page is swapped out. Do synthetic halt */
5594 vcpu->arch.apf.halted = true;
5595 r = 1;
5596 goto out;
5597 }
c9aaa895
GC		 5598 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5599 record_steal_time(vcpu);
5600
2f52d58c 5601 }
b93463aa 5602
3e007509
AK		 5603 r = kvm_mmu_reload(vcpu);
5604 if (unlikely(r))
5605 goto out;
5606
1499e54a
GN		 5607 /*
5608 * An NMI can be injected between local nmi_pending read and
5609 * vcpu->arch.nmi_pending read inside inject_pending_event().
5610 * But in that case, KVM_REQ_EVENT will be set, which makes
5611 * the race described above benign.
5612 */
5613 nmi_pending = ACCESS_ONCE(vcpu->arch.nmi_pending);
5614
b463a6f7
AK		 5615 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5616 inject_pending_event(vcpu);
5617
5618 /* enable NMI/IRQ window open exits if needed */
1499e54a 5619 if (nmi_pending)
b463a6f7
AK		 5620 kvm_x86_ops->enable_nmi_window(vcpu);
5621 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5622 kvm_x86_ops->enable_irq_window(vcpu);
5623
5624 if (kvm_lapic_enabled(vcpu)) {
5625 update_cr8_intercept(vcpu);
5626 kvm_lapic_sync_to_vapic(vcpu);
5627 }
5628 }
5629
b6c7a5dc
HB		 5630 preempt_disable();
5631
5632 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5633 if (vcpu->fpu_active)
5634 kvm_load_guest_fpu(vcpu);
2acf923e 5635 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5636
6b7e2d09
XG		 5637 vcpu->mode = IN_GUEST_MODE;
5638
5639 /* We should set ->mode before check ->requests,
5640 * see the comment in make_all_cpus_request.
5641 */
5642 smp_mb();
b6c7a5dc 5643
d94e1dc9 5644 local_irq_disable();
32f88400 5645
6b7e2d09 5646 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5647 || need_resched() || signal_pending(current)) {
6b7e2d09 5648 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5649 smp_wmb();
6c142801
AK		 5650 local_irq_enable();
5651 preempt_enable();
b463a6f7 5652 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5653 r = 1;
5654 goto out;
5655 }
5656
f656ce01 5657 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5658
b6c7a5dc
HB		 5659 kvm_guest_enter();
5660
42dbaa5a 5661 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5662 set_debugreg(0, 7);
5663 set_debugreg(vcpu->arch.eff_db[0], 0);
5664 set_debugreg(vcpu->arch.eff_db[1], 1);
5665 set_debugreg(vcpu->arch.eff_db[2], 2);
5666 set_debugreg(vcpu->arch.eff_db[3], 3);
5667 }
b6c7a5dc 5668
229456fc 5669 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5670 kvm_x86_ops->run(vcpu);
b6c7a5dc 5671
24f1e32c
FW		 5672 /*
5673 * If the guest has used debug registers, at least dr7
5674 * will be disabled while returning to the host.
5675 * If we don't have active breakpoints in the host, we don't
5676 * care about the messed up debug address registers. But if
5677 * we have some of them active, restore the old state.
5678 */
59d8eb53 5679 if (hw_breakpoint_active())
24f1e32c 5680 hw_breakpoint_restore();
42dbaa5a 5681
1d5f066e
ZA		 5682 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5683
6b7e2d09 5684 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5685 smp_wmb();
b6c7a5dc
HB		 5686 local_irq_enable();
5687
5688 ++vcpu->stat.exits;
5689
5690 /*
5691 * We must have an instruction between local_irq_enable() and
5692 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5693 * the interrupt shadow. The stat.exits increment will do nicely.
5694 * But we need to prevent reordering, hence this barrier():
5695 */
5696 barrier();
5697
5698 kvm_guest_exit();
5699
5700 preempt_enable();
5701
f656ce01 5702 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5703
b6c7a5dc
HB		 5704 /*
5705 * Profile KVM exit RIPs:
5706 */
5707 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5708 unsigned long rip = kvm_rip_read(vcpu);
5709 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5710 }
5711
298101da 5712
b93463aa
AK		 5713 kvm_lapic_sync_from_vapic(vcpu);
5714
851ba692 5715 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5716out:
5717 return r;
5718}
b6c7a5dc 5719
09cec754 5720
851ba692 5721static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5722{
5723 int r;
f656ce01 5724 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5725
5726 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5727 pr_debug("vcpu %d received sipi with vector # %x\n",
5728 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5729 kvm_lapic_reset(vcpu);
5f179287 5730 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5731 if (r)
5732 return r;
5733 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5734 }
5735
f656ce01 5736 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5737 vapic_enter(vcpu);
5738
5739 r = 1;
5740 while (r > 0) {
af585b92
GN		 5741 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5742 !vcpu->arch.apf.halted)
851ba692 5743 r = vcpu_enter_guest(vcpu);
d7690175 5744 else {
f656ce01 5745 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5746 kvm_vcpu_block(vcpu);
f656ce01 5747 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5748 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5749 {
5750 switch(vcpu->arch.mp_state) {
5751 case KVM_MP_STATE_HALTED:
d7690175 5752 vcpu->arch.mp_state =
09cec754
GN		 5753 KVM_MP_STATE_RUNNABLE;
5754 case KVM_MP_STATE_RUNNABLE:
af585b92 5755 vcpu->arch.apf.halted = false;
09cec754
GN		 5756 break;
5757 case KVM_MP_STATE_SIPI_RECEIVED:
5758 default:
5759 r = -EINTR;
5760 break;
5761 }
5762 }
d7690175
MT		 5763 }
5764
09cec754
GN		 5765 if (r <= 0)
5766 break;
5767
5768 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5769 if (kvm_cpu_has_pending_timer(vcpu))
5770 kvm_inject_pending_timer_irqs(vcpu);
5771
851ba692 5772 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5773 r = -EINTR;
851ba692 5774 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5775 ++vcpu->stat.request_irq_exits;
5776 }
af585b92
GN		 5777
5778 kvm_check_async_pf_completion(vcpu);
5779
09cec754
GN		 5780 if (signal_pending(current)) {
5781 r = -EINTR;
851ba692 5782 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5783 ++vcpu->stat.signal_exits;
5784 }
5785 if (need_resched()) {
f656ce01 5786 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5787 kvm_resched(vcpu);
f656ce01 5788 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5789 }
b6c7a5dc
HB		 5790 }
5791
f656ce01 5792 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5793
b93463aa
AK		 5794 vapic_exit(vcpu);
5795
b6c7a5dc
HB		 5796 return r;
5797}
5798
5287f194
AK		 5799static int complete_mmio(struct kvm_vcpu *vcpu)
5800{
5801 struct kvm_run *run = vcpu->run;
5802 int r;
5803
5804 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5805 return 1;
5806
5807 if (vcpu->mmio_needed) {
5287f194 5808 vcpu->mmio_needed = 0;
cef4dea0 5809 if (!vcpu->mmio_is_write)
0004c7c2
GN		 5810 memcpy(vcpu->mmio_data + vcpu->mmio_index,
5811 run->mmio.data, 8);
cef4dea0
AK		 5812 vcpu->mmio_index += 8;
5813 if (vcpu->mmio_index < vcpu->mmio_size) {
5814 run->exit_reason = KVM_EXIT_MMIO;
5815 run->mmio.phys_addr = vcpu->mmio_phys_addr + vcpu->mmio_index;
5816 memcpy(run->mmio.data, vcpu->mmio_data + vcpu->mmio_index, 8);
5817 run->mmio.len = min(vcpu->mmio_size - vcpu->mmio_index, 8);
5818 run->mmio.is_write = vcpu->mmio_is_write;
5819 vcpu->mmio_needed = 1;
5820 return 0;
5821 }
5822 if (vcpu->mmio_is_write)
5823 return 1;
5824 vcpu->mmio_read_completed = 1;
5287f194
AK		 5825 }
5826 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5827 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5828 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5829 if (r != EMULATE_DONE)
5830 return 0;
5831 return 1;
5832}
5833
b6c7a5dc
HB		 5834int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5835{
5836 int r;
5837 sigset_t sigsaved;
5838
e5c30142
AK		 5839 if (!tsk_used_math(current) && init_fpu(current))
5840 return -ENOMEM;
5841
ac9f6dc0
AK		 5842 if (vcpu->sigset_active)
5843 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5844
a4535290 5845 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5846 kvm_vcpu_block(vcpu);
d7690175 5847 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5848 r = -EAGAIN;
5849 goto out;
b6c7a5dc
HB		 5850 }
5851
b6c7a5dc 5852 /* re-sync apic's tpr */
eea1cff9
AP		 5853 if (!irqchip_in_kernel(vcpu->kvm)) {
5854 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5855 r = -EINVAL;
5856 goto out;
5857 }
5858 }
b6c7a5dc 5859
5287f194
AK		 5860 r = complete_mmio(vcpu);
5861 if (r <= 0)
5862 goto out;
5863
5fdbf976
MT		 5864 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5865 kvm_register_write(vcpu, VCPU_REGS_RAX,
5866 kvm_run->hypercall.ret);
b6c7a5dc 5867
851ba692 5868 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5869
5870out:
f1d86e46 5871 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5872 if (vcpu->sigset_active)
5873 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5874
b6c7a5dc
HB		 5875 return r;
5876}
5877
5878int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5879{
7ae441ea
GN		 5880 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5881 /*
5882 * We are here if userspace calls get_regs() in the middle of
5883 * instruction emulation. Registers state needs to be copied
5884 * back from emulation context to vcpu. Usrapace shouldn't do
5885 * that usually, but some bad designed PV devices (vmware
5886 * backdoor interface) need this to work
5887 */
9dac77fa
AK		 5888 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5889 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea
GN		 5890 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5891 }
5fdbf976
MT		 5892 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5893 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5894 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5895 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5896 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5897 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5898 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5899 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5900#ifdef CONFIG_X86_64
5fdbf976
MT		 5901 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5902 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5903 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5904 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5905 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5906 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5907 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5908 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5909#endif
5910
5fdbf976 5911 regs->rip = kvm_rip_read(vcpu);
91586a3b 5912 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5913
b6c7a5dc
HB		 5914 return 0;
5915}
5916
5917int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5918{
7ae441ea
GN		 5919 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5920 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5921
5fdbf976
MT		 5922 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5923 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5924 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5925 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5926 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5927 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5928 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5929 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5930#ifdef CONFIG_X86_64
5fdbf976
MT		 5931 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5932 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5933 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5934 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5935 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5936 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5937 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5938 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5939#endif
5940
5fdbf976 5941 kvm_rip_write(vcpu, regs->rip);
91586a3b 5942 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5943
b4f14abd
JK		 5944 vcpu->arch.exception.pending = false;
5945
3842d135
AK		 5946 kvm_make_request(KVM_REQ_EVENT, vcpu);
5947
b6c7a5dc
HB		 5948 return 0;
5949}
5950
b6c7a5dc
HB		 5951void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5952{
5953 struct kvm_segment cs;
5954
3e6e0aab 5955 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5956 *db = cs.db;
5957 *l = cs.l;
5958}
5959EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5960
5961int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5962 struct kvm_sregs *sregs)
5963{
89a27f4d 5964 struct desc_ptr dt;
b6c7a5dc 5965
3e6e0aab
GT		 5966 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5967 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5968 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5969 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5970 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5971 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5972
3e6e0aab
GT		 5973 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5974 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5975
5976 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5977 sregs->idt.limit = dt.size;
5978 sregs->idt.base = dt.address;
b6c7a5dc 5979 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5980 sregs->gdt.limit = dt.size;
5981 sregs->gdt.base = dt.address;
b6c7a5dc 5982
4d4ec087 5983 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 5984 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 5985 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 5986 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5987 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5988 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5989 sregs->apic_base = kvm_get_apic_base(vcpu);
5990
923c61bb 5991 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5992
36752c9b 5993 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5994 set_bit(vcpu->arch.interrupt.nr,
5995 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5996
b6c7a5dc
HB		 5997 return 0;
5998}
5999
62d9f0db
MT		 6000int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6001 struct kvm_mp_state *mp_state)
6002{
62d9f0db 6003 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 6004 return 0;
6005}
6006
6007int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6008 struct kvm_mp_state *mp_state)
6009{
62d9f0db 6010 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6011 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6012 return 0;
6013}
6014
e269fb21
JK		 6015int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
6016 bool has_error_code, u32 error_code)
b6c7a5dc 6017{
9d74191a 6018 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6019 int ret;
e01c2426 6020
8ec4722d 6021 init_emulate_ctxt(vcpu);
c697518a 6022
9d74191a
TY		 6023 ret = emulator_task_switch(ctxt, tss_selector, reason,
6024 has_error_code, error_code);
c697518a 6025
c697518a 6026 if (ret)
19d04437 6027 return EMULATE_FAIL;
37817f29 6028
9dac77fa 6029 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 6030 kvm_rip_write(vcpu, ctxt->eip);
6031 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6032 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6033 return EMULATE_DONE;
37817f29
IE		 6034}
6035EXPORT_SYMBOL_GPL(kvm_task_switch);
6036
b6c7a5dc
HB		 6037int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6038 struct kvm_sregs *sregs)
6039{
6040 int mmu_reset_needed = 0;
63f42e02 6041 int pending_vec, max_bits, idx;
89a27f4d 6042 struct desc_ptr dt;
b6c7a5dc 6043
89a27f4d
GN		 6044 dt.size = sregs->idt.limit;
6045 dt.address = sregs->idt.base;
b6c7a5dc 6046 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6047 dt.size = sregs->gdt.limit;
6048 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6049 kvm_x86_ops->set_gdt(vcpu, &dt);
6050
ad312c7c 6051 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6052 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6053 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6054 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6055
2d3ad1f4 6056 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6057
f6801dff 6058 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6059 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 6060 kvm_set_apic_base(vcpu, sregs->apic_base);
6061
4d4ec087 6062 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6063 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6064 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6065
fc78f519 6066 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6067 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c
SY		 6068 if (sregs->cr4 & X86_CR4_OSXSAVE)
6069 update_cpuid(vcpu);
63f42e02
XG		 6070
6071 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6072 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6073 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6074 mmu_reset_needed = 1;
6075 }
63f42e02 6076 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6077
6078 if (mmu_reset_needed)
6079 kvm_mmu_reset_context(vcpu);
6080
923c61bb
GN		 6081 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
6082 pending_vec = find_first_bit(
6083 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6084 if (pending_vec < max_bits) {
66fd3f7f 6085 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6086 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6087 }
6088
3e6e0aab
GT		 6089 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6090 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6091 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6092 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6093 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6094 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6095
3e6e0aab
GT		 6096 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6097 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6098
5f0269f5
ME		 6099 update_cr8_intercept(vcpu);
6100
9c3e4aab 6101 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6102 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6103 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6104 !is_protmode(vcpu))
9c3e4aab
MT		 6105 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6106
3842d135
AK		 6107 kvm_make_request(KVM_REQ_EVENT, vcpu);
6108
b6c7a5dc
HB		 6109 return 0;
6110}
6111
d0bfb940
JK		 6112int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6113 struct kvm_guest_debug *dbg)
b6c7a5dc 6114{
355be0b9 6115 unsigned long rflags;
ae675ef0 6116 int i, r;
b6c7a5dc 6117
4f926bf2
JK		 6118 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6119 r = -EBUSY;
6120 if (vcpu->arch.exception.pending)
2122ff5e 6121 goto out;
4f926bf2
JK		 6122 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6123 kvm_queue_exception(vcpu, DB_VECTOR);
6124 else
6125 kvm_queue_exception(vcpu, BP_VECTOR);
6126 }
6127
91586a3b
JK		 6128 /*
6129 * Read rflags as long as potentially injected trace flags are still
6130 * filtered out.
6131 */
6132 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6133
6134 vcpu->guest_debug = dbg->control;
6135 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6136 vcpu->guest_debug = 0;
6137
6138 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6139 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6140 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6141 vcpu->arch.switch_db_regs =
6142 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
6143 } else {
6144 for (i = 0; i < KVM_NR_DB_REGS; i++)
6145 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6146 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
6147 }
6148
f92653ee
JK		 6149 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6150 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6151 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6152
91586a3b
JK		 6153 /*
6154 * Trigger an rflags update that will inject or remove the trace
6155 * flags.
6156 */
6157 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6158
355be0b9 6159 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 6160
4f926bf2 6161 r = 0;
d0bfb940 6162
2122ff5e 6163out:
b6c7a5dc
HB		 6164
6165 return r;
6166}
6167
8b006791
ZX		 6168/*
6169 * Translate a guest virtual address to a guest physical address.
6170 */
6171int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6172 struct kvm_translation *tr)
6173{
6174 unsigned long vaddr = tr->linear_address;
6175 gpa_t gpa;
f656ce01 6176 int idx;
8b006791 6177
f656ce01 6178 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6179 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6180 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6181 tr->physical_address = gpa;
6182 tr->valid = gpa != UNMAPPED_GVA;
6183 tr->writeable = 1;
6184 tr->usermode = 0;
8b006791
ZX		 6185
6186 return 0;
6187}
6188
d0752060
HB		 6189int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6190{
98918833
SY		 6191 struct i387_fxsave_struct *fxsave =
6192 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6193
d0752060
HB		 6194 memcpy(fpu->fpr, fxsave->st_space, 128);
6195 fpu->fcw = fxsave->cwd;
6196 fpu->fsw = fxsave->swd;
6197 fpu->ftwx = fxsave->twd;
6198 fpu->last_opcode = fxsave->fop;
6199 fpu->last_ip = fxsave->rip;
6200 fpu->last_dp = fxsave->rdp;
6201 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6202
d0752060
HB		 6203 return 0;
6204}
6205
6206int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6207{
98918833
SY		 6208 struct i387_fxsave_struct *fxsave =
6209 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6210
d0752060
HB		 6211 memcpy(fxsave->st_space, fpu->fpr, 128);
6212 fxsave->cwd = fpu->fcw;
6213 fxsave->swd = fpu->fsw;
6214 fxsave->twd = fpu->ftwx;
6215 fxsave->fop = fpu->last_opcode;
6216 fxsave->rip = fpu->last_ip;
6217 fxsave->rdp = fpu->last_dp;
6218 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6219
d0752060
HB		 6220 return 0;
6221}
6222
10ab25cd 6223int fx_init(struct kvm_vcpu *vcpu)
d0752060 6224{
10ab25cd
JK		 6225 int err;
6226
6227 err = fpu_alloc(&vcpu->arch.guest_fpu);
6228 if (err)
6229 return err;
6230
98918833 6231 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6232
2acf923e
DC		 6233 /*
6234 * Ensure guest xcr0 is valid for loading
6235 */
6236 vcpu->arch.xcr0 = XSTATE_FP;
6237
ad312c7c 6238 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6239
6240 return 0;
d0752060
HB		 6241}
6242EXPORT_SYMBOL_GPL(fx_init);
6243
98918833
SY		 6244static void fx_free(struct kvm_vcpu *vcpu)
6245{
6246 fpu_free(&vcpu->arch.guest_fpu);
6247}
6248
d0752060
HB		 6249void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6250{
2608d7a1 6251 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6252 return;
6253
2acf923e
DC		 6254 /*
6255 * Restore all possible states in the guest,
6256 * and assume host would use all available bits.
6257 * Guest xcr0 would be loaded later.
6258 */
6259 kvm_put_guest_xcr0(vcpu);
d0752060 6260 vcpu->guest_fpu_loaded = 1;
7cf30855 6261 unlazy_fpu(current);
98918833 6262 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6263 trace_kvm_fpu(1);
d0752060 6264}
d0752060
HB		 6265
6266void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6267{
2acf923e
DC		 6268 kvm_put_guest_xcr0(vcpu);
6269
d0752060
HB		 6270 if (!vcpu->guest_fpu_loaded)
6271 return;
6272
6273 vcpu->guest_fpu_loaded = 0;
98918833 6274 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 6275 ++vcpu->stat.fpu_reload;
a8eeb04a 6276 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6277 trace_kvm_fpu(0);
d0752060 6278}
e9b11c17
ZX		 6279
6280void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6281{
12f9a48f 6282 kvmclock_reset(vcpu);
7f1ea208 6283
f5f48ee1 6284 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6285 fx_free(vcpu);
e9b11c17
ZX		 6286 kvm_x86_ops->vcpu_free(vcpu);
6287}
6288
6289struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6290 unsigned int id)
6291{
6755bae8
ZA		 6292 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6293 printk_once(KERN_WARNING
6294 "kvm: SMP vm created on host with unstable TSC; "
6295 "guest TSC will not be reliable\n");
26e5215f
AK		 6296 return kvm_x86_ops->vcpu_create(kvm, id);
6297}
e9b11c17 6298
26e5215f
AK		 6299int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6300{
6301 int r;
e9b11c17 6302
0bed3b56 6303 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 6304 vcpu_load(vcpu);
6305 r = kvm_arch_vcpu_reset(vcpu);
6306 if (r == 0)
6307 r = kvm_mmu_setup(vcpu);
6308 vcpu_put(vcpu);
e9b11c17 6309
26e5215f 6310 return r;
e9b11c17
ZX		 6311}
6312
d40ccc62 6313void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6314{
344d9588
GN		 6315 vcpu->arch.apf.msr_val = 0;
6316
e9b11c17
ZX		 6317 vcpu_load(vcpu);
6318 kvm_mmu_unload(vcpu);
6319 vcpu_put(vcpu);
6320
98918833 6321 fx_free(vcpu);
e9b11c17
ZX		 6322 kvm_x86_ops->vcpu_free(vcpu);
6323}
6324
6325int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
6326{
448fa4a9
JK		 6327 vcpu->arch.nmi_pending = false;
6328 vcpu->arch.nmi_injected = false;
6329
42dbaa5a
JK		 6330 vcpu->arch.switch_db_regs = 0;
6331 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6332 vcpu->arch.dr6 = DR6_FIXED_1;
6333 vcpu->arch.dr7 = DR7_FIXED_1;
6334
3842d135 6335 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6336 vcpu->arch.apf.msr_val = 0;
c9aaa895 6337 vcpu->arch.st.msr_val = 0;
3842d135 6338
12f9a48f
GC		 6339 kvmclock_reset(vcpu);
6340
af585b92
GN		 6341 kvm_clear_async_pf_completion_queue(vcpu);
6342 kvm_async_pf_hash_reset(vcpu);
6343 vcpu->arch.apf.halted = false;
3842d135 6344
e9b11c17
ZX		 6345 return kvm_x86_ops->vcpu_reset(vcpu);
6346}
6347
10474ae8 6348int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6349{
ca84d1a2
ZA		 6350 struct kvm *kvm;
6351 struct kvm_vcpu *vcpu;
6352 int i;
18863bdd
AK		 6353
6354 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 6355 list_for_each_entry(kvm, &vm_list, vm_list)
6356 kvm_for_each_vcpu(i, vcpu, kvm)
6357 if (vcpu->cpu == smp_processor_id())
c285545f 6358 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10474ae8 6359 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 6360}
6361
6362void kvm_arch_hardware_disable(void *garbage)
6363{
6364 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6365 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6366}
6367
6368int kvm_arch_hardware_setup(void)
6369{
6370 return kvm_x86_ops->hardware_setup();
6371}
6372
6373void kvm_arch_hardware_unsetup(void)
6374{
6375 kvm_x86_ops->hardware_unsetup();
6376}
6377
6378void kvm_arch_check_processor_compat(void *rtn)
6379{
6380 kvm_x86_ops->check_processor_compatibility(rtn);
6381}
6382
6383int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6384{
6385 struct page *page;
6386 struct kvm *kvm;
6387 int r;
6388
6389 BUG_ON(vcpu->kvm == NULL);
6390 kvm = vcpu->kvm;
6391
9aabc88f 6392 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
14dfe855 6393 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
ad312c7c 6394 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c30a358d 6395 vcpu->arch.mmu.translate_gpa = translate_gpa;
02f59dc9 6396 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
c5af89b6 6397 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6398 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6399 else
a4535290 6400 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6401
6402 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6403 if (!page) {
6404 r = -ENOMEM;
6405 goto fail;
6406 }
ad312c7c 6407 vcpu->arch.pio_data = page_address(page);
e9b11c17 6408
1e993611 6409 kvm_init_tsc_catchup(vcpu, max_tsc_khz);
c285545f 6410
e9b11c17
ZX		 6411 r = kvm_mmu_create(vcpu);
6412 if (r < 0)
6413 goto fail_free_pio_data;
6414
6415 if (irqchip_in_kernel(kvm)) {
6416 r = kvm_create_lapic(vcpu);
6417 if (r < 0)
6418 goto fail_mmu_destroy;
6419 }
6420
890ca9ae
HY		 6421 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6422 GFP_KERNEL);
6423 if (!vcpu->arch.mce_banks) {
6424 r = -ENOMEM;
443c39bc 6425 goto fail_free_lapic;
890ca9ae
HY		 6426 }
6427 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6428
f5f48ee1
SY		 6429 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6430 goto fail_free_mce_banks;
6431
af585b92
GN		 6432 kvm_async_pf_hash_reset(vcpu);
6433
e9b11c17 6434 return 0;
f5f48ee1
SY		 6435fail_free_mce_banks:
6436 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6437fail_free_lapic:
6438 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6439fail_mmu_destroy:
6440 kvm_mmu_destroy(vcpu);
6441fail_free_pio_data:
ad312c7c 6442 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6443fail:
6444 return r;
6445}
6446
6447void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6448{
f656ce01
MT		 6449 int idx;
6450
36cb93fd 6451 kfree(vcpu->arch.mce_banks);
e9b11c17 6452 kvm_free_lapic(vcpu);
f656ce01 6453 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6454 kvm_mmu_destroy(vcpu);
f656ce01 6455 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6456 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 6457}
d19a9cd2 6458
d89f5eff 6459int kvm_arch_init_vm(struct kvm *kvm)
d19a9cd2 6460{
f05e70ac 6461 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6462 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6463
5550af4d
SY		 6464 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6465 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6466
038f8c11 6467 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 6468
d89f5eff 6469 return 0;
d19a9cd2
ZX		 6470}
6471
6472static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6473{
6474 vcpu_load(vcpu);
6475 kvm_mmu_unload(vcpu);
6476 vcpu_put(vcpu);
6477}
6478
6479static void kvm_free_vcpus(struct kvm *kvm)
6480{
6481 unsigned int i;
988a2cae 6482 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6483
6484 /*
6485 * Unpin any mmu pages first.
6486 */
af585b92
GN		 6487 kvm_for_each_vcpu(i, vcpu, kvm) {
6488 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6489 kvm_unload_vcpu_mmu(vcpu);
af585b92 6490 }
988a2cae
GN		 6491 kvm_for_each_vcpu(i, vcpu, kvm)
6492 kvm_arch_vcpu_free(vcpu);
6493
6494 mutex_lock(&kvm->lock);
6495 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6496 kvm->vcpus[i] = NULL;
d19a9cd2 6497
988a2cae
GN		 6498 atomic_set(&kvm->online_vcpus, 0);
6499 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6500}
6501
ad8ba2cd
SY		 6502void kvm_arch_sync_events(struct kvm *kvm)
6503{
ba4cef31 6504 kvm_free_all_assigned_devices(kvm);
aea924f6 6505 kvm_free_pit(kvm);
ad8ba2cd
SY		 6506}
6507
d19a9cd2
ZX		 6508void kvm_arch_destroy_vm(struct kvm *kvm)
6509{
6eb55818 6510 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6511 kfree(kvm->arch.vpic);
6512 kfree(kvm->arch.vioapic);
d19a9cd2 6513 kvm_free_vcpus(kvm);
3d45830c
AK		 6514 if (kvm->arch.apic_access_page)
6515 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6516 if (kvm->arch.ept_identity_pagetable)
6517 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2 6518}
0de10343 6519
f7784b8e
MT		 6520int kvm_arch_prepare_memory_region(struct kvm *kvm,
6521 struct kvm_memory_slot *memslot,
0de10343 6522 struct kvm_memory_slot old,
f7784b8e 6523 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6524 int user_alloc)
6525{
f7784b8e 6526 int npages = memslot->npages;
7ac77099
AK		 6527 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6528
6529 /* Prevent internal slot pages from being moved by fork()/COW. */
6530 if (memslot->id >= KVM_MEMORY_SLOTS)
6531 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6532
6533 /*To keep backward compatibility with older userspace,
6534 *x86 needs to hanlde !user_alloc case.
6535 */
6536 if (!user_alloc) {
6537 if (npages && !old.rmap) {
604b38ac
AA		 6538 unsigned long userspace_addr;
6539
72dc67a6 6540 down_write(&current->mm->mmap_sem);
604b38ac
AA		 6541 userspace_addr = do_mmap(NULL, 0,
6542 npages * PAGE_SIZE,
6543 PROT_READ | PROT_WRITE,
7ac77099 6544 map_flags,
604b38ac 6545 0);
72dc67a6 6546 up_write(&current->mm->mmap_sem);
0de10343 6547
604b38ac
AA		 6548 if (IS_ERR((void *)userspace_addr))
6549 return PTR_ERR((void *)userspace_addr);
6550
604b38ac 6551 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6552 }
6553 }
6554
f7784b8e
MT		 6555
6556 return 0;
6557}
6558
6559void kvm_arch_commit_memory_region(struct kvm *kvm,
6560 struct kvm_userspace_memory_region *mem,
6561 struct kvm_memory_slot old,
6562 int user_alloc)
6563{
6564
48c0e4e9 6565 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
f7784b8e
MT		 6566
6567 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6568 int ret;
6569
6570 down_write(&current->mm->mmap_sem);
6571 ret = do_munmap(current->mm, old.userspace_addr,
6572 old.npages * PAGE_SIZE);
6573 up_write(&current->mm->mmap_sem);
6574 if (ret < 0)
6575 printk(KERN_WARNING
6576 "kvm_vm_ioctl_set_memory_region: "
6577 "failed to munmap memory\n");
6578 }
6579
48c0e4e9
XG		 6580 if (!kvm->arch.n_requested_mmu_pages)
6581 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6582
7c8a83b7 6583 spin_lock(&kvm->mmu_lock);
48c0e4e9 6584 if (nr_mmu_pages)
0de10343 6585 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
0de10343 6586 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6587 spin_unlock(&kvm->mmu_lock);
0de10343 6588}
1d737c8a 6589
34d4cb8f
MT		 6590void kvm_arch_flush_shadow(struct kvm *kvm)
6591{
6592 kvm_mmu_zap_all(kvm);
8986ecc0 6593 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6594}
6595
1d737c8a
ZX		 6596int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6597{
af585b92
GN		 6598 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6599 !vcpu->arch.apf.halted)
6600 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100
GN		 6601 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6602 || vcpu->arch.nmi_pending ||
6603 (kvm_arch_interrupt_allowed(vcpu) &&
6604 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6605}
5736199a 6606
5736199a
ZX		 6607void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6608{
32f88400
MT		 6609 int me;
6610 int cpu = vcpu->cpu;
5736199a
ZX		 6611
6612 if (waitqueue_active(&vcpu->wq)) {
6613 wake_up_interruptible(&vcpu->wq);
6614 ++vcpu->stat.halt_wakeup;
6615 }
32f88400
MT		 6616
6617 me = get_cpu();
6618 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
6b7e2d09 6619 if (kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE)
32f88400 6620 smp_send_reschedule(cpu);
e9571ed5 6621 put_cpu();
5736199a 6622}
78646121
GN		 6623
6624int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6625{
6626 return kvm_x86_ops->interrupt_allowed(vcpu);
6627}
229456fc 6628
f92653ee
JK		 6629bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6630{
6631 unsigned long current_rip = kvm_rip_read(vcpu) +
6632 get_segment_base(vcpu, VCPU_SREG_CS);
6633
6634 return current_rip == linear_rip;
6635}
6636EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6637
94fe45da
JK		 6638unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6639{
6640 unsigned long rflags;
6641
6642 rflags = kvm_x86_ops->get_rflags(vcpu);
6643 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6644 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6645 return rflags;
6646}
6647EXPORT_SYMBOL_GPL(kvm_get_rflags);
6648
6649void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6650{
6651 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6652 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6653 rflags |= X86_EFLAGS_TF;
94fe45da 6654 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6655 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6656}
6657EXPORT_SYMBOL_GPL(kvm_set_rflags);
6658
56028d08
GN		 6659void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6660{
6661 int r;
6662
fb67e14f 6663 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6664 is_error_page(work->page))
56028d08
GN		 6665 return;
6666
6667 r = kvm_mmu_reload(vcpu);
6668 if (unlikely(r))
6669 return;
6670
fb67e14f
XG		 6671 if (!vcpu->arch.mmu.direct_map &&
6672 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6673 return;
6674
56028d08
GN		 6675 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6676}
6677
af585b92
GN		 6678static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6679{
6680 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6681}
6682
6683static inline u32 kvm_async_pf_next_probe(u32 key)
6684{
6685 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6686}
6687
6688static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6689{
6690 u32 key = kvm_async_pf_hash_fn(gfn);
6691
6692 while (vcpu->arch.apf.gfns[key] != ~0)
6693 key = kvm_async_pf_next_probe(key);
6694
6695 vcpu->arch.apf.gfns[key] = gfn;
6696}
6697
6698static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6699{
6700 int i;
6701 u32 key = kvm_async_pf_hash_fn(gfn);
6702
6703 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6704 (vcpu->arch.apf.gfns[key] != gfn &&
6705 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6706 key = kvm_async_pf_next_probe(key);
6707
6708 return key;
6709}
6710
6711bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6712{
6713 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6714}
6715
6716static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6717{
6718 u32 i, j, k;
6719
6720 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6721 while (true) {
6722 vcpu->arch.apf.gfns[i] = ~0;
6723 do {
6724 j = kvm_async_pf_next_probe(j);
6725 if (vcpu->arch.apf.gfns[j] == ~0)
6726 return;
6727 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6728 /*
6729 * k lies cyclically in ]i,j]
6730 * | i.k.j |
6731 * |....j i.k.| or |.k..j i...|
6732 */
6733 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6734 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6735 i = j;
6736 }
6737}
6738
7c90705b
GN		 6739static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6740{
6741
6742 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6743 sizeof(val));
6744}
6745
af585b92
GN		 6746void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6747 struct kvm_async_pf *work)
6748{
6389ee94
AK		 6749 struct x86_exception fault;
6750
7c90705b 6751 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6752 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6753
6754 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6755 (vcpu->arch.apf.send_user_only &&
6756 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6757 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6758 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6759 fault.vector = PF_VECTOR;
6760 fault.error_code_valid = true;
6761 fault.error_code = 0;
6762 fault.nested_page_fault = false;
6763 fault.address = work->arch.token;
6764 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6765 }
af585b92
GN		 6766}
6767
6768void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6769 struct kvm_async_pf *work)
6770{
6389ee94
AK		 6771 struct x86_exception fault;
6772
7c90705b
GN		 6773 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6774 if (is_error_page(work->page))
6775 work->arch.token = ~0; /* broadcast wakeup */
6776 else
6777 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6778
6779 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6780 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6781 fault.vector = PF_VECTOR;
6782 fault.error_code_valid = true;
6783 fault.error_code = 0;
6784 fault.nested_page_fault = false;
6785 fault.address = work->arch.token;
6786 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6787 }
e6d53e3b 6788 vcpu->arch.apf.halted = false;
7c90705b
GN		 6789}
6790
6791bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6792{
6793 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6794 return true;
6795 else
6796 return !kvm_event_needs_reinjection(vcpu) &&
6797 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6798}
6799
229456fc
MT		 6800EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6801EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6802EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6803EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6804EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6805EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6806EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6807EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6808EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6809EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6810EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6811EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
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