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KVM: return true when user space query KVM_CAP_USER_NMI extension
[mirror_ubuntu-jammy-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
af585b92 46#include <linux/hash.h>
aec51dc4 47#include <trace/events/kvm.h>
2ed152af 48
229456fc
MT		 49#define CREATE_TRACE_POINTS
50#include "trace.h"
043405e1 51
24f1e32c 52#include <asm/debugreg.h>
d825ed0a 53#include <asm/msr.h>
a5f61300 54#include <asm/desc.h>
0bed3b56 55#include <asm/mtrr.h>
890ca9ae 56#include <asm/mce.h>
7cf30855 57#include <asm/i387.h>
98918833 58#include <asm/xcr.h>
1d5f066e 59#include <asm/pvclock.h>
217fc9cf 60#include <asm/div64.h>
043405e1 61
313a3dc7 62#define MAX_IO_MSRS 256
a03490ed
CO		 63#define CR0_RESERVED_BITS \
64 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
65 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
66 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
67#define CR4_RESERVED_BITS \
68 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
69 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
70 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
2acf923e 71 | X86_CR4_OSXSAVE \
a03490ed
CO		 72 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
73
74#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 75
76#define KVM_MAX_MCE_BANKS 32
5854dbca 77#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 78
50a37eb4
JR		 79/* EFER defaults:
80 * - enable syscall per default because its emulated by KVM
81 * - enable LME and LMA per default on 64 bit KVM
82 */
83#ifdef CONFIG_X86_64
84static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
85#else
86static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
87#endif
313a3dc7 88
ba1389b7
AK		 89#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 91
cb142eb7 92static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 93static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
94 struct kvm_cpuid_entry2 __user *entries);
95
97896d04 96struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 97EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 98
ed85c068
AP		 99int ignore_msrs = 0;
100module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
101
18863bdd
AK		 102#define KVM_NR_SHARED_MSRS 16
103
104struct kvm_shared_msrs_global {
105 int nr;
2bf78fa7 106 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 107};
108
109struct kvm_shared_msrs {
110 struct user_return_notifier urn;
111 bool registered;
2bf78fa7
SY		 112 struct kvm_shared_msr_values {
113 u64 host;
114 u64 curr;
115 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 116};
117
118static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
119static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
120
417bc304 121struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 122 { "pf_fixed", VCPU_STAT(pf_fixed) },
123 { "pf_guest", VCPU_STAT(pf_guest) },
124 { "tlb_flush", VCPU_STAT(tlb_flush) },
125 { "invlpg", VCPU_STAT(invlpg) },
126 { "exits", VCPU_STAT(exits) },
127 { "io_exits", VCPU_STAT(io_exits) },
128 { "mmio_exits", VCPU_STAT(mmio_exits) },
129 { "signal_exits", VCPU_STAT(signal_exits) },
130 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 131 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 132 { "halt_exits", VCPU_STAT(halt_exits) },
133 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 134 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 135 { "request_irq", VCPU_STAT(request_irq_exits) },
136 { "irq_exits", VCPU_STAT(irq_exits) },
137 { "host_state_reload", VCPU_STAT(host_state_reload) },
138 { "efer_reload", VCPU_STAT(efer_reload) },
139 { "fpu_reload", VCPU_STAT(fpu_reload) },
140 { "insn_emulation", VCPU_STAT(insn_emulation) },
141 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 142 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 143 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 144 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
145 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
146 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
147 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
148 { "mmu_flooded", VM_STAT(mmu_flooded) },
149 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 150 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 151 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 152 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 153 { "largepages", VM_STAT(lpages) },
417bc304
HB		 154 { NULL }
155};
156
2acf923e
DC		 157u64 __read_mostly host_xcr0;
158
af585b92
GN		 159static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
160{
161 int i;
162 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
163 vcpu->arch.apf.gfns[i] = ~0;
164}
165
18863bdd
AK		 166static void kvm_on_user_return(struct user_return_notifier *urn)
167{
168 unsigned slot;
18863bdd
AK		 169 struct kvm_shared_msrs *locals
170 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 171 struct kvm_shared_msr_values *values;
18863bdd
AK		 172
173 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 174 values = &locals->values[slot];
175 if (values->host != values->curr) {
176 wrmsrl(shared_msrs_global.msrs[slot], values->host);
177 values->curr = values->host;
18863bdd
AK		 178 }
179 }
180 locals->registered = false;
181 user_return_notifier_unregister(urn);
182}
183
2bf78fa7 184static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 185{
2bf78fa7 186 struct kvm_shared_msrs *smsr;
18863bdd
AK		 187 u64 value;
188
2bf78fa7
SY		 189 smsr = &__get_cpu_var(shared_msrs);
190 /* only read, and nobody should modify it at this time,
191 * so don't need lock */
192 if (slot >= shared_msrs_global.nr) {
193 printk(KERN_ERR "kvm: invalid MSR slot!");
194 return;
195 }
196 rdmsrl_safe(msr, &value);
197 smsr->values[slot].host = value;
198 smsr->values[slot].curr = value;
199}
200
201void kvm_define_shared_msr(unsigned slot, u32 msr)
202{
18863bdd
AK		 203 if (slot >= shared_msrs_global.nr)
204 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 205 shared_msrs_global.msrs[slot] = msr;
206 /* we need ensured the shared_msr_global have been updated */
207 smp_wmb();
18863bdd
AK		 208}
209EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
210
211static void kvm_shared_msr_cpu_online(void)
212{
213 unsigned i;
18863bdd
AK		 214
215 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 216 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 217}
218
d5696725 219void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 220{
221 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
222
2bf78fa7 223 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 224 return;
2bf78fa7
SY		 225 smsr->values[slot].curr = value;
226 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 227 if (!smsr->registered) {
228 smsr->urn.on_user_return = kvm_on_user_return;
229 user_return_notifier_register(&smsr->urn);
230 smsr->registered = true;
231 }
232}
233EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
234
3548bab5
AK		 235static void drop_user_return_notifiers(void *ignore)
236{
237 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
238
239 if (smsr->registered)
240 kvm_on_user_return(&smsr->urn);
241}
242
6866b83e
CO		 243u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
244{
245 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 246 return vcpu->arch.apic_base;
6866b83e 247 else
ad312c7c 248 return vcpu->arch.apic_base;
6866b83e
CO		 249}
250EXPORT_SYMBOL_GPL(kvm_get_apic_base);
251
252void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
253{
254 /* TODO: reserve bits check */
255 if (irqchip_in_kernel(vcpu->kvm))
256 kvm_lapic_set_base(vcpu, data);
257 else
ad312c7c 258 vcpu->arch.apic_base = data;
6866b83e
CO		 259}
260EXPORT_SYMBOL_GPL(kvm_set_apic_base);
261
3fd28fce
ED		 262#define EXCPT_BENIGN 0
263#define EXCPT_CONTRIBUTORY 1
264#define EXCPT_PF 2
265
266static int exception_class(int vector)
267{
268 switch (vector) {
269 case PF_VECTOR:
270 return EXCPT_PF;
271 case DE_VECTOR:
272 case TS_VECTOR:
273 case NP_VECTOR:
274 case SS_VECTOR:
275 case GP_VECTOR:
276 return EXCPT_CONTRIBUTORY;
277 default:
278 break;
279 }
280 return EXCPT_BENIGN;
281}
282
283static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 284 unsigned nr, bool has_error, u32 error_code,
285 bool reinject)
3fd28fce
ED		 286{
287 u32 prev_nr;
288 int class1, class2;
289
3842d135
AK		 290 kvm_make_request(KVM_REQ_EVENT, vcpu);
291
3fd28fce
ED		 292 if (!vcpu->arch.exception.pending) {
293 queue:
294 vcpu->arch.exception.pending = true;
295 vcpu->arch.exception.has_error_code = has_error;
296 vcpu->arch.exception.nr = nr;
297 vcpu->arch.exception.error_code = error_code;
3f0fd292 298 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 299 return;
300 }
301
302 /* to check exception */
303 prev_nr = vcpu->arch.exception.nr;
304 if (prev_nr == DF_VECTOR) {
305 /* triple fault -> shutdown */
a8eeb04a 306 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 307 return;
308 }
309 class1 = exception_class(prev_nr);
310 class2 = exception_class(nr);
311 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
312 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
313 /* generate double fault per SDM Table 5-5 */
314 vcpu->arch.exception.pending = true;
315 vcpu->arch.exception.has_error_code = true;
316 vcpu->arch.exception.nr = DF_VECTOR;
317 vcpu->arch.exception.error_code = 0;
318 } else
319 /* replace previous exception with a new one in a hope
320 that instruction re-execution will regenerate lost
321 exception */
322 goto queue;
323}
324
298101da
AK		 325void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
326{
ce7ddec4 327 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 328}
329EXPORT_SYMBOL_GPL(kvm_queue_exception);
330
ce7ddec4
JR		 331void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
332{
333 kvm_multiple_exception(vcpu, nr, false, 0, true);
334}
335EXPORT_SYMBOL_GPL(kvm_requeue_exception);
336
6389ee94 337void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 338{
339 ++vcpu->stat.pf_guest;
6389ee94
AK		 340 vcpu->arch.cr2 = fault->address;
341 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee
AK		 342}
343
6389ee94 344void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 345{
6389ee94
AK		 346 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
347 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 348 else
6389ee94 349 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 350}
351
3419ffc8
SY		 352void kvm_inject_nmi(struct kvm_vcpu *vcpu)
353{
3842d135 354 kvm_make_request(KVM_REQ_EVENT, vcpu);
3419ffc8
SY		 355 vcpu->arch.nmi_pending = 1;
356}
357EXPORT_SYMBOL_GPL(kvm_inject_nmi);
358
298101da
AK		 359void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
360{
ce7ddec4 361 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 362}
363EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
364
ce7ddec4
JR		 365void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
366{
367 kvm_multiple_exception(vcpu, nr, true, error_code, true);
368}
369EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
370
0a79b009
AK		 371/*
372 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
373 * a #GP and return false.
374 */
375bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 376{
0a79b009
AK		 377 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
378 return true;
379 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
380 return false;
298101da 381}
0a79b009 382EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 383
ec92fe44
JR		 384/*
385 * This function will be used to read from the physical memory of the currently
386 * running guest. The difference to kvm_read_guest_page is that this function
387 * can read from guest physical or from the guest's guest physical memory.
388 */
389int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
390 gfn_t ngfn, void *data, int offset, int len,
391 u32 access)
392{
393 gfn_t real_gfn;
394 gpa_t ngpa;
395
396 ngpa = gfn_to_gpa(ngfn);
397 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
398 if (real_gfn == UNMAPPED_GVA)
399 return -EFAULT;
400
401 real_gfn = gpa_to_gfn(real_gfn);
402
403 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
404}
405EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
406
3d06b8bf
JR		 407int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
408 void *data, int offset, int len, u32 access)
409{
410 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
411 data, offset, len, access);
412}
413
a03490ed
CO		 414/*
415 * Load the pae pdptrs. Return true is they are all valid.
416 */
ff03a073 417int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 418{
419 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
420 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
421 int i;
422 int ret;
ff03a073 423 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 424
ff03a073
JR		 425 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
426 offset * sizeof(u64), sizeof(pdpte),
427 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 428 if (ret < 0) {
429 ret = 0;
430 goto out;
431 }
432 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 433 if (is_present_gpte(pdpte[i]) &&
20c466b5 434 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 435 ret = 0;
436 goto out;
437 }
438 }
439 ret = 1;
440
ff03a073 441 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 442 __set_bit(VCPU_EXREG_PDPTR,
443 (unsigned long *)&vcpu->arch.regs_avail);
444 __set_bit(VCPU_EXREG_PDPTR,
445 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 446out:
a03490ed
CO		 447
448 return ret;
449}
cc4b6871 450EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 451
d835dfec
AK		 452static bool pdptrs_changed(struct kvm_vcpu *vcpu)
453{
ff03a073 454 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 455 bool changed = true;
3d06b8bf
JR		 456 int offset;
457 gfn_t gfn;
d835dfec
AK		 458 int r;
459
460 if (is_long_mode(vcpu) || !is_pae(vcpu))
461 return false;
462
6de4f3ad
AK		 463 if (!test_bit(VCPU_EXREG_PDPTR,
464 (unsigned long *)&vcpu->arch.regs_avail))
465 return true;
466
3d06b8bf
JR		 467 gfn = (vcpu->arch.cr3 & ~31u) >> PAGE_SHIFT;
468 offset = (vcpu->arch.cr3 & ~31u) & (PAGE_SIZE - 1);
469 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
470 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 471 if (r < 0)
472 goto out;
ff03a073 473 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 474out:
d835dfec
AK		 475
476 return changed;
477}
478
49a9b07e 479int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 480{
aad82703
SY		 481 unsigned long old_cr0 = kvm_read_cr0(vcpu);
482 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
483 X86_CR0_CD | X86_CR0_NW;
484
f9a48e6a
AK		 485 cr0 |= X86_CR0_ET;
486
ab344828 487#ifdef CONFIG_X86_64
0f12244f
GN		 488 if (cr0 & 0xffffffff00000000UL)
489 return 1;
ab344828
GN		 490#endif
491
492 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 493
0f12244f
GN		 494 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
495 return 1;
a03490ed 496
0f12244f
GN		 497 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
498 return 1;
a03490ed
CO		 499
500 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
501#ifdef CONFIG_X86_64
f6801dff 502 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 503 int cs_db, cs_l;
504
0f12244f
GN		 505 if (!is_pae(vcpu))
506 return 1;
a03490ed 507 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 508 if (cs_l)
509 return 1;
a03490ed
CO		 510 } else
511#endif
ff03a073
JR		 512 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
513 vcpu->arch.cr3))
0f12244f 514 return 1;
a03490ed
CO		 515 }
516
517 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 518
e5f3f027
XG		 519 if ((cr0 ^ old_cr0) & X86_CR0_PG)
520 kvm_clear_async_pf_completion_queue(vcpu);
521
aad82703
SY		 522 if ((cr0 ^ old_cr0) & update_bits)
523 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 524 return 0;
525}
2d3ad1f4 526EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 527
2d3ad1f4 528void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 529{
49a9b07e 530 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 531}
2d3ad1f4 532EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 533
2acf923e
DC		 534int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
535{
536 u64 xcr0;
537
538 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
539 if (index != XCR_XFEATURE_ENABLED_MASK)
540 return 1;
541 xcr0 = xcr;
542 if (kvm_x86_ops->get_cpl(vcpu) != 0)
543 return 1;
544 if (!(xcr0 & XSTATE_FP))
545 return 1;
546 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
547 return 1;
548 if (xcr0 & ~host_xcr0)
549 return 1;
550 vcpu->arch.xcr0 = xcr0;
551 vcpu->guest_xcr0_loaded = 0;
552 return 0;
553}
554
555int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
556{
557 if (__kvm_set_xcr(vcpu, index, xcr)) {
558 kvm_inject_gp(vcpu, 0);
559 return 1;
560 }
561 return 0;
562}
563EXPORT_SYMBOL_GPL(kvm_set_xcr);
564
565static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
566{
567 struct kvm_cpuid_entry2 *best;
568
569 best = kvm_find_cpuid_entry(vcpu, 1, 0);
570 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
571}
572
573static void update_cpuid(struct kvm_vcpu *vcpu)
574{
575 struct kvm_cpuid_entry2 *best;
576
577 best = kvm_find_cpuid_entry(vcpu, 1, 0);
578 if (!best)
579 return;
580
581 /* Update OSXSAVE bit */
582 if (cpu_has_xsave && best->function == 0x1) {
583 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
584 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
585 best->ecx |= bit(X86_FEATURE_OSXSAVE);
586 }
587}
588
a83b29c6 589int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 590{
fc78f519 591 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 592 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
593
0f12244f
GN		 594 if (cr4 & CR4_RESERVED_BITS)
595 return 1;
a03490ed 596
2acf923e
DC		 597 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
598 return 1;
599
a03490ed 600 if (is_long_mode(vcpu)) {
0f12244f
GN		 601 if (!(cr4 & X86_CR4_PAE))
602 return 1;
a2edf57f
AK		 603 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
604 && ((cr4 ^ old_cr4) & pdptr_bits)
ff03a073 605 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3))
0f12244f
GN		 606 return 1;
607
608 if (cr4 & X86_CR4_VMXE)
609 return 1;
a03490ed 610
a03490ed 611 kvm_x86_ops->set_cr4(vcpu, cr4);
62ad0755 612
aad82703
SY		 613 if ((cr4 ^ old_cr4) & pdptr_bits)
614 kvm_mmu_reset_context(vcpu);
0f12244f 615
2acf923e
DC		 616 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
617 update_cpuid(vcpu);
618
0f12244f
GN		 619 return 0;
620}
2d3ad1f4 621EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 622
2390218b 623int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 624{
ad312c7c 625 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 626 kvm_mmu_sync_roots(vcpu);
d835dfec 627 kvm_mmu_flush_tlb(vcpu);
0f12244f 628 return 0;
d835dfec
AK		 629 }
630
a03490ed 631 if (is_long_mode(vcpu)) {
0f12244f
GN		 632 if (cr3 & CR3_L_MODE_RESERVED_BITS)
633 return 1;
a03490ed
CO		 634 } else {
635 if (is_pae(vcpu)) {
0f12244f
GN		 636 if (cr3 & CR3_PAE_RESERVED_BITS)
637 return 1;
ff03a073
JR		 638 if (is_paging(vcpu) &&
639 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 640 return 1;
a03490ed
CO		 641 }
642 /*
643 * We don't check reserved bits in nonpae mode, because
644 * this isn't enforced, and VMware depends on this.
645 */
646 }
647
a03490ed
CO		 648 /*
649 * Does the new cr3 value map to physical memory? (Note, we
650 * catch an invalid cr3 even in real-mode, because it would
651 * cause trouble later on when we turn on paging anyway.)
652 *
653 * A real CPU would silently accept an invalid cr3 and would
654 * attempt to use it - with largely undefined (and often hard
655 * to debug) behavior on the guest side.
656 */
657 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 658 return 1;
659 vcpu->arch.cr3 = cr3;
660 vcpu->arch.mmu.new_cr3(vcpu);
661 return 0;
662}
2d3ad1f4 663EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 664
0f12244f 665int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 666{
0f12244f
GN		 667 if (cr8 & CR8_RESERVED_BITS)
668 return 1;
a03490ed
CO		 669 if (irqchip_in_kernel(vcpu->kvm))
670 kvm_lapic_set_tpr(vcpu, cr8);
671 else
ad312c7c 672 vcpu->arch.cr8 = cr8;
0f12244f
GN		 673 return 0;
674}
675
676void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
677{
678 if (__kvm_set_cr8(vcpu, cr8))
679 kvm_inject_gp(vcpu, 0);
a03490ed 680}
2d3ad1f4 681EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 682
2d3ad1f4 683unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 684{
685 if (irqchip_in_kernel(vcpu->kvm))
686 return kvm_lapic_get_cr8(vcpu);
687 else
ad312c7c 688 return vcpu->arch.cr8;
a03490ed 689}
2d3ad1f4 690EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 691
338dbc97 692static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 693{
694 switch (dr) {
695 case 0 ... 3:
696 vcpu->arch.db[dr] = val;
697 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
698 vcpu->arch.eff_db[dr] = val;
699 break;
700 case 4:
338dbc97
GN		 701 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
702 return 1; /* #UD */
020df079
GN		 703 /* fall through */
704 case 6:
338dbc97
GN		 705 if (val & 0xffffffff00000000ULL)
706 return -1; /* #GP */
020df079
GN		 707 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
708 break;
709 case 5:
338dbc97
GN		 710 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
711 return 1; /* #UD */
020df079
GN		 712 /* fall through */
713 default: /* 7 */
338dbc97
GN		 714 if (val & 0xffffffff00000000ULL)
715 return -1; /* #GP */
020df079
GN		 716 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
717 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
718 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
719 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
720 }
721 break;
722 }
723
724 return 0;
725}
338dbc97
GN		 726
727int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
728{
729 int res;
730
731 res = __kvm_set_dr(vcpu, dr, val);
732 if (res > 0)
733 kvm_queue_exception(vcpu, UD_VECTOR);
734 else if (res < 0)
735 kvm_inject_gp(vcpu, 0);
736
737 return res;
738}
020df079
GN		 739EXPORT_SYMBOL_GPL(kvm_set_dr);
740
338dbc97 741static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 742{
743 switch (dr) {
744 case 0 ... 3:
745 *val = vcpu->arch.db[dr];
746 break;
747 case 4:
338dbc97 748 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 749 return 1;
020df079
GN		 750 /* fall through */
751 case 6:
752 *val = vcpu->arch.dr6;
753 break;
754 case 5:
338dbc97 755 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 756 return 1;
020df079
GN		 757 /* fall through */
758 default: /* 7 */
759 *val = vcpu->arch.dr7;
760 break;
761 }
762
763 return 0;
764}
338dbc97
GN		 765
766int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
767{
768 if (_kvm_get_dr(vcpu, dr, val)) {
769 kvm_queue_exception(vcpu, UD_VECTOR);
770 return 1;
771 }
772 return 0;
773}
020df079
GN		 774EXPORT_SYMBOL_GPL(kvm_get_dr);
775
043405e1
CO		 776/*
777 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
778 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
779 *
780 * This list is modified at module load time to reflect the
e3267cbb
GC		 781 * capabilities of the host cpu. This capabilities test skips MSRs that are
782 * kvm-specific. Those are put in the beginning of the list.
043405e1 783 */
e3267cbb 784
344d9588 785#define KVM_SAVE_MSRS_BEGIN 8
043405e1 786static u32 msrs_to_save[] = {
e3267cbb 787 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 788 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 789 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
344d9588 790 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN,
043405e1 791 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 792 MSR_STAR,
043405e1
CO		 793#ifdef CONFIG_X86_64
794 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
795#endif
e90aa41e 796 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 797};
798
799static unsigned num_msrs_to_save;
800
801static u32 emulated_msrs[] = {
802 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 803 MSR_IA32_MCG_STATUS,
804 MSR_IA32_MCG_CTL,
043405e1
CO		 805};
806
b69e8cae 807static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 808{
aad82703
SY		 809 u64 old_efer = vcpu->arch.efer;
810
b69e8cae
RJ		 811 if (efer & efer_reserved_bits)
812 return 1;
15c4a640
CO		 813
814 if (is_paging(vcpu)
b69e8cae
RJ		 815 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
816 return 1;
15c4a640 817
1b2fd70c
AG		 818 if (efer & EFER_FFXSR) {
819 struct kvm_cpuid_entry2 *feat;
820
821 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 822 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
823 return 1;
1b2fd70c
AG		 824 }
825
d8017474
AG		 826 if (efer & EFER_SVME) {
827 struct kvm_cpuid_entry2 *feat;
828
829 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 830 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
831 return 1;
d8017474
AG		 832 }
833
15c4a640 834 efer &= ~EFER_LMA;
f6801dff 835 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 836
a3d204e2
SY		 837 kvm_x86_ops->set_efer(vcpu, efer);
838
9645bb56 839 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 840
aad82703
SY		 841 /* Update reserved bits */
842 if ((efer ^ old_efer) & EFER_NX)
843 kvm_mmu_reset_context(vcpu);
844
b69e8cae 845 return 0;
15c4a640
CO		 846}
847
f2b4b7dd
JR		 848void kvm_enable_efer_bits(u64 mask)
849{
850 efer_reserved_bits &= ~mask;
851}
852EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
853
854
15c4a640
CO		 855/*
856 * Writes msr value into into the appropriate "register".
857 * Returns 0 on success, non-0 otherwise.
858 * Assumes vcpu_load() was already called.
859 */
860int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
861{
862 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
863}
864
313a3dc7
CO		 865/*
866 * Adapt set_msr() to msr_io()'s calling convention
867 */
868static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
869{
870 return kvm_set_msr(vcpu, index, *data);
871}
872
18068523
GOC		 873static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
874{
9ed3c444
AK		 875 int version;
876 int r;
50d0a0f9 877 struct pvclock_wall_clock wc;
923de3cf 878 struct timespec boot;
18068523
GOC		 879
880 if (!wall_clock)
881 return;
882
9ed3c444
AK		 883 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
884 if (r)
885 return;
886
887 if (version & 1)
888 ++version; /* first time write, random junk */
889
890 ++version;
18068523 891
18068523
GOC		 892 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
893
50d0a0f9
GH		 894 /*
895 * The guest calculates current wall clock time by adding
34c238a1 896 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 897 * wall clock specified here. guest system time equals host
898 * system time for us, thus we must fill in host boot time here.
899 */
923de3cf 900 getboottime(&boot);
50d0a0f9
GH		 901
902 wc.sec = boot.tv_sec;
903 wc.nsec = boot.tv_nsec;
904 wc.version = version;
18068523
GOC		 905
906 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
907
908 version++;
909 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 910}
911
50d0a0f9
GH		 912static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
913{
914 uint32_t quotient, remainder;
915
916 /* Don't try to replace with do_div(), this one calculates
917 * "(dividend << 32) / divisor" */
918 __asm__ ( "divl %4"
919 : "=a" (quotient), "=d" (remainder)
920 : "0" (0), "1" (dividend), "r" (divisor) );
921 return quotient;
922}
923
5f4e3f88
ZA		 924static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
925 s8 *pshift, u32 *pmultiplier)
50d0a0f9 926{
5f4e3f88 927 uint64_t scaled64;
50d0a0f9
GH		 928 int32_t shift = 0;
929 uint64_t tps64;
930 uint32_t tps32;
931
5f4e3f88
ZA		 932 tps64 = base_khz * 1000LL;
933 scaled64 = scaled_khz * 1000LL;
50933623 934 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 935 tps64 >>= 1;
936 shift--;
937 }
938
939 tps32 = (uint32_t)tps64;
50933623
JK		 940 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
941 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 942 scaled64 >>= 1;
943 else
944 tps32 <<= 1;
50d0a0f9
GH		 945 shift++;
946 }
947
5f4e3f88
ZA		 948 *pshift = shift;
949 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 950
5f4e3f88
ZA		 951 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
952 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 953}
954
759379dd
ZA		 955static inline u64 get_kernel_ns(void)
956{
957 struct timespec ts;
958
959 WARN_ON(preemptible());
960 ktime_get_ts(&ts);
961 monotonic_to_bootbased(&ts);
962 return timespec_to_ns(&ts);
50d0a0f9
GH		 963}
964
c8076604 965static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 966unsigned long max_tsc_khz;
c8076604 967
8cfdc000
ZA		 968static inline int kvm_tsc_changes_freq(void)
969{
970 int cpu = get_cpu();
971 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
972 cpufreq_quick_get(cpu) != 0;
973 put_cpu();
974 return ret;
975}
976
759379dd
ZA		 977static inline u64 nsec_to_cycles(u64 nsec)
978{
217fc9cf
AK		 979 u64 ret;
980
759379dd
ZA		 981 WARN_ON(preemptible());
982 if (kvm_tsc_changes_freq())
983 printk_once(KERN_WARNING
984 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
217fc9cf
AK		 985 ret = nsec * __get_cpu_var(cpu_tsc_khz);
986 do_div(ret, USEC_PER_SEC);
987 return ret;
759379dd
ZA		 988}
989
c285545f
ZA		 990static void kvm_arch_set_tsc_khz(struct kvm *kvm, u32 this_tsc_khz)
991{
992 /* Compute a scale to convert nanoseconds in TSC cycles */
993 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
994 &kvm->arch.virtual_tsc_shift,
995 &kvm->arch.virtual_tsc_mult);
996 kvm->arch.virtual_tsc_khz = this_tsc_khz;
997}
998
999static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1000{
1001 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
1002 vcpu->kvm->arch.virtual_tsc_mult,
1003 vcpu->kvm->arch.virtual_tsc_shift);
1004 tsc += vcpu->arch.last_tsc_write;
1005 return tsc;
1006}
1007
99e3e30a
ZA		 1008void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1009{
1010 struct kvm *kvm = vcpu->kvm;
f38e098f 1011 u64 offset, ns, elapsed;
99e3e30a 1012 unsigned long flags;
46543ba4 1013 s64 sdiff;
99e3e30a
ZA		 1014
1015 spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1016 offset = data - native_read_tsc();
759379dd 1017 ns = get_kernel_ns();
f38e098f 1018 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 1019 sdiff = data - kvm->arch.last_tsc_write;
1020 if (sdiff < 0)
1021 sdiff = -sdiff;
f38e098f
ZA		 1022
1023 /*
46543ba4 1024 * Special case: close write to TSC within 5 seconds of
f38e098f 1025 * another CPU is interpreted as an attempt to synchronize
46543ba4
ZA		 1026 * The 5 seconds is to accomodate host load / swapping as
1027 * well as any reset of TSC during the boot process.
f38e098f
ZA		 1028 *
1029 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 1030 * or make a best guest using elapsed value.
f38e098f 1031 */
46543ba4
ZA		 1032 if (sdiff < nsec_to_cycles(5ULL * NSEC_PER_SEC) &&
1033 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 1034 if (!check_tsc_unstable()) {
1035 offset = kvm->arch.last_tsc_offset;
1036 pr_debug("kvm: matched tsc offset for %llu\n", data);
1037 } else {
759379dd
ZA		 1038 u64 delta = nsec_to_cycles(elapsed);
1039 offset += delta;
1040 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1041 }
1042 ns = kvm->arch.last_tsc_nsec;
1043 }
1044 kvm->arch.last_tsc_nsec = ns;
1045 kvm->arch.last_tsc_write = data;
1046 kvm->arch.last_tsc_offset = offset;
99e3e30a
ZA		 1047 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1048 spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1049
1050 /* Reset of TSC must disable overshoot protection below */
1051 vcpu->arch.hv_clock.tsc_timestamp = 0;
c285545f
ZA		 1052 vcpu->arch.last_tsc_write = data;
1053 vcpu->arch.last_tsc_nsec = ns;
99e3e30a
ZA		 1054}
1055EXPORT_SYMBOL_GPL(kvm_write_tsc);
1056
34c238a1 1057static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1058{
18068523
GOC		 1059 unsigned long flags;
1060 struct kvm_vcpu_arch *vcpu = &v->arch;
1061 void *shared_kaddr;
463656c0 1062 unsigned long this_tsc_khz;
1d5f066e
ZA		 1063 s64 kernel_ns, max_kernel_ns;
1064 u64 tsc_timestamp;
18068523 1065
18068523
GOC		 1066 /* Keep irq disabled to prevent changes to the clock */
1067 local_irq_save(flags);
1d5f066e 1068 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
759379dd 1069 kernel_ns = get_kernel_ns();
8cfdc000 1070 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
18068523 1071
8cfdc000 1072 if (unlikely(this_tsc_khz == 0)) {
c285545f 1073 local_irq_restore(flags);
34c238a1 1074 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1075 return 1;
1076 }
18068523 1077
c285545f
ZA		 1078 /*
1079 * We may have to catch up the TSC to match elapsed wall clock
1080 * time for two reasons, even if kvmclock is used.
1081 * 1) CPU could have been running below the maximum TSC rate
1082 * 2) Broken TSC compensation resets the base at each VCPU
1083 * entry to avoid unknown leaps of TSC even when running
1084 * again on the same CPU. This may cause apparent elapsed
1085 * time to disappear, and the guest to stand still or run
1086 * very slowly.
1087 */
1088 if (vcpu->tsc_catchup) {
1089 u64 tsc = compute_guest_tsc(v, kernel_ns);
1090 if (tsc > tsc_timestamp) {
1091 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1092 tsc_timestamp = tsc;
1093 }
50d0a0f9
GH		 1094 }
1095
18068523
GOC		 1096 local_irq_restore(flags);
1097
c285545f
ZA		 1098 if (!vcpu->time_page)
1099 return 0;
18068523 1100
1d5f066e
ZA		 1101 /*
1102 * Time as measured by the TSC may go backwards when resetting the base
1103 * tsc_timestamp. The reason for this is that the TSC resolution is
1104 * higher than the resolution of the other clock scales. Thus, many
1105 * possible measurments of the TSC correspond to one measurement of any
1106 * other clock, and so a spread of values is possible. This is not a
1107 * problem for the computation of the nanosecond clock; with TSC rates
1108 * around 1GHZ, there can only be a few cycles which correspond to one
1109 * nanosecond value, and any path through this code will inevitably
1110 * take longer than that. However, with the kernel_ns value itself,
1111 * the precision may be much lower, down to HZ granularity. If the
1112 * first sampling of TSC against kernel_ns ends in the low part of the
1113 * range, and the second in the high end of the range, we can get:
1114 *
1115 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1116 *
1117 * As the sampling errors potentially range in the thousands of cycles,
1118 * it is possible such a time value has already been observed by the
1119 * guest. To protect against this, we must compute the system time as
1120 * observed by the guest and ensure the new system time is greater.
1121 */
1122 max_kernel_ns = 0;
1123 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1124 max_kernel_ns = vcpu->last_guest_tsc -
1125 vcpu->hv_clock.tsc_timestamp;
1126 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1127 vcpu->hv_clock.tsc_to_system_mul,
1128 vcpu->hv_clock.tsc_shift);
1129 max_kernel_ns += vcpu->last_kernel_ns;
1130 }
afbcf7ab 1131
e48672fa 1132 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1133 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1134 &vcpu->hv_clock.tsc_shift,
1135 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1136 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1137 }
1138
1d5f066e
ZA		 1139 if (max_kernel_ns > kernel_ns)
1140 kernel_ns = max_kernel_ns;
1141
8cfdc000 1142 /* With all the info we got, fill in the values */
1d5f066e 1143 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1144 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1145 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1146 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1147 vcpu->hv_clock.flags = 0;
1148
18068523
GOC		 1149 /*
1150 * The interface expects us to write an even number signaling that the
1151 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1152 * state, we just increase by 2 at the end.
18068523 1153 */
50d0a0f9 1154 vcpu->hv_clock.version += 2;
18068523
GOC		 1155
1156 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1157
1158 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1159 sizeof(vcpu->hv_clock));
18068523
GOC		 1160
1161 kunmap_atomic(shared_kaddr, KM_USER0);
1162
1163 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1164 return 0;
c8076604
GH		 1165}
1166
9ba075a6
AK		 1167static bool msr_mtrr_valid(unsigned msr)
1168{
1169 switch (msr) {
1170 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1171 case MSR_MTRRfix64K_00000:
1172 case MSR_MTRRfix16K_80000:
1173 case MSR_MTRRfix16K_A0000:
1174 case MSR_MTRRfix4K_C0000:
1175 case MSR_MTRRfix4K_C8000:
1176 case MSR_MTRRfix4K_D0000:
1177 case MSR_MTRRfix4K_D8000:
1178 case MSR_MTRRfix4K_E0000:
1179 case MSR_MTRRfix4K_E8000:
1180 case MSR_MTRRfix4K_F0000:
1181 case MSR_MTRRfix4K_F8000:
1182 case MSR_MTRRdefType:
1183 case MSR_IA32_CR_PAT:
1184 return true;
1185 case 0x2f8:
1186 return true;
1187 }
1188 return false;
1189}
1190
d6289b93
MT		 1191static bool valid_pat_type(unsigned t)
1192{
1193 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1194}
1195
1196static bool valid_mtrr_type(unsigned t)
1197{
1198 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1199}
1200
1201static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1202{
1203 int i;
1204
1205 if (!msr_mtrr_valid(msr))
1206 return false;
1207
1208 if (msr == MSR_IA32_CR_PAT) {
1209 for (i = 0; i < 8; i++)
1210 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1211 return false;
1212 return true;
1213 } else if (msr == MSR_MTRRdefType) {
1214 if (data & ~0xcff)
1215 return false;
1216 return valid_mtrr_type(data & 0xff);
1217 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1218 for (i = 0; i < 8 ; i++)
1219 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1220 return false;
1221 return true;
1222 }
1223
1224 /* variable MTRRs */
1225 return valid_mtrr_type(data & 0xff);
1226}
1227
9ba075a6
AK		 1228static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1229{
0bed3b56
SY		 1230 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1231
d6289b93 1232 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1233 return 1;
1234
0bed3b56
SY		 1235 if (msr == MSR_MTRRdefType) {
1236 vcpu->arch.mtrr_state.def_type = data;
1237 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1238 } else if (msr == MSR_MTRRfix64K_00000)
1239 p[0] = data;
1240 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1241 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1242 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1243 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1244 else if (msr == MSR_IA32_CR_PAT)
1245 vcpu->arch.pat = data;
1246 else { /* Variable MTRRs */
1247 int idx, is_mtrr_mask;
1248 u64 *pt;
1249
1250 idx = (msr - 0x200) / 2;
1251 is_mtrr_mask = msr - 0x200 - 2 * idx;
1252 if (!is_mtrr_mask)
1253 pt =
1254 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1255 else
1256 pt =
1257 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1258 *pt = data;
1259 }
1260
1261 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1262 return 0;
1263}
15c4a640 1264
890ca9ae 1265static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1266{
890ca9ae
HY		 1267 u64 mcg_cap = vcpu->arch.mcg_cap;
1268 unsigned bank_num = mcg_cap & 0xff;
1269
15c4a640 1270 switch (msr) {
15c4a640 1271 case MSR_IA32_MCG_STATUS:
890ca9ae 1272 vcpu->arch.mcg_status = data;
15c4a640 1273 break;
c7ac679c 1274 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1275 if (!(mcg_cap & MCG_CTL_P))
1276 return 1;
1277 if (data != 0 && data != ~(u64)0)
1278 return -1;
1279 vcpu->arch.mcg_ctl = data;
1280 break;
1281 default:
1282 if (msr >= MSR_IA32_MC0_CTL &&
1283 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1284 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1285 /* only 0 or all 1s can be written to IA32_MCi_CTL
1286 * some Linux kernels though clear bit 10 in bank 4 to
1287 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1288 * this to avoid an uncatched #GP in the guest
1289 */
890ca9ae 1290 if ((offset & 0x3) == 0 &&
114be429 1291 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1292 return -1;
1293 vcpu->arch.mce_banks[offset] = data;
1294 break;
1295 }
1296 return 1;
1297 }
1298 return 0;
1299}
1300
ffde22ac
ES		 1301static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1302{
1303 struct kvm *kvm = vcpu->kvm;
1304 int lm = is_long_mode(vcpu);
1305 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1306 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1307 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1308 : kvm->arch.xen_hvm_config.blob_size_32;
1309 u32 page_num = data & ~PAGE_MASK;
1310 u64 page_addr = data & PAGE_MASK;
1311 u8 *page;
1312 int r;
1313
1314 r = -E2BIG;
1315 if (page_num >= blob_size)
1316 goto out;
1317 r = -ENOMEM;
1318 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1319 if (!page)
1320 goto out;
1321 r = -EFAULT;
1322 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1323 goto out_free;
1324 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1325 goto out_free;
1326 r = 0;
1327out_free:
1328 kfree(page);
1329out:
1330 return r;
1331}
1332
55cd8e5a
GN		 1333static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1334{
1335 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1336}
1337
1338static bool kvm_hv_msr_partition_wide(u32 msr)
1339{
1340 bool r = false;
1341 switch (msr) {
1342 case HV_X64_MSR_GUEST_OS_ID:
1343 case HV_X64_MSR_HYPERCALL:
1344 r = true;
1345 break;
1346 }
1347
1348 return r;
1349}
1350
1351static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1352{
1353 struct kvm *kvm = vcpu->kvm;
1354
1355 switch (msr) {
1356 case HV_X64_MSR_GUEST_OS_ID:
1357 kvm->arch.hv_guest_os_id = data;
1358 /* setting guest os id to zero disables hypercall page */
1359 if (!kvm->arch.hv_guest_os_id)
1360 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1361 break;
1362 case HV_X64_MSR_HYPERCALL: {
1363 u64 gfn;
1364 unsigned long addr;
1365 u8 instructions[4];
1366
1367 /* if guest os id is not set hypercall should remain disabled */
1368 if (!kvm->arch.hv_guest_os_id)
1369 break;
1370 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1371 kvm->arch.hv_hypercall = data;
1372 break;
1373 }
1374 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1375 addr = gfn_to_hva(kvm, gfn);
1376 if (kvm_is_error_hva(addr))
1377 return 1;
1378 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1379 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1380 if (copy_to_user((void __user *)addr, instructions, 4))
1381 return 1;
1382 kvm->arch.hv_hypercall = data;
1383 break;
1384 }
1385 default:
1386 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1387 "data 0x%llx\n", msr, data);
1388 return 1;
1389 }
1390 return 0;
1391}
1392
1393static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1394{
10388a07
GN		 1395 switch (msr) {
1396 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1397 unsigned long addr;
55cd8e5a 1398
10388a07
GN		 1399 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1400 vcpu->arch.hv_vapic = data;
1401 break;
1402 }
1403 addr = gfn_to_hva(vcpu->kvm, data >>
1404 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1405 if (kvm_is_error_hva(addr))
1406 return 1;
1407 if (clear_user((void __user *)addr, PAGE_SIZE))
1408 return 1;
1409 vcpu->arch.hv_vapic = data;
1410 break;
1411 }
1412 case HV_X64_MSR_EOI:
1413 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1414 case HV_X64_MSR_ICR:
1415 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1416 case HV_X64_MSR_TPR:
1417 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1418 default:
1419 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1420 "data 0x%llx\n", msr, data);
1421 return 1;
1422 }
1423
1424 return 0;
55cd8e5a
GN		 1425}
1426
344d9588
GN		 1427static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1428{
1429 gpa_t gpa = data & ~0x3f;
1430
6adba527
GN		 1431 /* Bits 2:5 are resrved, Should be zero */
1432 if (data & 0x3c)
344d9588
GN		 1433 return 1;
1434
1435 vcpu->arch.apf.msr_val = data;
1436
1437 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1438 kvm_clear_async_pf_completion_queue(vcpu);
1439 kvm_async_pf_hash_reset(vcpu);
1440 return 0;
1441 }
1442
1443 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1444 return 1;
1445
6adba527 1446 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1447 kvm_async_pf_wakeup_all(vcpu);
1448 return 0;
1449}
1450
15c4a640
CO		 1451int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1452{
1453 switch (msr) {
15c4a640 1454 case MSR_EFER:
b69e8cae 1455 return set_efer(vcpu, data);
8f1589d9
AP		 1456 case MSR_K7_HWCR:
1457 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1458 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1459 if (data != 0) {
1460 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1461 data);
1462 return 1;
1463 }
15c4a640 1464 break;
f7c6d140
AP		 1465 case MSR_FAM10H_MMIO_CONF_BASE:
1466 if (data != 0) {
1467 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1468 "0x%llx\n", data);
1469 return 1;
1470 }
15c4a640 1471 break;
c323c0e5 1472 case MSR_AMD64_NB_CFG:
c7ac679c 1473 break;
b5e2fec0
AG		 1474 case MSR_IA32_DEBUGCTLMSR:
1475 if (!data) {
1476 /* We support the non-activated case already */
1477 break;
1478 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1479 /* Values other than LBR and BTF are vendor-specific,
1480 thus reserved and should throw a #GP */
1481 return 1;
1482 }
1483 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1484 __func__, data);
1485 break;
15c4a640
CO		 1486 case MSR_IA32_UCODE_REV:
1487 case MSR_IA32_UCODE_WRITE:
61a6bd67 1488 case MSR_VM_HSAVE_PA:
6098ca93 1489 case MSR_AMD64_PATCH_LOADER:
15c4a640 1490 break;
9ba075a6
AK		 1491 case 0x200 ... 0x2ff:
1492 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1493 case MSR_IA32_APICBASE:
1494 kvm_set_apic_base(vcpu, data);
1495 break;
0105d1a5
GN		 1496 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1497 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1498 case MSR_IA32_MISC_ENABLE:
ad312c7c 1499 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1500 break;
11c6bffa 1501 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1502 case MSR_KVM_WALL_CLOCK:
1503 vcpu->kvm->arch.wall_clock = data;
1504 kvm_write_wall_clock(vcpu->kvm, data);
1505 break;
11c6bffa 1506 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1507 case MSR_KVM_SYSTEM_TIME: {
1508 if (vcpu->arch.time_page) {
1509 kvm_release_page_dirty(vcpu->arch.time_page);
1510 vcpu->arch.time_page = NULL;
1511 }
1512
1513 vcpu->arch.time = data;
c285545f 1514 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1515
1516 /* we verify if the enable bit is set... */
1517 if (!(data & 1))
1518 break;
1519
1520 /* ...but clean it before doing the actual write */
1521 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1522
18068523
GOC		 1523 vcpu->arch.time_page =
1524 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1525
1526 if (is_error_page(vcpu->arch.time_page)) {
1527 kvm_release_page_clean(vcpu->arch.time_page);
1528 vcpu->arch.time_page = NULL;
1529 }
18068523
GOC		 1530 break;
1531 }
344d9588
GN		 1532 case MSR_KVM_ASYNC_PF_EN:
1533 if (kvm_pv_enable_async_pf(vcpu, data))
1534 return 1;
1535 break;
890ca9ae
HY		 1536 case MSR_IA32_MCG_CTL:
1537 case MSR_IA32_MCG_STATUS:
1538 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1539 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1540
1541 /* Performance counters are not protected by a CPUID bit,
1542 * so we should check all of them in the generic path for the sake of
1543 * cross vendor migration.
1544 * Writing a zero into the event select MSRs disables them,
1545 * which we perfectly emulate ;-). Any other value should be at least
1546 * reported, some guests depend on them.
1547 */
1548 case MSR_P6_EVNTSEL0:
1549 case MSR_P6_EVNTSEL1:
1550 case MSR_K7_EVNTSEL0:
1551 case MSR_K7_EVNTSEL1:
1552 case MSR_K7_EVNTSEL2:
1553 case MSR_K7_EVNTSEL3:
1554 if (data != 0)
1555 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1556 "0x%x data 0x%llx\n", msr, data);
1557 break;
1558 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1559 * so we ignore writes to make it happy.
1560 */
1561 case MSR_P6_PERFCTR0:
1562 case MSR_P6_PERFCTR1:
1563 case MSR_K7_PERFCTR0:
1564 case MSR_K7_PERFCTR1:
1565 case MSR_K7_PERFCTR2:
1566 case MSR_K7_PERFCTR3:
1567 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1568 "0x%x data 0x%llx\n", msr, data);
1569 break;
84e0cefa
JS		 1570 case MSR_K7_CLK_CTL:
1571 /*
1572 * Ignore all writes to this no longer documented MSR.
1573 * Writes are only relevant for old K7 processors,
1574 * all pre-dating SVM, but a recommended workaround from
1575 * AMD for these chips. It is possible to speicify the
1576 * affected processor models on the command line, hence
1577 * the need to ignore the workaround.
1578 */
1579 break;
55cd8e5a
GN		 1580 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1581 if (kvm_hv_msr_partition_wide(msr)) {
1582 int r;
1583 mutex_lock(&vcpu->kvm->lock);
1584 r = set_msr_hyperv_pw(vcpu, msr, data);
1585 mutex_unlock(&vcpu->kvm->lock);
1586 return r;
1587 } else
1588 return set_msr_hyperv(vcpu, msr, data);
1589 break;
15c4a640 1590 default:
ffde22ac
ES		 1591 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1592 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1593 if (!ignore_msrs) {
1594 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1595 msr, data);
1596 return 1;
1597 } else {
1598 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1599 msr, data);
1600 break;
1601 }
15c4a640
CO		 1602 }
1603 return 0;
1604}
1605EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1606
1607
1608/*
1609 * Reads an msr value (of 'msr_index') into 'pdata'.
1610 * Returns 0 on success, non-0 otherwise.
1611 * Assumes vcpu_load() was already called.
1612 */
1613int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1614{
1615 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1616}
1617
9ba075a6
AK		 1618static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1619{
0bed3b56
SY		 1620 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1621
9ba075a6
AK		 1622 if (!msr_mtrr_valid(msr))
1623 return 1;
1624
0bed3b56
SY		 1625 if (msr == MSR_MTRRdefType)
1626 *pdata = vcpu->arch.mtrr_state.def_type +
1627 (vcpu->arch.mtrr_state.enabled << 10);
1628 else if (msr == MSR_MTRRfix64K_00000)
1629 *pdata = p[0];
1630 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1631 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1632 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1633 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1634 else if (msr == MSR_IA32_CR_PAT)
1635 *pdata = vcpu->arch.pat;
1636 else { /* Variable MTRRs */
1637 int idx, is_mtrr_mask;
1638 u64 *pt;
1639
1640 idx = (msr - 0x200) / 2;
1641 is_mtrr_mask = msr - 0x200 - 2 * idx;
1642 if (!is_mtrr_mask)
1643 pt =
1644 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1645 else
1646 pt =
1647 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1648 *pdata = *pt;
1649 }
1650
9ba075a6
AK		 1651 return 0;
1652}
1653
890ca9ae 1654static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1655{
1656 u64 data;
890ca9ae
HY		 1657 u64 mcg_cap = vcpu->arch.mcg_cap;
1658 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1659
1660 switch (msr) {
15c4a640
CO		 1661 case MSR_IA32_P5_MC_ADDR:
1662 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1663 data = 0;
1664 break;
15c4a640 1665 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1666 data = vcpu->arch.mcg_cap;
1667 break;
c7ac679c 1668 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1669 if (!(mcg_cap & MCG_CTL_P))
1670 return 1;
1671 data = vcpu->arch.mcg_ctl;
1672 break;
1673 case MSR_IA32_MCG_STATUS:
1674 data = vcpu->arch.mcg_status;
1675 break;
1676 default:
1677 if (msr >= MSR_IA32_MC0_CTL &&
1678 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1679 u32 offset = msr - MSR_IA32_MC0_CTL;
1680 data = vcpu->arch.mce_banks[offset];
1681 break;
1682 }
1683 return 1;
1684 }
1685 *pdata = data;
1686 return 0;
1687}
1688
55cd8e5a
GN		 1689static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1690{
1691 u64 data = 0;
1692 struct kvm *kvm = vcpu->kvm;
1693
1694 switch (msr) {
1695 case HV_X64_MSR_GUEST_OS_ID:
1696 data = kvm->arch.hv_guest_os_id;
1697 break;
1698 case HV_X64_MSR_HYPERCALL:
1699 data = kvm->arch.hv_hypercall;
1700 break;
1701 default:
1702 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1703 return 1;
1704 }
1705
1706 *pdata = data;
1707 return 0;
1708}
1709
1710static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1711{
1712 u64 data = 0;
1713
1714 switch (msr) {
1715 case HV_X64_MSR_VP_INDEX: {
1716 int r;
1717 struct kvm_vcpu *v;
1718 kvm_for_each_vcpu(r, v, vcpu->kvm)
1719 if (v == vcpu)
1720 data = r;
1721 break;
1722 }
10388a07
GN		 1723 case HV_X64_MSR_EOI:
1724 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1725 case HV_X64_MSR_ICR:
1726 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1727 case HV_X64_MSR_TPR:
1728 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1729 default:
1730 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1731 return 1;
1732 }
1733 *pdata = data;
1734 return 0;
1735}
1736
890ca9ae
HY		 1737int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1738{
1739 u64 data;
1740
1741 switch (msr) {
890ca9ae 1742 case MSR_IA32_PLATFORM_ID:
15c4a640 1743 case MSR_IA32_UCODE_REV:
15c4a640 1744 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1745 case MSR_IA32_DEBUGCTLMSR:
1746 case MSR_IA32_LASTBRANCHFROMIP:
1747 case MSR_IA32_LASTBRANCHTOIP:
1748 case MSR_IA32_LASTINTFROMIP:
1749 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1750 case MSR_K8_SYSCFG:
1751 case MSR_K7_HWCR:
61a6bd67 1752 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1753 case MSR_P6_PERFCTR0:
1754 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1755 case MSR_P6_EVNTSEL0:
1756 case MSR_P6_EVNTSEL1:
9e699624 1757 case MSR_K7_EVNTSEL0:
1f3ee616 1758 case MSR_K7_PERFCTR0:
1fdbd48c 1759 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1760 case MSR_AMD64_NB_CFG:
f7c6d140 1761 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1762 data = 0;
1763 break;
9ba075a6
AK		 1764 case MSR_MTRRcap:
1765 data = 0x500 | KVM_NR_VAR_MTRR;
1766 break;
1767 case 0x200 ... 0x2ff:
1768 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1769 case 0xcd: /* fsb frequency */
1770 data = 3;
1771 break;
7b914098
JS		 1772 /*
1773 * MSR_EBC_FREQUENCY_ID
1774 * Conservative value valid for even the basic CPU models.
1775 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1776 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1777 * and 266MHz for model 3, or 4. Set Core Clock
1778 * Frequency to System Bus Frequency Ratio to 1 (bits
1779 * 31:24) even though these are only valid for CPU
1780 * models > 2, however guests may end up dividing or
1781 * multiplying by zero otherwise.
1782 */
1783 case MSR_EBC_FREQUENCY_ID:
1784 data = 1 << 24;
1785 break;
15c4a640
CO		 1786 case MSR_IA32_APICBASE:
1787 data = kvm_get_apic_base(vcpu);
1788 break;
0105d1a5
GN		 1789 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1790 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1791 break;
15c4a640 1792 case MSR_IA32_MISC_ENABLE:
ad312c7c 1793 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1794 break;
847f0ad8
AG		 1795 case MSR_IA32_PERF_STATUS:
1796 /* TSC increment by tick */
1797 data = 1000ULL;
1798 /* CPU multiplier */
1799 data |= (((uint64_t)4ULL) << 40);
1800 break;
15c4a640 1801 case MSR_EFER:
f6801dff 1802 data = vcpu->arch.efer;
15c4a640 1803 break;
18068523 1804 case MSR_KVM_WALL_CLOCK:
11c6bffa 1805 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1806 data = vcpu->kvm->arch.wall_clock;
1807 break;
1808 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1809 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1810 data = vcpu->arch.time;
1811 break;
344d9588
GN		 1812 case MSR_KVM_ASYNC_PF_EN:
1813 data = vcpu->arch.apf.msr_val;
1814 break;
890ca9ae
HY		 1815 case MSR_IA32_P5_MC_ADDR:
1816 case MSR_IA32_P5_MC_TYPE:
1817 case MSR_IA32_MCG_CAP:
1818 case MSR_IA32_MCG_CTL:
1819 case MSR_IA32_MCG_STATUS:
1820 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1821 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1822 case MSR_K7_CLK_CTL:
1823 /*
1824 * Provide expected ramp-up count for K7. All other
1825 * are set to zero, indicating minimum divisors for
1826 * every field.
1827 *
1828 * This prevents guest kernels on AMD host with CPU
1829 * type 6, model 8 and higher from exploding due to
1830 * the rdmsr failing.
1831 */
1832 data = 0x20000000;
1833 break;
55cd8e5a
GN		 1834 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1835 if (kvm_hv_msr_partition_wide(msr)) {
1836 int r;
1837 mutex_lock(&vcpu->kvm->lock);
1838 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1839 mutex_unlock(&vcpu->kvm->lock);
1840 return r;
1841 } else
1842 return get_msr_hyperv(vcpu, msr, pdata);
1843 break;
15c4a640 1844 default:
ed85c068
AP		 1845 if (!ignore_msrs) {
1846 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1847 return 1;
1848 } else {
1849 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1850 data = 0;
1851 }
1852 break;
15c4a640
CO		 1853 }
1854 *pdata = data;
1855 return 0;
1856}
1857EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1858
313a3dc7
CO		 1859/*
1860 * Read or write a bunch of msrs. All parameters are kernel addresses.
1861 *
1862 * @return number of msrs set successfully.
1863 */
1864static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1865 struct kvm_msr_entry *entries,
1866 int (*do_msr)(struct kvm_vcpu *vcpu,
1867 unsigned index, u64 *data))
1868{
f656ce01 1869 int i, idx;
313a3dc7 1870
f656ce01 1871 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1872 for (i = 0; i < msrs->nmsrs; ++i)
1873 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1874 break;
f656ce01 1875 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1876
313a3dc7
CO		 1877 return i;
1878}
1879
1880/*
1881 * Read or write a bunch of msrs. Parameters are user addresses.
1882 *
1883 * @return number of msrs set successfully.
1884 */
1885static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1886 int (*do_msr)(struct kvm_vcpu *vcpu,
1887 unsigned index, u64 *data),
1888 int writeback)
1889{
1890 struct kvm_msrs msrs;
1891 struct kvm_msr_entry *entries;
1892 int r, n;
1893 unsigned size;
1894
1895 r = -EFAULT;
1896 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1897 goto out;
1898
1899 r = -E2BIG;
1900 if (msrs.nmsrs >= MAX_IO_MSRS)
1901 goto out;
1902
1903 r = -ENOMEM;
1904 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1905 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1906 if (!entries)
1907 goto out;
1908
1909 r = -EFAULT;
1910 if (copy_from_user(entries, user_msrs->entries, size))
1911 goto out_free;
1912
1913 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1914 if (r < 0)
1915 goto out_free;
1916
1917 r = -EFAULT;
1918 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1919 goto out_free;
1920
1921 r = n;
1922
1923out_free:
7a73c028 1924 kfree(entries);
313a3dc7
CO		 1925out:
1926 return r;
1927}
1928
018d00d2
ZX		 1929int kvm_dev_ioctl_check_extension(long ext)
1930{
1931 int r;
1932
1933 switch (ext) {
1934 case KVM_CAP_IRQCHIP:
1935 case KVM_CAP_HLT:
1936 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1937 case KVM_CAP_SET_TSS_ADDR:
07716717 1938 case KVM_CAP_EXT_CPUID:
c8076604 1939 case KVM_CAP_CLOCKSOURCE:
7837699f 1940 case KVM_CAP_PIT:
a28e4f5a 1941 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1942 case KVM_CAP_MP_STATE:
ed848624 1943 case KVM_CAP_SYNC_MMU:
a355c85c 1944 case KVM_CAP_USER_NMI:
52d939a0 1945 case KVM_CAP_REINJECT_CONTROL:
4925663a 1946 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1947 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1948 case KVM_CAP_IRQFD:
d34e6b17 1949 case KVM_CAP_IOEVENTFD:
c5ff41ce 1950 case KVM_CAP_PIT2:
e9f42757 1951 case KVM_CAP_PIT_STATE2:
b927a3ce 1952 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1953 case KVM_CAP_XEN_HVM:
afbcf7ab 1954 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1955 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1956 case KVM_CAP_HYPERV:
10388a07 1957 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1958 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1959 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1960 case KVM_CAP_DEBUGREGS:
d2be1651 1961 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 1962 case KVM_CAP_XSAVE:
344d9588 1963 case KVM_CAP_ASYNC_PF:
018d00d2
ZX		 1964 r = 1;
1965 break;
542472b5
LV		 1966 case KVM_CAP_COALESCED_MMIO:
1967 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1968 break;
774ead3a
AK		 1969 case KVM_CAP_VAPIC:
1970 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1971 break;
f725230a
AK		 1972 case KVM_CAP_NR_VCPUS:
1973 r = KVM_MAX_VCPUS;
1974 break;
a988b910
AK		 1975 case KVM_CAP_NR_MEMSLOTS:
1976 r = KVM_MEMORY_SLOTS;
1977 break;
a68a6a72
MT		 1978 case KVM_CAP_PV_MMU: /* obsolete */
1979 r = 0;
2f333bcb 1980 break;
62c476c7 1981 case KVM_CAP_IOMMU:
19de40a8 1982 r = iommu_found();
62c476c7 1983 break;
890ca9ae
HY		 1984 case KVM_CAP_MCE:
1985 r = KVM_MAX_MCE_BANKS;
1986 break;
2d5b5a66
SY		 1987 case KVM_CAP_XCRS:
1988 r = cpu_has_xsave;
1989 break;
018d00d2
ZX		 1990 default:
1991 r = 0;
1992 break;
1993 }
1994 return r;
1995
1996}
1997
043405e1
CO		 1998long kvm_arch_dev_ioctl(struct file *filp,
1999 unsigned int ioctl, unsigned long arg)
2000{
2001 void __user *argp = (void __user *)arg;
2002 long r;
2003
2004 switch (ioctl) {
2005 case KVM_GET_MSR_INDEX_LIST: {
2006 struct kvm_msr_list __user *user_msr_list = argp;
2007 struct kvm_msr_list msr_list;
2008 unsigned n;
2009
2010 r = -EFAULT;
2011 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2012 goto out;
2013 n = msr_list.nmsrs;
2014 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2015 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2016 goto out;
2017 r = -E2BIG;
e125e7b6 2018 if (n < msr_list.nmsrs)
043405e1
CO		 2019 goto out;
2020 r = -EFAULT;
2021 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2022 num_msrs_to_save * sizeof(u32)))
2023 goto out;
e125e7b6 2024 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2025 &emulated_msrs,
2026 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2027 goto out;
2028 r = 0;
2029 break;
2030 }
674eea0f
AK		 2031 case KVM_GET_SUPPORTED_CPUID: {
2032 struct kvm_cpuid2 __user *cpuid_arg = argp;
2033 struct kvm_cpuid2 cpuid;
2034
2035 r = -EFAULT;
2036 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2037 goto out;
2038 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2039 cpuid_arg->entries);
674eea0f
AK		 2040 if (r)
2041 goto out;
2042
2043 r = -EFAULT;
2044 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2045 goto out;
2046 r = 0;
2047 break;
2048 }
890ca9ae
HY		 2049 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2050 u64 mce_cap;
2051
2052 mce_cap = KVM_MCE_CAP_SUPPORTED;
2053 r = -EFAULT;
2054 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2055 goto out;
2056 r = 0;
2057 break;
2058 }
043405e1
CO		 2059 default:
2060 r = -EINVAL;
2061 }
2062out:
2063 return r;
2064}
2065
f5f48ee1
SY		 2066static void wbinvd_ipi(void *garbage)
2067{
2068 wbinvd();
2069}
2070
2071static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2072{
2073 return vcpu->kvm->arch.iommu_domain &&
2074 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2075}
2076
313a3dc7
CO		 2077void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2078{
f5f48ee1
SY		 2079 /* Address WBINVD may be executed by guest */
2080 if (need_emulate_wbinvd(vcpu)) {
2081 if (kvm_x86_ops->has_wbinvd_exit())
2082 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2083 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2084 smp_call_function_single(vcpu->cpu,
2085 wbinvd_ipi, NULL, 1);
2086 }
2087
313a3dc7 2088 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2089 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa
ZA		 2090 /* Make sure TSC doesn't go backwards */
2091 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2092 native_read_tsc() - vcpu->arch.last_host_tsc;
2093 if (tsc_delta < 0)
2094 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2095 if (check_tsc_unstable()) {
e48672fa 2096 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
c285545f
ZA		 2097 vcpu->arch.tsc_catchup = 1;
2098 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2099 }
2100 if (vcpu->cpu != cpu)
2101 kvm_migrate_timers(vcpu);
e48672fa 2102 vcpu->cpu = cpu;
6b7d7e76 2103 }
313a3dc7
CO		 2104}
2105
2106void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2107{
02daab21 2108 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2109 kvm_put_guest_fpu(vcpu);
e48672fa 2110 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2111}
2112
07716717 2113static int is_efer_nx(void)
313a3dc7 2114{
e286e86e 2115 unsigned long long efer = 0;
313a3dc7 2116
e286e86e 2117 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 2118 return efer & EFER_NX;
2119}
2120
2121static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2122{
2123 int i;
2124 struct kvm_cpuid_entry2 *e, *entry;
2125
313a3dc7 2126 entry = NULL;
ad312c7c
ZX		 2127 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2128 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 2129 if (e->function == 0x80000001) {
2130 entry = e;
2131 break;
2132 }
2133 }
07716717 2134 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 2135 entry->edx &= ~(1 << 20);
2136 printk(KERN_INFO "kvm: guest NX capability removed\n");
2137 }
2138}
2139
07716717 2140/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 2141static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2142 struct kvm_cpuid *cpuid,
2143 struct kvm_cpuid_entry __user *entries)
07716717
DK		 2144{
2145 int r, i;
2146 struct kvm_cpuid_entry *cpuid_entries;
2147
2148 r = -E2BIG;
2149 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2150 goto out;
2151 r = -ENOMEM;
2152 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2153 if (!cpuid_entries)
2154 goto out;
2155 r = -EFAULT;
2156 if (copy_from_user(cpuid_entries, entries,
2157 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2158 goto out_free;
2159 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 2160 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2161 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2162 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2163 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2164 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2165 vcpu->arch.cpuid_entries[i].index = 0;
2166 vcpu->arch.cpuid_entries[i].flags = 0;
2167 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2168 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2169 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2170 }
2171 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2172 cpuid_fix_nx_cap(vcpu);
2173 r = 0;
fc61b800 2174 kvm_apic_set_version(vcpu);
0e851880 2175 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2176 update_cpuid(vcpu);
07716717
DK		 2177
2178out_free:
2179 vfree(cpuid_entries);
2180out:
2181 return r;
2182}
2183
2184static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2185 struct kvm_cpuid2 *cpuid,
2186 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2187{
2188 int r;
2189
2190 r = -E2BIG;
2191 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2192 goto out;
2193 r = -EFAULT;
ad312c7c 2194 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2195 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2196 goto out;
ad312c7c 2197 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2198 kvm_apic_set_version(vcpu);
0e851880 2199 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2200 update_cpuid(vcpu);
313a3dc7
CO		 2201 return 0;
2202
2203out:
2204 return r;
2205}
2206
07716717 2207static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2208 struct kvm_cpuid2 *cpuid,
2209 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2210{
2211 int r;
2212
2213 r = -E2BIG;
ad312c7c 2214 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2215 goto out;
2216 r = -EFAULT;
ad312c7c 2217 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2218 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2219 goto out;
2220 return 0;
2221
2222out:
ad312c7c 2223 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2224 return r;
2225}
2226
945ee35e
AK		 2227static void cpuid_mask(u32 *word, int wordnum)
2228{
2229 *word &= boot_cpu_data.x86_capability[wordnum];
2230}
2231
07716717 2232static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2233 u32 index)
07716717
DK		 2234{
2235 entry->function = function;
2236 entry->index = index;
2237 cpuid_count(entry->function, entry->index,
19355475 2238 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2239 entry->flags = 0;
2240}
2241
7faa4ee1
AK		 2242#define F(x) bit(X86_FEATURE_##x)
2243
07716717
DK		 2244static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2245 u32 index, int *nent, int maxnent)
2246{
7faa4ee1 2247 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2248#ifdef CONFIG_X86_64
17cc3935
SY		 2249 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2250 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2251 unsigned f_lm = F(LM);
2252#else
17cc3935 2253 unsigned f_gbpages = 0;
7faa4ee1 2254 unsigned f_lm = 0;
07716717 2255#endif
4e47c7a6 2256 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2257
2258 /* cpuid 1.edx */
2259 const u32 kvm_supported_word0_x86_features =
2260 F(FPU) | F(VME) | F(DE) | F(PSE) |
2261 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2262 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2263 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2264 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2265 0 /* Reserved, DS, ACPI */ | F(MMX) |
2266 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2267 0 /* HTT, TM, Reserved, PBE */;
2268 /* cpuid 0x80000001.edx */
2269 const u32 kvm_supported_word1_x86_features =
2270 F(FPU) | F(VME) | F(DE) | F(PSE) |
2271 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2272 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2273 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2274 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2275 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2276 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2277 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2278 /* cpuid 1.ecx */
2279 const u32 kvm_supported_word4_x86_features =
6c3f6041 2280 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2281 0 /* DS-CPL, VMX, SMX, EST */ |
2282 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2283 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2284 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2285 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6d886fd0
AP		 2286 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
2287 F(F16C);
7faa4ee1 2288 /* cpuid 0x80000001.ecx */
07716717 2289 const u32 kvm_supported_word6_x86_features =
4c62a2dc 2290 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
7faa4ee1 2291 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
7ef8aa72 2292 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) |
6d886fd0 2293 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM);
07716717 2294
19355475 2295 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2296 get_cpu();
2297 do_cpuid_1_ent(entry, function, index);
2298 ++*nent;
2299
2300 switch (function) {
2301 case 0:
2acf923e 2302 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2303 break;
2304 case 1:
2305 entry->edx &= kvm_supported_word0_x86_features;
945ee35e 2306 cpuid_mask(&entry->edx, 0);
7faa4ee1 2307 entry->ecx &= kvm_supported_word4_x86_features;
945ee35e 2308 cpuid_mask(&entry->ecx, 4);
0d1de2d9
GN		 2309 /* we support x2apic emulation even if host does not support
2310 * it since we emulate x2apic in software */
2311 entry->ecx |= F(X2APIC);
07716717
DK		 2312 break;
2313 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2314 * may return different values. This forces us to get_cpu() before
2315 * issuing the first command, and also to emulate this annoying behavior
2316 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2317 case 2: {
2318 int t, times = entry->eax & 0xff;
2319
2320 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2321 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2322 for (t = 1; t < times && *nent < maxnent; ++t) {
2323 do_cpuid_1_ent(&entry[t], function, 0);
2324 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2325 ++*nent;
2326 }
2327 break;
2328 }
2329 /* function 4 and 0xb have additional index. */
2330 case 4: {
14af3f3c 2331 int i, cache_type;
07716717
DK		 2332
2333 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2334 /* read more entries until cache_type is zero */
14af3f3c
HH		 2335 for (i = 1; *nent < maxnent; ++i) {
2336 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2337 if (!cache_type)
2338 break;
14af3f3c
HH		 2339 do_cpuid_1_ent(&entry[i], function, i);
2340 entry[i].flags |=
07716717
DK		 2341 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2342 ++*nent;
2343 }
2344 break;
2345 }
2346 case 0xb: {
14af3f3c 2347 int i, level_type;
07716717
DK		 2348
2349 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2350 /* read more entries until level_type is zero */
14af3f3c 2351 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2352 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2353 if (!level_type)
2354 break;
14af3f3c
HH		 2355 do_cpuid_1_ent(&entry[i], function, i);
2356 entry[i].flags |=
07716717
DK		 2357 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2358 ++*nent;
2359 }
2360 break;
2361 }
2acf923e
DC		 2362 case 0xd: {
2363 int i;
2364
2365 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2366 for (i = 1; *nent < maxnent; ++i) {
2367 if (entry[i - 1].eax == 0 && i != 2)
2368 break;
2369 do_cpuid_1_ent(&entry[i], function, i);
2370 entry[i].flags |=
2371 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2372 ++*nent;
2373 }
2374 break;
2375 }
84478c82
GC		 2376 case KVM_CPUID_SIGNATURE: {
2377 char signature[12] = "KVMKVMKVM\0\0";
2378 u32 *sigptr = (u32 *)signature;
2379 entry->eax = 0;
2380 entry->ebx = sigptr[0];
2381 entry->ecx = sigptr[1];
2382 entry->edx = sigptr[2];
2383 break;
2384 }
2385 case KVM_CPUID_FEATURES:
2386 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2387 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64
GC		 2388 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2389 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2390 entry->ebx = 0;
2391 entry->ecx = 0;
2392 entry->edx = 0;
2393 break;
07716717
DK		 2394 case 0x80000000:
2395 entry->eax = min(entry->eax, 0x8000001a);
2396 break;
2397 case 0x80000001:
2398 entry->edx &= kvm_supported_word1_x86_features;
945ee35e 2399 cpuid_mask(&entry->edx, 1);
07716717 2400 entry->ecx &= kvm_supported_word6_x86_features;
945ee35e 2401 cpuid_mask(&entry->ecx, 6);
07716717
DK		 2402 break;
2403 }
d4330ef2
JR		 2404
2405 kvm_x86_ops->set_supported_cpuid(function, entry);
2406
07716717
DK		 2407 put_cpu();
2408}
2409
7faa4ee1
AK		 2410#undef F
2411
674eea0f 2412static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2413 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2414{
2415 struct kvm_cpuid_entry2 *cpuid_entries;
2416 int limit, nent = 0, r = -E2BIG;
2417 u32 func;
2418
2419 if (cpuid->nent < 1)
2420 goto out;
6a544355
AK		 2421 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2422 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2423 r = -ENOMEM;
2424 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2425 if (!cpuid_entries)
2426 goto out;
2427
2428 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2429 limit = cpuid_entries[0].eax;
2430 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2431 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2432 &nent, cpuid->nent);
07716717
DK		 2433 r = -E2BIG;
2434 if (nent >= cpuid->nent)
2435 goto out_free;
2436
2437 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2438 limit = cpuid_entries[nent - 1].eax;
2439 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2440 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2441 &nent, cpuid->nent);
84478c82
GC		 2442
2443
2444
2445 r = -E2BIG;
2446 if (nent >= cpuid->nent)
2447 goto out_free;
2448
2449 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2450 cpuid->nent);
2451
2452 r = -E2BIG;
2453 if (nent >= cpuid->nent)
2454 goto out_free;
2455
2456 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2457 cpuid->nent);
2458
cb007648
MM		 2459 r = -E2BIG;
2460 if (nent >= cpuid->nent)
2461 goto out_free;
2462
07716717
DK		 2463 r = -EFAULT;
2464 if (copy_to_user(entries, cpuid_entries,
19355475 2465 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2466 goto out_free;
2467 cpuid->nent = nent;
2468 r = 0;
2469
2470out_free:
2471 vfree(cpuid_entries);
2472out:
2473 return r;
2474}
2475
313a3dc7
CO		 2476static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2477 struct kvm_lapic_state *s)
2478{
ad312c7c 2479 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2480
2481 return 0;
2482}
2483
2484static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2485 struct kvm_lapic_state *s)
2486{
ad312c7c 2487 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2488 kvm_apic_post_state_restore(vcpu);
cb142eb7 2489 update_cr8_intercept(vcpu);
313a3dc7
CO		 2490
2491 return 0;
2492}
2493
f77bc6a4
ZX		 2494static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2495 struct kvm_interrupt *irq)
2496{
2497 if (irq->irq < 0 || irq->irq >= 256)
2498 return -EINVAL;
2499 if (irqchip_in_kernel(vcpu->kvm))
2500 return -ENXIO;
f77bc6a4 2501
66fd3f7f 2502 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2503 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2504
f77bc6a4
ZX		 2505 return 0;
2506}
2507
c4abb7c9
JK		 2508static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2509{
c4abb7c9 2510 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2511
2512 return 0;
2513}
2514
b209749f
AK		 2515static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2516 struct kvm_tpr_access_ctl *tac)
2517{
2518 if (tac->flags)
2519 return -EINVAL;
2520 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2521 return 0;
2522}
2523
890ca9ae
HY		 2524static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2525 u64 mcg_cap)
2526{
2527 int r;
2528 unsigned bank_num = mcg_cap & 0xff, bank;
2529
2530 r = -EINVAL;
a9e38c3e 2531 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2532 goto out;
2533 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2534 goto out;
2535 r = 0;
2536 vcpu->arch.mcg_cap = mcg_cap;
2537 /* Init IA32_MCG_CTL to all 1s */
2538 if (mcg_cap & MCG_CTL_P)
2539 vcpu->arch.mcg_ctl = ~(u64)0;
2540 /* Init IA32_MCi_CTL to all 1s */
2541 for (bank = 0; bank < bank_num; bank++)
2542 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2543out:
2544 return r;
2545}
2546
2547static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2548 struct kvm_x86_mce *mce)
2549{
2550 u64 mcg_cap = vcpu->arch.mcg_cap;
2551 unsigned bank_num = mcg_cap & 0xff;
2552 u64 *banks = vcpu->arch.mce_banks;
2553
2554 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2555 return -EINVAL;
2556 /*
2557 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2558 * reporting is disabled
2559 */
2560 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2561 vcpu->arch.mcg_ctl != ~(u64)0)
2562 return 0;
2563 banks += 4 * mce->bank;
2564 /*
2565 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2566 * reporting is disabled for the bank
2567 */
2568 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2569 return 0;
2570 if (mce->status & MCI_STATUS_UC) {
2571 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2572 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2573 printk(KERN_DEBUG "kvm: set_mce: "
2574 "injects mce exception while "
2575 "previous one is in progress!\n");
a8eeb04a 2576 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2577 return 0;
2578 }
2579 if (banks[1] & MCI_STATUS_VAL)
2580 mce->status |= MCI_STATUS_OVER;
2581 banks[2] = mce->addr;
2582 banks[3] = mce->misc;
2583 vcpu->arch.mcg_status = mce->mcg_status;
2584 banks[1] = mce->status;
2585 kvm_queue_exception(vcpu, MC_VECTOR);
2586 } else if (!(banks[1] & MCI_STATUS_VAL)
2587 || !(banks[1] & MCI_STATUS_UC)) {
2588 if (banks[1] & MCI_STATUS_VAL)
2589 mce->status |= MCI_STATUS_OVER;
2590 banks[2] = mce->addr;
2591 banks[3] = mce->misc;
2592 banks[1] = mce->status;
2593 } else
2594 banks[1] |= MCI_STATUS_OVER;
2595 return 0;
2596}
2597
3cfc3092
JK		 2598static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2599 struct kvm_vcpu_events *events)
2600{
03b82a30
JK		 2601 events->exception.injected =
2602 vcpu->arch.exception.pending &&
2603 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2604 events->exception.nr = vcpu->arch.exception.nr;
2605 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2606 events->exception.pad = 0;
3cfc3092
JK		 2607 events->exception.error_code = vcpu->arch.exception.error_code;
2608
03b82a30
JK		 2609 events->interrupt.injected =
2610 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2611 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2612 events->interrupt.soft = 0;
48005f64
JK		 2613 events->interrupt.shadow =
2614 kvm_x86_ops->get_interrupt_shadow(vcpu,
2615 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2616
2617 events->nmi.injected = vcpu->arch.nmi_injected;
2618 events->nmi.pending = vcpu->arch.nmi_pending;
2619 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2620 events->nmi.pad = 0;
3cfc3092
JK		 2621
2622 events->sipi_vector = vcpu->arch.sipi_vector;
2623
dab4b911 2624 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2625 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2626 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2627 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2628}
2629
2630static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2631 struct kvm_vcpu_events *events)
2632{
dab4b911 2633 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2634 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2635 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2636 return -EINVAL;
2637
3cfc3092
JK		 2638 vcpu->arch.exception.pending = events->exception.injected;
2639 vcpu->arch.exception.nr = events->exception.nr;
2640 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2641 vcpu->arch.exception.error_code = events->exception.error_code;
2642
2643 vcpu->arch.interrupt.pending = events->interrupt.injected;
2644 vcpu->arch.interrupt.nr = events->interrupt.nr;
2645 vcpu->arch.interrupt.soft = events->interrupt.soft;
2646 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2647 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2648 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2649 kvm_x86_ops->set_interrupt_shadow(vcpu,
2650 events->interrupt.shadow);
3cfc3092
JK		 2651
2652 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2653 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2654 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2655 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2656
dab4b911
JK		 2657 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2658 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2659
3842d135
AK		 2660 kvm_make_request(KVM_REQ_EVENT, vcpu);
2661
3cfc3092
JK		 2662 return 0;
2663}
2664
a1efbe77
JK		 2665static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2666 struct kvm_debugregs *dbgregs)
2667{
a1efbe77
JK		 2668 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2669 dbgregs->dr6 = vcpu->arch.dr6;
2670 dbgregs->dr7 = vcpu->arch.dr7;
2671 dbgregs->flags = 0;
97e69aa6 2672 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2673}
2674
2675static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2676 struct kvm_debugregs *dbgregs)
2677{
2678 if (dbgregs->flags)
2679 return -EINVAL;
2680
a1efbe77
JK		 2681 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2682 vcpu->arch.dr6 = dbgregs->dr6;
2683 vcpu->arch.dr7 = dbgregs->dr7;
2684
a1efbe77
JK		 2685 return 0;
2686}
2687
2d5b5a66
SY		 2688static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2689 struct kvm_xsave *guest_xsave)
2690{
2691 if (cpu_has_xsave)
2692 memcpy(guest_xsave->region,
2693 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2694 xstate_size);
2d5b5a66
SY		 2695 else {
2696 memcpy(guest_xsave->region,
2697 &vcpu->arch.guest_fpu.state->fxsave,
2698 sizeof(struct i387_fxsave_struct));
2699 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2700 XSTATE_FPSSE;
2701 }
2702}
2703
2704static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2705 struct kvm_xsave *guest_xsave)
2706{
2707 u64 xstate_bv =
2708 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2709
2710 if (cpu_has_xsave)
2711 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2712 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2713 else {
2714 if (xstate_bv & ~XSTATE_FPSSE)
2715 return -EINVAL;
2716 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2717 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2718 }
2719 return 0;
2720}
2721
2722static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2723 struct kvm_xcrs *guest_xcrs)
2724{
2725 if (!cpu_has_xsave) {
2726 guest_xcrs->nr_xcrs = 0;
2727 return;
2728 }
2729
2730 guest_xcrs->nr_xcrs = 1;
2731 guest_xcrs->flags = 0;
2732 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2733 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2734}
2735
2736static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2737 struct kvm_xcrs *guest_xcrs)
2738{
2739 int i, r = 0;
2740
2741 if (!cpu_has_xsave)
2742 return -EINVAL;
2743
2744 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2745 return -EINVAL;
2746
2747 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2748 /* Only support XCR0 currently */
2749 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2750 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2751 guest_xcrs->xcrs[0].value);
2752 break;
2753 }
2754 if (r)
2755 r = -EINVAL;
2756 return r;
2757}
2758
313a3dc7
CO		 2759long kvm_arch_vcpu_ioctl(struct file *filp,
2760 unsigned int ioctl, unsigned long arg)
2761{
2762 struct kvm_vcpu *vcpu = filp->private_data;
2763 void __user *argp = (void __user *)arg;
2764 int r;
d1ac91d8
AK		 2765 union {
2766 struct kvm_lapic_state *lapic;
2767 struct kvm_xsave *xsave;
2768 struct kvm_xcrs *xcrs;
2769 void *buffer;
2770 } u;
2771
2772 u.buffer = NULL;
313a3dc7
CO		 2773 switch (ioctl) {
2774 case KVM_GET_LAPIC: {
2204ae3c
MT		 2775 r = -EINVAL;
2776 if (!vcpu->arch.apic)
2777 goto out;
d1ac91d8 2778 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2779
b772ff36 2780 r = -ENOMEM;
d1ac91d8 2781 if (!u.lapic)
b772ff36 2782 goto out;
d1ac91d8 2783 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2784 if (r)
2785 goto out;
2786 r = -EFAULT;
d1ac91d8 2787 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2788 goto out;
2789 r = 0;
2790 break;
2791 }
2792 case KVM_SET_LAPIC: {
2204ae3c
MT		 2793 r = -EINVAL;
2794 if (!vcpu->arch.apic)
2795 goto out;
d1ac91d8 2796 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2797 r = -ENOMEM;
d1ac91d8 2798 if (!u.lapic)
b772ff36 2799 goto out;
313a3dc7 2800 r = -EFAULT;
d1ac91d8 2801 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2802 goto out;
d1ac91d8 2803 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2804 if (r)
2805 goto out;
2806 r = 0;
2807 break;
2808 }
f77bc6a4
ZX		 2809 case KVM_INTERRUPT: {
2810 struct kvm_interrupt irq;
2811
2812 r = -EFAULT;
2813 if (copy_from_user(&irq, argp, sizeof irq))
2814 goto out;
2815 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2816 if (r)
2817 goto out;
2818 r = 0;
2819 break;
2820 }
c4abb7c9
JK		 2821 case KVM_NMI: {
2822 r = kvm_vcpu_ioctl_nmi(vcpu);
2823 if (r)
2824 goto out;
2825 r = 0;
2826 break;
2827 }
313a3dc7
CO		 2828 case KVM_SET_CPUID: {
2829 struct kvm_cpuid __user *cpuid_arg = argp;
2830 struct kvm_cpuid cpuid;
2831
2832 r = -EFAULT;
2833 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2834 goto out;
2835 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2836 if (r)
2837 goto out;
2838 break;
2839 }
07716717
DK		 2840 case KVM_SET_CPUID2: {
2841 struct kvm_cpuid2 __user *cpuid_arg = argp;
2842 struct kvm_cpuid2 cpuid;
2843
2844 r = -EFAULT;
2845 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2846 goto out;
2847 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2848 cpuid_arg->entries);
07716717
DK		 2849 if (r)
2850 goto out;
2851 break;
2852 }
2853 case KVM_GET_CPUID2: {
2854 struct kvm_cpuid2 __user *cpuid_arg = argp;
2855 struct kvm_cpuid2 cpuid;
2856
2857 r = -EFAULT;
2858 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2859 goto out;
2860 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2861 cpuid_arg->entries);
07716717
DK		 2862 if (r)
2863 goto out;
2864 r = -EFAULT;
2865 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2866 goto out;
2867 r = 0;
2868 break;
2869 }
313a3dc7
CO		 2870 case KVM_GET_MSRS:
2871 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2872 break;
2873 case KVM_SET_MSRS:
2874 r = msr_io(vcpu, argp, do_set_msr, 0);
2875 break;
b209749f
AK		 2876 case KVM_TPR_ACCESS_REPORTING: {
2877 struct kvm_tpr_access_ctl tac;
2878
2879 r = -EFAULT;
2880 if (copy_from_user(&tac, argp, sizeof tac))
2881 goto out;
2882 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2883 if (r)
2884 goto out;
2885 r = -EFAULT;
2886 if (copy_to_user(argp, &tac, sizeof tac))
2887 goto out;
2888 r = 0;
2889 break;
2890 };
b93463aa
AK		 2891 case KVM_SET_VAPIC_ADDR: {
2892 struct kvm_vapic_addr va;
2893
2894 r = -EINVAL;
2895 if (!irqchip_in_kernel(vcpu->kvm))
2896 goto out;
2897 r = -EFAULT;
2898 if (copy_from_user(&va, argp, sizeof va))
2899 goto out;
2900 r = 0;
2901 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2902 break;
2903 }
890ca9ae
HY		 2904 case KVM_X86_SETUP_MCE: {
2905 u64 mcg_cap;
2906
2907 r = -EFAULT;
2908 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2909 goto out;
2910 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2911 break;
2912 }
2913 case KVM_X86_SET_MCE: {
2914 struct kvm_x86_mce mce;
2915
2916 r = -EFAULT;
2917 if (copy_from_user(&mce, argp, sizeof mce))
2918 goto out;
2919 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2920 break;
2921 }
3cfc3092
JK		 2922 case KVM_GET_VCPU_EVENTS: {
2923 struct kvm_vcpu_events events;
2924
2925 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2926
2927 r = -EFAULT;
2928 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2929 break;
2930 r = 0;
2931 break;
2932 }
2933 case KVM_SET_VCPU_EVENTS: {
2934 struct kvm_vcpu_events events;
2935
2936 r = -EFAULT;
2937 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2938 break;
2939
2940 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2941 break;
2942 }
a1efbe77
JK		 2943 case KVM_GET_DEBUGREGS: {
2944 struct kvm_debugregs dbgregs;
2945
2946 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2947
2948 r = -EFAULT;
2949 if (copy_to_user(argp, &dbgregs,
2950 sizeof(struct kvm_debugregs)))
2951 break;
2952 r = 0;
2953 break;
2954 }
2955 case KVM_SET_DEBUGREGS: {
2956 struct kvm_debugregs dbgregs;
2957
2958 r = -EFAULT;
2959 if (copy_from_user(&dbgregs, argp,
2960 sizeof(struct kvm_debugregs)))
2961 break;
2962
2963 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2964 break;
2965 }
2d5b5a66 2966 case KVM_GET_XSAVE: {
d1ac91d8 2967 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2968 r = -ENOMEM;
d1ac91d8 2969 if (!u.xsave)
2d5b5a66
SY		 2970 break;
2971
d1ac91d8 2972 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2973
2974 r = -EFAULT;
d1ac91d8 2975 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2976 break;
2977 r = 0;
2978 break;
2979 }
2980 case KVM_SET_XSAVE: {
d1ac91d8 2981 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2982 r = -ENOMEM;
d1ac91d8 2983 if (!u.xsave)
2d5b5a66
SY		 2984 break;
2985
2986 r = -EFAULT;
d1ac91d8 2987 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2988 break;
2989
d1ac91d8 2990 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2991 break;
2992 }
2993 case KVM_GET_XCRS: {
d1ac91d8 2994 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2995 r = -ENOMEM;
d1ac91d8 2996 if (!u.xcrs)
2d5b5a66
SY		 2997 break;
2998
d1ac91d8 2999 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3000
3001 r = -EFAULT;
d1ac91d8 3002 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3003 sizeof(struct kvm_xcrs)))
3004 break;
3005 r = 0;
3006 break;
3007 }
3008 case KVM_SET_XCRS: {
d1ac91d8 3009 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3010 r = -ENOMEM;
d1ac91d8 3011 if (!u.xcrs)
2d5b5a66
SY		 3012 break;
3013
3014 r = -EFAULT;
d1ac91d8 3015 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 3016 sizeof(struct kvm_xcrs)))
3017 break;
3018
d1ac91d8 3019 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3020 break;
3021 }
313a3dc7
CO		 3022 default:
3023 r = -EINVAL;
3024 }
3025out:
d1ac91d8 3026 kfree(u.buffer);
313a3dc7
CO		 3027 return r;
3028}
3029
1fe779f8
CO		 3030static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3031{
3032 int ret;
3033
3034 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3035 return -1;
3036 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3037 return ret;
3038}
3039
b927a3ce
SY		 3040static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3041 u64 ident_addr)
3042{
3043 kvm->arch.ept_identity_map_addr = ident_addr;
3044 return 0;
3045}
3046
1fe779f8
CO		 3047static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3048 u32 kvm_nr_mmu_pages)
3049{
3050 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3051 return -EINVAL;
3052
79fac95e 3053 mutex_lock(&kvm->slots_lock);
7c8a83b7 3054 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 3055
3056 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3057 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3058
7c8a83b7 3059 spin_unlock(&kvm->mmu_lock);
79fac95e 3060 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3061 return 0;
3062}
3063
3064static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3065{
39de71ec 3066 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3067}
3068
1fe779f8
CO		 3069static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3070{
3071 int r;
3072
3073 r = 0;
3074 switch (chip->chip_id) {
3075 case KVM_IRQCHIP_PIC_MASTER:
3076 memcpy(&chip->chip.pic,
3077 &pic_irqchip(kvm)->pics[0],
3078 sizeof(struct kvm_pic_state));
3079 break;
3080 case KVM_IRQCHIP_PIC_SLAVE:
3081 memcpy(&chip->chip.pic,
3082 &pic_irqchip(kvm)->pics[1],
3083 sizeof(struct kvm_pic_state));
3084 break;
3085 case KVM_IRQCHIP_IOAPIC:
eba0226b 3086 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3087 break;
3088 default:
3089 r = -EINVAL;
3090 break;
3091 }
3092 return r;
3093}
3094
3095static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3096{
3097 int r;
3098
3099 r = 0;
3100 switch (chip->chip_id) {
3101 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3102 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3103 memcpy(&pic_irqchip(kvm)->pics[0],
3104 &chip->chip.pic,
3105 sizeof(struct kvm_pic_state));
f4f51050 3106 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3107 break;
3108 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3109 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3110 memcpy(&pic_irqchip(kvm)->pics[1],
3111 &chip->chip.pic,
3112 sizeof(struct kvm_pic_state));
f4f51050 3113 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3114 break;
3115 case KVM_IRQCHIP_IOAPIC:
eba0226b 3116 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3117 break;
3118 default:
3119 r = -EINVAL;
3120 break;
3121 }
3122 kvm_pic_update_irq(pic_irqchip(kvm));
3123 return r;
3124}
3125
e0f63cb9
SY		 3126static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3127{
3128 int r = 0;
3129
894a9c55 3130 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3131 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3132 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3133 return r;
3134}
3135
3136static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3137{
3138 int r = 0;
3139
894a9c55 3140 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3141 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3142 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3143 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3144 return r;
3145}
3146
3147static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3148{
3149 int r = 0;
3150
3151 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3152 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3153 sizeof(ps->channels));
3154 ps->flags = kvm->arch.vpit->pit_state.flags;
3155 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3156 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3157 return r;
3158}
3159
3160static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3161{
3162 int r = 0, start = 0;
3163 u32 prev_legacy, cur_legacy;
3164 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3165 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3166 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3167 if (!prev_legacy && cur_legacy)
3168 start = 1;
3169 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3170 sizeof(kvm->arch.vpit->pit_state.channels));
3171 kvm->arch.vpit->pit_state.flags = ps->flags;
3172 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3173 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3174 return r;
3175}
3176
52d939a0
MT		 3177static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3178 struct kvm_reinject_control *control)
3179{
3180 if (!kvm->arch.vpit)
3181 return -ENXIO;
894a9c55 3182 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3183 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3184 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3185 return 0;
3186}
3187
5bb064dc
ZX		 3188/*
3189 * Get (and clear) the dirty memory log for a memory slot.
3190 */
3191int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3192 struct kvm_dirty_log *log)
3193{
87bf6e7d 3194 int r, i;
5bb064dc 3195 struct kvm_memory_slot *memslot;
87bf6e7d 3196 unsigned long n;
b050b015 3197 unsigned long is_dirty = 0;
5bb064dc 3198
79fac95e 3199 mutex_lock(&kvm->slots_lock);
5bb064dc 3200
b050b015
MT		 3201 r = -EINVAL;
3202 if (log->slot >= KVM_MEMORY_SLOTS)
3203 goto out;
3204
3205 memslot = &kvm->memslots->memslots[log->slot];
3206 r = -ENOENT;
3207 if (!memslot->dirty_bitmap)
3208 goto out;
3209
87bf6e7d 3210 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3211
b050b015
MT		 3212 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3213 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3214
3215 /* If nothing is dirty, don't bother messing with page tables. */
3216 if (is_dirty) {
b050b015 3217 struct kvm_memslots *slots, *old_slots;
914ebccd 3218 unsigned long *dirty_bitmap;
b050b015 3219
515a0127
TY		 3220 dirty_bitmap = memslot->dirty_bitmap_head;
3221 if (memslot->dirty_bitmap == dirty_bitmap)
3222 dirty_bitmap += n / sizeof(long);
914ebccd 3223 memset(dirty_bitmap, 0, n);
b050b015 3224
914ebccd
TY		 3225 r = -ENOMEM;
3226 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
515a0127 3227 if (!slots)
914ebccd 3228 goto out;
b050b015
MT		 3229 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3230 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
49c7754c 3231 slots->generation++;
b050b015
MT		 3232
3233 old_slots = kvm->memslots;
3234 rcu_assign_pointer(kvm->memslots, slots);
3235 synchronize_srcu_expedited(&kvm->srcu);
3236 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3237 kfree(old_slots);
914ebccd 3238
edde99ce
MT		 3239 spin_lock(&kvm->mmu_lock);
3240 kvm_mmu_slot_remove_write_access(kvm, log->slot);
3241 spin_unlock(&kvm->mmu_lock);
3242
914ebccd 3243 r = -EFAULT;
515a0127 3244 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
914ebccd 3245 goto out;
914ebccd
TY		 3246 } else {
3247 r = -EFAULT;
3248 if (clear_user(log->dirty_bitmap, n))
3249 goto out;
5bb064dc 3250 }
b050b015 3251
5bb064dc
ZX		 3252 r = 0;
3253out:
79fac95e 3254 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3255 return r;
3256}
3257
1fe779f8
CO		 3258long kvm_arch_vm_ioctl(struct file *filp,
3259 unsigned int ioctl, unsigned long arg)
3260{
3261 struct kvm *kvm = filp->private_data;
3262 void __user *argp = (void __user *)arg;
367e1319 3263 int r = -ENOTTY;
f0d66275
DH		 3264 /*
3265 * This union makes it completely explicit to gcc-3.x
3266 * that these two variables' stack usage should be
3267 * combined, not added together.
3268 */
3269 union {
3270 struct kvm_pit_state ps;
e9f42757 3271 struct kvm_pit_state2 ps2;
c5ff41ce 3272 struct kvm_pit_config pit_config;
f0d66275 3273 } u;
1fe779f8
CO		 3274
3275 switch (ioctl) {
3276 case KVM_SET_TSS_ADDR:
3277 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3278 if (r < 0)
3279 goto out;
3280 break;
b927a3ce
SY		 3281 case KVM_SET_IDENTITY_MAP_ADDR: {
3282 u64 ident_addr;
3283
3284 r = -EFAULT;
3285 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3286 goto out;
3287 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3288 if (r < 0)
3289 goto out;
3290 break;
3291 }
1fe779f8
CO		 3292 case KVM_SET_NR_MMU_PAGES:
3293 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3294 if (r)
3295 goto out;
3296 break;
3297 case KVM_GET_NR_MMU_PAGES:
3298 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3299 break;
3ddea128
MT		 3300 case KVM_CREATE_IRQCHIP: {
3301 struct kvm_pic *vpic;
3302
3303 mutex_lock(&kvm->lock);
3304 r = -EEXIST;
3305 if (kvm->arch.vpic)
3306 goto create_irqchip_unlock;
1fe779f8 3307 r = -ENOMEM;
3ddea128
MT		 3308 vpic = kvm_create_pic(kvm);
3309 if (vpic) {
1fe779f8
CO		 3310 r = kvm_ioapic_init(kvm);
3311 if (r) {
72bb2fcd
WY		 3312 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3313 &vpic->dev);
3ddea128
MT		 3314 kfree(vpic);
3315 goto create_irqchip_unlock;
1fe779f8
CO		 3316 }
3317 } else
3ddea128
MT		 3318 goto create_irqchip_unlock;
3319 smp_wmb();
3320 kvm->arch.vpic = vpic;
3321 smp_wmb();
399ec807
AK		 3322 r = kvm_setup_default_irq_routing(kvm);
3323 if (r) {
3ddea128 3324 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3325 kvm_ioapic_destroy(kvm);
3326 kvm_destroy_pic(kvm);
3ddea128 3327 mutex_unlock(&kvm->irq_lock);
399ec807 3328 }
3ddea128
MT		 3329 create_irqchip_unlock:
3330 mutex_unlock(&kvm->lock);
1fe779f8 3331 break;
3ddea128 3332 }
7837699f 3333 case KVM_CREATE_PIT:
c5ff41ce
JK		 3334 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3335 goto create_pit;
3336 case KVM_CREATE_PIT2:
3337 r = -EFAULT;
3338 if (copy_from_user(&u.pit_config, argp,
3339 sizeof(struct kvm_pit_config)))
3340 goto out;
3341 create_pit:
79fac95e 3342 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3343 r = -EEXIST;
3344 if (kvm->arch.vpit)
3345 goto create_pit_unlock;
7837699f 3346 r = -ENOMEM;
c5ff41ce 3347 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3348 if (kvm->arch.vpit)
3349 r = 0;
269e05e4 3350 create_pit_unlock:
79fac95e 3351 mutex_unlock(&kvm->slots_lock);
7837699f 3352 break;
4925663a 3353 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3354 case KVM_IRQ_LINE: {
3355 struct kvm_irq_level irq_event;
3356
3357 r = -EFAULT;
3358 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3359 goto out;
160d2f6c 3360 r = -ENXIO;
1fe779f8 3361 if (irqchip_in_kernel(kvm)) {
4925663a 3362 __s32 status;
4925663a
GN		 3363 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3364 irq_event.irq, irq_event.level);
4925663a 3365 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3366 r = -EFAULT;
4925663a
GN		 3367 irq_event.status = status;
3368 if (copy_to_user(argp, &irq_event,
3369 sizeof irq_event))
3370 goto out;
3371 }
1fe779f8
CO		 3372 r = 0;
3373 }
3374 break;
3375 }
3376 case KVM_GET_IRQCHIP: {
3377 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3378 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3379
f0d66275
DH		 3380 r = -ENOMEM;
3381 if (!chip)
1fe779f8 3382 goto out;
f0d66275
DH		 3383 r = -EFAULT;
3384 if (copy_from_user(chip, argp, sizeof *chip))
3385 goto get_irqchip_out;
1fe779f8
CO		 3386 r = -ENXIO;
3387 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3388 goto get_irqchip_out;
3389 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3390 if (r)
f0d66275 3391 goto get_irqchip_out;
1fe779f8 3392 r = -EFAULT;
f0d66275
DH		 3393 if (copy_to_user(argp, chip, sizeof *chip))
3394 goto get_irqchip_out;
1fe779f8 3395 r = 0;
f0d66275
DH		 3396 get_irqchip_out:
3397 kfree(chip);
3398 if (r)
3399 goto out;
1fe779f8
CO		 3400 break;
3401 }
3402 case KVM_SET_IRQCHIP: {
3403 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3404 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3405
f0d66275
DH		 3406 r = -ENOMEM;
3407 if (!chip)
1fe779f8 3408 goto out;
f0d66275
DH		 3409 r = -EFAULT;
3410 if (copy_from_user(chip, argp, sizeof *chip))
3411 goto set_irqchip_out;
1fe779f8
CO		 3412 r = -ENXIO;
3413 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3414 goto set_irqchip_out;
3415 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3416 if (r)
f0d66275 3417 goto set_irqchip_out;
1fe779f8 3418 r = 0;
f0d66275
DH		 3419 set_irqchip_out:
3420 kfree(chip);
3421 if (r)
3422 goto out;
1fe779f8
CO		 3423 break;
3424 }
e0f63cb9 3425 case KVM_GET_PIT: {
e0f63cb9 3426 r = -EFAULT;
f0d66275 3427 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3428 goto out;
3429 r = -ENXIO;
3430 if (!kvm->arch.vpit)
3431 goto out;
f0d66275 3432 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3433 if (r)
3434 goto out;
3435 r = -EFAULT;
f0d66275 3436 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3437 goto out;
3438 r = 0;
3439 break;
3440 }
3441 case KVM_SET_PIT: {
e0f63cb9 3442 r = -EFAULT;
f0d66275 3443 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3444 goto out;
3445 r = -ENXIO;
3446 if (!kvm->arch.vpit)
3447 goto out;
f0d66275 3448 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3449 if (r)
3450 goto out;
3451 r = 0;
3452 break;
3453 }
e9f42757
BK		 3454 case KVM_GET_PIT2: {
3455 r = -ENXIO;
3456 if (!kvm->arch.vpit)
3457 goto out;
3458 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3459 if (r)
3460 goto out;
3461 r = -EFAULT;
3462 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3463 goto out;
3464 r = 0;
3465 break;
3466 }
3467 case KVM_SET_PIT2: {
3468 r = -EFAULT;
3469 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3470 goto out;
3471 r = -ENXIO;
3472 if (!kvm->arch.vpit)
3473 goto out;
3474 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3475 if (r)
3476 goto out;
3477 r = 0;
3478 break;
3479 }
52d939a0
MT		 3480 case KVM_REINJECT_CONTROL: {
3481 struct kvm_reinject_control control;
3482 r = -EFAULT;
3483 if (copy_from_user(&control, argp, sizeof(control)))
3484 goto out;
3485 r = kvm_vm_ioctl_reinject(kvm, &control);
3486 if (r)
3487 goto out;
3488 r = 0;
3489 break;
3490 }
ffde22ac
ES		 3491 case KVM_XEN_HVM_CONFIG: {
3492 r = -EFAULT;
3493 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3494 sizeof(struct kvm_xen_hvm_config)))
3495 goto out;
3496 r = -EINVAL;
3497 if (kvm->arch.xen_hvm_config.flags)
3498 goto out;
3499 r = 0;
3500 break;
3501 }
afbcf7ab 3502 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3503 struct kvm_clock_data user_ns;
3504 u64 now_ns;
3505 s64 delta;
3506
3507 r = -EFAULT;
3508 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3509 goto out;
3510
3511 r = -EINVAL;
3512 if (user_ns.flags)
3513 goto out;
3514
3515 r = 0;
395c6b0a 3516 local_irq_disable();
759379dd 3517 now_ns = get_kernel_ns();
afbcf7ab 3518 delta = user_ns.clock - now_ns;
395c6b0a 3519 local_irq_enable();
afbcf7ab
GC		 3520 kvm->arch.kvmclock_offset = delta;
3521 break;
3522 }
3523 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3524 struct kvm_clock_data user_ns;
3525 u64 now_ns;
3526
395c6b0a 3527 local_irq_disable();
759379dd 3528 now_ns = get_kernel_ns();
afbcf7ab 3529 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3530 local_irq_enable();
afbcf7ab 3531 user_ns.flags = 0;
97e69aa6 3532 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3533
3534 r = -EFAULT;
3535 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3536 goto out;
3537 r = 0;
3538 break;
3539 }
3540
1fe779f8
CO		 3541 default:
3542 ;
3543 }
3544out:
3545 return r;
3546}
3547
a16b043c 3548static void kvm_init_msr_list(void)
043405e1
CO		 3549{
3550 u32 dummy[2];
3551 unsigned i, j;
3552
e3267cbb
GC		 3553 /* skip the first msrs in the list. KVM-specific */
3554 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3555 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3556 continue;
3557 if (j < i)
3558 msrs_to_save[j] = msrs_to_save[i];
3559 j++;
3560 }
3561 num_msrs_to_save = j;
3562}
3563
bda9020e
MT		 3564static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3565 const void *v)
bbd9b64e 3566{
bda9020e
MT		 3567 if (vcpu->arch.apic &&
3568 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3569 return 0;
bbd9b64e 3570
e93f8a0f 3571 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3572}
3573
bda9020e 3574static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3575{
bda9020e
MT		 3576 if (vcpu->arch.apic &&
3577 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3578 return 0;
bbd9b64e 3579
e93f8a0f 3580 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3581}
3582
2dafc6c2
GN		 3583static void kvm_set_segment(struct kvm_vcpu *vcpu,
3584 struct kvm_segment *var, int seg)
3585{
3586 kvm_x86_ops->set_segment(vcpu, var, seg);
3587}
3588
3589void kvm_get_segment(struct kvm_vcpu *vcpu,
3590 struct kvm_segment *var, int seg)
3591{
3592 kvm_x86_ops->get_segment(vcpu, var, seg);
3593}
3594
c30a358d
JR		 3595static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3596{
3597 return gpa;
3598}
3599
02f59dc9
JR		 3600static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3601{
3602 gpa_t t_gpa;
ab9ae313 3603 struct x86_exception exception;
02f59dc9
JR		 3604
3605 BUG_ON(!mmu_is_nested(vcpu));
3606
3607 /* NPT walks are always user-walks */
3608 access |= PFERR_USER_MASK;
ab9ae313 3609 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3610
3611 return t_gpa;
3612}
3613
ab9ae313
AK		 3614gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3615 struct x86_exception *exception)
1871c602
GN		 3616{
3617 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3618 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3619}
3620
ab9ae313
AK		 3621 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3622 struct x86_exception *exception)
1871c602
GN		 3623{
3624 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3625 access |= PFERR_FETCH_MASK;
ab9ae313 3626 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3627}
3628
ab9ae313
AK		 3629gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3630 struct x86_exception *exception)
1871c602
GN		 3631{
3632 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3633 access |= PFERR_WRITE_MASK;
ab9ae313 3634 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3635}
3636
3637/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3638gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3639 struct x86_exception *exception)
bcc55cba 3640{
ab9ae313 3641 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
bcc55cba
AK		 3642}
3643
1871c602
GN		 3644static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3645 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3646 struct x86_exception *exception)
bbd9b64e
CO		 3647{
3648 void *data = val;
10589a46 3649 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3650
3651 while (bytes) {
14dfe855 3652 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3653 exception);
bbd9b64e 3654 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3655 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3656 int ret;
3657
bcc55cba 3658 if (gpa == UNMAPPED_GVA)
ab9ae313 3659 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3660 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3661 if (ret < 0) {
c3cd7ffa 3662 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3663 goto out;
3664 }
bbd9b64e 3665
77c2002e
IE		 3666 bytes -= toread;
3667 data += toread;
3668 addr += toread;
bbd9b64e 3669 }
10589a46 3670out:
10589a46 3671 return r;
bbd9b64e 3672}
77c2002e 3673
1871c602
GN		 3674/* used for instruction fetching */
3675static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
bcc55cba
AK		 3676 struct kvm_vcpu *vcpu,
3677 struct x86_exception *exception)
1871c602
GN		 3678{
3679 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3680 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3681 access | PFERR_FETCH_MASK,
3682 exception);
1871c602
GN		 3683}
3684
3685static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
bcc55cba
AK		 3686 struct kvm_vcpu *vcpu,
3687 struct x86_exception *exception)
1871c602
GN		 3688{
3689 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3690 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3691 exception);
1871c602
GN		 3692}
3693
3694static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
bcc55cba
AK		 3695 struct kvm_vcpu *vcpu,
3696 struct x86_exception *exception)
1871c602 3697{
bcc55cba 3698 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3699}
3700
7972995b 3701static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3702 unsigned int bytes,
7972995b 3703 struct kvm_vcpu *vcpu,
bcc55cba 3704 struct x86_exception *exception)
77c2002e
IE		 3705{
3706 void *data = val;
3707 int r = X86EMUL_CONTINUE;
3708
3709 while (bytes) {
14dfe855
JR		 3710 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3711 PFERR_WRITE_MASK,
ab9ae313 3712 exception);
77c2002e
IE		 3713 unsigned offset = addr & (PAGE_SIZE-1);
3714 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3715 int ret;
3716
bcc55cba 3717 if (gpa == UNMAPPED_GVA)
ab9ae313 3718 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3719 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3720 if (ret < 0) {
c3cd7ffa 3721 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3722 goto out;
3723 }
3724
3725 bytes -= towrite;
3726 data += towrite;
3727 addr += towrite;
3728 }
3729out:
3730 return r;
3731}
3732
bbd9b64e
CO		 3733static int emulator_read_emulated(unsigned long addr,
3734 void *val,
3735 unsigned int bytes,
bcc55cba 3736 struct x86_exception *exception,
bbd9b64e
CO		 3737 struct kvm_vcpu *vcpu)
3738{
bbd9b64e
CO		 3739 gpa_t gpa;
3740
3741 if (vcpu->mmio_read_completed) {
3742 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3743 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3744 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3745 vcpu->mmio_read_completed = 0;
3746 return X86EMUL_CONTINUE;
3747 }
3748
ab9ae313 3749 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, exception);
1871c602 3750
8fe681e9 3751 if (gpa == UNMAPPED_GVA)
ab9ae313 3752 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3753
3754 /* For APIC access vmexit */
3755 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3756 goto mmio;
3757
bcc55cba
AK		 3758 if (kvm_read_guest_virt(addr, val, bytes, vcpu, exception)
3759 == X86EMUL_CONTINUE)
bbd9b64e 3760 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3761
3762mmio:
3763 /*
3764 * Is this MMIO handled locally?
3765 */
aec51dc4
AK		 3766 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3767 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3768 return X86EMUL_CONTINUE;
3769 }
aec51dc4
AK		 3770
3771 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3772
3773 vcpu->mmio_needed = 1;
411c35b7
GN		 3774 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3775 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3776 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3777 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
bbd9b64e 3778
c3cd7ffa 3779 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3780}
3781
3200f405 3782int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 3783 const void *val, int bytes)
bbd9b64e
CO		 3784{
3785 int ret;
3786
3787 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3788 if (ret < 0)
bbd9b64e 3789 return 0;
ad218f85 3790 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3791 return 1;
3792}
3793
3794static int emulator_write_emulated_onepage(unsigned long addr,
3795 const void *val,
3796 unsigned int bytes,
bcc55cba 3797 struct x86_exception *exception,
bbd9b64e
CO		 3798 struct kvm_vcpu *vcpu)
3799{
10589a46
MT		 3800 gpa_t gpa;
3801
ab9ae313 3802 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, exception);
bbd9b64e 3803
8fe681e9 3804 if (gpa == UNMAPPED_GVA)
ab9ae313 3805 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3806
3807 /* For APIC access vmexit */
3808 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3809 goto mmio;
3810
3811 if (emulator_write_phys(vcpu, gpa, val, bytes))
3812 return X86EMUL_CONTINUE;
3813
3814mmio:
aec51dc4 3815 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3816 /*
3817 * Is this MMIO handled locally?
3818 */
bda9020e 3819 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3820 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3821
3822 vcpu->mmio_needed = 1;
411c35b7
GN		 3823 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3824 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3825 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3826 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
3827 memcpy(vcpu->run->mmio.data, val, bytes);
bbd9b64e
CO		 3828
3829 return X86EMUL_CONTINUE;
3830}
3831
3832int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3833 const void *val,
3834 unsigned int bytes,
bcc55cba 3835 struct x86_exception *exception,
8f6abd06 3836 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3837{
3838 /* Crossing a page boundary? */
3839 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3840 int rc, now;
3841
3842 now = -addr & ~PAGE_MASK;
bcc55cba 3843 rc = emulator_write_emulated_onepage(addr, val, now, exception,
8fe681e9 3844 vcpu);
bbd9b64e
CO		 3845 if (rc != X86EMUL_CONTINUE)
3846 return rc;
3847 addr += now;
3848 val += now;
3849 bytes -= now;
3850 }
bcc55cba 3851 return emulator_write_emulated_onepage(addr, val, bytes, exception,
8fe681e9 3852 vcpu);
bbd9b64e 3853}
bbd9b64e 3854
daea3e73
AK		 3855#define CMPXCHG_TYPE(t, ptr, old, new) \
3856 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3857
3858#ifdef CONFIG_X86_64
3859# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3860#else
3861# define CMPXCHG64(ptr, old, new) \
9749a6c0 3862 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3863#endif
3864
bbd9b64e
CO		 3865static int emulator_cmpxchg_emulated(unsigned long addr,
3866 const void *old,
3867 const void *new,
3868 unsigned int bytes,
bcc55cba 3869 struct x86_exception *exception,
bbd9b64e
CO		 3870 struct kvm_vcpu *vcpu)
3871{
daea3e73
AK		 3872 gpa_t gpa;
3873 struct page *page;
3874 char *kaddr;
3875 bool exchanged;
2bacc55c 3876
daea3e73
AK		 3877 /* guests cmpxchg8b have to be emulated atomically */
3878 if (bytes > 8 || (bytes & (bytes - 1)))
3879 goto emul_write;
10589a46 3880
daea3e73 3881 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3882
daea3e73
AK		 3883 if (gpa == UNMAPPED_GVA ||
3884 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3885 goto emul_write;
2bacc55c 3886
daea3e73
AK		 3887 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3888 goto emul_write;
72dc67a6 3889
daea3e73 3890 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3891 if (is_error_page(page)) {
3892 kvm_release_page_clean(page);
3893 goto emul_write;
3894 }
72dc67a6 3895
daea3e73
AK		 3896 kaddr = kmap_atomic(page, KM_USER0);
3897 kaddr += offset_in_page(gpa);
3898 switch (bytes) {
3899 case 1:
3900 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3901 break;
3902 case 2:
3903 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3904 break;
3905 case 4:
3906 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3907 break;
3908 case 8:
3909 exchanged = CMPXCHG64(kaddr, old, new);
3910 break;
3911 default:
3912 BUG();
2bacc55c 3913 }
daea3e73
AK		 3914 kunmap_atomic(kaddr, KM_USER0);
3915 kvm_release_page_dirty(page);
3916
3917 if (!exchanged)
3918 return X86EMUL_CMPXCHG_FAILED;
3919
8f6abd06
GN		 3920 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3921
3922 return X86EMUL_CONTINUE;
4a5f48f6 3923
3200f405 3924emul_write:
daea3e73 3925 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3926
bcc55cba 3927 return emulator_write_emulated(addr, new, bytes, exception, vcpu);
bbd9b64e
CO		 3928}
3929
cf8f70bf
GN		 3930static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3931{
3932 /* TODO: String I/O for in kernel device */
3933 int r;
3934
3935 if (vcpu->arch.pio.in)
3936 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3937 vcpu->arch.pio.size, pd);
3938 else
3939 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3940 vcpu->arch.pio.port, vcpu->arch.pio.size,
3941 pd);
3942 return r;
3943}
3944
3945
3946static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3947 unsigned int count, struct kvm_vcpu *vcpu)
3948{
7972995b 3949 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3950 goto data_avail;
3951
61cfab2e 3952 trace_kvm_pio(0, port, size, count);
cf8f70bf
GN		 3953
3954 vcpu->arch.pio.port = port;
3955 vcpu->arch.pio.in = 1;
7972995b 3956 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3957 vcpu->arch.pio.size = size;
3958
3959 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3960 data_avail:
3961 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3962 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3963 return 1;
3964 }
3965
3966 vcpu->run->exit_reason = KVM_EXIT_IO;
3967 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3968 vcpu->run->io.size = size;
3969 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3970 vcpu->run->io.count = count;
3971 vcpu->run->io.port = port;
3972
3973 return 0;
3974}
3975
3976static int emulator_pio_out_emulated(int size, unsigned short port,
3977 const void *val, unsigned int count,
3978 struct kvm_vcpu *vcpu)
3979{
61cfab2e 3980 trace_kvm_pio(1, port, size, count);
cf8f70bf
GN		 3981
3982 vcpu->arch.pio.port = port;
3983 vcpu->arch.pio.in = 0;
7972995b 3984 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3985 vcpu->arch.pio.size = size;
3986
3987 memcpy(vcpu->arch.pio_data, val, size * count);
3988
3989 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3990 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3991 return 1;
3992 }
3993
3994 vcpu->run->exit_reason = KVM_EXIT_IO;
3995 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3996 vcpu->run->io.size = size;
3997 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3998 vcpu->run->io.count = count;
3999 vcpu->run->io.port = port;
4000
4001 return 0;
4002}
4003
bbd9b64e
CO		 4004static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4005{
4006 return kvm_x86_ops->get_segment_base(vcpu, seg);
4007}
4008
4009int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
4010{
a7052897 4011 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 4012 return X86EMUL_CONTINUE;
4013}
4014
f5f48ee1
SY		 4015int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4016{
4017 if (!need_emulate_wbinvd(vcpu))
4018 return X86EMUL_CONTINUE;
4019
4020 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4021 int cpu = get_cpu();
4022
4023 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4024 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4025 wbinvd_ipi, NULL, 1);
2eec7343 4026 put_cpu();
f5f48ee1 4027 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4028 } else
4029 wbinvd();
f5f48ee1
SY		 4030 return X86EMUL_CONTINUE;
4031}
4032EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4033
bbd9b64e
CO		 4034int emulate_clts(struct kvm_vcpu *vcpu)
4035{
4d4ec087 4036 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 4037 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 4038 return X86EMUL_CONTINUE;
4039}
4040
35aa5375 4041int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
bbd9b64e 4042{
338dbc97 4043 return _kvm_get_dr(vcpu, dr, dest);
bbd9b64e
CO		 4044}
4045
35aa5375 4046int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
bbd9b64e 4047{
338dbc97
GN		 4048
4049 return __kvm_set_dr(vcpu, dr, value);
bbd9b64e
CO		 4050}
4051
52a46617 4052static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4053{
52a46617 4054 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4055}
4056
52a46617 4057static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 4058{
52a46617
GN		 4059 unsigned long value;
4060
4061 switch (cr) {
4062 case 0:
4063 value = kvm_read_cr0(vcpu);
4064 break;
4065 case 2:
4066 value = vcpu->arch.cr2;
4067 break;
4068 case 3:
4069 value = vcpu->arch.cr3;
4070 break;
4071 case 4:
4072 value = kvm_read_cr4(vcpu);
4073 break;
4074 case 8:
4075 value = kvm_get_cr8(vcpu);
4076 break;
4077 default:
4078 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4079 return 0;
4080 }
4081
4082 return value;
4083}
4084
0f12244f 4085static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
52a46617 4086{
0f12244f
GN		 4087 int res = 0;
4088
52a46617
GN		 4089 switch (cr) {
4090 case 0:
49a9b07e 4091 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4092 break;
4093 case 2:
4094 vcpu->arch.cr2 = val;
4095 break;
4096 case 3:
2390218b 4097 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4098 break;
4099 case 4:
a83b29c6 4100 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4101 break;
4102 case 8:
0f12244f 4103 res = __kvm_set_cr8(vcpu, val & 0xfUL);
52a46617
GN		 4104 break;
4105 default:
4106 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4107 res = -1;
52a46617 4108 }
0f12244f
GN		 4109
4110 return res;
52a46617
GN		 4111}
4112
9c537244
GN		 4113static int emulator_get_cpl(struct kvm_vcpu *vcpu)
4114{
4115 return kvm_x86_ops->get_cpl(vcpu);
4116}
4117
2dafc6c2
GN		 4118static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4119{
4120 kvm_x86_ops->get_gdt(vcpu, dt);
4121}
4122
160ce1f1
MG		 4123static void emulator_get_idt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4124{
4125 kvm_x86_ops->get_idt(vcpu, dt);
4126}
4127
5951c442
GN		 4128static unsigned long emulator_get_cached_segment_base(int seg,
4129 struct kvm_vcpu *vcpu)
4130{
4131 return get_segment_base(vcpu, seg);
4132}
4133
2dafc6c2
GN		 4134static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
4135 struct kvm_vcpu *vcpu)
4136{
4137 struct kvm_segment var;
4138
4139 kvm_get_segment(vcpu, &var, seg);
4140
4141 if (var.unusable)
4142 return false;
4143
4144 if (var.g)
4145 var.limit >>= 12;
4146 set_desc_limit(desc, var.limit);
4147 set_desc_base(desc, (unsigned long)var.base);
4148 desc->type = var.type;
4149 desc->s = var.s;
4150 desc->dpl = var.dpl;
4151 desc->p = var.present;
4152 desc->avl = var.avl;
4153 desc->l = var.l;
4154 desc->d = var.db;
4155 desc->g = var.g;
4156
4157 return true;
4158}
4159
4160static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
4161 struct kvm_vcpu *vcpu)
4162{
4163 struct kvm_segment var;
4164
4165 /* needed to preserve selector */
4166 kvm_get_segment(vcpu, &var, seg);
4167
4168 var.base = get_desc_base(desc);
4169 var.limit = get_desc_limit(desc);
4170 if (desc->g)
4171 var.limit = (var.limit << 12) | 0xfff;
4172 var.type = desc->type;
4173 var.present = desc->p;
4174 var.dpl = desc->dpl;
4175 var.db = desc->d;
4176 var.s = desc->s;
4177 var.l = desc->l;
4178 var.g = desc->g;
4179 var.avl = desc->avl;
4180 var.present = desc->p;
4181 var.unusable = !var.present;
4182 var.padding = 0;
4183
4184 kvm_set_segment(vcpu, &var, seg);
4185 return;
4186}
4187
4188static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
4189{
4190 struct kvm_segment kvm_seg;
4191
4192 kvm_get_segment(vcpu, &kvm_seg, seg);
4193 return kvm_seg.selector;
4194}
4195
4196static void emulator_set_segment_selector(u16 sel, int seg,
4197 struct kvm_vcpu *vcpu)
4198{
4199 struct kvm_segment kvm_seg;
4200
4201 kvm_get_segment(vcpu, &kvm_seg, seg);
4202 kvm_seg.selector = sel;
4203 kvm_set_segment(vcpu, &kvm_seg, seg);
4204}
4205
14af3f3c 4206static struct x86_emulate_ops emulate_ops = {
1871c602 4207 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4208 .write_std = kvm_write_guest_virt_system,
1871c602 4209 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4210 .read_emulated = emulator_read_emulated,
4211 .write_emulated = emulator_write_emulated,
4212 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 4213 .pio_in_emulated = emulator_pio_in_emulated,
4214 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 4215 .get_cached_descriptor = emulator_get_cached_descriptor,
4216 .set_cached_descriptor = emulator_set_cached_descriptor,
4217 .get_segment_selector = emulator_get_segment_selector,
4218 .set_segment_selector = emulator_set_segment_selector,
5951c442 4219 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4220 .get_gdt = emulator_get_gdt,
160ce1f1 4221 .get_idt = emulator_get_idt,
52a46617
GN		 4222 .get_cr = emulator_get_cr,
4223 .set_cr = emulator_set_cr,
9c537244 4224 .cpl = emulator_get_cpl,
35aa5375
GN		 4225 .get_dr = emulator_get_dr,
4226 .set_dr = emulator_set_dr,
3fb1b5db
GN		 4227 .set_msr = kvm_set_msr,
4228 .get_msr = kvm_get_msr,
bbd9b64e
CO		 4229};
4230
5fdbf976
MT		 4231static void cache_all_regs(struct kvm_vcpu *vcpu)
4232{
4233 kvm_register_read(vcpu, VCPU_REGS_RAX);
4234 kvm_register_read(vcpu, VCPU_REGS_RSP);
4235 kvm_register_read(vcpu, VCPU_REGS_RIP);
4236 vcpu->arch.regs_dirty = ~0;
4237}
4238
95cb2295
GN		 4239static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4240{
4241 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4242 /*
4243 * an sti; sti; sequence only disable interrupts for the first
4244 * instruction. So, if the last instruction, be it emulated or
4245 * not, left the system with the INT_STI flag enabled, it
4246 * means that the last instruction is an sti. We should not
4247 * leave the flag on in this case. The same goes for mov ss
4248 */
4249 if (!(int_shadow & mask))
4250 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4251}
4252
54b8486f
GN		 4253static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4254{
4255 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4256 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4257 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4258 else if (ctxt->exception.error_code_valid)
4259 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4260 ctxt->exception.error_code);
54b8486f 4261 else
da9cb575 4262 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4263}
4264
8ec4722d
MG		 4265static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4266{
4267 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4268 int cs_db, cs_l;
4269
4270 cache_all_regs(vcpu);
4271
4272 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4273
4274 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4275 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4276 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4277 vcpu->arch.emulate_ctxt.mode =
4278 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4279 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4280 ? X86EMUL_MODE_VM86 : cs_l
4281 ? X86EMUL_MODE_PROT64 : cs_db
4282 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4283 memset(c, 0, sizeof(struct decode_cache));
4284 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4285}
4286
63995653
MG		 4287int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq)
4288{
4289 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4290 int ret;
4291
4292 init_emulate_ctxt(vcpu);
4293
4294 vcpu->arch.emulate_ctxt.decode.op_bytes = 2;
4295 vcpu->arch.emulate_ctxt.decode.ad_bytes = 2;
4296 vcpu->arch.emulate_ctxt.decode.eip = vcpu->arch.emulate_ctxt.eip;
4297 ret = emulate_int_real(&vcpu->arch.emulate_ctxt, &emulate_ops, irq);
4298
4299 if (ret != X86EMUL_CONTINUE)
4300 return EMULATE_FAIL;
4301
4302 vcpu->arch.emulate_ctxt.eip = c->eip;
4303 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4304 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4305 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4306
4307 if (irq == NMI_VECTOR)
4308 vcpu->arch.nmi_pending = false;
4309 else
4310 vcpu->arch.interrupt.pending = false;
4311
4312 return EMULATE_DONE;
4313}
4314EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4315
6d77dbfc
GN		 4316static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4317{
fc3a9157
JR		 4318 int r = EMULATE_DONE;
4319
6d77dbfc
GN		 4320 ++vcpu->stat.insn_emulation_fail;
4321 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4322 if (!is_guest_mode(vcpu)) {
4323 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4324 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4325 vcpu->run->internal.ndata = 0;
4326 r = EMULATE_FAIL;
4327 }
6d77dbfc 4328 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4329
4330 return r;
6d77dbfc
GN		 4331}
4332
a6f177ef
GN		 4333static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4334{
4335 gpa_t gpa;
4336
68be0803
GN		 4337 if (tdp_enabled)
4338 return false;
4339
a6f177ef
GN		 4340 /*
4341 * if emulation was due to access to shadowed page table
4342 * and it failed try to unshadow page and re-entetr the
4343 * guest to let CPU execute the instruction.
4344 */
4345 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4346 return true;
4347
4348 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4349
4350 if (gpa == UNMAPPED_GVA)
4351 return true; /* let cpu generate fault */
4352
4353 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4354 return true;
4355
4356 return false;
4357}
4358
bbd9b64e 4359int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 4360 unsigned long cr2,
4361 u16 error_code,
571008da 4362 int emulation_type)
bbd9b64e 4363{
95cb2295 4364 int r;
4d2179e1 4365 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
bbd9b64e 4366
26eef70c 4367 kvm_clear_exception_queue(vcpu);
ad312c7c 4368 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 4369 /*
56e82318 4370 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 4371 * instead of direct ->regs accesses, can save hundred cycles
4372 * on Intel for instructions that don't read/change RSP, for
4373 * for example.
4374 */
4375 cache_all_regs(vcpu);
bbd9b64e 4376
571008da 4377 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4378 init_emulate_ctxt(vcpu);
95cb2295 4379 vcpu->arch.emulate_ctxt.interruptibility = 0;
da9cb575 4380 vcpu->arch.emulate_ctxt.have_exception = false;
4fc40f07 4381 vcpu->arch.emulate_ctxt.perm_ok = false;
bbd9b64e 4382
9aabc88f 4383 r = x86_decode_insn(&vcpu->arch.emulate_ctxt);
d47f00a6
JR		 4384 if (r == X86EMUL_PROPAGATE_FAULT)
4385 goto done;
bbd9b64e 4386
e46479f8 4387 trace_kvm_emulate_insn_start(vcpu);
571008da 4388
0cb5762e
AP		 4389 /* Only allow emulation of specific instructions on #UD
4390 * (namely VMMCALL, sysenter, sysexit, syscall)*/
0cb5762e
AP		 4391 if (emulation_type & EMULTYPE_TRAP_UD) {
4392 if (!c->twobyte)
4393 return EMULATE_FAIL;
4394 switch (c->b) {
4395 case 0x01: /* VMMCALL */
4396 if (c->modrm_mod != 3 || c->modrm_rm != 1)
4397 return EMULATE_FAIL;
4398 break;
4399 case 0x34: /* sysenter */
4400 case 0x35: /* sysexit */
4401 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4402 return EMULATE_FAIL;
4403 break;
4404 case 0x05: /* syscall */
4405 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4406 return EMULATE_FAIL;
4407 break;
4408 default:
4409 return EMULATE_FAIL;
4410 }
4411
4412 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
4413 return EMULATE_FAIL;
4414 }
571008da 4415
f2b5756b 4416 ++vcpu->stat.insn_emulation;
bbd9b64e 4417 if (r) {
a6f177ef 4418 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4419 return EMULATE_DONE;
6d77dbfc
GN		 4420 if (emulation_type & EMULTYPE_SKIP)
4421 return EMULATE_FAIL;
4422 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4423 }
4424 }
4425
ba8afb6b
GN		 4426 if (emulation_type & EMULTYPE_SKIP) {
4427 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4428 return EMULATE_DONE;
4429 }
4430
4d2179e1
GN		 4431 /* this is needed for vmware backdor interface to work since it
4432 changes registers values during IO operation */
4433 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4434
5cd21917 4435restart:
9aabc88f 4436 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt);
bbd9b64e 4437
d2ddd1c4 4438 if (r == EMULATION_FAILED) {
a6f177ef 4439 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4440 return EMULATE_DONE;
4441
6d77dbfc 4442 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4443 }
4444
d47f00a6 4445done:
da9cb575 4446 if (vcpu->arch.emulate_ctxt.have_exception) {
54b8486f 4447 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4448 r = EMULATE_DONE;
4449 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4450 if (!vcpu->arch.pio.in)
4451 vcpu->arch.pio.count = 0;
e85d28f8
GN		 4452 r = EMULATE_DO_MMIO;
4453 } else if (vcpu->mmio_needed) {
3457e419
GN		 4454 if (vcpu->mmio_is_write)
4455 vcpu->mmio_needed = 0;
e85d28f8 4456 r = EMULATE_DO_MMIO;
d2ddd1c4 4457 } else if (r == EMULATION_RESTART)
5cd21917 4458 goto restart;
d2ddd1c4
GN		 4459 else
4460 r = EMULATE_DONE;
f850e2e6 4461
e85d28f8
GN		 4462 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
4463 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 4464 kvm_make_request(KVM_REQ_EVENT, vcpu);
e85d28f8
GN		 4465 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4466 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4467
4468 return r;
de7d789a 4469}
bbd9b64e 4470EXPORT_SYMBOL_GPL(emulate_instruction);
de7d789a 4471
cf8f70bf 4472int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4473{
cf8f70bf
GN		 4474 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4475 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
4476 /* do not return to emulator after return from userspace */
7972995b 4477 vcpu->arch.pio.count = 0;
de7d789a
CO		 4478 return ret;
4479}
cf8f70bf 4480EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4481
8cfdc000
ZA		 4482static void tsc_bad(void *info)
4483{
4484 __get_cpu_var(cpu_tsc_khz) = 0;
4485}
4486
4487static void tsc_khz_changed(void *data)
c8076604 4488{
8cfdc000
ZA		 4489 struct cpufreq_freqs *freq = data;
4490 unsigned long khz = 0;
4491
4492 if (data)
4493 khz = freq->new;
4494 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4495 khz = cpufreq_quick_get(raw_smp_processor_id());
4496 if (!khz)
4497 khz = tsc_khz;
4498 __get_cpu_var(cpu_tsc_khz) = khz;
c8076604
GH		 4499}
4500
c8076604
GH		 4501static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4502 void *data)
4503{
4504 struct cpufreq_freqs *freq = data;
4505 struct kvm *kvm;
4506 struct kvm_vcpu *vcpu;
4507 int i, send_ipi = 0;
4508
8cfdc000
ZA		 4509 /*
4510 * We allow guests to temporarily run on slowing clocks,
4511 * provided we notify them after, or to run on accelerating
4512 * clocks, provided we notify them before. Thus time never
4513 * goes backwards.
4514 *
4515 * However, we have a problem. We can't atomically update
4516 * the frequency of a given CPU from this function; it is
4517 * merely a notifier, which can be called from any CPU.
4518 * Changing the TSC frequency at arbitrary points in time
4519 * requires a recomputation of local variables related to
4520 * the TSC for each VCPU. We must flag these local variables
4521 * to be updated and be sure the update takes place with the
4522 * new frequency before any guests proceed.
4523 *
4524 * Unfortunately, the combination of hotplug CPU and frequency
4525 * change creates an intractable locking scenario; the order
4526 * of when these callouts happen is undefined with respect to
4527 * CPU hotplug, and they can race with each other. As such,
4528 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4529 * undefined; you can actually have a CPU frequency change take
4530 * place in between the computation of X and the setting of the
4531 * variable. To protect against this problem, all updates of
4532 * the per_cpu tsc_khz variable are done in an interrupt
4533 * protected IPI, and all callers wishing to update the value
4534 * must wait for a synchronous IPI to complete (which is trivial
4535 * if the caller is on the CPU already). This establishes the
4536 * necessary total order on variable updates.
4537 *
4538 * Note that because a guest time update may take place
4539 * anytime after the setting of the VCPU's request bit, the
4540 * correct TSC value must be set before the request. However,
4541 * to ensure the update actually makes it to any guest which
4542 * starts running in hardware virtualization between the set
4543 * and the acquisition of the spinlock, we must also ping the
4544 * CPU after setting the request bit.
4545 *
4546 */
4547
c8076604
GH		 4548 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4549 return 0;
4550 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4551 return 0;
8cfdc000
ZA		 4552
4553 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4554
4555 spin_lock(&kvm_lock);
4556 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4557 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4558 if (vcpu->cpu != freq->cpu)
4559 continue;
c285545f 4560 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4561 if (vcpu->cpu != smp_processor_id())
8cfdc000 4562 send_ipi = 1;
c8076604
GH		 4563 }
4564 }
4565 spin_unlock(&kvm_lock);
4566
4567 if (freq->old < freq->new && send_ipi) {
4568 /*
4569 * We upscale the frequency. Must make the guest
4570 * doesn't see old kvmclock values while running with
4571 * the new frequency, otherwise we risk the guest sees
4572 * time go backwards.
4573 *
4574 * In case we update the frequency for another cpu
4575 * (which might be in guest context) send an interrupt
4576 * to kick the cpu out of guest context. Next time
4577 * guest context is entered kvmclock will be updated,
4578 * so the guest will not see stale values.
4579 */
8cfdc000 4580 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4581 }
4582 return 0;
4583}
4584
4585static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4586 .notifier_call = kvmclock_cpufreq_notifier
4587};
4588
4589static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4590 unsigned long action, void *hcpu)
4591{
4592 unsigned int cpu = (unsigned long)hcpu;
4593
4594 switch (action) {
4595 case CPU_ONLINE:
4596 case CPU_DOWN_FAILED:
4597 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4598 break;
4599 case CPU_DOWN_PREPARE:
4600 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4601 break;
4602 }
4603 return NOTIFY_OK;
4604}
4605
4606static struct notifier_block kvmclock_cpu_notifier_block = {
4607 .notifier_call = kvmclock_cpu_notifier,
4608 .priority = -INT_MAX
c8076604
GH		 4609};
4610
b820cc0c
ZA		 4611static void kvm_timer_init(void)
4612{
4613 int cpu;
4614
c285545f 4615 max_tsc_khz = tsc_khz;
8cfdc000 4616 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4617 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4618#ifdef CONFIG_CPU_FREQ
4619 struct cpufreq_policy policy;
4620 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 4621 cpu = get_cpu();
4622 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 4623 if (policy.cpuinfo.max_freq)
4624 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 4625 put_cpu();
c285545f 4626#endif
b820cc0c
ZA		 4627 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4628 CPUFREQ_TRANSITION_NOTIFIER);
4629 }
c285545f 4630 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4631 for_each_online_cpu(cpu)
4632 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4633}
4634
ff9d07a0
ZY		 4635static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4636
4637static int kvm_is_in_guest(void)
4638{
4639 return percpu_read(current_vcpu) != NULL;
4640}
4641
4642static int kvm_is_user_mode(void)
4643{
4644 int user_mode = 3;
dcf46b94 4645
ff9d07a0
ZY		 4646 if (percpu_read(current_vcpu))
4647 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4648
ff9d07a0
ZY		 4649 return user_mode != 0;
4650}
4651
4652static unsigned long kvm_get_guest_ip(void)
4653{
4654 unsigned long ip = 0;
dcf46b94 4655
ff9d07a0
ZY		 4656 if (percpu_read(current_vcpu))
4657 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4658
ff9d07a0
ZY		 4659 return ip;
4660}
4661
4662static struct perf_guest_info_callbacks kvm_guest_cbs = {
4663 .is_in_guest = kvm_is_in_guest,
4664 .is_user_mode = kvm_is_user_mode,
4665 .get_guest_ip = kvm_get_guest_ip,
4666};
4667
4668void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4669{
4670 percpu_write(current_vcpu, vcpu);
4671}
4672EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4673
4674void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4675{
4676 percpu_write(current_vcpu, NULL);
4677}
4678EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4679
f8c16bba 4680int kvm_arch_init(void *opaque)
043405e1 4681{
b820cc0c 4682 int r;
f8c16bba
ZX		 4683 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4684
f8c16bba
ZX		 4685 if (kvm_x86_ops) {
4686 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4687 r = -EEXIST;
4688 goto out;
f8c16bba
ZX		 4689 }
4690
4691 if (!ops->cpu_has_kvm_support()) {
4692 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4693 r = -EOPNOTSUPP;
4694 goto out;
f8c16bba
ZX		 4695 }
4696 if (ops->disabled_by_bios()) {
4697 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4698 r = -EOPNOTSUPP;
4699 goto out;
f8c16bba
ZX		 4700 }
4701
97db56ce
AK		 4702 r = kvm_mmu_module_init();
4703 if (r)
4704 goto out;
4705
4706 kvm_init_msr_list();
4707
f8c16bba 4708 kvm_x86_ops = ops;
56c6d28a 4709 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e 4710 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4711 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4712
b820cc0c 4713 kvm_timer_init();
c8076604 4714
ff9d07a0
ZY		 4715 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4716
2acf923e
DC		 4717 if (cpu_has_xsave)
4718 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4719
f8c16bba 4720 return 0;
56c6d28a
ZX		 4721
4722out:
56c6d28a 4723 return r;
043405e1 4724}
8776e519 4725
f8c16bba
ZX		 4726void kvm_arch_exit(void)
4727{
ff9d07a0
ZY		 4728 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4729
888d256e
JK		 4730 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4731 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4732 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4733 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4734 kvm_x86_ops = NULL;
56c6d28a
ZX		 4735 kvm_mmu_module_exit();
4736}
f8c16bba 4737
8776e519
HB		 4738int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4739{
4740 ++vcpu->stat.halt_exits;
4741 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4742 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4743 return 1;
4744 } else {
4745 vcpu->run->exit_reason = KVM_EXIT_HLT;
4746 return 0;
4747 }
4748}
4749EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4750
2f333bcb
MT		 4751static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4752 unsigned long a1)
4753{
4754 if (is_long_mode(vcpu))
4755 return a0;
4756 else
4757 return a0 | ((gpa_t)a1 << 32);
4758}
4759
55cd8e5a
GN		 4760int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4761{
4762 u64 param, ingpa, outgpa, ret;
4763 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4764 bool fast, longmode;
4765 int cs_db, cs_l;
4766
4767 /*
4768 * hypercall generates UD from non zero cpl and real mode
4769 * per HYPER-V spec
4770 */
3eeb3288 4771 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4772 kvm_queue_exception(vcpu, UD_VECTOR);
4773 return 0;
4774 }
4775
4776 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4777 longmode = is_long_mode(vcpu) && cs_l == 1;
4778
4779 if (!longmode) {
ccd46936
GN		 4780 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4781 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4782 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4783 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4784 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4785 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4786 }
4787#ifdef CONFIG_X86_64
4788 else {
4789 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4790 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4791 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4792 }
4793#endif
4794
4795 code = param & 0xffff;
4796 fast = (param >> 16) & 0x1;
4797 rep_cnt = (param >> 32) & 0xfff;
4798 rep_idx = (param >> 48) & 0xfff;
4799
4800 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4801
c25bc163
GN		 4802 switch (code) {
4803 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4804 kvm_vcpu_on_spin(vcpu);
4805 break;
4806 default:
4807 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4808 break;
4809 }
55cd8e5a
GN		 4810
4811 ret = res | (((u64)rep_done & 0xfff) << 32);
4812 if (longmode) {
4813 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4814 } else {
4815 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4816 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4817 }
4818
4819 return 1;
4820}
4821
8776e519
HB		 4822int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4823{
4824 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4825 int r = 1;
8776e519 4826
55cd8e5a
GN		 4827 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4828 return kvm_hv_hypercall(vcpu);
4829
5fdbf976
MT		 4830 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4831 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4832 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4833 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4834 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4835
229456fc 4836 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4837
8776e519
HB		 4838 if (!is_long_mode(vcpu)) {
4839 nr &= 0xFFFFFFFF;
4840 a0 &= 0xFFFFFFFF;
4841 a1 &= 0xFFFFFFFF;
4842 a2 &= 0xFFFFFFFF;
4843 a3 &= 0xFFFFFFFF;
4844 }
4845
07708c4a
JK		 4846 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4847 ret = -KVM_EPERM;
4848 goto out;
4849 }
4850
8776e519 4851 switch (nr) {
b93463aa
AK		 4852 case KVM_HC_VAPIC_POLL_IRQ:
4853 ret = 0;
4854 break;
2f333bcb
MT		 4855 case KVM_HC_MMU_OP:
4856 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4857 break;
8776e519
HB		 4858 default:
4859 ret = -KVM_ENOSYS;
4860 break;
4861 }
07708c4a 4862out:
5fdbf976 4863 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4864 ++vcpu->stat.hypercalls;
2f333bcb 4865 return r;
8776e519
HB		 4866}
4867EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4868
4869int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4870{
4871 char instruction[3];
5fdbf976 4872 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4873
8776e519
HB		 4874 /*
4875 * Blow out the MMU to ensure that no other VCPU has an active mapping
4876 * to ensure that the updated hypercall appears atomically across all
4877 * VCPUs.
4878 */
4879 kvm_mmu_zap_all(vcpu->kvm);
4880
8776e519 4881 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4882
8fe681e9 4883 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
8776e519
HB		 4884}
4885
8776e519
HB		 4886void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4887{
89a27f4d 4888 struct desc_ptr dt = { limit, base };
8776e519
HB		 4889
4890 kvm_x86_ops->set_gdt(vcpu, &dt);
4891}
4892
4893void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4894{
89a27f4d 4895 struct desc_ptr dt = { limit, base };
8776e519
HB		 4896
4897 kvm_x86_ops->set_idt(vcpu, &dt);
4898}
4899
07716717
DK		 4900static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4901{
ad312c7c
ZX		 4902 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4903 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4904
4905 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4906 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4907 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4908 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4909 if (ej->function == e->function) {
4910 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4911 return j;
4912 }
4913 }
4914 return 0; /* silence gcc, even though control never reaches here */
4915}
4916
4917/* find an entry with matching function, matching index (if needed), and that
4918 * should be read next (if it's stateful) */
4919static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4920 u32 function, u32 index)
4921{
4922 if (e->function != function)
4923 return 0;
4924 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4925 return 0;
4926 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4927 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4928 return 0;
4929 return 1;
4930}
4931
d8017474
AG		 4932struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4933 u32 function, u32 index)
8776e519
HB		 4934{
4935 int i;
d8017474 4936 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4937
ad312c7c 4938 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4939 struct kvm_cpuid_entry2 *e;
4940
ad312c7c 4941 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4942 if (is_matching_cpuid_entry(e, function, index)) {
4943 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4944 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4945 best = e;
4946 break;
4947 }
4948 /*
4949 * Both basic or both extended?
4950 */
4951 if (((e->function ^ function) & 0x80000000) == 0)
4952 if (!best || e->function > best->function)
4953 best = e;
4954 }
d8017474
AG		 4955 return best;
4956}
0e851880 4957EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4958
82725b20
DE		 4959int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4960{
4961 struct kvm_cpuid_entry2 *best;
4962
f7a71197
AK		 4963 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4964 if (!best || best->eax < 0x80000008)
4965 goto not_found;
82725b20
DE		 4966 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4967 if (best)
4968 return best->eax & 0xff;
f7a71197 4969not_found:
82725b20
DE		 4970 return 36;
4971}
4972
d8017474
AG		 4973void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4974{
4975 u32 function, index;
4976 struct kvm_cpuid_entry2 *best;
4977
4978 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4979 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4980 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4981 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4982 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4983 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4984 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4985 if (best) {
5fdbf976
MT		 4986 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4987 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4988 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4989 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4990 }
8776e519 4991 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4992 trace_kvm_cpuid(function,
4993 kvm_register_read(vcpu, VCPU_REGS_RAX),
4994 kvm_register_read(vcpu, VCPU_REGS_RBX),
4995 kvm_register_read(vcpu, VCPU_REGS_RCX),
4996 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4997}
4998EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4999
b6c7a5dc
HB		 5000/*
5001 * Check if userspace requested an interrupt window, and that the
5002 * interrupt window is open.
5003 *
5004 * No need to exit to userspace if we already have an interrupt queued.
5005 */
851ba692 5006static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5007{
8061823a 5008 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5009 vcpu->run->request_interrupt_window &&
5df56646 5010 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5011}
5012
851ba692 5013static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5014{
851ba692
AK		 5015 struct kvm_run *kvm_run = vcpu->run;
5016
91586a3b 5017 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5018 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5019 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5020 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5021 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5022 else
b6c7a5dc 5023 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5024 kvm_arch_interrupt_allowed(vcpu) &&
5025 !kvm_cpu_has_interrupt(vcpu) &&
5026 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5027}
5028
b93463aa
AK		 5029static void vapic_enter(struct kvm_vcpu *vcpu)
5030{
5031 struct kvm_lapic *apic = vcpu->arch.apic;
5032 struct page *page;
5033
5034 if (!apic || !apic->vapic_addr)
5035 return;
5036
5037 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 5038
5039 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 5040}
5041
5042static void vapic_exit(struct kvm_vcpu *vcpu)
5043{
5044 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5045 int idx;
b93463aa
AK		 5046
5047 if (!apic || !apic->vapic_addr)
5048 return;
5049
f656ce01 5050 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5051 kvm_release_page_dirty(apic->vapic_page);
5052 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5053 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5054}
5055
95ba8273
GN		 5056static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5057{
5058 int max_irr, tpr;
5059
5060 if (!kvm_x86_ops->update_cr8_intercept)
5061 return;
5062
88c808fd
AK		 5063 if (!vcpu->arch.apic)
5064 return;
5065
8db3baa2
GN		 5066 if (!vcpu->arch.apic->vapic_addr)
5067 max_irr = kvm_lapic_find_highest_irr(vcpu);
5068 else
5069 max_irr = -1;
95ba8273
GN		 5070
5071 if (max_irr != -1)
5072 max_irr >>= 4;
5073
5074 tpr = kvm_lapic_get_cr8(vcpu);
5075
5076 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5077}
5078
851ba692 5079static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5080{
5081 /* try to reinject previous events if any */
b59bb7bd 5082 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5083 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5084 vcpu->arch.exception.has_error_code,
5085 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5086 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5087 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5088 vcpu->arch.exception.error_code,
5089 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5090 return;
5091 }
5092
95ba8273
GN		 5093 if (vcpu->arch.nmi_injected) {
5094 kvm_x86_ops->set_nmi(vcpu);
5095 return;
5096 }
5097
5098 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5099 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5100 return;
5101 }
5102
5103 /* try to inject new event if pending */
5104 if (vcpu->arch.nmi_pending) {
5105 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5106 vcpu->arch.nmi_pending = false;
5107 vcpu->arch.nmi_injected = true;
5108 kvm_x86_ops->set_nmi(vcpu);
5109 }
5110 } else if (kvm_cpu_has_interrupt(vcpu)) {
5111 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5112 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5113 false);
5114 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5115 }
5116 }
5117}
5118
2acf923e
DC		 5119static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5120{
5121 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5122 !vcpu->guest_xcr0_loaded) {
5123 /* kvm_set_xcr() also depends on this */
5124 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5125 vcpu->guest_xcr0_loaded = 1;
5126 }
5127}
5128
5129static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5130{
5131 if (vcpu->guest_xcr0_loaded) {
5132 if (vcpu->arch.xcr0 != host_xcr0)
5133 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5134 vcpu->guest_xcr0_loaded = 0;
5135 }
5136}
5137
851ba692 5138static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5139{
5140 int r;
6a8b1d13 5141 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5142 vcpu->run->request_interrupt_window;
b6c7a5dc 5143
3e007509 5144 if (vcpu->requests) {
a8eeb04a 5145 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5146 kvm_mmu_unload(vcpu);
a8eeb04a 5147 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5148 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5149 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5150 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5151 if (unlikely(r))
5152 goto out;
5153 }
a8eeb04a 5154 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5155 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5156 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5157 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5158 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5159 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5160 r = 0;
5161 goto out;
5162 }
a8eeb04a 5163 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5164 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5165 r = 0;
5166 goto out;
5167 }
a8eeb04a 5168 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5169 vcpu->fpu_active = 0;
5170 kvm_x86_ops->fpu_deactivate(vcpu);
5171 }
af585b92
GN		 5172 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5173 /* Page is swapped out. Do synthetic halt */
5174 vcpu->arch.apf.halted = true;
5175 r = 1;
5176 goto out;
5177 }
2f52d58c 5178 }
b93463aa 5179
3e007509
AK		 5180 r = kvm_mmu_reload(vcpu);
5181 if (unlikely(r))
5182 goto out;
5183
b463a6f7
AK		 5184 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5185 inject_pending_event(vcpu);
5186
5187 /* enable NMI/IRQ window open exits if needed */
5188 if (vcpu->arch.nmi_pending)
5189 kvm_x86_ops->enable_nmi_window(vcpu);
5190 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5191 kvm_x86_ops->enable_irq_window(vcpu);
5192
5193 if (kvm_lapic_enabled(vcpu)) {
5194 update_cr8_intercept(vcpu);
5195 kvm_lapic_sync_to_vapic(vcpu);
5196 }
5197 }
5198
b6c7a5dc
HB		 5199 preempt_disable();
5200
5201 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5202 if (vcpu->fpu_active)
5203 kvm_load_guest_fpu(vcpu);
2acf923e 5204 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5205
d94e1dc9
AK		 5206 atomic_set(&vcpu->guest_mode, 1);
5207 smp_wmb();
b6c7a5dc 5208
d94e1dc9 5209 local_irq_disable();
32f88400 5210
d94e1dc9
AK		 5211 if (!atomic_read(&vcpu->guest_mode) || vcpu->requests
5212 || need_resched() || signal_pending(current)) {
5213 atomic_set(&vcpu->guest_mode, 0);
5214 smp_wmb();
6c142801
AK		 5215 local_irq_enable();
5216 preempt_enable();
b463a6f7 5217 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5218 r = 1;
5219 goto out;
5220 }
5221
f656ce01 5222 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5223
b6c7a5dc
HB		 5224 kvm_guest_enter();
5225
42dbaa5a 5226 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5227 set_debugreg(0, 7);
5228 set_debugreg(vcpu->arch.eff_db[0], 0);
5229 set_debugreg(vcpu->arch.eff_db[1], 1);
5230 set_debugreg(vcpu->arch.eff_db[2], 2);
5231 set_debugreg(vcpu->arch.eff_db[3], 3);
5232 }
b6c7a5dc 5233
229456fc 5234 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5235 kvm_x86_ops->run(vcpu);
b6c7a5dc 5236
24f1e32c
FW		 5237 /*
5238 * If the guest has used debug registers, at least dr7
5239 * will be disabled while returning to the host.
5240 * If we don't have active breakpoints in the host, we don't
5241 * care about the messed up debug address registers. But if
5242 * we have some of them active, restore the old state.
5243 */
59d8eb53 5244 if (hw_breakpoint_active())
24f1e32c 5245 hw_breakpoint_restore();
42dbaa5a 5246
1d5f066e
ZA		 5247 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5248
d94e1dc9
AK		 5249 atomic_set(&vcpu->guest_mode, 0);
5250 smp_wmb();
b6c7a5dc
HB		 5251 local_irq_enable();
5252
5253 ++vcpu->stat.exits;
5254
5255 /*
5256 * We must have an instruction between local_irq_enable() and
5257 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5258 * the interrupt shadow. The stat.exits increment will do nicely.
5259 * But we need to prevent reordering, hence this barrier():
5260 */
5261 barrier();
5262
5263 kvm_guest_exit();
5264
5265 preempt_enable();
5266
f656ce01 5267 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5268
b6c7a5dc
HB		 5269 /*
5270 * Profile KVM exit RIPs:
5271 */
5272 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5273 unsigned long rip = kvm_rip_read(vcpu);
5274 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5275 }
5276
298101da 5277
b93463aa
AK		 5278 kvm_lapic_sync_from_vapic(vcpu);
5279
851ba692 5280 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5281out:
5282 return r;
5283}
b6c7a5dc 5284
09cec754 5285
851ba692 5286static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5287{
5288 int r;
f656ce01 5289 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5290
5291 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5292 pr_debug("vcpu %d received sipi with vector # %x\n",
5293 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5294 kvm_lapic_reset(vcpu);
5f179287 5295 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5296 if (r)
5297 return r;
5298 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5299 }
5300
f656ce01 5301 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5302 vapic_enter(vcpu);
5303
5304 r = 1;
5305 while (r > 0) {
af585b92
GN		 5306 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5307 !vcpu->arch.apf.halted)
851ba692 5308 r = vcpu_enter_guest(vcpu);
d7690175 5309 else {
f656ce01 5310 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5311 kvm_vcpu_block(vcpu);
f656ce01 5312 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5313 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5314 {
5315 switch(vcpu->arch.mp_state) {
5316 case KVM_MP_STATE_HALTED:
d7690175 5317 vcpu->arch.mp_state =
09cec754
GN		 5318 KVM_MP_STATE_RUNNABLE;
5319 case KVM_MP_STATE_RUNNABLE:
af585b92 5320 vcpu->arch.apf.halted = false;
09cec754
GN		 5321 break;
5322 case KVM_MP_STATE_SIPI_RECEIVED:
5323 default:
5324 r = -EINTR;
5325 break;
5326 }
5327 }
d7690175
MT		 5328 }
5329
09cec754
GN		 5330 if (r <= 0)
5331 break;
5332
5333 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5334 if (kvm_cpu_has_pending_timer(vcpu))
5335 kvm_inject_pending_timer_irqs(vcpu);
5336
851ba692 5337 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5338 r = -EINTR;
851ba692 5339 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5340 ++vcpu->stat.request_irq_exits;
5341 }
af585b92
GN		 5342
5343 kvm_check_async_pf_completion(vcpu);
5344
09cec754
GN		 5345 if (signal_pending(current)) {
5346 r = -EINTR;
851ba692 5347 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5348 ++vcpu->stat.signal_exits;
5349 }
5350 if (need_resched()) {
f656ce01 5351 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5352 kvm_resched(vcpu);
f656ce01 5353 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5354 }
b6c7a5dc
HB		 5355 }
5356
f656ce01 5357 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5358
b93463aa
AK		 5359 vapic_exit(vcpu);
5360
b6c7a5dc
HB		 5361 return r;
5362}
5363
5364int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5365{
5366 int r;
5367 sigset_t sigsaved;
5368
ac9f6dc0
AK		 5369 if (vcpu->sigset_active)
5370 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5371
a4535290 5372 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5373 kvm_vcpu_block(vcpu);
d7690175 5374 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5375 r = -EAGAIN;
5376 goto out;
b6c7a5dc
HB		 5377 }
5378
b6c7a5dc
HB		 5379 /* re-sync apic's tpr */
5380 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 5381 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 5382
d2ddd1c4 5383 if (vcpu->arch.pio.count || vcpu->mmio_needed) {
92bf9748
GN		 5384 if (vcpu->mmio_needed) {
5385 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
5386 vcpu->mmio_read_completed = 1;
5387 vcpu->mmio_needed = 0;
b6c7a5dc 5388 }
f656ce01 5389 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5cd21917 5390 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
f656ce01 5391 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6d77dbfc 5392 if (r != EMULATE_DONE) {
b6c7a5dc
HB		 5393 r = 0;
5394 goto out;
5395 }
5396 }
5fdbf976
MT		 5397 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5398 kvm_register_write(vcpu, VCPU_REGS_RAX,
5399 kvm_run->hypercall.ret);
b6c7a5dc 5400
851ba692 5401 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5402
5403out:
f1d86e46 5404 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5405 if (vcpu->sigset_active)
5406 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5407
b6c7a5dc
HB		 5408 return r;
5409}
5410
5411int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5412{
5fdbf976
MT		 5413 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5414 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5415 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5416 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5417 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5418 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5419 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5420 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5421#ifdef CONFIG_X86_64
5fdbf976
MT		 5422 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5423 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5424 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5425 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5426 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5427 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5428 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5429 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5430#endif
5431
5fdbf976 5432 regs->rip = kvm_rip_read(vcpu);
91586a3b 5433 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5434
b6c7a5dc
HB		 5435 return 0;
5436}
5437
5438int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5439{
5fdbf976
MT		 5440 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5441 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5442 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5443 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5444 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5445 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5446 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5447 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5448#ifdef CONFIG_X86_64
5fdbf976
MT		 5449 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5450 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5451 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5452 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5453 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5454 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5455 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5456 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5457#endif
5458
5fdbf976 5459 kvm_rip_write(vcpu, regs->rip);
91586a3b 5460 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5461
b4f14abd
JK		 5462 vcpu->arch.exception.pending = false;
5463
3842d135
AK		 5464 kvm_make_request(KVM_REQ_EVENT, vcpu);
5465
b6c7a5dc
HB		 5466 return 0;
5467}
5468
b6c7a5dc
HB		 5469void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5470{
5471 struct kvm_segment cs;
5472
3e6e0aab 5473 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5474 *db = cs.db;
5475 *l = cs.l;
5476}
5477EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5478
5479int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5480 struct kvm_sregs *sregs)
5481{
89a27f4d 5482 struct desc_ptr dt;
b6c7a5dc 5483
3e6e0aab
GT		 5484 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5485 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5486 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5487 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5488 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5489 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5490
3e6e0aab
GT		 5491 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5492 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5493
5494 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5495 sregs->idt.limit = dt.size;
5496 sregs->idt.base = dt.address;
b6c7a5dc 5497 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5498 sregs->gdt.limit = dt.size;
5499 sregs->gdt.base = dt.address;
b6c7a5dc 5500
4d4ec087 5501 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 5502 sregs->cr2 = vcpu->arch.cr2;
5503 sregs->cr3 = vcpu->arch.cr3;
fc78f519 5504 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5505 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5506 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5507 sregs->apic_base = kvm_get_apic_base(vcpu);
5508
923c61bb 5509 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5510
36752c9b 5511 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5512 set_bit(vcpu->arch.interrupt.nr,
5513 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5514
b6c7a5dc
HB		 5515 return 0;
5516}
5517
62d9f0db
MT		 5518int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5519 struct kvm_mp_state *mp_state)
5520{
62d9f0db 5521 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5522 return 0;
5523}
5524
5525int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5526 struct kvm_mp_state *mp_state)
5527{
62d9f0db 5528 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5529 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5530 return 0;
5531}
5532
e269fb21
JK		 5533int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5534 bool has_error_code, u32 error_code)
b6c7a5dc 5535{
4d2179e1 5536 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
8ec4722d 5537 int ret;
e01c2426 5538
8ec4722d 5539 init_emulate_ctxt(vcpu);
c697518a 5540
9aabc88f 5541 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt,
e269fb21
JK		 5542 tss_selector, reason, has_error_code,
5543 error_code);
c697518a 5544
c697518a 5545 if (ret)
19d04437 5546 return EMULATE_FAIL;
37817f29 5547
4d2179e1 5548 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 5549 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
19d04437 5550 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 5551 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5552 return EMULATE_DONE;
37817f29
IE		 5553}
5554EXPORT_SYMBOL_GPL(kvm_task_switch);
5555
b6c7a5dc
HB		 5556int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5557 struct kvm_sregs *sregs)
5558{
5559 int mmu_reset_needed = 0;
923c61bb 5560 int pending_vec, max_bits;
89a27f4d 5561 struct desc_ptr dt;
b6c7a5dc 5562
89a27f4d
GN		 5563 dt.size = sregs->idt.limit;
5564 dt.address = sregs->idt.base;
b6c7a5dc 5565 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5566 dt.size = sregs->gdt.limit;
5567 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5568 kvm_x86_ops->set_gdt(vcpu, &dt);
5569
ad312c7c
ZX		 5570 vcpu->arch.cr2 = sregs->cr2;
5571 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5572 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5573
2d3ad1f4 5574 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5575
f6801dff 5576 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5577 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5578 kvm_set_apic_base(vcpu, sregs->apic_base);
5579
4d4ec087 5580 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5581 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5582 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5583
fc78f519 5584 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5585 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c
SY		 5586 if (sregs->cr4 & X86_CR4_OSXSAVE)
5587 update_cpuid(vcpu);
7c93be44 5588 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ff03a073 5589 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
7c93be44
MT		 5590 mmu_reset_needed = 1;
5591 }
b6c7a5dc
HB		 5592
5593 if (mmu_reset_needed)
5594 kvm_mmu_reset_context(vcpu);
5595
923c61bb
GN		 5596 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5597 pending_vec = find_first_bit(
5598 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5599 if (pending_vec < max_bits) {
66fd3f7f 5600 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5601 pr_debug("Set back pending irq %d\n", pending_vec);
5602 if (irqchip_in_kernel(vcpu->kvm))
5603 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5604 }
5605
3e6e0aab
GT		 5606 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5607 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5608 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5609 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5610 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5611 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5612
3e6e0aab
GT		 5613 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5614 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5615
5f0269f5
ME		 5616 update_cr8_intercept(vcpu);
5617
9c3e4aab 5618 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5619 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5620 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5621 !is_protmode(vcpu))
9c3e4aab
MT		 5622 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5623
3842d135
AK		 5624 kvm_make_request(KVM_REQ_EVENT, vcpu);
5625
b6c7a5dc
HB		 5626 return 0;
5627}
5628
d0bfb940
JK		 5629int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5630 struct kvm_guest_debug *dbg)
b6c7a5dc 5631{
355be0b9 5632 unsigned long rflags;
ae675ef0 5633 int i, r;
b6c7a5dc 5634
4f926bf2
JK		 5635 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5636 r = -EBUSY;
5637 if (vcpu->arch.exception.pending)
2122ff5e 5638 goto out;
4f926bf2
JK		 5639 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5640 kvm_queue_exception(vcpu, DB_VECTOR);
5641 else
5642 kvm_queue_exception(vcpu, BP_VECTOR);
5643 }
5644
91586a3b
JK		 5645 /*
5646 * Read rflags as long as potentially injected trace flags are still
5647 * filtered out.
5648 */
5649 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5650
5651 vcpu->guest_debug = dbg->control;
5652 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5653 vcpu->guest_debug = 0;
5654
5655 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5656 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5657 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5658 vcpu->arch.switch_db_regs =
5659 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5660 } else {
5661 for (i = 0; i < KVM_NR_DB_REGS; i++)
5662 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5663 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5664 }
5665
f92653ee
JK		 5666 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5667 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5668 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5669
91586a3b
JK		 5670 /*
5671 * Trigger an rflags update that will inject or remove the trace
5672 * flags.
5673 */
5674 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5675
355be0b9 5676 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5677
4f926bf2 5678 r = 0;
d0bfb940 5679
2122ff5e 5680out:
b6c7a5dc
HB		 5681
5682 return r;
5683}
5684
8b006791
ZX		 5685/*
5686 * Translate a guest virtual address to a guest physical address.
5687 */
5688int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5689 struct kvm_translation *tr)
5690{
5691 unsigned long vaddr = tr->linear_address;
5692 gpa_t gpa;
f656ce01 5693 int idx;
8b006791 5694
f656ce01 5695 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5696 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5697 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5698 tr->physical_address = gpa;
5699 tr->valid = gpa != UNMAPPED_GVA;
5700 tr->writeable = 1;
5701 tr->usermode = 0;
8b006791
ZX		 5702
5703 return 0;
5704}
5705
d0752060
HB		 5706int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5707{
98918833
SY		 5708 struct i387_fxsave_struct *fxsave =
5709 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5710
d0752060
HB		 5711 memcpy(fpu->fpr, fxsave->st_space, 128);
5712 fpu->fcw = fxsave->cwd;
5713 fpu->fsw = fxsave->swd;
5714 fpu->ftwx = fxsave->twd;
5715 fpu->last_opcode = fxsave->fop;
5716 fpu->last_ip = fxsave->rip;
5717 fpu->last_dp = fxsave->rdp;
5718 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5719
d0752060
HB		 5720 return 0;
5721}
5722
5723int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5724{
98918833
SY		 5725 struct i387_fxsave_struct *fxsave =
5726 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5727
d0752060
HB		 5728 memcpy(fxsave->st_space, fpu->fpr, 128);
5729 fxsave->cwd = fpu->fcw;
5730 fxsave->swd = fpu->fsw;
5731 fxsave->twd = fpu->ftwx;
5732 fxsave->fop = fpu->last_opcode;
5733 fxsave->rip = fpu->last_ip;
5734 fxsave->rdp = fpu->last_dp;
5735 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5736
d0752060
HB		 5737 return 0;
5738}
5739
10ab25cd 5740int fx_init(struct kvm_vcpu *vcpu)
d0752060 5741{
10ab25cd
JK		 5742 int err;
5743
5744 err = fpu_alloc(&vcpu->arch.guest_fpu);
5745 if (err)
5746 return err;
5747
98918833 5748 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5749
2acf923e
DC		 5750 /*
5751 * Ensure guest xcr0 is valid for loading
5752 */
5753 vcpu->arch.xcr0 = XSTATE_FP;
5754
ad312c7c 5755 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5756
5757 return 0;
d0752060
HB		 5758}
5759EXPORT_SYMBOL_GPL(fx_init);
5760
98918833
SY		 5761static void fx_free(struct kvm_vcpu *vcpu)
5762{
5763 fpu_free(&vcpu->arch.guest_fpu);
5764}
5765
d0752060
HB		 5766void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5767{
2608d7a1 5768 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5769 return;
5770
2acf923e
DC		 5771 /*
5772 * Restore all possible states in the guest,
5773 * and assume host would use all available bits.
5774 * Guest xcr0 would be loaded later.
5775 */
5776 kvm_put_guest_xcr0(vcpu);
d0752060 5777 vcpu->guest_fpu_loaded = 1;
7cf30855 5778 unlazy_fpu(current);
98918833 5779 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5780 trace_kvm_fpu(1);
d0752060 5781}
d0752060
HB		 5782
5783void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5784{
2acf923e
DC		 5785 kvm_put_guest_xcr0(vcpu);
5786
d0752060
HB		 5787 if (!vcpu->guest_fpu_loaded)
5788 return;
5789
5790 vcpu->guest_fpu_loaded = 0;
98918833 5791 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5792 ++vcpu->stat.fpu_reload;
a8eeb04a 5793 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5794 trace_kvm_fpu(0);
d0752060 5795}
e9b11c17
ZX		 5796
5797void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5798{
7f1ea208
JR		 5799 if (vcpu->arch.time_page) {
5800 kvm_release_page_dirty(vcpu->arch.time_page);
5801 vcpu->arch.time_page = NULL;
5802 }
5803
f5f48ee1 5804 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5805 fx_free(vcpu);
e9b11c17
ZX		 5806 kvm_x86_ops->vcpu_free(vcpu);
5807}
5808
5809struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5810 unsigned int id)
5811{
6755bae8
ZA		 5812 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5813 printk_once(KERN_WARNING
5814 "kvm: SMP vm created on host with unstable TSC; "
5815 "guest TSC will not be reliable\n");
26e5215f
AK		 5816 return kvm_x86_ops->vcpu_create(kvm, id);
5817}
e9b11c17 5818
26e5215f
AK		 5819int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5820{
5821 int r;
e9b11c17 5822
0bed3b56 5823 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5824 vcpu_load(vcpu);
5825 r = kvm_arch_vcpu_reset(vcpu);
5826 if (r == 0)
5827 r = kvm_mmu_setup(vcpu);
5828 vcpu_put(vcpu);
5829 if (r < 0)
5830 goto free_vcpu;
5831
26e5215f 5832 return 0;
e9b11c17
ZX		 5833free_vcpu:
5834 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5835 return r;
e9b11c17
ZX		 5836}
5837
d40ccc62 5838void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 5839{
344d9588
GN		 5840 vcpu->arch.apf.msr_val = 0;
5841
e9b11c17
ZX		 5842 vcpu_load(vcpu);
5843 kvm_mmu_unload(vcpu);
5844 vcpu_put(vcpu);
5845
98918833 5846 fx_free(vcpu);
e9b11c17
ZX		 5847 kvm_x86_ops->vcpu_free(vcpu);
5848}
5849
5850int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5851{
448fa4a9
JK		 5852 vcpu->arch.nmi_pending = false;
5853 vcpu->arch.nmi_injected = false;
5854
42dbaa5a
JK		 5855 vcpu->arch.switch_db_regs = 0;
5856 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5857 vcpu->arch.dr6 = DR6_FIXED_1;
5858 vcpu->arch.dr7 = DR7_FIXED_1;
5859
3842d135 5860 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 5861 vcpu->arch.apf.msr_val = 0;
3842d135 5862
af585b92
GN		 5863 kvm_clear_async_pf_completion_queue(vcpu);
5864 kvm_async_pf_hash_reset(vcpu);
5865 vcpu->arch.apf.halted = false;
5866
e9b11c17
ZX		 5867 return kvm_x86_ops->vcpu_reset(vcpu);
5868}
5869
10474ae8 5870int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5871{
ca84d1a2
ZA		 5872 struct kvm *kvm;
5873 struct kvm_vcpu *vcpu;
5874 int i;
18863bdd
AK		 5875
5876 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 5877 list_for_each_entry(kvm, &vm_list, vm_list)
5878 kvm_for_each_vcpu(i, vcpu, kvm)
5879 if (vcpu->cpu == smp_processor_id())
c285545f 5880 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10474ae8 5881 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5882}
5883
5884void kvm_arch_hardware_disable(void *garbage)
5885{
5886 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5887 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5888}
5889
5890int kvm_arch_hardware_setup(void)
5891{
5892 return kvm_x86_ops->hardware_setup();
5893}
5894
5895void kvm_arch_hardware_unsetup(void)
5896{
5897 kvm_x86_ops->hardware_unsetup();
5898}
5899
5900void kvm_arch_check_processor_compat(void *rtn)
5901{
5902 kvm_x86_ops->check_processor_compatibility(rtn);
5903}
5904
5905int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5906{
5907 struct page *page;
5908 struct kvm *kvm;
5909 int r;
5910
5911 BUG_ON(vcpu->kvm == NULL);
5912 kvm = vcpu->kvm;
5913
9aabc88f 5914 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
14dfe855 5915 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
ad312c7c 5916 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c30a358d 5917 vcpu->arch.mmu.translate_gpa = translate_gpa;
02f59dc9 5918 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
c5af89b6 5919 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5920 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5921 else
a4535290 5922 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5923
5924 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5925 if (!page) {
5926 r = -ENOMEM;
5927 goto fail;
5928 }
ad312c7c 5929 vcpu->arch.pio_data = page_address(page);
e9b11c17 5930
c285545f
ZA		 5931 if (!kvm->arch.virtual_tsc_khz)
5932 kvm_arch_set_tsc_khz(kvm, max_tsc_khz);
5933
e9b11c17
ZX		 5934 r = kvm_mmu_create(vcpu);
5935 if (r < 0)
5936 goto fail_free_pio_data;
5937
5938 if (irqchip_in_kernel(kvm)) {
5939 r = kvm_create_lapic(vcpu);
5940 if (r < 0)
5941 goto fail_mmu_destroy;
5942 }
5943
890ca9ae
HY		 5944 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5945 GFP_KERNEL);
5946 if (!vcpu->arch.mce_banks) {
5947 r = -ENOMEM;
443c39bc 5948 goto fail_free_lapic;
890ca9ae
HY		 5949 }
5950 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5951
f5f48ee1
SY		 5952 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
5953 goto fail_free_mce_banks;
5954
af585b92
GN		 5955 kvm_async_pf_hash_reset(vcpu);
5956
e9b11c17 5957 return 0;
f5f48ee1
SY		 5958fail_free_mce_banks:
5959 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 5960fail_free_lapic:
5961 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5962fail_mmu_destroy:
5963 kvm_mmu_destroy(vcpu);
5964fail_free_pio_data:
ad312c7c 5965 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5966fail:
5967 return r;
5968}
5969
5970void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5971{
f656ce01
MT		 5972 int idx;
5973
36cb93fd 5974 kfree(vcpu->arch.mce_banks);
e9b11c17 5975 kvm_free_lapic(vcpu);
f656ce01 5976 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5977 kvm_mmu_destroy(vcpu);
f656ce01 5978 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5979 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5980}
d19a9cd2 5981
d89f5eff 5982int kvm_arch_init_vm(struct kvm *kvm)
d19a9cd2 5983{
f05e70ac 5984 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5985 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5986
5550af4d
SY		 5987 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5988 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5989
99e3e30a 5990 spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 5991
d89f5eff 5992 return 0;
d19a9cd2
ZX		 5993}
5994
5995static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5996{
5997 vcpu_load(vcpu);
5998 kvm_mmu_unload(vcpu);
5999 vcpu_put(vcpu);
6000}
6001
6002static void kvm_free_vcpus(struct kvm *kvm)
6003{
6004 unsigned int i;
988a2cae 6005 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6006
6007 /*
6008 * Unpin any mmu pages first.
6009 */
af585b92
GN		 6010 kvm_for_each_vcpu(i, vcpu, kvm) {
6011 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6012 kvm_unload_vcpu_mmu(vcpu);
af585b92 6013 }
988a2cae
GN		 6014 kvm_for_each_vcpu(i, vcpu, kvm)
6015 kvm_arch_vcpu_free(vcpu);
6016
6017 mutex_lock(&kvm->lock);
6018 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6019 kvm->vcpus[i] = NULL;
d19a9cd2 6020
988a2cae
GN		 6021 atomic_set(&kvm->online_vcpus, 0);
6022 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6023}
6024
ad8ba2cd
SY		 6025void kvm_arch_sync_events(struct kvm *kvm)
6026{
ba4cef31 6027 kvm_free_all_assigned_devices(kvm);
aea924f6 6028 kvm_free_pit(kvm);
ad8ba2cd
SY		 6029}
6030
d19a9cd2
ZX		 6031void kvm_arch_destroy_vm(struct kvm *kvm)
6032{
6eb55818 6033 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6034 kfree(kvm->arch.vpic);
6035 kfree(kvm->arch.vioapic);
d19a9cd2 6036 kvm_free_vcpus(kvm);
3d45830c
AK		 6037 if (kvm->arch.apic_access_page)
6038 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6039 if (kvm->arch.ept_identity_pagetable)
6040 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2 6041}
0de10343 6042
f7784b8e
MT		 6043int kvm_arch_prepare_memory_region(struct kvm *kvm,
6044 struct kvm_memory_slot *memslot,
0de10343 6045 struct kvm_memory_slot old,
f7784b8e 6046 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6047 int user_alloc)
6048{
f7784b8e 6049 int npages = memslot->npages;
7ac77099
AK		 6050 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6051
6052 /* Prevent internal slot pages from being moved by fork()/COW. */
6053 if (memslot->id >= KVM_MEMORY_SLOTS)
6054 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6055
6056 /*To keep backward compatibility with older userspace,
6057 *x86 needs to hanlde !user_alloc case.
6058 */
6059 if (!user_alloc) {
6060 if (npages && !old.rmap) {
604b38ac
AA		 6061 unsigned long userspace_addr;
6062
72dc67a6 6063 down_write(&current->mm->mmap_sem);
604b38ac
AA		 6064 userspace_addr = do_mmap(NULL, 0,
6065 npages * PAGE_SIZE,
6066 PROT_READ | PROT_WRITE,
7ac77099 6067 map_flags,
604b38ac 6068 0);
72dc67a6 6069 up_write(&current->mm->mmap_sem);
0de10343 6070
604b38ac
AA		 6071 if (IS_ERR((void *)userspace_addr))
6072 return PTR_ERR((void *)userspace_addr);
6073
604b38ac 6074 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6075 }
6076 }
6077
f7784b8e
MT		 6078
6079 return 0;
6080}
6081
6082void kvm_arch_commit_memory_region(struct kvm *kvm,
6083 struct kvm_userspace_memory_region *mem,
6084 struct kvm_memory_slot old,
6085 int user_alloc)
6086{
6087
6088 int npages = mem->memory_size >> PAGE_SHIFT;
6089
6090 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6091 int ret;
6092
6093 down_write(&current->mm->mmap_sem);
6094 ret = do_munmap(current->mm, old.userspace_addr,
6095 old.npages * PAGE_SIZE);
6096 up_write(&current->mm->mmap_sem);
6097 if (ret < 0)
6098 printk(KERN_WARNING
6099 "kvm_vm_ioctl_set_memory_region: "
6100 "failed to munmap memory\n");
6101 }
6102
7c8a83b7 6103 spin_lock(&kvm->mmu_lock);
f05e70ac 6104 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 6105 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6106 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
6107 }
6108
6109 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6110 spin_unlock(&kvm->mmu_lock);
0de10343 6111}
1d737c8a 6112
34d4cb8f
MT		 6113void kvm_arch_flush_shadow(struct kvm *kvm)
6114{
6115 kvm_mmu_zap_all(kvm);
8986ecc0 6116 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6117}
6118
1d737c8a
ZX		 6119int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6120{
af585b92
GN		 6121 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6122 !vcpu->arch.apf.halted)
6123 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100
GN		 6124 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6125 || vcpu->arch.nmi_pending ||
6126 (kvm_arch_interrupt_allowed(vcpu) &&
6127 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6128}
5736199a 6129
5736199a
ZX		 6130void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6131{
32f88400
MT		 6132 int me;
6133 int cpu = vcpu->cpu;
5736199a
ZX		 6134
6135 if (waitqueue_active(&vcpu->wq)) {
6136 wake_up_interruptible(&vcpu->wq);
6137 ++vcpu->stat.halt_wakeup;
6138 }
32f88400
MT		 6139
6140 me = get_cpu();
6141 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
d94e1dc9 6142 if (atomic_xchg(&vcpu->guest_mode, 0))
32f88400 6143 smp_send_reschedule(cpu);
e9571ed5 6144 put_cpu();
5736199a 6145}
78646121
GN		 6146
6147int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6148{
6149 return kvm_x86_ops->interrupt_allowed(vcpu);
6150}
229456fc 6151
f92653ee
JK		 6152bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6153{
6154 unsigned long current_rip = kvm_rip_read(vcpu) +
6155 get_segment_base(vcpu, VCPU_SREG_CS);
6156
6157 return current_rip == linear_rip;
6158}
6159EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6160
94fe45da
JK		 6161unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6162{
6163 unsigned long rflags;
6164
6165 rflags = kvm_x86_ops->get_rflags(vcpu);
6166 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6167 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6168 return rflags;
6169}
6170EXPORT_SYMBOL_GPL(kvm_get_rflags);
6171
6172void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6173{
6174 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6175 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6176 rflags |= X86_EFLAGS_TF;
94fe45da 6177 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6178 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6179}
6180EXPORT_SYMBOL_GPL(kvm_set_rflags);
6181
56028d08
GN		 6182void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6183{
6184 int r;
6185
fb67e14f 6186 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6187 is_error_page(work->page))
56028d08
GN		 6188 return;
6189
6190 r = kvm_mmu_reload(vcpu);
6191 if (unlikely(r))
6192 return;
6193
fb67e14f
XG		 6194 if (!vcpu->arch.mmu.direct_map &&
6195 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6196 return;
6197
56028d08
GN		 6198 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6199}
6200
af585b92
GN		 6201static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6202{
6203 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6204}
6205
6206static inline u32 kvm_async_pf_next_probe(u32 key)
6207{
6208 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6209}
6210
6211static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6212{
6213 u32 key = kvm_async_pf_hash_fn(gfn);
6214
6215 while (vcpu->arch.apf.gfns[key] != ~0)
6216 key = kvm_async_pf_next_probe(key);
6217
6218 vcpu->arch.apf.gfns[key] = gfn;
6219}
6220
6221static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6222{
6223 int i;
6224 u32 key = kvm_async_pf_hash_fn(gfn);
6225
6226 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6227 (vcpu->arch.apf.gfns[key] != gfn &&
6228 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6229 key = kvm_async_pf_next_probe(key);
6230
6231 return key;
6232}
6233
6234bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6235{
6236 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6237}
6238
6239static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6240{
6241 u32 i, j, k;
6242
6243 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6244 while (true) {
6245 vcpu->arch.apf.gfns[i] = ~0;
6246 do {
6247 j = kvm_async_pf_next_probe(j);
6248 if (vcpu->arch.apf.gfns[j] == ~0)
6249 return;
6250 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6251 /*
6252 * k lies cyclically in ]i,j]
6253 * | i.k.j |
6254 * |....j i.k.| or |.k..j i...|
6255 */
6256 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6257 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6258 i = j;
6259 }
6260}
6261
7c90705b
GN		 6262static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6263{
6264
6265 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6266 sizeof(val));
6267}
6268
af585b92
GN		 6269void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6270 struct kvm_async_pf *work)
6271{
6389ee94
AK		 6272 struct x86_exception fault;
6273
7c90705b 6274 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6275 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6276
6277 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6278 (vcpu->arch.apf.send_user_only &&
6279 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6280 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6281 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6282 fault.vector = PF_VECTOR;
6283 fault.error_code_valid = true;
6284 fault.error_code = 0;
6285 fault.nested_page_fault = false;
6286 fault.address = work->arch.token;
6287 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6288 }
af585b92
GN		 6289}
6290
6291void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6292 struct kvm_async_pf *work)
6293{
6389ee94
AK		 6294 struct x86_exception fault;
6295
7c90705b
GN		 6296 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6297 if (is_error_page(work->page))
6298 work->arch.token = ~0; /* broadcast wakeup */
6299 else
6300 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6301
6302 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6303 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6304 fault.vector = PF_VECTOR;
6305 fault.error_code_valid = true;
6306 fault.error_code = 0;
6307 fault.nested_page_fault = false;
6308 fault.address = work->arch.token;
6309 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6310 }
e6d53e3b 6311 vcpu->arch.apf.halted = false;
7c90705b
GN		 6312}
6313
6314bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6315{
6316 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6317 return true;
6318 else
6319 return !kvm_event_needs_reinjection(vcpu) &&
6320 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6321}
6322
229456fc
MT		 6323EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6324EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6325EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6326EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6327EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6328EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6329EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6330EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6331EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6332EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6333EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6334EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
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