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KVM: MMU: Inherit a shadow page's guest level count from vcpu setup
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
043405e1
CO		 39
40#include <asm/uaccess.h>
d825ed0a 41#include <asm/msr.h>
a5f61300 42#include <asm/desc.h>
0bed3b56 43#include <asm/mtrr.h>
043405e1 44
313a3dc7 45#define MAX_IO_MSRS 256
a03490ed
CO		 46#define CR0_RESERVED_BITS \
47 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
48 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
49 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
50#define CR4_RESERVED_BITS \
51 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
52 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
53 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
54 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
55
56#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
50a37eb4
JR		 57/* EFER defaults:
58 * - enable syscall per default because its emulated by KVM
59 * - enable LME and LMA per default on 64 bit KVM
60 */
61#ifdef CONFIG_X86_64
62static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
63#else
64static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
65#endif
313a3dc7 66
ba1389b7
AK		 67#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
68#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 69
674eea0f
AK		 70static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
71 struct kvm_cpuid_entry2 __user *entries);
d8017474
AG		 72struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
73 u32 function, u32 index);
674eea0f 74
97896d04 75struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 76EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 77
417bc304 78struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 79 { "pf_fixed", VCPU_STAT(pf_fixed) },
80 { "pf_guest", VCPU_STAT(pf_guest) },
81 { "tlb_flush", VCPU_STAT(tlb_flush) },
82 { "invlpg", VCPU_STAT(invlpg) },
83 { "exits", VCPU_STAT(exits) },
84 { "io_exits", VCPU_STAT(io_exits) },
85 { "mmio_exits", VCPU_STAT(mmio_exits) },
86 { "signal_exits", VCPU_STAT(signal_exits) },
87 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 88 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 89 { "halt_exits", VCPU_STAT(halt_exits) },
90 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 91 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7 92 { "request_irq", VCPU_STAT(request_irq_exits) },
c4abb7c9 93 { "request_nmi", VCPU_STAT(request_nmi_exits) },
ba1389b7
AK		 94 { "irq_exits", VCPU_STAT(irq_exits) },
95 { "host_state_reload", VCPU_STAT(host_state_reload) },
96 { "efer_reload", VCPU_STAT(efer_reload) },
97 { "fpu_reload", VCPU_STAT(fpu_reload) },
98 { "insn_emulation", VCPU_STAT(insn_emulation) },
99 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 100 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 101 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 102 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
103 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
104 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
105 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
106 { "mmu_flooded", VM_STAT(mmu_flooded) },
107 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 108 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 109 { "mmu_unsync", VM_STAT(mmu_unsync) },
6cffe8ca 110 { "mmu_unsync_global", VM_STAT(mmu_unsync_global) },
0f74a24c 111 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 112 { "largepages", VM_STAT(lpages) },
417bc304
HB		 113 { NULL }
114};
115
5fb76f9b
CO		 116unsigned long segment_base(u16 selector)
117{
118 struct descriptor_table gdt;
a5f61300 119 struct desc_struct *d;
5fb76f9b
CO		 120 unsigned long table_base;
121 unsigned long v;
122
123 if (selector == 0)
124 return 0;
125
126 asm("sgdt %0" : "=m"(gdt));
127 table_base = gdt.base;
128
129 if (selector & 4) { /* from ldt */
130 u16 ldt_selector;
131
132 asm("sldt %0" : "=g"(ldt_selector));
133 table_base = segment_base(ldt_selector);
134 }
a5f61300
AK		 135 d = (struct desc_struct *)(table_base + (selector & ~7));
136 v = d->base0 | ((unsigned long)d->base1 << 16) |
137 ((unsigned long)d->base2 << 24);
5fb76f9b 138#ifdef CONFIG_X86_64
a5f61300
AK		 139 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
140 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 141#endif
142 return v;
143}
144EXPORT_SYMBOL_GPL(segment_base);
145
6866b83e
CO		 146u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
147{
148 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 149 return vcpu->arch.apic_base;
6866b83e 150 else
ad312c7c 151 return vcpu->arch.apic_base;
6866b83e
CO		 152}
153EXPORT_SYMBOL_GPL(kvm_get_apic_base);
154
155void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
156{
157 /* TODO: reserve bits check */
158 if (irqchip_in_kernel(vcpu->kvm))
159 kvm_lapic_set_base(vcpu, data);
160 else
ad312c7c 161 vcpu->arch.apic_base = data;
6866b83e
CO		 162}
163EXPORT_SYMBOL_GPL(kvm_set_apic_base);
164
298101da
AK		 165void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
166{
ad312c7c
ZX		 167 WARN_ON(vcpu->arch.exception.pending);
168 vcpu->arch.exception.pending = true;
169 vcpu->arch.exception.has_error_code = false;
170 vcpu->arch.exception.nr = nr;
298101da
AK		 171}
172EXPORT_SYMBOL_GPL(kvm_queue_exception);
173
c3c91fee
AK		 174void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
175 u32 error_code)
176{
177 ++vcpu->stat.pf_guest;
d8017474 178
71c4dfaf
JR		 179 if (vcpu->arch.exception.pending) {
180 if (vcpu->arch.exception.nr == PF_VECTOR) {
181 printk(KERN_DEBUG "kvm: inject_page_fault:"
182 " double fault 0x%lx\n", addr);
183 vcpu->arch.exception.nr = DF_VECTOR;
184 vcpu->arch.exception.error_code = 0;
185 } else if (vcpu->arch.exception.nr == DF_VECTOR) {
186 /* triple fault -> shutdown */
187 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
188 }
c3c91fee
AK		 189 return;
190 }
ad312c7c 191 vcpu->arch.cr2 = addr;
c3c91fee
AK		 192 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
193}
194
3419ffc8
SY		 195void kvm_inject_nmi(struct kvm_vcpu *vcpu)
196{
197 vcpu->arch.nmi_pending = 1;
198}
199EXPORT_SYMBOL_GPL(kvm_inject_nmi);
200
298101da
AK		 201void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
202{
ad312c7c
ZX		 203 WARN_ON(vcpu->arch.exception.pending);
204 vcpu->arch.exception.pending = true;
205 vcpu->arch.exception.has_error_code = true;
206 vcpu->arch.exception.nr = nr;
207 vcpu->arch.exception.error_code = error_code;
298101da
AK		 208}
209EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
210
211static void __queue_exception(struct kvm_vcpu *vcpu)
212{
ad312c7c
ZX		 213 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
214 vcpu->arch.exception.has_error_code,
215 vcpu->arch.exception.error_code);
298101da
AK		 216}
217
a03490ed
CO		 218/*
219 * Load the pae pdptrs. Return true is they are all valid.
220 */
221int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
222{
223 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
224 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
225 int i;
226 int ret;
ad312c7c 227 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 228
a03490ed
CO		 229 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
230 offset * sizeof(u64), sizeof(pdpte));
231 if (ret < 0) {
232 ret = 0;
233 goto out;
234 }
235 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
236 if ((pdpte[i] & 1) && (pdpte[i] & 0xfffffff0000001e6ull)) {
237 ret = 0;
238 goto out;
239 }
240 }
241 ret = 1;
242
ad312c7c 243 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
a03490ed 244out:
a03490ed
CO		 245
246 return ret;
247}
cc4b6871 248EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 249
d835dfec
AK		 250static bool pdptrs_changed(struct kvm_vcpu *vcpu)
251{
ad312c7c 252 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 253 bool changed = true;
254 int r;
255
256 if (is_long_mode(vcpu) || !is_pae(vcpu))
257 return false;
258
ad312c7c 259 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 260 if (r < 0)
261 goto out;
ad312c7c 262 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 263out:
d835dfec
AK		 264
265 return changed;
266}
267
2d3ad1f4 268void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 269{
270 if (cr0 & CR0_RESERVED_BITS) {
271 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 272 cr0, vcpu->arch.cr0);
c1a5d4f9 273 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 274 return;
275 }
276
277 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
278 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 279 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 280 return;
281 }
282
283 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
284 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
285 "and a clear PE flag\n");
c1a5d4f9 286 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 287 return;
288 }
289
290 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
291#ifdef CONFIG_X86_64
ad312c7c 292 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 293 int cs_db, cs_l;
294
295 if (!is_pae(vcpu)) {
296 printk(KERN_DEBUG "set_cr0: #GP, start paging "
297 "in long mode while PAE is disabled\n");
c1a5d4f9 298 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 299 return;
300 }
301 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
302 if (cs_l) {
303 printk(KERN_DEBUG "set_cr0: #GP, start paging "
304 "in long mode while CS.L == 1\n");
c1a5d4f9 305 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 306 return;
307
308 }
309 } else
310#endif
ad312c7c 311 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 312 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
313 "reserved bits\n");
c1a5d4f9 314 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 315 return;
316 }
317
318 }
319
320 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 321 vcpu->arch.cr0 = cr0;
a03490ed 322
6cffe8ca 323 kvm_mmu_sync_global(vcpu);
a03490ed 324 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 325 return;
326}
2d3ad1f4 327EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 328
2d3ad1f4 329void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 330{
2d3ad1f4 331 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
2714d1d3
FEL		 332 KVMTRACE_1D(LMSW, vcpu,
333 (u32)((vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f)),
334 handler);
a03490ed 335}
2d3ad1f4 336EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 337
2d3ad1f4 338void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed
CO		 339{
340 if (cr4 & CR4_RESERVED_BITS) {
341 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 342 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 343 return;
344 }
345
346 if (is_long_mode(vcpu)) {
347 if (!(cr4 & X86_CR4_PAE)) {
348 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
349 "in long mode\n");
c1a5d4f9 350 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 351 return;
352 }
353 } else if (is_paging(vcpu) && !is_pae(vcpu) && (cr4 & X86_CR4_PAE)
ad312c7c 354 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 355 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 356 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 357 return;
358 }
359
360 if (cr4 & X86_CR4_VMXE) {
361 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 362 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 363 return;
364 }
365 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 366 vcpu->arch.cr4 = cr4;
6cffe8ca 367 kvm_mmu_sync_global(vcpu);
a03490ed 368 kvm_mmu_reset_context(vcpu);
a03490ed 369}
2d3ad1f4 370EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 371
2d3ad1f4 372void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 373{
ad312c7c 374 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 375 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 376 kvm_mmu_flush_tlb(vcpu);
377 return;
378 }
379
a03490ed
CO		 380 if (is_long_mode(vcpu)) {
381 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
382 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 383 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 384 return;
385 }
386 } else {
387 if (is_pae(vcpu)) {
388 if (cr3 & CR3_PAE_RESERVED_BITS) {
389 printk(KERN_DEBUG
390 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 391 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 392 return;
393 }
394 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
395 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
396 "reserved bits\n");
c1a5d4f9 397 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 398 return;
399 }
400 }
401 /*
402 * We don't check reserved bits in nonpae mode, because
403 * this isn't enforced, and VMware depends on this.
404 */
405 }
406
a03490ed
CO		 407 /*
408 * Does the new cr3 value map to physical memory? (Note, we
409 * catch an invalid cr3 even in real-mode, because it would
410 * cause trouble later on when we turn on paging anyway.)
411 *
412 * A real CPU would silently accept an invalid cr3 and would
413 * attempt to use it - with largely undefined (and often hard
414 * to debug) behavior on the guest side.
415 */
416 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 417 kvm_inject_gp(vcpu, 0);
a03490ed 418 else {
ad312c7c
ZX		 419 vcpu->arch.cr3 = cr3;
420 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 421 }
a03490ed 422}
2d3ad1f4 423EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 424
2d3ad1f4 425void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 426{
427 if (cr8 & CR8_RESERVED_BITS) {
428 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 429 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 430 return;
431 }
432 if (irqchip_in_kernel(vcpu->kvm))
433 kvm_lapic_set_tpr(vcpu, cr8);
434 else
ad312c7c 435 vcpu->arch.cr8 = cr8;
a03490ed 436}
2d3ad1f4 437EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 438
2d3ad1f4 439unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 440{
441 if (irqchip_in_kernel(vcpu->kvm))
442 return kvm_lapic_get_cr8(vcpu);
443 else
ad312c7c 444 return vcpu->arch.cr8;
a03490ed 445}
2d3ad1f4 446EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 447
d8017474
AG		 448static inline u32 bit(int bitno)
449{
450 return 1 << (bitno & 31);
451}
452
043405e1
CO		 453/*
454 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
455 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
456 *
457 * This list is modified at module load time to reflect the
458 * capabilities of the host cpu.
459 */
460static u32 msrs_to_save[] = {
461 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
462 MSR_K6_STAR,
463#ifdef CONFIG_X86_64
464 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
465#endif
18068523 466 MSR_IA32_TIME_STAMP_COUNTER, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
b286d5d8 467 MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 468};
469
470static unsigned num_msrs_to_save;
471
472static u32 emulated_msrs[] = {
473 MSR_IA32_MISC_ENABLE,
474};
475
15c4a640
CO		 476static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
477{
f2b4b7dd 478 if (efer & efer_reserved_bits) {
15c4a640
CO		 479 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
480 efer);
c1a5d4f9 481 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 482 return;
483 }
484
485 if (is_paging(vcpu)
ad312c7c 486 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 487 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 488 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 489 return;
490 }
491
d8017474
AG		 492 if (efer & EFER_SVME) {
493 struct kvm_cpuid_entry2 *feat;
494
495 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
496 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
497 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
498 kvm_inject_gp(vcpu, 0);
499 return;
500 }
501 }
502
15c4a640
CO		 503 kvm_x86_ops->set_efer(vcpu, efer);
504
505 efer &= ~EFER_LMA;
ad312c7c 506 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 507
ad312c7c 508 vcpu->arch.shadow_efer = efer;
15c4a640
CO		 509}
510
f2b4b7dd
JR		 511void kvm_enable_efer_bits(u64 mask)
512{
513 efer_reserved_bits &= ~mask;
514}
515EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
516
517
15c4a640
CO		 518/*
519 * Writes msr value into into the appropriate "register".
520 * Returns 0 on success, non-0 otherwise.
521 * Assumes vcpu_load() was already called.
522 */
523int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
524{
525 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
526}
527
313a3dc7
CO		 528/*
529 * Adapt set_msr() to msr_io()'s calling convention
530 */
531static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
532{
533 return kvm_set_msr(vcpu, index, *data);
534}
535
18068523
GOC		 536static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
537{
538 static int version;
50d0a0f9
GH		 539 struct pvclock_wall_clock wc;
540 struct timespec now, sys, boot;
18068523
GOC		 541
542 if (!wall_clock)
543 return;
544
545 version++;
546
18068523
GOC		 547 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
548
50d0a0f9
GH		 549 /*
550 * The guest calculates current wall clock time by adding
551 * system time (updated by kvm_write_guest_time below) to the
552 * wall clock specified here. guest system time equals host
553 * system time for us, thus we must fill in host boot time here.
554 */
555 now = current_kernel_time();
556 ktime_get_ts(&sys);
557 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
558
559 wc.sec = boot.tv_sec;
560 wc.nsec = boot.tv_nsec;
561 wc.version = version;
18068523
GOC		 562
563 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
564
565 version++;
566 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 567}
568
50d0a0f9
GH		 569static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
570{
571 uint32_t quotient, remainder;
572
573 /* Don't try to replace with do_div(), this one calculates
574 * "(dividend << 32) / divisor" */
575 __asm__ ( "divl %4"
576 : "=a" (quotient), "=d" (remainder)
577 : "0" (0), "1" (dividend), "r" (divisor) );
578 return quotient;
579}
580
581static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
582{
583 uint64_t nsecs = 1000000000LL;
584 int32_t shift = 0;
585 uint64_t tps64;
586 uint32_t tps32;
587
588 tps64 = tsc_khz * 1000LL;
589 while (tps64 > nsecs*2) {
590 tps64 >>= 1;
591 shift--;
592 }
593
594 tps32 = (uint32_t)tps64;
595 while (tps32 <= (uint32_t)nsecs) {
596 tps32 <<= 1;
597 shift++;
598 }
599
600 hv_clock->tsc_shift = shift;
601 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
602
603 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 604 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 605 hv_clock->tsc_to_system_mul);
606}
607
18068523
GOC		 608static void kvm_write_guest_time(struct kvm_vcpu *v)
609{
610 struct timespec ts;
611 unsigned long flags;
612 struct kvm_vcpu_arch *vcpu = &v->arch;
613 void *shared_kaddr;
614
615 if ((!vcpu->time_page))
616 return;
617
50d0a0f9
GH		 618 if (unlikely(vcpu->hv_clock_tsc_khz != tsc_khz)) {
619 kvm_set_time_scale(tsc_khz, &vcpu->hv_clock);
620 vcpu->hv_clock_tsc_khz = tsc_khz;
621 }
622
18068523
GOC		 623 /* Keep irq disabled to prevent changes to the clock */
624 local_irq_save(flags);
625 kvm_get_msr(v, MSR_IA32_TIME_STAMP_COUNTER,
626 &vcpu->hv_clock.tsc_timestamp);
627 ktime_get_ts(&ts);
628 local_irq_restore(flags);
629
630 /* With all the info we got, fill in the values */
631
632 vcpu->hv_clock.system_time = ts.tv_nsec +
633 (NSEC_PER_SEC * (u64)ts.tv_sec);
634 /*
635 * The interface expects us to write an even number signaling that the
636 * update is finished. Since the guest won't see the intermediate
50d0a0f9 637 * state, we just increase by 2 at the end.
18068523 638 */
50d0a0f9 639 vcpu->hv_clock.version += 2;
18068523
GOC		 640
641 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
642
643 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 644 sizeof(vcpu->hv_clock));
18068523
GOC		 645
646 kunmap_atomic(shared_kaddr, KM_USER0);
647
648 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
649}
650
9ba075a6
AK		 651static bool msr_mtrr_valid(unsigned msr)
652{
653 switch (msr) {
654 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
655 case MSR_MTRRfix64K_00000:
656 case MSR_MTRRfix16K_80000:
657 case MSR_MTRRfix16K_A0000:
658 case MSR_MTRRfix4K_C0000:
659 case MSR_MTRRfix4K_C8000:
660 case MSR_MTRRfix4K_D0000:
661 case MSR_MTRRfix4K_D8000:
662 case MSR_MTRRfix4K_E0000:
663 case MSR_MTRRfix4K_E8000:
664 case MSR_MTRRfix4K_F0000:
665 case MSR_MTRRfix4K_F8000:
666 case MSR_MTRRdefType:
667 case MSR_IA32_CR_PAT:
668 return true;
669 case 0x2f8:
670 return true;
671 }
672 return false;
673}
674
675static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
676{
0bed3b56
SY		 677 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
678
9ba075a6
AK		 679 if (!msr_mtrr_valid(msr))
680 return 1;
681
0bed3b56
SY		 682 if (msr == MSR_MTRRdefType) {
683 vcpu->arch.mtrr_state.def_type = data;
684 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
685 } else if (msr == MSR_MTRRfix64K_00000)
686 p[0] = data;
687 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
688 p[1 + msr - MSR_MTRRfix16K_80000] = data;
689 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
690 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
691 else if (msr == MSR_IA32_CR_PAT)
692 vcpu->arch.pat = data;
693 else { /* Variable MTRRs */
694 int idx, is_mtrr_mask;
695 u64 *pt;
696
697 idx = (msr - 0x200) / 2;
698 is_mtrr_mask = msr - 0x200 - 2 * idx;
699 if (!is_mtrr_mask)
700 pt =
701 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
702 else
703 pt =
704 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
705 *pt = data;
706 }
707
708 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 709 return 0;
710}
15c4a640
CO		 711
712int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
713{
714 switch (msr) {
15c4a640
CO		 715 case MSR_EFER:
716 set_efer(vcpu, data);
717 break;
15c4a640
CO		 718 case MSR_IA32_MC0_STATUS:
719 pr_unimpl(vcpu, "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n",
b8688d51 720 __func__, data);
15c4a640
CO		 721 break;
722 case MSR_IA32_MCG_STATUS:
723 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_STATUS 0x%llx, nop\n",
b8688d51 724 __func__, data);
15c4a640 725 break;
c7ac679c
JR		 726 case MSR_IA32_MCG_CTL:
727 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_CTL 0x%llx, nop\n",
b8688d51 728 __func__, data);
c7ac679c 729 break;
b5e2fec0
AG		 730 case MSR_IA32_DEBUGCTLMSR:
731 if (!data) {
732 /* We support the non-activated case already */
733 break;
734 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
735 /* Values other than LBR and BTF are vendor-specific,
736 thus reserved and should throw a #GP */
737 return 1;
738 }
739 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
740 __func__, data);
741 break;
15c4a640
CO		 742 case MSR_IA32_UCODE_REV:
743 case MSR_IA32_UCODE_WRITE:
15c4a640 744 break;
9ba075a6
AK		 745 case 0x200 ... 0x2ff:
746 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 747 case MSR_IA32_APICBASE:
748 kvm_set_apic_base(vcpu, data);
749 break;
750 case MSR_IA32_MISC_ENABLE:
ad312c7c 751 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 752 break;
18068523
GOC		 753 case MSR_KVM_WALL_CLOCK:
754 vcpu->kvm->arch.wall_clock = data;
755 kvm_write_wall_clock(vcpu->kvm, data);
756 break;
757 case MSR_KVM_SYSTEM_TIME: {
758 if (vcpu->arch.time_page) {
759 kvm_release_page_dirty(vcpu->arch.time_page);
760 vcpu->arch.time_page = NULL;
761 }
762
763 vcpu->arch.time = data;
764
765 /* we verify if the enable bit is set... */
766 if (!(data & 1))
767 break;
768
769 /* ...but clean it before doing the actual write */
770 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
771
18068523
GOC		 772 vcpu->arch.time_page =
773 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 774
775 if (is_error_page(vcpu->arch.time_page)) {
776 kvm_release_page_clean(vcpu->arch.time_page);
777 vcpu->arch.time_page = NULL;
778 }
779
780 kvm_write_guest_time(vcpu);
781 break;
782 }
15c4a640 783 default:
565f1fbd 784 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", msr, data);
15c4a640
CO		 785 return 1;
786 }
787 return 0;
788}
789EXPORT_SYMBOL_GPL(kvm_set_msr_common);
790
791
792/*
793 * Reads an msr value (of 'msr_index') into 'pdata'.
794 * Returns 0 on success, non-0 otherwise.
795 * Assumes vcpu_load() was already called.
796 */
797int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
798{
799 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
800}
801
9ba075a6
AK		 802static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
803{
0bed3b56
SY		 804 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
805
9ba075a6
AK		 806 if (!msr_mtrr_valid(msr))
807 return 1;
808
0bed3b56
SY		 809 if (msr == MSR_MTRRdefType)
810 *pdata = vcpu->arch.mtrr_state.def_type +
811 (vcpu->arch.mtrr_state.enabled << 10);
812 else if (msr == MSR_MTRRfix64K_00000)
813 *pdata = p[0];
814 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
815 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
816 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
817 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
818 else if (msr == MSR_IA32_CR_PAT)
819 *pdata = vcpu->arch.pat;
820 else { /* Variable MTRRs */
821 int idx, is_mtrr_mask;
822 u64 *pt;
823
824 idx = (msr - 0x200) / 2;
825 is_mtrr_mask = msr - 0x200 - 2 * idx;
826 if (!is_mtrr_mask)
827 pt =
828 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
829 else
830 pt =
831 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
832 *pdata = *pt;
833 }
834
9ba075a6
AK		 835 return 0;
836}
837
15c4a640
CO		 838int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
839{
840 u64 data;
841
842 switch (msr) {
843 case 0xc0010010: /* SYSCFG */
844 case 0xc0010015: /* HWCR */
845 case MSR_IA32_PLATFORM_ID:
846 case MSR_IA32_P5_MC_ADDR:
847 case MSR_IA32_P5_MC_TYPE:
848 case MSR_IA32_MC0_CTL:
849 case MSR_IA32_MCG_STATUS:
850 case MSR_IA32_MCG_CAP:
c7ac679c 851 case MSR_IA32_MCG_CTL:
15c4a640
CO		 852 case MSR_IA32_MC0_MISC:
853 case MSR_IA32_MC0_MISC+4:
854 case MSR_IA32_MC0_MISC+8:
855 case MSR_IA32_MC0_MISC+12:
856 case MSR_IA32_MC0_MISC+16:
a89c1ad2 857 case MSR_IA32_MC0_MISC+20:
15c4a640 858 case MSR_IA32_UCODE_REV:
15c4a640 859 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 860 case MSR_IA32_DEBUGCTLMSR:
861 case MSR_IA32_LASTBRANCHFROMIP:
862 case MSR_IA32_LASTBRANCHTOIP:
863 case MSR_IA32_LASTINTFROMIP:
864 case MSR_IA32_LASTINTTOIP:
15c4a640
CO		 865 data = 0;
866 break;
9ba075a6
AK		 867 case MSR_MTRRcap:
868 data = 0x500 | KVM_NR_VAR_MTRR;
869 break;
870 case 0x200 ... 0x2ff:
871 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 872 case 0xcd: /* fsb frequency */
873 data = 3;
874 break;
875 case MSR_IA32_APICBASE:
876 data = kvm_get_apic_base(vcpu);
877 break;
878 case MSR_IA32_MISC_ENABLE:
ad312c7c 879 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 880 break;
847f0ad8
AG		 881 case MSR_IA32_PERF_STATUS:
882 /* TSC increment by tick */
883 data = 1000ULL;
884 /* CPU multiplier */
885 data |= (((uint64_t)4ULL) << 40);
886 break;
15c4a640 887 case MSR_EFER:
ad312c7c 888 data = vcpu->arch.shadow_efer;
15c4a640 889 break;
18068523
GOC		 890 case MSR_KVM_WALL_CLOCK:
891 data = vcpu->kvm->arch.wall_clock;
892 break;
893 case MSR_KVM_SYSTEM_TIME:
894 data = vcpu->arch.time;
895 break;
15c4a640
CO		 896 default:
897 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
898 return 1;
899 }
900 *pdata = data;
901 return 0;
902}
903EXPORT_SYMBOL_GPL(kvm_get_msr_common);
904
313a3dc7
CO		 905/*
906 * Read or write a bunch of msrs. All parameters are kernel addresses.
907 *
908 * @return number of msrs set successfully.
909 */
910static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
911 struct kvm_msr_entry *entries,
912 int (*do_msr)(struct kvm_vcpu *vcpu,
913 unsigned index, u64 *data))
914{
915 int i;
916
917 vcpu_load(vcpu);
918
3200f405 919 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 920 for (i = 0; i < msrs->nmsrs; ++i)
921 if (do_msr(vcpu, entries[i].index, &entries[i].data))
922 break;
3200f405 923 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 924
925 vcpu_put(vcpu);
926
927 return i;
928}
929
930/*
931 * Read or write a bunch of msrs. Parameters are user addresses.
932 *
933 * @return number of msrs set successfully.
934 */
935static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
936 int (*do_msr)(struct kvm_vcpu *vcpu,
937 unsigned index, u64 *data),
938 int writeback)
939{
940 struct kvm_msrs msrs;
941 struct kvm_msr_entry *entries;
942 int r, n;
943 unsigned size;
944
945 r = -EFAULT;
946 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
947 goto out;
948
949 r = -E2BIG;
950 if (msrs.nmsrs >= MAX_IO_MSRS)
951 goto out;
952
953 r = -ENOMEM;
954 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
955 entries = vmalloc(size);
956 if (!entries)
957 goto out;
958
959 r = -EFAULT;
960 if (copy_from_user(entries, user_msrs->entries, size))
961 goto out_free;
962
963 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
964 if (r < 0)
965 goto out_free;
966
967 r = -EFAULT;
968 if (writeback && copy_to_user(user_msrs->entries, entries, size))
969 goto out_free;
970
971 r = n;
972
973out_free:
974 vfree(entries);
975out:
976 return r;
977}
978
018d00d2
ZX		 979int kvm_dev_ioctl_check_extension(long ext)
980{
981 int r;
982
983 switch (ext) {
984 case KVM_CAP_IRQCHIP:
985 case KVM_CAP_HLT:
986 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 987 case KVM_CAP_SET_TSS_ADDR:
07716717 988 case KVM_CAP_EXT_CPUID:
7837699f 989 case KVM_CAP_PIT:
a28e4f5a 990 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 991 case KVM_CAP_MP_STATE:
ed848624 992 case KVM_CAP_SYNC_MMU:
018d00d2
ZX		 993 r = 1;
994 break;
542472b5
LV		 995 case KVM_CAP_COALESCED_MMIO:
996 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
997 break;
774ead3a
AK		 998 case KVM_CAP_VAPIC:
999 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1000 break;
f725230a
AK		 1001 case KVM_CAP_NR_VCPUS:
1002 r = KVM_MAX_VCPUS;
1003 break;
a988b910
AK		 1004 case KVM_CAP_NR_MEMSLOTS:
1005 r = KVM_MEMORY_SLOTS;
1006 break;
2f333bcb
MT		 1007 case KVM_CAP_PV_MMU:
1008 r = !tdp_enabled;
1009 break;
62c476c7 1010 case KVM_CAP_IOMMU:
19de40a8 1011 r = iommu_found();
62c476c7 1012 break;
abe6655d
MT		 1013 case KVM_CAP_CLOCKSOURCE:
1014 r = boot_cpu_has(X86_FEATURE_CONSTANT_TSC);
1015 break;
018d00d2
ZX		 1016 default:
1017 r = 0;
1018 break;
1019 }
1020 return r;
1021
1022}
1023
043405e1
CO		 1024long kvm_arch_dev_ioctl(struct file *filp,
1025 unsigned int ioctl, unsigned long arg)
1026{
1027 void __user *argp = (void __user *)arg;
1028 long r;
1029
1030 switch (ioctl) {
1031 case KVM_GET_MSR_INDEX_LIST: {
1032 struct kvm_msr_list __user *user_msr_list = argp;
1033 struct kvm_msr_list msr_list;
1034 unsigned n;
1035
1036 r = -EFAULT;
1037 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1038 goto out;
1039 n = msr_list.nmsrs;
1040 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1041 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1042 goto out;
1043 r = -E2BIG;
1044 if (n < num_msrs_to_save)
1045 goto out;
1046 r = -EFAULT;
1047 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1048 num_msrs_to_save * sizeof(u32)))
1049 goto out;
1050 if (copy_to_user(user_msr_list->indices
1051 + num_msrs_to_save * sizeof(u32),
1052 &emulated_msrs,
1053 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1054 goto out;
1055 r = 0;
1056 break;
1057 }
674eea0f
AK		 1058 case KVM_GET_SUPPORTED_CPUID: {
1059 struct kvm_cpuid2 __user *cpuid_arg = argp;
1060 struct kvm_cpuid2 cpuid;
1061
1062 r = -EFAULT;
1063 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1064 goto out;
1065 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
1066 cpuid_arg->entries);
1067 if (r)
1068 goto out;
1069
1070 r = -EFAULT;
1071 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1072 goto out;
1073 r = 0;
1074 break;
1075 }
043405e1
CO		 1076 default:
1077 r = -EINVAL;
1078 }
1079out:
1080 return r;
1081}
1082
313a3dc7
CO		 1083void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1084{
1085 kvm_x86_ops->vcpu_load(vcpu, cpu);
18068523 1086 kvm_write_guest_time(vcpu);
313a3dc7
CO		 1087}
1088
1089void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1090{
1091 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 1092 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1093}
1094
07716717 1095static int is_efer_nx(void)
313a3dc7
CO		 1096{
1097 u64 efer;
313a3dc7
CO		 1098
1099 rdmsrl(MSR_EFER, efer);
07716717
DK		 1100 return efer & EFER_NX;
1101}
1102
1103static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1104{
1105 int i;
1106 struct kvm_cpuid_entry2 *e, *entry;
1107
313a3dc7 1108 entry = NULL;
ad312c7c
ZX		 1109 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1110 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1111 if (e->function == 0x80000001) {
1112 entry = e;
1113 break;
1114 }
1115 }
07716717 1116 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1117 entry->edx &= ~(1 << 20);
1118 printk(KERN_INFO "kvm: guest NX capability removed\n");
1119 }
1120}
1121
07716717 1122/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1123static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1124 struct kvm_cpuid *cpuid,
1125 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1126{
1127 int r, i;
1128 struct kvm_cpuid_entry *cpuid_entries;
1129
1130 r = -E2BIG;
1131 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1132 goto out;
1133 r = -ENOMEM;
1134 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1135 if (!cpuid_entries)
1136 goto out;
1137 r = -EFAULT;
1138 if (copy_from_user(cpuid_entries, entries,
1139 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1140 goto out_free;
1141 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1142 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1143 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1144 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1145 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1146 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1147 vcpu->arch.cpuid_entries[i].index = 0;
1148 vcpu->arch.cpuid_entries[i].flags = 0;
1149 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1150 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1151 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1152 }
1153 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1154 cpuid_fix_nx_cap(vcpu);
1155 r = 0;
1156
1157out_free:
1158 vfree(cpuid_entries);
1159out:
1160 return r;
1161}
1162
1163static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
1164 struct kvm_cpuid2 *cpuid,
1165 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1166{
1167 int r;
1168
1169 r = -E2BIG;
1170 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1171 goto out;
1172 r = -EFAULT;
ad312c7c 1173 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1174 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1175 goto out;
ad312c7c 1176 vcpu->arch.cpuid_nent = cpuid->nent;
313a3dc7
CO		 1177 return 0;
1178
1179out:
1180 return r;
1181}
1182
07716717
DK		 1183static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
1184 struct kvm_cpuid2 *cpuid,
1185 struct kvm_cpuid_entry2 __user *entries)
1186{
1187 int r;
1188
1189 r = -E2BIG;
ad312c7c 1190 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1191 goto out;
1192 r = -EFAULT;
ad312c7c
ZX		 1193 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
1194 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1195 goto out;
1196 return 0;
1197
1198out:
ad312c7c 1199 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1200 return r;
1201}
1202
07716717
DK		 1203static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1204 u32 index)
1205{
1206 entry->function = function;
1207 entry->index = index;
1208 cpuid_count(entry->function, entry->index,
1209 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
1210 entry->flags = 0;
1211}
1212
1213static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1214 u32 index, int *nent, int maxnent)
1215{
1216 const u32 kvm_supported_word0_x86_features = bit(X86_FEATURE_FPU) |
1217 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1218 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1219 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1220 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1221 bit(X86_FEATURE_SEP) | bit(X86_FEATURE_PGE) |
1222 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1223 bit(X86_FEATURE_CLFLSH) | bit(X86_FEATURE_MMX) |
1224 bit(X86_FEATURE_FXSR) | bit(X86_FEATURE_XMM) |
1225 bit(X86_FEATURE_XMM2) | bit(X86_FEATURE_SELFSNOOP);
1226 const u32 kvm_supported_word1_x86_features = bit(X86_FEATURE_FPU) |
1227 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1228 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1229 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1230 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1231 bit(X86_FEATURE_PGE) |
1232 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1233 bit(X86_FEATURE_MMX) | bit(X86_FEATURE_FXSR) |
1234 bit(X86_FEATURE_SYSCALL) |
1235 (bit(X86_FEATURE_NX) && is_efer_nx()) |
1236#ifdef CONFIG_X86_64
1237 bit(X86_FEATURE_LM) |
1238#endif
1239 bit(X86_FEATURE_MMXEXT) |
1240 bit(X86_FEATURE_3DNOWEXT) |
1241 bit(X86_FEATURE_3DNOW);
1242 const u32 kvm_supported_word3_x86_features =
1243 bit(X86_FEATURE_XMM3) | bit(X86_FEATURE_CX16);
1244 const u32 kvm_supported_word6_x86_features =
d8017474
AG		 1245 bit(X86_FEATURE_LAHF_LM) | bit(X86_FEATURE_CMP_LEGACY) |
1246 bit(X86_FEATURE_SVM);
07716717
DK		 1247
1248 /* all func 2 cpuid_count() should be called on the same cpu */
1249 get_cpu();
1250 do_cpuid_1_ent(entry, function, index);
1251 ++*nent;
1252
1253 switch (function) {
1254 case 0:
1255 entry->eax = min(entry->eax, (u32)0xb);
1256 break;
1257 case 1:
1258 entry->edx &= kvm_supported_word0_x86_features;
1259 entry->ecx &= kvm_supported_word3_x86_features;
1260 break;
1261 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1262 * may return different values. This forces us to get_cpu() before
1263 * issuing the first command, and also to emulate this annoying behavior
1264 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1265 case 2: {
1266 int t, times = entry->eax & 0xff;
1267
1268 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1269 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1270 for (t = 1; t < times && *nent < maxnent; ++t) {
1271 do_cpuid_1_ent(&entry[t], function, 0);
1272 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1273 ++*nent;
1274 }
1275 break;
1276 }
1277 /* function 4 and 0xb have additional index. */
1278 case 4: {
14af3f3c 1279 int i, cache_type;
07716717
DK		 1280
1281 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1282 /* read more entries until cache_type is zero */
14af3f3c
HH		 1283 for (i = 1; *nent < maxnent; ++i) {
1284 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1285 if (!cache_type)
1286 break;
14af3f3c
HH		 1287 do_cpuid_1_ent(&entry[i], function, i);
1288 entry[i].flags |=
07716717
DK		 1289 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1290 ++*nent;
1291 }
1292 break;
1293 }
1294 case 0xb: {
14af3f3c 1295 int i, level_type;
07716717
DK		 1296
1297 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1298 /* read more entries until level_type is zero */
14af3f3c 1299 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1300 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1301 if (!level_type)
1302 break;
14af3f3c
HH		 1303 do_cpuid_1_ent(&entry[i], function, i);
1304 entry[i].flags |=
07716717
DK		 1305 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1306 ++*nent;
1307 }
1308 break;
1309 }
1310 case 0x80000000:
1311 entry->eax = min(entry->eax, 0x8000001a);
1312 break;
1313 case 0x80000001:
1314 entry->edx &= kvm_supported_word1_x86_features;
1315 entry->ecx &= kvm_supported_word6_x86_features;
1316 break;
1317 }
1318 put_cpu();
1319}
1320
674eea0f 1321static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
07716717
DK		 1322 struct kvm_cpuid_entry2 __user *entries)
1323{
1324 struct kvm_cpuid_entry2 *cpuid_entries;
1325 int limit, nent = 0, r = -E2BIG;
1326 u32 func;
1327
1328 if (cpuid->nent < 1)
1329 goto out;
1330 r = -ENOMEM;
1331 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1332 if (!cpuid_entries)
1333 goto out;
1334
1335 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1336 limit = cpuid_entries[0].eax;
1337 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1338 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1339 &nent, cpuid->nent);
1340 r = -E2BIG;
1341 if (nent >= cpuid->nent)
1342 goto out_free;
1343
1344 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1345 limit = cpuid_entries[nent - 1].eax;
1346 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1347 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1348 &nent, cpuid->nent);
1349 r = -EFAULT;
1350 if (copy_to_user(entries, cpuid_entries,
1351 nent * sizeof(struct kvm_cpuid_entry2)))
1352 goto out_free;
1353 cpuid->nent = nent;
1354 r = 0;
1355
1356out_free:
1357 vfree(cpuid_entries);
1358out:
1359 return r;
1360}
1361
313a3dc7
CO		 1362static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1363 struct kvm_lapic_state *s)
1364{
1365 vcpu_load(vcpu);
ad312c7c 1366 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1367 vcpu_put(vcpu);
1368
1369 return 0;
1370}
1371
1372static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1373 struct kvm_lapic_state *s)
1374{
1375 vcpu_load(vcpu);
ad312c7c 1376 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7
CO		 1377 kvm_apic_post_state_restore(vcpu);
1378 vcpu_put(vcpu);
1379
1380 return 0;
1381}
1382
f77bc6a4
ZX		 1383static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1384 struct kvm_interrupt *irq)
1385{
1386 if (irq->irq < 0 || irq->irq >= 256)
1387 return -EINVAL;
1388 if (irqchip_in_kernel(vcpu->kvm))
1389 return -ENXIO;
1390 vcpu_load(vcpu);
1391
ad312c7c
ZX		 1392 set_bit(irq->irq, vcpu->arch.irq_pending);
1393 set_bit(irq->irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
f77bc6a4
ZX		 1394
1395 vcpu_put(vcpu);
1396
1397 return 0;
1398}
1399
c4abb7c9
JK		 1400static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1401{
1402 vcpu_load(vcpu);
1403 kvm_inject_nmi(vcpu);
1404 vcpu_put(vcpu);
1405
1406 return 0;
1407}
1408
b209749f
AK		 1409static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1410 struct kvm_tpr_access_ctl *tac)
1411{
1412 if (tac->flags)
1413 return -EINVAL;
1414 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1415 return 0;
1416}
1417
313a3dc7
CO		 1418long kvm_arch_vcpu_ioctl(struct file *filp,
1419 unsigned int ioctl, unsigned long arg)
1420{
1421 struct kvm_vcpu *vcpu = filp->private_data;
1422 void __user *argp = (void __user *)arg;
1423 int r;
b772ff36 1424 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 1425
1426 switch (ioctl) {
1427 case KVM_GET_LAPIC: {
b772ff36 1428 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 1429
b772ff36
DH		 1430 r = -ENOMEM;
1431 if (!lapic)
1432 goto out;
1433 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 1434 if (r)
1435 goto out;
1436 r = -EFAULT;
b772ff36 1437 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 1438 goto out;
1439 r = 0;
1440 break;
1441 }
1442 case KVM_SET_LAPIC: {
b772ff36
DH		 1443 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1444 r = -ENOMEM;
1445 if (!lapic)
1446 goto out;
313a3dc7 1447 r = -EFAULT;
b772ff36 1448 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 1449 goto out;
b772ff36 1450 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 1451 if (r)
1452 goto out;
1453 r = 0;
1454 break;
1455 }
f77bc6a4
ZX		 1456 case KVM_INTERRUPT: {
1457 struct kvm_interrupt irq;
1458
1459 r = -EFAULT;
1460 if (copy_from_user(&irq, argp, sizeof irq))
1461 goto out;
1462 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1463 if (r)
1464 goto out;
1465 r = 0;
1466 break;
1467 }
c4abb7c9
JK		 1468 case KVM_NMI: {
1469 r = kvm_vcpu_ioctl_nmi(vcpu);
1470 if (r)
1471 goto out;
1472 r = 0;
1473 break;
1474 }
313a3dc7
CO		 1475 case KVM_SET_CPUID: {
1476 struct kvm_cpuid __user *cpuid_arg = argp;
1477 struct kvm_cpuid cpuid;
1478
1479 r = -EFAULT;
1480 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1481 goto out;
1482 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1483 if (r)
1484 goto out;
1485 break;
1486 }
07716717
DK		 1487 case KVM_SET_CPUID2: {
1488 struct kvm_cpuid2 __user *cpuid_arg = argp;
1489 struct kvm_cpuid2 cpuid;
1490
1491 r = -EFAULT;
1492 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1493 goto out;
1494 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
1495 cpuid_arg->entries);
1496 if (r)
1497 goto out;
1498 break;
1499 }
1500 case KVM_GET_CPUID2: {
1501 struct kvm_cpuid2 __user *cpuid_arg = argp;
1502 struct kvm_cpuid2 cpuid;
1503
1504 r = -EFAULT;
1505 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1506 goto out;
1507 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
1508 cpuid_arg->entries);
1509 if (r)
1510 goto out;
1511 r = -EFAULT;
1512 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1513 goto out;
1514 r = 0;
1515 break;
1516 }
313a3dc7
CO		 1517 case KVM_GET_MSRS:
1518 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1519 break;
1520 case KVM_SET_MSRS:
1521 r = msr_io(vcpu, argp, do_set_msr, 0);
1522 break;
b209749f
AK		 1523 case KVM_TPR_ACCESS_REPORTING: {
1524 struct kvm_tpr_access_ctl tac;
1525
1526 r = -EFAULT;
1527 if (copy_from_user(&tac, argp, sizeof tac))
1528 goto out;
1529 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1530 if (r)
1531 goto out;
1532 r = -EFAULT;
1533 if (copy_to_user(argp, &tac, sizeof tac))
1534 goto out;
1535 r = 0;
1536 break;
1537 };
b93463aa
AK		 1538 case KVM_SET_VAPIC_ADDR: {
1539 struct kvm_vapic_addr va;
1540
1541 r = -EINVAL;
1542 if (!irqchip_in_kernel(vcpu->kvm))
1543 goto out;
1544 r = -EFAULT;
1545 if (copy_from_user(&va, argp, sizeof va))
1546 goto out;
1547 r = 0;
1548 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1549 break;
1550 }
313a3dc7
CO		 1551 default:
1552 r = -EINVAL;
1553 }
1554out:
b772ff36
DH		 1555 if (lapic)
1556 kfree(lapic);
313a3dc7
CO		 1557 return r;
1558}
1559
1fe779f8
CO		 1560static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1561{
1562 int ret;
1563
1564 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1565 return -1;
1566 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1567 return ret;
1568}
1569
1570static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1571 u32 kvm_nr_mmu_pages)
1572{
1573 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1574 return -EINVAL;
1575
72dc67a6 1576 down_write(&kvm->slots_lock);
1fe779f8
CO		 1577
1578 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1579 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1580
72dc67a6 1581 up_write(&kvm->slots_lock);
1fe779f8
CO		 1582 return 0;
1583}
1584
1585static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1586{
f05e70ac 1587 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1588}
1589
e9f85cde
ZX		 1590gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1591{
1592 int i;
1593 struct kvm_mem_alias *alias;
1594
d69fb81f
ZX		 1595 for (i = 0; i < kvm->arch.naliases; ++i) {
1596 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1597 if (gfn >= alias->base_gfn
1598 && gfn < alias->base_gfn + alias->npages)
1599 return alias->target_gfn + gfn - alias->base_gfn;
1600 }
1601 return gfn;
1602}
1603
1fe779f8
CO		 1604/*
1605 * Set a new alias region. Aliases map a portion of physical memory into
1606 * another portion. This is useful for memory windows, for example the PC
1607 * VGA region.
1608 */
1609static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1610 struct kvm_memory_alias *alias)
1611{
1612 int r, n;
1613 struct kvm_mem_alias *p;
1614
1615 r = -EINVAL;
1616 /* General sanity checks */
1617 if (alias->memory_size & (PAGE_SIZE - 1))
1618 goto out;
1619 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1620 goto out;
1621 if (alias->slot >= KVM_ALIAS_SLOTS)
1622 goto out;
1623 if (alias->guest_phys_addr + alias->memory_size
1624 < alias->guest_phys_addr)
1625 goto out;
1626 if (alias->target_phys_addr + alias->memory_size
1627 < alias->target_phys_addr)
1628 goto out;
1629
72dc67a6 1630 down_write(&kvm->slots_lock);
a1708ce8 1631 spin_lock(&kvm->mmu_lock);
1fe779f8 1632
d69fb81f 1633 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 1634 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1635 p->npages = alias->memory_size >> PAGE_SHIFT;
1636 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1637
1638 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 1639 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 1640 break;
d69fb81f 1641 kvm->arch.naliases = n;
1fe779f8 1642
a1708ce8 1643 spin_unlock(&kvm->mmu_lock);
1fe779f8
CO		 1644 kvm_mmu_zap_all(kvm);
1645
72dc67a6 1646 up_write(&kvm->slots_lock);
1fe779f8
CO		 1647
1648 return 0;
1649
1650out:
1651 return r;
1652}
1653
1654static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1655{
1656 int r;
1657
1658 r = 0;
1659 switch (chip->chip_id) {
1660 case KVM_IRQCHIP_PIC_MASTER:
1661 memcpy(&chip->chip.pic,
1662 &pic_irqchip(kvm)->pics[0],
1663 sizeof(struct kvm_pic_state));
1664 break;
1665 case KVM_IRQCHIP_PIC_SLAVE:
1666 memcpy(&chip->chip.pic,
1667 &pic_irqchip(kvm)->pics[1],
1668 sizeof(struct kvm_pic_state));
1669 break;
1670 case KVM_IRQCHIP_IOAPIC:
1671 memcpy(&chip->chip.ioapic,
1672 ioapic_irqchip(kvm),
1673 sizeof(struct kvm_ioapic_state));
1674 break;
1675 default:
1676 r = -EINVAL;
1677 break;
1678 }
1679 return r;
1680}
1681
1682static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1683{
1684 int r;
1685
1686 r = 0;
1687 switch (chip->chip_id) {
1688 case KVM_IRQCHIP_PIC_MASTER:
1689 memcpy(&pic_irqchip(kvm)->pics[0],
1690 &chip->chip.pic,
1691 sizeof(struct kvm_pic_state));
1692 break;
1693 case KVM_IRQCHIP_PIC_SLAVE:
1694 memcpy(&pic_irqchip(kvm)->pics[1],
1695 &chip->chip.pic,
1696 sizeof(struct kvm_pic_state));
1697 break;
1698 case KVM_IRQCHIP_IOAPIC:
1699 memcpy(ioapic_irqchip(kvm),
1700 &chip->chip.ioapic,
1701 sizeof(struct kvm_ioapic_state));
1702 break;
1703 default:
1704 r = -EINVAL;
1705 break;
1706 }
1707 kvm_pic_update_irq(pic_irqchip(kvm));
1708 return r;
1709}
1710
e0f63cb9
SY		 1711static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1712{
1713 int r = 0;
1714
1715 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
1716 return r;
1717}
1718
1719static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1720{
1721 int r = 0;
1722
1723 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
1724 kvm_pit_load_count(kvm, 0, ps->channels[0].count);
1725 return r;
1726}
1727
5bb064dc
ZX		 1728/*
1729 * Get (and clear) the dirty memory log for a memory slot.
1730 */
1731int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
1732 struct kvm_dirty_log *log)
1733{
1734 int r;
1735 int n;
1736 struct kvm_memory_slot *memslot;
1737 int is_dirty = 0;
1738
72dc67a6 1739 down_write(&kvm->slots_lock);
5bb064dc
ZX		 1740
1741 r = kvm_get_dirty_log(kvm, log, &is_dirty);
1742 if (r)
1743 goto out;
1744
1745 /* If nothing is dirty, don't bother messing with page tables. */
1746 if (is_dirty) {
1747 kvm_mmu_slot_remove_write_access(kvm, log->slot);
1748 kvm_flush_remote_tlbs(kvm);
1749 memslot = &kvm->memslots[log->slot];
1750 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
1751 memset(memslot->dirty_bitmap, 0, n);
1752 }
1753 r = 0;
1754out:
72dc67a6 1755 up_write(&kvm->slots_lock);
5bb064dc
ZX		 1756 return r;
1757}
1758
1fe779f8
CO		 1759long kvm_arch_vm_ioctl(struct file *filp,
1760 unsigned int ioctl, unsigned long arg)
1761{
1762 struct kvm *kvm = filp->private_data;
1763 void __user *argp = (void __user *)arg;
1764 int r = -EINVAL;
f0d66275
DH		 1765 /*
1766 * This union makes it completely explicit to gcc-3.x
1767 * that these two variables' stack usage should be
1768 * combined, not added together.
1769 */
1770 union {
1771 struct kvm_pit_state ps;
1772 struct kvm_memory_alias alias;
1773 } u;
1fe779f8
CO		 1774
1775 switch (ioctl) {
1776 case KVM_SET_TSS_ADDR:
1777 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1778 if (r < 0)
1779 goto out;
1780 break;
1781 case KVM_SET_MEMORY_REGION: {
1782 struct kvm_memory_region kvm_mem;
1783 struct kvm_userspace_memory_region kvm_userspace_mem;
1784
1785 r = -EFAULT;
1786 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
1787 goto out;
1788 kvm_userspace_mem.slot = kvm_mem.slot;
1789 kvm_userspace_mem.flags = kvm_mem.flags;
1790 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
1791 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
1792 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
1793 if (r)
1794 goto out;
1795 break;
1796 }
1797 case KVM_SET_NR_MMU_PAGES:
1798 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1799 if (r)
1800 goto out;
1801 break;
1802 case KVM_GET_NR_MMU_PAGES:
1803 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
1804 break;
f0d66275 1805 case KVM_SET_MEMORY_ALIAS:
1fe779f8 1806 r = -EFAULT;
f0d66275 1807 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 1808 goto out;
f0d66275 1809 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 1810 if (r)
1811 goto out;
1812 break;
1fe779f8
CO		 1813 case KVM_CREATE_IRQCHIP:
1814 r = -ENOMEM;
d7deeeb0
ZX		 1815 kvm->arch.vpic = kvm_create_pic(kvm);
1816 if (kvm->arch.vpic) {
1fe779f8
CO		 1817 r = kvm_ioapic_init(kvm);
1818 if (r) {
d7deeeb0
ZX		 1819 kfree(kvm->arch.vpic);
1820 kvm->arch.vpic = NULL;
1fe779f8
CO		 1821 goto out;
1822 }
1823 } else
1824 goto out;
1825 break;
7837699f
SY		 1826 case KVM_CREATE_PIT:
1827 r = -ENOMEM;
1828 kvm->arch.vpit = kvm_create_pit(kvm);
1829 if (kvm->arch.vpit)
1830 r = 0;
1831 break;
1fe779f8
CO		 1832 case KVM_IRQ_LINE: {
1833 struct kvm_irq_level irq_event;
1834
1835 r = -EFAULT;
1836 if (copy_from_user(&irq_event, argp, sizeof irq_event))
1837 goto out;
1838 if (irqchip_in_kernel(kvm)) {
1839 mutex_lock(&kvm->lock);
5550af4d
SY		 1840 kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
1841 irq_event.irq, irq_event.level);
1fe779f8
CO		 1842 mutex_unlock(&kvm->lock);
1843 r = 0;
1844 }
1845 break;
1846 }
1847 case KVM_GET_IRQCHIP: {
1848 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 1849 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 1850
f0d66275
DH		 1851 r = -ENOMEM;
1852 if (!chip)
1fe779f8 1853 goto out;
f0d66275
DH		 1854 r = -EFAULT;
1855 if (copy_from_user(chip, argp, sizeof *chip))
1856 goto get_irqchip_out;
1fe779f8
CO		 1857 r = -ENXIO;
1858 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 1859 goto get_irqchip_out;
1860 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 1861 if (r)
f0d66275 1862 goto get_irqchip_out;
1fe779f8 1863 r = -EFAULT;
f0d66275
DH		 1864 if (copy_to_user(argp, chip, sizeof *chip))
1865 goto get_irqchip_out;
1fe779f8 1866 r = 0;
f0d66275
DH		 1867 get_irqchip_out:
1868 kfree(chip);
1869 if (r)
1870 goto out;
1fe779f8
CO		 1871 break;
1872 }
1873 case KVM_SET_IRQCHIP: {
1874 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 1875 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 1876
f0d66275
DH		 1877 r = -ENOMEM;
1878 if (!chip)
1fe779f8 1879 goto out;
f0d66275
DH		 1880 r = -EFAULT;
1881 if (copy_from_user(chip, argp, sizeof *chip))
1882 goto set_irqchip_out;
1fe779f8
CO		 1883 r = -ENXIO;
1884 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 1885 goto set_irqchip_out;
1886 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 1887 if (r)
f0d66275 1888 goto set_irqchip_out;
1fe779f8 1889 r = 0;
f0d66275
DH		 1890 set_irqchip_out:
1891 kfree(chip);
1892 if (r)
1893 goto out;
1fe779f8
CO		 1894 break;
1895 }
e0f63cb9 1896 case KVM_GET_PIT: {
e0f63cb9 1897 r = -EFAULT;
f0d66275 1898 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 1899 goto out;
1900 r = -ENXIO;
1901 if (!kvm->arch.vpit)
1902 goto out;
f0d66275 1903 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 1904 if (r)
1905 goto out;
1906 r = -EFAULT;
f0d66275 1907 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 1908 goto out;
1909 r = 0;
1910 break;
1911 }
1912 case KVM_SET_PIT: {
e0f63cb9 1913 r = -EFAULT;
f0d66275 1914 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 1915 goto out;
1916 r = -ENXIO;
1917 if (!kvm->arch.vpit)
1918 goto out;
f0d66275 1919 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 1920 if (r)
1921 goto out;
1922 r = 0;
1923 break;
1924 }
1fe779f8
CO		 1925 default:
1926 ;
1927 }
1928out:
1929 return r;
1930}
1931
a16b043c 1932static void kvm_init_msr_list(void)
043405e1
CO		 1933{
1934 u32 dummy[2];
1935 unsigned i, j;
1936
1937 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
1938 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
1939 continue;
1940 if (j < i)
1941 msrs_to_save[j] = msrs_to_save[i];
1942 j++;
1943 }
1944 num_msrs_to_save = j;
1945}
1946
bbd9b64e
CO		 1947/*
1948 * Only apic need an MMIO device hook, so shortcut now..
1949 */
1950static struct kvm_io_device *vcpu_find_pervcpu_dev(struct kvm_vcpu *vcpu,
92760499
LV		 1951 gpa_t addr, int len,
1952 int is_write)
bbd9b64e
CO		 1953{
1954 struct kvm_io_device *dev;
1955
ad312c7c
ZX		 1956 if (vcpu->arch.apic) {
1957 dev = &vcpu->arch.apic->dev;
92760499 1958 if (dev->in_range(dev, addr, len, is_write))
bbd9b64e
CO		 1959 return dev;
1960 }
1961 return NULL;
1962}
1963
1964
1965static struct kvm_io_device *vcpu_find_mmio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 1966 gpa_t addr, int len,
1967 int is_write)
bbd9b64e
CO		 1968{
1969 struct kvm_io_device *dev;
1970
92760499 1971 dev = vcpu_find_pervcpu_dev(vcpu, addr, len, is_write);
bbd9b64e 1972 if (dev == NULL)
92760499
LV		 1973 dev = kvm_io_bus_find_dev(&vcpu->kvm->mmio_bus, addr, len,
1974 is_write);
bbd9b64e
CO		 1975 return dev;
1976}
1977
1978int emulator_read_std(unsigned long addr,
1979 void *val,
1980 unsigned int bytes,
1981 struct kvm_vcpu *vcpu)
1982{
1983 void *data = val;
10589a46 1984 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 1985
1986 while (bytes) {
ad312c7c 1987 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 1988 unsigned offset = addr & (PAGE_SIZE-1);
1989 unsigned tocopy = min(bytes, (unsigned)PAGE_SIZE - offset);
1990 int ret;
1991
10589a46
MT		 1992 if (gpa == UNMAPPED_GVA) {
1993 r = X86EMUL_PROPAGATE_FAULT;
1994 goto out;
1995 }
bbd9b64e 1996 ret = kvm_read_guest(vcpu->kvm, gpa, data, tocopy);
10589a46
MT		 1997 if (ret < 0) {
1998 r = X86EMUL_UNHANDLEABLE;
1999 goto out;
2000 }
bbd9b64e
CO		 2001
2002 bytes -= tocopy;
2003 data += tocopy;
2004 addr += tocopy;
2005 }
10589a46 2006out:
10589a46 2007 return r;
bbd9b64e
CO		 2008}
2009EXPORT_SYMBOL_GPL(emulator_read_std);
2010
bbd9b64e
CO		 2011static int emulator_read_emulated(unsigned long addr,
2012 void *val,
2013 unsigned int bytes,
2014 struct kvm_vcpu *vcpu)
2015{
2016 struct kvm_io_device *mmio_dev;
2017 gpa_t gpa;
2018
2019 if (vcpu->mmio_read_completed) {
2020 memcpy(val, vcpu->mmio_data, bytes);
2021 vcpu->mmio_read_completed = 0;
2022 return X86EMUL_CONTINUE;
2023 }
2024
ad312c7c 2025 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2026
2027 /* For APIC access vmexit */
2028 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2029 goto mmio;
2030
2031 if (emulator_read_std(addr, val, bytes, vcpu)
2032 == X86EMUL_CONTINUE)
2033 return X86EMUL_CONTINUE;
2034 if (gpa == UNMAPPED_GVA)
2035 return X86EMUL_PROPAGATE_FAULT;
2036
2037mmio:
2038 /*
2039 * Is this MMIO handled locally?
2040 */
10589a46 2041 mutex_lock(&vcpu->kvm->lock);
92760499 2042 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 0);
bbd9b64e
CO		 2043 if (mmio_dev) {
2044 kvm_iodevice_read(mmio_dev, gpa, bytes, val);
10589a46 2045 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2046 return X86EMUL_CONTINUE;
2047 }
10589a46 2048 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2049
2050 vcpu->mmio_needed = 1;
2051 vcpu->mmio_phys_addr = gpa;
2052 vcpu->mmio_size = bytes;
2053 vcpu->mmio_is_write = 0;
2054
2055 return X86EMUL_UNHANDLEABLE;
2056}
2057
3200f405 2058int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 2059 const void *val, int bytes)
bbd9b64e
CO		 2060{
2061 int ret;
2062
2063 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 2064 if (ret < 0)
bbd9b64e 2065 return 0;
ad218f85 2066 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 2067 return 1;
2068}
2069
2070static int emulator_write_emulated_onepage(unsigned long addr,
2071 const void *val,
2072 unsigned int bytes,
2073 struct kvm_vcpu *vcpu)
2074{
2075 struct kvm_io_device *mmio_dev;
10589a46
MT		 2076 gpa_t gpa;
2077
10589a46 2078 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2079
2080 if (gpa == UNMAPPED_GVA) {
c3c91fee 2081 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 2082 return X86EMUL_PROPAGATE_FAULT;
2083 }
2084
2085 /* For APIC access vmexit */
2086 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2087 goto mmio;
2088
2089 if (emulator_write_phys(vcpu, gpa, val, bytes))
2090 return X86EMUL_CONTINUE;
2091
2092mmio:
2093 /*
2094 * Is this MMIO handled locally?
2095 */
10589a46 2096 mutex_lock(&vcpu->kvm->lock);
92760499 2097 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 1);
bbd9b64e
CO		 2098 if (mmio_dev) {
2099 kvm_iodevice_write(mmio_dev, gpa, bytes, val);
10589a46 2100 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2101 return X86EMUL_CONTINUE;
2102 }
10589a46 2103 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2104
2105 vcpu->mmio_needed = 1;
2106 vcpu->mmio_phys_addr = gpa;
2107 vcpu->mmio_size = bytes;
2108 vcpu->mmio_is_write = 1;
2109 memcpy(vcpu->mmio_data, val, bytes);
2110
2111 return X86EMUL_CONTINUE;
2112}
2113
2114int emulator_write_emulated(unsigned long addr,
2115 const void *val,
2116 unsigned int bytes,
2117 struct kvm_vcpu *vcpu)
2118{
2119 /* Crossing a page boundary? */
2120 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2121 int rc, now;
2122
2123 now = -addr & ~PAGE_MASK;
2124 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2125 if (rc != X86EMUL_CONTINUE)
2126 return rc;
2127 addr += now;
2128 val += now;
2129 bytes -= now;
2130 }
2131 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2132}
2133EXPORT_SYMBOL_GPL(emulator_write_emulated);
2134
2135static int emulator_cmpxchg_emulated(unsigned long addr,
2136 const void *old,
2137 const void *new,
2138 unsigned int bytes,
2139 struct kvm_vcpu *vcpu)
2140{
2141 static int reported;
2142
2143 if (!reported) {
2144 reported = 1;
2145 printk(KERN_WARNING "kvm: emulating exchange as write\n");
2146 }
2bacc55c
MT		 2147#ifndef CONFIG_X86_64
2148 /* guests cmpxchg8b have to be emulated atomically */
2149 if (bytes == 8) {
10589a46 2150 gpa_t gpa;
2bacc55c 2151 struct page *page;
c0b49b0d 2152 char *kaddr;
2bacc55c
MT		 2153 u64 val;
2154
10589a46
MT		 2155 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2156
2bacc55c
MT		 2157 if (gpa == UNMAPPED_GVA ||
2158 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2159 goto emul_write;
2160
2161 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2162 goto emul_write;
2163
2164 val = *(u64 *)new;
72dc67a6 2165
2bacc55c 2166 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 2167
c0b49b0d
AM		 2168 kaddr = kmap_atomic(page, KM_USER0);
2169 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2170 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 2171 kvm_release_page_dirty(page);
2172 }
3200f405 2173emul_write:
2bacc55c
MT		 2174#endif
2175
bbd9b64e
CO		 2176 return emulator_write_emulated(addr, new, bytes, vcpu);
2177}
2178
2179static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2180{
2181 return kvm_x86_ops->get_segment_base(vcpu, seg);
2182}
2183
2184int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2185{
a7052897 2186 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 2187 return X86EMUL_CONTINUE;
2188}
2189
2190int emulate_clts(struct kvm_vcpu *vcpu)
2191{
54e445ca 2192 KVMTRACE_0D(CLTS, vcpu, handler);
ad312c7c 2193 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 2194 return X86EMUL_CONTINUE;
2195}
2196
2197int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2198{
2199 struct kvm_vcpu *vcpu = ctxt->vcpu;
2200
2201 switch (dr) {
2202 case 0 ... 3:
2203 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2204 return X86EMUL_CONTINUE;
2205 default:
b8688d51 2206 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2207 return X86EMUL_UNHANDLEABLE;
2208 }
2209}
2210
2211int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2212{
2213 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2214 int exception;
2215
2216 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2217 if (exception) {
2218 /* FIXME: better handling */
2219 return X86EMUL_UNHANDLEABLE;
2220 }
2221 return X86EMUL_CONTINUE;
2222}
2223
2224void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2225{
bbd9b64e 2226 u8 opcodes[4];
5fdbf976 2227 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 2228 unsigned long rip_linear;
2229
f76c710d 2230 if (!printk_ratelimit())
bbd9b64e
CO		 2231 return;
2232
25be4608
GC		 2233 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2234
bbd9b64e
CO		 2235 emulator_read_std(rip_linear, (void *)opcodes, 4, vcpu);
2236
2237 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2238 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 2239}
2240EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2241
14af3f3c 2242static struct x86_emulate_ops emulate_ops = {
bbd9b64e 2243 .read_std = emulator_read_std,
bbd9b64e
CO		 2244 .read_emulated = emulator_read_emulated,
2245 .write_emulated = emulator_write_emulated,
2246 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2247};
2248
5fdbf976
MT		 2249static void cache_all_regs(struct kvm_vcpu *vcpu)
2250{
2251 kvm_register_read(vcpu, VCPU_REGS_RAX);
2252 kvm_register_read(vcpu, VCPU_REGS_RSP);
2253 kvm_register_read(vcpu, VCPU_REGS_RIP);
2254 vcpu->arch.regs_dirty = ~0;
2255}
2256
bbd9b64e
CO		 2257int emulate_instruction(struct kvm_vcpu *vcpu,
2258 struct kvm_run *run,
2259 unsigned long cr2,
2260 u16 error_code,
571008da 2261 int emulation_type)
bbd9b64e
CO		 2262{
2263 int r;
571008da 2264 struct decode_cache *c;
bbd9b64e 2265
26eef70c 2266 kvm_clear_exception_queue(vcpu);
ad312c7c 2267 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976
MT		 2268 /*
2269 * TODO: fix x86_emulate.c to use guest_read/write_register
2270 * instead of direct ->regs accesses, can save hundred cycles
2271 * on Intel for instructions that don't read/change RSP, for
2272 * for example.
2273 */
2274 cache_all_regs(vcpu);
bbd9b64e
CO		 2275
2276 vcpu->mmio_is_write = 0;
ad312c7c 2277 vcpu->arch.pio.string = 0;
bbd9b64e 2278
571008da 2279 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2280 int cs_db, cs_l;
2281 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2282
ad312c7c
ZX		 2283 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2284 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2285 vcpu->arch.emulate_ctxt.mode =
2286 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2287 ? X86EMUL_MODE_REAL : cs_l
2288 ? X86EMUL_MODE_PROT64 : cs_db
2289 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2290
ad312c7c 2291 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da
SY		 2292
2293 /* Reject the instructions other than VMCALL/VMMCALL when
2294 * try to emulate invalid opcode */
2295 c = &vcpu->arch.emulate_ctxt.decode;
2296 if ((emulation_type & EMULTYPE_TRAP_UD) &&
2297 (!(c->twobyte && c->b == 0x01 &&
2298 (c->modrm_reg == 0 || c->modrm_reg == 3) &&
2299 c->modrm_mod == 3 && c->modrm_rm == 1)))
2300 return EMULATE_FAIL;
2301
f2b5756b 2302 ++vcpu->stat.insn_emulation;
bbd9b64e 2303 if (r) {
f2b5756b 2304 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2305 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2306 return EMULATE_DONE;
2307 return EMULATE_FAIL;
2308 }
2309 }
2310
ad312c7c 2311 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
bbd9b64e 2312
ad312c7c 2313 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2314 return EMULATE_DO_MMIO;
2315
2316 if ((r || vcpu->mmio_is_write) && run) {
2317 run->exit_reason = KVM_EXIT_MMIO;
2318 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2319 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2320 run->mmio.len = vcpu->mmio_size;
2321 run->mmio.is_write = vcpu->mmio_is_write;
2322 }
2323
2324 if (r) {
2325 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2326 return EMULATE_DONE;
2327 if (!vcpu->mmio_needed) {
2328 kvm_report_emulation_failure(vcpu, "mmio");
2329 return EMULATE_FAIL;
2330 }
2331 return EMULATE_DO_MMIO;
2332 }
2333
ad312c7c 2334 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2335
2336 if (vcpu->mmio_is_write) {
2337 vcpu->mmio_needed = 0;
2338 return EMULATE_DO_MMIO;
2339 }
2340
2341 return EMULATE_DONE;
2342}
2343EXPORT_SYMBOL_GPL(emulate_instruction);
2344
de7d789a
CO		 2345static void free_pio_guest_pages(struct kvm_vcpu *vcpu)
2346{
2347 int i;
2348
ad312c7c
ZX		 2349 for (i = 0; i < ARRAY_SIZE(vcpu->arch.pio.guest_pages); ++i)
2350 if (vcpu->arch.pio.guest_pages[i]) {
2351 kvm_release_page_dirty(vcpu->arch.pio.guest_pages[i]);
2352 vcpu->arch.pio.guest_pages[i] = NULL;
de7d789a
CO		 2353 }
2354}
2355
2356static int pio_copy_data(struct kvm_vcpu *vcpu)
2357{
ad312c7c 2358 void *p = vcpu->arch.pio_data;
de7d789a
CO		 2359 void *q;
2360 unsigned bytes;
ad312c7c 2361 int nr_pages = vcpu->arch.pio.guest_pages[1] ? 2 : 1;
de7d789a 2362
ad312c7c 2363 q = vmap(vcpu->arch.pio.guest_pages, nr_pages, VM_READ|VM_WRITE,
de7d789a
CO		 2364 PAGE_KERNEL);
2365 if (!q) {
2366 free_pio_guest_pages(vcpu);
2367 return -ENOMEM;
2368 }
ad312c7c
ZX		 2369 q += vcpu->arch.pio.guest_page_offset;
2370 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2371 if (vcpu->arch.pio.in)
de7d789a
CO		 2372 memcpy(q, p, bytes);
2373 else
2374 memcpy(p, q, bytes);
ad312c7c 2375 q -= vcpu->arch.pio.guest_page_offset;
de7d789a
CO		 2376 vunmap(q);
2377 free_pio_guest_pages(vcpu);
2378 return 0;
2379}
2380
2381int complete_pio(struct kvm_vcpu *vcpu)
2382{
ad312c7c 2383 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2384 long delta;
2385 int r;
5fdbf976 2386 unsigned long val;
de7d789a
CO		 2387
2388 if (!io->string) {
5fdbf976
MT		 2389 if (io->in) {
2390 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2391 memcpy(&val, vcpu->arch.pio_data, io->size);
2392 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2393 }
de7d789a
CO		 2394 } else {
2395 if (io->in) {
2396 r = pio_copy_data(vcpu);
5fdbf976 2397 if (r)
de7d789a 2398 return r;
de7d789a
CO		 2399 }
2400
2401 delta = 1;
2402 if (io->rep) {
2403 delta *= io->cur_count;
2404 /*
2405 * The size of the register should really depend on
2406 * current address size.
2407 */
5fdbf976
MT		 2408 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2409 val -= delta;
2410 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 2411 }
2412 if (io->down)
2413 delta = -delta;
2414 delta *= io->size;
5fdbf976
MT		 2415 if (io->in) {
2416 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2417 val += delta;
2418 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2419 } else {
2420 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2421 val += delta;
2422 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2423 }
de7d789a
CO		 2424 }
2425
de7d789a
CO		 2426 io->count -= io->cur_count;
2427 io->cur_count = 0;
2428
2429 return 0;
2430}
2431
2432static void kernel_pio(struct kvm_io_device *pio_dev,
2433 struct kvm_vcpu *vcpu,
2434 void *pd)
2435{
2436 /* TODO: String I/O for in kernel device */
2437
2438 mutex_lock(&vcpu->kvm->lock);
ad312c7c
ZX		 2439 if (vcpu->arch.pio.in)
2440 kvm_iodevice_read(pio_dev, vcpu->arch.pio.port,
2441 vcpu->arch.pio.size,
de7d789a
CO		 2442 pd);
2443 else
ad312c7c
ZX		 2444 kvm_iodevice_write(pio_dev, vcpu->arch.pio.port,
2445 vcpu->arch.pio.size,
de7d789a
CO		 2446 pd);
2447 mutex_unlock(&vcpu->kvm->lock);
2448}
2449
2450static void pio_string_write(struct kvm_io_device *pio_dev,
2451 struct kvm_vcpu *vcpu)
2452{
ad312c7c
ZX		 2453 struct kvm_pio_request *io = &vcpu->arch.pio;
2454 void *pd = vcpu->arch.pio_data;
de7d789a
CO		 2455 int i;
2456
2457 mutex_lock(&vcpu->kvm->lock);
2458 for (i = 0; i < io->cur_count; i++) {
2459 kvm_iodevice_write(pio_dev, io->port,
2460 io->size,
2461 pd);
2462 pd += io->size;
2463 }
2464 mutex_unlock(&vcpu->kvm->lock);
2465}
2466
2467static struct kvm_io_device *vcpu_find_pio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2468 gpa_t addr, int len,
2469 int is_write)
de7d789a 2470{
92760499 2471 return kvm_io_bus_find_dev(&vcpu->kvm->pio_bus, addr, len, is_write);
de7d789a
CO		 2472}
2473
2474int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2475 int size, unsigned port)
2476{
2477 struct kvm_io_device *pio_dev;
5fdbf976 2478 unsigned long val;
de7d789a
CO		 2479
2480 vcpu->run->exit_reason = KVM_EXIT_IO;
2481 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2482 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2483 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2484 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2485 vcpu->run->io.port = vcpu->arch.pio.port = port;
2486 vcpu->arch.pio.in = in;
2487 vcpu->arch.pio.string = 0;
2488 vcpu->arch.pio.down = 0;
2489 vcpu->arch.pio.guest_page_offset = 0;
2490 vcpu->arch.pio.rep = 0;
de7d789a 2491
2714d1d3
FEL		 2492 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2493 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2494 handler);
2495 else
2496 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2497 handler);
2498
5fdbf976
MT		 2499 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2500 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a 2501
92760499 2502 pio_dev = vcpu_find_pio_dev(vcpu, port, size, !in);
de7d789a 2503 if (pio_dev) {
ad312c7c 2504 kernel_pio(pio_dev, vcpu, vcpu->arch.pio_data);
de7d789a
CO		 2505 complete_pio(vcpu);
2506 return 1;
2507 }
2508 return 0;
2509}
2510EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2511
2512int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2513 int size, unsigned long count, int down,
2514 gva_t address, int rep, unsigned port)
2515{
2516 unsigned now, in_page;
2517 int i, ret = 0;
2518 int nr_pages = 1;
2519 struct page *page;
2520 struct kvm_io_device *pio_dev;
2521
2522 vcpu->run->exit_reason = KVM_EXIT_IO;
2523 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2524 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2525 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2526 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2527 vcpu->run->io.port = vcpu->arch.pio.port = port;
2528 vcpu->arch.pio.in = in;
2529 vcpu->arch.pio.string = 1;
2530 vcpu->arch.pio.down = down;
2531 vcpu->arch.pio.guest_page_offset = offset_in_page(address);
2532 vcpu->arch.pio.rep = rep;
de7d789a 2533
2714d1d3
FEL		 2534 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2535 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2536 handler);
2537 else
2538 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2539 handler);
2540
de7d789a
CO		 2541 if (!count) {
2542 kvm_x86_ops->skip_emulated_instruction(vcpu);
2543 return 1;
2544 }
2545
2546 if (!down)
2547 in_page = PAGE_SIZE - offset_in_page(address);
2548 else
2549 in_page = offset_in_page(address) + size;
2550 now = min(count, (unsigned long)in_page / size);
2551 if (!now) {
2552 /*
2553 * String I/O straddles page boundary. Pin two guest pages
2554 * so that we satisfy atomicity constraints. Do just one
2555 * transaction to avoid complexity.
2556 */
2557 nr_pages = 2;
2558 now = 1;
2559 }
2560 if (down) {
2561 /*
2562 * String I/O in reverse. Yuck. Kill the guest, fix later.
2563 */
2564 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 2565 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2566 return 1;
2567 }
2568 vcpu->run->io.count = now;
ad312c7c 2569 vcpu->arch.pio.cur_count = now;
de7d789a 2570
ad312c7c 2571 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 2572 kvm_x86_ops->skip_emulated_instruction(vcpu);
2573
2574 for (i = 0; i < nr_pages; ++i) {
de7d789a 2575 page = gva_to_page(vcpu, address + i * PAGE_SIZE);
ad312c7c 2576 vcpu->arch.pio.guest_pages[i] = page;
de7d789a 2577 if (!page) {
c1a5d4f9 2578 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2579 free_pio_guest_pages(vcpu);
2580 return 1;
2581 }
2582 }
2583
92760499
LV		 2584 pio_dev = vcpu_find_pio_dev(vcpu, port,
2585 vcpu->arch.pio.cur_count,
2586 !vcpu->arch.pio.in);
ad312c7c 2587 if (!vcpu->arch.pio.in) {
de7d789a
CO		 2588 /* string PIO write */
2589 ret = pio_copy_data(vcpu);
2590 if (ret >= 0 && pio_dev) {
2591 pio_string_write(pio_dev, vcpu);
2592 complete_pio(vcpu);
ad312c7c 2593 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 2594 ret = 1;
2595 }
2596 } else if (pio_dev)
2597 pr_unimpl(vcpu, "no string pio read support yet, "
2598 "port %x size %d count %ld\n",
2599 port, size, count);
2600
2601 return ret;
2602}
2603EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
2604
f8c16bba 2605int kvm_arch_init(void *opaque)
043405e1 2606{
56c6d28a 2607 int r;
f8c16bba
ZX		 2608 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
2609
f8c16bba
ZX		 2610 if (kvm_x86_ops) {
2611 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 2612 r = -EEXIST;
2613 goto out;
f8c16bba
ZX		 2614 }
2615
2616 if (!ops->cpu_has_kvm_support()) {
2617 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 2618 r = -EOPNOTSUPP;
2619 goto out;
f8c16bba
ZX		 2620 }
2621 if (ops->disabled_by_bios()) {
2622 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 2623 r = -EOPNOTSUPP;
2624 goto out;
f8c16bba
ZX		 2625 }
2626
97db56ce
AK		 2627 r = kvm_mmu_module_init();
2628 if (r)
2629 goto out;
2630
2631 kvm_init_msr_list();
2632
f8c16bba 2633 kvm_x86_ops = ops;
56c6d28a 2634 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 2635 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
2636 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
64d4d521 2637 PT_DIRTY_MASK, PT64_NX_MASK, 0, 0);
f8c16bba 2638 return 0;
56c6d28a
ZX		 2639
2640out:
56c6d28a 2641 return r;
043405e1 2642}
8776e519 2643
f8c16bba
ZX		 2644void kvm_arch_exit(void)
2645{
2646 kvm_x86_ops = NULL;
56c6d28a
ZX		 2647 kvm_mmu_module_exit();
2648}
f8c16bba 2649
8776e519
HB		 2650int kvm_emulate_halt(struct kvm_vcpu *vcpu)
2651{
2652 ++vcpu->stat.halt_exits;
2714d1d3 2653 KVMTRACE_0D(HLT, vcpu, handler);
8776e519 2654 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 2655 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 2656 return 1;
2657 } else {
2658 vcpu->run->exit_reason = KVM_EXIT_HLT;
2659 return 0;
2660 }
2661}
2662EXPORT_SYMBOL_GPL(kvm_emulate_halt);
2663
2f333bcb
MT		 2664static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
2665 unsigned long a1)
2666{
2667 if (is_long_mode(vcpu))
2668 return a0;
2669 else
2670 return a0 | ((gpa_t)a1 << 32);
2671}
2672
8776e519
HB		 2673int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
2674{
2675 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 2676 int r = 1;
8776e519 2677
5fdbf976
MT		 2678 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
2679 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
2680 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
2681 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
2682 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 2683
2714d1d3
FEL		 2684 KVMTRACE_1D(VMMCALL, vcpu, (u32)nr, handler);
2685
8776e519
HB		 2686 if (!is_long_mode(vcpu)) {
2687 nr &= 0xFFFFFFFF;
2688 a0 &= 0xFFFFFFFF;
2689 a1 &= 0xFFFFFFFF;
2690 a2 &= 0xFFFFFFFF;
2691 a3 &= 0xFFFFFFFF;
2692 }
2693
2694 switch (nr) {
b93463aa
AK		 2695 case KVM_HC_VAPIC_POLL_IRQ:
2696 ret = 0;
2697 break;
2f333bcb
MT		 2698 case KVM_HC_MMU_OP:
2699 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
2700 break;
8776e519
HB		 2701 default:
2702 ret = -KVM_ENOSYS;
2703 break;
2704 }
5fdbf976 2705 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 2706 ++vcpu->stat.hypercalls;
2f333bcb 2707 return r;
8776e519
HB		 2708}
2709EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
2710
2711int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
2712{
2713 char instruction[3];
2714 int ret = 0;
5fdbf976 2715 unsigned long rip = kvm_rip_read(vcpu);
8776e519 2716
8776e519
HB		 2717
2718 /*
2719 * Blow out the MMU to ensure that no other VCPU has an active mapping
2720 * to ensure that the updated hypercall appears atomically across all
2721 * VCPUs.
2722 */
2723 kvm_mmu_zap_all(vcpu->kvm);
2724
8776e519 2725 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 2726 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 2727 != X86EMUL_CONTINUE)
2728 ret = -EFAULT;
2729
8776e519
HB		 2730 return ret;
2731}
2732
2733static u64 mk_cr_64(u64 curr_cr, u32 new_val)
2734{
2735 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
2736}
2737
2738void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2739{
2740 struct descriptor_table dt = { limit, base };
2741
2742 kvm_x86_ops->set_gdt(vcpu, &dt);
2743}
2744
2745void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2746{
2747 struct descriptor_table dt = { limit, base };
2748
2749 kvm_x86_ops->set_idt(vcpu, &dt);
2750}
2751
2752void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
2753 unsigned long *rflags)
2754{
2d3ad1f4 2755 kvm_lmsw(vcpu, msw);
8776e519
HB		 2756 *rflags = kvm_x86_ops->get_rflags(vcpu);
2757}
2758
2759unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
2760{
54e445ca
JR		 2761 unsigned long value;
2762
8776e519
HB		 2763 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
2764 switch (cr) {
2765 case 0:
54e445ca
JR		 2766 value = vcpu->arch.cr0;
2767 break;
8776e519 2768 case 2:
54e445ca
JR		 2769 value = vcpu->arch.cr2;
2770 break;
8776e519 2771 case 3:
54e445ca
JR		 2772 value = vcpu->arch.cr3;
2773 break;
8776e519 2774 case 4:
54e445ca
JR		 2775 value = vcpu->arch.cr4;
2776 break;
152ff9be 2777 case 8:
54e445ca
JR		 2778 value = kvm_get_cr8(vcpu);
2779 break;
8776e519 2780 default:
b8688d51 2781 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2782 return 0;
2783 }
54e445ca
JR		 2784 KVMTRACE_3D(CR_READ, vcpu, (u32)cr, (u32)value,
2785 (u32)((u64)value >> 32), handler);
2786
2787 return value;
8776e519
HB		 2788}
2789
2790void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
2791 unsigned long *rflags)
2792{
54e445ca
JR		 2793 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)val,
2794 (u32)((u64)val >> 32), handler);
2795
8776e519
HB		 2796 switch (cr) {
2797 case 0:
2d3ad1f4 2798 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 2799 *rflags = kvm_x86_ops->get_rflags(vcpu);
2800 break;
2801 case 2:
ad312c7c 2802 vcpu->arch.cr2 = val;
8776e519
HB		 2803 break;
2804 case 3:
2d3ad1f4 2805 kvm_set_cr3(vcpu, val);
8776e519
HB		 2806 break;
2807 case 4:
2d3ad1f4 2808 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 2809 break;
152ff9be 2810 case 8:
2d3ad1f4 2811 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 2812 break;
8776e519 2813 default:
b8688d51 2814 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2815 }
2816}
2817
07716717
DK		 2818static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
2819{
ad312c7c
ZX		 2820 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
2821 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 2822
2823 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
2824 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 2825 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 2826 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 2827 if (ej->function == e->function) {
2828 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
2829 return j;
2830 }
2831 }
2832 return 0; /* silence gcc, even though control never reaches here */
2833}
2834
2835/* find an entry with matching function, matching index (if needed), and that
2836 * should be read next (if it's stateful) */
2837static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
2838 u32 function, u32 index)
2839{
2840 if (e->function != function)
2841 return 0;
2842 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
2843 return 0;
2844 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
2845 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
2846 return 0;
2847 return 1;
2848}
2849
d8017474
AG		 2850struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
2851 u32 function, u32 index)
8776e519
HB		 2852{
2853 int i;
d8017474 2854 struct kvm_cpuid_entry2 *best = NULL;
8776e519 2855
ad312c7c 2856 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 2857 struct kvm_cpuid_entry2 *e;
2858
ad312c7c 2859 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 2860 if (is_matching_cpuid_entry(e, function, index)) {
2861 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
2862 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 2863 best = e;
2864 break;
2865 }
2866 /*
2867 * Both basic or both extended?
2868 */
2869 if (((e->function ^ function) & 0x80000000) == 0)
2870 if (!best || e->function > best->function)
2871 best = e;
2872 }
d8017474
AG		 2873
2874 return best;
2875}
2876
2877void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
2878{
2879 u32 function, index;
2880 struct kvm_cpuid_entry2 *best;
2881
2882 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
2883 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
2884 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
2885 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
2886 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
2887 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
2888 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 2889 if (best) {
5fdbf976
MT		 2890 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
2891 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
2892 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
2893 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 2894 }
8776e519 2895 kvm_x86_ops->skip_emulated_instruction(vcpu);
2714d1d3 2896 KVMTRACE_5D(CPUID, vcpu, function,
5fdbf976
MT		 2897 (u32)kvm_register_read(vcpu, VCPU_REGS_RAX),
2898 (u32)kvm_register_read(vcpu, VCPU_REGS_RBX),
2899 (u32)kvm_register_read(vcpu, VCPU_REGS_RCX),
2900 (u32)kvm_register_read(vcpu, VCPU_REGS_RDX), handler);
8776e519
HB		 2901}
2902EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 2903
b6c7a5dc
HB		 2904/*
2905 * Check if userspace requested an interrupt window, and that the
2906 * interrupt window is open.
2907 *
2908 * No need to exit to userspace if we already have an interrupt queued.
2909 */
2910static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
2911 struct kvm_run *kvm_run)
2912{
ad312c7c 2913 return (!vcpu->arch.irq_summary &&
b6c7a5dc 2914 kvm_run->request_interrupt_window &&
ad312c7c 2915 vcpu->arch.interrupt_window_open &&
b6c7a5dc
HB		 2916 (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF));
2917}
2918
2919static void post_kvm_run_save(struct kvm_vcpu *vcpu,
2920 struct kvm_run *kvm_run)
2921{
2922 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 2923 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 2924 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 2925 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 2926 kvm_run->ready_for_interrupt_injection = 1;
4531220b 2927 else
b6c7a5dc 2928 kvm_run->ready_for_interrupt_injection =
ad312c7c
ZX		 2929 (vcpu->arch.interrupt_window_open &&
2930 vcpu->arch.irq_summary == 0);
b6c7a5dc
HB		 2931}
2932
b93463aa
AK		 2933static void vapic_enter(struct kvm_vcpu *vcpu)
2934{
2935 struct kvm_lapic *apic = vcpu->arch.apic;
2936 struct page *page;
2937
2938 if (!apic || !apic->vapic_addr)
2939 return;
2940
2941 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 2942
2943 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 2944}
2945
2946static void vapic_exit(struct kvm_vcpu *vcpu)
2947{
2948 struct kvm_lapic *apic = vcpu->arch.apic;
2949
2950 if (!apic || !apic->vapic_addr)
2951 return;
2952
f8b78fa3 2953 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 2954 kvm_release_page_dirty(apic->vapic_page);
2955 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 2956 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 2957}
2958
d7690175 2959static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
b6c7a5dc
HB		 2960{
2961 int r;
2962
2e53d63a
MT		 2963 if (vcpu->requests)
2964 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
2965 kvm_mmu_unload(vcpu);
2966
b6c7a5dc
HB		 2967 r = kvm_mmu_reload(vcpu);
2968 if (unlikely(r))
2969 goto out;
2970
2f52d58c
AK		 2971 if (vcpu->requests) {
2972 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 2973 __kvm_migrate_timers(vcpu);
4731d4c7
MT		 2974 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
2975 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 2976 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
2977 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 2978 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
2979 &vcpu->requests)) {
2980 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
2981 r = 0;
2982 goto out;
2983 }
71c4dfaf
JR		 2984 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
2985 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2986 r = 0;
2987 goto out;
2988 }
2f52d58c 2989 }
b93463aa 2990
06e05645 2991 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
b6c7a5dc
HB		 2992 kvm_inject_pending_timer_irqs(vcpu);
2993
2994 preempt_disable();
2995
2996 kvm_x86_ops->prepare_guest_switch(vcpu);
2997 kvm_load_guest_fpu(vcpu);
2998
2999 local_irq_disable();
3000
d7690175 3001 if (vcpu->requests || need_resched() || signal_pending(current)) {
6c142801
AK		 3002 local_irq_enable();
3003 preempt_enable();
3004 r = 1;
3005 goto out;
3006 }
3007
e9571ed5
MT		 3008 vcpu->guest_mode = 1;
3009 /*
3010 * Make sure that guest_mode assignment won't happen after
3011 * testing the pending IRQ vector bitmap.
3012 */
3013 smp_wmb();
3014
ad312c7c 3015 if (vcpu->arch.exception.pending)
298101da
AK		 3016 __queue_exception(vcpu);
3017 else if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3018 kvm_x86_ops->inject_pending_irq(vcpu);
eb9774f0 3019 else
b6c7a5dc
HB		 3020 kvm_x86_ops->inject_pending_vectors(vcpu, kvm_run);
3021
b93463aa
AK		 3022 kvm_lapic_sync_to_vapic(vcpu);
3023
3200f405
MT		 3024 up_read(&vcpu->kvm->slots_lock);
3025
b6c7a5dc
HB		 3026 kvm_guest_enter();
3027
42dbaa5a
JK		 3028 get_debugreg(vcpu->arch.host_dr6, 6);
3029 get_debugreg(vcpu->arch.host_dr7, 7);
3030 if (unlikely(vcpu->arch.switch_db_regs)) {
3031 get_debugreg(vcpu->arch.host_db[0], 0);
3032 get_debugreg(vcpu->arch.host_db[1], 1);
3033 get_debugreg(vcpu->arch.host_db[2], 2);
3034 get_debugreg(vcpu->arch.host_db[3], 3);
3035
3036 set_debugreg(0, 7);
3037 set_debugreg(vcpu->arch.eff_db[0], 0);
3038 set_debugreg(vcpu->arch.eff_db[1], 1);
3039 set_debugreg(vcpu->arch.eff_db[2], 2);
3040 set_debugreg(vcpu->arch.eff_db[3], 3);
3041 }
b6c7a5dc 3042
2714d1d3 3043 KVMTRACE_0D(VMENTRY, vcpu, entryexit);
b6c7a5dc
HB		 3044 kvm_x86_ops->run(vcpu, kvm_run);
3045
42dbaa5a
JK		 3046 if (unlikely(vcpu->arch.switch_db_regs)) {
3047 set_debugreg(0, 7);
3048 set_debugreg(vcpu->arch.host_db[0], 0);
3049 set_debugreg(vcpu->arch.host_db[1], 1);
3050 set_debugreg(vcpu->arch.host_db[2], 2);
3051 set_debugreg(vcpu->arch.host_db[3], 3);
3052 }
3053 set_debugreg(vcpu->arch.host_dr6, 6);
3054 set_debugreg(vcpu->arch.host_dr7, 7);
3055
b6c7a5dc
HB		 3056 vcpu->guest_mode = 0;
3057 local_irq_enable();
3058
3059 ++vcpu->stat.exits;
3060
3061 /*
3062 * We must have an instruction between local_irq_enable() and
3063 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3064 * the interrupt shadow. The stat.exits increment will do nicely.
3065 * But we need to prevent reordering, hence this barrier():
3066 */
3067 barrier();
3068
3069 kvm_guest_exit();
3070
3071 preempt_enable();
3072
3200f405
MT		 3073 down_read(&vcpu->kvm->slots_lock);
3074
b6c7a5dc
HB		 3075 /*
3076 * Profile KVM exit RIPs:
3077 */
3078 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 3079 unsigned long rip = kvm_rip_read(vcpu);
3080 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 3081 }
3082
ad312c7c
ZX		 3083 if (vcpu->arch.exception.pending && kvm_x86_ops->exception_injected(vcpu))
3084 vcpu->arch.exception.pending = false;
298101da 3085
b93463aa
AK		 3086 kvm_lapic_sync_from_vapic(vcpu);
3087
b6c7a5dc 3088 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
d7690175
MT		 3089out:
3090 return r;
3091}
b6c7a5dc 3092
d7690175
MT		 3093static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3094{
3095 int r;
3096
3097 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 3098 pr_debug("vcpu %d received sipi with vector # %x\n",
3099 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 3100 kvm_lapic_reset(vcpu);
5f179287 3101 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 3102 if (r)
3103 return r;
3104 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 3105 }
3106
d7690175
MT		 3107 down_read(&vcpu->kvm->slots_lock);
3108 vapic_enter(vcpu);
3109
3110 r = 1;
3111 while (r > 0) {
af2152f5 3112 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
d7690175
MT		 3113 r = vcpu_enter_guest(vcpu, kvm_run);
3114 else {
3115 up_read(&vcpu->kvm->slots_lock);
3116 kvm_vcpu_block(vcpu);
3117 down_read(&vcpu->kvm->slots_lock);
3118 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
3119 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
3120 vcpu->arch.mp_state =
3121 KVM_MP_STATE_RUNNABLE;
3122 if (vcpu->arch.mp_state != KVM_MP_STATE_RUNNABLE)
3123 r = -EINTR;
3124 }
3125
3126 if (r > 0) {
3127 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
3128 r = -EINTR;
3129 kvm_run->exit_reason = KVM_EXIT_INTR;
3130 ++vcpu->stat.request_irq_exits;
3131 }
3132 if (signal_pending(current)) {
3133 r = -EINTR;
3134 kvm_run->exit_reason = KVM_EXIT_INTR;
3135 ++vcpu->stat.signal_exits;
3136 }
3137 if (need_resched()) {
3138 up_read(&vcpu->kvm->slots_lock);
3139 kvm_resched(vcpu);
3140 down_read(&vcpu->kvm->slots_lock);
3141 }
3142 }
b6c7a5dc
HB		 3143 }
3144
d7690175 3145 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3146 post_kvm_run_save(vcpu, kvm_run);
3147
b93463aa
AK		 3148 vapic_exit(vcpu);
3149
b6c7a5dc
HB		 3150 return r;
3151}
3152
3153int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3154{
3155 int r;
3156 sigset_t sigsaved;
3157
3158 vcpu_load(vcpu);
3159
ac9f6dc0
AK		 3160 if (vcpu->sigset_active)
3161 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
3162
a4535290 3163 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 3164 kvm_vcpu_block(vcpu);
d7690175 3165 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 3166 r = -EAGAIN;
3167 goto out;
b6c7a5dc
HB		 3168 }
3169
b6c7a5dc
HB		 3170 /* re-sync apic's tpr */
3171 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 3172 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 3173
ad312c7c 3174 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 3175 r = complete_pio(vcpu);
3176 if (r)
3177 goto out;
3178 }
3179#if CONFIG_HAS_IOMEM
3180 if (vcpu->mmio_needed) {
3181 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3182 vcpu->mmio_read_completed = 1;
3183 vcpu->mmio_needed = 0;
3200f405
MT		 3184
3185 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc 3186 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 3187 vcpu->arch.mmio_fault_cr2, 0,
3188 EMULTYPE_NO_DECODE);
3200f405 3189 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3190 if (r == EMULATE_DO_MMIO) {
3191 /*
3192 * Read-modify-write. Back to userspace.
3193 */
3194 r = 0;
3195 goto out;
3196 }
3197 }
3198#endif
5fdbf976
MT		 3199 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3200 kvm_register_write(vcpu, VCPU_REGS_RAX,
3201 kvm_run->hypercall.ret);
b6c7a5dc
HB		 3202
3203 r = __vcpu_run(vcpu, kvm_run);
3204
3205out:
3206 if (vcpu->sigset_active)
3207 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3208
3209 vcpu_put(vcpu);
3210 return r;
3211}
3212
3213int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3214{
3215 vcpu_load(vcpu);
3216
5fdbf976
MT		 3217 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3218 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3219 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3220 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3221 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3222 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3223 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3224 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 3225#ifdef CONFIG_X86_64
5fdbf976
MT		 3226 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3227 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3228 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3229 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3230 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3231 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3232 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3233 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 3234#endif
3235
5fdbf976 3236 regs->rip = kvm_rip_read(vcpu);
b6c7a5dc
HB		 3237 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3238
3239 /*
3240 * Don't leak debug flags in case they were set for guest debugging
3241 */
d0bfb940 3242 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
b6c7a5dc
HB		 3243 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3244
3245 vcpu_put(vcpu);
3246
3247 return 0;
3248}
3249
3250int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3251{
3252 vcpu_load(vcpu);
3253
5fdbf976
MT		 3254 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3255 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3256 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3257 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3258 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3259 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3260 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3261 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 3262#ifdef CONFIG_X86_64
5fdbf976
MT		 3263 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3264 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3265 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3266 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3267 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3268 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3269 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3270 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
3271
b6c7a5dc
HB		 3272#endif
3273
5fdbf976 3274 kvm_rip_write(vcpu, regs->rip);
b6c7a5dc
HB		 3275 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3276
b6c7a5dc 3277
b4f14abd
JK		 3278 vcpu->arch.exception.pending = false;
3279
b6c7a5dc
HB		 3280 vcpu_put(vcpu);
3281
3282 return 0;
3283}
3284
3e6e0aab
GT		 3285void kvm_get_segment(struct kvm_vcpu *vcpu,
3286 struct kvm_segment *var, int seg)
b6c7a5dc 3287{
14af3f3c 3288 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 3289}
3290
3291void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3292{
3293 struct kvm_segment cs;
3294
3e6e0aab 3295 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 3296 *db = cs.db;
3297 *l = cs.l;
3298}
3299EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3300
3301int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3302 struct kvm_sregs *sregs)
3303{
3304 struct descriptor_table dt;
3305 int pending_vec;
3306
3307 vcpu_load(vcpu);
3308
3e6e0aab
GT		 3309 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3310 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3311 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3312 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3313 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3314 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3315
3e6e0aab
GT		 3316 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3317 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3318
3319 kvm_x86_ops->get_idt(vcpu, &dt);
3320 sregs->idt.limit = dt.limit;
3321 sregs->idt.base = dt.base;
3322 kvm_x86_ops->get_gdt(vcpu, &dt);
3323 sregs->gdt.limit = dt.limit;
3324 sregs->gdt.base = dt.base;
3325
3326 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3327 sregs->cr0 = vcpu->arch.cr0;
3328 sregs->cr2 = vcpu->arch.cr2;
3329 sregs->cr3 = vcpu->arch.cr3;
3330 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3331 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3332 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3333 sregs->apic_base = kvm_get_apic_base(vcpu);
3334
3335 if (irqchip_in_kernel(vcpu->kvm)) {
3336 memset(sregs->interrupt_bitmap, 0,
3337 sizeof sregs->interrupt_bitmap);
3338 pending_vec = kvm_x86_ops->get_irq(vcpu);
3339 if (pending_vec >= 0)
3340 set_bit(pending_vec,
3341 (unsigned long *)sregs->interrupt_bitmap);
3342 } else
ad312c7c 3343 memcpy(sregs->interrupt_bitmap, vcpu->arch.irq_pending,
b6c7a5dc
HB		 3344 sizeof sregs->interrupt_bitmap);
3345
3346 vcpu_put(vcpu);
3347
3348 return 0;
3349}
3350
62d9f0db
MT		 3351int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3352 struct kvm_mp_state *mp_state)
3353{
3354 vcpu_load(vcpu);
3355 mp_state->mp_state = vcpu->arch.mp_state;
3356 vcpu_put(vcpu);
3357 return 0;
3358}
3359
3360int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3361 struct kvm_mp_state *mp_state)
3362{
3363 vcpu_load(vcpu);
3364 vcpu->arch.mp_state = mp_state->mp_state;
3365 vcpu_put(vcpu);
3366 return 0;
3367}
3368
3e6e0aab 3369static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 3370 struct kvm_segment *var, int seg)
3371{
14af3f3c 3372 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 3373}
3374
37817f29
IE		 3375static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3376 struct kvm_segment *kvm_desct)
3377{
3378 kvm_desct->base = seg_desc->base0;
3379 kvm_desct->base |= seg_desc->base1 << 16;
3380 kvm_desct->base |= seg_desc->base2 << 24;
3381 kvm_desct->limit = seg_desc->limit0;
3382 kvm_desct->limit |= seg_desc->limit << 16;
c93cd3a5
MT		 3383 if (seg_desc->g) {
3384 kvm_desct->limit <<= 12;
3385 kvm_desct->limit |= 0xfff;
3386 }
37817f29
IE		 3387 kvm_desct->selector = selector;
3388 kvm_desct->type = seg_desc->type;
3389 kvm_desct->present = seg_desc->p;
3390 kvm_desct->dpl = seg_desc->dpl;
3391 kvm_desct->db = seg_desc->d;
3392 kvm_desct->s = seg_desc->s;
3393 kvm_desct->l = seg_desc->l;
3394 kvm_desct->g = seg_desc->g;
3395 kvm_desct->avl = seg_desc->avl;
3396 if (!selector)
3397 kvm_desct->unusable = 1;
3398 else
3399 kvm_desct->unusable = 0;
3400 kvm_desct->padding = 0;
3401}
3402
b8222ad2
AS		 3403static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
3404 u16 selector,
3405 struct descriptor_table *dtable)
37817f29
IE		 3406{
3407 if (selector & 1 << 2) {
3408 struct kvm_segment kvm_seg;
3409
3e6e0aab 3410 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 3411
3412 if (kvm_seg.unusable)
3413 dtable->limit = 0;
3414 else
3415 dtable->limit = kvm_seg.limit;
3416 dtable->base = kvm_seg.base;
3417 }
3418 else
3419 kvm_x86_ops->get_gdt(vcpu, dtable);
3420}
3421
3422/* allowed just for 8 bytes segments */
3423static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3424 struct desc_struct *seg_desc)
3425{
98899aa0 3426 gpa_t gpa;
37817f29
IE		 3427 struct descriptor_table dtable;
3428 u16 index = selector >> 3;
3429
b8222ad2 3430 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3431
3432 if (dtable.limit < index * 8 + 7) {
3433 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
3434 return 1;
3435 }
98899aa0
MT		 3436 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3437 gpa += index * 8;
3438 return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3439}
3440
3441/* allowed just for 8 bytes segments */
3442static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3443 struct desc_struct *seg_desc)
3444{
98899aa0 3445 gpa_t gpa;
37817f29
IE		 3446 struct descriptor_table dtable;
3447 u16 index = selector >> 3;
3448
b8222ad2 3449 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3450
3451 if (dtable.limit < index * 8 + 7)
3452 return 1;
98899aa0
MT		 3453 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3454 gpa += index * 8;
3455 return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3456}
3457
3458static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
3459 struct desc_struct *seg_desc)
3460{
3461 u32 base_addr;
3462
3463 base_addr = seg_desc->base0;
3464 base_addr |= (seg_desc->base1 << 16);
3465 base_addr |= (seg_desc->base2 << 24);
3466
98899aa0 3467 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 3468}
3469
37817f29
IE		 3470static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
3471{
3472 struct kvm_segment kvm_seg;
3473
3e6e0aab 3474 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3475 return kvm_seg.selector;
3476}
3477
3478static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
3479 u16 selector,
3480 struct kvm_segment *kvm_seg)
3481{
3482 struct desc_struct seg_desc;
3483
3484 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
3485 return 1;
3486 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
3487 return 0;
3488}
3489
2259e3a7 3490static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 3491{
3492 struct kvm_segment segvar = {
3493 .base = selector << 4,
3494 .limit = 0xffff,
3495 .selector = selector,
3496 .type = 3,
3497 .present = 1,
3498 .dpl = 3,
3499 .db = 0,
3500 .s = 1,
3501 .l = 0,
3502 .g = 0,
3503 .avl = 0,
3504 .unusable = 0,
3505 };
3506 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
3507 return 0;
3508}
3509
3e6e0aab
GT		 3510int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3511 int type_bits, int seg)
37817f29
IE		 3512{
3513 struct kvm_segment kvm_seg;
3514
f4bbd9aa
AK		 3515 if (!(vcpu->arch.cr0 & X86_CR0_PE))
3516 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 3517 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
3518 return 1;
3519 kvm_seg.type |= type_bits;
3520
3521 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
3522 seg != VCPU_SREG_LDTR)
3523 if (!kvm_seg.s)
3524 kvm_seg.unusable = 1;
3525
3e6e0aab 3526 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3527 return 0;
3528}
3529
3530static void save_state_to_tss32(struct kvm_vcpu *vcpu,
3531 struct tss_segment_32 *tss)
3532{
3533 tss->cr3 = vcpu->arch.cr3;
5fdbf976 3534 tss->eip = kvm_rip_read(vcpu);
37817f29 3535 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 3536 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3537 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3538 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3539 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3540 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3541 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3542 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3543 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 3544 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3545 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3546 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3547 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3548 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
3549 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
3550 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3551 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3552}
3553
3554static int load_state_from_tss32(struct kvm_vcpu *vcpu,
3555 struct tss_segment_32 *tss)
3556{
3557 kvm_set_cr3(vcpu, tss->cr3);
3558
5fdbf976 3559 kvm_rip_write(vcpu, tss->eip);
37817f29
IE		 3560 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
3561
5fdbf976
MT		 3562 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
3563 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
3564 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
3565 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
3566 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
3567 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
3568 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
3569 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 3570
3e6e0aab 3571 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 3572 return 1;
3573
3e6e0aab 3574 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 3575 return 1;
3576
3e6e0aab 3577 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 3578 return 1;
3579
3e6e0aab 3580 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 3581 return 1;
3582
3e6e0aab 3583 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 3584 return 1;
3585
3e6e0aab 3586 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 3587 return 1;
3588
3e6e0aab 3589 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 3590 return 1;
3591 return 0;
3592}
3593
3594static void save_state_to_tss16(struct kvm_vcpu *vcpu,
3595 struct tss_segment_16 *tss)
3596{
5fdbf976 3597 tss->ip = kvm_rip_read(vcpu);
37817f29 3598 tss->flag = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 3599 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3600 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3601 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3602 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3603 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3604 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3605 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
3606 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 3607
3608 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3609 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3610 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3611 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3612 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3613 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3614}
3615
3616static int load_state_from_tss16(struct kvm_vcpu *vcpu,
3617 struct tss_segment_16 *tss)
3618{
5fdbf976 3619 kvm_rip_write(vcpu, tss->ip);
37817f29 3620 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 3621 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
3622 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
3623 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
3624 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
3625 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
3626 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
3627 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
3628 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 3629
3e6e0aab 3630 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 3631 return 1;
3632
3e6e0aab 3633 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 3634 return 1;
3635
3e6e0aab 3636 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 3637 return 1;
3638
3e6e0aab 3639 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 3640 return 1;
3641
3e6e0aab 3642 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 3643 return 1;
3644 return 0;
3645}
3646
8b2cf73c 3647static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
34198bf8 3648 u32 old_tss_base,
37817f29
IE		 3649 struct desc_struct *nseg_desc)
3650{
3651 struct tss_segment_16 tss_segment_16;
3652 int ret = 0;
3653
34198bf8
MT		 3654 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
3655 sizeof tss_segment_16))
37817f29
IE		 3656 goto out;
3657
3658 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 3659
34198bf8
MT		 3660 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
3661 sizeof tss_segment_16))
37817f29 3662 goto out;
34198bf8
MT		 3663
3664 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
3665 &tss_segment_16, sizeof tss_segment_16))
3666 goto out;
3667
37817f29
IE		 3668 if (load_state_from_tss16(vcpu, &tss_segment_16))
3669 goto out;
3670
3671 ret = 1;
3672out:
3673 return ret;
3674}
3675
8b2cf73c 3676static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
34198bf8 3677 u32 old_tss_base,
37817f29
IE		 3678 struct desc_struct *nseg_desc)
3679{
3680 struct tss_segment_32 tss_segment_32;
3681 int ret = 0;
3682
34198bf8
MT		 3683 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
3684 sizeof tss_segment_32))
37817f29
IE		 3685 goto out;
3686
3687 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 3688
34198bf8
MT		 3689 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
3690 sizeof tss_segment_32))
3691 goto out;
3692
3693 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
3694 &tss_segment_32, sizeof tss_segment_32))
37817f29 3695 goto out;
34198bf8 3696
37817f29
IE		 3697 if (load_state_from_tss32(vcpu, &tss_segment_32))
3698 goto out;
3699
3700 ret = 1;
3701out:
3702 return ret;
3703}
3704
3705int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
3706{
3707 struct kvm_segment tr_seg;
3708 struct desc_struct cseg_desc;
3709 struct desc_struct nseg_desc;
3710 int ret = 0;
34198bf8
MT		 3711 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
3712 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 3713
34198bf8 3714 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 3715
34198bf8
MT		 3716 /* FIXME: Handle errors. Failure to read either TSS or their
3717 * descriptors should generate a pagefault.
3718 */
37817f29
IE		 3719 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
3720 goto out;
3721
34198bf8 3722 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 3723 goto out;
3724
37817f29
IE		 3725 if (reason != TASK_SWITCH_IRET) {
3726 int cpl;
3727
3728 cpl = kvm_x86_ops->get_cpl(vcpu);
3729 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
3730 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
3731 return 1;
3732 }
3733 }
3734
3735 if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) {
3736 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
3737 return 1;
3738 }
3739
3740 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 3741 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 3742 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 3743 }
3744
3745 if (reason == TASK_SWITCH_IRET) {
3746 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3747 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
3748 }
3749
3750 kvm_x86_ops->skip_emulated_instruction(vcpu);
37817f29
IE		 3751
3752 if (nseg_desc.type & 8)
34198bf8 3753 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_base,
37817f29
IE		 3754 &nseg_desc);
3755 else
34198bf8 3756 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_base,
37817f29
IE		 3757 &nseg_desc);
3758
3759 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
3760 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3761 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
3762 }
3763
3764 if (reason != TASK_SWITCH_IRET) {
3fe913e7 3765 nseg_desc.type |= (1 << 1);
37817f29
IE		 3766 save_guest_segment_descriptor(vcpu, tss_selector,
3767 &nseg_desc);
3768 }
3769
3770 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
3771 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
3772 tr_seg.type = 11;
3e6e0aab 3773 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 3774out:
37817f29
IE		 3775 return ret;
3776}
3777EXPORT_SYMBOL_GPL(kvm_task_switch);
3778
b6c7a5dc
HB		 3779int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
3780 struct kvm_sregs *sregs)
3781{
3782 int mmu_reset_needed = 0;
3783 int i, pending_vec, max_bits;
3784 struct descriptor_table dt;
3785
3786 vcpu_load(vcpu);
3787
3788 dt.limit = sregs->idt.limit;
3789 dt.base = sregs->idt.base;
3790 kvm_x86_ops->set_idt(vcpu, &dt);
3791 dt.limit = sregs->gdt.limit;
3792 dt.base = sregs->gdt.base;
3793 kvm_x86_ops->set_gdt(vcpu, &dt);
3794
ad312c7c
ZX		 3795 vcpu->arch.cr2 = sregs->cr2;
3796 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
3797 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 3798
2d3ad1f4 3799 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 3800
ad312c7c 3801 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 3802 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 3803 kvm_set_apic_base(vcpu, sregs->apic_base);
3804
3805 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3806
ad312c7c 3807 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 3808 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 3809 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 3810
ad312c7c 3811 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 3812 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3813 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 3814 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 3815
3816 if (mmu_reset_needed)
3817 kvm_mmu_reset_context(vcpu);
3818
3819 if (!irqchip_in_kernel(vcpu->kvm)) {
ad312c7c
ZX		 3820 memcpy(vcpu->arch.irq_pending, sregs->interrupt_bitmap,
3821 sizeof vcpu->arch.irq_pending);
3822 vcpu->arch.irq_summary = 0;
3823 for (i = 0; i < ARRAY_SIZE(vcpu->arch.irq_pending); ++i)
3824 if (vcpu->arch.irq_pending[i])
3825 __set_bit(i, &vcpu->arch.irq_summary);
b6c7a5dc
HB		 3826 } else {
3827 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
3828 pending_vec = find_first_bit(
3829 (const unsigned long *)sregs->interrupt_bitmap,
3830 max_bits);
3831 /* Only pending external irq is handled here */
3832 if (pending_vec < max_bits) {
3833 kvm_x86_ops->set_irq(vcpu, pending_vec);
3834 pr_debug("Set back pending irq %d\n",
3835 pending_vec);
3836 }
e4825800 3837 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 3838 }
3839
3e6e0aab
GT		 3840 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3841 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3842 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3843 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3844 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3845 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3846
3e6e0aab
GT		 3847 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3848 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 3849
9c3e4aab
MT		 3850 /* Older userspace won't unhalt the vcpu on reset. */
3851 if (vcpu->vcpu_id == 0 && kvm_rip_read(vcpu) == 0xfff0 &&
3852 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3853 !(vcpu->arch.cr0 & X86_CR0_PE))
3854 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
3855
b6c7a5dc
HB		 3856 vcpu_put(vcpu);
3857
3858 return 0;
3859}
3860
d0bfb940
JK		 3861int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
3862 struct kvm_guest_debug *dbg)
b6c7a5dc 3863{
ae675ef0 3864 int i, r;
b6c7a5dc
HB		 3865
3866 vcpu_load(vcpu);
3867
ae675ef0
JK		 3868 if ((dbg->control & (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) ==
3869 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) {
3870 for (i = 0; i < KVM_NR_DB_REGS; ++i)
3871 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
3872 vcpu->arch.switch_db_regs =
3873 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
3874 } else {
3875 for (i = 0; i < KVM_NR_DB_REGS; i++)
3876 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
3877 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
3878 }
3879
b6c7a5dc
HB		 3880 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
3881
d0bfb940
JK		 3882 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
3883 kvm_queue_exception(vcpu, DB_VECTOR);
3884 else if (dbg->control & KVM_GUESTDBG_INJECT_BP)
3885 kvm_queue_exception(vcpu, BP_VECTOR);
3886
b6c7a5dc
HB		 3887 vcpu_put(vcpu);
3888
3889 return r;
3890}
3891
d0752060
HB		 3892/*
3893 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
3894 * we have asm/x86/processor.h
3895 */
3896struct fxsave {
3897 u16 cwd;
3898 u16 swd;
3899 u16 twd;
3900 u16 fop;
3901 u64 rip;
3902 u64 rdp;
3903 u32 mxcsr;
3904 u32 mxcsr_mask;
3905 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
3906#ifdef CONFIG_X86_64
3907 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
3908#else
3909 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
3910#endif
3911};
3912
8b006791
ZX		 3913/*
3914 * Translate a guest virtual address to a guest physical address.
3915 */
3916int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
3917 struct kvm_translation *tr)
3918{
3919 unsigned long vaddr = tr->linear_address;
3920 gpa_t gpa;
3921
3922 vcpu_load(vcpu);
72dc67a6 3923 down_read(&vcpu->kvm->slots_lock);
ad312c7c 3924 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 3925 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 3926 tr->physical_address = gpa;
3927 tr->valid = gpa != UNMAPPED_GVA;
3928 tr->writeable = 1;
3929 tr->usermode = 0;
8b006791
ZX		 3930 vcpu_put(vcpu);
3931
3932 return 0;
3933}
3934
d0752060
HB		 3935int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
3936{
ad312c7c 3937 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 3938
3939 vcpu_load(vcpu);
3940
3941 memcpy(fpu->fpr, fxsave->st_space, 128);
3942 fpu->fcw = fxsave->cwd;
3943 fpu->fsw = fxsave->swd;
3944 fpu->ftwx = fxsave->twd;
3945 fpu->last_opcode = fxsave->fop;
3946 fpu->last_ip = fxsave->rip;
3947 fpu->last_dp = fxsave->rdp;
3948 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
3949
3950 vcpu_put(vcpu);
3951
3952 return 0;
3953}
3954
3955int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
3956{
ad312c7c 3957 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 3958
3959 vcpu_load(vcpu);
3960
3961 memcpy(fxsave->st_space, fpu->fpr, 128);
3962 fxsave->cwd = fpu->fcw;
3963 fxsave->swd = fpu->fsw;
3964 fxsave->twd = fpu->ftwx;
3965 fxsave->fop = fpu->last_opcode;
3966 fxsave->rip = fpu->last_ip;
3967 fxsave->rdp = fpu->last_dp;
3968 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
3969
3970 vcpu_put(vcpu);
3971
3972 return 0;
3973}
3974
3975void fx_init(struct kvm_vcpu *vcpu)
3976{
3977 unsigned after_mxcsr_mask;
3978
bc1a34f1
AA		 3979 /*
3980 * Touch the fpu the first time in non atomic context as if
3981 * this is the first fpu instruction the exception handler
3982 * will fire before the instruction returns and it'll have to
3983 * allocate ram with GFP_KERNEL.
3984 */
3985 if (!used_math())
d6e88aec 3986 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 3987
d0752060
HB		 3988 /* Initialize guest FPU by resetting ours and saving into guest's */
3989 preempt_disable();
d6e88aec
AK		 3990 kvm_fx_save(&vcpu->arch.host_fx_image);
3991 kvm_fx_finit();
3992 kvm_fx_save(&vcpu->arch.guest_fx_image);
3993 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 3994 preempt_enable();
3995
ad312c7c 3996 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 3997 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 3998 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
3999 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 4000 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
4001}
4002EXPORT_SYMBOL_GPL(fx_init);
4003
4004void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
4005{
4006 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
4007 return;
4008
4009 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 4010 kvm_fx_save(&vcpu->arch.host_fx_image);
4011 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 4012}
4013EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
4014
4015void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
4016{
4017 if (!vcpu->guest_fpu_loaded)
4018 return;
4019
4020 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 4021 kvm_fx_save(&vcpu->arch.guest_fx_image);
4022 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 4023 ++vcpu->stat.fpu_reload;
d0752060
HB		 4024}
4025EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 4026
4027void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
4028{
4029 kvm_x86_ops->vcpu_free(vcpu);
4030}
4031
4032struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
4033 unsigned int id)
4034{
26e5215f
AK		 4035 return kvm_x86_ops->vcpu_create(kvm, id);
4036}
e9b11c17 4037
26e5215f
AK		 4038int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
4039{
4040 int r;
e9b11c17
ZX		 4041
4042 /* We do fxsave: this must be aligned. */
ad312c7c 4043 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 4044
0bed3b56 4045 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 4046 vcpu_load(vcpu);
4047 r = kvm_arch_vcpu_reset(vcpu);
4048 if (r == 0)
4049 r = kvm_mmu_setup(vcpu);
4050 vcpu_put(vcpu);
4051 if (r < 0)
4052 goto free_vcpu;
4053
26e5215f 4054 return 0;
e9b11c17
ZX		 4055free_vcpu:
4056 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 4057 return r;
e9b11c17
ZX		 4058}
4059
d40ccc62 4060void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 4061{
4062 vcpu_load(vcpu);
4063 kvm_mmu_unload(vcpu);
4064 vcpu_put(vcpu);
4065
4066 kvm_x86_ops->vcpu_free(vcpu);
4067}
4068
4069int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4070{
448fa4a9
JK		 4071 vcpu->arch.nmi_pending = false;
4072 vcpu->arch.nmi_injected = false;
4073
42dbaa5a
JK		 4074 vcpu->arch.switch_db_regs = 0;
4075 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
4076 vcpu->arch.dr6 = DR6_FIXED_1;
4077 vcpu->arch.dr7 = DR7_FIXED_1;
4078
e9b11c17
ZX		 4079 return kvm_x86_ops->vcpu_reset(vcpu);
4080}
4081
4082void kvm_arch_hardware_enable(void *garbage)
4083{
4084 kvm_x86_ops->hardware_enable(garbage);
4085}
4086
4087void kvm_arch_hardware_disable(void *garbage)
4088{
4089 kvm_x86_ops->hardware_disable(garbage);
4090}
4091
4092int kvm_arch_hardware_setup(void)
4093{
4094 return kvm_x86_ops->hardware_setup();
4095}
4096
4097void kvm_arch_hardware_unsetup(void)
4098{
4099 kvm_x86_ops->hardware_unsetup();
4100}
4101
4102void kvm_arch_check_processor_compat(void *rtn)
4103{
4104 kvm_x86_ops->check_processor_compatibility(rtn);
4105}
4106
4107int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
4108{
4109 struct page *page;
4110 struct kvm *kvm;
4111 int r;
4112
4113 BUG_ON(vcpu->kvm == NULL);
4114 kvm = vcpu->kvm;
4115
ad312c7c 4116 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
e9b11c17 4117 if (!irqchip_in_kernel(kvm) || vcpu->vcpu_id == 0)
a4535290 4118 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 4119 else
a4535290 4120 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 4121
4122 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
4123 if (!page) {
4124 r = -ENOMEM;
4125 goto fail;
4126 }
ad312c7c 4127 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 4128
4129 r = kvm_mmu_create(vcpu);
4130 if (r < 0)
4131 goto fail_free_pio_data;
4132
4133 if (irqchip_in_kernel(kvm)) {
4134 r = kvm_create_lapic(vcpu);
4135 if (r < 0)
4136 goto fail_mmu_destroy;
4137 }
4138
4139 return 0;
4140
4141fail_mmu_destroy:
4142 kvm_mmu_destroy(vcpu);
4143fail_free_pio_data:
ad312c7c 4144 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 4145fail:
4146 return r;
4147}
4148
4149void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
4150{
4151 kvm_free_lapic(vcpu);
3200f405 4152 down_read(&vcpu->kvm->slots_lock);
e9b11c17 4153 kvm_mmu_destroy(vcpu);
3200f405 4154 up_read(&vcpu->kvm->slots_lock);
ad312c7c 4155 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 4156}
d19a9cd2
ZX		 4157
4158struct kvm *kvm_arch_create_vm(void)
4159{
4160 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
4161
4162 if (!kvm)
4163 return ERR_PTR(-ENOMEM);
4164
f05e70ac 4165 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
6cffe8ca 4166 INIT_LIST_HEAD(&kvm->arch.oos_global_pages);
4d5c5d0f 4167 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 4168
5550af4d
SY		 4169 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
4170 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
4171
d19a9cd2
ZX		 4172 return kvm;
4173}
4174
4175static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
4176{
4177 vcpu_load(vcpu);
4178 kvm_mmu_unload(vcpu);
4179 vcpu_put(vcpu);
4180}
4181
4182static void kvm_free_vcpus(struct kvm *kvm)
4183{
4184 unsigned int i;
4185
4186 /*
4187 * Unpin any mmu pages first.
4188 */
4189 for (i = 0; i < KVM_MAX_VCPUS; ++i)
4190 if (kvm->vcpus[i])
4191 kvm_unload_vcpu_mmu(kvm->vcpus[i]);
4192 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
4193 if (kvm->vcpus[i]) {
4194 kvm_arch_vcpu_free(kvm->vcpus[i]);
4195 kvm->vcpus[i] = NULL;
4196 }
4197 }
4198
4199}
4200
ad8ba2cd
SY		 4201void kvm_arch_sync_events(struct kvm *kvm)
4202{
ba4cef31 4203 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 4204}
4205
d19a9cd2
ZX		 4206void kvm_arch_destroy_vm(struct kvm *kvm)
4207{
6eb55818 4208 kvm_iommu_unmap_guest(kvm);
7837699f 4209 kvm_free_pit(kvm);
d7deeeb0
ZX		 4210 kfree(kvm->arch.vpic);
4211 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 4212 kvm_free_vcpus(kvm);
4213 kvm_free_physmem(kvm);
3d45830c
AK		 4214 if (kvm->arch.apic_access_page)
4215 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 4216 if (kvm->arch.ept_identity_pagetable)
4217 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 4218 kfree(kvm);
4219}
0de10343
ZX		 4220
4221int kvm_arch_set_memory_region(struct kvm *kvm,
4222 struct kvm_userspace_memory_region *mem,
4223 struct kvm_memory_slot old,
4224 int user_alloc)
4225{
4226 int npages = mem->memory_size >> PAGE_SHIFT;
4227 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
4228
4229 /*To keep backward compatibility with older userspace,
4230 *x86 needs to hanlde !user_alloc case.
4231 */
4232 if (!user_alloc) {
4233 if (npages && !old.rmap) {
604b38ac
AA		 4234 unsigned long userspace_addr;
4235
72dc67a6 4236 down_write(&current->mm->mmap_sem);
604b38ac
AA		 4237 userspace_addr = do_mmap(NULL, 0,
4238 npages * PAGE_SIZE,
4239 PROT_READ | PROT_WRITE,
acee3c04 4240 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 4241 0);
72dc67a6 4242 up_write(&current->mm->mmap_sem);
0de10343 4243
604b38ac
AA		 4244 if (IS_ERR((void *)userspace_addr))
4245 return PTR_ERR((void *)userspace_addr);
4246
4247 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4248 spin_lock(&kvm->mmu_lock);
4249 memslot->userspace_addr = userspace_addr;
4250 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4251 } else {
4252 if (!old.user_alloc && old.rmap) {
4253 int ret;
4254
72dc67a6 4255 down_write(&current->mm->mmap_sem);
0de10343
ZX		 4256 ret = do_munmap(current->mm, old.userspace_addr,
4257 old.npages * PAGE_SIZE);
72dc67a6 4258 up_write(&current->mm->mmap_sem);
0de10343
ZX		 4259 if (ret < 0)
4260 printk(KERN_WARNING
4261 "kvm_vm_ioctl_set_memory_region: "
4262 "failed to munmap memory\n");
4263 }
4264 }
4265 }
4266
f05e70ac 4267 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 4268 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4269 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4270 }
4271
4272 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
4273 kvm_flush_remote_tlbs(kvm);
4274
4275 return 0;
4276}
1d737c8a 4277
34d4cb8f
MT		 4278void kvm_arch_flush_shadow(struct kvm *kvm)
4279{
4280 kvm_mmu_zap_all(kvm);
4281}
4282
1d737c8a
ZX		 4283int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4284{
a4535290 4285 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
0496fbb9
JK		 4286 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
4287 || vcpu->arch.nmi_pending;
1d737c8a 4288}
5736199a
ZX		 4289
4290static void vcpu_kick_intr(void *info)
4291{
4292#ifdef DEBUG
4293 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)info;
4294 printk(KERN_DEBUG "vcpu_kick_intr %p \n", vcpu);
4295#endif
4296}
4297
4298void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4299{
4300 int ipi_pcpu = vcpu->cpu;
e9571ed5 4301 int cpu = get_cpu();
5736199a
ZX		 4302
4303 if (waitqueue_active(&vcpu->wq)) {
4304 wake_up_interruptible(&vcpu->wq);
4305 ++vcpu->stat.halt_wakeup;
4306 }
e9571ed5
MT		 4307 /*
4308 * We may be called synchronously with irqs disabled in guest mode,
4309 * So need not to call smp_call_function_single() in that case.
4310 */
4311 if (vcpu->guest_mode && vcpu->cpu != cpu)
8691e5a8 4312 smp_call_function_single(ipi_pcpu, vcpu_kick_intr, vcpu, 0);
e9571ed5 4313 put_cpu();
5736199a 4314}
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