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KVM: Add kvm_arch_sync_events to sync with asynchronize events
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
043405e1
CO		 39
40#include <asm/uaccess.h>
d825ed0a 41#include <asm/msr.h>
a5f61300 42#include <asm/desc.h>
0bed3b56 43#include <asm/mtrr.h>
043405e1 44
313a3dc7 45#define MAX_IO_MSRS 256
a03490ed
CO		 46#define CR0_RESERVED_BITS \
47 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
48 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
49 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
50#define CR4_RESERVED_BITS \
51 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
52 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
53 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
54 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
55
56#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
50a37eb4
JR		 57/* EFER defaults:
58 * - enable syscall per default because its emulated by KVM
59 * - enable LME and LMA per default on 64 bit KVM
60 */
61#ifdef CONFIG_X86_64
62static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
63#else
64static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
65#endif
313a3dc7 66
ba1389b7
AK		 67#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
68#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 69
674eea0f
AK		 70static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
71 struct kvm_cpuid_entry2 __user *entries);
72
97896d04 73struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 74EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 75
417bc304 76struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 77 { "pf_fixed", VCPU_STAT(pf_fixed) },
78 { "pf_guest", VCPU_STAT(pf_guest) },
79 { "tlb_flush", VCPU_STAT(tlb_flush) },
80 { "invlpg", VCPU_STAT(invlpg) },
81 { "exits", VCPU_STAT(exits) },
82 { "io_exits", VCPU_STAT(io_exits) },
83 { "mmio_exits", VCPU_STAT(mmio_exits) },
84 { "signal_exits", VCPU_STAT(signal_exits) },
85 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 86 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 87 { "halt_exits", VCPU_STAT(halt_exits) },
88 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 89 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7 90 { "request_irq", VCPU_STAT(request_irq_exits) },
c4abb7c9 91 { "request_nmi", VCPU_STAT(request_nmi_exits) },
ba1389b7
AK		 92 { "irq_exits", VCPU_STAT(irq_exits) },
93 { "host_state_reload", VCPU_STAT(host_state_reload) },
94 { "efer_reload", VCPU_STAT(efer_reload) },
95 { "fpu_reload", VCPU_STAT(fpu_reload) },
96 { "insn_emulation", VCPU_STAT(insn_emulation) },
97 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 98 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 99 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 100 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
101 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
102 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
103 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
104 { "mmu_flooded", VM_STAT(mmu_flooded) },
105 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 106 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 107 { "mmu_unsync", VM_STAT(mmu_unsync) },
6cffe8ca 108 { "mmu_unsync_global", VM_STAT(mmu_unsync_global) },
0f74a24c 109 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 110 { "largepages", VM_STAT(lpages) },
417bc304
HB		 111 { NULL }
112};
113
5fb76f9b
CO		 114unsigned long segment_base(u16 selector)
115{
116 struct descriptor_table gdt;
a5f61300 117 struct desc_struct *d;
5fb76f9b
CO		 118 unsigned long table_base;
119 unsigned long v;
120
121 if (selector == 0)
122 return 0;
123
124 asm("sgdt %0" : "=m"(gdt));
125 table_base = gdt.base;
126
127 if (selector & 4) { /* from ldt */
128 u16 ldt_selector;
129
130 asm("sldt %0" : "=g"(ldt_selector));
131 table_base = segment_base(ldt_selector);
132 }
a5f61300
AK		 133 d = (struct desc_struct *)(table_base + (selector & ~7));
134 v = d->base0 | ((unsigned long)d->base1 << 16) |
135 ((unsigned long)d->base2 << 24);
5fb76f9b 136#ifdef CONFIG_X86_64
a5f61300
AK		 137 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
138 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 139#endif
140 return v;
141}
142EXPORT_SYMBOL_GPL(segment_base);
143
6866b83e
CO		 144u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
145{
146 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 147 return vcpu->arch.apic_base;
6866b83e 148 else
ad312c7c 149 return vcpu->arch.apic_base;
6866b83e
CO		 150}
151EXPORT_SYMBOL_GPL(kvm_get_apic_base);
152
153void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
154{
155 /* TODO: reserve bits check */
156 if (irqchip_in_kernel(vcpu->kvm))
157 kvm_lapic_set_base(vcpu, data);
158 else
ad312c7c 159 vcpu->arch.apic_base = data;
6866b83e
CO		 160}
161EXPORT_SYMBOL_GPL(kvm_set_apic_base);
162
298101da
AK		 163void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
164{
ad312c7c
ZX		 165 WARN_ON(vcpu->arch.exception.pending);
166 vcpu->arch.exception.pending = true;
167 vcpu->arch.exception.has_error_code = false;
168 vcpu->arch.exception.nr = nr;
298101da
AK		 169}
170EXPORT_SYMBOL_GPL(kvm_queue_exception);
171
c3c91fee
AK		 172void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
173 u32 error_code)
174{
175 ++vcpu->stat.pf_guest;
71c4dfaf
JR		 176 if (vcpu->arch.exception.pending) {
177 if (vcpu->arch.exception.nr == PF_VECTOR) {
178 printk(KERN_DEBUG "kvm: inject_page_fault:"
179 " double fault 0x%lx\n", addr);
180 vcpu->arch.exception.nr = DF_VECTOR;
181 vcpu->arch.exception.error_code = 0;
182 } else if (vcpu->arch.exception.nr == DF_VECTOR) {
183 /* triple fault -> shutdown */
184 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
185 }
c3c91fee
AK		 186 return;
187 }
ad312c7c 188 vcpu->arch.cr2 = addr;
c3c91fee
AK		 189 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
190}
191
3419ffc8
SY		 192void kvm_inject_nmi(struct kvm_vcpu *vcpu)
193{
194 vcpu->arch.nmi_pending = 1;
195}
196EXPORT_SYMBOL_GPL(kvm_inject_nmi);
197
298101da
AK		 198void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
199{
ad312c7c
ZX		 200 WARN_ON(vcpu->arch.exception.pending);
201 vcpu->arch.exception.pending = true;
202 vcpu->arch.exception.has_error_code = true;
203 vcpu->arch.exception.nr = nr;
204 vcpu->arch.exception.error_code = error_code;
298101da
AK		 205}
206EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
207
208static void __queue_exception(struct kvm_vcpu *vcpu)
209{
ad312c7c
ZX		 210 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
211 vcpu->arch.exception.has_error_code,
212 vcpu->arch.exception.error_code);
298101da
AK		 213}
214
a03490ed
CO		 215/*
216 * Load the pae pdptrs. Return true is they are all valid.
217 */
218int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
219{
220 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
221 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
222 int i;
223 int ret;
ad312c7c 224 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 225
a03490ed
CO		 226 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
227 offset * sizeof(u64), sizeof(pdpte));
228 if (ret < 0) {
229 ret = 0;
230 goto out;
231 }
232 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
233 if ((pdpte[i] & 1) && (pdpte[i] & 0xfffffff0000001e6ull)) {
234 ret = 0;
235 goto out;
236 }
237 }
238 ret = 1;
239
ad312c7c 240 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
a03490ed 241out:
a03490ed
CO		 242
243 return ret;
244}
cc4b6871 245EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 246
d835dfec
AK		 247static bool pdptrs_changed(struct kvm_vcpu *vcpu)
248{
ad312c7c 249 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 250 bool changed = true;
251 int r;
252
253 if (is_long_mode(vcpu) || !is_pae(vcpu))
254 return false;
255
ad312c7c 256 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 257 if (r < 0)
258 goto out;
ad312c7c 259 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 260out:
d835dfec
AK		 261
262 return changed;
263}
264
2d3ad1f4 265void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 266{
267 if (cr0 & CR0_RESERVED_BITS) {
268 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 269 cr0, vcpu->arch.cr0);
c1a5d4f9 270 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 271 return;
272 }
273
274 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
275 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 276 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 277 return;
278 }
279
280 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
281 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
282 "and a clear PE flag\n");
c1a5d4f9 283 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 284 return;
285 }
286
287 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
288#ifdef CONFIG_X86_64
ad312c7c 289 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 290 int cs_db, cs_l;
291
292 if (!is_pae(vcpu)) {
293 printk(KERN_DEBUG "set_cr0: #GP, start paging "
294 "in long mode while PAE is disabled\n");
c1a5d4f9 295 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 296 return;
297 }
298 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
299 if (cs_l) {
300 printk(KERN_DEBUG "set_cr0: #GP, start paging "
301 "in long mode while CS.L == 1\n");
c1a5d4f9 302 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 303 return;
304
305 }
306 } else
307#endif
ad312c7c 308 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 309 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
310 "reserved bits\n");
c1a5d4f9 311 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 312 return;
313 }
314
315 }
316
317 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 318 vcpu->arch.cr0 = cr0;
a03490ed 319
6cffe8ca 320 kvm_mmu_sync_global(vcpu);
a03490ed 321 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 322 return;
323}
2d3ad1f4 324EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 325
2d3ad1f4 326void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 327{
2d3ad1f4 328 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
2714d1d3
FEL		 329 KVMTRACE_1D(LMSW, vcpu,
330 (u32)((vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f)),
331 handler);
a03490ed 332}
2d3ad1f4 333EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 334
2d3ad1f4 335void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed
CO		 336{
337 if (cr4 & CR4_RESERVED_BITS) {
338 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 339 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 340 return;
341 }
342
343 if (is_long_mode(vcpu)) {
344 if (!(cr4 & X86_CR4_PAE)) {
345 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
346 "in long mode\n");
c1a5d4f9 347 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 348 return;
349 }
350 } else if (is_paging(vcpu) && !is_pae(vcpu) && (cr4 & X86_CR4_PAE)
ad312c7c 351 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 352 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 353 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 354 return;
355 }
356
357 if (cr4 & X86_CR4_VMXE) {
358 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 359 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 360 return;
361 }
362 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 363 vcpu->arch.cr4 = cr4;
6cffe8ca 364 kvm_mmu_sync_global(vcpu);
a03490ed 365 kvm_mmu_reset_context(vcpu);
a03490ed 366}
2d3ad1f4 367EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 368
2d3ad1f4 369void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 370{
ad312c7c 371 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 372 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 373 kvm_mmu_flush_tlb(vcpu);
374 return;
375 }
376
a03490ed
CO		 377 if (is_long_mode(vcpu)) {
378 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
379 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 380 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 381 return;
382 }
383 } else {
384 if (is_pae(vcpu)) {
385 if (cr3 & CR3_PAE_RESERVED_BITS) {
386 printk(KERN_DEBUG
387 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 388 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 389 return;
390 }
391 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
392 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
393 "reserved bits\n");
c1a5d4f9 394 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 395 return;
396 }
397 }
398 /*
399 * We don't check reserved bits in nonpae mode, because
400 * this isn't enforced, and VMware depends on this.
401 */
402 }
403
a03490ed
CO		 404 /*
405 * Does the new cr3 value map to physical memory? (Note, we
406 * catch an invalid cr3 even in real-mode, because it would
407 * cause trouble later on when we turn on paging anyway.)
408 *
409 * A real CPU would silently accept an invalid cr3 and would
410 * attempt to use it - with largely undefined (and often hard
411 * to debug) behavior on the guest side.
412 */
413 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 414 kvm_inject_gp(vcpu, 0);
a03490ed 415 else {
ad312c7c
ZX		 416 vcpu->arch.cr3 = cr3;
417 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 418 }
a03490ed 419}
2d3ad1f4 420EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 421
2d3ad1f4 422void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 423{
424 if (cr8 & CR8_RESERVED_BITS) {
425 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 426 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 427 return;
428 }
429 if (irqchip_in_kernel(vcpu->kvm))
430 kvm_lapic_set_tpr(vcpu, cr8);
431 else
ad312c7c 432 vcpu->arch.cr8 = cr8;
a03490ed 433}
2d3ad1f4 434EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 435
2d3ad1f4 436unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 437{
438 if (irqchip_in_kernel(vcpu->kvm))
439 return kvm_lapic_get_cr8(vcpu);
440 else
ad312c7c 441 return vcpu->arch.cr8;
a03490ed 442}
2d3ad1f4 443EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 444
043405e1
CO		 445/*
446 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
447 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
448 *
449 * This list is modified at module load time to reflect the
450 * capabilities of the host cpu.
451 */
452static u32 msrs_to_save[] = {
453 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
454 MSR_K6_STAR,
455#ifdef CONFIG_X86_64
456 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
457#endif
18068523 458 MSR_IA32_TIME_STAMP_COUNTER, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
468d472f 459 MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT
043405e1
CO		 460};
461
462static unsigned num_msrs_to_save;
463
464static u32 emulated_msrs[] = {
465 MSR_IA32_MISC_ENABLE,
466};
467
15c4a640
CO		 468static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
469{
f2b4b7dd 470 if (efer & efer_reserved_bits) {
15c4a640
CO		 471 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
472 efer);
c1a5d4f9 473 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 474 return;
475 }
476
477 if (is_paging(vcpu)
ad312c7c 478 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 479 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 480 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 481 return;
482 }
483
484 kvm_x86_ops->set_efer(vcpu, efer);
485
486 efer &= ~EFER_LMA;
ad312c7c 487 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 488
ad312c7c 489 vcpu->arch.shadow_efer = efer;
15c4a640
CO		 490}
491
f2b4b7dd
JR		 492void kvm_enable_efer_bits(u64 mask)
493{
494 efer_reserved_bits &= ~mask;
495}
496EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
497
498
15c4a640
CO		 499/*
500 * Writes msr value into into the appropriate "register".
501 * Returns 0 on success, non-0 otherwise.
502 * Assumes vcpu_load() was already called.
503 */
504int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
505{
506 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
507}
508
313a3dc7
CO		 509/*
510 * Adapt set_msr() to msr_io()'s calling convention
511 */
512static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
513{
514 return kvm_set_msr(vcpu, index, *data);
515}
516
18068523
GOC		 517static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
518{
519 static int version;
50d0a0f9
GH		 520 struct pvclock_wall_clock wc;
521 struct timespec now, sys, boot;
18068523
GOC		 522
523 if (!wall_clock)
524 return;
525
526 version++;
527
18068523
GOC		 528 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
529
50d0a0f9
GH		 530 /*
531 * The guest calculates current wall clock time by adding
532 * system time (updated by kvm_write_guest_time below) to the
533 * wall clock specified here. guest system time equals host
534 * system time for us, thus we must fill in host boot time here.
535 */
536 now = current_kernel_time();
537 ktime_get_ts(&sys);
538 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
539
540 wc.sec = boot.tv_sec;
541 wc.nsec = boot.tv_nsec;
542 wc.version = version;
18068523
GOC		 543
544 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
545
546 version++;
547 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 548}
549
50d0a0f9
GH		 550static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
551{
552 uint32_t quotient, remainder;
553
554 /* Don't try to replace with do_div(), this one calculates
555 * "(dividend << 32) / divisor" */
556 __asm__ ( "divl %4"
557 : "=a" (quotient), "=d" (remainder)
558 : "0" (0), "1" (dividend), "r" (divisor) );
559 return quotient;
560}
561
562static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
563{
564 uint64_t nsecs = 1000000000LL;
565 int32_t shift = 0;
566 uint64_t tps64;
567 uint32_t tps32;
568
569 tps64 = tsc_khz * 1000LL;
570 while (tps64 > nsecs*2) {
571 tps64 >>= 1;
572 shift--;
573 }
574
575 tps32 = (uint32_t)tps64;
576 while (tps32 <= (uint32_t)nsecs) {
577 tps32 <<= 1;
578 shift++;
579 }
580
581 hv_clock->tsc_shift = shift;
582 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
583
584 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 585 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 586 hv_clock->tsc_to_system_mul);
587}
588
18068523
GOC		 589static void kvm_write_guest_time(struct kvm_vcpu *v)
590{
591 struct timespec ts;
592 unsigned long flags;
593 struct kvm_vcpu_arch *vcpu = &v->arch;
594 void *shared_kaddr;
595
596 if ((!vcpu->time_page))
597 return;
598
50d0a0f9
GH		 599 if (unlikely(vcpu->hv_clock_tsc_khz != tsc_khz)) {
600 kvm_set_time_scale(tsc_khz, &vcpu->hv_clock);
601 vcpu->hv_clock_tsc_khz = tsc_khz;
602 }
603
18068523
GOC		 604 /* Keep irq disabled to prevent changes to the clock */
605 local_irq_save(flags);
606 kvm_get_msr(v, MSR_IA32_TIME_STAMP_COUNTER,
607 &vcpu->hv_clock.tsc_timestamp);
608 ktime_get_ts(&ts);
609 local_irq_restore(flags);
610
611 /* With all the info we got, fill in the values */
612
613 vcpu->hv_clock.system_time = ts.tv_nsec +
614 (NSEC_PER_SEC * (u64)ts.tv_sec);
615 /*
616 * The interface expects us to write an even number signaling that the
617 * update is finished. Since the guest won't see the intermediate
50d0a0f9 618 * state, we just increase by 2 at the end.
18068523 619 */
50d0a0f9 620 vcpu->hv_clock.version += 2;
18068523
GOC		 621
622 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
623
624 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 625 sizeof(vcpu->hv_clock));
18068523
GOC		 626
627 kunmap_atomic(shared_kaddr, KM_USER0);
628
629 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
630}
631
9ba075a6
AK		 632static bool msr_mtrr_valid(unsigned msr)
633{
634 switch (msr) {
635 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
636 case MSR_MTRRfix64K_00000:
637 case MSR_MTRRfix16K_80000:
638 case MSR_MTRRfix16K_A0000:
639 case MSR_MTRRfix4K_C0000:
640 case MSR_MTRRfix4K_C8000:
641 case MSR_MTRRfix4K_D0000:
642 case MSR_MTRRfix4K_D8000:
643 case MSR_MTRRfix4K_E0000:
644 case MSR_MTRRfix4K_E8000:
645 case MSR_MTRRfix4K_F0000:
646 case MSR_MTRRfix4K_F8000:
647 case MSR_MTRRdefType:
648 case MSR_IA32_CR_PAT:
649 return true;
650 case 0x2f8:
651 return true;
652 }
653 return false;
654}
655
656static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
657{
0bed3b56
SY		 658 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
659
9ba075a6
AK		 660 if (!msr_mtrr_valid(msr))
661 return 1;
662
0bed3b56
SY		 663 if (msr == MSR_MTRRdefType) {
664 vcpu->arch.mtrr_state.def_type = data;
665 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
666 } else if (msr == MSR_MTRRfix64K_00000)
667 p[0] = data;
668 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
669 p[1 + msr - MSR_MTRRfix16K_80000] = data;
670 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
671 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
672 else if (msr == MSR_IA32_CR_PAT)
673 vcpu->arch.pat = data;
674 else { /* Variable MTRRs */
675 int idx, is_mtrr_mask;
676 u64 *pt;
677
678 idx = (msr - 0x200) / 2;
679 is_mtrr_mask = msr - 0x200 - 2 * idx;
680 if (!is_mtrr_mask)
681 pt =
682 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
683 else
684 pt =
685 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
686 *pt = data;
687 }
688
689 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 690 return 0;
691}
15c4a640
CO		 692
693int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
694{
695 switch (msr) {
15c4a640
CO		 696 case MSR_EFER:
697 set_efer(vcpu, data);
698 break;
15c4a640
CO		 699 case MSR_IA32_MC0_STATUS:
700 pr_unimpl(vcpu, "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n",
b8688d51 701 __func__, data);
15c4a640
CO		 702 break;
703 case MSR_IA32_MCG_STATUS:
704 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_STATUS 0x%llx, nop\n",
b8688d51 705 __func__, data);
15c4a640 706 break;
c7ac679c
JR		 707 case MSR_IA32_MCG_CTL:
708 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_CTL 0x%llx, nop\n",
b8688d51 709 __func__, data);
c7ac679c 710 break;
b5e2fec0
AG		 711 case MSR_IA32_DEBUGCTLMSR:
712 if (!data) {
713 /* We support the non-activated case already */
714 break;
715 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
716 /* Values other than LBR and BTF are vendor-specific,
717 thus reserved and should throw a #GP */
718 return 1;
719 }
720 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
721 __func__, data);
722 break;
15c4a640
CO		 723 case MSR_IA32_UCODE_REV:
724 case MSR_IA32_UCODE_WRITE:
15c4a640 725 break;
9ba075a6
AK		 726 case 0x200 ... 0x2ff:
727 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 728 case MSR_IA32_APICBASE:
729 kvm_set_apic_base(vcpu, data);
730 break;
731 case MSR_IA32_MISC_ENABLE:
ad312c7c 732 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 733 break;
18068523
GOC		 734 case MSR_KVM_WALL_CLOCK:
735 vcpu->kvm->arch.wall_clock = data;
736 kvm_write_wall_clock(vcpu->kvm, data);
737 break;
738 case MSR_KVM_SYSTEM_TIME: {
739 if (vcpu->arch.time_page) {
740 kvm_release_page_dirty(vcpu->arch.time_page);
741 vcpu->arch.time_page = NULL;
742 }
743
744 vcpu->arch.time = data;
745
746 /* we verify if the enable bit is set... */
747 if (!(data & 1))
748 break;
749
750 /* ...but clean it before doing the actual write */
751 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
752
18068523
GOC		 753 vcpu->arch.time_page =
754 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 755
756 if (is_error_page(vcpu->arch.time_page)) {
757 kvm_release_page_clean(vcpu->arch.time_page);
758 vcpu->arch.time_page = NULL;
759 }
760
761 kvm_write_guest_time(vcpu);
762 break;
763 }
15c4a640 764 default:
565f1fbd 765 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", msr, data);
15c4a640
CO		 766 return 1;
767 }
768 return 0;
769}
770EXPORT_SYMBOL_GPL(kvm_set_msr_common);
771
772
773/*
774 * Reads an msr value (of 'msr_index') into 'pdata'.
775 * Returns 0 on success, non-0 otherwise.
776 * Assumes vcpu_load() was already called.
777 */
778int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
779{
780 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
781}
782
9ba075a6
AK		 783static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
784{
0bed3b56
SY		 785 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
786
9ba075a6
AK		 787 if (!msr_mtrr_valid(msr))
788 return 1;
789
0bed3b56
SY		 790 if (msr == MSR_MTRRdefType)
791 *pdata = vcpu->arch.mtrr_state.def_type +
792 (vcpu->arch.mtrr_state.enabled << 10);
793 else if (msr == MSR_MTRRfix64K_00000)
794 *pdata = p[0];
795 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
796 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
797 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
798 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
799 else if (msr == MSR_IA32_CR_PAT)
800 *pdata = vcpu->arch.pat;
801 else { /* Variable MTRRs */
802 int idx, is_mtrr_mask;
803 u64 *pt;
804
805 idx = (msr - 0x200) / 2;
806 is_mtrr_mask = msr - 0x200 - 2 * idx;
807 if (!is_mtrr_mask)
808 pt =
809 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
810 else
811 pt =
812 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
813 *pdata = *pt;
814 }
815
9ba075a6
AK		 816 return 0;
817}
818
15c4a640
CO		 819int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
820{
821 u64 data;
822
823 switch (msr) {
824 case 0xc0010010: /* SYSCFG */
825 case 0xc0010015: /* HWCR */
826 case MSR_IA32_PLATFORM_ID:
827 case MSR_IA32_P5_MC_ADDR:
828 case MSR_IA32_P5_MC_TYPE:
829 case MSR_IA32_MC0_CTL:
830 case MSR_IA32_MCG_STATUS:
831 case MSR_IA32_MCG_CAP:
c7ac679c 832 case MSR_IA32_MCG_CTL:
15c4a640
CO		 833 case MSR_IA32_MC0_MISC:
834 case MSR_IA32_MC0_MISC+4:
835 case MSR_IA32_MC0_MISC+8:
836 case MSR_IA32_MC0_MISC+12:
837 case MSR_IA32_MC0_MISC+16:
a89c1ad2 838 case MSR_IA32_MC0_MISC+20:
15c4a640 839 case MSR_IA32_UCODE_REV:
15c4a640 840 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 841 case MSR_IA32_DEBUGCTLMSR:
842 case MSR_IA32_LASTBRANCHFROMIP:
843 case MSR_IA32_LASTBRANCHTOIP:
844 case MSR_IA32_LASTINTFROMIP:
845 case MSR_IA32_LASTINTTOIP:
15c4a640
CO		 846 data = 0;
847 break;
9ba075a6
AK		 848 case MSR_MTRRcap:
849 data = 0x500 | KVM_NR_VAR_MTRR;
850 break;
851 case 0x200 ... 0x2ff:
852 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 853 case 0xcd: /* fsb frequency */
854 data = 3;
855 break;
856 case MSR_IA32_APICBASE:
857 data = kvm_get_apic_base(vcpu);
858 break;
859 case MSR_IA32_MISC_ENABLE:
ad312c7c 860 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 861 break;
847f0ad8
AG		 862 case MSR_IA32_PERF_STATUS:
863 /* TSC increment by tick */
864 data = 1000ULL;
865 /* CPU multiplier */
866 data |= (((uint64_t)4ULL) << 40);
867 break;
15c4a640 868 case MSR_EFER:
ad312c7c 869 data = vcpu->arch.shadow_efer;
15c4a640 870 break;
18068523
GOC		 871 case MSR_KVM_WALL_CLOCK:
872 data = vcpu->kvm->arch.wall_clock;
873 break;
874 case MSR_KVM_SYSTEM_TIME:
875 data = vcpu->arch.time;
876 break;
15c4a640
CO		 877 default:
878 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
879 return 1;
880 }
881 *pdata = data;
882 return 0;
883}
884EXPORT_SYMBOL_GPL(kvm_get_msr_common);
885
313a3dc7
CO		 886/*
887 * Read or write a bunch of msrs. All parameters are kernel addresses.
888 *
889 * @return number of msrs set successfully.
890 */
891static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
892 struct kvm_msr_entry *entries,
893 int (*do_msr)(struct kvm_vcpu *vcpu,
894 unsigned index, u64 *data))
895{
896 int i;
897
898 vcpu_load(vcpu);
899
3200f405 900 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 901 for (i = 0; i < msrs->nmsrs; ++i)
902 if (do_msr(vcpu, entries[i].index, &entries[i].data))
903 break;
3200f405 904 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 905
906 vcpu_put(vcpu);
907
908 return i;
909}
910
911/*
912 * Read or write a bunch of msrs. Parameters are user addresses.
913 *
914 * @return number of msrs set successfully.
915 */
916static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
917 int (*do_msr)(struct kvm_vcpu *vcpu,
918 unsigned index, u64 *data),
919 int writeback)
920{
921 struct kvm_msrs msrs;
922 struct kvm_msr_entry *entries;
923 int r, n;
924 unsigned size;
925
926 r = -EFAULT;
927 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
928 goto out;
929
930 r = -E2BIG;
931 if (msrs.nmsrs >= MAX_IO_MSRS)
932 goto out;
933
934 r = -ENOMEM;
935 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
936 entries = vmalloc(size);
937 if (!entries)
938 goto out;
939
940 r = -EFAULT;
941 if (copy_from_user(entries, user_msrs->entries, size))
942 goto out_free;
943
944 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
945 if (r < 0)
946 goto out_free;
947
948 r = -EFAULT;
949 if (writeback && copy_to_user(user_msrs->entries, entries, size))
950 goto out_free;
951
952 r = n;
953
954out_free:
955 vfree(entries);
956out:
957 return r;
958}
959
018d00d2
ZX		 960int kvm_dev_ioctl_check_extension(long ext)
961{
962 int r;
963
964 switch (ext) {
965 case KVM_CAP_IRQCHIP:
966 case KVM_CAP_HLT:
967 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 968 case KVM_CAP_SET_TSS_ADDR:
07716717 969 case KVM_CAP_EXT_CPUID:
18068523 970 case KVM_CAP_CLOCKSOURCE:
7837699f 971 case KVM_CAP_PIT:
a28e4f5a 972 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 973 case KVM_CAP_MP_STATE:
ed848624 974 case KVM_CAP_SYNC_MMU:
018d00d2
ZX		 975 r = 1;
976 break;
542472b5
LV		 977 case KVM_CAP_COALESCED_MMIO:
978 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
979 break;
774ead3a
AK		 980 case KVM_CAP_VAPIC:
981 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
982 break;
f725230a
AK		 983 case KVM_CAP_NR_VCPUS:
984 r = KVM_MAX_VCPUS;
985 break;
a988b910
AK		 986 case KVM_CAP_NR_MEMSLOTS:
987 r = KVM_MEMORY_SLOTS;
988 break;
2f333bcb
MT		 989 case KVM_CAP_PV_MMU:
990 r = !tdp_enabled;
991 break;
62c476c7 992 case KVM_CAP_IOMMU:
19de40a8 993 r = iommu_found();
62c476c7 994 break;
018d00d2
ZX		 995 default:
996 r = 0;
997 break;
998 }
999 return r;
1000
1001}
1002
043405e1
CO		 1003long kvm_arch_dev_ioctl(struct file *filp,
1004 unsigned int ioctl, unsigned long arg)
1005{
1006 void __user *argp = (void __user *)arg;
1007 long r;
1008
1009 switch (ioctl) {
1010 case KVM_GET_MSR_INDEX_LIST: {
1011 struct kvm_msr_list __user *user_msr_list = argp;
1012 struct kvm_msr_list msr_list;
1013 unsigned n;
1014
1015 r = -EFAULT;
1016 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1017 goto out;
1018 n = msr_list.nmsrs;
1019 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1020 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1021 goto out;
1022 r = -E2BIG;
1023 if (n < num_msrs_to_save)
1024 goto out;
1025 r = -EFAULT;
1026 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1027 num_msrs_to_save * sizeof(u32)))
1028 goto out;
1029 if (copy_to_user(user_msr_list->indices
1030 + num_msrs_to_save * sizeof(u32),
1031 &emulated_msrs,
1032 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1033 goto out;
1034 r = 0;
1035 break;
1036 }
674eea0f
AK		 1037 case KVM_GET_SUPPORTED_CPUID: {
1038 struct kvm_cpuid2 __user *cpuid_arg = argp;
1039 struct kvm_cpuid2 cpuid;
1040
1041 r = -EFAULT;
1042 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1043 goto out;
1044 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
1045 cpuid_arg->entries);
1046 if (r)
1047 goto out;
1048
1049 r = -EFAULT;
1050 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1051 goto out;
1052 r = 0;
1053 break;
1054 }
043405e1
CO		 1055 default:
1056 r = -EINVAL;
1057 }
1058out:
1059 return r;
1060}
1061
313a3dc7
CO		 1062void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1063{
1064 kvm_x86_ops->vcpu_load(vcpu, cpu);
18068523 1065 kvm_write_guest_time(vcpu);
313a3dc7
CO		 1066}
1067
1068void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1069{
1070 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 1071 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1072}
1073
07716717 1074static int is_efer_nx(void)
313a3dc7
CO		 1075{
1076 u64 efer;
313a3dc7
CO		 1077
1078 rdmsrl(MSR_EFER, efer);
07716717
DK		 1079 return efer & EFER_NX;
1080}
1081
1082static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1083{
1084 int i;
1085 struct kvm_cpuid_entry2 *e, *entry;
1086
313a3dc7 1087 entry = NULL;
ad312c7c
ZX		 1088 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1089 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1090 if (e->function == 0x80000001) {
1091 entry = e;
1092 break;
1093 }
1094 }
07716717 1095 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1096 entry->edx &= ~(1 << 20);
1097 printk(KERN_INFO "kvm: guest NX capability removed\n");
1098 }
1099}
1100
07716717 1101/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1102static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1103 struct kvm_cpuid *cpuid,
1104 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1105{
1106 int r, i;
1107 struct kvm_cpuid_entry *cpuid_entries;
1108
1109 r = -E2BIG;
1110 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1111 goto out;
1112 r = -ENOMEM;
1113 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1114 if (!cpuid_entries)
1115 goto out;
1116 r = -EFAULT;
1117 if (copy_from_user(cpuid_entries, entries,
1118 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1119 goto out_free;
1120 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1121 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1122 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1123 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1124 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1125 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1126 vcpu->arch.cpuid_entries[i].index = 0;
1127 vcpu->arch.cpuid_entries[i].flags = 0;
1128 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1129 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1130 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1131 }
1132 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1133 cpuid_fix_nx_cap(vcpu);
1134 r = 0;
1135
1136out_free:
1137 vfree(cpuid_entries);
1138out:
1139 return r;
1140}
1141
1142static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
1143 struct kvm_cpuid2 *cpuid,
1144 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1145{
1146 int r;
1147
1148 r = -E2BIG;
1149 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1150 goto out;
1151 r = -EFAULT;
ad312c7c 1152 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1153 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1154 goto out;
ad312c7c 1155 vcpu->arch.cpuid_nent = cpuid->nent;
313a3dc7
CO		 1156 return 0;
1157
1158out:
1159 return r;
1160}
1161
07716717
DK		 1162static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
1163 struct kvm_cpuid2 *cpuid,
1164 struct kvm_cpuid_entry2 __user *entries)
1165{
1166 int r;
1167
1168 r = -E2BIG;
ad312c7c 1169 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1170 goto out;
1171 r = -EFAULT;
ad312c7c
ZX		 1172 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
1173 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1174 goto out;
1175 return 0;
1176
1177out:
ad312c7c 1178 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1179 return r;
1180}
1181
1182static inline u32 bit(int bitno)
1183{
1184 return 1 << (bitno & 31);
1185}
1186
1187static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1188 u32 index)
1189{
1190 entry->function = function;
1191 entry->index = index;
1192 cpuid_count(entry->function, entry->index,
1193 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
1194 entry->flags = 0;
1195}
1196
1197static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1198 u32 index, int *nent, int maxnent)
1199{
1200 const u32 kvm_supported_word0_x86_features = bit(X86_FEATURE_FPU) |
1201 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1202 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1203 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1204 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1205 bit(X86_FEATURE_SEP) | bit(X86_FEATURE_PGE) |
1206 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1207 bit(X86_FEATURE_CLFLSH) | bit(X86_FEATURE_MMX) |
1208 bit(X86_FEATURE_FXSR) | bit(X86_FEATURE_XMM) |
1209 bit(X86_FEATURE_XMM2) | bit(X86_FEATURE_SELFSNOOP);
1210 const u32 kvm_supported_word1_x86_features = bit(X86_FEATURE_FPU) |
1211 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1212 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1213 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1214 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1215 bit(X86_FEATURE_PGE) |
1216 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1217 bit(X86_FEATURE_MMX) | bit(X86_FEATURE_FXSR) |
1218 bit(X86_FEATURE_SYSCALL) |
1219 (bit(X86_FEATURE_NX) && is_efer_nx()) |
1220#ifdef CONFIG_X86_64
1221 bit(X86_FEATURE_LM) |
1222#endif
1223 bit(X86_FEATURE_MMXEXT) |
1224 bit(X86_FEATURE_3DNOWEXT) |
1225 bit(X86_FEATURE_3DNOW);
1226 const u32 kvm_supported_word3_x86_features =
1227 bit(X86_FEATURE_XMM3) | bit(X86_FEATURE_CX16);
1228 const u32 kvm_supported_word6_x86_features =
1229 bit(X86_FEATURE_LAHF_LM) | bit(X86_FEATURE_CMP_LEGACY);
1230
1231 /* all func 2 cpuid_count() should be called on the same cpu */
1232 get_cpu();
1233 do_cpuid_1_ent(entry, function, index);
1234 ++*nent;
1235
1236 switch (function) {
1237 case 0:
1238 entry->eax = min(entry->eax, (u32)0xb);
1239 break;
1240 case 1:
1241 entry->edx &= kvm_supported_word0_x86_features;
1242 entry->ecx &= kvm_supported_word3_x86_features;
1243 break;
1244 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1245 * may return different values. This forces us to get_cpu() before
1246 * issuing the first command, and also to emulate this annoying behavior
1247 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1248 case 2: {
1249 int t, times = entry->eax & 0xff;
1250
1251 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1252 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1253 for (t = 1; t < times && *nent < maxnent; ++t) {
1254 do_cpuid_1_ent(&entry[t], function, 0);
1255 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1256 ++*nent;
1257 }
1258 break;
1259 }
1260 /* function 4 and 0xb have additional index. */
1261 case 4: {
14af3f3c 1262 int i, cache_type;
07716717
DK		 1263
1264 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1265 /* read more entries until cache_type is zero */
14af3f3c
HH		 1266 for (i = 1; *nent < maxnent; ++i) {
1267 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1268 if (!cache_type)
1269 break;
14af3f3c
HH		 1270 do_cpuid_1_ent(&entry[i], function, i);
1271 entry[i].flags |=
07716717
DK		 1272 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1273 ++*nent;
1274 }
1275 break;
1276 }
1277 case 0xb: {
14af3f3c 1278 int i, level_type;
07716717
DK		 1279
1280 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1281 /* read more entries until level_type is zero */
14af3f3c 1282 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1283 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1284 if (!level_type)
1285 break;
14af3f3c
HH		 1286 do_cpuid_1_ent(&entry[i], function, i);
1287 entry[i].flags |=
07716717
DK		 1288 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1289 ++*nent;
1290 }
1291 break;
1292 }
1293 case 0x80000000:
1294 entry->eax = min(entry->eax, 0x8000001a);
1295 break;
1296 case 0x80000001:
1297 entry->edx &= kvm_supported_word1_x86_features;
1298 entry->ecx &= kvm_supported_word6_x86_features;
1299 break;
1300 }
1301 put_cpu();
1302}
1303
674eea0f 1304static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
07716717
DK		 1305 struct kvm_cpuid_entry2 __user *entries)
1306{
1307 struct kvm_cpuid_entry2 *cpuid_entries;
1308 int limit, nent = 0, r = -E2BIG;
1309 u32 func;
1310
1311 if (cpuid->nent < 1)
1312 goto out;
1313 r = -ENOMEM;
1314 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1315 if (!cpuid_entries)
1316 goto out;
1317
1318 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1319 limit = cpuid_entries[0].eax;
1320 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1321 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1322 &nent, cpuid->nent);
1323 r = -E2BIG;
1324 if (nent >= cpuid->nent)
1325 goto out_free;
1326
1327 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1328 limit = cpuid_entries[nent - 1].eax;
1329 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1330 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1331 &nent, cpuid->nent);
1332 r = -EFAULT;
1333 if (copy_to_user(entries, cpuid_entries,
1334 nent * sizeof(struct kvm_cpuid_entry2)))
1335 goto out_free;
1336 cpuid->nent = nent;
1337 r = 0;
1338
1339out_free:
1340 vfree(cpuid_entries);
1341out:
1342 return r;
1343}
1344
313a3dc7
CO		 1345static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1346 struct kvm_lapic_state *s)
1347{
1348 vcpu_load(vcpu);
ad312c7c 1349 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1350 vcpu_put(vcpu);
1351
1352 return 0;
1353}
1354
1355static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1356 struct kvm_lapic_state *s)
1357{
1358 vcpu_load(vcpu);
ad312c7c 1359 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7
CO		 1360 kvm_apic_post_state_restore(vcpu);
1361 vcpu_put(vcpu);
1362
1363 return 0;
1364}
1365
f77bc6a4
ZX		 1366static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1367 struct kvm_interrupt *irq)
1368{
1369 if (irq->irq < 0 || irq->irq >= 256)
1370 return -EINVAL;
1371 if (irqchip_in_kernel(vcpu->kvm))
1372 return -ENXIO;
1373 vcpu_load(vcpu);
1374
ad312c7c
ZX		 1375 set_bit(irq->irq, vcpu->arch.irq_pending);
1376 set_bit(irq->irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
f77bc6a4
ZX		 1377
1378 vcpu_put(vcpu);
1379
1380 return 0;
1381}
1382
c4abb7c9
JK		 1383static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1384{
1385 vcpu_load(vcpu);
1386 kvm_inject_nmi(vcpu);
1387 vcpu_put(vcpu);
1388
1389 return 0;
1390}
1391
b209749f
AK		 1392static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1393 struct kvm_tpr_access_ctl *tac)
1394{
1395 if (tac->flags)
1396 return -EINVAL;
1397 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1398 return 0;
1399}
1400
313a3dc7
CO		 1401long kvm_arch_vcpu_ioctl(struct file *filp,
1402 unsigned int ioctl, unsigned long arg)
1403{
1404 struct kvm_vcpu *vcpu = filp->private_data;
1405 void __user *argp = (void __user *)arg;
1406 int r;
b772ff36 1407 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 1408
1409 switch (ioctl) {
1410 case KVM_GET_LAPIC: {
b772ff36 1411 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 1412
b772ff36
DH		 1413 r = -ENOMEM;
1414 if (!lapic)
1415 goto out;
1416 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 1417 if (r)
1418 goto out;
1419 r = -EFAULT;
b772ff36 1420 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 1421 goto out;
1422 r = 0;
1423 break;
1424 }
1425 case KVM_SET_LAPIC: {
b772ff36
DH		 1426 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1427 r = -ENOMEM;
1428 if (!lapic)
1429 goto out;
313a3dc7 1430 r = -EFAULT;
b772ff36 1431 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 1432 goto out;
b772ff36 1433 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 1434 if (r)
1435 goto out;
1436 r = 0;
1437 break;
1438 }
f77bc6a4
ZX		 1439 case KVM_INTERRUPT: {
1440 struct kvm_interrupt irq;
1441
1442 r = -EFAULT;
1443 if (copy_from_user(&irq, argp, sizeof irq))
1444 goto out;
1445 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1446 if (r)
1447 goto out;
1448 r = 0;
1449 break;
1450 }
c4abb7c9
JK		 1451 case KVM_NMI: {
1452 r = kvm_vcpu_ioctl_nmi(vcpu);
1453 if (r)
1454 goto out;
1455 r = 0;
1456 break;
1457 }
313a3dc7
CO		 1458 case KVM_SET_CPUID: {
1459 struct kvm_cpuid __user *cpuid_arg = argp;
1460 struct kvm_cpuid cpuid;
1461
1462 r = -EFAULT;
1463 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1464 goto out;
1465 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1466 if (r)
1467 goto out;
1468 break;
1469 }
07716717
DK		 1470 case KVM_SET_CPUID2: {
1471 struct kvm_cpuid2 __user *cpuid_arg = argp;
1472 struct kvm_cpuid2 cpuid;
1473
1474 r = -EFAULT;
1475 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1476 goto out;
1477 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
1478 cpuid_arg->entries);
1479 if (r)
1480 goto out;
1481 break;
1482 }
1483 case KVM_GET_CPUID2: {
1484 struct kvm_cpuid2 __user *cpuid_arg = argp;
1485 struct kvm_cpuid2 cpuid;
1486
1487 r = -EFAULT;
1488 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1489 goto out;
1490 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
1491 cpuid_arg->entries);
1492 if (r)
1493 goto out;
1494 r = -EFAULT;
1495 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1496 goto out;
1497 r = 0;
1498 break;
1499 }
313a3dc7
CO		 1500 case KVM_GET_MSRS:
1501 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1502 break;
1503 case KVM_SET_MSRS:
1504 r = msr_io(vcpu, argp, do_set_msr, 0);
1505 break;
b209749f
AK		 1506 case KVM_TPR_ACCESS_REPORTING: {
1507 struct kvm_tpr_access_ctl tac;
1508
1509 r = -EFAULT;
1510 if (copy_from_user(&tac, argp, sizeof tac))
1511 goto out;
1512 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1513 if (r)
1514 goto out;
1515 r = -EFAULT;
1516 if (copy_to_user(argp, &tac, sizeof tac))
1517 goto out;
1518 r = 0;
1519 break;
1520 };
b93463aa
AK		 1521 case KVM_SET_VAPIC_ADDR: {
1522 struct kvm_vapic_addr va;
1523
1524 r = -EINVAL;
1525 if (!irqchip_in_kernel(vcpu->kvm))
1526 goto out;
1527 r = -EFAULT;
1528 if (copy_from_user(&va, argp, sizeof va))
1529 goto out;
1530 r = 0;
1531 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1532 break;
1533 }
313a3dc7
CO		 1534 default:
1535 r = -EINVAL;
1536 }
1537out:
b772ff36
DH		 1538 if (lapic)
1539 kfree(lapic);
313a3dc7
CO		 1540 return r;
1541}
1542
1fe779f8
CO		 1543static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1544{
1545 int ret;
1546
1547 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1548 return -1;
1549 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1550 return ret;
1551}
1552
1553static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1554 u32 kvm_nr_mmu_pages)
1555{
1556 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1557 return -EINVAL;
1558
72dc67a6 1559 down_write(&kvm->slots_lock);
1fe779f8
CO		 1560
1561 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1562 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1563
72dc67a6 1564 up_write(&kvm->slots_lock);
1fe779f8
CO		 1565 return 0;
1566}
1567
1568static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1569{
f05e70ac 1570 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1571}
1572
e9f85cde
ZX		 1573gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1574{
1575 int i;
1576 struct kvm_mem_alias *alias;
1577
d69fb81f
ZX		 1578 for (i = 0; i < kvm->arch.naliases; ++i) {
1579 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1580 if (gfn >= alias->base_gfn
1581 && gfn < alias->base_gfn + alias->npages)
1582 return alias->target_gfn + gfn - alias->base_gfn;
1583 }
1584 return gfn;
1585}
1586
1fe779f8
CO		 1587/*
1588 * Set a new alias region. Aliases map a portion of physical memory into
1589 * another portion. This is useful for memory windows, for example the PC
1590 * VGA region.
1591 */
1592static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1593 struct kvm_memory_alias *alias)
1594{
1595 int r, n;
1596 struct kvm_mem_alias *p;
1597
1598 r = -EINVAL;
1599 /* General sanity checks */
1600 if (alias->memory_size & (PAGE_SIZE - 1))
1601 goto out;
1602 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1603 goto out;
1604 if (alias->slot >= KVM_ALIAS_SLOTS)
1605 goto out;
1606 if (alias->guest_phys_addr + alias->memory_size
1607 < alias->guest_phys_addr)
1608 goto out;
1609 if (alias->target_phys_addr + alias->memory_size
1610 < alias->target_phys_addr)
1611 goto out;
1612
72dc67a6 1613 down_write(&kvm->slots_lock);
a1708ce8 1614 spin_lock(&kvm->mmu_lock);
1fe779f8 1615
d69fb81f 1616 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 1617 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1618 p->npages = alias->memory_size >> PAGE_SHIFT;
1619 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1620
1621 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 1622 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 1623 break;
d69fb81f 1624 kvm->arch.naliases = n;
1fe779f8 1625
a1708ce8 1626 spin_unlock(&kvm->mmu_lock);
1fe779f8
CO		 1627 kvm_mmu_zap_all(kvm);
1628
72dc67a6 1629 up_write(&kvm->slots_lock);
1fe779f8
CO		 1630
1631 return 0;
1632
1633out:
1634 return r;
1635}
1636
1637static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1638{
1639 int r;
1640
1641 r = 0;
1642 switch (chip->chip_id) {
1643 case KVM_IRQCHIP_PIC_MASTER:
1644 memcpy(&chip->chip.pic,
1645 &pic_irqchip(kvm)->pics[0],
1646 sizeof(struct kvm_pic_state));
1647 break;
1648 case KVM_IRQCHIP_PIC_SLAVE:
1649 memcpy(&chip->chip.pic,
1650 &pic_irqchip(kvm)->pics[1],
1651 sizeof(struct kvm_pic_state));
1652 break;
1653 case KVM_IRQCHIP_IOAPIC:
1654 memcpy(&chip->chip.ioapic,
1655 ioapic_irqchip(kvm),
1656 sizeof(struct kvm_ioapic_state));
1657 break;
1658 default:
1659 r = -EINVAL;
1660 break;
1661 }
1662 return r;
1663}
1664
1665static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1666{
1667 int r;
1668
1669 r = 0;
1670 switch (chip->chip_id) {
1671 case KVM_IRQCHIP_PIC_MASTER:
1672 memcpy(&pic_irqchip(kvm)->pics[0],
1673 &chip->chip.pic,
1674 sizeof(struct kvm_pic_state));
1675 break;
1676 case KVM_IRQCHIP_PIC_SLAVE:
1677 memcpy(&pic_irqchip(kvm)->pics[1],
1678 &chip->chip.pic,
1679 sizeof(struct kvm_pic_state));
1680 break;
1681 case KVM_IRQCHIP_IOAPIC:
1682 memcpy(ioapic_irqchip(kvm),
1683 &chip->chip.ioapic,
1684 sizeof(struct kvm_ioapic_state));
1685 break;
1686 default:
1687 r = -EINVAL;
1688 break;
1689 }
1690 kvm_pic_update_irq(pic_irqchip(kvm));
1691 return r;
1692}
1693
e0f63cb9
SY		 1694static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1695{
1696 int r = 0;
1697
1698 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
1699 return r;
1700}
1701
1702static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1703{
1704 int r = 0;
1705
1706 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
1707 kvm_pit_load_count(kvm, 0, ps->channels[0].count);
1708 return r;
1709}
1710
5bb064dc
ZX		 1711/*
1712 * Get (and clear) the dirty memory log for a memory slot.
1713 */
1714int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
1715 struct kvm_dirty_log *log)
1716{
1717 int r;
1718 int n;
1719 struct kvm_memory_slot *memslot;
1720 int is_dirty = 0;
1721
72dc67a6 1722 down_write(&kvm->slots_lock);
5bb064dc
ZX		 1723
1724 r = kvm_get_dirty_log(kvm, log, &is_dirty);
1725 if (r)
1726 goto out;
1727
1728 /* If nothing is dirty, don't bother messing with page tables. */
1729 if (is_dirty) {
1730 kvm_mmu_slot_remove_write_access(kvm, log->slot);
1731 kvm_flush_remote_tlbs(kvm);
1732 memslot = &kvm->memslots[log->slot];
1733 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
1734 memset(memslot->dirty_bitmap, 0, n);
1735 }
1736 r = 0;
1737out:
72dc67a6 1738 up_write(&kvm->slots_lock);
5bb064dc
ZX		 1739 return r;
1740}
1741
1fe779f8
CO		 1742long kvm_arch_vm_ioctl(struct file *filp,
1743 unsigned int ioctl, unsigned long arg)
1744{
1745 struct kvm *kvm = filp->private_data;
1746 void __user *argp = (void __user *)arg;
1747 int r = -EINVAL;
f0d66275
DH		 1748 /*
1749 * This union makes it completely explicit to gcc-3.x
1750 * that these two variables' stack usage should be
1751 * combined, not added together.
1752 */
1753 union {
1754 struct kvm_pit_state ps;
1755 struct kvm_memory_alias alias;
1756 } u;
1fe779f8
CO		 1757
1758 switch (ioctl) {
1759 case KVM_SET_TSS_ADDR:
1760 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1761 if (r < 0)
1762 goto out;
1763 break;
1764 case KVM_SET_MEMORY_REGION: {
1765 struct kvm_memory_region kvm_mem;
1766 struct kvm_userspace_memory_region kvm_userspace_mem;
1767
1768 r = -EFAULT;
1769 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
1770 goto out;
1771 kvm_userspace_mem.slot = kvm_mem.slot;
1772 kvm_userspace_mem.flags = kvm_mem.flags;
1773 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
1774 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
1775 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
1776 if (r)
1777 goto out;
1778 break;
1779 }
1780 case KVM_SET_NR_MMU_PAGES:
1781 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1782 if (r)
1783 goto out;
1784 break;
1785 case KVM_GET_NR_MMU_PAGES:
1786 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
1787 break;
f0d66275 1788 case KVM_SET_MEMORY_ALIAS:
1fe779f8 1789 r = -EFAULT;
f0d66275 1790 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 1791 goto out;
f0d66275 1792 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 1793 if (r)
1794 goto out;
1795 break;
1fe779f8
CO		 1796 case KVM_CREATE_IRQCHIP:
1797 r = -ENOMEM;
d7deeeb0
ZX		 1798 kvm->arch.vpic = kvm_create_pic(kvm);
1799 if (kvm->arch.vpic) {
1fe779f8
CO		 1800 r = kvm_ioapic_init(kvm);
1801 if (r) {
d7deeeb0
ZX		 1802 kfree(kvm->arch.vpic);
1803 kvm->arch.vpic = NULL;
1fe779f8
CO		 1804 goto out;
1805 }
1806 } else
1807 goto out;
1808 break;
7837699f
SY		 1809 case KVM_CREATE_PIT:
1810 r = -ENOMEM;
1811 kvm->arch.vpit = kvm_create_pit(kvm);
1812 if (kvm->arch.vpit)
1813 r = 0;
1814 break;
1fe779f8
CO		 1815 case KVM_IRQ_LINE: {
1816 struct kvm_irq_level irq_event;
1817
1818 r = -EFAULT;
1819 if (copy_from_user(&irq_event, argp, sizeof irq_event))
1820 goto out;
1821 if (irqchip_in_kernel(kvm)) {
1822 mutex_lock(&kvm->lock);
5550af4d
SY		 1823 kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
1824 irq_event.irq, irq_event.level);
1fe779f8
CO		 1825 mutex_unlock(&kvm->lock);
1826 r = 0;
1827 }
1828 break;
1829 }
1830 case KVM_GET_IRQCHIP: {
1831 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 1832 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 1833
f0d66275
DH		 1834 r = -ENOMEM;
1835 if (!chip)
1fe779f8 1836 goto out;
f0d66275
DH		 1837 r = -EFAULT;
1838 if (copy_from_user(chip, argp, sizeof *chip))
1839 goto get_irqchip_out;
1fe779f8
CO		 1840 r = -ENXIO;
1841 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 1842 goto get_irqchip_out;
1843 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 1844 if (r)
f0d66275 1845 goto get_irqchip_out;
1fe779f8 1846 r = -EFAULT;
f0d66275
DH		 1847 if (copy_to_user(argp, chip, sizeof *chip))
1848 goto get_irqchip_out;
1fe779f8 1849 r = 0;
f0d66275
DH		 1850 get_irqchip_out:
1851 kfree(chip);
1852 if (r)
1853 goto out;
1fe779f8
CO		 1854 break;
1855 }
1856 case KVM_SET_IRQCHIP: {
1857 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 1858 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 1859
f0d66275
DH		 1860 r = -ENOMEM;
1861 if (!chip)
1fe779f8 1862 goto out;
f0d66275
DH		 1863 r = -EFAULT;
1864 if (copy_from_user(chip, argp, sizeof *chip))
1865 goto set_irqchip_out;
1fe779f8
CO		 1866 r = -ENXIO;
1867 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 1868 goto set_irqchip_out;
1869 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 1870 if (r)
f0d66275 1871 goto set_irqchip_out;
1fe779f8 1872 r = 0;
f0d66275
DH		 1873 set_irqchip_out:
1874 kfree(chip);
1875 if (r)
1876 goto out;
1fe779f8
CO		 1877 break;
1878 }
e0f63cb9 1879 case KVM_GET_PIT: {
e0f63cb9 1880 r = -EFAULT;
f0d66275 1881 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 1882 goto out;
1883 r = -ENXIO;
1884 if (!kvm->arch.vpit)
1885 goto out;
f0d66275 1886 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 1887 if (r)
1888 goto out;
1889 r = -EFAULT;
f0d66275 1890 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 1891 goto out;
1892 r = 0;
1893 break;
1894 }
1895 case KVM_SET_PIT: {
e0f63cb9 1896 r = -EFAULT;
f0d66275 1897 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 1898 goto out;
1899 r = -ENXIO;
1900 if (!kvm->arch.vpit)
1901 goto out;
f0d66275 1902 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 1903 if (r)
1904 goto out;
1905 r = 0;
1906 break;
1907 }
1fe779f8
CO		 1908 default:
1909 ;
1910 }
1911out:
1912 return r;
1913}
1914
a16b043c 1915static void kvm_init_msr_list(void)
043405e1
CO		 1916{
1917 u32 dummy[2];
1918 unsigned i, j;
1919
1920 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
1921 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
1922 continue;
1923 if (j < i)
1924 msrs_to_save[j] = msrs_to_save[i];
1925 j++;
1926 }
1927 num_msrs_to_save = j;
1928}
1929
bbd9b64e
CO		 1930/*
1931 * Only apic need an MMIO device hook, so shortcut now..
1932 */
1933static struct kvm_io_device *vcpu_find_pervcpu_dev(struct kvm_vcpu *vcpu,
92760499
LV		 1934 gpa_t addr, int len,
1935 int is_write)
bbd9b64e
CO		 1936{
1937 struct kvm_io_device *dev;
1938
ad312c7c
ZX		 1939 if (vcpu->arch.apic) {
1940 dev = &vcpu->arch.apic->dev;
92760499 1941 if (dev->in_range(dev, addr, len, is_write))
bbd9b64e
CO		 1942 return dev;
1943 }
1944 return NULL;
1945}
1946
1947
1948static struct kvm_io_device *vcpu_find_mmio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 1949 gpa_t addr, int len,
1950 int is_write)
bbd9b64e
CO		 1951{
1952 struct kvm_io_device *dev;
1953
92760499 1954 dev = vcpu_find_pervcpu_dev(vcpu, addr, len, is_write);
bbd9b64e 1955 if (dev == NULL)
92760499
LV		 1956 dev = kvm_io_bus_find_dev(&vcpu->kvm->mmio_bus, addr, len,
1957 is_write);
bbd9b64e
CO		 1958 return dev;
1959}
1960
1961int emulator_read_std(unsigned long addr,
1962 void *val,
1963 unsigned int bytes,
1964 struct kvm_vcpu *vcpu)
1965{
1966 void *data = val;
10589a46 1967 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 1968
1969 while (bytes) {
ad312c7c 1970 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 1971 unsigned offset = addr & (PAGE_SIZE-1);
1972 unsigned tocopy = min(bytes, (unsigned)PAGE_SIZE - offset);
1973 int ret;
1974
10589a46
MT		 1975 if (gpa == UNMAPPED_GVA) {
1976 r = X86EMUL_PROPAGATE_FAULT;
1977 goto out;
1978 }
bbd9b64e 1979 ret = kvm_read_guest(vcpu->kvm, gpa, data, tocopy);
10589a46
MT		 1980 if (ret < 0) {
1981 r = X86EMUL_UNHANDLEABLE;
1982 goto out;
1983 }
bbd9b64e
CO		 1984
1985 bytes -= tocopy;
1986 data += tocopy;
1987 addr += tocopy;
1988 }
10589a46 1989out:
10589a46 1990 return r;
bbd9b64e
CO		 1991}
1992EXPORT_SYMBOL_GPL(emulator_read_std);
1993
bbd9b64e
CO		 1994static int emulator_read_emulated(unsigned long addr,
1995 void *val,
1996 unsigned int bytes,
1997 struct kvm_vcpu *vcpu)
1998{
1999 struct kvm_io_device *mmio_dev;
2000 gpa_t gpa;
2001
2002 if (vcpu->mmio_read_completed) {
2003 memcpy(val, vcpu->mmio_data, bytes);
2004 vcpu->mmio_read_completed = 0;
2005 return X86EMUL_CONTINUE;
2006 }
2007
ad312c7c 2008 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2009
2010 /* For APIC access vmexit */
2011 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2012 goto mmio;
2013
2014 if (emulator_read_std(addr, val, bytes, vcpu)
2015 == X86EMUL_CONTINUE)
2016 return X86EMUL_CONTINUE;
2017 if (gpa == UNMAPPED_GVA)
2018 return X86EMUL_PROPAGATE_FAULT;
2019
2020mmio:
2021 /*
2022 * Is this MMIO handled locally?
2023 */
10589a46 2024 mutex_lock(&vcpu->kvm->lock);
92760499 2025 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 0);
bbd9b64e
CO		 2026 if (mmio_dev) {
2027 kvm_iodevice_read(mmio_dev, gpa, bytes, val);
10589a46 2028 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2029 return X86EMUL_CONTINUE;
2030 }
10589a46 2031 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2032
2033 vcpu->mmio_needed = 1;
2034 vcpu->mmio_phys_addr = gpa;
2035 vcpu->mmio_size = bytes;
2036 vcpu->mmio_is_write = 0;
2037
2038 return X86EMUL_UNHANDLEABLE;
2039}
2040
3200f405 2041int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 2042 const void *val, int bytes)
bbd9b64e
CO		 2043{
2044 int ret;
2045
2046 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 2047 if (ret < 0)
bbd9b64e 2048 return 0;
ad218f85 2049 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 2050 return 1;
2051}
2052
2053static int emulator_write_emulated_onepage(unsigned long addr,
2054 const void *val,
2055 unsigned int bytes,
2056 struct kvm_vcpu *vcpu)
2057{
2058 struct kvm_io_device *mmio_dev;
10589a46
MT		 2059 gpa_t gpa;
2060
10589a46 2061 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2062
2063 if (gpa == UNMAPPED_GVA) {
c3c91fee 2064 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 2065 return X86EMUL_PROPAGATE_FAULT;
2066 }
2067
2068 /* For APIC access vmexit */
2069 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2070 goto mmio;
2071
2072 if (emulator_write_phys(vcpu, gpa, val, bytes))
2073 return X86EMUL_CONTINUE;
2074
2075mmio:
2076 /*
2077 * Is this MMIO handled locally?
2078 */
10589a46 2079 mutex_lock(&vcpu->kvm->lock);
92760499 2080 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 1);
bbd9b64e
CO		 2081 if (mmio_dev) {
2082 kvm_iodevice_write(mmio_dev, gpa, bytes, val);
10589a46 2083 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2084 return X86EMUL_CONTINUE;
2085 }
10589a46 2086 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2087
2088 vcpu->mmio_needed = 1;
2089 vcpu->mmio_phys_addr = gpa;
2090 vcpu->mmio_size = bytes;
2091 vcpu->mmio_is_write = 1;
2092 memcpy(vcpu->mmio_data, val, bytes);
2093
2094 return X86EMUL_CONTINUE;
2095}
2096
2097int emulator_write_emulated(unsigned long addr,
2098 const void *val,
2099 unsigned int bytes,
2100 struct kvm_vcpu *vcpu)
2101{
2102 /* Crossing a page boundary? */
2103 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2104 int rc, now;
2105
2106 now = -addr & ~PAGE_MASK;
2107 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2108 if (rc != X86EMUL_CONTINUE)
2109 return rc;
2110 addr += now;
2111 val += now;
2112 bytes -= now;
2113 }
2114 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2115}
2116EXPORT_SYMBOL_GPL(emulator_write_emulated);
2117
2118static int emulator_cmpxchg_emulated(unsigned long addr,
2119 const void *old,
2120 const void *new,
2121 unsigned int bytes,
2122 struct kvm_vcpu *vcpu)
2123{
2124 static int reported;
2125
2126 if (!reported) {
2127 reported = 1;
2128 printk(KERN_WARNING "kvm: emulating exchange as write\n");
2129 }
2bacc55c
MT		 2130#ifndef CONFIG_X86_64
2131 /* guests cmpxchg8b have to be emulated atomically */
2132 if (bytes == 8) {
10589a46 2133 gpa_t gpa;
2bacc55c 2134 struct page *page;
c0b49b0d 2135 char *kaddr;
2bacc55c
MT		 2136 u64 val;
2137
10589a46
MT		 2138 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2139
2bacc55c
MT		 2140 if (gpa == UNMAPPED_GVA ||
2141 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2142 goto emul_write;
2143
2144 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2145 goto emul_write;
2146
2147 val = *(u64 *)new;
72dc67a6 2148
2bacc55c 2149 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 2150
c0b49b0d
AM		 2151 kaddr = kmap_atomic(page, KM_USER0);
2152 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2153 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 2154 kvm_release_page_dirty(page);
2155 }
3200f405 2156emul_write:
2bacc55c
MT		 2157#endif
2158
bbd9b64e
CO		 2159 return emulator_write_emulated(addr, new, bytes, vcpu);
2160}
2161
2162static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2163{
2164 return kvm_x86_ops->get_segment_base(vcpu, seg);
2165}
2166
2167int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2168{
a7052897 2169 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 2170 return X86EMUL_CONTINUE;
2171}
2172
2173int emulate_clts(struct kvm_vcpu *vcpu)
2174{
54e445ca 2175 KVMTRACE_0D(CLTS, vcpu, handler);
ad312c7c 2176 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 2177 return X86EMUL_CONTINUE;
2178}
2179
2180int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2181{
2182 struct kvm_vcpu *vcpu = ctxt->vcpu;
2183
2184 switch (dr) {
2185 case 0 ... 3:
2186 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2187 return X86EMUL_CONTINUE;
2188 default:
b8688d51 2189 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2190 return X86EMUL_UNHANDLEABLE;
2191 }
2192}
2193
2194int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2195{
2196 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2197 int exception;
2198
2199 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2200 if (exception) {
2201 /* FIXME: better handling */
2202 return X86EMUL_UNHANDLEABLE;
2203 }
2204 return X86EMUL_CONTINUE;
2205}
2206
2207void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2208{
bbd9b64e 2209 u8 opcodes[4];
5fdbf976 2210 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 2211 unsigned long rip_linear;
2212
f76c710d 2213 if (!printk_ratelimit())
bbd9b64e
CO		 2214 return;
2215
25be4608
GC		 2216 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2217
bbd9b64e
CO		 2218 emulator_read_std(rip_linear, (void *)opcodes, 4, vcpu);
2219
2220 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2221 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 2222}
2223EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2224
14af3f3c 2225static struct x86_emulate_ops emulate_ops = {
bbd9b64e 2226 .read_std = emulator_read_std,
bbd9b64e
CO		 2227 .read_emulated = emulator_read_emulated,
2228 .write_emulated = emulator_write_emulated,
2229 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2230};
2231
5fdbf976
MT		 2232static void cache_all_regs(struct kvm_vcpu *vcpu)
2233{
2234 kvm_register_read(vcpu, VCPU_REGS_RAX);
2235 kvm_register_read(vcpu, VCPU_REGS_RSP);
2236 kvm_register_read(vcpu, VCPU_REGS_RIP);
2237 vcpu->arch.regs_dirty = ~0;
2238}
2239
bbd9b64e
CO		 2240int emulate_instruction(struct kvm_vcpu *vcpu,
2241 struct kvm_run *run,
2242 unsigned long cr2,
2243 u16 error_code,
571008da 2244 int emulation_type)
bbd9b64e
CO		 2245{
2246 int r;
571008da 2247 struct decode_cache *c;
bbd9b64e 2248
26eef70c 2249 kvm_clear_exception_queue(vcpu);
ad312c7c 2250 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976
MT		 2251 /*
2252 * TODO: fix x86_emulate.c to use guest_read/write_register
2253 * instead of direct ->regs accesses, can save hundred cycles
2254 * on Intel for instructions that don't read/change RSP, for
2255 * for example.
2256 */
2257 cache_all_regs(vcpu);
bbd9b64e
CO		 2258
2259 vcpu->mmio_is_write = 0;
ad312c7c 2260 vcpu->arch.pio.string = 0;
bbd9b64e 2261
571008da 2262 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2263 int cs_db, cs_l;
2264 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2265
ad312c7c
ZX		 2266 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2267 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2268 vcpu->arch.emulate_ctxt.mode =
2269 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2270 ? X86EMUL_MODE_REAL : cs_l
2271 ? X86EMUL_MODE_PROT64 : cs_db
2272 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2273
ad312c7c 2274 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da
SY		 2275
2276 /* Reject the instructions other than VMCALL/VMMCALL when
2277 * try to emulate invalid opcode */
2278 c = &vcpu->arch.emulate_ctxt.decode;
2279 if ((emulation_type & EMULTYPE_TRAP_UD) &&
2280 (!(c->twobyte && c->b == 0x01 &&
2281 (c->modrm_reg == 0 || c->modrm_reg == 3) &&
2282 c->modrm_mod == 3 && c->modrm_rm == 1)))
2283 return EMULATE_FAIL;
2284
f2b5756b 2285 ++vcpu->stat.insn_emulation;
bbd9b64e 2286 if (r) {
f2b5756b 2287 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2288 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2289 return EMULATE_DONE;
2290 return EMULATE_FAIL;
2291 }
2292 }
2293
ad312c7c 2294 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
bbd9b64e 2295
ad312c7c 2296 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2297 return EMULATE_DO_MMIO;
2298
2299 if ((r || vcpu->mmio_is_write) && run) {
2300 run->exit_reason = KVM_EXIT_MMIO;
2301 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2302 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2303 run->mmio.len = vcpu->mmio_size;
2304 run->mmio.is_write = vcpu->mmio_is_write;
2305 }
2306
2307 if (r) {
2308 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2309 return EMULATE_DONE;
2310 if (!vcpu->mmio_needed) {
2311 kvm_report_emulation_failure(vcpu, "mmio");
2312 return EMULATE_FAIL;
2313 }
2314 return EMULATE_DO_MMIO;
2315 }
2316
ad312c7c 2317 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2318
2319 if (vcpu->mmio_is_write) {
2320 vcpu->mmio_needed = 0;
2321 return EMULATE_DO_MMIO;
2322 }
2323
2324 return EMULATE_DONE;
2325}
2326EXPORT_SYMBOL_GPL(emulate_instruction);
2327
de7d789a
CO		 2328static void free_pio_guest_pages(struct kvm_vcpu *vcpu)
2329{
2330 int i;
2331
ad312c7c
ZX		 2332 for (i = 0; i < ARRAY_SIZE(vcpu->arch.pio.guest_pages); ++i)
2333 if (vcpu->arch.pio.guest_pages[i]) {
2334 kvm_release_page_dirty(vcpu->arch.pio.guest_pages[i]);
2335 vcpu->arch.pio.guest_pages[i] = NULL;
de7d789a
CO		 2336 }
2337}
2338
2339static int pio_copy_data(struct kvm_vcpu *vcpu)
2340{
ad312c7c 2341 void *p = vcpu->arch.pio_data;
de7d789a
CO		 2342 void *q;
2343 unsigned bytes;
ad312c7c 2344 int nr_pages = vcpu->arch.pio.guest_pages[1] ? 2 : 1;
de7d789a 2345
ad312c7c 2346 q = vmap(vcpu->arch.pio.guest_pages, nr_pages, VM_READ|VM_WRITE,
de7d789a
CO		 2347 PAGE_KERNEL);
2348 if (!q) {
2349 free_pio_guest_pages(vcpu);
2350 return -ENOMEM;
2351 }
ad312c7c
ZX		 2352 q += vcpu->arch.pio.guest_page_offset;
2353 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2354 if (vcpu->arch.pio.in)
de7d789a
CO		 2355 memcpy(q, p, bytes);
2356 else
2357 memcpy(p, q, bytes);
ad312c7c 2358 q -= vcpu->arch.pio.guest_page_offset;
de7d789a
CO		 2359 vunmap(q);
2360 free_pio_guest_pages(vcpu);
2361 return 0;
2362}
2363
2364int complete_pio(struct kvm_vcpu *vcpu)
2365{
ad312c7c 2366 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2367 long delta;
2368 int r;
5fdbf976 2369 unsigned long val;
de7d789a
CO		 2370
2371 if (!io->string) {
5fdbf976
MT		 2372 if (io->in) {
2373 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2374 memcpy(&val, vcpu->arch.pio_data, io->size);
2375 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2376 }
de7d789a
CO		 2377 } else {
2378 if (io->in) {
2379 r = pio_copy_data(vcpu);
5fdbf976 2380 if (r)
de7d789a 2381 return r;
de7d789a
CO		 2382 }
2383
2384 delta = 1;
2385 if (io->rep) {
2386 delta *= io->cur_count;
2387 /*
2388 * The size of the register should really depend on
2389 * current address size.
2390 */
5fdbf976
MT		 2391 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2392 val -= delta;
2393 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 2394 }
2395 if (io->down)
2396 delta = -delta;
2397 delta *= io->size;
5fdbf976
MT		 2398 if (io->in) {
2399 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2400 val += delta;
2401 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2402 } else {
2403 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2404 val += delta;
2405 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2406 }
de7d789a
CO		 2407 }
2408
de7d789a
CO		 2409 io->count -= io->cur_count;
2410 io->cur_count = 0;
2411
2412 return 0;
2413}
2414
2415static void kernel_pio(struct kvm_io_device *pio_dev,
2416 struct kvm_vcpu *vcpu,
2417 void *pd)
2418{
2419 /* TODO: String I/O for in kernel device */
2420
2421 mutex_lock(&vcpu->kvm->lock);
ad312c7c
ZX		 2422 if (vcpu->arch.pio.in)
2423 kvm_iodevice_read(pio_dev, vcpu->arch.pio.port,
2424 vcpu->arch.pio.size,
de7d789a
CO		 2425 pd);
2426 else
ad312c7c
ZX		 2427 kvm_iodevice_write(pio_dev, vcpu->arch.pio.port,
2428 vcpu->arch.pio.size,
de7d789a
CO		 2429 pd);
2430 mutex_unlock(&vcpu->kvm->lock);
2431}
2432
2433static void pio_string_write(struct kvm_io_device *pio_dev,
2434 struct kvm_vcpu *vcpu)
2435{
ad312c7c
ZX		 2436 struct kvm_pio_request *io = &vcpu->arch.pio;
2437 void *pd = vcpu->arch.pio_data;
de7d789a
CO		 2438 int i;
2439
2440 mutex_lock(&vcpu->kvm->lock);
2441 for (i = 0; i < io->cur_count; i++) {
2442 kvm_iodevice_write(pio_dev, io->port,
2443 io->size,
2444 pd);
2445 pd += io->size;
2446 }
2447 mutex_unlock(&vcpu->kvm->lock);
2448}
2449
2450static struct kvm_io_device *vcpu_find_pio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2451 gpa_t addr, int len,
2452 int is_write)
de7d789a 2453{
92760499 2454 return kvm_io_bus_find_dev(&vcpu->kvm->pio_bus, addr, len, is_write);
de7d789a
CO		 2455}
2456
2457int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2458 int size, unsigned port)
2459{
2460 struct kvm_io_device *pio_dev;
5fdbf976 2461 unsigned long val;
de7d789a
CO		 2462
2463 vcpu->run->exit_reason = KVM_EXIT_IO;
2464 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2465 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2466 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2467 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2468 vcpu->run->io.port = vcpu->arch.pio.port = port;
2469 vcpu->arch.pio.in = in;
2470 vcpu->arch.pio.string = 0;
2471 vcpu->arch.pio.down = 0;
2472 vcpu->arch.pio.guest_page_offset = 0;
2473 vcpu->arch.pio.rep = 0;
de7d789a 2474
2714d1d3
FEL		 2475 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2476 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2477 handler);
2478 else
2479 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2480 handler);
2481
5fdbf976
MT		 2482 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2483 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a 2484
92760499 2485 pio_dev = vcpu_find_pio_dev(vcpu, port, size, !in);
de7d789a 2486 if (pio_dev) {
ad312c7c 2487 kernel_pio(pio_dev, vcpu, vcpu->arch.pio_data);
de7d789a
CO		 2488 complete_pio(vcpu);
2489 return 1;
2490 }
2491 return 0;
2492}
2493EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2494
2495int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2496 int size, unsigned long count, int down,
2497 gva_t address, int rep, unsigned port)
2498{
2499 unsigned now, in_page;
2500 int i, ret = 0;
2501 int nr_pages = 1;
2502 struct page *page;
2503 struct kvm_io_device *pio_dev;
2504
2505 vcpu->run->exit_reason = KVM_EXIT_IO;
2506 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2507 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2508 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2509 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2510 vcpu->run->io.port = vcpu->arch.pio.port = port;
2511 vcpu->arch.pio.in = in;
2512 vcpu->arch.pio.string = 1;
2513 vcpu->arch.pio.down = down;
2514 vcpu->arch.pio.guest_page_offset = offset_in_page(address);
2515 vcpu->arch.pio.rep = rep;
de7d789a 2516
2714d1d3
FEL		 2517 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2518 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2519 handler);
2520 else
2521 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2522 handler);
2523
de7d789a
CO		 2524 if (!count) {
2525 kvm_x86_ops->skip_emulated_instruction(vcpu);
2526 return 1;
2527 }
2528
2529 if (!down)
2530 in_page = PAGE_SIZE - offset_in_page(address);
2531 else
2532 in_page = offset_in_page(address) + size;
2533 now = min(count, (unsigned long)in_page / size);
2534 if (!now) {
2535 /*
2536 * String I/O straddles page boundary. Pin two guest pages
2537 * so that we satisfy atomicity constraints. Do just one
2538 * transaction to avoid complexity.
2539 */
2540 nr_pages = 2;
2541 now = 1;
2542 }
2543 if (down) {
2544 /*
2545 * String I/O in reverse. Yuck. Kill the guest, fix later.
2546 */
2547 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 2548 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2549 return 1;
2550 }
2551 vcpu->run->io.count = now;
ad312c7c 2552 vcpu->arch.pio.cur_count = now;
de7d789a 2553
ad312c7c 2554 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 2555 kvm_x86_ops->skip_emulated_instruction(vcpu);
2556
2557 for (i = 0; i < nr_pages; ++i) {
de7d789a 2558 page = gva_to_page(vcpu, address + i * PAGE_SIZE);
ad312c7c 2559 vcpu->arch.pio.guest_pages[i] = page;
de7d789a 2560 if (!page) {
c1a5d4f9 2561 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2562 free_pio_guest_pages(vcpu);
2563 return 1;
2564 }
2565 }
2566
92760499
LV		 2567 pio_dev = vcpu_find_pio_dev(vcpu, port,
2568 vcpu->arch.pio.cur_count,
2569 !vcpu->arch.pio.in);
ad312c7c 2570 if (!vcpu->arch.pio.in) {
de7d789a
CO		 2571 /* string PIO write */
2572 ret = pio_copy_data(vcpu);
2573 if (ret >= 0 && pio_dev) {
2574 pio_string_write(pio_dev, vcpu);
2575 complete_pio(vcpu);
ad312c7c 2576 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 2577 ret = 1;
2578 }
2579 } else if (pio_dev)
2580 pr_unimpl(vcpu, "no string pio read support yet, "
2581 "port %x size %d count %ld\n",
2582 port, size, count);
2583
2584 return ret;
2585}
2586EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
2587
f8c16bba 2588int kvm_arch_init(void *opaque)
043405e1 2589{
56c6d28a 2590 int r;
f8c16bba
ZX		 2591 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
2592
f8c16bba
ZX		 2593 if (kvm_x86_ops) {
2594 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 2595 r = -EEXIST;
2596 goto out;
f8c16bba
ZX		 2597 }
2598
2599 if (!ops->cpu_has_kvm_support()) {
2600 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 2601 r = -EOPNOTSUPP;
2602 goto out;
f8c16bba
ZX		 2603 }
2604 if (ops->disabled_by_bios()) {
2605 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 2606 r = -EOPNOTSUPP;
2607 goto out;
f8c16bba
ZX		 2608 }
2609
97db56ce
AK		 2610 r = kvm_mmu_module_init();
2611 if (r)
2612 goto out;
2613
2614 kvm_init_msr_list();
2615
f8c16bba 2616 kvm_x86_ops = ops;
56c6d28a 2617 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 2618 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
2619 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
64d4d521 2620 PT_DIRTY_MASK, PT64_NX_MASK, 0, 0);
f8c16bba 2621 return 0;
56c6d28a
ZX		 2622
2623out:
56c6d28a 2624 return r;
043405e1 2625}
8776e519 2626
f8c16bba
ZX		 2627void kvm_arch_exit(void)
2628{
2629 kvm_x86_ops = NULL;
56c6d28a
ZX		 2630 kvm_mmu_module_exit();
2631}
f8c16bba 2632
8776e519
HB		 2633int kvm_emulate_halt(struct kvm_vcpu *vcpu)
2634{
2635 ++vcpu->stat.halt_exits;
2714d1d3 2636 KVMTRACE_0D(HLT, vcpu, handler);
8776e519 2637 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 2638 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 2639 return 1;
2640 } else {
2641 vcpu->run->exit_reason = KVM_EXIT_HLT;
2642 return 0;
2643 }
2644}
2645EXPORT_SYMBOL_GPL(kvm_emulate_halt);
2646
2f333bcb
MT		 2647static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
2648 unsigned long a1)
2649{
2650 if (is_long_mode(vcpu))
2651 return a0;
2652 else
2653 return a0 | ((gpa_t)a1 << 32);
2654}
2655
8776e519
HB		 2656int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
2657{
2658 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 2659 int r = 1;
8776e519 2660
5fdbf976
MT		 2661 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
2662 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
2663 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
2664 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
2665 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 2666
2714d1d3
FEL		 2667 KVMTRACE_1D(VMMCALL, vcpu, (u32)nr, handler);
2668
8776e519
HB		 2669 if (!is_long_mode(vcpu)) {
2670 nr &= 0xFFFFFFFF;
2671 a0 &= 0xFFFFFFFF;
2672 a1 &= 0xFFFFFFFF;
2673 a2 &= 0xFFFFFFFF;
2674 a3 &= 0xFFFFFFFF;
2675 }
2676
2677 switch (nr) {
b93463aa
AK		 2678 case KVM_HC_VAPIC_POLL_IRQ:
2679 ret = 0;
2680 break;
2f333bcb
MT		 2681 case KVM_HC_MMU_OP:
2682 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
2683 break;
8776e519
HB		 2684 default:
2685 ret = -KVM_ENOSYS;
2686 break;
2687 }
5fdbf976 2688 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 2689 ++vcpu->stat.hypercalls;
2f333bcb 2690 return r;
8776e519
HB		 2691}
2692EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
2693
2694int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
2695{
2696 char instruction[3];
2697 int ret = 0;
5fdbf976 2698 unsigned long rip = kvm_rip_read(vcpu);
8776e519 2699
8776e519
HB		 2700
2701 /*
2702 * Blow out the MMU to ensure that no other VCPU has an active mapping
2703 * to ensure that the updated hypercall appears atomically across all
2704 * VCPUs.
2705 */
2706 kvm_mmu_zap_all(vcpu->kvm);
2707
8776e519 2708 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 2709 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 2710 != X86EMUL_CONTINUE)
2711 ret = -EFAULT;
2712
8776e519
HB		 2713 return ret;
2714}
2715
2716static u64 mk_cr_64(u64 curr_cr, u32 new_val)
2717{
2718 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
2719}
2720
2721void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2722{
2723 struct descriptor_table dt = { limit, base };
2724
2725 kvm_x86_ops->set_gdt(vcpu, &dt);
2726}
2727
2728void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2729{
2730 struct descriptor_table dt = { limit, base };
2731
2732 kvm_x86_ops->set_idt(vcpu, &dt);
2733}
2734
2735void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
2736 unsigned long *rflags)
2737{
2d3ad1f4 2738 kvm_lmsw(vcpu, msw);
8776e519
HB		 2739 *rflags = kvm_x86_ops->get_rflags(vcpu);
2740}
2741
2742unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
2743{
54e445ca
JR		 2744 unsigned long value;
2745
8776e519
HB		 2746 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
2747 switch (cr) {
2748 case 0:
54e445ca
JR		 2749 value = vcpu->arch.cr0;
2750 break;
8776e519 2751 case 2:
54e445ca
JR		 2752 value = vcpu->arch.cr2;
2753 break;
8776e519 2754 case 3:
54e445ca
JR		 2755 value = vcpu->arch.cr3;
2756 break;
8776e519 2757 case 4:
54e445ca
JR		 2758 value = vcpu->arch.cr4;
2759 break;
152ff9be 2760 case 8:
54e445ca
JR		 2761 value = kvm_get_cr8(vcpu);
2762 break;
8776e519 2763 default:
b8688d51 2764 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2765 return 0;
2766 }
54e445ca
JR		 2767 KVMTRACE_3D(CR_READ, vcpu, (u32)cr, (u32)value,
2768 (u32)((u64)value >> 32), handler);
2769
2770 return value;
8776e519
HB		 2771}
2772
2773void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
2774 unsigned long *rflags)
2775{
54e445ca
JR		 2776 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)val,
2777 (u32)((u64)val >> 32), handler);
2778
8776e519
HB		 2779 switch (cr) {
2780 case 0:
2d3ad1f4 2781 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 2782 *rflags = kvm_x86_ops->get_rflags(vcpu);
2783 break;
2784 case 2:
ad312c7c 2785 vcpu->arch.cr2 = val;
8776e519
HB		 2786 break;
2787 case 3:
2d3ad1f4 2788 kvm_set_cr3(vcpu, val);
8776e519
HB		 2789 break;
2790 case 4:
2d3ad1f4 2791 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 2792 break;
152ff9be 2793 case 8:
2d3ad1f4 2794 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 2795 break;
8776e519 2796 default:
b8688d51 2797 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2798 }
2799}
2800
07716717
DK		 2801static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
2802{
ad312c7c
ZX		 2803 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
2804 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 2805
2806 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
2807 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 2808 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 2809 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 2810 if (ej->function == e->function) {
2811 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
2812 return j;
2813 }
2814 }
2815 return 0; /* silence gcc, even though control never reaches here */
2816}
2817
2818/* find an entry with matching function, matching index (if needed), and that
2819 * should be read next (if it's stateful) */
2820static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
2821 u32 function, u32 index)
2822{
2823 if (e->function != function)
2824 return 0;
2825 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
2826 return 0;
2827 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
2828 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
2829 return 0;
2830 return 1;
2831}
2832
8776e519
HB		 2833void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
2834{
2835 int i;
07716717
DK		 2836 u32 function, index;
2837 struct kvm_cpuid_entry2 *e, *best;
8776e519 2838
5fdbf976
MT		 2839 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
2840 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
2841 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
2842 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
2843 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
2844 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
8776e519 2845 best = NULL;
ad312c7c
ZX		 2846 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2847 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 2848 if (is_matching_cpuid_entry(e, function, index)) {
2849 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
2850 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 2851 best = e;
2852 break;
2853 }
2854 /*
2855 * Both basic or both extended?
2856 */
2857 if (((e->function ^ function) & 0x80000000) == 0)
2858 if (!best || e->function > best->function)
2859 best = e;
2860 }
2861 if (best) {
5fdbf976
MT		 2862 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
2863 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
2864 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
2865 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 2866 }
8776e519 2867 kvm_x86_ops->skip_emulated_instruction(vcpu);
2714d1d3 2868 KVMTRACE_5D(CPUID, vcpu, function,
5fdbf976
MT		 2869 (u32)kvm_register_read(vcpu, VCPU_REGS_RAX),
2870 (u32)kvm_register_read(vcpu, VCPU_REGS_RBX),
2871 (u32)kvm_register_read(vcpu, VCPU_REGS_RCX),
2872 (u32)kvm_register_read(vcpu, VCPU_REGS_RDX), handler);
8776e519
HB		 2873}
2874EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 2875
b6c7a5dc
HB		 2876/*
2877 * Check if userspace requested an interrupt window, and that the
2878 * interrupt window is open.
2879 *
2880 * No need to exit to userspace if we already have an interrupt queued.
2881 */
2882static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
2883 struct kvm_run *kvm_run)
2884{
ad312c7c 2885 return (!vcpu->arch.irq_summary &&
b6c7a5dc 2886 kvm_run->request_interrupt_window &&
ad312c7c 2887 vcpu->arch.interrupt_window_open &&
b6c7a5dc
HB		 2888 (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF));
2889}
2890
2891static void post_kvm_run_save(struct kvm_vcpu *vcpu,
2892 struct kvm_run *kvm_run)
2893{
2894 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 2895 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 2896 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 2897 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 2898 kvm_run->ready_for_interrupt_injection = 1;
4531220b 2899 else
b6c7a5dc 2900 kvm_run->ready_for_interrupt_injection =
ad312c7c
ZX		 2901 (vcpu->arch.interrupt_window_open &&
2902 vcpu->arch.irq_summary == 0);
b6c7a5dc
HB		 2903}
2904
b93463aa
AK		 2905static void vapic_enter(struct kvm_vcpu *vcpu)
2906{
2907 struct kvm_lapic *apic = vcpu->arch.apic;
2908 struct page *page;
2909
2910 if (!apic || !apic->vapic_addr)
2911 return;
2912
2913 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 2914
2915 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 2916}
2917
2918static void vapic_exit(struct kvm_vcpu *vcpu)
2919{
2920 struct kvm_lapic *apic = vcpu->arch.apic;
2921
2922 if (!apic || !apic->vapic_addr)
2923 return;
2924
f8b78fa3 2925 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 2926 kvm_release_page_dirty(apic->vapic_page);
2927 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 2928 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 2929}
2930
d7690175 2931static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
b6c7a5dc
HB		 2932{
2933 int r;
2934
2e53d63a
MT		 2935 if (vcpu->requests)
2936 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
2937 kvm_mmu_unload(vcpu);
2938
b6c7a5dc
HB		 2939 r = kvm_mmu_reload(vcpu);
2940 if (unlikely(r))
2941 goto out;
2942
2f52d58c
AK		 2943 if (vcpu->requests) {
2944 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 2945 __kvm_migrate_timers(vcpu);
4731d4c7
MT		 2946 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
2947 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 2948 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
2949 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 2950 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
2951 &vcpu->requests)) {
2952 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
2953 r = 0;
2954 goto out;
2955 }
71c4dfaf
JR		 2956 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
2957 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2958 r = 0;
2959 goto out;
2960 }
2f52d58c 2961 }
b93463aa 2962
06e05645 2963 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
b6c7a5dc
HB		 2964 kvm_inject_pending_timer_irqs(vcpu);
2965
2966 preempt_disable();
2967
2968 kvm_x86_ops->prepare_guest_switch(vcpu);
2969 kvm_load_guest_fpu(vcpu);
2970
2971 local_irq_disable();
2972
d7690175 2973 if (vcpu->requests || need_resched() || signal_pending(current)) {
6c142801
AK		 2974 local_irq_enable();
2975 preempt_enable();
2976 r = 1;
2977 goto out;
2978 }
2979
29415c37
MT		 2980 if (vcpu->guest_debug.enabled)
2981 kvm_x86_ops->guest_debug_pre(vcpu);
b6c7a5dc 2982
e9571ed5
MT		 2983 vcpu->guest_mode = 1;
2984 /*
2985 * Make sure that guest_mode assignment won't happen after
2986 * testing the pending IRQ vector bitmap.
2987 */
2988 smp_wmb();
2989
ad312c7c 2990 if (vcpu->arch.exception.pending)
298101da
AK		 2991 __queue_exception(vcpu);
2992 else if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 2993 kvm_x86_ops->inject_pending_irq(vcpu);
eb9774f0 2994 else
b6c7a5dc
HB		 2995 kvm_x86_ops->inject_pending_vectors(vcpu, kvm_run);
2996
b93463aa
AK		 2997 kvm_lapic_sync_to_vapic(vcpu);
2998
3200f405
MT		 2999 up_read(&vcpu->kvm->slots_lock);
3000
b6c7a5dc
HB		 3001 kvm_guest_enter();
3002
b6c7a5dc 3003
2714d1d3 3004 KVMTRACE_0D(VMENTRY, vcpu, entryexit);
b6c7a5dc
HB		 3005 kvm_x86_ops->run(vcpu, kvm_run);
3006
3007 vcpu->guest_mode = 0;
3008 local_irq_enable();
3009
3010 ++vcpu->stat.exits;
3011
3012 /*
3013 * We must have an instruction between local_irq_enable() and
3014 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3015 * the interrupt shadow. The stat.exits increment will do nicely.
3016 * But we need to prevent reordering, hence this barrier():
3017 */
3018 barrier();
3019
3020 kvm_guest_exit();
3021
3022 preempt_enable();
3023
3200f405
MT		 3024 down_read(&vcpu->kvm->slots_lock);
3025
b6c7a5dc
HB		 3026 /*
3027 * Profile KVM exit RIPs:
3028 */
3029 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 3030 unsigned long rip = kvm_rip_read(vcpu);
3031 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 3032 }
3033
ad312c7c
ZX		 3034 if (vcpu->arch.exception.pending && kvm_x86_ops->exception_injected(vcpu))
3035 vcpu->arch.exception.pending = false;
298101da 3036
b93463aa
AK		 3037 kvm_lapic_sync_from_vapic(vcpu);
3038
b6c7a5dc 3039 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
d7690175
MT		 3040out:
3041 return r;
3042}
b6c7a5dc 3043
d7690175
MT		 3044static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3045{
3046 int r;
3047
3048 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 3049 pr_debug("vcpu %d received sipi with vector # %x\n",
3050 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 3051 kvm_lapic_reset(vcpu);
5f179287 3052 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 3053 if (r)
3054 return r;
3055 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 3056 }
3057
d7690175
MT		 3058 down_read(&vcpu->kvm->slots_lock);
3059 vapic_enter(vcpu);
3060
3061 r = 1;
3062 while (r > 0) {
af2152f5 3063 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
d7690175
MT		 3064 r = vcpu_enter_guest(vcpu, kvm_run);
3065 else {
3066 up_read(&vcpu->kvm->slots_lock);
3067 kvm_vcpu_block(vcpu);
3068 down_read(&vcpu->kvm->slots_lock);
3069 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
3070 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
3071 vcpu->arch.mp_state =
3072 KVM_MP_STATE_RUNNABLE;
3073 if (vcpu->arch.mp_state != KVM_MP_STATE_RUNNABLE)
3074 r = -EINTR;
3075 }
3076
3077 if (r > 0) {
3078 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
3079 r = -EINTR;
3080 kvm_run->exit_reason = KVM_EXIT_INTR;
3081 ++vcpu->stat.request_irq_exits;
3082 }
3083 if (signal_pending(current)) {
3084 r = -EINTR;
3085 kvm_run->exit_reason = KVM_EXIT_INTR;
3086 ++vcpu->stat.signal_exits;
3087 }
3088 if (need_resched()) {
3089 up_read(&vcpu->kvm->slots_lock);
3090 kvm_resched(vcpu);
3091 down_read(&vcpu->kvm->slots_lock);
3092 }
3093 }
b6c7a5dc
HB		 3094 }
3095
d7690175 3096 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3097 post_kvm_run_save(vcpu, kvm_run);
3098
b93463aa
AK		 3099 vapic_exit(vcpu);
3100
b6c7a5dc
HB		 3101 return r;
3102}
3103
3104int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3105{
3106 int r;
3107 sigset_t sigsaved;
3108
3109 vcpu_load(vcpu);
3110
ac9f6dc0
AK		 3111 if (vcpu->sigset_active)
3112 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
3113
a4535290 3114 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 3115 kvm_vcpu_block(vcpu);
d7690175 3116 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 3117 r = -EAGAIN;
3118 goto out;
b6c7a5dc
HB		 3119 }
3120
b6c7a5dc
HB		 3121 /* re-sync apic's tpr */
3122 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 3123 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 3124
ad312c7c 3125 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 3126 r = complete_pio(vcpu);
3127 if (r)
3128 goto out;
3129 }
3130#if CONFIG_HAS_IOMEM
3131 if (vcpu->mmio_needed) {
3132 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3133 vcpu->mmio_read_completed = 1;
3134 vcpu->mmio_needed = 0;
3200f405
MT		 3135
3136 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc 3137 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 3138 vcpu->arch.mmio_fault_cr2, 0,
3139 EMULTYPE_NO_DECODE);
3200f405 3140 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3141 if (r == EMULATE_DO_MMIO) {
3142 /*
3143 * Read-modify-write. Back to userspace.
3144 */
3145 r = 0;
3146 goto out;
3147 }
3148 }
3149#endif
5fdbf976
MT		 3150 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3151 kvm_register_write(vcpu, VCPU_REGS_RAX,
3152 kvm_run->hypercall.ret);
b6c7a5dc
HB		 3153
3154 r = __vcpu_run(vcpu, kvm_run);
3155
3156out:
3157 if (vcpu->sigset_active)
3158 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3159
3160 vcpu_put(vcpu);
3161 return r;
3162}
3163
3164int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3165{
3166 vcpu_load(vcpu);
3167
5fdbf976
MT		 3168 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3169 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3170 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3171 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3172 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3173 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3174 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3175 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 3176#ifdef CONFIG_X86_64
5fdbf976
MT		 3177 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3178 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3179 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3180 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3181 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3182 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3183 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3184 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 3185#endif
3186
5fdbf976 3187 regs->rip = kvm_rip_read(vcpu);
b6c7a5dc
HB		 3188 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3189
3190 /*
3191 * Don't leak debug flags in case they were set for guest debugging
3192 */
3193 if (vcpu->guest_debug.enabled && vcpu->guest_debug.singlestep)
3194 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3195
3196 vcpu_put(vcpu);
3197
3198 return 0;
3199}
3200
3201int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3202{
3203 vcpu_load(vcpu);
3204
5fdbf976
MT		 3205 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3206 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3207 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3208 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3209 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3210 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3211 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3212 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 3213#ifdef CONFIG_X86_64
5fdbf976
MT		 3214 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3215 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3216 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3217 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3218 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3219 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3220 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3221 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
3222
b6c7a5dc
HB		 3223#endif
3224
5fdbf976 3225 kvm_rip_write(vcpu, regs->rip);
b6c7a5dc
HB		 3226 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3227
b6c7a5dc 3228
b4f14abd
JK		 3229 vcpu->arch.exception.pending = false;
3230
b6c7a5dc
HB		 3231 vcpu_put(vcpu);
3232
3233 return 0;
3234}
3235
3e6e0aab
GT		 3236void kvm_get_segment(struct kvm_vcpu *vcpu,
3237 struct kvm_segment *var, int seg)
b6c7a5dc 3238{
14af3f3c 3239 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 3240}
3241
3242void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3243{
3244 struct kvm_segment cs;
3245
3e6e0aab 3246 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 3247 *db = cs.db;
3248 *l = cs.l;
3249}
3250EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3251
3252int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3253 struct kvm_sregs *sregs)
3254{
3255 struct descriptor_table dt;
3256 int pending_vec;
3257
3258 vcpu_load(vcpu);
3259
3e6e0aab
GT		 3260 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3261 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3262 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3263 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3264 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3265 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3266
3e6e0aab
GT		 3267 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3268 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3269
3270 kvm_x86_ops->get_idt(vcpu, &dt);
3271 sregs->idt.limit = dt.limit;
3272 sregs->idt.base = dt.base;
3273 kvm_x86_ops->get_gdt(vcpu, &dt);
3274 sregs->gdt.limit = dt.limit;
3275 sregs->gdt.base = dt.base;
3276
3277 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3278 sregs->cr0 = vcpu->arch.cr0;
3279 sregs->cr2 = vcpu->arch.cr2;
3280 sregs->cr3 = vcpu->arch.cr3;
3281 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3282 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3283 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3284 sregs->apic_base = kvm_get_apic_base(vcpu);
3285
3286 if (irqchip_in_kernel(vcpu->kvm)) {
3287 memset(sregs->interrupt_bitmap, 0,
3288 sizeof sregs->interrupt_bitmap);
3289 pending_vec = kvm_x86_ops->get_irq(vcpu);
3290 if (pending_vec >= 0)
3291 set_bit(pending_vec,
3292 (unsigned long *)sregs->interrupt_bitmap);
3293 } else
ad312c7c 3294 memcpy(sregs->interrupt_bitmap, vcpu->arch.irq_pending,
b6c7a5dc
HB		 3295 sizeof sregs->interrupt_bitmap);
3296
3297 vcpu_put(vcpu);
3298
3299 return 0;
3300}
3301
62d9f0db
MT		 3302int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3303 struct kvm_mp_state *mp_state)
3304{
3305 vcpu_load(vcpu);
3306 mp_state->mp_state = vcpu->arch.mp_state;
3307 vcpu_put(vcpu);
3308 return 0;
3309}
3310
3311int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3312 struct kvm_mp_state *mp_state)
3313{
3314 vcpu_load(vcpu);
3315 vcpu->arch.mp_state = mp_state->mp_state;
3316 vcpu_put(vcpu);
3317 return 0;
3318}
3319
3e6e0aab 3320static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 3321 struct kvm_segment *var, int seg)
3322{
14af3f3c 3323 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 3324}
3325
37817f29
IE		 3326static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3327 struct kvm_segment *kvm_desct)
3328{
3329 kvm_desct->base = seg_desc->base0;
3330 kvm_desct->base |= seg_desc->base1 << 16;
3331 kvm_desct->base |= seg_desc->base2 << 24;
3332 kvm_desct->limit = seg_desc->limit0;
3333 kvm_desct->limit |= seg_desc->limit << 16;
c93cd3a5
MT		 3334 if (seg_desc->g) {
3335 kvm_desct->limit <<= 12;
3336 kvm_desct->limit |= 0xfff;
3337 }
37817f29
IE		 3338 kvm_desct->selector = selector;
3339 kvm_desct->type = seg_desc->type;
3340 kvm_desct->present = seg_desc->p;
3341 kvm_desct->dpl = seg_desc->dpl;
3342 kvm_desct->db = seg_desc->d;
3343 kvm_desct->s = seg_desc->s;
3344 kvm_desct->l = seg_desc->l;
3345 kvm_desct->g = seg_desc->g;
3346 kvm_desct->avl = seg_desc->avl;
3347 if (!selector)
3348 kvm_desct->unusable = 1;
3349 else
3350 kvm_desct->unusable = 0;
3351 kvm_desct->padding = 0;
3352}
3353
b8222ad2
AS		 3354static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
3355 u16 selector,
3356 struct descriptor_table *dtable)
37817f29
IE		 3357{
3358 if (selector & 1 << 2) {
3359 struct kvm_segment kvm_seg;
3360
3e6e0aab 3361 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 3362
3363 if (kvm_seg.unusable)
3364 dtable->limit = 0;
3365 else
3366 dtable->limit = kvm_seg.limit;
3367 dtable->base = kvm_seg.base;
3368 }
3369 else
3370 kvm_x86_ops->get_gdt(vcpu, dtable);
3371}
3372
3373/* allowed just for 8 bytes segments */
3374static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3375 struct desc_struct *seg_desc)
3376{
98899aa0 3377 gpa_t gpa;
37817f29
IE		 3378 struct descriptor_table dtable;
3379 u16 index = selector >> 3;
3380
b8222ad2 3381 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3382
3383 if (dtable.limit < index * 8 + 7) {
3384 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
3385 return 1;
3386 }
98899aa0
MT		 3387 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3388 gpa += index * 8;
3389 return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3390}
3391
3392/* allowed just for 8 bytes segments */
3393static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3394 struct desc_struct *seg_desc)
3395{
98899aa0 3396 gpa_t gpa;
37817f29
IE		 3397 struct descriptor_table dtable;
3398 u16 index = selector >> 3;
3399
b8222ad2 3400 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3401
3402 if (dtable.limit < index * 8 + 7)
3403 return 1;
98899aa0
MT		 3404 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3405 gpa += index * 8;
3406 return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3407}
3408
3409static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
3410 struct desc_struct *seg_desc)
3411{
3412 u32 base_addr;
3413
3414 base_addr = seg_desc->base0;
3415 base_addr |= (seg_desc->base1 << 16);
3416 base_addr |= (seg_desc->base2 << 24);
3417
98899aa0 3418 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 3419}
3420
37817f29
IE		 3421static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
3422{
3423 struct kvm_segment kvm_seg;
3424
3e6e0aab 3425 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3426 return kvm_seg.selector;
3427}
3428
3429static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
3430 u16 selector,
3431 struct kvm_segment *kvm_seg)
3432{
3433 struct desc_struct seg_desc;
3434
3435 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
3436 return 1;
3437 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
3438 return 0;
3439}
3440
2259e3a7 3441static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 3442{
3443 struct kvm_segment segvar = {
3444 .base = selector << 4,
3445 .limit = 0xffff,
3446 .selector = selector,
3447 .type = 3,
3448 .present = 1,
3449 .dpl = 3,
3450 .db = 0,
3451 .s = 1,
3452 .l = 0,
3453 .g = 0,
3454 .avl = 0,
3455 .unusable = 0,
3456 };
3457 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
3458 return 0;
3459}
3460
3e6e0aab
GT		 3461int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3462 int type_bits, int seg)
37817f29
IE		 3463{
3464 struct kvm_segment kvm_seg;
3465
f4bbd9aa
AK		 3466 if (!(vcpu->arch.cr0 & X86_CR0_PE))
3467 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 3468 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
3469 return 1;
3470 kvm_seg.type |= type_bits;
3471
3472 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
3473 seg != VCPU_SREG_LDTR)
3474 if (!kvm_seg.s)
3475 kvm_seg.unusable = 1;
3476
3e6e0aab 3477 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3478 return 0;
3479}
3480
3481static void save_state_to_tss32(struct kvm_vcpu *vcpu,
3482 struct tss_segment_32 *tss)
3483{
3484 tss->cr3 = vcpu->arch.cr3;
5fdbf976 3485 tss->eip = kvm_rip_read(vcpu);
37817f29 3486 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 3487 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3488 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3489 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3490 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3491 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3492 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3493 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3494 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 3495 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3496 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3497 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3498 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3499 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
3500 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
3501 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3502 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3503}
3504
3505static int load_state_from_tss32(struct kvm_vcpu *vcpu,
3506 struct tss_segment_32 *tss)
3507{
3508 kvm_set_cr3(vcpu, tss->cr3);
3509
5fdbf976 3510 kvm_rip_write(vcpu, tss->eip);
37817f29
IE		 3511 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
3512
5fdbf976
MT		 3513 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
3514 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
3515 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
3516 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
3517 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
3518 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
3519 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
3520 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 3521
3e6e0aab 3522 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 3523 return 1;
3524
3e6e0aab 3525 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 3526 return 1;
3527
3e6e0aab 3528 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 3529 return 1;
3530
3e6e0aab 3531 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 3532 return 1;
3533
3e6e0aab 3534 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 3535 return 1;
3536
3e6e0aab 3537 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 3538 return 1;
3539
3e6e0aab 3540 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 3541 return 1;
3542 return 0;
3543}
3544
3545static void save_state_to_tss16(struct kvm_vcpu *vcpu,
3546 struct tss_segment_16 *tss)
3547{
5fdbf976 3548 tss->ip = kvm_rip_read(vcpu);
37817f29 3549 tss->flag = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 3550 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3551 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3552 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3553 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3554 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3555 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3556 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
3557 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 3558
3559 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3560 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3561 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3562 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3563 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3564 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3565}
3566
3567static int load_state_from_tss16(struct kvm_vcpu *vcpu,
3568 struct tss_segment_16 *tss)
3569{
5fdbf976 3570 kvm_rip_write(vcpu, tss->ip);
37817f29 3571 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 3572 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
3573 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
3574 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
3575 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
3576 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
3577 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
3578 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
3579 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 3580
3e6e0aab 3581 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 3582 return 1;
3583
3e6e0aab 3584 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 3585 return 1;
3586
3e6e0aab 3587 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 3588 return 1;
3589
3e6e0aab 3590 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 3591 return 1;
3592
3e6e0aab 3593 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 3594 return 1;
3595 return 0;
3596}
3597
8b2cf73c 3598static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
34198bf8 3599 u32 old_tss_base,
37817f29
IE		 3600 struct desc_struct *nseg_desc)
3601{
3602 struct tss_segment_16 tss_segment_16;
3603 int ret = 0;
3604
34198bf8
MT		 3605 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
3606 sizeof tss_segment_16))
37817f29
IE		 3607 goto out;
3608
3609 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 3610
34198bf8
MT		 3611 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
3612 sizeof tss_segment_16))
37817f29 3613 goto out;
34198bf8
MT		 3614
3615 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
3616 &tss_segment_16, sizeof tss_segment_16))
3617 goto out;
3618
37817f29
IE		 3619 if (load_state_from_tss16(vcpu, &tss_segment_16))
3620 goto out;
3621
3622 ret = 1;
3623out:
3624 return ret;
3625}
3626
8b2cf73c 3627static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
34198bf8 3628 u32 old_tss_base,
37817f29
IE		 3629 struct desc_struct *nseg_desc)
3630{
3631 struct tss_segment_32 tss_segment_32;
3632 int ret = 0;
3633
34198bf8
MT		 3634 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
3635 sizeof tss_segment_32))
37817f29
IE		 3636 goto out;
3637
3638 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 3639
34198bf8
MT		 3640 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
3641 sizeof tss_segment_32))
3642 goto out;
3643
3644 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
3645 &tss_segment_32, sizeof tss_segment_32))
37817f29 3646 goto out;
34198bf8 3647
37817f29
IE		 3648 if (load_state_from_tss32(vcpu, &tss_segment_32))
3649 goto out;
3650
3651 ret = 1;
3652out:
3653 return ret;
3654}
3655
3656int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
3657{
3658 struct kvm_segment tr_seg;
3659 struct desc_struct cseg_desc;
3660 struct desc_struct nseg_desc;
3661 int ret = 0;
34198bf8
MT		 3662 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
3663 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 3664
34198bf8 3665 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 3666
34198bf8
MT		 3667 /* FIXME: Handle errors. Failure to read either TSS or their
3668 * descriptors should generate a pagefault.
3669 */
37817f29
IE		 3670 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
3671 goto out;
3672
34198bf8 3673 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 3674 goto out;
3675
37817f29
IE		 3676 if (reason != TASK_SWITCH_IRET) {
3677 int cpl;
3678
3679 cpl = kvm_x86_ops->get_cpl(vcpu);
3680 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
3681 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
3682 return 1;
3683 }
3684 }
3685
3686 if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) {
3687 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
3688 return 1;
3689 }
3690
3691 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 3692 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 3693 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 3694 }
3695
3696 if (reason == TASK_SWITCH_IRET) {
3697 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3698 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
3699 }
3700
3701 kvm_x86_ops->skip_emulated_instruction(vcpu);
37817f29
IE		 3702
3703 if (nseg_desc.type & 8)
34198bf8 3704 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_base,
37817f29
IE		 3705 &nseg_desc);
3706 else
34198bf8 3707 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_base,
37817f29
IE		 3708 &nseg_desc);
3709
3710 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
3711 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3712 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
3713 }
3714
3715 if (reason != TASK_SWITCH_IRET) {
3fe913e7 3716 nseg_desc.type |= (1 << 1);
37817f29
IE		 3717 save_guest_segment_descriptor(vcpu, tss_selector,
3718 &nseg_desc);
3719 }
3720
3721 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
3722 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
3723 tr_seg.type = 11;
3e6e0aab 3724 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 3725out:
37817f29
IE		 3726 return ret;
3727}
3728EXPORT_SYMBOL_GPL(kvm_task_switch);
3729
b6c7a5dc
HB		 3730int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
3731 struct kvm_sregs *sregs)
3732{
3733 int mmu_reset_needed = 0;
3734 int i, pending_vec, max_bits;
3735 struct descriptor_table dt;
3736
3737 vcpu_load(vcpu);
3738
3739 dt.limit = sregs->idt.limit;
3740 dt.base = sregs->idt.base;
3741 kvm_x86_ops->set_idt(vcpu, &dt);
3742 dt.limit = sregs->gdt.limit;
3743 dt.base = sregs->gdt.base;
3744 kvm_x86_ops->set_gdt(vcpu, &dt);
3745
ad312c7c
ZX		 3746 vcpu->arch.cr2 = sregs->cr2;
3747 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
3748 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 3749
2d3ad1f4 3750 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 3751
ad312c7c 3752 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 3753 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 3754 kvm_set_apic_base(vcpu, sregs->apic_base);
3755
3756 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3757
ad312c7c 3758 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 3759 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 3760 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 3761
ad312c7c 3762 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 3763 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3764 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 3765 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 3766
3767 if (mmu_reset_needed)
3768 kvm_mmu_reset_context(vcpu);
3769
3770 if (!irqchip_in_kernel(vcpu->kvm)) {
ad312c7c
ZX		 3771 memcpy(vcpu->arch.irq_pending, sregs->interrupt_bitmap,
3772 sizeof vcpu->arch.irq_pending);
3773 vcpu->arch.irq_summary = 0;
3774 for (i = 0; i < ARRAY_SIZE(vcpu->arch.irq_pending); ++i)
3775 if (vcpu->arch.irq_pending[i])
3776 __set_bit(i, &vcpu->arch.irq_summary);
b6c7a5dc
HB		 3777 } else {
3778 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
3779 pending_vec = find_first_bit(
3780 (const unsigned long *)sregs->interrupt_bitmap,
3781 max_bits);
3782 /* Only pending external irq is handled here */
3783 if (pending_vec < max_bits) {
3784 kvm_x86_ops->set_irq(vcpu, pending_vec);
3785 pr_debug("Set back pending irq %d\n",
3786 pending_vec);
3787 }
e4825800 3788 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 3789 }
3790
3e6e0aab
GT		 3791 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3792 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3793 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3794 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3795 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3796 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3797
3e6e0aab
GT		 3798 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3799 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 3800
9c3e4aab
MT		 3801 /* Older userspace won't unhalt the vcpu on reset. */
3802 if (vcpu->vcpu_id == 0 && kvm_rip_read(vcpu) == 0xfff0 &&
3803 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3804 !(vcpu->arch.cr0 & X86_CR0_PE))
3805 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
3806
b6c7a5dc
HB		 3807 vcpu_put(vcpu);
3808
3809 return 0;
3810}
3811
3812int kvm_arch_vcpu_ioctl_debug_guest(struct kvm_vcpu *vcpu,
3813 struct kvm_debug_guest *dbg)
3814{
3815 int r;
3816
3817 vcpu_load(vcpu);
3818
3819 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
3820
3821 vcpu_put(vcpu);
3822
3823 return r;
3824}
3825
d0752060
HB		 3826/*
3827 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
3828 * we have asm/x86/processor.h
3829 */
3830struct fxsave {
3831 u16 cwd;
3832 u16 swd;
3833 u16 twd;
3834 u16 fop;
3835 u64 rip;
3836 u64 rdp;
3837 u32 mxcsr;
3838 u32 mxcsr_mask;
3839 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
3840#ifdef CONFIG_X86_64
3841 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
3842#else
3843 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
3844#endif
3845};
3846
8b006791
ZX		 3847/*
3848 * Translate a guest virtual address to a guest physical address.
3849 */
3850int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
3851 struct kvm_translation *tr)
3852{
3853 unsigned long vaddr = tr->linear_address;
3854 gpa_t gpa;
3855
3856 vcpu_load(vcpu);
72dc67a6 3857 down_read(&vcpu->kvm->slots_lock);
ad312c7c 3858 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 3859 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 3860 tr->physical_address = gpa;
3861 tr->valid = gpa != UNMAPPED_GVA;
3862 tr->writeable = 1;
3863 tr->usermode = 0;
8b006791
ZX		 3864 vcpu_put(vcpu);
3865
3866 return 0;
3867}
3868
d0752060
HB		 3869int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
3870{
ad312c7c 3871 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 3872
3873 vcpu_load(vcpu);
3874
3875 memcpy(fpu->fpr, fxsave->st_space, 128);
3876 fpu->fcw = fxsave->cwd;
3877 fpu->fsw = fxsave->swd;
3878 fpu->ftwx = fxsave->twd;
3879 fpu->last_opcode = fxsave->fop;
3880 fpu->last_ip = fxsave->rip;
3881 fpu->last_dp = fxsave->rdp;
3882 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
3883
3884 vcpu_put(vcpu);
3885
3886 return 0;
3887}
3888
3889int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
3890{
ad312c7c 3891 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 3892
3893 vcpu_load(vcpu);
3894
3895 memcpy(fxsave->st_space, fpu->fpr, 128);
3896 fxsave->cwd = fpu->fcw;
3897 fxsave->swd = fpu->fsw;
3898 fxsave->twd = fpu->ftwx;
3899 fxsave->fop = fpu->last_opcode;
3900 fxsave->rip = fpu->last_ip;
3901 fxsave->rdp = fpu->last_dp;
3902 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
3903
3904 vcpu_put(vcpu);
3905
3906 return 0;
3907}
3908
3909void fx_init(struct kvm_vcpu *vcpu)
3910{
3911 unsigned after_mxcsr_mask;
3912
bc1a34f1
AA		 3913 /*
3914 * Touch the fpu the first time in non atomic context as if
3915 * this is the first fpu instruction the exception handler
3916 * will fire before the instruction returns and it'll have to
3917 * allocate ram with GFP_KERNEL.
3918 */
3919 if (!used_math())
d6e88aec 3920 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 3921
d0752060
HB		 3922 /* Initialize guest FPU by resetting ours and saving into guest's */
3923 preempt_disable();
d6e88aec
AK		 3924 kvm_fx_save(&vcpu->arch.host_fx_image);
3925 kvm_fx_finit();
3926 kvm_fx_save(&vcpu->arch.guest_fx_image);
3927 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 3928 preempt_enable();
3929
ad312c7c 3930 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 3931 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 3932 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
3933 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 3934 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
3935}
3936EXPORT_SYMBOL_GPL(fx_init);
3937
3938void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
3939{
3940 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
3941 return;
3942
3943 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 3944 kvm_fx_save(&vcpu->arch.host_fx_image);
3945 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 3946}
3947EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
3948
3949void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
3950{
3951 if (!vcpu->guest_fpu_loaded)
3952 return;
3953
3954 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 3955 kvm_fx_save(&vcpu->arch.guest_fx_image);
3956 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 3957 ++vcpu->stat.fpu_reload;
d0752060
HB		 3958}
3959EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 3960
3961void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
3962{
3963 kvm_x86_ops->vcpu_free(vcpu);
3964}
3965
3966struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
3967 unsigned int id)
3968{
26e5215f
AK		 3969 return kvm_x86_ops->vcpu_create(kvm, id);
3970}
e9b11c17 3971
26e5215f
AK		 3972int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
3973{
3974 int r;
e9b11c17
ZX		 3975
3976 /* We do fxsave: this must be aligned. */
ad312c7c 3977 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 3978
0bed3b56 3979 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 3980 vcpu_load(vcpu);
3981 r = kvm_arch_vcpu_reset(vcpu);
3982 if (r == 0)
3983 r = kvm_mmu_setup(vcpu);
3984 vcpu_put(vcpu);
3985 if (r < 0)
3986 goto free_vcpu;
3987
26e5215f 3988 return 0;
e9b11c17
ZX		 3989free_vcpu:
3990 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 3991 return r;
e9b11c17
ZX		 3992}
3993
d40ccc62 3994void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 3995{
3996 vcpu_load(vcpu);
3997 kvm_mmu_unload(vcpu);
3998 vcpu_put(vcpu);
3999
4000 kvm_x86_ops->vcpu_free(vcpu);
4001}
4002
4003int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4004{
448fa4a9
JK		 4005 vcpu->arch.nmi_pending = false;
4006 vcpu->arch.nmi_injected = false;
4007
e9b11c17
ZX		 4008 return kvm_x86_ops->vcpu_reset(vcpu);
4009}
4010
4011void kvm_arch_hardware_enable(void *garbage)
4012{
4013 kvm_x86_ops->hardware_enable(garbage);
4014}
4015
4016void kvm_arch_hardware_disable(void *garbage)
4017{
4018 kvm_x86_ops->hardware_disable(garbage);
4019}
4020
4021int kvm_arch_hardware_setup(void)
4022{
4023 return kvm_x86_ops->hardware_setup();
4024}
4025
4026void kvm_arch_hardware_unsetup(void)
4027{
4028 kvm_x86_ops->hardware_unsetup();
4029}
4030
4031void kvm_arch_check_processor_compat(void *rtn)
4032{
4033 kvm_x86_ops->check_processor_compatibility(rtn);
4034}
4035
4036int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
4037{
4038 struct page *page;
4039 struct kvm *kvm;
4040 int r;
4041
4042 BUG_ON(vcpu->kvm == NULL);
4043 kvm = vcpu->kvm;
4044
ad312c7c 4045 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
e9b11c17 4046 if (!irqchip_in_kernel(kvm) || vcpu->vcpu_id == 0)
a4535290 4047 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 4048 else
a4535290 4049 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 4050
4051 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
4052 if (!page) {
4053 r = -ENOMEM;
4054 goto fail;
4055 }
ad312c7c 4056 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 4057
4058 r = kvm_mmu_create(vcpu);
4059 if (r < 0)
4060 goto fail_free_pio_data;
4061
4062 if (irqchip_in_kernel(kvm)) {
4063 r = kvm_create_lapic(vcpu);
4064 if (r < 0)
4065 goto fail_mmu_destroy;
4066 }
4067
4068 return 0;
4069
4070fail_mmu_destroy:
4071 kvm_mmu_destroy(vcpu);
4072fail_free_pio_data:
ad312c7c 4073 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 4074fail:
4075 return r;
4076}
4077
4078void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
4079{
4080 kvm_free_lapic(vcpu);
3200f405 4081 down_read(&vcpu->kvm->slots_lock);
e9b11c17 4082 kvm_mmu_destroy(vcpu);
3200f405 4083 up_read(&vcpu->kvm->slots_lock);
ad312c7c 4084 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 4085}
d19a9cd2
ZX		 4086
4087struct kvm *kvm_arch_create_vm(void)
4088{
4089 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
4090
4091 if (!kvm)
4092 return ERR_PTR(-ENOMEM);
4093
f05e70ac 4094 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
6cffe8ca 4095 INIT_LIST_HEAD(&kvm->arch.oos_global_pages);
4d5c5d0f 4096 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 4097
5550af4d
SY		 4098 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
4099 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
4100
d19a9cd2
ZX		 4101 return kvm;
4102}
4103
4104static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
4105{
4106 vcpu_load(vcpu);
4107 kvm_mmu_unload(vcpu);
4108 vcpu_put(vcpu);
4109}
4110
4111static void kvm_free_vcpus(struct kvm *kvm)
4112{
4113 unsigned int i;
4114
4115 /*
4116 * Unpin any mmu pages first.
4117 */
4118 for (i = 0; i < KVM_MAX_VCPUS; ++i)
4119 if (kvm->vcpus[i])
4120 kvm_unload_vcpu_mmu(kvm->vcpus[i]);
4121 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
4122 if (kvm->vcpus[i]) {
4123 kvm_arch_vcpu_free(kvm->vcpus[i]);
4124 kvm->vcpus[i] = NULL;
4125 }
4126 }
4127
4128}
4129
ad8ba2cd
SY		 4130void kvm_arch_sync_events(struct kvm *kvm)
4131{
4132}
4133
d19a9cd2
ZX		 4134void kvm_arch_destroy_vm(struct kvm *kvm)
4135{
bfadaded 4136 kvm_free_all_assigned_devices(kvm);
6eb55818 4137 kvm_iommu_unmap_guest(kvm);
7837699f 4138 kvm_free_pit(kvm);
d7deeeb0
ZX		 4139 kfree(kvm->arch.vpic);
4140 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 4141 kvm_free_vcpus(kvm);
4142 kvm_free_physmem(kvm);
3d45830c
AK		 4143 if (kvm->arch.apic_access_page)
4144 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 4145 if (kvm->arch.ept_identity_pagetable)
4146 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 4147 kfree(kvm);
4148}
0de10343
ZX		 4149
4150int kvm_arch_set_memory_region(struct kvm *kvm,
4151 struct kvm_userspace_memory_region *mem,
4152 struct kvm_memory_slot old,
4153 int user_alloc)
4154{
4155 int npages = mem->memory_size >> PAGE_SHIFT;
4156 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
4157
4158 /*To keep backward compatibility with older userspace,
4159 *x86 needs to hanlde !user_alloc case.
4160 */
4161 if (!user_alloc) {
4162 if (npages && !old.rmap) {
604b38ac
AA		 4163 unsigned long userspace_addr;
4164
72dc67a6 4165 down_write(&current->mm->mmap_sem);
604b38ac
AA		 4166 userspace_addr = do_mmap(NULL, 0,
4167 npages * PAGE_SIZE,
4168 PROT_READ | PROT_WRITE,
acee3c04 4169 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 4170 0);
72dc67a6 4171 up_write(&current->mm->mmap_sem);
0de10343 4172
604b38ac
AA		 4173 if (IS_ERR((void *)userspace_addr))
4174 return PTR_ERR((void *)userspace_addr);
4175
4176 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4177 spin_lock(&kvm->mmu_lock);
4178 memslot->userspace_addr = userspace_addr;
4179 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4180 } else {
4181 if (!old.user_alloc && old.rmap) {
4182 int ret;
4183
72dc67a6 4184 down_write(&current->mm->mmap_sem);
0de10343
ZX		 4185 ret = do_munmap(current->mm, old.userspace_addr,
4186 old.npages * PAGE_SIZE);
72dc67a6 4187 up_write(&current->mm->mmap_sem);
0de10343
ZX		 4188 if (ret < 0)
4189 printk(KERN_WARNING
4190 "kvm_vm_ioctl_set_memory_region: "
4191 "failed to munmap memory\n");
4192 }
4193 }
4194 }
4195
f05e70ac 4196 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 4197 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4198 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4199 }
4200
4201 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
4202 kvm_flush_remote_tlbs(kvm);
4203
4204 return 0;
4205}
1d737c8a 4206
34d4cb8f
MT		 4207void kvm_arch_flush_shadow(struct kvm *kvm)
4208{
4209 kvm_mmu_zap_all(kvm);
4210}
4211
1d737c8a
ZX		 4212int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4213{
a4535290 4214 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
0496fbb9
JK		 4215 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
4216 || vcpu->arch.nmi_pending;
1d737c8a 4217}
5736199a
ZX		 4218
4219static void vcpu_kick_intr(void *info)
4220{
4221#ifdef DEBUG
4222 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)info;
4223 printk(KERN_DEBUG "vcpu_kick_intr %p \n", vcpu);
4224#endif
4225}
4226
4227void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4228{
4229 int ipi_pcpu = vcpu->cpu;
e9571ed5 4230 int cpu = get_cpu();
5736199a
ZX		 4231
4232 if (waitqueue_active(&vcpu->wq)) {
4233 wake_up_interruptible(&vcpu->wq);
4234 ++vcpu->stat.halt_wakeup;
4235 }
e9571ed5
MT		 4236 /*
4237 * We may be called synchronously with irqs disabled in guest mode,
4238 * So need not to call smp_call_function_single() in that case.
4239 */
4240 if (vcpu->guest_mode && vcpu->cpu != cpu)
8691e5a8 4241 smp_call_function_single(ipi_pcpu, vcpu_kick_intr, vcpu, 0);
e9571ed5 4242 put_cpu();
5736199a 4243}
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