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KVM: async_pf: Force a nested vmexit if the injected #PF is async_pf
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad
IM		 56#include <linux/sched/stat.h>
57
aec51dc4 58#include <trace/events/kvm.h>
2ed152af 59
24f1e32c 60#include <asm/debugreg.h>
d825ed0a 61#include <asm/msr.h>
a5f61300 62#include <asm/desc.h>
890ca9ae 63#include <asm/mce.h>
f89e32e0 64#include <linux/kernel_stat.h>
78f7f1e5 65#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 66#include <asm/pvclock.h>
217fc9cf 67#include <asm/div64.h>
efc64404 68#include <asm/irq_remapping.h>
043405e1 69
d1898b73
DH		 70#define CREATE_TRACE_POINTS
71#include "trace.h"
72
313a3dc7 73#define MAX_IO_MSRS 256
890ca9ae 74#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 75u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
76EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 77
0f65dd70
AK		 78#define emul_to_vcpu(ctxt) \
79 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
80
50a37eb4
JR		 81/* EFER defaults:
82 * - enable syscall per default because its emulated by KVM
83 * - enable LME and LMA per default on 64 bit KVM
84 */
85#ifdef CONFIG_X86_64
1260edbe
LJ		 86static
87u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 88#else
1260edbe 89static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 90#endif
313a3dc7 91
ba1389b7
AK		 92#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
93#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 94
c519265f
RK		 95#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
96 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 97
cb142eb7 98static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 99static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 100static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 101static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 102
893590c7 103struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 104EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 105
893590c7 106static bool __read_mostly ignore_msrs = 0;
476bc001 107module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 108
9ed96e87
MT		 109unsigned int min_timer_period_us = 500;
110module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
111
630994b3
MT		 112static bool __read_mostly kvmclock_periodic_sync = true;
113module_param(kvmclock_periodic_sync, bool, S_IRUGO);
114
893590c7 115bool __read_mostly kvm_has_tsc_control;
92a1f12d 116EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 117u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 118EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 119u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
120EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
121u64 __read_mostly kvm_max_tsc_scaling_ratio;
122EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 123u64 __read_mostly kvm_default_tsc_scaling_ratio;
124EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 125
cc578287 126/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 127static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 128module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
129
d0659d94 130/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 131unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 132module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
133
52004014
FW		 134static bool __read_mostly vector_hashing = true;
135module_param(vector_hashing, bool, S_IRUGO);
136
18863bdd
AK		 137#define KVM_NR_SHARED_MSRS 16
138
139struct kvm_shared_msrs_global {
140 int nr;
2bf78fa7 141 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 142};
143
144struct kvm_shared_msrs {
145 struct user_return_notifier urn;
146 bool registered;
2bf78fa7
SY		 147 struct kvm_shared_msr_values {
148 u64 host;
149 u64 curr;
150 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 151};
152
153static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 154static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 155
417bc304 156struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 157 { "pf_fixed", VCPU_STAT(pf_fixed) },
158 { "pf_guest", VCPU_STAT(pf_guest) },
159 { "tlb_flush", VCPU_STAT(tlb_flush) },
160 { "invlpg", VCPU_STAT(invlpg) },
161 { "exits", VCPU_STAT(exits) },
162 { "io_exits", VCPU_STAT(io_exits) },
163 { "mmio_exits", VCPU_STAT(mmio_exits) },
164 { "signal_exits", VCPU_STAT(signal_exits) },
165 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 166 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 167 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 168 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 169 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 170 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 171 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 172 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 173 { "request_irq", VCPU_STAT(request_irq_exits) },
174 { "irq_exits", VCPU_STAT(irq_exits) },
175 { "host_state_reload", VCPU_STAT(host_state_reload) },
176 { "efer_reload", VCPU_STAT(efer_reload) },
177 { "fpu_reload", VCPU_STAT(fpu_reload) },
178 { "insn_emulation", VCPU_STAT(insn_emulation) },
179 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 180 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 181 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 182 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 183 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
184 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
185 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
186 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
187 { "mmu_flooded", VM_STAT(mmu_flooded) },
188 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 189 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 190 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 191 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 192 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 193 { "max_mmu_page_hash_collisions",
194 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 195 { NULL }
196};
197
2acf923e
DC		 198u64 __read_mostly host_xcr0;
199
b6785def 200static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 201
af585b92
GN		 202static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
203{
204 int i;
205 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
206 vcpu->arch.apf.gfns[i] = ~0;
207}
208
18863bdd
AK		 209static void kvm_on_user_return(struct user_return_notifier *urn)
210{
211 unsigned slot;
18863bdd
AK		 212 struct kvm_shared_msrs *locals
213 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 214 struct kvm_shared_msr_values *values;
1650b4eb
IA		 215 unsigned long flags;
216
217 /*
218 * Disabling irqs at this point since the following code could be
219 * interrupted and executed through kvm_arch_hardware_disable()
220 */
221 local_irq_save(flags);
222 if (locals->registered) {
223 locals->registered = false;
224 user_return_notifier_unregister(urn);
225 }
226 local_irq_restore(flags);
18863bdd 227 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 228 values = &locals->values[slot];
229 if (values->host != values->curr) {
230 wrmsrl(shared_msrs_global.msrs[slot], values->host);
231 values->curr = values->host;
18863bdd
AK		 232 }
233 }
18863bdd
AK		 234}
235
2bf78fa7 236static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 237{
18863bdd 238 u64 value;
013f6a5d
MT		 239 unsigned int cpu = smp_processor_id();
240 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 241
2bf78fa7
SY		 242 /* only read, and nobody should modify it at this time,
243 * so don't need lock */
244 if (slot >= shared_msrs_global.nr) {
245 printk(KERN_ERR "kvm: invalid MSR slot!");
246 return;
247 }
248 rdmsrl_safe(msr, &value);
249 smsr->values[slot].host = value;
250 smsr->values[slot].curr = value;
251}
252
253void kvm_define_shared_msr(unsigned slot, u32 msr)
254{
0123be42 255 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 256 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 257 if (slot >= shared_msrs_global.nr)
258 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 259}
260EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
261
262static void kvm_shared_msr_cpu_online(void)
263{
264 unsigned i;
18863bdd
AK		 265
266 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 267 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 268}
269
8b3c3104 270int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 271{
013f6a5d
MT		 272 unsigned int cpu = smp_processor_id();
273 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 274 int err;
18863bdd 275
2bf78fa7 276 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 277 return 0;
2bf78fa7 278 smsr->values[slot].curr = value;
8b3c3104
AH		 279 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
280 if (err)
281 return 1;
282
18863bdd
AK		 283 if (!smsr->registered) {
284 smsr->urn.on_user_return = kvm_on_user_return;
285 user_return_notifier_register(&smsr->urn);
286 smsr->registered = true;
287 }
8b3c3104 288 return 0;
18863bdd
AK		 289}
290EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
291
13a34e06 292static void drop_user_return_notifiers(void)
3548bab5 293{
013f6a5d
MT		 294 unsigned int cpu = smp_processor_id();
295 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 296
297 if (smsr->registered)
298 kvm_on_user_return(&smsr->urn);
299}
300
6866b83e
CO		 301u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
302{
8a5a87d9 303 return vcpu->arch.apic_base;
6866b83e
CO		 304}
305EXPORT_SYMBOL_GPL(kvm_get_apic_base);
306
58cb628d
JK		 307int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
308{
309 u64 old_state = vcpu->arch.apic_base &
310 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
311 u64 new_state = msr_info->data &
312 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
313 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
314 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
315
316 if (!msr_info->host_initiated &&
317 ((msr_info->data & reserved_bits) != 0 ||
318 new_state == X2APIC_ENABLE ||
319 (new_state == MSR_IA32_APICBASE_ENABLE &&
320 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
321 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
322 old_state == 0)))
323 return 1;
324
325 kvm_lapic_set_base(vcpu, msr_info->data);
326 return 0;
6866b83e
CO		 327}
328EXPORT_SYMBOL_GPL(kvm_set_apic_base);
329
2605fc21 330asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 331{
332 /* Fault while not rebooting. We want the trace. */
333 BUG();
334}
335EXPORT_SYMBOL_GPL(kvm_spurious_fault);
336
3fd28fce
ED		 337#define EXCPT_BENIGN 0
338#define EXCPT_CONTRIBUTORY 1
339#define EXCPT_PF 2
340
341static int exception_class(int vector)
342{
343 switch (vector) {
344 case PF_VECTOR:
345 return EXCPT_PF;
346 case DE_VECTOR:
347 case TS_VECTOR:
348 case NP_VECTOR:
349 case SS_VECTOR:
350 case GP_VECTOR:
351 return EXCPT_CONTRIBUTORY;
352 default:
353 break;
354 }
355 return EXCPT_BENIGN;
356}
357
d6e8c854
NA		 358#define EXCPT_FAULT 0
359#define EXCPT_TRAP 1
360#define EXCPT_ABORT 2
361#define EXCPT_INTERRUPT 3
362
363static int exception_type(int vector)
364{
365 unsigned int mask;
366
367 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
368 return EXCPT_INTERRUPT;
369
370 mask = 1 << vector;
371
372 /* #DB is trap, as instruction watchpoints are handled elsewhere */
373 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
374 return EXCPT_TRAP;
375
376 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
377 return EXCPT_ABORT;
378
379 /* Reserved exceptions will result in fault */
380 return EXCPT_FAULT;
381}
382
3fd28fce 383static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 384 unsigned nr, bool has_error, u32 error_code,
385 bool reinject)
3fd28fce
ED		 386{
387 u32 prev_nr;
388 int class1, class2;
389
3842d135
AK		 390 kvm_make_request(KVM_REQ_EVENT, vcpu);
391
3fd28fce
ED		 392 if (!vcpu->arch.exception.pending) {
393 queue:
3ffb2468
NA		 394 if (has_error && !is_protmode(vcpu))
395 has_error = false;
3fd28fce
ED		 396 vcpu->arch.exception.pending = true;
397 vcpu->arch.exception.has_error_code = has_error;
398 vcpu->arch.exception.nr = nr;
399 vcpu->arch.exception.error_code = error_code;
3f0fd292 400 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 401 return;
402 }
403
404 /* to check exception */
405 prev_nr = vcpu->arch.exception.nr;
406 if (prev_nr == DF_VECTOR) {
407 /* triple fault -> shutdown */
a8eeb04a 408 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 409 return;
410 }
411 class1 = exception_class(prev_nr);
412 class2 = exception_class(nr);
413 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
414 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
415 /* generate double fault per SDM Table 5-5 */
416 vcpu->arch.exception.pending = true;
417 vcpu->arch.exception.has_error_code = true;
418 vcpu->arch.exception.nr = DF_VECTOR;
419 vcpu->arch.exception.error_code = 0;
420 } else
421 /* replace previous exception with a new one in a hope
422 that instruction re-execution will regenerate lost
423 exception */
424 goto queue;
425}
426
298101da
AK		 427void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
428{
ce7ddec4 429 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 430}
431EXPORT_SYMBOL_GPL(kvm_queue_exception);
432
ce7ddec4
JR		 433void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
434{
435 kvm_multiple_exception(vcpu, nr, false, 0, true);
436}
437EXPORT_SYMBOL_GPL(kvm_requeue_exception);
438
6affcbed 439int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 440{
db8fcefa
AP		 441 if (err)
442 kvm_inject_gp(vcpu, 0);
443 else
6affcbed
KH		 444 return kvm_skip_emulated_instruction(vcpu);
445
446 return 1;
db8fcefa
AP		 447}
448EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 449
6389ee94 450void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 451{
452 ++vcpu->stat.pf_guest;
adfe20fb
WL		 453 vcpu->arch.exception.nested_apf =
454 is_guest_mode(vcpu) && fault->async_page_fault;
455 if (vcpu->arch.exception.nested_apf)
456 vcpu->arch.apf.nested_apf_token = fault->address;
457 else
458 vcpu->arch.cr2 = fault->address;
6389ee94 459 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 460}
27d6c865 461EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 462
ef54bcfe 463static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 464{
6389ee94
AK		 465 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
466 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 467 else
6389ee94 468 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 469
470 return fault->nested_page_fault;
d4f8cf66
JR		 471}
472
3419ffc8
SY		 473void kvm_inject_nmi(struct kvm_vcpu *vcpu)
474{
7460fb4a
AK		 475 atomic_inc(&vcpu->arch.nmi_queued);
476 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 477}
478EXPORT_SYMBOL_GPL(kvm_inject_nmi);
479
298101da
AK		 480void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
481{
ce7ddec4 482 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 483}
484EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
485
ce7ddec4
JR		 486void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
487{
488 kvm_multiple_exception(vcpu, nr, true, error_code, true);
489}
490EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
491
0a79b009
AK		 492/*
493 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
494 * a #GP and return false.
495 */
496bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 497{
0a79b009
AK		 498 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
499 return true;
500 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
501 return false;
298101da 502}
0a79b009 503EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 504
16f8a6f9
NA		 505bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
506{
507 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
508 return true;
509
510 kvm_queue_exception(vcpu, UD_VECTOR);
511 return false;
512}
513EXPORT_SYMBOL_GPL(kvm_require_dr);
514
ec92fe44
JR		 515/*
516 * This function will be used to read from the physical memory of the currently
54bf36aa 517 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 518 * can read from guest physical or from the guest's guest physical memory.
519 */
520int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
521 gfn_t ngfn, void *data, int offset, int len,
522 u32 access)
523{
54987b7a 524 struct x86_exception exception;
ec92fe44
JR		 525 gfn_t real_gfn;
526 gpa_t ngpa;
527
528 ngpa = gfn_to_gpa(ngfn);
54987b7a 529 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 530 if (real_gfn == UNMAPPED_GVA)
531 return -EFAULT;
532
533 real_gfn = gpa_to_gfn(real_gfn);
534
54bf36aa 535 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 536}
537EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
538
69b0049a 539static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 540 void *data, int offset, int len, u32 access)
541{
542 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
543 data, offset, len, access);
544}
545
a03490ed
CO		 546/*
547 * Load the pae pdptrs. Return true is they are all valid.
548 */
ff03a073 549int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 550{
551 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
552 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
553 int i;
554 int ret;
ff03a073 555 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 556
ff03a073
JR		 557 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
558 offset * sizeof(u64), sizeof(pdpte),
559 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 560 if (ret < 0) {
561 ret = 0;
562 goto out;
563 }
564 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 565 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 566 (pdpte[i] &
567 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 568 ret = 0;
569 goto out;
570 }
571 }
572 ret = 1;
573
ff03a073 574 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 575 __set_bit(VCPU_EXREG_PDPTR,
576 (unsigned long *)&vcpu->arch.regs_avail);
577 __set_bit(VCPU_EXREG_PDPTR,
578 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 579out:
a03490ed
CO		 580
581 return ret;
582}
cc4b6871 583EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 584
9ed38ffa 585bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 586{
ff03a073 587 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 588 bool changed = true;
3d06b8bf
JR		 589 int offset;
590 gfn_t gfn;
d835dfec
AK		 591 int r;
592
593 if (is_long_mode(vcpu) || !is_pae(vcpu))
594 return false;
595
6de4f3ad
AK		 596 if (!test_bit(VCPU_EXREG_PDPTR,
597 (unsigned long *)&vcpu->arch.regs_avail))
598 return true;
599
9f8fe504
AK		 600 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
601 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 602 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
603 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 604 if (r < 0)
605 goto out;
ff03a073 606 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 607out:
d835dfec
AK		 608
609 return changed;
610}
9ed38ffa 611EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 612
49a9b07e 613int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 614{
aad82703 615 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 616 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 617
f9a48e6a
AK		 618 cr0 |= X86_CR0_ET;
619
ab344828 620#ifdef CONFIG_X86_64
0f12244f
GN		 621 if (cr0 & 0xffffffff00000000UL)
622 return 1;
ab344828
GN		 623#endif
624
625 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 626
0f12244f
GN		 627 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
628 return 1;
a03490ed 629
0f12244f
GN		 630 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
631 return 1;
a03490ed
CO		 632
633 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
634#ifdef CONFIG_X86_64
f6801dff 635 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 636 int cs_db, cs_l;
637
0f12244f
GN		 638 if (!is_pae(vcpu))
639 return 1;
a03490ed 640 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 641 if (cs_l)
642 return 1;
a03490ed
CO		 643 } else
644#endif
ff03a073 645 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 646 kvm_read_cr3(vcpu)))
0f12244f 647 return 1;
a03490ed
CO		 648 }
649
ad756a16
MJ		 650 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
651 return 1;
652
a03490ed 653 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 654
d170c419 655 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 656 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 657 kvm_async_pf_hash_reset(vcpu);
658 }
e5f3f027 659
aad82703
SY		 660 if ((cr0 ^ old_cr0) & update_bits)
661 kvm_mmu_reset_context(vcpu);
b18d5431 662
879ae188
LE		 663 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
664 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
665 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 666 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
667
0f12244f
GN		 668 return 0;
669}
2d3ad1f4 670EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 671
2d3ad1f4 672void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 673{
49a9b07e 674 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 675}
2d3ad1f4 676EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 677
42bdf991
MT		 678static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
679{
680 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
681 !vcpu->guest_xcr0_loaded) {
682 /* kvm_set_xcr() also depends on this */
683 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
684 vcpu->guest_xcr0_loaded = 1;
685 }
686}
687
688static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
689{
690 if (vcpu->guest_xcr0_loaded) {
691 if (vcpu->arch.xcr0 != host_xcr0)
692 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
693 vcpu->guest_xcr0_loaded = 0;
694 }
695}
696
69b0049a 697static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 698{
56c103ec
LJ		 699 u64 xcr0 = xcr;
700 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 701 u64 valid_bits;
2acf923e
DC		 702
703 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
704 if (index != XCR_XFEATURE_ENABLED_MASK)
705 return 1;
d91cab78 706 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 707 return 1;
d91cab78 708 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 709 return 1;
46c34cb0
PB		 710
711 /*
712 * Do not allow the guest to set bits that we do not support
713 * saving. However, xcr0 bit 0 is always set, even if the
714 * emulated CPU does not support XSAVE (see fx_init).
715 */
d91cab78 716 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 717 if (xcr0 & ~valid_bits)
2acf923e 718 return 1;
46c34cb0 719
d91cab78
DH		 720 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
721 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 722 return 1;
723
d91cab78
DH		 724 if (xcr0 & XFEATURE_MASK_AVX512) {
725 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 726 return 1;
d91cab78 727 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 728 return 1;
729 }
2acf923e 730 vcpu->arch.xcr0 = xcr0;
56c103ec 731
d91cab78 732 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 733 kvm_update_cpuid(vcpu);
2acf923e
DC		 734 return 0;
735}
736
737int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
738{
764bcbc5
Z		 739 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
740 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 741 kvm_inject_gp(vcpu, 0);
742 return 1;
743 }
744 return 0;
745}
746EXPORT_SYMBOL_GPL(kvm_set_xcr);
747
a83b29c6 748int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 749{
fc78f519 750 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 751 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 752 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 753
0f12244f
GN		 754 if (cr4 & CR4_RESERVED_BITS)
755 return 1;
a03490ed 756
2acf923e
DC		 757 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
758 return 1;
759
c68b734f
YW		 760 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
761 return 1;
762
97ec8c06
FW		 763 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
764 return 1;
765
afcbf13f 766 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 767 return 1;
768
b9baba86
HH		 769 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
770 return 1;
771
a03490ed 772 if (is_long_mode(vcpu)) {
0f12244f
GN		 773 if (!(cr4 & X86_CR4_PAE))
774 return 1;
a2edf57f
AK		 775 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
776 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 777 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
778 kvm_read_cr3(vcpu)))
0f12244f
GN		 779 return 1;
780
ad756a16
MJ		 781 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
782 if (!guest_cpuid_has_pcid(vcpu))
783 return 1;
784
785 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
786 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
787 return 1;
788 }
789
5e1746d6 790 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 791 return 1;
a03490ed 792
ad756a16
MJ		 793 if (((cr4 ^ old_cr4) & pdptr_bits) ||
794 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 795 kvm_mmu_reset_context(vcpu);
0f12244f 796
b9baba86 797 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 798 kvm_update_cpuid(vcpu);
2acf923e 799
0f12244f
GN		 800 return 0;
801}
2d3ad1f4 802EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 803
2390218b 804int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 805{
ac146235 806#ifdef CONFIG_X86_64
9d88fca7 807 cr3 &= ~CR3_PCID_INVD;
ac146235 808#endif
9d88fca7 809
9f8fe504 810 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 811 kvm_mmu_sync_roots(vcpu);
77c3913b 812 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 813 return 0;
d835dfec
AK		 814 }
815
a03490ed 816 if (is_long_mode(vcpu)) {
d9f89b88
JK		 817 if (cr3 & CR3_L_MODE_RESERVED_BITS)
818 return 1;
819 } else if (is_pae(vcpu) && is_paging(vcpu) &&
820 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 821 return 1;
a03490ed 822
0f12244f 823 vcpu->arch.cr3 = cr3;
aff48baa 824 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 825 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 826 return 0;
827}
2d3ad1f4 828EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 829
eea1cff9 830int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 831{
0f12244f
GN		 832 if (cr8 & CR8_RESERVED_BITS)
833 return 1;
35754c98 834 if (lapic_in_kernel(vcpu))
a03490ed
CO		 835 kvm_lapic_set_tpr(vcpu, cr8);
836 else
ad312c7c 837 vcpu->arch.cr8 = cr8;
0f12244f
GN		 838 return 0;
839}
2d3ad1f4 840EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 841
2d3ad1f4 842unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 843{
35754c98 844 if (lapic_in_kernel(vcpu))
a03490ed
CO		 845 return kvm_lapic_get_cr8(vcpu);
846 else
ad312c7c 847 return vcpu->arch.cr8;
a03490ed 848}
2d3ad1f4 849EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 850
ae561ede
NA		 851static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
852{
853 int i;
854
855 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
856 for (i = 0; i < KVM_NR_DB_REGS; i++)
857 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
858 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
859 }
860}
861
73aaf249
JK		 862static void kvm_update_dr6(struct kvm_vcpu *vcpu)
863{
864 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
865 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
866}
867
c8639010
JK		 868static void kvm_update_dr7(struct kvm_vcpu *vcpu)
869{
870 unsigned long dr7;
871
872 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
873 dr7 = vcpu->arch.guest_debug_dr7;
874 else
875 dr7 = vcpu->arch.dr7;
876 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 877 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
878 if (dr7 & DR7_BP_EN_MASK)
879 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 880}
881
6f43ed01
NA		 882static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
883{
884 u64 fixed = DR6_FIXED_1;
885
886 if (!guest_cpuid_has_rtm(vcpu))
887 fixed |= DR6_RTM;
888 return fixed;
889}
890
338dbc97 891static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 892{
893 switch (dr) {
894 case 0 ... 3:
895 vcpu->arch.db[dr] = val;
896 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
897 vcpu->arch.eff_db[dr] = val;
898 break;
899 case 4:
020df079
GN		 900 /* fall through */
901 case 6:
338dbc97
GN		 902 if (val & 0xffffffff00000000ULL)
903 return -1; /* #GP */
6f43ed01 904 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 905 kvm_update_dr6(vcpu);
020df079
GN		 906 break;
907 case 5:
020df079
GN		 908 /* fall through */
909 default: /* 7 */
338dbc97
GN		 910 if (val & 0xffffffff00000000ULL)
911 return -1; /* #GP */
020df079 912 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 913 kvm_update_dr7(vcpu);
020df079
GN		 914 break;
915 }
916
917 return 0;
918}
338dbc97
GN		 919
920int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
921{
16f8a6f9 922 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 923 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 924 return 1;
925 }
926 return 0;
338dbc97 927}
020df079
GN		 928EXPORT_SYMBOL_GPL(kvm_set_dr);
929
16f8a6f9 930int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 931{
932 switch (dr) {
933 case 0 ... 3:
934 *val = vcpu->arch.db[dr];
935 break;
936 case 4:
020df079
GN		 937 /* fall through */
938 case 6:
73aaf249
JK		 939 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
940 *val = vcpu->arch.dr6;
941 else
942 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 943 break;
944 case 5:
020df079
GN		 945 /* fall through */
946 default: /* 7 */
947 *val = vcpu->arch.dr7;
948 break;
949 }
338dbc97
GN		 950 return 0;
951}
020df079
GN		 952EXPORT_SYMBOL_GPL(kvm_get_dr);
953
022cd0e8
AK		 954bool kvm_rdpmc(struct kvm_vcpu *vcpu)
955{
956 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
957 u64 data;
958 int err;
959
c6702c9d 960 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 961 if (err)
962 return err;
963 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
964 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
965 return err;
966}
967EXPORT_SYMBOL_GPL(kvm_rdpmc);
968
043405e1
CO		 969/*
970 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
971 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
972 *
973 * This list is modified at module load time to reflect the
e3267cbb 974 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 975 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
976 * may depend on host virtualization features rather than host cpu features.
043405e1 977 */
e3267cbb 978
043405e1
CO		 979static u32 msrs_to_save[] = {
980 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 981 MSR_STAR,
043405e1
CO		 982#ifdef CONFIG_X86_64
983 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
984#endif
b3897a49 985 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 986 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 987};
988
989static unsigned num_msrs_to_save;
990
62ef68bb
PB		 991static u32 emulated_msrs[] = {
992 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
993 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
994 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
995 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 996 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
997 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 998 HV_X64_MSR_RESET,
11c4b1ca 999 HV_X64_MSR_VP_INDEX,
9eec50b8 1000 HV_X64_MSR_VP_RUNTIME,
5c919412 1001 HV_X64_MSR_SCONTROL,
1f4b34f8 1002 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 1003 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1004 MSR_KVM_PV_EOI_EN,
1005
ba904635 1006 MSR_IA32_TSC_ADJUST,
a3e06bbe 1007 MSR_IA32_TSCDEADLINE,
043405e1 1008 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1009 MSR_IA32_MCG_STATUS,
1010 MSR_IA32_MCG_CTL,
c45dcc71 1011 MSR_IA32_MCG_EXT_CTL,
64d60670 1012 MSR_IA32_SMBASE,
db2336a8
KH		 1013 MSR_PLATFORM_INFO,
1014 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1015};
1016
62ef68bb
PB		 1017static unsigned num_emulated_msrs;
1018
384bb783 1019bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1020{
b69e8cae 1021 if (efer & efer_reserved_bits)
384bb783 1022 return false;
15c4a640 1023
1b2fd70c
AG		 1024 if (efer & EFER_FFXSR) {
1025 struct kvm_cpuid_entry2 *feat;
1026
1027 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1028 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 1029 return false;
1b2fd70c
AG		 1030 }
1031
d8017474
AG		 1032 if (efer & EFER_SVME) {
1033 struct kvm_cpuid_entry2 *feat;
1034
1035 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1036 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1037 return false;
d8017474
AG		 1038 }
1039
384bb783
JK		 1040 return true;
1041}
1042EXPORT_SYMBOL_GPL(kvm_valid_efer);
1043
1044static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1045{
1046 u64 old_efer = vcpu->arch.efer;
1047
1048 if (!kvm_valid_efer(vcpu, efer))
1049 return 1;
1050
1051 if (is_paging(vcpu)
1052 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1053 return 1;
1054
15c4a640 1055 efer &= ~EFER_LMA;
f6801dff 1056 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1057
a3d204e2
SY		 1058 kvm_x86_ops->set_efer(vcpu, efer);
1059
aad82703
SY		 1060 /* Update reserved bits */
1061 if ((efer ^ old_efer) & EFER_NX)
1062 kvm_mmu_reset_context(vcpu);
1063
b69e8cae 1064 return 0;
15c4a640
CO		 1065}
1066
f2b4b7dd
JR		 1067void kvm_enable_efer_bits(u64 mask)
1068{
1069 efer_reserved_bits &= ~mask;
1070}
1071EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1072
15c4a640
CO		 1073/*
1074 * Writes msr value into into the appropriate "register".
1075 * Returns 0 on success, non-0 otherwise.
1076 * Assumes vcpu_load() was already called.
1077 */
8fe8ab46 1078int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1079{
854e8bb1
NA		 1080 switch (msr->index) {
1081 case MSR_FS_BASE:
1082 case MSR_GS_BASE:
1083 case MSR_KERNEL_GS_BASE:
1084 case MSR_CSTAR:
1085 case MSR_LSTAR:
1086 if (is_noncanonical_address(msr->data))
1087 return 1;
1088 break;
1089 case MSR_IA32_SYSENTER_EIP:
1090 case MSR_IA32_SYSENTER_ESP:
1091 /*
1092 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1093 * non-canonical address is written on Intel but not on
1094 * AMD (which ignores the top 32-bits, because it does
1095 * not implement 64-bit SYSENTER).
1096 *
1097 * 64-bit code should hence be able to write a non-canonical
1098 * value on AMD. Making the address canonical ensures that
1099 * vmentry does not fail on Intel after writing a non-canonical
1100 * value, and that something deterministic happens if the guest
1101 * invokes 64-bit SYSENTER.
1102 */
1103 msr->data = get_canonical(msr->data);
1104 }
8fe8ab46 1105 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1106}
854e8bb1 1107EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1108
313a3dc7
CO		 1109/*
1110 * Adapt set_msr() to msr_io()'s calling convention
1111 */
609e36d3
PB		 1112static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1113{
1114 struct msr_data msr;
1115 int r;
1116
1117 msr.index = index;
1118 msr.host_initiated = true;
1119 r = kvm_get_msr(vcpu, &msr);
1120 if (r)
1121 return r;
1122
1123 *data = msr.data;
1124 return 0;
1125}
1126
313a3dc7
CO		 1127static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1128{
8fe8ab46
WA		 1129 struct msr_data msr;
1130
1131 msr.data = *data;
1132 msr.index = index;
1133 msr.host_initiated = true;
1134 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1135}
1136
16e8d74d
MT		 1137#ifdef CONFIG_X86_64
1138struct pvclock_gtod_data {
1139 seqcount_t seq;
1140
1141 struct { /* extract of a clocksource struct */
1142 int vclock_mode;
a5a1d1c2
TG		 1143 u64 cycle_last;
1144 u64 mask;
16e8d74d
MT		 1145 u32 mult;
1146 u32 shift;
1147 } clock;
1148
cbcf2dd3
TG		 1149 u64 boot_ns;
1150 u64 nsec_base;
55dd00a7 1151 u64 wall_time_sec;
16e8d74d
MT		 1152};
1153
1154static struct pvclock_gtod_data pvclock_gtod_data;
1155
1156static void update_pvclock_gtod(struct timekeeper *tk)
1157{
1158 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1159 u64 boot_ns;
1160
876e7881 1161 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1162
1163 write_seqcount_begin(&vdata->seq);
1164
1165 /* copy pvclock gtod data */
876e7881
PZ		 1166 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1167 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1168 vdata->clock.mask = tk->tkr_mono.mask;
1169 vdata->clock.mult = tk->tkr_mono.mult;
1170 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1171
cbcf2dd3 1172 vdata->boot_ns = boot_ns;
876e7881 1173 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1174
55dd00a7
MT		 1175 vdata->wall_time_sec = tk->xtime_sec;
1176
16e8d74d
MT		 1177 write_seqcount_end(&vdata->seq);
1178}
1179#endif
1180
bab5bb39
NK		 1181void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1182{
1183 /*
1184 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1185 * vcpu_enter_guest. This function is only called from
1186 * the physical CPU that is running vcpu.
1187 */
1188 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1189}
16e8d74d 1190
18068523
GOC		 1191static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1192{
9ed3c444
AK		 1193 int version;
1194 int r;
50d0a0f9 1195 struct pvclock_wall_clock wc;
87aeb54f 1196 struct timespec64 boot;
18068523
GOC		 1197
1198 if (!wall_clock)
1199 return;
1200
9ed3c444
AK		 1201 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1202 if (r)
1203 return;
1204
1205 if (version & 1)
1206 ++version; /* first time write, random junk */
1207
1208 ++version;
18068523 1209
1dab1345
NK		 1210 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1211 return;
18068523 1212
50d0a0f9
GH		 1213 /*
1214 * The guest calculates current wall clock time by adding
34c238a1 1215 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1216 * wall clock specified here. guest system time equals host
1217 * system time for us, thus we must fill in host boot time here.
1218 */
87aeb54f 1219 getboottime64(&boot);
50d0a0f9 1220
4b648665 1221 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1222 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1223 boot = timespec64_sub(boot, ts);
4b648665 1224 }
87aeb54f 1225 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1226 wc.nsec = boot.tv_nsec;
1227 wc.version = version;
18068523
GOC		 1228
1229 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1230
1231 version++;
1232 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1233}
1234
50d0a0f9
GH		 1235static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1236{
b51012de
PB		 1237 do_shl32_div32(dividend, divisor);
1238 return dividend;
50d0a0f9
GH		 1239}
1240
3ae13faa 1241static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1242 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1243{
5f4e3f88 1244 uint64_t scaled64;
50d0a0f9
GH		 1245 int32_t shift = 0;
1246 uint64_t tps64;
1247 uint32_t tps32;
1248
3ae13faa
PB		 1249 tps64 = base_hz;
1250 scaled64 = scaled_hz;
50933623 1251 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1252 tps64 >>= 1;
1253 shift--;
1254 }
1255
1256 tps32 = (uint32_t)tps64;
50933623
JK		 1257 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1258 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1259 scaled64 >>= 1;
1260 else
1261 tps32 <<= 1;
50d0a0f9
GH		 1262 shift++;
1263 }
1264
5f4e3f88
ZA		 1265 *pshift = shift;
1266 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1267
3ae13faa
PB		 1268 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1269 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1270}
1271
d828199e 1272#ifdef CONFIG_X86_64
16e8d74d 1273static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1274#endif
16e8d74d 1275
c8076604 1276static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1277static unsigned long max_tsc_khz;
c8076604 1278
cc578287 1279static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1280{
cc578287
ZA		 1281 u64 v = (u64)khz * (1000000 + ppm);
1282 do_div(v, 1000000);
1283 return v;
1e993611
JR		 1284}
1285
381d585c
HZ		 1286static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1287{
1288 u64 ratio;
1289
1290 /* Guest TSC same frequency as host TSC? */
1291 if (!scale) {
1292 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1293 return 0;
1294 }
1295
1296 /* TSC scaling supported? */
1297 if (!kvm_has_tsc_control) {
1298 if (user_tsc_khz > tsc_khz) {
1299 vcpu->arch.tsc_catchup = 1;
1300 vcpu->arch.tsc_always_catchup = 1;
1301 return 0;
1302 } else {
1303 WARN(1, "user requested TSC rate below hardware speed\n");
1304 return -1;
1305 }
1306 }
1307
1308 /* TSC scaling required - calculate ratio */
1309 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1310 user_tsc_khz, tsc_khz);
1311
1312 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1313 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1314 user_tsc_khz);
1315 return -1;
1316 }
1317
1318 vcpu->arch.tsc_scaling_ratio = ratio;
1319 return 0;
1320}
1321
4941b8cb 1322static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1323{
cc578287
ZA		 1324 u32 thresh_lo, thresh_hi;
1325 int use_scaling = 0;
217fc9cf 1326
03ba32ca 1327 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1328 if (user_tsc_khz == 0) {
ad721883
HZ		 1329 /* set tsc_scaling_ratio to a safe value */
1330 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1331 return -1;
ad721883 1332 }
03ba32ca 1333
c285545f 1334 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1335 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1336 &vcpu->arch.virtual_tsc_shift,
1337 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1338 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1339
1340 /*
1341 * Compute the variation in TSC rate which is acceptable
1342 * within the range of tolerance and decide if the
1343 * rate being applied is within that bounds of the hardware
1344 * rate. If so, no scaling or compensation need be done.
1345 */
1346 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1347 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1348 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1349 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1350 use_scaling = 1;
1351 }
4941b8cb 1352 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1353}
1354
1355static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1356{
e26101b1 1357 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1358 vcpu->arch.virtual_tsc_mult,
1359 vcpu->arch.virtual_tsc_shift);
e26101b1 1360 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1361 return tsc;
1362}
1363
69b0049a 1364static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1365{
1366#ifdef CONFIG_X86_64
1367 bool vcpus_matched;
b48aa97e
MT		 1368 struct kvm_arch *ka = &vcpu->kvm->arch;
1369 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1370
1371 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1372 atomic_read(&vcpu->kvm->online_vcpus));
1373
7f187922
MT		 1374 /*
1375 * Once the masterclock is enabled, always perform request in
1376 * order to update it.
1377 *
1378 * In order to enable masterclock, the host clocksource must be TSC
1379 * and the vcpus need to have matched TSCs. When that happens,
1380 * perform request to enable masterclock.
1381 */
1382 if (ka->use_master_clock ||
1383 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1384 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1385
1386 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1387 atomic_read(&vcpu->kvm->online_vcpus),
1388 ka->use_master_clock, gtod->clock.vclock_mode);
1389#endif
1390}
1391
ba904635
WA		 1392static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1393{
3e3f5026 1394 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1395 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1396}
1397
35181e86
HZ		 1398/*
1399 * Multiply tsc by a fixed point number represented by ratio.
1400 *
1401 * The most significant 64-N bits (mult) of ratio represent the
1402 * integral part of the fixed point number; the remaining N bits
1403 * (frac) represent the fractional part, ie. ratio represents a fixed
1404 * point number (mult + frac * 2^(-N)).
1405 *
1406 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1407 */
1408static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1409{
1410 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1411}
1412
1413u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1414{
1415 u64 _tsc = tsc;
1416 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1417
1418 if (ratio != kvm_default_tsc_scaling_ratio)
1419 _tsc = __scale_tsc(ratio, tsc);
1420
1421 return _tsc;
1422}
1423EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1424
07c1419a
HZ		 1425static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1426{
1427 u64 tsc;
1428
1429 tsc = kvm_scale_tsc(vcpu, rdtsc());
1430
1431 return target_tsc - tsc;
1432}
1433
4ba76538
HZ		 1434u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1435{
ea26e4ec 1436 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1437}
1438EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1439
a545ab6a
LC		 1440static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1441{
1442 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1443 vcpu->arch.tsc_offset = offset;
1444}
1445
8fe8ab46 1446void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1447{
1448 struct kvm *kvm = vcpu->kvm;
f38e098f 1449 u64 offset, ns, elapsed;
99e3e30a 1450 unsigned long flags;
b48aa97e 1451 bool matched;
0d3da0d2 1452 bool already_matched;
8fe8ab46 1453 u64 data = msr->data;
c5e8ec8e 1454 bool synchronizing = false;
99e3e30a 1455
038f8c11 1456 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1457 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1458 ns = ktime_get_boot_ns();
f38e098f 1459 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1460
03ba32ca 1461 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1462 if (data == 0 && msr->host_initiated) {
1463 /*
1464 * detection of vcpu initialization -- need to sync
1465 * with other vCPUs. This particularly helps to keep
1466 * kvm_clock stable after CPU hotplug
1467 */
1468 synchronizing = true;
1469 } else {
1470 u64 tsc_exp = kvm->arch.last_tsc_write +
1471 nsec_to_cycles(vcpu, elapsed);
1472 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1473 /*
1474 * Special case: TSC write with a small delta (1 second)
1475 * of virtual cycle time against real time is
1476 * interpreted as an attempt to synchronize the CPU.
1477 */
1478 synchronizing = data < tsc_exp + tsc_hz &&
1479 data + tsc_hz > tsc_exp;
1480 }
c5e8ec8e 1481 }
f38e098f
ZA		 1482
1483 /*
5d3cb0f6
ZA		 1484 * For a reliable TSC, we can match TSC offsets, and for an unstable
1485 * TSC, we add elapsed time in this computation. We could let the
1486 * compensation code attempt to catch up if we fall behind, but
1487 * it's better to try to match offsets from the beginning.
1488 */
c5e8ec8e 1489 if (synchronizing &&
5d3cb0f6 1490 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1491 if (!check_tsc_unstable()) {
e26101b1 1492 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1493 pr_debug("kvm: matched tsc offset for %llu\n", data);
1494 } else {
857e4099 1495 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1496 data += delta;
07c1419a 1497 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1498 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1499 }
b48aa97e 1500 matched = true;
0d3da0d2 1501 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1502 } else {
1503 /*
1504 * We split periods of matched TSC writes into generations.
1505 * For each generation, we track the original measured
1506 * nanosecond time, offset, and write, so if TSCs are in
1507 * sync, we can match exact offset, and if not, we can match
4a969980 1508 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1509 *
1510 * These values are tracked in kvm->arch.cur_xxx variables.
1511 */
1512 kvm->arch.cur_tsc_generation++;
1513 kvm->arch.cur_tsc_nsec = ns;
1514 kvm->arch.cur_tsc_write = data;
1515 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1516 matched = false;
0d3da0d2 1517 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1518 kvm->arch.cur_tsc_generation, data);
f38e098f 1519 }
e26101b1
ZA		 1520
1521 /*
1522 * We also track th most recent recorded KHZ, write and time to
1523 * allow the matching interval to be extended at each write.
1524 */
f38e098f
ZA		 1525 kvm->arch.last_tsc_nsec = ns;
1526 kvm->arch.last_tsc_write = data;
5d3cb0f6 1527 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1528
b183aa58 1529 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1530
1531 /* Keep track of which generation this VCPU has synchronized to */
1532 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1533 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1534 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1535
ba904635
WA		 1536 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1537 update_ia32_tsc_adjust_msr(vcpu, offset);
a545ab6a 1538 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1539 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1540
1541 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1542 if (!matched) {
b48aa97e 1543 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1544 } else if (!already_matched) {
1545 kvm->arch.nr_vcpus_matched_tsc++;
1546 }
b48aa97e
MT		 1547
1548 kvm_track_tsc_matching(vcpu);
1549 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1550}
e26101b1 1551
99e3e30a
ZA		 1552EXPORT_SYMBOL_GPL(kvm_write_tsc);
1553
58ea6767
HZ		 1554static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1555 s64 adjustment)
1556{
ea26e4ec 1557 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1558}
1559
1560static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1561{
1562 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1563 WARN_ON(adjustment < 0);
1564 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1565 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1566}
1567
d828199e
MT		 1568#ifdef CONFIG_X86_64
1569
a5a1d1c2 1570static u64 read_tsc(void)
d828199e 1571{
a5a1d1c2 1572 u64 ret = (u64)rdtsc_ordered();
03b9730b 1573 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1574
1575 if (likely(ret >= last))
1576 return ret;
1577
1578 /*
1579 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1580 * predictable (it's just a function of time and the likely is
d828199e
MT		 1581 * very likely) and there's a data dependence, so force GCC
1582 * to generate a branch instead. I don't barrier() because
1583 * we don't actually need a barrier, and if this function
1584 * ever gets inlined it will generate worse code.
1585 */
1586 asm volatile ("");
1587 return last;
1588}
1589
a5a1d1c2 1590static inline u64 vgettsc(u64 *cycle_now)
d828199e
MT		 1591{
1592 long v;
1593 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1594
1595 *cycle_now = read_tsc();
1596
1597 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1598 return v * gtod->clock.mult;
1599}
1600
a5a1d1c2 1601static int do_monotonic_boot(s64 *t, u64 *cycle_now)
d828199e 1602{
cbcf2dd3 1603 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1604 unsigned long seq;
d828199e 1605 int mode;
cbcf2dd3 1606 u64 ns;
d828199e 1607
d828199e
MT		 1608 do {
1609 seq = read_seqcount_begin(&gtod->seq);
1610 mode = gtod->clock.vclock_mode;
cbcf2dd3 1611 ns = gtod->nsec_base;
d828199e
MT		 1612 ns += vgettsc(cycle_now);
1613 ns >>= gtod->clock.shift;
cbcf2dd3 1614 ns += gtod->boot_ns;
d828199e 1615 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1616 *t = ns;
d828199e
MT		 1617
1618 return mode;
1619}
1620
55dd00a7
MT		 1621static int do_realtime(struct timespec *ts, u64 *cycle_now)
1622{
1623 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1624 unsigned long seq;
1625 int mode;
1626 u64 ns;
1627
1628 do {
1629 seq = read_seqcount_begin(&gtod->seq);
1630 mode = gtod->clock.vclock_mode;
1631 ts->tv_sec = gtod->wall_time_sec;
1632 ns = gtod->nsec_base;
1633 ns += vgettsc(cycle_now);
1634 ns >>= gtod->clock.shift;
1635 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1636
1637 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1638 ts->tv_nsec = ns;
1639
1640 return mode;
1641}
1642
d828199e 1643/* returns true if host is using tsc clocksource */
a5a1d1c2 1644static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
d828199e 1645{
d828199e
MT		 1646 /* checked again under seqlock below */
1647 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1648 return false;
1649
cbcf2dd3 1650 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e 1651}
55dd00a7
MT		 1652
1653/* returns true if host is using tsc clocksource */
1654static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1655 u64 *cycle_now)
1656{
1657 /* checked again under seqlock below */
1658 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1659 return false;
1660
1661 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1662}
d828199e
MT		 1663#endif
1664
1665/*
1666 *
b48aa97e
MT		 1667 * Assuming a stable TSC across physical CPUS, and a stable TSC
1668 * across virtual CPUs, the following condition is possible.
1669 * Each numbered line represents an event visible to both
d828199e
MT		 1670 * CPUs at the next numbered event.
1671 *
1672 * "timespecX" represents host monotonic time. "tscX" represents
1673 * RDTSC value.
1674 *
1675 * VCPU0 on CPU0 | VCPU1 on CPU1
1676 *
1677 * 1. read timespec0,tsc0
1678 * 2. | timespec1 = timespec0 + N
1679 * | tsc1 = tsc0 + M
1680 * 3. transition to guest | transition to guest
1681 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1682 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1683 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1684 *
1685 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1686 *
1687 * - ret0 < ret1
1688 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1689 * ...
1690 * - 0 < N - M => M < N
1691 *
1692 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1693 * always the case (the difference between two distinct xtime instances
1694 * might be smaller then the difference between corresponding TSC reads,
1695 * when updating guest vcpus pvclock areas).
1696 *
1697 * To avoid that problem, do not allow visibility of distinct
1698 * system_timestamp/tsc_timestamp values simultaneously: use a master
1699 * copy of host monotonic time values. Update that master copy
1700 * in lockstep.
1701 *
b48aa97e 1702 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1703 *
1704 */
1705
1706static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1707{
1708#ifdef CONFIG_X86_64
1709 struct kvm_arch *ka = &kvm->arch;
1710 int vclock_mode;
b48aa97e
MT		 1711 bool host_tsc_clocksource, vcpus_matched;
1712
1713 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1714 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1715
1716 /*
1717 * If the host uses TSC clock, then passthrough TSC as stable
1718 * to the guest.
1719 */
b48aa97e 1720 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1721 &ka->master_kernel_ns,
1722 &ka->master_cycle_now);
1723
16a96021 1724 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1725 && !ka->backwards_tsc_observed
54750f2c 1726 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1727
d828199e
MT		 1728 if (ka->use_master_clock)
1729 atomic_set(&kvm_guest_has_master_clock, 1);
1730
1731 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1732 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1733 vcpus_matched);
d828199e
MT		 1734#endif
1735}
1736
2860c4b1
PB		 1737void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1738{
1739 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1740}
1741
2e762ff7
MT		 1742static void kvm_gen_update_masterclock(struct kvm *kvm)
1743{
1744#ifdef CONFIG_X86_64
1745 int i;
1746 struct kvm_vcpu *vcpu;
1747 struct kvm_arch *ka = &kvm->arch;
1748
1749 spin_lock(&ka->pvclock_gtod_sync_lock);
1750 kvm_make_mclock_inprogress_request(kvm);
1751 /* no guest entries from this point */
1752 pvclock_update_vm_gtod_copy(kvm);
1753
1754 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1755 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1756
1757 /* guest entries allowed */
1758 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1759 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1760
1761 spin_unlock(&ka->pvclock_gtod_sync_lock);
1762#endif
1763}
1764
e891a32e 1765u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1766{
108b249c 1767 struct kvm_arch *ka = &kvm->arch;
8b953440 1768 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1769 u64 ret;
108b249c 1770
8b953440
PB		 1771 spin_lock(&ka->pvclock_gtod_sync_lock);
1772 if (!ka->use_master_clock) {
1773 spin_unlock(&ka->pvclock_gtod_sync_lock);
1774 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1775 }
1776
8b953440
PB		 1777 hv_clock.tsc_timestamp = ka->master_cycle_now;
1778 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1779 spin_unlock(&ka->pvclock_gtod_sync_lock);
1780
e2c2206a
WL		 1781 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1782 get_cpu();
1783
8b953440
PB		 1784 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1785 &hv_clock.tsc_shift,
1786 &hv_clock.tsc_to_system_mul);
e2c2206a
WL		 1787 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1788
1789 put_cpu();
1790
1791 return ret;
108b249c
PB		 1792}
1793
0d6dd2ff
PB		 1794static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1795{
1796 struct kvm_vcpu_arch *vcpu = &v->arch;
1797 struct pvclock_vcpu_time_info guest_hv_clock;
1798
4e335d9e 1799 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1800 &guest_hv_clock, sizeof(guest_hv_clock))))
1801 return;
1802
1803 /* This VCPU is paused, but it's legal for a guest to read another
1804 * VCPU's kvmclock, so we really have to follow the specification where
1805 * it says that version is odd if data is being modified, and even after
1806 * it is consistent.
1807 *
1808 * Version field updates must be kept separate. This is because
1809 * kvm_write_guest_cached might use a "rep movs" instruction, and
1810 * writes within a string instruction are weakly ordered. So there
1811 * are three writes overall.
1812 *
1813 * As a small optimization, only write the version field in the first
1814 * and third write. The vcpu->pv_time cache is still valid, because the
1815 * version field is the first in the struct.
1816 */
1817 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1818
1819 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1820 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1821 &vcpu->hv_clock,
1822 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1823
1824 smp_wmb();
1825
1826 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1827 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1828
1829 if (vcpu->pvclock_set_guest_stopped_request) {
1830 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1831 vcpu->pvclock_set_guest_stopped_request = false;
1832 }
1833
1834 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1835
4e335d9e
PB		 1836 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1837 &vcpu->hv_clock,
1838 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1839
1840 smp_wmb();
1841
1842 vcpu->hv_clock.version++;
4e335d9e
PB		 1843 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1844 &vcpu->hv_clock,
1845 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1846}
1847
34c238a1 1848static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1849{
78db6a50 1850 unsigned long flags, tgt_tsc_khz;
18068523 1851 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1852 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1853 s64 kernel_ns;
d828199e 1854 u64 tsc_timestamp, host_tsc;
51d59c6b 1855 u8 pvclock_flags;
d828199e
MT		 1856 bool use_master_clock;
1857
1858 kernel_ns = 0;
1859 host_tsc = 0;
18068523 1860
d828199e
MT		 1861 /*
1862 * If the host uses TSC clock, then passthrough TSC as stable
1863 * to the guest.
1864 */
1865 spin_lock(&ka->pvclock_gtod_sync_lock);
1866 use_master_clock = ka->use_master_clock;
1867 if (use_master_clock) {
1868 host_tsc = ka->master_cycle_now;
1869 kernel_ns = ka->master_kernel_ns;
1870 }
1871 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1872
1873 /* Keep irq disabled to prevent changes to the clock */
1874 local_irq_save(flags);
78db6a50
PB		 1875 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1876 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1877 local_irq_restore(flags);
1878 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1879 return 1;
1880 }
d828199e 1881 if (!use_master_clock) {
4ea1636b 1882 host_tsc = rdtsc();
108b249c 1883 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1884 }
1885
4ba76538 1886 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1887
c285545f
ZA		 1888 /*
1889 * We may have to catch up the TSC to match elapsed wall clock
1890 * time for two reasons, even if kvmclock is used.
1891 * 1) CPU could have been running below the maximum TSC rate
1892 * 2) Broken TSC compensation resets the base at each VCPU
1893 * entry to avoid unknown leaps of TSC even when running
1894 * again on the same CPU. This may cause apparent elapsed
1895 * time to disappear, and the guest to stand still or run
1896 * very slowly.
1897 */
1898 if (vcpu->tsc_catchup) {
1899 u64 tsc = compute_guest_tsc(v, kernel_ns);
1900 if (tsc > tsc_timestamp) {
f1e2b260 1901 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1902 tsc_timestamp = tsc;
1903 }
50d0a0f9
GH		 1904 }
1905
18068523
GOC		 1906 local_irq_restore(flags);
1907
0d6dd2ff 1908 /* With all the info we got, fill in the values */
18068523 1909
78db6a50
PB		 1910 if (kvm_has_tsc_control)
1911 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1912
1913 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1914 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1915 &vcpu->hv_clock.tsc_shift,
1916 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1917 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1918 }
1919
1d5f066e 1920 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1921 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1922 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1923
d828199e 1924 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 1925 pvclock_flags = 0;
d828199e
MT		 1926 if (use_master_clock)
1927 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1928
78c0337a
MT		 1929 vcpu->hv_clock.flags = pvclock_flags;
1930
095cf55d
PB		 1931 if (vcpu->pv_time_enabled)
1932 kvm_setup_pvclock_page(v);
1933 if (v == kvm_get_vcpu(v->kvm, 0))
1934 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 1935 return 0;
c8076604
GH		 1936}
1937
0061d53d
MT		 1938/*
1939 * kvmclock updates which are isolated to a given vcpu, such as
1940 * vcpu->cpu migration, should not allow system_timestamp from
1941 * the rest of the vcpus to remain static. Otherwise ntp frequency
1942 * correction applies to one vcpu's system_timestamp but not
1943 * the others.
1944 *
1945 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1946 * We need to rate-limit these requests though, as they can
1947 * considerably slow guests that have a large number of vcpus.
1948 * The time for a remote vcpu to update its kvmclock is bound
1949 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1950 */
1951
7e44e449
AJ		 1952#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1953
1954static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1955{
1956 int i;
7e44e449
AJ		 1957 struct delayed_work *dwork = to_delayed_work(work);
1958 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1959 kvmclock_update_work);
1960 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1961 struct kvm_vcpu *vcpu;
1962
1963 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1964 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1965 kvm_vcpu_kick(vcpu);
1966 }
1967}
1968
7e44e449
AJ		 1969static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1970{
1971 struct kvm *kvm = v->kvm;
1972
105b21bb 1973 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1974 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1975 KVMCLOCK_UPDATE_DELAY);
1976}
1977
332967a3
AJ		 1978#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1979
1980static void kvmclock_sync_fn(struct work_struct *work)
1981{
1982 struct delayed_work *dwork = to_delayed_work(work);
1983 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1984 kvmclock_sync_work);
1985 struct kvm *kvm = container_of(ka, struct kvm, arch);
1986
630994b3
MT		 1987 if (!kvmclock_periodic_sync)
1988 return;
1989
332967a3
AJ		 1990 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1991 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1992 KVMCLOCK_SYNC_PERIOD);
1993}
1994
890ca9ae 1995static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1996{
890ca9ae
HY		 1997 u64 mcg_cap = vcpu->arch.mcg_cap;
1998 unsigned bank_num = mcg_cap & 0xff;
1999
15c4a640 2000 switch (msr) {
15c4a640 2001 case MSR_IA32_MCG_STATUS:
890ca9ae 2002 vcpu->arch.mcg_status = data;
15c4a640 2003 break;
c7ac679c 2004 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2005 if (!(mcg_cap & MCG_CTL_P))
2006 return 1;
2007 if (data != 0 && data != ~(u64)0)
2008 return -1;
2009 vcpu->arch.mcg_ctl = data;
2010 break;
2011 default:
2012 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2013 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2014 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2015 /* only 0 or all 1s can be written to IA32_MCi_CTL
2016 * some Linux kernels though clear bit 10 in bank 4 to
2017 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2018 * this to avoid an uncatched #GP in the guest
2019 */
890ca9ae 2020 if ((offset & 0x3) == 0 &&
114be429 2021 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 2022 return -1;
2023 vcpu->arch.mce_banks[offset] = data;
2024 break;
2025 }
2026 return 1;
2027 }
2028 return 0;
2029}
2030
ffde22ac
ES		 2031static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2032{
2033 struct kvm *kvm = vcpu->kvm;
2034 int lm = is_long_mode(vcpu);
2035 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2036 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2037 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2038 : kvm->arch.xen_hvm_config.blob_size_32;
2039 u32 page_num = data & ~PAGE_MASK;
2040 u64 page_addr = data & PAGE_MASK;
2041 u8 *page;
2042 int r;
2043
2044 r = -E2BIG;
2045 if (page_num >= blob_size)
2046 goto out;
2047 r = -ENOMEM;
ff5c2c03
SL		 2048 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2049 if (IS_ERR(page)) {
2050 r = PTR_ERR(page);
ffde22ac 2051 goto out;
ff5c2c03 2052 }
54bf36aa 2053 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2054 goto out_free;
2055 r = 0;
2056out_free:
2057 kfree(page);
2058out:
2059 return r;
2060}
2061
344d9588
GN		 2062static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2063{
2064 gpa_t gpa = data & ~0x3f;
2065
4a969980 2066 /* Bits 2:5 are reserved, Should be zero */
6adba527 2067 if (data & 0x3c)
344d9588
GN		 2068 return 1;
2069
2070 vcpu->arch.apf.msr_val = data;
2071
2072 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2073 kvm_clear_async_pf_completion_queue(vcpu);
2074 kvm_async_pf_hash_reset(vcpu);
2075 return 0;
2076 }
2077
4e335d9e 2078 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2079 sizeof(u32)))
344d9588
GN		 2080 return 1;
2081
6adba527 2082 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2083 kvm_async_pf_wakeup_all(vcpu);
2084 return 0;
2085}
2086
12f9a48f
GC		 2087static void kvmclock_reset(struct kvm_vcpu *vcpu)
2088{
0b79459b 2089 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2090}
2091
c9aaa895
GC		 2092static void record_steal_time(struct kvm_vcpu *vcpu)
2093{
2094 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2095 return;
2096
4e335d9e 2097 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2098 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2099 return;
2100
0b9f6c46
PX		 2101 vcpu->arch.st.steal.preempted = 0;
2102
35f3fae1
WL		 2103 if (vcpu->arch.st.steal.version & 1)
2104 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2105
2106 vcpu->arch.st.steal.version += 1;
2107
4e335d9e 2108 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2109 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2110
2111 smp_wmb();
2112
c54cdf14
LC		 2113 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2114 vcpu->arch.st.last_steal;
2115 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2116
4e335d9e 2117 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2118 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2119
2120 smp_wmb();
2121
2122 vcpu->arch.st.steal.version += 1;
c9aaa895 2123
4e335d9e 2124 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2125 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2126}
2127
8fe8ab46 2128int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2129{
5753785f 2130 bool pr = false;
8fe8ab46
WA		 2131 u32 msr = msr_info->index;
2132 u64 data = msr_info->data;
5753785f 2133
15c4a640 2134 switch (msr) {
2e32b719
BP		 2135 case MSR_AMD64_NB_CFG:
2136 case MSR_IA32_UCODE_REV:
2137 case MSR_IA32_UCODE_WRITE:
2138 case MSR_VM_HSAVE_PA:
2139 case MSR_AMD64_PATCH_LOADER:
2140 case MSR_AMD64_BU_CFG2:
405a353a 2141 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2142 break;
2143
15c4a640 2144 case MSR_EFER:
b69e8cae 2145 return set_efer(vcpu, data);
8f1589d9
AP		 2146 case MSR_K7_HWCR:
2147 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2148 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2149 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2150 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2151 if (data != 0) {
a737f256
CD		 2152 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2153 data);
8f1589d9
AP		 2154 return 1;
2155 }
15c4a640 2156 break;
f7c6d140
AP		 2157 case MSR_FAM10H_MMIO_CONF_BASE:
2158 if (data != 0) {
a737f256
CD		 2159 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2160 "0x%llx\n", data);
f7c6d140
AP		 2161 return 1;
2162 }
15c4a640 2163 break;
b5e2fec0
AG		 2164 case MSR_IA32_DEBUGCTLMSR:
2165 if (!data) {
2166 /* We support the non-activated case already */
2167 break;
2168 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2169 /* Values other than LBR and BTF are vendor-specific,
2170 thus reserved and should throw a #GP */
2171 return 1;
2172 }
a737f256
CD		 2173 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2174 __func__, data);
b5e2fec0 2175 break;
9ba075a6 2176 case 0x200 ... 0x2ff:
ff53604b 2177 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2178 case MSR_IA32_APICBASE:
58cb628d 2179 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2180 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2181 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2182 case MSR_IA32_TSCDEADLINE:
2183 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2184 break;
ba904635
WA		 2185 case MSR_IA32_TSC_ADJUST:
2186 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2187 if (!msr_info->host_initiated) {
d913b904 2188 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2189 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2190 }
2191 vcpu->arch.ia32_tsc_adjust_msr = data;
2192 }
2193 break;
15c4a640 2194 case MSR_IA32_MISC_ENABLE:
ad312c7c 2195 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2196 break;
64d60670
PB		 2197 case MSR_IA32_SMBASE:
2198 if (!msr_info->host_initiated)
2199 return 1;
2200 vcpu->arch.smbase = data;
2201 break;
11c6bffa 2202 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2203 case MSR_KVM_WALL_CLOCK:
2204 vcpu->kvm->arch.wall_clock = data;
2205 kvm_write_wall_clock(vcpu->kvm, data);
2206 break;
11c6bffa 2207 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2208 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2209 struct kvm_arch *ka = &vcpu->kvm->arch;
2210
12f9a48f 2211 kvmclock_reset(vcpu);
18068523 2212
54750f2c
MT		 2213 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2214 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2215
2216 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2217 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2218
2219 ka->boot_vcpu_runs_old_kvmclock = tmp;
2220 }
2221
18068523 2222 vcpu->arch.time = data;
0061d53d 2223 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2224
2225 /* we verify if the enable bit is set... */
2226 if (!(data & 1))
2227 break;
2228
4e335d9e 2229 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2230 &vcpu->arch.pv_time, data & ~1ULL,
2231 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2232 vcpu->arch.pv_time_enabled = false;
2233 else
2234 vcpu->arch.pv_time_enabled = true;
32cad84f 2235
18068523
GOC		 2236 break;
2237 }
344d9588
GN		 2238 case MSR_KVM_ASYNC_PF_EN:
2239 if (kvm_pv_enable_async_pf(vcpu, data))
2240 return 1;
2241 break;
c9aaa895
GC		 2242 case MSR_KVM_STEAL_TIME:
2243
2244 if (unlikely(!sched_info_on()))
2245 return 1;
2246
2247 if (data & KVM_STEAL_RESERVED_MASK)
2248 return 1;
2249
4e335d9e 2250 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2251 data & KVM_STEAL_VALID_BITS,
2252 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2253 return 1;
2254
2255 vcpu->arch.st.msr_val = data;
2256
2257 if (!(data & KVM_MSR_ENABLED))
2258 break;
2259
c9aaa895
GC		 2260 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2261
2262 break;
ae7a2a3f
MT		 2263 case MSR_KVM_PV_EOI_EN:
2264 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2265 return 1;
2266 break;
c9aaa895 2267
890ca9ae
HY		 2268 case MSR_IA32_MCG_CTL:
2269 case MSR_IA32_MCG_STATUS:
81760dcc 2270 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2271 return set_msr_mce(vcpu, msr, data);
71db6023 2272
6912ac32
WH		 2273 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2274 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2275 pr = true; /* fall through */
2276 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2277 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2278 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2279 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2280
2281 if (pr || data != 0)
a737f256
CD		 2282 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2283 "0x%x data 0x%llx\n", msr, data);
5753785f 2284 break;
84e0cefa
JS		 2285 case MSR_K7_CLK_CTL:
2286 /*
2287 * Ignore all writes to this no longer documented MSR.
2288 * Writes are only relevant for old K7 processors,
2289 * all pre-dating SVM, but a recommended workaround from
4a969980 2290 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2291 * affected processor models on the command line, hence
2292 * the need to ignore the workaround.
2293 */
2294 break;
55cd8e5a 2295 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2296 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2297 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2298 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2299 return kvm_hv_set_msr_common(vcpu, msr, data,
2300 msr_info->host_initiated);
91c9c3ed 2301 case MSR_IA32_BBL_CR_CTL3:
2302 /* Drop writes to this legacy MSR -- see rdmsr
2303 * counterpart for further detail.
2304 */
796f4687 2305 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", msr, data);
91c9c3ed 2306 break;
2b036c6b
BO		 2307 case MSR_AMD64_OSVW_ID_LENGTH:
2308 if (!guest_cpuid_has_osvw(vcpu))
2309 return 1;
2310 vcpu->arch.osvw.length = data;
2311 break;
2312 case MSR_AMD64_OSVW_STATUS:
2313 if (!guest_cpuid_has_osvw(vcpu))
2314 return 1;
2315 vcpu->arch.osvw.status = data;
2316 break;
db2336a8
KH		 2317 case MSR_PLATFORM_INFO:
2318 if (!msr_info->host_initiated ||
2319 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2320 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2321 cpuid_fault_enabled(vcpu)))
2322 return 1;
2323 vcpu->arch.msr_platform_info = data;
2324 break;
2325 case MSR_MISC_FEATURES_ENABLES:
2326 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2327 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2328 !supports_cpuid_fault(vcpu)))
2329 return 1;
2330 vcpu->arch.msr_misc_features_enables = data;
2331 break;
15c4a640 2332 default:
ffde22ac
ES		 2333 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2334 return xen_hvm_config(vcpu, data);
c6702c9d 2335 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2336 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2337 if (!ignore_msrs) {
ae0f5499 2338 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2339 msr, data);
ed85c068
AP		 2340 return 1;
2341 } else {
796f4687 2342 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
a737f256 2343 msr, data);
ed85c068
AP		 2344 break;
2345 }
15c4a640
CO		 2346 }
2347 return 0;
2348}
2349EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2350
2351
2352/*
2353 * Reads an msr value (of 'msr_index') into 'pdata'.
2354 * Returns 0 on success, non-0 otherwise.
2355 * Assumes vcpu_load() was already called.
2356 */
609e36d3 2357int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2358{
609e36d3 2359 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2360}
ff651cb6 2361EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2362
890ca9ae 2363static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2364{
2365 u64 data;
890ca9ae
HY		 2366 u64 mcg_cap = vcpu->arch.mcg_cap;
2367 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2368
2369 switch (msr) {
15c4a640
CO		 2370 case MSR_IA32_P5_MC_ADDR:
2371 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2372 data = 0;
2373 break;
15c4a640 2374 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2375 data = vcpu->arch.mcg_cap;
2376 break;
c7ac679c 2377 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2378 if (!(mcg_cap & MCG_CTL_P))
2379 return 1;
2380 data = vcpu->arch.mcg_ctl;
2381 break;
2382 case MSR_IA32_MCG_STATUS:
2383 data = vcpu->arch.mcg_status;
2384 break;
2385 default:
2386 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2387 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2388 u32 offset = msr - MSR_IA32_MC0_CTL;
2389 data = vcpu->arch.mce_banks[offset];
2390 break;
2391 }
2392 return 1;
2393 }
2394 *pdata = data;
2395 return 0;
2396}
2397
609e36d3 2398int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2399{
609e36d3 2400 switch (msr_info->index) {
890ca9ae 2401 case MSR_IA32_PLATFORM_ID:
15c4a640 2402 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2403 case MSR_IA32_DEBUGCTLMSR:
2404 case MSR_IA32_LASTBRANCHFROMIP:
2405 case MSR_IA32_LASTBRANCHTOIP:
2406 case MSR_IA32_LASTINTFROMIP:
2407 case MSR_IA32_LASTINTTOIP:
60af2ecd 2408 case MSR_K8_SYSCFG:
3afb1121
PB		 2409 case MSR_K8_TSEG_ADDR:
2410 case MSR_K8_TSEG_MASK:
60af2ecd 2411 case MSR_K7_HWCR:
61a6bd67 2412 case MSR_VM_HSAVE_PA:
1fdbd48c 2413 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2414 case MSR_AMD64_NB_CFG:
f7c6d140 2415 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2416 case MSR_AMD64_BU_CFG2:
0c2df2a1 2417 case MSR_IA32_PERF_CTL:
405a353a 2418 case MSR_AMD64_DC_CFG:
609e36d3 2419 msr_info->data = 0;
15c4a640 2420 break;
6912ac32
WH		 2421 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2422 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2423 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2424 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2425 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2426 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2427 msr_info->data = 0;
5753785f 2428 break;
742bc670 2429 case MSR_IA32_UCODE_REV:
609e36d3 2430 msr_info->data = 0x100000000ULL;
742bc670 2431 break;
9ba075a6 2432 case MSR_MTRRcap:
9ba075a6 2433 case 0x200 ... 0x2ff:
ff53604b 2434 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2435 case 0xcd: /* fsb frequency */
609e36d3 2436 msr_info->data = 3;
15c4a640 2437 break;
7b914098
JS		 2438 /*
2439 * MSR_EBC_FREQUENCY_ID
2440 * Conservative value valid for even the basic CPU models.
2441 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2442 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2443 * and 266MHz for model 3, or 4. Set Core Clock
2444 * Frequency to System Bus Frequency Ratio to 1 (bits
2445 * 31:24) even though these are only valid for CPU
2446 * models > 2, however guests may end up dividing or
2447 * multiplying by zero otherwise.
2448 */
2449 case MSR_EBC_FREQUENCY_ID:
609e36d3 2450 msr_info->data = 1 << 24;
7b914098 2451 break;
15c4a640 2452 case MSR_IA32_APICBASE:
609e36d3 2453 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2454 break;
0105d1a5 2455 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2456 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2457 break;
a3e06bbe 2458 case MSR_IA32_TSCDEADLINE:
609e36d3 2459 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2460 break;
ba904635 2461 case MSR_IA32_TSC_ADJUST:
609e36d3 2462 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2463 break;
15c4a640 2464 case MSR_IA32_MISC_ENABLE:
609e36d3 2465 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2466 break;
64d60670
PB		 2467 case MSR_IA32_SMBASE:
2468 if (!msr_info->host_initiated)
2469 return 1;
2470 msr_info->data = vcpu->arch.smbase;
15c4a640 2471 break;
847f0ad8
AG		 2472 case MSR_IA32_PERF_STATUS:
2473 /* TSC increment by tick */
609e36d3 2474 msr_info->data = 1000ULL;
847f0ad8 2475 /* CPU multiplier */
b0996ae4 2476 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2477 break;
15c4a640 2478 case MSR_EFER:
609e36d3 2479 msr_info->data = vcpu->arch.efer;
15c4a640 2480 break;
18068523 2481 case MSR_KVM_WALL_CLOCK:
11c6bffa 2482 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2483 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2484 break;
2485 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2486 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2487 msr_info->data = vcpu->arch.time;
18068523 2488 break;
344d9588 2489 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2490 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2491 break;
c9aaa895 2492 case MSR_KVM_STEAL_TIME:
609e36d3 2493 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2494 break;
1d92128f 2495 case MSR_KVM_PV_EOI_EN:
609e36d3 2496 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2497 break;
890ca9ae
HY		 2498 case MSR_IA32_P5_MC_ADDR:
2499 case MSR_IA32_P5_MC_TYPE:
2500 case MSR_IA32_MCG_CAP:
2501 case MSR_IA32_MCG_CTL:
2502 case MSR_IA32_MCG_STATUS:
81760dcc 2503 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2504 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2505 case MSR_K7_CLK_CTL:
2506 /*
2507 * Provide expected ramp-up count for K7. All other
2508 * are set to zero, indicating minimum divisors for
2509 * every field.
2510 *
2511 * This prevents guest kernels on AMD host with CPU
2512 * type 6, model 8 and higher from exploding due to
2513 * the rdmsr failing.
2514 */
609e36d3 2515 msr_info->data = 0x20000000;
84e0cefa 2516 break;
55cd8e5a 2517 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2518 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2519 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2520 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2521 return kvm_hv_get_msr_common(vcpu,
2522 msr_info->index, &msr_info->data);
55cd8e5a 2523 break;
91c9c3ed 2524 case MSR_IA32_BBL_CR_CTL3:
2525 /* This legacy MSR exists but isn't fully documented in current
2526 * silicon. It is however accessed by winxp in very narrow
2527 * scenarios where it sets bit #19, itself documented as
2528 * a "reserved" bit. Best effort attempt to source coherent
2529 * read data here should the balance of the register be
2530 * interpreted by the guest:
2531 *
2532 * L2 cache control register 3: 64GB range, 256KB size,
2533 * enabled, latency 0x1, configured
2534 */
609e36d3 2535 msr_info->data = 0xbe702111;
91c9c3ed 2536 break;
2b036c6b
BO		 2537 case MSR_AMD64_OSVW_ID_LENGTH:
2538 if (!guest_cpuid_has_osvw(vcpu))
2539 return 1;
609e36d3 2540 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2541 break;
2542 case MSR_AMD64_OSVW_STATUS:
2543 if (!guest_cpuid_has_osvw(vcpu))
2544 return 1;
609e36d3 2545 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2546 break;
db2336a8
KH		 2547 case MSR_PLATFORM_INFO:
2548 msr_info->data = vcpu->arch.msr_platform_info;
2549 break;
2550 case MSR_MISC_FEATURES_ENABLES:
2551 msr_info->data = vcpu->arch.msr_misc_features_enables;
2552 break;
15c4a640 2553 default:
c6702c9d 2554 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2555 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2556 if (!ignore_msrs) {
ae0f5499
BD		 2557 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2558 msr_info->index);
ed85c068
AP		 2559 return 1;
2560 } else {
609e36d3
PB		 2561 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2562 msr_info->data = 0;
ed85c068
AP		 2563 }
2564 break;
15c4a640 2565 }
15c4a640
CO		 2566 return 0;
2567}
2568EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2569
313a3dc7
CO		 2570/*
2571 * Read or write a bunch of msrs. All parameters are kernel addresses.
2572 *
2573 * @return number of msrs set successfully.
2574 */
2575static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2576 struct kvm_msr_entry *entries,
2577 int (*do_msr)(struct kvm_vcpu *vcpu,
2578 unsigned index, u64 *data))
2579{
f656ce01 2580 int i, idx;
313a3dc7 2581
f656ce01 2582 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2583 for (i = 0; i < msrs->nmsrs; ++i)
2584 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2585 break;
f656ce01 2586 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2587
313a3dc7
CO		 2588 return i;
2589}
2590
2591/*
2592 * Read or write a bunch of msrs. Parameters are user addresses.
2593 *
2594 * @return number of msrs set successfully.
2595 */
2596static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2597 int (*do_msr)(struct kvm_vcpu *vcpu,
2598 unsigned index, u64 *data),
2599 int writeback)
2600{
2601 struct kvm_msrs msrs;
2602 struct kvm_msr_entry *entries;
2603 int r, n;
2604 unsigned size;
2605
2606 r = -EFAULT;
2607 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2608 goto out;
2609
2610 r = -E2BIG;
2611 if (msrs.nmsrs >= MAX_IO_MSRS)
2612 goto out;
2613
313a3dc7 2614 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2615 entries = memdup_user(user_msrs->entries, size);
2616 if (IS_ERR(entries)) {
2617 r = PTR_ERR(entries);
313a3dc7 2618 goto out;
ff5c2c03 2619 }
313a3dc7
CO		 2620
2621 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2622 if (r < 0)
2623 goto out_free;
2624
2625 r = -EFAULT;
2626 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2627 goto out_free;
2628
2629 r = n;
2630
2631out_free:
7a73c028 2632 kfree(entries);
313a3dc7
CO		 2633out:
2634 return r;
2635}
2636
784aa3d7 2637int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2638{
2639 int r;
2640
2641 switch (ext) {
2642 case KVM_CAP_IRQCHIP:
2643 case KVM_CAP_HLT:
2644 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2645 case KVM_CAP_SET_TSS_ADDR:
07716717 2646 case KVM_CAP_EXT_CPUID:
9c15bb1d 2647 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2648 case KVM_CAP_CLOCKSOURCE:
7837699f 2649 case KVM_CAP_PIT:
a28e4f5a 2650 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2651 case KVM_CAP_MP_STATE:
ed848624 2652 case KVM_CAP_SYNC_MMU:
a355c85c 2653 case KVM_CAP_USER_NMI:
52d939a0 2654 case KVM_CAP_REINJECT_CONTROL:
4925663a 2655 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2656 case KVM_CAP_IOEVENTFD:
f848a5a8 2657 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2658 case KVM_CAP_PIT2:
e9f42757 2659 case KVM_CAP_PIT_STATE2:
b927a3ce 2660 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2661 case KVM_CAP_XEN_HVM:
3cfc3092 2662 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2663 case KVM_CAP_HYPERV:
10388a07 2664 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2665 case KVM_CAP_HYPERV_SPIN:
5c919412 2666 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2667 case KVM_CAP_HYPERV_SYNIC2:
ab9f4ecb 2668 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2669 case KVM_CAP_DEBUGREGS:
d2be1651 2670 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2671 case KVM_CAP_XSAVE:
344d9588 2672 case KVM_CAP_ASYNC_PF:
92a1f12d 2673 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2674 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2675 case KVM_CAP_READONLY_MEM:
5f66b620 2676 case KVM_CAP_HYPERV_TIME:
100943c5 2677 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2678 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2679 case KVM_CAP_ENABLE_CAP_VM:
2680 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2681 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2682 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2683 case KVM_CAP_IMMEDIATE_EXIT:
018d00d2
ZX		 2684 r = 1;
2685 break;
e3fd9a93
PB		 2686 case KVM_CAP_ADJUST_CLOCK:
2687 r = KVM_CLOCK_TSC_STABLE;
2688 break;
668fffa3
MT		 2689 case KVM_CAP_X86_GUEST_MWAIT:
2690 r = kvm_mwait_in_guest();
2691 break;
6d396b55
PB		 2692 case KVM_CAP_X86_SMM:
2693 /* SMBASE is usually relocated above 1M on modern chipsets,
2694 * and SMM handlers might indeed rely on 4G segment limits,
2695 * so do not report SMM to be available if real mode is
2696 * emulated via vm86 mode. Still, do not go to great lengths
2697 * to avoid userspace's usage of the feature, because it is a
2698 * fringe case that is not enabled except via specific settings
2699 * of the module parameters.
2700 */
2701 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2702 break;
774ead3a
AK		 2703 case KVM_CAP_VAPIC:
2704 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2705 break;
f725230a 2706 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2707 r = KVM_SOFT_MAX_VCPUS;
2708 break;
2709 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2710 r = KVM_MAX_VCPUS;
2711 break;
a988b910 2712 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2713 r = KVM_USER_MEM_SLOTS;
a988b910 2714 break;
a68a6a72
MT		 2715 case KVM_CAP_PV_MMU: /* obsolete */
2716 r = 0;
2f333bcb 2717 break;
890ca9ae
HY		 2718 case KVM_CAP_MCE:
2719 r = KVM_MAX_MCE_BANKS;
2720 break;
2d5b5a66 2721 case KVM_CAP_XCRS:
d366bf7e 2722 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2723 break;
92a1f12d
JR		 2724 case KVM_CAP_TSC_CONTROL:
2725 r = kvm_has_tsc_control;
2726 break;
37131313
RK		 2727 case KVM_CAP_X2APIC_API:
2728 r = KVM_X2APIC_API_VALID_FLAGS;
2729 break;
018d00d2
ZX		 2730 default:
2731 r = 0;
2732 break;
2733 }
2734 return r;
2735
2736}
2737
043405e1
CO		 2738long kvm_arch_dev_ioctl(struct file *filp,
2739 unsigned int ioctl, unsigned long arg)
2740{
2741 void __user *argp = (void __user *)arg;
2742 long r;
2743
2744 switch (ioctl) {
2745 case KVM_GET_MSR_INDEX_LIST: {
2746 struct kvm_msr_list __user *user_msr_list = argp;
2747 struct kvm_msr_list msr_list;
2748 unsigned n;
2749
2750 r = -EFAULT;
2751 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2752 goto out;
2753 n = msr_list.nmsrs;
62ef68bb 2754 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2755 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2756 goto out;
2757 r = -E2BIG;
e125e7b6 2758 if (n < msr_list.nmsrs)
043405e1
CO		 2759 goto out;
2760 r = -EFAULT;
2761 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2762 num_msrs_to_save * sizeof(u32)))
2763 goto out;
e125e7b6 2764 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2765 &emulated_msrs,
62ef68bb 2766 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2767 goto out;
2768 r = 0;
2769 break;
2770 }
9c15bb1d
BP		 2771 case KVM_GET_SUPPORTED_CPUID:
2772 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2773 struct kvm_cpuid2 __user *cpuid_arg = argp;
2774 struct kvm_cpuid2 cpuid;
2775
2776 r = -EFAULT;
2777 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2778 goto out;
9c15bb1d
BP		 2779
2780 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2781 ioctl);
674eea0f
AK		 2782 if (r)
2783 goto out;
2784
2785 r = -EFAULT;
2786 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2787 goto out;
2788 r = 0;
2789 break;
2790 }
890ca9ae 2791 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2792 r = -EFAULT;
c45dcc71
AR		 2793 if (copy_to_user(argp, &kvm_mce_cap_supported,
2794 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2795 goto out;
2796 r = 0;
2797 break;
2798 }
043405e1
CO		 2799 default:
2800 r = -EINVAL;
2801 }
2802out:
2803 return r;
2804}
2805
f5f48ee1
SY		 2806static void wbinvd_ipi(void *garbage)
2807{
2808 wbinvd();
2809}
2810
2811static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2812{
e0f0bbc5 2813 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2814}
2815
313a3dc7
CO		 2816void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2817{
f5f48ee1
SY		 2818 /* Address WBINVD may be executed by guest */
2819 if (need_emulate_wbinvd(vcpu)) {
2820 if (kvm_x86_ops->has_wbinvd_exit())
2821 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2822 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2823 smp_call_function_single(vcpu->cpu,
2824 wbinvd_ipi, NULL, 1);
2825 }
2826
313a3dc7 2827 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2828
0dd6a6ed
ZA		 2829 /* Apply any externally detected TSC adjustments (due to suspend) */
2830 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2831 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2832 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2833 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2834 }
8f6055cb 2835
48434c20 2836 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2837 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2838 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2839 if (tsc_delta < 0)
2840 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2841
c285545f 2842 if (check_tsc_unstable()) {
07c1419a 2843 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2844 vcpu->arch.last_guest_tsc);
a545ab6a 2845 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2846 vcpu->arch.tsc_catchup = 1;
c285545f 2847 }
a749e247
PB		 2848
2849 if (kvm_lapic_hv_timer_in_use(vcpu))
2850 kvm_lapic_restart_hv_timer(vcpu);
2851
d98d07ca
MT		 2852 /*
2853 * On a host with synchronized TSC, there is no need to update
2854 * kvmclock on vcpu->cpu migration
2855 */
2856 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2857 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 2858 if (vcpu->cpu != cpu)
1bd2009e 2859 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 2860 vcpu->cpu = cpu;
6b7d7e76 2861 }
c9aaa895 2862
c9aaa895 2863 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2864}
2865
0b9f6c46
PX		 2866static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2867{
2868 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2869 return;
2870
2871 vcpu->arch.st.steal.preempted = 1;
2872
4e335d9e 2873 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 2874 &vcpu->arch.st.steal.preempted,
2875 offsetof(struct kvm_steal_time, preempted),
2876 sizeof(vcpu->arch.st.steal.preempted));
2877}
2878
313a3dc7
CO		 2879void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2880{
cc0d907c 2881 int idx;
931f261b
AA		 2882 /*
2883 * Disable page faults because we're in atomic context here.
2884 * kvm_write_guest_offset_cached() would call might_fault()
2885 * that relies on pagefault_disable() to tell if there's a
2886 * bug. NOTE: the write to guest memory may not go through if
2887 * during postcopy live migration or if there's heavy guest
2888 * paging.
2889 */
2890 pagefault_disable();
cc0d907c
AA		 2891 /*
2892 * kvm_memslots() will be called by
2893 * kvm_write_guest_offset_cached() so take the srcu lock.
2894 */
2895 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 2896 kvm_steal_time_set_preempted(vcpu);
cc0d907c 2897 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 2898 pagefault_enable();
02daab21 2899 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2900 kvm_put_guest_fpu(vcpu);
4ea1636b 2901 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2902}
2903
313a3dc7
CO		 2904static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2905 struct kvm_lapic_state *s)
2906{
76dfafd5 2907 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb
AS		 2908 kvm_x86_ops->sync_pir_to_irr(vcpu);
2909
a92e2543 2910 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 2911}
2912
2913static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2914 struct kvm_lapic_state *s)
2915{
a92e2543
RK		 2916 int r;
2917
2918 r = kvm_apic_set_state(vcpu, s);
2919 if (r)
2920 return r;
cb142eb7 2921 update_cr8_intercept(vcpu);
313a3dc7
CO		 2922
2923 return 0;
2924}
2925
127a457a
MG		 2926static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2927{
2928 return (!lapic_in_kernel(vcpu) ||
2929 kvm_apic_accept_pic_intr(vcpu));
2930}
2931
782d422b
MG		 2932/*
2933 * if userspace requested an interrupt window, check that the
2934 * interrupt window is open.
2935 *
2936 * No need to exit to userspace if we already have an interrupt queued.
2937 */
2938static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2939{
2940 return kvm_arch_interrupt_allowed(vcpu) &&
2941 !kvm_cpu_has_interrupt(vcpu) &&
2942 !kvm_event_needs_reinjection(vcpu) &&
2943 kvm_cpu_accept_dm_intr(vcpu);
2944}
2945
f77bc6a4
ZX		 2946static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2947 struct kvm_interrupt *irq)
2948{
02cdb50f 2949 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2950 return -EINVAL;
1c1a9ce9
SR		 2951
2952 if (!irqchip_in_kernel(vcpu->kvm)) {
2953 kvm_queue_interrupt(vcpu, irq->irq, false);
2954 kvm_make_request(KVM_REQ_EVENT, vcpu);
2955 return 0;
2956 }
2957
2958 /*
2959 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2960 * fail for in-kernel 8259.
2961 */
2962 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2963 return -ENXIO;
f77bc6a4 2964
1c1a9ce9
SR		 2965 if (vcpu->arch.pending_external_vector != -1)
2966 return -EEXIST;
f77bc6a4 2967
1c1a9ce9 2968 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2969 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2970 return 0;
2971}
2972
c4abb7c9
JK		 2973static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2974{
c4abb7c9 2975 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2976
2977 return 0;
2978}
2979
f077825a
PB		 2980static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2981{
64d60670
PB		 2982 kvm_make_request(KVM_REQ_SMI, vcpu);
2983
f077825a
PB		 2984 return 0;
2985}
2986
b209749f
AK		 2987static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2988 struct kvm_tpr_access_ctl *tac)
2989{
2990 if (tac->flags)
2991 return -EINVAL;
2992 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2993 return 0;
2994}
2995
890ca9ae
HY		 2996static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2997 u64 mcg_cap)
2998{
2999 int r;
3000 unsigned bank_num = mcg_cap & 0xff, bank;
3001
3002 r = -EINVAL;
a9e38c3e 3003 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3004 goto out;
c45dcc71 3005 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3006 goto out;
3007 r = 0;
3008 vcpu->arch.mcg_cap = mcg_cap;
3009 /* Init IA32_MCG_CTL to all 1s */
3010 if (mcg_cap & MCG_CTL_P)
3011 vcpu->arch.mcg_ctl = ~(u64)0;
3012 /* Init IA32_MCi_CTL to all 1s */
3013 for (bank = 0; bank < bank_num; bank++)
3014 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3015
3016 if (kvm_x86_ops->setup_mce)
3017 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3018out:
3019 return r;
3020}
3021
3022static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3023 struct kvm_x86_mce *mce)
3024{
3025 u64 mcg_cap = vcpu->arch.mcg_cap;
3026 unsigned bank_num = mcg_cap & 0xff;
3027 u64 *banks = vcpu->arch.mce_banks;
3028
3029 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3030 return -EINVAL;
3031 /*
3032 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3033 * reporting is disabled
3034 */
3035 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3036 vcpu->arch.mcg_ctl != ~(u64)0)
3037 return 0;
3038 banks += 4 * mce->bank;
3039 /*
3040 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3041 * reporting is disabled for the bank
3042 */
3043 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3044 return 0;
3045 if (mce->status & MCI_STATUS_UC) {
3046 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3047 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3048 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3049 return 0;
3050 }
3051 if (banks[1] & MCI_STATUS_VAL)
3052 mce->status |= MCI_STATUS_OVER;
3053 banks[2] = mce->addr;
3054 banks[3] = mce->misc;
3055 vcpu->arch.mcg_status = mce->mcg_status;
3056 banks[1] = mce->status;
3057 kvm_queue_exception(vcpu, MC_VECTOR);
3058 } else if (!(banks[1] & MCI_STATUS_VAL)
3059 || !(banks[1] & MCI_STATUS_UC)) {
3060 if (banks[1] & MCI_STATUS_VAL)
3061 mce->status |= MCI_STATUS_OVER;
3062 banks[2] = mce->addr;
3063 banks[3] = mce->misc;
3064 banks[1] = mce->status;
3065 } else
3066 banks[1] |= MCI_STATUS_OVER;
3067 return 0;
3068}
3069
3cfc3092
JK		 3070static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3071 struct kvm_vcpu_events *events)
3072{
7460fb4a 3073 process_nmi(vcpu);
03b82a30
JK		 3074 events->exception.injected =
3075 vcpu->arch.exception.pending &&
3076 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3077 events->exception.nr = vcpu->arch.exception.nr;
3078 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3079 events->exception.pad = 0;
3cfc3092
JK		 3080 events->exception.error_code = vcpu->arch.exception.error_code;
3081
03b82a30
JK		 3082 events->interrupt.injected =
3083 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3084 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3085 events->interrupt.soft = 0;
37ccdcbe 3086 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3087
3088 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3089 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3090 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3091 events->nmi.pad = 0;
3cfc3092 3092
66450a21 3093 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3094
f077825a
PB		 3095 events->smi.smm = is_smm(vcpu);
3096 events->smi.pending = vcpu->arch.smi_pending;
3097 events->smi.smm_inside_nmi =
3098 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3099 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3100
dab4b911 3101 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3102 | KVM_VCPUEVENT_VALID_SHADOW
3103 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3104 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3105}
3106
6ef4e07e
XG		 3107static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3108
3cfc3092
JK		 3109static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3110 struct kvm_vcpu_events *events)
3111{
dab4b911 3112 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3113 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3114 | KVM_VCPUEVENT_VALID_SHADOW
3115 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3116 return -EINVAL;
3117
78e546c8 3118 if (events->exception.injected &&
28d06353
JM		 3119 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3120 is_guest_mode(vcpu)))
78e546c8
PB		 3121 return -EINVAL;
3122
28bf2888
DH		 3123 /* INITs are latched while in SMM */
3124 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3125 (events->smi.smm || events->smi.pending) &&
3126 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3127 return -EINVAL;
3128
7460fb4a 3129 process_nmi(vcpu);
3cfc3092
JK		 3130 vcpu->arch.exception.pending = events->exception.injected;
3131 vcpu->arch.exception.nr = events->exception.nr;
3132 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3133 vcpu->arch.exception.error_code = events->exception.error_code;
3134
3135 vcpu->arch.interrupt.pending = events->interrupt.injected;
3136 vcpu->arch.interrupt.nr = events->interrupt.nr;
3137 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3138 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3139 kvm_x86_ops->set_interrupt_shadow(vcpu,
3140 events->interrupt.shadow);
3cfc3092
JK		 3141
3142 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3143 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3144 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3145 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3146
66450a21 3147 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3148 lapic_in_kernel(vcpu))
66450a21 3149 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3150
f077825a 3151 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3152 u32 hflags = vcpu->arch.hflags;
f077825a 3153 if (events->smi.smm)
6ef4e07e 3154 hflags |= HF_SMM_MASK;
f077825a 3155 else
6ef4e07e
XG		 3156 hflags &= ~HF_SMM_MASK;
3157 kvm_set_hflags(vcpu, hflags);
3158
f077825a
PB		 3159 vcpu->arch.smi_pending = events->smi.pending;
3160 if (events->smi.smm_inside_nmi)
3161 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3162 else
3163 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
bce87cce 3164 if (lapic_in_kernel(vcpu)) {
f077825a
PB		 3165 if (events->smi.latched_init)
3166 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3167 else
3168 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3169 }
3170 }
3171
3842d135
AK		 3172 kvm_make_request(KVM_REQ_EVENT, vcpu);
3173
3cfc3092
JK		 3174 return 0;
3175}
3176
a1efbe77
JK		 3177static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3178 struct kvm_debugregs *dbgregs)
3179{
73aaf249
JK		 3180 unsigned long val;
3181
a1efbe77 3182 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3183 kvm_get_dr(vcpu, 6, &val);
73aaf249 3184 dbgregs->dr6 = val;
a1efbe77
JK		 3185 dbgregs->dr7 = vcpu->arch.dr7;
3186 dbgregs->flags = 0;
97e69aa6 3187 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3188}
3189
3190static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3191 struct kvm_debugregs *dbgregs)
3192{
3193 if (dbgregs->flags)
3194 return -EINVAL;
3195
d14bdb55
PB		 3196 if (dbgregs->dr6 & ~0xffffffffull)
3197 return -EINVAL;
3198 if (dbgregs->dr7 & ~0xffffffffull)
3199 return -EINVAL;
3200
a1efbe77 3201 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3202 kvm_update_dr0123(vcpu);
a1efbe77 3203 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3204 kvm_update_dr6(vcpu);
a1efbe77 3205 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3206 kvm_update_dr7(vcpu);
a1efbe77 3207
a1efbe77
JK		 3208 return 0;
3209}
3210
df1daba7
PB		 3211#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3212
3213static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3214{
c47ada30 3215 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3216 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3217 u64 valid;
3218
3219 /*
3220 * Copy legacy XSAVE area, to avoid complications with CPUID
3221 * leaves 0 and 1 in the loop below.
3222 */
3223 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3224
3225 /* Set XSTATE_BV */
00c87e9a 3226 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3227 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3228
3229 /*
3230 * Copy each region from the possibly compacted offset to the
3231 * non-compacted offset.
3232 */
d91cab78 3233 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3234 while (valid) {
3235 u64 feature = valid & -valid;
3236 int index = fls64(feature) - 1;
3237 void *src = get_xsave_addr(xsave, feature);
3238
3239 if (src) {
3240 u32 size, offset, ecx, edx;
3241 cpuid_count(XSTATE_CPUID, index,
3242 &size, &offset, &ecx, &edx);
3243 memcpy(dest + offset, src, size);
3244 }
3245
3246 valid -= feature;
3247 }
3248}
3249
3250static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3251{
c47ada30 3252 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3253 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3254 u64 valid;
3255
3256 /*
3257 * Copy legacy XSAVE area, to avoid complications with CPUID
3258 * leaves 0 and 1 in the loop below.
3259 */
3260 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3261
3262 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3263 xsave->header.xfeatures = xstate_bv;
782511b0 3264 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3265 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3266
3267 /*
3268 * Copy each region from the non-compacted offset to the
3269 * possibly compacted offset.
3270 */
d91cab78 3271 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3272 while (valid) {
3273 u64 feature = valid & -valid;
3274 int index = fls64(feature) - 1;
3275 void *dest = get_xsave_addr(xsave, feature);
3276
3277 if (dest) {
3278 u32 size, offset, ecx, edx;
3279 cpuid_count(XSTATE_CPUID, index,
3280 &size, &offset, &ecx, &edx);
3281 memcpy(dest, src + offset, size);
ee4100da 3282 }
df1daba7
PB		 3283
3284 valid -= feature;
3285 }
3286}
3287
2d5b5a66
SY		 3288static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3289 struct kvm_xsave *guest_xsave)
3290{
d366bf7e 3291 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3292 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3293 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3294 } else {
2d5b5a66 3295 memcpy(guest_xsave->region,
7366ed77 3296 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3297 sizeof(struct fxregs_state));
2d5b5a66 3298 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3299 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3300 }
3301}
3302
a575813b
WL		 3303#define XSAVE_MXCSR_OFFSET 24
3304
2d5b5a66
SY		 3305static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3306 struct kvm_xsave *guest_xsave)
3307{
3308 u64 xstate_bv =
3309 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3310 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3311
d366bf7e 3312 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3313 /*
3314 * Here we allow setting states that are not present in
3315 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3316 * with old userspace.
3317 */
a575813b
WL		 3318 if (xstate_bv & ~kvm_supported_xcr0() ||
3319 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3320 return -EINVAL;
df1daba7 3321 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3322 } else {
a575813b
WL		 3323 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3324 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3325 return -EINVAL;
7366ed77 3326 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3327 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3328 }
3329 return 0;
3330}
3331
3332static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3333 struct kvm_xcrs *guest_xcrs)
3334{
d366bf7e 3335 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3336 guest_xcrs->nr_xcrs = 0;
3337 return;
3338 }
3339
3340 guest_xcrs->nr_xcrs = 1;
3341 guest_xcrs->flags = 0;
3342 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3343 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3344}
3345
3346static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3347 struct kvm_xcrs *guest_xcrs)
3348{
3349 int i, r = 0;
3350
d366bf7e 3351 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3352 return -EINVAL;
3353
3354 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3355 return -EINVAL;
3356
3357 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3358 /* Only support XCR0 currently */
c67a04cb 3359 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3360 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3361 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3362 break;
3363 }
3364 if (r)
3365 r = -EINVAL;
3366 return r;
3367}
3368
1c0b28c2
EM		 3369/*
3370 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3371 * stopped by the hypervisor. This function will be called from the host only.
3372 * EINVAL is returned when the host attempts to set the flag for a guest that
3373 * does not support pv clocks.
3374 */
3375static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3376{
0b79459b 3377 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3378 return -EINVAL;
51d59c6b 3379 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3380 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3381 return 0;
3382}
3383
5c919412
AS		 3384static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3385 struct kvm_enable_cap *cap)
3386{
3387 if (cap->flags)
3388 return -EINVAL;
3389
3390 switch (cap->cap) {
efc479e6
RK		 3391 case KVM_CAP_HYPERV_SYNIC2:
3392 if (cap->args[0])
3393 return -EINVAL;
5c919412 3394 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3395 if (!irqchip_in_kernel(vcpu->kvm))
3396 return -EINVAL;
efc479e6
RK		 3397 return kvm_hv_activate_synic(vcpu, cap->cap ==
3398 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3399 default:
3400 return -EINVAL;
3401 }
3402}
3403
313a3dc7
CO		 3404long kvm_arch_vcpu_ioctl(struct file *filp,
3405 unsigned int ioctl, unsigned long arg)
3406{
3407 struct kvm_vcpu *vcpu = filp->private_data;
3408 void __user *argp = (void __user *)arg;
3409 int r;
d1ac91d8
AK		 3410 union {
3411 struct kvm_lapic_state *lapic;
3412 struct kvm_xsave *xsave;
3413 struct kvm_xcrs *xcrs;
3414 void *buffer;
3415 } u;
3416
3417 u.buffer = NULL;
313a3dc7
CO		 3418 switch (ioctl) {
3419 case KVM_GET_LAPIC: {
2204ae3c 3420 r = -EINVAL;
bce87cce 3421 if (!lapic_in_kernel(vcpu))
2204ae3c 3422 goto out;
d1ac91d8 3423 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3424
b772ff36 3425 r = -ENOMEM;
d1ac91d8 3426 if (!u.lapic)
b772ff36 3427 goto out;
d1ac91d8 3428 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3429 if (r)
3430 goto out;
3431 r = -EFAULT;
d1ac91d8 3432 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3433 goto out;
3434 r = 0;
3435 break;
3436 }
3437 case KVM_SET_LAPIC: {
2204ae3c 3438 r = -EINVAL;
bce87cce 3439 if (!lapic_in_kernel(vcpu))
2204ae3c 3440 goto out;
ff5c2c03 3441 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3442 if (IS_ERR(u.lapic))
3443 return PTR_ERR(u.lapic);
ff5c2c03 3444
d1ac91d8 3445 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3446 break;
3447 }
f77bc6a4
ZX		 3448 case KVM_INTERRUPT: {
3449 struct kvm_interrupt irq;
3450
3451 r = -EFAULT;
3452 if (copy_from_user(&irq, argp, sizeof irq))
3453 goto out;
3454 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3455 break;
3456 }
c4abb7c9
JK		 3457 case KVM_NMI: {
3458 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3459 break;
3460 }
f077825a
PB		 3461 case KVM_SMI: {
3462 r = kvm_vcpu_ioctl_smi(vcpu);
3463 break;
3464 }
313a3dc7
CO		 3465 case KVM_SET_CPUID: {
3466 struct kvm_cpuid __user *cpuid_arg = argp;
3467 struct kvm_cpuid cpuid;
3468
3469 r = -EFAULT;
3470 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3471 goto out;
3472 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3473 break;
3474 }
07716717
DK		 3475 case KVM_SET_CPUID2: {
3476 struct kvm_cpuid2 __user *cpuid_arg = argp;
3477 struct kvm_cpuid2 cpuid;
3478
3479 r = -EFAULT;
3480 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3481 goto out;
3482 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3483 cpuid_arg->entries);
07716717
DK		 3484 break;
3485 }
3486 case KVM_GET_CPUID2: {
3487 struct kvm_cpuid2 __user *cpuid_arg = argp;
3488 struct kvm_cpuid2 cpuid;
3489
3490 r = -EFAULT;
3491 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3492 goto out;
3493 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3494 cpuid_arg->entries);
07716717
DK		 3495 if (r)
3496 goto out;
3497 r = -EFAULT;
3498 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3499 goto out;
3500 r = 0;
3501 break;
3502 }
313a3dc7 3503 case KVM_GET_MSRS:
609e36d3 3504 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3505 break;
3506 case KVM_SET_MSRS:
3507 r = msr_io(vcpu, argp, do_set_msr, 0);
3508 break;
b209749f
AK		 3509 case KVM_TPR_ACCESS_REPORTING: {
3510 struct kvm_tpr_access_ctl tac;
3511
3512 r = -EFAULT;
3513 if (copy_from_user(&tac, argp, sizeof tac))
3514 goto out;
3515 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3516 if (r)
3517 goto out;
3518 r = -EFAULT;
3519 if (copy_to_user(argp, &tac, sizeof tac))
3520 goto out;
3521 r = 0;
3522 break;
3523 };
b93463aa
AK		 3524 case KVM_SET_VAPIC_ADDR: {
3525 struct kvm_vapic_addr va;
7301d6ab 3526 int idx;
b93463aa
AK		 3527
3528 r = -EINVAL;
35754c98 3529 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3530 goto out;
3531 r = -EFAULT;
3532 if (copy_from_user(&va, argp, sizeof va))
3533 goto out;
7301d6ab 3534 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3535 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3536 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3537 break;
3538 }
890ca9ae
HY		 3539 case KVM_X86_SETUP_MCE: {
3540 u64 mcg_cap;
3541
3542 r = -EFAULT;
3543 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3544 goto out;
3545 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3546 break;
3547 }
3548 case KVM_X86_SET_MCE: {
3549 struct kvm_x86_mce mce;
3550
3551 r = -EFAULT;
3552 if (copy_from_user(&mce, argp, sizeof mce))
3553 goto out;
3554 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3555 break;
3556 }
3cfc3092
JK		 3557 case KVM_GET_VCPU_EVENTS: {
3558 struct kvm_vcpu_events events;
3559
3560 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3561
3562 r = -EFAULT;
3563 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3564 break;
3565 r = 0;
3566 break;
3567 }
3568 case KVM_SET_VCPU_EVENTS: {
3569 struct kvm_vcpu_events events;
3570
3571 r = -EFAULT;
3572 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3573 break;
3574
3575 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3576 break;
3577 }
a1efbe77
JK		 3578 case KVM_GET_DEBUGREGS: {
3579 struct kvm_debugregs dbgregs;
3580
3581 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3582
3583 r = -EFAULT;
3584 if (copy_to_user(argp, &dbgregs,
3585 sizeof(struct kvm_debugregs)))
3586 break;
3587 r = 0;
3588 break;
3589 }
3590 case KVM_SET_DEBUGREGS: {
3591 struct kvm_debugregs dbgregs;
3592
3593 r = -EFAULT;
3594 if (copy_from_user(&dbgregs, argp,
3595 sizeof(struct kvm_debugregs)))
3596 break;
3597
3598 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3599 break;
3600 }
2d5b5a66 3601 case KVM_GET_XSAVE: {
d1ac91d8 3602 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3603 r = -ENOMEM;
d1ac91d8 3604 if (!u.xsave)
2d5b5a66
SY		 3605 break;
3606
d1ac91d8 3607 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3608
3609 r = -EFAULT;
d1ac91d8 3610 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3611 break;
3612 r = 0;
3613 break;
3614 }
3615 case KVM_SET_XSAVE: {
ff5c2c03 3616 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3617 if (IS_ERR(u.xsave))
3618 return PTR_ERR(u.xsave);
2d5b5a66 3619
d1ac91d8 3620 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3621 break;
3622 }
3623 case KVM_GET_XCRS: {
d1ac91d8 3624 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3625 r = -ENOMEM;
d1ac91d8 3626 if (!u.xcrs)
2d5b5a66
SY		 3627 break;
3628
d1ac91d8 3629 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3630
3631 r = -EFAULT;
d1ac91d8 3632 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3633 sizeof(struct kvm_xcrs)))
3634 break;
3635 r = 0;
3636 break;
3637 }
3638 case KVM_SET_XCRS: {
ff5c2c03 3639 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3640 if (IS_ERR(u.xcrs))
3641 return PTR_ERR(u.xcrs);
2d5b5a66 3642
d1ac91d8 3643 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3644 break;
3645 }
92a1f12d
JR		 3646 case KVM_SET_TSC_KHZ: {
3647 u32 user_tsc_khz;
3648
3649 r = -EINVAL;
92a1f12d
JR		 3650 user_tsc_khz = (u32)arg;
3651
3652 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3653 goto out;
3654
cc578287
ZA		 3655 if (user_tsc_khz == 0)
3656 user_tsc_khz = tsc_khz;
3657
381d585c
HZ		 3658 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3659 r = 0;
92a1f12d 3660
92a1f12d
JR		 3661 goto out;
3662 }
3663 case KVM_GET_TSC_KHZ: {
cc578287 3664 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3665 goto out;
3666 }
1c0b28c2
EM		 3667 case KVM_KVMCLOCK_CTRL: {
3668 r = kvm_set_guest_paused(vcpu);
3669 goto out;
3670 }
5c919412
AS		 3671 case KVM_ENABLE_CAP: {
3672 struct kvm_enable_cap cap;
3673
3674 r = -EFAULT;
3675 if (copy_from_user(&cap, argp, sizeof(cap)))
3676 goto out;
3677 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3678 break;
3679 }
313a3dc7
CO		 3680 default:
3681 r = -EINVAL;
3682 }
3683out:
d1ac91d8 3684 kfree(u.buffer);
313a3dc7
CO		 3685 return r;
3686}
3687
5b1c1493
CO		 3688int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3689{
3690 return VM_FAULT_SIGBUS;
3691}
3692
1fe779f8
CO		 3693static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3694{
3695 int ret;
3696
3697 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3698 return -EINVAL;
1fe779f8
CO		 3699 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3700 return ret;
3701}
3702
b927a3ce
SY		 3703static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3704 u64 ident_addr)
3705{
3706 kvm->arch.ept_identity_map_addr = ident_addr;
3707 return 0;
3708}
3709
1fe779f8
CO		 3710static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3711 u32 kvm_nr_mmu_pages)
3712{
3713 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3714 return -EINVAL;
3715
79fac95e 3716 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3717
3718 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3719 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3720
79fac95e 3721 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3722 return 0;
3723}
3724
3725static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3726{
39de71ec 3727 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3728}
3729
1fe779f8
CO		 3730static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3731{
90bca052 3732 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3733 int r;
3734
3735 r = 0;
3736 switch (chip->chip_id) {
3737 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3738 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3739 sizeof(struct kvm_pic_state));
3740 break;
3741 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3742 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 3743 sizeof(struct kvm_pic_state));
3744 break;
3745 case KVM_IRQCHIP_IOAPIC:
33392b49 3746 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3747 break;
3748 default:
3749 r = -EINVAL;
3750 break;
3751 }
3752 return r;
3753}
3754
3755static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3756{
90bca052 3757 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3758 int r;
3759
3760 r = 0;
3761 switch (chip->chip_id) {
3762 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 3763 spin_lock(&pic->lock);
3764 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 3765 sizeof(struct kvm_pic_state));
90bca052 3766 spin_unlock(&pic->lock);
1fe779f8
CO		 3767 break;
3768 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 3769 spin_lock(&pic->lock);
3770 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 3771 sizeof(struct kvm_pic_state));
90bca052 3772 spin_unlock(&pic->lock);
1fe779f8
CO		 3773 break;
3774 case KVM_IRQCHIP_IOAPIC:
33392b49 3775 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3776 break;
3777 default:
3778 r = -EINVAL;
3779 break;
3780 }
90bca052 3781 kvm_pic_update_irq(pic);
1fe779f8
CO		 3782 return r;
3783}
3784
e0f63cb9
SY		 3785static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3786{
34f3941c
RK		 3787 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3788
3789 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3790
3791 mutex_lock(&kps->lock);
3792 memcpy(ps, &kps->channels, sizeof(*ps));
3793 mutex_unlock(&kps->lock);
2da29bcc 3794 return 0;
e0f63cb9
SY		 3795}
3796
3797static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3798{
0185604c 3799 int i;
09edea72
RK		 3800 struct kvm_pit *pit = kvm->arch.vpit;
3801
3802 mutex_lock(&pit->pit_state.lock);
34f3941c 3803 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3804 for (i = 0; i < 3; i++)
09edea72
RK		 3805 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3806 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3807 return 0;
e9f42757
BK		 3808}
3809
3810static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3811{
e9f42757
BK		 3812 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3813 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3814 sizeof(ps->channels));
3815 ps->flags = kvm->arch.vpit->pit_state.flags;
3816 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3817 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3818 return 0;
e9f42757
BK		 3819}
3820
3821static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3822{
2da29bcc 3823 int start = 0;
0185604c 3824 int i;
e9f42757 3825 u32 prev_legacy, cur_legacy;
09edea72
RK		 3826 struct kvm_pit *pit = kvm->arch.vpit;
3827
3828 mutex_lock(&pit->pit_state.lock);
3829 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3830 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3831 if (!prev_legacy && cur_legacy)
3832 start = 1;
09edea72
RK		 3833 memcpy(&pit->pit_state.channels, &ps->channels,
3834 sizeof(pit->pit_state.channels));
3835 pit->pit_state.flags = ps->flags;
0185604c 3836 for (i = 0; i < 3; i++)
09edea72 3837 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3838 start && i == 0);
09edea72 3839 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3840 return 0;
e0f63cb9
SY		 3841}
3842
52d939a0
MT		 3843static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3844 struct kvm_reinject_control *control)
3845{
71474e2f
RK		 3846 struct kvm_pit *pit = kvm->arch.vpit;
3847
3848 if (!pit)
52d939a0 3849 return -ENXIO;
b39c90b6 3850
71474e2f
RK		 3851 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3852 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3853 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3854 */
3855 mutex_lock(&pit->pit_state.lock);
3856 kvm_pit_set_reinject(pit, control->pit_reinject);
3857 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3858
52d939a0
MT		 3859 return 0;
3860}
3861
95d4c16c 3862/**
60c34612
TY		 3863 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3864 * @kvm: kvm instance
3865 * @log: slot id and address to which we copy the log
95d4c16c 3866 *
e108ff2f
PB		 3867 * Steps 1-4 below provide general overview of dirty page logging. See
3868 * kvm_get_dirty_log_protect() function description for additional details.
3869 *
3870 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3871 * always flush the TLB (step 4) even if previous step failed and the dirty
3872 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3873 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3874 * writes will be marked dirty for next log read.
95d4c16c 3875 *
60c34612
TY		 3876 * 1. Take a snapshot of the bit and clear it if needed.
3877 * 2. Write protect the corresponding page.
e108ff2f
PB		 3878 * 3. Copy the snapshot to the userspace.
3879 * 4. Flush TLB's if needed.
5bb064dc 3880 */
60c34612 3881int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3882{
60c34612 3883 bool is_dirty = false;
e108ff2f 3884 int r;
5bb064dc 3885
79fac95e 3886 mutex_lock(&kvm->slots_lock);
5bb064dc 3887
88178fd4
KH		 3888 /*
3889 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3890 */
3891 if (kvm_x86_ops->flush_log_dirty)
3892 kvm_x86_ops->flush_log_dirty(kvm);
3893
e108ff2f 3894 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3895
3896 /*
3897 * All the TLBs can be flushed out of mmu lock, see the comments in
3898 * kvm_mmu_slot_remove_write_access().
3899 */
e108ff2f 3900 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3901 if (is_dirty)
3902 kvm_flush_remote_tlbs(kvm);
3903
79fac95e 3904 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3905 return r;
3906}
3907
aa2fbe6d
YZ		 3908int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3909 bool line_status)
23d43cf9
CD		 3910{
3911 if (!irqchip_in_kernel(kvm))
3912 return -ENXIO;
3913
3914 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3915 irq_event->irq, irq_event->level,
3916 line_status);
23d43cf9
CD		 3917 return 0;
3918}
3919
90de4a18
NA		 3920static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3921 struct kvm_enable_cap *cap)
3922{
3923 int r;
3924
3925 if (cap->flags)
3926 return -EINVAL;
3927
3928 switch (cap->cap) {
3929 case KVM_CAP_DISABLE_QUIRKS:
3930 kvm->arch.disabled_quirks = cap->args[0];
3931 r = 0;
3932 break;
49df6397
SR		 3933 case KVM_CAP_SPLIT_IRQCHIP: {
3934 mutex_lock(&kvm->lock);
b053b2ae
SR		 3935 r = -EINVAL;
3936 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3937 goto split_irqchip_unlock;
49df6397
SR		 3938 r = -EEXIST;
3939 if (irqchip_in_kernel(kvm))
3940 goto split_irqchip_unlock;
557abc40 3941 if (kvm->created_vcpus)
49df6397
SR		 3942 goto split_irqchip_unlock;
3943 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 3944 if (r)
49df6397
SR		 3945 goto split_irqchip_unlock;
3946 /* Pairs with irqchip_in_kernel. */
3947 smp_wmb();
49776faf 3948 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 3949 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3950 r = 0;
3951split_irqchip_unlock:
3952 mutex_unlock(&kvm->lock);
3953 break;
3954 }
37131313
RK		 3955 case KVM_CAP_X2APIC_API:
3956 r = -EINVAL;
3957 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
3958 break;
3959
3960 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
3961 kvm->arch.x2apic_format = true;
c519265f
RK		 3962 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
3963 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 3964
3965 r = 0;
3966 break;
90de4a18
NA		 3967 default:
3968 r = -EINVAL;
3969 break;
3970 }
3971 return r;
3972}
3973
1fe779f8
CO		 3974long kvm_arch_vm_ioctl(struct file *filp,
3975 unsigned int ioctl, unsigned long arg)
3976{
3977 struct kvm *kvm = filp->private_data;
3978 void __user *argp = (void __user *)arg;
367e1319 3979 int r = -ENOTTY;
f0d66275
DH		 3980 /*
3981 * This union makes it completely explicit to gcc-3.x
3982 * that these two variables' stack usage should be
3983 * combined, not added together.
3984 */
3985 union {
3986 struct kvm_pit_state ps;
e9f42757 3987 struct kvm_pit_state2 ps2;
c5ff41ce 3988 struct kvm_pit_config pit_config;
f0d66275 3989 } u;
1fe779f8
CO		 3990
3991 switch (ioctl) {
3992 case KVM_SET_TSS_ADDR:
3993 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3994 break;
b927a3ce
SY		 3995 case KVM_SET_IDENTITY_MAP_ADDR: {
3996 u64 ident_addr;
3997
3998 r = -EFAULT;
3999 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
4000 goto out;
4001 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 4002 break;
4003 }
1fe779f8
CO		 4004 case KVM_SET_NR_MMU_PAGES:
4005 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4006 break;
4007 case KVM_GET_NR_MMU_PAGES:
4008 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4009 break;
3ddea128 4010 case KVM_CREATE_IRQCHIP: {
3ddea128 4011 mutex_lock(&kvm->lock);
09941366 4012
3ddea128 4013 r = -EEXIST;
35e6eaa3 4014 if (irqchip_in_kernel(kvm))
3ddea128 4015 goto create_irqchip_unlock;
09941366 4016
3e515705 4017 r = -EINVAL;
557abc40 4018 if (kvm->created_vcpus)
3e515705 4019 goto create_irqchip_unlock;
09941366
RK		 4020
4021 r = kvm_pic_init(kvm);
4022 if (r)
3ddea128 4023 goto create_irqchip_unlock;
09941366
RK		 4024
4025 r = kvm_ioapic_init(kvm);
4026 if (r) {
09941366 4027 kvm_pic_destroy(kvm);
3ddea128 4028 goto create_irqchip_unlock;
09941366
RK		 4029 }
4030
399ec807
AK		 4031 r = kvm_setup_default_irq_routing(kvm);
4032 if (r) {
72bb2fcd 4033 kvm_ioapic_destroy(kvm);
09941366 4034 kvm_pic_destroy(kvm);
71ba994c 4035 goto create_irqchip_unlock;
399ec807 4036 }
49776faf 4037 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4038 smp_wmb();
49776faf 4039 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4040 create_irqchip_unlock:
4041 mutex_unlock(&kvm->lock);
1fe779f8 4042 break;
3ddea128 4043 }
7837699f 4044 case KVM_CREATE_PIT:
c5ff41ce
JK		 4045 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4046 goto create_pit;
4047 case KVM_CREATE_PIT2:
4048 r = -EFAULT;
4049 if (copy_from_user(&u.pit_config, argp,
4050 sizeof(struct kvm_pit_config)))
4051 goto out;
4052 create_pit:
250715a6 4053 mutex_lock(&kvm->lock);
269e05e4
AK		 4054 r = -EEXIST;
4055 if (kvm->arch.vpit)
4056 goto create_pit_unlock;
7837699f 4057 r = -ENOMEM;
c5ff41ce 4058 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4059 if (kvm->arch.vpit)
4060 r = 0;
269e05e4 4061 create_pit_unlock:
250715a6 4062 mutex_unlock(&kvm->lock);
7837699f 4063 break;
1fe779f8
CO		 4064 case KVM_GET_IRQCHIP: {
4065 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4066 struct kvm_irqchip *chip;
1fe779f8 4067
ff5c2c03
SL		 4068 chip = memdup_user(argp, sizeof(*chip));
4069 if (IS_ERR(chip)) {
4070 r = PTR_ERR(chip);
1fe779f8 4071 goto out;
ff5c2c03
SL		 4072 }
4073
1fe779f8 4074 r = -ENXIO;
826da321 4075 if (!irqchip_kernel(kvm))
f0d66275
DH		 4076 goto get_irqchip_out;
4077 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4078 if (r)
f0d66275 4079 goto get_irqchip_out;
1fe779f8 4080 r = -EFAULT;
f0d66275
DH		 4081 if (copy_to_user(argp, chip, sizeof *chip))
4082 goto get_irqchip_out;
1fe779f8 4083 r = 0;
f0d66275
DH		 4084 get_irqchip_out:
4085 kfree(chip);
1fe779f8
CO		 4086 break;
4087 }
4088 case KVM_SET_IRQCHIP: {
4089 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4090 struct kvm_irqchip *chip;
1fe779f8 4091
ff5c2c03
SL		 4092 chip = memdup_user(argp, sizeof(*chip));
4093 if (IS_ERR(chip)) {
4094 r = PTR_ERR(chip);
1fe779f8 4095 goto out;
ff5c2c03
SL		 4096 }
4097
1fe779f8 4098 r = -ENXIO;
826da321 4099 if (!irqchip_kernel(kvm))
f0d66275
DH		 4100 goto set_irqchip_out;
4101 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4102 if (r)
f0d66275 4103 goto set_irqchip_out;
1fe779f8 4104 r = 0;
f0d66275
DH		 4105 set_irqchip_out:
4106 kfree(chip);
1fe779f8
CO		 4107 break;
4108 }
e0f63cb9 4109 case KVM_GET_PIT: {
e0f63cb9 4110 r = -EFAULT;
f0d66275 4111 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4112 goto out;
4113 r = -ENXIO;
4114 if (!kvm->arch.vpit)
4115 goto out;
f0d66275 4116 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4117 if (r)
4118 goto out;
4119 r = -EFAULT;
f0d66275 4120 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4121 goto out;
4122 r = 0;
4123 break;
4124 }
4125 case KVM_SET_PIT: {
e0f63cb9 4126 r = -EFAULT;
f0d66275 4127 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4128 goto out;
4129 r = -ENXIO;
4130 if (!kvm->arch.vpit)
4131 goto out;
f0d66275 4132 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4133 break;
4134 }
e9f42757
BK		 4135 case KVM_GET_PIT2: {
4136 r = -ENXIO;
4137 if (!kvm->arch.vpit)
4138 goto out;
4139 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4140 if (r)
4141 goto out;
4142 r = -EFAULT;
4143 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4144 goto out;
4145 r = 0;
4146 break;
4147 }
4148 case KVM_SET_PIT2: {
4149 r = -EFAULT;
4150 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4151 goto out;
4152 r = -ENXIO;
4153 if (!kvm->arch.vpit)
4154 goto out;
4155 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4156 break;
4157 }
52d939a0
MT		 4158 case KVM_REINJECT_CONTROL: {
4159 struct kvm_reinject_control control;
4160 r = -EFAULT;
4161 if (copy_from_user(&control, argp, sizeof(control)))
4162 goto out;
4163 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4164 break;
4165 }
d71ba788
PB		 4166 case KVM_SET_BOOT_CPU_ID:
4167 r = 0;
4168 mutex_lock(&kvm->lock);
557abc40 4169 if (kvm->created_vcpus)
d71ba788
PB		 4170 r = -EBUSY;
4171 else
4172 kvm->arch.bsp_vcpu_id = arg;
4173 mutex_unlock(&kvm->lock);
4174 break;
ffde22ac
ES		 4175 case KVM_XEN_HVM_CONFIG: {
4176 r = -EFAULT;
4177 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4178 sizeof(struct kvm_xen_hvm_config)))
4179 goto out;
4180 r = -EINVAL;
4181 if (kvm->arch.xen_hvm_config.flags)
4182 goto out;
4183 r = 0;
4184 break;
4185 }
afbcf7ab 4186 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4187 struct kvm_clock_data user_ns;
4188 u64 now_ns;
afbcf7ab
GC		 4189
4190 r = -EFAULT;
4191 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4192 goto out;
4193
4194 r = -EINVAL;
4195 if (user_ns.flags)
4196 goto out;
4197
4198 r = 0;
0bc48bea
RK		 4199 /*
4200 * TODO: userspace has to take care of races with VCPU_RUN, so
4201 * kvm_gen_update_masterclock() can be cut down to locked
4202 * pvclock_update_vm_gtod_copy().
4203 */
4204 kvm_gen_update_masterclock(kvm);
e891a32e 4205 now_ns = get_kvmclock_ns(kvm);
108b249c 4206 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4207 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4208 break;
4209 }
4210 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4211 struct kvm_clock_data user_ns;
4212 u64 now_ns;
4213
e891a32e 4214 now_ns = get_kvmclock_ns(kvm);
108b249c 4215 user_ns.clock = now_ns;
e3fd9a93 4216 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4217 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4218
4219 r = -EFAULT;
4220 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4221 goto out;
4222 r = 0;
4223 break;
4224 }
90de4a18
NA		 4225 case KVM_ENABLE_CAP: {
4226 struct kvm_enable_cap cap;
afbcf7ab 4227
90de4a18
NA		 4228 r = -EFAULT;
4229 if (copy_from_user(&cap, argp, sizeof(cap)))
4230 goto out;
4231 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4232 break;
4233 }
1fe779f8 4234 default:
ad6260da 4235 r = -ENOTTY;
1fe779f8
CO		 4236 }
4237out:
4238 return r;
4239}
4240
a16b043c 4241static void kvm_init_msr_list(void)
043405e1
CO		 4242{
4243 u32 dummy[2];
4244 unsigned i, j;
4245
62ef68bb 4246 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4247 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4248 continue;
93c4adc7
PB		 4249
4250 /*
4251 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4252 * to the guests in some cases.
93c4adc7
PB		 4253 */
4254 switch (msrs_to_save[i]) {
4255 case MSR_IA32_BNDCFGS:
4256 if (!kvm_x86_ops->mpx_supported())
4257 continue;
4258 break;
9dbe6cf9
PB		 4259 case MSR_TSC_AUX:
4260 if (!kvm_x86_ops->rdtscp_supported())
4261 continue;
4262 break;
93c4adc7
PB		 4263 default:
4264 break;
4265 }
4266
043405e1
CO		 4267 if (j < i)
4268 msrs_to_save[j] = msrs_to_save[i];
4269 j++;
4270 }
4271 num_msrs_to_save = j;
62ef68bb
PB		 4272
4273 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4274 switch (emulated_msrs[i]) {
6d396b55
PB		 4275 case MSR_IA32_SMBASE:
4276 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4277 continue;
4278 break;
62ef68bb
PB		 4279 default:
4280 break;
4281 }
4282
4283 if (j < i)
4284 emulated_msrs[j] = emulated_msrs[i];
4285 j++;
4286 }
4287 num_emulated_msrs = j;
043405e1
CO		 4288}
4289
bda9020e
MT		 4290static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4291 const void *v)
bbd9b64e 4292{
70252a10
AK		 4293 int handled = 0;
4294 int n;
4295
4296 do {
4297 n = min(len, 8);
bce87cce 4298 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4299 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4300 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4301 break;
4302 handled += n;
4303 addr += n;
4304 len -= n;
4305 v += n;
4306 } while (len);
bbd9b64e 4307
70252a10 4308 return handled;
bbd9b64e
CO		 4309}
4310
bda9020e 4311static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4312{
70252a10
AK		 4313 int handled = 0;
4314 int n;
4315
4316 do {
4317 n = min(len, 8);
bce87cce 4318 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4319 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4320 addr, n, v))
4321 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4322 break;
4323 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4324 handled += n;
4325 addr += n;
4326 len -= n;
4327 v += n;
4328 } while (len);
bbd9b64e 4329
70252a10 4330 return handled;
bbd9b64e
CO		 4331}
4332
2dafc6c2
GN		 4333static void kvm_set_segment(struct kvm_vcpu *vcpu,
4334 struct kvm_segment *var, int seg)
4335{
4336 kvm_x86_ops->set_segment(vcpu, var, seg);
4337}
4338
4339void kvm_get_segment(struct kvm_vcpu *vcpu,
4340 struct kvm_segment *var, int seg)
4341{
4342 kvm_x86_ops->get_segment(vcpu, var, seg);
4343}
4344
54987b7a
PB		 4345gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4346 struct x86_exception *exception)
02f59dc9
JR		 4347{
4348 gpa_t t_gpa;
02f59dc9
JR		 4349
4350 BUG_ON(!mmu_is_nested(vcpu));
4351
4352 /* NPT walks are always user-walks */
4353 access |= PFERR_USER_MASK;
54987b7a 4354 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4355
4356 return t_gpa;
4357}
4358
ab9ae313
AK		 4359gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4360 struct x86_exception *exception)
1871c602
GN		 4361{
4362 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4363 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4364}
4365
ab9ae313
AK		 4366 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4367 struct x86_exception *exception)
1871c602
GN		 4368{
4369 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4370 access |= PFERR_FETCH_MASK;
ab9ae313 4371 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4372}
4373
ab9ae313
AK		 4374gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4375 struct x86_exception *exception)
1871c602
GN		 4376{
4377 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4378 access |= PFERR_WRITE_MASK;
ab9ae313 4379 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4380}
4381
4382/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4383gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4384 struct x86_exception *exception)
1871c602 4385{
ab9ae313 4386 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4387}
4388
4389static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4390 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4391 struct x86_exception *exception)
bbd9b64e
CO		 4392{
4393 void *data = val;
10589a46 4394 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4395
4396 while (bytes) {
14dfe855 4397 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4398 exception);
bbd9b64e 4399 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4400 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4401 int ret;
4402
bcc55cba 4403 if (gpa == UNMAPPED_GVA)
ab9ae313 4404 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4405 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4406 offset, toread);
10589a46 4407 if (ret < 0) {
c3cd7ffa 4408 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4409 goto out;
4410 }
bbd9b64e 4411
77c2002e
IE		 4412 bytes -= toread;
4413 data += toread;
4414 addr += toread;
bbd9b64e 4415 }
10589a46 4416out:
10589a46 4417 return r;
bbd9b64e 4418}
77c2002e 4419
1871c602 4420/* used for instruction fetching */
0f65dd70
AK		 4421static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4422 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4423 struct x86_exception *exception)
1871c602 4424{
0f65dd70 4425 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4426 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4427 unsigned offset;
4428 int ret;
0f65dd70 4429
44583cba
PB		 4430 /* Inline kvm_read_guest_virt_helper for speed. */
4431 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4432 exception);
4433 if (unlikely(gpa == UNMAPPED_GVA))
4434 return X86EMUL_PROPAGATE_FAULT;
4435
4436 offset = addr & (PAGE_SIZE-1);
4437 if (WARN_ON(offset + bytes > PAGE_SIZE))
4438 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4439 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4440 offset, bytes);
44583cba
PB		 4441 if (unlikely(ret < 0))
4442 return X86EMUL_IO_NEEDED;
4443
4444 return X86EMUL_CONTINUE;
1871c602
GN		 4445}
4446
064aea77 4447int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4448 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4449 struct x86_exception *exception)
1871c602 4450{
0f65dd70 4451 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4452 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4453
1871c602 4454 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4455 exception);
1871c602 4456}
064aea77 4457EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4458
0f65dd70
AK		 4459static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4460 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4461 struct x86_exception *exception)
1871c602 4462{
0f65dd70 4463 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4464 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4465}
4466
7a036a6f
RK		 4467static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4468 unsigned long addr, void *val, unsigned int bytes)
4469{
4470 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4471 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4472
4473 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4474}
4475
6a4d7550 4476int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4477 gva_t addr, void *val,
2dafc6c2 4478 unsigned int bytes,
bcc55cba 4479 struct x86_exception *exception)
77c2002e 4480{
0f65dd70 4481 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4482 void *data = val;
4483 int r = X86EMUL_CONTINUE;
4484
4485 while (bytes) {
14dfe855
JR		 4486 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4487 PFERR_WRITE_MASK,
ab9ae313 4488 exception);
77c2002e
IE		 4489 unsigned offset = addr & (PAGE_SIZE-1);
4490 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4491 int ret;
4492
bcc55cba 4493 if (gpa == UNMAPPED_GVA)
ab9ae313 4494 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4495 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4496 if (ret < 0) {
c3cd7ffa 4497 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4498 goto out;
4499 }
4500
4501 bytes -= towrite;
4502 data += towrite;
4503 addr += towrite;
4504 }
4505out:
4506 return r;
4507}
6a4d7550 4508EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4509
0f89b207
TL		 4510static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4511 gpa_t gpa, bool write)
4512{
4513 /* For APIC access vmexit */
4514 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4515 return 1;
4516
4517 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4518 trace_vcpu_match_mmio(gva, gpa, write, true);
4519 return 1;
4520 }
4521
4522 return 0;
4523}
4524
af7cc7d1
XG		 4525static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4526 gpa_t *gpa, struct x86_exception *exception,
4527 bool write)
4528{
97d64b78
AK		 4529 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4530 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4531
be94f6b7
HH		 4532 /*
4533 * currently PKRU is only applied to ept enabled guest so
4534 * there is no pkey in EPT page table for L1 guest or EPT
4535 * shadow page table for L2 guest.
4536 */
97d64b78 4537 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4538 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4539 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4540 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4541 (gva & (PAGE_SIZE - 1));
4f022648 4542 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4543 return 1;
4544 }
4545
af7cc7d1
XG		 4546 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4547
4548 if (*gpa == UNMAPPED_GVA)
4549 return -1;
4550
0f89b207 4551 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4552}
4553
3200f405 4554int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4555 const void *val, int bytes)
bbd9b64e
CO		 4556{
4557 int ret;
4558
54bf36aa 4559 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4560 if (ret < 0)
bbd9b64e 4561 return 0;
0eb05bf2 4562 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4563 return 1;
4564}
4565
77d197b2
XG		 4566struct read_write_emulator_ops {
4567 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4568 int bytes);
4569 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4570 void *val, int bytes);
4571 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4572 int bytes, void *val);
4573 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4574 void *val, int bytes);
4575 bool write;
4576};
4577
4578static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4579{
4580 if (vcpu->mmio_read_completed) {
77d197b2 4581 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4582 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4583 vcpu->mmio_read_completed = 0;
4584 return 1;
4585 }
4586
4587 return 0;
4588}
4589
4590static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4591 void *val, int bytes)
4592{
54bf36aa 4593 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4594}
4595
4596static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4597 void *val, int bytes)
4598{
4599 return emulator_write_phys(vcpu, gpa, val, bytes);
4600}
4601
4602static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4603{
4604 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4605 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4606}
4607
4608static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4609 void *val, int bytes)
4610{
4611 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4612 return X86EMUL_IO_NEEDED;
4613}
4614
4615static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4616 void *val, int bytes)
4617{
f78146b0
AK		 4618 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4619
87da7e66 4620 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4621 return X86EMUL_CONTINUE;
4622}
4623
0fbe9b0b 4624static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4625 .read_write_prepare = read_prepare,
4626 .read_write_emulate = read_emulate,
4627 .read_write_mmio = vcpu_mmio_read,
4628 .read_write_exit_mmio = read_exit_mmio,
4629};
4630
0fbe9b0b 4631static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4632 .read_write_emulate = write_emulate,
4633 .read_write_mmio = write_mmio,
4634 .read_write_exit_mmio = write_exit_mmio,
4635 .write = true,
4636};
4637
22388a3c
XG		 4638static int emulator_read_write_onepage(unsigned long addr, void *val,
4639 unsigned int bytes,
4640 struct x86_exception *exception,
4641 struct kvm_vcpu *vcpu,
0fbe9b0b 4642 const struct read_write_emulator_ops *ops)
bbd9b64e 4643{
af7cc7d1
XG		 4644 gpa_t gpa;
4645 int handled, ret;
22388a3c 4646 bool write = ops->write;
f78146b0 4647 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4648 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4649
4650 /*
4651 * If the exit was due to a NPF we may already have a GPA.
4652 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4653 * Note, this cannot be used on string operations since string
4654 * operation using rep will only have the initial GPA from the NPF
4655 * occurred.
4656 */
4657 if (vcpu->arch.gpa_available &&
4658 emulator_can_use_gpa(ctxt) &&
4659 vcpu_is_mmio_gpa(vcpu, addr, exception->address, write) &&
4660 (addr & ~PAGE_MASK) == (exception->address & ~PAGE_MASK)) {
4661 gpa = exception->address;
4662 goto mmio;
4663 }
10589a46 4664
22388a3c 4665 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4666
af7cc7d1 4667 if (ret < 0)
bbd9b64e 4668 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4669
4670 /* For APIC access vmexit */
af7cc7d1 4671 if (ret)
bbd9b64e
CO		 4672 goto mmio;
4673
22388a3c 4674 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4675 return X86EMUL_CONTINUE;
4676
4677mmio:
4678 /*
4679 * Is this MMIO handled locally?
4680 */
22388a3c 4681 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4682 if (handled == bytes)
bbd9b64e 4683 return X86EMUL_CONTINUE;
bbd9b64e 4684
70252a10
AK		 4685 gpa += handled;
4686 bytes -= handled;
4687 val += handled;
4688
87da7e66
XG		 4689 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4690 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4691 frag->gpa = gpa;
4692 frag->data = val;
4693 frag->len = bytes;
f78146b0 4694 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4695}
4696
52eb5a6d
XL		 4697static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4698 unsigned long addr,
22388a3c
XG		 4699 void *val, unsigned int bytes,
4700 struct x86_exception *exception,
0fbe9b0b 4701 const struct read_write_emulator_ops *ops)
bbd9b64e 4702{
0f65dd70 4703 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4704 gpa_t gpa;
4705 int rc;
4706
4707 if (ops->read_write_prepare &&
4708 ops->read_write_prepare(vcpu, val, bytes))
4709 return X86EMUL_CONTINUE;
4710
4711 vcpu->mmio_nr_fragments = 0;
0f65dd70 4712
bbd9b64e
CO		 4713 /* Crossing a page boundary? */
4714 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4715 int now;
bbd9b64e
CO		 4716
4717 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4718 rc = emulator_read_write_onepage(addr, val, now, exception,
4719 vcpu, ops);
4720
bbd9b64e
CO		 4721 if (rc != X86EMUL_CONTINUE)
4722 return rc;
4723 addr += now;
bac15531
NA		 4724 if (ctxt->mode != X86EMUL_MODE_PROT64)
4725 addr = (u32)addr;
bbd9b64e
CO		 4726 val += now;
4727 bytes -= now;
4728 }
22388a3c 4729
f78146b0
AK		 4730 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4731 vcpu, ops);
4732 if (rc != X86EMUL_CONTINUE)
4733 return rc;
4734
4735 if (!vcpu->mmio_nr_fragments)
4736 return rc;
4737
4738 gpa = vcpu->mmio_fragments[0].gpa;
4739
4740 vcpu->mmio_needed = 1;
4741 vcpu->mmio_cur_fragment = 0;
4742
87da7e66 4743 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4744 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4745 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4746 vcpu->run->mmio.phys_addr = gpa;
4747
4748 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4749}
4750
4751static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4752 unsigned long addr,
4753 void *val,
4754 unsigned int bytes,
4755 struct x86_exception *exception)
4756{
4757 return emulator_read_write(ctxt, addr, val, bytes,
4758 exception, &read_emultor);
4759}
4760
52eb5a6d 4761static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4762 unsigned long addr,
4763 const void *val,
4764 unsigned int bytes,
4765 struct x86_exception *exception)
4766{
4767 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4768 exception, &write_emultor);
bbd9b64e 4769}
bbd9b64e 4770
daea3e73
AK		 4771#define CMPXCHG_TYPE(t, ptr, old, new) \
4772 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4773
4774#ifdef CONFIG_X86_64
4775# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4776#else
4777# define CMPXCHG64(ptr, old, new) \
9749a6c0 4778 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4779#endif
4780
0f65dd70
AK		 4781static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4782 unsigned long addr,
bbd9b64e
CO		 4783 const void *old,
4784 const void *new,
4785 unsigned int bytes,
0f65dd70 4786 struct x86_exception *exception)
bbd9b64e 4787{
0f65dd70 4788 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4789 gpa_t gpa;
4790 struct page *page;
4791 char *kaddr;
4792 bool exchanged;
2bacc55c 4793
daea3e73
AK		 4794 /* guests cmpxchg8b have to be emulated atomically */
4795 if (bytes > 8 || (bytes & (bytes - 1)))
4796 goto emul_write;
10589a46 4797
daea3e73 4798 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4799
daea3e73
AK		 4800 if (gpa == UNMAPPED_GVA ||
4801 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4802 goto emul_write;
2bacc55c 4803
daea3e73
AK		 4804 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4805 goto emul_write;
72dc67a6 4806
54bf36aa 4807 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4808 if (is_error_page(page))
c19b8bd6 4809 goto emul_write;
72dc67a6 4810
8fd75e12 4811 kaddr = kmap_atomic(page);
daea3e73
AK		 4812 kaddr += offset_in_page(gpa);
4813 switch (bytes) {
4814 case 1:
4815 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4816 break;
4817 case 2:
4818 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4819 break;
4820 case 4:
4821 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4822 break;
4823 case 8:
4824 exchanged = CMPXCHG64(kaddr, old, new);
4825 break;
4826 default:
4827 BUG();
2bacc55c 4828 }
8fd75e12 4829 kunmap_atomic(kaddr);
daea3e73
AK		 4830 kvm_release_page_dirty(page);
4831
4832 if (!exchanged)
4833 return X86EMUL_CMPXCHG_FAILED;
4834
54bf36aa 4835 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4836 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4837
4838 return X86EMUL_CONTINUE;
4a5f48f6 4839
3200f405 4840emul_write:
daea3e73 4841 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4842
0f65dd70 4843 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4844}
4845
cf8f70bf
GN		 4846static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4847{
cbfc6c91 4848 int r = 0, i;
cf8f70bf 4849
cbfc6c91
WL		 4850 for (i = 0; i < vcpu->arch.pio.count; i++) {
4851 if (vcpu->arch.pio.in)
4852 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4853 vcpu->arch.pio.size, pd);
4854 else
4855 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4856 vcpu->arch.pio.port, vcpu->arch.pio.size,
4857 pd);
4858 if (r)
4859 break;
4860 pd += vcpu->arch.pio.size;
4861 }
cf8f70bf
GN		 4862 return r;
4863}
4864
6f6fbe98
XG		 4865static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4866 unsigned short port, void *val,
4867 unsigned int count, bool in)
cf8f70bf 4868{
cf8f70bf 4869 vcpu->arch.pio.port = port;
6f6fbe98 4870 vcpu->arch.pio.in = in;
7972995b 4871 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4872 vcpu->arch.pio.size = size;
4873
4874 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4875 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4876 return 1;
4877 }
4878
4879 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4880 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4881 vcpu->run->io.size = size;
4882 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4883 vcpu->run->io.count = count;
4884 vcpu->run->io.port = port;
4885
4886 return 0;
4887}
4888
6f6fbe98
XG		 4889static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4890 int size, unsigned short port, void *val,
4891 unsigned int count)
cf8f70bf 4892{
ca1d4a9e 4893 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4894 int ret;
ca1d4a9e 4895
6f6fbe98
XG		 4896 if (vcpu->arch.pio.count)
4897 goto data_avail;
cf8f70bf 4898
cbfc6c91
WL		 4899 memset(vcpu->arch.pio_data, 0, size * count);
4900
6f6fbe98
XG		 4901 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4902 if (ret) {
4903data_avail:
4904 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4905 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4906 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4907 return 1;
4908 }
4909
cf8f70bf
GN		 4910 return 0;
4911}
4912
6f6fbe98
XG		 4913static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4914 int size, unsigned short port,
4915 const void *val, unsigned int count)
4916{
4917 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4918
4919 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4920 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4921 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4922}
4923
bbd9b64e
CO		 4924static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4925{
4926 return kvm_x86_ops->get_segment_base(vcpu, seg);
4927}
4928
3cb16fe7 4929static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4930{
3cb16fe7 4931 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4932}
4933
ae6a2375 4934static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4935{
4936 if (!need_emulate_wbinvd(vcpu))
4937 return X86EMUL_CONTINUE;
4938
4939 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4940 int cpu = get_cpu();
4941
4942 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4943 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4944 wbinvd_ipi, NULL, 1);
2eec7343 4945 put_cpu();
f5f48ee1 4946 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4947 } else
4948 wbinvd();
f5f48ee1
SY		 4949 return X86EMUL_CONTINUE;
4950}
5cb56059
JS		 4951
4952int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4953{
6affcbed
KH		 4954 kvm_emulate_wbinvd_noskip(vcpu);
4955 return kvm_skip_emulated_instruction(vcpu);
5cb56059 4956}
f5f48ee1
SY		 4957EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4958
5cb56059
JS		 4959
4960
bcaf5cc5
AK		 4961static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4962{
5cb56059 4963 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4964}
4965
52eb5a6d
XL		 4966static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4967 unsigned long *dest)
bbd9b64e 4968{
16f8a6f9 4969 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4970}
4971
52eb5a6d
XL		 4972static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4973 unsigned long value)
bbd9b64e 4974{
338dbc97 4975
717746e3 4976 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4977}
4978
52a46617 4979static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4980{
52a46617 4981 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4982}
4983
717746e3 4984static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4985{
717746e3 4986 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4987 unsigned long value;
4988
4989 switch (cr) {
4990 case 0:
4991 value = kvm_read_cr0(vcpu);
4992 break;
4993 case 2:
4994 value = vcpu->arch.cr2;
4995 break;
4996 case 3:
9f8fe504 4997 value = kvm_read_cr3(vcpu);
52a46617
GN		 4998 break;
4999 case 4:
5000 value = kvm_read_cr4(vcpu);
5001 break;
5002 case 8:
5003 value = kvm_get_cr8(vcpu);
5004 break;
5005 default:
a737f256 5006 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5007 return 0;
5008 }
5009
5010 return value;
5011}
5012
717746e3 5013static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5014{
717746e3 5015 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5016 int res = 0;
5017
52a46617
GN		 5018 switch (cr) {
5019 case 0:
49a9b07e 5020 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5021 break;
5022 case 2:
5023 vcpu->arch.cr2 = val;
5024 break;
5025 case 3:
2390218b 5026 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5027 break;
5028 case 4:
a83b29c6 5029 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5030 break;
5031 case 8:
eea1cff9 5032 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5033 break;
5034 default:
a737f256 5035 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5036 res = -1;
52a46617 5037 }
0f12244f
GN		 5038
5039 return res;
52a46617
GN		 5040}
5041
717746e3 5042static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5043{
717746e3 5044 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5045}
5046
4bff1e86 5047static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5048{
4bff1e86 5049 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5050}
5051
4bff1e86 5052static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5053{
4bff1e86 5054 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5055}
5056
1ac9d0cf
AK		 5057static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5058{
5059 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5060}
5061
5062static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5063{
5064 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5065}
5066
4bff1e86
AK		 5067static unsigned long emulator_get_cached_segment_base(
5068 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5069{
4bff1e86 5070 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5071}
5072
1aa36616
AK		 5073static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5074 struct desc_struct *desc, u32 *base3,
5075 int seg)
2dafc6c2
GN		 5076{
5077 struct kvm_segment var;
5078
4bff1e86 5079 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5080 *selector = var.selector;
2dafc6c2 5081
378a8b09
GN		 5082 if (var.unusable) {
5083 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5084 if (base3)
5085 *base3 = 0;
2dafc6c2 5086 return false;
378a8b09 5087 }
2dafc6c2
GN		 5088
5089 if (var.g)
5090 var.limit >>= 12;
5091 set_desc_limit(desc, var.limit);
5092 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5093#ifdef CONFIG_X86_64
5094 if (base3)
5095 *base3 = var.base >> 32;
5096#endif
2dafc6c2
GN		 5097 desc->type = var.type;
5098 desc->s = var.s;
5099 desc->dpl = var.dpl;
5100 desc->p = var.present;
5101 desc->avl = var.avl;
5102 desc->l = var.l;
5103 desc->d = var.db;
5104 desc->g = var.g;
5105
5106 return true;
5107}
5108
1aa36616
AK		 5109static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5110 struct desc_struct *desc, u32 base3,
5111 int seg)
2dafc6c2 5112{
4bff1e86 5113 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5114 struct kvm_segment var;
5115
1aa36616 5116 var.selector = selector;
2dafc6c2 5117 var.base = get_desc_base(desc);
5601d05b
GN		 5118#ifdef CONFIG_X86_64
5119 var.base |= ((u64)base3) << 32;
5120#endif
2dafc6c2
GN		 5121 var.limit = get_desc_limit(desc);
5122 if (desc->g)
5123 var.limit = (var.limit << 12) | 0xfff;
5124 var.type = desc->type;
2dafc6c2
GN		 5125 var.dpl = desc->dpl;
5126 var.db = desc->d;
5127 var.s = desc->s;
5128 var.l = desc->l;
5129 var.g = desc->g;
5130 var.avl = desc->avl;
5131 var.present = desc->p;
5132 var.unusable = !var.present;
5133 var.padding = 0;
5134
5135 kvm_set_segment(vcpu, &var, seg);
5136 return;
5137}
5138
717746e3
AK		 5139static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5140 u32 msr_index, u64 *pdata)
5141{
609e36d3
PB		 5142 struct msr_data msr;
5143 int r;
5144
5145 msr.index = msr_index;
5146 msr.host_initiated = false;
5147 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5148 if (r)
5149 return r;
5150
5151 *pdata = msr.data;
5152 return 0;
717746e3
AK		 5153}
5154
5155static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5156 u32 msr_index, u64 data)
5157{
8fe8ab46
WA		 5158 struct msr_data msr;
5159
5160 msr.data = data;
5161 msr.index = msr_index;
5162 msr.host_initiated = false;
5163 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5164}
5165
64d60670
PB		 5166static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5167{
5168 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5169
5170 return vcpu->arch.smbase;
5171}
5172
5173static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5174{
5175 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5176
5177 vcpu->arch.smbase = smbase;
5178}
5179
67f4d428
NA		 5180static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5181 u32 pmc)
5182{
c6702c9d 5183 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5184}
5185
222d21aa
AK		 5186static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5187 u32 pmc, u64 *pdata)
5188{
c6702c9d 5189 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5190}
5191
6c3287f7
AK		 5192static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5193{
5194 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5195}
5196
5037f6f3
AK		 5197static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5198{
5199 preempt_disable();
5197b808 5200 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5201}
5202
5203static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5204{
5205 preempt_enable();
5206}
5207
2953538e 5208static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5209 struct x86_instruction_info *info,
c4f035c6
AK		 5210 enum x86_intercept_stage stage)
5211{
2953538e 5212 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5213}
5214
0017f93a 5215static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5216 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5217{
0017f93a 5218 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5219}
5220
dd856efa
AK		 5221static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5222{
5223 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5224}
5225
5226static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5227{
5228 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5229}
5230
801806d9
NA		 5231static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5232{
5233 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5234}
5235
6ed071f0
LP		 5236static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5237{
5238 return emul_to_vcpu(ctxt)->arch.hflags;
5239}
5240
5241static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5242{
5243 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5244}
5245
0225fb50 5246static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5247 .read_gpr = emulator_read_gpr,
5248 .write_gpr = emulator_write_gpr,
1871c602 5249 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5250 .write_std = kvm_write_guest_virt_system,
7a036a6f 5251 .read_phys = kvm_read_guest_phys_system,
1871c602 5252 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5253 .read_emulated = emulator_read_emulated,
5254 .write_emulated = emulator_write_emulated,
5255 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5256 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5257 .pio_in_emulated = emulator_pio_in_emulated,
5258 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5259 .get_segment = emulator_get_segment,
5260 .set_segment = emulator_set_segment,
5951c442 5261 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5262 .get_gdt = emulator_get_gdt,
160ce1f1 5263 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5264 .set_gdt = emulator_set_gdt,
5265 .set_idt = emulator_set_idt,
52a46617
GN		 5266 .get_cr = emulator_get_cr,
5267 .set_cr = emulator_set_cr,
9c537244 5268 .cpl = emulator_get_cpl,
35aa5375
GN		 5269 .get_dr = emulator_get_dr,
5270 .set_dr = emulator_set_dr,
64d60670
PB		 5271 .get_smbase = emulator_get_smbase,
5272 .set_smbase = emulator_set_smbase,
717746e3
AK		 5273 .set_msr = emulator_set_msr,
5274 .get_msr = emulator_get_msr,
67f4d428 5275 .check_pmc = emulator_check_pmc,
222d21aa 5276 .read_pmc = emulator_read_pmc,
6c3287f7 5277 .halt = emulator_halt,
bcaf5cc5 5278 .wbinvd = emulator_wbinvd,
d6aa1000 5279 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5280 .get_fpu = emulator_get_fpu,
5281 .put_fpu = emulator_put_fpu,
c4f035c6 5282 .intercept = emulator_intercept,
bdb42f5a 5283 .get_cpuid = emulator_get_cpuid,
801806d9 5284 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5285 .get_hflags = emulator_get_hflags,
5286 .set_hflags = emulator_set_hflags,
bbd9b64e
CO		 5287};
5288
95cb2295
GN		 5289static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5290{
37ccdcbe 5291 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5292 /*
5293 * an sti; sti; sequence only disable interrupts for the first
5294 * instruction. So, if the last instruction, be it emulated or
5295 * not, left the system with the INT_STI flag enabled, it
5296 * means that the last instruction is an sti. We should not
5297 * leave the flag on in this case. The same goes for mov ss
5298 */
37ccdcbe
PB		 5299 if (int_shadow & mask)
5300 mask = 0;
6addfc42 5301 if (unlikely(int_shadow || mask)) {
95cb2295 5302 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5303 if (!mask)
5304 kvm_make_request(KVM_REQ_EVENT, vcpu);
5305 }
95cb2295
GN		 5306}
5307
ef54bcfe 5308static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5309{
5310 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5311 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5312 return kvm_propagate_fault(vcpu, &ctxt->exception);
5313
5314 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5315 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5316 ctxt->exception.error_code);
54b8486f 5317 else
da9cb575 5318 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5319 return false;
54b8486f
GN		 5320}
5321
8ec4722d
MG		 5322static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5323{
adf52235 5324 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5325 int cs_db, cs_l;
5326
8ec4722d
MG		 5327 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5328
adf52235 5329 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5330 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5331
adf52235
TY		 5332 ctxt->eip = kvm_rip_read(vcpu);
5333 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5334 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5335 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5336 cs_db ? X86EMUL_MODE_PROT32 :
5337 X86EMUL_MODE_PROT16;
a584539b 5338 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5339 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5340 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5341
dd856efa 5342 init_decode_cache(ctxt);
7ae441ea 5343 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5344}
5345
71f9833b 5346int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5347{
9d74191a 5348 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5349 int ret;
5350
5351 init_emulate_ctxt(vcpu);
5352
9dac77fa
AK		 5353 ctxt->op_bytes = 2;
5354 ctxt->ad_bytes = 2;
5355 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5356 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5357
5358 if (ret != X86EMUL_CONTINUE)
5359 return EMULATE_FAIL;
5360
9dac77fa 5361 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5362 kvm_rip_write(vcpu, ctxt->eip);
5363 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5364
5365 if (irq == NMI_VECTOR)
7460fb4a 5366 vcpu->arch.nmi_pending = 0;
63995653
MG		 5367 else
5368 vcpu->arch.interrupt.pending = false;
5369
5370 return EMULATE_DONE;
5371}
5372EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5373
6d77dbfc
GN		 5374static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5375{
fc3a9157
JR		 5376 int r = EMULATE_DONE;
5377
6d77dbfc
GN		 5378 ++vcpu->stat.insn_emulation_fail;
5379 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5380 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5381 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5382 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5383 vcpu->run->internal.ndata = 0;
5384 r = EMULATE_FAIL;
5385 }
6d77dbfc 5386 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5387
5388 return r;
6d77dbfc
GN		 5389}
5390
93c05d3e 5391static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5392 bool write_fault_to_shadow_pgtable,
5393 int emulation_type)
a6f177ef 5394{
95b3cf69 5395 gpa_t gpa = cr2;
ba049e93 5396 kvm_pfn_t pfn;
a6f177ef 5397
991eebf9
GN		 5398 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5399 return false;
5400
95b3cf69
XG		 5401 if (!vcpu->arch.mmu.direct_map) {
5402 /*
5403 * Write permission should be allowed since only
5404 * write access need to be emulated.
5405 */
5406 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5407
95b3cf69
XG		 5408 /*
5409 * If the mapping is invalid in guest, let cpu retry
5410 * it to generate fault.
5411 */
5412 if (gpa == UNMAPPED_GVA)
5413 return true;
5414 }
a6f177ef 5415
8e3d9d06
XG		 5416 /*
5417 * Do not retry the unhandleable instruction if it faults on the
5418 * readonly host memory, otherwise it will goto a infinite loop:
5419 * retry instruction -> write #PF -> emulation fail -> retry
5420 * instruction -> ...
5421 */
5422 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5423
5424 /*
5425 * If the instruction failed on the error pfn, it can not be fixed,
5426 * report the error to userspace.
5427 */
5428 if (is_error_noslot_pfn(pfn))
5429 return false;
5430
5431 kvm_release_pfn_clean(pfn);
5432
5433 /* The instructions are well-emulated on direct mmu. */
5434 if (vcpu->arch.mmu.direct_map) {
5435 unsigned int indirect_shadow_pages;
5436
5437 spin_lock(&vcpu->kvm->mmu_lock);
5438 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5439 spin_unlock(&vcpu->kvm->mmu_lock);
5440
5441 if (indirect_shadow_pages)
5442 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5443
a6f177ef 5444 return true;
8e3d9d06 5445 }
a6f177ef 5446
95b3cf69
XG		 5447 /*
5448 * if emulation was due to access to shadowed page table
5449 * and it failed try to unshadow page and re-enter the
5450 * guest to let CPU execute the instruction.
5451 */
5452 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5453
5454 /*
5455 * If the access faults on its page table, it can not
5456 * be fixed by unprotecting shadow page and it should
5457 * be reported to userspace.
5458 */
5459 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5460}
5461
1cb3f3ae
XG		 5462static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5463 unsigned long cr2, int emulation_type)
5464{
5465 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5466 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5467
5468 last_retry_eip = vcpu->arch.last_retry_eip;
5469 last_retry_addr = vcpu->arch.last_retry_addr;
5470
5471 /*
5472 * If the emulation is caused by #PF and it is non-page_table
5473 * writing instruction, it means the VM-EXIT is caused by shadow
5474 * page protected, we can zap the shadow page and retry this
5475 * instruction directly.
5476 *
5477 * Note: if the guest uses a non-page-table modifying instruction
5478 * on the PDE that points to the instruction, then we will unmap
5479 * the instruction and go to an infinite loop. So, we cache the
5480 * last retried eip and the last fault address, if we meet the eip
5481 * and the address again, we can break out of the potential infinite
5482 * loop.
5483 */
5484 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5485
5486 if (!(emulation_type & EMULTYPE_RETRY))
5487 return false;
5488
5489 if (x86_page_table_writing_insn(ctxt))
5490 return false;
5491
5492 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5493 return false;
5494
5495 vcpu->arch.last_retry_eip = ctxt->eip;
5496 vcpu->arch.last_retry_addr = cr2;
5497
5498 if (!vcpu->arch.mmu.direct_map)
5499 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5500
22368028 5501 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5502
5503 return true;
5504}
5505
716d51ab
GN		 5506static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5507static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5508
64d60670 5509static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5510{
64d60670 5511 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5512 /* This is a good place to trace that we are exiting SMM. */
5513 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5514
c43203ca
PB		 5515 /* Process a latched INIT or SMI, if any. */
5516 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5517 }
699023e2
PB		 5518
5519 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5520}
5521
5522static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5523{
5524 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5525
a584539b 5526 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5527
5528 if (changed & HF_SMM_MASK)
5529 kvm_smm_changed(vcpu);
a584539b
PB		 5530}
5531
4a1e10d5
PB		 5532static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5533 unsigned long *db)
5534{
5535 u32 dr6 = 0;
5536 int i;
5537 u32 enable, rwlen;
5538
5539 enable = dr7;
5540 rwlen = dr7 >> 16;
5541 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5542 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5543 dr6 |= (1 << i);
5544 return dr6;
5545}
5546
c8401dda 5547static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5548{
5549 struct kvm_run *kvm_run = vcpu->run;
5550
c8401dda
PB		 5551 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5552 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5553 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5554 kvm_run->debug.arch.exception = DB_VECTOR;
5555 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5556 *r = EMULATE_USER_EXIT;
5557 } else {
5558 /*
5559 * "Certain debug exceptions may clear bit 0-3. The
5560 * remaining contents of the DR6 register are never
5561 * cleared by the processor".
5562 */
5563 vcpu->arch.dr6 &= ~15;
5564 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5565 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5566 }
5567}
5568
6affcbed
KH		 5569int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5570{
5571 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5572 int r = EMULATE_DONE;
5573
5574 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5575
5576 /*
5577 * rflags is the old, "raw" value of the flags. The new value has
5578 * not been saved yet.
5579 *
5580 * This is correct even for TF set by the guest, because "the
5581 * processor will not generate this exception after the instruction
5582 * that sets the TF flag".
5583 */
5584 if (unlikely(rflags & X86_EFLAGS_TF))
5585 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5586 return r == EMULATE_DONE;
5587}
5588EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5589
4a1e10d5
PB		 5590static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5591{
4a1e10d5
PB		 5592 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5593 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5594 struct kvm_run *kvm_run = vcpu->run;
5595 unsigned long eip = kvm_get_linear_rip(vcpu);
5596 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5597 vcpu->arch.guest_debug_dr7,
5598 vcpu->arch.eff_db);
5599
5600 if (dr6 != 0) {
6f43ed01 5601 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5602 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5603 kvm_run->debug.arch.exception = DB_VECTOR;
5604 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5605 *r = EMULATE_USER_EXIT;
5606 return true;
5607 }
5608 }
5609
4161a569
NA		 5610 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5611 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5612 unsigned long eip = kvm_get_linear_rip(vcpu);
5613 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5614 vcpu->arch.dr7,
5615 vcpu->arch.db);
5616
5617 if (dr6 != 0) {
5618 vcpu->arch.dr6 &= ~15;
6f43ed01 5619 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5620 kvm_queue_exception(vcpu, DB_VECTOR);
5621 *r = EMULATE_DONE;
5622 return true;
5623 }
5624 }
5625
5626 return false;
5627}
5628
51d8b661
AP		 5629int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5630 unsigned long cr2,
dc25e89e
AP		 5631 int emulation_type,
5632 void *insn,
5633 int insn_len)
bbd9b64e 5634{
95cb2295 5635 int r;
9d74191a 5636 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5637 bool writeback = true;
93c05d3e 5638 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5639
93c05d3e
XG		 5640 /*
5641 * Clear write_fault_to_shadow_pgtable here to ensure it is
5642 * never reused.
5643 */
5644 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5645 kvm_clear_exception_queue(vcpu);
8d7d8102 5646
571008da 5647 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5648 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5649
5650 /*
5651 * We will reenter on the same instruction since
5652 * we do not set complete_userspace_io. This does not
5653 * handle watchpoints yet, those would be handled in
5654 * the emulate_ops.
5655 */
5656 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5657 return r;
5658
9d74191a
TY		 5659 ctxt->interruptibility = 0;
5660 ctxt->have_exception = false;
e0ad0b47 5661 ctxt->exception.vector = -1;
9d74191a 5662 ctxt->perm_ok = false;
bbd9b64e 5663
b51e974f 5664 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5665
9d74191a 5666 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5667
e46479f8 5668 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5669 ++vcpu->stat.insn_emulation;
1d2887e2 5670 if (r != EMULATION_OK) {
4005996e
AK		 5671 if (emulation_type & EMULTYPE_TRAP_UD)
5672 return EMULATE_FAIL;
991eebf9
GN		 5673 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5674 emulation_type))
bbd9b64e 5675 return EMULATE_DONE;
6d77dbfc
GN		 5676 if (emulation_type & EMULTYPE_SKIP)
5677 return EMULATE_FAIL;
5678 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5679 }
5680 }
5681
ba8afb6b 5682 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5683 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5684 if (ctxt->eflags & X86_EFLAGS_RF)
5685 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5686 return EMULATE_DONE;
5687 }
5688
1cb3f3ae
XG		 5689 if (retry_instruction(ctxt, cr2, emulation_type))
5690 return EMULATE_DONE;
5691
7ae441ea 5692 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5693 changes registers values during IO operation */
7ae441ea
GN		 5694 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5695 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5696 emulator_invalidate_register_cache(ctxt);
7ae441ea 5697 }
4d2179e1 5698
5cd21917 5699restart:
0f89b207
TL		 5700 /* Save the faulting GPA (cr2) in the address field */
5701 ctxt->exception.address = cr2;
5702
9d74191a 5703 r = x86_emulate_insn(ctxt);
bbd9b64e 5704
775fde86
JR		 5705 if (r == EMULATION_INTERCEPTED)
5706 return EMULATE_DONE;
5707
d2ddd1c4 5708 if (r == EMULATION_FAILED) {
991eebf9
GN		 5709 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5710 emulation_type))
c3cd7ffa
GN		 5711 return EMULATE_DONE;
5712
6d77dbfc 5713 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5714 }
5715
9d74191a 5716 if (ctxt->have_exception) {
d2ddd1c4 5717 r = EMULATE_DONE;
ef54bcfe
PB		 5718 if (inject_emulated_exception(vcpu))
5719 return r;
d2ddd1c4 5720 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5721 if (!vcpu->arch.pio.in) {
5722 /* FIXME: return into emulator if single-stepping. */
3457e419 5723 vcpu->arch.pio.count = 0;
0912c977 5724 } else {
7ae441ea 5725 writeback = false;
716d51ab
GN		 5726 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5727 }
ac0a48c3 5728 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5729 } else if (vcpu->mmio_needed) {
5730 if (!vcpu->mmio_is_write)
5731 writeback = false;
ac0a48c3 5732 r = EMULATE_USER_EXIT;
716d51ab 5733 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5734 } else if (r == EMULATION_RESTART)
5cd21917 5735 goto restart;
d2ddd1c4
GN		 5736 else
5737 r = EMULATE_DONE;
f850e2e6 5738
7ae441ea 5739 if (writeback) {
6addfc42 5740 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5741 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5742 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5743 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 5744 if (r == EMULATE_DONE &&
5745 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
5746 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 5747 if (!ctxt->have_exception ||
5748 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5749 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5750
5751 /*
5752 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5753 * do nothing, and it will be requested again as soon as
5754 * the shadow expires. But we still need to check here,
5755 * because POPF has no interrupt shadow.
5756 */
5757 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5758 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5759 } else
5760 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5761
5762 return r;
de7d789a 5763}
51d8b661 5764EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5765
cf8f70bf 5766int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5767{
cf8f70bf 5768 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5769 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5770 size, port, &val, 1);
cf8f70bf 5771 /* do not return to emulator after return from userspace */
7972995b 5772 vcpu->arch.pio.count = 0;
de7d789a
CO		 5773 return ret;
5774}
cf8f70bf 5775EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5776
8370c3d0
TL		 5777static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5778{
5779 unsigned long val;
5780
5781 /* We should only ever be called with arch.pio.count equal to 1 */
5782 BUG_ON(vcpu->arch.pio.count != 1);
5783
5784 /* For size less than 4 we merge, else we zero extend */
5785 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5786 : 0;
5787
5788 /*
5789 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5790 * the copy and tracing
5791 */
5792 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5793 vcpu->arch.pio.port, &val, 1);
5794 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5795
5796 return 1;
5797}
5798
5799int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5800{
5801 unsigned long val;
5802 int ret;
5803
5804 /* For size less than 4 we merge, else we zero extend */
5805 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5806
5807 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5808 &val, 1);
5809 if (ret) {
5810 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5811 return ret;
5812 }
5813
5814 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5815
5816 return 0;
5817}
5818EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5819
251a5fd6 5820static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5821{
0a3aee0d 5822 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5823 return 0;
8cfdc000
ZA		 5824}
5825
5826static void tsc_khz_changed(void *data)
c8076604 5827{
8cfdc000
ZA		 5828 struct cpufreq_freqs *freq = data;
5829 unsigned long khz = 0;
5830
5831 if (data)
5832 khz = freq->new;
5833 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5834 khz = cpufreq_quick_get(raw_smp_processor_id());
5835 if (!khz)
5836 khz = tsc_khz;
0a3aee0d 5837 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5838}
5839
c8076604
GH		 5840static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5841 void *data)
5842{
5843 struct cpufreq_freqs *freq = data;
5844 struct kvm *kvm;
5845 struct kvm_vcpu *vcpu;
5846 int i, send_ipi = 0;
5847
8cfdc000
ZA		 5848 /*
5849 * We allow guests to temporarily run on slowing clocks,
5850 * provided we notify them after, or to run on accelerating
5851 * clocks, provided we notify them before. Thus time never
5852 * goes backwards.
5853 *
5854 * However, we have a problem. We can't atomically update
5855 * the frequency of a given CPU from this function; it is
5856 * merely a notifier, which can be called from any CPU.
5857 * Changing the TSC frequency at arbitrary points in time
5858 * requires a recomputation of local variables related to
5859 * the TSC for each VCPU. We must flag these local variables
5860 * to be updated and be sure the update takes place with the
5861 * new frequency before any guests proceed.
5862 *
5863 * Unfortunately, the combination of hotplug CPU and frequency
5864 * change creates an intractable locking scenario; the order
5865 * of when these callouts happen is undefined with respect to
5866 * CPU hotplug, and they can race with each other. As such,
5867 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5868 * undefined; you can actually have a CPU frequency change take
5869 * place in between the computation of X and the setting of the
5870 * variable. To protect against this problem, all updates of
5871 * the per_cpu tsc_khz variable are done in an interrupt
5872 * protected IPI, and all callers wishing to update the value
5873 * must wait for a synchronous IPI to complete (which is trivial
5874 * if the caller is on the CPU already). This establishes the
5875 * necessary total order on variable updates.
5876 *
5877 * Note that because a guest time update may take place
5878 * anytime after the setting of the VCPU's request bit, the
5879 * correct TSC value must be set before the request. However,
5880 * to ensure the update actually makes it to any guest which
5881 * starts running in hardware virtualization between the set
5882 * and the acquisition of the spinlock, we must also ping the
5883 * CPU after setting the request bit.
5884 *
5885 */
5886
c8076604
GH		 5887 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5888 return 0;
5889 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5890 return 0;
8cfdc000
ZA		 5891
5892 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5893
2f303b74 5894 spin_lock(&kvm_lock);
c8076604 5895 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5896 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5897 if (vcpu->cpu != freq->cpu)
5898 continue;
c285545f 5899 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5900 if (vcpu->cpu != smp_processor_id())
8cfdc000 5901 send_ipi = 1;
c8076604
GH		 5902 }
5903 }
2f303b74 5904 spin_unlock(&kvm_lock);
c8076604
GH		 5905
5906 if (freq->old < freq->new && send_ipi) {
5907 /*
5908 * We upscale the frequency. Must make the guest
5909 * doesn't see old kvmclock values while running with
5910 * the new frequency, otherwise we risk the guest sees
5911 * time go backwards.
5912 *
5913 * In case we update the frequency for another cpu
5914 * (which might be in guest context) send an interrupt
5915 * to kick the cpu out of guest context. Next time
5916 * guest context is entered kvmclock will be updated,
5917 * so the guest will not see stale values.
5918 */
8cfdc000 5919 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5920 }
5921 return 0;
5922}
5923
5924static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5925 .notifier_call = kvmclock_cpufreq_notifier
5926};
5927
251a5fd6 5928static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 5929{
251a5fd6
SAS		 5930 tsc_khz_changed(NULL);
5931 return 0;
8cfdc000
ZA		 5932}
5933
b820cc0c
ZA		 5934static void kvm_timer_init(void)
5935{
c285545f 5936 max_tsc_khz = tsc_khz;
460dd42e 5937
b820cc0c 5938 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5939#ifdef CONFIG_CPU_FREQ
5940 struct cpufreq_policy policy;
758f588d
BP		 5941 int cpu;
5942
c285545f 5943 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5944 cpu = get_cpu();
5945 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5946 if (policy.cpuinfo.max_freq)
5947 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5948 put_cpu();
c285545f 5949#endif
b820cc0c
ZA		 5950 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5951 CPUFREQ_TRANSITION_NOTIFIER);
5952 }
c285545f 5953 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 5954
73c1b41e 5955 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 5956 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 5957}
5958
ff9d07a0
ZY		 5959static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5960
f5132b01 5961int kvm_is_in_guest(void)
ff9d07a0 5962{
086c9855 5963 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5964}
5965
5966static int kvm_is_user_mode(void)
5967{
5968 int user_mode = 3;
dcf46b94 5969
086c9855
AS		 5970 if (__this_cpu_read(current_vcpu))
5971 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5972
ff9d07a0
ZY		 5973 return user_mode != 0;
5974}
5975
5976static unsigned long kvm_get_guest_ip(void)
5977{
5978 unsigned long ip = 0;
dcf46b94 5979
086c9855
AS		 5980 if (__this_cpu_read(current_vcpu))
5981 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5982
ff9d07a0
ZY		 5983 return ip;
5984}
5985
5986static struct perf_guest_info_callbacks kvm_guest_cbs = {
5987 .is_in_guest = kvm_is_in_guest,
5988 .is_user_mode = kvm_is_user_mode,
5989 .get_guest_ip = kvm_get_guest_ip,
5990};
5991
5992void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5993{
086c9855 5994 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5995}
5996EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5997
5998void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5999{
086c9855 6000 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 6001}
6002EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6003
ce88decf
XG		 6004static void kvm_set_mmio_spte_mask(void)
6005{
6006 u64 mask;
6007 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6008
6009 /*
6010 * Set the reserved bits and the present bit of an paging-structure
6011 * entry to generate page fault with PFER.RSV = 1.
6012 */
885032b9 6013 /* Mask the reserved physical address bits. */
d1431483 6014 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6015
885032b9 6016 /* Set the present bit. */
ce88decf
XG		 6017 mask |= 1ull;
6018
6019#ifdef CONFIG_X86_64
6020 /*
6021 * If reserved bit is not supported, clear the present bit to disable
6022 * mmio page fault.
6023 */
6024 if (maxphyaddr == 52)
6025 mask &= ~1ull;
6026#endif
6027
dcdca5fe 6028 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6029}
6030
16e8d74d
MT		 6031#ifdef CONFIG_X86_64
6032static void pvclock_gtod_update_fn(struct work_struct *work)
6033{
d828199e
MT		 6034 struct kvm *kvm;
6035
6036 struct kvm_vcpu *vcpu;
6037 int i;
6038
2f303b74 6039 spin_lock(&kvm_lock);
d828199e
MT		 6040 list_for_each_entry(kvm, &vm_list, vm_list)
6041 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6042 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6043 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6044 spin_unlock(&kvm_lock);
16e8d74d
MT		 6045}
6046
6047static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6048
6049/*
6050 * Notification about pvclock gtod data update.
6051 */
6052static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6053 void *priv)
6054{
6055 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6056 struct timekeeper *tk = priv;
6057
6058 update_pvclock_gtod(tk);
6059
6060 /* disable master clock if host does not trust, or does not
6061 * use, TSC clocksource
6062 */
6063 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6064 atomic_read(&kvm_guest_has_master_clock) != 0)
6065 queue_work(system_long_wq, &pvclock_gtod_work);
6066
6067 return 0;
6068}
6069
6070static struct notifier_block pvclock_gtod_notifier = {
6071 .notifier_call = pvclock_gtod_notify,
6072};
6073#endif
6074
f8c16bba 6075int kvm_arch_init(void *opaque)
043405e1 6076{
b820cc0c 6077 int r;
6b61edf7 6078 struct kvm_x86_ops *ops = opaque;
f8c16bba 6079
f8c16bba
ZX		 6080 if (kvm_x86_ops) {
6081 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6082 r = -EEXIST;
6083 goto out;
f8c16bba
ZX		 6084 }
6085
6086 if (!ops->cpu_has_kvm_support()) {
6087 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6088 r = -EOPNOTSUPP;
6089 goto out;
f8c16bba
ZX		 6090 }
6091 if (ops->disabled_by_bios()) {
6092 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6093 r = -EOPNOTSUPP;
6094 goto out;
f8c16bba
ZX		 6095 }
6096
013f6a5d
MT		 6097 r = -ENOMEM;
6098 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6099 if (!shared_msrs) {
6100 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6101 goto out;
6102 }
6103
97db56ce
AK		 6104 r = kvm_mmu_module_init();
6105 if (r)
013f6a5d 6106 goto out_free_percpu;
97db56ce 6107
ce88decf 6108 kvm_set_mmio_spte_mask();
97db56ce 6109
f8c16bba 6110 kvm_x86_ops = ops;
920c8377 6111
7b52345e 6112 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6113 PT_DIRTY_MASK, PT64_NX_MASK, 0,
f160c7b7 6114 PT_PRESENT_MASK, 0);
b820cc0c 6115 kvm_timer_init();
c8076604 6116
ff9d07a0
ZY		 6117 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6118
d366bf7e 6119 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6120 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6121
c5cc421b 6122 kvm_lapic_init();
16e8d74d
MT		 6123#ifdef CONFIG_X86_64
6124 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6125#endif
6126
f8c16bba 6127 return 0;
56c6d28a 6128
013f6a5d
MT		 6129out_free_percpu:
6130 free_percpu(shared_msrs);
56c6d28a 6131out:
56c6d28a 6132 return r;
043405e1 6133}
8776e519 6134
f8c16bba
ZX		 6135void kvm_arch_exit(void)
6136{
cef84c30 6137 kvm_lapic_exit();
ff9d07a0
ZY		 6138 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6139
888d256e
JK		 6140 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6141 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6142 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6143 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6144#ifdef CONFIG_X86_64
6145 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6146#endif
f8c16bba 6147 kvm_x86_ops = NULL;
56c6d28a 6148 kvm_mmu_module_exit();
013f6a5d 6149 free_percpu(shared_msrs);
56c6d28a 6150}
f8c16bba 6151
5cb56059 6152int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6153{
6154 ++vcpu->stat.halt_exits;
35754c98 6155 if (lapic_in_kernel(vcpu)) {
a4535290 6156 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6157 return 1;
6158 } else {
6159 vcpu->run->exit_reason = KVM_EXIT_HLT;
6160 return 0;
6161 }
6162}
5cb56059
JS		 6163EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6164
6165int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6166{
6affcbed
KH		 6167 int ret = kvm_skip_emulated_instruction(vcpu);
6168 /*
6169 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6170 * KVM_EXIT_DEBUG here.
6171 */
6172 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6173}
8776e519
HB		 6174EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6175
8ef81a9a 6176#ifdef CONFIG_X86_64
55dd00a7
MT		 6177static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6178 unsigned long clock_type)
6179{
6180 struct kvm_clock_pairing clock_pairing;
6181 struct timespec ts;
80fbd89c 6182 u64 cycle;
55dd00a7
MT		 6183 int ret;
6184
6185 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6186 return -KVM_EOPNOTSUPP;
6187
6188 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6189 return -KVM_EOPNOTSUPP;
6190
6191 clock_pairing.sec = ts.tv_sec;
6192 clock_pairing.nsec = ts.tv_nsec;
6193 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6194 clock_pairing.flags = 0;
6195
6196 ret = 0;
6197 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6198 sizeof(struct kvm_clock_pairing)))
6199 ret = -KVM_EFAULT;
6200
6201 return ret;
6202}
8ef81a9a 6203#endif
55dd00a7 6204
6aef266c
SV		 6205/*
6206 * kvm_pv_kick_cpu_op: Kick a vcpu.
6207 *
6208 * @apicid - apicid of vcpu to be kicked.
6209 */
6210static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6211{
24d2166b 6212 struct kvm_lapic_irq lapic_irq;
6aef266c 6213
24d2166b
R		 6214 lapic_irq.shorthand = 0;
6215 lapic_irq.dest_mode = 0;
6216 lapic_irq.dest_id = apicid;
93bbf0b8 6217 lapic_irq.msi_redir_hint = false;
6aef266c 6218
24d2166b 6219 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6220 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6221}
6222
d62caabb
AS		 6223void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6224{
6225 vcpu->arch.apicv_active = false;
6226 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6227}
6228
8776e519
HB		 6229int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6230{
6231 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6232 int op_64_bit, r;
8776e519 6233
6affcbed 6234 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6235
55cd8e5a
GN		 6236 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6237 return kvm_hv_hypercall(vcpu);
6238
5fdbf976
MT		 6239 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6240 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6241 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6242 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6243 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6244
229456fc 6245 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6246
a449c7aa
NA		 6247 op_64_bit = is_64_bit_mode(vcpu);
6248 if (!op_64_bit) {
8776e519
HB		 6249 nr &= 0xFFFFFFFF;
6250 a0 &= 0xFFFFFFFF;
6251 a1 &= 0xFFFFFFFF;
6252 a2 &= 0xFFFFFFFF;
6253 a3 &= 0xFFFFFFFF;
6254 }
6255
07708c4a
JK		 6256 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6257 ret = -KVM_EPERM;
6258 goto out;
6259 }
6260
8776e519 6261 switch (nr) {
b93463aa
AK		 6262 case KVM_HC_VAPIC_POLL_IRQ:
6263 ret = 0;
6264 break;
6aef266c
SV		 6265 case KVM_HC_KICK_CPU:
6266 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6267 ret = 0;
6268 break;
8ef81a9a 6269#ifdef CONFIG_X86_64
55dd00a7
MT		 6270 case KVM_HC_CLOCK_PAIRING:
6271 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6272 break;
8ef81a9a 6273#endif
8776e519
HB		 6274 default:
6275 ret = -KVM_ENOSYS;
6276 break;
6277 }
07708c4a 6278out:
a449c7aa
NA		 6279 if (!op_64_bit)
6280 ret = (u32)ret;
5fdbf976 6281 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6282 ++vcpu->stat.hypercalls;
2f333bcb 6283 return r;
8776e519
HB		 6284}
6285EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6286
b6785def 6287static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6288{
d6aa1000 6289 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6290 char instruction[3];
5fdbf976 6291 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6292
8776e519 6293 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6294
ce2e852e
DV		 6295 return emulator_write_emulated(ctxt, rip, instruction, 3,
6296 &ctxt->exception);
8776e519
HB		 6297}
6298
851ba692 6299static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6300{
782d422b
MG		 6301 return vcpu->run->request_interrupt_window &&
6302 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6303}
6304
851ba692 6305static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6306{
851ba692
AK		 6307 struct kvm_run *kvm_run = vcpu->run;
6308
91586a3b 6309 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6310 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6311 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6312 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6313 kvm_run->ready_for_interrupt_injection =
6314 pic_in_kernel(vcpu->kvm) ||
782d422b 6315 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6316}
6317
95ba8273
GN		 6318static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6319{
6320 int max_irr, tpr;
6321
6322 if (!kvm_x86_ops->update_cr8_intercept)
6323 return;
6324
bce87cce 6325 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6326 return;
6327
d62caabb
AS		 6328 if (vcpu->arch.apicv_active)
6329 return;
6330
8db3baa2
GN		 6331 if (!vcpu->arch.apic->vapic_addr)
6332 max_irr = kvm_lapic_find_highest_irr(vcpu);
6333 else
6334 max_irr = -1;
95ba8273
GN		 6335
6336 if (max_irr != -1)
6337 max_irr >>= 4;
6338
6339 tpr = kvm_lapic_get_cr8(vcpu);
6340
6341 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6342}
6343
b6b8a145 6344static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6345{
b6b8a145
JK		 6346 int r;
6347
95ba8273 6348 /* try to reinject previous events if any */
b59bb7bd 6349 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6350 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6351 vcpu->arch.exception.has_error_code,
6352 vcpu->arch.exception.error_code);
d6e8c854
NA		 6353
6354 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6355 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6356 X86_EFLAGS_RF);
6357
6bdf0662
NA		 6358 if (vcpu->arch.exception.nr == DB_VECTOR &&
6359 (vcpu->arch.dr7 & DR7_GD)) {
6360 vcpu->arch.dr7 &= ~DR7_GD;
6361 kvm_update_dr7(vcpu);
6362 }
6363
cfcd20e5 6364 kvm_x86_ops->queue_exception(vcpu);
b6b8a145 6365 return 0;
b59bb7bd
GN		 6366 }
6367
95ba8273
GN		 6368 if (vcpu->arch.nmi_injected) {
6369 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6370 return 0;
95ba8273
GN		 6371 }
6372
6373 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6374 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6375 return 0;
6376 }
6377
6378 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6379 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6380 if (r != 0)
6381 return r;
95ba8273
GN		 6382 }
6383
6384 /* try to inject new event if pending */
c43203ca
PB		 6385 if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
6386 vcpu->arch.smi_pending = false;
ee2cd4b7 6387 enter_smm(vcpu);
c43203ca 6388 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6389 --vcpu->arch.nmi_pending;
6390 vcpu->arch.nmi_injected = true;
6391 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6392 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6393 /*
6394 * Because interrupts can be injected asynchronously, we are
6395 * calling check_nested_events again here to avoid a race condition.
6396 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6397 * proposal and current concerns. Perhaps we should be setting
6398 * KVM_REQ_EVENT only on certain events and not unconditionally?
6399 */
6400 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6401 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6402 if (r != 0)
6403 return r;
6404 }
95ba8273 6405 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6406 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6407 false);
6408 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6409 }
6410 }
ee2cd4b7 6411
b6b8a145 6412 return 0;
95ba8273
GN		 6413}
6414
7460fb4a
AK		 6415static void process_nmi(struct kvm_vcpu *vcpu)
6416{
6417 unsigned limit = 2;
6418
6419 /*
6420 * x86 is limited to one NMI running, and one NMI pending after it.
6421 * If an NMI is already in progress, limit further NMIs to just one.
6422 * Otherwise, allow two (and we'll inject the first one immediately).
6423 */
6424 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6425 limit = 1;
6426
6427 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6428 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6429 kvm_make_request(KVM_REQ_EVENT, vcpu);
6430}
6431
660a5d51
PB		 6432#define put_smstate(type, buf, offset, val) \
6433 *(type *)((buf) + (offset) - 0x7e00) = val
6434
ee2cd4b7 6435static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6436{
6437 u32 flags = 0;
6438 flags |= seg->g << 23;
6439 flags |= seg->db << 22;
6440 flags |= seg->l << 21;
6441 flags |= seg->avl << 20;
6442 flags |= seg->present << 15;
6443 flags |= seg->dpl << 13;
6444 flags |= seg->s << 12;
6445 flags |= seg->type << 8;
6446 return flags;
6447}
6448
ee2cd4b7 6449static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6450{
6451 struct kvm_segment seg;
6452 int offset;
6453
6454 kvm_get_segment(vcpu, &seg, n);
6455 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6456
6457 if (n < 3)
6458 offset = 0x7f84 + n * 12;
6459 else
6460 offset = 0x7f2c + (n - 3) * 12;
6461
6462 put_smstate(u32, buf, offset + 8, seg.base);
6463 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6464 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6465}
6466
efbb288a 6467#ifdef CONFIG_X86_64
ee2cd4b7 6468static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6469{
6470 struct kvm_segment seg;
6471 int offset;
6472 u16 flags;
6473
6474 kvm_get_segment(vcpu, &seg, n);
6475 offset = 0x7e00 + n * 16;
6476
ee2cd4b7 6477 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6478 put_smstate(u16, buf, offset, seg.selector);
6479 put_smstate(u16, buf, offset + 2, flags);
6480 put_smstate(u32, buf, offset + 4, seg.limit);
6481 put_smstate(u64, buf, offset + 8, seg.base);
6482}
efbb288a 6483#endif
660a5d51 6484
ee2cd4b7 6485static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6486{
6487 struct desc_ptr dt;
6488 struct kvm_segment seg;
6489 unsigned long val;
6490 int i;
6491
6492 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6493 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6494 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6495 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6496
6497 for (i = 0; i < 8; i++)
6498 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6499
6500 kvm_get_dr(vcpu, 6, &val);
6501 put_smstate(u32, buf, 0x7fcc, (u32)val);
6502 kvm_get_dr(vcpu, 7, &val);
6503 put_smstate(u32, buf, 0x7fc8, (u32)val);
6504
6505 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6506 put_smstate(u32, buf, 0x7fc4, seg.selector);
6507 put_smstate(u32, buf, 0x7f64, seg.base);
6508 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6509 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6510
6511 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6512 put_smstate(u32, buf, 0x7fc0, seg.selector);
6513 put_smstate(u32, buf, 0x7f80, seg.base);
6514 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6515 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6516
6517 kvm_x86_ops->get_gdt(vcpu, &dt);
6518 put_smstate(u32, buf, 0x7f74, dt.address);
6519 put_smstate(u32, buf, 0x7f70, dt.size);
6520
6521 kvm_x86_ops->get_idt(vcpu, &dt);
6522 put_smstate(u32, buf, 0x7f58, dt.address);
6523 put_smstate(u32, buf, 0x7f54, dt.size);
6524
6525 for (i = 0; i < 6; i++)
ee2cd4b7 6526 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6527
6528 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6529
6530 /* revision id */
6531 put_smstate(u32, buf, 0x7efc, 0x00020000);
6532 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6533}
6534
ee2cd4b7 6535static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6536{
6537#ifdef CONFIG_X86_64
6538 struct desc_ptr dt;
6539 struct kvm_segment seg;
6540 unsigned long val;
6541 int i;
6542
6543 for (i = 0; i < 16; i++)
6544 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6545
6546 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6547 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6548
6549 kvm_get_dr(vcpu, 6, &val);
6550 put_smstate(u64, buf, 0x7f68, val);
6551 kvm_get_dr(vcpu, 7, &val);
6552 put_smstate(u64, buf, 0x7f60, val);
6553
6554 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6555 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6556 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6557
6558 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6559
6560 /* revision id */
6561 put_smstate(u32, buf, 0x7efc, 0x00020064);
6562
6563 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6564
6565 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6566 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6567 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6568 put_smstate(u32, buf, 0x7e94, seg.limit);
6569 put_smstate(u64, buf, 0x7e98, seg.base);
6570
6571 kvm_x86_ops->get_idt(vcpu, &dt);
6572 put_smstate(u32, buf, 0x7e84, dt.size);
6573 put_smstate(u64, buf, 0x7e88, dt.address);
6574
6575 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6576 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6577 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6578 put_smstate(u32, buf, 0x7e74, seg.limit);
6579 put_smstate(u64, buf, 0x7e78, seg.base);
6580
6581 kvm_x86_ops->get_gdt(vcpu, &dt);
6582 put_smstate(u32, buf, 0x7e64, dt.size);
6583 put_smstate(u64, buf, 0x7e68, dt.address);
6584
6585 for (i = 0; i < 6; i++)
ee2cd4b7 6586 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6587#else
6588 WARN_ON_ONCE(1);
6589#endif
6590}
6591
ee2cd4b7 6592static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6593{
660a5d51 6594 struct kvm_segment cs, ds;
18c3626e 6595 struct desc_ptr dt;
660a5d51
PB		 6596 char buf[512];
6597 u32 cr0;
6598
660a5d51
PB		 6599 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6600 vcpu->arch.hflags |= HF_SMM_MASK;
6601 memset(buf, 0, 512);
6602 if (guest_cpuid_has_longmode(vcpu))
ee2cd4b7 6603 enter_smm_save_state_64(vcpu, buf);
660a5d51 6604 else
ee2cd4b7 6605 enter_smm_save_state_32(vcpu, buf);
660a5d51 6606
54bf36aa 6607 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6608
6609 if (kvm_x86_ops->get_nmi_mask(vcpu))
6610 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6611 else
6612 kvm_x86_ops->set_nmi_mask(vcpu, true);
6613
6614 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6615 kvm_rip_write(vcpu, 0x8000);
6616
6617 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6618 kvm_x86_ops->set_cr0(vcpu, cr0);
6619 vcpu->arch.cr0 = cr0;
6620
6621 kvm_x86_ops->set_cr4(vcpu, 0);
6622
18c3626e
PB		 6623 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6624 dt.address = dt.size = 0;
6625 kvm_x86_ops->set_idt(vcpu, &dt);
6626
660a5d51
PB		 6627 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6628
6629 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6630 cs.base = vcpu->arch.smbase;
6631
6632 ds.selector = 0;
6633 ds.base = 0;
6634
6635 cs.limit = ds.limit = 0xffffffff;
6636 cs.type = ds.type = 0x3;
6637 cs.dpl = ds.dpl = 0;
6638 cs.db = ds.db = 0;
6639 cs.s = ds.s = 1;
6640 cs.l = ds.l = 0;
6641 cs.g = ds.g = 1;
6642 cs.avl = ds.avl = 0;
6643 cs.present = ds.present = 1;
6644 cs.unusable = ds.unusable = 0;
6645 cs.padding = ds.padding = 0;
6646
6647 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6648 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6649 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6650 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6651 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6652 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6653
6654 if (guest_cpuid_has_longmode(vcpu))
6655 kvm_x86_ops->set_efer(vcpu, 0);
6656
6657 kvm_update_cpuid(vcpu);
6658 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6659}
6660
ee2cd4b7 6661static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6662{
6663 vcpu->arch.smi_pending = true;
6664 kvm_make_request(KVM_REQ_EVENT, vcpu);
6665}
6666
2860c4b1
PB		 6667void kvm_make_scan_ioapic_request(struct kvm *kvm)
6668{
6669 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6670}
6671
3d81bc7e 6672static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6673{
5c919412
AS		 6674 u64 eoi_exit_bitmap[4];
6675
3d81bc7e
YZ		 6676 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6677 return;
c7c9c56c 6678
6308630b 6679 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6680
b053b2ae 6681 if (irqchip_split(vcpu->kvm))
6308630b 6682 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6683 else {
76dfafd5 6684 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb 6685 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6686 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6687 }
5c919412
AS		 6688 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6689 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6690 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6691}
6692
a70656b6
RK		 6693static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6694{
6695 ++vcpu->stat.tlb_flush;
6696 kvm_x86_ops->tlb_flush(vcpu);
6697}
6698
4256f43f
TC		 6699void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6700{
c24ae0dc
TC		 6701 struct page *page = NULL;
6702
35754c98 6703 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6704 return;
6705
4256f43f
TC		 6706 if (!kvm_x86_ops->set_apic_access_page_addr)
6707 return;
6708
c24ae0dc 6709 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6710 if (is_error_page(page))
6711 return;
c24ae0dc
TC		 6712 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6713
6714 /*
6715 * Do not pin apic access page in memory, the MMU notifier
6716 * will call us again if it is migrated or swapped out.
6717 */
6718 put_page(page);
4256f43f
TC		 6719}
6720EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6721
fe71557a
TC		 6722void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6723 unsigned long address)
6724{
c24ae0dc
TC		 6725 /*
6726 * The physical address of apic access page is stored in the VMCS.
6727 * Update it when it becomes invalid.
6728 */
6729 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6730 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6731}
6732
9357d939 6733/*
362c698f 6734 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6735 * exiting to the userspace. Otherwise, the value will be returned to the
6736 * userspace.
6737 */
851ba692 6738static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6739{
6740 int r;
62a193ed
MG		 6741 bool req_int_win =
6742 dm_request_for_irq_injection(vcpu) &&
6743 kvm_cpu_accept_dm_intr(vcpu);
6744
730dca42 6745 bool req_immediate_exit = false;
b6c7a5dc 6746
2fa6e1e1 6747 if (kvm_request_pending(vcpu)) {
a8eeb04a 6748 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6749 kvm_mmu_unload(vcpu);
a8eeb04a 6750 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6751 __kvm_migrate_timers(vcpu);
d828199e
MT		 6752 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6753 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6754 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6755 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6756 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6757 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6758 if (unlikely(r))
6759 goto out;
6760 }
a8eeb04a 6761 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6762 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6763 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6764 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6765 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6766 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6767 r = 0;
6768 goto out;
6769 }
a8eeb04a 6770 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6771 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6772 r = 0;
6773 goto out;
6774 }
af585b92
GN		 6775 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6776 /* Page is swapped out. Do synthetic halt */
6777 vcpu->arch.apf.halted = true;
6778 r = 1;
6779 goto out;
6780 }
c9aaa895
GC		 6781 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6782 record_steal_time(vcpu);
64d60670
PB		 6783 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6784 process_smi(vcpu);
7460fb4a
AK		 6785 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6786 process_nmi(vcpu);
f5132b01 6787 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6788 kvm_pmu_handle_event(vcpu);
f5132b01 6789 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6790 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6791 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6792 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6793 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6794 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6795 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6796 vcpu->run->eoi.vector =
6797 vcpu->arch.pending_ioapic_eoi;
6798 r = 0;
6799 goto out;
6800 }
6801 }
3d81bc7e
YZ		 6802 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6803 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6804 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6805 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6806 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6807 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6808 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6809 r = 0;
6810 goto out;
6811 }
e516cebb
AS		 6812 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6813 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6814 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6815 r = 0;
6816 goto out;
6817 }
db397571
AS		 6818 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6819 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6820 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6821 r = 0;
6822 goto out;
6823 }
f3b138c5
AS		 6824
6825 /*
6826 * KVM_REQ_HV_STIMER has to be processed after
6827 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6828 * depend on the guest clock being up-to-date
6829 */
1f4b34f8
AS		 6830 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6831 kvm_hv_process_stimers(vcpu);
2f52d58c 6832 }
b93463aa 6833
b463a6f7 6834 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 6835 ++vcpu->stat.req_event;
66450a21
JK		 6836 kvm_apic_accept_events(vcpu);
6837 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6838 r = 1;
6839 goto out;
6840 }
6841
b6b8a145
JK		 6842 if (inject_pending_event(vcpu, req_int_win) != 0)
6843 req_immediate_exit = true;
321c5658 6844 else {
c43203ca
PB		 6845 /* Enable NMI/IRQ window open exits if needed.
6846 *
6847 * SMIs have two cases: 1) they can be nested, and
6848 * then there is nothing to do here because RSM will
6849 * cause a vmexit anyway; 2) or the SMI can be pending
6850 * because inject_pending_event has completed the
6851 * injection of an IRQ or NMI from the previous vmexit,
6852 * and then we request an immediate exit to inject the SMI.
6853 */
6854 if (vcpu->arch.smi_pending && !is_smm(vcpu))
6855 req_immediate_exit = true;
321c5658
YS		 6856 if (vcpu->arch.nmi_pending)
6857 kvm_x86_ops->enable_nmi_window(vcpu);
6858 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6859 kvm_x86_ops->enable_irq_window(vcpu);
6860 }
b463a6f7
AK		 6861
6862 if (kvm_lapic_enabled(vcpu)) {
6863 update_cr8_intercept(vcpu);
6864 kvm_lapic_sync_to_vapic(vcpu);
6865 }
6866 }
6867
d8368af8
AK		 6868 r = kvm_mmu_reload(vcpu);
6869 if (unlikely(r)) {
d905c069 6870 goto cancel_injection;
d8368af8
AK		 6871 }
6872
b6c7a5dc
HB		 6873 preempt_disable();
6874
6875 kvm_x86_ops->prepare_guest_switch(vcpu);
bd7e5b08 6876 kvm_load_guest_fpu(vcpu);
b95234c8
PB		 6877
6878 /*
6879 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
6880 * IPI are then delayed after guest entry, which ensures that they
6881 * result in virtual interrupt delivery.
6882 */
6883 local_irq_disable();
6b7e2d09
XG		 6884 vcpu->mode = IN_GUEST_MODE;
6885
01b71917
MT		 6886 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6887
0f127d12 6888 /*
b95234c8 6889 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 6890 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 6891 *
6892 * 2) For APICv, we should set ->mode before checking PIR.ON. This
6893 * pairs with the memory barrier implicit in pi_test_and_set_on
6894 * (see vmx_deliver_posted_interrupt).
6895 *
6896 * 3) This also orders the write to mode from any reads to the page
6897 * tables done while the VCPU is running. Please see the comment
6898 * in kvm_flush_remote_tlbs.
6b7e2d09 6899 */
01b71917 6900 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6901
b95234c8
PB		 6902 /*
6903 * This handles the case where a posted interrupt was
6904 * notified with kvm_vcpu_kick.
6905 */
6906 if (kvm_lapic_enabled(vcpu)) {
6907 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6908 kvm_x86_ops->sync_pir_to_irr(vcpu);
6909 }
32f88400 6910
2fa6e1e1 6911 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 6912 || need_resched() || signal_pending(current)) {
6b7e2d09 6913 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6914 smp_wmb();
6c142801
AK		 6915 local_irq_enable();
6916 preempt_enable();
01b71917 6917 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6918 r = 1;
d905c069 6919 goto cancel_injection;
6c142801
AK		 6920 }
6921
fc5b7f3b
DM		 6922 kvm_load_guest_xcr0(vcpu);
6923
c43203ca
PB		 6924 if (req_immediate_exit) {
6925 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 6926 smp_send_reschedule(vcpu->cpu);
c43203ca 6927 }
d6185f20 6928
8b89fe1f
PB		 6929 trace_kvm_entry(vcpu->vcpu_id);
6930 wait_lapic_expire(vcpu);
6edaa530 6931 guest_enter_irqoff();
b6c7a5dc 6932
42dbaa5a 6933 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6934 set_debugreg(0, 7);
6935 set_debugreg(vcpu->arch.eff_db[0], 0);
6936 set_debugreg(vcpu->arch.eff_db[1], 1);
6937 set_debugreg(vcpu->arch.eff_db[2], 2);
6938 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6939 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6940 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6941 }
b6c7a5dc 6942
851ba692 6943 kvm_x86_ops->run(vcpu);
b6c7a5dc 6944
c77fb5fe
PB		 6945 /*
6946 * Do this here before restoring debug registers on the host. And
6947 * since we do this before handling the vmexit, a DR access vmexit
6948 * can (a) read the correct value of the debug registers, (b) set
6949 * KVM_DEBUGREG_WONT_EXIT again.
6950 */
6951 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 6952 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6953 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 6954 kvm_update_dr0123(vcpu);
6955 kvm_update_dr6(vcpu);
6956 kvm_update_dr7(vcpu);
6957 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 6958 }
6959
24f1e32c
FW		 6960 /*
6961 * If the guest has used debug registers, at least dr7
6962 * will be disabled while returning to the host.
6963 * If we don't have active breakpoints in the host, we don't
6964 * care about the messed up debug address registers. But if
6965 * we have some of them active, restore the old state.
6966 */
59d8eb53 6967 if (hw_breakpoint_active())
24f1e32c 6968 hw_breakpoint_restore();
42dbaa5a 6969
4ba76538 6970 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6971
6b7e2d09 6972 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6973 smp_wmb();
a547c6db 6974
fc5b7f3b
DM		 6975 kvm_put_guest_xcr0(vcpu);
6976
a547c6db 6977 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6978
6979 ++vcpu->stat.exits;
6980
f2485b3e 6981 guest_exit_irqoff();
b6c7a5dc 6982
f2485b3e 6983 local_irq_enable();
b6c7a5dc
HB		 6984 preempt_enable();
6985
f656ce01 6986 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6987
b6c7a5dc
HB		 6988 /*
6989 * Profile KVM exit RIPs:
6990 */
6991 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6992 unsigned long rip = kvm_rip_read(vcpu);
6993 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6994 }
6995
cc578287
ZA		 6996 if (unlikely(vcpu->arch.tsc_always_catchup))
6997 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6998
5cfb1d5a
MT		 6999 if (vcpu->arch.apic_attention)
7000 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7001
851ba692 7002 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7003 return r;
7004
7005cancel_injection:
7006 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7007 if (unlikely(vcpu->arch.apic_attention))
7008 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7009out:
7010 return r;
7011}
b6c7a5dc 7012
362c698f
PB		 7013static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7014{
bf9f6ac8
FW		 7015 if (!kvm_arch_vcpu_runnable(vcpu) &&
7016 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7017 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7018 kvm_vcpu_block(vcpu);
7019 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7020
7021 if (kvm_x86_ops->post_block)
7022 kvm_x86_ops->post_block(vcpu);
7023
9c8fd1ba
PB		 7024 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7025 return 1;
7026 }
362c698f
PB		 7027
7028 kvm_apic_accept_events(vcpu);
7029 switch(vcpu->arch.mp_state) {
7030 case KVM_MP_STATE_HALTED:
7031 vcpu->arch.pv.pv_unhalted = false;
7032 vcpu->arch.mp_state =
7033 KVM_MP_STATE_RUNNABLE;
7034 case KVM_MP_STATE_RUNNABLE:
7035 vcpu->arch.apf.halted = false;
7036 break;
7037 case KVM_MP_STATE_INIT_RECEIVED:
7038 break;
7039 default:
7040 return -EINTR;
7041 break;
7042 }
7043 return 1;
7044}
09cec754 7045
5d9bc648
PB		 7046static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7047{
0ad3bed6
PB		 7048 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7049 kvm_x86_ops->check_nested_events(vcpu, false);
7050
5d9bc648
PB		 7051 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7052 !vcpu->arch.apf.halted);
7053}
7054
362c698f 7055static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7056{
7057 int r;
f656ce01 7058 struct kvm *kvm = vcpu->kvm;
d7690175 7059
f656ce01 7060 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7061
362c698f 7062 for (;;) {
58f800d5 7063 if (kvm_vcpu_running(vcpu)) {
851ba692 7064 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7065 } else {
362c698f 7066 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7067 }
7068
09cec754
GN		 7069 if (r <= 0)
7070 break;
7071
72875d8a 7072 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7073 if (kvm_cpu_has_pending_timer(vcpu))
7074 kvm_inject_pending_timer_irqs(vcpu);
7075
782d422b
MG		 7076 if (dm_request_for_irq_injection(vcpu) &&
7077 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7078 r = 0;
7079 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7080 ++vcpu->stat.request_irq_exits;
362c698f 7081 break;
09cec754 7082 }
af585b92
GN		 7083
7084 kvm_check_async_pf_completion(vcpu);
7085
09cec754
GN		 7086 if (signal_pending(current)) {
7087 r = -EINTR;
851ba692 7088 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7089 ++vcpu->stat.signal_exits;
362c698f 7090 break;
09cec754
GN		 7091 }
7092 if (need_resched()) {
f656ce01 7093 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7094 cond_resched();
f656ce01 7095 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7096 }
b6c7a5dc
HB		 7097 }
7098
f656ce01 7099 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7100
7101 return r;
7102}
7103
716d51ab
GN		 7104static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7105{
7106 int r;
7107 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7108 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7109 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7110 if (r != EMULATE_DONE)
7111 return 0;
7112 return 1;
7113}
7114
7115static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7116{
7117 BUG_ON(!vcpu->arch.pio.count);
7118
7119 return complete_emulated_io(vcpu);
7120}
7121
f78146b0
AK		 7122/*
7123 * Implements the following, as a state machine:
7124 *
7125 * read:
7126 * for each fragment
87da7e66
XG		 7127 * for each mmio piece in the fragment
7128 * write gpa, len
7129 * exit
7130 * copy data
f78146b0
AK		 7131 * execute insn
7132 *
7133 * write:
7134 * for each fragment
87da7e66
XG		 7135 * for each mmio piece in the fragment
7136 * write gpa, len
7137 * copy data
7138 * exit
f78146b0 7139 */
716d51ab 7140static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7141{
7142 struct kvm_run *run = vcpu->run;
f78146b0 7143 struct kvm_mmio_fragment *frag;
87da7e66 7144 unsigned len;
5287f194 7145
716d51ab 7146 BUG_ON(!vcpu->mmio_needed);
5287f194 7147
716d51ab 7148 /* Complete previous fragment */
87da7e66
XG		 7149 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7150 len = min(8u, frag->len);
716d51ab 7151 if (!vcpu->mmio_is_write)
87da7e66
XG		 7152 memcpy(frag->data, run->mmio.data, len);
7153
7154 if (frag->len <= 8) {
7155 /* Switch to the next fragment. */
7156 frag++;
7157 vcpu->mmio_cur_fragment++;
7158 } else {
7159 /* Go forward to the next mmio piece. */
7160 frag->data += len;
7161 frag->gpa += len;
7162 frag->len -= len;
7163 }
7164
a08d3b3b 7165 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7166 vcpu->mmio_needed = 0;
0912c977
PB		 7167
7168 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7169 if (vcpu->mmio_is_write)
716d51ab
GN		 7170 return 1;
7171 vcpu->mmio_read_completed = 1;
7172 return complete_emulated_io(vcpu);
7173 }
87da7e66 7174
716d51ab
GN		 7175 run->exit_reason = KVM_EXIT_MMIO;
7176 run->mmio.phys_addr = frag->gpa;
7177 if (vcpu->mmio_is_write)
87da7e66
XG		 7178 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7179 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7180 run->mmio.is_write = vcpu->mmio_is_write;
7181 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7182 return 0;
5287f194
AK		 7183}
7184
716d51ab 7185
b6c7a5dc
HB		 7186int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7187{
c5bedc68 7188 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 7189 int r;
7190 sigset_t sigsaved;
7191
c4d72e2d 7192 fpu__activate_curr(fpu);
e5c30142 7193
ac9f6dc0
AK		 7194 if (vcpu->sigset_active)
7195 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
7196
a4535290 7197 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 7198 kvm_vcpu_block(vcpu);
66450a21 7199 kvm_apic_accept_events(vcpu);
72875d8a 7200 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0
AK		 7201 r = -EAGAIN;
7202 goto out;
b6c7a5dc
HB		 7203 }
7204
b6c7a5dc 7205 /* re-sync apic's tpr */
35754c98 7206 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7207 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7208 r = -EINVAL;
7209 goto out;
7210 }
7211 }
b6c7a5dc 7212
716d51ab
GN		 7213 if (unlikely(vcpu->arch.complete_userspace_io)) {
7214 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7215 vcpu->arch.complete_userspace_io = NULL;
7216 r = cui(vcpu);
7217 if (r <= 0)
7218 goto out;
7219 } else
7220 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7221
460df4c1
PB		 7222 if (kvm_run->immediate_exit)
7223 r = -EINTR;
7224 else
7225 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7226
7227out:
f1d86e46 7228 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 7229 if (vcpu->sigset_active)
7230 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
7231
b6c7a5dc
HB		 7232 return r;
7233}
7234
7235int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7236{
7ae441ea
GN		 7237 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7238 /*
7239 * We are here if userspace calls get_regs() in the middle of
7240 * instruction emulation. Registers state needs to be copied
4a969980 7241 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7242 * that usually, but some bad designed PV devices (vmware
7243 * backdoor interface) need this to work
7244 */
dd856efa 7245 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7246 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7247 }
5fdbf976
MT		 7248 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7249 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7250 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7251 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7252 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7253 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7254 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7255 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7256#ifdef CONFIG_X86_64
5fdbf976
MT		 7257 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7258 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7259 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7260 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7261 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7262 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7263 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7264 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7265#endif
7266
5fdbf976 7267 regs->rip = kvm_rip_read(vcpu);
91586a3b 7268 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7269
b6c7a5dc
HB		 7270 return 0;
7271}
7272
7273int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7274{
7ae441ea
GN		 7275 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7276 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7277
5fdbf976
MT		 7278 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7279 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7280 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7281 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7282 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7283 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7284 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7285 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7286#ifdef CONFIG_X86_64
5fdbf976
MT		 7287 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7288 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7289 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7290 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7291 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7292 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7293 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7294 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7295#endif
7296
5fdbf976 7297 kvm_rip_write(vcpu, regs->rip);
91586a3b 7298 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 7299
b4f14abd
JK		 7300 vcpu->arch.exception.pending = false;
7301
3842d135
AK		 7302 kvm_make_request(KVM_REQ_EVENT, vcpu);
7303
b6c7a5dc
HB		 7304 return 0;
7305}
7306
b6c7a5dc
HB		 7307void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7308{
7309 struct kvm_segment cs;
7310
3e6e0aab 7311 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7312 *db = cs.db;
7313 *l = cs.l;
7314}
7315EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7316
7317int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7318 struct kvm_sregs *sregs)
7319{
89a27f4d 7320 struct desc_ptr dt;
b6c7a5dc 7321
3e6e0aab
GT		 7322 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7323 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7324 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7325 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7326 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7327 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7328
3e6e0aab
GT		 7329 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7330 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7331
7332 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7333 sregs->idt.limit = dt.size;
7334 sregs->idt.base = dt.address;
b6c7a5dc 7335 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7336 sregs->gdt.limit = dt.size;
7337 sregs->gdt.base = dt.address;
b6c7a5dc 7338
4d4ec087 7339 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7340 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7341 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7342 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7343 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7344 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7345 sregs->apic_base = kvm_get_apic_base(vcpu);
7346
923c61bb 7347 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7348
36752c9b 7349 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7350 set_bit(vcpu->arch.interrupt.nr,
7351 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7352
b6c7a5dc
HB		 7353 return 0;
7354}
7355
62d9f0db
MT		 7356int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7357 struct kvm_mp_state *mp_state)
7358{
66450a21 7359 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7360 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7361 vcpu->arch.pv.pv_unhalted)
7362 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7363 else
7364 mp_state->mp_state = vcpu->arch.mp_state;
7365
62d9f0db
MT		 7366 return 0;
7367}
7368
7369int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7370 struct kvm_mp_state *mp_state)
7371{
bce87cce 7372 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7373 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7374 return -EINVAL;
7375
28bf2888
DH		 7376 /* INITs are latched while in SMM */
7377 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7378 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7379 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7380 return -EINVAL;
7381
66450a21
JK		 7382 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7383 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7384 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7385 } else
7386 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7387 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7388 return 0;
7389}
7390
7f3d35fd
KW		 7391int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7392 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7393{
9d74191a 7394 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7395 int ret;
e01c2426 7396
8ec4722d 7397 init_emulate_ctxt(vcpu);
c697518a 7398
7f3d35fd 7399 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7400 has_error_code, error_code);
c697518a 7401
c697518a 7402 if (ret)
19d04437 7403 return EMULATE_FAIL;
37817f29 7404
9d74191a
TY		 7405 kvm_rip_write(vcpu, ctxt->eip);
7406 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7407 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7408 return EMULATE_DONE;
37817f29
IE		 7409}
7410EXPORT_SYMBOL_GPL(kvm_task_switch);
7411
b6c7a5dc
HB		 7412int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7413 struct kvm_sregs *sregs)
7414{
58cb628d 7415 struct msr_data apic_base_msr;
b6c7a5dc 7416 int mmu_reset_needed = 0;
63f42e02 7417 int pending_vec, max_bits, idx;
89a27f4d 7418 struct desc_ptr dt;
b6c7a5dc 7419
6d1068b3
PM		 7420 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7421 return -EINVAL;
7422
89a27f4d
GN		 7423 dt.size = sregs->idt.limit;
7424 dt.address = sregs->idt.base;
b6c7a5dc 7425 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7426 dt.size = sregs->gdt.limit;
7427 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7428 kvm_x86_ops->set_gdt(vcpu, &dt);
7429
ad312c7c 7430 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7431 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7432 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7433 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7434
2d3ad1f4 7435 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7436
f6801dff 7437 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7438 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7439 apic_base_msr.data = sregs->apic_base;
7440 apic_base_msr.host_initiated = true;
7441 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7442
4d4ec087 7443 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7444 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7445 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7446
fc78f519 7447 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7448 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7449 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7450 kvm_update_cpuid(vcpu);
63f42e02
XG		 7451
7452 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7453 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7454 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7455 mmu_reset_needed = 1;
7456 }
63f42e02 7457 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7458
7459 if (mmu_reset_needed)
7460 kvm_mmu_reset_context(vcpu);
7461
a50abc3b 7462 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7463 pending_vec = find_first_bit(
7464 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7465 if (pending_vec < max_bits) {
66fd3f7f 7466 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7467 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7468 }
7469
3e6e0aab
GT		 7470 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7471 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7472 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7473 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7474 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7475 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7476
3e6e0aab
GT		 7477 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7478 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7479
5f0269f5
ME		 7480 update_cr8_intercept(vcpu);
7481
9c3e4aab 7482 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7483 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7484 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7485 !is_protmode(vcpu))
9c3e4aab
MT		 7486 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7487
3842d135
AK		 7488 kvm_make_request(KVM_REQ_EVENT, vcpu);
7489
b6c7a5dc
HB		 7490 return 0;
7491}
7492
d0bfb940
JK		 7493int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7494 struct kvm_guest_debug *dbg)
b6c7a5dc 7495{
355be0b9 7496 unsigned long rflags;
ae675ef0 7497 int i, r;
b6c7a5dc 7498
4f926bf2
JK		 7499 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7500 r = -EBUSY;
7501 if (vcpu->arch.exception.pending)
2122ff5e 7502 goto out;
4f926bf2
JK		 7503 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7504 kvm_queue_exception(vcpu, DB_VECTOR);
7505 else
7506 kvm_queue_exception(vcpu, BP_VECTOR);
7507 }
7508
91586a3b
JK		 7509 /*
7510 * Read rflags as long as potentially injected trace flags are still
7511 * filtered out.
7512 */
7513 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7514
7515 vcpu->guest_debug = dbg->control;
7516 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7517 vcpu->guest_debug = 0;
7518
7519 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7520 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7521 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7522 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7523 } else {
7524 for (i = 0; i < KVM_NR_DB_REGS; i++)
7525 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7526 }
c8639010 7527 kvm_update_dr7(vcpu);
ae675ef0 7528
f92653ee
JK		 7529 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7530 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7531 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7532
91586a3b
JK		 7533 /*
7534 * Trigger an rflags update that will inject or remove the trace
7535 * flags.
7536 */
7537 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7538
a96036b8 7539 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7540
4f926bf2 7541 r = 0;
d0bfb940 7542
2122ff5e 7543out:
b6c7a5dc
HB		 7544
7545 return r;
7546}
7547
8b006791
ZX		 7548/*
7549 * Translate a guest virtual address to a guest physical address.
7550 */
7551int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7552 struct kvm_translation *tr)
7553{
7554 unsigned long vaddr = tr->linear_address;
7555 gpa_t gpa;
f656ce01 7556 int idx;
8b006791 7557
f656ce01 7558 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7559 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7560 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7561 tr->physical_address = gpa;
7562 tr->valid = gpa != UNMAPPED_GVA;
7563 tr->writeable = 1;
7564 tr->usermode = 0;
8b006791
ZX		 7565
7566 return 0;
7567}
7568
d0752060
HB		 7569int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7570{
c47ada30 7571 struct fxregs_state *fxsave =
7366ed77 7572 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7573
d0752060
HB		 7574 memcpy(fpu->fpr, fxsave->st_space, 128);
7575 fpu->fcw = fxsave->cwd;
7576 fpu->fsw = fxsave->swd;
7577 fpu->ftwx = fxsave->twd;
7578 fpu->last_opcode = fxsave->fop;
7579 fpu->last_ip = fxsave->rip;
7580 fpu->last_dp = fxsave->rdp;
7581 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7582
d0752060
HB		 7583 return 0;
7584}
7585
7586int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7587{
c47ada30 7588 struct fxregs_state *fxsave =
7366ed77 7589 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7590
d0752060
HB		 7591 memcpy(fxsave->st_space, fpu->fpr, 128);
7592 fxsave->cwd = fpu->fcw;
7593 fxsave->swd = fpu->fsw;
7594 fxsave->twd = fpu->ftwx;
7595 fxsave->fop = fpu->last_opcode;
7596 fxsave->rip = fpu->last_ip;
7597 fxsave->rdp = fpu->last_dp;
7598 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7599
d0752060
HB		 7600 return 0;
7601}
7602
0ee6a517 7603static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7604{
bf935b0b 7605 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7606 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7607 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7608 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7609
2acf923e
DC		 7610 /*
7611 * Ensure guest xcr0 is valid for loading
7612 */
d91cab78 7613 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7614
ad312c7c 7615 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7616}
d0752060
HB		 7617
7618void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7619{
2608d7a1 7620 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7621 return;
7622
2acf923e
DC		 7623 /*
7624 * Restore all possible states in the guest,
7625 * and assume host would use all available bits.
7626 * Guest xcr0 would be loaded later.
7627 */
d0752060 7628 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7629 __kernel_fpu_begin();
003e2e8b 7630 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7631 trace_kvm_fpu(1);
d0752060 7632}
d0752060
HB		 7633
7634void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7635{
3d42de25 7636 if (!vcpu->guest_fpu_loaded)
d0752060
HB		 7637 return;
7638
7639 vcpu->guest_fpu_loaded = 0;
4f836347 7640 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7641 __kernel_fpu_end();
f096ed85 7642 ++vcpu->stat.fpu_reload;
0c04851c 7643 trace_kvm_fpu(0);
d0752060 7644}
e9b11c17
ZX		 7645
7646void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7647{
bd768e14
IY		 7648 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7649
12f9a48f 7650 kvmclock_reset(vcpu);
7f1ea208 7651
e9b11c17 7652 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 7653 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 7654}
7655
7656struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7657 unsigned int id)
7658{
c447e76b
LL		 7659 struct kvm_vcpu *vcpu;
7660
6755bae8
ZA		 7661 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7662 printk_once(KERN_WARNING
7663 "kvm: SMP vm created on host with unstable TSC; "
7664 "guest TSC will not be reliable\n");
c447e76b
LL		 7665
7666 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7667
c447e76b 7668 return vcpu;
26e5215f 7669}
e9b11c17 7670
26e5215f
AK		 7671int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7672{
7673 int r;
e9b11c17 7674
19efffa2 7675 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7676 r = vcpu_load(vcpu);
7677 if (r)
7678 return r;
d28bc9dd 7679 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7680 kvm_mmu_setup(vcpu);
e9b11c17 7681 vcpu_put(vcpu);
26e5215f 7682 return r;
e9b11c17
ZX		 7683}
7684
31928aa5 7685void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7686{
8fe8ab46 7687 struct msr_data msr;
332967a3 7688 struct kvm *kvm = vcpu->kvm;
42897d86 7689
31928aa5
DD		 7690 if (vcpu_load(vcpu))
7691 return;
8fe8ab46
WA		 7692 msr.data = 0x0;
7693 msr.index = MSR_IA32_TSC;
7694 msr.host_initiated = true;
7695 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7696 vcpu_put(vcpu);
7697
630994b3
MT		 7698 if (!kvmclock_periodic_sync)
7699 return;
7700
332967a3
AJ		 7701 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7702 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7703}
7704
d40ccc62 7705void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7706{
9fc77441 7707 int r;
344d9588
GN		 7708 vcpu->arch.apf.msr_val = 0;
7709
9fc77441
MT		 7710 r = vcpu_load(vcpu);
7711 BUG_ON(r);
e9b11c17
ZX		 7712 kvm_mmu_unload(vcpu);
7713 vcpu_put(vcpu);
7714
7715 kvm_x86_ops->vcpu_free(vcpu);
7716}
7717
d28bc9dd 7718void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7719{
e69fab5d
PB		 7720 vcpu->arch.hflags = 0;
7721
c43203ca 7722 vcpu->arch.smi_pending = 0;
7460fb4a
AK		 7723 atomic_set(&vcpu->arch.nmi_queued, 0);
7724 vcpu->arch.nmi_pending = 0;
448fa4a9 7725 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7726 kvm_clear_interrupt_queue(vcpu);
7727 kvm_clear_exception_queue(vcpu);
448fa4a9 7728
42dbaa5a 7729 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7730 kvm_update_dr0123(vcpu);
6f43ed01 7731 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7732 kvm_update_dr6(vcpu);
42dbaa5a 7733 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7734 kvm_update_dr7(vcpu);
42dbaa5a 7735
1119022c
NA		 7736 vcpu->arch.cr2 = 0;
7737
3842d135 7738 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7739 vcpu->arch.apf.msr_val = 0;
c9aaa895 7740 vcpu->arch.st.msr_val = 0;
3842d135 7741
12f9a48f
GC		 7742 kvmclock_reset(vcpu);
7743
af585b92
GN		 7744 kvm_clear_async_pf_completion_queue(vcpu);
7745 kvm_async_pf_hash_reset(vcpu);
7746 vcpu->arch.apf.halted = false;
3842d135 7747
64d60670 7748 if (!init_event) {
d28bc9dd 7749 kvm_pmu_reset(vcpu);
64d60670 7750 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 7751
7752 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
7753 vcpu->arch.msr_misc_features_enables = 0;
64d60670 7754 }
f5132b01 7755
66f7b72e
JS		 7756 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7757 vcpu->arch.regs_avail = ~0;
7758 vcpu->arch.regs_dirty = ~0;
7759
d28bc9dd 7760 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7761}
7762
2b4a273b 7763void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7764{
7765 struct kvm_segment cs;
7766
7767 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7768 cs.selector = vector << 8;
7769 cs.base = vector << 12;
7770 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7771 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7772}
7773
13a34e06 7774int kvm_arch_hardware_enable(void)
e9b11c17 7775{
ca84d1a2
ZA		 7776 struct kvm *kvm;
7777 struct kvm_vcpu *vcpu;
7778 int i;
0dd6a6ed
ZA		 7779 int ret;
7780 u64 local_tsc;
7781 u64 max_tsc = 0;
7782 bool stable, backwards_tsc = false;
18863bdd
AK		 7783
7784 kvm_shared_msr_cpu_online();
13a34e06 7785 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7786 if (ret != 0)
7787 return ret;
7788
4ea1636b 7789 local_tsc = rdtsc();
0dd6a6ed
ZA		 7790 stable = !check_tsc_unstable();
7791 list_for_each_entry(kvm, &vm_list, vm_list) {
7792 kvm_for_each_vcpu(i, vcpu, kvm) {
7793 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7794 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7795 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7796 backwards_tsc = true;
7797 if (vcpu->arch.last_host_tsc > max_tsc)
7798 max_tsc = vcpu->arch.last_host_tsc;
7799 }
7800 }
7801 }
7802
7803 /*
7804 * Sometimes, even reliable TSCs go backwards. This happens on
7805 * platforms that reset TSC during suspend or hibernate actions, but
7806 * maintain synchronization. We must compensate. Fortunately, we can
7807 * detect that condition here, which happens early in CPU bringup,
7808 * before any KVM threads can be running. Unfortunately, we can't
7809 * bring the TSCs fully up to date with real time, as we aren't yet far
7810 * enough into CPU bringup that we know how much real time has actually
108b249c 7811 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 7812 * variables that haven't been updated yet.
7813 *
7814 * So we simply find the maximum observed TSC above, then record the
7815 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7816 * the adjustment will be applied. Note that we accumulate
7817 * adjustments, in case multiple suspend cycles happen before some VCPU
7818 * gets a chance to run again. In the event that no KVM threads get a
7819 * chance to run, we will miss the entire elapsed period, as we'll have
7820 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7821 * loose cycle time. This isn't too big a deal, since the loss will be
7822 * uniform across all VCPUs (not to mention the scenario is extremely
7823 * unlikely). It is possible that a second hibernate recovery happens
7824 * much faster than a first, causing the observed TSC here to be
7825 * smaller; this would require additional padding adjustment, which is
7826 * why we set last_host_tsc to the local tsc observed here.
7827 *
7828 * N.B. - this code below runs only on platforms with reliable TSC,
7829 * as that is the only way backwards_tsc is set above. Also note
7830 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7831 * have the same delta_cyc adjustment applied if backwards_tsc
7832 * is detected. Note further, this adjustment is only done once,
7833 * as we reset last_host_tsc on all VCPUs to stop this from being
7834 * called multiple times (one for each physical CPU bringup).
7835 *
4a969980 7836 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7837 * will be compensated by the logic in vcpu_load, which sets the TSC to
7838 * catchup mode. This will catchup all VCPUs to real time, but cannot
7839 * guarantee that they stay in perfect synchronization.
7840 */
7841 if (backwards_tsc) {
7842 u64 delta_cyc = max_tsc - local_tsc;
7843 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 7844 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 7845 kvm_for_each_vcpu(i, vcpu, kvm) {
7846 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7847 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7848 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7849 }
7850
7851 /*
7852 * We have to disable TSC offset matching.. if you were
7853 * booting a VM while issuing an S4 host suspend....
7854 * you may have some problem. Solving this issue is
7855 * left as an exercise to the reader.
7856 */
7857 kvm->arch.last_tsc_nsec = 0;
7858 kvm->arch.last_tsc_write = 0;
7859 }
7860
7861 }
7862 return 0;
e9b11c17
ZX		 7863}
7864
13a34e06 7865void kvm_arch_hardware_disable(void)
e9b11c17 7866{
13a34e06
RK		 7867 kvm_x86_ops->hardware_disable();
7868 drop_user_return_notifiers();
e9b11c17
ZX		 7869}
7870
7871int kvm_arch_hardware_setup(void)
7872{
9e9c3fe4
NA		 7873 int r;
7874
7875 r = kvm_x86_ops->hardware_setup();
7876 if (r != 0)
7877 return r;
7878
35181e86
HZ		 7879 if (kvm_has_tsc_control) {
7880 /*
7881 * Make sure the user can only configure tsc_khz values that
7882 * fit into a signed integer.
7883 * A min value is not calculated needed because it will always
7884 * be 1 on all machines.
7885 */
7886 u64 max = min(0x7fffffffULL,
7887 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7888 kvm_max_guest_tsc_khz = max;
7889
ad721883 7890 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7891 }
ad721883 7892
9e9c3fe4
NA		 7893 kvm_init_msr_list();
7894 return 0;
e9b11c17
ZX		 7895}
7896
7897void kvm_arch_hardware_unsetup(void)
7898{
7899 kvm_x86_ops->hardware_unsetup();
7900}
7901
7902void kvm_arch_check_processor_compat(void *rtn)
7903{
7904 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7905}
7906
7907bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7908{
7909 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7910}
7911EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7912
7913bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7914{
7915 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7916}
7917
54e9818f 7918struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 7919EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 7920
e9b11c17
ZX		 7921int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7922{
7923 struct page *page;
7924 struct kvm *kvm;
7925 int r;
7926
7927 BUG_ON(vcpu->kvm == NULL);
7928 kvm = vcpu->kvm;
7929
d62caabb 7930 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7931 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7932 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7933 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7934 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7935 else
a4535290 7936 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7937
7938 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7939 if (!page) {
7940 r = -ENOMEM;
7941 goto fail;
7942 }
ad312c7c 7943 vcpu->arch.pio_data = page_address(page);
e9b11c17 7944
cc578287 7945 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7946
e9b11c17
ZX		 7947 r = kvm_mmu_create(vcpu);
7948 if (r < 0)
7949 goto fail_free_pio_data;
7950
7951 if (irqchip_in_kernel(kvm)) {
7952 r = kvm_create_lapic(vcpu);
7953 if (r < 0)
7954 goto fail_mmu_destroy;
54e9818f
GN		 7955 } else
7956 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7957
890ca9ae
HY		 7958 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7959 GFP_KERNEL);
7960 if (!vcpu->arch.mce_banks) {
7961 r = -ENOMEM;
443c39bc 7962 goto fail_free_lapic;
890ca9ae
HY		 7963 }
7964 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7965
f1797359
WY		 7966 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7967 r = -ENOMEM;
f5f48ee1 7968 goto fail_free_mce_banks;
f1797359 7969 }
f5f48ee1 7970
0ee6a517 7971 fx_init(vcpu);
66f7b72e 7972
ba904635 7973 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7974 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7975
7976 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7977 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7978
5a4f55cd
EK		 7979 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7980
74545705
RK		 7981 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7982
af585b92 7983 kvm_async_pf_hash_reset(vcpu);
f5132b01 7984 kvm_pmu_init(vcpu);
af585b92 7985
1c1a9ce9
SR		 7986 vcpu->arch.pending_external_vector = -1;
7987
5c919412
AS		 7988 kvm_hv_vcpu_init(vcpu);
7989
e9b11c17 7990 return 0;
0ee6a517 7991
f5f48ee1
SY		 7992fail_free_mce_banks:
7993 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7994fail_free_lapic:
7995 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7996fail_mmu_destroy:
7997 kvm_mmu_destroy(vcpu);
7998fail_free_pio_data:
ad312c7c 7999 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8000fail:
8001 return r;
8002}
8003
8004void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8005{
f656ce01
MT		 8006 int idx;
8007
1f4b34f8 8008 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8009 kvm_pmu_destroy(vcpu);
36cb93fd 8010 kfree(vcpu->arch.mce_banks);
e9b11c17 8011 kvm_free_lapic(vcpu);
f656ce01 8012 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8013 kvm_mmu_destroy(vcpu);
f656ce01 8014 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8015 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8016 if (!lapic_in_kernel(vcpu))
54e9818f 8017 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8018}
d19a9cd2 8019
e790d9ef
RK		 8020void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8021{
ae97a3b8 8022 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8023}
8024
e08b9637 8025int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8026{
e08b9637
CO		 8027 if (type)
8028 return -EINVAL;
8029
6ef768fa 8030 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8031 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8032 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8033 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8034 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8035
5550af4d
SY		 8036 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8037 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8038 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8039 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8040 &kvm->arch.irq_sources_bitmap);
5550af4d 8041
038f8c11 8042 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8043 mutex_init(&kvm->arch.apic_map_lock);
3f5ad8be 8044 mutex_init(&kvm->arch.hyperv.hv_lock);
d828199e
MT		 8045 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8046
108b249c 8047 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8048 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8049
7e44e449 8050 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8051 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8052
0eb05bf2 8053 kvm_page_track_init(kvm);
13d268ca 8054 kvm_mmu_init_vm(kvm);
0eb05bf2 8055
03543133
SS		 8056 if (kvm_x86_ops->vm_init)
8057 return kvm_x86_ops->vm_init(kvm);
8058
d89f5eff 8059 return 0;
d19a9cd2
ZX		 8060}
8061
8062static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8063{
9fc77441
MT		 8064 int r;
8065 r = vcpu_load(vcpu);
8066 BUG_ON(r);
d19a9cd2
ZX		 8067 kvm_mmu_unload(vcpu);
8068 vcpu_put(vcpu);
8069}
8070
8071static void kvm_free_vcpus(struct kvm *kvm)
8072{
8073 unsigned int i;
988a2cae 8074 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8075
8076 /*
8077 * Unpin any mmu pages first.
8078 */
af585b92
GN		 8079 kvm_for_each_vcpu(i, vcpu, kvm) {
8080 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8081 kvm_unload_vcpu_mmu(vcpu);
af585b92 8082 }
988a2cae
GN		 8083 kvm_for_each_vcpu(i, vcpu, kvm)
8084 kvm_arch_vcpu_free(vcpu);
8085
8086 mutex_lock(&kvm->lock);
8087 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8088 kvm->vcpus[i] = NULL;
d19a9cd2 8089
988a2cae
GN		 8090 atomic_set(&kvm->online_vcpus, 0);
8091 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8092}
8093
ad8ba2cd
SY		 8094void kvm_arch_sync_events(struct kvm *kvm)
8095{
332967a3 8096 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8097 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8098 kvm_free_pit(kvm);
ad8ba2cd
SY		 8099}
8100
1d8007bd 8101int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8102{
8103 int i, r;
25188b99 8104 unsigned long hva;
f0d648bd
PB		 8105 struct kvm_memslots *slots = kvm_memslots(kvm);
8106 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8107
8108 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8109 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8110 return -EINVAL;
9da0e4d5 8111
f0d648bd
PB		 8112 slot = id_to_memslot(slots, id);
8113 if (size) {
b21629da 8114 if (slot->npages)
f0d648bd
PB		 8115 return -EEXIST;
8116
8117 /*
8118 * MAP_SHARED to prevent internal slot pages from being moved
8119 * by fork()/COW.
8120 */
8121 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8122 MAP_SHARED | MAP_ANONYMOUS, 0);
8123 if (IS_ERR((void *)hva))
8124 return PTR_ERR((void *)hva);
8125 } else {
8126 if (!slot->npages)
8127 return 0;
8128
8129 hva = 0;
8130 }
8131
8132 old = *slot;
9da0e4d5 8133 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8134 struct kvm_userspace_memory_region m;
9da0e4d5 8135
1d8007bd
PB		 8136 m.slot = id | (i << 16);
8137 m.flags = 0;
8138 m.guest_phys_addr = gpa;
f0d648bd 8139 m.userspace_addr = hva;
1d8007bd 8140 m.memory_size = size;
9da0e4d5
PB		 8141 r = __kvm_set_memory_region(kvm, &m);
8142 if (r < 0)
8143 return r;
8144 }
8145
f0d648bd
PB		 8146 if (!size) {
8147 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8148 WARN_ON(r < 0);
8149 }
8150
9da0e4d5
PB		 8151 return 0;
8152}
8153EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8154
1d8007bd 8155int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8156{
8157 int r;
8158
8159 mutex_lock(&kvm->slots_lock);
1d8007bd 8160 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8161 mutex_unlock(&kvm->slots_lock);
8162
8163 return r;
8164}
8165EXPORT_SYMBOL_GPL(x86_set_memory_region);
8166
d19a9cd2
ZX		 8167void kvm_arch_destroy_vm(struct kvm *kvm)
8168{
27469d29
AH		 8169 if (current->mm == kvm->mm) {
8170 /*
8171 * Free memory regions allocated on behalf of userspace,
8172 * unless the the memory map has changed due to process exit
8173 * or fd copying.
8174 */
1d8007bd
PB		 8175 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8176 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8177 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8178 }
03543133
SS		 8179 if (kvm_x86_ops->vm_destroy)
8180 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8181 kvm_pic_destroy(kvm);
8182 kvm_ioapic_destroy(kvm);
d19a9cd2 8183 kvm_free_vcpus(kvm);
af1bae54 8184 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8185 kvm_mmu_uninit_vm(kvm);
2beb6dad 8186 kvm_page_track_cleanup(kvm);
d19a9cd2 8187}
0de10343 8188
5587027c 8189void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8190 struct kvm_memory_slot *dont)
8191{
8192 int i;
8193
d89cc617
TY		 8194 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8195 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8196 kvfree(free->arch.rmap[i]);
d89cc617 8197 free->arch.rmap[i] = NULL;
77d11309 8198 }
d89cc617
TY		 8199 if (i == 0)
8200 continue;
8201
8202 if (!dont || free->arch.lpage_info[i - 1] !=
8203 dont->arch.lpage_info[i - 1]) {
548ef284 8204 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8205 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8206 }
8207 }
21ebbeda
XG		 8208
8209 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8210}
8211
5587027c
AK		 8212int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8213 unsigned long npages)
db3fe4eb
TY		 8214{
8215 int i;
8216
d89cc617 8217 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8218 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8219 unsigned long ugfn;
8220 int lpages;
d89cc617 8221 int level = i + 1;
db3fe4eb
TY		 8222
8223 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8224 slot->base_gfn, level) + 1;
8225
d89cc617 8226 slot->arch.rmap[i] =
a7c3e901 8227 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8228 if (!slot->arch.rmap[i])
77d11309 8229 goto out_free;
d89cc617
TY		 8230 if (i == 0)
8231 continue;
77d11309 8232
a7c3e901 8233 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8234 if (!linfo)
db3fe4eb
TY		 8235 goto out_free;
8236
92f94f1e
XG		 8237 slot->arch.lpage_info[i - 1] = linfo;
8238
db3fe4eb 8239 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8240 linfo[0].disallow_lpage = 1;
db3fe4eb 8241 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8242 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8243 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8244 /*
8245 * If the gfn and userspace address are not aligned wrt each
8246 * other, or if explicitly asked to, disable large page
8247 * support for this slot
8248 */
8249 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8250 !kvm_largepages_enabled()) {
8251 unsigned long j;
8252
8253 for (j = 0; j < lpages; ++j)
92f94f1e 8254 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8255 }
8256 }
8257
21ebbeda
XG		 8258 if (kvm_page_track_create_memslot(slot, npages))
8259 goto out_free;
8260
db3fe4eb
TY		 8261 return 0;
8262
8263out_free:
d89cc617 8264 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8265 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8266 slot->arch.rmap[i] = NULL;
8267 if (i == 0)
8268 continue;
8269
548ef284 8270 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8271 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8272 }
8273 return -ENOMEM;
8274}
8275
15f46015 8276void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8277{
e6dff7d1
TY		 8278 /*
8279 * memslots->generation has been incremented.
8280 * mmio generation may have reached its maximum value.
8281 */
54bf36aa 8282 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8283}
8284
f7784b8e
MT		 8285int kvm_arch_prepare_memory_region(struct kvm *kvm,
8286 struct kvm_memory_slot *memslot,
09170a49 8287 const struct kvm_userspace_memory_region *mem,
7b6195a9 8288 enum kvm_mr_change change)
0de10343 8289{
f7784b8e
MT		 8290 return 0;
8291}
8292
88178fd4
KH		 8293static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8294 struct kvm_memory_slot *new)
8295{
8296 /* Still write protect RO slot */
8297 if (new->flags & KVM_MEM_READONLY) {
8298 kvm_mmu_slot_remove_write_access(kvm, new);
8299 return;
8300 }
8301
8302 /*
8303 * Call kvm_x86_ops dirty logging hooks when they are valid.
8304 *
8305 * kvm_x86_ops->slot_disable_log_dirty is called when:
8306 *
8307 * - KVM_MR_CREATE with dirty logging is disabled
8308 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8309 *
8310 * The reason is, in case of PML, we need to set D-bit for any slots
8311 * with dirty logging disabled in order to eliminate unnecessary GPA
8312 * logging in PML buffer (and potential PML buffer full VMEXT). This
8313 * guarantees leaving PML enabled during guest's lifetime won't have
8314 * any additonal overhead from PML when guest is running with dirty
8315 * logging disabled for memory slots.
8316 *
8317 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8318 * to dirty logging mode.
8319 *
8320 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8321 *
8322 * In case of write protect:
8323 *
8324 * Write protect all pages for dirty logging.
8325 *
8326 * All the sptes including the large sptes which point to this
8327 * slot are set to readonly. We can not create any new large
8328 * spte on this slot until the end of the logging.
8329 *
8330 * See the comments in fast_page_fault().
8331 */
8332 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8333 if (kvm_x86_ops->slot_enable_log_dirty)
8334 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8335 else
8336 kvm_mmu_slot_remove_write_access(kvm, new);
8337 } else {
8338 if (kvm_x86_ops->slot_disable_log_dirty)
8339 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8340 }
8341}
8342
f7784b8e 8343void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8344 const struct kvm_userspace_memory_region *mem,
8482644a 8345 const struct kvm_memory_slot *old,
f36f3f28 8346 const struct kvm_memory_slot *new,
8482644a 8347 enum kvm_mr_change change)
f7784b8e 8348{
8482644a 8349 int nr_mmu_pages = 0;
f7784b8e 8350
48c0e4e9
XG		 8351 if (!kvm->arch.n_requested_mmu_pages)
8352 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8353
48c0e4e9 8354 if (nr_mmu_pages)
0de10343 8355 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8356
3ea3b7fa
WL		 8357 /*
8358 * Dirty logging tracks sptes in 4k granularity, meaning that large
8359 * sptes have to be split. If live migration is successful, the guest
8360 * in the source machine will be destroyed and large sptes will be
8361 * created in the destination. However, if the guest continues to run
8362 * in the source machine (for example if live migration fails), small
8363 * sptes will remain around and cause bad performance.
8364 *
8365 * Scan sptes if dirty logging has been stopped, dropping those
8366 * which can be collapsed into a single large-page spte. Later
8367 * page faults will create the large-page sptes.
8368 */
8369 if ((change != KVM_MR_DELETE) &&
8370 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8371 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8372 kvm_mmu_zap_collapsible_sptes(kvm, new);
8373
c972f3b1 8374 /*
88178fd4 8375 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8376 *
88178fd4
KH		 8377 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8378 * been zapped so no dirty logging staff is needed for old slot. For
8379 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8380 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8381 *
8382 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8383 */
88178fd4 8384 if (change != KVM_MR_DELETE)
f36f3f28 8385 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8386}
1d737c8a 8387
2df72e9b 8388void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8389{
6ca18b69 8390 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8391}
8392
2df72e9b
MT		 8393void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8394 struct kvm_memory_slot *slot)
8395{
ae7cd873 8396 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8397}
8398
5d9bc648
PB		 8399static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8400{
8401 if (!list_empty_careful(&vcpu->async_pf.done))
8402 return true;
8403
8404 if (kvm_apic_has_events(vcpu))
8405 return true;
8406
8407 if (vcpu->arch.pv.pv_unhalted)
8408 return true;
8409
47a66eed
Z		 8410 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8411 (vcpu->arch.nmi_pending &&
8412 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 8413 return true;
8414
47a66eed
Z		 8415 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8416 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 8417 return true;
8418
5d9bc648
PB		 8419 if (kvm_arch_interrupt_allowed(vcpu) &&
8420 kvm_cpu_has_interrupt(vcpu))
8421 return true;
8422
1f4b34f8
AS		 8423 if (kvm_hv_has_stimer_pending(vcpu))
8424 return true;
8425
5d9bc648
PB		 8426 return false;
8427}
8428
1d737c8a
ZX		 8429int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8430{
5d9bc648 8431 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8432}
5736199a 8433
b6d33834 8434int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8435{
b6d33834 8436 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8437}
78646121
GN		 8438
8439int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8440{
8441 return kvm_x86_ops->interrupt_allowed(vcpu);
8442}
229456fc 8443
82b32774 8444unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8445{
82b32774
NA		 8446 if (is_64_bit_mode(vcpu))
8447 return kvm_rip_read(vcpu);
8448 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8449 kvm_rip_read(vcpu));
8450}
8451EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8452
82b32774
NA		 8453bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8454{
8455 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8456}
8457EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8458
94fe45da
JK		 8459unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8460{
8461 unsigned long rflags;
8462
8463 rflags = kvm_x86_ops->get_rflags(vcpu);
8464 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8465 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8466 return rflags;
8467}
8468EXPORT_SYMBOL_GPL(kvm_get_rflags);
8469
6addfc42 8470static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8471{
8472 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8473 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8474 rflags |= X86_EFLAGS_TF;
94fe45da 8475 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8476}
8477
8478void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8479{
8480 __kvm_set_rflags(vcpu, rflags);
3842d135 8481 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8482}
8483EXPORT_SYMBOL_GPL(kvm_set_rflags);
8484
56028d08
GN		 8485void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8486{
8487 int r;
8488
fb67e14f 8489 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8490 work->wakeup_all)
56028d08
GN		 8491 return;
8492
8493 r = kvm_mmu_reload(vcpu);
8494 if (unlikely(r))
8495 return;
8496
fb67e14f
XG		 8497 if (!vcpu->arch.mmu.direct_map &&
8498 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8499 return;
8500
56028d08
GN		 8501 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8502}
8503
af585b92
GN		 8504static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8505{
8506 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8507}
8508
8509static inline u32 kvm_async_pf_next_probe(u32 key)
8510{
8511 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8512}
8513
8514static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8515{
8516 u32 key = kvm_async_pf_hash_fn(gfn);
8517
8518 while (vcpu->arch.apf.gfns[key] != ~0)
8519 key = kvm_async_pf_next_probe(key);
8520
8521 vcpu->arch.apf.gfns[key] = gfn;
8522}
8523
8524static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8525{
8526 int i;
8527 u32 key = kvm_async_pf_hash_fn(gfn);
8528
8529 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8530 (vcpu->arch.apf.gfns[key] != gfn &&
8531 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8532 key = kvm_async_pf_next_probe(key);
8533
8534 return key;
8535}
8536
8537bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8538{
8539 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8540}
8541
8542static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8543{
8544 u32 i, j, k;
8545
8546 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8547 while (true) {
8548 vcpu->arch.apf.gfns[i] = ~0;
8549 do {
8550 j = kvm_async_pf_next_probe(j);
8551 if (vcpu->arch.apf.gfns[j] == ~0)
8552 return;
8553 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8554 /*
8555 * k lies cyclically in ]i,j]
8556 * | i.k.j |
8557 * |....j i.k.| or |.k..j i...|
8558 */
8559 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8560 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8561 i = j;
8562 }
8563}
8564
7c90705b
GN		 8565static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8566{
4e335d9e
PB		 8567
8568 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8569 sizeof(val));
7c90705b
GN		 8570}
8571
af585b92
GN		 8572void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8573 struct kvm_async_pf *work)
8574{
6389ee94
AK		 8575 struct x86_exception fault;
8576
7c90705b 8577 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8578 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8579
8580 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8581 (vcpu->arch.apf.send_user_only &&
8582 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8583 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8584 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8585 fault.vector = PF_VECTOR;
8586 fault.error_code_valid = true;
8587 fault.error_code = 0;
8588 fault.nested_page_fault = false;
8589 fault.address = work->arch.token;
adfe20fb 8590 fault.async_page_fault = true;
6389ee94 8591 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8592 }
af585b92
GN		 8593}
8594
8595void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8596 struct kvm_async_pf *work)
8597{
6389ee94
AK		 8598 struct x86_exception fault;
8599
f2e10669 8600 if (work->wakeup_all)
7c90705b
GN		 8601 work->arch.token = ~0; /* broadcast wakeup */
8602 else
8603 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 8604 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b
GN		 8605
8606 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8607 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8608 fault.vector = PF_VECTOR;
8609 fault.error_code_valid = true;
8610 fault.error_code = 0;
8611 fault.nested_page_fault = false;
8612 fault.address = work->arch.token;
adfe20fb 8613 fault.async_page_fault = true;
6389ee94 8614 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8615 }
e6d53e3b 8616 vcpu->arch.apf.halted = false;
a4fa1635 8617 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8618}
8619
8620bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8621{
8622 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8623 return true;
8624 else
9bc1f09f 8625 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 8626}
8627
5544eb9b
PB		 8628void kvm_arch_start_assignment(struct kvm *kvm)
8629{
8630 atomic_inc(&kvm->arch.assigned_device_count);
8631}
8632EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8633
8634void kvm_arch_end_assignment(struct kvm *kvm)
8635{
8636 atomic_dec(&kvm->arch.assigned_device_count);
8637}
8638EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8639
8640bool kvm_arch_has_assigned_device(struct kvm *kvm)
8641{
8642 return atomic_read(&kvm->arch.assigned_device_count);
8643}
8644EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8645
e0f0bbc5
AW		 8646void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8647{
8648 atomic_inc(&kvm->arch.noncoherent_dma_count);
8649}
8650EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8651
8652void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8653{
8654 atomic_dec(&kvm->arch.noncoherent_dma_count);
8655}
8656EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8657
8658bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8659{
8660 return atomic_read(&kvm->arch.noncoherent_dma_count);
8661}
8662EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8663
14717e20
AW		 8664bool kvm_arch_has_irq_bypass(void)
8665{
8666 return kvm_x86_ops->update_pi_irte != NULL;
8667}
8668
87276880
FW		 8669int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8670 struct irq_bypass_producer *prod)
8671{
8672 struct kvm_kernel_irqfd *irqfd =
8673 container_of(cons, struct kvm_kernel_irqfd, consumer);
8674
14717e20 8675 irqfd->producer = prod;
87276880 8676
14717e20
AW		 8677 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8678 prod->irq, irqfd->gsi, 1);
87276880
FW		 8679}
8680
8681void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8682 struct irq_bypass_producer *prod)
8683{
8684 int ret;
8685 struct kvm_kernel_irqfd *irqfd =
8686 container_of(cons, struct kvm_kernel_irqfd, consumer);
8687
87276880
FW		 8688 WARN_ON(irqfd->producer != prod);
8689 irqfd->producer = NULL;
8690
8691 /*
8692 * When producer of consumer is unregistered, we change back to
8693 * remapped mode, so we can re-use the current implementation
bb3541f1 8694 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8695 * int this case doesn't want to receive the interrupts.
8696 */
8697 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8698 if (ret)
8699 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8700 " fails: %d\n", irqfd->consumer.token, ret);
8701}
8702
8703int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8704 uint32_t guest_irq, bool set)
8705{
8706 if (!kvm_x86_ops->update_pi_irte)
8707 return -EINVAL;
8708
8709 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8710}
8711
52004014
FW		 8712bool kvm_vector_hashing_enabled(void)
8713{
8714 return vector_hashing;
8715}
8716EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8717
229456fc 8718EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8719EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8720EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8721EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8722EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8723EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8724EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8725EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8726EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8727EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8728EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8729EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8730EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8731EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8732EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8733EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8734EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8735EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8736EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
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