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043405e1 CO |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * derived from drivers/kvm/kvm_main.c | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
7 | * Copyright (C) 2008 Qumranet, Inc. |
8 | * Copyright IBM Corporation, 2008 | |
221d059d | 9 | * Copyright 2010 Red Hat, Inc. and/or its affilates. |
043405e1 CO |
10 | * |
11 | * Authors: | |
12 | * Avi Kivity <avi@qumranet.com> | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
14 | * Amit Shah <amit.shah@qumranet.com> |
15 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
16 | * |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | * | |
20 | */ | |
21 | ||
edf88417 | 22 | #include <linux/kvm_host.h> |
313a3dc7 | 23 | #include "irq.h" |
1d737c8a | 24 | #include "mmu.h" |
7837699f | 25 | #include "i8254.h" |
37817f29 | 26 | #include "tss.h" |
5fdbf976 | 27 | #include "kvm_cache_regs.h" |
26eef70c | 28 | #include "x86.h" |
313a3dc7 | 29 | |
18068523 | 30 | #include <linux/clocksource.h> |
4d5c5d0f | 31 | #include <linux/interrupt.h> |
313a3dc7 CO |
32 | #include <linux/kvm.h> |
33 | #include <linux/fs.h> | |
34 | #include <linux/vmalloc.h> | |
5fb76f9b | 35 | #include <linux/module.h> |
0de10343 | 36 | #include <linux/mman.h> |
2bacc55c | 37 | #include <linux/highmem.h> |
19de40a8 | 38 | #include <linux/iommu.h> |
62c476c7 | 39 | #include <linux/intel-iommu.h> |
c8076604 | 40 | #include <linux/cpufreq.h> |
18863bdd | 41 | #include <linux/user-return-notifier.h> |
a983fb23 | 42 | #include <linux/srcu.h> |
5a0e3ad6 | 43 | #include <linux/slab.h> |
ff9d07a0 | 44 | #include <linux/perf_event.h> |
7bee342a | 45 | #include <linux/uaccess.h> |
aec51dc4 | 46 | #include <trace/events/kvm.h> |
2ed152af | 47 | |
229456fc MT |
48 | #define CREATE_TRACE_POINTS |
49 | #include "trace.h" | |
043405e1 | 50 | |
24f1e32c | 51 | #include <asm/debugreg.h> |
d825ed0a | 52 | #include <asm/msr.h> |
a5f61300 | 53 | #include <asm/desc.h> |
0bed3b56 | 54 | #include <asm/mtrr.h> |
890ca9ae | 55 | #include <asm/mce.h> |
7cf30855 | 56 | #include <asm/i387.h> |
98918833 | 57 | #include <asm/xcr.h> |
043405e1 | 58 | |
313a3dc7 | 59 | #define MAX_IO_MSRS 256 |
a03490ed CO |
60 | #define CR0_RESERVED_BITS \ |
61 | (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ | |
62 | | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ | |
63 | | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) | |
64 | #define CR4_RESERVED_BITS \ | |
65 | (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ | |
66 | | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ | |
67 | | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \ | |
2acf923e | 68 | | X86_CR4_OSXSAVE \ |
a03490ed CO |
69 | | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE)) |
70 | ||
71 | #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) | |
890ca9ae HY |
72 | |
73 | #define KVM_MAX_MCE_BANKS 32 | |
74 | #define KVM_MCE_CAP_SUPPORTED MCG_CTL_P | |
75 | ||
50a37eb4 JR |
76 | /* EFER defaults: |
77 | * - enable syscall per default because its emulated by KVM | |
78 | * - enable LME and LMA per default on 64 bit KVM | |
79 | */ | |
80 | #ifdef CONFIG_X86_64 | |
81 | static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL; | |
82 | #else | |
83 | static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL; | |
84 | #endif | |
313a3dc7 | 85 | |
ba1389b7 AK |
86 | #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM |
87 | #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU | |
417bc304 | 88 | |
cb142eb7 | 89 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
674eea0f AK |
90 | static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid, |
91 | struct kvm_cpuid_entry2 __user *entries); | |
92 | ||
97896d04 | 93 | struct kvm_x86_ops *kvm_x86_ops; |
5fdbf976 | 94 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 95 | |
ed85c068 AP |
96 | int ignore_msrs = 0; |
97 | module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR); | |
98 | ||
18863bdd AK |
99 | #define KVM_NR_SHARED_MSRS 16 |
100 | ||
101 | struct kvm_shared_msrs_global { | |
102 | int nr; | |
2bf78fa7 | 103 | u32 msrs[KVM_NR_SHARED_MSRS]; |
18863bdd AK |
104 | }; |
105 | ||
106 | struct kvm_shared_msrs { | |
107 | struct user_return_notifier urn; | |
108 | bool registered; | |
2bf78fa7 SY |
109 | struct kvm_shared_msr_values { |
110 | u64 host; | |
111 | u64 curr; | |
112 | } values[KVM_NR_SHARED_MSRS]; | |
18863bdd AK |
113 | }; |
114 | ||
115 | static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; | |
116 | static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs); | |
117 | ||
417bc304 | 118 | struct kvm_stats_debugfs_item debugfs_entries[] = { |
ba1389b7 AK |
119 | { "pf_fixed", VCPU_STAT(pf_fixed) }, |
120 | { "pf_guest", VCPU_STAT(pf_guest) }, | |
121 | { "tlb_flush", VCPU_STAT(tlb_flush) }, | |
122 | { "invlpg", VCPU_STAT(invlpg) }, | |
123 | { "exits", VCPU_STAT(exits) }, | |
124 | { "io_exits", VCPU_STAT(io_exits) }, | |
125 | { "mmio_exits", VCPU_STAT(mmio_exits) }, | |
126 | { "signal_exits", VCPU_STAT(signal_exits) }, | |
127 | { "irq_window", VCPU_STAT(irq_window_exits) }, | |
f08864b4 | 128 | { "nmi_window", VCPU_STAT(nmi_window_exits) }, |
ba1389b7 AK |
129 | { "halt_exits", VCPU_STAT(halt_exits) }, |
130 | { "halt_wakeup", VCPU_STAT(halt_wakeup) }, | |
f11c3a8d | 131 | { "hypercalls", VCPU_STAT(hypercalls) }, |
ba1389b7 AK |
132 | { "request_irq", VCPU_STAT(request_irq_exits) }, |
133 | { "irq_exits", VCPU_STAT(irq_exits) }, | |
134 | { "host_state_reload", VCPU_STAT(host_state_reload) }, | |
135 | { "efer_reload", VCPU_STAT(efer_reload) }, | |
136 | { "fpu_reload", VCPU_STAT(fpu_reload) }, | |
137 | { "insn_emulation", VCPU_STAT(insn_emulation) }, | |
138 | { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, | |
fa89a817 | 139 | { "irq_injections", VCPU_STAT(irq_injections) }, |
c4abb7c9 | 140 | { "nmi_injections", VCPU_STAT(nmi_injections) }, |
4cee5764 AK |
141 | { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, |
142 | { "mmu_pte_write", VM_STAT(mmu_pte_write) }, | |
143 | { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, | |
144 | { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, | |
145 | { "mmu_flooded", VM_STAT(mmu_flooded) }, | |
146 | { "mmu_recycled", VM_STAT(mmu_recycled) }, | |
dfc5aa00 | 147 | { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, |
4731d4c7 | 148 | { "mmu_unsync", VM_STAT(mmu_unsync) }, |
0f74a24c | 149 | { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, |
05da4558 | 150 | { "largepages", VM_STAT(lpages) }, |
417bc304 HB |
151 | { NULL } |
152 | }; | |
153 | ||
2acf923e DC |
154 | u64 __read_mostly host_xcr0; |
155 | ||
156 | static inline u32 bit(int bitno) | |
157 | { | |
158 | return 1 << (bitno & 31); | |
159 | } | |
160 | ||
18863bdd AK |
161 | static void kvm_on_user_return(struct user_return_notifier *urn) |
162 | { | |
163 | unsigned slot; | |
18863bdd AK |
164 | struct kvm_shared_msrs *locals |
165 | = container_of(urn, struct kvm_shared_msrs, urn); | |
2bf78fa7 | 166 | struct kvm_shared_msr_values *values; |
18863bdd AK |
167 | |
168 | for (slot = 0; slot < shared_msrs_global.nr; ++slot) { | |
2bf78fa7 SY |
169 | values = &locals->values[slot]; |
170 | if (values->host != values->curr) { | |
171 | wrmsrl(shared_msrs_global.msrs[slot], values->host); | |
172 | values->curr = values->host; | |
18863bdd AK |
173 | } |
174 | } | |
175 | locals->registered = false; | |
176 | user_return_notifier_unregister(urn); | |
177 | } | |
178 | ||
2bf78fa7 | 179 | static void shared_msr_update(unsigned slot, u32 msr) |
18863bdd | 180 | { |
2bf78fa7 | 181 | struct kvm_shared_msrs *smsr; |
18863bdd AK |
182 | u64 value; |
183 | ||
2bf78fa7 SY |
184 | smsr = &__get_cpu_var(shared_msrs); |
185 | /* only read, and nobody should modify it at this time, | |
186 | * so don't need lock */ | |
187 | if (slot >= shared_msrs_global.nr) { | |
188 | printk(KERN_ERR "kvm: invalid MSR slot!"); | |
189 | return; | |
190 | } | |
191 | rdmsrl_safe(msr, &value); | |
192 | smsr->values[slot].host = value; | |
193 | smsr->values[slot].curr = value; | |
194 | } | |
195 | ||
196 | void kvm_define_shared_msr(unsigned slot, u32 msr) | |
197 | { | |
18863bdd AK |
198 | if (slot >= shared_msrs_global.nr) |
199 | shared_msrs_global.nr = slot + 1; | |
2bf78fa7 SY |
200 | shared_msrs_global.msrs[slot] = msr; |
201 | /* we need ensured the shared_msr_global have been updated */ | |
202 | smp_wmb(); | |
18863bdd AK |
203 | } |
204 | EXPORT_SYMBOL_GPL(kvm_define_shared_msr); | |
205 | ||
206 | static void kvm_shared_msr_cpu_online(void) | |
207 | { | |
208 | unsigned i; | |
18863bdd AK |
209 | |
210 | for (i = 0; i < shared_msrs_global.nr; ++i) | |
2bf78fa7 | 211 | shared_msr_update(i, shared_msrs_global.msrs[i]); |
18863bdd AK |
212 | } |
213 | ||
d5696725 | 214 | void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) |
18863bdd AK |
215 | { |
216 | struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs); | |
217 | ||
2bf78fa7 | 218 | if (((value ^ smsr->values[slot].curr) & mask) == 0) |
18863bdd | 219 | return; |
2bf78fa7 SY |
220 | smsr->values[slot].curr = value; |
221 | wrmsrl(shared_msrs_global.msrs[slot], value); | |
18863bdd AK |
222 | if (!smsr->registered) { |
223 | smsr->urn.on_user_return = kvm_on_user_return; | |
224 | user_return_notifier_register(&smsr->urn); | |
225 | smsr->registered = true; | |
226 | } | |
227 | } | |
228 | EXPORT_SYMBOL_GPL(kvm_set_shared_msr); | |
229 | ||
3548bab5 AK |
230 | static void drop_user_return_notifiers(void *ignore) |
231 | { | |
232 | struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs); | |
233 | ||
234 | if (smsr->registered) | |
235 | kvm_on_user_return(&smsr->urn); | |
236 | } | |
237 | ||
6866b83e CO |
238 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
239 | { | |
240 | if (irqchip_in_kernel(vcpu->kvm)) | |
ad312c7c | 241 | return vcpu->arch.apic_base; |
6866b83e | 242 | else |
ad312c7c | 243 | return vcpu->arch.apic_base; |
6866b83e CO |
244 | } |
245 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
246 | ||
247 | void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data) | |
248 | { | |
249 | /* TODO: reserve bits check */ | |
250 | if (irqchip_in_kernel(vcpu->kvm)) | |
251 | kvm_lapic_set_base(vcpu, data); | |
252 | else | |
ad312c7c | 253 | vcpu->arch.apic_base = data; |
6866b83e CO |
254 | } |
255 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
256 | ||
3fd28fce ED |
257 | #define EXCPT_BENIGN 0 |
258 | #define EXCPT_CONTRIBUTORY 1 | |
259 | #define EXCPT_PF 2 | |
260 | ||
261 | static int exception_class(int vector) | |
262 | { | |
263 | switch (vector) { | |
264 | case PF_VECTOR: | |
265 | return EXCPT_PF; | |
266 | case DE_VECTOR: | |
267 | case TS_VECTOR: | |
268 | case NP_VECTOR: | |
269 | case SS_VECTOR: | |
270 | case GP_VECTOR: | |
271 | return EXCPT_CONTRIBUTORY; | |
272 | default: | |
273 | break; | |
274 | } | |
275 | return EXCPT_BENIGN; | |
276 | } | |
277 | ||
278 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, | |
ce7ddec4 JR |
279 | unsigned nr, bool has_error, u32 error_code, |
280 | bool reinject) | |
3fd28fce ED |
281 | { |
282 | u32 prev_nr; | |
283 | int class1, class2; | |
284 | ||
285 | if (!vcpu->arch.exception.pending) { | |
286 | queue: | |
287 | vcpu->arch.exception.pending = true; | |
288 | vcpu->arch.exception.has_error_code = has_error; | |
289 | vcpu->arch.exception.nr = nr; | |
290 | vcpu->arch.exception.error_code = error_code; | |
3f0fd292 | 291 | vcpu->arch.exception.reinject = reinject; |
3fd28fce ED |
292 | return; |
293 | } | |
294 | ||
295 | /* to check exception */ | |
296 | prev_nr = vcpu->arch.exception.nr; | |
297 | if (prev_nr == DF_VECTOR) { | |
298 | /* triple fault -> shutdown */ | |
a8eeb04a | 299 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
3fd28fce ED |
300 | return; |
301 | } | |
302 | class1 = exception_class(prev_nr); | |
303 | class2 = exception_class(nr); | |
304 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) | |
305 | || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
306 | /* generate double fault per SDM Table 5-5 */ | |
307 | vcpu->arch.exception.pending = true; | |
308 | vcpu->arch.exception.has_error_code = true; | |
309 | vcpu->arch.exception.nr = DF_VECTOR; | |
310 | vcpu->arch.exception.error_code = 0; | |
311 | } else | |
312 | /* replace previous exception with a new one in a hope | |
313 | that instruction re-execution will regenerate lost | |
314 | exception */ | |
315 | goto queue; | |
316 | } | |
317 | ||
298101da AK |
318 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
319 | { | |
ce7ddec4 | 320 | kvm_multiple_exception(vcpu, nr, false, 0, false); |
298101da AK |
321 | } |
322 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
323 | ||
ce7ddec4 JR |
324 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
325 | { | |
326 | kvm_multiple_exception(vcpu, nr, false, 0, true); | |
327 | } | |
328 | EXPORT_SYMBOL_GPL(kvm_requeue_exception); | |
329 | ||
c3c91fee AK |
330 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr, |
331 | u32 error_code) | |
332 | { | |
333 | ++vcpu->stat.pf_guest; | |
ad312c7c | 334 | vcpu->arch.cr2 = addr; |
c3c91fee AK |
335 | kvm_queue_exception_e(vcpu, PF_VECTOR, error_code); |
336 | } | |
337 | ||
3419ffc8 SY |
338 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
339 | { | |
340 | vcpu->arch.nmi_pending = 1; | |
341 | } | |
342 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
343 | ||
298101da AK |
344 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
345 | { | |
ce7ddec4 | 346 | kvm_multiple_exception(vcpu, nr, true, error_code, false); |
298101da AK |
347 | } |
348 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
349 | ||
ce7ddec4 JR |
350 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
351 | { | |
352 | kvm_multiple_exception(vcpu, nr, true, error_code, true); | |
353 | } | |
354 | EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); | |
355 | ||
0a79b009 AK |
356 | /* |
357 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
358 | * a #GP and return false. | |
359 | */ | |
360 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 361 | { |
0a79b009 AK |
362 | if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) |
363 | return true; | |
364 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
365 | return false; | |
298101da | 366 | } |
0a79b009 | 367 | EXPORT_SYMBOL_GPL(kvm_require_cpl); |
298101da | 368 | |
a03490ed CO |
369 | /* |
370 | * Load the pae pdptrs. Return true is they are all valid. | |
371 | */ | |
372 | int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3) | |
373 | { | |
374 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
375 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
376 | int i; | |
377 | int ret; | |
ad312c7c | 378 | u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)]; |
a03490ed | 379 | |
a03490ed CO |
380 | ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte, |
381 | offset * sizeof(u64), sizeof(pdpte)); | |
382 | if (ret < 0) { | |
383 | ret = 0; | |
384 | goto out; | |
385 | } | |
386 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
43a3795a | 387 | if (is_present_gpte(pdpte[i]) && |
20c466b5 | 388 | (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) { |
a03490ed CO |
389 | ret = 0; |
390 | goto out; | |
391 | } | |
392 | } | |
393 | ret = 1; | |
394 | ||
ad312c7c | 395 | memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs)); |
6de4f3ad AK |
396 | __set_bit(VCPU_EXREG_PDPTR, |
397 | (unsigned long *)&vcpu->arch.regs_avail); | |
398 | __set_bit(VCPU_EXREG_PDPTR, | |
399 | (unsigned long *)&vcpu->arch.regs_dirty); | |
a03490ed | 400 | out: |
a03490ed CO |
401 | |
402 | return ret; | |
403 | } | |
cc4b6871 | 404 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 405 | |
d835dfec AK |
406 | static bool pdptrs_changed(struct kvm_vcpu *vcpu) |
407 | { | |
ad312c7c | 408 | u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)]; |
d835dfec AK |
409 | bool changed = true; |
410 | int r; | |
411 | ||
412 | if (is_long_mode(vcpu) || !is_pae(vcpu)) | |
413 | return false; | |
414 | ||
6de4f3ad AK |
415 | if (!test_bit(VCPU_EXREG_PDPTR, |
416 | (unsigned long *)&vcpu->arch.regs_avail)) | |
417 | return true; | |
418 | ||
ad312c7c | 419 | r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte)); |
d835dfec AK |
420 | if (r < 0) |
421 | goto out; | |
ad312c7c | 422 | changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0; |
d835dfec | 423 | out: |
d835dfec AK |
424 | |
425 | return changed; | |
426 | } | |
427 | ||
49a9b07e | 428 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 429 | { |
aad82703 SY |
430 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
431 | unsigned long update_bits = X86_CR0_PG | X86_CR0_WP | | |
432 | X86_CR0_CD | X86_CR0_NW; | |
433 | ||
f9a48e6a AK |
434 | cr0 |= X86_CR0_ET; |
435 | ||
ab344828 | 436 | #ifdef CONFIG_X86_64 |
0f12244f GN |
437 | if (cr0 & 0xffffffff00000000UL) |
438 | return 1; | |
ab344828 GN |
439 | #endif |
440 | ||
441 | cr0 &= ~CR0_RESERVED_BITS; | |
a03490ed | 442 | |
0f12244f GN |
443 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) |
444 | return 1; | |
a03490ed | 445 | |
0f12244f GN |
446 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) |
447 | return 1; | |
a03490ed CO |
448 | |
449 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { | |
450 | #ifdef CONFIG_X86_64 | |
f6801dff | 451 | if ((vcpu->arch.efer & EFER_LME)) { |
a03490ed CO |
452 | int cs_db, cs_l; |
453 | ||
0f12244f GN |
454 | if (!is_pae(vcpu)) |
455 | return 1; | |
a03490ed | 456 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
0f12244f GN |
457 | if (cs_l) |
458 | return 1; | |
a03490ed CO |
459 | } else |
460 | #endif | |
0f12244f GN |
461 | if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) |
462 | return 1; | |
a03490ed CO |
463 | } |
464 | ||
465 | kvm_x86_ops->set_cr0(vcpu, cr0); | |
a03490ed | 466 | |
aad82703 SY |
467 | if ((cr0 ^ old_cr0) & update_bits) |
468 | kvm_mmu_reset_context(vcpu); | |
0f12244f GN |
469 | return 0; |
470 | } | |
2d3ad1f4 | 471 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 472 | |
2d3ad1f4 | 473 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 474 | { |
49a9b07e | 475 | (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); |
a03490ed | 476 | } |
2d3ad1f4 | 477 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 478 | |
2acf923e DC |
479 | int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) |
480 | { | |
481 | u64 xcr0; | |
482 | ||
483 | /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ | |
484 | if (index != XCR_XFEATURE_ENABLED_MASK) | |
485 | return 1; | |
486 | xcr0 = xcr; | |
487 | if (kvm_x86_ops->get_cpl(vcpu) != 0) | |
488 | return 1; | |
489 | if (!(xcr0 & XSTATE_FP)) | |
490 | return 1; | |
491 | if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE)) | |
492 | return 1; | |
493 | if (xcr0 & ~host_xcr0) | |
494 | return 1; | |
495 | vcpu->arch.xcr0 = xcr0; | |
496 | vcpu->guest_xcr0_loaded = 0; | |
497 | return 0; | |
498 | } | |
499 | ||
500 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) | |
501 | { | |
502 | if (__kvm_set_xcr(vcpu, index, xcr)) { | |
503 | kvm_inject_gp(vcpu, 0); | |
504 | return 1; | |
505 | } | |
506 | return 0; | |
507 | } | |
508 | EXPORT_SYMBOL_GPL(kvm_set_xcr); | |
509 | ||
510 | static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu) | |
511 | { | |
512 | struct kvm_cpuid_entry2 *best; | |
513 | ||
514 | best = kvm_find_cpuid_entry(vcpu, 1, 0); | |
515 | return best && (best->ecx & bit(X86_FEATURE_XSAVE)); | |
516 | } | |
517 | ||
518 | static void update_cpuid(struct kvm_vcpu *vcpu) | |
519 | { | |
520 | struct kvm_cpuid_entry2 *best; | |
521 | ||
522 | best = kvm_find_cpuid_entry(vcpu, 1, 0); | |
523 | if (!best) | |
524 | return; | |
525 | ||
526 | /* Update OSXSAVE bit */ | |
527 | if (cpu_has_xsave && best->function == 0x1) { | |
528 | best->ecx &= ~(bit(X86_FEATURE_OSXSAVE)); | |
529 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) | |
530 | best->ecx |= bit(X86_FEATURE_OSXSAVE); | |
531 | } | |
532 | } | |
533 | ||
a83b29c6 | 534 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 535 | { |
fc78f519 | 536 | unsigned long old_cr4 = kvm_read_cr4(vcpu); |
a2edf57f AK |
537 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE; |
538 | ||
0f12244f GN |
539 | if (cr4 & CR4_RESERVED_BITS) |
540 | return 1; | |
a03490ed | 541 | |
2acf923e DC |
542 | if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE)) |
543 | return 1; | |
544 | ||
a03490ed | 545 | if (is_long_mode(vcpu)) { |
0f12244f GN |
546 | if (!(cr4 & X86_CR4_PAE)) |
547 | return 1; | |
a2edf57f AK |
548 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
549 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
0f12244f GN |
550 | && !load_pdptrs(vcpu, vcpu->arch.cr3)) |
551 | return 1; | |
552 | ||
553 | if (cr4 & X86_CR4_VMXE) | |
554 | return 1; | |
a03490ed | 555 | |
a03490ed | 556 | kvm_x86_ops->set_cr4(vcpu, cr4); |
62ad0755 | 557 | |
aad82703 SY |
558 | if ((cr4 ^ old_cr4) & pdptr_bits) |
559 | kvm_mmu_reset_context(vcpu); | |
0f12244f | 560 | |
2acf923e DC |
561 | if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE) |
562 | update_cpuid(vcpu); | |
563 | ||
0f12244f GN |
564 | return 0; |
565 | } | |
2d3ad1f4 | 566 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 567 | |
2390218b | 568 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 569 | { |
ad312c7c | 570 | if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) { |
0ba73cda | 571 | kvm_mmu_sync_roots(vcpu); |
d835dfec | 572 | kvm_mmu_flush_tlb(vcpu); |
0f12244f | 573 | return 0; |
d835dfec AK |
574 | } |
575 | ||
a03490ed | 576 | if (is_long_mode(vcpu)) { |
0f12244f GN |
577 | if (cr3 & CR3_L_MODE_RESERVED_BITS) |
578 | return 1; | |
a03490ed CO |
579 | } else { |
580 | if (is_pae(vcpu)) { | |
0f12244f GN |
581 | if (cr3 & CR3_PAE_RESERVED_BITS) |
582 | return 1; | |
583 | if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) | |
584 | return 1; | |
a03490ed CO |
585 | } |
586 | /* | |
587 | * We don't check reserved bits in nonpae mode, because | |
588 | * this isn't enforced, and VMware depends on this. | |
589 | */ | |
590 | } | |
591 | ||
a03490ed CO |
592 | /* |
593 | * Does the new cr3 value map to physical memory? (Note, we | |
594 | * catch an invalid cr3 even in real-mode, because it would | |
595 | * cause trouble later on when we turn on paging anyway.) | |
596 | * | |
597 | * A real CPU would silently accept an invalid cr3 and would | |
598 | * attempt to use it - with largely undefined (and often hard | |
599 | * to debug) behavior on the guest side. | |
600 | */ | |
601 | if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT))) | |
0f12244f GN |
602 | return 1; |
603 | vcpu->arch.cr3 = cr3; | |
604 | vcpu->arch.mmu.new_cr3(vcpu); | |
605 | return 0; | |
606 | } | |
2d3ad1f4 | 607 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 608 | |
0f12244f | 609 | int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed | 610 | { |
0f12244f GN |
611 | if (cr8 & CR8_RESERVED_BITS) |
612 | return 1; | |
a03490ed CO |
613 | if (irqchip_in_kernel(vcpu->kvm)) |
614 | kvm_lapic_set_tpr(vcpu, cr8); | |
615 | else | |
ad312c7c | 616 | vcpu->arch.cr8 = cr8; |
0f12244f GN |
617 | return 0; |
618 | } | |
619 | ||
620 | void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) | |
621 | { | |
622 | if (__kvm_set_cr8(vcpu, cr8)) | |
623 | kvm_inject_gp(vcpu, 0); | |
a03490ed | 624 | } |
2d3ad1f4 | 625 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 626 | |
2d3ad1f4 | 627 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed CO |
628 | { |
629 | if (irqchip_in_kernel(vcpu->kvm)) | |
630 | return kvm_lapic_get_cr8(vcpu); | |
631 | else | |
ad312c7c | 632 | return vcpu->arch.cr8; |
a03490ed | 633 | } |
2d3ad1f4 | 634 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 635 | |
338dbc97 | 636 | static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) |
020df079 GN |
637 | { |
638 | switch (dr) { | |
639 | case 0 ... 3: | |
640 | vcpu->arch.db[dr] = val; | |
641 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
642 | vcpu->arch.eff_db[dr] = val; | |
643 | break; | |
644 | case 4: | |
338dbc97 GN |
645 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) |
646 | return 1; /* #UD */ | |
020df079 GN |
647 | /* fall through */ |
648 | case 6: | |
338dbc97 GN |
649 | if (val & 0xffffffff00000000ULL) |
650 | return -1; /* #GP */ | |
020df079 GN |
651 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1; |
652 | break; | |
653 | case 5: | |
338dbc97 GN |
654 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) |
655 | return 1; /* #UD */ | |
020df079 GN |
656 | /* fall through */ |
657 | default: /* 7 */ | |
338dbc97 GN |
658 | if (val & 0xffffffff00000000ULL) |
659 | return -1; /* #GP */ | |
020df079 GN |
660 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; |
661 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
662 | kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7); | |
663 | vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK); | |
664 | } | |
665 | break; | |
666 | } | |
667 | ||
668 | return 0; | |
669 | } | |
338dbc97 GN |
670 | |
671 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) | |
672 | { | |
673 | int res; | |
674 | ||
675 | res = __kvm_set_dr(vcpu, dr, val); | |
676 | if (res > 0) | |
677 | kvm_queue_exception(vcpu, UD_VECTOR); | |
678 | else if (res < 0) | |
679 | kvm_inject_gp(vcpu, 0); | |
680 | ||
681 | return res; | |
682 | } | |
020df079 GN |
683 | EXPORT_SYMBOL_GPL(kvm_set_dr); |
684 | ||
338dbc97 | 685 | static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) |
020df079 GN |
686 | { |
687 | switch (dr) { | |
688 | case 0 ... 3: | |
689 | *val = vcpu->arch.db[dr]; | |
690 | break; | |
691 | case 4: | |
338dbc97 | 692 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) |
020df079 | 693 | return 1; |
020df079 GN |
694 | /* fall through */ |
695 | case 6: | |
696 | *val = vcpu->arch.dr6; | |
697 | break; | |
698 | case 5: | |
338dbc97 | 699 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) |
020df079 | 700 | return 1; |
020df079 GN |
701 | /* fall through */ |
702 | default: /* 7 */ | |
703 | *val = vcpu->arch.dr7; | |
704 | break; | |
705 | } | |
706 | ||
707 | return 0; | |
708 | } | |
338dbc97 GN |
709 | |
710 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) | |
711 | { | |
712 | if (_kvm_get_dr(vcpu, dr, val)) { | |
713 | kvm_queue_exception(vcpu, UD_VECTOR); | |
714 | return 1; | |
715 | } | |
716 | return 0; | |
717 | } | |
020df079 GN |
718 | EXPORT_SYMBOL_GPL(kvm_get_dr); |
719 | ||
043405e1 CO |
720 | /* |
721 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
722 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
723 | * | |
724 | * This list is modified at module load time to reflect the | |
e3267cbb GC |
725 | * capabilities of the host cpu. This capabilities test skips MSRs that are |
726 | * kvm-specific. Those are put in the beginning of the list. | |
043405e1 | 727 | */ |
e3267cbb | 728 | |
11c6bffa | 729 | #define KVM_SAVE_MSRS_BEGIN 7 |
043405e1 | 730 | static u32 msrs_to_save[] = { |
e3267cbb | 731 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, |
11c6bffa | 732 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, |
55cd8e5a | 733 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, |
10388a07 | 734 | HV_X64_MSR_APIC_ASSIST_PAGE, |
043405e1 CO |
735 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, |
736 | MSR_K6_STAR, | |
737 | #ifdef CONFIG_X86_64 | |
738 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
739 | #endif | |
e3267cbb | 740 | MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA |
043405e1 CO |
741 | }; |
742 | ||
743 | static unsigned num_msrs_to_save; | |
744 | ||
745 | static u32 emulated_msrs[] = { | |
746 | MSR_IA32_MISC_ENABLE, | |
747 | }; | |
748 | ||
b69e8cae | 749 | static int set_efer(struct kvm_vcpu *vcpu, u64 efer) |
15c4a640 | 750 | { |
aad82703 SY |
751 | u64 old_efer = vcpu->arch.efer; |
752 | ||
b69e8cae RJ |
753 | if (efer & efer_reserved_bits) |
754 | return 1; | |
15c4a640 CO |
755 | |
756 | if (is_paging(vcpu) | |
b69e8cae RJ |
757 | && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) |
758 | return 1; | |
15c4a640 | 759 | |
1b2fd70c AG |
760 | if (efer & EFER_FFXSR) { |
761 | struct kvm_cpuid_entry2 *feat; | |
762 | ||
763 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
b69e8cae RJ |
764 | if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) |
765 | return 1; | |
1b2fd70c AG |
766 | } |
767 | ||
d8017474 AG |
768 | if (efer & EFER_SVME) { |
769 | struct kvm_cpuid_entry2 *feat; | |
770 | ||
771 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
b69e8cae RJ |
772 | if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) |
773 | return 1; | |
d8017474 AG |
774 | } |
775 | ||
15c4a640 | 776 | efer &= ~EFER_LMA; |
f6801dff | 777 | efer |= vcpu->arch.efer & EFER_LMA; |
15c4a640 | 778 | |
a3d204e2 SY |
779 | kvm_x86_ops->set_efer(vcpu, efer); |
780 | ||
9645bb56 AK |
781 | vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled; |
782 | kvm_mmu_reset_context(vcpu); | |
b69e8cae | 783 | |
aad82703 SY |
784 | /* Update reserved bits */ |
785 | if ((efer ^ old_efer) & EFER_NX) | |
786 | kvm_mmu_reset_context(vcpu); | |
787 | ||
b69e8cae | 788 | return 0; |
15c4a640 CO |
789 | } |
790 | ||
f2b4b7dd JR |
791 | void kvm_enable_efer_bits(u64 mask) |
792 | { | |
793 | efer_reserved_bits &= ~mask; | |
794 | } | |
795 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
796 | ||
797 | ||
15c4a640 CO |
798 | /* |
799 | * Writes msr value into into the appropriate "register". | |
800 | * Returns 0 on success, non-0 otherwise. | |
801 | * Assumes vcpu_load() was already called. | |
802 | */ | |
803 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
804 | { | |
805 | return kvm_x86_ops->set_msr(vcpu, msr_index, data); | |
806 | } | |
807 | ||
313a3dc7 CO |
808 | /* |
809 | * Adapt set_msr() to msr_io()'s calling convention | |
810 | */ | |
811 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
812 | { | |
813 | return kvm_set_msr(vcpu, index, *data); | |
814 | } | |
815 | ||
18068523 GOC |
816 | static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) |
817 | { | |
9ed3c444 AK |
818 | int version; |
819 | int r; | |
50d0a0f9 | 820 | struct pvclock_wall_clock wc; |
923de3cf | 821 | struct timespec boot; |
18068523 GOC |
822 | |
823 | if (!wall_clock) | |
824 | return; | |
825 | ||
9ed3c444 AK |
826 | r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); |
827 | if (r) | |
828 | return; | |
829 | ||
830 | if (version & 1) | |
831 | ++version; /* first time write, random junk */ | |
832 | ||
833 | ++version; | |
18068523 | 834 | |
18068523 GOC |
835 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); |
836 | ||
50d0a0f9 GH |
837 | /* |
838 | * The guest calculates current wall clock time by adding | |
839 | * system time (updated by kvm_write_guest_time below) to the | |
840 | * wall clock specified here. guest system time equals host | |
841 | * system time for us, thus we must fill in host boot time here. | |
842 | */ | |
923de3cf | 843 | getboottime(&boot); |
50d0a0f9 GH |
844 | |
845 | wc.sec = boot.tv_sec; | |
846 | wc.nsec = boot.tv_nsec; | |
847 | wc.version = version; | |
18068523 GOC |
848 | |
849 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
850 | ||
851 | version++; | |
852 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
853 | } |
854 | ||
50d0a0f9 GH |
855 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
856 | { | |
857 | uint32_t quotient, remainder; | |
858 | ||
859 | /* Don't try to replace with do_div(), this one calculates | |
860 | * "(dividend << 32) / divisor" */ | |
861 | __asm__ ( "divl %4" | |
862 | : "=a" (quotient), "=d" (remainder) | |
863 | : "0" (0), "1" (dividend), "r" (divisor) ); | |
864 | return quotient; | |
865 | } | |
866 | ||
867 | static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock) | |
868 | { | |
869 | uint64_t nsecs = 1000000000LL; | |
870 | int32_t shift = 0; | |
871 | uint64_t tps64; | |
872 | uint32_t tps32; | |
873 | ||
874 | tps64 = tsc_khz * 1000LL; | |
875 | while (tps64 > nsecs*2) { | |
876 | tps64 >>= 1; | |
877 | shift--; | |
878 | } | |
879 | ||
880 | tps32 = (uint32_t)tps64; | |
881 | while (tps32 <= (uint32_t)nsecs) { | |
882 | tps32 <<= 1; | |
883 | shift++; | |
884 | } | |
885 | ||
886 | hv_clock->tsc_shift = shift; | |
887 | hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32); | |
888 | ||
889 | pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n", | |
80a914dc | 890 | __func__, tsc_khz, hv_clock->tsc_shift, |
50d0a0f9 GH |
891 | hv_clock->tsc_to_system_mul); |
892 | } | |
893 | ||
c8076604 GH |
894 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
895 | ||
18068523 GOC |
896 | static void kvm_write_guest_time(struct kvm_vcpu *v) |
897 | { | |
898 | struct timespec ts; | |
899 | unsigned long flags; | |
900 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
901 | void *shared_kaddr; | |
463656c0 | 902 | unsigned long this_tsc_khz; |
18068523 GOC |
903 | |
904 | if ((!vcpu->time_page)) | |
905 | return; | |
906 | ||
463656c0 AK |
907 | this_tsc_khz = get_cpu_var(cpu_tsc_khz); |
908 | if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) { | |
909 | kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock); | |
910 | vcpu->hv_clock_tsc_khz = this_tsc_khz; | |
50d0a0f9 | 911 | } |
463656c0 | 912 | put_cpu_var(cpu_tsc_khz); |
50d0a0f9 | 913 | |
18068523 GOC |
914 | /* Keep irq disabled to prevent changes to the clock */ |
915 | local_irq_save(flags); | |
af24a4e4 | 916 | kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp); |
18068523 | 917 | ktime_get_ts(&ts); |
923de3cf | 918 | monotonic_to_bootbased(&ts); |
18068523 GOC |
919 | local_irq_restore(flags); |
920 | ||
921 | /* With all the info we got, fill in the values */ | |
922 | ||
923 | vcpu->hv_clock.system_time = ts.tv_nsec + | |
afbcf7ab GC |
924 | (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset; |
925 | ||
371bcf64 GC |
926 | vcpu->hv_clock.flags = 0; |
927 | ||
18068523 GOC |
928 | /* |
929 | * The interface expects us to write an even number signaling that the | |
930 | * update is finished. Since the guest won't see the intermediate | |
50d0a0f9 | 931 | * state, we just increase by 2 at the end. |
18068523 | 932 | */ |
50d0a0f9 | 933 | vcpu->hv_clock.version += 2; |
18068523 GOC |
934 | |
935 | shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0); | |
936 | ||
937 | memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock, | |
50d0a0f9 | 938 | sizeof(vcpu->hv_clock)); |
18068523 GOC |
939 | |
940 | kunmap_atomic(shared_kaddr, KM_USER0); | |
941 | ||
942 | mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT); | |
943 | } | |
944 | ||
c8076604 GH |
945 | static int kvm_request_guest_time_update(struct kvm_vcpu *v) |
946 | { | |
947 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
948 | ||
949 | if (!vcpu->time_page) | |
950 | return 0; | |
a8eeb04a | 951 | kvm_make_request(KVM_REQ_KVMCLOCK_UPDATE, v); |
c8076604 GH |
952 | return 1; |
953 | } | |
954 | ||
9ba075a6 AK |
955 | static bool msr_mtrr_valid(unsigned msr) |
956 | { | |
957 | switch (msr) { | |
958 | case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1: | |
959 | case MSR_MTRRfix64K_00000: | |
960 | case MSR_MTRRfix16K_80000: | |
961 | case MSR_MTRRfix16K_A0000: | |
962 | case MSR_MTRRfix4K_C0000: | |
963 | case MSR_MTRRfix4K_C8000: | |
964 | case MSR_MTRRfix4K_D0000: | |
965 | case MSR_MTRRfix4K_D8000: | |
966 | case MSR_MTRRfix4K_E0000: | |
967 | case MSR_MTRRfix4K_E8000: | |
968 | case MSR_MTRRfix4K_F0000: | |
969 | case MSR_MTRRfix4K_F8000: | |
970 | case MSR_MTRRdefType: | |
971 | case MSR_IA32_CR_PAT: | |
972 | return true; | |
973 | case 0x2f8: | |
974 | return true; | |
975 | } | |
976 | return false; | |
977 | } | |
978 | ||
d6289b93 MT |
979 | static bool valid_pat_type(unsigned t) |
980 | { | |
981 | return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */ | |
982 | } | |
983 | ||
984 | static bool valid_mtrr_type(unsigned t) | |
985 | { | |
986 | return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */ | |
987 | } | |
988 | ||
989 | static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
990 | { | |
991 | int i; | |
992 | ||
993 | if (!msr_mtrr_valid(msr)) | |
994 | return false; | |
995 | ||
996 | if (msr == MSR_IA32_CR_PAT) { | |
997 | for (i = 0; i < 8; i++) | |
998 | if (!valid_pat_type((data >> (i * 8)) & 0xff)) | |
999 | return false; | |
1000 | return true; | |
1001 | } else if (msr == MSR_MTRRdefType) { | |
1002 | if (data & ~0xcff) | |
1003 | return false; | |
1004 | return valid_mtrr_type(data & 0xff); | |
1005 | } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) { | |
1006 | for (i = 0; i < 8 ; i++) | |
1007 | if (!valid_mtrr_type((data >> (i * 8)) & 0xff)) | |
1008 | return false; | |
1009 | return true; | |
1010 | } | |
1011 | ||
1012 | /* variable MTRRs */ | |
1013 | return valid_mtrr_type(data & 0xff); | |
1014 | } | |
1015 | ||
9ba075a6 AK |
1016 | static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
1017 | { | |
0bed3b56 SY |
1018 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; |
1019 | ||
d6289b93 | 1020 | if (!mtrr_valid(vcpu, msr, data)) |
9ba075a6 AK |
1021 | return 1; |
1022 | ||
0bed3b56 SY |
1023 | if (msr == MSR_MTRRdefType) { |
1024 | vcpu->arch.mtrr_state.def_type = data; | |
1025 | vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10; | |
1026 | } else if (msr == MSR_MTRRfix64K_00000) | |
1027 | p[0] = data; | |
1028 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
1029 | p[1 + msr - MSR_MTRRfix16K_80000] = data; | |
1030 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
1031 | p[3 + msr - MSR_MTRRfix4K_C0000] = data; | |
1032 | else if (msr == MSR_IA32_CR_PAT) | |
1033 | vcpu->arch.pat = data; | |
1034 | else { /* Variable MTRRs */ | |
1035 | int idx, is_mtrr_mask; | |
1036 | u64 *pt; | |
1037 | ||
1038 | idx = (msr - 0x200) / 2; | |
1039 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
1040 | if (!is_mtrr_mask) | |
1041 | pt = | |
1042 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
1043 | else | |
1044 | pt = | |
1045 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
1046 | *pt = data; | |
1047 | } | |
1048 | ||
1049 | kvm_mmu_reset_context(vcpu); | |
9ba075a6 AK |
1050 | return 0; |
1051 | } | |
15c4a640 | 1052 | |
890ca9ae | 1053 | static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
15c4a640 | 1054 | { |
890ca9ae HY |
1055 | u64 mcg_cap = vcpu->arch.mcg_cap; |
1056 | unsigned bank_num = mcg_cap & 0xff; | |
1057 | ||
15c4a640 | 1058 | switch (msr) { |
15c4a640 | 1059 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 1060 | vcpu->arch.mcg_status = data; |
15c4a640 | 1061 | break; |
c7ac679c | 1062 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
1063 | if (!(mcg_cap & MCG_CTL_P)) |
1064 | return 1; | |
1065 | if (data != 0 && data != ~(u64)0) | |
1066 | return -1; | |
1067 | vcpu->arch.mcg_ctl = data; | |
1068 | break; | |
1069 | default: | |
1070 | if (msr >= MSR_IA32_MC0_CTL && | |
1071 | msr < MSR_IA32_MC0_CTL + 4 * bank_num) { | |
1072 | u32 offset = msr - MSR_IA32_MC0_CTL; | |
114be429 AP |
1073 | /* only 0 or all 1s can be written to IA32_MCi_CTL |
1074 | * some Linux kernels though clear bit 10 in bank 4 to | |
1075 | * workaround a BIOS/GART TBL issue on AMD K8s, ignore | |
1076 | * this to avoid an uncatched #GP in the guest | |
1077 | */ | |
890ca9ae | 1078 | if ((offset & 0x3) == 0 && |
114be429 | 1079 | data != 0 && (data | (1 << 10)) != ~(u64)0) |
890ca9ae HY |
1080 | return -1; |
1081 | vcpu->arch.mce_banks[offset] = data; | |
1082 | break; | |
1083 | } | |
1084 | return 1; | |
1085 | } | |
1086 | return 0; | |
1087 | } | |
1088 | ||
ffde22ac ES |
1089 | static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) |
1090 | { | |
1091 | struct kvm *kvm = vcpu->kvm; | |
1092 | int lm = is_long_mode(vcpu); | |
1093 | u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 | |
1094 | : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; | |
1095 | u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 | |
1096 | : kvm->arch.xen_hvm_config.blob_size_32; | |
1097 | u32 page_num = data & ~PAGE_MASK; | |
1098 | u64 page_addr = data & PAGE_MASK; | |
1099 | u8 *page; | |
1100 | int r; | |
1101 | ||
1102 | r = -E2BIG; | |
1103 | if (page_num >= blob_size) | |
1104 | goto out; | |
1105 | r = -ENOMEM; | |
1106 | page = kzalloc(PAGE_SIZE, GFP_KERNEL); | |
1107 | if (!page) | |
1108 | goto out; | |
1109 | r = -EFAULT; | |
1110 | if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE)) | |
1111 | goto out_free; | |
1112 | if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE)) | |
1113 | goto out_free; | |
1114 | r = 0; | |
1115 | out_free: | |
1116 | kfree(page); | |
1117 | out: | |
1118 | return r; | |
1119 | } | |
1120 | ||
55cd8e5a GN |
1121 | static bool kvm_hv_hypercall_enabled(struct kvm *kvm) |
1122 | { | |
1123 | return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE; | |
1124 | } | |
1125 | ||
1126 | static bool kvm_hv_msr_partition_wide(u32 msr) | |
1127 | { | |
1128 | bool r = false; | |
1129 | switch (msr) { | |
1130 | case HV_X64_MSR_GUEST_OS_ID: | |
1131 | case HV_X64_MSR_HYPERCALL: | |
1132 | r = true; | |
1133 | break; | |
1134 | } | |
1135 | ||
1136 | return r; | |
1137 | } | |
1138 | ||
1139 | static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1140 | { | |
1141 | struct kvm *kvm = vcpu->kvm; | |
1142 | ||
1143 | switch (msr) { | |
1144 | case HV_X64_MSR_GUEST_OS_ID: | |
1145 | kvm->arch.hv_guest_os_id = data; | |
1146 | /* setting guest os id to zero disables hypercall page */ | |
1147 | if (!kvm->arch.hv_guest_os_id) | |
1148 | kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE; | |
1149 | break; | |
1150 | case HV_X64_MSR_HYPERCALL: { | |
1151 | u64 gfn; | |
1152 | unsigned long addr; | |
1153 | u8 instructions[4]; | |
1154 | ||
1155 | /* if guest os id is not set hypercall should remain disabled */ | |
1156 | if (!kvm->arch.hv_guest_os_id) | |
1157 | break; | |
1158 | if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) { | |
1159 | kvm->arch.hv_hypercall = data; | |
1160 | break; | |
1161 | } | |
1162 | gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT; | |
1163 | addr = gfn_to_hva(kvm, gfn); | |
1164 | if (kvm_is_error_hva(addr)) | |
1165 | return 1; | |
1166 | kvm_x86_ops->patch_hypercall(vcpu, instructions); | |
1167 | ((unsigned char *)instructions)[3] = 0xc3; /* ret */ | |
1168 | if (copy_to_user((void __user *)addr, instructions, 4)) | |
1169 | return 1; | |
1170 | kvm->arch.hv_hypercall = data; | |
1171 | break; | |
1172 | } | |
1173 | default: | |
1174 | pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " | |
1175 | "data 0x%llx\n", msr, data); | |
1176 | return 1; | |
1177 | } | |
1178 | return 0; | |
1179 | } | |
1180 | ||
1181 | static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1182 | { | |
10388a07 GN |
1183 | switch (msr) { |
1184 | case HV_X64_MSR_APIC_ASSIST_PAGE: { | |
1185 | unsigned long addr; | |
55cd8e5a | 1186 | |
10388a07 GN |
1187 | if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) { |
1188 | vcpu->arch.hv_vapic = data; | |
1189 | break; | |
1190 | } | |
1191 | addr = gfn_to_hva(vcpu->kvm, data >> | |
1192 | HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT); | |
1193 | if (kvm_is_error_hva(addr)) | |
1194 | return 1; | |
1195 | if (clear_user((void __user *)addr, PAGE_SIZE)) | |
1196 | return 1; | |
1197 | vcpu->arch.hv_vapic = data; | |
1198 | break; | |
1199 | } | |
1200 | case HV_X64_MSR_EOI: | |
1201 | return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data); | |
1202 | case HV_X64_MSR_ICR: | |
1203 | return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data); | |
1204 | case HV_X64_MSR_TPR: | |
1205 | return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data); | |
1206 | default: | |
1207 | pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " | |
1208 | "data 0x%llx\n", msr, data); | |
1209 | return 1; | |
1210 | } | |
1211 | ||
1212 | return 0; | |
55cd8e5a GN |
1213 | } |
1214 | ||
15c4a640 CO |
1215 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
1216 | { | |
1217 | switch (msr) { | |
15c4a640 | 1218 | case MSR_EFER: |
b69e8cae | 1219 | return set_efer(vcpu, data); |
8f1589d9 AP |
1220 | case MSR_K7_HWCR: |
1221 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
82494028 | 1222 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ |
8f1589d9 AP |
1223 | if (data != 0) { |
1224 | pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", | |
1225 | data); | |
1226 | return 1; | |
1227 | } | |
15c4a640 | 1228 | break; |
f7c6d140 AP |
1229 | case MSR_FAM10H_MMIO_CONF_BASE: |
1230 | if (data != 0) { | |
1231 | pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " | |
1232 | "0x%llx\n", data); | |
1233 | return 1; | |
1234 | } | |
15c4a640 | 1235 | break; |
c323c0e5 | 1236 | case MSR_AMD64_NB_CFG: |
c7ac679c | 1237 | break; |
b5e2fec0 AG |
1238 | case MSR_IA32_DEBUGCTLMSR: |
1239 | if (!data) { | |
1240 | /* We support the non-activated case already */ | |
1241 | break; | |
1242 | } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { | |
1243 | /* Values other than LBR and BTF are vendor-specific, | |
1244 | thus reserved and should throw a #GP */ | |
1245 | return 1; | |
1246 | } | |
1247 | pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", | |
1248 | __func__, data); | |
1249 | break; | |
15c4a640 CO |
1250 | case MSR_IA32_UCODE_REV: |
1251 | case MSR_IA32_UCODE_WRITE: | |
61a6bd67 | 1252 | case MSR_VM_HSAVE_PA: |
6098ca93 | 1253 | case MSR_AMD64_PATCH_LOADER: |
15c4a640 | 1254 | break; |
9ba075a6 AK |
1255 | case 0x200 ... 0x2ff: |
1256 | return set_msr_mtrr(vcpu, msr, data); | |
15c4a640 CO |
1257 | case MSR_IA32_APICBASE: |
1258 | kvm_set_apic_base(vcpu, data); | |
1259 | break; | |
0105d1a5 GN |
1260 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
1261 | return kvm_x2apic_msr_write(vcpu, msr, data); | |
15c4a640 | 1262 | case MSR_IA32_MISC_ENABLE: |
ad312c7c | 1263 | vcpu->arch.ia32_misc_enable_msr = data; |
15c4a640 | 1264 | break; |
11c6bffa | 1265 | case MSR_KVM_WALL_CLOCK_NEW: |
18068523 GOC |
1266 | case MSR_KVM_WALL_CLOCK: |
1267 | vcpu->kvm->arch.wall_clock = data; | |
1268 | kvm_write_wall_clock(vcpu->kvm, data); | |
1269 | break; | |
11c6bffa | 1270 | case MSR_KVM_SYSTEM_TIME_NEW: |
18068523 GOC |
1271 | case MSR_KVM_SYSTEM_TIME: { |
1272 | if (vcpu->arch.time_page) { | |
1273 | kvm_release_page_dirty(vcpu->arch.time_page); | |
1274 | vcpu->arch.time_page = NULL; | |
1275 | } | |
1276 | ||
1277 | vcpu->arch.time = data; | |
1278 | ||
1279 | /* we verify if the enable bit is set... */ | |
1280 | if (!(data & 1)) | |
1281 | break; | |
1282 | ||
1283 | /* ...but clean it before doing the actual write */ | |
1284 | vcpu->arch.time_offset = data & ~(PAGE_MASK | 1); | |
1285 | ||
18068523 GOC |
1286 | vcpu->arch.time_page = |
1287 | gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT); | |
18068523 GOC |
1288 | |
1289 | if (is_error_page(vcpu->arch.time_page)) { | |
1290 | kvm_release_page_clean(vcpu->arch.time_page); | |
1291 | vcpu->arch.time_page = NULL; | |
1292 | } | |
1293 | ||
c8076604 | 1294 | kvm_request_guest_time_update(vcpu); |
18068523 GOC |
1295 | break; |
1296 | } | |
890ca9ae HY |
1297 | case MSR_IA32_MCG_CTL: |
1298 | case MSR_IA32_MCG_STATUS: | |
1299 | case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1: | |
1300 | return set_msr_mce(vcpu, msr, data); | |
71db6023 AP |
1301 | |
1302 | /* Performance counters are not protected by a CPUID bit, | |
1303 | * so we should check all of them in the generic path for the sake of | |
1304 | * cross vendor migration. | |
1305 | * Writing a zero into the event select MSRs disables them, | |
1306 | * which we perfectly emulate ;-). Any other value should be at least | |
1307 | * reported, some guests depend on them. | |
1308 | */ | |
1309 | case MSR_P6_EVNTSEL0: | |
1310 | case MSR_P6_EVNTSEL1: | |
1311 | case MSR_K7_EVNTSEL0: | |
1312 | case MSR_K7_EVNTSEL1: | |
1313 | case MSR_K7_EVNTSEL2: | |
1314 | case MSR_K7_EVNTSEL3: | |
1315 | if (data != 0) | |
1316 | pr_unimpl(vcpu, "unimplemented perfctr wrmsr: " | |
1317 | "0x%x data 0x%llx\n", msr, data); | |
1318 | break; | |
1319 | /* at least RHEL 4 unconditionally writes to the perfctr registers, | |
1320 | * so we ignore writes to make it happy. | |
1321 | */ | |
1322 | case MSR_P6_PERFCTR0: | |
1323 | case MSR_P6_PERFCTR1: | |
1324 | case MSR_K7_PERFCTR0: | |
1325 | case MSR_K7_PERFCTR1: | |
1326 | case MSR_K7_PERFCTR2: | |
1327 | case MSR_K7_PERFCTR3: | |
1328 | pr_unimpl(vcpu, "unimplemented perfctr wrmsr: " | |
1329 | "0x%x data 0x%llx\n", msr, data); | |
1330 | break; | |
55cd8e5a GN |
1331 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
1332 | if (kvm_hv_msr_partition_wide(msr)) { | |
1333 | int r; | |
1334 | mutex_lock(&vcpu->kvm->lock); | |
1335 | r = set_msr_hyperv_pw(vcpu, msr, data); | |
1336 | mutex_unlock(&vcpu->kvm->lock); | |
1337 | return r; | |
1338 | } else | |
1339 | return set_msr_hyperv(vcpu, msr, data); | |
1340 | break; | |
15c4a640 | 1341 | default: |
ffde22ac ES |
1342 | if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) |
1343 | return xen_hvm_config(vcpu, data); | |
ed85c068 AP |
1344 | if (!ignore_msrs) { |
1345 | pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", | |
1346 | msr, data); | |
1347 | return 1; | |
1348 | } else { | |
1349 | pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", | |
1350 | msr, data); | |
1351 | break; | |
1352 | } | |
15c4a640 CO |
1353 | } |
1354 | return 0; | |
1355 | } | |
1356 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
1357 | ||
1358 | ||
1359 | /* | |
1360 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
1361 | * Returns 0 on success, non-0 otherwise. | |
1362 | * Assumes vcpu_load() was already called. | |
1363 | */ | |
1364 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
1365 | { | |
1366 | return kvm_x86_ops->get_msr(vcpu, msr_index, pdata); | |
1367 | } | |
1368 | ||
9ba075a6 AK |
1369 | static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
1370 | { | |
0bed3b56 SY |
1371 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; |
1372 | ||
9ba075a6 AK |
1373 | if (!msr_mtrr_valid(msr)) |
1374 | return 1; | |
1375 | ||
0bed3b56 SY |
1376 | if (msr == MSR_MTRRdefType) |
1377 | *pdata = vcpu->arch.mtrr_state.def_type + | |
1378 | (vcpu->arch.mtrr_state.enabled << 10); | |
1379 | else if (msr == MSR_MTRRfix64K_00000) | |
1380 | *pdata = p[0]; | |
1381 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
1382 | *pdata = p[1 + msr - MSR_MTRRfix16K_80000]; | |
1383 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
1384 | *pdata = p[3 + msr - MSR_MTRRfix4K_C0000]; | |
1385 | else if (msr == MSR_IA32_CR_PAT) | |
1386 | *pdata = vcpu->arch.pat; | |
1387 | else { /* Variable MTRRs */ | |
1388 | int idx, is_mtrr_mask; | |
1389 | u64 *pt; | |
1390 | ||
1391 | idx = (msr - 0x200) / 2; | |
1392 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
1393 | if (!is_mtrr_mask) | |
1394 | pt = | |
1395 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
1396 | else | |
1397 | pt = | |
1398 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
1399 | *pdata = *pt; | |
1400 | } | |
1401 | ||
9ba075a6 AK |
1402 | return 0; |
1403 | } | |
1404 | ||
890ca9ae | 1405 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
15c4a640 CO |
1406 | { |
1407 | u64 data; | |
890ca9ae HY |
1408 | u64 mcg_cap = vcpu->arch.mcg_cap; |
1409 | unsigned bank_num = mcg_cap & 0xff; | |
15c4a640 CO |
1410 | |
1411 | switch (msr) { | |
15c4a640 CO |
1412 | case MSR_IA32_P5_MC_ADDR: |
1413 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
1414 | data = 0; |
1415 | break; | |
15c4a640 | 1416 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
1417 | data = vcpu->arch.mcg_cap; |
1418 | break; | |
c7ac679c | 1419 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
1420 | if (!(mcg_cap & MCG_CTL_P)) |
1421 | return 1; | |
1422 | data = vcpu->arch.mcg_ctl; | |
1423 | break; | |
1424 | case MSR_IA32_MCG_STATUS: | |
1425 | data = vcpu->arch.mcg_status; | |
1426 | break; | |
1427 | default: | |
1428 | if (msr >= MSR_IA32_MC0_CTL && | |
1429 | msr < MSR_IA32_MC0_CTL + 4 * bank_num) { | |
1430 | u32 offset = msr - MSR_IA32_MC0_CTL; | |
1431 | data = vcpu->arch.mce_banks[offset]; | |
1432 | break; | |
1433 | } | |
1434 | return 1; | |
1435 | } | |
1436 | *pdata = data; | |
1437 | return 0; | |
1438 | } | |
1439 | ||
55cd8e5a GN |
1440 | static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
1441 | { | |
1442 | u64 data = 0; | |
1443 | struct kvm *kvm = vcpu->kvm; | |
1444 | ||
1445 | switch (msr) { | |
1446 | case HV_X64_MSR_GUEST_OS_ID: | |
1447 | data = kvm->arch.hv_guest_os_id; | |
1448 | break; | |
1449 | case HV_X64_MSR_HYPERCALL: | |
1450 | data = kvm->arch.hv_hypercall; | |
1451 | break; | |
1452 | default: | |
1453 | pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); | |
1454 | return 1; | |
1455 | } | |
1456 | ||
1457 | *pdata = data; | |
1458 | return 0; | |
1459 | } | |
1460 | ||
1461 | static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) | |
1462 | { | |
1463 | u64 data = 0; | |
1464 | ||
1465 | switch (msr) { | |
1466 | case HV_X64_MSR_VP_INDEX: { | |
1467 | int r; | |
1468 | struct kvm_vcpu *v; | |
1469 | kvm_for_each_vcpu(r, v, vcpu->kvm) | |
1470 | if (v == vcpu) | |
1471 | data = r; | |
1472 | break; | |
1473 | } | |
10388a07 GN |
1474 | case HV_X64_MSR_EOI: |
1475 | return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata); | |
1476 | case HV_X64_MSR_ICR: | |
1477 | return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata); | |
1478 | case HV_X64_MSR_TPR: | |
1479 | return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata); | |
55cd8e5a GN |
1480 | default: |
1481 | pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); | |
1482 | return 1; | |
1483 | } | |
1484 | *pdata = data; | |
1485 | return 0; | |
1486 | } | |
1487 | ||
890ca9ae HY |
1488 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
1489 | { | |
1490 | u64 data; | |
1491 | ||
1492 | switch (msr) { | |
890ca9ae | 1493 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 1494 | case MSR_IA32_UCODE_REV: |
15c4a640 | 1495 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
1496 | case MSR_IA32_DEBUGCTLMSR: |
1497 | case MSR_IA32_LASTBRANCHFROMIP: | |
1498 | case MSR_IA32_LASTBRANCHTOIP: | |
1499 | case MSR_IA32_LASTINTFROMIP: | |
1500 | case MSR_IA32_LASTINTTOIP: | |
60af2ecd JSR |
1501 | case MSR_K8_SYSCFG: |
1502 | case MSR_K7_HWCR: | |
61a6bd67 | 1503 | case MSR_VM_HSAVE_PA: |
1f3ee616 AS |
1504 | case MSR_P6_PERFCTR0: |
1505 | case MSR_P6_PERFCTR1: | |
7fe29e0f AS |
1506 | case MSR_P6_EVNTSEL0: |
1507 | case MSR_P6_EVNTSEL1: | |
9e699624 | 1508 | case MSR_K7_EVNTSEL0: |
1f3ee616 | 1509 | case MSR_K7_PERFCTR0: |
1fdbd48c | 1510 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 1511 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 1512 | case MSR_FAM10H_MMIO_CONF_BASE: |
15c4a640 CO |
1513 | data = 0; |
1514 | break; | |
9ba075a6 AK |
1515 | case MSR_MTRRcap: |
1516 | data = 0x500 | KVM_NR_VAR_MTRR; | |
1517 | break; | |
1518 | case 0x200 ... 0x2ff: | |
1519 | return get_msr_mtrr(vcpu, msr, pdata); | |
15c4a640 CO |
1520 | case 0xcd: /* fsb frequency */ |
1521 | data = 3; | |
1522 | break; | |
1523 | case MSR_IA32_APICBASE: | |
1524 | data = kvm_get_apic_base(vcpu); | |
1525 | break; | |
0105d1a5 GN |
1526 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
1527 | return kvm_x2apic_msr_read(vcpu, msr, pdata); | |
1528 | break; | |
15c4a640 | 1529 | case MSR_IA32_MISC_ENABLE: |
ad312c7c | 1530 | data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 1531 | break; |
847f0ad8 AG |
1532 | case MSR_IA32_PERF_STATUS: |
1533 | /* TSC increment by tick */ | |
1534 | data = 1000ULL; | |
1535 | /* CPU multiplier */ | |
1536 | data |= (((uint64_t)4ULL) << 40); | |
1537 | break; | |
15c4a640 | 1538 | case MSR_EFER: |
f6801dff | 1539 | data = vcpu->arch.efer; |
15c4a640 | 1540 | break; |
18068523 | 1541 | case MSR_KVM_WALL_CLOCK: |
11c6bffa | 1542 | case MSR_KVM_WALL_CLOCK_NEW: |
18068523 GOC |
1543 | data = vcpu->kvm->arch.wall_clock; |
1544 | break; | |
1545 | case MSR_KVM_SYSTEM_TIME: | |
11c6bffa | 1546 | case MSR_KVM_SYSTEM_TIME_NEW: |
18068523 GOC |
1547 | data = vcpu->arch.time; |
1548 | break; | |
890ca9ae HY |
1549 | case MSR_IA32_P5_MC_ADDR: |
1550 | case MSR_IA32_P5_MC_TYPE: | |
1551 | case MSR_IA32_MCG_CAP: | |
1552 | case MSR_IA32_MCG_CTL: | |
1553 | case MSR_IA32_MCG_STATUS: | |
1554 | case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1: | |
1555 | return get_msr_mce(vcpu, msr, pdata); | |
55cd8e5a GN |
1556 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
1557 | if (kvm_hv_msr_partition_wide(msr)) { | |
1558 | int r; | |
1559 | mutex_lock(&vcpu->kvm->lock); | |
1560 | r = get_msr_hyperv_pw(vcpu, msr, pdata); | |
1561 | mutex_unlock(&vcpu->kvm->lock); | |
1562 | return r; | |
1563 | } else | |
1564 | return get_msr_hyperv(vcpu, msr, pdata); | |
1565 | break; | |
15c4a640 | 1566 | default: |
ed85c068 AP |
1567 | if (!ignore_msrs) { |
1568 | pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr); | |
1569 | return 1; | |
1570 | } else { | |
1571 | pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr); | |
1572 | data = 0; | |
1573 | } | |
1574 | break; | |
15c4a640 CO |
1575 | } |
1576 | *pdata = data; | |
1577 | return 0; | |
1578 | } | |
1579 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
1580 | ||
313a3dc7 CO |
1581 | /* |
1582 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
1583 | * | |
1584 | * @return number of msrs set successfully. | |
1585 | */ | |
1586 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
1587 | struct kvm_msr_entry *entries, | |
1588 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
1589 | unsigned index, u64 *data)) | |
1590 | { | |
f656ce01 | 1591 | int i, idx; |
313a3dc7 | 1592 | |
f656ce01 | 1593 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
313a3dc7 CO |
1594 | for (i = 0; i < msrs->nmsrs; ++i) |
1595 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
1596 | break; | |
f656ce01 | 1597 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 1598 | |
313a3dc7 CO |
1599 | return i; |
1600 | } | |
1601 | ||
1602 | /* | |
1603 | * Read or write a bunch of msrs. Parameters are user addresses. | |
1604 | * | |
1605 | * @return number of msrs set successfully. | |
1606 | */ | |
1607 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
1608 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
1609 | unsigned index, u64 *data), | |
1610 | int writeback) | |
1611 | { | |
1612 | struct kvm_msrs msrs; | |
1613 | struct kvm_msr_entry *entries; | |
1614 | int r, n; | |
1615 | unsigned size; | |
1616 | ||
1617 | r = -EFAULT; | |
1618 | if (copy_from_user(&msrs, user_msrs, sizeof msrs)) | |
1619 | goto out; | |
1620 | ||
1621 | r = -E2BIG; | |
1622 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
1623 | goto out; | |
1624 | ||
1625 | r = -ENOMEM; | |
1626 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; | |
7a73c028 | 1627 | entries = kmalloc(size, GFP_KERNEL); |
313a3dc7 CO |
1628 | if (!entries) |
1629 | goto out; | |
1630 | ||
1631 | r = -EFAULT; | |
1632 | if (copy_from_user(entries, user_msrs->entries, size)) | |
1633 | goto out_free; | |
1634 | ||
1635 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
1636 | if (r < 0) | |
1637 | goto out_free; | |
1638 | ||
1639 | r = -EFAULT; | |
1640 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
1641 | goto out_free; | |
1642 | ||
1643 | r = n; | |
1644 | ||
1645 | out_free: | |
7a73c028 | 1646 | kfree(entries); |
313a3dc7 CO |
1647 | out: |
1648 | return r; | |
1649 | } | |
1650 | ||
018d00d2 ZX |
1651 | int kvm_dev_ioctl_check_extension(long ext) |
1652 | { | |
1653 | int r; | |
1654 | ||
1655 | switch (ext) { | |
1656 | case KVM_CAP_IRQCHIP: | |
1657 | case KVM_CAP_HLT: | |
1658 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 1659 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 1660 | case KVM_CAP_EXT_CPUID: |
c8076604 | 1661 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 1662 | case KVM_CAP_PIT: |
a28e4f5a | 1663 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 1664 | case KVM_CAP_MP_STATE: |
ed848624 | 1665 | case KVM_CAP_SYNC_MMU: |
52d939a0 | 1666 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 1667 | case KVM_CAP_IRQ_INJECT_STATUS: |
e56d532f | 1668 | case KVM_CAP_ASSIGN_DEV_IRQ: |
721eecbf | 1669 | case KVM_CAP_IRQFD: |
d34e6b17 | 1670 | case KVM_CAP_IOEVENTFD: |
c5ff41ce | 1671 | case KVM_CAP_PIT2: |
e9f42757 | 1672 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 1673 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
ffde22ac | 1674 | case KVM_CAP_XEN_HVM: |
afbcf7ab | 1675 | case KVM_CAP_ADJUST_CLOCK: |
3cfc3092 | 1676 | case KVM_CAP_VCPU_EVENTS: |
55cd8e5a | 1677 | case KVM_CAP_HYPERV: |
10388a07 | 1678 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 1679 | case KVM_CAP_HYPERV_SPIN: |
ab9f4ecb | 1680 | case KVM_CAP_PCI_SEGMENT: |
a1efbe77 | 1681 | case KVM_CAP_DEBUGREGS: |
d2be1651 | 1682 | case KVM_CAP_X86_ROBUST_SINGLESTEP: |
2d5b5a66 | 1683 | case KVM_CAP_XSAVE: |
018d00d2 ZX |
1684 | r = 1; |
1685 | break; | |
542472b5 LV |
1686 | case KVM_CAP_COALESCED_MMIO: |
1687 | r = KVM_COALESCED_MMIO_PAGE_OFFSET; | |
1688 | break; | |
774ead3a AK |
1689 | case KVM_CAP_VAPIC: |
1690 | r = !kvm_x86_ops->cpu_has_accelerated_tpr(); | |
1691 | break; | |
f725230a AK |
1692 | case KVM_CAP_NR_VCPUS: |
1693 | r = KVM_MAX_VCPUS; | |
1694 | break; | |
a988b910 AK |
1695 | case KVM_CAP_NR_MEMSLOTS: |
1696 | r = KVM_MEMORY_SLOTS; | |
1697 | break; | |
a68a6a72 MT |
1698 | case KVM_CAP_PV_MMU: /* obsolete */ |
1699 | r = 0; | |
2f333bcb | 1700 | break; |
62c476c7 | 1701 | case KVM_CAP_IOMMU: |
19de40a8 | 1702 | r = iommu_found(); |
62c476c7 | 1703 | break; |
890ca9ae HY |
1704 | case KVM_CAP_MCE: |
1705 | r = KVM_MAX_MCE_BANKS; | |
1706 | break; | |
2d5b5a66 SY |
1707 | case KVM_CAP_XCRS: |
1708 | r = cpu_has_xsave; | |
1709 | break; | |
018d00d2 ZX |
1710 | default: |
1711 | r = 0; | |
1712 | break; | |
1713 | } | |
1714 | return r; | |
1715 | ||
1716 | } | |
1717 | ||
043405e1 CO |
1718 | long kvm_arch_dev_ioctl(struct file *filp, |
1719 | unsigned int ioctl, unsigned long arg) | |
1720 | { | |
1721 | void __user *argp = (void __user *)arg; | |
1722 | long r; | |
1723 | ||
1724 | switch (ioctl) { | |
1725 | case KVM_GET_MSR_INDEX_LIST: { | |
1726 | struct kvm_msr_list __user *user_msr_list = argp; | |
1727 | struct kvm_msr_list msr_list; | |
1728 | unsigned n; | |
1729 | ||
1730 | r = -EFAULT; | |
1731 | if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) | |
1732 | goto out; | |
1733 | n = msr_list.nmsrs; | |
1734 | msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs); | |
1735 | if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) | |
1736 | goto out; | |
1737 | r = -E2BIG; | |
e125e7b6 | 1738 | if (n < msr_list.nmsrs) |
043405e1 CO |
1739 | goto out; |
1740 | r = -EFAULT; | |
1741 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
1742 | num_msrs_to_save * sizeof(u32))) | |
1743 | goto out; | |
e125e7b6 | 1744 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 CO |
1745 | &emulated_msrs, |
1746 | ARRAY_SIZE(emulated_msrs) * sizeof(u32))) | |
1747 | goto out; | |
1748 | r = 0; | |
1749 | break; | |
1750 | } | |
674eea0f AK |
1751 | case KVM_GET_SUPPORTED_CPUID: { |
1752 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
1753 | struct kvm_cpuid2 cpuid; | |
1754 | ||
1755 | r = -EFAULT; | |
1756 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
1757 | goto out; | |
1758 | r = kvm_dev_ioctl_get_supported_cpuid(&cpuid, | |
19355475 | 1759 | cpuid_arg->entries); |
674eea0f AK |
1760 | if (r) |
1761 | goto out; | |
1762 | ||
1763 | r = -EFAULT; | |
1764 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
1765 | goto out; | |
1766 | r = 0; | |
1767 | break; | |
1768 | } | |
890ca9ae HY |
1769 | case KVM_X86_GET_MCE_CAP_SUPPORTED: { |
1770 | u64 mce_cap; | |
1771 | ||
1772 | mce_cap = KVM_MCE_CAP_SUPPORTED; | |
1773 | r = -EFAULT; | |
1774 | if (copy_to_user(argp, &mce_cap, sizeof mce_cap)) | |
1775 | goto out; | |
1776 | r = 0; | |
1777 | break; | |
1778 | } | |
043405e1 CO |
1779 | default: |
1780 | r = -EINVAL; | |
1781 | } | |
1782 | out: | |
1783 | return r; | |
1784 | } | |
1785 | ||
f5f48ee1 SY |
1786 | static void wbinvd_ipi(void *garbage) |
1787 | { | |
1788 | wbinvd(); | |
1789 | } | |
1790 | ||
1791 | static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
1792 | { | |
1793 | return vcpu->kvm->arch.iommu_domain && | |
1794 | !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY); | |
1795 | } | |
1796 | ||
313a3dc7 CO |
1797 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
1798 | { | |
f5f48ee1 SY |
1799 | /* Address WBINVD may be executed by guest */ |
1800 | if (need_emulate_wbinvd(vcpu)) { | |
1801 | if (kvm_x86_ops->has_wbinvd_exit()) | |
1802 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
1803 | else if (vcpu->cpu != -1 && vcpu->cpu != cpu) | |
1804 | smp_call_function_single(vcpu->cpu, | |
1805 | wbinvd_ipi, NULL, 1); | |
1806 | } | |
1807 | ||
313a3dc7 | 1808 | kvm_x86_ops->vcpu_load(vcpu, cpu); |
6b7d7e76 ZA |
1809 | if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) { |
1810 | unsigned long khz = cpufreq_quick_get(cpu); | |
1811 | if (!khz) | |
1812 | khz = tsc_khz; | |
1813 | per_cpu(cpu_tsc_khz, cpu) = khz; | |
1814 | } | |
c8076604 | 1815 | kvm_request_guest_time_update(vcpu); |
313a3dc7 CO |
1816 | } |
1817 | ||
1818 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) | |
1819 | { | |
02daab21 | 1820 | kvm_x86_ops->vcpu_put(vcpu); |
1c11e713 | 1821 | kvm_put_guest_fpu(vcpu); |
313a3dc7 CO |
1822 | } |
1823 | ||
07716717 | 1824 | static int is_efer_nx(void) |
313a3dc7 | 1825 | { |
e286e86e | 1826 | unsigned long long efer = 0; |
313a3dc7 | 1827 | |
e286e86e | 1828 | rdmsrl_safe(MSR_EFER, &efer); |
07716717 DK |
1829 | return efer & EFER_NX; |
1830 | } | |
1831 | ||
1832 | static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu) | |
1833 | { | |
1834 | int i; | |
1835 | struct kvm_cpuid_entry2 *e, *entry; | |
1836 | ||
313a3dc7 | 1837 | entry = NULL; |
ad312c7c ZX |
1838 | for (i = 0; i < vcpu->arch.cpuid_nent; ++i) { |
1839 | e = &vcpu->arch.cpuid_entries[i]; | |
313a3dc7 CO |
1840 | if (e->function == 0x80000001) { |
1841 | entry = e; | |
1842 | break; | |
1843 | } | |
1844 | } | |
07716717 | 1845 | if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) { |
313a3dc7 CO |
1846 | entry->edx &= ~(1 << 20); |
1847 | printk(KERN_INFO "kvm: guest NX capability removed\n"); | |
1848 | } | |
1849 | } | |
1850 | ||
07716717 | 1851 | /* when an old userspace process fills a new kernel module */ |
313a3dc7 CO |
1852 | static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu, |
1853 | struct kvm_cpuid *cpuid, | |
1854 | struct kvm_cpuid_entry __user *entries) | |
07716717 DK |
1855 | { |
1856 | int r, i; | |
1857 | struct kvm_cpuid_entry *cpuid_entries; | |
1858 | ||
1859 | r = -E2BIG; | |
1860 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) | |
1861 | goto out; | |
1862 | r = -ENOMEM; | |
1863 | cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent); | |
1864 | if (!cpuid_entries) | |
1865 | goto out; | |
1866 | r = -EFAULT; | |
1867 | if (copy_from_user(cpuid_entries, entries, | |
1868 | cpuid->nent * sizeof(struct kvm_cpuid_entry))) | |
1869 | goto out_free; | |
1870 | for (i = 0; i < cpuid->nent; i++) { | |
ad312c7c ZX |
1871 | vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function; |
1872 | vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax; | |
1873 | vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx; | |
1874 | vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx; | |
1875 | vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx; | |
1876 | vcpu->arch.cpuid_entries[i].index = 0; | |
1877 | vcpu->arch.cpuid_entries[i].flags = 0; | |
1878 | vcpu->arch.cpuid_entries[i].padding[0] = 0; | |
1879 | vcpu->arch.cpuid_entries[i].padding[1] = 0; | |
1880 | vcpu->arch.cpuid_entries[i].padding[2] = 0; | |
1881 | } | |
1882 | vcpu->arch.cpuid_nent = cpuid->nent; | |
07716717 DK |
1883 | cpuid_fix_nx_cap(vcpu); |
1884 | r = 0; | |
fc61b800 | 1885 | kvm_apic_set_version(vcpu); |
0e851880 | 1886 | kvm_x86_ops->cpuid_update(vcpu); |
2acf923e | 1887 | update_cpuid(vcpu); |
07716717 DK |
1888 | |
1889 | out_free: | |
1890 | vfree(cpuid_entries); | |
1891 | out: | |
1892 | return r; | |
1893 | } | |
1894 | ||
1895 | static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu, | |
19355475 AS |
1896 | struct kvm_cpuid2 *cpuid, |
1897 | struct kvm_cpuid_entry2 __user *entries) | |
313a3dc7 CO |
1898 | { |
1899 | int r; | |
1900 | ||
1901 | r = -E2BIG; | |
1902 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) | |
1903 | goto out; | |
1904 | r = -EFAULT; | |
ad312c7c | 1905 | if (copy_from_user(&vcpu->arch.cpuid_entries, entries, |
07716717 | 1906 | cpuid->nent * sizeof(struct kvm_cpuid_entry2))) |
313a3dc7 | 1907 | goto out; |
ad312c7c | 1908 | vcpu->arch.cpuid_nent = cpuid->nent; |
fc61b800 | 1909 | kvm_apic_set_version(vcpu); |
0e851880 | 1910 | kvm_x86_ops->cpuid_update(vcpu); |
2acf923e | 1911 | update_cpuid(vcpu); |
313a3dc7 CO |
1912 | return 0; |
1913 | ||
1914 | out: | |
1915 | return r; | |
1916 | } | |
1917 | ||
07716717 | 1918 | static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu, |
19355475 AS |
1919 | struct kvm_cpuid2 *cpuid, |
1920 | struct kvm_cpuid_entry2 __user *entries) | |
07716717 DK |
1921 | { |
1922 | int r; | |
1923 | ||
1924 | r = -E2BIG; | |
ad312c7c | 1925 | if (cpuid->nent < vcpu->arch.cpuid_nent) |
07716717 DK |
1926 | goto out; |
1927 | r = -EFAULT; | |
ad312c7c | 1928 | if (copy_to_user(entries, &vcpu->arch.cpuid_entries, |
19355475 | 1929 | vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2))) |
07716717 DK |
1930 | goto out; |
1931 | return 0; | |
1932 | ||
1933 | out: | |
ad312c7c | 1934 | cpuid->nent = vcpu->arch.cpuid_nent; |
07716717 DK |
1935 | return r; |
1936 | } | |
1937 | ||
07716717 | 1938 | static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function, |
19355475 | 1939 | u32 index) |
07716717 DK |
1940 | { |
1941 | entry->function = function; | |
1942 | entry->index = index; | |
1943 | cpuid_count(entry->function, entry->index, | |
19355475 | 1944 | &entry->eax, &entry->ebx, &entry->ecx, &entry->edx); |
07716717 DK |
1945 | entry->flags = 0; |
1946 | } | |
1947 | ||
7faa4ee1 AK |
1948 | #define F(x) bit(X86_FEATURE_##x) |
1949 | ||
07716717 DK |
1950 | static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, |
1951 | u32 index, int *nent, int maxnent) | |
1952 | { | |
7faa4ee1 | 1953 | unsigned f_nx = is_efer_nx() ? F(NX) : 0; |
07716717 | 1954 | #ifdef CONFIG_X86_64 |
17cc3935 SY |
1955 | unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL) |
1956 | ? F(GBPAGES) : 0; | |
7faa4ee1 AK |
1957 | unsigned f_lm = F(LM); |
1958 | #else | |
17cc3935 | 1959 | unsigned f_gbpages = 0; |
7faa4ee1 | 1960 | unsigned f_lm = 0; |
07716717 | 1961 | #endif |
4e47c7a6 | 1962 | unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0; |
7faa4ee1 AK |
1963 | |
1964 | /* cpuid 1.edx */ | |
1965 | const u32 kvm_supported_word0_x86_features = | |
1966 | F(FPU) | F(VME) | F(DE) | F(PSE) | | |
1967 | F(TSC) | F(MSR) | F(PAE) | F(MCE) | | |
1968 | F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) | | |
1969 | F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | | |
1970 | F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) | | |
1971 | 0 /* Reserved, DS, ACPI */ | F(MMX) | | |
1972 | F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) | | |
1973 | 0 /* HTT, TM, Reserved, PBE */; | |
1974 | /* cpuid 0x80000001.edx */ | |
1975 | const u32 kvm_supported_word1_x86_features = | |
1976 | F(FPU) | F(VME) | F(DE) | F(PSE) | | |
1977 | F(TSC) | F(MSR) | F(PAE) | F(MCE) | | |
1978 | F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) | | |
1979 | F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | | |
1980 | F(PAT) | F(PSE36) | 0 /* Reserved */ | | |
1981 | f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) | | |
4e47c7a6 | 1982 | F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp | |
7faa4ee1 AK |
1983 | 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW); |
1984 | /* cpuid 1.ecx */ | |
1985 | const u32 kvm_supported_word4_x86_features = | |
6c3f6041 | 1986 | F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ | |
d149c731 AK |
1987 | 0 /* DS-CPL, VMX, SMX, EST */ | |
1988 | 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ | | |
1989 | 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ | | |
1990 | 0 /* Reserved, DCA */ | F(XMM4_1) | | |
0105d1a5 | 1991 | F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) | |
6c3f6041 | 1992 | 0 /* Reserved, AES */ | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX); |
7faa4ee1 | 1993 | /* cpuid 0x80000001.ecx */ |
07716717 | 1994 | const u32 kvm_supported_word6_x86_features = |
7faa4ee1 AK |
1995 | F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ | |
1996 | F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) | | |
1997 | F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) | | |
1998 | 0 /* SKINIT */ | 0 /* WDT */; | |
07716717 | 1999 | |
19355475 | 2000 | /* all calls to cpuid_count() should be made on the same cpu */ |
07716717 DK |
2001 | get_cpu(); |
2002 | do_cpuid_1_ent(entry, function, index); | |
2003 | ++*nent; | |
2004 | ||
2005 | switch (function) { | |
2006 | case 0: | |
2acf923e | 2007 | entry->eax = min(entry->eax, (u32)0xd); |
07716717 DK |
2008 | break; |
2009 | case 1: | |
2010 | entry->edx &= kvm_supported_word0_x86_features; | |
7faa4ee1 | 2011 | entry->ecx &= kvm_supported_word4_x86_features; |
0d1de2d9 GN |
2012 | /* we support x2apic emulation even if host does not support |
2013 | * it since we emulate x2apic in software */ | |
2014 | entry->ecx |= F(X2APIC); | |
07716717 DK |
2015 | break; |
2016 | /* function 2 entries are STATEFUL. That is, repeated cpuid commands | |
2017 | * may return different values. This forces us to get_cpu() before | |
2018 | * issuing the first command, and also to emulate this annoying behavior | |
2019 | * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */ | |
2020 | case 2: { | |
2021 | int t, times = entry->eax & 0xff; | |
2022 | ||
2023 | entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC; | |
0fdf8e59 | 2024 | entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT; |
07716717 DK |
2025 | for (t = 1; t < times && *nent < maxnent; ++t) { |
2026 | do_cpuid_1_ent(&entry[t], function, 0); | |
2027 | entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC; | |
2028 | ++*nent; | |
2029 | } | |
2030 | break; | |
2031 | } | |
2032 | /* function 4 and 0xb have additional index. */ | |
2033 | case 4: { | |
14af3f3c | 2034 | int i, cache_type; |
07716717 DK |
2035 | |
2036 | entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
2037 | /* read more entries until cache_type is zero */ | |
14af3f3c HH |
2038 | for (i = 1; *nent < maxnent; ++i) { |
2039 | cache_type = entry[i - 1].eax & 0x1f; | |
07716717 DK |
2040 | if (!cache_type) |
2041 | break; | |
14af3f3c HH |
2042 | do_cpuid_1_ent(&entry[i], function, i); |
2043 | entry[i].flags |= | |
07716717 DK |
2044 | KVM_CPUID_FLAG_SIGNIFCANT_INDEX; |
2045 | ++*nent; | |
2046 | } | |
2047 | break; | |
2048 | } | |
2049 | case 0xb: { | |
14af3f3c | 2050 | int i, level_type; |
07716717 DK |
2051 | |
2052 | entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
2053 | /* read more entries until level_type is zero */ | |
14af3f3c | 2054 | for (i = 1; *nent < maxnent; ++i) { |
0853d2c1 | 2055 | level_type = entry[i - 1].ecx & 0xff00; |
07716717 DK |
2056 | if (!level_type) |
2057 | break; | |
14af3f3c HH |
2058 | do_cpuid_1_ent(&entry[i], function, i); |
2059 | entry[i].flags |= | |
07716717 DK |
2060 | KVM_CPUID_FLAG_SIGNIFCANT_INDEX; |
2061 | ++*nent; | |
2062 | } | |
2063 | break; | |
2064 | } | |
2acf923e DC |
2065 | case 0xd: { |
2066 | int i; | |
2067 | ||
2068 | entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
2069 | for (i = 1; *nent < maxnent; ++i) { | |
2070 | if (entry[i - 1].eax == 0 && i != 2) | |
2071 | break; | |
2072 | do_cpuid_1_ent(&entry[i], function, i); | |
2073 | entry[i].flags |= | |
2074 | KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
2075 | ++*nent; | |
2076 | } | |
2077 | break; | |
2078 | } | |
84478c82 GC |
2079 | case KVM_CPUID_SIGNATURE: { |
2080 | char signature[12] = "KVMKVMKVM\0\0"; | |
2081 | u32 *sigptr = (u32 *)signature; | |
2082 | entry->eax = 0; | |
2083 | entry->ebx = sigptr[0]; | |
2084 | entry->ecx = sigptr[1]; | |
2085 | entry->edx = sigptr[2]; | |
2086 | break; | |
2087 | } | |
2088 | case KVM_CPUID_FEATURES: | |
2089 | entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) | | |
2090 | (1 << KVM_FEATURE_NOP_IO_DELAY) | | |
371bcf64 GC |
2091 | (1 << KVM_FEATURE_CLOCKSOURCE2) | |
2092 | (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT); | |
84478c82 GC |
2093 | entry->ebx = 0; |
2094 | entry->ecx = 0; | |
2095 | entry->edx = 0; | |
2096 | break; | |
07716717 DK |
2097 | case 0x80000000: |
2098 | entry->eax = min(entry->eax, 0x8000001a); | |
2099 | break; | |
2100 | case 0x80000001: | |
2101 | entry->edx &= kvm_supported_word1_x86_features; | |
2102 | entry->ecx &= kvm_supported_word6_x86_features; | |
2103 | break; | |
2104 | } | |
d4330ef2 JR |
2105 | |
2106 | kvm_x86_ops->set_supported_cpuid(function, entry); | |
2107 | ||
07716717 DK |
2108 | put_cpu(); |
2109 | } | |
2110 | ||
7faa4ee1 AK |
2111 | #undef F |
2112 | ||
674eea0f | 2113 | static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid, |
19355475 | 2114 | struct kvm_cpuid_entry2 __user *entries) |
07716717 DK |
2115 | { |
2116 | struct kvm_cpuid_entry2 *cpuid_entries; | |
2117 | int limit, nent = 0, r = -E2BIG; | |
2118 | u32 func; | |
2119 | ||
2120 | if (cpuid->nent < 1) | |
2121 | goto out; | |
6a544355 AK |
2122 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) |
2123 | cpuid->nent = KVM_MAX_CPUID_ENTRIES; | |
07716717 DK |
2124 | r = -ENOMEM; |
2125 | cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent); | |
2126 | if (!cpuid_entries) | |
2127 | goto out; | |
2128 | ||
2129 | do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent); | |
2130 | limit = cpuid_entries[0].eax; | |
2131 | for (func = 1; func <= limit && nent < cpuid->nent; ++func) | |
2132 | do_cpuid_ent(&cpuid_entries[nent], func, 0, | |
19355475 | 2133 | &nent, cpuid->nent); |
07716717 DK |
2134 | r = -E2BIG; |
2135 | if (nent >= cpuid->nent) | |
2136 | goto out_free; | |
2137 | ||
2138 | do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent); | |
2139 | limit = cpuid_entries[nent - 1].eax; | |
2140 | for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func) | |
2141 | do_cpuid_ent(&cpuid_entries[nent], func, 0, | |
19355475 | 2142 | &nent, cpuid->nent); |
84478c82 GC |
2143 | |
2144 | ||
2145 | ||
2146 | r = -E2BIG; | |
2147 | if (nent >= cpuid->nent) | |
2148 | goto out_free; | |
2149 | ||
2150 | do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent, | |
2151 | cpuid->nent); | |
2152 | ||
2153 | r = -E2BIG; | |
2154 | if (nent >= cpuid->nent) | |
2155 | goto out_free; | |
2156 | ||
2157 | do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent, | |
2158 | cpuid->nent); | |
2159 | ||
cb007648 MM |
2160 | r = -E2BIG; |
2161 | if (nent >= cpuid->nent) | |
2162 | goto out_free; | |
2163 | ||
07716717 DK |
2164 | r = -EFAULT; |
2165 | if (copy_to_user(entries, cpuid_entries, | |
19355475 | 2166 | nent * sizeof(struct kvm_cpuid_entry2))) |
07716717 DK |
2167 | goto out_free; |
2168 | cpuid->nent = nent; | |
2169 | r = 0; | |
2170 | ||
2171 | out_free: | |
2172 | vfree(cpuid_entries); | |
2173 | out: | |
2174 | return r; | |
2175 | } | |
2176 | ||
313a3dc7 CO |
2177 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
2178 | struct kvm_lapic_state *s) | |
2179 | { | |
ad312c7c | 2180 | memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s); |
313a3dc7 CO |
2181 | |
2182 | return 0; | |
2183 | } | |
2184 | ||
2185 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
2186 | struct kvm_lapic_state *s) | |
2187 | { | |
ad312c7c | 2188 | memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s); |
313a3dc7 | 2189 | kvm_apic_post_state_restore(vcpu); |
cb142eb7 | 2190 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
2191 | |
2192 | return 0; | |
2193 | } | |
2194 | ||
f77bc6a4 ZX |
2195 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
2196 | struct kvm_interrupt *irq) | |
2197 | { | |
2198 | if (irq->irq < 0 || irq->irq >= 256) | |
2199 | return -EINVAL; | |
2200 | if (irqchip_in_kernel(vcpu->kvm)) | |
2201 | return -ENXIO; | |
f77bc6a4 | 2202 | |
66fd3f7f | 2203 | kvm_queue_interrupt(vcpu, irq->irq, false); |
f77bc6a4 | 2204 | |
f77bc6a4 ZX |
2205 | return 0; |
2206 | } | |
2207 | ||
c4abb7c9 JK |
2208 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
2209 | { | |
c4abb7c9 | 2210 | kvm_inject_nmi(vcpu); |
c4abb7c9 JK |
2211 | |
2212 | return 0; | |
2213 | } | |
2214 | ||
b209749f AK |
2215 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
2216 | struct kvm_tpr_access_ctl *tac) | |
2217 | { | |
2218 | if (tac->flags) | |
2219 | return -EINVAL; | |
2220 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
2221 | return 0; | |
2222 | } | |
2223 | ||
890ca9ae HY |
2224 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
2225 | u64 mcg_cap) | |
2226 | { | |
2227 | int r; | |
2228 | unsigned bank_num = mcg_cap & 0xff, bank; | |
2229 | ||
2230 | r = -EINVAL; | |
a9e38c3e | 2231 | if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) |
890ca9ae HY |
2232 | goto out; |
2233 | if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000)) | |
2234 | goto out; | |
2235 | r = 0; | |
2236 | vcpu->arch.mcg_cap = mcg_cap; | |
2237 | /* Init IA32_MCG_CTL to all 1s */ | |
2238 | if (mcg_cap & MCG_CTL_P) | |
2239 | vcpu->arch.mcg_ctl = ~(u64)0; | |
2240 | /* Init IA32_MCi_CTL to all 1s */ | |
2241 | for (bank = 0; bank < bank_num; bank++) | |
2242 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
2243 | out: | |
2244 | return r; | |
2245 | } | |
2246 | ||
2247 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
2248 | struct kvm_x86_mce *mce) | |
2249 | { | |
2250 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
2251 | unsigned bank_num = mcg_cap & 0xff; | |
2252 | u64 *banks = vcpu->arch.mce_banks; | |
2253 | ||
2254 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
2255 | return -EINVAL; | |
2256 | /* | |
2257 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
2258 | * reporting is disabled | |
2259 | */ | |
2260 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
2261 | vcpu->arch.mcg_ctl != ~(u64)0) | |
2262 | return 0; | |
2263 | banks += 4 * mce->bank; | |
2264 | /* | |
2265 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
2266 | * reporting is disabled for the bank | |
2267 | */ | |
2268 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
2269 | return 0; | |
2270 | if (mce->status & MCI_STATUS_UC) { | |
2271 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
fc78f519 | 2272 | !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { |
890ca9ae HY |
2273 | printk(KERN_DEBUG "kvm: set_mce: " |
2274 | "injects mce exception while " | |
2275 | "previous one is in progress!\n"); | |
a8eeb04a | 2276 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
890ca9ae HY |
2277 | return 0; |
2278 | } | |
2279 | if (banks[1] & MCI_STATUS_VAL) | |
2280 | mce->status |= MCI_STATUS_OVER; | |
2281 | banks[2] = mce->addr; | |
2282 | banks[3] = mce->misc; | |
2283 | vcpu->arch.mcg_status = mce->mcg_status; | |
2284 | banks[1] = mce->status; | |
2285 | kvm_queue_exception(vcpu, MC_VECTOR); | |
2286 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
2287 | || !(banks[1] & MCI_STATUS_UC)) { | |
2288 | if (banks[1] & MCI_STATUS_VAL) | |
2289 | mce->status |= MCI_STATUS_OVER; | |
2290 | banks[2] = mce->addr; | |
2291 | banks[3] = mce->misc; | |
2292 | banks[1] = mce->status; | |
2293 | } else | |
2294 | banks[1] |= MCI_STATUS_OVER; | |
2295 | return 0; | |
2296 | } | |
2297 | ||
3cfc3092 JK |
2298 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
2299 | struct kvm_vcpu_events *events) | |
2300 | { | |
03b82a30 JK |
2301 | events->exception.injected = |
2302 | vcpu->arch.exception.pending && | |
2303 | !kvm_exception_is_soft(vcpu->arch.exception.nr); | |
3cfc3092 JK |
2304 | events->exception.nr = vcpu->arch.exception.nr; |
2305 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
2306 | events->exception.error_code = vcpu->arch.exception.error_code; | |
2307 | ||
03b82a30 JK |
2308 | events->interrupt.injected = |
2309 | vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; | |
3cfc3092 | 2310 | events->interrupt.nr = vcpu->arch.interrupt.nr; |
03b82a30 | 2311 | events->interrupt.soft = 0; |
48005f64 JK |
2312 | events->interrupt.shadow = |
2313 | kvm_x86_ops->get_interrupt_shadow(vcpu, | |
2314 | KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI); | |
3cfc3092 JK |
2315 | |
2316 | events->nmi.injected = vcpu->arch.nmi_injected; | |
2317 | events->nmi.pending = vcpu->arch.nmi_pending; | |
2318 | events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); | |
2319 | ||
2320 | events->sipi_vector = vcpu->arch.sipi_vector; | |
2321 | ||
dab4b911 | 2322 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 JK |
2323 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
2324 | | KVM_VCPUEVENT_VALID_SHADOW); | |
3cfc3092 JK |
2325 | } |
2326 | ||
2327 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, | |
2328 | struct kvm_vcpu_events *events) | |
2329 | { | |
dab4b911 | 2330 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 JK |
2331 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
2332 | | KVM_VCPUEVENT_VALID_SHADOW)) | |
3cfc3092 JK |
2333 | return -EINVAL; |
2334 | ||
3cfc3092 JK |
2335 | vcpu->arch.exception.pending = events->exception.injected; |
2336 | vcpu->arch.exception.nr = events->exception.nr; | |
2337 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
2338 | vcpu->arch.exception.error_code = events->exception.error_code; | |
2339 | ||
2340 | vcpu->arch.interrupt.pending = events->interrupt.injected; | |
2341 | vcpu->arch.interrupt.nr = events->interrupt.nr; | |
2342 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
2343 | if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm)) | |
2344 | kvm_pic_clear_isr_ack(vcpu->kvm); | |
48005f64 JK |
2345 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) |
2346 | kvm_x86_ops->set_interrupt_shadow(vcpu, | |
2347 | events->interrupt.shadow); | |
3cfc3092 JK |
2348 | |
2349 | vcpu->arch.nmi_injected = events->nmi.injected; | |
dab4b911 JK |
2350 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) |
2351 | vcpu->arch.nmi_pending = events->nmi.pending; | |
3cfc3092 JK |
2352 | kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); |
2353 | ||
dab4b911 JK |
2354 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR) |
2355 | vcpu->arch.sipi_vector = events->sipi_vector; | |
3cfc3092 | 2356 | |
3cfc3092 JK |
2357 | return 0; |
2358 | } | |
2359 | ||
a1efbe77 JK |
2360 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, |
2361 | struct kvm_debugregs *dbgregs) | |
2362 | { | |
a1efbe77 JK |
2363 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); |
2364 | dbgregs->dr6 = vcpu->arch.dr6; | |
2365 | dbgregs->dr7 = vcpu->arch.dr7; | |
2366 | dbgregs->flags = 0; | |
a1efbe77 JK |
2367 | } |
2368 | ||
2369 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
2370 | struct kvm_debugregs *dbgregs) | |
2371 | { | |
2372 | if (dbgregs->flags) | |
2373 | return -EINVAL; | |
2374 | ||
a1efbe77 JK |
2375 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); |
2376 | vcpu->arch.dr6 = dbgregs->dr6; | |
2377 | vcpu->arch.dr7 = dbgregs->dr7; | |
2378 | ||
a1efbe77 JK |
2379 | return 0; |
2380 | } | |
2381 | ||
2d5b5a66 SY |
2382 | static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, |
2383 | struct kvm_xsave *guest_xsave) | |
2384 | { | |
2385 | if (cpu_has_xsave) | |
2386 | memcpy(guest_xsave->region, | |
2387 | &vcpu->arch.guest_fpu.state->xsave, | |
2388 | sizeof(struct xsave_struct)); | |
2389 | else { | |
2390 | memcpy(guest_xsave->region, | |
2391 | &vcpu->arch.guest_fpu.state->fxsave, | |
2392 | sizeof(struct i387_fxsave_struct)); | |
2393 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = | |
2394 | XSTATE_FPSSE; | |
2395 | } | |
2396 | } | |
2397 | ||
2398 | static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, | |
2399 | struct kvm_xsave *guest_xsave) | |
2400 | { | |
2401 | u64 xstate_bv = | |
2402 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; | |
2403 | ||
2404 | if (cpu_has_xsave) | |
2405 | memcpy(&vcpu->arch.guest_fpu.state->xsave, | |
2406 | guest_xsave->region, sizeof(struct xsave_struct)); | |
2407 | else { | |
2408 | if (xstate_bv & ~XSTATE_FPSSE) | |
2409 | return -EINVAL; | |
2410 | memcpy(&vcpu->arch.guest_fpu.state->fxsave, | |
2411 | guest_xsave->region, sizeof(struct i387_fxsave_struct)); | |
2412 | } | |
2413 | return 0; | |
2414 | } | |
2415 | ||
2416 | static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, | |
2417 | struct kvm_xcrs *guest_xcrs) | |
2418 | { | |
2419 | if (!cpu_has_xsave) { | |
2420 | guest_xcrs->nr_xcrs = 0; | |
2421 | return; | |
2422 | } | |
2423 | ||
2424 | guest_xcrs->nr_xcrs = 1; | |
2425 | guest_xcrs->flags = 0; | |
2426 | guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; | |
2427 | guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; | |
2428 | } | |
2429 | ||
2430 | static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, | |
2431 | struct kvm_xcrs *guest_xcrs) | |
2432 | { | |
2433 | int i, r = 0; | |
2434 | ||
2435 | if (!cpu_has_xsave) | |
2436 | return -EINVAL; | |
2437 | ||
2438 | if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) | |
2439 | return -EINVAL; | |
2440 | ||
2441 | for (i = 0; i < guest_xcrs->nr_xcrs; i++) | |
2442 | /* Only support XCR0 currently */ | |
2443 | if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) { | |
2444 | r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, | |
2445 | guest_xcrs->xcrs[0].value); | |
2446 | break; | |
2447 | } | |
2448 | if (r) | |
2449 | r = -EINVAL; | |
2450 | return r; | |
2451 | } | |
2452 | ||
313a3dc7 CO |
2453 | long kvm_arch_vcpu_ioctl(struct file *filp, |
2454 | unsigned int ioctl, unsigned long arg) | |
2455 | { | |
2456 | struct kvm_vcpu *vcpu = filp->private_data; | |
2457 | void __user *argp = (void __user *)arg; | |
2458 | int r; | |
d1ac91d8 AK |
2459 | union { |
2460 | struct kvm_lapic_state *lapic; | |
2461 | struct kvm_xsave *xsave; | |
2462 | struct kvm_xcrs *xcrs; | |
2463 | void *buffer; | |
2464 | } u; | |
2465 | ||
2466 | u.buffer = NULL; | |
313a3dc7 CO |
2467 | switch (ioctl) { |
2468 | case KVM_GET_LAPIC: { | |
2204ae3c MT |
2469 | r = -EINVAL; |
2470 | if (!vcpu->arch.apic) | |
2471 | goto out; | |
d1ac91d8 | 2472 | u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); |
313a3dc7 | 2473 | |
b772ff36 | 2474 | r = -ENOMEM; |
d1ac91d8 | 2475 | if (!u.lapic) |
b772ff36 | 2476 | goto out; |
d1ac91d8 | 2477 | r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); |
313a3dc7 CO |
2478 | if (r) |
2479 | goto out; | |
2480 | r = -EFAULT; | |
d1ac91d8 | 2481 | if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
2482 | goto out; |
2483 | r = 0; | |
2484 | break; | |
2485 | } | |
2486 | case KVM_SET_LAPIC: { | |
2204ae3c MT |
2487 | r = -EINVAL; |
2488 | if (!vcpu->arch.apic) | |
2489 | goto out; | |
d1ac91d8 | 2490 | u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); |
b772ff36 | 2491 | r = -ENOMEM; |
d1ac91d8 | 2492 | if (!u.lapic) |
b772ff36 | 2493 | goto out; |
313a3dc7 | 2494 | r = -EFAULT; |
d1ac91d8 | 2495 | if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state))) |
313a3dc7 | 2496 | goto out; |
d1ac91d8 | 2497 | r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); |
313a3dc7 CO |
2498 | if (r) |
2499 | goto out; | |
2500 | r = 0; | |
2501 | break; | |
2502 | } | |
f77bc6a4 ZX |
2503 | case KVM_INTERRUPT: { |
2504 | struct kvm_interrupt irq; | |
2505 | ||
2506 | r = -EFAULT; | |
2507 | if (copy_from_user(&irq, argp, sizeof irq)) | |
2508 | goto out; | |
2509 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
2510 | if (r) | |
2511 | goto out; | |
2512 | r = 0; | |
2513 | break; | |
2514 | } | |
c4abb7c9 JK |
2515 | case KVM_NMI: { |
2516 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
2517 | if (r) | |
2518 | goto out; | |
2519 | r = 0; | |
2520 | break; | |
2521 | } | |
313a3dc7 CO |
2522 | case KVM_SET_CPUID: { |
2523 | struct kvm_cpuid __user *cpuid_arg = argp; | |
2524 | struct kvm_cpuid cpuid; | |
2525 | ||
2526 | r = -EFAULT; | |
2527 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2528 | goto out; | |
2529 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
2530 | if (r) | |
2531 | goto out; | |
2532 | break; | |
2533 | } | |
07716717 DK |
2534 | case KVM_SET_CPUID2: { |
2535 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
2536 | struct kvm_cpuid2 cpuid; | |
2537 | ||
2538 | r = -EFAULT; | |
2539 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2540 | goto out; | |
2541 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 2542 | cpuid_arg->entries); |
07716717 DK |
2543 | if (r) |
2544 | goto out; | |
2545 | break; | |
2546 | } | |
2547 | case KVM_GET_CPUID2: { | |
2548 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
2549 | struct kvm_cpuid2 cpuid; | |
2550 | ||
2551 | r = -EFAULT; | |
2552 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2553 | goto out; | |
2554 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 2555 | cpuid_arg->entries); |
07716717 DK |
2556 | if (r) |
2557 | goto out; | |
2558 | r = -EFAULT; | |
2559 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
2560 | goto out; | |
2561 | r = 0; | |
2562 | break; | |
2563 | } | |
313a3dc7 CO |
2564 | case KVM_GET_MSRS: |
2565 | r = msr_io(vcpu, argp, kvm_get_msr, 1); | |
2566 | break; | |
2567 | case KVM_SET_MSRS: | |
2568 | r = msr_io(vcpu, argp, do_set_msr, 0); | |
2569 | break; | |
b209749f AK |
2570 | case KVM_TPR_ACCESS_REPORTING: { |
2571 | struct kvm_tpr_access_ctl tac; | |
2572 | ||
2573 | r = -EFAULT; | |
2574 | if (copy_from_user(&tac, argp, sizeof tac)) | |
2575 | goto out; | |
2576 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
2577 | if (r) | |
2578 | goto out; | |
2579 | r = -EFAULT; | |
2580 | if (copy_to_user(argp, &tac, sizeof tac)) | |
2581 | goto out; | |
2582 | r = 0; | |
2583 | break; | |
2584 | }; | |
b93463aa AK |
2585 | case KVM_SET_VAPIC_ADDR: { |
2586 | struct kvm_vapic_addr va; | |
2587 | ||
2588 | r = -EINVAL; | |
2589 | if (!irqchip_in_kernel(vcpu->kvm)) | |
2590 | goto out; | |
2591 | r = -EFAULT; | |
2592 | if (copy_from_user(&va, argp, sizeof va)) | |
2593 | goto out; | |
2594 | r = 0; | |
2595 | kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); | |
2596 | break; | |
2597 | } | |
890ca9ae HY |
2598 | case KVM_X86_SETUP_MCE: { |
2599 | u64 mcg_cap; | |
2600 | ||
2601 | r = -EFAULT; | |
2602 | if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) | |
2603 | goto out; | |
2604 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
2605 | break; | |
2606 | } | |
2607 | case KVM_X86_SET_MCE: { | |
2608 | struct kvm_x86_mce mce; | |
2609 | ||
2610 | r = -EFAULT; | |
2611 | if (copy_from_user(&mce, argp, sizeof mce)) | |
2612 | goto out; | |
2613 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
2614 | break; | |
2615 | } | |
3cfc3092 JK |
2616 | case KVM_GET_VCPU_EVENTS: { |
2617 | struct kvm_vcpu_events events; | |
2618 | ||
2619 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
2620 | ||
2621 | r = -EFAULT; | |
2622 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
2623 | break; | |
2624 | r = 0; | |
2625 | break; | |
2626 | } | |
2627 | case KVM_SET_VCPU_EVENTS: { | |
2628 | struct kvm_vcpu_events events; | |
2629 | ||
2630 | r = -EFAULT; | |
2631 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
2632 | break; | |
2633 | ||
2634 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
2635 | break; | |
2636 | } | |
a1efbe77 JK |
2637 | case KVM_GET_DEBUGREGS: { |
2638 | struct kvm_debugregs dbgregs; | |
2639 | ||
2640 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
2641 | ||
2642 | r = -EFAULT; | |
2643 | if (copy_to_user(argp, &dbgregs, | |
2644 | sizeof(struct kvm_debugregs))) | |
2645 | break; | |
2646 | r = 0; | |
2647 | break; | |
2648 | } | |
2649 | case KVM_SET_DEBUGREGS: { | |
2650 | struct kvm_debugregs dbgregs; | |
2651 | ||
2652 | r = -EFAULT; | |
2653 | if (copy_from_user(&dbgregs, argp, | |
2654 | sizeof(struct kvm_debugregs))) | |
2655 | break; | |
2656 | ||
2657 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
2658 | break; | |
2659 | } | |
2d5b5a66 | 2660 | case KVM_GET_XSAVE: { |
d1ac91d8 | 2661 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); |
2d5b5a66 | 2662 | r = -ENOMEM; |
d1ac91d8 | 2663 | if (!u.xsave) |
2d5b5a66 SY |
2664 | break; |
2665 | ||
d1ac91d8 | 2666 | kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
2667 | |
2668 | r = -EFAULT; | |
d1ac91d8 | 2669 | if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
2670 | break; |
2671 | r = 0; | |
2672 | break; | |
2673 | } | |
2674 | case KVM_SET_XSAVE: { | |
d1ac91d8 | 2675 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); |
2d5b5a66 | 2676 | r = -ENOMEM; |
d1ac91d8 | 2677 | if (!u.xsave) |
2d5b5a66 SY |
2678 | break; |
2679 | ||
2680 | r = -EFAULT; | |
d1ac91d8 | 2681 | if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
2682 | break; |
2683 | ||
d1ac91d8 | 2684 | r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
2685 | break; |
2686 | } | |
2687 | case KVM_GET_XCRS: { | |
d1ac91d8 | 2688 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); |
2d5b5a66 | 2689 | r = -ENOMEM; |
d1ac91d8 | 2690 | if (!u.xcrs) |
2d5b5a66 SY |
2691 | break; |
2692 | ||
d1ac91d8 | 2693 | kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
2694 | |
2695 | r = -EFAULT; | |
d1ac91d8 | 2696 | if (copy_to_user(argp, u.xcrs, |
2d5b5a66 SY |
2697 | sizeof(struct kvm_xcrs))) |
2698 | break; | |
2699 | r = 0; | |
2700 | break; | |
2701 | } | |
2702 | case KVM_SET_XCRS: { | |
d1ac91d8 | 2703 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); |
2d5b5a66 | 2704 | r = -ENOMEM; |
d1ac91d8 | 2705 | if (!u.xcrs) |
2d5b5a66 SY |
2706 | break; |
2707 | ||
2708 | r = -EFAULT; | |
d1ac91d8 | 2709 | if (copy_from_user(u.xcrs, argp, |
2d5b5a66 SY |
2710 | sizeof(struct kvm_xcrs))) |
2711 | break; | |
2712 | ||
d1ac91d8 | 2713 | r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
2714 | break; |
2715 | } | |
313a3dc7 CO |
2716 | default: |
2717 | r = -EINVAL; | |
2718 | } | |
2719 | out: | |
d1ac91d8 | 2720 | kfree(u.buffer); |
313a3dc7 CO |
2721 | return r; |
2722 | } | |
2723 | ||
1fe779f8 CO |
2724 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
2725 | { | |
2726 | int ret; | |
2727 | ||
2728 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
2729 | return -1; | |
2730 | ret = kvm_x86_ops->set_tss_addr(kvm, addr); | |
2731 | return ret; | |
2732 | } | |
2733 | ||
b927a3ce SY |
2734 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
2735 | u64 ident_addr) | |
2736 | { | |
2737 | kvm->arch.ept_identity_map_addr = ident_addr; | |
2738 | return 0; | |
2739 | } | |
2740 | ||
1fe779f8 CO |
2741 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
2742 | u32 kvm_nr_mmu_pages) | |
2743 | { | |
2744 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
2745 | return -EINVAL; | |
2746 | ||
79fac95e | 2747 | mutex_lock(&kvm->slots_lock); |
7c8a83b7 | 2748 | spin_lock(&kvm->mmu_lock); |
1fe779f8 CO |
2749 | |
2750 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 2751 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 2752 | |
7c8a83b7 | 2753 | spin_unlock(&kvm->mmu_lock); |
79fac95e | 2754 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
2755 | return 0; |
2756 | } | |
2757 | ||
2758 | static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) | |
2759 | { | |
f05e70ac | 2760 | return kvm->arch.n_alloc_mmu_pages; |
1fe779f8 CO |
2761 | } |
2762 | ||
1fe779f8 CO |
2763 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) |
2764 | { | |
2765 | int r; | |
2766 | ||
2767 | r = 0; | |
2768 | switch (chip->chip_id) { | |
2769 | case KVM_IRQCHIP_PIC_MASTER: | |
2770 | memcpy(&chip->chip.pic, | |
2771 | &pic_irqchip(kvm)->pics[0], | |
2772 | sizeof(struct kvm_pic_state)); | |
2773 | break; | |
2774 | case KVM_IRQCHIP_PIC_SLAVE: | |
2775 | memcpy(&chip->chip.pic, | |
2776 | &pic_irqchip(kvm)->pics[1], | |
2777 | sizeof(struct kvm_pic_state)); | |
2778 | break; | |
2779 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 2780 | r = kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
2781 | break; |
2782 | default: | |
2783 | r = -EINVAL; | |
2784 | break; | |
2785 | } | |
2786 | return r; | |
2787 | } | |
2788 | ||
2789 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
2790 | { | |
2791 | int r; | |
2792 | ||
2793 | r = 0; | |
2794 | switch (chip->chip_id) { | |
2795 | case KVM_IRQCHIP_PIC_MASTER: | |
fa8273e9 | 2796 | raw_spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
2797 | memcpy(&pic_irqchip(kvm)->pics[0], |
2798 | &chip->chip.pic, | |
2799 | sizeof(struct kvm_pic_state)); | |
fa8273e9 | 2800 | raw_spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
2801 | break; |
2802 | case KVM_IRQCHIP_PIC_SLAVE: | |
fa8273e9 | 2803 | raw_spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
2804 | memcpy(&pic_irqchip(kvm)->pics[1], |
2805 | &chip->chip.pic, | |
2806 | sizeof(struct kvm_pic_state)); | |
fa8273e9 | 2807 | raw_spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
2808 | break; |
2809 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 2810 | r = kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
2811 | break; |
2812 | default: | |
2813 | r = -EINVAL; | |
2814 | break; | |
2815 | } | |
2816 | kvm_pic_update_irq(pic_irqchip(kvm)); | |
2817 | return r; | |
2818 | } | |
2819 | ||
e0f63cb9 SY |
2820 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
2821 | { | |
2822 | int r = 0; | |
2823 | ||
894a9c55 | 2824 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 | 2825 | memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state)); |
894a9c55 | 2826 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 SY |
2827 | return r; |
2828 | } | |
2829 | ||
2830 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
2831 | { | |
2832 | int r = 0; | |
2833 | ||
894a9c55 | 2834 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 | 2835 | memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state)); |
e9f42757 BK |
2836 | kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0); |
2837 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
2838 | return r; | |
2839 | } | |
2840 | ||
2841 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
2842 | { | |
2843 | int r = 0; | |
2844 | ||
2845 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
2846 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
2847 | sizeof(ps->channels)); | |
2848 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
2849 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
2850 | return r; | |
2851 | } | |
2852 | ||
2853 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
2854 | { | |
2855 | int r = 0, start = 0; | |
2856 | u32 prev_legacy, cur_legacy; | |
2857 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
2858 | prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
2859 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
2860 | if (!prev_legacy && cur_legacy) | |
2861 | start = 1; | |
2862 | memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels, | |
2863 | sizeof(kvm->arch.vpit->pit_state.channels)); | |
2864 | kvm->arch.vpit->pit_state.flags = ps->flags; | |
2865 | kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start); | |
894a9c55 | 2866 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 SY |
2867 | return r; |
2868 | } | |
2869 | ||
52d939a0 MT |
2870 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
2871 | struct kvm_reinject_control *control) | |
2872 | { | |
2873 | if (!kvm->arch.vpit) | |
2874 | return -ENXIO; | |
894a9c55 | 2875 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
52d939a0 | 2876 | kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject; |
894a9c55 | 2877 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
52d939a0 MT |
2878 | return 0; |
2879 | } | |
2880 | ||
5bb064dc ZX |
2881 | /* |
2882 | * Get (and clear) the dirty memory log for a memory slot. | |
2883 | */ | |
2884 | int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, | |
2885 | struct kvm_dirty_log *log) | |
2886 | { | |
87bf6e7d | 2887 | int r, i; |
5bb064dc | 2888 | struct kvm_memory_slot *memslot; |
87bf6e7d | 2889 | unsigned long n; |
b050b015 | 2890 | unsigned long is_dirty = 0; |
5bb064dc | 2891 | |
79fac95e | 2892 | mutex_lock(&kvm->slots_lock); |
5bb064dc | 2893 | |
b050b015 MT |
2894 | r = -EINVAL; |
2895 | if (log->slot >= KVM_MEMORY_SLOTS) | |
2896 | goto out; | |
2897 | ||
2898 | memslot = &kvm->memslots->memslots[log->slot]; | |
2899 | r = -ENOENT; | |
2900 | if (!memslot->dirty_bitmap) | |
2901 | goto out; | |
2902 | ||
87bf6e7d | 2903 | n = kvm_dirty_bitmap_bytes(memslot); |
b050b015 | 2904 | |
b050b015 MT |
2905 | for (i = 0; !is_dirty && i < n/sizeof(long); i++) |
2906 | is_dirty = memslot->dirty_bitmap[i]; | |
5bb064dc ZX |
2907 | |
2908 | /* If nothing is dirty, don't bother messing with page tables. */ | |
2909 | if (is_dirty) { | |
b050b015 | 2910 | struct kvm_memslots *slots, *old_slots; |
914ebccd | 2911 | unsigned long *dirty_bitmap; |
b050b015 | 2912 | |
7c8a83b7 | 2913 | spin_lock(&kvm->mmu_lock); |
5bb064dc | 2914 | kvm_mmu_slot_remove_write_access(kvm, log->slot); |
7c8a83b7 | 2915 | spin_unlock(&kvm->mmu_lock); |
b050b015 | 2916 | |
914ebccd TY |
2917 | r = -ENOMEM; |
2918 | dirty_bitmap = vmalloc(n); | |
2919 | if (!dirty_bitmap) | |
2920 | goto out; | |
2921 | memset(dirty_bitmap, 0, n); | |
b050b015 | 2922 | |
914ebccd TY |
2923 | r = -ENOMEM; |
2924 | slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL); | |
2925 | if (!slots) { | |
2926 | vfree(dirty_bitmap); | |
2927 | goto out; | |
2928 | } | |
b050b015 MT |
2929 | memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots)); |
2930 | slots->memslots[log->slot].dirty_bitmap = dirty_bitmap; | |
2931 | ||
2932 | old_slots = kvm->memslots; | |
2933 | rcu_assign_pointer(kvm->memslots, slots); | |
2934 | synchronize_srcu_expedited(&kvm->srcu); | |
2935 | dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap; | |
2936 | kfree(old_slots); | |
914ebccd TY |
2937 | |
2938 | r = -EFAULT; | |
2939 | if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) { | |
2940 | vfree(dirty_bitmap); | |
2941 | goto out; | |
2942 | } | |
2943 | vfree(dirty_bitmap); | |
2944 | } else { | |
2945 | r = -EFAULT; | |
2946 | if (clear_user(log->dirty_bitmap, n)) | |
2947 | goto out; | |
5bb064dc | 2948 | } |
b050b015 | 2949 | |
5bb064dc ZX |
2950 | r = 0; |
2951 | out: | |
79fac95e | 2952 | mutex_unlock(&kvm->slots_lock); |
5bb064dc ZX |
2953 | return r; |
2954 | } | |
2955 | ||
1fe779f8 CO |
2956 | long kvm_arch_vm_ioctl(struct file *filp, |
2957 | unsigned int ioctl, unsigned long arg) | |
2958 | { | |
2959 | struct kvm *kvm = filp->private_data; | |
2960 | void __user *argp = (void __user *)arg; | |
367e1319 | 2961 | int r = -ENOTTY; |
f0d66275 DH |
2962 | /* |
2963 | * This union makes it completely explicit to gcc-3.x | |
2964 | * that these two variables' stack usage should be | |
2965 | * combined, not added together. | |
2966 | */ | |
2967 | union { | |
2968 | struct kvm_pit_state ps; | |
e9f42757 | 2969 | struct kvm_pit_state2 ps2; |
c5ff41ce | 2970 | struct kvm_pit_config pit_config; |
f0d66275 | 2971 | } u; |
1fe779f8 CO |
2972 | |
2973 | switch (ioctl) { | |
2974 | case KVM_SET_TSS_ADDR: | |
2975 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
2976 | if (r < 0) | |
2977 | goto out; | |
2978 | break; | |
b927a3ce SY |
2979 | case KVM_SET_IDENTITY_MAP_ADDR: { |
2980 | u64 ident_addr; | |
2981 | ||
2982 | r = -EFAULT; | |
2983 | if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) | |
2984 | goto out; | |
2985 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); | |
2986 | if (r < 0) | |
2987 | goto out; | |
2988 | break; | |
2989 | } | |
1fe779f8 CO |
2990 | case KVM_SET_NR_MMU_PAGES: |
2991 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
2992 | if (r) | |
2993 | goto out; | |
2994 | break; | |
2995 | case KVM_GET_NR_MMU_PAGES: | |
2996 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
2997 | break; | |
3ddea128 MT |
2998 | case KVM_CREATE_IRQCHIP: { |
2999 | struct kvm_pic *vpic; | |
3000 | ||
3001 | mutex_lock(&kvm->lock); | |
3002 | r = -EEXIST; | |
3003 | if (kvm->arch.vpic) | |
3004 | goto create_irqchip_unlock; | |
1fe779f8 | 3005 | r = -ENOMEM; |
3ddea128 MT |
3006 | vpic = kvm_create_pic(kvm); |
3007 | if (vpic) { | |
1fe779f8 CO |
3008 | r = kvm_ioapic_init(kvm); |
3009 | if (r) { | |
72bb2fcd WY |
3010 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, |
3011 | &vpic->dev); | |
3ddea128 MT |
3012 | kfree(vpic); |
3013 | goto create_irqchip_unlock; | |
1fe779f8 CO |
3014 | } |
3015 | } else | |
3ddea128 MT |
3016 | goto create_irqchip_unlock; |
3017 | smp_wmb(); | |
3018 | kvm->arch.vpic = vpic; | |
3019 | smp_wmb(); | |
399ec807 AK |
3020 | r = kvm_setup_default_irq_routing(kvm); |
3021 | if (r) { | |
3ddea128 | 3022 | mutex_lock(&kvm->irq_lock); |
72bb2fcd WY |
3023 | kvm_ioapic_destroy(kvm); |
3024 | kvm_destroy_pic(kvm); | |
3ddea128 | 3025 | mutex_unlock(&kvm->irq_lock); |
399ec807 | 3026 | } |
3ddea128 MT |
3027 | create_irqchip_unlock: |
3028 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 3029 | break; |
3ddea128 | 3030 | } |
7837699f | 3031 | case KVM_CREATE_PIT: |
c5ff41ce JK |
3032 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
3033 | goto create_pit; | |
3034 | case KVM_CREATE_PIT2: | |
3035 | r = -EFAULT; | |
3036 | if (copy_from_user(&u.pit_config, argp, | |
3037 | sizeof(struct kvm_pit_config))) | |
3038 | goto out; | |
3039 | create_pit: | |
79fac95e | 3040 | mutex_lock(&kvm->slots_lock); |
269e05e4 AK |
3041 | r = -EEXIST; |
3042 | if (kvm->arch.vpit) | |
3043 | goto create_pit_unlock; | |
7837699f | 3044 | r = -ENOMEM; |
c5ff41ce | 3045 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
3046 | if (kvm->arch.vpit) |
3047 | r = 0; | |
269e05e4 | 3048 | create_pit_unlock: |
79fac95e | 3049 | mutex_unlock(&kvm->slots_lock); |
7837699f | 3050 | break; |
4925663a | 3051 | case KVM_IRQ_LINE_STATUS: |
1fe779f8 CO |
3052 | case KVM_IRQ_LINE: { |
3053 | struct kvm_irq_level irq_event; | |
3054 | ||
3055 | r = -EFAULT; | |
3056 | if (copy_from_user(&irq_event, argp, sizeof irq_event)) | |
3057 | goto out; | |
160d2f6c | 3058 | r = -ENXIO; |
1fe779f8 | 3059 | if (irqchip_in_kernel(kvm)) { |
4925663a | 3060 | __s32 status; |
4925663a GN |
3061 | status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, |
3062 | irq_event.irq, irq_event.level); | |
4925663a | 3063 | if (ioctl == KVM_IRQ_LINE_STATUS) { |
160d2f6c | 3064 | r = -EFAULT; |
4925663a GN |
3065 | irq_event.status = status; |
3066 | if (copy_to_user(argp, &irq_event, | |
3067 | sizeof irq_event)) | |
3068 | goto out; | |
3069 | } | |
1fe779f8 CO |
3070 | r = 0; |
3071 | } | |
3072 | break; | |
3073 | } | |
3074 | case KVM_GET_IRQCHIP: { | |
3075 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
f0d66275 | 3076 | struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL); |
1fe779f8 | 3077 | |
f0d66275 DH |
3078 | r = -ENOMEM; |
3079 | if (!chip) | |
1fe779f8 | 3080 | goto out; |
f0d66275 DH |
3081 | r = -EFAULT; |
3082 | if (copy_from_user(chip, argp, sizeof *chip)) | |
3083 | goto get_irqchip_out; | |
1fe779f8 CO |
3084 | r = -ENXIO; |
3085 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
3086 | goto get_irqchip_out; |
3087 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 3088 | if (r) |
f0d66275 | 3089 | goto get_irqchip_out; |
1fe779f8 | 3090 | r = -EFAULT; |
f0d66275 DH |
3091 | if (copy_to_user(argp, chip, sizeof *chip)) |
3092 | goto get_irqchip_out; | |
1fe779f8 | 3093 | r = 0; |
f0d66275 DH |
3094 | get_irqchip_out: |
3095 | kfree(chip); | |
3096 | if (r) | |
3097 | goto out; | |
1fe779f8 CO |
3098 | break; |
3099 | } | |
3100 | case KVM_SET_IRQCHIP: { | |
3101 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
f0d66275 | 3102 | struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL); |
1fe779f8 | 3103 | |
f0d66275 DH |
3104 | r = -ENOMEM; |
3105 | if (!chip) | |
1fe779f8 | 3106 | goto out; |
f0d66275 DH |
3107 | r = -EFAULT; |
3108 | if (copy_from_user(chip, argp, sizeof *chip)) | |
3109 | goto set_irqchip_out; | |
1fe779f8 CO |
3110 | r = -ENXIO; |
3111 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
3112 | goto set_irqchip_out; |
3113 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
1fe779f8 | 3114 | if (r) |
f0d66275 | 3115 | goto set_irqchip_out; |
1fe779f8 | 3116 | r = 0; |
f0d66275 DH |
3117 | set_irqchip_out: |
3118 | kfree(chip); | |
3119 | if (r) | |
3120 | goto out; | |
1fe779f8 CO |
3121 | break; |
3122 | } | |
e0f63cb9 | 3123 | case KVM_GET_PIT: { |
e0f63cb9 | 3124 | r = -EFAULT; |
f0d66275 | 3125 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
3126 | goto out; |
3127 | r = -ENXIO; | |
3128 | if (!kvm->arch.vpit) | |
3129 | goto out; | |
f0d66275 | 3130 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
3131 | if (r) |
3132 | goto out; | |
3133 | r = -EFAULT; | |
f0d66275 | 3134 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
3135 | goto out; |
3136 | r = 0; | |
3137 | break; | |
3138 | } | |
3139 | case KVM_SET_PIT: { | |
e0f63cb9 | 3140 | r = -EFAULT; |
f0d66275 | 3141 | if (copy_from_user(&u.ps, argp, sizeof u.ps)) |
e0f63cb9 SY |
3142 | goto out; |
3143 | r = -ENXIO; | |
3144 | if (!kvm->arch.vpit) | |
3145 | goto out; | |
f0d66275 | 3146 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
e0f63cb9 SY |
3147 | if (r) |
3148 | goto out; | |
3149 | r = 0; | |
3150 | break; | |
3151 | } | |
e9f42757 BK |
3152 | case KVM_GET_PIT2: { |
3153 | r = -ENXIO; | |
3154 | if (!kvm->arch.vpit) | |
3155 | goto out; | |
3156 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
3157 | if (r) | |
3158 | goto out; | |
3159 | r = -EFAULT; | |
3160 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
3161 | goto out; | |
3162 | r = 0; | |
3163 | break; | |
3164 | } | |
3165 | case KVM_SET_PIT2: { | |
3166 | r = -EFAULT; | |
3167 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
3168 | goto out; | |
3169 | r = -ENXIO; | |
3170 | if (!kvm->arch.vpit) | |
3171 | goto out; | |
3172 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); | |
3173 | if (r) | |
3174 | goto out; | |
3175 | r = 0; | |
3176 | break; | |
3177 | } | |
52d939a0 MT |
3178 | case KVM_REINJECT_CONTROL: { |
3179 | struct kvm_reinject_control control; | |
3180 | r = -EFAULT; | |
3181 | if (copy_from_user(&control, argp, sizeof(control))) | |
3182 | goto out; | |
3183 | r = kvm_vm_ioctl_reinject(kvm, &control); | |
3184 | if (r) | |
3185 | goto out; | |
3186 | r = 0; | |
3187 | break; | |
3188 | } | |
ffde22ac ES |
3189 | case KVM_XEN_HVM_CONFIG: { |
3190 | r = -EFAULT; | |
3191 | if (copy_from_user(&kvm->arch.xen_hvm_config, argp, | |
3192 | sizeof(struct kvm_xen_hvm_config))) | |
3193 | goto out; | |
3194 | r = -EINVAL; | |
3195 | if (kvm->arch.xen_hvm_config.flags) | |
3196 | goto out; | |
3197 | r = 0; | |
3198 | break; | |
3199 | } | |
afbcf7ab GC |
3200 | case KVM_SET_CLOCK: { |
3201 | struct timespec now; | |
3202 | struct kvm_clock_data user_ns; | |
3203 | u64 now_ns; | |
3204 | s64 delta; | |
3205 | ||
3206 | r = -EFAULT; | |
3207 | if (copy_from_user(&user_ns, argp, sizeof(user_ns))) | |
3208 | goto out; | |
3209 | ||
3210 | r = -EINVAL; | |
3211 | if (user_ns.flags) | |
3212 | goto out; | |
3213 | ||
3214 | r = 0; | |
3215 | ktime_get_ts(&now); | |
3216 | now_ns = timespec_to_ns(&now); | |
3217 | delta = user_ns.clock - now_ns; | |
3218 | kvm->arch.kvmclock_offset = delta; | |
3219 | break; | |
3220 | } | |
3221 | case KVM_GET_CLOCK: { | |
3222 | struct timespec now; | |
3223 | struct kvm_clock_data user_ns; | |
3224 | u64 now_ns; | |
3225 | ||
3226 | ktime_get_ts(&now); | |
3227 | now_ns = timespec_to_ns(&now); | |
3228 | user_ns.clock = kvm->arch.kvmclock_offset + now_ns; | |
3229 | user_ns.flags = 0; | |
3230 | ||
3231 | r = -EFAULT; | |
3232 | if (copy_to_user(argp, &user_ns, sizeof(user_ns))) | |
3233 | goto out; | |
3234 | r = 0; | |
3235 | break; | |
3236 | } | |
3237 | ||
1fe779f8 CO |
3238 | default: |
3239 | ; | |
3240 | } | |
3241 | out: | |
3242 | return r; | |
3243 | } | |
3244 | ||
a16b043c | 3245 | static void kvm_init_msr_list(void) |
043405e1 CO |
3246 | { |
3247 | u32 dummy[2]; | |
3248 | unsigned i, j; | |
3249 | ||
e3267cbb GC |
3250 | /* skip the first msrs in the list. KVM-specific */ |
3251 | for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) { | |
043405e1 CO |
3252 | if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) |
3253 | continue; | |
3254 | if (j < i) | |
3255 | msrs_to_save[j] = msrs_to_save[i]; | |
3256 | j++; | |
3257 | } | |
3258 | num_msrs_to_save = j; | |
3259 | } | |
3260 | ||
bda9020e MT |
3261 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
3262 | const void *v) | |
bbd9b64e | 3263 | { |
bda9020e MT |
3264 | if (vcpu->arch.apic && |
3265 | !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v)) | |
3266 | return 0; | |
bbd9b64e | 3267 | |
e93f8a0f | 3268 | return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v); |
bbd9b64e CO |
3269 | } |
3270 | ||
bda9020e | 3271 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 3272 | { |
bda9020e MT |
3273 | if (vcpu->arch.apic && |
3274 | !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v)) | |
3275 | return 0; | |
bbd9b64e | 3276 | |
e93f8a0f | 3277 | return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v); |
bbd9b64e CO |
3278 | } |
3279 | ||
2dafc6c2 GN |
3280 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
3281 | struct kvm_segment *var, int seg) | |
3282 | { | |
3283 | kvm_x86_ops->set_segment(vcpu, var, seg); | |
3284 | } | |
3285 | ||
3286 | void kvm_get_segment(struct kvm_vcpu *vcpu, | |
3287 | struct kvm_segment *var, int seg) | |
3288 | { | |
3289 | kvm_x86_ops->get_segment(vcpu, var, seg); | |
3290 | } | |
3291 | ||
1871c602 GN |
3292 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error) |
3293 | { | |
3294 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3295 | return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error); | |
3296 | } | |
3297 | ||
3298 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error) | |
3299 | { | |
3300 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3301 | access |= PFERR_FETCH_MASK; | |
3302 | return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error); | |
3303 | } | |
3304 | ||
3305 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error) | |
3306 | { | |
3307 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3308 | access |= PFERR_WRITE_MASK; | |
3309 | return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error); | |
3310 | } | |
3311 | ||
3312 | /* uses this to access any guest's mapped memory without checking CPL */ | |
3313 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error) | |
3314 | { | |
3315 | return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, 0, error); | |
3316 | } | |
3317 | ||
3318 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
3319 | struct kvm_vcpu *vcpu, u32 access, | |
3320 | u32 *error) | |
bbd9b64e CO |
3321 | { |
3322 | void *data = val; | |
10589a46 | 3323 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
3324 | |
3325 | while (bytes) { | |
1871c602 | 3326 | gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr, access, error); |
bbd9b64e | 3327 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 3328 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
3329 | int ret; |
3330 | ||
10589a46 MT |
3331 | if (gpa == UNMAPPED_GVA) { |
3332 | r = X86EMUL_PROPAGATE_FAULT; | |
3333 | goto out; | |
3334 | } | |
77c2002e | 3335 | ret = kvm_read_guest(vcpu->kvm, gpa, data, toread); |
10589a46 | 3336 | if (ret < 0) { |
c3cd7ffa | 3337 | r = X86EMUL_IO_NEEDED; |
10589a46 MT |
3338 | goto out; |
3339 | } | |
bbd9b64e | 3340 | |
77c2002e IE |
3341 | bytes -= toread; |
3342 | data += toread; | |
3343 | addr += toread; | |
bbd9b64e | 3344 | } |
10589a46 | 3345 | out: |
10589a46 | 3346 | return r; |
bbd9b64e | 3347 | } |
77c2002e | 3348 | |
1871c602 GN |
3349 | /* used for instruction fetching */ |
3350 | static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes, | |
3351 | struct kvm_vcpu *vcpu, u32 *error) | |
3352 | { | |
3353 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3354 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, | |
3355 | access | PFERR_FETCH_MASK, error); | |
3356 | } | |
3357 | ||
3358 | static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes, | |
3359 | struct kvm_vcpu *vcpu, u32 *error) | |
3360 | { | |
3361 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3362 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, | |
3363 | error); | |
3364 | } | |
3365 | ||
3366 | static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes, | |
3367 | struct kvm_vcpu *vcpu, u32 *error) | |
3368 | { | |
3369 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error); | |
3370 | } | |
3371 | ||
7972995b | 3372 | static int kvm_write_guest_virt_system(gva_t addr, void *val, |
2dafc6c2 | 3373 | unsigned int bytes, |
7972995b | 3374 | struct kvm_vcpu *vcpu, |
2dafc6c2 | 3375 | u32 *error) |
77c2002e IE |
3376 | { |
3377 | void *data = val; | |
3378 | int r = X86EMUL_CONTINUE; | |
3379 | ||
3380 | while (bytes) { | |
7972995b GN |
3381 | gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr, |
3382 | PFERR_WRITE_MASK, error); | |
77c2002e IE |
3383 | unsigned offset = addr & (PAGE_SIZE-1); |
3384 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
3385 | int ret; | |
3386 | ||
3387 | if (gpa == UNMAPPED_GVA) { | |
3388 | r = X86EMUL_PROPAGATE_FAULT; | |
3389 | goto out; | |
3390 | } | |
3391 | ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite); | |
3392 | if (ret < 0) { | |
c3cd7ffa | 3393 | r = X86EMUL_IO_NEEDED; |
77c2002e IE |
3394 | goto out; |
3395 | } | |
3396 | ||
3397 | bytes -= towrite; | |
3398 | data += towrite; | |
3399 | addr += towrite; | |
3400 | } | |
3401 | out: | |
3402 | return r; | |
3403 | } | |
3404 | ||
bbd9b64e CO |
3405 | static int emulator_read_emulated(unsigned long addr, |
3406 | void *val, | |
3407 | unsigned int bytes, | |
8fe681e9 | 3408 | unsigned int *error_code, |
bbd9b64e CO |
3409 | struct kvm_vcpu *vcpu) |
3410 | { | |
bbd9b64e CO |
3411 | gpa_t gpa; |
3412 | ||
3413 | if (vcpu->mmio_read_completed) { | |
3414 | memcpy(val, vcpu->mmio_data, bytes); | |
aec51dc4 AK |
3415 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
3416 | vcpu->mmio_phys_addr, *(u64 *)val); | |
bbd9b64e CO |
3417 | vcpu->mmio_read_completed = 0; |
3418 | return X86EMUL_CONTINUE; | |
3419 | } | |
3420 | ||
8fe681e9 | 3421 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, error_code); |
1871c602 | 3422 | |
8fe681e9 | 3423 | if (gpa == UNMAPPED_GVA) |
1871c602 | 3424 | return X86EMUL_PROPAGATE_FAULT; |
bbd9b64e CO |
3425 | |
3426 | /* For APIC access vmexit */ | |
3427 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
3428 | goto mmio; | |
3429 | ||
1871c602 | 3430 | if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL) |
77c2002e | 3431 | == X86EMUL_CONTINUE) |
bbd9b64e | 3432 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
3433 | |
3434 | mmio: | |
3435 | /* | |
3436 | * Is this MMIO handled locally? | |
3437 | */ | |
aec51dc4 AK |
3438 | if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) { |
3439 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val); | |
bbd9b64e CO |
3440 | return X86EMUL_CONTINUE; |
3441 | } | |
aec51dc4 AK |
3442 | |
3443 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); | |
bbd9b64e CO |
3444 | |
3445 | vcpu->mmio_needed = 1; | |
411c35b7 GN |
3446 | vcpu->run->exit_reason = KVM_EXIT_MMIO; |
3447 | vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa; | |
3448 | vcpu->run->mmio.len = vcpu->mmio_size = bytes; | |
3449 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0; | |
bbd9b64e | 3450 | |
c3cd7ffa | 3451 | return X86EMUL_IO_NEEDED; |
bbd9b64e CO |
3452 | } |
3453 | ||
3200f405 | 3454 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
9f811285 | 3455 | const void *val, int bytes) |
bbd9b64e CO |
3456 | { |
3457 | int ret; | |
3458 | ||
3459 | ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes); | |
9f811285 | 3460 | if (ret < 0) |
bbd9b64e | 3461 | return 0; |
ad218f85 | 3462 | kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1); |
bbd9b64e CO |
3463 | return 1; |
3464 | } | |
3465 | ||
3466 | static int emulator_write_emulated_onepage(unsigned long addr, | |
3467 | const void *val, | |
3468 | unsigned int bytes, | |
8fe681e9 | 3469 | unsigned int *error_code, |
bbd9b64e CO |
3470 | struct kvm_vcpu *vcpu) |
3471 | { | |
10589a46 MT |
3472 | gpa_t gpa; |
3473 | ||
8fe681e9 | 3474 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error_code); |
bbd9b64e | 3475 | |
8fe681e9 | 3476 | if (gpa == UNMAPPED_GVA) |
bbd9b64e | 3477 | return X86EMUL_PROPAGATE_FAULT; |
bbd9b64e CO |
3478 | |
3479 | /* For APIC access vmexit */ | |
3480 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
3481 | goto mmio; | |
3482 | ||
3483 | if (emulator_write_phys(vcpu, gpa, val, bytes)) | |
3484 | return X86EMUL_CONTINUE; | |
3485 | ||
3486 | mmio: | |
aec51dc4 | 3487 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); |
bbd9b64e CO |
3488 | /* |
3489 | * Is this MMIO handled locally? | |
3490 | */ | |
bda9020e | 3491 | if (!vcpu_mmio_write(vcpu, gpa, bytes, val)) |
bbd9b64e | 3492 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
3493 | |
3494 | vcpu->mmio_needed = 1; | |
411c35b7 GN |
3495 | vcpu->run->exit_reason = KVM_EXIT_MMIO; |
3496 | vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa; | |
3497 | vcpu->run->mmio.len = vcpu->mmio_size = bytes; | |
3498 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1; | |
3499 | memcpy(vcpu->run->mmio.data, val, bytes); | |
bbd9b64e CO |
3500 | |
3501 | return X86EMUL_CONTINUE; | |
3502 | } | |
3503 | ||
3504 | int emulator_write_emulated(unsigned long addr, | |
8f6abd06 GN |
3505 | const void *val, |
3506 | unsigned int bytes, | |
8fe681e9 | 3507 | unsigned int *error_code, |
8f6abd06 | 3508 | struct kvm_vcpu *vcpu) |
bbd9b64e CO |
3509 | { |
3510 | /* Crossing a page boundary? */ | |
3511 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
3512 | int rc, now; | |
3513 | ||
3514 | now = -addr & ~PAGE_MASK; | |
8fe681e9 GN |
3515 | rc = emulator_write_emulated_onepage(addr, val, now, error_code, |
3516 | vcpu); | |
bbd9b64e CO |
3517 | if (rc != X86EMUL_CONTINUE) |
3518 | return rc; | |
3519 | addr += now; | |
3520 | val += now; | |
3521 | bytes -= now; | |
3522 | } | |
8fe681e9 GN |
3523 | return emulator_write_emulated_onepage(addr, val, bytes, error_code, |
3524 | vcpu); | |
bbd9b64e | 3525 | } |
bbd9b64e | 3526 | |
daea3e73 AK |
3527 | #define CMPXCHG_TYPE(t, ptr, old, new) \ |
3528 | (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) | |
3529 | ||
3530 | #ifdef CONFIG_X86_64 | |
3531 | # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) | |
3532 | #else | |
3533 | # define CMPXCHG64(ptr, old, new) \ | |
9749a6c0 | 3534 | (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) |
daea3e73 AK |
3535 | #endif |
3536 | ||
bbd9b64e CO |
3537 | static int emulator_cmpxchg_emulated(unsigned long addr, |
3538 | const void *old, | |
3539 | const void *new, | |
3540 | unsigned int bytes, | |
8fe681e9 | 3541 | unsigned int *error_code, |
bbd9b64e CO |
3542 | struct kvm_vcpu *vcpu) |
3543 | { | |
daea3e73 AK |
3544 | gpa_t gpa; |
3545 | struct page *page; | |
3546 | char *kaddr; | |
3547 | bool exchanged; | |
2bacc55c | 3548 | |
daea3e73 AK |
3549 | /* guests cmpxchg8b have to be emulated atomically */ |
3550 | if (bytes > 8 || (bytes & (bytes - 1))) | |
3551 | goto emul_write; | |
10589a46 | 3552 | |
daea3e73 | 3553 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); |
2bacc55c | 3554 | |
daea3e73 AK |
3555 | if (gpa == UNMAPPED_GVA || |
3556 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
3557 | goto emul_write; | |
2bacc55c | 3558 | |
daea3e73 AK |
3559 | if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) |
3560 | goto emul_write; | |
72dc67a6 | 3561 | |
daea3e73 | 3562 | page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
72dc67a6 | 3563 | |
daea3e73 AK |
3564 | kaddr = kmap_atomic(page, KM_USER0); |
3565 | kaddr += offset_in_page(gpa); | |
3566 | switch (bytes) { | |
3567 | case 1: | |
3568 | exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); | |
3569 | break; | |
3570 | case 2: | |
3571 | exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); | |
3572 | break; | |
3573 | case 4: | |
3574 | exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); | |
3575 | break; | |
3576 | case 8: | |
3577 | exchanged = CMPXCHG64(kaddr, old, new); | |
3578 | break; | |
3579 | default: | |
3580 | BUG(); | |
2bacc55c | 3581 | } |
daea3e73 AK |
3582 | kunmap_atomic(kaddr, KM_USER0); |
3583 | kvm_release_page_dirty(page); | |
3584 | ||
3585 | if (!exchanged) | |
3586 | return X86EMUL_CMPXCHG_FAILED; | |
3587 | ||
8f6abd06 GN |
3588 | kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1); |
3589 | ||
3590 | return X86EMUL_CONTINUE; | |
4a5f48f6 | 3591 | |
3200f405 | 3592 | emul_write: |
daea3e73 | 3593 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); |
2bacc55c | 3594 | |
8fe681e9 | 3595 | return emulator_write_emulated(addr, new, bytes, error_code, vcpu); |
bbd9b64e CO |
3596 | } |
3597 | ||
cf8f70bf GN |
3598 | static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) |
3599 | { | |
3600 | /* TODO: String I/O for in kernel device */ | |
3601 | int r; | |
3602 | ||
3603 | if (vcpu->arch.pio.in) | |
3604 | r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port, | |
3605 | vcpu->arch.pio.size, pd); | |
3606 | else | |
3607 | r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS, | |
3608 | vcpu->arch.pio.port, vcpu->arch.pio.size, | |
3609 | pd); | |
3610 | return r; | |
3611 | } | |
3612 | ||
3613 | ||
3614 | static int emulator_pio_in_emulated(int size, unsigned short port, void *val, | |
3615 | unsigned int count, struct kvm_vcpu *vcpu) | |
3616 | { | |
7972995b | 3617 | if (vcpu->arch.pio.count) |
cf8f70bf GN |
3618 | goto data_avail; |
3619 | ||
3620 | trace_kvm_pio(1, port, size, 1); | |
3621 | ||
3622 | vcpu->arch.pio.port = port; | |
3623 | vcpu->arch.pio.in = 1; | |
7972995b | 3624 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
3625 | vcpu->arch.pio.size = size; |
3626 | ||
3627 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
3628 | data_avail: | |
3629 | memcpy(val, vcpu->arch.pio_data, size * count); | |
7972995b | 3630 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
3631 | return 1; |
3632 | } | |
3633 | ||
3634 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
3635 | vcpu->run->io.direction = KVM_EXIT_IO_IN; | |
3636 | vcpu->run->io.size = size; | |
3637 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
3638 | vcpu->run->io.count = count; | |
3639 | vcpu->run->io.port = port; | |
3640 | ||
3641 | return 0; | |
3642 | } | |
3643 | ||
3644 | static int emulator_pio_out_emulated(int size, unsigned short port, | |
3645 | const void *val, unsigned int count, | |
3646 | struct kvm_vcpu *vcpu) | |
3647 | { | |
3648 | trace_kvm_pio(0, port, size, 1); | |
3649 | ||
3650 | vcpu->arch.pio.port = port; | |
3651 | vcpu->arch.pio.in = 0; | |
7972995b | 3652 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
3653 | vcpu->arch.pio.size = size; |
3654 | ||
3655 | memcpy(vcpu->arch.pio_data, val, size * count); | |
3656 | ||
3657 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
7972995b | 3658 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
3659 | return 1; |
3660 | } | |
3661 | ||
3662 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
3663 | vcpu->run->io.direction = KVM_EXIT_IO_OUT; | |
3664 | vcpu->run->io.size = size; | |
3665 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
3666 | vcpu->run->io.count = count; | |
3667 | vcpu->run->io.port = port; | |
3668 | ||
3669 | return 0; | |
3670 | } | |
3671 | ||
bbd9b64e CO |
3672 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) |
3673 | { | |
3674 | return kvm_x86_ops->get_segment_base(vcpu, seg); | |
3675 | } | |
3676 | ||
3677 | int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address) | |
3678 | { | |
a7052897 | 3679 | kvm_mmu_invlpg(vcpu, address); |
bbd9b64e CO |
3680 | return X86EMUL_CONTINUE; |
3681 | } | |
3682 | ||
f5f48ee1 SY |
3683 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) |
3684 | { | |
3685 | if (!need_emulate_wbinvd(vcpu)) | |
3686 | return X86EMUL_CONTINUE; | |
3687 | ||
3688 | if (kvm_x86_ops->has_wbinvd_exit()) { | |
3689 | smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, | |
3690 | wbinvd_ipi, NULL, 1); | |
3691 | cpumask_clear(vcpu->arch.wbinvd_dirty_mask); | |
3692 | } | |
3693 | wbinvd(); | |
3694 | return X86EMUL_CONTINUE; | |
3695 | } | |
3696 | EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); | |
3697 | ||
bbd9b64e CO |
3698 | int emulate_clts(struct kvm_vcpu *vcpu) |
3699 | { | |
4d4ec087 | 3700 | kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); |
6b52d186 | 3701 | kvm_x86_ops->fpu_activate(vcpu); |
bbd9b64e CO |
3702 | return X86EMUL_CONTINUE; |
3703 | } | |
3704 | ||
35aa5375 | 3705 | int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu) |
bbd9b64e | 3706 | { |
338dbc97 | 3707 | return _kvm_get_dr(vcpu, dr, dest); |
bbd9b64e CO |
3708 | } |
3709 | ||
35aa5375 | 3710 | int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu) |
bbd9b64e | 3711 | { |
338dbc97 GN |
3712 | |
3713 | return __kvm_set_dr(vcpu, dr, value); | |
bbd9b64e CO |
3714 | } |
3715 | ||
52a46617 | 3716 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) |
5fdbf976 | 3717 | { |
52a46617 | 3718 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; |
5fdbf976 MT |
3719 | } |
3720 | ||
52a46617 | 3721 | static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu) |
bbd9b64e | 3722 | { |
52a46617 GN |
3723 | unsigned long value; |
3724 | ||
3725 | switch (cr) { | |
3726 | case 0: | |
3727 | value = kvm_read_cr0(vcpu); | |
3728 | break; | |
3729 | case 2: | |
3730 | value = vcpu->arch.cr2; | |
3731 | break; | |
3732 | case 3: | |
3733 | value = vcpu->arch.cr3; | |
3734 | break; | |
3735 | case 4: | |
3736 | value = kvm_read_cr4(vcpu); | |
3737 | break; | |
3738 | case 8: | |
3739 | value = kvm_get_cr8(vcpu); | |
3740 | break; | |
3741 | default: | |
3742 | vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr); | |
3743 | return 0; | |
3744 | } | |
3745 | ||
3746 | return value; | |
3747 | } | |
3748 | ||
0f12244f | 3749 | static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu) |
52a46617 | 3750 | { |
0f12244f GN |
3751 | int res = 0; |
3752 | ||
52a46617 GN |
3753 | switch (cr) { |
3754 | case 0: | |
49a9b07e | 3755 | res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
52a46617 GN |
3756 | break; |
3757 | case 2: | |
3758 | vcpu->arch.cr2 = val; | |
3759 | break; | |
3760 | case 3: | |
2390218b | 3761 | res = kvm_set_cr3(vcpu, val); |
52a46617 GN |
3762 | break; |
3763 | case 4: | |
a83b29c6 | 3764 | res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
52a46617 GN |
3765 | break; |
3766 | case 8: | |
0f12244f | 3767 | res = __kvm_set_cr8(vcpu, val & 0xfUL); |
52a46617 GN |
3768 | break; |
3769 | default: | |
3770 | vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr); | |
0f12244f | 3771 | res = -1; |
52a46617 | 3772 | } |
0f12244f GN |
3773 | |
3774 | return res; | |
52a46617 GN |
3775 | } |
3776 | ||
9c537244 GN |
3777 | static int emulator_get_cpl(struct kvm_vcpu *vcpu) |
3778 | { | |
3779 | return kvm_x86_ops->get_cpl(vcpu); | |
3780 | } | |
3781 | ||
2dafc6c2 GN |
3782 | static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu) |
3783 | { | |
3784 | kvm_x86_ops->get_gdt(vcpu, dt); | |
3785 | } | |
3786 | ||
5951c442 GN |
3787 | static unsigned long emulator_get_cached_segment_base(int seg, |
3788 | struct kvm_vcpu *vcpu) | |
3789 | { | |
3790 | return get_segment_base(vcpu, seg); | |
3791 | } | |
3792 | ||
2dafc6c2 GN |
3793 | static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg, |
3794 | struct kvm_vcpu *vcpu) | |
3795 | { | |
3796 | struct kvm_segment var; | |
3797 | ||
3798 | kvm_get_segment(vcpu, &var, seg); | |
3799 | ||
3800 | if (var.unusable) | |
3801 | return false; | |
3802 | ||
3803 | if (var.g) | |
3804 | var.limit >>= 12; | |
3805 | set_desc_limit(desc, var.limit); | |
3806 | set_desc_base(desc, (unsigned long)var.base); | |
3807 | desc->type = var.type; | |
3808 | desc->s = var.s; | |
3809 | desc->dpl = var.dpl; | |
3810 | desc->p = var.present; | |
3811 | desc->avl = var.avl; | |
3812 | desc->l = var.l; | |
3813 | desc->d = var.db; | |
3814 | desc->g = var.g; | |
3815 | ||
3816 | return true; | |
3817 | } | |
3818 | ||
3819 | static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg, | |
3820 | struct kvm_vcpu *vcpu) | |
3821 | { | |
3822 | struct kvm_segment var; | |
3823 | ||
3824 | /* needed to preserve selector */ | |
3825 | kvm_get_segment(vcpu, &var, seg); | |
3826 | ||
3827 | var.base = get_desc_base(desc); | |
3828 | var.limit = get_desc_limit(desc); | |
3829 | if (desc->g) | |
3830 | var.limit = (var.limit << 12) | 0xfff; | |
3831 | var.type = desc->type; | |
3832 | var.present = desc->p; | |
3833 | var.dpl = desc->dpl; | |
3834 | var.db = desc->d; | |
3835 | var.s = desc->s; | |
3836 | var.l = desc->l; | |
3837 | var.g = desc->g; | |
3838 | var.avl = desc->avl; | |
3839 | var.present = desc->p; | |
3840 | var.unusable = !var.present; | |
3841 | var.padding = 0; | |
3842 | ||
3843 | kvm_set_segment(vcpu, &var, seg); | |
3844 | return; | |
3845 | } | |
3846 | ||
3847 | static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu) | |
3848 | { | |
3849 | struct kvm_segment kvm_seg; | |
3850 | ||
3851 | kvm_get_segment(vcpu, &kvm_seg, seg); | |
3852 | return kvm_seg.selector; | |
3853 | } | |
3854 | ||
3855 | static void emulator_set_segment_selector(u16 sel, int seg, | |
3856 | struct kvm_vcpu *vcpu) | |
3857 | { | |
3858 | struct kvm_segment kvm_seg; | |
3859 | ||
3860 | kvm_get_segment(vcpu, &kvm_seg, seg); | |
3861 | kvm_seg.selector = sel; | |
3862 | kvm_set_segment(vcpu, &kvm_seg, seg); | |
3863 | } | |
3864 | ||
14af3f3c | 3865 | static struct x86_emulate_ops emulate_ops = { |
1871c602 | 3866 | .read_std = kvm_read_guest_virt_system, |
2dafc6c2 | 3867 | .write_std = kvm_write_guest_virt_system, |
1871c602 | 3868 | .fetch = kvm_fetch_guest_virt, |
bbd9b64e CO |
3869 | .read_emulated = emulator_read_emulated, |
3870 | .write_emulated = emulator_write_emulated, | |
3871 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
cf8f70bf GN |
3872 | .pio_in_emulated = emulator_pio_in_emulated, |
3873 | .pio_out_emulated = emulator_pio_out_emulated, | |
2dafc6c2 GN |
3874 | .get_cached_descriptor = emulator_get_cached_descriptor, |
3875 | .set_cached_descriptor = emulator_set_cached_descriptor, | |
3876 | .get_segment_selector = emulator_get_segment_selector, | |
3877 | .set_segment_selector = emulator_set_segment_selector, | |
5951c442 | 3878 | .get_cached_segment_base = emulator_get_cached_segment_base, |
2dafc6c2 | 3879 | .get_gdt = emulator_get_gdt, |
52a46617 GN |
3880 | .get_cr = emulator_get_cr, |
3881 | .set_cr = emulator_set_cr, | |
9c537244 | 3882 | .cpl = emulator_get_cpl, |
35aa5375 GN |
3883 | .get_dr = emulator_get_dr, |
3884 | .set_dr = emulator_set_dr, | |
3fb1b5db GN |
3885 | .set_msr = kvm_set_msr, |
3886 | .get_msr = kvm_get_msr, | |
bbd9b64e CO |
3887 | }; |
3888 | ||
5fdbf976 MT |
3889 | static void cache_all_regs(struct kvm_vcpu *vcpu) |
3890 | { | |
3891 | kvm_register_read(vcpu, VCPU_REGS_RAX); | |
3892 | kvm_register_read(vcpu, VCPU_REGS_RSP); | |
3893 | kvm_register_read(vcpu, VCPU_REGS_RIP); | |
3894 | vcpu->arch.regs_dirty = ~0; | |
3895 | } | |
3896 | ||
95cb2295 GN |
3897 | static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) |
3898 | { | |
3899 | u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask); | |
3900 | /* | |
3901 | * an sti; sti; sequence only disable interrupts for the first | |
3902 | * instruction. So, if the last instruction, be it emulated or | |
3903 | * not, left the system with the INT_STI flag enabled, it | |
3904 | * means that the last instruction is an sti. We should not | |
3905 | * leave the flag on in this case. The same goes for mov ss | |
3906 | */ | |
3907 | if (!(int_shadow & mask)) | |
3908 | kvm_x86_ops->set_interrupt_shadow(vcpu, mask); | |
3909 | } | |
3910 | ||
54b8486f GN |
3911 | static void inject_emulated_exception(struct kvm_vcpu *vcpu) |
3912 | { | |
3913 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; | |
3914 | if (ctxt->exception == PF_VECTOR) | |
3915 | kvm_inject_page_fault(vcpu, ctxt->cr2, ctxt->error_code); | |
3916 | else if (ctxt->error_code_valid) | |
3917 | kvm_queue_exception_e(vcpu, ctxt->exception, ctxt->error_code); | |
3918 | else | |
3919 | kvm_queue_exception(vcpu, ctxt->exception); | |
3920 | } | |
3921 | ||
6d77dbfc GN |
3922 | static int handle_emulation_failure(struct kvm_vcpu *vcpu) |
3923 | { | |
6d77dbfc GN |
3924 | ++vcpu->stat.insn_emulation_fail; |
3925 | trace_kvm_emulate_insn_failed(vcpu); | |
3926 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
3927 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
3928 | vcpu->run->internal.ndata = 0; | |
3929 | kvm_queue_exception(vcpu, UD_VECTOR); | |
3930 | return EMULATE_FAIL; | |
3931 | } | |
3932 | ||
a6f177ef GN |
3933 | static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva) |
3934 | { | |
3935 | gpa_t gpa; | |
3936 | ||
3937 | /* | |
3938 | * if emulation was due to access to shadowed page table | |
3939 | * and it failed try to unshadow page and re-entetr the | |
3940 | * guest to let CPU execute the instruction. | |
3941 | */ | |
3942 | if (kvm_mmu_unprotect_page_virt(vcpu, gva)) | |
3943 | return true; | |
3944 | ||
3945 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL); | |
3946 | ||
3947 | if (gpa == UNMAPPED_GVA) | |
3948 | return true; /* let cpu generate fault */ | |
3949 | ||
3950 | if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT))) | |
3951 | return true; | |
3952 | ||
3953 | return false; | |
3954 | } | |
3955 | ||
bbd9b64e | 3956 | int emulate_instruction(struct kvm_vcpu *vcpu, |
bbd9b64e CO |
3957 | unsigned long cr2, |
3958 | u16 error_code, | |
571008da | 3959 | int emulation_type) |
bbd9b64e | 3960 | { |
95cb2295 | 3961 | int r; |
4d2179e1 | 3962 | struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode; |
bbd9b64e | 3963 | |
26eef70c | 3964 | kvm_clear_exception_queue(vcpu); |
ad312c7c | 3965 | vcpu->arch.mmio_fault_cr2 = cr2; |
5fdbf976 | 3966 | /* |
56e82318 | 3967 | * TODO: fix emulate.c to use guest_read/write_register |
5fdbf976 MT |
3968 | * instead of direct ->regs accesses, can save hundred cycles |
3969 | * on Intel for instructions that don't read/change RSP, for | |
3970 | * for example. | |
3971 | */ | |
3972 | cache_all_regs(vcpu); | |
bbd9b64e | 3973 | |
571008da | 3974 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
bbd9b64e CO |
3975 | int cs_db, cs_l; |
3976 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
3977 | ||
ad312c7c | 3978 | vcpu->arch.emulate_ctxt.vcpu = vcpu; |
83bf0002 | 3979 | vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu); |
063db061 | 3980 | vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu); |
ad312c7c | 3981 | vcpu->arch.emulate_ctxt.mode = |
a0044755 | 3982 | (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : |
ad312c7c | 3983 | (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM) |
a0044755 | 3984 | ? X86EMUL_MODE_VM86 : cs_l |
bbd9b64e CO |
3985 | ? X86EMUL_MODE_PROT64 : cs_db |
3986 | ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16; | |
4d2179e1 GN |
3987 | memset(c, 0, sizeof(struct decode_cache)); |
3988 | memcpy(c->regs, vcpu->arch.regs, sizeof c->regs); | |
95cb2295 | 3989 | vcpu->arch.emulate_ctxt.interruptibility = 0; |
54b8486f | 3990 | vcpu->arch.emulate_ctxt.exception = -1; |
bbd9b64e | 3991 | |
ad312c7c | 3992 | r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops); |
e46479f8 | 3993 | trace_kvm_emulate_insn_start(vcpu); |
571008da | 3994 | |
0cb5762e AP |
3995 | /* Only allow emulation of specific instructions on #UD |
3996 | * (namely VMMCALL, sysenter, sysexit, syscall)*/ | |
0cb5762e AP |
3997 | if (emulation_type & EMULTYPE_TRAP_UD) { |
3998 | if (!c->twobyte) | |
3999 | return EMULATE_FAIL; | |
4000 | switch (c->b) { | |
4001 | case 0x01: /* VMMCALL */ | |
4002 | if (c->modrm_mod != 3 || c->modrm_rm != 1) | |
4003 | return EMULATE_FAIL; | |
4004 | break; | |
4005 | case 0x34: /* sysenter */ | |
4006 | case 0x35: /* sysexit */ | |
4007 | if (c->modrm_mod != 0 || c->modrm_rm != 0) | |
4008 | return EMULATE_FAIL; | |
4009 | break; | |
4010 | case 0x05: /* syscall */ | |
4011 | if (c->modrm_mod != 0 || c->modrm_rm != 0) | |
4012 | return EMULATE_FAIL; | |
4013 | break; | |
4014 | default: | |
4015 | return EMULATE_FAIL; | |
4016 | } | |
4017 | ||
4018 | if (!(c->modrm_reg == 0 || c->modrm_reg == 3)) | |
4019 | return EMULATE_FAIL; | |
4020 | } | |
571008da | 4021 | |
f2b5756b | 4022 | ++vcpu->stat.insn_emulation; |
bbd9b64e | 4023 | if (r) { |
a6f177ef | 4024 | if (reexecute_instruction(vcpu, cr2)) |
bbd9b64e | 4025 | return EMULATE_DONE; |
6d77dbfc GN |
4026 | if (emulation_type & EMULTYPE_SKIP) |
4027 | return EMULATE_FAIL; | |
4028 | return handle_emulation_failure(vcpu); | |
bbd9b64e CO |
4029 | } |
4030 | } | |
4031 | ||
ba8afb6b GN |
4032 | if (emulation_type & EMULTYPE_SKIP) { |
4033 | kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip); | |
4034 | return EMULATE_DONE; | |
4035 | } | |
4036 | ||
4d2179e1 GN |
4037 | /* this is needed for vmware backdor interface to work since it |
4038 | changes registers values during IO operation */ | |
4039 | memcpy(c->regs, vcpu->arch.regs, sizeof c->regs); | |
4040 | ||
5cd21917 | 4041 | restart: |
ad312c7c | 4042 | r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops); |
bbd9b64e | 4043 | |
c3cd7ffa | 4044 | if (r) { /* emulation failed */ |
a6f177ef | 4045 | if (reexecute_instruction(vcpu, cr2)) |
c3cd7ffa GN |
4046 | return EMULATE_DONE; |
4047 | ||
6d77dbfc | 4048 | return handle_emulation_failure(vcpu); |
bbd9b64e CO |
4049 | } |
4050 | ||
95cb2295 | 4051 | toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility); |
ef050dc0 | 4052 | kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags); |
4d2179e1 | 4053 | memcpy(vcpu->arch.regs, c->regs, sizeof c->regs); |
95c55886 | 4054 | kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip); |
3457e419 | 4055 | |
54b8486f GN |
4056 | if (vcpu->arch.emulate_ctxt.exception >= 0) { |
4057 | inject_emulated_exception(vcpu); | |
4058 | return EMULATE_DONE; | |
4059 | } | |
4060 | ||
3457e419 GN |
4061 | if (vcpu->arch.pio.count) { |
4062 | if (!vcpu->arch.pio.in) | |
4063 | vcpu->arch.pio.count = 0; | |
4064 | return EMULATE_DO_MMIO; | |
4065 | } | |
4066 | ||
4067 | if (vcpu->mmio_needed) { | |
4068 | if (vcpu->mmio_is_write) | |
4069 | vcpu->mmio_needed = 0; | |
4070 | return EMULATE_DO_MMIO; | |
4071 | } | |
4072 | ||
5cd21917 GN |
4073 | if (vcpu->arch.emulate_ctxt.restart) |
4074 | goto restart; | |
f850e2e6 | 4075 | |
bbd9b64e | 4076 | return EMULATE_DONE; |
de7d789a | 4077 | } |
bbd9b64e | 4078 | EXPORT_SYMBOL_GPL(emulate_instruction); |
de7d789a | 4079 | |
cf8f70bf | 4080 | int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port) |
de7d789a | 4081 | { |
cf8f70bf GN |
4082 | unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); |
4083 | int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu); | |
4084 | /* do not return to emulator after return from userspace */ | |
7972995b | 4085 | vcpu->arch.pio.count = 0; |
de7d789a CO |
4086 | return ret; |
4087 | } | |
cf8f70bf | 4088 | EXPORT_SYMBOL_GPL(kvm_fast_pio_out); |
de7d789a | 4089 | |
c8076604 GH |
4090 | static void bounce_off(void *info) |
4091 | { | |
4092 | /* nothing */ | |
4093 | } | |
4094 | ||
c8076604 GH |
4095 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, |
4096 | void *data) | |
4097 | { | |
4098 | struct cpufreq_freqs *freq = data; | |
4099 | struct kvm *kvm; | |
4100 | struct kvm_vcpu *vcpu; | |
4101 | int i, send_ipi = 0; | |
4102 | ||
c8076604 GH |
4103 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) |
4104 | return 0; | |
4105 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
4106 | return 0; | |
0cca7907 | 4107 | per_cpu(cpu_tsc_khz, freq->cpu) = freq->new; |
c8076604 GH |
4108 | |
4109 | spin_lock(&kvm_lock); | |
4110 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
988a2cae | 4111 | kvm_for_each_vcpu(i, vcpu, kvm) { |
c8076604 GH |
4112 | if (vcpu->cpu != freq->cpu) |
4113 | continue; | |
4114 | if (!kvm_request_guest_time_update(vcpu)) | |
4115 | continue; | |
4116 | if (vcpu->cpu != smp_processor_id()) | |
4117 | send_ipi++; | |
4118 | } | |
4119 | } | |
4120 | spin_unlock(&kvm_lock); | |
4121 | ||
4122 | if (freq->old < freq->new && send_ipi) { | |
4123 | /* | |
4124 | * We upscale the frequency. Must make the guest | |
4125 | * doesn't see old kvmclock values while running with | |
4126 | * the new frequency, otherwise we risk the guest sees | |
4127 | * time go backwards. | |
4128 | * | |
4129 | * In case we update the frequency for another cpu | |
4130 | * (which might be in guest context) send an interrupt | |
4131 | * to kick the cpu out of guest context. Next time | |
4132 | * guest context is entered kvmclock will be updated, | |
4133 | * so the guest will not see stale values. | |
4134 | */ | |
4135 | smp_call_function_single(freq->cpu, bounce_off, NULL, 1); | |
4136 | } | |
4137 | return 0; | |
4138 | } | |
4139 | ||
4140 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
4141 | .notifier_call = kvmclock_cpufreq_notifier | |
4142 | }; | |
4143 | ||
b820cc0c ZA |
4144 | static void kvm_timer_init(void) |
4145 | { | |
4146 | int cpu; | |
4147 | ||
b820cc0c | 4148 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
b820cc0c ZA |
4149 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
4150 | CPUFREQ_TRANSITION_NOTIFIER); | |
6b7d7e76 ZA |
4151 | for_each_online_cpu(cpu) { |
4152 | unsigned long khz = cpufreq_get(cpu); | |
4153 | if (!khz) | |
4154 | khz = tsc_khz; | |
4155 | per_cpu(cpu_tsc_khz, cpu) = khz; | |
4156 | } | |
0cca7907 ZA |
4157 | } else { |
4158 | for_each_possible_cpu(cpu) | |
4159 | per_cpu(cpu_tsc_khz, cpu) = tsc_khz; | |
b820cc0c ZA |
4160 | } |
4161 | } | |
4162 | ||
ff9d07a0 ZY |
4163 | static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); |
4164 | ||
4165 | static int kvm_is_in_guest(void) | |
4166 | { | |
4167 | return percpu_read(current_vcpu) != NULL; | |
4168 | } | |
4169 | ||
4170 | static int kvm_is_user_mode(void) | |
4171 | { | |
4172 | int user_mode = 3; | |
dcf46b94 | 4173 | |
ff9d07a0 ZY |
4174 | if (percpu_read(current_vcpu)) |
4175 | user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu)); | |
dcf46b94 | 4176 | |
ff9d07a0 ZY |
4177 | return user_mode != 0; |
4178 | } | |
4179 | ||
4180 | static unsigned long kvm_get_guest_ip(void) | |
4181 | { | |
4182 | unsigned long ip = 0; | |
dcf46b94 | 4183 | |
ff9d07a0 ZY |
4184 | if (percpu_read(current_vcpu)) |
4185 | ip = kvm_rip_read(percpu_read(current_vcpu)); | |
dcf46b94 | 4186 | |
ff9d07a0 ZY |
4187 | return ip; |
4188 | } | |
4189 | ||
4190 | static struct perf_guest_info_callbacks kvm_guest_cbs = { | |
4191 | .is_in_guest = kvm_is_in_guest, | |
4192 | .is_user_mode = kvm_is_user_mode, | |
4193 | .get_guest_ip = kvm_get_guest_ip, | |
4194 | }; | |
4195 | ||
4196 | void kvm_before_handle_nmi(struct kvm_vcpu *vcpu) | |
4197 | { | |
4198 | percpu_write(current_vcpu, vcpu); | |
4199 | } | |
4200 | EXPORT_SYMBOL_GPL(kvm_before_handle_nmi); | |
4201 | ||
4202 | void kvm_after_handle_nmi(struct kvm_vcpu *vcpu) | |
4203 | { | |
4204 | percpu_write(current_vcpu, NULL); | |
4205 | } | |
4206 | EXPORT_SYMBOL_GPL(kvm_after_handle_nmi); | |
4207 | ||
f8c16bba | 4208 | int kvm_arch_init(void *opaque) |
043405e1 | 4209 | { |
b820cc0c | 4210 | int r; |
f8c16bba ZX |
4211 | struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque; |
4212 | ||
f8c16bba ZX |
4213 | if (kvm_x86_ops) { |
4214 | printk(KERN_ERR "kvm: already loaded the other module\n"); | |
56c6d28a ZX |
4215 | r = -EEXIST; |
4216 | goto out; | |
f8c16bba ZX |
4217 | } |
4218 | ||
4219 | if (!ops->cpu_has_kvm_support()) { | |
4220 | printk(KERN_ERR "kvm: no hardware support\n"); | |
56c6d28a ZX |
4221 | r = -EOPNOTSUPP; |
4222 | goto out; | |
f8c16bba ZX |
4223 | } |
4224 | if (ops->disabled_by_bios()) { | |
4225 | printk(KERN_ERR "kvm: disabled by bios\n"); | |
56c6d28a ZX |
4226 | r = -EOPNOTSUPP; |
4227 | goto out; | |
f8c16bba ZX |
4228 | } |
4229 | ||
97db56ce AK |
4230 | r = kvm_mmu_module_init(); |
4231 | if (r) | |
4232 | goto out; | |
4233 | ||
4234 | kvm_init_msr_list(); | |
4235 | ||
f8c16bba | 4236 | kvm_x86_ops = ops; |
56c6d28a | 4237 | kvm_mmu_set_nonpresent_ptes(0ull, 0ull); |
7b52345e SY |
4238 | kvm_mmu_set_base_ptes(PT_PRESENT_MASK); |
4239 | kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, | |
4b12f0de | 4240 | PT_DIRTY_MASK, PT64_NX_MASK, 0); |
c8076604 | 4241 | |
b820cc0c | 4242 | kvm_timer_init(); |
c8076604 | 4243 | |
ff9d07a0 ZY |
4244 | perf_register_guest_info_callbacks(&kvm_guest_cbs); |
4245 | ||
2acf923e DC |
4246 | if (cpu_has_xsave) |
4247 | host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); | |
4248 | ||
f8c16bba | 4249 | return 0; |
56c6d28a ZX |
4250 | |
4251 | out: | |
56c6d28a | 4252 | return r; |
043405e1 | 4253 | } |
8776e519 | 4254 | |
f8c16bba ZX |
4255 | void kvm_arch_exit(void) |
4256 | { | |
ff9d07a0 ZY |
4257 | perf_unregister_guest_info_callbacks(&kvm_guest_cbs); |
4258 | ||
888d256e JK |
4259 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
4260 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
4261 | CPUFREQ_TRANSITION_NOTIFIER); | |
f8c16bba | 4262 | kvm_x86_ops = NULL; |
56c6d28a ZX |
4263 | kvm_mmu_module_exit(); |
4264 | } | |
f8c16bba | 4265 | |
8776e519 HB |
4266 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) |
4267 | { | |
4268 | ++vcpu->stat.halt_exits; | |
4269 | if (irqchip_in_kernel(vcpu->kvm)) { | |
a4535290 | 4270 | vcpu->arch.mp_state = KVM_MP_STATE_HALTED; |
8776e519 HB |
4271 | return 1; |
4272 | } else { | |
4273 | vcpu->run->exit_reason = KVM_EXIT_HLT; | |
4274 | return 0; | |
4275 | } | |
4276 | } | |
4277 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); | |
4278 | ||
2f333bcb MT |
4279 | static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0, |
4280 | unsigned long a1) | |
4281 | { | |
4282 | if (is_long_mode(vcpu)) | |
4283 | return a0; | |
4284 | else | |
4285 | return a0 | ((gpa_t)a1 << 32); | |
4286 | } | |
4287 | ||
55cd8e5a GN |
4288 | int kvm_hv_hypercall(struct kvm_vcpu *vcpu) |
4289 | { | |
4290 | u64 param, ingpa, outgpa, ret; | |
4291 | uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0; | |
4292 | bool fast, longmode; | |
4293 | int cs_db, cs_l; | |
4294 | ||
4295 | /* | |
4296 | * hypercall generates UD from non zero cpl and real mode | |
4297 | * per HYPER-V spec | |
4298 | */ | |
3eeb3288 | 4299 | if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) { |
55cd8e5a GN |
4300 | kvm_queue_exception(vcpu, UD_VECTOR); |
4301 | return 0; | |
4302 | } | |
4303 | ||
4304 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
4305 | longmode = is_long_mode(vcpu) && cs_l == 1; | |
4306 | ||
4307 | if (!longmode) { | |
ccd46936 GN |
4308 | param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) | |
4309 | (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff); | |
4310 | ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) | | |
4311 | (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff); | |
4312 | outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) | | |
4313 | (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff); | |
55cd8e5a GN |
4314 | } |
4315 | #ifdef CONFIG_X86_64 | |
4316 | else { | |
4317 | param = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
4318 | ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
4319 | outgpa = kvm_register_read(vcpu, VCPU_REGS_R8); | |
4320 | } | |
4321 | #endif | |
4322 | ||
4323 | code = param & 0xffff; | |
4324 | fast = (param >> 16) & 0x1; | |
4325 | rep_cnt = (param >> 32) & 0xfff; | |
4326 | rep_idx = (param >> 48) & 0xfff; | |
4327 | ||
4328 | trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa); | |
4329 | ||
c25bc163 GN |
4330 | switch (code) { |
4331 | case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT: | |
4332 | kvm_vcpu_on_spin(vcpu); | |
4333 | break; | |
4334 | default: | |
4335 | res = HV_STATUS_INVALID_HYPERCALL_CODE; | |
4336 | break; | |
4337 | } | |
55cd8e5a GN |
4338 | |
4339 | ret = res | (((u64)rep_done & 0xfff) << 32); | |
4340 | if (longmode) { | |
4341 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); | |
4342 | } else { | |
4343 | kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32); | |
4344 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff); | |
4345 | } | |
4346 | ||
4347 | return 1; | |
4348 | } | |
4349 | ||
8776e519 HB |
4350 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
4351 | { | |
4352 | unsigned long nr, a0, a1, a2, a3, ret; | |
2f333bcb | 4353 | int r = 1; |
8776e519 | 4354 | |
55cd8e5a GN |
4355 | if (kvm_hv_hypercall_enabled(vcpu->kvm)) |
4356 | return kvm_hv_hypercall(vcpu); | |
4357 | ||
5fdbf976 MT |
4358 | nr = kvm_register_read(vcpu, VCPU_REGS_RAX); |
4359 | a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
4360 | a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
4361 | a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
4362 | a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
8776e519 | 4363 | |
229456fc | 4364 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 4365 | |
8776e519 HB |
4366 | if (!is_long_mode(vcpu)) { |
4367 | nr &= 0xFFFFFFFF; | |
4368 | a0 &= 0xFFFFFFFF; | |
4369 | a1 &= 0xFFFFFFFF; | |
4370 | a2 &= 0xFFFFFFFF; | |
4371 | a3 &= 0xFFFFFFFF; | |
4372 | } | |
4373 | ||
07708c4a JK |
4374 | if (kvm_x86_ops->get_cpl(vcpu) != 0) { |
4375 | ret = -KVM_EPERM; | |
4376 | goto out; | |
4377 | } | |
4378 | ||
8776e519 | 4379 | switch (nr) { |
b93463aa AK |
4380 | case KVM_HC_VAPIC_POLL_IRQ: |
4381 | ret = 0; | |
4382 | break; | |
2f333bcb MT |
4383 | case KVM_HC_MMU_OP: |
4384 | r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret); | |
4385 | break; | |
8776e519 HB |
4386 | default: |
4387 | ret = -KVM_ENOSYS; | |
4388 | break; | |
4389 | } | |
07708c4a | 4390 | out: |
5fdbf976 | 4391 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); |
f11c3a8d | 4392 | ++vcpu->stat.hypercalls; |
2f333bcb | 4393 | return r; |
8776e519 HB |
4394 | } |
4395 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
4396 | ||
4397 | int kvm_fix_hypercall(struct kvm_vcpu *vcpu) | |
4398 | { | |
4399 | char instruction[3]; | |
5fdbf976 | 4400 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 4401 | |
8776e519 HB |
4402 | /* |
4403 | * Blow out the MMU to ensure that no other VCPU has an active mapping | |
4404 | * to ensure that the updated hypercall appears atomically across all | |
4405 | * VCPUs. | |
4406 | */ | |
4407 | kvm_mmu_zap_all(vcpu->kvm); | |
4408 | ||
8776e519 | 4409 | kvm_x86_ops->patch_hypercall(vcpu, instruction); |
8776e519 | 4410 | |
8fe681e9 | 4411 | return emulator_write_emulated(rip, instruction, 3, NULL, vcpu); |
8776e519 HB |
4412 | } |
4413 | ||
8776e519 HB |
4414 | void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base) |
4415 | { | |
89a27f4d | 4416 | struct desc_ptr dt = { limit, base }; |
8776e519 HB |
4417 | |
4418 | kvm_x86_ops->set_gdt(vcpu, &dt); | |
4419 | } | |
4420 | ||
4421 | void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base) | |
4422 | { | |
89a27f4d | 4423 | struct desc_ptr dt = { limit, base }; |
8776e519 HB |
4424 | |
4425 | kvm_x86_ops->set_idt(vcpu, &dt); | |
4426 | } | |
4427 | ||
07716717 DK |
4428 | static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i) |
4429 | { | |
ad312c7c ZX |
4430 | struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i]; |
4431 | int j, nent = vcpu->arch.cpuid_nent; | |
07716717 DK |
4432 | |
4433 | e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT; | |
4434 | /* when no next entry is found, the current entry[i] is reselected */ | |
0fdf8e59 | 4435 | for (j = i + 1; ; j = (j + 1) % nent) { |
ad312c7c | 4436 | struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j]; |
07716717 DK |
4437 | if (ej->function == e->function) { |
4438 | ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT; | |
4439 | return j; | |
4440 | } | |
4441 | } | |
4442 | return 0; /* silence gcc, even though control never reaches here */ | |
4443 | } | |
4444 | ||
4445 | /* find an entry with matching function, matching index (if needed), and that | |
4446 | * should be read next (if it's stateful) */ | |
4447 | static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e, | |
4448 | u32 function, u32 index) | |
4449 | { | |
4450 | if (e->function != function) | |
4451 | return 0; | |
4452 | if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index) | |
4453 | return 0; | |
4454 | if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) && | |
19355475 | 4455 | !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT)) |
07716717 DK |
4456 | return 0; |
4457 | return 1; | |
4458 | } | |
4459 | ||
d8017474 AG |
4460 | struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu, |
4461 | u32 function, u32 index) | |
8776e519 HB |
4462 | { |
4463 | int i; | |
d8017474 | 4464 | struct kvm_cpuid_entry2 *best = NULL; |
8776e519 | 4465 | |
ad312c7c | 4466 | for (i = 0; i < vcpu->arch.cpuid_nent; ++i) { |
d8017474 AG |
4467 | struct kvm_cpuid_entry2 *e; |
4468 | ||
ad312c7c | 4469 | e = &vcpu->arch.cpuid_entries[i]; |
07716717 DK |
4470 | if (is_matching_cpuid_entry(e, function, index)) { |
4471 | if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) | |
4472 | move_to_next_stateful_cpuid_entry(vcpu, i); | |
8776e519 HB |
4473 | best = e; |
4474 | break; | |
4475 | } | |
4476 | /* | |
4477 | * Both basic or both extended? | |
4478 | */ | |
4479 | if (((e->function ^ function) & 0x80000000) == 0) | |
4480 | if (!best || e->function > best->function) | |
4481 | best = e; | |
4482 | } | |
d8017474 AG |
4483 | return best; |
4484 | } | |
0e851880 | 4485 | EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry); |
d8017474 | 4486 | |
82725b20 DE |
4487 | int cpuid_maxphyaddr(struct kvm_vcpu *vcpu) |
4488 | { | |
4489 | struct kvm_cpuid_entry2 *best; | |
4490 | ||
f7a71197 AK |
4491 | best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0); |
4492 | if (!best || best->eax < 0x80000008) | |
4493 | goto not_found; | |
82725b20 DE |
4494 | best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0); |
4495 | if (best) | |
4496 | return best->eax & 0xff; | |
f7a71197 | 4497 | not_found: |
82725b20 DE |
4498 | return 36; |
4499 | } | |
4500 | ||
d8017474 AG |
4501 | void kvm_emulate_cpuid(struct kvm_vcpu *vcpu) |
4502 | { | |
4503 | u32 function, index; | |
4504 | struct kvm_cpuid_entry2 *best; | |
4505 | ||
4506 | function = kvm_register_read(vcpu, VCPU_REGS_RAX); | |
4507 | index = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
4508 | kvm_register_write(vcpu, VCPU_REGS_RAX, 0); | |
4509 | kvm_register_write(vcpu, VCPU_REGS_RBX, 0); | |
4510 | kvm_register_write(vcpu, VCPU_REGS_RCX, 0); | |
4511 | kvm_register_write(vcpu, VCPU_REGS_RDX, 0); | |
4512 | best = kvm_find_cpuid_entry(vcpu, function, index); | |
8776e519 | 4513 | if (best) { |
5fdbf976 MT |
4514 | kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax); |
4515 | kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx); | |
4516 | kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx); | |
4517 | kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx); | |
8776e519 | 4518 | } |
8776e519 | 4519 | kvm_x86_ops->skip_emulated_instruction(vcpu); |
229456fc MT |
4520 | trace_kvm_cpuid(function, |
4521 | kvm_register_read(vcpu, VCPU_REGS_RAX), | |
4522 | kvm_register_read(vcpu, VCPU_REGS_RBX), | |
4523 | kvm_register_read(vcpu, VCPU_REGS_RCX), | |
4524 | kvm_register_read(vcpu, VCPU_REGS_RDX)); | |
8776e519 HB |
4525 | } |
4526 | EXPORT_SYMBOL_GPL(kvm_emulate_cpuid); | |
d0752060 | 4527 | |
b6c7a5dc HB |
4528 | /* |
4529 | * Check if userspace requested an interrupt window, and that the | |
4530 | * interrupt window is open. | |
4531 | * | |
4532 | * No need to exit to userspace if we already have an interrupt queued. | |
4533 | */ | |
851ba692 | 4534 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 4535 | { |
8061823a | 4536 | return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) && |
851ba692 | 4537 | vcpu->run->request_interrupt_window && |
5df56646 | 4538 | kvm_arch_interrupt_allowed(vcpu)); |
b6c7a5dc HB |
4539 | } |
4540 | ||
851ba692 | 4541 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 4542 | { |
851ba692 AK |
4543 | struct kvm_run *kvm_run = vcpu->run; |
4544 | ||
91586a3b | 4545 | kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; |
2d3ad1f4 | 4546 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 4547 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
4531220b | 4548 | if (irqchip_in_kernel(vcpu->kvm)) |
b6c7a5dc | 4549 | kvm_run->ready_for_interrupt_injection = 1; |
4531220b | 4550 | else |
b6c7a5dc | 4551 | kvm_run->ready_for_interrupt_injection = |
fa9726b0 GN |
4552 | kvm_arch_interrupt_allowed(vcpu) && |
4553 | !kvm_cpu_has_interrupt(vcpu) && | |
4554 | !kvm_event_needs_reinjection(vcpu); | |
b6c7a5dc HB |
4555 | } |
4556 | ||
b93463aa AK |
4557 | static void vapic_enter(struct kvm_vcpu *vcpu) |
4558 | { | |
4559 | struct kvm_lapic *apic = vcpu->arch.apic; | |
4560 | struct page *page; | |
4561 | ||
4562 | if (!apic || !apic->vapic_addr) | |
4563 | return; | |
4564 | ||
4565 | page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT); | |
72dc67a6 IE |
4566 | |
4567 | vcpu->arch.apic->vapic_page = page; | |
b93463aa AK |
4568 | } |
4569 | ||
4570 | static void vapic_exit(struct kvm_vcpu *vcpu) | |
4571 | { | |
4572 | struct kvm_lapic *apic = vcpu->arch.apic; | |
f656ce01 | 4573 | int idx; |
b93463aa AK |
4574 | |
4575 | if (!apic || !apic->vapic_addr) | |
4576 | return; | |
4577 | ||
f656ce01 | 4578 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
b93463aa AK |
4579 | kvm_release_page_dirty(apic->vapic_page); |
4580 | mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT); | |
f656ce01 | 4581 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b93463aa AK |
4582 | } |
4583 | ||
95ba8273 GN |
4584 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
4585 | { | |
4586 | int max_irr, tpr; | |
4587 | ||
4588 | if (!kvm_x86_ops->update_cr8_intercept) | |
4589 | return; | |
4590 | ||
88c808fd AK |
4591 | if (!vcpu->arch.apic) |
4592 | return; | |
4593 | ||
8db3baa2 GN |
4594 | if (!vcpu->arch.apic->vapic_addr) |
4595 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
4596 | else | |
4597 | max_irr = -1; | |
95ba8273 GN |
4598 | |
4599 | if (max_irr != -1) | |
4600 | max_irr >>= 4; | |
4601 | ||
4602 | tpr = kvm_lapic_get_cr8(vcpu); | |
4603 | ||
4604 | kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); | |
4605 | } | |
4606 | ||
851ba692 | 4607 | static void inject_pending_event(struct kvm_vcpu *vcpu) |
95ba8273 GN |
4608 | { |
4609 | /* try to reinject previous events if any */ | |
b59bb7bd | 4610 | if (vcpu->arch.exception.pending) { |
5c1c85d0 AK |
4611 | trace_kvm_inj_exception(vcpu->arch.exception.nr, |
4612 | vcpu->arch.exception.has_error_code, | |
4613 | vcpu->arch.exception.error_code); | |
b59bb7bd GN |
4614 | kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, |
4615 | vcpu->arch.exception.has_error_code, | |
ce7ddec4 JR |
4616 | vcpu->arch.exception.error_code, |
4617 | vcpu->arch.exception.reinject); | |
b59bb7bd GN |
4618 | return; |
4619 | } | |
4620 | ||
95ba8273 GN |
4621 | if (vcpu->arch.nmi_injected) { |
4622 | kvm_x86_ops->set_nmi(vcpu); | |
4623 | return; | |
4624 | } | |
4625 | ||
4626 | if (vcpu->arch.interrupt.pending) { | |
66fd3f7f | 4627 | kvm_x86_ops->set_irq(vcpu); |
95ba8273 GN |
4628 | return; |
4629 | } | |
4630 | ||
4631 | /* try to inject new event if pending */ | |
4632 | if (vcpu->arch.nmi_pending) { | |
4633 | if (kvm_x86_ops->nmi_allowed(vcpu)) { | |
4634 | vcpu->arch.nmi_pending = false; | |
4635 | vcpu->arch.nmi_injected = true; | |
4636 | kvm_x86_ops->set_nmi(vcpu); | |
4637 | } | |
4638 | } else if (kvm_cpu_has_interrupt(vcpu)) { | |
4639 | if (kvm_x86_ops->interrupt_allowed(vcpu)) { | |
66fd3f7f GN |
4640 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), |
4641 | false); | |
4642 | kvm_x86_ops->set_irq(vcpu); | |
95ba8273 GN |
4643 | } |
4644 | } | |
4645 | } | |
4646 | ||
2acf923e DC |
4647 | static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) |
4648 | { | |
4649 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && | |
4650 | !vcpu->guest_xcr0_loaded) { | |
4651 | /* kvm_set_xcr() also depends on this */ | |
4652 | xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); | |
4653 | vcpu->guest_xcr0_loaded = 1; | |
4654 | } | |
4655 | } | |
4656 | ||
4657 | static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) | |
4658 | { | |
4659 | if (vcpu->guest_xcr0_loaded) { | |
4660 | if (vcpu->arch.xcr0 != host_xcr0) | |
4661 | xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); | |
4662 | vcpu->guest_xcr0_loaded = 0; | |
4663 | } | |
4664 | } | |
4665 | ||
851ba692 | 4666 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
4667 | { |
4668 | int r; | |
6a8b1d13 | 4669 | bool req_int_win = !irqchip_in_kernel(vcpu->kvm) && |
851ba692 | 4670 | vcpu->run->request_interrupt_window; |
b6c7a5dc | 4671 | |
3e007509 | 4672 | if (vcpu->requests) { |
a8eeb04a | 4673 | if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) |
2e53d63a | 4674 | kvm_mmu_unload(vcpu); |
a8eeb04a | 4675 | if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) |
2f599714 | 4676 | __kvm_migrate_timers(vcpu); |
a8eeb04a | 4677 | if (kvm_check_request(KVM_REQ_KVMCLOCK_UPDATE, vcpu)) |
c8076604 | 4678 | kvm_write_guest_time(vcpu); |
a8eeb04a | 4679 | if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) |
4731d4c7 | 4680 | kvm_mmu_sync_roots(vcpu); |
a8eeb04a | 4681 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) |
d4acf7e7 | 4682 | kvm_x86_ops->tlb_flush(vcpu); |
a8eeb04a | 4683 | if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { |
851ba692 | 4684 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
4685 | r = 0; |
4686 | goto out; | |
4687 | } | |
a8eeb04a | 4688 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
851ba692 | 4689 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
71c4dfaf JR |
4690 | r = 0; |
4691 | goto out; | |
4692 | } | |
a8eeb04a | 4693 | if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) { |
02daab21 AK |
4694 | vcpu->fpu_active = 0; |
4695 | kvm_x86_ops->fpu_deactivate(vcpu); | |
4696 | } | |
2f52d58c | 4697 | } |
b93463aa | 4698 | |
3e007509 AK |
4699 | r = kvm_mmu_reload(vcpu); |
4700 | if (unlikely(r)) | |
4701 | goto out; | |
4702 | ||
b6c7a5dc HB |
4703 | preempt_disable(); |
4704 | ||
4705 | kvm_x86_ops->prepare_guest_switch(vcpu); | |
2608d7a1 AK |
4706 | if (vcpu->fpu_active) |
4707 | kvm_load_guest_fpu(vcpu); | |
2acf923e | 4708 | kvm_load_guest_xcr0(vcpu); |
b6c7a5dc | 4709 | |
d94e1dc9 AK |
4710 | atomic_set(&vcpu->guest_mode, 1); |
4711 | smp_wmb(); | |
b6c7a5dc | 4712 | |
d94e1dc9 | 4713 | local_irq_disable(); |
32f88400 | 4714 | |
d94e1dc9 AK |
4715 | if (!atomic_read(&vcpu->guest_mode) || vcpu->requests |
4716 | || need_resched() || signal_pending(current)) { | |
4717 | atomic_set(&vcpu->guest_mode, 0); | |
4718 | smp_wmb(); | |
6c142801 AK |
4719 | local_irq_enable(); |
4720 | preempt_enable(); | |
4721 | r = 1; | |
4722 | goto out; | |
4723 | } | |
4724 | ||
851ba692 | 4725 | inject_pending_event(vcpu); |
b6c7a5dc | 4726 | |
6a8b1d13 GN |
4727 | /* enable NMI/IRQ window open exits if needed */ |
4728 | if (vcpu->arch.nmi_pending) | |
4729 | kvm_x86_ops->enable_nmi_window(vcpu); | |
4730 | else if (kvm_cpu_has_interrupt(vcpu) || req_int_win) | |
4731 | kvm_x86_ops->enable_irq_window(vcpu); | |
4732 | ||
95ba8273 | 4733 | if (kvm_lapic_enabled(vcpu)) { |
8db3baa2 GN |
4734 | update_cr8_intercept(vcpu); |
4735 | kvm_lapic_sync_to_vapic(vcpu); | |
95ba8273 | 4736 | } |
b93463aa | 4737 | |
f656ce01 | 4738 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
3200f405 | 4739 | |
b6c7a5dc HB |
4740 | kvm_guest_enter(); |
4741 | ||
42dbaa5a | 4742 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
4743 | set_debugreg(0, 7); |
4744 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
4745 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
4746 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
4747 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
4748 | } | |
b6c7a5dc | 4749 | |
229456fc | 4750 | trace_kvm_entry(vcpu->vcpu_id); |
851ba692 | 4751 | kvm_x86_ops->run(vcpu); |
b6c7a5dc | 4752 | |
24f1e32c FW |
4753 | /* |
4754 | * If the guest has used debug registers, at least dr7 | |
4755 | * will be disabled while returning to the host. | |
4756 | * If we don't have active breakpoints in the host, we don't | |
4757 | * care about the messed up debug address registers. But if | |
4758 | * we have some of them active, restore the old state. | |
4759 | */ | |
59d8eb53 | 4760 | if (hw_breakpoint_active()) |
24f1e32c | 4761 | hw_breakpoint_restore(); |
42dbaa5a | 4762 | |
d94e1dc9 AK |
4763 | atomic_set(&vcpu->guest_mode, 0); |
4764 | smp_wmb(); | |
b6c7a5dc HB |
4765 | local_irq_enable(); |
4766 | ||
4767 | ++vcpu->stat.exits; | |
4768 | ||
4769 | /* | |
4770 | * We must have an instruction between local_irq_enable() and | |
4771 | * kvm_guest_exit(), so the timer interrupt isn't delayed by | |
4772 | * the interrupt shadow. The stat.exits increment will do nicely. | |
4773 | * But we need to prevent reordering, hence this barrier(): | |
4774 | */ | |
4775 | barrier(); | |
4776 | ||
4777 | kvm_guest_exit(); | |
4778 | ||
4779 | preempt_enable(); | |
4780 | ||
f656ce01 | 4781 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
3200f405 | 4782 | |
b6c7a5dc HB |
4783 | /* |
4784 | * Profile KVM exit RIPs: | |
4785 | */ | |
4786 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
4787 | unsigned long rip = kvm_rip_read(vcpu); |
4788 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
4789 | } |
4790 | ||
298101da | 4791 | |
b93463aa AK |
4792 | kvm_lapic_sync_from_vapic(vcpu); |
4793 | ||
851ba692 | 4794 | r = kvm_x86_ops->handle_exit(vcpu); |
d7690175 MT |
4795 | out: |
4796 | return r; | |
4797 | } | |
b6c7a5dc | 4798 | |
09cec754 | 4799 | |
851ba692 | 4800 | static int __vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
4801 | { |
4802 | int r; | |
f656ce01 | 4803 | struct kvm *kvm = vcpu->kvm; |
d7690175 MT |
4804 | |
4805 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) { | |
1b10bf31 JK |
4806 | pr_debug("vcpu %d received sipi with vector # %x\n", |
4807 | vcpu->vcpu_id, vcpu->arch.sipi_vector); | |
d7690175 | 4808 | kvm_lapic_reset(vcpu); |
5f179287 | 4809 | r = kvm_arch_vcpu_reset(vcpu); |
d7690175 MT |
4810 | if (r) |
4811 | return r; | |
4812 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
b6c7a5dc HB |
4813 | } |
4814 | ||
f656ce01 | 4815 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 MT |
4816 | vapic_enter(vcpu); |
4817 | ||
4818 | r = 1; | |
4819 | while (r > 0) { | |
af2152f5 | 4820 | if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE) |
851ba692 | 4821 | r = vcpu_enter_guest(vcpu); |
d7690175 | 4822 | else { |
f656ce01 | 4823 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
d7690175 | 4824 | kvm_vcpu_block(vcpu); |
f656ce01 | 4825 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
a8eeb04a | 4826 | if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) |
09cec754 GN |
4827 | { |
4828 | switch(vcpu->arch.mp_state) { | |
4829 | case KVM_MP_STATE_HALTED: | |
d7690175 | 4830 | vcpu->arch.mp_state = |
09cec754 GN |
4831 | KVM_MP_STATE_RUNNABLE; |
4832 | case KVM_MP_STATE_RUNNABLE: | |
4833 | break; | |
4834 | case KVM_MP_STATE_SIPI_RECEIVED: | |
4835 | default: | |
4836 | r = -EINTR; | |
4837 | break; | |
4838 | } | |
4839 | } | |
d7690175 MT |
4840 | } |
4841 | ||
09cec754 GN |
4842 | if (r <= 0) |
4843 | break; | |
4844 | ||
4845 | clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); | |
4846 | if (kvm_cpu_has_pending_timer(vcpu)) | |
4847 | kvm_inject_pending_timer_irqs(vcpu); | |
4848 | ||
851ba692 | 4849 | if (dm_request_for_irq_injection(vcpu)) { |
09cec754 | 4850 | r = -EINTR; |
851ba692 | 4851 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 GN |
4852 | ++vcpu->stat.request_irq_exits; |
4853 | } | |
4854 | if (signal_pending(current)) { | |
4855 | r = -EINTR; | |
851ba692 | 4856 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 GN |
4857 | ++vcpu->stat.signal_exits; |
4858 | } | |
4859 | if (need_resched()) { | |
f656ce01 | 4860 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
09cec754 | 4861 | kvm_resched(vcpu); |
f656ce01 | 4862 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 4863 | } |
b6c7a5dc HB |
4864 | } |
4865 | ||
f656ce01 | 4866 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
b6c7a5dc | 4867 | |
b93463aa AK |
4868 | vapic_exit(vcpu); |
4869 | ||
b6c7a5dc HB |
4870 | return r; |
4871 | } | |
4872 | ||
4873 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
4874 | { | |
4875 | int r; | |
4876 | sigset_t sigsaved; | |
4877 | ||
ac9f6dc0 AK |
4878 | if (vcpu->sigset_active) |
4879 | sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); | |
4880 | ||
a4535290 | 4881 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
b6c7a5dc | 4882 | kvm_vcpu_block(vcpu); |
d7690175 | 4883 | clear_bit(KVM_REQ_UNHALT, &vcpu->requests); |
ac9f6dc0 AK |
4884 | r = -EAGAIN; |
4885 | goto out; | |
b6c7a5dc HB |
4886 | } |
4887 | ||
b6c7a5dc HB |
4888 | /* re-sync apic's tpr */ |
4889 | if (!irqchip_in_kernel(vcpu->kvm)) | |
2d3ad1f4 | 4890 | kvm_set_cr8(vcpu, kvm_run->cr8); |
b6c7a5dc | 4891 | |
92bf9748 GN |
4892 | if (vcpu->arch.pio.count || vcpu->mmio_needed || |
4893 | vcpu->arch.emulate_ctxt.restart) { | |
4894 | if (vcpu->mmio_needed) { | |
4895 | memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8); | |
4896 | vcpu->mmio_read_completed = 1; | |
4897 | vcpu->mmio_needed = 0; | |
b6c7a5dc | 4898 | } |
f656ce01 | 4899 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
5cd21917 | 4900 | r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE); |
f656ce01 | 4901 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
6d77dbfc | 4902 | if (r != EMULATE_DONE) { |
b6c7a5dc HB |
4903 | r = 0; |
4904 | goto out; | |
4905 | } | |
4906 | } | |
5fdbf976 MT |
4907 | if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL) |
4908 | kvm_register_write(vcpu, VCPU_REGS_RAX, | |
4909 | kvm_run->hypercall.ret); | |
b6c7a5dc | 4910 | |
851ba692 | 4911 | r = __vcpu_run(vcpu); |
b6c7a5dc HB |
4912 | |
4913 | out: | |
f1d86e46 | 4914 | post_kvm_run_save(vcpu); |
b6c7a5dc HB |
4915 | if (vcpu->sigset_active) |
4916 | sigprocmask(SIG_SETMASK, &sigsaved, NULL); | |
4917 | ||
b6c7a5dc HB |
4918 | return r; |
4919 | } | |
4920 | ||
4921 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
4922 | { | |
5fdbf976 MT |
4923 | regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); |
4924 | regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
4925 | regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
4926 | regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
4927 | regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
4928 | regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
4929 | regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
4930 | regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); | |
b6c7a5dc | 4931 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
4932 | regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); |
4933 | regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); | |
4934 | regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); | |
4935 | regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); | |
4936 | regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); | |
4937 | regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); | |
4938 | regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); | |
4939 | regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); | |
b6c7a5dc HB |
4940 | #endif |
4941 | ||
5fdbf976 | 4942 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 4943 | regs->rflags = kvm_get_rflags(vcpu); |
b6c7a5dc | 4944 | |
b6c7a5dc HB |
4945 | return 0; |
4946 | } | |
4947 | ||
4948 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
4949 | { | |
5fdbf976 MT |
4950 | kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); |
4951 | kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); | |
4952 | kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); | |
4953 | kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); | |
4954 | kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); | |
4955 | kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); | |
4956 | kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); | |
4957 | kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); | |
b6c7a5dc | 4958 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
4959 | kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); |
4960 | kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); | |
4961 | kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); | |
4962 | kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); | |
4963 | kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); | |
4964 | kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); | |
4965 | kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); | |
4966 | kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); | |
b6c7a5dc HB |
4967 | #endif |
4968 | ||
5fdbf976 | 4969 | kvm_rip_write(vcpu, regs->rip); |
91586a3b | 4970 | kvm_set_rflags(vcpu, regs->rflags); |
b6c7a5dc | 4971 | |
b4f14abd JK |
4972 | vcpu->arch.exception.pending = false; |
4973 | ||
b6c7a5dc HB |
4974 | return 0; |
4975 | } | |
4976 | ||
b6c7a5dc HB |
4977 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
4978 | { | |
4979 | struct kvm_segment cs; | |
4980 | ||
3e6e0aab | 4981 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
4982 | *db = cs.db; |
4983 | *l = cs.l; | |
4984 | } | |
4985 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
4986 | ||
4987 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, | |
4988 | struct kvm_sregs *sregs) | |
4989 | { | |
89a27f4d | 4990 | struct desc_ptr dt; |
b6c7a5dc | 4991 | |
3e6e0aab GT |
4992 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
4993 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
4994 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
4995 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
4996 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
4997 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 4998 | |
3e6e0aab GT |
4999 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
5000 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc HB |
5001 | |
5002 | kvm_x86_ops->get_idt(vcpu, &dt); | |
89a27f4d GN |
5003 | sregs->idt.limit = dt.size; |
5004 | sregs->idt.base = dt.address; | |
b6c7a5dc | 5005 | kvm_x86_ops->get_gdt(vcpu, &dt); |
89a27f4d GN |
5006 | sregs->gdt.limit = dt.size; |
5007 | sregs->gdt.base = dt.address; | |
b6c7a5dc | 5008 | |
4d4ec087 | 5009 | sregs->cr0 = kvm_read_cr0(vcpu); |
ad312c7c ZX |
5010 | sregs->cr2 = vcpu->arch.cr2; |
5011 | sregs->cr3 = vcpu->arch.cr3; | |
fc78f519 | 5012 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 5013 | sregs->cr8 = kvm_get_cr8(vcpu); |
f6801dff | 5014 | sregs->efer = vcpu->arch.efer; |
b6c7a5dc HB |
5015 | sregs->apic_base = kvm_get_apic_base(vcpu); |
5016 | ||
923c61bb | 5017 | memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); |
b6c7a5dc | 5018 | |
36752c9b | 5019 | if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
5020 | set_bit(vcpu->arch.interrupt.nr, |
5021 | (unsigned long *)sregs->interrupt_bitmap); | |
16d7a191 | 5022 | |
b6c7a5dc HB |
5023 | return 0; |
5024 | } | |
5025 | ||
62d9f0db MT |
5026 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
5027 | struct kvm_mp_state *mp_state) | |
5028 | { | |
62d9f0db | 5029 | mp_state->mp_state = vcpu->arch.mp_state; |
62d9f0db MT |
5030 | return 0; |
5031 | } | |
5032 | ||
5033 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
5034 | struct kvm_mp_state *mp_state) | |
5035 | { | |
62d9f0db | 5036 | vcpu->arch.mp_state = mp_state->mp_state; |
62d9f0db MT |
5037 | return 0; |
5038 | } | |
5039 | ||
e269fb21 JK |
5040 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason, |
5041 | bool has_error_code, u32 error_code) | |
b6c7a5dc | 5042 | { |
4d2179e1 | 5043 | struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode; |
ceffb459 GN |
5044 | int cs_db, cs_l, ret; |
5045 | cache_all_regs(vcpu); | |
37817f29 | 5046 | |
ceffb459 | 5047 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
e01c2426 | 5048 | |
ceffb459 GN |
5049 | vcpu->arch.emulate_ctxt.vcpu = vcpu; |
5050 | vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu); | |
5051 | vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu); | |
5052 | vcpu->arch.emulate_ctxt.mode = | |
5053 | (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : | |
5054 | (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM) | |
5055 | ? X86EMUL_MODE_VM86 : cs_l | |
5056 | ? X86EMUL_MODE_PROT64 : cs_db | |
5057 | ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16; | |
4d2179e1 GN |
5058 | memset(c, 0, sizeof(struct decode_cache)); |
5059 | memcpy(c->regs, vcpu->arch.regs, sizeof c->regs); | |
c697518a | 5060 | |
ceffb459 | 5061 | ret = emulator_task_switch(&vcpu->arch.emulate_ctxt, &emulate_ops, |
e269fb21 JK |
5062 | tss_selector, reason, has_error_code, |
5063 | error_code); | |
c697518a | 5064 | |
c697518a | 5065 | if (ret) |
19d04437 | 5066 | return EMULATE_FAIL; |
37817f29 | 5067 | |
4d2179e1 | 5068 | memcpy(vcpu->arch.regs, c->regs, sizeof c->regs); |
95c55886 | 5069 | kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip); |
19d04437 GN |
5070 | kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags); |
5071 | return EMULATE_DONE; | |
37817f29 IE |
5072 | } |
5073 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
5074 | ||
b6c7a5dc HB |
5075 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, |
5076 | struct kvm_sregs *sregs) | |
5077 | { | |
5078 | int mmu_reset_needed = 0; | |
923c61bb | 5079 | int pending_vec, max_bits; |
89a27f4d | 5080 | struct desc_ptr dt; |
b6c7a5dc | 5081 | |
89a27f4d GN |
5082 | dt.size = sregs->idt.limit; |
5083 | dt.address = sregs->idt.base; | |
b6c7a5dc | 5084 | kvm_x86_ops->set_idt(vcpu, &dt); |
89a27f4d GN |
5085 | dt.size = sregs->gdt.limit; |
5086 | dt.address = sregs->gdt.base; | |
b6c7a5dc HB |
5087 | kvm_x86_ops->set_gdt(vcpu, &dt); |
5088 | ||
ad312c7c ZX |
5089 | vcpu->arch.cr2 = sregs->cr2; |
5090 | mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3; | |
dc7e795e | 5091 | vcpu->arch.cr3 = sregs->cr3; |
b6c7a5dc | 5092 | |
2d3ad1f4 | 5093 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 5094 | |
f6801dff | 5095 | mmu_reset_needed |= vcpu->arch.efer != sregs->efer; |
b6c7a5dc | 5096 | kvm_x86_ops->set_efer(vcpu, sregs->efer); |
b6c7a5dc HB |
5097 | kvm_set_apic_base(vcpu, sregs->apic_base); |
5098 | ||
4d4ec087 | 5099 | mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
b6c7a5dc | 5100 | kvm_x86_ops->set_cr0(vcpu, sregs->cr0); |
d7306163 | 5101 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 5102 | |
fc78f519 | 5103 | mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
b6c7a5dc | 5104 | kvm_x86_ops->set_cr4(vcpu, sregs->cr4); |
7c93be44 | 5105 | if (!is_long_mode(vcpu) && is_pae(vcpu)) { |
ad312c7c | 5106 | load_pdptrs(vcpu, vcpu->arch.cr3); |
7c93be44 MT |
5107 | mmu_reset_needed = 1; |
5108 | } | |
b6c7a5dc HB |
5109 | |
5110 | if (mmu_reset_needed) | |
5111 | kvm_mmu_reset_context(vcpu); | |
5112 | ||
923c61bb GN |
5113 | max_bits = (sizeof sregs->interrupt_bitmap) << 3; |
5114 | pending_vec = find_first_bit( | |
5115 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
5116 | if (pending_vec < max_bits) { | |
66fd3f7f | 5117 | kvm_queue_interrupt(vcpu, pending_vec, false); |
923c61bb GN |
5118 | pr_debug("Set back pending irq %d\n", pending_vec); |
5119 | if (irqchip_in_kernel(vcpu->kvm)) | |
5120 | kvm_pic_clear_isr_ack(vcpu->kvm); | |
b6c7a5dc HB |
5121 | } |
5122 | ||
3e6e0aab GT |
5123 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
5124 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
5125 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
5126 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
5127 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
5128 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 5129 | |
3e6e0aab GT |
5130 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
5131 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 5132 | |
5f0269f5 ME |
5133 | update_cr8_intercept(vcpu); |
5134 | ||
9c3e4aab | 5135 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 5136 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 5137 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
3eeb3288 | 5138 | !is_protmode(vcpu)) |
9c3e4aab MT |
5139 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
5140 | ||
b6c7a5dc HB |
5141 | return 0; |
5142 | } | |
5143 | ||
d0bfb940 JK |
5144 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
5145 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 5146 | { |
355be0b9 | 5147 | unsigned long rflags; |
ae675ef0 | 5148 | int i, r; |
b6c7a5dc | 5149 | |
4f926bf2 JK |
5150 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
5151 | r = -EBUSY; | |
5152 | if (vcpu->arch.exception.pending) | |
2122ff5e | 5153 | goto out; |
4f926bf2 JK |
5154 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
5155 | kvm_queue_exception(vcpu, DB_VECTOR); | |
5156 | else | |
5157 | kvm_queue_exception(vcpu, BP_VECTOR); | |
5158 | } | |
5159 | ||
91586a3b JK |
5160 | /* |
5161 | * Read rflags as long as potentially injected trace flags are still | |
5162 | * filtered out. | |
5163 | */ | |
5164 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
5165 | |
5166 | vcpu->guest_debug = dbg->control; | |
5167 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
5168 | vcpu->guest_debug = 0; | |
5169 | ||
5170 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
5171 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
5172 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
5173 | vcpu->arch.switch_db_regs = | |
5174 | (dbg->arch.debugreg[7] & DR7_BP_EN_MASK); | |
5175 | } else { | |
5176 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
5177 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
5178 | vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK); | |
5179 | } | |
5180 | ||
f92653ee JK |
5181 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
5182 | vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + | |
5183 | get_segment_base(vcpu, VCPU_SREG_CS); | |
94fe45da | 5184 | |
91586a3b JK |
5185 | /* |
5186 | * Trigger an rflags update that will inject or remove the trace | |
5187 | * flags. | |
5188 | */ | |
5189 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 5190 | |
355be0b9 | 5191 | kvm_x86_ops->set_guest_debug(vcpu, dbg); |
b6c7a5dc | 5192 | |
4f926bf2 | 5193 | r = 0; |
d0bfb940 | 5194 | |
2122ff5e | 5195 | out: |
b6c7a5dc HB |
5196 | |
5197 | return r; | |
5198 | } | |
5199 | ||
8b006791 ZX |
5200 | /* |
5201 | * Translate a guest virtual address to a guest physical address. | |
5202 | */ | |
5203 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
5204 | struct kvm_translation *tr) | |
5205 | { | |
5206 | unsigned long vaddr = tr->linear_address; | |
5207 | gpa_t gpa; | |
f656ce01 | 5208 | int idx; |
8b006791 | 5209 | |
f656ce01 | 5210 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1871c602 | 5211 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); |
f656ce01 | 5212 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 ZX |
5213 | tr->physical_address = gpa; |
5214 | tr->valid = gpa != UNMAPPED_GVA; | |
5215 | tr->writeable = 1; | |
5216 | tr->usermode = 0; | |
8b006791 ZX |
5217 | |
5218 | return 0; | |
5219 | } | |
5220 | ||
d0752060 HB |
5221 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
5222 | { | |
98918833 SY |
5223 | struct i387_fxsave_struct *fxsave = |
5224 | &vcpu->arch.guest_fpu.state->fxsave; | |
d0752060 | 5225 | |
d0752060 HB |
5226 | memcpy(fpu->fpr, fxsave->st_space, 128); |
5227 | fpu->fcw = fxsave->cwd; | |
5228 | fpu->fsw = fxsave->swd; | |
5229 | fpu->ftwx = fxsave->twd; | |
5230 | fpu->last_opcode = fxsave->fop; | |
5231 | fpu->last_ip = fxsave->rip; | |
5232 | fpu->last_dp = fxsave->rdp; | |
5233 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); | |
5234 | ||
d0752060 HB |
5235 | return 0; |
5236 | } | |
5237 | ||
5238 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
5239 | { | |
98918833 SY |
5240 | struct i387_fxsave_struct *fxsave = |
5241 | &vcpu->arch.guest_fpu.state->fxsave; | |
d0752060 | 5242 | |
d0752060 HB |
5243 | memcpy(fxsave->st_space, fpu->fpr, 128); |
5244 | fxsave->cwd = fpu->fcw; | |
5245 | fxsave->swd = fpu->fsw; | |
5246 | fxsave->twd = fpu->ftwx; | |
5247 | fxsave->fop = fpu->last_opcode; | |
5248 | fxsave->rip = fpu->last_ip; | |
5249 | fxsave->rdp = fpu->last_dp; | |
5250 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); | |
5251 | ||
d0752060 HB |
5252 | return 0; |
5253 | } | |
5254 | ||
10ab25cd | 5255 | int fx_init(struct kvm_vcpu *vcpu) |
d0752060 | 5256 | { |
10ab25cd JK |
5257 | int err; |
5258 | ||
5259 | err = fpu_alloc(&vcpu->arch.guest_fpu); | |
5260 | if (err) | |
5261 | return err; | |
5262 | ||
98918833 | 5263 | fpu_finit(&vcpu->arch.guest_fpu); |
d0752060 | 5264 | |
2acf923e DC |
5265 | /* |
5266 | * Ensure guest xcr0 is valid for loading | |
5267 | */ | |
5268 | vcpu->arch.xcr0 = XSTATE_FP; | |
5269 | ||
ad312c7c | 5270 | vcpu->arch.cr0 |= X86_CR0_ET; |
10ab25cd JK |
5271 | |
5272 | return 0; | |
d0752060 HB |
5273 | } |
5274 | EXPORT_SYMBOL_GPL(fx_init); | |
5275 | ||
98918833 SY |
5276 | static void fx_free(struct kvm_vcpu *vcpu) |
5277 | { | |
5278 | fpu_free(&vcpu->arch.guest_fpu); | |
5279 | } | |
5280 | ||
d0752060 HB |
5281 | void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) |
5282 | { | |
2608d7a1 | 5283 | if (vcpu->guest_fpu_loaded) |
d0752060 HB |
5284 | return; |
5285 | ||
2acf923e DC |
5286 | /* |
5287 | * Restore all possible states in the guest, | |
5288 | * and assume host would use all available bits. | |
5289 | * Guest xcr0 would be loaded later. | |
5290 | */ | |
5291 | kvm_put_guest_xcr0(vcpu); | |
d0752060 | 5292 | vcpu->guest_fpu_loaded = 1; |
7cf30855 | 5293 | unlazy_fpu(current); |
98918833 | 5294 | fpu_restore_checking(&vcpu->arch.guest_fpu); |
0c04851c | 5295 | trace_kvm_fpu(1); |
d0752060 | 5296 | } |
d0752060 HB |
5297 | |
5298 | void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
5299 | { | |
2acf923e DC |
5300 | kvm_put_guest_xcr0(vcpu); |
5301 | ||
d0752060 HB |
5302 | if (!vcpu->guest_fpu_loaded) |
5303 | return; | |
5304 | ||
5305 | vcpu->guest_fpu_loaded = 0; | |
98918833 | 5306 | fpu_save_init(&vcpu->arch.guest_fpu); |
f096ed85 | 5307 | ++vcpu->stat.fpu_reload; |
a8eeb04a | 5308 | kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu); |
0c04851c | 5309 | trace_kvm_fpu(0); |
d0752060 | 5310 | } |
e9b11c17 ZX |
5311 | |
5312 | void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) | |
5313 | { | |
7f1ea208 JR |
5314 | if (vcpu->arch.time_page) { |
5315 | kvm_release_page_dirty(vcpu->arch.time_page); | |
5316 | vcpu->arch.time_page = NULL; | |
5317 | } | |
5318 | ||
f5f48ee1 | 5319 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); |
98918833 | 5320 | fx_free(vcpu); |
e9b11c17 ZX |
5321 | kvm_x86_ops->vcpu_free(vcpu); |
5322 | } | |
5323 | ||
5324 | struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, | |
5325 | unsigned int id) | |
5326 | { | |
26e5215f AK |
5327 | return kvm_x86_ops->vcpu_create(kvm, id); |
5328 | } | |
e9b11c17 | 5329 | |
26e5215f AK |
5330 | int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) |
5331 | { | |
5332 | int r; | |
e9b11c17 | 5333 | |
0bed3b56 | 5334 | vcpu->arch.mtrr_state.have_fixed = 1; |
e9b11c17 ZX |
5335 | vcpu_load(vcpu); |
5336 | r = kvm_arch_vcpu_reset(vcpu); | |
5337 | if (r == 0) | |
5338 | r = kvm_mmu_setup(vcpu); | |
5339 | vcpu_put(vcpu); | |
5340 | if (r < 0) | |
5341 | goto free_vcpu; | |
5342 | ||
26e5215f | 5343 | return 0; |
e9b11c17 ZX |
5344 | free_vcpu: |
5345 | kvm_x86_ops->vcpu_free(vcpu); | |
26e5215f | 5346 | return r; |
e9b11c17 ZX |
5347 | } |
5348 | ||
d40ccc62 | 5349 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 ZX |
5350 | { |
5351 | vcpu_load(vcpu); | |
5352 | kvm_mmu_unload(vcpu); | |
5353 | vcpu_put(vcpu); | |
5354 | ||
98918833 | 5355 | fx_free(vcpu); |
e9b11c17 ZX |
5356 | kvm_x86_ops->vcpu_free(vcpu); |
5357 | } | |
5358 | ||
5359 | int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu) | |
5360 | { | |
448fa4a9 JK |
5361 | vcpu->arch.nmi_pending = false; |
5362 | vcpu->arch.nmi_injected = false; | |
5363 | ||
42dbaa5a JK |
5364 | vcpu->arch.switch_db_regs = 0; |
5365 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); | |
5366 | vcpu->arch.dr6 = DR6_FIXED_1; | |
5367 | vcpu->arch.dr7 = DR7_FIXED_1; | |
5368 | ||
e9b11c17 ZX |
5369 | return kvm_x86_ops->vcpu_reset(vcpu); |
5370 | } | |
5371 | ||
10474ae8 | 5372 | int kvm_arch_hardware_enable(void *garbage) |
e9b11c17 | 5373 | { |
0cca7907 ZA |
5374 | /* |
5375 | * Since this may be called from a hotplug notifcation, | |
5376 | * we can't get the CPU frequency directly. | |
5377 | */ | |
5378 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { | |
5379 | int cpu = raw_smp_processor_id(); | |
5380 | per_cpu(cpu_tsc_khz, cpu) = 0; | |
5381 | } | |
18863bdd AK |
5382 | |
5383 | kvm_shared_msr_cpu_online(); | |
5384 | ||
10474ae8 | 5385 | return kvm_x86_ops->hardware_enable(garbage); |
e9b11c17 ZX |
5386 | } |
5387 | ||
5388 | void kvm_arch_hardware_disable(void *garbage) | |
5389 | { | |
5390 | kvm_x86_ops->hardware_disable(garbage); | |
3548bab5 | 5391 | drop_user_return_notifiers(garbage); |
e9b11c17 ZX |
5392 | } |
5393 | ||
5394 | int kvm_arch_hardware_setup(void) | |
5395 | { | |
5396 | return kvm_x86_ops->hardware_setup(); | |
5397 | } | |
5398 | ||
5399 | void kvm_arch_hardware_unsetup(void) | |
5400 | { | |
5401 | kvm_x86_ops->hardware_unsetup(); | |
5402 | } | |
5403 | ||
5404 | void kvm_arch_check_processor_compat(void *rtn) | |
5405 | { | |
5406 | kvm_x86_ops->check_processor_compatibility(rtn); | |
5407 | } | |
5408 | ||
5409 | int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) | |
5410 | { | |
5411 | struct page *page; | |
5412 | struct kvm *kvm; | |
5413 | int r; | |
5414 | ||
5415 | BUG_ON(vcpu->kvm == NULL); | |
5416 | kvm = vcpu->kvm; | |
5417 | ||
ad312c7c | 5418 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
c5af89b6 | 5419 | if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu)) |
a4535290 | 5420 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
e9b11c17 | 5421 | else |
a4535290 | 5422 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; |
e9b11c17 ZX |
5423 | |
5424 | page = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
5425 | if (!page) { | |
5426 | r = -ENOMEM; | |
5427 | goto fail; | |
5428 | } | |
ad312c7c | 5429 | vcpu->arch.pio_data = page_address(page); |
e9b11c17 ZX |
5430 | |
5431 | r = kvm_mmu_create(vcpu); | |
5432 | if (r < 0) | |
5433 | goto fail_free_pio_data; | |
5434 | ||
5435 | if (irqchip_in_kernel(kvm)) { | |
5436 | r = kvm_create_lapic(vcpu); | |
5437 | if (r < 0) | |
5438 | goto fail_mmu_destroy; | |
5439 | } | |
5440 | ||
890ca9ae HY |
5441 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, |
5442 | GFP_KERNEL); | |
5443 | if (!vcpu->arch.mce_banks) { | |
5444 | r = -ENOMEM; | |
443c39bc | 5445 | goto fail_free_lapic; |
890ca9ae HY |
5446 | } |
5447 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
5448 | ||
f5f48ee1 SY |
5449 | if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) |
5450 | goto fail_free_mce_banks; | |
5451 | ||
e9b11c17 | 5452 | return 0; |
f5f48ee1 SY |
5453 | fail_free_mce_banks: |
5454 | kfree(vcpu->arch.mce_banks); | |
443c39bc WY |
5455 | fail_free_lapic: |
5456 | kvm_free_lapic(vcpu); | |
e9b11c17 ZX |
5457 | fail_mmu_destroy: |
5458 | kvm_mmu_destroy(vcpu); | |
5459 | fail_free_pio_data: | |
ad312c7c | 5460 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 ZX |
5461 | fail: |
5462 | return r; | |
5463 | } | |
5464 | ||
5465 | void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) | |
5466 | { | |
f656ce01 MT |
5467 | int idx; |
5468 | ||
36cb93fd | 5469 | kfree(vcpu->arch.mce_banks); |
e9b11c17 | 5470 | kvm_free_lapic(vcpu); |
f656ce01 | 5471 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
e9b11c17 | 5472 | kvm_mmu_destroy(vcpu); |
f656ce01 | 5473 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
ad312c7c | 5474 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 | 5475 | } |
d19a9cd2 ZX |
5476 | |
5477 | struct kvm *kvm_arch_create_vm(void) | |
5478 | { | |
5479 | struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL); | |
5480 | ||
5481 | if (!kvm) | |
5482 | return ERR_PTR(-ENOMEM); | |
5483 | ||
f05e70ac | 5484 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
4d5c5d0f | 5485 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
d19a9cd2 | 5486 | |
5550af4d SY |
5487 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
5488 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
5489 | ||
53f658b3 MT |
5490 | rdtscll(kvm->arch.vm_init_tsc); |
5491 | ||
d19a9cd2 ZX |
5492 | return kvm; |
5493 | } | |
5494 | ||
5495 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) | |
5496 | { | |
5497 | vcpu_load(vcpu); | |
5498 | kvm_mmu_unload(vcpu); | |
5499 | vcpu_put(vcpu); | |
5500 | } | |
5501 | ||
5502 | static void kvm_free_vcpus(struct kvm *kvm) | |
5503 | { | |
5504 | unsigned int i; | |
988a2cae | 5505 | struct kvm_vcpu *vcpu; |
d19a9cd2 ZX |
5506 | |
5507 | /* | |
5508 | * Unpin any mmu pages first. | |
5509 | */ | |
988a2cae GN |
5510 | kvm_for_each_vcpu(i, vcpu, kvm) |
5511 | kvm_unload_vcpu_mmu(vcpu); | |
5512 | kvm_for_each_vcpu(i, vcpu, kvm) | |
5513 | kvm_arch_vcpu_free(vcpu); | |
5514 | ||
5515 | mutex_lock(&kvm->lock); | |
5516 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
5517 | kvm->vcpus[i] = NULL; | |
d19a9cd2 | 5518 | |
988a2cae GN |
5519 | atomic_set(&kvm->online_vcpus, 0); |
5520 | mutex_unlock(&kvm->lock); | |
d19a9cd2 ZX |
5521 | } |
5522 | ||
ad8ba2cd SY |
5523 | void kvm_arch_sync_events(struct kvm *kvm) |
5524 | { | |
ba4cef31 | 5525 | kvm_free_all_assigned_devices(kvm); |
aea924f6 | 5526 | kvm_free_pit(kvm); |
ad8ba2cd SY |
5527 | } |
5528 | ||
d19a9cd2 ZX |
5529 | void kvm_arch_destroy_vm(struct kvm *kvm) |
5530 | { | |
6eb55818 | 5531 | kvm_iommu_unmap_guest(kvm); |
d7deeeb0 ZX |
5532 | kfree(kvm->arch.vpic); |
5533 | kfree(kvm->arch.vioapic); | |
d19a9cd2 ZX |
5534 | kvm_free_vcpus(kvm); |
5535 | kvm_free_physmem(kvm); | |
3d45830c AK |
5536 | if (kvm->arch.apic_access_page) |
5537 | put_page(kvm->arch.apic_access_page); | |
b7ebfb05 SY |
5538 | if (kvm->arch.ept_identity_pagetable) |
5539 | put_page(kvm->arch.ept_identity_pagetable); | |
64749204 | 5540 | cleanup_srcu_struct(&kvm->srcu); |
d19a9cd2 ZX |
5541 | kfree(kvm); |
5542 | } | |
0de10343 | 5543 | |
f7784b8e MT |
5544 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
5545 | struct kvm_memory_slot *memslot, | |
0de10343 | 5546 | struct kvm_memory_slot old, |
f7784b8e | 5547 | struct kvm_userspace_memory_region *mem, |
0de10343 ZX |
5548 | int user_alloc) |
5549 | { | |
f7784b8e | 5550 | int npages = memslot->npages; |
7ac77099 AK |
5551 | int map_flags = MAP_PRIVATE | MAP_ANONYMOUS; |
5552 | ||
5553 | /* Prevent internal slot pages from being moved by fork()/COW. */ | |
5554 | if (memslot->id >= KVM_MEMORY_SLOTS) | |
5555 | map_flags = MAP_SHARED | MAP_ANONYMOUS; | |
0de10343 ZX |
5556 | |
5557 | /*To keep backward compatibility with older userspace, | |
5558 | *x86 needs to hanlde !user_alloc case. | |
5559 | */ | |
5560 | if (!user_alloc) { | |
5561 | if (npages && !old.rmap) { | |
604b38ac AA |
5562 | unsigned long userspace_addr; |
5563 | ||
72dc67a6 | 5564 | down_write(¤t->mm->mmap_sem); |
604b38ac AA |
5565 | userspace_addr = do_mmap(NULL, 0, |
5566 | npages * PAGE_SIZE, | |
5567 | PROT_READ | PROT_WRITE, | |
7ac77099 | 5568 | map_flags, |
604b38ac | 5569 | 0); |
72dc67a6 | 5570 | up_write(¤t->mm->mmap_sem); |
0de10343 | 5571 | |
604b38ac AA |
5572 | if (IS_ERR((void *)userspace_addr)) |
5573 | return PTR_ERR((void *)userspace_addr); | |
5574 | ||
604b38ac | 5575 | memslot->userspace_addr = userspace_addr; |
0de10343 ZX |
5576 | } |
5577 | } | |
5578 | ||
f7784b8e MT |
5579 | |
5580 | return 0; | |
5581 | } | |
5582 | ||
5583 | void kvm_arch_commit_memory_region(struct kvm *kvm, | |
5584 | struct kvm_userspace_memory_region *mem, | |
5585 | struct kvm_memory_slot old, | |
5586 | int user_alloc) | |
5587 | { | |
5588 | ||
5589 | int npages = mem->memory_size >> PAGE_SHIFT; | |
5590 | ||
5591 | if (!user_alloc && !old.user_alloc && old.rmap && !npages) { | |
5592 | int ret; | |
5593 | ||
5594 | down_write(¤t->mm->mmap_sem); | |
5595 | ret = do_munmap(current->mm, old.userspace_addr, | |
5596 | old.npages * PAGE_SIZE); | |
5597 | up_write(¤t->mm->mmap_sem); | |
5598 | if (ret < 0) | |
5599 | printk(KERN_WARNING | |
5600 | "kvm_vm_ioctl_set_memory_region: " | |
5601 | "failed to munmap memory\n"); | |
5602 | } | |
5603 | ||
7c8a83b7 | 5604 | spin_lock(&kvm->mmu_lock); |
f05e70ac | 5605 | if (!kvm->arch.n_requested_mmu_pages) { |
0de10343 ZX |
5606 | unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); |
5607 | kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); | |
5608 | } | |
5609 | ||
5610 | kvm_mmu_slot_remove_write_access(kvm, mem->slot); | |
7c8a83b7 | 5611 | spin_unlock(&kvm->mmu_lock); |
0de10343 | 5612 | } |
1d737c8a | 5613 | |
34d4cb8f MT |
5614 | void kvm_arch_flush_shadow(struct kvm *kvm) |
5615 | { | |
5616 | kvm_mmu_zap_all(kvm); | |
8986ecc0 | 5617 | kvm_reload_remote_mmus(kvm); |
34d4cb8f MT |
5618 | } |
5619 | ||
1d737c8a ZX |
5620 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
5621 | { | |
a4535290 | 5622 | return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE |
a1b37100 GN |
5623 | || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED |
5624 | || vcpu->arch.nmi_pending || | |
5625 | (kvm_arch_interrupt_allowed(vcpu) && | |
5626 | kvm_cpu_has_interrupt(vcpu)); | |
1d737c8a | 5627 | } |
5736199a | 5628 | |
5736199a ZX |
5629 | void kvm_vcpu_kick(struct kvm_vcpu *vcpu) |
5630 | { | |
32f88400 MT |
5631 | int me; |
5632 | int cpu = vcpu->cpu; | |
5736199a ZX |
5633 | |
5634 | if (waitqueue_active(&vcpu->wq)) { | |
5635 | wake_up_interruptible(&vcpu->wq); | |
5636 | ++vcpu->stat.halt_wakeup; | |
5637 | } | |
32f88400 MT |
5638 | |
5639 | me = get_cpu(); | |
5640 | if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu)) | |
d94e1dc9 | 5641 | if (atomic_xchg(&vcpu->guest_mode, 0)) |
32f88400 | 5642 | smp_send_reschedule(cpu); |
e9571ed5 | 5643 | put_cpu(); |
5736199a | 5644 | } |
78646121 GN |
5645 | |
5646 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
5647 | { | |
5648 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
5649 | } | |
229456fc | 5650 | |
f92653ee JK |
5651 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) |
5652 | { | |
5653 | unsigned long current_rip = kvm_rip_read(vcpu) + | |
5654 | get_segment_base(vcpu, VCPU_SREG_CS); | |
5655 | ||
5656 | return current_rip == linear_rip; | |
5657 | } | |
5658 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
5659 | ||
94fe45da JK |
5660 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
5661 | { | |
5662 | unsigned long rflags; | |
5663 | ||
5664 | rflags = kvm_x86_ops->get_rflags(vcpu); | |
5665 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
c310bac5 | 5666 | rflags &= ~X86_EFLAGS_TF; |
94fe45da JK |
5667 | return rflags; |
5668 | } | |
5669 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
5670 | ||
5671 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
5672 | { | |
5673 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
f92653ee | 5674 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) |
c310bac5 | 5675 | rflags |= X86_EFLAGS_TF; |
94fe45da JK |
5676 | kvm_x86_ops->set_rflags(vcpu, rflags); |
5677 | } | |
5678 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
5679 | ||
229456fc MT |
5680 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
5681 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); | |
5682 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
5683 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
5684 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
0ac406de | 5685 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); |
d8cabddf | 5686 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 5687 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 5688 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
ec1ff790 | 5689 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 5690 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |
2e554e8d | 5691 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); |