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KVM: MMU: fix bogus alloc_mmu_pages assignment
[mirror_ubuntu-zesty-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
aec51dc4
AK		 40#include <trace/events/kvm.h>
41#undef TRACE_INCLUDE_FILE
229456fc
MT		 42#define CREATE_TRACE_POINTS
43#include "trace.h"
043405e1
CO		 44
45#include <asm/uaccess.h>
d825ed0a 46#include <asm/msr.h>
a5f61300 47#include <asm/desc.h>
0bed3b56 48#include <asm/mtrr.h>
890ca9ae 49#include <asm/mce.h>
043405e1 50
313a3dc7 51#define MAX_IO_MSRS 256
a03490ed
CO		 52#define CR0_RESERVED_BITS \
53 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
54 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
55 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
56#define CR4_RESERVED_BITS \
57 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
58 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
59 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
60 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
61
62#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 63
64#define KVM_MAX_MCE_BANKS 32
65#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
66
50a37eb4
JR		 67/* EFER defaults:
68 * - enable syscall per default because its emulated by KVM
69 * - enable LME and LMA per default on 64 bit KVM
70 */
71#ifdef CONFIG_X86_64
72static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
73#else
74static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
75#endif
313a3dc7 76
ba1389b7
AK		 77#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
78#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 79
674eea0f
AK		 80static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
81 struct kvm_cpuid_entry2 __user *entries);
82
97896d04 83struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 84EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 85
ed85c068
AP		 86int ignore_msrs = 0;
87module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
88
417bc304 89struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 90 { "pf_fixed", VCPU_STAT(pf_fixed) },
91 { "pf_guest", VCPU_STAT(pf_guest) },
92 { "tlb_flush", VCPU_STAT(tlb_flush) },
93 { "invlpg", VCPU_STAT(invlpg) },
94 { "exits", VCPU_STAT(exits) },
95 { "io_exits", VCPU_STAT(io_exits) },
96 { "mmio_exits", VCPU_STAT(mmio_exits) },
97 { "signal_exits", VCPU_STAT(signal_exits) },
98 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 99 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 100 { "halt_exits", VCPU_STAT(halt_exits) },
101 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 102 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 103 { "request_irq", VCPU_STAT(request_irq_exits) },
104 { "irq_exits", VCPU_STAT(irq_exits) },
105 { "host_state_reload", VCPU_STAT(host_state_reload) },
106 { "efer_reload", VCPU_STAT(efer_reload) },
107 { "fpu_reload", VCPU_STAT(fpu_reload) },
108 { "insn_emulation", VCPU_STAT(insn_emulation) },
109 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 110 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 111 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 112 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
113 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
114 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
115 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
116 { "mmu_flooded", VM_STAT(mmu_flooded) },
117 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 118 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 119 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 120 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 121 { "largepages", VM_STAT(lpages) },
417bc304
HB		 122 { NULL }
123};
124
5fb76f9b
CO		 125unsigned long segment_base(u16 selector)
126{
127 struct descriptor_table gdt;
a5f61300 128 struct desc_struct *d;
5fb76f9b
CO		 129 unsigned long table_base;
130 unsigned long v;
131
132 if (selector == 0)
133 return 0;
134
b792c344 135 kvm_get_gdt(&gdt);
5fb76f9b
CO		 136 table_base = gdt.base;
137
138 if (selector & 4) { /* from ldt */
b792c344 139 u16 ldt_selector = kvm_read_ldt();
5fb76f9b 140
5fb76f9b
CO		 141 table_base = segment_base(ldt_selector);
142 }
a5f61300 143 d = (struct desc_struct *)(table_base + (selector & ~7));
46a359e7 144 v = get_desc_base(d);
5fb76f9b 145#ifdef CONFIG_X86_64
a5f61300
AK		 146 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
147 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 148#endif
149 return v;
150}
151EXPORT_SYMBOL_GPL(segment_base);
152
6866b83e
CO		 153u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
154{
155 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 156 return vcpu->arch.apic_base;
6866b83e 157 else
ad312c7c 158 return vcpu->arch.apic_base;
6866b83e
CO		 159}
160EXPORT_SYMBOL_GPL(kvm_get_apic_base);
161
162void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
163{
164 /* TODO: reserve bits check */
165 if (irqchip_in_kernel(vcpu->kvm))
166 kvm_lapic_set_base(vcpu, data);
167 else
ad312c7c 168 vcpu->arch.apic_base = data;
6866b83e
CO		 169}
170EXPORT_SYMBOL_GPL(kvm_set_apic_base);
171
298101da
AK		 172void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
173{
ad312c7c
ZX		 174 WARN_ON(vcpu->arch.exception.pending);
175 vcpu->arch.exception.pending = true;
176 vcpu->arch.exception.has_error_code = false;
177 vcpu->arch.exception.nr = nr;
298101da
AK		 178}
179EXPORT_SYMBOL_GPL(kvm_queue_exception);
180
c3c91fee
AK		 181void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
182 u32 error_code)
183{
184 ++vcpu->stat.pf_guest;
d8017474 185
71c4dfaf 186 if (vcpu->arch.exception.pending) {
6edf14d8
GN		 187 switch(vcpu->arch.exception.nr) {
188 case DF_VECTOR:
71c4dfaf
JR		 189 /* triple fault -> shutdown */
190 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
6edf14d8
GN		 191 return;
192 case PF_VECTOR:
193 vcpu->arch.exception.nr = DF_VECTOR;
194 vcpu->arch.exception.error_code = 0;
195 return;
196 default:
197 /* replace previous exception with a new one in a hope
198 that instruction re-execution will regenerate lost
199 exception */
200 vcpu->arch.exception.pending = false;
201 break;
71c4dfaf 202 }
c3c91fee 203 }
ad312c7c 204 vcpu->arch.cr2 = addr;
c3c91fee
AK		 205 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
206}
207
3419ffc8
SY		 208void kvm_inject_nmi(struct kvm_vcpu *vcpu)
209{
210 vcpu->arch.nmi_pending = 1;
211}
212EXPORT_SYMBOL_GPL(kvm_inject_nmi);
213
298101da
AK		 214void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
215{
ad312c7c
ZX		 216 WARN_ON(vcpu->arch.exception.pending);
217 vcpu->arch.exception.pending = true;
218 vcpu->arch.exception.has_error_code = true;
219 vcpu->arch.exception.nr = nr;
220 vcpu->arch.exception.error_code = error_code;
298101da
AK		 221}
222EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
223
a03490ed
CO		 224/*
225 * Load the pae pdptrs. Return true is they are all valid.
226 */
227int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
228{
229 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
230 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
231 int i;
232 int ret;
ad312c7c 233 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 234
a03490ed
CO		 235 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
236 offset * sizeof(u64), sizeof(pdpte));
237 if (ret < 0) {
238 ret = 0;
239 goto out;
240 }
241 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 242 if (is_present_gpte(pdpte[i]) &&
20c466b5 243 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 244 ret = 0;
245 goto out;
246 }
247 }
248 ret = 1;
249
ad312c7c 250 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 251 __set_bit(VCPU_EXREG_PDPTR,
252 (unsigned long *)&vcpu->arch.regs_avail);
253 __set_bit(VCPU_EXREG_PDPTR,
254 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 255out:
a03490ed
CO		 256
257 return ret;
258}
cc4b6871 259EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 260
d835dfec
AK		 261static bool pdptrs_changed(struct kvm_vcpu *vcpu)
262{
ad312c7c 263 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 264 bool changed = true;
265 int r;
266
267 if (is_long_mode(vcpu) || !is_pae(vcpu))
268 return false;
269
6de4f3ad
AK		 270 if (!test_bit(VCPU_EXREG_PDPTR,
271 (unsigned long *)&vcpu->arch.regs_avail))
272 return true;
273
ad312c7c 274 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 275 if (r < 0)
276 goto out;
ad312c7c 277 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 278out:
d835dfec
AK		 279
280 return changed;
281}
282
2d3ad1f4 283void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 284{
285 if (cr0 & CR0_RESERVED_BITS) {
286 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 287 cr0, vcpu->arch.cr0);
c1a5d4f9 288 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 289 return;
290 }
291
292 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
293 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 294 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 295 return;
296 }
297
298 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
299 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
300 "and a clear PE flag\n");
c1a5d4f9 301 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 302 return;
303 }
304
305 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
306#ifdef CONFIG_X86_64
ad312c7c 307 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 308 int cs_db, cs_l;
309
310 if (!is_pae(vcpu)) {
311 printk(KERN_DEBUG "set_cr0: #GP, start paging "
312 "in long mode while PAE is disabled\n");
c1a5d4f9 313 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 314 return;
315 }
316 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
317 if (cs_l) {
318 printk(KERN_DEBUG "set_cr0: #GP, start paging "
319 "in long mode while CS.L == 1\n");
c1a5d4f9 320 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 321 return;
322
323 }
324 } else
325#endif
ad312c7c 326 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 327 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
328 "reserved bits\n");
c1a5d4f9 329 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 330 return;
331 }
332
333 }
334
335 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 336 vcpu->arch.cr0 = cr0;
a03490ed 337
a03490ed 338 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 339 return;
340}
2d3ad1f4 341EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 342
2d3ad1f4 343void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 344{
2d3ad1f4 345 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
a03490ed 346}
2d3ad1f4 347EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 348
2d3ad1f4 349void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 350{
a2edf57f
AK		 351 unsigned long old_cr4 = vcpu->arch.cr4;
352 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
353
a03490ed
CO		 354 if (cr4 & CR4_RESERVED_BITS) {
355 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 356 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 357 return;
358 }
359
360 if (is_long_mode(vcpu)) {
361 if (!(cr4 & X86_CR4_PAE)) {
362 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
363 "in long mode\n");
c1a5d4f9 364 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 365 return;
366 }
a2edf57f
AK		 367 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
368 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 369 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 370 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 371 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 372 return;
373 }
374
375 if (cr4 & X86_CR4_VMXE) {
376 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 377 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 378 return;
379 }
380 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 381 vcpu->arch.cr4 = cr4;
5a41accd 382 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
a03490ed 383 kvm_mmu_reset_context(vcpu);
a03490ed 384}
2d3ad1f4 385EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 386
2d3ad1f4 387void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 388{
ad312c7c 389 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 390 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 391 kvm_mmu_flush_tlb(vcpu);
392 return;
393 }
394
a03490ed
CO		 395 if (is_long_mode(vcpu)) {
396 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
397 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 398 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 399 return;
400 }
401 } else {
402 if (is_pae(vcpu)) {
403 if (cr3 & CR3_PAE_RESERVED_BITS) {
404 printk(KERN_DEBUG
405 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 406 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 407 return;
408 }
409 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
410 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
411 "reserved bits\n");
c1a5d4f9 412 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 413 return;
414 }
415 }
416 /*
417 * We don't check reserved bits in nonpae mode, because
418 * this isn't enforced, and VMware depends on this.
419 */
420 }
421
a03490ed
CO		 422 /*
423 * Does the new cr3 value map to physical memory? (Note, we
424 * catch an invalid cr3 even in real-mode, because it would
425 * cause trouble later on when we turn on paging anyway.)
426 *
427 * A real CPU would silently accept an invalid cr3 and would
428 * attempt to use it - with largely undefined (and often hard
429 * to debug) behavior on the guest side.
430 */
431 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 432 kvm_inject_gp(vcpu, 0);
a03490ed 433 else {
ad312c7c
ZX		 434 vcpu->arch.cr3 = cr3;
435 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 436 }
a03490ed 437}
2d3ad1f4 438EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 439
2d3ad1f4 440void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 441{
442 if (cr8 & CR8_RESERVED_BITS) {
443 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 444 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 445 return;
446 }
447 if (irqchip_in_kernel(vcpu->kvm))
448 kvm_lapic_set_tpr(vcpu, cr8);
449 else
ad312c7c 450 vcpu->arch.cr8 = cr8;
a03490ed 451}
2d3ad1f4 452EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 453
2d3ad1f4 454unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 455{
456 if (irqchip_in_kernel(vcpu->kvm))
457 return kvm_lapic_get_cr8(vcpu);
458 else
ad312c7c 459 return vcpu->arch.cr8;
a03490ed 460}
2d3ad1f4 461EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 462
d8017474
AG		 463static inline u32 bit(int bitno)
464{
465 return 1 << (bitno & 31);
466}
467
043405e1
CO		 468/*
469 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
470 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
471 *
472 * This list is modified at module load time to reflect the
473 * capabilities of the host cpu.
474 */
475static u32 msrs_to_save[] = {
476 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
477 MSR_K6_STAR,
478#ifdef CONFIG_X86_64
479 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
480#endif
af24a4e4 481 MSR_IA32_TSC, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
b286d5d8 482 MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 483};
484
485static unsigned num_msrs_to_save;
486
487static u32 emulated_msrs[] = {
488 MSR_IA32_MISC_ENABLE,
489};
490
15c4a640
CO		 491static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
492{
f2b4b7dd 493 if (efer & efer_reserved_bits) {
15c4a640
CO		 494 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
495 efer);
c1a5d4f9 496 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 497 return;
498 }
499
500 if (is_paging(vcpu)
ad312c7c 501 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 502 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 503 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 504 return;
505 }
506
1b2fd70c
AG		 507 if (efer & EFER_FFXSR) {
508 struct kvm_cpuid_entry2 *feat;
509
510 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
511 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
512 printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
513 kvm_inject_gp(vcpu, 0);
514 return;
515 }
516 }
517
d8017474
AG		 518 if (efer & EFER_SVME) {
519 struct kvm_cpuid_entry2 *feat;
520
521 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
522 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
523 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
524 kvm_inject_gp(vcpu, 0);
525 return;
526 }
527 }
528
15c4a640
CO		 529 kvm_x86_ops->set_efer(vcpu, efer);
530
531 efer &= ~EFER_LMA;
ad312c7c 532 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 533
ad312c7c 534 vcpu->arch.shadow_efer = efer;
9645bb56
AK		 535
536 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
537 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 538}
539
f2b4b7dd
JR		 540void kvm_enable_efer_bits(u64 mask)
541{
542 efer_reserved_bits &= ~mask;
543}
544EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
545
546
15c4a640
CO		 547/*
548 * Writes msr value into into the appropriate "register".
549 * Returns 0 on success, non-0 otherwise.
550 * Assumes vcpu_load() was already called.
551 */
552int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
553{
554 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
555}
556
313a3dc7
CO		 557/*
558 * Adapt set_msr() to msr_io()'s calling convention
559 */
560static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
561{
562 return kvm_set_msr(vcpu, index, *data);
563}
564
18068523
GOC		 565static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
566{
567 static int version;
50d0a0f9
GH		 568 struct pvclock_wall_clock wc;
569 struct timespec now, sys, boot;
18068523
GOC		 570
571 if (!wall_clock)
572 return;
573
574 version++;
575
18068523
GOC		 576 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
577
50d0a0f9
GH		 578 /*
579 * The guest calculates current wall clock time by adding
580 * system time (updated by kvm_write_guest_time below) to the
581 * wall clock specified here. guest system time equals host
582 * system time for us, thus we must fill in host boot time here.
583 */
584 now = current_kernel_time();
585 ktime_get_ts(&sys);
586 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
587
588 wc.sec = boot.tv_sec;
589 wc.nsec = boot.tv_nsec;
590 wc.version = version;
18068523
GOC		 591
592 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
593
594 version++;
595 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 596}
597
50d0a0f9
GH		 598static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
599{
600 uint32_t quotient, remainder;
601
602 /* Don't try to replace with do_div(), this one calculates
603 * "(dividend << 32) / divisor" */
604 __asm__ ( "divl %4"
605 : "=a" (quotient), "=d" (remainder)
606 : "0" (0), "1" (dividend), "r" (divisor) );
607 return quotient;
608}
609
610static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
611{
612 uint64_t nsecs = 1000000000LL;
613 int32_t shift = 0;
614 uint64_t tps64;
615 uint32_t tps32;
616
617 tps64 = tsc_khz * 1000LL;
618 while (tps64 > nsecs*2) {
619 tps64 >>= 1;
620 shift--;
621 }
622
623 tps32 = (uint32_t)tps64;
624 while (tps32 <= (uint32_t)nsecs) {
625 tps32 <<= 1;
626 shift++;
627 }
628
629 hv_clock->tsc_shift = shift;
630 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
631
632 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 633 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 634 hv_clock->tsc_to_system_mul);
635}
636
c8076604
GH		 637static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
638
18068523
GOC		 639static void kvm_write_guest_time(struct kvm_vcpu *v)
640{
641 struct timespec ts;
642 unsigned long flags;
643 struct kvm_vcpu_arch *vcpu = &v->arch;
644 void *shared_kaddr;
463656c0 645 unsigned long this_tsc_khz;
18068523
GOC		 646
647 if ((!vcpu->time_page))
648 return;
649
463656c0
AK		 650 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
651 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
652 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
653 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 654 }
463656c0 655 put_cpu_var(cpu_tsc_khz);
50d0a0f9 656
18068523
GOC		 657 /* Keep irq disabled to prevent changes to the clock */
658 local_irq_save(flags);
af24a4e4 659 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523
GOC		 660 ktime_get_ts(&ts);
661 local_irq_restore(flags);
662
663 /* With all the info we got, fill in the values */
664
665 vcpu->hv_clock.system_time = ts.tv_nsec +
666 (NSEC_PER_SEC * (u64)ts.tv_sec);
667 /*
668 * The interface expects us to write an even number signaling that the
669 * update is finished. Since the guest won't see the intermediate
50d0a0f9 670 * state, we just increase by 2 at the end.
18068523 671 */
50d0a0f9 672 vcpu->hv_clock.version += 2;
18068523
GOC		 673
674 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
675
676 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 677 sizeof(vcpu->hv_clock));
18068523
GOC		 678
679 kunmap_atomic(shared_kaddr, KM_USER0);
680
681 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
682}
683
c8076604
GH		 684static int kvm_request_guest_time_update(struct kvm_vcpu *v)
685{
686 struct kvm_vcpu_arch *vcpu = &v->arch;
687
688 if (!vcpu->time_page)
689 return 0;
690 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
691 return 1;
692}
693
9ba075a6
AK		 694static bool msr_mtrr_valid(unsigned msr)
695{
696 switch (msr) {
697 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
698 case MSR_MTRRfix64K_00000:
699 case MSR_MTRRfix16K_80000:
700 case MSR_MTRRfix16K_A0000:
701 case MSR_MTRRfix4K_C0000:
702 case MSR_MTRRfix4K_C8000:
703 case MSR_MTRRfix4K_D0000:
704 case MSR_MTRRfix4K_D8000:
705 case MSR_MTRRfix4K_E0000:
706 case MSR_MTRRfix4K_E8000:
707 case MSR_MTRRfix4K_F0000:
708 case MSR_MTRRfix4K_F8000:
709 case MSR_MTRRdefType:
710 case MSR_IA32_CR_PAT:
711 return true;
712 case 0x2f8:
713 return true;
714 }
715 return false;
716}
717
d6289b93
MT		 718static bool valid_pat_type(unsigned t)
719{
720 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
721}
722
723static bool valid_mtrr_type(unsigned t)
724{
725 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
726}
727
728static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
729{
730 int i;
731
732 if (!msr_mtrr_valid(msr))
733 return false;
734
735 if (msr == MSR_IA32_CR_PAT) {
736 for (i = 0; i < 8; i++)
737 if (!valid_pat_type((data >> (i * 8)) & 0xff))
738 return false;
739 return true;
740 } else if (msr == MSR_MTRRdefType) {
741 if (data & ~0xcff)
742 return false;
743 return valid_mtrr_type(data & 0xff);
744 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
745 for (i = 0; i < 8 ; i++)
746 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
747 return false;
748 return true;
749 }
750
751 /* variable MTRRs */
752 return valid_mtrr_type(data & 0xff);
753}
754
9ba075a6
AK		 755static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
756{
0bed3b56
SY		 757 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
758
d6289b93 759 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 760 return 1;
761
0bed3b56
SY		 762 if (msr == MSR_MTRRdefType) {
763 vcpu->arch.mtrr_state.def_type = data;
764 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
765 } else if (msr == MSR_MTRRfix64K_00000)
766 p[0] = data;
767 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
768 p[1 + msr - MSR_MTRRfix16K_80000] = data;
769 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
770 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
771 else if (msr == MSR_IA32_CR_PAT)
772 vcpu->arch.pat = data;
773 else { /* Variable MTRRs */
774 int idx, is_mtrr_mask;
775 u64 *pt;
776
777 idx = (msr - 0x200) / 2;
778 is_mtrr_mask = msr - 0x200 - 2 * idx;
779 if (!is_mtrr_mask)
780 pt =
781 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
782 else
783 pt =
784 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
785 *pt = data;
786 }
787
788 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 789 return 0;
790}
15c4a640 791
890ca9ae 792static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 793{
890ca9ae
HY		 794 u64 mcg_cap = vcpu->arch.mcg_cap;
795 unsigned bank_num = mcg_cap & 0xff;
796
15c4a640 797 switch (msr) {
15c4a640 798 case MSR_IA32_MCG_STATUS:
890ca9ae 799 vcpu->arch.mcg_status = data;
15c4a640 800 break;
c7ac679c 801 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 802 if (!(mcg_cap & MCG_CTL_P))
803 return 1;
804 if (data != 0 && data != ~(u64)0)
805 return -1;
806 vcpu->arch.mcg_ctl = data;
807 break;
808 default:
809 if (msr >= MSR_IA32_MC0_CTL &&
810 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
811 u32 offset = msr - MSR_IA32_MC0_CTL;
812 /* only 0 or all 1s can be written to IA32_MCi_CTL */
813 if ((offset & 0x3) == 0 &&
814 data != 0 && data != ~(u64)0)
815 return -1;
816 vcpu->arch.mce_banks[offset] = data;
817 break;
818 }
819 return 1;
820 }
821 return 0;
822}
823
824int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
825{
826 switch (msr) {
827 case MSR_EFER:
828 set_efer(vcpu, data);
c7ac679c 829 break;
8f1589d9
AP		 830 case MSR_K7_HWCR:
831 data &= ~(u64)0x40; /* ignore flush filter disable */
832 if (data != 0) {
833 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
834 data);
835 return 1;
836 }
837 break;
f7c6d140
AP		 838 case MSR_FAM10H_MMIO_CONF_BASE:
839 if (data != 0) {
840 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
841 "0x%llx\n", data);
842 return 1;
843 }
844 break;
c323c0e5
AP		 845 case MSR_AMD64_NB_CFG:
846 break;
b5e2fec0
AG		 847 case MSR_IA32_DEBUGCTLMSR:
848 if (!data) {
849 /* We support the non-activated case already */
850 break;
851 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
852 /* Values other than LBR and BTF are vendor-specific,
853 thus reserved and should throw a #GP */
854 return 1;
855 }
856 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
857 __func__, data);
858 break;
15c4a640
CO		 859 case MSR_IA32_UCODE_REV:
860 case MSR_IA32_UCODE_WRITE:
61a6bd67 861 case MSR_VM_HSAVE_PA:
6098ca93 862 case MSR_AMD64_PATCH_LOADER:
15c4a640 863 break;
9ba075a6
AK		 864 case 0x200 ... 0x2ff:
865 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 866 case MSR_IA32_APICBASE:
867 kvm_set_apic_base(vcpu, data);
868 break;
0105d1a5
GN		 869 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
870 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 871 case MSR_IA32_MISC_ENABLE:
ad312c7c 872 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 873 break;
18068523
GOC		 874 case MSR_KVM_WALL_CLOCK:
875 vcpu->kvm->arch.wall_clock = data;
876 kvm_write_wall_clock(vcpu->kvm, data);
877 break;
878 case MSR_KVM_SYSTEM_TIME: {
879 if (vcpu->arch.time_page) {
880 kvm_release_page_dirty(vcpu->arch.time_page);
881 vcpu->arch.time_page = NULL;
882 }
883
884 vcpu->arch.time = data;
885
886 /* we verify if the enable bit is set... */
887 if (!(data & 1))
888 break;
889
890 /* ...but clean it before doing the actual write */
891 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
892
18068523
GOC		 893 vcpu->arch.time_page =
894 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 895
896 if (is_error_page(vcpu->arch.time_page)) {
897 kvm_release_page_clean(vcpu->arch.time_page);
898 vcpu->arch.time_page = NULL;
899 }
900
c8076604 901 kvm_request_guest_time_update(vcpu);
18068523
GOC		 902 break;
903 }
890ca9ae
HY		 904 case MSR_IA32_MCG_CTL:
905 case MSR_IA32_MCG_STATUS:
906 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
907 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 908
909 /* Performance counters are not protected by a CPUID bit,
910 * so we should check all of them in the generic path for the sake of
911 * cross vendor migration.
912 * Writing a zero into the event select MSRs disables them,
913 * which we perfectly emulate ;-). Any other value should be at least
914 * reported, some guests depend on them.
915 */
916 case MSR_P6_EVNTSEL0:
917 case MSR_P6_EVNTSEL1:
918 case MSR_K7_EVNTSEL0:
919 case MSR_K7_EVNTSEL1:
920 case MSR_K7_EVNTSEL2:
921 case MSR_K7_EVNTSEL3:
922 if (data != 0)
923 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
924 "0x%x data 0x%llx\n", msr, data);
925 break;
926 /* at least RHEL 4 unconditionally writes to the perfctr registers,
927 * so we ignore writes to make it happy.
928 */
929 case MSR_P6_PERFCTR0:
930 case MSR_P6_PERFCTR1:
931 case MSR_K7_PERFCTR0:
932 case MSR_K7_PERFCTR1:
933 case MSR_K7_PERFCTR2:
934 case MSR_K7_PERFCTR3:
935 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
936 "0x%x data 0x%llx\n", msr, data);
937 break;
15c4a640 938 default:
ed85c068
AP		 939 if (!ignore_msrs) {
940 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
941 msr, data);
942 return 1;
943 } else {
944 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
945 msr, data);
946 break;
947 }
15c4a640
CO		 948 }
949 return 0;
950}
951EXPORT_SYMBOL_GPL(kvm_set_msr_common);
952
953
954/*
955 * Reads an msr value (of 'msr_index') into 'pdata'.
956 * Returns 0 on success, non-0 otherwise.
957 * Assumes vcpu_load() was already called.
958 */
959int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
960{
961 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
962}
963
9ba075a6
AK		 964static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
965{
0bed3b56
SY		 966 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
967
9ba075a6
AK		 968 if (!msr_mtrr_valid(msr))
969 return 1;
970
0bed3b56
SY		 971 if (msr == MSR_MTRRdefType)
972 *pdata = vcpu->arch.mtrr_state.def_type +
973 (vcpu->arch.mtrr_state.enabled << 10);
974 else if (msr == MSR_MTRRfix64K_00000)
975 *pdata = p[0];
976 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
977 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
978 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
979 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
980 else if (msr == MSR_IA32_CR_PAT)
981 *pdata = vcpu->arch.pat;
982 else { /* Variable MTRRs */
983 int idx, is_mtrr_mask;
984 u64 *pt;
985
986 idx = (msr - 0x200) / 2;
987 is_mtrr_mask = msr - 0x200 - 2 * idx;
988 if (!is_mtrr_mask)
989 pt =
990 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
991 else
992 pt =
993 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
994 *pdata = *pt;
995 }
996
9ba075a6
AK		 997 return 0;
998}
999
890ca9ae 1000static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1001{
1002 u64 data;
890ca9ae
HY		 1003 u64 mcg_cap = vcpu->arch.mcg_cap;
1004 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1005
1006 switch (msr) {
15c4a640
CO		 1007 case MSR_IA32_P5_MC_ADDR:
1008 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1009 data = 0;
1010 break;
15c4a640 1011 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1012 data = vcpu->arch.mcg_cap;
1013 break;
c7ac679c 1014 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1015 if (!(mcg_cap & MCG_CTL_P))
1016 return 1;
1017 data = vcpu->arch.mcg_ctl;
1018 break;
1019 case MSR_IA32_MCG_STATUS:
1020 data = vcpu->arch.mcg_status;
1021 break;
1022 default:
1023 if (msr >= MSR_IA32_MC0_CTL &&
1024 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1025 u32 offset = msr - MSR_IA32_MC0_CTL;
1026 data = vcpu->arch.mce_banks[offset];
1027 break;
1028 }
1029 return 1;
1030 }
1031 *pdata = data;
1032 return 0;
1033}
1034
1035int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1036{
1037 u64 data;
1038
1039 switch (msr) {
890ca9ae 1040 case MSR_IA32_PLATFORM_ID:
15c4a640 1041 case MSR_IA32_UCODE_REV:
15c4a640 1042 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1043 case MSR_IA32_DEBUGCTLMSR:
1044 case MSR_IA32_LASTBRANCHFROMIP:
1045 case MSR_IA32_LASTBRANCHTOIP:
1046 case MSR_IA32_LASTINTFROMIP:
1047 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1048 case MSR_K8_SYSCFG:
1049 case MSR_K7_HWCR:
61a6bd67 1050 case MSR_VM_HSAVE_PA:
7fe29e0f
AS		 1051 case MSR_P6_EVNTSEL0:
1052 case MSR_P6_EVNTSEL1:
9e699624 1053 case MSR_K7_EVNTSEL0:
1fdbd48c 1054 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1055 case MSR_AMD64_NB_CFG:
f7c6d140 1056 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1057 data = 0;
1058 break;
9ba075a6
AK		 1059 case MSR_MTRRcap:
1060 data = 0x500 | KVM_NR_VAR_MTRR;
1061 break;
1062 case 0x200 ... 0x2ff:
1063 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1064 case 0xcd: /* fsb frequency */
1065 data = 3;
1066 break;
1067 case MSR_IA32_APICBASE:
1068 data = kvm_get_apic_base(vcpu);
1069 break;
0105d1a5
GN		 1070 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1071 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1072 break;
15c4a640 1073 case MSR_IA32_MISC_ENABLE:
ad312c7c 1074 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1075 break;
847f0ad8
AG		 1076 case MSR_IA32_PERF_STATUS:
1077 /* TSC increment by tick */
1078 data = 1000ULL;
1079 /* CPU multiplier */
1080 data |= (((uint64_t)4ULL) << 40);
1081 break;
15c4a640 1082 case MSR_EFER:
ad312c7c 1083 data = vcpu->arch.shadow_efer;
15c4a640 1084 break;
18068523
GOC		 1085 case MSR_KVM_WALL_CLOCK:
1086 data = vcpu->kvm->arch.wall_clock;
1087 break;
1088 case MSR_KVM_SYSTEM_TIME:
1089 data = vcpu->arch.time;
1090 break;
890ca9ae
HY		 1091 case MSR_IA32_P5_MC_ADDR:
1092 case MSR_IA32_P5_MC_TYPE:
1093 case MSR_IA32_MCG_CAP:
1094 case MSR_IA32_MCG_CTL:
1095 case MSR_IA32_MCG_STATUS:
1096 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1097 return get_msr_mce(vcpu, msr, pdata);
15c4a640 1098 default:
ed85c068
AP		 1099 if (!ignore_msrs) {
1100 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1101 return 1;
1102 } else {
1103 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1104 data = 0;
1105 }
1106 break;
15c4a640
CO		 1107 }
1108 *pdata = data;
1109 return 0;
1110}
1111EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1112
313a3dc7
CO		 1113/*
1114 * Read or write a bunch of msrs. All parameters are kernel addresses.
1115 *
1116 * @return number of msrs set successfully.
1117 */
1118static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1119 struct kvm_msr_entry *entries,
1120 int (*do_msr)(struct kvm_vcpu *vcpu,
1121 unsigned index, u64 *data))
1122{
1123 int i;
1124
1125 vcpu_load(vcpu);
1126
3200f405 1127 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1128 for (i = 0; i < msrs->nmsrs; ++i)
1129 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1130 break;
3200f405 1131 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1132
1133 vcpu_put(vcpu);
1134
1135 return i;
1136}
1137
1138/*
1139 * Read or write a bunch of msrs. Parameters are user addresses.
1140 *
1141 * @return number of msrs set successfully.
1142 */
1143static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1144 int (*do_msr)(struct kvm_vcpu *vcpu,
1145 unsigned index, u64 *data),
1146 int writeback)
1147{
1148 struct kvm_msrs msrs;
1149 struct kvm_msr_entry *entries;
1150 int r, n;
1151 unsigned size;
1152
1153 r = -EFAULT;
1154 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1155 goto out;
1156
1157 r = -E2BIG;
1158 if (msrs.nmsrs >= MAX_IO_MSRS)
1159 goto out;
1160
1161 r = -ENOMEM;
1162 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1163 entries = vmalloc(size);
1164 if (!entries)
1165 goto out;
1166
1167 r = -EFAULT;
1168 if (copy_from_user(entries, user_msrs->entries, size))
1169 goto out_free;
1170
1171 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1172 if (r < 0)
1173 goto out_free;
1174
1175 r = -EFAULT;
1176 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1177 goto out_free;
1178
1179 r = n;
1180
1181out_free:
1182 vfree(entries);
1183out:
1184 return r;
1185}
1186
018d00d2
ZX		 1187int kvm_dev_ioctl_check_extension(long ext)
1188{
1189 int r;
1190
1191 switch (ext) {
1192 case KVM_CAP_IRQCHIP:
1193 case KVM_CAP_HLT:
1194 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1195 case KVM_CAP_SET_TSS_ADDR:
07716717 1196 case KVM_CAP_EXT_CPUID:
c8076604 1197 case KVM_CAP_CLOCKSOURCE:
7837699f 1198 case KVM_CAP_PIT:
a28e4f5a 1199 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1200 case KVM_CAP_MP_STATE:
ed848624 1201 case KVM_CAP_SYNC_MMU:
52d939a0 1202 case KVM_CAP_REINJECT_CONTROL:
4925663a 1203 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1204 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1205 case KVM_CAP_IRQFD:
d34e6b17 1206 case KVM_CAP_IOEVENTFD:
c5ff41ce 1207 case KVM_CAP_PIT2:
e9f42757 1208 case KVM_CAP_PIT_STATE2:
b927a3ce 1209 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
018d00d2
ZX		 1210 r = 1;
1211 break;
542472b5
LV		 1212 case KVM_CAP_COALESCED_MMIO:
1213 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1214 break;
774ead3a
AK		 1215 case KVM_CAP_VAPIC:
1216 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1217 break;
f725230a
AK		 1218 case KVM_CAP_NR_VCPUS:
1219 r = KVM_MAX_VCPUS;
1220 break;
a988b910
AK		 1221 case KVM_CAP_NR_MEMSLOTS:
1222 r = KVM_MEMORY_SLOTS;
1223 break;
2f333bcb
MT		 1224 case KVM_CAP_PV_MMU:
1225 r = !tdp_enabled;
1226 break;
62c476c7 1227 case KVM_CAP_IOMMU:
19de40a8 1228 r = iommu_found();
62c476c7 1229 break;
890ca9ae
HY		 1230 case KVM_CAP_MCE:
1231 r = KVM_MAX_MCE_BANKS;
1232 break;
018d00d2
ZX		 1233 default:
1234 r = 0;
1235 break;
1236 }
1237 return r;
1238
1239}
1240
043405e1
CO		 1241long kvm_arch_dev_ioctl(struct file *filp,
1242 unsigned int ioctl, unsigned long arg)
1243{
1244 void __user *argp = (void __user *)arg;
1245 long r;
1246
1247 switch (ioctl) {
1248 case KVM_GET_MSR_INDEX_LIST: {
1249 struct kvm_msr_list __user *user_msr_list = argp;
1250 struct kvm_msr_list msr_list;
1251 unsigned n;
1252
1253 r = -EFAULT;
1254 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1255 goto out;
1256 n = msr_list.nmsrs;
1257 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1258 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1259 goto out;
1260 r = -E2BIG;
e125e7b6 1261 if (n < msr_list.nmsrs)
043405e1
CO		 1262 goto out;
1263 r = -EFAULT;
1264 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1265 num_msrs_to_save * sizeof(u32)))
1266 goto out;
e125e7b6 1267 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1268 &emulated_msrs,
1269 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1270 goto out;
1271 r = 0;
1272 break;
1273 }
674eea0f
AK		 1274 case KVM_GET_SUPPORTED_CPUID: {
1275 struct kvm_cpuid2 __user *cpuid_arg = argp;
1276 struct kvm_cpuid2 cpuid;
1277
1278 r = -EFAULT;
1279 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1280 goto out;
1281 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1282 cpuid_arg->entries);
674eea0f
AK		 1283 if (r)
1284 goto out;
1285
1286 r = -EFAULT;
1287 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1288 goto out;
1289 r = 0;
1290 break;
1291 }
890ca9ae
HY		 1292 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1293 u64 mce_cap;
1294
1295 mce_cap = KVM_MCE_CAP_SUPPORTED;
1296 r = -EFAULT;
1297 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1298 goto out;
1299 r = 0;
1300 break;
1301 }
043405e1
CO		 1302 default:
1303 r = -EINVAL;
1304 }
1305out:
1306 return r;
1307}
1308
313a3dc7
CO		 1309void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1310{
1311 kvm_x86_ops->vcpu_load(vcpu, cpu);
c8076604 1312 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1313}
1314
1315void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1316{
1317 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 1318 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1319}
1320
07716717 1321static int is_efer_nx(void)
313a3dc7 1322{
e286e86e 1323 unsigned long long efer = 0;
313a3dc7 1324
e286e86e 1325 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1326 return efer & EFER_NX;
1327}
1328
1329static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1330{
1331 int i;
1332 struct kvm_cpuid_entry2 *e, *entry;
1333
313a3dc7 1334 entry = NULL;
ad312c7c
ZX		 1335 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1336 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1337 if (e->function == 0x80000001) {
1338 entry = e;
1339 break;
1340 }
1341 }
07716717 1342 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1343 entry->edx &= ~(1 << 20);
1344 printk(KERN_INFO "kvm: guest NX capability removed\n");
1345 }
1346}
1347
07716717 1348/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1349static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1350 struct kvm_cpuid *cpuid,
1351 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1352{
1353 int r, i;
1354 struct kvm_cpuid_entry *cpuid_entries;
1355
1356 r = -E2BIG;
1357 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1358 goto out;
1359 r = -ENOMEM;
1360 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1361 if (!cpuid_entries)
1362 goto out;
1363 r = -EFAULT;
1364 if (copy_from_user(cpuid_entries, entries,
1365 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1366 goto out_free;
1367 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1368 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1369 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1370 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1371 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1372 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1373 vcpu->arch.cpuid_entries[i].index = 0;
1374 vcpu->arch.cpuid_entries[i].flags = 0;
1375 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1376 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1377 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1378 }
1379 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1380 cpuid_fix_nx_cap(vcpu);
1381 r = 0;
fc61b800 1382 kvm_apic_set_version(vcpu);
07716717
DK		 1383
1384out_free:
1385 vfree(cpuid_entries);
1386out:
1387 return r;
1388}
1389
1390static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1391 struct kvm_cpuid2 *cpuid,
1392 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1393{
1394 int r;
1395
1396 r = -E2BIG;
1397 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1398 goto out;
1399 r = -EFAULT;
ad312c7c 1400 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1401 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1402 goto out;
ad312c7c 1403 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1404 kvm_apic_set_version(vcpu);
313a3dc7
CO		 1405 return 0;
1406
1407out:
1408 return r;
1409}
1410
07716717 1411static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1412 struct kvm_cpuid2 *cpuid,
1413 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1414{
1415 int r;
1416
1417 r = -E2BIG;
ad312c7c 1418 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1419 goto out;
1420 r = -EFAULT;
ad312c7c 1421 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1422 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1423 goto out;
1424 return 0;
1425
1426out:
ad312c7c 1427 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1428 return r;
1429}
1430
07716717 1431static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1432 u32 index)
07716717
DK		 1433{
1434 entry->function = function;
1435 entry->index = index;
1436 cpuid_count(entry->function, entry->index,
19355475 1437 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1438 entry->flags = 0;
1439}
1440
7faa4ee1
AK		 1441#define F(x) bit(X86_FEATURE_##x)
1442
07716717
DK		 1443static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1444 u32 index, int *nent, int maxnent)
1445{
7faa4ee1 1446 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
344f414f 1447 unsigned f_gbpages = kvm_x86_ops->gb_page_enable() ? F(GBPAGES) : 0;
07716717 1448#ifdef CONFIG_X86_64
7faa4ee1
AK		 1449 unsigned f_lm = F(LM);
1450#else
1451 unsigned f_lm = 0;
07716717 1452#endif
7faa4ee1
AK		 1453
1454 /* cpuid 1.edx */
1455 const u32 kvm_supported_word0_x86_features =
1456 F(FPU) | F(VME) | F(DE) | F(PSE) |
1457 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1458 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1459 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1460 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1461 0 /* Reserved, DS, ACPI */ | F(MMX) |
1462 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1463 0 /* HTT, TM, Reserved, PBE */;
1464 /* cpuid 0x80000001.edx */
1465 const u32 kvm_supported_word1_x86_features =
1466 F(FPU) | F(VME) | F(DE) | F(PSE) |
1467 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1468 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1469 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1470 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1471 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
344f414f 1472 F(FXSR) | F(FXSR_OPT) | f_gbpages | 0 /* RDTSCP */ |
7faa4ee1
AK		 1473 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1474 /* cpuid 1.ecx */
1475 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1476 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1477 0 /* DS-CPL, VMX, SMX, EST */ |
1478 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1479 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1480 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1481 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1482 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1483 /* cpuid 0x80000001.ecx */
07716717 1484 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1485 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1486 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1487 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1488 0 /* SKINIT */ | 0 /* WDT */;
07716717 1489
19355475 1490 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1491 get_cpu();
1492 do_cpuid_1_ent(entry, function, index);
1493 ++*nent;
1494
1495 switch (function) {
1496 case 0:
1497 entry->eax = min(entry->eax, (u32)0xb);
1498 break;
1499 case 1:
1500 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1501 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1502 /* we support x2apic emulation even if host does not support
1503 * it since we emulate x2apic in software */
1504 entry->ecx |= F(X2APIC);
07716717
DK		 1505 break;
1506 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1507 * may return different values. This forces us to get_cpu() before
1508 * issuing the first command, and also to emulate this annoying behavior
1509 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1510 case 2: {
1511 int t, times = entry->eax & 0xff;
1512
1513 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1514 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1515 for (t = 1; t < times && *nent < maxnent; ++t) {
1516 do_cpuid_1_ent(&entry[t], function, 0);
1517 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1518 ++*nent;
1519 }
1520 break;
1521 }
1522 /* function 4 and 0xb have additional index. */
1523 case 4: {
14af3f3c 1524 int i, cache_type;
07716717
DK		 1525
1526 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1527 /* read more entries until cache_type is zero */
14af3f3c
HH		 1528 for (i = 1; *nent < maxnent; ++i) {
1529 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1530 if (!cache_type)
1531 break;
14af3f3c
HH		 1532 do_cpuid_1_ent(&entry[i], function, i);
1533 entry[i].flags |=
07716717
DK		 1534 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1535 ++*nent;
1536 }
1537 break;
1538 }
1539 case 0xb: {
14af3f3c 1540 int i, level_type;
07716717
DK		 1541
1542 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1543 /* read more entries until level_type is zero */
14af3f3c 1544 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1545 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1546 if (!level_type)
1547 break;
14af3f3c
HH		 1548 do_cpuid_1_ent(&entry[i], function, i);
1549 entry[i].flags |=
07716717
DK		 1550 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1551 ++*nent;
1552 }
1553 break;
1554 }
1555 case 0x80000000:
1556 entry->eax = min(entry->eax, 0x8000001a);
1557 break;
1558 case 0x80000001:
1559 entry->edx &= kvm_supported_word1_x86_features;
1560 entry->ecx &= kvm_supported_word6_x86_features;
1561 break;
1562 }
1563 put_cpu();
1564}
1565
7faa4ee1
AK		 1566#undef F
1567
674eea0f 1568static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1569 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1570{
1571 struct kvm_cpuid_entry2 *cpuid_entries;
1572 int limit, nent = 0, r = -E2BIG;
1573 u32 func;
1574
1575 if (cpuid->nent < 1)
1576 goto out;
1577 r = -ENOMEM;
1578 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1579 if (!cpuid_entries)
1580 goto out;
1581
1582 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1583 limit = cpuid_entries[0].eax;
1584 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1585 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1586 &nent, cpuid->nent);
07716717
DK		 1587 r = -E2BIG;
1588 if (nent >= cpuid->nent)
1589 goto out_free;
1590
1591 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1592 limit = cpuid_entries[nent - 1].eax;
1593 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1594 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1595 &nent, cpuid->nent);
cb007648
MM		 1596 r = -E2BIG;
1597 if (nent >= cpuid->nent)
1598 goto out_free;
1599
07716717
DK		 1600 r = -EFAULT;
1601 if (copy_to_user(entries, cpuid_entries,
19355475 1602 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1603 goto out_free;
1604 cpuid->nent = nent;
1605 r = 0;
1606
1607out_free:
1608 vfree(cpuid_entries);
1609out:
1610 return r;
1611}
1612
313a3dc7
CO		 1613static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1614 struct kvm_lapic_state *s)
1615{
1616 vcpu_load(vcpu);
ad312c7c 1617 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1618 vcpu_put(vcpu);
1619
1620 return 0;
1621}
1622
1623static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1624 struct kvm_lapic_state *s)
1625{
1626 vcpu_load(vcpu);
ad312c7c 1627 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7
CO		 1628 kvm_apic_post_state_restore(vcpu);
1629 vcpu_put(vcpu);
1630
1631 return 0;
1632}
1633
f77bc6a4
ZX		 1634static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1635 struct kvm_interrupt *irq)
1636{
1637 if (irq->irq < 0 || irq->irq >= 256)
1638 return -EINVAL;
1639 if (irqchip_in_kernel(vcpu->kvm))
1640 return -ENXIO;
1641 vcpu_load(vcpu);
1642
66fd3f7f 1643 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 1644
1645 vcpu_put(vcpu);
1646
1647 return 0;
1648}
1649
c4abb7c9
JK		 1650static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1651{
1652 vcpu_load(vcpu);
1653 kvm_inject_nmi(vcpu);
1654 vcpu_put(vcpu);
1655
1656 return 0;
1657}
1658
b209749f
AK		 1659static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1660 struct kvm_tpr_access_ctl *tac)
1661{
1662 if (tac->flags)
1663 return -EINVAL;
1664 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1665 return 0;
1666}
1667
890ca9ae
HY		 1668static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
1669 u64 mcg_cap)
1670{
1671 int r;
1672 unsigned bank_num = mcg_cap & 0xff, bank;
1673
1674 r = -EINVAL;
1675 if (!bank_num)
1676 goto out;
1677 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
1678 goto out;
1679 r = 0;
1680 vcpu->arch.mcg_cap = mcg_cap;
1681 /* Init IA32_MCG_CTL to all 1s */
1682 if (mcg_cap & MCG_CTL_P)
1683 vcpu->arch.mcg_ctl = ~(u64)0;
1684 /* Init IA32_MCi_CTL to all 1s */
1685 for (bank = 0; bank < bank_num; bank++)
1686 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
1687out:
1688 return r;
1689}
1690
1691static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
1692 struct kvm_x86_mce *mce)
1693{
1694 u64 mcg_cap = vcpu->arch.mcg_cap;
1695 unsigned bank_num = mcg_cap & 0xff;
1696 u64 *banks = vcpu->arch.mce_banks;
1697
1698 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
1699 return -EINVAL;
1700 /*
1701 * if IA32_MCG_CTL is not all 1s, the uncorrected error
1702 * reporting is disabled
1703 */
1704 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
1705 vcpu->arch.mcg_ctl != ~(u64)0)
1706 return 0;
1707 banks += 4 * mce->bank;
1708 /*
1709 * if IA32_MCi_CTL is not all 1s, the uncorrected error
1710 * reporting is disabled for the bank
1711 */
1712 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
1713 return 0;
1714 if (mce->status & MCI_STATUS_UC) {
1715 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
1716 !(vcpu->arch.cr4 & X86_CR4_MCE)) {
1717 printk(KERN_DEBUG "kvm: set_mce: "
1718 "injects mce exception while "
1719 "previous one is in progress!\n");
1720 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
1721 return 0;
1722 }
1723 if (banks[1] & MCI_STATUS_VAL)
1724 mce->status |= MCI_STATUS_OVER;
1725 banks[2] = mce->addr;
1726 banks[3] = mce->misc;
1727 vcpu->arch.mcg_status = mce->mcg_status;
1728 banks[1] = mce->status;
1729 kvm_queue_exception(vcpu, MC_VECTOR);
1730 } else if (!(banks[1] & MCI_STATUS_VAL)
1731 || !(banks[1] & MCI_STATUS_UC)) {
1732 if (banks[1] & MCI_STATUS_VAL)
1733 mce->status |= MCI_STATUS_OVER;
1734 banks[2] = mce->addr;
1735 banks[3] = mce->misc;
1736 banks[1] = mce->status;
1737 } else
1738 banks[1] |= MCI_STATUS_OVER;
1739 return 0;
1740}
1741
313a3dc7
CO		 1742long kvm_arch_vcpu_ioctl(struct file *filp,
1743 unsigned int ioctl, unsigned long arg)
1744{
1745 struct kvm_vcpu *vcpu = filp->private_data;
1746 void __user *argp = (void __user *)arg;
1747 int r;
b772ff36 1748 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 1749
1750 switch (ioctl) {
1751 case KVM_GET_LAPIC: {
b772ff36 1752 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 1753
b772ff36
DH		 1754 r = -ENOMEM;
1755 if (!lapic)
1756 goto out;
1757 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 1758 if (r)
1759 goto out;
1760 r = -EFAULT;
b772ff36 1761 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 1762 goto out;
1763 r = 0;
1764 break;
1765 }
1766 case KVM_SET_LAPIC: {
b772ff36
DH		 1767 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1768 r = -ENOMEM;
1769 if (!lapic)
1770 goto out;
313a3dc7 1771 r = -EFAULT;
b772ff36 1772 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 1773 goto out;
b772ff36 1774 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 1775 if (r)
1776 goto out;
1777 r = 0;
1778 break;
1779 }
f77bc6a4
ZX		 1780 case KVM_INTERRUPT: {
1781 struct kvm_interrupt irq;
1782
1783 r = -EFAULT;
1784 if (copy_from_user(&irq, argp, sizeof irq))
1785 goto out;
1786 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1787 if (r)
1788 goto out;
1789 r = 0;
1790 break;
1791 }
c4abb7c9
JK		 1792 case KVM_NMI: {
1793 r = kvm_vcpu_ioctl_nmi(vcpu);
1794 if (r)
1795 goto out;
1796 r = 0;
1797 break;
1798 }
313a3dc7
CO		 1799 case KVM_SET_CPUID: {
1800 struct kvm_cpuid __user *cpuid_arg = argp;
1801 struct kvm_cpuid cpuid;
1802
1803 r = -EFAULT;
1804 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1805 goto out;
1806 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1807 if (r)
1808 goto out;
1809 break;
1810 }
07716717
DK		 1811 case KVM_SET_CPUID2: {
1812 struct kvm_cpuid2 __user *cpuid_arg = argp;
1813 struct kvm_cpuid2 cpuid;
1814
1815 r = -EFAULT;
1816 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1817 goto out;
1818 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 1819 cpuid_arg->entries);
07716717
DK		 1820 if (r)
1821 goto out;
1822 break;
1823 }
1824 case KVM_GET_CPUID2: {
1825 struct kvm_cpuid2 __user *cpuid_arg = argp;
1826 struct kvm_cpuid2 cpuid;
1827
1828 r = -EFAULT;
1829 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1830 goto out;
1831 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 1832 cpuid_arg->entries);
07716717
DK		 1833 if (r)
1834 goto out;
1835 r = -EFAULT;
1836 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1837 goto out;
1838 r = 0;
1839 break;
1840 }
313a3dc7
CO		 1841 case KVM_GET_MSRS:
1842 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1843 break;
1844 case KVM_SET_MSRS:
1845 r = msr_io(vcpu, argp, do_set_msr, 0);
1846 break;
b209749f
AK		 1847 case KVM_TPR_ACCESS_REPORTING: {
1848 struct kvm_tpr_access_ctl tac;
1849
1850 r = -EFAULT;
1851 if (copy_from_user(&tac, argp, sizeof tac))
1852 goto out;
1853 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1854 if (r)
1855 goto out;
1856 r = -EFAULT;
1857 if (copy_to_user(argp, &tac, sizeof tac))
1858 goto out;
1859 r = 0;
1860 break;
1861 };
b93463aa
AK		 1862 case KVM_SET_VAPIC_ADDR: {
1863 struct kvm_vapic_addr va;
1864
1865 r = -EINVAL;
1866 if (!irqchip_in_kernel(vcpu->kvm))
1867 goto out;
1868 r = -EFAULT;
1869 if (copy_from_user(&va, argp, sizeof va))
1870 goto out;
1871 r = 0;
1872 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1873 break;
1874 }
890ca9ae
HY		 1875 case KVM_X86_SETUP_MCE: {
1876 u64 mcg_cap;
1877
1878 r = -EFAULT;
1879 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
1880 goto out;
1881 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
1882 break;
1883 }
1884 case KVM_X86_SET_MCE: {
1885 struct kvm_x86_mce mce;
1886
1887 r = -EFAULT;
1888 if (copy_from_user(&mce, argp, sizeof mce))
1889 goto out;
1890 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
1891 break;
1892 }
313a3dc7
CO		 1893 default:
1894 r = -EINVAL;
1895 }
1896out:
7a6ce84c 1897 kfree(lapic);
313a3dc7
CO		 1898 return r;
1899}
1900
1fe779f8
CO		 1901static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1902{
1903 int ret;
1904
1905 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1906 return -1;
1907 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1908 return ret;
1909}
1910
b927a3ce
SY		 1911static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
1912 u64 ident_addr)
1913{
1914 kvm->arch.ept_identity_map_addr = ident_addr;
1915 return 0;
1916}
1917
1fe779f8
CO		 1918static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1919 u32 kvm_nr_mmu_pages)
1920{
1921 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1922 return -EINVAL;
1923
72dc67a6 1924 down_write(&kvm->slots_lock);
7c8a83b7 1925 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 1926
1927 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1928 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1929
7c8a83b7 1930 spin_unlock(&kvm->mmu_lock);
72dc67a6 1931 up_write(&kvm->slots_lock);
1fe779f8
CO		 1932 return 0;
1933}
1934
1935static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1936{
f05e70ac 1937 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1938}
1939
e9f85cde
ZX		 1940gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1941{
1942 int i;
1943 struct kvm_mem_alias *alias;
1944
d69fb81f
ZX		 1945 for (i = 0; i < kvm->arch.naliases; ++i) {
1946 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1947 if (gfn >= alias->base_gfn
1948 && gfn < alias->base_gfn + alias->npages)
1949 return alias->target_gfn + gfn - alias->base_gfn;
1950 }
1951 return gfn;
1952}
1953
1fe779f8
CO		 1954/*
1955 * Set a new alias region. Aliases map a portion of physical memory into
1956 * another portion. This is useful for memory windows, for example the PC
1957 * VGA region.
1958 */
1959static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1960 struct kvm_memory_alias *alias)
1961{
1962 int r, n;
1963 struct kvm_mem_alias *p;
1964
1965 r = -EINVAL;
1966 /* General sanity checks */
1967 if (alias->memory_size & (PAGE_SIZE - 1))
1968 goto out;
1969 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1970 goto out;
1971 if (alias->slot >= KVM_ALIAS_SLOTS)
1972 goto out;
1973 if (alias->guest_phys_addr + alias->memory_size
1974 < alias->guest_phys_addr)
1975 goto out;
1976 if (alias->target_phys_addr + alias->memory_size
1977 < alias->target_phys_addr)
1978 goto out;
1979
72dc67a6 1980 down_write(&kvm->slots_lock);
a1708ce8 1981 spin_lock(&kvm->mmu_lock);
1fe779f8 1982
d69fb81f 1983 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 1984 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1985 p->npages = alias->memory_size >> PAGE_SHIFT;
1986 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1987
1988 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 1989 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 1990 break;
d69fb81f 1991 kvm->arch.naliases = n;
1fe779f8 1992
a1708ce8 1993 spin_unlock(&kvm->mmu_lock);
1fe779f8
CO		 1994 kvm_mmu_zap_all(kvm);
1995
72dc67a6 1996 up_write(&kvm->slots_lock);
1fe779f8
CO		 1997
1998 return 0;
1999
2000out:
2001 return r;
2002}
2003
2004static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2005{
2006 int r;
2007
2008 r = 0;
2009 switch (chip->chip_id) {
2010 case KVM_IRQCHIP_PIC_MASTER:
2011 memcpy(&chip->chip.pic,
2012 &pic_irqchip(kvm)->pics[0],
2013 sizeof(struct kvm_pic_state));
2014 break;
2015 case KVM_IRQCHIP_PIC_SLAVE:
2016 memcpy(&chip->chip.pic,
2017 &pic_irqchip(kvm)->pics[1],
2018 sizeof(struct kvm_pic_state));
2019 break;
2020 case KVM_IRQCHIP_IOAPIC:
2021 memcpy(&chip->chip.ioapic,
2022 ioapic_irqchip(kvm),
2023 sizeof(struct kvm_ioapic_state));
2024 break;
2025 default:
2026 r = -EINVAL;
2027 break;
2028 }
2029 return r;
2030}
2031
2032static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2033{
2034 int r;
2035
2036 r = 0;
2037 switch (chip->chip_id) {
2038 case KVM_IRQCHIP_PIC_MASTER:
894a9c55 2039 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2040 memcpy(&pic_irqchip(kvm)->pics[0],
2041 &chip->chip.pic,
2042 sizeof(struct kvm_pic_state));
894a9c55 2043 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2044 break;
2045 case KVM_IRQCHIP_PIC_SLAVE:
894a9c55 2046 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2047 memcpy(&pic_irqchip(kvm)->pics[1],
2048 &chip->chip.pic,
2049 sizeof(struct kvm_pic_state));
894a9c55 2050 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2051 break;
2052 case KVM_IRQCHIP_IOAPIC:
894a9c55 2053 mutex_lock(&kvm->irq_lock);
1fe779f8
CO		 2054 memcpy(ioapic_irqchip(kvm),
2055 &chip->chip.ioapic,
2056 sizeof(struct kvm_ioapic_state));
894a9c55 2057 mutex_unlock(&kvm->irq_lock);
1fe779f8
CO		 2058 break;
2059 default:
2060 r = -EINVAL;
2061 break;
2062 }
2063 kvm_pic_update_irq(pic_irqchip(kvm));
2064 return r;
2065}
2066
e0f63cb9
SY		 2067static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2068{
2069 int r = 0;
2070
894a9c55 2071 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2072 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2073 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2074 return r;
2075}
2076
2077static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2078{
2079 int r = 0;
2080
894a9c55 2081 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2082 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2083 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2084 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2085 return r;
2086}
2087
2088static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2089{
2090 int r = 0;
2091
2092 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2093 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2094 sizeof(ps->channels));
2095 ps->flags = kvm->arch.vpit->pit_state.flags;
2096 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2097 return r;
2098}
2099
2100static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2101{
2102 int r = 0, start = 0;
2103 u32 prev_legacy, cur_legacy;
2104 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2105 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2106 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2107 if (!prev_legacy && cur_legacy)
2108 start = 1;
2109 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2110 sizeof(kvm->arch.vpit->pit_state.channels));
2111 kvm->arch.vpit->pit_state.flags = ps->flags;
2112 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2113 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2114 return r;
2115}
2116
52d939a0
MT		 2117static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2118 struct kvm_reinject_control *control)
2119{
2120 if (!kvm->arch.vpit)
2121 return -ENXIO;
894a9c55 2122 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2123 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2124 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2125 return 0;
2126}
2127
5bb064dc
ZX		 2128/*
2129 * Get (and clear) the dirty memory log for a memory slot.
2130 */
2131int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2132 struct kvm_dirty_log *log)
2133{
2134 int r;
2135 int n;
2136 struct kvm_memory_slot *memslot;
2137 int is_dirty = 0;
2138
72dc67a6 2139 down_write(&kvm->slots_lock);
5bb064dc
ZX		 2140
2141 r = kvm_get_dirty_log(kvm, log, &is_dirty);
2142 if (r)
2143 goto out;
2144
2145 /* If nothing is dirty, don't bother messing with page tables. */
2146 if (is_dirty) {
7c8a83b7 2147 spin_lock(&kvm->mmu_lock);
5bb064dc 2148 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2149 spin_unlock(&kvm->mmu_lock);
5bb064dc
ZX		 2150 kvm_flush_remote_tlbs(kvm);
2151 memslot = &kvm->memslots[log->slot];
2152 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
2153 memset(memslot->dirty_bitmap, 0, n);
2154 }
2155 r = 0;
2156out:
72dc67a6 2157 up_write(&kvm->slots_lock);
5bb064dc
ZX		 2158 return r;
2159}
2160
1fe779f8
CO		 2161long kvm_arch_vm_ioctl(struct file *filp,
2162 unsigned int ioctl, unsigned long arg)
2163{
2164 struct kvm *kvm = filp->private_data;
2165 void __user *argp = (void __user *)arg;
2166 int r = -EINVAL;
f0d66275
DH		 2167 /*
2168 * This union makes it completely explicit to gcc-3.x
2169 * that these two variables' stack usage should be
2170 * combined, not added together.
2171 */
2172 union {
2173 struct kvm_pit_state ps;
e9f42757 2174 struct kvm_pit_state2 ps2;
f0d66275 2175 struct kvm_memory_alias alias;
c5ff41ce 2176 struct kvm_pit_config pit_config;
f0d66275 2177 } u;
1fe779f8
CO		 2178
2179 switch (ioctl) {
2180 case KVM_SET_TSS_ADDR:
2181 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2182 if (r < 0)
2183 goto out;
2184 break;
b927a3ce
SY		 2185 case KVM_SET_IDENTITY_MAP_ADDR: {
2186 u64 ident_addr;
2187
2188 r = -EFAULT;
2189 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2190 goto out;
2191 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2192 if (r < 0)
2193 goto out;
2194 break;
2195 }
1fe779f8
CO		 2196 case KVM_SET_MEMORY_REGION: {
2197 struct kvm_memory_region kvm_mem;
2198 struct kvm_userspace_memory_region kvm_userspace_mem;
2199
2200 r = -EFAULT;
2201 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2202 goto out;
2203 kvm_userspace_mem.slot = kvm_mem.slot;
2204 kvm_userspace_mem.flags = kvm_mem.flags;
2205 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2206 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2207 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2208 if (r)
2209 goto out;
2210 break;
2211 }
2212 case KVM_SET_NR_MMU_PAGES:
2213 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2214 if (r)
2215 goto out;
2216 break;
2217 case KVM_GET_NR_MMU_PAGES:
2218 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2219 break;
f0d66275 2220 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2221 r = -EFAULT;
f0d66275 2222 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2223 goto out;
f0d66275 2224 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2225 if (r)
2226 goto out;
2227 break;
1fe779f8
CO		 2228 case KVM_CREATE_IRQCHIP:
2229 r = -ENOMEM;
d7deeeb0
ZX		 2230 kvm->arch.vpic = kvm_create_pic(kvm);
2231 if (kvm->arch.vpic) {
1fe779f8
CO		 2232 r = kvm_ioapic_init(kvm);
2233 if (r) {
d7deeeb0
ZX		 2234 kfree(kvm->arch.vpic);
2235 kvm->arch.vpic = NULL;
1fe779f8
CO		 2236 goto out;
2237 }
2238 } else
2239 goto out;
399ec807
AK		 2240 r = kvm_setup_default_irq_routing(kvm);
2241 if (r) {
2242 kfree(kvm->arch.vpic);
2243 kfree(kvm->arch.vioapic);
2244 goto out;
2245 }
1fe779f8 2246 break;
7837699f 2247 case KVM_CREATE_PIT:
c5ff41ce
JK		 2248 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2249 goto create_pit;
2250 case KVM_CREATE_PIT2:
2251 r = -EFAULT;
2252 if (copy_from_user(&u.pit_config, argp,
2253 sizeof(struct kvm_pit_config)))
2254 goto out;
2255 create_pit:
108b5669 2256 down_write(&kvm->slots_lock);
269e05e4
AK		 2257 r = -EEXIST;
2258 if (kvm->arch.vpit)
2259 goto create_pit_unlock;
7837699f 2260 r = -ENOMEM;
c5ff41ce 2261 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2262 if (kvm->arch.vpit)
2263 r = 0;
269e05e4 2264 create_pit_unlock:
108b5669 2265 up_write(&kvm->slots_lock);
7837699f 2266 break;
4925663a 2267 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2268 case KVM_IRQ_LINE: {
2269 struct kvm_irq_level irq_event;
2270
2271 r = -EFAULT;
2272 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2273 goto out;
2274 if (irqchip_in_kernel(kvm)) {
4925663a 2275 __s32 status;
fa40a821 2276 mutex_lock(&kvm->irq_lock);
4925663a
GN		 2277 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2278 irq_event.irq, irq_event.level);
fa40a821 2279 mutex_unlock(&kvm->irq_lock);
4925663a
GN		 2280 if (ioctl == KVM_IRQ_LINE_STATUS) {
2281 irq_event.status = status;
2282 if (copy_to_user(argp, &irq_event,
2283 sizeof irq_event))
2284 goto out;
2285 }
1fe779f8
CO		 2286 r = 0;
2287 }
2288 break;
2289 }
2290 case KVM_GET_IRQCHIP: {
2291 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2292 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2293
f0d66275
DH		 2294 r = -ENOMEM;
2295 if (!chip)
1fe779f8 2296 goto out;
f0d66275
DH		 2297 r = -EFAULT;
2298 if (copy_from_user(chip, argp, sizeof *chip))
2299 goto get_irqchip_out;
1fe779f8
CO		 2300 r = -ENXIO;
2301 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2302 goto get_irqchip_out;
2303 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2304 if (r)
f0d66275 2305 goto get_irqchip_out;
1fe779f8 2306 r = -EFAULT;
f0d66275
DH		 2307 if (copy_to_user(argp, chip, sizeof *chip))
2308 goto get_irqchip_out;
1fe779f8 2309 r = 0;
f0d66275
DH		 2310 get_irqchip_out:
2311 kfree(chip);
2312 if (r)
2313 goto out;
1fe779f8
CO		 2314 break;
2315 }
2316 case KVM_SET_IRQCHIP: {
2317 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2318 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2319
f0d66275
DH		 2320 r = -ENOMEM;
2321 if (!chip)
1fe779f8 2322 goto out;
f0d66275
DH		 2323 r = -EFAULT;
2324 if (copy_from_user(chip, argp, sizeof *chip))
2325 goto set_irqchip_out;
1fe779f8
CO		 2326 r = -ENXIO;
2327 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2328 goto set_irqchip_out;
2329 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2330 if (r)
f0d66275 2331 goto set_irqchip_out;
1fe779f8 2332 r = 0;
f0d66275
DH		 2333 set_irqchip_out:
2334 kfree(chip);
2335 if (r)
2336 goto out;
1fe779f8
CO		 2337 break;
2338 }
e0f63cb9 2339 case KVM_GET_PIT: {
e0f63cb9 2340 r = -EFAULT;
f0d66275 2341 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2342 goto out;
2343 r = -ENXIO;
2344 if (!kvm->arch.vpit)
2345 goto out;
f0d66275 2346 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2347 if (r)
2348 goto out;
2349 r = -EFAULT;
f0d66275 2350 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2351 goto out;
2352 r = 0;
2353 break;
2354 }
2355 case KVM_SET_PIT: {
e0f63cb9 2356 r = -EFAULT;
f0d66275 2357 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 2358 goto out;
2359 r = -ENXIO;
2360 if (!kvm->arch.vpit)
2361 goto out;
f0d66275 2362 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 2363 if (r)
2364 goto out;
2365 r = 0;
2366 break;
2367 }
e9f42757
BK		 2368 case KVM_GET_PIT2: {
2369 r = -ENXIO;
2370 if (!kvm->arch.vpit)
2371 goto out;
2372 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
2373 if (r)
2374 goto out;
2375 r = -EFAULT;
2376 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
2377 goto out;
2378 r = 0;
2379 break;
2380 }
2381 case KVM_SET_PIT2: {
2382 r = -EFAULT;
2383 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
2384 goto out;
2385 r = -ENXIO;
2386 if (!kvm->arch.vpit)
2387 goto out;
2388 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
2389 if (r)
2390 goto out;
2391 r = 0;
2392 break;
2393 }
52d939a0
MT		 2394 case KVM_REINJECT_CONTROL: {
2395 struct kvm_reinject_control control;
2396 r = -EFAULT;
2397 if (copy_from_user(&control, argp, sizeof(control)))
2398 goto out;
2399 r = kvm_vm_ioctl_reinject(kvm, &control);
2400 if (r)
2401 goto out;
2402 r = 0;
2403 break;
2404 }
1fe779f8
CO		 2405 default:
2406 ;
2407 }
2408out:
2409 return r;
2410}
2411
a16b043c 2412static void kvm_init_msr_list(void)
043405e1
CO		 2413{
2414 u32 dummy[2];
2415 unsigned i, j;
2416
2417 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
2418 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2419 continue;
2420 if (j < i)
2421 msrs_to_save[j] = msrs_to_save[i];
2422 j++;
2423 }
2424 num_msrs_to_save = j;
2425}
2426
bda9020e
MT		 2427static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
2428 const void *v)
bbd9b64e 2429{
bda9020e
MT		 2430 if (vcpu->arch.apic &&
2431 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
2432 return 0;
bbd9b64e 2433
bda9020e 2434 return kvm_io_bus_write(&vcpu->kvm->mmio_bus, addr, len, v);
bbd9b64e
CO		 2435}
2436
bda9020e 2437static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 2438{
bda9020e
MT		 2439 if (vcpu->arch.apic &&
2440 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
2441 return 0;
bbd9b64e 2442
bda9020e 2443 return kvm_io_bus_read(&vcpu->kvm->mmio_bus, addr, len, v);
bbd9b64e
CO		 2444}
2445
cded19f3
HE		 2446static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
2447 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 2448{
2449 void *data = val;
10589a46 2450 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 2451
2452 while (bytes) {
ad312c7c 2453 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e 2454 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 2455 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 2456 int ret;
2457
10589a46
MT		 2458 if (gpa == UNMAPPED_GVA) {
2459 r = X86EMUL_PROPAGATE_FAULT;
2460 goto out;
2461 }
77c2002e 2462 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 2463 if (ret < 0) {
2464 r = X86EMUL_UNHANDLEABLE;
2465 goto out;
2466 }
bbd9b64e 2467
77c2002e
IE		 2468 bytes -= toread;
2469 data += toread;
2470 addr += toread;
bbd9b64e 2471 }
10589a46 2472out:
10589a46 2473 return r;
bbd9b64e 2474}
77c2002e 2475
cded19f3
HE		 2476static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2477 struct kvm_vcpu *vcpu)
77c2002e
IE		 2478{
2479 void *data = val;
2480 int r = X86EMUL_CONTINUE;
2481
2482 while (bytes) {
2483 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2484 unsigned offset = addr & (PAGE_SIZE-1);
2485 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2486 int ret;
2487
2488 if (gpa == UNMAPPED_GVA) {
2489 r = X86EMUL_PROPAGATE_FAULT;
2490 goto out;
2491 }
2492 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2493 if (ret < 0) {
2494 r = X86EMUL_UNHANDLEABLE;
2495 goto out;
2496 }
2497
2498 bytes -= towrite;
2499 data += towrite;
2500 addr += towrite;
2501 }
2502out:
2503 return r;
2504}
2505
bbd9b64e 2506
bbd9b64e
CO		 2507static int emulator_read_emulated(unsigned long addr,
2508 void *val,
2509 unsigned int bytes,
2510 struct kvm_vcpu *vcpu)
2511{
bbd9b64e
CO		 2512 gpa_t gpa;
2513
2514 if (vcpu->mmio_read_completed) {
2515 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 2516 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
2517 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 2518 vcpu->mmio_read_completed = 0;
2519 return X86EMUL_CONTINUE;
2520 }
2521
ad312c7c 2522 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2523
2524 /* For APIC access vmexit */
2525 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2526 goto mmio;
2527
77c2002e
IE		 2528 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2529 == X86EMUL_CONTINUE)
bbd9b64e
CO		 2530 return X86EMUL_CONTINUE;
2531 if (gpa == UNMAPPED_GVA)
2532 return X86EMUL_PROPAGATE_FAULT;
2533
2534mmio:
2535 /*
2536 * Is this MMIO handled locally?
2537 */
aec51dc4
AK		 2538 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
2539 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e 2540 return X86EMUL_CONTINUE;
aec51dc4
AK		 2541 }
2542
2543 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 2544
2545 vcpu->mmio_needed = 1;
2546 vcpu->mmio_phys_addr = gpa;
2547 vcpu->mmio_size = bytes;
2548 vcpu->mmio_is_write = 0;
2549
2550 return X86EMUL_UNHANDLEABLE;
2551}
2552
3200f405 2553int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 2554 const void *val, int bytes)
bbd9b64e
CO		 2555{
2556 int ret;
2557
2558 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 2559 if (ret < 0)
bbd9b64e 2560 return 0;
ad218f85 2561 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 2562 return 1;
2563}
2564
2565static int emulator_write_emulated_onepage(unsigned long addr,
2566 const void *val,
2567 unsigned int bytes,
2568 struct kvm_vcpu *vcpu)
2569{
10589a46
MT		 2570 gpa_t gpa;
2571
10589a46 2572 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2573
2574 if (gpa == UNMAPPED_GVA) {
c3c91fee 2575 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 2576 return X86EMUL_PROPAGATE_FAULT;
2577 }
2578
2579 /* For APIC access vmexit */
2580 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2581 goto mmio;
2582
2583 if (emulator_write_phys(vcpu, gpa, val, bytes))
2584 return X86EMUL_CONTINUE;
2585
2586mmio:
aec51dc4 2587 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 2588 /*
2589 * Is this MMIO handled locally?
2590 */
bda9020e 2591 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 2592 return X86EMUL_CONTINUE;
bbd9b64e
CO		 2593
2594 vcpu->mmio_needed = 1;
2595 vcpu->mmio_phys_addr = gpa;
2596 vcpu->mmio_size = bytes;
2597 vcpu->mmio_is_write = 1;
2598 memcpy(vcpu->mmio_data, val, bytes);
2599
2600 return X86EMUL_CONTINUE;
2601}
2602
2603int emulator_write_emulated(unsigned long addr,
2604 const void *val,
2605 unsigned int bytes,
2606 struct kvm_vcpu *vcpu)
2607{
2608 /* Crossing a page boundary? */
2609 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2610 int rc, now;
2611
2612 now = -addr & ~PAGE_MASK;
2613 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2614 if (rc != X86EMUL_CONTINUE)
2615 return rc;
2616 addr += now;
2617 val += now;
2618 bytes -= now;
2619 }
2620 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2621}
2622EXPORT_SYMBOL_GPL(emulator_write_emulated);
2623
2624static int emulator_cmpxchg_emulated(unsigned long addr,
2625 const void *old,
2626 const void *new,
2627 unsigned int bytes,
2628 struct kvm_vcpu *vcpu)
2629{
2630 static int reported;
2631
2632 if (!reported) {
2633 reported = 1;
2634 printk(KERN_WARNING "kvm: emulating exchange as write\n");
2635 }
2bacc55c
MT		 2636#ifndef CONFIG_X86_64
2637 /* guests cmpxchg8b have to be emulated atomically */
2638 if (bytes == 8) {
10589a46 2639 gpa_t gpa;
2bacc55c 2640 struct page *page;
c0b49b0d 2641 char *kaddr;
2bacc55c
MT		 2642 u64 val;
2643
10589a46
MT		 2644 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2645
2bacc55c
MT		 2646 if (gpa == UNMAPPED_GVA ||
2647 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2648 goto emul_write;
2649
2650 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2651 goto emul_write;
2652
2653 val = *(u64 *)new;
72dc67a6 2654
2bacc55c 2655 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 2656
c0b49b0d
AM		 2657 kaddr = kmap_atomic(page, KM_USER0);
2658 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2659 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 2660 kvm_release_page_dirty(page);
2661 }
3200f405 2662emul_write:
2bacc55c
MT		 2663#endif
2664
bbd9b64e
CO		 2665 return emulator_write_emulated(addr, new, bytes, vcpu);
2666}
2667
2668static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2669{
2670 return kvm_x86_ops->get_segment_base(vcpu, seg);
2671}
2672
2673int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2674{
a7052897 2675 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 2676 return X86EMUL_CONTINUE;
2677}
2678
2679int emulate_clts(struct kvm_vcpu *vcpu)
2680{
ad312c7c 2681 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 2682 return X86EMUL_CONTINUE;
2683}
2684
2685int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2686{
2687 struct kvm_vcpu *vcpu = ctxt->vcpu;
2688
2689 switch (dr) {
2690 case 0 ... 3:
2691 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2692 return X86EMUL_CONTINUE;
2693 default:
b8688d51 2694 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2695 return X86EMUL_UNHANDLEABLE;
2696 }
2697}
2698
2699int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2700{
2701 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2702 int exception;
2703
2704 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2705 if (exception) {
2706 /* FIXME: better handling */
2707 return X86EMUL_UNHANDLEABLE;
2708 }
2709 return X86EMUL_CONTINUE;
2710}
2711
2712void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2713{
bbd9b64e 2714 u8 opcodes[4];
5fdbf976 2715 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 2716 unsigned long rip_linear;
2717
f76c710d 2718 if (!printk_ratelimit())
bbd9b64e
CO		 2719 return;
2720
25be4608
GC		 2721 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2722
77c2002e 2723 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
bbd9b64e
CO		 2724
2725 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2726 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 2727}
2728EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2729
14af3f3c 2730static struct x86_emulate_ops emulate_ops = {
77c2002e 2731 .read_std = kvm_read_guest_virt,
bbd9b64e
CO		 2732 .read_emulated = emulator_read_emulated,
2733 .write_emulated = emulator_write_emulated,
2734 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2735};
2736
5fdbf976
MT		 2737static void cache_all_regs(struct kvm_vcpu *vcpu)
2738{
2739 kvm_register_read(vcpu, VCPU_REGS_RAX);
2740 kvm_register_read(vcpu, VCPU_REGS_RSP);
2741 kvm_register_read(vcpu, VCPU_REGS_RIP);
2742 vcpu->arch.regs_dirty = ~0;
2743}
2744
bbd9b64e
CO		 2745int emulate_instruction(struct kvm_vcpu *vcpu,
2746 struct kvm_run *run,
2747 unsigned long cr2,
2748 u16 error_code,
571008da 2749 int emulation_type)
bbd9b64e 2750{
310b5d30 2751 int r, shadow_mask;
571008da 2752 struct decode_cache *c;
bbd9b64e 2753
26eef70c 2754 kvm_clear_exception_queue(vcpu);
ad312c7c 2755 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976
MT		 2756 /*
2757 * TODO: fix x86_emulate.c to use guest_read/write_register
2758 * instead of direct ->regs accesses, can save hundred cycles
2759 * on Intel for instructions that don't read/change RSP, for
2760 * for example.
2761 */
2762 cache_all_regs(vcpu);
bbd9b64e
CO		 2763
2764 vcpu->mmio_is_write = 0;
ad312c7c 2765 vcpu->arch.pio.string = 0;
bbd9b64e 2766
571008da 2767 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2768 int cs_db, cs_l;
2769 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2770
ad312c7c
ZX		 2771 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2772 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2773 vcpu->arch.emulate_ctxt.mode =
2774 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2775 ? X86EMUL_MODE_REAL : cs_l
2776 ? X86EMUL_MODE_PROT64 : cs_db
2777 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2778
ad312c7c 2779 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da 2780
0cb5762e
AP		 2781 /* Only allow emulation of specific instructions on #UD
2782 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 2783 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 2784 if (emulation_type & EMULTYPE_TRAP_UD) {
2785 if (!c->twobyte)
2786 return EMULATE_FAIL;
2787 switch (c->b) {
2788 case 0x01: /* VMMCALL */
2789 if (c->modrm_mod != 3 || c->modrm_rm != 1)
2790 return EMULATE_FAIL;
2791 break;
2792 case 0x34: /* sysenter */
2793 case 0x35: /* sysexit */
2794 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2795 return EMULATE_FAIL;
2796 break;
2797 case 0x05: /* syscall */
2798 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2799 return EMULATE_FAIL;
2800 break;
2801 default:
2802 return EMULATE_FAIL;
2803 }
2804
2805 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
2806 return EMULATE_FAIL;
2807 }
571008da 2808
f2b5756b 2809 ++vcpu->stat.insn_emulation;
bbd9b64e 2810 if (r) {
f2b5756b 2811 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2812 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2813 return EMULATE_DONE;
2814 return EMULATE_FAIL;
2815 }
2816 }
2817
ba8afb6b
GN		 2818 if (emulation_type & EMULTYPE_SKIP) {
2819 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
2820 return EMULATE_DONE;
2821 }
2822
ad312c7c 2823 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 2824 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
2825
2826 if (r == 0)
2827 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 2828
ad312c7c 2829 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2830 return EMULATE_DO_MMIO;
2831
2832 if ((r || vcpu->mmio_is_write) && run) {
2833 run->exit_reason = KVM_EXIT_MMIO;
2834 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2835 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2836 run->mmio.len = vcpu->mmio_size;
2837 run->mmio.is_write = vcpu->mmio_is_write;
2838 }
2839
2840 if (r) {
2841 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2842 return EMULATE_DONE;
2843 if (!vcpu->mmio_needed) {
2844 kvm_report_emulation_failure(vcpu, "mmio");
2845 return EMULATE_FAIL;
2846 }
2847 return EMULATE_DO_MMIO;
2848 }
2849
ad312c7c 2850 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2851
2852 if (vcpu->mmio_is_write) {
2853 vcpu->mmio_needed = 0;
2854 return EMULATE_DO_MMIO;
2855 }
2856
2857 return EMULATE_DONE;
2858}
2859EXPORT_SYMBOL_GPL(emulate_instruction);
2860
de7d789a
CO		 2861static int pio_copy_data(struct kvm_vcpu *vcpu)
2862{
ad312c7c 2863 void *p = vcpu->arch.pio_data;
0f346074 2864 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 2865 unsigned bytes;
0f346074 2866 int ret;
de7d789a 2867
ad312c7c
ZX		 2868 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2869 if (vcpu->arch.pio.in)
0f346074 2870 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
de7d789a 2871 else
0f346074
IE		 2872 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
2873 return ret;
de7d789a
CO		 2874}
2875
2876int complete_pio(struct kvm_vcpu *vcpu)
2877{
ad312c7c 2878 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2879 long delta;
2880 int r;
5fdbf976 2881 unsigned long val;
de7d789a
CO		 2882
2883 if (!io->string) {
5fdbf976
MT		 2884 if (io->in) {
2885 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2886 memcpy(&val, vcpu->arch.pio_data, io->size);
2887 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2888 }
de7d789a
CO		 2889 } else {
2890 if (io->in) {
2891 r = pio_copy_data(vcpu);
5fdbf976 2892 if (r)
de7d789a 2893 return r;
de7d789a
CO		 2894 }
2895
2896 delta = 1;
2897 if (io->rep) {
2898 delta *= io->cur_count;
2899 /*
2900 * The size of the register should really depend on
2901 * current address size.
2902 */
5fdbf976
MT		 2903 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2904 val -= delta;
2905 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 2906 }
2907 if (io->down)
2908 delta = -delta;
2909 delta *= io->size;
5fdbf976
MT		 2910 if (io->in) {
2911 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2912 val += delta;
2913 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2914 } else {
2915 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2916 val += delta;
2917 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2918 }
de7d789a
CO		 2919 }
2920
de7d789a
CO		 2921 io->count -= io->cur_count;
2922 io->cur_count = 0;
2923
2924 return 0;
2925}
2926
bda9020e 2927static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
de7d789a
CO		 2928{
2929 /* TODO: String I/O for in kernel device */
bda9020e 2930 int r;
de7d789a 2931
ad312c7c 2932 if (vcpu->arch.pio.in)
bda9020e
MT		 2933 r = kvm_io_bus_read(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
2934 vcpu->arch.pio.size, pd);
de7d789a 2935 else
bda9020e
MT		 2936 r = kvm_io_bus_write(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
2937 vcpu->arch.pio.size, pd);
2938 return r;
de7d789a
CO		 2939}
2940
bda9020e 2941static int pio_string_write(struct kvm_vcpu *vcpu)
de7d789a 2942{
ad312c7c
ZX		 2943 struct kvm_pio_request *io = &vcpu->arch.pio;
2944 void *pd = vcpu->arch.pio_data;
bda9020e 2945 int i, r = 0;
de7d789a 2946
de7d789a 2947 for (i = 0; i < io->cur_count; i++) {
bda9020e
MT		 2948 if (kvm_io_bus_write(&vcpu->kvm->pio_bus,
2949 io->port, io->size, pd)) {
2950 r = -EOPNOTSUPP;
2951 break;
2952 }
de7d789a
CO		 2953 pd += io->size;
2954 }
bda9020e 2955 return r;
de7d789a
CO		 2956}
2957
2958int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2959 int size, unsigned port)
2960{
5fdbf976 2961 unsigned long val;
de7d789a
CO		 2962
2963 vcpu->run->exit_reason = KVM_EXIT_IO;
2964 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2965 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2966 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2967 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2968 vcpu->run->io.port = vcpu->arch.pio.port = port;
2969 vcpu->arch.pio.in = in;
2970 vcpu->arch.pio.string = 0;
2971 vcpu->arch.pio.down = 0;
ad312c7c 2972 vcpu->arch.pio.rep = 0;
de7d789a 2973
229456fc
MT		 2974 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
2975 size, 1);
2714d1d3 2976
5fdbf976
MT		 2977 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2978 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a 2979
bda9020e 2980 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
de7d789a
CO		 2981 complete_pio(vcpu);
2982 return 1;
2983 }
2984 return 0;
2985}
2986EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2987
2988int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2989 int size, unsigned long count, int down,
2990 gva_t address, int rep, unsigned port)
2991{
2992 unsigned now, in_page;
0f346074 2993 int ret = 0;
de7d789a
CO		 2994
2995 vcpu->run->exit_reason = KVM_EXIT_IO;
2996 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2997 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2998 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2999 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
3000 vcpu->run->io.port = vcpu->arch.pio.port = port;
3001 vcpu->arch.pio.in = in;
3002 vcpu->arch.pio.string = 1;
3003 vcpu->arch.pio.down = down;
ad312c7c 3004 vcpu->arch.pio.rep = rep;
de7d789a 3005
229456fc
MT		 3006 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
3007 size, count);
2714d1d3 3008
de7d789a
CO		 3009 if (!count) {
3010 kvm_x86_ops->skip_emulated_instruction(vcpu);
3011 return 1;
3012 }
3013
3014 if (!down)
3015 in_page = PAGE_SIZE - offset_in_page(address);
3016 else
3017 in_page = offset_in_page(address) + size;
3018 now = min(count, (unsigned long)in_page / size);
0f346074 3019 if (!now)
de7d789a 3020 now = 1;
de7d789a
CO		 3021 if (down) {
3022 /*
3023 * String I/O in reverse. Yuck. Kill the guest, fix later.
3024 */
3025 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 3026 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 3027 return 1;
3028 }
3029 vcpu->run->io.count = now;
ad312c7c 3030 vcpu->arch.pio.cur_count = now;
de7d789a 3031
ad312c7c 3032 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 3033 kvm_x86_ops->skip_emulated_instruction(vcpu);
3034
0f346074 3035 vcpu->arch.pio.guest_gva = address;
de7d789a 3036
ad312c7c 3037 if (!vcpu->arch.pio.in) {
de7d789a
CO		 3038 /* string PIO write */
3039 ret = pio_copy_data(vcpu);
0f346074
IE		 3040 if (ret == X86EMUL_PROPAGATE_FAULT) {
3041 kvm_inject_gp(vcpu, 0);
3042 return 1;
3043 }
bda9020e 3044 if (ret == 0 && !pio_string_write(vcpu)) {
de7d789a 3045 complete_pio(vcpu);
ad312c7c 3046 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 3047 ret = 1;
3048 }
bda9020e
MT		 3049 }
3050 /* no string PIO read support yet */
de7d789a
CO		 3051
3052 return ret;
3053}
3054EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
3055
c8076604
GH		 3056static void bounce_off(void *info)
3057{
3058 /* nothing */
3059}
3060
3061static unsigned int ref_freq;
3062static unsigned long tsc_khz_ref;
3063
3064static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3065 void *data)
3066{
3067 struct cpufreq_freqs *freq = data;
3068 struct kvm *kvm;
3069 struct kvm_vcpu *vcpu;
3070 int i, send_ipi = 0;
3071
3072 if (!ref_freq)
3073 ref_freq = freq->old;
3074
3075 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3076 return 0;
3077 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3078 return 0;
3079 per_cpu(cpu_tsc_khz, freq->cpu) = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
3080
3081 spin_lock(&kvm_lock);
3082 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3083 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3084 if (vcpu->cpu != freq->cpu)
3085 continue;
3086 if (!kvm_request_guest_time_update(vcpu))
3087 continue;
3088 if (vcpu->cpu != smp_processor_id())
3089 send_ipi++;
3090 }
3091 }
3092 spin_unlock(&kvm_lock);
3093
3094 if (freq->old < freq->new && send_ipi) {
3095 /*
3096 * We upscale the frequency. Must make the guest
3097 * doesn't see old kvmclock values while running with
3098 * the new frequency, otherwise we risk the guest sees
3099 * time go backwards.
3100 *
3101 * In case we update the frequency for another cpu
3102 * (which might be in guest context) send an interrupt
3103 * to kick the cpu out of guest context. Next time
3104 * guest context is entered kvmclock will be updated,
3105 * so the guest will not see stale values.
3106 */
3107 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3108 }
3109 return 0;
3110}
3111
3112static struct notifier_block kvmclock_cpufreq_notifier_block = {
3113 .notifier_call = kvmclock_cpufreq_notifier
3114};
3115
f8c16bba 3116int kvm_arch_init(void *opaque)
043405e1 3117{
c8076604 3118 int r, cpu;
f8c16bba
ZX		 3119 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3120
f8c16bba
ZX		 3121 if (kvm_x86_ops) {
3122 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 3123 r = -EEXIST;
3124 goto out;
f8c16bba
ZX		 3125 }
3126
3127 if (!ops->cpu_has_kvm_support()) {
3128 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 3129 r = -EOPNOTSUPP;
3130 goto out;
f8c16bba
ZX		 3131 }
3132 if (ops->disabled_by_bios()) {
3133 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 3134 r = -EOPNOTSUPP;
3135 goto out;
f8c16bba
ZX		 3136 }
3137
97db56ce
AK		 3138 r = kvm_mmu_module_init();
3139 if (r)
3140 goto out;
3141
3142 kvm_init_msr_list();
3143
f8c16bba 3144 kvm_x86_ops = ops;
56c6d28a 3145 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 3146 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3147 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 3148 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604
GH		 3149
3150 for_each_possible_cpu(cpu)
3151 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
3152 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
3153 tsc_khz_ref = tsc_khz;
3154 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3155 CPUFREQ_TRANSITION_NOTIFIER);
3156 }
3157
f8c16bba 3158 return 0;
56c6d28a
ZX		 3159
3160out:
56c6d28a 3161 return r;
043405e1 3162}
8776e519 3163
f8c16bba
ZX		 3164void kvm_arch_exit(void)
3165{
888d256e
JK		 3166 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3167 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3168 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 3169 kvm_x86_ops = NULL;
56c6d28a
ZX		 3170 kvm_mmu_module_exit();
3171}
f8c16bba 3172
8776e519
HB		 3173int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3174{
3175 ++vcpu->stat.halt_exits;
3176 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 3177 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 3178 return 1;
3179 } else {
3180 vcpu->run->exit_reason = KVM_EXIT_HLT;
3181 return 0;
3182 }
3183}
3184EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3185
2f333bcb
MT		 3186static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3187 unsigned long a1)
3188{
3189 if (is_long_mode(vcpu))
3190 return a0;
3191 else
3192 return a0 | ((gpa_t)a1 << 32);
3193}
3194
8776e519
HB		 3195int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3196{
3197 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 3198 int r = 1;
8776e519 3199
5fdbf976
MT		 3200 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3201 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3202 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3203 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3204 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 3205
229456fc 3206 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 3207
8776e519
HB		 3208 if (!is_long_mode(vcpu)) {
3209 nr &= 0xFFFFFFFF;
3210 a0 &= 0xFFFFFFFF;
3211 a1 &= 0xFFFFFFFF;
3212 a2 &= 0xFFFFFFFF;
3213 a3 &= 0xFFFFFFFF;
3214 }
3215
3216 switch (nr) {
b93463aa
AK		 3217 case KVM_HC_VAPIC_POLL_IRQ:
3218 ret = 0;
3219 break;
2f333bcb
MT		 3220 case KVM_HC_MMU_OP:
3221 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3222 break;
8776e519
HB		 3223 default:
3224 ret = -KVM_ENOSYS;
3225 break;
3226 }
5fdbf976 3227 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 3228 ++vcpu->stat.hypercalls;
2f333bcb 3229 return r;
8776e519
HB		 3230}
3231EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3232
3233int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3234{
3235 char instruction[3];
3236 int ret = 0;
5fdbf976 3237 unsigned long rip = kvm_rip_read(vcpu);
8776e519 3238
8776e519
HB		 3239
3240 /*
3241 * Blow out the MMU to ensure that no other VCPU has an active mapping
3242 * to ensure that the updated hypercall appears atomically across all
3243 * VCPUs.
3244 */
3245 kvm_mmu_zap_all(vcpu->kvm);
3246
8776e519 3247 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 3248 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 3249 != X86EMUL_CONTINUE)
3250 ret = -EFAULT;
3251
8776e519
HB		 3252 return ret;
3253}
3254
3255static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3256{
3257 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3258}
3259
3260void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3261{
3262 struct descriptor_table dt = { limit, base };
3263
3264 kvm_x86_ops->set_gdt(vcpu, &dt);
3265}
3266
3267void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3268{
3269 struct descriptor_table dt = { limit, base };
3270
3271 kvm_x86_ops->set_idt(vcpu, &dt);
3272}
3273
3274void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
3275 unsigned long *rflags)
3276{
2d3ad1f4 3277 kvm_lmsw(vcpu, msw);
8776e519
HB		 3278 *rflags = kvm_x86_ops->get_rflags(vcpu);
3279}
3280
3281unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3282{
54e445ca
JR		 3283 unsigned long value;
3284
8776e519
HB		 3285 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3286 switch (cr) {
3287 case 0:
54e445ca
JR		 3288 value = vcpu->arch.cr0;
3289 break;
8776e519 3290 case 2:
54e445ca
JR		 3291 value = vcpu->arch.cr2;
3292 break;
8776e519 3293 case 3:
54e445ca
JR		 3294 value = vcpu->arch.cr3;
3295 break;
8776e519 3296 case 4:
54e445ca
JR		 3297 value = vcpu->arch.cr4;
3298 break;
152ff9be 3299 case 8:
54e445ca
JR		 3300 value = kvm_get_cr8(vcpu);
3301 break;
8776e519 3302 default:
b8688d51 3303 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3304 return 0;
3305 }
54e445ca
JR		 3306
3307 return value;
8776e519
HB		 3308}
3309
3310void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
3311 unsigned long *rflags)
3312{
3313 switch (cr) {
3314 case 0:
2d3ad1f4 3315 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 3316 *rflags = kvm_x86_ops->get_rflags(vcpu);
3317 break;
3318 case 2:
ad312c7c 3319 vcpu->arch.cr2 = val;
8776e519
HB		 3320 break;
3321 case 3:
2d3ad1f4 3322 kvm_set_cr3(vcpu, val);
8776e519
HB		 3323 break;
3324 case 4:
2d3ad1f4 3325 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 3326 break;
152ff9be 3327 case 8:
2d3ad1f4 3328 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 3329 break;
8776e519 3330 default:
b8688d51 3331 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3332 }
3333}
3334
07716717
DK		 3335static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
3336{
ad312c7c
ZX		 3337 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
3338 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 3339
3340 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
3341 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 3342 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 3343 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 3344 if (ej->function == e->function) {
3345 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
3346 return j;
3347 }
3348 }
3349 return 0; /* silence gcc, even though control never reaches here */
3350}
3351
3352/* find an entry with matching function, matching index (if needed), and that
3353 * should be read next (if it's stateful) */
3354static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
3355 u32 function, u32 index)
3356{
3357 if (e->function != function)
3358 return 0;
3359 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
3360 return 0;
3361 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 3362 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 3363 return 0;
3364 return 1;
3365}
3366
d8017474
AG		 3367struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
3368 u32 function, u32 index)
8776e519
HB		 3369{
3370 int i;
d8017474 3371 struct kvm_cpuid_entry2 *best = NULL;
8776e519 3372
ad312c7c 3373 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 3374 struct kvm_cpuid_entry2 *e;
3375
ad312c7c 3376 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 3377 if (is_matching_cpuid_entry(e, function, index)) {
3378 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
3379 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 3380 best = e;
3381 break;
3382 }
3383 /*
3384 * Both basic or both extended?
3385 */
3386 if (((e->function ^ function) & 0x80000000) == 0)
3387 if (!best || e->function > best->function)
3388 best = e;
3389 }
d8017474
AG		 3390 return best;
3391}
3392
82725b20
DE		 3393int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
3394{
3395 struct kvm_cpuid_entry2 *best;
3396
3397 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
3398 if (best)
3399 return best->eax & 0xff;
3400 return 36;
3401}
3402
d8017474
AG		 3403void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
3404{
3405 u32 function, index;
3406 struct kvm_cpuid_entry2 *best;
3407
3408 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
3409 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3410 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
3411 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
3412 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
3413 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
3414 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 3415 if (best) {
5fdbf976
MT		 3416 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
3417 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
3418 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
3419 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 3420 }
8776e519 3421 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 3422 trace_kvm_cpuid(function,
3423 kvm_register_read(vcpu, VCPU_REGS_RAX),
3424 kvm_register_read(vcpu, VCPU_REGS_RBX),
3425 kvm_register_read(vcpu, VCPU_REGS_RCX),
3426 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 3427}
3428EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 3429
b6c7a5dc
HB		 3430/*
3431 * Check if userspace requested an interrupt window, and that the
3432 * interrupt window is open.
3433 *
3434 * No need to exit to userspace if we already have an interrupt queued.
3435 */
3436static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
3437 struct kvm_run *kvm_run)
3438{
8061823a 3439 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
b6c7a5dc 3440 kvm_run->request_interrupt_window &&
5df56646 3441 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 3442}
3443
3444static void post_kvm_run_save(struct kvm_vcpu *vcpu,
3445 struct kvm_run *kvm_run)
3446{
3447 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 3448 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 3449 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 3450 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3451 kvm_run->ready_for_interrupt_injection = 1;
4531220b 3452 else
b6c7a5dc 3453 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 3454 kvm_arch_interrupt_allowed(vcpu) &&
3455 !kvm_cpu_has_interrupt(vcpu) &&
3456 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 3457}
3458
b93463aa
AK		 3459static void vapic_enter(struct kvm_vcpu *vcpu)
3460{
3461 struct kvm_lapic *apic = vcpu->arch.apic;
3462 struct page *page;
3463
3464 if (!apic || !apic->vapic_addr)
3465 return;
3466
3467 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 3468
3469 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 3470}
3471
3472static void vapic_exit(struct kvm_vcpu *vcpu)
3473{
3474 struct kvm_lapic *apic = vcpu->arch.apic;
3475
3476 if (!apic || !apic->vapic_addr)
3477 return;
3478
f8b78fa3 3479 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3480 kvm_release_page_dirty(apic->vapic_page);
3481 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 3482 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3483}
3484
95ba8273
GN		 3485static void update_cr8_intercept(struct kvm_vcpu *vcpu)
3486{
3487 int max_irr, tpr;
3488
3489 if (!kvm_x86_ops->update_cr8_intercept)
3490 return;
3491
8db3baa2
GN		 3492 if (!vcpu->arch.apic->vapic_addr)
3493 max_irr = kvm_lapic_find_highest_irr(vcpu);
3494 else
3495 max_irr = -1;
95ba8273
GN		 3496
3497 if (max_irr != -1)
3498 max_irr >>= 4;
3499
3500 tpr = kvm_lapic_get_cr8(vcpu);
3501
3502 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
3503}
3504
b59bb7bd 3505static void inject_pending_event(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
95ba8273
GN		 3506{
3507 /* try to reinject previous events if any */
b59bb7bd
GN		 3508 if (vcpu->arch.exception.pending) {
3509 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
3510 vcpu->arch.exception.has_error_code,
3511 vcpu->arch.exception.error_code);
3512 return;
3513 }
3514
95ba8273
GN		 3515 if (vcpu->arch.nmi_injected) {
3516 kvm_x86_ops->set_nmi(vcpu);
3517 return;
3518 }
3519
3520 if (vcpu->arch.interrupt.pending) {
66fd3f7f 3521 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3522 return;
3523 }
3524
3525 /* try to inject new event if pending */
3526 if (vcpu->arch.nmi_pending) {
3527 if (kvm_x86_ops->nmi_allowed(vcpu)) {
3528 vcpu->arch.nmi_pending = false;
3529 vcpu->arch.nmi_injected = true;
3530 kvm_x86_ops->set_nmi(vcpu);
3531 }
3532 } else if (kvm_cpu_has_interrupt(vcpu)) {
3533 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 3534 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
3535 false);
3536 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3537 }
3538 }
3539}
3540
d7690175 3541static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
b6c7a5dc
HB		 3542{
3543 int r;
6a8b1d13
GN		 3544 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
3545 kvm_run->request_interrupt_window;
b6c7a5dc 3546
2e53d63a
MT		 3547 if (vcpu->requests)
3548 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
3549 kvm_mmu_unload(vcpu);
3550
b6c7a5dc
HB		 3551 r = kvm_mmu_reload(vcpu);
3552 if (unlikely(r))
3553 goto out;
3554
2f52d58c
AK		 3555 if (vcpu->requests) {
3556 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 3557 __kvm_migrate_timers(vcpu);
c8076604
GH		 3558 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
3559 kvm_write_guest_time(vcpu);
4731d4c7
MT		 3560 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
3561 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 3562 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
3563 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 3564 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
3565 &vcpu->requests)) {
3566 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
3567 r = 0;
3568 goto out;
3569 }
71c4dfaf
JR		 3570 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
3571 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
3572 r = 0;
3573 goto out;
3574 }
2f52d58c 3575 }
b93463aa 3576
b6c7a5dc
HB		 3577 preempt_disable();
3578
3579 kvm_x86_ops->prepare_guest_switch(vcpu);
3580 kvm_load_guest_fpu(vcpu);
3581
3582 local_irq_disable();
3583
32f88400
MT		 3584 clear_bit(KVM_REQ_KICK, &vcpu->requests);
3585 smp_mb__after_clear_bit();
3586
d7690175 3587 if (vcpu->requests || need_resched() || signal_pending(current)) {
c7f0f24b 3588 set_bit(KVM_REQ_KICK, &vcpu->requests);
6c142801
AK		 3589 local_irq_enable();
3590 preempt_enable();
3591 r = 1;
3592 goto out;
3593 }
3594
b59bb7bd 3595 inject_pending_event(vcpu, kvm_run);
b6c7a5dc 3596
6a8b1d13
GN		 3597 /* enable NMI/IRQ window open exits if needed */
3598 if (vcpu->arch.nmi_pending)
3599 kvm_x86_ops->enable_nmi_window(vcpu);
3600 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
3601 kvm_x86_ops->enable_irq_window(vcpu);
3602
95ba8273 3603 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 3604 update_cr8_intercept(vcpu);
3605 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 3606 }
b93463aa 3607
3200f405
MT		 3608 up_read(&vcpu->kvm->slots_lock);
3609
b6c7a5dc
HB		 3610 kvm_guest_enter();
3611
42dbaa5a
JK		 3612 get_debugreg(vcpu->arch.host_dr6, 6);
3613 get_debugreg(vcpu->arch.host_dr7, 7);
3614 if (unlikely(vcpu->arch.switch_db_regs)) {
3615 get_debugreg(vcpu->arch.host_db[0], 0);
3616 get_debugreg(vcpu->arch.host_db[1], 1);
3617 get_debugreg(vcpu->arch.host_db[2], 2);
3618 get_debugreg(vcpu->arch.host_db[3], 3);
3619
3620 set_debugreg(0, 7);
3621 set_debugreg(vcpu->arch.eff_db[0], 0);
3622 set_debugreg(vcpu->arch.eff_db[1], 1);
3623 set_debugreg(vcpu->arch.eff_db[2], 2);
3624 set_debugreg(vcpu->arch.eff_db[3], 3);
3625 }
b6c7a5dc 3626
229456fc 3627 trace_kvm_entry(vcpu->vcpu_id);
b6c7a5dc
HB		 3628 kvm_x86_ops->run(vcpu, kvm_run);
3629
42dbaa5a
JK		 3630 if (unlikely(vcpu->arch.switch_db_regs)) {
3631 set_debugreg(0, 7);
3632 set_debugreg(vcpu->arch.host_db[0], 0);
3633 set_debugreg(vcpu->arch.host_db[1], 1);
3634 set_debugreg(vcpu->arch.host_db[2], 2);
3635 set_debugreg(vcpu->arch.host_db[3], 3);
3636 }
3637 set_debugreg(vcpu->arch.host_dr6, 6);
3638 set_debugreg(vcpu->arch.host_dr7, 7);
3639
32f88400 3640 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 3641 local_irq_enable();
3642
3643 ++vcpu->stat.exits;
3644
3645 /*
3646 * We must have an instruction between local_irq_enable() and
3647 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3648 * the interrupt shadow. The stat.exits increment will do nicely.
3649 * But we need to prevent reordering, hence this barrier():
3650 */
3651 barrier();
3652
3653 kvm_guest_exit();
3654
3655 preempt_enable();
3656
3200f405
MT		 3657 down_read(&vcpu->kvm->slots_lock);
3658
b6c7a5dc
HB		 3659 /*
3660 * Profile KVM exit RIPs:
3661 */
3662 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 3663 unsigned long rip = kvm_rip_read(vcpu);
3664 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 3665 }
3666
298101da 3667
b93463aa
AK		 3668 kvm_lapic_sync_from_vapic(vcpu);
3669
b6c7a5dc 3670 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
d7690175
MT		 3671out:
3672 return r;
3673}
b6c7a5dc 3674
09cec754 3675
d7690175
MT		 3676static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3677{
3678 int r;
3679
3680 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 3681 pr_debug("vcpu %d received sipi with vector # %x\n",
3682 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 3683 kvm_lapic_reset(vcpu);
5f179287 3684 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 3685 if (r)
3686 return r;
3687 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 3688 }
3689
d7690175
MT		 3690 down_read(&vcpu->kvm->slots_lock);
3691 vapic_enter(vcpu);
3692
3693 r = 1;
3694 while (r > 0) {
af2152f5 3695 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
d7690175
MT		 3696 r = vcpu_enter_guest(vcpu, kvm_run);
3697 else {
3698 up_read(&vcpu->kvm->slots_lock);
3699 kvm_vcpu_block(vcpu);
3700 down_read(&vcpu->kvm->slots_lock);
3701 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 3702 {
3703 switch(vcpu->arch.mp_state) {
3704 case KVM_MP_STATE_HALTED:
d7690175 3705 vcpu->arch.mp_state =
09cec754
GN		 3706 KVM_MP_STATE_RUNNABLE;
3707 case KVM_MP_STATE_RUNNABLE:
3708 break;
3709 case KVM_MP_STATE_SIPI_RECEIVED:
3710 default:
3711 r = -EINTR;
3712 break;
3713 }
3714 }
d7690175
MT		 3715 }
3716
09cec754
GN		 3717 if (r <= 0)
3718 break;
3719
3720 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
3721 if (kvm_cpu_has_pending_timer(vcpu))
3722 kvm_inject_pending_timer_irqs(vcpu);
3723
3724 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
3725 r = -EINTR;
3726 kvm_run->exit_reason = KVM_EXIT_INTR;
3727 ++vcpu->stat.request_irq_exits;
3728 }
3729 if (signal_pending(current)) {
3730 r = -EINTR;
3731 kvm_run->exit_reason = KVM_EXIT_INTR;
3732 ++vcpu->stat.signal_exits;
3733 }
3734 if (need_resched()) {
3735 up_read(&vcpu->kvm->slots_lock);
3736 kvm_resched(vcpu);
3737 down_read(&vcpu->kvm->slots_lock);
d7690175 3738 }
b6c7a5dc
HB		 3739 }
3740
d7690175 3741 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3742 post_kvm_run_save(vcpu, kvm_run);
3743
b93463aa
AK		 3744 vapic_exit(vcpu);
3745
b6c7a5dc
HB		 3746 return r;
3747}
3748
3749int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3750{
3751 int r;
3752 sigset_t sigsaved;
3753
3754 vcpu_load(vcpu);
3755
ac9f6dc0
AK		 3756 if (vcpu->sigset_active)
3757 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
3758
a4535290 3759 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 3760 kvm_vcpu_block(vcpu);
d7690175 3761 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 3762 r = -EAGAIN;
3763 goto out;
b6c7a5dc
HB		 3764 }
3765
b6c7a5dc
HB		 3766 /* re-sync apic's tpr */
3767 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 3768 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 3769
ad312c7c 3770 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 3771 r = complete_pio(vcpu);
3772 if (r)
3773 goto out;
3774 }
3775#if CONFIG_HAS_IOMEM
3776 if (vcpu->mmio_needed) {
3777 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3778 vcpu->mmio_read_completed = 1;
3779 vcpu->mmio_needed = 0;
3200f405
MT		 3780
3781 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc 3782 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 3783 vcpu->arch.mmio_fault_cr2, 0,
3784 EMULTYPE_NO_DECODE);
3200f405 3785 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3786 if (r == EMULATE_DO_MMIO) {
3787 /*
3788 * Read-modify-write. Back to userspace.
3789 */
3790 r = 0;
3791 goto out;
3792 }
3793 }
3794#endif
5fdbf976
MT		 3795 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3796 kvm_register_write(vcpu, VCPU_REGS_RAX,
3797 kvm_run->hypercall.ret);
b6c7a5dc
HB		 3798
3799 r = __vcpu_run(vcpu, kvm_run);
3800
3801out:
3802 if (vcpu->sigset_active)
3803 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3804
3805 vcpu_put(vcpu);
3806 return r;
3807}
3808
3809int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3810{
3811 vcpu_load(vcpu);
3812
5fdbf976
MT		 3813 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3814 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3815 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3816 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3817 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3818 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3819 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3820 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 3821#ifdef CONFIG_X86_64
5fdbf976
MT		 3822 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3823 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3824 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3825 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3826 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3827 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3828 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3829 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 3830#endif
3831
5fdbf976 3832 regs->rip = kvm_rip_read(vcpu);
b6c7a5dc
HB		 3833 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3834
3835 /*
3836 * Don't leak debug flags in case they were set for guest debugging
3837 */
d0bfb940 3838 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
b6c7a5dc
HB		 3839 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3840
3841 vcpu_put(vcpu);
3842
3843 return 0;
3844}
3845
3846int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3847{
3848 vcpu_load(vcpu);
3849
5fdbf976
MT		 3850 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3851 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3852 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3853 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3854 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3855 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3856 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3857 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 3858#ifdef CONFIG_X86_64
5fdbf976
MT		 3859 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3860 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3861 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3862 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3863 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3864 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3865 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3866 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
3867
b6c7a5dc
HB		 3868#endif
3869
5fdbf976 3870 kvm_rip_write(vcpu, regs->rip);
b6c7a5dc
HB		 3871 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3872
b6c7a5dc 3873
b4f14abd
JK		 3874 vcpu->arch.exception.pending = false;
3875
b6c7a5dc
HB		 3876 vcpu_put(vcpu);
3877
3878 return 0;
3879}
3880
3e6e0aab
GT		 3881void kvm_get_segment(struct kvm_vcpu *vcpu,
3882 struct kvm_segment *var, int seg)
b6c7a5dc 3883{
14af3f3c 3884 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 3885}
3886
3887void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3888{
3889 struct kvm_segment cs;
3890
3e6e0aab 3891 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 3892 *db = cs.db;
3893 *l = cs.l;
3894}
3895EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3896
3897int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3898 struct kvm_sregs *sregs)
3899{
3900 struct descriptor_table dt;
b6c7a5dc
HB		 3901
3902 vcpu_load(vcpu);
3903
3e6e0aab
GT		 3904 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3905 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3906 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3907 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3908 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3909 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3910
3e6e0aab
GT		 3911 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3912 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3913
3914 kvm_x86_ops->get_idt(vcpu, &dt);
3915 sregs->idt.limit = dt.limit;
3916 sregs->idt.base = dt.base;
3917 kvm_x86_ops->get_gdt(vcpu, &dt);
3918 sregs->gdt.limit = dt.limit;
3919 sregs->gdt.base = dt.base;
3920
3921 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3922 sregs->cr0 = vcpu->arch.cr0;
3923 sregs->cr2 = vcpu->arch.cr2;
3924 sregs->cr3 = vcpu->arch.cr3;
3925 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3926 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3927 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3928 sregs->apic_base = kvm_get_apic_base(vcpu);
3929
923c61bb 3930 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 3931
36752c9b 3932 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 3933 set_bit(vcpu->arch.interrupt.nr,
3934 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 3935
b6c7a5dc
HB		 3936 vcpu_put(vcpu);
3937
3938 return 0;
3939}
3940
62d9f0db
MT		 3941int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3942 struct kvm_mp_state *mp_state)
3943{
3944 vcpu_load(vcpu);
3945 mp_state->mp_state = vcpu->arch.mp_state;
3946 vcpu_put(vcpu);
3947 return 0;
3948}
3949
3950int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3951 struct kvm_mp_state *mp_state)
3952{
3953 vcpu_load(vcpu);
3954 vcpu->arch.mp_state = mp_state->mp_state;
3955 vcpu_put(vcpu);
3956 return 0;
3957}
3958
3e6e0aab 3959static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 3960 struct kvm_segment *var, int seg)
3961{
14af3f3c 3962 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 3963}
3964
37817f29
IE		 3965static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3966 struct kvm_segment *kvm_desct)
3967{
46a359e7
AM		 3968 kvm_desct->base = get_desc_base(seg_desc);
3969 kvm_desct->limit = get_desc_limit(seg_desc);
c93cd3a5
MT		 3970 if (seg_desc->g) {
3971 kvm_desct->limit <<= 12;
3972 kvm_desct->limit |= 0xfff;
3973 }
37817f29
IE		 3974 kvm_desct->selector = selector;
3975 kvm_desct->type = seg_desc->type;
3976 kvm_desct->present = seg_desc->p;
3977 kvm_desct->dpl = seg_desc->dpl;
3978 kvm_desct->db = seg_desc->d;
3979 kvm_desct->s = seg_desc->s;
3980 kvm_desct->l = seg_desc->l;
3981 kvm_desct->g = seg_desc->g;
3982 kvm_desct->avl = seg_desc->avl;
3983 if (!selector)
3984 kvm_desct->unusable = 1;
3985 else
3986 kvm_desct->unusable = 0;
3987 kvm_desct->padding = 0;
3988}
3989
b8222ad2
AS		 3990static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
3991 u16 selector,
3992 struct descriptor_table *dtable)
37817f29
IE		 3993{
3994 if (selector & 1 << 2) {
3995 struct kvm_segment kvm_seg;
3996
3e6e0aab 3997 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 3998
3999 if (kvm_seg.unusable)
4000 dtable->limit = 0;
4001 else
4002 dtable->limit = kvm_seg.limit;
4003 dtable->base = kvm_seg.base;
4004 }
4005 else
4006 kvm_x86_ops->get_gdt(vcpu, dtable);
4007}
4008
4009/* allowed just for 8 bytes segments */
4010static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4011 struct desc_struct *seg_desc)
4012{
98899aa0 4013 gpa_t gpa;
37817f29
IE		 4014 struct descriptor_table dtable;
4015 u16 index = selector >> 3;
4016
b8222ad2 4017 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 4018
4019 if (dtable.limit < index * 8 + 7) {
4020 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
4021 return 1;
4022 }
98899aa0
MT		 4023 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
4024 gpa += index * 8;
4025 return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 4026}
4027
4028/* allowed just for 8 bytes segments */
4029static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4030 struct desc_struct *seg_desc)
4031{
98899aa0 4032 gpa_t gpa;
37817f29
IE		 4033 struct descriptor_table dtable;
4034 u16 index = selector >> 3;
4035
b8222ad2 4036 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 4037
4038 if (dtable.limit < index * 8 + 7)
4039 return 1;
98899aa0
MT		 4040 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
4041 gpa += index * 8;
4042 return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 4043}
4044
4045static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
4046 struct desc_struct *seg_desc)
4047{
46a359e7 4048 u32 base_addr = get_desc_base(seg_desc);
37817f29 4049
98899aa0 4050 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 4051}
4052
37817f29
IE		 4053static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
4054{
4055 struct kvm_segment kvm_seg;
4056
3e6e0aab 4057 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4058 return kvm_seg.selector;
4059}
4060
4061static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
4062 u16 selector,
4063 struct kvm_segment *kvm_seg)
4064{
4065 struct desc_struct seg_desc;
4066
4067 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
4068 return 1;
4069 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
4070 return 0;
4071}
4072
2259e3a7 4073static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 4074{
4075 struct kvm_segment segvar = {
4076 .base = selector << 4,
4077 .limit = 0xffff,
4078 .selector = selector,
4079 .type = 3,
4080 .present = 1,
4081 .dpl = 3,
4082 .db = 0,
4083 .s = 1,
4084 .l = 0,
4085 .g = 0,
4086 .avl = 0,
4087 .unusable = 0,
4088 };
4089 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
4090 return 0;
4091}
4092
3e6e0aab
GT		 4093int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4094 int type_bits, int seg)
37817f29
IE		 4095{
4096 struct kvm_segment kvm_seg;
4097
f4bbd9aa
AK		 4098 if (!(vcpu->arch.cr0 & X86_CR0_PE))
4099 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 4100 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
4101 return 1;
4102 kvm_seg.type |= type_bits;
4103
4104 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
4105 seg != VCPU_SREG_LDTR)
4106 if (!kvm_seg.s)
4107 kvm_seg.unusable = 1;
4108
3e6e0aab 4109 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4110 return 0;
4111}
4112
4113static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4114 struct tss_segment_32 *tss)
4115{
4116 tss->cr3 = vcpu->arch.cr3;
5fdbf976 4117 tss->eip = kvm_rip_read(vcpu);
37817f29 4118 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 4119 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4120 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4121 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4122 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4123 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4124 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4125 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4126 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4127 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4128 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4129 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4130 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4131 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4132 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4133 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4134}
4135
4136static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4137 struct tss_segment_32 *tss)
4138{
4139 kvm_set_cr3(vcpu, tss->cr3);
4140
5fdbf976 4141 kvm_rip_write(vcpu, tss->eip);
37817f29
IE		 4142 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
4143
5fdbf976
MT		 4144 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4145 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4146 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4147 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4148 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
4149 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
4150 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
4151 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 4152
3e6e0aab 4153 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 4154 return 1;
4155
3e6e0aab 4156 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4157 return 1;
4158
3e6e0aab 4159 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4160 return 1;
4161
3e6e0aab 4162 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4163 return 1;
4164
3e6e0aab 4165 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4166 return 1;
4167
3e6e0aab 4168 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 4169 return 1;
4170
3e6e0aab 4171 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 4172 return 1;
4173 return 0;
4174}
4175
4176static void save_state_to_tss16(struct kvm_vcpu *vcpu,
4177 struct tss_segment_16 *tss)
4178{
5fdbf976 4179 tss->ip = kvm_rip_read(vcpu);
37817f29 4180 tss->flag = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 4181 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4182 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4183 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4184 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4185 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4186 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4187 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
4188 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4189
4190 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4191 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4192 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4193 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4194 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
4195 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
4196}
4197
4198static int load_state_from_tss16(struct kvm_vcpu *vcpu,
4199 struct tss_segment_16 *tss)
4200{
5fdbf976 4201 kvm_rip_write(vcpu, tss->ip);
37817f29 4202 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 4203 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
4204 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
4205 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
4206 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
4207 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
4208 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
4209 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
4210 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 4211
3e6e0aab 4212 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 4213 return 1;
4214
3e6e0aab 4215 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4216 return 1;
4217
3e6e0aab 4218 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4219 return 1;
4220
3e6e0aab 4221 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4222 return 1;
4223
3e6e0aab 4224 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4225 return 1;
4226 return 0;
4227}
4228
8b2cf73c 4229static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37
GN		 4230 u16 old_tss_sel, u32 old_tss_base,
4231 struct desc_struct *nseg_desc)
37817f29
IE		 4232{
4233 struct tss_segment_16 tss_segment_16;
4234 int ret = 0;
4235
34198bf8
MT		 4236 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4237 sizeof tss_segment_16))
37817f29
IE		 4238 goto out;
4239
4240 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 4241
34198bf8
MT		 4242 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4243 sizeof tss_segment_16))
37817f29 4244 goto out;
34198bf8
MT		 4245
4246 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4247 &tss_segment_16, sizeof tss_segment_16))
4248 goto out;
4249
b237ac37
GN		 4250 if (old_tss_sel != 0xffff) {
4251 tss_segment_16.prev_task_link = old_tss_sel;
4252
4253 if (kvm_write_guest(vcpu->kvm,
4254 get_tss_base_addr(vcpu, nseg_desc),
4255 &tss_segment_16.prev_task_link,
4256 sizeof tss_segment_16.prev_task_link))
4257 goto out;
4258 }
4259
37817f29
IE		 4260 if (load_state_from_tss16(vcpu, &tss_segment_16))
4261 goto out;
4262
4263 ret = 1;
4264out:
4265 return ret;
4266}
4267
8b2cf73c 4268static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37 4269 u16 old_tss_sel, u32 old_tss_base,
37817f29
IE		 4270 struct desc_struct *nseg_desc)
4271{
4272 struct tss_segment_32 tss_segment_32;
4273 int ret = 0;
4274
34198bf8
MT		 4275 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4276 sizeof tss_segment_32))
37817f29
IE		 4277 goto out;
4278
4279 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 4280
34198bf8
MT		 4281 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4282 sizeof tss_segment_32))
4283 goto out;
4284
4285 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4286 &tss_segment_32, sizeof tss_segment_32))
37817f29 4287 goto out;
34198bf8 4288
b237ac37
GN		 4289 if (old_tss_sel != 0xffff) {
4290 tss_segment_32.prev_task_link = old_tss_sel;
4291
4292 if (kvm_write_guest(vcpu->kvm,
4293 get_tss_base_addr(vcpu, nseg_desc),
4294 &tss_segment_32.prev_task_link,
4295 sizeof tss_segment_32.prev_task_link))
4296 goto out;
4297 }
4298
37817f29
IE		 4299 if (load_state_from_tss32(vcpu, &tss_segment_32))
4300 goto out;
4301
4302 ret = 1;
4303out:
4304 return ret;
4305}
4306
4307int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
4308{
4309 struct kvm_segment tr_seg;
4310 struct desc_struct cseg_desc;
4311 struct desc_struct nseg_desc;
4312 int ret = 0;
34198bf8
MT		 4313 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
4314 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 4315
34198bf8 4316 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 4317
34198bf8
MT		 4318 /* FIXME: Handle errors. Failure to read either TSS or their
4319 * descriptors should generate a pagefault.
4320 */
37817f29
IE		 4321 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
4322 goto out;
4323
34198bf8 4324 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 4325 goto out;
4326
37817f29
IE		 4327 if (reason != TASK_SWITCH_IRET) {
4328 int cpl;
4329
4330 cpl = kvm_x86_ops->get_cpl(vcpu);
4331 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
4332 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
4333 return 1;
4334 }
4335 }
4336
46a359e7 4337 if (!nseg_desc.p || get_desc_limit(&nseg_desc) < 0x67) {
37817f29
IE		 4338 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
4339 return 1;
4340 }
4341
4342 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 4343 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 4344 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 4345 }
4346
4347 if (reason == TASK_SWITCH_IRET) {
4348 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4349 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
4350 }
4351
64a7ec06
GN		 4352 /* set back link to prev task only if NT bit is set in eflags
4353 note that old_tss_sel is not used afetr this point */
4354 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4355 old_tss_sel = 0xffff;
37817f29 4356
b237ac37
GN		 4357 /* set back link to prev task only if NT bit is set in eflags
4358 note that old_tss_sel is not used afetr this point */
4359 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4360 old_tss_sel = 0xffff;
4361
37817f29 4362 if (nseg_desc.type & 8)
b237ac37
GN		 4363 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
4364 old_tss_base, &nseg_desc);
37817f29 4365 else
b237ac37
GN		 4366 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
4367 old_tss_base, &nseg_desc);
37817f29
IE		 4368
4369 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
4370 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4371 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
4372 }
4373
4374 if (reason != TASK_SWITCH_IRET) {
3fe913e7 4375 nseg_desc.type |= (1 << 1);
37817f29
IE		 4376 save_guest_segment_descriptor(vcpu, tss_selector,
4377 &nseg_desc);
4378 }
4379
4380 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
4381 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
4382 tr_seg.type = 11;
3e6e0aab 4383 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 4384out:
37817f29
IE		 4385 return ret;
4386}
4387EXPORT_SYMBOL_GPL(kvm_task_switch);
4388
b6c7a5dc
HB		 4389int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4390 struct kvm_sregs *sregs)
4391{
4392 int mmu_reset_needed = 0;
923c61bb 4393 int pending_vec, max_bits;
b6c7a5dc
HB		 4394 struct descriptor_table dt;
4395
4396 vcpu_load(vcpu);
4397
4398 dt.limit = sregs->idt.limit;
4399 dt.base = sregs->idt.base;
4400 kvm_x86_ops->set_idt(vcpu, &dt);
4401 dt.limit = sregs->gdt.limit;
4402 dt.base = sregs->gdt.base;
4403 kvm_x86_ops->set_gdt(vcpu, &dt);
4404
ad312c7c
ZX		 4405 vcpu->arch.cr2 = sregs->cr2;
4406 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 4407 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 4408
2d3ad1f4 4409 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 4410
ad312c7c 4411 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 4412 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 4413 kvm_set_apic_base(vcpu, sregs->apic_base);
4414
4415 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
4416
ad312c7c 4417 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 4418 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 4419 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 4420
ad312c7c 4421 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 4422 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
4423 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 4424 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 4425
4426 if (mmu_reset_needed)
4427 kvm_mmu_reset_context(vcpu);
4428
923c61bb
GN		 4429 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4430 pending_vec = find_first_bit(
4431 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4432 if (pending_vec < max_bits) {
66fd3f7f 4433 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 4434 pr_debug("Set back pending irq %d\n", pending_vec);
4435 if (irqchip_in_kernel(vcpu->kvm))
4436 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 4437 }
4438
3e6e0aab
GT		 4439 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4440 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4441 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4442 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4443 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4444 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4445
3e6e0aab
GT		 4446 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4447 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 4448
5f0269f5
ME		 4449 update_cr8_intercept(vcpu);
4450
9c3e4aab 4451 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 4452 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab
MT		 4453 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
4454 !(vcpu->arch.cr0 & X86_CR0_PE))
4455 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4456
b6c7a5dc
HB		 4457 vcpu_put(vcpu);
4458
4459 return 0;
4460}
4461
d0bfb940
JK		 4462int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4463 struct kvm_guest_debug *dbg)
b6c7a5dc 4464{
ae675ef0 4465 int i, r;
b6c7a5dc
HB		 4466
4467 vcpu_load(vcpu);
4468
ae675ef0
JK		 4469 if ((dbg->control & (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) ==
4470 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) {
4471 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4472 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4473 vcpu->arch.switch_db_regs =
4474 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4475 } else {
4476 for (i = 0; i < KVM_NR_DB_REGS; i++)
4477 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4478 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4479 }
4480
b6c7a5dc
HB		 4481 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
4482
d0bfb940
JK		 4483 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
4484 kvm_queue_exception(vcpu, DB_VECTOR);
4485 else if (dbg->control & KVM_GUESTDBG_INJECT_BP)
4486 kvm_queue_exception(vcpu, BP_VECTOR);
4487
b6c7a5dc
HB		 4488 vcpu_put(vcpu);
4489
4490 return r;
4491}
4492
d0752060
HB		 4493/*
4494 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4495 * we have asm/x86/processor.h
4496 */
4497struct fxsave {
4498 u16 cwd;
4499 u16 swd;
4500 u16 twd;
4501 u16 fop;
4502 u64 rip;
4503 u64 rdp;
4504 u32 mxcsr;
4505 u32 mxcsr_mask;
4506 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
4507#ifdef CONFIG_X86_64
4508 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
4509#else
4510 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
4511#endif
4512};
4513
8b006791
ZX		 4514/*
4515 * Translate a guest virtual address to a guest physical address.
4516 */
4517int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
4518 struct kvm_translation *tr)
4519{
4520 unsigned long vaddr = tr->linear_address;
4521 gpa_t gpa;
4522
4523 vcpu_load(vcpu);
72dc67a6 4524 down_read(&vcpu->kvm->slots_lock);
ad312c7c 4525 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 4526 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 4527 tr->physical_address = gpa;
4528 tr->valid = gpa != UNMAPPED_GVA;
4529 tr->writeable = 1;
4530 tr->usermode = 0;
8b006791
ZX		 4531 vcpu_put(vcpu);
4532
4533 return 0;
4534}
4535
d0752060
HB		 4536int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4537{
ad312c7c 4538 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4539
4540 vcpu_load(vcpu);
4541
4542 memcpy(fpu->fpr, fxsave->st_space, 128);
4543 fpu->fcw = fxsave->cwd;
4544 fpu->fsw = fxsave->swd;
4545 fpu->ftwx = fxsave->twd;
4546 fpu->last_opcode = fxsave->fop;
4547 fpu->last_ip = fxsave->rip;
4548 fpu->last_dp = fxsave->rdp;
4549 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
4550
4551 vcpu_put(vcpu);
4552
4553 return 0;
4554}
4555
4556int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4557{
ad312c7c 4558 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4559
4560 vcpu_load(vcpu);
4561
4562 memcpy(fxsave->st_space, fpu->fpr, 128);
4563 fxsave->cwd = fpu->fcw;
4564 fxsave->swd = fpu->fsw;
4565 fxsave->twd = fpu->ftwx;
4566 fxsave->fop = fpu->last_opcode;
4567 fxsave->rip = fpu->last_ip;
4568 fxsave->rdp = fpu->last_dp;
4569 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
4570
4571 vcpu_put(vcpu);
4572
4573 return 0;
4574}
4575
4576void fx_init(struct kvm_vcpu *vcpu)
4577{
4578 unsigned after_mxcsr_mask;
4579
bc1a34f1
AA		 4580 /*
4581 * Touch the fpu the first time in non atomic context as if
4582 * this is the first fpu instruction the exception handler
4583 * will fire before the instruction returns and it'll have to
4584 * allocate ram with GFP_KERNEL.
4585 */
4586 if (!used_math())
d6e88aec 4587 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 4588
d0752060
HB		 4589 /* Initialize guest FPU by resetting ours and saving into guest's */
4590 preempt_disable();
d6e88aec
AK		 4591 kvm_fx_save(&vcpu->arch.host_fx_image);
4592 kvm_fx_finit();
4593 kvm_fx_save(&vcpu->arch.guest_fx_image);
4594 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 4595 preempt_enable();
4596
ad312c7c 4597 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 4598 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 4599 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
4600 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 4601 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
4602}
4603EXPORT_SYMBOL_GPL(fx_init);
4604
4605void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
4606{
4607 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
4608 return;
4609
4610 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 4611 kvm_fx_save(&vcpu->arch.host_fx_image);
4612 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 4613}
4614EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
4615
4616void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
4617{
4618 if (!vcpu->guest_fpu_loaded)
4619 return;
4620
4621 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 4622 kvm_fx_save(&vcpu->arch.guest_fx_image);
4623 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 4624 ++vcpu->stat.fpu_reload;
d0752060
HB		 4625}
4626EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 4627
4628void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
4629{
7f1ea208
JR		 4630 if (vcpu->arch.time_page) {
4631 kvm_release_page_dirty(vcpu->arch.time_page);
4632 vcpu->arch.time_page = NULL;
4633 }
4634
e9b11c17
ZX		 4635 kvm_x86_ops->vcpu_free(vcpu);
4636}
4637
4638struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
4639 unsigned int id)
4640{
26e5215f
AK		 4641 return kvm_x86_ops->vcpu_create(kvm, id);
4642}
e9b11c17 4643
26e5215f
AK		 4644int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
4645{
4646 int r;
e9b11c17
ZX		 4647
4648 /* We do fxsave: this must be aligned. */
ad312c7c 4649 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 4650
0bed3b56 4651 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 4652 vcpu_load(vcpu);
4653 r = kvm_arch_vcpu_reset(vcpu);
4654 if (r == 0)
4655 r = kvm_mmu_setup(vcpu);
4656 vcpu_put(vcpu);
4657 if (r < 0)
4658 goto free_vcpu;
4659
26e5215f 4660 return 0;
e9b11c17
ZX		 4661free_vcpu:
4662 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 4663 return r;
e9b11c17
ZX		 4664}
4665
d40ccc62 4666void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 4667{
4668 vcpu_load(vcpu);
4669 kvm_mmu_unload(vcpu);
4670 vcpu_put(vcpu);
4671
4672 kvm_x86_ops->vcpu_free(vcpu);
4673}
4674
4675int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4676{
448fa4a9
JK		 4677 vcpu->arch.nmi_pending = false;
4678 vcpu->arch.nmi_injected = false;
4679
42dbaa5a
JK		 4680 vcpu->arch.switch_db_regs = 0;
4681 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
4682 vcpu->arch.dr6 = DR6_FIXED_1;
4683 vcpu->arch.dr7 = DR7_FIXED_1;
4684
e9b11c17
ZX		 4685 return kvm_x86_ops->vcpu_reset(vcpu);
4686}
4687
4688void kvm_arch_hardware_enable(void *garbage)
4689{
4690 kvm_x86_ops->hardware_enable(garbage);
4691}
4692
4693void kvm_arch_hardware_disable(void *garbage)
4694{
4695 kvm_x86_ops->hardware_disable(garbage);
4696}
4697
4698int kvm_arch_hardware_setup(void)
4699{
4700 return kvm_x86_ops->hardware_setup();
4701}
4702
4703void kvm_arch_hardware_unsetup(void)
4704{
4705 kvm_x86_ops->hardware_unsetup();
4706}
4707
4708void kvm_arch_check_processor_compat(void *rtn)
4709{
4710 kvm_x86_ops->check_processor_compatibility(rtn);
4711}
4712
4713int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
4714{
4715 struct page *page;
4716 struct kvm *kvm;
4717 int r;
4718
4719 BUG_ON(vcpu->kvm == NULL);
4720 kvm = vcpu->kvm;
4721
ad312c7c 4722 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 4723 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 4724 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 4725 else
a4535290 4726 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 4727
4728 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
4729 if (!page) {
4730 r = -ENOMEM;
4731 goto fail;
4732 }
ad312c7c 4733 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 4734
4735 r = kvm_mmu_create(vcpu);
4736 if (r < 0)
4737 goto fail_free_pio_data;
4738
4739 if (irqchip_in_kernel(kvm)) {
4740 r = kvm_create_lapic(vcpu);
4741 if (r < 0)
4742 goto fail_mmu_destroy;
4743 }
4744
890ca9ae
HY		 4745 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
4746 GFP_KERNEL);
4747 if (!vcpu->arch.mce_banks) {
4748 r = -ENOMEM;
4749 goto fail_mmu_destroy;
4750 }
4751 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
4752
e9b11c17
ZX		 4753 return 0;
4754
4755fail_mmu_destroy:
4756 kvm_mmu_destroy(vcpu);
4757fail_free_pio_data:
ad312c7c 4758 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 4759fail:
4760 return r;
4761}
4762
4763void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
4764{
4765 kvm_free_lapic(vcpu);
3200f405 4766 down_read(&vcpu->kvm->slots_lock);
e9b11c17 4767 kvm_mmu_destroy(vcpu);
3200f405 4768 up_read(&vcpu->kvm->slots_lock);
ad312c7c 4769 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 4770}
d19a9cd2
ZX		 4771
4772struct kvm *kvm_arch_create_vm(void)
4773{
4774 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
4775
4776 if (!kvm)
4777 return ERR_PTR(-ENOMEM);
4778
f05e70ac 4779 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 4780 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 4781
5550af4d
SY		 4782 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
4783 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
4784
53f658b3
MT		 4785 rdtscll(kvm->arch.vm_init_tsc);
4786
d19a9cd2
ZX		 4787 return kvm;
4788}
4789
4790static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
4791{
4792 vcpu_load(vcpu);
4793 kvm_mmu_unload(vcpu);
4794 vcpu_put(vcpu);
4795}
4796
4797static void kvm_free_vcpus(struct kvm *kvm)
4798{
4799 unsigned int i;
988a2cae 4800 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 4801
4802 /*
4803 * Unpin any mmu pages first.
4804 */
988a2cae
GN		 4805 kvm_for_each_vcpu(i, vcpu, kvm)
4806 kvm_unload_vcpu_mmu(vcpu);
4807 kvm_for_each_vcpu(i, vcpu, kvm)
4808 kvm_arch_vcpu_free(vcpu);
4809
4810 mutex_lock(&kvm->lock);
4811 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
4812 kvm->vcpus[i] = NULL;
d19a9cd2 4813
988a2cae
GN		 4814 atomic_set(&kvm->online_vcpus, 0);
4815 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 4816}
4817
ad8ba2cd
SY		 4818void kvm_arch_sync_events(struct kvm *kvm)
4819{
ba4cef31 4820 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 4821}
4822
d19a9cd2
ZX		 4823void kvm_arch_destroy_vm(struct kvm *kvm)
4824{
6eb55818 4825 kvm_iommu_unmap_guest(kvm);
7837699f 4826 kvm_free_pit(kvm);
d7deeeb0
ZX		 4827 kfree(kvm->arch.vpic);
4828 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 4829 kvm_free_vcpus(kvm);
4830 kvm_free_physmem(kvm);
3d45830c
AK		 4831 if (kvm->arch.apic_access_page)
4832 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 4833 if (kvm->arch.ept_identity_pagetable)
4834 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 4835 kfree(kvm);
4836}
0de10343
ZX		 4837
4838int kvm_arch_set_memory_region(struct kvm *kvm,
4839 struct kvm_userspace_memory_region *mem,
4840 struct kvm_memory_slot old,
4841 int user_alloc)
4842{
4843 int npages = mem->memory_size >> PAGE_SHIFT;
4844 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
4845
4846 /*To keep backward compatibility with older userspace,
4847 *x86 needs to hanlde !user_alloc case.
4848 */
4849 if (!user_alloc) {
4850 if (npages && !old.rmap) {
604b38ac
AA		 4851 unsigned long userspace_addr;
4852
72dc67a6 4853 down_write(&current->mm->mmap_sem);
604b38ac
AA		 4854 userspace_addr = do_mmap(NULL, 0,
4855 npages * PAGE_SIZE,
4856 PROT_READ | PROT_WRITE,
acee3c04 4857 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 4858 0);
72dc67a6 4859 up_write(&current->mm->mmap_sem);
0de10343 4860
604b38ac
AA		 4861 if (IS_ERR((void *)userspace_addr))
4862 return PTR_ERR((void *)userspace_addr);
4863
4864 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4865 spin_lock(&kvm->mmu_lock);
4866 memslot->userspace_addr = userspace_addr;
4867 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4868 } else {
4869 if (!old.user_alloc && old.rmap) {
4870 int ret;
4871
72dc67a6 4872 down_write(&current->mm->mmap_sem);
0de10343
ZX		 4873 ret = do_munmap(current->mm, old.userspace_addr,
4874 old.npages * PAGE_SIZE);
72dc67a6 4875 up_write(&current->mm->mmap_sem);
0de10343
ZX		 4876 if (ret < 0)
4877 printk(KERN_WARNING
4878 "kvm_vm_ioctl_set_memory_region: "
4879 "failed to munmap memory\n");
4880 }
4881 }
4882 }
4883
7c8a83b7 4884 spin_lock(&kvm->mmu_lock);
f05e70ac 4885 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 4886 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4887 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4888 }
4889
4890 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 4891 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4892 kvm_flush_remote_tlbs(kvm);
4893
4894 return 0;
4895}
1d737c8a 4896
34d4cb8f
MT		 4897void kvm_arch_flush_shadow(struct kvm *kvm)
4898{
4899 kvm_mmu_zap_all(kvm);
8986ecc0 4900 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 4901}
4902
1d737c8a
ZX		 4903int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4904{
a4535290 4905 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 4906 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
4907 || vcpu->arch.nmi_pending ||
4908 (kvm_arch_interrupt_allowed(vcpu) &&
4909 kvm_cpu_has_interrupt(vcpu));
1d737c8a 4910}
5736199a 4911
5736199a
ZX		 4912void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4913{
32f88400
MT		 4914 int me;
4915 int cpu = vcpu->cpu;
5736199a
ZX		 4916
4917 if (waitqueue_active(&vcpu->wq)) {
4918 wake_up_interruptible(&vcpu->wq);
4919 ++vcpu->stat.halt_wakeup;
4920 }
32f88400
MT		 4921
4922 me = get_cpu();
4923 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
4924 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
4925 smp_send_reschedule(cpu);
e9571ed5 4926 put_cpu();
5736199a 4927}
78646121
GN		 4928
4929int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
4930{
4931 return kvm_x86_ops->interrupt_allowed(vcpu);
4932}
229456fc
MT		 4933
4934EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
4935EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
4936EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
4937EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
4938EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
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