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20c8ccb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
043405e1 CO |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * | |
5 | * derived from drivers/kvm/kvm_main.c | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
8 | * Copyright (C) 2008 Qumranet, Inc. |
9 | * Copyright IBM Corporation, 2008 | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
043405e1 CO |
11 | * |
12 | * Authors: | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
15 | * Amit Shah <amit.shah@qumranet.com> |
16 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
17 | */ |
18 | ||
edf88417 | 19 | #include <linux/kvm_host.h> |
313a3dc7 | 20 | #include "irq.h" |
88197e6a | 21 | #include "ioapic.h" |
1d737c8a | 22 | #include "mmu.h" |
7837699f | 23 | #include "i8254.h" |
37817f29 | 24 | #include "tss.h" |
5fdbf976 | 25 | #include "kvm_cache_regs.h" |
2f728d66 | 26 | #include "kvm_emulate.h" |
26eef70c | 27 | #include "x86.h" |
00b27a3e | 28 | #include "cpuid.h" |
474a5bb9 | 29 | #include "pmu.h" |
e83d5887 | 30 | #include "hyperv.h" |
8df14af4 | 31 | #include "lapic.h" |
313a3dc7 | 32 | |
18068523 | 33 | #include <linux/clocksource.h> |
4d5c5d0f | 34 | #include <linux/interrupt.h> |
313a3dc7 CO |
35 | #include <linux/kvm.h> |
36 | #include <linux/fs.h> | |
37 | #include <linux/vmalloc.h> | |
1767e931 PG |
38 | #include <linux/export.h> |
39 | #include <linux/moduleparam.h> | |
0de10343 | 40 | #include <linux/mman.h> |
2bacc55c | 41 | #include <linux/highmem.h> |
19de40a8 | 42 | #include <linux/iommu.h> |
62c476c7 | 43 | #include <linux/intel-iommu.h> |
c8076604 | 44 | #include <linux/cpufreq.h> |
18863bdd | 45 | #include <linux/user-return-notifier.h> |
a983fb23 | 46 | #include <linux/srcu.h> |
5a0e3ad6 | 47 | #include <linux/slab.h> |
ff9d07a0 | 48 | #include <linux/perf_event.h> |
7bee342a | 49 | #include <linux/uaccess.h> |
af585b92 | 50 | #include <linux/hash.h> |
a1b60c1c | 51 | #include <linux/pci.h> |
16e8d74d MT |
52 | #include <linux/timekeeper_internal.h> |
53 | #include <linux/pvclock_gtod.h> | |
87276880 FW |
54 | #include <linux/kvm_irqfd.h> |
55 | #include <linux/irqbypass.h> | |
3905f9ad | 56 | #include <linux/sched/stat.h> |
0c5f81da | 57 | #include <linux/sched/isolation.h> |
d0ec49d4 | 58 | #include <linux/mem_encrypt.h> |
72c3c0fe | 59 | #include <linux/entry-kvm.h> |
3905f9ad | 60 | |
aec51dc4 | 61 | #include <trace/events/kvm.h> |
2ed152af | 62 | |
24f1e32c | 63 | #include <asm/debugreg.h> |
d825ed0a | 64 | #include <asm/msr.h> |
a5f61300 | 65 | #include <asm/desc.h> |
890ca9ae | 66 | #include <asm/mce.h> |
f89e32e0 | 67 | #include <linux/kernel_stat.h> |
78f7f1e5 | 68 | #include <asm/fpu/internal.h> /* Ugh! */ |
1d5f066e | 69 | #include <asm/pvclock.h> |
217fc9cf | 70 | #include <asm/div64.h> |
efc64404 | 71 | #include <asm/irq_remapping.h> |
b0c39dc6 | 72 | #include <asm/mshyperv.h> |
0092e434 | 73 | #include <asm/hypervisor.h> |
9715092f | 74 | #include <asm/tlbflush.h> |
bf8c55d8 | 75 | #include <asm/intel_pt.h> |
b3dc0695 | 76 | #include <asm/emulate_prefix.h> |
dd2cb348 | 77 | #include <clocksource/hyperv_timer.h> |
043405e1 | 78 | |
d1898b73 DH |
79 | #define CREATE_TRACE_POINTS |
80 | #include "trace.h" | |
81 | ||
313a3dc7 | 82 | #define MAX_IO_MSRS 256 |
890ca9ae | 83 | #define KVM_MAX_MCE_BANKS 32 |
c45dcc71 AR |
84 | u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; |
85 | EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); | |
890ca9ae | 86 | |
0f65dd70 | 87 | #define emul_to_vcpu(ctxt) \ |
c9b8b07c | 88 | ((struct kvm_vcpu *)(ctxt)->vcpu) |
0f65dd70 | 89 | |
50a37eb4 JR |
90 | /* EFER defaults: |
91 | * - enable syscall per default because its emulated by KVM | |
92 | * - enable LME and LMA per default on 64 bit KVM | |
93 | */ | |
94 | #ifdef CONFIG_X86_64 | |
1260edbe LJ |
95 | static |
96 | u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); | |
50a37eb4 | 97 | #else |
1260edbe | 98 | static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); |
50a37eb4 | 99 | #endif |
313a3dc7 | 100 | |
b11306b5 SC |
101 | static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; |
102 | ||
c519265f RK |
103 | #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ |
104 | KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) | |
37131313 | 105 | |
cb142eb7 | 106 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
7460fb4a | 107 | static void process_nmi(struct kvm_vcpu *vcpu); |
ee2cd4b7 | 108 | static void enter_smm(struct kvm_vcpu *vcpu); |
6addfc42 | 109 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); |
01643c51 KH |
110 | static void store_regs(struct kvm_vcpu *vcpu); |
111 | static int sync_regs(struct kvm_vcpu *vcpu); | |
674eea0f | 112 | |
afaf0b2f | 113 | struct kvm_x86_ops kvm_x86_ops __read_mostly; |
5fdbf976 | 114 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 115 | |
893590c7 | 116 | static bool __read_mostly ignore_msrs = 0; |
476bc001 | 117 | module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); |
ed85c068 | 118 | |
fab0aa3b EM |
119 | static bool __read_mostly report_ignored_msrs = true; |
120 | module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); | |
121 | ||
4c27625b | 122 | unsigned int min_timer_period_us = 200; |
9ed96e87 MT |
123 | module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); |
124 | ||
630994b3 MT |
125 | static bool __read_mostly kvmclock_periodic_sync = true; |
126 | module_param(kvmclock_periodic_sync, bool, S_IRUGO); | |
127 | ||
893590c7 | 128 | bool __read_mostly kvm_has_tsc_control; |
92a1f12d | 129 | EXPORT_SYMBOL_GPL(kvm_has_tsc_control); |
893590c7 | 130 | u32 __read_mostly kvm_max_guest_tsc_khz; |
92a1f12d | 131 | EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); |
bc9b961b HZ |
132 | u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; |
133 | EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); | |
134 | u64 __read_mostly kvm_max_tsc_scaling_ratio; | |
135 | EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); | |
64672c95 YJ |
136 | u64 __read_mostly kvm_default_tsc_scaling_ratio; |
137 | EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); | |
92a1f12d | 138 | |
cc578287 | 139 | /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ |
893590c7 | 140 | static u32 __read_mostly tsc_tolerance_ppm = 250; |
cc578287 ZA |
141 | module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); |
142 | ||
c3941d9e SC |
143 | /* |
144 | * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables | |
145 | * adaptive tuning starting from default advancment of 1000ns. '0' disables | |
146 | * advancement entirely. Any other value is used as-is and disables adaptive | |
147 | * tuning, i.e. allows priveleged userspace to set an exact advancement time. | |
148 | */ | |
149 | static int __read_mostly lapic_timer_advance_ns = -1; | |
0e6edceb | 150 | module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR); |
d0659d94 | 151 | |
52004014 FW |
152 | static bool __read_mostly vector_hashing = true; |
153 | module_param(vector_hashing, bool, S_IRUGO); | |
154 | ||
c4ae60e4 LA |
155 | bool __read_mostly enable_vmware_backdoor = false; |
156 | module_param(enable_vmware_backdoor, bool, S_IRUGO); | |
157 | EXPORT_SYMBOL_GPL(enable_vmware_backdoor); | |
158 | ||
6c86eedc WL |
159 | static bool __read_mostly force_emulation_prefix = false; |
160 | module_param(force_emulation_prefix, bool, S_IRUGO); | |
161 | ||
0c5f81da WL |
162 | int __read_mostly pi_inject_timer = -1; |
163 | module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); | |
164 | ||
7e34fbd0 SC |
165 | /* |
166 | * Restoring the host value for MSRs that are only consumed when running in | |
167 | * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU | |
168 | * returns to userspace, i.e. the kernel can run with the guest's value. | |
169 | */ | |
170 | #define KVM_MAX_NR_USER_RETURN_MSRS 16 | |
18863bdd | 171 | |
7e34fbd0 | 172 | struct kvm_user_return_msrs_global { |
18863bdd | 173 | int nr; |
7e34fbd0 | 174 | u32 msrs[KVM_MAX_NR_USER_RETURN_MSRS]; |
18863bdd AK |
175 | }; |
176 | ||
7e34fbd0 | 177 | struct kvm_user_return_msrs { |
18863bdd AK |
178 | struct user_return_notifier urn; |
179 | bool registered; | |
7e34fbd0 | 180 | struct kvm_user_return_msr_values { |
2bf78fa7 SY |
181 | u64 host; |
182 | u64 curr; | |
7e34fbd0 | 183 | } values[KVM_MAX_NR_USER_RETURN_MSRS]; |
18863bdd AK |
184 | }; |
185 | ||
7e34fbd0 SC |
186 | static struct kvm_user_return_msrs_global __read_mostly user_return_msrs_global; |
187 | static struct kvm_user_return_msrs __percpu *user_return_msrs; | |
18863bdd | 188 | |
cfc48181 SC |
189 | #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ |
190 | | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ | |
191 | | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ | |
192 | | XFEATURE_MASK_PKRU) | |
193 | ||
91661989 SC |
194 | u64 __read_mostly host_efer; |
195 | EXPORT_SYMBOL_GPL(host_efer); | |
196 | ||
b96e6506 | 197 | bool __read_mostly allow_smaller_maxphyaddr = 0; |
3edd6839 MG |
198 | EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr); |
199 | ||
139a12cf | 200 | static u64 __read_mostly host_xss; |
408e9a31 PB |
201 | u64 __read_mostly supported_xss; |
202 | EXPORT_SYMBOL_GPL(supported_xss); | |
139a12cf | 203 | |
417bc304 | 204 | struct kvm_stats_debugfs_item debugfs_entries[] = { |
812756a8 EGE |
205 | VCPU_STAT("pf_fixed", pf_fixed), |
206 | VCPU_STAT("pf_guest", pf_guest), | |
207 | VCPU_STAT("tlb_flush", tlb_flush), | |
208 | VCPU_STAT("invlpg", invlpg), | |
209 | VCPU_STAT("exits", exits), | |
210 | VCPU_STAT("io_exits", io_exits), | |
211 | VCPU_STAT("mmio_exits", mmio_exits), | |
212 | VCPU_STAT("signal_exits", signal_exits), | |
213 | VCPU_STAT("irq_window", irq_window_exits), | |
214 | VCPU_STAT("nmi_window", nmi_window_exits), | |
215 | VCPU_STAT("halt_exits", halt_exits), | |
216 | VCPU_STAT("halt_successful_poll", halt_successful_poll), | |
217 | VCPU_STAT("halt_attempted_poll", halt_attempted_poll), | |
218 | VCPU_STAT("halt_poll_invalid", halt_poll_invalid), | |
219 | VCPU_STAT("halt_wakeup", halt_wakeup), | |
220 | VCPU_STAT("hypercalls", hypercalls), | |
221 | VCPU_STAT("request_irq", request_irq_exits), | |
222 | VCPU_STAT("irq_exits", irq_exits), | |
223 | VCPU_STAT("host_state_reload", host_state_reload), | |
224 | VCPU_STAT("fpu_reload", fpu_reload), | |
225 | VCPU_STAT("insn_emulation", insn_emulation), | |
226 | VCPU_STAT("insn_emulation_fail", insn_emulation_fail), | |
227 | VCPU_STAT("irq_injections", irq_injections), | |
228 | VCPU_STAT("nmi_injections", nmi_injections), | |
229 | VCPU_STAT("req_event", req_event), | |
230 | VCPU_STAT("l1d_flush", l1d_flush), | |
cb953129 DM |
231 | VCPU_STAT("halt_poll_success_ns", halt_poll_success_ns), |
232 | VCPU_STAT("halt_poll_fail_ns", halt_poll_fail_ns), | |
812756a8 EGE |
233 | VM_STAT("mmu_shadow_zapped", mmu_shadow_zapped), |
234 | VM_STAT("mmu_pte_write", mmu_pte_write), | |
235 | VM_STAT("mmu_pte_updated", mmu_pte_updated), | |
236 | VM_STAT("mmu_pde_zapped", mmu_pde_zapped), | |
237 | VM_STAT("mmu_flooded", mmu_flooded), | |
238 | VM_STAT("mmu_recycled", mmu_recycled), | |
239 | VM_STAT("mmu_cache_miss", mmu_cache_miss), | |
240 | VM_STAT("mmu_unsync", mmu_unsync), | |
241 | VM_STAT("remote_tlb_flush", remote_tlb_flush), | |
242 | VM_STAT("largepages", lpages, .mode = 0444), | |
243 | VM_STAT("nx_largepages_splitted", nx_lpage_splits, .mode = 0444), | |
244 | VM_STAT("max_mmu_page_hash_collisions", max_mmu_page_hash_collisions), | |
417bc304 HB |
245 | { NULL } |
246 | }; | |
247 | ||
2acf923e | 248 | u64 __read_mostly host_xcr0; |
cfc48181 SC |
249 | u64 __read_mostly supported_xcr0; |
250 | EXPORT_SYMBOL_GPL(supported_xcr0); | |
2acf923e | 251 | |
80fbd280 | 252 | static struct kmem_cache *x86_fpu_cache; |
b666a4b6 | 253 | |
c9b8b07c SC |
254 | static struct kmem_cache *x86_emulator_cache; |
255 | ||
6abe9c13 PX |
256 | /* |
257 | * When called, it means the previous get/set msr reached an invalid msr. | |
cc4cb017 | 258 | * Return true if we want to ignore/silent this failed msr access. |
6abe9c13 | 259 | */ |
cc4cb017 ML |
260 | static bool kvm_msr_ignored_check(struct kvm_vcpu *vcpu, u32 msr, |
261 | u64 data, bool write) | |
6abe9c13 PX |
262 | { |
263 | const char *op = write ? "wrmsr" : "rdmsr"; | |
264 | ||
265 | if (ignore_msrs) { | |
266 | if (report_ignored_msrs) | |
d383b314 TI |
267 | kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n", |
268 | op, msr, data); | |
6abe9c13 | 269 | /* Mask the error */ |
cc4cb017 | 270 | return true; |
6abe9c13 | 271 | } else { |
d383b314 TI |
272 | kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n", |
273 | op, msr, data); | |
cc4cb017 | 274 | return false; |
6abe9c13 PX |
275 | } |
276 | } | |
277 | ||
c9b8b07c SC |
278 | static struct kmem_cache *kvm_alloc_emulator_cache(void) |
279 | { | |
06add254 SC |
280 | unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src); |
281 | unsigned int size = sizeof(struct x86_emulate_ctxt); | |
282 | ||
283 | return kmem_cache_create_usercopy("x86_emulator", size, | |
c9b8b07c | 284 | __alignof__(struct x86_emulate_ctxt), |
06add254 SC |
285 | SLAB_ACCOUNT, useroffset, |
286 | size - useroffset, NULL); | |
c9b8b07c SC |
287 | } |
288 | ||
b6785def | 289 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); |
d6aa1000 | 290 | |
af585b92 GN |
291 | static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) |
292 | { | |
293 | int i; | |
dd03bcaa | 294 | for (i = 0; i < ASYNC_PF_PER_VCPU; i++) |
af585b92 GN |
295 | vcpu->arch.apf.gfns[i] = ~0; |
296 | } | |
297 | ||
18863bdd AK |
298 | static void kvm_on_user_return(struct user_return_notifier *urn) |
299 | { | |
300 | unsigned slot; | |
7e34fbd0 SC |
301 | struct kvm_user_return_msrs *msrs |
302 | = container_of(urn, struct kvm_user_return_msrs, urn); | |
303 | struct kvm_user_return_msr_values *values; | |
1650b4eb IA |
304 | unsigned long flags; |
305 | ||
306 | /* | |
307 | * Disabling irqs at this point since the following code could be | |
308 | * interrupted and executed through kvm_arch_hardware_disable() | |
309 | */ | |
310 | local_irq_save(flags); | |
7e34fbd0 SC |
311 | if (msrs->registered) { |
312 | msrs->registered = false; | |
1650b4eb IA |
313 | user_return_notifier_unregister(urn); |
314 | } | |
315 | local_irq_restore(flags); | |
7e34fbd0 SC |
316 | for (slot = 0; slot < user_return_msrs_global.nr; ++slot) { |
317 | values = &msrs->values[slot]; | |
2bf78fa7 | 318 | if (values->host != values->curr) { |
7e34fbd0 | 319 | wrmsrl(user_return_msrs_global.msrs[slot], values->host); |
2bf78fa7 | 320 | values->curr = values->host; |
18863bdd AK |
321 | } |
322 | } | |
18863bdd AK |
323 | } |
324 | ||
7e34fbd0 | 325 | void kvm_define_user_return_msr(unsigned slot, u32 msr) |
2bf78fa7 | 326 | { |
7e34fbd0 SC |
327 | BUG_ON(slot >= KVM_MAX_NR_USER_RETURN_MSRS); |
328 | user_return_msrs_global.msrs[slot] = msr; | |
329 | if (slot >= user_return_msrs_global.nr) | |
330 | user_return_msrs_global.nr = slot + 1; | |
18863bdd | 331 | } |
7e34fbd0 | 332 | EXPORT_SYMBOL_GPL(kvm_define_user_return_msr); |
18863bdd | 333 | |
7e34fbd0 | 334 | static void kvm_user_return_msr_cpu_online(void) |
18863bdd | 335 | { |
05c19c2f | 336 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 337 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
05c19c2f SC |
338 | u64 value; |
339 | int i; | |
18863bdd | 340 | |
7e34fbd0 SC |
341 | for (i = 0; i < user_return_msrs_global.nr; ++i) { |
342 | rdmsrl_safe(user_return_msrs_global.msrs[i], &value); | |
343 | msrs->values[i].host = value; | |
344 | msrs->values[i].curr = value; | |
05c19c2f | 345 | } |
18863bdd AK |
346 | } |
347 | ||
7e34fbd0 | 348 | int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask) |
18863bdd | 349 | { |
013f6a5d | 350 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 351 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
8b3c3104 | 352 | int err; |
18863bdd | 353 | |
7e34fbd0 SC |
354 | value = (value & mask) | (msrs->values[slot].host & ~mask); |
355 | if (value == msrs->values[slot].curr) | |
8b3c3104 | 356 | return 0; |
7e34fbd0 | 357 | err = wrmsrl_safe(user_return_msrs_global.msrs[slot], value); |
8b3c3104 AH |
358 | if (err) |
359 | return 1; | |
360 | ||
7e34fbd0 SC |
361 | msrs->values[slot].curr = value; |
362 | if (!msrs->registered) { | |
363 | msrs->urn.on_user_return = kvm_on_user_return; | |
364 | user_return_notifier_register(&msrs->urn); | |
365 | msrs->registered = true; | |
18863bdd | 366 | } |
8b3c3104 | 367 | return 0; |
18863bdd | 368 | } |
7e34fbd0 | 369 | EXPORT_SYMBOL_GPL(kvm_set_user_return_msr); |
18863bdd | 370 | |
13a34e06 | 371 | static void drop_user_return_notifiers(void) |
3548bab5 | 372 | { |
013f6a5d | 373 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 374 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
3548bab5 | 375 | |
7e34fbd0 SC |
376 | if (msrs->registered) |
377 | kvm_on_user_return(&msrs->urn); | |
3548bab5 AK |
378 | } |
379 | ||
6866b83e CO |
380 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
381 | { | |
8a5a87d9 | 382 | return vcpu->arch.apic_base; |
6866b83e CO |
383 | } |
384 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
385 | ||
58871649 JM |
386 | enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) |
387 | { | |
388 | return kvm_apic_mode(kvm_get_apic_base(vcpu)); | |
389 | } | |
390 | EXPORT_SYMBOL_GPL(kvm_get_apic_mode); | |
391 | ||
58cb628d JK |
392 | int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
393 | { | |
58871649 JM |
394 | enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); |
395 | enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); | |
d6321d49 RK |
396 | u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff | |
397 | (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); | |
58cb628d | 398 | |
58871649 | 399 | if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) |
58cb628d | 400 | return 1; |
58871649 JM |
401 | if (!msr_info->host_initiated) { |
402 | if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) | |
403 | return 1; | |
404 | if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) | |
405 | return 1; | |
406 | } | |
58cb628d JK |
407 | |
408 | kvm_lapic_set_base(vcpu, msr_info->data); | |
4abaffce | 409 | kvm_recalculate_apic_map(vcpu->kvm); |
58cb628d | 410 | return 0; |
6866b83e CO |
411 | } |
412 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
413 | ||
3ebccdf3 | 414 | asmlinkage __visible noinstr void kvm_spurious_fault(void) |
e3ba45b8 GL |
415 | { |
416 | /* Fault while not rebooting. We want the trace. */ | |
b4fdcf60 | 417 | BUG_ON(!kvm_rebooting); |
e3ba45b8 GL |
418 | } |
419 | EXPORT_SYMBOL_GPL(kvm_spurious_fault); | |
420 | ||
3fd28fce ED |
421 | #define EXCPT_BENIGN 0 |
422 | #define EXCPT_CONTRIBUTORY 1 | |
423 | #define EXCPT_PF 2 | |
424 | ||
425 | static int exception_class(int vector) | |
426 | { | |
427 | switch (vector) { | |
428 | case PF_VECTOR: | |
429 | return EXCPT_PF; | |
430 | case DE_VECTOR: | |
431 | case TS_VECTOR: | |
432 | case NP_VECTOR: | |
433 | case SS_VECTOR: | |
434 | case GP_VECTOR: | |
435 | return EXCPT_CONTRIBUTORY; | |
436 | default: | |
437 | break; | |
438 | } | |
439 | return EXCPT_BENIGN; | |
440 | } | |
441 | ||
d6e8c854 NA |
442 | #define EXCPT_FAULT 0 |
443 | #define EXCPT_TRAP 1 | |
444 | #define EXCPT_ABORT 2 | |
445 | #define EXCPT_INTERRUPT 3 | |
446 | ||
447 | static int exception_type(int vector) | |
448 | { | |
449 | unsigned int mask; | |
450 | ||
451 | if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) | |
452 | return EXCPT_INTERRUPT; | |
453 | ||
454 | mask = 1 << vector; | |
455 | ||
456 | /* #DB is trap, as instruction watchpoints are handled elsewhere */ | |
457 | if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) | |
458 | return EXCPT_TRAP; | |
459 | ||
460 | if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) | |
461 | return EXCPT_ABORT; | |
462 | ||
463 | /* Reserved exceptions will result in fault */ | |
464 | return EXCPT_FAULT; | |
465 | } | |
466 | ||
da998b46 JM |
467 | void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) |
468 | { | |
469 | unsigned nr = vcpu->arch.exception.nr; | |
470 | bool has_payload = vcpu->arch.exception.has_payload; | |
471 | unsigned long payload = vcpu->arch.exception.payload; | |
472 | ||
473 | if (!has_payload) | |
474 | return; | |
475 | ||
476 | switch (nr) { | |
f10c729f JM |
477 | case DB_VECTOR: |
478 | /* | |
479 | * "Certain debug exceptions may clear bit 0-3. The | |
480 | * remaining contents of the DR6 register are never | |
481 | * cleared by the processor". | |
482 | */ | |
483 | vcpu->arch.dr6 &= ~DR_TRAP_BITS; | |
484 | /* | |
485 | * DR6.RTM is set by all #DB exceptions that don't clear it. | |
486 | */ | |
487 | vcpu->arch.dr6 |= DR6_RTM; | |
488 | vcpu->arch.dr6 |= payload; | |
489 | /* | |
490 | * Bit 16 should be set in the payload whenever the #DB | |
491 | * exception should clear DR6.RTM. This makes the payload | |
492 | * compatible with the pending debug exceptions under VMX. | |
493 | * Though not currently documented in the SDM, this also | |
494 | * makes the payload compatible with the exit qualification | |
495 | * for #DB exceptions under VMX. | |
496 | */ | |
497 | vcpu->arch.dr6 ^= payload & DR6_RTM; | |
307f1cfa OU |
498 | |
499 | /* | |
500 | * The #DB payload is defined as compatible with the 'pending | |
501 | * debug exceptions' field under VMX, not DR6. While bit 12 is | |
502 | * defined in the 'pending debug exceptions' field (enabled | |
503 | * breakpoint), it is reserved and must be zero in DR6. | |
504 | */ | |
505 | vcpu->arch.dr6 &= ~BIT(12); | |
f10c729f | 506 | break; |
da998b46 JM |
507 | case PF_VECTOR: |
508 | vcpu->arch.cr2 = payload; | |
509 | break; | |
510 | } | |
511 | ||
512 | vcpu->arch.exception.has_payload = false; | |
513 | vcpu->arch.exception.payload = 0; | |
514 | } | |
515 | EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); | |
516 | ||
3fd28fce | 517 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, |
ce7ddec4 | 518 | unsigned nr, bool has_error, u32 error_code, |
91e86d22 | 519 | bool has_payload, unsigned long payload, bool reinject) |
3fd28fce ED |
520 | { |
521 | u32 prev_nr; | |
522 | int class1, class2; | |
523 | ||
3842d135 AK |
524 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
525 | ||
664f8e26 | 526 | if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { |
3fd28fce | 527 | queue: |
3ffb2468 NA |
528 | if (has_error && !is_protmode(vcpu)) |
529 | has_error = false; | |
664f8e26 WL |
530 | if (reinject) { |
531 | /* | |
532 | * On vmentry, vcpu->arch.exception.pending is only | |
533 | * true if an event injection was blocked by | |
534 | * nested_run_pending. In that case, however, | |
535 | * vcpu_enter_guest requests an immediate exit, | |
536 | * and the guest shouldn't proceed far enough to | |
537 | * need reinjection. | |
538 | */ | |
539 | WARN_ON_ONCE(vcpu->arch.exception.pending); | |
540 | vcpu->arch.exception.injected = true; | |
91e86d22 JM |
541 | if (WARN_ON_ONCE(has_payload)) { |
542 | /* | |
543 | * A reinjected event has already | |
544 | * delivered its payload. | |
545 | */ | |
546 | has_payload = false; | |
547 | payload = 0; | |
548 | } | |
664f8e26 WL |
549 | } else { |
550 | vcpu->arch.exception.pending = true; | |
551 | vcpu->arch.exception.injected = false; | |
552 | } | |
3fd28fce ED |
553 | vcpu->arch.exception.has_error_code = has_error; |
554 | vcpu->arch.exception.nr = nr; | |
555 | vcpu->arch.exception.error_code = error_code; | |
91e86d22 JM |
556 | vcpu->arch.exception.has_payload = has_payload; |
557 | vcpu->arch.exception.payload = payload; | |
a06230b6 | 558 | if (!is_guest_mode(vcpu)) |
da998b46 | 559 | kvm_deliver_exception_payload(vcpu); |
3fd28fce ED |
560 | return; |
561 | } | |
562 | ||
563 | /* to check exception */ | |
564 | prev_nr = vcpu->arch.exception.nr; | |
565 | if (prev_nr == DF_VECTOR) { | |
566 | /* triple fault -> shutdown */ | |
a8eeb04a | 567 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
3fd28fce ED |
568 | return; |
569 | } | |
570 | class1 = exception_class(prev_nr); | |
571 | class2 = exception_class(nr); | |
572 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) | |
573 | || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
664f8e26 WL |
574 | /* |
575 | * Generate double fault per SDM Table 5-5. Set | |
576 | * exception.pending = true so that the double fault | |
577 | * can trigger a nested vmexit. | |
578 | */ | |
3fd28fce | 579 | vcpu->arch.exception.pending = true; |
664f8e26 | 580 | vcpu->arch.exception.injected = false; |
3fd28fce ED |
581 | vcpu->arch.exception.has_error_code = true; |
582 | vcpu->arch.exception.nr = DF_VECTOR; | |
583 | vcpu->arch.exception.error_code = 0; | |
c851436a JM |
584 | vcpu->arch.exception.has_payload = false; |
585 | vcpu->arch.exception.payload = 0; | |
3fd28fce ED |
586 | } else |
587 | /* replace previous exception with a new one in a hope | |
588 | that instruction re-execution will regenerate lost | |
589 | exception */ | |
590 | goto queue; | |
591 | } | |
592 | ||
298101da AK |
593 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
594 | { | |
91e86d22 | 595 | kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); |
298101da AK |
596 | } |
597 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
598 | ||
ce7ddec4 JR |
599 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
600 | { | |
91e86d22 | 601 | kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); |
ce7ddec4 JR |
602 | } |
603 | EXPORT_SYMBOL_GPL(kvm_requeue_exception); | |
604 | ||
4d5523cf PB |
605 | void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, |
606 | unsigned long payload) | |
f10c729f JM |
607 | { |
608 | kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); | |
609 | } | |
4d5523cf | 610 | EXPORT_SYMBOL_GPL(kvm_queue_exception_p); |
f10c729f | 611 | |
da998b46 JM |
612 | static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, |
613 | u32 error_code, unsigned long payload) | |
614 | { | |
615 | kvm_multiple_exception(vcpu, nr, true, error_code, | |
616 | true, payload, false); | |
617 | } | |
618 | ||
6affcbed | 619 | int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) |
c3c91fee | 620 | { |
db8fcefa AP |
621 | if (err) |
622 | kvm_inject_gp(vcpu, 0); | |
623 | else | |
6affcbed KH |
624 | return kvm_skip_emulated_instruction(vcpu); |
625 | ||
626 | return 1; | |
db8fcefa AP |
627 | } |
628 | EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); | |
8df25a32 | 629 | |
6389ee94 | 630 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
c3c91fee AK |
631 | { |
632 | ++vcpu->stat.pf_guest; | |
adfe20fb WL |
633 | vcpu->arch.exception.nested_apf = |
634 | is_guest_mode(vcpu) && fault->async_page_fault; | |
da998b46 | 635 | if (vcpu->arch.exception.nested_apf) { |
adfe20fb | 636 | vcpu->arch.apf.nested_apf_token = fault->address; |
da998b46 JM |
637 | kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); |
638 | } else { | |
639 | kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, | |
640 | fault->address); | |
641 | } | |
c3c91fee | 642 | } |
27d6c865 | 643 | EXPORT_SYMBOL_GPL(kvm_inject_page_fault); |
c3c91fee | 644 | |
53b3d8e9 SC |
645 | bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, |
646 | struct x86_exception *fault) | |
d4f8cf66 | 647 | { |
0cd665bd | 648 | struct kvm_mmu *fault_mmu; |
53b3d8e9 SC |
649 | WARN_ON_ONCE(fault->vector != PF_VECTOR); |
650 | ||
0cd665bd PB |
651 | fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu : |
652 | vcpu->arch.walk_mmu; | |
ef54bcfe | 653 | |
ee1fa209 JS |
654 | /* |
655 | * Invalidate the TLB entry for the faulting address, if it exists, | |
656 | * else the access will fault indefinitely (and to emulate hardware). | |
657 | */ | |
658 | if ((fault->error_code & PFERR_PRESENT_MASK) && | |
659 | !(fault->error_code & PFERR_RSVD_MASK)) | |
660 | kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address, | |
661 | fault_mmu->root_hpa); | |
662 | ||
663 | fault_mmu->inject_page_fault(vcpu, fault); | |
ef54bcfe | 664 | return fault->nested_page_fault; |
d4f8cf66 | 665 | } |
53b3d8e9 | 666 | EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault); |
d4f8cf66 | 667 | |
3419ffc8 SY |
668 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
669 | { | |
7460fb4a AK |
670 | atomic_inc(&vcpu->arch.nmi_queued); |
671 | kvm_make_request(KVM_REQ_NMI, vcpu); | |
3419ffc8 SY |
672 | } |
673 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
674 | ||
298101da AK |
675 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
676 | { | |
91e86d22 | 677 | kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); |
298101da AK |
678 | } |
679 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
680 | ||
ce7ddec4 JR |
681 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
682 | { | |
91e86d22 | 683 | kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); |
ce7ddec4 JR |
684 | } |
685 | EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); | |
686 | ||
0a79b009 AK |
687 | /* |
688 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
689 | * a #GP and return false. | |
690 | */ | |
691 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 692 | { |
afaf0b2f | 693 | if (kvm_x86_ops.get_cpl(vcpu) <= required_cpl) |
0a79b009 AK |
694 | return true; |
695 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
696 | return false; | |
298101da | 697 | } |
0a79b009 | 698 | EXPORT_SYMBOL_GPL(kvm_require_cpl); |
298101da | 699 | |
16f8a6f9 NA |
700 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) |
701 | { | |
702 | if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
703 | return true; | |
704 | ||
705 | kvm_queue_exception(vcpu, UD_VECTOR); | |
706 | return false; | |
707 | } | |
708 | EXPORT_SYMBOL_GPL(kvm_require_dr); | |
709 | ||
ec92fe44 JR |
710 | /* |
711 | * This function will be used to read from the physical memory of the currently | |
54bf36aa | 712 | * running guest. The difference to kvm_vcpu_read_guest_page is that this function |
ec92fe44 JR |
713 | * can read from guest physical or from the guest's guest physical memory. |
714 | */ | |
715 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
716 | gfn_t ngfn, void *data, int offset, int len, | |
717 | u32 access) | |
718 | { | |
54987b7a | 719 | struct x86_exception exception; |
ec92fe44 JR |
720 | gfn_t real_gfn; |
721 | gpa_t ngpa; | |
722 | ||
723 | ngpa = gfn_to_gpa(ngfn); | |
54987b7a | 724 | real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); |
ec92fe44 JR |
725 | if (real_gfn == UNMAPPED_GVA) |
726 | return -EFAULT; | |
727 | ||
728 | real_gfn = gpa_to_gfn(real_gfn); | |
729 | ||
54bf36aa | 730 | return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); |
ec92fe44 JR |
731 | } |
732 | EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); | |
733 | ||
69b0049a | 734 | static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, |
3d06b8bf JR |
735 | void *data, int offset, int len, u32 access) |
736 | { | |
737 | return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, | |
738 | data, offset, len, access); | |
739 | } | |
740 | ||
16cfacc8 SC |
741 | static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) |
742 | { | |
743 | return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) | | |
744 | rsvd_bits(1, 2); | |
745 | } | |
746 | ||
a03490ed | 747 | /* |
16cfacc8 | 748 | * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. |
a03490ed | 749 | */ |
ff03a073 | 750 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) |
a03490ed CO |
751 | { |
752 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
753 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
754 | int i; | |
755 | int ret; | |
ff03a073 | 756 | u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; |
a03490ed | 757 | |
ff03a073 JR |
758 | ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, |
759 | offset * sizeof(u64), sizeof(pdpte), | |
760 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
a03490ed CO |
761 | if (ret < 0) { |
762 | ret = 0; | |
763 | goto out; | |
764 | } | |
765 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
812f30b2 | 766 | if ((pdpte[i] & PT_PRESENT_MASK) && |
16cfacc8 | 767 | (pdpte[i] & pdptr_rsvd_bits(vcpu))) { |
a03490ed CO |
768 | ret = 0; |
769 | goto out; | |
770 | } | |
771 | } | |
772 | ret = 1; | |
773 | ||
ff03a073 | 774 | memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); |
cb3c1e2f SC |
775 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); |
776 | ||
a03490ed | 777 | out: |
a03490ed CO |
778 | |
779 | return ret; | |
780 | } | |
cc4b6871 | 781 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 782 | |
9ed38ffa | 783 | bool pdptrs_changed(struct kvm_vcpu *vcpu) |
d835dfec | 784 | { |
ff03a073 | 785 | u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; |
3d06b8bf JR |
786 | int offset; |
787 | gfn_t gfn; | |
d835dfec AK |
788 | int r; |
789 | ||
bf03d4f9 | 790 | if (!is_pae_paging(vcpu)) |
d835dfec AK |
791 | return false; |
792 | ||
cb3c1e2f | 793 | if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR)) |
6de4f3ad AK |
794 | return true; |
795 | ||
a512177e PB |
796 | gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT; |
797 | offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1); | |
3d06b8bf JR |
798 | r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), |
799 | PFERR_USER_MASK | PFERR_WRITE_MASK); | |
d835dfec | 800 | if (r < 0) |
7f7f0d9c | 801 | return true; |
d835dfec | 802 | |
7f7f0d9c | 803 | return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; |
d835dfec | 804 | } |
9ed38ffa | 805 | EXPORT_SYMBOL_GPL(pdptrs_changed); |
d835dfec | 806 | |
49a9b07e | 807 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 808 | { |
aad82703 | 809 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
d42e3fae | 810 | unsigned long pdptr_bits = X86_CR0_CD | X86_CR0_NW | X86_CR0_PG; |
d81135a5 | 811 | unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; |
aad82703 | 812 | |
f9a48e6a AK |
813 | cr0 |= X86_CR0_ET; |
814 | ||
ab344828 | 815 | #ifdef CONFIG_X86_64 |
0f12244f GN |
816 | if (cr0 & 0xffffffff00000000UL) |
817 | return 1; | |
ab344828 GN |
818 | #endif |
819 | ||
820 | cr0 &= ~CR0_RESERVED_BITS; | |
a03490ed | 821 | |
0f12244f GN |
822 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) |
823 | return 1; | |
a03490ed | 824 | |
0f12244f GN |
825 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) |
826 | return 1; | |
a03490ed | 827 | |
a03490ed | 828 | #ifdef CONFIG_X86_64 |
05487215 SC |
829 | if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) && |
830 | (cr0 & X86_CR0_PG)) { | |
831 | int cs_db, cs_l; | |
832 | ||
833 | if (!is_pae(vcpu)) | |
834 | return 1; | |
835 | kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
836 | if (cs_l) | |
0f12244f | 837 | return 1; |
a03490ed | 838 | } |
05487215 SC |
839 | #endif |
840 | if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) && | |
841 | is_pae(vcpu) && ((cr0 ^ old_cr0) & pdptr_bits) && | |
842 | !load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu))) | |
843 | return 1; | |
a03490ed | 844 | |
ad756a16 MJ |
845 | if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) |
846 | return 1; | |
847 | ||
afaf0b2f | 848 | kvm_x86_ops.set_cr0(vcpu, cr0); |
a03490ed | 849 | |
d170c419 | 850 | if ((cr0 ^ old_cr0) & X86_CR0_PG) { |
e5f3f027 | 851 | kvm_clear_async_pf_completion_queue(vcpu); |
d170c419 LJ |
852 | kvm_async_pf_hash_reset(vcpu); |
853 | } | |
e5f3f027 | 854 | |
aad82703 SY |
855 | if ((cr0 ^ old_cr0) & update_bits) |
856 | kvm_mmu_reset_context(vcpu); | |
b18d5431 | 857 | |
879ae188 LE |
858 | if (((cr0 ^ old_cr0) & X86_CR0_CD) && |
859 | kvm_arch_has_noncoherent_dma(vcpu->kvm) && | |
860 | !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) | |
b18d5431 XG |
861 | kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); |
862 | ||
0f12244f GN |
863 | return 0; |
864 | } | |
2d3ad1f4 | 865 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 866 | |
2d3ad1f4 | 867 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 868 | { |
49a9b07e | 869 | (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); |
a03490ed | 870 | } |
2d3ad1f4 | 871 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 872 | |
139a12cf | 873 | void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) |
42bdf991 | 874 | { |
139a12cf AL |
875 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { |
876 | ||
877 | if (vcpu->arch.xcr0 != host_xcr0) | |
878 | xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); | |
879 | ||
880 | if (vcpu->arch.xsaves_enabled && | |
881 | vcpu->arch.ia32_xss != host_xss) | |
882 | wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); | |
883 | } | |
37486135 BM |
884 | |
885 | if (static_cpu_has(X86_FEATURE_PKU) && | |
886 | (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || | |
887 | (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) && | |
888 | vcpu->arch.pkru != vcpu->arch.host_pkru) | |
889 | __write_pkru(vcpu->arch.pkru); | |
42bdf991 | 890 | } |
139a12cf | 891 | EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state); |
42bdf991 | 892 | |
139a12cf | 893 | void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) |
42bdf991 | 894 | { |
37486135 BM |
895 | if (static_cpu_has(X86_FEATURE_PKU) && |
896 | (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || | |
897 | (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) { | |
898 | vcpu->arch.pkru = rdpkru(); | |
899 | if (vcpu->arch.pkru != vcpu->arch.host_pkru) | |
900 | __write_pkru(vcpu->arch.host_pkru); | |
901 | } | |
902 | ||
139a12cf AL |
903 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { |
904 | ||
905 | if (vcpu->arch.xcr0 != host_xcr0) | |
906 | xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); | |
907 | ||
908 | if (vcpu->arch.xsaves_enabled && | |
909 | vcpu->arch.ia32_xss != host_xss) | |
910 | wrmsrl(MSR_IA32_XSS, host_xss); | |
911 | } | |
912 | ||
42bdf991 | 913 | } |
139a12cf | 914 | EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state); |
42bdf991 | 915 | |
69b0049a | 916 | static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) |
2acf923e | 917 | { |
56c103ec LJ |
918 | u64 xcr0 = xcr; |
919 | u64 old_xcr0 = vcpu->arch.xcr0; | |
46c34cb0 | 920 | u64 valid_bits; |
2acf923e DC |
921 | |
922 | /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ | |
923 | if (index != XCR_XFEATURE_ENABLED_MASK) | |
924 | return 1; | |
d91cab78 | 925 | if (!(xcr0 & XFEATURE_MASK_FP)) |
2acf923e | 926 | return 1; |
d91cab78 | 927 | if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) |
2acf923e | 928 | return 1; |
46c34cb0 PB |
929 | |
930 | /* | |
931 | * Do not allow the guest to set bits that we do not support | |
932 | * saving. However, xcr0 bit 0 is always set, even if the | |
933 | * emulated CPU does not support XSAVE (see fx_init). | |
934 | */ | |
d91cab78 | 935 | valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; |
46c34cb0 | 936 | if (xcr0 & ~valid_bits) |
2acf923e | 937 | return 1; |
46c34cb0 | 938 | |
d91cab78 DH |
939 | if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != |
940 | (!(xcr0 & XFEATURE_MASK_BNDCSR))) | |
390bd528 LJ |
941 | return 1; |
942 | ||
d91cab78 DH |
943 | if (xcr0 & XFEATURE_MASK_AVX512) { |
944 | if (!(xcr0 & XFEATURE_MASK_YMM)) | |
612263b3 | 945 | return 1; |
d91cab78 | 946 | if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) |
612263b3 CP |
947 | return 1; |
948 | } | |
2acf923e | 949 | vcpu->arch.xcr0 = xcr0; |
56c103ec | 950 | |
d91cab78 | 951 | if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) |
aedbaf4f | 952 | kvm_update_cpuid_runtime(vcpu); |
2acf923e DC |
953 | return 0; |
954 | } | |
955 | ||
956 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) | |
957 | { | |
afaf0b2f | 958 | if (kvm_x86_ops.get_cpl(vcpu) != 0 || |
764bcbc5 | 959 | __kvm_set_xcr(vcpu, index, xcr)) { |
2acf923e DC |
960 | kvm_inject_gp(vcpu, 0); |
961 | return 1; | |
962 | } | |
963 | return 0; | |
964 | } | |
965 | EXPORT_SYMBOL_GPL(kvm_set_xcr); | |
966 | ||
761e4169 | 967 | int kvm_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 968 | { |
b11306b5 | 969 | if (cr4 & cr4_reserved_bits) |
3ca94192 | 970 | return -EINVAL; |
b9baba86 | 971 | |
b899c132 | 972 | if (cr4 & vcpu->arch.cr4_guest_rsvd_bits) |
3ca94192 WL |
973 | return -EINVAL; |
974 | ||
c2fe3cd4 SC |
975 | if (!kvm_x86_ops.is_valid_cr4(vcpu, cr4)) |
976 | return -EINVAL; | |
977 | ||
3ca94192 WL |
978 | return 0; |
979 | } | |
761e4169 | 980 | EXPORT_SYMBOL_GPL(kvm_valid_cr4); |
3ca94192 WL |
981 | |
982 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
983 | { | |
984 | unsigned long old_cr4 = kvm_read_cr4(vcpu); | |
985 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | | |
cb957adb | 986 | X86_CR4_SMEP; |
8d214c48 | 987 | unsigned long mmu_role_bits = pdptr_bits | X86_CR4_SMAP | X86_CR4_PKE; |
3ca94192 WL |
988 | |
989 | if (kvm_valid_cr4(vcpu, cr4)) | |
ae3e61e1 PB |
990 | return 1; |
991 | ||
a03490ed | 992 | if (is_long_mode(vcpu)) { |
0f12244f GN |
993 | if (!(cr4 & X86_CR4_PAE)) |
994 | return 1; | |
d74fcfc1 SC |
995 | if ((cr4 ^ old_cr4) & X86_CR4_LA57) |
996 | return 1; | |
a2edf57f AK |
997 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
998 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
9f8fe504 AK |
999 | && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
1000 | kvm_read_cr3(vcpu))) | |
0f12244f GN |
1001 | return 1; |
1002 | ||
ad756a16 | 1003 | if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { |
d6321d49 | 1004 | if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) |
ad756a16 MJ |
1005 | return 1; |
1006 | ||
1007 | /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ | |
1008 | if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) | |
1009 | return 1; | |
1010 | } | |
1011 | ||
c2fe3cd4 | 1012 | kvm_x86_ops.set_cr4(vcpu, cr4); |
a03490ed | 1013 | |
8d214c48 | 1014 | if (((cr4 ^ old_cr4) & mmu_role_bits) || |
ad756a16 | 1015 | (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) |
aad82703 | 1016 | kvm_mmu_reset_context(vcpu); |
0f12244f | 1017 | |
b9baba86 | 1018 | if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE)) |
aedbaf4f | 1019 | kvm_update_cpuid_runtime(vcpu); |
2acf923e | 1020 | |
0f12244f GN |
1021 | return 0; |
1022 | } | |
2d3ad1f4 | 1023 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 1024 | |
2390218b | 1025 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 1026 | { |
ade61e28 | 1027 | bool skip_tlb_flush = false; |
ac146235 | 1028 | #ifdef CONFIG_X86_64 |
c19986fe JS |
1029 | bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); |
1030 | ||
ade61e28 | 1031 | if (pcid_enabled) { |
208320ba JS |
1032 | skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; |
1033 | cr3 &= ~X86_CR3_PCID_NOFLUSH; | |
ade61e28 | 1034 | } |
ac146235 | 1035 | #endif |
9d88fca7 | 1036 | |
9f8fe504 | 1037 | if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { |
956bf353 JS |
1038 | if (!skip_tlb_flush) { |
1039 | kvm_mmu_sync_roots(vcpu); | |
eeeb4f67 | 1040 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
956bf353 | 1041 | } |
0f12244f | 1042 | return 0; |
d835dfec AK |
1043 | } |
1044 | ||
d1cd3ce9 | 1045 | if (is_long_mode(vcpu) && |
0107973a | 1046 | (cr3 & vcpu->arch.cr3_lm_rsvd_bits)) |
d1cd3ce9 | 1047 | return 1; |
bf03d4f9 PB |
1048 | else if (is_pae_paging(vcpu) && |
1049 | !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) | |
346874c9 | 1050 | return 1; |
a03490ed | 1051 | |
be01e8e2 | 1052 | kvm_mmu_new_pgd(vcpu, cr3, skip_tlb_flush, skip_tlb_flush); |
0f12244f | 1053 | vcpu->arch.cr3 = cr3; |
cb3c1e2f | 1054 | kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); |
7c390d35 | 1055 | |
0f12244f GN |
1056 | return 0; |
1057 | } | |
2d3ad1f4 | 1058 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 1059 | |
eea1cff9 | 1060 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed | 1061 | { |
0f12244f GN |
1062 | if (cr8 & CR8_RESERVED_BITS) |
1063 | return 1; | |
35754c98 | 1064 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
1065 | kvm_lapic_set_tpr(vcpu, cr8); |
1066 | else | |
ad312c7c | 1067 | vcpu->arch.cr8 = cr8; |
0f12244f GN |
1068 | return 0; |
1069 | } | |
2d3ad1f4 | 1070 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 1071 | |
2d3ad1f4 | 1072 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed | 1073 | { |
35754c98 | 1074 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
1075 | return kvm_lapic_get_cr8(vcpu); |
1076 | else | |
ad312c7c | 1077 | return vcpu->arch.cr8; |
a03490ed | 1078 | } |
2d3ad1f4 | 1079 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 1080 | |
ae561ede NA |
1081 | static void kvm_update_dr0123(struct kvm_vcpu *vcpu) |
1082 | { | |
1083 | int i; | |
1084 | ||
1085 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
1086 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
1087 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
1088 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; | |
1089 | } | |
1090 | } | |
1091 | ||
7c86663b | 1092 | void kvm_update_dr7(struct kvm_vcpu *vcpu) |
c8639010 JK |
1093 | { |
1094 | unsigned long dr7; | |
1095 | ||
1096 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
1097 | dr7 = vcpu->arch.guest_debug_dr7; | |
1098 | else | |
1099 | dr7 = vcpu->arch.dr7; | |
afaf0b2f | 1100 | kvm_x86_ops.set_dr7(vcpu, dr7); |
360b948d PB |
1101 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; |
1102 | if (dr7 & DR7_BP_EN_MASK) | |
1103 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; | |
c8639010 | 1104 | } |
7c86663b | 1105 | EXPORT_SYMBOL_GPL(kvm_update_dr7); |
c8639010 | 1106 | |
6f43ed01 NA |
1107 | static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) |
1108 | { | |
1109 | u64 fixed = DR6_FIXED_1; | |
1110 | ||
d6321d49 | 1111 | if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) |
6f43ed01 NA |
1112 | fixed |= DR6_RTM; |
1113 | return fixed; | |
1114 | } | |
1115 | ||
338dbc97 | 1116 | static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) |
020df079 | 1117 | { |
ea740059 MP |
1118 | size_t size = ARRAY_SIZE(vcpu->arch.db); |
1119 | ||
020df079 GN |
1120 | switch (dr) { |
1121 | case 0 ... 3: | |
ea740059 | 1122 | vcpu->arch.db[array_index_nospec(dr, size)] = val; |
020df079 GN |
1123 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) |
1124 | vcpu->arch.eff_db[dr] = val; | |
1125 | break; | |
1126 | case 4: | |
020df079 | 1127 | case 6: |
f5f6145e | 1128 | if (!kvm_dr6_valid(val)) |
338dbc97 | 1129 | return -1; /* #GP */ |
6f43ed01 | 1130 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); |
020df079 GN |
1131 | break; |
1132 | case 5: | |
020df079 | 1133 | default: /* 7 */ |
b91991bf | 1134 | if (!kvm_dr7_valid(val)) |
338dbc97 | 1135 | return -1; /* #GP */ |
020df079 | 1136 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; |
c8639010 | 1137 | kvm_update_dr7(vcpu); |
020df079 GN |
1138 | break; |
1139 | } | |
1140 | ||
1141 | return 0; | |
1142 | } | |
338dbc97 GN |
1143 | |
1144 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) | |
1145 | { | |
16f8a6f9 | 1146 | if (__kvm_set_dr(vcpu, dr, val)) { |
338dbc97 | 1147 | kvm_inject_gp(vcpu, 0); |
16f8a6f9 NA |
1148 | return 1; |
1149 | } | |
1150 | return 0; | |
338dbc97 | 1151 | } |
020df079 GN |
1152 | EXPORT_SYMBOL_GPL(kvm_set_dr); |
1153 | ||
16f8a6f9 | 1154 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) |
020df079 | 1155 | { |
ea740059 MP |
1156 | size_t size = ARRAY_SIZE(vcpu->arch.db); |
1157 | ||
020df079 GN |
1158 | switch (dr) { |
1159 | case 0 ... 3: | |
ea740059 | 1160 | *val = vcpu->arch.db[array_index_nospec(dr, size)]; |
020df079 GN |
1161 | break; |
1162 | case 4: | |
020df079 | 1163 | case 6: |
5679b803 | 1164 | *val = vcpu->arch.dr6; |
020df079 GN |
1165 | break; |
1166 | case 5: | |
020df079 GN |
1167 | default: /* 7 */ |
1168 | *val = vcpu->arch.dr7; | |
1169 | break; | |
1170 | } | |
338dbc97 GN |
1171 | return 0; |
1172 | } | |
020df079 GN |
1173 | EXPORT_SYMBOL_GPL(kvm_get_dr); |
1174 | ||
022cd0e8 AK |
1175 | bool kvm_rdpmc(struct kvm_vcpu *vcpu) |
1176 | { | |
de3cd117 | 1177 | u32 ecx = kvm_rcx_read(vcpu); |
022cd0e8 AK |
1178 | u64 data; |
1179 | int err; | |
1180 | ||
c6702c9d | 1181 | err = kvm_pmu_rdpmc(vcpu, ecx, &data); |
022cd0e8 AK |
1182 | if (err) |
1183 | return err; | |
de3cd117 SC |
1184 | kvm_rax_write(vcpu, (u32)data); |
1185 | kvm_rdx_write(vcpu, data >> 32); | |
022cd0e8 AK |
1186 | return err; |
1187 | } | |
1188 | EXPORT_SYMBOL_GPL(kvm_rdpmc); | |
1189 | ||
043405e1 CO |
1190 | /* |
1191 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
1192 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
1193 | * | |
7a5ee6ed CQ |
1194 | * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) |
1195 | * extract the supported MSRs from the related const lists. | |
1196 | * msrs_to_save is selected from the msrs_to_save_all to reflect the | |
e3267cbb | 1197 | * capabilities of the host cpu. This capabilities test skips MSRs that are |
7a5ee6ed | 1198 | * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs |
62ef68bb | 1199 | * may depend on host virtualization features rather than host cpu features. |
043405e1 | 1200 | */ |
e3267cbb | 1201 | |
7a5ee6ed | 1202 | static const u32 msrs_to_save_all[] = { |
043405e1 | 1203 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, |
8c06585d | 1204 | MSR_STAR, |
043405e1 CO |
1205 | #ifdef CONFIG_X86_64 |
1206 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
1207 | #endif | |
b3897a49 | 1208 | MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, |
32ad73db | 1209 | MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, |
2bdb76c0 | 1210 | MSR_IA32_SPEC_CTRL, |
bf8c55d8 CP |
1211 | MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, |
1212 | MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, | |
1213 | MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, | |
1214 | MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, | |
1215 | MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, | |
1216 | MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, | |
6e3ba4ab TX |
1217 | MSR_IA32_UMWAIT_CONTROL, |
1218 | ||
e2ada66e JM |
1219 | MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, |
1220 | MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3, | |
1221 | MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, | |
1222 | MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, | |
1223 | MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, | |
1224 | MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, | |
1225 | MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, | |
1226 | MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, | |
1227 | MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9, | |
1228 | MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11, | |
1229 | MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13, | |
1230 | MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15, | |
1231 | MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17, | |
e2ada66e JM |
1232 | MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, |
1233 | MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, | |
1234 | MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, | |
1235 | MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, | |
1236 | MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9, | |
1237 | MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11, | |
1238 | MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13, | |
1239 | MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15, | |
1240 | MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17, | |
043405e1 CO |
1241 | }; |
1242 | ||
7a5ee6ed | 1243 | static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)]; |
043405e1 CO |
1244 | static unsigned num_msrs_to_save; |
1245 | ||
7a5ee6ed | 1246 | static const u32 emulated_msrs_all[] = { |
62ef68bb PB |
1247 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, |
1248 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, | |
1249 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, | |
1250 | HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, | |
72c139ba | 1251 | HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, |
e7d9513b AS |
1252 | HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, |
1253 | HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, | |
e516cebb | 1254 | HV_X64_MSR_RESET, |
11c4b1ca | 1255 | HV_X64_MSR_VP_INDEX, |
9eec50b8 | 1256 | HV_X64_MSR_VP_RUNTIME, |
5c919412 | 1257 | HV_X64_MSR_SCONTROL, |
1f4b34f8 | 1258 | HV_X64_MSR_STIMER0_CONFIG, |
d4abc577 | 1259 | HV_X64_MSR_VP_ASSIST_PAGE, |
a2e164e7 VK |
1260 | HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, |
1261 | HV_X64_MSR_TSC_EMULATION_STATUS, | |
f97f5a56 JD |
1262 | HV_X64_MSR_SYNDBG_OPTIONS, |
1263 | HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS, | |
1264 | HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER, | |
1265 | HV_X64_MSR_SYNDBG_PENDING_BUFFER, | |
a2e164e7 VK |
1266 | |
1267 | MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, | |
557a961a | 1268 | MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK, |
62ef68bb | 1269 | |
ba904635 | 1270 | MSR_IA32_TSC_ADJUST, |
a3e06bbe | 1271 | MSR_IA32_TSCDEADLINE, |
2bdb76c0 | 1272 | MSR_IA32_ARCH_CAPABILITIES, |
27461da3 | 1273 | MSR_IA32_PERF_CAPABILITIES, |
043405e1 | 1274 | MSR_IA32_MISC_ENABLE, |
908e75f3 AK |
1275 | MSR_IA32_MCG_STATUS, |
1276 | MSR_IA32_MCG_CTL, | |
c45dcc71 | 1277 | MSR_IA32_MCG_EXT_CTL, |
64d60670 | 1278 | MSR_IA32_SMBASE, |
52797bf9 | 1279 | MSR_SMI_COUNT, |
db2336a8 KH |
1280 | MSR_PLATFORM_INFO, |
1281 | MSR_MISC_FEATURES_ENABLES, | |
bc226f07 | 1282 | MSR_AMD64_VIRT_SPEC_CTRL, |
6c6a2ab9 | 1283 | MSR_IA32_POWER_CTL, |
99634e3e | 1284 | MSR_IA32_UCODE_REV, |
191c8137 | 1285 | |
95c5c7c7 PB |
1286 | /* |
1287 | * The following list leaves out MSRs whose values are determined | |
1288 | * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs. | |
1289 | * We always support the "true" VMX control MSRs, even if the host | |
1290 | * processor does not, so I am putting these registers here rather | |
7a5ee6ed | 1291 | * than in msrs_to_save_all. |
95c5c7c7 PB |
1292 | */ |
1293 | MSR_IA32_VMX_BASIC, | |
1294 | MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
1295 | MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
1296 | MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
1297 | MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
1298 | MSR_IA32_VMX_MISC, | |
1299 | MSR_IA32_VMX_CR0_FIXED0, | |
1300 | MSR_IA32_VMX_CR4_FIXED0, | |
1301 | MSR_IA32_VMX_VMCS_ENUM, | |
1302 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
1303 | MSR_IA32_VMX_EPT_VPID_CAP, | |
1304 | MSR_IA32_VMX_VMFUNC, | |
1305 | ||
191c8137 | 1306 | MSR_K7_HWCR, |
2d5ba19b | 1307 | MSR_KVM_POLL_CONTROL, |
043405e1 CO |
1308 | }; |
1309 | ||
7a5ee6ed | 1310 | static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]; |
62ef68bb PB |
1311 | static unsigned num_emulated_msrs; |
1312 | ||
801e459a TL |
1313 | /* |
1314 | * List of msr numbers which are used to expose MSR-based features that | |
1315 | * can be used by a hypervisor to validate requested CPU features. | |
1316 | */ | |
7a5ee6ed | 1317 | static const u32 msr_based_features_all[] = { |
1389309c PB |
1318 | MSR_IA32_VMX_BASIC, |
1319 | MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
1320 | MSR_IA32_VMX_PINBASED_CTLS, | |
1321 | MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
1322 | MSR_IA32_VMX_PROCBASED_CTLS, | |
1323 | MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
1324 | MSR_IA32_VMX_EXIT_CTLS, | |
1325 | MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
1326 | MSR_IA32_VMX_ENTRY_CTLS, | |
1327 | MSR_IA32_VMX_MISC, | |
1328 | MSR_IA32_VMX_CR0_FIXED0, | |
1329 | MSR_IA32_VMX_CR0_FIXED1, | |
1330 | MSR_IA32_VMX_CR4_FIXED0, | |
1331 | MSR_IA32_VMX_CR4_FIXED1, | |
1332 | MSR_IA32_VMX_VMCS_ENUM, | |
1333 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
1334 | MSR_IA32_VMX_EPT_VPID_CAP, | |
1335 | MSR_IA32_VMX_VMFUNC, | |
1336 | ||
d1d93fa9 | 1337 | MSR_F10H_DECFG, |
518e7b94 | 1338 | MSR_IA32_UCODE_REV, |
cd283252 | 1339 | MSR_IA32_ARCH_CAPABILITIES, |
27461da3 | 1340 | MSR_IA32_PERF_CAPABILITIES, |
801e459a TL |
1341 | }; |
1342 | ||
7a5ee6ed | 1343 | static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)]; |
801e459a TL |
1344 | static unsigned int num_msr_based_features; |
1345 | ||
4d22c17c | 1346 | static u64 kvm_get_arch_capabilities(void) |
5b76a3cf | 1347 | { |
4d22c17c | 1348 | u64 data = 0; |
5b76a3cf | 1349 | |
4d22c17c XL |
1350 | if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) |
1351 | rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data); | |
5b76a3cf | 1352 | |
b8e8c830 PB |
1353 | /* |
1354 | * If nx_huge_pages is enabled, KVM's shadow paging will ensure that | |
1355 | * the nested hypervisor runs with NX huge pages. If it is not, | |
1356 | * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other | |
1357 | * L1 guests, so it need not worry about its own (L2) guests. | |
1358 | */ | |
1359 | data |= ARCH_CAP_PSCHANGE_MC_NO; | |
1360 | ||
5b76a3cf PB |
1361 | /* |
1362 | * If we're doing cache flushes (either "always" or "cond") | |
1363 | * we will do one whenever the guest does a vmlaunch/vmresume. | |
1364 | * If an outer hypervisor is doing the cache flush for us | |
1365 | * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that | |
1366 | * capability to the guest too, and if EPT is disabled we're not | |
1367 | * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will | |
1368 | * require a nested hypervisor to do a flush of its own. | |
1369 | */ | |
1370 | if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) | |
1371 | data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; | |
1372 | ||
0c54914d PB |
1373 | if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) |
1374 | data |= ARCH_CAP_RDCL_NO; | |
1375 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
1376 | data |= ARCH_CAP_SSB_NO; | |
1377 | if (!boot_cpu_has_bug(X86_BUG_MDS)) | |
1378 | data |= ARCH_CAP_MDS_NO; | |
1379 | ||
e1d38b63 | 1380 | /* |
c11f83e0 PB |
1381 | * On TAA affected systems: |
1382 | * - nothing to do if TSX is disabled on the host. | |
1383 | * - we emulate TSX_CTRL if present on the host. | |
1384 | * This lets the guest use VERW to clear CPU buffers. | |
e1d38b63 | 1385 | */ |
cbbaa272 | 1386 | if (!boot_cpu_has(X86_FEATURE_RTM)) |
c11f83e0 | 1387 | data &= ~(ARCH_CAP_TAA_NO | ARCH_CAP_TSX_CTRL_MSR); |
cbbaa272 PB |
1388 | else if (!boot_cpu_has_bug(X86_BUG_TAA)) |
1389 | data |= ARCH_CAP_TAA_NO; | |
e1d38b63 | 1390 | |
5b76a3cf PB |
1391 | return data; |
1392 | } | |
5b76a3cf | 1393 | |
66421c1e WL |
1394 | static int kvm_get_msr_feature(struct kvm_msr_entry *msr) |
1395 | { | |
1396 | switch (msr->index) { | |
cd283252 | 1397 | case MSR_IA32_ARCH_CAPABILITIES: |
5b76a3cf PB |
1398 | msr->data = kvm_get_arch_capabilities(); |
1399 | break; | |
1400 | case MSR_IA32_UCODE_REV: | |
cd283252 | 1401 | rdmsrl_safe(msr->index, &msr->data); |
518e7b94 | 1402 | break; |
66421c1e | 1403 | default: |
12bc2132 | 1404 | return kvm_x86_ops.get_msr_feature(msr); |
66421c1e WL |
1405 | } |
1406 | return 0; | |
1407 | } | |
1408 | ||
801e459a TL |
1409 | static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) |
1410 | { | |
1411 | struct kvm_msr_entry msr; | |
66421c1e | 1412 | int r; |
801e459a TL |
1413 | |
1414 | msr.index = index; | |
66421c1e | 1415 | r = kvm_get_msr_feature(&msr); |
12bc2132 PX |
1416 | |
1417 | if (r == KVM_MSR_RET_INVALID) { | |
1418 | /* Unconditionally clear the output for simplicity */ | |
1419 | *data = 0; | |
cc4cb017 ML |
1420 | if (kvm_msr_ignored_check(vcpu, index, 0, false)) |
1421 | r = 0; | |
12bc2132 PX |
1422 | } |
1423 | ||
66421c1e WL |
1424 | if (r) |
1425 | return r; | |
801e459a TL |
1426 | |
1427 | *data = msr.data; | |
1428 | ||
1429 | return 0; | |
1430 | } | |
1431 | ||
11988499 | 1432 | static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) |
15c4a640 | 1433 | { |
1b4d56b8 | 1434 | if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) |
11988499 | 1435 | return false; |
1b2fd70c | 1436 | |
1b4d56b8 | 1437 | if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) |
11988499 | 1438 | return false; |
d8017474 | 1439 | |
0a629563 SC |
1440 | if (efer & (EFER_LME | EFER_LMA) && |
1441 | !guest_cpuid_has(vcpu, X86_FEATURE_LM)) | |
1442 | return false; | |
1443 | ||
1444 | if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) | |
1445 | return false; | |
d8017474 | 1446 | |
384bb783 | 1447 | return true; |
11988499 SC |
1448 | |
1449 | } | |
1450 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) | |
1451 | { | |
1452 | if (efer & efer_reserved_bits) | |
1453 | return false; | |
1454 | ||
1455 | return __kvm_valid_efer(vcpu, efer); | |
384bb783 JK |
1456 | } |
1457 | EXPORT_SYMBOL_GPL(kvm_valid_efer); | |
1458 | ||
11988499 | 1459 | static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
384bb783 JK |
1460 | { |
1461 | u64 old_efer = vcpu->arch.efer; | |
11988499 | 1462 | u64 efer = msr_info->data; |
72f211ec | 1463 | int r; |
384bb783 | 1464 | |
11988499 | 1465 | if (efer & efer_reserved_bits) |
66f61c92 | 1466 | return 1; |
384bb783 | 1467 | |
11988499 SC |
1468 | if (!msr_info->host_initiated) { |
1469 | if (!__kvm_valid_efer(vcpu, efer)) | |
1470 | return 1; | |
1471 | ||
1472 | if (is_paging(vcpu) && | |
1473 | (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) | |
1474 | return 1; | |
1475 | } | |
384bb783 | 1476 | |
15c4a640 | 1477 | efer &= ~EFER_LMA; |
f6801dff | 1478 | efer |= vcpu->arch.efer & EFER_LMA; |
15c4a640 | 1479 | |
72f211ec ML |
1480 | r = kvm_x86_ops.set_efer(vcpu, efer); |
1481 | if (r) { | |
1482 | WARN_ON(r > 0); | |
1483 | return r; | |
1484 | } | |
a3d204e2 | 1485 | |
aad82703 SY |
1486 | /* Update reserved bits */ |
1487 | if ((efer ^ old_efer) & EFER_NX) | |
1488 | kvm_mmu_reset_context(vcpu); | |
1489 | ||
b69e8cae | 1490 | return 0; |
15c4a640 CO |
1491 | } |
1492 | ||
f2b4b7dd JR |
1493 | void kvm_enable_efer_bits(u64 mask) |
1494 | { | |
1495 | efer_reserved_bits &= ~mask; | |
1496 | } | |
1497 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
1498 | ||
51de8151 AG |
1499 | bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type) |
1500 | { | |
1a155254 AG |
1501 | struct kvm *kvm = vcpu->kvm; |
1502 | struct msr_bitmap_range *ranges = kvm->arch.msr_filter.ranges; | |
1503 | u32 count = kvm->arch.msr_filter.count; | |
1504 | u32 i; | |
1505 | bool r = kvm->arch.msr_filter.default_allow; | |
1506 | int idx; | |
1507 | ||
9389b9d5 SC |
1508 | /* MSR filtering not set up or x2APIC enabled, allow everything */ |
1509 | if (!count || (index >= 0x800 && index <= 0x8ff)) | |
1a155254 AG |
1510 | return true; |
1511 | ||
1512 | /* Prevent collision with set_msr_filter */ | |
1513 | idx = srcu_read_lock(&kvm->srcu); | |
1514 | ||
1515 | for (i = 0; i < count; i++) { | |
1516 | u32 start = ranges[i].base; | |
1517 | u32 end = start + ranges[i].nmsrs; | |
1518 | u32 flags = ranges[i].flags; | |
1519 | unsigned long *bitmap = ranges[i].bitmap; | |
1520 | ||
1521 | if ((index >= start) && (index < end) && (flags & type)) { | |
1522 | r = !!test_bit(index - start, bitmap); | |
1523 | break; | |
1524 | } | |
1525 | } | |
1526 | ||
1527 | srcu_read_unlock(&kvm->srcu, idx); | |
1528 | ||
1529 | return r; | |
51de8151 AG |
1530 | } |
1531 | EXPORT_SYMBOL_GPL(kvm_msr_allowed); | |
1532 | ||
15c4a640 | 1533 | /* |
f20935d8 SC |
1534 | * Write @data into the MSR specified by @index. Select MSR specific fault |
1535 | * checks are bypassed if @host_initiated is %true. | |
15c4a640 CO |
1536 | * Returns 0 on success, non-0 otherwise. |
1537 | * Assumes vcpu_load() was already called. | |
1538 | */ | |
f20935d8 SC |
1539 | static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, |
1540 | bool host_initiated) | |
15c4a640 | 1541 | { |
f20935d8 SC |
1542 | struct msr_data msr; |
1543 | ||
1a155254 | 1544 | if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE)) |
cc4cb017 | 1545 | return KVM_MSR_RET_FILTERED; |
1a155254 | 1546 | |
f20935d8 | 1547 | switch (index) { |
854e8bb1 NA |
1548 | case MSR_FS_BASE: |
1549 | case MSR_GS_BASE: | |
1550 | case MSR_KERNEL_GS_BASE: | |
1551 | case MSR_CSTAR: | |
1552 | case MSR_LSTAR: | |
f20935d8 | 1553 | if (is_noncanonical_address(data, vcpu)) |
854e8bb1 NA |
1554 | return 1; |
1555 | break; | |
1556 | case MSR_IA32_SYSENTER_EIP: | |
1557 | case MSR_IA32_SYSENTER_ESP: | |
1558 | /* | |
1559 | * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if | |
1560 | * non-canonical address is written on Intel but not on | |
1561 | * AMD (which ignores the top 32-bits, because it does | |
1562 | * not implement 64-bit SYSENTER). | |
1563 | * | |
1564 | * 64-bit code should hence be able to write a non-canonical | |
1565 | * value on AMD. Making the address canonical ensures that | |
1566 | * vmentry does not fail on Intel after writing a non-canonical | |
1567 | * value, and that something deterministic happens if the guest | |
1568 | * invokes 64-bit SYSENTER. | |
1569 | */ | |
f20935d8 | 1570 | data = get_canonical(data, vcpu_virt_addr_bits(vcpu)); |
854e8bb1 | 1571 | } |
f20935d8 SC |
1572 | |
1573 | msr.data = data; | |
1574 | msr.index = index; | |
1575 | msr.host_initiated = host_initiated; | |
1576 | ||
afaf0b2f | 1577 | return kvm_x86_ops.set_msr(vcpu, &msr); |
15c4a640 CO |
1578 | } |
1579 | ||
6abe9c13 PX |
1580 | static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu, |
1581 | u32 index, u64 data, bool host_initiated) | |
1582 | { | |
1583 | int ret = __kvm_set_msr(vcpu, index, data, host_initiated); | |
1584 | ||
1585 | if (ret == KVM_MSR_RET_INVALID) | |
cc4cb017 ML |
1586 | if (kvm_msr_ignored_check(vcpu, index, data, true)) |
1587 | ret = 0; | |
6abe9c13 PX |
1588 | |
1589 | return ret; | |
1590 | } | |
1591 | ||
313a3dc7 | 1592 | /* |
f20935d8 SC |
1593 | * Read the MSR specified by @index into @data. Select MSR specific fault |
1594 | * checks are bypassed if @host_initiated is %true. | |
1595 | * Returns 0 on success, non-0 otherwise. | |
1596 | * Assumes vcpu_load() was already called. | |
313a3dc7 | 1597 | */ |
edef5c36 PB |
1598 | int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, |
1599 | bool host_initiated) | |
609e36d3 PB |
1600 | { |
1601 | struct msr_data msr; | |
f20935d8 | 1602 | int ret; |
609e36d3 | 1603 | |
1a155254 | 1604 | if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ)) |
cc4cb017 | 1605 | return KVM_MSR_RET_FILTERED; |
1a155254 | 1606 | |
609e36d3 | 1607 | msr.index = index; |
f20935d8 | 1608 | msr.host_initiated = host_initiated; |
609e36d3 | 1609 | |
afaf0b2f | 1610 | ret = kvm_x86_ops.get_msr(vcpu, &msr); |
f20935d8 SC |
1611 | if (!ret) |
1612 | *data = msr.data; | |
1613 | return ret; | |
609e36d3 PB |
1614 | } |
1615 | ||
6abe9c13 PX |
1616 | static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu, |
1617 | u32 index, u64 *data, bool host_initiated) | |
1618 | { | |
1619 | int ret = __kvm_get_msr(vcpu, index, data, host_initiated); | |
1620 | ||
1621 | if (ret == KVM_MSR_RET_INVALID) { | |
1622 | /* Unconditionally clear *data for simplicity */ | |
1623 | *data = 0; | |
cc4cb017 ML |
1624 | if (kvm_msr_ignored_check(vcpu, index, 0, false)) |
1625 | ret = 0; | |
6abe9c13 PX |
1626 | } |
1627 | ||
1628 | return ret; | |
1629 | } | |
1630 | ||
f20935d8 | 1631 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) |
313a3dc7 | 1632 | { |
6abe9c13 | 1633 | return kvm_get_msr_ignored_check(vcpu, index, data, false); |
f20935d8 SC |
1634 | } |
1635 | EXPORT_SYMBOL_GPL(kvm_get_msr); | |
8fe8ab46 | 1636 | |
f20935d8 SC |
1637 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) |
1638 | { | |
6abe9c13 | 1639 | return kvm_set_msr_ignored_check(vcpu, index, data, false); |
f20935d8 SC |
1640 | } |
1641 | EXPORT_SYMBOL_GPL(kvm_set_msr); | |
1642 | ||
1ae09954 AG |
1643 | static int complete_emulated_msr(struct kvm_vcpu *vcpu, bool is_read) |
1644 | { | |
1645 | if (vcpu->run->msr.error) { | |
1646 | kvm_inject_gp(vcpu, 0); | |
1647 | return 1; | |
1648 | } else if (is_read) { | |
1649 | kvm_rax_write(vcpu, (u32)vcpu->run->msr.data); | |
1650 | kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32); | |
1651 | } | |
1652 | ||
1653 | return kvm_skip_emulated_instruction(vcpu); | |
1654 | } | |
1655 | ||
1656 | static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu) | |
1657 | { | |
1658 | return complete_emulated_msr(vcpu, true); | |
1659 | } | |
1660 | ||
1661 | static int complete_emulated_wrmsr(struct kvm_vcpu *vcpu) | |
1662 | { | |
1663 | return complete_emulated_msr(vcpu, false); | |
1664 | } | |
1665 | ||
1666 | static u64 kvm_msr_reason(int r) | |
1667 | { | |
1668 | switch (r) { | |
cc4cb017 | 1669 | case KVM_MSR_RET_INVALID: |
1ae09954 | 1670 | return KVM_MSR_EXIT_REASON_UNKNOWN; |
cc4cb017 | 1671 | case KVM_MSR_RET_FILTERED: |
1a155254 | 1672 | return KVM_MSR_EXIT_REASON_FILTER; |
1ae09954 AG |
1673 | default: |
1674 | return KVM_MSR_EXIT_REASON_INVAL; | |
1675 | } | |
1676 | } | |
1677 | ||
1678 | static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index, | |
1679 | u32 exit_reason, u64 data, | |
1680 | int (*completion)(struct kvm_vcpu *vcpu), | |
1681 | int r) | |
1682 | { | |
1683 | u64 msr_reason = kvm_msr_reason(r); | |
1684 | ||
1685 | /* Check if the user wanted to know about this MSR fault */ | |
1686 | if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason)) | |
1687 | return 0; | |
1688 | ||
1689 | vcpu->run->exit_reason = exit_reason; | |
1690 | vcpu->run->msr.error = 0; | |
1691 | memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad)); | |
1692 | vcpu->run->msr.reason = msr_reason; | |
1693 | vcpu->run->msr.index = index; | |
1694 | vcpu->run->msr.data = data; | |
1695 | vcpu->arch.complete_userspace_io = completion; | |
1696 | ||
1697 | return 1; | |
1698 | } | |
1699 | ||
1700 | static int kvm_get_msr_user_space(struct kvm_vcpu *vcpu, u32 index, int r) | |
1701 | { | |
1702 | return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_RDMSR, 0, | |
1703 | complete_emulated_rdmsr, r); | |
1704 | } | |
1705 | ||
1706 | static int kvm_set_msr_user_space(struct kvm_vcpu *vcpu, u32 index, u64 data, int r) | |
1707 | { | |
1708 | return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_WRMSR, data, | |
1709 | complete_emulated_wrmsr, r); | |
1710 | } | |
1711 | ||
1edce0a9 SC |
1712 | int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) |
1713 | { | |
1714 | u32 ecx = kvm_rcx_read(vcpu); | |
1715 | u64 data; | |
1ae09954 AG |
1716 | int r; |
1717 | ||
1718 | r = kvm_get_msr(vcpu, ecx, &data); | |
1edce0a9 | 1719 | |
1ae09954 AG |
1720 | /* MSR read failed? See if we should ask user space */ |
1721 | if (r && kvm_get_msr_user_space(vcpu, ecx, r)) { | |
1722 | /* Bounce to user space */ | |
1723 | return 0; | |
1724 | } | |
1725 | ||
1726 | /* MSR read failed? Inject a #GP */ | |
1727 | if (r) { | |
1edce0a9 SC |
1728 | trace_kvm_msr_read_ex(ecx); |
1729 | kvm_inject_gp(vcpu, 0); | |
1730 | return 1; | |
1731 | } | |
1732 | ||
1733 | trace_kvm_msr_read(ecx, data); | |
1734 | ||
1735 | kvm_rax_write(vcpu, data & -1u); | |
1736 | kvm_rdx_write(vcpu, (data >> 32) & -1u); | |
1737 | return kvm_skip_emulated_instruction(vcpu); | |
1738 | } | |
1739 | EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); | |
1740 | ||
1741 | int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) | |
1742 | { | |
1743 | u32 ecx = kvm_rcx_read(vcpu); | |
1744 | u64 data = kvm_read_edx_eax(vcpu); | |
1ae09954 | 1745 | int r; |
1edce0a9 | 1746 | |
1ae09954 AG |
1747 | r = kvm_set_msr(vcpu, ecx, data); |
1748 | ||
1749 | /* MSR write failed? See if we should ask user space */ | |
7dffecaf | 1750 | if (r && kvm_set_msr_user_space(vcpu, ecx, data, r)) |
1ae09954 AG |
1751 | /* Bounce to user space */ |
1752 | return 0; | |
7dffecaf ML |
1753 | |
1754 | /* Signal all other negative errors to userspace */ | |
1755 | if (r < 0) | |
1756 | return r; | |
1ae09954 AG |
1757 | |
1758 | /* MSR write failed? Inject a #GP */ | |
7dffecaf | 1759 | if (r > 0) { |
1edce0a9 SC |
1760 | trace_kvm_msr_write_ex(ecx, data); |
1761 | kvm_inject_gp(vcpu, 0); | |
1762 | return 1; | |
1763 | } | |
1764 | ||
1765 | trace_kvm_msr_write(ecx, data); | |
1766 | return kvm_skip_emulated_instruction(vcpu); | |
1767 | } | |
1768 | EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); | |
1769 | ||
5a9f5443 WL |
1770 | bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu) |
1771 | { | |
1772 | return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) || | |
72c3c0fe | 1773 | xfer_to_guest_mode_work_pending(); |
5a9f5443 WL |
1774 | } |
1775 | EXPORT_SYMBOL_GPL(kvm_vcpu_exit_request); | |
1776 | ||
1e9e2622 WL |
1777 | /* |
1778 | * The fast path for frequent and performance sensitive wrmsr emulation, | |
1779 | * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces | |
1780 | * the latency of virtual IPI by avoiding the expensive bits of transitioning | |
1781 | * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the | |
1782 | * other cases which must be called after interrupts are enabled on the host. | |
1783 | */ | |
1784 | static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data) | |
1785 | { | |
e1be9ac8 WL |
1786 | if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic)) |
1787 | return 1; | |
1788 | ||
1789 | if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) && | |
1e9e2622 | 1790 | ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) && |
4064a4c6 WL |
1791 | ((data & APIC_MODE_MASK) == APIC_DM_FIXED) && |
1792 | ((u32)(data >> 32) != X2APIC_BROADCAST)) { | |
1e9e2622 | 1793 | |
d5361678 WL |
1794 | data &= ~(1 << 12); |
1795 | kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32)); | |
1e9e2622 | 1796 | kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32)); |
d5361678 WL |
1797 | kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data); |
1798 | trace_kvm_apic_write(APIC_ICR, (u32)data); | |
1799 | return 0; | |
1e9e2622 WL |
1800 | } |
1801 | ||
1802 | return 1; | |
1803 | } | |
1804 | ||
ae95f566 WL |
1805 | static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data) |
1806 | { | |
1807 | if (!kvm_can_use_hv_timer(vcpu)) | |
1808 | return 1; | |
1809 | ||
1810 | kvm_set_lapic_tscdeadline_msr(vcpu, data); | |
1811 | return 0; | |
1812 | } | |
1813 | ||
404d5d7b | 1814 | fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu) |
1e9e2622 WL |
1815 | { |
1816 | u32 msr = kvm_rcx_read(vcpu); | |
8a1038de | 1817 | u64 data; |
404d5d7b | 1818 | fastpath_t ret = EXIT_FASTPATH_NONE; |
1e9e2622 WL |
1819 | |
1820 | switch (msr) { | |
1821 | case APIC_BASE_MSR + (APIC_ICR >> 4): | |
8a1038de | 1822 | data = kvm_read_edx_eax(vcpu); |
404d5d7b WL |
1823 | if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) { |
1824 | kvm_skip_emulated_instruction(vcpu); | |
1825 | ret = EXIT_FASTPATH_EXIT_HANDLED; | |
80bc97f2 | 1826 | } |
1e9e2622 | 1827 | break; |
ae95f566 WL |
1828 | case MSR_IA32_TSCDEADLINE: |
1829 | data = kvm_read_edx_eax(vcpu); | |
1830 | if (!handle_fastpath_set_tscdeadline(vcpu, data)) { | |
1831 | kvm_skip_emulated_instruction(vcpu); | |
1832 | ret = EXIT_FASTPATH_REENTER_GUEST; | |
1833 | } | |
1834 | break; | |
1e9e2622 | 1835 | default: |
404d5d7b | 1836 | break; |
1e9e2622 WL |
1837 | } |
1838 | ||
404d5d7b | 1839 | if (ret != EXIT_FASTPATH_NONE) |
1e9e2622 | 1840 | trace_kvm_msr_write(msr, data); |
1e9e2622 | 1841 | |
404d5d7b | 1842 | return ret; |
1e9e2622 WL |
1843 | } |
1844 | EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); | |
1845 | ||
f20935d8 SC |
1846 | /* |
1847 | * Adapt set_msr() to msr_io()'s calling convention | |
1848 | */ | |
1849 | static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
1850 | { | |
6abe9c13 | 1851 | return kvm_get_msr_ignored_check(vcpu, index, data, true); |
f20935d8 SC |
1852 | } |
1853 | ||
1854 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
1855 | { | |
6abe9c13 | 1856 | return kvm_set_msr_ignored_check(vcpu, index, *data, true); |
313a3dc7 CO |
1857 | } |
1858 | ||
16e8d74d | 1859 | #ifdef CONFIG_X86_64 |
53fafdbb MT |
1860 | struct pvclock_clock { |
1861 | int vclock_mode; | |
1862 | u64 cycle_last; | |
1863 | u64 mask; | |
1864 | u32 mult; | |
1865 | u32 shift; | |
917f9475 PB |
1866 | u64 base_cycles; |
1867 | u64 offset; | |
53fafdbb MT |
1868 | }; |
1869 | ||
16e8d74d MT |
1870 | struct pvclock_gtod_data { |
1871 | seqcount_t seq; | |
1872 | ||
53fafdbb MT |
1873 | struct pvclock_clock clock; /* extract of a clocksource struct */ |
1874 | struct pvclock_clock raw_clock; /* extract of a clocksource struct */ | |
16e8d74d | 1875 | |
917f9475 | 1876 | ktime_t offs_boot; |
55dd00a7 | 1877 | u64 wall_time_sec; |
16e8d74d MT |
1878 | }; |
1879 | ||
1880 | static struct pvclock_gtod_data pvclock_gtod_data; | |
1881 | ||
1882 | static void update_pvclock_gtod(struct timekeeper *tk) | |
1883 | { | |
1884 | struct pvclock_gtod_data *vdata = &pvclock_gtod_data; | |
1885 | ||
1886 | write_seqcount_begin(&vdata->seq); | |
1887 | ||
1888 | /* copy pvclock gtod data */ | |
b95a8a27 | 1889 | vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode; |
876e7881 PZ |
1890 | vdata->clock.cycle_last = tk->tkr_mono.cycle_last; |
1891 | vdata->clock.mask = tk->tkr_mono.mask; | |
1892 | vdata->clock.mult = tk->tkr_mono.mult; | |
1893 | vdata->clock.shift = tk->tkr_mono.shift; | |
917f9475 PB |
1894 | vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec; |
1895 | vdata->clock.offset = tk->tkr_mono.base; | |
16e8d74d | 1896 | |
b95a8a27 | 1897 | vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode; |
53fafdbb MT |
1898 | vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last; |
1899 | vdata->raw_clock.mask = tk->tkr_raw.mask; | |
1900 | vdata->raw_clock.mult = tk->tkr_raw.mult; | |
1901 | vdata->raw_clock.shift = tk->tkr_raw.shift; | |
917f9475 PB |
1902 | vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec; |
1903 | vdata->raw_clock.offset = tk->tkr_raw.base; | |
16e8d74d | 1904 | |
55dd00a7 MT |
1905 | vdata->wall_time_sec = tk->xtime_sec; |
1906 | ||
917f9475 | 1907 | vdata->offs_boot = tk->offs_boot; |
53fafdbb | 1908 | |
16e8d74d MT |
1909 | write_seqcount_end(&vdata->seq); |
1910 | } | |
8171cd68 PB |
1911 | |
1912 | static s64 get_kvmclock_base_ns(void) | |
1913 | { | |
1914 | /* Count up from boot time, but with the frequency of the raw clock. */ | |
1915 | return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot)); | |
1916 | } | |
1917 | #else | |
1918 | static s64 get_kvmclock_base_ns(void) | |
1919 | { | |
1920 | /* Master clock not used, so we can just use CLOCK_BOOTTIME. */ | |
1921 | return ktime_get_boottime_ns(); | |
1922 | } | |
16e8d74d MT |
1923 | #endif |
1924 | ||
18068523 GOC |
1925 | static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) |
1926 | { | |
9ed3c444 AK |
1927 | int version; |
1928 | int r; | |
50d0a0f9 | 1929 | struct pvclock_wall_clock wc; |
8171cd68 | 1930 | u64 wall_nsec; |
18068523 | 1931 | |
210dfd93 OU |
1932 | kvm->arch.wall_clock = wall_clock; |
1933 | ||
18068523 GOC |
1934 | if (!wall_clock) |
1935 | return; | |
1936 | ||
9ed3c444 AK |
1937 | r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); |
1938 | if (r) | |
1939 | return; | |
1940 | ||
1941 | if (version & 1) | |
1942 | ++version; /* first time write, random junk */ | |
1943 | ||
1944 | ++version; | |
18068523 | 1945 | |
1dab1345 NK |
1946 | if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) |
1947 | return; | |
18068523 | 1948 | |
50d0a0f9 GH |
1949 | /* |
1950 | * The guest calculates current wall clock time by adding | |
34c238a1 | 1951 | * system time (updated by kvm_guest_time_update below) to the |
8171cd68 | 1952 | * wall clock specified here. We do the reverse here. |
50d0a0f9 | 1953 | */ |
8171cd68 | 1954 | wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm); |
50d0a0f9 | 1955 | |
8171cd68 PB |
1956 | wc.nsec = do_div(wall_nsec, 1000000000); |
1957 | wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */ | |
50d0a0f9 | 1958 | wc.version = version; |
18068523 GOC |
1959 | |
1960 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
1961 | ||
1962 | version++; | |
1963 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
1964 | } |
1965 | ||
5b9bb0eb OU |
1966 | static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time, |
1967 | bool old_msr, bool host_initiated) | |
1968 | { | |
1969 | struct kvm_arch *ka = &vcpu->kvm->arch; | |
1970 | ||
1971 | if (vcpu->vcpu_id == 0 && !host_initiated) { | |
1e293d1a | 1972 | if (ka->boot_vcpu_runs_old_kvmclock != old_msr) |
5b9bb0eb OU |
1973 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
1974 | ||
1975 | ka->boot_vcpu_runs_old_kvmclock = old_msr; | |
1976 | } | |
1977 | ||
1978 | vcpu->arch.time = system_time; | |
1979 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); | |
1980 | ||
1981 | /* we verify if the enable bit is set... */ | |
1982 | vcpu->arch.pv_time_enabled = false; | |
1983 | if (!(system_time & 1)) | |
1984 | return; | |
1985 | ||
1986 | if (!kvm_gfn_to_hva_cache_init(vcpu->kvm, | |
1987 | &vcpu->arch.pv_time, system_time & ~1ULL, | |
1988 | sizeof(struct pvclock_vcpu_time_info))) | |
1989 | vcpu->arch.pv_time_enabled = true; | |
1990 | ||
1991 | return; | |
1992 | } | |
1993 | ||
50d0a0f9 GH |
1994 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
1995 | { | |
b51012de PB |
1996 | do_shl32_div32(dividend, divisor); |
1997 | return dividend; | |
50d0a0f9 GH |
1998 | } |
1999 | ||
3ae13faa | 2000 | static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, |
5f4e3f88 | 2001 | s8 *pshift, u32 *pmultiplier) |
50d0a0f9 | 2002 | { |
5f4e3f88 | 2003 | uint64_t scaled64; |
50d0a0f9 GH |
2004 | int32_t shift = 0; |
2005 | uint64_t tps64; | |
2006 | uint32_t tps32; | |
2007 | ||
3ae13faa PB |
2008 | tps64 = base_hz; |
2009 | scaled64 = scaled_hz; | |
50933623 | 2010 | while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { |
50d0a0f9 GH |
2011 | tps64 >>= 1; |
2012 | shift--; | |
2013 | } | |
2014 | ||
2015 | tps32 = (uint32_t)tps64; | |
50933623 JK |
2016 | while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { |
2017 | if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) | |
5f4e3f88 ZA |
2018 | scaled64 >>= 1; |
2019 | else | |
2020 | tps32 <<= 1; | |
50d0a0f9 GH |
2021 | shift++; |
2022 | } | |
2023 | ||
5f4e3f88 ZA |
2024 | *pshift = shift; |
2025 | *pmultiplier = div_frac(scaled64, tps32); | |
50d0a0f9 GH |
2026 | } |
2027 | ||
d828199e | 2028 | #ifdef CONFIG_X86_64 |
16e8d74d | 2029 | static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); |
d828199e | 2030 | #endif |
16e8d74d | 2031 | |
c8076604 | 2032 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
69b0049a | 2033 | static unsigned long max_tsc_khz; |
c8076604 | 2034 | |
cc578287 | 2035 | static u32 adjust_tsc_khz(u32 khz, s32 ppm) |
1e993611 | 2036 | { |
cc578287 ZA |
2037 | u64 v = (u64)khz * (1000000 + ppm); |
2038 | do_div(v, 1000000); | |
2039 | return v; | |
1e993611 JR |
2040 | } |
2041 | ||
381d585c HZ |
2042 | static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) |
2043 | { | |
2044 | u64 ratio; | |
2045 | ||
2046 | /* Guest TSC same frequency as host TSC? */ | |
2047 | if (!scale) { | |
2048 | vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; | |
2049 | return 0; | |
2050 | } | |
2051 | ||
2052 | /* TSC scaling supported? */ | |
2053 | if (!kvm_has_tsc_control) { | |
2054 | if (user_tsc_khz > tsc_khz) { | |
2055 | vcpu->arch.tsc_catchup = 1; | |
2056 | vcpu->arch.tsc_always_catchup = 1; | |
2057 | return 0; | |
2058 | } else { | |
3f16a5c3 | 2059 | pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); |
381d585c HZ |
2060 | return -1; |
2061 | } | |
2062 | } | |
2063 | ||
2064 | /* TSC scaling required - calculate ratio */ | |
2065 | ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, | |
2066 | user_tsc_khz, tsc_khz); | |
2067 | ||
2068 | if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { | |
3f16a5c3 PB |
2069 | pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", |
2070 | user_tsc_khz); | |
381d585c HZ |
2071 | return -1; |
2072 | } | |
2073 | ||
2074 | vcpu->arch.tsc_scaling_ratio = ratio; | |
2075 | return 0; | |
2076 | } | |
2077 | ||
4941b8cb | 2078 | static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) |
759379dd | 2079 | { |
cc578287 ZA |
2080 | u32 thresh_lo, thresh_hi; |
2081 | int use_scaling = 0; | |
217fc9cf | 2082 | |
03ba32ca | 2083 | /* tsc_khz can be zero if TSC calibration fails */ |
4941b8cb | 2084 | if (user_tsc_khz == 0) { |
ad721883 HZ |
2085 | /* set tsc_scaling_ratio to a safe value */ |
2086 | vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; | |
381d585c | 2087 | return -1; |
ad721883 | 2088 | } |
03ba32ca | 2089 | |
c285545f | 2090 | /* Compute a scale to convert nanoseconds in TSC cycles */ |
3ae13faa | 2091 | kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, |
cc578287 ZA |
2092 | &vcpu->arch.virtual_tsc_shift, |
2093 | &vcpu->arch.virtual_tsc_mult); | |
4941b8cb | 2094 | vcpu->arch.virtual_tsc_khz = user_tsc_khz; |
cc578287 ZA |
2095 | |
2096 | /* | |
2097 | * Compute the variation in TSC rate which is acceptable | |
2098 | * within the range of tolerance and decide if the | |
2099 | * rate being applied is within that bounds of the hardware | |
2100 | * rate. If so, no scaling or compensation need be done. | |
2101 | */ | |
2102 | thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); | |
2103 | thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); | |
4941b8cb PB |
2104 | if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { |
2105 | pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); | |
cc578287 ZA |
2106 | use_scaling = 1; |
2107 | } | |
4941b8cb | 2108 | return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); |
c285545f ZA |
2109 | } |
2110 | ||
2111 | static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) | |
2112 | { | |
e26101b1 | 2113 | u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, |
cc578287 ZA |
2114 | vcpu->arch.virtual_tsc_mult, |
2115 | vcpu->arch.virtual_tsc_shift); | |
e26101b1 | 2116 | tsc += vcpu->arch.this_tsc_write; |
c285545f ZA |
2117 | return tsc; |
2118 | } | |
2119 | ||
b0c39dc6 VK |
2120 | static inline int gtod_is_based_on_tsc(int mode) |
2121 | { | |
b95a8a27 | 2122 | return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK; |
b0c39dc6 VK |
2123 | } |
2124 | ||
69b0049a | 2125 | static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) |
b48aa97e MT |
2126 | { |
2127 | #ifdef CONFIG_X86_64 | |
2128 | bool vcpus_matched; | |
b48aa97e MT |
2129 | struct kvm_arch *ka = &vcpu->kvm->arch; |
2130 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
2131 | ||
2132 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
2133 | atomic_read(&vcpu->kvm->online_vcpus)); | |
2134 | ||
7f187922 MT |
2135 | /* |
2136 | * Once the masterclock is enabled, always perform request in | |
2137 | * order to update it. | |
2138 | * | |
2139 | * In order to enable masterclock, the host clocksource must be TSC | |
2140 | * and the vcpus need to have matched TSCs. When that happens, | |
2141 | * perform request to enable masterclock. | |
2142 | */ | |
2143 | if (ka->use_master_clock || | |
b0c39dc6 | 2144 | (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) |
b48aa97e MT |
2145 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
2146 | ||
2147 | trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, | |
2148 | atomic_read(&vcpu->kvm->online_vcpus), | |
2149 | ka->use_master_clock, gtod->clock.vclock_mode); | |
2150 | #endif | |
2151 | } | |
2152 | ||
35181e86 HZ |
2153 | /* |
2154 | * Multiply tsc by a fixed point number represented by ratio. | |
2155 | * | |
2156 | * The most significant 64-N bits (mult) of ratio represent the | |
2157 | * integral part of the fixed point number; the remaining N bits | |
2158 | * (frac) represent the fractional part, ie. ratio represents a fixed | |
2159 | * point number (mult + frac * 2^(-N)). | |
2160 | * | |
2161 | * N equals to kvm_tsc_scaling_ratio_frac_bits. | |
2162 | */ | |
2163 | static inline u64 __scale_tsc(u64 ratio, u64 tsc) | |
2164 | { | |
2165 | return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); | |
2166 | } | |
2167 | ||
2168 | u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) | |
2169 | { | |
2170 | u64 _tsc = tsc; | |
2171 | u64 ratio = vcpu->arch.tsc_scaling_ratio; | |
2172 | ||
2173 | if (ratio != kvm_default_tsc_scaling_ratio) | |
2174 | _tsc = __scale_tsc(ratio, tsc); | |
2175 | ||
2176 | return _tsc; | |
2177 | } | |
2178 | EXPORT_SYMBOL_GPL(kvm_scale_tsc); | |
2179 | ||
07c1419a HZ |
2180 | static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) |
2181 | { | |
2182 | u64 tsc; | |
2183 | ||
2184 | tsc = kvm_scale_tsc(vcpu, rdtsc()); | |
2185 | ||
2186 | return target_tsc - tsc; | |
2187 | } | |
2188 | ||
4ba76538 HZ |
2189 | u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) |
2190 | { | |
56ba77a4 | 2191 | return vcpu->arch.l1_tsc_offset + kvm_scale_tsc(vcpu, host_tsc); |
4ba76538 HZ |
2192 | } |
2193 | EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); | |
2194 | ||
a545ab6a LC |
2195 | static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
2196 | { | |
56ba77a4 | 2197 | vcpu->arch.l1_tsc_offset = offset; |
afaf0b2f | 2198 | vcpu->arch.tsc_offset = kvm_x86_ops.write_l1_tsc_offset(vcpu, offset); |
a545ab6a LC |
2199 | } |
2200 | ||
b0c39dc6 VK |
2201 | static inline bool kvm_check_tsc_unstable(void) |
2202 | { | |
2203 | #ifdef CONFIG_X86_64 | |
2204 | /* | |
2205 | * TSC is marked unstable when we're running on Hyper-V, | |
2206 | * 'TSC page' clocksource is good. | |
2207 | */ | |
b95a8a27 | 2208 | if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK) |
b0c39dc6 VK |
2209 | return false; |
2210 | #endif | |
2211 | return check_tsc_unstable(); | |
2212 | } | |
2213 | ||
0c899c25 | 2214 | static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data) |
99e3e30a ZA |
2215 | { |
2216 | struct kvm *kvm = vcpu->kvm; | |
f38e098f | 2217 | u64 offset, ns, elapsed; |
99e3e30a | 2218 | unsigned long flags; |
b48aa97e | 2219 | bool matched; |
0d3da0d2 | 2220 | bool already_matched; |
c5e8ec8e | 2221 | bool synchronizing = false; |
99e3e30a | 2222 | |
038f8c11 | 2223 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); |
07c1419a | 2224 | offset = kvm_compute_tsc_offset(vcpu, data); |
8171cd68 | 2225 | ns = get_kvmclock_base_ns(); |
f38e098f | 2226 | elapsed = ns - kvm->arch.last_tsc_nsec; |
5d3cb0f6 | 2227 | |
03ba32ca | 2228 | if (vcpu->arch.virtual_tsc_khz) { |
0c899c25 | 2229 | if (data == 0) { |
bd8fab39 DP |
2230 | /* |
2231 | * detection of vcpu initialization -- need to sync | |
2232 | * with other vCPUs. This particularly helps to keep | |
2233 | * kvm_clock stable after CPU hotplug | |
2234 | */ | |
2235 | synchronizing = true; | |
2236 | } else { | |
2237 | u64 tsc_exp = kvm->arch.last_tsc_write + | |
2238 | nsec_to_cycles(vcpu, elapsed); | |
2239 | u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; | |
2240 | /* | |
2241 | * Special case: TSC write with a small delta (1 second) | |
2242 | * of virtual cycle time against real time is | |
2243 | * interpreted as an attempt to synchronize the CPU. | |
2244 | */ | |
2245 | synchronizing = data < tsc_exp + tsc_hz && | |
2246 | data + tsc_hz > tsc_exp; | |
2247 | } | |
c5e8ec8e | 2248 | } |
f38e098f ZA |
2249 | |
2250 | /* | |
5d3cb0f6 ZA |
2251 | * For a reliable TSC, we can match TSC offsets, and for an unstable |
2252 | * TSC, we add elapsed time in this computation. We could let the | |
2253 | * compensation code attempt to catch up if we fall behind, but | |
2254 | * it's better to try to match offsets from the beginning. | |
2255 | */ | |
c5e8ec8e | 2256 | if (synchronizing && |
5d3cb0f6 | 2257 | vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { |
b0c39dc6 | 2258 | if (!kvm_check_tsc_unstable()) { |
e26101b1 | 2259 | offset = kvm->arch.cur_tsc_offset; |
f38e098f | 2260 | } else { |
857e4099 | 2261 | u64 delta = nsec_to_cycles(vcpu, elapsed); |
5d3cb0f6 | 2262 | data += delta; |
07c1419a | 2263 | offset = kvm_compute_tsc_offset(vcpu, data); |
f38e098f | 2264 | } |
b48aa97e | 2265 | matched = true; |
0d3da0d2 | 2266 | already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); |
e26101b1 ZA |
2267 | } else { |
2268 | /* | |
2269 | * We split periods of matched TSC writes into generations. | |
2270 | * For each generation, we track the original measured | |
2271 | * nanosecond time, offset, and write, so if TSCs are in | |
2272 | * sync, we can match exact offset, and if not, we can match | |
4a969980 | 2273 | * exact software computation in compute_guest_tsc() |
e26101b1 ZA |
2274 | * |
2275 | * These values are tracked in kvm->arch.cur_xxx variables. | |
2276 | */ | |
2277 | kvm->arch.cur_tsc_generation++; | |
2278 | kvm->arch.cur_tsc_nsec = ns; | |
2279 | kvm->arch.cur_tsc_write = data; | |
2280 | kvm->arch.cur_tsc_offset = offset; | |
b48aa97e | 2281 | matched = false; |
f38e098f | 2282 | } |
e26101b1 ZA |
2283 | |
2284 | /* | |
2285 | * We also track th most recent recorded KHZ, write and time to | |
2286 | * allow the matching interval to be extended at each write. | |
2287 | */ | |
f38e098f ZA |
2288 | kvm->arch.last_tsc_nsec = ns; |
2289 | kvm->arch.last_tsc_write = data; | |
5d3cb0f6 | 2290 | kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; |
99e3e30a | 2291 | |
b183aa58 | 2292 | vcpu->arch.last_guest_tsc = data; |
e26101b1 ZA |
2293 | |
2294 | /* Keep track of which generation this VCPU has synchronized to */ | |
2295 | vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; | |
2296 | vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; | |
2297 | vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; | |
2298 | ||
a545ab6a | 2299 | kvm_vcpu_write_tsc_offset(vcpu, offset); |
e26101b1 | 2300 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); |
b48aa97e MT |
2301 | |
2302 | spin_lock(&kvm->arch.pvclock_gtod_sync_lock); | |
0d3da0d2 | 2303 | if (!matched) { |
b48aa97e | 2304 | kvm->arch.nr_vcpus_matched_tsc = 0; |
0d3da0d2 TG |
2305 | } else if (!already_matched) { |
2306 | kvm->arch.nr_vcpus_matched_tsc++; | |
2307 | } | |
b48aa97e MT |
2308 | |
2309 | kvm_track_tsc_matching(vcpu); | |
2310 | spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); | |
99e3e30a | 2311 | } |
e26101b1 | 2312 | |
58ea6767 HZ |
2313 | static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, |
2314 | s64 adjustment) | |
2315 | { | |
56ba77a4 | 2316 | u64 tsc_offset = vcpu->arch.l1_tsc_offset; |
326e7425 | 2317 | kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); |
58ea6767 HZ |
2318 | } |
2319 | ||
2320 | static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) | |
2321 | { | |
2322 | if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) | |
2323 | WARN_ON(adjustment < 0); | |
2324 | adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); | |
ea26e4ec | 2325 | adjust_tsc_offset_guest(vcpu, adjustment); |
58ea6767 HZ |
2326 | } |
2327 | ||
d828199e MT |
2328 | #ifdef CONFIG_X86_64 |
2329 | ||
a5a1d1c2 | 2330 | static u64 read_tsc(void) |
d828199e | 2331 | { |
a5a1d1c2 | 2332 | u64 ret = (u64)rdtsc_ordered(); |
03b9730b | 2333 | u64 last = pvclock_gtod_data.clock.cycle_last; |
d828199e MT |
2334 | |
2335 | if (likely(ret >= last)) | |
2336 | return ret; | |
2337 | ||
2338 | /* | |
2339 | * GCC likes to generate cmov here, but this branch is extremely | |
6a6256f9 | 2340 | * predictable (it's just a function of time and the likely is |
d828199e MT |
2341 | * very likely) and there's a data dependence, so force GCC |
2342 | * to generate a branch instead. I don't barrier() because | |
2343 | * we don't actually need a barrier, and if this function | |
2344 | * ever gets inlined it will generate worse code. | |
2345 | */ | |
2346 | asm volatile (""); | |
2347 | return last; | |
2348 | } | |
2349 | ||
53fafdbb MT |
2350 | static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, |
2351 | int *mode) | |
d828199e MT |
2352 | { |
2353 | long v; | |
b0c39dc6 VK |
2354 | u64 tsc_pg_val; |
2355 | ||
53fafdbb | 2356 | switch (clock->vclock_mode) { |
b95a8a27 | 2357 | case VDSO_CLOCKMODE_HVCLOCK: |
b0c39dc6 VK |
2358 | tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), |
2359 | tsc_timestamp); | |
2360 | if (tsc_pg_val != U64_MAX) { | |
2361 | /* TSC page valid */ | |
b95a8a27 | 2362 | *mode = VDSO_CLOCKMODE_HVCLOCK; |
53fafdbb MT |
2363 | v = (tsc_pg_val - clock->cycle_last) & |
2364 | clock->mask; | |
b0c39dc6 VK |
2365 | } else { |
2366 | /* TSC page invalid */ | |
b95a8a27 | 2367 | *mode = VDSO_CLOCKMODE_NONE; |
b0c39dc6 VK |
2368 | } |
2369 | break; | |
b95a8a27 TG |
2370 | case VDSO_CLOCKMODE_TSC: |
2371 | *mode = VDSO_CLOCKMODE_TSC; | |
b0c39dc6 | 2372 | *tsc_timestamp = read_tsc(); |
53fafdbb MT |
2373 | v = (*tsc_timestamp - clock->cycle_last) & |
2374 | clock->mask; | |
b0c39dc6 VK |
2375 | break; |
2376 | default: | |
b95a8a27 | 2377 | *mode = VDSO_CLOCKMODE_NONE; |
b0c39dc6 | 2378 | } |
d828199e | 2379 | |
b95a8a27 | 2380 | if (*mode == VDSO_CLOCKMODE_NONE) |
b0c39dc6 | 2381 | *tsc_timestamp = v = 0; |
d828199e | 2382 | |
53fafdbb | 2383 | return v * clock->mult; |
d828199e MT |
2384 | } |
2385 | ||
53fafdbb | 2386 | static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp) |
d828199e | 2387 | { |
cbcf2dd3 | 2388 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; |
d828199e | 2389 | unsigned long seq; |
d828199e | 2390 | int mode; |
cbcf2dd3 | 2391 | u64 ns; |
d828199e | 2392 | |
d828199e MT |
2393 | do { |
2394 | seq = read_seqcount_begin(>od->seq); | |
917f9475 | 2395 | ns = gtod->raw_clock.base_cycles; |
53fafdbb | 2396 | ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode); |
917f9475 PB |
2397 | ns >>= gtod->raw_clock.shift; |
2398 | ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot)); | |
d828199e | 2399 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); |
cbcf2dd3 | 2400 | *t = ns; |
d828199e MT |
2401 | |
2402 | return mode; | |
2403 | } | |
2404 | ||
899a31f5 | 2405 | static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) |
55dd00a7 MT |
2406 | { |
2407 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
2408 | unsigned long seq; | |
2409 | int mode; | |
2410 | u64 ns; | |
2411 | ||
2412 | do { | |
2413 | seq = read_seqcount_begin(>od->seq); | |
55dd00a7 | 2414 | ts->tv_sec = gtod->wall_time_sec; |
917f9475 | 2415 | ns = gtod->clock.base_cycles; |
53fafdbb | 2416 | ns += vgettsc(>od->clock, tsc_timestamp, &mode); |
55dd00a7 MT |
2417 | ns >>= gtod->clock.shift; |
2418 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); | |
2419 | ||
2420 | ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); | |
2421 | ts->tv_nsec = ns; | |
2422 | ||
2423 | return mode; | |
2424 | } | |
2425 | ||
b0c39dc6 VK |
2426 | /* returns true if host is using TSC based clocksource */ |
2427 | static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) | |
d828199e | 2428 | { |
d828199e | 2429 | /* checked again under seqlock below */ |
b0c39dc6 | 2430 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
d828199e MT |
2431 | return false; |
2432 | ||
53fafdbb | 2433 | return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns, |
b0c39dc6 | 2434 | tsc_timestamp)); |
d828199e | 2435 | } |
55dd00a7 | 2436 | |
b0c39dc6 | 2437 | /* returns true if host is using TSC based clocksource */ |
899a31f5 | 2438 | static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, |
b0c39dc6 | 2439 | u64 *tsc_timestamp) |
55dd00a7 MT |
2440 | { |
2441 | /* checked again under seqlock below */ | |
b0c39dc6 | 2442 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
55dd00a7 MT |
2443 | return false; |
2444 | ||
b0c39dc6 | 2445 | return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); |
55dd00a7 | 2446 | } |
d828199e MT |
2447 | #endif |
2448 | ||
2449 | /* | |
2450 | * | |
b48aa97e MT |
2451 | * Assuming a stable TSC across physical CPUS, and a stable TSC |
2452 | * across virtual CPUs, the following condition is possible. | |
2453 | * Each numbered line represents an event visible to both | |
d828199e MT |
2454 | * CPUs at the next numbered event. |
2455 | * | |
2456 | * "timespecX" represents host monotonic time. "tscX" represents | |
2457 | * RDTSC value. | |
2458 | * | |
2459 | * VCPU0 on CPU0 | VCPU1 on CPU1 | |
2460 | * | |
2461 | * 1. read timespec0,tsc0 | |
2462 | * 2. | timespec1 = timespec0 + N | |
2463 | * | tsc1 = tsc0 + M | |
2464 | * 3. transition to guest | transition to guest | |
2465 | * 4. ret0 = timespec0 + (rdtsc - tsc0) | | |
2466 | * 5. | ret1 = timespec1 + (rdtsc - tsc1) | |
2467 | * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) | |
2468 | * | |
2469 | * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: | |
2470 | * | |
2471 | * - ret0 < ret1 | |
2472 | * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) | |
2473 | * ... | |
2474 | * - 0 < N - M => M < N | |
2475 | * | |
2476 | * That is, when timespec0 != timespec1, M < N. Unfortunately that is not | |
2477 | * always the case (the difference between two distinct xtime instances | |
2478 | * might be smaller then the difference between corresponding TSC reads, | |
2479 | * when updating guest vcpus pvclock areas). | |
2480 | * | |
2481 | * To avoid that problem, do not allow visibility of distinct | |
2482 | * system_timestamp/tsc_timestamp values simultaneously: use a master | |
2483 | * copy of host monotonic time values. Update that master copy | |
2484 | * in lockstep. | |
2485 | * | |
b48aa97e | 2486 | * Rely on synchronization of host TSCs and guest TSCs for monotonicity. |
d828199e MT |
2487 | * |
2488 | */ | |
2489 | ||
2490 | static void pvclock_update_vm_gtod_copy(struct kvm *kvm) | |
2491 | { | |
2492 | #ifdef CONFIG_X86_64 | |
2493 | struct kvm_arch *ka = &kvm->arch; | |
2494 | int vclock_mode; | |
b48aa97e MT |
2495 | bool host_tsc_clocksource, vcpus_matched; |
2496 | ||
2497 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
2498 | atomic_read(&kvm->online_vcpus)); | |
d828199e MT |
2499 | |
2500 | /* | |
2501 | * If the host uses TSC clock, then passthrough TSC as stable | |
2502 | * to the guest. | |
2503 | */ | |
b48aa97e | 2504 | host_tsc_clocksource = kvm_get_time_and_clockread( |
d828199e MT |
2505 | &ka->master_kernel_ns, |
2506 | &ka->master_cycle_now); | |
2507 | ||
16a96021 | 2508 | ka->use_master_clock = host_tsc_clocksource && vcpus_matched |
a826faf1 | 2509 | && !ka->backwards_tsc_observed |
54750f2c | 2510 | && !ka->boot_vcpu_runs_old_kvmclock; |
b48aa97e | 2511 | |
d828199e MT |
2512 | if (ka->use_master_clock) |
2513 | atomic_set(&kvm_guest_has_master_clock, 1); | |
2514 | ||
2515 | vclock_mode = pvclock_gtod_data.clock.vclock_mode; | |
b48aa97e MT |
2516 | trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, |
2517 | vcpus_matched); | |
d828199e MT |
2518 | #endif |
2519 | } | |
2520 | ||
2860c4b1 PB |
2521 | void kvm_make_mclock_inprogress_request(struct kvm *kvm) |
2522 | { | |
2523 | kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); | |
2524 | } | |
2525 | ||
2e762ff7 MT |
2526 | static void kvm_gen_update_masterclock(struct kvm *kvm) |
2527 | { | |
2528 | #ifdef CONFIG_X86_64 | |
2529 | int i; | |
2530 | struct kvm_vcpu *vcpu; | |
2531 | struct kvm_arch *ka = &kvm->arch; | |
2532 | ||
2533 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
2534 | kvm_make_mclock_inprogress_request(kvm); | |
2535 | /* no guest entries from this point */ | |
2536 | pvclock_update_vm_gtod_copy(kvm); | |
2537 | ||
2538 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 2539 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
2e762ff7 MT |
2540 | |
2541 | /* guest entries allowed */ | |
2542 | kvm_for_each_vcpu(i, vcpu, kvm) | |
72875d8a | 2543 | kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); |
2e762ff7 MT |
2544 | |
2545 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
2546 | #endif | |
2547 | } | |
2548 | ||
e891a32e | 2549 | u64 get_kvmclock_ns(struct kvm *kvm) |
108b249c | 2550 | { |
108b249c | 2551 | struct kvm_arch *ka = &kvm->arch; |
8b953440 | 2552 | struct pvclock_vcpu_time_info hv_clock; |
e2c2206a | 2553 | u64 ret; |
108b249c | 2554 | |
8b953440 PB |
2555 | spin_lock(&ka->pvclock_gtod_sync_lock); |
2556 | if (!ka->use_master_clock) { | |
2557 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
8171cd68 | 2558 | return get_kvmclock_base_ns() + ka->kvmclock_offset; |
108b249c PB |
2559 | } |
2560 | ||
8b953440 PB |
2561 | hv_clock.tsc_timestamp = ka->master_cycle_now; |
2562 | hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; | |
2563 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
2564 | ||
e2c2206a WL |
2565 | /* both __this_cpu_read() and rdtsc() should be on the same cpu */ |
2566 | get_cpu(); | |
2567 | ||
e70b57a6 WL |
2568 | if (__this_cpu_read(cpu_tsc_khz)) { |
2569 | kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, | |
2570 | &hv_clock.tsc_shift, | |
2571 | &hv_clock.tsc_to_system_mul); | |
2572 | ret = __pvclock_read_cycles(&hv_clock, rdtsc()); | |
2573 | } else | |
8171cd68 | 2574 | ret = get_kvmclock_base_ns() + ka->kvmclock_offset; |
e2c2206a WL |
2575 | |
2576 | put_cpu(); | |
2577 | ||
2578 | return ret; | |
108b249c PB |
2579 | } |
2580 | ||
0d6dd2ff PB |
2581 | static void kvm_setup_pvclock_page(struct kvm_vcpu *v) |
2582 | { | |
2583 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
2584 | struct pvclock_vcpu_time_info guest_hv_clock; | |
2585 | ||
4e335d9e | 2586 | if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, |
0d6dd2ff PB |
2587 | &guest_hv_clock, sizeof(guest_hv_clock)))) |
2588 | return; | |
2589 | ||
2590 | /* This VCPU is paused, but it's legal for a guest to read another | |
2591 | * VCPU's kvmclock, so we really have to follow the specification where | |
2592 | * it says that version is odd if data is being modified, and even after | |
2593 | * it is consistent. | |
2594 | * | |
2595 | * Version field updates must be kept separate. This is because | |
2596 | * kvm_write_guest_cached might use a "rep movs" instruction, and | |
2597 | * writes within a string instruction are weakly ordered. So there | |
2598 | * are three writes overall. | |
2599 | * | |
2600 | * As a small optimization, only write the version field in the first | |
2601 | * and third write. The vcpu->pv_time cache is still valid, because the | |
2602 | * version field is the first in the struct. | |
2603 | */ | |
2604 | BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); | |
2605 | ||
51c4b8bb LA |
2606 | if (guest_hv_clock.version & 1) |
2607 | ++guest_hv_clock.version; /* first time write, random junk */ | |
2608 | ||
0d6dd2ff | 2609 | vcpu->hv_clock.version = guest_hv_clock.version + 1; |
4e335d9e PB |
2610 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
2611 | &vcpu->hv_clock, | |
2612 | sizeof(vcpu->hv_clock.version)); | |
0d6dd2ff PB |
2613 | |
2614 | smp_wmb(); | |
2615 | ||
2616 | /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ | |
2617 | vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); | |
2618 | ||
2619 | if (vcpu->pvclock_set_guest_stopped_request) { | |
2620 | vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; | |
2621 | vcpu->pvclock_set_guest_stopped_request = false; | |
2622 | } | |
2623 | ||
2624 | trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); | |
2625 | ||
4e335d9e PB |
2626 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
2627 | &vcpu->hv_clock, | |
2628 | sizeof(vcpu->hv_clock)); | |
0d6dd2ff PB |
2629 | |
2630 | smp_wmb(); | |
2631 | ||
2632 | vcpu->hv_clock.version++; | |
4e335d9e PB |
2633 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
2634 | &vcpu->hv_clock, | |
2635 | sizeof(vcpu->hv_clock.version)); | |
0d6dd2ff PB |
2636 | } |
2637 | ||
34c238a1 | 2638 | static int kvm_guest_time_update(struct kvm_vcpu *v) |
18068523 | 2639 | { |
78db6a50 | 2640 | unsigned long flags, tgt_tsc_khz; |
18068523 | 2641 | struct kvm_vcpu_arch *vcpu = &v->arch; |
d828199e | 2642 | struct kvm_arch *ka = &v->kvm->arch; |
f25e656d | 2643 | s64 kernel_ns; |
d828199e | 2644 | u64 tsc_timestamp, host_tsc; |
51d59c6b | 2645 | u8 pvclock_flags; |
d828199e MT |
2646 | bool use_master_clock; |
2647 | ||
2648 | kernel_ns = 0; | |
2649 | host_tsc = 0; | |
18068523 | 2650 | |
d828199e MT |
2651 | /* |
2652 | * If the host uses TSC clock, then passthrough TSC as stable | |
2653 | * to the guest. | |
2654 | */ | |
2655 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
2656 | use_master_clock = ka->use_master_clock; | |
2657 | if (use_master_clock) { | |
2658 | host_tsc = ka->master_cycle_now; | |
2659 | kernel_ns = ka->master_kernel_ns; | |
2660 | } | |
2661 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
c09664bb MT |
2662 | |
2663 | /* Keep irq disabled to prevent changes to the clock */ | |
2664 | local_irq_save(flags); | |
78db6a50 PB |
2665 | tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); |
2666 | if (unlikely(tgt_tsc_khz == 0)) { | |
c09664bb MT |
2667 | local_irq_restore(flags); |
2668 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); | |
2669 | return 1; | |
2670 | } | |
d828199e | 2671 | if (!use_master_clock) { |
4ea1636b | 2672 | host_tsc = rdtsc(); |
8171cd68 | 2673 | kernel_ns = get_kvmclock_base_ns(); |
d828199e MT |
2674 | } |
2675 | ||
4ba76538 | 2676 | tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); |
d828199e | 2677 | |
c285545f ZA |
2678 | /* |
2679 | * We may have to catch up the TSC to match elapsed wall clock | |
2680 | * time for two reasons, even if kvmclock is used. | |
2681 | * 1) CPU could have been running below the maximum TSC rate | |
2682 | * 2) Broken TSC compensation resets the base at each VCPU | |
2683 | * entry to avoid unknown leaps of TSC even when running | |
2684 | * again on the same CPU. This may cause apparent elapsed | |
2685 | * time to disappear, and the guest to stand still or run | |
2686 | * very slowly. | |
2687 | */ | |
2688 | if (vcpu->tsc_catchup) { | |
2689 | u64 tsc = compute_guest_tsc(v, kernel_ns); | |
2690 | if (tsc > tsc_timestamp) { | |
f1e2b260 | 2691 | adjust_tsc_offset_guest(v, tsc - tsc_timestamp); |
c285545f ZA |
2692 | tsc_timestamp = tsc; |
2693 | } | |
50d0a0f9 GH |
2694 | } |
2695 | ||
18068523 GOC |
2696 | local_irq_restore(flags); |
2697 | ||
0d6dd2ff | 2698 | /* With all the info we got, fill in the values */ |
18068523 | 2699 | |
78db6a50 PB |
2700 | if (kvm_has_tsc_control) |
2701 | tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz); | |
2702 | ||
2703 | if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { | |
3ae13faa | 2704 | kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, |
5f4e3f88 ZA |
2705 | &vcpu->hv_clock.tsc_shift, |
2706 | &vcpu->hv_clock.tsc_to_system_mul); | |
78db6a50 | 2707 | vcpu->hw_tsc_khz = tgt_tsc_khz; |
8cfdc000 ZA |
2708 | } |
2709 | ||
1d5f066e | 2710 | vcpu->hv_clock.tsc_timestamp = tsc_timestamp; |
759379dd | 2711 | vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; |
28e4639a | 2712 | vcpu->last_guest_tsc = tsc_timestamp; |
51d59c6b | 2713 | |
d828199e | 2714 | /* If the host uses TSC clocksource, then it is stable */ |
0d6dd2ff | 2715 | pvclock_flags = 0; |
d828199e MT |
2716 | if (use_master_clock) |
2717 | pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; | |
2718 | ||
78c0337a MT |
2719 | vcpu->hv_clock.flags = pvclock_flags; |
2720 | ||
095cf55d PB |
2721 | if (vcpu->pv_time_enabled) |
2722 | kvm_setup_pvclock_page(v); | |
2723 | if (v == kvm_get_vcpu(v->kvm, 0)) | |
2724 | kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); | |
8cfdc000 | 2725 | return 0; |
c8076604 GH |
2726 | } |
2727 | ||
0061d53d MT |
2728 | /* |
2729 | * kvmclock updates which are isolated to a given vcpu, such as | |
2730 | * vcpu->cpu migration, should not allow system_timestamp from | |
2731 | * the rest of the vcpus to remain static. Otherwise ntp frequency | |
2732 | * correction applies to one vcpu's system_timestamp but not | |
2733 | * the others. | |
2734 | * | |
2735 | * So in those cases, request a kvmclock update for all vcpus. | |
7e44e449 AJ |
2736 | * We need to rate-limit these requests though, as they can |
2737 | * considerably slow guests that have a large number of vcpus. | |
2738 | * The time for a remote vcpu to update its kvmclock is bound | |
2739 | * by the delay we use to rate-limit the updates. | |
0061d53d MT |
2740 | */ |
2741 | ||
7e44e449 AJ |
2742 | #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) |
2743 | ||
2744 | static void kvmclock_update_fn(struct work_struct *work) | |
0061d53d MT |
2745 | { |
2746 | int i; | |
7e44e449 AJ |
2747 | struct delayed_work *dwork = to_delayed_work(work); |
2748 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
2749 | kvmclock_update_work); | |
2750 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
0061d53d MT |
2751 | struct kvm_vcpu *vcpu; |
2752 | ||
2753 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
105b21bb | 2754 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0061d53d MT |
2755 | kvm_vcpu_kick(vcpu); |
2756 | } | |
2757 | } | |
2758 | ||
7e44e449 AJ |
2759 | static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) |
2760 | { | |
2761 | struct kvm *kvm = v->kvm; | |
2762 | ||
105b21bb | 2763 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); |
7e44e449 AJ |
2764 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, |
2765 | KVMCLOCK_UPDATE_DELAY); | |
2766 | } | |
2767 | ||
332967a3 AJ |
2768 | #define KVMCLOCK_SYNC_PERIOD (300 * HZ) |
2769 | ||
2770 | static void kvmclock_sync_fn(struct work_struct *work) | |
2771 | { | |
2772 | struct delayed_work *dwork = to_delayed_work(work); | |
2773 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
2774 | kvmclock_sync_work); | |
2775 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
2776 | ||
630994b3 MT |
2777 | if (!kvmclock_periodic_sync) |
2778 | return; | |
2779 | ||
332967a3 AJ |
2780 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); |
2781 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
2782 | KVMCLOCK_SYNC_PERIOD); | |
2783 | } | |
2784 | ||
191c8137 BP |
2785 | /* |
2786 | * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. | |
2787 | */ | |
2788 | static bool can_set_mci_status(struct kvm_vcpu *vcpu) | |
2789 | { | |
2790 | /* McStatusWrEn enabled? */ | |
23493d0a | 2791 | if (guest_cpuid_is_amd_or_hygon(vcpu)) |
191c8137 BP |
2792 | return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); |
2793 | ||
2794 | return false; | |
2795 | } | |
2796 | ||
9ffd986c | 2797 | static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 2798 | { |
890ca9ae HY |
2799 | u64 mcg_cap = vcpu->arch.mcg_cap; |
2800 | unsigned bank_num = mcg_cap & 0xff; | |
9ffd986c WL |
2801 | u32 msr = msr_info->index; |
2802 | u64 data = msr_info->data; | |
890ca9ae | 2803 | |
15c4a640 | 2804 | switch (msr) { |
15c4a640 | 2805 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 2806 | vcpu->arch.mcg_status = data; |
15c4a640 | 2807 | break; |
c7ac679c | 2808 | case MSR_IA32_MCG_CTL: |
44883f01 PB |
2809 | if (!(mcg_cap & MCG_CTL_P) && |
2810 | (data || !msr_info->host_initiated)) | |
890ca9ae HY |
2811 | return 1; |
2812 | if (data != 0 && data != ~(u64)0) | |
44883f01 | 2813 | return 1; |
890ca9ae HY |
2814 | vcpu->arch.mcg_ctl = data; |
2815 | break; | |
2816 | default: | |
2817 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 2818 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
6ec4c5ee MP |
2819 | u32 offset = array_index_nospec( |
2820 | msr - MSR_IA32_MC0_CTL, | |
2821 | MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); | |
2822 | ||
114be429 AP |
2823 | /* only 0 or all 1s can be written to IA32_MCi_CTL |
2824 | * some Linux kernels though clear bit 10 in bank 4 to | |
2825 | * workaround a BIOS/GART TBL issue on AMD K8s, ignore | |
2826 | * this to avoid an uncatched #GP in the guest | |
2827 | */ | |
890ca9ae | 2828 | if ((offset & 0x3) == 0 && |
114be429 | 2829 | data != 0 && (data | (1 << 10)) != ~(u64)0) |
890ca9ae | 2830 | return -1; |
191c8137 BP |
2831 | |
2832 | /* MCi_STATUS */ | |
9ffd986c | 2833 | if (!msr_info->host_initiated && |
191c8137 BP |
2834 | (offset & 0x3) == 1 && data != 0) { |
2835 | if (!can_set_mci_status(vcpu)) | |
2836 | return -1; | |
2837 | } | |
2838 | ||
890ca9ae HY |
2839 | vcpu->arch.mce_banks[offset] = data; |
2840 | break; | |
2841 | } | |
2842 | return 1; | |
2843 | } | |
2844 | return 0; | |
2845 | } | |
2846 | ||
ffde22ac ES |
2847 | static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) |
2848 | { | |
2849 | struct kvm *kvm = vcpu->kvm; | |
2850 | int lm = is_long_mode(vcpu); | |
2851 | u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 | |
2852 | : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; | |
2853 | u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 | |
2854 | : kvm->arch.xen_hvm_config.blob_size_32; | |
2855 | u32 page_num = data & ~PAGE_MASK; | |
2856 | u64 page_addr = data & PAGE_MASK; | |
2857 | u8 *page; | |
ffde22ac | 2858 | |
ffde22ac | 2859 | if (page_num >= blob_size) |
36385ccc ML |
2860 | return 1; |
2861 | ||
ff5c2c03 | 2862 | page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); |
36385ccc ML |
2863 | if (IS_ERR(page)) |
2864 | return PTR_ERR(page); | |
2865 | ||
2866 | if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) { | |
2867 | kfree(page); | |
2868 | return 1; | |
ff5c2c03 | 2869 | } |
36385ccc | 2870 | return 0; |
ffde22ac ES |
2871 | } |
2872 | ||
2635b5c4 VK |
2873 | static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu) |
2874 | { | |
2875 | u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT; | |
2876 | ||
2877 | return (vcpu->arch.apf.msr_en_val & mask) == mask; | |
2878 | } | |
2879 | ||
344d9588 GN |
2880 | static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) |
2881 | { | |
2882 | gpa_t gpa = data & ~0x3f; | |
2883 | ||
2635b5c4 VK |
2884 | /* Bits 4:5 are reserved, Should be zero */ |
2885 | if (data & 0x30) | |
344d9588 GN |
2886 | return 1; |
2887 | ||
66570e96 OU |
2888 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) && |
2889 | (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT)) | |
2890 | return 1; | |
2891 | ||
2892 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) && | |
2893 | (data & KVM_ASYNC_PF_DELIVERY_AS_INT)) | |
2894 | return 1; | |
2895 | ||
9d3c447c | 2896 | if (!lapic_in_kernel(vcpu)) |
d831de17 | 2897 | return data ? 1 : 0; |
9d3c447c | 2898 | |
2635b5c4 | 2899 | vcpu->arch.apf.msr_en_val = data; |
344d9588 | 2900 | |
2635b5c4 | 2901 | if (!kvm_pv_async_pf_enabled(vcpu)) { |
344d9588 GN |
2902 | kvm_clear_async_pf_completion_queue(vcpu); |
2903 | kvm_async_pf_hash_reset(vcpu); | |
2904 | return 0; | |
2905 | } | |
2906 | ||
4e335d9e | 2907 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, |
68fd66f1 | 2908 | sizeof(u64))) |
344d9588 GN |
2909 | return 1; |
2910 | ||
6adba527 | 2911 | vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); |
52a5c155 | 2912 | vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; |
2635b5c4 | 2913 | |
344d9588 | 2914 | kvm_async_pf_wakeup_all(vcpu); |
2635b5c4 VK |
2915 | |
2916 | return 0; | |
2917 | } | |
2918 | ||
2919 | static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data) | |
2920 | { | |
2921 | /* Bits 8-63 are reserved */ | |
2922 | if (data >> 8) | |
2923 | return 1; | |
2924 | ||
2925 | if (!lapic_in_kernel(vcpu)) | |
2926 | return 1; | |
2927 | ||
2928 | vcpu->arch.apf.msr_int_val = data; | |
2929 | ||
2930 | vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK; | |
2931 | ||
344d9588 GN |
2932 | return 0; |
2933 | } | |
2934 | ||
12f9a48f GC |
2935 | static void kvmclock_reset(struct kvm_vcpu *vcpu) |
2936 | { | |
0b79459b | 2937 | vcpu->arch.pv_time_enabled = false; |
49dedf0d | 2938 | vcpu->arch.time = 0; |
12f9a48f GC |
2939 | } |
2940 | ||
7780938c | 2941 | static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu) |
f38a7b75 WL |
2942 | { |
2943 | ++vcpu->stat.tlb_flush; | |
7780938c | 2944 | kvm_x86_ops.tlb_flush_all(vcpu); |
f38a7b75 WL |
2945 | } |
2946 | ||
0baedd79 VK |
2947 | static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu) |
2948 | { | |
2949 | ++vcpu->stat.tlb_flush; | |
2950 | kvm_x86_ops.tlb_flush_guest(vcpu); | |
2951 | } | |
2952 | ||
c9aaa895 GC |
2953 | static void record_steal_time(struct kvm_vcpu *vcpu) |
2954 | { | |
b0431382 BO |
2955 | struct kvm_host_map map; |
2956 | struct kvm_steal_time *st; | |
2957 | ||
c9aaa895 GC |
2958 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) |
2959 | return; | |
2960 | ||
b0431382 BO |
2961 | /* -EAGAIN is returned in atomic context so we can just return. */ |
2962 | if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, | |
2963 | &map, &vcpu->arch.st.cache, false)) | |
c9aaa895 GC |
2964 | return; |
2965 | ||
b0431382 BO |
2966 | st = map.hva + |
2967 | offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); | |
2968 | ||
f38a7b75 WL |
2969 | /* |
2970 | * Doing a TLB flush here, on the guest's behalf, can avoid | |
2971 | * expensive IPIs. | |
2972 | */ | |
66570e96 OU |
2973 | if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) { |
2974 | trace_kvm_pv_tlb_flush(vcpu->vcpu_id, | |
2975 | st->preempted & KVM_VCPU_FLUSH_TLB); | |
2976 | if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB) | |
2977 | kvm_vcpu_flush_tlb_guest(vcpu); | |
2978 | } | |
0b9f6c46 | 2979 | |
a6bd811f | 2980 | vcpu->arch.st.preempted = 0; |
35f3fae1 | 2981 | |
b0431382 BO |
2982 | if (st->version & 1) |
2983 | st->version += 1; /* first time write, random junk */ | |
35f3fae1 | 2984 | |
b0431382 | 2985 | st->version += 1; |
35f3fae1 WL |
2986 | |
2987 | smp_wmb(); | |
2988 | ||
b0431382 | 2989 | st->steal += current->sched_info.run_delay - |
c54cdf14 LC |
2990 | vcpu->arch.st.last_steal; |
2991 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
35f3fae1 | 2992 | |
35f3fae1 WL |
2993 | smp_wmb(); |
2994 | ||
b0431382 | 2995 | st->version += 1; |
c9aaa895 | 2996 | |
b0431382 | 2997 | kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false); |
c9aaa895 GC |
2998 | } |
2999 | ||
8fe8ab46 | 3000 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 3001 | { |
5753785f | 3002 | bool pr = false; |
8fe8ab46 WA |
3003 | u32 msr = msr_info->index; |
3004 | u64 data = msr_info->data; | |
5753785f | 3005 | |
15c4a640 | 3006 | switch (msr) { |
2e32b719 | 3007 | case MSR_AMD64_NB_CFG: |
2e32b719 BP |
3008 | case MSR_IA32_UCODE_WRITE: |
3009 | case MSR_VM_HSAVE_PA: | |
3010 | case MSR_AMD64_PATCH_LOADER: | |
3011 | case MSR_AMD64_BU_CFG2: | |
405a353a | 3012 | case MSR_AMD64_DC_CFG: |
0e1b869f | 3013 | case MSR_F15H_EX_CFG: |
2e32b719 BP |
3014 | break; |
3015 | ||
518e7b94 WL |
3016 | case MSR_IA32_UCODE_REV: |
3017 | if (msr_info->host_initiated) | |
3018 | vcpu->arch.microcode_version = data; | |
3019 | break; | |
0cf9135b SC |
3020 | case MSR_IA32_ARCH_CAPABILITIES: |
3021 | if (!msr_info->host_initiated) | |
3022 | return 1; | |
3023 | vcpu->arch.arch_capabilities = data; | |
3024 | break; | |
d574c539 VK |
3025 | case MSR_IA32_PERF_CAPABILITIES: { |
3026 | struct kvm_msr_entry msr_ent = {.index = msr, .data = 0}; | |
3027 | ||
3028 | if (!msr_info->host_initiated) | |
3029 | return 1; | |
3030 | if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM) && kvm_get_msr_feature(&msr_ent)) | |
3031 | return 1; | |
3032 | if (data & ~msr_ent.data) | |
3033 | return 1; | |
3034 | ||
3035 | vcpu->arch.perf_capabilities = data; | |
3036 | ||
3037 | return 0; | |
3038 | } | |
15c4a640 | 3039 | case MSR_EFER: |
11988499 | 3040 | return set_efer(vcpu, msr_info); |
8f1589d9 AP |
3041 | case MSR_K7_HWCR: |
3042 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
82494028 | 3043 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ |
a223c313 | 3044 | data &= ~(u64)0x8; /* ignore TLB cache disable */ |
191c8137 BP |
3045 | |
3046 | /* Handle McStatusWrEn */ | |
3047 | if (data == BIT_ULL(18)) { | |
3048 | vcpu->arch.msr_hwcr = data; | |
3049 | } else if (data != 0) { | |
a737f256 CD |
3050 | vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", |
3051 | data); | |
8f1589d9 AP |
3052 | return 1; |
3053 | } | |
15c4a640 | 3054 | break; |
f7c6d140 AP |
3055 | case MSR_FAM10H_MMIO_CONF_BASE: |
3056 | if (data != 0) { | |
a737f256 CD |
3057 | vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " |
3058 | "0x%llx\n", data); | |
f7c6d140 AP |
3059 | return 1; |
3060 | } | |
15c4a640 | 3061 | break; |
b5e2fec0 AG |
3062 | case MSR_IA32_DEBUGCTLMSR: |
3063 | if (!data) { | |
3064 | /* We support the non-activated case already */ | |
3065 | break; | |
3066 | } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { | |
3067 | /* Values other than LBR and BTF are vendor-specific, | |
3068 | thus reserved and should throw a #GP */ | |
3069 | return 1; | |
2cdef91c PG |
3070 | } else if (report_ignored_msrs) |
3071 | vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", | |
3072 | __func__, data); | |
b5e2fec0 | 3073 | break; |
9ba075a6 | 3074 | case 0x200 ... 0x2ff: |
ff53604b | 3075 | return kvm_mtrr_set_msr(vcpu, msr, data); |
15c4a640 | 3076 | case MSR_IA32_APICBASE: |
58cb628d | 3077 | return kvm_set_apic_base(vcpu, msr_info); |
bf10bd0b | 3078 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: |
0105d1a5 | 3079 | return kvm_x2apic_msr_write(vcpu, msr, data); |
a3e06bbe LJ |
3080 | case MSR_IA32_TSCDEADLINE: |
3081 | kvm_set_lapic_tscdeadline_msr(vcpu, data); | |
3082 | break; | |
ba904635 | 3083 | case MSR_IA32_TSC_ADJUST: |
d6321d49 | 3084 | if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { |
ba904635 | 3085 | if (!msr_info->host_initiated) { |
d913b904 | 3086 | s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; |
d7add054 | 3087 | adjust_tsc_offset_guest(vcpu, adj); |
ba904635 WA |
3088 | } |
3089 | vcpu->arch.ia32_tsc_adjust_msr = data; | |
3090 | } | |
3091 | break; | |
15c4a640 | 3092 | case MSR_IA32_MISC_ENABLE: |
511a8556 WL |
3093 | if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && |
3094 | ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { | |
3095 | if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) | |
3096 | return 1; | |
3097 | vcpu->arch.ia32_misc_enable_msr = data; | |
aedbaf4f | 3098 | kvm_update_cpuid_runtime(vcpu); |
511a8556 WL |
3099 | } else { |
3100 | vcpu->arch.ia32_misc_enable_msr = data; | |
3101 | } | |
15c4a640 | 3102 | break; |
64d60670 PB |
3103 | case MSR_IA32_SMBASE: |
3104 | if (!msr_info->host_initiated) | |
3105 | return 1; | |
3106 | vcpu->arch.smbase = data; | |
3107 | break; | |
73f624f4 PB |
3108 | case MSR_IA32_POWER_CTL: |
3109 | vcpu->arch.msr_ia32_power_ctl = data; | |
3110 | break; | |
dd259935 | 3111 | case MSR_IA32_TSC: |
0c899c25 PB |
3112 | if (msr_info->host_initiated) { |
3113 | kvm_synchronize_tsc(vcpu, data); | |
3114 | } else { | |
3115 | u64 adj = kvm_compute_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset; | |
3116 | adjust_tsc_offset_guest(vcpu, adj); | |
3117 | vcpu->arch.ia32_tsc_adjust_msr += adj; | |
3118 | } | |
dd259935 | 3119 | break; |
864e2ab2 AL |
3120 | case MSR_IA32_XSS: |
3121 | if (!msr_info->host_initiated && | |
3122 | !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) | |
3123 | return 1; | |
3124 | /* | |
a1bead2a SC |
3125 | * KVM supports exposing PT to the guest, but does not support |
3126 | * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than | |
3127 | * XSAVES/XRSTORS to save/restore PT MSRs. | |
864e2ab2 | 3128 | */ |
408e9a31 | 3129 | if (data & ~supported_xss) |
864e2ab2 AL |
3130 | return 1; |
3131 | vcpu->arch.ia32_xss = data; | |
3132 | break; | |
52797bf9 LA |
3133 | case MSR_SMI_COUNT: |
3134 | if (!msr_info->host_initiated) | |
3135 | return 1; | |
3136 | vcpu->arch.smi_count = data; | |
3137 | break; | |
11c6bffa | 3138 | case MSR_KVM_WALL_CLOCK_NEW: |
66570e96 OU |
3139 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3140 | return 1; | |
3141 | ||
3142 | kvm_write_wall_clock(vcpu->kvm, data); | |
3143 | break; | |
18068523 | 3144 | case MSR_KVM_WALL_CLOCK: |
66570e96 OU |
3145 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3146 | return 1; | |
3147 | ||
18068523 GOC |
3148 | kvm_write_wall_clock(vcpu->kvm, data); |
3149 | break; | |
11c6bffa | 3150 | case MSR_KVM_SYSTEM_TIME_NEW: |
66570e96 OU |
3151 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3152 | return 1; | |
3153 | ||
5b9bb0eb OU |
3154 | kvm_write_system_time(vcpu, data, false, msr_info->host_initiated); |
3155 | break; | |
3156 | case MSR_KVM_SYSTEM_TIME: | |
66570e96 OU |
3157 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3158 | return 1; | |
3159 | ||
3160 | kvm_write_system_time(vcpu, data, true, msr_info->host_initiated); | |
18068523 | 3161 | break; |
344d9588 | 3162 | case MSR_KVM_ASYNC_PF_EN: |
66570e96 OU |
3163 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3164 | return 1; | |
3165 | ||
344d9588 GN |
3166 | if (kvm_pv_enable_async_pf(vcpu, data)) |
3167 | return 1; | |
3168 | break; | |
2635b5c4 | 3169 | case MSR_KVM_ASYNC_PF_INT: |
66570e96 OU |
3170 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
3171 | return 1; | |
3172 | ||
2635b5c4 VK |
3173 | if (kvm_pv_enable_async_pf_int(vcpu, data)) |
3174 | return 1; | |
3175 | break; | |
557a961a | 3176 | case MSR_KVM_ASYNC_PF_ACK: |
66570e96 OU |
3177 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3178 | return 1; | |
557a961a VK |
3179 | if (data & 0x1) { |
3180 | vcpu->arch.apf.pageready_pending = false; | |
3181 | kvm_check_async_pf_completion(vcpu); | |
3182 | } | |
3183 | break; | |
c9aaa895 | 3184 | case MSR_KVM_STEAL_TIME: |
66570e96 OU |
3185 | if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) |
3186 | return 1; | |
c9aaa895 GC |
3187 | |
3188 | if (unlikely(!sched_info_on())) | |
3189 | return 1; | |
3190 | ||
3191 | if (data & KVM_STEAL_RESERVED_MASK) | |
3192 | return 1; | |
3193 | ||
c9aaa895 GC |
3194 | vcpu->arch.st.msr_val = data; |
3195 | ||
3196 | if (!(data & KVM_MSR_ENABLED)) | |
3197 | break; | |
3198 | ||
c9aaa895 GC |
3199 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
3200 | ||
3201 | break; | |
ae7a2a3f | 3202 | case MSR_KVM_PV_EOI_EN: |
66570e96 OU |
3203 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) |
3204 | return 1; | |
3205 | ||
72bbf935 | 3206 | if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8))) |
ae7a2a3f MT |
3207 | return 1; |
3208 | break; | |
c9aaa895 | 3209 | |
2d5ba19b | 3210 | case MSR_KVM_POLL_CONTROL: |
66570e96 OU |
3211 | if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) |
3212 | return 1; | |
3213 | ||
2d5ba19b MT |
3214 | /* only enable bit supported */ |
3215 | if (data & (-1ULL << 1)) | |
3216 | return 1; | |
3217 | ||
3218 | vcpu->arch.msr_kvm_poll_control = data; | |
3219 | break; | |
3220 | ||
890ca9ae HY |
3221 | case MSR_IA32_MCG_CTL: |
3222 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 3223 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
9ffd986c | 3224 | return set_msr_mce(vcpu, msr_info); |
71db6023 | 3225 | |
6912ac32 WH |
3226 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: |
3227 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
df561f66 GS |
3228 | pr = true; |
3229 | fallthrough; | |
6912ac32 WH |
3230 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: |
3231 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 3232 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 3233 | return kvm_pmu_set_msr(vcpu, msr_info); |
5753785f GN |
3234 | |
3235 | if (pr || data != 0) | |
a737f256 CD |
3236 | vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " |
3237 | "0x%x data 0x%llx\n", msr, data); | |
5753785f | 3238 | break; |
84e0cefa JS |
3239 | case MSR_K7_CLK_CTL: |
3240 | /* | |
3241 | * Ignore all writes to this no longer documented MSR. | |
3242 | * Writes are only relevant for old K7 processors, | |
3243 | * all pre-dating SVM, but a recommended workaround from | |
4a969980 | 3244 | * AMD for these chips. It is possible to specify the |
84e0cefa JS |
3245 | * affected processor models on the command line, hence |
3246 | * the need to ignore the workaround. | |
3247 | */ | |
3248 | break; | |
55cd8e5a | 3249 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
f97f5a56 JD |
3250 | case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: |
3251 | case HV_X64_MSR_SYNDBG_OPTIONS: | |
e7d9513b AS |
3252 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
3253 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 3254 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
3255 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
3256 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
3257 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
e7d9513b AS |
3258 | return kvm_hv_set_msr_common(vcpu, msr, data, |
3259 | msr_info->host_initiated); | |
91c9c3ed | 3260 | case MSR_IA32_BBL_CR_CTL3: |
3261 | /* Drop writes to this legacy MSR -- see rdmsr | |
3262 | * counterpart for further detail. | |
3263 | */ | |
fab0aa3b EM |
3264 | if (report_ignored_msrs) |
3265 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", | |
3266 | msr, data); | |
91c9c3ed | 3267 | break; |
2b036c6b | 3268 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 3269 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
3270 | return 1; |
3271 | vcpu->arch.osvw.length = data; | |
3272 | break; | |
3273 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 3274 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
3275 | return 1; |
3276 | vcpu->arch.osvw.status = data; | |
3277 | break; | |
db2336a8 KH |
3278 | case MSR_PLATFORM_INFO: |
3279 | if (!msr_info->host_initiated || | |
db2336a8 KH |
3280 | (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && |
3281 | cpuid_fault_enabled(vcpu))) | |
3282 | return 1; | |
3283 | vcpu->arch.msr_platform_info = data; | |
3284 | break; | |
3285 | case MSR_MISC_FEATURES_ENABLES: | |
3286 | if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || | |
3287 | (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && | |
3288 | !supports_cpuid_fault(vcpu))) | |
3289 | return 1; | |
3290 | vcpu->arch.msr_misc_features_enables = data; | |
3291 | break; | |
15c4a640 | 3292 | default: |
ffde22ac ES |
3293 | if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) |
3294 | return xen_hvm_config(vcpu, data); | |
c6702c9d | 3295 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 3296 | return kvm_pmu_set_msr(vcpu, msr_info); |
6abe9c13 | 3297 | return KVM_MSR_RET_INVALID; |
15c4a640 CO |
3298 | } |
3299 | return 0; | |
3300 | } | |
3301 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
3302 | ||
44883f01 | 3303 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) |
15c4a640 CO |
3304 | { |
3305 | u64 data; | |
890ca9ae HY |
3306 | u64 mcg_cap = vcpu->arch.mcg_cap; |
3307 | unsigned bank_num = mcg_cap & 0xff; | |
15c4a640 CO |
3308 | |
3309 | switch (msr) { | |
15c4a640 CO |
3310 | case MSR_IA32_P5_MC_ADDR: |
3311 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
3312 | data = 0; |
3313 | break; | |
15c4a640 | 3314 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
3315 | data = vcpu->arch.mcg_cap; |
3316 | break; | |
c7ac679c | 3317 | case MSR_IA32_MCG_CTL: |
44883f01 | 3318 | if (!(mcg_cap & MCG_CTL_P) && !host) |
890ca9ae HY |
3319 | return 1; |
3320 | data = vcpu->arch.mcg_ctl; | |
3321 | break; | |
3322 | case MSR_IA32_MCG_STATUS: | |
3323 | data = vcpu->arch.mcg_status; | |
3324 | break; | |
3325 | default: | |
3326 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 3327 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
6ec4c5ee MP |
3328 | u32 offset = array_index_nospec( |
3329 | msr - MSR_IA32_MC0_CTL, | |
3330 | MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); | |
3331 | ||
890ca9ae HY |
3332 | data = vcpu->arch.mce_banks[offset]; |
3333 | break; | |
3334 | } | |
3335 | return 1; | |
3336 | } | |
3337 | *pdata = data; | |
3338 | return 0; | |
3339 | } | |
3340 | ||
609e36d3 | 3341 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
890ca9ae | 3342 | { |
609e36d3 | 3343 | switch (msr_info->index) { |
890ca9ae | 3344 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 3345 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
3346 | case MSR_IA32_DEBUGCTLMSR: |
3347 | case MSR_IA32_LASTBRANCHFROMIP: | |
3348 | case MSR_IA32_LASTBRANCHTOIP: | |
3349 | case MSR_IA32_LASTINTFROMIP: | |
3350 | case MSR_IA32_LASTINTTOIP: | |
60af2ecd | 3351 | case MSR_K8_SYSCFG: |
3afb1121 PB |
3352 | case MSR_K8_TSEG_ADDR: |
3353 | case MSR_K8_TSEG_MASK: | |
61a6bd67 | 3354 | case MSR_VM_HSAVE_PA: |
1fdbd48c | 3355 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 3356 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 3357 | case MSR_FAM10H_MMIO_CONF_BASE: |
2e32b719 | 3358 | case MSR_AMD64_BU_CFG2: |
0c2df2a1 | 3359 | case MSR_IA32_PERF_CTL: |
405a353a | 3360 | case MSR_AMD64_DC_CFG: |
0e1b869f | 3361 | case MSR_F15H_EX_CFG: |
2ca1a06a VS |
3362 | /* |
3363 | * Intel Sandy Bridge CPUs must support the RAPL (running average power | |
3364 | * limit) MSRs. Just return 0, as we do not want to expose the host | |
3365 | * data here. Do not conditionalize this on CPUID, as KVM does not do | |
3366 | * so for existing CPU-specific MSRs. | |
3367 | */ | |
3368 | case MSR_RAPL_POWER_UNIT: | |
3369 | case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */ | |
3370 | case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */ | |
3371 | case MSR_PKG_ENERGY_STATUS: /* Total package */ | |
3372 | case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */ | |
609e36d3 | 3373 | msr_info->data = 0; |
15c4a640 | 3374 | break; |
c51eb52b | 3375 | case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: |
6912ac32 WH |
3376 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: |
3377 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: | |
3378 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
3379 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 3380 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
cbd71758 | 3381 | return kvm_pmu_get_msr(vcpu, msr_info); |
609e36d3 | 3382 | msr_info->data = 0; |
5753785f | 3383 | break; |
742bc670 | 3384 | case MSR_IA32_UCODE_REV: |
518e7b94 | 3385 | msr_info->data = vcpu->arch.microcode_version; |
742bc670 | 3386 | break; |
0cf9135b SC |
3387 | case MSR_IA32_ARCH_CAPABILITIES: |
3388 | if (!msr_info->host_initiated && | |
3389 | !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) | |
3390 | return 1; | |
3391 | msr_info->data = vcpu->arch.arch_capabilities; | |
3392 | break; | |
d574c539 VK |
3393 | case MSR_IA32_PERF_CAPABILITIES: |
3394 | if (!msr_info->host_initiated && | |
3395 | !guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) | |
3396 | return 1; | |
3397 | msr_info->data = vcpu->arch.perf_capabilities; | |
3398 | break; | |
73f624f4 PB |
3399 | case MSR_IA32_POWER_CTL: |
3400 | msr_info->data = vcpu->arch.msr_ia32_power_ctl; | |
3401 | break; | |
cc5b54dd ML |
3402 | case MSR_IA32_TSC: { |
3403 | /* | |
3404 | * Intel SDM states that MSR_IA32_TSC read adds the TSC offset | |
3405 | * even when not intercepted. AMD manual doesn't explicitly | |
3406 | * state this but appears to behave the same. | |
3407 | * | |
ee6fa053 | 3408 | * On userspace reads and writes, however, we unconditionally |
c0623f5e | 3409 | * return L1's TSC value to ensure backwards-compatible |
ee6fa053 | 3410 | * behavior for migration. |
cc5b54dd ML |
3411 | */ |
3412 | u64 tsc_offset = msr_info->host_initiated ? vcpu->arch.l1_tsc_offset : | |
3413 | vcpu->arch.tsc_offset; | |
3414 | ||
3415 | msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + tsc_offset; | |
dd259935 | 3416 | break; |
cc5b54dd | 3417 | } |
9ba075a6 | 3418 | case MSR_MTRRcap: |
9ba075a6 | 3419 | case 0x200 ... 0x2ff: |
ff53604b | 3420 | return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); |
15c4a640 | 3421 | case 0xcd: /* fsb frequency */ |
609e36d3 | 3422 | msr_info->data = 3; |
15c4a640 | 3423 | break; |
7b914098 JS |
3424 | /* |
3425 | * MSR_EBC_FREQUENCY_ID | |
3426 | * Conservative value valid for even the basic CPU models. | |
3427 | * Models 0,1: 000 in bits 23:21 indicating a bus speed of | |
3428 | * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, | |
3429 | * and 266MHz for model 3, or 4. Set Core Clock | |
3430 | * Frequency to System Bus Frequency Ratio to 1 (bits | |
3431 | * 31:24) even though these are only valid for CPU | |
3432 | * models > 2, however guests may end up dividing or | |
3433 | * multiplying by zero otherwise. | |
3434 | */ | |
3435 | case MSR_EBC_FREQUENCY_ID: | |
609e36d3 | 3436 | msr_info->data = 1 << 24; |
7b914098 | 3437 | break; |
15c4a640 | 3438 | case MSR_IA32_APICBASE: |
609e36d3 | 3439 | msr_info->data = kvm_get_apic_base(vcpu); |
15c4a640 | 3440 | break; |
bf10bd0b | 3441 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: |
609e36d3 | 3442 | return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); |
a3e06bbe | 3443 | case MSR_IA32_TSCDEADLINE: |
609e36d3 | 3444 | msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); |
a3e06bbe | 3445 | break; |
ba904635 | 3446 | case MSR_IA32_TSC_ADJUST: |
609e36d3 | 3447 | msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; |
ba904635 | 3448 | break; |
15c4a640 | 3449 | case MSR_IA32_MISC_ENABLE: |
609e36d3 | 3450 | msr_info->data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 3451 | break; |
64d60670 PB |
3452 | case MSR_IA32_SMBASE: |
3453 | if (!msr_info->host_initiated) | |
3454 | return 1; | |
3455 | msr_info->data = vcpu->arch.smbase; | |
15c4a640 | 3456 | break; |
52797bf9 LA |
3457 | case MSR_SMI_COUNT: |
3458 | msr_info->data = vcpu->arch.smi_count; | |
3459 | break; | |
847f0ad8 AG |
3460 | case MSR_IA32_PERF_STATUS: |
3461 | /* TSC increment by tick */ | |
609e36d3 | 3462 | msr_info->data = 1000ULL; |
847f0ad8 | 3463 | /* CPU multiplier */ |
b0996ae4 | 3464 | msr_info->data |= (((uint64_t)4ULL) << 40); |
847f0ad8 | 3465 | break; |
15c4a640 | 3466 | case MSR_EFER: |
609e36d3 | 3467 | msr_info->data = vcpu->arch.efer; |
15c4a640 | 3468 | break; |
18068523 | 3469 | case MSR_KVM_WALL_CLOCK: |
1930e5dd OU |
3470 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3471 | return 1; | |
3472 | ||
3473 | msr_info->data = vcpu->kvm->arch.wall_clock; | |
3474 | break; | |
11c6bffa | 3475 | case MSR_KVM_WALL_CLOCK_NEW: |
1930e5dd OU |
3476 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3477 | return 1; | |
3478 | ||
609e36d3 | 3479 | msr_info->data = vcpu->kvm->arch.wall_clock; |
18068523 GOC |
3480 | break; |
3481 | case MSR_KVM_SYSTEM_TIME: | |
1930e5dd OU |
3482 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3483 | return 1; | |
3484 | ||
3485 | msr_info->data = vcpu->arch.time; | |
3486 | break; | |
11c6bffa | 3487 | case MSR_KVM_SYSTEM_TIME_NEW: |
1930e5dd OU |
3488 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3489 | return 1; | |
3490 | ||
609e36d3 | 3491 | msr_info->data = vcpu->arch.time; |
18068523 | 3492 | break; |
344d9588 | 3493 | case MSR_KVM_ASYNC_PF_EN: |
1930e5dd OU |
3494 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3495 | return 1; | |
3496 | ||
2635b5c4 VK |
3497 | msr_info->data = vcpu->arch.apf.msr_en_val; |
3498 | break; | |
3499 | case MSR_KVM_ASYNC_PF_INT: | |
1930e5dd OU |
3500 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
3501 | return 1; | |
3502 | ||
2635b5c4 | 3503 | msr_info->data = vcpu->arch.apf.msr_int_val; |
344d9588 | 3504 | break; |
557a961a | 3505 | case MSR_KVM_ASYNC_PF_ACK: |
1930e5dd OU |
3506 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3507 | return 1; | |
3508 | ||
557a961a VK |
3509 | msr_info->data = 0; |
3510 | break; | |
c9aaa895 | 3511 | case MSR_KVM_STEAL_TIME: |
1930e5dd OU |
3512 | if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) |
3513 | return 1; | |
3514 | ||
609e36d3 | 3515 | msr_info->data = vcpu->arch.st.msr_val; |
c9aaa895 | 3516 | break; |
1d92128f | 3517 | case MSR_KVM_PV_EOI_EN: |
1930e5dd OU |
3518 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) |
3519 | return 1; | |
3520 | ||
609e36d3 | 3521 | msr_info->data = vcpu->arch.pv_eoi.msr_val; |
1d92128f | 3522 | break; |
2d5ba19b | 3523 | case MSR_KVM_POLL_CONTROL: |
1930e5dd OU |
3524 | if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) |
3525 | return 1; | |
3526 | ||
2d5ba19b MT |
3527 | msr_info->data = vcpu->arch.msr_kvm_poll_control; |
3528 | break; | |
890ca9ae HY |
3529 | case MSR_IA32_P5_MC_ADDR: |
3530 | case MSR_IA32_P5_MC_TYPE: | |
3531 | case MSR_IA32_MCG_CAP: | |
3532 | case MSR_IA32_MCG_CTL: | |
3533 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 3534 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
44883f01 PB |
3535 | return get_msr_mce(vcpu, msr_info->index, &msr_info->data, |
3536 | msr_info->host_initiated); | |
864e2ab2 AL |
3537 | case MSR_IA32_XSS: |
3538 | if (!msr_info->host_initiated && | |
3539 | !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) | |
3540 | return 1; | |
3541 | msr_info->data = vcpu->arch.ia32_xss; | |
3542 | break; | |
84e0cefa JS |
3543 | case MSR_K7_CLK_CTL: |
3544 | /* | |
3545 | * Provide expected ramp-up count for K7. All other | |
3546 | * are set to zero, indicating minimum divisors for | |
3547 | * every field. | |
3548 | * | |
3549 | * This prevents guest kernels on AMD host with CPU | |
3550 | * type 6, model 8 and higher from exploding due to | |
3551 | * the rdmsr failing. | |
3552 | */ | |
609e36d3 | 3553 | msr_info->data = 0x20000000; |
84e0cefa | 3554 | break; |
55cd8e5a | 3555 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
f97f5a56 JD |
3556 | case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: |
3557 | case HV_X64_MSR_SYNDBG_OPTIONS: | |
e7d9513b AS |
3558 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
3559 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 3560 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
3561 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
3562 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
3563 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
e83d5887 | 3564 | return kvm_hv_get_msr_common(vcpu, |
44883f01 PB |
3565 | msr_info->index, &msr_info->data, |
3566 | msr_info->host_initiated); | |
91c9c3ed | 3567 | case MSR_IA32_BBL_CR_CTL3: |
3568 | /* This legacy MSR exists but isn't fully documented in current | |
3569 | * silicon. It is however accessed by winxp in very narrow | |
3570 | * scenarios where it sets bit #19, itself documented as | |
3571 | * a "reserved" bit. Best effort attempt to source coherent | |
3572 | * read data here should the balance of the register be | |
3573 | * interpreted by the guest: | |
3574 | * | |
3575 | * L2 cache control register 3: 64GB range, 256KB size, | |
3576 | * enabled, latency 0x1, configured | |
3577 | */ | |
609e36d3 | 3578 | msr_info->data = 0xbe702111; |
91c9c3ed | 3579 | break; |
2b036c6b | 3580 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 3581 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 3582 | return 1; |
609e36d3 | 3583 | msr_info->data = vcpu->arch.osvw.length; |
2b036c6b BO |
3584 | break; |
3585 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 3586 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 3587 | return 1; |
609e36d3 | 3588 | msr_info->data = vcpu->arch.osvw.status; |
2b036c6b | 3589 | break; |
db2336a8 | 3590 | case MSR_PLATFORM_INFO: |
6fbbde9a DS |
3591 | if (!msr_info->host_initiated && |
3592 | !vcpu->kvm->arch.guest_can_read_msr_platform_info) | |
3593 | return 1; | |
db2336a8 KH |
3594 | msr_info->data = vcpu->arch.msr_platform_info; |
3595 | break; | |
3596 | case MSR_MISC_FEATURES_ENABLES: | |
3597 | msr_info->data = vcpu->arch.msr_misc_features_enables; | |
3598 | break; | |
191c8137 BP |
3599 | case MSR_K7_HWCR: |
3600 | msr_info->data = vcpu->arch.msr_hwcr; | |
3601 | break; | |
15c4a640 | 3602 | default: |
c6702c9d | 3603 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
cbd71758 | 3604 | return kvm_pmu_get_msr(vcpu, msr_info); |
6abe9c13 | 3605 | return KVM_MSR_RET_INVALID; |
15c4a640 | 3606 | } |
15c4a640 CO |
3607 | return 0; |
3608 | } | |
3609 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
3610 | ||
313a3dc7 CO |
3611 | /* |
3612 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
3613 | * | |
3614 | * @return number of msrs set successfully. | |
3615 | */ | |
3616 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
3617 | struct kvm_msr_entry *entries, | |
3618 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
3619 | unsigned index, u64 *data)) | |
3620 | { | |
801e459a | 3621 | int i; |
313a3dc7 | 3622 | |
313a3dc7 CO |
3623 | for (i = 0; i < msrs->nmsrs; ++i) |
3624 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
3625 | break; | |
3626 | ||
313a3dc7 CO |
3627 | return i; |
3628 | } | |
3629 | ||
3630 | /* | |
3631 | * Read or write a bunch of msrs. Parameters are user addresses. | |
3632 | * | |
3633 | * @return number of msrs set successfully. | |
3634 | */ | |
3635 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
3636 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
3637 | unsigned index, u64 *data), | |
3638 | int writeback) | |
3639 | { | |
3640 | struct kvm_msrs msrs; | |
3641 | struct kvm_msr_entry *entries; | |
3642 | int r, n; | |
3643 | unsigned size; | |
3644 | ||
3645 | r = -EFAULT; | |
0e96f31e | 3646 | if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) |
313a3dc7 CO |
3647 | goto out; |
3648 | ||
3649 | r = -E2BIG; | |
3650 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
3651 | goto out; | |
3652 | ||
313a3dc7 | 3653 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; |
ff5c2c03 SL |
3654 | entries = memdup_user(user_msrs->entries, size); |
3655 | if (IS_ERR(entries)) { | |
3656 | r = PTR_ERR(entries); | |
313a3dc7 | 3657 | goto out; |
ff5c2c03 | 3658 | } |
313a3dc7 CO |
3659 | |
3660 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
3661 | if (r < 0) | |
3662 | goto out_free; | |
3663 | ||
3664 | r = -EFAULT; | |
3665 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
3666 | goto out_free; | |
3667 | ||
3668 | r = n; | |
3669 | ||
3670 | out_free: | |
7a73c028 | 3671 | kfree(entries); |
313a3dc7 CO |
3672 | out: |
3673 | return r; | |
3674 | } | |
3675 | ||
4d5422ce WL |
3676 | static inline bool kvm_can_mwait_in_guest(void) |
3677 | { | |
3678 | return boot_cpu_has(X86_FEATURE_MWAIT) && | |
8e9b29b6 KA |
3679 | !boot_cpu_has_bug(X86_BUG_MONITOR) && |
3680 | boot_cpu_has(X86_FEATURE_ARAT); | |
4d5422ce WL |
3681 | } |
3682 | ||
784aa3d7 | 3683 | int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) |
018d00d2 | 3684 | { |
4d5422ce | 3685 | int r = 0; |
018d00d2 ZX |
3686 | |
3687 | switch (ext) { | |
3688 | case KVM_CAP_IRQCHIP: | |
3689 | case KVM_CAP_HLT: | |
3690 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 3691 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 3692 | case KVM_CAP_EXT_CPUID: |
9c15bb1d | 3693 | case KVM_CAP_EXT_EMUL_CPUID: |
c8076604 | 3694 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 3695 | case KVM_CAP_PIT: |
a28e4f5a | 3696 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 3697 | case KVM_CAP_MP_STATE: |
ed848624 | 3698 | case KVM_CAP_SYNC_MMU: |
a355c85c | 3699 | case KVM_CAP_USER_NMI: |
52d939a0 | 3700 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 3701 | case KVM_CAP_IRQ_INJECT_STATUS: |
d34e6b17 | 3702 | case KVM_CAP_IOEVENTFD: |
f848a5a8 | 3703 | case KVM_CAP_IOEVENTFD_NO_LENGTH: |
c5ff41ce | 3704 | case KVM_CAP_PIT2: |
e9f42757 | 3705 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 3706 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
ffde22ac | 3707 | case KVM_CAP_XEN_HVM: |
3cfc3092 | 3708 | case KVM_CAP_VCPU_EVENTS: |
55cd8e5a | 3709 | case KVM_CAP_HYPERV: |
10388a07 | 3710 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 3711 | case KVM_CAP_HYPERV_SPIN: |
5c919412 | 3712 | case KVM_CAP_HYPERV_SYNIC: |
efc479e6 | 3713 | case KVM_CAP_HYPERV_SYNIC2: |
d3457c87 | 3714 | case KVM_CAP_HYPERV_VP_INDEX: |
faeb7833 | 3715 | case KVM_CAP_HYPERV_EVENTFD: |
c1aea919 | 3716 | case KVM_CAP_HYPERV_TLBFLUSH: |
214ff83d | 3717 | case KVM_CAP_HYPERV_SEND_IPI: |
2bc39970 | 3718 | case KVM_CAP_HYPERV_CPUID: |
ab9f4ecb | 3719 | case KVM_CAP_PCI_SEGMENT: |
a1efbe77 | 3720 | case KVM_CAP_DEBUGREGS: |
d2be1651 | 3721 | case KVM_CAP_X86_ROBUST_SINGLESTEP: |
2d5b5a66 | 3722 | case KVM_CAP_XSAVE: |
344d9588 | 3723 | case KVM_CAP_ASYNC_PF: |
72de5fa4 | 3724 | case KVM_CAP_ASYNC_PF_INT: |
92a1f12d | 3725 | case KVM_CAP_GET_TSC_KHZ: |
1c0b28c2 | 3726 | case KVM_CAP_KVMCLOCK_CTRL: |
4d8b81ab | 3727 | case KVM_CAP_READONLY_MEM: |
5f66b620 | 3728 | case KVM_CAP_HYPERV_TIME: |
100943c5 | 3729 | case KVM_CAP_IOAPIC_POLARITY_IGNORED: |
defcf51f | 3730 | case KVM_CAP_TSC_DEADLINE_TIMER: |
90de4a18 | 3731 | case KVM_CAP_DISABLE_QUIRKS: |
d71ba788 | 3732 | case KVM_CAP_SET_BOOT_CPU_ID: |
49df6397 | 3733 | case KVM_CAP_SPLIT_IRQCHIP: |
460df4c1 | 3734 | case KVM_CAP_IMMEDIATE_EXIT: |
66bb8a06 | 3735 | case KVM_CAP_PMU_EVENT_FILTER: |
801e459a | 3736 | case KVM_CAP_GET_MSR_FEATURES: |
6fbbde9a | 3737 | case KVM_CAP_MSR_PLATFORM_INFO: |
c4f55198 | 3738 | case KVM_CAP_EXCEPTION_PAYLOAD: |
b9b2782c | 3739 | case KVM_CAP_SET_GUEST_DEBUG: |
1aa561b1 | 3740 | case KVM_CAP_LAST_CPU: |
1ae09954 | 3741 | case KVM_CAP_X86_USER_SPACE_MSR: |
1a155254 | 3742 | case KVM_CAP_X86_MSR_FILTER: |
66570e96 | 3743 | case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: |
018d00d2 ZX |
3744 | r = 1; |
3745 | break; | |
01643c51 KH |
3746 | case KVM_CAP_SYNC_REGS: |
3747 | r = KVM_SYNC_X86_VALID_FIELDS; | |
3748 | break; | |
e3fd9a93 PB |
3749 | case KVM_CAP_ADJUST_CLOCK: |
3750 | r = KVM_CLOCK_TSC_STABLE; | |
3751 | break; | |
4d5422ce | 3752 | case KVM_CAP_X86_DISABLE_EXITS: |
b5170063 WL |
3753 | r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE | |
3754 | KVM_X86_DISABLE_EXITS_CSTATE; | |
4d5422ce WL |
3755 | if(kvm_can_mwait_in_guest()) |
3756 | r |= KVM_X86_DISABLE_EXITS_MWAIT; | |
668fffa3 | 3757 | break; |
6d396b55 PB |
3758 | case KVM_CAP_X86_SMM: |
3759 | /* SMBASE is usually relocated above 1M on modern chipsets, | |
3760 | * and SMM handlers might indeed rely on 4G segment limits, | |
3761 | * so do not report SMM to be available if real mode is | |
3762 | * emulated via vm86 mode. Still, do not go to great lengths | |
3763 | * to avoid userspace's usage of the feature, because it is a | |
3764 | * fringe case that is not enabled except via specific settings | |
3765 | * of the module parameters. | |
3766 | */ | |
afaf0b2f | 3767 | r = kvm_x86_ops.has_emulated_msr(MSR_IA32_SMBASE); |
6d396b55 | 3768 | break; |
774ead3a | 3769 | case KVM_CAP_VAPIC: |
afaf0b2f | 3770 | r = !kvm_x86_ops.cpu_has_accelerated_tpr(); |
774ead3a | 3771 | break; |
f725230a | 3772 | case KVM_CAP_NR_VCPUS: |
8c3ba334 SL |
3773 | r = KVM_SOFT_MAX_VCPUS; |
3774 | break; | |
3775 | case KVM_CAP_MAX_VCPUS: | |
f725230a AK |
3776 | r = KVM_MAX_VCPUS; |
3777 | break; | |
a86cb413 TH |
3778 | case KVM_CAP_MAX_VCPU_ID: |
3779 | r = KVM_MAX_VCPU_ID; | |
3780 | break; | |
a68a6a72 MT |
3781 | case KVM_CAP_PV_MMU: /* obsolete */ |
3782 | r = 0; | |
2f333bcb | 3783 | break; |
890ca9ae HY |
3784 | case KVM_CAP_MCE: |
3785 | r = KVM_MAX_MCE_BANKS; | |
3786 | break; | |
2d5b5a66 | 3787 | case KVM_CAP_XCRS: |
d366bf7e | 3788 | r = boot_cpu_has(X86_FEATURE_XSAVE); |
2d5b5a66 | 3789 | break; |
92a1f12d JR |
3790 | case KVM_CAP_TSC_CONTROL: |
3791 | r = kvm_has_tsc_control; | |
3792 | break; | |
37131313 RK |
3793 | case KVM_CAP_X2APIC_API: |
3794 | r = KVM_X2APIC_API_VALID_FLAGS; | |
3795 | break; | |
8fcc4b59 | 3796 | case KVM_CAP_NESTED_STATE: |
33b22172 PB |
3797 | r = kvm_x86_ops.nested_ops->get_state ? |
3798 | kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0; | |
8fcc4b59 | 3799 | break; |
344c6c80 | 3800 | case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: |
afaf0b2f | 3801 | r = kvm_x86_ops.enable_direct_tlbflush != NULL; |
5a0165f6 VK |
3802 | break; |
3803 | case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: | |
33b22172 | 3804 | r = kvm_x86_ops.nested_ops->enable_evmcs != NULL; |
344c6c80 | 3805 | break; |
3edd6839 MG |
3806 | case KVM_CAP_SMALLER_MAXPHYADDR: |
3807 | r = (int) allow_smaller_maxphyaddr; | |
3808 | break; | |
004a0124 AJ |
3809 | case KVM_CAP_STEAL_TIME: |
3810 | r = sched_info_on(); | |
3811 | break; | |
018d00d2 | 3812 | default: |
018d00d2 ZX |
3813 | break; |
3814 | } | |
3815 | return r; | |
3816 | ||
3817 | } | |
3818 | ||
043405e1 CO |
3819 | long kvm_arch_dev_ioctl(struct file *filp, |
3820 | unsigned int ioctl, unsigned long arg) | |
3821 | { | |
3822 | void __user *argp = (void __user *)arg; | |
3823 | long r; | |
3824 | ||
3825 | switch (ioctl) { | |
3826 | case KVM_GET_MSR_INDEX_LIST: { | |
3827 | struct kvm_msr_list __user *user_msr_list = argp; | |
3828 | struct kvm_msr_list msr_list; | |
3829 | unsigned n; | |
3830 | ||
3831 | r = -EFAULT; | |
0e96f31e | 3832 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) |
043405e1 CO |
3833 | goto out; |
3834 | n = msr_list.nmsrs; | |
62ef68bb | 3835 | msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; |
0e96f31e | 3836 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) |
043405e1 CO |
3837 | goto out; |
3838 | r = -E2BIG; | |
e125e7b6 | 3839 | if (n < msr_list.nmsrs) |
043405e1 CO |
3840 | goto out; |
3841 | r = -EFAULT; | |
3842 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
3843 | num_msrs_to_save * sizeof(u32))) | |
3844 | goto out; | |
e125e7b6 | 3845 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 | 3846 | &emulated_msrs, |
62ef68bb | 3847 | num_emulated_msrs * sizeof(u32))) |
043405e1 CO |
3848 | goto out; |
3849 | r = 0; | |
3850 | break; | |
3851 | } | |
9c15bb1d BP |
3852 | case KVM_GET_SUPPORTED_CPUID: |
3853 | case KVM_GET_EMULATED_CPUID: { | |
674eea0f AK |
3854 | struct kvm_cpuid2 __user *cpuid_arg = argp; |
3855 | struct kvm_cpuid2 cpuid; | |
3856 | ||
3857 | r = -EFAULT; | |
0e96f31e | 3858 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
674eea0f | 3859 | goto out; |
9c15bb1d BP |
3860 | |
3861 | r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, | |
3862 | ioctl); | |
674eea0f AK |
3863 | if (r) |
3864 | goto out; | |
3865 | ||
3866 | r = -EFAULT; | |
0e96f31e | 3867 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) |
674eea0f AK |
3868 | goto out; |
3869 | r = 0; | |
3870 | break; | |
3871 | } | |
cf6c26ec | 3872 | case KVM_X86_GET_MCE_CAP_SUPPORTED: |
890ca9ae | 3873 | r = -EFAULT; |
c45dcc71 AR |
3874 | if (copy_to_user(argp, &kvm_mce_cap_supported, |
3875 | sizeof(kvm_mce_cap_supported))) | |
890ca9ae HY |
3876 | goto out; |
3877 | r = 0; | |
3878 | break; | |
801e459a TL |
3879 | case KVM_GET_MSR_FEATURE_INDEX_LIST: { |
3880 | struct kvm_msr_list __user *user_msr_list = argp; | |
3881 | struct kvm_msr_list msr_list; | |
3882 | unsigned int n; | |
3883 | ||
3884 | r = -EFAULT; | |
3885 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) | |
3886 | goto out; | |
3887 | n = msr_list.nmsrs; | |
3888 | msr_list.nmsrs = num_msr_based_features; | |
3889 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) | |
3890 | goto out; | |
3891 | r = -E2BIG; | |
3892 | if (n < msr_list.nmsrs) | |
3893 | goto out; | |
3894 | r = -EFAULT; | |
3895 | if (copy_to_user(user_msr_list->indices, &msr_based_features, | |
3896 | num_msr_based_features * sizeof(u32))) | |
3897 | goto out; | |
3898 | r = 0; | |
3899 | break; | |
3900 | } | |
3901 | case KVM_GET_MSRS: | |
3902 | r = msr_io(NULL, argp, do_get_msr_feature, 1); | |
3903 | break; | |
043405e1 CO |
3904 | default: |
3905 | r = -EINVAL; | |
cf6c26ec | 3906 | break; |
043405e1 CO |
3907 | } |
3908 | out: | |
3909 | return r; | |
3910 | } | |
3911 | ||
f5f48ee1 SY |
3912 | static void wbinvd_ipi(void *garbage) |
3913 | { | |
3914 | wbinvd(); | |
3915 | } | |
3916 | ||
3917 | static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
3918 | { | |
e0f0bbc5 | 3919 | return kvm_arch_has_noncoherent_dma(vcpu->kvm); |
f5f48ee1 SY |
3920 | } |
3921 | ||
313a3dc7 CO |
3922 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
3923 | { | |
f5f48ee1 SY |
3924 | /* Address WBINVD may be executed by guest */ |
3925 | if (need_emulate_wbinvd(vcpu)) { | |
afaf0b2f | 3926 | if (kvm_x86_ops.has_wbinvd_exit()) |
f5f48ee1 SY |
3927 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); |
3928 | else if (vcpu->cpu != -1 && vcpu->cpu != cpu) | |
3929 | smp_call_function_single(vcpu->cpu, | |
3930 | wbinvd_ipi, NULL, 1); | |
3931 | } | |
3932 | ||
afaf0b2f | 3933 | kvm_x86_ops.vcpu_load(vcpu, cpu); |
8f6055cb | 3934 | |
37486135 BM |
3935 | /* Save host pkru register if supported */ |
3936 | vcpu->arch.host_pkru = read_pkru(); | |
3937 | ||
0dd6a6ed ZA |
3938 | /* Apply any externally detected TSC adjustments (due to suspend) */ |
3939 | if (unlikely(vcpu->arch.tsc_offset_adjustment)) { | |
3940 | adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); | |
3941 | vcpu->arch.tsc_offset_adjustment = 0; | |
105b21bb | 3942 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed | 3943 | } |
8f6055cb | 3944 | |
b0c39dc6 | 3945 | if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { |
6f526ec5 | 3946 | s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : |
4ea1636b | 3947 | rdtsc() - vcpu->arch.last_host_tsc; |
e48672fa ZA |
3948 | if (tsc_delta < 0) |
3949 | mark_tsc_unstable("KVM discovered backwards TSC"); | |
ce7a058a | 3950 | |
b0c39dc6 | 3951 | if (kvm_check_tsc_unstable()) { |
07c1419a | 3952 | u64 offset = kvm_compute_tsc_offset(vcpu, |
b183aa58 | 3953 | vcpu->arch.last_guest_tsc); |
a545ab6a | 3954 | kvm_vcpu_write_tsc_offset(vcpu, offset); |
c285545f | 3955 | vcpu->arch.tsc_catchup = 1; |
c285545f | 3956 | } |
a749e247 PB |
3957 | |
3958 | if (kvm_lapic_hv_timer_in_use(vcpu)) | |
3959 | kvm_lapic_restart_hv_timer(vcpu); | |
3960 | ||
d98d07ca MT |
3961 | /* |
3962 | * On a host with synchronized TSC, there is no need to update | |
3963 | * kvmclock on vcpu->cpu migration | |
3964 | */ | |
3965 | if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) | |
0061d53d | 3966 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
c285545f | 3967 | if (vcpu->cpu != cpu) |
1bd2009e | 3968 | kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); |
e48672fa | 3969 | vcpu->cpu = cpu; |
6b7d7e76 | 3970 | } |
c9aaa895 | 3971 | |
c9aaa895 | 3972 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
313a3dc7 CO |
3973 | } |
3974 | ||
0b9f6c46 PX |
3975 | static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) |
3976 | { | |
b0431382 BO |
3977 | struct kvm_host_map map; |
3978 | struct kvm_steal_time *st; | |
3979 | ||
0b9f6c46 PX |
3980 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) |
3981 | return; | |
3982 | ||
a6bd811f | 3983 | if (vcpu->arch.st.preempted) |
8c6de56a BO |
3984 | return; |
3985 | ||
b0431382 BO |
3986 | if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map, |
3987 | &vcpu->arch.st.cache, true)) | |
3988 | return; | |
3989 | ||
3990 | st = map.hva + | |
3991 | offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); | |
0b9f6c46 | 3992 | |
a6bd811f | 3993 | st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; |
0b9f6c46 | 3994 | |
b0431382 | 3995 | kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true); |
0b9f6c46 PX |
3996 | } |
3997 | ||
313a3dc7 CO |
3998 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) |
3999 | { | |
cc0d907c | 4000 | int idx; |
de63ad4c LM |
4001 | |
4002 | if (vcpu->preempted) | |
afaf0b2f | 4003 | vcpu->arch.preempted_in_kernel = !kvm_x86_ops.get_cpl(vcpu); |
de63ad4c | 4004 | |
931f261b AA |
4005 | /* |
4006 | * Disable page faults because we're in atomic context here. | |
4007 | * kvm_write_guest_offset_cached() would call might_fault() | |
4008 | * that relies on pagefault_disable() to tell if there's a | |
4009 | * bug. NOTE: the write to guest memory may not go through if | |
4010 | * during postcopy live migration or if there's heavy guest | |
4011 | * paging. | |
4012 | */ | |
4013 | pagefault_disable(); | |
cc0d907c AA |
4014 | /* |
4015 | * kvm_memslots() will be called by | |
4016 | * kvm_write_guest_offset_cached() so take the srcu lock. | |
4017 | */ | |
4018 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
0b9f6c46 | 4019 | kvm_steal_time_set_preempted(vcpu); |
cc0d907c | 4020 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
931f261b | 4021 | pagefault_enable(); |
afaf0b2f | 4022 | kvm_x86_ops.vcpu_put(vcpu); |
4ea1636b | 4023 | vcpu->arch.last_host_tsc = rdtsc(); |
efdab992 | 4024 | /* |
f9dcf08e RK |
4025 | * If userspace has set any breakpoints or watchpoints, dr6 is restored |
4026 | * on every vmexit, but if not, we might have a stale dr6 from the | |
4027 | * guest. do_debug expects dr6 to be cleared after it runs, do the same. | |
efdab992 | 4028 | */ |
f9dcf08e | 4029 | set_debugreg(0, 6); |
313a3dc7 CO |
4030 | } |
4031 | ||
313a3dc7 CO |
4032 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
4033 | struct kvm_lapic_state *s) | |
4034 | { | |
fa59cc00 | 4035 | if (vcpu->arch.apicv_active) |
afaf0b2f | 4036 | kvm_x86_ops.sync_pir_to_irr(vcpu); |
d62caabb | 4037 | |
a92e2543 | 4038 | return kvm_apic_get_state(vcpu, s); |
313a3dc7 CO |
4039 | } |
4040 | ||
4041 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
4042 | struct kvm_lapic_state *s) | |
4043 | { | |
a92e2543 RK |
4044 | int r; |
4045 | ||
4046 | r = kvm_apic_set_state(vcpu, s); | |
4047 | if (r) | |
4048 | return r; | |
cb142eb7 | 4049 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
4050 | |
4051 | return 0; | |
4052 | } | |
4053 | ||
127a457a MG |
4054 | static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) |
4055 | { | |
4056 | return (!lapic_in_kernel(vcpu) || | |
4057 | kvm_apic_accept_pic_intr(vcpu)); | |
4058 | } | |
4059 | ||
782d422b MG |
4060 | /* |
4061 | * if userspace requested an interrupt window, check that the | |
4062 | * interrupt window is open. | |
4063 | * | |
4064 | * No need to exit to userspace if we already have an interrupt queued. | |
4065 | */ | |
4066 | static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) | |
4067 | { | |
4068 | return kvm_arch_interrupt_allowed(vcpu) && | |
4069 | !kvm_cpu_has_interrupt(vcpu) && | |
4070 | !kvm_event_needs_reinjection(vcpu) && | |
4071 | kvm_cpu_accept_dm_intr(vcpu); | |
4072 | } | |
4073 | ||
f77bc6a4 ZX |
4074 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
4075 | struct kvm_interrupt *irq) | |
4076 | { | |
02cdb50f | 4077 | if (irq->irq >= KVM_NR_INTERRUPTS) |
f77bc6a4 | 4078 | return -EINVAL; |
1c1a9ce9 SR |
4079 | |
4080 | if (!irqchip_in_kernel(vcpu->kvm)) { | |
4081 | kvm_queue_interrupt(vcpu, irq->irq, false); | |
4082 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
4083 | return 0; | |
4084 | } | |
4085 | ||
4086 | /* | |
4087 | * With in-kernel LAPIC, we only use this to inject EXTINT, so | |
4088 | * fail for in-kernel 8259. | |
4089 | */ | |
4090 | if (pic_in_kernel(vcpu->kvm)) | |
f77bc6a4 | 4091 | return -ENXIO; |
f77bc6a4 | 4092 | |
1c1a9ce9 SR |
4093 | if (vcpu->arch.pending_external_vector != -1) |
4094 | return -EEXIST; | |
f77bc6a4 | 4095 | |
1c1a9ce9 | 4096 | vcpu->arch.pending_external_vector = irq->irq; |
934bf653 | 4097 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f77bc6a4 ZX |
4098 | return 0; |
4099 | } | |
4100 | ||
c4abb7c9 JK |
4101 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
4102 | { | |
c4abb7c9 | 4103 | kvm_inject_nmi(vcpu); |
c4abb7c9 JK |
4104 | |
4105 | return 0; | |
4106 | } | |
4107 | ||
f077825a PB |
4108 | static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) |
4109 | { | |
64d60670 PB |
4110 | kvm_make_request(KVM_REQ_SMI, vcpu); |
4111 | ||
f077825a PB |
4112 | return 0; |
4113 | } | |
4114 | ||
b209749f AK |
4115 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
4116 | struct kvm_tpr_access_ctl *tac) | |
4117 | { | |
4118 | if (tac->flags) | |
4119 | return -EINVAL; | |
4120 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
4121 | return 0; | |
4122 | } | |
4123 | ||
890ca9ae HY |
4124 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
4125 | u64 mcg_cap) | |
4126 | { | |
4127 | int r; | |
4128 | unsigned bank_num = mcg_cap & 0xff, bank; | |
4129 | ||
4130 | r = -EINVAL; | |
c4e0e4ab | 4131 | if (!bank_num || bank_num > KVM_MAX_MCE_BANKS) |
890ca9ae | 4132 | goto out; |
c45dcc71 | 4133 | if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) |
890ca9ae HY |
4134 | goto out; |
4135 | r = 0; | |
4136 | vcpu->arch.mcg_cap = mcg_cap; | |
4137 | /* Init IA32_MCG_CTL to all 1s */ | |
4138 | if (mcg_cap & MCG_CTL_P) | |
4139 | vcpu->arch.mcg_ctl = ~(u64)0; | |
4140 | /* Init IA32_MCi_CTL to all 1s */ | |
4141 | for (bank = 0; bank < bank_num; bank++) | |
4142 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
c45dcc71 | 4143 | |
afaf0b2f | 4144 | kvm_x86_ops.setup_mce(vcpu); |
890ca9ae HY |
4145 | out: |
4146 | return r; | |
4147 | } | |
4148 | ||
4149 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
4150 | struct kvm_x86_mce *mce) | |
4151 | { | |
4152 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
4153 | unsigned bank_num = mcg_cap & 0xff; | |
4154 | u64 *banks = vcpu->arch.mce_banks; | |
4155 | ||
4156 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
4157 | return -EINVAL; | |
4158 | /* | |
4159 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
4160 | * reporting is disabled | |
4161 | */ | |
4162 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
4163 | vcpu->arch.mcg_ctl != ~(u64)0) | |
4164 | return 0; | |
4165 | banks += 4 * mce->bank; | |
4166 | /* | |
4167 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
4168 | * reporting is disabled for the bank | |
4169 | */ | |
4170 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
4171 | return 0; | |
4172 | if (mce->status & MCI_STATUS_UC) { | |
4173 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
fc78f519 | 4174 | !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { |
a8eeb04a | 4175 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
890ca9ae HY |
4176 | return 0; |
4177 | } | |
4178 | if (banks[1] & MCI_STATUS_VAL) | |
4179 | mce->status |= MCI_STATUS_OVER; | |
4180 | banks[2] = mce->addr; | |
4181 | banks[3] = mce->misc; | |
4182 | vcpu->arch.mcg_status = mce->mcg_status; | |
4183 | banks[1] = mce->status; | |
4184 | kvm_queue_exception(vcpu, MC_VECTOR); | |
4185 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
4186 | || !(banks[1] & MCI_STATUS_UC)) { | |
4187 | if (banks[1] & MCI_STATUS_VAL) | |
4188 | mce->status |= MCI_STATUS_OVER; | |
4189 | banks[2] = mce->addr; | |
4190 | banks[3] = mce->misc; | |
4191 | banks[1] = mce->status; | |
4192 | } else | |
4193 | banks[1] |= MCI_STATUS_OVER; | |
4194 | return 0; | |
4195 | } | |
4196 | ||
3cfc3092 JK |
4197 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
4198 | struct kvm_vcpu_events *events) | |
4199 | { | |
7460fb4a | 4200 | process_nmi(vcpu); |
59073aaf | 4201 | |
a06230b6 OU |
4202 | /* |
4203 | * In guest mode, payload delivery should be deferred, | |
4204 | * so that the L1 hypervisor can intercept #PF before | |
4205 | * CR2 is modified (or intercept #DB before DR6 is | |
4206 | * modified under nVMX). Unless the per-VM capability, | |
4207 | * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of | |
4208 | * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we | |
4209 | * opportunistically defer the exception payload, deliver it if the | |
4210 | * capability hasn't been requested before processing a | |
4211 | * KVM_GET_VCPU_EVENTS. | |
4212 | */ | |
4213 | if (!vcpu->kvm->arch.exception_payload_enabled && | |
4214 | vcpu->arch.exception.pending && vcpu->arch.exception.has_payload) | |
4215 | kvm_deliver_exception_payload(vcpu); | |
4216 | ||
664f8e26 | 4217 | /* |
59073aaf JM |
4218 | * The API doesn't provide the instruction length for software |
4219 | * exceptions, so don't report them. As long as the guest RIP | |
4220 | * isn't advanced, we should expect to encounter the exception | |
4221 | * again. | |
664f8e26 | 4222 | */ |
59073aaf JM |
4223 | if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { |
4224 | events->exception.injected = 0; | |
4225 | events->exception.pending = 0; | |
4226 | } else { | |
4227 | events->exception.injected = vcpu->arch.exception.injected; | |
4228 | events->exception.pending = vcpu->arch.exception.pending; | |
4229 | /* | |
4230 | * For ABI compatibility, deliberately conflate | |
4231 | * pending and injected exceptions when | |
4232 | * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. | |
4233 | */ | |
4234 | if (!vcpu->kvm->arch.exception_payload_enabled) | |
4235 | events->exception.injected |= | |
4236 | vcpu->arch.exception.pending; | |
4237 | } | |
3cfc3092 JK |
4238 | events->exception.nr = vcpu->arch.exception.nr; |
4239 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
4240 | events->exception.error_code = vcpu->arch.exception.error_code; | |
59073aaf JM |
4241 | events->exception_has_payload = vcpu->arch.exception.has_payload; |
4242 | events->exception_payload = vcpu->arch.exception.payload; | |
3cfc3092 | 4243 | |
03b82a30 | 4244 | events->interrupt.injected = |
04140b41 | 4245 | vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; |
3cfc3092 | 4246 | events->interrupt.nr = vcpu->arch.interrupt.nr; |
03b82a30 | 4247 | events->interrupt.soft = 0; |
afaf0b2f | 4248 | events->interrupt.shadow = kvm_x86_ops.get_interrupt_shadow(vcpu); |
3cfc3092 JK |
4249 | |
4250 | events->nmi.injected = vcpu->arch.nmi_injected; | |
7460fb4a | 4251 | events->nmi.pending = vcpu->arch.nmi_pending != 0; |
afaf0b2f | 4252 | events->nmi.masked = kvm_x86_ops.get_nmi_mask(vcpu); |
97e69aa6 | 4253 | events->nmi.pad = 0; |
3cfc3092 | 4254 | |
66450a21 | 4255 | events->sipi_vector = 0; /* never valid when reporting to user space */ |
3cfc3092 | 4256 | |
f077825a PB |
4257 | events->smi.smm = is_smm(vcpu); |
4258 | events->smi.pending = vcpu->arch.smi_pending; | |
4259 | events->smi.smm_inside_nmi = | |
4260 | !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); | |
4261 | events->smi.latched_init = kvm_lapic_latched_init(vcpu); | |
4262 | ||
dab4b911 | 4263 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
f077825a PB |
4264 | | KVM_VCPUEVENT_VALID_SHADOW |
4265 | | KVM_VCPUEVENT_VALID_SMM); | |
59073aaf JM |
4266 | if (vcpu->kvm->arch.exception_payload_enabled) |
4267 | events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; | |
4268 | ||
97e69aa6 | 4269 | memset(&events->reserved, 0, sizeof(events->reserved)); |
3cfc3092 JK |
4270 | } |
4271 | ||
c5833c7a | 4272 | static void kvm_smm_changed(struct kvm_vcpu *vcpu); |
6ef4e07e | 4273 | |
3cfc3092 JK |
4274 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, |
4275 | struct kvm_vcpu_events *events) | |
4276 | { | |
dab4b911 | 4277 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 | 4278 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
f077825a | 4279 | | KVM_VCPUEVENT_VALID_SHADOW |
59073aaf JM |
4280 | | KVM_VCPUEVENT_VALID_SMM |
4281 | | KVM_VCPUEVENT_VALID_PAYLOAD)) | |
3cfc3092 JK |
4282 | return -EINVAL; |
4283 | ||
59073aaf JM |
4284 | if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { |
4285 | if (!vcpu->kvm->arch.exception_payload_enabled) | |
4286 | return -EINVAL; | |
4287 | if (events->exception.pending) | |
4288 | events->exception.injected = 0; | |
4289 | else | |
4290 | events->exception_has_payload = 0; | |
4291 | } else { | |
4292 | events->exception.pending = 0; | |
4293 | events->exception_has_payload = 0; | |
4294 | } | |
4295 | ||
4296 | if ((events->exception.injected || events->exception.pending) && | |
4297 | (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) | |
78e546c8 PB |
4298 | return -EINVAL; |
4299 | ||
28bf2888 DH |
4300 | /* INITs are latched while in SMM */ |
4301 | if (events->flags & KVM_VCPUEVENT_VALID_SMM && | |
4302 | (events->smi.smm || events->smi.pending) && | |
4303 | vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) | |
4304 | return -EINVAL; | |
4305 | ||
7460fb4a | 4306 | process_nmi(vcpu); |
59073aaf JM |
4307 | vcpu->arch.exception.injected = events->exception.injected; |
4308 | vcpu->arch.exception.pending = events->exception.pending; | |
3cfc3092 JK |
4309 | vcpu->arch.exception.nr = events->exception.nr; |
4310 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
4311 | vcpu->arch.exception.error_code = events->exception.error_code; | |
59073aaf JM |
4312 | vcpu->arch.exception.has_payload = events->exception_has_payload; |
4313 | vcpu->arch.exception.payload = events->exception_payload; | |
3cfc3092 | 4314 | |
04140b41 | 4315 | vcpu->arch.interrupt.injected = events->interrupt.injected; |
3cfc3092 JK |
4316 | vcpu->arch.interrupt.nr = events->interrupt.nr; |
4317 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
48005f64 | 4318 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) |
afaf0b2f | 4319 | kvm_x86_ops.set_interrupt_shadow(vcpu, |
48005f64 | 4320 | events->interrupt.shadow); |
3cfc3092 JK |
4321 | |
4322 | vcpu->arch.nmi_injected = events->nmi.injected; | |
dab4b911 JK |
4323 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) |
4324 | vcpu->arch.nmi_pending = events->nmi.pending; | |
afaf0b2f | 4325 | kvm_x86_ops.set_nmi_mask(vcpu, events->nmi.masked); |
3cfc3092 | 4326 | |
66450a21 | 4327 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && |
bce87cce | 4328 | lapic_in_kernel(vcpu)) |
66450a21 | 4329 | vcpu->arch.apic->sipi_vector = events->sipi_vector; |
3cfc3092 | 4330 | |
f077825a | 4331 | if (events->flags & KVM_VCPUEVENT_VALID_SMM) { |
c5833c7a SC |
4332 | if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) { |
4333 | if (events->smi.smm) | |
4334 | vcpu->arch.hflags |= HF_SMM_MASK; | |
4335 | else | |
4336 | vcpu->arch.hflags &= ~HF_SMM_MASK; | |
4337 | kvm_smm_changed(vcpu); | |
4338 | } | |
6ef4e07e | 4339 | |
f077825a | 4340 | vcpu->arch.smi_pending = events->smi.pending; |
f4ef1910 WL |
4341 | |
4342 | if (events->smi.smm) { | |
4343 | if (events->smi.smm_inside_nmi) | |
4344 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; | |
f077825a | 4345 | else |
f4ef1910 | 4346 | vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; |
ff90afa7 LA |
4347 | } |
4348 | ||
4349 | if (lapic_in_kernel(vcpu)) { | |
4350 | if (events->smi.latched_init) | |
4351 | set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
4352 | else | |
4353 | clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
f077825a PB |
4354 | } |
4355 | } | |
4356 | ||
3842d135 AK |
4357 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
4358 | ||
3cfc3092 JK |
4359 | return 0; |
4360 | } | |
4361 | ||
a1efbe77 JK |
4362 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, |
4363 | struct kvm_debugregs *dbgregs) | |
4364 | { | |
73aaf249 JK |
4365 | unsigned long val; |
4366 | ||
a1efbe77 | 4367 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); |
16f8a6f9 | 4368 | kvm_get_dr(vcpu, 6, &val); |
73aaf249 | 4369 | dbgregs->dr6 = val; |
a1efbe77 JK |
4370 | dbgregs->dr7 = vcpu->arch.dr7; |
4371 | dbgregs->flags = 0; | |
97e69aa6 | 4372 | memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); |
a1efbe77 JK |
4373 | } |
4374 | ||
4375 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
4376 | struct kvm_debugregs *dbgregs) | |
4377 | { | |
4378 | if (dbgregs->flags) | |
4379 | return -EINVAL; | |
4380 | ||
d14bdb55 PB |
4381 | if (dbgregs->dr6 & ~0xffffffffull) |
4382 | return -EINVAL; | |
4383 | if (dbgregs->dr7 & ~0xffffffffull) | |
4384 | return -EINVAL; | |
4385 | ||
a1efbe77 | 4386 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); |
ae561ede | 4387 | kvm_update_dr0123(vcpu); |
a1efbe77 JK |
4388 | vcpu->arch.dr6 = dbgregs->dr6; |
4389 | vcpu->arch.dr7 = dbgregs->dr7; | |
9926c9fd | 4390 | kvm_update_dr7(vcpu); |
a1efbe77 | 4391 | |
a1efbe77 JK |
4392 | return 0; |
4393 | } | |
4394 | ||
df1daba7 PB |
4395 | #define XSTATE_COMPACTION_ENABLED (1ULL << 63) |
4396 | ||
4397 | static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) | |
4398 | { | |
b666a4b6 | 4399 | struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; |
400e4b20 | 4400 | u64 xstate_bv = xsave->header.xfeatures; |
df1daba7 PB |
4401 | u64 valid; |
4402 | ||
4403 | /* | |
4404 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
4405 | * leaves 0 and 1 in the loop below. | |
4406 | */ | |
4407 | memcpy(dest, xsave, XSAVE_HDR_OFFSET); | |
4408 | ||
4409 | /* Set XSTATE_BV */ | |
00c87e9a | 4410 | xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE; |
df1daba7 PB |
4411 | *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; |
4412 | ||
4413 | /* | |
4414 | * Copy each region from the possibly compacted offset to the | |
4415 | * non-compacted offset. | |
4416 | */ | |
d91cab78 | 4417 | valid = xstate_bv & ~XFEATURE_MASK_FPSSE; |
df1daba7 | 4418 | while (valid) { |
abd16d68 SAS |
4419 | u64 xfeature_mask = valid & -valid; |
4420 | int xfeature_nr = fls64(xfeature_mask) - 1; | |
4421 | void *src = get_xsave_addr(xsave, xfeature_nr); | |
df1daba7 PB |
4422 | |
4423 | if (src) { | |
4424 | u32 size, offset, ecx, edx; | |
abd16d68 | 4425 | cpuid_count(XSTATE_CPUID, xfeature_nr, |
df1daba7 | 4426 | &size, &offset, &ecx, &edx); |
abd16d68 | 4427 | if (xfeature_nr == XFEATURE_PKRU) |
38cfd5e3 PB |
4428 | memcpy(dest + offset, &vcpu->arch.pkru, |
4429 | sizeof(vcpu->arch.pkru)); | |
4430 | else | |
4431 | memcpy(dest + offset, src, size); | |
4432 | ||
df1daba7 PB |
4433 | } |
4434 | ||
abd16d68 | 4435 | valid -= xfeature_mask; |
df1daba7 PB |
4436 | } |
4437 | } | |
4438 | ||
4439 | static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) | |
4440 | { | |
b666a4b6 | 4441 | struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; |
df1daba7 PB |
4442 | u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); |
4443 | u64 valid; | |
4444 | ||
4445 | /* | |
4446 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
4447 | * leaves 0 and 1 in the loop below. | |
4448 | */ | |
4449 | memcpy(xsave, src, XSAVE_HDR_OFFSET); | |
4450 | ||
4451 | /* Set XSTATE_BV and possibly XCOMP_BV. */ | |
400e4b20 | 4452 | xsave->header.xfeatures = xstate_bv; |
782511b0 | 4453 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
3a54450b | 4454 | xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; |
df1daba7 PB |
4455 | |
4456 | /* | |
4457 | * Copy each region from the non-compacted offset to the | |
4458 | * possibly compacted offset. | |
4459 | */ | |
d91cab78 | 4460 | valid = xstate_bv & ~XFEATURE_MASK_FPSSE; |
df1daba7 | 4461 | while (valid) { |
abd16d68 SAS |
4462 | u64 xfeature_mask = valid & -valid; |
4463 | int xfeature_nr = fls64(xfeature_mask) - 1; | |
4464 | void *dest = get_xsave_addr(xsave, xfeature_nr); | |
df1daba7 PB |
4465 | |
4466 | if (dest) { | |
4467 | u32 size, offset, ecx, edx; | |
abd16d68 | 4468 | cpuid_count(XSTATE_CPUID, xfeature_nr, |
df1daba7 | 4469 | &size, &offset, &ecx, &edx); |
abd16d68 | 4470 | if (xfeature_nr == XFEATURE_PKRU) |
38cfd5e3 PB |
4471 | memcpy(&vcpu->arch.pkru, src + offset, |
4472 | sizeof(vcpu->arch.pkru)); | |
4473 | else | |
4474 | memcpy(dest, src + offset, size); | |
ee4100da | 4475 | } |
df1daba7 | 4476 | |
abd16d68 | 4477 | valid -= xfeature_mask; |
df1daba7 PB |
4478 | } |
4479 | } | |
4480 | ||
2d5b5a66 SY |
4481 | static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, |
4482 | struct kvm_xsave *guest_xsave) | |
4483 | { | |
d366bf7e | 4484 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
df1daba7 PB |
4485 | memset(guest_xsave, 0, sizeof(struct kvm_xsave)); |
4486 | fill_xsave((u8 *) guest_xsave->region, vcpu); | |
4344ee98 | 4487 | } else { |
2d5b5a66 | 4488 | memcpy(guest_xsave->region, |
b666a4b6 | 4489 | &vcpu->arch.guest_fpu->state.fxsave, |
c47ada30 | 4490 | sizeof(struct fxregs_state)); |
2d5b5a66 | 4491 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = |
d91cab78 | 4492 | XFEATURE_MASK_FPSSE; |
2d5b5a66 SY |
4493 | } |
4494 | } | |
4495 | ||
a575813b WL |
4496 | #define XSAVE_MXCSR_OFFSET 24 |
4497 | ||
2d5b5a66 SY |
4498 | static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, |
4499 | struct kvm_xsave *guest_xsave) | |
4500 | { | |
4501 | u64 xstate_bv = | |
4502 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; | |
a575813b | 4503 | u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)]; |
2d5b5a66 | 4504 | |
d366bf7e | 4505 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
d7876f1b PB |
4506 | /* |
4507 | * Here we allow setting states that are not present in | |
4508 | * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility | |
4509 | * with old userspace. | |
4510 | */ | |
cfc48181 | 4511 | if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask) |
d7876f1b | 4512 | return -EINVAL; |
df1daba7 | 4513 | load_xsave(vcpu, (u8 *)guest_xsave->region); |
d7876f1b | 4514 | } else { |
a575813b WL |
4515 | if (xstate_bv & ~XFEATURE_MASK_FPSSE || |
4516 | mxcsr & ~mxcsr_feature_mask) | |
2d5b5a66 | 4517 | return -EINVAL; |
b666a4b6 | 4518 | memcpy(&vcpu->arch.guest_fpu->state.fxsave, |
c47ada30 | 4519 | guest_xsave->region, sizeof(struct fxregs_state)); |
2d5b5a66 SY |
4520 | } |
4521 | return 0; | |
4522 | } | |
4523 | ||
4524 | static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, | |
4525 | struct kvm_xcrs *guest_xcrs) | |
4526 | { | |
d366bf7e | 4527 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) { |
2d5b5a66 SY |
4528 | guest_xcrs->nr_xcrs = 0; |
4529 | return; | |
4530 | } | |
4531 | ||
4532 | guest_xcrs->nr_xcrs = 1; | |
4533 | guest_xcrs->flags = 0; | |
4534 | guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; | |
4535 | guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; | |
4536 | } | |
4537 | ||
4538 | static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, | |
4539 | struct kvm_xcrs *guest_xcrs) | |
4540 | { | |
4541 | int i, r = 0; | |
4542 | ||
d366bf7e | 4543 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) |
2d5b5a66 SY |
4544 | return -EINVAL; |
4545 | ||
4546 | if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) | |
4547 | return -EINVAL; | |
4548 | ||
4549 | for (i = 0; i < guest_xcrs->nr_xcrs; i++) | |
4550 | /* Only support XCR0 currently */ | |
c67a04cb | 4551 | if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { |
2d5b5a66 | 4552 | r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, |
c67a04cb | 4553 | guest_xcrs->xcrs[i].value); |
2d5b5a66 SY |
4554 | break; |
4555 | } | |
4556 | if (r) | |
4557 | r = -EINVAL; | |
4558 | return r; | |
4559 | } | |
4560 | ||
1c0b28c2 EM |
4561 | /* |
4562 | * kvm_set_guest_paused() indicates to the guest kernel that it has been | |
4563 | * stopped by the hypervisor. This function will be called from the host only. | |
4564 | * EINVAL is returned when the host attempts to set the flag for a guest that | |
4565 | * does not support pv clocks. | |
4566 | */ | |
4567 | static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) | |
4568 | { | |
0b79459b | 4569 | if (!vcpu->arch.pv_time_enabled) |
1c0b28c2 | 4570 | return -EINVAL; |
51d59c6b | 4571 | vcpu->arch.pvclock_set_guest_stopped_request = true; |
1c0b28c2 EM |
4572 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
4573 | return 0; | |
4574 | } | |
4575 | ||
5c919412 AS |
4576 | static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, |
4577 | struct kvm_enable_cap *cap) | |
4578 | { | |
57b119da VK |
4579 | int r; |
4580 | uint16_t vmcs_version; | |
4581 | void __user *user_ptr; | |
4582 | ||
5c919412 AS |
4583 | if (cap->flags) |
4584 | return -EINVAL; | |
4585 | ||
4586 | switch (cap->cap) { | |
efc479e6 RK |
4587 | case KVM_CAP_HYPERV_SYNIC2: |
4588 | if (cap->args[0]) | |
4589 | return -EINVAL; | |
df561f66 | 4590 | fallthrough; |
b2869f28 | 4591 | |
5c919412 | 4592 | case KVM_CAP_HYPERV_SYNIC: |
546d87e5 WL |
4593 | if (!irqchip_in_kernel(vcpu->kvm)) |
4594 | return -EINVAL; | |
efc479e6 RK |
4595 | return kvm_hv_activate_synic(vcpu, cap->cap == |
4596 | KVM_CAP_HYPERV_SYNIC2); | |
57b119da | 4597 | case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: |
33b22172 | 4598 | if (!kvm_x86_ops.nested_ops->enable_evmcs) |
5158917c | 4599 | return -ENOTTY; |
33b22172 | 4600 | r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version); |
57b119da VK |
4601 | if (!r) { |
4602 | user_ptr = (void __user *)(uintptr_t)cap->args[0]; | |
4603 | if (copy_to_user(user_ptr, &vmcs_version, | |
4604 | sizeof(vmcs_version))) | |
4605 | r = -EFAULT; | |
4606 | } | |
4607 | return r; | |
344c6c80 | 4608 | case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: |
afaf0b2f | 4609 | if (!kvm_x86_ops.enable_direct_tlbflush) |
344c6c80 TL |
4610 | return -ENOTTY; |
4611 | ||
afaf0b2f | 4612 | return kvm_x86_ops.enable_direct_tlbflush(vcpu); |
57b119da | 4613 | |
66570e96 OU |
4614 | case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: |
4615 | vcpu->arch.pv_cpuid.enforce = cap->args[0]; | |
01b4f510 OU |
4616 | if (vcpu->arch.pv_cpuid.enforce) |
4617 | kvm_update_pv_runtime(vcpu); | |
66570e96 OU |
4618 | |
4619 | return 0; | |
4620 | ||
5c919412 AS |
4621 | default: |
4622 | return -EINVAL; | |
4623 | } | |
4624 | } | |
4625 | ||
313a3dc7 CO |
4626 | long kvm_arch_vcpu_ioctl(struct file *filp, |
4627 | unsigned int ioctl, unsigned long arg) | |
4628 | { | |
4629 | struct kvm_vcpu *vcpu = filp->private_data; | |
4630 | void __user *argp = (void __user *)arg; | |
4631 | int r; | |
d1ac91d8 AK |
4632 | union { |
4633 | struct kvm_lapic_state *lapic; | |
4634 | struct kvm_xsave *xsave; | |
4635 | struct kvm_xcrs *xcrs; | |
4636 | void *buffer; | |
4637 | } u; | |
4638 | ||
9b062471 CD |
4639 | vcpu_load(vcpu); |
4640 | ||
d1ac91d8 | 4641 | u.buffer = NULL; |
313a3dc7 CO |
4642 | switch (ioctl) { |
4643 | case KVM_GET_LAPIC: { | |
2204ae3c | 4644 | r = -EINVAL; |
bce87cce | 4645 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 4646 | goto out; |
254272ce BG |
4647 | u.lapic = kzalloc(sizeof(struct kvm_lapic_state), |
4648 | GFP_KERNEL_ACCOUNT); | |
313a3dc7 | 4649 | |
b772ff36 | 4650 | r = -ENOMEM; |
d1ac91d8 | 4651 | if (!u.lapic) |
b772ff36 | 4652 | goto out; |
d1ac91d8 | 4653 | r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); |
313a3dc7 CO |
4654 | if (r) |
4655 | goto out; | |
4656 | r = -EFAULT; | |
d1ac91d8 | 4657 | if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
4658 | goto out; |
4659 | r = 0; | |
4660 | break; | |
4661 | } | |
4662 | case KVM_SET_LAPIC: { | |
2204ae3c | 4663 | r = -EINVAL; |
bce87cce | 4664 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 4665 | goto out; |
ff5c2c03 | 4666 | u.lapic = memdup_user(argp, sizeof(*u.lapic)); |
9b062471 CD |
4667 | if (IS_ERR(u.lapic)) { |
4668 | r = PTR_ERR(u.lapic); | |
4669 | goto out_nofree; | |
4670 | } | |
ff5c2c03 | 4671 | |
d1ac91d8 | 4672 | r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); |
313a3dc7 CO |
4673 | break; |
4674 | } | |
f77bc6a4 ZX |
4675 | case KVM_INTERRUPT: { |
4676 | struct kvm_interrupt irq; | |
4677 | ||
4678 | r = -EFAULT; | |
0e96f31e | 4679 | if (copy_from_user(&irq, argp, sizeof(irq))) |
f77bc6a4 ZX |
4680 | goto out; |
4681 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
f77bc6a4 ZX |
4682 | break; |
4683 | } | |
c4abb7c9 JK |
4684 | case KVM_NMI: { |
4685 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
c4abb7c9 JK |
4686 | break; |
4687 | } | |
f077825a PB |
4688 | case KVM_SMI: { |
4689 | r = kvm_vcpu_ioctl_smi(vcpu); | |
4690 | break; | |
4691 | } | |
313a3dc7 CO |
4692 | case KVM_SET_CPUID: { |
4693 | struct kvm_cpuid __user *cpuid_arg = argp; | |
4694 | struct kvm_cpuid cpuid; | |
4695 | ||
4696 | r = -EFAULT; | |
0e96f31e | 4697 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
313a3dc7 CO |
4698 | goto out; |
4699 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
313a3dc7 CO |
4700 | break; |
4701 | } | |
07716717 DK |
4702 | case KVM_SET_CPUID2: { |
4703 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
4704 | struct kvm_cpuid2 cpuid; | |
4705 | ||
4706 | r = -EFAULT; | |
0e96f31e | 4707 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
07716717 DK |
4708 | goto out; |
4709 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 4710 | cpuid_arg->entries); |
07716717 DK |
4711 | break; |
4712 | } | |
4713 | case KVM_GET_CPUID2: { | |
4714 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
4715 | struct kvm_cpuid2 cpuid; | |
4716 | ||
4717 | r = -EFAULT; | |
0e96f31e | 4718 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
07716717 DK |
4719 | goto out; |
4720 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 4721 | cpuid_arg->entries); |
07716717 DK |
4722 | if (r) |
4723 | goto out; | |
4724 | r = -EFAULT; | |
0e96f31e | 4725 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) |
07716717 DK |
4726 | goto out; |
4727 | r = 0; | |
4728 | break; | |
4729 | } | |
801e459a TL |
4730 | case KVM_GET_MSRS: { |
4731 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
609e36d3 | 4732 | r = msr_io(vcpu, argp, do_get_msr, 1); |
801e459a | 4733 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 4734 | break; |
801e459a TL |
4735 | } |
4736 | case KVM_SET_MSRS: { | |
4737 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
313a3dc7 | 4738 | r = msr_io(vcpu, argp, do_set_msr, 0); |
801e459a | 4739 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 4740 | break; |
801e459a | 4741 | } |
b209749f AK |
4742 | case KVM_TPR_ACCESS_REPORTING: { |
4743 | struct kvm_tpr_access_ctl tac; | |
4744 | ||
4745 | r = -EFAULT; | |
0e96f31e | 4746 | if (copy_from_user(&tac, argp, sizeof(tac))) |
b209749f AK |
4747 | goto out; |
4748 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
4749 | if (r) | |
4750 | goto out; | |
4751 | r = -EFAULT; | |
0e96f31e | 4752 | if (copy_to_user(argp, &tac, sizeof(tac))) |
b209749f AK |
4753 | goto out; |
4754 | r = 0; | |
4755 | break; | |
4756 | }; | |
b93463aa AK |
4757 | case KVM_SET_VAPIC_ADDR: { |
4758 | struct kvm_vapic_addr va; | |
7301d6ab | 4759 | int idx; |
b93463aa AK |
4760 | |
4761 | r = -EINVAL; | |
35754c98 | 4762 | if (!lapic_in_kernel(vcpu)) |
b93463aa AK |
4763 | goto out; |
4764 | r = -EFAULT; | |
0e96f31e | 4765 | if (copy_from_user(&va, argp, sizeof(va))) |
b93463aa | 4766 | goto out; |
7301d6ab | 4767 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
fda4e2e8 | 4768 | r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); |
7301d6ab | 4769 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b93463aa AK |
4770 | break; |
4771 | } | |
890ca9ae HY |
4772 | case KVM_X86_SETUP_MCE: { |
4773 | u64 mcg_cap; | |
4774 | ||
4775 | r = -EFAULT; | |
0e96f31e | 4776 | if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) |
890ca9ae HY |
4777 | goto out; |
4778 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
4779 | break; | |
4780 | } | |
4781 | case KVM_X86_SET_MCE: { | |
4782 | struct kvm_x86_mce mce; | |
4783 | ||
4784 | r = -EFAULT; | |
0e96f31e | 4785 | if (copy_from_user(&mce, argp, sizeof(mce))) |
890ca9ae HY |
4786 | goto out; |
4787 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
4788 | break; | |
4789 | } | |
3cfc3092 JK |
4790 | case KVM_GET_VCPU_EVENTS: { |
4791 | struct kvm_vcpu_events events; | |
4792 | ||
4793 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
4794 | ||
4795 | r = -EFAULT; | |
4796 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
4797 | break; | |
4798 | r = 0; | |
4799 | break; | |
4800 | } | |
4801 | case KVM_SET_VCPU_EVENTS: { | |
4802 | struct kvm_vcpu_events events; | |
4803 | ||
4804 | r = -EFAULT; | |
4805 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
4806 | break; | |
4807 | ||
4808 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
4809 | break; | |
4810 | } | |
a1efbe77 JK |
4811 | case KVM_GET_DEBUGREGS: { |
4812 | struct kvm_debugregs dbgregs; | |
4813 | ||
4814 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
4815 | ||
4816 | r = -EFAULT; | |
4817 | if (copy_to_user(argp, &dbgregs, | |
4818 | sizeof(struct kvm_debugregs))) | |
4819 | break; | |
4820 | r = 0; | |
4821 | break; | |
4822 | } | |
4823 | case KVM_SET_DEBUGREGS: { | |
4824 | struct kvm_debugregs dbgregs; | |
4825 | ||
4826 | r = -EFAULT; | |
4827 | if (copy_from_user(&dbgregs, argp, | |
4828 | sizeof(struct kvm_debugregs))) | |
4829 | break; | |
4830 | ||
4831 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
4832 | break; | |
4833 | } | |
2d5b5a66 | 4834 | case KVM_GET_XSAVE: { |
254272ce | 4835 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); |
2d5b5a66 | 4836 | r = -ENOMEM; |
d1ac91d8 | 4837 | if (!u.xsave) |
2d5b5a66 SY |
4838 | break; |
4839 | ||
d1ac91d8 | 4840 | kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
4841 | |
4842 | r = -EFAULT; | |
d1ac91d8 | 4843 | if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
4844 | break; |
4845 | r = 0; | |
4846 | break; | |
4847 | } | |
4848 | case KVM_SET_XSAVE: { | |
ff5c2c03 | 4849 | u.xsave = memdup_user(argp, sizeof(*u.xsave)); |
9b062471 CD |
4850 | if (IS_ERR(u.xsave)) { |
4851 | r = PTR_ERR(u.xsave); | |
4852 | goto out_nofree; | |
4853 | } | |
2d5b5a66 | 4854 | |
d1ac91d8 | 4855 | r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
4856 | break; |
4857 | } | |
4858 | case KVM_GET_XCRS: { | |
254272ce | 4859 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); |
2d5b5a66 | 4860 | r = -ENOMEM; |
d1ac91d8 | 4861 | if (!u.xcrs) |
2d5b5a66 SY |
4862 | break; |
4863 | ||
d1ac91d8 | 4864 | kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
4865 | |
4866 | r = -EFAULT; | |
d1ac91d8 | 4867 | if (copy_to_user(argp, u.xcrs, |
2d5b5a66 SY |
4868 | sizeof(struct kvm_xcrs))) |
4869 | break; | |
4870 | r = 0; | |
4871 | break; | |
4872 | } | |
4873 | case KVM_SET_XCRS: { | |
ff5c2c03 | 4874 | u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); |
9b062471 CD |
4875 | if (IS_ERR(u.xcrs)) { |
4876 | r = PTR_ERR(u.xcrs); | |
4877 | goto out_nofree; | |
4878 | } | |
2d5b5a66 | 4879 | |
d1ac91d8 | 4880 | r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
4881 | break; |
4882 | } | |
92a1f12d JR |
4883 | case KVM_SET_TSC_KHZ: { |
4884 | u32 user_tsc_khz; | |
4885 | ||
4886 | r = -EINVAL; | |
92a1f12d JR |
4887 | user_tsc_khz = (u32)arg; |
4888 | ||
26769f96 MT |
4889 | if (kvm_has_tsc_control && |
4890 | user_tsc_khz >= kvm_max_guest_tsc_khz) | |
92a1f12d JR |
4891 | goto out; |
4892 | ||
cc578287 ZA |
4893 | if (user_tsc_khz == 0) |
4894 | user_tsc_khz = tsc_khz; | |
4895 | ||
381d585c HZ |
4896 | if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) |
4897 | r = 0; | |
92a1f12d | 4898 | |
92a1f12d JR |
4899 | goto out; |
4900 | } | |
4901 | case KVM_GET_TSC_KHZ: { | |
cc578287 | 4902 | r = vcpu->arch.virtual_tsc_khz; |
92a1f12d JR |
4903 | goto out; |
4904 | } | |
1c0b28c2 EM |
4905 | case KVM_KVMCLOCK_CTRL: { |
4906 | r = kvm_set_guest_paused(vcpu); | |
4907 | goto out; | |
4908 | } | |
5c919412 AS |
4909 | case KVM_ENABLE_CAP: { |
4910 | struct kvm_enable_cap cap; | |
4911 | ||
4912 | r = -EFAULT; | |
4913 | if (copy_from_user(&cap, argp, sizeof(cap))) | |
4914 | goto out; | |
4915 | r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); | |
4916 | break; | |
4917 | } | |
8fcc4b59 JM |
4918 | case KVM_GET_NESTED_STATE: { |
4919 | struct kvm_nested_state __user *user_kvm_nested_state = argp; | |
4920 | u32 user_data_size; | |
4921 | ||
4922 | r = -EINVAL; | |
33b22172 | 4923 | if (!kvm_x86_ops.nested_ops->get_state) |
8fcc4b59 JM |
4924 | break; |
4925 | ||
4926 | BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); | |
26b471c7 | 4927 | r = -EFAULT; |
8fcc4b59 | 4928 | if (get_user(user_data_size, &user_kvm_nested_state->size)) |
26b471c7 | 4929 | break; |
8fcc4b59 | 4930 | |
33b22172 PB |
4931 | r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state, |
4932 | user_data_size); | |
8fcc4b59 | 4933 | if (r < 0) |
26b471c7 | 4934 | break; |
8fcc4b59 JM |
4935 | |
4936 | if (r > user_data_size) { | |
4937 | if (put_user(r, &user_kvm_nested_state->size)) | |
26b471c7 LA |
4938 | r = -EFAULT; |
4939 | else | |
4940 | r = -E2BIG; | |
4941 | break; | |
8fcc4b59 | 4942 | } |
26b471c7 | 4943 | |
8fcc4b59 JM |
4944 | r = 0; |
4945 | break; | |
4946 | } | |
4947 | case KVM_SET_NESTED_STATE: { | |
4948 | struct kvm_nested_state __user *user_kvm_nested_state = argp; | |
4949 | struct kvm_nested_state kvm_state; | |
ad5996d9 | 4950 | int idx; |
8fcc4b59 JM |
4951 | |
4952 | r = -EINVAL; | |
33b22172 | 4953 | if (!kvm_x86_ops.nested_ops->set_state) |
8fcc4b59 JM |
4954 | break; |
4955 | ||
26b471c7 | 4956 | r = -EFAULT; |
8fcc4b59 | 4957 | if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) |
26b471c7 | 4958 | break; |
8fcc4b59 | 4959 | |
26b471c7 | 4960 | r = -EINVAL; |
8fcc4b59 | 4961 | if (kvm_state.size < sizeof(kvm_state)) |
26b471c7 | 4962 | break; |
8fcc4b59 JM |
4963 | |
4964 | if (kvm_state.flags & | |
8cab6507 | 4965 | ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE |
cc440cda PB |
4966 | | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING |
4967 | | KVM_STATE_NESTED_GIF_SET)) | |
26b471c7 | 4968 | break; |
8fcc4b59 JM |
4969 | |
4970 | /* nested_run_pending implies guest_mode. */ | |
8cab6507 VK |
4971 | if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) |
4972 | && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) | |
26b471c7 | 4973 | break; |
8fcc4b59 | 4974 | |
ad5996d9 | 4975 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
33b22172 | 4976 | r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state); |
ad5996d9 | 4977 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8fcc4b59 JM |
4978 | break; |
4979 | } | |
2bc39970 VK |
4980 | case KVM_GET_SUPPORTED_HV_CPUID: { |
4981 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
4982 | struct kvm_cpuid2 cpuid; | |
4983 | ||
4984 | r = -EFAULT; | |
4985 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) | |
4986 | goto out; | |
4987 | ||
4988 | r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid, | |
4989 | cpuid_arg->entries); | |
4990 | if (r) | |
4991 | goto out; | |
4992 | ||
4993 | r = -EFAULT; | |
4994 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) | |
4995 | goto out; | |
4996 | r = 0; | |
4997 | break; | |
4998 | } | |
313a3dc7 CO |
4999 | default: |
5000 | r = -EINVAL; | |
5001 | } | |
5002 | out: | |
d1ac91d8 | 5003 | kfree(u.buffer); |
9b062471 CD |
5004 | out_nofree: |
5005 | vcpu_put(vcpu); | |
313a3dc7 CO |
5006 | return r; |
5007 | } | |
5008 | ||
1499fa80 | 5009 | vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) |
5b1c1493 CO |
5010 | { |
5011 | return VM_FAULT_SIGBUS; | |
5012 | } | |
5013 | ||
1fe779f8 CO |
5014 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
5015 | { | |
5016 | int ret; | |
5017 | ||
5018 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
951179ce | 5019 | return -EINVAL; |
afaf0b2f | 5020 | ret = kvm_x86_ops.set_tss_addr(kvm, addr); |
1fe779f8 CO |
5021 | return ret; |
5022 | } | |
5023 | ||
b927a3ce SY |
5024 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
5025 | u64 ident_addr) | |
5026 | { | |
afaf0b2f | 5027 | return kvm_x86_ops.set_identity_map_addr(kvm, ident_addr); |
b927a3ce SY |
5028 | } |
5029 | ||
1fe779f8 | 5030 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
bc8a3d89 | 5031 | unsigned long kvm_nr_mmu_pages) |
1fe779f8 CO |
5032 | { |
5033 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
5034 | return -EINVAL; | |
5035 | ||
79fac95e | 5036 | mutex_lock(&kvm->slots_lock); |
1fe779f8 CO |
5037 | |
5038 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 5039 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 5040 | |
79fac95e | 5041 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
5042 | return 0; |
5043 | } | |
5044 | ||
bc8a3d89 | 5045 | static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) |
1fe779f8 | 5046 | { |
39de71ec | 5047 | return kvm->arch.n_max_mmu_pages; |
1fe779f8 CO |
5048 | } |
5049 | ||
1fe779f8 CO |
5050 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) |
5051 | { | |
90bca052 | 5052 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
5053 | int r; |
5054 | ||
5055 | r = 0; | |
5056 | switch (chip->chip_id) { | |
5057 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 | 5058 | memcpy(&chip->chip.pic, &pic->pics[0], |
1fe779f8 CO |
5059 | sizeof(struct kvm_pic_state)); |
5060 | break; | |
5061 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 | 5062 | memcpy(&chip->chip.pic, &pic->pics[1], |
1fe779f8 CO |
5063 | sizeof(struct kvm_pic_state)); |
5064 | break; | |
5065 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 5066 | kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
5067 | break; |
5068 | default: | |
5069 | r = -EINVAL; | |
5070 | break; | |
5071 | } | |
5072 | return r; | |
5073 | } | |
5074 | ||
5075 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
5076 | { | |
90bca052 | 5077 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
5078 | int r; |
5079 | ||
5080 | r = 0; | |
5081 | switch (chip->chip_id) { | |
5082 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 DH |
5083 | spin_lock(&pic->lock); |
5084 | memcpy(&pic->pics[0], &chip->chip.pic, | |
1fe779f8 | 5085 | sizeof(struct kvm_pic_state)); |
90bca052 | 5086 | spin_unlock(&pic->lock); |
1fe779f8 CO |
5087 | break; |
5088 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 DH |
5089 | spin_lock(&pic->lock); |
5090 | memcpy(&pic->pics[1], &chip->chip.pic, | |
1fe779f8 | 5091 | sizeof(struct kvm_pic_state)); |
90bca052 | 5092 | spin_unlock(&pic->lock); |
1fe779f8 CO |
5093 | break; |
5094 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 5095 | kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
5096 | break; |
5097 | default: | |
5098 | r = -EINVAL; | |
5099 | break; | |
5100 | } | |
90bca052 | 5101 | kvm_pic_update_irq(pic); |
1fe779f8 CO |
5102 | return r; |
5103 | } | |
5104 | ||
e0f63cb9 SY |
5105 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
5106 | { | |
34f3941c RK |
5107 | struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; |
5108 | ||
5109 | BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); | |
5110 | ||
5111 | mutex_lock(&kps->lock); | |
5112 | memcpy(ps, &kps->channels, sizeof(*ps)); | |
5113 | mutex_unlock(&kps->lock); | |
2da29bcc | 5114 | return 0; |
e0f63cb9 SY |
5115 | } |
5116 | ||
5117 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
5118 | { | |
0185604c | 5119 | int i; |
09edea72 RK |
5120 | struct kvm_pit *pit = kvm->arch.vpit; |
5121 | ||
5122 | mutex_lock(&pit->pit_state.lock); | |
34f3941c | 5123 | memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); |
0185604c | 5124 | for (i = 0; i < 3; i++) |
09edea72 RK |
5125 | kvm_pit_load_count(pit, i, ps->channels[i].count, 0); |
5126 | mutex_unlock(&pit->pit_state.lock); | |
2da29bcc | 5127 | return 0; |
e9f42757 BK |
5128 | } |
5129 | ||
5130 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
5131 | { | |
e9f42757 BK |
5132 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
5133 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
5134 | sizeof(ps->channels)); | |
5135 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
5136 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
97e69aa6 | 5137 | memset(&ps->reserved, 0, sizeof(ps->reserved)); |
2da29bcc | 5138 | return 0; |
e9f42757 BK |
5139 | } |
5140 | ||
5141 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
5142 | { | |
2da29bcc | 5143 | int start = 0; |
0185604c | 5144 | int i; |
e9f42757 | 5145 | u32 prev_legacy, cur_legacy; |
09edea72 RK |
5146 | struct kvm_pit *pit = kvm->arch.vpit; |
5147 | ||
5148 | mutex_lock(&pit->pit_state.lock); | |
5149 | prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
e9f42757 BK |
5150 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; |
5151 | if (!prev_legacy && cur_legacy) | |
5152 | start = 1; | |
09edea72 RK |
5153 | memcpy(&pit->pit_state.channels, &ps->channels, |
5154 | sizeof(pit->pit_state.channels)); | |
5155 | pit->pit_state.flags = ps->flags; | |
0185604c | 5156 | for (i = 0; i < 3; i++) |
09edea72 | 5157 | kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, |
e5e57e7a | 5158 | start && i == 0); |
09edea72 | 5159 | mutex_unlock(&pit->pit_state.lock); |
2da29bcc | 5160 | return 0; |
e0f63cb9 SY |
5161 | } |
5162 | ||
52d939a0 MT |
5163 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
5164 | struct kvm_reinject_control *control) | |
5165 | { | |
71474e2f RK |
5166 | struct kvm_pit *pit = kvm->arch.vpit; |
5167 | ||
71474e2f RK |
5168 | /* pit->pit_state.lock was overloaded to prevent userspace from getting |
5169 | * an inconsistent state after running multiple KVM_REINJECT_CONTROL | |
5170 | * ioctls in parallel. Use a separate lock if that ioctl isn't rare. | |
5171 | */ | |
5172 | mutex_lock(&pit->pit_state.lock); | |
5173 | kvm_pit_set_reinject(pit, control->pit_reinject); | |
5174 | mutex_unlock(&pit->pit_state.lock); | |
b39c90b6 | 5175 | |
52d939a0 MT |
5176 | return 0; |
5177 | } | |
5178 | ||
0dff0846 | 5179 | void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) |
5bb064dc | 5180 | { |
88178fd4 KH |
5181 | /* |
5182 | * Flush potentially hardware-cached dirty pages to dirty_bitmap. | |
5183 | */ | |
afaf0b2f SC |
5184 | if (kvm_x86_ops.flush_log_dirty) |
5185 | kvm_x86_ops.flush_log_dirty(kvm); | |
5bb064dc ZX |
5186 | } |
5187 | ||
aa2fbe6d YZ |
5188 | int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, |
5189 | bool line_status) | |
23d43cf9 CD |
5190 | { |
5191 | if (!irqchip_in_kernel(kvm)) | |
5192 | return -ENXIO; | |
5193 | ||
5194 | irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, | |
aa2fbe6d YZ |
5195 | irq_event->irq, irq_event->level, |
5196 | line_status); | |
23d43cf9 CD |
5197 | return 0; |
5198 | } | |
5199 | ||
e5d83c74 PB |
5200 | int kvm_vm_ioctl_enable_cap(struct kvm *kvm, |
5201 | struct kvm_enable_cap *cap) | |
90de4a18 NA |
5202 | { |
5203 | int r; | |
5204 | ||
5205 | if (cap->flags) | |
5206 | return -EINVAL; | |
5207 | ||
5208 | switch (cap->cap) { | |
5209 | case KVM_CAP_DISABLE_QUIRKS: | |
5210 | kvm->arch.disabled_quirks = cap->args[0]; | |
5211 | r = 0; | |
5212 | break; | |
49df6397 SR |
5213 | case KVM_CAP_SPLIT_IRQCHIP: { |
5214 | mutex_lock(&kvm->lock); | |
b053b2ae SR |
5215 | r = -EINVAL; |
5216 | if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) | |
5217 | goto split_irqchip_unlock; | |
49df6397 SR |
5218 | r = -EEXIST; |
5219 | if (irqchip_in_kernel(kvm)) | |
5220 | goto split_irqchip_unlock; | |
557abc40 | 5221 | if (kvm->created_vcpus) |
49df6397 SR |
5222 | goto split_irqchip_unlock; |
5223 | r = kvm_setup_empty_irq_routing(kvm); | |
5c0aea0e | 5224 | if (r) |
49df6397 SR |
5225 | goto split_irqchip_unlock; |
5226 | /* Pairs with irqchip_in_kernel. */ | |
5227 | smp_wmb(); | |
49776faf | 5228 | kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; |
b053b2ae | 5229 | kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; |
49df6397 SR |
5230 | r = 0; |
5231 | split_irqchip_unlock: | |
5232 | mutex_unlock(&kvm->lock); | |
5233 | break; | |
5234 | } | |
37131313 RK |
5235 | case KVM_CAP_X2APIC_API: |
5236 | r = -EINVAL; | |
5237 | if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) | |
5238 | break; | |
5239 | ||
5240 | if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) | |
5241 | kvm->arch.x2apic_format = true; | |
c519265f RK |
5242 | if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) |
5243 | kvm->arch.x2apic_broadcast_quirk_disabled = true; | |
37131313 RK |
5244 | |
5245 | r = 0; | |
5246 | break; | |
4d5422ce WL |
5247 | case KVM_CAP_X86_DISABLE_EXITS: |
5248 | r = -EINVAL; | |
5249 | if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) | |
5250 | break; | |
5251 | ||
5252 | if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && | |
5253 | kvm_can_mwait_in_guest()) | |
5254 | kvm->arch.mwait_in_guest = true; | |
766d3571 | 5255 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) |
caa057a2 | 5256 | kvm->arch.hlt_in_guest = true; |
b31c114b WL |
5257 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) |
5258 | kvm->arch.pause_in_guest = true; | |
b5170063 WL |
5259 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) |
5260 | kvm->arch.cstate_in_guest = true; | |
4d5422ce WL |
5261 | r = 0; |
5262 | break; | |
6fbbde9a DS |
5263 | case KVM_CAP_MSR_PLATFORM_INFO: |
5264 | kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; | |
5265 | r = 0; | |
c4f55198 JM |
5266 | break; |
5267 | case KVM_CAP_EXCEPTION_PAYLOAD: | |
5268 | kvm->arch.exception_payload_enabled = cap->args[0]; | |
5269 | r = 0; | |
6fbbde9a | 5270 | break; |
1ae09954 AG |
5271 | case KVM_CAP_X86_USER_SPACE_MSR: |
5272 | kvm->arch.user_space_msr_mask = cap->args[0]; | |
5273 | r = 0; | |
5274 | break; | |
90de4a18 NA |
5275 | default: |
5276 | r = -EINVAL; | |
5277 | break; | |
5278 | } | |
5279 | return r; | |
5280 | } | |
5281 | ||
1a155254 AG |
5282 | static void kvm_clear_msr_filter(struct kvm *kvm) |
5283 | { | |
5284 | u32 i; | |
5285 | u32 count = kvm->arch.msr_filter.count; | |
5286 | struct msr_bitmap_range ranges[16]; | |
5287 | ||
5288 | mutex_lock(&kvm->lock); | |
5289 | kvm->arch.msr_filter.count = 0; | |
5290 | memcpy(ranges, kvm->arch.msr_filter.ranges, count * sizeof(ranges[0])); | |
5291 | mutex_unlock(&kvm->lock); | |
5292 | synchronize_srcu(&kvm->srcu); | |
5293 | ||
5294 | for (i = 0; i < count; i++) | |
5295 | kfree(ranges[i].bitmap); | |
5296 | } | |
5297 | ||
5298 | static int kvm_add_msr_filter(struct kvm *kvm, struct kvm_msr_filter_range *user_range) | |
5299 | { | |
5300 | struct msr_bitmap_range *ranges = kvm->arch.msr_filter.ranges; | |
5301 | struct msr_bitmap_range range; | |
5302 | unsigned long *bitmap = NULL; | |
5303 | size_t bitmap_size; | |
5304 | int r; | |
5305 | ||
5306 | if (!user_range->nmsrs) | |
5307 | return 0; | |
5308 | ||
5309 | bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long); | |
5310 | if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE) | |
5311 | return -EINVAL; | |
5312 | ||
5313 | bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size); | |
5314 | if (IS_ERR(bitmap)) | |
5315 | return PTR_ERR(bitmap); | |
5316 | ||
5317 | range = (struct msr_bitmap_range) { | |
5318 | .flags = user_range->flags, | |
5319 | .base = user_range->base, | |
5320 | .nmsrs = user_range->nmsrs, | |
5321 | .bitmap = bitmap, | |
5322 | }; | |
5323 | ||
5324 | if (range.flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) { | |
5325 | r = -EINVAL; | |
5326 | goto err; | |
5327 | } | |
5328 | ||
5329 | if (!range.flags) { | |
5330 | r = -EINVAL; | |
5331 | goto err; | |
5332 | } | |
5333 | ||
5334 | /* Everything ok, add this range identifier to our global pool */ | |
5335 | ranges[kvm->arch.msr_filter.count] = range; | |
5336 | /* Make sure we filled the array before we tell anyone to walk it */ | |
5337 | smp_wmb(); | |
5338 | kvm->arch.msr_filter.count++; | |
5339 | ||
5340 | return 0; | |
5341 | err: | |
5342 | kfree(bitmap); | |
5343 | return r; | |
5344 | } | |
5345 | ||
5346 | static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp) | |
5347 | { | |
5348 | struct kvm_msr_filter __user *user_msr_filter = argp; | |
5349 | struct kvm_msr_filter filter; | |
5350 | bool default_allow; | |
5351 | int r = 0; | |
043248b3 | 5352 | bool empty = true; |
1a155254 AG |
5353 | u32 i; |
5354 | ||
5355 | if (copy_from_user(&filter, user_msr_filter, sizeof(filter))) | |
5356 | return -EFAULT; | |
5357 | ||
043248b3 PB |
5358 | for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) |
5359 | empty &= !filter.ranges[i].nmsrs; | |
1a155254 AG |
5360 | |
5361 | default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY); | |
043248b3 PB |
5362 | if (empty && !default_allow) |
5363 | return -EINVAL; | |
5364 | ||
5365 | kvm_clear_msr_filter(kvm); | |
5366 | ||
1a155254 AG |
5367 | kvm->arch.msr_filter.default_allow = default_allow; |
5368 | ||
5369 | /* | |
5370 | * Protect from concurrent calls to this function that could trigger | |
5371 | * a TOCTOU violation on kvm->arch.msr_filter.count. | |
5372 | */ | |
5373 | mutex_lock(&kvm->lock); | |
5374 | for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) { | |
5375 | r = kvm_add_msr_filter(kvm, &filter.ranges[i]); | |
5376 | if (r) | |
5377 | break; | |
5378 | } | |
5379 | ||
5380 | kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED); | |
5381 | mutex_unlock(&kvm->lock); | |
5382 | ||
5383 | return r; | |
5384 | } | |
5385 | ||
1fe779f8 CO |
5386 | long kvm_arch_vm_ioctl(struct file *filp, |
5387 | unsigned int ioctl, unsigned long arg) | |
5388 | { | |
5389 | struct kvm *kvm = filp->private_data; | |
5390 | void __user *argp = (void __user *)arg; | |
367e1319 | 5391 | int r = -ENOTTY; |
f0d66275 DH |
5392 | /* |
5393 | * This union makes it completely explicit to gcc-3.x | |
5394 | * that these two variables' stack usage should be | |
5395 | * combined, not added together. | |
5396 | */ | |
5397 | union { | |
5398 | struct kvm_pit_state ps; | |
e9f42757 | 5399 | struct kvm_pit_state2 ps2; |
c5ff41ce | 5400 | struct kvm_pit_config pit_config; |
f0d66275 | 5401 | } u; |
1fe779f8 CO |
5402 | |
5403 | switch (ioctl) { | |
5404 | case KVM_SET_TSS_ADDR: | |
5405 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
1fe779f8 | 5406 | break; |
b927a3ce SY |
5407 | case KVM_SET_IDENTITY_MAP_ADDR: { |
5408 | u64 ident_addr; | |
5409 | ||
1af1ac91 DH |
5410 | mutex_lock(&kvm->lock); |
5411 | r = -EINVAL; | |
5412 | if (kvm->created_vcpus) | |
5413 | goto set_identity_unlock; | |
b927a3ce | 5414 | r = -EFAULT; |
0e96f31e | 5415 | if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) |
1af1ac91 | 5416 | goto set_identity_unlock; |
b927a3ce | 5417 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); |
1af1ac91 DH |
5418 | set_identity_unlock: |
5419 | mutex_unlock(&kvm->lock); | |
b927a3ce SY |
5420 | break; |
5421 | } | |
1fe779f8 CO |
5422 | case KVM_SET_NR_MMU_PAGES: |
5423 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
1fe779f8 CO |
5424 | break; |
5425 | case KVM_GET_NR_MMU_PAGES: | |
5426 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
5427 | break; | |
3ddea128 | 5428 | case KVM_CREATE_IRQCHIP: { |
3ddea128 | 5429 | mutex_lock(&kvm->lock); |
09941366 | 5430 | |
3ddea128 | 5431 | r = -EEXIST; |
35e6eaa3 | 5432 | if (irqchip_in_kernel(kvm)) |
3ddea128 | 5433 | goto create_irqchip_unlock; |
09941366 | 5434 | |
3e515705 | 5435 | r = -EINVAL; |
557abc40 | 5436 | if (kvm->created_vcpus) |
3e515705 | 5437 | goto create_irqchip_unlock; |
09941366 RK |
5438 | |
5439 | r = kvm_pic_init(kvm); | |
5440 | if (r) | |
3ddea128 | 5441 | goto create_irqchip_unlock; |
09941366 RK |
5442 | |
5443 | r = kvm_ioapic_init(kvm); | |
5444 | if (r) { | |
09941366 | 5445 | kvm_pic_destroy(kvm); |
3ddea128 | 5446 | goto create_irqchip_unlock; |
09941366 RK |
5447 | } |
5448 | ||
399ec807 AK |
5449 | r = kvm_setup_default_irq_routing(kvm); |
5450 | if (r) { | |
72bb2fcd | 5451 | kvm_ioapic_destroy(kvm); |
09941366 | 5452 | kvm_pic_destroy(kvm); |
71ba994c | 5453 | goto create_irqchip_unlock; |
399ec807 | 5454 | } |
49776faf | 5455 | /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ |
71ba994c | 5456 | smp_wmb(); |
49776faf | 5457 | kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; |
3ddea128 MT |
5458 | create_irqchip_unlock: |
5459 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 5460 | break; |
3ddea128 | 5461 | } |
7837699f | 5462 | case KVM_CREATE_PIT: |
c5ff41ce JK |
5463 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
5464 | goto create_pit; | |
5465 | case KVM_CREATE_PIT2: | |
5466 | r = -EFAULT; | |
5467 | if (copy_from_user(&u.pit_config, argp, | |
5468 | sizeof(struct kvm_pit_config))) | |
5469 | goto out; | |
5470 | create_pit: | |
250715a6 | 5471 | mutex_lock(&kvm->lock); |
269e05e4 AK |
5472 | r = -EEXIST; |
5473 | if (kvm->arch.vpit) | |
5474 | goto create_pit_unlock; | |
7837699f | 5475 | r = -ENOMEM; |
c5ff41ce | 5476 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
5477 | if (kvm->arch.vpit) |
5478 | r = 0; | |
269e05e4 | 5479 | create_pit_unlock: |
250715a6 | 5480 | mutex_unlock(&kvm->lock); |
7837699f | 5481 | break; |
1fe779f8 CO |
5482 | case KVM_GET_IRQCHIP: { |
5483 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 5484 | struct kvm_irqchip *chip; |
1fe779f8 | 5485 | |
ff5c2c03 SL |
5486 | chip = memdup_user(argp, sizeof(*chip)); |
5487 | if (IS_ERR(chip)) { | |
5488 | r = PTR_ERR(chip); | |
1fe779f8 | 5489 | goto out; |
ff5c2c03 SL |
5490 | } |
5491 | ||
1fe779f8 | 5492 | r = -ENXIO; |
826da321 | 5493 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
5494 | goto get_irqchip_out; |
5495 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 5496 | if (r) |
f0d66275 | 5497 | goto get_irqchip_out; |
1fe779f8 | 5498 | r = -EFAULT; |
0e96f31e | 5499 | if (copy_to_user(argp, chip, sizeof(*chip))) |
f0d66275 | 5500 | goto get_irqchip_out; |
1fe779f8 | 5501 | r = 0; |
f0d66275 DH |
5502 | get_irqchip_out: |
5503 | kfree(chip); | |
1fe779f8 CO |
5504 | break; |
5505 | } | |
5506 | case KVM_SET_IRQCHIP: { | |
5507 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 5508 | struct kvm_irqchip *chip; |
1fe779f8 | 5509 | |
ff5c2c03 SL |
5510 | chip = memdup_user(argp, sizeof(*chip)); |
5511 | if (IS_ERR(chip)) { | |
5512 | r = PTR_ERR(chip); | |
1fe779f8 | 5513 | goto out; |
ff5c2c03 SL |
5514 | } |
5515 | ||
1fe779f8 | 5516 | r = -ENXIO; |
826da321 | 5517 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
5518 | goto set_irqchip_out; |
5519 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
f0d66275 DH |
5520 | set_irqchip_out: |
5521 | kfree(chip); | |
1fe779f8 CO |
5522 | break; |
5523 | } | |
e0f63cb9 | 5524 | case KVM_GET_PIT: { |
e0f63cb9 | 5525 | r = -EFAULT; |
f0d66275 | 5526 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
5527 | goto out; |
5528 | r = -ENXIO; | |
5529 | if (!kvm->arch.vpit) | |
5530 | goto out; | |
f0d66275 | 5531 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
5532 | if (r) |
5533 | goto out; | |
5534 | r = -EFAULT; | |
f0d66275 | 5535 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
5536 | goto out; |
5537 | r = 0; | |
5538 | break; | |
5539 | } | |
5540 | case KVM_SET_PIT: { | |
e0f63cb9 | 5541 | r = -EFAULT; |
0e96f31e | 5542 | if (copy_from_user(&u.ps, argp, sizeof(u.ps))) |
e0f63cb9 | 5543 | goto out; |
7289fdb5 | 5544 | mutex_lock(&kvm->lock); |
e0f63cb9 SY |
5545 | r = -ENXIO; |
5546 | if (!kvm->arch.vpit) | |
7289fdb5 | 5547 | goto set_pit_out; |
f0d66275 | 5548 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
7289fdb5 SR |
5549 | set_pit_out: |
5550 | mutex_unlock(&kvm->lock); | |
e0f63cb9 SY |
5551 | break; |
5552 | } | |
e9f42757 BK |
5553 | case KVM_GET_PIT2: { |
5554 | r = -ENXIO; | |
5555 | if (!kvm->arch.vpit) | |
5556 | goto out; | |
5557 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
5558 | if (r) | |
5559 | goto out; | |
5560 | r = -EFAULT; | |
5561 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
5562 | goto out; | |
5563 | r = 0; | |
5564 | break; | |
5565 | } | |
5566 | case KVM_SET_PIT2: { | |
5567 | r = -EFAULT; | |
5568 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
5569 | goto out; | |
7289fdb5 | 5570 | mutex_lock(&kvm->lock); |
e9f42757 BK |
5571 | r = -ENXIO; |
5572 | if (!kvm->arch.vpit) | |
7289fdb5 | 5573 | goto set_pit2_out; |
e9f42757 | 5574 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); |
7289fdb5 SR |
5575 | set_pit2_out: |
5576 | mutex_unlock(&kvm->lock); | |
e9f42757 BK |
5577 | break; |
5578 | } | |
52d939a0 MT |
5579 | case KVM_REINJECT_CONTROL: { |
5580 | struct kvm_reinject_control control; | |
5581 | r = -EFAULT; | |
5582 | if (copy_from_user(&control, argp, sizeof(control))) | |
5583 | goto out; | |
cad23e72 ML |
5584 | r = -ENXIO; |
5585 | if (!kvm->arch.vpit) | |
5586 | goto out; | |
52d939a0 | 5587 | r = kvm_vm_ioctl_reinject(kvm, &control); |
52d939a0 MT |
5588 | break; |
5589 | } | |
d71ba788 PB |
5590 | case KVM_SET_BOOT_CPU_ID: |
5591 | r = 0; | |
5592 | mutex_lock(&kvm->lock); | |
557abc40 | 5593 | if (kvm->created_vcpus) |
d71ba788 PB |
5594 | r = -EBUSY; |
5595 | else | |
5596 | kvm->arch.bsp_vcpu_id = arg; | |
5597 | mutex_unlock(&kvm->lock); | |
5598 | break; | |
ffde22ac | 5599 | case KVM_XEN_HVM_CONFIG: { |
51776043 | 5600 | struct kvm_xen_hvm_config xhc; |
ffde22ac | 5601 | r = -EFAULT; |
51776043 | 5602 | if (copy_from_user(&xhc, argp, sizeof(xhc))) |
ffde22ac ES |
5603 | goto out; |
5604 | r = -EINVAL; | |
51776043 | 5605 | if (xhc.flags) |
ffde22ac | 5606 | goto out; |
51776043 | 5607 | memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc)); |
ffde22ac ES |
5608 | r = 0; |
5609 | break; | |
5610 | } | |
afbcf7ab | 5611 | case KVM_SET_CLOCK: { |
afbcf7ab GC |
5612 | struct kvm_clock_data user_ns; |
5613 | u64 now_ns; | |
afbcf7ab GC |
5614 | |
5615 | r = -EFAULT; | |
5616 | if (copy_from_user(&user_ns, argp, sizeof(user_ns))) | |
5617 | goto out; | |
5618 | ||
5619 | r = -EINVAL; | |
5620 | if (user_ns.flags) | |
5621 | goto out; | |
5622 | ||
5623 | r = 0; | |
0bc48bea RK |
5624 | /* |
5625 | * TODO: userspace has to take care of races with VCPU_RUN, so | |
5626 | * kvm_gen_update_masterclock() can be cut down to locked | |
5627 | * pvclock_update_vm_gtod_copy(). | |
5628 | */ | |
5629 | kvm_gen_update_masterclock(kvm); | |
e891a32e | 5630 | now_ns = get_kvmclock_ns(kvm); |
108b249c | 5631 | kvm->arch.kvmclock_offset += user_ns.clock - now_ns; |
0bc48bea | 5632 | kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE); |
afbcf7ab GC |
5633 | break; |
5634 | } | |
5635 | case KVM_GET_CLOCK: { | |
afbcf7ab GC |
5636 | struct kvm_clock_data user_ns; |
5637 | u64 now_ns; | |
5638 | ||
e891a32e | 5639 | now_ns = get_kvmclock_ns(kvm); |
108b249c | 5640 | user_ns.clock = now_ns; |
e3fd9a93 | 5641 | user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; |
97e69aa6 | 5642 | memset(&user_ns.pad, 0, sizeof(user_ns.pad)); |
afbcf7ab GC |
5643 | |
5644 | r = -EFAULT; | |
5645 | if (copy_to_user(argp, &user_ns, sizeof(user_ns))) | |
5646 | goto out; | |
5647 | r = 0; | |
5648 | break; | |
5649 | } | |
5acc5c06 BS |
5650 | case KVM_MEMORY_ENCRYPT_OP: { |
5651 | r = -ENOTTY; | |
afaf0b2f SC |
5652 | if (kvm_x86_ops.mem_enc_op) |
5653 | r = kvm_x86_ops.mem_enc_op(kvm, argp); | |
5acc5c06 BS |
5654 | break; |
5655 | } | |
69eaedee BS |
5656 | case KVM_MEMORY_ENCRYPT_REG_REGION: { |
5657 | struct kvm_enc_region region; | |
5658 | ||
5659 | r = -EFAULT; | |
5660 | if (copy_from_user(®ion, argp, sizeof(region))) | |
5661 | goto out; | |
5662 | ||
5663 | r = -ENOTTY; | |
afaf0b2f SC |
5664 | if (kvm_x86_ops.mem_enc_reg_region) |
5665 | r = kvm_x86_ops.mem_enc_reg_region(kvm, ®ion); | |
69eaedee BS |
5666 | break; |
5667 | } | |
5668 | case KVM_MEMORY_ENCRYPT_UNREG_REGION: { | |
5669 | struct kvm_enc_region region; | |
5670 | ||
5671 | r = -EFAULT; | |
5672 | if (copy_from_user(®ion, argp, sizeof(region))) | |
5673 | goto out; | |
5674 | ||
5675 | r = -ENOTTY; | |
afaf0b2f SC |
5676 | if (kvm_x86_ops.mem_enc_unreg_region) |
5677 | r = kvm_x86_ops.mem_enc_unreg_region(kvm, ®ion); | |
69eaedee BS |
5678 | break; |
5679 | } | |
faeb7833 RK |
5680 | case KVM_HYPERV_EVENTFD: { |
5681 | struct kvm_hyperv_eventfd hvevfd; | |
5682 | ||
5683 | r = -EFAULT; | |
5684 | if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) | |
5685 | goto out; | |
5686 | r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); | |
5687 | break; | |
5688 | } | |
66bb8a06 EH |
5689 | case KVM_SET_PMU_EVENT_FILTER: |
5690 | r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); | |
5691 | break; | |
1a155254 AG |
5692 | case KVM_X86_SET_MSR_FILTER: |
5693 | r = kvm_vm_ioctl_set_msr_filter(kvm, argp); | |
5694 | break; | |
1fe779f8 | 5695 | default: |
ad6260da | 5696 | r = -ENOTTY; |
1fe779f8 CO |
5697 | } |
5698 | out: | |
5699 | return r; | |
5700 | } | |
5701 | ||
a16b043c | 5702 | static void kvm_init_msr_list(void) |
043405e1 | 5703 | { |
24c29b7a | 5704 | struct x86_pmu_capability x86_pmu; |
043405e1 | 5705 | u32 dummy[2]; |
7a5ee6ed | 5706 | unsigned i; |
043405e1 | 5707 | |
e2ada66e | 5708 | BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4, |
7a5ee6ed | 5709 | "Please update the fixed PMCs in msrs_to_saved_all[]"); |
24c29b7a PB |
5710 | |
5711 | perf_get_x86_pmu_capability(&x86_pmu); | |
e2ada66e | 5712 | |
6cbee2b9 XL |
5713 | num_msrs_to_save = 0; |
5714 | num_emulated_msrs = 0; | |
5715 | num_msr_based_features = 0; | |
5716 | ||
7a5ee6ed CQ |
5717 | for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) { |
5718 | if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0) | |
043405e1 | 5719 | continue; |
93c4adc7 PB |
5720 | |
5721 | /* | |
5722 | * Even MSRs that are valid in the host may not be exposed | |
9dbe6cf9 | 5723 | * to the guests in some cases. |
93c4adc7 | 5724 | */ |
7a5ee6ed | 5725 | switch (msrs_to_save_all[i]) { |
93c4adc7 | 5726 | case MSR_IA32_BNDCFGS: |
503234b3 | 5727 | if (!kvm_mpx_supported()) |
93c4adc7 PB |
5728 | continue; |
5729 | break; | |
9dbe6cf9 | 5730 | case MSR_TSC_AUX: |
13908510 | 5731 | if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) |
9dbe6cf9 PB |
5732 | continue; |
5733 | break; | |
f4cfcd2d ML |
5734 | case MSR_IA32_UMWAIT_CONTROL: |
5735 | if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG)) | |
5736 | continue; | |
5737 | break; | |
bf8c55d8 CP |
5738 | case MSR_IA32_RTIT_CTL: |
5739 | case MSR_IA32_RTIT_STATUS: | |
7b874c26 | 5740 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) |
bf8c55d8 CP |
5741 | continue; |
5742 | break; | |
5743 | case MSR_IA32_RTIT_CR3_MATCH: | |
7b874c26 | 5744 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
bf8c55d8 CP |
5745 | !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) |
5746 | continue; | |
5747 | break; | |
5748 | case MSR_IA32_RTIT_OUTPUT_BASE: | |
5749 | case MSR_IA32_RTIT_OUTPUT_MASK: | |
7b874c26 | 5750 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
bf8c55d8 CP |
5751 | (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && |
5752 | !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) | |
5753 | continue; | |
5754 | break; | |
7cb85fc4 | 5755 | case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: |
7b874c26 | 5756 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
7a5ee6ed | 5757 | msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >= |
bf8c55d8 CP |
5758 | intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) |
5759 | continue; | |
5760 | break; | |
cf05a67b | 5761 | case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17: |
7a5ee6ed | 5762 | if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >= |
24c29b7a PB |
5763 | min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) |
5764 | continue; | |
5765 | break; | |
cf05a67b | 5766 | case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17: |
7a5ee6ed | 5767 | if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= |
24c29b7a PB |
5768 | min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) |
5769 | continue; | |
7cb85fc4 | 5770 | break; |
93c4adc7 PB |
5771 | default: |
5772 | break; | |
5773 | } | |
5774 | ||
7a5ee6ed | 5775 | msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i]; |
043405e1 | 5776 | } |
62ef68bb | 5777 | |
7a5ee6ed | 5778 | for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) { |
afaf0b2f | 5779 | if (!kvm_x86_ops.has_emulated_msr(emulated_msrs_all[i])) |
bc226f07 | 5780 | continue; |
62ef68bb | 5781 | |
7a5ee6ed | 5782 | emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i]; |
62ef68bb | 5783 | } |
801e459a | 5784 | |
7a5ee6ed | 5785 | for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) { |
801e459a TL |
5786 | struct kvm_msr_entry msr; |
5787 | ||
7a5ee6ed | 5788 | msr.index = msr_based_features_all[i]; |
66421c1e | 5789 | if (kvm_get_msr_feature(&msr)) |
801e459a TL |
5790 | continue; |
5791 | ||
7a5ee6ed | 5792 | msr_based_features[num_msr_based_features++] = msr_based_features_all[i]; |
801e459a | 5793 | } |
043405e1 CO |
5794 | } |
5795 | ||
bda9020e MT |
5796 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
5797 | const void *v) | |
bbd9b64e | 5798 | { |
70252a10 AK |
5799 | int handled = 0; |
5800 | int n; | |
5801 | ||
5802 | do { | |
5803 | n = min(len, 8); | |
bce87cce | 5804 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
5805 | !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) |
5806 | && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 AK |
5807 | break; |
5808 | handled += n; | |
5809 | addr += n; | |
5810 | len -= n; | |
5811 | v += n; | |
5812 | } while (len); | |
bbd9b64e | 5813 | |
70252a10 | 5814 | return handled; |
bbd9b64e CO |
5815 | } |
5816 | ||
bda9020e | 5817 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 5818 | { |
70252a10 AK |
5819 | int handled = 0; |
5820 | int n; | |
5821 | ||
5822 | do { | |
5823 | n = min(len, 8); | |
bce87cce | 5824 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
5825 | !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, |
5826 | addr, n, v)) | |
5827 | && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 | 5828 | break; |
e39d200f | 5829 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); |
70252a10 AK |
5830 | handled += n; |
5831 | addr += n; | |
5832 | len -= n; | |
5833 | v += n; | |
5834 | } while (len); | |
bbd9b64e | 5835 | |
70252a10 | 5836 | return handled; |
bbd9b64e CO |
5837 | } |
5838 | ||
2dafc6c2 GN |
5839 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
5840 | struct kvm_segment *var, int seg) | |
5841 | { | |
afaf0b2f | 5842 | kvm_x86_ops.set_segment(vcpu, var, seg); |
2dafc6c2 GN |
5843 | } |
5844 | ||
5845 | void kvm_get_segment(struct kvm_vcpu *vcpu, | |
5846 | struct kvm_segment *var, int seg) | |
5847 | { | |
afaf0b2f | 5848 | kvm_x86_ops.get_segment(vcpu, var, seg); |
2dafc6c2 GN |
5849 | } |
5850 | ||
54987b7a PB |
5851 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
5852 | struct x86_exception *exception) | |
02f59dc9 JR |
5853 | { |
5854 | gpa_t t_gpa; | |
02f59dc9 JR |
5855 | |
5856 | BUG_ON(!mmu_is_nested(vcpu)); | |
5857 | ||
5858 | /* NPT walks are always user-walks */ | |
5859 | access |= PFERR_USER_MASK; | |
44dd3ffa | 5860 | t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception); |
02f59dc9 JR |
5861 | |
5862 | return t_gpa; | |
5863 | } | |
5864 | ||
ab9ae313 AK |
5865 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
5866 | struct x86_exception *exception) | |
1871c602 | 5867 | { |
afaf0b2f | 5868 | u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
ab9ae313 | 5869 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
5870 | } |
5871 | ||
ab9ae313 AK |
5872 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, |
5873 | struct x86_exception *exception) | |
1871c602 | 5874 | { |
afaf0b2f | 5875 | u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
1871c602 | 5876 | access |= PFERR_FETCH_MASK; |
ab9ae313 | 5877 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
5878 | } |
5879 | ||
ab9ae313 AK |
5880 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, |
5881 | struct x86_exception *exception) | |
1871c602 | 5882 | { |
afaf0b2f | 5883 | u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
1871c602 | 5884 | access |= PFERR_WRITE_MASK; |
ab9ae313 | 5885 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
5886 | } |
5887 | ||
5888 | /* uses this to access any guest's mapped memory without checking CPL */ | |
ab9ae313 AK |
5889 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, |
5890 | struct x86_exception *exception) | |
1871c602 | 5891 | { |
ab9ae313 | 5892 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); |
1871c602 GN |
5893 | } |
5894 | ||
5895 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
5896 | struct kvm_vcpu *vcpu, u32 access, | |
bcc55cba | 5897 | struct x86_exception *exception) |
bbd9b64e CO |
5898 | { |
5899 | void *data = val; | |
10589a46 | 5900 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
5901 | |
5902 | while (bytes) { | |
14dfe855 | 5903 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, |
ab9ae313 | 5904 | exception); |
bbd9b64e | 5905 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 5906 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
5907 | int ret; |
5908 | ||
bcc55cba | 5909 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 5910 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa PB |
5911 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, |
5912 | offset, toread); | |
10589a46 | 5913 | if (ret < 0) { |
c3cd7ffa | 5914 | r = X86EMUL_IO_NEEDED; |
10589a46 MT |
5915 | goto out; |
5916 | } | |
bbd9b64e | 5917 | |
77c2002e IE |
5918 | bytes -= toread; |
5919 | data += toread; | |
5920 | addr += toread; | |
bbd9b64e | 5921 | } |
10589a46 | 5922 | out: |
10589a46 | 5923 | return r; |
bbd9b64e | 5924 | } |
77c2002e | 5925 | |
1871c602 | 5926 | /* used for instruction fetching */ |
0f65dd70 AK |
5927 | static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, |
5928 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 5929 | struct x86_exception *exception) |
1871c602 | 5930 | { |
0f65dd70 | 5931 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
afaf0b2f | 5932 | u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
44583cba PB |
5933 | unsigned offset; |
5934 | int ret; | |
0f65dd70 | 5935 | |
44583cba PB |
5936 | /* Inline kvm_read_guest_virt_helper for speed. */ |
5937 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, | |
5938 | exception); | |
5939 | if (unlikely(gpa == UNMAPPED_GVA)) | |
5940 | return X86EMUL_PROPAGATE_FAULT; | |
5941 | ||
5942 | offset = addr & (PAGE_SIZE-1); | |
5943 | if (WARN_ON(offset + bytes > PAGE_SIZE)) | |
5944 | bytes = (unsigned)PAGE_SIZE - offset; | |
54bf36aa PB |
5945 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, |
5946 | offset, bytes); | |
44583cba PB |
5947 | if (unlikely(ret < 0)) |
5948 | return X86EMUL_IO_NEEDED; | |
5949 | ||
5950 | return X86EMUL_CONTINUE; | |
1871c602 GN |
5951 | } |
5952 | ||
ce14e868 | 5953 | int kvm_read_guest_virt(struct kvm_vcpu *vcpu, |
0f65dd70 | 5954 | gva_t addr, void *val, unsigned int bytes, |
bcc55cba | 5955 | struct x86_exception *exception) |
1871c602 | 5956 | { |
afaf0b2f | 5957 | u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
0f65dd70 | 5958 | |
353c0956 PB |
5959 | /* |
5960 | * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED | |
5961 | * is returned, but our callers are not ready for that and they blindly | |
5962 | * call kvm_inject_page_fault. Ensure that they at least do not leak | |
5963 | * uninitialized kernel stack memory into cr2 and error code. | |
5964 | */ | |
5965 | memset(exception, 0, sizeof(*exception)); | |
1871c602 | 5966 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, |
bcc55cba | 5967 | exception); |
1871c602 | 5968 | } |
064aea77 | 5969 | EXPORT_SYMBOL_GPL(kvm_read_guest_virt); |
1871c602 | 5970 | |
ce14e868 PB |
5971 | static int emulator_read_std(struct x86_emulate_ctxt *ctxt, |
5972 | gva_t addr, void *val, unsigned int bytes, | |
3c9fa24c | 5973 | struct x86_exception *exception, bool system) |
1871c602 | 5974 | { |
0f65dd70 | 5975 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
3c9fa24c PB |
5976 | u32 access = 0; |
5977 | ||
afaf0b2f | 5978 | if (!system && kvm_x86_ops.get_cpl(vcpu) == 3) |
3c9fa24c PB |
5979 | access |= PFERR_USER_MASK; |
5980 | ||
5981 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); | |
1871c602 GN |
5982 | } |
5983 | ||
7a036a6f RK |
5984 | static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, |
5985 | unsigned long addr, void *val, unsigned int bytes) | |
5986 | { | |
5987 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
5988 | int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); | |
5989 | ||
5990 | return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; | |
5991 | } | |
5992 | ||
ce14e868 PB |
5993 | static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, |
5994 | struct kvm_vcpu *vcpu, u32 access, | |
5995 | struct x86_exception *exception) | |
77c2002e IE |
5996 | { |
5997 | void *data = val; | |
5998 | int r = X86EMUL_CONTINUE; | |
5999 | ||
6000 | while (bytes) { | |
14dfe855 | 6001 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, |
ce14e868 | 6002 | access, |
ab9ae313 | 6003 | exception); |
77c2002e IE |
6004 | unsigned offset = addr & (PAGE_SIZE-1); |
6005 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
6006 | int ret; | |
6007 | ||
bcc55cba | 6008 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 6009 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa | 6010 | ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); |
77c2002e | 6011 | if (ret < 0) { |
c3cd7ffa | 6012 | r = X86EMUL_IO_NEEDED; |
77c2002e IE |
6013 | goto out; |
6014 | } | |
6015 | ||
6016 | bytes -= towrite; | |
6017 | data += towrite; | |
6018 | addr += towrite; | |
6019 | } | |
6020 | out: | |
6021 | return r; | |
6022 | } | |
ce14e868 PB |
6023 | |
6024 | static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, | |
3c9fa24c PB |
6025 | unsigned int bytes, struct x86_exception *exception, |
6026 | bool system) | |
ce14e868 PB |
6027 | { |
6028 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
3c9fa24c PB |
6029 | u32 access = PFERR_WRITE_MASK; |
6030 | ||
afaf0b2f | 6031 | if (!system && kvm_x86_ops.get_cpl(vcpu) == 3) |
3c9fa24c | 6032 | access |= PFERR_USER_MASK; |
ce14e868 PB |
6033 | |
6034 | return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, | |
3c9fa24c | 6035 | access, exception); |
ce14e868 PB |
6036 | } |
6037 | ||
6038 | int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, | |
6039 | unsigned int bytes, struct x86_exception *exception) | |
6040 | { | |
c595ceee PB |
6041 | /* kvm_write_guest_virt_system can pull in tons of pages. */ |
6042 | vcpu->arch.l1tf_flush_l1d = true; | |
6043 | ||
ce14e868 PB |
6044 | return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, |
6045 | PFERR_WRITE_MASK, exception); | |
6046 | } | |
6a4d7550 | 6047 | EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); |
77c2002e | 6048 | |
082d06ed WL |
6049 | int handle_ud(struct kvm_vcpu *vcpu) |
6050 | { | |
b3dc0695 | 6051 | static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX }; |
6c86eedc | 6052 | int emul_type = EMULTYPE_TRAP_UD; |
6c86eedc WL |
6053 | char sig[5]; /* ud2; .ascii "kvm" */ |
6054 | struct x86_exception e; | |
6055 | ||
09e3e2a1 SC |
6056 | if (unlikely(!kvm_x86_ops.can_emulate_instruction(vcpu, NULL, 0))) |
6057 | return 1; | |
6058 | ||
6c86eedc | 6059 | if (force_emulation_prefix && |
3c9fa24c PB |
6060 | kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), |
6061 | sig, sizeof(sig), &e) == 0 && | |
b3dc0695 | 6062 | memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) { |
6c86eedc | 6063 | kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); |
b4000606 | 6064 | emul_type = EMULTYPE_TRAP_UD_FORCED; |
6c86eedc | 6065 | } |
082d06ed | 6066 | |
60fc3d02 | 6067 | return kvm_emulate_instruction(vcpu, emul_type); |
082d06ed WL |
6068 | } |
6069 | EXPORT_SYMBOL_GPL(handle_ud); | |
6070 | ||
0f89b207 TL |
6071 | static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
6072 | gpa_t gpa, bool write) | |
6073 | { | |
6074 | /* For APIC access vmexit */ | |
6075 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
6076 | return 1; | |
6077 | ||
6078 | if (vcpu_match_mmio_gpa(vcpu, gpa)) { | |
6079 | trace_vcpu_match_mmio(gva, gpa, write, true); | |
6080 | return 1; | |
6081 | } | |
6082 | ||
6083 | return 0; | |
6084 | } | |
6085 | ||
af7cc7d1 XG |
6086 | static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
6087 | gpa_t *gpa, struct x86_exception *exception, | |
6088 | bool write) | |
6089 | { | |
afaf0b2f | 6090 | u32 access = ((kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) |
97d64b78 | 6091 | | (write ? PFERR_WRITE_MASK : 0); |
af7cc7d1 | 6092 | |
be94f6b7 HH |
6093 | /* |
6094 | * currently PKRU is only applied to ept enabled guest so | |
6095 | * there is no pkey in EPT page table for L1 guest or EPT | |
6096 | * shadow page table for L2 guest. | |
6097 | */ | |
97d64b78 | 6098 | if (vcpu_match_mmio_gva(vcpu, gva) |
97ec8c06 | 6099 | && !permission_fault(vcpu, vcpu->arch.walk_mmu, |
871bd034 | 6100 | vcpu->arch.mmio_access, 0, access)) { |
bebb106a XG |
6101 | *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | |
6102 | (gva & (PAGE_SIZE - 1)); | |
4f022648 | 6103 | trace_vcpu_match_mmio(gva, *gpa, write, false); |
bebb106a XG |
6104 | return 1; |
6105 | } | |
6106 | ||
af7cc7d1 XG |
6107 | *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
6108 | ||
6109 | if (*gpa == UNMAPPED_GVA) | |
6110 | return -1; | |
6111 | ||
0f89b207 | 6112 | return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); |
af7cc7d1 XG |
6113 | } |
6114 | ||
3200f405 | 6115 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
bcc55cba | 6116 | const void *val, int bytes) |
bbd9b64e CO |
6117 | { |
6118 | int ret; | |
6119 | ||
54bf36aa | 6120 | ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); |
9f811285 | 6121 | if (ret < 0) |
bbd9b64e | 6122 | return 0; |
0eb05bf2 | 6123 | kvm_page_track_write(vcpu, gpa, val, bytes); |
bbd9b64e CO |
6124 | return 1; |
6125 | } | |
6126 | ||
77d197b2 XG |
6127 | struct read_write_emulator_ops { |
6128 | int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, | |
6129 | int bytes); | |
6130 | int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6131 | void *val, int bytes); | |
6132 | int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6133 | int bytes, void *val); | |
6134 | int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6135 | void *val, int bytes); | |
6136 | bool write; | |
6137 | }; | |
6138 | ||
6139 | static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) | |
6140 | { | |
6141 | if (vcpu->mmio_read_completed) { | |
77d197b2 | 6142 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
e39d200f | 6143 | vcpu->mmio_fragments[0].gpa, val); |
77d197b2 XG |
6144 | vcpu->mmio_read_completed = 0; |
6145 | return 1; | |
6146 | } | |
6147 | ||
6148 | return 0; | |
6149 | } | |
6150 | ||
6151 | static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6152 | void *val, int bytes) | |
6153 | { | |
54bf36aa | 6154 | return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); |
77d197b2 XG |
6155 | } |
6156 | ||
6157 | static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6158 | void *val, int bytes) | |
6159 | { | |
6160 | return emulator_write_phys(vcpu, gpa, val, bytes); | |
6161 | } | |
6162 | ||
6163 | static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) | |
6164 | { | |
e39d200f | 6165 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); |
77d197b2 XG |
6166 | return vcpu_mmio_write(vcpu, gpa, bytes, val); |
6167 | } | |
6168 | ||
6169 | static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6170 | void *val, int bytes) | |
6171 | { | |
e39d200f | 6172 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); |
77d197b2 XG |
6173 | return X86EMUL_IO_NEEDED; |
6174 | } | |
6175 | ||
6176 | static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6177 | void *val, int bytes) | |
6178 | { | |
f78146b0 AK |
6179 | struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; |
6180 | ||
87da7e66 | 6181 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); |
77d197b2 XG |
6182 | return X86EMUL_CONTINUE; |
6183 | } | |
6184 | ||
0fbe9b0b | 6185 | static const struct read_write_emulator_ops read_emultor = { |
77d197b2 XG |
6186 | .read_write_prepare = read_prepare, |
6187 | .read_write_emulate = read_emulate, | |
6188 | .read_write_mmio = vcpu_mmio_read, | |
6189 | .read_write_exit_mmio = read_exit_mmio, | |
6190 | }; | |
6191 | ||
0fbe9b0b | 6192 | static const struct read_write_emulator_ops write_emultor = { |
77d197b2 XG |
6193 | .read_write_emulate = write_emulate, |
6194 | .read_write_mmio = write_mmio, | |
6195 | .read_write_exit_mmio = write_exit_mmio, | |
6196 | .write = true, | |
6197 | }; | |
6198 | ||
22388a3c XG |
6199 | static int emulator_read_write_onepage(unsigned long addr, void *val, |
6200 | unsigned int bytes, | |
6201 | struct x86_exception *exception, | |
6202 | struct kvm_vcpu *vcpu, | |
0fbe9b0b | 6203 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 6204 | { |
af7cc7d1 XG |
6205 | gpa_t gpa; |
6206 | int handled, ret; | |
22388a3c | 6207 | bool write = ops->write; |
f78146b0 | 6208 | struct kvm_mmio_fragment *frag; |
c9b8b07c | 6209 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
0f89b207 TL |
6210 | |
6211 | /* | |
6212 | * If the exit was due to a NPF we may already have a GPA. | |
6213 | * If the GPA is present, use it to avoid the GVA to GPA table walk. | |
6214 | * Note, this cannot be used on string operations since string | |
6215 | * operation using rep will only have the initial GPA from the NPF | |
6216 | * occurred. | |
6217 | */ | |
744e699c SC |
6218 | if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) && |
6219 | (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) { | |
6220 | gpa = ctxt->gpa_val; | |
618232e2 BS |
6221 | ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); |
6222 | } else { | |
6223 | ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); | |
6224 | if (ret < 0) | |
6225 | return X86EMUL_PROPAGATE_FAULT; | |
0f89b207 | 6226 | } |
10589a46 | 6227 | |
618232e2 | 6228 | if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) |
bbd9b64e CO |
6229 | return X86EMUL_CONTINUE; |
6230 | ||
bbd9b64e CO |
6231 | /* |
6232 | * Is this MMIO handled locally? | |
6233 | */ | |
22388a3c | 6234 | handled = ops->read_write_mmio(vcpu, gpa, bytes, val); |
70252a10 | 6235 | if (handled == bytes) |
bbd9b64e | 6236 | return X86EMUL_CONTINUE; |
bbd9b64e | 6237 | |
70252a10 AK |
6238 | gpa += handled; |
6239 | bytes -= handled; | |
6240 | val += handled; | |
6241 | ||
87da7e66 XG |
6242 | WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); |
6243 | frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; | |
6244 | frag->gpa = gpa; | |
6245 | frag->data = val; | |
6246 | frag->len = bytes; | |
f78146b0 | 6247 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
6248 | } |
6249 | ||
52eb5a6d XL |
6250 | static int emulator_read_write(struct x86_emulate_ctxt *ctxt, |
6251 | unsigned long addr, | |
22388a3c XG |
6252 | void *val, unsigned int bytes, |
6253 | struct x86_exception *exception, | |
0fbe9b0b | 6254 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 6255 | { |
0f65dd70 | 6256 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
f78146b0 AK |
6257 | gpa_t gpa; |
6258 | int rc; | |
6259 | ||
6260 | if (ops->read_write_prepare && | |
6261 | ops->read_write_prepare(vcpu, val, bytes)) | |
6262 | return X86EMUL_CONTINUE; | |
6263 | ||
6264 | vcpu->mmio_nr_fragments = 0; | |
0f65dd70 | 6265 | |
bbd9b64e CO |
6266 | /* Crossing a page boundary? */ |
6267 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
f78146b0 | 6268 | int now; |
bbd9b64e CO |
6269 | |
6270 | now = -addr & ~PAGE_MASK; | |
22388a3c XG |
6271 | rc = emulator_read_write_onepage(addr, val, now, exception, |
6272 | vcpu, ops); | |
6273 | ||
bbd9b64e CO |
6274 | if (rc != X86EMUL_CONTINUE) |
6275 | return rc; | |
6276 | addr += now; | |
bac15531 NA |
6277 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
6278 | addr = (u32)addr; | |
bbd9b64e CO |
6279 | val += now; |
6280 | bytes -= now; | |
6281 | } | |
22388a3c | 6282 | |
f78146b0 AK |
6283 | rc = emulator_read_write_onepage(addr, val, bytes, exception, |
6284 | vcpu, ops); | |
6285 | if (rc != X86EMUL_CONTINUE) | |
6286 | return rc; | |
6287 | ||
6288 | if (!vcpu->mmio_nr_fragments) | |
6289 | return rc; | |
6290 | ||
6291 | gpa = vcpu->mmio_fragments[0].gpa; | |
6292 | ||
6293 | vcpu->mmio_needed = 1; | |
6294 | vcpu->mmio_cur_fragment = 0; | |
6295 | ||
87da7e66 | 6296 | vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); |
f78146b0 AK |
6297 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; |
6298 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
6299 | vcpu->run->mmio.phys_addr = gpa; | |
6300 | ||
6301 | return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); | |
22388a3c XG |
6302 | } |
6303 | ||
6304 | static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, | |
6305 | unsigned long addr, | |
6306 | void *val, | |
6307 | unsigned int bytes, | |
6308 | struct x86_exception *exception) | |
6309 | { | |
6310 | return emulator_read_write(ctxt, addr, val, bytes, | |
6311 | exception, &read_emultor); | |
6312 | } | |
6313 | ||
52eb5a6d | 6314 | static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, |
22388a3c XG |
6315 | unsigned long addr, |
6316 | const void *val, | |
6317 | unsigned int bytes, | |
6318 | struct x86_exception *exception) | |
6319 | { | |
6320 | return emulator_read_write(ctxt, addr, (void *)val, bytes, | |
6321 | exception, &write_emultor); | |
bbd9b64e | 6322 | } |
bbd9b64e | 6323 | |
daea3e73 AK |
6324 | #define CMPXCHG_TYPE(t, ptr, old, new) \ |
6325 | (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) | |
6326 | ||
6327 | #ifdef CONFIG_X86_64 | |
6328 | # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) | |
6329 | #else | |
6330 | # define CMPXCHG64(ptr, old, new) \ | |
9749a6c0 | 6331 | (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) |
daea3e73 AK |
6332 | #endif |
6333 | ||
0f65dd70 AK |
6334 | static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, |
6335 | unsigned long addr, | |
bbd9b64e CO |
6336 | const void *old, |
6337 | const void *new, | |
6338 | unsigned int bytes, | |
0f65dd70 | 6339 | struct x86_exception *exception) |
bbd9b64e | 6340 | { |
42e35f80 | 6341 | struct kvm_host_map map; |
0f65dd70 | 6342 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
9de6fe3c | 6343 | u64 page_line_mask; |
daea3e73 | 6344 | gpa_t gpa; |
daea3e73 AK |
6345 | char *kaddr; |
6346 | bool exchanged; | |
2bacc55c | 6347 | |
daea3e73 AK |
6348 | /* guests cmpxchg8b have to be emulated atomically */ |
6349 | if (bytes > 8 || (bytes & (bytes - 1))) | |
6350 | goto emul_write; | |
10589a46 | 6351 | |
daea3e73 | 6352 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); |
2bacc55c | 6353 | |
daea3e73 AK |
6354 | if (gpa == UNMAPPED_GVA || |
6355 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
6356 | goto emul_write; | |
2bacc55c | 6357 | |
9de6fe3c XL |
6358 | /* |
6359 | * Emulate the atomic as a straight write to avoid #AC if SLD is | |
6360 | * enabled in the host and the access splits a cache line. | |
6361 | */ | |
6362 | if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) | |
6363 | page_line_mask = ~(cache_line_size() - 1); | |
6364 | else | |
6365 | page_line_mask = PAGE_MASK; | |
6366 | ||
6367 | if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask)) | |
daea3e73 | 6368 | goto emul_write; |
72dc67a6 | 6369 | |
42e35f80 | 6370 | if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map)) |
c19b8bd6 | 6371 | goto emul_write; |
72dc67a6 | 6372 | |
42e35f80 KA |
6373 | kaddr = map.hva + offset_in_page(gpa); |
6374 | ||
daea3e73 AK |
6375 | switch (bytes) { |
6376 | case 1: | |
6377 | exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); | |
6378 | break; | |
6379 | case 2: | |
6380 | exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); | |
6381 | break; | |
6382 | case 4: | |
6383 | exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); | |
6384 | break; | |
6385 | case 8: | |
6386 | exchanged = CMPXCHG64(kaddr, old, new); | |
6387 | break; | |
6388 | default: | |
6389 | BUG(); | |
2bacc55c | 6390 | } |
42e35f80 KA |
6391 | |
6392 | kvm_vcpu_unmap(vcpu, &map, true); | |
daea3e73 AK |
6393 | |
6394 | if (!exchanged) | |
6395 | return X86EMUL_CMPXCHG_FAILED; | |
6396 | ||
0eb05bf2 | 6397 | kvm_page_track_write(vcpu, gpa, new, bytes); |
8f6abd06 GN |
6398 | |
6399 | return X86EMUL_CONTINUE; | |
4a5f48f6 | 6400 | |
3200f405 | 6401 | emul_write: |
daea3e73 | 6402 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); |
2bacc55c | 6403 | |
0f65dd70 | 6404 | return emulator_write_emulated(ctxt, addr, new, bytes, exception); |
bbd9b64e CO |
6405 | } |
6406 | ||
cf8f70bf GN |
6407 | static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) |
6408 | { | |
cbfc6c91 | 6409 | int r = 0, i; |
cf8f70bf | 6410 | |
cbfc6c91 WL |
6411 | for (i = 0; i < vcpu->arch.pio.count; i++) { |
6412 | if (vcpu->arch.pio.in) | |
6413 | r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, | |
6414 | vcpu->arch.pio.size, pd); | |
6415 | else | |
6416 | r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, | |
6417 | vcpu->arch.pio.port, vcpu->arch.pio.size, | |
6418 | pd); | |
6419 | if (r) | |
6420 | break; | |
6421 | pd += vcpu->arch.pio.size; | |
6422 | } | |
cf8f70bf GN |
6423 | return r; |
6424 | } | |
6425 | ||
6f6fbe98 XG |
6426 | static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, |
6427 | unsigned short port, void *val, | |
6428 | unsigned int count, bool in) | |
cf8f70bf | 6429 | { |
cf8f70bf | 6430 | vcpu->arch.pio.port = port; |
6f6fbe98 | 6431 | vcpu->arch.pio.in = in; |
7972995b | 6432 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
6433 | vcpu->arch.pio.size = size; |
6434 | ||
6435 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
7972995b | 6436 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
6437 | return 1; |
6438 | } | |
6439 | ||
6440 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
6f6fbe98 | 6441 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; |
cf8f70bf GN |
6442 | vcpu->run->io.size = size; |
6443 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
6444 | vcpu->run->io.count = count; | |
6445 | vcpu->run->io.port = port; | |
6446 | ||
6447 | return 0; | |
6448 | } | |
6449 | ||
2e3bb4d8 SC |
6450 | static int emulator_pio_in(struct kvm_vcpu *vcpu, int size, |
6451 | unsigned short port, void *val, unsigned int count) | |
cf8f70bf | 6452 | { |
6f6fbe98 | 6453 | int ret; |
ca1d4a9e | 6454 | |
6f6fbe98 XG |
6455 | if (vcpu->arch.pio.count) |
6456 | goto data_avail; | |
cf8f70bf | 6457 | |
cbfc6c91 WL |
6458 | memset(vcpu->arch.pio_data, 0, size * count); |
6459 | ||
6f6fbe98 XG |
6460 | ret = emulator_pio_in_out(vcpu, size, port, val, count, true); |
6461 | if (ret) { | |
6462 | data_avail: | |
6463 | memcpy(val, vcpu->arch.pio_data, size * count); | |
1171903d | 6464 | trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); |
7972995b | 6465 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
6466 | return 1; |
6467 | } | |
6468 | ||
cf8f70bf GN |
6469 | return 0; |
6470 | } | |
6471 | ||
2e3bb4d8 SC |
6472 | static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
6473 | int size, unsigned short port, void *val, | |
6474 | unsigned int count) | |
6f6fbe98 | 6475 | { |
2e3bb4d8 | 6476 | return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count); |
6f6fbe98 | 6477 | |
2e3bb4d8 | 6478 | } |
6f6fbe98 | 6479 | |
2e3bb4d8 SC |
6480 | static int emulator_pio_out(struct kvm_vcpu *vcpu, int size, |
6481 | unsigned short port, const void *val, | |
6482 | unsigned int count) | |
6483 | { | |
6f6fbe98 | 6484 | memcpy(vcpu->arch.pio_data, val, size * count); |
1171903d | 6485 | trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); |
6f6fbe98 XG |
6486 | return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); |
6487 | } | |
6488 | ||
2e3bb4d8 SC |
6489 | static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, |
6490 | int size, unsigned short port, | |
6491 | const void *val, unsigned int count) | |
6492 | { | |
6493 | return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count); | |
6494 | } | |
6495 | ||
bbd9b64e CO |
6496 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) |
6497 | { | |
afaf0b2f | 6498 | return kvm_x86_ops.get_segment_base(vcpu, seg); |
bbd9b64e CO |
6499 | } |
6500 | ||
3cb16fe7 | 6501 | static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) |
bbd9b64e | 6502 | { |
3cb16fe7 | 6503 | kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); |
bbd9b64e CO |
6504 | } |
6505 | ||
ae6a2375 | 6506 | static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) |
f5f48ee1 SY |
6507 | { |
6508 | if (!need_emulate_wbinvd(vcpu)) | |
6509 | return X86EMUL_CONTINUE; | |
6510 | ||
afaf0b2f | 6511 | if (kvm_x86_ops.has_wbinvd_exit()) { |
2eec7343 JK |
6512 | int cpu = get_cpu(); |
6513 | ||
6514 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
f5f48ee1 SY |
6515 | smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, |
6516 | wbinvd_ipi, NULL, 1); | |
2eec7343 | 6517 | put_cpu(); |
f5f48ee1 | 6518 | cpumask_clear(vcpu->arch.wbinvd_dirty_mask); |
2eec7343 JK |
6519 | } else |
6520 | wbinvd(); | |
f5f48ee1 SY |
6521 | return X86EMUL_CONTINUE; |
6522 | } | |
5cb56059 JS |
6523 | |
6524 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
6525 | { | |
6affcbed KH |
6526 | kvm_emulate_wbinvd_noskip(vcpu); |
6527 | return kvm_skip_emulated_instruction(vcpu); | |
5cb56059 | 6528 | } |
f5f48ee1 SY |
6529 | EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); |
6530 | ||
5cb56059 JS |
6531 | |
6532 | ||
bcaf5cc5 AK |
6533 | static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) |
6534 | { | |
5cb56059 | 6535 | kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); |
bcaf5cc5 AK |
6536 | } |
6537 | ||
52eb5a6d XL |
6538 | static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, |
6539 | unsigned long *dest) | |
bbd9b64e | 6540 | { |
16f8a6f9 | 6541 | return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); |
bbd9b64e CO |
6542 | } |
6543 | ||
52eb5a6d XL |
6544 | static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, |
6545 | unsigned long value) | |
bbd9b64e | 6546 | { |
338dbc97 | 6547 | |
717746e3 | 6548 | return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); |
bbd9b64e CO |
6549 | } |
6550 | ||
52a46617 | 6551 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) |
5fdbf976 | 6552 | { |
52a46617 | 6553 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; |
5fdbf976 MT |
6554 | } |
6555 | ||
717746e3 | 6556 | static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) |
bbd9b64e | 6557 | { |
717746e3 | 6558 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
52a46617 GN |
6559 | unsigned long value; |
6560 | ||
6561 | switch (cr) { | |
6562 | case 0: | |
6563 | value = kvm_read_cr0(vcpu); | |
6564 | break; | |
6565 | case 2: | |
6566 | value = vcpu->arch.cr2; | |
6567 | break; | |
6568 | case 3: | |
9f8fe504 | 6569 | value = kvm_read_cr3(vcpu); |
52a46617 GN |
6570 | break; |
6571 | case 4: | |
6572 | value = kvm_read_cr4(vcpu); | |
6573 | break; | |
6574 | case 8: | |
6575 | value = kvm_get_cr8(vcpu); | |
6576 | break; | |
6577 | default: | |
a737f256 | 6578 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
52a46617 GN |
6579 | return 0; |
6580 | } | |
6581 | ||
6582 | return value; | |
6583 | } | |
6584 | ||
717746e3 | 6585 | static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) |
52a46617 | 6586 | { |
717746e3 | 6587 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
0f12244f GN |
6588 | int res = 0; |
6589 | ||
52a46617 GN |
6590 | switch (cr) { |
6591 | case 0: | |
49a9b07e | 6592 | res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
52a46617 GN |
6593 | break; |
6594 | case 2: | |
6595 | vcpu->arch.cr2 = val; | |
6596 | break; | |
6597 | case 3: | |
2390218b | 6598 | res = kvm_set_cr3(vcpu, val); |
52a46617 GN |
6599 | break; |
6600 | case 4: | |
a83b29c6 | 6601 | res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
52a46617 GN |
6602 | break; |
6603 | case 8: | |
eea1cff9 | 6604 | res = kvm_set_cr8(vcpu, val); |
52a46617 GN |
6605 | break; |
6606 | default: | |
a737f256 | 6607 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
0f12244f | 6608 | res = -1; |
52a46617 | 6609 | } |
0f12244f GN |
6610 | |
6611 | return res; | |
52a46617 GN |
6612 | } |
6613 | ||
717746e3 | 6614 | static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) |
9c537244 | 6615 | { |
afaf0b2f | 6616 | return kvm_x86_ops.get_cpl(emul_to_vcpu(ctxt)); |
9c537244 GN |
6617 | } |
6618 | ||
4bff1e86 | 6619 | static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
2dafc6c2 | 6620 | { |
afaf0b2f | 6621 | kvm_x86_ops.get_gdt(emul_to_vcpu(ctxt), dt); |
2dafc6c2 GN |
6622 | } |
6623 | ||
4bff1e86 | 6624 | static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
160ce1f1 | 6625 | { |
afaf0b2f | 6626 | kvm_x86_ops.get_idt(emul_to_vcpu(ctxt), dt); |
160ce1f1 MG |
6627 | } |
6628 | ||
1ac9d0cf AK |
6629 | static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
6630 | { | |
afaf0b2f | 6631 | kvm_x86_ops.set_gdt(emul_to_vcpu(ctxt), dt); |
1ac9d0cf AK |
6632 | } |
6633 | ||
6634 | static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) | |
6635 | { | |
afaf0b2f | 6636 | kvm_x86_ops.set_idt(emul_to_vcpu(ctxt), dt); |
1ac9d0cf AK |
6637 | } |
6638 | ||
4bff1e86 AK |
6639 | static unsigned long emulator_get_cached_segment_base( |
6640 | struct x86_emulate_ctxt *ctxt, int seg) | |
5951c442 | 6641 | { |
4bff1e86 | 6642 | return get_segment_base(emul_to_vcpu(ctxt), seg); |
5951c442 GN |
6643 | } |
6644 | ||
1aa36616 AK |
6645 | static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, |
6646 | struct desc_struct *desc, u32 *base3, | |
6647 | int seg) | |
2dafc6c2 GN |
6648 | { |
6649 | struct kvm_segment var; | |
6650 | ||
4bff1e86 | 6651 | kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); |
1aa36616 | 6652 | *selector = var.selector; |
2dafc6c2 | 6653 | |
378a8b09 GN |
6654 | if (var.unusable) { |
6655 | memset(desc, 0, sizeof(*desc)); | |
f0367ee1 RK |
6656 | if (base3) |
6657 | *base3 = 0; | |
2dafc6c2 | 6658 | return false; |
378a8b09 | 6659 | } |
2dafc6c2 GN |
6660 | |
6661 | if (var.g) | |
6662 | var.limit >>= 12; | |
6663 | set_desc_limit(desc, var.limit); | |
6664 | set_desc_base(desc, (unsigned long)var.base); | |
5601d05b GN |
6665 | #ifdef CONFIG_X86_64 |
6666 | if (base3) | |
6667 | *base3 = var.base >> 32; | |
6668 | #endif | |
2dafc6c2 GN |
6669 | desc->type = var.type; |
6670 | desc->s = var.s; | |
6671 | desc->dpl = var.dpl; | |
6672 | desc->p = var.present; | |
6673 | desc->avl = var.avl; | |
6674 | desc->l = var.l; | |
6675 | desc->d = var.db; | |
6676 | desc->g = var.g; | |
6677 | ||
6678 | return true; | |
6679 | } | |
6680 | ||
1aa36616 AK |
6681 | static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, |
6682 | struct desc_struct *desc, u32 base3, | |
6683 | int seg) | |
2dafc6c2 | 6684 | { |
4bff1e86 | 6685 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
2dafc6c2 GN |
6686 | struct kvm_segment var; |
6687 | ||
1aa36616 | 6688 | var.selector = selector; |
2dafc6c2 | 6689 | var.base = get_desc_base(desc); |
5601d05b GN |
6690 | #ifdef CONFIG_X86_64 |
6691 | var.base |= ((u64)base3) << 32; | |
6692 | #endif | |
2dafc6c2 GN |
6693 | var.limit = get_desc_limit(desc); |
6694 | if (desc->g) | |
6695 | var.limit = (var.limit << 12) | 0xfff; | |
6696 | var.type = desc->type; | |
2dafc6c2 GN |
6697 | var.dpl = desc->dpl; |
6698 | var.db = desc->d; | |
6699 | var.s = desc->s; | |
6700 | var.l = desc->l; | |
6701 | var.g = desc->g; | |
6702 | var.avl = desc->avl; | |
6703 | var.present = desc->p; | |
6704 | var.unusable = !var.present; | |
6705 | var.padding = 0; | |
6706 | ||
6707 | kvm_set_segment(vcpu, &var, seg); | |
6708 | return; | |
6709 | } | |
6710 | ||
717746e3 AK |
6711 | static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, |
6712 | u32 msr_index, u64 *pdata) | |
6713 | { | |
1ae09954 AG |
6714 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
6715 | int r; | |
6716 | ||
6717 | r = kvm_get_msr(vcpu, msr_index, pdata); | |
6718 | ||
6719 | if (r && kvm_get_msr_user_space(vcpu, msr_index, r)) { | |
6720 | /* Bounce to user space */ | |
6721 | return X86EMUL_IO_NEEDED; | |
6722 | } | |
6723 | ||
6724 | return r; | |
717746e3 AK |
6725 | } |
6726 | ||
6727 | static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, | |
6728 | u32 msr_index, u64 data) | |
6729 | { | |
1ae09954 AG |
6730 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
6731 | int r; | |
6732 | ||
6733 | r = kvm_set_msr(vcpu, msr_index, data); | |
6734 | ||
6735 | if (r && kvm_set_msr_user_space(vcpu, msr_index, data, r)) { | |
6736 | /* Bounce to user space */ | |
6737 | return X86EMUL_IO_NEEDED; | |
6738 | } | |
6739 | ||
6740 | return r; | |
717746e3 AK |
6741 | } |
6742 | ||
64d60670 PB |
6743 | static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) |
6744 | { | |
6745 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
6746 | ||
6747 | return vcpu->arch.smbase; | |
6748 | } | |
6749 | ||
6750 | static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) | |
6751 | { | |
6752 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
6753 | ||
6754 | vcpu->arch.smbase = smbase; | |
6755 | } | |
6756 | ||
67f4d428 NA |
6757 | static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, |
6758 | u32 pmc) | |
6759 | { | |
98ff80f5 | 6760 | return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc); |
67f4d428 NA |
6761 | } |
6762 | ||
222d21aa AK |
6763 | static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, |
6764 | u32 pmc, u64 *pdata) | |
6765 | { | |
c6702c9d | 6766 | return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); |
222d21aa AK |
6767 | } |
6768 | ||
6c3287f7 AK |
6769 | static void emulator_halt(struct x86_emulate_ctxt *ctxt) |
6770 | { | |
6771 | emul_to_vcpu(ctxt)->arch.halt_request = 1; | |
6772 | } | |
6773 | ||
2953538e | 6774 | static int emulator_intercept(struct x86_emulate_ctxt *ctxt, |
8a76d7f2 | 6775 | struct x86_instruction_info *info, |
c4f035c6 AK |
6776 | enum x86_intercept_stage stage) |
6777 | { | |
afaf0b2f | 6778 | return kvm_x86_ops.check_intercept(emul_to_vcpu(ctxt), info, stage, |
21f1b8f2 | 6779 | &ctxt->exception); |
c4f035c6 AK |
6780 | } |
6781 | ||
e911eb3b | 6782 | static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, |
f91af517 SC |
6783 | u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, |
6784 | bool exact_only) | |
bdb42f5a | 6785 | { |
f91af517 | 6786 | return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only); |
bdb42f5a SB |
6787 | } |
6788 | ||
5ae78e95 SC |
6789 | static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt) |
6790 | { | |
6791 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM); | |
6792 | } | |
6793 | ||
6794 | static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt) | |
6795 | { | |
6796 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE); | |
6797 | } | |
6798 | ||
6799 | static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt) | |
6800 | { | |
6801 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR); | |
6802 | } | |
6803 | ||
dd856efa AK |
6804 | static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) |
6805 | { | |
6806 | return kvm_register_read(emul_to_vcpu(ctxt), reg); | |
6807 | } | |
6808 | ||
6809 | static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) | |
6810 | { | |
6811 | kvm_register_write(emul_to_vcpu(ctxt), reg, val); | |
6812 | } | |
6813 | ||
801806d9 NA |
6814 | static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) |
6815 | { | |
afaf0b2f | 6816 | kvm_x86_ops.set_nmi_mask(emul_to_vcpu(ctxt), masked); |
801806d9 NA |
6817 | } |
6818 | ||
6ed071f0 LP |
6819 | static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) |
6820 | { | |
6821 | return emul_to_vcpu(ctxt)->arch.hflags; | |
6822 | } | |
6823 | ||
6824 | static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags) | |
6825 | { | |
c5833c7a | 6826 | emul_to_vcpu(ctxt)->arch.hflags = emul_flags; |
6ed071f0 LP |
6827 | } |
6828 | ||
ed19321f SC |
6829 | static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, |
6830 | const char *smstate) | |
0234bf88 | 6831 | { |
afaf0b2f | 6832 | return kvm_x86_ops.pre_leave_smm(emul_to_vcpu(ctxt), smstate); |
0234bf88 LP |
6833 | } |
6834 | ||
c5833c7a SC |
6835 | static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt) |
6836 | { | |
6837 | kvm_smm_changed(emul_to_vcpu(ctxt)); | |
6838 | } | |
6839 | ||
02d4160f VK |
6840 | static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) |
6841 | { | |
6842 | return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); | |
6843 | } | |
6844 | ||
0225fb50 | 6845 | static const struct x86_emulate_ops emulate_ops = { |
dd856efa AK |
6846 | .read_gpr = emulator_read_gpr, |
6847 | .write_gpr = emulator_write_gpr, | |
ce14e868 PB |
6848 | .read_std = emulator_read_std, |
6849 | .write_std = emulator_write_std, | |
7a036a6f | 6850 | .read_phys = kvm_read_guest_phys_system, |
1871c602 | 6851 | .fetch = kvm_fetch_guest_virt, |
bbd9b64e CO |
6852 | .read_emulated = emulator_read_emulated, |
6853 | .write_emulated = emulator_write_emulated, | |
6854 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
3cb16fe7 | 6855 | .invlpg = emulator_invlpg, |
cf8f70bf GN |
6856 | .pio_in_emulated = emulator_pio_in_emulated, |
6857 | .pio_out_emulated = emulator_pio_out_emulated, | |
1aa36616 AK |
6858 | .get_segment = emulator_get_segment, |
6859 | .set_segment = emulator_set_segment, | |
5951c442 | 6860 | .get_cached_segment_base = emulator_get_cached_segment_base, |
2dafc6c2 | 6861 | .get_gdt = emulator_get_gdt, |
160ce1f1 | 6862 | .get_idt = emulator_get_idt, |
1ac9d0cf AK |
6863 | .set_gdt = emulator_set_gdt, |
6864 | .set_idt = emulator_set_idt, | |
52a46617 GN |
6865 | .get_cr = emulator_get_cr, |
6866 | .set_cr = emulator_set_cr, | |
9c537244 | 6867 | .cpl = emulator_get_cpl, |
35aa5375 GN |
6868 | .get_dr = emulator_get_dr, |
6869 | .set_dr = emulator_set_dr, | |
64d60670 PB |
6870 | .get_smbase = emulator_get_smbase, |
6871 | .set_smbase = emulator_set_smbase, | |
717746e3 AK |
6872 | .set_msr = emulator_set_msr, |
6873 | .get_msr = emulator_get_msr, | |
67f4d428 | 6874 | .check_pmc = emulator_check_pmc, |
222d21aa | 6875 | .read_pmc = emulator_read_pmc, |
6c3287f7 | 6876 | .halt = emulator_halt, |
bcaf5cc5 | 6877 | .wbinvd = emulator_wbinvd, |
d6aa1000 | 6878 | .fix_hypercall = emulator_fix_hypercall, |
c4f035c6 | 6879 | .intercept = emulator_intercept, |
bdb42f5a | 6880 | .get_cpuid = emulator_get_cpuid, |
5ae78e95 SC |
6881 | .guest_has_long_mode = emulator_guest_has_long_mode, |
6882 | .guest_has_movbe = emulator_guest_has_movbe, | |
6883 | .guest_has_fxsr = emulator_guest_has_fxsr, | |
801806d9 | 6884 | .set_nmi_mask = emulator_set_nmi_mask, |
6ed071f0 LP |
6885 | .get_hflags = emulator_get_hflags, |
6886 | .set_hflags = emulator_set_hflags, | |
0234bf88 | 6887 | .pre_leave_smm = emulator_pre_leave_smm, |
c5833c7a | 6888 | .post_leave_smm = emulator_post_leave_smm, |
02d4160f | 6889 | .set_xcr = emulator_set_xcr, |
bbd9b64e CO |
6890 | }; |
6891 | ||
95cb2295 GN |
6892 | static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) |
6893 | { | |
afaf0b2f | 6894 | u32 int_shadow = kvm_x86_ops.get_interrupt_shadow(vcpu); |
95cb2295 GN |
6895 | /* |
6896 | * an sti; sti; sequence only disable interrupts for the first | |
6897 | * instruction. So, if the last instruction, be it emulated or | |
6898 | * not, left the system with the INT_STI flag enabled, it | |
6899 | * means that the last instruction is an sti. We should not | |
6900 | * leave the flag on in this case. The same goes for mov ss | |
6901 | */ | |
37ccdcbe PB |
6902 | if (int_shadow & mask) |
6903 | mask = 0; | |
6addfc42 | 6904 | if (unlikely(int_shadow || mask)) { |
afaf0b2f | 6905 | kvm_x86_ops.set_interrupt_shadow(vcpu, mask); |
6addfc42 PB |
6906 | if (!mask) |
6907 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
6908 | } | |
95cb2295 GN |
6909 | } |
6910 | ||
ef54bcfe | 6911 | static bool inject_emulated_exception(struct kvm_vcpu *vcpu) |
54b8486f | 6912 | { |
c9b8b07c | 6913 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
da9cb575 | 6914 | if (ctxt->exception.vector == PF_VECTOR) |
53b3d8e9 | 6915 | return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception); |
ef54bcfe PB |
6916 | |
6917 | if (ctxt->exception.error_code_valid) | |
da9cb575 AK |
6918 | kvm_queue_exception_e(vcpu, ctxt->exception.vector, |
6919 | ctxt->exception.error_code); | |
54b8486f | 6920 | else |
da9cb575 | 6921 | kvm_queue_exception(vcpu, ctxt->exception.vector); |
ef54bcfe | 6922 | return false; |
54b8486f GN |
6923 | } |
6924 | ||
c9b8b07c SC |
6925 | static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu) |
6926 | { | |
6927 | struct x86_emulate_ctxt *ctxt; | |
6928 | ||
6929 | ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT); | |
6930 | if (!ctxt) { | |
6931 | pr_err("kvm: failed to allocate vcpu's emulator\n"); | |
6932 | return NULL; | |
6933 | } | |
6934 | ||
6935 | ctxt->vcpu = vcpu; | |
6936 | ctxt->ops = &emulate_ops; | |
6937 | vcpu->arch.emulate_ctxt = ctxt; | |
6938 | ||
6939 | return ctxt; | |
6940 | } | |
6941 | ||
8ec4722d MG |
6942 | static void init_emulate_ctxt(struct kvm_vcpu *vcpu) |
6943 | { | |
c9b8b07c | 6944 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
8ec4722d MG |
6945 | int cs_db, cs_l; |
6946 | ||
afaf0b2f | 6947 | kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
8ec4722d | 6948 | |
744e699c | 6949 | ctxt->gpa_available = false; |
adf52235 | 6950 | ctxt->eflags = kvm_get_rflags(vcpu); |
c8401dda PB |
6951 | ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; |
6952 | ||
adf52235 TY |
6953 | ctxt->eip = kvm_rip_read(vcpu); |
6954 | ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : | |
6955 | (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : | |
42bf549f | 6956 | (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : |
adf52235 TY |
6957 | cs_db ? X86EMUL_MODE_PROT32 : |
6958 | X86EMUL_MODE_PROT16; | |
a584539b | 6959 | BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); |
64d60670 PB |
6960 | BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); |
6961 | BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); | |
adf52235 | 6962 | |
dd856efa | 6963 | init_decode_cache(ctxt); |
7ae441ea | 6964 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; |
8ec4722d MG |
6965 | } |
6966 | ||
9497e1f2 | 6967 | void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) |
63995653 | 6968 | { |
c9b8b07c | 6969 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
63995653 MG |
6970 | int ret; |
6971 | ||
6972 | init_emulate_ctxt(vcpu); | |
6973 | ||
9dac77fa AK |
6974 | ctxt->op_bytes = 2; |
6975 | ctxt->ad_bytes = 2; | |
6976 | ctxt->_eip = ctxt->eip + inc_eip; | |
9d74191a | 6977 | ret = emulate_int_real(ctxt, irq); |
63995653 | 6978 | |
9497e1f2 SC |
6979 | if (ret != X86EMUL_CONTINUE) { |
6980 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
6981 | } else { | |
6982 | ctxt->eip = ctxt->_eip; | |
6983 | kvm_rip_write(vcpu, ctxt->eip); | |
6984 | kvm_set_rflags(vcpu, ctxt->eflags); | |
6985 | } | |
63995653 MG |
6986 | } |
6987 | EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); | |
6988 | ||
e2366171 | 6989 | static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) |
6d77dbfc | 6990 | { |
6d77dbfc GN |
6991 | ++vcpu->stat.insn_emulation_fail; |
6992 | trace_kvm_emulate_insn_failed(vcpu); | |
e2366171 | 6993 | |
42cbf068 SC |
6994 | if (emulation_type & EMULTYPE_VMWARE_GP) { |
6995 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
60fc3d02 | 6996 | return 1; |
42cbf068 | 6997 | } |
e2366171 | 6998 | |
738fece4 SC |
6999 | if (emulation_type & EMULTYPE_SKIP) { |
7000 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
7001 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
7002 | vcpu->run->internal.ndata = 0; | |
60fc3d02 | 7003 | return 0; |
738fece4 SC |
7004 | } |
7005 | ||
22da61c9 SC |
7006 | kvm_queue_exception(vcpu, UD_VECTOR); |
7007 | ||
afaf0b2f | 7008 | if (!is_guest_mode(vcpu) && kvm_x86_ops.get_cpl(vcpu) == 0) { |
fc3a9157 JR |
7009 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
7010 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
7011 | vcpu->run->internal.ndata = 0; | |
60fc3d02 | 7012 | return 0; |
fc3a9157 | 7013 | } |
e2366171 | 7014 | |
60fc3d02 | 7015 | return 1; |
6d77dbfc GN |
7016 | } |
7017 | ||
736c291c | 7018 | static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
991eebf9 GN |
7019 | bool write_fault_to_shadow_pgtable, |
7020 | int emulation_type) | |
a6f177ef | 7021 | { |
736c291c | 7022 | gpa_t gpa = cr2_or_gpa; |
ba049e93 | 7023 | kvm_pfn_t pfn; |
a6f177ef | 7024 | |
92daa48b | 7025 | if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) |
991eebf9 GN |
7026 | return false; |
7027 | ||
92daa48b SC |
7028 | if (WARN_ON_ONCE(is_guest_mode(vcpu)) || |
7029 | WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) | |
6c3dfeb6 SC |
7030 | return false; |
7031 | ||
44dd3ffa | 7032 | if (!vcpu->arch.mmu->direct_map) { |
95b3cf69 XG |
7033 | /* |
7034 | * Write permission should be allowed since only | |
7035 | * write access need to be emulated. | |
7036 | */ | |
736c291c | 7037 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); |
a6f177ef | 7038 | |
95b3cf69 XG |
7039 | /* |
7040 | * If the mapping is invalid in guest, let cpu retry | |
7041 | * it to generate fault. | |
7042 | */ | |
7043 | if (gpa == UNMAPPED_GVA) | |
7044 | return true; | |
7045 | } | |
a6f177ef | 7046 | |
8e3d9d06 XG |
7047 | /* |
7048 | * Do not retry the unhandleable instruction if it faults on the | |
7049 | * readonly host memory, otherwise it will goto a infinite loop: | |
7050 | * retry instruction -> write #PF -> emulation fail -> retry | |
7051 | * instruction -> ... | |
7052 | */ | |
7053 | pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); | |
95b3cf69 XG |
7054 | |
7055 | /* | |
7056 | * If the instruction failed on the error pfn, it can not be fixed, | |
7057 | * report the error to userspace. | |
7058 | */ | |
7059 | if (is_error_noslot_pfn(pfn)) | |
7060 | return false; | |
7061 | ||
7062 | kvm_release_pfn_clean(pfn); | |
7063 | ||
7064 | /* The instructions are well-emulated on direct mmu. */ | |
44dd3ffa | 7065 | if (vcpu->arch.mmu->direct_map) { |
95b3cf69 XG |
7066 | unsigned int indirect_shadow_pages; |
7067 | ||
7068 | spin_lock(&vcpu->kvm->mmu_lock); | |
7069 | indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; | |
7070 | spin_unlock(&vcpu->kvm->mmu_lock); | |
7071 | ||
7072 | if (indirect_shadow_pages) | |
7073 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
7074 | ||
a6f177ef | 7075 | return true; |
8e3d9d06 | 7076 | } |
a6f177ef | 7077 | |
95b3cf69 XG |
7078 | /* |
7079 | * if emulation was due to access to shadowed page table | |
7080 | * and it failed try to unshadow page and re-enter the | |
7081 | * guest to let CPU execute the instruction. | |
7082 | */ | |
7083 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
93c05d3e XG |
7084 | |
7085 | /* | |
7086 | * If the access faults on its page table, it can not | |
7087 | * be fixed by unprotecting shadow page and it should | |
7088 | * be reported to userspace. | |
7089 | */ | |
7090 | return !write_fault_to_shadow_pgtable; | |
a6f177ef GN |
7091 | } |
7092 | ||
1cb3f3ae | 7093 | static bool retry_instruction(struct x86_emulate_ctxt *ctxt, |
736c291c | 7094 | gpa_t cr2_or_gpa, int emulation_type) |
1cb3f3ae XG |
7095 | { |
7096 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
736c291c | 7097 | unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa; |
1cb3f3ae XG |
7098 | |
7099 | last_retry_eip = vcpu->arch.last_retry_eip; | |
7100 | last_retry_addr = vcpu->arch.last_retry_addr; | |
7101 | ||
7102 | /* | |
7103 | * If the emulation is caused by #PF and it is non-page_table | |
7104 | * writing instruction, it means the VM-EXIT is caused by shadow | |
7105 | * page protected, we can zap the shadow page and retry this | |
7106 | * instruction directly. | |
7107 | * | |
7108 | * Note: if the guest uses a non-page-table modifying instruction | |
7109 | * on the PDE that points to the instruction, then we will unmap | |
7110 | * the instruction and go to an infinite loop. So, we cache the | |
7111 | * last retried eip and the last fault address, if we meet the eip | |
7112 | * and the address again, we can break out of the potential infinite | |
7113 | * loop. | |
7114 | */ | |
7115 | vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; | |
7116 | ||
92daa48b | 7117 | if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) |
1cb3f3ae XG |
7118 | return false; |
7119 | ||
92daa48b SC |
7120 | if (WARN_ON_ONCE(is_guest_mode(vcpu)) || |
7121 | WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) | |
6c3dfeb6 SC |
7122 | return false; |
7123 | ||
1cb3f3ae XG |
7124 | if (x86_page_table_writing_insn(ctxt)) |
7125 | return false; | |
7126 | ||
736c291c | 7127 | if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa) |
1cb3f3ae XG |
7128 | return false; |
7129 | ||
7130 | vcpu->arch.last_retry_eip = ctxt->eip; | |
736c291c | 7131 | vcpu->arch.last_retry_addr = cr2_or_gpa; |
1cb3f3ae | 7132 | |
44dd3ffa | 7133 | if (!vcpu->arch.mmu->direct_map) |
736c291c | 7134 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); |
1cb3f3ae | 7135 | |
22368028 | 7136 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); |
1cb3f3ae XG |
7137 | |
7138 | return true; | |
7139 | } | |
7140 | ||
716d51ab GN |
7141 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu); |
7142 | static int complete_emulated_pio(struct kvm_vcpu *vcpu); | |
7143 | ||
64d60670 | 7144 | static void kvm_smm_changed(struct kvm_vcpu *vcpu) |
a584539b | 7145 | { |
64d60670 | 7146 | if (!(vcpu->arch.hflags & HF_SMM_MASK)) { |
660a5d51 PB |
7147 | /* This is a good place to trace that we are exiting SMM. */ |
7148 | trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); | |
7149 | ||
c43203ca PB |
7150 | /* Process a latched INIT or SMI, if any. */ |
7151 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
64d60670 | 7152 | } |
699023e2 PB |
7153 | |
7154 | kvm_mmu_reset_context(vcpu); | |
64d60670 PB |
7155 | } |
7156 | ||
4a1e10d5 PB |
7157 | static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, |
7158 | unsigned long *db) | |
7159 | { | |
7160 | u32 dr6 = 0; | |
7161 | int i; | |
7162 | u32 enable, rwlen; | |
7163 | ||
7164 | enable = dr7; | |
7165 | rwlen = dr7 >> 16; | |
7166 | for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) | |
7167 | if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) | |
7168 | dr6 |= (1 << i); | |
7169 | return dr6; | |
7170 | } | |
7171 | ||
120c2c4f | 7172 | static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu) |
663f4c61 PB |
7173 | { |
7174 | struct kvm_run *kvm_run = vcpu->run; | |
7175 | ||
c8401dda PB |
7176 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { |
7177 | kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM; | |
d5d260c5 | 7178 | kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu); |
c8401dda PB |
7179 | kvm_run->debug.arch.exception = DB_VECTOR; |
7180 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
60fc3d02 | 7181 | return 0; |
663f4c61 | 7182 | } |
120c2c4f | 7183 | kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); |
60fc3d02 | 7184 | return 1; |
663f4c61 PB |
7185 | } |
7186 | ||
6affcbed KH |
7187 | int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) |
7188 | { | |
afaf0b2f | 7189 | unsigned long rflags = kvm_x86_ops.get_rflags(vcpu); |
f8ea7c60 | 7190 | int r; |
6affcbed | 7191 | |
afaf0b2f | 7192 | r = kvm_x86_ops.skip_emulated_instruction(vcpu); |
60fc3d02 | 7193 | if (unlikely(!r)) |
f8ea7c60 | 7194 | return 0; |
c8401dda PB |
7195 | |
7196 | /* | |
7197 | * rflags is the old, "raw" value of the flags. The new value has | |
7198 | * not been saved yet. | |
7199 | * | |
7200 | * This is correct even for TF set by the guest, because "the | |
7201 | * processor will not generate this exception after the instruction | |
7202 | * that sets the TF flag". | |
7203 | */ | |
7204 | if (unlikely(rflags & X86_EFLAGS_TF)) | |
120c2c4f | 7205 | r = kvm_vcpu_do_singlestep(vcpu); |
60fc3d02 | 7206 | return r; |
6affcbed KH |
7207 | } |
7208 | EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); | |
7209 | ||
4a1e10d5 PB |
7210 | static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) |
7211 | { | |
4a1e10d5 PB |
7212 | if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && |
7213 | (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { | |
82b32774 NA |
7214 | struct kvm_run *kvm_run = vcpu->run; |
7215 | unsigned long eip = kvm_get_linear_rip(vcpu); | |
7216 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
7217 | vcpu->arch.guest_debug_dr7, |
7218 | vcpu->arch.eff_db); | |
7219 | ||
7220 | if (dr6 != 0) { | |
6f43ed01 | 7221 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; |
82b32774 | 7222 | kvm_run->debug.arch.pc = eip; |
4a1e10d5 PB |
7223 | kvm_run->debug.arch.exception = DB_VECTOR; |
7224 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
60fc3d02 | 7225 | *r = 0; |
4a1e10d5 PB |
7226 | return true; |
7227 | } | |
7228 | } | |
7229 | ||
4161a569 NA |
7230 | if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && |
7231 | !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { | |
82b32774 NA |
7232 | unsigned long eip = kvm_get_linear_rip(vcpu); |
7233 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
7234 | vcpu->arch.dr7, |
7235 | vcpu->arch.db); | |
7236 | ||
7237 | if (dr6 != 0) { | |
4d5523cf | 7238 | kvm_queue_exception_p(vcpu, DB_VECTOR, dr6); |
60fc3d02 | 7239 | *r = 1; |
4a1e10d5 PB |
7240 | return true; |
7241 | } | |
7242 | } | |
7243 | ||
7244 | return false; | |
7245 | } | |
7246 | ||
04789b66 LA |
7247 | static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) |
7248 | { | |
2d7921c4 AM |
7249 | switch (ctxt->opcode_len) { |
7250 | case 1: | |
7251 | switch (ctxt->b) { | |
7252 | case 0xe4: /* IN */ | |
7253 | case 0xe5: | |
7254 | case 0xec: | |
7255 | case 0xed: | |
7256 | case 0xe6: /* OUT */ | |
7257 | case 0xe7: | |
7258 | case 0xee: | |
7259 | case 0xef: | |
7260 | case 0x6c: /* INS */ | |
7261 | case 0x6d: | |
7262 | case 0x6e: /* OUTS */ | |
7263 | case 0x6f: | |
7264 | return true; | |
7265 | } | |
7266 | break; | |
7267 | case 2: | |
7268 | switch (ctxt->b) { | |
7269 | case 0x33: /* RDPMC */ | |
7270 | return true; | |
7271 | } | |
7272 | break; | |
04789b66 LA |
7273 | } |
7274 | ||
7275 | return false; | |
7276 | } | |
7277 | ||
736c291c SC |
7278 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
7279 | int emulation_type, void *insn, int insn_len) | |
bbd9b64e | 7280 | { |
95cb2295 | 7281 | int r; |
c9b8b07c | 7282 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
7ae441ea | 7283 | bool writeback = true; |
09e3e2a1 SC |
7284 | bool write_fault_to_spt; |
7285 | ||
7286 | if (unlikely(!kvm_x86_ops.can_emulate_instruction(vcpu, insn, insn_len))) | |
7287 | return 1; | |
bbd9b64e | 7288 | |
c595ceee PB |
7289 | vcpu->arch.l1tf_flush_l1d = true; |
7290 | ||
93c05d3e XG |
7291 | /* |
7292 | * Clear write_fault_to_shadow_pgtable here to ensure it is | |
7293 | * never reused. | |
7294 | */ | |
09e3e2a1 | 7295 | write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; |
93c05d3e | 7296 | vcpu->arch.write_fault_to_shadow_pgtable = false; |
26eef70c | 7297 | kvm_clear_exception_queue(vcpu); |
8d7d8102 | 7298 | |
571008da | 7299 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
8ec4722d | 7300 | init_emulate_ctxt(vcpu); |
4a1e10d5 PB |
7301 | |
7302 | /* | |
7303 | * We will reenter on the same instruction since | |
7304 | * we do not set complete_userspace_io. This does not | |
7305 | * handle watchpoints yet, those would be handled in | |
7306 | * the emulate_ops. | |
7307 | */ | |
d391f120 VK |
7308 | if (!(emulation_type & EMULTYPE_SKIP) && |
7309 | kvm_vcpu_check_breakpoint(vcpu, &r)) | |
4a1e10d5 PB |
7310 | return r; |
7311 | ||
9d74191a TY |
7312 | ctxt->interruptibility = 0; |
7313 | ctxt->have_exception = false; | |
e0ad0b47 | 7314 | ctxt->exception.vector = -1; |
9d74191a | 7315 | ctxt->perm_ok = false; |
bbd9b64e | 7316 | |
b51e974f | 7317 | ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; |
4005996e | 7318 | |
9d74191a | 7319 | r = x86_decode_insn(ctxt, insn, insn_len); |
bbd9b64e | 7320 | |
e46479f8 | 7321 | trace_kvm_emulate_insn_start(vcpu); |
f2b5756b | 7322 | ++vcpu->stat.insn_emulation; |
1d2887e2 | 7323 | if (r != EMULATION_OK) { |
b4000606 | 7324 | if ((emulation_type & EMULTYPE_TRAP_UD) || |
c83fad65 SC |
7325 | (emulation_type & EMULTYPE_TRAP_UD_FORCED)) { |
7326 | kvm_queue_exception(vcpu, UD_VECTOR); | |
60fc3d02 | 7327 | return 1; |
c83fad65 | 7328 | } |
736c291c SC |
7329 | if (reexecute_instruction(vcpu, cr2_or_gpa, |
7330 | write_fault_to_spt, | |
7331 | emulation_type)) | |
60fc3d02 | 7332 | return 1; |
8530a79c | 7333 | if (ctxt->have_exception) { |
c8848cee JD |
7334 | /* |
7335 | * #UD should result in just EMULATION_FAILED, and trap-like | |
7336 | * exception should not be encountered during decode. | |
7337 | */ | |
7338 | WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || | |
7339 | exception_type(ctxt->exception.vector) == EXCPT_TRAP); | |
8530a79c | 7340 | inject_emulated_exception(vcpu); |
60fc3d02 | 7341 | return 1; |
8530a79c | 7342 | } |
e2366171 | 7343 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
7344 | } |
7345 | } | |
7346 | ||
42cbf068 SC |
7347 | if ((emulation_type & EMULTYPE_VMWARE_GP) && |
7348 | !is_vmware_backdoor_opcode(ctxt)) { | |
7349 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
60fc3d02 | 7350 | return 1; |
42cbf068 | 7351 | } |
04789b66 | 7352 | |
1957aa63 SC |
7353 | /* |
7354 | * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks | |
7355 | * for kvm_skip_emulated_instruction(). The caller is responsible for | |
7356 | * updating interruptibility state and injecting single-step #DBs. | |
7357 | */ | |
ba8afb6b | 7358 | if (emulation_type & EMULTYPE_SKIP) { |
9dac77fa | 7359 | kvm_rip_write(vcpu, ctxt->_eip); |
bb663c7a NA |
7360 | if (ctxt->eflags & X86_EFLAGS_RF) |
7361 | kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); | |
60fc3d02 | 7362 | return 1; |
ba8afb6b GN |
7363 | } |
7364 | ||
736c291c | 7365 | if (retry_instruction(ctxt, cr2_or_gpa, emulation_type)) |
60fc3d02 | 7366 | return 1; |
1cb3f3ae | 7367 | |
7ae441ea | 7368 | /* this is needed for vmware backdoor interface to work since it |
4d2179e1 | 7369 | changes registers values during IO operation */ |
7ae441ea GN |
7370 | if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { |
7371 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; | |
dd856efa | 7372 | emulator_invalidate_register_cache(ctxt); |
7ae441ea | 7373 | } |
4d2179e1 | 7374 | |
5cd21917 | 7375 | restart: |
92daa48b SC |
7376 | if (emulation_type & EMULTYPE_PF) { |
7377 | /* Save the faulting GPA (cr2) in the address field */ | |
7378 | ctxt->exception.address = cr2_or_gpa; | |
7379 | ||
7380 | /* With shadow page tables, cr2 contains a GVA or nGPA. */ | |
7381 | if (vcpu->arch.mmu->direct_map) { | |
744e699c SC |
7382 | ctxt->gpa_available = true; |
7383 | ctxt->gpa_val = cr2_or_gpa; | |
92daa48b SC |
7384 | } |
7385 | } else { | |
7386 | /* Sanitize the address out of an abundance of paranoia. */ | |
7387 | ctxt->exception.address = 0; | |
7388 | } | |
0f89b207 | 7389 | |
9d74191a | 7390 | r = x86_emulate_insn(ctxt); |
bbd9b64e | 7391 | |
775fde86 | 7392 | if (r == EMULATION_INTERCEPTED) |
60fc3d02 | 7393 | return 1; |
775fde86 | 7394 | |
d2ddd1c4 | 7395 | if (r == EMULATION_FAILED) { |
736c291c | 7396 | if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt, |
991eebf9 | 7397 | emulation_type)) |
60fc3d02 | 7398 | return 1; |
c3cd7ffa | 7399 | |
e2366171 | 7400 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
7401 | } |
7402 | ||
9d74191a | 7403 | if (ctxt->have_exception) { |
60fc3d02 | 7404 | r = 1; |
ef54bcfe PB |
7405 | if (inject_emulated_exception(vcpu)) |
7406 | return r; | |
d2ddd1c4 | 7407 | } else if (vcpu->arch.pio.count) { |
0912c977 PB |
7408 | if (!vcpu->arch.pio.in) { |
7409 | /* FIXME: return into emulator if single-stepping. */ | |
3457e419 | 7410 | vcpu->arch.pio.count = 0; |
0912c977 | 7411 | } else { |
7ae441ea | 7412 | writeback = false; |
716d51ab GN |
7413 | vcpu->arch.complete_userspace_io = complete_emulated_pio; |
7414 | } | |
60fc3d02 | 7415 | r = 0; |
7ae441ea | 7416 | } else if (vcpu->mmio_needed) { |
bc8a0aaf SC |
7417 | ++vcpu->stat.mmio_exits; |
7418 | ||
7ae441ea GN |
7419 | if (!vcpu->mmio_is_write) |
7420 | writeback = false; | |
60fc3d02 | 7421 | r = 0; |
716d51ab | 7422 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; |
7ae441ea | 7423 | } else if (r == EMULATION_RESTART) |
5cd21917 | 7424 | goto restart; |
d2ddd1c4 | 7425 | else |
60fc3d02 | 7426 | r = 1; |
f850e2e6 | 7427 | |
7ae441ea | 7428 | if (writeback) { |
afaf0b2f | 7429 | unsigned long rflags = kvm_x86_ops.get_rflags(vcpu); |
9d74191a | 7430 | toggle_interruptibility(vcpu, ctxt->interruptibility); |
7ae441ea | 7431 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
38827dbd | 7432 | if (!ctxt->have_exception || |
75ee23b3 SC |
7433 | exception_type(ctxt->exception.vector) == EXCPT_TRAP) { |
7434 | kvm_rip_write(vcpu, ctxt->eip); | |
384dea1c | 7435 | if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) |
120c2c4f | 7436 | r = kvm_vcpu_do_singlestep(vcpu); |
afaf0b2f SC |
7437 | if (kvm_x86_ops.update_emulated_instruction) |
7438 | kvm_x86_ops.update_emulated_instruction(vcpu); | |
38827dbd | 7439 | __kvm_set_rflags(vcpu, ctxt->eflags); |
75ee23b3 | 7440 | } |
6addfc42 PB |
7441 | |
7442 | /* | |
7443 | * For STI, interrupts are shadowed; so KVM_REQ_EVENT will | |
7444 | * do nothing, and it will be requested again as soon as | |
7445 | * the shadow expires. But we still need to check here, | |
7446 | * because POPF has no interrupt shadow. | |
7447 | */ | |
7448 | if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) | |
7449 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7ae441ea GN |
7450 | } else |
7451 | vcpu->arch.emulate_regs_need_sync_to_vcpu = true; | |
e85d28f8 GN |
7452 | |
7453 | return r; | |
de7d789a | 7454 | } |
c60658d1 SC |
7455 | |
7456 | int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) | |
7457 | { | |
7458 | return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); | |
7459 | } | |
7460 | EXPORT_SYMBOL_GPL(kvm_emulate_instruction); | |
7461 | ||
7462 | int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, | |
7463 | void *insn, int insn_len) | |
7464 | { | |
7465 | return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); | |
7466 | } | |
7467 | EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); | |
de7d789a | 7468 | |
8764ed55 SC |
7469 | static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) |
7470 | { | |
7471 | vcpu->arch.pio.count = 0; | |
7472 | return 1; | |
7473 | } | |
7474 | ||
45def77e SC |
7475 | static int complete_fast_pio_out(struct kvm_vcpu *vcpu) |
7476 | { | |
7477 | vcpu->arch.pio.count = 0; | |
7478 | ||
7479 | if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) | |
7480 | return 1; | |
7481 | ||
7482 | return kvm_skip_emulated_instruction(vcpu); | |
7483 | } | |
7484 | ||
dca7f128 SC |
7485 | static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, |
7486 | unsigned short port) | |
de7d789a | 7487 | { |
de3cd117 | 7488 | unsigned long val = kvm_rax_read(vcpu); |
2e3bb4d8 SC |
7489 | int ret = emulator_pio_out(vcpu, size, port, &val, 1); |
7490 | ||
8764ed55 SC |
7491 | if (ret) |
7492 | return ret; | |
45def77e | 7493 | |
8764ed55 SC |
7494 | /* |
7495 | * Workaround userspace that relies on old KVM behavior of %rip being | |
7496 | * incremented prior to exiting to userspace to handle "OUT 0x7e". | |
7497 | */ | |
7498 | if (port == 0x7e && | |
7499 | kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { | |
7500 | vcpu->arch.complete_userspace_io = | |
7501 | complete_fast_pio_out_port_0x7e; | |
7502 | kvm_skip_emulated_instruction(vcpu); | |
7503 | } else { | |
45def77e SC |
7504 | vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); |
7505 | vcpu->arch.complete_userspace_io = complete_fast_pio_out; | |
7506 | } | |
8764ed55 | 7507 | return 0; |
de7d789a | 7508 | } |
de7d789a | 7509 | |
8370c3d0 TL |
7510 | static int complete_fast_pio_in(struct kvm_vcpu *vcpu) |
7511 | { | |
7512 | unsigned long val; | |
7513 | ||
7514 | /* We should only ever be called with arch.pio.count equal to 1 */ | |
7515 | BUG_ON(vcpu->arch.pio.count != 1); | |
7516 | ||
45def77e SC |
7517 | if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { |
7518 | vcpu->arch.pio.count = 0; | |
7519 | return 1; | |
7520 | } | |
7521 | ||
8370c3d0 | 7522 | /* For size less than 4 we merge, else we zero extend */ |
de3cd117 | 7523 | val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; |
8370c3d0 TL |
7524 | |
7525 | /* | |
2e3bb4d8 | 7526 | * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform |
8370c3d0 TL |
7527 | * the copy and tracing |
7528 | */ | |
2e3bb4d8 | 7529 | emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1); |
de3cd117 | 7530 | kvm_rax_write(vcpu, val); |
8370c3d0 | 7531 | |
45def77e | 7532 | return kvm_skip_emulated_instruction(vcpu); |
8370c3d0 TL |
7533 | } |
7534 | ||
dca7f128 SC |
7535 | static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, |
7536 | unsigned short port) | |
8370c3d0 TL |
7537 | { |
7538 | unsigned long val; | |
7539 | int ret; | |
7540 | ||
7541 | /* For size less than 4 we merge, else we zero extend */ | |
de3cd117 | 7542 | val = (size < 4) ? kvm_rax_read(vcpu) : 0; |
8370c3d0 | 7543 | |
2e3bb4d8 | 7544 | ret = emulator_pio_in(vcpu, size, port, &val, 1); |
8370c3d0 | 7545 | if (ret) { |
de3cd117 | 7546 | kvm_rax_write(vcpu, val); |
8370c3d0 TL |
7547 | return ret; |
7548 | } | |
7549 | ||
45def77e | 7550 | vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); |
8370c3d0 TL |
7551 | vcpu->arch.complete_userspace_io = complete_fast_pio_in; |
7552 | ||
7553 | return 0; | |
7554 | } | |
dca7f128 SC |
7555 | |
7556 | int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) | |
7557 | { | |
45def77e | 7558 | int ret; |
dca7f128 | 7559 | |
dca7f128 | 7560 | if (in) |
45def77e | 7561 | ret = kvm_fast_pio_in(vcpu, size, port); |
dca7f128 | 7562 | else |
45def77e SC |
7563 | ret = kvm_fast_pio_out(vcpu, size, port); |
7564 | return ret && kvm_skip_emulated_instruction(vcpu); | |
dca7f128 SC |
7565 | } |
7566 | EXPORT_SYMBOL_GPL(kvm_fast_pio); | |
8370c3d0 | 7567 | |
251a5fd6 | 7568 | static int kvmclock_cpu_down_prep(unsigned int cpu) |
8cfdc000 | 7569 | { |
0a3aee0d | 7570 | __this_cpu_write(cpu_tsc_khz, 0); |
251a5fd6 | 7571 | return 0; |
8cfdc000 ZA |
7572 | } |
7573 | ||
7574 | static void tsc_khz_changed(void *data) | |
c8076604 | 7575 | { |
8cfdc000 ZA |
7576 | struct cpufreq_freqs *freq = data; |
7577 | unsigned long khz = 0; | |
7578 | ||
7579 | if (data) | |
7580 | khz = freq->new; | |
7581 | else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
7582 | khz = cpufreq_quick_get(raw_smp_processor_id()); | |
7583 | if (!khz) | |
7584 | khz = tsc_khz; | |
0a3aee0d | 7585 | __this_cpu_write(cpu_tsc_khz, khz); |
c8076604 GH |
7586 | } |
7587 | ||
5fa4ec9c | 7588 | #ifdef CONFIG_X86_64 |
0092e434 VK |
7589 | static void kvm_hyperv_tsc_notifier(void) |
7590 | { | |
0092e434 VK |
7591 | struct kvm *kvm; |
7592 | struct kvm_vcpu *vcpu; | |
7593 | int cpu; | |
7594 | ||
0d9ce162 | 7595 | mutex_lock(&kvm_lock); |
0092e434 VK |
7596 | list_for_each_entry(kvm, &vm_list, vm_list) |
7597 | kvm_make_mclock_inprogress_request(kvm); | |
7598 | ||
7599 | hyperv_stop_tsc_emulation(); | |
7600 | ||
7601 | /* TSC frequency always matches when on Hyper-V */ | |
7602 | for_each_present_cpu(cpu) | |
7603 | per_cpu(cpu_tsc_khz, cpu) = tsc_khz; | |
7604 | kvm_max_guest_tsc_khz = tsc_khz; | |
7605 | ||
7606 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
7607 | struct kvm_arch *ka = &kvm->arch; | |
7608 | ||
7609 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
7610 | ||
7611 | pvclock_update_vm_gtod_copy(kvm); | |
7612 | ||
7613 | kvm_for_each_vcpu(cpu, vcpu, kvm) | |
7614 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
7615 | ||
7616 | kvm_for_each_vcpu(cpu, vcpu, kvm) | |
7617 | kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); | |
7618 | ||
7619 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
7620 | } | |
0d9ce162 | 7621 | mutex_unlock(&kvm_lock); |
0092e434 | 7622 | } |
5fa4ec9c | 7623 | #endif |
0092e434 | 7624 | |
df24014a | 7625 | static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) |
c8076604 | 7626 | { |
c8076604 GH |
7627 | struct kvm *kvm; |
7628 | struct kvm_vcpu *vcpu; | |
7629 | int i, send_ipi = 0; | |
7630 | ||
8cfdc000 ZA |
7631 | /* |
7632 | * We allow guests to temporarily run on slowing clocks, | |
7633 | * provided we notify them after, or to run on accelerating | |
7634 | * clocks, provided we notify them before. Thus time never | |
7635 | * goes backwards. | |
7636 | * | |
7637 | * However, we have a problem. We can't atomically update | |
7638 | * the frequency of a given CPU from this function; it is | |
7639 | * merely a notifier, which can be called from any CPU. | |
7640 | * Changing the TSC frequency at arbitrary points in time | |
7641 | * requires a recomputation of local variables related to | |
7642 | * the TSC for each VCPU. We must flag these local variables | |
7643 | * to be updated and be sure the update takes place with the | |
7644 | * new frequency before any guests proceed. | |
7645 | * | |
7646 | * Unfortunately, the combination of hotplug CPU and frequency | |
7647 | * change creates an intractable locking scenario; the order | |
7648 | * of when these callouts happen is undefined with respect to | |
7649 | * CPU hotplug, and they can race with each other. As such, | |
7650 | * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is | |
7651 | * undefined; you can actually have a CPU frequency change take | |
7652 | * place in between the computation of X and the setting of the | |
7653 | * variable. To protect against this problem, all updates of | |
7654 | * the per_cpu tsc_khz variable are done in an interrupt | |
7655 | * protected IPI, and all callers wishing to update the value | |
7656 | * must wait for a synchronous IPI to complete (which is trivial | |
7657 | * if the caller is on the CPU already). This establishes the | |
7658 | * necessary total order on variable updates. | |
7659 | * | |
7660 | * Note that because a guest time update may take place | |
7661 | * anytime after the setting of the VCPU's request bit, the | |
7662 | * correct TSC value must be set before the request. However, | |
7663 | * to ensure the update actually makes it to any guest which | |
7664 | * starts running in hardware virtualization between the set | |
7665 | * and the acquisition of the spinlock, we must also ping the | |
7666 | * CPU after setting the request bit. | |
7667 | * | |
7668 | */ | |
7669 | ||
df24014a | 7670 | smp_call_function_single(cpu, tsc_khz_changed, freq, 1); |
c8076604 | 7671 | |
0d9ce162 | 7672 | mutex_lock(&kvm_lock); |
c8076604 | 7673 | list_for_each_entry(kvm, &vm_list, vm_list) { |
988a2cae | 7674 | kvm_for_each_vcpu(i, vcpu, kvm) { |
df24014a | 7675 | if (vcpu->cpu != cpu) |
c8076604 | 7676 | continue; |
c285545f | 7677 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0d9ce162 | 7678 | if (vcpu->cpu != raw_smp_processor_id()) |
8cfdc000 | 7679 | send_ipi = 1; |
c8076604 GH |
7680 | } |
7681 | } | |
0d9ce162 | 7682 | mutex_unlock(&kvm_lock); |
c8076604 GH |
7683 | |
7684 | if (freq->old < freq->new && send_ipi) { | |
7685 | /* | |
7686 | * We upscale the frequency. Must make the guest | |
7687 | * doesn't see old kvmclock values while running with | |
7688 | * the new frequency, otherwise we risk the guest sees | |
7689 | * time go backwards. | |
7690 | * | |
7691 | * In case we update the frequency for another cpu | |
7692 | * (which might be in guest context) send an interrupt | |
7693 | * to kick the cpu out of guest context. Next time | |
7694 | * guest context is entered kvmclock will be updated, | |
7695 | * so the guest will not see stale values. | |
7696 | */ | |
df24014a | 7697 | smp_call_function_single(cpu, tsc_khz_changed, freq, 1); |
c8076604 | 7698 | } |
df24014a VK |
7699 | } |
7700 | ||
7701 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, | |
7702 | void *data) | |
7703 | { | |
7704 | struct cpufreq_freqs *freq = data; | |
7705 | int cpu; | |
7706 | ||
7707 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) | |
7708 | return 0; | |
7709 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
7710 | return 0; | |
7711 | ||
7712 | for_each_cpu(cpu, freq->policy->cpus) | |
7713 | __kvmclock_cpufreq_notifier(freq, cpu); | |
7714 | ||
c8076604 GH |
7715 | return 0; |
7716 | } | |
7717 | ||
7718 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
8cfdc000 ZA |
7719 | .notifier_call = kvmclock_cpufreq_notifier |
7720 | }; | |
7721 | ||
251a5fd6 | 7722 | static int kvmclock_cpu_online(unsigned int cpu) |
8cfdc000 | 7723 | { |
251a5fd6 SAS |
7724 | tsc_khz_changed(NULL); |
7725 | return 0; | |
8cfdc000 ZA |
7726 | } |
7727 | ||
b820cc0c ZA |
7728 | static void kvm_timer_init(void) |
7729 | { | |
c285545f | 7730 | max_tsc_khz = tsc_khz; |
460dd42e | 7731 | |
b820cc0c | 7732 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
c285545f | 7733 | #ifdef CONFIG_CPU_FREQ |
aaec7c03 | 7734 | struct cpufreq_policy *policy; |
758f588d BP |
7735 | int cpu; |
7736 | ||
3e26f230 | 7737 | cpu = get_cpu(); |
aaec7c03 | 7738 | policy = cpufreq_cpu_get(cpu); |
9a11997e WL |
7739 | if (policy) { |
7740 | if (policy->cpuinfo.max_freq) | |
7741 | max_tsc_khz = policy->cpuinfo.max_freq; | |
7742 | cpufreq_cpu_put(policy); | |
7743 | } | |
3e26f230 | 7744 | put_cpu(); |
c285545f | 7745 | #endif |
b820cc0c ZA |
7746 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
7747 | CPUFREQ_TRANSITION_NOTIFIER); | |
7748 | } | |
460dd42e | 7749 | |
73c1b41e | 7750 | cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", |
251a5fd6 | 7751 | kvmclock_cpu_online, kvmclock_cpu_down_prep); |
b820cc0c ZA |
7752 | } |
7753 | ||
dd60d217 AK |
7754 | DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); |
7755 | EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu); | |
ff9d07a0 | 7756 | |
f5132b01 | 7757 | int kvm_is_in_guest(void) |
ff9d07a0 | 7758 | { |
086c9855 | 7759 | return __this_cpu_read(current_vcpu) != NULL; |
ff9d07a0 ZY |
7760 | } |
7761 | ||
7762 | static int kvm_is_user_mode(void) | |
7763 | { | |
7764 | int user_mode = 3; | |
dcf46b94 | 7765 | |
086c9855 | 7766 | if (__this_cpu_read(current_vcpu)) |
afaf0b2f | 7767 | user_mode = kvm_x86_ops.get_cpl(__this_cpu_read(current_vcpu)); |
dcf46b94 | 7768 | |
ff9d07a0 ZY |
7769 | return user_mode != 0; |
7770 | } | |
7771 | ||
7772 | static unsigned long kvm_get_guest_ip(void) | |
7773 | { | |
7774 | unsigned long ip = 0; | |
dcf46b94 | 7775 | |
086c9855 AS |
7776 | if (__this_cpu_read(current_vcpu)) |
7777 | ip = kvm_rip_read(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 7778 | |
ff9d07a0 ZY |
7779 | return ip; |
7780 | } | |
7781 | ||
8479e04e LK |
7782 | static void kvm_handle_intel_pt_intr(void) |
7783 | { | |
7784 | struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu); | |
7785 | ||
7786 | kvm_make_request(KVM_REQ_PMI, vcpu); | |
7787 | __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT, | |
7788 | (unsigned long *)&vcpu->arch.pmu.global_status); | |
7789 | } | |
7790 | ||
ff9d07a0 ZY |
7791 | static struct perf_guest_info_callbacks kvm_guest_cbs = { |
7792 | .is_in_guest = kvm_is_in_guest, | |
7793 | .is_user_mode = kvm_is_user_mode, | |
7794 | .get_guest_ip = kvm_get_guest_ip, | |
8479e04e | 7795 | .handle_intel_pt_intr = kvm_handle_intel_pt_intr, |
ff9d07a0 ZY |
7796 | }; |
7797 | ||
16e8d74d MT |
7798 | #ifdef CONFIG_X86_64 |
7799 | static void pvclock_gtod_update_fn(struct work_struct *work) | |
7800 | { | |
d828199e MT |
7801 | struct kvm *kvm; |
7802 | ||
7803 | struct kvm_vcpu *vcpu; | |
7804 | int i; | |
7805 | ||
0d9ce162 | 7806 | mutex_lock(&kvm_lock); |
d828199e MT |
7807 | list_for_each_entry(kvm, &vm_list, vm_list) |
7808 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 7809 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
d828199e | 7810 | atomic_set(&kvm_guest_has_master_clock, 0); |
0d9ce162 | 7811 | mutex_unlock(&kvm_lock); |
16e8d74d MT |
7812 | } |
7813 | ||
7814 | static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); | |
7815 | ||
7816 | /* | |
7817 | * Notification about pvclock gtod data update. | |
7818 | */ | |
7819 | static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, | |
7820 | void *priv) | |
7821 | { | |
7822 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
7823 | struct timekeeper *tk = priv; | |
7824 | ||
7825 | update_pvclock_gtod(tk); | |
7826 | ||
7827 | /* disable master clock if host does not trust, or does not | |
b0c39dc6 | 7828 | * use, TSC based clocksource. |
16e8d74d | 7829 | */ |
b0c39dc6 | 7830 | if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && |
16e8d74d MT |
7831 | atomic_read(&kvm_guest_has_master_clock) != 0) |
7832 | queue_work(system_long_wq, &pvclock_gtod_work); | |
7833 | ||
7834 | return 0; | |
7835 | } | |
7836 | ||
7837 | static struct notifier_block pvclock_gtod_notifier = { | |
7838 | .notifier_call = pvclock_gtod_notify, | |
7839 | }; | |
7840 | #endif | |
7841 | ||
f8c16bba | 7842 | int kvm_arch_init(void *opaque) |
043405e1 | 7843 | { |
d008dfdb | 7844 | struct kvm_x86_init_ops *ops = opaque; |
b820cc0c | 7845 | int r; |
f8c16bba | 7846 | |
afaf0b2f | 7847 | if (kvm_x86_ops.hardware_enable) { |
f8c16bba | 7848 | printk(KERN_ERR "kvm: already loaded the other module\n"); |
56c6d28a ZX |
7849 | r = -EEXIST; |
7850 | goto out; | |
f8c16bba ZX |
7851 | } |
7852 | ||
7853 | if (!ops->cpu_has_kvm_support()) { | |
ef935c25 | 7854 | pr_err_ratelimited("kvm: no hardware support\n"); |
56c6d28a ZX |
7855 | r = -EOPNOTSUPP; |
7856 | goto out; | |
f8c16bba ZX |
7857 | } |
7858 | if (ops->disabled_by_bios()) { | |
ef935c25 | 7859 | pr_err_ratelimited("kvm: disabled by bios\n"); |
56c6d28a ZX |
7860 | r = -EOPNOTSUPP; |
7861 | goto out; | |
f8c16bba ZX |
7862 | } |
7863 | ||
b666a4b6 MO |
7864 | /* |
7865 | * KVM explicitly assumes that the guest has an FPU and | |
7866 | * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the | |
7867 | * vCPU's FPU state as a fxregs_state struct. | |
7868 | */ | |
7869 | if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { | |
7870 | printk(KERN_ERR "kvm: inadequate fpu\n"); | |
7871 | r = -EOPNOTSUPP; | |
7872 | goto out; | |
7873 | } | |
7874 | ||
013f6a5d | 7875 | r = -ENOMEM; |
ed8e4812 | 7876 | x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu), |
b666a4b6 MO |
7877 | __alignof__(struct fpu), SLAB_ACCOUNT, |
7878 | NULL); | |
7879 | if (!x86_fpu_cache) { | |
7880 | printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n"); | |
7881 | goto out; | |
7882 | } | |
7883 | ||
c9b8b07c SC |
7884 | x86_emulator_cache = kvm_alloc_emulator_cache(); |
7885 | if (!x86_emulator_cache) { | |
7886 | pr_err("kvm: failed to allocate cache for x86 emulator\n"); | |
7887 | goto out_free_x86_fpu_cache; | |
7888 | } | |
7889 | ||
7e34fbd0 SC |
7890 | user_return_msrs = alloc_percpu(struct kvm_user_return_msrs); |
7891 | if (!user_return_msrs) { | |
7892 | printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n"); | |
c9b8b07c | 7893 | goto out_free_x86_emulator_cache; |
013f6a5d MT |
7894 | } |
7895 | ||
97db56ce AK |
7896 | r = kvm_mmu_module_init(); |
7897 | if (r) | |
013f6a5d | 7898 | goto out_free_percpu; |
97db56ce | 7899 | |
7b52345e | 7900 | kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, |
ffb128c8 | 7901 | PT_DIRTY_MASK, PT64_NX_MASK, 0, |
d0ec49d4 | 7902 | PT_PRESENT_MASK, 0, sme_me_mask); |
b820cc0c | 7903 | kvm_timer_init(); |
c8076604 | 7904 | |
ff9d07a0 ZY |
7905 | perf_register_guest_info_callbacks(&kvm_guest_cbs); |
7906 | ||
cfc48181 | 7907 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
2acf923e | 7908 | host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); |
cfc48181 SC |
7909 | supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0; |
7910 | } | |
2acf923e | 7911 | |
c5cc421b | 7912 | kvm_lapic_init(); |
0c5f81da WL |
7913 | if (pi_inject_timer == -1) |
7914 | pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER); | |
16e8d74d MT |
7915 | #ifdef CONFIG_X86_64 |
7916 | pvclock_gtod_register_notifier(&pvclock_gtod_notifier); | |
0092e434 | 7917 | |
5fa4ec9c | 7918 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 | 7919 | set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); |
16e8d74d MT |
7920 | #endif |
7921 | ||
f8c16bba | 7922 | return 0; |
56c6d28a | 7923 | |
013f6a5d | 7924 | out_free_percpu: |
7e34fbd0 | 7925 | free_percpu(user_return_msrs); |
c9b8b07c SC |
7926 | out_free_x86_emulator_cache: |
7927 | kmem_cache_destroy(x86_emulator_cache); | |
b666a4b6 MO |
7928 | out_free_x86_fpu_cache: |
7929 | kmem_cache_destroy(x86_fpu_cache); | |
56c6d28a | 7930 | out: |
56c6d28a | 7931 | return r; |
043405e1 | 7932 | } |
8776e519 | 7933 | |
f8c16bba ZX |
7934 | void kvm_arch_exit(void) |
7935 | { | |
0092e434 | 7936 | #ifdef CONFIG_X86_64 |
5fa4ec9c | 7937 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 VK |
7938 | clear_hv_tscchange_cb(); |
7939 | #endif | |
cef84c30 | 7940 | kvm_lapic_exit(); |
ff9d07a0 ZY |
7941 | perf_unregister_guest_info_callbacks(&kvm_guest_cbs); |
7942 | ||
888d256e JK |
7943 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
7944 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
7945 | CPUFREQ_TRANSITION_NOTIFIER); | |
251a5fd6 | 7946 | cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); |
16e8d74d MT |
7947 | #ifdef CONFIG_X86_64 |
7948 | pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); | |
7949 | #endif | |
afaf0b2f | 7950 | kvm_x86_ops.hardware_enable = NULL; |
56c6d28a | 7951 | kvm_mmu_module_exit(); |
7e34fbd0 | 7952 | free_percpu(user_return_msrs); |
b666a4b6 | 7953 | kmem_cache_destroy(x86_fpu_cache); |
56c6d28a | 7954 | } |
f8c16bba | 7955 | |
5cb56059 | 7956 | int kvm_vcpu_halt(struct kvm_vcpu *vcpu) |
8776e519 HB |
7957 | { |
7958 | ++vcpu->stat.halt_exits; | |
35754c98 | 7959 | if (lapic_in_kernel(vcpu)) { |
a4535290 | 7960 | vcpu->arch.mp_state = KVM_MP_STATE_HALTED; |
8776e519 HB |
7961 | return 1; |
7962 | } else { | |
7963 | vcpu->run->exit_reason = KVM_EXIT_HLT; | |
7964 | return 0; | |
7965 | } | |
7966 | } | |
5cb56059 JS |
7967 | EXPORT_SYMBOL_GPL(kvm_vcpu_halt); |
7968 | ||
7969 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) | |
7970 | { | |
6affcbed KH |
7971 | int ret = kvm_skip_emulated_instruction(vcpu); |
7972 | /* | |
7973 | * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered | |
7974 | * KVM_EXIT_DEBUG here. | |
7975 | */ | |
7976 | return kvm_vcpu_halt(vcpu) && ret; | |
5cb56059 | 7977 | } |
8776e519 HB |
7978 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); |
7979 | ||
8ef81a9a | 7980 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
7981 | static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, |
7982 | unsigned long clock_type) | |
7983 | { | |
7984 | struct kvm_clock_pairing clock_pairing; | |
899a31f5 | 7985 | struct timespec64 ts; |
80fbd89c | 7986 | u64 cycle; |
55dd00a7 MT |
7987 | int ret; |
7988 | ||
7989 | if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) | |
7990 | return -KVM_EOPNOTSUPP; | |
7991 | ||
7992 | if (kvm_get_walltime_and_clockread(&ts, &cycle) == false) | |
7993 | return -KVM_EOPNOTSUPP; | |
7994 | ||
7995 | clock_pairing.sec = ts.tv_sec; | |
7996 | clock_pairing.nsec = ts.tv_nsec; | |
7997 | clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); | |
7998 | clock_pairing.flags = 0; | |
bcbfbd8e | 7999 | memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); |
55dd00a7 MT |
8000 | |
8001 | ret = 0; | |
8002 | if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, | |
8003 | sizeof(struct kvm_clock_pairing))) | |
8004 | ret = -KVM_EFAULT; | |
8005 | ||
8006 | return ret; | |
8007 | } | |
8ef81a9a | 8008 | #endif |
55dd00a7 | 8009 | |
6aef266c SV |
8010 | /* |
8011 | * kvm_pv_kick_cpu_op: Kick a vcpu. | |
8012 | * | |
8013 | * @apicid - apicid of vcpu to be kicked. | |
8014 | */ | |
8015 | static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) | |
8016 | { | |
24d2166b | 8017 | struct kvm_lapic_irq lapic_irq; |
6aef266c | 8018 | |
150a84fe | 8019 | lapic_irq.shorthand = APIC_DEST_NOSHORT; |
c96001c5 | 8020 | lapic_irq.dest_mode = APIC_DEST_PHYSICAL; |
ebd28fcb | 8021 | lapic_irq.level = 0; |
24d2166b | 8022 | lapic_irq.dest_id = apicid; |
93bbf0b8 | 8023 | lapic_irq.msi_redir_hint = false; |
6aef266c | 8024 | |
24d2166b | 8025 | lapic_irq.delivery_mode = APIC_DM_REMRD; |
795a149e | 8026 | kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); |
6aef266c SV |
8027 | } |
8028 | ||
4e19c36f SS |
8029 | bool kvm_apicv_activated(struct kvm *kvm) |
8030 | { | |
8031 | return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0); | |
8032 | } | |
8033 | EXPORT_SYMBOL_GPL(kvm_apicv_activated); | |
8034 | ||
8035 | void kvm_apicv_init(struct kvm *kvm, bool enable) | |
8036 | { | |
8037 | if (enable) | |
8038 | clear_bit(APICV_INHIBIT_REASON_DISABLE, | |
8039 | &kvm->arch.apicv_inhibit_reasons); | |
8040 | else | |
8041 | set_bit(APICV_INHIBIT_REASON_DISABLE, | |
8042 | &kvm->arch.apicv_inhibit_reasons); | |
8043 | } | |
8044 | EXPORT_SYMBOL_GPL(kvm_apicv_init); | |
8045 | ||
71506297 WL |
8046 | static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id) |
8047 | { | |
8048 | struct kvm_vcpu *target = NULL; | |
8049 | struct kvm_apic_map *map; | |
8050 | ||
8051 | rcu_read_lock(); | |
8052 | map = rcu_dereference(kvm->arch.apic_map); | |
8053 | ||
8054 | if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) | |
8055 | target = map->phys_map[dest_id]->vcpu; | |
8056 | ||
8057 | rcu_read_unlock(); | |
8058 | ||
266e85a5 | 8059 | if (target && READ_ONCE(target->ready)) |
71506297 WL |
8060 | kvm_vcpu_yield_to(target); |
8061 | } | |
8062 | ||
8776e519 HB |
8063 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
8064 | { | |
8065 | unsigned long nr, a0, a1, a2, a3, ret; | |
6356ee0c | 8066 | int op_64_bit; |
8776e519 | 8067 | |
696ca779 RK |
8068 | if (kvm_hv_hypercall_enabled(vcpu->kvm)) |
8069 | return kvm_hv_hypercall(vcpu); | |
55cd8e5a | 8070 | |
de3cd117 SC |
8071 | nr = kvm_rax_read(vcpu); |
8072 | a0 = kvm_rbx_read(vcpu); | |
8073 | a1 = kvm_rcx_read(vcpu); | |
8074 | a2 = kvm_rdx_read(vcpu); | |
8075 | a3 = kvm_rsi_read(vcpu); | |
8776e519 | 8076 | |
229456fc | 8077 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 8078 | |
a449c7aa NA |
8079 | op_64_bit = is_64_bit_mode(vcpu); |
8080 | if (!op_64_bit) { | |
8776e519 HB |
8081 | nr &= 0xFFFFFFFF; |
8082 | a0 &= 0xFFFFFFFF; | |
8083 | a1 &= 0xFFFFFFFF; | |
8084 | a2 &= 0xFFFFFFFF; | |
8085 | a3 &= 0xFFFFFFFF; | |
8086 | } | |
8087 | ||
afaf0b2f | 8088 | if (kvm_x86_ops.get_cpl(vcpu) != 0) { |
07708c4a | 8089 | ret = -KVM_EPERM; |
696ca779 | 8090 | goto out; |
07708c4a JK |
8091 | } |
8092 | ||
66570e96 OU |
8093 | ret = -KVM_ENOSYS; |
8094 | ||
8776e519 | 8095 | switch (nr) { |
b93463aa AK |
8096 | case KVM_HC_VAPIC_POLL_IRQ: |
8097 | ret = 0; | |
8098 | break; | |
6aef266c | 8099 | case KVM_HC_KICK_CPU: |
66570e96 OU |
8100 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT)) |
8101 | break; | |
8102 | ||
6aef266c | 8103 | kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); |
266e85a5 | 8104 | kvm_sched_yield(vcpu->kvm, a1); |
6aef266c SV |
8105 | ret = 0; |
8106 | break; | |
8ef81a9a | 8107 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
8108 | case KVM_HC_CLOCK_PAIRING: |
8109 | ret = kvm_pv_clock_pairing(vcpu, a0, a1); | |
8110 | break; | |
1ed199a4 | 8111 | #endif |
4180bf1b | 8112 | case KVM_HC_SEND_IPI: |
66570e96 OU |
8113 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI)) |
8114 | break; | |
8115 | ||
4180bf1b WL |
8116 | ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); |
8117 | break; | |
71506297 | 8118 | case KVM_HC_SCHED_YIELD: |
66570e96 OU |
8119 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD)) |
8120 | break; | |
8121 | ||
71506297 WL |
8122 | kvm_sched_yield(vcpu->kvm, a0); |
8123 | ret = 0; | |
8124 | break; | |
8776e519 HB |
8125 | default: |
8126 | ret = -KVM_ENOSYS; | |
8127 | break; | |
8128 | } | |
696ca779 | 8129 | out: |
a449c7aa NA |
8130 | if (!op_64_bit) |
8131 | ret = (u32)ret; | |
de3cd117 | 8132 | kvm_rax_write(vcpu, ret); |
6356ee0c | 8133 | |
f11c3a8d | 8134 | ++vcpu->stat.hypercalls; |
6356ee0c | 8135 | return kvm_skip_emulated_instruction(vcpu); |
8776e519 HB |
8136 | } |
8137 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
8138 | ||
b6785def | 8139 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) |
8776e519 | 8140 | { |
d6aa1000 | 8141 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
8776e519 | 8142 | char instruction[3]; |
5fdbf976 | 8143 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 8144 | |
afaf0b2f | 8145 | kvm_x86_ops.patch_hypercall(vcpu, instruction); |
8776e519 | 8146 | |
ce2e852e DV |
8147 | return emulator_write_emulated(ctxt, rip, instruction, 3, |
8148 | &ctxt->exception); | |
8776e519 HB |
8149 | } |
8150 | ||
851ba692 | 8151 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 8152 | { |
782d422b MG |
8153 | return vcpu->run->request_interrupt_window && |
8154 | likely(!pic_in_kernel(vcpu->kvm)); | |
b6c7a5dc HB |
8155 | } |
8156 | ||
851ba692 | 8157 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 8158 | { |
851ba692 AK |
8159 | struct kvm_run *kvm_run = vcpu->run; |
8160 | ||
91586a3b | 8161 | kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; |
f077825a | 8162 | kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0; |
2d3ad1f4 | 8163 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 8164 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
127a457a MG |
8165 | kvm_run->ready_for_interrupt_injection = |
8166 | pic_in_kernel(vcpu->kvm) || | |
782d422b | 8167 | kvm_vcpu_ready_for_interrupt_injection(vcpu); |
b6c7a5dc HB |
8168 | } |
8169 | ||
95ba8273 GN |
8170 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
8171 | { | |
8172 | int max_irr, tpr; | |
8173 | ||
afaf0b2f | 8174 | if (!kvm_x86_ops.update_cr8_intercept) |
95ba8273 GN |
8175 | return; |
8176 | ||
bce87cce | 8177 | if (!lapic_in_kernel(vcpu)) |
88c808fd AK |
8178 | return; |
8179 | ||
d62caabb AS |
8180 | if (vcpu->arch.apicv_active) |
8181 | return; | |
8182 | ||
8db3baa2 GN |
8183 | if (!vcpu->arch.apic->vapic_addr) |
8184 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
8185 | else | |
8186 | max_irr = -1; | |
95ba8273 GN |
8187 | |
8188 | if (max_irr != -1) | |
8189 | max_irr >>= 4; | |
8190 | ||
8191 | tpr = kvm_lapic_get_cr8(vcpu); | |
8192 | ||
afaf0b2f | 8193 | kvm_x86_ops.update_cr8_intercept(vcpu, tpr, max_irr); |
95ba8273 GN |
8194 | } |
8195 | ||
c9d40913 | 8196 | static void inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit) |
95ba8273 | 8197 | { |
b6b8a145 | 8198 | int r; |
c6b22f59 | 8199 | bool can_inject = true; |
b6b8a145 | 8200 | |
95ba8273 | 8201 | /* try to reinject previous events if any */ |
664f8e26 | 8202 | |
c6b22f59 | 8203 | if (vcpu->arch.exception.injected) { |
afaf0b2f | 8204 | kvm_x86_ops.queue_exception(vcpu); |
c6b22f59 PB |
8205 | can_inject = false; |
8206 | } | |
664f8e26 | 8207 | /* |
a042c26f LA |
8208 | * Do not inject an NMI or interrupt if there is a pending |
8209 | * exception. Exceptions and interrupts are recognized at | |
8210 | * instruction boundaries, i.e. the start of an instruction. | |
8211 | * Trap-like exceptions, e.g. #DB, have higher priority than | |
8212 | * NMIs and interrupts, i.e. traps are recognized before an | |
8213 | * NMI/interrupt that's pending on the same instruction. | |
8214 | * Fault-like exceptions, e.g. #GP and #PF, are the lowest | |
8215 | * priority, but are only generated (pended) during instruction | |
8216 | * execution, i.e. a pending fault-like exception means the | |
8217 | * fault occurred on the *previous* instruction and must be | |
8218 | * serviced prior to recognizing any new events in order to | |
8219 | * fully complete the previous instruction. | |
664f8e26 | 8220 | */ |
1a680e35 | 8221 | else if (!vcpu->arch.exception.pending) { |
c6b22f59 | 8222 | if (vcpu->arch.nmi_injected) { |
afaf0b2f | 8223 | kvm_x86_ops.set_nmi(vcpu); |
c6b22f59 PB |
8224 | can_inject = false; |
8225 | } else if (vcpu->arch.interrupt.injected) { | |
afaf0b2f | 8226 | kvm_x86_ops.set_irq(vcpu); |
c6b22f59 PB |
8227 | can_inject = false; |
8228 | } | |
664f8e26 WL |
8229 | } |
8230 | ||
3b82b8d7 SC |
8231 | WARN_ON_ONCE(vcpu->arch.exception.injected && |
8232 | vcpu->arch.exception.pending); | |
8233 | ||
1a680e35 LA |
8234 | /* |
8235 | * Call check_nested_events() even if we reinjected a previous event | |
8236 | * in order for caller to determine if it should require immediate-exit | |
8237 | * from L2 to L1 due to pending L1 events which require exit | |
8238 | * from L2 to L1. | |
8239 | */ | |
56083bdf | 8240 | if (is_guest_mode(vcpu)) { |
33b22172 | 8241 | r = kvm_x86_ops.nested_ops->check_events(vcpu); |
c9d40913 PB |
8242 | if (r < 0) |
8243 | goto busy; | |
664f8e26 WL |
8244 | } |
8245 | ||
8246 | /* try to inject new event if pending */ | |
b59bb7bd | 8247 | if (vcpu->arch.exception.pending) { |
5c1c85d0 AK |
8248 | trace_kvm_inj_exception(vcpu->arch.exception.nr, |
8249 | vcpu->arch.exception.has_error_code, | |
8250 | vcpu->arch.exception.error_code); | |
d6e8c854 | 8251 | |
664f8e26 WL |
8252 | vcpu->arch.exception.pending = false; |
8253 | vcpu->arch.exception.injected = true; | |
8254 | ||
d6e8c854 NA |
8255 | if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) |
8256 | __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | | |
8257 | X86_EFLAGS_RF); | |
8258 | ||
f10c729f | 8259 | if (vcpu->arch.exception.nr == DB_VECTOR) { |
f10c729f JM |
8260 | kvm_deliver_exception_payload(vcpu); |
8261 | if (vcpu->arch.dr7 & DR7_GD) { | |
8262 | vcpu->arch.dr7 &= ~DR7_GD; | |
8263 | kvm_update_dr7(vcpu); | |
8264 | } | |
6bdf0662 NA |
8265 | } |
8266 | ||
afaf0b2f | 8267 | kvm_x86_ops.queue_exception(vcpu); |
c6b22f59 | 8268 | can_inject = false; |
1a680e35 LA |
8269 | } |
8270 | ||
c9d40913 PB |
8271 | /* |
8272 | * Finally, inject interrupt events. If an event cannot be injected | |
8273 | * due to architectural conditions (e.g. IF=0) a window-open exit | |
8274 | * will re-request KVM_REQ_EVENT. Sometimes however an event is pending | |
8275 | * and can architecturally be injected, but we cannot do it right now: | |
8276 | * an interrupt could have arrived just now and we have to inject it | |
8277 | * as a vmexit, or there could already an event in the queue, which is | |
8278 | * indicated by can_inject. In that case we request an immediate exit | |
8279 | * in order to make progress and get back here for another iteration. | |
8280 | * The kvm_x86_ops hooks communicate this by returning -EBUSY. | |
8281 | */ | |
8282 | if (vcpu->arch.smi_pending) { | |
8283 | r = can_inject ? kvm_x86_ops.smi_allowed(vcpu, true) : -EBUSY; | |
8284 | if (r < 0) | |
8285 | goto busy; | |
8286 | if (r) { | |
8287 | vcpu->arch.smi_pending = false; | |
8288 | ++vcpu->arch.smi_count; | |
8289 | enter_smm(vcpu); | |
8290 | can_inject = false; | |
8291 | } else | |
8292 | kvm_x86_ops.enable_smi_window(vcpu); | |
8293 | } | |
8294 | ||
8295 | if (vcpu->arch.nmi_pending) { | |
8296 | r = can_inject ? kvm_x86_ops.nmi_allowed(vcpu, true) : -EBUSY; | |
8297 | if (r < 0) | |
8298 | goto busy; | |
8299 | if (r) { | |
8300 | --vcpu->arch.nmi_pending; | |
8301 | vcpu->arch.nmi_injected = true; | |
8302 | kvm_x86_ops.set_nmi(vcpu); | |
8303 | can_inject = false; | |
8304 | WARN_ON(kvm_x86_ops.nmi_allowed(vcpu, true) < 0); | |
8305 | } | |
8306 | if (vcpu->arch.nmi_pending) | |
8307 | kvm_x86_ops.enable_nmi_window(vcpu); | |
8308 | } | |
1a680e35 | 8309 | |
c9d40913 PB |
8310 | if (kvm_cpu_has_injectable_intr(vcpu)) { |
8311 | r = can_inject ? kvm_x86_ops.interrupt_allowed(vcpu, true) : -EBUSY; | |
8312 | if (r < 0) | |
8313 | goto busy; | |
8314 | if (r) { | |
8315 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false); | |
8316 | kvm_x86_ops.set_irq(vcpu); | |
8317 | WARN_ON(kvm_x86_ops.interrupt_allowed(vcpu, true) < 0); | |
8318 | } | |
8319 | if (kvm_cpu_has_injectable_intr(vcpu)) | |
8320 | kvm_x86_ops.enable_irq_window(vcpu); | |
95ba8273 | 8321 | } |
ee2cd4b7 | 8322 | |
c9d40913 PB |
8323 | if (is_guest_mode(vcpu) && |
8324 | kvm_x86_ops.nested_ops->hv_timer_pending && | |
8325 | kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) | |
8326 | *req_immediate_exit = true; | |
8327 | ||
8328 | WARN_ON(vcpu->arch.exception.pending); | |
8329 | return; | |
8330 | ||
8331 | busy: | |
8332 | *req_immediate_exit = true; | |
8333 | return; | |
95ba8273 GN |
8334 | } |
8335 | ||
7460fb4a AK |
8336 | static void process_nmi(struct kvm_vcpu *vcpu) |
8337 | { | |
8338 | unsigned limit = 2; | |
8339 | ||
8340 | /* | |
8341 | * x86 is limited to one NMI running, and one NMI pending after it. | |
8342 | * If an NMI is already in progress, limit further NMIs to just one. | |
8343 | * Otherwise, allow two (and we'll inject the first one immediately). | |
8344 | */ | |
afaf0b2f | 8345 | if (kvm_x86_ops.get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) |
7460fb4a AK |
8346 | limit = 1; |
8347 | ||
8348 | vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); | |
8349 | vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); | |
8350 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
8351 | } | |
8352 | ||
ee2cd4b7 | 8353 | static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) |
660a5d51 PB |
8354 | { |
8355 | u32 flags = 0; | |
8356 | flags |= seg->g << 23; | |
8357 | flags |= seg->db << 22; | |
8358 | flags |= seg->l << 21; | |
8359 | flags |= seg->avl << 20; | |
8360 | flags |= seg->present << 15; | |
8361 | flags |= seg->dpl << 13; | |
8362 | flags |= seg->s << 12; | |
8363 | flags |= seg->type << 8; | |
8364 | return flags; | |
8365 | } | |
8366 | ||
ee2cd4b7 | 8367 | static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) |
660a5d51 PB |
8368 | { |
8369 | struct kvm_segment seg; | |
8370 | int offset; | |
8371 | ||
8372 | kvm_get_segment(vcpu, &seg, n); | |
8373 | put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); | |
8374 | ||
8375 | if (n < 3) | |
8376 | offset = 0x7f84 + n * 12; | |
8377 | else | |
8378 | offset = 0x7f2c + (n - 3) * 12; | |
8379 | ||
8380 | put_smstate(u32, buf, offset + 8, seg.base); | |
8381 | put_smstate(u32, buf, offset + 4, seg.limit); | |
ee2cd4b7 | 8382 | put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
8383 | } |
8384 | ||
efbb288a | 8385 | #ifdef CONFIG_X86_64 |
ee2cd4b7 | 8386 | static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) |
660a5d51 PB |
8387 | { |
8388 | struct kvm_segment seg; | |
8389 | int offset; | |
8390 | u16 flags; | |
8391 | ||
8392 | kvm_get_segment(vcpu, &seg, n); | |
8393 | offset = 0x7e00 + n * 16; | |
8394 | ||
ee2cd4b7 | 8395 | flags = enter_smm_get_segment_flags(&seg) >> 8; |
660a5d51 PB |
8396 | put_smstate(u16, buf, offset, seg.selector); |
8397 | put_smstate(u16, buf, offset + 2, flags); | |
8398 | put_smstate(u32, buf, offset + 4, seg.limit); | |
8399 | put_smstate(u64, buf, offset + 8, seg.base); | |
8400 | } | |
efbb288a | 8401 | #endif |
660a5d51 | 8402 | |
ee2cd4b7 | 8403 | static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) |
660a5d51 PB |
8404 | { |
8405 | struct desc_ptr dt; | |
8406 | struct kvm_segment seg; | |
8407 | unsigned long val; | |
8408 | int i; | |
8409 | ||
8410 | put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); | |
8411 | put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); | |
8412 | put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); | |
8413 | put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); | |
8414 | ||
8415 | for (i = 0; i < 8; i++) | |
8416 | put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); | |
8417 | ||
8418 | kvm_get_dr(vcpu, 6, &val); | |
8419 | put_smstate(u32, buf, 0x7fcc, (u32)val); | |
8420 | kvm_get_dr(vcpu, 7, &val); | |
8421 | put_smstate(u32, buf, 0x7fc8, (u32)val); | |
8422 | ||
8423 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
8424 | put_smstate(u32, buf, 0x7fc4, seg.selector); | |
8425 | put_smstate(u32, buf, 0x7f64, seg.base); | |
8426 | put_smstate(u32, buf, 0x7f60, seg.limit); | |
ee2cd4b7 | 8427 | put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
8428 | |
8429 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
8430 | put_smstate(u32, buf, 0x7fc0, seg.selector); | |
8431 | put_smstate(u32, buf, 0x7f80, seg.base); | |
8432 | put_smstate(u32, buf, 0x7f7c, seg.limit); | |
ee2cd4b7 | 8433 | put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); |
660a5d51 | 8434 | |
afaf0b2f | 8435 | kvm_x86_ops.get_gdt(vcpu, &dt); |
660a5d51 PB |
8436 | put_smstate(u32, buf, 0x7f74, dt.address); |
8437 | put_smstate(u32, buf, 0x7f70, dt.size); | |
8438 | ||
afaf0b2f | 8439 | kvm_x86_ops.get_idt(vcpu, &dt); |
660a5d51 PB |
8440 | put_smstate(u32, buf, 0x7f58, dt.address); |
8441 | put_smstate(u32, buf, 0x7f54, dt.size); | |
8442 | ||
8443 | for (i = 0; i < 6; i++) | |
ee2cd4b7 | 8444 | enter_smm_save_seg_32(vcpu, buf, i); |
660a5d51 PB |
8445 | |
8446 | put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); | |
8447 | ||
8448 | /* revision id */ | |
8449 | put_smstate(u32, buf, 0x7efc, 0x00020000); | |
8450 | put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); | |
8451 | } | |
8452 | ||
b68f3cc7 | 8453 | #ifdef CONFIG_X86_64 |
ee2cd4b7 | 8454 | static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) |
660a5d51 | 8455 | { |
660a5d51 PB |
8456 | struct desc_ptr dt; |
8457 | struct kvm_segment seg; | |
8458 | unsigned long val; | |
8459 | int i; | |
8460 | ||
8461 | for (i = 0; i < 16; i++) | |
8462 | put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); | |
8463 | ||
8464 | put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); | |
8465 | put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); | |
8466 | ||
8467 | kvm_get_dr(vcpu, 6, &val); | |
8468 | put_smstate(u64, buf, 0x7f68, val); | |
8469 | kvm_get_dr(vcpu, 7, &val); | |
8470 | put_smstate(u64, buf, 0x7f60, val); | |
8471 | ||
8472 | put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); | |
8473 | put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); | |
8474 | put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); | |
8475 | ||
8476 | put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); | |
8477 | ||
8478 | /* revision id */ | |
8479 | put_smstate(u32, buf, 0x7efc, 0x00020064); | |
8480 | ||
8481 | put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); | |
8482 | ||
8483 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
8484 | put_smstate(u16, buf, 0x7e90, seg.selector); | |
ee2cd4b7 | 8485 | put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); |
660a5d51 PB |
8486 | put_smstate(u32, buf, 0x7e94, seg.limit); |
8487 | put_smstate(u64, buf, 0x7e98, seg.base); | |
8488 | ||
afaf0b2f | 8489 | kvm_x86_ops.get_idt(vcpu, &dt); |
660a5d51 PB |
8490 | put_smstate(u32, buf, 0x7e84, dt.size); |
8491 | put_smstate(u64, buf, 0x7e88, dt.address); | |
8492 | ||
8493 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
8494 | put_smstate(u16, buf, 0x7e70, seg.selector); | |
ee2cd4b7 | 8495 | put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); |
660a5d51 PB |
8496 | put_smstate(u32, buf, 0x7e74, seg.limit); |
8497 | put_smstate(u64, buf, 0x7e78, seg.base); | |
8498 | ||
afaf0b2f | 8499 | kvm_x86_ops.get_gdt(vcpu, &dt); |
660a5d51 PB |
8500 | put_smstate(u32, buf, 0x7e64, dt.size); |
8501 | put_smstate(u64, buf, 0x7e68, dt.address); | |
8502 | ||
8503 | for (i = 0; i < 6; i++) | |
ee2cd4b7 | 8504 | enter_smm_save_seg_64(vcpu, buf, i); |
660a5d51 | 8505 | } |
b68f3cc7 | 8506 | #endif |
660a5d51 | 8507 | |
ee2cd4b7 | 8508 | static void enter_smm(struct kvm_vcpu *vcpu) |
64d60670 | 8509 | { |
660a5d51 | 8510 | struct kvm_segment cs, ds; |
18c3626e | 8511 | struct desc_ptr dt; |
660a5d51 PB |
8512 | char buf[512]; |
8513 | u32 cr0; | |
8514 | ||
660a5d51 | 8515 | trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); |
660a5d51 | 8516 | memset(buf, 0, 512); |
b68f3cc7 | 8517 | #ifdef CONFIG_X86_64 |
d6321d49 | 8518 | if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) |
ee2cd4b7 | 8519 | enter_smm_save_state_64(vcpu, buf); |
660a5d51 | 8520 | else |
b68f3cc7 | 8521 | #endif |
ee2cd4b7 | 8522 | enter_smm_save_state_32(vcpu, buf); |
660a5d51 | 8523 | |
0234bf88 LP |
8524 | /* |
8525 | * Give pre_enter_smm() a chance to make ISA-specific changes to the | |
8526 | * vCPU state (e.g. leave guest mode) after we've saved the state into | |
8527 | * the SMM state-save area. | |
8528 | */ | |
afaf0b2f | 8529 | kvm_x86_ops.pre_enter_smm(vcpu, buf); |
0234bf88 LP |
8530 | |
8531 | vcpu->arch.hflags |= HF_SMM_MASK; | |
54bf36aa | 8532 | kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); |
660a5d51 | 8533 | |
afaf0b2f | 8534 | if (kvm_x86_ops.get_nmi_mask(vcpu)) |
660a5d51 PB |
8535 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; |
8536 | else | |
afaf0b2f | 8537 | kvm_x86_ops.set_nmi_mask(vcpu, true); |
660a5d51 PB |
8538 | |
8539 | kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); | |
8540 | kvm_rip_write(vcpu, 0x8000); | |
8541 | ||
8542 | cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); | |
afaf0b2f | 8543 | kvm_x86_ops.set_cr0(vcpu, cr0); |
660a5d51 PB |
8544 | vcpu->arch.cr0 = cr0; |
8545 | ||
afaf0b2f | 8546 | kvm_x86_ops.set_cr4(vcpu, 0); |
660a5d51 | 8547 | |
18c3626e PB |
8548 | /* Undocumented: IDT limit is set to zero on entry to SMM. */ |
8549 | dt.address = dt.size = 0; | |
afaf0b2f | 8550 | kvm_x86_ops.set_idt(vcpu, &dt); |
18c3626e | 8551 | |
660a5d51 PB |
8552 | __kvm_set_dr(vcpu, 7, DR7_FIXED_1); |
8553 | ||
8554 | cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; | |
8555 | cs.base = vcpu->arch.smbase; | |
8556 | ||
8557 | ds.selector = 0; | |
8558 | ds.base = 0; | |
8559 | ||
8560 | cs.limit = ds.limit = 0xffffffff; | |
8561 | cs.type = ds.type = 0x3; | |
8562 | cs.dpl = ds.dpl = 0; | |
8563 | cs.db = ds.db = 0; | |
8564 | cs.s = ds.s = 1; | |
8565 | cs.l = ds.l = 0; | |
8566 | cs.g = ds.g = 1; | |
8567 | cs.avl = ds.avl = 0; | |
8568 | cs.present = ds.present = 1; | |
8569 | cs.unusable = ds.unusable = 0; | |
8570 | cs.padding = ds.padding = 0; | |
8571 | ||
8572 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
8573 | kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); | |
8574 | kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); | |
8575 | kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); | |
8576 | kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); | |
8577 | kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); | |
8578 | ||
b68f3cc7 | 8579 | #ifdef CONFIG_X86_64 |
d6321d49 | 8580 | if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) |
afaf0b2f | 8581 | kvm_x86_ops.set_efer(vcpu, 0); |
b68f3cc7 | 8582 | #endif |
660a5d51 | 8583 | |
aedbaf4f | 8584 | kvm_update_cpuid_runtime(vcpu); |
660a5d51 | 8585 | kvm_mmu_reset_context(vcpu); |
64d60670 PB |
8586 | } |
8587 | ||
ee2cd4b7 | 8588 | static void process_smi(struct kvm_vcpu *vcpu) |
c43203ca PB |
8589 | { |
8590 | vcpu->arch.smi_pending = true; | |
8591 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
8592 | } | |
8593 | ||
7ee30bc1 NNL |
8594 | void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, |
8595 | unsigned long *vcpu_bitmap) | |
8596 | { | |
8597 | cpumask_var_t cpus; | |
7ee30bc1 NNL |
8598 | |
8599 | zalloc_cpumask_var(&cpus, GFP_ATOMIC); | |
8600 | ||
db5a95ec | 8601 | kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, |
54163a34 | 8602 | NULL, vcpu_bitmap, cpus); |
7ee30bc1 NNL |
8603 | |
8604 | free_cpumask_var(cpus); | |
8605 | } | |
8606 | ||
2860c4b1 PB |
8607 | void kvm_make_scan_ioapic_request(struct kvm *kvm) |
8608 | { | |
8609 | kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); | |
8610 | } | |
8611 | ||
8df14af4 SS |
8612 | void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) |
8613 | { | |
8614 | if (!lapic_in_kernel(vcpu)) | |
8615 | return; | |
8616 | ||
8617 | vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm); | |
8618 | kvm_apic_update_apicv(vcpu); | |
afaf0b2f | 8619 | kvm_x86_ops.refresh_apicv_exec_ctrl(vcpu); |
8df14af4 SS |
8620 | } |
8621 | EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv); | |
8622 | ||
8623 | /* | |
8624 | * NOTE: Do not hold any lock prior to calling this. | |
8625 | * | |
8626 | * In particular, kvm_request_apicv_update() expects kvm->srcu not to be | |
8627 | * locked, because it calls __x86_set_memory_region() which does | |
8628 | * synchronize_srcu(&kvm->srcu). | |
8629 | */ | |
8630 | void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit) | |
8631 | { | |
7d611233 | 8632 | struct kvm_vcpu *except; |
8e205a6b PB |
8633 | unsigned long old, new, expected; |
8634 | ||
afaf0b2f SC |
8635 | if (!kvm_x86_ops.check_apicv_inhibit_reasons || |
8636 | !kvm_x86_ops.check_apicv_inhibit_reasons(bit)) | |
ef8efd7a SS |
8637 | return; |
8638 | ||
8e205a6b PB |
8639 | old = READ_ONCE(kvm->arch.apicv_inhibit_reasons); |
8640 | do { | |
8641 | expected = new = old; | |
8642 | if (activate) | |
8643 | __clear_bit(bit, &new); | |
8644 | else | |
8645 | __set_bit(bit, &new); | |
8646 | if (new == old) | |
8647 | break; | |
8648 | old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new); | |
8649 | } while (old != expected); | |
8650 | ||
8651 | if (!!old == !!new) | |
8652 | return; | |
8df14af4 | 8653 | |
24bbf74c | 8654 | trace_kvm_apicv_update_request(activate, bit); |
afaf0b2f SC |
8655 | if (kvm_x86_ops.pre_update_apicv_exec_ctrl) |
8656 | kvm_x86_ops.pre_update_apicv_exec_ctrl(kvm, activate); | |
7d611233 SS |
8657 | |
8658 | /* | |
8659 | * Sending request to update APICV for all other vcpus, | |
8660 | * while update the calling vcpu immediately instead of | |
8661 | * waiting for another #VMEXIT to handle the request. | |
8662 | */ | |
8663 | except = kvm_get_running_vcpu(); | |
8664 | kvm_make_all_cpus_request_except(kvm, KVM_REQ_APICV_UPDATE, | |
8665 | except); | |
8666 | if (except) | |
8667 | kvm_vcpu_update_apicv(except); | |
8df14af4 SS |
8668 | } |
8669 | EXPORT_SYMBOL_GPL(kvm_request_apicv_update); | |
8670 | ||
3d81bc7e | 8671 | static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) |
c7c9c56c | 8672 | { |
dcbd3e49 | 8673 | if (!kvm_apic_present(vcpu)) |
3d81bc7e | 8674 | return; |
c7c9c56c | 8675 | |
6308630b | 8676 | bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); |
c7c9c56c | 8677 | |
b053b2ae | 8678 | if (irqchip_split(vcpu->kvm)) |
6308630b | 8679 | kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); |
db2bdcbb | 8680 | else { |
fa59cc00 | 8681 | if (vcpu->arch.apicv_active) |
afaf0b2f | 8682 | kvm_x86_ops.sync_pir_to_irr(vcpu); |
e97f852f WL |
8683 | if (ioapic_in_kernel(vcpu->kvm)) |
8684 | kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); | |
db2bdcbb | 8685 | } |
e40ff1d6 LA |
8686 | |
8687 | if (is_guest_mode(vcpu)) | |
8688 | vcpu->arch.load_eoi_exitmap_pending = true; | |
8689 | else | |
8690 | kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); | |
8691 | } | |
8692 | ||
8693 | static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) | |
8694 | { | |
8695 | u64 eoi_exit_bitmap[4]; | |
8696 | ||
8697 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) | |
8698 | return; | |
8699 | ||
5c919412 AS |
8700 | bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors, |
8701 | vcpu_to_synic(vcpu)->vec_bitmap, 256); | |
afaf0b2f | 8702 | kvm_x86_ops.load_eoi_exitmap(vcpu, eoi_exit_bitmap); |
c7c9c56c YZ |
8703 | } |
8704 | ||
e649b3f0 ET |
8705 | void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, |
8706 | unsigned long start, unsigned long end) | |
b1394e74 RK |
8707 | { |
8708 | unsigned long apic_address; | |
8709 | ||
8710 | /* | |
8711 | * The physical address of apic access page is stored in the VMCS. | |
8712 | * Update it when it becomes invalid. | |
8713 | */ | |
8714 | apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); | |
8715 | if (start <= apic_address && apic_address < end) | |
8716 | kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); | |
8717 | } | |
8718 | ||
4256f43f TC |
8719 | void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) |
8720 | { | |
35754c98 | 8721 | if (!lapic_in_kernel(vcpu)) |
f439ed27 PB |
8722 | return; |
8723 | ||
afaf0b2f | 8724 | if (!kvm_x86_ops.set_apic_access_page_addr) |
4256f43f TC |
8725 | return; |
8726 | ||
a4148b7c | 8727 | kvm_x86_ops.set_apic_access_page_addr(vcpu); |
4256f43f | 8728 | } |
4256f43f | 8729 | |
d264ee0c SC |
8730 | void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) |
8731 | { | |
8732 | smp_send_reschedule(vcpu->cpu); | |
8733 | } | |
8734 | EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); | |
8735 | ||
9357d939 | 8736 | /* |
362c698f | 8737 | * Returns 1 to let vcpu_run() continue the guest execution loop without |
9357d939 TY |
8738 | * exiting to the userspace. Otherwise, the value will be returned to the |
8739 | * userspace. | |
8740 | */ | |
851ba692 | 8741 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
8742 | { |
8743 | int r; | |
62a193ed MG |
8744 | bool req_int_win = |
8745 | dm_request_for_irq_injection(vcpu) && | |
8746 | kvm_cpu_accept_dm_intr(vcpu); | |
404d5d7b | 8747 | fastpath_t exit_fastpath; |
62a193ed | 8748 | |
730dca42 | 8749 | bool req_immediate_exit = false; |
b6c7a5dc | 8750 | |
2fa6e1e1 | 8751 | if (kvm_request_pending(vcpu)) { |
729c15c2 PB |
8752 | if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) { |
8753 | if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) { | |
671ddc70 JM |
8754 | r = 0; |
8755 | goto out; | |
8756 | } | |
8757 | } | |
a8eeb04a | 8758 | if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) |
2e53d63a | 8759 | kvm_mmu_unload(vcpu); |
a8eeb04a | 8760 | if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) |
2f599714 | 8761 | __kvm_migrate_timers(vcpu); |
d828199e MT |
8762 | if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) |
8763 | kvm_gen_update_masterclock(vcpu->kvm); | |
0061d53d MT |
8764 | if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) |
8765 | kvm_gen_kvmclock_update(vcpu); | |
34c238a1 ZA |
8766 | if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { |
8767 | r = kvm_guest_time_update(vcpu); | |
8cfdc000 ZA |
8768 | if (unlikely(r)) |
8769 | goto out; | |
8770 | } | |
a8eeb04a | 8771 | if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) |
4731d4c7 | 8772 | kvm_mmu_sync_roots(vcpu); |
727a7e27 PB |
8773 | if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu)) |
8774 | kvm_mmu_load_pgd(vcpu); | |
eeeb4f67 | 8775 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) { |
7780938c | 8776 | kvm_vcpu_flush_tlb_all(vcpu); |
eeeb4f67 SC |
8777 | |
8778 | /* Flushing all ASIDs flushes the current ASID... */ | |
8779 | kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); | |
8780 | } | |
8781 | if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu)) | |
8782 | kvm_vcpu_flush_tlb_current(vcpu); | |
0baedd79 VK |
8783 | if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu)) |
8784 | kvm_vcpu_flush_tlb_guest(vcpu); | |
eeeb4f67 | 8785 | |
a8eeb04a | 8786 | if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { |
851ba692 | 8787 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
8788 | r = 0; |
8789 | goto out; | |
8790 | } | |
a8eeb04a | 8791 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
851ba692 | 8792 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
bbeac283 | 8793 | vcpu->mmio_needed = 0; |
71c4dfaf JR |
8794 | r = 0; |
8795 | goto out; | |
8796 | } | |
af585b92 GN |
8797 | if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { |
8798 | /* Page is swapped out. Do synthetic halt */ | |
8799 | vcpu->arch.apf.halted = true; | |
8800 | r = 1; | |
8801 | goto out; | |
8802 | } | |
c9aaa895 GC |
8803 | if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) |
8804 | record_steal_time(vcpu); | |
64d60670 PB |
8805 | if (kvm_check_request(KVM_REQ_SMI, vcpu)) |
8806 | process_smi(vcpu); | |
7460fb4a AK |
8807 | if (kvm_check_request(KVM_REQ_NMI, vcpu)) |
8808 | process_nmi(vcpu); | |
f5132b01 | 8809 | if (kvm_check_request(KVM_REQ_PMU, vcpu)) |
c6702c9d | 8810 | kvm_pmu_handle_event(vcpu); |
f5132b01 | 8811 | if (kvm_check_request(KVM_REQ_PMI, vcpu)) |
c6702c9d | 8812 | kvm_pmu_deliver_pmi(vcpu); |
7543a635 SR |
8813 | if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { |
8814 | BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); | |
8815 | if (test_bit(vcpu->arch.pending_ioapic_eoi, | |
6308630b | 8816 | vcpu->arch.ioapic_handled_vectors)) { |
7543a635 SR |
8817 | vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; |
8818 | vcpu->run->eoi.vector = | |
8819 | vcpu->arch.pending_ioapic_eoi; | |
8820 | r = 0; | |
8821 | goto out; | |
8822 | } | |
8823 | } | |
3d81bc7e YZ |
8824 | if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) |
8825 | vcpu_scan_ioapic(vcpu); | |
e40ff1d6 LA |
8826 | if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) |
8827 | vcpu_load_eoi_exitmap(vcpu); | |
4256f43f TC |
8828 | if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) |
8829 | kvm_vcpu_reload_apic_access_page(vcpu); | |
2ce79189 AS |
8830 | if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { |
8831 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
8832 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; | |
8833 | r = 0; | |
8834 | goto out; | |
8835 | } | |
e516cebb AS |
8836 | if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { |
8837 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
8838 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; | |
8839 | r = 0; | |
8840 | goto out; | |
8841 | } | |
db397571 AS |
8842 | if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { |
8843 | vcpu->run->exit_reason = KVM_EXIT_HYPERV; | |
8844 | vcpu->run->hyperv = vcpu->arch.hyperv.exit; | |
8845 | r = 0; | |
8846 | goto out; | |
8847 | } | |
f3b138c5 AS |
8848 | |
8849 | /* | |
8850 | * KVM_REQ_HV_STIMER has to be processed after | |
8851 | * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers | |
8852 | * depend on the guest clock being up-to-date | |
8853 | */ | |
1f4b34f8 AS |
8854 | if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) |
8855 | kvm_hv_process_stimers(vcpu); | |
8df14af4 SS |
8856 | if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) |
8857 | kvm_vcpu_update_apicv(vcpu); | |
557a961a VK |
8858 | if (kvm_check_request(KVM_REQ_APF_READY, vcpu)) |
8859 | kvm_check_async_pf_completion(vcpu); | |
1a155254 AG |
8860 | if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu)) |
8861 | kvm_x86_ops.msr_filter_changed(vcpu); | |
2f52d58c | 8862 | } |
b93463aa | 8863 | |
b463a6f7 | 8864 | if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { |
0f1e261e | 8865 | ++vcpu->stat.req_event; |
66450a21 JK |
8866 | kvm_apic_accept_events(vcpu); |
8867 | if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { | |
8868 | r = 1; | |
8869 | goto out; | |
8870 | } | |
8871 | ||
c9d40913 PB |
8872 | inject_pending_event(vcpu, &req_immediate_exit); |
8873 | if (req_int_win) | |
8874 | kvm_x86_ops.enable_irq_window(vcpu); | |
b463a6f7 AK |
8875 | |
8876 | if (kvm_lapic_enabled(vcpu)) { | |
8877 | update_cr8_intercept(vcpu); | |
8878 | kvm_lapic_sync_to_vapic(vcpu); | |
8879 | } | |
8880 | } | |
8881 | ||
d8368af8 AK |
8882 | r = kvm_mmu_reload(vcpu); |
8883 | if (unlikely(r)) { | |
d905c069 | 8884 | goto cancel_injection; |
d8368af8 AK |
8885 | } |
8886 | ||
b6c7a5dc HB |
8887 | preempt_disable(); |
8888 | ||
afaf0b2f | 8889 | kvm_x86_ops.prepare_guest_switch(vcpu); |
b95234c8 PB |
8890 | |
8891 | /* | |
8892 | * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt | |
8893 | * IPI are then delayed after guest entry, which ensures that they | |
8894 | * result in virtual interrupt delivery. | |
8895 | */ | |
8896 | local_irq_disable(); | |
6b7e2d09 XG |
8897 | vcpu->mode = IN_GUEST_MODE; |
8898 | ||
01b71917 MT |
8899 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
8900 | ||
0f127d12 | 8901 | /* |
b95234c8 | 8902 | * 1) We should set ->mode before checking ->requests. Please see |
cde9af6e | 8903 | * the comment in kvm_vcpu_exiting_guest_mode(). |
b95234c8 | 8904 | * |
81b01667 | 8905 | * 2) For APICv, we should set ->mode before checking PID.ON. This |
b95234c8 PB |
8906 | * pairs with the memory barrier implicit in pi_test_and_set_on |
8907 | * (see vmx_deliver_posted_interrupt). | |
8908 | * | |
8909 | * 3) This also orders the write to mode from any reads to the page | |
8910 | * tables done while the VCPU is running. Please see the comment | |
8911 | * in kvm_flush_remote_tlbs. | |
6b7e2d09 | 8912 | */ |
01b71917 | 8913 | smp_mb__after_srcu_read_unlock(); |
b6c7a5dc | 8914 | |
b95234c8 PB |
8915 | /* |
8916 | * This handles the case where a posted interrupt was | |
8917 | * notified with kvm_vcpu_kick. | |
8918 | */ | |
fa59cc00 | 8919 | if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active) |
afaf0b2f | 8920 | kvm_x86_ops.sync_pir_to_irr(vcpu); |
32f88400 | 8921 | |
5a9f5443 | 8922 | if (kvm_vcpu_exit_request(vcpu)) { |
6b7e2d09 | 8923 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 8924 | smp_wmb(); |
6c142801 AK |
8925 | local_irq_enable(); |
8926 | preempt_enable(); | |
01b71917 | 8927 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
6c142801 | 8928 | r = 1; |
d905c069 | 8929 | goto cancel_injection; |
6c142801 AK |
8930 | } |
8931 | ||
c43203ca PB |
8932 | if (req_immediate_exit) { |
8933 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
afaf0b2f | 8934 | kvm_x86_ops.request_immediate_exit(vcpu); |
c43203ca | 8935 | } |
d6185f20 | 8936 | |
b2d52255 | 8937 | trace_kvm_entry(vcpu); |
b6c7a5dc | 8938 | |
2620fe26 SC |
8939 | fpregs_assert_state_consistent(); |
8940 | if (test_thread_flag(TIF_NEED_FPU_LOAD)) | |
8941 | switch_fpu_return(); | |
5f409e20 | 8942 | |
42dbaa5a | 8943 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
8944 | set_debugreg(0, 7); |
8945 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
8946 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
8947 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
8948 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
c77fb5fe | 8949 | set_debugreg(vcpu->arch.dr6, 6); |
ae561ede | 8950 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; |
42dbaa5a | 8951 | } |
b6c7a5dc | 8952 | |
a9ab13ff | 8953 | exit_fastpath = kvm_x86_ops.run(vcpu); |
b6c7a5dc | 8954 | |
c77fb5fe PB |
8955 | /* |
8956 | * Do this here before restoring debug registers on the host. And | |
8957 | * since we do this before handling the vmexit, a DR access vmexit | |
8958 | * can (a) read the correct value of the debug registers, (b) set | |
8959 | * KVM_DEBUGREG_WONT_EXIT again. | |
8960 | */ | |
8961 | if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { | |
c77fb5fe | 8962 | WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); |
afaf0b2f | 8963 | kvm_x86_ops.sync_dirty_debug_regs(vcpu); |
70e4da7a | 8964 | kvm_update_dr0123(vcpu); |
70e4da7a PB |
8965 | kvm_update_dr7(vcpu); |
8966 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; | |
c77fb5fe PB |
8967 | } |
8968 | ||
24f1e32c FW |
8969 | /* |
8970 | * If the guest has used debug registers, at least dr7 | |
8971 | * will be disabled while returning to the host. | |
8972 | * If we don't have active breakpoints in the host, we don't | |
8973 | * care about the messed up debug address registers. But if | |
8974 | * we have some of them active, restore the old state. | |
8975 | */ | |
59d8eb53 | 8976 | if (hw_breakpoint_active()) |
24f1e32c | 8977 | hw_breakpoint_restore(); |
42dbaa5a | 8978 | |
c967118d | 8979 | vcpu->arch.last_vmentry_cpu = vcpu->cpu; |
4ba76538 | 8980 | vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); |
1d5f066e | 8981 | |
6b7e2d09 | 8982 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 8983 | smp_wmb(); |
a547c6db | 8984 | |
a9ab13ff | 8985 | kvm_x86_ops.handle_exit_irqoff(vcpu); |
b6c7a5dc | 8986 | |
d7a08882 SC |
8987 | /* |
8988 | * Consume any pending interrupts, including the possible source of | |
8989 | * VM-Exit on SVM and any ticks that occur between VM-Exit and now. | |
8990 | * An instruction is required after local_irq_enable() to fully unblock | |
8991 | * interrupts on processors that implement an interrupt shadow, the | |
8992 | * stat.exits increment will do nicely. | |
8993 | */ | |
8994 | kvm_before_interrupt(vcpu); | |
8995 | local_irq_enable(); | |
b6c7a5dc | 8996 | ++vcpu->stat.exits; |
d7a08882 SC |
8997 | local_irq_disable(); |
8998 | kvm_after_interrupt(vcpu); | |
b6c7a5dc | 8999 | |
ec0671d5 WL |
9000 | if (lapic_in_kernel(vcpu)) { |
9001 | s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta; | |
9002 | if (delta != S64_MIN) { | |
9003 | trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta); | |
9004 | vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN; | |
9005 | } | |
9006 | } | |
b6c7a5dc | 9007 | |
f2485b3e | 9008 | local_irq_enable(); |
b6c7a5dc HB |
9009 | preempt_enable(); |
9010 | ||
f656ce01 | 9011 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
3200f405 | 9012 | |
b6c7a5dc HB |
9013 | /* |
9014 | * Profile KVM exit RIPs: | |
9015 | */ | |
9016 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
9017 | unsigned long rip = kvm_rip_read(vcpu); |
9018 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
9019 | } |
9020 | ||
cc578287 ZA |
9021 | if (unlikely(vcpu->arch.tsc_always_catchup)) |
9022 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
298101da | 9023 | |
5cfb1d5a MT |
9024 | if (vcpu->arch.apic_attention) |
9025 | kvm_lapic_sync_from_vapic(vcpu); | |
b93463aa | 9026 | |
afaf0b2f | 9027 | r = kvm_x86_ops.handle_exit(vcpu, exit_fastpath); |
d905c069 MT |
9028 | return r; |
9029 | ||
9030 | cancel_injection: | |
8081ad06 SC |
9031 | if (req_immediate_exit) |
9032 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
afaf0b2f | 9033 | kvm_x86_ops.cancel_injection(vcpu); |
ae7a2a3f MT |
9034 | if (unlikely(vcpu->arch.apic_attention)) |
9035 | kvm_lapic_sync_from_vapic(vcpu); | |
d7690175 MT |
9036 | out: |
9037 | return r; | |
9038 | } | |
b6c7a5dc | 9039 | |
362c698f PB |
9040 | static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) |
9041 | { | |
bf9f6ac8 | 9042 | if (!kvm_arch_vcpu_runnable(vcpu) && |
afaf0b2f | 9043 | (!kvm_x86_ops.pre_block || kvm_x86_ops.pre_block(vcpu) == 0)) { |
9c8fd1ba PB |
9044 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
9045 | kvm_vcpu_block(vcpu); | |
9046 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); | |
bf9f6ac8 | 9047 | |
afaf0b2f SC |
9048 | if (kvm_x86_ops.post_block) |
9049 | kvm_x86_ops.post_block(vcpu); | |
bf9f6ac8 | 9050 | |
9c8fd1ba PB |
9051 | if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) |
9052 | return 1; | |
9053 | } | |
362c698f PB |
9054 | |
9055 | kvm_apic_accept_events(vcpu); | |
9056 | switch(vcpu->arch.mp_state) { | |
9057 | case KVM_MP_STATE_HALTED: | |
9058 | vcpu->arch.pv.pv_unhalted = false; | |
9059 | vcpu->arch.mp_state = | |
9060 | KVM_MP_STATE_RUNNABLE; | |
df561f66 | 9061 | fallthrough; |
362c698f PB |
9062 | case KVM_MP_STATE_RUNNABLE: |
9063 | vcpu->arch.apf.halted = false; | |
9064 | break; | |
9065 | case KVM_MP_STATE_INIT_RECEIVED: | |
9066 | break; | |
9067 | default: | |
9068 | return -EINTR; | |
362c698f PB |
9069 | } |
9070 | return 1; | |
9071 | } | |
09cec754 | 9072 | |
5d9bc648 PB |
9073 | static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) |
9074 | { | |
56083bdf | 9075 | if (is_guest_mode(vcpu)) |
33b22172 | 9076 | kvm_x86_ops.nested_ops->check_events(vcpu); |
0ad3bed6 | 9077 | |
5d9bc648 PB |
9078 | return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
9079 | !vcpu->arch.apf.halted); | |
9080 | } | |
9081 | ||
362c698f | 9082 | static int vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
9083 | { |
9084 | int r; | |
f656ce01 | 9085 | struct kvm *kvm = vcpu->kvm; |
d7690175 | 9086 | |
f656ce01 | 9087 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
c595ceee | 9088 | vcpu->arch.l1tf_flush_l1d = true; |
d7690175 | 9089 | |
362c698f | 9090 | for (;;) { |
58f800d5 | 9091 | if (kvm_vcpu_running(vcpu)) { |
851ba692 | 9092 | r = vcpu_enter_guest(vcpu); |
bf9f6ac8 | 9093 | } else { |
362c698f | 9094 | r = vcpu_block(kvm, vcpu); |
bf9f6ac8 FW |
9095 | } |
9096 | ||
09cec754 GN |
9097 | if (r <= 0) |
9098 | break; | |
9099 | ||
72875d8a | 9100 | kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu); |
09cec754 GN |
9101 | if (kvm_cpu_has_pending_timer(vcpu)) |
9102 | kvm_inject_pending_timer_irqs(vcpu); | |
9103 | ||
782d422b MG |
9104 | if (dm_request_for_irq_injection(vcpu) && |
9105 | kvm_vcpu_ready_for_interrupt_injection(vcpu)) { | |
4ca7dd8c PB |
9106 | r = 0; |
9107 | vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; | |
09cec754 | 9108 | ++vcpu->stat.request_irq_exits; |
362c698f | 9109 | break; |
09cec754 | 9110 | } |
af585b92 | 9111 | |
f3020b88 | 9112 | if (__xfer_to_guest_mode_work_pending()) { |
f656ce01 | 9113 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
72c3c0fe TG |
9114 | r = xfer_to_guest_mode_handle_work(vcpu); |
9115 | if (r) | |
9116 | return r; | |
f656ce01 | 9117 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 9118 | } |
b6c7a5dc HB |
9119 | } |
9120 | ||
f656ce01 | 9121 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
b6c7a5dc HB |
9122 | |
9123 | return r; | |
9124 | } | |
9125 | ||
716d51ab GN |
9126 | static inline int complete_emulated_io(struct kvm_vcpu *vcpu) |
9127 | { | |
9128 | int r; | |
60fc3d02 | 9129 | |
716d51ab | 9130 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
0ce97a2b | 9131 | r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); |
716d51ab | 9132 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
60fc3d02 | 9133 | return r; |
716d51ab GN |
9134 | } |
9135 | ||
9136 | static int complete_emulated_pio(struct kvm_vcpu *vcpu) | |
9137 | { | |
9138 | BUG_ON(!vcpu->arch.pio.count); | |
9139 | ||
9140 | return complete_emulated_io(vcpu); | |
9141 | } | |
9142 | ||
f78146b0 AK |
9143 | /* |
9144 | * Implements the following, as a state machine: | |
9145 | * | |
9146 | * read: | |
9147 | * for each fragment | |
87da7e66 XG |
9148 | * for each mmio piece in the fragment |
9149 | * write gpa, len | |
9150 | * exit | |
9151 | * copy data | |
f78146b0 AK |
9152 | * execute insn |
9153 | * | |
9154 | * write: | |
9155 | * for each fragment | |
87da7e66 XG |
9156 | * for each mmio piece in the fragment |
9157 | * write gpa, len | |
9158 | * copy data | |
9159 | * exit | |
f78146b0 | 9160 | */ |
716d51ab | 9161 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu) |
5287f194 AK |
9162 | { |
9163 | struct kvm_run *run = vcpu->run; | |
f78146b0 | 9164 | struct kvm_mmio_fragment *frag; |
87da7e66 | 9165 | unsigned len; |
5287f194 | 9166 | |
716d51ab | 9167 | BUG_ON(!vcpu->mmio_needed); |
5287f194 | 9168 | |
716d51ab | 9169 | /* Complete previous fragment */ |
87da7e66 XG |
9170 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; |
9171 | len = min(8u, frag->len); | |
716d51ab | 9172 | if (!vcpu->mmio_is_write) |
87da7e66 XG |
9173 | memcpy(frag->data, run->mmio.data, len); |
9174 | ||
9175 | if (frag->len <= 8) { | |
9176 | /* Switch to the next fragment. */ | |
9177 | frag++; | |
9178 | vcpu->mmio_cur_fragment++; | |
9179 | } else { | |
9180 | /* Go forward to the next mmio piece. */ | |
9181 | frag->data += len; | |
9182 | frag->gpa += len; | |
9183 | frag->len -= len; | |
9184 | } | |
9185 | ||
a08d3b3b | 9186 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { |
716d51ab | 9187 | vcpu->mmio_needed = 0; |
0912c977 PB |
9188 | |
9189 | /* FIXME: return into emulator if single-stepping. */ | |
cef4dea0 | 9190 | if (vcpu->mmio_is_write) |
716d51ab GN |
9191 | return 1; |
9192 | vcpu->mmio_read_completed = 1; | |
9193 | return complete_emulated_io(vcpu); | |
9194 | } | |
87da7e66 | 9195 | |
716d51ab GN |
9196 | run->exit_reason = KVM_EXIT_MMIO; |
9197 | run->mmio.phys_addr = frag->gpa; | |
9198 | if (vcpu->mmio_is_write) | |
87da7e66 XG |
9199 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); |
9200 | run->mmio.len = min(8u, frag->len); | |
716d51ab GN |
9201 | run->mmio.is_write = vcpu->mmio_is_write; |
9202 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; | |
9203 | return 0; | |
5287f194 AK |
9204 | } |
9205 | ||
c9aef3b8 SC |
9206 | static void kvm_save_current_fpu(struct fpu *fpu) |
9207 | { | |
9208 | /* | |
9209 | * If the target FPU state is not resident in the CPU registers, just | |
9210 | * memcpy() from current, else save CPU state directly to the target. | |
9211 | */ | |
9212 | if (test_thread_flag(TIF_NEED_FPU_LOAD)) | |
9213 | memcpy(&fpu->state, ¤t->thread.fpu.state, | |
9214 | fpu_kernel_xstate_size); | |
9215 | else | |
9216 | copy_fpregs_to_fpstate(fpu); | |
9217 | } | |
9218 | ||
822f312d SAS |
9219 | /* Swap (qemu) user FPU context for the guest FPU context. */ |
9220 | static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) | |
9221 | { | |
5f409e20 RR |
9222 | fpregs_lock(); |
9223 | ||
c9aef3b8 SC |
9224 | kvm_save_current_fpu(vcpu->arch.user_fpu); |
9225 | ||
afaf0b2f | 9226 | /* PKRU is separately restored in kvm_x86_ops.run. */ |
b666a4b6 | 9227 | __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state, |
822f312d | 9228 | ~XFEATURE_MASK_PKRU); |
5f409e20 RR |
9229 | |
9230 | fpregs_mark_activate(); | |
9231 | fpregs_unlock(); | |
9232 | ||
822f312d SAS |
9233 | trace_kvm_fpu(1); |
9234 | } | |
9235 | ||
9236 | /* When vcpu_run ends, restore user space FPU context. */ | |
9237 | static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
9238 | { | |
5f409e20 RR |
9239 | fpregs_lock(); |
9240 | ||
c9aef3b8 SC |
9241 | kvm_save_current_fpu(vcpu->arch.guest_fpu); |
9242 | ||
d9a710e5 | 9243 | copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state); |
5f409e20 RR |
9244 | |
9245 | fpregs_mark_activate(); | |
9246 | fpregs_unlock(); | |
9247 | ||
822f312d SAS |
9248 | ++vcpu->stat.fpu_reload; |
9249 | trace_kvm_fpu(0); | |
9250 | } | |
9251 | ||
1b94f6f8 | 9252 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) |
b6c7a5dc | 9253 | { |
1b94f6f8 | 9254 | struct kvm_run *kvm_run = vcpu->run; |
b6c7a5dc | 9255 | int r; |
b6c7a5dc | 9256 | |
accb757d | 9257 | vcpu_load(vcpu); |
20b7035c | 9258 | kvm_sigset_activate(vcpu); |
5663d8f9 PX |
9259 | kvm_load_guest_fpu(vcpu); |
9260 | ||
a4535290 | 9261 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
2f173d26 JS |
9262 | if (kvm_run->immediate_exit) { |
9263 | r = -EINTR; | |
9264 | goto out; | |
9265 | } | |
b6c7a5dc | 9266 | kvm_vcpu_block(vcpu); |
66450a21 | 9267 | kvm_apic_accept_events(vcpu); |
72875d8a | 9268 | kvm_clear_request(KVM_REQ_UNHALT, vcpu); |
ac9f6dc0 | 9269 | r = -EAGAIN; |
a0595000 JS |
9270 | if (signal_pending(current)) { |
9271 | r = -EINTR; | |
1b94f6f8 | 9272 | kvm_run->exit_reason = KVM_EXIT_INTR; |
a0595000 JS |
9273 | ++vcpu->stat.signal_exits; |
9274 | } | |
ac9f6dc0 | 9275 | goto out; |
b6c7a5dc HB |
9276 | } |
9277 | ||
1b94f6f8 | 9278 | if (kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) { |
01643c51 KH |
9279 | r = -EINVAL; |
9280 | goto out; | |
9281 | } | |
9282 | ||
1b94f6f8 | 9283 | if (kvm_run->kvm_dirty_regs) { |
01643c51 KH |
9284 | r = sync_regs(vcpu); |
9285 | if (r != 0) | |
9286 | goto out; | |
9287 | } | |
9288 | ||
b6c7a5dc | 9289 | /* re-sync apic's tpr */ |
35754c98 | 9290 | if (!lapic_in_kernel(vcpu)) { |
eea1cff9 AP |
9291 | if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { |
9292 | r = -EINVAL; | |
9293 | goto out; | |
9294 | } | |
9295 | } | |
b6c7a5dc | 9296 | |
716d51ab GN |
9297 | if (unlikely(vcpu->arch.complete_userspace_io)) { |
9298 | int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; | |
9299 | vcpu->arch.complete_userspace_io = NULL; | |
9300 | r = cui(vcpu); | |
9301 | if (r <= 0) | |
5663d8f9 | 9302 | goto out; |
716d51ab GN |
9303 | } else |
9304 | WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); | |
5287f194 | 9305 | |
460df4c1 PB |
9306 | if (kvm_run->immediate_exit) |
9307 | r = -EINTR; | |
9308 | else | |
9309 | r = vcpu_run(vcpu); | |
b6c7a5dc HB |
9310 | |
9311 | out: | |
5663d8f9 | 9312 | kvm_put_guest_fpu(vcpu); |
1b94f6f8 | 9313 | if (kvm_run->kvm_valid_regs) |
01643c51 | 9314 | store_regs(vcpu); |
f1d86e46 | 9315 | post_kvm_run_save(vcpu); |
20b7035c | 9316 | kvm_sigset_deactivate(vcpu); |
b6c7a5dc | 9317 | |
accb757d | 9318 | vcpu_put(vcpu); |
b6c7a5dc HB |
9319 | return r; |
9320 | } | |
9321 | ||
01643c51 | 9322 | static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 9323 | { |
7ae441ea GN |
9324 | if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { |
9325 | /* | |
9326 | * We are here if userspace calls get_regs() in the middle of | |
9327 | * instruction emulation. Registers state needs to be copied | |
4a969980 | 9328 | * back from emulation context to vcpu. Userspace shouldn't do |
7ae441ea GN |
9329 | * that usually, but some bad designed PV devices (vmware |
9330 | * backdoor interface) need this to work | |
9331 | */ | |
c9b8b07c | 9332 | emulator_writeback_register_cache(vcpu->arch.emulate_ctxt); |
7ae441ea GN |
9333 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
9334 | } | |
de3cd117 SC |
9335 | regs->rax = kvm_rax_read(vcpu); |
9336 | regs->rbx = kvm_rbx_read(vcpu); | |
9337 | regs->rcx = kvm_rcx_read(vcpu); | |
9338 | regs->rdx = kvm_rdx_read(vcpu); | |
9339 | regs->rsi = kvm_rsi_read(vcpu); | |
9340 | regs->rdi = kvm_rdi_read(vcpu); | |
e9c16c78 | 9341 | regs->rsp = kvm_rsp_read(vcpu); |
de3cd117 | 9342 | regs->rbp = kvm_rbp_read(vcpu); |
b6c7a5dc | 9343 | #ifdef CONFIG_X86_64 |
de3cd117 SC |
9344 | regs->r8 = kvm_r8_read(vcpu); |
9345 | regs->r9 = kvm_r9_read(vcpu); | |
9346 | regs->r10 = kvm_r10_read(vcpu); | |
9347 | regs->r11 = kvm_r11_read(vcpu); | |
9348 | regs->r12 = kvm_r12_read(vcpu); | |
9349 | regs->r13 = kvm_r13_read(vcpu); | |
9350 | regs->r14 = kvm_r14_read(vcpu); | |
9351 | regs->r15 = kvm_r15_read(vcpu); | |
b6c7a5dc HB |
9352 | #endif |
9353 | ||
5fdbf976 | 9354 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 9355 | regs->rflags = kvm_get_rflags(vcpu); |
01643c51 | 9356 | } |
b6c7a5dc | 9357 | |
01643c51 KH |
9358 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
9359 | { | |
9360 | vcpu_load(vcpu); | |
9361 | __get_regs(vcpu, regs); | |
1fc9b76b | 9362 | vcpu_put(vcpu); |
b6c7a5dc HB |
9363 | return 0; |
9364 | } | |
9365 | ||
01643c51 | 9366 | static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 9367 | { |
7ae441ea GN |
9368 | vcpu->arch.emulate_regs_need_sync_from_vcpu = true; |
9369 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; | |
9370 | ||
de3cd117 SC |
9371 | kvm_rax_write(vcpu, regs->rax); |
9372 | kvm_rbx_write(vcpu, regs->rbx); | |
9373 | kvm_rcx_write(vcpu, regs->rcx); | |
9374 | kvm_rdx_write(vcpu, regs->rdx); | |
9375 | kvm_rsi_write(vcpu, regs->rsi); | |
9376 | kvm_rdi_write(vcpu, regs->rdi); | |
e9c16c78 | 9377 | kvm_rsp_write(vcpu, regs->rsp); |
de3cd117 | 9378 | kvm_rbp_write(vcpu, regs->rbp); |
b6c7a5dc | 9379 | #ifdef CONFIG_X86_64 |
de3cd117 SC |
9380 | kvm_r8_write(vcpu, regs->r8); |
9381 | kvm_r9_write(vcpu, regs->r9); | |
9382 | kvm_r10_write(vcpu, regs->r10); | |
9383 | kvm_r11_write(vcpu, regs->r11); | |
9384 | kvm_r12_write(vcpu, regs->r12); | |
9385 | kvm_r13_write(vcpu, regs->r13); | |
9386 | kvm_r14_write(vcpu, regs->r14); | |
9387 | kvm_r15_write(vcpu, regs->r15); | |
b6c7a5dc HB |
9388 | #endif |
9389 | ||
5fdbf976 | 9390 | kvm_rip_write(vcpu, regs->rip); |
d73235d1 | 9391 | kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); |
b6c7a5dc | 9392 | |
b4f14abd JK |
9393 | vcpu->arch.exception.pending = false; |
9394 | ||
3842d135 | 9395 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
01643c51 | 9396 | } |
3842d135 | 9397 | |
01643c51 KH |
9398 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
9399 | { | |
9400 | vcpu_load(vcpu); | |
9401 | __set_regs(vcpu, regs); | |
875656fe | 9402 | vcpu_put(vcpu); |
b6c7a5dc HB |
9403 | return 0; |
9404 | } | |
9405 | ||
b6c7a5dc HB |
9406 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
9407 | { | |
9408 | struct kvm_segment cs; | |
9409 | ||
3e6e0aab | 9410 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
9411 | *db = cs.db; |
9412 | *l = cs.l; | |
9413 | } | |
9414 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
9415 | ||
01643c51 | 9416 | static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
b6c7a5dc | 9417 | { |
89a27f4d | 9418 | struct desc_ptr dt; |
b6c7a5dc | 9419 | |
3e6e0aab GT |
9420 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
9421 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
9422 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
9423 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
9424 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
9425 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 9426 | |
3e6e0aab GT |
9427 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
9428 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 9429 | |
afaf0b2f | 9430 | kvm_x86_ops.get_idt(vcpu, &dt); |
89a27f4d GN |
9431 | sregs->idt.limit = dt.size; |
9432 | sregs->idt.base = dt.address; | |
afaf0b2f | 9433 | kvm_x86_ops.get_gdt(vcpu, &dt); |
89a27f4d GN |
9434 | sregs->gdt.limit = dt.size; |
9435 | sregs->gdt.base = dt.address; | |
b6c7a5dc | 9436 | |
4d4ec087 | 9437 | sregs->cr0 = kvm_read_cr0(vcpu); |
ad312c7c | 9438 | sregs->cr2 = vcpu->arch.cr2; |
9f8fe504 | 9439 | sregs->cr3 = kvm_read_cr3(vcpu); |
fc78f519 | 9440 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 9441 | sregs->cr8 = kvm_get_cr8(vcpu); |
f6801dff | 9442 | sregs->efer = vcpu->arch.efer; |
b6c7a5dc HB |
9443 | sregs->apic_base = kvm_get_apic_base(vcpu); |
9444 | ||
0e96f31e | 9445 | memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap)); |
b6c7a5dc | 9446 | |
04140b41 | 9447 | if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
9448 | set_bit(vcpu->arch.interrupt.nr, |
9449 | (unsigned long *)sregs->interrupt_bitmap); | |
01643c51 | 9450 | } |
16d7a191 | 9451 | |
01643c51 KH |
9452 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, |
9453 | struct kvm_sregs *sregs) | |
9454 | { | |
9455 | vcpu_load(vcpu); | |
9456 | __get_sregs(vcpu, sregs); | |
bcdec41c | 9457 | vcpu_put(vcpu); |
b6c7a5dc HB |
9458 | return 0; |
9459 | } | |
9460 | ||
62d9f0db MT |
9461 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
9462 | struct kvm_mp_state *mp_state) | |
9463 | { | |
fd232561 | 9464 | vcpu_load(vcpu); |
f958bd23 SC |
9465 | if (kvm_mpx_supported()) |
9466 | kvm_load_guest_fpu(vcpu); | |
fd232561 | 9467 | |
66450a21 | 9468 | kvm_apic_accept_events(vcpu); |
6aef266c SV |
9469 | if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && |
9470 | vcpu->arch.pv.pv_unhalted) | |
9471 | mp_state->mp_state = KVM_MP_STATE_RUNNABLE; | |
9472 | else | |
9473 | mp_state->mp_state = vcpu->arch.mp_state; | |
9474 | ||
f958bd23 SC |
9475 | if (kvm_mpx_supported()) |
9476 | kvm_put_guest_fpu(vcpu); | |
fd232561 | 9477 | vcpu_put(vcpu); |
62d9f0db MT |
9478 | return 0; |
9479 | } | |
9480 | ||
9481 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
9482 | struct kvm_mp_state *mp_state) | |
9483 | { | |
e83dff5e CD |
9484 | int ret = -EINVAL; |
9485 | ||
9486 | vcpu_load(vcpu); | |
9487 | ||
bce87cce | 9488 | if (!lapic_in_kernel(vcpu) && |
66450a21 | 9489 | mp_state->mp_state != KVM_MP_STATE_RUNNABLE) |
e83dff5e | 9490 | goto out; |
66450a21 | 9491 | |
27cbe7d6 LA |
9492 | /* |
9493 | * KVM_MP_STATE_INIT_RECEIVED means the processor is in | |
9494 | * INIT state; latched init should be reported using | |
9495 | * KVM_SET_VCPU_EVENTS, so reject it here. | |
9496 | */ | |
9497 | if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) && | |
28bf2888 DH |
9498 | (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || |
9499 | mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) | |
e83dff5e | 9500 | goto out; |
28bf2888 | 9501 | |
66450a21 JK |
9502 | if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { |
9503 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
9504 | set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); | |
9505 | } else | |
9506 | vcpu->arch.mp_state = mp_state->mp_state; | |
3842d135 | 9507 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
e83dff5e CD |
9508 | |
9509 | ret = 0; | |
9510 | out: | |
9511 | vcpu_put(vcpu); | |
9512 | return ret; | |
62d9f0db MT |
9513 | } |
9514 | ||
7f3d35fd KW |
9515 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
9516 | int reason, bool has_error_code, u32 error_code) | |
b6c7a5dc | 9517 | { |
c9b8b07c | 9518 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
8ec4722d | 9519 | int ret; |
e01c2426 | 9520 | |
8ec4722d | 9521 | init_emulate_ctxt(vcpu); |
c697518a | 9522 | |
7f3d35fd | 9523 | ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, |
9d74191a | 9524 | has_error_code, error_code); |
1051778f SC |
9525 | if (ret) { |
9526 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
9527 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
9528 | vcpu->run->internal.ndata = 0; | |
60fc3d02 | 9529 | return 0; |
1051778f | 9530 | } |
37817f29 | 9531 | |
9d74191a TY |
9532 | kvm_rip_write(vcpu, ctxt->eip); |
9533 | kvm_set_rflags(vcpu, ctxt->eflags); | |
60fc3d02 | 9534 | return 1; |
37817f29 IE |
9535 | } |
9536 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
9537 | ||
3140c156 | 9538 | static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
f2981033 | 9539 | { |
37b95951 | 9540 | if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { |
f2981033 LT |
9541 | /* |
9542 | * When EFER.LME and CR0.PG are set, the processor is in | |
9543 | * 64-bit mode (though maybe in a 32-bit code segment). | |
9544 | * CR4.PAE and EFER.LMA must be set. | |
9545 | */ | |
37b95951 | 9546 | if (!(sregs->cr4 & X86_CR4_PAE) |
f2981033 LT |
9547 | || !(sregs->efer & EFER_LMA)) |
9548 | return -EINVAL; | |
9549 | } else { | |
9550 | /* | |
9551 | * Not in 64-bit mode: EFER.LMA is clear and the code | |
9552 | * segment cannot be 64-bit. | |
9553 | */ | |
9554 | if (sregs->efer & EFER_LMA || sregs->cs.l) | |
9555 | return -EINVAL; | |
9556 | } | |
9557 | ||
3ca94192 | 9558 | return kvm_valid_cr4(vcpu, sregs->cr4); |
f2981033 LT |
9559 | } |
9560 | ||
01643c51 | 9561 | static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
b6c7a5dc | 9562 | { |
58cb628d | 9563 | struct msr_data apic_base_msr; |
b6c7a5dc | 9564 | int mmu_reset_needed = 0; |
c4d21882 | 9565 | int cpuid_update_needed = 0; |
63f42e02 | 9566 | int pending_vec, max_bits, idx; |
89a27f4d | 9567 | struct desc_ptr dt; |
b4ef9d4e CD |
9568 | int ret = -EINVAL; |
9569 | ||
f2981033 | 9570 | if (kvm_valid_sregs(vcpu, sregs)) |
8dbfb2bf | 9571 | goto out; |
f2981033 | 9572 | |
d3802286 JM |
9573 | apic_base_msr.data = sregs->apic_base; |
9574 | apic_base_msr.host_initiated = true; | |
9575 | if (kvm_set_apic_base(vcpu, &apic_base_msr)) | |
b4ef9d4e | 9576 | goto out; |
6d1068b3 | 9577 | |
89a27f4d GN |
9578 | dt.size = sregs->idt.limit; |
9579 | dt.address = sregs->idt.base; | |
afaf0b2f | 9580 | kvm_x86_ops.set_idt(vcpu, &dt); |
89a27f4d GN |
9581 | dt.size = sregs->gdt.limit; |
9582 | dt.address = sregs->gdt.base; | |
afaf0b2f | 9583 | kvm_x86_ops.set_gdt(vcpu, &dt); |
b6c7a5dc | 9584 | |
ad312c7c | 9585 | vcpu->arch.cr2 = sregs->cr2; |
9f8fe504 | 9586 | mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; |
dc7e795e | 9587 | vcpu->arch.cr3 = sregs->cr3; |
cb3c1e2f | 9588 | kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); |
b6c7a5dc | 9589 | |
2d3ad1f4 | 9590 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 9591 | |
f6801dff | 9592 | mmu_reset_needed |= vcpu->arch.efer != sregs->efer; |
afaf0b2f | 9593 | kvm_x86_ops.set_efer(vcpu, sregs->efer); |
b6c7a5dc | 9594 | |
4d4ec087 | 9595 | mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
afaf0b2f | 9596 | kvm_x86_ops.set_cr0(vcpu, sregs->cr0); |
d7306163 | 9597 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 9598 | |
fc78f519 | 9599 | mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
c4d21882 WH |
9600 | cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) & |
9601 | (X86_CR4_OSXSAVE | X86_CR4_PKE)); | |
afaf0b2f | 9602 | kvm_x86_ops.set_cr4(vcpu, sregs->cr4); |
c4d21882 | 9603 | if (cpuid_update_needed) |
aedbaf4f | 9604 | kvm_update_cpuid_runtime(vcpu); |
63f42e02 XG |
9605 | |
9606 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
bf03d4f9 | 9607 | if (is_pae_paging(vcpu)) { |
9f8fe504 | 9608 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
7c93be44 MT |
9609 | mmu_reset_needed = 1; |
9610 | } | |
63f42e02 | 9611 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b6c7a5dc HB |
9612 | |
9613 | if (mmu_reset_needed) | |
9614 | kvm_mmu_reset_context(vcpu); | |
9615 | ||
a50abc3b | 9616 | max_bits = KVM_NR_INTERRUPTS; |
923c61bb GN |
9617 | pending_vec = find_first_bit( |
9618 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
9619 | if (pending_vec < max_bits) { | |
66fd3f7f | 9620 | kvm_queue_interrupt(vcpu, pending_vec, false); |
923c61bb | 9621 | pr_debug("Set back pending irq %d\n", pending_vec); |
b6c7a5dc HB |
9622 | } |
9623 | ||
3e6e0aab GT |
9624 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
9625 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
9626 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
9627 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
9628 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
9629 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 9630 | |
3e6e0aab GT |
9631 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
9632 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 9633 | |
5f0269f5 ME |
9634 | update_cr8_intercept(vcpu); |
9635 | ||
9c3e4aab | 9636 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 9637 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 9638 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
3eeb3288 | 9639 | !is_protmode(vcpu)) |
9c3e4aab MT |
9640 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
9641 | ||
3842d135 AK |
9642 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
9643 | ||
b4ef9d4e CD |
9644 | ret = 0; |
9645 | out: | |
01643c51 KH |
9646 | return ret; |
9647 | } | |
9648 | ||
9649 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, | |
9650 | struct kvm_sregs *sregs) | |
9651 | { | |
9652 | int ret; | |
9653 | ||
9654 | vcpu_load(vcpu); | |
9655 | ret = __set_sregs(vcpu, sregs); | |
b4ef9d4e CD |
9656 | vcpu_put(vcpu); |
9657 | return ret; | |
b6c7a5dc HB |
9658 | } |
9659 | ||
d0bfb940 JK |
9660 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
9661 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 9662 | { |
355be0b9 | 9663 | unsigned long rflags; |
ae675ef0 | 9664 | int i, r; |
b6c7a5dc | 9665 | |
66b56562 CD |
9666 | vcpu_load(vcpu); |
9667 | ||
4f926bf2 JK |
9668 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
9669 | r = -EBUSY; | |
9670 | if (vcpu->arch.exception.pending) | |
2122ff5e | 9671 | goto out; |
4f926bf2 JK |
9672 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
9673 | kvm_queue_exception(vcpu, DB_VECTOR); | |
9674 | else | |
9675 | kvm_queue_exception(vcpu, BP_VECTOR); | |
9676 | } | |
9677 | ||
91586a3b JK |
9678 | /* |
9679 | * Read rflags as long as potentially injected trace flags are still | |
9680 | * filtered out. | |
9681 | */ | |
9682 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
9683 | |
9684 | vcpu->guest_debug = dbg->control; | |
9685 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
9686 | vcpu->guest_debug = 0; | |
9687 | ||
9688 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
9689 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
9690 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
c8639010 | 9691 | vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; |
ae675ef0 JK |
9692 | } else { |
9693 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
9694 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
ae675ef0 | 9695 | } |
c8639010 | 9696 | kvm_update_dr7(vcpu); |
ae675ef0 | 9697 | |
f92653ee JK |
9698 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
9699 | vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + | |
9700 | get_segment_base(vcpu, VCPU_SREG_CS); | |
94fe45da | 9701 | |
91586a3b JK |
9702 | /* |
9703 | * Trigger an rflags update that will inject or remove the trace | |
9704 | * flags. | |
9705 | */ | |
9706 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 9707 | |
6986982f | 9708 | kvm_x86_ops.update_exception_bitmap(vcpu); |
b6c7a5dc | 9709 | |
4f926bf2 | 9710 | r = 0; |
d0bfb940 | 9711 | |
2122ff5e | 9712 | out: |
66b56562 | 9713 | vcpu_put(vcpu); |
b6c7a5dc HB |
9714 | return r; |
9715 | } | |
9716 | ||
8b006791 ZX |
9717 | /* |
9718 | * Translate a guest virtual address to a guest physical address. | |
9719 | */ | |
9720 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
9721 | struct kvm_translation *tr) | |
9722 | { | |
9723 | unsigned long vaddr = tr->linear_address; | |
9724 | gpa_t gpa; | |
f656ce01 | 9725 | int idx; |
8b006791 | 9726 | |
1da5b61d CD |
9727 | vcpu_load(vcpu); |
9728 | ||
f656ce01 | 9729 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1871c602 | 9730 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); |
f656ce01 | 9731 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 ZX |
9732 | tr->physical_address = gpa; |
9733 | tr->valid = gpa != UNMAPPED_GVA; | |
9734 | tr->writeable = 1; | |
9735 | tr->usermode = 0; | |
8b006791 | 9736 | |
1da5b61d | 9737 | vcpu_put(vcpu); |
8b006791 ZX |
9738 | return 0; |
9739 | } | |
9740 | ||
d0752060 HB |
9741 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
9742 | { | |
1393123e | 9743 | struct fxregs_state *fxsave; |
d0752060 | 9744 | |
1393123e | 9745 | vcpu_load(vcpu); |
d0752060 | 9746 | |
b666a4b6 | 9747 | fxsave = &vcpu->arch.guest_fpu->state.fxsave; |
d0752060 HB |
9748 | memcpy(fpu->fpr, fxsave->st_space, 128); |
9749 | fpu->fcw = fxsave->cwd; | |
9750 | fpu->fsw = fxsave->swd; | |
9751 | fpu->ftwx = fxsave->twd; | |
9752 | fpu->last_opcode = fxsave->fop; | |
9753 | fpu->last_ip = fxsave->rip; | |
9754 | fpu->last_dp = fxsave->rdp; | |
0e96f31e | 9755 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); |
d0752060 | 9756 | |
1393123e | 9757 | vcpu_put(vcpu); |
d0752060 HB |
9758 | return 0; |
9759 | } | |
9760 | ||
9761 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
9762 | { | |
6a96bc7f CD |
9763 | struct fxregs_state *fxsave; |
9764 | ||
9765 | vcpu_load(vcpu); | |
9766 | ||
b666a4b6 | 9767 | fxsave = &vcpu->arch.guest_fpu->state.fxsave; |
d0752060 | 9768 | |
d0752060 HB |
9769 | memcpy(fxsave->st_space, fpu->fpr, 128); |
9770 | fxsave->cwd = fpu->fcw; | |
9771 | fxsave->swd = fpu->fsw; | |
9772 | fxsave->twd = fpu->ftwx; | |
9773 | fxsave->fop = fpu->last_opcode; | |
9774 | fxsave->rip = fpu->last_ip; | |
9775 | fxsave->rdp = fpu->last_dp; | |
0e96f31e | 9776 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); |
d0752060 | 9777 | |
6a96bc7f | 9778 | vcpu_put(vcpu); |
d0752060 HB |
9779 | return 0; |
9780 | } | |
9781 | ||
01643c51 KH |
9782 | static void store_regs(struct kvm_vcpu *vcpu) |
9783 | { | |
9784 | BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); | |
9785 | ||
9786 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) | |
9787 | __get_regs(vcpu, &vcpu->run->s.regs.regs); | |
9788 | ||
9789 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) | |
9790 | __get_sregs(vcpu, &vcpu->run->s.regs.sregs); | |
9791 | ||
9792 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) | |
9793 | kvm_vcpu_ioctl_x86_get_vcpu_events( | |
9794 | vcpu, &vcpu->run->s.regs.events); | |
9795 | } | |
9796 | ||
9797 | static int sync_regs(struct kvm_vcpu *vcpu) | |
9798 | { | |
9799 | if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS) | |
9800 | return -EINVAL; | |
9801 | ||
9802 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { | |
9803 | __set_regs(vcpu, &vcpu->run->s.regs.regs); | |
9804 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; | |
9805 | } | |
9806 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { | |
9807 | if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) | |
9808 | return -EINVAL; | |
9809 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; | |
9810 | } | |
9811 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { | |
9812 | if (kvm_vcpu_ioctl_x86_set_vcpu_events( | |
9813 | vcpu, &vcpu->run->s.regs.events)) | |
9814 | return -EINVAL; | |
9815 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; | |
9816 | } | |
9817 | ||
9818 | return 0; | |
9819 | } | |
9820 | ||
0ee6a517 | 9821 | static void fx_init(struct kvm_vcpu *vcpu) |
d0752060 | 9822 | { |
b666a4b6 | 9823 | fpstate_init(&vcpu->arch.guest_fpu->state); |
782511b0 | 9824 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
b666a4b6 | 9825 | vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv = |
df1daba7 | 9826 | host_xcr0 | XSTATE_COMPACTION_ENABLED; |
d0752060 | 9827 | |
2acf923e DC |
9828 | /* |
9829 | * Ensure guest xcr0 is valid for loading | |
9830 | */ | |
d91cab78 | 9831 | vcpu->arch.xcr0 = XFEATURE_MASK_FP; |
2acf923e | 9832 | |
ad312c7c | 9833 | vcpu->arch.cr0 |= X86_CR0_ET; |
d0752060 | 9834 | } |
d0752060 | 9835 | |
897cc38e | 9836 | int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) |
e9b11c17 | 9837 | { |
897cc38e SC |
9838 | if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) |
9839 | pr_warn_once("kvm: SMP vm created on host with unstable TSC; " | |
9840 | "guest TSC will not be reliable\n"); | |
7f1ea208 | 9841 | |
897cc38e | 9842 | return 0; |
e9b11c17 ZX |
9843 | } |
9844 | ||
e529ef66 | 9845 | int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) |
e9b11c17 | 9846 | { |
95a0d01e SC |
9847 | struct page *page; |
9848 | int r; | |
c447e76b | 9849 | |
95a0d01e SC |
9850 | if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) |
9851 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
9852 | else | |
9853 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; | |
c447e76b | 9854 | |
95a0d01e | 9855 | kvm_set_tsc_khz(vcpu, max_tsc_khz); |
c447e76b | 9856 | |
95a0d01e SC |
9857 | r = kvm_mmu_create(vcpu); |
9858 | if (r < 0) | |
9859 | return r; | |
9860 | ||
9861 | if (irqchip_in_kernel(vcpu->kvm)) { | |
95a0d01e SC |
9862 | r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); |
9863 | if (r < 0) | |
9864 | goto fail_mmu_destroy; | |
4e19c36f SS |
9865 | if (kvm_apicv_activated(vcpu->kvm)) |
9866 | vcpu->arch.apicv_active = true; | |
95a0d01e SC |
9867 | } else |
9868 | static_key_slow_inc(&kvm_no_apic_vcpu); | |
9869 | ||
9870 | r = -ENOMEM; | |
9871 | ||
9872 | page = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
9873 | if (!page) | |
9874 | goto fail_free_lapic; | |
9875 | vcpu->arch.pio_data = page_address(page); | |
9876 | ||
9877 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, | |
9878 | GFP_KERNEL_ACCOUNT); | |
9879 | if (!vcpu->arch.mce_banks) | |
9880 | goto fail_free_pio_data; | |
9881 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
9882 | ||
9883 | if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, | |
9884 | GFP_KERNEL_ACCOUNT)) | |
9885 | goto fail_free_mce_banks; | |
9886 | ||
c9b8b07c SC |
9887 | if (!alloc_emulate_ctxt(vcpu)) |
9888 | goto free_wbinvd_dirty_mask; | |
9889 | ||
95a0d01e SC |
9890 | vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache, |
9891 | GFP_KERNEL_ACCOUNT); | |
9892 | if (!vcpu->arch.user_fpu) { | |
9893 | pr_err("kvm: failed to allocate userspace's fpu\n"); | |
c9b8b07c | 9894 | goto free_emulate_ctxt; |
95a0d01e SC |
9895 | } |
9896 | ||
9897 | vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, | |
9898 | GFP_KERNEL_ACCOUNT); | |
9899 | if (!vcpu->arch.guest_fpu) { | |
9900 | pr_err("kvm: failed to allocate vcpu's fpu\n"); | |
9901 | goto free_user_fpu; | |
9902 | } | |
9903 | fx_init(vcpu); | |
9904 | ||
95a0d01e SC |
9905 | vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); |
9906 | ||
9907 | vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; | |
9908 | ||
9909 | kvm_async_pf_hash_reset(vcpu); | |
9910 | kvm_pmu_init(vcpu); | |
9911 | ||
9912 | vcpu->arch.pending_external_vector = -1; | |
9913 | vcpu->arch.preempted_in_kernel = false; | |
9914 | ||
9915 | kvm_hv_vcpu_init(vcpu); | |
9916 | ||
afaf0b2f | 9917 | r = kvm_x86_ops.vcpu_create(vcpu); |
95a0d01e SC |
9918 | if (r) |
9919 | goto free_guest_fpu; | |
e9b11c17 | 9920 | |
0cf9135b | 9921 | vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); |
e53d88af | 9922 | vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; |
19efffa2 | 9923 | kvm_vcpu_mtrr_init(vcpu); |
ec7660cc | 9924 | vcpu_load(vcpu); |
d28bc9dd | 9925 | kvm_vcpu_reset(vcpu, false); |
e1732991 | 9926 | kvm_init_mmu(vcpu, false); |
e9b11c17 | 9927 | vcpu_put(vcpu); |
ec7660cc | 9928 | return 0; |
95a0d01e SC |
9929 | |
9930 | free_guest_fpu: | |
9931 | kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu); | |
9932 | free_user_fpu: | |
9933 | kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); | |
c9b8b07c SC |
9934 | free_emulate_ctxt: |
9935 | kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); | |
95a0d01e SC |
9936 | free_wbinvd_dirty_mask: |
9937 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); | |
9938 | fail_free_mce_banks: | |
9939 | kfree(vcpu->arch.mce_banks); | |
9940 | fail_free_pio_data: | |
9941 | free_page((unsigned long)vcpu->arch.pio_data); | |
9942 | fail_free_lapic: | |
9943 | kvm_free_lapic(vcpu); | |
9944 | fail_mmu_destroy: | |
9945 | kvm_mmu_destroy(vcpu); | |
9946 | return r; | |
e9b11c17 ZX |
9947 | } |
9948 | ||
31928aa5 | 9949 | void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) |
42897d86 | 9950 | { |
332967a3 | 9951 | struct kvm *kvm = vcpu->kvm; |
42897d86 | 9952 | |
d3457c87 RK |
9953 | kvm_hv_vcpu_postcreate(vcpu); |
9954 | ||
ec7660cc | 9955 | if (mutex_lock_killable(&vcpu->mutex)) |
31928aa5 | 9956 | return; |
ec7660cc | 9957 | vcpu_load(vcpu); |
0c899c25 | 9958 | kvm_synchronize_tsc(vcpu, 0); |
42897d86 | 9959 | vcpu_put(vcpu); |
2d5ba19b MT |
9960 | |
9961 | /* poll control enabled by default */ | |
9962 | vcpu->arch.msr_kvm_poll_control = 1; | |
9963 | ||
ec7660cc | 9964 | mutex_unlock(&vcpu->mutex); |
42897d86 | 9965 | |
b34de572 WL |
9966 | if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0) |
9967 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
9968 | KVMCLOCK_SYNC_PERIOD); | |
42897d86 MT |
9969 | } |
9970 | ||
d40ccc62 | 9971 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 | 9972 | { |
4cbc418a | 9973 | struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache; |
95a0d01e | 9974 | int idx; |
344d9588 | 9975 | |
4cbc418a PB |
9976 | kvm_release_pfn(cache->pfn, cache->dirty, cache); |
9977 | ||
50b143e1 | 9978 | kvmclock_reset(vcpu); |
e9b11c17 | 9979 | |
afaf0b2f | 9980 | kvm_x86_ops.vcpu_free(vcpu); |
50b143e1 | 9981 | |
c9b8b07c | 9982 | kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); |
50b143e1 SC |
9983 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); |
9984 | kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); | |
9985 | kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu); | |
95a0d01e SC |
9986 | |
9987 | kvm_hv_vcpu_uninit(vcpu); | |
9988 | kvm_pmu_destroy(vcpu); | |
9989 | kfree(vcpu->arch.mce_banks); | |
9990 | kvm_free_lapic(vcpu); | |
9991 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
9992 | kvm_mmu_destroy(vcpu); | |
9993 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
9994 | free_page((unsigned long)vcpu->arch.pio_data); | |
255cbecf | 9995 | kvfree(vcpu->arch.cpuid_entries); |
95a0d01e SC |
9996 | if (!lapic_in_kernel(vcpu)) |
9997 | static_key_slow_dec(&kvm_no_apic_vcpu); | |
e9b11c17 ZX |
9998 | } |
9999 | ||
d28bc9dd | 10000 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
e9b11c17 | 10001 | { |
b7e31be3 RK |
10002 | kvm_lapic_reset(vcpu, init_event); |
10003 | ||
e69fab5d PB |
10004 | vcpu->arch.hflags = 0; |
10005 | ||
c43203ca | 10006 | vcpu->arch.smi_pending = 0; |
52797bf9 | 10007 | vcpu->arch.smi_count = 0; |
7460fb4a AK |
10008 | atomic_set(&vcpu->arch.nmi_queued, 0); |
10009 | vcpu->arch.nmi_pending = 0; | |
448fa4a9 | 10010 | vcpu->arch.nmi_injected = false; |
5f7552d4 NA |
10011 | kvm_clear_interrupt_queue(vcpu); |
10012 | kvm_clear_exception_queue(vcpu); | |
448fa4a9 | 10013 | |
42dbaa5a | 10014 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); |
ae561ede | 10015 | kvm_update_dr0123(vcpu); |
6f43ed01 | 10016 | vcpu->arch.dr6 = DR6_INIT; |
42dbaa5a | 10017 | vcpu->arch.dr7 = DR7_FIXED_1; |
c8639010 | 10018 | kvm_update_dr7(vcpu); |
42dbaa5a | 10019 | |
1119022c NA |
10020 | vcpu->arch.cr2 = 0; |
10021 | ||
3842d135 | 10022 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
2635b5c4 VK |
10023 | vcpu->arch.apf.msr_en_val = 0; |
10024 | vcpu->arch.apf.msr_int_val = 0; | |
c9aaa895 | 10025 | vcpu->arch.st.msr_val = 0; |
3842d135 | 10026 | |
12f9a48f GC |
10027 | kvmclock_reset(vcpu); |
10028 | ||
af585b92 GN |
10029 | kvm_clear_async_pf_completion_queue(vcpu); |
10030 | kvm_async_pf_hash_reset(vcpu); | |
10031 | vcpu->arch.apf.halted = false; | |
3842d135 | 10032 | |
a554d207 WL |
10033 | if (kvm_mpx_supported()) { |
10034 | void *mpx_state_buffer; | |
10035 | ||
10036 | /* | |
10037 | * To avoid have the INIT path from kvm_apic_has_events() that be | |
10038 | * called with loaded FPU and does not let userspace fix the state. | |
10039 | */ | |
f775b13e RR |
10040 | if (init_event) |
10041 | kvm_put_guest_fpu(vcpu); | |
b666a4b6 | 10042 | mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, |
abd16d68 | 10043 | XFEATURE_BNDREGS); |
a554d207 WL |
10044 | if (mpx_state_buffer) |
10045 | memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state)); | |
b666a4b6 | 10046 | mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, |
abd16d68 | 10047 | XFEATURE_BNDCSR); |
a554d207 WL |
10048 | if (mpx_state_buffer) |
10049 | memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr)); | |
f775b13e RR |
10050 | if (init_event) |
10051 | kvm_load_guest_fpu(vcpu); | |
a554d207 WL |
10052 | } |
10053 | ||
64d60670 | 10054 | if (!init_event) { |
d28bc9dd | 10055 | kvm_pmu_reset(vcpu); |
64d60670 | 10056 | vcpu->arch.smbase = 0x30000; |
db2336a8 | 10057 | |
db2336a8 | 10058 | vcpu->arch.msr_misc_features_enables = 0; |
a554d207 WL |
10059 | |
10060 | vcpu->arch.xcr0 = XFEATURE_MASK_FP; | |
64d60670 | 10061 | } |
f5132b01 | 10062 | |
66f7b72e JS |
10063 | memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); |
10064 | vcpu->arch.regs_avail = ~0; | |
10065 | vcpu->arch.regs_dirty = ~0; | |
10066 | ||
a554d207 WL |
10067 | vcpu->arch.ia32_xss = 0; |
10068 | ||
afaf0b2f | 10069 | kvm_x86_ops.vcpu_reset(vcpu, init_event); |
e9b11c17 ZX |
10070 | } |
10071 | ||
2b4a273b | 10072 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) |
66450a21 JK |
10073 | { |
10074 | struct kvm_segment cs; | |
10075 | ||
10076 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
10077 | cs.selector = vector << 8; | |
10078 | cs.base = vector << 12; | |
10079 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
10080 | kvm_rip_write(vcpu, 0); | |
e9b11c17 ZX |
10081 | } |
10082 | ||
13a34e06 | 10083 | int kvm_arch_hardware_enable(void) |
e9b11c17 | 10084 | { |
ca84d1a2 ZA |
10085 | struct kvm *kvm; |
10086 | struct kvm_vcpu *vcpu; | |
10087 | int i; | |
0dd6a6ed ZA |
10088 | int ret; |
10089 | u64 local_tsc; | |
10090 | u64 max_tsc = 0; | |
10091 | bool stable, backwards_tsc = false; | |
18863bdd | 10092 | |
7e34fbd0 | 10093 | kvm_user_return_msr_cpu_online(); |
afaf0b2f | 10094 | ret = kvm_x86_ops.hardware_enable(); |
0dd6a6ed ZA |
10095 | if (ret != 0) |
10096 | return ret; | |
10097 | ||
4ea1636b | 10098 | local_tsc = rdtsc(); |
b0c39dc6 | 10099 | stable = !kvm_check_tsc_unstable(); |
0dd6a6ed ZA |
10100 | list_for_each_entry(kvm, &vm_list, vm_list) { |
10101 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
10102 | if (!stable && vcpu->cpu == smp_processor_id()) | |
105b21bb | 10103 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
10104 | if (stable && vcpu->arch.last_host_tsc > local_tsc) { |
10105 | backwards_tsc = true; | |
10106 | if (vcpu->arch.last_host_tsc > max_tsc) | |
10107 | max_tsc = vcpu->arch.last_host_tsc; | |
10108 | } | |
10109 | } | |
10110 | } | |
10111 | ||
10112 | /* | |
10113 | * Sometimes, even reliable TSCs go backwards. This happens on | |
10114 | * platforms that reset TSC during suspend or hibernate actions, but | |
10115 | * maintain synchronization. We must compensate. Fortunately, we can | |
10116 | * detect that condition here, which happens early in CPU bringup, | |
10117 | * before any KVM threads can be running. Unfortunately, we can't | |
10118 | * bring the TSCs fully up to date with real time, as we aren't yet far | |
10119 | * enough into CPU bringup that we know how much real time has actually | |
9285ec4c | 10120 | * elapsed; our helper function, ktime_get_boottime_ns() will be using boot |
0dd6a6ed ZA |
10121 | * variables that haven't been updated yet. |
10122 | * | |
10123 | * So we simply find the maximum observed TSC above, then record the | |
10124 | * adjustment to TSC in each VCPU. When the VCPU later gets loaded, | |
10125 | * the adjustment will be applied. Note that we accumulate | |
10126 | * adjustments, in case multiple suspend cycles happen before some VCPU | |
10127 | * gets a chance to run again. In the event that no KVM threads get a | |
10128 | * chance to run, we will miss the entire elapsed period, as we'll have | |
10129 | * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may | |
10130 | * loose cycle time. This isn't too big a deal, since the loss will be | |
10131 | * uniform across all VCPUs (not to mention the scenario is extremely | |
10132 | * unlikely). It is possible that a second hibernate recovery happens | |
10133 | * much faster than a first, causing the observed TSC here to be | |
10134 | * smaller; this would require additional padding adjustment, which is | |
10135 | * why we set last_host_tsc to the local tsc observed here. | |
10136 | * | |
10137 | * N.B. - this code below runs only on platforms with reliable TSC, | |
10138 | * as that is the only way backwards_tsc is set above. Also note | |
10139 | * that this runs for ALL vcpus, which is not a bug; all VCPUs should | |
10140 | * have the same delta_cyc adjustment applied if backwards_tsc | |
10141 | * is detected. Note further, this adjustment is only done once, | |
10142 | * as we reset last_host_tsc on all VCPUs to stop this from being | |
10143 | * called multiple times (one for each physical CPU bringup). | |
10144 | * | |
4a969980 | 10145 | * Platforms with unreliable TSCs don't have to deal with this, they |
0dd6a6ed ZA |
10146 | * will be compensated by the logic in vcpu_load, which sets the TSC to |
10147 | * catchup mode. This will catchup all VCPUs to real time, but cannot | |
10148 | * guarantee that they stay in perfect synchronization. | |
10149 | */ | |
10150 | if (backwards_tsc) { | |
10151 | u64 delta_cyc = max_tsc - local_tsc; | |
10152 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
a826faf1 | 10153 | kvm->arch.backwards_tsc_observed = true; |
0dd6a6ed ZA |
10154 | kvm_for_each_vcpu(i, vcpu, kvm) { |
10155 | vcpu->arch.tsc_offset_adjustment += delta_cyc; | |
10156 | vcpu->arch.last_host_tsc = local_tsc; | |
105b21bb | 10157 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
10158 | } |
10159 | ||
10160 | /* | |
10161 | * We have to disable TSC offset matching.. if you were | |
10162 | * booting a VM while issuing an S4 host suspend.... | |
10163 | * you may have some problem. Solving this issue is | |
10164 | * left as an exercise to the reader. | |
10165 | */ | |
10166 | kvm->arch.last_tsc_nsec = 0; | |
10167 | kvm->arch.last_tsc_write = 0; | |
10168 | } | |
10169 | ||
10170 | } | |
10171 | return 0; | |
e9b11c17 ZX |
10172 | } |
10173 | ||
13a34e06 | 10174 | void kvm_arch_hardware_disable(void) |
e9b11c17 | 10175 | { |
afaf0b2f | 10176 | kvm_x86_ops.hardware_disable(); |
13a34e06 | 10177 | drop_user_return_notifiers(); |
e9b11c17 ZX |
10178 | } |
10179 | ||
b9904085 | 10180 | int kvm_arch_hardware_setup(void *opaque) |
e9b11c17 | 10181 | { |
d008dfdb | 10182 | struct kvm_x86_init_ops *ops = opaque; |
9e9c3fe4 NA |
10183 | int r; |
10184 | ||
91661989 SC |
10185 | rdmsrl_safe(MSR_EFER, &host_efer); |
10186 | ||
408e9a31 PB |
10187 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
10188 | rdmsrl(MSR_IA32_XSS, host_xss); | |
10189 | ||
d008dfdb | 10190 | r = ops->hardware_setup(); |
9e9c3fe4 NA |
10191 | if (r != 0) |
10192 | return r; | |
10193 | ||
afaf0b2f | 10194 | memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops)); |
69c6f69a | 10195 | |
408e9a31 PB |
10196 | if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES)) |
10197 | supported_xss = 0; | |
10198 | ||
139f7425 PB |
10199 | #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f) |
10200 | cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_); | |
10201 | #undef __kvm_cpu_cap_has | |
b11306b5 | 10202 | |
35181e86 HZ |
10203 | if (kvm_has_tsc_control) { |
10204 | /* | |
10205 | * Make sure the user can only configure tsc_khz values that | |
10206 | * fit into a signed integer. | |
273ba457 | 10207 | * A min value is not calculated because it will always |
35181e86 HZ |
10208 | * be 1 on all machines. |
10209 | */ | |
10210 | u64 max = min(0x7fffffffULL, | |
10211 | __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); | |
10212 | kvm_max_guest_tsc_khz = max; | |
10213 | ||
ad721883 | 10214 | kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; |
35181e86 | 10215 | } |
ad721883 | 10216 | |
9e9c3fe4 NA |
10217 | kvm_init_msr_list(); |
10218 | return 0; | |
e9b11c17 ZX |
10219 | } |
10220 | ||
10221 | void kvm_arch_hardware_unsetup(void) | |
10222 | { | |
afaf0b2f | 10223 | kvm_x86_ops.hardware_unsetup(); |
e9b11c17 ZX |
10224 | } |
10225 | ||
b9904085 | 10226 | int kvm_arch_check_processor_compat(void *opaque) |
e9b11c17 | 10227 | { |
f1cdecf5 | 10228 | struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); |
d008dfdb | 10229 | struct kvm_x86_init_ops *ops = opaque; |
f1cdecf5 SC |
10230 | |
10231 | WARN_ON(!irqs_disabled()); | |
10232 | ||
139f7425 PB |
10233 | if (__cr4_reserved_bits(cpu_has, c) != |
10234 | __cr4_reserved_bits(cpu_has, &boot_cpu_data)) | |
f1cdecf5 SC |
10235 | return -EIO; |
10236 | ||
d008dfdb | 10237 | return ops->check_processor_compatibility(); |
d71ba788 PB |
10238 | } |
10239 | ||
10240 | bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) | |
10241 | { | |
10242 | return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; | |
10243 | } | |
10244 | EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); | |
10245 | ||
10246 | bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) | |
10247 | { | |
10248 | return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; | |
e9b11c17 ZX |
10249 | } |
10250 | ||
54e9818f | 10251 | struct static_key kvm_no_apic_vcpu __read_mostly; |
bce87cce | 10252 | EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu); |
54e9818f | 10253 | |
e790d9ef RK |
10254 | void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) |
10255 | { | |
b35e5548 LX |
10256 | struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); |
10257 | ||
c595ceee | 10258 | vcpu->arch.l1tf_flush_l1d = true; |
b35e5548 LX |
10259 | if (pmu->version && unlikely(pmu->event_count)) { |
10260 | pmu->need_cleanup = true; | |
10261 | kvm_make_request(KVM_REQ_PMU, vcpu); | |
10262 | } | |
afaf0b2f | 10263 | kvm_x86_ops.sched_in(vcpu, cpu); |
e790d9ef RK |
10264 | } |
10265 | ||
562b6b08 SC |
10266 | void kvm_arch_free_vm(struct kvm *kvm) |
10267 | { | |
10268 | kfree(kvm->arch.hyperv.hv_pa_pg); | |
10269 | vfree(kvm); | |
e790d9ef RK |
10270 | } |
10271 | ||
562b6b08 | 10272 | |
e08b9637 | 10273 | int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) |
d19a9cd2 | 10274 | { |
e08b9637 CO |
10275 | if (type) |
10276 | return -EINVAL; | |
10277 | ||
6ef768fa | 10278 | INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); |
f05e70ac | 10279 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
10605204 | 10280 | INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); |
1aa9b957 | 10281 | INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages); |
4d5c5d0f | 10282 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
e0f0bbc5 | 10283 | atomic_set(&kvm->arch.noncoherent_dma_count, 0); |
d19a9cd2 | 10284 | |
5550af4d SY |
10285 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
10286 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
7a84428a AW |
10287 | /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ |
10288 | set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, | |
10289 | &kvm->arch.irq_sources_bitmap); | |
5550af4d | 10290 | |
038f8c11 | 10291 | raw_spin_lock_init(&kvm->arch.tsc_write_lock); |
1e08ec4a | 10292 | mutex_init(&kvm->arch.apic_map_lock); |
d828199e MT |
10293 | spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); |
10294 | ||
8171cd68 | 10295 | kvm->arch.kvmclock_offset = -get_kvmclock_base_ns(); |
d828199e | 10296 | pvclock_update_vm_gtod_copy(kvm); |
53f658b3 | 10297 | |
6fbbde9a DS |
10298 | kvm->arch.guest_can_read_msr_platform_info = true; |
10299 | ||
7e44e449 | 10300 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); |
332967a3 | 10301 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); |
7e44e449 | 10302 | |
cbc0236a | 10303 | kvm_hv_init_vm(kvm); |
0eb05bf2 | 10304 | kvm_page_track_init(kvm); |
13d268ca | 10305 | kvm_mmu_init_vm(kvm); |
0eb05bf2 | 10306 | |
afaf0b2f | 10307 | return kvm_x86_ops.vm_init(kvm); |
d19a9cd2 ZX |
10308 | } |
10309 | ||
1aa9b957 JS |
10310 | int kvm_arch_post_init_vm(struct kvm *kvm) |
10311 | { | |
10312 | return kvm_mmu_post_init_vm(kvm); | |
10313 | } | |
10314 | ||
d19a9cd2 ZX |
10315 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) |
10316 | { | |
ec7660cc | 10317 | vcpu_load(vcpu); |
d19a9cd2 ZX |
10318 | kvm_mmu_unload(vcpu); |
10319 | vcpu_put(vcpu); | |
10320 | } | |
10321 | ||
10322 | static void kvm_free_vcpus(struct kvm *kvm) | |
10323 | { | |
10324 | unsigned int i; | |
988a2cae | 10325 | struct kvm_vcpu *vcpu; |
d19a9cd2 ZX |
10326 | |
10327 | /* | |
10328 | * Unpin any mmu pages first. | |
10329 | */ | |
af585b92 GN |
10330 | kvm_for_each_vcpu(i, vcpu, kvm) { |
10331 | kvm_clear_async_pf_completion_queue(vcpu); | |
988a2cae | 10332 | kvm_unload_vcpu_mmu(vcpu); |
af585b92 | 10333 | } |
988a2cae | 10334 | kvm_for_each_vcpu(i, vcpu, kvm) |
4543bdc0 | 10335 | kvm_vcpu_destroy(vcpu); |
988a2cae GN |
10336 | |
10337 | mutex_lock(&kvm->lock); | |
10338 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
10339 | kvm->vcpus[i] = NULL; | |
d19a9cd2 | 10340 | |
988a2cae GN |
10341 | atomic_set(&kvm->online_vcpus, 0); |
10342 | mutex_unlock(&kvm->lock); | |
d19a9cd2 ZX |
10343 | } |
10344 | ||
ad8ba2cd SY |
10345 | void kvm_arch_sync_events(struct kvm *kvm) |
10346 | { | |
332967a3 | 10347 | cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); |
7e44e449 | 10348 | cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); |
aea924f6 | 10349 | kvm_free_pit(kvm); |
ad8ba2cd SY |
10350 | } |
10351 | ||
1d8007bd | 10352 | int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) |
9da0e4d5 PB |
10353 | { |
10354 | int i, r; | |
3f649ab7 | 10355 | unsigned long hva, old_npages; |
f0d648bd | 10356 | struct kvm_memslots *slots = kvm_memslots(kvm); |
0577d1ab | 10357 | struct kvm_memory_slot *slot; |
9da0e4d5 PB |
10358 | |
10359 | /* Called with kvm->slots_lock held. */ | |
1d8007bd PB |
10360 | if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) |
10361 | return -EINVAL; | |
9da0e4d5 | 10362 | |
f0d648bd PB |
10363 | slot = id_to_memslot(slots, id); |
10364 | if (size) { | |
0577d1ab | 10365 | if (slot && slot->npages) |
f0d648bd PB |
10366 | return -EEXIST; |
10367 | ||
10368 | /* | |
10369 | * MAP_SHARED to prevent internal slot pages from being moved | |
10370 | * by fork()/COW. | |
10371 | */ | |
10372 | hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, | |
10373 | MAP_SHARED | MAP_ANONYMOUS, 0); | |
10374 | if (IS_ERR((void *)hva)) | |
10375 | return PTR_ERR((void *)hva); | |
10376 | } else { | |
0577d1ab | 10377 | if (!slot || !slot->npages) |
f0d648bd PB |
10378 | return 0; |
10379 | ||
0577d1ab | 10380 | old_npages = slot->npages; |
e0135a10 | 10381 | hva = 0; |
f0d648bd PB |
10382 | } |
10383 | ||
9da0e4d5 | 10384 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
1d8007bd | 10385 | struct kvm_userspace_memory_region m; |
9da0e4d5 | 10386 | |
1d8007bd PB |
10387 | m.slot = id | (i << 16); |
10388 | m.flags = 0; | |
10389 | m.guest_phys_addr = gpa; | |
f0d648bd | 10390 | m.userspace_addr = hva; |
1d8007bd | 10391 | m.memory_size = size; |
9da0e4d5 PB |
10392 | r = __kvm_set_memory_region(kvm, &m); |
10393 | if (r < 0) | |
10394 | return r; | |
10395 | } | |
10396 | ||
103c763c | 10397 | if (!size) |
0577d1ab | 10398 | vm_munmap(hva, old_npages * PAGE_SIZE); |
f0d648bd | 10399 | |
9da0e4d5 PB |
10400 | return 0; |
10401 | } | |
10402 | EXPORT_SYMBOL_GPL(__x86_set_memory_region); | |
10403 | ||
1aa9b957 JS |
10404 | void kvm_arch_pre_destroy_vm(struct kvm *kvm) |
10405 | { | |
10406 | kvm_mmu_pre_destroy_vm(kvm); | |
10407 | } | |
10408 | ||
d19a9cd2 ZX |
10409 | void kvm_arch_destroy_vm(struct kvm *kvm) |
10410 | { | |
1a155254 AG |
10411 | u32 i; |
10412 | ||
27469d29 AH |
10413 | if (current->mm == kvm->mm) { |
10414 | /* | |
10415 | * Free memory regions allocated on behalf of userspace, | |
10416 | * unless the the memory map has changed due to process exit | |
10417 | * or fd copying. | |
10418 | */ | |
6a3c623b PX |
10419 | mutex_lock(&kvm->slots_lock); |
10420 | __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, | |
10421 | 0, 0); | |
10422 | __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, | |
10423 | 0, 0); | |
10424 | __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); | |
10425 | mutex_unlock(&kvm->slots_lock); | |
27469d29 | 10426 | } |
afaf0b2f SC |
10427 | if (kvm_x86_ops.vm_destroy) |
10428 | kvm_x86_ops.vm_destroy(kvm); | |
1a155254 AG |
10429 | for (i = 0; i < kvm->arch.msr_filter.count; i++) |
10430 | kfree(kvm->arch.msr_filter.ranges[i].bitmap); | |
c761159c PX |
10431 | kvm_pic_destroy(kvm); |
10432 | kvm_ioapic_destroy(kvm); | |
d19a9cd2 | 10433 | kvm_free_vcpus(kvm); |
af1bae54 | 10434 | kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); |
66bb8a06 | 10435 | kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); |
13d268ca | 10436 | kvm_mmu_uninit_vm(kvm); |
2beb6dad | 10437 | kvm_page_track_cleanup(kvm); |
cbc0236a | 10438 | kvm_hv_destroy_vm(kvm); |
d19a9cd2 | 10439 | } |
0de10343 | 10440 | |
e96c81ee | 10441 | void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) |
db3fe4eb TY |
10442 | { |
10443 | int i; | |
10444 | ||
d89cc617 | 10445 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
e96c81ee SC |
10446 | kvfree(slot->arch.rmap[i]); |
10447 | slot->arch.rmap[i] = NULL; | |
10448 | ||
d89cc617 TY |
10449 | if (i == 0) |
10450 | continue; | |
10451 | ||
e96c81ee SC |
10452 | kvfree(slot->arch.lpage_info[i - 1]); |
10453 | slot->arch.lpage_info[i - 1] = NULL; | |
db3fe4eb | 10454 | } |
21ebbeda | 10455 | |
e96c81ee | 10456 | kvm_page_track_free_memslot(slot); |
db3fe4eb TY |
10457 | } |
10458 | ||
0dab98b7 SC |
10459 | static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot, |
10460 | unsigned long npages) | |
db3fe4eb TY |
10461 | { |
10462 | int i; | |
10463 | ||
edd4fa37 SC |
10464 | /* |
10465 | * Clear out the previous array pointers for the KVM_MR_MOVE case. The | |
10466 | * old arrays will be freed by __kvm_set_memory_region() if installing | |
10467 | * the new memslot is successful. | |
10468 | */ | |
10469 | memset(&slot->arch, 0, sizeof(slot->arch)); | |
10470 | ||
d89cc617 | 10471 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
92f94f1e | 10472 | struct kvm_lpage_info *linfo; |
db3fe4eb TY |
10473 | unsigned long ugfn; |
10474 | int lpages; | |
d89cc617 | 10475 | int level = i + 1; |
db3fe4eb TY |
10476 | |
10477 | lpages = gfn_to_index(slot->base_gfn + npages - 1, | |
10478 | slot->base_gfn, level) + 1; | |
10479 | ||
d89cc617 | 10480 | slot->arch.rmap[i] = |
778e1cdd | 10481 | kvcalloc(lpages, sizeof(*slot->arch.rmap[i]), |
254272ce | 10482 | GFP_KERNEL_ACCOUNT); |
d89cc617 | 10483 | if (!slot->arch.rmap[i]) |
77d11309 | 10484 | goto out_free; |
d89cc617 TY |
10485 | if (i == 0) |
10486 | continue; | |
77d11309 | 10487 | |
254272ce | 10488 | linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); |
92f94f1e | 10489 | if (!linfo) |
db3fe4eb TY |
10490 | goto out_free; |
10491 | ||
92f94f1e XG |
10492 | slot->arch.lpage_info[i - 1] = linfo; |
10493 | ||
db3fe4eb | 10494 | if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 10495 | linfo[0].disallow_lpage = 1; |
db3fe4eb | 10496 | if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 10497 | linfo[lpages - 1].disallow_lpage = 1; |
db3fe4eb TY |
10498 | ugfn = slot->userspace_addr >> PAGE_SHIFT; |
10499 | /* | |
10500 | * If the gfn and userspace address are not aligned wrt each | |
600087b6 | 10501 | * other, disable large page support for this slot. |
db3fe4eb | 10502 | */ |
600087b6 | 10503 | if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) { |
db3fe4eb TY |
10504 | unsigned long j; |
10505 | ||
10506 | for (j = 0; j < lpages; ++j) | |
92f94f1e | 10507 | linfo[j].disallow_lpage = 1; |
db3fe4eb TY |
10508 | } |
10509 | } | |
10510 | ||
21ebbeda XG |
10511 | if (kvm_page_track_create_memslot(slot, npages)) |
10512 | goto out_free; | |
10513 | ||
db3fe4eb TY |
10514 | return 0; |
10515 | ||
10516 | out_free: | |
d89cc617 | 10517 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
548ef284 | 10518 | kvfree(slot->arch.rmap[i]); |
d89cc617 TY |
10519 | slot->arch.rmap[i] = NULL; |
10520 | if (i == 0) | |
10521 | continue; | |
10522 | ||
548ef284 | 10523 | kvfree(slot->arch.lpage_info[i - 1]); |
d89cc617 | 10524 | slot->arch.lpage_info[i - 1] = NULL; |
db3fe4eb TY |
10525 | } |
10526 | return -ENOMEM; | |
10527 | } | |
10528 | ||
15248258 | 10529 | void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) |
e59dbe09 | 10530 | { |
91724814 BO |
10531 | struct kvm_vcpu *vcpu; |
10532 | int i; | |
10533 | ||
e6dff7d1 TY |
10534 | /* |
10535 | * memslots->generation has been incremented. | |
10536 | * mmio generation may have reached its maximum value. | |
10537 | */ | |
15248258 | 10538 | kvm_mmu_invalidate_mmio_sptes(kvm, gen); |
91724814 BO |
10539 | |
10540 | /* Force re-initialization of steal_time cache */ | |
10541 | kvm_for_each_vcpu(i, vcpu, kvm) | |
10542 | kvm_vcpu_kick(vcpu); | |
e59dbe09 TY |
10543 | } |
10544 | ||
f7784b8e MT |
10545 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
10546 | struct kvm_memory_slot *memslot, | |
09170a49 | 10547 | const struct kvm_userspace_memory_region *mem, |
7b6195a9 | 10548 | enum kvm_mr_change change) |
0de10343 | 10549 | { |
0dab98b7 SC |
10550 | if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) |
10551 | return kvm_alloc_memslot_metadata(memslot, | |
10552 | mem->memory_size >> PAGE_SHIFT); | |
f7784b8e MT |
10553 | return 0; |
10554 | } | |
10555 | ||
88178fd4 | 10556 | static void kvm_mmu_slot_apply_flags(struct kvm *kvm, |
3741679b AY |
10557 | struct kvm_memory_slot *old, |
10558 | struct kvm_memory_slot *new, | |
10559 | enum kvm_mr_change change) | |
88178fd4 | 10560 | { |
3741679b AY |
10561 | /* |
10562 | * Nothing to do for RO slots or CREATE/MOVE/DELETE of a slot. | |
10563 | * See comments below. | |
10564 | */ | |
10565 | if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY)) | |
88178fd4 | 10566 | return; |
88178fd4 KH |
10567 | |
10568 | /* | |
3741679b AY |
10569 | * Dirty logging tracks sptes in 4k granularity, meaning that large |
10570 | * sptes have to be split. If live migration is successful, the guest | |
10571 | * in the source machine will be destroyed and large sptes will be | |
10572 | * created in the destination. However, if the guest continues to run | |
10573 | * in the source machine (for example if live migration fails), small | |
10574 | * sptes will remain around and cause bad performance. | |
88178fd4 | 10575 | * |
3741679b AY |
10576 | * Scan sptes if dirty logging has been stopped, dropping those |
10577 | * which can be collapsed into a single large-page spte. Later | |
10578 | * page faults will create the large-page sptes. | |
88178fd4 | 10579 | * |
3741679b AY |
10580 | * There is no need to do this in any of the following cases: |
10581 | * CREATE: No dirty mappings will already exist. | |
10582 | * MOVE/DELETE: The old mappings will already have been cleaned up by | |
10583 | * kvm_arch_flush_shadow_memslot() | |
10584 | */ | |
10585 | if ((old->flags & KVM_MEM_LOG_DIRTY_PAGES) && | |
10586 | !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) | |
10587 | kvm_mmu_zap_collapsible_sptes(kvm, new); | |
10588 | ||
10589 | /* | |
10590 | * Enable or disable dirty logging for the slot. | |
88178fd4 | 10591 | * |
3741679b AY |
10592 | * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of the old |
10593 | * slot have been zapped so no dirty logging updates are needed for | |
10594 | * the old slot. | |
10595 | * For KVM_MR_CREATE and KVM_MR_MOVE, once the new slot is visible | |
10596 | * any mappings that might be created in it will consume the | |
10597 | * properties of the new slot and do not need to be updated here. | |
88178fd4 | 10598 | * |
3741679b AY |
10599 | * When PML is enabled, the kvm_x86_ops dirty logging hooks are |
10600 | * called to enable/disable dirty logging. | |
88178fd4 | 10601 | * |
3741679b AY |
10602 | * When disabling dirty logging with PML enabled, the D-bit is set |
10603 | * for sptes in the slot in order to prevent unnecessary GPA | |
10604 | * logging in the PML buffer (and potential PML buffer full VMEXIT). | |
10605 | * This guarantees leaving PML enabled for the guest's lifetime | |
10606 | * won't have any additional overhead from PML when the guest is | |
10607 | * running with dirty logging disabled. | |
88178fd4 | 10608 | * |
3741679b AY |
10609 | * When enabling dirty logging, large sptes are write-protected |
10610 | * so they can be split on first write. New large sptes cannot | |
10611 | * be created for this slot until the end of the logging. | |
88178fd4 | 10612 | * See the comments in fast_page_fault(). |
3741679b AY |
10613 | * For small sptes, nothing is done if the dirty log is in the |
10614 | * initial-all-set state. Otherwise, depending on whether pml | |
10615 | * is enabled the D-bit or the W-bit will be cleared. | |
88178fd4 KH |
10616 | */ |
10617 | if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { | |
afaf0b2f SC |
10618 | if (kvm_x86_ops.slot_enable_log_dirty) { |
10619 | kvm_x86_ops.slot_enable_log_dirty(kvm, new); | |
3c9bd400 JZ |
10620 | } else { |
10621 | int level = | |
10622 | kvm_dirty_log_manual_protect_and_init_set(kvm) ? | |
3bae0459 | 10623 | PG_LEVEL_2M : PG_LEVEL_4K; |
3c9bd400 JZ |
10624 | |
10625 | /* | |
10626 | * If we're with initial-all-set, we don't need | |
10627 | * to write protect any small page because | |
10628 | * they're reported as dirty already. However | |
10629 | * we still need to write-protect huge pages | |
10630 | * so that the page split can happen lazily on | |
10631 | * the first write to the huge page. | |
10632 | */ | |
10633 | kvm_mmu_slot_remove_write_access(kvm, new, level); | |
10634 | } | |
88178fd4 | 10635 | } else { |
afaf0b2f SC |
10636 | if (kvm_x86_ops.slot_disable_log_dirty) |
10637 | kvm_x86_ops.slot_disable_log_dirty(kvm, new); | |
88178fd4 KH |
10638 | } |
10639 | } | |
10640 | ||
f7784b8e | 10641 | void kvm_arch_commit_memory_region(struct kvm *kvm, |
09170a49 | 10642 | const struct kvm_userspace_memory_region *mem, |
9d4c197c | 10643 | struct kvm_memory_slot *old, |
f36f3f28 | 10644 | const struct kvm_memory_slot *new, |
8482644a | 10645 | enum kvm_mr_change change) |
f7784b8e | 10646 | { |
48c0e4e9 | 10647 | if (!kvm->arch.n_requested_mmu_pages) |
4d66623c WY |
10648 | kvm_mmu_change_mmu_pages(kvm, |
10649 | kvm_mmu_calculate_default_mmu_pages(kvm)); | |
1c91cad4 | 10650 | |
3ea3b7fa | 10651 | /* |
f36f3f28 | 10652 | * FIXME: const-ify all uses of struct kvm_memory_slot. |
c972f3b1 | 10653 | */ |
3741679b | 10654 | kvm_mmu_slot_apply_flags(kvm, old, (struct kvm_memory_slot *) new, change); |
21198846 SC |
10655 | |
10656 | /* Free the arrays associated with the old memslot. */ | |
10657 | if (change == KVM_MR_MOVE) | |
e96c81ee | 10658 | kvm_arch_free_memslot(kvm, old); |
0de10343 | 10659 | } |
1d737c8a | 10660 | |
2df72e9b | 10661 | void kvm_arch_flush_shadow_all(struct kvm *kvm) |
34d4cb8f | 10662 | { |
7390de1e | 10663 | kvm_mmu_zap_all(kvm); |
34d4cb8f MT |
10664 | } |
10665 | ||
2df72e9b MT |
10666 | void kvm_arch_flush_shadow_memslot(struct kvm *kvm, |
10667 | struct kvm_memory_slot *slot) | |
10668 | { | |
ae7cd873 | 10669 | kvm_page_track_flush_slot(kvm, slot); |
2df72e9b MT |
10670 | } |
10671 | ||
e6c67d8c LA |
10672 | static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) |
10673 | { | |
10674 | return (is_guest_mode(vcpu) && | |
afaf0b2f SC |
10675 | kvm_x86_ops.guest_apic_has_interrupt && |
10676 | kvm_x86_ops.guest_apic_has_interrupt(vcpu)); | |
e6c67d8c LA |
10677 | } |
10678 | ||
5d9bc648 PB |
10679 | static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) |
10680 | { | |
10681 | if (!list_empty_careful(&vcpu->async_pf.done)) | |
10682 | return true; | |
10683 | ||
10684 | if (kvm_apic_has_events(vcpu)) | |
10685 | return true; | |
10686 | ||
10687 | if (vcpu->arch.pv.pv_unhalted) | |
10688 | return true; | |
10689 | ||
a5f01f8e WL |
10690 | if (vcpu->arch.exception.pending) |
10691 | return true; | |
10692 | ||
47a66eed Z |
10693 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || |
10694 | (vcpu->arch.nmi_pending && | |
c300ab9f | 10695 | kvm_x86_ops.nmi_allowed(vcpu, false))) |
5d9bc648 PB |
10696 | return true; |
10697 | ||
47a66eed | 10698 | if (kvm_test_request(KVM_REQ_SMI, vcpu) || |
a9fa7cb6 | 10699 | (vcpu->arch.smi_pending && |
c300ab9f | 10700 | kvm_x86_ops.smi_allowed(vcpu, false))) |
73917739 PB |
10701 | return true; |
10702 | ||
5d9bc648 | 10703 | if (kvm_arch_interrupt_allowed(vcpu) && |
e6c67d8c LA |
10704 | (kvm_cpu_has_interrupt(vcpu) || |
10705 | kvm_guest_apic_has_interrupt(vcpu))) | |
5d9bc648 PB |
10706 | return true; |
10707 | ||
1f4b34f8 AS |
10708 | if (kvm_hv_has_stimer_pending(vcpu)) |
10709 | return true; | |
10710 | ||
d2060bd4 SC |
10711 | if (is_guest_mode(vcpu) && |
10712 | kvm_x86_ops.nested_ops->hv_timer_pending && | |
10713 | kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) | |
10714 | return true; | |
10715 | ||
5d9bc648 PB |
10716 | return false; |
10717 | } | |
10718 | ||
1d737c8a ZX |
10719 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
10720 | { | |
5d9bc648 | 10721 | return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); |
1d737c8a | 10722 | } |
5736199a | 10723 | |
17e433b5 WL |
10724 | bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) |
10725 | { | |
10726 | if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) | |
10727 | return true; | |
10728 | ||
10729 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || | |
10730 | kvm_test_request(KVM_REQ_SMI, vcpu) || | |
10731 | kvm_test_request(KVM_REQ_EVENT, vcpu)) | |
10732 | return true; | |
10733 | ||
afaf0b2f | 10734 | if (vcpu->arch.apicv_active && kvm_x86_ops.dy_apicv_has_pending_interrupt(vcpu)) |
17e433b5 WL |
10735 | return true; |
10736 | ||
10737 | return false; | |
10738 | } | |
10739 | ||
199b5763 LM |
10740 | bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) |
10741 | { | |
de63ad4c | 10742 | return vcpu->arch.preempted_in_kernel; |
199b5763 LM |
10743 | } |
10744 | ||
b6d33834 | 10745 | int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) |
5736199a | 10746 | { |
b6d33834 | 10747 | return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; |
5736199a | 10748 | } |
78646121 GN |
10749 | |
10750 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
10751 | { | |
c300ab9f | 10752 | return kvm_x86_ops.interrupt_allowed(vcpu, false); |
78646121 | 10753 | } |
229456fc | 10754 | |
82b32774 | 10755 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) |
f92653ee | 10756 | { |
82b32774 NA |
10757 | if (is_64_bit_mode(vcpu)) |
10758 | return kvm_rip_read(vcpu); | |
10759 | return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + | |
10760 | kvm_rip_read(vcpu)); | |
10761 | } | |
10762 | EXPORT_SYMBOL_GPL(kvm_get_linear_rip); | |
f92653ee | 10763 | |
82b32774 NA |
10764 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) |
10765 | { | |
10766 | return kvm_get_linear_rip(vcpu) == linear_rip; | |
f92653ee JK |
10767 | } |
10768 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
10769 | ||
94fe45da JK |
10770 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
10771 | { | |
10772 | unsigned long rflags; | |
10773 | ||
afaf0b2f | 10774 | rflags = kvm_x86_ops.get_rflags(vcpu); |
94fe45da | 10775 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
c310bac5 | 10776 | rflags &= ~X86_EFLAGS_TF; |
94fe45da JK |
10777 | return rflags; |
10778 | } | |
10779 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
10780 | ||
6addfc42 | 10781 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) |
94fe45da JK |
10782 | { |
10783 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
f92653ee | 10784 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) |
c310bac5 | 10785 | rflags |= X86_EFLAGS_TF; |
afaf0b2f | 10786 | kvm_x86_ops.set_rflags(vcpu, rflags); |
6addfc42 PB |
10787 | } |
10788 | ||
10789 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
10790 | { | |
10791 | __kvm_set_rflags(vcpu, rflags); | |
3842d135 | 10792 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
94fe45da JK |
10793 | } |
10794 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
10795 | ||
56028d08 GN |
10796 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) |
10797 | { | |
10798 | int r; | |
10799 | ||
44dd3ffa | 10800 | if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) || |
f2e10669 | 10801 | work->wakeup_all) |
56028d08 GN |
10802 | return; |
10803 | ||
10804 | r = kvm_mmu_reload(vcpu); | |
10805 | if (unlikely(r)) | |
10806 | return; | |
10807 | ||
44dd3ffa | 10808 | if (!vcpu->arch.mmu->direct_map && |
d8dd54e0 | 10809 | work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu)) |
fb67e14f XG |
10810 | return; |
10811 | ||
7a02674d | 10812 | kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true); |
56028d08 GN |
10813 | } |
10814 | ||
af585b92 GN |
10815 | static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) |
10816 | { | |
dd03bcaa PX |
10817 | BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU)); |
10818 | ||
af585b92 GN |
10819 | return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); |
10820 | } | |
10821 | ||
10822 | static inline u32 kvm_async_pf_next_probe(u32 key) | |
10823 | { | |
dd03bcaa | 10824 | return (key + 1) & (ASYNC_PF_PER_VCPU - 1); |
af585b92 GN |
10825 | } |
10826 | ||
10827 | static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
10828 | { | |
10829 | u32 key = kvm_async_pf_hash_fn(gfn); | |
10830 | ||
10831 | while (vcpu->arch.apf.gfns[key] != ~0) | |
10832 | key = kvm_async_pf_next_probe(key); | |
10833 | ||
10834 | vcpu->arch.apf.gfns[key] = gfn; | |
10835 | } | |
10836 | ||
10837 | static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) | |
10838 | { | |
10839 | int i; | |
10840 | u32 key = kvm_async_pf_hash_fn(gfn); | |
10841 | ||
dd03bcaa | 10842 | for (i = 0; i < ASYNC_PF_PER_VCPU && |
c7d28c24 XG |
10843 | (vcpu->arch.apf.gfns[key] != gfn && |
10844 | vcpu->arch.apf.gfns[key] != ~0); i++) | |
af585b92 GN |
10845 | key = kvm_async_pf_next_probe(key); |
10846 | ||
10847 | return key; | |
10848 | } | |
10849 | ||
10850 | bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
10851 | { | |
10852 | return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; | |
10853 | } | |
10854 | ||
10855 | static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
10856 | { | |
10857 | u32 i, j, k; | |
10858 | ||
10859 | i = j = kvm_async_pf_gfn_slot(vcpu, gfn); | |
0fd46044 PX |
10860 | |
10861 | if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn)) | |
10862 | return; | |
10863 | ||
af585b92 GN |
10864 | while (true) { |
10865 | vcpu->arch.apf.gfns[i] = ~0; | |
10866 | do { | |
10867 | j = kvm_async_pf_next_probe(j); | |
10868 | if (vcpu->arch.apf.gfns[j] == ~0) | |
10869 | return; | |
10870 | k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); | |
10871 | /* | |
10872 | * k lies cyclically in ]i,j] | |
10873 | * | i.k.j | | |
10874 | * |....j i.k.| or |.k..j i...| | |
10875 | */ | |
10876 | } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); | |
10877 | vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; | |
10878 | i = j; | |
10879 | } | |
10880 | } | |
10881 | ||
68fd66f1 | 10882 | static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu) |
7c90705b | 10883 | { |
68fd66f1 VK |
10884 | u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT; |
10885 | ||
10886 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason, | |
10887 | sizeof(reason)); | |
10888 | } | |
10889 | ||
10890 | static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token) | |
10891 | { | |
2635b5c4 | 10892 | unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); |
4e335d9e | 10893 | |
2635b5c4 VK |
10894 | return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, |
10895 | &token, offset, sizeof(token)); | |
10896 | } | |
10897 | ||
10898 | static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu) | |
10899 | { | |
10900 | unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); | |
10901 | u32 val; | |
10902 | ||
10903 | if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, | |
10904 | &val, offset, sizeof(val))) | |
10905 | return false; | |
10906 | ||
10907 | return !val; | |
7c90705b GN |
10908 | } |
10909 | ||
1dfdb45e PB |
10910 | static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) |
10911 | { | |
10912 | if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu)) | |
10913 | return false; | |
10914 | ||
2635b5c4 VK |
10915 | if (!kvm_pv_async_pf_enabled(vcpu) || |
10916 | (vcpu->arch.apf.send_user_only && kvm_x86_ops.get_cpl(vcpu) == 0)) | |
1dfdb45e PB |
10917 | return false; |
10918 | ||
10919 | return true; | |
10920 | } | |
10921 | ||
10922 | bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) | |
10923 | { | |
10924 | if (unlikely(!lapic_in_kernel(vcpu) || | |
10925 | kvm_event_needs_reinjection(vcpu) || | |
10926 | vcpu->arch.exception.pending)) | |
10927 | return false; | |
10928 | ||
10929 | if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) | |
10930 | return false; | |
10931 | ||
10932 | /* | |
10933 | * If interrupts are off we cannot even use an artificial | |
10934 | * halt state. | |
10935 | */ | |
c300ab9f | 10936 | return kvm_arch_interrupt_allowed(vcpu); |
1dfdb45e PB |
10937 | } |
10938 | ||
2a18b7e7 | 10939 | bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
af585b92 GN |
10940 | struct kvm_async_pf *work) |
10941 | { | |
6389ee94 AK |
10942 | struct x86_exception fault; |
10943 | ||
736c291c | 10944 | trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa); |
af585b92 | 10945 | kvm_add_async_pf_gfn(vcpu, work->arch.gfn); |
7c90705b | 10946 | |
1dfdb45e | 10947 | if (kvm_can_deliver_async_pf(vcpu) && |
68fd66f1 | 10948 | !apf_put_user_notpresent(vcpu)) { |
6389ee94 AK |
10949 | fault.vector = PF_VECTOR; |
10950 | fault.error_code_valid = true; | |
10951 | fault.error_code = 0; | |
10952 | fault.nested_page_fault = false; | |
10953 | fault.address = work->arch.token; | |
adfe20fb | 10954 | fault.async_page_fault = true; |
6389ee94 | 10955 | kvm_inject_page_fault(vcpu, &fault); |
2a18b7e7 | 10956 | return true; |
1dfdb45e PB |
10957 | } else { |
10958 | /* | |
10959 | * It is not possible to deliver a paravirtualized asynchronous | |
10960 | * page fault, but putting the guest in an artificial halt state | |
10961 | * can be beneficial nevertheless: if an interrupt arrives, we | |
10962 | * can deliver it timely and perhaps the guest will schedule | |
10963 | * another process. When the instruction that triggered a page | |
10964 | * fault is retried, hopefully the page will be ready in the host. | |
10965 | */ | |
10966 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
2a18b7e7 | 10967 | return false; |
7c90705b | 10968 | } |
af585b92 GN |
10969 | } |
10970 | ||
10971 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
10972 | struct kvm_async_pf *work) | |
10973 | { | |
2635b5c4 VK |
10974 | struct kvm_lapic_irq irq = { |
10975 | .delivery_mode = APIC_DM_FIXED, | |
10976 | .vector = vcpu->arch.apf.vec | |
10977 | }; | |
6389ee94 | 10978 | |
f2e10669 | 10979 | if (work->wakeup_all) |
7c90705b GN |
10980 | work->arch.token = ~0; /* broadcast wakeup */ |
10981 | else | |
10982 | kvm_del_async_pf_gfn(vcpu, work->arch.gfn); | |
736c291c | 10983 | trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa); |
7c90705b | 10984 | |
2a18b7e7 VK |
10985 | if ((work->wakeup_all || work->notpresent_injected) && |
10986 | kvm_pv_async_pf_enabled(vcpu) && | |
557a961a VK |
10987 | !apf_put_user_ready(vcpu, work->arch.token)) { |
10988 | vcpu->arch.apf.pageready_pending = true; | |
2635b5c4 | 10989 | kvm_apic_set_irq(vcpu, &irq, NULL); |
557a961a | 10990 | } |
2635b5c4 | 10991 | |
e6d53e3b | 10992 | vcpu->arch.apf.halted = false; |
a4fa1635 | 10993 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
7c90705b GN |
10994 | } |
10995 | ||
557a961a VK |
10996 | void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu) |
10997 | { | |
10998 | kvm_make_request(KVM_REQ_APF_READY, vcpu); | |
10999 | if (!vcpu->arch.apf.pageready_pending) | |
11000 | kvm_vcpu_kick(vcpu); | |
11001 | } | |
11002 | ||
7c0ade6c | 11003 | bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu) |
7c90705b | 11004 | { |
2635b5c4 | 11005 | if (!kvm_pv_async_pf_enabled(vcpu)) |
7c90705b GN |
11006 | return true; |
11007 | else | |
2635b5c4 | 11008 | return apf_pageready_slot_free(vcpu); |
af585b92 GN |
11009 | } |
11010 | ||
5544eb9b PB |
11011 | void kvm_arch_start_assignment(struct kvm *kvm) |
11012 | { | |
11013 | atomic_inc(&kvm->arch.assigned_device_count); | |
11014 | } | |
11015 | EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); | |
11016 | ||
11017 | void kvm_arch_end_assignment(struct kvm *kvm) | |
11018 | { | |
11019 | atomic_dec(&kvm->arch.assigned_device_count); | |
11020 | } | |
11021 | EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); | |
11022 | ||
11023 | bool kvm_arch_has_assigned_device(struct kvm *kvm) | |
11024 | { | |
11025 | return atomic_read(&kvm->arch.assigned_device_count); | |
11026 | } | |
11027 | EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); | |
11028 | ||
e0f0bbc5 AW |
11029 | void kvm_arch_register_noncoherent_dma(struct kvm *kvm) |
11030 | { | |
11031 | atomic_inc(&kvm->arch.noncoherent_dma_count); | |
11032 | } | |
11033 | EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); | |
11034 | ||
11035 | void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) | |
11036 | { | |
11037 | atomic_dec(&kvm->arch.noncoherent_dma_count); | |
11038 | } | |
11039 | EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); | |
11040 | ||
11041 | bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) | |
11042 | { | |
11043 | return atomic_read(&kvm->arch.noncoherent_dma_count); | |
11044 | } | |
11045 | EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); | |
11046 | ||
14717e20 AW |
11047 | bool kvm_arch_has_irq_bypass(void) |
11048 | { | |
92735b1b | 11049 | return true; |
14717e20 AW |
11050 | } |
11051 | ||
87276880 FW |
11052 | int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, |
11053 | struct irq_bypass_producer *prod) | |
11054 | { | |
11055 | struct kvm_kernel_irqfd *irqfd = | |
11056 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
2edd9cb7 | 11057 | int ret; |
87276880 | 11058 | |
14717e20 | 11059 | irqfd->producer = prod; |
2edd9cb7 ZL |
11060 | kvm_arch_start_assignment(irqfd->kvm); |
11061 | ret = kvm_x86_ops.update_pi_irte(irqfd->kvm, | |
11062 | prod->irq, irqfd->gsi, 1); | |
11063 | ||
11064 | if (ret) | |
11065 | kvm_arch_end_assignment(irqfd->kvm); | |
87276880 | 11066 | |
2edd9cb7 | 11067 | return ret; |
87276880 FW |
11068 | } |
11069 | ||
11070 | void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, | |
11071 | struct irq_bypass_producer *prod) | |
11072 | { | |
11073 | int ret; | |
11074 | struct kvm_kernel_irqfd *irqfd = | |
11075 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
11076 | ||
87276880 FW |
11077 | WARN_ON(irqfd->producer != prod); |
11078 | irqfd->producer = NULL; | |
11079 | ||
11080 | /* | |
11081 | * When producer of consumer is unregistered, we change back to | |
11082 | * remapped mode, so we can re-use the current implementation | |
bb3541f1 | 11083 | * when the irq is masked/disabled or the consumer side (KVM |
87276880 FW |
11084 | * int this case doesn't want to receive the interrupts. |
11085 | */ | |
afaf0b2f | 11086 | ret = kvm_x86_ops.update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0); |
87276880 FW |
11087 | if (ret) |
11088 | printk(KERN_INFO "irq bypass consumer (token %p) unregistration" | |
11089 | " fails: %d\n", irqfd->consumer.token, ret); | |
2edd9cb7 ZL |
11090 | |
11091 | kvm_arch_end_assignment(irqfd->kvm); | |
87276880 FW |
11092 | } |
11093 | ||
11094 | int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, | |
11095 | uint32_t guest_irq, bool set) | |
11096 | { | |
afaf0b2f | 11097 | return kvm_x86_ops.update_pi_irte(kvm, host_irq, guest_irq, set); |
87276880 FW |
11098 | } |
11099 | ||
52004014 FW |
11100 | bool kvm_vector_hashing_enabled(void) |
11101 | { | |
11102 | return vector_hashing; | |
11103 | } | |
52004014 | 11104 | |
2d5ba19b MT |
11105 | bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) |
11106 | { | |
11107 | return (vcpu->arch.msr_kvm_poll_control & 1) == 0; | |
11108 | } | |
11109 | EXPORT_SYMBOL_GPL(kvm_arch_no_poll); | |
11110 | ||
841c2be0 ML |
11111 | |
11112 | int kvm_spec_ctrl_test_value(u64 value) | |
6441fa61 | 11113 | { |
841c2be0 ML |
11114 | /* |
11115 | * test that setting IA32_SPEC_CTRL to given value | |
11116 | * is allowed by the host processor | |
11117 | */ | |
6441fa61 | 11118 | |
841c2be0 ML |
11119 | u64 saved_value; |
11120 | unsigned long flags; | |
11121 | int ret = 0; | |
6441fa61 | 11122 | |
841c2be0 | 11123 | local_irq_save(flags); |
6441fa61 | 11124 | |
841c2be0 ML |
11125 | if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value)) |
11126 | ret = 1; | |
11127 | else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value)) | |
11128 | ret = 1; | |
11129 | else | |
11130 | wrmsrl(MSR_IA32_SPEC_CTRL, saved_value); | |
6441fa61 | 11131 | |
841c2be0 | 11132 | local_irq_restore(flags); |
6441fa61 | 11133 | |
841c2be0 | 11134 | return ret; |
6441fa61 | 11135 | } |
841c2be0 | 11136 | EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value); |
2d5ba19b | 11137 | |
89786147 MG |
11138 | void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code) |
11139 | { | |
11140 | struct x86_exception fault; | |
19cf4b7e PB |
11141 | u32 access = error_code & |
11142 | (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK); | |
89786147 MG |
11143 | |
11144 | if (!(error_code & PFERR_PRESENT_MASK) || | |
19cf4b7e | 11145 | vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, &fault) != UNMAPPED_GVA) { |
89786147 MG |
11146 | /* |
11147 | * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page | |
11148 | * tables probably do not match the TLB. Just proceed | |
11149 | * with the error code that the processor gave. | |
11150 | */ | |
11151 | fault.vector = PF_VECTOR; | |
11152 | fault.error_code_valid = true; | |
11153 | fault.error_code = error_code; | |
11154 | fault.nested_page_fault = false; | |
11155 | fault.address = gva; | |
11156 | } | |
11157 | vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault); | |
6441fa61 | 11158 | } |
89786147 | 11159 | EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error); |
2d5ba19b | 11160 | |
3f3393b3 BM |
11161 | /* |
11162 | * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns | |
11163 | * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value | |
11164 | * indicates whether exit to userspace is needed. | |
11165 | */ | |
11166 | int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, | |
11167 | struct x86_exception *e) | |
11168 | { | |
11169 | if (r == X86EMUL_PROPAGATE_FAULT) { | |
11170 | kvm_inject_emulated_page_fault(vcpu, e); | |
11171 | return 1; | |
11172 | } | |
11173 | ||
11174 | /* | |
11175 | * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED | |
11176 | * while handling a VMX instruction KVM could've handled the request | |
11177 | * correctly by exiting to userspace and performing I/O but there | |
11178 | * doesn't seem to be a real use-case behind such requests, just return | |
11179 | * KVM_EXIT_INTERNAL_ERROR for now. | |
11180 | */ | |
11181 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
11182 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
11183 | vcpu->run->internal.ndata = 0; | |
11184 | ||
11185 | return 0; | |
11186 | } | |
11187 | EXPORT_SYMBOL_GPL(kvm_handle_memory_failure); | |
11188 | ||
9715092f BM |
11189 | int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva) |
11190 | { | |
11191 | bool pcid_enabled; | |
11192 | struct x86_exception e; | |
11193 | unsigned i; | |
11194 | unsigned long roots_to_free = 0; | |
11195 | struct { | |
11196 | u64 pcid; | |
11197 | u64 gla; | |
11198 | } operand; | |
11199 | int r; | |
11200 | ||
11201 | r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); | |
11202 | if (r != X86EMUL_CONTINUE) | |
11203 | return kvm_handle_memory_failure(vcpu, r, &e); | |
11204 | ||
11205 | if (operand.pcid >> 12 != 0) { | |
11206 | kvm_inject_gp(vcpu, 0); | |
11207 | return 1; | |
11208 | } | |
11209 | ||
11210 | pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); | |
11211 | ||
11212 | switch (type) { | |
11213 | case INVPCID_TYPE_INDIV_ADDR: | |
11214 | if ((!pcid_enabled && (operand.pcid != 0)) || | |
11215 | is_noncanonical_address(operand.gla, vcpu)) { | |
11216 | kvm_inject_gp(vcpu, 0); | |
11217 | return 1; | |
11218 | } | |
11219 | kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); | |
11220 | return kvm_skip_emulated_instruction(vcpu); | |
11221 | ||
11222 | case INVPCID_TYPE_SINGLE_CTXT: | |
11223 | if (!pcid_enabled && (operand.pcid != 0)) { | |
11224 | kvm_inject_gp(vcpu, 0); | |
11225 | return 1; | |
11226 | } | |
11227 | ||
11228 | if (kvm_get_active_pcid(vcpu) == operand.pcid) { | |
11229 | kvm_mmu_sync_roots(vcpu); | |
11230 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); | |
11231 | } | |
11232 | ||
11233 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
11234 | if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].pgd) | |
11235 | == operand.pcid) | |
11236 | roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); | |
11237 | ||
11238 | kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free); | |
11239 | /* | |
11240 | * If neither the current cr3 nor any of the prev_roots use the | |
11241 | * given PCID, then nothing needs to be done here because a | |
11242 | * resync will happen anyway before switching to any other CR3. | |
11243 | */ | |
11244 | ||
11245 | return kvm_skip_emulated_instruction(vcpu); | |
11246 | ||
11247 | case INVPCID_TYPE_ALL_NON_GLOBAL: | |
11248 | /* | |
11249 | * Currently, KVM doesn't mark global entries in the shadow | |
11250 | * page tables, so a non-global flush just degenerates to a | |
11251 | * global flush. If needed, we could optimize this later by | |
11252 | * keeping track of global entries in shadow page tables. | |
11253 | */ | |
11254 | ||
11255 | fallthrough; | |
11256 | case INVPCID_TYPE_ALL_INCL_GLOBAL: | |
11257 | kvm_mmu_unload(vcpu); | |
11258 | return kvm_skip_emulated_instruction(vcpu); | |
11259 | ||
11260 | default: | |
11261 | BUG(); /* We have already checked above that type <= 3 */ | |
11262 | } | |
11263 | } | |
11264 | EXPORT_SYMBOL_GPL(kvm_handle_invpcid); | |
11265 | ||
229456fc | 11266 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
931c33b1 | 11267 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); |
229456fc MT |
11268 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); |
11269 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
11270 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
11271 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
0ac406de | 11272 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); |
d8cabddf | 11273 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 11274 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 11275 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
5497b955 | 11276 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); |
ec1ff790 | 11277 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 11278 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |
2e554e8d | 11279 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); |
489223ed | 11280 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); |
4f75bcc3 | 11281 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); |
843e4330 | 11282 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); |
efc64404 | 11283 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); |
18f40c53 SS |
11284 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); |
11285 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); | |
ab56f8e6 | 11286 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log); |
24bbf74c | 11287 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request); |