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Commit | Line | Data |
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043405e1 CO |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * derived from drivers/kvm/kvm_main.c | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
7 | * Copyright (C) 2008 Qumranet, Inc. |
8 | * Copyright IBM Corporation, 2008 | |
043405e1 CO |
9 | * |
10 | * Authors: | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
13 | * Amit Shah <amit.shah@qumranet.com> |
14 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
15 | * |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
20 | ||
edf88417 | 21 | #include <linux/kvm_host.h> |
313a3dc7 | 22 | #include "irq.h" |
1d737c8a | 23 | #include "mmu.h" |
7837699f | 24 | #include "i8254.h" |
37817f29 | 25 | #include "tss.h" |
5fdbf976 | 26 | #include "kvm_cache_regs.h" |
26eef70c | 27 | #include "x86.h" |
313a3dc7 | 28 | |
18068523 | 29 | #include <linux/clocksource.h> |
4d5c5d0f | 30 | #include <linux/interrupt.h> |
313a3dc7 CO |
31 | #include <linux/kvm.h> |
32 | #include <linux/fs.h> | |
33 | #include <linux/vmalloc.h> | |
5fb76f9b | 34 | #include <linux/module.h> |
0de10343 | 35 | #include <linux/mman.h> |
2bacc55c | 36 | #include <linux/highmem.h> |
19de40a8 | 37 | #include <linux/iommu.h> |
62c476c7 | 38 | #include <linux/intel-iommu.h> |
c8076604 | 39 | #include <linux/cpufreq.h> |
18863bdd | 40 | #include <linux/user-return-notifier.h> |
a983fb23 | 41 | #include <linux/srcu.h> |
aec51dc4 AK |
42 | #include <trace/events/kvm.h> |
43 | #undef TRACE_INCLUDE_FILE | |
229456fc MT |
44 | #define CREATE_TRACE_POINTS |
45 | #include "trace.h" | |
043405e1 | 46 | |
24f1e32c | 47 | #include <asm/debugreg.h> |
043405e1 | 48 | #include <asm/uaccess.h> |
d825ed0a | 49 | #include <asm/msr.h> |
a5f61300 | 50 | #include <asm/desc.h> |
0bed3b56 | 51 | #include <asm/mtrr.h> |
890ca9ae | 52 | #include <asm/mce.h> |
043405e1 | 53 | |
313a3dc7 | 54 | #define MAX_IO_MSRS 256 |
a03490ed CO |
55 | #define CR0_RESERVED_BITS \ |
56 | (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ | |
57 | | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ | |
58 | | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) | |
59 | #define CR4_RESERVED_BITS \ | |
60 | (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ | |
61 | | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ | |
62 | | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \ | |
63 | | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE)) | |
64 | ||
65 | #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) | |
890ca9ae HY |
66 | |
67 | #define KVM_MAX_MCE_BANKS 32 | |
68 | #define KVM_MCE_CAP_SUPPORTED MCG_CTL_P | |
69 | ||
50a37eb4 JR |
70 | /* EFER defaults: |
71 | * - enable syscall per default because its emulated by KVM | |
72 | * - enable LME and LMA per default on 64 bit KVM | |
73 | */ | |
74 | #ifdef CONFIG_X86_64 | |
75 | static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL; | |
76 | #else | |
77 | static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL; | |
78 | #endif | |
313a3dc7 | 79 | |
ba1389b7 AK |
80 | #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM |
81 | #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU | |
417bc304 | 82 | |
cb142eb7 | 83 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
674eea0f AK |
84 | static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid, |
85 | struct kvm_cpuid_entry2 __user *entries); | |
86 | ||
97896d04 | 87 | struct kvm_x86_ops *kvm_x86_ops; |
5fdbf976 | 88 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 89 | |
ed85c068 AP |
90 | int ignore_msrs = 0; |
91 | module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR); | |
92 | ||
18863bdd AK |
93 | #define KVM_NR_SHARED_MSRS 16 |
94 | ||
95 | struct kvm_shared_msrs_global { | |
96 | int nr; | |
2bf78fa7 | 97 | u32 msrs[KVM_NR_SHARED_MSRS]; |
18863bdd AK |
98 | }; |
99 | ||
100 | struct kvm_shared_msrs { | |
101 | struct user_return_notifier urn; | |
102 | bool registered; | |
2bf78fa7 SY |
103 | struct kvm_shared_msr_values { |
104 | u64 host; | |
105 | u64 curr; | |
106 | } values[KVM_NR_SHARED_MSRS]; | |
18863bdd AK |
107 | }; |
108 | ||
109 | static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; | |
110 | static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs); | |
111 | ||
417bc304 | 112 | struct kvm_stats_debugfs_item debugfs_entries[] = { |
ba1389b7 AK |
113 | { "pf_fixed", VCPU_STAT(pf_fixed) }, |
114 | { "pf_guest", VCPU_STAT(pf_guest) }, | |
115 | { "tlb_flush", VCPU_STAT(tlb_flush) }, | |
116 | { "invlpg", VCPU_STAT(invlpg) }, | |
117 | { "exits", VCPU_STAT(exits) }, | |
118 | { "io_exits", VCPU_STAT(io_exits) }, | |
119 | { "mmio_exits", VCPU_STAT(mmio_exits) }, | |
120 | { "signal_exits", VCPU_STAT(signal_exits) }, | |
121 | { "irq_window", VCPU_STAT(irq_window_exits) }, | |
f08864b4 | 122 | { "nmi_window", VCPU_STAT(nmi_window_exits) }, |
ba1389b7 AK |
123 | { "halt_exits", VCPU_STAT(halt_exits) }, |
124 | { "halt_wakeup", VCPU_STAT(halt_wakeup) }, | |
f11c3a8d | 125 | { "hypercalls", VCPU_STAT(hypercalls) }, |
ba1389b7 AK |
126 | { "request_irq", VCPU_STAT(request_irq_exits) }, |
127 | { "irq_exits", VCPU_STAT(irq_exits) }, | |
128 | { "host_state_reload", VCPU_STAT(host_state_reload) }, | |
129 | { "efer_reload", VCPU_STAT(efer_reload) }, | |
130 | { "fpu_reload", VCPU_STAT(fpu_reload) }, | |
131 | { "insn_emulation", VCPU_STAT(insn_emulation) }, | |
132 | { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, | |
fa89a817 | 133 | { "irq_injections", VCPU_STAT(irq_injections) }, |
c4abb7c9 | 134 | { "nmi_injections", VCPU_STAT(nmi_injections) }, |
4cee5764 AK |
135 | { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, |
136 | { "mmu_pte_write", VM_STAT(mmu_pte_write) }, | |
137 | { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, | |
138 | { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, | |
139 | { "mmu_flooded", VM_STAT(mmu_flooded) }, | |
140 | { "mmu_recycled", VM_STAT(mmu_recycled) }, | |
dfc5aa00 | 141 | { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, |
4731d4c7 | 142 | { "mmu_unsync", VM_STAT(mmu_unsync) }, |
0f74a24c | 143 | { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, |
05da4558 | 144 | { "largepages", VM_STAT(lpages) }, |
417bc304 HB |
145 | { NULL } |
146 | }; | |
147 | ||
18863bdd AK |
148 | static void kvm_on_user_return(struct user_return_notifier *urn) |
149 | { | |
150 | unsigned slot; | |
18863bdd AK |
151 | struct kvm_shared_msrs *locals |
152 | = container_of(urn, struct kvm_shared_msrs, urn); | |
2bf78fa7 | 153 | struct kvm_shared_msr_values *values; |
18863bdd AK |
154 | |
155 | for (slot = 0; slot < shared_msrs_global.nr; ++slot) { | |
2bf78fa7 SY |
156 | values = &locals->values[slot]; |
157 | if (values->host != values->curr) { | |
158 | wrmsrl(shared_msrs_global.msrs[slot], values->host); | |
159 | values->curr = values->host; | |
18863bdd AK |
160 | } |
161 | } | |
162 | locals->registered = false; | |
163 | user_return_notifier_unregister(urn); | |
164 | } | |
165 | ||
2bf78fa7 | 166 | static void shared_msr_update(unsigned slot, u32 msr) |
18863bdd | 167 | { |
2bf78fa7 | 168 | struct kvm_shared_msrs *smsr; |
18863bdd AK |
169 | u64 value; |
170 | ||
2bf78fa7 SY |
171 | smsr = &__get_cpu_var(shared_msrs); |
172 | /* only read, and nobody should modify it at this time, | |
173 | * so don't need lock */ | |
174 | if (slot >= shared_msrs_global.nr) { | |
175 | printk(KERN_ERR "kvm: invalid MSR slot!"); | |
176 | return; | |
177 | } | |
178 | rdmsrl_safe(msr, &value); | |
179 | smsr->values[slot].host = value; | |
180 | smsr->values[slot].curr = value; | |
181 | } | |
182 | ||
183 | void kvm_define_shared_msr(unsigned slot, u32 msr) | |
184 | { | |
18863bdd AK |
185 | if (slot >= shared_msrs_global.nr) |
186 | shared_msrs_global.nr = slot + 1; | |
2bf78fa7 SY |
187 | shared_msrs_global.msrs[slot] = msr; |
188 | /* we need ensured the shared_msr_global have been updated */ | |
189 | smp_wmb(); | |
18863bdd AK |
190 | } |
191 | EXPORT_SYMBOL_GPL(kvm_define_shared_msr); | |
192 | ||
193 | static void kvm_shared_msr_cpu_online(void) | |
194 | { | |
195 | unsigned i; | |
18863bdd AK |
196 | |
197 | for (i = 0; i < shared_msrs_global.nr; ++i) | |
2bf78fa7 | 198 | shared_msr_update(i, shared_msrs_global.msrs[i]); |
18863bdd AK |
199 | } |
200 | ||
d5696725 | 201 | void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) |
18863bdd AK |
202 | { |
203 | struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs); | |
204 | ||
2bf78fa7 | 205 | if (((value ^ smsr->values[slot].curr) & mask) == 0) |
18863bdd | 206 | return; |
2bf78fa7 SY |
207 | smsr->values[slot].curr = value; |
208 | wrmsrl(shared_msrs_global.msrs[slot], value); | |
18863bdd AK |
209 | if (!smsr->registered) { |
210 | smsr->urn.on_user_return = kvm_on_user_return; | |
211 | user_return_notifier_register(&smsr->urn); | |
212 | smsr->registered = true; | |
213 | } | |
214 | } | |
215 | EXPORT_SYMBOL_GPL(kvm_set_shared_msr); | |
216 | ||
3548bab5 AK |
217 | static void drop_user_return_notifiers(void *ignore) |
218 | { | |
219 | struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs); | |
220 | ||
221 | if (smsr->registered) | |
222 | kvm_on_user_return(&smsr->urn); | |
223 | } | |
224 | ||
5fb76f9b CO |
225 | unsigned long segment_base(u16 selector) |
226 | { | |
227 | struct descriptor_table gdt; | |
a5f61300 | 228 | struct desc_struct *d; |
5fb76f9b CO |
229 | unsigned long table_base; |
230 | unsigned long v; | |
231 | ||
232 | if (selector == 0) | |
233 | return 0; | |
234 | ||
b792c344 | 235 | kvm_get_gdt(&gdt); |
5fb76f9b CO |
236 | table_base = gdt.base; |
237 | ||
238 | if (selector & 4) { /* from ldt */ | |
b792c344 | 239 | u16 ldt_selector = kvm_read_ldt(); |
5fb76f9b | 240 | |
5fb76f9b CO |
241 | table_base = segment_base(ldt_selector); |
242 | } | |
a5f61300 | 243 | d = (struct desc_struct *)(table_base + (selector & ~7)); |
46a359e7 | 244 | v = get_desc_base(d); |
5fb76f9b | 245 | #ifdef CONFIG_X86_64 |
a5f61300 AK |
246 | if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11)) |
247 | v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32; | |
5fb76f9b CO |
248 | #endif |
249 | return v; | |
250 | } | |
251 | EXPORT_SYMBOL_GPL(segment_base); | |
252 | ||
6866b83e CO |
253 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
254 | { | |
255 | if (irqchip_in_kernel(vcpu->kvm)) | |
ad312c7c | 256 | return vcpu->arch.apic_base; |
6866b83e | 257 | else |
ad312c7c | 258 | return vcpu->arch.apic_base; |
6866b83e CO |
259 | } |
260 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
261 | ||
262 | void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data) | |
263 | { | |
264 | /* TODO: reserve bits check */ | |
265 | if (irqchip_in_kernel(vcpu->kvm)) | |
266 | kvm_lapic_set_base(vcpu, data); | |
267 | else | |
ad312c7c | 268 | vcpu->arch.apic_base = data; |
6866b83e CO |
269 | } |
270 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
271 | ||
3fd28fce ED |
272 | #define EXCPT_BENIGN 0 |
273 | #define EXCPT_CONTRIBUTORY 1 | |
274 | #define EXCPT_PF 2 | |
275 | ||
276 | static int exception_class(int vector) | |
277 | { | |
278 | switch (vector) { | |
279 | case PF_VECTOR: | |
280 | return EXCPT_PF; | |
281 | case DE_VECTOR: | |
282 | case TS_VECTOR: | |
283 | case NP_VECTOR: | |
284 | case SS_VECTOR: | |
285 | case GP_VECTOR: | |
286 | return EXCPT_CONTRIBUTORY; | |
287 | default: | |
288 | break; | |
289 | } | |
290 | return EXCPT_BENIGN; | |
291 | } | |
292 | ||
293 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, | |
294 | unsigned nr, bool has_error, u32 error_code) | |
295 | { | |
296 | u32 prev_nr; | |
297 | int class1, class2; | |
298 | ||
299 | if (!vcpu->arch.exception.pending) { | |
300 | queue: | |
301 | vcpu->arch.exception.pending = true; | |
302 | vcpu->arch.exception.has_error_code = has_error; | |
303 | vcpu->arch.exception.nr = nr; | |
304 | vcpu->arch.exception.error_code = error_code; | |
305 | return; | |
306 | } | |
307 | ||
308 | /* to check exception */ | |
309 | prev_nr = vcpu->arch.exception.nr; | |
310 | if (prev_nr == DF_VECTOR) { | |
311 | /* triple fault -> shutdown */ | |
312 | set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests); | |
313 | return; | |
314 | } | |
315 | class1 = exception_class(prev_nr); | |
316 | class2 = exception_class(nr); | |
317 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) | |
318 | || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
319 | /* generate double fault per SDM Table 5-5 */ | |
320 | vcpu->arch.exception.pending = true; | |
321 | vcpu->arch.exception.has_error_code = true; | |
322 | vcpu->arch.exception.nr = DF_VECTOR; | |
323 | vcpu->arch.exception.error_code = 0; | |
324 | } else | |
325 | /* replace previous exception with a new one in a hope | |
326 | that instruction re-execution will regenerate lost | |
327 | exception */ | |
328 | goto queue; | |
329 | } | |
330 | ||
298101da AK |
331 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
332 | { | |
3fd28fce | 333 | kvm_multiple_exception(vcpu, nr, false, 0); |
298101da AK |
334 | } |
335 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
336 | ||
c3c91fee AK |
337 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr, |
338 | u32 error_code) | |
339 | { | |
340 | ++vcpu->stat.pf_guest; | |
ad312c7c | 341 | vcpu->arch.cr2 = addr; |
c3c91fee AK |
342 | kvm_queue_exception_e(vcpu, PF_VECTOR, error_code); |
343 | } | |
344 | ||
3419ffc8 SY |
345 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
346 | { | |
347 | vcpu->arch.nmi_pending = 1; | |
348 | } | |
349 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
350 | ||
298101da AK |
351 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
352 | { | |
3fd28fce | 353 | kvm_multiple_exception(vcpu, nr, true, error_code); |
298101da AK |
354 | } |
355 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
356 | ||
0a79b009 AK |
357 | /* |
358 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
359 | * a #GP and return false. | |
360 | */ | |
361 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 362 | { |
0a79b009 AK |
363 | if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) |
364 | return true; | |
365 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
366 | return false; | |
298101da | 367 | } |
0a79b009 | 368 | EXPORT_SYMBOL_GPL(kvm_require_cpl); |
298101da | 369 | |
a03490ed CO |
370 | /* |
371 | * Load the pae pdptrs. Return true is they are all valid. | |
372 | */ | |
373 | int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3) | |
374 | { | |
375 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
376 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
377 | int i; | |
378 | int ret; | |
ad312c7c | 379 | u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)]; |
a03490ed | 380 | |
a03490ed CO |
381 | ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte, |
382 | offset * sizeof(u64), sizeof(pdpte)); | |
383 | if (ret < 0) { | |
384 | ret = 0; | |
385 | goto out; | |
386 | } | |
387 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
43a3795a | 388 | if (is_present_gpte(pdpte[i]) && |
20c466b5 | 389 | (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) { |
a03490ed CO |
390 | ret = 0; |
391 | goto out; | |
392 | } | |
393 | } | |
394 | ret = 1; | |
395 | ||
ad312c7c | 396 | memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs)); |
6de4f3ad AK |
397 | __set_bit(VCPU_EXREG_PDPTR, |
398 | (unsigned long *)&vcpu->arch.regs_avail); | |
399 | __set_bit(VCPU_EXREG_PDPTR, | |
400 | (unsigned long *)&vcpu->arch.regs_dirty); | |
a03490ed | 401 | out: |
a03490ed CO |
402 | |
403 | return ret; | |
404 | } | |
cc4b6871 | 405 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 406 | |
d835dfec AK |
407 | static bool pdptrs_changed(struct kvm_vcpu *vcpu) |
408 | { | |
ad312c7c | 409 | u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)]; |
d835dfec AK |
410 | bool changed = true; |
411 | int r; | |
412 | ||
413 | if (is_long_mode(vcpu) || !is_pae(vcpu)) | |
414 | return false; | |
415 | ||
6de4f3ad AK |
416 | if (!test_bit(VCPU_EXREG_PDPTR, |
417 | (unsigned long *)&vcpu->arch.regs_avail)) | |
418 | return true; | |
419 | ||
ad312c7c | 420 | r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte)); |
d835dfec AK |
421 | if (r < 0) |
422 | goto out; | |
ad312c7c | 423 | changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0; |
d835dfec | 424 | out: |
d835dfec AK |
425 | |
426 | return changed; | |
427 | } | |
428 | ||
2d3ad1f4 | 429 | void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 430 | { |
f9a48e6a AK |
431 | cr0 |= X86_CR0_ET; |
432 | ||
a03490ed CO |
433 | if (cr0 & CR0_RESERVED_BITS) { |
434 | printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n", | |
4d4ec087 | 435 | cr0, kvm_read_cr0(vcpu)); |
c1a5d4f9 | 436 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
437 | return; |
438 | } | |
439 | ||
440 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) { | |
441 | printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n"); | |
c1a5d4f9 | 442 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
443 | return; |
444 | } | |
445 | ||
446 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) { | |
447 | printk(KERN_DEBUG "set_cr0: #GP, set PG flag " | |
448 | "and a clear PE flag\n"); | |
c1a5d4f9 | 449 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
450 | return; |
451 | } | |
452 | ||
453 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { | |
454 | #ifdef CONFIG_X86_64 | |
ad312c7c | 455 | if ((vcpu->arch.shadow_efer & EFER_LME)) { |
a03490ed CO |
456 | int cs_db, cs_l; |
457 | ||
458 | if (!is_pae(vcpu)) { | |
459 | printk(KERN_DEBUG "set_cr0: #GP, start paging " | |
460 | "in long mode while PAE is disabled\n"); | |
c1a5d4f9 | 461 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
462 | return; |
463 | } | |
464 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
465 | if (cs_l) { | |
466 | printk(KERN_DEBUG "set_cr0: #GP, start paging " | |
467 | "in long mode while CS.L == 1\n"); | |
c1a5d4f9 | 468 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
469 | return; |
470 | ||
471 | } | |
472 | } else | |
473 | #endif | |
ad312c7c | 474 | if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) { |
a03490ed CO |
475 | printk(KERN_DEBUG "set_cr0: #GP, pdptrs " |
476 | "reserved bits\n"); | |
c1a5d4f9 | 477 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
478 | return; |
479 | } | |
480 | ||
481 | } | |
482 | ||
483 | kvm_x86_ops->set_cr0(vcpu, cr0); | |
ad312c7c | 484 | vcpu->arch.cr0 = cr0; |
a03490ed | 485 | |
a03490ed | 486 | kvm_mmu_reset_context(vcpu); |
a03490ed CO |
487 | return; |
488 | } | |
2d3ad1f4 | 489 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 490 | |
2d3ad1f4 | 491 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 492 | { |
4d4ec087 | 493 | kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0ful) | (msw & 0x0f)); |
a03490ed | 494 | } |
2d3ad1f4 | 495 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 496 | |
2d3ad1f4 | 497 | void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 498 | { |
fc78f519 | 499 | unsigned long old_cr4 = kvm_read_cr4(vcpu); |
a2edf57f AK |
500 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE; |
501 | ||
a03490ed CO |
502 | if (cr4 & CR4_RESERVED_BITS) { |
503 | printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n"); | |
c1a5d4f9 | 504 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
505 | return; |
506 | } | |
507 | ||
508 | if (is_long_mode(vcpu)) { | |
509 | if (!(cr4 & X86_CR4_PAE)) { | |
510 | printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while " | |
511 | "in long mode\n"); | |
c1a5d4f9 | 512 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
513 | return; |
514 | } | |
a2edf57f AK |
515 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
516 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
ad312c7c | 517 | && !load_pdptrs(vcpu, vcpu->arch.cr3)) { |
a03490ed | 518 | printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n"); |
c1a5d4f9 | 519 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
520 | return; |
521 | } | |
522 | ||
523 | if (cr4 & X86_CR4_VMXE) { | |
524 | printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n"); | |
c1a5d4f9 | 525 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
526 | return; |
527 | } | |
528 | kvm_x86_ops->set_cr4(vcpu, cr4); | |
ad312c7c | 529 | vcpu->arch.cr4 = cr4; |
5a41accd | 530 | vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled; |
a03490ed | 531 | kvm_mmu_reset_context(vcpu); |
a03490ed | 532 | } |
2d3ad1f4 | 533 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 534 | |
2d3ad1f4 | 535 | void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 536 | { |
ad312c7c | 537 | if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) { |
0ba73cda | 538 | kvm_mmu_sync_roots(vcpu); |
d835dfec AK |
539 | kvm_mmu_flush_tlb(vcpu); |
540 | return; | |
541 | } | |
542 | ||
a03490ed CO |
543 | if (is_long_mode(vcpu)) { |
544 | if (cr3 & CR3_L_MODE_RESERVED_BITS) { | |
545 | printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n"); | |
c1a5d4f9 | 546 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
547 | return; |
548 | } | |
549 | } else { | |
550 | if (is_pae(vcpu)) { | |
551 | if (cr3 & CR3_PAE_RESERVED_BITS) { | |
552 | printk(KERN_DEBUG | |
553 | "set_cr3: #GP, reserved bits\n"); | |
c1a5d4f9 | 554 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
555 | return; |
556 | } | |
557 | if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) { | |
558 | printk(KERN_DEBUG "set_cr3: #GP, pdptrs " | |
559 | "reserved bits\n"); | |
c1a5d4f9 | 560 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
561 | return; |
562 | } | |
563 | } | |
564 | /* | |
565 | * We don't check reserved bits in nonpae mode, because | |
566 | * this isn't enforced, and VMware depends on this. | |
567 | */ | |
568 | } | |
569 | ||
a03490ed CO |
570 | /* |
571 | * Does the new cr3 value map to physical memory? (Note, we | |
572 | * catch an invalid cr3 even in real-mode, because it would | |
573 | * cause trouble later on when we turn on paging anyway.) | |
574 | * | |
575 | * A real CPU would silently accept an invalid cr3 and would | |
576 | * attempt to use it - with largely undefined (and often hard | |
577 | * to debug) behavior on the guest side. | |
578 | */ | |
579 | if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT))) | |
c1a5d4f9 | 580 | kvm_inject_gp(vcpu, 0); |
a03490ed | 581 | else { |
ad312c7c ZX |
582 | vcpu->arch.cr3 = cr3; |
583 | vcpu->arch.mmu.new_cr3(vcpu); | |
a03490ed | 584 | } |
a03490ed | 585 | } |
2d3ad1f4 | 586 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 587 | |
2d3ad1f4 | 588 | void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed CO |
589 | { |
590 | if (cr8 & CR8_RESERVED_BITS) { | |
591 | printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8); | |
c1a5d4f9 | 592 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
593 | return; |
594 | } | |
595 | if (irqchip_in_kernel(vcpu->kvm)) | |
596 | kvm_lapic_set_tpr(vcpu, cr8); | |
597 | else | |
ad312c7c | 598 | vcpu->arch.cr8 = cr8; |
a03490ed | 599 | } |
2d3ad1f4 | 600 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 601 | |
2d3ad1f4 | 602 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed CO |
603 | { |
604 | if (irqchip_in_kernel(vcpu->kvm)) | |
605 | return kvm_lapic_get_cr8(vcpu); | |
606 | else | |
ad312c7c | 607 | return vcpu->arch.cr8; |
a03490ed | 608 | } |
2d3ad1f4 | 609 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 610 | |
d8017474 AG |
611 | static inline u32 bit(int bitno) |
612 | { | |
613 | return 1 << (bitno & 31); | |
614 | } | |
615 | ||
043405e1 CO |
616 | /* |
617 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
618 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
619 | * | |
620 | * This list is modified at module load time to reflect the | |
e3267cbb GC |
621 | * capabilities of the host cpu. This capabilities test skips MSRs that are |
622 | * kvm-specific. Those are put in the beginning of the list. | |
043405e1 | 623 | */ |
e3267cbb | 624 | |
10388a07 | 625 | #define KVM_SAVE_MSRS_BEGIN 5 |
043405e1 | 626 | static u32 msrs_to_save[] = { |
e3267cbb | 627 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, |
55cd8e5a | 628 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, |
10388a07 | 629 | HV_X64_MSR_APIC_ASSIST_PAGE, |
043405e1 CO |
630 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, |
631 | MSR_K6_STAR, | |
632 | #ifdef CONFIG_X86_64 | |
633 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
634 | #endif | |
e3267cbb | 635 | MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA |
043405e1 CO |
636 | }; |
637 | ||
638 | static unsigned num_msrs_to_save; | |
639 | ||
640 | static u32 emulated_msrs[] = { | |
641 | MSR_IA32_MISC_ENABLE, | |
642 | }; | |
643 | ||
15c4a640 CO |
644 | static void set_efer(struct kvm_vcpu *vcpu, u64 efer) |
645 | { | |
f2b4b7dd | 646 | if (efer & efer_reserved_bits) { |
15c4a640 CO |
647 | printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n", |
648 | efer); | |
c1a5d4f9 | 649 | kvm_inject_gp(vcpu, 0); |
15c4a640 CO |
650 | return; |
651 | } | |
652 | ||
653 | if (is_paging(vcpu) | |
ad312c7c | 654 | && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) { |
15c4a640 | 655 | printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n"); |
c1a5d4f9 | 656 | kvm_inject_gp(vcpu, 0); |
15c4a640 CO |
657 | return; |
658 | } | |
659 | ||
1b2fd70c AG |
660 | if (efer & EFER_FFXSR) { |
661 | struct kvm_cpuid_entry2 *feat; | |
662 | ||
663 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
664 | if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) { | |
665 | printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n"); | |
666 | kvm_inject_gp(vcpu, 0); | |
667 | return; | |
668 | } | |
669 | } | |
670 | ||
d8017474 AG |
671 | if (efer & EFER_SVME) { |
672 | struct kvm_cpuid_entry2 *feat; | |
673 | ||
674 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
675 | if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) { | |
676 | printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n"); | |
677 | kvm_inject_gp(vcpu, 0); | |
678 | return; | |
679 | } | |
680 | } | |
681 | ||
15c4a640 CO |
682 | kvm_x86_ops->set_efer(vcpu, efer); |
683 | ||
684 | efer &= ~EFER_LMA; | |
ad312c7c | 685 | efer |= vcpu->arch.shadow_efer & EFER_LMA; |
15c4a640 | 686 | |
ad312c7c | 687 | vcpu->arch.shadow_efer = efer; |
9645bb56 AK |
688 | |
689 | vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled; | |
690 | kvm_mmu_reset_context(vcpu); | |
15c4a640 CO |
691 | } |
692 | ||
f2b4b7dd JR |
693 | void kvm_enable_efer_bits(u64 mask) |
694 | { | |
695 | efer_reserved_bits &= ~mask; | |
696 | } | |
697 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
698 | ||
699 | ||
15c4a640 CO |
700 | /* |
701 | * Writes msr value into into the appropriate "register". | |
702 | * Returns 0 on success, non-0 otherwise. | |
703 | * Assumes vcpu_load() was already called. | |
704 | */ | |
705 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
706 | { | |
707 | return kvm_x86_ops->set_msr(vcpu, msr_index, data); | |
708 | } | |
709 | ||
313a3dc7 CO |
710 | /* |
711 | * Adapt set_msr() to msr_io()'s calling convention | |
712 | */ | |
713 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
714 | { | |
715 | return kvm_set_msr(vcpu, index, *data); | |
716 | } | |
717 | ||
18068523 GOC |
718 | static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) |
719 | { | |
720 | static int version; | |
50d0a0f9 | 721 | struct pvclock_wall_clock wc; |
923de3cf | 722 | struct timespec boot; |
18068523 GOC |
723 | |
724 | if (!wall_clock) | |
725 | return; | |
726 | ||
727 | version++; | |
728 | ||
18068523 GOC |
729 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); |
730 | ||
50d0a0f9 GH |
731 | /* |
732 | * The guest calculates current wall clock time by adding | |
733 | * system time (updated by kvm_write_guest_time below) to the | |
734 | * wall clock specified here. guest system time equals host | |
735 | * system time for us, thus we must fill in host boot time here. | |
736 | */ | |
923de3cf | 737 | getboottime(&boot); |
50d0a0f9 GH |
738 | |
739 | wc.sec = boot.tv_sec; | |
740 | wc.nsec = boot.tv_nsec; | |
741 | wc.version = version; | |
18068523 GOC |
742 | |
743 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
744 | ||
745 | version++; | |
746 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
747 | } |
748 | ||
50d0a0f9 GH |
749 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
750 | { | |
751 | uint32_t quotient, remainder; | |
752 | ||
753 | /* Don't try to replace with do_div(), this one calculates | |
754 | * "(dividend << 32) / divisor" */ | |
755 | __asm__ ( "divl %4" | |
756 | : "=a" (quotient), "=d" (remainder) | |
757 | : "0" (0), "1" (dividend), "r" (divisor) ); | |
758 | return quotient; | |
759 | } | |
760 | ||
761 | static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock) | |
762 | { | |
763 | uint64_t nsecs = 1000000000LL; | |
764 | int32_t shift = 0; | |
765 | uint64_t tps64; | |
766 | uint32_t tps32; | |
767 | ||
768 | tps64 = tsc_khz * 1000LL; | |
769 | while (tps64 > nsecs*2) { | |
770 | tps64 >>= 1; | |
771 | shift--; | |
772 | } | |
773 | ||
774 | tps32 = (uint32_t)tps64; | |
775 | while (tps32 <= (uint32_t)nsecs) { | |
776 | tps32 <<= 1; | |
777 | shift++; | |
778 | } | |
779 | ||
780 | hv_clock->tsc_shift = shift; | |
781 | hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32); | |
782 | ||
783 | pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n", | |
80a914dc | 784 | __func__, tsc_khz, hv_clock->tsc_shift, |
50d0a0f9 GH |
785 | hv_clock->tsc_to_system_mul); |
786 | } | |
787 | ||
c8076604 GH |
788 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
789 | ||
18068523 GOC |
790 | static void kvm_write_guest_time(struct kvm_vcpu *v) |
791 | { | |
792 | struct timespec ts; | |
793 | unsigned long flags; | |
794 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
795 | void *shared_kaddr; | |
463656c0 | 796 | unsigned long this_tsc_khz; |
18068523 GOC |
797 | |
798 | if ((!vcpu->time_page)) | |
799 | return; | |
800 | ||
463656c0 AK |
801 | this_tsc_khz = get_cpu_var(cpu_tsc_khz); |
802 | if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) { | |
803 | kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock); | |
804 | vcpu->hv_clock_tsc_khz = this_tsc_khz; | |
50d0a0f9 | 805 | } |
463656c0 | 806 | put_cpu_var(cpu_tsc_khz); |
50d0a0f9 | 807 | |
18068523 GOC |
808 | /* Keep irq disabled to prevent changes to the clock */ |
809 | local_irq_save(flags); | |
af24a4e4 | 810 | kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp); |
18068523 | 811 | ktime_get_ts(&ts); |
923de3cf | 812 | monotonic_to_bootbased(&ts); |
18068523 GOC |
813 | local_irq_restore(flags); |
814 | ||
815 | /* With all the info we got, fill in the values */ | |
816 | ||
817 | vcpu->hv_clock.system_time = ts.tv_nsec + | |
afbcf7ab GC |
818 | (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset; |
819 | ||
18068523 GOC |
820 | /* |
821 | * The interface expects us to write an even number signaling that the | |
822 | * update is finished. Since the guest won't see the intermediate | |
50d0a0f9 | 823 | * state, we just increase by 2 at the end. |
18068523 | 824 | */ |
50d0a0f9 | 825 | vcpu->hv_clock.version += 2; |
18068523 GOC |
826 | |
827 | shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0); | |
828 | ||
829 | memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock, | |
50d0a0f9 | 830 | sizeof(vcpu->hv_clock)); |
18068523 GOC |
831 | |
832 | kunmap_atomic(shared_kaddr, KM_USER0); | |
833 | ||
834 | mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT); | |
835 | } | |
836 | ||
c8076604 GH |
837 | static int kvm_request_guest_time_update(struct kvm_vcpu *v) |
838 | { | |
839 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
840 | ||
841 | if (!vcpu->time_page) | |
842 | return 0; | |
843 | set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests); | |
844 | return 1; | |
845 | } | |
846 | ||
9ba075a6 AK |
847 | static bool msr_mtrr_valid(unsigned msr) |
848 | { | |
849 | switch (msr) { | |
850 | case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1: | |
851 | case MSR_MTRRfix64K_00000: | |
852 | case MSR_MTRRfix16K_80000: | |
853 | case MSR_MTRRfix16K_A0000: | |
854 | case MSR_MTRRfix4K_C0000: | |
855 | case MSR_MTRRfix4K_C8000: | |
856 | case MSR_MTRRfix4K_D0000: | |
857 | case MSR_MTRRfix4K_D8000: | |
858 | case MSR_MTRRfix4K_E0000: | |
859 | case MSR_MTRRfix4K_E8000: | |
860 | case MSR_MTRRfix4K_F0000: | |
861 | case MSR_MTRRfix4K_F8000: | |
862 | case MSR_MTRRdefType: | |
863 | case MSR_IA32_CR_PAT: | |
864 | return true; | |
865 | case 0x2f8: | |
866 | return true; | |
867 | } | |
868 | return false; | |
869 | } | |
870 | ||
d6289b93 MT |
871 | static bool valid_pat_type(unsigned t) |
872 | { | |
873 | return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */ | |
874 | } | |
875 | ||
876 | static bool valid_mtrr_type(unsigned t) | |
877 | { | |
878 | return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */ | |
879 | } | |
880 | ||
881 | static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
882 | { | |
883 | int i; | |
884 | ||
885 | if (!msr_mtrr_valid(msr)) | |
886 | return false; | |
887 | ||
888 | if (msr == MSR_IA32_CR_PAT) { | |
889 | for (i = 0; i < 8; i++) | |
890 | if (!valid_pat_type((data >> (i * 8)) & 0xff)) | |
891 | return false; | |
892 | return true; | |
893 | } else if (msr == MSR_MTRRdefType) { | |
894 | if (data & ~0xcff) | |
895 | return false; | |
896 | return valid_mtrr_type(data & 0xff); | |
897 | } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) { | |
898 | for (i = 0; i < 8 ; i++) | |
899 | if (!valid_mtrr_type((data >> (i * 8)) & 0xff)) | |
900 | return false; | |
901 | return true; | |
902 | } | |
903 | ||
904 | /* variable MTRRs */ | |
905 | return valid_mtrr_type(data & 0xff); | |
906 | } | |
907 | ||
9ba075a6 AK |
908 | static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
909 | { | |
0bed3b56 SY |
910 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; |
911 | ||
d6289b93 | 912 | if (!mtrr_valid(vcpu, msr, data)) |
9ba075a6 AK |
913 | return 1; |
914 | ||
0bed3b56 SY |
915 | if (msr == MSR_MTRRdefType) { |
916 | vcpu->arch.mtrr_state.def_type = data; | |
917 | vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10; | |
918 | } else if (msr == MSR_MTRRfix64K_00000) | |
919 | p[0] = data; | |
920 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
921 | p[1 + msr - MSR_MTRRfix16K_80000] = data; | |
922 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
923 | p[3 + msr - MSR_MTRRfix4K_C0000] = data; | |
924 | else if (msr == MSR_IA32_CR_PAT) | |
925 | vcpu->arch.pat = data; | |
926 | else { /* Variable MTRRs */ | |
927 | int idx, is_mtrr_mask; | |
928 | u64 *pt; | |
929 | ||
930 | idx = (msr - 0x200) / 2; | |
931 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
932 | if (!is_mtrr_mask) | |
933 | pt = | |
934 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
935 | else | |
936 | pt = | |
937 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
938 | *pt = data; | |
939 | } | |
940 | ||
941 | kvm_mmu_reset_context(vcpu); | |
9ba075a6 AK |
942 | return 0; |
943 | } | |
15c4a640 | 944 | |
890ca9ae | 945 | static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
15c4a640 | 946 | { |
890ca9ae HY |
947 | u64 mcg_cap = vcpu->arch.mcg_cap; |
948 | unsigned bank_num = mcg_cap & 0xff; | |
949 | ||
15c4a640 | 950 | switch (msr) { |
15c4a640 | 951 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 952 | vcpu->arch.mcg_status = data; |
15c4a640 | 953 | break; |
c7ac679c | 954 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
955 | if (!(mcg_cap & MCG_CTL_P)) |
956 | return 1; | |
957 | if (data != 0 && data != ~(u64)0) | |
958 | return -1; | |
959 | vcpu->arch.mcg_ctl = data; | |
960 | break; | |
961 | default: | |
962 | if (msr >= MSR_IA32_MC0_CTL && | |
963 | msr < MSR_IA32_MC0_CTL + 4 * bank_num) { | |
964 | u32 offset = msr - MSR_IA32_MC0_CTL; | |
965 | /* only 0 or all 1s can be written to IA32_MCi_CTL */ | |
966 | if ((offset & 0x3) == 0 && | |
967 | data != 0 && data != ~(u64)0) | |
968 | return -1; | |
969 | vcpu->arch.mce_banks[offset] = data; | |
970 | break; | |
971 | } | |
972 | return 1; | |
973 | } | |
974 | return 0; | |
975 | } | |
976 | ||
ffde22ac ES |
977 | static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) |
978 | { | |
979 | struct kvm *kvm = vcpu->kvm; | |
980 | int lm = is_long_mode(vcpu); | |
981 | u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 | |
982 | : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; | |
983 | u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 | |
984 | : kvm->arch.xen_hvm_config.blob_size_32; | |
985 | u32 page_num = data & ~PAGE_MASK; | |
986 | u64 page_addr = data & PAGE_MASK; | |
987 | u8 *page; | |
988 | int r; | |
989 | ||
990 | r = -E2BIG; | |
991 | if (page_num >= blob_size) | |
992 | goto out; | |
993 | r = -ENOMEM; | |
994 | page = kzalloc(PAGE_SIZE, GFP_KERNEL); | |
995 | if (!page) | |
996 | goto out; | |
997 | r = -EFAULT; | |
998 | if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE)) | |
999 | goto out_free; | |
1000 | if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE)) | |
1001 | goto out_free; | |
1002 | r = 0; | |
1003 | out_free: | |
1004 | kfree(page); | |
1005 | out: | |
1006 | return r; | |
1007 | } | |
1008 | ||
55cd8e5a GN |
1009 | static bool kvm_hv_hypercall_enabled(struct kvm *kvm) |
1010 | { | |
1011 | return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE; | |
1012 | } | |
1013 | ||
1014 | static bool kvm_hv_msr_partition_wide(u32 msr) | |
1015 | { | |
1016 | bool r = false; | |
1017 | switch (msr) { | |
1018 | case HV_X64_MSR_GUEST_OS_ID: | |
1019 | case HV_X64_MSR_HYPERCALL: | |
1020 | r = true; | |
1021 | break; | |
1022 | } | |
1023 | ||
1024 | return r; | |
1025 | } | |
1026 | ||
1027 | static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1028 | { | |
1029 | struct kvm *kvm = vcpu->kvm; | |
1030 | ||
1031 | switch (msr) { | |
1032 | case HV_X64_MSR_GUEST_OS_ID: | |
1033 | kvm->arch.hv_guest_os_id = data; | |
1034 | /* setting guest os id to zero disables hypercall page */ | |
1035 | if (!kvm->arch.hv_guest_os_id) | |
1036 | kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE; | |
1037 | break; | |
1038 | case HV_X64_MSR_HYPERCALL: { | |
1039 | u64 gfn; | |
1040 | unsigned long addr; | |
1041 | u8 instructions[4]; | |
1042 | ||
1043 | /* if guest os id is not set hypercall should remain disabled */ | |
1044 | if (!kvm->arch.hv_guest_os_id) | |
1045 | break; | |
1046 | if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) { | |
1047 | kvm->arch.hv_hypercall = data; | |
1048 | break; | |
1049 | } | |
1050 | gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT; | |
1051 | addr = gfn_to_hva(kvm, gfn); | |
1052 | if (kvm_is_error_hva(addr)) | |
1053 | return 1; | |
1054 | kvm_x86_ops->patch_hypercall(vcpu, instructions); | |
1055 | ((unsigned char *)instructions)[3] = 0xc3; /* ret */ | |
1056 | if (copy_to_user((void __user *)addr, instructions, 4)) | |
1057 | return 1; | |
1058 | kvm->arch.hv_hypercall = data; | |
1059 | break; | |
1060 | } | |
1061 | default: | |
1062 | pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " | |
1063 | "data 0x%llx\n", msr, data); | |
1064 | return 1; | |
1065 | } | |
1066 | return 0; | |
1067 | } | |
1068 | ||
1069 | static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1070 | { | |
10388a07 GN |
1071 | switch (msr) { |
1072 | case HV_X64_MSR_APIC_ASSIST_PAGE: { | |
1073 | unsigned long addr; | |
55cd8e5a | 1074 | |
10388a07 GN |
1075 | if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) { |
1076 | vcpu->arch.hv_vapic = data; | |
1077 | break; | |
1078 | } | |
1079 | addr = gfn_to_hva(vcpu->kvm, data >> | |
1080 | HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT); | |
1081 | if (kvm_is_error_hva(addr)) | |
1082 | return 1; | |
1083 | if (clear_user((void __user *)addr, PAGE_SIZE)) | |
1084 | return 1; | |
1085 | vcpu->arch.hv_vapic = data; | |
1086 | break; | |
1087 | } | |
1088 | case HV_X64_MSR_EOI: | |
1089 | return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data); | |
1090 | case HV_X64_MSR_ICR: | |
1091 | return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data); | |
1092 | case HV_X64_MSR_TPR: | |
1093 | return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data); | |
1094 | default: | |
1095 | pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " | |
1096 | "data 0x%llx\n", msr, data); | |
1097 | return 1; | |
1098 | } | |
1099 | ||
1100 | return 0; | |
55cd8e5a GN |
1101 | } |
1102 | ||
15c4a640 CO |
1103 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
1104 | { | |
1105 | switch (msr) { | |
15c4a640 CO |
1106 | case MSR_EFER: |
1107 | set_efer(vcpu, data); | |
1108 | break; | |
8f1589d9 AP |
1109 | case MSR_K7_HWCR: |
1110 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
1111 | if (data != 0) { | |
1112 | pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", | |
1113 | data); | |
1114 | return 1; | |
1115 | } | |
15c4a640 | 1116 | break; |
f7c6d140 AP |
1117 | case MSR_FAM10H_MMIO_CONF_BASE: |
1118 | if (data != 0) { | |
1119 | pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " | |
1120 | "0x%llx\n", data); | |
1121 | return 1; | |
1122 | } | |
15c4a640 | 1123 | break; |
c323c0e5 | 1124 | case MSR_AMD64_NB_CFG: |
c7ac679c | 1125 | break; |
b5e2fec0 AG |
1126 | case MSR_IA32_DEBUGCTLMSR: |
1127 | if (!data) { | |
1128 | /* We support the non-activated case already */ | |
1129 | break; | |
1130 | } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { | |
1131 | /* Values other than LBR and BTF are vendor-specific, | |
1132 | thus reserved and should throw a #GP */ | |
1133 | return 1; | |
1134 | } | |
1135 | pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", | |
1136 | __func__, data); | |
1137 | break; | |
15c4a640 CO |
1138 | case MSR_IA32_UCODE_REV: |
1139 | case MSR_IA32_UCODE_WRITE: | |
61a6bd67 | 1140 | case MSR_VM_HSAVE_PA: |
6098ca93 | 1141 | case MSR_AMD64_PATCH_LOADER: |
15c4a640 | 1142 | break; |
9ba075a6 AK |
1143 | case 0x200 ... 0x2ff: |
1144 | return set_msr_mtrr(vcpu, msr, data); | |
15c4a640 CO |
1145 | case MSR_IA32_APICBASE: |
1146 | kvm_set_apic_base(vcpu, data); | |
1147 | break; | |
0105d1a5 GN |
1148 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
1149 | return kvm_x2apic_msr_write(vcpu, msr, data); | |
15c4a640 | 1150 | case MSR_IA32_MISC_ENABLE: |
ad312c7c | 1151 | vcpu->arch.ia32_misc_enable_msr = data; |
15c4a640 | 1152 | break; |
18068523 GOC |
1153 | case MSR_KVM_WALL_CLOCK: |
1154 | vcpu->kvm->arch.wall_clock = data; | |
1155 | kvm_write_wall_clock(vcpu->kvm, data); | |
1156 | break; | |
1157 | case MSR_KVM_SYSTEM_TIME: { | |
1158 | if (vcpu->arch.time_page) { | |
1159 | kvm_release_page_dirty(vcpu->arch.time_page); | |
1160 | vcpu->arch.time_page = NULL; | |
1161 | } | |
1162 | ||
1163 | vcpu->arch.time = data; | |
1164 | ||
1165 | /* we verify if the enable bit is set... */ | |
1166 | if (!(data & 1)) | |
1167 | break; | |
1168 | ||
1169 | /* ...but clean it before doing the actual write */ | |
1170 | vcpu->arch.time_offset = data & ~(PAGE_MASK | 1); | |
1171 | ||
18068523 GOC |
1172 | vcpu->arch.time_page = |
1173 | gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT); | |
18068523 GOC |
1174 | |
1175 | if (is_error_page(vcpu->arch.time_page)) { | |
1176 | kvm_release_page_clean(vcpu->arch.time_page); | |
1177 | vcpu->arch.time_page = NULL; | |
1178 | } | |
1179 | ||
c8076604 | 1180 | kvm_request_guest_time_update(vcpu); |
18068523 GOC |
1181 | break; |
1182 | } | |
890ca9ae HY |
1183 | case MSR_IA32_MCG_CTL: |
1184 | case MSR_IA32_MCG_STATUS: | |
1185 | case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1: | |
1186 | return set_msr_mce(vcpu, msr, data); | |
71db6023 AP |
1187 | |
1188 | /* Performance counters are not protected by a CPUID bit, | |
1189 | * so we should check all of them in the generic path for the sake of | |
1190 | * cross vendor migration. | |
1191 | * Writing a zero into the event select MSRs disables them, | |
1192 | * which we perfectly emulate ;-). Any other value should be at least | |
1193 | * reported, some guests depend on them. | |
1194 | */ | |
1195 | case MSR_P6_EVNTSEL0: | |
1196 | case MSR_P6_EVNTSEL1: | |
1197 | case MSR_K7_EVNTSEL0: | |
1198 | case MSR_K7_EVNTSEL1: | |
1199 | case MSR_K7_EVNTSEL2: | |
1200 | case MSR_K7_EVNTSEL3: | |
1201 | if (data != 0) | |
1202 | pr_unimpl(vcpu, "unimplemented perfctr wrmsr: " | |
1203 | "0x%x data 0x%llx\n", msr, data); | |
1204 | break; | |
1205 | /* at least RHEL 4 unconditionally writes to the perfctr registers, | |
1206 | * so we ignore writes to make it happy. | |
1207 | */ | |
1208 | case MSR_P6_PERFCTR0: | |
1209 | case MSR_P6_PERFCTR1: | |
1210 | case MSR_K7_PERFCTR0: | |
1211 | case MSR_K7_PERFCTR1: | |
1212 | case MSR_K7_PERFCTR2: | |
1213 | case MSR_K7_PERFCTR3: | |
1214 | pr_unimpl(vcpu, "unimplemented perfctr wrmsr: " | |
1215 | "0x%x data 0x%llx\n", msr, data); | |
1216 | break; | |
55cd8e5a GN |
1217 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
1218 | if (kvm_hv_msr_partition_wide(msr)) { | |
1219 | int r; | |
1220 | mutex_lock(&vcpu->kvm->lock); | |
1221 | r = set_msr_hyperv_pw(vcpu, msr, data); | |
1222 | mutex_unlock(&vcpu->kvm->lock); | |
1223 | return r; | |
1224 | } else | |
1225 | return set_msr_hyperv(vcpu, msr, data); | |
1226 | break; | |
15c4a640 | 1227 | default: |
ffde22ac ES |
1228 | if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) |
1229 | return xen_hvm_config(vcpu, data); | |
ed85c068 AP |
1230 | if (!ignore_msrs) { |
1231 | pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", | |
1232 | msr, data); | |
1233 | return 1; | |
1234 | } else { | |
1235 | pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", | |
1236 | msr, data); | |
1237 | break; | |
1238 | } | |
15c4a640 CO |
1239 | } |
1240 | return 0; | |
1241 | } | |
1242 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
1243 | ||
1244 | ||
1245 | /* | |
1246 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
1247 | * Returns 0 on success, non-0 otherwise. | |
1248 | * Assumes vcpu_load() was already called. | |
1249 | */ | |
1250 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
1251 | { | |
1252 | return kvm_x86_ops->get_msr(vcpu, msr_index, pdata); | |
1253 | } | |
1254 | ||
9ba075a6 AK |
1255 | static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
1256 | { | |
0bed3b56 SY |
1257 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; |
1258 | ||
9ba075a6 AK |
1259 | if (!msr_mtrr_valid(msr)) |
1260 | return 1; | |
1261 | ||
0bed3b56 SY |
1262 | if (msr == MSR_MTRRdefType) |
1263 | *pdata = vcpu->arch.mtrr_state.def_type + | |
1264 | (vcpu->arch.mtrr_state.enabled << 10); | |
1265 | else if (msr == MSR_MTRRfix64K_00000) | |
1266 | *pdata = p[0]; | |
1267 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
1268 | *pdata = p[1 + msr - MSR_MTRRfix16K_80000]; | |
1269 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
1270 | *pdata = p[3 + msr - MSR_MTRRfix4K_C0000]; | |
1271 | else if (msr == MSR_IA32_CR_PAT) | |
1272 | *pdata = vcpu->arch.pat; | |
1273 | else { /* Variable MTRRs */ | |
1274 | int idx, is_mtrr_mask; | |
1275 | u64 *pt; | |
1276 | ||
1277 | idx = (msr - 0x200) / 2; | |
1278 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
1279 | if (!is_mtrr_mask) | |
1280 | pt = | |
1281 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
1282 | else | |
1283 | pt = | |
1284 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
1285 | *pdata = *pt; | |
1286 | } | |
1287 | ||
9ba075a6 AK |
1288 | return 0; |
1289 | } | |
1290 | ||
890ca9ae | 1291 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
15c4a640 CO |
1292 | { |
1293 | u64 data; | |
890ca9ae HY |
1294 | u64 mcg_cap = vcpu->arch.mcg_cap; |
1295 | unsigned bank_num = mcg_cap & 0xff; | |
15c4a640 CO |
1296 | |
1297 | switch (msr) { | |
15c4a640 CO |
1298 | case MSR_IA32_P5_MC_ADDR: |
1299 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
1300 | data = 0; |
1301 | break; | |
15c4a640 | 1302 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
1303 | data = vcpu->arch.mcg_cap; |
1304 | break; | |
c7ac679c | 1305 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
1306 | if (!(mcg_cap & MCG_CTL_P)) |
1307 | return 1; | |
1308 | data = vcpu->arch.mcg_ctl; | |
1309 | break; | |
1310 | case MSR_IA32_MCG_STATUS: | |
1311 | data = vcpu->arch.mcg_status; | |
1312 | break; | |
1313 | default: | |
1314 | if (msr >= MSR_IA32_MC0_CTL && | |
1315 | msr < MSR_IA32_MC0_CTL + 4 * bank_num) { | |
1316 | u32 offset = msr - MSR_IA32_MC0_CTL; | |
1317 | data = vcpu->arch.mce_banks[offset]; | |
1318 | break; | |
1319 | } | |
1320 | return 1; | |
1321 | } | |
1322 | *pdata = data; | |
1323 | return 0; | |
1324 | } | |
1325 | ||
55cd8e5a GN |
1326 | static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
1327 | { | |
1328 | u64 data = 0; | |
1329 | struct kvm *kvm = vcpu->kvm; | |
1330 | ||
1331 | switch (msr) { | |
1332 | case HV_X64_MSR_GUEST_OS_ID: | |
1333 | data = kvm->arch.hv_guest_os_id; | |
1334 | break; | |
1335 | case HV_X64_MSR_HYPERCALL: | |
1336 | data = kvm->arch.hv_hypercall; | |
1337 | break; | |
1338 | default: | |
1339 | pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); | |
1340 | return 1; | |
1341 | } | |
1342 | ||
1343 | *pdata = data; | |
1344 | return 0; | |
1345 | } | |
1346 | ||
1347 | static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) | |
1348 | { | |
1349 | u64 data = 0; | |
1350 | ||
1351 | switch (msr) { | |
1352 | case HV_X64_MSR_VP_INDEX: { | |
1353 | int r; | |
1354 | struct kvm_vcpu *v; | |
1355 | kvm_for_each_vcpu(r, v, vcpu->kvm) | |
1356 | if (v == vcpu) | |
1357 | data = r; | |
1358 | break; | |
1359 | } | |
10388a07 GN |
1360 | case HV_X64_MSR_EOI: |
1361 | return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata); | |
1362 | case HV_X64_MSR_ICR: | |
1363 | return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata); | |
1364 | case HV_X64_MSR_TPR: | |
1365 | return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata); | |
55cd8e5a GN |
1366 | default: |
1367 | pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); | |
1368 | return 1; | |
1369 | } | |
1370 | *pdata = data; | |
1371 | return 0; | |
1372 | } | |
1373 | ||
890ca9ae HY |
1374 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
1375 | { | |
1376 | u64 data; | |
1377 | ||
1378 | switch (msr) { | |
890ca9ae | 1379 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 1380 | case MSR_IA32_UCODE_REV: |
15c4a640 | 1381 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
1382 | case MSR_IA32_DEBUGCTLMSR: |
1383 | case MSR_IA32_LASTBRANCHFROMIP: | |
1384 | case MSR_IA32_LASTBRANCHTOIP: | |
1385 | case MSR_IA32_LASTINTFROMIP: | |
1386 | case MSR_IA32_LASTINTTOIP: | |
60af2ecd JSR |
1387 | case MSR_K8_SYSCFG: |
1388 | case MSR_K7_HWCR: | |
61a6bd67 | 1389 | case MSR_VM_HSAVE_PA: |
1f3ee616 AS |
1390 | case MSR_P6_PERFCTR0: |
1391 | case MSR_P6_PERFCTR1: | |
7fe29e0f AS |
1392 | case MSR_P6_EVNTSEL0: |
1393 | case MSR_P6_EVNTSEL1: | |
9e699624 | 1394 | case MSR_K7_EVNTSEL0: |
1f3ee616 | 1395 | case MSR_K7_PERFCTR0: |
1fdbd48c | 1396 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 1397 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 1398 | case MSR_FAM10H_MMIO_CONF_BASE: |
15c4a640 CO |
1399 | data = 0; |
1400 | break; | |
9ba075a6 AK |
1401 | case MSR_MTRRcap: |
1402 | data = 0x500 | KVM_NR_VAR_MTRR; | |
1403 | break; | |
1404 | case 0x200 ... 0x2ff: | |
1405 | return get_msr_mtrr(vcpu, msr, pdata); | |
15c4a640 CO |
1406 | case 0xcd: /* fsb frequency */ |
1407 | data = 3; | |
1408 | break; | |
1409 | case MSR_IA32_APICBASE: | |
1410 | data = kvm_get_apic_base(vcpu); | |
1411 | break; | |
0105d1a5 GN |
1412 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
1413 | return kvm_x2apic_msr_read(vcpu, msr, pdata); | |
1414 | break; | |
15c4a640 | 1415 | case MSR_IA32_MISC_ENABLE: |
ad312c7c | 1416 | data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 1417 | break; |
847f0ad8 AG |
1418 | case MSR_IA32_PERF_STATUS: |
1419 | /* TSC increment by tick */ | |
1420 | data = 1000ULL; | |
1421 | /* CPU multiplier */ | |
1422 | data |= (((uint64_t)4ULL) << 40); | |
1423 | break; | |
15c4a640 | 1424 | case MSR_EFER: |
ad312c7c | 1425 | data = vcpu->arch.shadow_efer; |
15c4a640 | 1426 | break; |
18068523 GOC |
1427 | case MSR_KVM_WALL_CLOCK: |
1428 | data = vcpu->kvm->arch.wall_clock; | |
1429 | break; | |
1430 | case MSR_KVM_SYSTEM_TIME: | |
1431 | data = vcpu->arch.time; | |
1432 | break; | |
890ca9ae HY |
1433 | case MSR_IA32_P5_MC_ADDR: |
1434 | case MSR_IA32_P5_MC_TYPE: | |
1435 | case MSR_IA32_MCG_CAP: | |
1436 | case MSR_IA32_MCG_CTL: | |
1437 | case MSR_IA32_MCG_STATUS: | |
1438 | case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1: | |
1439 | return get_msr_mce(vcpu, msr, pdata); | |
55cd8e5a GN |
1440 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
1441 | if (kvm_hv_msr_partition_wide(msr)) { | |
1442 | int r; | |
1443 | mutex_lock(&vcpu->kvm->lock); | |
1444 | r = get_msr_hyperv_pw(vcpu, msr, pdata); | |
1445 | mutex_unlock(&vcpu->kvm->lock); | |
1446 | return r; | |
1447 | } else | |
1448 | return get_msr_hyperv(vcpu, msr, pdata); | |
1449 | break; | |
15c4a640 | 1450 | default: |
ed85c068 AP |
1451 | if (!ignore_msrs) { |
1452 | pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr); | |
1453 | return 1; | |
1454 | } else { | |
1455 | pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr); | |
1456 | data = 0; | |
1457 | } | |
1458 | break; | |
15c4a640 CO |
1459 | } |
1460 | *pdata = data; | |
1461 | return 0; | |
1462 | } | |
1463 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
1464 | ||
313a3dc7 CO |
1465 | /* |
1466 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
1467 | * | |
1468 | * @return number of msrs set successfully. | |
1469 | */ | |
1470 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
1471 | struct kvm_msr_entry *entries, | |
1472 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
1473 | unsigned index, u64 *data)) | |
1474 | { | |
f656ce01 | 1475 | int i, idx; |
313a3dc7 CO |
1476 | |
1477 | vcpu_load(vcpu); | |
1478 | ||
f656ce01 | 1479 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
313a3dc7 CO |
1480 | for (i = 0; i < msrs->nmsrs; ++i) |
1481 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
1482 | break; | |
f656ce01 | 1483 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 CO |
1484 | |
1485 | vcpu_put(vcpu); | |
1486 | ||
1487 | return i; | |
1488 | } | |
1489 | ||
1490 | /* | |
1491 | * Read or write a bunch of msrs. Parameters are user addresses. | |
1492 | * | |
1493 | * @return number of msrs set successfully. | |
1494 | */ | |
1495 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
1496 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
1497 | unsigned index, u64 *data), | |
1498 | int writeback) | |
1499 | { | |
1500 | struct kvm_msrs msrs; | |
1501 | struct kvm_msr_entry *entries; | |
1502 | int r, n; | |
1503 | unsigned size; | |
1504 | ||
1505 | r = -EFAULT; | |
1506 | if (copy_from_user(&msrs, user_msrs, sizeof msrs)) | |
1507 | goto out; | |
1508 | ||
1509 | r = -E2BIG; | |
1510 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
1511 | goto out; | |
1512 | ||
1513 | r = -ENOMEM; | |
1514 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; | |
1515 | entries = vmalloc(size); | |
1516 | if (!entries) | |
1517 | goto out; | |
1518 | ||
1519 | r = -EFAULT; | |
1520 | if (copy_from_user(entries, user_msrs->entries, size)) | |
1521 | goto out_free; | |
1522 | ||
1523 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
1524 | if (r < 0) | |
1525 | goto out_free; | |
1526 | ||
1527 | r = -EFAULT; | |
1528 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
1529 | goto out_free; | |
1530 | ||
1531 | r = n; | |
1532 | ||
1533 | out_free: | |
1534 | vfree(entries); | |
1535 | out: | |
1536 | return r; | |
1537 | } | |
1538 | ||
018d00d2 ZX |
1539 | int kvm_dev_ioctl_check_extension(long ext) |
1540 | { | |
1541 | int r; | |
1542 | ||
1543 | switch (ext) { | |
1544 | case KVM_CAP_IRQCHIP: | |
1545 | case KVM_CAP_HLT: | |
1546 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 1547 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 1548 | case KVM_CAP_EXT_CPUID: |
c8076604 | 1549 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 1550 | case KVM_CAP_PIT: |
a28e4f5a | 1551 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 1552 | case KVM_CAP_MP_STATE: |
ed848624 | 1553 | case KVM_CAP_SYNC_MMU: |
52d939a0 | 1554 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 1555 | case KVM_CAP_IRQ_INJECT_STATUS: |
e56d532f | 1556 | case KVM_CAP_ASSIGN_DEV_IRQ: |
721eecbf | 1557 | case KVM_CAP_IRQFD: |
d34e6b17 | 1558 | case KVM_CAP_IOEVENTFD: |
c5ff41ce | 1559 | case KVM_CAP_PIT2: |
e9f42757 | 1560 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 1561 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
ffde22ac | 1562 | case KVM_CAP_XEN_HVM: |
afbcf7ab | 1563 | case KVM_CAP_ADJUST_CLOCK: |
3cfc3092 | 1564 | case KVM_CAP_VCPU_EVENTS: |
55cd8e5a | 1565 | case KVM_CAP_HYPERV: |
10388a07 | 1566 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 1567 | case KVM_CAP_HYPERV_SPIN: |
018d00d2 ZX |
1568 | r = 1; |
1569 | break; | |
542472b5 LV |
1570 | case KVM_CAP_COALESCED_MMIO: |
1571 | r = KVM_COALESCED_MMIO_PAGE_OFFSET; | |
1572 | break; | |
774ead3a AK |
1573 | case KVM_CAP_VAPIC: |
1574 | r = !kvm_x86_ops->cpu_has_accelerated_tpr(); | |
1575 | break; | |
f725230a AK |
1576 | case KVM_CAP_NR_VCPUS: |
1577 | r = KVM_MAX_VCPUS; | |
1578 | break; | |
a988b910 AK |
1579 | case KVM_CAP_NR_MEMSLOTS: |
1580 | r = KVM_MEMORY_SLOTS; | |
1581 | break; | |
a68a6a72 MT |
1582 | case KVM_CAP_PV_MMU: /* obsolete */ |
1583 | r = 0; | |
2f333bcb | 1584 | break; |
62c476c7 | 1585 | case KVM_CAP_IOMMU: |
19de40a8 | 1586 | r = iommu_found(); |
62c476c7 | 1587 | break; |
890ca9ae HY |
1588 | case KVM_CAP_MCE: |
1589 | r = KVM_MAX_MCE_BANKS; | |
1590 | break; | |
018d00d2 ZX |
1591 | default: |
1592 | r = 0; | |
1593 | break; | |
1594 | } | |
1595 | return r; | |
1596 | ||
1597 | } | |
1598 | ||
043405e1 CO |
1599 | long kvm_arch_dev_ioctl(struct file *filp, |
1600 | unsigned int ioctl, unsigned long arg) | |
1601 | { | |
1602 | void __user *argp = (void __user *)arg; | |
1603 | long r; | |
1604 | ||
1605 | switch (ioctl) { | |
1606 | case KVM_GET_MSR_INDEX_LIST: { | |
1607 | struct kvm_msr_list __user *user_msr_list = argp; | |
1608 | struct kvm_msr_list msr_list; | |
1609 | unsigned n; | |
1610 | ||
1611 | r = -EFAULT; | |
1612 | if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) | |
1613 | goto out; | |
1614 | n = msr_list.nmsrs; | |
1615 | msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs); | |
1616 | if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) | |
1617 | goto out; | |
1618 | r = -E2BIG; | |
e125e7b6 | 1619 | if (n < msr_list.nmsrs) |
043405e1 CO |
1620 | goto out; |
1621 | r = -EFAULT; | |
1622 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
1623 | num_msrs_to_save * sizeof(u32))) | |
1624 | goto out; | |
e125e7b6 | 1625 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 CO |
1626 | &emulated_msrs, |
1627 | ARRAY_SIZE(emulated_msrs) * sizeof(u32))) | |
1628 | goto out; | |
1629 | r = 0; | |
1630 | break; | |
1631 | } | |
674eea0f AK |
1632 | case KVM_GET_SUPPORTED_CPUID: { |
1633 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
1634 | struct kvm_cpuid2 cpuid; | |
1635 | ||
1636 | r = -EFAULT; | |
1637 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
1638 | goto out; | |
1639 | r = kvm_dev_ioctl_get_supported_cpuid(&cpuid, | |
19355475 | 1640 | cpuid_arg->entries); |
674eea0f AK |
1641 | if (r) |
1642 | goto out; | |
1643 | ||
1644 | r = -EFAULT; | |
1645 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
1646 | goto out; | |
1647 | r = 0; | |
1648 | break; | |
1649 | } | |
890ca9ae HY |
1650 | case KVM_X86_GET_MCE_CAP_SUPPORTED: { |
1651 | u64 mce_cap; | |
1652 | ||
1653 | mce_cap = KVM_MCE_CAP_SUPPORTED; | |
1654 | r = -EFAULT; | |
1655 | if (copy_to_user(argp, &mce_cap, sizeof mce_cap)) | |
1656 | goto out; | |
1657 | r = 0; | |
1658 | break; | |
1659 | } | |
043405e1 CO |
1660 | default: |
1661 | r = -EINVAL; | |
1662 | } | |
1663 | out: | |
1664 | return r; | |
1665 | } | |
1666 | ||
313a3dc7 CO |
1667 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
1668 | { | |
1669 | kvm_x86_ops->vcpu_load(vcpu, cpu); | |
6b7d7e76 ZA |
1670 | if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) { |
1671 | unsigned long khz = cpufreq_quick_get(cpu); | |
1672 | if (!khz) | |
1673 | khz = tsc_khz; | |
1674 | per_cpu(cpu_tsc_khz, cpu) = khz; | |
1675 | } | |
c8076604 | 1676 | kvm_request_guest_time_update(vcpu); |
313a3dc7 CO |
1677 | } |
1678 | ||
1679 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) | |
1680 | { | |
9327fd11 | 1681 | kvm_put_guest_fpu(vcpu); |
02daab21 | 1682 | kvm_x86_ops->vcpu_put(vcpu); |
313a3dc7 CO |
1683 | } |
1684 | ||
07716717 | 1685 | static int is_efer_nx(void) |
313a3dc7 | 1686 | { |
e286e86e | 1687 | unsigned long long efer = 0; |
313a3dc7 | 1688 | |
e286e86e | 1689 | rdmsrl_safe(MSR_EFER, &efer); |
07716717 DK |
1690 | return efer & EFER_NX; |
1691 | } | |
1692 | ||
1693 | static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu) | |
1694 | { | |
1695 | int i; | |
1696 | struct kvm_cpuid_entry2 *e, *entry; | |
1697 | ||
313a3dc7 | 1698 | entry = NULL; |
ad312c7c ZX |
1699 | for (i = 0; i < vcpu->arch.cpuid_nent; ++i) { |
1700 | e = &vcpu->arch.cpuid_entries[i]; | |
313a3dc7 CO |
1701 | if (e->function == 0x80000001) { |
1702 | entry = e; | |
1703 | break; | |
1704 | } | |
1705 | } | |
07716717 | 1706 | if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) { |
313a3dc7 CO |
1707 | entry->edx &= ~(1 << 20); |
1708 | printk(KERN_INFO "kvm: guest NX capability removed\n"); | |
1709 | } | |
1710 | } | |
1711 | ||
07716717 | 1712 | /* when an old userspace process fills a new kernel module */ |
313a3dc7 CO |
1713 | static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu, |
1714 | struct kvm_cpuid *cpuid, | |
1715 | struct kvm_cpuid_entry __user *entries) | |
07716717 DK |
1716 | { |
1717 | int r, i; | |
1718 | struct kvm_cpuid_entry *cpuid_entries; | |
1719 | ||
1720 | r = -E2BIG; | |
1721 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) | |
1722 | goto out; | |
1723 | r = -ENOMEM; | |
1724 | cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent); | |
1725 | if (!cpuid_entries) | |
1726 | goto out; | |
1727 | r = -EFAULT; | |
1728 | if (copy_from_user(cpuid_entries, entries, | |
1729 | cpuid->nent * sizeof(struct kvm_cpuid_entry))) | |
1730 | goto out_free; | |
1731 | for (i = 0; i < cpuid->nent; i++) { | |
ad312c7c ZX |
1732 | vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function; |
1733 | vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax; | |
1734 | vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx; | |
1735 | vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx; | |
1736 | vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx; | |
1737 | vcpu->arch.cpuid_entries[i].index = 0; | |
1738 | vcpu->arch.cpuid_entries[i].flags = 0; | |
1739 | vcpu->arch.cpuid_entries[i].padding[0] = 0; | |
1740 | vcpu->arch.cpuid_entries[i].padding[1] = 0; | |
1741 | vcpu->arch.cpuid_entries[i].padding[2] = 0; | |
1742 | } | |
1743 | vcpu->arch.cpuid_nent = cpuid->nent; | |
07716717 DK |
1744 | cpuid_fix_nx_cap(vcpu); |
1745 | r = 0; | |
fc61b800 | 1746 | kvm_apic_set_version(vcpu); |
0e851880 | 1747 | kvm_x86_ops->cpuid_update(vcpu); |
07716717 DK |
1748 | |
1749 | out_free: | |
1750 | vfree(cpuid_entries); | |
1751 | out: | |
1752 | return r; | |
1753 | } | |
1754 | ||
1755 | static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu, | |
19355475 AS |
1756 | struct kvm_cpuid2 *cpuid, |
1757 | struct kvm_cpuid_entry2 __user *entries) | |
313a3dc7 CO |
1758 | { |
1759 | int r; | |
1760 | ||
1761 | r = -E2BIG; | |
1762 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) | |
1763 | goto out; | |
1764 | r = -EFAULT; | |
ad312c7c | 1765 | if (copy_from_user(&vcpu->arch.cpuid_entries, entries, |
07716717 | 1766 | cpuid->nent * sizeof(struct kvm_cpuid_entry2))) |
313a3dc7 | 1767 | goto out; |
ad312c7c | 1768 | vcpu->arch.cpuid_nent = cpuid->nent; |
fc61b800 | 1769 | kvm_apic_set_version(vcpu); |
0e851880 | 1770 | kvm_x86_ops->cpuid_update(vcpu); |
313a3dc7 CO |
1771 | return 0; |
1772 | ||
1773 | out: | |
1774 | return r; | |
1775 | } | |
1776 | ||
07716717 | 1777 | static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu, |
19355475 AS |
1778 | struct kvm_cpuid2 *cpuid, |
1779 | struct kvm_cpuid_entry2 __user *entries) | |
07716717 DK |
1780 | { |
1781 | int r; | |
1782 | ||
1783 | r = -E2BIG; | |
ad312c7c | 1784 | if (cpuid->nent < vcpu->arch.cpuid_nent) |
07716717 DK |
1785 | goto out; |
1786 | r = -EFAULT; | |
ad312c7c | 1787 | if (copy_to_user(entries, &vcpu->arch.cpuid_entries, |
19355475 | 1788 | vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2))) |
07716717 DK |
1789 | goto out; |
1790 | return 0; | |
1791 | ||
1792 | out: | |
ad312c7c | 1793 | cpuid->nent = vcpu->arch.cpuid_nent; |
07716717 DK |
1794 | return r; |
1795 | } | |
1796 | ||
07716717 | 1797 | static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function, |
19355475 | 1798 | u32 index) |
07716717 DK |
1799 | { |
1800 | entry->function = function; | |
1801 | entry->index = index; | |
1802 | cpuid_count(entry->function, entry->index, | |
19355475 | 1803 | &entry->eax, &entry->ebx, &entry->ecx, &entry->edx); |
07716717 DK |
1804 | entry->flags = 0; |
1805 | } | |
1806 | ||
7faa4ee1 AK |
1807 | #define F(x) bit(X86_FEATURE_##x) |
1808 | ||
07716717 DK |
1809 | static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, |
1810 | u32 index, int *nent, int maxnent) | |
1811 | { | |
7faa4ee1 | 1812 | unsigned f_nx = is_efer_nx() ? F(NX) : 0; |
07716717 | 1813 | #ifdef CONFIG_X86_64 |
17cc3935 SY |
1814 | unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL) |
1815 | ? F(GBPAGES) : 0; | |
7faa4ee1 AK |
1816 | unsigned f_lm = F(LM); |
1817 | #else | |
17cc3935 | 1818 | unsigned f_gbpages = 0; |
7faa4ee1 | 1819 | unsigned f_lm = 0; |
07716717 | 1820 | #endif |
4e47c7a6 | 1821 | unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0; |
7faa4ee1 AK |
1822 | |
1823 | /* cpuid 1.edx */ | |
1824 | const u32 kvm_supported_word0_x86_features = | |
1825 | F(FPU) | F(VME) | F(DE) | F(PSE) | | |
1826 | F(TSC) | F(MSR) | F(PAE) | F(MCE) | | |
1827 | F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) | | |
1828 | F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | | |
1829 | F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) | | |
1830 | 0 /* Reserved, DS, ACPI */ | F(MMX) | | |
1831 | F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) | | |
1832 | 0 /* HTT, TM, Reserved, PBE */; | |
1833 | /* cpuid 0x80000001.edx */ | |
1834 | const u32 kvm_supported_word1_x86_features = | |
1835 | F(FPU) | F(VME) | F(DE) | F(PSE) | | |
1836 | F(TSC) | F(MSR) | F(PAE) | F(MCE) | | |
1837 | F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) | | |
1838 | F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | | |
1839 | F(PAT) | F(PSE36) | 0 /* Reserved */ | | |
1840 | f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) | | |
4e47c7a6 | 1841 | F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp | |
7faa4ee1 AK |
1842 | 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW); |
1843 | /* cpuid 1.ecx */ | |
1844 | const u32 kvm_supported_word4_x86_features = | |
d149c731 AK |
1845 | F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ | |
1846 | 0 /* DS-CPL, VMX, SMX, EST */ | | |
1847 | 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ | | |
1848 | 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ | | |
1849 | 0 /* Reserved, DCA */ | F(XMM4_1) | | |
0105d1a5 | 1850 | F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) | |
d149c731 | 1851 | 0 /* Reserved, XSAVE, OSXSAVE */; |
7faa4ee1 | 1852 | /* cpuid 0x80000001.ecx */ |
07716717 | 1853 | const u32 kvm_supported_word6_x86_features = |
7faa4ee1 AK |
1854 | F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ | |
1855 | F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) | | |
1856 | F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) | | |
1857 | 0 /* SKINIT */ | 0 /* WDT */; | |
07716717 | 1858 | |
19355475 | 1859 | /* all calls to cpuid_count() should be made on the same cpu */ |
07716717 DK |
1860 | get_cpu(); |
1861 | do_cpuid_1_ent(entry, function, index); | |
1862 | ++*nent; | |
1863 | ||
1864 | switch (function) { | |
1865 | case 0: | |
1866 | entry->eax = min(entry->eax, (u32)0xb); | |
1867 | break; | |
1868 | case 1: | |
1869 | entry->edx &= kvm_supported_word0_x86_features; | |
7faa4ee1 | 1870 | entry->ecx &= kvm_supported_word4_x86_features; |
0d1de2d9 GN |
1871 | /* we support x2apic emulation even if host does not support |
1872 | * it since we emulate x2apic in software */ | |
1873 | entry->ecx |= F(X2APIC); | |
07716717 DK |
1874 | break; |
1875 | /* function 2 entries are STATEFUL. That is, repeated cpuid commands | |
1876 | * may return different values. This forces us to get_cpu() before | |
1877 | * issuing the first command, and also to emulate this annoying behavior | |
1878 | * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */ | |
1879 | case 2: { | |
1880 | int t, times = entry->eax & 0xff; | |
1881 | ||
1882 | entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC; | |
0fdf8e59 | 1883 | entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT; |
07716717 DK |
1884 | for (t = 1; t < times && *nent < maxnent; ++t) { |
1885 | do_cpuid_1_ent(&entry[t], function, 0); | |
1886 | entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC; | |
1887 | ++*nent; | |
1888 | } | |
1889 | break; | |
1890 | } | |
1891 | /* function 4 and 0xb have additional index. */ | |
1892 | case 4: { | |
14af3f3c | 1893 | int i, cache_type; |
07716717 DK |
1894 | |
1895 | entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
1896 | /* read more entries until cache_type is zero */ | |
14af3f3c HH |
1897 | for (i = 1; *nent < maxnent; ++i) { |
1898 | cache_type = entry[i - 1].eax & 0x1f; | |
07716717 DK |
1899 | if (!cache_type) |
1900 | break; | |
14af3f3c HH |
1901 | do_cpuid_1_ent(&entry[i], function, i); |
1902 | entry[i].flags |= | |
07716717 DK |
1903 | KVM_CPUID_FLAG_SIGNIFCANT_INDEX; |
1904 | ++*nent; | |
1905 | } | |
1906 | break; | |
1907 | } | |
1908 | case 0xb: { | |
14af3f3c | 1909 | int i, level_type; |
07716717 DK |
1910 | |
1911 | entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
1912 | /* read more entries until level_type is zero */ | |
14af3f3c | 1913 | for (i = 1; *nent < maxnent; ++i) { |
0853d2c1 | 1914 | level_type = entry[i - 1].ecx & 0xff00; |
07716717 DK |
1915 | if (!level_type) |
1916 | break; | |
14af3f3c HH |
1917 | do_cpuid_1_ent(&entry[i], function, i); |
1918 | entry[i].flags |= | |
07716717 DK |
1919 | KVM_CPUID_FLAG_SIGNIFCANT_INDEX; |
1920 | ++*nent; | |
1921 | } | |
1922 | break; | |
1923 | } | |
1924 | case 0x80000000: | |
1925 | entry->eax = min(entry->eax, 0x8000001a); | |
1926 | break; | |
1927 | case 0x80000001: | |
1928 | entry->edx &= kvm_supported_word1_x86_features; | |
1929 | entry->ecx &= kvm_supported_word6_x86_features; | |
1930 | break; | |
1931 | } | |
1932 | put_cpu(); | |
1933 | } | |
1934 | ||
7faa4ee1 AK |
1935 | #undef F |
1936 | ||
674eea0f | 1937 | static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid, |
19355475 | 1938 | struct kvm_cpuid_entry2 __user *entries) |
07716717 DK |
1939 | { |
1940 | struct kvm_cpuid_entry2 *cpuid_entries; | |
1941 | int limit, nent = 0, r = -E2BIG; | |
1942 | u32 func; | |
1943 | ||
1944 | if (cpuid->nent < 1) | |
1945 | goto out; | |
6a544355 AK |
1946 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) |
1947 | cpuid->nent = KVM_MAX_CPUID_ENTRIES; | |
07716717 DK |
1948 | r = -ENOMEM; |
1949 | cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent); | |
1950 | if (!cpuid_entries) | |
1951 | goto out; | |
1952 | ||
1953 | do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent); | |
1954 | limit = cpuid_entries[0].eax; | |
1955 | for (func = 1; func <= limit && nent < cpuid->nent; ++func) | |
1956 | do_cpuid_ent(&cpuid_entries[nent], func, 0, | |
19355475 | 1957 | &nent, cpuid->nent); |
07716717 DK |
1958 | r = -E2BIG; |
1959 | if (nent >= cpuid->nent) | |
1960 | goto out_free; | |
1961 | ||
1962 | do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent); | |
1963 | limit = cpuid_entries[nent - 1].eax; | |
1964 | for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func) | |
1965 | do_cpuid_ent(&cpuid_entries[nent], func, 0, | |
19355475 | 1966 | &nent, cpuid->nent); |
cb007648 MM |
1967 | r = -E2BIG; |
1968 | if (nent >= cpuid->nent) | |
1969 | goto out_free; | |
1970 | ||
07716717 DK |
1971 | r = -EFAULT; |
1972 | if (copy_to_user(entries, cpuid_entries, | |
19355475 | 1973 | nent * sizeof(struct kvm_cpuid_entry2))) |
07716717 DK |
1974 | goto out_free; |
1975 | cpuid->nent = nent; | |
1976 | r = 0; | |
1977 | ||
1978 | out_free: | |
1979 | vfree(cpuid_entries); | |
1980 | out: | |
1981 | return r; | |
1982 | } | |
1983 | ||
313a3dc7 CO |
1984 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
1985 | struct kvm_lapic_state *s) | |
1986 | { | |
1987 | vcpu_load(vcpu); | |
ad312c7c | 1988 | memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s); |
313a3dc7 CO |
1989 | vcpu_put(vcpu); |
1990 | ||
1991 | return 0; | |
1992 | } | |
1993 | ||
1994 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
1995 | struct kvm_lapic_state *s) | |
1996 | { | |
1997 | vcpu_load(vcpu); | |
ad312c7c | 1998 | memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s); |
313a3dc7 | 1999 | kvm_apic_post_state_restore(vcpu); |
cb142eb7 | 2000 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
2001 | vcpu_put(vcpu); |
2002 | ||
2003 | return 0; | |
2004 | } | |
2005 | ||
f77bc6a4 ZX |
2006 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
2007 | struct kvm_interrupt *irq) | |
2008 | { | |
2009 | if (irq->irq < 0 || irq->irq >= 256) | |
2010 | return -EINVAL; | |
2011 | if (irqchip_in_kernel(vcpu->kvm)) | |
2012 | return -ENXIO; | |
2013 | vcpu_load(vcpu); | |
2014 | ||
66fd3f7f | 2015 | kvm_queue_interrupt(vcpu, irq->irq, false); |
f77bc6a4 ZX |
2016 | |
2017 | vcpu_put(vcpu); | |
2018 | ||
2019 | return 0; | |
2020 | } | |
2021 | ||
c4abb7c9 JK |
2022 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
2023 | { | |
2024 | vcpu_load(vcpu); | |
2025 | kvm_inject_nmi(vcpu); | |
2026 | vcpu_put(vcpu); | |
2027 | ||
2028 | return 0; | |
2029 | } | |
2030 | ||
b209749f AK |
2031 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
2032 | struct kvm_tpr_access_ctl *tac) | |
2033 | { | |
2034 | if (tac->flags) | |
2035 | return -EINVAL; | |
2036 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
2037 | return 0; | |
2038 | } | |
2039 | ||
890ca9ae HY |
2040 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
2041 | u64 mcg_cap) | |
2042 | { | |
2043 | int r; | |
2044 | unsigned bank_num = mcg_cap & 0xff, bank; | |
2045 | ||
2046 | r = -EINVAL; | |
a9e38c3e | 2047 | if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) |
890ca9ae HY |
2048 | goto out; |
2049 | if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000)) | |
2050 | goto out; | |
2051 | r = 0; | |
2052 | vcpu->arch.mcg_cap = mcg_cap; | |
2053 | /* Init IA32_MCG_CTL to all 1s */ | |
2054 | if (mcg_cap & MCG_CTL_P) | |
2055 | vcpu->arch.mcg_ctl = ~(u64)0; | |
2056 | /* Init IA32_MCi_CTL to all 1s */ | |
2057 | for (bank = 0; bank < bank_num; bank++) | |
2058 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
2059 | out: | |
2060 | return r; | |
2061 | } | |
2062 | ||
2063 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
2064 | struct kvm_x86_mce *mce) | |
2065 | { | |
2066 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
2067 | unsigned bank_num = mcg_cap & 0xff; | |
2068 | u64 *banks = vcpu->arch.mce_banks; | |
2069 | ||
2070 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
2071 | return -EINVAL; | |
2072 | /* | |
2073 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
2074 | * reporting is disabled | |
2075 | */ | |
2076 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
2077 | vcpu->arch.mcg_ctl != ~(u64)0) | |
2078 | return 0; | |
2079 | banks += 4 * mce->bank; | |
2080 | /* | |
2081 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
2082 | * reporting is disabled for the bank | |
2083 | */ | |
2084 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
2085 | return 0; | |
2086 | if (mce->status & MCI_STATUS_UC) { | |
2087 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
fc78f519 | 2088 | !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { |
890ca9ae HY |
2089 | printk(KERN_DEBUG "kvm: set_mce: " |
2090 | "injects mce exception while " | |
2091 | "previous one is in progress!\n"); | |
2092 | set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests); | |
2093 | return 0; | |
2094 | } | |
2095 | if (banks[1] & MCI_STATUS_VAL) | |
2096 | mce->status |= MCI_STATUS_OVER; | |
2097 | banks[2] = mce->addr; | |
2098 | banks[3] = mce->misc; | |
2099 | vcpu->arch.mcg_status = mce->mcg_status; | |
2100 | banks[1] = mce->status; | |
2101 | kvm_queue_exception(vcpu, MC_VECTOR); | |
2102 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
2103 | || !(banks[1] & MCI_STATUS_UC)) { | |
2104 | if (banks[1] & MCI_STATUS_VAL) | |
2105 | mce->status |= MCI_STATUS_OVER; | |
2106 | banks[2] = mce->addr; | |
2107 | banks[3] = mce->misc; | |
2108 | banks[1] = mce->status; | |
2109 | } else | |
2110 | banks[1] |= MCI_STATUS_OVER; | |
2111 | return 0; | |
2112 | } | |
2113 | ||
3cfc3092 JK |
2114 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
2115 | struct kvm_vcpu_events *events) | |
2116 | { | |
2117 | vcpu_load(vcpu); | |
2118 | ||
2119 | events->exception.injected = vcpu->arch.exception.pending; | |
2120 | events->exception.nr = vcpu->arch.exception.nr; | |
2121 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
2122 | events->exception.error_code = vcpu->arch.exception.error_code; | |
2123 | ||
2124 | events->interrupt.injected = vcpu->arch.interrupt.pending; | |
2125 | events->interrupt.nr = vcpu->arch.interrupt.nr; | |
2126 | events->interrupt.soft = vcpu->arch.interrupt.soft; | |
2127 | ||
2128 | events->nmi.injected = vcpu->arch.nmi_injected; | |
2129 | events->nmi.pending = vcpu->arch.nmi_pending; | |
2130 | events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); | |
2131 | ||
2132 | events->sipi_vector = vcpu->arch.sipi_vector; | |
2133 | ||
dab4b911 JK |
2134 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
2135 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR); | |
3cfc3092 JK |
2136 | |
2137 | vcpu_put(vcpu); | |
2138 | } | |
2139 | ||
2140 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, | |
2141 | struct kvm_vcpu_events *events) | |
2142 | { | |
dab4b911 JK |
2143 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
2144 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR)) | |
3cfc3092 JK |
2145 | return -EINVAL; |
2146 | ||
2147 | vcpu_load(vcpu); | |
2148 | ||
2149 | vcpu->arch.exception.pending = events->exception.injected; | |
2150 | vcpu->arch.exception.nr = events->exception.nr; | |
2151 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
2152 | vcpu->arch.exception.error_code = events->exception.error_code; | |
2153 | ||
2154 | vcpu->arch.interrupt.pending = events->interrupt.injected; | |
2155 | vcpu->arch.interrupt.nr = events->interrupt.nr; | |
2156 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
2157 | if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm)) | |
2158 | kvm_pic_clear_isr_ack(vcpu->kvm); | |
2159 | ||
2160 | vcpu->arch.nmi_injected = events->nmi.injected; | |
dab4b911 JK |
2161 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) |
2162 | vcpu->arch.nmi_pending = events->nmi.pending; | |
3cfc3092 JK |
2163 | kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); |
2164 | ||
dab4b911 JK |
2165 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR) |
2166 | vcpu->arch.sipi_vector = events->sipi_vector; | |
3cfc3092 JK |
2167 | |
2168 | vcpu_put(vcpu); | |
2169 | ||
2170 | return 0; | |
2171 | } | |
2172 | ||
313a3dc7 CO |
2173 | long kvm_arch_vcpu_ioctl(struct file *filp, |
2174 | unsigned int ioctl, unsigned long arg) | |
2175 | { | |
2176 | struct kvm_vcpu *vcpu = filp->private_data; | |
2177 | void __user *argp = (void __user *)arg; | |
2178 | int r; | |
b772ff36 | 2179 | struct kvm_lapic_state *lapic = NULL; |
313a3dc7 CO |
2180 | |
2181 | switch (ioctl) { | |
2182 | case KVM_GET_LAPIC: { | |
2204ae3c MT |
2183 | r = -EINVAL; |
2184 | if (!vcpu->arch.apic) | |
2185 | goto out; | |
b772ff36 | 2186 | lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); |
313a3dc7 | 2187 | |
b772ff36 DH |
2188 | r = -ENOMEM; |
2189 | if (!lapic) | |
2190 | goto out; | |
2191 | r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic); | |
313a3dc7 CO |
2192 | if (r) |
2193 | goto out; | |
2194 | r = -EFAULT; | |
b772ff36 | 2195 | if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
2196 | goto out; |
2197 | r = 0; | |
2198 | break; | |
2199 | } | |
2200 | case KVM_SET_LAPIC: { | |
2204ae3c MT |
2201 | r = -EINVAL; |
2202 | if (!vcpu->arch.apic) | |
2203 | goto out; | |
b772ff36 DH |
2204 | lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); |
2205 | r = -ENOMEM; | |
2206 | if (!lapic) | |
2207 | goto out; | |
313a3dc7 | 2208 | r = -EFAULT; |
b772ff36 | 2209 | if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state))) |
313a3dc7 | 2210 | goto out; |
b772ff36 | 2211 | r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic); |
313a3dc7 CO |
2212 | if (r) |
2213 | goto out; | |
2214 | r = 0; | |
2215 | break; | |
2216 | } | |
f77bc6a4 ZX |
2217 | case KVM_INTERRUPT: { |
2218 | struct kvm_interrupt irq; | |
2219 | ||
2220 | r = -EFAULT; | |
2221 | if (copy_from_user(&irq, argp, sizeof irq)) | |
2222 | goto out; | |
2223 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
2224 | if (r) | |
2225 | goto out; | |
2226 | r = 0; | |
2227 | break; | |
2228 | } | |
c4abb7c9 JK |
2229 | case KVM_NMI: { |
2230 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
2231 | if (r) | |
2232 | goto out; | |
2233 | r = 0; | |
2234 | break; | |
2235 | } | |
313a3dc7 CO |
2236 | case KVM_SET_CPUID: { |
2237 | struct kvm_cpuid __user *cpuid_arg = argp; | |
2238 | struct kvm_cpuid cpuid; | |
2239 | ||
2240 | r = -EFAULT; | |
2241 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2242 | goto out; | |
2243 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
2244 | if (r) | |
2245 | goto out; | |
2246 | break; | |
2247 | } | |
07716717 DK |
2248 | case KVM_SET_CPUID2: { |
2249 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
2250 | struct kvm_cpuid2 cpuid; | |
2251 | ||
2252 | r = -EFAULT; | |
2253 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2254 | goto out; | |
2255 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 2256 | cpuid_arg->entries); |
07716717 DK |
2257 | if (r) |
2258 | goto out; | |
2259 | break; | |
2260 | } | |
2261 | case KVM_GET_CPUID2: { | |
2262 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
2263 | struct kvm_cpuid2 cpuid; | |
2264 | ||
2265 | r = -EFAULT; | |
2266 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2267 | goto out; | |
2268 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 2269 | cpuid_arg->entries); |
07716717 DK |
2270 | if (r) |
2271 | goto out; | |
2272 | r = -EFAULT; | |
2273 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
2274 | goto out; | |
2275 | r = 0; | |
2276 | break; | |
2277 | } | |
313a3dc7 CO |
2278 | case KVM_GET_MSRS: |
2279 | r = msr_io(vcpu, argp, kvm_get_msr, 1); | |
2280 | break; | |
2281 | case KVM_SET_MSRS: | |
2282 | r = msr_io(vcpu, argp, do_set_msr, 0); | |
2283 | break; | |
b209749f AK |
2284 | case KVM_TPR_ACCESS_REPORTING: { |
2285 | struct kvm_tpr_access_ctl tac; | |
2286 | ||
2287 | r = -EFAULT; | |
2288 | if (copy_from_user(&tac, argp, sizeof tac)) | |
2289 | goto out; | |
2290 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
2291 | if (r) | |
2292 | goto out; | |
2293 | r = -EFAULT; | |
2294 | if (copy_to_user(argp, &tac, sizeof tac)) | |
2295 | goto out; | |
2296 | r = 0; | |
2297 | break; | |
2298 | }; | |
b93463aa AK |
2299 | case KVM_SET_VAPIC_ADDR: { |
2300 | struct kvm_vapic_addr va; | |
2301 | ||
2302 | r = -EINVAL; | |
2303 | if (!irqchip_in_kernel(vcpu->kvm)) | |
2304 | goto out; | |
2305 | r = -EFAULT; | |
2306 | if (copy_from_user(&va, argp, sizeof va)) | |
2307 | goto out; | |
2308 | r = 0; | |
2309 | kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); | |
2310 | break; | |
2311 | } | |
890ca9ae HY |
2312 | case KVM_X86_SETUP_MCE: { |
2313 | u64 mcg_cap; | |
2314 | ||
2315 | r = -EFAULT; | |
2316 | if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) | |
2317 | goto out; | |
2318 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
2319 | break; | |
2320 | } | |
2321 | case KVM_X86_SET_MCE: { | |
2322 | struct kvm_x86_mce mce; | |
2323 | ||
2324 | r = -EFAULT; | |
2325 | if (copy_from_user(&mce, argp, sizeof mce)) | |
2326 | goto out; | |
2327 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
2328 | break; | |
2329 | } | |
3cfc3092 JK |
2330 | case KVM_GET_VCPU_EVENTS: { |
2331 | struct kvm_vcpu_events events; | |
2332 | ||
2333 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
2334 | ||
2335 | r = -EFAULT; | |
2336 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
2337 | break; | |
2338 | r = 0; | |
2339 | break; | |
2340 | } | |
2341 | case KVM_SET_VCPU_EVENTS: { | |
2342 | struct kvm_vcpu_events events; | |
2343 | ||
2344 | r = -EFAULT; | |
2345 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
2346 | break; | |
2347 | ||
2348 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
2349 | break; | |
2350 | } | |
313a3dc7 CO |
2351 | default: |
2352 | r = -EINVAL; | |
2353 | } | |
2354 | out: | |
7a6ce84c | 2355 | kfree(lapic); |
313a3dc7 CO |
2356 | return r; |
2357 | } | |
2358 | ||
1fe779f8 CO |
2359 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
2360 | { | |
2361 | int ret; | |
2362 | ||
2363 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
2364 | return -1; | |
2365 | ret = kvm_x86_ops->set_tss_addr(kvm, addr); | |
2366 | return ret; | |
2367 | } | |
2368 | ||
b927a3ce SY |
2369 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
2370 | u64 ident_addr) | |
2371 | { | |
2372 | kvm->arch.ept_identity_map_addr = ident_addr; | |
2373 | return 0; | |
2374 | } | |
2375 | ||
1fe779f8 CO |
2376 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
2377 | u32 kvm_nr_mmu_pages) | |
2378 | { | |
2379 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
2380 | return -EINVAL; | |
2381 | ||
79fac95e | 2382 | mutex_lock(&kvm->slots_lock); |
7c8a83b7 | 2383 | spin_lock(&kvm->mmu_lock); |
1fe779f8 CO |
2384 | |
2385 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 2386 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 2387 | |
7c8a83b7 | 2388 | spin_unlock(&kvm->mmu_lock); |
79fac95e | 2389 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
2390 | return 0; |
2391 | } | |
2392 | ||
2393 | static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) | |
2394 | { | |
f05e70ac | 2395 | return kvm->arch.n_alloc_mmu_pages; |
1fe779f8 CO |
2396 | } |
2397 | ||
a983fb23 MT |
2398 | gfn_t unalias_gfn_instantiation(struct kvm *kvm, gfn_t gfn) |
2399 | { | |
2400 | int i; | |
2401 | struct kvm_mem_alias *alias; | |
2402 | struct kvm_mem_aliases *aliases; | |
2403 | ||
2404 | aliases = rcu_dereference(kvm->arch.aliases); | |
2405 | ||
2406 | for (i = 0; i < aliases->naliases; ++i) { | |
2407 | alias = &aliases->aliases[i]; | |
2408 | if (alias->flags & KVM_ALIAS_INVALID) | |
2409 | continue; | |
2410 | if (gfn >= alias->base_gfn | |
2411 | && gfn < alias->base_gfn + alias->npages) | |
2412 | return alias->target_gfn + gfn - alias->base_gfn; | |
2413 | } | |
2414 | return gfn; | |
2415 | } | |
2416 | ||
e9f85cde ZX |
2417 | gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn) |
2418 | { | |
2419 | int i; | |
2420 | struct kvm_mem_alias *alias; | |
a983fb23 MT |
2421 | struct kvm_mem_aliases *aliases; |
2422 | ||
2423 | aliases = rcu_dereference(kvm->arch.aliases); | |
e9f85cde | 2424 | |
fef9cce0 MT |
2425 | for (i = 0; i < aliases->naliases; ++i) { |
2426 | alias = &aliases->aliases[i]; | |
e9f85cde ZX |
2427 | if (gfn >= alias->base_gfn |
2428 | && gfn < alias->base_gfn + alias->npages) | |
2429 | return alias->target_gfn + gfn - alias->base_gfn; | |
2430 | } | |
2431 | return gfn; | |
2432 | } | |
2433 | ||
1fe779f8 CO |
2434 | /* |
2435 | * Set a new alias region. Aliases map a portion of physical memory into | |
2436 | * another portion. This is useful for memory windows, for example the PC | |
2437 | * VGA region. | |
2438 | */ | |
2439 | static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm, | |
2440 | struct kvm_memory_alias *alias) | |
2441 | { | |
2442 | int r, n; | |
2443 | struct kvm_mem_alias *p; | |
a983fb23 | 2444 | struct kvm_mem_aliases *aliases, *old_aliases; |
1fe779f8 CO |
2445 | |
2446 | r = -EINVAL; | |
2447 | /* General sanity checks */ | |
2448 | if (alias->memory_size & (PAGE_SIZE - 1)) | |
2449 | goto out; | |
2450 | if (alias->guest_phys_addr & (PAGE_SIZE - 1)) | |
2451 | goto out; | |
2452 | if (alias->slot >= KVM_ALIAS_SLOTS) | |
2453 | goto out; | |
2454 | if (alias->guest_phys_addr + alias->memory_size | |
2455 | < alias->guest_phys_addr) | |
2456 | goto out; | |
2457 | if (alias->target_phys_addr + alias->memory_size | |
2458 | < alias->target_phys_addr) | |
2459 | goto out; | |
2460 | ||
a983fb23 MT |
2461 | r = -ENOMEM; |
2462 | aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL); | |
2463 | if (!aliases) | |
2464 | goto out; | |
2465 | ||
79fac95e | 2466 | mutex_lock(&kvm->slots_lock); |
1fe779f8 | 2467 | |
a983fb23 MT |
2468 | /* invalidate any gfn reference in case of deletion/shrinking */ |
2469 | memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases)); | |
2470 | aliases->aliases[alias->slot].flags |= KVM_ALIAS_INVALID; | |
2471 | old_aliases = kvm->arch.aliases; | |
2472 | rcu_assign_pointer(kvm->arch.aliases, aliases); | |
2473 | synchronize_srcu_expedited(&kvm->srcu); | |
2474 | kvm_mmu_zap_all(kvm); | |
2475 | kfree(old_aliases); | |
2476 | ||
2477 | r = -ENOMEM; | |
2478 | aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL); | |
2479 | if (!aliases) | |
2480 | goto out_unlock; | |
2481 | ||
2482 | memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases)); | |
fef9cce0 MT |
2483 | |
2484 | p = &aliases->aliases[alias->slot]; | |
1fe779f8 CO |
2485 | p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT; |
2486 | p->npages = alias->memory_size >> PAGE_SHIFT; | |
2487 | p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT; | |
a983fb23 | 2488 | p->flags &= ~(KVM_ALIAS_INVALID); |
1fe779f8 CO |
2489 | |
2490 | for (n = KVM_ALIAS_SLOTS; n > 0; --n) | |
fef9cce0 | 2491 | if (aliases->aliases[n - 1].npages) |
1fe779f8 | 2492 | break; |
fef9cce0 | 2493 | aliases->naliases = n; |
1fe779f8 | 2494 | |
a983fb23 MT |
2495 | old_aliases = kvm->arch.aliases; |
2496 | rcu_assign_pointer(kvm->arch.aliases, aliases); | |
2497 | synchronize_srcu_expedited(&kvm->srcu); | |
2498 | kfree(old_aliases); | |
2499 | r = 0; | |
1fe779f8 | 2500 | |
a983fb23 | 2501 | out_unlock: |
79fac95e | 2502 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
2503 | out: |
2504 | return r; | |
2505 | } | |
2506 | ||
2507 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
2508 | { | |
2509 | int r; | |
2510 | ||
2511 | r = 0; | |
2512 | switch (chip->chip_id) { | |
2513 | case KVM_IRQCHIP_PIC_MASTER: | |
2514 | memcpy(&chip->chip.pic, | |
2515 | &pic_irqchip(kvm)->pics[0], | |
2516 | sizeof(struct kvm_pic_state)); | |
2517 | break; | |
2518 | case KVM_IRQCHIP_PIC_SLAVE: | |
2519 | memcpy(&chip->chip.pic, | |
2520 | &pic_irqchip(kvm)->pics[1], | |
2521 | sizeof(struct kvm_pic_state)); | |
2522 | break; | |
2523 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 2524 | r = kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
2525 | break; |
2526 | default: | |
2527 | r = -EINVAL; | |
2528 | break; | |
2529 | } | |
2530 | return r; | |
2531 | } | |
2532 | ||
2533 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
2534 | { | |
2535 | int r; | |
2536 | ||
2537 | r = 0; | |
2538 | switch (chip->chip_id) { | |
2539 | case KVM_IRQCHIP_PIC_MASTER: | |
894a9c55 | 2540 | spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
2541 | memcpy(&pic_irqchip(kvm)->pics[0], |
2542 | &chip->chip.pic, | |
2543 | sizeof(struct kvm_pic_state)); | |
894a9c55 | 2544 | spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
2545 | break; |
2546 | case KVM_IRQCHIP_PIC_SLAVE: | |
894a9c55 | 2547 | spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
2548 | memcpy(&pic_irqchip(kvm)->pics[1], |
2549 | &chip->chip.pic, | |
2550 | sizeof(struct kvm_pic_state)); | |
894a9c55 | 2551 | spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
2552 | break; |
2553 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 2554 | r = kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
2555 | break; |
2556 | default: | |
2557 | r = -EINVAL; | |
2558 | break; | |
2559 | } | |
2560 | kvm_pic_update_irq(pic_irqchip(kvm)); | |
2561 | return r; | |
2562 | } | |
2563 | ||
e0f63cb9 SY |
2564 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
2565 | { | |
2566 | int r = 0; | |
2567 | ||
894a9c55 | 2568 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 | 2569 | memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state)); |
894a9c55 | 2570 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 SY |
2571 | return r; |
2572 | } | |
2573 | ||
2574 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
2575 | { | |
2576 | int r = 0; | |
2577 | ||
894a9c55 | 2578 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 | 2579 | memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state)); |
e9f42757 BK |
2580 | kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0); |
2581 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
2582 | return r; | |
2583 | } | |
2584 | ||
2585 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
2586 | { | |
2587 | int r = 0; | |
2588 | ||
2589 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
2590 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
2591 | sizeof(ps->channels)); | |
2592 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
2593 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
2594 | return r; | |
2595 | } | |
2596 | ||
2597 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
2598 | { | |
2599 | int r = 0, start = 0; | |
2600 | u32 prev_legacy, cur_legacy; | |
2601 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
2602 | prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
2603 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
2604 | if (!prev_legacy && cur_legacy) | |
2605 | start = 1; | |
2606 | memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels, | |
2607 | sizeof(kvm->arch.vpit->pit_state.channels)); | |
2608 | kvm->arch.vpit->pit_state.flags = ps->flags; | |
2609 | kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start); | |
894a9c55 | 2610 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 SY |
2611 | return r; |
2612 | } | |
2613 | ||
52d939a0 MT |
2614 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
2615 | struct kvm_reinject_control *control) | |
2616 | { | |
2617 | if (!kvm->arch.vpit) | |
2618 | return -ENXIO; | |
894a9c55 | 2619 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
52d939a0 | 2620 | kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject; |
894a9c55 | 2621 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
52d939a0 MT |
2622 | return 0; |
2623 | } | |
2624 | ||
5bb064dc ZX |
2625 | /* |
2626 | * Get (and clear) the dirty memory log for a memory slot. | |
2627 | */ | |
2628 | int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, | |
2629 | struct kvm_dirty_log *log) | |
2630 | { | |
b050b015 | 2631 | int r, n, i; |
5bb064dc | 2632 | struct kvm_memory_slot *memslot; |
b050b015 MT |
2633 | unsigned long is_dirty = 0; |
2634 | unsigned long *dirty_bitmap = NULL; | |
5bb064dc | 2635 | |
79fac95e | 2636 | mutex_lock(&kvm->slots_lock); |
5bb064dc | 2637 | |
b050b015 MT |
2638 | r = -EINVAL; |
2639 | if (log->slot >= KVM_MEMORY_SLOTS) | |
2640 | goto out; | |
2641 | ||
2642 | memslot = &kvm->memslots->memslots[log->slot]; | |
2643 | r = -ENOENT; | |
2644 | if (!memslot->dirty_bitmap) | |
2645 | goto out; | |
2646 | ||
2647 | n = ALIGN(memslot->npages, BITS_PER_LONG) / 8; | |
2648 | ||
2649 | r = -ENOMEM; | |
2650 | dirty_bitmap = vmalloc(n); | |
2651 | if (!dirty_bitmap) | |
5bb064dc | 2652 | goto out; |
b050b015 MT |
2653 | memset(dirty_bitmap, 0, n); |
2654 | ||
2655 | for (i = 0; !is_dirty && i < n/sizeof(long); i++) | |
2656 | is_dirty = memslot->dirty_bitmap[i]; | |
5bb064dc ZX |
2657 | |
2658 | /* If nothing is dirty, don't bother messing with page tables. */ | |
2659 | if (is_dirty) { | |
b050b015 MT |
2660 | struct kvm_memslots *slots, *old_slots; |
2661 | ||
7c8a83b7 | 2662 | spin_lock(&kvm->mmu_lock); |
5bb064dc | 2663 | kvm_mmu_slot_remove_write_access(kvm, log->slot); |
7c8a83b7 | 2664 | spin_unlock(&kvm->mmu_lock); |
b050b015 MT |
2665 | |
2666 | slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL); | |
2667 | if (!slots) | |
2668 | goto out_free; | |
2669 | ||
2670 | memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots)); | |
2671 | slots->memslots[log->slot].dirty_bitmap = dirty_bitmap; | |
2672 | ||
2673 | old_slots = kvm->memslots; | |
2674 | rcu_assign_pointer(kvm->memslots, slots); | |
2675 | synchronize_srcu_expedited(&kvm->srcu); | |
2676 | dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap; | |
2677 | kfree(old_slots); | |
5bb064dc | 2678 | } |
b050b015 | 2679 | |
5bb064dc | 2680 | r = 0; |
b050b015 MT |
2681 | if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) |
2682 | r = -EFAULT; | |
2683 | out_free: | |
2684 | vfree(dirty_bitmap); | |
5bb064dc | 2685 | out: |
79fac95e | 2686 | mutex_unlock(&kvm->slots_lock); |
5bb064dc ZX |
2687 | return r; |
2688 | } | |
2689 | ||
1fe779f8 CO |
2690 | long kvm_arch_vm_ioctl(struct file *filp, |
2691 | unsigned int ioctl, unsigned long arg) | |
2692 | { | |
2693 | struct kvm *kvm = filp->private_data; | |
2694 | void __user *argp = (void __user *)arg; | |
367e1319 | 2695 | int r = -ENOTTY; |
f0d66275 DH |
2696 | /* |
2697 | * This union makes it completely explicit to gcc-3.x | |
2698 | * that these two variables' stack usage should be | |
2699 | * combined, not added together. | |
2700 | */ | |
2701 | union { | |
2702 | struct kvm_pit_state ps; | |
e9f42757 | 2703 | struct kvm_pit_state2 ps2; |
f0d66275 | 2704 | struct kvm_memory_alias alias; |
c5ff41ce | 2705 | struct kvm_pit_config pit_config; |
f0d66275 | 2706 | } u; |
1fe779f8 CO |
2707 | |
2708 | switch (ioctl) { | |
2709 | case KVM_SET_TSS_ADDR: | |
2710 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
2711 | if (r < 0) | |
2712 | goto out; | |
2713 | break; | |
b927a3ce SY |
2714 | case KVM_SET_IDENTITY_MAP_ADDR: { |
2715 | u64 ident_addr; | |
2716 | ||
2717 | r = -EFAULT; | |
2718 | if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) | |
2719 | goto out; | |
2720 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); | |
2721 | if (r < 0) | |
2722 | goto out; | |
2723 | break; | |
2724 | } | |
1fe779f8 CO |
2725 | case KVM_SET_MEMORY_REGION: { |
2726 | struct kvm_memory_region kvm_mem; | |
2727 | struct kvm_userspace_memory_region kvm_userspace_mem; | |
2728 | ||
2729 | r = -EFAULT; | |
2730 | if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem)) | |
2731 | goto out; | |
2732 | kvm_userspace_mem.slot = kvm_mem.slot; | |
2733 | kvm_userspace_mem.flags = kvm_mem.flags; | |
2734 | kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr; | |
2735 | kvm_userspace_mem.memory_size = kvm_mem.memory_size; | |
2736 | r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0); | |
2737 | if (r) | |
2738 | goto out; | |
2739 | break; | |
2740 | } | |
2741 | case KVM_SET_NR_MMU_PAGES: | |
2742 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
2743 | if (r) | |
2744 | goto out; | |
2745 | break; | |
2746 | case KVM_GET_NR_MMU_PAGES: | |
2747 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
2748 | break; | |
f0d66275 | 2749 | case KVM_SET_MEMORY_ALIAS: |
1fe779f8 | 2750 | r = -EFAULT; |
f0d66275 | 2751 | if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias))) |
1fe779f8 | 2752 | goto out; |
f0d66275 | 2753 | r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias); |
1fe779f8 CO |
2754 | if (r) |
2755 | goto out; | |
2756 | break; | |
3ddea128 MT |
2757 | case KVM_CREATE_IRQCHIP: { |
2758 | struct kvm_pic *vpic; | |
2759 | ||
2760 | mutex_lock(&kvm->lock); | |
2761 | r = -EEXIST; | |
2762 | if (kvm->arch.vpic) | |
2763 | goto create_irqchip_unlock; | |
1fe779f8 | 2764 | r = -ENOMEM; |
3ddea128 MT |
2765 | vpic = kvm_create_pic(kvm); |
2766 | if (vpic) { | |
1fe779f8 CO |
2767 | r = kvm_ioapic_init(kvm); |
2768 | if (r) { | |
3ddea128 MT |
2769 | kfree(vpic); |
2770 | goto create_irqchip_unlock; | |
1fe779f8 CO |
2771 | } |
2772 | } else | |
3ddea128 MT |
2773 | goto create_irqchip_unlock; |
2774 | smp_wmb(); | |
2775 | kvm->arch.vpic = vpic; | |
2776 | smp_wmb(); | |
399ec807 AK |
2777 | r = kvm_setup_default_irq_routing(kvm); |
2778 | if (r) { | |
3ddea128 | 2779 | mutex_lock(&kvm->irq_lock); |
399ec807 AK |
2780 | kfree(kvm->arch.vpic); |
2781 | kfree(kvm->arch.vioapic); | |
3ddea128 MT |
2782 | kvm->arch.vpic = NULL; |
2783 | kvm->arch.vioapic = NULL; | |
2784 | mutex_unlock(&kvm->irq_lock); | |
399ec807 | 2785 | } |
3ddea128 MT |
2786 | create_irqchip_unlock: |
2787 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 2788 | break; |
3ddea128 | 2789 | } |
7837699f | 2790 | case KVM_CREATE_PIT: |
c5ff41ce JK |
2791 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
2792 | goto create_pit; | |
2793 | case KVM_CREATE_PIT2: | |
2794 | r = -EFAULT; | |
2795 | if (copy_from_user(&u.pit_config, argp, | |
2796 | sizeof(struct kvm_pit_config))) | |
2797 | goto out; | |
2798 | create_pit: | |
79fac95e | 2799 | mutex_lock(&kvm->slots_lock); |
269e05e4 AK |
2800 | r = -EEXIST; |
2801 | if (kvm->arch.vpit) | |
2802 | goto create_pit_unlock; | |
7837699f | 2803 | r = -ENOMEM; |
c5ff41ce | 2804 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
2805 | if (kvm->arch.vpit) |
2806 | r = 0; | |
269e05e4 | 2807 | create_pit_unlock: |
79fac95e | 2808 | mutex_unlock(&kvm->slots_lock); |
7837699f | 2809 | break; |
4925663a | 2810 | case KVM_IRQ_LINE_STATUS: |
1fe779f8 CO |
2811 | case KVM_IRQ_LINE: { |
2812 | struct kvm_irq_level irq_event; | |
2813 | ||
2814 | r = -EFAULT; | |
2815 | if (copy_from_user(&irq_event, argp, sizeof irq_event)) | |
2816 | goto out; | |
2817 | if (irqchip_in_kernel(kvm)) { | |
4925663a | 2818 | __s32 status; |
4925663a GN |
2819 | status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, |
2820 | irq_event.irq, irq_event.level); | |
4925663a GN |
2821 | if (ioctl == KVM_IRQ_LINE_STATUS) { |
2822 | irq_event.status = status; | |
2823 | if (copy_to_user(argp, &irq_event, | |
2824 | sizeof irq_event)) | |
2825 | goto out; | |
2826 | } | |
1fe779f8 CO |
2827 | r = 0; |
2828 | } | |
2829 | break; | |
2830 | } | |
2831 | case KVM_GET_IRQCHIP: { | |
2832 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
f0d66275 | 2833 | struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL); |
1fe779f8 | 2834 | |
f0d66275 DH |
2835 | r = -ENOMEM; |
2836 | if (!chip) | |
1fe779f8 | 2837 | goto out; |
f0d66275 DH |
2838 | r = -EFAULT; |
2839 | if (copy_from_user(chip, argp, sizeof *chip)) | |
2840 | goto get_irqchip_out; | |
1fe779f8 CO |
2841 | r = -ENXIO; |
2842 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
2843 | goto get_irqchip_out; |
2844 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 2845 | if (r) |
f0d66275 | 2846 | goto get_irqchip_out; |
1fe779f8 | 2847 | r = -EFAULT; |
f0d66275 DH |
2848 | if (copy_to_user(argp, chip, sizeof *chip)) |
2849 | goto get_irqchip_out; | |
1fe779f8 | 2850 | r = 0; |
f0d66275 DH |
2851 | get_irqchip_out: |
2852 | kfree(chip); | |
2853 | if (r) | |
2854 | goto out; | |
1fe779f8 CO |
2855 | break; |
2856 | } | |
2857 | case KVM_SET_IRQCHIP: { | |
2858 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
f0d66275 | 2859 | struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL); |
1fe779f8 | 2860 | |
f0d66275 DH |
2861 | r = -ENOMEM; |
2862 | if (!chip) | |
1fe779f8 | 2863 | goto out; |
f0d66275 DH |
2864 | r = -EFAULT; |
2865 | if (copy_from_user(chip, argp, sizeof *chip)) | |
2866 | goto set_irqchip_out; | |
1fe779f8 CO |
2867 | r = -ENXIO; |
2868 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
2869 | goto set_irqchip_out; |
2870 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
1fe779f8 | 2871 | if (r) |
f0d66275 | 2872 | goto set_irqchip_out; |
1fe779f8 | 2873 | r = 0; |
f0d66275 DH |
2874 | set_irqchip_out: |
2875 | kfree(chip); | |
2876 | if (r) | |
2877 | goto out; | |
1fe779f8 CO |
2878 | break; |
2879 | } | |
e0f63cb9 | 2880 | case KVM_GET_PIT: { |
e0f63cb9 | 2881 | r = -EFAULT; |
f0d66275 | 2882 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
2883 | goto out; |
2884 | r = -ENXIO; | |
2885 | if (!kvm->arch.vpit) | |
2886 | goto out; | |
f0d66275 | 2887 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
2888 | if (r) |
2889 | goto out; | |
2890 | r = -EFAULT; | |
f0d66275 | 2891 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
2892 | goto out; |
2893 | r = 0; | |
2894 | break; | |
2895 | } | |
2896 | case KVM_SET_PIT: { | |
e0f63cb9 | 2897 | r = -EFAULT; |
f0d66275 | 2898 | if (copy_from_user(&u.ps, argp, sizeof u.ps)) |
e0f63cb9 SY |
2899 | goto out; |
2900 | r = -ENXIO; | |
2901 | if (!kvm->arch.vpit) | |
2902 | goto out; | |
f0d66275 | 2903 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
e0f63cb9 SY |
2904 | if (r) |
2905 | goto out; | |
2906 | r = 0; | |
2907 | break; | |
2908 | } | |
e9f42757 BK |
2909 | case KVM_GET_PIT2: { |
2910 | r = -ENXIO; | |
2911 | if (!kvm->arch.vpit) | |
2912 | goto out; | |
2913 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
2914 | if (r) | |
2915 | goto out; | |
2916 | r = -EFAULT; | |
2917 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
2918 | goto out; | |
2919 | r = 0; | |
2920 | break; | |
2921 | } | |
2922 | case KVM_SET_PIT2: { | |
2923 | r = -EFAULT; | |
2924 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
2925 | goto out; | |
2926 | r = -ENXIO; | |
2927 | if (!kvm->arch.vpit) | |
2928 | goto out; | |
2929 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); | |
2930 | if (r) | |
2931 | goto out; | |
2932 | r = 0; | |
2933 | break; | |
2934 | } | |
52d939a0 MT |
2935 | case KVM_REINJECT_CONTROL: { |
2936 | struct kvm_reinject_control control; | |
2937 | r = -EFAULT; | |
2938 | if (copy_from_user(&control, argp, sizeof(control))) | |
2939 | goto out; | |
2940 | r = kvm_vm_ioctl_reinject(kvm, &control); | |
2941 | if (r) | |
2942 | goto out; | |
2943 | r = 0; | |
2944 | break; | |
2945 | } | |
ffde22ac ES |
2946 | case KVM_XEN_HVM_CONFIG: { |
2947 | r = -EFAULT; | |
2948 | if (copy_from_user(&kvm->arch.xen_hvm_config, argp, | |
2949 | sizeof(struct kvm_xen_hvm_config))) | |
2950 | goto out; | |
2951 | r = -EINVAL; | |
2952 | if (kvm->arch.xen_hvm_config.flags) | |
2953 | goto out; | |
2954 | r = 0; | |
2955 | break; | |
2956 | } | |
afbcf7ab GC |
2957 | case KVM_SET_CLOCK: { |
2958 | struct timespec now; | |
2959 | struct kvm_clock_data user_ns; | |
2960 | u64 now_ns; | |
2961 | s64 delta; | |
2962 | ||
2963 | r = -EFAULT; | |
2964 | if (copy_from_user(&user_ns, argp, sizeof(user_ns))) | |
2965 | goto out; | |
2966 | ||
2967 | r = -EINVAL; | |
2968 | if (user_ns.flags) | |
2969 | goto out; | |
2970 | ||
2971 | r = 0; | |
2972 | ktime_get_ts(&now); | |
2973 | now_ns = timespec_to_ns(&now); | |
2974 | delta = user_ns.clock - now_ns; | |
2975 | kvm->arch.kvmclock_offset = delta; | |
2976 | break; | |
2977 | } | |
2978 | case KVM_GET_CLOCK: { | |
2979 | struct timespec now; | |
2980 | struct kvm_clock_data user_ns; | |
2981 | u64 now_ns; | |
2982 | ||
2983 | ktime_get_ts(&now); | |
2984 | now_ns = timespec_to_ns(&now); | |
2985 | user_ns.clock = kvm->arch.kvmclock_offset + now_ns; | |
2986 | user_ns.flags = 0; | |
2987 | ||
2988 | r = -EFAULT; | |
2989 | if (copy_to_user(argp, &user_ns, sizeof(user_ns))) | |
2990 | goto out; | |
2991 | r = 0; | |
2992 | break; | |
2993 | } | |
2994 | ||
1fe779f8 CO |
2995 | default: |
2996 | ; | |
2997 | } | |
2998 | out: | |
2999 | return r; | |
3000 | } | |
3001 | ||
a16b043c | 3002 | static void kvm_init_msr_list(void) |
043405e1 CO |
3003 | { |
3004 | u32 dummy[2]; | |
3005 | unsigned i, j; | |
3006 | ||
e3267cbb GC |
3007 | /* skip the first msrs in the list. KVM-specific */ |
3008 | for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) { | |
043405e1 CO |
3009 | if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) |
3010 | continue; | |
3011 | if (j < i) | |
3012 | msrs_to_save[j] = msrs_to_save[i]; | |
3013 | j++; | |
3014 | } | |
3015 | num_msrs_to_save = j; | |
3016 | } | |
3017 | ||
bda9020e MT |
3018 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
3019 | const void *v) | |
bbd9b64e | 3020 | { |
bda9020e MT |
3021 | if (vcpu->arch.apic && |
3022 | !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v)) | |
3023 | return 0; | |
bbd9b64e | 3024 | |
e93f8a0f | 3025 | return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v); |
bbd9b64e CO |
3026 | } |
3027 | ||
bda9020e | 3028 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 3029 | { |
bda9020e MT |
3030 | if (vcpu->arch.apic && |
3031 | !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v)) | |
3032 | return 0; | |
bbd9b64e | 3033 | |
e93f8a0f | 3034 | return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v); |
bbd9b64e CO |
3035 | } |
3036 | ||
cded19f3 HE |
3037 | static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes, |
3038 | struct kvm_vcpu *vcpu) | |
bbd9b64e CO |
3039 | { |
3040 | void *data = val; | |
10589a46 | 3041 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
3042 | |
3043 | while (bytes) { | |
ad312c7c | 3044 | gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr); |
bbd9b64e | 3045 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 3046 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
3047 | int ret; |
3048 | ||
10589a46 MT |
3049 | if (gpa == UNMAPPED_GVA) { |
3050 | r = X86EMUL_PROPAGATE_FAULT; | |
3051 | goto out; | |
3052 | } | |
77c2002e | 3053 | ret = kvm_read_guest(vcpu->kvm, gpa, data, toread); |
10589a46 MT |
3054 | if (ret < 0) { |
3055 | r = X86EMUL_UNHANDLEABLE; | |
3056 | goto out; | |
3057 | } | |
bbd9b64e | 3058 | |
77c2002e IE |
3059 | bytes -= toread; |
3060 | data += toread; | |
3061 | addr += toread; | |
bbd9b64e | 3062 | } |
10589a46 | 3063 | out: |
10589a46 | 3064 | return r; |
bbd9b64e | 3065 | } |
77c2002e | 3066 | |
cded19f3 HE |
3067 | static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes, |
3068 | struct kvm_vcpu *vcpu) | |
77c2002e IE |
3069 | { |
3070 | void *data = val; | |
3071 | int r = X86EMUL_CONTINUE; | |
3072 | ||
3073 | while (bytes) { | |
3074 | gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr); | |
3075 | unsigned offset = addr & (PAGE_SIZE-1); | |
3076 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
3077 | int ret; | |
3078 | ||
3079 | if (gpa == UNMAPPED_GVA) { | |
3080 | r = X86EMUL_PROPAGATE_FAULT; | |
3081 | goto out; | |
3082 | } | |
3083 | ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite); | |
3084 | if (ret < 0) { | |
3085 | r = X86EMUL_UNHANDLEABLE; | |
3086 | goto out; | |
3087 | } | |
3088 | ||
3089 | bytes -= towrite; | |
3090 | data += towrite; | |
3091 | addr += towrite; | |
3092 | } | |
3093 | out: | |
3094 | return r; | |
3095 | } | |
3096 | ||
bbd9b64e | 3097 | |
bbd9b64e CO |
3098 | static int emulator_read_emulated(unsigned long addr, |
3099 | void *val, | |
3100 | unsigned int bytes, | |
3101 | struct kvm_vcpu *vcpu) | |
3102 | { | |
bbd9b64e CO |
3103 | gpa_t gpa; |
3104 | ||
3105 | if (vcpu->mmio_read_completed) { | |
3106 | memcpy(val, vcpu->mmio_data, bytes); | |
aec51dc4 AK |
3107 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
3108 | vcpu->mmio_phys_addr, *(u64 *)val); | |
bbd9b64e CO |
3109 | vcpu->mmio_read_completed = 0; |
3110 | return X86EMUL_CONTINUE; | |
3111 | } | |
3112 | ||
ad312c7c | 3113 | gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr); |
bbd9b64e CO |
3114 | |
3115 | /* For APIC access vmexit */ | |
3116 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
3117 | goto mmio; | |
3118 | ||
77c2002e IE |
3119 | if (kvm_read_guest_virt(addr, val, bytes, vcpu) |
3120 | == X86EMUL_CONTINUE) | |
bbd9b64e CO |
3121 | return X86EMUL_CONTINUE; |
3122 | if (gpa == UNMAPPED_GVA) | |
3123 | return X86EMUL_PROPAGATE_FAULT; | |
3124 | ||
3125 | mmio: | |
3126 | /* | |
3127 | * Is this MMIO handled locally? | |
3128 | */ | |
aec51dc4 AK |
3129 | if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) { |
3130 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val); | |
bbd9b64e CO |
3131 | return X86EMUL_CONTINUE; |
3132 | } | |
aec51dc4 AK |
3133 | |
3134 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); | |
bbd9b64e CO |
3135 | |
3136 | vcpu->mmio_needed = 1; | |
3137 | vcpu->mmio_phys_addr = gpa; | |
3138 | vcpu->mmio_size = bytes; | |
3139 | vcpu->mmio_is_write = 0; | |
3140 | ||
3141 | return X86EMUL_UNHANDLEABLE; | |
3142 | } | |
3143 | ||
3200f405 | 3144 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
9f811285 | 3145 | const void *val, int bytes) |
bbd9b64e CO |
3146 | { |
3147 | int ret; | |
3148 | ||
3149 | ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes); | |
9f811285 | 3150 | if (ret < 0) |
bbd9b64e | 3151 | return 0; |
ad218f85 | 3152 | kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1); |
bbd9b64e CO |
3153 | return 1; |
3154 | } | |
3155 | ||
3156 | static int emulator_write_emulated_onepage(unsigned long addr, | |
3157 | const void *val, | |
3158 | unsigned int bytes, | |
3159 | struct kvm_vcpu *vcpu) | |
3160 | { | |
10589a46 MT |
3161 | gpa_t gpa; |
3162 | ||
10589a46 | 3163 | gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr); |
bbd9b64e CO |
3164 | |
3165 | if (gpa == UNMAPPED_GVA) { | |
c3c91fee | 3166 | kvm_inject_page_fault(vcpu, addr, 2); |
bbd9b64e CO |
3167 | return X86EMUL_PROPAGATE_FAULT; |
3168 | } | |
3169 | ||
3170 | /* For APIC access vmexit */ | |
3171 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
3172 | goto mmio; | |
3173 | ||
3174 | if (emulator_write_phys(vcpu, gpa, val, bytes)) | |
3175 | return X86EMUL_CONTINUE; | |
3176 | ||
3177 | mmio: | |
aec51dc4 | 3178 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); |
bbd9b64e CO |
3179 | /* |
3180 | * Is this MMIO handled locally? | |
3181 | */ | |
bda9020e | 3182 | if (!vcpu_mmio_write(vcpu, gpa, bytes, val)) |
bbd9b64e | 3183 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
3184 | |
3185 | vcpu->mmio_needed = 1; | |
3186 | vcpu->mmio_phys_addr = gpa; | |
3187 | vcpu->mmio_size = bytes; | |
3188 | vcpu->mmio_is_write = 1; | |
3189 | memcpy(vcpu->mmio_data, val, bytes); | |
3190 | ||
3191 | return X86EMUL_CONTINUE; | |
3192 | } | |
3193 | ||
3194 | int emulator_write_emulated(unsigned long addr, | |
3195 | const void *val, | |
3196 | unsigned int bytes, | |
3197 | struct kvm_vcpu *vcpu) | |
3198 | { | |
3199 | /* Crossing a page boundary? */ | |
3200 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
3201 | int rc, now; | |
3202 | ||
3203 | now = -addr & ~PAGE_MASK; | |
3204 | rc = emulator_write_emulated_onepage(addr, val, now, vcpu); | |
3205 | if (rc != X86EMUL_CONTINUE) | |
3206 | return rc; | |
3207 | addr += now; | |
3208 | val += now; | |
3209 | bytes -= now; | |
3210 | } | |
3211 | return emulator_write_emulated_onepage(addr, val, bytes, vcpu); | |
3212 | } | |
3213 | EXPORT_SYMBOL_GPL(emulator_write_emulated); | |
3214 | ||
3215 | static int emulator_cmpxchg_emulated(unsigned long addr, | |
3216 | const void *old, | |
3217 | const void *new, | |
3218 | unsigned int bytes, | |
3219 | struct kvm_vcpu *vcpu) | |
3220 | { | |
9f51e24e | 3221 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); |
2bacc55c MT |
3222 | #ifndef CONFIG_X86_64 |
3223 | /* guests cmpxchg8b have to be emulated atomically */ | |
3224 | if (bytes == 8) { | |
10589a46 | 3225 | gpa_t gpa; |
2bacc55c | 3226 | struct page *page; |
c0b49b0d | 3227 | char *kaddr; |
2bacc55c MT |
3228 | u64 val; |
3229 | ||
10589a46 MT |
3230 | gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr); |
3231 | ||
2bacc55c MT |
3232 | if (gpa == UNMAPPED_GVA || |
3233 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
3234 | goto emul_write; | |
3235 | ||
3236 | if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) | |
3237 | goto emul_write; | |
3238 | ||
3239 | val = *(u64 *)new; | |
72dc67a6 | 3240 | |
2bacc55c | 3241 | page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
72dc67a6 | 3242 | |
c0b49b0d AM |
3243 | kaddr = kmap_atomic(page, KM_USER0); |
3244 | set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val); | |
3245 | kunmap_atomic(kaddr, KM_USER0); | |
2bacc55c MT |
3246 | kvm_release_page_dirty(page); |
3247 | } | |
3200f405 | 3248 | emul_write: |
2bacc55c MT |
3249 | #endif |
3250 | ||
bbd9b64e CO |
3251 | return emulator_write_emulated(addr, new, bytes, vcpu); |
3252 | } | |
3253 | ||
3254 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
3255 | { | |
3256 | return kvm_x86_ops->get_segment_base(vcpu, seg); | |
3257 | } | |
3258 | ||
3259 | int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address) | |
3260 | { | |
a7052897 | 3261 | kvm_mmu_invlpg(vcpu, address); |
bbd9b64e CO |
3262 | return X86EMUL_CONTINUE; |
3263 | } | |
3264 | ||
3265 | int emulate_clts(struct kvm_vcpu *vcpu) | |
3266 | { | |
4d4ec087 | 3267 | kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); |
bbd9b64e CO |
3268 | return X86EMUL_CONTINUE; |
3269 | } | |
3270 | ||
3271 | int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest) | |
3272 | { | |
c76de350 | 3273 | return kvm_x86_ops->get_dr(ctxt->vcpu, dr, dest); |
bbd9b64e CO |
3274 | } |
3275 | ||
3276 | int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value) | |
3277 | { | |
3278 | unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U; | |
bbd9b64e | 3279 | |
c76de350 | 3280 | return kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask); |
bbd9b64e CO |
3281 | } |
3282 | ||
3283 | void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context) | |
3284 | { | |
bbd9b64e | 3285 | u8 opcodes[4]; |
5fdbf976 | 3286 | unsigned long rip = kvm_rip_read(vcpu); |
bbd9b64e CO |
3287 | unsigned long rip_linear; |
3288 | ||
f76c710d | 3289 | if (!printk_ratelimit()) |
bbd9b64e CO |
3290 | return; |
3291 | ||
25be4608 GC |
3292 | rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS); |
3293 | ||
77c2002e | 3294 | kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu); |
bbd9b64e CO |
3295 | |
3296 | printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n", | |
3297 | context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]); | |
bbd9b64e CO |
3298 | } |
3299 | EXPORT_SYMBOL_GPL(kvm_report_emulation_failure); | |
3300 | ||
14af3f3c | 3301 | static struct x86_emulate_ops emulate_ops = { |
77c2002e | 3302 | .read_std = kvm_read_guest_virt, |
bbd9b64e CO |
3303 | .read_emulated = emulator_read_emulated, |
3304 | .write_emulated = emulator_write_emulated, | |
3305 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
3306 | }; | |
3307 | ||
5fdbf976 MT |
3308 | static void cache_all_regs(struct kvm_vcpu *vcpu) |
3309 | { | |
3310 | kvm_register_read(vcpu, VCPU_REGS_RAX); | |
3311 | kvm_register_read(vcpu, VCPU_REGS_RSP); | |
3312 | kvm_register_read(vcpu, VCPU_REGS_RIP); | |
3313 | vcpu->arch.regs_dirty = ~0; | |
3314 | } | |
3315 | ||
bbd9b64e | 3316 | int emulate_instruction(struct kvm_vcpu *vcpu, |
bbd9b64e CO |
3317 | unsigned long cr2, |
3318 | u16 error_code, | |
571008da | 3319 | int emulation_type) |
bbd9b64e | 3320 | { |
310b5d30 | 3321 | int r, shadow_mask; |
571008da | 3322 | struct decode_cache *c; |
851ba692 | 3323 | struct kvm_run *run = vcpu->run; |
bbd9b64e | 3324 | |
26eef70c | 3325 | kvm_clear_exception_queue(vcpu); |
ad312c7c | 3326 | vcpu->arch.mmio_fault_cr2 = cr2; |
5fdbf976 | 3327 | /* |
56e82318 | 3328 | * TODO: fix emulate.c to use guest_read/write_register |
5fdbf976 MT |
3329 | * instead of direct ->regs accesses, can save hundred cycles |
3330 | * on Intel for instructions that don't read/change RSP, for | |
3331 | * for example. | |
3332 | */ | |
3333 | cache_all_regs(vcpu); | |
bbd9b64e CO |
3334 | |
3335 | vcpu->mmio_is_write = 0; | |
ad312c7c | 3336 | vcpu->arch.pio.string = 0; |
bbd9b64e | 3337 | |
571008da | 3338 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
bbd9b64e CO |
3339 | int cs_db, cs_l; |
3340 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
3341 | ||
ad312c7c | 3342 | vcpu->arch.emulate_ctxt.vcpu = vcpu; |
91586a3b | 3343 | vcpu->arch.emulate_ctxt.eflags = kvm_get_rflags(vcpu); |
ad312c7c ZX |
3344 | vcpu->arch.emulate_ctxt.mode = |
3345 | (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM) | |
bbd9b64e CO |
3346 | ? X86EMUL_MODE_REAL : cs_l |
3347 | ? X86EMUL_MODE_PROT64 : cs_db | |
3348 | ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16; | |
3349 | ||
ad312c7c | 3350 | r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops); |
571008da | 3351 | |
0cb5762e AP |
3352 | /* Only allow emulation of specific instructions on #UD |
3353 | * (namely VMMCALL, sysenter, sysexit, syscall)*/ | |
571008da | 3354 | c = &vcpu->arch.emulate_ctxt.decode; |
0cb5762e AP |
3355 | if (emulation_type & EMULTYPE_TRAP_UD) { |
3356 | if (!c->twobyte) | |
3357 | return EMULATE_FAIL; | |
3358 | switch (c->b) { | |
3359 | case 0x01: /* VMMCALL */ | |
3360 | if (c->modrm_mod != 3 || c->modrm_rm != 1) | |
3361 | return EMULATE_FAIL; | |
3362 | break; | |
3363 | case 0x34: /* sysenter */ | |
3364 | case 0x35: /* sysexit */ | |
3365 | if (c->modrm_mod != 0 || c->modrm_rm != 0) | |
3366 | return EMULATE_FAIL; | |
3367 | break; | |
3368 | case 0x05: /* syscall */ | |
3369 | if (c->modrm_mod != 0 || c->modrm_rm != 0) | |
3370 | return EMULATE_FAIL; | |
3371 | break; | |
3372 | default: | |
3373 | return EMULATE_FAIL; | |
3374 | } | |
3375 | ||
3376 | if (!(c->modrm_reg == 0 || c->modrm_reg == 3)) | |
3377 | return EMULATE_FAIL; | |
3378 | } | |
571008da | 3379 | |
f2b5756b | 3380 | ++vcpu->stat.insn_emulation; |
bbd9b64e | 3381 | if (r) { |
f2b5756b | 3382 | ++vcpu->stat.insn_emulation_fail; |
bbd9b64e CO |
3383 | if (kvm_mmu_unprotect_page_virt(vcpu, cr2)) |
3384 | return EMULATE_DONE; | |
3385 | return EMULATE_FAIL; | |
3386 | } | |
3387 | } | |
3388 | ||
ba8afb6b GN |
3389 | if (emulation_type & EMULTYPE_SKIP) { |
3390 | kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip); | |
3391 | return EMULATE_DONE; | |
3392 | } | |
3393 | ||
ad312c7c | 3394 | r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops); |
310b5d30 GC |
3395 | shadow_mask = vcpu->arch.emulate_ctxt.interruptibility; |
3396 | ||
3397 | if (r == 0) | |
3398 | kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask); | |
bbd9b64e | 3399 | |
ad312c7c | 3400 | if (vcpu->arch.pio.string) |
bbd9b64e CO |
3401 | return EMULATE_DO_MMIO; |
3402 | ||
3403 | if ((r || vcpu->mmio_is_write) && run) { | |
3404 | run->exit_reason = KVM_EXIT_MMIO; | |
3405 | run->mmio.phys_addr = vcpu->mmio_phys_addr; | |
3406 | memcpy(run->mmio.data, vcpu->mmio_data, 8); | |
3407 | run->mmio.len = vcpu->mmio_size; | |
3408 | run->mmio.is_write = vcpu->mmio_is_write; | |
3409 | } | |
3410 | ||
3411 | if (r) { | |
3412 | if (kvm_mmu_unprotect_page_virt(vcpu, cr2)) | |
3413 | return EMULATE_DONE; | |
3414 | if (!vcpu->mmio_needed) { | |
3415 | kvm_report_emulation_failure(vcpu, "mmio"); | |
3416 | return EMULATE_FAIL; | |
3417 | } | |
3418 | return EMULATE_DO_MMIO; | |
3419 | } | |
3420 | ||
91586a3b | 3421 | kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags); |
bbd9b64e CO |
3422 | |
3423 | if (vcpu->mmio_is_write) { | |
3424 | vcpu->mmio_needed = 0; | |
3425 | return EMULATE_DO_MMIO; | |
3426 | } | |
3427 | ||
3428 | return EMULATE_DONE; | |
3429 | } | |
3430 | EXPORT_SYMBOL_GPL(emulate_instruction); | |
3431 | ||
de7d789a CO |
3432 | static int pio_copy_data(struct kvm_vcpu *vcpu) |
3433 | { | |
ad312c7c | 3434 | void *p = vcpu->arch.pio_data; |
0f346074 | 3435 | gva_t q = vcpu->arch.pio.guest_gva; |
de7d789a | 3436 | unsigned bytes; |
0f346074 | 3437 | int ret; |
de7d789a | 3438 | |
ad312c7c ZX |
3439 | bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count; |
3440 | if (vcpu->arch.pio.in) | |
0f346074 | 3441 | ret = kvm_write_guest_virt(q, p, bytes, vcpu); |
de7d789a | 3442 | else |
0f346074 IE |
3443 | ret = kvm_read_guest_virt(q, p, bytes, vcpu); |
3444 | return ret; | |
de7d789a CO |
3445 | } |
3446 | ||
3447 | int complete_pio(struct kvm_vcpu *vcpu) | |
3448 | { | |
ad312c7c | 3449 | struct kvm_pio_request *io = &vcpu->arch.pio; |
de7d789a CO |
3450 | long delta; |
3451 | int r; | |
5fdbf976 | 3452 | unsigned long val; |
de7d789a CO |
3453 | |
3454 | if (!io->string) { | |
5fdbf976 MT |
3455 | if (io->in) { |
3456 | val = kvm_register_read(vcpu, VCPU_REGS_RAX); | |
3457 | memcpy(&val, vcpu->arch.pio_data, io->size); | |
3458 | kvm_register_write(vcpu, VCPU_REGS_RAX, val); | |
3459 | } | |
de7d789a CO |
3460 | } else { |
3461 | if (io->in) { | |
3462 | r = pio_copy_data(vcpu); | |
5fdbf976 | 3463 | if (r) |
de7d789a | 3464 | return r; |
de7d789a CO |
3465 | } |
3466 | ||
3467 | delta = 1; | |
3468 | if (io->rep) { | |
3469 | delta *= io->cur_count; | |
3470 | /* | |
3471 | * The size of the register should really depend on | |
3472 | * current address size. | |
3473 | */ | |
5fdbf976 MT |
3474 | val = kvm_register_read(vcpu, VCPU_REGS_RCX); |
3475 | val -= delta; | |
3476 | kvm_register_write(vcpu, VCPU_REGS_RCX, val); | |
de7d789a CO |
3477 | } |
3478 | if (io->down) | |
3479 | delta = -delta; | |
3480 | delta *= io->size; | |
5fdbf976 MT |
3481 | if (io->in) { |
3482 | val = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
3483 | val += delta; | |
3484 | kvm_register_write(vcpu, VCPU_REGS_RDI, val); | |
3485 | } else { | |
3486 | val = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
3487 | val += delta; | |
3488 | kvm_register_write(vcpu, VCPU_REGS_RSI, val); | |
3489 | } | |
de7d789a CO |
3490 | } |
3491 | ||
de7d789a CO |
3492 | io->count -= io->cur_count; |
3493 | io->cur_count = 0; | |
3494 | ||
3495 | return 0; | |
3496 | } | |
3497 | ||
bda9020e | 3498 | static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) |
de7d789a CO |
3499 | { |
3500 | /* TODO: String I/O for in kernel device */ | |
bda9020e | 3501 | int r; |
de7d789a | 3502 | |
ad312c7c | 3503 | if (vcpu->arch.pio.in) |
e93f8a0f | 3504 | r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port, |
bda9020e | 3505 | vcpu->arch.pio.size, pd); |
de7d789a | 3506 | else |
e93f8a0f MT |
3507 | r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS, |
3508 | vcpu->arch.pio.port, vcpu->arch.pio.size, | |
3509 | pd); | |
bda9020e | 3510 | return r; |
de7d789a CO |
3511 | } |
3512 | ||
bda9020e | 3513 | static int pio_string_write(struct kvm_vcpu *vcpu) |
de7d789a | 3514 | { |
ad312c7c ZX |
3515 | struct kvm_pio_request *io = &vcpu->arch.pio; |
3516 | void *pd = vcpu->arch.pio_data; | |
bda9020e | 3517 | int i, r = 0; |
de7d789a | 3518 | |
de7d789a | 3519 | for (i = 0; i < io->cur_count; i++) { |
e93f8a0f | 3520 | if (kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS, |
bda9020e MT |
3521 | io->port, io->size, pd)) { |
3522 | r = -EOPNOTSUPP; | |
3523 | break; | |
3524 | } | |
de7d789a CO |
3525 | pd += io->size; |
3526 | } | |
bda9020e | 3527 | return r; |
de7d789a CO |
3528 | } |
3529 | ||
851ba692 | 3530 | int kvm_emulate_pio(struct kvm_vcpu *vcpu, int in, int size, unsigned port) |
de7d789a | 3531 | { |
5fdbf976 | 3532 | unsigned long val; |
de7d789a CO |
3533 | |
3534 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
3535 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; | |
ad312c7c | 3536 | vcpu->run->io.size = vcpu->arch.pio.size = size; |
de7d789a | 3537 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; |
ad312c7c ZX |
3538 | vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1; |
3539 | vcpu->run->io.port = vcpu->arch.pio.port = port; | |
3540 | vcpu->arch.pio.in = in; | |
3541 | vcpu->arch.pio.string = 0; | |
3542 | vcpu->arch.pio.down = 0; | |
ad312c7c | 3543 | vcpu->arch.pio.rep = 0; |
de7d789a | 3544 | |
229456fc MT |
3545 | trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port, |
3546 | size, 1); | |
2714d1d3 | 3547 | |
5fdbf976 MT |
3548 | val = kvm_register_read(vcpu, VCPU_REGS_RAX); |
3549 | memcpy(vcpu->arch.pio_data, &val, 4); | |
de7d789a | 3550 | |
bda9020e | 3551 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { |
de7d789a CO |
3552 | complete_pio(vcpu); |
3553 | return 1; | |
3554 | } | |
3555 | return 0; | |
3556 | } | |
3557 | EXPORT_SYMBOL_GPL(kvm_emulate_pio); | |
3558 | ||
851ba692 | 3559 | int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, int in, |
de7d789a CO |
3560 | int size, unsigned long count, int down, |
3561 | gva_t address, int rep, unsigned port) | |
3562 | { | |
3563 | unsigned now, in_page; | |
0f346074 | 3564 | int ret = 0; |
de7d789a CO |
3565 | |
3566 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
3567 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; | |
ad312c7c | 3568 | vcpu->run->io.size = vcpu->arch.pio.size = size; |
de7d789a | 3569 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; |
ad312c7c ZX |
3570 | vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count; |
3571 | vcpu->run->io.port = vcpu->arch.pio.port = port; | |
3572 | vcpu->arch.pio.in = in; | |
3573 | vcpu->arch.pio.string = 1; | |
3574 | vcpu->arch.pio.down = down; | |
ad312c7c | 3575 | vcpu->arch.pio.rep = rep; |
de7d789a | 3576 | |
229456fc MT |
3577 | trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port, |
3578 | size, count); | |
2714d1d3 | 3579 | |
de7d789a CO |
3580 | if (!count) { |
3581 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
3582 | return 1; | |
3583 | } | |
3584 | ||
3585 | if (!down) | |
3586 | in_page = PAGE_SIZE - offset_in_page(address); | |
3587 | else | |
3588 | in_page = offset_in_page(address) + size; | |
3589 | now = min(count, (unsigned long)in_page / size); | |
0f346074 | 3590 | if (!now) |
de7d789a | 3591 | now = 1; |
de7d789a CO |
3592 | if (down) { |
3593 | /* | |
3594 | * String I/O in reverse. Yuck. Kill the guest, fix later. | |
3595 | */ | |
3596 | pr_unimpl(vcpu, "guest string pio down\n"); | |
c1a5d4f9 | 3597 | kvm_inject_gp(vcpu, 0); |
de7d789a CO |
3598 | return 1; |
3599 | } | |
3600 | vcpu->run->io.count = now; | |
ad312c7c | 3601 | vcpu->arch.pio.cur_count = now; |
de7d789a | 3602 | |
ad312c7c | 3603 | if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count) |
de7d789a CO |
3604 | kvm_x86_ops->skip_emulated_instruction(vcpu); |
3605 | ||
0f346074 | 3606 | vcpu->arch.pio.guest_gva = address; |
de7d789a | 3607 | |
ad312c7c | 3608 | if (!vcpu->arch.pio.in) { |
de7d789a CO |
3609 | /* string PIO write */ |
3610 | ret = pio_copy_data(vcpu); | |
0f346074 IE |
3611 | if (ret == X86EMUL_PROPAGATE_FAULT) { |
3612 | kvm_inject_gp(vcpu, 0); | |
3613 | return 1; | |
3614 | } | |
bda9020e | 3615 | if (ret == 0 && !pio_string_write(vcpu)) { |
de7d789a | 3616 | complete_pio(vcpu); |
ad312c7c | 3617 | if (vcpu->arch.pio.count == 0) |
de7d789a CO |
3618 | ret = 1; |
3619 | } | |
bda9020e MT |
3620 | } |
3621 | /* no string PIO read support yet */ | |
de7d789a CO |
3622 | |
3623 | return ret; | |
3624 | } | |
3625 | EXPORT_SYMBOL_GPL(kvm_emulate_pio_string); | |
3626 | ||
c8076604 GH |
3627 | static void bounce_off(void *info) |
3628 | { | |
3629 | /* nothing */ | |
3630 | } | |
3631 | ||
c8076604 GH |
3632 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, |
3633 | void *data) | |
3634 | { | |
3635 | struct cpufreq_freqs *freq = data; | |
3636 | struct kvm *kvm; | |
3637 | struct kvm_vcpu *vcpu; | |
3638 | int i, send_ipi = 0; | |
3639 | ||
c8076604 GH |
3640 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) |
3641 | return 0; | |
3642 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
3643 | return 0; | |
0cca7907 | 3644 | per_cpu(cpu_tsc_khz, freq->cpu) = freq->new; |
c8076604 GH |
3645 | |
3646 | spin_lock(&kvm_lock); | |
3647 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
988a2cae | 3648 | kvm_for_each_vcpu(i, vcpu, kvm) { |
c8076604 GH |
3649 | if (vcpu->cpu != freq->cpu) |
3650 | continue; | |
3651 | if (!kvm_request_guest_time_update(vcpu)) | |
3652 | continue; | |
3653 | if (vcpu->cpu != smp_processor_id()) | |
3654 | send_ipi++; | |
3655 | } | |
3656 | } | |
3657 | spin_unlock(&kvm_lock); | |
3658 | ||
3659 | if (freq->old < freq->new && send_ipi) { | |
3660 | /* | |
3661 | * We upscale the frequency. Must make the guest | |
3662 | * doesn't see old kvmclock values while running with | |
3663 | * the new frequency, otherwise we risk the guest sees | |
3664 | * time go backwards. | |
3665 | * | |
3666 | * In case we update the frequency for another cpu | |
3667 | * (which might be in guest context) send an interrupt | |
3668 | * to kick the cpu out of guest context. Next time | |
3669 | * guest context is entered kvmclock will be updated, | |
3670 | * so the guest will not see stale values. | |
3671 | */ | |
3672 | smp_call_function_single(freq->cpu, bounce_off, NULL, 1); | |
3673 | } | |
3674 | return 0; | |
3675 | } | |
3676 | ||
3677 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
3678 | .notifier_call = kvmclock_cpufreq_notifier | |
3679 | }; | |
3680 | ||
b820cc0c ZA |
3681 | static void kvm_timer_init(void) |
3682 | { | |
3683 | int cpu; | |
3684 | ||
b820cc0c | 3685 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
b820cc0c ZA |
3686 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
3687 | CPUFREQ_TRANSITION_NOTIFIER); | |
6b7d7e76 ZA |
3688 | for_each_online_cpu(cpu) { |
3689 | unsigned long khz = cpufreq_get(cpu); | |
3690 | if (!khz) | |
3691 | khz = tsc_khz; | |
3692 | per_cpu(cpu_tsc_khz, cpu) = khz; | |
3693 | } | |
0cca7907 ZA |
3694 | } else { |
3695 | for_each_possible_cpu(cpu) | |
3696 | per_cpu(cpu_tsc_khz, cpu) = tsc_khz; | |
b820cc0c ZA |
3697 | } |
3698 | } | |
3699 | ||
f8c16bba | 3700 | int kvm_arch_init(void *opaque) |
043405e1 | 3701 | { |
b820cc0c | 3702 | int r; |
f8c16bba ZX |
3703 | struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque; |
3704 | ||
f8c16bba ZX |
3705 | if (kvm_x86_ops) { |
3706 | printk(KERN_ERR "kvm: already loaded the other module\n"); | |
56c6d28a ZX |
3707 | r = -EEXIST; |
3708 | goto out; | |
f8c16bba ZX |
3709 | } |
3710 | ||
3711 | if (!ops->cpu_has_kvm_support()) { | |
3712 | printk(KERN_ERR "kvm: no hardware support\n"); | |
56c6d28a ZX |
3713 | r = -EOPNOTSUPP; |
3714 | goto out; | |
f8c16bba ZX |
3715 | } |
3716 | if (ops->disabled_by_bios()) { | |
3717 | printk(KERN_ERR "kvm: disabled by bios\n"); | |
56c6d28a ZX |
3718 | r = -EOPNOTSUPP; |
3719 | goto out; | |
f8c16bba ZX |
3720 | } |
3721 | ||
97db56ce AK |
3722 | r = kvm_mmu_module_init(); |
3723 | if (r) | |
3724 | goto out; | |
3725 | ||
3726 | kvm_init_msr_list(); | |
3727 | ||
f8c16bba | 3728 | kvm_x86_ops = ops; |
56c6d28a | 3729 | kvm_mmu_set_nonpresent_ptes(0ull, 0ull); |
7b52345e SY |
3730 | kvm_mmu_set_base_ptes(PT_PRESENT_MASK); |
3731 | kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, | |
4b12f0de | 3732 | PT_DIRTY_MASK, PT64_NX_MASK, 0); |
c8076604 | 3733 | |
b820cc0c | 3734 | kvm_timer_init(); |
c8076604 | 3735 | |
f8c16bba | 3736 | return 0; |
56c6d28a ZX |
3737 | |
3738 | out: | |
56c6d28a | 3739 | return r; |
043405e1 | 3740 | } |
8776e519 | 3741 | |
f8c16bba ZX |
3742 | void kvm_arch_exit(void) |
3743 | { | |
888d256e JK |
3744 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
3745 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
3746 | CPUFREQ_TRANSITION_NOTIFIER); | |
f8c16bba | 3747 | kvm_x86_ops = NULL; |
56c6d28a ZX |
3748 | kvm_mmu_module_exit(); |
3749 | } | |
f8c16bba | 3750 | |
8776e519 HB |
3751 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) |
3752 | { | |
3753 | ++vcpu->stat.halt_exits; | |
3754 | if (irqchip_in_kernel(vcpu->kvm)) { | |
a4535290 | 3755 | vcpu->arch.mp_state = KVM_MP_STATE_HALTED; |
8776e519 HB |
3756 | return 1; |
3757 | } else { | |
3758 | vcpu->run->exit_reason = KVM_EXIT_HLT; | |
3759 | return 0; | |
3760 | } | |
3761 | } | |
3762 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); | |
3763 | ||
2f333bcb MT |
3764 | static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0, |
3765 | unsigned long a1) | |
3766 | { | |
3767 | if (is_long_mode(vcpu)) | |
3768 | return a0; | |
3769 | else | |
3770 | return a0 | ((gpa_t)a1 << 32); | |
3771 | } | |
3772 | ||
55cd8e5a GN |
3773 | int kvm_hv_hypercall(struct kvm_vcpu *vcpu) |
3774 | { | |
3775 | u64 param, ingpa, outgpa, ret; | |
3776 | uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0; | |
3777 | bool fast, longmode; | |
3778 | int cs_db, cs_l; | |
3779 | ||
3780 | /* | |
3781 | * hypercall generates UD from non zero cpl and real mode | |
3782 | * per HYPER-V spec | |
3783 | */ | |
3784 | if (kvm_x86_ops->get_cpl(vcpu) != 0 || | |
3785 | !kvm_read_cr0_bits(vcpu, X86_CR0_PE)) { | |
3786 | kvm_queue_exception(vcpu, UD_VECTOR); | |
3787 | return 0; | |
3788 | } | |
3789 | ||
3790 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
3791 | longmode = is_long_mode(vcpu) && cs_l == 1; | |
3792 | ||
3793 | if (!longmode) { | |
ccd46936 GN |
3794 | param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) | |
3795 | (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff); | |
3796 | ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) | | |
3797 | (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff); | |
3798 | outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) | | |
3799 | (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff); | |
55cd8e5a GN |
3800 | } |
3801 | #ifdef CONFIG_X86_64 | |
3802 | else { | |
3803 | param = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
3804 | ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
3805 | outgpa = kvm_register_read(vcpu, VCPU_REGS_R8); | |
3806 | } | |
3807 | #endif | |
3808 | ||
3809 | code = param & 0xffff; | |
3810 | fast = (param >> 16) & 0x1; | |
3811 | rep_cnt = (param >> 32) & 0xfff; | |
3812 | rep_idx = (param >> 48) & 0xfff; | |
3813 | ||
3814 | trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa); | |
3815 | ||
c25bc163 GN |
3816 | switch (code) { |
3817 | case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT: | |
3818 | kvm_vcpu_on_spin(vcpu); | |
3819 | break; | |
3820 | default: | |
3821 | res = HV_STATUS_INVALID_HYPERCALL_CODE; | |
3822 | break; | |
3823 | } | |
55cd8e5a GN |
3824 | |
3825 | ret = res | (((u64)rep_done & 0xfff) << 32); | |
3826 | if (longmode) { | |
3827 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); | |
3828 | } else { | |
3829 | kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32); | |
3830 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff); | |
3831 | } | |
3832 | ||
3833 | return 1; | |
3834 | } | |
3835 | ||
8776e519 HB |
3836 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
3837 | { | |
3838 | unsigned long nr, a0, a1, a2, a3, ret; | |
2f333bcb | 3839 | int r = 1; |
8776e519 | 3840 | |
55cd8e5a GN |
3841 | if (kvm_hv_hypercall_enabled(vcpu->kvm)) |
3842 | return kvm_hv_hypercall(vcpu); | |
3843 | ||
5fdbf976 MT |
3844 | nr = kvm_register_read(vcpu, VCPU_REGS_RAX); |
3845 | a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
3846 | a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
3847 | a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
3848 | a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
8776e519 | 3849 | |
229456fc | 3850 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 3851 | |
8776e519 HB |
3852 | if (!is_long_mode(vcpu)) { |
3853 | nr &= 0xFFFFFFFF; | |
3854 | a0 &= 0xFFFFFFFF; | |
3855 | a1 &= 0xFFFFFFFF; | |
3856 | a2 &= 0xFFFFFFFF; | |
3857 | a3 &= 0xFFFFFFFF; | |
3858 | } | |
3859 | ||
07708c4a JK |
3860 | if (kvm_x86_ops->get_cpl(vcpu) != 0) { |
3861 | ret = -KVM_EPERM; | |
3862 | goto out; | |
3863 | } | |
3864 | ||
8776e519 | 3865 | switch (nr) { |
b93463aa AK |
3866 | case KVM_HC_VAPIC_POLL_IRQ: |
3867 | ret = 0; | |
3868 | break; | |
2f333bcb MT |
3869 | case KVM_HC_MMU_OP: |
3870 | r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret); | |
3871 | break; | |
8776e519 HB |
3872 | default: |
3873 | ret = -KVM_ENOSYS; | |
3874 | break; | |
3875 | } | |
07708c4a | 3876 | out: |
5fdbf976 | 3877 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); |
f11c3a8d | 3878 | ++vcpu->stat.hypercalls; |
2f333bcb | 3879 | return r; |
8776e519 HB |
3880 | } |
3881 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
3882 | ||
3883 | int kvm_fix_hypercall(struct kvm_vcpu *vcpu) | |
3884 | { | |
3885 | char instruction[3]; | |
3886 | int ret = 0; | |
5fdbf976 | 3887 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 3888 | |
8776e519 HB |
3889 | |
3890 | /* | |
3891 | * Blow out the MMU to ensure that no other VCPU has an active mapping | |
3892 | * to ensure that the updated hypercall appears atomically across all | |
3893 | * VCPUs. | |
3894 | */ | |
3895 | kvm_mmu_zap_all(vcpu->kvm); | |
3896 | ||
8776e519 | 3897 | kvm_x86_ops->patch_hypercall(vcpu, instruction); |
5fdbf976 | 3898 | if (emulator_write_emulated(rip, instruction, 3, vcpu) |
8776e519 HB |
3899 | != X86EMUL_CONTINUE) |
3900 | ret = -EFAULT; | |
3901 | ||
8776e519 HB |
3902 | return ret; |
3903 | } | |
3904 | ||
3905 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) | |
3906 | { | |
3907 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; | |
3908 | } | |
3909 | ||
3910 | void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base) | |
3911 | { | |
3912 | struct descriptor_table dt = { limit, base }; | |
3913 | ||
3914 | kvm_x86_ops->set_gdt(vcpu, &dt); | |
3915 | } | |
3916 | ||
3917 | void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base) | |
3918 | { | |
3919 | struct descriptor_table dt = { limit, base }; | |
3920 | ||
3921 | kvm_x86_ops->set_idt(vcpu, &dt); | |
3922 | } | |
3923 | ||
3924 | void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw, | |
3925 | unsigned long *rflags) | |
3926 | { | |
2d3ad1f4 | 3927 | kvm_lmsw(vcpu, msw); |
91586a3b | 3928 | *rflags = kvm_get_rflags(vcpu); |
8776e519 HB |
3929 | } |
3930 | ||
3931 | unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr) | |
3932 | { | |
54e445ca JR |
3933 | unsigned long value; |
3934 | ||
8776e519 HB |
3935 | switch (cr) { |
3936 | case 0: | |
4d4ec087 | 3937 | value = kvm_read_cr0(vcpu); |
54e445ca | 3938 | break; |
8776e519 | 3939 | case 2: |
54e445ca JR |
3940 | value = vcpu->arch.cr2; |
3941 | break; | |
8776e519 | 3942 | case 3: |
54e445ca JR |
3943 | value = vcpu->arch.cr3; |
3944 | break; | |
8776e519 | 3945 | case 4: |
fc78f519 | 3946 | value = kvm_read_cr4(vcpu); |
54e445ca | 3947 | break; |
152ff9be | 3948 | case 8: |
54e445ca JR |
3949 | value = kvm_get_cr8(vcpu); |
3950 | break; | |
8776e519 | 3951 | default: |
b8688d51 | 3952 | vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr); |
8776e519 HB |
3953 | return 0; |
3954 | } | |
54e445ca JR |
3955 | |
3956 | return value; | |
8776e519 HB |
3957 | } |
3958 | ||
3959 | void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val, | |
3960 | unsigned long *rflags) | |
3961 | { | |
3962 | switch (cr) { | |
3963 | case 0: | |
4d4ec087 | 3964 | kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
91586a3b | 3965 | *rflags = kvm_get_rflags(vcpu); |
8776e519 HB |
3966 | break; |
3967 | case 2: | |
ad312c7c | 3968 | vcpu->arch.cr2 = val; |
8776e519 HB |
3969 | break; |
3970 | case 3: | |
2d3ad1f4 | 3971 | kvm_set_cr3(vcpu, val); |
8776e519 HB |
3972 | break; |
3973 | case 4: | |
fc78f519 | 3974 | kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
8776e519 | 3975 | break; |
152ff9be | 3976 | case 8: |
2d3ad1f4 | 3977 | kvm_set_cr8(vcpu, val & 0xfUL); |
152ff9be | 3978 | break; |
8776e519 | 3979 | default: |
b8688d51 | 3980 | vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr); |
8776e519 HB |
3981 | } |
3982 | } | |
3983 | ||
07716717 DK |
3984 | static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i) |
3985 | { | |
ad312c7c ZX |
3986 | struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i]; |
3987 | int j, nent = vcpu->arch.cpuid_nent; | |
07716717 DK |
3988 | |
3989 | e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT; | |
3990 | /* when no next entry is found, the current entry[i] is reselected */ | |
0fdf8e59 | 3991 | for (j = i + 1; ; j = (j + 1) % nent) { |
ad312c7c | 3992 | struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j]; |
07716717 DK |
3993 | if (ej->function == e->function) { |
3994 | ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT; | |
3995 | return j; | |
3996 | } | |
3997 | } | |
3998 | return 0; /* silence gcc, even though control never reaches here */ | |
3999 | } | |
4000 | ||
4001 | /* find an entry with matching function, matching index (if needed), and that | |
4002 | * should be read next (if it's stateful) */ | |
4003 | static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e, | |
4004 | u32 function, u32 index) | |
4005 | { | |
4006 | if (e->function != function) | |
4007 | return 0; | |
4008 | if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index) | |
4009 | return 0; | |
4010 | if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) && | |
19355475 | 4011 | !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT)) |
07716717 DK |
4012 | return 0; |
4013 | return 1; | |
4014 | } | |
4015 | ||
d8017474 AG |
4016 | struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu, |
4017 | u32 function, u32 index) | |
8776e519 HB |
4018 | { |
4019 | int i; | |
d8017474 | 4020 | struct kvm_cpuid_entry2 *best = NULL; |
8776e519 | 4021 | |
ad312c7c | 4022 | for (i = 0; i < vcpu->arch.cpuid_nent; ++i) { |
d8017474 AG |
4023 | struct kvm_cpuid_entry2 *e; |
4024 | ||
ad312c7c | 4025 | e = &vcpu->arch.cpuid_entries[i]; |
07716717 DK |
4026 | if (is_matching_cpuid_entry(e, function, index)) { |
4027 | if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) | |
4028 | move_to_next_stateful_cpuid_entry(vcpu, i); | |
8776e519 HB |
4029 | best = e; |
4030 | break; | |
4031 | } | |
4032 | /* | |
4033 | * Both basic or both extended? | |
4034 | */ | |
4035 | if (((e->function ^ function) & 0x80000000) == 0) | |
4036 | if (!best || e->function > best->function) | |
4037 | best = e; | |
4038 | } | |
d8017474 AG |
4039 | return best; |
4040 | } | |
0e851880 | 4041 | EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry); |
d8017474 | 4042 | |
82725b20 DE |
4043 | int cpuid_maxphyaddr(struct kvm_vcpu *vcpu) |
4044 | { | |
4045 | struct kvm_cpuid_entry2 *best; | |
4046 | ||
4047 | best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0); | |
4048 | if (best) | |
4049 | return best->eax & 0xff; | |
4050 | return 36; | |
4051 | } | |
4052 | ||
d8017474 AG |
4053 | void kvm_emulate_cpuid(struct kvm_vcpu *vcpu) |
4054 | { | |
4055 | u32 function, index; | |
4056 | struct kvm_cpuid_entry2 *best; | |
4057 | ||
4058 | function = kvm_register_read(vcpu, VCPU_REGS_RAX); | |
4059 | index = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
4060 | kvm_register_write(vcpu, VCPU_REGS_RAX, 0); | |
4061 | kvm_register_write(vcpu, VCPU_REGS_RBX, 0); | |
4062 | kvm_register_write(vcpu, VCPU_REGS_RCX, 0); | |
4063 | kvm_register_write(vcpu, VCPU_REGS_RDX, 0); | |
4064 | best = kvm_find_cpuid_entry(vcpu, function, index); | |
8776e519 | 4065 | if (best) { |
5fdbf976 MT |
4066 | kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax); |
4067 | kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx); | |
4068 | kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx); | |
4069 | kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx); | |
8776e519 | 4070 | } |
8776e519 | 4071 | kvm_x86_ops->skip_emulated_instruction(vcpu); |
229456fc MT |
4072 | trace_kvm_cpuid(function, |
4073 | kvm_register_read(vcpu, VCPU_REGS_RAX), | |
4074 | kvm_register_read(vcpu, VCPU_REGS_RBX), | |
4075 | kvm_register_read(vcpu, VCPU_REGS_RCX), | |
4076 | kvm_register_read(vcpu, VCPU_REGS_RDX)); | |
8776e519 HB |
4077 | } |
4078 | EXPORT_SYMBOL_GPL(kvm_emulate_cpuid); | |
d0752060 | 4079 | |
b6c7a5dc HB |
4080 | /* |
4081 | * Check if userspace requested an interrupt window, and that the | |
4082 | * interrupt window is open. | |
4083 | * | |
4084 | * No need to exit to userspace if we already have an interrupt queued. | |
4085 | */ | |
851ba692 | 4086 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 4087 | { |
8061823a | 4088 | return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) && |
851ba692 | 4089 | vcpu->run->request_interrupt_window && |
5df56646 | 4090 | kvm_arch_interrupt_allowed(vcpu)); |
b6c7a5dc HB |
4091 | } |
4092 | ||
851ba692 | 4093 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 4094 | { |
851ba692 AK |
4095 | struct kvm_run *kvm_run = vcpu->run; |
4096 | ||
91586a3b | 4097 | kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; |
2d3ad1f4 | 4098 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 4099 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
4531220b | 4100 | if (irqchip_in_kernel(vcpu->kvm)) |
b6c7a5dc | 4101 | kvm_run->ready_for_interrupt_injection = 1; |
4531220b | 4102 | else |
b6c7a5dc | 4103 | kvm_run->ready_for_interrupt_injection = |
fa9726b0 GN |
4104 | kvm_arch_interrupt_allowed(vcpu) && |
4105 | !kvm_cpu_has_interrupt(vcpu) && | |
4106 | !kvm_event_needs_reinjection(vcpu); | |
b6c7a5dc HB |
4107 | } |
4108 | ||
b93463aa AK |
4109 | static void vapic_enter(struct kvm_vcpu *vcpu) |
4110 | { | |
4111 | struct kvm_lapic *apic = vcpu->arch.apic; | |
4112 | struct page *page; | |
4113 | ||
4114 | if (!apic || !apic->vapic_addr) | |
4115 | return; | |
4116 | ||
4117 | page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT); | |
72dc67a6 IE |
4118 | |
4119 | vcpu->arch.apic->vapic_page = page; | |
b93463aa AK |
4120 | } |
4121 | ||
4122 | static void vapic_exit(struct kvm_vcpu *vcpu) | |
4123 | { | |
4124 | struct kvm_lapic *apic = vcpu->arch.apic; | |
f656ce01 | 4125 | int idx; |
b93463aa AK |
4126 | |
4127 | if (!apic || !apic->vapic_addr) | |
4128 | return; | |
4129 | ||
f656ce01 | 4130 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
b93463aa AK |
4131 | kvm_release_page_dirty(apic->vapic_page); |
4132 | mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT); | |
f656ce01 | 4133 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b93463aa AK |
4134 | } |
4135 | ||
95ba8273 GN |
4136 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
4137 | { | |
4138 | int max_irr, tpr; | |
4139 | ||
4140 | if (!kvm_x86_ops->update_cr8_intercept) | |
4141 | return; | |
4142 | ||
88c808fd AK |
4143 | if (!vcpu->arch.apic) |
4144 | return; | |
4145 | ||
8db3baa2 GN |
4146 | if (!vcpu->arch.apic->vapic_addr) |
4147 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
4148 | else | |
4149 | max_irr = -1; | |
95ba8273 GN |
4150 | |
4151 | if (max_irr != -1) | |
4152 | max_irr >>= 4; | |
4153 | ||
4154 | tpr = kvm_lapic_get_cr8(vcpu); | |
4155 | ||
4156 | kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); | |
4157 | } | |
4158 | ||
851ba692 | 4159 | static void inject_pending_event(struct kvm_vcpu *vcpu) |
95ba8273 GN |
4160 | { |
4161 | /* try to reinject previous events if any */ | |
b59bb7bd GN |
4162 | if (vcpu->arch.exception.pending) { |
4163 | kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, | |
4164 | vcpu->arch.exception.has_error_code, | |
4165 | vcpu->arch.exception.error_code); | |
4166 | return; | |
4167 | } | |
4168 | ||
95ba8273 GN |
4169 | if (vcpu->arch.nmi_injected) { |
4170 | kvm_x86_ops->set_nmi(vcpu); | |
4171 | return; | |
4172 | } | |
4173 | ||
4174 | if (vcpu->arch.interrupt.pending) { | |
66fd3f7f | 4175 | kvm_x86_ops->set_irq(vcpu); |
95ba8273 GN |
4176 | return; |
4177 | } | |
4178 | ||
4179 | /* try to inject new event if pending */ | |
4180 | if (vcpu->arch.nmi_pending) { | |
4181 | if (kvm_x86_ops->nmi_allowed(vcpu)) { | |
4182 | vcpu->arch.nmi_pending = false; | |
4183 | vcpu->arch.nmi_injected = true; | |
4184 | kvm_x86_ops->set_nmi(vcpu); | |
4185 | } | |
4186 | } else if (kvm_cpu_has_interrupt(vcpu)) { | |
4187 | if (kvm_x86_ops->interrupt_allowed(vcpu)) { | |
66fd3f7f GN |
4188 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), |
4189 | false); | |
4190 | kvm_x86_ops->set_irq(vcpu); | |
95ba8273 GN |
4191 | } |
4192 | } | |
4193 | } | |
4194 | ||
851ba692 | 4195 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
4196 | { |
4197 | int r; | |
6a8b1d13 | 4198 | bool req_int_win = !irqchip_in_kernel(vcpu->kvm) && |
851ba692 | 4199 | vcpu->run->request_interrupt_window; |
b6c7a5dc | 4200 | |
2e53d63a MT |
4201 | if (vcpu->requests) |
4202 | if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests)) | |
4203 | kvm_mmu_unload(vcpu); | |
4204 | ||
b6c7a5dc HB |
4205 | r = kvm_mmu_reload(vcpu); |
4206 | if (unlikely(r)) | |
4207 | goto out; | |
4208 | ||
2f52d58c AK |
4209 | if (vcpu->requests) { |
4210 | if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests)) | |
2f599714 | 4211 | __kvm_migrate_timers(vcpu); |
c8076604 GH |
4212 | if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests)) |
4213 | kvm_write_guest_time(vcpu); | |
4731d4c7 MT |
4214 | if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests)) |
4215 | kvm_mmu_sync_roots(vcpu); | |
d4acf7e7 MT |
4216 | if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests)) |
4217 | kvm_x86_ops->tlb_flush(vcpu); | |
b93463aa AK |
4218 | if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS, |
4219 | &vcpu->requests)) { | |
851ba692 | 4220 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
4221 | r = 0; |
4222 | goto out; | |
4223 | } | |
71c4dfaf | 4224 | if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) { |
851ba692 | 4225 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
71c4dfaf JR |
4226 | r = 0; |
4227 | goto out; | |
4228 | } | |
02daab21 AK |
4229 | if (test_and_clear_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests)) { |
4230 | vcpu->fpu_active = 0; | |
4231 | kvm_x86_ops->fpu_deactivate(vcpu); | |
4232 | } | |
2f52d58c | 4233 | } |
b93463aa | 4234 | |
b6c7a5dc HB |
4235 | preempt_disable(); |
4236 | ||
4237 | kvm_x86_ops->prepare_guest_switch(vcpu); | |
4238 | kvm_load_guest_fpu(vcpu); | |
4239 | ||
4240 | local_irq_disable(); | |
4241 | ||
32f88400 MT |
4242 | clear_bit(KVM_REQ_KICK, &vcpu->requests); |
4243 | smp_mb__after_clear_bit(); | |
4244 | ||
d7690175 | 4245 | if (vcpu->requests || need_resched() || signal_pending(current)) { |
c7f0f24b | 4246 | set_bit(KVM_REQ_KICK, &vcpu->requests); |
6c142801 AK |
4247 | local_irq_enable(); |
4248 | preempt_enable(); | |
4249 | r = 1; | |
4250 | goto out; | |
4251 | } | |
4252 | ||
851ba692 | 4253 | inject_pending_event(vcpu); |
b6c7a5dc | 4254 | |
6a8b1d13 GN |
4255 | /* enable NMI/IRQ window open exits if needed */ |
4256 | if (vcpu->arch.nmi_pending) | |
4257 | kvm_x86_ops->enable_nmi_window(vcpu); | |
4258 | else if (kvm_cpu_has_interrupt(vcpu) || req_int_win) | |
4259 | kvm_x86_ops->enable_irq_window(vcpu); | |
4260 | ||
95ba8273 | 4261 | if (kvm_lapic_enabled(vcpu)) { |
8db3baa2 GN |
4262 | update_cr8_intercept(vcpu); |
4263 | kvm_lapic_sync_to_vapic(vcpu); | |
95ba8273 | 4264 | } |
b93463aa | 4265 | |
f656ce01 | 4266 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
3200f405 | 4267 | |
b6c7a5dc HB |
4268 | kvm_guest_enter(); |
4269 | ||
42dbaa5a | 4270 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
4271 | set_debugreg(0, 7); |
4272 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
4273 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
4274 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
4275 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
4276 | } | |
b6c7a5dc | 4277 | |
229456fc | 4278 | trace_kvm_entry(vcpu->vcpu_id); |
851ba692 | 4279 | kvm_x86_ops->run(vcpu); |
b6c7a5dc | 4280 | |
24f1e32c FW |
4281 | /* |
4282 | * If the guest has used debug registers, at least dr7 | |
4283 | * will be disabled while returning to the host. | |
4284 | * If we don't have active breakpoints in the host, we don't | |
4285 | * care about the messed up debug address registers. But if | |
4286 | * we have some of them active, restore the old state. | |
4287 | */ | |
59d8eb53 | 4288 | if (hw_breakpoint_active()) |
24f1e32c | 4289 | hw_breakpoint_restore(); |
42dbaa5a | 4290 | |
32f88400 | 4291 | set_bit(KVM_REQ_KICK, &vcpu->requests); |
b6c7a5dc HB |
4292 | local_irq_enable(); |
4293 | ||
4294 | ++vcpu->stat.exits; | |
4295 | ||
4296 | /* | |
4297 | * We must have an instruction between local_irq_enable() and | |
4298 | * kvm_guest_exit(), so the timer interrupt isn't delayed by | |
4299 | * the interrupt shadow. The stat.exits increment will do nicely. | |
4300 | * But we need to prevent reordering, hence this barrier(): | |
4301 | */ | |
4302 | barrier(); | |
4303 | ||
4304 | kvm_guest_exit(); | |
4305 | ||
4306 | preempt_enable(); | |
4307 | ||
f656ce01 | 4308 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
3200f405 | 4309 | |
b6c7a5dc HB |
4310 | /* |
4311 | * Profile KVM exit RIPs: | |
4312 | */ | |
4313 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
4314 | unsigned long rip = kvm_rip_read(vcpu); |
4315 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
4316 | } |
4317 | ||
298101da | 4318 | |
b93463aa AK |
4319 | kvm_lapic_sync_from_vapic(vcpu); |
4320 | ||
851ba692 | 4321 | r = kvm_x86_ops->handle_exit(vcpu); |
d7690175 MT |
4322 | out: |
4323 | return r; | |
4324 | } | |
b6c7a5dc | 4325 | |
09cec754 | 4326 | |
851ba692 | 4327 | static int __vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
4328 | { |
4329 | int r; | |
f656ce01 | 4330 | struct kvm *kvm = vcpu->kvm; |
d7690175 MT |
4331 | |
4332 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) { | |
1b10bf31 JK |
4333 | pr_debug("vcpu %d received sipi with vector # %x\n", |
4334 | vcpu->vcpu_id, vcpu->arch.sipi_vector); | |
d7690175 | 4335 | kvm_lapic_reset(vcpu); |
5f179287 | 4336 | r = kvm_arch_vcpu_reset(vcpu); |
d7690175 MT |
4337 | if (r) |
4338 | return r; | |
4339 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
b6c7a5dc HB |
4340 | } |
4341 | ||
f656ce01 | 4342 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 MT |
4343 | vapic_enter(vcpu); |
4344 | ||
4345 | r = 1; | |
4346 | while (r > 0) { | |
af2152f5 | 4347 | if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE) |
851ba692 | 4348 | r = vcpu_enter_guest(vcpu); |
d7690175 | 4349 | else { |
f656ce01 | 4350 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
d7690175 | 4351 | kvm_vcpu_block(vcpu); |
f656ce01 | 4352 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 4353 | if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests)) |
09cec754 GN |
4354 | { |
4355 | switch(vcpu->arch.mp_state) { | |
4356 | case KVM_MP_STATE_HALTED: | |
d7690175 | 4357 | vcpu->arch.mp_state = |
09cec754 GN |
4358 | KVM_MP_STATE_RUNNABLE; |
4359 | case KVM_MP_STATE_RUNNABLE: | |
4360 | break; | |
4361 | case KVM_MP_STATE_SIPI_RECEIVED: | |
4362 | default: | |
4363 | r = -EINTR; | |
4364 | break; | |
4365 | } | |
4366 | } | |
d7690175 MT |
4367 | } |
4368 | ||
09cec754 GN |
4369 | if (r <= 0) |
4370 | break; | |
4371 | ||
4372 | clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); | |
4373 | if (kvm_cpu_has_pending_timer(vcpu)) | |
4374 | kvm_inject_pending_timer_irqs(vcpu); | |
4375 | ||
851ba692 | 4376 | if (dm_request_for_irq_injection(vcpu)) { |
09cec754 | 4377 | r = -EINTR; |
851ba692 | 4378 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 GN |
4379 | ++vcpu->stat.request_irq_exits; |
4380 | } | |
4381 | if (signal_pending(current)) { | |
4382 | r = -EINTR; | |
851ba692 | 4383 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 GN |
4384 | ++vcpu->stat.signal_exits; |
4385 | } | |
4386 | if (need_resched()) { | |
f656ce01 | 4387 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
09cec754 | 4388 | kvm_resched(vcpu); |
f656ce01 | 4389 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 4390 | } |
b6c7a5dc HB |
4391 | } |
4392 | ||
f656ce01 | 4393 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
851ba692 | 4394 | post_kvm_run_save(vcpu); |
b6c7a5dc | 4395 | |
b93463aa AK |
4396 | vapic_exit(vcpu); |
4397 | ||
b6c7a5dc HB |
4398 | return r; |
4399 | } | |
4400 | ||
4401 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
4402 | { | |
4403 | int r; | |
4404 | sigset_t sigsaved; | |
4405 | ||
4406 | vcpu_load(vcpu); | |
4407 | ||
ac9f6dc0 AK |
4408 | if (vcpu->sigset_active) |
4409 | sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); | |
4410 | ||
a4535290 | 4411 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
b6c7a5dc | 4412 | kvm_vcpu_block(vcpu); |
d7690175 | 4413 | clear_bit(KVM_REQ_UNHALT, &vcpu->requests); |
ac9f6dc0 AK |
4414 | r = -EAGAIN; |
4415 | goto out; | |
b6c7a5dc HB |
4416 | } |
4417 | ||
b6c7a5dc HB |
4418 | /* re-sync apic's tpr */ |
4419 | if (!irqchip_in_kernel(vcpu->kvm)) | |
2d3ad1f4 | 4420 | kvm_set_cr8(vcpu, kvm_run->cr8); |
b6c7a5dc | 4421 | |
ad312c7c | 4422 | if (vcpu->arch.pio.cur_count) { |
b6c7a5dc HB |
4423 | r = complete_pio(vcpu); |
4424 | if (r) | |
4425 | goto out; | |
4426 | } | |
b6c7a5dc HB |
4427 | if (vcpu->mmio_needed) { |
4428 | memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8); | |
4429 | vcpu->mmio_read_completed = 1; | |
4430 | vcpu->mmio_needed = 0; | |
3200f405 | 4431 | |
f656ce01 | 4432 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
851ba692 | 4433 | r = emulate_instruction(vcpu, vcpu->arch.mmio_fault_cr2, 0, |
571008da | 4434 | EMULTYPE_NO_DECODE); |
f656ce01 | 4435 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
b6c7a5dc HB |
4436 | if (r == EMULATE_DO_MMIO) { |
4437 | /* | |
4438 | * Read-modify-write. Back to userspace. | |
4439 | */ | |
4440 | r = 0; | |
4441 | goto out; | |
4442 | } | |
4443 | } | |
5fdbf976 MT |
4444 | if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL) |
4445 | kvm_register_write(vcpu, VCPU_REGS_RAX, | |
4446 | kvm_run->hypercall.ret); | |
b6c7a5dc | 4447 | |
851ba692 | 4448 | r = __vcpu_run(vcpu); |
b6c7a5dc HB |
4449 | |
4450 | out: | |
4451 | if (vcpu->sigset_active) | |
4452 | sigprocmask(SIG_SETMASK, &sigsaved, NULL); | |
4453 | ||
4454 | vcpu_put(vcpu); | |
4455 | return r; | |
4456 | } | |
4457 | ||
4458 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
4459 | { | |
4460 | vcpu_load(vcpu); | |
4461 | ||
5fdbf976 MT |
4462 | regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); |
4463 | regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
4464 | regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
4465 | regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
4466 | regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
4467 | regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
4468 | regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
4469 | regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); | |
b6c7a5dc | 4470 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
4471 | regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); |
4472 | regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); | |
4473 | regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); | |
4474 | regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); | |
4475 | regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); | |
4476 | regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); | |
4477 | regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); | |
4478 | regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); | |
b6c7a5dc HB |
4479 | #endif |
4480 | ||
5fdbf976 | 4481 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 4482 | regs->rflags = kvm_get_rflags(vcpu); |
b6c7a5dc HB |
4483 | |
4484 | vcpu_put(vcpu); | |
4485 | ||
4486 | return 0; | |
4487 | } | |
4488 | ||
4489 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
4490 | { | |
4491 | vcpu_load(vcpu); | |
4492 | ||
5fdbf976 MT |
4493 | kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); |
4494 | kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); | |
4495 | kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); | |
4496 | kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); | |
4497 | kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); | |
4498 | kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); | |
4499 | kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); | |
4500 | kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); | |
b6c7a5dc | 4501 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
4502 | kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); |
4503 | kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); | |
4504 | kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); | |
4505 | kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); | |
4506 | kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); | |
4507 | kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); | |
4508 | kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); | |
4509 | kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); | |
b6c7a5dc HB |
4510 | #endif |
4511 | ||
5fdbf976 | 4512 | kvm_rip_write(vcpu, regs->rip); |
91586a3b | 4513 | kvm_set_rflags(vcpu, regs->rflags); |
b6c7a5dc | 4514 | |
b4f14abd JK |
4515 | vcpu->arch.exception.pending = false; |
4516 | ||
b6c7a5dc HB |
4517 | vcpu_put(vcpu); |
4518 | ||
4519 | return 0; | |
4520 | } | |
4521 | ||
3e6e0aab GT |
4522 | void kvm_get_segment(struct kvm_vcpu *vcpu, |
4523 | struct kvm_segment *var, int seg) | |
b6c7a5dc | 4524 | { |
14af3f3c | 4525 | kvm_x86_ops->get_segment(vcpu, var, seg); |
b6c7a5dc HB |
4526 | } |
4527 | ||
4528 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) | |
4529 | { | |
4530 | struct kvm_segment cs; | |
4531 | ||
3e6e0aab | 4532 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
4533 | *db = cs.db; |
4534 | *l = cs.l; | |
4535 | } | |
4536 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
4537 | ||
4538 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, | |
4539 | struct kvm_sregs *sregs) | |
4540 | { | |
4541 | struct descriptor_table dt; | |
b6c7a5dc HB |
4542 | |
4543 | vcpu_load(vcpu); | |
4544 | ||
3e6e0aab GT |
4545 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
4546 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
4547 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
4548 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
4549 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
4550 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 4551 | |
3e6e0aab GT |
4552 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
4553 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc HB |
4554 | |
4555 | kvm_x86_ops->get_idt(vcpu, &dt); | |
4556 | sregs->idt.limit = dt.limit; | |
4557 | sregs->idt.base = dt.base; | |
4558 | kvm_x86_ops->get_gdt(vcpu, &dt); | |
4559 | sregs->gdt.limit = dt.limit; | |
4560 | sregs->gdt.base = dt.base; | |
4561 | ||
4d4ec087 | 4562 | sregs->cr0 = kvm_read_cr0(vcpu); |
ad312c7c ZX |
4563 | sregs->cr2 = vcpu->arch.cr2; |
4564 | sregs->cr3 = vcpu->arch.cr3; | |
fc78f519 | 4565 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 4566 | sregs->cr8 = kvm_get_cr8(vcpu); |
ad312c7c | 4567 | sregs->efer = vcpu->arch.shadow_efer; |
b6c7a5dc HB |
4568 | sregs->apic_base = kvm_get_apic_base(vcpu); |
4569 | ||
923c61bb | 4570 | memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); |
b6c7a5dc | 4571 | |
36752c9b | 4572 | if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
4573 | set_bit(vcpu->arch.interrupt.nr, |
4574 | (unsigned long *)sregs->interrupt_bitmap); | |
16d7a191 | 4575 | |
b6c7a5dc HB |
4576 | vcpu_put(vcpu); |
4577 | ||
4578 | return 0; | |
4579 | } | |
4580 | ||
62d9f0db MT |
4581 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
4582 | struct kvm_mp_state *mp_state) | |
4583 | { | |
4584 | vcpu_load(vcpu); | |
4585 | mp_state->mp_state = vcpu->arch.mp_state; | |
4586 | vcpu_put(vcpu); | |
4587 | return 0; | |
4588 | } | |
4589 | ||
4590 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
4591 | struct kvm_mp_state *mp_state) | |
4592 | { | |
4593 | vcpu_load(vcpu); | |
4594 | vcpu->arch.mp_state = mp_state->mp_state; | |
4595 | vcpu_put(vcpu); | |
4596 | return 0; | |
4597 | } | |
4598 | ||
3e6e0aab | 4599 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
b6c7a5dc HB |
4600 | struct kvm_segment *var, int seg) |
4601 | { | |
14af3f3c | 4602 | kvm_x86_ops->set_segment(vcpu, var, seg); |
b6c7a5dc HB |
4603 | } |
4604 | ||
37817f29 IE |
4605 | static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector, |
4606 | struct kvm_segment *kvm_desct) | |
4607 | { | |
46a359e7 AM |
4608 | kvm_desct->base = get_desc_base(seg_desc); |
4609 | kvm_desct->limit = get_desc_limit(seg_desc); | |
c93cd3a5 MT |
4610 | if (seg_desc->g) { |
4611 | kvm_desct->limit <<= 12; | |
4612 | kvm_desct->limit |= 0xfff; | |
4613 | } | |
37817f29 IE |
4614 | kvm_desct->selector = selector; |
4615 | kvm_desct->type = seg_desc->type; | |
4616 | kvm_desct->present = seg_desc->p; | |
4617 | kvm_desct->dpl = seg_desc->dpl; | |
4618 | kvm_desct->db = seg_desc->d; | |
4619 | kvm_desct->s = seg_desc->s; | |
4620 | kvm_desct->l = seg_desc->l; | |
4621 | kvm_desct->g = seg_desc->g; | |
4622 | kvm_desct->avl = seg_desc->avl; | |
4623 | if (!selector) | |
4624 | kvm_desct->unusable = 1; | |
4625 | else | |
4626 | kvm_desct->unusable = 0; | |
4627 | kvm_desct->padding = 0; | |
4628 | } | |
4629 | ||
b8222ad2 AS |
4630 | static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu, |
4631 | u16 selector, | |
4632 | struct descriptor_table *dtable) | |
37817f29 IE |
4633 | { |
4634 | if (selector & 1 << 2) { | |
4635 | struct kvm_segment kvm_seg; | |
4636 | ||
3e6e0aab | 4637 | kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR); |
37817f29 IE |
4638 | |
4639 | if (kvm_seg.unusable) | |
4640 | dtable->limit = 0; | |
4641 | else | |
4642 | dtable->limit = kvm_seg.limit; | |
4643 | dtable->base = kvm_seg.base; | |
4644 | } | |
4645 | else | |
4646 | kvm_x86_ops->get_gdt(vcpu, dtable); | |
4647 | } | |
4648 | ||
4649 | /* allowed just for 8 bytes segments */ | |
4650 | static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, | |
4651 | struct desc_struct *seg_desc) | |
4652 | { | |
4653 | struct descriptor_table dtable; | |
4654 | u16 index = selector >> 3; | |
4655 | ||
b8222ad2 | 4656 | get_segment_descriptor_dtable(vcpu, selector, &dtable); |
37817f29 IE |
4657 | |
4658 | if (dtable.limit < index * 8 + 7) { | |
4659 | kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc); | |
4660 | return 1; | |
4661 | } | |
d9048d32 | 4662 | return kvm_read_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu); |
37817f29 IE |
4663 | } |
4664 | ||
4665 | /* allowed just for 8 bytes segments */ | |
4666 | static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, | |
4667 | struct desc_struct *seg_desc) | |
4668 | { | |
4669 | struct descriptor_table dtable; | |
4670 | u16 index = selector >> 3; | |
4671 | ||
b8222ad2 | 4672 | get_segment_descriptor_dtable(vcpu, selector, &dtable); |
37817f29 IE |
4673 | |
4674 | if (dtable.limit < index * 8 + 7) | |
4675 | return 1; | |
d9048d32 | 4676 | return kvm_write_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu); |
37817f29 IE |
4677 | } |
4678 | ||
abb39119 | 4679 | static gpa_t get_tss_base_addr(struct kvm_vcpu *vcpu, |
37817f29 IE |
4680 | struct desc_struct *seg_desc) |
4681 | { | |
46a359e7 | 4682 | u32 base_addr = get_desc_base(seg_desc); |
37817f29 | 4683 | |
98899aa0 | 4684 | return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr); |
37817f29 IE |
4685 | } |
4686 | ||
37817f29 IE |
4687 | static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg) |
4688 | { | |
4689 | struct kvm_segment kvm_seg; | |
4690 | ||
3e6e0aab | 4691 | kvm_get_segment(vcpu, &kvm_seg, seg); |
37817f29 IE |
4692 | return kvm_seg.selector; |
4693 | } | |
4694 | ||
4695 | static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu, | |
4696 | u16 selector, | |
4697 | struct kvm_segment *kvm_seg) | |
4698 | { | |
4699 | struct desc_struct seg_desc; | |
4700 | ||
4701 | if (load_guest_segment_descriptor(vcpu, selector, &seg_desc)) | |
4702 | return 1; | |
4703 | seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg); | |
4704 | return 0; | |
4705 | } | |
4706 | ||
2259e3a7 | 4707 | static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg) |
f4bbd9aa AK |
4708 | { |
4709 | struct kvm_segment segvar = { | |
4710 | .base = selector << 4, | |
4711 | .limit = 0xffff, | |
4712 | .selector = selector, | |
4713 | .type = 3, | |
4714 | .present = 1, | |
4715 | .dpl = 3, | |
4716 | .db = 0, | |
4717 | .s = 1, | |
4718 | .l = 0, | |
4719 | .g = 0, | |
4720 | .avl = 0, | |
4721 | .unusable = 0, | |
4722 | }; | |
4723 | kvm_x86_ops->set_segment(vcpu, &segvar, seg); | |
4724 | return 0; | |
4725 | } | |
4726 | ||
c0c7c04b AL |
4727 | static int is_vm86_segment(struct kvm_vcpu *vcpu, int seg) |
4728 | { | |
4729 | return (seg != VCPU_SREG_LDTR) && | |
4730 | (seg != VCPU_SREG_TR) && | |
91586a3b | 4731 | (kvm_get_rflags(vcpu) & X86_EFLAGS_VM); |
c0c7c04b AL |
4732 | } |
4733 | ||
cb84b55f MT |
4734 | static void kvm_check_segment_descriptor(struct kvm_vcpu *vcpu, int seg, |
4735 | u16 selector) | |
4736 | { | |
4737 | /* NULL selector is not valid for CS and SS */ | |
4738 | if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS) | |
4739 | if (!selector) | |
4740 | kvm_queue_exception_e(vcpu, TS_VECTOR, selector >> 3); | |
4741 | } | |
4742 | ||
3e6e0aab GT |
4743 | int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, |
4744 | int type_bits, int seg) | |
37817f29 IE |
4745 | { |
4746 | struct kvm_segment kvm_seg; | |
4747 | ||
4d4ec087 | 4748 | if (is_vm86_segment(vcpu, seg) || !(kvm_read_cr0_bits(vcpu, X86_CR0_PE))) |
f4bbd9aa | 4749 | return kvm_load_realmode_segment(vcpu, selector, seg); |
37817f29 IE |
4750 | if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg)) |
4751 | return 1; | |
cb84b55f MT |
4752 | |
4753 | kvm_check_segment_descriptor(vcpu, seg, selector); | |
37817f29 IE |
4754 | kvm_seg.type |= type_bits; |
4755 | ||
4756 | if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS && | |
4757 | seg != VCPU_SREG_LDTR) | |
4758 | if (!kvm_seg.s) | |
4759 | kvm_seg.unusable = 1; | |
4760 | ||
3e6e0aab | 4761 | kvm_set_segment(vcpu, &kvm_seg, seg); |
37817f29 IE |
4762 | return 0; |
4763 | } | |
4764 | ||
4765 | static void save_state_to_tss32(struct kvm_vcpu *vcpu, | |
4766 | struct tss_segment_32 *tss) | |
4767 | { | |
4768 | tss->cr3 = vcpu->arch.cr3; | |
5fdbf976 | 4769 | tss->eip = kvm_rip_read(vcpu); |
91586a3b | 4770 | tss->eflags = kvm_get_rflags(vcpu); |
5fdbf976 MT |
4771 | tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX); |
4772 | tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
4773 | tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
4774 | tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
4775 | tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
4776 | tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP); | |
4777 | tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
4778 | tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
37817f29 IE |
4779 | tss->es = get_segment_selector(vcpu, VCPU_SREG_ES); |
4780 | tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS); | |
4781 | tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS); | |
4782 | tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS); | |
4783 | tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS); | |
4784 | tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS); | |
4785 | tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR); | |
37817f29 IE |
4786 | } |
4787 | ||
4788 | static int load_state_from_tss32(struct kvm_vcpu *vcpu, | |
4789 | struct tss_segment_32 *tss) | |
4790 | { | |
4791 | kvm_set_cr3(vcpu, tss->cr3); | |
4792 | ||
5fdbf976 | 4793 | kvm_rip_write(vcpu, tss->eip); |
91586a3b | 4794 | kvm_set_rflags(vcpu, tss->eflags | 2); |
37817f29 | 4795 | |
5fdbf976 MT |
4796 | kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax); |
4797 | kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx); | |
4798 | kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx); | |
4799 | kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx); | |
4800 | kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp); | |
4801 | kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp); | |
4802 | kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi); | |
4803 | kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi); | |
37817f29 | 4804 | |
3e6e0aab | 4805 | if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR)) |
37817f29 IE |
4806 | return 1; |
4807 | ||
3e6e0aab | 4808 | if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES)) |
37817f29 IE |
4809 | return 1; |
4810 | ||
3e6e0aab | 4811 | if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS)) |
37817f29 IE |
4812 | return 1; |
4813 | ||
3e6e0aab | 4814 | if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS)) |
37817f29 IE |
4815 | return 1; |
4816 | ||
3e6e0aab | 4817 | if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS)) |
37817f29 IE |
4818 | return 1; |
4819 | ||
3e6e0aab | 4820 | if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS)) |
37817f29 IE |
4821 | return 1; |
4822 | ||
3e6e0aab | 4823 | if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS)) |
37817f29 IE |
4824 | return 1; |
4825 | return 0; | |
4826 | } | |
4827 | ||
4828 | static void save_state_to_tss16(struct kvm_vcpu *vcpu, | |
4829 | struct tss_segment_16 *tss) | |
4830 | { | |
5fdbf976 | 4831 | tss->ip = kvm_rip_read(vcpu); |
91586a3b | 4832 | tss->flag = kvm_get_rflags(vcpu); |
5fdbf976 MT |
4833 | tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX); |
4834 | tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
4835 | tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
4836 | tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
4837 | tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
4838 | tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP); | |
4839 | tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
4840 | tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
37817f29 IE |
4841 | |
4842 | tss->es = get_segment_selector(vcpu, VCPU_SREG_ES); | |
4843 | tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS); | |
4844 | tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS); | |
4845 | tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS); | |
4846 | tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR); | |
37817f29 IE |
4847 | } |
4848 | ||
4849 | static int load_state_from_tss16(struct kvm_vcpu *vcpu, | |
4850 | struct tss_segment_16 *tss) | |
4851 | { | |
5fdbf976 | 4852 | kvm_rip_write(vcpu, tss->ip); |
91586a3b | 4853 | kvm_set_rflags(vcpu, tss->flag | 2); |
5fdbf976 MT |
4854 | kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax); |
4855 | kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx); | |
4856 | kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx); | |
4857 | kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx); | |
4858 | kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp); | |
4859 | kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp); | |
4860 | kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si); | |
4861 | kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di); | |
37817f29 | 4862 | |
3e6e0aab | 4863 | if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR)) |
37817f29 IE |
4864 | return 1; |
4865 | ||
3e6e0aab | 4866 | if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES)) |
37817f29 IE |
4867 | return 1; |
4868 | ||
3e6e0aab | 4869 | if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS)) |
37817f29 IE |
4870 | return 1; |
4871 | ||
3e6e0aab | 4872 | if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS)) |
37817f29 IE |
4873 | return 1; |
4874 | ||
3e6e0aab | 4875 | if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS)) |
37817f29 IE |
4876 | return 1; |
4877 | return 0; | |
4878 | } | |
4879 | ||
8b2cf73c | 4880 | static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector, |
b237ac37 GN |
4881 | u16 old_tss_sel, u32 old_tss_base, |
4882 | struct desc_struct *nseg_desc) | |
37817f29 IE |
4883 | { |
4884 | struct tss_segment_16 tss_segment_16; | |
4885 | int ret = 0; | |
4886 | ||
34198bf8 MT |
4887 | if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16, |
4888 | sizeof tss_segment_16)) | |
37817f29 IE |
4889 | goto out; |
4890 | ||
4891 | save_state_to_tss16(vcpu, &tss_segment_16); | |
37817f29 | 4892 | |
34198bf8 MT |
4893 | if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16, |
4894 | sizeof tss_segment_16)) | |
37817f29 | 4895 | goto out; |
34198bf8 MT |
4896 | |
4897 | if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc), | |
4898 | &tss_segment_16, sizeof tss_segment_16)) | |
4899 | goto out; | |
4900 | ||
b237ac37 GN |
4901 | if (old_tss_sel != 0xffff) { |
4902 | tss_segment_16.prev_task_link = old_tss_sel; | |
4903 | ||
4904 | if (kvm_write_guest(vcpu->kvm, | |
4905 | get_tss_base_addr(vcpu, nseg_desc), | |
4906 | &tss_segment_16.prev_task_link, | |
4907 | sizeof tss_segment_16.prev_task_link)) | |
4908 | goto out; | |
4909 | } | |
4910 | ||
37817f29 IE |
4911 | if (load_state_from_tss16(vcpu, &tss_segment_16)) |
4912 | goto out; | |
4913 | ||
4914 | ret = 1; | |
4915 | out: | |
4916 | return ret; | |
4917 | } | |
4918 | ||
8b2cf73c | 4919 | static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector, |
b237ac37 | 4920 | u16 old_tss_sel, u32 old_tss_base, |
37817f29 IE |
4921 | struct desc_struct *nseg_desc) |
4922 | { | |
4923 | struct tss_segment_32 tss_segment_32; | |
4924 | int ret = 0; | |
4925 | ||
34198bf8 MT |
4926 | if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32, |
4927 | sizeof tss_segment_32)) | |
37817f29 IE |
4928 | goto out; |
4929 | ||
4930 | save_state_to_tss32(vcpu, &tss_segment_32); | |
37817f29 | 4931 | |
34198bf8 MT |
4932 | if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32, |
4933 | sizeof tss_segment_32)) | |
4934 | goto out; | |
4935 | ||
4936 | if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc), | |
4937 | &tss_segment_32, sizeof tss_segment_32)) | |
37817f29 | 4938 | goto out; |
34198bf8 | 4939 | |
b237ac37 GN |
4940 | if (old_tss_sel != 0xffff) { |
4941 | tss_segment_32.prev_task_link = old_tss_sel; | |
4942 | ||
4943 | if (kvm_write_guest(vcpu->kvm, | |
4944 | get_tss_base_addr(vcpu, nseg_desc), | |
4945 | &tss_segment_32.prev_task_link, | |
4946 | sizeof tss_segment_32.prev_task_link)) | |
4947 | goto out; | |
4948 | } | |
4949 | ||
37817f29 IE |
4950 | if (load_state_from_tss32(vcpu, &tss_segment_32)) |
4951 | goto out; | |
4952 | ||
4953 | ret = 1; | |
4954 | out: | |
4955 | return ret; | |
4956 | } | |
4957 | ||
4958 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason) | |
4959 | { | |
4960 | struct kvm_segment tr_seg; | |
4961 | struct desc_struct cseg_desc; | |
4962 | struct desc_struct nseg_desc; | |
4963 | int ret = 0; | |
34198bf8 MT |
4964 | u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR); |
4965 | u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR); | |
37817f29 | 4966 | |
34198bf8 | 4967 | old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base); |
37817f29 | 4968 | |
34198bf8 MT |
4969 | /* FIXME: Handle errors. Failure to read either TSS or their |
4970 | * descriptors should generate a pagefault. | |
4971 | */ | |
37817f29 IE |
4972 | if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc)) |
4973 | goto out; | |
4974 | ||
34198bf8 | 4975 | if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc)) |
37817f29 IE |
4976 | goto out; |
4977 | ||
37817f29 IE |
4978 | if (reason != TASK_SWITCH_IRET) { |
4979 | int cpl; | |
4980 | ||
4981 | cpl = kvm_x86_ops->get_cpl(vcpu); | |
4982 | if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) { | |
4983 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
4984 | return 1; | |
4985 | } | |
4986 | } | |
4987 | ||
46a359e7 | 4988 | if (!nseg_desc.p || get_desc_limit(&nseg_desc) < 0x67) { |
37817f29 IE |
4989 | kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc); |
4990 | return 1; | |
4991 | } | |
4992 | ||
4993 | if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { | |
3fe913e7 | 4994 | cseg_desc.type &= ~(1 << 1); //clear the B flag |
34198bf8 | 4995 | save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc); |
37817f29 IE |
4996 | } |
4997 | ||
4998 | if (reason == TASK_SWITCH_IRET) { | |
91586a3b JK |
4999 | u32 eflags = kvm_get_rflags(vcpu); |
5000 | kvm_set_rflags(vcpu, eflags & ~X86_EFLAGS_NT); | |
37817f29 IE |
5001 | } |
5002 | ||
b237ac37 GN |
5003 | /* set back link to prev task only if NT bit is set in eflags |
5004 | note that old_tss_sel is not used afetr this point */ | |
5005 | if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) | |
5006 | old_tss_sel = 0xffff; | |
5007 | ||
37817f29 | 5008 | if (nseg_desc.type & 8) |
b237ac37 GN |
5009 | ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel, |
5010 | old_tss_base, &nseg_desc); | |
37817f29 | 5011 | else |
b237ac37 GN |
5012 | ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel, |
5013 | old_tss_base, &nseg_desc); | |
37817f29 IE |
5014 | |
5015 | if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) { | |
91586a3b JK |
5016 | u32 eflags = kvm_get_rflags(vcpu); |
5017 | kvm_set_rflags(vcpu, eflags | X86_EFLAGS_NT); | |
37817f29 IE |
5018 | } |
5019 | ||
5020 | if (reason != TASK_SWITCH_IRET) { | |
3fe913e7 | 5021 | nseg_desc.type |= (1 << 1); |
37817f29 IE |
5022 | save_guest_segment_descriptor(vcpu, tss_selector, |
5023 | &nseg_desc); | |
5024 | } | |
5025 | ||
4d4ec087 | 5026 | kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0(vcpu) | X86_CR0_TS); |
37817f29 IE |
5027 | seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg); |
5028 | tr_seg.type = 11; | |
3e6e0aab | 5029 | kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR); |
37817f29 | 5030 | out: |
37817f29 IE |
5031 | return ret; |
5032 | } | |
5033 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
5034 | ||
b6c7a5dc HB |
5035 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, |
5036 | struct kvm_sregs *sregs) | |
5037 | { | |
5038 | int mmu_reset_needed = 0; | |
923c61bb | 5039 | int pending_vec, max_bits; |
b6c7a5dc HB |
5040 | struct descriptor_table dt; |
5041 | ||
5042 | vcpu_load(vcpu); | |
5043 | ||
5044 | dt.limit = sregs->idt.limit; | |
5045 | dt.base = sregs->idt.base; | |
5046 | kvm_x86_ops->set_idt(vcpu, &dt); | |
5047 | dt.limit = sregs->gdt.limit; | |
5048 | dt.base = sregs->gdt.base; | |
5049 | kvm_x86_ops->set_gdt(vcpu, &dt); | |
5050 | ||
ad312c7c ZX |
5051 | vcpu->arch.cr2 = sregs->cr2; |
5052 | mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3; | |
dc7e795e | 5053 | vcpu->arch.cr3 = sregs->cr3; |
b6c7a5dc | 5054 | |
2d3ad1f4 | 5055 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 5056 | |
ad312c7c | 5057 | mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer; |
b6c7a5dc | 5058 | kvm_x86_ops->set_efer(vcpu, sregs->efer); |
b6c7a5dc HB |
5059 | kvm_set_apic_base(vcpu, sregs->apic_base); |
5060 | ||
4d4ec087 | 5061 | mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
b6c7a5dc | 5062 | kvm_x86_ops->set_cr0(vcpu, sregs->cr0); |
d7306163 | 5063 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 5064 | |
fc78f519 | 5065 | mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
b6c7a5dc | 5066 | kvm_x86_ops->set_cr4(vcpu, sregs->cr4); |
7c93be44 | 5067 | if (!is_long_mode(vcpu) && is_pae(vcpu)) { |
ad312c7c | 5068 | load_pdptrs(vcpu, vcpu->arch.cr3); |
7c93be44 MT |
5069 | mmu_reset_needed = 1; |
5070 | } | |
b6c7a5dc HB |
5071 | |
5072 | if (mmu_reset_needed) | |
5073 | kvm_mmu_reset_context(vcpu); | |
5074 | ||
923c61bb GN |
5075 | max_bits = (sizeof sregs->interrupt_bitmap) << 3; |
5076 | pending_vec = find_first_bit( | |
5077 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
5078 | if (pending_vec < max_bits) { | |
66fd3f7f | 5079 | kvm_queue_interrupt(vcpu, pending_vec, false); |
923c61bb GN |
5080 | pr_debug("Set back pending irq %d\n", pending_vec); |
5081 | if (irqchip_in_kernel(vcpu->kvm)) | |
5082 | kvm_pic_clear_isr_ack(vcpu->kvm); | |
b6c7a5dc HB |
5083 | } |
5084 | ||
3e6e0aab GT |
5085 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
5086 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
5087 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
5088 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
5089 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
5090 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 5091 | |
3e6e0aab GT |
5092 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
5093 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 5094 | |
5f0269f5 ME |
5095 | update_cr8_intercept(vcpu); |
5096 | ||
9c3e4aab | 5097 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 5098 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 5099 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
4d4ec087 | 5100 | !(kvm_read_cr0_bits(vcpu, X86_CR0_PE))) |
9c3e4aab MT |
5101 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
5102 | ||
b6c7a5dc HB |
5103 | vcpu_put(vcpu); |
5104 | ||
5105 | return 0; | |
5106 | } | |
5107 | ||
d0bfb940 JK |
5108 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
5109 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 5110 | { |
355be0b9 | 5111 | unsigned long rflags; |
ae675ef0 | 5112 | int i, r; |
b6c7a5dc HB |
5113 | |
5114 | vcpu_load(vcpu); | |
5115 | ||
4f926bf2 JK |
5116 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
5117 | r = -EBUSY; | |
5118 | if (vcpu->arch.exception.pending) | |
5119 | goto unlock_out; | |
5120 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) | |
5121 | kvm_queue_exception(vcpu, DB_VECTOR); | |
5122 | else | |
5123 | kvm_queue_exception(vcpu, BP_VECTOR); | |
5124 | } | |
5125 | ||
91586a3b JK |
5126 | /* |
5127 | * Read rflags as long as potentially injected trace flags are still | |
5128 | * filtered out. | |
5129 | */ | |
5130 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
5131 | |
5132 | vcpu->guest_debug = dbg->control; | |
5133 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
5134 | vcpu->guest_debug = 0; | |
5135 | ||
5136 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
5137 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
5138 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
5139 | vcpu->arch.switch_db_regs = | |
5140 | (dbg->arch.debugreg[7] & DR7_BP_EN_MASK); | |
5141 | } else { | |
5142 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
5143 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
5144 | vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK); | |
5145 | } | |
5146 | ||
94fe45da JK |
5147 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { |
5148 | vcpu->arch.singlestep_cs = | |
5149 | get_segment_selector(vcpu, VCPU_SREG_CS); | |
5150 | vcpu->arch.singlestep_rip = kvm_rip_read(vcpu); | |
5151 | } | |
5152 | ||
91586a3b JK |
5153 | /* |
5154 | * Trigger an rflags update that will inject or remove the trace | |
5155 | * flags. | |
5156 | */ | |
5157 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 5158 | |
355be0b9 | 5159 | kvm_x86_ops->set_guest_debug(vcpu, dbg); |
b6c7a5dc | 5160 | |
4f926bf2 | 5161 | r = 0; |
d0bfb940 | 5162 | |
4f926bf2 | 5163 | unlock_out: |
b6c7a5dc HB |
5164 | vcpu_put(vcpu); |
5165 | ||
5166 | return r; | |
5167 | } | |
5168 | ||
d0752060 HB |
5169 | /* |
5170 | * fxsave fpu state. Taken from x86_64/processor.h. To be killed when | |
5171 | * we have asm/x86/processor.h | |
5172 | */ | |
5173 | struct fxsave { | |
5174 | u16 cwd; | |
5175 | u16 swd; | |
5176 | u16 twd; | |
5177 | u16 fop; | |
5178 | u64 rip; | |
5179 | u64 rdp; | |
5180 | u32 mxcsr; | |
5181 | u32 mxcsr_mask; | |
5182 | u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */ | |
5183 | #ifdef CONFIG_X86_64 | |
5184 | u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */ | |
5185 | #else | |
5186 | u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */ | |
5187 | #endif | |
5188 | }; | |
5189 | ||
8b006791 ZX |
5190 | /* |
5191 | * Translate a guest virtual address to a guest physical address. | |
5192 | */ | |
5193 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
5194 | struct kvm_translation *tr) | |
5195 | { | |
5196 | unsigned long vaddr = tr->linear_address; | |
5197 | gpa_t gpa; | |
f656ce01 | 5198 | int idx; |
8b006791 ZX |
5199 | |
5200 | vcpu_load(vcpu); | |
f656ce01 | 5201 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
ad312c7c | 5202 | gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr); |
f656ce01 | 5203 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 ZX |
5204 | tr->physical_address = gpa; |
5205 | tr->valid = gpa != UNMAPPED_GVA; | |
5206 | tr->writeable = 1; | |
5207 | tr->usermode = 0; | |
8b006791 ZX |
5208 | vcpu_put(vcpu); |
5209 | ||
5210 | return 0; | |
5211 | } | |
5212 | ||
d0752060 HB |
5213 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
5214 | { | |
ad312c7c | 5215 | struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image; |
d0752060 HB |
5216 | |
5217 | vcpu_load(vcpu); | |
5218 | ||
5219 | memcpy(fpu->fpr, fxsave->st_space, 128); | |
5220 | fpu->fcw = fxsave->cwd; | |
5221 | fpu->fsw = fxsave->swd; | |
5222 | fpu->ftwx = fxsave->twd; | |
5223 | fpu->last_opcode = fxsave->fop; | |
5224 | fpu->last_ip = fxsave->rip; | |
5225 | fpu->last_dp = fxsave->rdp; | |
5226 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); | |
5227 | ||
5228 | vcpu_put(vcpu); | |
5229 | ||
5230 | return 0; | |
5231 | } | |
5232 | ||
5233 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
5234 | { | |
ad312c7c | 5235 | struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image; |
d0752060 HB |
5236 | |
5237 | vcpu_load(vcpu); | |
5238 | ||
5239 | memcpy(fxsave->st_space, fpu->fpr, 128); | |
5240 | fxsave->cwd = fpu->fcw; | |
5241 | fxsave->swd = fpu->fsw; | |
5242 | fxsave->twd = fpu->ftwx; | |
5243 | fxsave->fop = fpu->last_opcode; | |
5244 | fxsave->rip = fpu->last_ip; | |
5245 | fxsave->rdp = fpu->last_dp; | |
5246 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); | |
5247 | ||
5248 | vcpu_put(vcpu); | |
5249 | ||
5250 | return 0; | |
5251 | } | |
5252 | ||
5253 | void fx_init(struct kvm_vcpu *vcpu) | |
5254 | { | |
5255 | unsigned after_mxcsr_mask; | |
5256 | ||
bc1a34f1 AA |
5257 | /* |
5258 | * Touch the fpu the first time in non atomic context as if | |
5259 | * this is the first fpu instruction the exception handler | |
5260 | * will fire before the instruction returns and it'll have to | |
5261 | * allocate ram with GFP_KERNEL. | |
5262 | */ | |
5263 | if (!used_math()) | |
d6e88aec | 5264 | kvm_fx_save(&vcpu->arch.host_fx_image); |
bc1a34f1 | 5265 | |
d0752060 HB |
5266 | /* Initialize guest FPU by resetting ours and saving into guest's */ |
5267 | preempt_disable(); | |
d6e88aec AK |
5268 | kvm_fx_save(&vcpu->arch.host_fx_image); |
5269 | kvm_fx_finit(); | |
5270 | kvm_fx_save(&vcpu->arch.guest_fx_image); | |
5271 | kvm_fx_restore(&vcpu->arch.host_fx_image); | |
d0752060 HB |
5272 | preempt_enable(); |
5273 | ||
ad312c7c | 5274 | vcpu->arch.cr0 |= X86_CR0_ET; |
d0752060 | 5275 | after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space); |
ad312c7c ZX |
5276 | vcpu->arch.guest_fx_image.mxcsr = 0x1f80; |
5277 | memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask, | |
d0752060 HB |
5278 | 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask); |
5279 | } | |
5280 | EXPORT_SYMBOL_GPL(fx_init); | |
5281 | ||
5282 | void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) | |
5283 | { | |
5284 | if (!vcpu->fpu_active || vcpu->guest_fpu_loaded) | |
5285 | return; | |
5286 | ||
5287 | vcpu->guest_fpu_loaded = 1; | |
d6e88aec AK |
5288 | kvm_fx_save(&vcpu->arch.host_fx_image); |
5289 | kvm_fx_restore(&vcpu->arch.guest_fx_image); | |
d0752060 HB |
5290 | } |
5291 | EXPORT_SYMBOL_GPL(kvm_load_guest_fpu); | |
5292 | ||
5293 | void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
5294 | { | |
5295 | if (!vcpu->guest_fpu_loaded) | |
5296 | return; | |
5297 | ||
5298 | vcpu->guest_fpu_loaded = 0; | |
d6e88aec AK |
5299 | kvm_fx_save(&vcpu->arch.guest_fx_image); |
5300 | kvm_fx_restore(&vcpu->arch.host_fx_image); | |
f096ed85 | 5301 | ++vcpu->stat.fpu_reload; |
02daab21 | 5302 | set_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests); |
d0752060 HB |
5303 | } |
5304 | EXPORT_SYMBOL_GPL(kvm_put_guest_fpu); | |
e9b11c17 ZX |
5305 | |
5306 | void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) | |
5307 | { | |
7f1ea208 JR |
5308 | if (vcpu->arch.time_page) { |
5309 | kvm_release_page_dirty(vcpu->arch.time_page); | |
5310 | vcpu->arch.time_page = NULL; | |
5311 | } | |
5312 | ||
e9b11c17 ZX |
5313 | kvm_x86_ops->vcpu_free(vcpu); |
5314 | } | |
5315 | ||
5316 | struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, | |
5317 | unsigned int id) | |
5318 | { | |
26e5215f AK |
5319 | return kvm_x86_ops->vcpu_create(kvm, id); |
5320 | } | |
e9b11c17 | 5321 | |
26e5215f AK |
5322 | int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) |
5323 | { | |
5324 | int r; | |
e9b11c17 ZX |
5325 | |
5326 | /* We do fxsave: this must be aligned. */ | |
ad312c7c | 5327 | BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF); |
e9b11c17 | 5328 | |
0bed3b56 | 5329 | vcpu->arch.mtrr_state.have_fixed = 1; |
e9b11c17 ZX |
5330 | vcpu_load(vcpu); |
5331 | r = kvm_arch_vcpu_reset(vcpu); | |
5332 | if (r == 0) | |
5333 | r = kvm_mmu_setup(vcpu); | |
5334 | vcpu_put(vcpu); | |
5335 | if (r < 0) | |
5336 | goto free_vcpu; | |
5337 | ||
26e5215f | 5338 | return 0; |
e9b11c17 ZX |
5339 | free_vcpu: |
5340 | kvm_x86_ops->vcpu_free(vcpu); | |
26e5215f | 5341 | return r; |
e9b11c17 ZX |
5342 | } |
5343 | ||
d40ccc62 | 5344 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 ZX |
5345 | { |
5346 | vcpu_load(vcpu); | |
5347 | kvm_mmu_unload(vcpu); | |
5348 | vcpu_put(vcpu); | |
5349 | ||
5350 | kvm_x86_ops->vcpu_free(vcpu); | |
5351 | } | |
5352 | ||
5353 | int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu) | |
5354 | { | |
448fa4a9 JK |
5355 | vcpu->arch.nmi_pending = false; |
5356 | vcpu->arch.nmi_injected = false; | |
5357 | ||
42dbaa5a JK |
5358 | vcpu->arch.switch_db_regs = 0; |
5359 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); | |
5360 | vcpu->arch.dr6 = DR6_FIXED_1; | |
5361 | vcpu->arch.dr7 = DR7_FIXED_1; | |
5362 | ||
e9b11c17 ZX |
5363 | return kvm_x86_ops->vcpu_reset(vcpu); |
5364 | } | |
5365 | ||
10474ae8 | 5366 | int kvm_arch_hardware_enable(void *garbage) |
e9b11c17 | 5367 | { |
0cca7907 ZA |
5368 | /* |
5369 | * Since this may be called from a hotplug notifcation, | |
5370 | * we can't get the CPU frequency directly. | |
5371 | */ | |
5372 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { | |
5373 | int cpu = raw_smp_processor_id(); | |
5374 | per_cpu(cpu_tsc_khz, cpu) = 0; | |
5375 | } | |
18863bdd AK |
5376 | |
5377 | kvm_shared_msr_cpu_online(); | |
5378 | ||
10474ae8 | 5379 | return kvm_x86_ops->hardware_enable(garbage); |
e9b11c17 ZX |
5380 | } |
5381 | ||
5382 | void kvm_arch_hardware_disable(void *garbage) | |
5383 | { | |
5384 | kvm_x86_ops->hardware_disable(garbage); | |
3548bab5 | 5385 | drop_user_return_notifiers(garbage); |
e9b11c17 ZX |
5386 | } |
5387 | ||
5388 | int kvm_arch_hardware_setup(void) | |
5389 | { | |
5390 | return kvm_x86_ops->hardware_setup(); | |
5391 | } | |
5392 | ||
5393 | void kvm_arch_hardware_unsetup(void) | |
5394 | { | |
5395 | kvm_x86_ops->hardware_unsetup(); | |
5396 | } | |
5397 | ||
5398 | void kvm_arch_check_processor_compat(void *rtn) | |
5399 | { | |
5400 | kvm_x86_ops->check_processor_compatibility(rtn); | |
5401 | } | |
5402 | ||
5403 | int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) | |
5404 | { | |
5405 | struct page *page; | |
5406 | struct kvm *kvm; | |
5407 | int r; | |
5408 | ||
5409 | BUG_ON(vcpu->kvm == NULL); | |
5410 | kvm = vcpu->kvm; | |
5411 | ||
ad312c7c | 5412 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
c5af89b6 | 5413 | if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu)) |
a4535290 | 5414 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
e9b11c17 | 5415 | else |
a4535290 | 5416 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; |
e9b11c17 ZX |
5417 | |
5418 | page = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
5419 | if (!page) { | |
5420 | r = -ENOMEM; | |
5421 | goto fail; | |
5422 | } | |
ad312c7c | 5423 | vcpu->arch.pio_data = page_address(page); |
e9b11c17 ZX |
5424 | |
5425 | r = kvm_mmu_create(vcpu); | |
5426 | if (r < 0) | |
5427 | goto fail_free_pio_data; | |
5428 | ||
5429 | if (irqchip_in_kernel(kvm)) { | |
5430 | r = kvm_create_lapic(vcpu); | |
5431 | if (r < 0) | |
5432 | goto fail_mmu_destroy; | |
5433 | } | |
5434 | ||
890ca9ae HY |
5435 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, |
5436 | GFP_KERNEL); | |
5437 | if (!vcpu->arch.mce_banks) { | |
5438 | r = -ENOMEM; | |
443c39bc | 5439 | goto fail_free_lapic; |
890ca9ae HY |
5440 | } |
5441 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
5442 | ||
e9b11c17 | 5443 | return 0; |
443c39bc WY |
5444 | fail_free_lapic: |
5445 | kvm_free_lapic(vcpu); | |
e9b11c17 ZX |
5446 | fail_mmu_destroy: |
5447 | kvm_mmu_destroy(vcpu); | |
5448 | fail_free_pio_data: | |
ad312c7c | 5449 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 ZX |
5450 | fail: |
5451 | return r; | |
5452 | } | |
5453 | ||
5454 | void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) | |
5455 | { | |
f656ce01 MT |
5456 | int idx; |
5457 | ||
36cb93fd | 5458 | kfree(vcpu->arch.mce_banks); |
e9b11c17 | 5459 | kvm_free_lapic(vcpu); |
f656ce01 | 5460 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
e9b11c17 | 5461 | kvm_mmu_destroy(vcpu); |
f656ce01 | 5462 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
ad312c7c | 5463 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 | 5464 | } |
d19a9cd2 ZX |
5465 | |
5466 | struct kvm *kvm_arch_create_vm(void) | |
5467 | { | |
5468 | struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL); | |
5469 | ||
5470 | if (!kvm) | |
5471 | return ERR_PTR(-ENOMEM); | |
5472 | ||
fef9cce0 MT |
5473 | kvm->arch.aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL); |
5474 | if (!kvm->arch.aliases) { | |
5475 | kfree(kvm); | |
5476 | return ERR_PTR(-ENOMEM); | |
5477 | } | |
5478 | ||
f05e70ac | 5479 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
4d5c5d0f | 5480 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
d19a9cd2 | 5481 | |
5550af4d SY |
5482 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
5483 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
5484 | ||
53f658b3 MT |
5485 | rdtscll(kvm->arch.vm_init_tsc); |
5486 | ||
d19a9cd2 ZX |
5487 | return kvm; |
5488 | } | |
5489 | ||
5490 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) | |
5491 | { | |
5492 | vcpu_load(vcpu); | |
5493 | kvm_mmu_unload(vcpu); | |
5494 | vcpu_put(vcpu); | |
5495 | } | |
5496 | ||
5497 | static void kvm_free_vcpus(struct kvm *kvm) | |
5498 | { | |
5499 | unsigned int i; | |
988a2cae | 5500 | struct kvm_vcpu *vcpu; |
d19a9cd2 ZX |
5501 | |
5502 | /* | |
5503 | * Unpin any mmu pages first. | |
5504 | */ | |
988a2cae GN |
5505 | kvm_for_each_vcpu(i, vcpu, kvm) |
5506 | kvm_unload_vcpu_mmu(vcpu); | |
5507 | kvm_for_each_vcpu(i, vcpu, kvm) | |
5508 | kvm_arch_vcpu_free(vcpu); | |
5509 | ||
5510 | mutex_lock(&kvm->lock); | |
5511 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
5512 | kvm->vcpus[i] = NULL; | |
d19a9cd2 | 5513 | |
988a2cae GN |
5514 | atomic_set(&kvm->online_vcpus, 0); |
5515 | mutex_unlock(&kvm->lock); | |
d19a9cd2 ZX |
5516 | } |
5517 | ||
ad8ba2cd SY |
5518 | void kvm_arch_sync_events(struct kvm *kvm) |
5519 | { | |
ba4cef31 | 5520 | kvm_free_all_assigned_devices(kvm); |
ad8ba2cd SY |
5521 | } |
5522 | ||
d19a9cd2 ZX |
5523 | void kvm_arch_destroy_vm(struct kvm *kvm) |
5524 | { | |
6eb55818 | 5525 | kvm_iommu_unmap_guest(kvm); |
7837699f | 5526 | kvm_free_pit(kvm); |
d7deeeb0 ZX |
5527 | kfree(kvm->arch.vpic); |
5528 | kfree(kvm->arch.vioapic); | |
d19a9cd2 ZX |
5529 | kvm_free_vcpus(kvm); |
5530 | kvm_free_physmem(kvm); | |
3d45830c AK |
5531 | if (kvm->arch.apic_access_page) |
5532 | put_page(kvm->arch.apic_access_page); | |
b7ebfb05 SY |
5533 | if (kvm->arch.ept_identity_pagetable) |
5534 | put_page(kvm->arch.ept_identity_pagetable); | |
64749204 | 5535 | cleanup_srcu_struct(&kvm->srcu); |
fef9cce0 | 5536 | kfree(kvm->arch.aliases); |
d19a9cd2 ZX |
5537 | kfree(kvm); |
5538 | } | |
0de10343 | 5539 | |
f7784b8e MT |
5540 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
5541 | struct kvm_memory_slot *memslot, | |
0de10343 | 5542 | struct kvm_memory_slot old, |
f7784b8e | 5543 | struct kvm_userspace_memory_region *mem, |
0de10343 ZX |
5544 | int user_alloc) |
5545 | { | |
f7784b8e | 5546 | int npages = memslot->npages; |
0de10343 ZX |
5547 | |
5548 | /*To keep backward compatibility with older userspace, | |
5549 | *x86 needs to hanlde !user_alloc case. | |
5550 | */ | |
5551 | if (!user_alloc) { | |
5552 | if (npages && !old.rmap) { | |
604b38ac AA |
5553 | unsigned long userspace_addr; |
5554 | ||
72dc67a6 | 5555 | down_write(¤t->mm->mmap_sem); |
604b38ac AA |
5556 | userspace_addr = do_mmap(NULL, 0, |
5557 | npages * PAGE_SIZE, | |
5558 | PROT_READ | PROT_WRITE, | |
acee3c04 | 5559 | MAP_PRIVATE | MAP_ANONYMOUS, |
604b38ac | 5560 | 0); |
72dc67a6 | 5561 | up_write(¤t->mm->mmap_sem); |
0de10343 | 5562 | |
604b38ac AA |
5563 | if (IS_ERR((void *)userspace_addr)) |
5564 | return PTR_ERR((void *)userspace_addr); | |
5565 | ||
604b38ac | 5566 | memslot->userspace_addr = userspace_addr; |
0de10343 ZX |
5567 | } |
5568 | } | |
5569 | ||
f7784b8e MT |
5570 | |
5571 | return 0; | |
5572 | } | |
5573 | ||
5574 | void kvm_arch_commit_memory_region(struct kvm *kvm, | |
5575 | struct kvm_userspace_memory_region *mem, | |
5576 | struct kvm_memory_slot old, | |
5577 | int user_alloc) | |
5578 | { | |
5579 | ||
5580 | int npages = mem->memory_size >> PAGE_SHIFT; | |
5581 | ||
5582 | if (!user_alloc && !old.user_alloc && old.rmap && !npages) { | |
5583 | int ret; | |
5584 | ||
5585 | down_write(¤t->mm->mmap_sem); | |
5586 | ret = do_munmap(current->mm, old.userspace_addr, | |
5587 | old.npages * PAGE_SIZE); | |
5588 | up_write(¤t->mm->mmap_sem); | |
5589 | if (ret < 0) | |
5590 | printk(KERN_WARNING | |
5591 | "kvm_vm_ioctl_set_memory_region: " | |
5592 | "failed to munmap memory\n"); | |
5593 | } | |
5594 | ||
7c8a83b7 | 5595 | spin_lock(&kvm->mmu_lock); |
f05e70ac | 5596 | if (!kvm->arch.n_requested_mmu_pages) { |
0de10343 ZX |
5597 | unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); |
5598 | kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); | |
5599 | } | |
5600 | ||
5601 | kvm_mmu_slot_remove_write_access(kvm, mem->slot); | |
7c8a83b7 | 5602 | spin_unlock(&kvm->mmu_lock); |
0de10343 | 5603 | } |
1d737c8a | 5604 | |
34d4cb8f MT |
5605 | void kvm_arch_flush_shadow(struct kvm *kvm) |
5606 | { | |
5607 | kvm_mmu_zap_all(kvm); | |
8986ecc0 | 5608 | kvm_reload_remote_mmus(kvm); |
34d4cb8f MT |
5609 | } |
5610 | ||
1d737c8a ZX |
5611 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
5612 | { | |
a4535290 | 5613 | return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE |
a1b37100 GN |
5614 | || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED |
5615 | || vcpu->arch.nmi_pending || | |
5616 | (kvm_arch_interrupt_allowed(vcpu) && | |
5617 | kvm_cpu_has_interrupt(vcpu)); | |
1d737c8a | 5618 | } |
5736199a | 5619 | |
5736199a ZX |
5620 | void kvm_vcpu_kick(struct kvm_vcpu *vcpu) |
5621 | { | |
32f88400 MT |
5622 | int me; |
5623 | int cpu = vcpu->cpu; | |
5736199a ZX |
5624 | |
5625 | if (waitqueue_active(&vcpu->wq)) { | |
5626 | wake_up_interruptible(&vcpu->wq); | |
5627 | ++vcpu->stat.halt_wakeup; | |
5628 | } | |
32f88400 MT |
5629 | |
5630 | me = get_cpu(); | |
5631 | if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu)) | |
5632 | if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests)) | |
5633 | smp_send_reschedule(cpu); | |
e9571ed5 | 5634 | put_cpu(); |
5736199a | 5635 | } |
78646121 GN |
5636 | |
5637 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
5638 | { | |
5639 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
5640 | } | |
229456fc | 5641 | |
94fe45da JK |
5642 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
5643 | { | |
5644 | unsigned long rflags; | |
5645 | ||
5646 | rflags = kvm_x86_ops->get_rflags(vcpu); | |
5647 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
5648 | rflags &= ~(unsigned long)(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
5649 | return rflags; | |
5650 | } | |
5651 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
5652 | ||
5653 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
5654 | { | |
5655 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
5656 | vcpu->arch.singlestep_cs == | |
5657 | get_segment_selector(vcpu, VCPU_SREG_CS) && | |
5658 | vcpu->arch.singlestep_rip == kvm_rip_read(vcpu)) | |
5659 | rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF; | |
5660 | kvm_x86_ops->set_rflags(vcpu, rflags); | |
5661 | } | |
5662 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
5663 | ||
229456fc MT |
5664 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
5665 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); | |
5666 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
5667 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
5668 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
0ac406de | 5669 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); |
d8cabddf | 5670 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 5671 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 5672 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
ec1ff790 | 5673 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 5674 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |