]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blame - arch/x86/kvm/x86.c
projects / mirror_ubuntu-jammy-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: vmx: we do rely on loading DR7 on entry
[mirror_ubuntu-jammy-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 90
97896d04 91struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 92EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 93
476bc001
RR		 94static bool ignore_msrs = 0;
95module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 96
9ed96e87
MT		 97unsigned int min_timer_period_us = 500;
98module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
99
92a1f12d
JR		 100bool kvm_has_tsc_control;
101EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
102u32 kvm_max_guest_tsc_khz;
103EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
104
cc578287
ZA		 105/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
106static u32 tsc_tolerance_ppm = 250;
107module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
108
18863bdd
AK		 109#define KVM_NR_SHARED_MSRS 16
110
111struct kvm_shared_msrs_global {
112 int nr;
2bf78fa7 113 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 114};
115
116struct kvm_shared_msrs {
117 struct user_return_notifier urn;
118 bool registered;
2bf78fa7
SY		 119 struct kvm_shared_msr_values {
120 u64 host;
121 u64 curr;
122 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 123};
124
125static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 126static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 127
417bc304 128struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 129 { "pf_fixed", VCPU_STAT(pf_fixed) },
130 { "pf_guest", VCPU_STAT(pf_guest) },
131 { "tlb_flush", VCPU_STAT(tlb_flush) },
132 { "invlpg", VCPU_STAT(invlpg) },
133 { "exits", VCPU_STAT(exits) },
134 { "io_exits", VCPU_STAT(io_exits) },
135 { "mmio_exits", VCPU_STAT(mmio_exits) },
136 { "signal_exits", VCPU_STAT(signal_exits) },
137 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 138 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 139 { "halt_exits", VCPU_STAT(halt_exits) },
140 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 141 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 142 { "request_irq", VCPU_STAT(request_irq_exits) },
143 { "irq_exits", VCPU_STAT(irq_exits) },
144 { "host_state_reload", VCPU_STAT(host_state_reload) },
145 { "efer_reload", VCPU_STAT(efer_reload) },
146 { "fpu_reload", VCPU_STAT(fpu_reload) },
147 { "insn_emulation", VCPU_STAT(insn_emulation) },
148 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 149 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 150 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 151 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
152 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
153 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
154 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
155 { "mmu_flooded", VM_STAT(mmu_flooded) },
156 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 157 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 158 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 159 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 160 { "largepages", VM_STAT(lpages) },
417bc304
HB		 161 { NULL }
162};
163
2acf923e
DC		 164u64 __read_mostly host_xcr0;
165
b6785def 166static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 167
af585b92
GN		 168static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
169{
170 int i;
171 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
172 vcpu->arch.apf.gfns[i] = ~0;
173}
174
18863bdd
AK		 175static void kvm_on_user_return(struct user_return_notifier *urn)
176{
177 unsigned slot;
18863bdd
AK		 178 struct kvm_shared_msrs *locals
179 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 180 struct kvm_shared_msr_values *values;
18863bdd
AK		 181
182 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 183 values = &locals->values[slot];
184 if (values->host != values->curr) {
185 wrmsrl(shared_msrs_global.msrs[slot], values->host);
186 values->curr = values->host;
18863bdd
AK		 187 }
188 }
189 locals->registered = false;
190 user_return_notifier_unregister(urn);
191}
192
2bf78fa7 193static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 194{
18863bdd 195 u64 value;
013f6a5d
MT		 196 unsigned int cpu = smp_processor_id();
197 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 198
2bf78fa7
SY		 199 /* only read, and nobody should modify it at this time,
200 * so don't need lock */
201 if (slot >= shared_msrs_global.nr) {
202 printk(KERN_ERR "kvm: invalid MSR slot!");
203 return;
204 }
205 rdmsrl_safe(msr, &value);
206 smsr->values[slot].host = value;
207 smsr->values[slot].curr = value;
208}
209
210void kvm_define_shared_msr(unsigned slot, u32 msr)
211{
18863bdd
AK		 212 if (slot >= shared_msrs_global.nr)
213 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 214 shared_msrs_global.msrs[slot] = msr;
215 /* we need ensured the shared_msr_global have been updated */
216 smp_wmb();
18863bdd
AK		 217}
218EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
219
220static void kvm_shared_msr_cpu_online(void)
221{
222 unsigned i;
18863bdd
AK		 223
224 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 225 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 226}
227
d5696725 228void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 229{
013f6a5d
MT		 230 unsigned int cpu = smp_processor_id();
231 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 232
2bf78fa7 233 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 234 return;
2bf78fa7
SY		 235 smsr->values[slot].curr = value;
236 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 237 if (!smsr->registered) {
238 smsr->urn.on_user_return = kvm_on_user_return;
239 user_return_notifier_register(&smsr->urn);
240 smsr->registered = true;
241 }
242}
243EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
244
3548bab5
AK		 245static void drop_user_return_notifiers(void *ignore)
246{
013f6a5d
MT		 247 unsigned int cpu = smp_processor_id();
248 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 249
250 if (smsr->registered)
251 kvm_on_user_return(&smsr->urn);
252}
253
6866b83e
CO		 254u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
255{
8a5a87d9 256 return vcpu->arch.apic_base;
6866b83e
CO		 257}
258EXPORT_SYMBOL_GPL(kvm_get_apic_base);
259
58cb628d
JK		 260int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
261{
262 u64 old_state = vcpu->arch.apic_base &
263 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
264 u64 new_state = msr_info->data &
265 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
266 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
267 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
268
269 if (!msr_info->host_initiated &&
270 ((msr_info->data & reserved_bits) != 0 ||
271 new_state == X2APIC_ENABLE ||
272 (new_state == MSR_IA32_APICBASE_ENABLE &&
273 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
274 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
275 old_state == 0)))
276 return 1;
277
278 kvm_lapic_set_base(vcpu, msr_info->data);
279 return 0;
6866b83e
CO		 280}
281EXPORT_SYMBOL_GPL(kvm_set_apic_base);
282
e3ba45b8
GL		 283asmlinkage void kvm_spurious_fault(void)
284{
285 /* Fault while not rebooting. We want the trace. */
286 BUG();
287}
288EXPORT_SYMBOL_GPL(kvm_spurious_fault);
289
3fd28fce
ED		 290#define EXCPT_BENIGN 0
291#define EXCPT_CONTRIBUTORY 1
292#define EXCPT_PF 2
293
294static int exception_class(int vector)
295{
296 switch (vector) {
297 case PF_VECTOR:
298 return EXCPT_PF;
299 case DE_VECTOR:
300 case TS_VECTOR:
301 case NP_VECTOR:
302 case SS_VECTOR:
303 case GP_VECTOR:
304 return EXCPT_CONTRIBUTORY;
305 default:
306 break;
307 }
308 return EXCPT_BENIGN;
309}
310
311static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 312 unsigned nr, bool has_error, u32 error_code,
313 bool reinject)
3fd28fce
ED		 314{
315 u32 prev_nr;
316 int class1, class2;
317
3842d135
AK		 318 kvm_make_request(KVM_REQ_EVENT, vcpu);
319
3fd28fce
ED		 320 if (!vcpu->arch.exception.pending) {
321 queue:
322 vcpu->arch.exception.pending = true;
323 vcpu->arch.exception.has_error_code = has_error;
324 vcpu->arch.exception.nr = nr;
325 vcpu->arch.exception.error_code = error_code;
3f0fd292 326 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 327 return;
328 }
329
330 /* to check exception */
331 prev_nr = vcpu->arch.exception.nr;
332 if (prev_nr == DF_VECTOR) {
333 /* triple fault -> shutdown */
a8eeb04a 334 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 335 return;
336 }
337 class1 = exception_class(prev_nr);
338 class2 = exception_class(nr);
339 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
340 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
341 /* generate double fault per SDM Table 5-5 */
342 vcpu->arch.exception.pending = true;
343 vcpu->arch.exception.has_error_code = true;
344 vcpu->arch.exception.nr = DF_VECTOR;
345 vcpu->arch.exception.error_code = 0;
346 } else
347 /* replace previous exception with a new one in a hope
348 that instruction re-execution will regenerate lost
349 exception */
350 goto queue;
351}
352
298101da
AK		 353void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
354{
ce7ddec4 355 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 356}
357EXPORT_SYMBOL_GPL(kvm_queue_exception);
358
ce7ddec4
JR		 359void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
360{
361 kvm_multiple_exception(vcpu, nr, false, 0, true);
362}
363EXPORT_SYMBOL_GPL(kvm_requeue_exception);
364
db8fcefa 365void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 366{
db8fcefa
AP		 367 if (err)
368 kvm_inject_gp(vcpu, 0);
369 else
370 kvm_x86_ops->skip_emulated_instruction(vcpu);
371}
372EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 373
6389ee94 374void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 375{
376 ++vcpu->stat.pf_guest;
6389ee94
AK		 377 vcpu->arch.cr2 = fault->address;
378 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 379}
27d6c865 380EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 381
6389ee94 382void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 383{
6389ee94
AK		 384 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
385 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 386 else
6389ee94 387 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 388}
389
3419ffc8
SY		 390void kvm_inject_nmi(struct kvm_vcpu *vcpu)
391{
7460fb4a
AK		 392 atomic_inc(&vcpu->arch.nmi_queued);
393 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 394}
395EXPORT_SYMBOL_GPL(kvm_inject_nmi);
396
298101da
AK		 397void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
398{
ce7ddec4 399 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 400}
401EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
402
ce7ddec4
JR		 403void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
404{
405 kvm_multiple_exception(vcpu, nr, true, error_code, true);
406}
407EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
408
0a79b009
AK		 409/*
410 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
411 * a #GP and return false.
412 */
413bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 414{
0a79b009
AK		 415 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
416 return true;
417 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
418 return false;
298101da 419}
0a79b009 420EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 421
ec92fe44
JR		 422/*
423 * This function will be used to read from the physical memory of the currently
424 * running guest. The difference to kvm_read_guest_page is that this function
425 * can read from guest physical or from the guest's guest physical memory.
426 */
427int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
428 gfn_t ngfn, void *data, int offset, int len,
429 u32 access)
430{
431 gfn_t real_gfn;
432 gpa_t ngpa;
433
434 ngpa = gfn_to_gpa(ngfn);
435 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
436 if (real_gfn == UNMAPPED_GVA)
437 return -EFAULT;
438
439 real_gfn = gpa_to_gfn(real_gfn);
440
441 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
442}
443EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
444
3d06b8bf
JR		 445int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
446 void *data, int offset, int len, u32 access)
447{
448 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
449 data, offset, len, access);
450}
451
a03490ed
CO		 452/*
453 * Load the pae pdptrs. Return true is they are all valid.
454 */
ff03a073 455int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 456{
457 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
458 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
459 int i;
460 int ret;
ff03a073 461 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 462
ff03a073
JR		 463 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
464 offset * sizeof(u64), sizeof(pdpte),
465 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 466 if (ret < 0) {
467 ret = 0;
468 goto out;
469 }
470 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 471 if (is_present_gpte(pdpte[i]) &&
20c466b5 472 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 473 ret = 0;
474 goto out;
475 }
476 }
477 ret = 1;
478
ff03a073 479 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 480 __set_bit(VCPU_EXREG_PDPTR,
481 (unsigned long *)&vcpu->arch.regs_avail);
482 __set_bit(VCPU_EXREG_PDPTR,
483 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 484out:
a03490ed
CO		 485
486 return ret;
487}
cc4b6871 488EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 489
d835dfec
AK		 490static bool pdptrs_changed(struct kvm_vcpu *vcpu)
491{
ff03a073 492 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 493 bool changed = true;
3d06b8bf
JR		 494 int offset;
495 gfn_t gfn;
d835dfec
AK		 496 int r;
497
498 if (is_long_mode(vcpu) || !is_pae(vcpu))
499 return false;
500
6de4f3ad
AK		 501 if (!test_bit(VCPU_EXREG_PDPTR,
502 (unsigned long *)&vcpu->arch.regs_avail))
503 return true;
504
9f8fe504
AK		 505 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
506 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 507 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
508 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 509 if (r < 0)
510 goto out;
ff03a073 511 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 512out:
d835dfec
AK		 513
514 return changed;
515}
516
49a9b07e 517int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 518{
aad82703
SY		 519 unsigned long old_cr0 = kvm_read_cr0(vcpu);
520 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
521 X86_CR0_CD | X86_CR0_NW;
522
f9a48e6a
AK		 523 cr0 |= X86_CR0_ET;
524
ab344828 525#ifdef CONFIG_X86_64
0f12244f
GN		 526 if (cr0 & 0xffffffff00000000UL)
527 return 1;
ab344828
GN		 528#endif
529
530 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 531
0f12244f
GN		 532 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
533 return 1;
a03490ed 534
0f12244f
GN		 535 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
536 return 1;
a03490ed
CO		 537
538 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
539#ifdef CONFIG_X86_64
f6801dff 540 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 541 int cs_db, cs_l;
542
0f12244f
GN		 543 if (!is_pae(vcpu))
544 return 1;
a03490ed 545 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 546 if (cs_l)
547 return 1;
a03490ed
CO		 548 } else
549#endif
ff03a073 550 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 551 kvm_read_cr3(vcpu)))
0f12244f 552 return 1;
a03490ed
CO		 553 }
554
ad756a16
MJ		 555 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
556 return 1;
557
a03490ed 558 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 559
d170c419 560 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 561 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 562 kvm_async_pf_hash_reset(vcpu);
563 }
e5f3f027 564
aad82703
SY		 565 if ((cr0 ^ old_cr0) & update_bits)
566 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 567 return 0;
568}
2d3ad1f4 569EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 570
2d3ad1f4 571void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 572{
49a9b07e 573 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 574}
2d3ad1f4 575EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 576
42bdf991
MT		 577static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
578{
579 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
580 !vcpu->guest_xcr0_loaded) {
581 /* kvm_set_xcr() also depends on this */
582 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
583 vcpu->guest_xcr0_loaded = 1;
584 }
585}
586
587static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
588{
589 if (vcpu->guest_xcr0_loaded) {
590 if (vcpu->arch.xcr0 != host_xcr0)
591 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
592 vcpu->guest_xcr0_loaded = 0;
593 }
594}
595
2acf923e
DC		 596int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
597{
56c103ec
LJ		 598 u64 xcr0 = xcr;
599 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 600 u64 valid_bits;
2acf923e
DC		 601
602 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
603 if (index != XCR_XFEATURE_ENABLED_MASK)
604 return 1;
2acf923e
DC		 605 if (!(xcr0 & XSTATE_FP))
606 return 1;
607 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
608 return 1;
46c34cb0
PB		 609
610 /*
611 * Do not allow the guest to set bits that we do not support
612 * saving. However, xcr0 bit 0 is always set, even if the
613 * emulated CPU does not support XSAVE (see fx_init).
614 */
615 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
616 if (xcr0 & ~valid_bits)
2acf923e 617 return 1;
46c34cb0 618
390bd528
LJ		 619 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
620 return 1;
621
42bdf991 622 kvm_put_guest_xcr0(vcpu);
2acf923e 623 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 624
625 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
626 kvm_update_cpuid(vcpu);
2acf923e
DC		 627 return 0;
628}
629
630int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
631{
764bcbc5
Z		 632 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
633 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 634 kvm_inject_gp(vcpu, 0);
635 return 1;
636 }
637 return 0;
638}
639EXPORT_SYMBOL_GPL(kvm_set_xcr);
640
a83b29c6 641int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 642{
fc78f519 643 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 644 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
645 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 646 if (cr4 & CR4_RESERVED_BITS)
647 return 1;
a03490ed 648
2acf923e
DC		 649 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
650 return 1;
651
c68b734f
YW		 652 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
653 return 1;
654
afcbf13f 655 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 656 return 1;
657
a03490ed 658 if (is_long_mode(vcpu)) {
0f12244f
GN		 659 if (!(cr4 & X86_CR4_PAE))
660 return 1;
a2edf57f
AK		 661 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
662 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 663 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
664 kvm_read_cr3(vcpu)))
0f12244f
GN		 665 return 1;
666
ad756a16
MJ		 667 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
668 if (!guest_cpuid_has_pcid(vcpu))
669 return 1;
670
671 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
672 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
673 return 1;
674 }
675
5e1746d6 676 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 677 return 1;
a03490ed 678
ad756a16
MJ		 679 if (((cr4 ^ old_cr4) & pdptr_bits) ||
680 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 681 kvm_mmu_reset_context(vcpu);
0f12244f 682
2acf923e 683 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 684 kvm_update_cpuid(vcpu);
2acf923e 685
0f12244f
GN		 686 return 0;
687}
2d3ad1f4 688EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 689
2390218b 690int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 691{
9f8fe504 692 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 693 kvm_mmu_sync_roots(vcpu);
d835dfec 694 kvm_mmu_flush_tlb(vcpu);
0f12244f 695 return 0;
d835dfec
AK		 696 }
697
a03490ed 698 if (is_long_mode(vcpu)) {
471842ec 699 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
ad756a16
MJ		 700 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
701 return 1;
702 } else
703 if (cr3 & CR3_L_MODE_RESERVED_BITS)
704 return 1;
a03490ed
CO		 705 } else {
706 if (is_pae(vcpu)) {
0f12244f
GN		 707 if (cr3 & CR3_PAE_RESERVED_BITS)
708 return 1;
ff03a073
JR		 709 if (is_paging(vcpu) &&
710 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 711 return 1;
a03490ed
CO		 712 }
713 /*
714 * We don't check reserved bits in nonpae mode, because
715 * this isn't enforced, and VMware depends on this.
716 */
717 }
718
0f12244f 719 vcpu->arch.cr3 = cr3;
aff48baa 720 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 721 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 722 return 0;
723}
2d3ad1f4 724EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 725
eea1cff9 726int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 727{
0f12244f
GN		 728 if (cr8 & CR8_RESERVED_BITS)
729 return 1;
a03490ed
CO		 730 if (irqchip_in_kernel(vcpu->kvm))
731 kvm_lapic_set_tpr(vcpu, cr8);
732 else
ad312c7c 733 vcpu->arch.cr8 = cr8;
0f12244f
GN		 734 return 0;
735}
2d3ad1f4 736EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 737
2d3ad1f4 738unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 739{
740 if (irqchip_in_kernel(vcpu->kvm))
741 return kvm_lapic_get_cr8(vcpu);
742 else
ad312c7c 743 return vcpu->arch.cr8;
a03490ed 744}
2d3ad1f4 745EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 746
73aaf249
JK		 747static void kvm_update_dr6(struct kvm_vcpu *vcpu)
748{
749 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
750 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
751}
752
c8639010
JK		 753static void kvm_update_dr7(struct kvm_vcpu *vcpu)
754{
755 unsigned long dr7;
756
757 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
758 dr7 = vcpu->arch.guest_debug_dr7;
759 else
760 dr7 = vcpu->arch.dr7;
761 kvm_x86_ops->set_dr7(vcpu, dr7);
762 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
763}
764
338dbc97 765static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 766{
767 switch (dr) {
768 case 0 ... 3:
769 vcpu->arch.db[dr] = val;
770 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
771 vcpu->arch.eff_db[dr] = val;
772 break;
773 case 4:
338dbc97
GN		 774 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
775 return 1; /* #UD */
020df079
GN		 776 /* fall through */
777 case 6:
338dbc97
GN		 778 if (val & 0xffffffff00000000ULL)
779 return -1; /* #GP */
020df079 780 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
73aaf249 781 kvm_update_dr6(vcpu);
020df079
GN		 782 break;
783 case 5:
338dbc97
GN		 784 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
785 return 1; /* #UD */
020df079
GN		 786 /* fall through */
787 default: /* 7 */
338dbc97
GN		 788 if (val & 0xffffffff00000000ULL)
789 return -1; /* #GP */
020df079 790 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 791 kvm_update_dr7(vcpu);
020df079
GN		 792 break;
793 }
794
795 return 0;
796}
338dbc97
GN		 797
798int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
799{
800 int res;
801
802 res = __kvm_set_dr(vcpu, dr, val);
803 if (res > 0)
804 kvm_queue_exception(vcpu, UD_VECTOR);
805 else if (res < 0)
806 kvm_inject_gp(vcpu, 0);
807
808 return res;
809}
020df079
GN		 810EXPORT_SYMBOL_GPL(kvm_set_dr);
811
338dbc97 812static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 813{
814 switch (dr) {
815 case 0 ... 3:
816 *val = vcpu->arch.db[dr];
817 break;
818 case 4:
338dbc97 819 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 820 return 1;
020df079
GN		 821 /* fall through */
822 case 6:
73aaf249
JK		 823 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
824 *val = vcpu->arch.dr6;
825 else
826 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 827 break;
828 case 5:
338dbc97 829 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 830 return 1;
020df079
GN		 831 /* fall through */
832 default: /* 7 */
833 *val = vcpu->arch.dr7;
834 break;
835 }
836
837 return 0;
838}
338dbc97
GN		 839
840int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
841{
842 if (_kvm_get_dr(vcpu, dr, val)) {
843 kvm_queue_exception(vcpu, UD_VECTOR);
844 return 1;
845 }
846 return 0;
847}
020df079
GN		 848EXPORT_SYMBOL_GPL(kvm_get_dr);
849
022cd0e8
AK		 850bool kvm_rdpmc(struct kvm_vcpu *vcpu)
851{
852 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
853 u64 data;
854 int err;
855
856 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
857 if (err)
858 return err;
859 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
860 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
861 return err;
862}
863EXPORT_SYMBOL_GPL(kvm_rdpmc);
864
043405e1
CO		 865/*
866 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
867 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
868 *
869 * This list is modified at module load time to reflect the
e3267cbb
GC		 870 * capabilities of the host cpu. This capabilities test skips MSRs that are
871 * kvm-specific. Those are put in the beginning of the list.
043405e1 872 */
e3267cbb 873
e984097b 874#define KVM_SAVE_MSRS_BEGIN 12
043405e1 875static u32 msrs_to_save[] = {
e3267cbb 876 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 877 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 878 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 879 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 880 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 881 MSR_KVM_PV_EOI_EN,
043405e1 882 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 883 MSR_STAR,
043405e1
CO		 884#ifdef CONFIG_X86_64
885 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
886#endif
b3897a49 887 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 888 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 889};
890
891static unsigned num_msrs_to_save;
892
f1d24831 893static const u32 emulated_msrs[] = {
ba904635 894 MSR_IA32_TSC_ADJUST,
a3e06bbe 895 MSR_IA32_TSCDEADLINE,
043405e1 896 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 897 MSR_IA32_MCG_STATUS,
898 MSR_IA32_MCG_CTL,
043405e1
CO		 899};
900
384bb783 901bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 902{
b69e8cae 903 if (efer & efer_reserved_bits)
384bb783 904 return false;
15c4a640 905
1b2fd70c
AG		 906 if (efer & EFER_FFXSR) {
907 struct kvm_cpuid_entry2 *feat;
908
909 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 910 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 911 return false;
1b2fd70c
AG		 912 }
913
d8017474
AG		 914 if (efer & EFER_SVME) {
915 struct kvm_cpuid_entry2 *feat;
916
917 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 918 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 919 return false;
d8017474
AG		 920 }
921
384bb783
JK		 922 return true;
923}
924EXPORT_SYMBOL_GPL(kvm_valid_efer);
925
926static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
927{
928 u64 old_efer = vcpu->arch.efer;
929
930 if (!kvm_valid_efer(vcpu, efer))
931 return 1;
932
933 if (is_paging(vcpu)
934 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
935 return 1;
936
15c4a640 937 efer &= ~EFER_LMA;
f6801dff 938 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 939
a3d204e2
SY		 940 kvm_x86_ops->set_efer(vcpu, efer);
941
aad82703
SY		 942 /* Update reserved bits */
943 if ((efer ^ old_efer) & EFER_NX)
944 kvm_mmu_reset_context(vcpu);
945
b69e8cae 946 return 0;
15c4a640
CO		 947}
948
f2b4b7dd
JR		 949void kvm_enable_efer_bits(u64 mask)
950{
951 efer_reserved_bits &= ~mask;
952}
953EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
954
955
15c4a640
CO		 956/*
957 * Writes msr value into into the appropriate "register".
958 * Returns 0 on success, non-0 otherwise.
959 * Assumes vcpu_load() was already called.
960 */
8fe8ab46 961int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 962{
8fe8ab46 963 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 964}
965
313a3dc7
CO		 966/*
967 * Adapt set_msr() to msr_io()'s calling convention
968 */
969static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
970{
8fe8ab46
WA		 971 struct msr_data msr;
972
973 msr.data = *data;
974 msr.index = index;
975 msr.host_initiated = true;
976 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 977}
978
16e8d74d
MT		 979#ifdef CONFIG_X86_64
980struct pvclock_gtod_data {
981 seqcount_t seq;
982
983 struct { /* extract of a clocksource struct */
984 int vclock_mode;
985 cycle_t cycle_last;
986 cycle_t mask;
987 u32 mult;
988 u32 shift;
989 } clock;
990
991 /* open coded 'struct timespec' */
992 u64 monotonic_time_snsec;
993 time_t monotonic_time_sec;
994};
995
996static struct pvclock_gtod_data pvclock_gtod_data;
997
998static void update_pvclock_gtod(struct timekeeper *tk)
999{
1000 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1001
1002 write_seqcount_begin(&vdata->seq);
1003
1004 /* copy pvclock gtod data */
1005 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
1006 vdata->clock.cycle_last = tk->clock->cycle_last;
1007 vdata->clock.mask = tk->clock->mask;
1008 vdata->clock.mult = tk->mult;
1009 vdata->clock.shift = tk->shift;
1010
1011 vdata->monotonic_time_sec = tk->xtime_sec
1012 + tk->wall_to_monotonic.tv_sec;
1013 vdata->monotonic_time_snsec = tk->xtime_nsec
1014 + (tk->wall_to_monotonic.tv_nsec
1015 << tk->shift);
1016 while (vdata->monotonic_time_snsec >=
1017 (((u64)NSEC_PER_SEC) << tk->shift)) {
1018 vdata->monotonic_time_snsec -=
1019 ((u64)NSEC_PER_SEC) << tk->shift;
1020 vdata->monotonic_time_sec++;
1021 }
1022
1023 write_seqcount_end(&vdata->seq);
1024}
1025#endif
1026
1027
18068523
GOC		 1028static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1029{
9ed3c444
AK		 1030 int version;
1031 int r;
50d0a0f9 1032 struct pvclock_wall_clock wc;
923de3cf 1033 struct timespec boot;
18068523
GOC		 1034
1035 if (!wall_clock)
1036 return;
1037
9ed3c444
AK		 1038 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1039 if (r)
1040 return;
1041
1042 if (version & 1)
1043 ++version; /* first time write, random junk */
1044
1045 ++version;
18068523 1046
18068523
GOC		 1047 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1048
50d0a0f9
GH		 1049 /*
1050 * The guest calculates current wall clock time by adding
34c238a1 1051 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1052 * wall clock specified here. guest system time equals host
1053 * system time for us, thus we must fill in host boot time here.
1054 */
923de3cf 1055 getboottime(&boot);
50d0a0f9 1056
4b648665
BR		 1057 if (kvm->arch.kvmclock_offset) {
1058 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1059 boot = timespec_sub(boot, ts);
1060 }
50d0a0f9
GH		 1061 wc.sec = boot.tv_sec;
1062 wc.nsec = boot.tv_nsec;
1063 wc.version = version;
18068523
GOC		 1064
1065 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1066
1067 version++;
1068 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1069}
1070
50d0a0f9
GH		 1071static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1072{
1073 uint32_t quotient, remainder;
1074
1075 /* Don't try to replace with do_div(), this one calculates
1076 * "(dividend << 32) / divisor" */
1077 __asm__ ( "divl %4"
1078 : "=a" (quotient), "=d" (remainder)
1079 : "0" (0), "1" (dividend), "r" (divisor) );
1080 return quotient;
1081}
1082
5f4e3f88
ZA		 1083static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1084 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1085{
5f4e3f88 1086 uint64_t scaled64;
50d0a0f9
GH		 1087 int32_t shift = 0;
1088 uint64_t tps64;
1089 uint32_t tps32;
1090
5f4e3f88
ZA		 1091 tps64 = base_khz * 1000LL;
1092 scaled64 = scaled_khz * 1000LL;
50933623 1093 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1094 tps64 >>= 1;
1095 shift--;
1096 }
1097
1098 tps32 = (uint32_t)tps64;
50933623
JK		 1099 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1100 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1101 scaled64 >>= 1;
1102 else
1103 tps32 <<= 1;
50d0a0f9
GH		 1104 shift++;
1105 }
1106
5f4e3f88
ZA		 1107 *pshift = shift;
1108 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1109
5f4e3f88
ZA		 1110 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1111 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1112}
1113
759379dd
ZA		 1114static inline u64 get_kernel_ns(void)
1115{
1116 struct timespec ts;
1117
1118 WARN_ON(preemptible());
1119 ktime_get_ts(&ts);
1120 monotonic_to_bootbased(&ts);
1121 return timespec_to_ns(&ts);
50d0a0f9
GH		 1122}
1123
d828199e 1124#ifdef CONFIG_X86_64
16e8d74d 1125static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1126#endif
16e8d74d 1127
c8076604 1128static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1129unsigned long max_tsc_khz;
c8076604 1130
cc578287 1131static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1132{
cc578287
ZA		 1133 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1134 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1135}
1136
cc578287 1137static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1138{
cc578287
ZA		 1139 u64 v = (u64)khz * (1000000 + ppm);
1140 do_div(v, 1000000);
1141 return v;
1e993611
JR		 1142}
1143
cc578287 1144static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1145{
cc578287
ZA		 1146 u32 thresh_lo, thresh_hi;
1147 int use_scaling = 0;
217fc9cf 1148
03ba32ca
MT		 1149 /* tsc_khz can be zero if TSC calibration fails */
1150 if (this_tsc_khz == 0)
1151 return;
1152
c285545f
ZA		 1153 /* Compute a scale to convert nanoseconds in TSC cycles */
1154 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1155 &vcpu->arch.virtual_tsc_shift,
1156 &vcpu->arch.virtual_tsc_mult);
1157 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1158
1159 /*
1160 * Compute the variation in TSC rate which is acceptable
1161 * within the range of tolerance and decide if the
1162 * rate being applied is within that bounds of the hardware
1163 * rate. If so, no scaling or compensation need be done.
1164 */
1165 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1166 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1167 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1168 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1169 use_scaling = 1;
1170 }
1171 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1172}
1173
1174static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1175{
e26101b1 1176 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1177 vcpu->arch.virtual_tsc_mult,
1178 vcpu->arch.virtual_tsc_shift);
e26101b1 1179 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1180 return tsc;
1181}
1182
b48aa97e
MT		 1183void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1184{
1185#ifdef CONFIG_X86_64
1186 bool vcpus_matched;
1187 bool do_request = false;
1188 struct kvm_arch *ka = &vcpu->kvm->arch;
1189 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1190
1191 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1192 atomic_read(&vcpu->kvm->online_vcpus));
1193
1194 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1195 if (!ka->use_master_clock)
1196 do_request = 1;
1197
1198 if (!vcpus_matched && ka->use_master_clock)
1199 do_request = 1;
1200
1201 if (do_request)
1202 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1203
1204 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1205 atomic_read(&vcpu->kvm->online_vcpus),
1206 ka->use_master_clock, gtod->clock.vclock_mode);
1207#endif
1208}
1209
ba904635
WA		 1210static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1211{
1212 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1213 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1214}
1215
8fe8ab46 1216void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1217{
1218 struct kvm *kvm = vcpu->kvm;
f38e098f 1219 u64 offset, ns, elapsed;
99e3e30a 1220 unsigned long flags;
02626b6a 1221 s64 usdiff;
b48aa97e 1222 bool matched;
8fe8ab46 1223 u64 data = msr->data;
99e3e30a 1224
038f8c11 1225 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1226 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1227 ns = get_kernel_ns();
f38e098f 1228 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1229
03ba32ca 1230 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1231 int faulted = 0;
1232
03ba32ca
MT		 1233 /* n.b - signed multiplication and division required */
1234 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1235#ifdef CONFIG_X86_64
03ba32ca 1236 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1237#else
03ba32ca 1238 /* do_div() only does unsigned */
8915aa27
MT		 1239 asm("1: idivl %[divisor]\n"
1240 "2: xor %%edx, %%edx\n"
1241 " movl $0, %[faulted]\n"
1242 "3:\n"
1243 ".section .fixup,\"ax\"\n"
1244 "4: movl $1, %[faulted]\n"
1245 " jmp 3b\n"
1246 ".previous\n"
1247
1248 _ASM_EXTABLE(1b, 4b)
1249
1250 : "=A"(usdiff), [faulted] "=r" (faulted)
1251 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1252
5d3cb0f6 1253#endif
03ba32ca
MT		 1254 do_div(elapsed, 1000);
1255 usdiff -= elapsed;
1256 if (usdiff < 0)
1257 usdiff = -usdiff;
8915aa27
MT		 1258
1259 /* idivl overflow => difference is larger than USEC_PER_SEC */
1260 if (faulted)
1261 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1262 } else
1263 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1264
1265 /*
5d3cb0f6
ZA		 1266 * Special case: TSC write with a small delta (1 second) of virtual
1267 * cycle time against real time is interpreted as an attempt to
1268 * synchronize the CPU.
1269 *
1270 * For a reliable TSC, we can match TSC offsets, and for an unstable
1271 * TSC, we add elapsed time in this computation. We could let the
1272 * compensation code attempt to catch up if we fall behind, but
1273 * it's better to try to match offsets from the beginning.
1274 */
02626b6a 1275 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1276 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1277 if (!check_tsc_unstable()) {
e26101b1 1278 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1279 pr_debug("kvm: matched tsc offset for %llu\n", data);
1280 } else {
857e4099 1281 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1282 data += delta;
1283 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1284 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1285 }
b48aa97e 1286 matched = true;
e26101b1
ZA		 1287 } else {
1288 /*
1289 * We split periods of matched TSC writes into generations.
1290 * For each generation, we track the original measured
1291 * nanosecond time, offset, and write, so if TSCs are in
1292 * sync, we can match exact offset, and if not, we can match
4a969980 1293 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1294 *
1295 * These values are tracked in kvm->arch.cur_xxx variables.
1296 */
1297 kvm->arch.cur_tsc_generation++;
1298 kvm->arch.cur_tsc_nsec = ns;
1299 kvm->arch.cur_tsc_write = data;
1300 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1301 matched = false;
e26101b1
ZA		 1302 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1303 kvm->arch.cur_tsc_generation, data);
f38e098f 1304 }
e26101b1
ZA		 1305
1306 /*
1307 * We also track th most recent recorded KHZ, write and time to
1308 * allow the matching interval to be extended at each write.
1309 */
f38e098f
ZA		 1310 kvm->arch.last_tsc_nsec = ns;
1311 kvm->arch.last_tsc_write = data;
5d3cb0f6 1312 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1313
b183aa58 1314 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1315
1316 /* Keep track of which generation this VCPU has synchronized to */
1317 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1318 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1319 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1320
ba904635
WA		 1321 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1322 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1323 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1324 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1325
1326 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1327 if (matched)
1328 kvm->arch.nr_vcpus_matched_tsc++;
1329 else
1330 kvm->arch.nr_vcpus_matched_tsc = 0;
1331
1332 kvm_track_tsc_matching(vcpu);
1333 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1334}
e26101b1 1335
99e3e30a
ZA		 1336EXPORT_SYMBOL_GPL(kvm_write_tsc);
1337
d828199e
MT		 1338#ifdef CONFIG_X86_64
1339
1340static cycle_t read_tsc(void)
1341{
1342 cycle_t ret;
1343 u64 last;
1344
1345 /*
1346 * Empirically, a fence (of type that depends on the CPU)
1347 * before rdtsc is enough to ensure that rdtsc is ordered
1348 * with respect to loads. The various CPU manuals are unclear
1349 * as to whether rdtsc can be reordered with later loads,
1350 * but no one has ever seen it happen.
1351 */
1352 rdtsc_barrier();
1353 ret = (cycle_t)vget_cycles();
1354
1355 last = pvclock_gtod_data.clock.cycle_last;
1356
1357 if (likely(ret >= last))
1358 return ret;
1359
1360 /*
1361 * GCC likes to generate cmov here, but this branch is extremely
1362 * predictable (it's just a funciton of time and the likely is
1363 * very likely) and there's a data dependence, so force GCC
1364 * to generate a branch instead. I don't barrier() because
1365 * we don't actually need a barrier, and if this function
1366 * ever gets inlined it will generate worse code.
1367 */
1368 asm volatile ("");
1369 return last;
1370}
1371
1372static inline u64 vgettsc(cycle_t *cycle_now)
1373{
1374 long v;
1375 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1376
1377 *cycle_now = read_tsc();
1378
1379 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1380 return v * gtod->clock.mult;
1381}
1382
1383static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1384{
1385 unsigned long seq;
1386 u64 ns;
1387 int mode;
1388 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1389
1390 ts->tv_nsec = 0;
1391 do {
1392 seq = read_seqcount_begin(&gtod->seq);
1393 mode = gtod->clock.vclock_mode;
1394 ts->tv_sec = gtod->monotonic_time_sec;
1395 ns = gtod->monotonic_time_snsec;
1396 ns += vgettsc(cycle_now);
1397 ns >>= gtod->clock.shift;
1398 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1399 timespec_add_ns(ts, ns);
1400
1401 return mode;
1402}
1403
1404/* returns true if host is using tsc clocksource */
1405static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1406{
1407 struct timespec ts;
1408
1409 /* checked again under seqlock below */
1410 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1411 return false;
1412
1413 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1414 return false;
1415
1416 monotonic_to_bootbased(&ts);
1417 *kernel_ns = timespec_to_ns(&ts);
1418
1419 return true;
1420}
1421#endif
1422
1423/*
1424 *
b48aa97e
MT		 1425 * Assuming a stable TSC across physical CPUS, and a stable TSC
1426 * across virtual CPUs, the following condition is possible.
1427 * Each numbered line represents an event visible to both
d828199e
MT		 1428 * CPUs at the next numbered event.
1429 *
1430 * "timespecX" represents host monotonic time. "tscX" represents
1431 * RDTSC value.
1432 *
1433 * VCPU0 on CPU0 | VCPU1 on CPU1
1434 *
1435 * 1. read timespec0,tsc0
1436 * 2. | timespec1 = timespec0 + N
1437 * | tsc1 = tsc0 + M
1438 * 3. transition to guest | transition to guest
1439 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1440 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1441 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1442 *
1443 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1444 *
1445 * - ret0 < ret1
1446 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1447 * ...
1448 * - 0 < N - M => M < N
1449 *
1450 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1451 * always the case (the difference between two distinct xtime instances
1452 * might be smaller then the difference between corresponding TSC reads,
1453 * when updating guest vcpus pvclock areas).
1454 *
1455 * To avoid that problem, do not allow visibility of distinct
1456 * system_timestamp/tsc_timestamp values simultaneously: use a master
1457 * copy of host monotonic time values. Update that master copy
1458 * in lockstep.
1459 *
b48aa97e 1460 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1461 *
1462 */
1463
1464static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1465{
1466#ifdef CONFIG_X86_64
1467 struct kvm_arch *ka = &kvm->arch;
1468 int vclock_mode;
b48aa97e
MT		 1469 bool host_tsc_clocksource, vcpus_matched;
1470
1471 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1472 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1473
1474 /*
1475 * If the host uses TSC clock, then passthrough TSC as stable
1476 * to the guest.
1477 */
b48aa97e 1478 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1479 &ka->master_kernel_ns,
1480 &ka->master_cycle_now);
1481
b48aa97e
MT		 1482 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1483
d828199e
MT		 1484 if (ka->use_master_clock)
1485 atomic_set(&kvm_guest_has_master_clock, 1);
1486
1487 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1488 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1489 vcpus_matched);
d828199e
MT		 1490#endif
1491}
1492
2e762ff7
MT		 1493static void kvm_gen_update_masterclock(struct kvm *kvm)
1494{
1495#ifdef CONFIG_X86_64
1496 int i;
1497 struct kvm_vcpu *vcpu;
1498 struct kvm_arch *ka = &kvm->arch;
1499
1500 spin_lock(&ka->pvclock_gtod_sync_lock);
1501 kvm_make_mclock_inprogress_request(kvm);
1502 /* no guest entries from this point */
1503 pvclock_update_vm_gtod_copy(kvm);
1504
1505 kvm_for_each_vcpu(i, vcpu, kvm)
1506 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1507
1508 /* guest entries allowed */
1509 kvm_for_each_vcpu(i, vcpu, kvm)
1510 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1511
1512 spin_unlock(&ka->pvclock_gtod_sync_lock);
1513#endif
1514}
1515
34c238a1 1516static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1517{
d828199e 1518 unsigned long flags, this_tsc_khz;
18068523 1519 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1520 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1521 s64 kernel_ns;
d828199e 1522 u64 tsc_timestamp, host_tsc;
0b79459b 1523 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1524 u8 pvclock_flags;
d828199e
MT		 1525 bool use_master_clock;
1526
1527 kernel_ns = 0;
1528 host_tsc = 0;
18068523 1529
d828199e
MT		 1530 /*
1531 * If the host uses TSC clock, then passthrough TSC as stable
1532 * to the guest.
1533 */
1534 spin_lock(&ka->pvclock_gtod_sync_lock);
1535 use_master_clock = ka->use_master_clock;
1536 if (use_master_clock) {
1537 host_tsc = ka->master_cycle_now;
1538 kernel_ns = ka->master_kernel_ns;
1539 }
1540 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1541
1542 /* Keep irq disabled to prevent changes to the clock */
1543 local_irq_save(flags);
1544 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1545 if (unlikely(this_tsc_khz == 0)) {
1546 local_irq_restore(flags);
1547 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1548 return 1;
1549 }
d828199e
MT		 1550 if (!use_master_clock) {
1551 host_tsc = native_read_tsc();
1552 kernel_ns = get_kernel_ns();
1553 }
1554
1555 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1556
c285545f
ZA		 1557 /*
1558 * We may have to catch up the TSC to match elapsed wall clock
1559 * time for two reasons, even if kvmclock is used.
1560 * 1) CPU could have been running below the maximum TSC rate
1561 * 2) Broken TSC compensation resets the base at each VCPU
1562 * entry to avoid unknown leaps of TSC even when running
1563 * again on the same CPU. This may cause apparent elapsed
1564 * time to disappear, and the guest to stand still or run
1565 * very slowly.
1566 */
1567 if (vcpu->tsc_catchup) {
1568 u64 tsc = compute_guest_tsc(v, kernel_ns);
1569 if (tsc > tsc_timestamp) {
f1e2b260 1570 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1571 tsc_timestamp = tsc;
1572 }
50d0a0f9
GH		 1573 }
1574
18068523
GOC		 1575 local_irq_restore(flags);
1576
0b79459b 1577 if (!vcpu->pv_time_enabled)
c285545f 1578 return 0;
18068523 1579
e48672fa 1580 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1581 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1582 &vcpu->hv_clock.tsc_shift,
1583 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1584 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1585 }
1586
1587 /* With all the info we got, fill in the values */
1d5f066e 1588 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1589 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1590 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1591
18068523
GOC		 1592 /*
1593 * The interface expects us to write an even number signaling that the
1594 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1595 * state, we just increase by 2 at the end.
18068523 1596 */
50d0a0f9 1597 vcpu->hv_clock.version += 2;
18068523 1598
0b79459b
AH		 1599 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1600 &guest_hv_clock, sizeof(guest_hv_clock))))
1601 return 0;
78c0337a
MT		 1602
1603 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1604 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1605
1606 if (vcpu->pvclock_set_guest_stopped_request) {
1607 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1608 vcpu->pvclock_set_guest_stopped_request = false;
1609 }
1610
d828199e
MT		 1611 /* If the host uses TSC clocksource, then it is stable */
1612 if (use_master_clock)
1613 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1614
78c0337a
MT		 1615 vcpu->hv_clock.flags = pvclock_flags;
1616
0b79459b
AH		 1617 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1618 &vcpu->hv_clock,
1619 sizeof(vcpu->hv_clock));
8cfdc000 1620 return 0;
c8076604
GH		 1621}
1622
0061d53d
MT		 1623/*
1624 * kvmclock updates which are isolated to a given vcpu, such as
1625 * vcpu->cpu migration, should not allow system_timestamp from
1626 * the rest of the vcpus to remain static. Otherwise ntp frequency
1627 * correction applies to one vcpu's system_timestamp but not
1628 * the others.
1629 *
1630 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1631 * We need to rate-limit these requests though, as they can
1632 * considerably slow guests that have a large number of vcpus.
1633 * The time for a remote vcpu to update its kvmclock is bound
1634 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1635 */
1636
7e44e449
AJ		 1637#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1638
1639static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1640{
1641 int i;
7e44e449
AJ		 1642 struct delayed_work *dwork = to_delayed_work(work);
1643 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1644 kvmclock_update_work);
1645 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1646 struct kvm_vcpu *vcpu;
1647
1648 kvm_for_each_vcpu(i, vcpu, kvm) {
1649 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1650 kvm_vcpu_kick(vcpu);
1651 }
1652}
1653
7e44e449
AJ		 1654static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1655{
1656 struct kvm *kvm = v->kvm;
1657
1658 set_bit(KVM_REQ_CLOCK_UPDATE, &v->requests);
1659 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1660 KVMCLOCK_UPDATE_DELAY);
1661}
1662
332967a3
AJ		 1663#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1664
1665static void kvmclock_sync_fn(struct work_struct *work)
1666{
1667 struct delayed_work *dwork = to_delayed_work(work);
1668 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1669 kvmclock_sync_work);
1670 struct kvm *kvm = container_of(ka, struct kvm, arch);
1671
1672 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1673 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1674 KVMCLOCK_SYNC_PERIOD);
1675}
1676
9ba075a6
AK		 1677static bool msr_mtrr_valid(unsigned msr)
1678{
1679 switch (msr) {
1680 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1681 case MSR_MTRRfix64K_00000:
1682 case MSR_MTRRfix16K_80000:
1683 case MSR_MTRRfix16K_A0000:
1684 case MSR_MTRRfix4K_C0000:
1685 case MSR_MTRRfix4K_C8000:
1686 case MSR_MTRRfix4K_D0000:
1687 case MSR_MTRRfix4K_D8000:
1688 case MSR_MTRRfix4K_E0000:
1689 case MSR_MTRRfix4K_E8000:
1690 case MSR_MTRRfix4K_F0000:
1691 case MSR_MTRRfix4K_F8000:
1692 case MSR_MTRRdefType:
1693 case MSR_IA32_CR_PAT:
1694 return true;
1695 case 0x2f8:
1696 return true;
1697 }
1698 return false;
1699}
1700
d6289b93
MT		 1701static bool valid_pat_type(unsigned t)
1702{
1703 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1704}
1705
1706static bool valid_mtrr_type(unsigned t)
1707{
1708 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1709}
1710
1711static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1712{
1713 int i;
1714
1715 if (!msr_mtrr_valid(msr))
1716 return false;
1717
1718 if (msr == MSR_IA32_CR_PAT) {
1719 for (i = 0; i < 8; i++)
1720 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1721 return false;
1722 return true;
1723 } else if (msr == MSR_MTRRdefType) {
1724 if (data & ~0xcff)
1725 return false;
1726 return valid_mtrr_type(data & 0xff);
1727 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1728 for (i = 0; i < 8 ; i++)
1729 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1730 return false;
1731 return true;
1732 }
1733
1734 /* variable MTRRs */
1735 return valid_mtrr_type(data & 0xff);
1736}
1737
9ba075a6
AK		 1738static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1739{
0bed3b56
SY		 1740 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1741
d6289b93 1742 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1743 return 1;
1744
0bed3b56
SY		 1745 if (msr == MSR_MTRRdefType) {
1746 vcpu->arch.mtrr_state.def_type = data;
1747 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1748 } else if (msr == MSR_MTRRfix64K_00000)
1749 p[0] = data;
1750 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1751 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1752 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1753 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1754 else if (msr == MSR_IA32_CR_PAT)
1755 vcpu->arch.pat = data;
1756 else { /* Variable MTRRs */
1757 int idx, is_mtrr_mask;
1758 u64 *pt;
1759
1760 idx = (msr - 0x200) / 2;
1761 is_mtrr_mask = msr - 0x200 - 2 * idx;
1762 if (!is_mtrr_mask)
1763 pt =
1764 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1765 else
1766 pt =
1767 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1768 *pt = data;
1769 }
1770
1771 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1772 return 0;
1773}
15c4a640 1774
890ca9ae 1775static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1776{
890ca9ae
HY		 1777 u64 mcg_cap = vcpu->arch.mcg_cap;
1778 unsigned bank_num = mcg_cap & 0xff;
1779
15c4a640 1780 switch (msr) {
15c4a640 1781 case MSR_IA32_MCG_STATUS:
890ca9ae 1782 vcpu->arch.mcg_status = data;
15c4a640 1783 break;
c7ac679c 1784 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1785 if (!(mcg_cap & MCG_CTL_P))
1786 return 1;
1787 if (data != 0 && data != ~(u64)0)
1788 return -1;
1789 vcpu->arch.mcg_ctl = data;
1790 break;
1791 default:
1792 if (msr >= MSR_IA32_MC0_CTL &&
1793 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1794 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1795 /* only 0 or all 1s can be written to IA32_MCi_CTL
1796 * some Linux kernels though clear bit 10 in bank 4 to
1797 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1798 * this to avoid an uncatched #GP in the guest
1799 */
890ca9ae 1800 if ((offset & 0x3) == 0 &&
114be429 1801 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1802 return -1;
1803 vcpu->arch.mce_banks[offset] = data;
1804 break;
1805 }
1806 return 1;
1807 }
1808 return 0;
1809}
1810
ffde22ac
ES		 1811static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1812{
1813 struct kvm *kvm = vcpu->kvm;
1814 int lm = is_long_mode(vcpu);
1815 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1816 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1817 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1818 : kvm->arch.xen_hvm_config.blob_size_32;
1819 u32 page_num = data & ~PAGE_MASK;
1820 u64 page_addr = data & PAGE_MASK;
1821 u8 *page;
1822 int r;
1823
1824 r = -E2BIG;
1825 if (page_num >= blob_size)
1826 goto out;
1827 r = -ENOMEM;
ff5c2c03
SL		 1828 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1829 if (IS_ERR(page)) {
1830 r = PTR_ERR(page);
ffde22ac 1831 goto out;
ff5c2c03 1832 }
ffde22ac
ES		 1833 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1834 goto out_free;
1835 r = 0;
1836out_free:
1837 kfree(page);
1838out:
1839 return r;
1840}
1841
55cd8e5a
GN		 1842static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1843{
1844 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1845}
1846
1847static bool kvm_hv_msr_partition_wide(u32 msr)
1848{
1849 bool r = false;
1850 switch (msr) {
1851 case HV_X64_MSR_GUEST_OS_ID:
1852 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1853 case HV_X64_MSR_REFERENCE_TSC:
1854 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1855 r = true;
1856 break;
1857 }
1858
1859 return r;
1860}
1861
1862static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1863{
1864 struct kvm *kvm = vcpu->kvm;
1865
1866 switch (msr) {
1867 case HV_X64_MSR_GUEST_OS_ID:
1868 kvm->arch.hv_guest_os_id = data;
1869 /* setting guest os id to zero disables hypercall page */
1870 if (!kvm->arch.hv_guest_os_id)
1871 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1872 break;
1873 case HV_X64_MSR_HYPERCALL: {
1874 u64 gfn;
1875 unsigned long addr;
1876 u8 instructions[4];
1877
1878 /* if guest os id is not set hypercall should remain disabled */
1879 if (!kvm->arch.hv_guest_os_id)
1880 break;
1881 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1882 kvm->arch.hv_hypercall = data;
1883 break;
1884 }
1885 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1886 addr = gfn_to_hva(kvm, gfn);
1887 if (kvm_is_error_hva(addr))
1888 return 1;
1889 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1890 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1891 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1892 return 1;
1893 kvm->arch.hv_hypercall = data;
b94b64c9 1894 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 1895 break;
1896 }
e984097b
VR		 1897 case HV_X64_MSR_REFERENCE_TSC: {
1898 u64 gfn;
1899 HV_REFERENCE_TSC_PAGE tsc_ref;
1900 memset(&tsc_ref, 0, sizeof(tsc_ref));
1901 kvm->arch.hv_tsc_page = data;
1902 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1903 break;
1904 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1905 if (kvm_write_guest(kvm, data,
1906 &tsc_ref, sizeof(tsc_ref)))
1907 return 1;
1908 mark_page_dirty(kvm, gfn);
1909 break;
1910 }
55cd8e5a 1911 default:
a737f256
CD		 1912 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1913 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1914 return 1;
1915 }
1916 return 0;
1917}
1918
1919static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1920{
10388a07
GN		 1921 switch (msr) {
1922 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 1923 u64 gfn;
10388a07 1924 unsigned long addr;
55cd8e5a 1925
10388a07
GN		 1926 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1927 vcpu->arch.hv_vapic = data;
1928 break;
1929 }
b3af1e88
VR		 1930 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1931 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 1932 if (kvm_is_error_hva(addr))
1933 return 1;
8b0cedff 1934 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1935 return 1;
1936 vcpu->arch.hv_vapic = data;
b3af1e88 1937 mark_page_dirty(vcpu->kvm, gfn);
10388a07
GN		 1938 break;
1939 }
1940 case HV_X64_MSR_EOI:
1941 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1942 case HV_X64_MSR_ICR:
1943 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1944 case HV_X64_MSR_TPR:
1945 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1946 default:
a737f256
CD		 1947 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1948 "data 0x%llx\n", msr, data);
10388a07
GN		 1949 return 1;
1950 }
1951
1952 return 0;
55cd8e5a
GN		 1953}
1954
344d9588
GN		 1955static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1956{
1957 gpa_t gpa = data & ~0x3f;
1958
4a969980 1959 /* Bits 2:5 are reserved, Should be zero */
6adba527 1960 if (data & 0x3c)
344d9588
GN		 1961 return 1;
1962
1963 vcpu->arch.apf.msr_val = data;
1964
1965 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1966 kvm_clear_async_pf_completion_queue(vcpu);
1967 kvm_async_pf_hash_reset(vcpu);
1968 return 0;
1969 }
1970
8f964525
AH		 1971 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1972 sizeof(u32)))
344d9588
GN		 1973 return 1;
1974
6adba527 1975 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1976 kvm_async_pf_wakeup_all(vcpu);
1977 return 0;
1978}
1979
12f9a48f
GC		 1980static void kvmclock_reset(struct kvm_vcpu *vcpu)
1981{
0b79459b 1982 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1983}
1984
c9aaa895
GC		 1985static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1986{
1987 u64 delta;
1988
1989 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1990 return;
1991
1992 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1993 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1994 vcpu->arch.st.accum_steal = delta;
1995}
1996
1997static void record_steal_time(struct kvm_vcpu *vcpu)
1998{
1999 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2000 return;
2001
2002 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2003 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2004 return;
2005
2006 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2007 vcpu->arch.st.steal.version += 2;
2008 vcpu->arch.st.accum_steal = 0;
2009
2010 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2011 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2012}
2013
8fe8ab46 2014int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2015{
5753785f 2016 bool pr = false;
8fe8ab46
WA		 2017 u32 msr = msr_info->index;
2018 u64 data = msr_info->data;
5753785f 2019
15c4a640 2020 switch (msr) {
2e32b719
BP		 2021 case MSR_AMD64_NB_CFG:
2022 case MSR_IA32_UCODE_REV:
2023 case MSR_IA32_UCODE_WRITE:
2024 case MSR_VM_HSAVE_PA:
2025 case MSR_AMD64_PATCH_LOADER:
2026 case MSR_AMD64_BU_CFG2:
2027 break;
2028
15c4a640 2029 case MSR_EFER:
b69e8cae 2030 return set_efer(vcpu, data);
8f1589d9
AP		 2031 case MSR_K7_HWCR:
2032 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2033 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2034 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 2035 if (data != 0) {
a737f256
CD		 2036 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2037 data);
8f1589d9
AP		 2038 return 1;
2039 }
15c4a640 2040 break;
f7c6d140
AP		 2041 case MSR_FAM10H_MMIO_CONF_BASE:
2042 if (data != 0) {
a737f256
CD		 2043 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2044 "0x%llx\n", data);
f7c6d140
AP		 2045 return 1;
2046 }
15c4a640 2047 break;
b5e2fec0
AG		 2048 case MSR_IA32_DEBUGCTLMSR:
2049 if (!data) {
2050 /* We support the non-activated case already */
2051 break;
2052 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2053 /* Values other than LBR and BTF are vendor-specific,
2054 thus reserved and should throw a #GP */
2055 return 1;
2056 }
a737f256
CD		 2057 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2058 __func__, data);
b5e2fec0 2059 break;
9ba075a6
AK		 2060 case 0x200 ... 0x2ff:
2061 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2062 case MSR_IA32_APICBASE:
58cb628d 2063 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2064 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2065 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2066 case MSR_IA32_TSCDEADLINE:
2067 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2068 break;
ba904635
WA		 2069 case MSR_IA32_TSC_ADJUST:
2070 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2071 if (!msr_info->host_initiated) {
2072 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2073 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2074 }
2075 vcpu->arch.ia32_tsc_adjust_msr = data;
2076 }
2077 break;
15c4a640 2078 case MSR_IA32_MISC_ENABLE:
ad312c7c 2079 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2080 break;
11c6bffa 2081 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2082 case MSR_KVM_WALL_CLOCK:
2083 vcpu->kvm->arch.wall_clock = data;
2084 kvm_write_wall_clock(vcpu->kvm, data);
2085 break;
11c6bffa 2086 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2087 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2088 u64 gpa_offset;
12f9a48f 2089 kvmclock_reset(vcpu);
18068523
GOC		 2090
2091 vcpu->arch.time = data;
0061d53d 2092 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2093
2094 /* we verify if the enable bit is set... */
2095 if (!(data & 1))
2096 break;
2097
0b79459b 2098 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2099
0b79459b 2100 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2101 &vcpu->arch.pv_time, data & ~1ULL,
2102 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2103 vcpu->arch.pv_time_enabled = false;
2104 else
2105 vcpu->arch.pv_time_enabled = true;
32cad84f 2106
18068523
GOC		 2107 break;
2108 }
344d9588
GN		 2109 case MSR_KVM_ASYNC_PF_EN:
2110 if (kvm_pv_enable_async_pf(vcpu, data))
2111 return 1;
2112 break;
c9aaa895
GC		 2113 case MSR_KVM_STEAL_TIME:
2114
2115 if (unlikely(!sched_info_on()))
2116 return 1;
2117
2118 if (data & KVM_STEAL_RESERVED_MASK)
2119 return 1;
2120
2121 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2122 data & KVM_STEAL_VALID_BITS,
2123 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2124 return 1;
2125
2126 vcpu->arch.st.msr_val = data;
2127
2128 if (!(data & KVM_MSR_ENABLED))
2129 break;
2130
2131 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2132
2133 preempt_disable();
2134 accumulate_steal_time(vcpu);
2135 preempt_enable();
2136
2137 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2138
2139 break;
ae7a2a3f
MT		 2140 case MSR_KVM_PV_EOI_EN:
2141 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2142 return 1;
2143 break;
c9aaa895 2144
890ca9ae
HY		 2145 case MSR_IA32_MCG_CTL:
2146 case MSR_IA32_MCG_STATUS:
2147 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2148 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2149
2150 /* Performance counters are not protected by a CPUID bit,
2151 * so we should check all of them in the generic path for the sake of
2152 * cross vendor migration.
2153 * Writing a zero into the event select MSRs disables them,
2154 * which we perfectly emulate ;-). Any other value should be at least
2155 * reported, some guests depend on them.
2156 */
71db6023
AP		 2157 case MSR_K7_EVNTSEL0:
2158 case MSR_K7_EVNTSEL1:
2159 case MSR_K7_EVNTSEL2:
2160 case MSR_K7_EVNTSEL3:
2161 if (data != 0)
a737f256
CD		 2162 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2163 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2164 break;
2165 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2166 * so we ignore writes to make it happy.
2167 */
71db6023
AP		 2168 case MSR_K7_PERFCTR0:
2169 case MSR_K7_PERFCTR1:
2170 case MSR_K7_PERFCTR2:
2171 case MSR_K7_PERFCTR3:
a737f256
CD		 2172 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2173 "0x%x data 0x%llx\n", msr, data);
71db6023 2174 break;
5753785f
GN		 2175 case MSR_P6_PERFCTR0:
2176 case MSR_P6_PERFCTR1:
2177 pr = true;
2178 case MSR_P6_EVNTSEL0:
2179 case MSR_P6_EVNTSEL1:
2180 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2181 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2182
2183 if (pr || data != 0)
a737f256
CD		 2184 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2185 "0x%x data 0x%llx\n", msr, data);
5753785f 2186 break;
84e0cefa
JS		 2187 case MSR_K7_CLK_CTL:
2188 /*
2189 * Ignore all writes to this no longer documented MSR.
2190 * Writes are only relevant for old K7 processors,
2191 * all pre-dating SVM, but a recommended workaround from
4a969980 2192 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2193 * affected processor models on the command line, hence
2194 * the need to ignore the workaround.
2195 */
2196 break;
55cd8e5a
GN		 2197 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2198 if (kvm_hv_msr_partition_wide(msr)) {
2199 int r;
2200 mutex_lock(&vcpu->kvm->lock);
2201 r = set_msr_hyperv_pw(vcpu, msr, data);
2202 mutex_unlock(&vcpu->kvm->lock);
2203 return r;
2204 } else
2205 return set_msr_hyperv(vcpu, msr, data);
2206 break;
91c9c3ed 2207 case MSR_IA32_BBL_CR_CTL3:
2208 /* Drop writes to this legacy MSR -- see rdmsr
2209 * counterpart for further detail.
2210 */
a737f256 2211 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2212 break;
2b036c6b
BO		 2213 case MSR_AMD64_OSVW_ID_LENGTH:
2214 if (!guest_cpuid_has_osvw(vcpu))
2215 return 1;
2216 vcpu->arch.osvw.length = data;
2217 break;
2218 case MSR_AMD64_OSVW_STATUS:
2219 if (!guest_cpuid_has_osvw(vcpu))
2220 return 1;
2221 vcpu->arch.osvw.status = data;
2222 break;
15c4a640 2223 default:
ffde22ac
ES		 2224 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2225 return xen_hvm_config(vcpu, data);
f5132b01 2226 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2227 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2228 if (!ignore_msrs) {
a737f256
CD		 2229 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2230 msr, data);
ed85c068
AP		 2231 return 1;
2232 } else {
a737f256
CD		 2233 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2234 msr, data);
ed85c068
AP		 2235 break;
2236 }
15c4a640
CO		 2237 }
2238 return 0;
2239}
2240EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2241
2242
2243/*
2244 * Reads an msr value (of 'msr_index') into 'pdata'.
2245 * Returns 0 on success, non-0 otherwise.
2246 * Assumes vcpu_load() was already called.
2247 */
2248int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2249{
2250 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2251}
2252
9ba075a6
AK		 2253static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2254{
0bed3b56
SY		 2255 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2256
9ba075a6
AK		 2257 if (!msr_mtrr_valid(msr))
2258 return 1;
2259
0bed3b56
SY		 2260 if (msr == MSR_MTRRdefType)
2261 *pdata = vcpu->arch.mtrr_state.def_type +
2262 (vcpu->arch.mtrr_state.enabled << 10);
2263 else if (msr == MSR_MTRRfix64K_00000)
2264 *pdata = p[0];
2265 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2266 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2267 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2268 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2269 else if (msr == MSR_IA32_CR_PAT)
2270 *pdata = vcpu->arch.pat;
2271 else { /* Variable MTRRs */
2272 int idx, is_mtrr_mask;
2273 u64 *pt;
2274
2275 idx = (msr - 0x200) / 2;
2276 is_mtrr_mask = msr - 0x200 - 2 * idx;
2277 if (!is_mtrr_mask)
2278 pt =
2279 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2280 else
2281 pt =
2282 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2283 *pdata = *pt;
2284 }
2285
9ba075a6
AK		 2286 return 0;
2287}
2288
890ca9ae 2289static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2290{
2291 u64 data;
890ca9ae
HY		 2292 u64 mcg_cap = vcpu->arch.mcg_cap;
2293 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2294
2295 switch (msr) {
15c4a640
CO		 2296 case MSR_IA32_P5_MC_ADDR:
2297 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2298 data = 0;
2299 break;
15c4a640 2300 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2301 data = vcpu->arch.mcg_cap;
2302 break;
c7ac679c 2303 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2304 if (!(mcg_cap & MCG_CTL_P))
2305 return 1;
2306 data = vcpu->arch.mcg_ctl;
2307 break;
2308 case MSR_IA32_MCG_STATUS:
2309 data = vcpu->arch.mcg_status;
2310 break;
2311 default:
2312 if (msr >= MSR_IA32_MC0_CTL &&
2313 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2314 u32 offset = msr - MSR_IA32_MC0_CTL;
2315 data = vcpu->arch.mce_banks[offset];
2316 break;
2317 }
2318 return 1;
2319 }
2320 *pdata = data;
2321 return 0;
2322}
2323
55cd8e5a
GN		 2324static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2325{
2326 u64 data = 0;
2327 struct kvm *kvm = vcpu->kvm;
2328
2329 switch (msr) {
2330 case HV_X64_MSR_GUEST_OS_ID:
2331 data = kvm->arch.hv_guest_os_id;
2332 break;
2333 case HV_X64_MSR_HYPERCALL:
2334 data = kvm->arch.hv_hypercall;
2335 break;
e984097b
VR		 2336 case HV_X64_MSR_TIME_REF_COUNT: {
2337 data =
2338 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2339 break;
2340 }
2341 case HV_X64_MSR_REFERENCE_TSC:
2342 data = kvm->arch.hv_tsc_page;
2343 break;
55cd8e5a 2344 default:
a737f256 2345 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2346 return 1;
2347 }
2348
2349 *pdata = data;
2350 return 0;
2351}
2352
2353static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2354{
2355 u64 data = 0;
2356
2357 switch (msr) {
2358 case HV_X64_MSR_VP_INDEX: {
2359 int r;
2360 struct kvm_vcpu *v;
684851a1
TY		 2361 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2362 if (v == vcpu) {
55cd8e5a 2363 data = r;
684851a1
TY		 2364 break;
2365 }
2366 }
55cd8e5a
GN		 2367 break;
2368 }
10388a07
GN		 2369 case HV_X64_MSR_EOI:
2370 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2371 case HV_X64_MSR_ICR:
2372 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2373 case HV_X64_MSR_TPR:
2374 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2375 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2376 data = vcpu->arch.hv_vapic;
2377 break;
55cd8e5a 2378 default:
a737f256 2379 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2380 return 1;
2381 }
2382 *pdata = data;
2383 return 0;
2384}
2385
890ca9ae
HY		 2386int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2387{
2388 u64 data;
2389
2390 switch (msr) {
890ca9ae 2391 case MSR_IA32_PLATFORM_ID:
15c4a640 2392 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2393 case MSR_IA32_DEBUGCTLMSR:
2394 case MSR_IA32_LASTBRANCHFROMIP:
2395 case MSR_IA32_LASTBRANCHTOIP:
2396 case MSR_IA32_LASTINTFROMIP:
2397 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2398 case MSR_K8_SYSCFG:
2399 case MSR_K7_HWCR:
61a6bd67 2400 case MSR_VM_HSAVE_PA:
9e699624 2401 case MSR_K7_EVNTSEL0:
1f3ee616 2402 case MSR_K7_PERFCTR0:
1fdbd48c 2403 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2404 case MSR_AMD64_NB_CFG:
f7c6d140 2405 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2406 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2407 data = 0;
2408 break;
5753785f
GN		 2409 case MSR_P6_PERFCTR0:
2410 case MSR_P6_PERFCTR1:
2411 case MSR_P6_EVNTSEL0:
2412 case MSR_P6_EVNTSEL1:
2413 if (kvm_pmu_msr(vcpu, msr))
2414 return kvm_pmu_get_msr(vcpu, msr, pdata);
2415 data = 0;
2416 break;
742bc670
MT		 2417 case MSR_IA32_UCODE_REV:
2418 data = 0x100000000ULL;
2419 break;
9ba075a6
AK		 2420 case MSR_MTRRcap:
2421 data = 0x500 | KVM_NR_VAR_MTRR;
2422 break;
2423 case 0x200 ... 0x2ff:
2424 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2425 case 0xcd: /* fsb frequency */
2426 data = 3;
2427 break;
7b914098
JS		 2428 /*
2429 * MSR_EBC_FREQUENCY_ID
2430 * Conservative value valid for even the basic CPU models.
2431 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2432 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2433 * and 266MHz for model 3, or 4. Set Core Clock
2434 * Frequency to System Bus Frequency Ratio to 1 (bits
2435 * 31:24) even though these are only valid for CPU
2436 * models > 2, however guests may end up dividing or
2437 * multiplying by zero otherwise.
2438 */
2439 case MSR_EBC_FREQUENCY_ID:
2440 data = 1 << 24;
2441 break;
15c4a640
CO		 2442 case MSR_IA32_APICBASE:
2443 data = kvm_get_apic_base(vcpu);
2444 break;
0105d1a5
GN		 2445 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2446 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2447 break;
a3e06bbe
LJ		 2448 case MSR_IA32_TSCDEADLINE:
2449 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2450 break;
ba904635
WA		 2451 case MSR_IA32_TSC_ADJUST:
2452 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2453 break;
15c4a640 2454 case MSR_IA32_MISC_ENABLE:
ad312c7c 2455 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2456 break;
847f0ad8
AG		 2457 case MSR_IA32_PERF_STATUS:
2458 /* TSC increment by tick */
2459 data = 1000ULL;
2460 /* CPU multiplier */
2461 data |= (((uint64_t)4ULL) << 40);
2462 break;
15c4a640 2463 case MSR_EFER:
f6801dff 2464 data = vcpu->arch.efer;
15c4a640 2465 break;
18068523 2466 case MSR_KVM_WALL_CLOCK:
11c6bffa 2467 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2468 data = vcpu->kvm->arch.wall_clock;
2469 break;
2470 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2471 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2472 data = vcpu->arch.time;
2473 break;
344d9588
GN		 2474 case MSR_KVM_ASYNC_PF_EN:
2475 data = vcpu->arch.apf.msr_val;
2476 break;
c9aaa895
GC		 2477 case MSR_KVM_STEAL_TIME:
2478 data = vcpu->arch.st.msr_val;
2479 break;
1d92128f
MT		 2480 case MSR_KVM_PV_EOI_EN:
2481 data = vcpu->arch.pv_eoi.msr_val;
2482 break;
890ca9ae
HY		 2483 case MSR_IA32_P5_MC_ADDR:
2484 case MSR_IA32_P5_MC_TYPE:
2485 case MSR_IA32_MCG_CAP:
2486 case MSR_IA32_MCG_CTL:
2487 case MSR_IA32_MCG_STATUS:
2488 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2489 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2490 case MSR_K7_CLK_CTL:
2491 /*
2492 * Provide expected ramp-up count for K7. All other
2493 * are set to zero, indicating minimum divisors for
2494 * every field.
2495 *
2496 * This prevents guest kernels on AMD host with CPU
2497 * type 6, model 8 and higher from exploding due to
2498 * the rdmsr failing.
2499 */
2500 data = 0x20000000;
2501 break;
55cd8e5a
GN		 2502 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2503 if (kvm_hv_msr_partition_wide(msr)) {
2504 int r;
2505 mutex_lock(&vcpu->kvm->lock);
2506 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2507 mutex_unlock(&vcpu->kvm->lock);
2508 return r;
2509 } else
2510 return get_msr_hyperv(vcpu, msr, pdata);
2511 break;
91c9c3ed 2512 case MSR_IA32_BBL_CR_CTL3:
2513 /* This legacy MSR exists but isn't fully documented in current
2514 * silicon. It is however accessed by winxp in very narrow
2515 * scenarios where it sets bit #19, itself documented as
2516 * a "reserved" bit. Best effort attempt to source coherent
2517 * read data here should the balance of the register be
2518 * interpreted by the guest:
2519 *
2520 * L2 cache control register 3: 64GB range, 256KB size,
2521 * enabled, latency 0x1, configured
2522 */
2523 data = 0xbe702111;
2524 break;
2b036c6b
BO		 2525 case MSR_AMD64_OSVW_ID_LENGTH:
2526 if (!guest_cpuid_has_osvw(vcpu))
2527 return 1;
2528 data = vcpu->arch.osvw.length;
2529 break;
2530 case MSR_AMD64_OSVW_STATUS:
2531 if (!guest_cpuid_has_osvw(vcpu))
2532 return 1;
2533 data = vcpu->arch.osvw.status;
2534 break;
15c4a640 2535 default:
f5132b01
GN		 2536 if (kvm_pmu_msr(vcpu, msr))
2537 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2538 if (!ignore_msrs) {
a737f256 2539 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2540 return 1;
2541 } else {
a737f256 2542 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2543 data = 0;
2544 }
2545 break;
15c4a640
CO		 2546 }
2547 *pdata = data;
2548 return 0;
2549}
2550EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2551
313a3dc7
CO		 2552/*
2553 * Read or write a bunch of msrs. All parameters are kernel addresses.
2554 *
2555 * @return number of msrs set successfully.
2556 */
2557static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2558 struct kvm_msr_entry *entries,
2559 int (*do_msr)(struct kvm_vcpu *vcpu,
2560 unsigned index, u64 *data))
2561{
f656ce01 2562 int i, idx;
313a3dc7 2563
f656ce01 2564 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2565 for (i = 0; i < msrs->nmsrs; ++i)
2566 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2567 break;
f656ce01 2568 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2569
313a3dc7
CO		 2570 return i;
2571}
2572
2573/*
2574 * Read or write a bunch of msrs. Parameters are user addresses.
2575 *
2576 * @return number of msrs set successfully.
2577 */
2578static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2579 int (*do_msr)(struct kvm_vcpu *vcpu,
2580 unsigned index, u64 *data),
2581 int writeback)
2582{
2583 struct kvm_msrs msrs;
2584 struct kvm_msr_entry *entries;
2585 int r, n;
2586 unsigned size;
2587
2588 r = -EFAULT;
2589 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2590 goto out;
2591
2592 r = -E2BIG;
2593 if (msrs.nmsrs >= MAX_IO_MSRS)
2594 goto out;
2595
313a3dc7 2596 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2597 entries = memdup_user(user_msrs->entries, size);
2598 if (IS_ERR(entries)) {
2599 r = PTR_ERR(entries);
313a3dc7 2600 goto out;
ff5c2c03 2601 }
313a3dc7
CO		 2602
2603 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2604 if (r < 0)
2605 goto out_free;
2606
2607 r = -EFAULT;
2608 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2609 goto out_free;
2610
2611 r = n;
2612
2613out_free:
7a73c028 2614 kfree(entries);
313a3dc7
CO		 2615out:
2616 return r;
2617}
2618
018d00d2
ZX		 2619int kvm_dev_ioctl_check_extension(long ext)
2620{
2621 int r;
2622
2623 switch (ext) {
2624 case KVM_CAP_IRQCHIP:
2625 case KVM_CAP_HLT:
2626 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2627 case KVM_CAP_SET_TSS_ADDR:
07716717 2628 case KVM_CAP_EXT_CPUID:
9c15bb1d 2629 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2630 case KVM_CAP_CLOCKSOURCE:
7837699f 2631 case KVM_CAP_PIT:
a28e4f5a 2632 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2633 case KVM_CAP_MP_STATE:
ed848624 2634 case KVM_CAP_SYNC_MMU:
a355c85c 2635 case KVM_CAP_USER_NMI:
52d939a0 2636 case KVM_CAP_REINJECT_CONTROL:
4925663a 2637 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2638 case KVM_CAP_IRQFD:
d34e6b17 2639 case KVM_CAP_IOEVENTFD:
c5ff41ce 2640 case KVM_CAP_PIT2:
e9f42757 2641 case KVM_CAP_PIT_STATE2:
b927a3ce 2642 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2643 case KVM_CAP_XEN_HVM:
afbcf7ab 2644 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2645 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2646 case KVM_CAP_HYPERV:
10388a07 2647 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2648 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2649 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2650 case KVM_CAP_DEBUGREGS:
d2be1651 2651 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2652 case KVM_CAP_XSAVE:
344d9588 2653 case KVM_CAP_ASYNC_PF:
92a1f12d 2654 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2655 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2656 case KVM_CAP_READONLY_MEM:
5f66b620 2657 case KVM_CAP_HYPERV_TIME:
2a5bab10
AW		 2658#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2659 case KVM_CAP_ASSIGN_DEV_IRQ:
2660 case KVM_CAP_PCI_2_3:
2661#endif
018d00d2
ZX		 2662 r = 1;
2663 break;
542472b5
LV		 2664 case KVM_CAP_COALESCED_MMIO:
2665 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2666 break;
774ead3a
AK		 2667 case KVM_CAP_VAPIC:
2668 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2669 break;
f725230a 2670 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2671 r = KVM_SOFT_MAX_VCPUS;
2672 break;
2673 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2674 r = KVM_MAX_VCPUS;
2675 break;
a988b910 2676 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2677 r = KVM_USER_MEM_SLOTS;
a988b910 2678 break;
a68a6a72
MT		 2679 case KVM_CAP_PV_MMU: /* obsolete */
2680 r = 0;
2f333bcb 2681 break;
4cee4b72 2682#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2683 case KVM_CAP_IOMMU:
a1b60c1c 2684 r = iommu_present(&pci_bus_type);
62c476c7 2685 break;
4cee4b72 2686#endif
890ca9ae
HY		 2687 case KVM_CAP_MCE:
2688 r = KVM_MAX_MCE_BANKS;
2689 break;
2d5b5a66
SY		 2690 case KVM_CAP_XCRS:
2691 r = cpu_has_xsave;
2692 break;
92a1f12d
JR		 2693 case KVM_CAP_TSC_CONTROL:
2694 r = kvm_has_tsc_control;
2695 break;
4d25a066
JK		 2696 case KVM_CAP_TSC_DEADLINE_TIMER:
2697 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2698 break;
018d00d2
ZX		 2699 default:
2700 r = 0;
2701 break;
2702 }
2703 return r;
2704
2705}
2706
043405e1
CO		 2707long kvm_arch_dev_ioctl(struct file *filp,
2708 unsigned int ioctl, unsigned long arg)
2709{
2710 void __user *argp = (void __user *)arg;
2711 long r;
2712
2713 switch (ioctl) {
2714 case KVM_GET_MSR_INDEX_LIST: {
2715 struct kvm_msr_list __user *user_msr_list = argp;
2716 struct kvm_msr_list msr_list;
2717 unsigned n;
2718
2719 r = -EFAULT;
2720 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2721 goto out;
2722 n = msr_list.nmsrs;
2723 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2724 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2725 goto out;
2726 r = -E2BIG;
e125e7b6 2727 if (n < msr_list.nmsrs)
043405e1
CO		 2728 goto out;
2729 r = -EFAULT;
2730 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2731 num_msrs_to_save * sizeof(u32)))
2732 goto out;
e125e7b6 2733 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2734 &emulated_msrs,
2735 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2736 goto out;
2737 r = 0;
2738 break;
2739 }
9c15bb1d
BP		 2740 case KVM_GET_SUPPORTED_CPUID:
2741 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2742 struct kvm_cpuid2 __user *cpuid_arg = argp;
2743 struct kvm_cpuid2 cpuid;
2744
2745 r = -EFAULT;
2746 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2747 goto out;
9c15bb1d
BP		 2748
2749 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2750 ioctl);
674eea0f
AK		 2751 if (r)
2752 goto out;
2753
2754 r = -EFAULT;
2755 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2756 goto out;
2757 r = 0;
2758 break;
2759 }
890ca9ae
HY		 2760 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2761 u64 mce_cap;
2762
2763 mce_cap = KVM_MCE_CAP_SUPPORTED;
2764 r = -EFAULT;
2765 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2766 goto out;
2767 r = 0;
2768 break;
2769 }
043405e1
CO		 2770 default:
2771 r = -EINVAL;
2772 }
2773out:
2774 return r;
2775}
2776
f5f48ee1
SY		 2777static void wbinvd_ipi(void *garbage)
2778{
2779 wbinvd();
2780}
2781
2782static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2783{
e0f0bbc5 2784 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2785}
2786
313a3dc7
CO		 2787void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2788{
f5f48ee1
SY		 2789 /* Address WBINVD may be executed by guest */
2790 if (need_emulate_wbinvd(vcpu)) {
2791 if (kvm_x86_ops->has_wbinvd_exit())
2792 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2793 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2794 smp_call_function_single(vcpu->cpu,
2795 wbinvd_ipi, NULL, 1);
2796 }
2797
313a3dc7 2798 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2799
0dd6a6ed
ZA		 2800 /* Apply any externally detected TSC adjustments (due to suspend) */
2801 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2802 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2803 vcpu->arch.tsc_offset_adjustment = 0;
2804 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2805 }
8f6055cb 2806
48434c20 2807 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2808 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2809 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2810 if (tsc_delta < 0)
2811 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2812 if (check_tsc_unstable()) {
b183aa58
ZA		 2813 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2814 vcpu->arch.last_guest_tsc);
2815 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2816 vcpu->arch.tsc_catchup = 1;
c285545f 2817 }
d98d07ca
MT		 2818 /*
2819 * On a host with synchronized TSC, there is no need to update
2820 * kvmclock on vcpu->cpu migration
2821 */
2822 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2823 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2824 if (vcpu->cpu != cpu)
2825 kvm_migrate_timers(vcpu);
e48672fa 2826 vcpu->cpu = cpu;
6b7d7e76 2827 }
c9aaa895
GC		 2828
2829 accumulate_steal_time(vcpu);
2830 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2831}
2832
2833void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2834{
02daab21 2835 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2836 kvm_put_guest_fpu(vcpu);
6f526ec5 2837 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2838}
2839
313a3dc7
CO		 2840static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2841 struct kvm_lapic_state *s)
2842{
5a71785d 2843 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2844 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2845
2846 return 0;
2847}
2848
2849static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2850 struct kvm_lapic_state *s)
2851{
64eb0620 2852 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2853 update_cr8_intercept(vcpu);
313a3dc7
CO		 2854
2855 return 0;
2856}
2857
f77bc6a4
ZX		 2858static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2859 struct kvm_interrupt *irq)
2860{
02cdb50f 2861 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2862 return -EINVAL;
2863 if (irqchip_in_kernel(vcpu->kvm))
2864 return -ENXIO;
f77bc6a4 2865
66fd3f7f 2866 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2867 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2868
f77bc6a4
ZX		 2869 return 0;
2870}
2871
c4abb7c9
JK		 2872static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2873{
c4abb7c9 2874 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2875
2876 return 0;
2877}
2878
b209749f
AK		 2879static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2880 struct kvm_tpr_access_ctl *tac)
2881{
2882 if (tac->flags)
2883 return -EINVAL;
2884 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2885 return 0;
2886}
2887
890ca9ae
HY		 2888static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2889 u64 mcg_cap)
2890{
2891 int r;
2892 unsigned bank_num = mcg_cap & 0xff, bank;
2893
2894 r = -EINVAL;
a9e38c3e 2895 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2896 goto out;
2897 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2898 goto out;
2899 r = 0;
2900 vcpu->arch.mcg_cap = mcg_cap;
2901 /* Init IA32_MCG_CTL to all 1s */
2902 if (mcg_cap & MCG_CTL_P)
2903 vcpu->arch.mcg_ctl = ~(u64)0;
2904 /* Init IA32_MCi_CTL to all 1s */
2905 for (bank = 0; bank < bank_num; bank++)
2906 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2907out:
2908 return r;
2909}
2910
2911static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2912 struct kvm_x86_mce *mce)
2913{
2914 u64 mcg_cap = vcpu->arch.mcg_cap;
2915 unsigned bank_num = mcg_cap & 0xff;
2916 u64 *banks = vcpu->arch.mce_banks;
2917
2918 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2919 return -EINVAL;
2920 /*
2921 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2922 * reporting is disabled
2923 */
2924 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2925 vcpu->arch.mcg_ctl != ~(u64)0)
2926 return 0;
2927 banks += 4 * mce->bank;
2928 /*
2929 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2930 * reporting is disabled for the bank
2931 */
2932 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2933 return 0;
2934 if (mce->status & MCI_STATUS_UC) {
2935 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2936 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2937 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2938 return 0;
2939 }
2940 if (banks[1] & MCI_STATUS_VAL)
2941 mce->status |= MCI_STATUS_OVER;
2942 banks[2] = mce->addr;
2943 banks[3] = mce->misc;
2944 vcpu->arch.mcg_status = mce->mcg_status;
2945 banks[1] = mce->status;
2946 kvm_queue_exception(vcpu, MC_VECTOR);
2947 } else if (!(banks[1] & MCI_STATUS_VAL)
2948 || !(banks[1] & MCI_STATUS_UC)) {
2949 if (banks[1] & MCI_STATUS_VAL)
2950 mce->status |= MCI_STATUS_OVER;
2951 banks[2] = mce->addr;
2952 banks[3] = mce->misc;
2953 banks[1] = mce->status;
2954 } else
2955 banks[1] |= MCI_STATUS_OVER;
2956 return 0;
2957}
2958
3cfc3092
JK		 2959static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2960 struct kvm_vcpu_events *events)
2961{
7460fb4a 2962 process_nmi(vcpu);
03b82a30
JK		 2963 events->exception.injected =
2964 vcpu->arch.exception.pending &&
2965 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2966 events->exception.nr = vcpu->arch.exception.nr;
2967 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2968 events->exception.pad = 0;
3cfc3092
JK		 2969 events->exception.error_code = vcpu->arch.exception.error_code;
2970
03b82a30
JK		 2971 events->interrupt.injected =
2972 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2973 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2974 events->interrupt.soft = 0;
48005f64
JK		 2975 events->interrupt.shadow =
2976 kvm_x86_ops->get_interrupt_shadow(vcpu,
2977 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2978
2979 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2980 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2981 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2982 events->nmi.pad = 0;
3cfc3092 2983
66450a21 2984 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2985
dab4b911 2986 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2987 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2988 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2989}
2990
2991static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2992 struct kvm_vcpu_events *events)
2993{
dab4b911 2994 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2995 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2996 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2997 return -EINVAL;
2998
7460fb4a 2999 process_nmi(vcpu);
3cfc3092
JK		 3000 vcpu->arch.exception.pending = events->exception.injected;
3001 vcpu->arch.exception.nr = events->exception.nr;
3002 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3003 vcpu->arch.exception.error_code = events->exception.error_code;
3004
3005 vcpu->arch.interrupt.pending = events->interrupt.injected;
3006 vcpu->arch.interrupt.nr = events->interrupt.nr;
3007 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3008 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3009 kvm_x86_ops->set_interrupt_shadow(vcpu,
3010 events->interrupt.shadow);
3cfc3092
JK		 3011
3012 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3013 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3014 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3015 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3016
66450a21
JK		 3017 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3018 kvm_vcpu_has_lapic(vcpu))
3019 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3020
3842d135
AK		 3021 kvm_make_request(KVM_REQ_EVENT, vcpu);
3022
3cfc3092
JK		 3023 return 0;
3024}
3025
a1efbe77
JK		 3026static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3027 struct kvm_debugregs *dbgregs)
3028{
73aaf249
JK		 3029 unsigned long val;
3030
a1efbe77 3031 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
73aaf249
JK		 3032 _kvm_get_dr(vcpu, 6, &val);
3033 dbgregs->dr6 = val;
a1efbe77
JK		 3034 dbgregs->dr7 = vcpu->arch.dr7;
3035 dbgregs->flags = 0;
97e69aa6 3036 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3037}
3038
3039static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3040 struct kvm_debugregs *dbgregs)
3041{
3042 if (dbgregs->flags)
3043 return -EINVAL;
3044
a1efbe77
JK		 3045 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3046 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3047 kvm_update_dr6(vcpu);
a1efbe77 3048 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3049 kvm_update_dr7(vcpu);
a1efbe77 3050
a1efbe77
JK		 3051 return 0;
3052}
3053
2d5b5a66
SY		 3054static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3055 struct kvm_xsave *guest_xsave)
3056{
4344ee98 3057 if (cpu_has_xsave) {
2d5b5a66
SY		 3058 memcpy(guest_xsave->region,
3059 &vcpu->arch.guest_fpu.state->xsave,
4344ee98
PB		 3060 vcpu->arch.guest_xstate_size);
3061 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3062 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3063 } else {
2d5b5a66
SY		 3064 memcpy(guest_xsave->region,
3065 &vcpu->arch.guest_fpu.state->fxsave,
3066 sizeof(struct i387_fxsave_struct));
3067 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3068 XSTATE_FPSSE;
3069 }
3070}
3071
3072static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3073 struct kvm_xsave *guest_xsave)
3074{
3075 u64 xstate_bv =
3076 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3077
d7876f1b
PB		 3078 if (cpu_has_xsave) {
3079 /*
3080 * Here we allow setting states that are not present in
3081 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3082 * with old userspace.
3083 */
3084 if (xstate_bv & ~KVM_SUPPORTED_XCR0)
3085 return -EINVAL;
3086 if (xstate_bv & ~host_xcr0)
3087 return -EINVAL;
2d5b5a66 3088 memcpy(&vcpu->arch.guest_fpu.state->xsave,
4344ee98 3089 guest_xsave->region, vcpu->arch.guest_xstate_size);
d7876f1b 3090 } else {
2d5b5a66
SY		 3091 if (xstate_bv & ~XSTATE_FPSSE)
3092 return -EINVAL;
3093 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3094 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3095 }
3096 return 0;
3097}
3098
3099static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3100 struct kvm_xcrs *guest_xcrs)
3101{
3102 if (!cpu_has_xsave) {
3103 guest_xcrs->nr_xcrs = 0;
3104 return;
3105 }
3106
3107 guest_xcrs->nr_xcrs = 1;
3108 guest_xcrs->flags = 0;
3109 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3110 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3111}
3112
3113static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3114 struct kvm_xcrs *guest_xcrs)
3115{
3116 int i, r = 0;
3117
3118 if (!cpu_has_xsave)
3119 return -EINVAL;
3120
3121 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3122 return -EINVAL;
3123
3124 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3125 /* Only support XCR0 currently */
c67a04cb 3126 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3127 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3128 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3129 break;
3130 }
3131 if (r)
3132 r = -EINVAL;
3133 return r;
3134}
3135
1c0b28c2
EM		 3136/*
3137 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3138 * stopped by the hypervisor. This function will be called from the host only.
3139 * EINVAL is returned when the host attempts to set the flag for a guest that
3140 * does not support pv clocks.
3141 */
3142static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3143{
0b79459b 3144 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3145 return -EINVAL;
51d59c6b 3146 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3147 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3148 return 0;
3149}
3150
313a3dc7
CO		 3151long kvm_arch_vcpu_ioctl(struct file *filp,
3152 unsigned int ioctl, unsigned long arg)
3153{
3154 struct kvm_vcpu *vcpu = filp->private_data;
3155 void __user *argp = (void __user *)arg;
3156 int r;
d1ac91d8
AK		 3157 union {
3158 struct kvm_lapic_state *lapic;
3159 struct kvm_xsave *xsave;
3160 struct kvm_xcrs *xcrs;
3161 void *buffer;
3162 } u;
3163
3164 u.buffer = NULL;
313a3dc7
CO		 3165 switch (ioctl) {
3166 case KVM_GET_LAPIC: {
2204ae3c
MT		 3167 r = -EINVAL;
3168 if (!vcpu->arch.apic)
3169 goto out;
d1ac91d8 3170 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3171
b772ff36 3172 r = -ENOMEM;
d1ac91d8 3173 if (!u.lapic)
b772ff36 3174 goto out;
d1ac91d8 3175 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3176 if (r)
3177 goto out;
3178 r = -EFAULT;
d1ac91d8 3179 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3180 goto out;
3181 r = 0;
3182 break;
3183 }
3184 case KVM_SET_LAPIC: {
2204ae3c
MT		 3185 r = -EINVAL;
3186 if (!vcpu->arch.apic)
3187 goto out;
ff5c2c03 3188 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3189 if (IS_ERR(u.lapic))
3190 return PTR_ERR(u.lapic);
ff5c2c03 3191
d1ac91d8 3192 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3193 break;
3194 }
f77bc6a4
ZX		 3195 case KVM_INTERRUPT: {
3196 struct kvm_interrupt irq;
3197
3198 r = -EFAULT;
3199 if (copy_from_user(&irq, argp, sizeof irq))
3200 goto out;
3201 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3202 break;
3203 }
c4abb7c9
JK		 3204 case KVM_NMI: {
3205 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3206 break;
3207 }
313a3dc7
CO		 3208 case KVM_SET_CPUID: {
3209 struct kvm_cpuid __user *cpuid_arg = argp;
3210 struct kvm_cpuid cpuid;
3211
3212 r = -EFAULT;
3213 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3214 goto out;
3215 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3216 break;
3217 }
07716717
DK		 3218 case KVM_SET_CPUID2: {
3219 struct kvm_cpuid2 __user *cpuid_arg = argp;
3220 struct kvm_cpuid2 cpuid;
3221
3222 r = -EFAULT;
3223 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3224 goto out;
3225 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3226 cpuid_arg->entries);
07716717
DK		 3227 break;
3228 }
3229 case KVM_GET_CPUID2: {
3230 struct kvm_cpuid2 __user *cpuid_arg = argp;
3231 struct kvm_cpuid2 cpuid;
3232
3233 r = -EFAULT;
3234 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3235 goto out;
3236 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3237 cpuid_arg->entries);
07716717
DK		 3238 if (r)
3239 goto out;
3240 r = -EFAULT;
3241 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3242 goto out;
3243 r = 0;
3244 break;
3245 }
313a3dc7
CO		 3246 case KVM_GET_MSRS:
3247 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3248 break;
3249 case KVM_SET_MSRS:
3250 r = msr_io(vcpu, argp, do_set_msr, 0);
3251 break;
b209749f
AK		 3252 case KVM_TPR_ACCESS_REPORTING: {
3253 struct kvm_tpr_access_ctl tac;
3254
3255 r = -EFAULT;
3256 if (copy_from_user(&tac, argp, sizeof tac))
3257 goto out;
3258 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3259 if (r)
3260 goto out;
3261 r = -EFAULT;
3262 if (copy_to_user(argp, &tac, sizeof tac))
3263 goto out;
3264 r = 0;
3265 break;
3266 };
b93463aa
AK		 3267 case KVM_SET_VAPIC_ADDR: {
3268 struct kvm_vapic_addr va;
3269
3270 r = -EINVAL;
3271 if (!irqchip_in_kernel(vcpu->kvm))
3272 goto out;
3273 r = -EFAULT;
3274 if (copy_from_user(&va, argp, sizeof va))
3275 goto out;
fda4e2e8 3276 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3277 break;
3278 }
890ca9ae
HY		 3279 case KVM_X86_SETUP_MCE: {
3280 u64 mcg_cap;
3281
3282 r = -EFAULT;
3283 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3284 goto out;
3285 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3286 break;
3287 }
3288 case KVM_X86_SET_MCE: {
3289 struct kvm_x86_mce mce;
3290
3291 r = -EFAULT;
3292 if (copy_from_user(&mce, argp, sizeof mce))
3293 goto out;
3294 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3295 break;
3296 }
3cfc3092
JK		 3297 case KVM_GET_VCPU_EVENTS: {
3298 struct kvm_vcpu_events events;
3299
3300 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3301
3302 r = -EFAULT;
3303 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3304 break;
3305 r = 0;
3306 break;
3307 }
3308 case KVM_SET_VCPU_EVENTS: {
3309 struct kvm_vcpu_events events;
3310
3311 r = -EFAULT;
3312 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3313 break;
3314
3315 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3316 break;
3317 }
a1efbe77
JK		 3318 case KVM_GET_DEBUGREGS: {
3319 struct kvm_debugregs dbgregs;
3320
3321 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3322
3323 r = -EFAULT;
3324 if (copy_to_user(argp, &dbgregs,
3325 sizeof(struct kvm_debugregs)))
3326 break;
3327 r = 0;
3328 break;
3329 }
3330 case KVM_SET_DEBUGREGS: {
3331 struct kvm_debugregs dbgregs;
3332
3333 r = -EFAULT;
3334 if (copy_from_user(&dbgregs, argp,
3335 sizeof(struct kvm_debugregs)))
3336 break;
3337
3338 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3339 break;
3340 }
2d5b5a66 3341 case KVM_GET_XSAVE: {
d1ac91d8 3342 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3343 r = -ENOMEM;
d1ac91d8 3344 if (!u.xsave)
2d5b5a66
SY		 3345 break;
3346
d1ac91d8 3347 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3348
3349 r = -EFAULT;
d1ac91d8 3350 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3351 break;
3352 r = 0;
3353 break;
3354 }
3355 case KVM_SET_XSAVE: {
ff5c2c03 3356 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3357 if (IS_ERR(u.xsave))
3358 return PTR_ERR(u.xsave);
2d5b5a66 3359
d1ac91d8 3360 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3361 break;
3362 }
3363 case KVM_GET_XCRS: {
d1ac91d8 3364 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3365 r = -ENOMEM;
d1ac91d8 3366 if (!u.xcrs)
2d5b5a66
SY		 3367 break;
3368
d1ac91d8 3369 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3370
3371 r = -EFAULT;
d1ac91d8 3372 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3373 sizeof(struct kvm_xcrs)))
3374 break;
3375 r = 0;
3376 break;
3377 }
3378 case KVM_SET_XCRS: {
ff5c2c03 3379 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3380 if (IS_ERR(u.xcrs))
3381 return PTR_ERR(u.xcrs);
2d5b5a66 3382
d1ac91d8 3383 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3384 break;
3385 }
92a1f12d
JR		 3386 case KVM_SET_TSC_KHZ: {
3387 u32 user_tsc_khz;
3388
3389 r = -EINVAL;
92a1f12d
JR		 3390 user_tsc_khz = (u32)arg;
3391
3392 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3393 goto out;
3394
cc578287
ZA		 3395 if (user_tsc_khz == 0)
3396 user_tsc_khz = tsc_khz;
3397
3398 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3399
3400 r = 0;
3401 goto out;
3402 }
3403 case KVM_GET_TSC_KHZ: {
cc578287 3404 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3405 goto out;
3406 }
1c0b28c2
EM		 3407 case KVM_KVMCLOCK_CTRL: {
3408 r = kvm_set_guest_paused(vcpu);
3409 goto out;
3410 }
313a3dc7
CO		 3411 default:
3412 r = -EINVAL;
3413 }
3414out:
d1ac91d8 3415 kfree(u.buffer);
313a3dc7
CO		 3416 return r;
3417}
3418
5b1c1493
CO		 3419int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3420{
3421 return VM_FAULT_SIGBUS;
3422}
3423
1fe779f8
CO		 3424static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3425{
3426 int ret;
3427
3428 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3429 return -EINVAL;
1fe779f8
CO		 3430 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3431 return ret;
3432}
3433
b927a3ce
SY		 3434static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3435 u64 ident_addr)
3436{
3437 kvm->arch.ept_identity_map_addr = ident_addr;
3438 return 0;
3439}
3440
1fe779f8
CO		 3441static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3442 u32 kvm_nr_mmu_pages)
3443{
3444 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3445 return -EINVAL;
3446
79fac95e 3447 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3448
3449 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3450 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3451
79fac95e 3452 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3453 return 0;
3454}
3455
3456static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3457{
39de71ec 3458 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3459}
3460
1fe779f8
CO		 3461static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3462{
3463 int r;
3464
3465 r = 0;
3466 switch (chip->chip_id) {
3467 case KVM_IRQCHIP_PIC_MASTER:
3468 memcpy(&chip->chip.pic,
3469 &pic_irqchip(kvm)->pics[0],
3470 sizeof(struct kvm_pic_state));
3471 break;
3472 case KVM_IRQCHIP_PIC_SLAVE:
3473 memcpy(&chip->chip.pic,
3474 &pic_irqchip(kvm)->pics[1],
3475 sizeof(struct kvm_pic_state));
3476 break;
3477 case KVM_IRQCHIP_IOAPIC:
eba0226b 3478 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3479 break;
3480 default:
3481 r = -EINVAL;
3482 break;
3483 }
3484 return r;
3485}
3486
3487static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3488{
3489 int r;
3490
3491 r = 0;
3492 switch (chip->chip_id) {
3493 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3494 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3495 memcpy(&pic_irqchip(kvm)->pics[0],
3496 &chip->chip.pic,
3497 sizeof(struct kvm_pic_state));
f4f51050 3498 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3499 break;
3500 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3501 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3502 memcpy(&pic_irqchip(kvm)->pics[1],
3503 &chip->chip.pic,
3504 sizeof(struct kvm_pic_state));
f4f51050 3505 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3506 break;
3507 case KVM_IRQCHIP_IOAPIC:
eba0226b 3508 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3509 break;
3510 default:
3511 r = -EINVAL;
3512 break;
3513 }
3514 kvm_pic_update_irq(pic_irqchip(kvm));
3515 return r;
3516}
3517
e0f63cb9
SY		 3518static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3519{
3520 int r = 0;
3521
894a9c55 3522 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3523 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3524 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3525 return r;
3526}
3527
3528static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3529{
3530 int r = 0;
3531
894a9c55 3532 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3533 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3534 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3535 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3536 return r;
3537}
3538
3539static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3540{
3541 int r = 0;
3542
3543 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3544 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3545 sizeof(ps->channels));
3546 ps->flags = kvm->arch.vpit->pit_state.flags;
3547 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3548 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3549 return r;
3550}
3551
3552static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3553{
3554 int r = 0, start = 0;
3555 u32 prev_legacy, cur_legacy;
3556 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3557 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3558 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3559 if (!prev_legacy && cur_legacy)
3560 start = 1;
3561 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3562 sizeof(kvm->arch.vpit->pit_state.channels));
3563 kvm->arch.vpit->pit_state.flags = ps->flags;
3564 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3565 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3566 return r;
3567}
3568
52d939a0
MT		 3569static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3570 struct kvm_reinject_control *control)
3571{
3572 if (!kvm->arch.vpit)
3573 return -ENXIO;
894a9c55 3574 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3575 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3576 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3577 return 0;
3578}
3579
95d4c16c 3580/**
60c34612
TY		 3581 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3582 * @kvm: kvm instance
3583 * @log: slot id and address to which we copy the log
95d4c16c 3584 *
60c34612
TY		 3585 * We need to keep it in mind that VCPU threads can write to the bitmap
3586 * concurrently. So, to avoid losing data, we keep the following order for
3587 * each bit:
95d4c16c 3588 *
60c34612
TY		 3589 * 1. Take a snapshot of the bit and clear it if needed.
3590 * 2. Write protect the corresponding page.
3591 * 3. Flush TLB's if needed.
3592 * 4. Copy the snapshot to the userspace.
95d4c16c 3593 *
60c34612
TY		 3594 * Between 2 and 3, the guest may write to the page using the remaining TLB
3595 * entry. This is not a problem because the page will be reported dirty at
3596 * step 4 using the snapshot taken before and step 3 ensures that successive
3597 * writes will be logged for the next call.
5bb064dc 3598 */
60c34612 3599int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3600{
7850ac54 3601 int r;
5bb064dc 3602 struct kvm_memory_slot *memslot;
60c34612
TY		 3603 unsigned long n, i;
3604 unsigned long *dirty_bitmap;
3605 unsigned long *dirty_bitmap_buffer;
3606 bool is_dirty = false;
5bb064dc 3607
79fac95e 3608 mutex_lock(&kvm->slots_lock);
5bb064dc 3609
b050b015 3610 r = -EINVAL;
bbacc0c1 3611 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3612 goto out;
3613
28a37544 3614 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3615
3616 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3617 r = -ENOENT;
60c34612 3618 if (!dirty_bitmap)
b050b015
MT		 3619 goto out;
3620
87bf6e7d 3621 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3622
60c34612
TY		 3623 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3624 memset(dirty_bitmap_buffer, 0, n);
b050b015 3625
60c34612 3626 spin_lock(&kvm->mmu_lock);
b050b015 3627
60c34612
TY		 3628 for (i = 0; i < n / sizeof(long); i++) {
3629 unsigned long mask;
3630 gfn_t offset;
cdfca7b3 3631
60c34612
TY		 3632 if (!dirty_bitmap[i])
3633 continue;
b050b015 3634
60c34612 3635 is_dirty = true;
914ebccd 3636
60c34612
TY		 3637 mask = xchg(&dirty_bitmap[i], 0);
3638 dirty_bitmap_buffer[i] = mask;
edde99ce 3639
60c34612
TY		 3640 offset = i * BITS_PER_LONG;
3641 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3642 }
60c34612
TY		 3643 if (is_dirty)
3644 kvm_flush_remote_tlbs(kvm);
3645
3646 spin_unlock(&kvm->mmu_lock);
3647
3648 r = -EFAULT;
3649 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3650 goto out;
b050b015 3651
5bb064dc
ZX		 3652 r = 0;
3653out:
79fac95e 3654 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3655 return r;
3656}
3657
aa2fbe6d
YZ		 3658int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3659 bool line_status)
23d43cf9
CD		 3660{
3661 if (!irqchip_in_kernel(kvm))
3662 return -ENXIO;
3663
3664 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3665 irq_event->irq, irq_event->level,
3666 line_status);
23d43cf9
CD		 3667 return 0;
3668}
3669
1fe779f8
CO		 3670long kvm_arch_vm_ioctl(struct file *filp,
3671 unsigned int ioctl, unsigned long arg)
3672{
3673 struct kvm *kvm = filp->private_data;
3674 void __user *argp = (void __user *)arg;
367e1319 3675 int r = -ENOTTY;
f0d66275
DH		 3676 /*
3677 * This union makes it completely explicit to gcc-3.x
3678 * that these two variables' stack usage should be
3679 * combined, not added together.
3680 */
3681 union {
3682 struct kvm_pit_state ps;
e9f42757 3683 struct kvm_pit_state2 ps2;
c5ff41ce 3684 struct kvm_pit_config pit_config;
f0d66275 3685 } u;
1fe779f8
CO		 3686
3687 switch (ioctl) {
3688 case KVM_SET_TSS_ADDR:
3689 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3690 break;
b927a3ce
SY		 3691 case KVM_SET_IDENTITY_MAP_ADDR: {
3692 u64 ident_addr;
3693
3694 r = -EFAULT;
3695 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3696 goto out;
3697 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3698 break;
3699 }
1fe779f8
CO		 3700 case KVM_SET_NR_MMU_PAGES:
3701 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3702 break;
3703 case KVM_GET_NR_MMU_PAGES:
3704 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3705 break;
3ddea128
MT		 3706 case KVM_CREATE_IRQCHIP: {
3707 struct kvm_pic *vpic;
3708
3709 mutex_lock(&kvm->lock);
3710 r = -EEXIST;
3711 if (kvm->arch.vpic)
3712 goto create_irqchip_unlock;
3e515705
AK		 3713 r = -EINVAL;
3714 if (atomic_read(&kvm->online_vcpus))
3715 goto create_irqchip_unlock;
1fe779f8 3716 r = -ENOMEM;
3ddea128
MT		 3717 vpic = kvm_create_pic(kvm);
3718 if (vpic) {
1fe779f8
CO		 3719 r = kvm_ioapic_init(kvm);
3720 if (r) {
175504cd 3721 mutex_lock(&kvm->slots_lock);
72bb2fcd 3722 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3723 &vpic->dev_master);
3724 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3725 &vpic->dev_slave);
3726 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3727 &vpic->dev_eclr);
175504cd 3728 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3729 kfree(vpic);
3730 goto create_irqchip_unlock;
1fe779f8
CO		 3731 }
3732 } else
3ddea128
MT		 3733 goto create_irqchip_unlock;
3734 smp_wmb();
3735 kvm->arch.vpic = vpic;
3736 smp_wmb();
399ec807
AK		 3737 r = kvm_setup_default_irq_routing(kvm);
3738 if (r) {
175504cd 3739 mutex_lock(&kvm->slots_lock);
3ddea128 3740 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3741 kvm_ioapic_destroy(kvm);
3742 kvm_destroy_pic(kvm);
3ddea128 3743 mutex_unlock(&kvm->irq_lock);
175504cd 3744 mutex_unlock(&kvm->slots_lock);
399ec807 3745 }
3ddea128
MT		 3746 create_irqchip_unlock:
3747 mutex_unlock(&kvm->lock);
1fe779f8 3748 break;
3ddea128 3749 }
7837699f 3750 case KVM_CREATE_PIT:
c5ff41ce
JK		 3751 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3752 goto create_pit;
3753 case KVM_CREATE_PIT2:
3754 r = -EFAULT;
3755 if (copy_from_user(&u.pit_config, argp,
3756 sizeof(struct kvm_pit_config)))
3757 goto out;
3758 create_pit:
79fac95e 3759 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3760 r = -EEXIST;
3761 if (kvm->arch.vpit)
3762 goto create_pit_unlock;
7837699f 3763 r = -ENOMEM;
c5ff41ce 3764 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3765 if (kvm->arch.vpit)
3766 r = 0;
269e05e4 3767 create_pit_unlock:
79fac95e 3768 mutex_unlock(&kvm->slots_lock);
7837699f 3769 break;
1fe779f8
CO		 3770 case KVM_GET_IRQCHIP: {
3771 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3772 struct kvm_irqchip *chip;
1fe779f8 3773
ff5c2c03
SL		 3774 chip = memdup_user(argp, sizeof(*chip));
3775 if (IS_ERR(chip)) {
3776 r = PTR_ERR(chip);
1fe779f8 3777 goto out;
ff5c2c03
SL		 3778 }
3779
1fe779f8
CO		 3780 r = -ENXIO;
3781 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3782 goto get_irqchip_out;
3783 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3784 if (r)
f0d66275 3785 goto get_irqchip_out;
1fe779f8 3786 r = -EFAULT;
f0d66275
DH		 3787 if (copy_to_user(argp, chip, sizeof *chip))
3788 goto get_irqchip_out;
1fe779f8 3789 r = 0;
f0d66275
DH		 3790 get_irqchip_out:
3791 kfree(chip);
1fe779f8
CO		 3792 break;
3793 }
3794 case KVM_SET_IRQCHIP: {
3795 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3796 struct kvm_irqchip *chip;
1fe779f8 3797
ff5c2c03
SL		 3798 chip = memdup_user(argp, sizeof(*chip));
3799 if (IS_ERR(chip)) {
3800 r = PTR_ERR(chip);
1fe779f8 3801 goto out;
ff5c2c03
SL		 3802 }
3803
1fe779f8
CO		 3804 r = -ENXIO;
3805 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3806 goto set_irqchip_out;
3807 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3808 if (r)
f0d66275 3809 goto set_irqchip_out;
1fe779f8 3810 r = 0;
f0d66275
DH		 3811 set_irqchip_out:
3812 kfree(chip);
1fe779f8
CO		 3813 break;
3814 }
e0f63cb9 3815 case KVM_GET_PIT: {
e0f63cb9 3816 r = -EFAULT;
f0d66275 3817 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3818 goto out;
3819 r = -ENXIO;
3820 if (!kvm->arch.vpit)
3821 goto out;
f0d66275 3822 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3823 if (r)
3824 goto out;
3825 r = -EFAULT;
f0d66275 3826 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3827 goto out;
3828 r = 0;
3829 break;
3830 }
3831 case KVM_SET_PIT: {
e0f63cb9 3832 r = -EFAULT;
f0d66275 3833 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3834 goto out;
3835 r = -ENXIO;
3836 if (!kvm->arch.vpit)
3837 goto out;
f0d66275 3838 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3839 break;
3840 }
e9f42757
BK		 3841 case KVM_GET_PIT2: {
3842 r = -ENXIO;
3843 if (!kvm->arch.vpit)
3844 goto out;
3845 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3846 if (r)
3847 goto out;
3848 r = -EFAULT;
3849 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3850 goto out;
3851 r = 0;
3852 break;
3853 }
3854 case KVM_SET_PIT2: {
3855 r = -EFAULT;
3856 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3857 goto out;
3858 r = -ENXIO;
3859 if (!kvm->arch.vpit)
3860 goto out;
3861 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3862 break;
3863 }
52d939a0
MT		 3864 case KVM_REINJECT_CONTROL: {
3865 struct kvm_reinject_control control;
3866 r = -EFAULT;
3867 if (copy_from_user(&control, argp, sizeof(control)))
3868 goto out;
3869 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3870 break;
3871 }
ffde22ac
ES		 3872 case KVM_XEN_HVM_CONFIG: {
3873 r = -EFAULT;
3874 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3875 sizeof(struct kvm_xen_hvm_config)))
3876 goto out;
3877 r = -EINVAL;
3878 if (kvm->arch.xen_hvm_config.flags)
3879 goto out;
3880 r = 0;
3881 break;
3882 }
afbcf7ab 3883 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3884 struct kvm_clock_data user_ns;
3885 u64 now_ns;
3886 s64 delta;
3887
3888 r = -EFAULT;
3889 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3890 goto out;
3891
3892 r = -EINVAL;
3893 if (user_ns.flags)
3894 goto out;
3895
3896 r = 0;
395c6b0a 3897 local_irq_disable();
759379dd 3898 now_ns = get_kernel_ns();
afbcf7ab 3899 delta = user_ns.clock - now_ns;
395c6b0a 3900 local_irq_enable();
afbcf7ab 3901 kvm->arch.kvmclock_offset = delta;
2e762ff7 3902 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3903 break;
3904 }
3905 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3906 struct kvm_clock_data user_ns;
3907 u64 now_ns;
3908
395c6b0a 3909 local_irq_disable();
759379dd 3910 now_ns = get_kernel_ns();
afbcf7ab 3911 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3912 local_irq_enable();
afbcf7ab 3913 user_ns.flags = 0;
97e69aa6 3914 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3915
3916 r = -EFAULT;
3917 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3918 goto out;
3919 r = 0;
3920 break;
3921 }
3922
1fe779f8
CO		 3923 default:
3924 ;
3925 }
3926out:
3927 return r;
3928}
3929
a16b043c 3930static void kvm_init_msr_list(void)
043405e1
CO		 3931{
3932 u32 dummy[2];
3933 unsigned i, j;
3934
e3267cbb
GC		 3935 /* skip the first msrs in the list. KVM-specific */
3936 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3937 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3938 continue;
3939 if (j < i)
3940 msrs_to_save[j] = msrs_to_save[i];
3941 j++;
3942 }
3943 num_msrs_to_save = j;
3944}
3945
bda9020e
MT		 3946static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3947 const void *v)
bbd9b64e 3948{
70252a10
AK		 3949 int handled = 0;
3950 int n;
3951
3952 do {
3953 n = min(len, 8);
3954 if (!(vcpu->arch.apic &&
3955 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3956 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3957 break;
3958 handled += n;
3959 addr += n;
3960 len -= n;
3961 v += n;
3962 } while (len);
bbd9b64e 3963
70252a10 3964 return handled;
bbd9b64e
CO		 3965}
3966
bda9020e 3967static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3968{
70252a10
AK		 3969 int handled = 0;
3970 int n;
3971
3972 do {
3973 n = min(len, 8);
3974 if (!(vcpu->arch.apic &&
3975 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3976 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3977 break;
3978 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3979 handled += n;
3980 addr += n;
3981 len -= n;
3982 v += n;
3983 } while (len);
bbd9b64e 3984
70252a10 3985 return handled;
bbd9b64e
CO		 3986}
3987
2dafc6c2
GN		 3988static void kvm_set_segment(struct kvm_vcpu *vcpu,
3989 struct kvm_segment *var, int seg)
3990{
3991 kvm_x86_ops->set_segment(vcpu, var, seg);
3992}
3993
3994void kvm_get_segment(struct kvm_vcpu *vcpu,
3995 struct kvm_segment *var, int seg)
3996{
3997 kvm_x86_ops->get_segment(vcpu, var, seg);
3998}
3999
e459e322 4000gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 4001{
4002 gpa_t t_gpa;
ab9ae313 4003 struct x86_exception exception;
02f59dc9
JR		 4004
4005 BUG_ON(!mmu_is_nested(vcpu));
4006
4007 /* NPT walks are always user-walks */
4008 access |= PFERR_USER_MASK;
ab9ae313 4009 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 4010
4011 return t_gpa;
4012}
4013
ab9ae313
AK		 4014gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4015 struct x86_exception *exception)
1871c602
GN		 4016{
4017 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4018 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4019}
4020
ab9ae313
AK		 4021 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4022 struct x86_exception *exception)
1871c602
GN		 4023{
4024 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4025 access |= PFERR_FETCH_MASK;
ab9ae313 4026 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4027}
4028
ab9ae313
AK		 4029gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4030 struct x86_exception *exception)
1871c602
GN		 4031{
4032 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4033 access |= PFERR_WRITE_MASK;
ab9ae313 4034 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4035}
4036
4037/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4038gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4039 struct x86_exception *exception)
1871c602 4040{
ab9ae313 4041 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4042}
4043
4044static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4045 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4046 struct x86_exception *exception)
bbd9b64e
CO		 4047{
4048 void *data = val;
10589a46 4049 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4050
4051 while (bytes) {
14dfe855 4052 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4053 exception);
bbd9b64e 4054 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4055 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4056 int ret;
4057
bcc55cba 4058 if (gpa == UNMAPPED_GVA)
ab9ae313 4059 return X86EMUL_PROPAGATE_FAULT;
77c2002e 4060 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 4061 if (ret < 0) {
c3cd7ffa 4062 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4063 goto out;
4064 }
bbd9b64e 4065
77c2002e
IE		 4066 bytes -= toread;
4067 data += toread;
4068 addr += toread;
bbd9b64e 4069 }
10589a46 4070out:
10589a46 4071 return r;
bbd9b64e 4072}
77c2002e 4073
1871c602 4074/* used for instruction fetching */
0f65dd70
AK		 4075static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4076 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4077 struct x86_exception *exception)
1871c602 4078{
0f65dd70 4079 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4080 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4081
1871c602 4082 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 4083 access | PFERR_FETCH_MASK,
4084 exception);
1871c602
GN		 4085}
4086
064aea77 4087int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4088 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4089 struct x86_exception *exception)
1871c602 4090{
0f65dd70 4091 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4092 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4093
1871c602 4094 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4095 exception);
1871c602 4096}
064aea77 4097EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4098
0f65dd70
AK		 4099static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4100 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4101 struct x86_exception *exception)
1871c602 4102{
0f65dd70 4103 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4104 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4105}
4106
6a4d7550 4107int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4108 gva_t addr, void *val,
2dafc6c2 4109 unsigned int bytes,
bcc55cba 4110 struct x86_exception *exception)
77c2002e 4111{
0f65dd70 4112 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4113 void *data = val;
4114 int r = X86EMUL_CONTINUE;
4115
4116 while (bytes) {
14dfe855
JR		 4117 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4118 PFERR_WRITE_MASK,
ab9ae313 4119 exception);
77c2002e
IE		 4120 unsigned offset = addr & (PAGE_SIZE-1);
4121 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4122 int ret;
4123
bcc55cba 4124 if (gpa == UNMAPPED_GVA)
ab9ae313 4125 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4126 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4127 if (ret < 0) {
c3cd7ffa 4128 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4129 goto out;
4130 }
4131
4132 bytes -= towrite;
4133 data += towrite;
4134 addr += towrite;
4135 }
4136out:
4137 return r;
4138}
6a4d7550 4139EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4140
af7cc7d1
XG		 4141static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4142 gpa_t *gpa, struct x86_exception *exception,
4143 bool write)
4144{
97d64b78
AK		 4145 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4146 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4147
97d64b78
AK		 4148 if (vcpu_match_mmio_gva(vcpu, gva)
4149 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
bebb106a
XG		 4150 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4151 (gva & (PAGE_SIZE - 1));
4f022648 4152 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4153 return 1;
4154 }
4155
af7cc7d1
XG		 4156 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4157
4158 if (*gpa == UNMAPPED_GVA)
4159 return -1;
4160
4161 /* For APIC access vmexit */
4162 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4163 return 1;
4164
4f022648
XG		 4165 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4166 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4167 return 1;
4f022648 4168 }
bebb106a 4169
af7cc7d1
XG		 4170 return 0;
4171}
4172
3200f405 4173int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4174 const void *val, int bytes)
bbd9b64e
CO		 4175{
4176 int ret;
4177
4178 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4179 if (ret < 0)
bbd9b64e 4180 return 0;
f57f2ef5 4181 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4182 return 1;
4183}
4184
77d197b2
XG		 4185struct read_write_emulator_ops {
4186 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4187 int bytes);
4188 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4189 void *val, int bytes);
4190 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4191 int bytes, void *val);
4192 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4193 void *val, int bytes);
4194 bool write;
4195};
4196
4197static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4198{
4199 if (vcpu->mmio_read_completed) {
77d197b2 4200 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4201 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4202 vcpu->mmio_read_completed = 0;
4203 return 1;
4204 }
4205
4206 return 0;
4207}
4208
4209static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4210 void *val, int bytes)
4211{
4212 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4213}
4214
4215static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4216 void *val, int bytes)
4217{
4218 return emulator_write_phys(vcpu, gpa, val, bytes);
4219}
4220
4221static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4222{
4223 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4224 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4225}
4226
4227static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4228 void *val, int bytes)
4229{
4230 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4231 return X86EMUL_IO_NEEDED;
4232}
4233
4234static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4235 void *val, int bytes)
4236{
f78146b0
AK		 4237 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4238
87da7e66 4239 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4240 return X86EMUL_CONTINUE;
4241}
4242
0fbe9b0b 4243static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4244 .read_write_prepare = read_prepare,
4245 .read_write_emulate = read_emulate,
4246 .read_write_mmio = vcpu_mmio_read,
4247 .read_write_exit_mmio = read_exit_mmio,
4248};
4249
0fbe9b0b 4250static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4251 .read_write_emulate = write_emulate,
4252 .read_write_mmio = write_mmio,
4253 .read_write_exit_mmio = write_exit_mmio,
4254 .write = true,
4255};
4256
22388a3c
XG		 4257static int emulator_read_write_onepage(unsigned long addr, void *val,
4258 unsigned int bytes,
4259 struct x86_exception *exception,
4260 struct kvm_vcpu *vcpu,
0fbe9b0b 4261 const struct read_write_emulator_ops *ops)
bbd9b64e 4262{
af7cc7d1
XG		 4263 gpa_t gpa;
4264 int handled, ret;
22388a3c 4265 bool write = ops->write;
f78146b0 4266 struct kvm_mmio_fragment *frag;
10589a46 4267
22388a3c 4268 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4269
af7cc7d1 4270 if (ret < 0)
bbd9b64e 4271 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4272
4273 /* For APIC access vmexit */
af7cc7d1 4274 if (ret)
bbd9b64e
CO		 4275 goto mmio;
4276
22388a3c 4277 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4278 return X86EMUL_CONTINUE;
4279
4280mmio:
4281 /*
4282 * Is this MMIO handled locally?
4283 */
22388a3c 4284 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4285 if (handled == bytes)
bbd9b64e 4286 return X86EMUL_CONTINUE;
bbd9b64e 4287
70252a10
AK		 4288 gpa += handled;
4289 bytes -= handled;
4290 val += handled;
4291
87da7e66
XG		 4292 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4293 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4294 frag->gpa = gpa;
4295 frag->data = val;
4296 frag->len = bytes;
f78146b0 4297 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4298}
4299
22388a3c
XG		 4300int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4301 void *val, unsigned int bytes,
4302 struct x86_exception *exception,
0fbe9b0b 4303 const struct read_write_emulator_ops *ops)
bbd9b64e 4304{
0f65dd70 4305 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4306 gpa_t gpa;
4307 int rc;
4308
4309 if (ops->read_write_prepare &&
4310 ops->read_write_prepare(vcpu, val, bytes))
4311 return X86EMUL_CONTINUE;
4312
4313 vcpu->mmio_nr_fragments = 0;
0f65dd70 4314
bbd9b64e
CO		 4315 /* Crossing a page boundary? */
4316 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4317 int now;
bbd9b64e
CO		 4318
4319 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4320 rc = emulator_read_write_onepage(addr, val, now, exception,
4321 vcpu, ops);
4322
bbd9b64e
CO		 4323 if (rc != X86EMUL_CONTINUE)
4324 return rc;
4325 addr += now;
4326 val += now;
4327 bytes -= now;
4328 }
22388a3c 4329
f78146b0
AK		 4330 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4331 vcpu, ops);
4332 if (rc != X86EMUL_CONTINUE)
4333 return rc;
4334
4335 if (!vcpu->mmio_nr_fragments)
4336 return rc;
4337
4338 gpa = vcpu->mmio_fragments[0].gpa;
4339
4340 vcpu->mmio_needed = 1;
4341 vcpu->mmio_cur_fragment = 0;
4342
87da7e66 4343 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4344 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4345 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4346 vcpu->run->mmio.phys_addr = gpa;
4347
4348 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4349}
4350
4351static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4352 unsigned long addr,
4353 void *val,
4354 unsigned int bytes,
4355 struct x86_exception *exception)
4356{
4357 return emulator_read_write(ctxt, addr, val, bytes,
4358 exception, &read_emultor);
4359}
4360
4361int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4362 unsigned long addr,
4363 const void *val,
4364 unsigned int bytes,
4365 struct x86_exception *exception)
4366{
4367 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4368 exception, &write_emultor);
bbd9b64e 4369}
bbd9b64e 4370
daea3e73
AK		 4371#define CMPXCHG_TYPE(t, ptr, old, new) \
4372 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4373
4374#ifdef CONFIG_X86_64
4375# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4376#else
4377# define CMPXCHG64(ptr, old, new) \
9749a6c0 4378 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4379#endif
4380
0f65dd70
AK		 4381static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4382 unsigned long addr,
bbd9b64e
CO		 4383 const void *old,
4384 const void *new,
4385 unsigned int bytes,
0f65dd70 4386 struct x86_exception *exception)
bbd9b64e 4387{
0f65dd70 4388 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4389 gpa_t gpa;
4390 struct page *page;
4391 char *kaddr;
4392 bool exchanged;
2bacc55c 4393
daea3e73
AK		 4394 /* guests cmpxchg8b have to be emulated atomically */
4395 if (bytes > 8 || (bytes & (bytes - 1)))
4396 goto emul_write;
10589a46 4397
daea3e73 4398 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4399
daea3e73
AK		 4400 if (gpa == UNMAPPED_GVA ||
4401 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4402 goto emul_write;
2bacc55c 4403
daea3e73
AK		 4404 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4405 goto emul_write;
72dc67a6 4406
daea3e73 4407 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4408 if (is_error_page(page))
c19b8bd6 4409 goto emul_write;
72dc67a6 4410
8fd75e12 4411 kaddr = kmap_atomic(page);
daea3e73
AK		 4412 kaddr += offset_in_page(gpa);
4413 switch (bytes) {
4414 case 1:
4415 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4416 break;
4417 case 2:
4418 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4419 break;
4420 case 4:
4421 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4422 break;
4423 case 8:
4424 exchanged = CMPXCHG64(kaddr, old, new);
4425 break;
4426 default:
4427 BUG();
2bacc55c 4428 }
8fd75e12 4429 kunmap_atomic(kaddr);
daea3e73
AK		 4430 kvm_release_page_dirty(page);
4431
4432 if (!exchanged)
4433 return X86EMUL_CMPXCHG_FAILED;
4434
d3714010 4435 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4436 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4437
4438 return X86EMUL_CONTINUE;
4a5f48f6 4439
3200f405 4440emul_write:
daea3e73 4441 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4442
0f65dd70 4443 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4444}
4445
cf8f70bf
GN		 4446static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4447{
4448 /* TODO: String I/O for in kernel device */
4449 int r;
4450
4451 if (vcpu->arch.pio.in)
4452 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4453 vcpu->arch.pio.size, pd);
4454 else
4455 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4456 vcpu->arch.pio.port, vcpu->arch.pio.size,
4457 pd);
4458 return r;
4459}
4460
6f6fbe98
XG		 4461static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4462 unsigned short port, void *val,
4463 unsigned int count, bool in)
cf8f70bf 4464{
6f6fbe98 4465 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 4466
4467 vcpu->arch.pio.port = port;
6f6fbe98 4468 vcpu->arch.pio.in = in;
7972995b 4469 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4470 vcpu->arch.pio.size = size;
4471
4472 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4473 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4474 return 1;
4475 }
4476
4477 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4478 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4479 vcpu->run->io.size = size;
4480 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4481 vcpu->run->io.count = count;
4482 vcpu->run->io.port = port;
4483
4484 return 0;
4485}
4486
6f6fbe98
XG		 4487static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4488 int size, unsigned short port, void *val,
4489 unsigned int count)
cf8f70bf 4490{
ca1d4a9e 4491 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4492 int ret;
ca1d4a9e 4493
6f6fbe98
XG		 4494 if (vcpu->arch.pio.count)
4495 goto data_avail;
cf8f70bf 4496
6f6fbe98
XG		 4497 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4498 if (ret) {
4499data_avail:
4500 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4501 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4502 return 1;
4503 }
4504
cf8f70bf
GN		 4505 return 0;
4506}
4507
6f6fbe98
XG		 4508static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4509 int size, unsigned short port,
4510 const void *val, unsigned int count)
4511{
4512 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4513
4514 memcpy(vcpu->arch.pio_data, val, size * count);
4515 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4516}
4517
bbd9b64e
CO		 4518static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4519{
4520 return kvm_x86_ops->get_segment_base(vcpu, seg);
4521}
4522
3cb16fe7 4523static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4524{
3cb16fe7 4525 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4526}
4527
f5f48ee1
SY		 4528int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4529{
4530 if (!need_emulate_wbinvd(vcpu))
4531 return X86EMUL_CONTINUE;
4532
4533 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4534 int cpu = get_cpu();
4535
4536 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4537 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4538 wbinvd_ipi, NULL, 1);
2eec7343 4539 put_cpu();
f5f48ee1 4540 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4541 } else
4542 wbinvd();
f5f48ee1
SY		 4543 return X86EMUL_CONTINUE;
4544}
4545EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4546
bcaf5cc5
AK		 4547static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4548{
4549 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4550}
4551
717746e3 4552int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4553{
717746e3 4554 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4555}
4556
717746e3 4557int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4558{
338dbc97 4559
717746e3 4560 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4561}
4562
52a46617 4563static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4564{
52a46617 4565 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4566}
4567
717746e3 4568static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4569{
717746e3 4570 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4571 unsigned long value;
4572
4573 switch (cr) {
4574 case 0:
4575 value = kvm_read_cr0(vcpu);
4576 break;
4577 case 2:
4578 value = vcpu->arch.cr2;
4579 break;
4580 case 3:
9f8fe504 4581 value = kvm_read_cr3(vcpu);
52a46617
GN		 4582 break;
4583 case 4:
4584 value = kvm_read_cr4(vcpu);
4585 break;
4586 case 8:
4587 value = kvm_get_cr8(vcpu);
4588 break;
4589 default:
a737f256 4590 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4591 return 0;
4592 }
4593
4594 return value;
4595}
4596
717746e3 4597static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4598{
717746e3 4599 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4600 int res = 0;
4601
52a46617
GN		 4602 switch (cr) {
4603 case 0:
49a9b07e 4604 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4605 break;
4606 case 2:
4607 vcpu->arch.cr2 = val;
4608 break;
4609 case 3:
2390218b 4610 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4611 break;
4612 case 4:
a83b29c6 4613 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4614 break;
4615 case 8:
eea1cff9 4616 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4617 break;
4618 default:
a737f256 4619 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4620 res = -1;
52a46617 4621 }
0f12244f
GN		 4622
4623 return res;
52a46617
GN		 4624}
4625
4cee4798
KW		 4626static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4627{
4628 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4629}
4630
717746e3 4631static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4632{
717746e3 4633 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4634}
4635
4bff1e86 4636static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4637{
4bff1e86 4638 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4639}
4640
4bff1e86 4641static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4642{
4bff1e86 4643 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4644}
4645
1ac9d0cf
AK		 4646static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4647{
4648 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4649}
4650
4651static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4652{
4653 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4654}
4655
4bff1e86
AK		 4656static unsigned long emulator_get_cached_segment_base(
4657 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4658{
4bff1e86 4659 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4660}
4661
1aa36616
AK		 4662static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4663 struct desc_struct *desc, u32 *base3,
4664 int seg)
2dafc6c2
GN		 4665{
4666 struct kvm_segment var;
4667
4bff1e86 4668 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4669 *selector = var.selector;
2dafc6c2 4670
378a8b09
GN		 4671 if (var.unusable) {
4672 memset(desc, 0, sizeof(*desc));
2dafc6c2 4673 return false;
378a8b09 4674 }
2dafc6c2
GN		 4675
4676 if (var.g)
4677 var.limit >>= 12;
4678 set_desc_limit(desc, var.limit);
4679 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4680#ifdef CONFIG_X86_64
4681 if (base3)
4682 *base3 = var.base >> 32;
4683#endif
2dafc6c2
GN		 4684 desc->type = var.type;
4685 desc->s = var.s;
4686 desc->dpl = var.dpl;
4687 desc->p = var.present;
4688 desc->avl = var.avl;
4689 desc->l = var.l;
4690 desc->d = var.db;
4691 desc->g = var.g;
4692
4693 return true;
4694}
4695
1aa36616
AK		 4696static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4697 struct desc_struct *desc, u32 base3,
4698 int seg)
2dafc6c2 4699{
4bff1e86 4700 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4701 struct kvm_segment var;
4702
1aa36616 4703 var.selector = selector;
2dafc6c2 4704 var.base = get_desc_base(desc);
5601d05b
GN		 4705#ifdef CONFIG_X86_64
4706 var.base |= ((u64)base3) << 32;
4707#endif
2dafc6c2
GN		 4708 var.limit = get_desc_limit(desc);
4709 if (desc->g)
4710 var.limit = (var.limit << 12) | 0xfff;
4711 var.type = desc->type;
4712 var.present = desc->p;
4713 var.dpl = desc->dpl;
4714 var.db = desc->d;
4715 var.s = desc->s;
4716 var.l = desc->l;
4717 var.g = desc->g;
4718 var.avl = desc->avl;
4719 var.present = desc->p;
4720 var.unusable = !var.present;
4721 var.padding = 0;
4722
4723 kvm_set_segment(vcpu, &var, seg);
4724 return;
4725}
4726
717746e3
AK		 4727static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4728 u32 msr_index, u64 *pdata)
4729{
4730 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4731}
4732
4733static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4734 u32 msr_index, u64 data)
4735{
8fe8ab46
WA		 4736 struct msr_data msr;
4737
4738 msr.data = data;
4739 msr.index = msr_index;
4740 msr.host_initiated = false;
4741 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4742}
4743
222d21aa
AK		 4744static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4745 u32 pmc, u64 *pdata)
4746{
4747 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4748}
4749
6c3287f7
AK		 4750static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4751{
4752 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4753}
4754
5037f6f3
AK		 4755static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4756{
4757 preempt_disable();
5197b808 4758 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4759 /*
4760 * CR0.TS may reference the host fpu state, not the guest fpu state,
4761 * so it may be clear at this point.
4762 */
4763 clts();
4764}
4765
4766static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4767{
4768 preempt_enable();
4769}
4770
2953538e 4771static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4772 struct x86_instruction_info *info,
c4f035c6
AK		 4773 enum x86_intercept_stage stage)
4774{
2953538e 4775 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4776}
4777
0017f93a 4778static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4779 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4780{
0017f93a 4781 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4782}
4783
dd856efa
AK		 4784static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4785{
4786 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4787}
4788
4789static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4790{
4791 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4792}
4793
0225fb50 4794static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4795 .read_gpr = emulator_read_gpr,
4796 .write_gpr = emulator_write_gpr,
1871c602 4797 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4798 .write_std = kvm_write_guest_virt_system,
1871c602 4799 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4800 .read_emulated = emulator_read_emulated,
4801 .write_emulated = emulator_write_emulated,
4802 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4803 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4804 .pio_in_emulated = emulator_pio_in_emulated,
4805 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4806 .get_segment = emulator_get_segment,
4807 .set_segment = emulator_set_segment,
5951c442 4808 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4809 .get_gdt = emulator_get_gdt,
160ce1f1 4810 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4811 .set_gdt = emulator_set_gdt,
4812 .set_idt = emulator_set_idt,
52a46617
GN		 4813 .get_cr = emulator_get_cr,
4814 .set_cr = emulator_set_cr,
4cee4798 4815 .set_rflags = emulator_set_rflags,
9c537244 4816 .cpl = emulator_get_cpl,
35aa5375
GN		 4817 .get_dr = emulator_get_dr,
4818 .set_dr = emulator_set_dr,
717746e3
AK		 4819 .set_msr = emulator_set_msr,
4820 .get_msr = emulator_get_msr,
222d21aa 4821 .read_pmc = emulator_read_pmc,
6c3287f7 4822 .halt = emulator_halt,
bcaf5cc5 4823 .wbinvd = emulator_wbinvd,
d6aa1000 4824 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4825 .get_fpu = emulator_get_fpu,
4826 .put_fpu = emulator_put_fpu,
c4f035c6 4827 .intercept = emulator_intercept,
bdb42f5a 4828 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4829};
4830
95cb2295
GN		 4831static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4832{
4833 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4834 /*
4835 * an sti; sti; sequence only disable interrupts for the first
4836 * instruction. So, if the last instruction, be it emulated or
4837 * not, left the system with the INT_STI flag enabled, it
4838 * means that the last instruction is an sti. We should not
4839 * leave the flag on in this case. The same goes for mov ss
4840 */
4841 if (!(int_shadow & mask))
4842 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4843}
4844
54b8486f
GN		 4845static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4846{
4847 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4848 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4849 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4850 else if (ctxt->exception.error_code_valid)
4851 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4852 ctxt->exception.error_code);
54b8486f 4853 else
da9cb575 4854 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4855}
4856
dd856efa 4857static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
b5c9ff73 4858{
1ce19dc1
BP		 4859 memset(&ctxt->opcode_len, 0,
4860 (void *)&ctxt->_regs - (void *)&ctxt->opcode_len);
b5c9ff73 4861
9dac77fa
AK		 4862 ctxt->fetch.start = 0;
4863 ctxt->fetch.end = 0;
4864 ctxt->io_read.pos = 0;
4865 ctxt->io_read.end = 0;
4866 ctxt->mem_read.pos = 0;
4867 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4868}
4869
8ec4722d
MG		 4870static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4871{
adf52235 4872 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4873 int cs_db, cs_l;
4874
8ec4722d
MG		 4875 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4876
adf52235
TY		 4877 ctxt->eflags = kvm_get_rflags(vcpu);
4878 ctxt->eip = kvm_rip_read(vcpu);
4879 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4880 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4881 cs_l ? X86EMUL_MODE_PROT64 :
4882 cs_db ? X86EMUL_MODE_PROT32 :
4883 X86EMUL_MODE_PROT16;
4884 ctxt->guest_mode = is_guest_mode(vcpu);
4885
dd856efa 4886 init_decode_cache(ctxt);
7ae441ea 4887 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4888}
4889
71f9833b 4890int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4891{
9d74191a 4892 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4893 int ret;
4894
4895 init_emulate_ctxt(vcpu);
4896
9dac77fa
AK		 4897 ctxt->op_bytes = 2;
4898 ctxt->ad_bytes = 2;
4899 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4900 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4901
4902 if (ret != X86EMUL_CONTINUE)
4903 return EMULATE_FAIL;
4904
9dac77fa 4905 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4906 kvm_rip_write(vcpu, ctxt->eip);
4907 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4908
4909 if (irq == NMI_VECTOR)
7460fb4a 4910 vcpu->arch.nmi_pending = 0;
63995653
MG		 4911 else
4912 vcpu->arch.interrupt.pending = false;
4913
4914 return EMULATE_DONE;
4915}
4916EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4917
6d77dbfc
GN		 4918static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4919{
fc3a9157
JR		 4920 int r = EMULATE_DONE;
4921
6d77dbfc
GN		 4922 ++vcpu->stat.insn_emulation_fail;
4923 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4924 if (!is_guest_mode(vcpu)) {
4925 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4926 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4927 vcpu->run->internal.ndata = 0;
4928 r = EMULATE_FAIL;
4929 }
6d77dbfc 4930 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4931
4932 return r;
6d77dbfc
GN		 4933}
4934
93c05d3e 4935static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4936 bool write_fault_to_shadow_pgtable,
4937 int emulation_type)
a6f177ef 4938{
95b3cf69 4939 gpa_t gpa = cr2;
8e3d9d06 4940 pfn_t pfn;
a6f177ef 4941
991eebf9
GN		 4942 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4943 return false;
4944
95b3cf69
XG		 4945 if (!vcpu->arch.mmu.direct_map) {
4946 /*
4947 * Write permission should be allowed since only
4948 * write access need to be emulated.
4949 */
4950 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 4951
95b3cf69
XG		 4952 /*
4953 * If the mapping is invalid in guest, let cpu retry
4954 * it to generate fault.
4955 */
4956 if (gpa == UNMAPPED_GVA)
4957 return true;
4958 }
a6f177ef 4959
8e3d9d06
XG		 4960 /*
4961 * Do not retry the unhandleable instruction if it faults on the
4962 * readonly host memory, otherwise it will goto a infinite loop:
4963 * retry instruction -> write #PF -> emulation fail -> retry
4964 * instruction -> ...
4965 */
4966 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 4967
4968 /*
4969 * If the instruction failed on the error pfn, it can not be fixed,
4970 * report the error to userspace.
4971 */
4972 if (is_error_noslot_pfn(pfn))
4973 return false;
4974
4975 kvm_release_pfn_clean(pfn);
4976
4977 /* The instructions are well-emulated on direct mmu. */
4978 if (vcpu->arch.mmu.direct_map) {
4979 unsigned int indirect_shadow_pages;
4980
4981 spin_lock(&vcpu->kvm->mmu_lock);
4982 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4983 spin_unlock(&vcpu->kvm->mmu_lock);
4984
4985 if (indirect_shadow_pages)
4986 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4987
a6f177ef 4988 return true;
8e3d9d06 4989 }
a6f177ef 4990
95b3cf69
XG		 4991 /*
4992 * if emulation was due to access to shadowed page table
4993 * and it failed try to unshadow page and re-enter the
4994 * guest to let CPU execute the instruction.
4995 */
4996 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 4997
4998 /*
4999 * If the access faults on its page table, it can not
5000 * be fixed by unprotecting shadow page and it should
5001 * be reported to userspace.
5002 */
5003 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5004}
5005
1cb3f3ae
XG		 5006static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5007 unsigned long cr2, int emulation_type)
5008{
5009 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5010 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5011
5012 last_retry_eip = vcpu->arch.last_retry_eip;
5013 last_retry_addr = vcpu->arch.last_retry_addr;
5014
5015 /*
5016 * If the emulation is caused by #PF and it is non-page_table
5017 * writing instruction, it means the VM-EXIT is caused by shadow
5018 * page protected, we can zap the shadow page and retry this
5019 * instruction directly.
5020 *
5021 * Note: if the guest uses a non-page-table modifying instruction
5022 * on the PDE that points to the instruction, then we will unmap
5023 * the instruction and go to an infinite loop. So, we cache the
5024 * last retried eip and the last fault address, if we meet the eip
5025 * and the address again, we can break out of the potential infinite
5026 * loop.
5027 */
5028 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5029
5030 if (!(emulation_type & EMULTYPE_RETRY))
5031 return false;
5032
5033 if (x86_page_table_writing_insn(ctxt))
5034 return false;
5035
5036 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5037 return false;
5038
5039 vcpu->arch.last_retry_eip = ctxt->eip;
5040 vcpu->arch.last_retry_addr = cr2;
5041
5042 if (!vcpu->arch.mmu.direct_map)
5043 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5044
22368028 5045 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5046
5047 return true;
5048}
5049
716d51ab
GN		 5050static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5051static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5052
4a1e10d5
PB		 5053static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5054 unsigned long *db)
5055{
5056 u32 dr6 = 0;
5057 int i;
5058 u32 enable, rwlen;
5059
5060 enable = dr7;
5061 rwlen = dr7 >> 16;
5062 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5063 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5064 dr6 |= (1 << i);
5065 return dr6;
5066}
5067
663f4c61
PB		 5068static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, int *r)
5069{
5070 struct kvm_run *kvm_run = vcpu->run;
5071
5072 /*
5073 * Use the "raw" value to see if TF was passed to the processor.
5074 * Note that the new value of the flags has not been saved yet.
5075 *
5076 * This is correct even for TF set by the guest, because "the
5077 * processor will not generate this exception after the instruction
5078 * that sets the TF flag".
5079 */
5080 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5081
5082 if (unlikely(rflags & X86_EFLAGS_TF)) {
5083 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5084 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1;
5085 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5086 kvm_run->debug.arch.exception = DB_VECTOR;
5087 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5088 *r = EMULATE_USER_EXIT;
5089 } else {
5090 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5091 /*
5092 * "Certain debug exceptions may clear bit 0-3. The
5093 * remaining contents of the DR6 register are never
5094 * cleared by the processor".
5095 */
5096 vcpu->arch.dr6 &= ~15;
5097 vcpu->arch.dr6 |= DR6_BS;
5098 kvm_queue_exception(vcpu, DB_VECTOR);
5099 }
5100 }
5101}
5102
4a1e10d5
PB		 5103static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5104{
5105 struct kvm_run *kvm_run = vcpu->run;
5106 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5107 u32 dr6 = 0;
5108
5109 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5110 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5111 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5112 vcpu->arch.guest_debug_dr7,
5113 vcpu->arch.eff_db);
5114
5115 if (dr6 != 0) {
5116 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5117 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5118 get_segment_base(vcpu, VCPU_SREG_CS);
5119
5120 kvm_run->debug.arch.exception = DB_VECTOR;
5121 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5122 *r = EMULATE_USER_EXIT;
5123 return true;
5124 }
5125 }
5126
5127 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) {
5128 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5129 vcpu->arch.dr7,
5130 vcpu->arch.db);
5131
5132 if (dr6 != 0) {
5133 vcpu->arch.dr6 &= ~15;
5134 vcpu->arch.dr6 |= dr6;
5135 kvm_queue_exception(vcpu, DB_VECTOR);
5136 *r = EMULATE_DONE;
5137 return true;
5138 }
5139 }
5140
5141 return false;
5142}
5143
51d8b661
AP		 5144int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5145 unsigned long cr2,
dc25e89e
AP		 5146 int emulation_type,
5147 void *insn,
5148 int insn_len)
bbd9b64e 5149{
95cb2295 5150 int r;
9d74191a 5151 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5152 bool writeback = true;
93c05d3e 5153 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5154
93c05d3e
XG		 5155 /*
5156 * Clear write_fault_to_shadow_pgtable here to ensure it is
5157 * never reused.
5158 */
5159 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5160 kvm_clear_exception_queue(vcpu);
8d7d8102 5161
571008da 5162 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5163 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5164
5165 /*
5166 * We will reenter on the same instruction since
5167 * we do not set complete_userspace_io. This does not
5168 * handle watchpoints yet, those would be handled in
5169 * the emulate_ops.
5170 */
5171 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5172 return r;
5173
9d74191a
TY		 5174 ctxt->interruptibility = 0;
5175 ctxt->have_exception = false;
5176 ctxt->perm_ok = false;
bbd9b64e 5177
b51e974f 5178 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5179
9d74191a 5180 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5181
e46479f8 5182 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5183 ++vcpu->stat.insn_emulation;
1d2887e2 5184 if (r != EMULATION_OK) {
4005996e
AK		 5185 if (emulation_type & EMULTYPE_TRAP_UD)
5186 return EMULATE_FAIL;
991eebf9
GN		 5187 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5188 emulation_type))
bbd9b64e 5189 return EMULATE_DONE;
6d77dbfc
GN		 5190 if (emulation_type & EMULTYPE_SKIP)
5191 return EMULATE_FAIL;
5192 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5193 }
5194 }
5195
ba8afb6b 5196 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5197 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 5198 return EMULATE_DONE;
5199 }
5200
1cb3f3ae
XG		 5201 if (retry_instruction(ctxt, cr2, emulation_type))
5202 return EMULATE_DONE;
5203
7ae441ea 5204 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5205 changes registers values during IO operation */
7ae441ea
GN		 5206 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5207 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5208 emulator_invalidate_register_cache(ctxt);
7ae441ea 5209 }
4d2179e1 5210
5cd21917 5211restart:
9d74191a 5212 r = x86_emulate_insn(ctxt);
bbd9b64e 5213
775fde86
JR		 5214 if (r == EMULATION_INTERCEPTED)
5215 return EMULATE_DONE;
5216
d2ddd1c4 5217 if (r == EMULATION_FAILED) {
991eebf9
GN		 5218 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5219 emulation_type))
c3cd7ffa
GN		 5220 return EMULATE_DONE;
5221
6d77dbfc 5222 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5223 }
5224
9d74191a 5225 if (ctxt->have_exception) {
54b8486f 5226 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 5227 r = EMULATE_DONE;
5228 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5229 if (!vcpu->arch.pio.in) {
5230 /* FIXME: return into emulator if single-stepping. */
3457e419 5231 vcpu->arch.pio.count = 0;
0912c977 5232 } else {
7ae441ea 5233 writeback = false;
716d51ab
GN		 5234 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5235 }
ac0a48c3 5236 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5237 } else if (vcpu->mmio_needed) {
5238 if (!vcpu->mmio_is_write)
5239 writeback = false;
ac0a48c3 5240 r = EMULATE_USER_EXIT;
716d51ab 5241 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5242 } else if (r == EMULATION_RESTART)
5cd21917 5243 goto restart;
d2ddd1c4
GN		 5244 else
5245 r = EMULATE_DONE;
f850e2e6 5246
7ae441ea 5247 if (writeback) {
9d74191a 5248 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5249 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea 5250 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5251 kvm_rip_write(vcpu, ctxt->eip);
663f4c61
PB		 5252 if (r == EMULATE_DONE)
5253 kvm_vcpu_check_singlestep(vcpu, &r);
5254 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea
GN		 5255 } else
5256 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5257
5258 return r;
de7d789a 5259}
51d8b661 5260EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5261
cf8f70bf 5262int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5263{
cf8f70bf 5264 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5265 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5266 size, port, &val, 1);
cf8f70bf 5267 /* do not return to emulator after return from userspace */
7972995b 5268 vcpu->arch.pio.count = 0;
de7d789a
CO		 5269 return ret;
5270}
cf8f70bf 5271EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5272
8cfdc000
ZA		 5273static void tsc_bad(void *info)
5274{
0a3aee0d 5275 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5276}
5277
5278static void tsc_khz_changed(void *data)
c8076604 5279{
8cfdc000
ZA		 5280 struct cpufreq_freqs *freq = data;
5281 unsigned long khz = 0;
5282
5283 if (data)
5284 khz = freq->new;
5285 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5286 khz = cpufreq_quick_get(raw_smp_processor_id());
5287 if (!khz)
5288 khz = tsc_khz;
0a3aee0d 5289 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5290}
5291
c8076604
GH		 5292static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5293 void *data)
5294{
5295 struct cpufreq_freqs *freq = data;
5296 struct kvm *kvm;
5297 struct kvm_vcpu *vcpu;
5298 int i, send_ipi = 0;
5299
8cfdc000
ZA		 5300 /*
5301 * We allow guests to temporarily run on slowing clocks,
5302 * provided we notify them after, or to run on accelerating
5303 * clocks, provided we notify them before. Thus time never
5304 * goes backwards.
5305 *
5306 * However, we have a problem. We can't atomically update
5307 * the frequency of a given CPU from this function; it is
5308 * merely a notifier, which can be called from any CPU.
5309 * Changing the TSC frequency at arbitrary points in time
5310 * requires a recomputation of local variables related to
5311 * the TSC for each VCPU. We must flag these local variables
5312 * to be updated and be sure the update takes place with the
5313 * new frequency before any guests proceed.
5314 *
5315 * Unfortunately, the combination of hotplug CPU and frequency
5316 * change creates an intractable locking scenario; the order
5317 * of when these callouts happen is undefined with respect to
5318 * CPU hotplug, and they can race with each other. As such,
5319 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5320 * undefined; you can actually have a CPU frequency change take
5321 * place in between the computation of X and the setting of the
5322 * variable. To protect against this problem, all updates of
5323 * the per_cpu tsc_khz variable are done in an interrupt
5324 * protected IPI, and all callers wishing to update the value
5325 * must wait for a synchronous IPI to complete (which is trivial
5326 * if the caller is on the CPU already). This establishes the
5327 * necessary total order on variable updates.
5328 *
5329 * Note that because a guest time update may take place
5330 * anytime after the setting of the VCPU's request bit, the
5331 * correct TSC value must be set before the request. However,
5332 * to ensure the update actually makes it to any guest which
5333 * starts running in hardware virtualization between the set
5334 * and the acquisition of the spinlock, we must also ping the
5335 * CPU after setting the request bit.
5336 *
5337 */
5338
c8076604
GH		 5339 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5340 return 0;
5341 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5342 return 0;
8cfdc000
ZA		 5343
5344 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5345
2f303b74 5346 spin_lock(&kvm_lock);
c8076604 5347 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5348 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5349 if (vcpu->cpu != freq->cpu)
5350 continue;
c285545f 5351 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5352 if (vcpu->cpu != smp_processor_id())
8cfdc000 5353 send_ipi = 1;
c8076604
GH		 5354 }
5355 }
2f303b74 5356 spin_unlock(&kvm_lock);
c8076604
GH		 5357
5358 if (freq->old < freq->new && send_ipi) {
5359 /*
5360 * We upscale the frequency. Must make the guest
5361 * doesn't see old kvmclock values while running with
5362 * the new frequency, otherwise we risk the guest sees
5363 * time go backwards.
5364 *
5365 * In case we update the frequency for another cpu
5366 * (which might be in guest context) send an interrupt
5367 * to kick the cpu out of guest context. Next time
5368 * guest context is entered kvmclock will be updated,
5369 * so the guest will not see stale values.
5370 */
8cfdc000 5371 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5372 }
5373 return 0;
5374}
5375
5376static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5377 .notifier_call = kvmclock_cpufreq_notifier
5378};
5379
5380static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5381 unsigned long action, void *hcpu)
5382{
5383 unsigned int cpu = (unsigned long)hcpu;
5384
5385 switch (action) {
5386 case CPU_ONLINE:
5387 case CPU_DOWN_FAILED:
5388 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5389 break;
5390 case CPU_DOWN_PREPARE:
5391 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5392 break;
5393 }
5394 return NOTIFY_OK;
5395}
5396
5397static struct notifier_block kvmclock_cpu_notifier_block = {
5398 .notifier_call = kvmclock_cpu_notifier,
5399 .priority = -INT_MAX
c8076604
GH		 5400};
5401
b820cc0c
ZA		 5402static void kvm_timer_init(void)
5403{
5404 int cpu;
5405
c285545f 5406 max_tsc_khz = tsc_khz;
8cfdc000 5407 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 5408 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5409#ifdef CONFIG_CPU_FREQ
5410 struct cpufreq_policy policy;
5411 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5412 cpu = get_cpu();
5413 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5414 if (policy.cpuinfo.max_freq)
5415 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5416 put_cpu();
c285545f 5417#endif
b820cc0c
ZA		 5418 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5419 CPUFREQ_TRANSITION_NOTIFIER);
5420 }
c285545f 5421 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5422 for_each_online_cpu(cpu)
5423 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 5424}
5425
ff9d07a0
ZY		 5426static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5427
f5132b01 5428int kvm_is_in_guest(void)
ff9d07a0 5429{
086c9855 5430 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5431}
5432
5433static int kvm_is_user_mode(void)
5434{
5435 int user_mode = 3;
dcf46b94 5436
086c9855
AS		 5437 if (__this_cpu_read(current_vcpu))
5438 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5439
ff9d07a0
ZY		 5440 return user_mode != 0;
5441}
5442
5443static unsigned long kvm_get_guest_ip(void)
5444{
5445 unsigned long ip = 0;
dcf46b94 5446
086c9855
AS		 5447 if (__this_cpu_read(current_vcpu))
5448 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5449
ff9d07a0
ZY		 5450 return ip;
5451}
5452
5453static struct perf_guest_info_callbacks kvm_guest_cbs = {
5454 .is_in_guest = kvm_is_in_guest,
5455 .is_user_mode = kvm_is_user_mode,
5456 .get_guest_ip = kvm_get_guest_ip,
5457};
5458
5459void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5460{
086c9855 5461 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5462}
5463EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5464
5465void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5466{
086c9855 5467 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5468}
5469EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5470
ce88decf
XG		 5471static void kvm_set_mmio_spte_mask(void)
5472{
5473 u64 mask;
5474 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5475
5476 /*
5477 * Set the reserved bits and the present bit of an paging-structure
5478 * entry to generate page fault with PFER.RSV = 1.
5479 */
885032b9
XG		 5480 /* Mask the reserved physical address bits. */
5481 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5482
5483 /* Bit 62 is always reserved for 32bit host. */
5484 mask |= 0x3ull << 62;
5485
5486 /* Set the present bit. */
ce88decf
XG		 5487 mask |= 1ull;
5488
5489#ifdef CONFIG_X86_64
5490 /*
5491 * If reserved bit is not supported, clear the present bit to disable
5492 * mmio page fault.
5493 */
5494 if (maxphyaddr == 52)
5495 mask &= ~1ull;
5496#endif
5497
5498 kvm_mmu_set_mmio_spte_mask(mask);
5499}
5500
16e8d74d
MT		 5501#ifdef CONFIG_X86_64
5502static void pvclock_gtod_update_fn(struct work_struct *work)
5503{
d828199e
MT		 5504 struct kvm *kvm;
5505
5506 struct kvm_vcpu *vcpu;
5507 int i;
5508
2f303b74 5509 spin_lock(&kvm_lock);
d828199e
MT		 5510 list_for_each_entry(kvm, &vm_list, vm_list)
5511 kvm_for_each_vcpu(i, vcpu, kvm)
5512 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5513 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5514 spin_unlock(&kvm_lock);
16e8d74d
MT		 5515}
5516
5517static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5518
5519/*
5520 * Notification about pvclock gtod data update.
5521 */
5522static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5523 void *priv)
5524{
5525 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5526 struct timekeeper *tk = priv;
5527
5528 update_pvclock_gtod(tk);
5529
5530 /* disable master clock if host does not trust, or does not
5531 * use, TSC clocksource
5532 */
5533 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5534 atomic_read(&kvm_guest_has_master_clock) != 0)
5535 queue_work(system_long_wq, &pvclock_gtod_work);
5536
5537 return 0;
5538}
5539
5540static struct notifier_block pvclock_gtod_notifier = {
5541 .notifier_call = pvclock_gtod_notify,
5542};
5543#endif
5544
f8c16bba 5545int kvm_arch_init(void *opaque)
043405e1 5546{
b820cc0c 5547 int r;
6b61edf7 5548 struct kvm_x86_ops *ops = opaque;
f8c16bba 5549
f8c16bba
ZX		 5550 if (kvm_x86_ops) {
5551 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5552 r = -EEXIST;
5553 goto out;
f8c16bba
ZX		 5554 }
5555
5556 if (!ops->cpu_has_kvm_support()) {
5557 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5558 r = -EOPNOTSUPP;
5559 goto out;
f8c16bba
ZX		 5560 }
5561 if (ops->disabled_by_bios()) {
5562 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5563 r = -EOPNOTSUPP;
5564 goto out;
f8c16bba
ZX		 5565 }
5566
013f6a5d
MT		 5567 r = -ENOMEM;
5568 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5569 if (!shared_msrs) {
5570 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5571 goto out;
5572 }
5573
97db56ce
AK		 5574 r = kvm_mmu_module_init();
5575 if (r)
013f6a5d 5576 goto out_free_percpu;
97db56ce 5577
ce88decf 5578 kvm_set_mmio_spte_mask();
97db56ce
AK		 5579 kvm_init_msr_list();
5580
f8c16bba 5581 kvm_x86_ops = ops;
7b52345e 5582 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5583 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5584
b820cc0c 5585 kvm_timer_init();
c8076604 5586
ff9d07a0
ZY		 5587 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5588
2acf923e
DC		 5589 if (cpu_has_xsave)
5590 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5591
c5cc421b 5592 kvm_lapic_init();
16e8d74d
MT		 5593#ifdef CONFIG_X86_64
5594 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5595#endif
5596
f8c16bba 5597 return 0;
56c6d28a 5598
013f6a5d
MT		 5599out_free_percpu:
5600 free_percpu(shared_msrs);
56c6d28a 5601out:
56c6d28a 5602 return r;
043405e1 5603}
8776e519 5604
f8c16bba
ZX		 5605void kvm_arch_exit(void)
5606{
ff9d07a0
ZY		 5607 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5608
888d256e
JK		 5609 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5610 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5611 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5612 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5613#ifdef CONFIG_X86_64
5614 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5615#endif
f8c16bba 5616 kvm_x86_ops = NULL;
56c6d28a 5617 kvm_mmu_module_exit();
013f6a5d 5618 free_percpu(shared_msrs);
56c6d28a 5619}
f8c16bba 5620
8776e519
HB		 5621int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5622{
5623 ++vcpu->stat.halt_exits;
5624 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5625 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5626 return 1;
5627 } else {
5628 vcpu->run->exit_reason = KVM_EXIT_HLT;
5629 return 0;
5630 }
5631}
5632EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5633
55cd8e5a
GN		 5634int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5635{
5636 u64 param, ingpa, outgpa, ret;
5637 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5638 bool fast, longmode;
5639 int cs_db, cs_l;
5640
5641 /*
5642 * hypercall generates UD from non zero cpl and real mode
5643 * per HYPER-V spec
5644 */
3eeb3288 5645 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5646 kvm_queue_exception(vcpu, UD_VECTOR);
5647 return 0;
5648 }
5649
5650 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5651 longmode = is_long_mode(vcpu) && cs_l == 1;
5652
5653 if (!longmode) {
ccd46936
GN		 5654 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5655 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5656 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5657 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5658 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5659 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5660 }
5661#ifdef CONFIG_X86_64
5662 else {
5663 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5664 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5665 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5666 }
5667#endif
5668
5669 code = param & 0xffff;
5670 fast = (param >> 16) & 0x1;
5671 rep_cnt = (param >> 32) & 0xfff;
5672 rep_idx = (param >> 48) & 0xfff;
5673
5674 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5675
c25bc163
GN		 5676 switch (code) {
5677 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5678 kvm_vcpu_on_spin(vcpu);
5679 break;
5680 default:
5681 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5682 break;
5683 }
55cd8e5a
GN		 5684
5685 ret = res | (((u64)rep_done & 0xfff) << 32);
5686 if (longmode) {
5687 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5688 } else {
5689 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5690 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5691 }
5692
5693 return 1;
5694}
5695
6aef266c
SV		 5696/*
5697 * kvm_pv_kick_cpu_op: Kick a vcpu.
5698 *
5699 * @apicid - apicid of vcpu to be kicked.
5700 */
5701static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5702{
24d2166b 5703 struct kvm_lapic_irq lapic_irq;
6aef266c 5704
24d2166b
R		 5705 lapic_irq.shorthand = 0;
5706 lapic_irq.dest_mode = 0;
5707 lapic_irq.dest_id = apicid;
6aef266c 5708
24d2166b
R		 5709 lapic_irq.delivery_mode = APIC_DM_REMRD;
5710 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
6aef266c
SV		 5711}
5712
8776e519
HB		 5713int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5714{
5715 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5716 int r = 1;
8776e519 5717
55cd8e5a
GN		 5718 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5719 return kvm_hv_hypercall(vcpu);
5720
5fdbf976
MT		 5721 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5722 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5723 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5724 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5725 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5726
229456fc 5727 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5728
8776e519
HB		 5729 if (!is_long_mode(vcpu)) {
5730 nr &= 0xFFFFFFFF;
5731 a0 &= 0xFFFFFFFF;
5732 a1 &= 0xFFFFFFFF;
5733 a2 &= 0xFFFFFFFF;
5734 a3 &= 0xFFFFFFFF;
5735 }
5736
07708c4a
JK		 5737 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5738 ret = -KVM_EPERM;
5739 goto out;
5740 }
5741
8776e519 5742 switch (nr) {
b93463aa
AK		 5743 case KVM_HC_VAPIC_POLL_IRQ:
5744 ret = 0;
5745 break;
6aef266c
SV		 5746 case KVM_HC_KICK_CPU:
5747 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5748 ret = 0;
5749 break;
8776e519
HB		 5750 default:
5751 ret = -KVM_ENOSYS;
5752 break;
5753 }
07708c4a 5754out:
5fdbf976 5755 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5756 ++vcpu->stat.hypercalls;
2f333bcb 5757 return r;
8776e519
HB		 5758}
5759EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5760
b6785def 5761static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5762{
d6aa1000 5763 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5764 char instruction[3];
5fdbf976 5765 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5766
8776e519 5767 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5768
9d74191a 5769 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5770}
5771
b6c7a5dc
HB		 5772/*
5773 * Check if userspace requested an interrupt window, and that the
5774 * interrupt window is open.
5775 *
5776 * No need to exit to userspace if we already have an interrupt queued.
5777 */
851ba692 5778static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5779{
8061823a 5780 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5781 vcpu->run->request_interrupt_window &&
5df56646 5782 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5783}
5784
851ba692 5785static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5786{
851ba692
AK		 5787 struct kvm_run *kvm_run = vcpu->run;
5788
91586a3b 5789 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5790 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5791 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5792 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5793 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5794 else
b6c7a5dc 5795 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5796 kvm_arch_interrupt_allowed(vcpu) &&
5797 !kvm_cpu_has_interrupt(vcpu) &&
5798 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5799}
5800
95ba8273
GN		 5801static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5802{
5803 int max_irr, tpr;
5804
5805 if (!kvm_x86_ops->update_cr8_intercept)
5806 return;
5807
88c808fd
AK		 5808 if (!vcpu->arch.apic)
5809 return;
5810
8db3baa2
GN		 5811 if (!vcpu->arch.apic->vapic_addr)
5812 max_irr = kvm_lapic_find_highest_irr(vcpu);
5813 else
5814 max_irr = -1;
95ba8273
GN		 5815
5816 if (max_irr != -1)
5817 max_irr >>= 4;
5818
5819 tpr = kvm_lapic_get_cr8(vcpu);
5820
5821 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5822}
5823
b6b8a145 5824static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 5825{
b6b8a145
JK		 5826 int r;
5827
95ba8273 5828 /* try to reinject previous events if any */
b59bb7bd 5829 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5830 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5831 vcpu->arch.exception.has_error_code,
5832 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5833 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5834 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5835 vcpu->arch.exception.error_code,
5836 vcpu->arch.exception.reinject);
b6b8a145 5837 return 0;
b59bb7bd
GN		 5838 }
5839
95ba8273
GN		 5840 if (vcpu->arch.nmi_injected) {
5841 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 5842 return 0;
95ba8273
GN		 5843 }
5844
5845 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5846 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 5847 return 0;
5848 }
5849
5850 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5851 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5852 if (r != 0)
5853 return r;
95ba8273
GN		 5854 }
5855
5856 /* try to inject new event if pending */
5857 if (vcpu->arch.nmi_pending) {
5858 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5859 --vcpu->arch.nmi_pending;
95ba8273
GN		 5860 vcpu->arch.nmi_injected = true;
5861 kvm_x86_ops->set_nmi(vcpu);
5862 }
c7c9c56c 5863 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
95ba8273 5864 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5865 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5866 false);
5867 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5868 }
5869 }
b6b8a145 5870 return 0;
95ba8273
GN		 5871}
5872
7460fb4a
AK		 5873static void process_nmi(struct kvm_vcpu *vcpu)
5874{
5875 unsigned limit = 2;
5876
5877 /*
5878 * x86 is limited to one NMI running, and one NMI pending after it.
5879 * If an NMI is already in progress, limit further NMIs to just one.
5880 * Otherwise, allow two (and we'll inject the first one immediately).
5881 */
5882 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5883 limit = 1;
5884
5885 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5886 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5887 kvm_make_request(KVM_REQ_EVENT, vcpu);
5888}
5889
3d81bc7e 5890static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 5891{
5892 u64 eoi_exit_bitmap[4];
cf9e65b7 5893 u32 tmr[8];
c7c9c56c 5894
3d81bc7e
YZ		 5895 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5896 return;
c7c9c56c
YZ		 5897
5898 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 5899 memset(tmr, 0, 32);
c7c9c56c 5900
cf9e65b7 5901 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 5902 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 5903 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 5904}
5905
9357d939
TY		 5906/*
5907 * Returns 1 to let __vcpu_run() continue the guest execution loop without
5908 * exiting to the userspace. Otherwise, the value will be returned to the
5909 * userspace.
5910 */
851ba692 5911static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5912{
5913 int r;
6a8b1d13 5914 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5915 vcpu->run->request_interrupt_window;
730dca42 5916 bool req_immediate_exit = false;
b6c7a5dc 5917
3e007509 5918 if (vcpu->requests) {
a8eeb04a 5919 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5920 kvm_mmu_unload(vcpu);
a8eeb04a 5921 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5922 __kvm_migrate_timers(vcpu);
d828199e
MT		 5923 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5924 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 5925 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5926 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 5927 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5928 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5929 if (unlikely(r))
5930 goto out;
5931 }
a8eeb04a 5932 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5933 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5934 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5935 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5936 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5937 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5938 r = 0;
5939 goto out;
5940 }
a8eeb04a 5941 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5942 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5943 r = 0;
5944 goto out;
5945 }
a8eeb04a 5946 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5947 vcpu->fpu_active = 0;
5948 kvm_x86_ops->fpu_deactivate(vcpu);
5949 }
af585b92
GN		 5950 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5951 /* Page is swapped out. Do synthetic halt */
5952 vcpu->arch.apf.halted = true;
5953 r = 1;
5954 goto out;
5955 }
c9aaa895
GC		 5956 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5957 record_steal_time(vcpu);
7460fb4a
AK		 5958 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5959 process_nmi(vcpu);
f5132b01
GN		 5960 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5961 kvm_handle_pmu_event(vcpu);
5962 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5963 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 5964 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5965 vcpu_scan_ioapic(vcpu);
2f52d58c 5966 }
b93463aa 5967
b463a6f7 5968 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 5969 kvm_apic_accept_events(vcpu);
5970 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5971 r = 1;
5972 goto out;
5973 }
5974
b6b8a145
JK		 5975 if (inject_pending_event(vcpu, req_int_win) != 0)
5976 req_immediate_exit = true;
b463a6f7 5977 /* enable NMI/IRQ window open exits if needed */
b6b8a145 5978 else if (vcpu->arch.nmi_pending)
c9a7953f 5979 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 5980 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 5981 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 5982
5983 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 5984 /*
5985 * Update architecture specific hints for APIC
5986 * virtual interrupt delivery.
5987 */
5988 if (kvm_x86_ops->hwapic_irr_update)
5989 kvm_x86_ops->hwapic_irr_update(vcpu,
5990 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 5991 update_cr8_intercept(vcpu);
5992 kvm_lapic_sync_to_vapic(vcpu);
5993 }
5994 }
5995
d8368af8
AK		 5996 r = kvm_mmu_reload(vcpu);
5997 if (unlikely(r)) {
d905c069 5998 goto cancel_injection;
d8368af8
AK		 5999 }
6000
b6c7a5dc
HB		 6001 preempt_disable();
6002
6003 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6004 if (vcpu->fpu_active)
6005 kvm_load_guest_fpu(vcpu);
2acf923e 6006 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6007
6b7e2d09
XG		 6008 vcpu->mode = IN_GUEST_MODE;
6009
01b71917
MT		 6010 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6011
6b7e2d09
XG		 6012 /* We should set ->mode before check ->requests,
6013 * see the comment in make_all_cpus_request.
6014 */
01b71917 6015 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6016
d94e1dc9 6017 local_irq_disable();
32f88400 6018
6b7e2d09 6019 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6020 || need_resched() || signal_pending(current)) {
6b7e2d09 6021 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6022 smp_wmb();
6c142801
AK		 6023 local_irq_enable();
6024 preempt_enable();
01b71917 6025 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6026 r = 1;
d905c069 6027 goto cancel_injection;
6c142801
AK		 6028 }
6029
d6185f20
NHE		 6030 if (req_immediate_exit)
6031 smp_send_reschedule(vcpu->cpu);
6032
b6c7a5dc
HB		 6033 kvm_guest_enter();
6034
42dbaa5a 6035 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6036 set_debugreg(0, 7);
6037 set_debugreg(vcpu->arch.eff_db[0], 0);
6038 set_debugreg(vcpu->arch.eff_db[1], 1);
6039 set_debugreg(vcpu->arch.eff_db[2], 2);
6040 set_debugreg(vcpu->arch.eff_db[3], 3);
6041 }
b6c7a5dc 6042
229456fc 6043 trace_kvm_entry(vcpu->vcpu_id);
851ba692 6044 kvm_x86_ops->run(vcpu);
b6c7a5dc 6045
24f1e32c
FW		 6046 /*
6047 * If the guest has used debug registers, at least dr7
6048 * will be disabled while returning to the host.
6049 * If we don't have active breakpoints in the host, we don't
6050 * care about the messed up debug address registers. But if
6051 * we have some of them active, restore the old state.
6052 */
59d8eb53 6053 if (hw_breakpoint_active())
24f1e32c 6054 hw_breakpoint_restore();
42dbaa5a 6055
886b470c
MT		 6056 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6057 native_read_tsc());
1d5f066e 6058
6b7e2d09 6059 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6060 smp_wmb();
a547c6db
YZ		 6061
6062 /* Interrupt is enabled by handle_external_intr() */
6063 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6064
6065 ++vcpu->stat.exits;
6066
6067 /*
6068 * We must have an instruction between local_irq_enable() and
6069 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6070 * the interrupt shadow. The stat.exits increment will do nicely.
6071 * But we need to prevent reordering, hence this barrier():
6072 */
6073 barrier();
6074
6075 kvm_guest_exit();
6076
6077 preempt_enable();
6078
f656ce01 6079 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6080
b6c7a5dc
HB		 6081 /*
6082 * Profile KVM exit RIPs:
6083 */
6084 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6085 unsigned long rip = kvm_rip_read(vcpu);
6086 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6087 }
6088
cc578287
ZA		 6089 if (unlikely(vcpu->arch.tsc_always_catchup))
6090 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6091
5cfb1d5a
MT		 6092 if (vcpu->arch.apic_attention)
6093 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6094
851ba692 6095 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6096 return r;
6097
6098cancel_injection:
6099 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6100 if (unlikely(vcpu->arch.apic_attention))
6101 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6102out:
6103 return r;
6104}
b6c7a5dc 6105
09cec754 6106
851ba692 6107static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6108{
6109 int r;
f656ce01 6110 struct kvm *kvm = vcpu->kvm;
d7690175 6111
f656ce01 6112 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 6113
6114 r = 1;
6115 while (r > 0) {
af585b92
GN		 6116 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6117 !vcpu->arch.apf.halted)
851ba692 6118 r = vcpu_enter_guest(vcpu);
d7690175 6119 else {
f656ce01 6120 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6121 kvm_vcpu_block(vcpu);
f656ce01 6122 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6123 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6124 kvm_apic_accept_events(vcpu);
09cec754
GN		 6125 switch(vcpu->arch.mp_state) {
6126 case KVM_MP_STATE_HALTED:
6aef266c 6127 vcpu->arch.pv.pv_unhalted = false;
d7690175 6128 vcpu->arch.mp_state =
09cec754
GN		 6129 KVM_MP_STATE_RUNNABLE;
6130 case KVM_MP_STATE_RUNNABLE:
af585b92 6131 vcpu->arch.apf.halted = false;
09cec754 6132 break;
66450a21
JK		 6133 case KVM_MP_STATE_INIT_RECEIVED:
6134 break;
09cec754
GN		 6135 default:
6136 r = -EINTR;
6137 break;
6138 }
6139 }
d7690175
MT		 6140 }
6141
09cec754
GN		 6142 if (r <= 0)
6143 break;
6144
6145 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6146 if (kvm_cpu_has_pending_timer(vcpu))
6147 kvm_inject_pending_timer_irqs(vcpu);
6148
851ba692 6149 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6150 r = -EINTR;
851ba692 6151 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6152 ++vcpu->stat.request_irq_exits;
6153 }
af585b92
GN		 6154
6155 kvm_check_async_pf_completion(vcpu);
6156
09cec754
GN		 6157 if (signal_pending(current)) {
6158 r = -EINTR;
851ba692 6159 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6160 ++vcpu->stat.signal_exits;
6161 }
6162 if (need_resched()) {
f656ce01 6163 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6164 cond_resched();
f656ce01 6165 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6166 }
b6c7a5dc
HB		 6167 }
6168
f656ce01 6169 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6170
6171 return r;
6172}
6173
716d51ab
GN		 6174static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6175{
6176 int r;
6177 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6178 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6179 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6180 if (r != EMULATE_DONE)
6181 return 0;
6182 return 1;
6183}
6184
6185static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6186{
6187 BUG_ON(!vcpu->arch.pio.count);
6188
6189 return complete_emulated_io(vcpu);
6190}
6191
f78146b0
AK		 6192/*
6193 * Implements the following, as a state machine:
6194 *
6195 * read:
6196 * for each fragment
87da7e66
XG		 6197 * for each mmio piece in the fragment
6198 * write gpa, len
6199 * exit
6200 * copy data
f78146b0
AK		 6201 * execute insn
6202 *
6203 * write:
6204 * for each fragment
87da7e66
XG		 6205 * for each mmio piece in the fragment
6206 * write gpa, len
6207 * copy data
6208 * exit
f78146b0 6209 */
716d51ab 6210static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6211{
6212 struct kvm_run *run = vcpu->run;
f78146b0 6213 struct kvm_mmio_fragment *frag;
87da7e66 6214 unsigned len;
5287f194 6215
716d51ab 6216 BUG_ON(!vcpu->mmio_needed);
5287f194 6217
716d51ab 6218 /* Complete previous fragment */
87da7e66
XG		 6219 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6220 len = min(8u, frag->len);
716d51ab 6221 if (!vcpu->mmio_is_write)
87da7e66
XG		 6222 memcpy(frag->data, run->mmio.data, len);
6223
6224 if (frag->len <= 8) {
6225 /* Switch to the next fragment. */
6226 frag++;
6227 vcpu->mmio_cur_fragment++;
6228 } else {
6229 /* Go forward to the next mmio piece. */
6230 frag->data += len;
6231 frag->gpa += len;
6232 frag->len -= len;
6233 }
6234
a08d3b3b 6235 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6236 vcpu->mmio_needed = 0;
0912c977
PB		 6237
6238 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6239 if (vcpu->mmio_is_write)
716d51ab
GN		 6240 return 1;
6241 vcpu->mmio_read_completed = 1;
6242 return complete_emulated_io(vcpu);
6243 }
87da7e66 6244
716d51ab
GN		 6245 run->exit_reason = KVM_EXIT_MMIO;
6246 run->mmio.phys_addr = frag->gpa;
6247 if (vcpu->mmio_is_write)
87da7e66
XG		 6248 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6249 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6250 run->mmio.is_write = vcpu->mmio_is_write;
6251 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6252 return 0;
5287f194
AK		 6253}
6254
716d51ab 6255
b6c7a5dc
HB		 6256int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6257{
6258 int r;
6259 sigset_t sigsaved;
6260
e5c30142
AK		 6261 if (!tsk_used_math(current) && init_fpu(current))
6262 return -ENOMEM;
6263
ac9f6dc0
AK		 6264 if (vcpu->sigset_active)
6265 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6266
a4535290 6267 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6268 kvm_vcpu_block(vcpu);
66450a21 6269 kvm_apic_accept_events(vcpu);
d7690175 6270 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6271 r = -EAGAIN;
6272 goto out;
b6c7a5dc
HB		 6273 }
6274
b6c7a5dc 6275 /* re-sync apic's tpr */
eea1cff9
AP		 6276 if (!irqchip_in_kernel(vcpu->kvm)) {
6277 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6278 r = -EINVAL;
6279 goto out;
6280 }
6281 }
b6c7a5dc 6282
716d51ab
GN		 6283 if (unlikely(vcpu->arch.complete_userspace_io)) {
6284 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6285 vcpu->arch.complete_userspace_io = NULL;
6286 r = cui(vcpu);
6287 if (r <= 0)
6288 goto out;
6289 } else
6290 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6291
851ba692 6292 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6293
6294out:
f1d86e46 6295 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6296 if (vcpu->sigset_active)
6297 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6298
b6c7a5dc
HB		 6299 return r;
6300}
6301
6302int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6303{
7ae441ea
GN		 6304 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6305 /*
6306 * We are here if userspace calls get_regs() in the middle of
6307 * instruction emulation. Registers state needs to be copied
4a969980 6308 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6309 * that usually, but some bad designed PV devices (vmware
6310 * backdoor interface) need this to work
6311 */
dd856efa 6312 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6313 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6314 }
5fdbf976
MT		 6315 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6316 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6317 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6318 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6319 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6320 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6321 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6322 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6323#ifdef CONFIG_X86_64
5fdbf976
MT		 6324 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6325 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6326 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6327 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6328 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6329 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6330 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6331 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6332#endif
6333
5fdbf976 6334 regs->rip = kvm_rip_read(vcpu);
91586a3b 6335 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6336
b6c7a5dc
HB		 6337 return 0;
6338}
6339
6340int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6341{
7ae441ea
GN		 6342 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6343 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6344
5fdbf976
MT		 6345 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6346 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6347 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6348 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6349 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6350 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6351 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6352 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6353#ifdef CONFIG_X86_64
5fdbf976
MT		 6354 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6355 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6356 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6357 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6358 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6359 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6360 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6361 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6362#endif
6363
5fdbf976 6364 kvm_rip_write(vcpu, regs->rip);
91586a3b 6365 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6366
b4f14abd
JK		 6367 vcpu->arch.exception.pending = false;
6368
3842d135
AK		 6369 kvm_make_request(KVM_REQ_EVENT, vcpu);
6370
b6c7a5dc
HB		 6371 return 0;
6372}
6373
b6c7a5dc
HB		 6374void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6375{
6376 struct kvm_segment cs;
6377
3e6e0aab 6378 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6379 *db = cs.db;
6380 *l = cs.l;
6381}
6382EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6383
6384int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6385 struct kvm_sregs *sregs)
6386{
89a27f4d 6387 struct desc_ptr dt;
b6c7a5dc 6388
3e6e0aab
GT		 6389 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6390 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6391 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6392 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6393 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6394 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6395
3e6e0aab
GT		 6396 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6397 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6398
6399 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6400 sregs->idt.limit = dt.size;
6401 sregs->idt.base = dt.address;
b6c7a5dc 6402 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6403 sregs->gdt.limit = dt.size;
6404 sregs->gdt.base = dt.address;
b6c7a5dc 6405
4d4ec087 6406 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6407 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6408 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6409 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6410 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6411 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6412 sregs->apic_base = kvm_get_apic_base(vcpu);
6413
923c61bb 6414 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6415
36752c9b 6416 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6417 set_bit(vcpu->arch.interrupt.nr,
6418 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6419
b6c7a5dc
HB		 6420 return 0;
6421}
6422
62d9f0db
MT		 6423int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6424 struct kvm_mp_state *mp_state)
6425{
66450a21 6426 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6427 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6428 vcpu->arch.pv.pv_unhalted)
6429 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6430 else
6431 mp_state->mp_state = vcpu->arch.mp_state;
6432
62d9f0db
MT		 6433 return 0;
6434}
6435
6436int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6437 struct kvm_mp_state *mp_state)
6438{
66450a21
JK		 6439 if (!kvm_vcpu_has_lapic(vcpu) &&
6440 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6441 return -EINVAL;
6442
6443 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6444 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6445 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6446 } else
6447 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6448 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6449 return 0;
6450}
6451
7f3d35fd
KW		 6452int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6453 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6454{
9d74191a 6455 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6456 int ret;
e01c2426 6457
8ec4722d 6458 init_emulate_ctxt(vcpu);
c697518a 6459
7f3d35fd 6460 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6461 has_error_code, error_code);
c697518a 6462
c697518a 6463 if (ret)
19d04437 6464 return EMULATE_FAIL;
37817f29 6465
9d74191a
TY		 6466 kvm_rip_write(vcpu, ctxt->eip);
6467 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6468 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6469 return EMULATE_DONE;
37817f29
IE		 6470}
6471EXPORT_SYMBOL_GPL(kvm_task_switch);
6472
b6c7a5dc
HB		 6473int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6474 struct kvm_sregs *sregs)
6475{
58cb628d 6476 struct msr_data apic_base_msr;
b6c7a5dc 6477 int mmu_reset_needed = 0;
63f42e02 6478 int pending_vec, max_bits, idx;
89a27f4d 6479 struct desc_ptr dt;
b6c7a5dc 6480
6d1068b3
PM		 6481 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6482 return -EINVAL;
6483
89a27f4d
GN		 6484 dt.size = sregs->idt.limit;
6485 dt.address = sregs->idt.base;
b6c7a5dc 6486 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6487 dt.size = sregs->gdt.limit;
6488 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6489 kvm_x86_ops->set_gdt(vcpu, &dt);
6490
ad312c7c 6491 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6492 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6493 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6494 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6495
2d3ad1f4 6496 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6497
f6801dff 6498 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6499 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6500 apic_base_msr.data = sregs->apic_base;
6501 apic_base_msr.host_initiated = true;
6502 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6503
4d4ec087 6504 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6505 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6506 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6507
fc78f519 6508 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6509 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6510 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6511 kvm_update_cpuid(vcpu);
63f42e02
XG		 6512
6513 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6514 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6515 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6516 mmu_reset_needed = 1;
6517 }
63f42e02 6518 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6519
6520 if (mmu_reset_needed)
6521 kvm_mmu_reset_context(vcpu);
6522
a50abc3b 6523 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6524 pending_vec = find_first_bit(
6525 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6526 if (pending_vec < max_bits) {
66fd3f7f 6527 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6528 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6529 }
6530
3e6e0aab
GT		 6531 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6532 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6533 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6534 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6535 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6536 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6537
3e6e0aab
GT		 6538 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6539 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6540
5f0269f5
ME		 6541 update_cr8_intercept(vcpu);
6542
9c3e4aab 6543 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6544 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6545 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6546 !is_protmode(vcpu))
9c3e4aab
MT		 6547 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6548
3842d135
AK		 6549 kvm_make_request(KVM_REQ_EVENT, vcpu);
6550
b6c7a5dc
HB		 6551 return 0;
6552}
6553
d0bfb940
JK		 6554int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6555 struct kvm_guest_debug *dbg)
b6c7a5dc 6556{
355be0b9 6557 unsigned long rflags;
ae675ef0 6558 int i, r;
b6c7a5dc 6559
4f926bf2
JK		 6560 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6561 r = -EBUSY;
6562 if (vcpu->arch.exception.pending)
2122ff5e 6563 goto out;
4f926bf2
JK		 6564 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6565 kvm_queue_exception(vcpu, DB_VECTOR);
6566 else
6567 kvm_queue_exception(vcpu, BP_VECTOR);
6568 }
6569
91586a3b
JK		 6570 /*
6571 * Read rflags as long as potentially injected trace flags are still
6572 * filtered out.
6573 */
6574 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6575
6576 vcpu->guest_debug = dbg->control;
6577 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6578 vcpu->guest_debug = 0;
6579
6580 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6581 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6582 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6583 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6584 } else {
6585 for (i = 0; i < KVM_NR_DB_REGS; i++)
6586 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6587 }
c8639010 6588 kvm_update_dr7(vcpu);
ae675ef0 6589
f92653ee
JK		 6590 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6591 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6592 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6593
91586a3b
JK		 6594 /*
6595 * Trigger an rflags update that will inject or remove the trace
6596 * flags.
6597 */
6598 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6599
c8639010 6600 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6601
4f926bf2 6602 r = 0;
d0bfb940 6603
2122ff5e 6604out:
b6c7a5dc
HB		 6605
6606 return r;
6607}
6608
8b006791
ZX		 6609/*
6610 * Translate a guest virtual address to a guest physical address.
6611 */
6612int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6613 struct kvm_translation *tr)
6614{
6615 unsigned long vaddr = tr->linear_address;
6616 gpa_t gpa;
f656ce01 6617 int idx;
8b006791 6618
f656ce01 6619 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6620 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6621 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6622 tr->physical_address = gpa;
6623 tr->valid = gpa != UNMAPPED_GVA;
6624 tr->writeable = 1;
6625 tr->usermode = 0;
8b006791
ZX		 6626
6627 return 0;
6628}
6629
d0752060
HB		 6630int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6631{
98918833
SY		 6632 struct i387_fxsave_struct *fxsave =
6633 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6634
d0752060
HB		 6635 memcpy(fpu->fpr, fxsave->st_space, 128);
6636 fpu->fcw = fxsave->cwd;
6637 fpu->fsw = fxsave->swd;
6638 fpu->ftwx = fxsave->twd;
6639 fpu->last_opcode = fxsave->fop;
6640 fpu->last_ip = fxsave->rip;
6641 fpu->last_dp = fxsave->rdp;
6642 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6643
d0752060
HB		 6644 return 0;
6645}
6646
6647int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6648{
98918833
SY		 6649 struct i387_fxsave_struct *fxsave =
6650 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6651
d0752060
HB		 6652 memcpy(fxsave->st_space, fpu->fpr, 128);
6653 fxsave->cwd = fpu->fcw;
6654 fxsave->swd = fpu->fsw;
6655 fxsave->twd = fpu->ftwx;
6656 fxsave->fop = fpu->last_opcode;
6657 fxsave->rip = fpu->last_ip;
6658 fxsave->rdp = fpu->last_dp;
6659 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6660
d0752060
HB		 6661 return 0;
6662}
6663
10ab25cd 6664int fx_init(struct kvm_vcpu *vcpu)
d0752060 6665{
10ab25cd
JK		 6666 int err;
6667
6668 err = fpu_alloc(&vcpu->arch.guest_fpu);
6669 if (err)
6670 return err;
6671
98918833 6672 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6673
2acf923e
DC		 6674 /*
6675 * Ensure guest xcr0 is valid for loading
6676 */
6677 vcpu->arch.xcr0 = XSTATE_FP;
6678
ad312c7c 6679 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6680
6681 return 0;
d0752060
HB		 6682}
6683EXPORT_SYMBOL_GPL(fx_init);
6684
98918833
SY		 6685static void fx_free(struct kvm_vcpu *vcpu)
6686{
6687 fpu_free(&vcpu->arch.guest_fpu);
6688}
6689
d0752060
HB		 6690void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6691{
2608d7a1 6692 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6693 return;
6694
2acf923e
DC		 6695 /*
6696 * Restore all possible states in the guest,
6697 * and assume host would use all available bits.
6698 * Guest xcr0 would be loaded later.
6699 */
6700 kvm_put_guest_xcr0(vcpu);
d0752060 6701 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6702 __kernel_fpu_begin();
98918833 6703 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6704 trace_kvm_fpu(1);
d0752060 6705}
d0752060
HB		 6706
6707void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6708{
2acf923e
DC		 6709 kvm_put_guest_xcr0(vcpu);
6710
d0752060
HB		 6711 if (!vcpu->guest_fpu_loaded)
6712 return;
6713
6714 vcpu->guest_fpu_loaded = 0;
98918833 6715 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6716 __kernel_fpu_end();
f096ed85 6717 ++vcpu->stat.fpu_reload;
a8eeb04a 6718 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6719 trace_kvm_fpu(0);
d0752060 6720}
e9b11c17
ZX		 6721
6722void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6723{
12f9a48f 6724 kvmclock_reset(vcpu);
7f1ea208 6725
f5f48ee1 6726 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6727 fx_free(vcpu);
e9b11c17
ZX		 6728 kvm_x86_ops->vcpu_free(vcpu);
6729}
6730
6731struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6732 unsigned int id)
6733{
6755bae8
ZA		 6734 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6735 printk_once(KERN_WARNING
6736 "kvm: SMP vm created on host with unstable TSC; "
6737 "guest TSC will not be reliable\n");
26e5215f
AK		 6738 return kvm_x86_ops->vcpu_create(kvm, id);
6739}
e9b11c17 6740
26e5215f
AK		 6741int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6742{
6743 int r;
e9b11c17 6744
0bed3b56 6745 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6746 r = vcpu_load(vcpu);
6747 if (r)
6748 return r;
57f252f2 6749 kvm_vcpu_reset(vcpu);
8a3c1a33 6750 kvm_mmu_setup(vcpu);
e9b11c17 6751 vcpu_put(vcpu);
e9b11c17 6752
26e5215f 6753 return r;
e9b11c17
ZX		 6754}
6755
42897d86
MT		 6756int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6757{
6758 int r;
8fe8ab46 6759 struct msr_data msr;
332967a3 6760 struct kvm *kvm = vcpu->kvm;
42897d86
MT		 6761
6762 r = vcpu_load(vcpu);
6763 if (r)
6764 return r;
8fe8ab46
WA		 6765 msr.data = 0x0;
6766 msr.index = MSR_IA32_TSC;
6767 msr.host_initiated = true;
6768 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6769 vcpu_put(vcpu);
6770
332967a3
AJ		 6771 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
6772 KVMCLOCK_SYNC_PERIOD);
6773
42897d86
MT		 6774 return r;
6775}
6776
d40ccc62 6777void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6778{
9fc77441 6779 int r;
344d9588
GN		 6780 vcpu->arch.apf.msr_val = 0;
6781
9fc77441
MT		 6782 r = vcpu_load(vcpu);
6783 BUG_ON(r);
e9b11c17
ZX		 6784 kvm_mmu_unload(vcpu);
6785 vcpu_put(vcpu);
6786
98918833 6787 fx_free(vcpu);
e9b11c17
ZX		 6788 kvm_x86_ops->vcpu_free(vcpu);
6789}
6790
66450a21 6791void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6792{
7460fb4a
AK		 6793 atomic_set(&vcpu->arch.nmi_queued, 0);
6794 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6795 vcpu->arch.nmi_injected = false;
6796
42dbaa5a
JK		 6797 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6798 vcpu->arch.dr6 = DR6_FIXED_1;
73aaf249 6799 kvm_update_dr6(vcpu);
42dbaa5a 6800 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6801 kvm_update_dr7(vcpu);
42dbaa5a 6802
3842d135 6803 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6804 vcpu->arch.apf.msr_val = 0;
c9aaa895 6805 vcpu->arch.st.msr_val = 0;
3842d135 6806
12f9a48f
GC		 6807 kvmclock_reset(vcpu);
6808
af585b92
GN		 6809 kvm_clear_async_pf_completion_queue(vcpu);
6810 kvm_async_pf_hash_reset(vcpu);
6811 vcpu->arch.apf.halted = false;
3842d135 6812
f5132b01
GN		 6813 kvm_pmu_reset(vcpu);
6814
66f7b72e
JS		 6815 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6816 vcpu->arch.regs_avail = ~0;
6817 vcpu->arch.regs_dirty = ~0;
6818
57f252f2 6819 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 6820}
6821
66450a21
JK		 6822void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6823{
6824 struct kvm_segment cs;
6825
6826 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6827 cs.selector = vector << 8;
6828 cs.base = vector << 12;
6829 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6830 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 6831}
6832
10474ae8 6833int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6834{
ca84d1a2
ZA		 6835 struct kvm *kvm;
6836 struct kvm_vcpu *vcpu;
6837 int i;
0dd6a6ed
ZA		 6838 int ret;
6839 u64 local_tsc;
6840 u64 max_tsc = 0;
6841 bool stable, backwards_tsc = false;
18863bdd
AK		 6842
6843 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6844 ret = kvm_x86_ops->hardware_enable(garbage);
6845 if (ret != 0)
6846 return ret;
6847
6848 local_tsc = native_read_tsc();
6849 stable = !check_tsc_unstable();
6850 list_for_each_entry(kvm, &vm_list, vm_list) {
6851 kvm_for_each_vcpu(i, vcpu, kvm) {
6852 if (!stable && vcpu->cpu == smp_processor_id())
6853 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6854 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6855 backwards_tsc = true;
6856 if (vcpu->arch.last_host_tsc > max_tsc)
6857 max_tsc = vcpu->arch.last_host_tsc;
6858 }
6859 }
6860 }
6861
6862 /*
6863 * Sometimes, even reliable TSCs go backwards. This happens on
6864 * platforms that reset TSC during suspend or hibernate actions, but
6865 * maintain synchronization. We must compensate. Fortunately, we can
6866 * detect that condition here, which happens early in CPU bringup,
6867 * before any KVM threads can be running. Unfortunately, we can't
6868 * bring the TSCs fully up to date with real time, as we aren't yet far
6869 * enough into CPU bringup that we know how much real time has actually
6870 * elapsed; our helper function, get_kernel_ns() will be using boot
6871 * variables that haven't been updated yet.
6872 *
6873 * So we simply find the maximum observed TSC above, then record the
6874 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6875 * the adjustment will be applied. Note that we accumulate
6876 * adjustments, in case multiple suspend cycles happen before some VCPU
6877 * gets a chance to run again. In the event that no KVM threads get a
6878 * chance to run, we will miss the entire elapsed period, as we'll have
6879 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6880 * loose cycle time. This isn't too big a deal, since the loss will be
6881 * uniform across all VCPUs (not to mention the scenario is extremely
6882 * unlikely). It is possible that a second hibernate recovery happens
6883 * much faster than a first, causing the observed TSC here to be
6884 * smaller; this would require additional padding adjustment, which is
6885 * why we set last_host_tsc to the local tsc observed here.
6886 *
6887 * N.B. - this code below runs only on platforms with reliable TSC,
6888 * as that is the only way backwards_tsc is set above. Also note
6889 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6890 * have the same delta_cyc adjustment applied if backwards_tsc
6891 * is detected. Note further, this adjustment is only done once,
6892 * as we reset last_host_tsc on all VCPUs to stop this from being
6893 * called multiple times (one for each physical CPU bringup).
6894 *
4a969980 6895 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6896 * will be compensated by the logic in vcpu_load, which sets the TSC to
6897 * catchup mode. This will catchup all VCPUs to real time, but cannot
6898 * guarantee that they stay in perfect synchronization.
6899 */
6900 if (backwards_tsc) {
6901 u64 delta_cyc = max_tsc - local_tsc;
6902 list_for_each_entry(kvm, &vm_list, vm_list) {
6903 kvm_for_each_vcpu(i, vcpu, kvm) {
6904 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6905 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 6906 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6907 &vcpu->requests);
0dd6a6ed
ZA		 6908 }
6909
6910 /*
6911 * We have to disable TSC offset matching.. if you were
6912 * booting a VM while issuing an S4 host suspend....
6913 * you may have some problem. Solving this issue is
6914 * left as an exercise to the reader.
6915 */
6916 kvm->arch.last_tsc_nsec = 0;
6917 kvm->arch.last_tsc_write = 0;
6918 }
6919
6920 }
6921 return 0;
e9b11c17
ZX		 6922}
6923
6924void kvm_arch_hardware_disable(void *garbage)
6925{
6926 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6927 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6928}
6929
6930int kvm_arch_hardware_setup(void)
6931{
6932 return kvm_x86_ops->hardware_setup();
6933}
6934
6935void kvm_arch_hardware_unsetup(void)
6936{
6937 kvm_x86_ops->hardware_unsetup();
6938}
6939
6940void kvm_arch_check_processor_compat(void *rtn)
6941{
6942 kvm_x86_ops->check_processor_compatibility(rtn);
6943}
6944
3e515705
AK		 6945bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6946{
6947 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6948}
6949
54e9818f
GN		 6950struct static_key kvm_no_apic_vcpu __read_mostly;
6951
e9b11c17
ZX		 6952int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6953{
6954 struct page *page;
6955 struct kvm *kvm;
6956 int r;
6957
6958 BUG_ON(vcpu->kvm == NULL);
6959 kvm = vcpu->kvm;
6960
6aef266c 6961 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 6962 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6963 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6964 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6965 else
a4535290 6966 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6967
6968 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6969 if (!page) {
6970 r = -ENOMEM;
6971 goto fail;
6972 }
ad312c7c 6973 vcpu->arch.pio_data = page_address(page);
e9b11c17 6974
cc578287 6975 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6976
e9b11c17
ZX		 6977 r = kvm_mmu_create(vcpu);
6978 if (r < 0)
6979 goto fail_free_pio_data;
6980
6981 if (irqchip_in_kernel(kvm)) {
6982 r = kvm_create_lapic(vcpu);
6983 if (r < 0)
6984 goto fail_mmu_destroy;
54e9818f
GN		 6985 } else
6986 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 6987
890ca9ae
HY		 6988 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6989 GFP_KERNEL);
6990 if (!vcpu->arch.mce_banks) {
6991 r = -ENOMEM;
443c39bc 6992 goto fail_free_lapic;
890ca9ae
HY		 6993 }
6994 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6995
f1797359
WY		 6996 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
6997 r = -ENOMEM;
f5f48ee1 6998 goto fail_free_mce_banks;
f1797359 6999 }
f5f48ee1 7000
66f7b72e
JS		 7001 r = fx_init(vcpu);
7002 if (r)
7003 goto fail_free_wbinvd_dirty_mask;
7004
ba904635 7005 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7006 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7007
7008 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7009 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7010
af585b92 7011 kvm_async_pf_hash_reset(vcpu);
f5132b01 7012 kvm_pmu_init(vcpu);
af585b92 7013
e9b11c17 7014 return 0;
66f7b72e
JS		 7015fail_free_wbinvd_dirty_mask:
7016 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 7017fail_free_mce_banks:
7018 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7019fail_free_lapic:
7020 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7021fail_mmu_destroy:
7022 kvm_mmu_destroy(vcpu);
7023fail_free_pio_data:
ad312c7c 7024 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7025fail:
7026 return r;
7027}
7028
7029void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7030{
f656ce01
MT		 7031 int idx;
7032
f5132b01 7033 kvm_pmu_destroy(vcpu);
36cb93fd 7034 kfree(vcpu->arch.mce_banks);
e9b11c17 7035 kvm_free_lapic(vcpu);
f656ce01 7036 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7037 kvm_mmu_destroy(vcpu);
f656ce01 7038 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7039 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7040 if (!irqchip_in_kernel(vcpu->kvm))
7041 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7042}
d19a9cd2 7043
e08b9637 7044int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7045{
e08b9637
CO		 7046 if (type)
7047 return -EINVAL;
7048
f05e70ac 7049 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7050 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7051 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7052 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7053
5550af4d
SY		 7054 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7055 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7056 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7057 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7058 &kvm->arch.irq_sources_bitmap);
5550af4d 7059
038f8c11 7060 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7061 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7062 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7063
7064 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7065
7e44e449 7066 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7067 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7068
d89f5eff 7069 return 0;
d19a9cd2
ZX		 7070}
7071
7072static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7073{
9fc77441
MT		 7074 int r;
7075 r = vcpu_load(vcpu);
7076 BUG_ON(r);
d19a9cd2
ZX		 7077 kvm_mmu_unload(vcpu);
7078 vcpu_put(vcpu);
7079}
7080
7081static void kvm_free_vcpus(struct kvm *kvm)
7082{
7083 unsigned int i;
988a2cae 7084 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7085
7086 /*
7087 * Unpin any mmu pages first.
7088 */
af585b92
GN		 7089 kvm_for_each_vcpu(i, vcpu, kvm) {
7090 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7091 kvm_unload_vcpu_mmu(vcpu);
af585b92 7092 }
988a2cae
GN		 7093 kvm_for_each_vcpu(i, vcpu, kvm)
7094 kvm_arch_vcpu_free(vcpu);
7095
7096 mutex_lock(&kvm->lock);
7097 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7098 kvm->vcpus[i] = NULL;
d19a9cd2 7099
988a2cae
GN		 7100 atomic_set(&kvm->online_vcpus, 0);
7101 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7102}
7103
ad8ba2cd
SY		 7104void kvm_arch_sync_events(struct kvm *kvm)
7105{
332967a3 7106 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7107 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7108 kvm_free_all_assigned_devices(kvm);
aea924f6 7109 kvm_free_pit(kvm);
ad8ba2cd
SY		 7110}
7111
d19a9cd2
ZX		 7112void kvm_arch_destroy_vm(struct kvm *kvm)
7113{
27469d29
AH		 7114 if (current->mm == kvm->mm) {
7115 /*
7116 * Free memory regions allocated on behalf of userspace,
7117 * unless the the memory map has changed due to process exit
7118 * or fd copying.
7119 */
7120 struct kvm_userspace_memory_region mem;
7121 memset(&mem, 0, sizeof(mem));
7122 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7123 kvm_set_memory_region(kvm, &mem);
7124
7125 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7126 kvm_set_memory_region(kvm, &mem);
7127
7128 mem.slot = TSS_PRIVATE_MEMSLOT;
7129 kvm_set_memory_region(kvm, &mem);
7130 }
6eb55818 7131 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7132 kfree(kvm->arch.vpic);
7133 kfree(kvm->arch.vioapic);
d19a9cd2 7134 kvm_free_vcpus(kvm);
3d45830c
AK		 7135 if (kvm->arch.apic_access_page)
7136 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 7137 if (kvm->arch.ept_identity_pagetable)
7138 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 7139 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7140}
0de10343 7141
5587027c 7142void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7143 struct kvm_memory_slot *dont)
7144{
7145 int i;
7146
d89cc617
TY		 7147 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7148 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7149 kvm_kvfree(free->arch.rmap[i]);
7150 free->arch.rmap[i] = NULL;
77d11309 7151 }
d89cc617
TY		 7152 if (i == 0)
7153 continue;
7154
7155 if (!dont || free->arch.lpage_info[i - 1] !=
7156 dont->arch.lpage_info[i - 1]) {
7157 kvm_kvfree(free->arch.lpage_info[i - 1]);
7158 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7159 }
7160 }
7161}
7162
5587027c
AK		 7163int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7164 unsigned long npages)
db3fe4eb
TY		 7165{
7166 int i;
7167
d89cc617 7168 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7169 unsigned long ugfn;
7170 int lpages;
d89cc617 7171 int level = i + 1;
db3fe4eb
TY		 7172
7173 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7174 slot->base_gfn, level) + 1;
7175
d89cc617
TY		 7176 slot->arch.rmap[i] =
7177 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7178 if (!slot->arch.rmap[i])
77d11309 7179 goto out_free;
d89cc617
TY		 7180 if (i == 0)
7181 continue;
77d11309 7182
d89cc617
TY		 7183 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7184 sizeof(*slot->arch.lpage_info[i - 1]));
7185 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7186 goto out_free;
7187
7188 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7189 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7190 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7191 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7192 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7193 /*
7194 * If the gfn and userspace address are not aligned wrt each
7195 * other, or if explicitly asked to, disable large page
7196 * support for this slot
7197 */
7198 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7199 !kvm_largepages_enabled()) {
7200 unsigned long j;
7201
7202 for (j = 0; j < lpages; ++j)
d89cc617 7203 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7204 }
7205 }
7206
7207 return 0;
7208
7209out_free:
d89cc617
TY		 7210 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7211 kvm_kvfree(slot->arch.rmap[i]);
7212 slot->arch.rmap[i] = NULL;
7213 if (i == 0)
7214 continue;
7215
7216 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7217 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7218 }
7219 return -ENOMEM;
7220}
7221
e59dbe09
TY		 7222void kvm_arch_memslots_updated(struct kvm *kvm)
7223{
e6dff7d1
TY		 7224 /*
7225 * memslots->generation has been incremented.
7226 * mmio generation may have reached its maximum value.
7227 */
7228 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7229}
7230
f7784b8e
MT		 7231int kvm_arch_prepare_memory_region(struct kvm *kvm,
7232 struct kvm_memory_slot *memslot,
f7784b8e 7233 struct kvm_userspace_memory_region *mem,
7b6195a9 7234 enum kvm_mr_change change)
0de10343 7235{
7a905b14
TY		 7236 /*
7237 * Only private memory slots need to be mapped here since
7238 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7239 */
7b6195a9 7240 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7241 unsigned long userspace_addr;
604b38ac 7242
7a905b14
TY		 7243 /*
7244 * MAP_SHARED to prevent internal slot pages from being moved
7245 * by fork()/COW.
7246 */
7b6195a9 7247 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7248 PROT_READ | PROT_WRITE,
7249 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7250
7a905b14
TY		 7251 if (IS_ERR((void *)userspace_addr))
7252 return PTR_ERR((void *)userspace_addr);
604b38ac 7253
7a905b14 7254 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7255 }
7256
f7784b8e
MT		 7257 return 0;
7258}
7259
7260void kvm_arch_commit_memory_region(struct kvm *kvm,
7261 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7262 const struct kvm_memory_slot *old,
7263 enum kvm_mr_change change)
f7784b8e
MT		 7264{
7265
8482644a 7266 int nr_mmu_pages = 0;
f7784b8e 7267
8482644a 7268 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7269 int ret;
7270
8482644a
TY		 7271 ret = vm_munmap(old->userspace_addr,
7272 old->npages * PAGE_SIZE);
f7784b8e
MT		 7273 if (ret < 0)
7274 printk(KERN_WARNING
7275 "kvm_vm_ioctl_set_memory_region: "
7276 "failed to munmap memory\n");
7277 }
7278
48c0e4e9
XG		 7279 if (!kvm->arch.n_requested_mmu_pages)
7280 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7281
48c0e4e9 7282 if (nr_mmu_pages)
0de10343 7283 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7284 /*
7285 * Write protect all pages for dirty logging.
7286 * Existing largepage mappings are destroyed here and new ones will
7287 * not be created until the end of the logging.
7288 */
8482644a 7289 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7290 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7291}
1d737c8a 7292
2df72e9b 7293void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7294{
6ca18b69 7295 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7296}
7297
2df72e9b
MT		 7298void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7299 struct kvm_memory_slot *slot)
7300{
6ca18b69 7301 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7302}
7303
1d737c8a
ZX		 7304int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7305{
b6b8a145
JK		 7306 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7307 kvm_x86_ops->check_nested_events(vcpu, false);
7308
af585b92
GN		 7309 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7310 !vcpu->arch.apf.halted)
7311 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7312 || kvm_apic_has_events(vcpu)
6aef266c 7313 || vcpu->arch.pv.pv_unhalted
7460fb4a 7314 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7315 (kvm_arch_interrupt_allowed(vcpu) &&
7316 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7317}
5736199a 7318
b6d33834 7319int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7320{
b6d33834 7321 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7322}
78646121
GN		 7323
7324int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7325{
7326 return kvm_x86_ops->interrupt_allowed(vcpu);
7327}
229456fc 7328
f92653ee
JK		 7329bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7330{
7331 unsigned long current_rip = kvm_rip_read(vcpu) +
7332 get_segment_base(vcpu, VCPU_SREG_CS);
7333
7334 return current_rip == linear_rip;
7335}
7336EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7337
94fe45da
JK		 7338unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7339{
7340 unsigned long rflags;
7341
7342 rflags = kvm_x86_ops->get_rflags(vcpu);
7343 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7344 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7345 return rflags;
7346}
7347EXPORT_SYMBOL_GPL(kvm_get_rflags);
7348
7349void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7350{
7351 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7352 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7353 rflags |= X86_EFLAGS_TF;
94fe45da 7354 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 7355 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7356}
7357EXPORT_SYMBOL_GPL(kvm_set_rflags);
7358
56028d08
GN		 7359void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7360{
7361 int r;
7362
fb67e14f 7363 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7364 work->wakeup_all)
56028d08
GN		 7365 return;
7366
7367 r = kvm_mmu_reload(vcpu);
7368 if (unlikely(r))
7369 return;
7370
fb67e14f
XG		 7371 if (!vcpu->arch.mmu.direct_map &&
7372 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7373 return;
7374
56028d08
GN		 7375 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7376}
7377
af585b92
GN		 7378static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7379{
7380 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7381}
7382
7383static inline u32 kvm_async_pf_next_probe(u32 key)
7384{
7385 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7386}
7387
7388static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7389{
7390 u32 key = kvm_async_pf_hash_fn(gfn);
7391
7392 while (vcpu->arch.apf.gfns[key] != ~0)
7393 key = kvm_async_pf_next_probe(key);
7394
7395 vcpu->arch.apf.gfns[key] = gfn;
7396}
7397
7398static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7399{
7400 int i;
7401 u32 key = kvm_async_pf_hash_fn(gfn);
7402
7403 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7404 (vcpu->arch.apf.gfns[key] != gfn &&
7405 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7406 key = kvm_async_pf_next_probe(key);
7407
7408 return key;
7409}
7410
7411bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7412{
7413 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7414}
7415
7416static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7417{
7418 u32 i, j, k;
7419
7420 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7421 while (true) {
7422 vcpu->arch.apf.gfns[i] = ~0;
7423 do {
7424 j = kvm_async_pf_next_probe(j);
7425 if (vcpu->arch.apf.gfns[j] == ~0)
7426 return;
7427 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7428 /*
7429 * k lies cyclically in ]i,j]
7430 * | i.k.j |
7431 * |....j i.k.| or |.k..j i...|
7432 */
7433 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7434 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7435 i = j;
7436 }
7437}
7438
7c90705b
GN		 7439static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7440{
7441
7442 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7443 sizeof(val));
7444}
7445
af585b92
GN		 7446void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7447 struct kvm_async_pf *work)
7448{
6389ee94
AK		 7449 struct x86_exception fault;
7450
7c90705b 7451 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7452 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7453
7454 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7455 (vcpu->arch.apf.send_user_only &&
7456 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7457 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7458 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7459 fault.vector = PF_VECTOR;
7460 fault.error_code_valid = true;
7461 fault.error_code = 0;
7462 fault.nested_page_fault = false;
7463 fault.address = work->arch.token;
7464 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7465 }
af585b92
GN		 7466}
7467
7468void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7469 struct kvm_async_pf *work)
7470{
6389ee94
AK		 7471 struct x86_exception fault;
7472
7c90705b 7473 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7474 if (work->wakeup_all)
7c90705b
GN		 7475 work->arch.token = ~0; /* broadcast wakeup */
7476 else
7477 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7478
7479 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7480 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7481 fault.vector = PF_VECTOR;
7482 fault.error_code_valid = true;
7483 fault.error_code = 0;
7484 fault.nested_page_fault = false;
7485 fault.address = work->arch.token;
7486 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7487 }
e6d53e3b 7488 vcpu->arch.apf.halted = false;
a4fa1635 7489 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7490}
7491
7492bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7493{
7494 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7495 return true;
7496 else
7497 return !kvm_event_needs_reinjection(vcpu) &&
7498 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7499}
7500
e0f0bbc5
AW		 7501void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7502{
7503 atomic_inc(&kvm->arch.noncoherent_dma_count);
7504}
7505EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7506
7507void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7508{
7509 atomic_dec(&kvm->arch.noncoherent_dma_count);
7510}
7511EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7512
7513bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7514{
7515 return atomic_read(&kvm->arch.noncoherent_dma_count);
7516}
7517EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7518
229456fc
MT		 7519EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7520EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7521EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7522EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7523EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7524EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7525EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7526EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7527EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7528EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7529EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7530EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7531EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
Ubuntu Jammy Linux kernel mirror