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KVM paravirt: Move kvm_smp_prepare_boot_cpu() from kvmclock.c to kvm.c.
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
af585b92 46#include <linux/hash.h>
aec51dc4 47#include <trace/events/kvm.h>
2ed152af 48
229456fc
MT		 49#define CREATE_TRACE_POINTS
50#include "trace.h"
043405e1 51
24f1e32c 52#include <asm/debugreg.h>
d825ed0a 53#include <asm/msr.h>
a5f61300 54#include <asm/desc.h>
0bed3b56 55#include <asm/mtrr.h>
890ca9ae 56#include <asm/mce.h>
7cf30855 57#include <asm/i387.h>
98918833 58#include <asm/xcr.h>
1d5f066e 59#include <asm/pvclock.h>
217fc9cf 60#include <asm/div64.h>
043405e1 61
313a3dc7 62#define MAX_IO_MSRS 256
a03490ed
CO		 63#define CR0_RESERVED_BITS \
64 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
65 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
66 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
67#define CR4_RESERVED_BITS \
68 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
69 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
70 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
2acf923e 71 | X86_CR4_OSXSAVE \
a03490ed
CO		 72 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
73
74#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 75
76#define KVM_MAX_MCE_BANKS 32
5854dbca 77#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 78
50a37eb4
JR		 79/* EFER defaults:
80 * - enable syscall per default because its emulated by KVM
81 * - enable LME and LMA per default on 64 bit KVM
82 */
83#ifdef CONFIG_X86_64
84static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
85#else
86static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
87#endif
313a3dc7 88
ba1389b7
AK		 89#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 91
cb142eb7 92static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 93static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
94 struct kvm_cpuid_entry2 __user *entries);
95
97896d04 96struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 97EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 98
ed85c068
AP		 99int ignore_msrs = 0;
100module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
101
18863bdd
AK		 102#define KVM_NR_SHARED_MSRS 16
103
104struct kvm_shared_msrs_global {
105 int nr;
2bf78fa7 106 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 107};
108
109struct kvm_shared_msrs {
110 struct user_return_notifier urn;
111 bool registered;
2bf78fa7
SY		 112 struct kvm_shared_msr_values {
113 u64 host;
114 u64 curr;
115 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 116};
117
118static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
119static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
120
417bc304 121struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 122 { "pf_fixed", VCPU_STAT(pf_fixed) },
123 { "pf_guest", VCPU_STAT(pf_guest) },
124 { "tlb_flush", VCPU_STAT(tlb_flush) },
125 { "invlpg", VCPU_STAT(invlpg) },
126 { "exits", VCPU_STAT(exits) },
127 { "io_exits", VCPU_STAT(io_exits) },
128 { "mmio_exits", VCPU_STAT(mmio_exits) },
129 { "signal_exits", VCPU_STAT(signal_exits) },
130 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 131 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 132 { "halt_exits", VCPU_STAT(halt_exits) },
133 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 134 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 135 { "request_irq", VCPU_STAT(request_irq_exits) },
136 { "irq_exits", VCPU_STAT(irq_exits) },
137 { "host_state_reload", VCPU_STAT(host_state_reload) },
138 { "efer_reload", VCPU_STAT(efer_reload) },
139 { "fpu_reload", VCPU_STAT(fpu_reload) },
140 { "insn_emulation", VCPU_STAT(insn_emulation) },
141 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 142 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 143 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 144 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
145 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
146 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
147 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
148 { "mmu_flooded", VM_STAT(mmu_flooded) },
149 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 150 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 151 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 152 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 153 { "largepages", VM_STAT(lpages) },
417bc304
HB		 154 { NULL }
155};
156
2acf923e
DC		 157u64 __read_mostly host_xcr0;
158
af585b92
GN		 159static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
160{
161 int i;
162 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
163 vcpu->arch.apf.gfns[i] = ~0;
164}
165
18863bdd
AK		 166static void kvm_on_user_return(struct user_return_notifier *urn)
167{
168 unsigned slot;
18863bdd
AK		 169 struct kvm_shared_msrs *locals
170 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 171 struct kvm_shared_msr_values *values;
18863bdd
AK		 172
173 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 174 values = &locals->values[slot];
175 if (values->host != values->curr) {
176 wrmsrl(shared_msrs_global.msrs[slot], values->host);
177 values->curr = values->host;
18863bdd
AK		 178 }
179 }
180 locals->registered = false;
181 user_return_notifier_unregister(urn);
182}
183
2bf78fa7 184static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 185{
2bf78fa7 186 struct kvm_shared_msrs *smsr;
18863bdd
AK		 187 u64 value;
188
2bf78fa7
SY		 189 smsr = &__get_cpu_var(shared_msrs);
190 /* only read, and nobody should modify it at this time,
191 * so don't need lock */
192 if (slot >= shared_msrs_global.nr) {
193 printk(KERN_ERR "kvm: invalid MSR slot!");
194 return;
195 }
196 rdmsrl_safe(msr, &value);
197 smsr->values[slot].host = value;
198 smsr->values[slot].curr = value;
199}
200
201void kvm_define_shared_msr(unsigned slot, u32 msr)
202{
18863bdd
AK		 203 if (slot >= shared_msrs_global.nr)
204 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 205 shared_msrs_global.msrs[slot] = msr;
206 /* we need ensured the shared_msr_global have been updated */
207 smp_wmb();
18863bdd
AK		 208}
209EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
210
211static void kvm_shared_msr_cpu_online(void)
212{
213 unsigned i;
18863bdd
AK		 214
215 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 216 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 217}
218
d5696725 219void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 220{
221 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
222
2bf78fa7 223 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 224 return;
2bf78fa7
SY		 225 smsr->values[slot].curr = value;
226 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 227 if (!smsr->registered) {
228 smsr->urn.on_user_return = kvm_on_user_return;
229 user_return_notifier_register(&smsr->urn);
230 smsr->registered = true;
231 }
232}
233EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
234
3548bab5
AK		 235static void drop_user_return_notifiers(void *ignore)
236{
237 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
238
239 if (smsr->registered)
240 kvm_on_user_return(&smsr->urn);
241}
242
6866b83e
CO		 243u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
244{
245 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 246 return vcpu->arch.apic_base;
6866b83e 247 else
ad312c7c 248 return vcpu->arch.apic_base;
6866b83e
CO		 249}
250EXPORT_SYMBOL_GPL(kvm_get_apic_base);
251
252void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
253{
254 /* TODO: reserve bits check */
255 if (irqchip_in_kernel(vcpu->kvm))
256 kvm_lapic_set_base(vcpu, data);
257 else
ad312c7c 258 vcpu->arch.apic_base = data;
6866b83e
CO		 259}
260EXPORT_SYMBOL_GPL(kvm_set_apic_base);
261
3fd28fce
ED		 262#define EXCPT_BENIGN 0
263#define EXCPT_CONTRIBUTORY 1
264#define EXCPT_PF 2
265
266static int exception_class(int vector)
267{
268 switch (vector) {
269 case PF_VECTOR:
270 return EXCPT_PF;
271 case DE_VECTOR:
272 case TS_VECTOR:
273 case NP_VECTOR:
274 case SS_VECTOR:
275 case GP_VECTOR:
276 return EXCPT_CONTRIBUTORY;
277 default:
278 break;
279 }
280 return EXCPT_BENIGN;
281}
282
283static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 284 unsigned nr, bool has_error, u32 error_code,
285 bool reinject)
3fd28fce
ED		 286{
287 u32 prev_nr;
288 int class1, class2;
289
3842d135
AK		 290 kvm_make_request(KVM_REQ_EVENT, vcpu);
291
3fd28fce
ED		 292 if (!vcpu->arch.exception.pending) {
293 queue:
294 vcpu->arch.exception.pending = true;
295 vcpu->arch.exception.has_error_code = has_error;
296 vcpu->arch.exception.nr = nr;
297 vcpu->arch.exception.error_code = error_code;
3f0fd292 298 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 299 return;
300 }
301
302 /* to check exception */
303 prev_nr = vcpu->arch.exception.nr;
304 if (prev_nr == DF_VECTOR) {
305 /* triple fault -> shutdown */
a8eeb04a 306 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 307 return;
308 }
309 class1 = exception_class(prev_nr);
310 class2 = exception_class(nr);
311 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
312 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
313 /* generate double fault per SDM Table 5-5 */
314 vcpu->arch.exception.pending = true;
315 vcpu->arch.exception.has_error_code = true;
316 vcpu->arch.exception.nr = DF_VECTOR;
317 vcpu->arch.exception.error_code = 0;
318 } else
319 /* replace previous exception with a new one in a hope
320 that instruction re-execution will regenerate lost
321 exception */
322 goto queue;
323}
324
298101da
AK		 325void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
326{
ce7ddec4 327 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 328}
329EXPORT_SYMBOL_GPL(kvm_queue_exception);
330
ce7ddec4
JR		 331void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
332{
333 kvm_multiple_exception(vcpu, nr, false, 0, true);
334}
335EXPORT_SYMBOL_GPL(kvm_requeue_exception);
336
8df25a32 337void kvm_inject_page_fault(struct kvm_vcpu *vcpu)
c3c91fee 338{
8df25a32
JR		 339 unsigned error_code = vcpu->arch.fault.error_code;
340
c3c91fee 341 ++vcpu->stat.pf_guest;
8df25a32 342 vcpu->arch.cr2 = vcpu->arch.fault.address;
c3c91fee
AK		 343 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
344}
345
d4f8cf66
JR		 346void kvm_propagate_fault(struct kvm_vcpu *vcpu)
347{
0959ffac 348 if (mmu_is_nested(vcpu) && !vcpu->arch.fault.nested)
d4f8cf66
JR		 349 vcpu->arch.nested_mmu.inject_page_fault(vcpu);
350 else
351 vcpu->arch.mmu.inject_page_fault(vcpu);
0959ffac
JR		 352
353 vcpu->arch.fault.nested = false;
d4f8cf66
JR		 354}
355
3419ffc8
SY		 356void kvm_inject_nmi(struct kvm_vcpu *vcpu)
357{
3842d135 358 kvm_make_request(KVM_REQ_EVENT, vcpu);
3419ffc8
SY		 359 vcpu->arch.nmi_pending = 1;
360}
361EXPORT_SYMBOL_GPL(kvm_inject_nmi);
362
298101da
AK		 363void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
364{
ce7ddec4 365 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 366}
367EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
368
ce7ddec4
JR		 369void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
370{
371 kvm_multiple_exception(vcpu, nr, true, error_code, true);
372}
373EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
374
0a79b009
AK		 375/*
376 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
377 * a #GP and return false.
378 */
379bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 380{
0a79b009
AK		 381 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
382 return true;
383 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
384 return false;
298101da 385}
0a79b009 386EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 387
ec92fe44
JR		 388/*
389 * This function will be used to read from the physical memory of the currently
390 * running guest. The difference to kvm_read_guest_page is that this function
391 * can read from guest physical or from the guest's guest physical memory.
392 */
393int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
394 gfn_t ngfn, void *data, int offset, int len,
395 u32 access)
396{
397 gfn_t real_gfn;
398 gpa_t ngpa;
399
400 ngpa = gfn_to_gpa(ngfn);
401 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
402 if (real_gfn == UNMAPPED_GVA)
403 return -EFAULT;
404
405 real_gfn = gpa_to_gfn(real_gfn);
406
407 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
408}
409EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
410
3d06b8bf
JR		 411int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
412 void *data, int offset, int len, u32 access)
413{
414 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
415 data, offset, len, access);
416}
417
a03490ed
CO		 418/*
419 * Load the pae pdptrs. Return true is they are all valid.
420 */
ff03a073 421int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 422{
423 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
424 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
425 int i;
426 int ret;
ff03a073 427 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 428
ff03a073
JR		 429 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
430 offset * sizeof(u64), sizeof(pdpte),
431 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 432 if (ret < 0) {
433 ret = 0;
434 goto out;
435 }
436 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 437 if (is_present_gpte(pdpte[i]) &&
20c466b5 438 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 439 ret = 0;
440 goto out;
441 }
442 }
443 ret = 1;
444
ff03a073 445 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 446 __set_bit(VCPU_EXREG_PDPTR,
447 (unsigned long *)&vcpu->arch.regs_avail);
448 __set_bit(VCPU_EXREG_PDPTR,
449 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 450out:
a03490ed
CO		 451
452 return ret;
453}
cc4b6871 454EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 455
d835dfec
AK		 456static bool pdptrs_changed(struct kvm_vcpu *vcpu)
457{
ff03a073 458 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 459 bool changed = true;
3d06b8bf
JR		 460 int offset;
461 gfn_t gfn;
d835dfec
AK		 462 int r;
463
464 if (is_long_mode(vcpu) || !is_pae(vcpu))
465 return false;
466
6de4f3ad
AK		 467 if (!test_bit(VCPU_EXREG_PDPTR,
468 (unsigned long *)&vcpu->arch.regs_avail))
469 return true;
470
3d06b8bf
JR		 471 gfn = (vcpu->arch.cr3 & ~31u) >> PAGE_SHIFT;
472 offset = (vcpu->arch.cr3 & ~31u) & (PAGE_SIZE - 1);
473 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
474 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 475 if (r < 0)
476 goto out;
ff03a073 477 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 478out:
d835dfec
AK		 479
480 return changed;
481}
482
49a9b07e 483int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 484{
aad82703
SY		 485 unsigned long old_cr0 = kvm_read_cr0(vcpu);
486 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
487 X86_CR0_CD | X86_CR0_NW;
488
f9a48e6a
AK		 489 cr0 |= X86_CR0_ET;
490
ab344828 491#ifdef CONFIG_X86_64
0f12244f
GN		 492 if (cr0 & 0xffffffff00000000UL)
493 return 1;
ab344828
GN		 494#endif
495
496 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 497
0f12244f
GN		 498 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
499 return 1;
a03490ed 500
0f12244f
GN		 501 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
502 return 1;
a03490ed
CO		 503
504 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
505#ifdef CONFIG_X86_64
f6801dff 506 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 507 int cs_db, cs_l;
508
0f12244f
GN		 509 if (!is_pae(vcpu))
510 return 1;
a03490ed 511 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 512 if (cs_l)
513 return 1;
a03490ed
CO		 514 } else
515#endif
ff03a073
JR		 516 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
517 vcpu->arch.cr3))
0f12244f 518 return 1;
a03490ed
CO		 519 }
520
521 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 522
aad82703
SY		 523 if ((cr0 ^ old_cr0) & update_bits)
524 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 525 return 0;
526}
2d3ad1f4 527EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 528
2d3ad1f4 529void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 530{
49a9b07e 531 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 532}
2d3ad1f4 533EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 534
2acf923e
DC		 535int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
536{
537 u64 xcr0;
538
539 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
540 if (index != XCR_XFEATURE_ENABLED_MASK)
541 return 1;
542 xcr0 = xcr;
543 if (kvm_x86_ops->get_cpl(vcpu) != 0)
544 return 1;
545 if (!(xcr0 & XSTATE_FP))
546 return 1;
547 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
548 return 1;
549 if (xcr0 & ~host_xcr0)
550 return 1;
551 vcpu->arch.xcr0 = xcr0;
552 vcpu->guest_xcr0_loaded = 0;
553 return 0;
554}
555
556int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
557{
558 if (__kvm_set_xcr(vcpu, index, xcr)) {
559 kvm_inject_gp(vcpu, 0);
560 return 1;
561 }
562 return 0;
563}
564EXPORT_SYMBOL_GPL(kvm_set_xcr);
565
566static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
567{
568 struct kvm_cpuid_entry2 *best;
569
570 best = kvm_find_cpuid_entry(vcpu, 1, 0);
571 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
572}
573
574static void update_cpuid(struct kvm_vcpu *vcpu)
575{
576 struct kvm_cpuid_entry2 *best;
577
578 best = kvm_find_cpuid_entry(vcpu, 1, 0);
579 if (!best)
580 return;
581
582 /* Update OSXSAVE bit */
583 if (cpu_has_xsave && best->function == 0x1) {
584 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
585 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
586 best->ecx |= bit(X86_FEATURE_OSXSAVE);
587 }
588}
589
a83b29c6 590int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 591{
fc78f519 592 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 593 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
594
0f12244f
GN		 595 if (cr4 & CR4_RESERVED_BITS)
596 return 1;
a03490ed 597
2acf923e
DC		 598 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
599 return 1;
600
a03490ed 601 if (is_long_mode(vcpu)) {
0f12244f
GN		 602 if (!(cr4 & X86_CR4_PAE))
603 return 1;
a2edf57f
AK		 604 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
605 && ((cr4 ^ old_cr4) & pdptr_bits)
ff03a073 606 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3))
0f12244f
GN		 607 return 1;
608
609 if (cr4 & X86_CR4_VMXE)
610 return 1;
a03490ed 611
a03490ed 612 kvm_x86_ops->set_cr4(vcpu, cr4);
62ad0755 613
aad82703
SY		 614 if ((cr4 ^ old_cr4) & pdptr_bits)
615 kvm_mmu_reset_context(vcpu);
0f12244f 616
2acf923e
DC		 617 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
618 update_cpuid(vcpu);
619
0f12244f
GN		 620 return 0;
621}
2d3ad1f4 622EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 623
2390218b 624int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 625{
ad312c7c 626 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 627 kvm_mmu_sync_roots(vcpu);
d835dfec 628 kvm_mmu_flush_tlb(vcpu);
0f12244f 629 return 0;
d835dfec
AK		 630 }
631
a03490ed 632 if (is_long_mode(vcpu)) {
0f12244f
GN		 633 if (cr3 & CR3_L_MODE_RESERVED_BITS)
634 return 1;
a03490ed
CO		 635 } else {
636 if (is_pae(vcpu)) {
0f12244f
GN		 637 if (cr3 & CR3_PAE_RESERVED_BITS)
638 return 1;
ff03a073
JR		 639 if (is_paging(vcpu) &&
640 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 641 return 1;
a03490ed
CO		 642 }
643 /*
644 * We don't check reserved bits in nonpae mode, because
645 * this isn't enforced, and VMware depends on this.
646 */
647 }
648
a03490ed
CO		 649 /*
650 * Does the new cr3 value map to physical memory? (Note, we
651 * catch an invalid cr3 even in real-mode, because it would
652 * cause trouble later on when we turn on paging anyway.)
653 *
654 * A real CPU would silently accept an invalid cr3 and would
655 * attempt to use it - with largely undefined (and often hard
656 * to debug) behavior on the guest side.
657 */
658 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 659 return 1;
660 vcpu->arch.cr3 = cr3;
661 vcpu->arch.mmu.new_cr3(vcpu);
662 return 0;
663}
2d3ad1f4 664EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 665
0f12244f 666int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 667{
0f12244f
GN		 668 if (cr8 & CR8_RESERVED_BITS)
669 return 1;
a03490ed
CO		 670 if (irqchip_in_kernel(vcpu->kvm))
671 kvm_lapic_set_tpr(vcpu, cr8);
672 else
ad312c7c 673 vcpu->arch.cr8 = cr8;
0f12244f
GN		 674 return 0;
675}
676
677void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
678{
679 if (__kvm_set_cr8(vcpu, cr8))
680 kvm_inject_gp(vcpu, 0);
a03490ed 681}
2d3ad1f4 682EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 683
2d3ad1f4 684unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 685{
686 if (irqchip_in_kernel(vcpu->kvm))
687 return kvm_lapic_get_cr8(vcpu);
688 else
ad312c7c 689 return vcpu->arch.cr8;
a03490ed 690}
2d3ad1f4 691EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 692
338dbc97 693static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 694{
695 switch (dr) {
696 case 0 ... 3:
697 vcpu->arch.db[dr] = val;
698 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
699 vcpu->arch.eff_db[dr] = val;
700 break;
701 case 4:
338dbc97
GN		 702 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
703 return 1; /* #UD */
020df079
GN		 704 /* fall through */
705 case 6:
338dbc97
GN		 706 if (val & 0xffffffff00000000ULL)
707 return -1; /* #GP */
020df079
GN		 708 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
709 break;
710 case 5:
338dbc97
GN		 711 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
712 return 1; /* #UD */
020df079
GN		 713 /* fall through */
714 default: /* 7 */
338dbc97
GN		 715 if (val & 0xffffffff00000000ULL)
716 return -1; /* #GP */
020df079
GN		 717 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
718 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
719 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
720 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
721 }
722 break;
723 }
724
725 return 0;
726}
338dbc97
GN		 727
728int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
729{
730 int res;
731
732 res = __kvm_set_dr(vcpu, dr, val);
733 if (res > 0)
734 kvm_queue_exception(vcpu, UD_VECTOR);
735 else if (res < 0)
736 kvm_inject_gp(vcpu, 0);
737
738 return res;
739}
020df079
GN		 740EXPORT_SYMBOL_GPL(kvm_set_dr);
741
338dbc97 742static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 743{
744 switch (dr) {
745 case 0 ... 3:
746 *val = vcpu->arch.db[dr];
747 break;
748 case 4:
338dbc97 749 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 750 return 1;
020df079
GN		 751 /* fall through */
752 case 6:
753 *val = vcpu->arch.dr6;
754 break;
755 case 5:
338dbc97 756 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 757 return 1;
020df079
GN		 758 /* fall through */
759 default: /* 7 */
760 *val = vcpu->arch.dr7;
761 break;
762 }
763
764 return 0;
765}
338dbc97
GN		 766
767int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
768{
769 if (_kvm_get_dr(vcpu, dr, val)) {
770 kvm_queue_exception(vcpu, UD_VECTOR);
771 return 1;
772 }
773 return 0;
774}
020df079
GN		 775EXPORT_SYMBOL_GPL(kvm_get_dr);
776
043405e1
CO		 777/*
778 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
779 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
780 *
781 * This list is modified at module load time to reflect the
e3267cbb
GC		 782 * capabilities of the host cpu. This capabilities test skips MSRs that are
783 * kvm-specific. Those are put in the beginning of the list.
043405e1 784 */
e3267cbb 785
11c6bffa 786#define KVM_SAVE_MSRS_BEGIN 7
043405e1 787static u32 msrs_to_save[] = {
e3267cbb 788 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 789 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 790 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 791 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1 792 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 793 MSR_STAR,
043405e1
CO		 794#ifdef CONFIG_X86_64
795 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
796#endif
e90aa41e 797 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 798};
799
800static unsigned num_msrs_to_save;
801
802static u32 emulated_msrs[] = {
803 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 804 MSR_IA32_MCG_STATUS,
805 MSR_IA32_MCG_CTL,
043405e1
CO		 806};
807
b69e8cae 808static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 809{
aad82703
SY		 810 u64 old_efer = vcpu->arch.efer;
811
b69e8cae
RJ		 812 if (efer & efer_reserved_bits)
813 return 1;
15c4a640
CO		 814
815 if (is_paging(vcpu)
b69e8cae
RJ		 816 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
817 return 1;
15c4a640 818
1b2fd70c
AG		 819 if (efer & EFER_FFXSR) {
820 struct kvm_cpuid_entry2 *feat;
821
822 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 823 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
824 return 1;
1b2fd70c
AG		 825 }
826
d8017474
AG		 827 if (efer & EFER_SVME) {
828 struct kvm_cpuid_entry2 *feat;
829
830 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 831 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
832 return 1;
d8017474
AG		 833 }
834
15c4a640 835 efer &= ~EFER_LMA;
f6801dff 836 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 837
a3d204e2
SY		 838 kvm_x86_ops->set_efer(vcpu, efer);
839
9645bb56 840 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 841
aad82703
SY		 842 /* Update reserved bits */
843 if ((efer ^ old_efer) & EFER_NX)
844 kvm_mmu_reset_context(vcpu);
845
b69e8cae 846 return 0;
15c4a640
CO		 847}
848
f2b4b7dd
JR		 849void kvm_enable_efer_bits(u64 mask)
850{
851 efer_reserved_bits &= ~mask;
852}
853EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
854
855
15c4a640
CO		 856/*
857 * Writes msr value into into the appropriate "register".
858 * Returns 0 on success, non-0 otherwise.
859 * Assumes vcpu_load() was already called.
860 */
861int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
862{
863 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
864}
865
313a3dc7
CO		 866/*
867 * Adapt set_msr() to msr_io()'s calling convention
868 */
869static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
870{
871 return kvm_set_msr(vcpu, index, *data);
872}
873
18068523
GOC		 874static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
875{
9ed3c444
AK		 876 int version;
877 int r;
50d0a0f9 878 struct pvclock_wall_clock wc;
923de3cf 879 struct timespec boot;
18068523
GOC		 880
881 if (!wall_clock)
882 return;
883
9ed3c444
AK		 884 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
885 if (r)
886 return;
887
888 if (version & 1)
889 ++version; /* first time write, random junk */
890
891 ++version;
18068523 892
18068523
GOC		 893 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
894
50d0a0f9
GH		 895 /*
896 * The guest calculates current wall clock time by adding
34c238a1 897 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 898 * wall clock specified here. guest system time equals host
899 * system time for us, thus we must fill in host boot time here.
900 */
923de3cf 901 getboottime(&boot);
50d0a0f9
GH		 902
903 wc.sec = boot.tv_sec;
904 wc.nsec = boot.tv_nsec;
905 wc.version = version;
18068523
GOC		 906
907 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
908
909 version++;
910 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 911}
912
50d0a0f9
GH		 913static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
914{
915 uint32_t quotient, remainder;
916
917 /* Don't try to replace with do_div(), this one calculates
918 * "(dividend << 32) / divisor" */
919 __asm__ ( "divl %4"
920 : "=a" (quotient), "=d" (remainder)
921 : "0" (0), "1" (dividend), "r" (divisor) );
922 return quotient;
923}
924
5f4e3f88
ZA		 925static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
926 s8 *pshift, u32 *pmultiplier)
50d0a0f9 927{
5f4e3f88 928 uint64_t scaled64;
50d0a0f9
GH		 929 int32_t shift = 0;
930 uint64_t tps64;
931 uint32_t tps32;
932
5f4e3f88
ZA		 933 tps64 = base_khz * 1000LL;
934 scaled64 = scaled_khz * 1000LL;
50933623 935 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 936 tps64 >>= 1;
937 shift--;
938 }
939
940 tps32 = (uint32_t)tps64;
50933623
JK		 941 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
942 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 943 scaled64 >>= 1;
944 else
945 tps32 <<= 1;
50d0a0f9
GH		 946 shift++;
947 }
948
5f4e3f88
ZA		 949 *pshift = shift;
950 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 951
5f4e3f88
ZA		 952 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
953 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 954}
955
759379dd
ZA		 956static inline u64 get_kernel_ns(void)
957{
958 struct timespec ts;
959
960 WARN_ON(preemptible());
961 ktime_get_ts(&ts);
962 monotonic_to_bootbased(&ts);
963 return timespec_to_ns(&ts);
50d0a0f9
GH		 964}
965
c8076604 966static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 967unsigned long max_tsc_khz;
c8076604 968
8cfdc000
ZA		 969static inline int kvm_tsc_changes_freq(void)
970{
971 int cpu = get_cpu();
972 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
973 cpufreq_quick_get(cpu) != 0;
974 put_cpu();
975 return ret;
976}
977
759379dd
ZA		 978static inline u64 nsec_to_cycles(u64 nsec)
979{
217fc9cf
AK		 980 u64 ret;
981
759379dd
ZA		 982 WARN_ON(preemptible());
983 if (kvm_tsc_changes_freq())
984 printk_once(KERN_WARNING
985 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
217fc9cf
AK		 986 ret = nsec * __get_cpu_var(cpu_tsc_khz);
987 do_div(ret, USEC_PER_SEC);
988 return ret;
759379dd
ZA		 989}
990
c285545f
ZA		 991static void kvm_arch_set_tsc_khz(struct kvm *kvm, u32 this_tsc_khz)
992{
993 /* Compute a scale to convert nanoseconds in TSC cycles */
994 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
995 &kvm->arch.virtual_tsc_shift,
996 &kvm->arch.virtual_tsc_mult);
997 kvm->arch.virtual_tsc_khz = this_tsc_khz;
998}
999
1000static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1001{
1002 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
1003 vcpu->kvm->arch.virtual_tsc_mult,
1004 vcpu->kvm->arch.virtual_tsc_shift);
1005 tsc += vcpu->arch.last_tsc_write;
1006 return tsc;
1007}
1008
99e3e30a
ZA		 1009void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1010{
1011 struct kvm *kvm = vcpu->kvm;
f38e098f 1012 u64 offset, ns, elapsed;
99e3e30a 1013 unsigned long flags;
46543ba4 1014 s64 sdiff;
99e3e30a
ZA		 1015
1016 spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1017 offset = data - native_read_tsc();
759379dd 1018 ns = get_kernel_ns();
f38e098f 1019 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 1020 sdiff = data - kvm->arch.last_tsc_write;
1021 if (sdiff < 0)
1022 sdiff = -sdiff;
f38e098f
ZA		 1023
1024 /*
46543ba4 1025 * Special case: close write to TSC within 5 seconds of
f38e098f 1026 * another CPU is interpreted as an attempt to synchronize
46543ba4
ZA		 1027 * The 5 seconds is to accomodate host load / swapping as
1028 * well as any reset of TSC during the boot process.
f38e098f
ZA		 1029 *
1030 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 1031 * or make a best guest using elapsed value.
f38e098f 1032 */
46543ba4
ZA		 1033 if (sdiff < nsec_to_cycles(5ULL * NSEC_PER_SEC) &&
1034 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 1035 if (!check_tsc_unstable()) {
1036 offset = kvm->arch.last_tsc_offset;
1037 pr_debug("kvm: matched tsc offset for %llu\n", data);
1038 } else {
759379dd
ZA		 1039 u64 delta = nsec_to_cycles(elapsed);
1040 offset += delta;
1041 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1042 }
1043 ns = kvm->arch.last_tsc_nsec;
1044 }
1045 kvm->arch.last_tsc_nsec = ns;
1046 kvm->arch.last_tsc_write = data;
1047 kvm->arch.last_tsc_offset = offset;
99e3e30a
ZA		 1048 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1049 spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1050
1051 /* Reset of TSC must disable overshoot protection below */
1052 vcpu->arch.hv_clock.tsc_timestamp = 0;
c285545f
ZA		 1053 vcpu->arch.last_tsc_write = data;
1054 vcpu->arch.last_tsc_nsec = ns;
99e3e30a
ZA		 1055}
1056EXPORT_SYMBOL_GPL(kvm_write_tsc);
1057
34c238a1 1058static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1059{
18068523
GOC		 1060 unsigned long flags;
1061 struct kvm_vcpu_arch *vcpu = &v->arch;
1062 void *shared_kaddr;
463656c0 1063 unsigned long this_tsc_khz;
1d5f066e
ZA		 1064 s64 kernel_ns, max_kernel_ns;
1065 u64 tsc_timestamp;
18068523 1066
18068523
GOC		 1067 /* Keep irq disabled to prevent changes to the clock */
1068 local_irq_save(flags);
1d5f066e 1069 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
759379dd 1070 kernel_ns = get_kernel_ns();
8cfdc000 1071 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
18068523 1072
8cfdc000 1073 if (unlikely(this_tsc_khz == 0)) {
c285545f 1074 local_irq_restore(flags);
34c238a1 1075 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1076 return 1;
1077 }
18068523 1078
c285545f
ZA		 1079 /*
1080 * We may have to catch up the TSC to match elapsed wall clock
1081 * time for two reasons, even if kvmclock is used.
1082 * 1) CPU could have been running below the maximum TSC rate
1083 * 2) Broken TSC compensation resets the base at each VCPU
1084 * entry to avoid unknown leaps of TSC even when running
1085 * again on the same CPU. This may cause apparent elapsed
1086 * time to disappear, and the guest to stand still or run
1087 * very slowly.
1088 */
1089 if (vcpu->tsc_catchup) {
1090 u64 tsc = compute_guest_tsc(v, kernel_ns);
1091 if (tsc > tsc_timestamp) {
1092 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1093 tsc_timestamp = tsc;
1094 }
50d0a0f9
GH		 1095 }
1096
18068523
GOC		 1097 local_irq_restore(flags);
1098
c285545f
ZA		 1099 if (!vcpu->time_page)
1100 return 0;
18068523 1101
1d5f066e
ZA		 1102 /*
1103 * Time as measured by the TSC may go backwards when resetting the base
1104 * tsc_timestamp. The reason for this is that the TSC resolution is
1105 * higher than the resolution of the other clock scales. Thus, many
1106 * possible measurments of the TSC correspond to one measurement of any
1107 * other clock, and so a spread of values is possible. This is not a
1108 * problem for the computation of the nanosecond clock; with TSC rates
1109 * around 1GHZ, there can only be a few cycles which correspond to one
1110 * nanosecond value, and any path through this code will inevitably
1111 * take longer than that. However, with the kernel_ns value itself,
1112 * the precision may be much lower, down to HZ granularity. If the
1113 * first sampling of TSC against kernel_ns ends in the low part of the
1114 * range, and the second in the high end of the range, we can get:
1115 *
1116 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1117 *
1118 * As the sampling errors potentially range in the thousands of cycles,
1119 * it is possible such a time value has already been observed by the
1120 * guest. To protect against this, we must compute the system time as
1121 * observed by the guest and ensure the new system time is greater.
1122 */
1123 max_kernel_ns = 0;
1124 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1125 max_kernel_ns = vcpu->last_guest_tsc -
1126 vcpu->hv_clock.tsc_timestamp;
1127 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1128 vcpu->hv_clock.tsc_to_system_mul,
1129 vcpu->hv_clock.tsc_shift);
1130 max_kernel_ns += vcpu->last_kernel_ns;
1131 }
afbcf7ab 1132
e48672fa 1133 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1134 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1135 &vcpu->hv_clock.tsc_shift,
1136 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1137 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1138 }
1139
1d5f066e
ZA		 1140 if (max_kernel_ns > kernel_ns)
1141 kernel_ns = max_kernel_ns;
1142
8cfdc000 1143 /* With all the info we got, fill in the values */
1d5f066e 1144 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1145 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1146 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1147 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1148 vcpu->hv_clock.flags = 0;
1149
18068523
GOC		 1150 /*
1151 * The interface expects us to write an even number signaling that the
1152 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1153 * state, we just increase by 2 at the end.
18068523 1154 */
50d0a0f9 1155 vcpu->hv_clock.version += 2;
18068523
GOC		 1156
1157 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1158
1159 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1160 sizeof(vcpu->hv_clock));
18068523
GOC		 1161
1162 kunmap_atomic(shared_kaddr, KM_USER0);
1163
1164 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1165 return 0;
c8076604
GH		 1166}
1167
9ba075a6
AK		 1168static bool msr_mtrr_valid(unsigned msr)
1169{
1170 switch (msr) {
1171 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1172 case MSR_MTRRfix64K_00000:
1173 case MSR_MTRRfix16K_80000:
1174 case MSR_MTRRfix16K_A0000:
1175 case MSR_MTRRfix4K_C0000:
1176 case MSR_MTRRfix4K_C8000:
1177 case MSR_MTRRfix4K_D0000:
1178 case MSR_MTRRfix4K_D8000:
1179 case MSR_MTRRfix4K_E0000:
1180 case MSR_MTRRfix4K_E8000:
1181 case MSR_MTRRfix4K_F0000:
1182 case MSR_MTRRfix4K_F8000:
1183 case MSR_MTRRdefType:
1184 case MSR_IA32_CR_PAT:
1185 return true;
1186 case 0x2f8:
1187 return true;
1188 }
1189 return false;
1190}
1191
d6289b93
MT		 1192static bool valid_pat_type(unsigned t)
1193{
1194 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1195}
1196
1197static bool valid_mtrr_type(unsigned t)
1198{
1199 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1200}
1201
1202static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1203{
1204 int i;
1205
1206 if (!msr_mtrr_valid(msr))
1207 return false;
1208
1209 if (msr == MSR_IA32_CR_PAT) {
1210 for (i = 0; i < 8; i++)
1211 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1212 return false;
1213 return true;
1214 } else if (msr == MSR_MTRRdefType) {
1215 if (data & ~0xcff)
1216 return false;
1217 return valid_mtrr_type(data & 0xff);
1218 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1219 for (i = 0; i < 8 ; i++)
1220 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1221 return false;
1222 return true;
1223 }
1224
1225 /* variable MTRRs */
1226 return valid_mtrr_type(data & 0xff);
1227}
1228
9ba075a6
AK		 1229static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1230{
0bed3b56
SY		 1231 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1232
d6289b93 1233 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1234 return 1;
1235
0bed3b56
SY		 1236 if (msr == MSR_MTRRdefType) {
1237 vcpu->arch.mtrr_state.def_type = data;
1238 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1239 } else if (msr == MSR_MTRRfix64K_00000)
1240 p[0] = data;
1241 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1242 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1243 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1244 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1245 else if (msr == MSR_IA32_CR_PAT)
1246 vcpu->arch.pat = data;
1247 else { /* Variable MTRRs */
1248 int idx, is_mtrr_mask;
1249 u64 *pt;
1250
1251 idx = (msr - 0x200) / 2;
1252 is_mtrr_mask = msr - 0x200 - 2 * idx;
1253 if (!is_mtrr_mask)
1254 pt =
1255 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1256 else
1257 pt =
1258 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1259 *pt = data;
1260 }
1261
1262 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1263 return 0;
1264}
15c4a640 1265
890ca9ae 1266static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1267{
890ca9ae
HY		 1268 u64 mcg_cap = vcpu->arch.mcg_cap;
1269 unsigned bank_num = mcg_cap & 0xff;
1270
15c4a640 1271 switch (msr) {
15c4a640 1272 case MSR_IA32_MCG_STATUS:
890ca9ae 1273 vcpu->arch.mcg_status = data;
15c4a640 1274 break;
c7ac679c 1275 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1276 if (!(mcg_cap & MCG_CTL_P))
1277 return 1;
1278 if (data != 0 && data != ~(u64)0)
1279 return -1;
1280 vcpu->arch.mcg_ctl = data;
1281 break;
1282 default:
1283 if (msr >= MSR_IA32_MC0_CTL &&
1284 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1285 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1286 /* only 0 or all 1s can be written to IA32_MCi_CTL
1287 * some Linux kernels though clear bit 10 in bank 4 to
1288 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1289 * this to avoid an uncatched #GP in the guest
1290 */
890ca9ae 1291 if ((offset & 0x3) == 0 &&
114be429 1292 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1293 return -1;
1294 vcpu->arch.mce_banks[offset] = data;
1295 break;
1296 }
1297 return 1;
1298 }
1299 return 0;
1300}
1301
ffde22ac
ES		 1302static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1303{
1304 struct kvm *kvm = vcpu->kvm;
1305 int lm = is_long_mode(vcpu);
1306 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1307 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1308 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1309 : kvm->arch.xen_hvm_config.blob_size_32;
1310 u32 page_num = data & ~PAGE_MASK;
1311 u64 page_addr = data & PAGE_MASK;
1312 u8 *page;
1313 int r;
1314
1315 r = -E2BIG;
1316 if (page_num >= blob_size)
1317 goto out;
1318 r = -ENOMEM;
1319 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1320 if (!page)
1321 goto out;
1322 r = -EFAULT;
1323 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1324 goto out_free;
1325 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1326 goto out_free;
1327 r = 0;
1328out_free:
1329 kfree(page);
1330out:
1331 return r;
1332}
1333
55cd8e5a
GN		 1334static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1335{
1336 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1337}
1338
1339static bool kvm_hv_msr_partition_wide(u32 msr)
1340{
1341 bool r = false;
1342 switch (msr) {
1343 case HV_X64_MSR_GUEST_OS_ID:
1344 case HV_X64_MSR_HYPERCALL:
1345 r = true;
1346 break;
1347 }
1348
1349 return r;
1350}
1351
1352static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1353{
1354 struct kvm *kvm = vcpu->kvm;
1355
1356 switch (msr) {
1357 case HV_X64_MSR_GUEST_OS_ID:
1358 kvm->arch.hv_guest_os_id = data;
1359 /* setting guest os id to zero disables hypercall page */
1360 if (!kvm->arch.hv_guest_os_id)
1361 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1362 break;
1363 case HV_X64_MSR_HYPERCALL: {
1364 u64 gfn;
1365 unsigned long addr;
1366 u8 instructions[4];
1367
1368 /* if guest os id is not set hypercall should remain disabled */
1369 if (!kvm->arch.hv_guest_os_id)
1370 break;
1371 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1372 kvm->arch.hv_hypercall = data;
1373 break;
1374 }
1375 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1376 addr = gfn_to_hva(kvm, gfn);
1377 if (kvm_is_error_hva(addr))
1378 return 1;
1379 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1380 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1381 if (copy_to_user((void __user *)addr, instructions, 4))
1382 return 1;
1383 kvm->arch.hv_hypercall = data;
1384 break;
1385 }
1386 default:
1387 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1388 "data 0x%llx\n", msr, data);
1389 return 1;
1390 }
1391 return 0;
1392}
1393
1394static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1395{
10388a07
GN		 1396 switch (msr) {
1397 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1398 unsigned long addr;
55cd8e5a 1399
10388a07
GN		 1400 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1401 vcpu->arch.hv_vapic = data;
1402 break;
1403 }
1404 addr = gfn_to_hva(vcpu->kvm, data >>
1405 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1406 if (kvm_is_error_hva(addr))
1407 return 1;
1408 if (clear_user((void __user *)addr, PAGE_SIZE))
1409 return 1;
1410 vcpu->arch.hv_vapic = data;
1411 break;
1412 }
1413 case HV_X64_MSR_EOI:
1414 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1415 case HV_X64_MSR_ICR:
1416 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1417 case HV_X64_MSR_TPR:
1418 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1419 default:
1420 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1421 "data 0x%llx\n", msr, data);
1422 return 1;
1423 }
1424
1425 return 0;
55cd8e5a
GN		 1426}
1427
15c4a640
CO		 1428int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1429{
1430 switch (msr) {
15c4a640 1431 case MSR_EFER:
b69e8cae 1432 return set_efer(vcpu, data);
8f1589d9
AP		 1433 case MSR_K7_HWCR:
1434 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1435 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1436 if (data != 0) {
1437 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1438 data);
1439 return 1;
1440 }
15c4a640 1441 break;
f7c6d140
AP		 1442 case MSR_FAM10H_MMIO_CONF_BASE:
1443 if (data != 0) {
1444 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1445 "0x%llx\n", data);
1446 return 1;
1447 }
15c4a640 1448 break;
c323c0e5 1449 case MSR_AMD64_NB_CFG:
c7ac679c 1450 break;
b5e2fec0
AG		 1451 case MSR_IA32_DEBUGCTLMSR:
1452 if (!data) {
1453 /* We support the non-activated case already */
1454 break;
1455 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1456 /* Values other than LBR and BTF are vendor-specific,
1457 thus reserved and should throw a #GP */
1458 return 1;
1459 }
1460 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1461 __func__, data);
1462 break;
15c4a640
CO		 1463 case MSR_IA32_UCODE_REV:
1464 case MSR_IA32_UCODE_WRITE:
61a6bd67 1465 case MSR_VM_HSAVE_PA:
6098ca93 1466 case MSR_AMD64_PATCH_LOADER:
15c4a640 1467 break;
9ba075a6
AK		 1468 case 0x200 ... 0x2ff:
1469 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1470 case MSR_IA32_APICBASE:
1471 kvm_set_apic_base(vcpu, data);
1472 break;
0105d1a5
GN		 1473 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1474 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1475 case MSR_IA32_MISC_ENABLE:
ad312c7c 1476 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1477 break;
11c6bffa 1478 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1479 case MSR_KVM_WALL_CLOCK:
1480 vcpu->kvm->arch.wall_clock = data;
1481 kvm_write_wall_clock(vcpu->kvm, data);
1482 break;
11c6bffa 1483 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1484 case MSR_KVM_SYSTEM_TIME: {
1485 if (vcpu->arch.time_page) {
1486 kvm_release_page_dirty(vcpu->arch.time_page);
1487 vcpu->arch.time_page = NULL;
1488 }
1489
1490 vcpu->arch.time = data;
c285545f 1491 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1492
1493 /* we verify if the enable bit is set... */
1494 if (!(data & 1))
1495 break;
1496
1497 /* ...but clean it before doing the actual write */
1498 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1499
18068523
GOC		 1500 vcpu->arch.time_page =
1501 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1502
1503 if (is_error_page(vcpu->arch.time_page)) {
1504 kvm_release_page_clean(vcpu->arch.time_page);
1505 vcpu->arch.time_page = NULL;
1506 }
18068523
GOC		 1507 break;
1508 }
890ca9ae
HY		 1509 case MSR_IA32_MCG_CTL:
1510 case MSR_IA32_MCG_STATUS:
1511 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1512 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1513
1514 /* Performance counters are not protected by a CPUID bit,
1515 * so we should check all of them in the generic path for the sake of
1516 * cross vendor migration.
1517 * Writing a zero into the event select MSRs disables them,
1518 * which we perfectly emulate ;-). Any other value should be at least
1519 * reported, some guests depend on them.
1520 */
1521 case MSR_P6_EVNTSEL0:
1522 case MSR_P6_EVNTSEL1:
1523 case MSR_K7_EVNTSEL0:
1524 case MSR_K7_EVNTSEL1:
1525 case MSR_K7_EVNTSEL2:
1526 case MSR_K7_EVNTSEL3:
1527 if (data != 0)
1528 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1529 "0x%x data 0x%llx\n", msr, data);
1530 break;
1531 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1532 * so we ignore writes to make it happy.
1533 */
1534 case MSR_P6_PERFCTR0:
1535 case MSR_P6_PERFCTR1:
1536 case MSR_K7_PERFCTR0:
1537 case MSR_K7_PERFCTR1:
1538 case MSR_K7_PERFCTR2:
1539 case MSR_K7_PERFCTR3:
1540 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1541 "0x%x data 0x%llx\n", msr, data);
1542 break;
84e0cefa
JS		 1543 case MSR_K7_CLK_CTL:
1544 /*
1545 * Ignore all writes to this no longer documented MSR.
1546 * Writes are only relevant for old K7 processors,
1547 * all pre-dating SVM, but a recommended workaround from
1548 * AMD for these chips. It is possible to speicify the
1549 * affected processor models on the command line, hence
1550 * the need to ignore the workaround.
1551 */
1552 break;
55cd8e5a
GN		 1553 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1554 if (kvm_hv_msr_partition_wide(msr)) {
1555 int r;
1556 mutex_lock(&vcpu->kvm->lock);
1557 r = set_msr_hyperv_pw(vcpu, msr, data);
1558 mutex_unlock(&vcpu->kvm->lock);
1559 return r;
1560 } else
1561 return set_msr_hyperv(vcpu, msr, data);
1562 break;
15c4a640 1563 default:
ffde22ac
ES		 1564 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1565 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1566 if (!ignore_msrs) {
1567 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1568 msr, data);
1569 return 1;
1570 } else {
1571 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1572 msr, data);
1573 break;
1574 }
15c4a640
CO		 1575 }
1576 return 0;
1577}
1578EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1579
1580
1581/*
1582 * Reads an msr value (of 'msr_index') into 'pdata'.
1583 * Returns 0 on success, non-0 otherwise.
1584 * Assumes vcpu_load() was already called.
1585 */
1586int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1587{
1588 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1589}
1590
9ba075a6
AK		 1591static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1592{
0bed3b56
SY		 1593 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1594
9ba075a6
AK		 1595 if (!msr_mtrr_valid(msr))
1596 return 1;
1597
0bed3b56
SY		 1598 if (msr == MSR_MTRRdefType)
1599 *pdata = vcpu->arch.mtrr_state.def_type +
1600 (vcpu->arch.mtrr_state.enabled << 10);
1601 else if (msr == MSR_MTRRfix64K_00000)
1602 *pdata = p[0];
1603 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1604 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1605 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1606 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1607 else if (msr == MSR_IA32_CR_PAT)
1608 *pdata = vcpu->arch.pat;
1609 else { /* Variable MTRRs */
1610 int idx, is_mtrr_mask;
1611 u64 *pt;
1612
1613 idx = (msr - 0x200) / 2;
1614 is_mtrr_mask = msr - 0x200 - 2 * idx;
1615 if (!is_mtrr_mask)
1616 pt =
1617 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1618 else
1619 pt =
1620 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1621 *pdata = *pt;
1622 }
1623
9ba075a6
AK		 1624 return 0;
1625}
1626
890ca9ae 1627static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1628{
1629 u64 data;
890ca9ae
HY		 1630 u64 mcg_cap = vcpu->arch.mcg_cap;
1631 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1632
1633 switch (msr) {
15c4a640
CO		 1634 case MSR_IA32_P5_MC_ADDR:
1635 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1636 data = 0;
1637 break;
15c4a640 1638 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1639 data = vcpu->arch.mcg_cap;
1640 break;
c7ac679c 1641 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1642 if (!(mcg_cap & MCG_CTL_P))
1643 return 1;
1644 data = vcpu->arch.mcg_ctl;
1645 break;
1646 case MSR_IA32_MCG_STATUS:
1647 data = vcpu->arch.mcg_status;
1648 break;
1649 default:
1650 if (msr >= MSR_IA32_MC0_CTL &&
1651 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1652 u32 offset = msr - MSR_IA32_MC0_CTL;
1653 data = vcpu->arch.mce_banks[offset];
1654 break;
1655 }
1656 return 1;
1657 }
1658 *pdata = data;
1659 return 0;
1660}
1661
55cd8e5a
GN		 1662static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1663{
1664 u64 data = 0;
1665 struct kvm *kvm = vcpu->kvm;
1666
1667 switch (msr) {
1668 case HV_X64_MSR_GUEST_OS_ID:
1669 data = kvm->arch.hv_guest_os_id;
1670 break;
1671 case HV_X64_MSR_HYPERCALL:
1672 data = kvm->arch.hv_hypercall;
1673 break;
1674 default:
1675 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1676 return 1;
1677 }
1678
1679 *pdata = data;
1680 return 0;
1681}
1682
1683static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1684{
1685 u64 data = 0;
1686
1687 switch (msr) {
1688 case HV_X64_MSR_VP_INDEX: {
1689 int r;
1690 struct kvm_vcpu *v;
1691 kvm_for_each_vcpu(r, v, vcpu->kvm)
1692 if (v == vcpu)
1693 data = r;
1694 break;
1695 }
10388a07
GN		 1696 case HV_X64_MSR_EOI:
1697 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1698 case HV_X64_MSR_ICR:
1699 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1700 case HV_X64_MSR_TPR:
1701 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1702 default:
1703 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1704 return 1;
1705 }
1706 *pdata = data;
1707 return 0;
1708}
1709
890ca9ae
HY		 1710int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1711{
1712 u64 data;
1713
1714 switch (msr) {
890ca9ae 1715 case MSR_IA32_PLATFORM_ID:
15c4a640 1716 case MSR_IA32_UCODE_REV:
15c4a640 1717 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1718 case MSR_IA32_DEBUGCTLMSR:
1719 case MSR_IA32_LASTBRANCHFROMIP:
1720 case MSR_IA32_LASTBRANCHTOIP:
1721 case MSR_IA32_LASTINTFROMIP:
1722 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1723 case MSR_K8_SYSCFG:
1724 case MSR_K7_HWCR:
61a6bd67 1725 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1726 case MSR_P6_PERFCTR0:
1727 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1728 case MSR_P6_EVNTSEL0:
1729 case MSR_P6_EVNTSEL1:
9e699624 1730 case MSR_K7_EVNTSEL0:
1f3ee616 1731 case MSR_K7_PERFCTR0:
1fdbd48c 1732 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1733 case MSR_AMD64_NB_CFG:
f7c6d140 1734 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1735 data = 0;
1736 break;
9ba075a6
AK		 1737 case MSR_MTRRcap:
1738 data = 0x500 | KVM_NR_VAR_MTRR;
1739 break;
1740 case 0x200 ... 0x2ff:
1741 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1742 case 0xcd: /* fsb frequency */
1743 data = 3;
1744 break;
7b914098
JS		 1745 /*
1746 * MSR_EBC_FREQUENCY_ID
1747 * Conservative value valid for even the basic CPU models.
1748 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1749 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1750 * and 266MHz for model 3, or 4. Set Core Clock
1751 * Frequency to System Bus Frequency Ratio to 1 (bits
1752 * 31:24) even though these are only valid for CPU
1753 * models > 2, however guests may end up dividing or
1754 * multiplying by zero otherwise.
1755 */
1756 case MSR_EBC_FREQUENCY_ID:
1757 data = 1 << 24;
1758 break;
15c4a640
CO		 1759 case MSR_IA32_APICBASE:
1760 data = kvm_get_apic_base(vcpu);
1761 break;
0105d1a5
GN		 1762 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1763 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1764 break;
15c4a640 1765 case MSR_IA32_MISC_ENABLE:
ad312c7c 1766 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1767 break;
847f0ad8
AG		 1768 case MSR_IA32_PERF_STATUS:
1769 /* TSC increment by tick */
1770 data = 1000ULL;
1771 /* CPU multiplier */
1772 data |= (((uint64_t)4ULL) << 40);
1773 break;
15c4a640 1774 case MSR_EFER:
f6801dff 1775 data = vcpu->arch.efer;
15c4a640 1776 break;
18068523 1777 case MSR_KVM_WALL_CLOCK:
11c6bffa 1778 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1779 data = vcpu->kvm->arch.wall_clock;
1780 break;
1781 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1782 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1783 data = vcpu->arch.time;
1784 break;
890ca9ae
HY		 1785 case MSR_IA32_P5_MC_ADDR:
1786 case MSR_IA32_P5_MC_TYPE:
1787 case MSR_IA32_MCG_CAP:
1788 case MSR_IA32_MCG_CTL:
1789 case MSR_IA32_MCG_STATUS:
1790 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1791 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1792 case MSR_K7_CLK_CTL:
1793 /*
1794 * Provide expected ramp-up count for K7. All other
1795 * are set to zero, indicating minimum divisors for
1796 * every field.
1797 *
1798 * This prevents guest kernels on AMD host with CPU
1799 * type 6, model 8 and higher from exploding due to
1800 * the rdmsr failing.
1801 */
1802 data = 0x20000000;
1803 break;
55cd8e5a
GN		 1804 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1805 if (kvm_hv_msr_partition_wide(msr)) {
1806 int r;
1807 mutex_lock(&vcpu->kvm->lock);
1808 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1809 mutex_unlock(&vcpu->kvm->lock);
1810 return r;
1811 } else
1812 return get_msr_hyperv(vcpu, msr, pdata);
1813 break;
15c4a640 1814 default:
ed85c068
AP		 1815 if (!ignore_msrs) {
1816 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1817 return 1;
1818 } else {
1819 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1820 data = 0;
1821 }
1822 break;
15c4a640
CO		 1823 }
1824 *pdata = data;
1825 return 0;
1826}
1827EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1828
313a3dc7
CO		 1829/*
1830 * Read or write a bunch of msrs. All parameters are kernel addresses.
1831 *
1832 * @return number of msrs set successfully.
1833 */
1834static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1835 struct kvm_msr_entry *entries,
1836 int (*do_msr)(struct kvm_vcpu *vcpu,
1837 unsigned index, u64 *data))
1838{
f656ce01 1839 int i, idx;
313a3dc7 1840
f656ce01 1841 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1842 for (i = 0; i < msrs->nmsrs; ++i)
1843 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1844 break;
f656ce01 1845 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1846
313a3dc7
CO		 1847 return i;
1848}
1849
1850/*
1851 * Read or write a bunch of msrs. Parameters are user addresses.
1852 *
1853 * @return number of msrs set successfully.
1854 */
1855static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1856 int (*do_msr)(struct kvm_vcpu *vcpu,
1857 unsigned index, u64 *data),
1858 int writeback)
1859{
1860 struct kvm_msrs msrs;
1861 struct kvm_msr_entry *entries;
1862 int r, n;
1863 unsigned size;
1864
1865 r = -EFAULT;
1866 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1867 goto out;
1868
1869 r = -E2BIG;
1870 if (msrs.nmsrs >= MAX_IO_MSRS)
1871 goto out;
1872
1873 r = -ENOMEM;
1874 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1875 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1876 if (!entries)
1877 goto out;
1878
1879 r = -EFAULT;
1880 if (copy_from_user(entries, user_msrs->entries, size))
1881 goto out_free;
1882
1883 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1884 if (r < 0)
1885 goto out_free;
1886
1887 r = -EFAULT;
1888 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1889 goto out_free;
1890
1891 r = n;
1892
1893out_free:
7a73c028 1894 kfree(entries);
313a3dc7
CO		 1895out:
1896 return r;
1897}
1898
018d00d2
ZX		 1899int kvm_dev_ioctl_check_extension(long ext)
1900{
1901 int r;
1902
1903 switch (ext) {
1904 case KVM_CAP_IRQCHIP:
1905 case KVM_CAP_HLT:
1906 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1907 case KVM_CAP_SET_TSS_ADDR:
07716717 1908 case KVM_CAP_EXT_CPUID:
c8076604 1909 case KVM_CAP_CLOCKSOURCE:
7837699f 1910 case KVM_CAP_PIT:
a28e4f5a 1911 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1912 case KVM_CAP_MP_STATE:
ed848624 1913 case KVM_CAP_SYNC_MMU:
52d939a0 1914 case KVM_CAP_REINJECT_CONTROL:
4925663a 1915 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1916 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1917 case KVM_CAP_IRQFD:
d34e6b17 1918 case KVM_CAP_IOEVENTFD:
c5ff41ce 1919 case KVM_CAP_PIT2:
e9f42757 1920 case KVM_CAP_PIT_STATE2:
b927a3ce 1921 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1922 case KVM_CAP_XEN_HVM:
afbcf7ab 1923 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1924 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1925 case KVM_CAP_HYPERV:
10388a07 1926 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1927 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1928 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1929 case KVM_CAP_DEBUGREGS:
d2be1651 1930 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 1931 case KVM_CAP_XSAVE:
018d00d2
ZX		 1932 r = 1;
1933 break;
542472b5
LV		 1934 case KVM_CAP_COALESCED_MMIO:
1935 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1936 break;
774ead3a
AK		 1937 case KVM_CAP_VAPIC:
1938 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1939 break;
f725230a
AK		 1940 case KVM_CAP_NR_VCPUS:
1941 r = KVM_MAX_VCPUS;
1942 break;
a988b910
AK		 1943 case KVM_CAP_NR_MEMSLOTS:
1944 r = KVM_MEMORY_SLOTS;
1945 break;
a68a6a72
MT		 1946 case KVM_CAP_PV_MMU: /* obsolete */
1947 r = 0;
2f333bcb 1948 break;
62c476c7 1949 case KVM_CAP_IOMMU:
19de40a8 1950 r = iommu_found();
62c476c7 1951 break;
890ca9ae
HY		 1952 case KVM_CAP_MCE:
1953 r = KVM_MAX_MCE_BANKS;
1954 break;
2d5b5a66
SY		 1955 case KVM_CAP_XCRS:
1956 r = cpu_has_xsave;
1957 break;
018d00d2
ZX		 1958 default:
1959 r = 0;
1960 break;
1961 }
1962 return r;
1963
1964}
1965
043405e1
CO		 1966long kvm_arch_dev_ioctl(struct file *filp,
1967 unsigned int ioctl, unsigned long arg)
1968{
1969 void __user *argp = (void __user *)arg;
1970 long r;
1971
1972 switch (ioctl) {
1973 case KVM_GET_MSR_INDEX_LIST: {
1974 struct kvm_msr_list __user *user_msr_list = argp;
1975 struct kvm_msr_list msr_list;
1976 unsigned n;
1977
1978 r = -EFAULT;
1979 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1980 goto out;
1981 n = msr_list.nmsrs;
1982 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1983 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1984 goto out;
1985 r = -E2BIG;
e125e7b6 1986 if (n < msr_list.nmsrs)
043405e1
CO		 1987 goto out;
1988 r = -EFAULT;
1989 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1990 num_msrs_to_save * sizeof(u32)))
1991 goto out;
e125e7b6 1992 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1993 &emulated_msrs,
1994 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1995 goto out;
1996 r = 0;
1997 break;
1998 }
674eea0f
AK		 1999 case KVM_GET_SUPPORTED_CPUID: {
2000 struct kvm_cpuid2 __user *cpuid_arg = argp;
2001 struct kvm_cpuid2 cpuid;
2002
2003 r = -EFAULT;
2004 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2005 goto out;
2006 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2007 cpuid_arg->entries);
674eea0f
AK		 2008 if (r)
2009 goto out;
2010
2011 r = -EFAULT;
2012 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2013 goto out;
2014 r = 0;
2015 break;
2016 }
890ca9ae
HY		 2017 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2018 u64 mce_cap;
2019
2020 mce_cap = KVM_MCE_CAP_SUPPORTED;
2021 r = -EFAULT;
2022 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2023 goto out;
2024 r = 0;
2025 break;
2026 }
043405e1
CO		 2027 default:
2028 r = -EINVAL;
2029 }
2030out:
2031 return r;
2032}
2033
f5f48ee1
SY		 2034static void wbinvd_ipi(void *garbage)
2035{
2036 wbinvd();
2037}
2038
2039static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2040{
2041 return vcpu->kvm->arch.iommu_domain &&
2042 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2043}
2044
313a3dc7
CO		 2045void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2046{
f5f48ee1
SY		 2047 /* Address WBINVD may be executed by guest */
2048 if (need_emulate_wbinvd(vcpu)) {
2049 if (kvm_x86_ops->has_wbinvd_exit())
2050 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2051 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2052 smp_call_function_single(vcpu->cpu,
2053 wbinvd_ipi, NULL, 1);
2054 }
2055
313a3dc7 2056 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2057 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa
ZA		 2058 /* Make sure TSC doesn't go backwards */
2059 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2060 native_read_tsc() - vcpu->arch.last_host_tsc;
2061 if (tsc_delta < 0)
2062 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2063 if (check_tsc_unstable()) {
e48672fa 2064 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
c285545f
ZA		 2065 vcpu->arch.tsc_catchup = 1;
2066 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2067 }
2068 if (vcpu->cpu != cpu)
2069 kvm_migrate_timers(vcpu);
e48672fa 2070 vcpu->cpu = cpu;
6b7d7e76 2071 }
313a3dc7
CO		 2072}
2073
2074void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2075{
02daab21 2076 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2077 kvm_put_guest_fpu(vcpu);
e48672fa 2078 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2079}
2080
07716717 2081static int is_efer_nx(void)
313a3dc7 2082{
e286e86e 2083 unsigned long long efer = 0;
313a3dc7 2084
e286e86e 2085 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 2086 return efer & EFER_NX;
2087}
2088
2089static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2090{
2091 int i;
2092 struct kvm_cpuid_entry2 *e, *entry;
2093
313a3dc7 2094 entry = NULL;
ad312c7c
ZX		 2095 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2096 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 2097 if (e->function == 0x80000001) {
2098 entry = e;
2099 break;
2100 }
2101 }
07716717 2102 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 2103 entry->edx &= ~(1 << 20);
2104 printk(KERN_INFO "kvm: guest NX capability removed\n");
2105 }
2106}
2107
07716717 2108/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 2109static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2110 struct kvm_cpuid *cpuid,
2111 struct kvm_cpuid_entry __user *entries)
07716717
DK		 2112{
2113 int r, i;
2114 struct kvm_cpuid_entry *cpuid_entries;
2115
2116 r = -E2BIG;
2117 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2118 goto out;
2119 r = -ENOMEM;
2120 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2121 if (!cpuid_entries)
2122 goto out;
2123 r = -EFAULT;
2124 if (copy_from_user(cpuid_entries, entries,
2125 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2126 goto out_free;
2127 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 2128 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2129 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2130 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2131 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2132 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2133 vcpu->arch.cpuid_entries[i].index = 0;
2134 vcpu->arch.cpuid_entries[i].flags = 0;
2135 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2136 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2137 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2138 }
2139 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2140 cpuid_fix_nx_cap(vcpu);
2141 r = 0;
fc61b800 2142 kvm_apic_set_version(vcpu);
0e851880 2143 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2144 update_cpuid(vcpu);
07716717
DK		 2145
2146out_free:
2147 vfree(cpuid_entries);
2148out:
2149 return r;
2150}
2151
2152static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2153 struct kvm_cpuid2 *cpuid,
2154 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2155{
2156 int r;
2157
2158 r = -E2BIG;
2159 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2160 goto out;
2161 r = -EFAULT;
ad312c7c 2162 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2163 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2164 goto out;
ad312c7c 2165 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2166 kvm_apic_set_version(vcpu);
0e851880 2167 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2168 update_cpuid(vcpu);
313a3dc7
CO		 2169 return 0;
2170
2171out:
2172 return r;
2173}
2174
07716717 2175static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2176 struct kvm_cpuid2 *cpuid,
2177 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2178{
2179 int r;
2180
2181 r = -E2BIG;
ad312c7c 2182 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2183 goto out;
2184 r = -EFAULT;
ad312c7c 2185 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2186 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2187 goto out;
2188 return 0;
2189
2190out:
ad312c7c 2191 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2192 return r;
2193}
2194
07716717 2195static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2196 u32 index)
07716717
DK		 2197{
2198 entry->function = function;
2199 entry->index = index;
2200 cpuid_count(entry->function, entry->index,
19355475 2201 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2202 entry->flags = 0;
2203}
2204
7faa4ee1
AK		 2205#define F(x) bit(X86_FEATURE_##x)
2206
07716717
DK		 2207static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2208 u32 index, int *nent, int maxnent)
2209{
7faa4ee1 2210 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2211#ifdef CONFIG_X86_64
17cc3935
SY		 2212 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2213 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2214 unsigned f_lm = F(LM);
2215#else
17cc3935 2216 unsigned f_gbpages = 0;
7faa4ee1 2217 unsigned f_lm = 0;
07716717 2218#endif
4e47c7a6 2219 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2220
2221 /* cpuid 1.edx */
2222 const u32 kvm_supported_word0_x86_features =
2223 F(FPU) | F(VME) | F(DE) | F(PSE) |
2224 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2225 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2226 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2227 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2228 0 /* Reserved, DS, ACPI */ | F(MMX) |
2229 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2230 0 /* HTT, TM, Reserved, PBE */;
2231 /* cpuid 0x80000001.edx */
2232 const u32 kvm_supported_word1_x86_features =
2233 F(FPU) | F(VME) | F(DE) | F(PSE) |
2234 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2235 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2236 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2237 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2238 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2239 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2240 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2241 /* cpuid 1.ecx */
2242 const u32 kvm_supported_word4_x86_features =
6c3f6041 2243 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2244 0 /* DS-CPL, VMX, SMX, EST */ |
2245 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2246 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2247 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2248 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6d886fd0
AP		 2249 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
2250 F(F16C);
7faa4ee1 2251 /* cpuid 0x80000001.ecx */
07716717 2252 const u32 kvm_supported_word6_x86_features =
4c62a2dc 2253 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
7faa4ee1 2254 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
7ef8aa72 2255 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) |
6d886fd0 2256 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM);
07716717 2257
19355475 2258 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2259 get_cpu();
2260 do_cpuid_1_ent(entry, function, index);
2261 ++*nent;
2262
2263 switch (function) {
2264 case 0:
2acf923e 2265 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2266 break;
2267 case 1:
2268 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 2269 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 2270 /* we support x2apic emulation even if host does not support
2271 * it since we emulate x2apic in software */
2272 entry->ecx |= F(X2APIC);
07716717
DK		 2273 break;
2274 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2275 * may return different values. This forces us to get_cpu() before
2276 * issuing the first command, and also to emulate this annoying behavior
2277 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2278 case 2: {
2279 int t, times = entry->eax & 0xff;
2280
2281 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2282 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2283 for (t = 1; t < times && *nent < maxnent; ++t) {
2284 do_cpuid_1_ent(&entry[t], function, 0);
2285 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2286 ++*nent;
2287 }
2288 break;
2289 }
2290 /* function 4 and 0xb have additional index. */
2291 case 4: {
14af3f3c 2292 int i, cache_type;
07716717
DK		 2293
2294 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2295 /* read more entries until cache_type is zero */
14af3f3c
HH		 2296 for (i = 1; *nent < maxnent; ++i) {
2297 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2298 if (!cache_type)
2299 break;
14af3f3c
HH		 2300 do_cpuid_1_ent(&entry[i], function, i);
2301 entry[i].flags |=
07716717
DK		 2302 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2303 ++*nent;
2304 }
2305 break;
2306 }
2307 case 0xb: {
14af3f3c 2308 int i, level_type;
07716717
DK		 2309
2310 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2311 /* read more entries until level_type is zero */
14af3f3c 2312 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2313 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2314 if (!level_type)
2315 break;
14af3f3c
HH		 2316 do_cpuid_1_ent(&entry[i], function, i);
2317 entry[i].flags |=
07716717
DK		 2318 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2319 ++*nent;
2320 }
2321 break;
2322 }
2acf923e
DC		 2323 case 0xd: {
2324 int i;
2325
2326 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2327 for (i = 1; *nent < maxnent; ++i) {
2328 if (entry[i - 1].eax == 0 && i != 2)
2329 break;
2330 do_cpuid_1_ent(&entry[i], function, i);
2331 entry[i].flags |=
2332 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2333 ++*nent;
2334 }
2335 break;
2336 }
84478c82
GC		 2337 case KVM_CPUID_SIGNATURE: {
2338 char signature[12] = "KVMKVMKVM\0\0";
2339 u32 *sigptr = (u32 *)signature;
2340 entry->eax = 0;
2341 entry->ebx = sigptr[0];
2342 entry->ecx = sigptr[1];
2343 entry->edx = sigptr[2];
2344 break;
2345 }
2346 case KVM_CPUID_FEATURES:
2347 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2348 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64
GC		 2349 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2350 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2351 entry->ebx = 0;
2352 entry->ecx = 0;
2353 entry->edx = 0;
2354 break;
07716717
DK		 2355 case 0x80000000:
2356 entry->eax = min(entry->eax, 0x8000001a);
2357 break;
2358 case 0x80000001:
2359 entry->edx &= kvm_supported_word1_x86_features;
2360 entry->ecx &= kvm_supported_word6_x86_features;
2361 break;
2362 }
d4330ef2
JR		 2363
2364 kvm_x86_ops->set_supported_cpuid(function, entry);
2365
07716717
DK		 2366 put_cpu();
2367}
2368
7faa4ee1
AK		 2369#undef F
2370
674eea0f 2371static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2372 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2373{
2374 struct kvm_cpuid_entry2 *cpuid_entries;
2375 int limit, nent = 0, r = -E2BIG;
2376 u32 func;
2377
2378 if (cpuid->nent < 1)
2379 goto out;
6a544355
AK		 2380 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2381 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2382 r = -ENOMEM;
2383 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2384 if (!cpuid_entries)
2385 goto out;
2386
2387 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2388 limit = cpuid_entries[0].eax;
2389 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2390 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2391 &nent, cpuid->nent);
07716717
DK		 2392 r = -E2BIG;
2393 if (nent >= cpuid->nent)
2394 goto out_free;
2395
2396 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2397 limit = cpuid_entries[nent - 1].eax;
2398 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2399 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2400 &nent, cpuid->nent);
84478c82
GC		 2401
2402
2403
2404 r = -E2BIG;
2405 if (nent >= cpuid->nent)
2406 goto out_free;
2407
2408 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2409 cpuid->nent);
2410
2411 r = -E2BIG;
2412 if (nent >= cpuid->nent)
2413 goto out_free;
2414
2415 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2416 cpuid->nent);
2417
cb007648
MM		 2418 r = -E2BIG;
2419 if (nent >= cpuid->nent)
2420 goto out_free;
2421
07716717
DK		 2422 r = -EFAULT;
2423 if (copy_to_user(entries, cpuid_entries,
19355475 2424 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2425 goto out_free;
2426 cpuid->nent = nent;
2427 r = 0;
2428
2429out_free:
2430 vfree(cpuid_entries);
2431out:
2432 return r;
2433}
2434
313a3dc7
CO		 2435static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2436 struct kvm_lapic_state *s)
2437{
ad312c7c 2438 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2439
2440 return 0;
2441}
2442
2443static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2444 struct kvm_lapic_state *s)
2445{
ad312c7c 2446 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2447 kvm_apic_post_state_restore(vcpu);
cb142eb7 2448 update_cr8_intercept(vcpu);
313a3dc7
CO		 2449
2450 return 0;
2451}
2452
f77bc6a4
ZX		 2453static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2454 struct kvm_interrupt *irq)
2455{
2456 if (irq->irq < 0 || irq->irq >= 256)
2457 return -EINVAL;
2458 if (irqchip_in_kernel(vcpu->kvm))
2459 return -ENXIO;
f77bc6a4 2460
66fd3f7f 2461 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2462 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2463
f77bc6a4
ZX		 2464 return 0;
2465}
2466
c4abb7c9
JK		 2467static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2468{
c4abb7c9 2469 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2470
2471 return 0;
2472}
2473
b209749f
AK		 2474static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2475 struct kvm_tpr_access_ctl *tac)
2476{
2477 if (tac->flags)
2478 return -EINVAL;
2479 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2480 return 0;
2481}
2482
890ca9ae
HY		 2483static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2484 u64 mcg_cap)
2485{
2486 int r;
2487 unsigned bank_num = mcg_cap & 0xff, bank;
2488
2489 r = -EINVAL;
a9e38c3e 2490 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2491 goto out;
2492 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2493 goto out;
2494 r = 0;
2495 vcpu->arch.mcg_cap = mcg_cap;
2496 /* Init IA32_MCG_CTL to all 1s */
2497 if (mcg_cap & MCG_CTL_P)
2498 vcpu->arch.mcg_ctl = ~(u64)0;
2499 /* Init IA32_MCi_CTL to all 1s */
2500 for (bank = 0; bank < bank_num; bank++)
2501 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2502out:
2503 return r;
2504}
2505
2506static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2507 struct kvm_x86_mce *mce)
2508{
2509 u64 mcg_cap = vcpu->arch.mcg_cap;
2510 unsigned bank_num = mcg_cap & 0xff;
2511 u64 *banks = vcpu->arch.mce_banks;
2512
2513 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2514 return -EINVAL;
2515 /*
2516 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2517 * reporting is disabled
2518 */
2519 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2520 vcpu->arch.mcg_ctl != ~(u64)0)
2521 return 0;
2522 banks += 4 * mce->bank;
2523 /*
2524 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2525 * reporting is disabled for the bank
2526 */
2527 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2528 return 0;
2529 if (mce->status & MCI_STATUS_UC) {
2530 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2531 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2532 printk(KERN_DEBUG "kvm: set_mce: "
2533 "injects mce exception while "
2534 "previous one is in progress!\n");
a8eeb04a 2535 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2536 return 0;
2537 }
2538 if (banks[1] & MCI_STATUS_VAL)
2539 mce->status |= MCI_STATUS_OVER;
2540 banks[2] = mce->addr;
2541 banks[3] = mce->misc;
2542 vcpu->arch.mcg_status = mce->mcg_status;
2543 banks[1] = mce->status;
2544 kvm_queue_exception(vcpu, MC_VECTOR);
2545 } else if (!(banks[1] & MCI_STATUS_VAL)
2546 || !(banks[1] & MCI_STATUS_UC)) {
2547 if (banks[1] & MCI_STATUS_VAL)
2548 mce->status |= MCI_STATUS_OVER;
2549 banks[2] = mce->addr;
2550 banks[3] = mce->misc;
2551 banks[1] = mce->status;
2552 } else
2553 banks[1] |= MCI_STATUS_OVER;
2554 return 0;
2555}
2556
3cfc3092
JK		 2557static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2558 struct kvm_vcpu_events *events)
2559{
03b82a30
JK		 2560 events->exception.injected =
2561 vcpu->arch.exception.pending &&
2562 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2563 events->exception.nr = vcpu->arch.exception.nr;
2564 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2565 events->exception.pad = 0;
3cfc3092
JK		 2566 events->exception.error_code = vcpu->arch.exception.error_code;
2567
03b82a30
JK		 2568 events->interrupt.injected =
2569 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2570 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2571 events->interrupt.soft = 0;
48005f64
JK		 2572 events->interrupt.shadow =
2573 kvm_x86_ops->get_interrupt_shadow(vcpu,
2574 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2575
2576 events->nmi.injected = vcpu->arch.nmi_injected;
2577 events->nmi.pending = vcpu->arch.nmi_pending;
2578 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2579 events->nmi.pad = 0;
3cfc3092
JK		 2580
2581 events->sipi_vector = vcpu->arch.sipi_vector;
2582
dab4b911 2583 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2584 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2585 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2586 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2587}
2588
2589static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2590 struct kvm_vcpu_events *events)
2591{
dab4b911 2592 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2593 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2594 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2595 return -EINVAL;
2596
3cfc3092
JK		 2597 vcpu->arch.exception.pending = events->exception.injected;
2598 vcpu->arch.exception.nr = events->exception.nr;
2599 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2600 vcpu->arch.exception.error_code = events->exception.error_code;
2601
2602 vcpu->arch.interrupt.pending = events->interrupt.injected;
2603 vcpu->arch.interrupt.nr = events->interrupt.nr;
2604 vcpu->arch.interrupt.soft = events->interrupt.soft;
2605 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2606 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2607 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2608 kvm_x86_ops->set_interrupt_shadow(vcpu,
2609 events->interrupt.shadow);
3cfc3092
JK		 2610
2611 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2612 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2613 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2614 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2615
dab4b911
JK		 2616 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2617 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2618
3842d135
AK		 2619 kvm_make_request(KVM_REQ_EVENT, vcpu);
2620
3cfc3092
JK		 2621 return 0;
2622}
2623
a1efbe77
JK		 2624static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2625 struct kvm_debugregs *dbgregs)
2626{
a1efbe77
JK		 2627 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2628 dbgregs->dr6 = vcpu->arch.dr6;
2629 dbgregs->dr7 = vcpu->arch.dr7;
2630 dbgregs->flags = 0;
97e69aa6 2631 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2632}
2633
2634static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2635 struct kvm_debugregs *dbgregs)
2636{
2637 if (dbgregs->flags)
2638 return -EINVAL;
2639
a1efbe77
JK		 2640 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2641 vcpu->arch.dr6 = dbgregs->dr6;
2642 vcpu->arch.dr7 = dbgregs->dr7;
2643
a1efbe77
JK		 2644 return 0;
2645}
2646
2d5b5a66
SY		 2647static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2648 struct kvm_xsave *guest_xsave)
2649{
2650 if (cpu_has_xsave)
2651 memcpy(guest_xsave->region,
2652 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2653 xstate_size);
2d5b5a66
SY		 2654 else {
2655 memcpy(guest_xsave->region,
2656 &vcpu->arch.guest_fpu.state->fxsave,
2657 sizeof(struct i387_fxsave_struct));
2658 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2659 XSTATE_FPSSE;
2660 }
2661}
2662
2663static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2664 struct kvm_xsave *guest_xsave)
2665{
2666 u64 xstate_bv =
2667 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2668
2669 if (cpu_has_xsave)
2670 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2671 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2672 else {
2673 if (xstate_bv & ~XSTATE_FPSSE)
2674 return -EINVAL;
2675 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2676 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2677 }
2678 return 0;
2679}
2680
2681static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2682 struct kvm_xcrs *guest_xcrs)
2683{
2684 if (!cpu_has_xsave) {
2685 guest_xcrs->nr_xcrs = 0;
2686 return;
2687 }
2688
2689 guest_xcrs->nr_xcrs = 1;
2690 guest_xcrs->flags = 0;
2691 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2692 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2693}
2694
2695static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2696 struct kvm_xcrs *guest_xcrs)
2697{
2698 int i, r = 0;
2699
2700 if (!cpu_has_xsave)
2701 return -EINVAL;
2702
2703 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2704 return -EINVAL;
2705
2706 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2707 /* Only support XCR0 currently */
2708 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2709 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2710 guest_xcrs->xcrs[0].value);
2711 break;
2712 }
2713 if (r)
2714 r = -EINVAL;
2715 return r;
2716}
2717
313a3dc7
CO		 2718long kvm_arch_vcpu_ioctl(struct file *filp,
2719 unsigned int ioctl, unsigned long arg)
2720{
2721 struct kvm_vcpu *vcpu = filp->private_data;
2722 void __user *argp = (void __user *)arg;
2723 int r;
d1ac91d8
AK		 2724 union {
2725 struct kvm_lapic_state *lapic;
2726 struct kvm_xsave *xsave;
2727 struct kvm_xcrs *xcrs;
2728 void *buffer;
2729 } u;
2730
2731 u.buffer = NULL;
313a3dc7
CO		 2732 switch (ioctl) {
2733 case KVM_GET_LAPIC: {
2204ae3c
MT		 2734 r = -EINVAL;
2735 if (!vcpu->arch.apic)
2736 goto out;
d1ac91d8 2737 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2738
b772ff36 2739 r = -ENOMEM;
d1ac91d8 2740 if (!u.lapic)
b772ff36 2741 goto out;
d1ac91d8 2742 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2743 if (r)
2744 goto out;
2745 r = -EFAULT;
d1ac91d8 2746 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2747 goto out;
2748 r = 0;
2749 break;
2750 }
2751 case KVM_SET_LAPIC: {
2204ae3c
MT		 2752 r = -EINVAL;
2753 if (!vcpu->arch.apic)
2754 goto out;
d1ac91d8 2755 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2756 r = -ENOMEM;
d1ac91d8 2757 if (!u.lapic)
b772ff36 2758 goto out;
313a3dc7 2759 r = -EFAULT;
d1ac91d8 2760 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2761 goto out;
d1ac91d8 2762 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2763 if (r)
2764 goto out;
2765 r = 0;
2766 break;
2767 }
f77bc6a4
ZX		 2768 case KVM_INTERRUPT: {
2769 struct kvm_interrupt irq;
2770
2771 r = -EFAULT;
2772 if (copy_from_user(&irq, argp, sizeof irq))
2773 goto out;
2774 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2775 if (r)
2776 goto out;
2777 r = 0;
2778 break;
2779 }
c4abb7c9
JK		 2780 case KVM_NMI: {
2781 r = kvm_vcpu_ioctl_nmi(vcpu);
2782 if (r)
2783 goto out;
2784 r = 0;
2785 break;
2786 }
313a3dc7
CO		 2787 case KVM_SET_CPUID: {
2788 struct kvm_cpuid __user *cpuid_arg = argp;
2789 struct kvm_cpuid cpuid;
2790
2791 r = -EFAULT;
2792 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2793 goto out;
2794 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2795 if (r)
2796 goto out;
2797 break;
2798 }
07716717
DK		 2799 case KVM_SET_CPUID2: {
2800 struct kvm_cpuid2 __user *cpuid_arg = argp;
2801 struct kvm_cpuid2 cpuid;
2802
2803 r = -EFAULT;
2804 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2805 goto out;
2806 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2807 cpuid_arg->entries);
07716717
DK		 2808 if (r)
2809 goto out;
2810 break;
2811 }
2812 case KVM_GET_CPUID2: {
2813 struct kvm_cpuid2 __user *cpuid_arg = argp;
2814 struct kvm_cpuid2 cpuid;
2815
2816 r = -EFAULT;
2817 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2818 goto out;
2819 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2820 cpuid_arg->entries);
07716717
DK		 2821 if (r)
2822 goto out;
2823 r = -EFAULT;
2824 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2825 goto out;
2826 r = 0;
2827 break;
2828 }
313a3dc7
CO		 2829 case KVM_GET_MSRS:
2830 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2831 break;
2832 case KVM_SET_MSRS:
2833 r = msr_io(vcpu, argp, do_set_msr, 0);
2834 break;
b209749f
AK		 2835 case KVM_TPR_ACCESS_REPORTING: {
2836 struct kvm_tpr_access_ctl tac;
2837
2838 r = -EFAULT;
2839 if (copy_from_user(&tac, argp, sizeof tac))
2840 goto out;
2841 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2842 if (r)
2843 goto out;
2844 r = -EFAULT;
2845 if (copy_to_user(argp, &tac, sizeof tac))
2846 goto out;
2847 r = 0;
2848 break;
2849 };
b93463aa
AK		 2850 case KVM_SET_VAPIC_ADDR: {
2851 struct kvm_vapic_addr va;
2852
2853 r = -EINVAL;
2854 if (!irqchip_in_kernel(vcpu->kvm))
2855 goto out;
2856 r = -EFAULT;
2857 if (copy_from_user(&va, argp, sizeof va))
2858 goto out;
2859 r = 0;
2860 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2861 break;
2862 }
890ca9ae
HY		 2863 case KVM_X86_SETUP_MCE: {
2864 u64 mcg_cap;
2865
2866 r = -EFAULT;
2867 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2868 goto out;
2869 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2870 break;
2871 }
2872 case KVM_X86_SET_MCE: {
2873 struct kvm_x86_mce mce;
2874
2875 r = -EFAULT;
2876 if (copy_from_user(&mce, argp, sizeof mce))
2877 goto out;
2878 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2879 break;
2880 }
3cfc3092
JK		 2881 case KVM_GET_VCPU_EVENTS: {
2882 struct kvm_vcpu_events events;
2883
2884 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2885
2886 r = -EFAULT;
2887 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2888 break;
2889 r = 0;
2890 break;
2891 }
2892 case KVM_SET_VCPU_EVENTS: {
2893 struct kvm_vcpu_events events;
2894
2895 r = -EFAULT;
2896 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2897 break;
2898
2899 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2900 break;
2901 }
a1efbe77
JK		 2902 case KVM_GET_DEBUGREGS: {
2903 struct kvm_debugregs dbgregs;
2904
2905 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2906
2907 r = -EFAULT;
2908 if (copy_to_user(argp, &dbgregs,
2909 sizeof(struct kvm_debugregs)))
2910 break;
2911 r = 0;
2912 break;
2913 }
2914 case KVM_SET_DEBUGREGS: {
2915 struct kvm_debugregs dbgregs;
2916
2917 r = -EFAULT;
2918 if (copy_from_user(&dbgregs, argp,
2919 sizeof(struct kvm_debugregs)))
2920 break;
2921
2922 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2923 break;
2924 }
2d5b5a66 2925 case KVM_GET_XSAVE: {
d1ac91d8 2926 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2927 r = -ENOMEM;
d1ac91d8 2928 if (!u.xsave)
2d5b5a66
SY		 2929 break;
2930
d1ac91d8 2931 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2932
2933 r = -EFAULT;
d1ac91d8 2934 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2935 break;
2936 r = 0;
2937 break;
2938 }
2939 case KVM_SET_XSAVE: {
d1ac91d8 2940 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2941 r = -ENOMEM;
d1ac91d8 2942 if (!u.xsave)
2d5b5a66
SY		 2943 break;
2944
2945 r = -EFAULT;
d1ac91d8 2946 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2947 break;
2948
d1ac91d8 2949 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2950 break;
2951 }
2952 case KVM_GET_XCRS: {
d1ac91d8 2953 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2954 r = -ENOMEM;
d1ac91d8 2955 if (!u.xcrs)
2d5b5a66
SY		 2956 break;
2957
d1ac91d8 2958 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2959
2960 r = -EFAULT;
d1ac91d8 2961 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2962 sizeof(struct kvm_xcrs)))
2963 break;
2964 r = 0;
2965 break;
2966 }
2967 case KVM_SET_XCRS: {
d1ac91d8 2968 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2969 r = -ENOMEM;
d1ac91d8 2970 if (!u.xcrs)
2d5b5a66
SY		 2971 break;
2972
2973 r = -EFAULT;
d1ac91d8 2974 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 2975 sizeof(struct kvm_xcrs)))
2976 break;
2977
d1ac91d8 2978 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2979 break;
2980 }
313a3dc7
CO		 2981 default:
2982 r = -EINVAL;
2983 }
2984out:
d1ac91d8 2985 kfree(u.buffer);
313a3dc7
CO		 2986 return r;
2987}
2988
1fe779f8
CO		 2989static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2990{
2991 int ret;
2992
2993 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2994 return -1;
2995 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2996 return ret;
2997}
2998
b927a3ce
SY		 2999static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3000 u64 ident_addr)
3001{
3002 kvm->arch.ept_identity_map_addr = ident_addr;
3003 return 0;
3004}
3005
1fe779f8
CO		 3006static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3007 u32 kvm_nr_mmu_pages)
3008{
3009 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3010 return -EINVAL;
3011
79fac95e 3012 mutex_lock(&kvm->slots_lock);
7c8a83b7 3013 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 3014
3015 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3016 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3017
7c8a83b7 3018 spin_unlock(&kvm->mmu_lock);
79fac95e 3019 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3020 return 0;
3021}
3022
3023static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3024{
39de71ec 3025 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3026}
3027
1fe779f8
CO		 3028static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3029{
3030 int r;
3031
3032 r = 0;
3033 switch (chip->chip_id) {
3034 case KVM_IRQCHIP_PIC_MASTER:
3035 memcpy(&chip->chip.pic,
3036 &pic_irqchip(kvm)->pics[0],
3037 sizeof(struct kvm_pic_state));
3038 break;
3039 case KVM_IRQCHIP_PIC_SLAVE:
3040 memcpy(&chip->chip.pic,
3041 &pic_irqchip(kvm)->pics[1],
3042 sizeof(struct kvm_pic_state));
3043 break;
3044 case KVM_IRQCHIP_IOAPIC:
eba0226b 3045 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3046 break;
3047 default:
3048 r = -EINVAL;
3049 break;
3050 }
3051 return r;
3052}
3053
3054static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3055{
3056 int r;
3057
3058 r = 0;
3059 switch (chip->chip_id) {
3060 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3061 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3062 memcpy(&pic_irqchip(kvm)->pics[0],
3063 &chip->chip.pic,
3064 sizeof(struct kvm_pic_state));
f4f51050 3065 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3066 break;
3067 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3068 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3069 memcpy(&pic_irqchip(kvm)->pics[1],
3070 &chip->chip.pic,
3071 sizeof(struct kvm_pic_state));
f4f51050 3072 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3073 break;
3074 case KVM_IRQCHIP_IOAPIC:
eba0226b 3075 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3076 break;
3077 default:
3078 r = -EINVAL;
3079 break;
3080 }
3081 kvm_pic_update_irq(pic_irqchip(kvm));
3082 return r;
3083}
3084
e0f63cb9
SY		 3085static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3086{
3087 int r = 0;
3088
894a9c55 3089 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3090 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3091 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3092 return r;
3093}
3094
3095static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3096{
3097 int r = 0;
3098
894a9c55 3099 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3100 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3101 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3102 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3103 return r;
3104}
3105
3106static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3107{
3108 int r = 0;
3109
3110 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3111 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3112 sizeof(ps->channels));
3113 ps->flags = kvm->arch.vpit->pit_state.flags;
3114 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3115 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3116 return r;
3117}
3118
3119static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3120{
3121 int r = 0, start = 0;
3122 u32 prev_legacy, cur_legacy;
3123 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3124 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3125 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3126 if (!prev_legacy && cur_legacy)
3127 start = 1;
3128 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3129 sizeof(kvm->arch.vpit->pit_state.channels));
3130 kvm->arch.vpit->pit_state.flags = ps->flags;
3131 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3132 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3133 return r;
3134}
3135
52d939a0
MT		 3136static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3137 struct kvm_reinject_control *control)
3138{
3139 if (!kvm->arch.vpit)
3140 return -ENXIO;
894a9c55 3141 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3142 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3143 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3144 return 0;
3145}
3146
5bb064dc
ZX		 3147/*
3148 * Get (and clear) the dirty memory log for a memory slot.
3149 */
3150int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3151 struct kvm_dirty_log *log)
3152{
87bf6e7d 3153 int r, i;
5bb064dc 3154 struct kvm_memory_slot *memslot;
87bf6e7d 3155 unsigned long n;
b050b015 3156 unsigned long is_dirty = 0;
5bb064dc 3157
79fac95e 3158 mutex_lock(&kvm->slots_lock);
5bb064dc 3159
b050b015
MT		 3160 r = -EINVAL;
3161 if (log->slot >= KVM_MEMORY_SLOTS)
3162 goto out;
3163
3164 memslot = &kvm->memslots->memslots[log->slot];
3165 r = -ENOENT;
3166 if (!memslot->dirty_bitmap)
3167 goto out;
3168
87bf6e7d 3169 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3170
b050b015
MT		 3171 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3172 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3173
3174 /* If nothing is dirty, don't bother messing with page tables. */
3175 if (is_dirty) {
b050b015 3176 struct kvm_memslots *slots, *old_slots;
914ebccd 3177 unsigned long *dirty_bitmap;
b050b015 3178
914ebccd
TY		 3179 r = -ENOMEM;
3180 dirty_bitmap = vmalloc(n);
3181 if (!dirty_bitmap)
3182 goto out;
3183 memset(dirty_bitmap, 0, n);
b050b015 3184
914ebccd
TY		 3185 r = -ENOMEM;
3186 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
3187 if (!slots) {
3188 vfree(dirty_bitmap);
3189 goto out;
3190 }
b050b015
MT		 3191 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3192 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
49c7754c 3193 slots->generation++;
b050b015
MT		 3194
3195 old_slots = kvm->memslots;
3196 rcu_assign_pointer(kvm->memslots, slots);
3197 synchronize_srcu_expedited(&kvm->srcu);
3198 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3199 kfree(old_slots);
914ebccd 3200
edde99ce
MT		 3201 spin_lock(&kvm->mmu_lock);
3202 kvm_mmu_slot_remove_write_access(kvm, log->slot);
3203 spin_unlock(&kvm->mmu_lock);
3204
914ebccd
TY		 3205 r = -EFAULT;
3206 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) {
3207 vfree(dirty_bitmap);
3208 goto out;
3209 }
3210 vfree(dirty_bitmap);
3211 } else {
3212 r = -EFAULT;
3213 if (clear_user(log->dirty_bitmap, n))
3214 goto out;
5bb064dc 3215 }
b050b015 3216
5bb064dc
ZX		 3217 r = 0;
3218out:
79fac95e 3219 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3220 return r;
3221}
3222
1fe779f8
CO		 3223long kvm_arch_vm_ioctl(struct file *filp,
3224 unsigned int ioctl, unsigned long arg)
3225{
3226 struct kvm *kvm = filp->private_data;
3227 void __user *argp = (void __user *)arg;
367e1319 3228 int r = -ENOTTY;
f0d66275
DH		 3229 /*
3230 * This union makes it completely explicit to gcc-3.x
3231 * that these two variables' stack usage should be
3232 * combined, not added together.
3233 */
3234 union {
3235 struct kvm_pit_state ps;
e9f42757 3236 struct kvm_pit_state2 ps2;
c5ff41ce 3237 struct kvm_pit_config pit_config;
f0d66275 3238 } u;
1fe779f8
CO		 3239
3240 switch (ioctl) {
3241 case KVM_SET_TSS_ADDR:
3242 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3243 if (r < 0)
3244 goto out;
3245 break;
b927a3ce
SY		 3246 case KVM_SET_IDENTITY_MAP_ADDR: {
3247 u64 ident_addr;
3248
3249 r = -EFAULT;
3250 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3251 goto out;
3252 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3253 if (r < 0)
3254 goto out;
3255 break;
3256 }
1fe779f8
CO		 3257 case KVM_SET_NR_MMU_PAGES:
3258 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3259 if (r)
3260 goto out;
3261 break;
3262 case KVM_GET_NR_MMU_PAGES:
3263 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3264 break;
3ddea128
MT		 3265 case KVM_CREATE_IRQCHIP: {
3266 struct kvm_pic *vpic;
3267
3268 mutex_lock(&kvm->lock);
3269 r = -EEXIST;
3270 if (kvm->arch.vpic)
3271 goto create_irqchip_unlock;
1fe779f8 3272 r = -ENOMEM;
3ddea128
MT		 3273 vpic = kvm_create_pic(kvm);
3274 if (vpic) {
1fe779f8
CO		 3275 r = kvm_ioapic_init(kvm);
3276 if (r) {
72bb2fcd
WY		 3277 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3278 &vpic->dev);
3ddea128
MT		 3279 kfree(vpic);
3280 goto create_irqchip_unlock;
1fe779f8
CO		 3281 }
3282 } else
3ddea128
MT		 3283 goto create_irqchip_unlock;
3284 smp_wmb();
3285 kvm->arch.vpic = vpic;
3286 smp_wmb();
399ec807
AK		 3287 r = kvm_setup_default_irq_routing(kvm);
3288 if (r) {
3ddea128 3289 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3290 kvm_ioapic_destroy(kvm);
3291 kvm_destroy_pic(kvm);
3ddea128 3292 mutex_unlock(&kvm->irq_lock);
399ec807 3293 }
3ddea128
MT		 3294 create_irqchip_unlock:
3295 mutex_unlock(&kvm->lock);
1fe779f8 3296 break;
3ddea128 3297 }
7837699f 3298 case KVM_CREATE_PIT:
c5ff41ce
JK		 3299 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3300 goto create_pit;
3301 case KVM_CREATE_PIT2:
3302 r = -EFAULT;
3303 if (copy_from_user(&u.pit_config, argp,
3304 sizeof(struct kvm_pit_config)))
3305 goto out;
3306 create_pit:
79fac95e 3307 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3308 r = -EEXIST;
3309 if (kvm->arch.vpit)
3310 goto create_pit_unlock;
7837699f 3311 r = -ENOMEM;
c5ff41ce 3312 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3313 if (kvm->arch.vpit)
3314 r = 0;
269e05e4 3315 create_pit_unlock:
79fac95e 3316 mutex_unlock(&kvm->slots_lock);
7837699f 3317 break;
4925663a 3318 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3319 case KVM_IRQ_LINE: {
3320 struct kvm_irq_level irq_event;
3321
3322 r = -EFAULT;
3323 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3324 goto out;
160d2f6c 3325 r = -ENXIO;
1fe779f8 3326 if (irqchip_in_kernel(kvm)) {
4925663a 3327 __s32 status;
4925663a
GN		 3328 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3329 irq_event.irq, irq_event.level);
4925663a 3330 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3331 r = -EFAULT;
4925663a
GN		 3332 irq_event.status = status;
3333 if (copy_to_user(argp, &irq_event,
3334 sizeof irq_event))
3335 goto out;
3336 }
1fe779f8
CO		 3337 r = 0;
3338 }
3339 break;
3340 }
3341 case KVM_GET_IRQCHIP: {
3342 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3343 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3344
f0d66275
DH		 3345 r = -ENOMEM;
3346 if (!chip)
1fe779f8 3347 goto out;
f0d66275
DH		 3348 r = -EFAULT;
3349 if (copy_from_user(chip, argp, sizeof *chip))
3350 goto get_irqchip_out;
1fe779f8
CO		 3351 r = -ENXIO;
3352 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3353 goto get_irqchip_out;
3354 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3355 if (r)
f0d66275 3356 goto get_irqchip_out;
1fe779f8 3357 r = -EFAULT;
f0d66275
DH		 3358 if (copy_to_user(argp, chip, sizeof *chip))
3359 goto get_irqchip_out;
1fe779f8 3360 r = 0;
f0d66275
DH		 3361 get_irqchip_out:
3362 kfree(chip);
3363 if (r)
3364 goto out;
1fe779f8
CO		 3365 break;
3366 }
3367 case KVM_SET_IRQCHIP: {
3368 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3369 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3370
f0d66275
DH		 3371 r = -ENOMEM;
3372 if (!chip)
1fe779f8 3373 goto out;
f0d66275
DH		 3374 r = -EFAULT;
3375 if (copy_from_user(chip, argp, sizeof *chip))
3376 goto set_irqchip_out;
1fe779f8
CO		 3377 r = -ENXIO;
3378 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3379 goto set_irqchip_out;
3380 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3381 if (r)
f0d66275 3382 goto set_irqchip_out;
1fe779f8 3383 r = 0;
f0d66275
DH		 3384 set_irqchip_out:
3385 kfree(chip);
3386 if (r)
3387 goto out;
1fe779f8
CO		 3388 break;
3389 }
e0f63cb9 3390 case KVM_GET_PIT: {
e0f63cb9 3391 r = -EFAULT;
f0d66275 3392 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3393 goto out;
3394 r = -ENXIO;
3395 if (!kvm->arch.vpit)
3396 goto out;
f0d66275 3397 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3398 if (r)
3399 goto out;
3400 r = -EFAULT;
f0d66275 3401 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3402 goto out;
3403 r = 0;
3404 break;
3405 }
3406 case KVM_SET_PIT: {
e0f63cb9 3407 r = -EFAULT;
f0d66275 3408 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3409 goto out;
3410 r = -ENXIO;
3411 if (!kvm->arch.vpit)
3412 goto out;
f0d66275 3413 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3414 if (r)
3415 goto out;
3416 r = 0;
3417 break;
3418 }
e9f42757
BK		 3419 case KVM_GET_PIT2: {
3420 r = -ENXIO;
3421 if (!kvm->arch.vpit)
3422 goto out;
3423 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3424 if (r)
3425 goto out;
3426 r = -EFAULT;
3427 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3428 goto out;
3429 r = 0;
3430 break;
3431 }
3432 case KVM_SET_PIT2: {
3433 r = -EFAULT;
3434 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3435 goto out;
3436 r = -ENXIO;
3437 if (!kvm->arch.vpit)
3438 goto out;
3439 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3440 if (r)
3441 goto out;
3442 r = 0;
3443 break;
3444 }
52d939a0
MT		 3445 case KVM_REINJECT_CONTROL: {
3446 struct kvm_reinject_control control;
3447 r = -EFAULT;
3448 if (copy_from_user(&control, argp, sizeof(control)))
3449 goto out;
3450 r = kvm_vm_ioctl_reinject(kvm, &control);
3451 if (r)
3452 goto out;
3453 r = 0;
3454 break;
3455 }
ffde22ac
ES		 3456 case KVM_XEN_HVM_CONFIG: {
3457 r = -EFAULT;
3458 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3459 sizeof(struct kvm_xen_hvm_config)))
3460 goto out;
3461 r = -EINVAL;
3462 if (kvm->arch.xen_hvm_config.flags)
3463 goto out;
3464 r = 0;
3465 break;
3466 }
afbcf7ab 3467 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3468 struct kvm_clock_data user_ns;
3469 u64 now_ns;
3470 s64 delta;
3471
3472 r = -EFAULT;
3473 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3474 goto out;
3475
3476 r = -EINVAL;
3477 if (user_ns.flags)
3478 goto out;
3479
3480 r = 0;
395c6b0a 3481 local_irq_disable();
759379dd 3482 now_ns = get_kernel_ns();
afbcf7ab 3483 delta = user_ns.clock - now_ns;
395c6b0a 3484 local_irq_enable();
afbcf7ab
GC		 3485 kvm->arch.kvmclock_offset = delta;
3486 break;
3487 }
3488 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3489 struct kvm_clock_data user_ns;
3490 u64 now_ns;
3491
395c6b0a 3492 local_irq_disable();
759379dd 3493 now_ns = get_kernel_ns();
afbcf7ab 3494 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3495 local_irq_enable();
afbcf7ab 3496 user_ns.flags = 0;
97e69aa6 3497 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3498
3499 r = -EFAULT;
3500 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3501 goto out;
3502 r = 0;
3503 break;
3504 }
3505
1fe779f8
CO		 3506 default:
3507 ;
3508 }
3509out:
3510 return r;
3511}
3512
a16b043c 3513static void kvm_init_msr_list(void)
043405e1
CO		 3514{
3515 u32 dummy[2];
3516 unsigned i, j;
3517
e3267cbb
GC		 3518 /* skip the first msrs in the list. KVM-specific */
3519 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3520 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3521 continue;
3522 if (j < i)
3523 msrs_to_save[j] = msrs_to_save[i];
3524 j++;
3525 }
3526 num_msrs_to_save = j;
3527}
3528
bda9020e
MT		 3529static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3530 const void *v)
bbd9b64e 3531{
bda9020e
MT		 3532 if (vcpu->arch.apic &&
3533 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3534 return 0;
bbd9b64e 3535
e93f8a0f 3536 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3537}
3538
bda9020e 3539static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3540{
bda9020e
MT		 3541 if (vcpu->arch.apic &&
3542 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3543 return 0;
bbd9b64e 3544
e93f8a0f 3545 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3546}
3547
2dafc6c2
GN		 3548static void kvm_set_segment(struct kvm_vcpu *vcpu,
3549 struct kvm_segment *var, int seg)
3550{
3551 kvm_x86_ops->set_segment(vcpu, var, seg);
3552}
3553
3554void kvm_get_segment(struct kvm_vcpu *vcpu,
3555 struct kvm_segment *var, int seg)
3556{
3557 kvm_x86_ops->get_segment(vcpu, var, seg);
3558}
3559
c30a358d
JR		 3560static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3561{
3562 return gpa;
3563}
3564
02f59dc9
JR		 3565static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3566{
3567 gpa_t t_gpa;
3568 u32 error;
3569
3570 BUG_ON(!mmu_is_nested(vcpu));
3571
3572 /* NPT walks are always user-walks */
3573 access |= PFERR_USER_MASK;
3574 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &error);
3575 if (t_gpa == UNMAPPED_GVA)
0959ffac 3576 vcpu->arch.fault.nested = true;
02f59dc9
JR		 3577
3578 return t_gpa;
3579}
3580
1871c602
GN		 3581gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3582{
3583 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
14dfe855 3584 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3585}
3586
3587 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3588{
3589 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3590 access |= PFERR_FETCH_MASK;
14dfe855 3591 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3592}
3593
3594gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3595{
3596 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3597 access |= PFERR_WRITE_MASK;
14dfe855 3598 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3599}
3600
3601/* uses this to access any guest's mapped memory without checking CPL */
3602gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3603{
14dfe855 3604 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, error);
1871c602
GN		 3605}
3606
3607static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3608 struct kvm_vcpu *vcpu, u32 access,
3609 u32 *error)
bbd9b64e
CO		 3610{
3611 void *data = val;
10589a46 3612 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3613
3614 while (bytes) {
14dfe855
JR		 3615 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3616 error);
bbd9b64e 3617 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3618 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3619 int ret;
3620
10589a46
MT		 3621 if (gpa == UNMAPPED_GVA) {
3622 r = X86EMUL_PROPAGATE_FAULT;
3623 goto out;
3624 }
77c2002e 3625 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3626 if (ret < 0) {
c3cd7ffa 3627 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3628 goto out;
3629 }
bbd9b64e 3630
77c2002e
IE		 3631 bytes -= toread;
3632 data += toread;
3633 addr += toread;
bbd9b64e 3634 }
10589a46 3635out:
10589a46 3636 return r;
bbd9b64e 3637}
77c2002e 3638
1871c602
GN		 3639/* used for instruction fetching */
3640static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3641 struct kvm_vcpu *vcpu, u32 *error)
3642{
3643 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3644 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3645 access | PFERR_FETCH_MASK, error);
3646}
3647
3648static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3649 struct kvm_vcpu *vcpu, u32 *error)
3650{
3651 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3652 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3653 error);
3654}
3655
3656static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3657 struct kvm_vcpu *vcpu, u32 *error)
3658{
3659 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3660}
3661
7972995b 3662static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3663 unsigned int bytes,
7972995b 3664 struct kvm_vcpu *vcpu,
2dafc6c2 3665 u32 *error)
77c2002e
IE		 3666{
3667 void *data = val;
3668 int r = X86EMUL_CONTINUE;
3669
3670 while (bytes) {
14dfe855
JR		 3671 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3672 PFERR_WRITE_MASK,
3673 error);
77c2002e
IE		 3674 unsigned offset = addr & (PAGE_SIZE-1);
3675 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3676 int ret;
3677
3678 if (gpa == UNMAPPED_GVA) {
3679 r = X86EMUL_PROPAGATE_FAULT;
3680 goto out;
3681 }
3682 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3683 if (ret < 0) {
c3cd7ffa 3684 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3685 goto out;
3686 }
3687
3688 bytes -= towrite;
3689 data += towrite;
3690 addr += towrite;
3691 }
3692out:
3693 return r;
3694}
3695
bbd9b64e
CO		 3696static int emulator_read_emulated(unsigned long addr,
3697 void *val,
3698 unsigned int bytes,
8fe681e9 3699 unsigned int *error_code,
bbd9b64e
CO		 3700 struct kvm_vcpu *vcpu)
3701{
bbd9b64e
CO		 3702 gpa_t gpa;
3703
3704 if (vcpu->mmio_read_completed) {
3705 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3706 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3707 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3708 vcpu->mmio_read_completed = 0;
3709 return X86EMUL_CONTINUE;
3710 }
3711
8fe681e9 3712 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, error_code);
1871c602 3713
8fe681e9 3714 if (gpa == UNMAPPED_GVA)
1871c602 3715 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3716
3717 /* For APIC access vmexit */
3718 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3719 goto mmio;
3720
1871c602 3721 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3722 == X86EMUL_CONTINUE)
bbd9b64e 3723 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3724
3725mmio:
3726 /*
3727 * Is this MMIO handled locally?
3728 */
aec51dc4
AK		 3729 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3730 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3731 return X86EMUL_CONTINUE;
3732 }
aec51dc4
AK		 3733
3734 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3735
3736 vcpu->mmio_needed = 1;
411c35b7
GN		 3737 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3738 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3739 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3740 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
bbd9b64e 3741
c3cd7ffa 3742 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3743}
3744
3200f405 3745int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3746 const void *val, int bytes)
bbd9b64e
CO		 3747{
3748 int ret;
3749
3750 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3751 if (ret < 0)
bbd9b64e 3752 return 0;
ad218f85 3753 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3754 return 1;
3755}
3756
3757static int emulator_write_emulated_onepage(unsigned long addr,
3758 const void *val,
3759 unsigned int bytes,
8fe681e9 3760 unsigned int *error_code,
bbd9b64e
CO		 3761 struct kvm_vcpu *vcpu)
3762{
10589a46
MT		 3763 gpa_t gpa;
3764
8fe681e9 3765 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error_code);
bbd9b64e 3766
8fe681e9 3767 if (gpa == UNMAPPED_GVA)
bbd9b64e 3768 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3769
3770 /* For APIC access vmexit */
3771 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3772 goto mmio;
3773
3774 if (emulator_write_phys(vcpu, gpa, val, bytes))
3775 return X86EMUL_CONTINUE;
3776
3777mmio:
aec51dc4 3778 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3779 /*
3780 * Is this MMIO handled locally?
3781 */
bda9020e 3782 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3783 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3784
3785 vcpu->mmio_needed = 1;
411c35b7
GN		 3786 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3787 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3788 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3789 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
3790 memcpy(vcpu->run->mmio.data, val, bytes);
bbd9b64e
CO		 3791
3792 return X86EMUL_CONTINUE;
3793}
3794
3795int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3796 const void *val,
3797 unsigned int bytes,
8fe681e9 3798 unsigned int *error_code,
8f6abd06 3799 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3800{
3801 /* Crossing a page boundary? */
3802 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3803 int rc, now;
3804
3805 now = -addr & ~PAGE_MASK;
8fe681e9
GN		 3806 rc = emulator_write_emulated_onepage(addr, val, now, error_code,
3807 vcpu);
bbd9b64e
CO		 3808 if (rc != X86EMUL_CONTINUE)
3809 return rc;
3810 addr += now;
3811 val += now;
3812 bytes -= now;
3813 }
8fe681e9
GN		 3814 return emulator_write_emulated_onepage(addr, val, bytes, error_code,
3815 vcpu);
bbd9b64e 3816}
bbd9b64e 3817
daea3e73
AK		 3818#define CMPXCHG_TYPE(t, ptr, old, new) \
3819 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3820
3821#ifdef CONFIG_X86_64
3822# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3823#else
3824# define CMPXCHG64(ptr, old, new) \
9749a6c0 3825 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3826#endif
3827
bbd9b64e
CO		 3828static int emulator_cmpxchg_emulated(unsigned long addr,
3829 const void *old,
3830 const void *new,
3831 unsigned int bytes,
8fe681e9 3832 unsigned int *error_code,
bbd9b64e
CO		 3833 struct kvm_vcpu *vcpu)
3834{
daea3e73
AK		 3835 gpa_t gpa;
3836 struct page *page;
3837 char *kaddr;
3838 bool exchanged;
2bacc55c 3839
daea3e73
AK		 3840 /* guests cmpxchg8b have to be emulated atomically */
3841 if (bytes > 8 || (bytes & (bytes - 1)))
3842 goto emul_write;
10589a46 3843
daea3e73 3844 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3845
daea3e73
AK		 3846 if (gpa == UNMAPPED_GVA ||
3847 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3848 goto emul_write;
2bacc55c 3849
daea3e73
AK		 3850 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3851 goto emul_write;
72dc67a6 3852
daea3e73 3853 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3854 if (is_error_page(page)) {
3855 kvm_release_page_clean(page);
3856 goto emul_write;
3857 }
72dc67a6 3858
daea3e73
AK		 3859 kaddr = kmap_atomic(page, KM_USER0);
3860 kaddr += offset_in_page(gpa);
3861 switch (bytes) {
3862 case 1:
3863 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3864 break;
3865 case 2:
3866 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3867 break;
3868 case 4:
3869 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3870 break;
3871 case 8:
3872 exchanged = CMPXCHG64(kaddr, old, new);
3873 break;
3874 default:
3875 BUG();
2bacc55c 3876 }
daea3e73
AK		 3877 kunmap_atomic(kaddr, KM_USER0);
3878 kvm_release_page_dirty(page);
3879
3880 if (!exchanged)
3881 return X86EMUL_CMPXCHG_FAILED;
3882
8f6abd06
GN		 3883 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3884
3885 return X86EMUL_CONTINUE;
4a5f48f6 3886
3200f405 3887emul_write:
daea3e73 3888 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3889
8fe681e9 3890 return emulator_write_emulated(addr, new, bytes, error_code, vcpu);
bbd9b64e
CO		 3891}
3892
cf8f70bf
GN		 3893static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3894{
3895 /* TODO: String I/O for in kernel device */
3896 int r;
3897
3898 if (vcpu->arch.pio.in)
3899 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3900 vcpu->arch.pio.size, pd);
3901 else
3902 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3903 vcpu->arch.pio.port, vcpu->arch.pio.size,
3904 pd);
3905 return r;
3906}
3907
3908
3909static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3910 unsigned int count, struct kvm_vcpu *vcpu)
3911{
7972995b 3912 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3913 goto data_avail;
3914
c41a15dd 3915 trace_kvm_pio(0, port, size, 1);
cf8f70bf
GN		 3916
3917 vcpu->arch.pio.port = port;
3918 vcpu->arch.pio.in = 1;
7972995b 3919 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3920 vcpu->arch.pio.size = size;
3921
3922 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3923 data_avail:
3924 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3925 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3926 return 1;
3927 }
3928
3929 vcpu->run->exit_reason = KVM_EXIT_IO;
3930 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3931 vcpu->run->io.size = size;
3932 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3933 vcpu->run->io.count = count;
3934 vcpu->run->io.port = port;
3935
3936 return 0;
3937}
3938
3939static int emulator_pio_out_emulated(int size, unsigned short port,
3940 const void *val, unsigned int count,
3941 struct kvm_vcpu *vcpu)
3942{
c41a15dd 3943 trace_kvm_pio(1, port, size, 1);
cf8f70bf
GN		 3944
3945 vcpu->arch.pio.port = port;
3946 vcpu->arch.pio.in = 0;
7972995b 3947 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3948 vcpu->arch.pio.size = size;
3949
3950 memcpy(vcpu->arch.pio_data, val, size * count);
3951
3952 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3953 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3954 return 1;
3955 }
3956
3957 vcpu->run->exit_reason = KVM_EXIT_IO;
3958 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3959 vcpu->run->io.size = size;
3960 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3961 vcpu->run->io.count = count;
3962 vcpu->run->io.port = port;
3963
3964 return 0;
3965}
3966
bbd9b64e
CO		 3967static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3968{
3969 return kvm_x86_ops->get_segment_base(vcpu, seg);
3970}
3971
3972int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3973{
a7052897 3974 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3975 return X86EMUL_CONTINUE;
3976}
3977
f5f48ee1
SY		 3978int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
3979{
3980 if (!need_emulate_wbinvd(vcpu))
3981 return X86EMUL_CONTINUE;
3982
3983 if (kvm_x86_ops->has_wbinvd_exit()) {
453d9c57 3984 preempt_disable();
f5f48ee1
SY		 3985 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
3986 wbinvd_ipi, NULL, 1);
453d9c57 3987 preempt_enable();
f5f48ee1
SY		 3988 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
3989 }
3990 wbinvd();
3991 return X86EMUL_CONTINUE;
3992}
3993EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
3994
bbd9b64e
CO		 3995int emulate_clts(struct kvm_vcpu *vcpu)
3996{
4d4ec087 3997 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3998 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3999 return X86EMUL_CONTINUE;
4000}
4001
35aa5375 4002int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
bbd9b64e 4003{
338dbc97 4004 return _kvm_get_dr(vcpu, dr, dest);
bbd9b64e
CO		 4005}
4006
35aa5375 4007int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
bbd9b64e 4008{
338dbc97
GN		 4009
4010 return __kvm_set_dr(vcpu, dr, value);
bbd9b64e
CO		 4011}
4012
52a46617 4013static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4014{
52a46617 4015 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4016}
4017
52a46617 4018static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 4019{
52a46617
GN		 4020 unsigned long value;
4021
4022 switch (cr) {
4023 case 0:
4024 value = kvm_read_cr0(vcpu);
4025 break;
4026 case 2:
4027 value = vcpu->arch.cr2;
4028 break;
4029 case 3:
4030 value = vcpu->arch.cr3;
4031 break;
4032 case 4:
4033 value = kvm_read_cr4(vcpu);
4034 break;
4035 case 8:
4036 value = kvm_get_cr8(vcpu);
4037 break;
4038 default:
4039 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4040 return 0;
4041 }
4042
4043 return value;
4044}
4045
0f12244f 4046static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
52a46617 4047{
0f12244f
GN		 4048 int res = 0;
4049
52a46617
GN		 4050 switch (cr) {
4051 case 0:
49a9b07e 4052 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4053 break;
4054 case 2:
4055 vcpu->arch.cr2 = val;
4056 break;
4057 case 3:
2390218b 4058 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4059 break;
4060 case 4:
a83b29c6 4061 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4062 break;
4063 case 8:
0f12244f 4064 res = __kvm_set_cr8(vcpu, val & 0xfUL);
52a46617
GN		 4065 break;
4066 default:
4067 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4068 res = -1;
52a46617 4069 }
0f12244f
GN		 4070
4071 return res;
52a46617
GN		 4072}
4073
9c537244
GN		 4074static int emulator_get_cpl(struct kvm_vcpu *vcpu)
4075{
4076 return kvm_x86_ops->get_cpl(vcpu);
4077}
4078
2dafc6c2
GN		 4079static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4080{
4081 kvm_x86_ops->get_gdt(vcpu, dt);
4082}
4083
160ce1f1
MG		 4084static void emulator_get_idt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4085{
4086 kvm_x86_ops->get_idt(vcpu, dt);
4087}
4088
5951c442
GN		 4089static unsigned long emulator_get_cached_segment_base(int seg,
4090 struct kvm_vcpu *vcpu)
4091{
4092 return get_segment_base(vcpu, seg);
4093}
4094
2dafc6c2
GN		 4095static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
4096 struct kvm_vcpu *vcpu)
4097{
4098 struct kvm_segment var;
4099
4100 kvm_get_segment(vcpu, &var, seg);
4101
4102 if (var.unusable)
4103 return false;
4104
4105 if (var.g)
4106 var.limit >>= 12;
4107 set_desc_limit(desc, var.limit);
4108 set_desc_base(desc, (unsigned long)var.base);
4109 desc->type = var.type;
4110 desc->s = var.s;
4111 desc->dpl = var.dpl;
4112 desc->p = var.present;
4113 desc->avl = var.avl;
4114 desc->l = var.l;
4115 desc->d = var.db;
4116 desc->g = var.g;
4117
4118 return true;
4119}
4120
4121static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
4122 struct kvm_vcpu *vcpu)
4123{
4124 struct kvm_segment var;
4125
4126 /* needed to preserve selector */
4127 kvm_get_segment(vcpu, &var, seg);
4128
4129 var.base = get_desc_base(desc);
4130 var.limit = get_desc_limit(desc);
4131 if (desc->g)
4132 var.limit = (var.limit << 12) | 0xfff;
4133 var.type = desc->type;
4134 var.present = desc->p;
4135 var.dpl = desc->dpl;
4136 var.db = desc->d;
4137 var.s = desc->s;
4138 var.l = desc->l;
4139 var.g = desc->g;
4140 var.avl = desc->avl;
4141 var.present = desc->p;
4142 var.unusable = !var.present;
4143 var.padding = 0;
4144
4145 kvm_set_segment(vcpu, &var, seg);
4146 return;
4147}
4148
4149static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
4150{
4151 struct kvm_segment kvm_seg;
4152
4153 kvm_get_segment(vcpu, &kvm_seg, seg);
4154 return kvm_seg.selector;
4155}
4156
4157static void emulator_set_segment_selector(u16 sel, int seg,
4158 struct kvm_vcpu *vcpu)
4159{
4160 struct kvm_segment kvm_seg;
4161
4162 kvm_get_segment(vcpu, &kvm_seg, seg);
4163 kvm_seg.selector = sel;
4164 kvm_set_segment(vcpu, &kvm_seg, seg);
4165}
4166
14af3f3c 4167static struct x86_emulate_ops emulate_ops = {
1871c602 4168 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4169 .write_std = kvm_write_guest_virt_system,
1871c602 4170 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4171 .read_emulated = emulator_read_emulated,
4172 .write_emulated = emulator_write_emulated,
4173 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 4174 .pio_in_emulated = emulator_pio_in_emulated,
4175 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 4176 .get_cached_descriptor = emulator_get_cached_descriptor,
4177 .set_cached_descriptor = emulator_set_cached_descriptor,
4178 .get_segment_selector = emulator_get_segment_selector,
4179 .set_segment_selector = emulator_set_segment_selector,
5951c442 4180 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4181 .get_gdt = emulator_get_gdt,
160ce1f1 4182 .get_idt = emulator_get_idt,
52a46617
GN		 4183 .get_cr = emulator_get_cr,
4184 .set_cr = emulator_set_cr,
9c537244 4185 .cpl = emulator_get_cpl,
35aa5375
GN		 4186 .get_dr = emulator_get_dr,
4187 .set_dr = emulator_set_dr,
3fb1b5db
GN		 4188 .set_msr = kvm_set_msr,
4189 .get_msr = kvm_get_msr,
bbd9b64e
CO		 4190};
4191
5fdbf976
MT		 4192static void cache_all_regs(struct kvm_vcpu *vcpu)
4193{
4194 kvm_register_read(vcpu, VCPU_REGS_RAX);
4195 kvm_register_read(vcpu, VCPU_REGS_RSP);
4196 kvm_register_read(vcpu, VCPU_REGS_RIP);
4197 vcpu->arch.regs_dirty = ~0;
4198}
4199
95cb2295
GN		 4200static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4201{
4202 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4203 /*
4204 * an sti; sti; sequence only disable interrupts for the first
4205 * instruction. So, if the last instruction, be it emulated or
4206 * not, left the system with the INT_STI flag enabled, it
4207 * means that the last instruction is an sti. We should not
4208 * leave the flag on in this case. The same goes for mov ss
4209 */
4210 if (!(int_shadow & mask))
4211 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4212}
4213
54b8486f
GN		 4214static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4215{
4216 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4217 if (ctxt->exception == PF_VECTOR)
d4f8cf66 4218 kvm_propagate_fault(vcpu);
54b8486f
GN		 4219 else if (ctxt->error_code_valid)
4220 kvm_queue_exception_e(vcpu, ctxt->exception, ctxt->error_code);
4221 else
4222 kvm_queue_exception(vcpu, ctxt->exception);
4223}
4224
8ec4722d
MG		 4225static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4226{
4227 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4228 int cs_db, cs_l;
4229
4230 cache_all_regs(vcpu);
4231
4232 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4233
4234 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4235 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4236 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4237 vcpu->arch.emulate_ctxt.mode =
4238 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4239 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4240 ? X86EMUL_MODE_VM86 : cs_l
4241 ? X86EMUL_MODE_PROT64 : cs_db
4242 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4243 memset(c, 0, sizeof(struct decode_cache));
4244 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4245}
4246
63995653
MG		 4247int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq)
4248{
4249 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4250 int ret;
4251
4252 init_emulate_ctxt(vcpu);
4253
4254 vcpu->arch.emulate_ctxt.decode.op_bytes = 2;
4255 vcpu->arch.emulate_ctxt.decode.ad_bytes = 2;
4256 vcpu->arch.emulate_ctxt.decode.eip = vcpu->arch.emulate_ctxt.eip;
4257 ret = emulate_int_real(&vcpu->arch.emulate_ctxt, &emulate_ops, irq);
4258
4259 if (ret != X86EMUL_CONTINUE)
4260 return EMULATE_FAIL;
4261
4262 vcpu->arch.emulate_ctxt.eip = c->eip;
4263 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4264 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4265 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4266
4267 if (irq == NMI_VECTOR)
4268 vcpu->arch.nmi_pending = false;
4269 else
4270 vcpu->arch.interrupt.pending = false;
4271
4272 return EMULATE_DONE;
4273}
4274EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4275
6d77dbfc
GN		 4276static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4277{
6d77dbfc
GN		 4278 ++vcpu->stat.insn_emulation_fail;
4279 trace_kvm_emulate_insn_failed(vcpu);
4280 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4281 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4282 vcpu->run->internal.ndata = 0;
4283 kvm_queue_exception(vcpu, UD_VECTOR);
4284 return EMULATE_FAIL;
4285}
4286
a6f177ef
GN		 4287static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4288{
4289 gpa_t gpa;
4290
68be0803
GN		 4291 if (tdp_enabled)
4292 return false;
4293
a6f177ef
GN		 4294 /*
4295 * if emulation was due to access to shadowed page table
4296 * and it failed try to unshadow page and re-entetr the
4297 * guest to let CPU execute the instruction.
4298 */
4299 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4300 return true;
4301
4302 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4303
4304 if (gpa == UNMAPPED_GVA)
4305 return true; /* let cpu generate fault */
4306
4307 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4308 return true;
4309
4310 return false;
4311}
4312
bbd9b64e 4313int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 4314 unsigned long cr2,
4315 u16 error_code,
571008da 4316 int emulation_type)
bbd9b64e 4317{
95cb2295 4318 int r;
4d2179e1 4319 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
bbd9b64e 4320
26eef70c 4321 kvm_clear_exception_queue(vcpu);
ad312c7c 4322 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 4323 /*
56e82318 4324 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 4325 * instead of direct ->regs accesses, can save hundred cycles
4326 * on Intel for instructions that don't read/change RSP, for
4327 * for example.
4328 */
4329 cache_all_regs(vcpu);
bbd9b64e 4330
571008da 4331 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4332 init_emulate_ctxt(vcpu);
95cb2295 4333 vcpu->arch.emulate_ctxt.interruptibility = 0;
54b8486f 4334 vcpu->arch.emulate_ctxt.exception = -1;
4fc40f07 4335 vcpu->arch.emulate_ctxt.perm_ok = false;
bbd9b64e 4336
9aabc88f 4337 r = x86_decode_insn(&vcpu->arch.emulate_ctxt);
d47f00a6
JR		 4338 if (r == X86EMUL_PROPAGATE_FAULT)
4339 goto done;
bbd9b64e 4340
e46479f8 4341 trace_kvm_emulate_insn_start(vcpu);
571008da 4342
0cb5762e
AP		 4343 /* Only allow emulation of specific instructions on #UD
4344 * (namely VMMCALL, sysenter, sysexit, syscall)*/
0cb5762e
AP		 4345 if (emulation_type & EMULTYPE_TRAP_UD) {
4346 if (!c->twobyte)
4347 return EMULATE_FAIL;
4348 switch (c->b) {
4349 case 0x01: /* VMMCALL */
4350 if (c->modrm_mod != 3 || c->modrm_rm != 1)
4351 return EMULATE_FAIL;
4352 break;
4353 case 0x34: /* sysenter */
4354 case 0x35: /* sysexit */
4355 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4356 return EMULATE_FAIL;
4357 break;
4358 case 0x05: /* syscall */
4359 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4360 return EMULATE_FAIL;
4361 break;
4362 default:
4363 return EMULATE_FAIL;
4364 }
4365
4366 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
4367 return EMULATE_FAIL;
4368 }
571008da 4369
f2b5756b 4370 ++vcpu->stat.insn_emulation;
bbd9b64e 4371 if (r) {
a6f177ef 4372 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4373 return EMULATE_DONE;
6d77dbfc
GN		 4374 if (emulation_type & EMULTYPE_SKIP)
4375 return EMULATE_FAIL;
4376 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4377 }
4378 }
4379
ba8afb6b
GN		 4380 if (emulation_type & EMULTYPE_SKIP) {
4381 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4382 return EMULATE_DONE;
4383 }
4384
4d2179e1
GN		 4385 /* this is needed for vmware backdor interface to work since it
4386 changes registers values during IO operation */
4387 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4388
5cd21917 4389restart:
9aabc88f 4390 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt);
bbd9b64e 4391
d2ddd1c4 4392 if (r == EMULATION_FAILED) {
a6f177ef 4393 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4394 return EMULATE_DONE;
4395
6d77dbfc 4396 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4397 }
4398
d47f00a6 4399done:
54b8486f
GN		 4400 if (vcpu->arch.emulate_ctxt.exception >= 0) {
4401 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4402 r = EMULATE_DONE;
4403 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4404 if (!vcpu->arch.pio.in)
4405 vcpu->arch.pio.count = 0;
e85d28f8
GN		 4406 r = EMULATE_DO_MMIO;
4407 } else if (vcpu->mmio_needed) {
3457e419
GN		 4408 if (vcpu->mmio_is_write)
4409 vcpu->mmio_needed = 0;
e85d28f8 4410 r = EMULATE_DO_MMIO;
d2ddd1c4 4411 } else if (r == EMULATION_RESTART)
5cd21917 4412 goto restart;
d2ddd1c4
GN		 4413 else
4414 r = EMULATE_DONE;
f850e2e6 4415
e85d28f8
GN		 4416 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
4417 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 4418 kvm_make_request(KVM_REQ_EVENT, vcpu);
e85d28f8
GN		 4419 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4420 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4421
4422 return r;
de7d789a 4423}
bbd9b64e 4424EXPORT_SYMBOL_GPL(emulate_instruction);
de7d789a 4425
cf8f70bf 4426int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4427{
cf8f70bf
GN		 4428 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4429 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
4430 /* do not return to emulator after return from userspace */
7972995b 4431 vcpu->arch.pio.count = 0;
de7d789a
CO		 4432 return ret;
4433}
cf8f70bf 4434EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4435
8cfdc000
ZA		 4436static void tsc_bad(void *info)
4437{
4438 __get_cpu_var(cpu_tsc_khz) = 0;
4439}
4440
4441static void tsc_khz_changed(void *data)
c8076604 4442{
8cfdc000
ZA		 4443 struct cpufreq_freqs *freq = data;
4444 unsigned long khz = 0;
4445
4446 if (data)
4447 khz = freq->new;
4448 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4449 khz = cpufreq_quick_get(raw_smp_processor_id());
4450 if (!khz)
4451 khz = tsc_khz;
4452 __get_cpu_var(cpu_tsc_khz) = khz;
c8076604
GH		 4453}
4454
c8076604
GH		 4455static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4456 void *data)
4457{
4458 struct cpufreq_freqs *freq = data;
4459 struct kvm *kvm;
4460 struct kvm_vcpu *vcpu;
4461 int i, send_ipi = 0;
4462
8cfdc000
ZA		 4463 /*
4464 * We allow guests to temporarily run on slowing clocks,
4465 * provided we notify them after, or to run on accelerating
4466 * clocks, provided we notify them before. Thus time never
4467 * goes backwards.
4468 *
4469 * However, we have a problem. We can't atomically update
4470 * the frequency of a given CPU from this function; it is
4471 * merely a notifier, which can be called from any CPU.
4472 * Changing the TSC frequency at arbitrary points in time
4473 * requires a recomputation of local variables related to
4474 * the TSC for each VCPU. We must flag these local variables
4475 * to be updated and be sure the update takes place with the
4476 * new frequency before any guests proceed.
4477 *
4478 * Unfortunately, the combination of hotplug CPU and frequency
4479 * change creates an intractable locking scenario; the order
4480 * of when these callouts happen is undefined with respect to
4481 * CPU hotplug, and they can race with each other. As such,
4482 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4483 * undefined; you can actually have a CPU frequency change take
4484 * place in between the computation of X and the setting of the
4485 * variable. To protect against this problem, all updates of
4486 * the per_cpu tsc_khz variable are done in an interrupt
4487 * protected IPI, and all callers wishing to update the value
4488 * must wait for a synchronous IPI to complete (which is trivial
4489 * if the caller is on the CPU already). This establishes the
4490 * necessary total order on variable updates.
4491 *
4492 * Note that because a guest time update may take place
4493 * anytime after the setting of the VCPU's request bit, the
4494 * correct TSC value must be set before the request. However,
4495 * to ensure the update actually makes it to any guest which
4496 * starts running in hardware virtualization between the set
4497 * and the acquisition of the spinlock, we must also ping the
4498 * CPU after setting the request bit.
4499 *
4500 */
4501
c8076604
GH		 4502 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4503 return 0;
4504 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4505 return 0;
8cfdc000
ZA		 4506
4507 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4508
4509 spin_lock(&kvm_lock);
4510 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4511 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4512 if (vcpu->cpu != freq->cpu)
4513 continue;
c285545f 4514 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4515 if (vcpu->cpu != smp_processor_id())
8cfdc000 4516 send_ipi = 1;
c8076604
GH		 4517 }
4518 }
4519 spin_unlock(&kvm_lock);
4520
4521 if (freq->old < freq->new && send_ipi) {
4522 /*
4523 * We upscale the frequency. Must make the guest
4524 * doesn't see old kvmclock values while running with
4525 * the new frequency, otherwise we risk the guest sees
4526 * time go backwards.
4527 *
4528 * In case we update the frequency for another cpu
4529 * (which might be in guest context) send an interrupt
4530 * to kick the cpu out of guest context. Next time
4531 * guest context is entered kvmclock will be updated,
4532 * so the guest will not see stale values.
4533 */
8cfdc000 4534 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4535 }
4536 return 0;
4537}
4538
4539static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4540 .notifier_call = kvmclock_cpufreq_notifier
4541};
4542
4543static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4544 unsigned long action, void *hcpu)
4545{
4546 unsigned int cpu = (unsigned long)hcpu;
4547
4548 switch (action) {
4549 case CPU_ONLINE:
4550 case CPU_DOWN_FAILED:
4551 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4552 break;
4553 case CPU_DOWN_PREPARE:
4554 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4555 break;
4556 }
4557 return NOTIFY_OK;
4558}
4559
4560static struct notifier_block kvmclock_cpu_notifier_block = {
4561 .notifier_call = kvmclock_cpu_notifier,
4562 .priority = -INT_MAX
c8076604
GH		 4563};
4564
b820cc0c
ZA		 4565static void kvm_timer_init(void)
4566{
4567 int cpu;
4568
c285545f 4569 max_tsc_khz = tsc_khz;
8cfdc000 4570 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4571 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4572#ifdef CONFIG_CPU_FREQ
4573 struct cpufreq_policy policy;
4574 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 4575 cpu = get_cpu();
4576 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 4577 if (policy.cpuinfo.max_freq)
4578 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 4579 put_cpu();
c285545f 4580#endif
b820cc0c
ZA		 4581 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4582 CPUFREQ_TRANSITION_NOTIFIER);
4583 }
c285545f 4584 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4585 for_each_online_cpu(cpu)
4586 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4587}
4588
ff9d07a0
ZY		 4589static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4590
4591static int kvm_is_in_guest(void)
4592{
4593 return percpu_read(current_vcpu) != NULL;
4594}
4595
4596static int kvm_is_user_mode(void)
4597{
4598 int user_mode = 3;
dcf46b94 4599
ff9d07a0
ZY		 4600 if (percpu_read(current_vcpu))
4601 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4602
ff9d07a0
ZY		 4603 return user_mode != 0;
4604}
4605
4606static unsigned long kvm_get_guest_ip(void)
4607{
4608 unsigned long ip = 0;
dcf46b94 4609
ff9d07a0
ZY		 4610 if (percpu_read(current_vcpu))
4611 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4612
ff9d07a0
ZY		 4613 return ip;
4614}
4615
4616static struct perf_guest_info_callbacks kvm_guest_cbs = {
4617 .is_in_guest = kvm_is_in_guest,
4618 .is_user_mode = kvm_is_user_mode,
4619 .get_guest_ip = kvm_get_guest_ip,
4620};
4621
4622void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4623{
4624 percpu_write(current_vcpu, vcpu);
4625}
4626EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4627
4628void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4629{
4630 percpu_write(current_vcpu, NULL);
4631}
4632EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4633
f8c16bba 4634int kvm_arch_init(void *opaque)
043405e1 4635{
b820cc0c 4636 int r;
f8c16bba
ZX		 4637 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4638
f8c16bba
ZX		 4639 if (kvm_x86_ops) {
4640 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4641 r = -EEXIST;
4642 goto out;
f8c16bba
ZX		 4643 }
4644
4645 if (!ops->cpu_has_kvm_support()) {
4646 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4647 r = -EOPNOTSUPP;
4648 goto out;
f8c16bba
ZX		 4649 }
4650 if (ops->disabled_by_bios()) {
4651 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4652 r = -EOPNOTSUPP;
4653 goto out;
f8c16bba
ZX		 4654 }
4655
97db56ce
AK		 4656 r = kvm_mmu_module_init();
4657 if (r)
4658 goto out;
4659
4660 kvm_init_msr_list();
4661
f8c16bba 4662 kvm_x86_ops = ops;
56c6d28a 4663 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 4664 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
4665 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4666 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4667
b820cc0c 4668 kvm_timer_init();
c8076604 4669
ff9d07a0
ZY		 4670 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4671
2acf923e
DC		 4672 if (cpu_has_xsave)
4673 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4674
f8c16bba 4675 return 0;
56c6d28a
ZX		 4676
4677out:
56c6d28a 4678 return r;
043405e1 4679}
8776e519 4680
f8c16bba
ZX		 4681void kvm_arch_exit(void)
4682{
ff9d07a0
ZY		 4683 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4684
888d256e
JK		 4685 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4686 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4687 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4688 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4689 kvm_x86_ops = NULL;
56c6d28a
ZX		 4690 kvm_mmu_module_exit();
4691}
f8c16bba 4692
8776e519
HB		 4693int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4694{
4695 ++vcpu->stat.halt_exits;
4696 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4697 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4698 return 1;
4699 } else {
4700 vcpu->run->exit_reason = KVM_EXIT_HLT;
4701 return 0;
4702 }
4703}
4704EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4705
2f333bcb
MT		 4706static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4707 unsigned long a1)
4708{
4709 if (is_long_mode(vcpu))
4710 return a0;
4711 else
4712 return a0 | ((gpa_t)a1 << 32);
4713}
4714
55cd8e5a
GN		 4715int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4716{
4717 u64 param, ingpa, outgpa, ret;
4718 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4719 bool fast, longmode;
4720 int cs_db, cs_l;
4721
4722 /*
4723 * hypercall generates UD from non zero cpl and real mode
4724 * per HYPER-V spec
4725 */
3eeb3288 4726 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4727 kvm_queue_exception(vcpu, UD_VECTOR);
4728 return 0;
4729 }
4730
4731 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4732 longmode = is_long_mode(vcpu) && cs_l == 1;
4733
4734 if (!longmode) {
ccd46936
GN		 4735 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4736 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4737 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4738 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4739 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4740 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4741 }
4742#ifdef CONFIG_X86_64
4743 else {
4744 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4745 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4746 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4747 }
4748#endif
4749
4750 code = param & 0xffff;
4751 fast = (param >> 16) & 0x1;
4752 rep_cnt = (param >> 32) & 0xfff;
4753 rep_idx = (param >> 48) & 0xfff;
4754
4755 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4756
c25bc163
GN		 4757 switch (code) {
4758 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4759 kvm_vcpu_on_spin(vcpu);
4760 break;
4761 default:
4762 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4763 break;
4764 }
55cd8e5a
GN		 4765
4766 ret = res | (((u64)rep_done & 0xfff) << 32);
4767 if (longmode) {
4768 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4769 } else {
4770 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4771 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4772 }
4773
4774 return 1;
4775}
4776
8776e519
HB		 4777int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4778{
4779 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4780 int r = 1;
8776e519 4781
55cd8e5a
GN		 4782 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4783 return kvm_hv_hypercall(vcpu);
4784
5fdbf976
MT		 4785 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4786 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4787 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4788 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4789 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4790
229456fc 4791 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4792
8776e519
HB		 4793 if (!is_long_mode(vcpu)) {
4794 nr &= 0xFFFFFFFF;
4795 a0 &= 0xFFFFFFFF;
4796 a1 &= 0xFFFFFFFF;
4797 a2 &= 0xFFFFFFFF;
4798 a3 &= 0xFFFFFFFF;
4799 }
4800
07708c4a
JK		 4801 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4802 ret = -KVM_EPERM;
4803 goto out;
4804 }
4805
8776e519 4806 switch (nr) {
b93463aa
AK		 4807 case KVM_HC_VAPIC_POLL_IRQ:
4808 ret = 0;
4809 break;
2f333bcb
MT		 4810 case KVM_HC_MMU_OP:
4811 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4812 break;
8776e519
HB		 4813 default:
4814 ret = -KVM_ENOSYS;
4815 break;
4816 }
07708c4a 4817out:
5fdbf976 4818 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4819 ++vcpu->stat.hypercalls;
2f333bcb 4820 return r;
8776e519
HB		 4821}
4822EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4823
4824int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4825{
4826 char instruction[3];
5fdbf976 4827 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4828
8776e519
HB		 4829 /*
4830 * Blow out the MMU to ensure that no other VCPU has an active mapping
4831 * to ensure that the updated hypercall appears atomically across all
4832 * VCPUs.
4833 */
4834 kvm_mmu_zap_all(vcpu->kvm);
4835
8776e519 4836 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4837
8fe681e9 4838 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
8776e519
HB		 4839}
4840
8776e519
HB		 4841void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4842{
89a27f4d 4843 struct desc_ptr dt = { limit, base };
8776e519
HB		 4844
4845 kvm_x86_ops->set_gdt(vcpu, &dt);
4846}
4847
4848void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4849{
89a27f4d 4850 struct desc_ptr dt = { limit, base };
8776e519
HB		 4851
4852 kvm_x86_ops->set_idt(vcpu, &dt);
4853}
4854
07716717
DK		 4855static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4856{
ad312c7c
ZX		 4857 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4858 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4859
4860 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4861 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4862 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4863 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4864 if (ej->function == e->function) {
4865 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4866 return j;
4867 }
4868 }
4869 return 0; /* silence gcc, even though control never reaches here */
4870}
4871
4872/* find an entry with matching function, matching index (if needed), and that
4873 * should be read next (if it's stateful) */
4874static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4875 u32 function, u32 index)
4876{
4877 if (e->function != function)
4878 return 0;
4879 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4880 return 0;
4881 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4882 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4883 return 0;
4884 return 1;
4885}
4886
d8017474
AG		 4887struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4888 u32 function, u32 index)
8776e519
HB		 4889{
4890 int i;
d8017474 4891 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4892
ad312c7c 4893 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4894 struct kvm_cpuid_entry2 *e;
4895
ad312c7c 4896 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4897 if (is_matching_cpuid_entry(e, function, index)) {
4898 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4899 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4900 best = e;
4901 break;
4902 }
4903 /*
4904 * Both basic or both extended?
4905 */
4906 if (((e->function ^ function) & 0x80000000) == 0)
4907 if (!best || e->function > best->function)
4908 best = e;
4909 }
d8017474
AG		 4910 return best;
4911}
0e851880 4912EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4913
82725b20
DE		 4914int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4915{
4916 struct kvm_cpuid_entry2 *best;
4917
f7a71197
AK		 4918 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4919 if (!best || best->eax < 0x80000008)
4920 goto not_found;
82725b20
DE		 4921 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4922 if (best)
4923 return best->eax & 0xff;
f7a71197 4924not_found:
82725b20
DE		 4925 return 36;
4926}
4927
d8017474
AG		 4928void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4929{
4930 u32 function, index;
4931 struct kvm_cpuid_entry2 *best;
4932
4933 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4934 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4935 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4936 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4937 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4938 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4939 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4940 if (best) {
5fdbf976
MT		 4941 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4942 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4943 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4944 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4945 }
8776e519 4946 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4947 trace_kvm_cpuid(function,
4948 kvm_register_read(vcpu, VCPU_REGS_RAX),
4949 kvm_register_read(vcpu, VCPU_REGS_RBX),
4950 kvm_register_read(vcpu, VCPU_REGS_RCX),
4951 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4952}
4953EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4954
b6c7a5dc
HB		 4955/*
4956 * Check if userspace requested an interrupt window, and that the
4957 * interrupt window is open.
4958 *
4959 * No need to exit to userspace if we already have an interrupt queued.
4960 */
851ba692 4961static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4962{
8061823a 4963 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4964 vcpu->run->request_interrupt_window &&
5df56646 4965 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4966}
4967
851ba692 4968static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4969{
851ba692
AK		 4970 struct kvm_run *kvm_run = vcpu->run;
4971
91586a3b 4972 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4973 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4974 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4975 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4976 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4977 else
b6c7a5dc 4978 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4979 kvm_arch_interrupt_allowed(vcpu) &&
4980 !kvm_cpu_has_interrupt(vcpu) &&
4981 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4982}
4983
b93463aa
AK		 4984static void vapic_enter(struct kvm_vcpu *vcpu)
4985{
4986 struct kvm_lapic *apic = vcpu->arch.apic;
4987 struct page *page;
4988
4989 if (!apic || !apic->vapic_addr)
4990 return;
4991
4992 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4993
4994 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4995}
4996
4997static void vapic_exit(struct kvm_vcpu *vcpu)
4998{
4999 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5000 int idx;
b93463aa
AK		 5001
5002 if (!apic || !apic->vapic_addr)
5003 return;
5004
f656ce01 5005 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5006 kvm_release_page_dirty(apic->vapic_page);
5007 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5008 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5009}
5010
95ba8273
GN		 5011static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5012{
5013 int max_irr, tpr;
5014
5015 if (!kvm_x86_ops->update_cr8_intercept)
5016 return;
5017
88c808fd
AK		 5018 if (!vcpu->arch.apic)
5019 return;
5020
8db3baa2
GN		 5021 if (!vcpu->arch.apic->vapic_addr)
5022 max_irr = kvm_lapic_find_highest_irr(vcpu);
5023 else
5024 max_irr = -1;
95ba8273
GN		 5025
5026 if (max_irr != -1)
5027 max_irr >>= 4;
5028
5029 tpr = kvm_lapic_get_cr8(vcpu);
5030
5031 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5032}
5033
851ba692 5034static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5035{
5036 /* try to reinject previous events if any */
b59bb7bd 5037 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5038 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5039 vcpu->arch.exception.has_error_code,
5040 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5041 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5042 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5043 vcpu->arch.exception.error_code,
5044 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5045 return;
5046 }
5047
95ba8273
GN		 5048 if (vcpu->arch.nmi_injected) {
5049 kvm_x86_ops->set_nmi(vcpu);
5050 return;
5051 }
5052
5053 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5054 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5055 return;
5056 }
5057
5058 /* try to inject new event if pending */
5059 if (vcpu->arch.nmi_pending) {
5060 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5061 vcpu->arch.nmi_pending = false;
5062 vcpu->arch.nmi_injected = true;
5063 kvm_x86_ops->set_nmi(vcpu);
5064 }
5065 } else if (kvm_cpu_has_interrupt(vcpu)) {
5066 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5067 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5068 false);
5069 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5070 }
5071 }
5072}
5073
2acf923e
DC		 5074static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5075{
5076 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5077 !vcpu->guest_xcr0_loaded) {
5078 /* kvm_set_xcr() also depends on this */
5079 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5080 vcpu->guest_xcr0_loaded = 1;
5081 }
5082}
5083
5084static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5085{
5086 if (vcpu->guest_xcr0_loaded) {
5087 if (vcpu->arch.xcr0 != host_xcr0)
5088 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5089 vcpu->guest_xcr0_loaded = 0;
5090 }
5091}
5092
851ba692 5093static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5094{
5095 int r;
6a8b1d13 5096 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5097 vcpu->run->request_interrupt_window;
b6c7a5dc 5098
3e007509 5099 if (vcpu->requests) {
a8eeb04a 5100 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5101 kvm_mmu_unload(vcpu);
a8eeb04a 5102 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5103 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5104 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5105 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5106 if (unlikely(r))
5107 goto out;
5108 }
a8eeb04a 5109 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5110 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5111 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5112 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5113 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5114 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5115 r = 0;
5116 goto out;
5117 }
a8eeb04a 5118 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5119 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5120 r = 0;
5121 goto out;
5122 }
a8eeb04a 5123 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5124 vcpu->fpu_active = 0;
5125 kvm_x86_ops->fpu_deactivate(vcpu);
5126 }
af585b92
GN		 5127 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5128 /* Page is swapped out. Do synthetic halt */
5129 vcpu->arch.apf.halted = true;
5130 r = 1;
5131 goto out;
5132 }
2f52d58c 5133 }
b93463aa 5134
3e007509
AK		 5135 r = kvm_mmu_reload(vcpu);
5136 if (unlikely(r))
5137 goto out;
5138
b463a6f7
AK		 5139 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5140 inject_pending_event(vcpu);
5141
5142 /* enable NMI/IRQ window open exits if needed */
5143 if (vcpu->arch.nmi_pending)
5144 kvm_x86_ops->enable_nmi_window(vcpu);
5145 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5146 kvm_x86_ops->enable_irq_window(vcpu);
5147
5148 if (kvm_lapic_enabled(vcpu)) {
5149 update_cr8_intercept(vcpu);
5150 kvm_lapic_sync_to_vapic(vcpu);
5151 }
5152 }
5153
b6c7a5dc
HB		 5154 preempt_disable();
5155
5156 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5157 if (vcpu->fpu_active)
5158 kvm_load_guest_fpu(vcpu);
2acf923e 5159 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5160
d94e1dc9
AK		 5161 atomic_set(&vcpu->guest_mode, 1);
5162 smp_wmb();
b6c7a5dc 5163
d94e1dc9 5164 local_irq_disable();
32f88400 5165
d94e1dc9
AK		 5166 if (!atomic_read(&vcpu->guest_mode) || vcpu->requests
5167 || need_resched() || signal_pending(current)) {
5168 atomic_set(&vcpu->guest_mode, 0);
5169 smp_wmb();
6c142801
AK		 5170 local_irq_enable();
5171 preempt_enable();
b463a6f7 5172 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5173 r = 1;
5174 goto out;
5175 }
5176
f656ce01 5177 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5178
b6c7a5dc
HB		 5179 kvm_guest_enter();
5180
42dbaa5a 5181 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5182 set_debugreg(0, 7);
5183 set_debugreg(vcpu->arch.eff_db[0], 0);
5184 set_debugreg(vcpu->arch.eff_db[1], 1);
5185 set_debugreg(vcpu->arch.eff_db[2], 2);
5186 set_debugreg(vcpu->arch.eff_db[3], 3);
5187 }
b6c7a5dc 5188
229456fc 5189 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5190 kvm_x86_ops->run(vcpu);
b6c7a5dc 5191
24f1e32c
FW		 5192 /*
5193 * If the guest has used debug registers, at least dr7
5194 * will be disabled while returning to the host.
5195 * If we don't have active breakpoints in the host, we don't
5196 * care about the messed up debug address registers. But if
5197 * we have some of them active, restore the old state.
5198 */
59d8eb53 5199 if (hw_breakpoint_active())
24f1e32c 5200 hw_breakpoint_restore();
42dbaa5a 5201
1d5f066e
ZA		 5202 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5203
d94e1dc9
AK		 5204 atomic_set(&vcpu->guest_mode, 0);
5205 smp_wmb();
b6c7a5dc
HB		 5206 local_irq_enable();
5207
5208 ++vcpu->stat.exits;
5209
5210 /*
5211 * We must have an instruction between local_irq_enable() and
5212 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5213 * the interrupt shadow. The stat.exits increment will do nicely.
5214 * But we need to prevent reordering, hence this barrier():
5215 */
5216 barrier();
5217
5218 kvm_guest_exit();
5219
5220 preempt_enable();
5221
f656ce01 5222 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5223
b6c7a5dc
HB		 5224 /*
5225 * Profile KVM exit RIPs:
5226 */
5227 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5228 unsigned long rip = kvm_rip_read(vcpu);
5229 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5230 }
5231
298101da 5232
b93463aa
AK		 5233 kvm_lapic_sync_from_vapic(vcpu);
5234
851ba692 5235 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5236out:
5237 return r;
5238}
b6c7a5dc 5239
09cec754 5240
851ba692 5241static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5242{
5243 int r;
f656ce01 5244 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5245
5246 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5247 pr_debug("vcpu %d received sipi with vector # %x\n",
5248 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5249 kvm_lapic_reset(vcpu);
5f179287 5250 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5251 if (r)
5252 return r;
5253 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5254 }
5255
f656ce01 5256 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5257 vapic_enter(vcpu);
5258
5259 r = 1;
5260 while (r > 0) {
af585b92
GN		 5261 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5262 !vcpu->arch.apf.halted)
851ba692 5263 r = vcpu_enter_guest(vcpu);
d7690175 5264 else {
f656ce01 5265 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5266 kvm_vcpu_block(vcpu);
f656ce01 5267 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5268 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5269 {
5270 switch(vcpu->arch.mp_state) {
5271 case KVM_MP_STATE_HALTED:
d7690175 5272 vcpu->arch.mp_state =
09cec754
GN		 5273 KVM_MP_STATE_RUNNABLE;
5274 case KVM_MP_STATE_RUNNABLE:
af585b92 5275 vcpu->arch.apf.halted = false;
09cec754
GN		 5276 break;
5277 case KVM_MP_STATE_SIPI_RECEIVED:
5278 default:
5279 r = -EINTR;
5280 break;
5281 }
5282 }
d7690175
MT		 5283 }
5284
09cec754
GN		 5285 if (r <= 0)
5286 break;
5287
5288 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5289 if (kvm_cpu_has_pending_timer(vcpu))
5290 kvm_inject_pending_timer_irqs(vcpu);
5291
851ba692 5292 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5293 r = -EINTR;
851ba692 5294 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5295 ++vcpu->stat.request_irq_exits;
5296 }
af585b92
GN		 5297
5298 kvm_check_async_pf_completion(vcpu);
5299
09cec754
GN		 5300 if (signal_pending(current)) {
5301 r = -EINTR;
851ba692 5302 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5303 ++vcpu->stat.signal_exits;
5304 }
5305 if (need_resched()) {
f656ce01 5306 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5307 kvm_resched(vcpu);
f656ce01 5308 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5309 }
b6c7a5dc
HB		 5310 }
5311
f656ce01 5312 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5313
b93463aa
AK		 5314 vapic_exit(vcpu);
5315
b6c7a5dc
HB		 5316 return r;
5317}
5318
5319int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5320{
5321 int r;
5322 sigset_t sigsaved;
5323
ac9f6dc0
AK		 5324 if (vcpu->sigset_active)
5325 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5326
a4535290 5327 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5328 kvm_vcpu_block(vcpu);
d7690175 5329 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5330 r = -EAGAIN;
5331 goto out;
b6c7a5dc
HB		 5332 }
5333
b6c7a5dc
HB		 5334 /* re-sync apic's tpr */
5335 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 5336 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 5337
d2ddd1c4 5338 if (vcpu->arch.pio.count || vcpu->mmio_needed) {
92bf9748
GN		 5339 if (vcpu->mmio_needed) {
5340 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
5341 vcpu->mmio_read_completed = 1;
5342 vcpu->mmio_needed = 0;
b6c7a5dc 5343 }
f656ce01 5344 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5cd21917 5345 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
f656ce01 5346 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6d77dbfc 5347 if (r != EMULATE_DONE) {
b6c7a5dc
HB		 5348 r = 0;
5349 goto out;
5350 }
5351 }
5fdbf976
MT		 5352 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5353 kvm_register_write(vcpu, VCPU_REGS_RAX,
5354 kvm_run->hypercall.ret);
b6c7a5dc 5355
851ba692 5356 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5357
5358out:
f1d86e46 5359 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5360 if (vcpu->sigset_active)
5361 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5362
b6c7a5dc
HB		 5363 return r;
5364}
5365
5366int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5367{
5fdbf976
MT		 5368 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5369 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5370 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5371 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5372 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5373 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5374 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5375 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5376#ifdef CONFIG_X86_64
5fdbf976
MT		 5377 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5378 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5379 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5380 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5381 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5382 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5383 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5384 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5385#endif
5386
5fdbf976 5387 regs->rip = kvm_rip_read(vcpu);
91586a3b 5388 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5389
b6c7a5dc
HB		 5390 return 0;
5391}
5392
5393int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5394{
5fdbf976
MT		 5395 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5396 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5397 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5398 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5399 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5400 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5401 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5402 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5403#ifdef CONFIG_X86_64
5fdbf976
MT		 5404 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5405 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5406 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5407 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5408 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5409 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5410 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5411 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5412#endif
5413
5fdbf976 5414 kvm_rip_write(vcpu, regs->rip);
91586a3b 5415 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5416
b4f14abd
JK		 5417 vcpu->arch.exception.pending = false;
5418
3842d135
AK		 5419 kvm_make_request(KVM_REQ_EVENT, vcpu);
5420
b6c7a5dc
HB		 5421 return 0;
5422}
5423
b6c7a5dc
HB		 5424void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5425{
5426 struct kvm_segment cs;
5427
3e6e0aab 5428 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5429 *db = cs.db;
5430 *l = cs.l;
5431}
5432EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5433
5434int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5435 struct kvm_sregs *sregs)
5436{
89a27f4d 5437 struct desc_ptr dt;
b6c7a5dc 5438
3e6e0aab
GT		 5439 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5440 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5441 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5442 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5443 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5444 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5445
3e6e0aab
GT		 5446 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5447 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5448
5449 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5450 sregs->idt.limit = dt.size;
5451 sregs->idt.base = dt.address;
b6c7a5dc 5452 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5453 sregs->gdt.limit = dt.size;
5454 sregs->gdt.base = dt.address;
b6c7a5dc 5455
4d4ec087 5456 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 5457 sregs->cr2 = vcpu->arch.cr2;
5458 sregs->cr3 = vcpu->arch.cr3;
fc78f519 5459 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5460 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5461 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5462 sregs->apic_base = kvm_get_apic_base(vcpu);
5463
923c61bb 5464 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5465
36752c9b 5466 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5467 set_bit(vcpu->arch.interrupt.nr,
5468 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5469
b6c7a5dc
HB		 5470 return 0;
5471}
5472
62d9f0db
MT		 5473int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5474 struct kvm_mp_state *mp_state)
5475{
62d9f0db 5476 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5477 return 0;
5478}
5479
5480int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5481 struct kvm_mp_state *mp_state)
5482{
62d9f0db 5483 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5484 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5485 return 0;
5486}
5487
e269fb21
JK		 5488int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5489 bool has_error_code, u32 error_code)
b6c7a5dc 5490{
4d2179e1 5491 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
8ec4722d 5492 int ret;
e01c2426 5493
8ec4722d 5494 init_emulate_ctxt(vcpu);
c697518a 5495
9aabc88f 5496 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt,
e269fb21
JK		 5497 tss_selector, reason, has_error_code,
5498 error_code);
c697518a 5499
c697518a 5500 if (ret)
19d04437 5501 return EMULATE_FAIL;
37817f29 5502
4d2179e1 5503 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 5504 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
19d04437 5505 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 5506 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5507 return EMULATE_DONE;
37817f29
IE		 5508}
5509EXPORT_SYMBOL_GPL(kvm_task_switch);
5510
b6c7a5dc
HB		 5511int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5512 struct kvm_sregs *sregs)
5513{
5514 int mmu_reset_needed = 0;
923c61bb 5515 int pending_vec, max_bits;
89a27f4d 5516 struct desc_ptr dt;
b6c7a5dc 5517
89a27f4d
GN		 5518 dt.size = sregs->idt.limit;
5519 dt.address = sregs->idt.base;
b6c7a5dc 5520 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5521 dt.size = sregs->gdt.limit;
5522 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5523 kvm_x86_ops->set_gdt(vcpu, &dt);
5524
ad312c7c
ZX		 5525 vcpu->arch.cr2 = sregs->cr2;
5526 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5527 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5528
2d3ad1f4 5529 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5530
f6801dff 5531 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5532 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5533 kvm_set_apic_base(vcpu, sregs->apic_base);
5534
4d4ec087 5535 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5536 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5537 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5538
fc78f519 5539 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5540 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c
SY		 5541 if (sregs->cr4 & X86_CR4_OSXSAVE)
5542 update_cpuid(vcpu);
7c93be44 5543 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ff03a073 5544 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
7c93be44
MT		 5545 mmu_reset_needed = 1;
5546 }
b6c7a5dc
HB		 5547
5548 if (mmu_reset_needed)
5549 kvm_mmu_reset_context(vcpu);
5550
923c61bb
GN		 5551 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5552 pending_vec = find_first_bit(
5553 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5554 if (pending_vec < max_bits) {
66fd3f7f 5555 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5556 pr_debug("Set back pending irq %d\n", pending_vec);
5557 if (irqchip_in_kernel(vcpu->kvm))
5558 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5559 }
5560
3e6e0aab
GT		 5561 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5562 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5563 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5564 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5565 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5566 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5567
3e6e0aab
GT		 5568 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5569 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5570
5f0269f5
ME		 5571 update_cr8_intercept(vcpu);
5572
9c3e4aab 5573 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5574 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5575 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5576 !is_protmode(vcpu))
9c3e4aab
MT		 5577 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5578
3842d135
AK		 5579 kvm_make_request(KVM_REQ_EVENT, vcpu);
5580
b6c7a5dc
HB		 5581 return 0;
5582}
5583
d0bfb940
JK		 5584int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5585 struct kvm_guest_debug *dbg)
b6c7a5dc 5586{
355be0b9 5587 unsigned long rflags;
ae675ef0 5588 int i, r;
b6c7a5dc 5589
4f926bf2
JK		 5590 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5591 r = -EBUSY;
5592 if (vcpu->arch.exception.pending)
2122ff5e 5593 goto out;
4f926bf2
JK		 5594 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5595 kvm_queue_exception(vcpu, DB_VECTOR);
5596 else
5597 kvm_queue_exception(vcpu, BP_VECTOR);
5598 }
5599
91586a3b
JK		 5600 /*
5601 * Read rflags as long as potentially injected trace flags are still
5602 * filtered out.
5603 */
5604 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5605
5606 vcpu->guest_debug = dbg->control;
5607 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5608 vcpu->guest_debug = 0;
5609
5610 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5611 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5612 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5613 vcpu->arch.switch_db_regs =
5614 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5615 } else {
5616 for (i = 0; i < KVM_NR_DB_REGS; i++)
5617 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5618 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5619 }
5620
f92653ee
JK		 5621 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5622 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5623 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5624
91586a3b
JK		 5625 /*
5626 * Trigger an rflags update that will inject or remove the trace
5627 * flags.
5628 */
5629 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5630
355be0b9 5631 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5632
4f926bf2 5633 r = 0;
d0bfb940 5634
2122ff5e 5635out:
b6c7a5dc
HB		 5636
5637 return r;
5638}
5639
8b006791
ZX		 5640/*
5641 * Translate a guest virtual address to a guest physical address.
5642 */
5643int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5644 struct kvm_translation *tr)
5645{
5646 unsigned long vaddr = tr->linear_address;
5647 gpa_t gpa;
f656ce01 5648 int idx;
8b006791 5649
f656ce01 5650 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5651 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5652 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5653 tr->physical_address = gpa;
5654 tr->valid = gpa != UNMAPPED_GVA;
5655 tr->writeable = 1;
5656 tr->usermode = 0;
8b006791
ZX		 5657
5658 return 0;
5659}
5660
d0752060
HB		 5661int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5662{
98918833
SY		 5663 struct i387_fxsave_struct *fxsave =
5664 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5665
d0752060
HB		 5666 memcpy(fpu->fpr, fxsave->st_space, 128);
5667 fpu->fcw = fxsave->cwd;
5668 fpu->fsw = fxsave->swd;
5669 fpu->ftwx = fxsave->twd;
5670 fpu->last_opcode = fxsave->fop;
5671 fpu->last_ip = fxsave->rip;
5672 fpu->last_dp = fxsave->rdp;
5673 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5674
d0752060
HB		 5675 return 0;
5676}
5677
5678int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5679{
98918833
SY		 5680 struct i387_fxsave_struct *fxsave =
5681 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5682
d0752060
HB		 5683 memcpy(fxsave->st_space, fpu->fpr, 128);
5684 fxsave->cwd = fpu->fcw;
5685 fxsave->swd = fpu->fsw;
5686 fxsave->twd = fpu->ftwx;
5687 fxsave->fop = fpu->last_opcode;
5688 fxsave->rip = fpu->last_ip;
5689 fxsave->rdp = fpu->last_dp;
5690 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5691
d0752060
HB		 5692 return 0;
5693}
5694
10ab25cd 5695int fx_init(struct kvm_vcpu *vcpu)
d0752060 5696{
10ab25cd
JK		 5697 int err;
5698
5699 err = fpu_alloc(&vcpu->arch.guest_fpu);
5700 if (err)
5701 return err;
5702
98918833 5703 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5704
2acf923e
DC		 5705 /*
5706 * Ensure guest xcr0 is valid for loading
5707 */
5708 vcpu->arch.xcr0 = XSTATE_FP;
5709
ad312c7c 5710 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5711
5712 return 0;
d0752060
HB		 5713}
5714EXPORT_SYMBOL_GPL(fx_init);
5715
98918833
SY		 5716static void fx_free(struct kvm_vcpu *vcpu)
5717{
5718 fpu_free(&vcpu->arch.guest_fpu);
5719}
5720
d0752060
HB		 5721void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5722{
2608d7a1 5723 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5724 return;
5725
2acf923e
DC		 5726 /*
5727 * Restore all possible states in the guest,
5728 * and assume host would use all available bits.
5729 * Guest xcr0 would be loaded later.
5730 */
5731 kvm_put_guest_xcr0(vcpu);
d0752060 5732 vcpu->guest_fpu_loaded = 1;
7cf30855 5733 unlazy_fpu(current);
98918833 5734 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5735 trace_kvm_fpu(1);
d0752060 5736}
d0752060
HB		 5737
5738void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5739{
2acf923e
DC		 5740 kvm_put_guest_xcr0(vcpu);
5741
d0752060
HB		 5742 if (!vcpu->guest_fpu_loaded)
5743 return;
5744
5745 vcpu->guest_fpu_loaded = 0;
98918833 5746 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5747 ++vcpu->stat.fpu_reload;
a8eeb04a 5748 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5749 trace_kvm_fpu(0);
d0752060 5750}
e9b11c17
ZX		 5751
5752void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5753{
7f1ea208
JR		 5754 if (vcpu->arch.time_page) {
5755 kvm_release_page_dirty(vcpu->arch.time_page);
5756 vcpu->arch.time_page = NULL;
5757 }
5758
f5f48ee1 5759 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5760 fx_free(vcpu);
e9b11c17
ZX		 5761 kvm_x86_ops->vcpu_free(vcpu);
5762}
5763
5764struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5765 unsigned int id)
5766{
6755bae8
ZA		 5767 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5768 printk_once(KERN_WARNING
5769 "kvm: SMP vm created on host with unstable TSC; "
5770 "guest TSC will not be reliable\n");
26e5215f
AK		 5771 return kvm_x86_ops->vcpu_create(kvm, id);
5772}
e9b11c17 5773
26e5215f
AK		 5774int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5775{
5776 int r;
e9b11c17 5777
0bed3b56 5778 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5779 vcpu_load(vcpu);
5780 r = kvm_arch_vcpu_reset(vcpu);
5781 if (r == 0)
5782 r = kvm_mmu_setup(vcpu);
5783 vcpu_put(vcpu);
5784 if (r < 0)
5785 goto free_vcpu;
5786
26e5215f 5787 return 0;
e9b11c17
ZX		 5788free_vcpu:
5789 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5790 return r;
e9b11c17
ZX		 5791}
5792
d40ccc62 5793void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5794{
5795 vcpu_load(vcpu);
5796 kvm_mmu_unload(vcpu);
5797 vcpu_put(vcpu);
5798
98918833 5799 fx_free(vcpu);
e9b11c17
ZX		 5800 kvm_x86_ops->vcpu_free(vcpu);
5801}
5802
5803int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5804{
448fa4a9
JK		 5805 vcpu->arch.nmi_pending = false;
5806 vcpu->arch.nmi_injected = false;
5807
42dbaa5a
JK		 5808 vcpu->arch.switch_db_regs = 0;
5809 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5810 vcpu->arch.dr6 = DR6_FIXED_1;
5811 vcpu->arch.dr7 = DR7_FIXED_1;
5812
3842d135
AK		 5813 kvm_make_request(KVM_REQ_EVENT, vcpu);
5814
af585b92
GN		 5815 kvm_clear_async_pf_completion_queue(vcpu);
5816 kvm_async_pf_hash_reset(vcpu);
5817 vcpu->arch.apf.halted = false;
5818
e9b11c17
ZX		 5819 return kvm_x86_ops->vcpu_reset(vcpu);
5820}
5821
10474ae8 5822int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5823{
ca84d1a2
ZA		 5824 struct kvm *kvm;
5825 struct kvm_vcpu *vcpu;
5826 int i;
18863bdd
AK		 5827
5828 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 5829 list_for_each_entry(kvm, &vm_list, vm_list)
5830 kvm_for_each_vcpu(i, vcpu, kvm)
5831 if (vcpu->cpu == smp_processor_id())
c285545f 5832 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10474ae8 5833 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5834}
5835
5836void kvm_arch_hardware_disable(void *garbage)
5837{
5838 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5839 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5840}
5841
5842int kvm_arch_hardware_setup(void)
5843{
5844 return kvm_x86_ops->hardware_setup();
5845}
5846
5847void kvm_arch_hardware_unsetup(void)
5848{
5849 kvm_x86_ops->hardware_unsetup();
5850}
5851
5852void kvm_arch_check_processor_compat(void *rtn)
5853{
5854 kvm_x86_ops->check_processor_compatibility(rtn);
5855}
5856
5857int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5858{
5859 struct page *page;
5860 struct kvm *kvm;
5861 int r;
5862
5863 BUG_ON(vcpu->kvm == NULL);
5864 kvm = vcpu->kvm;
5865
9aabc88f 5866 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
14dfe855 5867 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
ad312c7c 5868 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c30a358d 5869 vcpu->arch.mmu.translate_gpa = translate_gpa;
02f59dc9 5870 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
c5af89b6 5871 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5872 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5873 else
a4535290 5874 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5875
5876 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5877 if (!page) {
5878 r = -ENOMEM;
5879 goto fail;
5880 }
ad312c7c 5881 vcpu->arch.pio_data = page_address(page);
e9b11c17 5882
c285545f
ZA		 5883 if (!kvm->arch.virtual_tsc_khz)
5884 kvm_arch_set_tsc_khz(kvm, max_tsc_khz);
5885
e9b11c17
ZX		 5886 r = kvm_mmu_create(vcpu);
5887 if (r < 0)
5888 goto fail_free_pio_data;
5889
5890 if (irqchip_in_kernel(kvm)) {
5891 r = kvm_create_lapic(vcpu);
5892 if (r < 0)
5893 goto fail_mmu_destroy;
5894 }
5895
890ca9ae
HY		 5896 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5897 GFP_KERNEL);
5898 if (!vcpu->arch.mce_banks) {
5899 r = -ENOMEM;
443c39bc 5900 goto fail_free_lapic;
890ca9ae
HY		 5901 }
5902 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5903
f5f48ee1
SY		 5904 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
5905 goto fail_free_mce_banks;
5906
af585b92
GN		 5907 kvm_async_pf_hash_reset(vcpu);
5908
e9b11c17 5909 return 0;
f5f48ee1
SY		 5910fail_free_mce_banks:
5911 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 5912fail_free_lapic:
5913 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5914fail_mmu_destroy:
5915 kvm_mmu_destroy(vcpu);
5916fail_free_pio_data:
ad312c7c 5917 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5918fail:
5919 return r;
5920}
5921
5922void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5923{
f656ce01
MT		 5924 int idx;
5925
36cb93fd 5926 kfree(vcpu->arch.mce_banks);
e9b11c17 5927 kvm_free_lapic(vcpu);
f656ce01 5928 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5929 kvm_mmu_destroy(vcpu);
f656ce01 5930 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5931 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5932}
d19a9cd2
ZX		 5933
5934struct kvm *kvm_arch_create_vm(void)
5935{
5936 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5937
5938 if (!kvm)
5939 return ERR_PTR(-ENOMEM);
5940
f05e70ac 5941 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5942 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5943
5550af4d
SY		 5944 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5945 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5946
99e3e30a 5947 spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 5948
d19a9cd2
ZX		 5949 return kvm;
5950}
5951
5952static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5953{
5954 vcpu_load(vcpu);
5955 kvm_mmu_unload(vcpu);
5956 vcpu_put(vcpu);
5957}
5958
5959static void kvm_free_vcpus(struct kvm *kvm)
5960{
5961 unsigned int i;
988a2cae 5962 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5963
5964 /*
5965 * Unpin any mmu pages first.
5966 */
af585b92
GN		 5967 kvm_for_each_vcpu(i, vcpu, kvm) {
5968 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 5969 kvm_unload_vcpu_mmu(vcpu);
af585b92 5970 }
988a2cae
GN		 5971 kvm_for_each_vcpu(i, vcpu, kvm)
5972 kvm_arch_vcpu_free(vcpu);
5973
5974 mutex_lock(&kvm->lock);
5975 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5976 kvm->vcpus[i] = NULL;
d19a9cd2 5977
988a2cae
GN		 5978 atomic_set(&kvm->online_vcpus, 0);
5979 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5980}
5981
ad8ba2cd
SY		 5982void kvm_arch_sync_events(struct kvm *kvm)
5983{
ba4cef31 5984 kvm_free_all_assigned_devices(kvm);
aea924f6 5985 kvm_free_pit(kvm);
ad8ba2cd
SY		 5986}
5987
d19a9cd2
ZX		 5988void kvm_arch_destroy_vm(struct kvm *kvm)
5989{
6eb55818 5990 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 5991 kfree(kvm->arch.vpic);
5992 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5993 kvm_free_vcpus(kvm);
5994 kvm_free_physmem(kvm);
3d45830c
AK		 5995 if (kvm->arch.apic_access_page)
5996 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5997 if (kvm->arch.ept_identity_pagetable)
5998 put_page(kvm->arch.ept_identity_pagetable);
64749204 5999 cleanup_srcu_struct(&kvm->srcu);
d19a9cd2
ZX		 6000 kfree(kvm);
6001}
0de10343 6002
f7784b8e
MT		 6003int kvm_arch_prepare_memory_region(struct kvm *kvm,
6004 struct kvm_memory_slot *memslot,
0de10343 6005 struct kvm_memory_slot old,
f7784b8e 6006 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6007 int user_alloc)
6008{
f7784b8e 6009 int npages = memslot->npages;
7ac77099
AK		 6010 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6011
6012 /* Prevent internal slot pages from being moved by fork()/COW. */
6013 if (memslot->id >= KVM_MEMORY_SLOTS)
6014 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6015
6016 /*To keep backward compatibility with older userspace,
6017 *x86 needs to hanlde !user_alloc case.
6018 */
6019 if (!user_alloc) {
6020 if (npages && !old.rmap) {
604b38ac
AA		 6021 unsigned long userspace_addr;
6022
72dc67a6 6023 down_write(&current->mm->mmap_sem);
604b38ac
AA		 6024 userspace_addr = do_mmap(NULL, 0,
6025 npages * PAGE_SIZE,
6026 PROT_READ | PROT_WRITE,
7ac77099 6027 map_flags,
604b38ac 6028 0);
72dc67a6 6029 up_write(&current->mm->mmap_sem);
0de10343 6030
604b38ac
AA		 6031 if (IS_ERR((void *)userspace_addr))
6032 return PTR_ERR((void *)userspace_addr);
6033
604b38ac 6034 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6035 }
6036 }
6037
f7784b8e
MT		 6038
6039 return 0;
6040}
6041
6042void kvm_arch_commit_memory_region(struct kvm *kvm,
6043 struct kvm_userspace_memory_region *mem,
6044 struct kvm_memory_slot old,
6045 int user_alloc)
6046{
6047
6048 int npages = mem->memory_size >> PAGE_SHIFT;
6049
6050 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6051 int ret;
6052
6053 down_write(&current->mm->mmap_sem);
6054 ret = do_munmap(current->mm, old.userspace_addr,
6055 old.npages * PAGE_SIZE);
6056 up_write(&current->mm->mmap_sem);
6057 if (ret < 0)
6058 printk(KERN_WARNING
6059 "kvm_vm_ioctl_set_memory_region: "
6060 "failed to munmap memory\n");
6061 }
6062
7c8a83b7 6063 spin_lock(&kvm->mmu_lock);
f05e70ac 6064 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 6065 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6066 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
6067 }
6068
6069 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6070 spin_unlock(&kvm->mmu_lock);
0de10343 6071}
1d737c8a 6072
34d4cb8f
MT		 6073void kvm_arch_flush_shadow(struct kvm *kvm)
6074{
6075 kvm_mmu_zap_all(kvm);
8986ecc0 6076 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6077}
6078
1d737c8a
ZX		 6079int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6080{
af585b92
GN		 6081 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6082 !vcpu->arch.apf.halted)
6083 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100
GN		 6084 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6085 || vcpu->arch.nmi_pending ||
6086 (kvm_arch_interrupt_allowed(vcpu) &&
6087 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6088}
5736199a 6089
5736199a
ZX		 6090void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6091{
32f88400
MT		 6092 int me;
6093 int cpu = vcpu->cpu;
5736199a
ZX		 6094
6095 if (waitqueue_active(&vcpu->wq)) {
6096 wake_up_interruptible(&vcpu->wq);
6097 ++vcpu->stat.halt_wakeup;
6098 }
32f88400
MT		 6099
6100 me = get_cpu();
6101 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
d94e1dc9 6102 if (atomic_xchg(&vcpu->guest_mode, 0))
32f88400 6103 smp_send_reschedule(cpu);
e9571ed5 6104 put_cpu();
5736199a 6105}
78646121
GN		 6106
6107int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6108{
6109 return kvm_x86_ops->interrupt_allowed(vcpu);
6110}
229456fc 6111
f92653ee
JK		 6112bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6113{
6114 unsigned long current_rip = kvm_rip_read(vcpu) +
6115 get_segment_base(vcpu, VCPU_SREG_CS);
6116
6117 return current_rip == linear_rip;
6118}
6119EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6120
94fe45da
JK		 6121unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6122{
6123 unsigned long rflags;
6124
6125 rflags = kvm_x86_ops->get_rflags(vcpu);
6126 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6127 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6128 return rflags;
6129}
6130EXPORT_SYMBOL_GPL(kvm_get_rflags);
6131
6132void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6133{
6134 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6135 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6136 rflags |= X86_EFLAGS_TF;
94fe45da 6137 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6138 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6139}
6140EXPORT_SYMBOL_GPL(kvm_set_rflags);
6141
56028d08
GN		 6142void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6143{
6144 int r;
6145
6146 if (!vcpu->arch.mmu.direct_map || is_error_page(work->page))
6147 return;
6148
6149 r = kvm_mmu_reload(vcpu);
6150 if (unlikely(r))
6151 return;
6152
6153 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6154}
6155
af585b92
GN		 6156static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6157{
6158 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6159}
6160
6161static inline u32 kvm_async_pf_next_probe(u32 key)
6162{
6163 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6164}
6165
6166static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6167{
6168 u32 key = kvm_async_pf_hash_fn(gfn);
6169
6170 while (vcpu->arch.apf.gfns[key] != ~0)
6171 key = kvm_async_pf_next_probe(key);
6172
6173 vcpu->arch.apf.gfns[key] = gfn;
6174}
6175
6176static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6177{
6178 int i;
6179 u32 key = kvm_async_pf_hash_fn(gfn);
6180
6181 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
6182 (vcpu->arch.apf.gfns[key] != gfn ||
6183 vcpu->arch.apf.gfns[key] == ~0); i++)
6184 key = kvm_async_pf_next_probe(key);
6185
6186 return key;
6187}
6188
6189bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6190{
6191 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6192}
6193
6194static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6195{
6196 u32 i, j, k;
6197
6198 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6199 while (true) {
6200 vcpu->arch.apf.gfns[i] = ~0;
6201 do {
6202 j = kvm_async_pf_next_probe(j);
6203 if (vcpu->arch.apf.gfns[j] == ~0)
6204 return;
6205 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6206 /*
6207 * k lies cyclically in ]i,j]
6208 * | i.k.j |
6209 * |....j i.k.| or |.k..j i...|
6210 */
6211 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6212 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6213 i = j;
6214 }
6215}
6216
6217void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6218 struct kvm_async_pf *work)
6219{
6220 trace_kvm_async_pf_not_present(work->gva);
6221
6222 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6223 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
6224}
6225
6226void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6227 struct kvm_async_pf *work)
6228{
6229 trace_kvm_async_pf_ready(work->gva);
6230 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6231}
6232
229456fc
MT		 6233EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6234EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6235EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6236EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6237EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6238EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6239EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6240EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6241EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6242EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6243EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6244EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
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