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KVM: direct mmio pfn check
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Avi Kivity <avi@qumranet.com>
10 * Yaniv Kamay <yaniv@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16
edf88417 17#include <linux/kvm_host.h>
313a3dc7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
7837699f 20#include "i8254.h"
37817f29 21#include "tss.h"
5fdbf976 22#include "kvm_cache_regs.h"
26eef70c 23#include "x86.h"
313a3dc7 24
18068523 25#include <linux/clocksource.h>
313a3dc7
CO		 26#include <linux/kvm.h>
27#include <linux/fs.h>
28#include <linux/vmalloc.h>
5fb76f9b 29#include <linux/module.h>
0de10343 30#include <linux/mman.h>
2bacc55c 31#include <linux/highmem.h>
043405e1
CO		 32
33#include <asm/uaccess.h>
d825ed0a 34#include <asm/msr.h>
a5f61300 35#include <asm/desc.h>
043405e1 36
313a3dc7 37#define MAX_IO_MSRS 256
a03490ed
CO		 38#define CR0_RESERVED_BITS \
39 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
40 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
41 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
42#define CR4_RESERVED_BITS \
43 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
44 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
45 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
46 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
47
48#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
50a37eb4
JR		 49/* EFER defaults:
50 * - enable syscall per default because its emulated by KVM
51 * - enable LME and LMA per default on 64 bit KVM
52 */
53#ifdef CONFIG_X86_64
54static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
55#else
56static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
57#endif
313a3dc7 58
ba1389b7
AK		 59#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
60#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 61
674eea0f
AK		 62static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
63 struct kvm_cpuid_entry2 __user *entries);
64
97896d04 65struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 66EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 67
417bc304 68struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 69 { "pf_fixed", VCPU_STAT(pf_fixed) },
70 { "pf_guest", VCPU_STAT(pf_guest) },
71 { "tlb_flush", VCPU_STAT(tlb_flush) },
72 { "invlpg", VCPU_STAT(invlpg) },
73 { "exits", VCPU_STAT(exits) },
74 { "io_exits", VCPU_STAT(io_exits) },
75 { "mmio_exits", VCPU_STAT(mmio_exits) },
76 { "signal_exits", VCPU_STAT(signal_exits) },
77 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 78 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 79 { "halt_exits", VCPU_STAT(halt_exits) },
80 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 81 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 82 { "request_irq", VCPU_STAT(request_irq_exits) },
83 { "irq_exits", VCPU_STAT(irq_exits) },
84 { "host_state_reload", VCPU_STAT(host_state_reload) },
85 { "efer_reload", VCPU_STAT(efer_reload) },
86 { "fpu_reload", VCPU_STAT(fpu_reload) },
87 { "insn_emulation", VCPU_STAT(insn_emulation) },
88 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
4cee5764
AK		 89 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
90 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
91 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
92 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
93 { "mmu_flooded", VM_STAT(mmu_flooded) },
94 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 95 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
0f74a24c 96 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 97 { "largepages", VM_STAT(lpages) },
417bc304
HB		 98 { NULL }
99};
100
101
5fb76f9b
CO		 102unsigned long segment_base(u16 selector)
103{
104 struct descriptor_table gdt;
a5f61300 105 struct desc_struct *d;
5fb76f9b
CO		 106 unsigned long table_base;
107 unsigned long v;
108
109 if (selector == 0)
110 return 0;
111
112 asm("sgdt %0" : "=m"(gdt));
113 table_base = gdt.base;
114
115 if (selector & 4) { /* from ldt */
116 u16 ldt_selector;
117
118 asm("sldt %0" : "=g"(ldt_selector));
119 table_base = segment_base(ldt_selector);
120 }
a5f61300
AK		 121 d = (struct desc_struct *)(table_base + (selector & ~7));
122 v = d->base0 | ((unsigned long)d->base1 << 16) |
123 ((unsigned long)d->base2 << 24);
5fb76f9b 124#ifdef CONFIG_X86_64
a5f61300
AK		 125 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
126 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 127#endif
128 return v;
129}
130EXPORT_SYMBOL_GPL(segment_base);
131
6866b83e
CO		 132u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
133{
134 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 135 return vcpu->arch.apic_base;
6866b83e 136 else
ad312c7c 137 return vcpu->arch.apic_base;
6866b83e
CO		 138}
139EXPORT_SYMBOL_GPL(kvm_get_apic_base);
140
141void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
142{
143 /* TODO: reserve bits check */
144 if (irqchip_in_kernel(vcpu->kvm))
145 kvm_lapic_set_base(vcpu, data);
146 else
ad312c7c 147 vcpu->arch.apic_base = data;
6866b83e
CO		 148}
149EXPORT_SYMBOL_GPL(kvm_set_apic_base);
150
298101da
AK		 151void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
152{
ad312c7c
ZX		 153 WARN_ON(vcpu->arch.exception.pending);
154 vcpu->arch.exception.pending = true;
155 vcpu->arch.exception.has_error_code = false;
156 vcpu->arch.exception.nr = nr;
298101da
AK		 157}
158EXPORT_SYMBOL_GPL(kvm_queue_exception);
159
c3c91fee
AK		 160void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
161 u32 error_code)
162{
163 ++vcpu->stat.pf_guest;
71c4dfaf
JR		 164 if (vcpu->arch.exception.pending) {
165 if (vcpu->arch.exception.nr == PF_VECTOR) {
166 printk(KERN_DEBUG "kvm: inject_page_fault:"
167 " double fault 0x%lx\n", addr);
168 vcpu->arch.exception.nr = DF_VECTOR;
169 vcpu->arch.exception.error_code = 0;
170 } else if (vcpu->arch.exception.nr == DF_VECTOR) {
171 /* triple fault -> shutdown */
172 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
173 }
c3c91fee
AK		 174 return;
175 }
ad312c7c 176 vcpu->arch.cr2 = addr;
c3c91fee
AK		 177 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
178}
179
3419ffc8
SY		 180void kvm_inject_nmi(struct kvm_vcpu *vcpu)
181{
182 vcpu->arch.nmi_pending = 1;
183}
184EXPORT_SYMBOL_GPL(kvm_inject_nmi);
185
298101da
AK		 186void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
187{
ad312c7c
ZX		 188 WARN_ON(vcpu->arch.exception.pending);
189 vcpu->arch.exception.pending = true;
190 vcpu->arch.exception.has_error_code = true;
191 vcpu->arch.exception.nr = nr;
192 vcpu->arch.exception.error_code = error_code;
298101da
AK		 193}
194EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
195
196static void __queue_exception(struct kvm_vcpu *vcpu)
197{
ad312c7c
ZX		 198 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
199 vcpu->arch.exception.has_error_code,
200 vcpu->arch.exception.error_code);
298101da
AK		 201}
202
a03490ed
CO		 203/*
204 * Load the pae pdptrs. Return true is they are all valid.
205 */
206int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
207{
208 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
209 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
210 int i;
211 int ret;
ad312c7c 212 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 213
a03490ed
CO		 214 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
215 offset * sizeof(u64), sizeof(pdpte));
216 if (ret < 0) {
217 ret = 0;
218 goto out;
219 }
220 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
221 if ((pdpte[i] & 1) && (pdpte[i] & 0xfffffff0000001e6ull)) {
222 ret = 0;
223 goto out;
224 }
225 }
226 ret = 1;
227
ad312c7c 228 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
a03490ed 229out:
a03490ed
CO		 230
231 return ret;
232}
cc4b6871 233EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 234
d835dfec
AK		 235static bool pdptrs_changed(struct kvm_vcpu *vcpu)
236{
ad312c7c 237 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 238 bool changed = true;
239 int r;
240
241 if (is_long_mode(vcpu) || !is_pae(vcpu))
242 return false;
243
ad312c7c 244 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 245 if (r < 0)
246 goto out;
ad312c7c 247 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 248out:
d835dfec
AK		 249
250 return changed;
251}
252
2d3ad1f4 253void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 254{
255 if (cr0 & CR0_RESERVED_BITS) {
256 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 257 cr0, vcpu->arch.cr0);
c1a5d4f9 258 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 259 return;
260 }
261
262 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
263 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 264 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 265 return;
266 }
267
268 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
269 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
270 "and a clear PE flag\n");
c1a5d4f9 271 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 272 return;
273 }
274
275 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
276#ifdef CONFIG_X86_64
ad312c7c 277 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 278 int cs_db, cs_l;
279
280 if (!is_pae(vcpu)) {
281 printk(KERN_DEBUG "set_cr0: #GP, start paging "
282 "in long mode while PAE is disabled\n");
c1a5d4f9 283 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 284 return;
285 }
286 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
287 if (cs_l) {
288 printk(KERN_DEBUG "set_cr0: #GP, start paging "
289 "in long mode while CS.L == 1\n");
c1a5d4f9 290 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 291 return;
292
293 }
294 } else
295#endif
ad312c7c 296 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 297 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
298 "reserved bits\n");
c1a5d4f9 299 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 300 return;
301 }
302
303 }
304
305 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 306 vcpu->arch.cr0 = cr0;
a03490ed 307
a03490ed 308 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 309 return;
310}
2d3ad1f4 311EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 312
2d3ad1f4 313void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 314{
2d3ad1f4 315 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
2714d1d3
FEL		 316 KVMTRACE_1D(LMSW, vcpu,
317 (u32)((vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f)),
318 handler);
a03490ed 319}
2d3ad1f4 320EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 321
2d3ad1f4 322void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed
CO		 323{
324 if (cr4 & CR4_RESERVED_BITS) {
325 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 326 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 327 return;
328 }
329
330 if (is_long_mode(vcpu)) {
331 if (!(cr4 & X86_CR4_PAE)) {
332 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
333 "in long mode\n");
c1a5d4f9 334 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 335 return;
336 }
337 } else if (is_paging(vcpu) && !is_pae(vcpu) && (cr4 & X86_CR4_PAE)
ad312c7c 338 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 339 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 340 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 341 return;
342 }
343
344 if (cr4 & X86_CR4_VMXE) {
345 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 346 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 347 return;
348 }
349 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 350 vcpu->arch.cr4 = cr4;
a03490ed 351 kvm_mmu_reset_context(vcpu);
a03490ed 352}
2d3ad1f4 353EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 354
2d3ad1f4 355void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 356{
ad312c7c 357 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
d835dfec
AK		 358 kvm_mmu_flush_tlb(vcpu);
359 return;
360 }
361
a03490ed
CO		 362 if (is_long_mode(vcpu)) {
363 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
364 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 365 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 366 return;
367 }
368 } else {
369 if (is_pae(vcpu)) {
370 if (cr3 & CR3_PAE_RESERVED_BITS) {
371 printk(KERN_DEBUG
372 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 373 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 374 return;
375 }
376 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
377 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
378 "reserved bits\n");
c1a5d4f9 379 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 380 return;
381 }
382 }
383 /*
384 * We don't check reserved bits in nonpae mode, because
385 * this isn't enforced, and VMware depends on this.
386 */
387 }
388
a03490ed
CO		 389 /*
390 * Does the new cr3 value map to physical memory? (Note, we
391 * catch an invalid cr3 even in real-mode, because it would
392 * cause trouble later on when we turn on paging anyway.)
393 *
394 * A real CPU would silently accept an invalid cr3 and would
395 * attempt to use it - with largely undefined (and often hard
396 * to debug) behavior on the guest side.
397 */
398 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 399 kvm_inject_gp(vcpu, 0);
a03490ed 400 else {
ad312c7c
ZX		 401 vcpu->arch.cr3 = cr3;
402 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 403 }
a03490ed 404}
2d3ad1f4 405EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 406
2d3ad1f4 407void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 408{
409 if (cr8 & CR8_RESERVED_BITS) {
410 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 411 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 412 return;
413 }
414 if (irqchip_in_kernel(vcpu->kvm))
415 kvm_lapic_set_tpr(vcpu, cr8);
416 else
ad312c7c 417 vcpu->arch.cr8 = cr8;
a03490ed 418}
2d3ad1f4 419EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 420
2d3ad1f4 421unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 422{
423 if (irqchip_in_kernel(vcpu->kvm))
424 return kvm_lapic_get_cr8(vcpu);
425 else
ad312c7c 426 return vcpu->arch.cr8;
a03490ed 427}
2d3ad1f4 428EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 429
043405e1
CO		 430/*
431 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
432 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
433 *
434 * This list is modified at module load time to reflect the
435 * capabilities of the host cpu.
436 */
437static u32 msrs_to_save[] = {
438 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
439 MSR_K6_STAR,
440#ifdef CONFIG_X86_64
441 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
442#endif
18068523 443 MSR_IA32_TIME_STAMP_COUNTER, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
847f0ad8 444 MSR_IA32_PERF_STATUS,
043405e1
CO		 445};
446
447static unsigned num_msrs_to_save;
448
449static u32 emulated_msrs[] = {
450 MSR_IA32_MISC_ENABLE,
451};
452
15c4a640
CO		 453static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
454{
f2b4b7dd 455 if (efer & efer_reserved_bits) {
15c4a640
CO		 456 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
457 efer);
c1a5d4f9 458 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 459 return;
460 }
461
462 if (is_paging(vcpu)
ad312c7c 463 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 464 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 465 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 466 return;
467 }
468
469 kvm_x86_ops->set_efer(vcpu, efer);
470
471 efer &= ~EFER_LMA;
ad312c7c 472 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 473
ad312c7c 474 vcpu->arch.shadow_efer = efer;
15c4a640
CO		 475}
476
f2b4b7dd
JR		 477void kvm_enable_efer_bits(u64 mask)
478{
479 efer_reserved_bits &= ~mask;
480}
481EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
482
483
15c4a640
CO		 484/*
485 * Writes msr value into into the appropriate "register".
486 * Returns 0 on success, non-0 otherwise.
487 * Assumes vcpu_load() was already called.
488 */
489int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
490{
491 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
492}
493
313a3dc7
CO		 494/*
495 * Adapt set_msr() to msr_io()'s calling convention
496 */
497static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
498{
499 return kvm_set_msr(vcpu, index, *data);
500}
501
18068523
GOC		 502static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
503{
504 static int version;
50d0a0f9
GH		 505 struct pvclock_wall_clock wc;
506 struct timespec now, sys, boot;
18068523
GOC		 507
508 if (!wall_clock)
509 return;
510
511 version++;
512
18068523
GOC		 513 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
514
50d0a0f9
GH		 515 /*
516 * The guest calculates current wall clock time by adding
517 * system time (updated by kvm_write_guest_time below) to the
518 * wall clock specified here. guest system time equals host
519 * system time for us, thus we must fill in host boot time here.
520 */
521 now = current_kernel_time();
522 ktime_get_ts(&sys);
523 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
524
525 wc.sec = boot.tv_sec;
526 wc.nsec = boot.tv_nsec;
527 wc.version = version;
18068523
GOC		 528
529 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
530
531 version++;
532 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 533}
534
50d0a0f9
GH		 535static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
536{
537 uint32_t quotient, remainder;
538
539 /* Don't try to replace with do_div(), this one calculates
540 * "(dividend << 32) / divisor" */
541 __asm__ ( "divl %4"
542 : "=a" (quotient), "=d" (remainder)
543 : "0" (0), "1" (dividend), "r" (divisor) );
544 return quotient;
545}
546
547static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
548{
549 uint64_t nsecs = 1000000000LL;
550 int32_t shift = 0;
551 uint64_t tps64;
552 uint32_t tps32;
553
554 tps64 = tsc_khz * 1000LL;
555 while (tps64 > nsecs*2) {
556 tps64 >>= 1;
557 shift--;
558 }
559
560 tps32 = (uint32_t)tps64;
561 while (tps32 <= (uint32_t)nsecs) {
562 tps32 <<= 1;
563 shift++;
564 }
565
566 hv_clock->tsc_shift = shift;
567 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
568
569 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
570 __FUNCTION__, tsc_khz, hv_clock->tsc_shift,
571 hv_clock->tsc_to_system_mul);
572}
573
18068523
GOC		 574static void kvm_write_guest_time(struct kvm_vcpu *v)
575{
576 struct timespec ts;
577 unsigned long flags;
578 struct kvm_vcpu_arch *vcpu = &v->arch;
579 void *shared_kaddr;
580
581 if ((!vcpu->time_page))
582 return;
583
50d0a0f9
GH		 584 if (unlikely(vcpu->hv_clock_tsc_khz != tsc_khz)) {
585 kvm_set_time_scale(tsc_khz, &vcpu->hv_clock);
586 vcpu->hv_clock_tsc_khz = tsc_khz;
587 }
588
18068523
GOC		 589 /* Keep irq disabled to prevent changes to the clock */
590 local_irq_save(flags);
591 kvm_get_msr(v, MSR_IA32_TIME_STAMP_COUNTER,
592 &vcpu->hv_clock.tsc_timestamp);
593 ktime_get_ts(&ts);
594 local_irq_restore(flags);
595
596 /* With all the info we got, fill in the values */
597
598 vcpu->hv_clock.system_time = ts.tv_nsec +
599 (NSEC_PER_SEC * (u64)ts.tv_sec);
600 /*
601 * The interface expects us to write an even number signaling that the
602 * update is finished. Since the guest won't see the intermediate
50d0a0f9 603 * state, we just increase by 2 at the end.
18068523 604 */
50d0a0f9 605 vcpu->hv_clock.version += 2;
18068523
GOC		 606
607 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
608
609 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 610 sizeof(vcpu->hv_clock));
18068523
GOC		 611
612 kunmap_atomic(shared_kaddr, KM_USER0);
613
614 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
615}
616
9ba075a6
AK		 617static bool msr_mtrr_valid(unsigned msr)
618{
619 switch (msr) {
620 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
621 case MSR_MTRRfix64K_00000:
622 case MSR_MTRRfix16K_80000:
623 case MSR_MTRRfix16K_A0000:
624 case MSR_MTRRfix4K_C0000:
625 case MSR_MTRRfix4K_C8000:
626 case MSR_MTRRfix4K_D0000:
627 case MSR_MTRRfix4K_D8000:
628 case MSR_MTRRfix4K_E0000:
629 case MSR_MTRRfix4K_E8000:
630 case MSR_MTRRfix4K_F0000:
631 case MSR_MTRRfix4K_F8000:
632 case MSR_MTRRdefType:
633 case MSR_IA32_CR_PAT:
634 return true;
635 case 0x2f8:
636 return true;
637 }
638 return false;
639}
640
641static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
642{
643 if (!msr_mtrr_valid(msr))
644 return 1;
645
646 vcpu->arch.mtrr[msr - 0x200] = data;
647 return 0;
648}
15c4a640
CO		 649
650int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
651{
652 switch (msr) {
15c4a640
CO		 653 case MSR_EFER:
654 set_efer(vcpu, data);
655 break;
15c4a640
CO		 656 case MSR_IA32_MC0_STATUS:
657 pr_unimpl(vcpu, "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n",
b8688d51 658 __func__, data);
15c4a640
CO		 659 break;
660 case MSR_IA32_MCG_STATUS:
661 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_STATUS 0x%llx, nop\n",
b8688d51 662 __func__, data);
15c4a640 663 break;
c7ac679c
JR		 664 case MSR_IA32_MCG_CTL:
665 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_CTL 0x%llx, nop\n",
b8688d51 666 __func__, data);
c7ac679c 667 break;
b5e2fec0
AG		 668 case MSR_IA32_DEBUGCTLMSR:
669 if (!data) {
670 /* We support the non-activated case already */
671 break;
672 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
673 /* Values other than LBR and BTF are vendor-specific,
674 thus reserved and should throw a #GP */
675 return 1;
676 }
677 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
678 __func__, data);
679 break;
15c4a640
CO		 680 case MSR_IA32_UCODE_REV:
681 case MSR_IA32_UCODE_WRITE:
15c4a640 682 break;
9ba075a6
AK		 683 case 0x200 ... 0x2ff:
684 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 685 case MSR_IA32_APICBASE:
686 kvm_set_apic_base(vcpu, data);
687 break;
688 case MSR_IA32_MISC_ENABLE:
ad312c7c 689 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 690 break;
18068523
GOC		 691 case MSR_KVM_WALL_CLOCK:
692 vcpu->kvm->arch.wall_clock = data;
693 kvm_write_wall_clock(vcpu->kvm, data);
694 break;
695 case MSR_KVM_SYSTEM_TIME: {
696 if (vcpu->arch.time_page) {
697 kvm_release_page_dirty(vcpu->arch.time_page);
698 vcpu->arch.time_page = NULL;
699 }
700
701 vcpu->arch.time = data;
702
703 /* we verify if the enable bit is set... */
704 if (!(data & 1))
705 break;
706
707 /* ...but clean it before doing the actual write */
708 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
709
18068523 710 down_read(&current->mm->mmap_sem);
18068523
GOC		 711 vcpu->arch.time_page =
712 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 713 up_read(&current->mm->mmap_sem);
714
715 if (is_error_page(vcpu->arch.time_page)) {
716 kvm_release_page_clean(vcpu->arch.time_page);
717 vcpu->arch.time_page = NULL;
718 }
719
720 kvm_write_guest_time(vcpu);
721 break;
722 }
15c4a640 723 default:
565f1fbd 724 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", msr, data);
15c4a640
CO		 725 return 1;
726 }
727 return 0;
728}
729EXPORT_SYMBOL_GPL(kvm_set_msr_common);
730
731
732/*
733 * Reads an msr value (of 'msr_index') into 'pdata'.
734 * Returns 0 on success, non-0 otherwise.
735 * Assumes vcpu_load() was already called.
736 */
737int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
738{
739 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
740}
741
9ba075a6
AK		 742static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
743{
744 if (!msr_mtrr_valid(msr))
745 return 1;
746
747 *pdata = vcpu->arch.mtrr[msr - 0x200];
748 return 0;
749}
750
15c4a640
CO		 751int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
752{
753 u64 data;
754
755 switch (msr) {
756 case 0xc0010010: /* SYSCFG */
757 case 0xc0010015: /* HWCR */
758 case MSR_IA32_PLATFORM_ID:
759 case MSR_IA32_P5_MC_ADDR:
760 case MSR_IA32_P5_MC_TYPE:
761 case MSR_IA32_MC0_CTL:
762 case MSR_IA32_MCG_STATUS:
763 case MSR_IA32_MCG_CAP:
c7ac679c 764 case MSR_IA32_MCG_CTL:
15c4a640
CO		 765 case MSR_IA32_MC0_MISC:
766 case MSR_IA32_MC0_MISC+4:
767 case MSR_IA32_MC0_MISC+8:
768 case MSR_IA32_MC0_MISC+12:
769 case MSR_IA32_MC0_MISC+16:
770 case MSR_IA32_UCODE_REV:
15c4a640 771 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 772 case MSR_IA32_DEBUGCTLMSR:
773 case MSR_IA32_LASTBRANCHFROMIP:
774 case MSR_IA32_LASTBRANCHTOIP:
775 case MSR_IA32_LASTINTFROMIP:
776 case MSR_IA32_LASTINTTOIP:
15c4a640
CO		 777 data = 0;
778 break;
9ba075a6
AK		 779 case MSR_MTRRcap:
780 data = 0x500 | KVM_NR_VAR_MTRR;
781 break;
782 case 0x200 ... 0x2ff:
783 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 784 case 0xcd: /* fsb frequency */
785 data = 3;
786 break;
787 case MSR_IA32_APICBASE:
788 data = kvm_get_apic_base(vcpu);
789 break;
790 case MSR_IA32_MISC_ENABLE:
ad312c7c 791 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 792 break;
847f0ad8
AG		 793 case MSR_IA32_PERF_STATUS:
794 /* TSC increment by tick */
795 data = 1000ULL;
796 /* CPU multiplier */
797 data |= (((uint64_t)4ULL) << 40);
798 break;
15c4a640 799 case MSR_EFER:
ad312c7c 800 data = vcpu->arch.shadow_efer;
15c4a640 801 break;
18068523
GOC		 802 case MSR_KVM_WALL_CLOCK:
803 data = vcpu->kvm->arch.wall_clock;
804 break;
805 case MSR_KVM_SYSTEM_TIME:
806 data = vcpu->arch.time;
807 break;
15c4a640
CO		 808 default:
809 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
810 return 1;
811 }
812 *pdata = data;
813 return 0;
814}
815EXPORT_SYMBOL_GPL(kvm_get_msr_common);
816
313a3dc7
CO		 817/*
818 * Read or write a bunch of msrs. All parameters are kernel addresses.
819 *
820 * @return number of msrs set successfully.
821 */
822static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
823 struct kvm_msr_entry *entries,
824 int (*do_msr)(struct kvm_vcpu *vcpu,
825 unsigned index, u64 *data))
826{
827 int i;
828
829 vcpu_load(vcpu);
830
3200f405 831 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 832 for (i = 0; i < msrs->nmsrs; ++i)
833 if (do_msr(vcpu, entries[i].index, &entries[i].data))
834 break;
3200f405 835 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 836
837 vcpu_put(vcpu);
838
839 return i;
840}
841
842/*
843 * Read or write a bunch of msrs. Parameters are user addresses.
844 *
845 * @return number of msrs set successfully.
846 */
847static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
848 int (*do_msr)(struct kvm_vcpu *vcpu,
849 unsigned index, u64 *data),
850 int writeback)
851{
852 struct kvm_msrs msrs;
853 struct kvm_msr_entry *entries;
854 int r, n;
855 unsigned size;
856
857 r = -EFAULT;
858 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
859 goto out;
860
861 r = -E2BIG;
862 if (msrs.nmsrs >= MAX_IO_MSRS)
863 goto out;
864
865 r = -ENOMEM;
866 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
867 entries = vmalloc(size);
868 if (!entries)
869 goto out;
870
871 r = -EFAULT;
872 if (copy_from_user(entries, user_msrs->entries, size))
873 goto out_free;
874
875 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
876 if (r < 0)
877 goto out_free;
878
879 r = -EFAULT;
880 if (writeback && copy_to_user(user_msrs->entries, entries, size))
881 goto out_free;
882
883 r = n;
884
885out_free:
886 vfree(entries);
887out:
888 return r;
889}
890
018d00d2
ZX		 891int kvm_dev_ioctl_check_extension(long ext)
892{
893 int r;
894
895 switch (ext) {
896 case KVM_CAP_IRQCHIP:
897 case KVM_CAP_HLT:
898 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
899 case KVM_CAP_USER_MEMORY:
900 case KVM_CAP_SET_TSS_ADDR:
07716717 901 case KVM_CAP_EXT_CPUID:
18068523 902 case KVM_CAP_CLOCKSOURCE:
7837699f 903 case KVM_CAP_PIT:
a28e4f5a 904 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 905 case KVM_CAP_MP_STATE:
ed848624 906 case KVM_CAP_SYNC_MMU:
018d00d2
ZX		 907 r = 1;
908 break;
542472b5
LV		 909 case KVM_CAP_COALESCED_MMIO:
910 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
911 break;
774ead3a
AK		 912 case KVM_CAP_VAPIC:
913 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
914 break;
f725230a
AK		 915 case KVM_CAP_NR_VCPUS:
916 r = KVM_MAX_VCPUS;
917 break;
a988b910
AK		 918 case KVM_CAP_NR_MEMSLOTS:
919 r = KVM_MEMORY_SLOTS;
920 break;
2f333bcb
MT		 921 case KVM_CAP_PV_MMU:
922 r = !tdp_enabled;
923 break;
018d00d2
ZX		 924 default:
925 r = 0;
926 break;
927 }
928 return r;
929
930}
931
043405e1
CO		 932long kvm_arch_dev_ioctl(struct file *filp,
933 unsigned int ioctl, unsigned long arg)
934{
935 void __user *argp = (void __user *)arg;
936 long r;
937
938 switch (ioctl) {
939 case KVM_GET_MSR_INDEX_LIST: {
940 struct kvm_msr_list __user *user_msr_list = argp;
941 struct kvm_msr_list msr_list;
942 unsigned n;
943
944 r = -EFAULT;
945 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
946 goto out;
947 n = msr_list.nmsrs;
948 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
949 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
950 goto out;
951 r = -E2BIG;
952 if (n < num_msrs_to_save)
953 goto out;
954 r = -EFAULT;
955 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
956 num_msrs_to_save * sizeof(u32)))
957 goto out;
958 if (copy_to_user(user_msr_list->indices
959 + num_msrs_to_save * sizeof(u32),
960 &emulated_msrs,
961 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
962 goto out;
963 r = 0;
964 break;
965 }
674eea0f
AK		 966 case KVM_GET_SUPPORTED_CPUID: {
967 struct kvm_cpuid2 __user *cpuid_arg = argp;
968 struct kvm_cpuid2 cpuid;
969
970 r = -EFAULT;
971 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
972 goto out;
973 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
974 cpuid_arg->entries);
975 if (r)
976 goto out;
977
978 r = -EFAULT;
979 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
980 goto out;
981 r = 0;
982 break;
983 }
043405e1
CO		 984 default:
985 r = -EINVAL;
986 }
987out:
988 return r;
989}
990
313a3dc7
CO		 991void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
992{
993 kvm_x86_ops->vcpu_load(vcpu, cpu);
18068523 994 kvm_write_guest_time(vcpu);
313a3dc7
CO		 995}
996
997void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
998{
999 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 1000 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1001}
1002
07716717 1003static int is_efer_nx(void)
313a3dc7
CO		 1004{
1005 u64 efer;
313a3dc7
CO		 1006
1007 rdmsrl(MSR_EFER, efer);
07716717
DK		 1008 return efer & EFER_NX;
1009}
1010
1011static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1012{
1013 int i;
1014 struct kvm_cpuid_entry2 *e, *entry;
1015
313a3dc7 1016 entry = NULL;
ad312c7c
ZX		 1017 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1018 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1019 if (e->function == 0x80000001) {
1020 entry = e;
1021 break;
1022 }
1023 }
07716717 1024 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1025 entry->edx &= ~(1 << 20);
1026 printk(KERN_INFO "kvm: guest NX capability removed\n");
1027 }
1028}
1029
07716717 1030/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1031static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1032 struct kvm_cpuid *cpuid,
1033 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1034{
1035 int r, i;
1036 struct kvm_cpuid_entry *cpuid_entries;
1037
1038 r = -E2BIG;
1039 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1040 goto out;
1041 r = -ENOMEM;
1042 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1043 if (!cpuid_entries)
1044 goto out;
1045 r = -EFAULT;
1046 if (copy_from_user(cpuid_entries, entries,
1047 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1048 goto out_free;
1049 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1050 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1051 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1052 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1053 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1054 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1055 vcpu->arch.cpuid_entries[i].index = 0;
1056 vcpu->arch.cpuid_entries[i].flags = 0;
1057 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1058 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1059 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1060 }
1061 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1062 cpuid_fix_nx_cap(vcpu);
1063 r = 0;
1064
1065out_free:
1066 vfree(cpuid_entries);
1067out:
1068 return r;
1069}
1070
1071static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
1072 struct kvm_cpuid2 *cpuid,
1073 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1074{
1075 int r;
1076
1077 r = -E2BIG;
1078 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1079 goto out;
1080 r = -EFAULT;
ad312c7c 1081 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1082 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1083 goto out;
ad312c7c 1084 vcpu->arch.cpuid_nent = cpuid->nent;
313a3dc7
CO		 1085 return 0;
1086
1087out:
1088 return r;
1089}
1090
07716717
DK		 1091static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
1092 struct kvm_cpuid2 *cpuid,
1093 struct kvm_cpuid_entry2 __user *entries)
1094{
1095 int r;
1096
1097 r = -E2BIG;
ad312c7c 1098 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1099 goto out;
1100 r = -EFAULT;
ad312c7c
ZX		 1101 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
1102 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1103 goto out;
1104 return 0;
1105
1106out:
ad312c7c 1107 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1108 return r;
1109}
1110
1111static inline u32 bit(int bitno)
1112{
1113 return 1 << (bitno & 31);
1114}
1115
1116static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1117 u32 index)
1118{
1119 entry->function = function;
1120 entry->index = index;
1121 cpuid_count(entry->function, entry->index,
1122 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
1123 entry->flags = 0;
1124}
1125
1126static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1127 u32 index, int *nent, int maxnent)
1128{
1129 const u32 kvm_supported_word0_x86_features = bit(X86_FEATURE_FPU) |
1130 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1131 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1132 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1133 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1134 bit(X86_FEATURE_SEP) | bit(X86_FEATURE_PGE) |
1135 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1136 bit(X86_FEATURE_CLFLSH) | bit(X86_FEATURE_MMX) |
1137 bit(X86_FEATURE_FXSR) | bit(X86_FEATURE_XMM) |
1138 bit(X86_FEATURE_XMM2) | bit(X86_FEATURE_SELFSNOOP);
1139 const u32 kvm_supported_word1_x86_features = bit(X86_FEATURE_FPU) |
1140 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1141 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1142 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1143 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1144 bit(X86_FEATURE_PGE) |
1145 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1146 bit(X86_FEATURE_MMX) | bit(X86_FEATURE_FXSR) |
1147 bit(X86_FEATURE_SYSCALL) |
1148 (bit(X86_FEATURE_NX) && is_efer_nx()) |
1149#ifdef CONFIG_X86_64
1150 bit(X86_FEATURE_LM) |
1151#endif
1152 bit(X86_FEATURE_MMXEXT) |
1153 bit(X86_FEATURE_3DNOWEXT) |
1154 bit(X86_FEATURE_3DNOW);
1155 const u32 kvm_supported_word3_x86_features =
1156 bit(X86_FEATURE_XMM3) | bit(X86_FEATURE_CX16);
1157 const u32 kvm_supported_word6_x86_features =
1158 bit(X86_FEATURE_LAHF_LM) | bit(X86_FEATURE_CMP_LEGACY);
1159
1160 /* all func 2 cpuid_count() should be called on the same cpu */
1161 get_cpu();
1162 do_cpuid_1_ent(entry, function, index);
1163 ++*nent;
1164
1165 switch (function) {
1166 case 0:
1167 entry->eax = min(entry->eax, (u32)0xb);
1168 break;
1169 case 1:
1170 entry->edx &= kvm_supported_word0_x86_features;
1171 entry->ecx &= kvm_supported_word3_x86_features;
1172 break;
1173 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1174 * may return different values. This forces us to get_cpu() before
1175 * issuing the first command, and also to emulate this annoying behavior
1176 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1177 case 2: {
1178 int t, times = entry->eax & 0xff;
1179
1180 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1181 for (t = 1; t < times && *nent < maxnent; ++t) {
1182 do_cpuid_1_ent(&entry[t], function, 0);
1183 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1184 ++*nent;
1185 }
1186 break;
1187 }
1188 /* function 4 and 0xb have additional index. */
1189 case 4: {
14af3f3c 1190 int i, cache_type;
07716717
DK		 1191
1192 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1193 /* read more entries until cache_type is zero */
14af3f3c
HH		 1194 for (i = 1; *nent < maxnent; ++i) {
1195 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1196 if (!cache_type)
1197 break;
14af3f3c
HH		 1198 do_cpuid_1_ent(&entry[i], function, i);
1199 entry[i].flags |=
07716717
DK		 1200 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1201 ++*nent;
1202 }
1203 break;
1204 }
1205 case 0xb: {
14af3f3c 1206 int i, level_type;
07716717
DK		 1207
1208 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1209 /* read more entries until level_type is zero */
14af3f3c
HH		 1210 for (i = 1; *nent < maxnent; ++i) {
1211 level_type = entry[i - 1].ecx & 0xff;
07716717
DK		 1212 if (!level_type)
1213 break;
14af3f3c
HH		 1214 do_cpuid_1_ent(&entry[i], function, i);
1215 entry[i].flags |=
07716717
DK		 1216 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1217 ++*nent;
1218 }
1219 break;
1220 }
1221 case 0x80000000:
1222 entry->eax = min(entry->eax, 0x8000001a);
1223 break;
1224 case 0x80000001:
1225 entry->edx &= kvm_supported_word1_x86_features;
1226 entry->ecx &= kvm_supported_word6_x86_features;
1227 break;
1228 }
1229 put_cpu();
1230}
1231
674eea0f 1232static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
07716717
DK		 1233 struct kvm_cpuid_entry2 __user *entries)
1234{
1235 struct kvm_cpuid_entry2 *cpuid_entries;
1236 int limit, nent = 0, r = -E2BIG;
1237 u32 func;
1238
1239 if (cpuid->nent < 1)
1240 goto out;
1241 r = -ENOMEM;
1242 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1243 if (!cpuid_entries)
1244 goto out;
1245
1246 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1247 limit = cpuid_entries[0].eax;
1248 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1249 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1250 &nent, cpuid->nent);
1251 r = -E2BIG;
1252 if (nent >= cpuid->nent)
1253 goto out_free;
1254
1255 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1256 limit = cpuid_entries[nent - 1].eax;
1257 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1258 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1259 &nent, cpuid->nent);
1260 r = -EFAULT;
1261 if (copy_to_user(entries, cpuid_entries,
1262 nent * sizeof(struct kvm_cpuid_entry2)))
1263 goto out_free;
1264 cpuid->nent = nent;
1265 r = 0;
1266
1267out_free:
1268 vfree(cpuid_entries);
1269out:
1270 return r;
1271}
1272
313a3dc7
CO		 1273static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1274 struct kvm_lapic_state *s)
1275{
1276 vcpu_load(vcpu);
ad312c7c 1277 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1278 vcpu_put(vcpu);
1279
1280 return 0;
1281}
1282
1283static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1284 struct kvm_lapic_state *s)
1285{
1286 vcpu_load(vcpu);
ad312c7c 1287 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7
CO		 1288 kvm_apic_post_state_restore(vcpu);
1289 vcpu_put(vcpu);
1290
1291 return 0;
1292}
1293
f77bc6a4
ZX		 1294static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1295 struct kvm_interrupt *irq)
1296{
1297 if (irq->irq < 0 || irq->irq >= 256)
1298 return -EINVAL;
1299 if (irqchip_in_kernel(vcpu->kvm))
1300 return -ENXIO;
1301 vcpu_load(vcpu);
1302
ad312c7c
ZX		 1303 set_bit(irq->irq, vcpu->arch.irq_pending);
1304 set_bit(irq->irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
f77bc6a4
ZX		 1305
1306 vcpu_put(vcpu);
1307
1308 return 0;
1309}
1310
b209749f
AK		 1311static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1312 struct kvm_tpr_access_ctl *tac)
1313{
1314 if (tac->flags)
1315 return -EINVAL;
1316 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1317 return 0;
1318}
1319
313a3dc7
CO		 1320long kvm_arch_vcpu_ioctl(struct file *filp,
1321 unsigned int ioctl, unsigned long arg)
1322{
1323 struct kvm_vcpu *vcpu = filp->private_data;
1324 void __user *argp = (void __user *)arg;
1325 int r;
1326
1327 switch (ioctl) {
1328 case KVM_GET_LAPIC: {
1329 struct kvm_lapic_state lapic;
1330
1331 memset(&lapic, 0, sizeof lapic);
1332 r = kvm_vcpu_ioctl_get_lapic(vcpu, &lapic);
1333 if (r)
1334 goto out;
1335 r = -EFAULT;
1336 if (copy_to_user(argp, &lapic, sizeof lapic))
1337 goto out;
1338 r = 0;
1339 break;
1340 }
1341 case KVM_SET_LAPIC: {
1342 struct kvm_lapic_state lapic;
1343
1344 r = -EFAULT;
1345 if (copy_from_user(&lapic, argp, sizeof lapic))
1346 goto out;
1347 r = kvm_vcpu_ioctl_set_lapic(vcpu, &lapic);;
1348 if (r)
1349 goto out;
1350 r = 0;
1351 break;
1352 }
f77bc6a4
ZX		 1353 case KVM_INTERRUPT: {
1354 struct kvm_interrupt irq;
1355
1356 r = -EFAULT;
1357 if (copy_from_user(&irq, argp, sizeof irq))
1358 goto out;
1359 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1360 if (r)
1361 goto out;
1362 r = 0;
1363 break;
1364 }
313a3dc7
CO		 1365 case KVM_SET_CPUID: {
1366 struct kvm_cpuid __user *cpuid_arg = argp;
1367 struct kvm_cpuid cpuid;
1368
1369 r = -EFAULT;
1370 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1371 goto out;
1372 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1373 if (r)
1374 goto out;
1375 break;
1376 }
07716717
DK		 1377 case KVM_SET_CPUID2: {
1378 struct kvm_cpuid2 __user *cpuid_arg = argp;
1379 struct kvm_cpuid2 cpuid;
1380
1381 r = -EFAULT;
1382 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1383 goto out;
1384 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
1385 cpuid_arg->entries);
1386 if (r)
1387 goto out;
1388 break;
1389 }
1390 case KVM_GET_CPUID2: {
1391 struct kvm_cpuid2 __user *cpuid_arg = argp;
1392 struct kvm_cpuid2 cpuid;
1393
1394 r = -EFAULT;
1395 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1396 goto out;
1397 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
1398 cpuid_arg->entries);
1399 if (r)
1400 goto out;
1401 r = -EFAULT;
1402 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1403 goto out;
1404 r = 0;
1405 break;
1406 }
313a3dc7
CO		 1407 case KVM_GET_MSRS:
1408 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1409 break;
1410 case KVM_SET_MSRS:
1411 r = msr_io(vcpu, argp, do_set_msr, 0);
1412 break;
b209749f
AK		 1413 case KVM_TPR_ACCESS_REPORTING: {
1414 struct kvm_tpr_access_ctl tac;
1415
1416 r = -EFAULT;
1417 if (copy_from_user(&tac, argp, sizeof tac))
1418 goto out;
1419 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1420 if (r)
1421 goto out;
1422 r = -EFAULT;
1423 if (copy_to_user(argp, &tac, sizeof tac))
1424 goto out;
1425 r = 0;
1426 break;
1427 };
b93463aa
AK		 1428 case KVM_SET_VAPIC_ADDR: {
1429 struct kvm_vapic_addr va;
1430
1431 r = -EINVAL;
1432 if (!irqchip_in_kernel(vcpu->kvm))
1433 goto out;
1434 r = -EFAULT;
1435 if (copy_from_user(&va, argp, sizeof va))
1436 goto out;
1437 r = 0;
1438 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1439 break;
1440 }
313a3dc7
CO		 1441 default:
1442 r = -EINVAL;
1443 }
1444out:
1445 return r;
1446}
1447
1fe779f8
CO		 1448static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1449{
1450 int ret;
1451
1452 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1453 return -1;
1454 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1455 return ret;
1456}
1457
1458static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1459 u32 kvm_nr_mmu_pages)
1460{
1461 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1462 return -EINVAL;
1463
72dc67a6 1464 down_write(&kvm->slots_lock);
1fe779f8
CO		 1465
1466 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1467 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1468
72dc67a6 1469 up_write(&kvm->slots_lock);
1fe779f8
CO		 1470 return 0;
1471}
1472
1473static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1474{
f05e70ac 1475 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1476}
1477
e9f85cde
ZX		 1478gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1479{
1480 int i;
1481 struct kvm_mem_alias *alias;
1482
d69fb81f
ZX		 1483 for (i = 0; i < kvm->arch.naliases; ++i) {
1484 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1485 if (gfn >= alias->base_gfn
1486 && gfn < alias->base_gfn + alias->npages)
1487 return alias->target_gfn + gfn - alias->base_gfn;
1488 }
1489 return gfn;
1490}
1491
1fe779f8
CO		 1492/*
1493 * Set a new alias region. Aliases map a portion of physical memory into
1494 * another portion. This is useful for memory windows, for example the PC
1495 * VGA region.
1496 */
1497static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1498 struct kvm_memory_alias *alias)
1499{
1500 int r, n;
1501 struct kvm_mem_alias *p;
1502
1503 r = -EINVAL;
1504 /* General sanity checks */
1505 if (alias->memory_size & (PAGE_SIZE - 1))
1506 goto out;
1507 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1508 goto out;
1509 if (alias->slot >= KVM_ALIAS_SLOTS)
1510 goto out;
1511 if (alias->guest_phys_addr + alias->memory_size
1512 < alias->guest_phys_addr)
1513 goto out;
1514 if (alias->target_phys_addr + alias->memory_size
1515 < alias->target_phys_addr)
1516 goto out;
1517
72dc67a6 1518 down_write(&kvm->slots_lock);
a1708ce8 1519 spin_lock(&kvm->mmu_lock);
1fe779f8 1520
d69fb81f 1521 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 1522 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1523 p->npages = alias->memory_size >> PAGE_SHIFT;
1524 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1525
1526 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 1527 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 1528 break;
d69fb81f 1529 kvm->arch.naliases = n;
1fe779f8 1530
a1708ce8 1531 spin_unlock(&kvm->mmu_lock);
1fe779f8
CO		 1532 kvm_mmu_zap_all(kvm);
1533
72dc67a6 1534 up_write(&kvm->slots_lock);
1fe779f8
CO		 1535
1536 return 0;
1537
1538out:
1539 return r;
1540}
1541
1542static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1543{
1544 int r;
1545
1546 r = 0;
1547 switch (chip->chip_id) {
1548 case KVM_IRQCHIP_PIC_MASTER:
1549 memcpy(&chip->chip.pic,
1550 &pic_irqchip(kvm)->pics[0],
1551 sizeof(struct kvm_pic_state));
1552 break;
1553 case KVM_IRQCHIP_PIC_SLAVE:
1554 memcpy(&chip->chip.pic,
1555 &pic_irqchip(kvm)->pics[1],
1556 sizeof(struct kvm_pic_state));
1557 break;
1558 case KVM_IRQCHIP_IOAPIC:
1559 memcpy(&chip->chip.ioapic,
1560 ioapic_irqchip(kvm),
1561 sizeof(struct kvm_ioapic_state));
1562 break;
1563 default:
1564 r = -EINVAL;
1565 break;
1566 }
1567 return r;
1568}
1569
1570static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1571{
1572 int r;
1573
1574 r = 0;
1575 switch (chip->chip_id) {
1576 case KVM_IRQCHIP_PIC_MASTER:
1577 memcpy(&pic_irqchip(kvm)->pics[0],
1578 &chip->chip.pic,
1579 sizeof(struct kvm_pic_state));
1580 break;
1581 case KVM_IRQCHIP_PIC_SLAVE:
1582 memcpy(&pic_irqchip(kvm)->pics[1],
1583 &chip->chip.pic,
1584 sizeof(struct kvm_pic_state));
1585 break;
1586 case KVM_IRQCHIP_IOAPIC:
1587 memcpy(ioapic_irqchip(kvm),
1588 &chip->chip.ioapic,
1589 sizeof(struct kvm_ioapic_state));
1590 break;
1591 default:
1592 r = -EINVAL;
1593 break;
1594 }
1595 kvm_pic_update_irq(pic_irqchip(kvm));
1596 return r;
1597}
1598
e0f63cb9
SY		 1599static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1600{
1601 int r = 0;
1602
1603 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
1604 return r;
1605}
1606
1607static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1608{
1609 int r = 0;
1610
1611 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
1612 kvm_pit_load_count(kvm, 0, ps->channels[0].count);
1613 return r;
1614}
1615
5bb064dc
ZX		 1616/*
1617 * Get (and clear) the dirty memory log for a memory slot.
1618 */
1619int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
1620 struct kvm_dirty_log *log)
1621{
1622 int r;
1623 int n;
1624 struct kvm_memory_slot *memslot;
1625 int is_dirty = 0;
1626
72dc67a6 1627 down_write(&kvm->slots_lock);
5bb064dc
ZX		 1628
1629 r = kvm_get_dirty_log(kvm, log, &is_dirty);
1630 if (r)
1631 goto out;
1632
1633 /* If nothing is dirty, don't bother messing with page tables. */
1634 if (is_dirty) {
1635 kvm_mmu_slot_remove_write_access(kvm, log->slot);
1636 kvm_flush_remote_tlbs(kvm);
1637 memslot = &kvm->memslots[log->slot];
1638 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
1639 memset(memslot->dirty_bitmap, 0, n);
1640 }
1641 r = 0;
1642out:
72dc67a6 1643 up_write(&kvm->slots_lock);
5bb064dc
ZX		 1644 return r;
1645}
1646
1fe779f8
CO		 1647long kvm_arch_vm_ioctl(struct file *filp,
1648 unsigned int ioctl, unsigned long arg)
1649{
1650 struct kvm *kvm = filp->private_data;
1651 void __user *argp = (void __user *)arg;
1652 int r = -EINVAL;
1653
1654 switch (ioctl) {
1655 case KVM_SET_TSS_ADDR:
1656 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1657 if (r < 0)
1658 goto out;
1659 break;
1660 case KVM_SET_MEMORY_REGION: {
1661 struct kvm_memory_region kvm_mem;
1662 struct kvm_userspace_memory_region kvm_userspace_mem;
1663
1664 r = -EFAULT;
1665 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
1666 goto out;
1667 kvm_userspace_mem.slot = kvm_mem.slot;
1668 kvm_userspace_mem.flags = kvm_mem.flags;
1669 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
1670 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
1671 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
1672 if (r)
1673 goto out;
1674 break;
1675 }
1676 case KVM_SET_NR_MMU_PAGES:
1677 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1678 if (r)
1679 goto out;
1680 break;
1681 case KVM_GET_NR_MMU_PAGES:
1682 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
1683 break;
1684 case KVM_SET_MEMORY_ALIAS: {
1685 struct kvm_memory_alias alias;
1686
1687 r = -EFAULT;
1688 if (copy_from_user(&alias, argp, sizeof alias))
1689 goto out;
1690 r = kvm_vm_ioctl_set_memory_alias(kvm, &alias);
1691 if (r)
1692 goto out;
1693 break;
1694 }
1695 case KVM_CREATE_IRQCHIP:
1696 r = -ENOMEM;
d7deeeb0
ZX		 1697 kvm->arch.vpic = kvm_create_pic(kvm);
1698 if (kvm->arch.vpic) {
1fe779f8
CO		 1699 r = kvm_ioapic_init(kvm);
1700 if (r) {
d7deeeb0
ZX		 1701 kfree(kvm->arch.vpic);
1702 kvm->arch.vpic = NULL;
1fe779f8
CO		 1703 goto out;
1704 }
1705 } else
1706 goto out;
1707 break;
7837699f
SY		 1708 case KVM_CREATE_PIT:
1709 r = -ENOMEM;
1710 kvm->arch.vpit = kvm_create_pit(kvm);
1711 if (kvm->arch.vpit)
1712 r = 0;
1713 break;
1fe779f8
CO		 1714 case KVM_IRQ_LINE: {
1715 struct kvm_irq_level irq_event;
1716
1717 r = -EFAULT;
1718 if (copy_from_user(&irq_event, argp, sizeof irq_event))
1719 goto out;
1720 if (irqchip_in_kernel(kvm)) {
1721 mutex_lock(&kvm->lock);
1722 if (irq_event.irq < 16)
1723 kvm_pic_set_irq(pic_irqchip(kvm),
1724 irq_event.irq,
1725 irq_event.level);
d7deeeb0 1726 kvm_ioapic_set_irq(kvm->arch.vioapic,
1fe779f8
CO		 1727 irq_event.irq,
1728 irq_event.level);
1729 mutex_unlock(&kvm->lock);
1730 r = 0;
1731 }
1732 break;
1733 }
1734 case KVM_GET_IRQCHIP: {
1735 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
1736 struct kvm_irqchip chip;
1737
1738 r = -EFAULT;
1739 if (copy_from_user(&chip, argp, sizeof chip))
1740 goto out;
1741 r = -ENXIO;
1742 if (!irqchip_in_kernel(kvm))
1743 goto out;
1744 r = kvm_vm_ioctl_get_irqchip(kvm, &chip);
1745 if (r)
1746 goto out;
1747 r = -EFAULT;
1748 if (copy_to_user(argp, &chip, sizeof chip))
1749 goto out;
1750 r = 0;
1751 break;
1752 }
1753 case KVM_SET_IRQCHIP: {
1754 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
1755 struct kvm_irqchip chip;
1756
1757 r = -EFAULT;
1758 if (copy_from_user(&chip, argp, sizeof chip))
1759 goto out;
1760 r = -ENXIO;
1761 if (!irqchip_in_kernel(kvm))
1762 goto out;
1763 r = kvm_vm_ioctl_set_irqchip(kvm, &chip);
1764 if (r)
1765 goto out;
1766 r = 0;
1767 break;
1768 }
e0f63cb9
SY		 1769 case KVM_GET_PIT: {
1770 struct kvm_pit_state ps;
1771 r = -EFAULT;
1772 if (copy_from_user(&ps, argp, sizeof ps))
1773 goto out;
1774 r = -ENXIO;
1775 if (!kvm->arch.vpit)
1776 goto out;
1777 r = kvm_vm_ioctl_get_pit(kvm, &ps);
1778 if (r)
1779 goto out;
1780 r = -EFAULT;
1781 if (copy_to_user(argp, &ps, sizeof ps))
1782 goto out;
1783 r = 0;
1784 break;
1785 }
1786 case KVM_SET_PIT: {
1787 struct kvm_pit_state ps;
1788 r = -EFAULT;
1789 if (copy_from_user(&ps, argp, sizeof ps))
1790 goto out;
1791 r = -ENXIO;
1792 if (!kvm->arch.vpit)
1793 goto out;
1794 r = kvm_vm_ioctl_set_pit(kvm, &ps);
1795 if (r)
1796 goto out;
1797 r = 0;
1798 break;
1799 }
1fe779f8
CO		 1800 default:
1801 ;
1802 }
1803out:
1804 return r;
1805}
1806
a16b043c 1807static void kvm_init_msr_list(void)
043405e1
CO		 1808{
1809 u32 dummy[2];
1810 unsigned i, j;
1811
1812 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
1813 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
1814 continue;
1815 if (j < i)
1816 msrs_to_save[j] = msrs_to_save[i];
1817 j++;
1818 }
1819 num_msrs_to_save = j;
1820}
1821
bbd9b64e
CO		 1822/*
1823 * Only apic need an MMIO device hook, so shortcut now..
1824 */
1825static struct kvm_io_device *vcpu_find_pervcpu_dev(struct kvm_vcpu *vcpu,
92760499
LV		 1826 gpa_t addr, int len,
1827 int is_write)
bbd9b64e
CO		 1828{
1829 struct kvm_io_device *dev;
1830
ad312c7c
ZX		 1831 if (vcpu->arch.apic) {
1832 dev = &vcpu->arch.apic->dev;
92760499 1833 if (dev->in_range(dev, addr, len, is_write))
bbd9b64e
CO		 1834 return dev;
1835 }
1836 return NULL;
1837}
1838
1839
1840static struct kvm_io_device *vcpu_find_mmio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 1841 gpa_t addr, int len,
1842 int is_write)
bbd9b64e
CO		 1843{
1844 struct kvm_io_device *dev;
1845
92760499 1846 dev = vcpu_find_pervcpu_dev(vcpu, addr, len, is_write);
bbd9b64e 1847 if (dev == NULL)
92760499
LV		 1848 dev = kvm_io_bus_find_dev(&vcpu->kvm->mmio_bus, addr, len,
1849 is_write);
bbd9b64e
CO		 1850 return dev;
1851}
1852
1853int emulator_read_std(unsigned long addr,
1854 void *val,
1855 unsigned int bytes,
1856 struct kvm_vcpu *vcpu)
1857{
1858 void *data = val;
10589a46 1859 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 1860
1861 while (bytes) {
ad312c7c 1862 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 1863 unsigned offset = addr & (PAGE_SIZE-1);
1864 unsigned tocopy = min(bytes, (unsigned)PAGE_SIZE - offset);
1865 int ret;
1866
10589a46
MT		 1867 if (gpa == UNMAPPED_GVA) {
1868 r = X86EMUL_PROPAGATE_FAULT;
1869 goto out;
1870 }
bbd9b64e 1871 ret = kvm_read_guest(vcpu->kvm, gpa, data, tocopy);
10589a46
MT		 1872 if (ret < 0) {
1873 r = X86EMUL_UNHANDLEABLE;
1874 goto out;
1875 }
bbd9b64e
CO		 1876
1877 bytes -= tocopy;
1878 data += tocopy;
1879 addr += tocopy;
1880 }
10589a46 1881out:
10589a46 1882 return r;
bbd9b64e
CO		 1883}
1884EXPORT_SYMBOL_GPL(emulator_read_std);
1885
bbd9b64e
CO		 1886static int emulator_read_emulated(unsigned long addr,
1887 void *val,
1888 unsigned int bytes,
1889 struct kvm_vcpu *vcpu)
1890{
1891 struct kvm_io_device *mmio_dev;
1892 gpa_t gpa;
1893
1894 if (vcpu->mmio_read_completed) {
1895 memcpy(val, vcpu->mmio_data, bytes);
1896 vcpu->mmio_read_completed = 0;
1897 return X86EMUL_CONTINUE;
1898 }
1899
ad312c7c 1900 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 1901
1902 /* For APIC access vmexit */
1903 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
1904 goto mmio;
1905
1906 if (emulator_read_std(addr, val, bytes, vcpu)
1907 == X86EMUL_CONTINUE)
1908 return X86EMUL_CONTINUE;
1909 if (gpa == UNMAPPED_GVA)
1910 return X86EMUL_PROPAGATE_FAULT;
1911
1912mmio:
1913 /*
1914 * Is this MMIO handled locally?
1915 */
10589a46 1916 mutex_lock(&vcpu->kvm->lock);
92760499 1917 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 0);
bbd9b64e
CO		 1918 if (mmio_dev) {
1919 kvm_iodevice_read(mmio_dev, gpa, bytes, val);
10589a46 1920 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 1921 return X86EMUL_CONTINUE;
1922 }
10589a46 1923 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 1924
1925 vcpu->mmio_needed = 1;
1926 vcpu->mmio_phys_addr = gpa;
1927 vcpu->mmio_size = bytes;
1928 vcpu->mmio_is_write = 0;
1929
1930 return X86EMUL_UNHANDLEABLE;
1931}
1932
3200f405 1933int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 1934 const void *val, int bytes)
bbd9b64e
CO		 1935{
1936 int ret;
1937
1938 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 1939 if (ret < 0)
bbd9b64e
CO		 1940 return 0;
1941 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
1942 return 1;
1943}
1944
1945static int emulator_write_emulated_onepage(unsigned long addr,
1946 const void *val,
1947 unsigned int bytes,
1948 struct kvm_vcpu *vcpu)
1949{
1950 struct kvm_io_device *mmio_dev;
10589a46
MT		 1951 gpa_t gpa;
1952
10589a46 1953 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 1954
1955 if (gpa == UNMAPPED_GVA) {
c3c91fee 1956 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 1957 return X86EMUL_PROPAGATE_FAULT;
1958 }
1959
1960 /* For APIC access vmexit */
1961 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
1962 goto mmio;
1963
1964 if (emulator_write_phys(vcpu, gpa, val, bytes))
1965 return X86EMUL_CONTINUE;
1966
1967mmio:
1968 /*
1969 * Is this MMIO handled locally?
1970 */
10589a46 1971 mutex_lock(&vcpu->kvm->lock);
92760499 1972 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 1);
bbd9b64e
CO		 1973 if (mmio_dev) {
1974 kvm_iodevice_write(mmio_dev, gpa, bytes, val);
10589a46 1975 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 1976 return X86EMUL_CONTINUE;
1977 }
10589a46 1978 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 1979
1980 vcpu->mmio_needed = 1;
1981 vcpu->mmio_phys_addr = gpa;
1982 vcpu->mmio_size = bytes;
1983 vcpu->mmio_is_write = 1;
1984 memcpy(vcpu->mmio_data, val, bytes);
1985
1986 return X86EMUL_CONTINUE;
1987}
1988
1989int emulator_write_emulated(unsigned long addr,
1990 const void *val,
1991 unsigned int bytes,
1992 struct kvm_vcpu *vcpu)
1993{
1994 /* Crossing a page boundary? */
1995 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
1996 int rc, now;
1997
1998 now = -addr & ~PAGE_MASK;
1999 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2000 if (rc != X86EMUL_CONTINUE)
2001 return rc;
2002 addr += now;
2003 val += now;
2004 bytes -= now;
2005 }
2006 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2007}
2008EXPORT_SYMBOL_GPL(emulator_write_emulated);
2009
2010static int emulator_cmpxchg_emulated(unsigned long addr,
2011 const void *old,
2012 const void *new,
2013 unsigned int bytes,
2014 struct kvm_vcpu *vcpu)
2015{
2016 static int reported;
2017
2018 if (!reported) {
2019 reported = 1;
2020 printk(KERN_WARNING "kvm: emulating exchange as write\n");
2021 }
2bacc55c
MT		 2022#ifndef CONFIG_X86_64
2023 /* guests cmpxchg8b have to be emulated atomically */
2024 if (bytes == 8) {
10589a46 2025 gpa_t gpa;
2bacc55c 2026 struct page *page;
c0b49b0d 2027 char *kaddr;
2bacc55c
MT		 2028 u64 val;
2029
10589a46
MT		 2030 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2031
2bacc55c
MT		 2032 if (gpa == UNMAPPED_GVA ||
2033 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2034 goto emul_write;
2035
2036 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2037 goto emul_write;
2038
2039 val = *(u64 *)new;
72dc67a6
IE		 2040
2041 down_read(&current->mm->mmap_sem);
2bacc55c 2042 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6
IE		 2043 up_read(&current->mm->mmap_sem);
2044
c0b49b0d
AM		 2045 kaddr = kmap_atomic(page, KM_USER0);
2046 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2047 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 2048 kvm_release_page_dirty(page);
2049 }
3200f405 2050emul_write:
2bacc55c
MT		 2051#endif
2052
bbd9b64e
CO		 2053 return emulator_write_emulated(addr, new, bytes, vcpu);
2054}
2055
2056static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2057{
2058 return kvm_x86_ops->get_segment_base(vcpu, seg);
2059}
2060
2061int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2062{
2063 return X86EMUL_CONTINUE;
2064}
2065
2066int emulate_clts(struct kvm_vcpu *vcpu)
2067{
54e445ca 2068 KVMTRACE_0D(CLTS, vcpu, handler);
ad312c7c 2069 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 2070 return X86EMUL_CONTINUE;
2071}
2072
2073int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2074{
2075 struct kvm_vcpu *vcpu = ctxt->vcpu;
2076
2077 switch (dr) {
2078 case 0 ... 3:
2079 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2080 return X86EMUL_CONTINUE;
2081 default:
b8688d51 2082 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2083 return X86EMUL_UNHANDLEABLE;
2084 }
2085}
2086
2087int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2088{
2089 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2090 int exception;
2091
2092 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2093 if (exception) {
2094 /* FIXME: better handling */
2095 return X86EMUL_UNHANDLEABLE;
2096 }
2097 return X86EMUL_CONTINUE;
2098}
2099
2100void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2101{
bbd9b64e 2102 u8 opcodes[4];
5fdbf976 2103 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 2104 unsigned long rip_linear;
2105
f76c710d 2106 if (!printk_ratelimit())
bbd9b64e
CO		 2107 return;
2108
25be4608
GC		 2109 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2110
bbd9b64e
CO		 2111 emulator_read_std(rip_linear, (void *)opcodes, 4, vcpu);
2112
2113 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2114 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 2115}
2116EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2117
14af3f3c 2118static struct x86_emulate_ops emulate_ops = {
bbd9b64e 2119 .read_std = emulator_read_std,
bbd9b64e
CO		 2120 .read_emulated = emulator_read_emulated,
2121 .write_emulated = emulator_write_emulated,
2122 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2123};
2124
5fdbf976
MT		 2125static void cache_all_regs(struct kvm_vcpu *vcpu)
2126{
2127 kvm_register_read(vcpu, VCPU_REGS_RAX);
2128 kvm_register_read(vcpu, VCPU_REGS_RSP);
2129 kvm_register_read(vcpu, VCPU_REGS_RIP);
2130 vcpu->arch.regs_dirty = ~0;
2131}
2132
bbd9b64e
CO		 2133int emulate_instruction(struct kvm_vcpu *vcpu,
2134 struct kvm_run *run,
2135 unsigned long cr2,
2136 u16 error_code,
571008da 2137 int emulation_type)
bbd9b64e
CO		 2138{
2139 int r;
571008da 2140 struct decode_cache *c;
bbd9b64e 2141
26eef70c 2142 kvm_clear_exception_queue(vcpu);
ad312c7c 2143 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976
MT		 2144 /*
2145 * TODO: fix x86_emulate.c to use guest_read/write_register
2146 * instead of direct ->regs accesses, can save hundred cycles
2147 * on Intel for instructions that don't read/change RSP, for
2148 * for example.
2149 */
2150 cache_all_regs(vcpu);
bbd9b64e
CO		 2151
2152 vcpu->mmio_is_write = 0;
ad312c7c 2153 vcpu->arch.pio.string = 0;
bbd9b64e 2154
571008da 2155 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2156 int cs_db, cs_l;
2157 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2158
ad312c7c
ZX		 2159 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2160 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2161 vcpu->arch.emulate_ctxt.mode =
2162 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2163 ? X86EMUL_MODE_REAL : cs_l
2164 ? X86EMUL_MODE_PROT64 : cs_db
2165 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2166
ad312c7c 2167 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da
SY		 2168
2169 /* Reject the instructions other than VMCALL/VMMCALL when
2170 * try to emulate invalid opcode */
2171 c = &vcpu->arch.emulate_ctxt.decode;
2172 if ((emulation_type & EMULTYPE_TRAP_UD) &&
2173 (!(c->twobyte && c->b == 0x01 &&
2174 (c->modrm_reg == 0 || c->modrm_reg == 3) &&
2175 c->modrm_mod == 3 && c->modrm_rm == 1)))
2176 return EMULATE_FAIL;
2177
f2b5756b 2178 ++vcpu->stat.insn_emulation;
bbd9b64e 2179 if (r) {
f2b5756b 2180 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2181 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2182 return EMULATE_DONE;
2183 return EMULATE_FAIL;
2184 }
2185 }
2186
ad312c7c 2187 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
bbd9b64e 2188
ad312c7c 2189 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2190 return EMULATE_DO_MMIO;
2191
2192 if ((r || vcpu->mmio_is_write) && run) {
2193 run->exit_reason = KVM_EXIT_MMIO;
2194 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2195 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2196 run->mmio.len = vcpu->mmio_size;
2197 run->mmio.is_write = vcpu->mmio_is_write;
2198 }
2199
2200 if (r) {
2201 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2202 return EMULATE_DONE;
2203 if (!vcpu->mmio_needed) {
2204 kvm_report_emulation_failure(vcpu, "mmio");
2205 return EMULATE_FAIL;
2206 }
2207 return EMULATE_DO_MMIO;
2208 }
2209
ad312c7c 2210 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2211
2212 if (vcpu->mmio_is_write) {
2213 vcpu->mmio_needed = 0;
2214 return EMULATE_DO_MMIO;
2215 }
2216
2217 return EMULATE_DONE;
2218}
2219EXPORT_SYMBOL_GPL(emulate_instruction);
2220
de7d789a
CO		 2221static void free_pio_guest_pages(struct kvm_vcpu *vcpu)
2222{
2223 int i;
2224
ad312c7c
ZX		 2225 for (i = 0; i < ARRAY_SIZE(vcpu->arch.pio.guest_pages); ++i)
2226 if (vcpu->arch.pio.guest_pages[i]) {
2227 kvm_release_page_dirty(vcpu->arch.pio.guest_pages[i]);
2228 vcpu->arch.pio.guest_pages[i] = NULL;
de7d789a
CO		 2229 }
2230}
2231
2232static int pio_copy_data(struct kvm_vcpu *vcpu)
2233{
ad312c7c 2234 void *p = vcpu->arch.pio_data;
de7d789a
CO		 2235 void *q;
2236 unsigned bytes;
ad312c7c 2237 int nr_pages = vcpu->arch.pio.guest_pages[1] ? 2 : 1;
de7d789a 2238
ad312c7c 2239 q = vmap(vcpu->arch.pio.guest_pages, nr_pages, VM_READ|VM_WRITE,
de7d789a
CO		 2240 PAGE_KERNEL);
2241 if (!q) {
2242 free_pio_guest_pages(vcpu);
2243 return -ENOMEM;
2244 }
ad312c7c
ZX		 2245 q += vcpu->arch.pio.guest_page_offset;
2246 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2247 if (vcpu->arch.pio.in)
de7d789a
CO		 2248 memcpy(q, p, bytes);
2249 else
2250 memcpy(p, q, bytes);
ad312c7c 2251 q -= vcpu->arch.pio.guest_page_offset;
de7d789a
CO		 2252 vunmap(q);
2253 free_pio_guest_pages(vcpu);
2254 return 0;
2255}
2256
2257int complete_pio(struct kvm_vcpu *vcpu)
2258{
ad312c7c 2259 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2260 long delta;
2261 int r;
5fdbf976 2262 unsigned long val;
de7d789a
CO		 2263
2264 if (!io->string) {
5fdbf976
MT		 2265 if (io->in) {
2266 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2267 memcpy(&val, vcpu->arch.pio_data, io->size);
2268 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2269 }
de7d789a
CO		 2270 } else {
2271 if (io->in) {
2272 r = pio_copy_data(vcpu);
5fdbf976 2273 if (r)
de7d789a 2274 return r;
de7d789a
CO		 2275 }
2276
2277 delta = 1;
2278 if (io->rep) {
2279 delta *= io->cur_count;
2280 /*
2281 * The size of the register should really depend on
2282 * current address size.
2283 */
5fdbf976
MT		 2284 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2285 val -= delta;
2286 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 2287 }
2288 if (io->down)
2289 delta = -delta;
2290 delta *= io->size;
5fdbf976
MT		 2291 if (io->in) {
2292 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2293 val += delta;
2294 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2295 } else {
2296 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2297 val += delta;
2298 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2299 }
de7d789a
CO		 2300 }
2301
de7d789a
CO		 2302 io->count -= io->cur_count;
2303 io->cur_count = 0;
2304
2305 return 0;
2306}
2307
2308static void kernel_pio(struct kvm_io_device *pio_dev,
2309 struct kvm_vcpu *vcpu,
2310 void *pd)
2311{
2312 /* TODO: String I/O for in kernel device */
2313
2314 mutex_lock(&vcpu->kvm->lock);
ad312c7c
ZX		 2315 if (vcpu->arch.pio.in)
2316 kvm_iodevice_read(pio_dev, vcpu->arch.pio.port,
2317 vcpu->arch.pio.size,
de7d789a
CO		 2318 pd);
2319 else
ad312c7c
ZX		 2320 kvm_iodevice_write(pio_dev, vcpu->arch.pio.port,
2321 vcpu->arch.pio.size,
de7d789a
CO		 2322 pd);
2323 mutex_unlock(&vcpu->kvm->lock);
2324}
2325
2326static void pio_string_write(struct kvm_io_device *pio_dev,
2327 struct kvm_vcpu *vcpu)
2328{
ad312c7c
ZX		 2329 struct kvm_pio_request *io = &vcpu->arch.pio;
2330 void *pd = vcpu->arch.pio_data;
de7d789a
CO		 2331 int i;
2332
2333 mutex_lock(&vcpu->kvm->lock);
2334 for (i = 0; i < io->cur_count; i++) {
2335 kvm_iodevice_write(pio_dev, io->port,
2336 io->size,
2337 pd);
2338 pd += io->size;
2339 }
2340 mutex_unlock(&vcpu->kvm->lock);
2341}
2342
2343static struct kvm_io_device *vcpu_find_pio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2344 gpa_t addr, int len,
2345 int is_write)
de7d789a 2346{
92760499 2347 return kvm_io_bus_find_dev(&vcpu->kvm->pio_bus, addr, len, is_write);
de7d789a
CO		 2348}
2349
2350int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2351 int size, unsigned port)
2352{
2353 struct kvm_io_device *pio_dev;
5fdbf976 2354 unsigned long val;
de7d789a
CO		 2355
2356 vcpu->run->exit_reason = KVM_EXIT_IO;
2357 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2358 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2359 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2360 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2361 vcpu->run->io.port = vcpu->arch.pio.port = port;
2362 vcpu->arch.pio.in = in;
2363 vcpu->arch.pio.string = 0;
2364 vcpu->arch.pio.down = 0;
2365 vcpu->arch.pio.guest_page_offset = 0;
2366 vcpu->arch.pio.rep = 0;
de7d789a 2367
2714d1d3
FEL		 2368 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2369 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2370 handler);
2371 else
2372 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2373 handler);
2374
5fdbf976
MT		 2375 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2376 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a
CO		 2377
2378 kvm_x86_ops->skip_emulated_instruction(vcpu);
2379
92760499 2380 pio_dev = vcpu_find_pio_dev(vcpu, port, size, !in);
de7d789a 2381 if (pio_dev) {
ad312c7c 2382 kernel_pio(pio_dev, vcpu, vcpu->arch.pio_data);
de7d789a
CO		 2383 complete_pio(vcpu);
2384 return 1;
2385 }
2386 return 0;
2387}
2388EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2389
2390int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2391 int size, unsigned long count, int down,
2392 gva_t address, int rep, unsigned port)
2393{
2394 unsigned now, in_page;
2395 int i, ret = 0;
2396 int nr_pages = 1;
2397 struct page *page;
2398 struct kvm_io_device *pio_dev;
2399
2400 vcpu->run->exit_reason = KVM_EXIT_IO;
2401 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2402 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2403 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2404 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2405 vcpu->run->io.port = vcpu->arch.pio.port = port;
2406 vcpu->arch.pio.in = in;
2407 vcpu->arch.pio.string = 1;
2408 vcpu->arch.pio.down = down;
2409 vcpu->arch.pio.guest_page_offset = offset_in_page(address);
2410 vcpu->arch.pio.rep = rep;
de7d789a 2411
2714d1d3
FEL		 2412 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2413 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2414 handler);
2415 else
2416 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2417 handler);
2418
de7d789a
CO		 2419 if (!count) {
2420 kvm_x86_ops->skip_emulated_instruction(vcpu);
2421 return 1;
2422 }
2423
2424 if (!down)
2425 in_page = PAGE_SIZE - offset_in_page(address);
2426 else
2427 in_page = offset_in_page(address) + size;
2428 now = min(count, (unsigned long)in_page / size);
2429 if (!now) {
2430 /*
2431 * String I/O straddles page boundary. Pin two guest pages
2432 * so that we satisfy atomicity constraints. Do just one
2433 * transaction to avoid complexity.
2434 */
2435 nr_pages = 2;
2436 now = 1;
2437 }
2438 if (down) {
2439 /*
2440 * String I/O in reverse. Yuck. Kill the guest, fix later.
2441 */
2442 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 2443 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2444 return 1;
2445 }
2446 vcpu->run->io.count = now;
ad312c7c 2447 vcpu->arch.pio.cur_count = now;
de7d789a 2448
ad312c7c 2449 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 2450 kvm_x86_ops->skip_emulated_instruction(vcpu);
2451
2452 for (i = 0; i < nr_pages; ++i) {
de7d789a 2453 page = gva_to_page(vcpu, address + i * PAGE_SIZE);
ad312c7c 2454 vcpu->arch.pio.guest_pages[i] = page;
de7d789a 2455 if (!page) {
c1a5d4f9 2456 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2457 free_pio_guest_pages(vcpu);
2458 return 1;
2459 }
2460 }
2461
92760499
LV		 2462 pio_dev = vcpu_find_pio_dev(vcpu, port,
2463 vcpu->arch.pio.cur_count,
2464 !vcpu->arch.pio.in);
ad312c7c 2465 if (!vcpu->arch.pio.in) {
de7d789a
CO		 2466 /* string PIO write */
2467 ret = pio_copy_data(vcpu);
2468 if (ret >= 0 && pio_dev) {
2469 pio_string_write(pio_dev, vcpu);
2470 complete_pio(vcpu);
ad312c7c 2471 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 2472 ret = 1;
2473 }
2474 } else if (pio_dev)
2475 pr_unimpl(vcpu, "no string pio read support yet, "
2476 "port %x size %d count %ld\n",
2477 port, size, count);
2478
2479 return ret;
2480}
2481EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
2482
f8c16bba 2483int kvm_arch_init(void *opaque)
043405e1 2484{
56c6d28a 2485 int r;
f8c16bba
ZX		 2486 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
2487
f8c16bba
ZX		 2488 if (kvm_x86_ops) {
2489 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 2490 r = -EEXIST;
2491 goto out;
f8c16bba
ZX		 2492 }
2493
2494 if (!ops->cpu_has_kvm_support()) {
2495 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 2496 r = -EOPNOTSUPP;
2497 goto out;
f8c16bba
ZX		 2498 }
2499 if (ops->disabled_by_bios()) {
2500 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 2501 r = -EOPNOTSUPP;
2502 goto out;
f8c16bba
ZX		 2503 }
2504
97db56ce
AK		 2505 r = kvm_mmu_module_init();
2506 if (r)
2507 goto out;
2508
2509 kvm_init_msr_list();
2510
f8c16bba 2511 kvm_x86_ops = ops;
56c6d28a 2512 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 2513 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
2514 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
2515 PT_DIRTY_MASK, PT64_NX_MASK, 0);
f8c16bba 2516 return 0;
56c6d28a
ZX		 2517
2518out:
56c6d28a 2519 return r;
043405e1 2520}
8776e519 2521
f8c16bba
ZX		 2522void kvm_arch_exit(void)
2523{
2524 kvm_x86_ops = NULL;
56c6d28a
ZX		 2525 kvm_mmu_module_exit();
2526}
f8c16bba 2527
8776e519
HB		 2528int kvm_emulate_halt(struct kvm_vcpu *vcpu)
2529{
2530 ++vcpu->stat.halt_exits;
2714d1d3 2531 KVMTRACE_0D(HLT, vcpu, handler);
8776e519 2532 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 2533 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
3200f405 2534 up_read(&vcpu->kvm->slots_lock);
8776e519 2535 kvm_vcpu_block(vcpu);
3200f405 2536 down_read(&vcpu->kvm->slots_lock);
a4535290 2537 if (vcpu->arch.mp_state != KVM_MP_STATE_RUNNABLE)
8776e519
HB		 2538 return -EINTR;
2539 return 1;
2540 } else {
2541 vcpu->run->exit_reason = KVM_EXIT_HLT;
2542 return 0;
2543 }
2544}
2545EXPORT_SYMBOL_GPL(kvm_emulate_halt);
2546
2f333bcb
MT		 2547static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
2548 unsigned long a1)
2549{
2550 if (is_long_mode(vcpu))
2551 return a0;
2552 else
2553 return a0 | ((gpa_t)a1 << 32);
2554}
2555
8776e519
HB		 2556int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
2557{
2558 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 2559 int r = 1;
8776e519 2560
5fdbf976
MT		 2561 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
2562 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
2563 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
2564 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
2565 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 2566
2714d1d3
FEL		 2567 KVMTRACE_1D(VMMCALL, vcpu, (u32)nr, handler);
2568
8776e519
HB		 2569 if (!is_long_mode(vcpu)) {
2570 nr &= 0xFFFFFFFF;
2571 a0 &= 0xFFFFFFFF;
2572 a1 &= 0xFFFFFFFF;
2573 a2 &= 0xFFFFFFFF;
2574 a3 &= 0xFFFFFFFF;
2575 }
2576
2577 switch (nr) {
b93463aa
AK		 2578 case KVM_HC_VAPIC_POLL_IRQ:
2579 ret = 0;
2580 break;
2f333bcb
MT		 2581 case KVM_HC_MMU_OP:
2582 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
2583 break;
8776e519
HB		 2584 default:
2585 ret = -KVM_ENOSYS;
2586 break;
2587 }
5fdbf976 2588 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 2589 ++vcpu->stat.hypercalls;
2f333bcb 2590 return r;
8776e519
HB		 2591}
2592EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
2593
2594int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
2595{
2596 char instruction[3];
2597 int ret = 0;
5fdbf976 2598 unsigned long rip = kvm_rip_read(vcpu);
8776e519 2599
8776e519
HB		 2600
2601 /*
2602 * Blow out the MMU to ensure that no other VCPU has an active mapping
2603 * to ensure that the updated hypercall appears atomically across all
2604 * VCPUs.
2605 */
2606 kvm_mmu_zap_all(vcpu->kvm);
2607
8776e519 2608 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 2609 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 2610 != X86EMUL_CONTINUE)
2611 ret = -EFAULT;
2612
8776e519
HB		 2613 return ret;
2614}
2615
2616static u64 mk_cr_64(u64 curr_cr, u32 new_val)
2617{
2618 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
2619}
2620
2621void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2622{
2623 struct descriptor_table dt = { limit, base };
2624
2625 kvm_x86_ops->set_gdt(vcpu, &dt);
2626}
2627
2628void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2629{
2630 struct descriptor_table dt = { limit, base };
2631
2632 kvm_x86_ops->set_idt(vcpu, &dt);
2633}
2634
2635void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
2636 unsigned long *rflags)
2637{
2d3ad1f4 2638 kvm_lmsw(vcpu, msw);
8776e519
HB		 2639 *rflags = kvm_x86_ops->get_rflags(vcpu);
2640}
2641
2642unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
2643{
54e445ca
JR		 2644 unsigned long value;
2645
8776e519
HB		 2646 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
2647 switch (cr) {
2648 case 0:
54e445ca
JR		 2649 value = vcpu->arch.cr0;
2650 break;
8776e519 2651 case 2:
54e445ca
JR		 2652 value = vcpu->arch.cr2;
2653 break;
8776e519 2654 case 3:
54e445ca
JR		 2655 value = vcpu->arch.cr3;
2656 break;
8776e519 2657 case 4:
54e445ca
JR		 2658 value = vcpu->arch.cr4;
2659 break;
152ff9be 2660 case 8:
54e445ca
JR		 2661 value = kvm_get_cr8(vcpu);
2662 break;
8776e519 2663 default:
b8688d51 2664 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2665 return 0;
2666 }
54e445ca
JR		 2667 KVMTRACE_3D(CR_READ, vcpu, (u32)cr, (u32)value,
2668 (u32)((u64)value >> 32), handler);
2669
2670 return value;
8776e519
HB		 2671}
2672
2673void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
2674 unsigned long *rflags)
2675{
54e445ca
JR		 2676 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)val,
2677 (u32)((u64)val >> 32), handler);
2678
8776e519
HB		 2679 switch (cr) {
2680 case 0:
2d3ad1f4 2681 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 2682 *rflags = kvm_x86_ops->get_rflags(vcpu);
2683 break;
2684 case 2:
ad312c7c 2685 vcpu->arch.cr2 = val;
8776e519
HB		 2686 break;
2687 case 3:
2d3ad1f4 2688 kvm_set_cr3(vcpu, val);
8776e519
HB		 2689 break;
2690 case 4:
2d3ad1f4 2691 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 2692 break;
152ff9be 2693 case 8:
2d3ad1f4 2694 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 2695 break;
8776e519 2696 default:
b8688d51 2697 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2698 }
2699}
2700
07716717
DK		 2701static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
2702{
ad312c7c
ZX		 2703 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
2704 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 2705
2706 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
2707 /* when no next entry is found, the current entry[i] is reselected */
2708 for (j = i + 1; j == i; j = (j + 1) % nent) {
ad312c7c 2709 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 2710 if (ej->function == e->function) {
2711 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
2712 return j;
2713 }
2714 }
2715 return 0; /* silence gcc, even though control never reaches here */
2716}
2717
2718/* find an entry with matching function, matching index (if needed), and that
2719 * should be read next (if it's stateful) */
2720static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
2721 u32 function, u32 index)
2722{
2723 if (e->function != function)
2724 return 0;
2725 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
2726 return 0;
2727 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
2728 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
2729 return 0;
2730 return 1;
2731}
2732
8776e519
HB		 2733void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
2734{
2735 int i;
07716717
DK		 2736 u32 function, index;
2737 struct kvm_cpuid_entry2 *e, *best;
8776e519 2738
5fdbf976
MT		 2739 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
2740 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
2741 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
2742 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
2743 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
2744 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
8776e519 2745 best = NULL;
ad312c7c
ZX		 2746 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2747 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 2748 if (is_matching_cpuid_entry(e, function, index)) {
2749 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
2750 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 2751 best = e;
2752 break;
2753 }
2754 /*
2755 * Both basic or both extended?
2756 */
2757 if (((e->function ^ function) & 0x80000000) == 0)
2758 if (!best || e->function > best->function)
2759 best = e;
2760 }
2761 if (best) {
5fdbf976
MT		 2762 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
2763 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
2764 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
2765 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 2766 }
8776e519 2767 kvm_x86_ops->skip_emulated_instruction(vcpu);
2714d1d3 2768 KVMTRACE_5D(CPUID, vcpu, function,
5fdbf976
MT		 2769 (u32)kvm_register_read(vcpu, VCPU_REGS_RAX),
2770 (u32)kvm_register_read(vcpu, VCPU_REGS_RBX),
2771 (u32)kvm_register_read(vcpu, VCPU_REGS_RCX),
2772 (u32)kvm_register_read(vcpu, VCPU_REGS_RDX), handler);
8776e519
HB		 2773}
2774EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 2775
b6c7a5dc
HB		 2776/*
2777 * Check if userspace requested an interrupt window, and that the
2778 * interrupt window is open.
2779 *
2780 * No need to exit to userspace if we already have an interrupt queued.
2781 */
2782static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
2783 struct kvm_run *kvm_run)
2784{
ad312c7c 2785 return (!vcpu->arch.irq_summary &&
b6c7a5dc 2786 kvm_run->request_interrupt_window &&
ad312c7c 2787 vcpu->arch.interrupt_window_open &&
b6c7a5dc
HB		 2788 (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF));
2789}
2790
2791static void post_kvm_run_save(struct kvm_vcpu *vcpu,
2792 struct kvm_run *kvm_run)
2793{
2794 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 2795 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc
HB		 2796 kvm_run->apic_base = kvm_get_apic_base(vcpu);
2797 if (irqchip_in_kernel(vcpu->kvm))
2798 kvm_run->ready_for_interrupt_injection = 1;
2799 else
2800 kvm_run->ready_for_interrupt_injection =
ad312c7c
ZX		 2801 (vcpu->arch.interrupt_window_open &&
2802 vcpu->arch.irq_summary == 0);
b6c7a5dc
HB		 2803}
2804
b93463aa
AK		 2805static void vapic_enter(struct kvm_vcpu *vcpu)
2806{
2807 struct kvm_lapic *apic = vcpu->arch.apic;
2808 struct page *page;
2809
2810 if (!apic || !apic->vapic_addr)
2811 return;
2812
10589a46 2813 down_read(&current->mm->mmap_sem);
b93463aa 2814 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
10589a46 2815 up_read(&current->mm->mmap_sem);
72dc67a6
IE		 2816
2817 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 2818}
2819
2820static void vapic_exit(struct kvm_vcpu *vcpu)
2821{
2822 struct kvm_lapic *apic = vcpu->arch.apic;
2823
2824 if (!apic || !apic->vapic_addr)
2825 return;
2826
f8b78fa3 2827 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 2828 kvm_release_page_dirty(apic->vapic_page);
2829 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 2830 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 2831}
2832
b6c7a5dc
HB		 2833static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2834{
2835 int r;
2836
a4535290 2837 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
b6c7a5dc 2838 pr_debug("vcpu %d received sipi with vector # %x\n",
ad312c7c 2839 vcpu->vcpu_id, vcpu->arch.sipi_vector);
b6c7a5dc
HB		 2840 kvm_lapic_reset(vcpu);
2841 r = kvm_x86_ops->vcpu_reset(vcpu);
2842 if (r)
2843 return r;
a4535290 2844 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 2845 }
2846
3200f405 2847 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 2848 vapic_enter(vcpu);
2849
b6c7a5dc
HB		 2850preempted:
2851 if (vcpu->guest_debug.enabled)
2852 kvm_x86_ops->guest_debug_pre(vcpu);
2853
2854again:
2e53d63a
MT		 2855 if (vcpu->requests)
2856 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
2857 kvm_mmu_unload(vcpu);
2858
b6c7a5dc
HB		 2859 r = kvm_mmu_reload(vcpu);
2860 if (unlikely(r))
2861 goto out;
2862
2f52d58c
AK		 2863 if (vcpu->requests) {
2864 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 2865 __kvm_migrate_timers(vcpu);
d4acf7e7
MT		 2866 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
2867 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 2868 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
2869 &vcpu->requests)) {
2870 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
2871 r = 0;
2872 goto out;
2873 }
71c4dfaf
JR		 2874 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
2875 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2876 r = 0;
2877 goto out;
2878 }
2f52d58c 2879 }
b93463aa 2880
06e05645 2881 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
b6c7a5dc
HB		 2882 kvm_inject_pending_timer_irqs(vcpu);
2883
2884 preempt_disable();
2885
2886 kvm_x86_ops->prepare_guest_switch(vcpu);
2887 kvm_load_guest_fpu(vcpu);
2888
2889 local_irq_disable();
2890
d4acf7e7 2891 if (vcpu->requests || need_resched()) {
6c142801
AK		 2892 local_irq_enable();
2893 preempt_enable();
2894 r = 1;
2895 goto out;
2896 }
2897
b6c7a5dc
HB		 2898 if (signal_pending(current)) {
2899 local_irq_enable();
2900 preempt_enable();
2901 r = -EINTR;
2902 kvm_run->exit_reason = KVM_EXIT_INTR;
2903 ++vcpu->stat.signal_exits;
2904 goto out;
2905 }
2906
e9571ed5
MT		 2907 vcpu->guest_mode = 1;
2908 /*
2909 * Make sure that guest_mode assignment won't happen after
2910 * testing the pending IRQ vector bitmap.
2911 */
2912 smp_wmb();
2913
ad312c7c 2914 if (vcpu->arch.exception.pending)
298101da
AK		 2915 __queue_exception(vcpu);
2916 else if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 2917 kvm_x86_ops->inject_pending_irq(vcpu);
eb9774f0 2918 else
b6c7a5dc
HB		 2919 kvm_x86_ops->inject_pending_vectors(vcpu, kvm_run);
2920
b93463aa
AK		 2921 kvm_lapic_sync_to_vapic(vcpu);
2922
3200f405
MT		 2923 up_read(&vcpu->kvm->slots_lock);
2924
b6c7a5dc
HB		 2925 kvm_guest_enter();
2926
b6c7a5dc 2927
2714d1d3 2928 KVMTRACE_0D(VMENTRY, vcpu, entryexit);
b6c7a5dc
HB		 2929 kvm_x86_ops->run(vcpu, kvm_run);
2930
2931 vcpu->guest_mode = 0;
2932 local_irq_enable();
2933
2934 ++vcpu->stat.exits;
2935
2936 /*
2937 * We must have an instruction between local_irq_enable() and
2938 * kvm_guest_exit(), so the timer interrupt isn't delayed by
2939 * the interrupt shadow. The stat.exits increment will do nicely.
2940 * But we need to prevent reordering, hence this barrier():
2941 */
2942 barrier();
2943
2944 kvm_guest_exit();
2945
2946 preempt_enable();
2947
3200f405
MT		 2948 down_read(&vcpu->kvm->slots_lock);
2949
b6c7a5dc
HB		 2950 /*
2951 * Profile KVM exit RIPs:
2952 */
2953 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 2954 unsigned long rip = kvm_rip_read(vcpu);
2955 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 2956 }
2957
ad312c7c
ZX		 2958 if (vcpu->arch.exception.pending && kvm_x86_ops->exception_injected(vcpu))
2959 vcpu->arch.exception.pending = false;
298101da 2960
b93463aa
AK		 2961 kvm_lapic_sync_from_vapic(vcpu);
2962
b6c7a5dc
HB		 2963 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
2964
2965 if (r > 0) {
2966 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
2967 r = -EINTR;
2968 kvm_run->exit_reason = KVM_EXIT_INTR;
2969 ++vcpu->stat.request_irq_exits;
2970 goto out;
2971 }
e1beb1d3 2972 if (!need_resched())
b6c7a5dc 2973 goto again;
b6c7a5dc
HB		 2974 }
2975
2976out:
3200f405 2977 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 2978 if (r > 0) {
2979 kvm_resched(vcpu);
3200f405 2980 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 2981 goto preempted;
2982 }
2983
2984 post_kvm_run_save(vcpu, kvm_run);
2985
b93463aa
AK		 2986 vapic_exit(vcpu);
2987
b6c7a5dc
HB		 2988 return r;
2989}
2990
2991int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2992{
2993 int r;
2994 sigset_t sigsaved;
2995
2996 vcpu_load(vcpu);
2997
ac9f6dc0
AK		 2998 if (vcpu->sigset_active)
2999 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
3000
a4535290 3001 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 3002 kvm_vcpu_block(vcpu);
ac9f6dc0
AK		 3003 r = -EAGAIN;
3004 goto out;
b6c7a5dc
HB		 3005 }
3006
b6c7a5dc
HB		 3007 /* re-sync apic's tpr */
3008 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 3009 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 3010
ad312c7c 3011 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 3012 r = complete_pio(vcpu);
3013 if (r)
3014 goto out;
3015 }
3016#if CONFIG_HAS_IOMEM
3017 if (vcpu->mmio_needed) {
3018 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3019 vcpu->mmio_read_completed = 1;
3020 vcpu->mmio_needed = 0;
3200f405
MT		 3021
3022 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc 3023 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 3024 vcpu->arch.mmio_fault_cr2, 0,
3025 EMULTYPE_NO_DECODE);
3200f405 3026 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3027 if (r == EMULATE_DO_MMIO) {
3028 /*
3029 * Read-modify-write. Back to userspace.
3030 */
3031 r = 0;
3032 goto out;
3033 }
3034 }
3035#endif
5fdbf976
MT		 3036 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3037 kvm_register_write(vcpu, VCPU_REGS_RAX,
3038 kvm_run->hypercall.ret);
b6c7a5dc
HB		 3039
3040 r = __vcpu_run(vcpu, kvm_run);
3041
3042out:
3043 if (vcpu->sigset_active)
3044 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3045
3046 vcpu_put(vcpu);
3047 return r;
3048}
3049
3050int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3051{
3052 vcpu_load(vcpu);
3053
5fdbf976
MT		 3054 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3055 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3056 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3057 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3058 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3059 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3060 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3061 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 3062#ifdef CONFIG_X86_64
5fdbf976
MT		 3063 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3064 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3065 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3066 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3067 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3068 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3069 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3070 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 3071#endif
3072
5fdbf976 3073 regs->rip = kvm_rip_read(vcpu);
b6c7a5dc
HB		 3074 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3075
3076 /*
3077 * Don't leak debug flags in case they were set for guest debugging
3078 */
3079 if (vcpu->guest_debug.enabled && vcpu->guest_debug.singlestep)
3080 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3081
3082 vcpu_put(vcpu);
3083
3084 return 0;
3085}
3086
3087int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3088{
3089 vcpu_load(vcpu);
3090
5fdbf976
MT		 3091 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3092 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3093 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3094 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3095 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3096 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3097 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3098 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 3099#ifdef CONFIG_X86_64
5fdbf976
MT		 3100 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3101 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3102 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3103 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3104 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3105 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3106 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3107 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
3108
b6c7a5dc
HB		 3109#endif
3110
5fdbf976 3111 kvm_rip_write(vcpu, regs->rip);
b6c7a5dc
HB		 3112 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3113
b6c7a5dc 3114
b4f14abd
JK		 3115 vcpu->arch.exception.pending = false;
3116
b6c7a5dc
HB		 3117 vcpu_put(vcpu);
3118
3119 return 0;
3120}
3121
3e6e0aab
GT		 3122void kvm_get_segment(struct kvm_vcpu *vcpu,
3123 struct kvm_segment *var, int seg)
b6c7a5dc 3124{
14af3f3c 3125 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 3126}
3127
3128void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3129{
3130 struct kvm_segment cs;
3131
3e6e0aab 3132 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 3133 *db = cs.db;
3134 *l = cs.l;
3135}
3136EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3137
3138int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3139 struct kvm_sregs *sregs)
3140{
3141 struct descriptor_table dt;
3142 int pending_vec;
3143
3144 vcpu_load(vcpu);
3145
3e6e0aab
GT		 3146 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3147 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3148 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3149 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3150 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3151 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3152
3e6e0aab
GT		 3153 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3154 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3155
3156 kvm_x86_ops->get_idt(vcpu, &dt);
3157 sregs->idt.limit = dt.limit;
3158 sregs->idt.base = dt.base;
3159 kvm_x86_ops->get_gdt(vcpu, &dt);
3160 sregs->gdt.limit = dt.limit;
3161 sregs->gdt.base = dt.base;
3162
3163 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3164 sregs->cr0 = vcpu->arch.cr0;
3165 sregs->cr2 = vcpu->arch.cr2;
3166 sregs->cr3 = vcpu->arch.cr3;
3167 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3168 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3169 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3170 sregs->apic_base = kvm_get_apic_base(vcpu);
3171
3172 if (irqchip_in_kernel(vcpu->kvm)) {
3173 memset(sregs->interrupt_bitmap, 0,
3174 sizeof sregs->interrupt_bitmap);
3175 pending_vec = kvm_x86_ops->get_irq(vcpu);
3176 if (pending_vec >= 0)
3177 set_bit(pending_vec,
3178 (unsigned long *)sregs->interrupt_bitmap);
3179 } else
ad312c7c 3180 memcpy(sregs->interrupt_bitmap, vcpu->arch.irq_pending,
b6c7a5dc
HB		 3181 sizeof sregs->interrupt_bitmap);
3182
3183 vcpu_put(vcpu);
3184
3185 return 0;
3186}
3187
62d9f0db
MT		 3188int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3189 struct kvm_mp_state *mp_state)
3190{
3191 vcpu_load(vcpu);
3192 mp_state->mp_state = vcpu->arch.mp_state;
3193 vcpu_put(vcpu);
3194 return 0;
3195}
3196
3197int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3198 struct kvm_mp_state *mp_state)
3199{
3200 vcpu_load(vcpu);
3201 vcpu->arch.mp_state = mp_state->mp_state;
3202 vcpu_put(vcpu);
3203 return 0;
3204}
3205
3e6e0aab 3206static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 3207 struct kvm_segment *var, int seg)
3208{
14af3f3c 3209 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 3210}
3211
37817f29
IE		 3212static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3213 struct kvm_segment *kvm_desct)
3214{
3215 kvm_desct->base = seg_desc->base0;
3216 kvm_desct->base |= seg_desc->base1 << 16;
3217 kvm_desct->base |= seg_desc->base2 << 24;
3218 kvm_desct->limit = seg_desc->limit0;
3219 kvm_desct->limit |= seg_desc->limit << 16;
c93cd3a5
MT		 3220 if (seg_desc->g) {
3221 kvm_desct->limit <<= 12;
3222 kvm_desct->limit |= 0xfff;
3223 }
37817f29
IE		 3224 kvm_desct->selector = selector;
3225 kvm_desct->type = seg_desc->type;
3226 kvm_desct->present = seg_desc->p;
3227 kvm_desct->dpl = seg_desc->dpl;
3228 kvm_desct->db = seg_desc->d;
3229 kvm_desct->s = seg_desc->s;
3230 kvm_desct->l = seg_desc->l;
3231 kvm_desct->g = seg_desc->g;
3232 kvm_desct->avl = seg_desc->avl;
3233 if (!selector)
3234 kvm_desct->unusable = 1;
3235 else
3236 kvm_desct->unusable = 0;
3237 kvm_desct->padding = 0;
3238}
3239
3240static void get_segment_descritptor_dtable(struct kvm_vcpu *vcpu,
3241 u16 selector,
3242 struct descriptor_table *dtable)
3243{
3244 if (selector & 1 << 2) {
3245 struct kvm_segment kvm_seg;
3246
3e6e0aab 3247 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 3248
3249 if (kvm_seg.unusable)
3250 dtable->limit = 0;
3251 else
3252 dtable->limit = kvm_seg.limit;
3253 dtable->base = kvm_seg.base;
3254 }
3255 else
3256 kvm_x86_ops->get_gdt(vcpu, dtable);
3257}
3258
3259/* allowed just for 8 bytes segments */
3260static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3261 struct desc_struct *seg_desc)
3262{
98899aa0 3263 gpa_t gpa;
37817f29
IE		 3264 struct descriptor_table dtable;
3265 u16 index = selector >> 3;
3266
3267 get_segment_descritptor_dtable(vcpu, selector, &dtable);
3268
3269 if (dtable.limit < index * 8 + 7) {
3270 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
3271 return 1;
3272 }
98899aa0
MT		 3273 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3274 gpa += index * 8;
3275 return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3276}
3277
3278/* allowed just for 8 bytes segments */
3279static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3280 struct desc_struct *seg_desc)
3281{
98899aa0 3282 gpa_t gpa;
37817f29
IE		 3283 struct descriptor_table dtable;
3284 u16 index = selector >> 3;
3285
3286 get_segment_descritptor_dtable(vcpu, selector, &dtable);
3287
3288 if (dtable.limit < index * 8 + 7)
3289 return 1;
98899aa0
MT		 3290 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3291 gpa += index * 8;
3292 return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3293}
3294
3295static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
3296 struct desc_struct *seg_desc)
3297{
3298 u32 base_addr;
3299
3300 base_addr = seg_desc->base0;
3301 base_addr |= (seg_desc->base1 << 16);
3302 base_addr |= (seg_desc->base2 << 24);
3303
98899aa0 3304 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 3305}
3306
37817f29
IE		 3307static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
3308{
3309 struct kvm_segment kvm_seg;
3310
3e6e0aab 3311 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3312 return kvm_seg.selector;
3313}
3314
3315static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
3316 u16 selector,
3317 struct kvm_segment *kvm_seg)
3318{
3319 struct desc_struct seg_desc;
3320
3321 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
3322 return 1;
3323 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
3324 return 0;
3325}
3326
3e6e0aab
GT		 3327int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3328 int type_bits, int seg)
37817f29
IE		 3329{
3330 struct kvm_segment kvm_seg;
3331
3332 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
3333 return 1;
3334 kvm_seg.type |= type_bits;
3335
3336 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
3337 seg != VCPU_SREG_LDTR)
3338 if (!kvm_seg.s)
3339 kvm_seg.unusable = 1;
3340
3e6e0aab 3341 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3342 return 0;
3343}
3344
3345static void save_state_to_tss32(struct kvm_vcpu *vcpu,
3346 struct tss_segment_32 *tss)
3347{
3348 tss->cr3 = vcpu->arch.cr3;
5fdbf976 3349 tss->eip = kvm_rip_read(vcpu);
37817f29 3350 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 3351 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3352 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3353 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3354 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3355 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3356 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3357 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3358 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 3359 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3360 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3361 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3362 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3363 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
3364 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
3365 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3366 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3367}
3368
3369static int load_state_from_tss32(struct kvm_vcpu *vcpu,
3370 struct tss_segment_32 *tss)
3371{
3372 kvm_set_cr3(vcpu, tss->cr3);
3373
5fdbf976 3374 kvm_rip_write(vcpu, tss->eip);
37817f29
IE		 3375 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
3376
5fdbf976
MT		 3377 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
3378 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
3379 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
3380 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
3381 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
3382 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
3383 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
3384 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 3385
3e6e0aab 3386 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 3387 return 1;
3388
3e6e0aab 3389 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 3390 return 1;
3391
3e6e0aab 3392 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 3393 return 1;
3394
3e6e0aab 3395 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 3396 return 1;
3397
3e6e0aab 3398 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 3399 return 1;
3400
3e6e0aab 3401 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 3402 return 1;
3403
3e6e0aab 3404 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 3405 return 1;
3406 return 0;
3407}
3408
3409static void save_state_to_tss16(struct kvm_vcpu *vcpu,
3410 struct tss_segment_16 *tss)
3411{
5fdbf976 3412 tss->ip = kvm_rip_read(vcpu);
37817f29 3413 tss->flag = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 3414 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3415 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3416 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3417 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3418 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3419 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3420 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
3421 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 3422
3423 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3424 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3425 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3426 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3427 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3428 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3429}
3430
3431static int load_state_from_tss16(struct kvm_vcpu *vcpu,
3432 struct tss_segment_16 *tss)
3433{
5fdbf976 3434 kvm_rip_write(vcpu, tss->ip);
37817f29 3435 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 3436 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
3437 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
3438 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
3439 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
3440 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
3441 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
3442 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
3443 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 3444
3e6e0aab 3445 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 3446 return 1;
3447
3e6e0aab 3448 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 3449 return 1;
3450
3e6e0aab 3451 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 3452 return 1;
3453
3e6e0aab 3454 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 3455 return 1;
3456
3e6e0aab 3457 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 3458 return 1;
3459 return 0;
3460}
3461
8b2cf73c 3462static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
34198bf8 3463 u32 old_tss_base,
37817f29
IE		 3464 struct desc_struct *nseg_desc)
3465{
3466 struct tss_segment_16 tss_segment_16;
3467 int ret = 0;
3468
34198bf8
MT		 3469 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
3470 sizeof tss_segment_16))
37817f29
IE		 3471 goto out;
3472
3473 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 3474
34198bf8
MT		 3475 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
3476 sizeof tss_segment_16))
37817f29 3477 goto out;
34198bf8
MT		 3478
3479 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
3480 &tss_segment_16, sizeof tss_segment_16))
3481 goto out;
3482
37817f29
IE		 3483 if (load_state_from_tss16(vcpu, &tss_segment_16))
3484 goto out;
3485
3486 ret = 1;
3487out:
3488 return ret;
3489}
3490
8b2cf73c 3491static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
34198bf8 3492 u32 old_tss_base,
37817f29
IE		 3493 struct desc_struct *nseg_desc)
3494{
3495 struct tss_segment_32 tss_segment_32;
3496 int ret = 0;
3497
34198bf8
MT		 3498 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
3499 sizeof tss_segment_32))
37817f29
IE		 3500 goto out;
3501
3502 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 3503
34198bf8
MT		 3504 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
3505 sizeof tss_segment_32))
3506 goto out;
3507
3508 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
3509 &tss_segment_32, sizeof tss_segment_32))
37817f29 3510 goto out;
34198bf8 3511
37817f29
IE		 3512 if (load_state_from_tss32(vcpu, &tss_segment_32))
3513 goto out;
3514
3515 ret = 1;
3516out:
3517 return ret;
3518}
3519
3520int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
3521{
3522 struct kvm_segment tr_seg;
3523 struct desc_struct cseg_desc;
3524 struct desc_struct nseg_desc;
3525 int ret = 0;
34198bf8
MT		 3526 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
3527 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 3528
34198bf8 3529 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 3530
34198bf8
MT		 3531 /* FIXME: Handle errors. Failure to read either TSS or their
3532 * descriptors should generate a pagefault.
3533 */
37817f29
IE		 3534 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
3535 goto out;
3536
34198bf8 3537 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 3538 goto out;
3539
37817f29
IE		 3540 if (reason != TASK_SWITCH_IRET) {
3541 int cpl;
3542
3543 cpl = kvm_x86_ops->get_cpl(vcpu);
3544 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
3545 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
3546 return 1;
3547 }
3548 }
3549
3550 if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) {
3551 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
3552 return 1;
3553 }
3554
3555 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 3556 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 3557 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 3558 }
3559
3560 if (reason == TASK_SWITCH_IRET) {
3561 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3562 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
3563 }
3564
3565 kvm_x86_ops->skip_emulated_instruction(vcpu);
37817f29
IE		 3566
3567 if (nseg_desc.type & 8)
34198bf8 3568 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_base,
37817f29
IE		 3569 &nseg_desc);
3570 else
34198bf8 3571 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_base,
37817f29
IE		 3572 &nseg_desc);
3573
3574 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
3575 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3576 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
3577 }
3578
3579 if (reason != TASK_SWITCH_IRET) {
3fe913e7 3580 nseg_desc.type |= (1 << 1);
37817f29
IE		 3581 save_guest_segment_descriptor(vcpu, tss_selector,
3582 &nseg_desc);
3583 }
3584
3585 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
3586 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
3587 tr_seg.type = 11;
3e6e0aab 3588 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 3589out:
37817f29
IE		 3590 return ret;
3591}
3592EXPORT_SYMBOL_GPL(kvm_task_switch);
3593
b6c7a5dc
HB		 3594int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
3595 struct kvm_sregs *sregs)
3596{
3597 int mmu_reset_needed = 0;
3598 int i, pending_vec, max_bits;
3599 struct descriptor_table dt;
3600
3601 vcpu_load(vcpu);
3602
3603 dt.limit = sregs->idt.limit;
3604 dt.base = sregs->idt.base;
3605 kvm_x86_ops->set_idt(vcpu, &dt);
3606 dt.limit = sregs->gdt.limit;
3607 dt.base = sregs->gdt.base;
3608 kvm_x86_ops->set_gdt(vcpu, &dt);
3609
ad312c7c
ZX		 3610 vcpu->arch.cr2 = sregs->cr2;
3611 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
3612 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 3613
2d3ad1f4 3614 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 3615
ad312c7c 3616 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 3617 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 3618 kvm_set_apic_base(vcpu, sregs->apic_base);
3619
3620 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3621
ad312c7c 3622 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 3623 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 3624 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 3625
ad312c7c 3626 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 3627 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3628 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 3629 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 3630
3631 if (mmu_reset_needed)
3632 kvm_mmu_reset_context(vcpu);
3633
3634 if (!irqchip_in_kernel(vcpu->kvm)) {
ad312c7c
ZX		 3635 memcpy(vcpu->arch.irq_pending, sregs->interrupt_bitmap,
3636 sizeof vcpu->arch.irq_pending);
3637 vcpu->arch.irq_summary = 0;
3638 for (i = 0; i < ARRAY_SIZE(vcpu->arch.irq_pending); ++i)
3639 if (vcpu->arch.irq_pending[i])
3640 __set_bit(i, &vcpu->arch.irq_summary);
b6c7a5dc
HB		 3641 } else {
3642 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
3643 pending_vec = find_first_bit(
3644 (const unsigned long *)sregs->interrupt_bitmap,
3645 max_bits);
3646 /* Only pending external irq is handled here */
3647 if (pending_vec < max_bits) {
3648 kvm_x86_ops->set_irq(vcpu, pending_vec);
3649 pr_debug("Set back pending irq %d\n",
3650 pending_vec);
3651 }
3652 }
3653
3e6e0aab
GT		 3654 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3655 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3656 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3657 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3658 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3659 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3660
3e6e0aab
GT		 3661 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3662 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3663
3664 vcpu_put(vcpu);
3665
3666 return 0;
3667}
3668
3669int kvm_arch_vcpu_ioctl_debug_guest(struct kvm_vcpu *vcpu,
3670 struct kvm_debug_guest *dbg)
3671{
3672 int r;
3673
3674 vcpu_load(vcpu);
3675
3676 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
3677
3678 vcpu_put(vcpu);
3679
3680 return r;
3681}
3682
d0752060
HB		 3683/*
3684 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
3685 * we have asm/x86/processor.h
3686 */
3687struct fxsave {
3688 u16 cwd;
3689 u16 swd;
3690 u16 twd;
3691 u16 fop;
3692 u64 rip;
3693 u64 rdp;
3694 u32 mxcsr;
3695 u32 mxcsr_mask;
3696 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
3697#ifdef CONFIG_X86_64
3698 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
3699#else
3700 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
3701#endif
3702};
3703
8b006791
ZX		 3704/*
3705 * Translate a guest virtual address to a guest physical address.
3706 */
3707int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
3708 struct kvm_translation *tr)
3709{
3710 unsigned long vaddr = tr->linear_address;
3711 gpa_t gpa;
3712
3713 vcpu_load(vcpu);
72dc67a6 3714 down_read(&vcpu->kvm->slots_lock);
ad312c7c 3715 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 3716 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 3717 tr->physical_address = gpa;
3718 tr->valid = gpa != UNMAPPED_GVA;
3719 tr->writeable = 1;
3720 tr->usermode = 0;
8b006791
ZX		 3721 vcpu_put(vcpu);
3722
3723 return 0;
3724}
3725
d0752060
HB		 3726int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
3727{
ad312c7c 3728 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 3729
3730 vcpu_load(vcpu);
3731
3732 memcpy(fpu->fpr, fxsave->st_space, 128);
3733 fpu->fcw = fxsave->cwd;
3734 fpu->fsw = fxsave->swd;
3735 fpu->ftwx = fxsave->twd;
3736 fpu->last_opcode = fxsave->fop;
3737 fpu->last_ip = fxsave->rip;
3738 fpu->last_dp = fxsave->rdp;
3739 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
3740
3741 vcpu_put(vcpu);
3742
3743 return 0;
3744}
3745
3746int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
3747{
ad312c7c 3748 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 3749
3750 vcpu_load(vcpu);
3751
3752 memcpy(fxsave->st_space, fpu->fpr, 128);
3753 fxsave->cwd = fpu->fcw;
3754 fxsave->swd = fpu->fsw;
3755 fxsave->twd = fpu->ftwx;
3756 fxsave->fop = fpu->last_opcode;
3757 fxsave->rip = fpu->last_ip;
3758 fxsave->rdp = fpu->last_dp;
3759 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
3760
3761 vcpu_put(vcpu);
3762
3763 return 0;
3764}
3765
3766void fx_init(struct kvm_vcpu *vcpu)
3767{
3768 unsigned after_mxcsr_mask;
3769
bc1a34f1
AA		 3770 /*
3771 * Touch the fpu the first time in non atomic context as if
3772 * this is the first fpu instruction the exception handler
3773 * will fire before the instruction returns and it'll have to
3774 * allocate ram with GFP_KERNEL.
3775 */
3776 if (!used_math())
d6e88aec 3777 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 3778
d0752060
HB		 3779 /* Initialize guest FPU by resetting ours and saving into guest's */
3780 preempt_disable();
d6e88aec
AK		 3781 kvm_fx_save(&vcpu->arch.host_fx_image);
3782 kvm_fx_finit();
3783 kvm_fx_save(&vcpu->arch.guest_fx_image);
3784 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 3785 preempt_enable();
3786
ad312c7c 3787 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 3788 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 3789 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
3790 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 3791 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
3792}
3793EXPORT_SYMBOL_GPL(fx_init);
3794
3795void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
3796{
3797 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
3798 return;
3799
3800 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 3801 kvm_fx_save(&vcpu->arch.host_fx_image);
3802 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 3803}
3804EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
3805
3806void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
3807{
3808 if (!vcpu->guest_fpu_loaded)
3809 return;
3810
3811 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 3812 kvm_fx_save(&vcpu->arch.guest_fx_image);
3813 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 3814 ++vcpu->stat.fpu_reload;
d0752060
HB		 3815}
3816EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 3817
3818void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
3819{
3820 kvm_x86_ops->vcpu_free(vcpu);
3821}
3822
3823struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
3824 unsigned int id)
3825{
26e5215f
AK		 3826 return kvm_x86_ops->vcpu_create(kvm, id);
3827}
e9b11c17 3828
26e5215f
AK		 3829int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
3830{
3831 int r;
e9b11c17
ZX		 3832
3833 /* We do fxsave: this must be aligned. */
ad312c7c 3834 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17
ZX		 3835
3836 vcpu_load(vcpu);
3837 r = kvm_arch_vcpu_reset(vcpu);
3838 if (r == 0)
3839 r = kvm_mmu_setup(vcpu);
3840 vcpu_put(vcpu);
3841 if (r < 0)
3842 goto free_vcpu;
3843
26e5215f 3844 return 0;
e9b11c17
ZX		 3845free_vcpu:
3846 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 3847 return r;
e9b11c17
ZX		 3848}
3849
d40ccc62 3850void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 3851{
3852 vcpu_load(vcpu);
3853 kvm_mmu_unload(vcpu);
3854 vcpu_put(vcpu);
3855
3856 kvm_x86_ops->vcpu_free(vcpu);
3857}
3858
3859int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
3860{
3861 return kvm_x86_ops->vcpu_reset(vcpu);
3862}
3863
3864void kvm_arch_hardware_enable(void *garbage)
3865{
3866 kvm_x86_ops->hardware_enable(garbage);
3867}
3868
3869void kvm_arch_hardware_disable(void *garbage)
3870{
3871 kvm_x86_ops->hardware_disable(garbage);
3872}
3873
3874int kvm_arch_hardware_setup(void)
3875{
3876 return kvm_x86_ops->hardware_setup();
3877}
3878
3879void kvm_arch_hardware_unsetup(void)
3880{
3881 kvm_x86_ops->hardware_unsetup();
3882}
3883
3884void kvm_arch_check_processor_compat(void *rtn)
3885{
3886 kvm_x86_ops->check_processor_compatibility(rtn);
3887}
3888
3889int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
3890{
3891 struct page *page;
3892 struct kvm *kvm;
3893 int r;
3894
3895 BUG_ON(vcpu->kvm == NULL);
3896 kvm = vcpu->kvm;
3897
ad312c7c 3898 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
e9b11c17 3899 if (!irqchip_in_kernel(kvm) || vcpu->vcpu_id == 0)
a4535290 3900 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 3901 else
a4535290 3902 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 3903
3904 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
3905 if (!page) {
3906 r = -ENOMEM;
3907 goto fail;
3908 }
ad312c7c 3909 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 3910
3911 r = kvm_mmu_create(vcpu);
3912 if (r < 0)
3913 goto fail_free_pio_data;
3914
3915 if (irqchip_in_kernel(kvm)) {
3916 r = kvm_create_lapic(vcpu);
3917 if (r < 0)
3918 goto fail_mmu_destroy;
3919 }
3920
3921 return 0;
3922
3923fail_mmu_destroy:
3924 kvm_mmu_destroy(vcpu);
3925fail_free_pio_data:
ad312c7c 3926 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 3927fail:
3928 return r;
3929}
3930
3931void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
3932{
3933 kvm_free_lapic(vcpu);
3200f405 3934 down_read(&vcpu->kvm->slots_lock);
e9b11c17 3935 kvm_mmu_destroy(vcpu);
3200f405 3936 up_read(&vcpu->kvm->slots_lock);
ad312c7c 3937 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 3938}
d19a9cd2
ZX		 3939
3940struct kvm *kvm_arch_create_vm(void)
3941{
3942 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
3943
3944 if (!kvm)
3945 return ERR_PTR(-ENOMEM);
3946
f05e70ac 3947 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
d19a9cd2
ZX		 3948
3949 return kvm;
3950}
3951
3952static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
3953{
3954 vcpu_load(vcpu);
3955 kvm_mmu_unload(vcpu);
3956 vcpu_put(vcpu);
3957}
3958
3959static void kvm_free_vcpus(struct kvm *kvm)
3960{
3961 unsigned int i;
3962
3963 /*
3964 * Unpin any mmu pages first.
3965 */
3966 for (i = 0; i < KVM_MAX_VCPUS; ++i)
3967 if (kvm->vcpus[i])
3968 kvm_unload_vcpu_mmu(kvm->vcpus[i]);
3969 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
3970 if (kvm->vcpus[i]) {
3971 kvm_arch_vcpu_free(kvm->vcpus[i]);
3972 kvm->vcpus[i] = NULL;
3973 }
3974 }
3975
3976}
3977
3978void kvm_arch_destroy_vm(struct kvm *kvm)
3979{
7837699f 3980 kvm_free_pit(kvm);
d7deeeb0
ZX		 3981 kfree(kvm->arch.vpic);
3982 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 3983 kvm_free_vcpus(kvm);
3984 kvm_free_physmem(kvm);
3d45830c
AK		 3985 if (kvm->arch.apic_access_page)
3986 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 3987 if (kvm->arch.ept_identity_pagetable)
3988 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 3989 kfree(kvm);
3990}
0de10343
ZX		 3991
3992int kvm_arch_set_memory_region(struct kvm *kvm,
3993 struct kvm_userspace_memory_region *mem,
3994 struct kvm_memory_slot old,
3995 int user_alloc)
3996{
3997 int npages = mem->memory_size >> PAGE_SHIFT;
3998 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
3999
4000 /*To keep backward compatibility with older userspace,
4001 *x86 needs to hanlde !user_alloc case.
4002 */
4003 if (!user_alloc) {
4004 if (npages && !old.rmap) {
604b38ac
AA		 4005 unsigned long userspace_addr;
4006
72dc67a6 4007 down_write(&current->mm->mmap_sem);
604b38ac
AA		 4008 userspace_addr = do_mmap(NULL, 0,
4009 npages * PAGE_SIZE,
4010 PROT_READ | PROT_WRITE,
4011 MAP_SHARED | MAP_ANONYMOUS,
4012 0);
72dc67a6 4013 up_write(&current->mm->mmap_sem);
0de10343 4014
604b38ac
AA		 4015 if (IS_ERR((void *)userspace_addr))
4016 return PTR_ERR((void *)userspace_addr);
4017
4018 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4019 spin_lock(&kvm->mmu_lock);
4020 memslot->userspace_addr = userspace_addr;
4021 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4022 } else {
4023 if (!old.user_alloc && old.rmap) {
4024 int ret;
4025
72dc67a6 4026 down_write(&current->mm->mmap_sem);
0de10343
ZX		 4027 ret = do_munmap(current->mm, old.userspace_addr,
4028 old.npages * PAGE_SIZE);
72dc67a6 4029 up_write(&current->mm->mmap_sem);
0de10343
ZX		 4030 if (ret < 0)
4031 printk(KERN_WARNING
4032 "kvm_vm_ioctl_set_memory_region: "
4033 "failed to munmap memory\n");
4034 }
4035 }
4036 }
4037
f05e70ac 4038 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 4039 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4040 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4041 }
4042
4043 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
4044 kvm_flush_remote_tlbs(kvm);
4045
4046 return 0;
4047}
1d737c8a 4048
34d4cb8f
MT		 4049void kvm_arch_flush_shadow(struct kvm *kvm)
4050{
4051 kvm_mmu_zap_all(kvm);
4052}
4053
1d737c8a
ZX		 4054int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4055{
a4535290
AK		 4056 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
4057 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED;
1d737c8a 4058}
5736199a
ZX		 4059
4060static void vcpu_kick_intr(void *info)
4061{
4062#ifdef DEBUG
4063 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)info;
4064 printk(KERN_DEBUG "vcpu_kick_intr %p \n", vcpu);
4065#endif
4066}
4067
4068void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4069{
4070 int ipi_pcpu = vcpu->cpu;
e9571ed5 4071 int cpu = get_cpu();
5736199a
ZX		 4072
4073 if (waitqueue_active(&vcpu->wq)) {
4074 wake_up_interruptible(&vcpu->wq);
4075 ++vcpu->stat.halt_wakeup;
4076 }
e9571ed5
MT		 4077 /*
4078 * We may be called synchronously with irqs disabled in guest mode,
4079 * So need not to call smp_call_function_single() in that case.
4080 */
4081 if (vcpu->guest_mode && vcpu->cpu != cpu)
8691e5a8 4082 smp_call_function_single(ipi_pcpu, vcpu_kick_intr, vcpu, 0);
e9571ed5 4083 put_cpu();
5736199a 4084}
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