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KVM: Use kmemdup() instead of kmalloc/memcpy
[mirror_ubuntu-jammy-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
aec51dc4 49#include <trace/events/kvm.h>
2ed152af 50
229456fc
MT		 51#define CREATE_TRACE_POINTS
52#include "trace.h"
043405e1 53
24f1e32c 54#include <asm/debugreg.h>
d825ed0a 55#include <asm/msr.h>
a5f61300 56#include <asm/desc.h>
0bed3b56 57#include <asm/mtrr.h>
890ca9ae 58#include <asm/mce.h>
7cf30855 59#include <asm/i387.h>
98918833 60#include <asm/xcr.h>
1d5f066e 61#include <asm/pvclock.h>
217fc9cf 62#include <asm/div64.h>
043405e1 63
313a3dc7 64#define MAX_IO_MSRS 256
890ca9ae 65#define KVM_MAX_MCE_BANKS 32
5854dbca 66#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 67
0f65dd70
AK		 68#define emul_to_vcpu(ctxt) \
69 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
70
50a37eb4
JR		 71/* EFER defaults:
72 * - enable syscall per default because its emulated by KVM
73 * - enable LME and LMA per default on 64 bit KVM
74 */
75#ifdef CONFIG_X86_64
1260edbe
LJ		 76static
77u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 78#else
1260edbe 79static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 80#endif
313a3dc7 81
ba1389b7
AK		 82#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
83#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 84
cb142eb7 85static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 86static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 87
97896d04 88struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 89EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 90
ed85c068
AP		 91int ignore_msrs = 0;
92module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
93
92a1f12d
JR		 94bool kvm_has_tsc_control;
95EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
96u32 kvm_max_guest_tsc_khz;
97EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
98
18863bdd
AK		 99#define KVM_NR_SHARED_MSRS 16
100
101struct kvm_shared_msrs_global {
102 int nr;
2bf78fa7 103 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 104};
105
106struct kvm_shared_msrs {
107 struct user_return_notifier urn;
108 bool registered;
2bf78fa7
SY		 109 struct kvm_shared_msr_values {
110 u64 host;
111 u64 curr;
112 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 113};
114
115static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
116static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
117
417bc304 118struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 119 { "pf_fixed", VCPU_STAT(pf_fixed) },
120 { "pf_guest", VCPU_STAT(pf_guest) },
121 { "tlb_flush", VCPU_STAT(tlb_flush) },
122 { "invlpg", VCPU_STAT(invlpg) },
123 { "exits", VCPU_STAT(exits) },
124 { "io_exits", VCPU_STAT(io_exits) },
125 { "mmio_exits", VCPU_STAT(mmio_exits) },
126 { "signal_exits", VCPU_STAT(signal_exits) },
127 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 128 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 129 { "halt_exits", VCPU_STAT(halt_exits) },
130 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 131 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 132 { "request_irq", VCPU_STAT(request_irq_exits) },
133 { "irq_exits", VCPU_STAT(irq_exits) },
134 { "host_state_reload", VCPU_STAT(host_state_reload) },
135 { "efer_reload", VCPU_STAT(efer_reload) },
136 { "fpu_reload", VCPU_STAT(fpu_reload) },
137 { "insn_emulation", VCPU_STAT(insn_emulation) },
138 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 139 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 140 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 141 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
142 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
143 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
144 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
145 { "mmu_flooded", VM_STAT(mmu_flooded) },
146 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 147 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 148 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 149 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 150 { "largepages", VM_STAT(lpages) },
417bc304
HB		 151 { NULL }
152};
153
2acf923e
DC		 154u64 __read_mostly host_xcr0;
155
d6aa1000
AK		 156int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
157
af585b92
GN		 158static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
159{
160 int i;
161 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
162 vcpu->arch.apf.gfns[i] = ~0;
163}
164
18863bdd
AK		 165static void kvm_on_user_return(struct user_return_notifier *urn)
166{
167 unsigned slot;
18863bdd
AK		 168 struct kvm_shared_msrs *locals
169 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 170 struct kvm_shared_msr_values *values;
18863bdd
AK		 171
172 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 173 values = &locals->values[slot];
174 if (values->host != values->curr) {
175 wrmsrl(shared_msrs_global.msrs[slot], values->host);
176 values->curr = values->host;
18863bdd
AK		 177 }
178 }
179 locals->registered = false;
180 user_return_notifier_unregister(urn);
181}
182
2bf78fa7 183static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 184{
2bf78fa7 185 struct kvm_shared_msrs *smsr;
18863bdd
AK		 186 u64 value;
187
2bf78fa7
SY		 188 smsr = &__get_cpu_var(shared_msrs);
189 /* only read, and nobody should modify it at this time,
190 * so don't need lock */
191 if (slot >= shared_msrs_global.nr) {
192 printk(KERN_ERR "kvm: invalid MSR slot!");
193 return;
194 }
195 rdmsrl_safe(msr, &value);
196 smsr->values[slot].host = value;
197 smsr->values[slot].curr = value;
198}
199
200void kvm_define_shared_msr(unsigned slot, u32 msr)
201{
18863bdd
AK		 202 if (slot >= shared_msrs_global.nr)
203 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 204 shared_msrs_global.msrs[slot] = msr;
205 /* we need ensured the shared_msr_global have been updated */
206 smp_wmb();
18863bdd
AK		 207}
208EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
209
210static void kvm_shared_msr_cpu_online(void)
211{
212 unsigned i;
18863bdd
AK		 213
214 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 215 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 216}
217
d5696725 218void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 219{
220 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
221
2bf78fa7 222 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 223 return;
2bf78fa7
SY		 224 smsr->values[slot].curr = value;
225 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 226 if (!smsr->registered) {
227 smsr->urn.on_user_return = kvm_on_user_return;
228 user_return_notifier_register(&smsr->urn);
229 smsr->registered = true;
230 }
231}
232EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
233
3548bab5
AK		 234static void drop_user_return_notifiers(void *ignore)
235{
236 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
237
238 if (smsr->registered)
239 kvm_on_user_return(&smsr->urn);
240}
241
6866b83e
CO		 242u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
243{
244 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 245 return vcpu->arch.apic_base;
6866b83e 246 else
ad312c7c 247 return vcpu->arch.apic_base;
6866b83e
CO		 248}
249EXPORT_SYMBOL_GPL(kvm_get_apic_base);
250
251void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
252{
253 /* TODO: reserve bits check */
254 if (irqchip_in_kernel(vcpu->kvm))
255 kvm_lapic_set_base(vcpu, data);
256 else
ad312c7c 257 vcpu->arch.apic_base = data;
6866b83e
CO		 258}
259EXPORT_SYMBOL_GPL(kvm_set_apic_base);
260
3fd28fce
ED		 261#define EXCPT_BENIGN 0
262#define EXCPT_CONTRIBUTORY 1
263#define EXCPT_PF 2
264
265static int exception_class(int vector)
266{
267 switch (vector) {
268 case PF_VECTOR:
269 return EXCPT_PF;
270 case DE_VECTOR:
271 case TS_VECTOR:
272 case NP_VECTOR:
273 case SS_VECTOR:
274 case GP_VECTOR:
275 return EXCPT_CONTRIBUTORY;
276 default:
277 break;
278 }
279 return EXCPT_BENIGN;
280}
281
282static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 283 unsigned nr, bool has_error, u32 error_code,
284 bool reinject)
3fd28fce
ED		 285{
286 u32 prev_nr;
287 int class1, class2;
288
3842d135
AK		 289 kvm_make_request(KVM_REQ_EVENT, vcpu);
290
3fd28fce
ED		 291 if (!vcpu->arch.exception.pending) {
292 queue:
293 vcpu->arch.exception.pending = true;
294 vcpu->arch.exception.has_error_code = has_error;
295 vcpu->arch.exception.nr = nr;
296 vcpu->arch.exception.error_code = error_code;
3f0fd292 297 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 298 return;
299 }
300
301 /* to check exception */
302 prev_nr = vcpu->arch.exception.nr;
303 if (prev_nr == DF_VECTOR) {
304 /* triple fault -> shutdown */
a8eeb04a 305 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 306 return;
307 }
308 class1 = exception_class(prev_nr);
309 class2 = exception_class(nr);
310 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
311 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
312 /* generate double fault per SDM Table 5-5 */
313 vcpu->arch.exception.pending = true;
314 vcpu->arch.exception.has_error_code = true;
315 vcpu->arch.exception.nr = DF_VECTOR;
316 vcpu->arch.exception.error_code = 0;
317 } else
318 /* replace previous exception with a new one in a hope
319 that instruction re-execution will regenerate lost
320 exception */
321 goto queue;
322}
323
298101da
AK		 324void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
325{
ce7ddec4 326 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 327}
328EXPORT_SYMBOL_GPL(kvm_queue_exception);
329
ce7ddec4
JR		 330void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
331{
332 kvm_multiple_exception(vcpu, nr, false, 0, true);
333}
334EXPORT_SYMBOL_GPL(kvm_requeue_exception);
335
db8fcefa 336void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 337{
db8fcefa
AP		 338 if (err)
339 kvm_inject_gp(vcpu, 0);
340 else
341 kvm_x86_ops->skip_emulated_instruction(vcpu);
342}
343EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 344
6389ee94 345void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 346{
347 ++vcpu->stat.pf_guest;
6389ee94
AK		 348 vcpu->arch.cr2 = fault->address;
349 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 350}
27d6c865 351EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 352
6389ee94 353void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 354{
6389ee94
AK		 355 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
356 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 357 else
6389ee94 358 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 359}
360
3419ffc8
SY		 361void kvm_inject_nmi(struct kvm_vcpu *vcpu)
362{
7460fb4a
AK		 363 atomic_inc(&vcpu->arch.nmi_queued);
364 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 365}
366EXPORT_SYMBOL_GPL(kvm_inject_nmi);
367
298101da
AK		 368void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
369{
ce7ddec4 370 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 371}
372EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
373
ce7ddec4
JR		 374void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
375{
376 kvm_multiple_exception(vcpu, nr, true, error_code, true);
377}
378EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
379
0a79b009
AK		 380/*
381 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
382 * a #GP and return false.
383 */
384bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 385{
0a79b009
AK		 386 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
387 return true;
388 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
389 return false;
298101da 390}
0a79b009 391EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 392
ec92fe44
JR		 393/*
394 * This function will be used to read from the physical memory of the currently
395 * running guest. The difference to kvm_read_guest_page is that this function
396 * can read from guest physical or from the guest's guest physical memory.
397 */
398int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
399 gfn_t ngfn, void *data, int offset, int len,
400 u32 access)
401{
402 gfn_t real_gfn;
403 gpa_t ngpa;
404
405 ngpa = gfn_to_gpa(ngfn);
406 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
407 if (real_gfn == UNMAPPED_GVA)
408 return -EFAULT;
409
410 real_gfn = gpa_to_gfn(real_gfn);
411
412 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
413}
414EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
415
3d06b8bf
JR		 416int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
417 void *data, int offset, int len, u32 access)
418{
419 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
420 data, offset, len, access);
421}
422
a03490ed
CO		 423/*
424 * Load the pae pdptrs. Return true is they are all valid.
425 */
ff03a073 426int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 427{
428 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
429 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
430 int i;
431 int ret;
ff03a073 432 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 433
ff03a073
JR		 434 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
435 offset * sizeof(u64), sizeof(pdpte),
436 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 437 if (ret < 0) {
438 ret = 0;
439 goto out;
440 }
441 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 442 if (is_present_gpte(pdpte[i]) &&
20c466b5 443 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 444 ret = 0;
445 goto out;
446 }
447 }
448 ret = 1;
449
ff03a073 450 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 451 __set_bit(VCPU_EXREG_PDPTR,
452 (unsigned long *)&vcpu->arch.regs_avail);
453 __set_bit(VCPU_EXREG_PDPTR,
454 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 455out:
a03490ed
CO		 456
457 return ret;
458}
cc4b6871 459EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 460
d835dfec
AK		 461static bool pdptrs_changed(struct kvm_vcpu *vcpu)
462{
ff03a073 463 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 464 bool changed = true;
3d06b8bf
JR		 465 int offset;
466 gfn_t gfn;
d835dfec
AK		 467 int r;
468
469 if (is_long_mode(vcpu) || !is_pae(vcpu))
470 return false;
471
6de4f3ad
AK		 472 if (!test_bit(VCPU_EXREG_PDPTR,
473 (unsigned long *)&vcpu->arch.regs_avail))
474 return true;
475
9f8fe504
AK		 476 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
477 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 478 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
479 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 480 if (r < 0)
481 goto out;
ff03a073 482 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 483out:
d835dfec
AK		 484
485 return changed;
486}
487
49a9b07e 488int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 489{
aad82703
SY		 490 unsigned long old_cr0 = kvm_read_cr0(vcpu);
491 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
492 X86_CR0_CD | X86_CR0_NW;
493
f9a48e6a
AK		 494 cr0 |= X86_CR0_ET;
495
ab344828 496#ifdef CONFIG_X86_64
0f12244f
GN		 497 if (cr0 & 0xffffffff00000000UL)
498 return 1;
ab344828
GN		 499#endif
500
501 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 502
0f12244f
GN		 503 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
504 return 1;
a03490ed 505
0f12244f
GN		 506 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
507 return 1;
a03490ed
CO		 508
509 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
510#ifdef CONFIG_X86_64
f6801dff 511 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 512 int cs_db, cs_l;
513
0f12244f
GN		 514 if (!is_pae(vcpu))
515 return 1;
a03490ed 516 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 517 if (cs_l)
518 return 1;
a03490ed
CO		 519 } else
520#endif
ff03a073 521 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 522 kvm_read_cr3(vcpu)))
0f12244f 523 return 1;
a03490ed
CO		 524 }
525
526 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 527
d170c419 528 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 529 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 530 kvm_async_pf_hash_reset(vcpu);
531 }
e5f3f027 532
aad82703
SY		 533 if ((cr0 ^ old_cr0) & update_bits)
534 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 535 return 0;
536}
2d3ad1f4 537EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 538
2d3ad1f4 539void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 540{
49a9b07e 541 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 542}
2d3ad1f4 543EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 544
2acf923e
DC		 545int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
546{
547 u64 xcr0;
548
549 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
550 if (index != XCR_XFEATURE_ENABLED_MASK)
551 return 1;
552 xcr0 = xcr;
553 if (kvm_x86_ops->get_cpl(vcpu) != 0)
554 return 1;
555 if (!(xcr0 & XSTATE_FP))
556 return 1;
557 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
558 return 1;
559 if (xcr0 & ~host_xcr0)
560 return 1;
561 vcpu->arch.xcr0 = xcr0;
562 vcpu->guest_xcr0_loaded = 0;
563 return 0;
564}
565
566int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
567{
568 if (__kvm_set_xcr(vcpu, index, xcr)) {
569 kvm_inject_gp(vcpu, 0);
570 return 1;
571 }
572 return 0;
573}
574EXPORT_SYMBOL_GPL(kvm_set_xcr);
575
a83b29c6 576int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 577{
fc78f519 578 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 579 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
580 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 581 if (cr4 & CR4_RESERVED_BITS)
582 return 1;
a03490ed 583
2acf923e
DC		 584 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
585 return 1;
586
c68b734f
YW		 587 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
588 return 1;
589
74dc2b4f
YW		 590 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
591 return 1;
592
a03490ed 593 if (is_long_mode(vcpu)) {
0f12244f
GN		 594 if (!(cr4 & X86_CR4_PAE))
595 return 1;
a2edf57f
AK		 596 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
597 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 598 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
599 kvm_read_cr3(vcpu)))
0f12244f
GN		 600 return 1;
601
5e1746d6 602 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 603 return 1;
a03490ed 604
aad82703
SY		 605 if ((cr4 ^ old_cr4) & pdptr_bits)
606 kvm_mmu_reset_context(vcpu);
0f12244f 607
2acf923e 608 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 609 kvm_update_cpuid(vcpu);
2acf923e 610
0f12244f
GN		 611 return 0;
612}
2d3ad1f4 613EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 614
2390218b 615int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 616{
9f8fe504 617 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 618 kvm_mmu_sync_roots(vcpu);
d835dfec 619 kvm_mmu_flush_tlb(vcpu);
0f12244f 620 return 0;
d835dfec
AK		 621 }
622
a03490ed 623 if (is_long_mode(vcpu)) {
0f12244f
GN		 624 if (cr3 & CR3_L_MODE_RESERVED_BITS)
625 return 1;
a03490ed
CO		 626 } else {
627 if (is_pae(vcpu)) {
0f12244f
GN		 628 if (cr3 & CR3_PAE_RESERVED_BITS)
629 return 1;
ff03a073
JR		 630 if (is_paging(vcpu) &&
631 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 632 return 1;
a03490ed
CO		 633 }
634 /*
635 * We don't check reserved bits in nonpae mode, because
636 * this isn't enforced, and VMware depends on this.
637 */
638 }
639
a03490ed
CO		 640 /*
641 * Does the new cr3 value map to physical memory? (Note, we
642 * catch an invalid cr3 even in real-mode, because it would
643 * cause trouble later on when we turn on paging anyway.)
644 *
645 * A real CPU would silently accept an invalid cr3 and would
646 * attempt to use it - with largely undefined (and often hard
647 * to debug) behavior on the guest side.
648 */
649 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 650 return 1;
651 vcpu->arch.cr3 = cr3;
aff48baa 652 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 653 vcpu->arch.mmu.new_cr3(vcpu);
654 return 0;
655}
2d3ad1f4 656EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 657
eea1cff9 658int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 659{
0f12244f
GN		 660 if (cr8 & CR8_RESERVED_BITS)
661 return 1;
a03490ed
CO		 662 if (irqchip_in_kernel(vcpu->kvm))
663 kvm_lapic_set_tpr(vcpu, cr8);
664 else
ad312c7c 665 vcpu->arch.cr8 = cr8;
0f12244f
GN		 666 return 0;
667}
2d3ad1f4 668EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 669
2d3ad1f4 670unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 671{
672 if (irqchip_in_kernel(vcpu->kvm))
673 return kvm_lapic_get_cr8(vcpu);
674 else
ad312c7c 675 return vcpu->arch.cr8;
a03490ed 676}
2d3ad1f4 677EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 678
338dbc97 679static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 680{
681 switch (dr) {
682 case 0 ... 3:
683 vcpu->arch.db[dr] = val;
684 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
685 vcpu->arch.eff_db[dr] = val;
686 break;
687 case 4:
338dbc97
GN		 688 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
689 return 1; /* #UD */
020df079
GN		 690 /* fall through */
691 case 6:
338dbc97
GN		 692 if (val & 0xffffffff00000000ULL)
693 return -1; /* #GP */
020df079
GN		 694 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
695 break;
696 case 5:
338dbc97
GN		 697 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
698 return 1; /* #UD */
020df079
GN		 699 /* fall through */
700 default: /* 7 */
338dbc97
GN		 701 if (val & 0xffffffff00000000ULL)
702 return -1; /* #GP */
020df079
GN		 703 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
704 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
705 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
706 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
707 }
708 break;
709 }
710
711 return 0;
712}
338dbc97
GN		 713
714int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
715{
716 int res;
717
718 res = __kvm_set_dr(vcpu, dr, val);
719 if (res > 0)
720 kvm_queue_exception(vcpu, UD_VECTOR);
721 else if (res < 0)
722 kvm_inject_gp(vcpu, 0);
723
724 return res;
725}
020df079
GN		 726EXPORT_SYMBOL_GPL(kvm_set_dr);
727
338dbc97 728static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 729{
730 switch (dr) {
731 case 0 ... 3:
732 *val = vcpu->arch.db[dr];
733 break;
734 case 4:
338dbc97 735 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 736 return 1;
020df079
GN		 737 /* fall through */
738 case 6:
739 *val = vcpu->arch.dr6;
740 break;
741 case 5:
338dbc97 742 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 743 return 1;
020df079
GN		 744 /* fall through */
745 default: /* 7 */
746 *val = vcpu->arch.dr7;
747 break;
748 }
749
750 return 0;
751}
338dbc97
GN		 752
753int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
754{
755 if (_kvm_get_dr(vcpu, dr, val)) {
756 kvm_queue_exception(vcpu, UD_VECTOR);
757 return 1;
758 }
759 return 0;
760}
020df079
GN		 761EXPORT_SYMBOL_GPL(kvm_get_dr);
762
043405e1
CO		 763/*
764 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
765 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
766 *
767 * This list is modified at module load time to reflect the
e3267cbb
GC		 768 * capabilities of the host cpu. This capabilities test skips MSRs that are
769 * kvm-specific. Those are put in the beginning of the list.
043405e1 770 */
e3267cbb 771
c9aaa895 772#define KVM_SAVE_MSRS_BEGIN 9
043405e1 773static u32 msrs_to_save[] = {
e3267cbb 774 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 775 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 776 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 777 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
043405e1 778 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 779 MSR_STAR,
043405e1
CO		 780#ifdef CONFIG_X86_64
781 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
782#endif
e90aa41e 783 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 784};
785
786static unsigned num_msrs_to_save;
787
788static u32 emulated_msrs[] = {
a3e06bbe 789 MSR_IA32_TSCDEADLINE,
043405e1 790 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 791 MSR_IA32_MCG_STATUS,
792 MSR_IA32_MCG_CTL,
043405e1
CO		 793};
794
b69e8cae 795static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 796{
aad82703
SY		 797 u64 old_efer = vcpu->arch.efer;
798
b69e8cae
RJ		 799 if (efer & efer_reserved_bits)
800 return 1;
15c4a640
CO		 801
802 if (is_paging(vcpu)
b69e8cae
RJ		 803 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
804 return 1;
15c4a640 805
1b2fd70c
AG		 806 if (efer & EFER_FFXSR) {
807 struct kvm_cpuid_entry2 *feat;
808
809 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 810 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
811 return 1;
1b2fd70c
AG		 812 }
813
d8017474
AG		 814 if (efer & EFER_SVME) {
815 struct kvm_cpuid_entry2 *feat;
816
817 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 818 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
819 return 1;
d8017474
AG		 820 }
821
15c4a640 822 efer &= ~EFER_LMA;
f6801dff 823 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 824
a3d204e2
SY		 825 kvm_x86_ops->set_efer(vcpu, efer);
826
9645bb56 827 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 828
aad82703
SY		 829 /* Update reserved bits */
830 if ((efer ^ old_efer) & EFER_NX)
831 kvm_mmu_reset_context(vcpu);
832
b69e8cae 833 return 0;
15c4a640
CO		 834}
835
f2b4b7dd
JR		 836void kvm_enable_efer_bits(u64 mask)
837{
838 efer_reserved_bits &= ~mask;
839}
840EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
841
842
15c4a640
CO		 843/*
844 * Writes msr value into into the appropriate "register".
845 * Returns 0 on success, non-0 otherwise.
846 * Assumes vcpu_load() was already called.
847 */
848int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
849{
850 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
851}
852
313a3dc7
CO		 853/*
854 * Adapt set_msr() to msr_io()'s calling convention
855 */
856static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
857{
858 return kvm_set_msr(vcpu, index, *data);
859}
860
18068523
GOC		 861static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
862{
9ed3c444
AK		 863 int version;
864 int r;
50d0a0f9 865 struct pvclock_wall_clock wc;
923de3cf 866 struct timespec boot;
18068523
GOC		 867
868 if (!wall_clock)
869 return;
870
9ed3c444
AK		 871 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
872 if (r)
873 return;
874
875 if (version & 1)
876 ++version; /* first time write, random junk */
877
878 ++version;
18068523 879
18068523
GOC		 880 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
881
50d0a0f9
GH		 882 /*
883 * The guest calculates current wall clock time by adding
34c238a1 884 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 885 * wall clock specified here. guest system time equals host
886 * system time for us, thus we must fill in host boot time here.
887 */
923de3cf 888 getboottime(&boot);
50d0a0f9
GH		 889
890 wc.sec = boot.tv_sec;
891 wc.nsec = boot.tv_nsec;
892 wc.version = version;
18068523
GOC		 893
894 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
895
896 version++;
897 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 898}
899
50d0a0f9
GH		 900static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
901{
902 uint32_t quotient, remainder;
903
904 /* Don't try to replace with do_div(), this one calculates
905 * "(dividend << 32) / divisor" */
906 __asm__ ( "divl %4"
907 : "=a" (quotient), "=d" (remainder)
908 : "0" (0), "1" (dividend), "r" (divisor) );
909 return quotient;
910}
911
5f4e3f88
ZA		 912static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
913 s8 *pshift, u32 *pmultiplier)
50d0a0f9 914{
5f4e3f88 915 uint64_t scaled64;
50d0a0f9
GH		 916 int32_t shift = 0;
917 uint64_t tps64;
918 uint32_t tps32;
919
5f4e3f88
ZA		 920 tps64 = base_khz * 1000LL;
921 scaled64 = scaled_khz * 1000LL;
50933623 922 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 923 tps64 >>= 1;
924 shift--;
925 }
926
927 tps32 = (uint32_t)tps64;
50933623
JK		 928 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
929 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 930 scaled64 >>= 1;
931 else
932 tps32 <<= 1;
50d0a0f9
GH		 933 shift++;
934 }
935
5f4e3f88
ZA		 936 *pshift = shift;
937 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 938
5f4e3f88
ZA		 939 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
940 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 941}
942
759379dd
ZA		 943static inline u64 get_kernel_ns(void)
944{
945 struct timespec ts;
946
947 WARN_ON(preemptible());
948 ktime_get_ts(&ts);
949 monotonic_to_bootbased(&ts);
950 return timespec_to_ns(&ts);
50d0a0f9
GH		 951}
952
c8076604 953static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 954unsigned long max_tsc_khz;
c8076604 955
8cfdc000
ZA		 956static inline int kvm_tsc_changes_freq(void)
957{
958 int cpu = get_cpu();
959 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
960 cpufreq_quick_get(cpu) != 0;
961 put_cpu();
962 return ret;
963}
964
a3e06bbe 965u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu)
1e993611
JR		 966{
967 if (vcpu->arch.virtual_tsc_khz)
968 return vcpu->arch.virtual_tsc_khz;
969 else
970 return __this_cpu_read(cpu_tsc_khz);
971}
972
857e4099 973static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
759379dd 974{
217fc9cf
AK		 975 u64 ret;
976
759379dd
ZA		 977 WARN_ON(preemptible());
978 if (kvm_tsc_changes_freq())
979 printk_once(KERN_WARNING
980 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
857e4099 981 ret = nsec * vcpu_tsc_khz(vcpu);
217fc9cf
AK		 982 do_div(ret, USEC_PER_SEC);
983 return ret;
759379dd
ZA		 984}
985
1e993611 986static void kvm_init_tsc_catchup(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
c285545f
ZA		 987{
988 /* Compute a scale to convert nanoseconds in TSC cycles */
989 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1e993611
JR		 990 &vcpu->arch.tsc_catchup_shift,
991 &vcpu->arch.tsc_catchup_mult);
c285545f
ZA		 992}
993
994static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
995{
996 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
1e993611
JR		 997 vcpu->arch.tsc_catchup_mult,
998 vcpu->arch.tsc_catchup_shift);
c285545f
ZA		 999 tsc += vcpu->arch.last_tsc_write;
1000 return tsc;
1001}
1002
99e3e30a
ZA		 1003void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1004{
1005 struct kvm *kvm = vcpu->kvm;
f38e098f 1006 u64 offset, ns, elapsed;
99e3e30a 1007 unsigned long flags;
46543ba4 1008 s64 sdiff;
99e3e30a 1009
038f8c11 1010 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1011 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1012 ns = get_kernel_ns();
f38e098f 1013 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 1014 sdiff = data - kvm->arch.last_tsc_write;
1015 if (sdiff < 0)
1016 sdiff = -sdiff;
f38e098f
ZA		 1017
1018 /*
46543ba4 1019 * Special case: close write to TSC within 5 seconds of
f38e098f 1020 * another CPU is interpreted as an attempt to synchronize
0d2eb44f 1021 * The 5 seconds is to accommodate host load / swapping as
46543ba4 1022 * well as any reset of TSC during the boot process.
f38e098f
ZA		 1023 *
1024 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 1025 * or make a best guest using elapsed value.
f38e098f 1026 */
857e4099 1027 if (sdiff < nsec_to_cycles(vcpu, 5ULL * NSEC_PER_SEC) &&
46543ba4 1028 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 1029 if (!check_tsc_unstable()) {
1030 offset = kvm->arch.last_tsc_offset;
1031 pr_debug("kvm: matched tsc offset for %llu\n", data);
1032 } else {
857e4099 1033 u64 delta = nsec_to_cycles(vcpu, elapsed);
759379dd
ZA		 1034 offset += delta;
1035 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1036 }
1037 ns = kvm->arch.last_tsc_nsec;
1038 }
1039 kvm->arch.last_tsc_nsec = ns;
1040 kvm->arch.last_tsc_write = data;
1041 kvm->arch.last_tsc_offset = offset;
99e3e30a 1042 kvm_x86_ops->write_tsc_offset(vcpu, offset);
038f8c11 1043 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
99e3e30a
ZA		 1044
1045 /* Reset of TSC must disable overshoot protection below */
1046 vcpu->arch.hv_clock.tsc_timestamp = 0;
c285545f
ZA		 1047 vcpu->arch.last_tsc_write = data;
1048 vcpu->arch.last_tsc_nsec = ns;
99e3e30a
ZA		 1049}
1050EXPORT_SYMBOL_GPL(kvm_write_tsc);
1051
34c238a1 1052static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1053{
18068523
GOC		 1054 unsigned long flags;
1055 struct kvm_vcpu_arch *vcpu = &v->arch;
1056 void *shared_kaddr;
463656c0 1057 unsigned long this_tsc_khz;
1d5f066e
ZA		 1058 s64 kernel_ns, max_kernel_ns;
1059 u64 tsc_timestamp;
18068523 1060
18068523
GOC		 1061 /* Keep irq disabled to prevent changes to the clock */
1062 local_irq_save(flags);
d5c1785d 1063 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v);
759379dd 1064 kernel_ns = get_kernel_ns();
1e993611 1065 this_tsc_khz = vcpu_tsc_khz(v);
8cfdc000 1066 if (unlikely(this_tsc_khz == 0)) {
c285545f 1067 local_irq_restore(flags);
34c238a1 1068 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1069 return 1;
1070 }
18068523 1071
c285545f
ZA		 1072 /*
1073 * We may have to catch up the TSC to match elapsed wall clock
1074 * time for two reasons, even if kvmclock is used.
1075 * 1) CPU could have been running below the maximum TSC rate
1076 * 2) Broken TSC compensation resets the base at each VCPU
1077 * entry to avoid unknown leaps of TSC even when running
1078 * again on the same CPU. This may cause apparent elapsed
1079 * time to disappear, and the guest to stand still or run
1080 * very slowly.
1081 */
1082 if (vcpu->tsc_catchup) {
1083 u64 tsc = compute_guest_tsc(v, kernel_ns);
1084 if (tsc > tsc_timestamp) {
1085 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1086 tsc_timestamp = tsc;
1087 }
50d0a0f9
GH		 1088 }
1089
18068523
GOC		 1090 local_irq_restore(flags);
1091
c285545f
ZA		 1092 if (!vcpu->time_page)
1093 return 0;
18068523 1094
1d5f066e
ZA		 1095 /*
1096 * Time as measured by the TSC may go backwards when resetting the base
1097 * tsc_timestamp. The reason for this is that the TSC resolution is
1098 * higher than the resolution of the other clock scales. Thus, many
1099 * possible measurments of the TSC correspond to one measurement of any
1100 * other clock, and so a spread of values is possible. This is not a
1101 * problem for the computation of the nanosecond clock; with TSC rates
1102 * around 1GHZ, there can only be a few cycles which correspond to one
1103 * nanosecond value, and any path through this code will inevitably
1104 * take longer than that. However, with the kernel_ns value itself,
1105 * the precision may be much lower, down to HZ granularity. If the
1106 * first sampling of TSC against kernel_ns ends in the low part of the
1107 * range, and the second in the high end of the range, we can get:
1108 *
1109 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1110 *
1111 * As the sampling errors potentially range in the thousands of cycles,
1112 * it is possible such a time value has already been observed by the
1113 * guest. To protect against this, we must compute the system time as
1114 * observed by the guest and ensure the new system time is greater.
1115 */
1116 max_kernel_ns = 0;
1117 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1118 max_kernel_ns = vcpu->last_guest_tsc -
1119 vcpu->hv_clock.tsc_timestamp;
1120 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1121 vcpu->hv_clock.tsc_to_system_mul,
1122 vcpu->hv_clock.tsc_shift);
1123 max_kernel_ns += vcpu->last_kernel_ns;
1124 }
afbcf7ab 1125
e48672fa 1126 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1127 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1128 &vcpu->hv_clock.tsc_shift,
1129 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1130 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1131 }
1132
1d5f066e
ZA		 1133 if (max_kernel_ns > kernel_ns)
1134 kernel_ns = max_kernel_ns;
1135
8cfdc000 1136 /* With all the info we got, fill in the values */
1d5f066e 1137 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1138 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1139 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1140 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1141 vcpu->hv_clock.flags = 0;
1142
18068523
GOC		 1143 /*
1144 * The interface expects us to write an even number signaling that the
1145 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1146 * state, we just increase by 2 at the end.
18068523 1147 */
50d0a0f9 1148 vcpu->hv_clock.version += 2;
18068523
GOC		 1149
1150 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1151
1152 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1153 sizeof(vcpu->hv_clock));
18068523
GOC		 1154
1155 kunmap_atomic(shared_kaddr, KM_USER0);
1156
1157 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1158 return 0;
c8076604
GH		 1159}
1160
9ba075a6
AK		 1161static bool msr_mtrr_valid(unsigned msr)
1162{
1163 switch (msr) {
1164 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1165 case MSR_MTRRfix64K_00000:
1166 case MSR_MTRRfix16K_80000:
1167 case MSR_MTRRfix16K_A0000:
1168 case MSR_MTRRfix4K_C0000:
1169 case MSR_MTRRfix4K_C8000:
1170 case MSR_MTRRfix4K_D0000:
1171 case MSR_MTRRfix4K_D8000:
1172 case MSR_MTRRfix4K_E0000:
1173 case MSR_MTRRfix4K_E8000:
1174 case MSR_MTRRfix4K_F0000:
1175 case MSR_MTRRfix4K_F8000:
1176 case MSR_MTRRdefType:
1177 case MSR_IA32_CR_PAT:
1178 return true;
1179 case 0x2f8:
1180 return true;
1181 }
1182 return false;
1183}
1184
d6289b93
MT		 1185static bool valid_pat_type(unsigned t)
1186{
1187 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1188}
1189
1190static bool valid_mtrr_type(unsigned t)
1191{
1192 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1193}
1194
1195static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1196{
1197 int i;
1198
1199 if (!msr_mtrr_valid(msr))
1200 return false;
1201
1202 if (msr == MSR_IA32_CR_PAT) {
1203 for (i = 0; i < 8; i++)
1204 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1205 return false;
1206 return true;
1207 } else if (msr == MSR_MTRRdefType) {
1208 if (data & ~0xcff)
1209 return false;
1210 return valid_mtrr_type(data & 0xff);
1211 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1212 for (i = 0; i < 8 ; i++)
1213 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1214 return false;
1215 return true;
1216 }
1217
1218 /* variable MTRRs */
1219 return valid_mtrr_type(data & 0xff);
1220}
1221
9ba075a6
AK		 1222static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1223{
0bed3b56
SY		 1224 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1225
d6289b93 1226 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1227 return 1;
1228
0bed3b56
SY		 1229 if (msr == MSR_MTRRdefType) {
1230 vcpu->arch.mtrr_state.def_type = data;
1231 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1232 } else if (msr == MSR_MTRRfix64K_00000)
1233 p[0] = data;
1234 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1235 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1236 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1237 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1238 else if (msr == MSR_IA32_CR_PAT)
1239 vcpu->arch.pat = data;
1240 else { /* Variable MTRRs */
1241 int idx, is_mtrr_mask;
1242 u64 *pt;
1243
1244 idx = (msr - 0x200) / 2;
1245 is_mtrr_mask = msr - 0x200 - 2 * idx;
1246 if (!is_mtrr_mask)
1247 pt =
1248 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1249 else
1250 pt =
1251 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1252 *pt = data;
1253 }
1254
1255 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1256 return 0;
1257}
15c4a640 1258
890ca9ae 1259static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1260{
890ca9ae
HY		 1261 u64 mcg_cap = vcpu->arch.mcg_cap;
1262 unsigned bank_num = mcg_cap & 0xff;
1263
15c4a640 1264 switch (msr) {
15c4a640 1265 case MSR_IA32_MCG_STATUS:
890ca9ae 1266 vcpu->arch.mcg_status = data;
15c4a640 1267 break;
c7ac679c 1268 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1269 if (!(mcg_cap & MCG_CTL_P))
1270 return 1;
1271 if (data != 0 && data != ~(u64)0)
1272 return -1;
1273 vcpu->arch.mcg_ctl = data;
1274 break;
1275 default:
1276 if (msr >= MSR_IA32_MC0_CTL &&
1277 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1278 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1279 /* only 0 or all 1s can be written to IA32_MCi_CTL
1280 * some Linux kernels though clear bit 10 in bank 4 to
1281 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1282 * this to avoid an uncatched #GP in the guest
1283 */
890ca9ae 1284 if ((offset & 0x3) == 0 &&
114be429 1285 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1286 return -1;
1287 vcpu->arch.mce_banks[offset] = data;
1288 break;
1289 }
1290 return 1;
1291 }
1292 return 0;
1293}
1294
ffde22ac
ES		 1295static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1296{
1297 struct kvm *kvm = vcpu->kvm;
1298 int lm = is_long_mode(vcpu);
1299 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1300 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1301 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1302 : kvm->arch.xen_hvm_config.blob_size_32;
1303 u32 page_num = data & ~PAGE_MASK;
1304 u64 page_addr = data & PAGE_MASK;
1305 u8 *page;
1306 int r;
1307
1308 r = -E2BIG;
1309 if (page_num >= blob_size)
1310 goto out;
1311 r = -ENOMEM;
1312 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1313 if (!page)
1314 goto out;
1315 r = -EFAULT;
1316 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1317 goto out_free;
1318 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1319 goto out_free;
1320 r = 0;
1321out_free:
1322 kfree(page);
1323out:
1324 return r;
1325}
1326
55cd8e5a
GN		 1327static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1328{
1329 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1330}
1331
1332static bool kvm_hv_msr_partition_wide(u32 msr)
1333{
1334 bool r = false;
1335 switch (msr) {
1336 case HV_X64_MSR_GUEST_OS_ID:
1337 case HV_X64_MSR_HYPERCALL:
1338 r = true;
1339 break;
1340 }
1341
1342 return r;
1343}
1344
1345static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1346{
1347 struct kvm *kvm = vcpu->kvm;
1348
1349 switch (msr) {
1350 case HV_X64_MSR_GUEST_OS_ID:
1351 kvm->arch.hv_guest_os_id = data;
1352 /* setting guest os id to zero disables hypercall page */
1353 if (!kvm->arch.hv_guest_os_id)
1354 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1355 break;
1356 case HV_X64_MSR_HYPERCALL: {
1357 u64 gfn;
1358 unsigned long addr;
1359 u8 instructions[4];
1360
1361 /* if guest os id is not set hypercall should remain disabled */
1362 if (!kvm->arch.hv_guest_os_id)
1363 break;
1364 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1365 kvm->arch.hv_hypercall = data;
1366 break;
1367 }
1368 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1369 addr = gfn_to_hva(kvm, gfn);
1370 if (kvm_is_error_hva(addr))
1371 return 1;
1372 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1373 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1374 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1375 return 1;
1376 kvm->arch.hv_hypercall = data;
1377 break;
1378 }
1379 default:
1380 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1381 "data 0x%llx\n", msr, data);
1382 return 1;
1383 }
1384 return 0;
1385}
1386
1387static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1388{
10388a07
GN		 1389 switch (msr) {
1390 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1391 unsigned long addr;
55cd8e5a 1392
10388a07
GN		 1393 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1394 vcpu->arch.hv_vapic = data;
1395 break;
1396 }
1397 addr = gfn_to_hva(vcpu->kvm, data >>
1398 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1399 if (kvm_is_error_hva(addr))
1400 return 1;
8b0cedff 1401 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1402 return 1;
1403 vcpu->arch.hv_vapic = data;
1404 break;
1405 }
1406 case HV_X64_MSR_EOI:
1407 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1408 case HV_X64_MSR_ICR:
1409 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1410 case HV_X64_MSR_TPR:
1411 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1412 default:
1413 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1414 "data 0x%llx\n", msr, data);
1415 return 1;
1416 }
1417
1418 return 0;
55cd8e5a
GN		 1419}
1420
344d9588
GN		 1421static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1422{
1423 gpa_t gpa = data & ~0x3f;
1424
6adba527
GN		 1425 /* Bits 2:5 are resrved, Should be zero */
1426 if (data & 0x3c)
344d9588
GN		 1427 return 1;
1428
1429 vcpu->arch.apf.msr_val = data;
1430
1431 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1432 kvm_clear_async_pf_completion_queue(vcpu);
1433 kvm_async_pf_hash_reset(vcpu);
1434 return 0;
1435 }
1436
1437 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1438 return 1;
1439
6adba527 1440 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1441 kvm_async_pf_wakeup_all(vcpu);
1442 return 0;
1443}
1444
12f9a48f
GC		 1445static void kvmclock_reset(struct kvm_vcpu *vcpu)
1446{
1447 if (vcpu->arch.time_page) {
1448 kvm_release_page_dirty(vcpu->arch.time_page);
1449 vcpu->arch.time_page = NULL;
1450 }
1451}
1452
c9aaa895
GC		 1453static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1454{
1455 u64 delta;
1456
1457 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1458 return;
1459
1460 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1461 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1462 vcpu->arch.st.accum_steal = delta;
1463}
1464
1465static void record_steal_time(struct kvm_vcpu *vcpu)
1466{
1467 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1468 return;
1469
1470 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1471 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1472 return;
1473
1474 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1475 vcpu->arch.st.steal.version += 2;
1476 vcpu->arch.st.accum_steal = 0;
1477
1478 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1479 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1480}
1481
15c4a640
CO		 1482int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1483{
1484 switch (msr) {
15c4a640 1485 case MSR_EFER:
b69e8cae 1486 return set_efer(vcpu, data);
8f1589d9
AP		 1487 case MSR_K7_HWCR:
1488 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1489 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1490 if (data != 0) {
1491 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1492 data);
1493 return 1;
1494 }
15c4a640 1495 break;
f7c6d140
AP		 1496 case MSR_FAM10H_MMIO_CONF_BASE:
1497 if (data != 0) {
1498 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1499 "0x%llx\n", data);
1500 return 1;
1501 }
15c4a640 1502 break;
c323c0e5 1503 case MSR_AMD64_NB_CFG:
c7ac679c 1504 break;
b5e2fec0
AG		 1505 case MSR_IA32_DEBUGCTLMSR:
1506 if (!data) {
1507 /* We support the non-activated case already */
1508 break;
1509 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1510 /* Values other than LBR and BTF are vendor-specific,
1511 thus reserved and should throw a #GP */
1512 return 1;
1513 }
1514 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1515 __func__, data);
1516 break;
15c4a640
CO		 1517 case MSR_IA32_UCODE_REV:
1518 case MSR_IA32_UCODE_WRITE:
61a6bd67 1519 case MSR_VM_HSAVE_PA:
6098ca93 1520 case MSR_AMD64_PATCH_LOADER:
15c4a640 1521 break;
9ba075a6
AK		 1522 case 0x200 ... 0x2ff:
1523 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1524 case MSR_IA32_APICBASE:
1525 kvm_set_apic_base(vcpu, data);
1526 break;
0105d1a5
GN		 1527 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1528 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1529 case MSR_IA32_TSCDEADLINE:
1530 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1531 break;
15c4a640 1532 case MSR_IA32_MISC_ENABLE:
ad312c7c 1533 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1534 break;
11c6bffa 1535 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1536 case MSR_KVM_WALL_CLOCK:
1537 vcpu->kvm->arch.wall_clock = data;
1538 kvm_write_wall_clock(vcpu->kvm, data);
1539 break;
11c6bffa 1540 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1541 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1542 kvmclock_reset(vcpu);
18068523
GOC		 1543
1544 vcpu->arch.time = data;
c285545f 1545 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1546
1547 /* we verify if the enable bit is set... */
1548 if (!(data & 1))
1549 break;
1550
1551 /* ...but clean it before doing the actual write */
1552 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1553
18068523
GOC		 1554 vcpu->arch.time_page =
1555 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1556
1557 if (is_error_page(vcpu->arch.time_page)) {
1558 kvm_release_page_clean(vcpu->arch.time_page);
1559 vcpu->arch.time_page = NULL;
1560 }
18068523
GOC		 1561 break;
1562 }
344d9588
GN		 1563 case MSR_KVM_ASYNC_PF_EN:
1564 if (kvm_pv_enable_async_pf(vcpu, data))
1565 return 1;
1566 break;
c9aaa895
GC		 1567 case MSR_KVM_STEAL_TIME:
1568
1569 if (unlikely(!sched_info_on()))
1570 return 1;
1571
1572 if (data & KVM_STEAL_RESERVED_MASK)
1573 return 1;
1574
1575 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1576 data & KVM_STEAL_VALID_BITS))
1577 return 1;
1578
1579 vcpu->arch.st.msr_val = data;
1580
1581 if (!(data & KVM_MSR_ENABLED))
1582 break;
1583
1584 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1585
1586 preempt_disable();
1587 accumulate_steal_time(vcpu);
1588 preempt_enable();
1589
1590 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1591
1592 break;
1593
890ca9ae
HY		 1594 case MSR_IA32_MCG_CTL:
1595 case MSR_IA32_MCG_STATUS:
1596 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1597 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1598
1599 /* Performance counters are not protected by a CPUID bit,
1600 * so we should check all of them in the generic path for the sake of
1601 * cross vendor migration.
1602 * Writing a zero into the event select MSRs disables them,
1603 * which we perfectly emulate ;-). Any other value should be at least
1604 * reported, some guests depend on them.
1605 */
1606 case MSR_P6_EVNTSEL0:
1607 case MSR_P6_EVNTSEL1:
1608 case MSR_K7_EVNTSEL0:
1609 case MSR_K7_EVNTSEL1:
1610 case MSR_K7_EVNTSEL2:
1611 case MSR_K7_EVNTSEL3:
1612 if (data != 0)
1613 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1614 "0x%x data 0x%llx\n", msr, data);
1615 break;
1616 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1617 * so we ignore writes to make it happy.
1618 */
1619 case MSR_P6_PERFCTR0:
1620 case MSR_P6_PERFCTR1:
1621 case MSR_K7_PERFCTR0:
1622 case MSR_K7_PERFCTR1:
1623 case MSR_K7_PERFCTR2:
1624 case MSR_K7_PERFCTR3:
1625 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1626 "0x%x data 0x%llx\n", msr, data);
1627 break;
84e0cefa
JS		 1628 case MSR_K7_CLK_CTL:
1629 /*
1630 * Ignore all writes to this no longer documented MSR.
1631 * Writes are only relevant for old K7 processors,
1632 * all pre-dating SVM, but a recommended workaround from
1633 * AMD for these chips. It is possible to speicify the
1634 * affected processor models on the command line, hence
1635 * the need to ignore the workaround.
1636 */
1637 break;
55cd8e5a
GN		 1638 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1639 if (kvm_hv_msr_partition_wide(msr)) {
1640 int r;
1641 mutex_lock(&vcpu->kvm->lock);
1642 r = set_msr_hyperv_pw(vcpu, msr, data);
1643 mutex_unlock(&vcpu->kvm->lock);
1644 return r;
1645 } else
1646 return set_msr_hyperv(vcpu, msr, data);
1647 break;
91c9c3ed 1648 case MSR_IA32_BBL_CR_CTL3:
1649 /* Drop writes to this legacy MSR -- see rdmsr
1650 * counterpart for further detail.
1651 */
1652 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1653 break;
15c4a640 1654 default:
ffde22ac
ES		 1655 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1656 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1657 if (!ignore_msrs) {
1658 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1659 msr, data);
1660 return 1;
1661 } else {
1662 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1663 msr, data);
1664 break;
1665 }
15c4a640
CO		 1666 }
1667 return 0;
1668}
1669EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1670
1671
1672/*
1673 * Reads an msr value (of 'msr_index') into 'pdata'.
1674 * Returns 0 on success, non-0 otherwise.
1675 * Assumes vcpu_load() was already called.
1676 */
1677int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1678{
1679 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1680}
1681
9ba075a6
AK		 1682static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1683{
0bed3b56
SY		 1684 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1685
9ba075a6
AK		 1686 if (!msr_mtrr_valid(msr))
1687 return 1;
1688
0bed3b56
SY		 1689 if (msr == MSR_MTRRdefType)
1690 *pdata = vcpu->arch.mtrr_state.def_type +
1691 (vcpu->arch.mtrr_state.enabled << 10);
1692 else if (msr == MSR_MTRRfix64K_00000)
1693 *pdata = p[0];
1694 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1695 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1696 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1697 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1698 else if (msr == MSR_IA32_CR_PAT)
1699 *pdata = vcpu->arch.pat;
1700 else { /* Variable MTRRs */
1701 int idx, is_mtrr_mask;
1702 u64 *pt;
1703
1704 idx = (msr - 0x200) / 2;
1705 is_mtrr_mask = msr - 0x200 - 2 * idx;
1706 if (!is_mtrr_mask)
1707 pt =
1708 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1709 else
1710 pt =
1711 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1712 *pdata = *pt;
1713 }
1714
9ba075a6
AK		 1715 return 0;
1716}
1717
890ca9ae 1718static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1719{
1720 u64 data;
890ca9ae
HY		 1721 u64 mcg_cap = vcpu->arch.mcg_cap;
1722 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1723
1724 switch (msr) {
15c4a640
CO		 1725 case MSR_IA32_P5_MC_ADDR:
1726 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1727 data = 0;
1728 break;
15c4a640 1729 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1730 data = vcpu->arch.mcg_cap;
1731 break;
c7ac679c 1732 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1733 if (!(mcg_cap & MCG_CTL_P))
1734 return 1;
1735 data = vcpu->arch.mcg_ctl;
1736 break;
1737 case MSR_IA32_MCG_STATUS:
1738 data = vcpu->arch.mcg_status;
1739 break;
1740 default:
1741 if (msr >= MSR_IA32_MC0_CTL &&
1742 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1743 u32 offset = msr - MSR_IA32_MC0_CTL;
1744 data = vcpu->arch.mce_banks[offset];
1745 break;
1746 }
1747 return 1;
1748 }
1749 *pdata = data;
1750 return 0;
1751}
1752
55cd8e5a
GN		 1753static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1754{
1755 u64 data = 0;
1756 struct kvm *kvm = vcpu->kvm;
1757
1758 switch (msr) {
1759 case HV_X64_MSR_GUEST_OS_ID:
1760 data = kvm->arch.hv_guest_os_id;
1761 break;
1762 case HV_X64_MSR_HYPERCALL:
1763 data = kvm->arch.hv_hypercall;
1764 break;
1765 default:
1766 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1767 return 1;
1768 }
1769
1770 *pdata = data;
1771 return 0;
1772}
1773
1774static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1775{
1776 u64 data = 0;
1777
1778 switch (msr) {
1779 case HV_X64_MSR_VP_INDEX: {
1780 int r;
1781 struct kvm_vcpu *v;
1782 kvm_for_each_vcpu(r, v, vcpu->kvm)
1783 if (v == vcpu)
1784 data = r;
1785 break;
1786 }
10388a07
GN		 1787 case HV_X64_MSR_EOI:
1788 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1789 case HV_X64_MSR_ICR:
1790 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1791 case HV_X64_MSR_TPR:
1792 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 1793 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 1794 data = vcpu->arch.hv_vapic;
1795 break;
55cd8e5a
GN		 1796 default:
1797 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1798 return 1;
1799 }
1800 *pdata = data;
1801 return 0;
1802}
1803
890ca9ae
HY		 1804int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1805{
1806 u64 data;
1807
1808 switch (msr) {
890ca9ae 1809 case MSR_IA32_PLATFORM_ID:
15c4a640 1810 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1811 case MSR_IA32_DEBUGCTLMSR:
1812 case MSR_IA32_LASTBRANCHFROMIP:
1813 case MSR_IA32_LASTBRANCHTOIP:
1814 case MSR_IA32_LASTINTFROMIP:
1815 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1816 case MSR_K8_SYSCFG:
1817 case MSR_K7_HWCR:
61a6bd67 1818 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1819 case MSR_P6_PERFCTR0:
1820 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1821 case MSR_P6_EVNTSEL0:
1822 case MSR_P6_EVNTSEL1:
9e699624 1823 case MSR_K7_EVNTSEL0:
1f3ee616 1824 case MSR_K7_PERFCTR0:
1fdbd48c 1825 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1826 case MSR_AMD64_NB_CFG:
f7c6d140 1827 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1828 data = 0;
1829 break;
742bc670
MT		 1830 case MSR_IA32_UCODE_REV:
1831 data = 0x100000000ULL;
1832 break;
9ba075a6
AK		 1833 case MSR_MTRRcap:
1834 data = 0x500 | KVM_NR_VAR_MTRR;
1835 break;
1836 case 0x200 ... 0x2ff:
1837 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1838 case 0xcd: /* fsb frequency */
1839 data = 3;
1840 break;
7b914098
JS		 1841 /*
1842 * MSR_EBC_FREQUENCY_ID
1843 * Conservative value valid for even the basic CPU models.
1844 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1845 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1846 * and 266MHz for model 3, or 4. Set Core Clock
1847 * Frequency to System Bus Frequency Ratio to 1 (bits
1848 * 31:24) even though these are only valid for CPU
1849 * models > 2, however guests may end up dividing or
1850 * multiplying by zero otherwise.
1851 */
1852 case MSR_EBC_FREQUENCY_ID:
1853 data = 1 << 24;
1854 break;
15c4a640
CO		 1855 case MSR_IA32_APICBASE:
1856 data = kvm_get_apic_base(vcpu);
1857 break;
0105d1a5
GN		 1858 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1859 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1860 break;
a3e06bbe
LJ		 1861 case MSR_IA32_TSCDEADLINE:
1862 data = kvm_get_lapic_tscdeadline_msr(vcpu);
1863 break;
15c4a640 1864 case MSR_IA32_MISC_ENABLE:
ad312c7c 1865 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1866 break;
847f0ad8
AG		 1867 case MSR_IA32_PERF_STATUS:
1868 /* TSC increment by tick */
1869 data = 1000ULL;
1870 /* CPU multiplier */
1871 data |= (((uint64_t)4ULL) << 40);
1872 break;
15c4a640 1873 case MSR_EFER:
f6801dff 1874 data = vcpu->arch.efer;
15c4a640 1875 break;
18068523 1876 case MSR_KVM_WALL_CLOCK:
11c6bffa 1877 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1878 data = vcpu->kvm->arch.wall_clock;
1879 break;
1880 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1881 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1882 data = vcpu->arch.time;
1883 break;
344d9588
GN		 1884 case MSR_KVM_ASYNC_PF_EN:
1885 data = vcpu->arch.apf.msr_val;
1886 break;
c9aaa895
GC		 1887 case MSR_KVM_STEAL_TIME:
1888 data = vcpu->arch.st.msr_val;
1889 break;
890ca9ae
HY		 1890 case MSR_IA32_P5_MC_ADDR:
1891 case MSR_IA32_P5_MC_TYPE:
1892 case MSR_IA32_MCG_CAP:
1893 case MSR_IA32_MCG_CTL:
1894 case MSR_IA32_MCG_STATUS:
1895 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1896 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1897 case MSR_K7_CLK_CTL:
1898 /*
1899 * Provide expected ramp-up count for K7. All other
1900 * are set to zero, indicating minimum divisors for
1901 * every field.
1902 *
1903 * This prevents guest kernels on AMD host with CPU
1904 * type 6, model 8 and higher from exploding due to
1905 * the rdmsr failing.
1906 */
1907 data = 0x20000000;
1908 break;
55cd8e5a
GN		 1909 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1910 if (kvm_hv_msr_partition_wide(msr)) {
1911 int r;
1912 mutex_lock(&vcpu->kvm->lock);
1913 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1914 mutex_unlock(&vcpu->kvm->lock);
1915 return r;
1916 } else
1917 return get_msr_hyperv(vcpu, msr, pdata);
1918 break;
91c9c3ed 1919 case MSR_IA32_BBL_CR_CTL3:
1920 /* This legacy MSR exists but isn't fully documented in current
1921 * silicon. It is however accessed by winxp in very narrow
1922 * scenarios where it sets bit #19, itself documented as
1923 * a "reserved" bit. Best effort attempt to source coherent
1924 * read data here should the balance of the register be
1925 * interpreted by the guest:
1926 *
1927 * L2 cache control register 3: 64GB range, 256KB size,
1928 * enabled, latency 0x1, configured
1929 */
1930 data = 0xbe702111;
1931 break;
15c4a640 1932 default:
ed85c068
AP		 1933 if (!ignore_msrs) {
1934 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1935 return 1;
1936 } else {
1937 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1938 data = 0;
1939 }
1940 break;
15c4a640
CO		 1941 }
1942 *pdata = data;
1943 return 0;
1944}
1945EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1946
313a3dc7
CO		 1947/*
1948 * Read or write a bunch of msrs. All parameters are kernel addresses.
1949 *
1950 * @return number of msrs set successfully.
1951 */
1952static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1953 struct kvm_msr_entry *entries,
1954 int (*do_msr)(struct kvm_vcpu *vcpu,
1955 unsigned index, u64 *data))
1956{
f656ce01 1957 int i, idx;
313a3dc7 1958
f656ce01 1959 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1960 for (i = 0; i < msrs->nmsrs; ++i)
1961 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1962 break;
f656ce01 1963 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1964
313a3dc7
CO		 1965 return i;
1966}
1967
1968/*
1969 * Read or write a bunch of msrs. Parameters are user addresses.
1970 *
1971 * @return number of msrs set successfully.
1972 */
1973static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1974 int (*do_msr)(struct kvm_vcpu *vcpu,
1975 unsigned index, u64 *data),
1976 int writeback)
1977{
1978 struct kvm_msrs msrs;
1979 struct kvm_msr_entry *entries;
1980 int r, n;
1981 unsigned size;
1982
1983 r = -EFAULT;
1984 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1985 goto out;
1986
1987 r = -E2BIG;
1988 if (msrs.nmsrs >= MAX_IO_MSRS)
1989 goto out;
1990
1991 r = -ENOMEM;
1992 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1993 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1994 if (!entries)
1995 goto out;
1996
1997 r = -EFAULT;
1998 if (copy_from_user(entries, user_msrs->entries, size))
1999 goto out_free;
2000
2001 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2002 if (r < 0)
2003 goto out_free;
2004
2005 r = -EFAULT;
2006 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2007 goto out_free;
2008
2009 r = n;
2010
2011out_free:
7a73c028 2012 kfree(entries);
313a3dc7
CO		 2013out:
2014 return r;
2015}
2016
018d00d2
ZX		 2017int kvm_dev_ioctl_check_extension(long ext)
2018{
2019 int r;
2020
2021 switch (ext) {
2022 case KVM_CAP_IRQCHIP:
2023 case KVM_CAP_HLT:
2024 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2025 case KVM_CAP_SET_TSS_ADDR:
07716717 2026 case KVM_CAP_EXT_CPUID:
c8076604 2027 case KVM_CAP_CLOCKSOURCE:
7837699f 2028 case KVM_CAP_PIT:
a28e4f5a 2029 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2030 case KVM_CAP_MP_STATE:
ed848624 2031 case KVM_CAP_SYNC_MMU:
a355c85c 2032 case KVM_CAP_USER_NMI:
52d939a0 2033 case KVM_CAP_REINJECT_CONTROL:
4925663a 2034 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 2035 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 2036 case KVM_CAP_IRQFD:
d34e6b17 2037 case KVM_CAP_IOEVENTFD:
c5ff41ce 2038 case KVM_CAP_PIT2:
e9f42757 2039 case KVM_CAP_PIT_STATE2:
b927a3ce 2040 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2041 case KVM_CAP_XEN_HVM:
afbcf7ab 2042 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2043 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2044 case KVM_CAP_HYPERV:
10388a07 2045 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2046 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2047 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2048 case KVM_CAP_DEBUGREGS:
d2be1651 2049 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2050 case KVM_CAP_XSAVE:
344d9588 2051 case KVM_CAP_ASYNC_PF:
92a1f12d 2052 case KVM_CAP_GET_TSC_KHZ:
018d00d2
ZX		 2053 r = 1;
2054 break;
542472b5
LV		 2055 case KVM_CAP_COALESCED_MMIO:
2056 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2057 break;
774ead3a
AK		 2058 case KVM_CAP_VAPIC:
2059 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2060 break;
f725230a 2061 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2062 r = KVM_SOFT_MAX_VCPUS;
2063 break;
2064 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2065 r = KVM_MAX_VCPUS;
2066 break;
a988b910
AK		 2067 case KVM_CAP_NR_MEMSLOTS:
2068 r = KVM_MEMORY_SLOTS;
2069 break;
a68a6a72
MT		 2070 case KVM_CAP_PV_MMU: /* obsolete */
2071 r = 0;
2f333bcb 2072 break;
62c476c7 2073 case KVM_CAP_IOMMU:
a1b60c1c 2074 r = iommu_present(&pci_bus_type);
62c476c7 2075 break;
890ca9ae
HY		 2076 case KVM_CAP_MCE:
2077 r = KVM_MAX_MCE_BANKS;
2078 break;
2d5b5a66
SY		 2079 case KVM_CAP_XCRS:
2080 r = cpu_has_xsave;
2081 break;
92a1f12d
JR		 2082 case KVM_CAP_TSC_CONTROL:
2083 r = kvm_has_tsc_control;
2084 break;
4d25a066
JK		 2085 case KVM_CAP_TSC_DEADLINE_TIMER:
2086 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2087 break;
018d00d2
ZX		 2088 default:
2089 r = 0;
2090 break;
2091 }
2092 return r;
2093
2094}
2095
043405e1
CO		 2096long kvm_arch_dev_ioctl(struct file *filp,
2097 unsigned int ioctl, unsigned long arg)
2098{
2099 void __user *argp = (void __user *)arg;
2100 long r;
2101
2102 switch (ioctl) {
2103 case KVM_GET_MSR_INDEX_LIST: {
2104 struct kvm_msr_list __user *user_msr_list = argp;
2105 struct kvm_msr_list msr_list;
2106 unsigned n;
2107
2108 r = -EFAULT;
2109 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2110 goto out;
2111 n = msr_list.nmsrs;
2112 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2113 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2114 goto out;
2115 r = -E2BIG;
e125e7b6 2116 if (n < msr_list.nmsrs)
043405e1
CO		 2117 goto out;
2118 r = -EFAULT;
2119 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2120 num_msrs_to_save * sizeof(u32)))
2121 goto out;
e125e7b6 2122 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2123 &emulated_msrs,
2124 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2125 goto out;
2126 r = 0;
2127 break;
2128 }
674eea0f
AK		 2129 case KVM_GET_SUPPORTED_CPUID: {
2130 struct kvm_cpuid2 __user *cpuid_arg = argp;
2131 struct kvm_cpuid2 cpuid;
2132
2133 r = -EFAULT;
2134 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2135 goto out;
2136 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2137 cpuid_arg->entries);
674eea0f
AK		 2138 if (r)
2139 goto out;
2140
2141 r = -EFAULT;
2142 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2143 goto out;
2144 r = 0;
2145 break;
2146 }
890ca9ae
HY		 2147 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2148 u64 mce_cap;
2149
2150 mce_cap = KVM_MCE_CAP_SUPPORTED;
2151 r = -EFAULT;
2152 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2153 goto out;
2154 r = 0;
2155 break;
2156 }
043405e1
CO		 2157 default:
2158 r = -EINVAL;
2159 }
2160out:
2161 return r;
2162}
2163
f5f48ee1
SY		 2164static void wbinvd_ipi(void *garbage)
2165{
2166 wbinvd();
2167}
2168
2169static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2170{
2171 return vcpu->kvm->arch.iommu_domain &&
2172 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2173}
2174
313a3dc7
CO		 2175void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2176{
f5f48ee1
SY		 2177 /* Address WBINVD may be executed by guest */
2178 if (need_emulate_wbinvd(vcpu)) {
2179 if (kvm_x86_ops->has_wbinvd_exit())
2180 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2181 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2182 smp_call_function_single(vcpu->cpu,
2183 wbinvd_ipi, NULL, 1);
2184 }
2185
313a3dc7 2186 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2187 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa 2188 /* Make sure TSC doesn't go backwards */
8f6055cb
JR		 2189 s64 tsc_delta;
2190 u64 tsc;
2191
d5c1785d 2192 tsc = kvm_x86_ops->read_l1_tsc(vcpu);
8f6055cb
JR		 2193 tsc_delta = !vcpu->arch.last_guest_tsc ? 0 :
2194 tsc - vcpu->arch.last_guest_tsc;
2195
e48672fa
ZA		 2196 if (tsc_delta < 0)
2197 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2198 if (check_tsc_unstable()) {
e48672fa 2199 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
c285545f 2200 vcpu->arch.tsc_catchup = 1;
c285545f 2201 }
1aa8ceef 2202 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2203 if (vcpu->cpu != cpu)
2204 kvm_migrate_timers(vcpu);
e48672fa 2205 vcpu->cpu = cpu;
6b7d7e76 2206 }
c9aaa895
GC		 2207
2208 accumulate_steal_time(vcpu);
2209 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2210}
2211
2212void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2213{
02daab21 2214 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2215 kvm_put_guest_fpu(vcpu);
d5c1785d 2216 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
313a3dc7
CO		 2217}
2218
313a3dc7
CO		 2219static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2220 struct kvm_lapic_state *s)
2221{
ad312c7c 2222 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2223
2224 return 0;
2225}
2226
2227static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2228 struct kvm_lapic_state *s)
2229{
ad312c7c 2230 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2231 kvm_apic_post_state_restore(vcpu);
cb142eb7 2232 update_cr8_intercept(vcpu);
313a3dc7
CO		 2233
2234 return 0;
2235}
2236
f77bc6a4
ZX		 2237static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2238 struct kvm_interrupt *irq)
2239{
2240 if (irq->irq < 0 || irq->irq >= 256)
2241 return -EINVAL;
2242 if (irqchip_in_kernel(vcpu->kvm))
2243 return -ENXIO;
f77bc6a4 2244
66fd3f7f 2245 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2246 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2247
f77bc6a4
ZX		 2248 return 0;
2249}
2250
c4abb7c9
JK		 2251static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2252{
c4abb7c9 2253 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2254
2255 return 0;
2256}
2257
b209749f
AK		 2258static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2259 struct kvm_tpr_access_ctl *tac)
2260{
2261 if (tac->flags)
2262 return -EINVAL;
2263 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2264 return 0;
2265}
2266
890ca9ae
HY		 2267static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2268 u64 mcg_cap)
2269{
2270 int r;
2271 unsigned bank_num = mcg_cap & 0xff, bank;
2272
2273 r = -EINVAL;
a9e38c3e 2274 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2275 goto out;
2276 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2277 goto out;
2278 r = 0;
2279 vcpu->arch.mcg_cap = mcg_cap;
2280 /* Init IA32_MCG_CTL to all 1s */
2281 if (mcg_cap & MCG_CTL_P)
2282 vcpu->arch.mcg_ctl = ~(u64)0;
2283 /* Init IA32_MCi_CTL to all 1s */
2284 for (bank = 0; bank < bank_num; bank++)
2285 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2286out:
2287 return r;
2288}
2289
2290static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2291 struct kvm_x86_mce *mce)
2292{
2293 u64 mcg_cap = vcpu->arch.mcg_cap;
2294 unsigned bank_num = mcg_cap & 0xff;
2295 u64 *banks = vcpu->arch.mce_banks;
2296
2297 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2298 return -EINVAL;
2299 /*
2300 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2301 * reporting is disabled
2302 */
2303 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2304 vcpu->arch.mcg_ctl != ~(u64)0)
2305 return 0;
2306 banks += 4 * mce->bank;
2307 /*
2308 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2309 * reporting is disabled for the bank
2310 */
2311 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2312 return 0;
2313 if (mce->status & MCI_STATUS_UC) {
2314 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2315 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2316 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2317 return 0;
2318 }
2319 if (banks[1] & MCI_STATUS_VAL)
2320 mce->status |= MCI_STATUS_OVER;
2321 banks[2] = mce->addr;
2322 banks[3] = mce->misc;
2323 vcpu->arch.mcg_status = mce->mcg_status;
2324 banks[1] = mce->status;
2325 kvm_queue_exception(vcpu, MC_VECTOR);
2326 } else if (!(banks[1] & MCI_STATUS_VAL)
2327 || !(banks[1] & MCI_STATUS_UC)) {
2328 if (banks[1] & MCI_STATUS_VAL)
2329 mce->status |= MCI_STATUS_OVER;
2330 banks[2] = mce->addr;
2331 banks[3] = mce->misc;
2332 banks[1] = mce->status;
2333 } else
2334 banks[1] |= MCI_STATUS_OVER;
2335 return 0;
2336}
2337
3cfc3092
JK		 2338static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2339 struct kvm_vcpu_events *events)
2340{
7460fb4a 2341 process_nmi(vcpu);
03b82a30
JK		 2342 events->exception.injected =
2343 vcpu->arch.exception.pending &&
2344 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2345 events->exception.nr = vcpu->arch.exception.nr;
2346 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2347 events->exception.pad = 0;
3cfc3092
JK		 2348 events->exception.error_code = vcpu->arch.exception.error_code;
2349
03b82a30
JK		 2350 events->interrupt.injected =
2351 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2352 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2353 events->interrupt.soft = 0;
48005f64
JK		 2354 events->interrupt.shadow =
2355 kvm_x86_ops->get_interrupt_shadow(vcpu,
2356 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2357
2358 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2359 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2360 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2361 events->nmi.pad = 0;
3cfc3092
JK		 2362
2363 events->sipi_vector = vcpu->arch.sipi_vector;
2364
dab4b911 2365 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2366 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2367 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2368 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2369}
2370
2371static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2372 struct kvm_vcpu_events *events)
2373{
dab4b911 2374 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2375 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2376 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2377 return -EINVAL;
2378
7460fb4a 2379 process_nmi(vcpu);
3cfc3092
JK		 2380 vcpu->arch.exception.pending = events->exception.injected;
2381 vcpu->arch.exception.nr = events->exception.nr;
2382 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2383 vcpu->arch.exception.error_code = events->exception.error_code;
2384
2385 vcpu->arch.interrupt.pending = events->interrupt.injected;
2386 vcpu->arch.interrupt.nr = events->interrupt.nr;
2387 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2388 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2389 kvm_x86_ops->set_interrupt_shadow(vcpu,
2390 events->interrupt.shadow);
3cfc3092
JK		 2391
2392 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2393 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2394 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2395 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2396
dab4b911
JK		 2397 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2398 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2399
3842d135
AK		 2400 kvm_make_request(KVM_REQ_EVENT, vcpu);
2401
3cfc3092
JK		 2402 return 0;
2403}
2404
a1efbe77
JK		 2405static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2406 struct kvm_debugregs *dbgregs)
2407{
a1efbe77
JK		 2408 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2409 dbgregs->dr6 = vcpu->arch.dr6;
2410 dbgregs->dr7 = vcpu->arch.dr7;
2411 dbgregs->flags = 0;
97e69aa6 2412 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2413}
2414
2415static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2416 struct kvm_debugregs *dbgregs)
2417{
2418 if (dbgregs->flags)
2419 return -EINVAL;
2420
a1efbe77
JK		 2421 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2422 vcpu->arch.dr6 = dbgregs->dr6;
2423 vcpu->arch.dr7 = dbgregs->dr7;
2424
a1efbe77
JK		 2425 return 0;
2426}
2427
2d5b5a66
SY		 2428static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2429 struct kvm_xsave *guest_xsave)
2430{
2431 if (cpu_has_xsave)
2432 memcpy(guest_xsave->region,
2433 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2434 xstate_size);
2d5b5a66
SY		 2435 else {
2436 memcpy(guest_xsave->region,
2437 &vcpu->arch.guest_fpu.state->fxsave,
2438 sizeof(struct i387_fxsave_struct));
2439 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2440 XSTATE_FPSSE;
2441 }
2442}
2443
2444static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2445 struct kvm_xsave *guest_xsave)
2446{
2447 u64 xstate_bv =
2448 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2449
2450 if (cpu_has_xsave)
2451 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2452 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2453 else {
2454 if (xstate_bv & ~XSTATE_FPSSE)
2455 return -EINVAL;
2456 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2457 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2458 }
2459 return 0;
2460}
2461
2462static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2463 struct kvm_xcrs *guest_xcrs)
2464{
2465 if (!cpu_has_xsave) {
2466 guest_xcrs->nr_xcrs = 0;
2467 return;
2468 }
2469
2470 guest_xcrs->nr_xcrs = 1;
2471 guest_xcrs->flags = 0;
2472 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2473 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2474}
2475
2476static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2477 struct kvm_xcrs *guest_xcrs)
2478{
2479 int i, r = 0;
2480
2481 if (!cpu_has_xsave)
2482 return -EINVAL;
2483
2484 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2485 return -EINVAL;
2486
2487 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2488 /* Only support XCR0 currently */
2489 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2490 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2491 guest_xcrs->xcrs[0].value);
2492 break;
2493 }
2494 if (r)
2495 r = -EINVAL;
2496 return r;
2497}
2498
313a3dc7
CO		 2499long kvm_arch_vcpu_ioctl(struct file *filp,
2500 unsigned int ioctl, unsigned long arg)
2501{
2502 struct kvm_vcpu *vcpu = filp->private_data;
2503 void __user *argp = (void __user *)arg;
2504 int r;
d1ac91d8
AK		 2505 union {
2506 struct kvm_lapic_state *lapic;
2507 struct kvm_xsave *xsave;
2508 struct kvm_xcrs *xcrs;
2509 void *buffer;
2510 } u;
2511
2512 u.buffer = NULL;
313a3dc7
CO		 2513 switch (ioctl) {
2514 case KVM_GET_LAPIC: {
2204ae3c
MT		 2515 r = -EINVAL;
2516 if (!vcpu->arch.apic)
2517 goto out;
d1ac91d8 2518 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2519
b772ff36 2520 r = -ENOMEM;
d1ac91d8 2521 if (!u.lapic)
b772ff36 2522 goto out;
d1ac91d8 2523 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2524 if (r)
2525 goto out;
2526 r = -EFAULT;
d1ac91d8 2527 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2528 goto out;
2529 r = 0;
2530 break;
2531 }
2532 case KVM_SET_LAPIC: {
2204ae3c
MT		 2533 r = -EINVAL;
2534 if (!vcpu->arch.apic)
2535 goto out;
d1ac91d8 2536 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2537 r = -ENOMEM;
d1ac91d8 2538 if (!u.lapic)
b772ff36 2539 goto out;
313a3dc7 2540 r = -EFAULT;
d1ac91d8 2541 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2542 goto out;
d1ac91d8 2543 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2544 if (r)
2545 goto out;
2546 r = 0;
2547 break;
2548 }
f77bc6a4
ZX		 2549 case KVM_INTERRUPT: {
2550 struct kvm_interrupt irq;
2551
2552 r = -EFAULT;
2553 if (copy_from_user(&irq, argp, sizeof irq))
2554 goto out;
2555 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2556 if (r)
2557 goto out;
2558 r = 0;
2559 break;
2560 }
c4abb7c9
JK		 2561 case KVM_NMI: {
2562 r = kvm_vcpu_ioctl_nmi(vcpu);
2563 if (r)
2564 goto out;
2565 r = 0;
2566 break;
2567 }
313a3dc7
CO		 2568 case KVM_SET_CPUID: {
2569 struct kvm_cpuid __user *cpuid_arg = argp;
2570 struct kvm_cpuid cpuid;
2571
2572 r = -EFAULT;
2573 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2574 goto out;
2575 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2576 if (r)
2577 goto out;
2578 break;
2579 }
07716717
DK		 2580 case KVM_SET_CPUID2: {
2581 struct kvm_cpuid2 __user *cpuid_arg = argp;
2582 struct kvm_cpuid2 cpuid;
2583
2584 r = -EFAULT;
2585 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2586 goto out;
2587 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2588 cpuid_arg->entries);
07716717
DK		 2589 if (r)
2590 goto out;
2591 break;
2592 }
2593 case KVM_GET_CPUID2: {
2594 struct kvm_cpuid2 __user *cpuid_arg = argp;
2595 struct kvm_cpuid2 cpuid;
2596
2597 r = -EFAULT;
2598 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2599 goto out;
2600 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2601 cpuid_arg->entries);
07716717
DK		 2602 if (r)
2603 goto out;
2604 r = -EFAULT;
2605 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2606 goto out;
2607 r = 0;
2608 break;
2609 }
313a3dc7
CO		 2610 case KVM_GET_MSRS:
2611 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2612 break;
2613 case KVM_SET_MSRS:
2614 r = msr_io(vcpu, argp, do_set_msr, 0);
2615 break;
b209749f
AK		 2616 case KVM_TPR_ACCESS_REPORTING: {
2617 struct kvm_tpr_access_ctl tac;
2618
2619 r = -EFAULT;
2620 if (copy_from_user(&tac, argp, sizeof tac))
2621 goto out;
2622 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2623 if (r)
2624 goto out;
2625 r = -EFAULT;
2626 if (copy_to_user(argp, &tac, sizeof tac))
2627 goto out;
2628 r = 0;
2629 break;
2630 };
b93463aa
AK		 2631 case KVM_SET_VAPIC_ADDR: {
2632 struct kvm_vapic_addr va;
2633
2634 r = -EINVAL;
2635 if (!irqchip_in_kernel(vcpu->kvm))
2636 goto out;
2637 r = -EFAULT;
2638 if (copy_from_user(&va, argp, sizeof va))
2639 goto out;
2640 r = 0;
2641 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2642 break;
2643 }
890ca9ae
HY		 2644 case KVM_X86_SETUP_MCE: {
2645 u64 mcg_cap;
2646
2647 r = -EFAULT;
2648 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2649 goto out;
2650 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2651 break;
2652 }
2653 case KVM_X86_SET_MCE: {
2654 struct kvm_x86_mce mce;
2655
2656 r = -EFAULT;
2657 if (copy_from_user(&mce, argp, sizeof mce))
2658 goto out;
2659 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2660 break;
2661 }
3cfc3092
JK		 2662 case KVM_GET_VCPU_EVENTS: {
2663 struct kvm_vcpu_events events;
2664
2665 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2666
2667 r = -EFAULT;
2668 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2669 break;
2670 r = 0;
2671 break;
2672 }
2673 case KVM_SET_VCPU_EVENTS: {
2674 struct kvm_vcpu_events events;
2675
2676 r = -EFAULT;
2677 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2678 break;
2679
2680 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2681 break;
2682 }
a1efbe77
JK		 2683 case KVM_GET_DEBUGREGS: {
2684 struct kvm_debugregs dbgregs;
2685
2686 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2687
2688 r = -EFAULT;
2689 if (copy_to_user(argp, &dbgregs,
2690 sizeof(struct kvm_debugregs)))
2691 break;
2692 r = 0;
2693 break;
2694 }
2695 case KVM_SET_DEBUGREGS: {
2696 struct kvm_debugregs dbgregs;
2697
2698 r = -EFAULT;
2699 if (copy_from_user(&dbgregs, argp,
2700 sizeof(struct kvm_debugregs)))
2701 break;
2702
2703 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2704 break;
2705 }
2d5b5a66 2706 case KVM_GET_XSAVE: {
d1ac91d8 2707 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2708 r = -ENOMEM;
d1ac91d8 2709 if (!u.xsave)
2d5b5a66
SY		 2710 break;
2711
d1ac91d8 2712 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2713
2714 r = -EFAULT;
d1ac91d8 2715 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2716 break;
2717 r = 0;
2718 break;
2719 }
2720 case KVM_SET_XSAVE: {
d1ac91d8 2721 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2722 r = -ENOMEM;
d1ac91d8 2723 if (!u.xsave)
2d5b5a66
SY		 2724 break;
2725
2726 r = -EFAULT;
d1ac91d8 2727 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2728 break;
2729
d1ac91d8 2730 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2731 break;
2732 }
2733 case KVM_GET_XCRS: {
d1ac91d8 2734 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2735 r = -ENOMEM;
d1ac91d8 2736 if (!u.xcrs)
2d5b5a66
SY		 2737 break;
2738
d1ac91d8 2739 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2740
2741 r = -EFAULT;
d1ac91d8 2742 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2743 sizeof(struct kvm_xcrs)))
2744 break;
2745 r = 0;
2746 break;
2747 }
2748 case KVM_SET_XCRS: {
d1ac91d8 2749 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2750 r = -ENOMEM;
d1ac91d8 2751 if (!u.xcrs)
2d5b5a66
SY		 2752 break;
2753
2754 r = -EFAULT;
d1ac91d8 2755 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 2756 sizeof(struct kvm_xcrs)))
2757 break;
2758
d1ac91d8 2759 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2760 break;
2761 }
92a1f12d
JR		 2762 case KVM_SET_TSC_KHZ: {
2763 u32 user_tsc_khz;
2764
2765 r = -EINVAL;
2766 if (!kvm_has_tsc_control)
2767 break;
2768
2769 user_tsc_khz = (u32)arg;
2770
2771 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
2772 goto out;
2773
2774 kvm_x86_ops->set_tsc_khz(vcpu, user_tsc_khz);
2775
2776 r = 0;
2777 goto out;
2778 }
2779 case KVM_GET_TSC_KHZ: {
2780 r = -EIO;
2781 if (check_tsc_unstable())
2782 goto out;
2783
2784 r = vcpu_tsc_khz(vcpu);
2785
2786 goto out;
2787 }
313a3dc7
CO		 2788 default:
2789 r = -EINVAL;
2790 }
2791out:
d1ac91d8 2792 kfree(u.buffer);
313a3dc7
CO		 2793 return r;
2794}
2795
1fe779f8
CO		 2796static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2797{
2798 int ret;
2799
2800 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2801 return -1;
2802 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2803 return ret;
2804}
2805
b927a3ce
SY		 2806static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2807 u64 ident_addr)
2808{
2809 kvm->arch.ept_identity_map_addr = ident_addr;
2810 return 0;
2811}
2812
1fe779f8
CO		 2813static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2814 u32 kvm_nr_mmu_pages)
2815{
2816 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2817 return -EINVAL;
2818
79fac95e 2819 mutex_lock(&kvm->slots_lock);
7c8a83b7 2820 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2821
2822 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2823 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2824
7c8a83b7 2825 spin_unlock(&kvm->mmu_lock);
79fac95e 2826 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2827 return 0;
2828}
2829
2830static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2831{
39de71ec 2832 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 2833}
2834
1fe779f8
CO		 2835static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2836{
2837 int r;
2838
2839 r = 0;
2840 switch (chip->chip_id) {
2841 case KVM_IRQCHIP_PIC_MASTER:
2842 memcpy(&chip->chip.pic,
2843 &pic_irqchip(kvm)->pics[0],
2844 sizeof(struct kvm_pic_state));
2845 break;
2846 case KVM_IRQCHIP_PIC_SLAVE:
2847 memcpy(&chip->chip.pic,
2848 &pic_irqchip(kvm)->pics[1],
2849 sizeof(struct kvm_pic_state));
2850 break;
2851 case KVM_IRQCHIP_IOAPIC:
eba0226b 2852 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2853 break;
2854 default:
2855 r = -EINVAL;
2856 break;
2857 }
2858 return r;
2859}
2860
2861static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2862{
2863 int r;
2864
2865 r = 0;
2866 switch (chip->chip_id) {
2867 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 2868 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2869 memcpy(&pic_irqchip(kvm)->pics[0],
2870 &chip->chip.pic,
2871 sizeof(struct kvm_pic_state));
f4f51050 2872 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2873 break;
2874 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 2875 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2876 memcpy(&pic_irqchip(kvm)->pics[1],
2877 &chip->chip.pic,
2878 sizeof(struct kvm_pic_state));
f4f51050 2879 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2880 break;
2881 case KVM_IRQCHIP_IOAPIC:
eba0226b 2882 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2883 break;
2884 default:
2885 r = -EINVAL;
2886 break;
2887 }
2888 kvm_pic_update_irq(pic_irqchip(kvm));
2889 return r;
2890}
2891
e0f63cb9
SY		 2892static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2893{
2894 int r = 0;
2895
894a9c55 2896 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2897 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2898 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2899 return r;
2900}
2901
2902static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2903{
2904 int r = 0;
2905
894a9c55 2906 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2907 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2908 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2909 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2910 return r;
2911}
2912
2913static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2914{
2915 int r = 0;
2916
2917 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2918 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2919 sizeof(ps->channels));
2920 ps->flags = kvm->arch.vpit->pit_state.flags;
2921 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 2922 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 2923 return r;
2924}
2925
2926static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2927{
2928 int r = 0, start = 0;
2929 u32 prev_legacy, cur_legacy;
2930 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2931 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2932 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2933 if (!prev_legacy && cur_legacy)
2934 start = 1;
2935 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2936 sizeof(kvm->arch.vpit->pit_state.channels));
2937 kvm->arch.vpit->pit_state.flags = ps->flags;
2938 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2939 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2940 return r;
2941}
2942
52d939a0
MT		 2943static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2944 struct kvm_reinject_control *control)
2945{
2946 if (!kvm->arch.vpit)
2947 return -ENXIO;
894a9c55 2948 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2949 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2950 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2951 return 0;
2952}
2953
95d4c16c
TY		 2954/**
2955 * write_protect_slot - write protect a slot for dirty logging
2956 * @kvm: the kvm instance
2957 * @memslot: the slot we protect
2958 * @dirty_bitmap: the bitmap indicating which pages are dirty
2959 * @nr_dirty_pages: the number of dirty pages
2960 *
2961 * We have two ways to find all sptes to protect:
2962 * 1. Use kvm_mmu_slot_remove_write_access() which walks all shadow pages and
2963 * checks ones that have a spte mapping a page in the slot.
2964 * 2. Use kvm_mmu_rmap_write_protect() for each gfn found in the bitmap.
2965 *
2966 * Generally speaking, if there are not so many dirty pages compared to the
2967 * number of shadow pages, we should use the latter.
2968 *
2969 * Note that letting others write into a page marked dirty in the old bitmap
2970 * by using the remaining tlb entry is not a problem. That page will become
2971 * write protected again when we flush the tlb and then be reported dirty to
2972 * the user space by copying the old bitmap.
2973 */
2974static void write_protect_slot(struct kvm *kvm,
2975 struct kvm_memory_slot *memslot,
2976 unsigned long *dirty_bitmap,
2977 unsigned long nr_dirty_pages)
2978{
2979 /* Not many dirty pages compared to # of shadow pages. */
2980 if (nr_dirty_pages < kvm->arch.n_used_mmu_pages) {
2981 unsigned long gfn_offset;
2982
2983 for_each_set_bit(gfn_offset, dirty_bitmap, memslot->npages) {
2984 unsigned long gfn = memslot->base_gfn + gfn_offset;
2985
2986 spin_lock(&kvm->mmu_lock);
2987 kvm_mmu_rmap_write_protect(kvm, gfn, memslot);
2988 spin_unlock(&kvm->mmu_lock);
2989 }
2990 kvm_flush_remote_tlbs(kvm);
2991 } else {
2992 spin_lock(&kvm->mmu_lock);
2993 kvm_mmu_slot_remove_write_access(kvm, memslot->id);
2994 spin_unlock(&kvm->mmu_lock);
2995 }
2996}
2997
5bb064dc
ZX		 2998/*
2999 * Get (and clear) the dirty memory log for a memory slot.
3000 */
3001int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3002 struct kvm_dirty_log *log)
3003{
7850ac54 3004 int r;
5bb064dc 3005 struct kvm_memory_slot *memslot;
95d4c16c 3006 unsigned long n, nr_dirty_pages;
5bb064dc 3007
79fac95e 3008 mutex_lock(&kvm->slots_lock);
5bb064dc 3009
b050b015
MT		 3010 r = -EINVAL;
3011 if (log->slot >= KVM_MEMORY_SLOTS)
3012 goto out;
3013
28a37544 3014 memslot = id_to_memslot(kvm->memslots, log->slot);
b050b015
MT		 3015 r = -ENOENT;
3016 if (!memslot->dirty_bitmap)
3017 goto out;
3018
87bf6e7d 3019 n = kvm_dirty_bitmap_bytes(memslot);
95d4c16c 3020 nr_dirty_pages = memslot->nr_dirty_pages;
b050b015 3021
5bb064dc 3022 /* If nothing is dirty, don't bother messing with page tables. */
95d4c16c 3023 if (nr_dirty_pages) {
b050b015 3024 struct kvm_memslots *slots, *old_slots;
28a37544 3025 unsigned long *dirty_bitmap, *dirty_bitmap_head;
b050b015 3026
28a37544
XG		 3027 dirty_bitmap = memslot->dirty_bitmap;
3028 dirty_bitmap_head = memslot->dirty_bitmap_head;
3029 if (dirty_bitmap == dirty_bitmap_head)
3030 dirty_bitmap_head += n / sizeof(long);
3031 memset(dirty_bitmap_head, 0, n);
b050b015 3032
914ebccd 3033 r = -ENOMEM;
cdfca7b3 3034 slots = kmemdup(kvm->memslots, sizeof(*kvm->memslots), GFP_KERNEL);
515a0127 3035 if (!slots)
914ebccd 3036 goto out;
cdfca7b3 3037
28a37544 3038 memslot = id_to_memslot(slots, log->slot);
95d4c16c 3039 memslot->nr_dirty_pages = 0;
28a37544 3040 memslot->dirty_bitmap = dirty_bitmap_head;
be593d62 3041 update_memslots(slots, NULL);
b050b015
MT		 3042
3043 old_slots = kvm->memslots;
3044 rcu_assign_pointer(kvm->memslots, slots);
3045 synchronize_srcu_expedited(&kvm->srcu);
b050b015 3046 kfree(old_slots);
914ebccd 3047
95d4c16c 3048 write_protect_slot(kvm, memslot, dirty_bitmap, nr_dirty_pages);
edde99ce 3049
914ebccd 3050 r = -EFAULT;
515a0127 3051 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
914ebccd 3052 goto out;
914ebccd
TY		 3053 } else {
3054 r = -EFAULT;
3055 if (clear_user(log->dirty_bitmap, n))
3056 goto out;
5bb064dc 3057 }
b050b015 3058
5bb064dc
ZX		 3059 r = 0;
3060out:
79fac95e 3061 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3062 return r;
3063}
3064
1fe779f8
CO		 3065long kvm_arch_vm_ioctl(struct file *filp,
3066 unsigned int ioctl, unsigned long arg)
3067{
3068 struct kvm *kvm = filp->private_data;
3069 void __user *argp = (void __user *)arg;
367e1319 3070 int r = -ENOTTY;
f0d66275
DH		 3071 /*
3072 * This union makes it completely explicit to gcc-3.x
3073 * that these two variables' stack usage should be
3074 * combined, not added together.
3075 */
3076 union {
3077 struct kvm_pit_state ps;
e9f42757 3078 struct kvm_pit_state2 ps2;
c5ff41ce 3079 struct kvm_pit_config pit_config;
f0d66275 3080 } u;
1fe779f8
CO		 3081
3082 switch (ioctl) {
3083 case KVM_SET_TSS_ADDR:
3084 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3085 if (r < 0)
3086 goto out;
3087 break;
b927a3ce
SY		 3088 case KVM_SET_IDENTITY_MAP_ADDR: {
3089 u64 ident_addr;
3090
3091 r = -EFAULT;
3092 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3093 goto out;
3094 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3095 if (r < 0)
3096 goto out;
3097 break;
3098 }
1fe779f8
CO		 3099 case KVM_SET_NR_MMU_PAGES:
3100 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3101 if (r)
3102 goto out;
3103 break;
3104 case KVM_GET_NR_MMU_PAGES:
3105 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3106 break;
3ddea128
MT		 3107 case KVM_CREATE_IRQCHIP: {
3108 struct kvm_pic *vpic;
3109
3110 mutex_lock(&kvm->lock);
3111 r = -EEXIST;
3112 if (kvm->arch.vpic)
3113 goto create_irqchip_unlock;
1fe779f8 3114 r = -ENOMEM;
3ddea128
MT		 3115 vpic = kvm_create_pic(kvm);
3116 if (vpic) {
1fe779f8
CO		 3117 r = kvm_ioapic_init(kvm);
3118 if (r) {
175504cd 3119 mutex_lock(&kvm->slots_lock);
72bb2fcd 3120 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3121 &vpic->dev_master);
3122 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3123 &vpic->dev_slave);
3124 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3125 &vpic->dev_eclr);
175504cd 3126 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3127 kfree(vpic);
3128 goto create_irqchip_unlock;
1fe779f8
CO		 3129 }
3130 } else
3ddea128
MT		 3131 goto create_irqchip_unlock;
3132 smp_wmb();
3133 kvm->arch.vpic = vpic;
3134 smp_wmb();
399ec807
AK		 3135 r = kvm_setup_default_irq_routing(kvm);
3136 if (r) {
175504cd 3137 mutex_lock(&kvm->slots_lock);
3ddea128 3138 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3139 kvm_ioapic_destroy(kvm);
3140 kvm_destroy_pic(kvm);
3ddea128 3141 mutex_unlock(&kvm->irq_lock);
175504cd 3142 mutex_unlock(&kvm->slots_lock);
399ec807 3143 }
3ddea128
MT		 3144 create_irqchip_unlock:
3145 mutex_unlock(&kvm->lock);
1fe779f8 3146 break;
3ddea128 3147 }
7837699f 3148 case KVM_CREATE_PIT:
c5ff41ce
JK		 3149 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3150 goto create_pit;
3151 case KVM_CREATE_PIT2:
3152 r = -EFAULT;
3153 if (copy_from_user(&u.pit_config, argp,
3154 sizeof(struct kvm_pit_config)))
3155 goto out;
3156 create_pit:
79fac95e 3157 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3158 r = -EEXIST;
3159 if (kvm->arch.vpit)
3160 goto create_pit_unlock;
7837699f 3161 r = -ENOMEM;
c5ff41ce 3162 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3163 if (kvm->arch.vpit)
3164 r = 0;
269e05e4 3165 create_pit_unlock:
79fac95e 3166 mutex_unlock(&kvm->slots_lock);
7837699f 3167 break;
4925663a 3168 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3169 case KVM_IRQ_LINE: {
3170 struct kvm_irq_level irq_event;
3171
3172 r = -EFAULT;
3173 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3174 goto out;
160d2f6c 3175 r = -ENXIO;
1fe779f8 3176 if (irqchip_in_kernel(kvm)) {
4925663a 3177 __s32 status;
4925663a
GN		 3178 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3179 irq_event.irq, irq_event.level);
4925663a 3180 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3181 r = -EFAULT;
4925663a
GN		 3182 irq_event.status = status;
3183 if (copy_to_user(argp, &irq_event,
3184 sizeof irq_event))
3185 goto out;
3186 }
1fe779f8
CO		 3187 r = 0;
3188 }
3189 break;
3190 }
3191 case KVM_GET_IRQCHIP: {
3192 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3193 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3194
f0d66275
DH		 3195 r = -ENOMEM;
3196 if (!chip)
1fe779f8 3197 goto out;
f0d66275
DH		 3198 r = -EFAULT;
3199 if (copy_from_user(chip, argp, sizeof *chip))
3200 goto get_irqchip_out;
1fe779f8
CO		 3201 r = -ENXIO;
3202 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3203 goto get_irqchip_out;
3204 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3205 if (r)
f0d66275 3206 goto get_irqchip_out;
1fe779f8 3207 r = -EFAULT;
f0d66275
DH		 3208 if (copy_to_user(argp, chip, sizeof *chip))
3209 goto get_irqchip_out;
1fe779f8 3210 r = 0;
f0d66275
DH		 3211 get_irqchip_out:
3212 kfree(chip);
3213 if (r)
3214 goto out;
1fe779f8
CO		 3215 break;
3216 }
3217 case KVM_SET_IRQCHIP: {
3218 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3219 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3220
f0d66275
DH		 3221 r = -ENOMEM;
3222 if (!chip)
1fe779f8 3223 goto out;
f0d66275
DH		 3224 r = -EFAULT;
3225 if (copy_from_user(chip, argp, sizeof *chip))
3226 goto set_irqchip_out;
1fe779f8
CO		 3227 r = -ENXIO;
3228 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3229 goto set_irqchip_out;
3230 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3231 if (r)
f0d66275 3232 goto set_irqchip_out;
1fe779f8 3233 r = 0;
f0d66275
DH		 3234 set_irqchip_out:
3235 kfree(chip);
3236 if (r)
3237 goto out;
1fe779f8
CO		 3238 break;
3239 }
e0f63cb9 3240 case KVM_GET_PIT: {
e0f63cb9 3241 r = -EFAULT;
f0d66275 3242 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3243 goto out;
3244 r = -ENXIO;
3245 if (!kvm->arch.vpit)
3246 goto out;
f0d66275 3247 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3248 if (r)
3249 goto out;
3250 r = -EFAULT;
f0d66275 3251 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3252 goto out;
3253 r = 0;
3254 break;
3255 }
3256 case KVM_SET_PIT: {
e0f63cb9 3257 r = -EFAULT;
f0d66275 3258 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3259 goto out;
3260 r = -ENXIO;
3261 if (!kvm->arch.vpit)
3262 goto out;
f0d66275 3263 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3264 if (r)
3265 goto out;
3266 r = 0;
3267 break;
3268 }
e9f42757
BK		 3269 case KVM_GET_PIT2: {
3270 r = -ENXIO;
3271 if (!kvm->arch.vpit)
3272 goto out;
3273 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3274 if (r)
3275 goto out;
3276 r = -EFAULT;
3277 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3278 goto out;
3279 r = 0;
3280 break;
3281 }
3282 case KVM_SET_PIT2: {
3283 r = -EFAULT;
3284 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3285 goto out;
3286 r = -ENXIO;
3287 if (!kvm->arch.vpit)
3288 goto out;
3289 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3290 if (r)
3291 goto out;
3292 r = 0;
3293 break;
3294 }
52d939a0
MT		 3295 case KVM_REINJECT_CONTROL: {
3296 struct kvm_reinject_control control;
3297 r = -EFAULT;
3298 if (copy_from_user(&control, argp, sizeof(control)))
3299 goto out;
3300 r = kvm_vm_ioctl_reinject(kvm, &control);
3301 if (r)
3302 goto out;
3303 r = 0;
3304 break;
3305 }
ffde22ac
ES		 3306 case KVM_XEN_HVM_CONFIG: {
3307 r = -EFAULT;
3308 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3309 sizeof(struct kvm_xen_hvm_config)))
3310 goto out;
3311 r = -EINVAL;
3312 if (kvm->arch.xen_hvm_config.flags)
3313 goto out;
3314 r = 0;
3315 break;
3316 }
afbcf7ab 3317 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3318 struct kvm_clock_data user_ns;
3319 u64 now_ns;
3320 s64 delta;
3321
3322 r = -EFAULT;
3323 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3324 goto out;
3325
3326 r = -EINVAL;
3327 if (user_ns.flags)
3328 goto out;
3329
3330 r = 0;
395c6b0a 3331 local_irq_disable();
759379dd 3332 now_ns = get_kernel_ns();
afbcf7ab 3333 delta = user_ns.clock - now_ns;
395c6b0a 3334 local_irq_enable();
afbcf7ab
GC		 3335 kvm->arch.kvmclock_offset = delta;
3336 break;
3337 }
3338 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3339 struct kvm_clock_data user_ns;
3340 u64 now_ns;
3341
395c6b0a 3342 local_irq_disable();
759379dd 3343 now_ns = get_kernel_ns();
afbcf7ab 3344 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3345 local_irq_enable();
afbcf7ab 3346 user_ns.flags = 0;
97e69aa6 3347 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3348
3349 r = -EFAULT;
3350 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3351 goto out;
3352 r = 0;
3353 break;
3354 }
3355
1fe779f8
CO		 3356 default:
3357 ;
3358 }
3359out:
3360 return r;
3361}
3362
a16b043c 3363static void kvm_init_msr_list(void)
043405e1
CO		 3364{
3365 u32 dummy[2];
3366 unsigned i, j;
3367
e3267cbb
GC		 3368 /* skip the first msrs in the list. KVM-specific */
3369 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3370 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3371 continue;
3372 if (j < i)
3373 msrs_to_save[j] = msrs_to_save[i];
3374 j++;
3375 }
3376 num_msrs_to_save = j;
3377}
3378
bda9020e
MT		 3379static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3380 const void *v)
bbd9b64e 3381{
70252a10
AK		 3382 int handled = 0;
3383 int n;
3384
3385 do {
3386 n = min(len, 8);
3387 if (!(vcpu->arch.apic &&
3388 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3389 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3390 break;
3391 handled += n;
3392 addr += n;
3393 len -= n;
3394 v += n;
3395 } while (len);
bbd9b64e 3396
70252a10 3397 return handled;
bbd9b64e
CO		 3398}
3399
bda9020e 3400static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3401{
70252a10
AK		 3402 int handled = 0;
3403 int n;
3404
3405 do {
3406 n = min(len, 8);
3407 if (!(vcpu->arch.apic &&
3408 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3409 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3410 break;
3411 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3412 handled += n;
3413 addr += n;
3414 len -= n;
3415 v += n;
3416 } while (len);
bbd9b64e 3417
70252a10 3418 return handled;
bbd9b64e
CO		 3419}
3420
2dafc6c2
GN		 3421static void kvm_set_segment(struct kvm_vcpu *vcpu,
3422 struct kvm_segment *var, int seg)
3423{
3424 kvm_x86_ops->set_segment(vcpu, var, seg);
3425}
3426
3427void kvm_get_segment(struct kvm_vcpu *vcpu,
3428 struct kvm_segment *var, int seg)
3429{
3430 kvm_x86_ops->get_segment(vcpu, var, seg);
3431}
3432
e459e322 3433gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3434{
3435 gpa_t t_gpa;
ab9ae313 3436 struct x86_exception exception;
02f59dc9
JR		 3437
3438 BUG_ON(!mmu_is_nested(vcpu));
3439
3440 /* NPT walks are always user-walks */
3441 access |= PFERR_USER_MASK;
ab9ae313 3442 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3443
3444 return t_gpa;
3445}
3446
ab9ae313
AK		 3447gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3448 struct x86_exception *exception)
1871c602
GN		 3449{
3450 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3451 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3452}
3453
ab9ae313
AK		 3454 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3455 struct x86_exception *exception)
1871c602
GN		 3456{
3457 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3458 access |= PFERR_FETCH_MASK;
ab9ae313 3459 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3460}
3461
ab9ae313
AK		 3462gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3463 struct x86_exception *exception)
1871c602
GN		 3464{
3465 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3466 access |= PFERR_WRITE_MASK;
ab9ae313 3467 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3468}
3469
3470/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3471gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3472 struct x86_exception *exception)
1871c602 3473{
ab9ae313 3474 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3475}
3476
3477static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3478 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3479 struct x86_exception *exception)
bbd9b64e
CO		 3480{
3481 void *data = val;
10589a46 3482 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3483
3484 while (bytes) {
14dfe855 3485 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3486 exception);
bbd9b64e 3487 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3488 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3489 int ret;
3490
bcc55cba 3491 if (gpa == UNMAPPED_GVA)
ab9ae313 3492 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3493 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3494 if (ret < 0) {
c3cd7ffa 3495 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3496 goto out;
3497 }
bbd9b64e 3498
77c2002e
IE		 3499 bytes -= toread;
3500 data += toread;
3501 addr += toread;
bbd9b64e 3502 }
10589a46 3503out:
10589a46 3504 return r;
bbd9b64e 3505}
77c2002e 3506
1871c602 3507/* used for instruction fetching */
0f65dd70
AK		 3508static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3509 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3510 struct x86_exception *exception)
1871c602 3511{
0f65dd70 3512 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3513 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3514
1871c602 3515 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3516 access | PFERR_FETCH_MASK,
3517 exception);
1871c602
GN		 3518}
3519
064aea77 3520int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3521 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3522 struct x86_exception *exception)
1871c602 3523{
0f65dd70 3524 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3525 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3526
1871c602 3527 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3528 exception);
1871c602 3529}
064aea77 3530EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 3531
0f65dd70
AK		 3532static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3533 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3534 struct x86_exception *exception)
1871c602 3535{
0f65dd70 3536 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 3537 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3538}
3539
6a4d7550 3540int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 3541 gva_t addr, void *val,
2dafc6c2 3542 unsigned int bytes,
bcc55cba 3543 struct x86_exception *exception)
77c2002e 3544{
0f65dd70 3545 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 3546 void *data = val;
3547 int r = X86EMUL_CONTINUE;
3548
3549 while (bytes) {
14dfe855
JR		 3550 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3551 PFERR_WRITE_MASK,
ab9ae313 3552 exception);
77c2002e
IE		 3553 unsigned offset = addr & (PAGE_SIZE-1);
3554 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3555 int ret;
3556
bcc55cba 3557 if (gpa == UNMAPPED_GVA)
ab9ae313 3558 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3559 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3560 if (ret < 0) {
c3cd7ffa 3561 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3562 goto out;
3563 }
3564
3565 bytes -= towrite;
3566 data += towrite;
3567 addr += towrite;
3568 }
3569out:
3570 return r;
3571}
6a4d7550 3572EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 3573
af7cc7d1
XG		 3574static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3575 gpa_t *gpa, struct x86_exception *exception,
3576 bool write)
3577{
3578 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3579
bebb106a
XG		 3580 if (vcpu_match_mmio_gva(vcpu, gva) &&
3581 check_write_user_access(vcpu, write, access,
3582 vcpu->arch.access)) {
3583 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3584 (gva & (PAGE_SIZE - 1));
4f022648 3585 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 3586 return 1;
3587 }
3588
af7cc7d1
XG		 3589 if (write)
3590 access |= PFERR_WRITE_MASK;
3591
3592 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3593
3594 if (*gpa == UNMAPPED_GVA)
3595 return -1;
3596
3597 /* For APIC access vmexit */
3598 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3599 return 1;
3600
4f022648
XG		 3601 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3602 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 3603 return 1;
4f022648 3604 }
bebb106a 3605
af7cc7d1
XG		 3606 return 0;
3607}
3608
3200f405 3609int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 3610 const void *val, int bytes)
bbd9b64e
CO		 3611{
3612 int ret;
3613
3614 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3615 if (ret < 0)
bbd9b64e 3616 return 0;
f57f2ef5 3617 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 3618 return 1;
3619}
3620
77d197b2
XG		 3621struct read_write_emulator_ops {
3622 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
3623 int bytes);
3624 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
3625 void *val, int bytes);
3626 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3627 int bytes, void *val);
3628 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3629 void *val, int bytes);
3630 bool write;
3631};
3632
3633static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
3634{
3635 if (vcpu->mmio_read_completed) {
3636 memcpy(val, vcpu->mmio_data, bytes);
3637 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3638 vcpu->mmio_phys_addr, *(u64 *)val);
3639 vcpu->mmio_read_completed = 0;
3640 return 1;
3641 }
3642
3643 return 0;
3644}
3645
3646static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3647 void *val, int bytes)
3648{
3649 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
3650}
3651
3652static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3653 void *val, int bytes)
3654{
3655 return emulator_write_phys(vcpu, gpa, val, bytes);
3656}
3657
3658static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
3659{
3660 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
3661 return vcpu_mmio_write(vcpu, gpa, bytes, val);
3662}
3663
3664static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3665 void *val, int bytes)
3666{
3667 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
3668 return X86EMUL_IO_NEEDED;
3669}
3670
3671static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3672 void *val, int bytes)
3673{
3674 memcpy(vcpu->mmio_data, val, bytes);
3675 memcpy(vcpu->run->mmio.data, vcpu->mmio_data, 8);
3676 return X86EMUL_CONTINUE;
3677}
3678
3679static struct read_write_emulator_ops read_emultor = {
3680 .read_write_prepare = read_prepare,
3681 .read_write_emulate = read_emulate,
3682 .read_write_mmio = vcpu_mmio_read,
3683 .read_write_exit_mmio = read_exit_mmio,
3684};
3685
3686static struct read_write_emulator_ops write_emultor = {
3687 .read_write_emulate = write_emulate,
3688 .read_write_mmio = write_mmio,
3689 .read_write_exit_mmio = write_exit_mmio,
3690 .write = true,
3691};
3692
22388a3c
XG		 3693static int emulator_read_write_onepage(unsigned long addr, void *val,
3694 unsigned int bytes,
3695 struct x86_exception *exception,
3696 struct kvm_vcpu *vcpu,
3697 struct read_write_emulator_ops *ops)
bbd9b64e 3698{
af7cc7d1
XG		 3699 gpa_t gpa;
3700 int handled, ret;
22388a3c
XG		 3701 bool write = ops->write;
3702
3703 if (ops->read_write_prepare &&
3704 ops->read_write_prepare(vcpu, val, bytes))
3705 return X86EMUL_CONTINUE;
10589a46 3706
22388a3c 3707 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 3708
af7cc7d1 3709 if (ret < 0)
bbd9b64e 3710 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3711
3712 /* For APIC access vmexit */
af7cc7d1 3713 if (ret)
bbd9b64e
CO		 3714 goto mmio;
3715
22388a3c 3716 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 3717 return X86EMUL_CONTINUE;
3718
3719mmio:
3720 /*
3721 * Is this MMIO handled locally?
3722 */
22388a3c 3723 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 3724 if (handled == bytes)
bbd9b64e 3725 return X86EMUL_CONTINUE;
bbd9b64e 3726
70252a10
AK		 3727 gpa += handled;
3728 bytes -= handled;
3729 val += handled;
3730
bbd9b64e 3731 vcpu->mmio_needed = 1;
411c35b7
GN		 3732 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3733 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
cef4dea0
AK		 3734 vcpu->mmio_size = bytes;
3735 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
22388a3c 3736 vcpu->run->mmio.is_write = vcpu->mmio_is_write = write;
cef4dea0 3737 vcpu->mmio_index = 0;
bbd9b64e 3738
22388a3c 3739 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
bbd9b64e
CO		 3740}
3741
22388a3c
XG		 3742int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
3743 void *val, unsigned int bytes,
3744 struct x86_exception *exception,
3745 struct read_write_emulator_ops *ops)
bbd9b64e 3746{
0f65dd70
AK		 3747 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3748
bbd9b64e
CO		 3749 /* Crossing a page boundary? */
3750 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3751 int rc, now;
3752
3753 now = -addr & ~PAGE_MASK;
22388a3c
XG		 3754 rc = emulator_read_write_onepage(addr, val, now, exception,
3755 vcpu, ops);
3756
bbd9b64e
CO		 3757 if (rc != X86EMUL_CONTINUE)
3758 return rc;
3759 addr += now;
3760 val += now;
3761 bytes -= now;
3762 }
22388a3c
XG		 3763
3764 return emulator_read_write_onepage(addr, val, bytes, exception,
3765 vcpu, ops);
3766}
3767
3768static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
3769 unsigned long addr,
3770 void *val,
3771 unsigned int bytes,
3772 struct x86_exception *exception)
3773{
3774 return emulator_read_write(ctxt, addr, val, bytes,
3775 exception, &read_emultor);
3776}
3777
3778int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
3779 unsigned long addr,
3780 const void *val,
3781 unsigned int bytes,
3782 struct x86_exception *exception)
3783{
3784 return emulator_read_write(ctxt, addr, (void *)val, bytes,
3785 exception, &write_emultor);
bbd9b64e 3786}
bbd9b64e 3787
daea3e73
AK		 3788#define CMPXCHG_TYPE(t, ptr, old, new) \
3789 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3790
3791#ifdef CONFIG_X86_64
3792# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3793#else
3794# define CMPXCHG64(ptr, old, new) \
9749a6c0 3795 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3796#endif
3797
0f65dd70
AK		 3798static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
3799 unsigned long addr,
bbd9b64e
CO		 3800 const void *old,
3801 const void *new,
3802 unsigned int bytes,
0f65dd70 3803 struct x86_exception *exception)
bbd9b64e 3804{
0f65dd70 3805 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 3806 gpa_t gpa;
3807 struct page *page;
3808 char *kaddr;
3809 bool exchanged;
2bacc55c 3810
daea3e73
AK		 3811 /* guests cmpxchg8b have to be emulated atomically */
3812 if (bytes > 8 || (bytes & (bytes - 1)))
3813 goto emul_write;
10589a46 3814
daea3e73 3815 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3816
daea3e73
AK		 3817 if (gpa == UNMAPPED_GVA ||
3818 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3819 goto emul_write;
2bacc55c 3820
daea3e73
AK		 3821 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3822 goto emul_write;
72dc67a6 3823
daea3e73 3824 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3825 if (is_error_page(page)) {
3826 kvm_release_page_clean(page);
3827 goto emul_write;
3828 }
72dc67a6 3829
daea3e73
AK		 3830 kaddr = kmap_atomic(page, KM_USER0);
3831 kaddr += offset_in_page(gpa);
3832 switch (bytes) {
3833 case 1:
3834 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3835 break;
3836 case 2:
3837 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3838 break;
3839 case 4:
3840 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3841 break;
3842 case 8:
3843 exchanged = CMPXCHG64(kaddr, old, new);
3844 break;
3845 default:
3846 BUG();
2bacc55c 3847 }
daea3e73
AK		 3848 kunmap_atomic(kaddr, KM_USER0);
3849 kvm_release_page_dirty(page);
3850
3851 if (!exchanged)
3852 return X86EMUL_CMPXCHG_FAILED;
3853
f57f2ef5 3854 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 3855
3856 return X86EMUL_CONTINUE;
4a5f48f6 3857
3200f405 3858emul_write:
daea3e73 3859 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3860
0f65dd70 3861 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 3862}
3863
cf8f70bf
GN		 3864static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3865{
3866 /* TODO: String I/O for in kernel device */
3867 int r;
3868
3869 if (vcpu->arch.pio.in)
3870 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3871 vcpu->arch.pio.size, pd);
3872 else
3873 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3874 vcpu->arch.pio.port, vcpu->arch.pio.size,
3875 pd);
3876 return r;
3877}
3878
6f6fbe98
XG		 3879static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
3880 unsigned short port, void *val,
3881 unsigned int count, bool in)
cf8f70bf 3882{
6f6fbe98 3883 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 3884
3885 vcpu->arch.pio.port = port;
6f6fbe98 3886 vcpu->arch.pio.in = in;
7972995b 3887 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3888 vcpu->arch.pio.size = size;
3889
3890 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3891 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3892 return 1;
3893 }
3894
3895 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 3896 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 3897 vcpu->run->io.size = size;
3898 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3899 vcpu->run->io.count = count;
3900 vcpu->run->io.port = port;
3901
3902 return 0;
3903}
3904
6f6fbe98
XG		 3905static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
3906 int size, unsigned short port, void *val,
3907 unsigned int count)
cf8f70bf 3908{
ca1d4a9e 3909 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 3910 int ret;
ca1d4a9e 3911
6f6fbe98
XG		 3912 if (vcpu->arch.pio.count)
3913 goto data_avail;
cf8f70bf 3914
6f6fbe98
XG		 3915 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
3916 if (ret) {
3917data_avail:
3918 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3919 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3920 return 1;
3921 }
3922
cf8f70bf
GN		 3923 return 0;
3924}
3925
6f6fbe98
XG		 3926static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
3927 int size, unsigned short port,
3928 const void *val, unsigned int count)
3929{
3930 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3931
3932 memcpy(vcpu->arch.pio_data, val, size * count);
3933 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
3934}
3935
bbd9b64e
CO		 3936static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3937{
3938 return kvm_x86_ops->get_segment_base(vcpu, seg);
3939}
3940
3cb16fe7 3941static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 3942{
3cb16fe7 3943 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 3944}
3945
f5f48ee1
SY		 3946int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
3947{
3948 if (!need_emulate_wbinvd(vcpu))
3949 return X86EMUL_CONTINUE;
3950
3951 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 3952 int cpu = get_cpu();
3953
3954 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 3955 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
3956 wbinvd_ipi, NULL, 1);
2eec7343 3957 put_cpu();
f5f48ee1 3958 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 3959 } else
3960 wbinvd();
f5f48ee1
SY		 3961 return X86EMUL_CONTINUE;
3962}
3963EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
3964
bcaf5cc5
AK		 3965static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
3966{
3967 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
3968}
3969
717746e3 3970int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 3971{
717746e3 3972 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 3973}
3974
717746e3 3975int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 3976{
338dbc97 3977
717746e3 3978 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 3979}
3980
52a46617 3981static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 3982{
52a46617 3983 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 3984}
3985
717746e3 3986static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 3987{
717746e3 3988 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 3989 unsigned long value;
3990
3991 switch (cr) {
3992 case 0:
3993 value = kvm_read_cr0(vcpu);
3994 break;
3995 case 2:
3996 value = vcpu->arch.cr2;
3997 break;
3998 case 3:
9f8fe504 3999 value = kvm_read_cr3(vcpu);
52a46617
GN		 4000 break;
4001 case 4:
4002 value = kvm_read_cr4(vcpu);
4003 break;
4004 case 8:
4005 value = kvm_get_cr8(vcpu);
4006 break;
4007 default:
4008 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4009 return 0;
4010 }
4011
4012 return value;
4013}
4014
717746e3 4015static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4016{
717746e3 4017 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4018 int res = 0;
4019
52a46617
GN		 4020 switch (cr) {
4021 case 0:
49a9b07e 4022 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4023 break;
4024 case 2:
4025 vcpu->arch.cr2 = val;
4026 break;
4027 case 3:
2390218b 4028 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4029 break;
4030 case 4:
a83b29c6 4031 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4032 break;
4033 case 8:
eea1cff9 4034 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4035 break;
4036 default:
4037 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4038 res = -1;
52a46617 4039 }
0f12244f
GN		 4040
4041 return res;
52a46617
GN		 4042}
4043
717746e3 4044static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4045{
717746e3 4046 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4047}
4048
4bff1e86 4049static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4050{
4bff1e86 4051 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4052}
4053
4bff1e86 4054static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4055{
4bff1e86 4056 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4057}
4058
1ac9d0cf
AK		 4059static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4060{
4061 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4062}
4063
4064static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4065{
4066 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4067}
4068
4bff1e86
AK		 4069static unsigned long emulator_get_cached_segment_base(
4070 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4071{
4bff1e86 4072 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4073}
4074
1aa36616
AK		 4075static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4076 struct desc_struct *desc, u32 *base3,
4077 int seg)
2dafc6c2
GN		 4078{
4079 struct kvm_segment var;
4080
4bff1e86 4081 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4082 *selector = var.selector;
2dafc6c2
GN		 4083
4084 if (var.unusable)
4085 return false;
4086
4087 if (var.g)
4088 var.limit >>= 12;
4089 set_desc_limit(desc, var.limit);
4090 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4091#ifdef CONFIG_X86_64
4092 if (base3)
4093 *base3 = var.base >> 32;
4094#endif
2dafc6c2
GN		 4095 desc->type = var.type;
4096 desc->s = var.s;
4097 desc->dpl = var.dpl;
4098 desc->p = var.present;
4099 desc->avl = var.avl;
4100 desc->l = var.l;
4101 desc->d = var.db;
4102 desc->g = var.g;
4103
4104 return true;
4105}
4106
1aa36616
AK		 4107static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4108 struct desc_struct *desc, u32 base3,
4109 int seg)
2dafc6c2 4110{
4bff1e86 4111 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4112 struct kvm_segment var;
4113
1aa36616 4114 var.selector = selector;
2dafc6c2 4115 var.base = get_desc_base(desc);
5601d05b
GN		 4116#ifdef CONFIG_X86_64
4117 var.base |= ((u64)base3) << 32;
4118#endif
2dafc6c2
GN		 4119 var.limit = get_desc_limit(desc);
4120 if (desc->g)
4121 var.limit = (var.limit << 12) | 0xfff;
4122 var.type = desc->type;
4123 var.present = desc->p;
4124 var.dpl = desc->dpl;
4125 var.db = desc->d;
4126 var.s = desc->s;
4127 var.l = desc->l;
4128 var.g = desc->g;
4129 var.avl = desc->avl;
4130 var.present = desc->p;
4131 var.unusable = !var.present;
4132 var.padding = 0;
4133
4134 kvm_set_segment(vcpu, &var, seg);
4135 return;
4136}
4137
717746e3
AK		 4138static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4139 u32 msr_index, u64 *pdata)
4140{
4141 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4142}
4143
4144static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4145 u32 msr_index, u64 data)
4146{
4147 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4148}
4149
6c3287f7
AK		 4150static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4151{
4152 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4153}
4154
5037f6f3
AK		 4155static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4156{
4157 preempt_disable();
5197b808 4158 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4159 /*
4160 * CR0.TS may reference the host fpu state, not the guest fpu state,
4161 * so it may be clear at this point.
4162 */
4163 clts();
4164}
4165
4166static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4167{
4168 preempt_enable();
4169}
4170
2953538e 4171static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4172 struct x86_instruction_info *info,
c4f035c6
AK		 4173 enum x86_intercept_stage stage)
4174{
2953538e 4175 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4176}
4177
14af3f3c 4178static struct x86_emulate_ops emulate_ops = {
1871c602 4179 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4180 .write_std = kvm_write_guest_virt_system,
1871c602 4181 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4182 .read_emulated = emulator_read_emulated,
4183 .write_emulated = emulator_write_emulated,
4184 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4185 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4186 .pio_in_emulated = emulator_pio_in_emulated,
4187 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4188 .get_segment = emulator_get_segment,
4189 .set_segment = emulator_set_segment,
5951c442 4190 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4191 .get_gdt = emulator_get_gdt,
160ce1f1 4192 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4193 .set_gdt = emulator_set_gdt,
4194 .set_idt = emulator_set_idt,
52a46617
GN		 4195 .get_cr = emulator_get_cr,
4196 .set_cr = emulator_set_cr,
9c537244 4197 .cpl = emulator_get_cpl,
35aa5375
GN		 4198 .get_dr = emulator_get_dr,
4199 .set_dr = emulator_set_dr,
717746e3
AK		 4200 .set_msr = emulator_set_msr,
4201 .get_msr = emulator_get_msr,
6c3287f7 4202 .halt = emulator_halt,
bcaf5cc5 4203 .wbinvd = emulator_wbinvd,
d6aa1000 4204 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4205 .get_fpu = emulator_get_fpu,
4206 .put_fpu = emulator_put_fpu,
c4f035c6 4207 .intercept = emulator_intercept,
bbd9b64e
CO		 4208};
4209
5fdbf976
MT		 4210static void cache_all_regs(struct kvm_vcpu *vcpu)
4211{
4212 kvm_register_read(vcpu, VCPU_REGS_RAX);
4213 kvm_register_read(vcpu, VCPU_REGS_RSP);
4214 kvm_register_read(vcpu, VCPU_REGS_RIP);
4215 vcpu->arch.regs_dirty = ~0;
4216}
4217
95cb2295
GN		 4218static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4219{
4220 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4221 /*
4222 * an sti; sti; sequence only disable interrupts for the first
4223 * instruction. So, if the last instruction, be it emulated or
4224 * not, left the system with the INT_STI flag enabled, it
4225 * means that the last instruction is an sti. We should not
4226 * leave the flag on in this case. The same goes for mov ss
4227 */
4228 if (!(int_shadow & mask))
4229 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4230}
4231
54b8486f
GN		 4232static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4233{
4234 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4235 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4236 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4237 else if (ctxt->exception.error_code_valid)
4238 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4239 ctxt->exception.error_code);
54b8486f 4240 else
da9cb575 4241 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4242}
4243
9dac77fa 4244static void init_decode_cache(struct x86_emulate_ctxt *ctxt,
b5c9ff73
TY		 4245 const unsigned long *regs)
4246{
9dac77fa
AK		 4247 memset(&ctxt->twobyte, 0,
4248 (void *)&ctxt->regs - (void *)&ctxt->twobyte);
4249 memcpy(ctxt->regs, regs, sizeof(ctxt->regs));
b5c9ff73 4250
9dac77fa
AK		 4251 ctxt->fetch.start = 0;
4252 ctxt->fetch.end = 0;
4253 ctxt->io_read.pos = 0;
4254 ctxt->io_read.end = 0;
4255 ctxt->mem_read.pos = 0;
4256 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4257}
4258
8ec4722d
MG		 4259static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4260{
adf52235 4261 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4262 int cs_db, cs_l;
4263
2aab2c5b
GN		 4264 /*
4265 * TODO: fix emulate.c to use guest_read/write_register
4266 * instead of direct ->regs accesses, can save hundred cycles
4267 * on Intel for instructions that don't read/change RSP, for
4268 * for example.
4269 */
8ec4722d
MG		 4270 cache_all_regs(vcpu);
4271
4272 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4273
adf52235
TY		 4274 ctxt->eflags = kvm_get_rflags(vcpu);
4275 ctxt->eip = kvm_rip_read(vcpu);
4276 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4277 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4278 cs_l ? X86EMUL_MODE_PROT64 :
4279 cs_db ? X86EMUL_MODE_PROT32 :
4280 X86EMUL_MODE_PROT16;
4281 ctxt->guest_mode = is_guest_mode(vcpu);
4282
9dac77fa 4283 init_decode_cache(ctxt, vcpu->arch.regs);
7ae441ea 4284 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4285}
4286
71f9833b 4287int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4288{
9d74191a 4289 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4290 int ret;
4291
4292 init_emulate_ctxt(vcpu);
4293
9dac77fa
AK		 4294 ctxt->op_bytes = 2;
4295 ctxt->ad_bytes = 2;
4296 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4297 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4298
4299 if (ret != X86EMUL_CONTINUE)
4300 return EMULATE_FAIL;
4301
9dac77fa
AK		 4302 ctxt->eip = ctxt->_eip;
4303 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 4304 kvm_rip_write(vcpu, ctxt->eip);
4305 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4306
4307 if (irq == NMI_VECTOR)
7460fb4a 4308 vcpu->arch.nmi_pending = 0;
63995653
MG		 4309 else
4310 vcpu->arch.interrupt.pending = false;
4311
4312 return EMULATE_DONE;
4313}
4314EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4315
6d77dbfc
GN		 4316static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4317{
fc3a9157
JR		 4318 int r = EMULATE_DONE;
4319
6d77dbfc
GN		 4320 ++vcpu->stat.insn_emulation_fail;
4321 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4322 if (!is_guest_mode(vcpu)) {
4323 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4324 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4325 vcpu->run->internal.ndata = 0;
4326 r = EMULATE_FAIL;
4327 }
6d77dbfc 4328 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4329
4330 return r;
6d77dbfc
GN		 4331}
4332
a6f177ef
GN		 4333static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4334{
4335 gpa_t gpa;
4336
68be0803
GN		 4337 if (tdp_enabled)
4338 return false;
4339
a6f177ef
GN		 4340 /*
4341 * if emulation was due to access to shadowed page table
4342 * and it failed try to unshadow page and re-entetr the
4343 * guest to let CPU execute the instruction.
4344 */
4345 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4346 return true;
4347
4348 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4349
4350 if (gpa == UNMAPPED_GVA)
4351 return true; /* let cpu generate fault */
4352
4353 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4354 return true;
4355
4356 return false;
4357}
4358
1cb3f3ae
XG		 4359static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4360 unsigned long cr2, int emulation_type)
4361{
4362 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4363 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4364
4365 last_retry_eip = vcpu->arch.last_retry_eip;
4366 last_retry_addr = vcpu->arch.last_retry_addr;
4367
4368 /*
4369 * If the emulation is caused by #PF and it is non-page_table
4370 * writing instruction, it means the VM-EXIT is caused by shadow
4371 * page protected, we can zap the shadow page and retry this
4372 * instruction directly.
4373 *
4374 * Note: if the guest uses a non-page-table modifying instruction
4375 * on the PDE that points to the instruction, then we will unmap
4376 * the instruction and go to an infinite loop. So, we cache the
4377 * last retried eip and the last fault address, if we meet the eip
4378 * and the address again, we can break out of the potential infinite
4379 * loop.
4380 */
4381 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4382
4383 if (!(emulation_type & EMULTYPE_RETRY))
4384 return false;
4385
4386 if (x86_page_table_writing_insn(ctxt))
4387 return false;
4388
4389 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4390 return false;
4391
4392 vcpu->arch.last_retry_eip = ctxt->eip;
4393 vcpu->arch.last_retry_addr = cr2;
4394
4395 if (!vcpu->arch.mmu.direct_map)
4396 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4397
4398 kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4399
4400 return true;
4401}
4402
51d8b661
AP		 4403int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4404 unsigned long cr2,
dc25e89e
AP		 4405 int emulation_type,
4406 void *insn,
4407 int insn_len)
bbd9b64e 4408{
95cb2295 4409 int r;
9d74191a 4410 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 4411 bool writeback = true;
bbd9b64e 4412
26eef70c 4413 kvm_clear_exception_queue(vcpu);
8d7d8102 4414
571008da 4415 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4416 init_emulate_ctxt(vcpu);
9d74191a
TY		 4417 ctxt->interruptibility = 0;
4418 ctxt->have_exception = false;
4419 ctxt->perm_ok = false;
bbd9b64e 4420
9d74191a 4421 ctxt->only_vendor_specific_insn
4005996e
AK		 4422 = emulation_type & EMULTYPE_TRAP_UD;
4423
9d74191a 4424 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 4425
e46479f8 4426 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4427 ++vcpu->stat.insn_emulation;
1d2887e2 4428 if (r != EMULATION_OK) {
4005996e
AK		 4429 if (emulation_type & EMULTYPE_TRAP_UD)
4430 return EMULATE_FAIL;
a6f177ef 4431 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4432 return EMULATE_DONE;
6d77dbfc
GN		 4433 if (emulation_type & EMULTYPE_SKIP)
4434 return EMULATE_FAIL;
4435 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4436 }
4437 }
4438
ba8afb6b 4439 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 4440 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 4441 return EMULATE_DONE;
4442 }
4443
1cb3f3ae
XG		 4444 if (retry_instruction(ctxt, cr2, emulation_type))
4445 return EMULATE_DONE;
4446
7ae441ea 4447 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4448 changes registers values during IO operation */
7ae441ea
GN		 4449 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4450 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
9dac77fa 4451 memcpy(ctxt->regs, vcpu->arch.regs, sizeof ctxt->regs);
7ae441ea 4452 }
4d2179e1 4453
5cd21917 4454restart:
9d74191a 4455 r = x86_emulate_insn(ctxt);
bbd9b64e 4456
775fde86
JR		 4457 if (r == EMULATION_INTERCEPTED)
4458 return EMULATE_DONE;
4459
d2ddd1c4 4460 if (r == EMULATION_FAILED) {
a6f177ef 4461 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4462 return EMULATE_DONE;
4463
6d77dbfc 4464 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4465 }
4466
9d74191a 4467 if (ctxt->have_exception) {
54b8486f 4468 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4469 r = EMULATE_DONE;
4470 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4471 if (!vcpu->arch.pio.in)
4472 vcpu->arch.pio.count = 0;
7ae441ea
GN		 4473 else
4474 writeback = false;
e85d28f8 4475 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4476 } else if (vcpu->mmio_needed) {
4477 if (!vcpu->mmio_is_write)
4478 writeback = false;
e85d28f8 4479 r = EMULATE_DO_MMIO;
7ae441ea 4480 } else if (r == EMULATION_RESTART)
5cd21917 4481 goto restart;
d2ddd1c4
GN		 4482 else
4483 r = EMULATE_DONE;
f850e2e6 4484
7ae441ea 4485 if (writeback) {
9d74191a
TY		 4486 toggle_interruptibility(vcpu, ctxt->interruptibility);
4487 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea 4488 kvm_make_request(KVM_REQ_EVENT, vcpu);
9dac77fa 4489 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea 4490 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 4491 kvm_rip_write(vcpu, ctxt->eip);
7ae441ea
GN		 4492 } else
4493 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4494
4495 return r;
de7d789a 4496}
51d8b661 4497EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4498
cf8f70bf 4499int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4500{
cf8f70bf 4501 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 4502 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4503 size, port, &val, 1);
cf8f70bf 4504 /* do not return to emulator after return from userspace */
7972995b 4505 vcpu->arch.pio.count = 0;
de7d789a
CO		 4506 return ret;
4507}
cf8f70bf 4508EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4509
8cfdc000
ZA		 4510static void tsc_bad(void *info)
4511{
0a3aee0d 4512 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4513}
4514
4515static void tsc_khz_changed(void *data)
c8076604 4516{
8cfdc000
ZA		 4517 struct cpufreq_freqs *freq = data;
4518 unsigned long khz = 0;
4519
4520 if (data)
4521 khz = freq->new;
4522 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4523 khz = cpufreq_quick_get(raw_smp_processor_id());
4524 if (!khz)
4525 khz = tsc_khz;
0a3aee0d 4526 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 4527}
4528
c8076604
GH		 4529static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4530 void *data)
4531{
4532 struct cpufreq_freqs *freq = data;
4533 struct kvm *kvm;
4534 struct kvm_vcpu *vcpu;
4535 int i, send_ipi = 0;
4536
8cfdc000
ZA		 4537 /*
4538 * We allow guests to temporarily run on slowing clocks,
4539 * provided we notify them after, or to run on accelerating
4540 * clocks, provided we notify them before. Thus time never
4541 * goes backwards.
4542 *
4543 * However, we have a problem. We can't atomically update
4544 * the frequency of a given CPU from this function; it is
4545 * merely a notifier, which can be called from any CPU.
4546 * Changing the TSC frequency at arbitrary points in time
4547 * requires a recomputation of local variables related to
4548 * the TSC for each VCPU. We must flag these local variables
4549 * to be updated and be sure the update takes place with the
4550 * new frequency before any guests proceed.
4551 *
4552 * Unfortunately, the combination of hotplug CPU and frequency
4553 * change creates an intractable locking scenario; the order
4554 * of when these callouts happen is undefined with respect to
4555 * CPU hotplug, and they can race with each other. As such,
4556 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4557 * undefined; you can actually have a CPU frequency change take
4558 * place in between the computation of X and the setting of the
4559 * variable. To protect against this problem, all updates of
4560 * the per_cpu tsc_khz variable are done in an interrupt
4561 * protected IPI, and all callers wishing to update the value
4562 * must wait for a synchronous IPI to complete (which is trivial
4563 * if the caller is on the CPU already). This establishes the
4564 * necessary total order on variable updates.
4565 *
4566 * Note that because a guest time update may take place
4567 * anytime after the setting of the VCPU's request bit, the
4568 * correct TSC value must be set before the request. However,
4569 * to ensure the update actually makes it to any guest which
4570 * starts running in hardware virtualization between the set
4571 * and the acquisition of the spinlock, we must also ping the
4572 * CPU after setting the request bit.
4573 *
4574 */
4575
c8076604
GH		 4576 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4577 return 0;
4578 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4579 return 0;
8cfdc000
ZA		 4580
4581 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 4582
e935b837 4583 raw_spin_lock(&kvm_lock);
c8076604 4584 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4585 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4586 if (vcpu->cpu != freq->cpu)
4587 continue;
c285545f 4588 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4589 if (vcpu->cpu != smp_processor_id())
8cfdc000 4590 send_ipi = 1;
c8076604
GH		 4591 }
4592 }
e935b837 4593 raw_spin_unlock(&kvm_lock);
c8076604
GH		 4594
4595 if (freq->old < freq->new && send_ipi) {
4596 /*
4597 * We upscale the frequency. Must make the guest
4598 * doesn't see old kvmclock values while running with
4599 * the new frequency, otherwise we risk the guest sees
4600 * time go backwards.
4601 *
4602 * In case we update the frequency for another cpu
4603 * (which might be in guest context) send an interrupt
4604 * to kick the cpu out of guest context. Next time
4605 * guest context is entered kvmclock will be updated,
4606 * so the guest will not see stale values.
4607 */
8cfdc000 4608 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4609 }
4610 return 0;
4611}
4612
4613static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4614 .notifier_call = kvmclock_cpufreq_notifier
4615};
4616
4617static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4618 unsigned long action, void *hcpu)
4619{
4620 unsigned int cpu = (unsigned long)hcpu;
4621
4622 switch (action) {
4623 case CPU_ONLINE:
4624 case CPU_DOWN_FAILED:
4625 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4626 break;
4627 case CPU_DOWN_PREPARE:
4628 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4629 break;
4630 }
4631 return NOTIFY_OK;
4632}
4633
4634static struct notifier_block kvmclock_cpu_notifier_block = {
4635 .notifier_call = kvmclock_cpu_notifier,
4636 .priority = -INT_MAX
c8076604
GH		 4637};
4638
b820cc0c
ZA		 4639static void kvm_timer_init(void)
4640{
4641 int cpu;
4642
c285545f 4643 max_tsc_khz = tsc_khz;
8cfdc000 4644 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4645 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4646#ifdef CONFIG_CPU_FREQ
4647 struct cpufreq_policy policy;
4648 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 4649 cpu = get_cpu();
4650 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 4651 if (policy.cpuinfo.max_freq)
4652 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 4653 put_cpu();
c285545f 4654#endif
b820cc0c
ZA		 4655 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4656 CPUFREQ_TRANSITION_NOTIFIER);
4657 }
c285545f 4658 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4659 for_each_online_cpu(cpu)
4660 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4661}
4662
ff9d07a0
ZY		 4663static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4664
4665static int kvm_is_in_guest(void)
4666{
086c9855 4667 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 4668}
4669
4670static int kvm_is_user_mode(void)
4671{
4672 int user_mode = 3;
dcf46b94 4673
086c9855
AS		 4674 if (__this_cpu_read(current_vcpu))
4675 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 4676
ff9d07a0
ZY		 4677 return user_mode != 0;
4678}
4679
4680static unsigned long kvm_get_guest_ip(void)
4681{
4682 unsigned long ip = 0;
dcf46b94 4683
086c9855
AS		 4684 if (__this_cpu_read(current_vcpu))
4685 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 4686
ff9d07a0
ZY		 4687 return ip;
4688}
4689
4690static struct perf_guest_info_callbacks kvm_guest_cbs = {
4691 .is_in_guest = kvm_is_in_guest,
4692 .is_user_mode = kvm_is_user_mode,
4693 .get_guest_ip = kvm_get_guest_ip,
4694};
4695
4696void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4697{
086c9855 4698 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 4699}
4700EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4701
4702void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4703{
086c9855 4704 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 4705}
4706EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4707
ce88decf
XG		 4708static void kvm_set_mmio_spte_mask(void)
4709{
4710 u64 mask;
4711 int maxphyaddr = boot_cpu_data.x86_phys_bits;
4712
4713 /*
4714 * Set the reserved bits and the present bit of an paging-structure
4715 * entry to generate page fault with PFER.RSV = 1.
4716 */
4717 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
4718 mask |= 1ull;
4719
4720#ifdef CONFIG_X86_64
4721 /*
4722 * If reserved bit is not supported, clear the present bit to disable
4723 * mmio page fault.
4724 */
4725 if (maxphyaddr == 52)
4726 mask &= ~1ull;
4727#endif
4728
4729 kvm_mmu_set_mmio_spte_mask(mask);
4730}
4731
f8c16bba 4732int kvm_arch_init(void *opaque)
043405e1 4733{
b820cc0c 4734 int r;
f8c16bba
ZX		 4735 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4736
f8c16bba
ZX		 4737 if (kvm_x86_ops) {
4738 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4739 r = -EEXIST;
4740 goto out;
f8c16bba
ZX		 4741 }
4742
4743 if (!ops->cpu_has_kvm_support()) {
4744 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4745 r = -EOPNOTSUPP;
4746 goto out;
f8c16bba
ZX		 4747 }
4748 if (ops->disabled_by_bios()) {
4749 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4750 r = -EOPNOTSUPP;
4751 goto out;
f8c16bba
ZX		 4752 }
4753
97db56ce
AK		 4754 r = kvm_mmu_module_init();
4755 if (r)
4756 goto out;
4757
ce88decf 4758 kvm_set_mmio_spte_mask();
97db56ce
AK		 4759 kvm_init_msr_list();
4760
f8c16bba 4761 kvm_x86_ops = ops;
7b52345e 4762 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4763 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4764
b820cc0c 4765 kvm_timer_init();
c8076604 4766
ff9d07a0
ZY		 4767 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4768
2acf923e
DC		 4769 if (cpu_has_xsave)
4770 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4771
f8c16bba 4772 return 0;
56c6d28a
ZX		 4773
4774out:
56c6d28a 4775 return r;
043405e1 4776}
8776e519 4777
f8c16bba
ZX		 4778void kvm_arch_exit(void)
4779{
ff9d07a0
ZY		 4780 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4781
888d256e
JK		 4782 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4783 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4784 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4785 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4786 kvm_x86_ops = NULL;
56c6d28a
ZX		 4787 kvm_mmu_module_exit();
4788}
f8c16bba 4789
8776e519
HB		 4790int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4791{
4792 ++vcpu->stat.halt_exits;
4793 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4794 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4795 return 1;
4796 } else {
4797 vcpu->run->exit_reason = KVM_EXIT_HLT;
4798 return 0;
4799 }
4800}
4801EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4802
55cd8e5a
GN		 4803int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4804{
4805 u64 param, ingpa, outgpa, ret;
4806 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4807 bool fast, longmode;
4808 int cs_db, cs_l;
4809
4810 /*
4811 * hypercall generates UD from non zero cpl and real mode
4812 * per HYPER-V spec
4813 */
3eeb3288 4814 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4815 kvm_queue_exception(vcpu, UD_VECTOR);
4816 return 0;
4817 }
4818
4819 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4820 longmode = is_long_mode(vcpu) && cs_l == 1;
4821
4822 if (!longmode) {
ccd46936
GN		 4823 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4824 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4825 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4826 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4827 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4828 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4829 }
4830#ifdef CONFIG_X86_64
4831 else {
4832 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4833 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4834 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4835 }
4836#endif
4837
4838 code = param & 0xffff;
4839 fast = (param >> 16) & 0x1;
4840 rep_cnt = (param >> 32) & 0xfff;
4841 rep_idx = (param >> 48) & 0xfff;
4842
4843 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4844
c25bc163
GN		 4845 switch (code) {
4846 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4847 kvm_vcpu_on_spin(vcpu);
4848 break;
4849 default:
4850 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4851 break;
4852 }
55cd8e5a
GN		 4853
4854 ret = res | (((u64)rep_done & 0xfff) << 32);
4855 if (longmode) {
4856 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4857 } else {
4858 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4859 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4860 }
4861
4862 return 1;
4863}
4864
8776e519
HB		 4865int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4866{
4867 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4868 int r = 1;
8776e519 4869
55cd8e5a
GN		 4870 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4871 return kvm_hv_hypercall(vcpu);
4872
5fdbf976
MT		 4873 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4874 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4875 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4876 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4877 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4878
229456fc 4879 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4880
8776e519
HB		 4881 if (!is_long_mode(vcpu)) {
4882 nr &= 0xFFFFFFFF;
4883 a0 &= 0xFFFFFFFF;
4884 a1 &= 0xFFFFFFFF;
4885 a2 &= 0xFFFFFFFF;
4886 a3 &= 0xFFFFFFFF;
4887 }
4888
07708c4a
JK		 4889 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4890 ret = -KVM_EPERM;
4891 goto out;
4892 }
4893
8776e519 4894 switch (nr) {
b93463aa
AK		 4895 case KVM_HC_VAPIC_POLL_IRQ:
4896 ret = 0;
4897 break;
8776e519
HB		 4898 default:
4899 ret = -KVM_ENOSYS;
4900 break;
4901 }
07708c4a 4902out:
5fdbf976 4903 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4904 ++vcpu->stat.hypercalls;
2f333bcb 4905 return r;
8776e519
HB		 4906}
4907EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4908
d6aa1000 4909int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 4910{
d6aa1000 4911 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 4912 char instruction[3];
5fdbf976 4913 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4914
8776e519
HB		 4915 /*
4916 * Blow out the MMU to ensure that no other VCPU has an active mapping
4917 * to ensure that the updated hypercall appears atomically across all
4918 * VCPUs.
4919 */
4920 kvm_mmu_zap_all(vcpu->kvm);
4921
8776e519 4922 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4923
9d74191a 4924 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 4925}
4926
b6c7a5dc
HB		 4927/*
4928 * Check if userspace requested an interrupt window, and that the
4929 * interrupt window is open.
4930 *
4931 * No need to exit to userspace if we already have an interrupt queued.
4932 */
851ba692 4933static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4934{
8061823a 4935 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4936 vcpu->run->request_interrupt_window &&
5df56646 4937 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4938}
4939
851ba692 4940static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4941{
851ba692
AK		 4942 struct kvm_run *kvm_run = vcpu->run;
4943
91586a3b 4944 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4945 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4946 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4947 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4948 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4949 else
b6c7a5dc 4950 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4951 kvm_arch_interrupt_allowed(vcpu) &&
4952 !kvm_cpu_has_interrupt(vcpu) &&
4953 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4954}
4955
b93463aa
AK		 4956static void vapic_enter(struct kvm_vcpu *vcpu)
4957{
4958 struct kvm_lapic *apic = vcpu->arch.apic;
4959 struct page *page;
4960
4961 if (!apic || !apic->vapic_addr)
4962 return;
4963
4964 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4965
4966 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4967}
4968
4969static void vapic_exit(struct kvm_vcpu *vcpu)
4970{
4971 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4972 int idx;
b93463aa
AK		 4973
4974 if (!apic || !apic->vapic_addr)
4975 return;
4976
f656ce01 4977 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4978 kvm_release_page_dirty(apic->vapic_page);
4979 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4980 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4981}
4982
95ba8273
GN		 4983static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4984{
4985 int max_irr, tpr;
4986
4987 if (!kvm_x86_ops->update_cr8_intercept)
4988 return;
4989
88c808fd
AK		 4990 if (!vcpu->arch.apic)
4991 return;
4992
8db3baa2
GN		 4993 if (!vcpu->arch.apic->vapic_addr)
4994 max_irr = kvm_lapic_find_highest_irr(vcpu);
4995 else
4996 max_irr = -1;
95ba8273
GN		 4997
4998 if (max_irr != -1)
4999 max_irr >>= 4;
5000
5001 tpr = kvm_lapic_get_cr8(vcpu);
5002
5003 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5004}
5005
851ba692 5006static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5007{
5008 /* try to reinject previous events if any */
b59bb7bd 5009 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5010 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5011 vcpu->arch.exception.has_error_code,
5012 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5013 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5014 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5015 vcpu->arch.exception.error_code,
5016 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5017 return;
5018 }
5019
95ba8273
GN		 5020 if (vcpu->arch.nmi_injected) {
5021 kvm_x86_ops->set_nmi(vcpu);
5022 return;
5023 }
5024
5025 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5026 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5027 return;
5028 }
5029
5030 /* try to inject new event if pending */
5031 if (vcpu->arch.nmi_pending) {
5032 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5033 --vcpu->arch.nmi_pending;
95ba8273
GN		 5034 vcpu->arch.nmi_injected = true;
5035 kvm_x86_ops->set_nmi(vcpu);
5036 }
5037 } else if (kvm_cpu_has_interrupt(vcpu)) {
5038 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5039 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5040 false);
5041 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5042 }
5043 }
5044}
5045
2acf923e
DC		 5046static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5047{
5048 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5049 !vcpu->guest_xcr0_loaded) {
5050 /* kvm_set_xcr() also depends on this */
5051 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5052 vcpu->guest_xcr0_loaded = 1;
5053 }
5054}
5055
5056static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5057{
5058 if (vcpu->guest_xcr0_loaded) {
5059 if (vcpu->arch.xcr0 != host_xcr0)
5060 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5061 vcpu->guest_xcr0_loaded = 0;
5062 }
5063}
5064
7460fb4a
AK		 5065static void process_nmi(struct kvm_vcpu *vcpu)
5066{
5067 unsigned limit = 2;
5068
5069 /*
5070 * x86 is limited to one NMI running, and one NMI pending after it.
5071 * If an NMI is already in progress, limit further NMIs to just one.
5072 * Otherwise, allow two (and we'll inject the first one immediately).
5073 */
5074 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5075 limit = 1;
5076
5077 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5078 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5079 kvm_make_request(KVM_REQ_EVENT, vcpu);
5080}
5081
851ba692 5082static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5083{
5084 int r;
6a8b1d13 5085 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5086 vcpu->run->request_interrupt_window;
d6185f20 5087 bool req_immediate_exit = 0;
b6c7a5dc 5088
3e007509 5089 if (vcpu->requests) {
a8eeb04a 5090 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5091 kvm_mmu_unload(vcpu);
a8eeb04a 5092 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5093 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5094 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5095 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5096 if (unlikely(r))
5097 goto out;
5098 }
a8eeb04a 5099 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5100 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5101 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5102 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5103 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5104 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5105 r = 0;
5106 goto out;
5107 }
a8eeb04a 5108 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5109 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5110 r = 0;
5111 goto out;
5112 }
a8eeb04a 5113 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5114 vcpu->fpu_active = 0;
5115 kvm_x86_ops->fpu_deactivate(vcpu);
5116 }
af585b92
GN		 5117 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5118 /* Page is swapped out. Do synthetic halt */
5119 vcpu->arch.apf.halted = true;
5120 r = 1;
5121 goto out;
5122 }
c9aaa895
GC		 5123 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5124 record_steal_time(vcpu);
7460fb4a
AK		 5125 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5126 process_nmi(vcpu);
d6185f20
NHE		 5127 req_immediate_exit =
5128 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
2f52d58c 5129 }
b93463aa 5130
3e007509
AK		 5131 r = kvm_mmu_reload(vcpu);
5132 if (unlikely(r))
5133 goto out;
5134
b463a6f7
AK		 5135 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5136 inject_pending_event(vcpu);
5137
5138 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5139 if (vcpu->arch.nmi_pending)
b463a6f7
AK		 5140 kvm_x86_ops->enable_nmi_window(vcpu);
5141 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5142 kvm_x86_ops->enable_irq_window(vcpu);
5143
5144 if (kvm_lapic_enabled(vcpu)) {
5145 update_cr8_intercept(vcpu);
5146 kvm_lapic_sync_to_vapic(vcpu);
5147 }
5148 }
5149
b6c7a5dc
HB		 5150 preempt_disable();
5151
5152 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5153 if (vcpu->fpu_active)
5154 kvm_load_guest_fpu(vcpu);
2acf923e 5155 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5156
6b7e2d09
XG		 5157 vcpu->mode = IN_GUEST_MODE;
5158
5159 /* We should set ->mode before check ->requests,
5160 * see the comment in make_all_cpus_request.
5161 */
5162 smp_mb();
b6c7a5dc 5163
d94e1dc9 5164 local_irq_disable();
32f88400 5165
6b7e2d09 5166 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5167 || need_resched() || signal_pending(current)) {
6b7e2d09 5168 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5169 smp_wmb();
6c142801
AK		 5170 local_irq_enable();
5171 preempt_enable();
b463a6f7 5172 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5173 r = 1;
5174 goto out;
5175 }
5176
f656ce01 5177 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5178
d6185f20
NHE		 5179 if (req_immediate_exit)
5180 smp_send_reschedule(vcpu->cpu);
5181
b6c7a5dc
HB		 5182 kvm_guest_enter();
5183
42dbaa5a 5184 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5185 set_debugreg(0, 7);
5186 set_debugreg(vcpu->arch.eff_db[0], 0);
5187 set_debugreg(vcpu->arch.eff_db[1], 1);
5188 set_debugreg(vcpu->arch.eff_db[2], 2);
5189 set_debugreg(vcpu->arch.eff_db[3], 3);
5190 }
b6c7a5dc 5191
229456fc 5192 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5193 kvm_x86_ops->run(vcpu);
b6c7a5dc 5194
24f1e32c
FW		 5195 /*
5196 * If the guest has used debug registers, at least dr7
5197 * will be disabled while returning to the host.
5198 * If we don't have active breakpoints in the host, we don't
5199 * care about the messed up debug address registers. But if
5200 * we have some of them active, restore the old state.
5201 */
59d8eb53 5202 if (hw_breakpoint_active())
24f1e32c 5203 hw_breakpoint_restore();
42dbaa5a 5204
d5c1785d 5205 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
1d5f066e 5206
6b7e2d09 5207 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5208 smp_wmb();
b6c7a5dc
HB		 5209 local_irq_enable();
5210
5211 ++vcpu->stat.exits;
5212
5213 /*
5214 * We must have an instruction between local_irq_enable() and
5215 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5216 * the interrupt shadow. The stat.exits increment will do nicely.
5217 * But we need to prevent reordering, hence this barrier():
5218 */
5219 barrier();
5220
5221 kvm_guest_exit();
5222
5223 preempt_enable();
5224
f656ce01 5225 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5226
b6c7a5dc
HB		 5227 /*
5228 * Profile KVM exit RIPs:
5229 */
5230 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5231 unsigned long rip = kvm_rip_read(vcpu);
5232 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5233 }
5234
298101da 5235
b93463aa
AK		 5236 kvm_lapic_sync_from_vapic(vcpu);
5237
851ba692 5238 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5239out:
5240 return r;
5241}
b6c7a5dc 5242
09cec754 5243
851ba692 5244static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5245{
5246 int r;
f656ce01 5247 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5248
5249 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5250 pr_debug("vcpu %d received sipi with vector # %x\n",
5251 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5252 kvm_lapic_reset(vcpu);
5f179287 5253 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5254 if (r)
5255 return r;
5256 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5257 }
5258
f656ce01 5259 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5260 vapic_enter(vcpu);
5261
5262 r = 1;
5263 while (r > 0) {
af585b92
GN		 5264 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5265 !vcpu->arch.apf.halted)
851ba692 5266 r = vcpu_enter_guest(vcpu);
d7690175 5267 else {
f656ce01 5268 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5269 kvm_vcpu_block(vcpu);
f656ce01 5270 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5271 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5272 {
5273 switch(vcpu->arch.mp_state) {
5274 case KVM_MP_STATE_HALTED:
d7690175 5275 vcpu->arch.mp_state =
09cec754
GN		 5276 KVM_MP_STATE_RUNNABLE;
5277 case KVM_MP_STATE_RUNNABLE:
af585b92 5278 vcpu->arch.apf.halted = false;
09cec754
GN		 5279 break;
5280 case KVM_MP_STATE_SIPI_RECEIVED:
5281 default:
5282 r = -EINTR;
5283 break;
5284 }
5285 }
d7690175
MT		 5286 }
5287
09cec754
GN		 5288 if (r <= 0)
5289 break;
5290
5291 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5292 if (kvm_cpu_has_pending_timer(vcpu))
5293 kvm_inject_pending_timer_irqs(vcpu);
5294
851ba692 5295 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5296 r = -EINTR;
851ba692 5297 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5298 ++vcpu->stat.request_irq_exits;
5299 }
af585b92
GN		 5300
5301 kvm_check_async_pf_completion(vcpu);
5302
09cec754
GN		 5303 if (signal_pending(current)) {
5304 r = -EINTR;
851ba692 5305 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5306 ++vcpu->stat.signal_exits;
5307 }
5308 if (need_resched()) {
f656ce01 5309 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5310 kvm_resched(vcpu);
f656ce01 5311 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5312 }
b6c7a5dc
HB		 5313 }
5314
f656ce01 5315 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5316
b93463aa
AK		 5317 vapic_exit(vcpu);
5318
b6c7a5dc
HB		 5319 return r;
5320}
5321
5287f194
AK		 5322static int complete_mmio(struct kvm_vcpu *vcpu)
5323{
5324 struct kvm_run *run = vcpu->run;
5325 int r;
5326
5327 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5328 return 1;
5329
5330 if (vcpu->mmio_needed) {
5287f194 5331 vcpu->mmio_needed = 0;
cef4dea0 5332 if (!vcpu->mmio_is_write)
0004c7c2
GN		 5333 memcpy(vcpu->mmio_data + vcpu->mmio_index,
5334 run->mmio.data, 8);
cef4dea0
AK		 5335 vcpu->mmio_index += 8;
5336 if (vcpu->mmio_index < vcpu->mmio_size) {
5337 run->exit_reason = KVM_EXIT_MMIO;
5338 run->mmio.phys_addr = vcpu->mmio_phys_addr + vcpu->mmio_index;
5339 memcpy(run->mmio.data, vcpu->mmio_data + vcpu->mmio_index, 8);
5340 run->mmio.len = min(vcpu->mmio_size - vcpu->mmio_index, 8);
5341 run->mmio.is_write = vcpu->mmio_is_write;
5342 vcpu->mmio_needed = 1;
5343 return 0;
5344 }
5345 if (vcpu->mmio_is_write)
5346 return 1;
5347 vcpu->mmio_read_completed = 1;
5287f194
AK		 5348 }
5349 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5350 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5351 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5352 if (r != EMULATE_DONE)
5353 return 0;
5354 return 1;
5355}
5356
b6c7a5dc
HB		 5357int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5358{
5359 int r;
5360 sigset_t sigsaved;
5361
e5c30142
AK		 5362 if (!tsk_used_math(current) && init_fpu(current))
5363 return -ENOMEM;
5364
ac9f6dc0
AK		 5365 if (vcpu->sigset_active)
5366 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5367
a4535290 5368 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5369 kvm_vcpu_block(vcpu);
d7690175 5370 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5371 r = -EAGAIN;
5372 goto out;
b6c7a5dc
HB		 5373 }
5374
b6c7a5dc 5375 /* re-sync apic's tpr */
eea1cff9
AP		 5376 if (!irqchip_in_kernel(vcpu->kvm)) {
5377 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5378 r = -EINVAL;
5379 goto out;
5380 }
5381 }
b6c7a5dc 5382
5287f194
AK		 5383 r = complete_mmio(vcpu);
5384 if (r <= 0)
5385 goto out;
5386
851ba692 5387 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5388
5389out:
f1d86e46 5390 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5391 if (vcpu->sigset_active)
5392 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5393
b6c7a5dc
HB		 5394 return r;
5395}
5396
5397int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5398{
7ae441ea
GN		 5399 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5400 /*
5401 * We are here if userspace calls get_regs() in the middle of
5402 * instruction emulation. Registers state needs to be copied
5403 * back from emulation context to vcpu. Usrapace shouldn't do
5404 * that usually, but some bad designed PV devices (vmware
5405 * backdoor interface) need this to work
5406 */
9dac77fa
AK		 5407 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5408 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea
GN		 5409 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5410 }
5fdbf976
MT		 5411 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5412 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5413 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5414 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5415 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5416 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5417 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5418 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5419#ifdef CONFIG_X86_64
5fdbf976
MT		 5420 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5421 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5422 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5423 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5424 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5425 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5426 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5427 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5428#endif
5429
5fdbf976 5430 regs->rip = kvm_rip_read(vcpu);
91586a3b 5431 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5432
b6c7a5dc
HB		 5433 return 0;
5434}
5435
5436int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5437{
7ae441ea
GN		 5438 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5439 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5440
5fdbf976
MT		 5441 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5442 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5443 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5444 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5445 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5446 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5447 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5448 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5449#ifdef CONFIG_X86_64
5fdbf976
MT		 5450 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5451 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5452 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5453 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5454 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5455 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5456 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5457 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5458#endif
5459
5fdbf976 5460 kvm_rip_write(vcpu, regs->rip);
91586a3b 5461 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5462
b4f14abd
JK		 5463 vcpu->arch.exception.pending = false;
5464
3842d135
AK		 5465 kvm_make_request(KVM_REQ_EVENT, vcpu);
5466
b6c7a5dc
HB		 5467 return 0;
5468}
5469
b6c7a5dc
HB		 5470void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5471{
5472 struct kvm_segment cs;
5473
3e6e0aab 5474 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5475 *db = cs.db;
5476 *l = cs.l;
5477}
5478EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5479
5480int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5481 struct kvm_sregs *sregs)
5482{
89a27f4d 5483 struct desc_ptr dt;
b6c7a5dc 5484
3e6e0aab
GT		 5485 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5486 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5487 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5488 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5489 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5490 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5491
3e6e0aab
GT		 5492 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5493 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5494
5495 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5496 sregs->idt.limit = dt.size;
5497 sregs->idt.base = dt.address;
b6c7a5dc 5498 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5499 sregs->gdt.limit = dt.size;
5500 sregs->gdt.base = dt.address;
b6c7a5dc 5501
4d4ec087 5502 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 5503 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 5504 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 5505 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5506 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5507 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5508 sregs->apic_base = kvm_get_apic_base(vcpu);
5509
923c61bb 5510 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5511
36752c9b 5512 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5513 set_bit(vcpu->arch.interrupt.nr,
5514 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5515
b6c7a5dc
HB		 5516 return 0;
5517}
5518
62d9f0db
MT		 5519int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5520 struct kvm_mp_state *mp_state)
5521{
62d9f0db 5522 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5523 return 0;
5524}
5525
5526int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5527 struct kvm_mp_state *mp_state)
5528{
62d9f0db 5529 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5530 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5531 return 0;
5532}
5533
e269fb21
JK		 5534int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5535 bool has_error_code, u32 error_code)
b6c7a5dc 5536{
9d74191a 5537 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 5538 int ret;
e01c2426 5539
8ec4722d 5540 init_emulate_ctxt(vcpu);
c697518a 5541
9d74191a
TY		 5542 ret = emulator_task_switch(ctxt, tss_selector, reason,
5543 has_error_code, error_code);
c697518a 5544
c697518a 5545 if (ret)
19d04437 5546 return EMULATE_FAIL;
37817f29 5547
9dac77fa 5548 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 5549 kvm_rip_write(vcpu, ctxt->eip);
5550 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 5551 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5552 return EMULATE_DONE;
37817f29
IE		 5553}
5554EXPORT_SYMBOL_GPL(kvm_task_switch);
5555
b6c7a5dc
HB		 5556int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5557 struct kvm_sregs *sregs)
5558{
5559 int mmu_reset_needed = 0;
63f42e02 5560 int pending_vec, max_bits, idx;
89a27f4d 5561 struct desc_ptr dt;
b6c7a5dc 5562
89a27f4d
GN		 5563 dt.size = sregs->idt.limit;
5564 dt.address = sregs->idt.base;
b6c7a5dc 5565 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5566 dt.size = sregs->gdt.limit;
5567 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5568 kvm_x86_ops->set_gdt(vcpu, &dt);
5569
ad312c7c 5570 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 5571 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 5572 vcpu->arch.cr3 = sregs->cr3;
aff48baa 5573 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 5574
2d3ad1f4 5575 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5576
f6801dff 5577 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5578 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5579 kvm_set_apic_base(vcpu, sregs->apic_base);
5580
4d4ec087 5581 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5582 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5583 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5584
fc78f519 5585 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5586 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 5587 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 5588 kvm_update_cpuid(vcpu);
63f42e02
XG		 5589
5590 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 5591 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 5592 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 5593 mmu_reset_needed = 1;
5594 }
63f42e02 5595 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 5596
5597 if (mmu_reset_needed)
5598 kvm_mmu_reset_context(vcpu);
5599
923c61bb
GN		 5600 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5601 pending_vec = find_first_bit(
5602 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5603 if (pending_vec < max_bits) {
66fd3f7f 5604 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 5605 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 5606 }
5607
3e6e0aab
GT		 5608 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5609 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5610 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5611 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5612 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5613 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5614
3e6e0aab
GT		 5615 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5616 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5617
5f0269f5
ME		 5618 update_cr8_intercept(vcpu);
5619
9c3e4aab 5620 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5621 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5622 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5623 !is_protmode(vcpu))
9c3e4aab
MT		 5624 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5625
3842d135
AK		 5626 kvm_make_request(KVM_REQ_EVENT, vcpu);
5627
b6c7a5dc
HB		 5628 return 0;
5629}
5630
d0bfb940
JK		 5631int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5632 struct kvm_guest_debug *dbg)
b6c7a5dc 5633{
355be0b9 5634 unsigned long rflags;
ae675ef0 5635 int i, r;
b6c7a5dc 5636
4f926bf2
JK		 5637 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5638 r = -EBUSY;
5639 if (vcpu->arch.exception.pending)
2122ff5e 5640 goto out;
4f926bf2
JK		 5641 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5642 kvm_queue_exception(vcpu, DB_VECTOR);
5643 else
5644 kvm_queue_exception(vcpu, BP_VECTOR);
5645 }
5646
91586a3b
JK		 5647 /*
5648 * Read rflags as long as potentially injected trace flags are still
5649 * filtered out.
5650 */
5651 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5652
5653 vcpu->guest_debug = dbg->control;
5654 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5655 vcpu->guest_debug = 0;
5656
5657 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5658 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5659 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5660 vcpu->arch.switch_db_regs =
5661 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5662 } else {
5663 for (i = 0; i < KVM_NR_DB_REGS; i++)
5664 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5665 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5666 }
5667
f92653ee
JK		 5668 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5669 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5670 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5671
91586a3b
JK		 5672 /*
5673 * Trigger an rflags update that will inject or remove the trace
5674 * flags.
5675 */
5676 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5677
355be0b9 5678 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5679
4f926bf2 5680 r = 0;
d0bfb940 5681
2122ff5e 5682out:
b6c7a5dc
HB		 5683
5684 return r;
5685}
5686
8b006791
ZX		 5687/*
5688 * Translate a guest virtual address to a guest physical address.
5689 */
5690int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5691 struct kvm_translation *tr)
5692{
5693 unsigned long vaddr = tr->linear_address;
5694 gpa_t gpa;
f656ce01 5695 int idx;
8b006791 5696
f656ce01 5697 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5698 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5699 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5700 tr->physical_address = gpa;
5701 tr->valid = gpa != UNMAPPED_GVA;
5702 tr->writeable = 1;
5703 tr->usermode = 0;
8b006791
ZX		 5704
5705 return 0;
5706}
5707
d0752060
HB		 5708int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5709{
98918833
SY		 5710 struct i387_fxsave_struct *fxsave =
5711 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5712
d0752060
HB		 5713 memcpy(fpu->fpr, fxsave->st_space, 128);
5714 fpu->fcw = fxsave->cwd;
5715 fpu->fsw = fxsave->swd;
5716 fpu->ftwx = fxsave->twd;
5717 fpu->last_opcode = fxsave->fop;
5718 fpu->last_ip = fxsave->rip;
5719 fpu->last_dp = fxsave->rdp;
5720 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5721
d0752060
HB		 5722 return 0;
5723}
5724
5725int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5726{
98918833
SY		 5727 struct i387_fxsave_struct *fxsave =
5728 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5729
d0752060
HB		 5730 memcpy(fxsave->st_space, fpu->fpr, 128);
5731 fxsave->cwd = fpu->fcw;
5732 fxsave->swd = fpu->fsw;
5733 fxsave->twd = fpu->ftwx;
5734 fxsave->fop = fpu->last_opcode;
5735 fxsave->rip = fpu->last_ip;
5736 fxsave->rdp = fpu->last_dp;
5737 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5738
d0752060
HB		 5739 return 0;
5740}
5741
10ab25cd 5742int fx_init(struct kvm_vcpu *vcpu)
d0752060 5743{
10ab25cd
JK		 5744 int err;
5745
5746 err = fpu_alloc(&vcpu->arch.guest_fpu);
5747 if (err)
5748 return err;
5749
98918833 5750 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5751
2acf923e
DC		 5752 /*
5753 * Ensure guest xcr0 is valid for loading
5754 */
5755 vcpu->arch.xcr0 = XSTATE_FP;
5756
ad312c7c 5757 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5758
5759 return 0;
d0752060
HB		 5760}
5761EXPORT_SYMBOL_GPL(fx_init);
5762
98918833
SY		 5763static void fx_free(struct kvm_vcpu *vcpu)
5764{
5765 fpu_free(&vcpu->arch.guest_fpu);
5766}
5767
d0752060
HB		 5768void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5769{
2608d7a1 5770 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5771 return;
5772
2acf923e
DC		 5773 /*
5774 * Restore all possible states in the guest,
5775 * and assume host would use all available bits.
5776 * Guest xcr0 would be loaded later.
5777 */
5778 kvm_put_guest_xcr0(vcpu);
d0752060 5779 vcpu->guest_fpu_loaded = 1;
7cf30855 5780 unlazy_fpu(current);
98918833 5781 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5782 trace_kvm_fpu(1);
d0752060 5783}
d0752060
HB		 5784
5785void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5786{
2acf923e
DC		 5787 kvm_put_guest_xcr0(vcpu);
5788
d0752060
HB		 5789 if (!vcpu->guest_fpu_loaded)
5790 return;
5791
5792 vcpu->guest_fpu_loaded = 0;
98918833 5793 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5794 ++vcpu->stat.fpu_reload;
a8eeb04a 5795 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5796 trace_kvm_fpu(0);
d0752060 5797}
e9b11c17
ZX		 5798
5799void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5800{
12f9a48f 5801 kvmclock_reset(vcpu);
7f1ea208 5802
f5f48ee1 5803 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5804 fx_free(vcpu);
e9b11c17
ZX		 5805 kvm_x86_ops->vcpu_free(vcpu);
5806}
5807
5808struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5809 unsigned int id)
5810{
6755bae8
ZA		 5811 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5812 printk_once(KERN_WARNING
5813 "kvm: SMP vm created on host with unstable TSC; "
5814 "guest TSC will not be reliable\n");
26e5215f
AK		 5815 return kvm_x86_ops->vcpu_create(kvm, id);
5816}
e9b11c17 5817
26e5215f
AK		 5818int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5819{
5820 int r;
e9b11c17 5821
0bed3b56 5822 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5823 vcpu_load(vcpu);
5824 r = kvm_arch_vcpu_reset(vcpu);
5825 if (r == 0)
5826 r = kvm_mmu_setup(vcpu);
5827 vcpu_put(vcpu);
e9b11c17 5828
26e5215f 5829 return r;
e9b11c17
ZX		 5830}
5831
d40ccc62 5832void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 5833{
344d9588
GN		 5834 vcpu->arch.apf.msr_val = 0;
5835
e9b11c17
ZX		 5836 vcpu_load(vcpu);
5837 kvm_mmu_unload(vcpu);
5838 vcpu_put(vcpu);
5839
98918833 5840 fx_free(vcpu);
e9b11c17
ZX		 5841 kvm_x86_ops->vcpu_free(vcpu);
5842}
5843
5844int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5845{
7460fb4a
AK		 5846 atomic_set(&vcpu->arch.nmi_queued, 0);
5847 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 5848 vcpu->arch.nmi_injected = false;
5849
42dbaa5a
JK		 5850 vcpu->arch.switch_db_regs = 0;
5851 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5852 vcpu->arch.dr6 = DR6_FIXED_1;
5853 vcpu->arch.dr7 = DR7_FIXED_1;
5854
3842d135 5855 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 5856 vcpu->arch.apf.msr_val = 0;
c9aaa895 5857 vcpu->arch.st.msr_val = 0;
3842d135 5858
12f9a48f
GC		 5859 kvmclock_reset(vcpu);
5860
af585b92
GN		 5861 kvm_clear_async_pf_completion_queue(vcpu);
5862 kvm_async_pf_hash_reset(vcpu);
5863 vcpu->arch.apf.halted = false;
3842d135 5864
e9b11c17
ZX		 5865 return kvm_x86_ops->vcpu_reset(vcpu);
5866}
5867
10474ae8 5868int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5869{
ca84d1a2
ZA		 5870 struct kvm *kvm;
5871 struct kvm_vcpu *vcpu;
5872 int i;
18863bdd
AK		 5873
5874 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 5875 list_for_each_entry(kvm, &vm_list, vm_list)
5876 kvm_for_each_vcpu(i, vcpu, kvm)
5877 if (vcpu->cpu == smp_processor_id())
c285545f 5878 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10474ae8 5879 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5880}
5881
5882void kvm_arch_hardware_disable(void *garbage)
5883{
5884 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5885 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5886}
5887
5888int kvm_arch_hardware_setup(void)
5889{
5890 return kvm_x86_ops->hardware_setup();
5891}
5892
5893void kvm_arch_hardware_unsetup(void)
5894{
5895 kvm_x86_ops->hardware_unsetup();
5896}
5897
5898void kvm_arch_check_processor_compat(void *rtn)
5899{
5900 kvm_x86_ops->check_processor_compatibility(rtn);
5901}
5902
5903int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5904{
5905 struct page *page;
5906 struct kvm *kvm;
5907 int r;
5908
5909 BUG_ON(vcpu->kvm == NULL);
5910 kvm = vcpu->kvm;
5911
9aabc88f 5912 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 5913 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5914 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5915 else
a4535290 5916 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5917
5918 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5919 if (!page) {
5920 r = -ENOMEM;
5921 goto fail;
5922 }
ad312c7c 5923 vcpu->arch.pio_data = page_address(page);
e9b11c17 5924
1e993611 5925 kvm_init_tsc_catchup(vcpu, max_tsc_khz);
c285545f 5926
e9b11c17
ZX		 5927 r = kvm_mmu_create(vcpu);
5928 if (r < 0)
5929 goto fail_free_pio_data;
5930
5931 if (irqchip_in_kernel(kvm)) {
5932 r = kvm_create_lapic(vcpu);
5933 if (r < 0)
5934 goto fail_mmu_destroy;
5935 }
5936
890ca9ae
HY		 5937 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5938 GFP_KERNEL);
5939 if (!vcpu->arch.mce_banks) {
5940 r = -ENOMEM;
443c39bc 5941 goto fail_free_lapic;
890ca9ae
HY		 5942 }
5943 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5944
f5f48ee1
SY		 5945 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
5946 goto fail_free_mce_banks;
5947
af585b92
GN		 5948 kvm_async_pf_hash_reset(vcpu);
5949
e9b11c17 5950 return 0;
f5f48ee1
SY		 5951fail_free_mce_banks:
5952 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 5953fail_free_lapic:
5954 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5955fail_mmu_destroy:
5956 kvm_mmu_destroy(vcpu);
5957fail_free_pio_data:
ad312c7c 5958 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5959fail:
5960 return r;
5961}
5962
5963void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5964{
f656ce01
MT		 5965 int idx;
5966
36cb93fd 5967 kfree(vcpu->arch.mce_banks);
e9b11c17 5968 kvm_free_lapic(vcpu);
f656ce01 5969 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5970 kvm_mmu_destroy(vcpu);
f656ce01 5971 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5972 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5973}
d19a9cd2 5974
d89f5eff 5975int kvm_arch_init_vm(struct kvm *kvm)
d19a9cd2 5976{
f05e70ac 5977 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5978 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5979
5550af4d
SY		 5980 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5981 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5982
038f8c11 5983 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 5984
d89f5eff 5985 return 0;
d19a9cd2
ZX		 5986}
5987
5988static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5989{
5990 vcpu_load(vcpu);
5991 kvm_mmu_unload(vcpu);
5992 vcpu_put(vcpu);
5993}
5994
5995static void kvm_free_vcpus(struct kvm *kvm)
5996{
5997 unsigned int i;
988a2cae 5998 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5999
6000 /*
6001 * Unpin any mmu pages first.
6002 */
af585b92
GN		 6003 kvm_for_each_vcpu(i, vcpu, kvm) {
6004 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6005 kvm_unload_vcpu_mmu(vcpu);
af585b92 6006 }
988a2cae
GN		 6007 kvm_for_each_vcpu(i, vcpu, kvm)
6008 kvm_arch_vcpu_free(vcpu);
6009
6010 mutex_lock(&kvm->lock);
6011 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6012 kvm->vcpus[i] = NULL;
d19a9cd2 6013
988a2cae
GN		 6014 atomic_set(&kvm->online_vcpus, 0);
6015 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6016}
6017
ad8ba2cd
SY		 6018void kvm_arch_sync_events(struct kvm *kvm)
6019{
ba4cef31 6020 kvm_free_all_assigned_devices(kvm);
aea924f6 6021 kvm_free_pit(kvm);
ad8ba2cd
SY		 6022}
6023
d19a9cd2
ZX		 6024void kvm_arch_destroy_vm(struct kvm *kvm)
6025{
6eb55818 6026 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6027 kfree(kvm->arch.vpic);
6028 kfree(kvm->arch.vioapic);
d19a9cd2 6029 kvm_free_vcpus(kvm);
3d45830c
AK		 6030 if (kvm->arch.apic_access_page)
6031 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6032 if (kvm->arch.ept_identity_pagetable)
6033 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2 6034}
0de10343 6035
f7784b8e
MT		 6036int kvm_arch_prepare_memory_region(struct kvm *kvm,
6037 struct kvm_memory_slot *memslot,
0de10343 6038 struct kvm_memory_slot old,
f7784b8e 6039 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6040 int user_alloc)
6041{
f7784b8e 6042 int npages = memslot->npages;
7ac77099
AK		 6043 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6044
6045 /* Prevent internal slot pages from being moved by fork()/COW. */
6046 if (memslot->id >= KVM_MEMORY_SLOTS)
6047 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6048
6049 /*To keep backward compatibility with older userspace,
6050 *x86 needs to hanlde !user_alloc case.
6051 */
6052 if (!user_alloc) {
6053 if (npages && !old.rmap) {
604b38ac
AA		 6054 unsigned long userspace_addr;
6055
72dc67a6 6056 down_write(&current->mm->mmap_sem);
604b38ac
AA		 6057 userspace_addr = do_mmap(NULL, 0,
6058 npages * PAGE_SIZE,
6059 PROT_READ | PROT_WRITE,
7ac77099 6060 map_flags,
604b38ac 6061 0);
72dc67a6 6062 up_write(&current->mm->mmap_sem);
0de10343 6063
604b38ac
AA		 6064 if (IS_ERR((void *)userspace_addr))
6065 return PTR_ERR((void *)userspace_addr);
6066
604b38ac 6067 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6068 }
6069 }
6070
f7784b8e
MT		 6071
6072 return 0;
6073}
6074
6075void kvm_arch_commit_memory_region(struct kvm *kvm,
6076 struct kvm_userspace_memory_region *mem,
6077 struct kvm_memory_slot old,
6078 int user_alloc)
6079{
6080
48c0e4e9 6081 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
f7784b8e
MT		 6082
6083 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6084 int ret;
6085
6086 down_write(&current->mm->mmap_sem);
6087 ret = do_munmap(current->mm, old.userspace_addr,
6088 old.npages * PAGE_SIZE);
6089 up_write(&current->mm->mmap_sem);
6090 if (ret < 0)
6091 printk(KERN_WARNING
6092 "kvm_vm_ioctl_set_memory_region: "
6093 "failed to munmap memory\n");
6094 }
6095
48c0e4e9
XG		 6096 if (!kvm->arch.n_requested_mmu_pages)
6097 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6098
7c8a83b7 6099 spin_lock(&kvm->mmu_lock);
48c0e4e9 6100 if (nr_mmu_pages)
0de10343 6101 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
0de10343 6102 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6103 spin_unlock(&kvm->mmu_lock);
0de10343 6104}
1d737c8a 6105
34d4cb8f
MT		 6106void kvm_arch_flush_shadow(struct kvm *kvm)
6107{
6108 kvm_mmu_zap_all(kvm);
8986ecc0 6109 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6110}
6111
1d737c8a
ZX		 6112int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6113{
af585b92
GN		 6114 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6115 !vcpu->arch.apf.halted)
6116 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100 6117 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
7460fb4a 6118 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 6119 (kvm_arch_interrupt_allowed(vcpu) &&
6120 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6121}
5736199a 6122
5736199a
ZX		 6123void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6124{
32f88400
MT		 6125 int me;
6126 int cpu = vcpu->cpu;
5736199a
ZX		 6127
6128 if (waitqueue_active(&vcpu->wq)) {
6129 wake_up_interruptible(&vcpu->wq);
6130 ++vcpu->stat.halt_wakeup;
6131 }
32f88400
MT		 6132
6133 me = get_cpu();
6134 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
6b7e2d09 6135 if (kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE)
32f88400 6136 smp_send_reschedule(cpu);
e9571ed5 6137 put_cpu();
5736199a 6138}
78646121
GN		 6139
6140int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6141{
6142 return kvm_x86_ops->interrupt_allowed(vcpu);
6143}
229456fc 6144
f92653ee
JK		 6145bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6146{
6147 unsigned long current_rip = kvm_rip_read(vcpu) +
6148 get_segment_base(vcpu, VCPU_SREG_CS);
6149
6150 return current_rip == linear_rip;
6151}
6152EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6153
94fe45da
JK		 6154unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6155{
6156 unsigned long rflags;
6157
6158 rflags = kvm_x86_ops->get_rflags(vcpu);
6159 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6160 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6161 return rflags;
6162}
6163EXPORT_SYMBOL_GPL(kvm_get_rflags);
6164
6165void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6166{
6167 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6168 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6169 rflags |= X86_EFLAGS_TF;
94fe45da 6170 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6171 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6172}
6173EXPORT_SYMBOL_GPL(kvm_set_rflags);
6174
56028d08
GN		 6175void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6176{
6177 int r;
6178
fb67e14f 6179 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6180 is_error_page(work->page))
56028d08
GN		 6181 return;
6182
6183 r = kvm_mmu_reload(vcpu);
6184 if (unlikely(r))
6185 return;
6186
fb67e14f
XG		 6187 if (!vcpu->arch.mmu.direct_map &&
6188 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6189 return;
6190
56028d08
GN		 6191 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6192}
6193
af585b92
GN		 6194static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6195{
6196 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6197}
6198
6199static inline u32 kvm_async_pf_next_probe(u32 key)
6200{
6201 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6202}
6203
6204static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6205{
6206 u32 key = kvm_async_pf_hash_fn(gfn);
6207
6208 while (vcpu->arch.apf.gfns[key] != ~0)
6209 key = kvm_async_pf_next_probe(key);
6210
6211 vcpu->arch.apf.gfns[key] = gfn;
6212}
6213
6214static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6215{
6216 int i;
6217 u32 key = kvm_async_pf_hash_fn(gfn);
6218
6219 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6220 (vcpu->arch.apf.gfns[key] != gfn &&
6221 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6222 key = kvm_async_pf_next_probe(key);
6223
6224 return key;
6225}
6226
6227bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6228{
6229 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6230}
6231
6232static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6233{
6234 u32 i, j, k;
6235
6236 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6237 while (true) {
6238 vcpu->arch.apf.gfns[i] = ~0;
6239 do {
6240 j = kvm_async_pf_next_probe(j);
6241 if (vcpu->arch.apf.gfns[j] == ~0)
6242 return;
6243 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6244 /*
6245 * k lies cyclically in ]i,j]
6246 * | i.k.j |
6247 * |....j i.k.| or |.k..j i...|
6248 */
6249 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6250 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6251 i = j;
6252 }
6253}
6254
7c90705b
GN		 6255static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6256{
6257
6258 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6259 sizeof(val));
6260}
6261
af585b92
GN		 6262void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6263 struct kvm_async_pf *work)
6264{
6389ee94
AK		 6265 struct x86_exception fault;
6266
7c90705b 6267 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6268 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6269
6270 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6271 (vcpu->arch.apf.send_user_only &&
6272 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6273 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6274 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6275 fault.vector = PF_VECTOR;
6276 fault.error_code_valid = true;
6277 fault.error_code = 0;
6278 fault.nested_page_fault = false;
6279 fault.address = work->arch.token;
6280 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6281 }
af585b92
GN		 6282}
6283
6284void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6285 struct kvm_async_pf *work)
6286{
6389ee94
AK		 6287 struct x86_exception fault;
6288
7c90705b
GN		 6289 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6290 if (is_error_page(work->page))
6291 work->arch.token = ~0; /* broadcast wakeup */
6292 else
6293 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6294
6295 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6296 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6297 fault.vector = PF_VECTOR;
6298 fault.error_code_valid = true;
6299 fault.error_code = 0;
6300 fault.nested_page_fault = false;
6301 fault.address = work->arch.token;
6302 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6303 }
e6d53e3b 6304 vcpu->arch.apf.halted = false;
7c90705b
GN		 6305}
6306
6307bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6308{
6309 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6310 return true;
6311 else
6312 return !kvm_event_needs_reinjection(vcpu) &&
6313 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6314}
6315
229456fc
MT		 6316EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6317EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6318EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6319EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6320EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6321EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6322EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6323EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6324EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6325EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6326EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6327EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
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