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KVM: SVM: Add MSR-based feature support for serializing LFENCE
[mirror_ubuntu-jammy-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
b0c39dc6 70#include <asm/mshyperv.h>
0092e434 71#include <asm/hypervisor.h>
043405e1 72
d1898b73
DH		 73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
313a3dc7 76#define MAX_IO_MSRS 256
890ca9ae 77#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 80
0f65dd70
AK		 81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
50a37eb4
JR		 84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
1260edbe
LJ		 89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 91#else
1260edbe 92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 93#endif
313a3dc7 94
ba1389b7
AK		 95#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 97
c519265f
RK		 98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 100
cb142eb7 101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 102static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 103static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 105
893590c7 106struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 107EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 108
893590c7 109static bool __read_mostly ignore_msrs = 0;
476bc001 110module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 111
fab0aa3b
EM		 112static bool __read_mostly report_ignored_msrs = true;
113module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
114
9ed96e87
MT		 115unsigned int min_timer_period_us = 500;
116module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
117
630994b3
MT		 118static bool __read_mostly kvmclock_periodic_sync = true;
119module_param(kvmclock_periodic_sync, bool, S_IRUGO);
120
893590c7 121bool __read_mostly kvm_has_tsc_control;
92a1f12d 122EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 123u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 124EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 125u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
126EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
127u64 __read_mostly kvm_max_tsc_scaling_ratio;
128EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 129u64 __read_mostly kvm_default_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 131
cc578287 132/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 133static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 134module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
135
d0659d94 136/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 137unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 138module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
139
52004014
FW		 140static bool __read_mostly vector_hashing = true;
141module_param(vector_hashing, bool, S_IRUGO);
142
18863bdd
AK		 143#define KVM_NR_SHARED_MSRS 16
144
145struct kvm_shared_msrs_global {
146 int nr;
2bf78fa7 147 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 148};
149
150struct kvm_shared_msrs {
151 struct user_return_notifier urn;
152 bool registered;
2bf78fa7
SY		 153 struct kvm_shared_msr_values {
154 u64 host;
155 u64 curr;
156 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 157};
158
159static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 160static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 161
417bc304 162struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 163 { "pf_fixed", VCPU_STAT(pf_fixed) },
164 { "pf_guest", VCPU_STAT(pf_guest) },
165 { "tlb_flush", VCPU_STAT(tlb_flush) },
166 { "invlpg", VCPU_STAT(invlpg) },
167 { "exits", VCPU_STAT(exits) },
168 { "io_exits", VCPU_STAT(io_exits) },
169 { "mmio_exits", VCPU_STAT(mmio_exits) },
170 { "signal_exits", VCPU_STAT(signal_exits) },
171 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 172 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 173 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 174 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 175 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 176 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 177 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 178 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 179 { "request_irq", VCPU_STAT(request_irq_exits) },
180 { "irq_exits", VCPU_STAT(irq_exits) },
181 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 182 { "fpu_reload", VCPU_STAT(fpu_reload) },
183 { "insn_emulation", VCPU_STAT(insn_emulation) },
184 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 185 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 186 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 187 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 188 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
189 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
190 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
191 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
192 { "mmu_flooded", VM_STAT(mmu_flooded) },
193 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 194 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 195 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 196 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 197 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 198 { "max_mmu_page_hash_collisions",
199 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 200 { NULL }
201};
202
2acf923e
DC		 203u64 __read_mostly host_xcr0;
204
b6785def 205static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 206
af585b92
GN		 207static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
208{
209 int i;
210 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
211 vcpu->arch.apf.gfns[i] = ~0;
212}
213
18863bdd
AK		 214static void kvm_on_user_return(struct user_return_notifier *urn)
215{
216 unsigned slot;
18863bdd
AK		 217 struct kvm_shared_msrs *locals
218 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 219 struct kvm_shared_msr_values *values;
1650b4eb
IA		 220 unsigned long flags;
221
222 /*
223 * Disabling irqs at this point since the following code could be
224 * interrupted and executed through kvm_arch_hardware_disable()
225 */
226 local_irq_save(flags);
227 if (locals->registered) {
228 locals->registered = false;
229 user_return_notifier_unregister(urn);
230 }
231 local_irq_restore(flags);
18863bdd 232 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 233 values = &locals->values[slot];
234 if (values->host != values->curr) {
235 wrmsrl(shared_msrs_global.msrs[slot], values->host);
236 values->curr = values->host;
18863bdd
AK		 237 }
238 }
18863bdd
AK		 239}
240
2bf78fa7 241static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 242{
18863bdd 243 u64 value;
013f6a5d
MT		 244 unsigned int cpu = smp_processor_id();
245 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 246
2bf78fa7
SY		 247 /* only read, and nobody should modify it at this time,
248 * so don't need lock */
249 if (slot >= shared_msrs_global.nr) {
250 printk(KERN_ERR "kvm: invalid MSR slot!");
251 return;
252 }
253 rdmsrl_safe(msr, &value);
254 smsr->values[slot].host = value;
255 smsr->values[slot].curr = value;
256}
257
258void kvm_define_shared_msr(unsigned slot, u32 msr)
259{
0123be42 260 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 261 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 262 if (slot >= shared_msrs_global.nr)
263 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 264}
265EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
266
267static void kvm_shared_msr_cpu_online(void)
268{
269 unsigned i;
18863bdd
AK		 270
271 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 272 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 273}
274
8b3c3104 275int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 276{
013f6a5d
MT		 277 unsigned int cpu = smp_processor_id();
278 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 279 int err;
18863bdd 280
2bf78fa7 281 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 282 return 0;
2bf78fa7 283 smsr->values[slot].curr = value;
8b3c3104
AH		 284 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
285 if (err)
286 return 1;
287
18863bdd
AK		 288 if (!smsr->registered) {
289 smsr->urn.on_user_return = kvm_on_user_return;
290 user_return_notifier_register(&smsr->urn);
291 smsr->registered = true;
292 }
8b3c3104 293 return 0;
18863bdd
AK		 294}
295EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
296
13a34e06 297static void drop_user_return_notifiers(void)
3548bab5 298{
013f6a5d
MT		 299 unsigned int cpu = smp_processor_id();
300 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 301
302 if (smsr->registered)
303 kvm_on_user_return(&smsr->urn);
304}
305
6866b83e
CO		 306u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
307{
8a5a87d9 308 return vcpu->arch.apic_base;
6866b83e
CO		 309}
310EXPORT_SYMBOL_GPL(kvm_get_apic_base);
311
58cb628d
JK		 312int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
313{
314 u64 old_state = vcpu->arch.apic_base &
315 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
316 u64 new_state = msr_info->data &
317 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
d6321d49
RK		 318 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
319 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 320
d3802286
JM		 321 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
322 return 1;
58cb628d 323 if (!msr_info->host_initiated &&
d3802286 324 ((new_state == MSR_IA32_APICBASE_ENABLE &&
58cb628d
JK		 325 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
326 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
327 old_state == 0)))
328 return 1;
329
330 kvm_lapic_set_base(vcpu, msr_info->data);
331 return 0;
6866b83e
CO		 332}
333EXPORT_SYMBOL_GPL(kvm_set_apic_base);
334
2605fc21 335asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 336{
337 /* Fault while not rebooting. We want the trace. */
338 BUG();
339}
340EXPORT_SYMBOL_GPL(kvm_spurious_fault);
341
3fd28fce
ED		 342#define EXCPT_BENIGN 0
343#define EXCPT_CONTRIBUTORY 1
344#define EXCPT_PF 2
345
346static int exception_class(int vector)
347{
348 switch (vector) {
349 case PF_VECTOR:
350 return EXCPT_PF;
351 case DE_VECTOR:
352 case TS_VECTOR:
353 case NP_VECTOR:
354 case SS_VECTOR:
355 case GP_VECTOR:
356 return EXCPT_CONTRIBUTORY;
357 default:
358 break;
359 }
360 return EXCPT_BENIGN;
361}
362
d6e8c854
NA		 363#define EXCPT_FAULT 0
364#define EXCPT_TRAP 1
365#define EXCPT_ABORT 2
366#define EXCPT_INTERRUPT 3
367
368static int exception_type(int vector)
369{
370 unsigned int mask;
371
372 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
373 return EXCPT_INTERRUPT;
374
375 mask = 1 << vector;
376
377 /* #DB is trap, as instruction watchpoints are handled elsewhere */
378 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
379 return EXCPT_TRAP;
380
381 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
382 return EXCPT_ABORT;
383
384 /* Reserved exceptions will result in fault */
385 return EXCPT_FAULT;
386}
387
3fd28fce 388static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 389 unsigned nr, bool has_error, u32 error_code,
390 bool reinject)
3fd28fce
ED		 391{
392 u32 prev_nr;
393 int class1, class2;
394
3842d135
AK		 395 kvm_make_request(KVM_REQ_EVENT, vcpu);
396
664f8e26 397 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 398 queue:
3ffb2468
NA		 399 if (has_error && !is_protmode(vcpu))
400 has_error = false;
664f8e26
WL		 401 if (reinject) {
402 /*
403 * On vmentry, vcpu->arch.exception.pending is only
404 * true if an event injection was blocked by
405 * nested_run_pending. In that case, however,
406 * vcpu_enter_guest requests an immediate exit,
407 * and the guest shouldn't proceed far enough to
408 * need reinjection.
409 */
410 WARN_ON_ONCE(vcpu->arch.exception.pending);
411 vcpu->arch.exception.injected = true;
412 } else {
413 vcpu->arch.exception.pending = true;
414 vcpu->arch.exception.injected = false;
415 }
3fd28fce
ED		 416 vcpu->arch.exception.has_error_code = has_error;
417 vcpu->arch.exception.nr = nr;
418 vcpu->arch.exception.error_code = error_code;
419 return;
420 }
421
422 /* to check exception */
423 prev_nr = vcpu->arch.exception.nr;
424 if (prev_nr == DF_VECTOR) {
425 /* triple fault -> shutdown */
a8eeb04a 426 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 427 return;
428 }
429 class1 = exception_class(prev_nr);
430 class2 = exception_class(nr);
431 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
432 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 433 /*
434 * Generate double fault per SDM Table 5-5. Set
435 * exception.pending = true so that the double fault
436 * can trigger a nested vmexit.
437 */
3fd28fce 438 vcpu->arch.exception.pending = true;
664f8e26 439 vcpu->arch.exception.injected = false;
3fd28fce
ED		 440 vcpu->arch.exception.has_error_code = true;
441 vcpu->arch.exception.nr = DF_VECTOR;
442 vcpu->arch.exception.error_code = 0;
443 } else
444 /* replace previous exception with a new one in a hope
445 that instruction re-execution will regenerate lost
446 exception */
447 goto queue;
448}
449
298101da
AK		 450void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
451{
ce7ddec4 452 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 453}
454EXPORT_SYMBOL_GPL(kvm_queue_exception);
455
ce7ddec4
JR		 456void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
457{
458 kvm_multiple_exception(vcpu, nr, false, 0, true);
459}
460EXPORT_SYMBOL_GPL(kvm_requeue_exception);
461
6affcbed 462int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 463{
db8fcefa
AP		 464 if (err)
465 kvm_inject_gp(vcpu, 0);
466 else
6affcbed
KH		 467 return kvm_skip_emulated_instruction(vcpu);
468
469 return 1;
db8fcefa
AP		 470}
471EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 472
6389ee94 473void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 474{
475 ++vcpu->stat.pf_guest;
adfe20fb
WL		 476 vcpu->arch.exception.nested_apf =
477 is_guest_mode(vcpu) && fault->async_page_fault;
478 if (vcpu->arch.exception.nested_apf)
479 vcpu->arch.apf.nested_apf_token = fault->address;
480 else
481 vcpu->arch.cr2 = fault->address;
6389ee94 482 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 483}
27d6c865 484EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 485
ef54bcfe 486static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 487{
6389ee94
AK		 488 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
489 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 490 else
6389ee94 491 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 492
493 return fault->nested_page_fault;
d4f8cf66
JR		 494}
495
3419ffc8
SY		 496void kvm_inject_nmi(struct kvm_vcpu *vcpu)
497{
7460fb4a
AK		 498 atomic_inc(&vcpu->arch.nmi_queued);
499 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 500}
501EXPORT_SYMBOL_GPL(kvm_inject_nmi);
502
298101da
AK		 503void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
504{
ce7ddec4 505 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 506}
507EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
508
ce7ddec4
JR		 509void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
510{
511 kvm_multiple_exception(vcpu, nr, true, error_code, true);
512}
513EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
514
0a79b009
AK		 515/*
516 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
517 * a #GP and return false.
518 */
519bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 520{
0a79b009
AK		 521 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
522 return true;
523 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
524 return false;
298101da 525}
0a79b009 526EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 527
16f8a6f9
NA		 528bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
529{
530 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
531 return true;
532
533 kvm_queue_exception(vcpu, UD_VECTOR);
534 return false;
535}
536EXPORT_SYMBOL_GPL(kvm_require_dr);
537
ec92fe44
JR		 538/*
539 * This function will be used to read from the physical memory of the currently
54bf36aa 540 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 541 * can read from guest physical or from the guest's guest physical memory.
542 */
543int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
544 gfn_t ngfn, void *data, int offset, int len,
545 u32 access)
546{
54987b7a 547 struct x86_exception exception;
ec92fe44
JR		 548 gfn_t real_gfn;
549 gpa_t ngpa;
550
551 ngpa = gfn_to_gpa(ngfn);
54987b7a 552 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 553 if (real_gfn == UNMAPPED_GVA)
554 return -EFAULT;
555
556 real_gfn = gpa_to_gfn(real_gfn);
557
54bf36aa 558 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 559}
560EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
561
69b0049a 562static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 563 void *data, int offset, int len, u32 access)
564{
565 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
566 data, offset, len, access);
567}
568
a03490ed
CO		 569/*
570 * Load the pae pdptrs. Return true is they are all valid.
571 */
ff03a073 572int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 573{
574 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
575 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
576 int i;
577 int ret;
ff03a073 578 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 579
ff03a073
JR		 580 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
581 offset * sizeof(u64), sizeof(pdpte),
582 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 583 if (ret < 0) {
584 ret = 0;
585 goto out;
586 }
587 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 588 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 589 (pdpte[i] &
590 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 591 ret = 0;
592 goto out;
593 }
594 }
595 ret = 1;
596
ff03a073 597 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 598 __set_bit(VCPU_EXREG_PDPTR,
599 (unsigned long *)&vcpu->arch.regs_avail);
600 __set_bit(VCPU_EXREG_PDPTR,
601 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 602out:
a03490ed
CO		 603
604 return ret;
605}
cc4b6871 606EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 607
9ed38ffa 608bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 609{
ff03a073 610 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 611 bool changed = true;
3d06b8bf
JR		 612 int offset;
613 gfn_t gfn;
d835dfec
AK		 614 int r;
615
616 if (is_long_mode(vcpu) || !is_pae(vcpu))
617 return false;
618
6de4f3ad
AK		 619 if (!test_bit(VCPU_EXREG_PDPTR,
620 (unsigned long *)&vcpu->arch.regs_avail))
621 return true;
622
a512177e
PB		 623 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
624 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 625 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
626 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 627 if (r < 0)
628 goto out;
ff03a073 629 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 630out:
d835dfec
AK		 631
632 return changed;
633}
9ed38ffa 634EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 635
49a9b07e 636int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 637{
aad82703 638 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 639 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 640
f9a48e6a
AK		 641 cr0 |= X86_CR0_ET;
642
ab344828 643#ifdef CONFIG_X86_64
0f12244f
GN		 644 if (cr0 & 0xffffffff00000000UL)
645 return 1;
ab344828
GN		 646#endif
647
648 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 649
0f12244f
GN		 650 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
651 return 1;
a03490ed 652
0f12244f
GN		 653 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
654 return 1;
a03490ed
CO		 655
656 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
657#ifdef CONFIG_X86_64
f6801dff 658 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 659 int cs_db, cs_l;
660
0f12244f
GN		 661 if (!is_pae(vcpu))
662 return 1;
a03490ed 663 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 664 if (cs_l)
665 return 1;
a03490ed
CO		 666 } else
667#endif
ff03a073 668 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 669 kvm_read_cr3(vcpu)))
0f12244f 670 return 1;
a03490ed
CO		 671 }
672
ad756a16
MJ		 673 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
674 return 1;
675
a03490ed 676 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 677
d170c419 678 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 679 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 680 kvm_async_pf_hash_reset(vcpu);
681 }
e5f3f027 682
aad82703
SY		 683 if ((cr0 ^ old_cr0) & update_bits)
684 kvm_mmu_reset_context(vcpu);
b18d5431 685
879ae188
LE		 686 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
687 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
688 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 689 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
690
0f12244f
GN		 691 return 0;
692}
2d3ad1f4 693EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 694
2d3ad1f4 695void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 696{
49a9b07e 697 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 698}
2d3ad1f4 699EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 700
42bdf991
MT		 701static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
702{
703 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
704 !vcpu->guest_xcr0_loaded) {
705 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 706 if (vcpu->arch.xcr0 != host_xcr0)
707 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 708 vcpu->guest_xcr0_loaded = 1;
709 }
710}
711
712static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
713{
714 if (vcpu->guest_xcr0_loaded) {
715 if (vcpu->arch.xcr0 != host_xcr0)
716 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
717 vcpu->guest_xcr0_loaded = 0;
718 }
719}
720
69b0049a 721static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 722{
56c103ec
LJ		 723 u64 xcr0 = xcr;
724 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 725 u64 valid_bits;
2acf923e
DC		 726
727 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
728 if (index != XCR_XFEATURE_ENABLED_MASK)
729 return 1;
d91cab78 730 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 731 return 1;
d91cab78 732 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 733 return 1;
46c34cb0
PB		 734
735 /*
736 * Do not allow the guest to set bits that we do not support
737 * saving. However, xcr0 bit 0 is always set, even if the
738 * emulated CPU does not support XSAVE (see fx_init).
739 */
d91cab78 740 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 741 if (xcr0 & ~valid_bits)
2acf923e 742 return 1;
46c34cb0 743
d91cab78
DH		 744 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
745 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 746 return 1;
747
d91cab78
DH		 748 if (xcr0 & XFEATURE_MASK_AVX512) {
749 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 750 return 1;
d91cab78 751 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 752 return 1;
753 }
2acf923e 754 vcpu->arch.xcr0 = xcr0;
56c103ec 755
d91cab78 756 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 757 kvm_update_cpuid(vcpu);
2acf923e
DC		 758 return 0;
759}
760
761int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
762{
764bcbc5
Z		 763 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
764 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 765 kvm_inject_gp(vcpu, 0);
766 return 1;
767 }
768 return 0;
769}
770EXPORT_SYMBOL_GPL(kvm_set_xcr);
771
a83b29c6 772int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 773{
fc78f519 774 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 775 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 776 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 777
0f12244f
GN		 778 if (cr4 & CR4_RESERVED_BITS)
779 return 1;
a03490ed 780
d6321d49 781 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 782 return 1;
783
d6321d49 784 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 785 return 1;
786
d6321d49 787 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 788 return 1;
789
d6321d49 790 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 791 return 1;
792
d6321d49 793 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 794 return 1;
795
fd8cb433 796 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 797 return 1;
798
ae3e61e1
PB		 799 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
800 return 1;
801
a03490ed 802 if (is_long_mode(vcpu)) {
0f12244f
GN		 803 if (!(cr4 & X86_CR4_PAE))
804 return 1;
a2edf57f
AK		 805 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
806 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 807 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
808 kvm_read_cr3(vcpu)))
0f12244f
GN		 809 return 1;
810
ad756a16 811 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 812 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 813 return 1;
814
815 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
816 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
817 return 1;
818 }
819
5e1746d6 820 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 821 return 1;
a03490ed 822
ad756a16
MJ		 823 if (((cr4 ^ old_cr4) & pdptr_bits) ||
824 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 825 kvm_mmu_reset_context(vcpu);
0f12244f 826
b9baba86 827 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 828 kvm_update_cpuid(vcpu);
2acf923e 829
0f12244f
GN		 830 return 0;
831}
2d3ad1f4 832EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 833
2390218b 834int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 835{
ac146235 836#ifdef CONFIG_X86_64
9d88fca7 837 cr3 &= ~CR3_PCID_INVD;
ac146235 838#endif
9d88fca7 839
9f8fe504 840 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 841 kvm_mmu_sync_roots(vcpu);
77c3913b 842 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 843 return 0;
d835dfec
AK		 844 }
845
d1cd3ce9
YZ		 846 if (is_long_mode(vcpu) &&
847 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62)))
848 return 1;
849 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 850 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 851 return 1;
a03490ed 852
0f12244f 853 vcpu->arch.cr3 = cr3;
aff48baa 854 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 855 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 856 return 0;
857}
2d3ad1f4 858EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 859
eea1cff9 860int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 861{
0f12244f
GN		 862 if (cr8 & CR8_RESERVED_BITS)
863 return 1;
35754c98 864 if (lapic_in_kernel(vcpu))
a03490ed
CO		 865 kvm_lapic_set_tpr(vcpu, cr8);
866 else
ad312c7c 867 vcpu->arch.cr8 = cr8;
0f12244f
GN		 868 return 0;
869}
2d3ad1f4 870EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 871
2d3ad1f4 872unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 873{
35754c98 874 if (lapic_in_kernel(vcpu))
a03490ed
CO		 875 return kvm_lapic_get_cr8(vcpu);
876 else
ad312c7c 877 return vcpu->arch.cr8;
a03490ed 878}
2d3ad1f4 879EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 880
ae561ede
NA		 881static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
882{
883 int i;
884
885 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
886 for (i = 0; i < KVM_NR_DB_REGS; i++)
887 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
888 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
889 }
890}
891
73aaf249
JK		 892static void kvm_update_dr6(struct kvm_vcpu *vcpu)
893{
894 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
895 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
896}
897
c8639010
JK		 898static void kvm_update_dr7(struct kvm_vcpu *vcpu)
899{
900 unsigned long dr7;
901
902 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
903 dr7 = vcpu->arch.guest_debug_dr7;
904 else
905 dr7 = vcpu->arch.dr7;
906 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 907 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
908 if (dr7 & DR7_BP_EN_MASK)
909 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 910}
911
6f43ed01
NA		 912static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
913{
914 u64 fixed = DR6_FIXED_1;
915
d6321d49 916 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 917 fixed |= DR6_RTM;
918 return fixed;
919}
920
338dbc97 921static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 922{
923 switch (dr) {
924 case 0 ... 3:
925 vcpu->arch.db[dr] = val;
926 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
927 vcpu->arch.eff_db[dr] = val;
928 break;
929 case 4:
020df079
GN		 930 /* fall through */
931 case 6:
338dbc97
GN		 932 if (val & 0xffffffff00000000ULL)
933 return -1; /* #GP */
6f43ed01 934 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 935 kvm_update_dr6(vcpu);
020df079
GN		 936 break;
937 case 5:
020df079
GN		 938 /* fall through */
939 default: /* 7 */
338dbc97
GN		 940 if (val & 0xffffffff00000000ULL)
941 return -1; /* #GP */
020df079 942 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 943 kvm_update_dr7(vcpu);
020df079
GN		 944 break;
945 }
946
947 return 0;
948}
338dbc97
GN		 949
950int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
951{
16f8a6f9 952 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 953 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 954 return 1;
955 }
956 return 0;
338dbc97 957}
020df079
GN		 958EXPORT_SYMBOL_GPL(kvm_set_dr);
959
16f8a6f9 960int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 961{
962 switch (dr) {
963 case 0 ... 3:
964 *val = vcpu->arch.db[dr];
965 break;
966 case 4:
020df079
GN		 967 /* fall through */
968 case 6:
73aaf249
JK		 969 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
970 *val = vcpu->arch.dr6;
971 else
972 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 973 break;
974 case 5:
020df079
GN		 975 /* fall through */
976 default: /* 7 */
977 *val = vcpu->arch.dr7;
978 break;
979 }
338dbc97
GN		 980 return 0;
981}
020df079
GN		 982EXPORT_SYMBOL_GPL(kvm_get_dr);
983
022cd0e8
AK		 984bool kvm_rdpmc(struct kvm_vcpu *vcpu)
985{
986 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
987 u64 data;
988 int err;
989
c6702c9d 990 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 991 if (err)
992 return err;
993 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
994 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
995 return err;
996}
997EXPORT_SYMBOL_GPL(kvm_rdpmc);
998
043405e1
CO		 999/*
1000 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1001 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1002 *
1003 * This list is modified at module load time to reflect the
e3267cbb 1004 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1005 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1006 * may depend on host virtualization features rather than host cpu features.
043405e1 1007 */
e3267cbb 1008
043405e1
CO		 1009static u32 msrs_to_save[] = {
1010 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1011 MSR_STAR,
043405e1
CO		 1012#ifdef CONFIG_X86_64
1013 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1014#endif
b3897a49 1015 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1016 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
d28b387f 1017 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
043405e1
CO		 1018};
1019
1020static unsigned num_msrs_to_save;
1021
62ef68bb
PB		 1022static u32 emulated_msrs[] = {
1023 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1024 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1025 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1026 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1027 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1028 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1029 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1030 HV_X64_MSR_RESET,
11c4b1ca 1031 HV_X64_MSR_VP_INDEX,
9eec50b8 1032 HV_X64_MSR_VP_RUNTIME,
5c919412 1033 HV_X64_MSR_SCONTROL,
1f4b34f8 1034 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 1035 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1036 MSR_KVM_PV_EOI_EN,
1037
ba904635 1038 MSR_IA32_TSC_ADJUST,
a3e06bbe 1039 MSR_IA32_TSCDEADLINE,
043405e1 1040 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1041 MSR_IA32_MCG_STATUS,
1042 MSR_IA32_MCG_CTL,
c45dcc71 1043 MSR_IA32_MCG_EXT_CTL,
64d60670 1044 MSR_IA32_SMBASE,
52797bf9 1045 MSR_SMI_COUNT,
db2336a8
KH		 1046 MSR_PLATFORM_INFO,
1047 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1048};
1049
62ef68bb
PB		 1050static unsigned num_emulated_msrs;
1051
801e459a
TL		 1052/*
1053 * List of msr numbers which are used to expose MSR-based features that
1054 * can be used by a hypervisor to validate requested CPU features.
1055 */
1056static u32 msr_based_features[] = {
d1d93fa9 1057 MSR_F10H_DECFG,
801e459a
TL		 1058};
1059
1060static unsigned int num_msr_based_features;
1061
1062static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1063{
1064 struct kvm_msr_entry msr;
1065
1066 msr.index = index;
1067 if (kvm_x86_ops->get_msr_feature(&msr))
1068 return 1;
1069
1070 *data = msr.data;
1071
1072 return 0;
1073}
1074
384bb783 1075bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1076{
b69e8cae 1077 if (efer & efer_reserved_bits)
384bb783 1078 return false;
15c4a640 1079
1b4d56b8 1080 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1081 return false;
1b2fd70c 1082
1b4d56b8 1083 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1084 return false;
d8017474 1085
384bb783
JK		 1086 return true;
1087}
1088EXPORT_SYMBOL_GPL(kvm_valid_efer);
1089
1090static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1091{
1092 u64 old_efer = vcpu->arch.efer;
1093
1094 if (!kvm_valid_efer(vcpu, efer))
1095 return 1;
1096
1097 if (is_paging(vcpu)
1098 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1099 return 1;
1100
15c4a640 1101 efer &= ~EFER_LMA;
f6801dff 1102 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1103
a3d204e2
SY		 1104 kvm_x86_ops->set_efer(vcpu, efer);
1105
aad82703
SY		 1106 /* Update reserved bits */
1107 if ((efer ^ old_efer) & EFER_NX)
1108 kvm_mmu_reset_context(vcpu);
1109
b69e8cae 1110 return 0;
15c4a640
CO		 1111}
1112
f2b4b7dd
JR		 1113void kvm_enable_efer_bits(u64 mask)
1114{
1115 efer_reserved_bits &= ~mask;
1116}
1117EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1118
15c4a640
CO		 1119/*
1120 * Writes msr value into into the appropriate "register".
1121 * Returns 0 on success, non-0 otherwise.
1122 * Assumes vcpu_load() was already called.
1123 */
8fe8ab46 1124int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1125{
854e8bb1
NA		 1126 switch (msr->index) {
1127 case MSR_FS_BASE:
1128 case MSR_GS_BASE:
1129 case MSR_KERNEL_GS_BASE:
1130 case MSR_CSTAR:
1131 case MSR_LSTAR:
fd8cb433 1132 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1133 return 1;
1134 break;
1135 case MSR_IA32_SYSENTER_EIP:
1136 case MSR_IA32_SYSENTER_ESP:
1137 /*
1138 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1139 * non-canonical address is written on Intel but not on
1140 * AMD (which ignores the top 32-bits, because it does
1141 * not implement 64-bit SYSENTER).
1142 *
1143 * 64-bit code should hence be able to write a non-canonical
1144 * value on AMD. Making the address canonical ensures that
1145 * vmentry does not fail on Intel after writing a non-canonical
1146 * value, and that something deterministic happens if the guest
1147 * invokes 64-bit SYSENTER.
1148 */
fd8cb433 1149 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1150 }
8fe8ab46 1151 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1152}
854e8bb1 1153EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1154
313a3dc7
CO		 1155/*
1156 * Adapt set_msr() to msr_io()'s calling convention
1157 */
609e36d3
PB		 1158static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1159{
1160 struct msr_data msr;
1161 int r;
1162
1163 msr.index = index;
1164 msr.host_initiated = true;
1165 r = kvm_get_msr(vcpu, &msr);
1166 if (r)
1167 return r;
1168
1169 *data = msr.data;
1170 return 0;
1171}
1172
313a3dc7
CO		 1173static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1174{
8fe8ab46
WA		 1175 struct msr_data msr;
1176
1177 msr.data = *data;
1178 msr.index = index;
1179 msr.host_initiated = true;
1180 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1181}
1182
16e8d74d
MT		 1183#ifdef CONFIG_X86_64
1184struct pvclock_gtod_data {
1185 seqcount_t seq;
1186
1187 struct { /* extract of a clocksource struct */
1188 int vclock_mode;
a5a1d1c2
TG		 1189 u64 cycle_last;
1190 u64 mask;
16e8d74d
MT		 1191 u32 mult;
1192 u32 shift;
1193 } clock;
1194
cbcf2dd3
TG		 1195 u64 boot_ns;
1196 u64 nsec_base;
55dd00a7 1197 u64 wall_time_sec;
16e8d74d
MT		 1198};
1199
1200static struct pvclock_gtod_data pvclock_gtod_data;
1201
1202static void update_pvclock_gtod(struct timekeeper *tk)
1203{
1204 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1205 u64 boot_ns;
1206
876e7881 1207 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1208
1209 write_seqcount_begin(&vdata->seq);
1210
1211 /* copy pvclock gtod data */
876e7881
PZ		 1212 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1213 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1214 vdata->clock.mask = tk->tkr_mono.mask;
1215 vdata->clock.mult = tk->tkr_mono.mult;
1216 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1217
cbcf2dd3 1218 vdata->boot_ns = boot_ns;
876e7881 1219 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1220
55dd00a7
MT		 1221 vdata->wall_time_sec = tk->xtime_sec;
1222
16e8d74d
MT		 1223 write_seqcount_end(&vdata->seq);
1224}
1225#endif
1226
bab5bb39
NK		 1227void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1228{
1229 /*
1230 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1231 * vcpu_enter_guest. This function is only called from
1232 * the physical CPU that is running vcpu.
1233 */
1234 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1235}
16e8d74d 1236
18068523
GOC		 1237static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1238{
9ed3c444
AK		 1239 int version;
1240 int r;
50d0a0f9 1241 struct pvclock_wall_clock wc;
87aeb54f 1242 struct timespec64 boot;
18068523
GOC		 1243
1244 if (!wall_clock)
1245 return;
1246
9ed3c444
AK		 1247 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1248 if (r)
1249 return;
1250
1251 if (version & 1)
1252 ++version; /* first time write, random junk */
1253
1254 ++version;
18068523 1255
1dab1345
NK		 1256 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1257 return;
18068523 1258
50d0a0f9
GH		 1259 /*
1260 * The guest calculates current wall clock time by adding
34c238a1 1261 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1262 * wall clock specified here. guest system time equals host
1263 * system time for us, thus we must fill in host boot time here.
1264 */
87aeb54f 1265 getboottime64(&boot);
50d0a0f9 1266
4b648665 1267 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1268 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1269 boot = timespec64_sub(boot, ts);
4b648665 1270 }
87aeb54f 1271 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1272 wc.nsec = boot.tv_nsec;
1273 wc.version = version;
18068523
GOC		 1274
1275 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1276
1277 version++;
1278 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1279}
1280
50d0a0f9
GH		 1281static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1282{
b51012de
PB		 1283 do_shl32_div32(dividend, divisor);
1284 return dividend;
50d0a0f9
GH		 1285}
1286
3ae13faa 1287static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1288 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1289{
5f4e3f88 1290 uint64_t scaled64;
50d0a0f9
GH		 1291 int32_t shift = 0;
1292 uint64_t tps64;
1293 uint32_t tps32;
1294
3ae13faa
PB		 1295 tps64 = base_hz;
1296 scaled64 = scaled_hz;
50933623 1297 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1298 tps64 >>= 1;
1299 shift--;
1300 }
1301
1302 tps32 = (uint32_t)tps64;
50933623
JK		 1303 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1304 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1305 scaled64 >>= 1;
1306 else
1307 tps32 <<= 1;
50d0a0f9
GH		 1308 shift++;
1309 }
1310
5f4e3f88
ZA		 1311 *pshift = shift;
1312 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1313
3ae13faa
PB		 1314 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1315 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1316}
1317
d828199e 1318#ifdef CONFIG_X86_64
16e8d74d 1319static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1320#endif
16e8d74d 1321
c8076604 1322static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1323static unsigned long max_tsc_khz;
c8076604 1324
cc578287 1325static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1326{
cc578287
ZA		 1327 u64 v = (u64)khz * (1000000 + ppm);
1328 do_div(v, 1000000);
1329 return v;
1e993611
JR		 1330}
1331
381d585c
HZ		 1332static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1333{
1334 u64 ratio;
1335
1336 /* Guest TSC same frequency as host TSC? */
1337 if (!scale) {
1338 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1339 return 0;
1340 }
1341
1342 /* TSC scaling supported? */
1343 if (!kvm_has_tsc_control) {
1344 if (user_tsc_khz > tsc_khz) {
1345 vcpu->arch.tsc_catchup = 1;
1346 vcpu->arch.tsc_always_catchup = 1;
1347 return 0;
1348 } else {
1349 WARN(1, "user requested TSC rate below hardware speed\n");
1350 return -1;
1351 }
1352 }
1353
1354 /* TSC scaling required - calculate ratio */
1355 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1356 user_tsc_khz, tsc_khz);
1357
1358 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1359 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1360 user_tsc_khz);
1361 return -1;
1362 }
1363
1364 vcpu->arch.tsc_scaling_ratio = ratio;
1365 return 0;
1366}
1367
4941b8cb 1368static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1369{
cc578287
ZA		 1370 u32 thresh_lo, thresh_hi;
1371 int use_scaling = 0;
217fc9cf 1372
03ba32ca 1373 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1374 if (user_tsc_khz == 0) {
ad721883
HZ		 1375 /* set tsc_scaling_ratio to a safe value */
1376 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1377 return -1;
ad721883 1378 }
03ba32ca 1379
c285545f 1380 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1381 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1382 &vcpu->arch.virtual_tsc_shift,
1383 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1384 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1385
1386 /*
1387 * Compute the variation in TSC rate which is acceptable
1388 * within the range of tolerance and decide if the
1389 * rate being applied is within that bounds of the hardware
1390 * rate. If so, no scaling or compensation need be done.
1391 */
1392 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1393 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1394 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1395 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1396 use_scaling = 1;
1397 }
4941b8cb 1398 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1399}
1400
1401static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1402{
e26101b1 1403 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1404 vcpu->arch.virtual_tsc_mult,
1405 vcpu->arch.virtual_tsc_shift);
e26101b1 1406 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1407 return tsc;
1408}
1409
b0c39dc6
VK		 1410static inline int gtod_is_based_on_tsc(int mode)
1411{
1412 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1413}
1414
69b0049a 1415static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1416{
1417#ifdef CONFIG_X86_64
1418 bool vcpus_matched;
b48aa97e
MT		 1419 struct kvm_arch *ka = &vcpu->kvm->arch;
1420 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1421
1422 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1423 atomic_read(&vcpu->kvm->online_vcpus));
1424
7f187922
MT		 1425 /*
1426 * Once the masterclock is enabled, always perform request in
1427 * order to update it.
1428 *
1429 * In order to enable masterclock, the host clocksource must be TSC
1430 * and the vcpus need to have matched TSCs. When that happens,
1431 * perform request to enable masterclock.
1432 */
1433 if (ka->use_master_clock ||
b0c39dc6 1434 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1435 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1436
1437 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1438 atomic_read(&vcpu->kvm->online_vcpus),
1439 ka->use_master_clock, gtod->clock.vclock_mode);
1440#endif
1441}
1442
ba904635
WA		 1443static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1444{
3e3f5026 1445 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1446 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1447}
1448
35181e86
HZ		 1449/*
1450 * Multiply tsc by a fixed point number represented by ratio.
1451 *
1452 * The most significant 64-N bits (mult) of ratio represent the
1453 * integral part of the fixed point number; the remaining N bits
1454 * (frac) represent the fractional part, ie. ratio represents a fixed
1455 * point number (mult + frac * 2^(-N)).
1456 *
1457 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1458 */
1459static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1460{
1461 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1462}
1463
1464u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1465{
1466 u64 _tsc = tsc;
1467 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1468
1469 if (ratio != kvm_default_tsc_scaling_ratio)
1470 _tsc = __scale_tsc(ratio, tsc);
1471
1472 return _tsc;
1473}
1474EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1475
07c1419a
HZ		 1476static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1477{
1478 u64 tsc;
1479
1480 tsc = kvm_scale_tsc(vcpu, rdtsc());
1481
1482 return target_tsc - tsc;
1483}
1484
4ba76538
HZ		 1485u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1486{
ea26e4ec 1487 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1488}
1489EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1490
a545ab6a
LC		 1491static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1492{
1493 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1494 vcpu->arch.tsc_offset = offset;
1495}
1496
b0c39dc6
VK		 1497static inline bool kvm_check_tsc_unstable(void)
1498{
1499#ifdef CONFIG_X86_64
1500 /*
1501 * TSC is marked unstable when we're running on Hyper-V,
1502 * 'TSC page' clocksource is good.
1503 */
1504 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1505 return false;
1506#endif
1507 return check_tsc_unstable();
1508}
1509
8fe8ab46 1510void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1511{
1512 struct kvm *kvm = vcpu->kvm;
f38e098f 1513 u64 offset, ns, elapsed;
99e3e30a 1514 unsigned long flags;
b48aa97e 1515 bool matched;
0d3da0d2 1516 bool already_matched;
8fe8ab46 1517 u64 data = msr->data;
c5e8ec8e 1518 bool synchronizing = false;
99e3e30a 1519
038f8c11 1520 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1521 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1522 ns = ktime_get_boot_ns();
f38e098f 1523 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1524
03ba32ca 1525 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1526 if (data == 0 && msr->host_initiated) {
1527 /*
1528 * detection of vcpu initialization -- need to sync
1529 * with other vCPUs. This particularly helps to keep
1530 * kvm_clock stable after CPU hotplug
1531 */
1532 synchronizing = true;
1533 } else {
1534 u64 tsc_exp = kvm->arch.last_tsc_write +
1535 nsec_to_cycles(vcpu, elapsed);
1536 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1537 /*
1538 * Special case: TSC write with a small delta (1 second)
1539 * of virtual cycle time against real time is
1540 * interpreted as an attempt to synchronize the CPU.
1541 */
1542 synchronizing = data < tsc_exp + tsc_hz &&
1543 data + tsc_hz > tsc_exp;
1544 }
c5e8ec8e 1545 }
f38e098f
ZA		 1546
1547 /*
5d3cb0f6
ZA		 1548 * For a reliable TSC, we can match TSC offsets, and for an unstable
1549 * TSC, we add elapsed time in this computation. We could let the
1550 * compensation code attempt to catch up if we fall behind, but
1551 * it's better to try to match offsets from the beginning.
1552 */
c5e8ec8e 1553 if (synchronizing &&
5d3cb0f6 1554 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1555 if (!kvm_check_tsc_unstable()) {
e26101b1 1556 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1557 pr_debug("kvm: matched tsc offset for %llu\n", data);
1558 } else {
857e4099 1559 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1560 data += delta;
07c1419a 1561 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1562 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1563 }
b48aa97e 1564 matched = true;
0d3da0d2 1565 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1566 } else {
1567 /*
1568 * We split periods of matched TSC writes into generations.
1569 * For each generation, we track the original measured
1570 * nanosecond time, offset, and write, so if TSCs are in
1571 * sync, we can match exact offset, and if not, we can match
4a969980 1572 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1573 *
1574 * These values are tracked in kvm->arch.cur_xxx variables.
1575 */
1576 kvm->arch.cur_tsc_generation++;
1577 kvm->arch.cur_tsc_nsec = ns;
1578 kvm->arch.cur_tsc_write = data;
1579 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1580 matched = false;
0d3da0d2 1581 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1582 kvm->arch.cur_tsc_generation, data);
f38e098f 1583 }
e26101b1
ZA		 1584
1585 /*
1586 * We also track th most recent recorded KHZ, write and time to
1587 * allow the matching interval to be extended at each write.
1588 */
f38e098f
ZA		 1589 kvm->arch.last_tsc_nsec = ns;
1590 kvm->arch.last_tsc_write = data;
5d3cb0f6 1591 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1592
b183aa58 1593 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1594
1595 /* Keep track of which generation this VCPU has synchronized to */
1596 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1597 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1598 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1599
d6321d49 1600 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1601 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1602
a545ab6a 1603 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1604 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1605
1606 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1607 if (!matched) {
b48aa97e 1608 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1609 } else if (!already_matched) {
1610 kvm->arch.nr_vcpus_matched_tsc++;
1611 }
b48aa97e
MT		 1612
1613 kvm_track_tsc_matching(vcpu);
1614 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1615}
e26101b1 1616
99e3e30a
ZA		 1617EXPORT_SYMBOL_GPL(kvm_write_tsc);
1618
58ea6767
HZ		 1619static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1620 s64 adjustment)
1621{
ea26e4ec 1622 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1623}
1624
1625static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1626{
1627 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1628 WARN_ON(adjustment < 0);
1629 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1630 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1631}
1632
d828199e
MT		 1633#ifdef CONFIG_X86_64
1634
a5a1d1c2 1635static u64 read_tsc(void)
d828199e 1636{
a5a1d1c2 1637 u64 ret = (u64)rdtsc_ordered();
03b9730b 1638 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1639
1640 if (likely(ret >= last))
1641 return ret;
1642
1643 /*
1644 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1645 * predictable (it's just a function of time and the likely is
d828199e
MT		 1646 * very likely) and there's a data dependence, so force GCC
1647 * to generate a branch instead. I don't barrier() because
1648 * we don't actually need a barrier, and if this function
1649 * ever gets inlined it will generate worse code.
1650 */
1651 asm volatile ("");
1652 return last;
1653}
1654
b0c39dc6 1655static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1656{
1657 long v;
1658 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1659 u64 tsc_pg_val;
1660
1661 switch (gtod->clock.vclock_mode) {
1662 case VCLOCK_HVCLOCK:
1663 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1664 tsc_timestamp);
1665 if (tsc_pg_val != U64_MAX) {
1666 /* TSC page valid */
1667 *mode = VCLOCK_HVCLOCK;
1668 v = (tsc_pg_val - gtod->clock.cycle_last) &
1669 gtod->clock.mask;
1670 } else {
1671 /* TSC page invalid */
1672 *mode = VCLOCK_NONE;
1673 }
1674 break;
1675 case VCLOCK_TSC:
1676 *mode = VCLOCK_TSC;
1677 *tsc_timestamp = read_tsc();
1678 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1679 gtod->clock.mask;
1680 break;
1681 default:
1682 *mode = VCLOCK_NONE;
1683 }
d828199e 1684
b0c39dc6
VK		 1685 if (*mode == VCLOCK_NONE)
1686 *tsc_timestamp = v = 0;
d828199e 1687
d828199e
MT		 1688 return v * gtod->clock.mult;
1689}
1690
b0c39dc6 1691static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1692{
cbcf2dd3 1693 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1694 unsigned long seq;
d828199e 1695 int mode;
cbcf2dd3 1696 u64 ns;
d828199e 1697
d828199e
MT		 1698 do {
1699 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1700 ns = gtod->nsec_base;
b0c39dc6 1701 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1702 ns >>= gtod->clock.shift;
cbcf2dd3 1703 ns += gtod->boot_ns;
d828199e 1704 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1705 *t = ns;
d828199e
MT		 1706
1707 return mode;
1708}
1709
b0c39dc6 1710static int do_realtime(struct timespec *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1711{
1712 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1713 unsigned long seq;
1714 int mode;
1715 u64 ns;
1716
1717 do {
1718 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1719 ts->tv_sec = gtod->wall_time_sec;
1720 ns = gtod->nsec_base;
b0c39dc6 1721 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1722 ns >>= gtod->clock.shift;
1723 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1724
1725 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1726 ts->tv_nsec = ns;
1727
1728 return mode;
1729}
1730
b0c39dc6
VK		 1731/* returns true if host is using TSC based clocksource */
1732static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1733{
d828199e 1734 /* checked again under seqlock below */
b0c39dc6 1735 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1736 return false;
1737
b0c39dc6
VK		 1738 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1739 tsc_timestamp));
d828199e 1740}
55dd00a7 1741
b0c39dc6 1742/* returns true if host is using TSC based clocksource */
55dd00a7 1743static bool kvm_get_walltime_and_clockread(struct timespec *ts,
b0c39dc6 1744 u64 *tsc_timestamp)
55dd00a7
MT		 1745{
1746 /* checked again under seqlock below */
b0c39dc6 1747 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1748 return false;
1749
b0c39dc6 1750 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1751}
d828199e
MT		 1752#endif
1753
1754/*
1755 *
b48aa97e
MT		 1756 * Assuming a stable TSC across physical CPUS, and a stable TSC
1757 * across virtual CPUs, the following condition is possible.
1758 * Each numbered line represents an event visible to both
d828199e
MT		 1759 * CPUs at the next numbered event.
1760 *
1761 * "timespecX" represents host monotonic time. "tscX" represents
1762 * RDTSC value.
1763 *
1764 * VCPU0 on CPU0 | VCPU1 on CPU1
1765 *
1766 * 1. read timespec0,tsc0
1767 * 2. | timespec1 = timespec0 + N
1768 * | tsc1 = tsc0 + M
1769 * 3. transition to guest | transition to guest
1770 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1771 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1772 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1773 *
1774 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1775 *
1776 * - ret0 < ret1
1777 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1778 * ...
1779 * - 0 < N - M => M < N
1780 *
1781 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1782 * always the case (the difference between two distinct xtime instances
1783 * might be smaller then the difference between corresponding TSC reads,
1784 * when updating guest vcpus pvclock areas).
1785 *
1786 * To avoid that problem, do not allow visibility of distinct
1787 * system_timestamp/tsc_timestamp values simultaneously: use a master
1788 * copy of host monotonic time values. Update that master copy
1789 * in lockstep.
1790 *
b48aa97e 1791 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1792 *
1793 */
1794
1795static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1796{
1797#ifdef CONFIG_X86_64
1798 struct kvm_arch *ka = &kvm->arch;
1799 int vclock_mode;
b48aa97e
MT		 1800 bool host_tsc_clocksource, vcpus_matched;
1801
1802 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1803 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1804
1805 /*
1806 * If the host uses TSC clock, then passthrough TSC as stable
1807 * to the guest.
1808 */
b48aa97e 1809 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1810 &ka->master_kernel_ns,
1811 &ka->master_cycle_now);
1812
16a96021 1813 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1814 && !ka->backwards_tsc_observed
54750f2c 1815 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1816
d828199e
MT		 1817 if (ka->use_master_clock)
1818 atomic_set(&kvm_guest_has_master_clock, 1);
1819
1820 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1821 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1822 vcpus_matched);
d828199e
MT		 1823#endif
1824}
1825
2860c4b1
PB		 1826void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1827{
1828 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1829}
1830
2e762ff7
MT		 1831static void kvm_gen_update_masterclock(struct kvm *kvm)
1832{
1833#ifdef CONFIG_X86_64
1834 int i;
1835 struct kvm_vcpu *vcpu;
1836 struct kvm_arch *ka = &kvm->arch;
1837
1838 spin_lock(&ka->pvclock_gtod_sync_lock);
1839 kvm_make_mclock_inprogress_request(kvm);
1840 /* no guest entries from this point */
1841 pvclock_update_vm_gtod_copy(kvm);
1842
1843 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1844 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1845
1846 /* guest entries allowed */
1847 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1848 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1849
1850 spin_unlock(&ka->pvclock_gtod_sync_lock);
1851#endif
1852}
1853
e891a32e 1854u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1855{
108b249c 1856 struct kvm_arch *ka = &kvm->arch;
8b953440 1857 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1858 u64 ret;
108b249c 1859
8b953440
PB		 1860 spin_lock(&ka->pvclock_gtod_sync_lock);
1861 if (!ka->use_master_clock) {
1862 spin_unlock(&ka->pvclock_gtod_sync_lock);
1863 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1864 }
1865
8b953440
PB		 1866 hv_clock.tsc_timestamp = ka->master_cycle_now;
1867 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1868 spin_unlock(&ka->pvclock_gtod_sync_lock);
1869
e2c2206a
WL		 1870 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1871 get_cpu();
1872
e70b57a6
WL		 1873 if (__this_cpu_read(cpu_tsc_khz)) {
1874 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1875 &hv_clock.tsc_shift,
1876 &hv_clock.tsc_to_system_mul);
1877 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1878 } else
1879 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 1880
1881 put_cpu();
1882
1883 return ret;
108b249c
PB		 1884}
1885
0d6dd2ff
PB		 1886static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1887{
1888 struct kvm_vcpu_arch *vcpu = &v->arch;
1889 struct pvclock_vcpu_time_info guest_hv_clock;
1890
4e335d9e 1891 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1892 &guest_hv_clock, sizeof(guest_hv_clock))))
1893 return;
1894
1895 /* This VCPU is paused, but it's legal for a guest to read another
1896 * VCPU's kvmclock, so we really have to follow the specification where
1897 * it says that version is odd if data is being modified, and even after
1898 * it is consistent.
1899 *
1900 * Version field updates must be kept separate. This is because
1901 * kvm_write_guest_cached might use a "rep movs" instruction, and
1902 * writes within a string instruction are weakly ordered. So there
1903 * are three writes overall.
1904 *
1905 * As a small optimization, only write the version field in the first
1906 * and third write. The vcpu->pv_time cache is still valid, because the
1907 * version field is the first in the struct.
1908 */
1909 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1910
51c4b8bb
LA		 1911 if (guest_hv_clock.version & 1)
1912 ++guest_hv_clock.version; /* first time write, random junk */
1913
0d6dd2ff 1914 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1915 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1916 &vcpu->hv_clock,
1917 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1918
1919 smp_wmb();
1920
1921 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1922 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1923
1924 if (vcpu->pvclock_set_guest_stopped_request) {
1925 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1926 vcpu->pvclock_set_guest_stopped_request = false;
1927 }
1928
1929 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1930
4e335d9e
PB		 1931 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1932 &vcpu->hv_clock,
1933 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1934
1935 smp_wmb();
1936
1937 vcpu->hv_clock.version++;
4e335d9e
PB		 1938 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1939 &vcpu->hv_clock,
1940 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1941}
1942
34c238a1 1943static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1944{
78db6a50 1945 unsigned long flags, tgt_tsc_khz;
18068523 1946 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1947 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1948 s64 kernel_ns;
d828199e 1949 u64 tsc_timestamp, host_tsc;
51d59c6b 1950 u8 pvclock_flags;
d828199e
MT		 1951 bool use_master_clock;
1952
1953 kernel_ns = 0;
1954 host_tsc = 0;
18068523 1955
d828199e
MT		 1956 /*
1957 * If the host uses TSC clock, then passthrough TSC as stable
1958 * to the guest.
1959 */
1960 spin_lock(&ka->pvclock_gtod_sync_lock);
1961 use_master_clock = ka->use_master_clock;
1962 if (use_master_clock) {
1963 host_tsc = ka->master_cycle_now;
1964 kernel_ns = ka->master_kernel_ns;
1965 }
1966 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1967
1968 /* Keep irq disabled to prevent changes to the clock */
1969 local_irq_save(flags);
78db6a50
PB		 1970 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1971 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1972 local_irq_restore(flags);
1973 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1974 return 1;
1975 }
d828199e 1976 if (!use_master_clock) {
4ea1636b 1977 host_tsc = rdtsc();
108b249c 1978 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1979 }
1980
4ba76538 1981 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1982
c285545f
ZA		 1983 /*
1984 * We may have to catch up the TSC to match elapsed wall clock
1985 * time for two reasons, even if kvmclock is used.
1986 * 1) CPU could have been running below the maximum TSC rate
1987 * 2) Broken TSC compensation resets the base at each VCPU
1988 * entry to avoid unknown leaps of TSC even when running
1989 * again on the same CPU. This may cause apparent elapsed
1990 * time to disappear, and the guest to stand still or run
1991 * very slowly.
1992 */
1993 if (vcpu->tsc_catchup) {
1994 u64 tsc = compute_guest_tsc(v, kernel_ns);
1995 if (tsc > tsc_timestamp) {
f1e2b260 1996 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1997 tsc_timestamp = tsc;
1998 }
50d0a0f9
GH		 1999 }
2000
18068523
GOC		 2001 local_irq_restore(flags);
2002
0d6dd2ff 2003 /* With all the info we got, fill in the values */
18068523 2004
78db6a50
PB		 2005 if (kvm_has_tsc_control)
2006 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2007
2008 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2009 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2010 &vcpu->hv_clock.tsc_shift,
2011 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2012 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2013 }
2014
1d5f066e 2015 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2016 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2017 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2018
d828199e 2019 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2020 pvclock_flags = 0;
d828199e
MT		 2021 if (use_master_clock)
2022 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2023
78c0337a
MT		 2024 vcpu->hv_clock.flags = pvclock_flags;
2025
095cf55d
PB		 2026 if (vcpu->pv_time_enabled)
2027 kvm_setup_pvclock_page(v);
2028 if (v == kvm_get_vcpu(v->kvm, 0))
2029 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2030 return 0;
c8076604
GH		 2031}
2032
0061d53d
MT		 2033/*
2034 * kvmclock updates which are isolated to a given vcpu, such as
2035 * vcpu->cpu migration, should not allow system_timestamp from
2036 * the rest of the vcpus to remain static. Otherwise ntp frequency
2037 * correction applies to one vcpu's system_timestamp but not
2038 * the others.
2039 *
2040 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2041 * We need to rate-limit these requests though, as they can
2042 * considerably slow guests that have a large number of vcpus.
2043 * The time for a remote vcpu to update its kvmclock is bound
2044 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2045 */
2046
7e44e449
AJ		 2047#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2048
2049static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2050{
2051 int i;
7e44e449
AJ		 2052 struct delayed_work *dwork = to_delayed_work(work);
2053 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2054 kvmclock_update_work);
2055 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2056 struct kvm_vcpu *vcpu;
2057
2058 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2059 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2060 kvm_vcpu_kick(vcpu);
2061 }
2062}
2063
7e44e449
AJ		 2064static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2065{
2066 struct kvm *kvm = v->kvm;
2067
105b21bb 2068 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2069 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2070 KVMCLOCK_UPDATE_DELAY);
2071}
2072
332967a3
AJ		 2073#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2074
2075static void kvmclock_sync_fn(struct work_struct *work)
2076{
2077 struct delayed_work *dwork = to_delayed_work(work);
2078 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2079 kvmclock_sync_work);
2080 struct kvm *kvm = container_of(ka, struct kvm, arch);
2081
630994b3
MT		 2082 if (!kvmclock_periodic_sync)
2083 return;
2084
332967a3
AJ		 2085 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2086 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2087 KVMCLOCK_SYNC_PERIOD);
2088}
2089
9ffd986c 2090static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2091{
890ca9ae
HY		 2092 u64 mcg_cap = vcpu->arch.mcg_cap;
2093 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2094 u32 msr = msr_info->index;
2095 u64 data = msr_info->data;
890ca9ae 2096
15c4a640 2097 switch (msr) {
15c4a640 2098 case MSR_IA32_MCG_STATUS:
890ca9ae 2099 vcpu->arch.mcg_status = data;
15c4a640 2100 break;
c7ac679c 2101 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2102 if (!(mcg_cap & MCG_CTL_P))
2103 return 1;
2104 if (data != 0 && data != ~(u64)0)
2105 return -1;
2106 vcpu->arch.mcg_ctl = data;
2107 break;
2108 default:
2109 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2110 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2111 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2112 /* only 0 or all 1s can be written to IA32_MCi_CTL
2113 * some Linux kernels though clear bit 10 in bank 4 to
2114 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2115 * this to avoid an uncatched #GP in the guest
2116 */
890ca9ae 2117 if ((offset & 0x3) == 0 &&
114be429 2118 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2119 return -1;
9ffd986c
WL		 2120 if (!msr_info->host_initiated &&
2121 (offset & 0x3) == 1 && data != 0)
2122 return -1;
890ca9ae
HY		 2123 vcpu->arch.mce_banks[offset] = data;
2124 break;
2125 }
2126 return 1;
2127 }
2128 return 0;
2129}
2130
ffde22ac
ES		 2131static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2132{
2133 struct kvm *kvm = vcpu->kvm;
2134 int lm = is_long_mode(vcpu);
2135 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2136 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2137 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2138 : kvm->arch.xen_hvm_config.blob_size_32;
2139 u32 page_num = data & ~PAGE_MASK;
2140 u64 page_addr = data & PAGE_MASK;
2141 u8 *page;
2142 int r;
2143
2144 r = -E2BIG;
2145 if (page_num >= blob_size)
2146 goto out;
2147 r = -ENOMEM;
ff5c2c03
SL		 2148 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2149 if (IS_ERR(page)) {
2150 r = PTR_ERR(page);
ffde22ac 2151 goto out;
ff5c2c03 2152 }
54bf36aa 2153 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2154 goto out_free;
2155 r = 0;
2156out_free:
2157 kfree(page);
2158out:
2159 return r;
2160}
2161
344d9588
GN		 2162static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2163{
2164 gpa_t gpa = data & ~0x3f;
2165
52a5c155
WL		 2166 /* Bits 3:5 are reserved, Should be zero */
2167 if (data & 0x38)
344d9588
GN		 2168 return 1;
2169
2170 vcpu->arch.apf.msr_val = data;
2171
2172 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2173 kvm_clear_async_pf_completion_queue(vcpu);
2174 kvm_async_pf_hash_reset(vcpu);
2175 return 0;
2176 }
2177
4e335d9e 2178 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2179 sizeof(u32)))
344d9588
GN		 2180 return 1;
2181
6adba527 2182 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2183 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2184 kvm_async_pf_wakeup_all(vcpu);
2185 return 0;
2186}
2187
12f9a48f
GC		 2188static void kvmclock_reset(struct kvm_vcpu *vcpu)
2189{
0b79459b 2190 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2191}
2192
f38a7b75
WL		 2193static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2194{
2195 ++vcpu->stat.tlb_flush;
2196 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2197}
2198
c9aaa895
GC		 2199static void record_steal_time(struct kvm_vcpu *vcpu)
2200{
2201 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2202 return;
2203
4e335d9e 2204 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2205 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2206 return;
2207
f38a7b75
WL		 2208 /*
2209 * Doing a TLB flush here, on the guest's behalf, can avoid
2210 * expensive IPIs.
2211 */
2212 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2213 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2214
35f3fae1
WL		 2215 if (vcpu->arch.st.steal.version & 1)
2216 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2217
2218 vcpu->arch.st.steal.version += 1;
2219
4e335d9e 2220 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2221 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2222
2223 smp_wmb();
2224
c54cdf14
LC		 2225 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2226 vcpu->arch.st.last_steal;
2227 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2228
4e335d9e 2229 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2230 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2231
2232 smp_wmb();
2233
2234 vcpu->arch.st.steal.version += 1;
c9aaa895 2235
4e335d9e 2236 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2237 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2238}
2239
8fe8ab46 2240int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2241{
5753785f 2242 bool pr = false;
8fe8ab46
WA		 2243 u32 msr = msr_info->index;
2244 u64 data = msr_info->data;
5753785f 2245
15c4a640 2246 switch (msr) {
2e32b719
BP		 2247 case MSR_AMD64_NB_CFG:
2248 case MSR_IA32_UCODE_REV:
2249 case MSR_IA32_UCODE_WRITE:
2250 case MSR_VM_HSAVE_PA:
2251 case MSR_AMD64_PATCH_LOADER:
2252 case MSR_AMD64_BU_CFG2:
405a353a 2253 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2254 break;
2255
15c4a640 2256 case MSR_EFER:
b69e8cae 2257 return set_efer(vcpu, data);
8f1589d9
AP		 2258 case MSR_K7_HWCR:
2259 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2260 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2261 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2262 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2263 if (data != 0) {
a737f256
CD		 2264 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2265 data);
8f1589d9
AP		 2266 return 1;
2267 }
15c4a640 2268 break;
f7c6d140
AP		 2269 case MSR_FAM10H_MMIO_CONF_BASE:
2270 if (data != 0) {
a737f256
CD		 2271 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2272 "0x%llx\n", data);
f7c6d140
AP		 2273 return 1;
2274 }
15c4a640 2275 break;
b5e2fec0
AG		 2276 case MSR_IA32_DEBUGCTLMSR:
2277 if (!data) {
2278 /* We support the non-activated case already */
2279 break;
2280 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2281 /* Values other than LBR and BTF are vendor-specific,
2282 thus reserved and should throw a #GP */
2283 return 1;
2284 }
a737f256
CD		 2285 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2286 __func__, data);
b5e2fec0 2287 break;
9ba075a6 2288 case 0x200 ... 0x2ff:
ff53604b 2289 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2290 case MSR_IA32_APICBASE:
58cb628d 2291 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2292 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2293 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2294 case MSR_IA32_TSCDEADLINE:
2295 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2296 break;
ba904635 2297 case MSR_IA32_TSC_ADJUST:
d6321d49 2298 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2299 if (!msr_info->host_initiated) {
d913b904 2300 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2301 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2302 }
2303 vcpu->arch.ia32_tsc_adjust_msr = data;
2304 }
2305 break;
15c4a640 2306 case MSR_IA32_MISC_ENABLE:
ad312c7c 2307 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2308 break;
64d60670
PB		 2309 case MSR_IA32_SMBASE:
2310 if (!msr_info->host_initiated)
2311 return 1;
2312 vcpu->arch.smbase = data;
2313 break;
52797bf9
LA		 2314 case MSR_SMI_COUNT:
2315 if (!msr_info->host_initiated)
2316 return 1;
2317 vcpu->arch.smi_count = data;
2318 break;
11c6bffa 2319 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2320 case MSR_KVM_WALL_CLOCK:
2321 vcpu->kvm->arch.wall_clock = data;
2322 kvm_write_wall_clock(vcpu->kvm, data);
2323 break;
11c6bffa 2324 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2325 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2326 struct kvm_arch *ka = &vcpu->kvm->arch;
2327
12f9a48f 2328 kvmclock_reset(vcpu);
18068523 2329
54750f2c
MT		 2330 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2331 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2332
2333 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2334 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2335
2336 ka->boot_vcpu_runs_old_kvmclock = tmp;
2337 }
2338
18068523 2339 vcpu->arch.time = data;
0061d53d 2340 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2341
2342 /* we verify if the enable bit is set... */
2343 if (!(data & 1))
2344 break;
2345
4e335d9e 2346 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2347 &vcpu->arch.pv_time, data & ~1ULL,
2348 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2349 vcpu->arch.pv_time_enabled = false;
2350 else
2351 vcpu->arch.pv_time_enabled = true;
32cad84f 2352
18068523
GOC		 2353 break;
2354 }
344d9588
GN		 2355 case MSR_KVM_ASYNC_PF_EN:
2356 if (kvm_pv_enable_async_pf(vcpu, data))
2357 return 1;
2358 break;
c9aaa895
GC		 2359 case MSR_KVM_STEAL_TIME:
2360
2361 if (unlikely(!sched_info_on()))
2362 return 1;
2363
2364 if (data & KVM_STEAL_RESERVED_MASK)
2365 return 1;
2366
4e335d9e 2367 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2368 data & KVM_STEAL_VALID_BITS,
2369 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2370 return 1;
2371
2372 vcpu->arch.st.msr_val = data;
2373
2374 if (!(data & KVM_MSR_ENABLED))
2375 break;
2376
c9aaa895
GC		 2377 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2378
2379 break;
ae7a2a3f
MT		 2380 case MSR_KVM_PV_EOI_EN:
2381 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2382 return 1;
2383 break;
c9aaa895 2384
890ca9ae
HY		 2385 case MSR_IA32_MCG_CTL:
2386 case MSR_IA32_MCG_STATUS:
81760dcc 2387 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2388 return set_msr_mce(vcpu, msr_info);
71db6023 2389
6912ac32
WH		 2390 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2391 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2392 pr = true; /* fall through */
2393 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2394 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2395 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2396 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2397
2398 if (pr || data != 0)
a737f256
CD		 2399 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2400 "0x%x data 0x%llx\n", msr, data);
5753785f 2401 break;
84e0cefa
JS		 2402 case MSR_K7_CLK_CTL:
2403 /*
2404 * Ignore all writes to this no longer documented MSR.
2405 * Writes are only relevant for old K7 processors,
2406 * all pre-dating SVM, but a recommended workaround from
4a969980 2407 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2408 * affected processor models on the command line, hence
2409 * the need to ignore the workaround.
2410 */
2411 break;
55cd8e5a 2412 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2413 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2414 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2415 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2416 return kvm_hv_set_msr_common(vcpu, msr, data,
2417 msr_info->host_initiated);
91c9c3ed 2418 case MSR_IA32_BBL_CR_CTL3:
2419 /* Drop writes to this legacy MSR -- see rdmsr
2420 * counterpart for further detail.
2421 */
fab0aa3b
EM		 2422 if (report_ignored_msrs)
2423 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2424 msr, data);
91c9c3ed 2425 break;
2b036c6b 2426 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2427 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2428 return 1;
2429 vcpu->arch.osvw.length = data;
2430 break;
2431 case MSR_AMD64_OSVW_STATUS:
d6321d49 2432 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2433 return 1;
2434 vcpu->arch.osvw.status = data;
2435 break;
db2336a8
KH		 2436 case MSR_PLATFORM_INFO:
2437 if (!msr_info->host_initiated ||
2438 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2439 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2440 cpuid_fault_enabled(vcpu)))
2441 return 1;
2442 vcpu->arch.msr_platform_info = data;
2443 break;
2444 case MSR_MISC_FEATURES_ENABLES:
2445 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2446 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2447 !supports_cpuid_fault(vcpu)))
2448 return 1;
2449 vcpu->arch.msr_misc_features_enables = data;
2450 break;
15c4a640 2451 default:
ffde22ac
ES		 2452 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2453 return xen_hvm_config(vcpu, data);
c6702c9d 2454 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2455 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2456 if (!ignore_msrs) {
ae0f5499 2457 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2458 msr, data);
ed85c068
AP		 2459 return 1;
2460 } else {
fab0aa3b
EM		 2461 if (report_ignored_msrs)
2462 vcpu_unimpl(vcpu,
2463 "ignored wrmsr: 0x%x data 0x%llx\n",
2464 msr, data);
ed85c068
AP		 2465 break;
2466 }
15c4a640
CO		 2467 }
2468 return 0;
2469}
2470EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2471
2472
2473/*
2474 * Reads an msr value (of 'msr_index') into 'pdata'.
2475 * Returns 0 on success, non-0 otherwise.
2476 * Assumes vcpu_load() was already called.
2477 */
609e36d3 2478int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2479{
609e36d3 2480 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2481}
ff651cb6 2482EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2483
890ca9ae 2484static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2485{
2486 u64 data;
890ca9ae
HY		 2487 u64 mcg_cap = vcpu->arch.mcg_cap;
2488 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2489
2490 switch (msr) {
15c4a640
CO		 2491 case MSR_IA32_P5_MC_ADDR:
2492 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2493 data = 0;
2494 break;
15c4a640 2495 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2496 data = vcpu->arch.mcg_cap;
2497 break;
c7ac679c 2498 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2499 if (!(mcg_cap & MCG_CTL_P))
2500 return 1;
2501 data = vcpu->arch.mcg_ctl;
2502 break;
2503 case MSR_IA32_MCG_STATUS:
2504 data = vcpu->arch.mcg_status;
2505 break;
2506 default:
2507 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2508 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2509 u32 offset = msr - MSR_IA32_MC0_CTL;
2510 data = vcpu->arch.mce_banks[offset];
2511 break;
2512 }
2513 return 1;
2514 }
2515 *pdata = data;
2516 return 0;
2517}
2518
609e36d3 2519int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2520{
609e36d3 2521 switch (msr_info->index) {
890ca9ae 2522 case MSR_IA32_PLATFORM_ID:
15c4a640 2523 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2524 case MSR_IA32_DEBUGCTLMSR:
2525 case MSR_IA32_LASTBRANCHFROMIP:
2526 case MSR_IA32_LASTBRANCHTOIP:
2527 case MSR_IA32_LASTINTFROMIP:
2528 case MSR_IA32_LASTINTTOIP:
60af2ecd 2529 case MSR_K8_SYSCFG:
3afb1121
PB		 2530 case MSR_K8_TSEG_ADDR:
2531 case MSR_K8_TSEG_MASK:
60af2ecd 2532 case MSR_K7_HWCR:
61a6bd67 2533 case MSR_VM_HSAVE_PA:
1fdbd48c 2534 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2535 case MSR_AMD64_NB_CFG:
f7c6d140 2536 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2537 case MSR_AMD64_BU_CFG2:
0c2df2a1 2538 case MSR_IA32_PERF_CTL:
405a353a 2539 case MSR_AMD64_DC_CFG:
609e36d3 2540 msr_info->data = 0;
15c4a640 2541 break;
6912ac32
WH		 2542 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2543 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2544 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2545 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2546 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2547 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2548 msr_info->data = 0;
5753785f 2549 break;
742bc670 2550 case MSR_IA32_UCODE_REV:
609e36d3 2551 msr_info->data = 0x100000000ULL;
742bc670 2552 break;
9ba075a6 2553 case MSR_MTRRcap:
9ba075a6 2554 case 0x200 ... 0x2ff:
ff53604b 2555 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2556 case 0xcd: /* fsb frequency */
609e36d3 2557 msr_info->data = 3;
15c4a640 2558 break;
7b914098
JS		 2559 /*
2560 * MSR_EBC_FREQUENCY_ID
2561 * Conservative value valid for even the basic CPU models.
2562 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2563 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2564 * and 266MHz for model 3, or 4. Set Core Clock
2565 * Frequency to System Bus Frequency Ratio to 1 (bits
2566 * 31:24) even though these are only valid for CPU
2567 * models > 2, however guests may end up dividing or
2568 * multiplying by zero otherwise.
2569 */
2570 case MSR_EBC_FREQUENCY_ID:
609e36d3 2571 msr_info->data = 1 << 24;
7b914098 2572 break;
15c4a640 2573 case MSR_IA32_APICBASE:
609e36d3 2574 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2575 break;
0105d1a5 2576 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2577 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2578 break;
a3e06bbe 2579 case MSR_IA32_TSCDEADLINE:
609e36d3 2580 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2581 break;
ba904635 2582 case MSR_IA32_TSC_ADJUST:
609e36d3 2583 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2584 break;
15c4a640 2585 case MSR_IA32_MISC_ENABLE:
609e36d3 2586 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2587 break;
64d60670
PB		 2588 case MSR_IA32_SMBASE:
2589 if (!msr_info->host_initiated)
2590 return 1;
2591 msr_info->data = vcpu->arch.smbase;
15c4a640 2592 break;
52797bf9
LA		 2593 case MSR_SMI_COUNT:
2594 msr_info->data = vcpu->arch.smi_count;
2595 break;
847f0ad8
AG		 2596 case MSR_IA32_PERF_STATUS:
2597 /* TSC increment by tick */
609e36d3 2598 msr_info->data = 1000ULL;
847f0ad8 2599 /* CPU multiplier */
b0996ae4 2600 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2601 break;
15c4a640 2602 case MSR_EFER:
609e36d3 2603 msr_info->data = vcpu->arch.efer;
15c4a640 2604 break;
18068523 2605 case MSR_KVM_WALL_CLOCK:
11c6bffa 2606 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2607 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2608 break;
2609 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2610 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2611 msr_info->data = vcpu->arch.time;
18068523 2612 break;
344d9588 2613 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2614 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2615 break;
c9aaa895 2616 case MSR_KVM_STEAL_TIME:
609e36d3 2617 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2618 break;
1d92128f 2619 case MSR_KVM_PV_EOI_EN:
609e36d3 2620 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2621 break;
890ca9ae
HY		 2622 case MSR_IA32_P5_MC_ADDR:
2623 case MSR_IA32_P5_MC_TYPE:
2624 case MSR_IA32_MCG_CAP:
2625 case MSR_IA32_MCG_CTL:
2626 case MSR_IA32_MCG_STATUS:
81760dcc 2627 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2628 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2629 case MSR_K7_CLK_CTL:
2630 /*
2631 * Provide expected ramp-up count for K7. All other
2632 * are set to zero, indicating minimum divisors for
2633 * every field.
2634 *
2635 * This prevents guest kernels on AMD host with CPU
2636 * type 6, model 8 and higher from exploding due to
2637 * the rdmsr failing.
2638 */
609e36d3 2639 msr_info->data = 0x20000000;
84e0cefa 2640 break;
55cd8e5a 2641 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2642 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2643 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2644 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2645 return kvm_hv_get_msr_common(vcpu,
2646 msr_info->index, &msr_info->data);
55cd8e5a 2647 break;
91c9c3ed 2648 case MSR_IA32_BBL_CR_CTL3:
2649 /* This legacy MSR exists but isn't fully documented in current
2650 * silicon. It is however accessed by winxp in very narrow
2651 * scenarios where it sets bit #19, itself documented as
2652 * a "reserved" bit. Best effort attempt to source coherent
2653 * read data here should the balance of the register be
2654 * interpreted by the guest:
2655 *
2656 * L2 cache control register 3: 64GB range, 256KB size,
2657 * enabled, latency 0x1, configured
2658 */
609e36d3 2659 msr_info->data = 0xbe702111;
91c9c3ed 2660 break;
2b036c6b 2661 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2662 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2663 return 1;
609e36d3 2664 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2665 break;
2666 case MSR_AMD64_OSVW_STATUS:
d6321d49 2667 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2668 return 1;
609e36d3 2669 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2670 break;
db2336a8
KH		 2671 case MSR_PLATFORM_INFO:
2672 msr_info->data = vcpu->arch.msr_platform_info;
2673 break;
2674 case MSR_MISC_FEATURES_ENABLES:
2675 msr_info->data = vcpu->arch.msr_misc_features_enables;
2676 break;
15c4a640 2677 default:
c6702c9d 2678 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2679 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2680 if (!ignore_msrs) {
ae0f5499
BD		 2681 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2682 msr_info->index);
ed85c068
AP		 2683 return 1;
2684 } else {
fab0aa3b
EM		 2685 if (report_ignored_msrs)
2686 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2687 msr_info->index);
609e36d3 2688 msr_info->data = 0;
ed85c068
AP		 2689 }
2690 break;
15c4a640 2691 }
15c4a640
CO		 2692 return 0;
2693}
2694EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2695
313a3dc7
CO		 2696/*
2697 * Read or write a bunch of msrs. All parameters are kernel addresses.
2698 *
2699 * @return number of msrs set successfully.
2700 */
2701static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2702 struct kvm_msr_entry *entries,
2703 int (*do_msr)(struct kvm_vcpu *vcpu,
2704 unsigned index, u64 *data))
2705{
801e459a 2706 int i;
313a3dc7 2707
313a3dc7
CO		 2708 for (i = 0; i < msrs->nmsrs; ++i)
2709 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2710 break;
2711
313a3dc7
CO		 2712 return i;
2713}
2714
2715/*
2716 * Read or write a bunch of msrs. Parameters are user addresses.
2717 *
2718 * @return number of msrs set successfully.
2719 */
2720static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2721 int (*do_msr)(struct kvm_vcpu *vcpu,
2722 unsigned index, u64 *data),
2723 int writeback)
2724{
2725 struct kvm_msrs msrs;
2726 struct kvm_msr_entry *entries;
2727 int r, n;
2728 unsigned size;
2729
2730 r = -EFAULT;
2731 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2732 goto out;
2733
2734 r = -E2BIG;
2735 if (msrs.nmsrs >= MAX_IO_MSRS)
2736 goto out;
2737
313a3dc7 2738 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2739 entries = memdup_user(user_msrs->entries, size);
2740 if (IS_ERR(entries)) {
2741 r = PTR_ERR(entries);
313a3dc7 2742 goto out;
ff5c2c03 2743 }
313a3dc7
CO		 2744
2745 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2746 if (r < 0)
2747 goto out_free;
2748
2749 r = -EFAULT;
2750 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2751 goto out_free;
2752
2753 r = n;
2754
2755out_free:
7a73c028 2756 kfree(entries);
313a3dc7
CO		 2757out:
2758 return r;
2759}
2760
784aa3d7 2761int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2762{
2763 int r;
2764
2765 switch (ext) {
2766 case KVM_CAP_IRQCHIP:
2767 case KVM_CAP_HLT:
2768 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2769 case KVM_CAP_SET_TSS_ADDR:
07716717 2770 case KVM_CAP_EXT_CPUID:
9c15bb1d 2771 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2772 case KVM_CAP_CLOCKSOURCE:
7837699f 2773 case KVM_CAP_PIT:
a28e4f5a 2774 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2775 case KVM_CAP_MP_STATE:
ed848624 2776 case KVM_CAP_SYNC_MMU:
a355c85c 2777 case KVM_CAP_USER_NMI:
52d939a0 2778 case KVM_CAP_REINJECT_CONTROL:
4925663a 2779 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2780 case KVM_CAP_IOEVENTFD:
f848a5a8 2781 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2782 case KVM_CAP_PIT2:
e9f42757 2783 case KVM_CAP_PIT_STATE2:
b927a3ce 2784 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2785 case KVM_CAP_XEN_HVM:
3cfc3092 2786 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2787 case KVM_CAP_HYPERV:
10388a07 2788 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2789 case KVM_CAP_HYPERV_SPIN:
5c919412 2790 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2791 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2792 case KVM_CAP_HYPERV_VP_INDEX:
ab9f4ecb 2793 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2794 case KVM_CAP_DEBUGREGS:
d2be1651 2795 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2796 case KVM_CAP_XSAVE:
344d9588 2797 case KVM_CAP_ASYNC_PF:
92a1f12d 2798 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2799 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2800 case KVM_CAP_READONLY_MEM:
5f66b620 2801 case KVM_CAP_HYPERV_TIME:
100943c5 2802 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2803 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2804 case KVM_CAP_ENABLE_CAP_VM:
2805 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2806 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2807 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2808 case KVM_CAP_IMMEDIATE_EXIT:
801e459a 2809 case KVM_CAP_GET_MSR_FEATURES:
018d00d2
ZX		 2810 r = 1;
2811 break;
e3fd9a93
PB		 2812 case KVM_CAP_ADJUST_CLOCK:
2813 r = KVM_CLOCK_TSC_STABLE;
2814 break;
668fffa3
MT		 2815 case KVM_CAP_X86_GUEST_MWAIT:
2816 r = kvm_mwait_in_guest();
2817 break;
6d396b55
PB		 2818 case KVM_CAP_X86_SMM:
2819 /* SMBASE is usually relocated above 1M on modern chipsets,
2820 * and SMM handlers might indeed rely on 4G segment limits,
2821 * so do not report SMM to be available if real mode is
2822 * emulated via vm86 mode. Still, do not go to great lengths
2823 * to avoid userspace's usage of the feature, because it is a
2824 * fringe case that is not enabled except via specific settings
2825 * of the module parameters.
2826 */
2827 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2828 break;
774ead3a
AK		 2829 case KVM_CAP_VAPIC:
2830 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2831 break;
f725230a 2832 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2833 r = KVM_SOFT_MAX_VCPUS;
2834 break;
2835 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2836 r = KVM_MAX_VCPUS;
2837 break;
a988b910 2838 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2839 r = KVM_USER_MEM_SLOTS;
a988b910 2840 break;
a68a6a72
MT		 2841 case KVM_CAP_PV_MMU: /* obsolete */
2842 r = 0;
2f333bcb 2843 break;
890ca9ae
HY		 2844 case KVM_CAP_MCE:
2845 r = KVM_MAX_MCE_BANKS;
2846 break;
2d5b5a66 2847 case KVM_CAP_XCRS:
d366bf7e 2848 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2849 break;
92a1f12d
JR		 2850 case KVM_CAP_TSC_CONTROL:
2851 r = kvm_has_tsc_control;
2852 break;
37131313
RK		 2853 case KVM_CAP_X2APIC_API:
2854 r = KVM_X2APIC_API_VALID_FLAGS;
2855 break;
018d00d2
ZX		 2856 default:
2857 r = 0;
2858 break;
2859 }
2860 return r;
2861
2862}
2863
043405e1
CO		 2864long kvm_arch_dev_ioctl(struct file *filp,
2865 unsigned int ioctl, unsigned long arg)
2866{
2867 void __user *argp = (void __user *)arg;
2868 long r;
2869
2870 switch (ioctl) {
2871 case KVM_GET_MSR_INDEX_LIST: {
2872 struct kvm_msr_list __user *user_msr_list = argp;
2873 struct kvm_msr_list msr_list;
2874 unsigned n;
2875
2876 r = -EFAULT;
2877 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2878 goto out;
2879 n = msr_list.nmsrs;
62ef68bb 2880 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2881 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2882 goto out;
2883 r = -E2BIG;
e125e7b6 2884 if (n < msr_list.nmsrs)
043405e1
CO		 2885 goto out;
2886 r = -EFAULT;
2887 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2888 num_msrs_to_save * sizeof(u32)))
2889 goto out;
e125e7b6 2890 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2891 &emulated_msrs,
62ef68bb 2892 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2893 goto out;
2894 r = 0;
2895 break;
2896 }
9c15bb1d
BP		 2897 case KVM_GET_SUPPORTED_CPUID:
2898 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2899 struct kvm_cpuid2 __user *cpuid_arg = argp;
2900 struct kvm_cpuid2 cpuid;
2901
2902 r = -EFAULT;
2903 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2904 goto out;
9c15bb1d
BP		 2905
2906 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2907 ioctl);
674eea0f
AK		 2908 if (r)
2909 goto out;
2910
2911 r = -EFAULT;
2912 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2913 goto out;
2914 r = 0;
2915 break;
2916 }
890ca9ae 2917 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2918 r = -EFAULT;
c45dcc71
AR		 2919 if (copy_to_user(argp, &kvm_mce_cap_supported,
2920 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2921 goto out;
2922 r = 0;
2923 break;
801e459a
TL		 2924 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
2925 struct kvm_msr_list __user *user_msr_list = argp;
2926 struct kvm_msr_list msr_list;
2927 unsigned int n;
2928
2929 r = -EFAULT;
2930 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
2931 goto out;
2932 n = msr_list.nmsrs;
2933 msr_list.nmsrs = num_msr_based_features;
2934 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
2935 goto out;
2936 r = -E2BIG;
2937 if (n < msr_list.nmsrs)
2938 goto out;
2939 r = -EFAULT;
2940 if (copy_to_user(user_msr_list->indices, &msr_based_features,
2941 num_msr_based_features * sizeof(u32)))
2942 goto out;
2943 r = 0;
2944 break;
2945 }
2946 case KVM_GET_MSRS:
2947 r = msr_io(NULL, argp, do_get_msr_feature, 1);
2948 break;
890ca9ae 2949 }
043405e1
CO		 2950 default:
2951 r = -EINVAL;
2952 }
2953out:
2954 return r;
2955}
2956
f5f48ee1
SY		 2957static void wbinvd_ipi(void *garbage)
2958{
2959 wbinvd();
2960}
2961
2962static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2963{
e0f0bbc5 2964 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2965}
2966
313a3dc7
CO		 2967void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2968{
f5f48ee1
SY		 2969 /* Address WBINVD may be executed by guest */
2970 if (need_emulate_wbinvd(vcpu)) {
2971 if (kvm_x86_ops->has_wbinvd_exit())
2972 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2973 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2974 smp_call_function_single(vcpu->cpu,
2975 wbinvd_ipi, NULL, 1);
2976 }
2977
313a3dc7 2978 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2979
0dd6a6ed
ZA		 2980 /* Apply any externally detected TSC adjustments (due to suspend) */
2981 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2982 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2983 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2984 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2985 }
8f6055cb 2986
b0c39dc6 2987 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 2988 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2989 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2990 if (tsc_delta < 0)
2991 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2992
b0c39dc6 2993 if (kvm_check_tsc_unstable()) {
07c1419a 2994 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2995 vcpu->arch.last_guest_tsc);
a545ab6a 2996 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2997 vcpu->arch.tsc_catchup = 1;
c285545f 2998 }
a749e247
PB		 2999
3000 if (kvm_lapic_hv_timer_in_use(vcpu))
3001 kvm_lapic_restart_hv_timer(vcpu);
3002
d98d07ca
MT		 3003 /*
3004 * On a host with synchronized TSC, there is no need to update
3005 * kvmclock on vcpu->cpu migration
3006 */
3007 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3008 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3009 if (vcpu->cpu != cpu)
1bd2009e 3010 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3011 vcpu->cpu = cpu;
6b7d7e76 3012 }
c9aaa895 3013
c9aaa895 3014 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3015}
3016
0b9f6c46
PX		 3017static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3018{
3019 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3020 return;
3021
fa55eedd 3022 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3023
4e335d9e 3024 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3025 &vcpu->arch.st.steal.preempted,
3026 offsetof(struct kvm_steal_time, preempted),
3027 sizeof(vcpu->arch.st.steal.preempted));
3028}
3029
313a3dc7
CO		 3030void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3031{
cc0d907c 3032 int idx;
de63ad4c
LM		 3033
3034 if (vcpu->preempted)
3035 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3036
931f261b
AA		 3037 /*
3038 * Disable page faults because we're in atomic context here.
3039 * kvm_write_guest_offset_cached() would call might_fault()
3040 * that relies on pagefault_disable() to tell if there's a
3041 * bug. NOTE: the write to guest memory may not go through if
3042 * during postcopy live migration or if there's heavy guest
3043 * paging.
3044 */
3045 pagefault_disable();
cc0d907c
AA		 3046 /*
3047 * kvm_memslots() will be called by
3048 * kvm_write_guest_offset_cached() so take the srcu lock.
3049 */
3050 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3051 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3052 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3053 pagefault_enable();
02daab21 3054 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3055 vcpu->arch.last_host_tsc = rdtsc();
efdab992
WL		 3056 /*
3057 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3058 * on every vmexit, but if not, we might have a stale dr6 from the
3059 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3060 */
3061 set_debugreg(0, 6);
313a3dc7
CO		 3062}
3063
313a3dc7
CO		 3064static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3065 struct kvm_lapic_state *s)
3066{
fa59cc00 3067 if (vcpu->arch.apicv_active)
d62caabb
AS		 3068 kvm_x86_ops->sync_pir_to_irr(vcpu);
3069
a92e2543 3070 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3071}
3072
3073static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3074 struct kvm_lapic_state *s)
3075{
a92e2543
RK		 3076 int r;
3077
3078 r = kvm_apic_set_state(vcpu, s);
3079 if (r)
3080 return r;
cb142eb7 3081 update_cr8_intercept(vcpu);
313a3dc7
CO		 3082
3083 return 0;
3084}
3085
127a457a
MG		 3086static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3087{
3088 return (!lapic_in_kernel(vcpu) ||
3089 kvm_apic_accept_pic_intr(vcpu));
3090}
3091
782d422b
MG		 3092/*
3093 * if userspace requested an interrupt window, check that the
3094 * interrupt window is open.
3095 *
3096 * No need to exit to userspace if we already have an interrupt queued.
3097 */
3098static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3099{
3100 return kvm_arch_interrupt_allowed(vcpu) &&
3101 !kvm_cpu_has_interrupt(vcpu) &&
3102 !kvm_event_needs_reinjection(vcpu) &&
3103 kvm_cpu_accept_dm_intr(vcpu);
3104}
3105
f77bc6a4
ZX		 3106static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3107 struct kvm_interrupt *irq)
3108{
02cdb50f 3109 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3110 return -EINVAL;
1c1a9ce9
SR		 3111
3112 if (!irqchip_in_kernel(vcpu->kvm)) {
3113 kvm_queue_interrupt(vcpu, irq->irq, false);
3114 kvm_make_request(KVM_REQ_EVENT, vcpu);
3115 return 0;
3116 }
3117
3118 /*
3119 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3120 * fail for in-kernel 8259.
3121 */
3122 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3123 return -ENXIO;
f77bc6a4 3124
1c1a9ce9
SR		 3125 if (vcpu->arch.pending_external_vector != -1)
3126 return -EEXIST;
f77bc6a4 3127
1c1a9ce9 3128 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3129 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3130 return 0;
3131}
3132
c4abb7c9
JK		 3133static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3134{
c4abb7c9 3135 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3136
3137 return 0;
3138}
3139
f077825a
PB		 3140static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3141{
64d60670
PB		 3142 kvm_make_request(KVM_REQ_SMI, vcpu);
3143
f077825a
PB		 3144 return 0;
3145}
3146
b209749f
AK		 3147static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3148 struct kvm_tpr_access_ctl *tac)
3149{
3150 if (tac->flags)
3151 return -EINVAL;
3152 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3153 return 0;
3154}
3155
890ca9ae
HY		 3156static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3157 u64 mcg_cap)
3158{
3159 int r;
3160 unsigned bank_num = mcg_cap & 0xff, bank;
3161
3162 r = -EINVAL;
a9e38c3e 3163 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3164 goto out;
c45dcc71 3165 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3166 goto out;
3167 r = 0;
3168 vcpu->arch.mcg_cap = mcg_cap;
3169 /* Init IA32_MCG_CTL to all 1s */
3170 if (mcg_cap & MCG_CTL_P)
3171 vcpu->arch.mcg_ctl = ~(u64)0;
3172 /* Init IA32_MCi_CTL to all 1s */
3173 for (bank = 0; bank < bank_num; bank++)
3174 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3175
3176 if (kvm_x86_ops->setup_mce)
3177 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3178out:
3179 return r;
3180}
3181
3182static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3183 struct kvm_x86_mce *mce)
3184{
3185 u64 mcg_cap = vcpu->arch.mcg_cap;
3186 unsigned bank_num = mcg_cap & 0xff;
3187 u64 *banks = vcpu->arch.mce_banks;
3188
3189 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3190 return -EINVAL;
3191 /*
3192 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3193 * reporting is disabled
3194 */
3195 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3196 vcpu->arch.mcg_ctl != ~(u64)0)
3197 return 0;
3198 banks += 4 * mce->bank;
3199 /*
3200 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3201 * reporting is disabled for the bank
3202 */
3203 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3204 return 0;
3205 if (mce->status & MCI_STATUS_UC) {
3206 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3207 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3208 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3209 return 0;
3210 }
3211 if (banks[1] & MCI_STATUS_VAL)
3212 mce->status |= MCI_STATUS_OVER;
3213 banks[2] = mce->addr;
3214 banks[3] = mce->misc;
3215 vcpu->arch.mcg_status = mce->mcg_status;
3216 banks[1] = mce->status;
3217 kvm_queue_exception(vcpu, MC_VECTOR);
3218 } else if (!(banks[1] & MCI_STATUS_VAL)
3219 || !(banks[1] & MCI_STATUS_UC)) {
3220 if (banks[1] & MCI_STATUS_VAL)
3221 mce->status |= MCI_STATUS_OVER;
3222 banks[2] = mce->addr;
3223 banks[3] = mce->misc;
3224 banks[1] = mce->status;
3225 } else
3226 banks[1] |= MCI_STATUS_OVER;
3227 return 0;
3228}
3229
3cfc3092
JK		 3230static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3231 struct kvm_vcpu_events *events)
3232{
7460fb4a 3233 process_nmi(vcpu);
664f8e26
WL		 3234 /*
3235 * FIXME: pass injected and pending separately. This is only
3236 * needed for nested virtualization, whose state cannot be
3237 * migrated yet. For now we can combine them.
3238 */
03b82a30 3239 events->exception.injected =
664f8e26
WL		 3240 (vcpu->arch.exception.pending ||
3241 vcpu->arch.exception.injected) &&
03b82a30 3242 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3243 events->exception.nr = vcpu->arch.exception.nr;
3244 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3245 events->exception.pad = 0;
3cfc3092
JK		 3246 events->exception.error_code = vcpu->arch.exception.error_code;
3247
03b82a30
JK		 3248 events->interrupt.injected =
3249 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3250 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3251 events->interrupt.soft = 0;
37ccdcbe 3252 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3253
3254 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3255 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3256 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3257 events->nmi.pad = 0;
3cfc3092 3258
66450a21 3259 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3260
f077825a
PB		 3261 events->smi.smm = is_smm(vcpu);
3262 events->smi.pending = vcpu->arch.smi_pending;
3263 events->smi.smm_inside_nmi =
3264 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3265 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3266
dab4b911 3267 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3268 | KVM_VCPUEVENT_VALID_SHADOW
3269 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3270 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3271}
3272
6ef4e07e
XG		 3273static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3274
3cfc3092
JK		 3275static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3276 struct kvm_vcpu_events *events)
3277{
dab4b911 3278 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3279 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3280 | KVM_VCPUEVENT_VALID_SHADOW
3281 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3282 return -EINVAL;
3283
78e546c8 3284 if (events->exception.injected &&
28d06353
JM		 3285 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3286 is_guest_mode(vcpu)))
78e546c8
PB		 3287 return -EINVAL;
3288
28bf2888
DH		 3289 /* INITs are latched while in SMM */
3290 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3291 (events->smi.smm || events->smi.pending) &&
3292 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3293 return -EINVAL;
3294
7460fb4a 3295 process_nmi(vcpu);
664f8e26 3296 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3297 vcpu->arch.exception.pending = events->exception.injected;
3298 vcpu->arch.exception.nr = events->exception.nr;
3299 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3300 vcpu->arch.exception.error_code = events->exception.error_code;
3301
3302 vcpu->arch.interrupt.pending = events->interrupt.injected;
3303 vcpu->arch.interrupt.nr = events->interrupt.nr;
3304 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3305 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3306 kvm_x86_ops->set_interrupt_shadow(vcpu,
3307 events->interrupt.shadow);
3cfc3092
JK		 3308
3309 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3310 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3311 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3312 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3313
66450a21 3314 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3315 lapic_in_kernel(vcpu))
66450a21 3316 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3317
f077825a 3318 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3319 u32 hflags = vcpu->arch.hflags;
f077825a 3320 if (events->smi.smm)
6ef4e07e 3321 hflags |= HF_SMM_MASK;
f077825a 3322 else
6ef4e07e
XG		 3323 hflags &= ~HF_SMM_MASK;
3324 kvm_set_hflags(vcpu, hflags);
3325
f077825a 3326 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3327
3328 if (events->smi.smm) {
3329 if (events->smi.smm_inside_nmi)
3330 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3331 else
f4ef1910
WL		 3332 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3333 if (lapic_in_kernel(vcpu)) {
3334 if (events->smi.latched_init)
3335 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3336 else
3337 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3338 }
f077825a
PB		 3339 }
3340 }
3341
3842d135
AK		 3342 kvm_make_request(KVM_REQ_EVENT, vcpu);
3343
3cfc3092
JK		 3344 return 0;
3345}
3346
a1efbe77
JK		 3347static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3348 struct kvm_debugregs *dbgregs)
3349{
73aaf249
JK		 3350 unsigned long val;
3351
a1efbe77 3352 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3353 kvm_get_dr(vcpu, 6, &val);
73aaf249 3354 dbgregs->dr6 = val;
a1efbe77
JK		 3355 dbgregs->dr7 = vcpu->arch.dr7;
3356 dbgregs->flags = 0;
97e69aa6 3357 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3358}
3359
3360static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3361 struct kvm_debugregs *dbgregs)
3362{
3363 if (dbgregs->flags)
3364 return -EINVAL;
3365
d14bdb55
PB		 3366 if (dbgregs->dr6 & ~0xffffffffull)
3367 return -EINVAL;
3368 if (dbgregs->dr7 & ~0xffffffffull)
3369 return -EINVAL;
3370
a1efbe77 3371 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3372 kvm_update_dr0123(vcpu);
a1efbe77 3373 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3374 kvm_update_dr6(vcpu);
a1efbe77 3375 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3376 kvm_update_dr7(vcpu);
a1efbe77 3377
a1efbe77
JK		 3378 return 0;
3379}
3380
df1daba7
PB		 3381#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3382
3383static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3384{
c47ada30 3385 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3386 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3387 u64 valid;
3388
3389 /*
3390 * Copy legacy XSAVE area, to avoid complications with CPUID
3391 * leaves 0 and 1 in the loop below.
3392 */
3393 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3394
3395 /* Set XSTATE_BV */
00c87e9a 3396 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3397 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3398
3399 /*
3400 * Copy each region from the possibly compacted offset to the
3401 * non-compacted offset.
3402 */
d91cab78 3403 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3404 while (valid) {
3405 u64 feature = valid & -valid;
3406 int index = fls64(feature) - 1;
3407 void *src = get_xsave_addr(xsave, feature);
3408
3409 if (src) {
3410 u32 size, offset, ecx, edx;
3411 cpuid_count(XSTATE_CPUID, index,
3412 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3413 if (feature == XFEATURE_MASK_PKRU)
3414 memcpy(dest + offset, &vcpu->arch.pkru,
3415 sizeof(vcpu->arch.pkru));
3416 else
3417 memcpy(dest + offset, src, size);
3418
df1daba7
PB		 3419 }
3420
3421 valid -= feature;
3422 }
3423}
3424
3425static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3426{
c47ada30 3427 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3428 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3429 u64 valid;
3430
3431 /*
3432 * Copy legacy XSAVE area, to avoid complications with CPUID
3433 * leaves 0 and 1 in the loop below.
3434 */
3435 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3436
3437 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3438 xsave->header.xfeatures = xstate_bv;
782511b0 3439 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3440 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3441
3442 /*
3443 * Copy each region from the non-compacted offset to the
3444 * possibly compacted offset.
3445 */
d91cab78 3446 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3447 while (valid) {
3448 u64 feature = valid & -valid;
3449 int index = fls64(feature) - 1;
3450 void *dest = get_xsave_addr(xsave, feature);
3451
3452 if (dest) {
3453 u32 size, offset, ecx, edx;
3454 cpuid_count(XSTATE_CPUID, index,
3455 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3456 if (feature == XFEATURE_MASK_PKRU)
3457 memcpy(&vcpu->arch.pkru, src + offset,
3458 sizeof(vcpu->arch.pkru));
3459 else
3460 memcpy(dest, src + offset, size);
ee4100da 3461 }
df1daba7
PB		 3462
3463 valid -= feature;
3464 }
3465}
3466
2d5b5a66
SY		 3467static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3468 struct kvm_xsave *guest_xsave)
3469{
d366bf7e 3470 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3471 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3472 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3473 } else {
2d5b5a66 3474 memcpy(guest_xsave->region,
7366ed77 3475 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3476 sizeof(struct fxregs_state));
2d5b5a66 3477 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3478 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3479 }
3480}
3481
a575813b
WL		 3482#define XSAVE_MXCSR_OFFSET 24
3483
2d5b5a66
SY		 3484static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3485 struct kvm_xsave *guest_xsave)
3486{
3487 u64 xstate_bv =
3488 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3489 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3490
d366bf7e 3491 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3492 /*
3493 * Here we allow setting states that are not present in
3494 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3495 * with old userspace.
3496 */
a575813b
WL		 3497 if (xstate_bv & ~kvm_supported_xcr0() ||
3498 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3499 return -EINVAL;
df1daba7 3500 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3501 } else {
a575813b
WL		 3502 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3503 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3504 return -EINVAL;
7366ed77 3505 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3506 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3507 }
3508 return 0;
3509}
3510
3511static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3512 struct kvm_xcrs *guest_xcrs)
3513{
d366bf7e 3514 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3515 guest_xcrs->nr_xcrs = 0;
3516 return;
3517 }
3518
3519 guest_xcrs->nr_xcrs = 1;
3520 guest_xcrs->flags = 0;
3521 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3522 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3523}
3524
3525static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3526 struct kvm_xcrs *guest_xcrs)
3527{
3528 int i, r = 0;
3529
d366bf7e 3530 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3531 return -EINVAL;
3532
3533 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3534 return -EINVAL;
3535
3536 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3537 /* Only support XCR0 currently */
c67a04cb 3538 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3539 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3540 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3541 break;
3542 }
3543 if (r)
3544 r = -EINVAL;
3545 return r;
3546}
3547
1c0b28c2
EM		 3548/*
3549 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3550 * stopped by the hypervisor. This function will be called from the host only.
3551 * EINVAL is returned when the host attempts to set the flag for a guest that
3552 * does not support pv clocks.
3553 */
3554static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3555{
0b79459b 3556 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3557 return -EINVAL;
51d59c6b 3558 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3559 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3560 return 0;
3561}
3562
5c919412
AS		 3563static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3564 struct kvm_enable_cap *cap)
3565{
3566 if (cap->flags)
3567 return -EINVAL;
3568
3569 switch (cap->cap) {
efc479e6
RK		 3570 case KVM_CAP_HYPERV_SYNIC2:
3571 if (cap->args[0])
3572 return -EINVAL;
5c919412 3573 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3574 if (!irqchip_in_kernel(vcpu->kvm))
3575 return -EINVAL;
efc479e6
RK		 3576 return kvm_hv_activate_synic(vcpu, cap->cap ==
3577 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3578 default:
3579 return -EINVAL;
3580 }
3581}
3582
313a3dc7
CO		 3583long kvm_arch_vcpu_ioctl(struct file *filp,
3584 unsigned int ioctl, unsigned long arg)
3585{
3586 struct kvm_vcpu *vcpu = filp->private_data;
3587 void __user *argp = (void __user *)arg;
3588 int r;
d1ac91d8
AK		 3589 union {
3590 struct kvm_lapic_state *lapic;
3591 struct kvm_xsave *xsave;
3592 struct kvm_xcrs *xcrs;
3593 void *buffer;
3594 } u;
3595
9b062471
CD		 3596 vcpu_load(vcpu);
3597
d1ac91d8 3598 u.buffer = NULL;
313a3dc7
CO		 3599 switch (ioctl) {
3600 case KVM_GET_LAPIC: {
2204ae3c 3601 r = -EINVAL;
bce87cce 3602 if (!lapic_in_kernel(vcpu))
2204ae3c 3603 goto out;
d1ac91d8 3604 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3605
b772ff36 3606 r = -ENOMEM;
d1ac91d8 3607 if (!u.lapic)
b772ff36 3608 goto out;
d1ac91d8 3609 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3610 if (r)
3611 goto out;
3612 r = -EFAULT;
d1ac91d8 3613 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3614 goto out;
3615 r = 0;
3616 break;
3617 }
3618 case KVM_SET_LAPIC: {
2204ae3c 3619 r = -EINVAL;
bce87cce 3620 if (!lapic_in_kernel(vcpu))
2204ae3c 3621 goto out;
ff5c2c03 3622 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3623 if (IS_ERR(u.lapic)) {
3624 r = PTR_ERR(u.lapic);
3625 goto out_nofree;
3626 }
ff5c2c03 3627
d1ac91d8 3628 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3629 break;
3630 }
f77bc6a4
ZX		 3631 case KVM_INTERRUPT: {
3632 struct kvm_interrupt irq;
3633
3634 r = -EFAULT;
3635 if (copy_from_user(&irq, argp, sizeof irq))
3636 goto out;
3637 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3638 break;
3639 }
c4abb7c9
JK		 3640 case KVM_NMI: {
3641 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3642 break;
3643 }
f077825a
PB		 3644 case KVM_SMI: {
3645 r = kvm_vcpu_ioctl_smi(vcpu);
3646 break;
3647 }
313a3dc7
CO		 3648 case KVM_SET_CPUID: {
3649 struct kvm_cpuid __user *cpuid_arg = argp;
3650 struct kvm_cpuid cpuid;
3651
3652 r = -EFAULT;
3653 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3654 goto out;
3655 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3656 break;
3657 }
07716717
DK		 3658 case KVM_SET_CPUID2: {
3659 struct kvm_cpuid2 __user *cpuid_arg = argp;
3660 struct kvm_cpuid2 cpuid;
3661
3662 r = -EFAULT;
3663 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3664 goto out;
3665 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3666 cpuid_arg->entries);
07716717
DK		 3667 break;
3668 }
3669 case KVM_GET_CPUID2: {
3670 struct kvm_cpuid2 __user *cpuid_arg = argp;
3671 struct kvm_cpuid2 cpuid;
3672
3673 r = -EFAULT;
3674 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3675 goto out;
3676 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3677 cpuid_arg->entries);
07716717
DK		 3678 if (r)
3679 goto out;
3680 r = -EFAULT;
3681 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3682 goto out;
3683 r = 0;
3684 break;
3685 }
801e459a
TL		 3686 case KVM_GET_MSRS: {
3687 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 3688 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 3689 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3690 break;
801e459a
TL		 3691 }
3692 case KVM_SET_MSRS: {
3693 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 3694 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 3695 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3696 break;
801e459a 3697 }
b209749f
AK		 3698 case KVM_TPR_ACCESS_REPORTING: {
3699 struct kvm_tpr_access_ctl tac;
3700
3701 r = -EFAULT;
3702 if (copy_from_user(&tac, argp, sizeof tac))
3703 goto out;
3704 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3705 if (r)
3706 goto out;
3707 r = -EFAULT;
3708 if (copy_to_user(argp, &tac, sizeof tac))
3709 goto out;
3710 r = 0;
3711 break;
3712 };
b93463aa
AK		 3713 case KVM_SET_VAPIC_ADDR: {
3714 struct kvm_vapic_addr va;
7301d6ab 3715 int idx;
b93463aa
AK		 3716
3717 r = -EINVAL;
35754c98 3718 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3719 goto out;
3720 r = -EFAULT;
3721 if (copy_from_user(&va, argp, sizeof va))
3722 goto out;
7301d6ab 3723 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3724 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3725 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3726 break;
3727 }
890ca9ae
HY		 3728 case KVM_X86_SETUP_MCE: {
3729 u64 mcg_cap;
3730
3731 r = -EFAULT;
3732 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3733 goto out;
3734 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3735 break;
3736 }
3737 case KVM_X86_SET_MCE: {
3738 struct kvm_x86_mce mce;
3739
3740 r = -EFAULT;
3741 if (copy_from_user(&mce, argp, sizeof mce))
3742 goto out;
3743 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3744 break;
3745 }
3cfc3092
JK		 3746 case KVM_GET_VCPU_EVENTS: {
3747 struct kvm_vcpu_events events;
3748
3749 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3750
3751 r = -EFAULT;
3752 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3753 break;
3754 r = 0;
3755 break;
3756 }
3757 case KVM_SET_VCPU_EVENTS: {
3758 struct kvm_vcpu_events events;
3759
3760 r = -EFAULT;
3761 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3762 break;
3763
3764 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3765 break;
3766 }
a1efbe77
JK		 3767 case KVM_GET_DEBUGREGS: {
3768 struct kvm_debugregs dbgregs;
3769
3770 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3771
3772 r = -EFAULT;
3773 if (copy_to_user(argp, &dbgregs,
3774 sizeof(struct kvm_debugregs)))
3775 break;
3776 r = 0;
3777 break;
3778 }
3779 case KVM_SET_DEBUGREGS: {
3780 struct kvm_debugregs dbgregs;
3781
3782 r = -EFAULT;
3783 if (copy_from_user(&dbgregs, argp,
3784 sizeof(struct kvm_debugregs)))
3785 break;
3786
3787 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3788 break;
3789 }
2d5b5a66 3790 case KVM_GET_XSAVE: {
d1ac91d8 3791 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3792 r = -ENOMEM;
d1ac91d8 3793 if (!u.xsave)
2d5b5a66
SY		 3794 break;
3795
d1ac91d8 3796 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3797
3798 r = -EFAULT;
d1ac91d8 3799 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3800 break;
3801 r = 0;
3802 break;
3803 }
3804 case KVM_SET_XSAVE: {
ff5c2c03 3805 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 3806 if (IS_ERR(u.xsave)) {
3807 r = PTR_ERR(u.xsave);
3808 goto out_nofree;
3809 }
2d5b5a66 3810
d1ac91d8 3811 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3812 break;
3813 }
3814 case KVM_GET_XCRS: {
d1ac91d8 3815 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3816 r = -ENOMEM;
d1ac91d8 3817 if (!u.xcrs)
2d5b5a66
SY		 3818 break;
3819
d1ac91d8 3820 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3821
3822 r = -EFAULT;
d1ac91d8 3823 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3824 sizeof(struct kvm_xcrs)))
3825 break;
3826 r = 0;
3827 break;
3828 }
3829 case KVM_SET_XCRS: {
ff5c2c03 3830 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 3831 if (IS_ERR(u.xcrs)) {
3832 r = PTR_ERR(u.xcrs);
3833 goto out_nofree;
3834 }
2d5b5a66 3835
d1ac91d8 3836 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3837 break;
3838 }
92a1f12d
JR		 3839 case KVM_SET_TSC_KHZ: {
3840 u32 user_tsc_khz;
3841
3842 r = -EINVAL;
92a1f12d
JR		 3843 user_tsc_khz = (u32)arg;
3844
3845 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3846 goto out;
3847
cc578287
ZA		 3848 if (user_tsc_khz == 0)
3849 user_tsc_khz = tsc_khz;
3850
381d585c
HZ		 3851 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3852 r = 0;
92a1f12d 3853
92a1f12d
JR		 3854 goto out;
3855 }
3856 case KVM_GET_TSC_KHZ: {
cc578287 3857 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3858 goto out;
3859 }
1c0b28c2
EM		 3860 case KVM_KVMCLOCK_CTRL: {
3861 r = kvm_set_guest_paused(vcpu);
3862 goto out;
3863 }
5c919412
AS		 3864 case KVM_ENABLE_CAP: {
3865 struct kvm_enable_cap cap;
3866
3867 r = -EFAULT;
3868 if (copy_from_user(&cap, argp, sizeof(cap)))
3869 goto out;
3870 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3871 break;
3872 }
313a3dc7
CO		 3873 default:
3874 r = -EINVAL;
3875 }
3876out:
d1ac91d8 3877 kfree(u.buffer);
9b062471
CD		 3878out_nofree:
3879 vcpu_put(vcpu);
313a3dc7
CO		 3880 return r;
3881}
3882
5b1c1493
CO		 3883int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3884{
3885 return VM_FAULT_SIGBUS;
3886}
3887
1fe779f8
CO		 3888static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3889{
3890 int ret;
3891
3892 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3893 return -EINVAL;
1fe779f8
CO		 3894 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3895 return ret;
3896}
3897
b927a3ce
SY		 3898static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3899 u64 ident_addr)
3900{
3901 kvm->arch.ept_identity_map_addr = ident_addr;
3902 return 0;
3903}
3904
1fe779f8
CO		 3905static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3906 u32 kvm_nr_mmu_pages)
3907{
3908 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3909 return -EINVAL;
3910
79fac95e 3911 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3912
3913 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3914 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3915
79fac95e 3916 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3917 return 0;
3918}
3919
3920static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3921{
39de71ec 3922 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3923}
3924
1fe779f8
CO		 3925static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3926{
90bca052 3927 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3928 int r;
3929
3930 r = 0;
3931 switch (chip->chip_id) {
3932 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3933 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3934 sizeof(struct kvm_pic_state));
3935 break;
3936 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3937 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 3938 sizeof(struct kvm_pic_state));
3939 break;
3940 case KVM_IRQCHIP_IOAPIC:
33392b49 3941 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3942 break;
3943 default:
3944 r = -EINVAL;
3945 break;
3946 }
3947 return r;
3948}
3949
3950static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3951{
90bca052 3952 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3953 int r;
3954
3955 r = 0;
3956 switch (chip->chip_id) {
3957 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 3958 spin_lock(&pic->lock);
3959 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 3960 sizeof(struct kvm_pic_state));
90bca052 3961 spin_unlock(&pic->lock);
1fe779f8
CO		 3962 break;
3963 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 3964 spin_lock(&pic->lock);
3965 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 3966 sizeof(struct kvm_pic_state));
90bca052 3967 spin_unlock(&pic->lock);
1fe779f8
CO		 3968 break;
3969 case KVM_IRQCHIP_IOAPIC:
33392b49 3970 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3971 break;
3972 default:
3973 r = -EINVAL;
3974 break;
3975 }
90bca052 3976 kvm_pic_update_irq(pic);
1fe779f8
CO		 3977 return r;
3978}
3979
e0f63cb9
SY		 3980static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3981{
34f3941c
RK		 3982 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3983
3984 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3985
3986 mutex_lock(&kps->lock);
3987 memcpy(ps, &kps->channels, sizeof(*ps));
3988 mutex_unlock(&kps->lock);
2da29bcc 3989 return 0;
e0f63cb9
SY		 3990}
3991
3992static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3993{
0185604c 3994 int i;
09edea72
RK		 3995 struct kvm_pit *pit = kvm->arch.vpit;
3996
3997 mutex_lock(&pit->pit_state.lock);
34f3941c 3998 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3999 for (i = 0; i < 3; i++)
09edea72
RK		 4000 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4001 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4002 return 0;
e9f42757
BK		 4003}
4004
4005static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4006{
e9f42757
BK		 4007 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4008 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4009 sizeof(ps->channels));
4010 ps->flags = kvm->arch.vpit->pit_state.flags;
4011 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4012 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4013 return 0;
e9f42757
BK		 4014}
4015
4016static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4017{
2da29bcc 4018 int start = 0;
0185604c 4019 int i;
e9f42757 4020 u32 prev_legacy, cur_legacy;
09edea72
RK		 4021 struct kvm_pit *pit = kvm->arch.vpit;
4022
4023 mutex_lock(&pit->pit_state.lock);
4024 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4025 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4026 if (!prev_legacy && cur_legacy)
4027 start = 1;
09edea72
RK		 4028 memcpy(&pit->pit_state.channels, &ps->channels,
4029 sizeof(pit->pit_state.channels));
4030 pit->pit_state.flags = ps->flags;
0185604c 4031 for (i = 0; i < 3; i++)
09edea72 4032 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4033 start && i == 0);
09edea72 4034 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4035 return 0;
e0f63cb9
SY		 4036}
4037
52d939a0
MT		 4038static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4039 struct kvm_reinject_control *control)
4040{
71474e2f
RK		 4041 struct kvm_pit *pit = kvm->arch.vpit;
4042
4043 if (!pit)
52d939a0 4044 return -ENXIO;
b39c90b6 4045
71474e2f
RK		 4046 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4047 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4048 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4049 */
4050 mutex_lock(&pit->pit_state.lock);
4051 kvm_pit_set_reinject(pit, control->pit_reinject);
4052 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4053
52d939a0
MT		 4054 return 0;
4055}
4056
95d4c16c 4057/**
60c34612
TY		 4058 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4059 * @kvm: kvm instance
4060 * @log: slot id and address to which we copy the log
95d4c16c 4061 *
e108ff2f
PB		 4062 * Steps 1-4 below provide general overview of dirty page logging. See
4063 * kvm_get_dirty_log_protect() function description for additional details.
4064 *
4065 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4066 * always flush the TLB (step 4) even if previous step failed and the dirty
4067 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4068 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4069 * writes will be marked dirty for next log read.
95d4c16c 4070 *
60c34612
TY		 4071 * 1. Take a snapshot of the bit and clear it if needed.
4072 * 2. Write protect the corresponding page.
e108ff2f
PB		 4073 * 3. Copy the snapshot to the userspace.
4074 * 4. Flush TLB's if needed.
5bb064dc 4075 */
60c34612 4076int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4077{
60c34612 4078 bool is_dirty = false;
e108ff2f 4079 int r;
5bb064dc 4080
79fac95e 4081 mutex_lock(&kvm->slots_lock);
5bb064dc 4082
88178fd4
KH		 4083 /*
4084 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4085 */
4086 if (kvm_x86_ops->flush_log_dirty)
4087 kvm_x86_ops->flush_log_dirty(kvm);
4088
e108ff2f 4089 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 4090
4091 /*
4092 * All the TLBs can be flushed out of mmu lock, see the comments in
4093 * kvm_mmu_slot_remove_write_access().
4094 */
e108ff2f 4095 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 4096 if (is_dirty)
4097 kvm_flush_remote_tlbs(kvm);
4098
79fac95e 4099 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4100 return r;
4101}
4102
aa2fbe6d
YZ		 4103int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4104 bool line_status)
23d43cf9
CD		 4105{
4106 if (!irqchip_in_kernel(kvm))
4107 return -ENXIO;
4108
4109 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4110 irq_event->irq, irq_event->level,
4111 line_status);
23d43cf9
CD		 4112 return 0;
4113}
4114
90de4a18
NA		 4115static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4116 struct kvm_enable_cap *cap)
4117{
4118 int r;
4119
4120 if (cap->flags)
4121 return -EINVAL;
4122
4123 switch (cap->cap) {
4124 case KVM_CAP_DISABLE_QUIRKS:
4125 kvm->arch.disabled_quirks = cap->args[0];
4126 r = 0;
4127 break;
49df6397
SR		 4128 case KVM_CAP_SPLIT_IRQCHIP: {
4129 mutex_lock(&kvm->lock);
b053b2ae
SR		 4130 r = -EINVAL;
4131 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4132 goto split_irqchip_unlock;
49df6397
SR		 4133 r = -EEXIST;
4134 if (irqchip_in_kernel(kvm))
4135 goto split_irqchip_unlock;
557abc40 4136 if (kvm->created_vcpus)
49df6397
SR		 4137 goto split_irqchip_unlock;
4138 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4139 if (r)
49df6397
SR		 4140 goto split_irqchip_unlock;
4141 /* Pairs with irqchip_in_kernel. */
4142 smp_wmb();
49776faf 4143 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4144 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4145 r = 0;
4146split_irqchip_unlock:
4147 mutex_unlock(&kvm->lock);
4148 break;
4149 }
37131313
RK		 4150 case KVM_CAP_X2APIC_API:
4151 r = -EINVAL;
4152 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4153 break;
4154
4155 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4156 kvm->arch.x2apic_format = true;
c519265f
RK		 4157 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4158 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4159
4160 r = 0;
4161 break;
90de4a18
NA		 4162 default:
4163 r = -EINVAL;
4164 break;
4165 }
4166 return r;
4167}
4168
1fe779f8
CO		 4169long kvm_arch_vm_ioctl(struct file *filp,
4170 unsigned int ioctl, unsigned long arg)
4171{
4172 struct kvm *kvm = filp->private_data;
4173 void __user *argp = (void __user *)arg;
367e1319 4174 int r = -ENOTTY;
f0d66275
DH		 4175 /*
4176 * This union makes it completely explicit to gcc-3.x
4177 * that these two variables' stack usage should be
4178 * combined, not added together.
4179 */
4180 union {
4181 struct kvm_pit_state ps;
e9f42757 4182 struct kvm_pit_state2 ps2;
c5ff41ce 4183 struct kvm_pit_config pit_config;
f0d66275 4184 } u;
1fe779f8
CO		 4185
4186 switch (ioctl) {
4187 case KVM_SET_TSS_ADDR:
4188 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4189 break;
b927a3ce
SY		 4190 case KVM_SET_IDENTITY_MAP_ADDR: {
4191 u64 ident_addr;
4192
1af1ac91
DH		 4193 mutex_lock(&kvm->lock);
4194 r = -EINVAL;
4195 if (kvm->created_vcpus)
4196 goto set_identity_unlock;
b927a3ce
SY		 4197 r = -EFAULT;
4198 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4199 goto set_identity_unlock;
b927a3ce 4200 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4201set_identity_unlock:
4202 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4203 break;
4204 }
1fe779f8
CO		 4205 case KVM_SET_NR_MMU_PAGES:
4206 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4207 break;
4208 case KVM_GET_NR_MMU_PAGES:
4209 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4210 break;
3ddea128 4211 case KVM_CREATE_IRQCHIP: {
3ddea128 4212 mutex_lock(&kvm->lock);
09941366 4213
3ddea128 4214 r = -EEXIST;
35e6eaa3 4215 if (irqchip_in_kernel(kvm))
3ddea128 4216 goto create_irqchip_unlock;
09941366 4217
3e515705 4218 r = -EINVAL;
557abc40 4219 if (kvm->created_vcpus)
3e515705 4220 goto create_irqchip_unlock;
09941366
RK		 4221
4222 r = kvm_pic_init(kvm);
4223 if (r)
3ddea128 4224 goto create_irqchip_unlock;
09941366
RK		 4225
4226 r = kvm_ioapic_init(kvm);
4227 if (r) {
09941366 4228 kvm_pic_destroy(kvm);
3ddea128 4229 goto create_irqchip_unlock;
09941366
RK		 4230 }
4231
399ec807
AK		 4232 r = kvm_setup_default_irq_routing(kvm);
4233 if (r) {
72bb2fcd 4234 kvm_ioapic_destroy(kvm);
09941366 4235 kvm_pic_destroy(kvm);
71ba994c 4236 goto create_irqchip_unlock;
399ec807 4237 }
49776faf 4238 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4239 smp_wmb();
49776faf 4240 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4241 create_irqchip_unlock:
4242 mutex_unlock(&kvm->lock);
1fe779f8 4243 break;
3ddea128 4244 }
7837699f 4245 case KVM_CREATE_PIT:
c5ff41ce
JK		 4246 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4247 goto create_pit;
4248 case KVM_CREATE_PIT2:
4249 r = -EFAULT;
4250 if (copy_from_user(&u.pit_config, argp,
4251 sizeof(struct kvm_pit_config)))
4252 goto out;
4253 create_pit:
250715a6 4254 mutex_lock(&kvm->lock);
269e05e4
AK		 4255 r = -EEXIST;
4256 if (kvm->arch.vpit)
4257 goto create_pit_unlock;
7837699f 4258 r = -ENOMEM;
c5ff41ce 4259 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4260 if (kvm->arch.vpit)
4261 r = 0;
269e05e4 4262 create_pit_unlock:
250715a6 4263 mutex_unlock(&kvm->lock);
7837699f 4264 break;
1fe779f8
CO		 4265 case KVM_GET_IRQCHIP: {
4266 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4267 struct kvm_irqchip *chip;
1fe779f8 4268
ff5c2c03
SL		 4269 chip = memdup_user(argp, sizeof(*chip));
4270 if (IS_ERR(chip)) {
4271 r = PTR_ERR(chip);
1fe779f8 4272 goto out;
ff5c2c03
SL		 4273 }
4274
1fe779f8 4275 r = -ENXIO;
826da321 4276 if (!irqchip_kernel(kvm))
f0d66275
DH		 4277 goto get_irqchip_out;
4278 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4279 if (r)
f0d66275 4280 goto get_irqchip_out;
1fe779f8 4281 r = -EFAULT;
f0d66275
DH		 4282 if (copy_to_user(argp, chip, sizeof *chip))
4283 goto get_irqchip_out;
1fe779f8 4284 r = 0;
f0d66275
DH		 4285 get_irqchip_out:
4286 kfree(chip);
1fe779f8
CO		 4287 break;
4288 }
4289 case KVM_SET_IRQCHIP: {
4290 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4291 struct kvm_irqchip *chip;
1fe779f8 4292
ff5c2c03
SL		 4293 chip = memdup_user(argp, sizeof(*chip));
4294 if (IS_ERR(chip)) {
4295 r = PTR_ERR(chip);
1fe779f8 4296 goto out;
ff5c2c03
SL		 4297 }
4298
1fe779f8 4299 r = -ENXIO;
826da321 4300 if (!irqchip_kernel(kvm))
f0d66275
DH		 4301 goto set_irqchip_out;
4302 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4303 if (r)
f0d66275 4304 goto set_irqchip_out;
1fe779f8 4305 r = 0;
f0d66275
DH		 4306 set_irqchip_out:
4307 kfree(chip);
1fe779f8
CO		 4308 break;
4309 }
e0f63cb9 4310 case KVM_GET_PIT: {
e0f63cb9 4311 r = -EFAULT;
f0d66275 4312 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4313 goto out;
4314 r = -ENXIO;
4315 if (!kvm->arch.vpit)
4316 goto out;
f0d66275 4317 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4318 if (r)
4319 goto out;
4320 r = -EFAULT;
f0d66275 4321 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4322 goto out;
4323 r = 0;
4324 break;
4325 }
4326 case KVM_SET_PIT: {
e0f63cb9 4327 r = -EFAULT;
f0d66275 4328 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4329 goto out;
4330 r = -ENXIO;
4331 if (!kvm->arch.vpit)
4332 goto out;
f0d66275 4333 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4334 break;
4335 }
e9f42757
BK		 4336 case KVM_GET_PIT2: {
4337 r = -ENXIO;
4338 if (!kvm->arch.vpit)
4339 goto out;
4340 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4341 if (r)
4342 goto out;
4343 r = -EFAULT;
4344 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4345 goto out;
4346 r = 0;
4347 break;
4348 }
4349 case KVM_SET_PIT2: {
4350 r = -EFAULT;
4351 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4352 goto out;
4353 r = -ENXIO;
4354 if (!kvm->arch.vpit)
4355 goto out;
4356 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4357 break;
4358 }
52d939a0
MT		 4359 case KVM_REINJECT_CONTROL: {
4360 struct kvm_reinject_control control;
4361 r = -EFAULT;
4362 if (copy_from_user(&control, argp, sizeof(control)))
4363 goto out;
4364 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4365 break;
4366 }
d71ba788
PB		 4367 case KVM_SET_BOOT_CPU_ID:
4368 r = 0;
4369 mutex_lock(&kvm->lock);
557abc40 4370 if (kvm->created_vcpus)
d71ba788
PB		 4371 r = -EBUSY;
4372 else
4373 kvm->arch.bsp_vcpu_id = arg;
4374 mutex_unlock(&kvm->lock);
4375 break;
ffde22ac 4376 case KVM_XEN_HVM_CONFIG: {
51776043 4377 struct kvm_xen_hvm_config xhc;
ffde22ac 4378 r = -EFAULT;
51776043 4379 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4380 goto out;
4381 r = -EINVAL;
51776043 4382 if (xhc.flags)
ffde22ac 4383 goto out;
51776043 4384 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4385 r = 0;
4386 break;
4387 }
afbcf7ab 4388 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4389 struct kvm_clock_data user_ns;
4390 u64 now_ns;
afbcf7ab
GC		 4391
4392 r = -EFAULT;
4393 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4394 goto out;
4395
4396 r = -EINVAL;
4397 if (user_ns.flags)
4398 goto out;
4399
4400 r = 0;
0bc48bea
RK		 4401 /*
4402 * TODO: userspace has to take care of races with VCPU_RUN, so
4403 * kvm_gen_update_masterclock() can be cut down to locked
4404 * pvclock_update_vm_gtod_copy().
4405 */
4406 kvm_gen_update_masterclock(kvm);
e891a32e 4407 now_ns = get_kvmclock_ns(kvm);
108b249c 4408 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4409 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4410 break;
4411 }
4412 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4413 struct kvm_clock_data user_ns;
4414 u64 now_ns;
4415
e891a32e 4416 now_ns = get_kvmclock_ns(kvm);
108b249c 4417 user_ns.clock = now_ns;
e3fd9a93 4418 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4419 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4420
4421 r = -EFAULT;
4422 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4423 goto out;
4424 r = 0;
4425 break;
4426 }
90de4a18
NA		 4427 case KVM_ENABLE_CAP: {
4428 struct kvm_enable_cap cap;
afbcf7ab 4429
90de4a18
NA		 4430 r = -EFAULT;
4431 if (copy_from_user(&cap, argp, sizeof(cap)))
4432 goto out;
4433 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4434 break;
4435 }
5acc5c06
BS		 4436 case KVM_MEMORY_ENCRYPT_OP: {
4437 r = -ENOTTY;
4438 if (kvm_x86_ops->mem_enc_op)
4439 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4440 break;
4441 }
69eaedee
BS		 4442 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4443 struct kvm_enc_region region;
4444
4445 r = -EFAULT;
4446 if (copy_from_user(&region, argp, sizeof(region)))
4447 goto out;
4448
4449 r = -ENOTTY;
4450 if (kvm_x86_ops->mem_enc_reg_region)
4451 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4452 break;
4453 }
4454 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4455 struct kvm_enc_region region;
4456
4457 r = -EFAULT;
4458 if (copy_from_user(&region, argp, sizeof(region)))
4459 goto out;
4460
4461 r = -ENOTTY;
4462 if (kvm_x86_ops->mem_enc_unreg_region)
4463 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4464 break;
4465 }
1fe779f8 4466 default:
ad6260da 4467 r = -ENOTTY;
1fe779f8
CO		 4468 }
4469out:
4470 return r;
4471}
4472
a16b043c 4473static void kvm_init_msr_list(void)
043405e1
CO		 4474{
4475 u32 dummy[2];
4476 unsigned i, j;
4477
62ef68bb 4478 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4479 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4480 continue;
93c4adc7
PB		 4481
4482 /*
4483 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4484 * to the guests in some cases.
93c4adc7
PB		 4485 */
4486 switch (msrs_to_save[i]) {
4487 case MSR_IA32_BNDCFGS:
4488 if (!kvm_x86_ops->mpx_supported())
4489 continue;
4490 break;
9dbe6cf9
PB		 4491 case MSR_TSC_AUX:
4492 if (!kvm_x86_ops->rdtscp_supported())
4493 continue;
4494 break;
93c4adc7
PB		 4495 default:
4496 break;
4497 }
4498
043405e1
CO		 4499 if (j < i)
4500 msrs_to_save[j] = msrs_to_save[i];
4501 j++;
4502 }
4503 num_msrs_to_save = j;
62ef68bb
PB		 4504
4505 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4506 switch (emulated_msrs[i]) {
6d396b55
PB		 4507 case MSR_IA32_SMBASE:
4508 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4509 continue;
4510 break;
62ef68bb
PB		 4511 default:
4512 break;
4513 }
4514
4515 if (j < i)
4516 emulated_msrs[j] = emulated_msrs[i];
4517 j++;
4518 }
4519 num_emulated_msrs = j;
801e459a
TL		 4520
4521 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4522 struct kvm_msr_entry msr;
4523
4524 msr.index = msr_based_features[i];
4525 if (kvm_x86_ops->get_msr_feature(&msr))
4526 continue;
4527
4528 if (j < i)
4529 msr_based_features[j] = msr_based_features[i];
4530 j++;
4531 }
4532 num_msr_based_features = j;
043405e1
CO		 4533}
4534
bda9020e
MT		 4535static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4536 const void *v)
bbd9b64e 4537{
70252a10
AK		 4538 int handled = 0;
4539 int n;
4540
4541 do {
4542 n = min(len, 8);
bce87cce 4543 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4544 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4545 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4546 break;
4547 handled += n;
4548 addr += n;
4549 len -= n;
4550 v += n;
4551 } while (len);
bbd9b64e 4552
70252a10 4553 return handled;
bbd9b64e
CO		 4554}
4555
bda9020e 4556static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4557{
70252a10
AK		 4558 int handled = 0;
4559 int n;
4560
4561 do {
4562 n = min(len, 8);
bce87cce 4563 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4564 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4565 addr, n, v))
4566 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 4567 break;
e39d200f 4568 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 4569 handled += n;
4570 addr += n;
4571 len -= n;
4572 v += n;
4573 } while (len);
bbd9b64e 4574
70252a10 4575 return handled;
bbd9b64e
CO		 4576}
4577
2dafc6c2
GN		 4578static void kvm_set_segment(struct kvm_vcpu *vcpu,
4579 struct kvm_segment *var, int seg)
4580{
4581 kvm_x86_ops->set_segment(vcpu, var, seg);
4582}
4583
4584void kvm_get_segment(struct kvm_vcpu *vcpu,
4585 struct kvm_segment *var, int seg)
4586{
4587 kvm_x86_ops->get_segment(vcpu, var, seg);
4588}
4589
54987b7a
PB		 4590gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4591 struct x86_exception *exception)
02f59dc9
JR		 4592{
4593 gpa_t t_gpa;
02f59dc9
JR		 4594
4595 BUG_ON(!mmu_is_nested(vcpu));
4596
4597 /* NPT walks are always user-walks */
4598 access |= PFERR_USER_MASK;
54987b7a 4599 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4600
4601 return t_gpa;
4602}
4603
ab9ae313
AK		 4604gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4605 struct x86_exception *exception)
1871c602
GN		 4606{
4607 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4608 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4609}
4610
ab9ae313
AK		 4611 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4612 struct x86_exception *exception)
1871c602
GN		 4613{
4614 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4615 access |= PFERR_FETCH_MASK;
ab9ae313 4616 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4617}
4618
ab9ae313
AK		 4619gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4620 struct x86_exception *exception)
1871c602
GN		 4621{
4622 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4623 access |= PFERR_WRITE_MASK;
ab9ae313 4624 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4625}
4626
4627/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4628gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4629 struct x86_exception *exception)
1871c602 4630{
ab9ae313 4631 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4632}
4633
4634static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4635 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4636 struct x86_exception *exception)
bbd9b64e
CO		 4637{
4638 void *data = val;
10589a46 4639 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4640
4641 while (bytes) {
14dfe855 4642 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4643 exception);
bbd9b64e 4644 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4645 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4646 int ret;
4647
bcc55cba 4648 if (gpa == UNMAPPED_GVA)
ab9ae313 4649 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4650 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4651 offset, toread);
10589a46 4652 if (ret < 0) {
c3cd7ffa 4653 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4654 goto out;
4655 }
bbd9b64e 4656
77c2002e
IE		 4657 bytes -= toread;
4658 data += toread;
4659 addr += toread;
bbd9b64e 4660 }
10589a46 4661out:
10589a46 4662 return r;
bbd9b64e 4663}
77c2002e 4664
1871c602 4665/* used for instruction fetching */
0f65dd70
AK		 4666static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4667 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4668 struct x86_exception *exception)
1871c602 4669{
0f65dd70 4670 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4671 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4672 unsigned offset;
4673 int ret;
0f65dd70 4674
44583cba
PB		 4675 /* Inline kvm_read_guest_virt_helper for speed. */
4676 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4677 exception);
4678 if (unlikely(gpa == UNMAPPED_GVA))
4679 return X86EMUL_PROPAGATE_FAULT;
4680
4681 offset = addr & (PAGE_SIZE-1);
4682 if (WARN_ON(offset + bytes > PAGE_SIZE))
4683 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4684 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4685 offset, bytes);
44583cba
PB		 4686 if (unlikely(ret < 0))
4687 return X86EMUL_IO_NEEDED;
4688
4689 return X86EMUL_CONTINUE;
1871c602
GN		 4690}
4691
064aea77 4692int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4693 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4694 struct x86_exception *exception)
1871c602 4695{
0f65dd70 4696 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4697 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4698
1871c602 4699 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4700 exception);
1871c602 4701}
064aea77 4702EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4703
0f65dd70
AK		 4704static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4705 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4706 struct x86_exception *exception)
1871c602 4707{
0f65dd70 4708 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4709 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4710}
4711
7a036a6f
RK		 4712static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4713 unsigned long addr, void *val, unsigned int bytes)
4714{
4715 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4716 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4717
4718 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4719}
4720
6a4d7550 4721int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4722 gva_t addr, void *val,
2dafc6c2 4723 unsigned int bytes,
bcc55cba 4724 struct x86_exception *exception)
77c2002e 4725{
0f65dd70 4726 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4727 void *data = val;
4728 int r = X86EMUL_CONTINUE;
4729
4730 while (bytes) {
14dfe855
JR		 4731 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4732 PFERR_WRITE_MASK,
ab9ae313 4733 exception);
77c2002e
IE		 4734 unsigned offset = addr & (PAGE_SIZE-1);
4735 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4736 int ret;
4737
bcc55cba 4738 if (gpa == UNMAPPED_GVA)
ab9ae313 4739 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4740 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4741 if (ret < 0) {
c3cd7ffa 4742 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4743 goto out;
4744 }
4745
4746 bytes -= towrite;
4747 data += towrite;
4748 addr += towrite;
4749 }
4750out:
4751 return r;
4752}
6a4d7550 4753EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4754
0f89b207
TL		 4755static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4756 gpa_t gpa, bool write)
4757{
4758 /* For APIC access vmexit */
4759 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4760 return 1;
4761
4762 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4763 trace_vcpu_match_mmio(gva, gpa, write, true);
4764 return 1;
4765 }
4766
4767 return 0;
4768}
4769
af7cc7d1
XG		 4770static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4771 gpa_t *gpa, struct x86_exception *exception,
4772 bool write)
4773{
97d64b78
AK		 4774 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4775 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4776
be94f6b7
HH		 4777 /*
4778 * currently PKRU is only applied to ept enabled guest so
4779 * there is no pkey in EPT page table for L1 guest or EPT
4780 * shadow page table for L2 guest.
4781 */
97d64b78 4782 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4783 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4784 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4785 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4786 (gva & (PAGE_SIZE - 1));
4f022648 4787 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4788 return 1;
4789 }
4790
af7cc7d1
XG		 4791 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4792
4793 if (*gpa == UNMAPPED_GVA)
4794 return -1;
4795
0f89b207 4796 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4797}
4798
3200f405 4799int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4800 const void *val, int bytes)
bbd9b64e
CO		 4801{
4802 int ret;
4803
54bf36aa 4804 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4805 if (ret < 0)
bbd9b64e 4806 return 0;
0eb05bf2 4807 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4808 return 1;
4809}
4810
77d197b2
XG		 4811struct read_write_emulator_ops {
4812 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4813 int bytes);
4814 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4815 void *val, int bytes);
4816 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4817 int bytes, void *val);
4818 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4819 void *val, int bytes);
4820 bool write;
4821};
4822
4823static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4824{
4825 if (vcpu->mmio_read_completed) {
77d197b2 4826 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 4827 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 4828 vcpu->mmio_read_completed = 0;
4829 return 1;
4830 }
4831
4832 return 0;
4833}
4834
4835static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4836 void *val, int bytes)
4837{
54bf36aa 4838 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4839}
4840
4841static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4842 void *val, int bytes)
4843{
4844 return emulator_write_phys(vcpu, gpa, val, bytes);
4845}
4846
4847static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4848{
e39d200f 4849 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 4850 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4851}
4852
4853static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4854 void *val, int bytes)
4855{
e39d200f 4856 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 4857 return X86EMUL_IO_NEEDED;
4858}
4859
4860static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4861 void *val, int bytes)
4862{
f78146b0
AK		 4863 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4864
87da7e66 4865 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4866 return X86EMUL_CONTINUE;
4867}
4868
0fbe9b0b 4869static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4870 .read_write_prepare = read_prepare,
4871 .read_write_emulate = read_emulate,
4872 .read_write_mmio = vcpu_mmio_read,
4873 .read_write_exit_mmio = read_exit_mmio,
4874};
4875
0fbe9b0b 4876static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4877 .read_write_emulate = write_emulate,
4878 .read_write_mmio = write_mmio,
4879 .read_write_exit_mmio = write_exit_mmio,
4880 .write = true,
4881};
4882
22388a3c
XG		 4883static int emulator_read_write_onepage(unsigned long addr, void *val,
4884 unsigned int bytes,
4885 struct x86_exception *exception,
4886 struct kvm_vcpu *vcpu,
0fbe9b0b 4887 const struct read_write_emulator_ops *ops)
bbd9b64e 4888{
af7cc7d1
XG		 4889 gpa_t gpa;
4890 int handled, ret;
22388a3c 4891 bool write = ops->write;
f78146b0 4892 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4893 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4894
4895 /*
4896 * If the exit was due to a NPF we may already have a GPA.
4897 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4898 * Note, this cannot be used on string operations since string
4899 * operation using rep will only have the initial GPA from the NPF
4900 * occurred.
4901 */
4902 if (vcpu->arch.gpa_available &&
4903 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 4904 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
4905 gpa = vcpu->arch.gpa_val;
4906 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
4907 } else {
4908 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4909 if (ret < 0)
4910 return X86EMUL_PROPAGATE_FAULT;
0f89b207 4911 }
10589a46 4912
618232e2 4913 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4914 return X86EMUL_CONTINUE;
4915
bbd9b64e
CO		 4916 /*
4917 * Is this MMIO handled locally?
4918 */
22388a3c 4919 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4920 if (handled == bytes)
bbd9b64e 4921 return X86EMUL_CONTINUE;
bbd9b64e 4922
70252a10
AK		 4923 gpa += handled;
4924 bytes -= handled;
4925 val += handled;
4926
87da7e66
XG		 4927 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4928 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4929 frag->gpa = gpa;
4930 frag->data = val;
4931 frag->len = bytes;
f78146b0 4932 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4933}
4934
52eb5a6d
XL		 4935static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4936 unsigned long addr,
22388a3c
XG		 4937 void *val, unsigned int bytes,
4938 struct x86_exception *exception,
0fbe9b0b 4939 const struct read_write_emulator_ops *ops)
bbd9b64e 4940{
0f65dd70 4941 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4942 gpa_t gpa;
4943 int rc;
4944
4945 if (ops->read_write_prepare &&
4946 ops->read_write_prepare(vcpu, val, bytes))
4947 return X86EMUL_CONTINUE;
4948
4949 vcpu->mmio_nr_fragments = 0;
0f65dd70 4950
bbd9b64e
CO		 4951 /* Crossing a page boundary? */
4952 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4953 int now;
bbd9b64e
CO		 4954
4955 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4956 rc = emulator_read_write_onepage(addr, val, now, exception,
4957 vcpu, ops);
4958
bbd9b64e
CO		 4959 if (rc != X86EMUL_CONTINUE)
4960 return rc;
4961 addr += now;
bac15531
NA		 4962 if (ctxt->mode != X86EMUL_MODE_PROT64)
4963 addr = (u32)addr;
bbd9b64e
CO		 4964 val += now;
4965 bytes -= now;
4966 }
22388a3c 4967
f78146b0
AK		 4968 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4969 vcpu, ops);
4970 if (rc != X86EMUL_CONTINUE)
4971 return rc;
4972
4973 if (!vcpu->mmio_nr_fragments)
4974 return rc;
4975
4976 gpa = vcpu->mmio_fragments[0].gpa;
4977
4978 vcpu->mmio_needed = 1;
4979 vcpu->mmio_cur_fragment = 0;
4980
87da7e66 4981 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4982 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4983 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4984 vcpu->run->mmio.phys_addr = gpa;
4985
4986 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4987}
4988
4989static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4990 unsigned long addr,
4991 void *val,
4992 unsigned int bytes,
4993 struct x86_exception *exception)
4994{
4995 return emulator_read_write(ctxt, addr, val, bytes,
4996 exception, &read_emultor);
4997}
4998
52eb5a6d 4999static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5000 unsigned long addr,
5001 const void *val,
5002 unsigned int bytes,
5003 struct x86_exception *exception)
5004{
5005 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5006 exception, &write_emultor);
bbd9b64e 5007}
bbd9b64e 5008
daea3e73
AK		 5009#define CMPXCHG_TYPE(t, ptr, old, new) \
5010 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5011
5012#ifdef CONFIG_X86_64
5013# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5014#else
5015# define CMPXCHG64(ptr, old, new) \
9749a6c0 5016 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5017#endif
5018
0f65dd70
AK		 5019static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5020 unsigned long addr,
bbd9b64e
CO		 5021 const void *old,
5022 const void *new,
5023 unsigned int bytes,
0f65dd70 5024 struct x86_exception *exception)
bbd9b64e 5025{
0f65dd70 5026 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 5027 gpa_t gpa;
5028 struct page *page;
5029 char *kaddr;
5030 bool exchanged;
2bacc55c 5031
daea3e73
AK		 5032 /* guests cmpxchg8b have to be emulated atomically */
5033 if (bytes > 8 || (bytes & (bytes - 1)))
5034 goto emul_write;
10589a46 5035
daea3e73 5036 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5037
daea3e73
AK		 5038 if (gpa == UNMAPPED_GVA ||
5039 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5040 goto emul_write;
2bacc55c 5041
daea3e73
AK		 5042 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5043 goto emul_write;
72dc67a6 5044
54bf36aa 5045 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 5046 if (is_error_page(page))
c19b8bd6 5047 goto emul_write;
72dc67a6 5048
8fd75e12 5049 kaddr = kmap_atomic(page);
daea3e73
AK		 5050 kaddr += offset_in_page(gpa);
5051 switch (bytes) {
5052 case 1:
5053 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5054 break;
5055 case 2:
5056 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5057 break;
5058 case 4:
5059 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5060 break;
5061 case 8:
5062 exchanged = CMPXCHG64(kaddr, old, new);
5063 break;
5064 default:
5065 BUG();
2bacc55c 5066 }
8fd75e12 5067 kunmap_atomic(kaddr);
daea3e73
AK		 5068 kvm_release_page_dirty(page);
5069
5070 if (!exchanged)
5071 return X86EMUL_CMPXCHG_FAILED;
5072
54bf36aa 5073 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 5074 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5075
5076 return X86EMUL_CONTINUE;
4a5f48f6 5077
3200f405 5078emul_write:
daea3e73 5079 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5080
0f65dd70 5081 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5082}
5083
cf8f70bf
GN		 5084static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5085{
cbfc6c91 5086 int r = 0, i;
cf8f70bf 5087
cbfc6c91
WL		 5088 for (i = 0; i < vcpu->arch.pio.count; i++) {
5089 if (vcpu->arch.pio.in)
5090 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5091 vcpu->arch.pio.size, pd);
5092 else
5093 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5094 vcpu->arch.pio.port, vcpu->arch.pio.size,
5095 pd);
5096 if (r)
5097 break;
5098 pd += vcpu->arch.pio.size;
5099 }
cf8f70bf
GN		 5100 return r;
5101}
5102
6f6fbe98
XG		 5103static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5104 unsigned short port, void *val,
5105 unsigned int count, bool in)
cf8f70bf 5106{
cf8f70bf 5107 vcpu->arch.pio.port = port;
6f6fbe98 5108 vcpu->arch.pio.in = in;
7972995b 5109 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5110 vcpu->arch.pio.size = size;
5111
5112 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5113 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5114 return 1;
5115 }
5116
5117 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5118 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5119 vcpu->run->io.size = size;
5120 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5121 vcpu->run->io.count = count;
5122 vcpu->run->io.port = port;
5123
5124 return 0;
5125}
5126
6f6fbe98
XG		 5127static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5128 int size, unsigned short port, void *val,
5129 unsigned int count)
cf8f70bf 5130{
ca1d4a9e 5131 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5132 int ret;
ca1d4a9e 5133
6f6fbe98
XG		 5134 if (vcpu->arch.pio.count)
5135 goto data_avail;
cf8f70bf 5136
cbfc6c91
WL		 5137 memset(vcpu->arch.pio_data, 0, size * count);
5138
6f6fbe98
XG		 5139 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5140 if (ret) {
5141data_avail:
5142 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5143 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5144 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5145 return 1;
5146 }
5147
cf8f70bf
GN		 5148 return 0;
5149}
5150
6f6fbe98
XG		 5151static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5152 int size, unsigned short port,
5153 const void *val, unsigned int count)
5154{
5155 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5156
5157 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5158 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5159 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5160}
5161
bbd9b64e
CO		 5162static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5163{
5164 return kvm_x86_ops->get_segment_base(vcpu, seg);
5165}
5166
3cb16fe7 5167static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5168{
3cb16fe7 5169 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5170}
5171
ae6a2375 5172static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5173{
5174 if (!need_emulate_wbinvd(vcpu))
5175 return X86EMUL_CONTINUE;
5176
5177 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5178 int cpu = get_cpu();
5179
5180 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5181 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5182 wbinvd_ipi, NULL, 1);
2eec7343 5183 put_cpu();
f5f48ee1 5184 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5185 } else
5186 wbinvd();
f5f48ee1
SY		 5187 return X86EMUL_CONTINUE;
5188}
5cb56059
JS		 5189
5190int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5191{
6affcbed
KH		 5192 kvm_emulate_wbinvd_noskip(vcpu);
5193 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5194}
f5f48ee1
SY		 5195EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5196
5cb56059
JS		 5197
5198
bcaf5cc5
AK		 5199static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5200{
5cb56059 5201 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5202}
5203
52eb5a6d
XL		 5204static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5205 unsigned long *dest)
bbd9b64e 5206{
16f8a6f9 5207 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5208}
5209
52eb5a6d
XL		 5210static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5211 unsigned long value)
bbd9b64e 5212{
338dbc97 5213
717746e3 5214 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5215}
5216
52a46617 5217static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5218{
52a46617 5219 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5220}
5221
717746e3 5222static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5223{
717746e3 5224 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5225 unsigned long value;
5226
5227 switch (cr) {
5228 case 0:
5229 value = kvm_read_cr0(vcpu);
5230 break;
5231 case 2:
5232 value = vcpu->arch.cr2;
5233 break;
5234 case 3:
9f8fe504 5235 value = kvm_read_cr3(vcpu);
52a46617
GN		 5236 break;
5237 case 4:
5238 value = kvm_read_cr4(vcpu);
5239 break;
5240 case 8:
5241 value = kvm_get_cr8(vcpu);
5242 break;
5243 default:
a737f256 5244 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5245 return 0;
5246 }
5247
5248 return value;
5249}
5250
717746e3 5251static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5252{
717746e3 5253 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5254 int res = 0;
5255
52a46617
GN		 5256 switch (cr) {
5257 case 0:
49a9b07e 5258 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5259 break;
5260 case 2:
5261 vcpu->arch.cr2 = val;
5262 break;
5263 case 3:
2390218b 5264 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5265 break;
5266 case 4:
a83b29c6 5267 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5268 break;
5269 case 8:
eea1cff9 5270 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5271 break;
5272 default:
a737f256 5273 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5274 res = -1;
52a46617 5275 }
0f12244f
GN		 5276
5277 return res;
52a46617
GN		 5278}
5279
717746e3 5280static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5281{
717746e3 5282 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5283}
5284
4bff1e86 5285static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5286{
4bff1e86 5287 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5288}
5289
4bff1e86 5290static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5291{
4bff1e86 5292 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5293}
5294
1ac9d0cf
AK		 5295static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5296{
5297 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5298}
5299
5300static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5301{
5302 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5303}
5304
4bff1e86
AK		 5305static unsigned long emulator_get_cached_segment_base(
5306 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5307{
4bff1e86 5308 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5309}
5310
1aa36616
AK		 5311static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5312 struct desc_struct *desc, u32 *base3,
5313 int seg)
2dafc6c2
GN		 5314{
5315 struct kvm_segment var;
5316
4bff1e86 5317 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5318 *selector = var.selector;
2dafc6c2 5319
378a8b09
GN		 5320 if (var.unusable) {
5321 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5322 if (base3)
5323 *base3 = 0;
2dafc6c2 5324 return false;
378a8b09 5325 }
2dafc6c2
GN		 5326
5327 if (var.g)
5328 var.limit >>= 12;
5329 set_desc_limit(desc, var.limit);
5330 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5331#ifdef CONFIG_X86_64
5332 if (base3)
5333 *base3 = var.base >> 32;
5334#endif
2dafc6c2
GN		 5335 desc->type = var.type;
5336 desc->s = var.s;
5337 desc->dpl = var.dpl;
5338 desc->p = var.present;
5339 desc->avl = var.avl;
5340 desc->l = var.l;
5341 desc->d = var.db;
5342 desc->g = var.g;
5343
5344 return true;
5345}
5346
1aa36616
AK		 5347static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5348 struct desc_struct *desc, u32 base3,
5349 int seg)
2dafc6c2 5350{
4bff1e86 5351 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5352 struct kvm_segment var;
5353
1aa36616 5354 var.selector = selector;
2dafc6c2 5355 var.base = get_desc_base(desc);
5601d05b
GN		 5356#ifdef CONFIG_X86_64
5357 var.base |= ((u64)base3) << 32;
5358#endif
2dafc6c2
GN		 5359 var.limit = get_desc_limit(desc);
5360 if (desc->g)
5361 var.limit = (var.limit << 12) | 0xfff;
5362 var.type = desc->type;
2dafc6c2
GN		 5363 var.dpl = desc->dpl;
5364 var.db = desc->d;
5365 var.s = desc->s;
5366 var.l = desc->l;
5367 var.g = desc->g;
5368 var.avl = desc->avl;
5369 var.present = desc->p;
5370 var.unusable = !var.present;
5371 var.padding = 0;
5372
5373 kvm_set_segment(vcpu, &var, seg);
5374 return;
5375}
5376
717746e3
AK		 5377static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5378 u32 msr_index, u64 *pdata)
5379{
609e36d3
PB		 5380 struct msr_data msr;
5381 int r;
5382
5383 msr.index = msr_index;
5384 msr.host_initiated = false;
5385 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5386 if (r)
5387 return r;
5388
5389 *pdata = msr.data;
5390 return 0;
717746e3
AK		 5391}
5392
5393static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5394 u32 msr_index, u64 data)
5395{
8fe8ab46
WA		 5396 struct msr_data msr;
5397
5398 msr.data = data;
5399 msr.index = msr_index;
5400 msr.host_initiated = false;
5401 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5402}
5403
64d60670
PB		 5404static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5405{
5406 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5407
5408 return vcpu->arch.smbase;
5409}
5410
5411static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5412{
5413 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5414
5415 vcpu->arch.smbase = smbase;
5416}
5417
67f4d428
NA		 5418static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5419 u32 pmc)
5420{
c6702c9d 5421 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5422}
5423
222d21aa
AK		 5424static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5425 u32 pmc, u64 *pdata)
5426{
c6702c9d 5427 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5428}
5429
6c3287f7
AK		 5430static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5431{
5432 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5433}
5434
2953538e 5435static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5436 struct x86_instruction_info *info,
c4f035c6
AK		 5437 enum x86_intercept_stage stage)
5438{
2953538e 5439 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5440}
5441
e911eb3b
YZ		 5442static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5443 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5444{
e911eb3b 5445 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5446}
5447
dd856efa
AK		 5448static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5449{
5450 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5451}
5452
5453static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5454{
5455 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5456}
5457
801806d9
NA		 5458static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5459{
5460 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5461}
5462
6ed071f0
LP		 5463static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5464{
5465 return emul_to_vcpu(ctxt)->arch.hflags;
5466}
5467
5468static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5469{
5470 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5471}
5472
0234bf88
LP		 5473static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5474{
5475 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5476}
5477
0225fb50 5478static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5479 .read_gpr = emulator_read_gpr,
5480 .write_gpr = emulator_write_gpr,
1871c602 5481 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5482 .write_std = kvm_write_guest_virt_system,
7a036a6f 5483 .read_phys = kvm_read_guest_phys_system,
1871c602 5484 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5485 .read_emulated = emulator_read_emulated,
5486 .write_emulated = emulator_write_emulated,
5487 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5488 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5489 .pio_in_emulated = emulator_pio_in_emulated,
5490 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5491 .get_segment = emulator_get_segment,
5492 .set_segment = emulator_set_segment,
5951c442 5493 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5494 .get_gdt = emulator_get_gdt,
160ce1f1 5495 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5496 .set_gdt = emulator_set_gdt,
5497 .set_idt = emulator_set_idt,
52a46617
GN		 5498 .get_cr = emulator_get_cr,
5499 .set_cr = emulator_set_cr,
9c537244 5500 .cpl = emulator_get_cpl,
35aa5375
GN		 5501 .get_dr = emulator_get_dr,
5502 .set_dr = emulator_set_dr,
64d60670
PB		 5503 .get_smbase = emulator_get_smbase,
5504 .set_smbase = emulator_set_smbase,
717746e3
AK		 5505 .set_msr = emulator_set_msr,
5506 .get_msr = emulator_get_msr,
67f4d428 5507 .check_pmc = emulator_check_pmc,
222d21aa 5508 .read_pmc = emulator_read_pmc,
6c3287f7 5509 .halt = emulator_halt,
bcaf5cc5 5510 .wbinvd = emulator_wbinvd,
d6aa1000 5511 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5512 .intercept = emulator_intercept,
bdb42f5a 5513 .get_cpuid = emulator_get_cpuid,
801806d9 5514 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5515 .get_hflags = emulator_get_hflags,
5516 .set_hflags = emulator_set_hflags,
0234bf88 5517 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5518};
5519
95cb2295
GN		 5520static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5521{
37ccdcbe 5522 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5523 /*
5524 * an sti; sti; sequence only disable interrupts for the first
5525 * instruction. So, if the last instruction, be it emulated or
5526 * not, left the system with the INT_STI flag enabled, it
5527 * means that the last instruction is an sti. We should not
5528 * leave the flag on in this case. The same goes for mov ss
5529 */
37ccdcbe
PB		 5530 if (int_shadow & mask)
5531 mask = 0;
6addfc42 5532 if (unlikely(int_shadow || mask)) {
95cb2295 5533 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5534 if (!mask)
5535 kvm_make_request(KVM_REQ_EVENT, vcpu);
5536 }
95cb2295
GN		 5537}
5538
ef54bcfe 5539static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5540{
5541 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5542 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5543 return kvm_propagate_fault(vcpu, &ctxt->exception);
5544
5545 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5546 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5547 ctxt->exception.error_code);
54b8486f 5548 else
da9cb575 5549 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5550 return false;
54b8486f
GN		 5551}
5552
8ec4722d
MG		 5553static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5554{
adf52235 5555 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5556 int cs_db, cs_l;
5557
8ec4722d
MG		 5558 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5559
adf52235 5560 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5561 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5562
adf52235
TY		 5563 ctxt->eip = kvm_rip_read(vcpu);
5564 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5565 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5566 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5567 cs_db ? X86EMUL_MODE_PROT32 :
5568 X86EMUL_MODE_PROT16;
a584539b 5569 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5570 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5571 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5572
dd856efa 5573 init_decode_cache(ctxt);
7ae441ea 5574 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5575}
5576
71f9833b 5577int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5578{
9d74191a 5579 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5580 int ret;
5581
5582 init_emulate_ctxt(vcpu);
5583
9dac77fa
AK		 5584 ctxt->op_bytes = 2;
5585 ctxt->ad_bytes = 2;
5586 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5587 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5588
5589 if (ret != X86EMUL_CONTINUE)
5590 return EMULATE_FAIL;
5591
9dac77fa 5592 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5593 kvm_rip_write(vcpu, ctxt->eip);
5594 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5595
5596 if (irq == NMI_VECTOR)
7460fb4a 5597 vcpu->arch.nmi_pending = 0;
63995653
MG		 5598 else
5599 vcpu->arch.interrupt.pending = false;
5600
5601 return EMULATE_DONE;
5602}
5603EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5604
6d77dbfc
GN		 5605static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5606{
fc3a9157
JR		 5607 int r = EMULATE_DONE;
5608
6d77dbfc
GN		 5609 ++vcpu->stat.insn_emulation_fail;
5610 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5611 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5612 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5613 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5614 vcpu->run->internal.ndata = 0;
1f4dcb3b 5615 r = EMULATE_USER_EXIT;
fc3a9157 5616 }
6d77dbfc 5617 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5618
5619 return r;
6d77dbfc
GN		 5620}
5621
93c05d3e 5622static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5623 bool write_fault_to_shadow_pgtable,
5624 int emulation_type)
a6f177ef 5625{
95b3cf69 5626 gpa_t gpa = cr2;
ba049e93 5627 kvm_pfn_t pfn;
a6f177ef 5628
991eebf9
GN		 5629 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5630 return false;
5631
95b3cf69
XG		 5632 if (!vcpu->arch.mmu.direct_map) {
5633 /*
5634 * Write permission should be allowed since only
5635 * write access need to be emulated.
5636 */
5637 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5638
95b3cf69
XG		 5639 /*
5640 * If the mapping is invalid in guest, let cpu retry
5641 * it to generate fault.
5642 */
5643 if (gpa == UNMAPPED_GVA)
5644 return true;
5645 }
a6f177ef 5646
8e3d9d06
XG		 5647 /*
5648 * Do not retry the unhandleable instruction if it faults on the
5649 * readonly host memory, otherwise it will goto a infinite loop:
5650 * retry instruction -> write #PF -> emulation fail -> retry
5651 * instruction -> ...
5652 */
5653 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5654
5655 /*
5656 * If the instruction failed on the error pfn, it can not be fixed,
5657 * report the error to userspace.
5658 */
5659 if (is_error_noslot_pfn(pfn))
5660 return false;
5661
5662 kvm_release_pfn_clean(pfn);
5663
5664 /* The instructions are well-emulated on direct mmu. */
5665 if (vcpu->arch.mmu.direct_map) {
5666 unsigned int indirect_shadow_pages;
5667
5668 spin_lock(&vcpu->kvm->mmu_lock);
5669 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5670 spin_unlock(&vcpu->kvm->mmu_lock);
5671
5672 if (indirect_shadow_pages)
5673 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5674
a6f177ef 5675 return true;
8e3d9d06 5676 }
a6f177ef 5677
95b3cf69
XG		 5678 /*
5679 * if emulation was due to access to shadowed page table
5680 * and it failed try to unshadow page and re-enter the
5681 * guest to let CPU execute the instruction.
5682 */
5683 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5684
5685 /*
5686 * If the access faults on its page table, it can not
5687 * be fixed by unprotecting shadow page and it should
5688 * be reported to userspace.
5689 */
5690 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5691}
5692
1cb3f3ae
XG		 5693static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5694 unsigned long cr2, int emulation_type)
5695{
5696 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5697 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5698
5699 last_retry_eip = vcpu->arch.last_retry_eip;
5700 last_retry_addr = vcpu->arch.last_retry_addr;
5701
5702 /*
5703 * If the emulation is caused by #PF and it is non-page_table
5704 * writing instruction, it means the VM-EXIT is caused by shadow
5705 * page protected, we can zap the shadow page and retry this
5706 * instruction directly.
5707 *
5708 * Note: if the guest uses a non-page-table modifying instruction
5709 * on the PDE that points to the instruction, then we will unmap
5710 * the instruction and go to an infinite loop. So, we cache the
5711 * last retried eip and the last fault address, if we meet the eip
5712 * and the address again, we can break out of the potential infinite
5713 * loop.
5714 */
5715 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5716
5717 if (!(emulation_type & EMULTYPE_RETRY))
5718 return false;
5719
5720 if (x86_page_table_writing_insn(ctxt))
5721 return false;
5722
5723 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5724 return false;
5725
5726 vcpu->arch.last_retry_eip = ctxt->eip;
5727 vcpu->arch.last_retry_addr = cr2;
5728
5729 if (!vcpu->arch.mmu.direct_map)
5730 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5731
22368028 5732 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5733
5734 return true;
5735}
5736
716d51ab
GN		 5737static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5738static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5739
64d60670 5740static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5741{
64d60670 5742 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5743 /* This is a good place to trace that we are exiting SMM. */
5744 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5745
c43203ca
PB		 5746 /* Process a latched INIT or SMI, if any. */
5747 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5748 }
699023e2
PB		 5749
5750 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5751}
5752
5753static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5754{
5755 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5756
a584539b 5757 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5758
5759 if (changed & HF_SMM_MASK)
5760 kvm_smm_changed(vcpu);
a584539b
PB		 5761}
5762
4a1e10d5
PB		 5763static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5764 unsigned long *db)
5765{
5766 u32 dr6 = 0;
5767 int i;
5768 u32 enable, rwlen;
5769
5770 enable = dr7;
5771 rwlen = dr7 >> 16;
5772 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5773 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5774 dr6 |= (1 << i);
5775 return dr6;
5776}
5777
c8401dda 5778static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5779{
5780 struct kvm_run *kvm_run = vcpu->run;
5781
c8401dda
PB		 5782 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5783 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5784 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5785 kvm_run->debug.arch.exception = DB_VECTOR;
5786 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5787 *r = EMULATE_USER_EXIT;
5788 } else {
5789 /*
5790 * "Certain debug exceptions may clear bit 0-3. The
5791 * remaining contents of the DR6 register are never
5792 * cleared by the processor".
5793 */
5794 vcpu->arch.dr6 &= ~15;
5795 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5796 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5797 }
5798}
5799
6affcbed
KH		 5800int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5801{
5802 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5803 int r = EMULATE_DONE;
5804
5805 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5806
5807 /*
5808 * rflags is the old, "raw" value of the flags. The new value has
5809 * not been saved yet.
5810 *
5811 * This is correct even for TF set by the guest, because "the
5812 * processor will not generate this exception after the instruction
5813 * that sets the TF flag".
5814 */
5815 if (unlikely(rflags & X86_EFLAGS_TF))
5816 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5817 return r == EMULATE_DONE;
5818}
5819EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5820
4a1e10d5
PB		 5821static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5822{
4a1e10d5
PB		 5823 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5824 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5825 struct kvm_run *kvm_run = vcpu->run;
5826 unsigned long eip = kvm_get_linear_rip(vcpu);
5827 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5828 vcpu->arch.guest_debug_dr7,
5829 vcpu->arch.eff_db);
5830
5831 if (dr6 != 0) {
6f43ed01 5832 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5833 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5834 kvm_run->debug.arch.exception = DB_VECTOR;
5835 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5836 *r = EMULATE_USER_EXIT;
5837 return true;
5838 }
5839 }
5840
4161a569
NA		 5841 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5842 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5843 unsigned long eip = kvm_get_linear_rip(vcpu);
5844 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5845 vcpu->arch.dr7,
5846 vcpu->arch.db);
5847
5848 if (dr6 != 0) {
5849 vcpu->arch.dr6 &= ~15;
6f43ed01 5850 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5851 kvm_queue_exception(vcpu, DB_VECTOR);
5852 *r = EMULATE_DONE;
5853 return true;
5854 }
5855 }
5856
5857 return false;
5858}
5859
51d8b661
AP		 5860int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5861 unsigned long cr2,
dc25e89e
AP		 5862 int emulation_type,
5863 void *insn,
5864 int insn_len)
bbd9b64e 5865{
95cb2295 5866 int r;
9d74191a 5867 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5868 bool writeback = true;
93c05d3e 5869 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5870
93c05d3e
XG		 5871 /*
5872 * Clear write_fault_to_shadow_pgtable here to ensure it is
5873 * never reused.
5874 */
5875 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5876 kvm_clear_exception_queue(vcpu);
8d7d8102 5877
571008da 5878 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5879 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5880
5881 /*
5882 * We will reenter on the same instruction since
5883 * we do not set complete_userspace_io. This does not
5884 * handle watchpoints yet, those would be handled in
5885 * the emulate_ops.
5886 */
d391f120
VK		 5887 if (!(emulation_type & EMULTYPE_SKIP) &&
5888 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 5889 return r;
5890
9d74191a
TY		 5891 ctxt->interruptibility = 0;
5892 ctxt->have_exception = false;
e0ad0b47 5893 ctxt->exception.vector = -1;
9d74191a 5894 ctxt->perm_ok = false;
bbd9b64e 5895
b51e974f 5896 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5897
9d74191a 5898 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5899
e46479f8 5900 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5901 ++vcpu->stat.insn_emulation;
1d2887e2 5902 if (r != EMULATION_OK) {
4005996e
AK		 5903 if (emulation_type & EMULTYPE_TRAP_UD)
5904 return EMULATE_FAIL;
991eebf9
GN		 5905 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5906 emulation_type))
bbd9b64e 5907 return EMULATE_DONE;
6ea6e843
PB		 5908 if (ctxt->have_exception && inject_emulated_exception(vcpu))
5909 return EMULATE_DONE;
6d77dbfc
GN		 5910 if (emulation_type & EMULTYPE_SKIP)
5911 return EMULATE_FAIL;
5912 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5913 }
5914 }
5915
ba8afb6b 5916 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5917 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5918 if (ctxt->eflags & X86_EFLAGS_RF)
5919 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5920 return EMULATE_DONE;
5921 }
5922
1cb3f3ae
XG		 5923 if (retry_instruction(ctxt, cr2, emulation_type))
5924 return EMULATE_DONE;
5925
7ae441ea 5926 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5927 changes registers values during IO operation */
7ae441ea
GN		 5928 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5929 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5930 emulator_invalidate_register_cache(ctxt);
7ae441ea 5931 }
4d2179e1 5932
5cd21917 5933restart:
0f89b207
TL		 5934 /* Save the faulting GPA (cr2) in the address field */
5935 ctxt->exception.address = cr2;
5936
9d74191a 5937 r = x86_emulate_insn(ctxt);
bbd9b64e 5938
775fde86
JR		 5939 if (r == EMULATION_INTERCEPTED)
5940 return EMULATE_DONE;
5941
d2ddd1c4 5942 if (r == EMULATION_FAILED) {
991eebf9
GN		 5943 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5944 emulation_type))
c3cd7ffa
GN		 5945 return EMULATE_DONE;
5946
6d77dbfc 5947 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5948 }
5949
9d74191a 5950 if (ctxt->have_exception) {
d2ddd1c4 5951 r = EMULATE_DONE;
ef54bcfe
PB		 5952 if (inject_emulated_exception(vcpu))
5953 return r;
d2ddd1c4 5954 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5955 if (!vcpu->arch.pio.in) {
5956 /* FIXME: return into emulator if single-stepping. */
3457e419 5957 vcpu->arch.pio.count = 0;
0912c977 5958 } else {
7ae441ea 5959 writeback = false;
716d51ab
GN		 5960 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5961 }
ac0a48c3 5962 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5963 } else if (vcpu->mmio_needed) {
5964 if (!vcpu->mmio_is_write)
5965 writeback = false;
ac0a48c3 5966 r = EMULATE_USER_EXIT;
716d51ab 5967 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5968 } else if (r == EMULATION_RESTART)
5cd21917 5969 goto restart;
d2ddd1c4
GN		 5970 else
5971 r = EMULATE_DONE;
f850e2e6 5972
7ae441ea 5973 if (writeback) {
6addfc42 5974 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5975 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5976 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5977 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 5978 if (r == EMULATE_DONE &&
5979 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
5980 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 5981 if (!ctxt->have_exception ||
5982 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5983 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5984
5985 /*
5986 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5987 * do nothing, and it will be requested again as soon as
5988 * the shadow expires. But we still need to check here,
5989 * because POPF has no interrupt shadow.
5990 */
5991 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5992 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5993 } else
5994 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5995
5996 return r;
de7d789a 5997}
51d8b661 5998EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5999
cf8f70bf 6000int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 6001{
cf8f70bf 6002 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 6003 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6004 size, port, &val, 1);
cf8f70bf 6005 /* do not return to emulator after return from userspace */
7972995b 6006 vcpu->arch.pio.count = 0;
de7d789a
CO		 6007 return ret;
6008}
cf8f70bf 6009EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 6010
8370c3d0
TL		 6011static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6012{
6013 unsigned long val;
6014
6015 /* We should only ever be called with arch.pio.count equal to 1 */
6016 BUG_ON(vcpu->arch.pio.count != 1);
6017
6018 /* For size less than 4 we merge, else we zero extend */
6019 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6020 : 0;
6021
6022 /*
6023 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6024 * the copy and tracing
6025 */
6026 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6027 vcpu->arch.pio.port, &val, 1);
6028 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6029
6030 return 1;
6031}
6032
6033int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
6034{
6035 unsigned long val;
6036 int ret;
6037
6038 /* For size less than 4 we merge, else we zero extend */
6039 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6040
6041 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6042 &val, 1);
6043 if (ret) {
6044 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6045 return ret;
6046 }
6047
6048 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6049
6050 return 0;
6051}
6052EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
6053
251a5fd6 6054static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6055{
0a3aee0d 6056 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6057 return 0;
8cfdc000
ZA		 6058}
6059
6060static void tsc_khz_changed(void *data)
c8076604 6061{
8cfdc000
ZA		 6062 struct cpufreq_freqs *freq = data;
6063 unsigned long khz = 0;
6064
6065 if (data)
6066 khz = freq->new;
6067 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6068 khz = cpufreq_quick_get(raw_smp_processor_id());
6069 if (!khz)
6070 khz = tsc_khz;
0a3aee0d 6071 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6072}
6073
5fa4ec9c 6074#ifdef CONFIG_X86_64
0092e434
VK		 6075static void kvm_hyperv_tsc_notifier(void)
6076{
0092e434
VK		 6077 struct kvm *kvm;
6078 struct kvm_vcpu *vcpu;
6079 int cpu;
6080
6081 spin_lock(&kvm_lock);
6082 list_for_each_entry(kvm, &vm_list, vm_list)
6083 kvm_make_mclock_inprogress_request(kvm);
6084
6085 hyperv_stop_tsc_emulation();
6086
6087 /* TSC frequency always matches when on Hyper-V */
6088 for_each_present_cpu(cpu)
6089 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6090 kvm_max_guest_tsc_khz = tsc_khz;
6091
6092 list_for_each_entry(kvm, &vm_list, vm_list) {
6093 struct kvm_arch *ka = &kvm->arch;
6094
6095 spin_lock(&ka->pvclock_gtod_sync_lock);
6096
6097 pvclock_update_vm_gtod_copy(kvm);
6098
6099 kvm_for_each_vcpu(cpu, vcpu, kvm)
6100 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6101
6102 kvm_for_each_vcpu(cpu, vcpu, kvm)
6103 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6104
6105 spin_unlock(&ka->pvclock_gtod_sync_lock);
6106 }
6107 spin_unlock(&kvm_lock);
0092e434 6108}
5fa4ec9c 6109#endif
0092e434 6110
c8076604
GH		 6111static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6112 void *data)
6113{
6114 struct cpufreq_freqs *freq = data;
6115 struct kvm *kvm;
6116 struct kvm_vcpu *vcpu;
6117 int i, send_ipi = 0;
6118
8cfdc000
ZA		 6119 /*
6120 * We allow guests to temporarily run on slowing clocks,
6121 * provided we notify them after, or to run on accelerating
6122 * clocks, provided we notify them before. Thus time never
6123 * goes backwards.
6124 *
6125 * However, we have a problem. We can't atomically update
6126 * the frequency of a given CPU from this function; it is
6127 * merely a notifier, which can be called from any CPU.
6128 * Changing the TSC frequency at arbitrary points in time
6129 * requires a recomputation of local variables related to
6130 * the TSC for each VCPU. We must flag these local variables
6131 * to be updated and be sure the update takes place with the
6132 * new frequency before any guests proceed.
6133 *
6134 * Unfortunately, the combination of hotplug CPU and frequency
6135 * change creates an intractable locking scenario; the order
6136 * of when these callouts happen is undefined with respect to
6137 * CPU hotplug, and they can race with each other. As such,
6138 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6139 * undefined; you can actually have a CPU frequency change take
6140 * place in between the computation of X and the setting of the
6141 * variable. To protect against this problem, all updates of
6142 * the per_cpu tsc_khz variable are done in an interrupt
6143 * protected IPI, and all callers wishing to update the value
6144 * must wait for a synchronous IPI to complete (which is trivial
6145 * if the caller is on the CPU already). This establishes the
6146 * necessary total order on variable updates.
6147 *
6148 * Note that because a guest time update may take place
6149 * anytime after the setting of the VCPU's request bit, the
6150 * correct TSC value must be set before the request. However,
6151 * to ensure the update actually makes it to any guest which
6152 * starts running in hardware virtualization between the set
6153 * and the acquisition of the spinlock, we must also ping the
6154 * CPU after setting the request bit.
6155 *
6156 */
6157
c8076604
GH		 6158 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6159 return 0;
6160 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6161 return 0;
8cfdc000
ZA		 6162
6163 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 6164
2f303b74 6165 spin_lock(&kvm_lock);
c8076604 6166 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6167 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 6168 if (vcpu->cpu != freq->cpu)
6169 continue;
c285545f 6170 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 6171 if (vcpu->cpu != smp_processor_id())
8cfdc000 6172 send_ipi = 1;
c8076604
GH		 6173 }
6174 }
2f303b74 6175 spin_unlock(&kvm_lock);
c8076604
GH		 6176
6177 if (freq->old < freq->new && send_ipi) {
6178 /*
6179 * We upscale the frequency. Must make the guest
6180 * doesn't see old kvmclock values while running with
6181 * the new frequency, otherwise we risk the guest sees
6182 * time go backwards.
6183 *
6184 * In case we update the frequency for another cpu
6185 * (which might be in guest context) send an interrupt
6186 * to kick the cpu out of guest context. Next time
6187 * guest context is entered kvmclock will be updated,
6188 * so the guest will not see stale values.
6189 */
8cfdc000 6190 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 6191 }
6192 return 0;
6193}
6194
6195static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6196 .notifier_call = kvmclock_cpufreq_notifier
6197};
6198
251a5fd6 6199static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6200{
251a5fd6
SAS		 6201 tsc_khz_changed(NULL);
6202 return 0;
8cfdc000
ZA		 6203}
6204
b820cc0c
ZA		 6205static void kvm_timer_init(void)
6206{
c285545f 6207 max_tsc_khz = tsc_khz;
460dd42e 6208
b820cc0c 6209 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6210#ifdef CONFIG_CPU_FREQ
6211 struct cpufreq_policy policy;
758f588d
BP		 6212 int cpu;
6213
c285545f 6214 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6215 cpu = get_cpu();
6216 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6217 if (policy.cpuinfo.max_freq)
6218 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6219 put_cpu();
c285545f 6220#endif
b820cc0c
ZA		 6221 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6222 CPUFREQ_TRANSITION_NOTIFIER);
6223 }
c285545f 6224 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6225
73c1b41e 6226 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6227 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6228}
6229
ff9d07a0
ZY		 6230static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6231
f5132b01 6232int kvm_is_in_guest(void)
ff9d07a0 6233{
086c9855 6234 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6235}
6236
6237static int kvm_is_user_mode(void)
6238{
6239 int user_mode = 3;
dcf46b94 6240
086c9855
AS		 6241 if (__this_cpu_read(current_vcpu))
6242 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6243
ff9d07a0
ZY		 6244 return user_mode != 0;
6245}
6246
6247static unsigned long kvm_get_guest_ip(void)
6248{
6249 unsigned long ip = 0;
dcf46b94 6250
086c9855
AS		 6251 if (__this_cpu_read(current_vcpu))
6252 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6253
ff9d07a0
ZY		 6254 return ip;
6255}
6256
6257static struct perf_guest_info_callbacks kvm_guest_cbs = {
6258 .is_in_guest = kvm_is_in_guest,
6259 .is_user_mode = kvm_is_user_mode,
6260 .get_guest_ip = kvm_get_guest_ip,
6261};
6262
6263void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
6264{
086c9855 6265 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 6266}
6267EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
6268
6269void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6270{
086c9855 6271 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 6272}
6273EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6274
ce88decf
XG		 6275static void kvm_set_mmio_spte_mask(void)
6276{
6277 u64 mask;
6278 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6279
6280 /*
6281 * Set the reserved bits and the present bit of an paging-structure
6282 * entry to generate page fault with PFER.RSV = 1.
6283 */
885032b9 6284 /* Mask the reserved physical address bits. */
d1431483 6285 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6286
885032b9 6287 /* Set the present bit. */
ce88decf
XG		 6288 mask |= 1ull;
6289
6290#ifdef CONFIG_X86_64
6291 /*
6292 * If reserved bit is not supported, clear the present bit to disable
6293 * mmio page fault.
6294 */
6295 if (maxphyaddr == 52)
6296 mask &= ~1ull;
6297#endif
6298
dcdca5fe 6299 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6300}
6301
16e8d74d
MT		 6302#ifdef CONFIG_X86_64
6303static void pvclock_gtod_update_fn(struct work_struct *work)
6304{
d828199e
MT		 6305 struct kvm *kvm;
6306
6307 struct kvm_vcpu *vcpu;
6308 int i;
6309
2f303b74 6310 spin_lock(&kvm_lock);
d828199e
MT		 6311 list_for_each_entry(kvm, &vm_list, vm_list)
6312 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6313 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6314 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6315 spin_unlock(&kvm_lock);
16e8d74d
MT		 6316}
6317
6318static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6319
6320/*
6321 * Notification about pvclock gtod data update.
6322 */
6323static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6324 void *priv)
6325{
6326 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6327 struct timekeeper *tk = priv;
6328
6329 update_pvclock_gtod(tk);
6330
6331 /* disable master clock if host does not trust, or does not
b0c39dc6 6332 * use, TSC based clocksource.
16e8d74d 6333 */
b0c39dc6 6334 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6335 atomic_read(&kvm_guest_has_master_clock) != 0)
6336 queue_work(system_long_wq, &pvclock_gtod_work);
6337
6338 return 0;
6339}
6340
6341static struct notifier_block pvclock_gtod_notifier = {
6342 .notifier_call = pvclock_gtod_notify,
6343};
6344#endif
6345
f8c16bba 6346int kvm_arch_init(void *opaque)
043405e1 6347{
b820cc0c 6348 int r;
6b61edf7 6349 struct kvm_x86_ops *ops = opaque;
f8c16bba 6350
f8c16bba
ZX		 6351 if (kvm_x86_ops) {
6352 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6353 r = -EEXIST;
6354 goto out;
f8c16bba
ZX		 6355 }
6356
6357 if (!ops->cpu_has_kvm_support()) {
6358 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6359 r = -EOPNOTSUPP;
6360 goto out;
f8c16bba
ZX		 6361 }
6362 if (ops->disabled_by_bios()) {
6363 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6364 r = -EOPNOTSUPP;
6365 goto out;
f8c16bba
ZX		 6366 }
6367
013f6a5d
MT		 6368 r = -ENOMEM;
6369 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6370 if (!shared_msrs) {
6371 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6372 goto out;
6373 }
6374
97db56ce
AK		 6375 r = kvm_mmu_module_init();
6376 if (r)
013f6a5d 6377 goto out_free_percpu;
97db56ce 6378
ce88decf 6379 kvm_set_mmio_spte_mask();
97db56ce 6380
f8c16bba 6381 kvm_x86_ops = ops;
920c8377 6382
7b52345e 6383 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6384 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6385 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6386 kvm_timer_init();
c8076604 6387
ff9d07a0
ZY		 6388 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6389
d366bf7e 6390 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6391 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6392
c5cc421b 6393 kvm_lapic_init();
16e8d74d
MT		 6394#ifdef CONFIG_X86_64
6395 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 6396
5fa4ec9c 6397 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 6398 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 6399#endif
6400
f8c16bba 6401 return 0;
56c6d28a 6402
013f6a5d
MT		 6403out_free_percpu:
6404 free_percpu(shared_msrs);
56c6d28a 6405out:
56c6d28a 6406 return r;
043405e1 6407}
8776e519 6408
f8c16bba
ZX		 6409void kvm_arch_exit(void)
6410{
0092e434 6411#ifdef CONFIG_X86_64
5fa4ec9c 6412 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 6413 clear_hv_tscchange_cb();
6414#endif
cef84c30 6415 kvm_lapic_exit();
ff9d07a0
ZY		 6416 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6417
888d256e
JK		 6418 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6419 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6420 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6421 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6422#ifdef CONFIG_X86_64
6423 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6424#endif
f8c16bba 6425 kvm_x86_ops = NULL;
56c6d28a 6426 kvm_mmu_module_exit();
013f6a5d 6427 free_percpu(shared_msrs);
56c6d28a 6428}
f8c16bba 6429
5cb56059 6430int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6431{
6432 ++vcpu->stat.halt_exits;
35754c98 6433 if (lapic_in_kernel(vcpu)) {
a4535290 6434 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6435 return 1;
6436 } else {
6437 vcpu->run->exit_reason = KVM_EXIT_HLT;
6438 return 0;
6439 }
6440}
5cb56059
JS		 6441EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6442
6443int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6444{
6affcbed
KH		 6445 int ret = kvm_skip_emulated_instruction(vcpu);
6446 /*
6447 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6448 * KVM_EXIT_DEBUG here.
6449 */
6450 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6451}
8776e519
HB		 6452EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6453
8ef81a9a 6454#ifdef CONFIG_X86_64
55dd00a7
MT		 6455static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6456 unsigned long clock_type)
6457{
6458 struct kvm_clock_pairing clock_pairing;
6459 struct timespec ts;
80fbd89c 6460 u64 cycle;
55dd00a7
MT		 6461 int ret;
6462
6463 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6464 return -KVM_EOPNOTSUPP;
6465
6466 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6467 return -KVM_EOPNOTSUPP;
6468
6469 clock_pairing.sec = ts.tv_sec;
6470 clock_pairing.nsec = ts.tv_nsec;
6471 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6472 clock_pairing.flags = 0;
6473
6474 ret = 0;
6475 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6476 sizeof(struct kvm_clock_pairing)))
6477 ret = -KVM_EFAULT;
6478
6479 return ret;
6480}
8ef81a9a 6481#endif
55dd00a7 6482
6aef266c
SV		 6483/*
6484 * kvm_pv_kick_cpu_op: Kick a vcpu.
6485 *
6486 * @apicid - apicid of vcpu to be kicked.
6487 */
6488static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6489{
24d2166b 6490 struct kvm_lapic_irq lapic_irq;
6aef266c 6491
24d2166b
R		 6492 lapic_irq.shorthand = 0;
6493 lapic_irq.dest_mode = 0;
ebd28fcb 6494 lapic_irq.level = 0;
24d2166b 6495 lapic_irq.dest_id = apicid;
93bbf0b8 6496 lapic_irq.msi_redir_hint = false;
6aef266c 6497
24d2166b 6498 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6499 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6500}
6501
d62caabb
AS		 6502void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6503{
6504 vcpu->arch.apicv_active = false;
6505 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6506}
6507
8776e519
HB		 6508int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6509{
6510 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6511 int op_64_bit, r;
8776e519 6512
6affcbed 6513 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6514
55cd8e5a
GN		 6515 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6516 return kvm_hv_hypercall(vcpu);
6517
5fdbf976
MT		 6518 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6519 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6520 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6521 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6522 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6523
229456fc 6524 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6525
a449c7aa
NA		 6526 op_64_bit = is_64_bit_mode(vcpu);
6527 if (!op_64_bit) {
8776e519
HB		 6528 nr &= 0xFFFFFFFF;
6529 a0 &= 0xFFFFFFFF;
6530 a1 &= 0xFFFFFFFF;
6531 a2 &= 0xFFFFFFFF;
6532 a3 &= 0xFFFFFFFF;
6533 }
6534
07708c4a
JK		 6535 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6536 ret = -KVM_EPERM;
6537 goto out;
6538 }
6539
8776e519 6540 switch (nr) {
b93463aa
AK		 6541 case KVM_HC_VAPIC_POLL_IRQ:
6542 ret = 0;
6543 break;
6aef266c
SV		 6544 case KVM_HC_KICK_CPU:
6545 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6546 ret = 0;
6547 break;
8ef81a9a 6548#ifdef CONFIG_X86_64
55dd00a7
MT		 6549 case KVM_HC_CLOCK_PAIRING:
6550 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6551 break;
8ef81a9a 6552#endif
8776e519
HB		 6553 default:
6554 ret = -KVM_ENOSYS;
6555 break;
6556 }
07708c4a 6557out:
a449c7aa
NA		 6558 if (!op_64_bit)
6559 ret = (u32)ret;
5fdbf976 6560 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6561 ++vcpu->stat.hypercalls;
2f333bcb 6562 return r;
8776e519
HB		 6563}
6564EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6565
b6785def 6566static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6567{
d6aa1000 6568 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6569 char instruction[3];
5fdbf976 6570 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6571
8776e519 6572 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6573
ce2e852e
DV		 6574 return emulator_write_emulated(ctxt, rip, instruction, 3,
6575 &ctxt->exception);
8776e519
HB		 6576}
6577
851ba692 6578static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6579{
782d422b
MG		 6580 return vcpu->run->request_interrupt_window &&
6581 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6582}
6583
851ba692 6584static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6585{
851ba692
AK		 6586 struct kvm_run *kvm_run = vcpu->run;
6587
91586a3b 6588 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6589 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6590 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6591 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6592 kvm_run->ready_for_interrupt_injection =
6593 pic_in_kernel(vcpu->kvm) ||
782d422b 6594 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6595}
6596
95ba8273
GN		 6597static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6598{
6599 int max_irr, tpr;
6600
6601 if (!kvm_x86_ops->update_cr8_intercept)
6602 return;
6603
bce87cce 6604 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6605 return;
6606
d62caabb
AS		 6607 if (vcpu->arch.apicv_active)
6608 return;
6609
8db3baa2
GN		 6610 if (!vcpu->arch.apic->vapic_addr)
6611 max_irr = kvm_lapic_find_highest_irr(vcpu);
6612 else
6613 max_irr = -1;
95ba8273
GN		 6614
6615 if (max_irr != -1)
6616 max_irr >>= 4;
6617
6618 tpr = kvm_lapic_get_cr8(vcpu);
6619
6620 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6621}
6622
b6b8a145 6623static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6624{
b6b8a145
JK		 6625 int r;
6626
95ba8273 6627 /* try to reinject previous events if any */
664f8e26
WL		 6628 if (vcpu->arch.exception.injected) {
6629 kvm_x86_ops->queue_exception(vcpu);
6630 return 0;
6631 }
6632
6633 /*
6634 * Exceptions must be injected immediately, or the exception
6635 * frame will have the address of the NMI or interrupt handler.
6636 */
6637 if (!vcpu->arch.exception.pending) {
6638 if (vcpu->arch.nmi_injected) {
6639 kvm_x86_ops->set_nmi(vcpu);
6640 return 0;
6641 }
6642
6643 if (vcpu->arch.interrupt.pending) {
6644 kvm_x86_ops->set_irq(vcpu);
6645 return 0;
6646 }
6647 }
6648
6649 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6650 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6651 if (r != 0)
6652 return r;
6653 }
6654
6655 /* try to inject new event if pending */
b59bb7bd 6656 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6657 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6658 vcpu->arch.exception.has_error_code,
6659 vcpu->arch.exception.error_code);
d6e8c854 6660
664f8e26
WL		 6661 vcpu->arch.exception.pending = false;
6662 vcpu->arch.exception.injected = true;
6663
d6e8c854
NA		 6664 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6665 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6666 X86_EFLAGS_RF);
6667
6bdf0662
NA		 6668 if (vcpu->arch.exception.nr == DB_VECTOR &&
6669 (vcpu->arch.dr7 & DR7_GD)) {
6670 vcpu->arch.dr7 &= ~DR7_GD;
6671 kvm_update_dr7(vcpu);
6672 }
6673
cfcd20e5 6674 kvm_x86_ops->queue_exception(vcpu);
72d7b374 6675 } else if (vcpu->arch.smi_pending && !is_smm(vcpu) && kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 6676 vcpu->arch.smi_pending = false;
52797bf9 6677 ++vcpu->arch.smi_count;
ee2cd4b7 6678 enter_smm(vcpu);
c43203ca 6679 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6680 --vcpu->arch.nmi_pending;
6681 vcpu->arch.nmi_injected = true;
6682 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6683 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6684 /*
6685 * Because interrupts can be injected asynchronously, we are
6686 * calling check_nested_events again here to avoid a race condition.
6687 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6688 * proposal and current concerns. Perhaps we should be setting
6689 * KVM_REQ_EVENT only on certain events and not unconditionally?
6690 */
6691 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6692 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6693 if (r != 0)
6694 return r;
6695 }
95ba8273 6696 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6697 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6698 false);
6699 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6700 }
6701 }
ee2cd4b7 6702
b6b8a145 6703 return 0;
95ba8273
GN		 6704}
6705
7460fb4a
AK		 6706static void process_nmi(struct kvm_vcpu *vcpu)
6707{
6708 unsigned limit = 2;
6709
6710 /*
6711 * x86 is limited to one NMI running, and one NMI pending after it.
6712 * If an NMI is already in progress, limit further NMIs to just one.
6713 * Otherwise, allow two (and we'll inject the first one immediately).
6714 */
6715 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6716 limit = 1;
6717
6718 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6719 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6720 kvm_make_request(KVM_REQ_EVENT, vcpu);
6721}
6722
ee2cd4b7 6723static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6724{
6725 u32 flags = 0;
6726 flags |= seg->g << 23;
6727 flags |= seg->db << 22;
6728 flags |= seg->l << 21;
6729 flags |= seg->avl << 20;
6730 flags |= seg->present << 15;
6731 flags |= seg->dpl << 13;
6732 flags |= seg->s << 12;
6733 flags |= seg->type << 8;
6734 return flags;
6735}
6736
ee2cd4b7 6737static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6738{
6739 struct kvm_segment seg;
6740 int offset;
6741
6742 kvm_get_segment(vcpu, &seg, n);
6743 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6744
6745 if (n < 3)
6746 offset = 0x7f84 + n * 12;
6747 else
6748 offset = 0x7f2c + (n - 3) * 12;
6749
6750 put_smstate(u32, buf, offset + 8, seg.base);
6751 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6752 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6753}
6754
efbb288a 6755#ifdef CONFIG_X86_64
ee2cd4b7 6756static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6757{
6758 struct kvm_segment seg;
6759 int offset;
6760 u16 flags;
6761
6762 kvm_get_segment(vcpu, &seg, n);
6763 offset = 0x7e00 + n * 16;
6764
ee2cd4b7 6765 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6766 put_smstate(u16, buf, offset, seg.selector);
6767 put_smstate(u16, buf, offset + 2, flags);
6768 put_smstate(u32, buf, offset + 4, seg.limit);
6769 put_smstate(u64, buf, offset + 8, seg.base);
6770}
efbb288a 6771#endif
660a5d51 6772
ee2cd4b7 6773static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6774{
6775 struct desc_ptr dt;
6776 struct kvm_segment seg;
6777 unsigned long val;
6778 int i;
6779
6780 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6781 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6782 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6783 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6784
6785 for (i = 0; i < 8; i++)
6786 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6787
6788 kvm_get_dr(vcpu, 6, &val);
6789 put_smstate(u32, buf, 0x7fcc, (u32)val);
6790 kvm_get_dr(vcpu, 7, &val);
6791 put_smstate(u32, buf, 0x7fc8, (u32)val);
6792
6793 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6794 put_smstate(u32, buf, 0x7fc4, seg.selector);
6795 put_smstate(u32, buf, 0x7f64, seg.base);
6796 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6797 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6798
6799 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6800 put_smstate(u32, buf, 0x7fc0, seg.selector);
6801 put_smstate(u32, buf, 0x7f80, seg.base);
6802 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6803 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6804
6805 kvm_x86_ops->get_gdt(vcpu, &dt);
6806 put_smstate(u32, buf, 0x7f74, dt.address);
6807 put_smstate(u32, buf, 0x7f70, dt.size);
6808
6809 kvm_x86_ops->get_idt(vcpu, &dt);
6810 put_smstate(u32, buf, 0x7f58, dt.address);
6811 put_smstate(u32, buf, 0x7f54, dt.size);
6812
6813 for (i = 0; i < 6; i++)
ee2cd4b7 6814 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6815
6816 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6817
6818 /* revision id */
6819 put_smstate(u32, buf, 0x7efc, 0x00020000);
6820 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6821}
6822
ee2cd4b7 6823static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6824{
6825#ifdef CONFIG_X86_64
6826 struct desc_ptr dt;
6827 struct kvm_segment seg;
6828 unsigned long val;
6829 int i;
6830
6831 for (i = 0; i < 16; i++)
6832 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6833
6834 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6835 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6836
6837 kvm_get_dr(vcpu, 6, &val);
6838 put_smstate(u64, buf, 0x7f68, val);
6839 kvm_get_dr(vcpu, 7, &val);
6840 put_smstate(u64, buf, 0x7f60, val);
6841
6842 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6843 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6844 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6845
6846 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6847
6848 /* revision id */
6849 put_smstate(u32, buf, 0x7efc, 0x00020064);
6850
6851 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6852
6853 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6854 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6855 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6856 put_smstate(u32, buf, 0x7e94, seg.limit);
6857 put_smstate(u64, buf, 0x7e98, seg.base);
6858
6859 kvm_x86_ops->get_idt(vcpu, &dt);
6860 put_smstate(u32, buf, 0x7e84, dt.size);
6861 put_smstate(u64, buf, 0x7e88, dt.address);
6862
6863 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6864 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6865 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6866 put_smstate(u32, buf, 0x7e74, seg.limit);
6867 put_smstate(u64, buf, 0x7e78, seg.base);
6868
6869 kvm_x86_ops->get_gdt(vcpu, &dt);
6870 put_smstate(u32, buf, 0x7e64, dt.size);
6871 put_smstate(u64, buf, 0x7e68, dt.address);
6872
6873 for (i = 0; i < 6; i++)
ee2cd4b7 6874 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6875#else
6876 WARN_ON_ONCE(1);
6877#endif
6878}
6879
ee2cd4b7 6880static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6881{
660a5d51 6882 struct kvm_segment cs, ds;
18c3626e 6883 struct desc_ptr dt;
660a5d51
PB		 6884 char buf[512];
6885 u32 cr0;
6886
660a5d51 6887 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 6888 memset(buf, 0, 512);
d6321d49 6889 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 6890 enter_smm_save_state_64(vcpu, buf);
660a5d51 6891 else
ee2cd4b7 6892 enter_smm_save_state_32(vcpu, buf);
660a5d51 6893
0234bf88
LP		 6894 /*
6895 * Give pre_enter_smm() a chance to make ISA-specific changes to the
6896 * vCPU state (e.g. leave guest mode) after we've saved the state into
6897 * the SMM state-save area.
6898 */
6899 kvm_x86_ops->pre_enter_smm(vcpu, buf);
6900
6901 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 6902 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6903
6904 if (kvm_x86_ops->get_nmi_mask(vcpu))
6905 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6906 else
6907 kvm_x86_ops->set_nmi_mask(vcpu, true);
6908
6909 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6910 kvm_rip_write(vcpu, 0x8000);
6911
6912 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6913 kvm_x86_ops->set_cr0(vcpu, cr0);
6914 vcpu->arch.cr0 = cr0;
6915
6916 kvm_x86_ops->set_cr4(vcpu, 0);
6917
18c3626e
PB		 6918 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6919 dt.address = dt.size = 0;
6920 kvm_x86_ops->set_idt(vcpu, &dt);
6921
660a5d51
PB		 6922 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6923
6924 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6925 cs.base = vcpu->arch.smbase;
6926
6927 ds.selector = 0;
6928 ds.base = 0;
6929
6930 cs.limit = ds.limit = 0xffffffff;
6931 cs.type = ds.type = 0x3;
6932 cs.dpl = ds.dpl = 0;
6933 cs.db = ds.db = 0;
6934 cs.s = ds.s = 1;
6935 cs.l = ds.l = 0;
6936 cs.g = ds.g = 1;
6937 cs.avl = ds.avl = 0;
6938 cs.present = ds.present = 1;
6939 cs.unusable = ds.unusable = 0;
6940 cs.padding = ds.padding = 0;
6941
6942 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6943 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6944 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6945 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6946 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6947 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6948
d6321d49 6949 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 6950 kvm_x86_ops->set_efer(vcpu, 0);
6951
6952 kvm_update_cpuid(vcpu);
6953 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6954}
6955
ee2cd4b7 6956static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6957{
6958 vcpu->arch.smi_pending = true;
6959 kvm_make_request(KVM_REQ_EVENT, vcpu);
6960}
6961
2860c4b1
PB		 6962void kvm_make_scan_ioapic_request(struct kvm *kvm)
6963{
6964 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6965}
6966
3d81bc7e 6967static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6968{
5c919412
AS		 6969 u64 eoi_exit_bitmap[4];
6970
3d81bc7e
YZ		 6971 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6972 return;
c7c9c56c 6973
6308630b 6974 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6975
b053b2ae 6976 if (irqchip_split(vcpu->kvm))
6308630b 6977 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6978 else {
fa59cc00 6979 if (vcpu->arch.apicv_active)
d62caabb 6980 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6981 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6982 }
5c919412
AS		 6983 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6984 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6985 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6986}
6987
b1394e74
RK		 6988void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
6989 unsigned long start, unsigned long end)
6990{
6991 unsigned long apic_address;
6992
6993 /*
6994 * The physical address of apic access page is stored in the VMCS.
6995 * Update it when it becomes invalid.
6996 */
6997 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6998 if (start <= apic_address && apic_address < end)
6999 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
7000}
7001
4256f43f
TC		 7002void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7003{
c24ae0dc
TC		 7004 struct page *page = NULL;
7005
35754c98 7006 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7007 return;
7008
4256f43f
TC		 7009 if (!kvm_x86_ops->set_apic_access_page_addr)
7010 return;
7011
c24ae0dc 7012 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7013 if (is_error_page(page))
7014 return;
c24ae0dc
TC		 7015 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7016
7017 /*
7018 * Do not pin apic access page in memory, the MMU notifier
7019 * will call us again if it is migrated or swapped out.
7020 */
7021 put_page(page);
4256f43f
TC		 7022}
7023EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7024
9357d939 7025/*
362c698f 7026 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7027 * exiting to the userspace. Otherwise, the value will be returned to the
7028 * userspace.
7029 */
851ba692 7030static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7031{
7032 int r;
62a193ed
MG		 7033 bool req_int_win =
7034 dm_request_for_irq_injection(vcpu) &&
7035 kvm_cpu_accept_dm_intr(vcpu);
7036
730dca42 7037 bool req_immediate_exit = false;
b6c7a5dc 7038
2fa6e1e1 7039 if (kvm_request_pending(vcpu)) {
a8eeb04a 7040 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7041 kvm_mmu_unload(vcpu);
a8eeb04a 7042 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7043 __kvm_migrate_timers(vcpu);
d828199e
MT		 7044 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7045 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7046 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7047 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7048 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7049 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7050 if (unlikely(r))
7051 goto out;
7052 }
a8eeb04a 7053 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7054 kvm_mmu_sync_roots(vcpu);
a8eeb04a 7055 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7056 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7057 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7058 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7059 r = 0;
7060 goto out;
7061 }
a8eeb04a 7062 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7063 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7064 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7065 r = 0;
7066 goto out;
7067 }
af585b92
GN		 7068 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7069 /* Page is swapped out. Do synthetic halt */
7070 vcpu->arch.apf.halted = true;
7071 r = 1;
7072 goto out;
7073 }
c9aaa895
GC		 7074 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7075 record_steal_time(vcpu);
64d60670
PB		 7076 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7077 process_smi(vcpu);
7460fb4a
AK		 7078 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7079 process_nmi(vcpu);
f5132b01 7080 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7081 kvm_pmu_handle_event(vcpu);
f5132b01 7082 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7083 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7084 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7085 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7086 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7087 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7088 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7089 vcpu->run->eoi.vector =
7090 vcpu->arch.pending_ioapic_eoi;
7091 r = 0;
7092 goto out;
7093 }
7094 }
3d81bc7e
YZ		 7095 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7096 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 7097 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7098 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7099 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7100 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7101 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7102 r = 0;
7103 goto out;
7104 }
e516cebb
AS		 7105 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7106 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7107 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7108 r = 0;
7109 goto out;
7110 }
db397571
AS		 7111 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7112 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7113 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7114 r = 0;
7115 goto out;
7116 }
f3b138c5
AS		 7117
7118 /*
7119 * KVM_REQ_HV_STIMER has to be processed after
7120 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7121 * depend on the guest clock being up-to-date
7122 */
1f4b34f8
AS		 7123 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7124 kvm_hv_process_stimers(vcpu);
2f52d58c 7125 }
b93463aa 7126
b463a6f7 7127 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7128 ++vcpu->stat.req_event;
66450a21
JK		 7129 kvm_apic_accept_events(vcpu);
7130 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7131 r = 1;
7132 goto out;
7133 }
7134
b6b8a145
JK		 7135 if (inject_pending_event(vcpu, req_int_win) != 0)
7136 req_immediate_exit = true;
321c5658 7137 else {
cc3d967f 7138 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7139 *
cc3d967f
LP		 7140 * SMIs have three cases:
7141 * 1) They can be nested, and then there is nothing to
7142 * do here because RSM will cause a vmexit anyway.
7143 * 2) There is an ISA-specific reason why SMI cannot be
7144 * injected, and the moment when this changes can be
7145 * intercepted.
7146 * 3) Or the SMI can be pending because
7147 * inject_pending_event has completed the injection
7148 * of an IRQ or NMI from the previous vmexit, and
7149 * then we request an immediate exit to inject the
7150 * SMI.
c43203ca
PB		 7151 */
7152 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7153 if (!kvm_x86_ops->enable_smi_window(vcpu))
7154 req_immediate_exit = true;
321c5658
YS		 7155 if (vcpu->arch.nmi_pending)
7156 kvm_x86_ops->enable_nmi_window(vcpu);
7157 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7158 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7159 WARN_ON(vcpu->arch.exception.pending);
321c5658 7160 }
b463a6f7
AK		 7161
7162 if (kvm_lapic_enabled(vcpu)) {
7163 update_cr8_intercept(vcpu);
7164 kvm_lapic_sync_to_vapic(vcpu);
7165 }
7166 }
7167
d8368af8
AK		 7168 r = kvm_mmu_reload(vcpu);
7169 if (unlikely(r)) {
d905c069 7170 goto cancel_injection;
d8368af8
AK		 7171 }
7172
b6c7a5dc
HB		 7173 preempt_disable();
7174
7175 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7176
7177 /*
7178 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7179 * IPI are then delayed after guest entry, which ensures that they
7180 * result in virtual interrupt delivery.
7181 */
7182 local_irq_disable();
6b7e2d09
XG		 7183 vcpu->mode = IN_GUEST_MODE;
7184
01b71917
MT		 7185 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7186
0f127d12 7187 /*
b95234c8 7188 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7189 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 7190 *
7191 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7192 * pairs with the memory barrier implicit in pi_test_and_set_on
7193 * (see vmx_deliver_posted_interrupt).
7194 *
7195 * 3) This also orders the write to mode from any reads to the page
7196 * tables done while the VCPU is running. Please see the comment
7197 * in kvm_flush_remote_tlbs.
6b7e2d09 7198 */
01b71917 7199 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7200
b95234c8
PB		 7201 /*
7202 * This handles the case where a posted interrupt was
7203 * notified with kvm_vcpu_kick.
7204 */
fa59cc00
LA		 7205 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7206 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7207
2fa6e1e1 7208 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7209 || need_resched() || signal_pending(current)) {
6b7e2d09 7210 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7211 smp_wmb();
6c142801
AK		 7212 local_irq_enable();
7213 preempt_enable();
01b71917 7214 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7215 r = 1;
d905c069 7216 goto cancel_injection;
6c142801
AK		 7217 }
7218
fc5b7f3b
DM		 7219 kvm_load_guest_xcr0(vcpu);
7220
c43203ca
PB		 7221 if (req_immediate_exit) {
7222 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 7223 smp_send_reschedule(vcpu->cpu);
c43203ca 7224 }
d6185f20 7225
8b89fe1f 7226 trace_kvm_entry(vcpu->vcpu_id);
9c48d517
WL		 7227 if (lapic_timer_advance_ns)
7228 wait_lapic_expire(vcpu);
6edaa530 7229 guest_enter_irqoff();
b6c7a5dc 7230
42dbaa5a 7231 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7232 set_debugreg(0, 7);
7233 set_debugreg(vcpu->arch.eff_db[0], 0);
7234 set_debugreg(vcpu->arch.eff_db[1], 1);
7235 set_debugreg(vcpu->arch.eff_db[2], 2);
7236 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7237 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7238 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7239 }
b6c7a5dc 7240
851ba692 7241 kvm_x86_ops->run(vcpu);
b6c7a5dc 7242
c77fb5fe
PB		 7243 /*
7244 * Do this here before restoring debug registers on the host. And
7245 * since we do this before handling the vmexit, a DR access vmexit
7246 * can (a) read the correct value of the debug registers, (b) set
7247 * KVM_DEBUGREG_WONT_EXIT again.
7248 */
7249 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7250 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7251 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7252 kvm_update_dr0123(vcpu);
7253 kvm_update_dr6(vcpu);
7254 kvm_update_dr7(vcpu);
7255 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7256 }
7257
24f1e32c
FW		 7258 /*
7259 * If the guest has used debug registers, at least dr7
7260 * will be disabled while returning to the host.
7261 * If we don't have active breakpoints in the host, we don't
7262 * care about the messed up debug address registers. But if
7263 * we have some of them active, restore the old state.
7264 */
59d8eb53 7265 if (hw_breakpoint_active())
24f1e32c 7266 hw_breakpoint_restore();
42dbaa5a 7267
4ba76538 7268 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7269
6b7e2d09 7270 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7271 smp_wmb();
a547c6db 7272
fc5b7f3b
DM		 7273 kvm_put_guest_xcr0(vcpu);
7274
a547c6db 7275 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 7276
7277 ++vcpu->stat.exits;
7278
f2485b3e 7279 guest_exit_irqoff();
b6c7a5dc 7280
f2485b3e 7281 local_irq_enable();
b6c7a5dc
HB		 7282 preempt_enable();
7283
f656ce01 7284 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7285
b6c7a5dc
HB		 7286 /*
7287 * Profile KVM exit RIPs:
7288 */
7289 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7290 unsigned long rip = kvm_rip_read(vcpu);
7291 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7292 }
7293
cc578287
ZA		 7294 if (unlikely(vcpu->arch.tsc_always_catchup))
7295 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7296
5cfb1d5a
MT		 7297 if (vcpu->arch.apic_attention)
7298 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7299
618232e2 7300 vcpu->arch.gpa_available = false;
851ba692 7301 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7302 return r;
7303
7304cancel_injection:
7305 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7306 if (unlikely(vcpu->arch.apic_attention))
7307 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7308out:
7309 return r;
7310}
b6c7a5dc 7311
362c698f
PB		 7312static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7313{
bf9f6ac8
FW		 7314 if (!kvm_arch_vcpu_runnable(vcpu) &&
7315 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7316 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7317 kvm_vcpu_block(vcpu);
7318 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7319
7320 if (kvm_x86_ops->post_block)
7321 kvm_x86_ops->post_block(vcpu);
7322
9c8fd1ba
PB		 7323 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7324 return 1;
7325 }
362c698f
PB		 7326
7327 kvm_apic_accept_events(vcpu);
7328 switch(vcpu->arch.mp_state) {
7329 case KVM_MP_STATE_HALTED:
7330 vcpu->arch.pv.pv_unhalted = false;
7331 vcpu->arch.mp_state =
7332 KVM_MP_STATE_RUNNABLE;
7333 case KVM_MP_STATE_RUNNABLE:
7334 vcpu->arch.apf.halted = false;
7335 break;
7336 case KVM_MP_STATE_INIT_RECEIVED:
7337 break;
7338 default:
7339 return -EINTR;
7340 break;
7341 }
7342 return 1;
7343}
09cec754 7344
5d9bc648
PB		 7345static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7346{
0ad3bed6
PB		 7347 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7348 kvm_x86_ops->check_nested_events(vcpu, false);
7349
5d9bc648
PB		 7350 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7351 !vcpu->arch.apf.halted);
7352}
7353
362c698f 7354static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7355{
7356 int r;
f656ce01 7357 struct kvm *kvm = vcpu->kvm;
d7690175 7358
f656ce01 7359 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7360
362c698f 7361 for (;;) {
58f800d5 7362 if (kvm_vcpu_running(vcpu)) {
851ba692 7363 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7364 } else {
362c698f 7365 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7366 }
7367
09cec754
GN		 7368 if (r <= 0)
7369 break;
7370
72875d8a 7371 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7372 if (kvm_cpu_has_pending_timer(vcpu))
7373 kvm_inject_pending_timer_irqs(vcpu);
7374
782d422b
MG		 7375 if (dm_request_for_irq_injection(vcpu) &&
7376 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7377 r = 0;
7378 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7379 ++vcpu->stat.request_irq_exits;
362c698f 7380 break;
09cec754 7381 }
af585b92
GN		 7382
7383 kvm_check_async_pf_completion(vcpu);
7384
09cec754
GN		 7385 if (signal_pending(current)) {
7386 r = -EINTR;
851ba692 7387 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7388 ++vcpu->stat.signal_exits;
362c698f 7389 break;
09cec754
GN		 7390 }
7391 if (need_resched()) {
f656ce01 7392 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7393 cond_resched();
f656ce01 7394 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7395 }
b6c7a5dc
HB		 7396 }
7397
f656ce01 7398 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7399
7400 return r;
7401}
7402
716d51ab
GN		 7403static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7404{
7405 int r;
7406 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7407 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7408 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7409 if (r != EMULATE_DONE)
7410 return 0;
7411 return 1;
7412}
7413
7414static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7415{
7416 BUG_ON(!vcpu->arch.pio.count);
7417
7418 return complete_emulated_io(vcpu);
7419}
7420
f78146b0
AK		 7421/*
7422 * Implements the following, as a state machine:
7423 *
7424 * read:
7425 * for each fragment
87da7e66
XG		 7426 * for each mmio piece in the fragment
7427 * write gpa, len
7428 * exit
7429 * copy data
f78146b0
AK		 7430 * execute insn
7431 *
7432 * write:
7433 * for each fragment
87da7e66
XG		 7434 * for each mmio piece in the fragment
7435 * write gpa, len
7436 * copy data
7437 * exit
f78146b0 7438 */
716d51ab 7439static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7440{
7441 struct kvm_run *run = vcpu->run;
f78146b0 7442 struct kvm_mmio_fragment *frag;
87da7e66 7443 unsigned len;
5287f194 7444
716d51ab 7445 BUG_ON(!vcpu->mmio_needed);
5287f194 7446
716d51ab 7447 /* Complete previous fragment */
87da7e66
XG		 7448 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7449 len = min(8u, frag->len);
716d51ab 7450 if (!vcpu->mmio_is_write)
87da7e66
XG		 7451 memcpy(frag->data, run->mmio.data, len);
7452
7453 if (frag->len <= 8) {
7454 /* Switch to the next fragment. */
7455 frag++;
7456 vcpu->mmio_cur_fragment++;
7457 } else {
7458 /* Go forward to the next mmio piece. */
7459 frag->data += len;
7460 frag->gpa += len;
7461 frag->len -= len;
7462 }
7463
a08d3b3b 7464 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7465 vcpu->mmio_needed = 0;
0912c977
PB		 7466
7467 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7468 if (vcpu->mmio_is_write)
716d51ab
GN		 7469 return 1;
7470 vcpu->mmio_read_completed = 1;
7471 return complete_emulated_io(vcpu);
7472 }
87da7e66 7473
716d51ab
GN		 7474 run->exit_reason = KVM_EXIT_MMIO;
7475 run->mmio.phys_addr = frag->gpa;
7476 if (vcpu->mmio_is_write)
87da7e66
XG		 7477 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7478 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7479 run->mmio.is_write = vcpu->mmio_is_write;
7480 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7481 return 0;
5287f194
AK		 7482}
7483
716d51ab 7484
b6c7a5dc
HB		 7485int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7486{
7487 int r;
b6c7a5dc 7488
accb757d 7489 vcpu_load(vcpu);
20b7035c 7490 kvm_sigset_activate(vcpu);
5663d8f9
PX		 7491 kvm_load_guest_fpu(vcpu);
7492
a4535290 7493 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7494 if (kvm_run->immediate_exit) {
7495 r = -EINTR;
7496 goto out;
7497 }
b6c7a5dc 7498 kvm_vcpu_block(vcpu);
66450a21 7499 kvm_apic_accept_events(vcpu);
72875d8a 7500 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7501 r = -EAGAIN;
a0595000
JS		 7502 if (signal_pending(current)) {
7503 r = -EINTR;
7504 vcpu->run->exit_reason = KVM_EXIT_INTR;
7505 ++vcpu->stat.signal_exits;
7506 }
ac9f6dc0 7507 goto out;
b6c7a5dc
HB		 7508 }
7509
b6c7a5dc 7510 /* re-sync apic's tpr */
35754c98 7511 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7512 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7513 r = -EINVAL;
7514 goto out;
7515 }
7516 }
b6c7a5dc 7517
716d51ab
GN		 7518 if (unlikely(vcpu->arch.complete_userspace_io)) {
7519 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7520 vcpu->arch.complete_userspace_io = NULL;
7521 r = cui(vcpu);
7522 if (r <= 0)
5663d8f9 7523 goto out;
716d51ab
GN		 7524 } else
7525 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7526
460df4c1
PB		 7527 if (kvm_run->immediate_exit)
7528 r = -EINTR;
7529 else
7530 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7531
7532out:
5663d8f9 7533 kvm_put_guest_fpu(vcpu);
f1d86e46 7534 post_kvm_run_save(vcpu);
20b7035c 7535 kvm_sigset_deactivate(vcpu);
b6c7a5dc 7536
accb757d 7537 vcpu_put(vcpu);
b6c7a5dc
HB		 7538 return r;
7539}
7540
7541int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7542{
1fc9b76b
CD		 7543 vcpu_load(vcpu);
7544
7ae441ea
GN		 7545 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7546 /*
7547 * We are here if userspace calls get_regs() in the middle of
7548 * instruction emulation. Registers state needs to be copied
4a969980 7549 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7550 * that usually, but some bad designed PV devices (vmware
7551 * backdoor interface) need this to work
7552 */
dd856efa 7553 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7554 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7555 }
5fdbf976
MT		 7556 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7557 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7558 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7559 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7560 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7561 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7562 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7563 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7564#ifdef CONFIG_X86_64
5fdbf976
MT		 7565 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7566 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7567 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7568 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7569 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7570 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7571 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7572 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7573#endif
7574
5fdbf976 7575 regs->rip = kvm_rip_read(vcpu);
91586a3b 7576 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7577
1fc9b76b 7578 vcpu_put(vcpu);
b6c7a5dc
HB		 7579 return 0;
7580}
7581
7582int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7583{
875656fe
CD		 7584 vcpu_load(vcpu);
7585
7ae441ea
GN		 7586 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7587 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7588
5fdbf976
MT		 7589 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7590 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7591 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7592 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7593 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7594 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7595 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7596 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7597#ifdef CONFIG_X86_64
5fdbf976
MT		 7598 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7599 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7600 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7601 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7602 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7603 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7604 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7605 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7606#endif
7607
5fdbf976 7608 kvm_rip_write(vcpu, regs->rip);
d73235d1 7609 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 7610
b4f14abd
JK		 7611 vcpu->arch.exception.pending = false;
7612
3842d135
AK		 7613 kvm_make_request(KVM_REQ_EVENT, vcpu);
7614
875656fe 7615 vcpu_put(vcpu);
b6c7a5dc
HB		 7616 return 0;
7617}
7618
b6c7a5dc
HB		 7619void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7620{
7621 struct kvm_segment cs;
7622
3e6e0aab 7623 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7624 *db = cs.db;
7625 *l = cs.l;
7626}
7627EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7628
7629int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7630 struct kvm_sregs *sregs)
7631{
89a27f4d 7632 struct desc_ptr dt;
b6c7a5dc 7633
bcdec41c
CD		 7634 vcpu_load(vcpu);
7635
3e6e0aab
GT		 7636 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7637 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7638 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7639 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7640 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7641 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7642
3e6e0aab
GT		 7643 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7644 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7645
7646 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7647 sregs->idt.limit = dt.size;
7648 sregs->idt.base = dt.address;
b6c7a5dc 7649 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7650 sregs->gdt.limit = dt.size;
7651 sregs->gdt.base = dt.address;
b6c7a5dc 7652
4d4ec087 7653 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7654 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7655 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7656 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7657 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7658 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7659 sregs->apic_base = kvm_get_apic_base(vcpu);
7660
923c61bb 7661 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7662
36752c9b 7663 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7664 set_bit(vcpu->arch.interrupt.nr,
7665 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7666
bcdec41c 7667 vcpu_put(vcpu);
b6c7a5dc
HB		 7668 return 0;
7669}
7670
62d9f0db
MT		 7671int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7672 struct kvm_mp_state *mp_state)
7673{
fd232561
CD		 7674 vcpu_load(vcpu);
7675
66450a21 7676 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7677 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7678 vcpu->arch.pv.pv_unhalted)
7679 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7680 else
7681 mp_state->mp_state = vcpu->arch.mp_state;
7682
fd232561 7683 vcpu_put(vcpu);
62d9f0db
MT		 7684 return 0;
7685}
7686
7687int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7688 struct kvm_mp_state *mp_state)
7689{
e83dff5e
CD		 7690 int ret = -EINVAL;
7691
7692 vcpu_load(vcpu);
7693
bce87cce 7694 if (!lapic_in_kernel(vcpu) &&
66450a21 7695 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 7696 goto out;
66450a21 7697
28bf2888
DH		 7698 /* INITs are latched while in SMM */
7699 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7700 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7701 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 7702 goto out;
28bf2888 7703
66450a21
JK		 7704 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7705 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7706 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7707 } else
7708 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7709 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 7710
7711 ret = 0;
7712out:
7713 vcpu_put(vcpu);
7714 return ret;
62d9f0db
MT		 7715}
7716
7f3d35fd
KW		 7717int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7718 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7719{
9d74191a 7720 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7721 int ret;
e01c2426 7722
8ec4722d 7723 init_emulate_ctxt(vcpu);
c697518a 7724
7f3d35fd 7725 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7726 has_error_code, error_code);
c697518a 7727
c697518a 7728 if (ret)
19d04437 7729 return EMULATE_FAIL;
37817f29 7730
9d74191a
TY		 7731 kvm_rip_write(vcpu, ctxt->eip);
7732 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7733 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7734 return EMULATE_DONE;
37817f29
IE		 7735}
7736EXPORT_SYMBOL_GPL(kvm_task_switch);
7737
f2981033
LT		 7738int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
7739{
37b95951 7740 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 7741 /*
7742 * When EFER.LME and CR0.PG are set, the processor is in
7743 * 64-bit mode (though maybe in a 32-bit code segment).
7744 * CR4.PAE and EFER.LMA must be set.
7745 */
37b95951 7746 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 7747 || !(sregs->efer & EFER_LMA))
7748 return -EINVAL;
7749 } else {
7750 /*
7751 * Not in 64-bit mode: EFER.LMA is clear and the code
7752 * segment cannot be 64-bit.
7753 */
7754 if (sregs->efer & EFER_LMA || sregs->cs.l)
7755 return -EINVAL;
7756 }
7757
7758 return 0;
7759}
7760
b6c7a5dc
HB		 7761int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7762 struct kvm_sregs *sregs)
7763{
58cb628d 7764 struct msr_data apic_base_msr;
b6c7a5dc 7765 int mmu_reset_needed = 0;
63f42e02 7766 int pending_vec, max_bits, idx;
89a27f4d 7767 struct desc_ptr dt;
b4ef9d4e
CD		 7768 int ret = -EINVAL;
7769
7770 vcpu_load(vcpu);
b6c7a5dc 7771
d6321d49
RK		 7772 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7773 (sregs->cr4 & X86_CR4_OSXSAVE))
b4ef9d4e 7774 goto out;
6d1068b3 7775
f2981033 7776 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 7777 goto out;
f2981033 7778
d3802286
JM		 7779 apic_base_msr.data = sregs->apic_base;
7780 apic_base_msr.host_initiated = true;
7781 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 7782 goto out;
6d1068b3 7783
89a27f4d
GN		 7784 dt.size = sregs->idt.limit;
7785 dt.address = sregs->idt.base;
b6c7a5dc 7786 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7787 dt.size = sregs->gdt.limit;
7788 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7789 kvm_x86_ops->set_gdt(vcpu, &dt);
7790
ad312c7c 7791 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7792 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7793 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7794 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7795
2d3ad1f4 7796 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7797
f6801dff 7798 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7799 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 7800
4d4ec087 7801 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7802 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7803 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7804
fc78f519 7805 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7806 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7807 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7808 kvm_update_cpuid(vcpu);
63f42e02
XG		 7809
7810 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7811 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7812 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7813 mmu_reset_needed = 1;
7814 }
63f42e02 7815 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7816
7817 if (mmu_reset_needed)
7818 kvm_mmu_reset_context(vcpu);
7819
a50abc3b 7820 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7821 pending_vec = find_first_bit(
7822 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7823 if (pending_vec < max_bits) {
66fd3f7f 7824 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7825 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7826 }
7827
3e6e0aab
GT		 7828 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7829 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7830 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7831 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7832 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7833 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7834
3e6e0aab
GT		 7835 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7836 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7837
5f0269f5
ME		 7838 update_cr8_intercept(vcpu);
7839
9c3e4aab 7840 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7841 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7842 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7843 !is_protmode(vcpu))
9c3e4aab
MT		 7844 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7845
3842d135
AK		 7846 kvm_make_request(KVM_REQ_EVENT, vcpu);
7847
b4ef9d4e
CD		 7848 ret = 0;
7849out:
7850 vcpu_put(vcpu);
7851 return ret;
b6c7a5dc
HB		 7852}
7853
d0bfb940
JK		 7854int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7855 struct kvm_guest_debug *dbg)
b6c7a5dc 7856{
355be0b9 7857 unsigned long rflags;
ae675ef0 7858 int i, r;
b6c7a5dc 7859
66b56562
CD		 7860 vcpu_load(vcpu);
7861
4f926bf2
JK		 7862 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7863 r = -EBUSY;
7864 if (vcpu->arch.exception.pending)
2122ff5e 7865 goto out;
4f926bf2
JK		 7866 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7867 kvm_queue_exception(vcpu, DB_VECTOR);
7868 else
7869 kvm_queue_exception(vcpu, BP_VECTOR);
7870 }
7871
91586a3b
JK		 7872 /*
7873 * Read rflags as long as potentially injected trace flags are still
7874 * filtered out.
7875 */
7876 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7877
7878 vcpu->guest_debug = dbg->control;
7879 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7880 vcpu->guest_debug = 0;
7881
7882 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7883 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7884 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7885 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7886 } else {
7887 for (i = 0; i < KVM_NR_DB_REGS; i++)
7888 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7889 }
c8639010 7890 kvm_update_dr7(vcpu);
ae675ef0 7891
f92653ee
JK		 7892 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7893 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7894 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7895
91586a3b
JK		 7896 /*
7897 * Trigger an rflags update that will inject or remove the trace
7898 * flags.
7899 */
7900 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7901
a96036b8 7902 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7903
4f926bf2 7904 r = 0;
d0bfb940 7905
2122ff5e 7906out:
66b56562 7907 vcpu_put(vcpu);
b6c7a5dc
HB		 7908 return r;
7909}
7910
8b006791
ZX		 7911/*
7912 * Translate a guest virtual address to a guest physical address.
7913 */
7914int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7915 struct kvm_translation *tr)
7916{
7917 unsigned long vaddr = tr->linear_address;
7918 gpa_t gpa;
f656ce01 7919 int idx;
8b006791 7920
1da5b61d
CD		 7921 vcpu_load(vcpu);
7922
f656ce01 7923 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7924 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7925 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7926 tr->physical_address = gpa;
7927 tr->valid = gpa != UNMAPPED_GVA;
7928 tr->writeable = 1;
7929 tr->usermode = 0;
8b006791 7930
1da5b61d 7931 vcpu_put(vcpu);
8b006791
ZX		 7932 return 0;
7933}
7934
d0752060
HB		 7935int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7936{
1393123e 7937 struct fxregs_state *fxsave;
d0752060 7938
1393123e 7939 vcpu_load(vcpu);
d0752060 7940
1393123e 7941 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060
HB		 7942 memcpy(fpu->fpr, fxsave->st_space, 128);
7943 fpu->fcw = fxsave->cwd;
7944 fpu->fsw = fxsave->swd;
7945 fpu->ftwx = fxsave->twd;
7946 fpu->last_opcode = fxsave->fop;
7947 fpu->last_ip = fxsave->rip;
7948 fpu->last_dp = fxsave->rdp;
7949 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7950
1393123e 7951 vcpu_put(vcpu);
d0752060
HB		 7952 return 0;
7953}
7954
7955int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7956{
6a96bc7f
CD		 7957 struct fxregs_state *fxsave;
7958
7959 vcpu_load(vcpu);
7960
7961 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7962
d0752060
HB		 7963 memcpy(fxsave->st_space, fpu->fpr, 128);
7964 fxsave->cwd = fpu->fcw;
7965 fxsave->swd = fpu->fsw;
7966 fxsave->twd = fpu->ftwx;
7967 fxsave->fop = fpu->last_opcode;
7968 fxsave->rip = fpu->last_ip;
7969 fxsave->rdp = fpu->last_dp;
7970 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7971
6a96bc7f 7972 vcpu_put(vcpu);
d0752060
HB		 7973 return 0;
7974}
7975
0ee6a517 7976static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7977{
bf935b0b 7978 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7979 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7980 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7981 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7982
2acf923e
DC		 7983 /*
7984 * Ensure guest xcr0 is valid for loading
7985 */
d91cab78 7986 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7987
ad312c7c 7988 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7989}
d0752060 7990
f775b13e 7991/* Swap (qemu) user FPU context for the guest FPU context. */
d0752060
HB		 7992void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7993{
f775b13e
RR		 7994 preempt_disable();
7995 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
38cfd5e3
PB		 7996 /* PKRU is separately restored in kvm_x86_ops->run. */
7997 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
7998 ~XFEATURE_MASK_PKRU);
f775b13e 7999 preempt_enable();
0c04851c 8000 trace_kvm_fpu(1);
d0752060 8001}
d0752060 8002
f775b13e 8003/* When vcpu_run ends, restore user space FPU context. */
d0752060
HB		 8004void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8005{
f775b13e 8006 preempt_disable();
4f836347 8007 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
f775b13e
RR		 8008 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
8009 preempt_enable();
f096ed85 8010 ++vcpu->stat.fpu_reload;
0c04851c 8011 trace_kvm_fpu(0);
d0752060 8012}
e9b11c17
ZX		 8013
8014void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8015{
bd768e14
IY		 8016 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8017
12f9a48f 8018 kvmclock_reset(vcpu);
7f1ea208 8019
e9b11c17 8020 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 8021 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 8022}
8023
8024struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8025 unsigned int id)
8026{
c447e76b
LL		 8027 struct kvm_vcpu *vcpu;
8028
b0c39dc6 8029 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 8030 printk_once(KERN_WARNING
8031 "kvm: SMP vm created on host with unstable TSC; "
8032 "guest TSC will not be reliable\n");
c447e76b
LL		 8033
8034 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8035
c447e76b 8036 return vcpu;
26e5215f 8037}
e9b11c17 8038
26e5215f
AK		 8039int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8040{
19efffa2 8041 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 8042 vcpu_load(vcpu);
d28bc9dd 8043 kvm_vcpu_reset(vcpu, false);
0b2e9904 8044 kvm_lapic_reset(vcpu, false);
8a3c1a33 8045 kvm_mmu_setup(vcpu);
e9b11c17 8046 vcpu_put(vcpu);
ec7660cc 8047 return 0;
e9b11c17
ZX		 8048}
8049
31928aa5 8050void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 8051{
8fe8ab46 8052 struct msr_data msr;
332967a3 8053 struct kvm *kvm = vcpu->kvm;
42897d86 8054
d3457c87
RK		 8055 kvm_hv_vcpu_postcreate(vcpu);
8056
ec7660cc 8057 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 8058 return;
ec7660cc 8059 vcpu_load(vcpu);
8fe8ab46
WA		 8060 msr.data = 0x0;
8061 msr.index = MSR_IA32_TSC;
8062 msr.host_initiated = true;
8063 kvm_write_tsc(vcpu, &msr);
42897d86 8064 vcpu_put(vcpu);
ec7660cc 8065 mutex_unlock(&vcpu->mutex);
42897d86 8066
630994b3
MT		 8067 if (!kvmclock_periodic_sync)
8068 return;
8069
332967a3
AJ		 8070 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8071 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8072}
8073
d40ccc62 8074void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8075{
344d9588
GN		 8076 vcpu->arch.apf.msr_val = 0;
8077
ec7660cc 8078 vcpu_load(vcpu);
e9b11c17
ZX		 8079 kvm_mmu_unload(vcpu);
8080 vcpu_put(vcpu);
8081
8082 kvm_x86_ops->vcpu_free(vcpu);
8083}
8084
d28bc9dd 8085void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8086{
e69fab5d
PB		 8087 vcpu->arch.hflags = 0;
8088
c43203ca 8089 vcpu->arch.smi_pending = 0;
52797bf9 8090 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8091 atomic_set(&vcpu->arch.nmi_queued, 0);
8092 vcpu->arch.nmi_pending = 0;
448fa4a9 8093 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8094 kvm_clear_interrupt_queue(vcpu);
8095 kvm_clear_exception_queue(vcpu);
664f8e26 8096 vcpu->arch.exception.pending = false;
448fa4a9 8097
42dbaa5a 8098 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8099 kvm_update_dr0123(vcpu);
6f43ed01 8100 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8101 kvm_update_dr6(vcpu);
42dbaa5a 8102 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8103 kvm_update_dr7(vcpu);
42dbaa5a 8104
1119022c
NA		 8105 vcpu->arch.cr2 = 0;
8106
3842d135 8107 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8108 vcpu->arch.apf.msr_val = 0;
c9aaa895 8109 vcpu->arch.st.msr_val = 0;
3842d135 8110
12f9a48f
GC		 8111 kvmclock_reset(vcpu);
8112
af585b92
GN		 8113 kvm_clear_async_pf_completion_queue(vcpu);
8114 kvm_async_pf_hash_reset(vcpu);
8115 vcpu->arch.apf.halted = false;
3842d135 8116
a554d207
WL		 8117 if (kvm_mpx_supported()) {
8118 void *mpx_state_buffer;
8119
8120 /*
8121 * To avoid have the INIT path from kvm_apic_has_events() that be
8122 * called with loaded FPU and does not let userspace fix the state.
8123 */
f775b13e
RR		 8124 if (init_event)
8125 kvm_put_guest_fpu(vcpu);
a554d207
WL		 8126 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8127 XFEATURE_MASK_BNDREGS);
8128 if (mpx_state_buffer)
8129 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8130 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8131 XFEATURE_MASK_BNDCSR);
8132 if (mpx_state_buffer)
8133 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 8134 if (init_event)
8135 kvm_load_guest_fpu(vcpu);
a554d207
WL		 8136 }
8137
64d60670 8138 if (!init_event) {
d28bc9dd 8139 kvm_pmu_reset(vcpu);
64d60670 8140 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 8141
8142 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8143 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 8144
8145 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 8146 }
f5132b01 8147
66f7b72e
JS		 8148 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8149 vcpu->arch.regs_avail = ~0;
8150 vcpu->arch.regs_dirty = ~0;
8151
a554d207
WL		 8152 vcpu->arch.ia32_xss = 0;
8153
d28bc9dd 8154 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 8155}
8156
2b4a273b 8157void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 8158{
8159 struct kvm_segment cs;
8160
8161 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8162 cs.selector = vector << 8;
8163 cs.base = vector << 12;
8164 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8165 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 8166}
8167
13a34e06 8168int kvm_arch_hardware_enable(void)
e9b11c17 8169{
ca84d1a2
ZA		 8170 struct kvm *kvm;
8171 struct kvm_vcpu *vcpu;
8172 int i;
0dd6a6ed
ZA		 8173 int ret;
8174 u64 local_tsc;
8175 u64 max_tsc = 0;
8176 bool stable, backwards_tsc = false;
18863bdd
AK		 8177
8178 kvm_shared_msr_cpu_online();
13a34e06 8179 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 8180 if (ret != 0)
8181 return ret;
8182
4ea1636b 8183 local_tsc = rdtsc();
b0c39dc6 8184 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 8185 list_for_each_entry(kvm, &vm_list, vm_list) {
8186 kvm_for_each_vcpu(i, vcpu, kvm) {
8187 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 8188 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8189 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8190 backwards_tsc = true;
8191 if (vcpu->arch.last_host_tsc > max_tsc)
8192 max_tsc = vcpu->arch.last_host_tsc;
8193 }
8194 }
8195 }
8196
8197 /*
8198 * Sometimes, even reliable TSCs go backwards. This happens on
8199 * platforms that reset TSC during suspend or hibernate actions, but
8200 * maintain synchronization. We must compensate. Fortunately, we can
8201 * detect that condition here, which happens early in CPU bringup,
8202 * before any KVM threads can be running. Unfortunately, we can't
8203 * bring the TSCs fully up to date with real time, as we aren't yet far
8204 * enough into CPU bringup that we know how much real time has actually
108b249c 8205 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 8206 * variables that haven't been updated yet.
8207 *
8208 * So we simply find the maximum observed TSC above, then record the
8209 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8210 * the adjustment will be applied. Note that we accumulate
8211 * adjustments, in case multiple suspend cycles happen before some VCPU
8212 * gets a chance to run again. In the event that no KVM threads get a
8213 * chance to run, we will miss the entire elapsed period, as we'll have
8214 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8215 * loose cycle time. This isn't too big a deal, since the loss will be
8216 * uniform across all VCPUs (not to mention the scenario is extremely
8217 * unlikely). It is possible that a second hibernate recovery happens
8218 * much faster than a first, causing the observed TSC here to be
8219 * smaller; this would require additional padding adjustment, which is
8220 * why we set last_host_tsc to the local tsc observed here.
8221 *
8222 * N.B. - this code below runs only on platforms with reliable TSC,
8223 * as that is the only way backwards_tsc is set above. Also note
8224 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8225 * have the same delta_cyc adjustment applied if backwards_tsc
8226 * is detected. Note further, this adjustment is only done once,
8227 * as we reset last_host_tsc on all VCPUs to stop this from being
8228 * called multiple times (one for each physical CPU bringup).
8229 *
4a969980 8230 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 8231 * will be compensated by the logic in vcpu_load, which sets the TSC to
8232 * catchup mode. This will catchup all VCPUs to real time, but cannot
8233 * guarantee that they stay in perfect synchronization.
8234 */
8235 if (backwards_tsc) {
8236 u64 delta_cyc = max_tsc - local_tsc;
8237 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8238 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 8239 kvm_for_each_vcpu(i, vcpu, kvm) {
8240 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8241 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8242 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8243 }
8244
8245 /*
8246 * We have to disable TSC offset matching.. if you were
8247 * booting a VM while issuing an S4 host suspend....
8248 * you may have some problem. Solving this issue is
8249 * left as an exercise to the reader.
8250 */
8251 kvm->arch.last_tsc_nsec = 0;
8252 kvm->arch.last_tsc_write = 0;
8253 }
8254
8255 }
8256 return 0;
e9b11c17
ZX		 8257}
8258
13a34e06 8259void kvm_arch_hardware_disable(void)
e9b11c17 8260{
13a34e06
RK		 8261 kvm_x86_ops->hardware_disable();
8262 drop_user_return_notifiers();
e9b11c17
ZX		 8263}
8264
8265int kvm_arch_hardware_setup(void)
8266{
9e9c3fe4
NA		 8267 int r;
8268
8269 r = kvm_x86_ops->hardware_setup();
8270 if (r != 0)
8271 return r;
8272
35181e86
HZ		 8273 if (kvm_has_tsc_control) {
8274 /*
8275 * Make sure the user can only configure tsc_khz values that
8276 * fit into a signed integer.
8277 * A min value is not calculated needed because it will always
8278 * be 1 on all machines.
8279 */
8280 u64 max = min(0x7fffffffULL,
8281 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8282 kvm_max_guest_tsc_khz = max;
8283
ad721883 8284 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8285 }
ad721883 8286
9e9c3fe4
NA		 8287 kvm_init_msr_list();
8288 return 0;
e9b11c17
ZX		 8289}
8290
8291void kvm_arch_hardware_unsetup(void)
8292{
8293 kvm_x86_ops->hardware_unsetup();
8294}
8295
8296void kvm_arch_check_processor_compat(void *rtn)
8297{
8298 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8299}
8300
8301bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8302{
8303 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8304}
8305EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8306
8307bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8308{
8309 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8310}
8311
54e9818f 8312struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8313EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8314
e9b11c17
ZX		 8315int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8316{
8317 struct page *page;
e9b11c17
ZX		 8318 int r;
8319
b2a05fef 8320 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8321 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8322 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8323 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8324 else
a4535290 8325 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8326
8327 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8328 if (!page) {
8329 r = -ENOMEM;
8330 goto fail;
8331 }
ad312c7c 8332 vcpu->arch.pio_data = page_address(page);
e9b11c17 8333
cc578287 8334 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8335
e9b11c17
ZX		 8336 r = kvm_mmu_create(vcpu);
8337 if (r < 0)
8338 goto fail_free_pio_data;
8339
26de7988 8340 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8341 r = kvm_create_lapic(vcpu);
8342 if (r < 0)
8343 goto fail_mmu_destroy;
54e9818f
GN		 8344 } else
8345 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8346
890ca9ae
HY		 8347 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8348 GFP_KERNEL);
8349 if (!vcpu->arch.mce_banks) {
8350 r = -ENOMEM;
443c39bc 8351 goto fail_free_lapic;
890ca9ae
HY		 8352 }
8353 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8354
f1797359
WY		 8355 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8356 r = -ENOMEM;
f5f48ee1 8357 goto fail_free_mce_banks;
f1797359 8358 }
f5f48ee1 8359
0ee6a517 8360 fx_init(vcpu);
66f7b72e 8361
4344ee98 8362 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8363
5a4f55cd
EK		 8364 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8365
74545705
RK		 8366 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8367
af585b92 8368 kvm_async_pf_hash_reset(vcpu);
f5132b01 8369 kvm_pmu_init(vcpu);
af585b92 8370
1c1a9ce9 8371 vcpu->arch.pending_external_vector = -1;
de63ad4c 8372 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8373
5c919412
AS		 8374 kvm_hv_vcpu_init(vcpu);
8375
e9b11c17 8376 return 0;
0ee6a517 8377
f5f48ee1
SY		 8378fail_free_mce_banks:
8379 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8380fail_free_lapic:
8381 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8382fail_mmu_destroy:
8383 kvm_mmu_destroy(vcpu);
8384fail_free_pio_data:
ad312c7c 8385 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8386fail:
8387 return r;
8388}
8389
8390void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8391{
f656ce01
MT		 8392 int idx;
8393
1f4b34f8 8394 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8395 kvm_pmu_destroy(vcpu);
36cb93fd 8396 kfree(vcpu->arch.mce_banks);
e9b11c17 8397 kvm_free_lapic(vcpu);
f656ce01 8398 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8399 kvm_mmu_destroy(vcpu);
f656ce01 8400 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8401 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8402 if (!lapic_in_kernel(vcpu))
54e9818f 8403 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8404}
d19a9cd2 8405
e790d9ef
RK		 8406void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8407{
ae97a3b8 8408 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8409}
8410
e08b9637 8411int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8412{
e08b9637
CO		 8413 if (type)
8414 return -EINVAL;
8415
6ef768fa 8416 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8417 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8418 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8419 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8420 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8421
5550af4d
SY		 8422 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8423 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8424 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8425 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8426 &kvm->arch.irq_sources_bitmap);
5550af4d 8427
038f8c11 8428 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8429 mutex_init(&kvm->arch.apic_map_lock);
3f5ad8be 8430 mutex_init(&kvm->arch.hyperv.hv_lock);
d828199e
MT		 8431 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8432
108b249c 8433 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8434 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8435
7e44e449 8436 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8437 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8438
0eb05bf2 8439 kvm_page_track_init(kvm);
13d268ca 8440 kvm_mmu_init_vm(kvm);
0eb05bf2 8441
03543133
SS		 8442 if (kvm_x86_ops->vm_init)
8443 return kvm_x86_ops->vm_init(kvm);
8444
d89f5eff 8445 return 0;
d19a9cd2
ZX		 8446}
8447
8448static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8449{
ec7660cc 8450 vcpu_load(vcpu);
d19a9cd2
ZX		 8451 kvm_mmu_unload(vcpu);
8452 vcpu_put(vcpu);
8453}
8454
8455static void kvm_free_vcpus(struct kvm *kvm)
8456{
8457 unsigned int i;
988a2cae 8458 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8459
8460 /*
8461 * Unpin any mmu pages first.
8462 */
af585b92
GN		 8463 kvm_for_each_vcpu(i, vcpu, kvm) {
8464 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8465 kvm_unload_vcpu_mmu(vcpu);
af585b92 8466 }
988a2cae
GN		 8467 kvm_for_each_vcpu(i, vcpu, kvm)
8468 kvm_arch_vcpu_free(vcpu);
8469
8470 mutex_lock(&kvm->lock);
8471 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8472 kvm->vcpus[i] = NULL;
d19a9cd2 8473
988a2cae
GN		 8474 atomic_set(&kvm->online_vcpus, 0);
8475 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8476}
8477
ad8ba2cd
SY		 8478void kvm_arch_sync_events(struct kvm *kvm)
8479{
332967a3 8480 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8481 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8482 kvm_free_pit(kvm);
ad8ba2cd
SY		 8483}
8484
1d8007bd 8485int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8486{
8487 int i, r;
25188b99 8488 unsigned long hva;
f0d648bd
PB		 8489 struct kvm_memslots *slots = kvm_memslots(kvm);
8490 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8491
8492 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8493 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8494 return -EINVAL;
9da0e4d5 8495
f0d648bd
PB		 8496 slot = id_to_memslot(slots, id);
8497 if (size) {
b21629da 8498 if (slot->npages)
f0d648bd
PB		 8499 return -EEXIST;
8500
8501 /*
8502 * MAP_SHARED to prevent internal slot pages from being moved
8503 * by fork()/COW.
8504 */
8505 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8506 MAP_SHARED | MAP_ANONYMOUS, 0);
8507 if (IS_ERR((void *)hva))
8508 return PTR_ERR((void *)hva);
8509 } else {
8510 if (!slot->npages)
8511 return 0;
8512
8513 hva = 0;
8514 }
8515
8516 old = *slot;
9da0e4d5 8517 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8518 struct kvm_userspace_memory_region m;
9da0e4d5 8519
1d8007bd
PB		 8520 m.slot = id | (i << 16);
8521 m.flags = 0;
8522 m.guest_phys_addr = gpa;
f0d648bd 8523 m.userspace_addr = hva;
1d8007bd 8524 m.memory_size = size;
9da0e4d5
PB		 8525 r = __kvm_set_memory_region(kvm, &m);
8526 if (r < 0)
8527 return r;
8528 }
8529
103c763c
EB		 8530 if (!size)
8531 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 8532
9da0e4d5
PB		 8533 return 0;
8534}
8535EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8536
1d8007bd 8537int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8538{
8539 int r;
8540
8541 mutex_lock(&kvm->slots_lock);
1d8007bd 8542 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8543 mutex_unlock(&kvm->slots_lock);
8544
8545 return r;
8546}
8547EXPORT_SYMBOL_GPL(x86_set_memory_region);
8548
d19a9cd2
ZX		 8549void kvm_arch_destroy_vm(struct kvm *kvm)
8550{
27469d29
AH		 8551 if (current->mm == kvm->mm) {
8552 /*
8553 * Free memory regions allocated on behalf of userspace,
8554 * unless the the memory map has changed due to process exit
8555 * or fd copying.
8556 */
1d8007bd
PB		 8557 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8558 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8559 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8560 }
03543133
SS		 8561 if (kvm_x86_ops->vm_destroy)
8562 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8563 kvm_pic_destroy(kvm);
8564 kvm_ioapic_destroy(kvm);
d19a9cd2 8565 kvm_free_vcpus(kvm);
af1bae54 8566 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8567 kvm_mmu_uninit_vm(kvm);
2beb6dad 8568 kvm_page_track_cleanup(kvm);
d19a9cd2 8569}
0de10343 8570
5587027c 8571void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8572 struct kvm_memory_slot *dont)
8573{
8574 int i;
8575
d89cc617
TY		 8576 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8577 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8578 kvfree(free->arch.rmap[i]);
d89cc617 8579 free->arch.rmap[i] = NULL;
77d11309 8580 }
d89cc617
TY		 8581 if (i == 0)
8582 continue;
8583
8584 if (!dont || free->arch.lpage_info[i - 1] !=
8585 dont->arch.lpage_info[i - 1]) {
548ef284 8586 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8587 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8588 }
8589 }
21ebbeda
XG		 8590
8591 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8592}
8593
5587027c
AK		 8594int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8595 unsigned long npages)
db3fe4eb
TY		 8596{
8597 int i;
8598
d89cc617 8599 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8600 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8601 unsigned long ugfn;
8602 int lpages;
d89cc617 8603 int level = i + 1;
db3fe4eb
TY		 8604
8605 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8606 slot->base_gfn, level) + 1;
8607
d89cc617 8608 slot->arch.rmap[i] =
a7c3e901 8609 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8610 if (!slot->arch.rmap[i])
77d11309 8611 goto out_free;
d89cc617
TY		 8612 if (i == 0)
8613 continue;
77d11309 8614
a7c3e901 8615 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8616 if (!linfo)
db3fe4eb
TY		 8617 goto out_free;
8618
92f94f1e
XG		 8619 slot->arch.lpage_info[i - 1] = linfo;
8620
db3fe4eb 8621 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8622 linfo[0].disallow_lpage = 1;
db3fe4eb 8623 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8624 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8625 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8626 /*
8627 * If the gfn and userspace address are not aligned wrt each
8628 * other, or if explicitly asked to, disable large page
8629 * support for this slot
8630 */
8631 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8632 !kvm_largepages_enabled()) {
8633 unsigned long j;
8634
8635 for (j = 0; j < lpages; ++j)
92f94f1e 8636 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8637 }
8638 }
8639
21ebbeda
XG		 8640 if (kvm_page_track_create_memslot(slot, npages))
8641 goto out_free;
8642
db3fe4eb
TY		 8643 return 0;
8644
8645out_free:
d89cc617 8646 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8647 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8648 slot->arch.rmap[i] = NULL;
8649 if (i == 0)
8650 continue;
8651
548ef284 8652 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8653 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8654 }
8655 return -ENOMEM;
8656}
8657
15f46015 8658void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8659{
e6dff7d1
TY		 8660 /*
8661 * memslots->generation has been incremented.
8662 * mmio generation may have reached its maximum value.
8663 */
54bf36aa 8664 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8665}
8666
f7784b8e
MT		 8667int kvm_arch_prepare_memory_region(struct kvm *kvm,
8668 struct kvm_memory_slot *memslot,
09170a49 8669 const struct kvm_userspace_memory_region *mem,
7b6195a9 8670 enum kvm_mr_change change)
0de10343 8671{
f7784b8e
MT		 8672 return 0;
8673}
8674
88178fd4
KH		 8675static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8676 struct kvm_memory_slot *new)
8677{
8678 /* Still write protect RO slot */
8679 if (new->flags & KVM_MEM_READONLY) {
8680 kvm_mmu_slot_remove_write_access(kvm, new);
8681 return;
8682 }
8683
8684 /*
8685 * Call kvm_x86_ops dirty logging hooks when they are valid.
8686 *
8687 * kvm_x86_ops->slot_disable_log_dirty is called when:
8688 *
8689 * - KVM_MR_CREATE with dirty logging is disabled
8690 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8691 *
8692 * The reason is, in case of PML, we need to set D-bit for any slots
8693 * with dirty logging disabled in order to eliminate unnecessary GPA
8694 * logging in PML buffer (and potential PML buffer full VMEXT). This
8695 * guarantees leaving PML enabled during guest's lifetime won't have
8696 * any additonal overhead from PML when guest is running with dirty
8697 * logging disabled for memory slots.
8698 *
8699 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8700 * to dirty logging mode.
8701 *
8702 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8703 *
8704 * In case of write protect:
8705 *
8706 * Write protect all pages for dirty logging.
8707 *
8708 * All the sptes including the large sptes which point to this
8709 * slot are set to readonly. We can not create any new large
8710 * spte on this slot until the end of the logging.
8711 *
8712 * See the comments in fast_page_fault().
8713 */
8714 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8715 if (kvm_x86_ops->slot_enable_log_dirty)
8716 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8717 else
8718 kvm_mmu_slot_remove_write_access(kvm, new);
8719 } else {
8720 if (kvm_x86_ops->slot_disable_log_dirty)
8721 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8722 }
8723}
8724
f7784b8e 8725void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8726 const struct kvm_userspace_memory_region *mem,
8482644a 8727 const struct kvm_memory_slot *old,
f36f3f28 8728 const struct kvm_memory_slot *new,
8482644a 8729 enum kvm_mr_change change)
f7784b8e 8730{
8482644a 8731 int nr_mmu_pages = 0;
f7784b8e 8732
48c0e4e9
XG		 8733 if (!kvm->arch.n_requested_mmu_pages)
8734 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8735
48c0e4e9 8736 if (nr_mmu_pages)
0de10343 8737 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8738
3ea3b7fa
WL		 8739 /*
8740 * Dirty logging tracks sptes in 4k granularity, meaning that large
8741 * sptes have to be split. If live migration is successful, the guest
8742 * in the source machine will be destroyed and large sptes will be
8743 * created in the destination. However, if the guest continues to run
8744 * in the source machine (for example if live migration fails), small
8745 * sptes will remain around and cause bad performance.
8746 *
8747 * Scan sptes if dirty logging has been stopped, dropping those
8748 * which can be collapsed into a single large-page spte. Later
8749 * page faults will create the large-page sptes.
8750 */
8751 if ((change != KVM_MR_DELETE) &&
8752 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8753 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8754 kvm_mmu_zap_collapsible_sptes(kvm, new);
8755
c972f3b1 8756 /*
88178fd4 8757 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8758 *
88178fd4
KH		 8759 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8760 * been zapped so no dirty logging staff is needed for old slot. For
8761 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8762 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8763 *
8764 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8765 */
88178fd4 8766 if (change != KVM_MR_DELETE)
f36f3f28 8767 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8768}
1d737c8a 8769
2df72e9b 8770void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8771{
6ca18b69 8772 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8773}
8774
2df72e9b
MT		 8775void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8776 struct kvm_memory_slot *slot)
8777{
ae7cd873 8778 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8779}
8780
5d9bc648
PB		 8781static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8782{
8783 if (!list_empty_careful(&vcpu->async_pf.done))
8784 return true;
8785
8786 if (kvm_apic_has_events(vcpu))
8787 return true;
8788
8789 if (vcpu->arch.pv.pv_unhalted)
8790 return true;
8791
a5f01f8e
WL		 8792 if (vcpu->arch.exception.pending)
8793 return true;
8794
47a66eed
Z		 8795 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8796 (vcpu->arch.nmi_pending &&
8797 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 8798 return true;
8799
47a66eed
Z		 8800 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8801 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 8802 return true;
8803
5d9bc648
PB		 8804 if (kvm_arch_interrupt_allowed(vcpu) &&
8805 kvm_cpu_has_interrupt(vcpu))
8806 return true;
8807
1f4b34f8
AS		 8808 if (kvm_hv_has_stimer_pending(vcpu))
8809 return true;
8810
5d9bc648
PB		 8811 return false;
8812}
8813
1d737c8a
ZX		 8814int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8815{
5d9bc648 8816 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8817}
5736199a 8818
199b5763
LM		 8819bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
8820{
de63ad4c 8821 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 8822}
8823
b6d33834 8824int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8825{
b6d33834 8826 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8827}
78646121
GN		 8828
8829int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8830{
8831 return kvm_x86_ops->interrupt_allowed(vcpu);
8832}
229456fc 8833
82b32774 8834unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8835{
82b32774
NA		 8836 if (is_64_bit_mode(vcpu))
8837 return kvm_rip_read(vcpu);
8838 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8839 kvm_rip_read(vcpu));
8840}
8841EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8842
82b32774
NA		 8843bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8844{
8845 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8846}
8847EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8848
94fe45da
JK		 8849unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8850{
8851 unsigned long rflags;
8852
8853 rflags = kvm_x86_ops->get_rflags(vcpu);
8854 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8855 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8856 return rflags;
8857}
8858EXPORT_SYMBOL_GPL(kvm_get_rflags);
8859
6addfc42 8860static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8861{
8862 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8863 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8864 rflags |= X86_EFLAGS_TF;
94fe45da 8865 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8866}
8867
8868void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8869{
8870 __kvm_set_rflags(vcpu, rflags);
3842d135 8871 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8872}
8873EXPORT_SYMBOL_GPL(kvm_set_rflags);
8874
56028d08
GN		 8875void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8876{
8877 int r;
8878
fb67e14f 8879 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8880 work->wakeup_all)
56028d08
GN		 8881 return;
8882
8883 r = kvm_mmu_reload(vcpu);
8884 if (unlikely(r))
8885 return;
8886
fb67e14f
XG		 8887 if (!vcpu->arch.mmu.direct_map &&
8888 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8889 return;
8890
56028d08
GN		 8891 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8892}
8893
af585b92
GN		 8894static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8895{
8896 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8897}
8898
8899static inline u32 kvm_async_pf_next_probe(u32 key)
8900{
8901 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8902}
8903
8904static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8905{
8906 u32 key = kvm_async_pf_hash_fn(gfn);
8907
8908 while (vcpu->arch.apf.gfns[key] != ~0)
8909 key = kvm_async_pf_next_probe(key);
8910
8911 vcpu->arch.apf.gfns[key] = gfn;
8912}
8913
8914static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8915{
8916 int i;
8917 u32 key = kvm_async_pf_hash_fn(gfn);
8918
8919 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8920 (vcpu->arch.apf.gfns[key] != gfn &&
8921 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8922 key = kvm_async_pf_next_probe(key);
8923
8924 return key;
8925}
8926
8927bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8928{
8929 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8930}
8931
8932static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8933{
8934 u32 i, j, k;
8935
8936 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8937 while (true) {
8938 vcpu->arch.apf.gfns[i] = ~0;
8939 do {
8940 j = kvm_async_pf_next_probe(j);
8941 if (vcpu->arch.apf.gfns[j] == ~0)
8942 return;
8943 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8944 /*
8945 * k lies cyclically in ]i,j]
8946 * | i.k.j |
8947 * |....j i.k.| or |.k..j i...|
8948 */
8949 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8950 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8951 i = j;
8952 }
8953}
8954
7c90705b
GN		 8955static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8956{
4e335d9e
PB		 8957
8958 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8959 sizeof(val));
7c90705b
GN		 8960}
8961
9a6e7c39
WL		 8962static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
8963{
8964
8965 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
8966 sizeof(u32));
8967}
8968
af585b92
GN		 8969void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8970 struct kvm_async_pf *work)
8971{
6389ee94
AK		 8972 struct x86_exception fault;
8973
7c90705b 8974 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8975 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8976
8977 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8978 (vcpu->arch.apf.send_user_only &&
8979 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8980 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8981 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8982 fault.vector = PF_VECTOR;
8983 fault.error_code_valid = true;
8984 fault.error_code = 0;
8985 fault.nested_page_fault = false;
8986 fault.address = work->arch.token;
adfe20fb 8987 fault.async_page_fault = true;
6389ee94 8988 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8989 }
af585b92
GN		 8990}
8991
8992void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8993 struct kvm_async_pf *work)
8994{
6389ee94 8995 struct x86_exception fault;
9a6e7c39 8996 u32 val;
6389ee94 8997
f2e10669 8998 if (work->wakeup_all)
7c90705b
GN		 8999 work->arch.token = ~0; /* broadcast wakeup */
9000 else
9001 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 9002 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 9003
9a6e7c39
WL		 9004 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9005 !apf_get_user(vcpu, &val)) {
9006 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9007 vcpu->arch.exception.pending &&
9008 vcpu->arch.exception.nr == PF_VECTOR &&
9009 !apf_put_user(vcpu, 0)) {
9010 vcpu->arch.exception.injected = false;
9011 vcpu->arch.exception.pending = false;
9012 vcpu->arch.exception.nr = 0;
9013 vcpu->arch.exception.has_error_code = false;
9014 vcpu->arch.exception.error_code = 0;
9015 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9016 fault.vector = PF_VECTOR;
9017 fault.error_code_valid = true;
9018 fault.error_code = 0;
9019 fault.nested_page_fault = false;
9020 fault.address = work->arch.token;
9021 fault.async_page_fault = true;
9022 kvm_inject_page_fault(vcpu, &fault);
9023 }
7c90705b 9024 }
e6d53e3b 9025 vcpu->arch.apf.halted = false;
a4fa1635 9026 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 9027}
9028
9029bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9030{
9031 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9032 return true;
9033 else
9bc1f09f 9034 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 9035}
9036
5544eb9b
PB		 9037void kvm_arch_start_assignment(struct kvm *kvm)
9038{
9039 atomic_inc(&kvm->arch.assigned_device_count);
9040}
9041EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9042
9043void kvm_arch_end_assignment(struct kvm *kvm)
9044{
9045 atomic_dec(&kvm->arch.assigned_device_count);
9046}
9047EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9048
9049bool kvm_arch_has_assigned_device(struct kvm *kvm)
9050{
9051 return atomic_read(&kvm->arch.assigned_device_count);
9052}
9053EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9054
e0f0bbc5
AW		 9055void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9056{
9057 atomic_inc(&kvm->arch.noncoherent_dma_count);
9058}
9059EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9060
9061void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9062{
9063 atomic_dec(&kvm->arch.noncoherent_dma_count);
9064}
9065EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9066
9067bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9068{
9069 return atomic_read(&kvm->arch.noncoherent_dma_count);
9070}
9071EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9072
14717e20
AW		 9073bool kvm_arch_has_irq_bypass(void)
9074{
9075 return kvm_x86_ops->update_pi_irte != NULL;
9076}
9077
87276880
FW		 9078int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9079 struct irq_bypass_producer *prod)
9080{
9081 struct kvm_kernel_irqfd *irqfd =
9082 container_of(cons, struct kvm_kernel_irqfd, consumer);
9083
14717e20 9084 irqfd->producer = prod;
87276880 9085
14717e20
AW		 9086 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9087 prod->irq, irqfd->gsi, 1);
87276880
FW		 9088}
9089
9090void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9091 struct irq_bypass_producer *prod)
9092{
9093 int ret;
9094 struct kvm_kernel_irqfd *irqfd =
9095 container_of(cons, struct kvm_kernel_irqfd, consumer);
9096
87276880
FW		 9097 WARN_ON(irqfd->producer != prod);
9098 irqfd->producer = NULL;
9099
9100 /*
9101 * When producer of consumer is unregistered, we change back to
9102 * remapped mode, so we can re-use the current implementation
bb3541f1 9103 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 9104 * int this case doesn't want to receive the interrupts.
9105 */
9106 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9107 if (ret)
9108 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9109 " fails: %d\n", irqfd->consumer.token, ret);
9110}
9111
9112int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9113 uint32_t guest_irq, bool set)
9114{
9115 if (!kvm_x86_ops->update_pi_irte)
9116 return -EINVAL;
9117
9118 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9119}
9120
52004014
FW		 9121bool kvm_vector_hashing_enabled(void)
9122{
9123 return vector_hashing;
9124}
9125EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9126
229456fc 9127EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 9128EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 9129EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9130EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9131EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9132EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 9133EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 9134EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 9135EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 9136EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 9137EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 9138EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 9139EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 9140EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 9141EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 9142EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 9143EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 9144EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9145EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
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