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KVM: Silence underflow warning in avic_get_physical_id_entry()
[mirror_ubuntu-hirsute-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad
IM		 56#include <linux/sched/stat.h>
57
aec51dc4 58#include <trace/events/kvm.h>
2ed152af 59
24f1e32c 60#include <asm/debugreg.h>
d825ed0a 61#include <asm/msr.h>
a5f61300 62#include <asm/desc.h>
890ca9ae 63#include <asm/mce.h>
f89e32e0 64#include <linux/kernel_stat.h>
78f7f1e5 65#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 66#include <asm/pvclock.h>
217fc9cf 67#include <asm/div64.h>
efc64404 68#include <asm/irq_remapping.h>
043405e1 69
d1898b73
DH		 70#define CREATE_TRACE_POINTS
71#include "trace.h"
72
313a3dc7 73#define MAX_IO_MSRS 256
890ca9ae 74#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 75u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
76EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 77
0f65dd70
AK		 78#define emul_to_vcpu(ctxt) \
79 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
80
50a37eb4
JR		 81/* EFER defaults:
82 * - enable syscall per default because its emulated by KVM
83 * - enable LME and LMA per default on 64 bit KVM
84 */
85#ifdef CONFIG_X86_64
1260edbe
LJ		 86static
87u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 88#else
1260edbe 89static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 90#endif
313a3dc7 91
ba1389b7
AK		 92#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
93#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 94
c519265f
RK		 95#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
96 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 97
cb142eb7 98static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 99static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 100static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 101static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 102
893590c7 103struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 104EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 105
893590c7 106static bool __read_mostly ignore_msrs = 0;
476bc001 107module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 108
9ed96e87
MT		 109unsigned int min_timer_period_us = 500;
110module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
111
630994b3
MT		 112static bool __read_mostly kvmclock_periodic_sync = true;
113module_param(kvmclock_periodic_sync, bool, S_IRUGO);
114
893590c7 115bool __read_mostly kvm_has_tsc_control;
92a1f12d 116EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 117u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 118EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 119u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
120EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
121u64 __read_mostly kvm_max_tsc_scaling_ratio;
122EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 123u64 __read_mostly kvm_default_tsc_scaling_ratio;
124EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 125
cc578287 126/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 127static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 128module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
129
d0659d94 130/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 131unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 132module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
133
52004014
FW		 134static bool __read_mostly vector_hashing = true;
135module_param(vector_hashing, bool, S_IRUGO);
136
893590c7 137static bool __read_mostly backwards_tsc_observed = false;
16a96021 138
18863bdd
AK		 139#define KVM_NR_SHARED_MSRS 16
140
141struct kvm_shared_msrs_global {
142 int nr;
2bf78fa7 143 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 144};
145
146struct kvm_shared_msrs {
147 struct user_return_notifier urn;
148 bool registered;
2bf78fa7
SY		 149 struct kvm_shared_msr_values {
150 u64 host;
151 u64 curr;
152 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 153};
154
155static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 156static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 157
417bc304 158struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 159 { "pf_fixed", VCPU_STAT(pf_fixed) },
160 { "pf_guest", VCPU_STAT(pf_guest) },
161 { "tlb_flush", VCPU_STAT(tlb_flush) },
162 { "invlpg", VCPU_STAT(invlpg) },
163 { "exits", VCPU_STAT(exits) },
164 { "io_exits", VCPU_STAT(io_exits) },
165 { "mmio_exits", VCPU_STAT(mmio_exits) },
166 { "signal_exits", VCPU_STAT(signal_exits) },
167 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 168 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 169 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 170 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 171 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 172 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 173 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 174 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 175 { "request_irq", VCPU_STAT(request_irq_exits) },
176 { "irq_exits", VCPU_STAT(irq_exits) },
177 { "host_state_reload", VCPU_STAT(host_state_reload) },
178 { "efer_reload", VCPU_STAT(efer_reload) },
179 { "fpu_reload", VCPU_STAT(fpu_reload) },
180 { "insn_emulation", VCPU_STAT(insn_emulation) },
181 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 182 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 183 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 184 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 185 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
186 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
187 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
188 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
189 { "mmu_flooded", VM_STAT(mmu_flooded) },
190 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 191 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 192 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 193 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 194 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 195 { "max_mmu_page_hash_collisions",
196 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 197 { NULL }
198};
199
2acf923e
DC		 200u64 __read_mostly host_xcr0;
201
b6785def 202static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 203
af585b92
GN		 204static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
205{
206 int i;
207 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
208 vcpu->arch.apf.gfns[i] = ~0;
209}
210
18863bdd
AK		 211static void kvm_on_user_return(struct user_return_notifier *urn)
212{
213 unsigned slot;
18863bdd
AK		 214 struct kvm_shared_msrs *locals
215 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 216 struct kvm_shared_msr_values *values;
1650b4eb
IA		 217 unsigned long flags;
218
219 /*
220 * Disabling irqs at this point since the following code could be
221 * interrupted and executed through kvm_arch_hardware_disable()
222 */
223 local_irq_save(flags);
224 if (locals->registered) {
225 locals->registered = false;
226 user_return_notifier_unregister(urn);
227 }
228 local_irq_restore(flags);
18863bdd 229 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 230 values = &locals->values[slot];
231 if (values->host != values->curr) {
232 wrmsrl(shared_msrs_global.msrs[slot], values->host);
233 values->curr = values->host;
18863bdd
AK		 234 }
235 }
18863bdd
AK		 236}
237
2bf78fa7 238static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 239{
18863bdd 240 u64 value;
013f6a5d
MT		 241 unsigned int cpu = smp_processor_id();
242 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 243
2bf78fa7
SY		 244 /* only read, and nobody should modify it at this time,
245 * so don't need lock */
246 if (slot >= shared_msrs_global.nr) {
247 printk(KERN_ERR "kvm: invalid MSR slot!");
248 return;
249 }
250 rdmsrl_safe(msr, &value);
251 smsr->values[slot].host = value;
252 smsr->values[slot].curr = value;
253}
254
255void kvm_define_shared_msr(unsigned slot, u32 msr)
256{
0123be42 257 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 258 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 259 if (slot >= shared_msrs_global.nr)
260 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 261}
262EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
263
264static void kvm_shared_msr_cpu_online(void)
265{
266 unsigned i;
18863bdd
AK		 267
268 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 269 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 270}
271
8b3c3104 272int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 273{
013f6a5d
MT		 274 unsigned int cpu = smp_processor_id();
275 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 276 int err;
18863bdd 277
2bf78fa7 278 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 279 return 0;
2bf78fa7 280 smsr->values[slot].curr = value;
8b3c3104
AH		 281 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
282 if (err)
283 return 1;
284
18863bdd
AK		 285 if (!smsr->registered) {
286 smsr->urn.on_user_return = kvm_on_user_return;
287 user_return_notifier_register(&smsr->urn);
288 smsr->registered = true;
289 }
8b3c3104 290 return 0;
18863bdd
AK		 291}
292EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
293
13a34e06 294static void drop_user_return_notifiers(void)
3548bab5 295{
013f6a5d
MT		 296 unsigned int cpu = smp_processor_id();
297 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 298
299 if (smsr->registered)
300 kvm_on_user_return(&smsr->urn);
301}
302
6866b83e
CO		 303u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
304{
8a5a87d9 305 return vcpu->arch.apic_base;
6866b83e
CO		 306}
307EXPORT_SYMBOL_GPL(kvm_get_apic_base);
308
58cb628d
JK		 309int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
310{
311 u64 old_state = vcpu->arch.apic_base &
312 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
313 u64 new_state = msr_info->data &
314 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
315 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
316 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
317
318 if (!msr_info->host_initiated &&
319 ((msr_info->data & reserved_bits) != 0 ||
320 new_state == X2APIC_ENABLE ||
321 (new_state == MSR_IA32_APICBASE_ENABLE &&
322 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
323 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
324 old_state == 0)))
325 return 1;
326
327 kvm_lapic_set_base(vcpu, msr_info->data);
328 return 0;
6866b83e
CO		 329}
330EXPORT_SYMBOL_GPL(kvm_set_apic_base);
331
2605fc21 332asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 333{
334 /* Fault while not rebooting. We want the trace. */
335 BUG();
336}
337EXPORT_SYMBOL_GPL(kvm_spurious_fault);
338
3fd28fce
ED		 339#define EXCPT_BENIGN 0
340#define EXCPT_CONTRIBUTORY 1
341#define EXCPT_PF 2
342
343static int exception_class(int vector)
344{
345 switch (vector) {
346 case PF_VECTOR:
347 return EXCPT_PF;
348 case DE_VECTOR:
349 case TS_VECTOR:
350 case NP_VECTOR:
351 case SS_VECTOR:
352 case GP_VECTOR:
353 return EXCPT_CONTRIBUTORY;
354 default:
355 break;
356 }
357 return EXCPT_BENIGN;
358}
359
d6e8c854
NA		 360#define EXCPT_FAULT 0
361#define EXCPT_TRAP 1
362#define EXCPT_ABORT 2
363#define EXCPT_INTERRUPT 3
364
365static int exception_type(int vector)
366{
367 unsigned int mask;
368
369 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
370 return EXCPT_INTERRUPT;
371
372 mask = 1 << vector;
373
374 /* #DB is trap, as instruction watchpoints are handled elsewhere */
375 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
376 return EXCPT_TRAP;
377
378 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
379 return EXCPT_ABORT;
380
381 /* Reserved exceptions will result in fault */
382 return EXCPT_FAULT;
383}
384
3fd28fce 385static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 386 unsigned nr, bool has_error, u32 error_code,
387 bool reinject)
3fd28fce
ED		 388{
389 u32 prev_nr;
390 int class1, class2;
391
3842d135
AK		 392 kvm_make_request(KVM_REQ_EVENT, vcpu);
393
3fd28fce
ED		 394 if (!vcpu->arch.exception.pending) {
395 queue:
3ffb2468
NA		 396 if (has_error && !is_protmode(vcpu))
397 has_error = false;
3fd28fce
ED		 398 vcpu->arch.exception.pending = true;
399 vcpu->arch.exception.has_error_code = has_error;
400 vcpu->arch.exception.nr = nr;
401 vcpu->arch.exception.error_code = error_code;
3f0fd292 402 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 403 return;
404 }
405
406 /* to check exception */
407 prev_nr = vcpu->arch.exception.nr;
408 if (prev_nr == DF_VECTOR) {
409 /* triple fault -> shutdown */
a8eeb04a 410 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 411 return;
412 }
413 class1 = exception_class(prev_nr);
414 class2 = exception_class(nr);
415 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
416 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
417 /* generate double fault per SDM Table 5-5 */
418 vcpu->arch.exception.pending = true;
419 vcpu->arch.exception.has_error_code = true;
420 vcpu->arch.exception.nr = DF_VECTOR;
421 vcpu->arch.exception.error_code = 0;
422 } else
423 /* replace previous exception with a new one in a hope
424 that instruction re-execution will regenerate lost
425 exception */
426 goto queue;
427}
428
298101da
AK		 429void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
430{
ce7ddec4 431 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 432}
433EXPORT_SYMBOL_GPL(kvm_queue_exception);
434
ce7ddec4
JR		 435void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
436{
437 kvm_multiple_exception(vcpu, nr, false, 0, true);
438}
439EXPORT_SYMBOL_GPL(kvm_requeue_exception);
440
6affcbed 441int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 442{
db8fcefa
AP		 443 if (err)
444 kvm_inject_gp(vcpu, 0);
445 else
6affcbed
KH		 446 return kvm_skip_emulated_instruction(vcpu);
447
448 return 1;
db8fcefa
AP		 449}
450EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 451
6389ee94 452void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 453{
454 ++vcpu->stat.pf_guest;
6389ee94
AK		 455 vcpu->arch.cr2 = fault->address;
456 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 457}
27d6c865 458EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 459
ef54bcfe 460static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 461{
6389ee94
AK		 462 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
463 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 464 else
6389ee94 465 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 466
467 return fault->nested_page_fault;
d4f8cf66
JR		 468}
469
3419ffc8
SY		 470void kvm_inject_nmi(struct kvm_vcpu *vcpu)
471{
7460fb4a
AK		 472 atomic_inc(&vcpu->arch.nmi_queued);
473 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 474}
475EXPORT_SYMBOL_GPL(kvm_inject_nmi);
476
298101da
AK		 477void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
478{
ce7ddec4 479 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 480}
481EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
482
ce7ddec4
JR		 483void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
484{
485 kvm_multiple_exception(vcpu, nr, true, error_code, true);
486}
487EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
488
0a79b009
AK		 489/*
490 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
491 * a #GP and return false.
492 */
493bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 494{
0a79b009
AK		 495 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
496 return true;
497 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
498 return false;
298101da 499}
0a79b009 500EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 501
16f8a6f9
NA		 502bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
503{
504 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
505 return true;
506
507 kvm_queue_exception(vcpu, UD_VECTOR);
508 return false;
509}
510EXPORT_SYMBOL_GPL(kvm_require_dr);
511
ec92fe44
JR		 512/*
513 * This function will be used to read from the physical memory of the currently
54bf36aa 514 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 515 * can read from guest physical or from the guest's guest physical memory.
516 */
517int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
518 gfn_t ngfn, void *data, int offset, int len,
519 u32 access)
520{
54987b7a 521 struct x86_exception exception;
ec92fe44
JR		 522 gfn_t real_gfn;
523 gpa_t ngpa;
524
525 ngpa = gfn_to_gpa(ngfn);
54987b7a 526 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 527 if (real_gfn == UNMAPPED_GVA)
528 return -EFAULT;
529
530 real_gfn = gpa_to_gfn(real_gfn);
531
54bf36aa 532 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 533}
534EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
535
69b0049a 536static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 537 void *data, int offset, int len, u32 access)
538{
539 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
540 data, offset, len, access);
541}
542
a03490ed
CO		 543/*
544 * Load the pae pdptrs. Return true is they are all valid.
545 */
ff03a073 546int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 547{
548 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
549 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
550 int i;
551 int ret;
ff03a073 552 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 553
ff03a073
JR		 554 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
555 offset * sizeof(u64), sizeof(pdpte),
556 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 557 if (ret < 0) {
558 ret = 0;
559 goto out;
560 }
561 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 562 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 563 (pdpte[i] &
564 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 565 ret = 0;
566 goto out;
567 }
568 }
569 ret = 1;
570
ff03a073 571 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 572 __set_bit(VCPU_EXREG_PDPTR,
573 (unsigned long *)&vcpu->arch.regs_avail);
574 __set_bit(VCPU_EXREG_PDPTR,
575 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 576out:
a03490ed
CO		 577
578 return ret;
579}
cc4b6871 580EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 581
9ed38ffa 582bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 583{
ff03a073 584 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 585 bool changed = true;
3d06b8bf
JR		 586 int offset;
587 gfn_t gfn;
d835dfec
AK		 588 int r;
589
590 if (is_long_mode(vcpu) || !is_pae(vcpu))
591 return false;
592
6de4f3ad
AK		 593 if (!test_bit(VCPU_EXREG_PDPTR,
594 (unsigned long *)&vcpu->arch.regs_avail))
595 return true;
596
9f8fe504
AK		 597 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
598 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 599 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
600 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 601 if (r < 0)
602 goto out;
ff03a073 603 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 604out:
d835dfec
AK		 605
606 return changed;
607}
9ed38ffa 608EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 609
49a9b07e 610int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 611{
aad82703 612 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 613 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 614
f9a48e6a
AK		 615 cr0 |= X86_CR0_ET;
616
ab344828 617#ifdef CONFIG_X86_64
0f12244f
GN		 618 if (cr0 & 0xffffffff00000000UL)
619 return 1;
ab344828
GN		 620#endif
621
622 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 623
0f12244f
GN		 624 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
625 return 1;
a03490ed 626
0f12244f
GN		 627 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
628 return 1;
a03490ed
CO		 629
630 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
631#ifdef CONFIG_X86_64
f6801dff 632 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 633 int cs_db, cs_l;
634
0f12244f
GN		 635 if (!is_pae(vcpu))
636 return 1;
a03490ed 637 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 638 if (cs_l)
639 return 1;
a03490ed
CO		 640 } else
641#endif
ff03a073 642 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 643 kvm_read_cr3(vcpu)))
0f12244f 644 return 1;
a03490ed
CO		 645 }
646
ad756a16
MJ		 647 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
648 return 1;
649
a03490ed 650 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 651
d170c419 652 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 653 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 654 kvm_async_pf_hash_reset(vcpu);
655 }
e5f3f027 656
aad82703
SY		 657 if ((cr0 ^ old_cr0) & update_bits)
658 kvm_mmu_reset_context(vcpu);
b18d5431 659
879ae188
LE		 660 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
661 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
662 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 663 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
664
0f12244f
GN		 665 return 0;
666}
2d3ad1f4 667EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 668
2d3ad1f4 669void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 670{
49a9b07e 671 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 672}
2d3ad1f4 673EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 674
42bdf991
MT		 675static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
676{
677 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
678 !vcpu->guest_xcr0_loaded) {
679 /* kvm_set_xcr() also depends on this */
680 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
681 vcpu->guest_xcr0_loaded = 1;
682 }
683}
684
685static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
686{
687 if (vcpu->guest_xcr0_loaded) {
688 if (vcpu->arch.xcr0 != host_xcr0)
689 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
690 vcpu->guest_xcr0_loaded = 0;
691 }
692}
693
69b0049a 694static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 695{
56c103ec
LJ		 696 u64 xcr0 = xcr;
697 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 698 u64 valid_bits;
2acf923e
DC		 699
700 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
701 if (index != XCR_XFEATURE_ENABLED_MASK)
702 return 1;
d91cab78 703 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 704 return 1;
d91cab78 705 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 706 return 1;
46c34cb0
PB		 707
708 /*
709 * Do not allow the guest to set bits that we do not support
710 * saving. However, xcr0 bit 0 is always set, even if the
711 * emulated CPU does not support XSAVE (see fx_init).
712 */
d91cab78 713 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 714 if (xcr0 & ~valid_bits)
2acf923e 715 return 1;
46c34cb0 716
d91cab78
DH		 717 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
718 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 719 return 1;
720
d91cab78
DH		 721 if (xcr0 & XFEATURE_MASK_AVX512) {
722 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 723 return 1;
d91cab78 724 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 725 return 1;
726 }
2acf923e 727 vcpu->arch.xcr0 = xcr0;
56c103ec 728
d91cab78 729 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 730 kvm_update_cpuid(vcpu);
2acf923e
DC		 731 return 0;
732}
733
734int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
735{
764bcbc5
Z		 736 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
737 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 738 kvm_inject_gp(vcpu, 0);
739 return 1;
740 }
741 return 0;
742}
743EXPORT_SYMBOL_GPL(kvm_set_xcr);
744
a83b29c6 745int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 746{
fc78f519 747 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 748 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 749 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 750
0f12244f
GN		 751 if (cr4 & CR4_RESERVED_BITS)
752 return 1;
a03490ed 753
2acf923e
DC		 754 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
755 return 1;
756
c68b734f
YW		 757 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
758 return 1;
759
97ec8c06
FW		 760 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
761 return 1;
762
afcbf13f 763 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 764 return 1;
765
b9baba86
HH		 766 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
767 return 1;
768
a03490ed 769 if (is_long_mode(vcpu)) {
0f12244f
GN		 770 if (!(cr4 & X86_CR4_PAE))
771 return 1;
a2edf57f
AK		 772 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
773 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 774 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
775 kvm_read_cr3(vcpu)))
0f12244f
GN		 776 return 1;
777
ad756a16
MJ		 778 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
779 if (!guest_cpuid_has_pcid(vcpu))
780 return 1;
781
782 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
783 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
784 return 1;
785 }
786
5e1746d6 787 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 788 return 1;
a03490ed 789
ad756a16
MJ		 790 if (((cr4 ^ old_cr4) & pdptr_bits) ||
791 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 792 kvm_mmu_reset_context(vcpu);
0f12244f 793
b9baba86 794 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 795 kvm_update_cpuid(vcpu);
2acf923e 796
0f12244f
GN		 797 return 0;
798}
2d3ad1f4 799EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 800
2390218b 801int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 802{
ac146235 803#ifdef CONFIG_X86_64
9d88fca7 804 cr3 &= ~CR3_PCID_INVD;
ac146235 805#endif
9d88fca7 806
9f8fe504 807 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 808 kvm_mmu_sync_roots(vcpu);
77c3913b 809 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 810 return 0;
d835dfec
AK		 811 }
812
a03490ed 813 if (is_long_mode(vcpu)) {
d9f89b88
JK		 814 if (cr3 & CR3_L_MODE_RESERVED_BITS)
815 return 1;
816 } else if (is_pae(vcpu) && is_paging(vcpu) &&
817 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 818 return 1;
a03490ed 819
0f12244f 820 vcpu->arch.cr3 = cr3;
aff48baa 821 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 822 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 823 return 0;
824}
2d3ad1f4 825EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 826
eea1cff9 827int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 828{
0f12244f
GN		 829 if (cr8 & CR8_RESERVED_BITS)
830 return 1;
35754c98 831 if (lapic_in_kernel(vcpu))
a03490ed
CO		 832 kvm_lapic_set_tpr(vcpu, cr8);
833 else
ad312c7c 834 vcpu->arch.cr8 = cr8;
0f12244f
GN		 835 return 0;
836}
2d3ad1f4 837EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 838
2d3ad1f4 839unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 840{
35754c98 841 if (lapic_in_kernel(vcpu))
a03490ed
CO		 842 return kvm_lapic_get_cr8(vcpu);
843 else
ad312c7c 844 return vcpu->arch.cr8;
a03490ed 845}
2d3ad1f4 846EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 847
ae561ede
NA		 848static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
849{
850 int i;
851
852 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
853 for (i = 0; i < KVM_NR_DB_REGS; i++)
854 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
855 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
856 }
857}
858
73aaf249
JK		 859static void kvm_update_dr6(struct kvm_vcpu *vcpu)
860{
861 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
862 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
863}
864
c8639010
JK		 865static void kvm_update_dr7(struct kvm_vcpu *vcpu)
866{
867 unsigned long dr7;
868
869 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
870 dr7 = vcpu->arch.guest_debug_dr7;
871 else
872 dr7 = vcpu->arch.dr7;
873 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 874 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
875 if (dr7 & DR7_BP_EN_MASK)
876 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 877}
878
6f43ed01
NA		 879static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
880{
881 u64 fixed = DR6_FIXED_1;
882
883 if (!guest_cpuid_has_rtm(vcpu))
884 fixed |= DR6_RTM;
885 return fixed;
886}
887
338dbc97 888static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 889{
890 switch (dr) {
891 case 0 ... 3:
892 vcpu->arch.db[dr] = val;
893 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
894 vcpu->arch.eff_db[dr] = val;
895 break;
896 case 4:
020df079
GN		 897 /* fall through */
898 case 6:
338dbc97
GN		 899 if (val & 0xffffffff00000000ULL)
900 return -1; /* #GP */
6f43ed01 901 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 902 kvm_update_dr6(vcpu);
020df079
GN		 903 break;
904 case 5:
020df079
GN		 905 /* fall through */
906 default: /* 7 */
338dbc97
GN		 907 if (val & 0xffffffff00000000ULL)
908 return -1; /* #GP */
020df079 909 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 910 kvm_update_dr7(vcpu);
020df079
GN		 911 break;
912 }
913
914 return 0;
915}
338dbc97
GN		 916
917int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
918{
16f8a6f9 919 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 920 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 921 return 1;
922 }
923 return 0;
338dbc97 924}
020df079
GN		 925EXPORT_SYMBOL_GPL(kvm_set_dr);
926
16f8a6f9 927int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 928{
929 switch (dr) {
930 case 0 ... 3:
931 *val = vcpu->arch.db[dr];
932 break;
933 case 4:
020df079
GN		 934 /* fall through */
935 case 6:
73aaf249
JK		 936 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
937 *val = vcpu->arch.dr6;
938 else
939 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 940 break;
941 case 5:
020df079
GN		 942 /* fall through */
943 default: /* 7 */
944 *val = vcpu->arch.dr7;
945 break;
946 }
338dbc97
GN		 947 return 0;
948}
020df079
GN		 949EXPORT_SYMBOL_GPL(kvm_get_dr);
950
022cd0e8
AK		 951bool kvm_rdpmc(struct kvm_vcpu *vcpu)
952{
953 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
954 u64 data;
955 int err;
956
c6702c9d 957 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 958 if (err)
959 return err;
960 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
961 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
962 return err;
963}
964EXPORT_SYMBOL_GPL(kvm_rdpmc);
965
043405e1
CO		 966/*
967 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
968 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
969 *
970 * This list is modified at module load time to reflect the
e3267cbb 971 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 972 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
973 * may depend on host virtualization features rather than host cpu features.
043405e1 974 */
e3267cbb 975
043405e1
CO		 976static u32 msrs_to_save[] = {
977 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 978 MSR_STAR,
043405e1
CO		 979#ifdef CONFIG_X86_64
980 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
981#endif
b3897a49 982 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 983 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 984};
985
986static unsigned num_msrs_to_save;
987
62ef68bb
PB		 988static u32 emulated_msrs[] = {
989 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
990 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
991 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
992 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 993 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
994 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 995 HV_X64_MSR_RESET,
11c4b1ca 996 HV_X64_MSR_VP_INDEX,
9eec50b8 997 HV_X64_MSR_VP_RUNTIME,
5c919412 998 HV_X64_MSR_SCONTROL,
1f4b34f8 999 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 1000 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1001 MSR_KVM_PV_EOI_EN,
1002
ba904635 1003 MSR_IA32_TSC_ADJUST,
a3e06bbe 1004 MSR_IA32_TSCDEADLINE,
043405e1 1005 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1006 MSR_IA32_MCG_STATUS,
1007 MSR_IA32_MCG_CTL,
c45dcc71 1008 MSR_IA32_MCG_EXT_CTL,
64d60670 1009 MSR_IA32_SMBASE,
db2336a8
KH		 1010 MSR_PLATFORM_INFO,
1011 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1012};
1013
62ef68bb
PB		 1014static unsigned num_emulated_msrs;
1015
384bb783 1016bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1017{
b69e8cae 1018 if (efer & efer_reserved_bits)
384bb783 1019 return false;
15c4a640 1020
1b2fd70c
AG		 1021 if (efer & EFER_FFXSR) {
1022 struct kvm_cpuid_entry2 *feat;
1023
1024 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1025 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 1026 return false;
1b2fd70c
AG		 1027 }
1028
d8017474
AG		 1029 if (efer & EFER_SVME) {
1030 struct kvm_cpuid_entry2 *feat;
1031
1032 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1033 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1034 return false;
d8017474
AG		 1035 }
1036
384bb783
JK		 1037 return true;
1038}
1039EXPORT_SYMBOL_GPL(kvm_valid_efer);
1040
1041static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1042{
1043 u64 old_efer = vcpu->arch.efer;
1044
1045 if (!kvm_valid_efer(vcpu, efer))
1046 return 1;
1047
1048 if (is_paging(vcpu)
1049 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1050 return 1;
1051
15c4a640 1052 efer &= ~EFER_LMA;
f6801dff 1053 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1054
a3d204e2
SY		 1055 kvm_x86_ops->set_efer(vcpu, efer);
1056
aad82703
SY		 1057 /* Update reserved bits */
1058 if ((efer ^ old_efer) & EFER_NX)
1059 kvm_mmu_reset_context(vcpu);
1060
b69e8cae 1061 return 0;
15c4a640
CO		 1062}
1063
f2b4b7dd
JR		 1064void kvm_enable_efer_bits(u64 mask)
1065{
1066 efer_reserved_bits &= ~mask;
1067}
1068EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1069
15c4a640
CO		 1070/*
1071 * Writes msr value into into the appropriate "register".
1072 * Returns 0 on success, non-0 otherwise.
1073 * Assumes vcpu_load() was already called.
1074 */
8fe8ab46 1075int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1076{
854e8bb1
NA		 1077 switch (msr->index) {
1078 case MSR_FS_BASE:
1079 case MSR_GS_BASE:
1080 case MSR_KERNEL_GS_BASE:
1081 case MSR_CSTAR:
1082 case MSR_LSTAR:
1083 if (is_noncanonical_address(msr->data))
1084 return 1;
1085 break;
1086 case MSR_IA32_SYSENTER_EIP:
1087 case MSR_IA32_SYSENTER_ESP:
1088 /*
1089 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1090 * non-canonical address is written on Intel but not on
1091 * AMD (which ignores the top 32-bits, because it does
1092 * not implement 64-bit SYSENTER).
1093 *
1094 * 64-bit code should hence be able to write a non-canonical
1095 * value on AMD. Making the address canonical ensures that
1096 * vmentry does not fail on Intel after writing a non-canonical
1097 * value, and that something deterministic happens if the guest
1098 * invokes 64-bit SYSENTER.
1099 */
1100 msr->data = get_canonical(msr->data);
1101 }
8fe8ab46 1102 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1103}
854e8bb1 1104EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1105
313a3dc7
CO		 1106/*
1107 * Adapt set_msr() to msr_io()'s calling convention
1108 */
609e36d3
PB		 1109static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1110{
1111 struct msr_data msr;
1112 int r;
1113
1114 msr.index = index;
1115 msr.host_initiated = true;
1116 r = kvm_get_msr(vcpu, &msr);
1117 if (r)
1118 return r;
1119
1120 *data = msr.data;
1121 return 0;
1122}
1123
313a3dc7
CO		 1124static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1125{
8fe8ab46
WA		 1126 struct msr_data msr;
1127
1128 msr.data = *data;
1129 msr.index = index;
1130 msr.host_initiated = true;
1131 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1132}
1133
16e8d74d
MT		 1134#ifdef CONFIG_X86_64
1135struct pvclock_gtod_data {
1136 seqcount_t seq;
1137
1138 struct { /* extract of a clocksource struct */
1139 int vclock_mode;
a5a1d1c2
TG		 1140 u64 cycle_last;
1141 u64 mask;
16e8d74d
MT		 1142 u32 mult;
1143 u32 shift;
1144 } clock;
1145
cbcf2dd3
TG		 1146 u64 boot_ns;
1147 u64 nsec_base;
55dd00a7 1148 u64 wall_time_sec;
16e8d74d
MT		 1149};
1150
1151static struct pvclock_gtod_data pvclock_gtod_data;
1152
1153static void update_pvclock_gtod(struct timekeeper *tk)
1154{
1155 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1156 u64 boot_ns;
1157
876e7881 1158 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1159
1160 write_seqcount_begin(&vdata->seq);
1161
1162 /* copy pvclock gtod data */
876e7881
PZ		 1163 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1164 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1165 vdata->clock.mask = tk->tkr_mono.mask;
1166 vdata->clock.mult = tk->tkr_mono.mult;
1167 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1168
cbcf2dd3 1169 vdata->boot_ns = boot_ns;
876e7881 1170 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1171
55dd00a7
MT		 1172 vdata->wall_time_sec = tk->xtime_sec;
1173
16e8d74d
MT		 1174 write_seqcount_end(&vdata->seq);
1175}
1176#endif
1177
bab5bb39
NK		 1178void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1179{
1180 /*
1181 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1182 * vcpu_enter_guest. This function is only called from
1183 * the physical CPU that is running vcpu.
1184 */
1185 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1186}
16e8d74d 1187
18068523
GOC		 1188static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1189{
9ed3c444
AK		 1190 int version;
1191 int r;
50d0a0f9 1192 struct pvclock_wall_clock wc;
87aeb54f 1193 struct timespec64 boot;
18068523
GOC		 1194
1195 if (!wall_clock)
1196 return;
1197
9ed3c444
AK		 1198 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1199 if (r)
1200 return;
1201
1202 if (version & 1)
1203 ++version; /* first time write, random junk */
1204
1205 ++version;
18068523 1206
1dab1345
NK		 1207 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1208 return;
18068523 1209
50d0a0f9
GH		 1210 /*
1211 * The guest calculates current wall clock time by adding
34c238a1 1212 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1213 * wall clock specified here. guest system time equals host
1214 * system time for us, thus we must fill in host boot time here.
1215 */
87aeb54f 1216 getboottime64(&boot);
50d0a0f9 1217
4b648665 1218 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1219 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1220 boot = timespec64_sub(boot, ts);
4b648665 1221 }
87aeb54f 1222 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1223 wc.nsec = boot.tv_nsec;
1224 wc.version = version;
18068523
GOC		 1225
1226 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1227
1228 version++;
1229 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1230}
1231
50d0a0f9
GH		 1232static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1233{
b51012de
PB		 1234 do_shl32_div32(dividend, divisor);
1235 return dividend;
50d0a0f9
GH		 1236}
1237
3ae13faa 1238static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1239 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1240{
5f4e3f88 1241 uint64_t scaled64;
50d0a0f9
GH		 1242 int32_t shift = 0;
1243 uint64_t tps64;
1244 uint32_t tps32;
1245
3ae13faa
PB		 1246 tps64 = base_hz;
1247 scaled64 = scaled_hz;
50933623 1248 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1249 tps64 >>= 1;
1250 shift--;
1251 }
1252
1253 tps32 = (uint32_t)tps64;
50933623
JK		 1254 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1255 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1256 scaled64 >>= 1;
1257 else
1258 tps32 <<= 1;
50d0a0f9
GH		 1259 shift++;
1260 }
1261
5f4e3f88
ZA		 1262 *pshift = shift;
1263 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1264
3ae13faa
PB		 1265 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1266 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1267}
1268
d828199e 1269#ifdef CONFIG_X86_64
16e8d74d 1270static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1271#endif
16e8d74d 1272
c8076604 1273static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1274static unsigned long max_tsc_khz;
c8076604 1275
cc578287 1276static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1277{
cc578287
ZA		 1278 u64 v = (u64)khz * (1000000 + ppm);
1279 do_div(v, 1000000);
1280 return v;
1e993611
JR		 1281}
1282
381d585c
HZ		 1283static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1284{
1285 u64 ratio;
1286
1287 /* Guest TSC same frequency as host TSC? */
1288 if (!scale) {
1289 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1290 return 0;
1291 }
1292
1293 /* TSC scaling supported? */
1294 if (!kvm_has_tsc_control) {
1295 if (user_tsc_khz > tsc_khz) {
1296 vcpu->arch.tsc_catchup = 1;
1297 vcpu->arch.tsc_always_catchup = 1;
1298 return 0;
1299 } else {
1300 WARN(1, "user requested TSC rate below hardware speed\n");
1301 return -1;
1302 }
1303 }
1304
1305 /* TSC scaling required - calculate ratio */
1306 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1307 user_tsc_khz, tsc_khz);
1308
1309 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1310 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1311 user_tsc_khz);
1312 return -1;
1313 }
1314
1315 vcpu->arch.tsc_scaling_ratio = ratio;
1316 return 0;
1317}
1318
4941b8cb 1319static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1320{
cc578287
ZA		 1321 u32 thresh_lo, thresh_hi;
1322 int use_scaling = 0;
217fc9cf 1323
03ba32ca 1324 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1325 if (user_tsc_khz == 0) {
ad721883
HZ		 1326 /* set tsc_scaling_ratio to a safe value */
1327 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1328 return -1;
ad721883 1329 }
03ba32ca 1330
c285545f 1331 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1332 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1333 &vcpu->arch.virtual_tsc_shift,
1334 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1335 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1336
1337 /*
1338 * Compute the variation in TSC rate which is acceptable
1339 * within the range of tolerance and decide if the
1340 * rate being applied is within that bounds of the hardware
1341 * rate. If so, no scaling or compensation need be done.
1342 */
1343 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1344 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1345 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1346 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1347 use_scaling = 1;
1348 }
4941b8cb 1349 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1350}
1351
1352static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1353{
e26101b1 1354 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1355 vcpu->arch.virtual_tsc_mult,
1356 vcpu->arch.virtual_tsc_shift);
e26101b1 1357 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1358 return tsc;
1359}
1360
69b0049a 1361static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1362{
1363#ifdef CONFIG_X86_64
1364 bool vcpus_matched;
b48aa97e
MT		 1365 struct kvm_arch *ka = &vcpu->kvm->arch;
1366 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1367
1368 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1369 atomic_read(&vcpu->kvm->online_vcpus));
1370
7f187922
MT		 1371 /*
1372 * Once the masterclock is enabled, always perform request in
1373 * order to update it.
1374 *
1375 * In order to enable masterclock, the host clocksource must be TSC
1376 * and the vcpus need to have matched TSCs. When that happens,
1377 * perform request to enable masterclock.
1378 */
1379 if (ka->use_master_clock ||
1380 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1381 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1382
1383 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1384 atomic_read(&vcpu->kvm->online_vcpus),
1385 ka->use_master_clock, gtod->clock.vclock_mode);
1386#endif
1387}
1388
ba904635
WA		 1389static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1390{
3e3f5026 1391 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1392 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1393}
1394
35181e86
HZ		 1395/*
1396 * Multiply tsc by a fixed point number represented by ratio.
1397 *
1398 * The most significant 64-N bits (mult) of ratio represent the
1399 * integral part of the fixed point number; the remaining N bits
1400 * (frac) represent the fractional part, ie. ratio represents a fixed
1401 * point number (mult + frac * 2^(-N)).
1402 *
1403 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1404 */
1405static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1406{
1407 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1408}
1409
1410u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1411{
1412 u64 _tsc = tsc;
1413 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1414
1415 if (ratio != kvm_default_tsc_scaling_ratio)
1416 _tsc = __scale_tsc(ratio, tsc);
1417
1418 return _tsc;
1419}
1420EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1421
07c1419a
HZ		 1422static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1423{
1424 u64 tsc;
1425
1426 tsc = kvm_scale_tsc(vcpu, rdtsc());
1427
1428 return target_tsc - tsc;
1429}
1430
4ba76538
HZ		 1431u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1432{
ea26e4ec 1433 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1434}
1435EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1436
a545ab6a
LC		 1437static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1438{
1439 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1440 vcpu->arch.tsc_offset = offset;
1441}
1442
8fe8ab46 1443void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1444{
1445 struct kvm *kvm = vcpu->kvm;
f38e098f 1446 u64 offset, ns, elapsed;
99e3e30a 1447 unsigned long flags;
b48aa97e 1448 bool matched;
0d3da0d2 1449 bool already_matched;
8fe8ab46 1450 u64 data = msr->data;
c5e8ec8e 1451 bool synchronizing = false;
99e3e30a 1452
038f8c11 1453 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1454 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1455 ns = ktime_get_boot_ns();
f38e098f 1456 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1457
03ba32ca 1458 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1459 if (data == 0 && msr->host_initiated) {
1460 /*
1461 * detection of vcpu initialization -- need to sync
1462 * with other vCPUs. This particularly helps to keep
1463 * kvm_clock stable after CPU hotplug
1464 */
1465 synchronizing = true;
1466 } else {
1467 u64 tsc_exp = kvm->arch.last_tsc_write +
1468 nsec_to_cycles(vcpu, elapsed);
1469 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1470 /*
1471 * Special case: TSC write with a small delta (1 second)
1472 * of virtual cycle time against real time is
1473 * interpreted as an attempt to synchronize the CPU.
1474 */
1475 synchronizing = data < tsc_exp + tsc_hz &&
1476 data + tsc_hz > tsc_exp;
1477 }
c5e8ec8e 1478 }
f38e098f
ZA		 1479
1480 /*
5d3cb0f6
ZA		 1481 * For a reliable TSC, we can match TSC offsets, and for an unstable
1482 * TSC, we add elapsed time in this computation. We could let the
1483 * compensation code attempt to catch up if we fall behind, but
1484 * it's better to try to match offsets from the beginning.
1485 */
c5e8ec8e 1486 if (synchronizing &&
5d3cb0f6 1487 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1488 if (!check_tsc_unstable()) {
e26101b1 1489 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1490 pr_debug("kvm: matched tsc offset for %llu\n", data);
1491 } else {
857e4099 1492 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1493 data += delta;
07c1419a 1494 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1495 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1496 }
b48aa97e 1497 matched = true;
0d3da0d2 1498 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1499 } else {
1500 /*
1501 * We split periods of matched TSC writes into generations.
1502 * For each generation, we track the original measured
1503 * nanosecond time, offset, and write, so if TSCs are in
1504 * sync, we can match exact offset, and if not, we can match
4a969980 1505 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1506 *
1507 * These values are tracked in kvm->arch.cur_xxx variables.
1508 */
1509 kvm->arch.cur_tsc_generation++;
1510 kvm->arch.cur_tsc_nsec = ns;
1511 kvm->arch.cur_tsc_write = data;
1512 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1513 matched = false;
0d3da0d2 1514 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1515 kvm->arch.cur_tsc_generation, data);
f38e098f 1516 }
e26101b1
ZA		 1517
1518 /*
1519 * We also track th most recent recorded KHZ, write and time to
1520 * allow the matching interval to be extended at each write.
1521 */
f38e098f
ZA		 1522 kvm->arch.last_tsc_nsec = ns;
1523 kvm->arch.last_tsc_write = data;
5d3cb0f6 1524 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1525
b183aa58 1526 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1527
1528 /* Keep track of which generation this VCPU has synchronized to */
1529 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1530 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1531 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1532
ba904635
WA		 1533 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1534 update_ia32_tsc_adjust_msr(vcpu, offset);
a545ab6a 1535 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1536 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1537
1538 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1539 if (!matched) {
b48aa97e 1540 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1541 } else if (!already_matched) {
1542 kvm->arch.nr_vcpus_matched_tsc++;
1543 }
b48aa97e
MT		 1544
1545 kvm_track_tsc_matching(vcpu);
1546 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1547}
e26101b1 1548
99e3e30a
ZA		 1549EXPORT_SYMBOL_GPL(kvm_write_tsc);
1550
58ea6767
HZ		 1551static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1552 s64 adjustment)
1553{
ea26e4ec 1554 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1555}
1556
1557static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1558{
1559 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1560 WARN_ON(adjustment < 0);
1561 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1562 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1563}
1564
d828199e
MT		 1565#ifdef CONFIG_X86_64
1566
a5a1d1c2 1567static u64 read_tsc(void)
d828199e 1568{
a5a1d1c2 1569 u64 ret = (u64)rdtsc_ordered();
03b9730b 1570 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1571
1572 if (likely(ret >= last))
1573 return ret;
1574
1575 /*
1576 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1577 * predictable (it's just a function of time and the likely is
d828199e
MT		 1578 * very likely) and there's a data dependence, so force GCC
1579 * to generate a branch instead. I don't barrier() because
1580 * we don't actually need a barrier, and if this function
1581 * ever gets inlined it will generate worse code.
1582 */
1583 asm volatile ("");
1584 return last;
1585}
1586
a5a1d1c2 1587static inline u64 vgettsc(u64 *cycle_now)
d828199e
MT		 1588{
1589 long v;
1590 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1591
1592 *cycle_now = read_tsc();
1593
1594 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1595 return v * gtod->clock.mult;
1596}
1597
a5a1d1c2 1598static int do_monotonic_boot(s64 *t, u64 *cycle_now)
d828199e 1599{
cbcf2dd3 1600 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1601 unsigned long seq;
d828199e 1602 int mode;
cbcf2dd3 1603 u64 ns;
d828199e 1604
d828199e
MT		 1605 do {
1606 seq = read_seqcount_begin(&gtod->seq);
1607 mode = gtod->clock.vclock_mode;
cbcf2dd3 1608 ns = gtod->nsec_base;
d828199e
MT		 1609 ns += vgettsc(cycle_now);
1610 ns >>= gtod->clock.shift;
cbcf2dd3 1611 ns += gtod->boot_ns;
d828199e 1612 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1613 *t = ns;
d828199e
MT		 1614
1615 return mode;
1616}
1617
55dd00a7
MT		 1618static int do_realtime(struct timespec *ts, u64 *cycle_now)
1619{
1620 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1621 unsigned long seq;
1622 int mode;
1623 u64 ns;
1624
1625 do {
1626 seq = read_seqcount_begin(&gtod->seq);
1627 mode = gtod->clock.vclock_mode;
1628 ts->tv_sec = gtod->wall_time_sec;
1629 ns = gtod->nsec_base;
1630 ns += vgettsc(cycle_now);
1631 ns >>= gtod->clock.shift;
1632 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1633
1634 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1635 ts->tv_nsec = ns;
1636
1637 return mode;
1638}
1639
d828199e 1640/* returns true if host is using tsc clocksource */
a5a1d1c2 1641static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
d828199e 1642{
d828199e
MT		 1643 /* checked again under seqlock below */
1644 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1645 return false;
1646
cbcf2dd3 1647 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e 1648}
55dd00a7
MT		 1649
1650/* returns true if host is using tsc clocksource */
1651static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1652 u64 *cycle_now)
1653{
1654 /* checked again under seqlock below */
1655 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1656 return false;
1657
1658 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1659}
d828199e
MT		 1660#endif
1661
1662/*
1663 *
b48aa97e
MT		 1664 * Assuming a stable TSC across physical CPUS, and a stable TSC
1665 * across virtual CPUs, the following condition is possible.
1666 * Each numbered line represents an event visible to both
d828199e
MT		 1667 * CPUs at the next numbered event.
1668 *
1669 * "timespecX" represents host monotonic time. "tscX" represents
1670 * RDTSC value.
1671 *
1672 * VCPU0 on CPU0 | VCPU1 on CPU1
1673 *
1674 * 1. read timespec0,tsc0
1675 * 2. | timespec1 = timespec0 + N
1676 * | tsc1 = tsc0 + M
1677 * 3. transition to guest | transition to guest
1678 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1679 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1680 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1681 *
1682 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1683 *
1684 * - ret0 < ret1
1685 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1686 * ...
1687 * - 0 < N - M => M < N
1688 *
1689 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1690 * always the case (the difference between two distinct xtime instances
1691 * might be smaller then the difference between corresponding TSC reads,
1692 * when updating guest vcpus pvclock areas).
1693 *
1694 * To avoid that problem, do not allow visibility of distinct
1695 * system_timestamp/tsc_timestamp values simultaneously: use a master
1696 * copy of host monotonic time values. Update that master copy
1697 * in lockstep.
1698 *
b48aa97e 1699 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1700 *
1701 */
1702
1703static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1704{
1705#ifdef CONFIG_X86_64
1706 struct kvm_arch *ka = &kvm->arch;
1707 int vclock_mode;
b48aa97e
MT		 1708 bool host_tsc_clocksource, vcpus_matched;
1709
1710 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1711 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1712
1713 /*
1714 * If the host uses TSC clock, then passthrough TSC as stable
1715 * to the guest.
1716 */
b48aa97e 1717 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1718 &ka->master_kernel_ns,
1719 &ka->master_cycle_now);
1720
16a96021 1721 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1722 && !backwards_tsc_observed
1723 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1724
d828199e
MT		 1725 if (ka->use_master_clock)
1726 atomic_set(&kvm_guest_has_master_clock, 1);
1727
1728 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1729 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1730 vcpus_matched);
d828199e
MT		 1731#endif
1732}
1733
2860c4b1
PB		 1734void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1735{
1736 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1737}
1738
2e762ff7
MT		 1739static void kvm_gen_update_masterclock(struct kvm *kvm)
1740{
1741#ifdef CONFIG_X86_64
1742 int i;
1743 struct kvm_vcpu *vcpu;
1744 struct kvm_arch *ka = &kvm->arch;
1745
1746 spin_lock(&ka->pvclock_gtod_sync_lock);
1747 kvm_make_mclock_inprogress_request(kvm);
1748 /* no guest entries from this point */
1749 pvclock_update_vm_gtod_copy(kvm);
1750
1751 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1752 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1753
1754 /* guest entries allowed */
1755 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1756 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1757
1758 spin_unlock(&ka->pvclock_gtod_sync_lock);
1759#endif
1760}
1761
e891a32e 1762u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1763{
108b249c 1764 struct kvm_arch *ka = &kvm->arch;
8b953440 1765 struct pvclock_vcpu_time_info hv_clock;
108b249c 1766
8b953440
PB		 1767 spin_lock(&ka->pvclock_gtod_sync_lock);
1768 if (!ka->use_master_clock) {
1769 spin_unlock(&ka->pvclock_gtod_sync_lock);
1770 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1771 }
1772
8b953440
PB		 1773 hv_clock.tsc_timestamp = ka->master_cycle_now;
1774 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1775 spin_unlock(&ka->pvclock_gtod_sync_lock);
1776
1777 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1778 &hv_clock.tsc_shift,
1779 &hv_clock.tsc_to_system_mul);
1780 return __pvclock_read_cycles(&hv_clock, rdtsc());
108b249c
PB		 1781}
1782
0d6dd2ff
PB		 1783static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1784{
1785 struct kvm_vcpu_arch *vcpu = &v->arch;
1786 struct pvclock_vcpu_time_info guest_hv_clock;
1787
4e335d9e 1788 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1789 &guest_hv_clock, sizeof(guest_hv_clock))))
1790 return;
1791
1792 /* This VCPU is paused, but it's legal for a guest to read another
1793 * VCPU's kvmclock, so we really have to follow the specification where
1794 * it says that version is odd if data is being modified, and even after
1795 * it is consistent.
1796 *
1797 * Version field updates must be kept separate. This is because
1798 * kvm_write_guest_cached might use a "rep movs" instruction, and
1799 * writes within a string instruction are weakly ordered. So there
1800 * are three writes overall.
1801 *
1802 * As a small optimization, only write the version field in the first
1803 * and third write. The vcpu->pv_time cache is still valid, because the
1804 * version field is the first in the struct.
1805 */
1806 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1807
1808 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1809 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1810 &vcpu->hv_clock,
1811 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1812
1813 smp_wmb();
1814
1815 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1816 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1817
1818 if (vcpu->pvclock_set_guest_stopped_request) {
1819 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1820 vcpu->pvclock_set_guest_stopped_request = false;
1821 }
1822
1823 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1824
4e335d9e
PB		 1825 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1826 &vcpu->hv_clock,
1827 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1828
1829 smp_wmb();
1830
1831 vcpu->hv_clock.version++;
4e335d9e
PB		 1832 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1833 &vcpu->hv_clock,
1834 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1835}
1836
34c238a1 1837static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1838{
78db6a50 1839 unsigned long flags, tgt_tsc_khz;
18068523 1840 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1841 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1842 s64 kernel_ns;
d828199e 1843 u64 tsc_timestamp, host_tsc;
51d59c6b 1844 u8 pvclock_flags;
d828199e
MT		 1845 bool use_master_clock;
1846
1847 kernel_ns = 0;
1848 host_tsc = 0;
18068523 1849
d828199e
MT		 1850 /*
1851 * If the host uses TSC clock, then passthrough TSC as stable
1852 * to the guest.
1853 */
1854 spin_lock(&ka->pvclock_gtod_sync_lock);
1855 use_master_clock = ka->use_master_clock;
1856 if (use_master_clock) {
1857 host_tsc = ka->master_cycle_now;
1858 kernel_ns = ka->master_kernel_ns;
1859 }
1860 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1861
1862 /* Keep irq disabled to prevent changes to the clock */
1863 local_irq_save(flags);
78db6a50
PB		 1864 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1865 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1866 local_irq_restore(flags);
1867 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1868 return 1;
1869 }
d828199e 1870 if (!use_master_clock) {
4ea1636b 1871 host_tsc = rdtsc();
108b249c 1872 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1873 }
1874
4ba76538 1875 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1876
c285545f
ZA		 1877 /*
1878 * We may have to catch up the TSC to match elapsed wall clock
1879 * time for two reasons, even if kvmclock is used.
1880 * 1) CPU could have been running below the maximum TSC rate
1881 * 2) Broken TSC compensation resets the base at each VCPU
1882 * entry to avoid unknown leaps of TSC even when running
1883 * again on the same CPU. This may cause apparent elapsed
1884 * time to disappear, and the guest to stand still or run
1885 * very slowly.
1886 */
1887 if (vcpu->tsc_catchup) {
1888 u64 tsc = compute_guest_tsc(v, kernel_ns);
1889 if (tsc > tsc_timestamp) {
f1e2b260 1890 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1891 tsc_timestamp = tsc;
1892 }
50d0a0f9
GH		 1893 }
1894
18068523
GOC		 1895 local_irq_restore(flags);
1896
0d6dd2ff 1897 /* With all the info we got, fill in the values */
18068523 1898
78db6a50
PB		 1899 if (kvm_has_tsc_control)
1900 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1901
1902 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1903 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1904 &vcpu->hv_clock.tsc_shift,
1905 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1906 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1907 }
1908
1d5f066e 1909 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1910 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1911 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1912
d828199e 1913 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 1914 pvclock_flags = 0;
d828199e
MT		 1915 if (use_master_clock)
1916 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1917
78c0337a
MT		 1918 vcpu->hv_clock.flags = pvclock_flags;
1919
095cf55d
PB		 1920 if (vcpu->pv_time_enabled)
1921 kvm_setup_pvclock_page(v);
1922 if (v == kvm_get_vcpu(v->kvm, 0))
1923 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 1924 return 0;
c8076604
GH		 1925}
1926
0061d53d
MT		 1927/*
1928 * kvmclock updates which are isolated to a given vcpu, such as
1929 * vcpu->cpu migration, should not allow system_timestamp from
1930 * the rest of the vcpus to remain static. Otherwise ntp frequency
1931 * correction applies to one vcpu's system_timestamp but not
1932 * the others.
1933 *
1934 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1935 * We need to rate-limit these requests though, as they can
1936 * considerably slow guests that have a large number of vcpus.
1937 * The time for a remote vcpu to update its kvmclock is bound
1938 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1939 */
1940
7e44e449
AJ		 1941#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1942
1943static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1944{
1945 int i;
7e44e449
AJ		 1946 struct delayed_work *dwork = to_delayed_work(work);
1947 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1948 kvmclock_update_work);
1949 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1950 struct kvm_vcpu *vcpu;
1951
1952 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1953 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1954 kvm_vcpu_kick(vcpu);
1955 }
1956}
1957
7e44e449
AJ		 1958static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1959{
1960 struct kvm *kvm = v->kvm;
1961
105b21bb 1962 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1963 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1964 KVMCLOCK_UPDATE_DELAY);
1965}
1966
332967a3
AJ		 1967#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1968
1969static void kvmclock_sync_fn(struct work_struct *work)
1970{
1971 struct delayed_work *dwork = to_delayed_work(work);
1972 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1973 kvmclock_sync_work);
1974 struct kvm *kvm = container_of(ka, struct kvm, arch);
1975
630994b3
MT		 1976 if (!kvmclock_periodic_sync)
1977 return;
1978
332967a3
AJ		 1979 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1980 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1981 KVMCLOCK_SYNC_PERIOD);
1982}
1983
890ca9ae 1984static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1985{
890ca9ae
HY		 1986 u64 mcg_cap = vcpu->arch.mcg_cap;
1987 unsigned bank_num = mcg_cap & 0xff;
1988
15c4a640 1989 switch (msr) {
15c4a640 1990 case MSR_IA32_MCG_STATUS:
890ca9ae 1991 vcpu->arch.mcg_status = data;
15c4a640 1992 break;
c7ac679c 1993 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1994 if (!(mcg_cap & MCG_CTL_P))
1995 return 1;
1996 if (data != 0 && data != ~(u64)0)
1997 return -1;
1998 vcpu->arch.mcg_ctl = data;
1999 break;
2000 default:
2001 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2002 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2003 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2004 /* only 0 or all 1s can be written to IA32_MCi_CTL
2005 * some Linux kernels though clear bit 10 in bank 4 to
2006 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2007 * this to avoid an uncatched #GP in the guest
2008 */
890ca9ae 2009 if ((offset & 0x3) == 0 &&
114be429 2010 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 2011 return -1;
2012 vcpu->arch.mce_banks[offset] = data;
2013 break;
2014 }
2015 return 1;
2016 }
2017 return 0;
2018}
2019
ffde22ac
ES		 2020static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2021{
2022 struct kvm *kvm = vcpu->kvm;
2023 int lm = is_long_mode(vcpu);
2024 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2025 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2026 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2027 : kvm->arch.xen_hvm_config.blob_size_32;
2028 u32 page_num = data & ~PAGE_MASK;
2029 u64 page_addr = data & PAGE_MASK;
2030 u8 *page;
2031 int r;
2032
2033 r = -E2BIG;
2034 if (page_num >= blob_size)
2035 goto out;
2036 r = -ENOMEM;
ff5c2c03
SL		 2037 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2038 if (IS_ERR(page)) {
2039 r = PTR_ERR(page);
ffde22ac 2040 goto out;
ff5c2c03 2041 }
54bf36aa 2042 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2043 goto out_free;
2044 r = 0;
2045out_free:
2046 kfree(page);
2047out:
2048 return r;
2049}
2050
344d9588
GN		 2051static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2052{
2053 gpa_t gpa = data & ~0x3f;
2054
4a969980 2055 /* Bits 2:5 are reserved, Should be zero */
6adba527 2056 if (data & 0x3c)
344d9588
GN		 2057 return 1;
2058
2059 vcpu->arch.apf.msr_val = data;
2060
2061 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2062 kvm_clear_async_pf_completion_queue(vcpu);
2063 kvm_async_pf_hash_reset(vcpu);
2064 return 0;
2065 }
2066
4e335d9e 2067 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2068 sizeof(u32)))
344d9588
GN		 2069 return 1;
2070
6adba527 2071 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2072 kvm_async_pf_wakeup_all(vcpu);
2073 return 0;
2074}
2075
12f9a48f
GC		 2076static void kvmclock_reset(struct kvm_vcpu *vcpu)
2077{
0b79459b 2078 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2079}
2080
c9aaa895
GC		 2081static void record_steal_time(struct kvm_vcpu *vcpu)
2082{
2083 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2084 return;
2085
4e335d9e 2086 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2087 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2088 return;
2089
0b9f6c46
PX		 2090 vcpu->arch.st.steal.preempted = 0;
2091
35f3fae1
WL		 2092 if (vcpu->arch.st.steal.version & 1)
2093 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2094
2095 vcpu->arch.st.steal.version += 1;
2096
4e335d9e 2097 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2098 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2099
2100 smp_wmb();
2101
c54cdf14
LC		 2102 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2103 vcpu->arch.st.last_steal;
2104 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2105
4e335d9e 2106 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2107 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2108
2109 smp_wmb();
2110
2111 vcpu->arch.st.steal.version += 1;
c9aaa895 2112
4e335d9e 2113 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2114 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2115}
2116
8fe8ab46 2117int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2118{
5753785f 2119 bool pr = false;
8fe8ab46
WA		 2120 u32 msr = msr_info->index;
2121 u64 data = msr_info->data;
5753785f 2122
15c4a640 2123 switch (msr) {
2e32b719
BP		 2124 case MSR_AMD64_NB_CFG:
2125 case MSR_IA32_UCODE_REV:
2126 case MSR_IA32_UCODE_WRITE:
2127 case MSR_VM_HSAVE_PA:
2128 case MSR_AMD64_PATCH_LOADER:
2129 case MSR_AMD64_BU_CFG2:
405a353a 2130 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2131 break;
2132
15c4a640 2133 case MSR_EFER:
b69e8cae 2134 return set_efer(vcpu, data);
8f1589d9
AP		 2135 case MSR_K7_HWCR:
2136 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2137 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2138 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2139 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2140 if (data != 0) {
a737f256
CD		 2141 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2142 data);
8f1589d9
AP		 2143 return 1;
2144 }
15c4a640 2145 break;
f7c6d140
AP		 2146 case MSR_FAM10H_MMIO_CONF_BASE:
2147 if (data != 0) {
a737f256
CD		 2148 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2149 "0x%llx\n", data);
f7c6d140
AP		 2150 return 1;
2151 }
15c4a640 2152 break;
b5e2fec0
AG		 2153 case MSR_IA32_DEBUGCTLMSR:
2154 if (!data) {
2155 /* We support the non-activated case already */
2156 break;
2157 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2158 /* Values other than LBR and BTF are vendor-specific,
2159 thus reserved and should throw a #GP */
2160 return 1;
2161 }
a737f256
CD		 2162 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2163 __func__, data);
b5e2fec0 2164 break;
9ba075a6 2165 case 0x200 ... 0x2ff:
ff53604b 2166 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2167 case MSR_IA32_APICBASE:
58cb628d 2168 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2169 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2170 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2171 case MSR_IA32_TSCDEADLINE:
2172 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2173 break;
ba904635
WA		 2174 case MSR_IA32_TSC_ADJUST:
2175 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2176 if (!msr_info->host_initiated) {
d913b904 2177 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2178 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2179 }
2180 vcpu->arch.ia32_tsc_adjust_msr = data;
2181 }
2182 break;
15c4a640 2183 case MSR_IA32_MISC_ENABLE:
ad312c7c 2184 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2185 break;
64d60670
PB		 2186 case MSR_IA32_SMBASE:
2187 if (!msr_info->host_initiated)
2188 return 1;
2189 vcpu->arch.smbase = data;
2190 break;
11c6bffa 2191 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2192 case MSR_KVM_WALL_CLOCK:
2193 vcpu->kvm->arch.wall_clock = data;
2194 kvm_write_wall_clock(vcpu->kvm, data);
2195 break;
11c6bffa 2196 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2197 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2198 struct kvm_arch *ka = &vcpu->kvm->arch;
2199
12f9a48f 2200 kvmclock_reset(vcpu);
18068523 2201
54750f2c
MT		 2202 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2203 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2204
2205 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2206 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2207
2208 ka->boot_vcpu_runs_old_kvmclock = tmp;
2209 }
2210
18068523 2211 vcpu->arch.time = data;
0061d53d 2212 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2213
2214 /* we verify if the enable bit is set... */
2215 if (!(data & 1))
2216 break;
2217
4e335d9e 2218 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2219 &vcpu->arch.pv_time, data & ~1ULL,
2220 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2221 vcpu->arch.pv_time_enabled = false;
2222 else
2223 vcpu->arch.pv_time_enabled = true;
32cad84f 2224
18068523
GOC		 2225 break;
2226 }
344d9588
GN		 2227 case MSR_KVM_ASYNC_PF_EN:
2228 if (kvm_pv_enable_async_pf(vcpu, data))
2229 return 1;
2230 break;
c9aaa895
GC		 2231 case MSR_KVM_STEAL_TIME:
2232
2233 if (unlikely(!sched_info_on()))
2234 return 1;
2235
2236 if (data & KVM_STEAL_RESERVED_MASK)
2237 return 1;
2238
4e335d9e 2239 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2240 data & KVM_STEAL_VALID_BITS,
2241 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2242 return 1;
2243
2244 vcpu->arch.st.msr_val = data;
2245
2246 if (!(data & KVM_MSR_ENABLED))
2247 break;
2248
c9aaa895
GC		 2249 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2250
2251 break;
ae7a2a3f
MT		 2252 case MSR_KVM_PV_EOI_EN:
2253 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2254 return 1;
2255 break;
c9aaa895 2256
890ca9ae
HY		 2257 case MSR_IA32_MCG_CTL:
2258 case MSR_IA32_MCG_STATUS:
81760dcc 2259 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2260 return set_msr_mce(vcpu, msr, data);
71db6023 2261
6912ac32
WH		 2262 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2263 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2264 pr = true; /* fall through */
2265 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2266 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2267 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2268 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2269
2270 if (pr || data != 0)
a737f256
CD		 2271 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2272 "0x%x data 0x%llx\n", msr, data);
5753785f 2273 break;
84e0cefa
JS		 2274 case MSR_K7_CLK_CTL:
2275 /*
2276 * Ignore all writes to this no longer documented MSR.
2277 * Writes are only relevant for old K7 processors,
2278 * all pre-dating SVM, but a recommended workaround from
4a969980 2279 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2280 * affected processor models on the command line, hence
2281 * the need to ignore the workaround.
2282 */
2283 break;
55cd8e5a 2284 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2285 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2286 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2287 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2288 return kvm_hv_set_msr_common(vcpu, msr, data,
2289 msr_info->host_initiated);
91c9c3ed 2290 case MSR_IA32_BBL_CR_CTL3:
2291 /* Drop writes to this legacy MSR -- see rdmsr
2292 * counterpart for further detail.
2293 */
796f4687 2294 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", msr, data);
91c9c3ed 2295 break;
2b036c6b
BO		 2296 case MSR_AMD64_OSVW_ID_LENGTH:
2297 if (!guest_cpuid_has_osvw(vcpu))
2298 return 1;
2299 vcpu->arch.osvw.length = data;
2300 break;
2301 case MSR_AMD64_OSVW_STATUS:
2302 if (!guest_cpuid_has_osvw(vcpu))
2303 return 1;
2304 vcpu->arch.osvw.status = data;
2305 break;
db2336a8
KH		 2306 case MSR_PLATFORM_INFO:
2307 if (!msr_info->host_initiated ||
2308 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2309 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2310 cpuid_fault_enabled(vcpu)))
2311 return 1;
2312 vcpu->arch.msr_platform_info = data;
2313 break;
2314 case MSR_MISC_FEATURES_ENABLES:
2315 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2316 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2317 !supports_cpuid_fault(vcpu)))
2318 return 1;
2319 vcpu->arch.msr_misc_features_enables = data;
2320 break;
15c4a640 2321 default:
ffde22ac
ES		 2322 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2323 return xen_hvm_config(vcpu, data);
c6702c9d 2324 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2325 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2326 if (!ignore_msrs) {
ae0f5499 2327 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2328 msr, data);
ed85c068
AP		 2329 return 1;
2330 } else {
796f4687 2331 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
a737f256 2332 msr, data);
ed85c068
AP		 2333 break;
2334 }
15c4a640
CO		 2335 }
2336 return 0;
2337}
2338EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2339
2340
2341/*
2342 * Reads an msr value (of 'msr_index') into 'pdata'.
2343 * Returns 0 on success, non-0 otherwise.
2344 * Assumes vcpu_load() was already called.
2345 */
609e36d3 2346int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2347{
609e36d3 2348 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2349}
ff651cb6 2350EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2351
890ca9ae 2352static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2353{
2354 u64 data;
890ca9ae
HY		 2355 u64 mcg_cap = vcpu->arch.mcg_cap;
2356 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2357
2358 switch (msr) {
15c4a640
CO		 2359 case MSR_IA32_P5_MC_ADDR:
2360 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2361 data = 0;
2362 break;
15c4a640 2363 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2364 data = vcpu->arch.mcg_cap;
2365 break;
c7ac679c 2366 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2367 if (!(mcg_cap & MCG_CTL_P))
2368 return 1;
2369 data = vcpu->arch.mcg_ctl;
2370 break;
2371 case MSR_IA32_MCG_STATUS:
2372 data = vcpu->arch.mcg_status;
2373 break;
2374 default:
2375 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2376 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2377 u32 offset = msr - MSR_IA32_MC0_CTL;
2378 data = vcpu->arch.mce_banks[offset];
2379 break;
2380 }
2381 return 1;
2382 }
2383 *pdata = data;
2384 return 0;
2385}
2386
609e36d3 2387int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2388{
609e36d3 2389 switch (msr_info->index) {
890ca9ae 2390 case MSR_IA32_PLATFORM_ID:
15c4a640 2391 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2392 case MSR_IA32_DEBUGCTLMSR:
2393 case MSR_IA32_LASTBRANCHFROMIP:
2394 case MSR_IA32_LASTBRANCHTOIP:
2395 case MSR_IA32_LASTINTFROMIP:
2396 case MSR_IA32_LASTINTTOIP:
60af2ecd 2397 case MSR_K8_SYSCFG:
3afb1121
PB		 2398 case MSR_K8_TSEG_ADDR:
2399 case MSR_K8_TSEG_MASK:
60af2ecd 2400 case MSR_K7_HWCR:
61a6bd67 2401 case MSR_VM_HSAVE_PA:
1fdbd48c 2402 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2403 case MSR_AMD64_NB_CFG:
f7c6d140 2404 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2405 case MSR_AMD64_BU_CFG2:
0c2df2a1 2406 case MSR_IA32_PERF_CTL:
405a353a 2407 case MSR_AMD64_DC_CFG:
609e36d3 2408 msr_info->data = 0;
15c4a640 2409 break;
6912ac32
WH		 2410 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2411 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2412 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2413 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2414 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2415 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2416 msr_info->data = 0;
5753785f 2417 break;
742bc670 2418 case MSR_IA32_UCODE_REV:
609e36d3 2419 msr_info->data = 0x100000000ULL;
742bc670 2420 break;
9ba075a6 2421 case MSR_MTRRcap:
9ba075a6 2422 case 0x200 ... 0x2ff:
ff53604b 2423 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2424 case 0xcd: /* fsb frequency */
609e36d3 2425 msr_info->data = 3;
15c4a640 2426 break;
7b914098
JS		 2427 /*
2428 * MSR_EBC_FREQUENCY_ID
2429 * Conservative value valid for even the basic CPU models.
2430 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2431 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2432 * and 266MHz for model 3, or 4. Set Core Clock
2433 * Frequency to System Bus Frequency Ratio to 1 (bits
2434 * 31:24) even though these are only valid for CPU
2435 * models > 2, however guests may end up dividing or
2436 * multiplying by zero otherwise.
2437 */
2438 case MSR_EBC_FREQUENCY_ID:
609e36d3 2439 msr_info->data = 1 << 24;
7b914098 2440 break;
15c4a640 2441 case MSR_IA32_APICBASE:
609e36d3 2442 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2443 break;
0105d1a5 2444 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2445 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2446 break;
a3e06bbe 2447 case MSR_IA32_TSCDEADLINE:
609e36d3 2448 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2449 break;
ba904635 2450 case MSR_IA32_TSC_ADJUST:
609e36d3 2451 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2452 break;
15c4a640 2453 case MSR_IA32_MISC_ENABLE:
609e36d3 2454 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2455 break;
64d60670
PB		 2456 case MSR_IA32_SMBASE:
2457 if (!msr_info->host_initiated)
2458 return 1;
2459 msr_info->data = vcpu->arch.smbase;
15c4a640 2460 break;
847f0ad8
AG		 2461 case MSR_IA32_PERF_STATUS:
2462 /* TSC increment by tick */
609e36d3 2463 msr_info->data = 1000ULL;
847f0ad8 2464 /* CPU multiplier */
b0996ae4 2465 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2466 break;
15c4a640 2467 case MSR_EFER:
609e36d3 2468 msr_info->data = vcpu->arch.efer;
15c4a640 2469 break;
18068523 2470 case MSR_KVM_WALL_CLOCK:
11c6bffa 2471 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2472 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2473 break;
2474 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2475 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2476 msr_info->data = vcpu->arch.time;
18068523 2477 break;
344d9588 2478 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2479 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2480 break;
c9aaa895 2481 case MSR_KVM_STEAL_TIME:
609e36d3 2482 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2483 break;
1d92128f 2484 case MSR_KVM_PV_EOI_EN:
609e36d3 2485 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2486 break;
890ca9ae
HY		 2487 case MSR_IA32_P5_MC_ADDR:
2488 case MSR_IA32_P5_MC_TYPE:
2489 case MSR_IA32_MCG_CAP:
2490 case MSR_IA32_MCG_CTL:
2491 case MSR_IA32_MCG_STATUS:
81760dcc 2492 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2493 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2494 case MSR_K7_CLK_CTL:
2495 /*
2496 * Provide expected ramp-up count for K7. All other
2497 * are set to zero, indicating minimum divisors for
2498 * every field.
2499 *
2500 * This prevents guest kernels on AMD host with CPU
2501 * type 6, model 8 and higher from exploding due to
2502 * the rdmsr failing.
2503 */
609e36d3 2504 msr_info->data = 0x20000000;
84e0cefa 2505 break;
55cd8e5a 2506 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2507 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2508 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2509 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2510 return kvm_hv_get_msr_common(vcpu,
2511 msr_info->index, &msr_info->data);
55cd8e5a 2512 break;
91c9c3ed 2513 case MSR_IA32_BBL_CR_CTL3:
2514 /* This legacy MSR exists but isn't fully documented in current
2515 * silicon. It is however accessed by winxp in very narrow
2516 * scenarios where it sets bit #19, itself documented as
2517 * a "reserved" bit. Best effort attempt to source coherent
2518 * read data here should the balance of the register be
2519 * interpreted by the guest:
2520 *
2521 * L2 cache control register 3: 64GB range, 256KB size,
2522 * enabled, latency 0x1, configured
2523 */
609e36d3 2524 msr_info->data = 0xbe702111;
91c9c3ed 2525 break;
2b036c6b
BO		 2526 case MSR_AMD64_OSVW_ID_LENGTH:
2527 if (!guest_cpuid_has_osvw(vcpu))
2528 return 1;
609e36d3 2529 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2530 break;
2531 case MSR_AMD64_OSVW_STATUS:
2532 if (!guest_cpuid_has_osvw(vcpu))
2533 return 1;
609e36d3 2534 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2535 break;
db2336a8
KH		 2536 case MSR_PLATFORM_INFO:
2537 msr_info->data = vcpu->arch.msr_platform_info;
2538 break;
2539 case MSR_MISC_FEATURES_ENABLES:
2540 msr_info->data = vcpu->arch.msr_misc_features_enables;
2541 break;
15c4a640 2542 default:
c6702c9d 2543 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2544 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2545 if (!ignore_msrs) {
ae0f5499
BD		 2546 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2547 msr_info->index);
ed85c068
AP		 2548 return 1;
2549 } else {
609e36d3
PB		 2550 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2551 msr_info->data = 0;
ed85c068
AP		 2552 }
2553 break;
15c4a640 2554 }
15c4a640
CO		 2555 return 0;
2556}
2557EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2558
313a3dc7
CO		 2559/*
2560 * Read or write a bunch of msrs. All parameters are kernel addresses.
2561 *
2562 * @return number of msrs set successfully.
2563 */
2564static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2565 struct kvm_msr_entry *entries,
2566 int (*do_msr)(struct kvm_vcpu *vcpu,
2567 unsigned index, u64 *data))
2568{
f656ce01 2569 int i, idx;
313a3dc7 2570
f656ce01 2571 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2572 for (i = 0; i < msrs->nmsrs; ++i)
2573 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2574 break;
f656ce01 2575 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2576
313a3dc7
CO		 2577 return i;
2578}
2579
2580/*
2581 * Read or write a bunch of msrs. Parameters are user addresses.
2582 *
2583 * @return number of msrs set successfully.
2584 */
2585static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2586 int (*do_msr)(struct kvm_vcpu *vcpu,
2587 unsigned index, u64 *data),
2588 int writeback)
2589{
2590 struct kvm_msrs msrs;
2591 struct kvm_msr_entry *entries;
2592 int r, n;
2593 unsigned size;
2594
2595 r = -EFAULT;
2596 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2597 goto out;
2598
2599 r = -E2BIG;
2600 if (msrs.nmsrs >= MAX_IO_MSRS)
2601 goto out;
2602
313a3dc7 2603 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2604 entries = memdup_user(user_msrs->entries, size);
2605 if (IS_ERR(entries)) {
2606 r = PTR_ERR(entries);
313a3dc7 2607 goto out;
ff5c2c03 2608 }
313a3dc7
CO		 2609
2610 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2611 if (r < 0)
2612 goto out_free;
2613
2614 r = -EFAULT;
2615 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2616 goto out_free;
2617
2618 r = n;
2619
2620out_free:
7a73c028 2621 kfree(entries);
313a3dc7
CO		 2622out:
2623 return r;
2624}
2625
784aa3d7 2626int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2627{
2628 int r;
2629
2630 switch (ext) {
2631 case KVM_CAP_IRQCHIP:
2632 case KVM_CAP_HLT:
2633 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2634 case KVM_CAP_SET_TSS_ADDR:
07716717 2635 case KVM_CAP_EXT_CPUID:
9c15bb1d 2636 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2637 case KVM_CAP_CLOCKSOURCE:
7837699f 2638 case KVM_CAP_PIT:
a28e4f5a 2639 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2640 case KVM_CAP_MP_STATE:
ed848624 2641 case KVM_CAP_SYNC_MMU:
a355c85c 2642 case KVM_CAP_USER_NMI:
52d939a0 2643 case KVM_CAP_REINJECT_CONTROL:
4925663a 2644 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2645 case KVM_CAP_IOEVENTFD:
f848a5a8 2646 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2647 case KVM_CAP_PIT2:
e9f42757 2648 case KVM_CAP_PIT_STATE2:
b927a3ce 2649 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2650 case KVM_CAP_XEN_HVM:
3cfc3092 2651 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2652 case KVM_CAP_HYPERV:
10388a07 2653 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2654 case KVM_CAP_HYPERV_SPIN:
5c919412 2655 case KVM_CAP_HYPERV_SYNIC:
ab9f4ecb 2656 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2657 case KVM_CAP_DEBUGREGS:
d2be1651 2658 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2659 case KVM_CAP_XSAVE:
344d9588 2660 case KVM_CAP_ASYNC_PF:
92a1f12d 2661 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2662 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2663 case KVM_CAP_READONLY_MEM:
5f66b620 2664 case KVM_CAP_HYPERV_TIME:
100943c5 2665 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2666 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2667 case KVM_CAP_ENABLE_CAP_VM:
2668 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2669 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2670 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2671 case KVM_CAP_IMMEDIATE_EXIT:
018d00d2
ZX		 2672 r = 1;
2673 break;
e3fd9a93
PB		 2674 case KVM_CAP_ADJUST_CLOCK:
2675 r = KVM_CLOCK_TSC_STABLE;
2676 break;
668fffa3
MT		 2677 case KVM_CAP_X86_GUEST_MWAIT:
2678 r = kvm_mwait_in_guest();
2679 break;
6d396b55
PB		 2680 case KVM_CAP_X86_SMM:
2681 /* SMBASE is usually relocated above 1M on modern chipsets,
2682 * and SMM handlers might indeed rely on 4G segment limits,
2683 * so do not report SMM to be available if real mode is
2684 * emulated via vm86 mode. Still, do not go to great lengths
2685 * to avoid userspace's usage of the feature, because it is a
2686 * fringe case that is not enabled except via specific settings
2687 * of the module parameters.
2688 */
2689 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2690 break;
774ead3a
AK		 2691 case KVM_CAP_VAPIC:
2692 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2693 break;
f725230a 2694 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2695 r = KVM_SOFT_MAX_VCPUS;
2696 break;
2697 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2698 r = KVM_MAX_VCPUS;
2699 break;
a988b910 2700 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2701 r = KVM_USER_MEM_SLOTS;
a988b910 2702 break;
a68a6a72
MT		 2703 case KVM_CAP_PV_MMU: /* obsolete */
2704 r = 0;
2f333bcb 2705 break;
890ca9ae
HY		 2706 case KVM_CAP_MCE:
2707 r = KVM_MAX_MCE_BANKS;
2708 break;
2d5b5a66 2709 case KVM_CAP_XCRS:
d366bf7e 2710 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2711 break;
92a1f12d
JR		 2712 case KVM_CAP_TSC_CONTROL:
2713 r = kvm_has_tsc_control;
2714 break;
37131313
RK		 2715 case KVM_CAP_X2APIC_API:
2716 r = KVM_X2APIC_API_VALID_FLAGS;
2717 break;
018d00d2
ZX		 2718 default:
2719 r = 0;
2720 break;
2721 }
2722 return r;
2723
2724}
2725
043405e1
CO		 2726long kvm_arch_dev_ioctl(struct file *filp,
2727 unsigned int ioctl, unsigned long arg)
2728{
2729 void __user *argp = (void __user *)arg;
2730 long r;
2731
2732 switch (ioctl) {
2733 case KVM_GET_MSR_INDEX_LIST: {
2734 struct kvm_msr_list __user *user_msr_list = argp;
2735 struct kvm_msr_list msr_list;
2736 unsigned n;
2737
2738 r = -EFAULT;
2739 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2740 goto out;
2741 n = msr_list.nmsrs;
62ef68bb 2742 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2743 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2744 goto out;
2745 r = -E2BIG;
e125e7b6 2746 if (n < msr_list.nmsrs)
043405e1
CO		 2747 goto out;
2748 r = -EFAULT;
2749 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2750 num_msrs_to_save * sizeof(u32)))
2751 goto out;
e125e7b6 2752 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2753 &emulated_msrs,
62ef68bb 2754 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2755 goto out;
2756 r = 0;
2757 break;
2758 }
9c15bb1d
BP		 2759 case KVM_GET_SUPPORTED_CPUID:
2760 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2761 struct kvm_cpuid2 __user *cpuid_arg = argp;
2762 struct kvm_cpuid2 cpuid;
2763
2764 r = -EFAULT;
2765 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2766 goto out;
9c15bb1d
BP		 2767
2768 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2769 ioctl);
674eea0f
AK		 2770 if (r)
2771 goto out;
2772
2773 r = -EFAULT;
2774 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2775 goto out;
2776 r = 0;
2777 break;
2778 }
890ca9ae 2779 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2780 r = -EFAULT;
c45dcc71
AR		 2781 if (copy_to_user(argp, &kvm_mce_cap_supported,
2782 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2783 goto out;
2784 r = 0;
2785 break;
2786 }
043405e1
CO		 2787 default:
2788 r = -EINVAL;
2789 }
2790out:
2791 return r;
2792}
2793
f5f48ee1
SY		 2794static void wbinvd_ipi(void *garbage)
2795{
2796 wbinvd();
2797}
2798
2799static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2800{
e0f0bbc5 2801 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2802}
2803
313a3dc7
CO		 2804void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2805{
f5f48ee1
SY		 2806 /* Address WBINVD may be executed by guest */
2807 if (need_emulate_wbinvd(vcpu)) {
2808 if (kvm_x86_ops->has_wbinvd_exit())
2809 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2810 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2811 smp_call_function_single(vcpu->cpu,
2812 wbinvd_ipi, NULL, 1);
2813 }
2814
313a3dc7 2815 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2816
0dd6a6ed
ZA		 2817 /* Apply any externally detected TSC adjustments (due to suspend) */
2818 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2819 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2820 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2821 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2822 }
8f6055cb 2823
48434c20 2824 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2825 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2826 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2827 if (tsc_delta < 0)
2828 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2829
c285545f 2830 if (check_tsc_unstable()) {
07c1419a 2831 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2832 vcpu->arch.last_guest_tsc);
a545ab6a 2833 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2834 vcpu->arch.tsc_catchup = 1;
c285545f 2835 }
e12c8f36
WL		 2836 if (kvm_lapic_hv_timer_in_use(vcpu) &&
2837 kvm_x86_ops->set_hv_timer(vcpu,
498f8162 2838 kvm_get_lapic_target_expiration_tsc(vcpu)))
e12c8f36 2839 kvm_lapic_switch_to_sw_timer(vcpu);
d98d07ca
MT		 2840 /*
2841 * On a host with synchronized TSC, there is no need to update
2842 * kvmclock on vcpu->cpu migration
2843 */
2844 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2845 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 2846 if (vcpu->cpu != cpu)
1bd2009e 2847 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 2848 vcpu->cpu = cpu;
6b7d7e76 2849 }
c9aaa895 2850
c9aaa895 2851 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2852}
2853
0b9f6c46
PX		 2854static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2855{
2856 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2857 return;
2858
2859 vcpu->arch.st.steal.preempted = 1;
2860
4e335d9e 2861 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 2862 &vcpu->arch.st.steal.preempted,
2863 offsetof(struct kvm_steal_time, preempted),
2864 sizeof(vcpu->arch.st.steal.preempted));
2865}
2866
313a3dc7
CO		 2867void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2868{
cc0d907c 2869 int idx;
931f261b
AA		 2870 /*
2871 * Disable page faults because we're in atomic context here.
2872 * kvm_write_guest_offset_cached() would call might_fault()
2873 * that relies on pagefault_disable() to tell if there's a
2874 * bug. NOTE: the write to guest memory may not go through if
2875 * during postcopy live migration or if there's heavy guest
2876 * paging.
2877 */
2878 pagefault_disable();
cc0d907c
AA		 2879 /*
2880 * kvm_memslots() will be called by
2881 * kvm_write_guest_offset_cached() so take the srcu lock.
2882 */
2883 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 2884 kvm_steal_time_set_preempted(vcpu);
cc0d907c 2885 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 2886 pagefault_enable();
02daab21 2887 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2888 kvm_put_guest_fpu(vcpu);
4ea1636b 2889 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2890}
2891
313a3dc7
CO		 2892static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2893 struct kvm_lapic_state *s)
2894{
76dfafd5 2895 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb
AS		 2896 kvm_x86_ops->sync_pir_to_irr(vcpu);
2897
a92e2543 2898 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 2899}
2900
2901static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2902 struct kvm_lapic_state *s)
2903{
a92e2543
RK		 2904 int r;
2905
2906 r = kvm_apic_set_state(vcpu, s);
2907 if (r)
2908 return r;
cb142eb7 2909 update_cr8_intercept(vcpu);
313a3dc7
CO		 2910
2911 return 0;
2912}
2913
127a457a
MG		 2914static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2915{
2916 return (!lapic_in_kernel(vcpu) ||
2917 kvm_apic_accept_pic_intr(vcpu));
2918}
2919
782d422b
MG		 2920/*
2921 * if userspace requested an interrupt window, check that the
2922 * interrupt window is open.
2923 *
2924 * No need to exit to userspace if we already have an interrupt queued.
2925 */
2926static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2927{
2928 return kvm_arch_interrupt_allowed(vcpu) &&
2929 !kvm_cpu_has_interrupt(vcpu) &&
2930 !kvm_event_needs_reinjection(vcpu) &&
2931 kvm_cpu_accept_dm_intr(vcpu);
2932}
2933
f77bc6a4
ZX		 2934static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2935 struct kvm_interrupt *irq)
2936{
02cdb50f 2937 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2938 return -EINVAL;
1c1a9ce9
SR		 2939
2940 if (!irqchip_in_kernel(vcpu->kvm)) {
2941 kvm_queue_interrupt(vcpu, irq->irq, false);
2942 kvm_make_request(KVM_REQ_EVENT, vcpu);
2943 return 0;
2944 }
2945
2946 /*
2947 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2948 * fail for in-kernel 8259.
2949 */
2950 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2951 return -ENXIO;
f77bc6a4 2952
1c1a9ce9
SR		 2953 if (vcpu->arch.pending_external_vector != -1)
2954 return -EEXIST;
f77bc6a4 2955
1c1a9ce9 2956 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2957 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2958 return 0;
2959}
2960
c4abb7c9
JK		 2961static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2962{
c4abb7c9 2963 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2964
2965 return 0;
2966}
2967
f077825a
PB		 2968static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2969{
64d60670
PB		 2970 kvm_make_request(KVM_REQ_SMI, vcpu);
2971
f077825a
PB		 2972 return 0;
2973}
2974
b209749f
AK		 2975static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2976 struct kvm_tpr_access_ctl *tac)
2977{
2978 if (tac->flags)
2979 return -EINVAL;
2980 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2981 return 0;
2982}
2983
890ca9ae
HY		 2984static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2985 u64 mcg_cap)
2986{
2987 int r;
2988 unsigned bank_num = mcg_cap & 0xff, bank;
2989
2990 r = -EINVAL;
a9e38c3e 2991 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 2992 goto out;
c45dcc71 2993 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 2994 goto out;
2995 r = 0;
2996 vcpu->arch.mcg_cap = mcg_cap;
2997 /* Init IA32_MCG_CTL to all 1s */
2998 if (mcg_cap & MCG_CTL_P)
2999 vcpu->arch.mcg_ctl = ~(u64)0;
3000 /* Init IA32_MCi_CTL to all 1s */
3001 for (bank = 0; bank < bank_num; bank++)
3002 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3003
3004 if (kvm_x86_ops->setup_mce)
3005 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3006out:
3007 return r;
3008}
3009
3010static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3011 struct kvm_x86_mce *mce)
3012{
3013 u64 mcg_cap = vcpu->arch.mcg_cap;
3014 unsigned bank_num = mcg_cap & 0xff;
3015 u64 *banks = vcpu->arch.mce_banks;
3016
3017 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3018 return -EINVAL;
3019 /*
3020 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3021 * reporting is disabled
3022 */
3023 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3024 vcpu->arch.mcg_ctl != ~(u64)0)
3025 return 0;
3026 banks += 4 * mce->bank;
3027 /*
3028 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3029 * reporting is disabled for the bank
3030 */
3031 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3032 return 0;
3033 if (mce->status & MCI_STATUS_UC) {
3034 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3035 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3036 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3037 return 0;
3038 }
3039 if (banks[1] & MCI_STATUS_VAL)
3040 mce->status |= MCI_STATUS_OVER;
3041 banks[2] = mce->addr;
3042 banks[3] = mce->misc;
3043 vcpu->arch.mcg_status = mce->mcg_status;
3044 banks[1] = mce->status;
3045 kvm_queue_exception(vcpu, MC_VECTOR);
3046 } else if (!(banks[1] & MCI_STATUS_VAL)
3047 || !(banks[1] & MCI_STATUS_UC)) {
3048 if (banks[1] & MCI_STATUS_VAL)
3049 mce->status |= MCI_STATUS_OVER;
3050 banks[2] = mce->addr;
3051 banks[3] = mce->misc;
3052 banks[1] = mce->status;
3053 } else
3054 banks[1] |= MCI_STATUS_OVER;
3055 return 0;
3056}
3057
3cfc3092
JK		 3058static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3059 struct kvm_vcpu_events *events)
3060{
7460fb4a 3061 process_nmi(vcpu);
03b82a30
JK		 3062 events->exception.injected =
3063 vcpu->arch.exception.pending &&
3064 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3065 events->exception.nr = vcpu->arch.exception.nr;
3066 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3067 events->exception.pad = 0;
3cfc3092
JK		 3068 events->exception.error_code = vcpu->arch.exception.error_code;
3069
03b82a30
JK		 3070 events->interrupt.injected =
3071 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3072 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3073 events->interrupt.soft = 0;
37ccdcbe 3074 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3075
3076 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3077 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3078 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3079 events->nmi.pad = 0;
3cfc3092 3080
66450a21 3081 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3082
f077825a
PB		 3083 events->smi.smm = is_smm(vcpu);
3084 events->smi.pending = vcpu->arch.smi_pending;
3085 events->smi.smm_inside_nmi =
3086 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3087 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3088
dab4b911 3089 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3090 | KVM_VCPUEVENT_VALID_SHADOW
3091 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3092 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3093}
3094
6ef4e07e
XG		 3095static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3096
3cfc3092
JK		 3097static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3098 struct kvm_vcpu_events *events)
3099{
dab4b911 3100 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3101 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3102 | KVM_VCPUEVENT_VALID_SHADOW
3103 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3104 return -EINVAL;
3105
78e546c8 3106 if (events->exception.injected &&
28d06353
JM		 3107 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3108 is_guest_mode(vcpu)))
78e546c8
PB		 3109 return -EINVAL;
3110
28bf2888
DH		 3111 /* INITs are latched while in SMM */
3112 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3113 (events->smi.smm || events->smi.pending) &&
3114 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3115 return -EINVAL;
3116
7460fb4a 3117 process_nmi(vcpu);
3cfc3092
JK		 3118 vcpu->arch.exception.pending = events->exception.injected;
3119 vcpu->arch.exception.nr = events->exception.nr;
3120 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3121 vcpu->arch.exception.error_code = events->exception.error_code;
3122
3123 vcpu->arch.interrupt.pending = events->interrupt.injected;
3124 vcpu->arch.interrupt.nr = events->interrupt.nr;
3125 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3126 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3127 kvm_x86_ops->set_interrupt_shadow(vcpu,
3128 events->interrupt.shadow);
3cfc3092
JK		 3129
3130 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3131 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3132 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3133 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3134
66450a21 3135 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3136 lapic_in_kernel(vcpu))
66450a21 3137 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3138
f077825a 3139 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3140 u32 hflags = vcpu->arch.hflags;
f077825a 3141 if (events->smi.smm)
6ef4e07e 3142 hflags |= HF_SMM_MASK;
f077825a 3143 else
6ef4e07e
XG		 3144 hflags &= ~HF_SMM_MASK;
3145 kvm_set_hflags(vcpu, hflags);
3146
f077825a
PB		 3147 vcpu->arch.smi_pending = events->smi.pending;
3148 if (events->smi.smm_inside_nmi)
3149 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3150 else
3151 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
bce87cce 3152 if (lapic_in_kernel(vcpu)) {
f077825a
PB		 3153 if (events->smi.latched_init)
3154 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3155 else
3156 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3157 }
3158 }
3159
3842d135
AK		 3160 kvm_make_request(KVM_REQ_EVENT, vcpu);
3161
3cfc3092
JK		 3162 return 0;
3163}
3164
a1efbe77
JK		 3165static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3166 struct kvm_debugregs *dbgregs)
3167{
73aaf249
JK		 3168 unsigned long val;
3169
a1efbe77 3170 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3171 kvm_get_dr(vcpu, 6, &val);
73aaf249 3172 dbgregs->dr6 = val;
a1efbe77
JK		 3173 dbgregs->dr7 = vcpu->arch.dr7;
3174 dbgregs->flags = 0;
97e69aa6 3175 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3176}
3177
3178static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3179 struct kvm_debugregs *dbgregs)
3180{
3181 if (dbgregs->flags)
3182 return -EINVAL;
3183
d14bdb55
PB		 3184 if (dbgregs->dr6 & ~0xffffffffull)
3185 return -EINVAL;
3186 if (dbgregs->dr7 & ~0xffffffffull)
3187 return -EINVAL;
3188
a1efbe77 3189 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3190 kvm_update_dr0123(vcpu);
a1efbe77 3191 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3192 kvm_update_dr6(vcpu);
a1efbe77 3193 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3194 kvm_update_dr7(vcpu);
a1efbe77 3195
a1efbe77
JK		 3196 return 0;
3197}
3198
df1daba7
PB		 3199#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3200
3201static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3202{
c47ada30 3203 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3204 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3205 u64 valid;
3206
3207 /*
3208 * Copy legacy XSAVE area, to avoid complications with CPUID
3209 * leaves 0 and 1 in the loop below.
3210 */
3211 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3212
3213 /* Set XSTATE_BV */
00c87e9a 3214 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3215 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3216
3217 /*
3218 * Copy each region from the possibly compacted offset to the
3219 * non-compacted offset.
3220 */
d91cab78 3221 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3222 while (valid) {
3223 u64 feature = valid & -valid;
3224 int index = fls64(feature) - 1;
3225 void *src = get_xsave_addr(xsave, feature);
3226
3227 if (src) {
3228 u32 size, offset, ecx, edx;
3229 cpuid_count(XSTATE_CPUID, index,
3230 &size, &offset, &ecx, &edx);
3231 memcpy(dest + offset, src, size);
3232 }
3233
3234 valid -= feature;
3235 }
3236}
3237
3238static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3239{
c47ada30 3240 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3241 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3242 u64 valid;
3243
3244 /*
3245 * Copy legacy XSAVE area, to avoid complications with CPUID
3246 * leaves 0 and 1 in the loop below.
3247 */
3248 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3249
3250 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3251 xsave->header.xfeatures = xstate_bv;
782511b0 3252 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3253 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3254
3255 /*
3256 * Copy each region from the non-compacted offset to the
3257 * possibly compacted offset.
3258 */
d91cab78 3259 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3260 while (valid) {
3261 u64 feature = valid & -valid;
3262 int index = fls64(feature) - 1;
3263 void *dest = get_xsave_addr(xsave, feature);
3264
3265 if (dest) {
3266 u32 size, offset, ecx, edx;
3267 cpuid_count(XSTATE_CPUID, index,
3268 &size, &offset, &ecx, &edx);
3269 memcpy(dest, src + offset, size);
ee4100da 3270 }
df1daba7
PB		 3271
3272 valid -= feature;
3273 }
3274}
3275
2d5b5a66
SY		 3276static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3277 struct kvm_xsave *guest_xsave)
3278{
d366bf7e 3279 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3280 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3281 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3282 } else {
2d5b5a66 3283 memcpy(guest_xsave->region,
7366ed77 3284 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3285 sizeof(struct fxregs_state));
2d5b5a66 3286 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3287 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3288 }
3289}
3290
a575813b
WL		 3291#define XSAVE_MXCSR_OFFSET 24
3292
2d5b5a66
SY		 3293static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3294 struct kvm_xsave *guest_xsave)
3295{
3296 u64 xstate_bv =
3297 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3298 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3299
d366bf7e 3300 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3301 /*
3302 * Here we allow setting states that are not present in
3303 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3304 * with old userspace.
3305 */
a575813b
WL		 3306 if (xstate_bv & ~kvm_supported_xcr0() ||
3307 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3308 return -EINVAL;
df1daba7 3309 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3310 } else {
a575813b
WL		 3311 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3312 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3313 return -EINVAL;
7366ed77 3314 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3315 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3316 }
3317 return 0;
3318}
3319
3320static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3321 struct kvm_xcrs *guest_xcrs)
3322{
d366bf7e 3323 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3324 guest_xcrs->nr_xcrs = 0;
3325 return;
3326 }
3327
3328 guest_xcrs->nr_xcrs = 1;
3329 guest_xcrs->flags = 0;
3330 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3331 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3332}
3333
3334static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3335 struct kvm_xcrs *guest_xcrs)
3336{
3337 int i, r = 0;
3338
d366bf7e 3339 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3340 return -EINVAL;
3341
3342 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3343 return -EINVAL;
3344
3345 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3346 /* Only support XCR0 currently */
c67a04cb 3347 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3348 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3349 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3350 break;
3351 }
3352 if (r)
3353 r = -EINVAL;
3354 return r;
3355}
3356
1c0b28c2
EM		 3357/*
3358 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3359 * stopped by the hypervisor. This function will be called from the host only.
3360 * EINVAL is returned when the host attempts to set the flag for a guest that
3361 * does not support pv clocks.
3362 */
3363static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3364{
0b79459b 3365 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3366 return -EINVAL;
51d59c6b 3367 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3368 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3369 return 0;
3370}
3371
5c919412
AS		 3372static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3373 struct kvm_enable_cap *cap)
3374{
3375 if (cap->flags)
3376 return -EINVAL;
3377
3378 switch (cap->cap) {
3379 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3380 if (!irqchip_in_kernel(vcpu->kvm))
3381 return -EINVAL;
5c919412
AS		 3382 return kvm_hv_activate_synic(vcpu);
3383 default:
3384 return -EINVAL;
3385 }
3386}
3387
313a3dc7
CO		 3388long kvm_arch_vcpu_ioctl(struct file *filp,
3389 unsigned int ioctl, unsigned long arg)
3390{
3391 struct kvm_vcpu *vcpu = filp->private_data;
3392 void __user *argp = (void __user *)arg;
3393 int r;
d1ac91d8
AK		 3394 union {
3395 struct kvm_lapic_state *lapic;
3396 struct kvm_xsave *xsave;
3397 struct kvm_xcrs *xcrs;
3398 void *buffer;
3399 } u;
3400
3401 u.buffer = NULL;
313a3dc7
CO		 3402 switch (ioctl) {
3403 case KVM_GET_LAPIC: {
2204ae3c 3404 r = -EINVAL;
bce87cce 3405 if (!lapic_in_kernel(vcpu))
2204ae3c 3406 goto out;
d1ac91d8 3407 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3408
b772ff36 3409 r = -ENOMEM;
d1ac91d8 3410 if (!u.lapic)
b772ff36 3411 goto out;
d1ac91d8 3412 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3413 if (r)
3414 goto out;
3415 r = -EFAULT;
d1ac91d8 3416 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3417 goto out;
3418 r = 0;
3419 break;
3420 }
3421 case KVM_SET_LAPIC: {
2204ae3c 3422 r = -EINVAL;
bce87cce 3423 if (!lapic_in_kernel(vcpu))
2204ae3c 3424 goto out;
ff5c2c03 3425 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3426 if (IS_ERR(u.lapic))
3427 return PTR_ERR(u.lapic);
ff5c2c03 3428
d1ac91d8 3429 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3430 break;
3431 }
f77bc6a4
ZX		 3432 case KVM_INTERRUPT: {
3433 struct kvm_interrupt irq;
3434
3435 r = -EFAULT;
3436 if (copy_from_user(&irq, argp, sizeof irq))
3437 goto out;
3438 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3439 break;
3440 }
c4abb7c9
JK		 3441 case KVM_NMI: {
3442 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3443 break;
3444 }
f077825a
PB		 3445 case KVM_SMI: {
3446 r = kvm_vcpu_ioctl_smi(vcpu);
3447 break;
3448 }
313a3dc7
CO		 3449 case KVM_SET_CPUID: {
3450 struct kvm_cpuid __user *cpuid_arg = argp;
3451 struct kvm_cpuid cpuid;
3452
3453 r = -EFAULT;
3454 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3455 goto out;
3456 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3457 break;
3458 }
07716717
DK		 3459 case KVM_SET_CPUID2: {
3460 struct kvm_cpuid2 __user *cpuid_arg = argp;
3461 struct kvm_cpuid2 cpuid;
3462
3463 r = -EFAULT;
3464 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3465 goto out;
3466 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3467 cpuid_arg->entries);
07716717
DK		 3468 break;
3469 }
3470 case KVM_GET_CPUID2: {
3471 struct kvm_cpuid2 __user *cpuid_arg = argp;
3472 struct kvm_cpuid2 cpuid;
3473
3474 r = -EFAULT;
3475 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3476 goto out;
3477 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3478 cpuid_arg->entries);
07716717
DK		 3479 if (r)
3480 goto out;
3481 r = -EFAULT;
3482 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3483 goto out;
3484 r = 0;
3485 break;
3486 }
313a3dc7 3487 case KVM_GET_MSRS:
609e36d3 3488 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3489 break;
3490 case KVM_SET_MSRS:
3491 r = msr_io(vcpu, argp, do_set_msr, 0);
3492 break;
b209749f
AK		 3493 case KVM_TPR_ACCESS_REPORTING: {
3494 struct kvm_tpr_access_ctl tac;
3495
3496 r = -EFAULT;
3497 if (copy_from_user(&tac, argp, sizeof tac))
3498 goto out;
3499 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3500 if (r)
3501 goto out;
3502 r = -EFAULT;
3503 if (copy_to_user(argp, &tac, sizeof tac))
3504 goto out;
3505 r = 0;
3506 break;
3507 };
b93463aa
AK		 3508 case KVM_SET_VAPIC_ADDR: {
3509 struct kvm_vapic_addr va;
7301d6ab 3510 int idx;
b93463aa
AK		 3511
3512 r = -EINVAL;
35754c98 3513 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3514 goto out;
3515 r = -EFAULT;
3516 if (copy_from_user(&va, argp, sizeof va))
3517 goto out;
7301d6ab 3518 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3519 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3520 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3521 break;
3522 }
890ca9ae
HY		 3523 case KVM_X86_SETUP_MCE: {
3524 u64 mcg_cap;
3525
3526 r = -EFAULT;
3527 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3528 goto out;
3529 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3530 break;
3531 }
3532 case KVM_X86_SET_MCE: {
3533 struct kvm_x86_mce mce;
3534
3535 r = -EFAULT;
3536 if (copy_from_user(&mce, argp, sizeof mce))
3537 goto out;
3538 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3539 break;
3540 }
3cfc3092
JK		 3541 case KVM_GET_VCPU_EVENTS: {
3542 struct kvm_vcpu_events events;
3543
3544 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3545
3546 r = -EFAULT;
3547 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3548 break;
3549 r = 0;
3550 break;
3551 }
3552 case KVM_SET_VCPU_EVENTS: {
3553 struct kvm_vcpu_events events;
3554
3555 r = -EFAULT;
3556 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3557 break;
3558
3559 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3560 break;
3561 }
a1efbe77
JK		 3562 case KVM_GET_DEBUGREGS: {
3563 struct kvm_debugregs dbgregs;
3564
3565 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3566
3567 r = -EFAULT;
3568 if (copy_to_user(argp, &dbgregs,
3569 sizeof(struct kvm_debugregs)))
3570 break;
3571 r = 0;
3572 break;
3573 }
3574 case KVM_SET_DEBUGREGS: {
3575 struct kvm_debugregs dbgregs;
3576
3577 r = -EFAULT;
3578 if (copy_from_user(&dbgregs, argp,
3579 sizeof(struct kvm_debugregs)))
3580 break;
3581
3582 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3583 break;
3584 }
2d5b5a66 3585 case KVM_GET_XSAVE: {
d1ac91d8 3586 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3587 r = -ENOMEM;
d1ac91d8 3588 if (!u.xsave)
2d5b5a66
SY		 3589 break;
3590
d1ac91d8 3591 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3592
3593 r = -EFAULT;
d1ac91d8 3594 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3595 break;
3596 r = 0;
3597 break;
3598 }
3599 case KVM_SET_XSAVE: {
ff5c2c03 3600 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3601 if (IS_ERR(u.xsave))
3602 return PTR_ERR(u.xsave);
2d5b5a66 3603
d1ac91d8 3604 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3605 break;
3606 }
3607 case KVM_GET_XCRS: {
d1ac91d8 3608 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3609 r = -ENOMEM;
d1ac91d8 3610 if (!u.xcrs)
2d5b5a66
SY		 3611 break;
3612
d1ac91d8 3613 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3614
3615 r = -EFAULT;
d1ac91d8 3616 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3617 sizeof(struct kvm_xcrs)))
3618 break;
3619 r = 0;
3620 break;
3621 }
3622 case KVM_SET_XCRS: {
ff5c2c03 3623 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3624 if (IS_ERR(u.xcrs))
3625 return PTR_ERR(u.xcrs);
2d5b5a66 3626
d1ac91d8 3627 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3628 break;
3629 }
92a1f12d
JR		 3630 case KVM_SET_TSC_KHZ: {
3631 u32 user_tsc_khz;
3632
3633 r = -EINVAL;
92a1f12d
JR		 3634 user_tsc_khz = (u32)arg;
3635
3636 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3637 goto out;
3638
cc578287
ZA		 3639 if (user_tsc_khz == 0)
3640 user_tsc_khz = tsc_khz;
3641
381d585c
HZ		 3642 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3643 r = 0;
92a1f12d 3644
92a1f12d
JR		 3645 goto out;
3646 }
3647 case KVM_GET_TSC_KHZ: {
cc578287 3648 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3649 goto out;
3650 }
1c0b28c2
EM		 3651 case KVM_KVMCLOCK_CTRL: {
3652 r = kvm_set_guest_paused(vcpu);
3653 goto out;
3654 }
5c919412
AS		 3655 case KVM_ENABLE_CAP: {
3656 struct kvm_enable_cap cap;
3657
3658 r = -EFAULT;
3659 if (copy_from_user(&cap, argp, sizeof(cap)))
3660 goto out;
3661 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3662 break;
3663 }
313a3dc7
CO		 3664 default:
3665 r = -EINVAL;
3666 }
3667out:
d1ac91d8 3668 kfree(u.buffer);
313a3dc7
CO		 3669 return r;
3670}
3671
5b1c1493
CO		 3672int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3673{
3674 return VM_FAULT_SIGBUS;
3675}
3676
1fe779f8
CO		 3677static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3678{
3679 int ret;
3680
3681 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3682 return -EINVAL;
1fe779f8
CO		 3683 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3684 return ret;
3685}
3686
b927a3ce
SY		 3687static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3688 u64 ident_addr)
3689{
3690 kvm->arch.ept_identity_map_addr = ident_addr;
3691 return 0;
3692}
3693
1fe779f8
CO		 3694static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3695 u32 kvm_nr_mmu_pages)
3696{
3697 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3698 return -EINVAL;
3699
79fac95e 3700 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3701
3702 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3703 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3704
79fac95e 3705 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3706 return 0;
3707}
3708
3709static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3710{
39de71ec 3711 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3712}
3713
1fe779f8
CO		 3714static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3715{
90bca052 3716 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3717 int r;
3718
3719 r = 0;
3720 switch (chip->chip_id) {
3721 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3722 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3723 sizeof(struct kvm_pic_state));
3724 break;
3725 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3726 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 3727 sizeof(struct kvm_pic_state));
3728 break;
3729 case KVM_IRQCHIP_IOAPIC:
33392b49 3730 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3731 break;
3732 default:
3733 r = -EINVAL;
3734 break;
3735 }
3736 return r;
3737}
3738
3739static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3740{
90bca052 3741 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3742 int r;
3743
3744 r = 0;
3745 switch (chip->chip_id) {
3746 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 3747 spin_lock(&pic->lock);
3748 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 3749 sizeof(struct kvm_pic_state));
90bca052 3750 spin_unlock(&pic->lock);
1fe779f8
CO		 3751 break;
3752 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 3753 spin_lock(&pic->lock);
3754 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 3755 sizeof(struct kvm_pic_state));
90bca052 3756 spin_unlock(&pic->lock);
1fe779f8
CO		 3757 break;
3758 case KVM_IRQCHIP_IOAPIC:
33392b49 3759 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3760 break;
3761 default:
3762 r = -EINVAL;
3763 break;
3764 }
90bca052 3765 kvm_pic_update_irq(pic);
1fe779f8
CO		 3766 return r;
3767}
3768
e0f63cb9
SY		 3769static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3770{
34f3941c
RK		 3771 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3772
3773 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3774
3775 mutex_lock(&kps->lock);
3776 memcpy(ps, &kps->channels, sizeof(*ps));
3777 mutex_unlock(&kps->lock);
2da29bcc 3778 return 0;
e0f63cb9
SY		 3779}
3780
3781static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3782{
0185604c 3783 int i;
09edea72
RK		 3784 struct kvm_pit *pit = kvm->arch.vpit;
3785
3786 mutex_lock(&pit->pit_state.lock);
34f3941c 3787 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3788 for (i = 0; i < 3; i++)
09edea72
RK		 3789 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3790 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3791 return 0;
e9f42757
BK		 3792}
3793
3794static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3795{
e9f42757
BK		 3796 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3797 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3798 sizeof(ps->channels));
3799 ps->flags = kvm->arch.vpit->pit_state.flags;
3800 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3801 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3802 return 0;
e9f42757
BK		 3803}
3804
3805static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3806{
2da29bcc 3807 int start = 0;
0185604c 3808 int i;
e9f42757 3809 u32 prev_legacy, cur_legacy;
09edea72
RK		 3810 struct kvm_pit *pit = kvm->arch.vpit;
3811
3812 mutex_lock(&pit->pit_state.lock);
3813 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3814 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3815 if (!prev_legacy && cur_legacy)
3816 start = 1;
09edea72
RK		 3817 memcpy(&pit->pit_state.channels, &ps->channels,
3818 sizeof(pit->pit_state.channels));
3819 pit->pit_state.flags = ps->flags;
0185604c 3820 for (i = 0; i < 3; i++)
09edea72 3821 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3822 start && i == 0);
09edea72 3823 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3824 return 0;
e0f63cb9
SY		 3825}
3826
52d939a0
MT		 3827static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3828 struct kvm_reinject_control *control)
3829{
71474e2f
RK		 3830 struct kvm_pit *pit = kvm->arch.vpit;
3831
3832 if (!pit)
52d939a0 3833 return -ENXIO;
b39c90b6 3834
71474e2f
RK		 3835 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3836 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3837 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3838 */
3839 mutex_lock(&pit->pit_state.lock);
3840 kvm_pit_set_reinject(pit, control->pit_reinject);
3841 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3842
52d939a0
MT		 3843 return 0;
3844}
3845
95d4c16c 3846/**
60c34612
TY		 3847 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3848 * @kvm: kvm instance
3849 * @log: slot id and address to which we copy the log
95d4c16c 3850 *
e108ff2f
PB		 3851 * Steps 1-4 below provide general overview of dirty page logging. See
3852 * kvm_get_dirty_log_protect() function description for additional details.
3853 *
3854 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3855 * always flush the TLB (step 4) even if previous step failed and the dirty
3856 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3857 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3858 * writes will be marked dirty for next log read.
95d4c16c 3859 *
60c34612
TY		 3860 * 1. Take a snapshot of the bit and clear it if needed.
3861 * 2. Write protect the corresponding page.
e108ff2f
PB		 3862 * 3. Copy the snapshot to the userspace.
3863 * 4. Flush TLB's if needed.
5bb064dc 3864 */
60c34612 3865int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3866{
60c34612 3867 bool is_dirty = false;
e108ff2f 3868 int r;
5bb064dc 3869
79fac95e 3870 mutex_lock(&kvm->slots_lock);
5bb064dc 3871
88178fd4
KH		 3872 /*
3873 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3874 */
3875 if (kvm_x86_ops->flush_log_dirty)
3876 kvm_x86_ops->flush_log_dirty(kvm);
3877
e108ff2f 3878 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3879
3880 /*
3881 * All the TLBs can be flushed out of mmu lock, see the comments in
3882 * kvm_mmu_slot_remove_write_access().
3883 */
e108ff2f 3884 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3885 if (is_dirty)
3886 kvm_flush_remote_tlbs(kvm);
3887
79fac95e 3888 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3889 return r;
3890}
3891
aa2fbe6d
YZ		 3892int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3893 bool line_status)
23d43cf9
CD		 3894{
3895 if (!irqchip_in_kernel(kvm))
3896 return -ENXIO;
3897
3898 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3899 irq_event->irq, irq_event->level,
3900 line_status);
23d43cf9
CD		 3901 return 0;
3902}
3903
90de4a18
NA		 3904static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3905 struct kvm_enable_cap *cap)
3906{
3907 int r;
3908
3909 if (cap->flags)
3910 return -EINVAL;
3911
3912 switch (cap->cap) {
3913 case KVM_CAP_DISABLE_QUIRKS:
3914 kvm->arch.disabled_quirks = cap->args[0];
3915 r = 0;
3916 break;
49df6397
SR		 3917 case KVM_CAP_SPLIT_IRQCHIP: {
3918 mutex_lock(&kvm->lock);
b053b2ae
SR		 3919 r = -EINVAL;
3920 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3921 goto split_irqchip_unlock;
49df6397
SR		 3922 r = -EEXIST;
3923 if (irqchip_in_kernel(kvm))
3924 goto split_irqchip_unlock;
557abc40 3925 if (kvm->created_vcpus)
49df6397
SR		 3926 goto split_irqchip_unlock;
3927 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 3928 if (r)
49df6397
SR		 3929 goto split_irqchip_unlock;
3930 /* Pairs with irqchip_in_kernel. */
3931 smp_wmb();
49776faf 3932 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 3933 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3934 r = 0;
3935split_irqchip_unlock:
3936 mutex_unlock(&kvm->lock);
3937 break;
3938 }
37131313
RK		 3939 case KVM_CAP_X2APIC_API:
3940 r = -EINVAL;
3941 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
3942 break;
3943
3944 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
3945 kvm->arch.x2apic_format = true;
c519265f
RK		 3946 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
3947 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 3948
3949 r = 0;
3950 break;
90de4a18
NA		 3951 default:
3952 r = -EINVAL;
3953 break;
3954 }
3955 return r;
3956}
3957
1fe779f8
CO		 3958long kvm_arch_vm_ioctl(struct file *filp,
3959 unsigned int ioctl, unsigned long arg)
3960{
3961 struct kvm *kvm = filp->private_data;
3962 void __user *argp = (void __user *)arg;
367e1319 3963 int r = -ENOTTY;
f0d66275
DH		 3964 /*
3965 * This union makes it completely explicit to gcc-3.x
3966 * that these two variables' stack usage should be
3967 * combined, not added together.
3968 */
3969 union {
3970 struct kvm_pit_state ps;
e9f42757 3971 struct kvm_pit_state2 ps2;
c5ff41ce 3972 struct kvm_pit_config pit_config;
f0d66275 3973 } u;
1fe779f8
CO		 3974
3975 switch (ioctl) {
3976 case KVM_SET_TSS_ADDR:
3977 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3978 break;
b927a3ce
SY		 3979 case KVM_SET_IDENTITY_MAP_ADDR: {
3980 u64 ident_addr;
3981
3982 r = -EFAULT;
3983 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3984 goto out;
3985 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3986 break;
3987 }
1fe779f8
CO		 3988 case KVM_SET_NR_MMU_PAGES:
3989 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3990 break;
3991 case KVM_GET_NR_MMU_PAGES:
3992 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3993 break;
3ddea128 3994 case KVM_CREATE_IRQCHIP: {
3ddea128 3995 mutex_lock(&kvm->lock);
09941366 3996
3ddea128 3997 r = -EEXIST;
35e6eaa3 3998 if (irqchip_in_kernel(kvm))
3ddea128 3999 goto create_irqchip_unlock;
09941366 4000
3e515705 4001 r = -EINVAL;
557abc40 4002 if (kvm->created_vcpus)
3e515705 4003 goto create_irqchip_unlock;
09941366
RK		 4004
4005 r = kvm_pic_init(kvm);
4006 if (r)
3ddea128 4007 goto create_irqchip_unlock;
09941366
RK		 4008
4009 r = kvm_ioapic_init(kvm);
4010 if (r) {
09941366 4011 kvm_pic_destroy(kvm);
3ddea128 4012 goto create_irqchip_unlock;
09941366
RK		 4013 }
4014
399ec807
AK		 4015 r = kvm_setup_default_irq_routing(kvm);
4016 if (r) {
72bb2fcd 4017 kvm_ioapic_destroy(kvm);
09941366 4018 kvm_pic_destroy(kvm);
71ba994c 4019 goto create_irqchip_unlock;
399ec807 4020 }
49776faf 4021 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4022 smp_wmb();
49776faf 4023 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4024 create_irqchip_unlock:
4025 mutex_unlock(&kvm->lock);
1fe779f8 4026 break;
3ddea128 4027 }
7837699f 4028 case KVM_CREATE_PIT:
c5ff41ce
JK		 4029 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4030 goto create_pit;
4031 case KVM_CREATE_PIT2:
4032 r = -EFAULT;
4033 if (copy_from_user(&u.pit_config, argp,
4034 sizeof(struct kvm_pit_config)))
4035 goto out;
4036 create_pit:
250715a6 4037 mutex_lock(&kvm->lock);
269e05e4
AK		 4038 r = -EEXIST;
4039 if (kvm->arch.vpit)
4040 goto create_pit_unlock;
7837699f 4041 r = -ENOMEM;
c5ff41ce 4042 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4043 if (kvm->arch.vpit)
4044 r = 0;
269e05e4 4045 create_pit_unlock:
250715a6 4046 mutex_unlock(&kvm->lock);
7837699f 4047 break;
1fe779f8
CO		 4048 case KVM_GET_IRQCHIP: {
4049 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4050 struct kvm_irqchip *chip;
1fe779f8 4051
ff5c2c03
SL		 4052 chip = memdup_user(argp, sizeof(*chip));
4053 if (IS_ERR(chip)) {
4054 r = PTR_ERR(chip);
1fe779f8 4055 goto out;
ff5c2c03
SL		 4056 }
4057
1fe779f8 4058 r = -ENXIO;
826da321 4059 if (!irqchip_kernel(kvm))
f0d66275
DH		 4060 goto get_irqchip_out;
4061 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4062 if (r)
f0d66275 4063 goto get_irqchip_out;
1fe779f8 4064 r = -EFAULT;
f0d66275
DH		 4065 if (copy_to_user(argp, chip, sizeof *chip))
4066 goto get_irqchip_out;
1fe779f8 4067 r = 0;
f0d66275
DH		 4068 get_irqchip_out:
4069 kfree(chip);
1fe779f8
CO		 4070 break;
4071 }
4072 case KVM_SET_IRQCHIP: {
4073 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4074 struct kvm_irqchip *chip;
1fe779f8 4075
ff5c2c03
SL		 4076 chip = memdup_user(argp, sizeof(*chip));
4077 if (IS_ERR(chip)) {
4078 r = PTR_ERR(chip);
1fe779f8 4079 goto out;
ff5c2c03
SL		 4080 }
4081
1fe779f8 4082 r = -ENXIO;
826da321 4083 if (!irqchip_kernel(kvm))
f0d66275
DH		 4084 goto set_irqchip_out;
4085 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4086 if (r)
f0d66275 4087 goto set_irqchip_out;
1fe779f8 4088 r = 0;
f0d66275
DH		 4089 set_irqchip_out:
4090 kfree(chip);
1fe779f8
CO		 4091 break;
4092 }
e0f63cb9 4093 case KVM_GET_PIT: {
e0f63cb9 4094 r = -EFAULT;
f0d66275 4095 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4096 goto out;
4097 r = -ENXIO;
4098 if (!kvm->arch.vpit)
4099 goto out;
f0d66275 4100 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4101 if (r)
4102 goto out;
4103 r = -EFAULT;
f0d66275 4104 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4105 goto out;
4106 r = 0;
4107 break;
4108 }
4109 case KVM_SET_PIT: {
e0f63cb9 4110 r = -EFAULT;
f0d66275 4111 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4112 goto out;
4113 r = -ENXIO;
4114 if (!kvm->arch.vpit)
4115 goto out;
f0d66275 4116 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4117 break;
4118 }
e9f42757
BK		 4119 case KVM_GET_PIT2: {
4120 r = -ENXIO;
4121 if (!kvm->arch.vpit)
4122 goto out;
4123 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4124 if (r)
4125 goto out;
4126 r = -EFAULT;
4127 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4128 goto out;
4129 r = 0;
4130 break;
4131 }
4132 case KVM_SET_PIT2: {
4133 r = -EFAULT;
4134 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4135 goto out;
4136 r = -ENXIO;
4137 if (!kvm->arch.vpit)
4138 goto out;
4139 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4140 break;
4141 }
52d939a0
MT		 4142 case KVM_REINJECT_CONTROL: {
4143 struct kvm_reinject_control control;
4144 r = -EFAULT;
4145 if (copy_from_user(&control, argp, sizeof(control)))
4146 goto out;
4147 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4148 break;
4149 }
d71ba788
PB		 4150 case KVM_SET_BOOT_CPU_ID:
4151 r = 0;
4152 mutex_lock(&kvm->lock);
557abc40 4153 if (kvm->created_vcpus)
d71ba788
PB		 4154 r = -EBUSY;
4155 else
4156 kvm->arch.bsp_vcpu_id = arg;
4157 mutex_unlock(&kvm->lock);
4158 break;
ffde22ac
ES		 4159 case KVM_XEN_HVM_CONFIG: {
4160 r = -EFAULT;
4161 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4162 sizeof(struct kvm_xen_hvm_config)))
4163 goto out;
4164 r = -EINVAL;
4165 if (kvm->arch.xen_hvm_config.flags)
4166 goto out;
4167 r = 0;
4168 break;
4169 }
afbcf7ab 4170 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4171 struct kvm_clock_data user_ns;
4172 u64 now_ns;
afbcf7ab
GC		 4173
4174 r = -EFAULT;
4175 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4176 goto out;
4177
4178 r = -EINVAL;
4179 if (user_ns.flags)
4180 goto out;
4181
4182 r = 0;
e891a32e 4183 now_ns = get_kvmclock_ns(kvm);
108b249c 4184 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
2e762ff7 4185 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4186 break;
4187 }
4188 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4189 struct kvm_clock_data user_ns;
4190 u64 now_ns;
4191
e891a32e 4192 now_ns = get_kvmclock_ns(kvm);
108b249c 4193 user_ns.clock = now_ns;
e3fd9a93 4194 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4195 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4196
4197 r = -EFAULT;
4198 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4199 goto out;
4200 r = 0;
4201 break;
4202 }
90de4a18
NA		 4203 case KVM_ENABLE_CAP: {
4204 struct kvm_enable_cap cap;
afbcf7ab 4205
90de4a18
NA		 4206 r = -EFAULT;
4207 if (copy_from_user(&cap, argp, sizeof(cap)))
4208 goto out;
4209 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4210 break;
4211 }
1fe779f8 4212 default:
ad6260da 4213 r = -ENOTTY;
1fe779f8
CO		 4214 }
4215out:
4216 return r;
4217}
4218
a16b043c 4219static void kvm_init_msr_list(void)
043405e1
CO		 4220{
4221 u32 dummy[2];
4222 unsigned i, j;
4223
62ef68bb 4224 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4225 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4226 continue;
93c4adc7
PB		 4227
4228 /*
4229 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4230 * to the guests in some cases.
93c4adc7
PB		 4231 */
4232 switch (msrs_to_save[i]) {
4233 case MSR_IA32_BNDCFGS:
4234 if (!kvm_x86_ops->mpx_supported())
4235 continue;
4236 break;
9dbe6cf9
PB		 4237 case MSR_TSC_AUX:
4238 if (!kvm_x86_ops->rdtscp_supported())
4239 continue;
4240 break;
93c4adc7
PB		 4241 default:
4242 break;
4243 }
4244
043405e1
CO		 4245 if (j < i)
4246 msrs_to_save[j] = msrs_to_save[i];
4247 j++;
4248 }
4249 num_msrs_to_save = j;
62ef68bb
PB		 4250
4251 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4252 switch (emulated_msrs[i]) {
6d396b55
PB		 4253 case MSR_IA32_SMBASE:
4254 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4255 continue;
4256 break;
62ef68bb
PB		 4257 default:
4258 break;
4259 }
4260
4261 if (j < i)
4262 emulated_msrs[j] = emulated_msrs[i];
4263 j++;
4264 }
4265 num_emulated_msrs = j;
043405e1
CO		 4266}
4267
bda9020e
MT		 4268static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4269 const void *v)
bbd9b64e 4270{
70252a10
AK		 4271 int handled = 0;
4272 int n;
4273
4274 do {
4275 n = min(len, 8);
bce87cce 4276 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4277 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4278 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4279 break;
4280 handled += n;
4281 addr += n;
4282 len -= n;
4283 v += n;
4284 } while (len);
bbd9b64e 4285
70252a10 4286 return handled;
bbd9b64e
CO		 4287}
4288
bda9020e 4289static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4290{
70252a10
AK		 4291 int handled = 0;
4292 int n;
4293
4294 do {
4295 n = min(len, 8);
bce87cce 4296 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4297 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4298 addr, n, v))
4299 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4300 break;
4301 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4302 handled += n;
4303 addr += n;
4304 len -= n;
4305 v += n;
4306 } while (len);
bbd9b64e 4307
70252a10 4308 return handled;
bbd9b64e
CO		 4309}
4310
2dafc6c2
GN		 4311static void kvm_set_segment(struct kvm_vcpu *vcpu,
4312 struct kvm_segment *var, int seg)
4313{
4314 kvm_x86_ops->set_segment(vcpu, var, seg);
4315}
4316
4317void kvm_get_segment(struct kvm_vcpu *vcpu,
4318 struct kvm_segment *var, int seg)
4319{
4320 kvm_x86_ops->get_segment(vcpu, var, seg);
4321}
4322
54987b7a
PB		 4323gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4324 struct x86_exception *exception)
02f59dc9
JR		 4325{
4326 gpa_t t_gpa;
02f59dc9
JR		 4327
4328 BUG_ON(!mmu_is_nested(vcpu));
4329
4330 /* NPT walks are always user-walks */
4331 access |= PFERR_USER_MASK;
54987b7a 4332 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4333
4334 return t_gpa;
4335}
4336
ab9ae313
AK		 4337gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4338 struct x86_exception *exception)
1871c602
GN		 4339{
4340 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4341 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4342}
4343
ab9ae313
AK		 4344 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4345 struct x86_exception *exception)
1871c602
GN		 4346{
4347 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4348 access |= PFERR_FETCH_MASK;
ab9ae313 4349 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4350}
4351
ab9ae313
AK		 4352gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4353 struct x86_exception *exception)
1871c602
GN		 4354{
4355 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4356 access |= PFERR_WRITE_MASK;
ab9ae313 4357 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4358}
4359
4360/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4361gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4362 struct x86_exception *exception)
1871c602 4363{
ab9ae313 4364 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4365}
4366
4367static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4368 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4369 struct x86_exception *exception)
bbd9b64e
CO		 4370{
4371 void *data = val;
10589a46 4372 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4373
4374 while (bytes) {
14dfe855 4375 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4376 exception);
bbd9b64e 4377 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4378 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4379 int ret;
4380
bcc55cba 4381 if (gpa == UNMAPPED_GVA)
ab9ae313 4382 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4383 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4384 offset, toread);
10589a46 4385 if (ret < 0) {
c3cd7ffa 4386 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4387 goto out;
4388 }
bbd9b64e 4389
77c2002e
IE		 4390 bytes -= toread;
4391 data += toread;
4392 addr += toread;
bbd9b64e 4393 }
10589a46 4394out:
10589a46 4395 return r;
bbd9b64e 4396}
77c2002e 4397
1871c602 4398/* used for instruction fetching */
0f65dd70
AK		 4399static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4400 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4401 struct x86_exception *exception)
1871c602 4402{
0f65dd70 4403 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4404 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4405 unsigned offset;
4406 int ret;
0f65dd70 4407
44583cba
PB		 4408 /* Inline kvm_read_guest_virt_helper for speed. */
4409 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4410 exception);
4411 if (unlikely(gpa == UNMAPPED_GVA))
4412 return X86EMUL_PROPAGATE_FAULT;
4413
4414 offset = addr & (PAGE_SIZE-1);
4415 if (WARN_ON(offset + bytes > PAGE_SIZE))
4416 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4417 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4418 offset, bytes);
44583cba
PB		 4419 if (unlikely(ret < 0))
4420 return X86EMUL_IO_NEEDED;
4421
4422 return X86EMUL_CONTINUE;
1871c602
GN		 4423}
4424
064aea77 4425int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4426 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4427 struct x86_exception *exception)
1871c602 4428{
0f65dd70 4429 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4430 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4431
1871c602 4432 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4433 exception);
1871c602 4434}
064aea77 4435EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4436
0f65dd70
AK		 4437static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4438 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4439 struct x86_exception *exception)
1871c602 4440{
0f65dd70 4441 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4442 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4443}
4444
7a036a6f
RK		 4445static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4446 unsigned long addr, void *val, unsigned int bytes)
4447{
4448 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4449 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4450
4451 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4452}
4453
6a4d7550 4454int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4455 gva_t addr, void *val,
2dafc6c2 4456 unsigned int bytes,
bcc55cba 4457 struct x86_exception *exception)
77c2002e 4458{
0f65dd70 4459 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4460 void *data = val;
4461 int r = X86EMUL_CONTINUE;
4462
4463 while (bytes) {
14dfe855
JR		 4464 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4465 PFERR_WRITE_MASK,
ab9ae313 4466 exception);
77c2002e
IE		 4467 unsigned offset = addr & (PAGE_SIZE-1);
4468 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4469 int ret;
4470
bcc55cba 4471 if (gpa == UNMAPPED_GVA)
ab9ae313 4472 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4473 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4474 if (ret < 0) {
c3cd7ffa 4475 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4476 goto out;
4477 }
4478
4479 bytes -= towrite;
4480 data += towrite;
4481 addr += towrite;
4482 }
4483out:
4484 return r;
4485}
6a4d7550 4486EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4487
0f89b207
TL		 4488static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4489 gpa_t gpa, bool write)
4490{
4491 /* For APIC access vmexit */
4492 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4493 return 1;
4494
4495 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4496 trace_vcpu_match_mmio(gva, gpa, write, true);
4497 return 1;
4498 }
4499
4500 return 0;
4501}
4502
af7cc7d1
XG		 4503static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4504 gpa_t *gpa, struct x86_exception *exception,
4505 bool write)
4506{
97d64b78
AK		 4507 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4508 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4509
be94f6b7
HH		 4510 /*
4511 * currently PKRU is only applied to ept enabled guest so
4512 * there is no pkey in EPT page table for L1 guest or EPT
4513 * shadow page table for L2 guest.
4514 */
97d64b78 4515 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4516 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4517 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4518 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4519 (gva & (PAGE_SIZE - 1));
4f022648 4520 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4521 return 1;
4522 }
4523
af7cc7d1
XG		 4524 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4525
4526 if (*gpa == UNMAPPED_GVA)
4527 return -1;
4528
0f89b207 4529 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4530}
4531
3200f405 4532int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4533 const void *val, int bytes)
bbd9b64e
CO		 4534{
4535 int ret;
4536
54bf36aa 4537 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4538 if (ret < 0)
bbd9b64e 4539 return 0;
0eb05bf2 4540 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4541 return 1;
4542}
4543
77d197b2
XG		 4544struct read_write_emulator_ops {
4545 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4546 int bytes);
4547 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4548 void *val, int bytes);
4549 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4550 int bytes, void *val);
4551 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4552 void *val, int bytes);
4553 bool write;
4554};
4555
4556static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4557{
4558 if (vcpu->mmio_read_completed) {
77d197b2 4559 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4560 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4561 vcpu->mmio_read_completed = 0;
4562 return 1;
4563 }
4564
4565 return 0;
4566}
4567
4568static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4569 void *val, int bytes)
4570{
54bf36aa 4571 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4572}
4573
4574static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4575 void *val, int bytes)
4576{
4577 return emulator_write_phys(vcpu, gpa, val, bytes);
4578}
4579
4580static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4581{
4582 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4583 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4584}
4585
4586static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4587 void *val, int bytes)
4588{
4589 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4590 return X86EMUL_IO_NEEDED;
4591}
4592
4593static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4594 void *val, int bytes)
4595{
f78146b0
AK		 4596 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4597
87da7e66 4598 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4599 return X86EMUL_CONTINUE;
4600}
4601
0fbe9b0b 4602static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4603 .read_write_prepare = read_prepare,
4604 .read_write_emulate = read_emulate,
4605 .read_write_mmio = vcpu_mmio_read,
4606 .read_write_exit_mmio = read_exit_mmio,
4607};
4608
0fbe9b0b 4609static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4610 .read_write_emulate = write_emulate,
4611 .read_write_mmio = write_mmio,
4612 .read_write_exit_mmio = write_exit_mmio,
4613 .write = true,
4614};
4615
22388a3c
XG		 4616static int emulator_read_write_onepage(unsigned long addr, void *val,
4617 unsigned int bytes,
4618 struct x86_exception *exception,
4619 struct kvm_vcpu *vcpu,
0fbe9b0b 4620 const struct read_write_emulator_ops *ops)
bbd9b64e 4621{
af7cc7d1
XG		 4622 gpa_t gpa;
4623 int handled, ret;
22388a3c 4624 bool write = ops->write;
f78146b0 4625 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4626 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4627
4628 /*
4629 * If the exit was due to a NPF we may already have a GPA.
4630 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4631 * Note, this cannot be used on string operations since string
4632 * operation using rep will only have the initial GPA from the NPF
4633 * occurred.
4634 */
4635 if (vcpu->arch.gpa_available &&
4636 emulator_can_use_gpa(ctxt) &&
4637 vcpu_is_mmio_gpa(vcpu, addr, exception->address, write) &&
4638 (addr & ~PAGE_MASK) == (exception->address & ~PAGE_MASK)) {
4639 gpa = exception->address;
4640 goto mmio;
4641 }
10589a46 4642
22388a3c 4643 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4644
af7cc7d1 4645 if (ret < 0)
bbd9b64e 4646 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4647
4648 /* For APIC access vmexit */
af7cc7d1 4649 if (ret)
bbd9b64e
CO		 4650 goto mmio;
4651
22388a3c 4652 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4653 return X86EMUL_CONTINUE;
4654
4655mmio:
4656 /*
4657 * Is this MMIO handled locally?
4658 */
22388a3c 4659 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4660 if (handled == bytes)
bbd9b64e 4661 return X86EMUL_CONTINUE;
bbd9b64e 4662
70252a10
AK		 4663 gpa += handled;
4664 bytes -= handled;
4665 val += handled;
4666
87da7e66
XG		 4667 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4668 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4669 frag->gpa = gpa;
4670 frag->data = val;
4671 frag->len = bytes;
f78146b0 4672 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4673}
4674
52eb5a6d
XL		 4675static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4676 unsigned long addr,
22388a3c
XG		 4677 void *val, unsigned int bytes,
4678 struct x86_exception *exception,
0fbe9b0b 4679 const struct read_write_emulator_ops *ops)
bbd9b64e 4680{
0f65dd70 4681 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4682 gpa_t gpa;
4683 int rc;
4684
4685 if (ops->read_write_prepare &&
4686 ops->read_write_prepare(vcpu, val, bytes))
4687 return X86EMUL_CONTINUE;
4688
4689 vcpu->mmio_nr_fragments = 0;
0f65dd70 4690
bbd9b64e
CO		 4691 /* Crossing a page boundary? */
4692 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4693 int now;
bbd9b64e
CO		 4694
4695 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4696 rc = emulator_read_write_onepage(addr, val, now, exception,
4697 vcpu, ops);
4698
bbd9b64e
CO		 4699 if (rc != X86EMUL_CONTINUE)
4700 return rc;
4701 addr += now;
bac15531
NA		 4702 if (ctxt->mode != X86EMUL_MODE_PROT64)
4703 addr = (u32)addr;
bbd9b64e
CO		 4704 val += now;
4705 bytes -= now;
4706 }
22388a3c 4707
f78146b0
AK		 4708 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4709 vcpu, ops);
4710 if (rc != X86EMUL_CONTINUE)
4711 return rc;
4712
4713 if (!vcpu->mmio_nr_fragments)
4714 return rc;
4715
4716 gpa = vcpu->mmio_fragments[0].gpa;
4717
4718 vcpu->mmio_needed = 1;
4719 vcpu->mmio_cur_fragment = 0;
4720
87da7e66 4721 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4722 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4723 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4724 vcpu->run->mmio.phys_addr = gpa;
4725
4726 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4727}
4728
4729static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4730 unsigned long addr,
4731 void *val,
4732 unsigned int bytes,
4733 struct x86_exception *exception)
4734{
4735 return emulator_read_write(ctxt, addr, val, bytes,
4736 exception, &read_emultor);
4737}
4738
52eb5a6d 4739static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4740 unsigned long addr,
4741 const void *val,
4742 unsigned int bytes,
4743 struct x86_exception *exception)
4744{
4745 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4746 exception, &write_emultor);
bbd9b64e 4747}
bbd9b64e 4748
daea3e73
AK		 4749#define CMPXCHG_TYPE(t, ptr, old, new) \
4750 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4751
4752#ifdef CONFIG_X86_64
4753# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4754#else
4755# define CMPXCHG64(ptr, old, new) \
9749a6c0 4756 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4757#endif
4758
0f65dd70
AK		 4759static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4760 unsigned long addr,
bbd9b64e
CO		 4761 const void *old,
4762 const void *new,
4763 unsigned int bytes,
0f65dd70 4764 struct x86_exception *exception)
bbd9b64e 4765{
0f65dd70 4766 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4767 gpa_t gpa;
4768 struct page *page;
4769 char *kaddr;
4770 bool exchanged;
2bacc55c 4771
daea3e73
AK		 4772 /* guests cmpxchg8b have to be emulated atomically */
4773 if (bytes > 8 || (bytes & (bytes - 1)))
4774 goto emul_write;
10589a46 4775
daea3e73 4776 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4777
daea3e73
AK		 4778 if (gpa == UNMAPPED_GVA ||
4779 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4780 goto emul_write;
2bacc55c 4781
daea3e73
AK		 4782 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4783 goto emul_write;
72dc67a6 4784
54bf36aa 4785 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4786 if (is_error_page(page))
c19b8bd6 4787 goto emul_write;
72dc67a6 4788
8fd75e12 4789 kaddr = kmap_atomic(page);
daea3e73
AK		 4790 kaddr += offset_in_page(gpa);
4791 switch (bytes) {
4792 case 1:
4793 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4794 break;
4795 case 2:
4796 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4797 break;
4798 case 4:
4799 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4800 break;
4801 case 8:
4802 exchanged = CMPXCHG64(kaddr, old, new);
4803 break;
4804 default:
4805 BUG();
2bacc55c 4806 }
8fd75e12 4807 kunmap_atomic(kaddr);
daea3e73
AK		 4808 kvm_release_page_dirty(page);
4809
4810 if (!exchanged)
4811 return X86EMUL_CMPXCHG_FAILED;
4812
54bf36aa 4813 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4814 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4815
4816 return X86EMUL_CONTINUE;
4a5f48f6 4817
3200f405 4818emul_write:
daea3e73 4819 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4820
0f65dd70 4821 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4822}
4823
cf8f70bf
GN		 4824static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4825{
4826 /* TODO: String I/O for in kernel device */
4827 int r;
4828
4829 if (vcpu->arch.pio.in)
e32edf4f 4830 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4831 vcpu->arch.pio.size, pd);
4832 else
e32edf4f 4833 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4834 vcpu->arch.pio.port, vcpu->arch.pio.size,
4835 pd);
4836 return r;
4837}
4838
6f6fbe98
XG		 4839static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4840 unsigned short port, void *val,
4841 unsigned int count, bool in)
cf8f70bf 4842{
cf8f70bf 4843 vcpu->arch.pio.port = port;
6f6fbe98 4844 vcpu->arch.pio.in = in;
7972995b 4845 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4846 vcpu->arch.pio.size = size;
4847
4848 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4849 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4850 return 1;
4851 }
4852
4853 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4854 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4855 vcpu->run->io.size = size;
4856 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4857 vcpu->run->io.count = count;
4858 vcpu->run->io.port = port;
4859
4860 return 0;
4861}
4862
6f6fbe98
XG		 4863static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4864 int size, unsigned short port, void *val,
4865 unsigned int count)
cf8f70bf 4866{
ca1d4a9e 4867 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4868 int ret;
ca1d4a9e 4869
6f6fbe98
XG		 4870 if (vcpu->arch.pio.count)
4871 goto data_avail;
cf8f70bf 4872
6f6fbe98
XG		 4873 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4874 if (ret) {
4875data_avail:
4876 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4877 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4878 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4879 return 1;
4880 }
4881
cf8f70bf
GN		 4882 return 0;
4883}
4884
6f6fbe98
XG		 4885static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4886 int size, unsigned short port,
4887 const void *val, unsigned int count)
4888{
4889 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4890
4891 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4892 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4893 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4894}
4895
bbd9b64e
CO		 4896static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4897{
4898 return kvm_x86_ops->get_segment_base(vcpu, seg);
4899}
4900
3cb16fe7 4901static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4902{
3cb16fe7 4903 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4904}
4905
ae6a2375 4906static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4907{
4908 if (!need_emulate_wbinvd(vcpu))
4909 return X86EMUL_CONTINUE;
4910
4911 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4912 int cpu = get_cpu();
4913
4914 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4915 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4916 wbinvd_ipi, NULL, 1);
2eec7343 4917 put_cpu();
f5f48ee1 4918 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4919 } else
4920 wbinvd();
f5f48ee1
SY		 4921 return X86EMUL_CONTINUE;
4922}
5cb56059
JS		 4923
4924int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4925{
6affcbed
KH		 4926 kvm_emulate_wbinvd_noskip(vcpu);
4927 return kvm_skip_emulated_instruction(vcpu);
5cb56059 4928}
f5f48ee1
SY		 4929EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4930
5cb56059
JS		 4931
4932
bcaf5cc5
AK		 4933static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4934{
5cb56059 4935 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4936}
4937
52eb5a6d
XL		 4938static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4939 unsigned long *dest)
bbd9b64e 4940{
16f8a6f9 4941 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4942}
4943
52eb5a6d
XL		 4944static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4945 unsigned long value)
bbd9b64e 4946{
338dbc97 4947
717746e3 4948 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4949}
4950
52a46617 4951static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4952{
52a46617 4953 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4954}
4955
717746e3 4956static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4957{
717746e3 4958 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4959 unsigned long value;
4960
4961 switch (cr) {
4962 case 0:
4963 value = kvm_read_cr0(vcpu);
4964 break;
4965 case 2:
4966 value = vcpu->arch.cr2;
4967 break;
4968 case 3:
9f8fe504 4969 value = kvm_read_cr3(vcpu);
52a46617
GN		 4970 break;
4971 case 4:
4972 value = kvm_read_cr4(vcpu);
4973 break;
4974 case 8:
4975 value = kvm_get_cr8(vcpu);
4976 break;
4977 default:
a737f256 4978 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4979 return 0;
4980 }
4981
4982 return value;
4983}
4984
717746e3 4985static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4986{
717746e3 4987 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4988 int res = 0;
4989
52a46617
GN		 4990 switch (cr) {
4991 case 0:
49a9b07e 4992 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4993 break;
4994 case 2:
4995 vcpu->arch.cr2 = val;
4996 break;
4997 case 3:
2390218b 4998 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4999 break;
5000 case 4:
a83b29c6 5001 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5002 break;
5003 case 8:
eea1cff9 5004 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5005 break;
5006 default:
a737f256 5007 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5008 res = -1;
52a46617 5009 }
0f12244f
GN		 5010
5011 return res;
52a46617
GN		 5012}
5013
717746e3 5014static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5015{
717746e3 5016 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5017}
5018
4bff1e86 5019static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5020{
4bff1e86 5021 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5022}
5023
4bff1e86 5024static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5025{
4bff1e86 5026 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5027}
5028
1ac9d0cf
AK		 5029static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5030{
5031 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5032}
5033
5034static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5035{
5036 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5037}
5038
4bff1e86
AK		 5039static unsigned long emulator_get_cached_segment_base(
5040 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5041{
4bff1e86 5042 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5043}
5044
1aa36616
AK		 5045static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5046 struct desc_struct *desc, u32 *base3,
5047 int seg)
2dafc6c2
GN		 5048{
5049 struct kvm_segment var;
5050
4bff1e86 5051 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5052 *selector = var.selector;
2dafc6c2 5053
378a8b09
GN		 5054 if (var.unusable) {
5055 memset(desc, 0, sizeof(*desc));
2dafc6c2 5056 return false;
378a8b09 5057 }
2dafc6c2
GN		 5058
5059 if (var.g)
5060 var.limit >>= 12;
5061 set_desc_limit(desc, var.limit);
5062 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5063#ifdef CONFIG_X86_64
5064 if (base3)
5065 *base3 = var.base >> 32;
5066#endif
2dafc6c2
GN		 5067 desc->type = var.type;
5068 desc->s = var.s;
5069 desc->dpl = var.dpl;
5070 desc->p = var.present;
5071 desc->avl = var.avl;
5072 desc->l = var.l;
5073 desc->d = var.db;
5074 desc->g = var.g;
5075
5076 return true;
5077}
5078
1aa36616
AK		 5079static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5080 struct desc_struct *desc, u32 base3,
5081 int seg)
2dafc6c2 5082{
4bff1e86 5083 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5084 struct kvm_segment var;
5085
1aa36616 5086 var.selector = selector;
2dafc6c2 5087 var.base = get_desc_base(desc);
5601d05b
GN		 5088#ifdef CONFIG_X86_64
5089 var.base |= ((u64)base3) << 32;
5090#endif
2dafc6c2
GN		 5091 var.limit = get_desc_limit(desc);
5092 if (desc->g)
5093 var.limit = (var.limit << 12) | 0xfff;
5094 var.type = desc->type;
2dafc6c2
GN		 5095 var.dpl = desc->dpl;
5096 var.db = desc->d;
5097 var.s = desc->s;
5098 var.l = desc->l;
5099 var.g = desc->g;
5100 var.avl = desc->avl;
5101 var.present = desc->p;
5102 var.unusable = !var.present;
5103 var.padding = 0;
5104
5105 kvm_set_segment(vcpu, &var, seg);
5106 return;
5107}
5108
717746e3
AK		 5109static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5110 u32 msr_index, u64 *pdata)
5111{
609e36d3
PB		 5112 struct msr_data msr;
5113 int r;
5114
5115 msr.index = msr_index;
5116 msr.host_initiated = false;
5117 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5118 if (r)
5119 return r;
5120
5121 *pdata = msr.data;
5122 return 0;
717746e3
AK		 5123}
5124
5125static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5126 u32 msr_index, u64 data)
5127{
8fe8ab46
WA		 5128 struct msr_data msr;
5129
5130 msr.data = data;
5131 msr.index = msr_index;
5132 msr.host_initiated = false;
5133 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5134}
5135
64d60670
PB		 5136static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5137{
5138 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5139
5140 return vcpu->arch.smbase;
5141}
5142
5143static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5144{
5145 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5146
5147 vcpu->arch.smbase = smbase;
5148}
5149
67f4d428
NA		 5150static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5151 u32 pmc)
5152{
c6702c9d 5153 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5154}
5155
222d21aa
AK		 5156static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5157 u32 pmc, u64 *pdata)
5158{
c6702c9d 5159 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5160}
5161
6c3287f7
AK		 5162static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5163{
5164 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5165}
5166
5037f6f3
AK		 5167static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5168{
5169 preempt_disable();
5197b808 5170 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5171}
5172
5173static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5174{
5175 preempt_enable();
5176}
5177
2953538e 5178static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5179 struct x86_instruction_info *info,
c4f035c6
AK		 5180 enum x86_intercept_stage stage)
5181{
2953538e 5182 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5183}
5184
0017f93a 5185static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5186 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5187{
0017f93a 5188 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5189}
5190
dd856efa
AK		 5191static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5192{
5193 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5194}
5195
5196static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5197{
5198 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5199}
5200
801806d9
NA		 5201static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5202{
5203 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5204}
5205
6ed071f0
LP		 5206static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5207{
5208 return emul_to_vcpu(ctxt)->arch.hflags;
5209}
5210
5211static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5212{
5213 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5214}
5215
0225fb50 5216static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5217 .read_gpr = emulator_read_gpr,
5218 .write_gpr = emulator_write_gpr,
1871c602 5219 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5220 .write_std = kvm_write_guest_virt_system,
7a036a6f 5221 .read_phys = kvm_read_guest_phys_system,
1871c602 5222 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5223 .read_emulated = emulator_read_emulated,
5224 .write_emulated = emulator_write_emulated,
5225 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5226 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5227 .pio_in_emulated = emulator_pio_in_emulated,
5228 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5229 .get_segment = emulator_get_segment,
5230 .set_segment = emulator_set_segment,
5951c442 5231 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5232 .get_gdt = emulator_get_gdt,
160ce1f1 5233 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5234 .set_gdt = emulator_set_gdt,
5235 .set_idt = emulator_set_idt,
52a46617
GN		 5236 .get_cr = emulator_get_cr,
5237 .set_cr = emulator_set_cr,
9c537244 5238 .cpl = emulator_get_cpl,
35aa5375
GN		 5239 .get_dr = emulator_get_dr,
5240 .set_dr = emulator_set_dr,
64d60670
PB		 5241 .get_smbase = emulator_get_smbase,
5242 .set_smbase = emulator_set_smbase,
717746e3
AK		 5243 .set_msr = emulator_set_msr,
5244 .get_msr = emulator_get_msr,
67f4d428 5245 .check_pmc = emulator_check_pmc,
222d21aa 5246 .read_pmc = emulator_read_pmc,
6c3287f7 5247 .halt = emulator_halt,
bcaf5cc5 5248 .wbinvd = emulator_wbinvd,
d6aa1000 5249 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5250 .get_fpu = emulator_get_fpu,
5251 .put_fpu = emulator_put_fpu,
c4f035c6 5252 .intercept = emulator_intercept,
bdb42f5a 5253 .get_cpuid = emulator_get_cpuid,
801806d9 5254 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5255 .get_hflags = emulator_get_hflags,
5256 .set_hflags = emulator_set_hflags,
bbd9b64e
CO		 5257};
5258
95cb2295
GN		 5259static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5260{
37ccdcbe 5261 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5262 /*
5263 * an sti; sti; sequence only disable interrupts for the first
5264 * instruction. So, if the last instruction, be it emulated or
5265 * not, left the system with the INT_STI flag enabled, it
5266 * means that the last instruction is an sti. We should not
5267 * leave the flag on in this case. The same goes for mov ss
5268 */
37ccdcbe
PB		 5269 if (int_shadow & mask)
5270 mask = 0;
6addfc42 5271 if (unlikely(int_shadow || mask)) {
95cb2295 5272 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5273 if (!mask)
5274 kvm_make_request(KVM_REQ_EVENT, vcpu);
5275 }
95cb2295
GN		 5276}
5277
ef54bcfe 5278static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5279{
5280 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5281 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5282 return kvm_propagate_fault(vcpu, &ctxt->exception);
5283
5284 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5285 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5286 ctxt->exception.error_code);
54b8486f 5287 else
da9cb575 5288 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5289 return false;
54b8486f
GN		 5290}
5291
8ec4722d
MG		 5292static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5293{
adf52235 5294 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5295 int cs_db, cs_l;
5296
8ec4722d
MG		 5297 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5298
adf52235
TY		 5299 ctxt->eflags = kvm_get_rflags(vcpu);
5300 ctxt->eip = kvm_rip_read(vcpu);
5301 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5302 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5303 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5304 cs_db ? X86EMUL_MODE_PROT32 :
5305 X86EMUL_MODE_PROT16;
a584539b 5306 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5307 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5308 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5309
dd856efa 5310 init_decode_cache(ctxt);
7ae441ea 5311 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5312}
5313
71f9833b 5314int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5315{
9d74191a 5316 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5317 int ret;
5318
5319 init_emulate_ctxt(vcpu);
5320
9dac77fa
AK		 5321 ctxt->op_bytes = 2;
5322 ctxt->ad_bytes = 2;
5323 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5324 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5325
5326 if (ret != X86EMUL_CONTINUE)
5327 return EMULATE_FAIL;
5328
9dac77fa 5329 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5330 kvm_rip_write(vcpu, ctxt->eip);
5331 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5332
5333 if (irq == NMI_VECTOR)
7460fb4a 5334 vcpu->arch.nmi_pending = 0;
63995653
MG		 5335 else
5336 vcpu->arch.interrupt.pending = false;
5337
5338 return EMULATE_DONE;
5339}
5340EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5341
6d77dbfc
GN		 5342static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5343{
fc3a9157
JR		 5344 int r = EMULATE_DONE;
5345
6d77dbfc
GN		 5346 ++vcpu->stat.insn_emulation_fail;
5347 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5348 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5349 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5350 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5351 vcpu->run->internal.ndata = 0;
5352 r = EMULATE_FAIL;
5353 }
6d77dbfc 5354 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5355
5356 return r;
6d77dbfc
GN		 5357}
5358
93c05d3e 5359static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5360 bool write_fault_to_shadow_pgtable,
5361 int emulation_type)
a6f177ef 5362{
95b3cf69 5363 gpa_t gpa = cr2;
ba049e93 5364 kvm_pfn_t pfn;
a6f177ef 5365
991eebf9
GN		 5366 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5367 return false;
5368
95b3cf69
XG		 5369 if (!vcpu->arch.mmu.direct_map) {
5370 /*
5371 * Write permission should be allowed since only
5372 * write access need to be emulated.
5373 */
5374 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5375
95b3cf69
XG		 5376 /*
5377 * If the mapping is invalid in guest, let cpu retry
5378 * it to generate fault.
5379 */
5380 if (gpa == UNMAPPED_GVA)
5381 return true;
5382 }
a6f177ef 5383
8e3d9d06
XG		 5384 /*
5385 * Do not retry the unhandleable instruction if it faults on the
5386 * readonly host memory, otherwise it will goto a infinite loop:
5387 * retry instruction -> write #PF -> emulation fail -> retry
5388 * instruction -> ...
5389 */
5390 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5391
5392 /*
5393 * If the instruction failed on the error pfn, it can not be fixed,
5394 * report the error to userspace.
5395 */
5396 if (is_error_noslot_pfn(pfn))
5397 return false;
5398
5399 kvm_release_pfn_clean(pfn);
5400
5401 /* The instructions are well-emulated on direct mmu. */
5402 if (vcpu->arch.mmu.direct_map) {
5403 unsigned int indirect_shadow_pages;
5404
5405 spin_lock(&vcpu->kvm->mmu_lock);
5406 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5407 spin_unlock(&vcpu->kvm->mmu_lock);
5408
5409 if (indirect_shadow_pages)
5410 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5411
a6f177ef 5412 return true;
8e3d9d06 5413 }
a6f177ef 5414
95b3cf69
XG		 5415 /*
5416 * if emulation was due to access to shadowed page table
5417 * and it failed try to unshadow page and re-enter the
5418 * guest to let CPU execute the instruction.
5419 */
5420 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5421
5422 /*
5423 * If the access faults on its page table, it can not
5424 * be fixed by unprotecting shadow page and it should
5425 * be reported to userspace.
5426 */
5427 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5428}
5429
1cb3f3ae
XG		 5430static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5431 unsigned long cr2, int emulation_type)
5432{
5433 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5434 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5435
5436 last_retry_eip = vcpu->arch.last_retry_eip;
5437 last_retry_addr = vcpu->arch.last_retry_addr;
5438
5439 /*
5440 * If the emulation is caused by #PF and it is non-page_table
5441 * writing instruction, it means the VM-EXIT is caused by shadow
5442 * page protected, we can zap the shadow page and retry this
5443 * instruction directly.
5444 *
5445 * Note: if the guest uses a non-page-table modifying instruction
5446 * on the PDE that points to the instruction, then we will unmap
5447 * the instruction and go to an infinite loop. So, we cache the
5448 * last retried eip and the last fault address, if we meet the eip
5449 * and the address again, we can break out of the potential infinite
5450 * loop.
5451 */
5452 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5453
5454 if (!(emulation_type & EMULTYPE_RETRY))
5455 return false;
5456
5457 if (x86_page_table_writing_insn(ctxt))
5458 return false;
5459
5460 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5461 return false;
5462
5463 vcpu->arch.last_retry_eip = ctxt->eip;
5464 vcpu->arch.last_retry_addr = cr2;
5465
5466 if (!vcpu->arch.mmu.direct_map)
5467 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5468
22368028 5469 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5470
5471 return true;
5472}
5473
716d51ab
GN		 5474static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5475static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5476
64d60670 5477static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5478{
64d60670 5479 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5480 /* This is a good place to trace that we are exiting SMM. */
5481 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5482
c43203ca
PB		 5483 /* Process a latched INIT or SMI, if any. */
5484 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5485 }
699023e2
PB		 5486
5487 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5488}
5489
5490static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5491{
5492 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5493
a584539b 5494 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5495
5496 if (changed & HF_SMM_MASK)
5497 kvm_smm_changed(vcpu);
a584539b
PB		 5498}
5499
4a1e10d5
PB		 5500static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5501 unsigned long *db)
5502{
5503 u32 dr6 = 0;
5504 int i;
5505 u32 enable, rwlen;
5506
5507 enable = dr7;
5508 rwlen = dr7 >> 16;
5509 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5510 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5511 dr6 |= (1 << i);
5512 return dr6;
5513}
5514
6addfc42 5515static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5516{
5517 struct kvm_run *kvm_run = vcpu->run;
5518
5519 /*
6addfc42
PB		 5520 * rflags is the old, "raw" value of the flags. The new value has
5521 * not been saved yet.
663f4c61
PB		 5522 *
5523 * This is correct even for TF set by the guest, because "the
5524 * processor will not generate this exception after the instruction
5525 * that sets the TF flag".
5526 */
663f4c61
PB		 5527 if (unlikely(rflags & X86_EFLAGS_TF)) {
5528 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5529 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5530 DR6_RTM;
663f4c61
PB		 5531 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5532 kvm_run->debug.arch.exception = DB_VECTOR;
5533 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5534 *r = EMULATE_USER_EXIT;
5535 } else {
663f4c61
PB		 5536 /*
5537 * "Certain debug exceptions may clear bit 0-3. The
5538 * remaining contents of the DR6 register are never
5539 * cleared by the processor".
5540 */
5541 vcpu->arch.dr6 &= ~15;
6f43ed01 5542 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5543 kvm_queue_exception(vcpu, DB_VECTOR);
5544 }
5545 }
5546}
5547
6affcbed
KH		 5548int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5549{
5550 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5551 int r = EMULATE_DONE;
5552
5553 kvm_x86_ops->skip_emulated_instruction(vcpu);
5554 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5555 return r == EMULATE_DONE;
5556}
5557EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5558
4a1e10d5
PB		 5559static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5560{
4a1e10d5
PB		 5561 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5562 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5563 struct kvm_run *kvm_run = vcpu->run;
5564 unsigned long eip = kvm_get_linear_rip(vcpu);
5565 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5566 vcpu->arch.guest_debug_dr7,
5567 vcpu->arch.eff_db);
5568
5569 if (dr6 != 0) {
6f43ed01 5570 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5571 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5572 kvm_run->debug.arch.exception = DB_VECTOR;
5573 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5574 *r = EMULATE_USER_EXIT;
5575 return true;
5576 }
5577 }
5578
4161a569
NA		 5579 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5580 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5581 unsigned long eip = kvm_get_linear_rip(vcpu);
5582 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5583 vcpu->arch.dr7,
5584 vcpu->arch.db);
5585
5586 if (dr6 != 0) {
5587 vcpu->arch.dr6 &= ~15;
6f43ed01 5588 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5589 kvm_queue_exception(vcpu, DB_VECTOR);
5590 *r = EMULATE_DONE;
5591 return true;
5592 }
5593 }
5594
5595 return false;
5596}
5597
51d8b661
AP		 5598int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5599 unsigned long cr2,
dc25e89e
AP		 5600 int emulation_type,
5601 void *insn,
5602 int insn_len)
bbd9b64e 5603{
95cb2295 5604 int r;
9d74191a 5605 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5606 bool writeback = true;
93c05d3e 5607 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5608
93c05d3e
XG		 5609 /*
5610 * Clear write_fault_to_shadow_pgtable here to ensure it is
5611 * never reused.
5612 */
5613 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5614 kvm_clear_exception_queue(vcpu);
8d7d8102 5615
571008da 5616 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5617 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5618
5619 /*
5620 * We will reenter on the same instruction since
5621 * we do not set complete_userspace_io. This does not
5622 * handle watchpoints yet, those would be handled in
5623 * the emulate_ops.
5624 */
5625 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5626 return r;
5627
9d74191a
TY		 5628 ctxt->interruptibility = 0;
5629 ctxt->have_exception = false;
e0ad0b47 5630 ctxt->exception.vector = -1;
9d74191a 5631 ctxt->perm_ok = false;
bbd9b64e 5632
b51e974f 5633 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5634
9d74191a 5635 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5636
e46479f8 5637 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5638 ++vcpu->stat.insn_emulation;
1d2887e2 5639 if (r != EMULATION_OK) {
4005996e
AK		 5640 if (emulation_type & EMULTYPE_TRAP_UD)
5641 return EMULATE_FAIL;
991eebf9
GN		 5642 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5643 emulation_type))
bbd9b64e 5644 return EMULATE_DONE;
6d77dbfc
GN		 5645 if (emulation_type & EMULTYPE_SKIP)
5646 return EMULATE_FAIL;
5647 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5648 }
5649 }
5650
ba8afb6b 5651 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5652 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5653 if (ctxt->eflags & X86_EFLAGS_RF)
5654 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5655 return EMULATE_DONE;
5656 }
5657
1cb3f3ae
XG		 5658 if (retry_instruction(ctxt, cr2, emulation_type))
5659 return EMULATE_DONE;
5660
7ae441ea 5661 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5662 changes registers values during IO operation */
7ae441ea
GN		 5663 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5664 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5665 emulator_invalidate_register_cache(ctxt);
7ae441ea 5666 }
4d2179e1 5667
5cd21917 5668restart:
0f89b207
TL		 5669 /* Save the faulting GPA (cr2) in the address field */
5670 ctxt->exception.address = cr2;
5671
9d74191a 5672 r = x86_emulate_insn(ctxt);
bbd9b64e 5673
775fde86
JR		 5674 if (r == EMULATION_INTERCEPTED)
5675 return EMULATE_DONE;
5676
d2ddd1c4 5677 if (r == EMULATION_FAILED) {
991eebf9
GN		 5678 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5679 emulation_type))
c3cd7ffa
GN		 5680 return EMULATE_DONE;
5681
6d77dbfc 5682 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5683 }
5684
9d74191a 5685 if (ctxt->have_exception) {
d2ddd1c4 5686 r = EMULATE_DONE;
ef54bcfe
PB		 5687 if (inject_emulated_exception(vcpu))
5688 return r;
d2ddd1c4 5689 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5690 if (!vcpu->arch.pio.in) {
5691 /* FIXME: return into emulator if single-stepping. */
3457e419 5692 vcpu->arch.pio.count = 0;
0912c977 5693 } else {
7ae441ea 5694 writeback = false;
716d51ab
GN		 5695 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5696 }
ac0a48c3 5697 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5698 } else if (vcpu->mmio_needed) {
5699 if (!vcpu->mmio_is_write)
5700 writeback = false;
ac0a48c3 5701 r = EMULATE_USER_EXIT;
716d51ab 5702 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5703 } else if (r == EMULATION_RESTART)
5cd21917 5704 goto restart;
d2ddd1c4
GN		 5705 else
5706 r = EMULATE_DONE;
f850e2e6 5707
7ae441ea 5708 if (writeback) {
6addfc42 5709 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5710 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5711 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5712 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5713 if (r == EMULATE_DONE)
6addfc42 5714 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5715 if (!ctxt->have_exception ||
5716 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5717 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5718
5719 /*
5720 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5721 * do nothing, and it will be requested again as soon as
5722 * the shadow expires. But we still need to check here,
5723 * because POPF has no interrupt shadow.
5724 */
5725 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5726 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5727 } else
5728 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5729
5730 return r;
de7d789a 5731}
51d8b661 5732EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5733
cf8f70bf 5734int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5735{
cf8f70bf 5736 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5737 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5738 size, port, &val, 1);
cf8f70bf 5739 /* do not return to emulator after return from userspace */
7972995b 5740 vcpu->arch.pio.count = 0;
de7d789a
CO		 5741 return ret;
5742}
cf8f70bf 5743EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5744
8370c3d0
TL		 5745static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5746{
5747 unsigned long val;
5748
5749 /* We should only ever be called with arch.pio.count equal to 1 */
5750 BUG_ON(vcpu->arch.pio.count != 1);
5751
5752 /* For size less than 4 we merge, else we zero extend */
5753 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5754 : 0;
5755
5756 /*
5757 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5758 * the copy and tracing
5759 */
5760 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5761 vcpu->arch.pio.port, &val, 1);
5762 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5763
5764 return 1;
5765}
5766
5767int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5768{
5769 unsigned long val;
5770 int ret;
5771
5772 /* For size less than 4 we merge, else we zero extend */
5773 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5774
5775 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5776 &val, 1);
5777 if (ret) {
5778 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5779 return ret;
5780 }
5781
5782 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5783
5784 return 0;
5785}
5786EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5787
251a5fd6 5788static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5789{
0a3aee0d 5790 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5791 return 0;
8cfdc000
ZA		 5792}
5793
5794static void tsc_khz_changed(void *data)
c8076604 5795{
8cfdc000
ZA		 5796 struct cpufreq_freqs *freq = data;
5797 unsigned long khz = 0;
5798
5799 if (data)
5800 khz = freq->new;
5801 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5802 khz = cpufreq_quick_get(raw_smp_processor_id());
5803 if (!khz)
5804 khz = tsc_khz;
0a3aee0d 5805 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5806}
5807
c8076604
GH		 5808static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5809 void *data)
5810{
5811 struct cpufreq_freqs *freq = data;
5812 struct kvm *kvm;
5813 struct kvm_vcpu *vcpu;
5814 int i, send_ipi = 0;
5815
8cfdc000
ZA		 5816 /*
5817 * We allow guests to temporarily run on slowing clocks,
5818 * provided we notify them after, or to run on accelerating
5819 * clocks, provided we notify them before. Thus time never
5820 * goes backwards.
5821 *
5822 * However, we have a problem. We can't atomically update
5823 * the frequency of a given CPU from this function; it is
5824 * merely a notifier, which can be called from any CPU.
5825 * Changing the TSC frequency at arbitrary points in time
5826 * requires a recomputation of local variables related to
5827 * the TSC for each VCPU. We must flag these local variables
5828 * to be updated and be sure the update takes place with the
5829 * new frequency before any guests proceed.
5830 *
5831 * Unfortunately, the combination of hotplug CPU and frequency
5832 * change creates an intractable locking scenario; the order
5833 * of when these callouts happen is undefined with respect to
5834 * CPU hotplug, and they can race with each other. As such,
5835 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5836 * undefined; you can actually have a CPU frequency change take
5837 * place in between the computation of X and the setting of the
5838 * variable. To protect against this problem, all updates of
5839 * the per_cpu tsc_khz variable are done in an interrupt
5840 * protected IPI, and all callers wishing to update the value
5841 * must wait for a synchronous IPI to complete (which is trivial
5842 * if the caller is on the CPU already). This establishes the
5843 * necessary total order on variable updates.
5844 *
5845 * Note that because a guest time update may take place
5846 * anytime after the setting of the VCPU's request bit, the
5847 * correct TSC value must be set before the request. However,
5848 * to ensure the update actually makes it to any guest which
5849 * starts running in hardware virtualization between the set
5850 * and the acquisition of the spinlock, we must also ping the
5851 * CPU after setting the request bit.
5852 *
5853 */
5854
c8076604
GH		 5855 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5856 return 0;
5857 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5858 return 0;
8cfdc000
ZA		 5859
5860 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5861
2f303b74 5862 spin_lock(&kvm_lock);
c8076604 5863 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5864 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5865 if (vcpu->cpu != freq->cpu)
5866 continue;
c285545f 5867 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5868 if (vcpu->cpu != smp_processor_id())
8cfdc000 5869 send_ipi = 1;
c8076604
GH		 5870 }
5871 }
2f303b74 5872 spin_unlock(&kvm_lock);
c8076604
GH		 5873
5874 if (freq->old < freq->new && send_ipi) {
5875 /*
5876 * We upscale the frequency. Must make the guest
5877 * doesn't see old kvmclock values while running with
5878 * the new frequency, otherwise we risk the guest sees
5879 * time go backwards.
5880 *
5881 * In case we update the frequency for another cpu
5882 * (which might be in guest context) send an interrupt
5883 * to kick the cpu out of guest context. Next time
5884 * guest context is entered kvmclock will be updated,
5885 * so the guest will not see stale values.
5886 */
8cfdc000 5887 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5888 }
5889 return 0;
5890}
5891
5892static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5893 .notifier_call = kvmclock_cpufreq_notifier
5894};
5895
251a5fd6 5896static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 5897{
251a5fd6
SAS		 5898 tsc_khz_changed(NULL);
5899 return 0;
8cfdc000
ZA		 5900}
5901
b820cc0c
ZA		 5902static void kvm_timer_init(void)
5903{
c285545f 5904 max_tsc_khz = tsc_khz;
460dd42e 5905
b820cc0c 5906 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5907#ifdef CONFIG_CPU_FREQ
5908 struct cpufreq_policy policy;
758f588d
BP		 5909 int cpu;
5910
c285545f 5911 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5912 cpu = get_cpu();
5913 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5914 if (policy.cpuinfo.max_freq)
5915 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5916 put_cpu();
c285545f 5917#endif
b820cc0c
ZA		 5918 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5919 CPUFREQ_TRANSITION_NOTIFIER);
5920 }
c285545f 5921 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 5922
73c1b41e 5923 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 5924 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 5925}
5926
ff9d07a0
ZY		 5927static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5928
f5132b01 5929int kvm_is_in_guest(void)
ff9d07a0 5930{
086c9855 5931 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5932}
5933
5934static int kvm_is_user_mode(void)
5935{
5936 int user_mode = 3;
dcf46b94 5937
086c9855
AS		 5938 if (__this_cpu_read(current_vcpu))
5939 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5940
ff9d07a0
ZY		 5941 return user_mode != 0;
5942}
5943
5944static unsigned long kvm_get_guest_ip(void)
5945{
5946 unsigned long ip = 0;
dcf46b94 5947
086c9855
AS		 5948 if (__this_cpu_read(current_vcpu))
5949 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5950
ff9d07a0
ZY		 5951 return ip;
5952}
5953
5954static struct perf_guest_info_callbacks kvm_guest_cbs = {
5955 .is_in_guest = kvm_is_in_guest,
5956 .is_user_mode = kvm_is_user_mode,
5957 .get_guest_ip = kvm_get_guest_ip,
5958};
5959
5960void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5961{
086c9855 5962 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5963}
5964EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5965
5966void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5967{
086c9855 5968 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5969}
5970EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5971
ce88decf
XG		 5972static void kvm_set_mmio_spte_mask(void)
5973{
5974 u64 mask;
5975 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5976
5977 /*
5978 * Set the reserved bits and the present bit of an paging-structure
5979 * entry to generate page fault with PFER.RSV = 1.
5980 */
885032b9 5981 /* Mask the reserved physical address bits. */
d1431483 5982 mask = rsvd_bits(maxphyaddr, 51);
885032b9 5983
885032b9 5984 /* Set the present bit. */
ce88decf
XG		 5985 mask |= 1ull;
5986
5987#ifdef CONFIG_X86_64
5988 /*
5989 * If reserved bit is not supported, clear the present bit to disable
5990 * mmio page fault.
5991 */
5992 if (maxphyaddr == 52)
5993 mask &= ~1ull;
5994#endif
5995
5996 kvm_mmu_set_mmio_spte_mask(mask);
5997}
5998
16e8d74d
MT		 5999#ifdef CONFIG_X86_64
6000static void pvclock_gtod_update_fn(struct work_struct *work)
6001{
d828199e
MT		 6002 struct kvm *kvm;
6003
6004 struct kvm_vcpu *vcpu;
6005 int i;
6006
2f303b74 6007 spin_lock(&kvm_lock);
d828199e
MT		 6008 list_for_each_entry(kvm, &vm_list, vm_list)
6009 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6010 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6011 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6012 spin_unlock(&kvm_lock);
16e8d74d
MT		 6013}
6014
6015static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6016
6017/*
6018 * Notification about pvclock gtod data update.
6019 */
6020static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6021 void *priv)
6022{
6023 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6024 struct timekeeper *tk = priv;
6025
6026 update_pvclock_gtod(tk);
6027
6028 /* disable master clock if host does not trust, or does not
6029 * use, TSC clocksource
6030 */
6031 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6032 atomic_read(&kvm_guest_has_master_clock) != 0)
6033 queue_work(system_long_wq, &pvclock_gtod_work);
6034
6035 return 0;
6036}
6037
6038static struct notifier_block pvclock_gtod_notifier = {
6039 .notifier_call = pvclock_gtod_notify,
6040};
6041#endif
6042
f8c16bba 6043int kvm_arch_init(void *opaque)
043405e1 6044{
b820cc0c 6045 int r;
6b61edf7 6046 struct kvm_x86_ops *ops = opaque;
f8c16bba 6047
f8c16bba
ZX		 6048 if (kvm_x86_ops) {
6049 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6050 r = -EEXIST;
6051 goto out;
f8c16bba
ZX		 6052 }
6053
6054 if (!ops->cpu_has_kvm_support()) {
6055 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6056 r = -EOPNOTSUPP;
6057 goto out;
f8c16bba
ZX		 6058 }
6059 if (ops->disabled_by_bios()) {
6060 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6061 r = -EOPNOTSUPP;
6062 goto out;
f8c16bba
ZX		 6063 }
6064
013f6a5d
MT		 6065 r = -ENOMEM;
6066 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6067 if (!shared_msrs) {
6068 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6069 goto out;
6070 }
6071
97db56ce
AK		 6072 r = kvm_mmu_module_init();
6073 if (r)
013f6a5d 6074 goto out_free_percpu;
97db56ce 6075
ce88decf 6076 kvm_set_mmio_spte_mask();
97db56ce 6077
f8c16bba 6078 kvm_x86_ops = ops;
920c8377 6079
7b52345e 6080 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6081 PT_DIRTY_MASK, PT64_NX_MASK, 0,
f160c7b7 6082 PT_PRESENT_MASK, 0);
b820cc0c 6083 kvm_timer_init();
c8076604 6084
ff9d07a0
ZY		 6085 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6086
d366bf7e 6087 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6088 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6089
c5cc421b 6090 kvm_lapic_init();
16e8d74d
MT		 6091#ifdef CONFIG_X86_64
6092 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6093#endif
6094
f8c16bba 6095 return 0;
56c6d28a 6096
013f6a5d
MT		 6097out_free_percpu:
6098 free_percpu(shared_msrs);
56c6d28a 6099out:
56c6d28a 6100 return r;
043405e1 6101}
8776e519 6102
f8c16bba
ZX		 6103void kvm_arch_exit(void)
6104{
cef84c30 6105 kvm_lapic_exit();
ff9d07a0
ZY		 6106 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6107
888d256e
JK		 6108 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6109 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6110 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6111 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6112#ifdef CONFIG_X86_64
6113 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6114#endif
f8c16bba 6115 kvm_x86_ops = NULL;
56c6d28a 6116 kvm_mmu_module_exit();
013f6a5d 6117 free_percpu(shared_msrs);
56c6d28a 6118}
f8c16bba 6119
5cb56059 6120int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6121{
6122 ++vcpu->stat.halt_exits;
35754c98 6123 if (lapic_in_kernel(vcpu)) {
a4535290 6124 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6125 return 1;
6126 } else {
6127 vcpu->run->exit_reason = KVM_EXIT_HLT;
6128 return 0;
6129 }
6130}
5cb56059
JS		 6131EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6132
6133int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6134{
6affcbed
KH		 6135 int ret = kvm_skip_emulated_instruction(vcpu);
6136 /*
6137 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6138 * KVM_EXIT_DEBUG here.
6139 */
6140 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6141}
8776e519
HB		 6142EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6143
8ef81a9a 6144#ifdef CONFIG_X86_64
55dd00a7
MT		 6145static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6146 unsigned long clock_type)
6147{
6148 struct kvm_clock_pairing clock_pairing;
6149 struct timespec ts;
80fbd89c 6150 u64 cycle;
55dd00a7
MT		 6151 int ret;
6152
6153 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6154 return -KVM_EOPNOTSUPP;
6155
6156 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6157 return -KVM_EOPNOTSUPP;
6158
6159 clock_pairing.sec = ts.tv_sec;
6160 clock_pairing.nsec = ts.tv_nsec;
6161 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6162 clock_pairing.flags = 0;
6163
6164 ret = 0;
6165 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6166 sizeof(struct kvm_clock_pairing)))
6167 ret = -KVM_EFAULT;
6168
6169 return ret;
6170}
8ef81a9a 6171#endif
55dd00a7 6172
6aef266c
SV		 6173/*
6174 * kvm_pv_kick_cpu_op: Kick a vcpu.
6175 *
6176 * @apicid - apicid of vcpu to be kicked.
6177 */
6178static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6179{
24d2166b 6180 struct kvm_lapic_irq lapic_irq;
6aef266c 6181
24d2166b
R		 6182 lapic_irq.shorthand = 0;
6183 lapic_irq.dest_mode = 0;
6184 lapic_irq.dest_id = apicid;
93bbf0b8 6185 lapic_irq.msi_redir_hint = false;
6aef266c 6186
24d2166b 6187 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6188 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6189}
6190
d62caabb
AS		 6191void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6192{
6193 vcpu->arch.apicv_active = false;
6194 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6195}
6196
8776e519
HB		 6197int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6198{
6199 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6200 int op_64_bit, r;
8776e519 6201
6affcbed 6202 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6203
55cd8e5a
GN		 6204 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6205 return kvm_hv_hypercall(vcpu);
6206
5fdbf976
MT		 6207 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6208 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6209 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6210 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6211 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6212
229456fc 6213 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6214
a449c7aa
NA		 6215 op_64_bit = is_64_bit_mode(vcpu);
6216 if (!op_64_bit) {
8776e519
HB		 6217 nr &= 0xFFFFFFFF;
6218 a0 &= 0xFFFFFFFF;
6219 a1 &= 0xFFFFFFFF;
6220 a2 &= 0xFFFFFFFF;
6221 a3 &= 0xFFFFFFFF;
6222 }
6223
07708c4a
JK		 6224 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6225 ret = -KVM_EPERM;
6226 goto out;
6227 }
6228
8776e519 6229 switch (nr) {
b93463aa
AK		 6230 case KVM_HC_VAPIC_POLL_IRQ:
6231 ret = 0;
6232 break;
6aef266c
SV		 6233 case KVM_HC_KICK_CPU:
6234 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6235 ret = 0;
6236 break;
8ef81a9a 6237#ifdef CONFIG_X86_64
55dd00a7
MT		 6238 case KVM_HC_CLOCK_PAIRING:
6239 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6240 break;
8ef81a9a 6241#endif
8776e519
HB		 6242 default:
6243 ret = -KVM_ENOSYS;
6244 break;
6245 }
07708c4a 6246out:
a449c7aa
NA		 6247 if (!op_64_bit)
6248 ret = (u32)ret;
5fdbf976 6249 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6250 ++vcpu->stat.hypercalls;
2f333bcb 6251 return r;
8776e519
HB		 6252}
6253EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6254
b6785def 6255static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6256{
d6aa1000 6257 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6258 char instruction[3];
5fdbf976 6259 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6260
8776e519 6261 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6262
ce2e852e
DV		 6263 return emulator_write_emulated(ctxt, rip, instruction, 3,
6264 &ctxt->exception);
8776e519
HB		 6265}
6266
851ba692 6267static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6268{
782d422b
MG		 6269 return vcpu->run->request_interrupt_window &&
6270 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6271}
6272
851ba692 6273static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6274{
851ba692
AK		 6275 struct kvm_run *kvm_run = vcpu->run;
6276
91586a3b 6277 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6278 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6279 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6280 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6281 kvm_run->ready_for_interrupt_injection =
6282 pic_in_kernel(vcpu->kvm) ||
782d422b 6283 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6284}
6285
95ba8273
GN		 6286static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6287{
6288 int max_irr, tpr;
6289
6290 if (!kvm_x86_ops->update_cr8_intercept)
6291 return;
6292
bce87cce 6293 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6294 return;
6295
d62caabb
AS		 6296 if (vcpu->arch.apicv_active)
6297 return;
6298
8db3baa2
GN		 6299 if (!vcpu->arch.apic->vapic_addr)
6300 max_irr = kvm_lapic_find_highest_irr(vcpu);
6301 else
6302 max_irr = -1;
95ba8273
GN		 6303
6304 if (max_irr != -1)
6305 max_irr >>= 4;
6306
6307 tpr = kvm_lapic_get_cr8(vcpu);
6308
6309 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6310}
6311
b6b8a145 6312static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6313{
b6b8a145
JK		 6314 int r;
6315
95ba8273 6316 /* try to reinject previous events if any */
b59bb7bd 6317 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6318 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6319 vcpu->arch.exception.has_error_code,
6320 vcpu->arch.exception.error_code);
d6e8c854
NA		 6321
6322 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6323 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6324 X86_EFLAGS_RF);
6325
6bdf0662
NA		 6326 if (vcpu->arch.exception.nr == DB_VECTOR &&
6327 (vcpu->arch.dr7 & DR7_GD)) {
6328 vcpu->arch.dr7 &= ~DR7_GD;
6329 kvm_update_dr7(vcpu);
6330 }
6331
b59bb7bd
GN		 6332 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6333 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6334 vcpu->arch.exception.error_code,
6335 vcpu->arch.exception.reinject);
b6b8a145 6336 return 0;
b59bb7bd
GN		 6337 }
6338
95ba8273
GN		 6339 if (vcpu->arch.nmi_injected) {
6340 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6341 return 0;
95ba8273
GN		 6342 }
6343
6344 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6345 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6346 return 0;
6347 }
6348
6349 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6350 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6351 if (r != 0)
6352 return r;
95ba8273
GN		 6353 }
6354
6355 /* try to inject new event if pending */
c43203ca
PB		 6356 if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
6357 vcpu->arch.smi_pending = false;
ee2cd4b7 6358 enter_smm(vcpu);
c43203ca 6359 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6360 --vcpu->arch.nmi_pending;
6361 vcpu->arch.nmi_injected = true;
6362 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6363 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6364 /*
6365 * Because interrupts can be injected asynchronously, we are
6366 * calling check_nested_events again here to avoid a race condition.
6367 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6368 * proposal and current concerns. Perhaps we should be setting
6369 * KVM_REQ_EVENT only on certain events and not unconditionally?
6370 */
6371 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6372 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6373 if (r != 0)
6374 return r;
6375 }
95ba8273 6376 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6377 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6378 false);
6379 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6380 }
6381 }
ee2cd4b7 6382
b6b8a145 6383 return 0;
95ba8273
GN		 6384}
6385
7460fb4a
AK		 6386static void process_nmi(struct kvm_vcpu *vcpu)
6387{
6388 unsigned limit = 2;
6389
6390 /*
6391 * x86 is limited to one NMI running, and one NMI pending after it.
6392 * If an NMI is already in progress, limit further NMIs to just one.
6393 * Otherwise, allow two (and we'll inject the first one immediately).
6394 */
6395 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6396 limit = 1;
6397
6398 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6399 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6400 kvm_make_request(KVM_REQ_EVENT, vcpu);
6401}
6402
660a5d51
PB		 6403#define put_smstate(type, buf, offset, val) \
6404 *(type *)((buf) + (offset) - 0x7e00) = val
6405
ee2cd4b7 6406static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6407{
6408 u32 flags = 0;
6409 flags |= seg->g << 23;
6410 flags |= seg->db << 22;
6411 flags |= seg->l << 21;
6412 flags |= seg->avl << 20;
6413 flags |= seg->present << 15;
6414 flags |= seg->dpl << 13;
6415 flags |= seg->s << 12;
6416 flags |= seg->type << 8;
6417 return flags;
6418}
6419
ee2cd4b7 6420static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6421{
6422 struct kvm_segment seg;
6423 int offset;
6424
6425 kvm_get_segment(vcpu, &seg, n);
6426 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6427
6428 if (n < 3)
6429 offset = 0x7f84 + n * 12;
6430 else
6431 offset = 0x7f2c + (n - 3) * 12;
6432
6433 put_smstate(u32, buf, offset + 8, seg.base);
6434 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6435 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6436}
6437
efbb288a 6438#ifdef CONFIG_X86_64
ee2cd4b7 6439static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6440{
6441 struct kvm_segment seg;
6442 int offset;
6443 u16 flags;
6444
6445 kvm_get_segment(vcpu, &seg, n);
6446 offset = 0x7e00 + n * 16;
6447
ee2cd4b7 6448 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6449 put_smstate(u16, buf, offset, seg.selector);
6450 put_smstate(u16, buf, offset + 2, flags);
6451 put_smstate(u32, buf, offset + 4, seg.limit);
6452 put_smstate(u64, buf, offset + 8, seg.base);
6453}
efbb288a 6454#endif
660a5d51 6455
ee2cd4b7 6456static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6457{
6458 struct desc_ptr dt;
6459 struct kvm_segment seg;
6460 unsigned long val;
6461 int i;
6462
6463 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6464 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6465 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6466 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6467
6468 for (i = 0; i < 8; i++)
6469 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6470
6471 kvm_get_dr(vcpu, 6, &val);
6472 put_smstate(u32, buf, 0x7fcc, (u32)val);
6473 kvm_get_dr(vcpu, 7, &val);
6474 put_smstate(u32, buf, 0x7fc8, (u32)val);
6475
6476 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6477 put_smstate(u32, buf, 0x7fc4, seg.selector);
6478 put_smstate(u32, buf, 0x7f64, seg.base);
6479 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6480 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6481
6482 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6483 put_smstate(u32, buf, 0x7fc0, seg.selector);
6484 put_smstate(u32, buf, 0x7f80, seg.base);
6485 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6486 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6487
6488 kvm_x86_ops->get_gdt(vcpu, &dt);
6489 put_smstate(u32, buf, 0x7f74, dt.address);
6490 put_smstate(u32, buf, 0x7f70, dt.size);
6491
6492 kvm_x86_ops->get_idt(vcpu, &dt);
6493 put_smstate(u32, buf, 0x7f58, dt.address);
6494 put_smstate(u32, buf, 0x7f54, dt.size);
6495
6496 for (i = 0; i < 6; i++)
ee2cd4b7 6497 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6498
6499 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6500
6501 /* revision id */
6502 put_smstate(u32, buf, 0x7efc, 0x00020000);
6503 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6504}
6505
ee2cd4b7 6506static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6507{
6508#ifdef CONFIG_X86_64
6509 struct desc_ptr dt;
6510 struct kvm_segment seg;
6511 unsigned long val;
6512 int i;
6513
6514 for (i = 0; i < 16; i++)
6515 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6516
6517 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6518 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6519
6520 kvm_get_dr(vcpu, 6, &val);
6521 put_smstate(u64, buf, 0x7f68, val);
6522 kvm_get_dr(vcpu, 7, &val);
6523 put_smstate(u64, buf, 0x7f60, val);
6524
6525 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6526 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6527 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6528
6529 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6530
6531 /* revision id */
6532 put_smstate(u32, buf, 0x7efc, 0x00020064);
6533
6534 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6535
6536 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6537 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6538 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6539 put_smstate(u32, buf, 0x7e94, seg.limit);
6540 put_smstate(u64, buf, 0x7e98, seg.base);
6541
6542 kvm_x86_ops->get_idt(vcpu, &dt);
6543 put_smstate(u32, buf, 0x7e84, dt.size);
6544 put_smstate(u64, buf, 0x7e88, dt.address);
6545
6546 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6547 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6548 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6549 put_smstate(u32, buf, 0x7e74, seg.limit);
6550 put_smstate(u64, buf, 0x7e78, seg.base);
6551
6552 kvm_x86_ops->get_gdt(vcpu, &dt);
6553 put_smstate(u32, buf, 0x7e64, dt.size);
6554 put_smstate(u64, buf, 0x7e68, dt.address);
6555
6556 for (i = 0; i < 6; i++)
ee2cd4b7 6557 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6558#else
6559 WARN_ON_ONCE(1);
6560#endif
6561}
6562
ee2cd4b7 6563static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6564{
660a5d51 6565 struct kvm_segment cs, ds;
18c3626e 6566 struct desc_ptr dt;
660a5d51
PB		 6567 char buf[512];
6568 u32 cr0;
6569
660a5d51
PB		 6570 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6571 vcpu->arch.hflags |= HF_SMM_MASK;
6572 memset(buf, 0, 512);
6573 if (guest_cpuid_has_longmode(vcpu))
ee2cd4b7 6574 enter_smm_save_state_64(vcpu, buf);
660a5d51 6575 else
ee2cd4b7 6576 enter_smm_save_state_32(vcpu, buf);
660a5d51 6577
54bf36aa 6578 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6579
6580 if (kvm_x86_ops->get_nmi_mask(vcpu))
6581 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6582 else
6583 kvm_x86_ops->set_nmi_mask(vcpu, true);
6584
6585 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6586 kvm_rip_write(vcpu, 0x8000);
6587
6588 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6589 kvm_x86_ops->set_cr0(vcpu, cr0);
6590 vcpu->arch.cr0 = cr0;
6591
6592 kvm_x86_ops->set_cr4(vcpu, 0);
6593
18c3626e
PB		 6594 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6595 dt.address = dt.size = 0;
6596 kvm_x86_ops->set_idt(vcpu, &dt);
6597
660a5d51
PB		 6598 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6599
6600 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6601 cs.base = vcpu->arch.smbase;
6602
6603 ds.selector = 0;
6604 ds.base = 0;
6605
6606 cs.limit = ds.limit = 0xffffffff;
6607 cs.type = ds.type = 0x3;
6608 cs.dpl = ds.dpl = 0;
6609 cs.db = ds.db = 0;
6610 cs.s = ds.s = 1;
6611 cs.l = ds.l = 0;
6612 cs.g = ds.g = 1;
6613 cs.avl = ds.avl = 0;
6614 cs.present = ds.present = 1;
6615 cs.unusable = ds.unusable = 0;
6616 cs.padding = ds.padding = 0;
6617
6618 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6619 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6620 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6621 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6622 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6623 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6624
6625 if (guest_cpuid_has_longmode(vcpu))
6626 kvm_x86_ops->set_efer(vcpu, 0);
6627
6628 kvm_update_cpuid(vcpu);
6629 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6630}
6631
ee2cd4b7 6632static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6633{
6634 vcpu->arch.smi_pending = true;
6635 kvm_make_request(KVM_REQ_EVENT, vcpu);
6636}
6637
2860c4b1
PB		 6638void kvm_make_scan_ioapic_request(struct kvm *kvm)
6639{
6640 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6641}
6642
3d81bc7e 6643static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6644{
5c919412
AS		 6645 u64 eoi_exit_bitmap[4];
6646
3d81bc7e
YZ		 6647 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6648 return;
c7c9c56c 6649
6308630b 6650 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6651
b053b2ae 6652 if (irqchip_split(vcpu->kvm))
6308630b 6653 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6654 else {
76dfafd5 6655 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb 6656 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6657 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6658 }
5c919412
AS		 6659 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6660 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6661 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6662}
6663
a70656b6
RK		 6664static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6665{
6666 ++vcpu->stat.tlb_flush;
6667 kvm_x86_ops->tlb_flush(vcpu);
6668}
6669
4256f43f
TC		 6670void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6671{
c24ae0dc
TC		 6672 struct page *page = NULL;
6673
35754c98 6674 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6675 return;
6676
4256f43f
TC		 6677 if (!kvm_x86_ops->set_apic_access_page_addr)
6678 return;
6679
c24ae0dc 6680 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6681 if (is_error_page(page))
6682 return;
c24ae0dc
TC		 6683 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6684
6685 /*
6686 * Do not pin apic access page in memory, the MMU notifier
6687 * will call us again if it is migrated or swapped out.
6688 */
6689 put_page(page);
4256f43f
TC		 6690}
6691EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6692
fe71557a
TC		 6693void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6694 unsigned long address)
6695{
c24ae0dc
TC		 6696 /*
6697 * The physical address of apic access page is stored in the VMCS.
6698 * Update it when it becomes invalid.
6699 */
6700 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6701 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6702}
6703
9357d939 6704/*
362c698f 6705 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6706 * exiting to the userspace. Otherwise, the value will be returned to the
6707 * userspace.
6708 */
851ba692 6709static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6710{
6711 int r;
62a193ed
MG		 6712 bool req_int_win =
6713 dm_request_for_irq_injection(vcpu) &&
6714 kvm_cpu_accept_dm_intr(vcpu);
6715
730dca42 6716 bool req_immediate_exit = false;
b6c7a5dc 6717
3e007509 6718 if (vcpu->requests) {
a8eeb04a 6719 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6720 kvm_mmu_unload(vcpu);
a8eeb04a 6721 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6722 __kvm_migrate_timers(vcpu);
d828199e
MT		 6723 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6724 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6725 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6726 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6727 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6728 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6729 if (unlikely(r))
6730 goto out;
6731 }
a8eeb04a 6732 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6733 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6734 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6735 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6736 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6737 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6738 r = 0;
6739 goto out;
6740 }
a8eeb04a 6741 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6742 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6743 r = 0;
6744 goto out;
6745 }
af585b92
GN		 6746 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6747 /* Page is swapped out. Do synthetic halt */
6748 vcpu->arch.apf.halted = true;
6749 r = 1;
6750 goto out;
6751 }
c9aaa895
GC		 6752 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6753 record_steal_time(vcpu);
64d60670
PB		 6754 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6755 process_smi(vcpu);
7460fb4a
AK		 6756 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6757 process_nmi(vcpu);
f5132b01 6758 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6759 kvm_pmu_handle_event(vcpu);
f5132b01 6760 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6761 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6762 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6763 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6764 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6765 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6766 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6767 vcpu->run->eoi.vector =
6768 vcpu->arch.pending_ioapic_eoi;
6769 r = 0;
6770 goto out;
6771 }
6772 }
3d81bc7e
YZ		 6773 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6774 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6775 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6776 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6777 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6778 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6779 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6780 r = 0;
6781 goto out;
6782 }
e516cebb
AS		 6783 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6784 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6785 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6786 r = 0;
6787 goto out;
6788 }
db397571
AS		 6789 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6790 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6791 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6792 r = 0;
6793 goto out;
6794 }
f3b138c5
AS		 6795
6796 /*
6797 * KVM_REQ_HV_STIMER has to be processed after
6798 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6799 * depend on the guest clock being up-to-date
6800 */
1f4b34f8
AS		 6801 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6802 kvm_hv_process_stimers(vcpu);
2f52d58c 6803 }
b93463aa 6804
b463a6f7 6805 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 6806 ++vcpu->stat.req_event;
66450a21
JK		 6807 kvm_apic_accept_events(vcpu);
6808 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6809 r = 1;
6810 goto out;
6811 }
6812
b6b8a145
JK		 6813 if (inject_pending_event(vcpu, req_int_win) != 0)
6814 req_immediate_exit = true;
321c5658 6815 else {
c43203ca
PB		 6816 /* Enable NMI/IRQ window open exits if needed.
6817 *
6818 * SMIs have two cases: 1) they can be nested, and
6819 * then there is nothing to do here because RSM will
6820 * cause a vmexit anyway; 2) or the SMI can be pending
6821 * because inject_pending_event has completed the
6822 * injection of an IRQ or NMI from the previous vmexit,
6823 * and then we request an immediate exit to inject the SMI.
6824 */
6825 if (vcpu->arch.smi_pending && !is_smm(vcpu))
6826 req_immediate_exit = true;
321c5658
YS		 6827 if (vcpu->arch.nmi_pending)
6828 kvm_x86_ops->enable_nmi_window(vcpu);
6829 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6830 kvm_x86_ops->enable_irq_window(vcpu);
6831 }
b463a6f7
AK		 6832
6833 if (kvm_lapic_enabled(vcpu)) {
6834 update_cr8_intercept(vcpu);
6835 kvm_lapic_sync_to_vapic(vcpu);
6836 }
6837 }
6838
d8368af8
AK		 6839 r = kvm_mmu_reload(vcpu);
6840 if (unlikely(r)) {
d905c069 6841 goto cancel_injection;
d8368af8
AK		 6842 }
6843
b6c7a5dc
HB		 6844 preempt_disable();
6845
6846 kvm_x86_ops->prepare_guest_switch(vcpu);
bd7e5b08 6847 kvm_load_guest_fpu(vcpu);
b95234c8
PB		 6848
6849 /*
6850 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
6851 * IPI are then delayed after guest entry, which ensures that they
6852 * result in virtual interrupt delivery.
6853 */
6854 local_irq_disable();
6b7e2d09
XG		 6855 vcpu->mode = IN_GUEST_MODE;
6856
01b71917
MT		 6857 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6858
0f127d12 6859 /*
b95234c8 6860 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 6861 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 6862 *
6863 * 2) For APICv, we should set ->mode before checking PIR.ON. This
6864 * pairs with the memory barrier implicit in pi_test_and_set_on
6865 * (see vmx_deliver_posted_interrupt).
6866 *
6867 * 3) This also orders the write to mode from any reads to the page
6868 * tables done while the VCPU is running. Please see the comment
6869 * in kvm_flush_remote_tlbs.
6b7e2d09 6870 */
01b71917 6871 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6872
b95234c8
PB		 6873 /*
6874 * This handles the case where a posted interrupt was
6875 * notified with kvm_vcpu_kick.
6876 */
6877 if (kvm_lapic_enabled(vcpu)) {
6878 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6879 kvm_x86_ops->sync_pir_to_irr(vcpu);
6880 }
32f88400 6881
6b7e2d09 6882 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6883 || need_resched() || signal_pending(current)) {
6b7e2d09 6884 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6885 smp_wmb();
6c142801
AK		 6886 local_irq_enable();
6887 preempt_enable();
01b71917 6888 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6889 r = 1;
d905c069 6890 goto cancel_injection;
6c142801
AK		 6891 }
6892
fc5b7f3b
DM		 6893 kvm_load_guest_xcr0(vcpu);
6894
c43203ca
PB		 6895 if (req_immediate_exit) {
6896 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 6897 smp_send_reschedule(vcpu->cpu);
c43203ca 6898 }
d6185f20 6899
8b89fe1f
PB		 6900 trace_kvm_entry(vcpu->vcpu_id);
6901 wait_lapic_expire(vcpu);
6edaa530 6902 guest_enter_irqoff();
b6c7a5dc 6903
42dbaa5a 6904 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6905 set_debugreg(0, 7);
6906 set_debugreg(vcpu->arch.eff_db[0], 0);
6907 set_debugreg(vcpu->arch.eff_db[1], 1);
6908 set_debugreg(vcpu->arch.eff_db[2], 2);
6909 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6910 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6911 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6912 }
b6c7a5dc 6913
851ba692 6914 kvm_x86_ops->run(vcpu);
b6c7a5dc 6915
c77fb5fe
PB		 6916 /*
6917 * Do this here before restoring debug registers on the host. And
6918 * since we do this before handling the vmexit, a DR access vmexit
6919 * can (a) read the correct value of the debug registers, (b) set
6920 * KVM_DEBUGREG_WONT_EXIT again.
6921 */
6922 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 6923 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6924 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 6925 kvm_update_dr0123(vcpu);
6926 kvm_update_dr6(vcpu);
6927 kvm_update_dr7(vcpu);
6928 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 6929 }
6930
24f1e32c
FW		 6931 /*
6932 * If the guest has used debug registers, at least dr7
6933 * will be disabled while returning to the host.
6934 * If we don't have active breakpoints in the host, we don't
6935 * care about the messed up debug address registers. But if
6936 * we have some of them active, restore the old state.
6937 */
59d8eb53 6938 if (hw_breakpoint_active())
24f1e32c 6939 hw_breakpoint_restore();
42dbaa5a 6940
4ba76538 6941 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6942
6b7e2d09 6943 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6944 smp_wmb();
a547c6db 6945
fc5b7f3b
DM		 6946 kvm_put_guest_xcr0(vcpu);
6947
a547c6db 6948 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6949
6950 ++vcpu->stat.exits;
6951
f2485b3e 6952 guest_exit_irqoff();
b6c7a5dc 6953
f2485b3e 6954 local_irq_enable();
b6c7a5dc
HB		 6955 preempt_enable();
6956
f656ce01 6957 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6958
b6c7a5dc
HB		 6959 /*
6960 * Profile KVM exit RIPs:
6961 */
6962 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6963 unsigned long rip = kvm_rip_read(vcpu);
6964 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6965 }
6966
cc578287
ZA		 6967 if (unlikely(vcpu->arch.tsc_always_catchup))
6968 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6969
5cfb1d5a
MT		 6970 if (vcpu->arch.apic_attention)
6971 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6972
851ba692 6973 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6974 return r;
6975
6976cancel_injection:
6977 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6978 if (unlikely(vcpu->arch.apic_attention))
6979 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6980out:
6981 return r;
6982}
b6c7a5dc 6983
362c698f
PB		 6984static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6985{
bf9f6ac8
FW		 6986 if (!kvm_arch_vcpu_runnable(vcpu) &&
6987 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6988 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6989 kvm_vcpu_block(vcpu);
6990 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6991
6992 if (kvm_x86_ops->post_block)
6993 kvm_x86_ops->post_block(vcpu);
6994
9c8fd1ba
PB		 6995 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6996 return 1;
6997 }
362c698f
PB		 6998
6999 kvm_apic_accept_events(vcpu);
7000 switch(vcpu->arch.mp_state) {
7001 case KVM_MP_STATE_HALTED:
7002 vcpu->arch.pv.pv_unhalted = false;
7003 vcpu->arch.mp_state =
7004 KVM_MP_STATE_RUNNABLE;
7005 case KVM_MP_STATE_RUNNABLE:
7006 vcpu->arch.apf.halted = false;
7007 break;
7008 case KVM_MP_STATE_INIT_RECEIVED:
7009 break;
7010 default:
7011 return -EINTR;
7012 break;
7013 }
7014 return 1;
7015}
09cec754 7016
5d9bc648
PB		 7017static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7018{
0ad3bed6
PB		 7019 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7020 kvm_x86_ops->check_nested_events(vcpu, false);
7021
5d9bc648
PB		 7022 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7023 !vcpu->arch.apf.halted);
7024}
7025
362c698f 7026static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7027{
7028 int r;
f656ce01 7029 struct kvm *kvm = vcpu->kvm;
d7690175 7030
f656ce01 7031 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7032
362c698f 7033 for (;;) {
58f800d5 7034 if (kvm_vcpu_running(vcpu)) {
851ba692 7035 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7036 } else {
362c698f 7037 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7038 }
7039
09cec754
GN		 7040 if (r <= 0)
7041 break;
7042
72875d8a 7043 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7044 if (kvm_cpu_has_pending_timer(vcpu))
7045 kvm_inject_pending_timer_irqs(vcpu);
7046
782d422b
MG		 7047 if (dm_request_for_irq_injection(vcpu) &&
7048 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7049 r = 0;
7050 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7051 ++vcpu->stat.request_irq_exits;
362c698f 7052 break;
09cec754 7053 }
af585b92
GN		 7054
7055 kvm_check_async_pf_completion(vcpu);
7056
09cec754
GN		 7057 if (signal_pending(current)) {
7058 r = -EINTR;
851ba692 7059 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7060 ++vcpu->stat.signal_exits;
362c698f 7061 break;
09cec754
GN		 7062 }
7063 if (need_resched()) {
f656ce01 7064 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7065 cond_resched();
f656ce01 7066 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7067 }
b6c7a5dc
HB		 7068 }
7069
f656ce01 7070 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7071
7072 return r;
7073}
7074
716d51ab
GN		 7075static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7076{
7077 int r;
7078 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7079 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7080 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7081 if (r != EMULATE_DONE)
7082 return 0;
7083 return 1;
7084}
7085
7086static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7087{
7088 BUG_ON(!vcpu->arch.pio.count);
7089
7090 return complete_emulated_io(vcpu);
7091}
7092
f78146b0
AK		 7093/*
7094 * Implements the following, as a state machine:
7095 *
7096 * read:
7097 * for each fragment
87da7e66
XG		 7098 * for each mmio piece in the fragment
7099 * write gpa, len
7100 * exit
7101 * copy data
f78146b0
AK		 7102 * execute insn
7103 *
7104 * write:
7105 * for each fragment
87da7e66
XG		 7106 * for each mmio piece in the fragment
7107 * write gpa, len
7108 * copy data
7109 * exit
f78146b0 7110 */
716d51ab 7111static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7112{
7113 struct kvm_run *run = vcpu->run;
f78146b0 7114 struct kvm_mmio_fragment *frag;
87da7e66 7115 unsigned len;
5287f194 7116
716d51ab 7117 BUG_ON(!vcpu->mmio_needed);
5287f194 7118
716d51ab 7119 /* Complete previous fragment */
87da7e66
XG		 7120 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7121 len = min(8u, frag->len);
716d51ab 7122 if (!vcpu->mmio_is_write)
87da7e66
XG		 7123 memcpy(frag->data, run->mmio.data, len);
7124
7125 if (frag->len <= 8) {
7126 /* Switch to the next fragment. */
7127 frag++;
7128 vcpu->mmio_cur_fragment++;
7129 } else {
7130 /* Go forward to the next mmio piece. */
7131 frag->data += len;
7132 frag->gpa += len;
7133 frag->len -= len;
7134 }
7135
a08d3b3b 7136 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7137 vcpu->mmio_needed = 0;
0912c977
PB		 7138
7139 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7140 if (vcpu->mmio_is_write)
716d51ab
GN		 7141 return 1;
7142 vcpu->mmio_read_completed = 1;
7143 return complete_emulated_io(vcpu);
7144 }
87da7e66 7145
716d51ab
GN		 7146 run->exit_reason = KVM_EXIT_MMIO;
7147 run->mmio.phys_addr = frag->gpa;
7148 if (vcpu->mmio_is_write)
87da7e66
XG		 7149 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7150 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7151 run->mmio.is_write = vcpu->mmio_is_write;
7152 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7153 return 0;
5287f194
AK		 7154}
7155
716d51ab 7156
b6c7a5dc
HB		 7157int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7158{
c5bedc68 7159 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 7160 int r;
7161 sigset_t sigsaved;
7162
c4d72e2d 7163 fpu__activate_curr(fpu);
e5c30142 7164
ac9f6dc0
AK		 7165 if (vcpu->sigset_active)
7166 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
7167
a4535290 7168 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 7169 kvm_vcpu_block(vcpu);
66450a21 7170 kvm_apic_accept_events(vcpu);
72875d8a 7171 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0
AK		 7172 r = -EAGAIN;
7173 goto out;
b6c7a5dc
HB		 7174 }
7175
b6c7a5dc 7176 /* re-sync apic's tpr */
35754c98 7177 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7178 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7179 r = -EINVAL;
7180 goto out;
7181 }
7182 }
b6c7a5dc 7183
716d51ab
GN		 7184 if (unlikely(vcpu->arch.complete_userspace_io)) {
7185 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7186 vcpu->arch.complete_userspace_io = NULL;
7187 r = cui(vcpu);
7188 if (r <= 0)
7189 goto out;
7190 } else
7191 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7192
460df4c1
PB		 7193 if (kvm_run->immediate_exit)
7194 r = -EINTR;
7195 else
7196 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7197
7198out:
f1d86e46 7199 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 7200 if (vcpu->sigset_active)
7201 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
7202
b6c7a5dc
HB		 7203 return r;
7204}
7205
7206int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7207{
7ae441ea
GN		 7208 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7209 /*
7210 * We are here if userspace calls get_regs() in the middle of
7211 * instruction emulation. Registers state needs to be copied
4a969980 7212 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7213 * that usually, but some bad designed PV devices (vmware
7214 * backdoor interface) need this to work
7215 */
dd856efa 7216 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7217 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7218 }
5fdbf976
MT		 7219 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7220 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7221 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7222 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7223 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7224 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7225 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7226 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7227#ifdef CONFIG_X86_64
5fdbf976
MT		 7228 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7229 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7230 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7231 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7232 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7233 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7234 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7235 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7236#endif
7237
5fdbf976 7238 regs->rip = kvm_rip_read(vcpu);
91586a3b 7239 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7240
b6c7a5dc
HB		 7241 return 0;
7242}
7243
7244int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7245{
7ae441ea
GN		 7246 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7247 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7248
5fdbf976
MT		 7249 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7250 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7251 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7252 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7253 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7254 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7255 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7256 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7257#ifdef CONFIG_X86_64
5fdbf976
MT		 7258 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7259 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7260 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7261 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7262 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7263 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7264 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7265 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7266#endif
7267
5fdbf976 7268 kvm_rip_write(vcpu, regs->rip);
91586a3b 7269 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 7270
b4f14abd
JK		 7271 vcpu->arch.exception.pending = false;
7272
3842d135
AK		 7273 kvm_make_request(KVM_REQ_EVENT, vcpu);
7274
b6c7a5dc
HB		 7275 return 0;
7276}
7277
b6c7a5dc
HB		 7278void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7279{
7280 struct kvm_segment cs;
7281
3e6e0aab 7282 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7283 *db = cs.db;
7284 *l = cs.l;
7285}
7286EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7287
7288int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7289 struct kvm_sregs *sregs)
7290{
89a27f4d 7291 struct desc_ptr dt;
b6c7a5dc 7292
3e6e0aab
GT		 7293 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7294 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7295 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7296 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7297 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7298 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7299
3e6e0aab
GT		 7300 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7301 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7302
7303 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7304 sregs->idt.limit = dt.size;
7305 sregs->idt.base = dt.address;
b6c7a5dc 7306 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7307 sregs->gdt.limit = dt.size;
7308 sregs->gdt.base = dt.address;
b6c7a5dc 7309
4d4ec087 7310 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7311 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7312 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7313 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7314 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7315 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7316 sregs->apic_base = kvm_get_apic_base(vcpu);
7317
923c61bb 7318 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7319
36752c9b 7320 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7321 set_bit(vcpu->arch.interrupt.nr,
7322 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7323
b6c7a5dc
HB		 7324 return 0;
7325}
7326
62d9f0db
MT		 7327int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7328 struct kvm_mp_state *mp_state)
7329{
66450a21 7330 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7331 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7332 vcpu->arch.pv.pv_unhalted)
7333 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7334 else
7335 mp_state->mp_state = vcpu->arch.mp_state;
7336
62d9f0db
MT		 7337 return 0;
7338}
7339
7340int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7341 struct kvm_mp_state *mp_state)
7342{
bce87cce 7343 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7344 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7345 return -EINVAL;
7346
28bf2888
DH		 7347 /* INITs are latched while in SMM */
7348 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7349 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7350 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7351 return -EINVAL;
7352
66450a21
JK		 7353 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7354 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7355 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7356 } else
7357 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7358 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7359 return 0;
7360}
7361
7f3d35fd
KW		 7362int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7363 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7364{
9d74191a 7365 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7366 int ret;
e01c2426 7367
8ec4722d 7368 init_emulate_ctxt(vcpu);
c697518a 7369
7f3d35fd 7370 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7371 has_error_code, error_code);
c697518a 7372
c697518a 7373 if (ret)
19d04437 7374 return EMULATE_FAIL;
37817f29 7375
9d74191a
TY		 7376 kvm_rip_write(vcpu, ctxt->eip);
7377 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7378 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7379 return EMULATE_DONE;
37817f29
IE		 7380}
7381EXPORT_SYMBOL_GPL(kvm_task_switch);
7382
b6c7a5dc
HB		 7383int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7384 struct kvm_sregs *sregs)
7385{
58cb628d 7386 struct msr_data apic_base_msr;
b6c7a5dc 7387 int mmu_reset_needed = 0;
63f42e02 7388 int pending_vec, max_bits, idx;
89a27f4d 7389 struct desc_ptr dt;
b6c7a5dc 7390
6d1068b3
PM		 7391 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7392 return -EINVAL;
7393
89a27f4d
GN		 7394 dt.size = sregs->idt.limit;
7395 dt.address = sregs->idt.base;
b6c7a5dc 7396 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7397 dt.size = sregs->gdt.limit;
7398 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7399 kvm_x86_ops->set_gdt(vcpu, &dt);
7400
ad312c7c 7401 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7402 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7403 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7404 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7405
2d3ad1f4 7406 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7407
f6801dff 7408 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7409 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7410 apic_base_msr.data = sregs->apic_base;
7411 apic_base_msr.host_initiated = true;
7412 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7413
4d4ec087 7414 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7415 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7416 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7417
fc78f519 7418 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7419 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7420 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7421 kvm_update_cpuid(vcpu);
63f42e02
XG		 7422
7423 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7424 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7425 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7426 mmu_reset_needed = 1;
7427 }
63f42e02 7428 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7429
7430 if (mmu_reset_needed)
7431 kvm_mmu_reset_context(vcpu);
7432
a50abc3b 7433 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7434 pending_vec = find_first_bit(
7435 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7436 if (pending_vec < max_bits) {
66fd3f7f 7437 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7438 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7439 }
7440
3e6e0aab
GT		 7441 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7442 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7443 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7444 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7445 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7446 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7447
3e6e0aab
GT		 7448 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7449 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7450
5f0269f5
ME		 7451 update_cr8_intercept(vcpu);
7452
9c3e4aab 7453 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7454 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7455 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7456 !is_protmode(vcpu))
9c3e4aab
MT		 7457 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7458
3842d135
AK		 7459 kvm_make_request(KVM_REQ_EVENT, vcpu);
7460
b6c7a5dc
HB		 7461 return 0;
7462}
7463
d0bfb940
JK		 7464int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7465 struct kvm_guest_debug *dbg)
b6c7a5dc 7466{
355be0b9 7467 unsigned long rflags;
ae675ef0 7468 int i, r;
b6c7a5dc 7469
4f926bf2
JK		 7470 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7471 r = -EBUSY;
7472 if (vcpu->arch.exception.pending)
2122ff5e 7473 goto out;
4f926bf2
JK		 7474 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7475 kvm_queue_exception(vcpu, DB_VECTOR);
7476 else
7477 kvm_queue_exception(vcpu, BP_VECTOR);
7478 }
7479
91586a3b
JK		 7480 /*
7481 * Read rflags as long as potentially injected trace flags are still
7482 * filtered out.
7483 */
7484 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7485
7486 vcpu->guest_debug = dbg->control;
7487 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7488 vcpu->guest_debug = 0;
7489
7490 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7491 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7492 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7493 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7494 } else {
7495 for (i = 0; i < KVM_NR_DB_REGS; i++)
7496 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7497 }
c8639010 7498 kvm_update_dr7(vcpu);
ae675ef0 7499
f92653ee
JK		 7500 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7501 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7502 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7503
91586a3b
JK		 7504 /*
7505 * Trigger an rflags update that will inject or remove the trace
7506 * flags.
7507 */
7508 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7509
a96036b8 7510 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7511
4f926bf2 7512 r = 0;
d0bfb940 7513
2122ff5e 7514out:
b6c7a5dc
HB		 7515
7516 return r;
7517}
7518
8b006791
ZX		 7519/*
7520 * Translate a guest virtual address to a guest physical address.
7521 */
7522int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7523 struct kvm_translation *tr)
7524{
7525 unsigned long vaddr = tr->linear_address;
7526 gpa_t gpa;
f656ce01 7527 int idx;
8b006791 7528
f656ce01 7529 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7530 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7531 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7532 tr->physical_address = gpa;
7533 tr->valid = gpa != UNMAPPED_GVA;
7534 tr->writeable = 1;
7535 tr->usermode = 0;
8b006791
ZX		 7536
7537 return 0;
7538}
7539
d0752060
HB		 7540int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7541{
c47ada30 7542 struct fxregs_state *fxsave =
7366ed77 7543 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7544
d0752060
HB		 7545 memcpy(fpu->fpr, fxsave->st_space, 128);
7546 fpu->fcw = fxsave->cwd;
7547 fpu->fsw = fxsave->swd;
7548 fpu->ftwx = fxsave->twd;
7549 fpu->last_opcode = fxsave->fop;
7550 fpu->last_ip = fxsave->rip;
7551 fpu->last_dp = fxsave->rdp;
7552 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7553
d0752060
HB		 7554 return 0;
7555}
7556
7557int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7558{
c47ada30 7559 struct fxregs_state *fxsave =
7366ed77 7560 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7561
d0752060
HB		 7562 memcpy(fxsave->st_space, fpu->fpr, 128);
7563 fxsave->cwd = fpu->fcw;
7564 fxsave->swd = fpu->fsw;
7565 fxsave->twd = fpu->ftwx;
7566 fxsave->fop = fpu->last_opcode;
7567 fxsave->rip = fpu->last_ip;
7568 fxsave->rdp = fpu->last_dp;
7569 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7570
d0752060
HB		 7571 return 0;
7572}
7573
0ee6a517 7574static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7575{
bf935b0b 7576 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7577 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7578 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7579 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7580
2acf923e
DC		 7581 /*
7582 * Ensure guest xcr0 is valid for loading
7583 */
d91cab78 7584 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7585
ad312c7c 7586 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7587}
d0752060
HB		 7588
7589void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7590{
2608d7a1 7591 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7592 return;
7593
2acf923e
DC		 7594 /*
7595 * Restore all possible states in the guest,
7596 * and assume host would use all available bits.
7597 * Guest xcr0 would be loaded later.
7598 */
d0752060 7599 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7600 __kernel_fpu_begin();
003e2e8b 7601 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7602 trace_kvm_fpu(1);
d0752060 7603}
d0752060
HB		 7604
7605void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7606{
3d42de25 7607 if (!vcpu->guest_fpu_loaded)
d0752060
HB		 7608 return;
7609
7610 vcpu->guest_fpu_loaded = 0;
4f836347 7611 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7612 __kernel_fpu_end();
f096ed85 7613 ++vcpu->stat.fpu_reload;
0c04851c 7614 trace_kvm_fpu(0);
d0752060 7615}
e9b11c17
ZX		 7616
7617void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7618{
bd768e14
IY		 7619 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7620
12f9a48f 7621 kvmclock_reset(vcpu);
7f1ea208 7622
e9b11c17 7623 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 7624 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 7625}
7626
7627struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7628 unsigned int id)
7629{
c447e76b
LL		 7630 struct kvm_vcpu *vcpu;
7631
6755bae8
ZA		 7632 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7633 printk_once(KERN_WARNING
7634 "kvm: SMP vm created on host with unstable TSC; "
7635 "guest TSC will not be reliable\n");
c447e76b
LL		 7636
7637 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7638
c447e76b 7639 return vcpu;
26e5215f 7640}
e9b11c17 7641
26e5215f
AK		 7642int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7643{
7644 int r;
e9b11c17 7645
19efffa2 7646 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7647 r = vcpu_load(vcpu);
7648 if (r)
7649 return r;
d28bc9dd 7650 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7651 kvm_mmu_setup(vcpu);
e9b11c17 7652 vcpu_put(vcpu);
26e5215f 7653 return r;
e9b11c17
ZX		 7654}
7655
31928aa5 7656void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7657{
8fe8ab46 7658 struct msr_data msr;
332967a3 7659 struct kvm *kvm = vcpu->kvm;
42897d86 7660
31928aa5
DD		 7661 if (vcpu_load(vcpu))
7662 return;
8fe8ab46
WA		 7663 msr.data = 0x0;
7664 msr.index = MSR_IA32_TSC;
7665 msr.host_initiated = true;
7666 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7667 vcpu_put(vcpu);
7668
630994b3
MT		 7669 if (!kvmclock_periodic_sync)
7670 return;
7671
332967a3
AJ		 7672 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7673 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7674}
7675
d40ccc62 7676void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7677{
9fc77441 7678 int r;
344d9588
GN		 7679 vcpu->arch.apf.msr_val = 0;
7680
9fc77441
MT		 7681 r = vcpu_load(vcpu);
7682 BUG_ON(r);
e9b11c17
ZX		 7683 kvm_mmu_unload(vcpu);
7684 vcpu_put(vcpu);
7685
7686 kvm_x86_ops->vcpu_free(vcpu);
7687}
7688
d28bc9dd 7689void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7690{
e69fab5d
PB		 7691 vcpu->arch.hflags = 0;
7692
c43203ca 7693 vcpu->arch.smi_pending = 0;
7460fb4a
AK		 7694 atomic_set(&vcpu->arch.nmi_queued, 0);
7695 vcpu->arch.nmi_pending = 0;
448fa4a9 7696 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7697 kvm_clear_interrupt_queue(vcpu);
7698 kvm_clear_exception_queue(vcpu);
448fa4a9 7699
42dbaa5a 7700 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7701 kvm_update_dr0123(vcpu);
6f43ed01 7702 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7703 kvm_update_dr6(vcpu);
42dbaa5a 7704 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7705 kvm_update_dr7(vcpu);
42dbaa5a 7706
1119022c
NA		 7707 vcpu->arch.cr2 = 0;
7708
3842d135 7709 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7710 vcpu->arch.apf.msr_val = 0;
c9aaa895 7711 vcpu->arch.st.msr_val = 0;
3842d135 7712
12f9a48f
GC		 7713 kvmclock_reset(vcpu);
7714
af585b92
GN		 7715 kvm_clear_async_pf_completion_queue(vcpu);
7716 kvm_async_pf_hash_reset(vcpu);
7717 vcpu->arch.apf.halted = false;
3842d135 7718
64d60670 7719 if (!init_event) {
d28bc9dd 7720 kvm_pmu_reset(vcpu);
64d60670 7721 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 7722
7723 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
7724 vcpu->arch.msr_misc_features_enables = 0;
64d60670 7725 }
f5132b01 7726
66f7b72e
JS		 7727 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7728 vcpu->arch.regs_avail = ~0;
7729 vcpu->arch.regs_dirty = ~0;
7730
d28bc9dd 7731 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7732}
7733
2b4a273b 7734void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7735{
7736 struct kvm_segment cs;
7737
7738 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7739 cs.selector = vector << 8;
7740 cs.base = vector << 12;
7741 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7742 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7743}
7744
13a34e06 7745int kvm_arch_hardware_enable(void)
e9b11c17 7746{
ca84d1a2
ZA		 7747 struct kvm *kvm;
7748 struct kvm_vcpu *vcpu;
7749 int i;
0dd6a6ed
ZA		 7750 int ret;
7751 u64 local_tsc;
7752 u64 max_tsc = 0;
7753 bool stable, backwards_tsc = false;
18863bdd
AK		 7754
7755 kvm_shared_msr_cpu_online();
13a34e06 7756 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7757 if (ret != 0)
7758 return ret;
7759
4ea1636b 7760 local_tsc = rdtsc();
0dd6a6ed
ZA		 7761 stable = !check_tsc_unstable();
7762 list_for_each_entry(kvm, &vm_list, vm_list) {
7763 kvm_for_each_vcpu(i, vcpu, kvm) {
7764 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7765 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7766 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7767 backwards_tsc = true;
7768 if (vcpu->arch.last_host_tsc > max_tsc)
7769 max_tsc = vcpu->arch.last_host_tsc;
7770 }
7771 }
7772 }
7773
7774 /*
7775 * Sometimes, even reliable TSCs go backwards. This happens on
7776 * platforms that reset TSC during suspend or hibernate actions, but
7777 * maintain synchronization. We must compensate. Fortunately, we can
7778 * detect that condition here, which happens early in CPU bringup,
7779 * before any KVM threads can be running. Unfortunately, we can't
7780 * bring the TSCs fully up to date with real time, as we aren't yet far
7781 * enough into CPU bringup that we know how much real time has actually
108b249c 7782 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 7783 * variables that haven't been updated yet.
7784 *
7785 * So we simply find the maximum observed TSC above, then record the
7786 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7787 * the adjustment will be applied. Note that we accumulate
7788 * adjustments, in case multiple suspend cycles happen before some VCPU
7789 * gets a chance to run again. In the event that no KVM threads get a
7790 * chance to run, we will miss the entire elapsed period, as we'll have
7791 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7792 * loose cycle time. This isn't too big a deal, since the loss will be
7793 * uniform across all VCPUs (not to mention the scenario is extremely
7794 * unlikely). It is possible that a second hibernate recovery happens
7795 * much faster than a first, causing the observed TSC here to be
7796 * smaller; this would require additional padding adjustment, which is
7797 * why we set last_host_tsc to the local tsc observed here.
7798 *
7799 * N.B. - this code below runs only on platforms with reliable TSC,
7800 * as that is the only way backwards_tsc is set above. Also note
7801 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7802 * have the same delta_cyc adjustment applied if backwards_tsc
7803 * is detected. Note further, this adjustment is only done once,
7804 * as we reset last_host_tsc on all VCPUs to stop this from being
7805 * called multiple times (one for each physical CPU bringup).
7806 *
4a969980 7807 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7808 * will be compensated by the logic in vcpu_load, which sets the TSC to
7809 * catchup mode. This will catchup all VCPUs to real time, but cannot
7810 * guarantee that they stay in perfect synchronization.
7811 */
7812 if (backwards_tsc) {
7813 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7814 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7815 list_for_each_entry(kvm, &vm_list, vm_list) {
7816 kvm_for_each_vcpu(i, vcpu, kvm) {
7817 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7818 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7819 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7820 }
7821
7822 /*
7823 * We have to disable TSC offset matching.. if you were
7824 * booting a VM while issuing an S4 host suspend....
7825 * you may have some problem. Solving this issue is
7826 * left as an exercise to the reader.
7827 */
7828 kvm->arch.last_tsc_nsec = 0;
7829 kvm->arch.last_tsc_write = 0;
7830 }
7831
7832 }
7833 return 0;
e9b11c17
ZX		 7834}
7835
13a34e06 7836void kvm_arch_hardware_disable(void)
e9b11c17 7837{
13a34e06
RK		 7838 kvm_x86_ops->hardware_disable();
7839 drop_user_return_notifiers();
e9b11c17
ZX		 7840}
7841
7842int kvm_arch_hardware_setup(void)
7843{
9e9c3fe4
NA		 7844 int r;
7845
7846 r = kvm_x86_ops->hardware_setup();
7847 if (r != 0)
7848 return r;
7849
35181e86
HZ		 7850 if (kvm_has_tsc_control) {
7851 /*
7852 * Make sure the user can only configure tsc_khz values that
7853 * fit into a signed integer.
7854 * A min value is not calculated needed because it will always
7855 * be 1 on all machines.
7856 */
7857 u64 max = min(0x7fffffffULL,
7858 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7859 kvm_max_guest_tsc_khz = max;
7860
ad721883 7861 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7862 }
ad721883 7863
9e9c3fe4
NA		 7864 kvm_init_msr_list();
7865 return 0;
e9b11c17
ZX		 7866}
7867
7868void kvm_arch_hardware_unsetup(void)
7869{
7870 kvm_x86_ops->hardware_unsetup();
7871}
7872
7873void kvm_arch_check_processor_compat(void *rtn)
7874{
7875 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7876}
7877
7878bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7879{
7880 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7881}
7882EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7883
7884bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7885{
7886 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7887}
7888
54e9818f 7889struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 7890EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 7891
e9b11c17
ZX		 7892int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7893{
7894 struct page *page;
7895 struct kvm *kvm;
7896 int r;
7897
7898 BUG_ON(vcpu->kvm == NULL);
7899 kvm = vcpu->kvm;
7900
d62caabb 7901 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7902 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7903 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7904 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7905 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7906 else
a4535290 7907 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7908
7909 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7910 if (!page) {
7911 r = -ENOMEM;
7912 goto fail;
7913 }
ad312c7c 7914 vcpu->arch.pio_data = page_address(page);
e9b11c17 7915
cc578287 7916 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7917
e9b11c17
ZX		 7918 r = kvm_mmu_create(vcpu);
7919 if (r < 0)
7920 goto fail_free_pio_data;
7921
7922 if (irqchip_in_kernel(kvm)) {
7923 r = kvm_create_lapic(vcpu);
7924 if (r < 0)
7925 goto fail_mmu_destroy;
54e9818f
GN		 7926 } else
7927 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7928
890ca9ae
HY		 7929 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7930 GFP_KERNEL);
7931 if (!vcpu->arch.mce_banks) {
7932 r = -ENOMEM;
443c39bc 7933 goto fail_free_lapic;
890ca9ae
HY		 7934 }
7935 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7936
f1797359
WY		 7937 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7938 r = -ENOMEM;
f5f48ee1 7939 goto fail_free_mce_banks;
f1797359 7940 }
f5f48ee1 7941
0ee6a517 7942 fx_init(vcpu);
66f7b72e 7943
ba904635 7944 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7945 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7946
7947 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7948 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7949
5a4f55cd
EK		 7950 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7951
74545705
RK		 7952 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7953
af585b92 7954 kvm_async_pf_hash_reset(vcpu);
f5132b01 7955 kvm_pmu_init(vcpu);
af585b92 7956
1c1a9ce9
SR		 7957 vcpu->arch.pending_external_vector = -1;
7958
5c919412
AS		 7959 kvm_hv_vcpu_init(vcpu);
7960
e9b11c17 7961 return 0;
0ee6a517 7962
f5f48ee1
SY		 7963fail_free_mce_banks:
7964 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7965fail_free_lapic:
7966 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7967fail_mmu_destroy:
7968 kvm_mmu_destroy(vcpu);
7969fail_free_pio_data:
ad312c7c 7970 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7971fail:
7972 return r;
7973}
7974
7975void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7976{
f656ce01
MT		 7977 int idx;
7978
1f4b34f8 7979 kvm_hv_vcpu_uninit(vcpu);
f5132b01 7980 kvm_pmu_destroy(vcpu);
36cb93fd 7981 kfree(vcpu->arch.mce_banks);
e9b11c17 7982 kvm_free_lapic(vcpu);
f656ce01 7983 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7984 kvm_mmu_destroy(vcpu);
f656ce01 7985 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7986 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7987 if (!lapic_in_kernel(vcpu))
54e9818f 7988 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7989}
d19a9cd2 7990
e790d9ef
RK		 7991void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7992{
ae97a3b8 7993 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7994}
7995
e08b9637 7996int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7997{
e08b9637
CO		 7998 if (type)
7999 return -EINVAL;
8000
6ef768fa 8001 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8002 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8003 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8004 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8005 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8006
5550af4d
SY		 8007 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8008 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8009 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8010 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8011 &kvm->arch.irq_sources_bitmap);
5550af4d 8012
038f8c11 8013 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8014 mutex_init(&kvm->arch.apic_map_lock);
3f5ad8be 8015 mutex_init(&kvm->arch.hyperv.hv_lock);
d828199e
MT		 8016 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8017
108b249c 8018 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8019 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8020
7e44e449 8021 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8022 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8023
0eb05bf2 8024 kvm_page_track_init(kvm);
13d268ca 8025 kvm_mmu_init_vm(kvm);
0eb05bf2 8026
03543133
SS		 8027 if (kvm_x86_ops->vm_init)
8028 return kvm_x86_ops->vm_init(kvm);
8029
d89f5eff 8030 return 0;
d19a9cd2
ZX		 8031}
8032
8033static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8034{
9fc77441
MT		 8035 int r;
8036 r = vcpu_load(vcpu);
8037 BUG_ON(r);
d19a9cd2
ZX		 8038 kvm_mmu_unload(vcpu);
8039 vcpu_put(vcpu);
8040}
8041
8042static void kvm_free_vcpus(struct kvm *kvm)
8043{
8044 unsigned int i;
988a2cae 8045 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8046
8047 /*
8048 * Unpin any mmu pages first.
8049 */
af585b92
GN		 8050 kvm_for_each_vcpu(i, vcpu, kvm) {
8051 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8052 kvm_unload_vcpu_mmu(vcpu);
af585b92 8053 }
988a2cae
GN		 8054 kvm_for_each_vcpu(i, vcpu, kvm)
8055 kvm_arch_vcpu_free(vcpu);
8056
8057 mutex_lock(&kvm->lock);
8058 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8059 kvm->vcpus[i] = NULL;
d19a9cd2 8060
988a2cae
GN		 8061 atomic_set(&kvm->online_vcpus, 0);
8062 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8063}
8064
ad8ba2cd
SY		 8065void kvm_arch_sync_events(struct kvm *kvm)
8066{
332967a3 8067 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8068 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8069 kvm_free_pit(kvm);
ad8ba2cd
SY		 8070}
8071
1d8007bd 8072int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8073{
8074 int i, r;
25188b99 8075 unsigned long hva;
f0d648bd
PB		 8076 struct kvm_memslots *slots = kvm_memslots(kvm);
8077 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8078
8079 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8080 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8081 return -EINVAL;
9da0e4d5 8082
f0d648bd
PB		 8083 slot = id_to_memslot(slots, id);
8084 if (size) {
b21629da 8085 if (slot->npages)
f0d648bd
PB		 8086 return -EEXIST;
8087
8088 /*
8089 * MAP_SHARED to prevent internal slot pages from being moved
8090 * by fork()/COW.
8091 */
8092 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8093 MAP_SHARED | MAP_ANONYMOUS, 0);
8094 if (IS_ERR((void *)hva))
8095 return PTR_ERR((void *)hva);
8096 } else {
8097 if (!slot->npages)
8098 return 0;
8099
8100 hva = 0;
8101 }
8102
8103 old = *slot;
9da0e4d5 8104 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8105 struct kvm_userspace_memory_region m;
9da0e4d5 8106
1d8007bd
PB		 8107 m.slot = id | (i << 16);
8108 m.flags = 0;
8109 m.guest_phys_addr = gpa;
f0d648bd 8110 m.userspace_addr = hva;
1d8007bd 8111 m.memory_size = size;
9da0e4d5
PB		 8112 r = __kvm_set_memory_region(kvm, &m);
8113 if (r < 0)
8114 return r;
8115 }
8116
f0d648bd
PB		 8117 if (!size) {
8118 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8119 WARN_ON(r < 0);
8120 }
8121
9da0e4d5
PB		 8122 return 0;
8123}
8124EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8125
1d8007bd 8126int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8127{
8128 int r;
8129
8130 mutex_lock(&kvm->slots_lock);
1d8007bd 8131 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8132 mutex_unlock(&kvm->slots_lock);
8133
8134 return r;
8135}
8136EXPORT_SYMBOL_GPL(x86_set_memory_region);
8137
d19a9cd2
ZX		 8138void kvm_arch_destroy_vm(struct kvm *kvm)
8139{
27469d29
AH		 8140 if (current->mm == kvm->mm) {
8141 /*
8142 * Free memory regions allocated on behalf of userspace,
8143 * unless the the memory map has changed due to process exit
8144 * or fd copying.
8145 */
1d8007bd
PB		 8146 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8147 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8148 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8149 }
03543133
SS		 8150 if (kvm_x86_ops->vm_destroy)
8151 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8152 kvm_pic_destroy(kvm);
8153 kvm_ioapic_destroy(kvm);
d19a9cd2 8154 kvm_free_vcpus(kvm);
af1bae54 8155 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8156 kvm_mmu_uninit_vm(kvm);
2beb6dad 8157 kvm_page_track_cleanup(kvm);
d19a9cd2 8158}
0de10343 8159
5587027c 8160void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8161 struct kvm_memory_slot *dont)
8162{
8163 int i;
8164
d89cc617
TY		 8165 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8166 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8167 kvfree(free->arch.rmap[i]);
d89cc617 8168 free->arch.rmap[i] = NULL;
77d11309 8169 }
d89cc617
TY		 8170 if (i == 0)
8171 continue;
8172
8173 if (!dont || free->arch.lpage_info[i - 1] !=
8174 dont->arch.lpage_info[i - 1]) {
548ef284 8175 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8176 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8177 }
8178 }
21ebbeda
XG		 8179
8180 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8181}
8182
5587027c
AK		 8183int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8184 unsigned long npages)
db3fe4eb
TY		 8185{
8186 int i;
8187
d89cc617 8188 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8189 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8190 unsigned long ugfn;
8191 int lpages;
d89cc617 8192 int level = i + 1;
db3fe4eb
TY		 8193
8194 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8195 slot->base_gfn, level) + 1;
8196
d89cc617 8197 slot->arch.rmap[i] =
a7c3e901 8198 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8199 if (!slot->arch.rmap[i])
77d11309 8200 goto out_free;
d89cc617
TY		 8201 if (i == 0)
8202 continue;
77d11309 8203
a7c3e901 8204 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8205 if (!linfo)
db3fe4eb
TY		 8206 goto out_free;
8207
92f94f1e
XG		 8208 slot->arch.lpage_info[i - 1] = linfo;
8209
db3fe4eb 8210 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8211 linfo[0].disallow_lpage = 1;
db3fe4eb 8212 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8213 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8214 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8215 /*
8216 * If the gfn and userspace address are not aligned wrt each
8217 * other, or if explicitly asked to, disable large page
8218 * support for this slot
8219 */
8220 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8221 !kvm_largepages_enabled()) {
8222 unsigned long j;
8223
8224 for (j = 0; j < lpages; ++j)
92f94f1e 8225 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8226 }
8227 }
8228
21ebbeda
XG		 8229 if (kvm_page_track_create_memslot(slot, npages))
8230 goto out_free;
8231
db3fe4eb
TY		 8232 return 0;
8233
8234out_free:
d89cc617 8235 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8236 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8237 slot->arch.rmap[i] = NULL;
8238 if (i == 0)
8239 continue;
8240
548ef284 8241 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8242 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8243 }
8244 return -ENOMEM;
8245}
8246
15f46015 8247void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8248{
e6dff7d1
TY		 8249 /*
8250 * memslots->generation has been incremented.
8251 * mmio generation may have reached its maximum value.
8252 */
54bf36aa 8253 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8254}
8255
f7784b8e
MT		 8256int kvm_arch_prepare_memory_region(struct kvm *kvm,
8257 struct kvm_memory_slot *memslot,
09170a49 8258 const struct kvm_userspace_memory_region *mem,
7b6195a9 8259 enum kvm_mr_change change)
0de10343 8260{
f7784b8e
MT		 8261 return 0;
8262}
8263
88178fd4
KH		 8264static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8265 struct kvm_memory_slot *new)
8266{
8267 /* Still write protect RO slot */
8268 if (new->flags & KVM_MEM_READONLY) {
8269 kvm_mmu_slot_remove_write_access(kvm, new);
8270 return;
8271 }
8272
8273 /*
8274 * Call kvm_x86_ops dirty logging hooks when they are valid.
8275 *
8276 * kvm_x86_ops->slot_disable_log_dirty is called when:
8277 *
8278 * - KVM_MR_CREATE with dirty logging is disabled
8279 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8280 *
8281 * The reason is, in case of PML, we need to set D-bit for any slots
8282 * with dirty logging disabled in order to eliminate unnecessary GPA
8283 * logging in PML buffer (and potential PML buffer full VMEXT). This
8284 * guarantees leaving PML enabled during guest's lifetime won't have
8285 * any additonal overhead from PML when guest is running with dirty
8286 * logging disabled for memory slots.
8287 *
8288 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8289 * to dirty logging mode.
8290 *
8291 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8292 *
8293 * In case of write protect:
8294 *
8295 * Write protect all pages for dirty logging.
8296 *
8297 * All the sptes including the large sptes which point to this
8298 * slot are set to readonly. We can not create any new large
8299 * spte on this slot until the end of the logging.
8300 *
8301 * See the comments in fast_page_fault().
8302 */
8303 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8304 if (kvm_x86_ops->slot_enable_log_dirty)
8305 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8306 else
8307 kvm_mmu_slot_remove_write_access(kvm, new);
8308 } else {
8309 if (kvm_x86_ops->slot_disable_log_dirty)
8310 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8311 }
8312}
8313
f7784b8e 8314void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8315 const struct kvm_userspace_memory_region *mem,
8482644a 8316 const struct kvm_memory_slot *old,
f36f3f28 8317 const struct kvm_memory_slot *new,
8482644a 8318 enum kvm_mr_change change)
f7784b8e 8319{
8482644a 8320 int nr_mmu_pages = 0;
f7784b8e 8321
48c0e4e9
XG		 8322 if (!kvm->arch.n_requested_mmu_pages)
8323 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8324
48c0e4e9 8325 if (nr_mmu_pages)
0de10343 8326 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8327
3ea3b7fa
WL		 8328 /*
8329 * Dirty logging tracks sptes in 4k granularity, meaning that large
8330 * sptes have to be split. If live migration is successful, the guest
8331 * in the source machine will be destroyed and large sptes will be
8332 * created in the destination. However, if the guest continues to run
8333 * in the source machine (for example if live migration fails), small
8334 * sptes will remain around and cause bad performance.
8335 *
8336 * Scan sptes if dirty logging has been stopped, dropping those
8337 * which can be collapsed into a single large-page spte. Later
8338 * page faults will create the large-page sptes.
8339 */
8340 if ((change != KVM_MR_DELETE) &&
8341 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8342 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8343 kvm_mmu_zap_collapsible_sptes(kvm, new);
8344
c972f3b1 8345 /*
88178fd4 8346 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8347 *
88178fd4
KH		 8348 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8349 * been zapped so no dirty logging staff is needed for old slot. For
8350 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8351 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8352 *
8353 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8354 */
88178fd4 8355 if (change != KVM_MR_DELETE)
f36f3f28 8356 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8357}
1d737c8a 8358
2df72e9b 8359void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8360{
6ca18b69 8361 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8362}
8363
2df72e9b
MT		 8364void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8365 struct kvm_memory_slot *slot)
8366{
ae7cd873 8367 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8368}
8369
5d9bc648
PB		 8370static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8371{
8372 if (!list_empty_careful(&vcpu->async_pf.done))
8373 return true;
8374
8375 if (kvm_apic_has_events(vcpu))
8376 return true;
8377
8378 if (vcpu->arch.pv.pv_unhalted)
8379 return true;
8380
8381 if (atomic_read(&vcpu->arch.nmi_queued))
8382 return true;
8383
72875d8a 8384 if (kvm_test_request(KVM_REQ_SMI, vcpu))
73917739
PB		 8385 return true;
8386
5d9bc648
PB		 8387 if (kvm_arch_interrupt_allowed(vcpu) &&
8388 kvm_cpu_has_interrupt(vcpu))
8389 return true;
8390
1f4b34f8
AS		 8391 if (kvm_hv_has_stimer_pending(vcpu))
8392 return true;
8393
5d9bc648
PB		 8394 return false;
8395}
8396
1d737c8a
ZX		 8397int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8398{
5d9bc648 8399 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8400}
5736199a 8401
b6d33834 8402int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8403{
b6d33834 8404 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8405}
78646121
GN		 8406
8407int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8408{
8409 return kvm_x86_ops->interrupt_allowed(vcpu);
8410}
229456fc 8411
82b32774 8412unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8413{
82b32774
NA		 8414 if (is_64_bit_mode(vcpu))
8415 return kvm_rip_read(vcpu);
8416 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8417 kvm_rip_read(vcpu));
8418}
8419EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8420
82b32774
NA		 8421bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8422{
8423 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8424}
8425EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8426
94fe45da
JK		 8427unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8428{
8429 unsigned long rflags;
8430
8431 rflags = kvm_x86_ops->get_rflags(vcpu);
8432 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8433 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8434 return rflags;
8435}
8436EXPORT_SYMBOL_GPL(kvm_get_rflags);
8437
6addfc42 8438static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8439{
8440 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8441 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8442 rflags |= X86_EFLAGS_TF;
94fe45da 8443 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8444}
8445
8446void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8447{
8448 __kvm_set_rflags(vcpu, rflags);
3842d135 8449 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8450}
8451EXPORT_SYMBOL_GPL(kvm_set_rflags);
8452
56028d08
GN		 8453void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8454{
8455 int r;
8456
fb67e14f 8457 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8458 work->wakeup_all)
56028d08
GN		 8459 return;
8460
8461 r = kvm_mmu_reload(vcpu);
8462 if (unlikely(r))
8463 return;
8464
fb67e14f
XG		 8465 if (!vcpu->arch.mmu.direct_map &&
8466 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8467 return;
8468
56028d08
GN		 8469 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8470}
8471
af585b92
GN		 8472static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8473{
8474 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8475}
8476
8477static inline u32 kvm_async_pf_next_probe(u32 key)
8478{
8479 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8480}
8481
8482static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8483{
8484 u32 key = kvm_async_pf_hash_fn(gfn);
8485
8486 while (vcpu->arch.apf.gfns[key] != ~0)
8487 key = kvm_async_pf_next_probe(key);
8488
8489 vcpu->arch.apf.gfns[key] = gfn;
8490}
8491
8492static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8493{
8494 int i;
8495 u32 key = kvm_async_pf_hash_fn(gfn);
8496
8497 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8498 (vcpu->arch.apf.gfns[key] != gfn &&
8499 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8500 key = kvm_async_pf_next_probe(key);
8501
8502 return key;
8503}
8504
8505bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8506{
8507 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8508}
8509
8510static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8511{
8512 u32 i, j, k;
8513
8514 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8515 while (true) {
8516 vcpu->arch.apf.gfns[i] = ~0;
8517 do {
8518 j = kvm_async_pf_next_probe(j);
8519 if (vcpu->arch.apf.gfns[j] == ~0)
8520 return;
8521 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8522 /*
8523 * k lies cyclically in ]i,j]
8524 * | i.k.j |
8525 * |....j i.k.| or |.k..j i...|
8526 */
8527 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8528 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8529 i = j;
8530 }
8531}
8532
7c90705b
GN		 8533static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8534{
4e335d9e
PB		 8535
8536 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8537 sizeof(val));
7c90705b
GN		 8538}
8539
af585b92
GN		 8540void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8541 struct kvm_async_pf *work)
8542{
6389ee94
AK		 8543 struct x86_exception fault;
8544
7c90705b 8545 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8546 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8547
8548 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8549 (vcpu->arch.apf.send_user_only &&
8550 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8551 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8552 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8553 fault.vector = PF_VECTOR;
8554 fault.error_code_valid = true;
8555 fault.error_code = 0;
8556 fault.nested_page_fault = false;
8557 fault.address = work->arch.token;
8558 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8559 }
af585b92
GN		 8560}
8561
8562void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8563 struct kvm_async_pf *work)
8564{
6389ee94
AK		 8565 struct x86_exception fault;
8566
f2e10669 8567 if (work->wakeup_all)
7c90705b
GN		 8568 work->arch.token = ~0; /* broadcast wakeup */
8569 else
8570 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 8571 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b
GN		 8572
8573 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8574 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8575 fault.vector = PF_VECTOR;
8576 fault.error_code_valid = true;
8577 fault.error_code = 0;
8578 fault.nested_page_fault = false;
8579 fault.address = work->arch.token;
8580 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8581 }
e6d53e3b 8582 vcpu->arch.apf.halted = false;
a4fa1635 8583 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8584}
8585
8586bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8587{
8588 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8589 return true;
8590 else
8591 return !kvm_event_needs_reinjection(vcpu) &&
8592 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8593}
8594
5544eb9b
PB		 8595void kvm_arch_start_assignment(struct kvm *kvm)
8596{
8597 atomic_inc(&kvm->arch.assigned_device_count);
8598}
8599EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8600
8601void kvm_arch_end_assignment(struct kvm *kvm)
8602{
8603 atomic_dec(&kvm->arch.assigned_device_count);
8604}
8605EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8606
8607bool kvm_arch_has_assigned_device(struct kvm *kvm)
8608{
8609 return atomic_read(&kvm->arch.assigned_device_count);
8610}
8611EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8612
e0f0bbc5
AW		 8613void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8614{
8615 atomic_inc(&kvm->arch.noncoherent_dma_count);
8616}
8617EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8618
8619void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8620{
8621 atomic_dec(&kvm->arch.noncoherent_dma_count);
8622}
8623EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8624
8625bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8626{
8627 return atomic_read(&kvm->arch.noncoherent_dma_count);
8628}
8629EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8630
14717e20
AW		 8631bool kvm_arch_has_irq_bypass(void)
8632{
8633 return kvm_x86_ops->update_pi_irte != NULL;
8634}
8635
87276880
FW		 8636int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8637 struct irq_bypass_producer *prod)
8638{
8639 struct kvm_kernel_irqfd *irqfd =
8640 container_of(cons, struct kvm_kernel_irqfd, consumer);
8641
14717e20 8642 irqfd->producer = prod;
87276880 8643
14717e20
AW		 8644 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8645 prod->irq, irqfd->gsi, 1);
87276880
FW		 8646}
8647
8648void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8649 struct irq_bypass_producer *prod)
8650{
8651 int ret;
8652 struct kvm_kernel_irqfd *irqfd =
8653 container_of(cons, struct kvm_kernel_irqfd, consumer);
8654
87276880
FW		 8655 WARN_ON(irqfd->producer != prod);
8656 irqfd->producer = NULL;
8657
8658 /*
8659 * When producer of consumer is unregistered, we change back to
8660 * remapped mode, so we can re-use the current implementation
bb3541f1 8661 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8662 * int this case doesn't want to receive the interrupts.
8663 */
8664 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8665 if (ret)
8666 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8667 " fails: %d\n", irqfd->consumer.token, ret);
8668}
8669
8670int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8671 uint32_t guest_irq, bool set)
8672{
8673 if (!kvm_x86_ops->update_pi_irte)
8674 return -EINVAL;
8675
8676 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8677}
8678
52004014
FW		 8679bool kvm_vector_hashing_enabled(void)
8680{
8681 return vector_hashing;
8682}
8683EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8684
229456fc 8685EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8686EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8687EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8688EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8689EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8690EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8691EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8692EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8693EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8694EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8695EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8696EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8697EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8698EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8699EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8700EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8701EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8702EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8703EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
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