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Merge tag 'for-linus-20170825' of git://git.infradead.org/linux-mtd
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad
IM		 56#include <linux/sched/stat.h>
57
aec51dc4 58#include <trace/events/kvm.h>
2ed152af 59
24f1e32c 60#include <asm/debugreg.h>
d825ed0a 61#include <asm/msr.h>
a5f61300 62#include <asm/desc.h>
890ca9ae 63#include <asm/mce.h>
f89e32e0 64#include <linux/kernel_stat.h>
78f7f1e5 65#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 66#include <asm/pvclock.h>
217fc9cf 67#include <asm/div64.h>
efc64404 68#include <asm/irq_remapping.h>
043405e1 69
d1898b73
DH		 70#define CREATE_TRACE_POINTS
71#include "trace.h"
72
313a3dc7 73#define MAX_IO_MSRS 256
890ca9ae 74#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 75u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
76EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 77
0f65dd70
AK		 78#define emul_to_vcpu(ctxt) \
79 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
80
50a37eb4
JR		 81/* EFER defaults:
82 * - enable syscall per default because its emulated by KVM
83 * - enable LME and LMA per default on 64 bit KVM
84 */
85#ifdef CONFIG_X86_64
1260edbe
LJ		 86static
87u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 88#else
1260edbe 89static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 90#endif
313a3dc7 91
ba1389b7
AK		 92#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
93#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 94
c519265f
RK		 95#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
96 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 97
cb142eb7 98static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 99static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 100static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 101static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 102
893590c7 103struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 104EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 105
893590c7 106static bool __read_mostly ignore_msrs = 0;
476bc001 107module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 108
9ed96e87
MT		 109unsigned int min_timer_period_us = 500;
110module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
111
630994b3
MT		 112static bool __read_mostly kvmclock_periodic_sync = true;
113module_param(kvmclock_periodic_sync, bool, S_IRUGO);
114
893590c7 115bool __read_mostly kvm_has_tsc_control;
92a1f12d 116EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 117u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 118EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 119u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
120EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
121u64 __read_mostly kvm_max_tsc_scaling_ratio;
122EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 123u64 __read_mostly kvm_default_tsc_scaling_ratio;
124EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 125
cc578287 126/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 127static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 128module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
129
d0659d94 130/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 131unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 132module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
133
52004014
FW		 134static bool __read_mostly vector_hashing = true;
135module_param(vector_hashing, bool, S_IRUGO);
136
18863bdd
AK		 137#define KVM_NR_SHARED_MSRS 16
138
139struct kvm_shared_msrs_global {
140 int nr;
2bf78fa7 141 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 142};
143
144struct kvm_shared_msrs {
145 struct user_return_notifier urn;
146 bool registered;
2bf78fa7
SY		 147 struct kvm_shared_msr_values {
148 u64 host;
149 u64 curr;
150 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 151};
152
153static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 154static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 155
417bc304 156struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 157 { "pf_fixed", VCPU_STAT(pf_fixed) },
158 { "pf_guest", VCPU_STAT(pf_guest) },
159 { "tlb_flush", VCPU_STAT(tlb_flush) },
160 { "invlpg", VCPU_STAT(invlpg) },
161 { "exits", VCPU_STAT(exits) },
162 { "io_exits", VCPU_STAT(io_exits) },
163 { "mmio_exits", VCPU_STAT(mmio_exits) },
164 { "signal_exits", VCPU_STAT(signal_exits) },
165 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 166 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 167 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 168 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 169 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 170 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 171 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 172 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 173 { "request_irq", VCPU_STAT(request_irq_exits) },
174 { "irq_exits", VCPU_STAT(irq_exits) },
175 { "host_state_reload", VCPU_STAT(host_state_reload) },
176 { "efer_reload", VCPU_STAT(efer_reload) },
177 { "fpu_reload", VCPU_STAT(fpu_reload) },
178 { "insn_emulation", VCPU_STAT(insn_emulation) },
179 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 180 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 181 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 182 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 183 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
184 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
185 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
186 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
187 { "mmu_flooded", VM_STAT(mmu_flooded) },
188 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 189 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 190 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 191 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 192 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 193 { "max_mmu_page_hash_collisions",
194 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 195 { NULL }
196};
197
2acf923e
DC		 198u64 __read_mostly host_xcr0;
199
b6785def 200static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 201
af585b92
GN		 202static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
203{
204 int i;
205 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
206 vcpu->arch.apf.gfns[i] = ~0;
207}
208
18863bdd
AK		 209static void kvm_on_user_return(struct user_return_notifier *urn)
210{
211 unsigned slot;
18863bdd
AK		 212 struct kvm_shared_msrs *locals
213 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 214 struct kvm_shared_msr_values *values;
1650b4eb
IA		 215 unsigned long flags;
216
217 /*
218 * Disabling irqs at this point since the following code could be
219 * interrupted and executed through kvm_arch_hardware_disable()
220 */
221 local_irq_save(flags);
222 if (locals->registered) {
223 locals->registered = false;
224 user_return_notifier_unregister(urn);
225 }
226 local_irq_restore(flags);
18863bdd 227 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 228 values = &locals->values[slot];
229 if (values->host != values->curr) {
230 wrmsrl(shared_msrs_global.msrs[slot], values->host);
231 values->curr = values->host;
18863bdd
AK		 232 }
233 }
18863bdd
AK		 234}
235
2bf78fa7 236static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 237{
18863bdd 238 u64 value;
013f6a5d
MT		 239 unsigned int cpu = smp_processor_id();
240 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 241
2bf78fa7
SY		 242 /* only read, and nobody should modify it at this time,
243 * so don't need lock */
244 if (slot >= shared_msrs_global.nr) {
245 printk(KERN_ERR "kvm: invalid MSR slot!");
246 return;
247 }
248 rdmsrl_safe(msr, &value);
249 smsr->values[slot].host = value;
250 smsr->values[slot].curr = value;
251}
252
253void kvm_define_shared_msr(unsigned slot, u32 msr)
254{
0123be42 255 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 256 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 257 if (slot >= shared_msrs_global.nr)
258 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 259}
260EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
261
262static void kvm_shared_msr_cpu_online(void)
263{
264 unsigned i;
18863bdd
AK		 265
266 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 267 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 268}
269
8b3c3104 270int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 271{
013f6a5d
MT		 272 unsigned int cpu = smp_processor_id();
273 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 274 int err;
18863bdd 275
2bf78fa7 276 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 277 return 0;
2bf78fa7 278 smsr->values[slot].curr = value;
8b3c3104
AH		 279 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
280 if (err)
281 return 1;
282
18863bdd
AK		 283 if (!smsr->registered) {
284 smsr->urn.on_user_return = kvm_on_user_return;
285 user_return_notifier_register(&smsr->urn);
286 smsr->registered = true;
287 }
8b3c3104 288 return 0;
18863bdd
AK		 289}
290EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
291
13a34e06 292static void drop_user_return_notifiers(void)
3548bab5 293{
013f6a5d
MT		 294 unsigned int cpu = smp_processor_id();
295 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 296
297 if (smsr->registered)
298 kvm_on_user_return(&smsr->urn);
299}
300
6866b83e
CO		 301u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
302{
8a5a87d9 303 return vcpu->arch.apic_base;
6866b83e
CO		 304}
305EXPORT_SYMBOL_GPL(kvm_get_apic_base);
306
58cb628d
JK		 307int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
308{
309 u64 old_state = vcpu->arch.apic_base &
310 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
311 u64 new_state = msr_info->data &
312 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
313 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
314 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
315
316 if (!msr_info->host_initiated &&
317 ((msr_info->data & reserved_bits) != 0 ||
318 new_state == X2APIC_ENABLE ||
319 (new_state == MSR_IA32_APICBASE_ENABLE &&
320 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
321 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
322 old_state == 0)))
323 return 1;
324
325 kvm_lapic_set_base(vcpu, msr_info->data);
326 return 0;
6866b83e
CO		 327}
328EXPORT_SYMBOL_GPL(kvm_set_apic_base);
329
2605fc21 330asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 331{
332 /* Fault while not rebooting. We want the trace. */
333 BUG();
334}
335EXPORT_SYMBOL_GPL(kvm_spurious_fault);
336
3fd28fce
ED		 337#define EXCPT_BENIGN 0
338#define EXCPT_CONTRIBUTORY 1
339#define EXCPT_PF 2
340
341static int exception_class(int vector)
342{
343 switch (vector) {
344 case PF_VECTOR:
345 return EXCPT_PF;
346 case DE_VECTOR:
347 case TS_VECTOR:
348 case NP_VECTOR:
349 case SS_VECTOR:
350 case GP_VECTOR:
351 return EXCPT_CONTRIBUTORY;
352 default:
353 break;
354 }
355 return EXCPT_BENIGN;
356}
357
d6e8c854
NA		 358#define EXCPT_FAULT 0
359#define EXCPT_TRAP 1
360#define EXCPT_ABORT 2
361#define EXCPT_INTERRUPT 3
362
363static int exception_type(int vector)
364{
365 unsigned int mask;
366
367 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
368 return EXCPT_INTERRUPT;
369
370 mask = 1 << vector;
371
372 /* #DB is trap, as instruction watchpoints are handled elsewhere */
373 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
374 return EXCPT_TRAP;
375
376 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
377 return EXCPT_ABORT;
378
379 /* Reserved exceptions will result in fault */
380 return EXCPT_FAULT;
381}
382
3fd28fce 383static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 384 unsigned nr, bool has_error, u32 error_code,
385 bool reinject)
3fd28fce
ED		 386{
387 u32 prev_nr;
388 int class1, class2;
389
3842d135
AK		 390 kvm_make_request(KVM_REQ_EVENT, vcpu);
391
3fd28fce
ED		 392 if (!vcpu->arch.exception.pending) {
393 queue:
3ffb2468
NA		 394 if (has_error && !is_protmode(vcpu))
395 has_error = false;
3fd28fce
ED		 396 vcpu->arch.exception.pending = true;
397 vcpu->arch.exception.has_error_code = has_error;
398 vcpu->arch.exception.nr = nr;
399 vcpu->arch.exception.error_code = error_code;
3f0fd292 400 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 401 return;
402 }
403
404 /* to check exception */
405 prev_nr = vcpu->arch.exception.nr;
406 if (prev_nr == DF_VECTOR) {
407 /* triple fault -> shutdown */
a8eeb04a 408 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 409 return;
410 }
411 class1 = exception_class(prev_nr);
412 class2 = exception_class(nr);
413 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
414 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
415 /* generate double fault per SDM Table 5-5 */
416 vcpu->arch.exception.pending = true;
417 vcpu->arch.exception.has_error_code = true;
418 vcpu->arch.exception.nr = DF_VECTOR;
419 vcpu->arch.exception.error_code = 0;
420 } else
421 /* replace previous exception with a new one in a hope
422 that instruction re-execution will regenerate lost
423 exception */
424 goto queue;
425}
426
298101da
AK		 427void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
428{
ce7ddec4 429 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 430}
431EXPORT_SYMBOL_GPL(kvm_queue_exception);
432
ce7ddec4
JR		 433void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
434{
435 kvm_multiple_exception(vcpu, nr, false, 0, true);
436}
437EXPORT_SYMBOL_GPL(kvm_requeue_exception);
438
6affcbed 439int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 440{
db8fcefa
AP		 441 if (err)
442 kvm_inject_gp(vcpu, 0);
443 else
6affcbed
KH		 444 return kvm_skip_emulated_instruction(vcpu);
445
446 return 1;
db8fcefa
AP		 447}
448EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 449
6389ee94 450void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 451{
452 ++vcpu->stat.pf_guest;
adfe20fb
WL		 453 vcpu->arch.exception.nested_apf =
454 is_guest_mode(vcpu) && fault->async_page_fault;
455 if (vcpu->arch.exception.nested_apf)
456 vcpu->arch.apf.nested_apf_token = fault->address;
457 else
458 vcpu->arch.cr2 = fault->address;
6389ee94 459 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 460}
27d6c865 461EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 462
ef54bcfe 463static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 464{
6389ee94
AK		 465 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
466 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 467 else
6389ee94 468 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 469
470 return fault->nested_page_fault;
d4f8cf66
JR		 471}
472
3419ffc8
SY		 473void kvm_inject_nmi(struct kvm_vcpu *vcpu)
474{
7460fb4a
AK		 475 atomic_inc(&vcpu->arch.nmi_queued);
476 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 477}
478EXPORT_SYMBOL_GPL(kvm_inject_nmi);
479
298101da
AK		 480void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
481{
ce7ddec4 482 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 483}
484EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
485
ce7ddec4
JR		 486void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
487{
488 kvm_multiple_exception(vcpu, nr, true, error_code, true);
489}
490EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
491
0a79b009
AK		 492/*
493 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
494 * a #GP and return false.
495 */
496bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 497{
0a79b009
AK		 498 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
499 return true;
500 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
501 return false;
298101da 502}
0a79b009 503EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 504
16f8a6f9
NA		 505bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
506{
507 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
508 return true;
509
510 kvm_queue_exception(vcpu, UD_VECTOR);
511 return false;
512}
513EXPORT_SYMBOL_GPL(kvm_require_dr);
514
ec92fe44
JR		 515/*
516 * This function will be used to read from the physical memory of the currently
54bf36aa 517 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 518 * can read from guest physical or from the guest's guest physical memory.
519 */
520int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
521 gfn_t ngfn, void *data, int offset, int len,
522 u32 access)
523{
54987b7a 524 struct x86_exception exception;
ec92fe44
JR		 525 gfn_t real_gfn;
526 gpa_t ngpa;
527
528 ngpa = gfn_to_gpa(ngfn);
54987b7a 529 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 530 if (real_gfn == UNMAPPED_GVA)
531 return -EFAULT;
532
533 real_gfn = gpa_to_gfn(real_gfn);
534
54bf36aa 535 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 536}
537EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
538
69b0049a 539static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 540 void *data, int offset, int len, u32 access)
541{
542 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
543 data, offset, len, access);
544}
545
a03490ed
CO		 546/*
547 * Load the pae pdptrs. Return true is they are all valid.
548 */
ff03a073 549int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 550{
551 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
552 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
553 int i;
554 int ret;
ff03a073 555 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 556
ff03a073
JR		 557 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
558 offset * sizeof(u64), sizeof(pdpte),
559 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 560 if (ret < 0) {
561 ret = 0;
562 goto out;
563 }
564 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 565 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 566 (pdpte[i] &
567 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 568 ret = 0;
569 goto out;
570 }
571 }
572 ret = 1;
573
ff03a073 574 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 575 __set_bit(VCPU_EXREG_PDPTR,
576 (unsigned long *)&vcpu->arch.regs_avail);
577 __set_bit(VCPU_EXREG_PDPTR,
578 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 579out:
a03490ed
CO		 580
581 return ret;
582}
cc4b6871 583EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 584
9ed38ffa 585bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 586{
ff03a073 587 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 588 bool changed = true;
3d06b8bf
JR		 589 int offset;
590 gfn_t gfn;
d835dfec
AK		 591 int r;
592
593 if (is_long_mode(vcpu) || !is_pae(vcpu))
594 return false;
595
6de4f3ad
AK		 596 if (!test_bit(VCPU_EXREG_PDPTR,
597 (unsigned long *)&vcpu->arch.regs_avail))
598 return true;
599
a512177e
PB		 600 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
601 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 602 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
603 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 604 if (r < 0)
605 goto out;
ff03a073 606 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 607out:
d835dfec
AK		 608
609 return changed;
610}
9ed38ffa 611EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 612
49a9b07e 613int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 614{
aad82703 615 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 616 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 617
f9a48e6a
AK		 618 cr0 |= X86_CR0_ET;
619
ab344828 620#ifdef CONFIG_X86_64
0f12244f
GN		 621 if (cr0 & 0xffffffff00000000UL)
622 return 1;
ab344828
GN		 623#endif
624
625 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 626
0f12244f
GN		 627 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
628 return 1;
a03490ed 629
0f12244f
GN		 630 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
631 return 1;
a03490ed
CO		 632
633 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
634#ifdef CONFIG_X86_64
f6801dff 635 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 636 int cs_db, cs_l;
637
0f12244f
GN		 638 if (!is_pae(vcpu))
639 return 1;
a03490ed 640 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 641 if (cs_l)
642 return 1;
a03490ed
CO		 643 } else
644#endif
ff03a073 645 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 646 kvm_read_cr3(vcpu)))
0f12244f 647 return 1;
a03490ed
CO		 648 }
649
ad756a16
MJ		 650 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
651 return 1;
652
a03490ed 653 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 654
d170c419 655 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 656 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 657 kvm_async_pf_hash_reset(vcpu);
658 }
e5f3f027 659
aad82703
SY		 660 if ((cr0 ^ old_cr0) & update_bits)
661 kvm_mmu_reset_context(vcpu);
b18d5431 662
879ae188
LE		 663 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
664 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
665 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 666 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
667
0f12244f
GN		 668 return 0;
669}
2d3ad1f4 670EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 671
2d3ad1f4 672void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 673{
49a9b07e 674 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 675}
2d3ad1f4 676EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 677
42bdf991
MT		 678static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
679{
680 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
681 !vcpu->guest_xcr0_loaded) {
682 /* kvm_set_xcr() also depends on this */
683 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
684 vcpu->guest_xcr0_loaded = 1;
685 }
686}
687
688static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
689{
690 if (vcpu->guest_xcr0_loaded) {
691 if (vcpu->arch.xcr0 != host_xcr0)
692 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
693 vcpu->guest_xcr0_loaded = 0;
694 }
695}
696
69b0049a 697static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 698{
56c103ec
LJ		 699 u64 xcr0 = xcr;
700 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 701 u64 valid_bits;
2acf923e
DC		 702
703 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
704 if (index != XCR_XFEATURE_ENABLED_MASK)
705 return 1;
d91cab78 706 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 707 return 1;
d91cab78 708 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 709 return 1;
46c34cb0
PB		 710
711 /*
712 * Do not allow the guest to set bits that we do not support
713 * saving. However, xcr0 bit 0 is always set, even if the
714 * emulated CPU does not support XSAVE (see fx_init).
715 */
d91cab78 716 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 717 if (xcr0 & ~valid_bits)
2acf923e 718 return 1;
46c34cb0 719
d91cab78
DH		 720 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
721 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 722 return 1;
723
d91cab78
DH		 724 if (xcr0 & XFEATURE_MASK_AVX512) {
725 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 726 return 1;
d91cab78 727 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 728 return 1;
729 }
2acf923e 730 vcpu->arch.xcr0 = xcr0;
56c103ec 731
d91cab78 732 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 733 kvm_update_cpuid(vcpu);
2acf923e
DC		 734 return 0;
735}
736
737int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
738{
764bcbc5
Z		 739 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
740 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 741 kvm_inject_gp(vcpu, 0);
742 return 1;
743 }
744 return 0;
745}
746EXPORT_SYMBOL_GPL(kvm_set_xcr);
747
a83b29c6 748int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 749{
fc78f519 750 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 751 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 752 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 753
0f12244f
GN		 754 if (cr4 & CR4_RESERVED_BITS)
755 return 1;
a03490ed 756
2acf923e
DC		 757 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
758 return 1;
759
c68b734f
YW		 760 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
761 return 1;
762
97ec8c06
FW		 763 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
764 return 1;
765
afcbf13f 766 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 767 return 1;
768
b9baba86
HH		 769 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
770 return 1;
771
a03490ed 772 if (is_long_mode(vcpu)) {
0f12244f
GN		 773 if (!(cr4 & X86_CR4_PAE))
774 return 1;
a2edf57f
AK		 775 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
776 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 777 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
778 kvm_read_cr3(vcpu)))
0f12244f
GN		 779 return 1;
780
ad756a16
MJ		 781 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
782 if (!guest_cpuid_has_pcid(vcpu))
783 return 1;
784
785 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
786 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
787 return 1;
788 }
789
5e1746d6 790 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 791 return 1;
a03490ed 792
ad756a16
MJ		 793 if (((cr4 ^ old_cr4) & pdptr_bits) ||
794 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 795 kvm_mmu_reset_context(vcpu);
0f12244f 796
b9baba86 797 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 798 kvm_update_cpuid(vcpu);
2acf923e 799
0f12244f
GN		 800 return 0;
801}
2d3ad1f4 802EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 803
2390218b 804int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 805{
ac146235 806#ifdef CONFIG_X86_64
9d88fca7 807 cr3 &= ~CR3_PCID_INVD;
ac146235 808#endif
9d88fca7 809
9f8fe504 810 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 811 kvm_mmu_sync_roots(vcpu);
77c3913b 812 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 813 return 0;
d835dfec
AK		 814 }
815
a03490ed 816 if (is_long_mode(vcpu)) {
d9f89b88
JK		 817 if (cr3 & CR3_L_MODE_RESERVED_BITS)
818 return 1;
819 } else if (is_pae(vcpu) && is_paging(vcpu) &&
820 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 821 return 1;
a03490ed 822
0f12244f 823 vcpu->arch.cr3 = cr3;
aff48baa 824 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 825 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 826 return 0;
827}
2d3ad1f4 828EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 829
eea1cff9 830int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 831{
0f12244f
GN		 832 if (cr8 & CR8_RESERVED_BITS)
833 return 1;
35754c98 834 if (lapic_in_kernel(vcpu))
a03490ed
CO		 835 kvm_lapic_set_tpr(vcpu, cr8);
836 else
ad312c7c 837 vcpu->arch.cr8 = cr8;
0f12244f
GN		 838 return 0;
839}
2d3ad1f4 840EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 841
2d3ad1f4 842unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 843{
35754c98 844 if (lapic_in_kernel(vcpu))
a03490ed
CO		 845 return kvm_lapic_get_cr8(vcpu);
846 else
ad312c7c 847 return vcpu->arch.cr8;
a03490ed 848}
2d3ad1f4 849EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 850
ae561ede
NA		 851static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
852{
853 int i;
854
855 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
856 for (i = 0; i < KVM_NR_DB_REGS; i++)
857 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
858 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
859 }
860}
861
73aaf249
JK		 862static void kvm_update_dr6(struct kvm_vcpu *vcpu)
863{
864 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
865 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
866}
867
c8639010
JK		 868static void kvm_update_dr7(struct kvm_vcpu *vcpu)
869{
870 unsigned long dr7;
871
872 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
873 dr7 = vcpu->arch.guest_debug_dr7;
874 else
875 dr7 = vcpu->arch.dr7;
876 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 877 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
878 if (dr7 & DR7_BP_EN_MASK)
879 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 880}
881
6f43ed01
NA		 882static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
883{
884 u64 fixed = DR6_FIXED_1;
885
886 if (!guest_cpuid_has_rtm(vcpu))
887 fixed |= DR6_RTM;
888 return fixed;
889}
890
338dbc97 891static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 892{
893 switch (dr) {
894 case 0 ... 3:
895 vcpu->arch.db[dr] = val;
896 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
897 vcpu->arch.eff_db[dr] = val;
898 break;
899 case 4:
020df079
GN		 900 /* fall through */
901 case 6:
338dbc97
GN		 902 if (val & 0xffffffff00000000ULL)
903 return -1; /* #GP */
6f43ed01 904 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 905 kvm_update_dr6(vcpu);
020df079
GN		 906 break;
907 case 5:
020df079
GN		 908 /* fall through */
909 default: /* 7 */
338dbc97
GN		 910 if (val & 0xffffffff00000000ULL)
911 return -1; /* #GP */
020df079 912 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 913 kvm_update_dr7(vcpu);
020df079
GN		 914 break;
915 }
916
917 return 0;
918}
338dbc97
GN		 919
920int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
921{
16f8a6f9 922 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 923 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 924 return 1;
925 }
926 return 0;
338dbc97 927}
020df079
GN		 928EXPORT_SYMBOL_GPL(kvm_set_dr);
929
16f8a6f9 930int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 931{
932 switch (dr) {
933 case 0 ... 3:
934 *val = vcpu->arch.db[dr];
935 break;
936 case 4:
020df079
GN		 937 /* fall through */
938 case 6:
73aaf249
JK		 939 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
940 *val = vcpu->arch.dr6;
941 else
942 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 943 break;
944 case 5:
020df079
GN		 945 /* fall through */
946 default: /* 7 */
947 *val = vcpu->arch.dr7;
948 break;
949 }
338dbc97
GN		 950 return 0;
951}
020df079
GN		 952EXPORT_SYMBOL_GPL(kvm_get_dr);
953
022cd0e8
AK		 954bool kvm_rdpmc(struct kvm_vcpu *vcpu)
955{
956 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
957 u64 data;
958 int err;
959
c6702c9d 960 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 961 if (err)
962 return err;
963 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
964 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
965 return err;
966}
967EXPORT_SYMBOL_GPL(kvm_rdpmc);
968
043405e1
CO		 969/*
970 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
971 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
972 *
973 * This list is modified at module load time to reflect the
e3267cbb 974 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 975 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
976 * may depend on host virtualization features rather than host cpu features.
043405e1 977 */
e3267cbb 978
043405e1
CO		 979static u32 msrs_to_save[] = {
980 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 981 MSR_STAR,
043405e1
CO		 982#ifdef CONFIG_X86_64
983 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
984#endif
b3897a49 985 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 986 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 987};
988
989static unsigned num_msrs_to_save;
990
62ef68bb
PB		 991static u32 emulated_msrs[] = {
992 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
993 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
994 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
995 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 996 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
997 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 998 HV_X64_MSR_RESET,
11c4b1ca 999 HV_X64_MSR_VP_INDEX,
9eec50b8 1000 HV_X64_MSR_VP_RUNTIME,
5c919412 1001 HV_X64_MSR_SCONTROL,
1f4b34f8 1002 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 1003 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1004 MSR_KVM_PV_EOI_EN,
1005
ba904635 1006 MSR_IA32_TSC_ADJUST,
a3e06bbe 1007 MSR_IA32_TSCDEADLINE,
043405e1 1008 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1009 MSR_IA32_MCG_STATUS,
1010 MSR_IA32_MCG_CTL,
c45dcc71 1011 MSR_IA32_MCG_EXT_CTL,
64d60670 1012 MSR_IA32_SMBASE,
db2336a8
KH		 1013 MSR_PLATFORM_INFO,
1014 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1015};
1016
62ef68bb
PB		 1017static unsigned num_emulated_msrs;
1018
384bb783 1019bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1020{
b69e8cae 1021 if (efer & efer_reserved_bits)
384bb783 1022 return false;
15c4a640 1023
1b2fd70c
AG		 1024 if (efer & EFER_FFXSR) {
1025 struct kvm_cpuid_entry2 *feat;
1026
1027 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1028 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 1029 return false;
1b2fd70c
AG		 1030 }
1031
d8017474
AG		 1032 if (efer & EFER_SVME) {
1033 struct kvm_cpuid_entry2 *feat;
1034
1035 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1036 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1037 return false;
d8017474
AG		 1038 }
1039
384bb783
JK		 1040 return true;
1041}
1042EXPORT_SYMBOL_GPL(kvm_valid_efer);
1043
1044static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1045{
1046 u64 old_efer = vcpu->arch.efer;
1047
1048 if (!kvm_valid_efer(vcpu, efer))
1049 return 1;
1050
1051 if (is_paging(vcpu)
1052 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1053 return 1;
1054
15c4a640 1055 efer &= ~EFER_LMA;
f6801dff 1056 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1057
a3d204e2
SY		 1058 kvm_x86_ops->set_efer(vcpu, efer);
1059
aad82703
SY		 1060 /* Update reserved bits */
1061 if ((efer ^ old_efer) & EFER_NX)
1062 kvm_mmu_reset_context(vcpu);
1063
b69e8cae 1064 return 0;
15c4a640
CO		 1065}
1066
f2b4b7dd
JR		 1067void kvm_enable_efer_bits(u64 mask)
1068{
1069 efer_reserved_bits &= ~mask;
1070}
1071EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1072
15c4a640
CO		 1073/*
1074 * Writes msr value into into the appropriate "register".
1075 * Returns 0 on success, non-0 otherwise.
1076 * Assumes vcpu_load() was already called.
1077 */
8fe8ab46 1078int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1079{
854e8bb1
NA		 1080 switch (msr->index) {
1081 case MSR_FS_BASE:
1082 case MSR_GS_BASE:
1083 case MSR_KERNEL_GS_BASE:
1084 case MSR_CSTAR:
1085 case MSR_LSTAR:
1086 if (is_noncanonical_address(msr->data))
1087 return 1;
1088 break;
1089 case MSR_IA32_SYSENTER_EIP:
1090 case MSR_IA32_SYSENTER_ESP:
1091 /*
1092 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1093 * non-canonical address is written on Intel but not on
1094 * AMD (which ignores the top 32-bits, because it does
1095 * not implement 64-bit SYSENTER).
1096 *
1097 * 64-bit code should hence be able to write a non-canonical
1098 * value on AMD. Making the address canonical ensures that
1099 * vmentry does not fail on Intel after writing a non-canonical
1100 * value, and that something deterministic happens if the guest
1101 * invokes 64-bit SYSENTER.
1102 */
1103 msr->data = get_canonical(msr->data);
1104 }
8fe8ab46 1105 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1106}
854e8bb1 1107EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1108
313a3dc7
CO		 1109/*
1110 * Adapt set_msr() to msr_io()'s calling convention
1111 */
609e36d3
PB		 1112static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1113{
1114 struct msr_data msr;
1115 int r;
1116
1117 msr.index = index;
1118 msr.host_initiated = true;
1119 r = kvm_get_msr(vcpu, &msr);
1120 if (r)
1121 return r;
1122
1123 *data = msr.data;
1124 return 0;
1125}
1126
313a3dc7
CO		 1127static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1128{
8fe8ab46
WA		 1129 struct msr_data msr;
1130
1131 msr.data = *data;
1132 msr.index = index;
1133 msr.host_initiated = true;
1134 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1135}
1136
16e8d74d
MT		 1137#ifdef CONFIG_X86_64
1138struct pvclock_gtod_data {
1139 seqcount_t seq;
1140
1141 struct { /* extract of a clocksource struct */
1142 int vclock_mode;
a5a1d1c2
TG		 1143 u64 cycle_last;
1144 u64 mask;
16e8d74d
MT		 1145 u32 mult;
1146 u32 shift;
1147 } clock;
1148
cbcf2dd3
TG		 1149 u64 boot_ns;
1150 u64 nsec_base;
55dd00a7 1151 u64 wall_time_sec;
16e8d74d
MT		 1152};
1153
1154static struct pvclock_gtod_data pvclock_gtod_data;
1155
1156static void update_pvclock_gtod(struct timekeeper *tk)
1157{
1158 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1159 u64 boot_ns;
1160
876e7881 1161 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1162
1163 write_seqcount_begin(&vdata->seq);
1164
1165 /* copy pvclock gtod data */
876e7881
PZ		 1166 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1167 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1168 vdata->clock.mask = tk->tkr_mono.mask;
1169 vdata->clock.mult = tk->tkr_mono.mult;
1170 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1171
cbcf2dd3 1172 vdata->boot_ns = boot_ns;
876e7881 1173 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1174
55dd00a7
MT		 1175 vdata->wall_time_sec = tk->xtime_sec;
1176
16e8d74d
MT		 1177 write_seqcount_end(&vdata->seq);
1178}
1179#endif
1180
bab5bb39
NK		 1181void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1182{
1183 /*
1184 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1185 * vcpu_enter_guest. This function is only called from
1186 * the physical CPU that is running vcpu.
1187 */
1188 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1189}
16e8d74d 1190
18068523
GOC		 1191static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1192{
9ed3c444
AK		 1193 int version;
1194 int r;
50d0a0f9 1195 struct pvclock_wall_clock wc;
87aeb54f 1196 struct timespec64 boot;
18068523
GOC		 1197
1198 if (!wall_clock)
1199 return;
1200
9ed3c444
AK		 1201 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1202 if (r)
1203 return;
1204
1205 if (version & 1)
1206 ++version; /* first time write, random junk */
1207
1208 ++version;
18068523 1209
1dab1345
NK		 1210 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1211 return;
18068523 1212
50d0a0f9
GH		 1213 /*
1214 * The guest calculates current wall clock time by adding
34c238a1 1215 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1216 * wall clock specified here. guest system time equals host
1217 * system time for us, thus we must fill in host boot time here.
1218 */
87aeb54f 1219 getboottime64(&boot);
50d0a0f9 1220
4b648665 1221 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1222 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1223 boot = timespec64_sub(boot, ts);
4b648665 1224 }
87aeb54f 1225 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1226 wc.nsec = boot.tv_nsec;
1227 wc.version = version;
18068523
GOC		 1228
1229 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1230
1231 version++;
1232 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1233}
1234
50d0a0f9
GH		 1235static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1236{
b51012de
PB		 1237 do_shl32_div32(dividend, divisor);
1238 return dividend;
50d0a0f9
GH		 1239}
1240
3ae13faa 1241static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1242 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1243{
5f4e3f88 1244 uint64_t scaled64;
50d0a0f9
GH		 1245 int32_t shift = 0;
1246 uint64_t tps64;
1247 uint32_t tps32;
1248
3ae13faa
PB		 1249 tps64 = base_hz;
1250 scaled64 = scaled_hz;
50933623 1251 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1252 tps64 >>= 1;
1253 shift--;
1254 }
1255
1256 tps32 = (uint32_t)tps64;
50933623
JK		 1257 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1258 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1259 scaled64 >>= 1;
1260 else
1261 tps32 <<= 1;
50d0a0f9
GH		 1262 shift++;
1263 }
1264
5f4e3f88
ZA		 1265 *pshift = shift;
1266 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1267
3ae13faa
PB		 1268 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1269 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1270}
1271
d828199e 1272#ifdef CONFIG_X86_64
16e8d74d 1273static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1274#endif
16e8d74d 1275
c8076604 1276static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1277static unsigned long max_tsc_khz;
c8076604 1278
cc578287 1279static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1280{
cc578287
ZA		 1281 u64 v = (u64)khz * (1000000 + ppm);
1282 do_div(v, 1000000);
1283 return v;
1e993611
JR		 1284}
1285
381d585c
HZ		 1286static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1287{
1288 u64 ratio;
1289
1290 /* Guest TSC same frequency as host TSC? */
1291 if (!scale) {
1292 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1293 return 0;
1294 }
1295
1296 /* TSC scaling supported? */
1297 if (!kvm_has_tsc_control) {
1298 if (user_tsc_khz > tsc_khz) {
1299 vcpu->arch.tsc_catchup = 1;
1300 vcpu->arch.tsc_always_catchup = 1;
1301 return 0;
1302 } else {
1303 WARN(1, "user requested TSC rate below hardware speed\n");
1304 return -1;
1305 }
1306 }
1307
1308 /* TSC scaling required - calculate ratio */
1309 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1310 user_tsc_khz, tsc_khz);
1311
1312 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1313 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1314 user_tsc_khz);
1315 return -1;
1316 }
1317
1318 vcpu->arch.tsc_scaling_ratio = ratio;
1319 return 0;
1320}
1321
4941b8cb 1322static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1323{
cc578287
ZA		 1324 u32 thresh_lo, thresh_hi;
1325 int use_scaling = 0;
217fc9cf 1326
03ba32ca 1327 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1328 if (user_tsc_khz == 0) {
ad721883
HZ		 1329 /* set tsc_scaling_ratio to a safe value */
1330 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1331 return -1;
ad721883 1332 }
03ba32ca 1333
c285545f 1334 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1335 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1336 &vcpu->arch.virtual_tsc_shift,
1337 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1338 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1339
1340 /*
1341 * Compute the variation in TSC rate which is acceptable
1342 * within the range of tolerance and decide if the
1343 * rate being applied is within that bounds of the hardware
1344 * rate. If so, no scaling or compensation need be done.
1345 */
1346 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1347 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1348 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1349 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1350 use_scaling = 1;
1351 }
4941b8cb 1352 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1353}
1354
1355static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1356{
e26101b1 1357 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1358 vcpu->arch.virtual_tsc_mult,
1359 vcpu->arch.virtual_tsc_shift);
e26101b1 1360 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1361 return tsc;
1362}
1363
69b0049a 1364static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1365{
1366#ifdef CONFIG_X86_64
1367 bool vcpus_matched;
b48aa97e
MT		 1368 struct kvm_arch *ka = &vcpu->kvm->arch;
1369 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1370
1371 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1372 atomic_read(&vcpu->kvm->online_vcpus));
1373
7f187922
MT		 1374 /*
1375 * Once the masterclock is enabled, always perform request in
1376 * order to update it.
1377 *
1378 * In order to enable masterclock, the host clocksource must be TSC
1379 * and the vcpus need to have matched TSCs. When that happens,
1380 * perform request to enable masterclock.
1381 */
1382 if (ka->use_master_clock ||
1383 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1384 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1385
1386 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1387 atomic_read(&vcpu->kvm->online_vcpus),
1388 ka->use_master_clock, gtod->clock.vclock_mode);
1389#endif
1390}
1391
ba904635
WA		 1392static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1393{
3e3f5026 1394 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1395 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1396}
1397
35181e86
HZ		 1398/*
1399 * Multiply tsc by a fixed point number represented by ratio.
1400 *
1401 * The most significant 64-N bits (mult) of ratio represent the
1402 * integral part of the fixed point number; the remaining N bits
1403 * (frac) represent the fractional part, ie. ratio represents a fixed
1404 * point number (mult + frac * 2^(-N)).
1405 *
1406 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1407 */
1408static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1409{
1410 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1411}
1412
1413u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1414{
1415 u64 _tsc = tsc;
1416 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1417
1418 if (ratio != kvm_default_tsc_scaling_ratio)
1419 _tsc = __scale_tsc(ratio, tsc);
1420
1421 return _tsc;
1422}
1423EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1424
07c1419a
HZ		 1425static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1426{
1427 u64 tsc;
1428
1429 tsc = kvm_scale_tsc(vcpu, rdtsc());
1430
1431 return target_tsc - tsc;
1432}
1433
4ba76538
HZ		 1434u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1435{
ea26e4ec 1436 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1437}
1438EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1439
a545ab6a
LC		 1440static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1441{
1442 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1443 vcpu->arch.tsc_offset = offset;
1444}
1445
8fe8ab46 1446void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1447{
1448 struct kvm *kvm = vcpu->kvm;
f38e098f 1449 u64 offset, ns, elapsed;
99e3e30a 1450 unsigned long flags;
b48aa97e 1451 bool matched;
0d3da0d2 1452 bool already_matched;
8fe8ab46 1453 u64 data = msr->data;
c5e8ec8e 1454 bool synchronizing = false;
99e3e30a 1455
038f8c11 1456 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1457 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1458 ns = ktime_get_boot_ns();
f38e098f 1459 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1460
03ba32ca 1461 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1462 if (data == 0 && msr->host_initiated) {
1463 /*
1464 * detection of vcpu initialization -- need to sync
1465 * with other vCPUs. This particularly helps to keep
1466 * kvm_clock stable after CPU hotplug
1467 */
1468 synchronizing = true;
1469 } else {
1470 u64 tsc_exp = kvm->arch.last_tsc_write +
1471 nsec_to_cycles(vcpu, elapsed);
1472 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1473 /*
1474 * Special case: TSC write with a small delta (1 second)
1475 * of virtual cycle time against real time is
1476 * interpreted as an attempt to synchronize the CPU.
1477 */
1478 synchronizing = data < tsc_exp + tsc_hz &&
1479 data + tsc_hz > tsc_exp;
1480 }
c5e8ec8e 1481 }
f38e098f
ZA		 1482
1483 /*
5d3cb0f6
ZA		 1484 * For a reliable TSC, we can match TSC offsets, and for an unstable
1485 * TSC, we add elapsed time in this computation. We could let the
1486 * compensation code attempt to catch up if we fall behind, but
1487 * it's better to try to match offsets from the beginning.
1488 */
c5e8ec8e 1489 if (synchronizing &&
5d3cb0f6 1490 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1491 if (!check_tsc_unstable()) {
e26101b1 1492 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1493 pr_debug("kvm: matched tsc offset for %llu\n", data);
1494 } else {
857e4099 1495 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1496 data += delta;
07c1419a 1497 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1498 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1499 }
b48aa97e 1500 matched = true;
0d3da0d2 1501 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1502 } else {
1503 /*
1504 * We split periods of matched TSC writes into generations.
1505 * For each generation, we track the original measured
1506 * nanosecond time, offset, and write, so if TSCs are in
1507 * sync, we can match exact offset, and if not, we can match
4a969980 1508 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1509 *
1510 * These values are tracked in kvm->arch.cur_xxx variables.
1511 */
1512 kvm->arch.cur_tsc_generation++;
1513 kvm->arch.cur_tsc_nsec = ns;
1514 kvm->arch.cur_tsc_write = data;
1515 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1516 matched = false;
0d3da0d2 1517 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1518 kvm->arch.cur_tsc_generation, data);
f38e098f 1519 }
e26101b1
ZA		 1520
1521 /*
1522 * We also track th most recent recorded KHZ, write and time to
1523 * allow the matching interval to be extended at each write.
1524 */
f38e098f
ZA		 1525 kvm->arch.last_tsc_nsec = ns;
1526 kvm->arch.last_tsc_write = data;
5d3cb0f6 1527 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1528
b183aa58 1529 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1530
1531 /* Keep track of which generation this VCPU has synchronized to */
1532 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1533 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1534 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1535
ba904635
WA		 1536 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1537 update_ia32_tsc_adjust_msr(vcpu, offset);
a545ab6a 1538 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1539 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1540
1541 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1542 if (!matched) {
b48aa97e 1543 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1544 } else if (!already_matched) {
1545 kvm->arch.nr_vcpus_matched_tsc++;
1546 }
b48aa97e
MT		 1547
1548 kvm_track_tsc_matching(vcpu);
1549 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1550}
e26101b1 1551
99e3e30a
ZA		 1552EXPORT_SYMBOL_GPL(kvm_write_tsc);
1553
58ea6767
HZ		 1554static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1555 s64 adjustment)
1556{
ea26e4ec 1557 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1558}
1559
1560static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1561{
1562 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1563 WARN_ON(adjustment < 0);
1564 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1565 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1566}
1567
d828199e
MT		 1568#ifdef CONFIG_X86_64
1569
a5a1d1c2 1570static u64 read_tsc(void)
d828199e 1571{
a5a1d1c2 1572 u64 ret = (u64)rdtsc_ordered();
03b9730b 1573 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1574
1575 if (likely(ret >= last))
1576 return ret;
1577
1578 /*
1579 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1580 * predictable (it's just a function of time and the likely is
d828199e
MT		 1581 * very likely) and there's a data dependence, so force GCC
1582 * to generate a branch instead. I don't barrier() because
1583 * we don't actually need a barrier, and if this function
1584 * ever gets inlined it will generate worse code.
1585 */
1586 asm volatile ("");
1587 return last;
1588}
1589
a5a1d1c2 1590static inline u64 vgettsc(u64 *cycle_now)
d828199e
MT		 1591{
1592 long v;
1593 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1594
1595 *cycle_now = read_tsc();
1596
1597 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1598 return v * gtod->clock.mult;
1599}
1600
a5a1d1c2 1601static int do_monotonic_boot(s64 *t, u64 *cycle_now)
d828199e 1602{
cbcf2dd3 1603 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1604 unsigned long seq;
d828199e 1605 int mode;
cbcf2dd3 1606 u64 ns;
d828199e 1607
d828199e
MT		 1608 do {
1609 seq = read_seqcount_begin(&gtod->seq);
1610 mode = gtod->clock.vclock_mode;
cbcf2dd3 1611 ns = gtod->nsec_base;
d828199e
MT		 1612 ns += vgettsc(cycle_now);
1613 ns >>= gtod->clock.shift;
cbcf2dd3 1614 ns += gtod->boot_ns;
d828199e 1615 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1616 *t = ns;
d828199e
MT		 1617
1618 return mode;
1619}
1620
55dd00a7
MT		 1621static int do_realtime(struct timespec *ts, u64 *cycle_now)
1622{
1623 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1624 unsigned long seq;
1625 int mode;
1626 u64 ns;
1627
1628 do {
1629 seq = read_seqcount_begin(&gtod->seq);
1630 mode = gtod->clock.vclock_mode;
1631 ts->tv_sec = gtod->wall_time_sec;
1632 ns = gtod->nsec_base;
1633 ns += vgettsc(cycle_now);
1634 ns >>= gtod->clock.shift;
1635 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1636
1637 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1638 ts->tv_nsec = ns;
1639
1640 return mode;
1641}
1642
d828199e 1643/* returns true if host is using tsc clocksource */
a5a1d1c2 1644static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
d828199e 1645{
d828199e
MT		 1646 /* checked again under seqlock below */
1647 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1648 return false;
1649
cbcf2dd3 1650 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e 1651}
55dd00a7
MT		 1652
1653/* returns true if host is using tsc clocksource */
1654static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1655 u64 *cycle_now)
1656{
1657 /* checked again under seqlock below */
1658 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1659 return false;
1660
1661 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1662}
d828199e
MT		 1663#endif
1664
1665/*
1666 *
b48aa97e
MT		 1667 * Assuming a stable TSC across physical CPUS, and a stable TSC
1668 * across virtual CPUs, the following condition is possible.
1669 * Each numbered line represents an event visible to both
d828199e
MT		 1670 * CPUs at the next numbered event.
1671 *
1672 * "timespecX" represents host monotonic time. "tscX" represents
1673 * RDTSC value.
1674 *
1675 * VCPU0 on CPU0 | VCPU1 on CPU1
1676 *
1677 * 1. read timespec0,tsc0
1678 * 2. | timespec1 = timespec0 + N
1679 * | tsc1 = tsc0 + M
1680 * 3. transition to guest | transition to guest
1681 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1682 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1683 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1684 *
1685 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1686 *
1687 * - ret0 < ret1
1688 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1689 * ...
1690 * - 0 < N - M => M < N
1691 *
1692 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1693 * always the case (the difference between two distinct xtime instances
1694 * might be smaller then the difference between corresponding TSC reads,
1695 * when updating guest vcpus pvclock areas).
1696 *
1697 * To avoid that problem, do not allow visibility of distinct
1698 * system_timestamp/tsc_timestamp values simultaneously: use a master
1699 * copy of host monotonic time values. Update that master copy
1700 * in lockstep.
1701 *
b48aa97e 1702 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1703 *
1704 */
1705
1706static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1707{
1708#ifdef CONFIG_X86_64
1709 struct kvm_arch *ka = &kvm->arch;
1710 int vclock_mode;
b48aa97e
MT		 1711 bool host_tsc_clocksource, vcpus_matched;
1712
1713 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1714 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1715
1716 /*
1717 * If the host uses TSC clock, then passthrough TSC as stable
1718 * to the guest.
1719 */
b48aa97e 1720 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1721 &ka->master_kernel_ns,
1722 &ka->master_cycle_now);
1723
16a96021 1724 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1725 && !ka->backwards_tsc_observed
54750f2c 1726 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1727
d828199e
MT		 1728 if (ka->use_master_clock)
1729 atomic_set(&kvm_guest_has_master_clock, 1);
1730
1731 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1732 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1733 vcpus_matched);
d828199e
MT		 1734#endif
1735}
1736
2860c4b1
PB		 1737void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1738{
1739 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1740}
1741
2e762ff7
MT		 1742static void kvm_gen_update_masterclock(struct kvm *kvm)
1743{
1744#ifdef CONFIG_X86_64
1745 int i;
1746 struct kvm_vcpu *vcpu;
1747 struct kvm_arch *ka = &kvm->arch;
1748
1749 spin_lock(&ka->pvclock_gtod_sync_lock);
1750 kvm_make_mclock_inprogress_request(kvm);
1751 /* no guest entries from this point */
1752 pvclock_update_vm_gtod_copy(kvm);
1753
1754 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1755 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1756
1757 /* guest entries allowed */
1758 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1759 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1760
1761 spin_unlock(&ka->pvclock_gtod_sync_lock);
1762#endif
1763}
1764
e891a32e 1765u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1766{
108b249c 1767 struct kvm_arch *ka = &kvm->arch;
8b953440 1768 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1769 u64 ret;
108b249c 1770
8b953440
PB		 1771 spin_lock(&ka->pvclock_gtod_sync_lock);
1772 if (!ka->use_master_clock) {
1773 spin_unlock(&ka->pvclock_gtod_sync_lock);
1774 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1775 }
1776
8b953440
PB		 1777 hv_clock.tsc_timestamp = ka->master_cycle_now;
1778 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1779 spin_unlock(&ka->pvclock_gtod_sync_lock);
1780
e2c2206a
WL		 1781 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1782 get_cpu();
1783
8b953440
PB		 1784 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1785 &hv_clock.tsc_shift,
1786 &hv_clock.tsc_to_system_mul);
e2c2206a
WL		 1787 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1788
1789 put_cpu();
1790
1791 return ret;
108b249c
PB		 1792}
1793
0d6dd2ff
PB		 1794static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1795{
1796 struct kvm_vcpu_arch *vcpu = &v->arch;
1797 struct pvclock_vcpu_time_info guest_hv_clock;
1798
4e335d9e 1799 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1800 &guest_hv_clock, sizeof(guest_hv_clock))))
1801 return;
1802
1803 /* This VCPU is paused, but it's legal for a guest to read another
1804 * VCPU's kvmclock, so we really have to follow the specification where
1805 * it says that version is odd if data is being modified, and even after
1806 * it is consistent.
1807 *
1808 * Version field updates must be kept separate. This is because
1809 * kvm_write_guest_cached might use a "rep movs" instruction, and
1810 * writes within a string instruction are weakly ordered. So there
1811 * are three writes overall.
1812 *
1813 * As a small optimization, only write the version field in the first
1814 * and third write. The vcpu->pv_time cache is still valid, because the
1815 * version field is the first in the struct.
1816 */
1817 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1818
1819 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1820 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1821 &vcpu->hv_clock,
1822 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1823
1824 smp_wmb();
1825
1826 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1827 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1828
1829 if (vcpu->pvclock_set_guest_stopped_request) {
1830 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1831 vcpu->pvclock_set_guest_stopped_request = false;
1832 }
1833
1834 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1835
4e335d9e
PB		 1836 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1837 &vcpu->hv_clock,
1838 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1839
1840 smp_wmb();
1841
1842 vcpu->hv_clock.version++;
4e335d9e
PB		 1843 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1844 &vcpu->hv_clock,
1845 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1846}
1847
34c238a1 1848static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1849{
78db6a50 1850 unsigned long flags, tgt_tsc_khz;
18068523 1851 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1852 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1853 s64 kernel_ns;
d828199e 1854 u64 tsc_timestamp, host_tsc;
51d59c6b 1855 u8 pvclock_flags;
d828199e
MT		 1856 bool use_master_clock;
1857
1858 kernel_ns = 0;
1859 host_tsc = 0;
18068523 1860
d828199e
MT		 1861 /*
1862 * If the host uses TSC clock, then passthrough TSC as stable
1863 * to the guest.
1864 */
1865 spin_lock(&ka->pvclock_gtod_sync_lock);
1866 use_master_clock = ka->use_master_clock;
1867 if (use_master_clock) {
1868 host_tsc = ka->master_cycle_now;
1869 kernel_ns = ka->master_kernel_ns;
1870 }
1871 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1872
1873 /* Keep irq disabled to prevent changes to the clock */
1874 local_irq_save(flags);
78db6a50
PB		 1875 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1876 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1877 local_irq_restore(flags);
1878 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1879 return 1;
1880 }
d828199e 1881 if (!use_master_clock) {
4ea1636b 1882 host_tsc = rdtsc();
108b249c 1883 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1884 }
1885
4ba76538 1886 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1887
c285545f
ZA		 1888 /*
1889 * We may have to catch up the TSC to match elapsed wall clock
1890 * time for two reasons, even if kvmclock is used.
1891 * 1) CPU could have been running below the maximum TSC rate
1892 * 2) Broken TSC compensation resets the base at each VCPU
1893 * entry to avoid unknown leaps of TSC even when running
1894 * again on the same CPU. This may cause apparent elapsed
1895 * time to disappear, and the guest to stand still or run
1896 * very slowly.
1897 */
1898 if (vcpu->tsc_catchup) {
1899 u64 tsc = compute_guest_tsc(v, kernel_ns);
1900 if (tsc > tsc_timestamp) {
f1e2b260 1901 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1902 tsc_timestamp = tsc;
1903 }
50d0a0f9
GH		 1904 }
1905
18068523
GOC		 1906 local_irq_restore(flags);
1907
0d6dd2ff 1908 /* With all the info we got, fill in the values */
18068523 1909
78db6a50
PB		 1910 if (kvm_has_tsc_control)
1911 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1912
1913 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1914 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1915 &vcpu->hv_clock.tsc_shift,
1916 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1917 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1918 }
1919
1d5f066e 1920 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1921 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1922 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1923
d828199e 1924 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 1925 pvclock_flags = 0;
d828199e
MT		 1926 if (use_master_clock)
1927 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1928
78c0337a
MT		 1929 vcpu->hv_clock.flags = pvclock_flags;
1930
095cf55d
PB		 1931 if (vcpu->pv_time_enabled)
1932 kvm_setup_pvclock_page(v);
1933 if (v == kvm_get_vcpu(v->kvm, 0))
1934 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 1935 return 0;
c8076604
GH		 1936}
1937
0061d53d
MT		 1938/*
1939 * kvmclock updates which are isolated to a given vcpu, such as
1940 * vcpu->cpu migration, should not allow system_timestamp from
1941 * the rest of the vcpus to remain static. Otherwise ntp frequency
1942 * correction applies to one vcpu's system_timestamp but not
1943 * the others.
1944 *
1945 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1946 * We need to rate-limit these requests though, as they can
1947 * considerably slow guests that have a large number of vcpus.
1948 * The time for a remote vcpu to update its kvmclock is bound
1949 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1950 */
1951
7e44e449
AJ		 1952#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1953
1954static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1955{
1956 int i;
7e44e449
AJ		 1957 struct delayed_work *dwork = to_delayed_work(work);
1958 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1959 kvmclock_update_work);
1960 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1961 struct kvm_vcpu *vcpu;
1962
1963 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1964 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1965 kvm_vcpu_kick(vcpu);
1966 }
1967}
1968
7e44e449
AJ		 1969static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1970{
1971 struct kvm *kvm = v->kvm;
1972
105b21bb 1973 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1974 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1975 KVMCLOCK_UPDATE_DELAY);
1976}
1977
332967a3
AJ		 1978#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1979
1980static void kvmclock_sync_fn(struct work_struct *work)
1981{
1982 struct delayed_work *dwork = to_delayed_work(work);
1983 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1984 kvmclock_sync_work);
1985 struct kvm *kvm = container_of(ka, struct kvm, arch);
1986
630994b3
MT		 1987 if (!kvmclock_periodic_sync)
1988 return;
1989
332967a3
AJ		 1990 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1991 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1992 KVMCLOCK_SYNC_PERIOD);
1993}
1994
890ca9ae 1995static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1996{
890ca9ae
HY		 1997 u64 mcg_cap = vcpu->arch.mcg_cap;
1998 unsigned bank_num = mcg_cap & 0xff;
1999
15c4a640 2000 switch (msr) {
15c4a640 2001 case MSR_IA32_MCG_STATUS:
890ca9ae 2002 vcpu->arch.mcg_status = data;
15c4a640 2003 break;
c7ac679c 2004 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2005 if (!(mcg_cap & MCG_CTL_P))
2006 return 1;
2007 if (data != 0 && data != ~(u64)0)
2008 return -1;
2009 vcpu->arch.mcg_ctl = data;
2010 break;
2011 default:
2012 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2013 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2014 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2015 /* only 0 or all 1s can be written to IA32_MCi_CTL
2016 * some Linux kernels though clear bit 10 in bank 4 to
2017 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2018 * this to avoid an uncatched #GP in the guest
2019 */
890ca9ae 2020 if ((offset & 0x3) == 0 &&
114be429 2021 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 2022 return -1;
2023 vcpu->arch.mce_banks[offset] = data;
2024 break;
2025 }
2026 return 1;
2027 }
2028 return 0;
2029}
2030
ffde22ac
ES		 2031static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2032{
2033 struct kvm *kvm = vcpu->kvm;
2034 int lm = is_long_mode(vcpu);
2035 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2036 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2037 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2038 : kvm->arch.xen_hvm_config.blob_size_32;
2039 u32 page_num = data & ~PAGE_MASK;
2040 u64 page_addr = data & PAGE_MASK;
2041 u8 *page;
2042 int r;
2043
2044 r = -E2BIG;
2045 if (page_num >= blob_size)
2046 goto out;
2047 r = -ENOMEM;
ff5c2c03
SL		 2048 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2049 if (IS_ERR(page)) {
2050 r = PTR_ERR(page);
ffde22ac 2051 goto out;
ff5c2c03 2052 }
54bf36aa 2053 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2054 goto out_free;
2055 r = 0;
2056out_free:
2057 kfree(page);
2058out:
2059 return r;
2060}
2061
344d9588
GN		 2062static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2063{
2064 gpa_t gpa = data & ~0x3f;
2065
52a5c155
WL		 2066 /* Bits 3:5 are reserved, Should be zero */
2067 if (data & 0x38)
344d9588
GN		 2068 return 1;
2069
2070 vcpu->arch.apf.msr_val = data;
2071
2072 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2073 kvm_clear_async_pf_completion_queue(vcpu);
2074 kvm_async_pf_hash_reset(vcpu);
2075 return 0;
2076 }
2077
4e335d9e 2078 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2079 sizeof(u32)))
344d9588
GN		 2080 return 1;
2081
6adba527 2082 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2083 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2084 kvm_async_pf_wakeup_all(vcpu);
2085 return 0;
2086}
2087
12f9a48f
GC		 2088static void kvmclock_reset(struct kvm_vcpu *vcpu)
2089{
0b79459b 2090 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2091}
2092
c9aaa895
GC		 2093static void record_steal_time(struct kvm_vcpu *vcpu)
2094{
2095 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2096 return;
2097
4e335d9e 2098 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2099 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2100 return;
2101
0b9f6c46
PX		 2102 vcpu->arch.st.steal.preempted = 0;
2103
35f3fae1
WL		 2104 if (vcpu->arch.st.steal.version & 1)
2105 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2106
2107 vcpu->arch.st.steal.version += 1;
2108
4e335d9e 2109 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2110 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2111
2112 smp_wmb();
2113
c54cdf14
LC		 2114 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2115 vcpu->arch.st.last_steal;
2116 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2117
4e335d9e 2118 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2119 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2120
2121 smp_wmb();
2122
2123 vcpu->arch.st.steal.version += 1;
c9aaa895 2124
4e335d9e 2125 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2126 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2127}
2128
8fe8ab46 2129int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2130{
5753785f 2131 bool pr = false;
8fe8ab46
WA		 2132 u32 msr = msr_info->index;
2133 u64 data = msr_info->data;
5753785f 2134
15c4a640 2135 switch (msr) {
2e32b719
BP		 2136 case MSR_AMD64_NB_CFG:
2137 case MSR_IA32_UCODE_REV:
2138 case MSR_IA32_UCODE_WRITE:
2139 case MSR_VM_HSAVE_PA:
2140 case MSR_AMD64_PATCH_LOADER:
2141 case MSR_AMD64_BU_CFG2:
405a353a 2142 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2143 break;
2144
15c4a640 2145 case MSR_EFER:
b69e8cae 2146 return set_efer(vcpu, data);
8f1589d9
AP		 2147 case MSR_K7_HWCR:
2148 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2149 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2150 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2151 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2152 if (data != 0) {
a737f256
CD		 2153 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2154 data);
8f1589d9
AP		 2155 return 1;
2156 }
15c4a640 2157 break;
f7c6d140
AP		 2158 case MSR_FAM10H_MMIO_CONF_BASE:
2159 if (data != 0) {
a737f256
CD		 2160 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2161 "0x%llx\n", data);
f7c6d140
AP		 2162 return 1;
2163 }
15c4a640 2164 break;
b5e2fec0
AG		 2165 case MSR_IA32_DEBUGCTLMSR:
2166 if (!data) {
2167 /* We support the non-activated case already */
2168 break;
2169 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2170 /* Values other than LBR and BTF are vendor-specific,
2171 thus reserved and should throw a #GP */
2172 return 1;
2173 }
a737f256
CD		 2174 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2175 __func__, data);
b5e2fec0 2176 break;
9ba075a6 2177 case 0x200 ... 0x2ff:
ff53604b 2178 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2179 case MSR_IA32_APICBASE:
58cb628d 2180 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2181 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2182 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2183 case MSR_IA32_TSCDEADLINE:
2184 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2185 break;
ba904635
WA		 2186 case MSR_IA32_TSC_ADJUST:
2187 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2188 if (!msr_info->host_initiated) {
d913b904 2189 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2190 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2191 }
2192 vcpu->arch.ia32_tsc_adjust_msr = data;
2193 }
2194 break;
15c4a640 2195 case MSR_IA32_MISC_ENABLE:
ad312c7c 2196 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2197 break;
64d60670
PB		 2198 case MSR_IA32_SMBASE:
2199 if (!msr_info->host_initiated)
2200 return 1;
2201 vcpu->arch.smbase = data;
2202 break;
11c6bffa 2203 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2204 case MSR_KVM_WALL_CLOCK:
2205 vcpu->kvm->arch.wall_clock = data;
2206 kvm_write_wall_clock(vcpu->kvm, data);
2207 break;
11c6bffa 2208 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2209 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2210 struct kvm_arch *ka = &vcpu->kvm->arch;
2211
12f9a48f 2212 kvmclock_reset(vcpu);
18068523 2213
54750f2c
MT		 2214 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2215 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2216
2217 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2218 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2219
2220 ka->boot_vcpu_runs_old_kvmclock = tmp;
2221 }
2222
18068523 2223 vcpu->arch.time = data;
0061d53d 2224 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2225
2226 /* we verify if the enable bit is set... */
2227 if (!(data & 1))
2228 break;
2229
4e335d9e 2230 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2231 &vcpu->arch.pv_time, data & ~1ULL,
2232 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2233 vcpu->arch.pv_time_enabled = false;
2234 else
2235 vcpu->arch.pv_time_enabled = true;
32cad84f 2236
18068523
GOC		 2237 break;
2238 }
344d9588
GN		 2239 case MSR_KVM_ASYNC_PF_EN:
2240 if (kvm_pv_enable_async_pf(vcpu, data))
2241 return 1;
2242 break;
c9aaa895
GC		 2243 case MSR_KVM_STEAL_TIME:
2244
2245 if (unlikely(!sched_info_on()))
2246 return 1;
2247
2248 if (data & KVM_STEAL_RESERVED_MASK)
2249 return 1;
2250
4e335d9e 2251 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2252 data & KVM_STEAL_VALID_BITS,
2253 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2254 return 1;
2255
2256 vcpu->arch.st.msr_val = data;
2257
2258 if (!(data & KVM_MSR_ENABLED))
2259 break;
2260
c9aaa895
GC		 2261 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2262
2263 break;
ae7a2a3f
MT		 2264 case MSR_KVM_PV_EOI_EN:
2265 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2266 return 1;
2267 break;
c9aaa895 2268
890ca9ae
HY		 2269 case MSR_IA32_MCG_CTL:
2270 case MSR_IA32_MCG_STATUS:
81760dcc 2271 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2272 return set_msr_mce(vcpu, msr, data);
71db6023 2273
6912ac32
WH		 2274 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2275 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2276 pr = true; /* fall through */
2277 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2278 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2279 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2280 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2281
2282 if (pr || data != 0)
a737f256
CD		 2283 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2284 "0x%x data 0x%llx\n", msr, data);
5753785f 2285 break;
84e0cefa
JS		 2286 case MSR_K7_CLK_CTL:
2287 /*
2288 * Ignore all writes to this no longer documented MSR.
2289 * Writes are only relevant for old K7 processors,
2290 * all pre-dating SVM, but a recommended workaround from
4a969980 2291 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2292 * affected processor models on the command line, hence
2293 * the need to ignore the workaround.
2294 */
2295 break;
55cd8e5a 2296 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2297 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2298 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2299 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2300 return kvm_hv_set_msr_common(vcpu, msr, data,
2301 msr_info->host_initiated);
91c9c3ed 2302 case MSR_IA32_BBL_CR_CTL3:
2303 /* Drop writes to this legacy MSR -- see rdmsr
2304 * counterpart for further detail.
2305 */
796f4687 2306 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", msr, data);
91c9c3ed 2307 break;
2b036c6b
BO		 2308 case MSR_AMD64_OSVW_ID_LENGTH:
2309 if (!guest_cpuid_has_osvw(vcpu))
2310 return 1;
2311 vcpu->arch.osvw.length = data;
2312 break;
2313 case MSR_AMD64_OSVW_STATUS:
2314 if (!guest_cpuid_has_osvw(vcpu))
2315 return 1;
2316 vcpu->arch.osvw.status = data;
2317 break;
db2336a8
KH		 2318 case MSR_PLATFORM_INFO:
2319 if (!msr_info->host_initiated ||
2320 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2321 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2322 cpuid_fault_enabled(vcpu)))
2323 return 1;
2324 vcpu->arch.msr_platform_info = data;
2325 break;
2326 case MSR_MISC_FEATURES_ENABLES:
2327 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2328 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2329 !supports_cpuid_fault(vcpu)))
2330 return 1;
2331 vcpu->arch.msr_misc_features_enables = data;
2332 break;
15c4a640 2333 default:
ffde22ac
ES		 2334 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2335 return xen_hvm_config(vcpu, data);
c6702c9d 2336 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2337 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2338 if (!ignore_msrs) {
ae0f5499 2339 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2340 msr, data);
ed85c068
AP		 2341 return 1;
2342 } else {
796f4687 2343 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
a737f256 2344 msr, data);
ed85c068
AP		 2345 break;
2346 }
15c4a640
CO		 2347 }
2348 return 0;
2349}
2350EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2351
2352
2353/*
2354 * Reads an msr value (of 'msr_index') into 'pdata'.
2355 * Returns 0 on success, non-0 otherwise.
2356 * Assumes vcpu_load() was already called.
2357 */
609e36d3 2358int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2359{
609e36d3 2360 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2361}
ff651cb6 2362EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2363
890ca9ae 2364static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2365{
2366 u64 data;
890ca9ae
HY		 2367 u64 mcg_cap = vcpu->arch.mcg_cap;
2368 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2369
2370 switch (msr) {
15c4a640
CO		 2371 case MSR_IA32_P5_MC_ADDR:
2372 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2373 data = 0;
2374 break;
15c4a640 2375 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2376 data = vcpu->arch.mcg_cap;
2377 break;
c7ac679c 2378 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2379 if (!(mcg_cap & MCG_CTL_P))
2380 return 1;
2381 data = vcpu->arch.mcg_ctl;
2382 break;
2383 case MSR_IA32_MCG_STATUS:
2384 data = vcpu->arch.mcg_status;
2385 break;
2386 default:
2387 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2388 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2389 u32 offset = msr - MSR_IA32_MC0_CTL;
2390 data = vcpu->arch.mce_banks[offset];
2391 break;
2392 }
2393 return 1;
2394 }
2395 *pdata = data;
2396 return 0;
2397}
2398
609e36d3 2399int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2400{
609e36d3 2401 switch (msr_info->index) {
890ca9ae 2402 case MSR_IA32_PLATFORM_ID:
15c4a640 2403 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2404 case MSR_IA32_DEBUGCTLMSR:
2405 case MSR_IA32_LASTBRANCHFROMIP:
2406 case MSR_IA32_LASTBRANCHTOIP:
2407 case MSR_IA32_LASTINTFROMIP:
2408 case MSR_IA32_LASTINTTOIP:
60af2ecd 2409 case MSR_K8_SYSCFG:
3afb1121
PB		 2410 case MSR_K8_TSEG_ADDR:
2411 case MSR_K8_TSEG_MASK:
60af2ecd 2412 case MSR_K7_HWCR:
61a6bd67 2413 case MSR_VM_HSAVE_PA:
1fdbd48c 2414 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2415 case MSR_AMD64_NB_CFG:
f7c6d140 2416 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2417 case MSR_AMD64_BU_CFG2:
0c2df2a1 2418 case MSR_IA32_PERF_CTL:
405a353a 2419 case MSR_AMD64_DC_CFG:
609e36d3 2420 msr_info->data = 0;
15c4a640 2421 break;
6912ac32
WH		 2422 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2423 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2424 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2425 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2426 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2427 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2428 msr_info->data = 0;
5753785f 2429 break;
742bc670 2430 case MSR_IA32_UCODE_REV:
609e36d3 2431 msr_info->data = 0x100000000ULL;
742bc670 2432 break;
9ba075a6 2433 case MSR_MTRRcap:
9ba075a6 2434 case 0x200 ... 0x2ff:
ff53604b 2435 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2436 case 0xcd: /* fsb frequency */
609e36d3 2437 msr_info->data = 3;
15c4a640 2438 break;
7b914098
JS		 2439 /*
2440 * MSR_EBC_FREQUENCY_ID
2441 * Conservative value valid for even the basic CPU models.
2442 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2443 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2444 * and 266MHz for model 3, or 4. Set Core Clock
2445 * Frequency to System Bus Frequency Ratio to 1 (bits
2446 * 31:24) even though these are only valid for CPU
2447 * models > 2, however guests may end up dividing or
2448 * multiplying by zero otherwise.
2449 */
2450 case MSR_EBC_FREQUENCY_ID:
609e36d3 2451 msr_info->data = 1 << 24;
7b914098 2452 break;
15c4a640 2453 case MSR_IA32_APICBASE:
609e36d3 2454 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2455 break;
0105d1a5 2456 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2457 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2458 break;
a3e06bbe 2459 case MSR_IA32_TSCDEADLINE:
609e36d3 2460 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2461 break;
ba904635 2462 case MSR_IA32_TSC_ADJUST:
609e36d3 2463 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2464 break;
15c4a640 2465 case MSR_IA32_MISC_ENABLE:
609e36d3 2466 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2467 break;
64d60670
PB		 2468 case MSR_IA32_SMBASE:
2469 if (!msr_info->host_initiated)
2470 return 1;
2471 msr_info->data = vcpu->arch.smbase;
15c4a640 2472 break;
847f0ad8
AG		 2473 case MSR_IA32_PERF_STATUS:
2474 /* TSC increment by tick */
609e36d3 2475 msr_info->data = 1000ULL;
847f0ad8 2476 /* CPU multiplier */
b0996ae4 2477 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2478 break;
15c4a640 2479 case MSR_EFER:
609e36d3 2480 msr_info->data = vcpu->arch.efer;
15c4a640 2481 break;
18068523 2482 case MSR_KVM_WALL_CLOCK:
11c6bffa 2483 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2484 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2485 break;
2486 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2487 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2488 msr_info->data = vcpu->arch.time;
18068523 2489 break;
344d9588 2490 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2491 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2492 break;
c9aaa895 2493 case MSR_KVM_STEAL_TIME:
609e36d3 2494 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2495 break;
1d92128f 2496 case MSR_KVM_PV_EOI_EN:
609e36d3 2497 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2498 break;
890ca9ae
HY		 2499 case MSR_IA32_P5_MC_ADDR:
2500 case MSR_IA32_P5_MC_TYPE:
2501 case MSR_IA32_MCG_CAP:
2502 case MSR_IA32_MCG_CTL:
2503 case MSR_IA32_MCG_STATUS:
81760dcc 2504 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2505 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2506 case MSR_K7_CLK_CTL:
2507 /*
2508 * Provide expected ramp-up count for K7. All other
2509 * are set to zero, indicating minimum divisors for
2510 * every field.
2511 *
2512 * This prevents guest kernels on AMD host with CPU
2513 * type 6, model 8 and higher from exploding due to
2514 * the rdmsr failing.
2515 */
609e36d3 2516 msr_info->data = 0x20000000;
84e0cefa 2517 break;
55cd8e5a 2518 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2519 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2520 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2521 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2522 return kvm_hv_get_msr_common(vcpu,
2523 msr_info->index, &msr_info->data);
55cd8e5a 2524 break;
91c9c3ed 2525 case MSR_IA32_BBL_CR_CTL3:
2526 /* This legacy MSR exists but isn't fully documented in current
2527 * silicon. It is however accessed by winxp in very narrow
2528 * scenarios where it sets bit #19, itself documented as
2529 * a "reserved" bit. Best effort attempt to source coherent
2530 * read data here should the balance of the register be
2531 * interpreted by the guest:
2532 *
2533 * L2 cache control register 3: 64GB range, 256KB size,
2534 * enabled, latency 0x1, configured
2535 */
609e36d3 2536 msr_info->data = 0xbe702111;
91c9c3ed 2537 break;
2b036c6b
BO		 2538 case MSR_AMD64_OSVW_ID_LENGTH:
2539 if (!guest_cpuid_has_osvw(vcpu))
2540 return 1;
609e36d3 2541 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2542 break;
2543 case MSR_AMD64_OSVW_STATUS:
2544 if (!guest_cpuid_has_osvw(vcpu))
2545 return 1;
609e36d3 2546 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2547 break;
db2336a8
KH		 2548 case MSR_PLATFORM_INFO:
2549 msr_info->data = vcpu->arch.msr_platform_info;
2550 break;
2551 case MSR_MISC_FEATURES_ENABLES:
2552 msr_info->data = vcpu->arch.msr_misc_features_enables;
2553 break;
15c4a640 2554 default:
c6702c9d 2555 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2556 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2557 if (!ignore_msrs) {
ae0f5499
BD		 2558 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2559 msr_info->index);
ed85c068
AP		 2560 return 1;
2561 } else {
609e36d3
PB		 2562 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2563 msr_info->data = 0;
ed85c068
AP		 2564 }
2565 break;
15c4a640 2566 }
15c4a640
CO		 2567 return 0;
2568}
2569EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2570
313a3dc7
CO		 2571/*
2572 * Read or write a bunch of msrs. All parameters are kernel addresses.
2573 *
2574 * @return number of msrs set successfully.
2575 */
2576static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2577 struct kvm_msr_entry *entries,
2578 int (*do_msr)(struct kvm_vcpu *vcpu,
2579 unsigned index, u64 *data))
2580{
f656ce01 2581 int i, idx;
313a3dc7 2582
f656ce01 2583 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2584 for (i = 0; i < msrs->nmsrs; ++i)
2585 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2586 break;
f656ce01 2587 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2588
313a3dc7
CO		 2589 return i;
2590}
2591
2592/*
2593 * Read or write a bunch of msrs. Parameters are user addresses.
2594 *
2595 * @return number of msrs set successfully.
2596 */
2597static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2598 int (*do_msr)(struct kvm_vcpu *vcpu,
2599 unsigned index, u64 *data),
2600 int writeback)
2601{
2602 struct kvm_msrs msrs;
2603 struct kvm_msr_entry *entries;
2604 int r, n;
2605 unsigned size;
2606
2607 r = -EFAULT;
2608 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2609 goto out;
2610
2611 r = -E2BIG;
2612 if (msrs.nmsrs >= MAX_IO_MSRS)
2613 goto out;
2614
313a3dc7 2615 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2616 entries = memdup_user(user_msrs->entries, size);
2617 if (IS_ERR(entries)) {
2618 r = PTR_ERR(entries);
313a3dc7 2619 goto out;
ff5c2c03 2620 }
313a3dc7
CO		 2621
2622 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2623 if (r < 0)
2624 goto out_free;
2625
2626 r = -EFAULT;
2627 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2628 goto out_free;
2629
2630 r = n;
2631
2632out_free:
7a73c028 2633 kfree(entries);
313a3dc7
CO		 2634out:
2635 return r;
2636}
2637
784aa3d7 2638int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2639{
2640 int r;
2641
2642 switch (ext) {
2643 case KVM_CAP_IRQCHIP:
2644 case KVM_CAP_HLT:
2645 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2646 case KVM_CAP_SET_TSS_ADDR:
07716717 2647 case KVM_CAP_EXT_CPUID:
9c15bb1d 2648 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2649 case KVM_CAP_CLOCKSOURCE:
7837699f 2650 case KVM_CAP_PIT:
a28e4f5a 2651 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2652 case KVM_CAP_MP_STATE:
ed848624 2653 case KVM_CAP_SYNC_MMU:
a355c85c 2654 case KVM_CAP_USER_NMI:
52d939a0 2655 case KVM_CAP_REINJECT_CONTROL:
4925663a 2656 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2657 case KVM_CAP_IOEVENTFD:
f848a5a8 2658 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2659 case KVM_CAP_PIT2:
e9f42757 2660 case KVM_CAP_PIT_STATE2:
b927a3ce 2661 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2662 case KVM_CAP_XEN_HVM:
3cfc3092 2663 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2664 case KVM_CAP_HYPERV:
10388a07 2665 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2666 case KVM_CAP_HYPERV_SPIN:
5c919412 2667 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2668 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2669 case KVM_CAP_HYPERV_VP_INDEX:
ab9f4ecb 2670 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2671 case KVM_CAP_DEBUGREGS:
d2be1651 2672 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2673 case KVM_CAP_XSAVE:
344d9588 2674 case KVM_CAP_ASYNC_PF:
92a1f12d 2675 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2676 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2677 case KVM_CAP_READONLY_MEM:
5f66b620 2678 case KVM_CAP_HYPERV_TIME:
100943c5 2679 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2680 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2681 case KVM_CAP_ENABLE_CAP_VM:
2682 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2683 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2684 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2685 case KVM_CAP_IMMEDIATE_EXIT:
018d00d2
ZX		 2686 r = 1;
2687 break;
e3fd9a93
PB		 2688 case KVM_CAP_ADJUST_CLOCK:
2689 r = KVM_CLOCK_TSC_STABLE;
2690 break;
668fffa3
MT		 2691 case KVM_CAP_X86_GUEST_MWAIT:
2692 r = kvm_mwait_in_guest();
2693 break;
6d396b55
PB		 2694 case KVM_CAP_X86_SMM:
2695 /* SMBASE is usually relocated above 1M on modern chipsets,
2696 * and SMM handlers might indeed rely on 4G segment limits,
2697 * so do not report SMM to be available if real mode is
2698 * emulated via vm86 mode. Still, do not go to great lengths
2699 * to avoid userspace's usage of the feature, because it is a
2700 * fringe case that is not enabled except via specific settings
2701 * of the module parameters.
2702 */
2703 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2704 break;
774ead3a
AK		 2705 case KVM_CAP_VAPIC:
2706 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2707 break;
f725230a 2708 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2709 r = KVM_SOFT_MAX_VCPUS;
2710 break;
2711 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2712 r = KVM_MAX_VCPUS;
2713 break;
a988b910 2714 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2715 r = KVM_USER_MEM_SLOTS;
a988b910 2716 break;
a68a6a72
MT		 2717 case KVM_CAP_PV_MMU: /* obsolete */
2718 r = 0;
2f333bcb 2719 break;
890ca9ae
HY		 2720 case KVM_CAP_MCE:
2721 r = KVM_MAX_MCE_BANKS;
2722 break;
2d5b5a66 2723 case KVM_CAP_XCRS:
d366bf7e 2724 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2725 break;
92a1f12d
JR		 2726 case KVM_CAP_TSC_CONTROL:
2727 r = kvm_has_tsc_control;
2728 break;
37131313
RK		 2729 case KVM_CAP_X2APIC_API:
2730 r = KVM_X2APIC_API_VALID_FLAGS;
2731 break;
018d00d2
ZX		 2732 default:
2733 r = 0;
2734 break;
2735 }
2736 return r;
2737
2738}
2739
043405e1
CO		 2740long kvm_arch_dev_ioctl(struct file *filp,
2741 unsigned int ioctl, unsigned long arg)
2742{
2743 void __user *argp = (void __user *)arg;
2744 long r;
2745
2746 switch (ioctl) {
2747 case KVM_GET_MSR_INDEX_LIST: {
2748 struct kvm_msr_list __user *user_msr_list = argp;
2749 struct kvm_msr_list msr_list;
2750 unsigned n;
2751
2752 r = -EFAULT;
2753 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2754 goto out;
2755 n = msr_list.nmsrs;
62ef68bb 2756 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2757 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2758 goto out;
2759 r = -E2BIG;
e125e7b6 2760 if (n < msr_list.nmsrs)
043405e1
CO		 2761 goto out;
2762 r = -EFAULT;
2763 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2764 num_msrs_to_save * sizeof(u32)))
2765 goto out;
e125e7b6 2766 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2767 &emulated_msrs,
62ef68bb 2768 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2769 goto out;
2770 r = 0;
2771 break;
2772 }
9c15bb1d
BP		 2773 case KVM_GET_SUPPORTED_CPUID:
2774 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2775 struct kvm_cpuid2 __user *cpuid_arg = argp;
2776 struct kvm_cpuid2 cpuid;
2777
2778 r = -EFAULT;
2779 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2780 goto out;
9c15bb1d
BP		 2781
2782 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2783 ioctl);
674eea0f
AK		 2784 if (r)
2785 goto out;
2786
2787 r = -EFAULT;
2788 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2789 goto out;
2790 r = 0;
2791 break;
2792 }
890ca9ae 2793 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2794 r = -EFAULT;
c45dcc71
AR		 2795 if (copy_to_user(argp, &kvm_mce_cap_supported,
2796 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2797 goto out;
2798 r = 0;
2799 break;
2800 }
043405e1
CO		 2801 default:
2802 r = -EINVAL;
2803 }
2804out:
2805 return r;
2806}
2807
f5f48ee1
SY		 2808static void wbinvd_ipi(void *garbage)
2809{
2810 wbinvd();
2811}
2812
2813static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2814{
e0f0bbc5 2815 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2816}
2817
313a3dc7
CO		 2818void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2819{
f5f48ee1
SY		 2820 /* Address WBINVD may be executed by guest */
2821 if (need_emulate_wbinvd(vcpu)) {
2822 if (kvm_x86_ops->has_wbinvd_exit())
2823 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2824 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2825 smp_call_function_single(vcpu->cpu,
2826 wbinvd_ipi, NULL, 1);
2827 }
2828
313a3dc7 2829 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2830
0dd6a6ed
ZA		 2831 /* Apply any externally detected TSC adjustments (due to suspend) */
2832 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2833 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2834 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2835 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2836 }
8f6055cb 2837
48434c20 2838 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2839 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2840 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2841 if (tsc_delta < 0)
2842 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2843
c285545f 2844 if (check_tsc_unstable()) {
07c1419a 2845 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2846 vcpu->arch.last_guest_tsc);
a545ab6a 2847 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2848 vcpu->arch.tsc_catchup = 1;
c285545f 2849 }
a749e247
PB		 2850
2851 if (kvm_lapic_hv_timer_in_use(vcpu))
2852 kvm_lapic_restart_hv_timer(vcpu);
2853
d98d07ca
MT		 2854 /*
2855 * On a host with synchronized TSC, there is no need to update
2856 * kvmclock on vcpu->cpu migration
2857 */
2858 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2859 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 2860 if (vcpu->cpu != cpu)
1bd2009e 2861 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 2862 vcpu->cpu = cpu;
6b7d7e76 2863 }
c9aaa895 2864
c9aaa895 2865 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2866}
2867
0b9f6c46
PX		 2868static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2869{
2870 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2871 return;
2872
2873 vcpu->arch.st.steal.preempted = 1;
2874
4e335d9e 2875 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 2876 &vcpu->arch.st.steal.preempted,
2877 offsetof(struct kvm_steal_time, preempted),
2878 sizeof(vcpu->arch.st.steal.preempted));
2879}
2880
313a3dc7
CO		 2881void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2882{
cc0d907c 2883 int idx;
931f261b
AA		 2884 /*
2885 * Disable page faults because we're in atomic context here.
2886 * kvm_write_guest_offset_cached() would call might_fault()
2887 * that relies on pagefault_disable() to tell if there's a
2888 * bug. NOTE: the write to guest memory may not go through if
2889 * during postcopy live migration or if there's heavy guest
2890 * paging.
2891 */
2892 pagefault_disable();
cc0d907c
AA		 2893 /*
2894 * kvm_memslots() will be called by
2895 * kvm_write_guest_offset_cached() so take the srcu lock.
2896 */
2897 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 2898 kvm_steal_time_set_preempted(vcpu);
cc0d907c 2899 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 2900 pagefault_enable();
02daab21 2901 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2902 kvm_put_guest_fpu(vcpu);
4ea1636b 2903 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2904}
2905
313a3dc7
CO		 2906static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2907 struct kvm_lapic_state *s)
2908{
76dfafd5 2909 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb
AS		 2910 kvm_x86_ops->sync_pir_to_irr(vcpu);
2911
a92e2543 2912 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 2913}
2914
2915static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2916 struct kvm_lapic_state *s)
2917{
a92e2543
RK		 2918 int r;
2919
2920 r = kvm_apic_set_state(vcpu, s);
2921 if (r)
2922 return r;
cb142eb7 2923 update_cr8_intercept(vcpu);
313a3dc7
CO		 2924
2925 return 0;
2926}
2927
127a457a
MG		 2928static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2929{
2930 return (!lapic_in_kernel(vcpu) ||
2931 kvm_apic_accept_pic_intr(vcpu));
2932}
2933
782d422b
MG		 2934/*
2935 * if userspace requested an interrupt window, check that the
2936 * interrupt window is open.
2937 *
2938 * No need to exit to userspace if we already have an interrupt queued.
2939 */
2940static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2941{
2942 return kvm_arch_interrupt_allowed(vcpu) &&
2943 !kvm_cpu_has_interrupt(vcpu) &&
2944 !kvm_event_needs_reinjection(vcpu) &&
2945 kvm_cpu_accept_dm_intr(vcpu);
2946}
2947
f77bc6a4
ZX		 2948static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2949 struct kvm_interrupt *irq)
2950{
02cdb50f 2951 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2952 return -EINVAL;
1c1a9ce9
SR		 2953
2954 if (!irqchip_in_kernel(vcpu->kvm)) {
2955 kvm_queue_interrupt(vcpu, irq->irq, false);
2956 kvm_make_request(KVM_REQ_EVENT, vcpu);
2957 return 0;
2958 }
2959
2960 /*
2961 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2962 * fail for in-kernel 8259.
2963 */
2964 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2965 return -ENXIO;
f77bc6a4 2966
1c1a9ce9
SR		 2967 if (vcpu->arch.pending_external_vector != -1)
2968 return -EEXIST;
f77bc6a4 2969
1c1a9ce9 2970 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2971 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2972 return 0;
2973}
2974
c4abb7c9
JK		 2975static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2976{
c4abb7c9 2977 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2978
2979 return 0;
2980}
2981
f077825a
PB		 2982static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2983{
64d60670
PB		 2984 kvm_make_request(KVM_REQ_SMI, vcpu);
2985
f077825a
PB		 2986 return 0;
2987}
2988
b209749f
AK		 2989static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2990 struct kvm_tpr_access_ctl *tac)
2991{
2992 if (tac->flags)
2993 return -EINVAL;
2994 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2995 return 0;
2996}
2997
890ca9ae
HY		 2998static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2999 u64 mcg_cap)
3000{
3001 int r;
3002 unsigned bank_num = mcg_cap & 0xff, bank;
3003
3004 r = -EINVAL;
a9e38c3e 3005 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3006 goto out;
c45dcc71 3007 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3008 goto out;
3009 r = 0;
3010 vcpu->arch.mcg_cap = mcg_cap;
3011 /* Init IA32_MCG_CTL to all 1s */
3012 if (mcg_cap & MCG_CTL_P)
3013 vcpu->arch.mcg_ctl = ~(u64)0;
3014 /* Init IA32_MCi_CTL to all 1s */
3015 for (bank = 0; bank < bank_num; bank++)
3016 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3017
3018 if (kvm_x86_ops->setup_mce)
3019 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3020out:
3021 return r;
3022}
3023
3024static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3025 struct kvm_x86_mce *mce)
3026{
3027 u64 mcg_cap = vcpu->arch.mcg_cap;
3028 unsigned bank_num = mcg_cap & 0xff;
3029 u64 *banks = vcpu->arch.mce_banks;
3030
3031 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3032 return -EINVAL;
3033 /*
3034 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3035 * reporting is disabled
3036 */
3037 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3038 vcpu->arch.mcg_ctl != ~(u64)0)
3039 return 0;
3040 banks += 4 * mce->bank;
3041 /*
3042 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3043 * reporting is disabled for the bank
3044 */
3045 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3046 return 0;
3047 if (mce->status & MCI_STATUS_UC) {
3048 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3049 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3050 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3051 return 0;
3052 }
3053 if (banks[1] & MCI_STATUS_VAL)
3054 mce->status |= MCI_STATUS_OVER;
3055 banks[2] = mce->addr;
3056 banks[3] = mce->misc;
3057 vcpu->arch.mcg_status = mce->mcg_status;
3058 banks[1] = mce->status;
3059 kvm_queue_exception(vcpu, MC_VECTOR);
3060 } else if (!(banks[1] & MCI_STATUS_VAL)
3061 || !(banks[1] & MCI_STATUS_UC)) {
3062 if (banks[1] & MCI_STATUS_VAL)
3063 mce->status |= MCI_STATUS_OVER;
3064 banks[2] = mce->addr;
3065 banks[3] = mce->misc;
3066 banks[1] = mce->status;
3067 } else
3068 banks[1] |= MCI_STATUS_OVER;
3069 return 0;
3070}
3071
3cfc3092
JK		 3072static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3073 struct kvm_vcpu_events *events)
3074{
7460fb4a 3075 process_nmi(vcpu);
03b82a30
JK		 3076 events->exception.injected =
3077 vcpu->arch.exception.pending &&
3078 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3079 events->exception.nr = vcpu->arch.exception.nr;
3080 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3081 events->exception.pad = 0;
3cfc3092
JK		 3082 events->exception.error_code = vcpu->arch.exception.error_code;
3083
03b82a30
JK		 3084 events->interrupt.injected =
3085 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3086 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3087 events->interrupt.soft = 0;
37ccdcbe 3088 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3089
3090 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3091 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3092 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3093 events->nmi.pad = 0;
3cfc3092 3094
66450a21 3095 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3096
f077825a
PB		 3097 events->smi.smm = is_smm(vcpu);
3098 events->smi.pending = vcpu->arch.smi_pending;
3099 events->smi.smm_inside_nmi =
3100 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3101 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3102
dab4b911 3103 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3104 | KVM_VCPUEVENT_VALID_SHADOW
3105 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3106 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3107}
3108
6ef4e07e
XG		 3109static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3110
3cfc3092
JK		 3111static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3112 struct kvm_vcpu_events *events)
3113{
dab4b911 3114 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3115 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3116 | KVM_VCPUEVENT_VALID_SHADOW
3117 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3118 return -EINVAL;
3119
78e546c8 3120 if (events->exception.injected &&
28d06353
JM		 3121 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3122 is_guest_mode(vcpu)))
78e546c8
PB		 3123 return -EINVAL;
3124
28bf2888
DH		 3125 /* INITs are latched while in SMM */
3126 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3127 (events->smi.smm || events->smi.pending) &&
3128 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3129 return -EINVAL;
3130
7460fb4a 3131 process_nmi(vcpu);
3cfc3092
JK		 3132 vcpu->arch.exception.pending = events->exception.injected;
3133 vcpu->arch.exception.nr = events->exception.nr;
3134 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3135 vcpu->arch.exception.error_code = events->exception.error_code;
3136
3137 vcpu->arch.interrupt.pending = events->interrupt.injected;
3138 vcpu->arch.interrupt.nr = events->interrupt.nr;
3139 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3140 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3141 kvm_x86_ops->set_interrupt_shadow(vcpu,
3142 events->interrupt.shadow);
3cfc3092
JK		 3143
3144 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3145 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3146 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3147 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3148
66450a21 3149 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3150 lapic_in_kernel(vcpu))
66450a21 3151 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3152
f077825a 3153 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3154 u32 hflags = vcpu->arch.hflags;
f077825a 3155 if (events->smi.smm)
6ef4e07e 3156 hflags |= HF_SMM_MASK;
f077825a 3157 else
6ef4e07e
XG		 3158 hflags &= ~HF_SMM_MASK;
3159 kvm_set_hflags(vcpu, hflags);
3160
f077825a 3161 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3162
3163 if (events->smi.smm) {
3164 if (events->smi.smm_inside_nmi)
3165 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3166 else
f4ef1910
WL		 3167 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3168 if (lapic_in_kernel(vcpu)) {
3169 if (events->smi.latched_init)
3170 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3171 else
3172 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3173 }
f077825a
PB		 3174 }
3175 }
3176
3842d135
AK		 3177 kvm_make_request(KVM_REQ_EVENT, vcpu);
3178
3cfc3092
JK		 3179 return 0;
3180}
3181
a1efbe77
JK		 3182static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3183 struct kvm_debugregs *dbgregs)
3184{
73aaf249
JK		 3185 unsigned long val;
3186
a1efbe77 3187 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3188 kvm_get_dr(vcpu, 6, &val);
73aaf249 3189 dbgregs->dr6 = val;
a1efbe77
JK		 3190 dbgregs->dr7 = vcpu->arch.dr7;
3191 dbgregs->flags = 0;
97e69aa6 3192 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3193}
3194
3195static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3196 struct kvm_debugregs *dbgregs)
3197{
3198 if (dbgregs->flags)
3199 return -EINVAL;
3200
d14bdb55
PB		 3201 if (dbgregs->dr6 & ~0xffffffffull)
3202 return -EINVAL;
3203 if (dbgregs->dr7 & ~0xffffffffull)
3204 return -EINVAL;
3205
a1efbe77 3206 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3207 kvm_update_dr0123(vcpu);
a1efbe77 3208 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3209 kvm_update_dr6(vcpu);
a1efbe77 3210 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3211 kvm_update_dr7(vcpu);
a1efbe77 3212
a1efbe77
JK		 3213 return 0;
3214}
3215
df1daba7
PB		 3216#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3217
3218static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3219{
c47ada30 3220 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3221 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3222 u64 valid;
3223
3224 /*
3225 * Copy legacy XSAVE area, to avoid complications with CPUID
3226 * leaves 0 and 1 in the loop below.
3227 */
3228 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3229
3230 /* Set XSTATE_BV */
00c87e9a 3231 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3232 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3233
3234 /*
3235 * Copy each region from the possibly compacted offset to the
3236 * non-compacted offset.
3237 */
d91cab78 3238 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3239 while (valid) {
3240 u64 feature = valid & -valid;
3241 int index = fls64(feature) - 1;
3242 void *src = get_xsave_addr(xsave, feature);
3243
3244 if (src) {
3245 u32 size, offset, ecx, edx;
3246 cpuid_count(XSTATE_CPUID, index,
3247 &size, &offset, &ecx, &edx);
3248 memcpy(dest + offset, src, size);
3249 }
3250
3251 valid -= feature;
3252 }
3253}
3254
3255static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3256{
c47ada30 3257 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3258 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3259 u64 valid;
3260
3261 /*
3262 * Copy legacy XSAVE area, to avoid complications with CPUID
3263 * leaves 0 and 1 in the loop below.
3264 */
3265 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3266
3267 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3268 xsave->header.xfeatures = xstate_bv;
782511b0 3269 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3270 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3271
3272 /*
3273 * Copy each region from the non-compacted offset to the
3274 * possibly compacted offset.
3275 */
d91cab78 3276 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3277 while (valid) {
3278 u64 feature = valid & -valid;
3279 int index = fls64(feature) - 1;
3280 void *dest = get_xsave_addr(xsave, feature);
3281
3282 if (dest) {
3283 u32 size, offset, ecx, edx;
3284 cpuid_count(XSTATE_CPUID, index,
3285 &size, &offset, &ecx, &edx);
3286 memcpy(dest, src + offset, size);
ee4100da 3287 }
df1daba7
PB		 3288
3289 valid -= feature;
3290 }
3291}
3292
2d5b5a66
SY		 3293static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3294 struct kvm_xsave *guest_xsave)
3295{
d366bf7e 3296 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3297 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3298 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3299 } else {
2d5b5a66 3300 memcpy(guest_xsave->region,
7366ed77 3301 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3302 sizeof(struct fxregs_state));
2d5b5a66 3303 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3304 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3305 }
3306}
3307
a575813b
WL		 3308#define XSAVE_MXCSR_OFFSET 24
3309
2d5b5a66
SY		 3310static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3311 struct kvm_xsave *guest_xsave)
3312{
3313 u64 xstate_bv =
3314 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3315 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3316
d366bf7e 3317 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3318 /*
3319 * Here we allow setting states that are not present in
3320 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3321 * with old userspace.
3322 */
a575813b
WL		 3323 if (xstate_bv & ~kvm_supported_xcr0() ||
3324 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3325 return -EINVAL;
df1daba7 3326 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3327 } else {
a575813b
WL		 3328 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3329 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3330 return -EINVAL;
7366ed77 3331 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3332 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3333 }
3334 return 0;
3335}
3336
3337static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3338 struct kvm_xcrs *guest_xcrs)
3339{
d366bf7e 3340 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3341 guest_xcrs->nr_xcrs = 0;
3342 return;
3343 }
3344
3345 guest_xcrs->nr_xcrs = 1;
3346 guest_xcrs->flags = 0;
3347 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3348 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3349}
3350
3351static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3352 struct kvm_xcrs *guest_xcrs)
3353{
3354 int i, r = 0;
3355
d366bf7e 3356 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3357 return -EINVAL;
3358
3359 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3360 return -EINVAL;
3361
3362 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3363 /* Only support XCR0 currently */
c67a04cb 3364 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3365 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3366 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3367 break;
3368 }
3369 if (r)
3370 r = -EINVAL;
3371 return r;
3372}
3373
1c0b28c2
EM		 3374/*
3375 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3376 * stopped by the hypervisor. This function will be called from the host only.
3377 * EINVAL is returned when the host attempts to set the flag for a guest that
3378 * does not support pv clocks.
3379 */
3380static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3381{
0b79459b 3382 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3383 return -EINVAL;
51d59c6b 3384 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3385 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3386 return 0;
3387}
3388
5c919412
AS		 3389static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3390 struct kvm_enable_cap *cap)
3391{
3392 if (cap->flags)
3393 return -EINVAL;
3394
3395 switch (cap->cap) {
efc479e6
RK		 3396 case KVM_CAP_HYPERV_SYNIC2:
3397 if (cap->args[0])
3398 return -EINVAL;
5c919412 3399 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3400 if (!irqchip_in_kernel(vcpu->kvm))
3401 return -EINVAL;
efc479e6
RK		 3402 return kvm_hv_activate_synic(vcpu, cap->cap ==
3403 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3404 default:
3405 return -EINVAL;
3406 }
3407}
3408
313a3dc7
CO		 3409long kvm_arch_vcpu_ioctl(struct file *filp,
3410 unsigned int ioctl, unsigned long arg)
3411{
3412 struct kvm_vcpu *vcpu = filp->private_data;
3413 void __user *argp = (void __user *)arg;
3414 int r;
d1ac91d8
AK		 3415 union {
3416 struct kvm_lapic_state *lapic;
3417 struct kvm_xsave *xsave;
3418 struct kvm_xcrs *xcrs;
3419 void *buffer;
3420 } u;
3421
3422 u.buffer = NULL;
313a3dc7
CO		 3423 switch (ioctl) {
3424 case KVM_GET_LAPIC: {
2204ae3c 3425 r = -EINVAL;
bce87cce 3426 if (!lapic_in_kernel(vcpu))
2204ae3c 3427 goto out;
d1ac91d8 3428 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3429
b772ff36 3430 r = -ENOMEM;
d1ac91d8 3431 if (!u.lapic)
b772ff36 3432 goto out;
d1ac91d8 3433 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3434 if (r)
3435 goto out;
3436 r = -EFAULT;
d1ac91d8 3437 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3438 goto out;
3439 r = 0;
3440 break;
3441 }
3442 case KVM_SET_LAPIC: {
2204ae3c 3443 r = -EINVAL;
bce87cce 3444 if (!lapic_in_kernel(vcpu))
2204ae3c 3445 goto out;
ff5c2c03 3446 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3447 if (IS_ERR(u.lapic))
3448 return PTR_ERR(u.lapic);
ff5c2c03 3449
d1ac91d8 3450 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3451 break;
3452 }
f77bc6a4
ZX		 3453 case KVM_INTERRUPT: {
3454 struct kvm_interrupt irq;
3455
3456 r = -EFAULT;
3457 if (copy_from_user(&irq, argp, sizeof irq))
3458 goto out;
3459 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3460 break;
3461 }
c4abb7c9
JK		 3462 case KVM_NMI: {
3463 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3464 break;
3465 }
f077825a
PB		 3466 case KVM_SMI: {
3467 r = kvm_vcpu_ioctl_smi(vcpu);
3468 break;
3469 }
313a3dc7
CO		 3470 case KVM_SET_CPUID: {
3471 struct kvm_cpuid __user *cpuid_arg = argp;
3472 struct kvm_cpuid cpuid;
3473
3474 r = -EFAULT;
3475 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3476 goto out;
3477 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3478 break;
3479 }
07716717
DK		 3480 case KVM_SET_CPUID2: {
3481 struct kvm_cpuid2 __user *cpuid_arg = argp;
3482 struct kvm_cpuid2 cpuid;
3483
3484 r = -EFAULT;
3485 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3486 goto out;
3487 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3488 cpuid_arg->entries);
07716717
DK		 3489 break;
3490 }
3491 case KVM_GET_CPUID2: {
3492 struct kvm_cpuid2 __user *cpuid_arg = argp;
3493 struct kvm_cpuid2 cpuid;
3494
3495 r = -EFAULT;
3496 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3497 goto out;
3498 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3499 cpuid_arg->entries);
07716717
DK		 3500 if (r)
3501 goto out;
3502 r = -EFAULT;
3503 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3504 goto out;
3505 r = 0;
3506 break;
3507 }
313a3dc7 3508 case KVM_GET_MSRS:
609e36d3 3509 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3510 break;
3511 case KVM_SET_MSRS:
3512 r = msr_io(vcpu, argp, do_set_msr, 0);
3513 break;
b209749f
AK		 3514 case KVM_TPR_ACCESS_REPORTING: {
3515 struct kvm_tpr_access_ctl tac;
3516
3517 r = -EFAULT;
3518 if (copy_from_user(&tac, argp, sizeof tac))
3519 goto out;
3520 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3521 if (r)
3522 goto out;
3523 r = -EFAULT;
3524 if (copy_to_user(argp, &tac, sizeof tac))
3525 goto out;
3526 r = 0;
3527 break;
3528 };
b93463aa
AK		 3529 case KVM_SET_VAPIC_ADDR: {
3530 struct kvm_vapic_addr va;
7301d6ab 3531 int idx;
b93463aa
AK		 3532
3533 r = -EINVAL;
35754c98 3534 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3535 goto out;
3536 r = -EFAULT;
3537 if (copy_from_user(&va, argp, sizeof va))
3538 goto out;
7301d6ab 3539 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3540 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3541 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3542 break;
3543 }
890ca9ae
HY		 3544 case KVM_X86_SETUP_MCE: {
3545 u64 mcg_cap;
3546
3547 r = -EFAULT;
3548 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3549 goto out;
3550 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3551 break;
3552 }
3553 case KVM_X86_SET_MCE: {
3554 struct kvm_x86_mce mce;
3555
3556 r = -EFAULT;
3557 if (copy_from_user(&mce, argp, sizeof mce))
3558 goto out;
3559 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3560 break;
3561 }
3cfc3092
JK		 3562 case KVM_GET_VCPU_EVENTS: {
3563 struct kvm_vcpu_events events;
3564
3565 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3566
3567 r = -EFAULT;
3568 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3569 break;
3570 r = 0;
3571 break;
3572 }
3573 case KVM_SET_VCPU_EVENTS: {
3574 struct kvm_vcpu_events events;
3575
3576 r = -EFAULT;
3577 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3578 break;
3579
3580 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3581 break;
3582 }
a1efbe77
JK		 3583 case KVM_GET_DEBUGREGS: {
3584 struct kvm_debugregs dbgregs;
3585
3586 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3587
3588 r = -EFAULT;
3589 if (copy_to_user(argp, &dbgregs,
3590 sizeof(struct kvm_debugregs)))
3591 break;
3592 r = 0;
3593 break;
3594 }
3595 case KVM_SET_DEBUGREGS: {
3596 struct kvm_debugregs dbgregs;
3597
3598 r = -EFAULT;
3599 if (copy_from_user(&dbgregs, argp,
3600 sizeof(struct kvm_debugregs)))
3601 break;
3602
3603 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3604 break;
3605 }
2d5b5a66 3606 case KVM_GET_XSAVE: {
d1ac91d8 3607 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3608 r = -ENOMEM;
d1ac91d8 3609 if (!u.xsave)
2d5b5a66
SY		 3610 break;
3611
d1ac91d8 3612 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3613
3614 r = -EFAULT;
d1ac91d8 3615 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3616 break;
3617 r = 0;
3618 break;
3619 }
3620 case KVM_SET_XSAVE: {
ff5c2c03 3621 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3622 if (IS_ERR(u.xsave))
3623 return PTR_ERR(u.xsave);
2d5b5a66 3624
d1ac91d8 3625 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3626 break;
3627 }
3628 case KVM_GET_XCRS: {
d1ac91d8 3629 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3630 r = -ENOMEM;
d1ac91d8 3631 if (!u.xcrs)
2d5b5a66
SY		 3632 break;
3633
d1ac91d8 3634 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3635
3636 r = -EFAULT;
d1ac91d8 3637 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3638 sizeof(struct kvm_xcrs)))
3639 break;
3640 r = 0;
3641 break;
3642 }
3643 case KVM_SET_XCRS: {
ff5c2c03 3644 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3645 if (IS_ERR(u.xcrs))
3646 return PTR_ERR(u.xcrs);
2d5b5a66 3647
d1ac91d8 3648 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3649 break;
3650 }
92a1f12d
JR		 3651 case KVM_SET_TSC_KHZ: {
3652 u32 user_tsc_khz;
3653
3654 r = -EINVAL;
92a1f12d
JR		 3655 user_tsc_khz = (u32)arg;
3656
3657 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3658 goto out;
3659
cc578287
ZA		 3660 if (user_tsc_khz == 0)
3661 user_tsc_khz = tsc_khz;
3662
381d585c
HZ		 3663 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3664 r = 0;
92a1f12d 3665
92a1f12d
JR		 3666 goto out;
3667 }
3668 case KVM_GET_TSC_KHZ: {
cc578287 3669 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3670 goto out;
3671 }
1c0b28c2
EM		 3672 case KVM_KVMCLOCK_CTRL: {
3673 r = kvm_set_guest_paused(vcpu);
3674 goto out;
3675 }
5c919412
AS		 3676 case KVM_ENABLE_CAP: {
3677 struct kvm_enable_cap cap;
3678
3679 r = -EFAULT;
3680 if (copy_from_user(&cap, argp, sizeof(cap)))
3681 goto out;
3682 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3683 break;
3684 }
313a3dc7
CO		 3685 default:
3686 r = -EINVAL;
3687 }
3688out:
d1ac91d8 3689 kfree(u.buffer);
313a3dc7
CO		 3690 return r;
3691}
3692
5b1c1493
CO		 3693int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3694{
3695 return VM_FAULT_SIGBUS;
3696}
3697
1fe779f8
CO		 3698static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3699{
3700 int ret;
3701
3702 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3703 return -EINVAL;
1fe779f8
CO		 3704 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3705 return ret;
3706}
3707
b927a3ce
SY		 3708static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3709 u64 ident_addr)
3710{
3711 kvm->arch.ept_identity_map_addr = ident_addr;
3712 return 0;
3713}
3714
1fe779f8
CO		 3715static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3716 u32 kvm_nr_mmu_pages)
3717{
3718 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3719 return -EINVAL;
3720
79fac95e 3721 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3722
3723 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3724 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3725
79fac95e 3726 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3727 return 0;
3728}
3729
3730static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3731{
39de71ec 3732 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3733}
3734
1fe779f8
CO		 3735static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3736{
90bca052 3737 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3738 int r;
3739
3740 r = 0;
3741 switch (chip->chip_id) {
3742 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3743 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3744 sizeof(struct kvm_pic_state));
3745 break;
3746 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3747 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 3748 sizeof(struct kvm_pic_state));
3749 break;
3750 case KVM_IRQCHIP_IOAPIC:
33392b49 3751 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3752 break;
3753 default:
3754 r = -EINVAL;
3755 break;
3756 }
3757 return r;
3758}
3759
3760static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3761{
90bca052 3762 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3763 int r;
3764
3765 r = 0;
3766 switch (chip->chip_id) {
3767 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 3768 spin_lock(&pic->lock);
3769 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 3770 sizeof(struct kvm_pic_state));
90bca052 3771 spin_unlock(&pic->lock);
1fe779f8
CO		 3772 break;
3773 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 3774 spin_lock(&pic->lock);
3775 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 3776 sizeof(struct kvm_pic_state));
90bca052 3777 spin_unlock(&pic->lock);
1fe779f8
CO		 3778 break;
3779 case KVM_IRQCHIP_IOAPIC:
33392b49 3780 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3781 break;
3782 default:
3783 r = -EINVAL;
3784 break;
3785 }
90bca052 3786 kvm_pic_update_irq(pic);
1fe779f8
CO		 3787 return r;
3788}
3789
e0f63cb9
SY		 3790static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3791{
34f3941c
RK		 3792 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3793
3794 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3795
3796 mutex_lock(&kps->lock);
3797 memcpy(ps, &kps->channels, sizeof(*ps));
3798 mutex_unlock(&kps->lock);
2da29bcc 3799 return 0;
e0f63cb9
SY		 3800}
3801
3802static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3803{
0185604c 3804 int i;
09edea72
RK		 3805 struct kvm_pit *pit = kvm->arch.vpit;
3806
3807 mutex_lock(&pit->pit_state.lock);
34f3941c 3808 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3809 for (i = 0; i < 3; i++)
09edea72
RK		 3810 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3811 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3812 return 0;
e9f42757
BK		 3813}
3814
3815static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3816{
e9f42757
BK		 3817 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3818 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3819 sizeof(ps->channels));
3820 ps->flags = kvm->arch.vpit->pit_state.flags;
3821 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3822 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3823 return 0;
e9f42757
BK		 3824}
3825
3826static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3827{
2da29bcc 3828 int start = 0;
0185604c 3829 int i;
e9f42757 3830 u32 prev_legacy, cur_legacy;
09edea72
RK		 3831 struct kvm_pit *pit = kvm->arch.vpit;
3832
3833 mutex_lock(&pit->pit_state.lock);
3834 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3835 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3836 if (!prev_legacy && cur_legacy)
3837 start = 1;
09edea72
RK		 3838 memcpy(&pit->pit_state.channels, &ps->channels,
3839 sizeof(pit->pit_state.channels));
3840 pit->pit_state.flags = ps->flags;
0185604c 3841 for (i = 0; i < 3; i++)
09edea72 3842 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3843 start && i == 0);
09edea72 3844 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3845 return 0;
e0f63cb9
SY		 3846}
3847
52d939a0
MT		 3848static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3849 struct kvm_reinject_control *control)
3850{
71474e2f
RK		 3851 struct kvm_pit *pit = kvm->arch.vpit;
3852
3853 if (!pit)
52d939a0 3854 return -ENXIO;
b39c90b6 3855
71474e2f
RK		 3856 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3857 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3858 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3859 */
3860 mutex_lock(&pit->pit_state.lock);
3861 kvm_pit_set_reinject(pit, control->pit_reinject);
3862 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3863
52d939a0
MT		 3864 return 0;
3865}
3866
95d4c16c 3867/**
60c34612
TY		 3868 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3869 * @kvm: kvm instance
3870 * @log: slot id and address to which we copy the log
95d4c16c 3871 *
e108ff2f
PB		 3872 * Steps 1-4 below provide general overview of dirty page logging. See
3873 * kvm_get_dirty_log_protect() function description for additional details.
3874 *
3875 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3876 * always flush the TLB (step 4) even if previous step failed and the dirty
3877 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3878 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3879 * writes will be marked dirty for next log read.
95d4c16c 3880 *
60c34612
TY		 3881 * 1. Take a snapshot of the bit and clear it if needed.
3882 * 2. Write protect the corresponding page.
e108ff2f
PB		 3883 * 3. Copy the snapshot to the userspace.
3884 * 4. Flush TLB's if needed.
5bb064dc 3885 */
60c34612 3886int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3887{
60c34612 3888 bool is_dirty = false;
e108ff2f 3889 int r;
5bb064dc 3890
79fac95e 3891 mutex_lock(&kvm->slots_lock);
5bb064dc 3892
88178fd4
KH		 3893 /*
3894 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3895 */
3896 if (kvm_x86_ops->flush_log_dirty)
3897 kvm_x86_ops->flush_log_dirty(kvm);
3898
e108ff2f 3899 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3900
3901 /*
3902 * All the TLBs can be flushed out of mmu lock, see the comments in
3903 * kvm_mmu_slot_remove_write_access().
3904 */
e108ff2f 3905 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3906 if (is_dirty)
3907 kvm_flush_remote_tlbs(kvm);
3908
79fac95e 3909 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3910 return r;
3911}
3912
aa2fbe6d
YZ		 3913int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3914 bool line_status)
23d43cf9
CD		 3915{
3916 if (!irqchip_in_kernel(kvm))
3917 return -ENXIO;
3918
3919 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3920 irq_event->irq, irq_event->level,
3921 line_status);
23d43cf9
CD		 3922 return 0;
3923}
3924
90de4a18
NA		 3925static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3926 struct kvm_enable_cap *cap)
3927{
3928 int r;
3929
3930 if (cap->flags)
3931 return -EINVAL;
3932
3933 switch (cap->cap) {
3934 case KVM_CAP_DISABLE_QUIRKS:
3935 kvm->arch.disabled_quirks = cap->args[0];
3936 r = 0;
3937 break;
49df6397
SR		 3938 case KVM_CAP_SPLIT_IRQCHIP: {
3939 mutex_lock(&kvm->lock);
b053b2ae
SR		 3940 r = -EINVAL;
3941 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3942 goto split_irqchip_unlock;
49df6397
SR		 3943 r = -EEXIST;
3944 if (irqchip_in_kernel(kvm))
3945 goto split_irqchip_unlock;
557abc40 3946 if (kvm->created_vcpus)
49df6397
SR		 3947 goto split_irqchip_unlock;
3948 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 3949 if (r)
49df6397
SR		 3950 goto split_irqchip_unlock;
3951 /* Pairs with irqchip_in_kernel. */
3952 smp_wmb();
49776faf 3953 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 3954 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3955 r = 0;
3956split_irqchip_unlock:
3957 mutex_unlock(&kvm->lock);
3958 break;
3959 }
37131313
RK		 3960 case KVM_CAP_X2APIC_API:
3961 r = -EINVAL;
3962 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
3963 break;
3964
3965 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
3966 kvm->arch.x2apic_format = true;
c519265f
RK		 3967 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
3968 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 3969
3970 r = 0;
3971 break;
90de4a18
NA		 3972 default:
3973 r = -EINVAL;
3974 break;
3975 }
3976 return r;
3977}
3978
1fe779f8
CO		 3979long kvm_arch_vm_ioctl(struct file *filp,
3980 unsigned int ioctl, unsigned long arg)
3981{
3982 struct kvm *kvm = filp->private_data;
3983 void __user *argp = (void __user *)arg;
367e1319 3984 int r = -ENOTTY;
f0d66275
DH		 3985 /*
3986 * This union makes it completely explicit to gcc-3.x
3987 * that these two variables' stack usage should be
3988 * combined, not added together.
3989 */
3990 union {
3991 struct kvm_pit_state ps;
e9f42757 3992 struct kvm_pit_state2 ps2;
c5ff41ce 3993 struct kvm_pit_config pit_config;
f0d66275 3994 } u;
1fe779f8
CO		 3995
3996 switch (ioctl) {
3997 case KVM_SET_TSS_ADDR:
3998 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3999 break;
b927a3ce
SY		 4000 case KVM_SET_IDENTITY_MAP_ADDR: {
4001 u64 ident_addr;
4002
4003 r = -EFAULT;
4004 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
4005 goto out;
4006 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 4007 break;
4008 }
1fe779f8
CO		 4009 case KVM_SET_NR_MMU_PAGES:
4010 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4011 break;
4012 case KVM_GET_NR_MMU_PAGES:
4013 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4014 break;
3ddea128 4015 case KVM_CREATE_IRQCHIP: {
3ddea128 4016 mutex_lock(&kvm->lock);
09941366 4017
3ddea128 4018 r = -EEXIST;
35e6eaa3 4019 if (irqchip_in_kernel(kvm))
3ddea128 4020 goto create_irqchip_unlock;
09941366 4021
3e515705 4022 r = -EINVAL;
557abc40 4023 if (kvm->created_vcpus)
3e515705 4024 goto create_irqchip_unlock;
09941366
RK		 4025
4026 r = kvm_pic_init(kvm);
4027 if (r)
3ddea128 4028 goto create_irqchip_unlock;
09941366
RK		 4029
4030 r = kvm_ioapic_init(kvm);
4031 if (r) {
09941366 4032 kvm_pic_destroy(kvm);
3ddea128 4033 goto create_irqchip_unlock;
09941366
RK		 4034 }
4035
399ec807
AK		 4036 r = kvm_setup_default_irq_routing(kvm);
4037 if (r) {
72bb2fcd 4038 kvm_ioapic_destroy(kvm);
09941366 4039 kvm_pic_destroy(kvm);
71ba994c 4040 goto create_irqchip_unlock;
399ec807 4041 }
49776faf 4042 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4043 smp_wmb();
49776faf 4044 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4045 create_irqchip_unlock:
4046 mutex_unlock(&kvm->lock);
1fe779f8 4047 break;
3ddea128 4048 }
7837699f 4049 case KVM_CREATE_PIT:
c5ff41ce
JK		 4050 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4051 goto create_pit;
4052 case KVM_CREATE_PIT2:
4053 r = -EFAULT;
4054 if (copy_from_user(&u.pit_config, argp,
4055 sizeof(struct kvm_pit_config)))
4056 goto out;
4057 create_pit:
250715a6 4058 mutex_lock(&kvm->lock);
269e05e4
AK		 4059 r = -EEXIST;
4060 if (kvm->arch.vpit)
4061 goto create_pit_unlock;
7837699f 4062 r = -ENOMEM;
c5ff41ce 4063 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4064 if (kvm->arch.vpit)
4065 r = 0;
269e05e4 4066 create_pit_unlock:
250715a6 4067 mutex_unlock(&kvm->lock);
7837699f 4068 break;
1fe779f8
CO		 4069 case KVM_GET_IRQCHIP: {
4070 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4071 struct kvm_irqchip *chip;
1fe779f8 4072
ff5c2c03
SL		 4073 chip = memdup_user(argp, sizeof(*chip));
4074 if (IS_ERR(chip)) {
4075 r = PTR_ERR(chip);
1fe779f8 4076 goto out;
ff5c2c03
SL		 4077 }
4078
1fe779f8 4079 r = -ENXIO;
826da321 4080 if (!irqchip_kernel(kvm))
f0d66275
DH		 4081 goto get_irqchip_out;
4082 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4083 if (r)
f0d66275 4084 goto get_irqchip_out;
1fe779f8 4085 r = -EFAULT;
f0d66275
DH		 4086 if (copy_to_user(argp, chip, sizeof *chip))
4087 goto get_irqchip_out;
1fe779f8 4088 r = 0;
f0d66275
DH		 4089 get_irqchip_out:
4090 kfree(chip);
1fe779f8
CO		 4091 break;
4092 }
4093 case KVM_SET_IRQCHIP: {
4094 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4095 struct kvm_irqchip *chip;
1fe779f8 4096
ff5c2c03
SL		 4097 chip = memdup_user(argp, sizeof(*chip));
4098 if (IS_ERR(chip)) {
4099 r = PTR_ERR(chip);
1fe779f8 4100 goto out;
ff5c2c03
SL		 4101 }
4102
1fe779f8 4103 r = -ENXIO;
826da321 4104 if (!irqchip_kernel(kvm))
f0d66275
DH		 4105 goto set_irqchip_out;
4106 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4107 if (r)
f0d66275 4108 goto set_irqchip_out;
1fe779f8 4109 r = 0;
f0d66275
DH		 4110 set_irqchip_out:
4111 kfree(chip);
1fe779f8
CO		 4112 break;
4113 }
e0f63cb9 4114 case KVM_GET_PIT: {
e0f63cb9 4115 r = -EFAULT;
f0d66275 4116 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4117 goto out;
4118 r = -ENXIO;
4119 if (!kvm->arch.vpit)
4120 goto out;
f0d66275 4121 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4122 if (r)
4123 goto out;
4124 r = -EFAULT;
f0d66275 4125 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4126 goto out;
4127 r = 0;
4128 break;
4129 }
4130 case KVM_SET_PIT: {
e0f63cb9 4131 r = -EFAULT;
f0d66275 4132 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4133 goto out;
4134 r = -ENXIO;
4135 if (!kvm->arch.vpit)
4136 goto out;
f0d66275 4137 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4138 break;
4139 }
e9f42757
BK		 4140 case KVM_GET_PIT2: {
4141 r = -ENXIO;
4142 if (!kvm->arch.vpit)
4143 goto out;
4144 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4145 if (r)
4146 goto out;
4147 r = -EFAULT;
4148 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4149 goto out;
4150 r = 0;
4151 break;
4152 }
4153 case KVM_SET_PIT2: {
4154 r = -EFAULT;
4155 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4156 goto out;
4157 r = -ENXIO;
4158 if (!kvm->arch.vpit)
4159 goto out;
4160 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4161 break;
4162 }
52d939a0
MT		 4163 case KVM_REINJECT_CONTROL: {
4164 struct kvm_reinject_control control;
4165 r = -EFAULT;
4166 if (copy_from_user(&control, argp, sizeof(control)))
4167 goto out;
4168 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4169 break;
4170 }
d71ba788
PB		 4171 case KVM_SET_BOOT_CPU_ID:
4172 r = 0;
4173 mutex_lock(&kvm->lock);
557abc40 4174 if (kvm->created_vcpus)
d71ba788
PB		 4175 r = -EBUSY;
4176 else
4177 kvm->arch.bsp_vcpu_id = arg;
4178 mutex_unlock(&kvm->lock);
4179 break;
ffde22ac
ES		 4180 case KVM_XEN_HVM_CONFIG: {
4181 r = -EFAULT;
4182 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4183 sizeof(struct kvm_xen_hvm_config)))
4184 goto out;
4185 r = -EINVAL;
4186 if (kvm->arch.xen_hvm_config.flags)
4187 goto out;
4188 r = 0;
4189 break;
4190 }
afbcf7ab 4191 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4192 struct kvm_clock_data user_ns;
4193 u64 now_ns;
afbcf7ab
GC		 4194
4195 r = -EFAULT;
4196 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4197 goto out;
4198
4199 r = -EINVAL;
4200 if (user_ns.flags)
4201 goto out;
4202
4203 r = 0;
0bc48bea
RK		 4204 /*
4205 * TODO: userspace has to take care of races with VCPU_RUN, so
4206 * kvm_gen_update_masterclock() can be cut down to locked
4207 * pvclock_update_vm_gtod_copy().
4208 */
4209 kvm_gen_update_masterclock(kvm);
e891a32e 4210 now_ns = get_kvmclock_ns(kvm);
108b249c 4211 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4212 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4213 break;
4214 }
4215 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4216 struct kvm_clock_data user_ns;
4217 u64 now_ns;
4218
e891a32e 4219 now_ns = get_kvmclock_ns(kvm);
108b249c 4220 user_ns.clock = now_ns;
e3fd9a93 4221 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4222 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4223
4224 r = -EFAULT;
4225 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4226 goto out;
4227 r = 0;
4228 break;
4229 }
90de4a18
NA		 4230 case KVM_ENABLE_CAP: {
4231 struct kvm_enable_cap cap;
afbcf7ab 4232
90de4a18
NA		 4233 r = -EFAULT;
4234 if (copy_from_user(&cap, argp, sizeof(cap)))
4235 goto out;
4236 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4237 break;
4238 }
1fe779f8 4239 default:
ad6260da 4240 r = -ENOTTY;
1fe779f8
CO		 4241 }
4242out:
4243 return r;
4244}
4245
a16b043c 4246static void kvm_init_msr_list(void)
043405e1
CO		 4247{
4248 u32 dummy[2];
4249 unsigned i, j;
4250
62ef68bb 4251 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4252 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4253 continue;
93c4adc7
PB		 4254
4255 /*
4256 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4257 * to the guests in some cases.
93c4adc7
PB		 4258 */
4259 switch (msrs_to_save[i]) {
4260 case MSR_IA32_BNDCFGS:
4261 if (!kvm_x86_ops->mpx_supported())
4262 continue;
4263 break;
9dbe6cf9
PB		 4264 case MSR_TSC_AUX:
4265 if (!kvm_x86_ops->rdtscp_supported())
4266 continue;
4267 break;
93c4adc7
PB		 4268 default:
4269 break;
4270 }
4271
043405e1
CO		 4272 if (j < i)
4273 msrs_to_save[j] = msrs_to_save[i];
4274 j++;
4275 }
4276 num_msrs_to_save = j;
62ef68bb
PB		 4277
4278 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4279 switch (emulated_msrs[i]) {
6d396b55
PB		 4280 case MSR_IA32_SMBASE:
4281 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4282 continue;
4283 break;
62ef68bb
PB		 4284 default:
4285 break;
4286 }
4287
4288 if (j < i)
4289 emulated_msrs[j] = emulated_msrs[i];
4290 j++;
4291 }
4292 num_emulated_msrs = j;
043405e1
CO		 4293}
4294
bda9020e
MT		 4295static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4296 const void *v)
bbd9b64e 4297{
70252a10
AK		 4298 int handled = 0;
4299 int n;
4300
4301 do {
4302 n = min(len, 8);
bce87cce 4303 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4304 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4305 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4306 break;
4307 handled += n;
4308 addr += n;
4309 len -= n;
4310 v += n;
4311 } while (len);
bbd9b64e 4312
70252a10 4313 return handled;
bbd9b64e
CO		 4314}
4315
bda9020e 4316static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4317{
70252a10
AK		 4318 int handled = 0;
4319 int n;
4320
4321 do {
4322 n = min(len, 8);
bce87cce 4323 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4324 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4325 addr, n, v))
4326 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4327 break;
4328 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4329 handled += n;
4330 addr += n;
4331 len -= n;
4332 v += n;
4333 } while (len);
bbd9b64e 4334
70252a10 4335 return handled;
bbd9b64e
CO		 4336}
4337
2dafc6c2
GN		 4338static void kvm_set_segment(struct kvm_vcpu *vcpu,
4339 struct kvm_segment *var, int seg)
4340{
4341 kvm_x86_ops->set_segment(vcpu, var, seg);
4342}
4343
4344void kvm_get_segment(struct kvm_vcpu *vcpu,
4345 struct kvm_segment *var, int seg)
4346{
4347 kvm_x86_ops->get_segment(vcpu, var, seg);
4348}
4349
54987b7a
PB		 4350gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4351 struct x86_exception *exception)
02f59dc9
JR		 4352{
4353 gpa_t t_gpa;
02f59dc9
JR		 4354
4355 BUG_ON(!mmu_is_nested(vcpu));
4356
4357 /* NPT walks are always user-walks */
4358 access |= PFERR_USER_MASK;
54987b7a 4359 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4360
4361 return t_gpa;
4362}
4363
ab9ae313
AK		 4364gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4365 struct x86_exception *exception)
1871c602
GN		 4366{
4367 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4368 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4369}
4370
ab9ae313
AK		 4371 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4372 struct x86_exception *exception)
1871c602
GN		 4373{
4374 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4375 access |= PFERR_FETCH_MASK;
ab9ae313 4376 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4377}
4378
ab9ae313
AK		 4379gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4380 struct x86_exception *exception)
1871c602
GN		 4381{
4382 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4383 access |= PFERR_WRITE_MASK;
ab9ae313 4384 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4385}
4386
4387/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4388gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4389 struct x86_exception *exception)
1871c602 4390{
ab9ae313 4391 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4392}
4393
4394static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4395 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4396 struct x86_exception *exception)
bbd9b64e
CO		 4397{
4398 void *data = val;
10589a46 4399 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4400
4401 while (bytes) {
14dfe855 4402 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4403 exception);
bbd9b64e 4404 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4405 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4406 int ret;
4407
bcc55cba 4408 if (gpa == UNMAPPED_GVA)
ab9ae313 4409 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4410 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4411 offset, toread);
10589a46 4412 if (ret < 0) {
c3cd7ffa 4413 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4414 goto out;
4415 }
bbd9b64e 4416
77c2002e
IE		 4417 bytes -= toread;
4418 data += toread;
4419 addr += toread;
bbd9b64e 4420 }
10589a46 4421out:
10589a46 4422 return r;
bbd9b64e 4423}
77c2002e 4424
1871c602 4425/* used for instruction fetching */
0f65dd70
AK		 4426static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4427 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4428 struct x86_exception *exception)
1871c602 4429{
0f65dd70 4430 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4431 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4432 unsigned offset;
4433 int ret;
0f65dd70 4434
44583cba
PB		 4435 /* Inline kvm_read_guest_virt_helper for speed. */
4436 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4437 exception);
4438 if (unlikely(gpa == UNMAPPED_GVA))
4439 return X86EMUL_PROPAGATE_FAULT;
4440
4441 offset = addr & (PAGE_SIZE-1);
4442 if (WARN_ON(offset + bytes > PAGE_SIZE))
4443 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4444 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4445 offset, bytes);
44583cba
PB		 4446 if (unlikely(ret < 0))
4447 return X86EMUL_IO_NEEDED;
4448
4449 return X86EMUL_CONTINUE;
1871c602
GN		 4450}
4451
064aea77 4452int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4453 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4454 struct x86_exception *exception)
1871c602 4455{
0f65dd70 4456 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4457 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4458
1871c602 4459 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4460 exception);
1871c602 4461}
064aea77 4462EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4463
0f65dd70
AK		 4464static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4465 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4466 struct x86_exception *exception)
1871c602 4467{
0f65dd70 4468 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4469 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4470}
4471
7a036a6f
RK		 4472static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4473 unsigned long addr, void *val, unsigned int bytes)
4474{
4475 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4476 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4477
4478 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4479}
4480
6a4d7550 4481int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4482 gva_t addr, void *val,
2dafc6c2 4483 unsigned int bytes,
bcc55cba 4484 struct x86_exception *exception)
77c2002e 4485{
0f65dd70 4486 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4487 void *data = val;
4488 int r = X86EMUL_CONTINUE;
4489
4490 while (bytes) {
14dfe855
JR		 4491 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4492 PFERR_WRITE_MASK,
ab9ae313 4493 exception);
77c2002e
IE		 4494 unsigned offset = addr & (PAGE_SIZE-1);
4495 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4496 int ret;
4497
bcc55cba 4498 if (gpa == UNMAPPED_GVA)
ab9ae313 4499 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4500 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4501 if (ret < 0) {
c3cd7ffa 4502 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4503 goto out;
4504 }
4505
4506 bytes -= towrite;
4507 data += towrite;
4508 addr += towrite;
4509 }
4510out:
4511 return r;
4512}
6a4d7550 4513EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4514
0f89b207
TL		 4515static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4516 gpa_t gpa, bool write)
4517{
4518 /* For APIC access vmexit */
4519 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4520 return 1;
4521
4522 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4523 trace_vcpu_match_mmio(gva, gpa, write, true);
4524 return 1;
4525 }
4526
4527 return 0;
4528}
4529
af7cc7d1
XG		 4530static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4531 gpa_t *gpa, struct x86_exception *exception,
4532 bool write)
4533{
97d64b78
AK		 4534 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4535 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4536
be94f6b7
HH		 4537 /*
4538 * currently PKRU is only applied to ept enabled guest so
4539 * there is no pkey in EPT page table for L1 guest or EPT
4540 * shadow page table for L2 guest.
4541 */
97d64b78 4542 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4543 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4544 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4545 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4546 (gva & (PAGE_SIZE - 1));
4f022648 4547 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4548 return 1;
4549 }
4550
af7cc7d1
XG		 4551 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4552
4553 if (*gpa == UNMAPPED_GVA)
4554 return -1;
4555
0f89b207 4556 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4557}
4558
3200f405 4559int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4560 const void *val, int bytes)
bbd9b64e
CO		 4561{
4562 int ret;
4563
54bf36aa 4564 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4565 if (ret < 0)
bbd9b64e 4566 return 0;
0eb05bf2 4567 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4568 return 1;
4569}
4570
77d197b2
XG		 4571struct read_write_emulator_ops {
4572 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4573 int bytes);
4574 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4575 void *val, int bytes);
4576 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4577 int bytes, void *val);
4578 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4579 void *val, int bytes);
4580 bool write;
4581};
4582
4583static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4584{
4585 if (vcpu->mmio_read_completed) {
77d197b2 4586 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4587 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4588 vcpu->mmio_read_completed = 0;
4589 return 1;
4590 }
4591
4592 return 0;
4593}
4594
4595static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4596 void *val, int bytes)
4597{
54bf36aa 4598 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4599}
4600
4601static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4602 void *val, int bytes)
4603{
4604 return emulator_write_phys(vcpu, gpa, val, bytes);
4605}
4606
4607static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4608{
4609 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4610 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4611}
4612
4613static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4614 void *val, int bytes)
4615{
4616 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4617 return X86EMUL_IO_NEEDED;
4618}
4619
4620static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4621 void *val, int bytes)
4622{
f78146b0
AK		 4623 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4624
87da7e66 4625 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4626 return X86EMUL_CONTINUE;
4627}
4628
0fbe9b0b 4629static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4630 .read_write_prepare = read_prepare,
4631 .read_write_emulate = read_emulate,
4632 .read_write_mmio = vcpu_mmio_read,
4633 .read_write_exit_mmio = read_exit_mmio,
4634};
4635
0fbe9b0b 4636static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4637 .read_write_emulate = write_emulate,
4638 .read_write_mmio = write_mmio,
4639 .read_write_exit_mmio = write_exit_mmio,
4640 .write = true,
4641};
4642
22388a3c
XG		 4643static int emulator_read_write_onepage(unsigned long addr, void *val,
4644 unsigned int bytes,
4645 struct x86_exception *exception,
4646 struct kvm_vcpu *vcpu,
0fbe9b0b 4647 const struct read_write_emulator_ops *ops)
bbd9b64e 4648{
af7cc7d1
XG		 4649 gpa_t gpa;
4650 int handled, ret;
22388a3c 4651 bool write = ops->write;
f78146b0 4652 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4653 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4654
4655 /*
4656 * If the exit was due to a NPF we may already have a GPA.
4657 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4658 * Note, this cannot be used on string operations since string
4659 * operation using rep will only have the initial GPA from the NPF
4660 * occurred.
4661 */
4662 if (vcpu->arch.gpa_available &&
4663 emulator_can_use_gpa(ctxt) &&
4664 vcpu_is_mmio_gpa(vcpu, addr, exception->address, write) &&
4665 (addr & ~PAGE_MASK) == (exception->address & ~PAGE_MASK)) {
4666 gpa = exception->address;
4667 goto mmio;
4668 }
10589a46 4669
22388a3c 4670 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4671
af7cc7d1 4672 if (ret < 0)
bbd9b64e 4673 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4674
4675 /* For APIC access vmexit */
af7cc7d1 4676 if (ret)
bbd9b64e
CO		 4677 goto mmio;
4678
22388a3c 4679 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4680 return X86EMUL_CONTINUE;
4681
4682mmio:
4683 /*
4684 * Is this MMIO handled locally?
4685 */
22388a3c 4686 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4687 if (handled == bytes)
bbd9b64e 4688 return X86EMUL_CONTINUE;
bbd9b64e 4689
70252a10
AK		 4690 gpa += handled;
4691 bytes -= handled;
4692 val += handled;
4693
87da7e66
XG		 4694 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4695 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4696 frag->gpa = gpa;
4697 frag->data = val;
4698 frag->len = bytes;
f78146b0 4699 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4700}
4701
52eb5a6d
XL		 4702static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4703 unsigned long addr,
22388a3c
XG		 4704 void *val, unsigned int bytes,
4705 struct x86_exception *exception,
0fbe9b0b 4706 const struct read_write_emulator_ops *ops)
bbd9b64e 4707{
0f65dd70 4708 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4709 gpa_t gpa;
4710 int rc;
4711
4712 if (ops->read_write_prepare &&
4713 ops->read_write_prepare(vcpu, val, bytes))
4714 return X86EMUL_CONTINUE;
4715
4716 vcpu->mmio_nr_fragments = 0;
0f65dd70 4717
bbd9b64e
CO		 4718 /* Crossing a page boundary? */
4719 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4720 int now;
bbd9b64e
CO		 4721
4722 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4723 rc = emulator_read_write_onepage(addr, val, now, exception,
4724 vcpu, ops);
4725
bbd9b64e
CO		 4726 if (rc != X86EMUL_CONTINUE)
4727 return rc;
4728 addr += now;
bac15531
NA		 4729 if (ctxt->mode != X86EMUL_MODE_PROT64)
4730 addr = (u32)addr;
bbd9b64e
CO		 4731 val += now;
4732 bytes -= now;
4733 }
22388a3c 4734
f78146b0
AK		 4735 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4736 vcpu, ops);
4737 if (rc != X86EMUL_CONTINUE)
4738 return rc;
4739
4740 if (!vcpu->mmio_nr_fragments)
4741 return rc;
4742
4743 gpa = vcpu->mmio_fragments[0].gpa;
4744
4745 vcpu->mmio_needed = 1;
4746 vcpu->mmio_cur_fragment = 0;
4747
87da7e66 4748 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4749 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4750 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4751 vcpu->run->mmio.phys_addr = gpa;
4752
4753 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4754}
4755
4756static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4757 unsigned long addr,
4758 void *val,
4759 unsigned int bytes,
4760 struct x86_exception *exception)
4761{
4762 return emulator_read_write(ctxt, addr, val, bytes,
4763 exception, &read_emultor);
4764}
4765
52eb5a6d 4766static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4767 unsigned long addr,
4768 const void *val,
4769 unsigned int bytes,
4770 struct x86_exception *exception)
4771{
4772 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4773 exception, &write_emultor);
bbd9b64e 4774}
bbd9b64e 4775
daea3e73
AK		 4776#define CMPXCHG_TYPE(t, ptr, old, new) \
4777 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4778
4779#ifdef CONFIG_X86_64
4780# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4781#else
4782# define CMPXCHG64(ptr, old, new) \
9749a6c0 4783 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4784#endif
4785
0f65dd70
AK		 4786static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4787 unsigned long addr,
bbd9b64e
CO		 4788 const void *old,
4789 const void *new,
4790 unsigned int bytes,
0f65dd70 4791 struct x86_exception *exception)
bbd9b64e 4792{
0f65dd70 4793 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4794 gpa_t gpa;
4795 struct page *page;
4796 char *kaddr;
4797 bool exchanged;
2bacc55c 4798
daea3e73
AK		 4799 /* guests cmpxchg8b have to be emulated atomically */
4800 if (bytes > 8 || (bytes & (bytes - 1)))
4801 goto emul_write;
10589a46 4802
daea3e73 4803 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4804
daea3e73
AK		 4805 if (gpa == UNMAPPED_GVA ||
4806 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4807 goto emul_write;
2bacc55c 4808
daea3e73
AK		 4809 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4810 goto emul_write;
72dc67a6 4811
54bf36aa 4812 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4813 if (is_error_page(page))
c19b8bd6 4814 goto emul_write;
72dc67a6 4815
8fd75e12 4816 kaddr = kmap_atomic(page);
daea3e73
AK		 4817 kaddr += offset_in_page(gpa);
4818 switch (bytes) {
4819 case 1:
4820 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4821 break;
4822 case 2:
4823 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4824 break;
4825 case 4:
4826 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4827 break;
4828 case 8:
4829 exchanged = CMPXCHG64(kaddr, old, new);
4830 break;
4831 default:
4832 BUG();
2bacc55c 4833 }
8fd75e12 4834 kunmap_atomic(kaddr);
daea3e73
AK		 4835 kvm_release_page_dirty(page);
4836
4837 if (!exchanged)
4838 return X86EMUL_CMPXCHG_FAILED;
4839
54bf36aa 4840 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4841 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4842
4843 return X86EMUL_CONTINUE;
4a5f48f6 4844
3200f405 4845emul_write:
daea3e73 4846 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4847
0f65dd70 4848 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4849}
4850
cf8f70bf
GN		 4851static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4852{
cbfc6c91 4853 int r = 0, i;
cf8f70bf 4854
cbfc6c91
WL		 4855 for (i = 0; i < vcpu->arch.pio.count; i++) {
4856 if (vcpu->arch.pio.in)
4857 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4858 vcpu->arch.pio.size, pd);
4859 else
4860 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4861 vcpu->arch.pio.port, vcpu->arch.pio.size,
4862 pd);
4863 if (r)
4864 break;
4865 pd += vcpu->arch.pio.size;
4866 }
cf8f70bf
GN		 4867 return r;
4868}
4869
6f6fbe98
XG		 4870static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4871 unsigned short port, void *val,
4872 unsigned int count, bool in)
cf8f70bf 4873{
cf8f70bf 4874 vcpu->arch.pio.port = port;
6f6fbe98 4875 vcpu->arch.pio.in = in;
7972995b 4876 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4877 vcpu->arch.pio.size = size;
4878
4879 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4880 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4881 return 1;
4882 }
4883
4884 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4885 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4886 vcpu->run->io.size = size;
4887 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4888 vcpu->run->io.count = count;
4889 vcpu->run->io.port = port;
4890
4891 return 0;
4892}
4893
6f6fbe98
XG		 4894static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4895 int size, unsigned short port, void *val,
4896 unsigned int count)
cf8f70bf 4897{
ca1d4a9e 4898 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4899 int ret;
ca1d4a9e 4900
6f6fbe98
XG		 4901 if (vcpu->arch.pio.count)
4902 goto data_avail;
cf8f70bf 4903
cbfc6c91
WL		 4904 memset(vcpu->arch.pio_data, 0, size * count);
4905
6f6fbe98
XG		 4906 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4907 if (ret) {
4908data_avail:
4909 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4910 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4911 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4912 return 1;
4913 }
4914
cf8f70bf
GN		 4915 return 0;
4916}
4917
6f6fbe98
XG		 4918static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4919 int size, unsigned short port,
4920 const void *val, unsigned int count)
4921{
4922 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4923
4924 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4925 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4926 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4927}
4928
bbd9b64e
CO		 4929static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4930{
4931 return kvm_x86_ops->get_segment_base(vcpu, seg);
4932}
4933
3cb16fe7 4934static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4935{
3cb16fe7 4936 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4937}
4938
ae6a2375 4939static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4940{
4941 if (!need_emulate_wbinvd(vcpu))
4942 return X86EMUL_CONTINUE;
4943
4944 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4945 int cpu = get_cpu();
4946
4947 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4948 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4949 wbinvd_ipi, NULL, 1);
2eec7343 4950 put_cpu();
f5f48ee1 4951 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4952 } else
4953 wbinvd();
f5f48ee1
SY		 4954 return X86EMUL_CONTINUE;
4955}
5cb56059
JS		 4956
4957int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4958{
6affcbed
KH		 4959 kvm_emulate_wbinvd_noskip(vcpu);
4960 return kvm_skip_emulated_instruction(vcpu);
5cb56059 4961}
f5f48ee1
SY		 4962EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4963
5cb56059
JS		 4964
4965
bcaf5cc5
AK		 4966static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4967{
5cb56059 4968 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4969}
4970
52eb5a6d
XL		 4971static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4972 unsigned long *dest)
bbd9b64e 4973{
16f8a6f9 4974 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4975}
4976
52eb5a6d
XL		 4977static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4978 unsigned long value)
bbd9b64e 4979{
338dbc97 4980
717746e3 4981 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4982}
4983
52a46617 4984static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4985{
52a46617 4986 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4987}
4988
717746e3 4989static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4990{
717746e3 4991 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4992 unsigned long value;
4993
4994 switch (cr) {
4995 case 0:
4996 value = kvm_read_cr0(vcpu);
4997 break;
4998 case 2:
4999 value = vcpu->arch.cr2;
5000 break;
5001 case 3:
9f8fe504 5002 value = kvm_read_cr3(vcpu);
52a46617
GN		 5003 break;
5004 case 4:
5005 value = kvm_read_cr4(vcpu);
5006 break;
5007 case 8:
5008 value = kvm_get_cr8(vcpu);
5009 break;
5010 default:
a737f256 5011 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5012 return 0;
5013 }
5014
5015 return value;
5016}
5017
717746e3 5018static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5019{
717746e3 5020 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5021 int res = 0;
5022
52a46617
GN		 5023 switch (cr) {
5024 case 0:
49a9b07e 5025 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5026 break;
5027 case 2:
5028 vcpu->arch.cr2 = val;
5029 break;
5030 case 3:
2390218b 5031 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5032 break;
5033 case 4:
a83b29c6 5034 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5035 break;
5036 case 8:
eea1cff9 5037 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5038 break;
5039 default:
a737f256 5040 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5041 res = -1;
52a46617 5042 }
0f12244f
GN		 5043
5044 return res;
52a46617
GN		 5045}
5046
717746e3 5047static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5048{
717746e3 5049 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5050}
5051
4bff1e86 5052static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5053{
4bff1e86 5054 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5055}
5056
4bff1e86 5057static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5058{
4bff1e86 5059 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5060}
5061
1ac9d0cf
AK		 5062static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5063{
5064 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5065}
5066
5067static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5068{
5069 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5070}
5071
4bff1e86
AK		 5072static unsigned long emulator_get_cached_segment_base(
5073 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5074{
4bff1e86 5075 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5076}
5077
1aa36616
AK		 5078static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5079 struct desc_struct *desc, u32 *base3,
5080 int seg)
2dafc6c2
GN		 5081{
5082 struct kvm_segment var;
5083
4bff1e86 5084 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5085 *selector = var.selector;
2dafc6c2 5086
378a8b09
GN		 5087 if (var.unusable) {
5088 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5089 if (base3)
5090 *base3 = 0;
2dafc6c2 5091 return false;
378a8b09 5092 }
2dafc6c2
GN		 5093
5094 if (var.g)
5095 var.limit >>= 12;
5096 set_desc_limit(desc, var.limit);
5097 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5098#ifdef CONFIG_X86_64
5099 if (base3)
5100 *base3 = var.base >> 32;
5101#endif
2dafc6c2
GN		 5102 desc->type = var.type;
5103 desc->s = var.s;
5104 desc->dpl = var.dpl;
5105 desc->p = var.present;
5106 desc->avl = var.avl;
5107 desc->l = var.l;
5108 desc->d = var.db;
5109 desc->g = var.g;
5110
5111 return true;
5112}
5113
1aa36616
AK		 5114static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5115 struct desc_struct *desc, u32 base3,
5116 int seg)
2dafc6c2 5117{
4bff1e86 5118 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5119 struct kvm_segment var;
5120
1aa36616 5121 var.selector = selector;
2dafc6c2 5122 var.base = get_desc_base(desc);
5601d05b
GN		 5123#ifdef CONFIG_X86_64
5124 var.base |= ((u64)base3) << 32;
5125#endif
2dafc6c2
GN		 5126 var.limit = get_desc_limit(desc);
5127 if (desc->g)
5128 var.limit = (var.limit << 12) | 0xfff;
5129 var.type = desc->type;
2dafc6c2
GN		 5130 var.dpl = desc->dpl;
5131 var.db = desc->d;
5132 var.s = desc->s;
5133 var.l = desc->l;
5134 var.g = desc->g;
5135 var.avl = desc->avl;
5136 var.present = desc->p;
5137 var.unusable = !var.present;
5138 var.padding = 0;
5139
5140 kvm_set_segment(vcpu, &var, seg);
5141 return;
5142}
5143
717746e3
AK		 5144static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5145 u32 msr_index, u64 *pdata)
5146{
609e36d3
PB		 5147 struct msr_data msr;
5148 int r;
5149
5150 msr.index = msr_index;
5151 msr.host_initiated = false;
5152 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5153 if (r)
5154 return r;
5155
5156 *pdata = msr.data;
5157 return 0;
717746e3
AK		 5158}
5159
5160static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5161 u32 msr_index, u64 data)
5162{
8fe8ab46
WA		 5163 struct msr_data msr;
5164
5165 msr.data = data;
5166 msr.index = msr_index;
5167 msr.host_initiated = false;
5168 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5169}
5170
64d60670
PB		 5171static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5172{
5173 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5174
5175 return vcpu->arch.smbase;
5176}
5177
5178static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5179{
5180 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5181
5182 vcpu->arch.smbase = smbase;
5183}
5184
67f4d428
NA		 5185static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5186 u32 pmc)
5187{
c6702c9d 5188 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5189}
5190
222d21aa
AK		 5191static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5192 u32 pmc, u64 *pdata)
5193{
c6702c9d 5194 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5195}
5196
6c3287f7
AK		 5197static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5198{
5199 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5200}
5201
5037f6f3
AK		 5202static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5203{
5204 preempt_disable();
5197b808 5205 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5206}
5207
5208static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5209{
5210 preempt_enable();
5211}
5212
2953538e 5213static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5214 struct x86_instruction_info *info,
c4f035c6
AK		 5215 enum x86_intercept_stage stage)
5216{
2953538e 5217 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5218}
5219
0017f93a 5220static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5221 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5222{
0017f93a 5223 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5224}
5225
dd856efa
AK		 5226static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5227{
5228 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5229}
5230
5231static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5232{
5233 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5234}
5235
801806d9
NA		 5236static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5237{
5238 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5239}
5240
6ed071f0
LP		 5241static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5242{
5243 return emul_to_vcpu(ctxt)->arch.hflags;
5244}
5245
5246static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5247{
5248 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5249}
5250
0225fb50 5251static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5252 .read_gpr = emulator_read_gpr,
5253 .write_gpr = emulator_write_gpr,
1871c602 5254 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5255 .write_std = kvm_write_guest_virt_system,
7a036a6f 5256 .read_phys = kvm_read_guest_phys_system,
1871c602 5257 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5258 .read_emulated = emulator_read_emulated,
5259 .write_emulated = emulator_write_emulated,
5260 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5261 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5262 .pio_in_emulated = emulator_pio_in_emulated,
5263 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5264 .get_segment = emulator_get_segment,
5265 .set_segment = emulator_set_segment,
5951c442 5266 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5267 .get_gdt = emulator_get_gdt,
160ce1f1 5268 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5269 .set_gdt = emulator_set_gdt,
5270 .set_idt = emulator_set_idt,
52a46617
GN		 5271 .get_cr = emulator_get_cr,
5272 .set_cr = emulator_set_cr,
9c537244 5273 .cpl = emulator_get_cpl,
35aa5375
GN		 5274 .get_dr = emulator_get_dr,
5275 .set_dr = emulator_set_dr,
64d60670
PB		 5276 .get_smbase = emulator_get_smbase,
5277 .set_smbase = emulator_set_smbase,
717746e3
AK		 5278 .set_msr = emulator_set_msr,
5279 .get_msr = emulator_get_msr,
67f4d428 5280 .check_pmc = emulator_check_pmc,
222d21aa 5281 .read_pmc = emulator_read_pmc,
6c3287f7 5282 .halt = emulator_halt,
bcaf5cc5 5283 .wbinvd = emulator_wbinvd,
d6aa1000 5284 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5285 .get_fpu = emulator_get_fpu,
5286 .put_fpu = emulator_put_fpu,
c4f035c6 5287 .intercept = emulator_intercept,
bdb42f5a 5288 .get_cpuid = emulator_get_cpuid,
801806d9 5289 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5290 .get_hflags = emulator_get_hflags,
5291 .set_hflags = emulator_set_hflags,
bbd9b64e
CO		 5292};
5293
95cb2295
GN		 5294static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5295{
37ccdcbe 5296 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5297 /*
5298 * an sti; sti; sequence only disable interrupts for the first
5299 * instruction. So, if the last instruction, be it emulated or
5300 * not, left the system with the INT_STI flag enabled, it
5301 * means that the last instruction is an sti. We should not
5302 * leave the flag on in this case. The same goes for mov ss
5303 */
37ccdcbe
PB		 5304 if (int_shadow & mask)
5305 mask = 0;
6addfc42 5306 if (unlikely(int_shadow || mask)) {
95cb2295 5307 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5308 if (!mask)
5309 kvm_make_request(KVM_REQ_EVENT, vcpu);
5310 }
95cb2295
GN		 5311}
5312
ef54bcfe 5313static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5314{
5315 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5316 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5317 return kvm_propagate_fault(vcpu, &ctxt->exception);
5318
5319 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5320 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5321 ctxt->exception.error_code);
54b8486f 5322 else
da9cb575 5323 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5324 return false;
54b8486f
GN		 5325}
5326
8ec4722d
MG		 5327static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5328{
adf52235 5329 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5330 int cs_db, cs_l;
5331
8ec4722d
MG		 5332 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5333
adf52235 5334 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5335 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5336
adf52235
TY		 5337 ctxt->eip = kvm_rip_read(vcpu);
5338 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5339 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5340 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5341 cs_db ? X86EMUL_MODE_PROT32 :
5342 X86EMUL_MODE_PROT16;
a584539b 5343 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5344 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5345 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5346
dd856efa 5347 init_decode_cache(ctxt);
7ae441ea 5348 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5349}
5350
71f9833b 5351int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5352{
9d74191a 5353 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5354 int ret;
5355
5356 init_emulate_ctxt(vcpu);
5357
9dac77fa
AK		 5358 ctxt->op_bytes = 2;
5359 ctxt->ad_bytes = 2;
5360 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5361 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5362
5363 if (ret != X86EMUL_CONTINUE)
5364 return EMULATE_FAIL;
5365
9dac77fa 5366 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5367 kvm_rip_write(vcpu, ctxt->eip);
5368 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5369
5370 if (irq == NMI_VECTOR)
7460fb4a 5371 vcpu->arch.nmi_pending = 0;
63995653
MG		 5372 else
5373 vcpu->arch.interrupt.pending = false;
5374
5375 return EMULATE_DONE;
5376}
5377EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5378
6d77dbfc
GN		 5379static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5380{
fc3a9157
JR		 5381 int r = EMULATE_DONE;
5382
6d77dbfc
GN		 5383 ++vcpu->stat.insn_emulation_fail;
5384 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5385 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5386 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5387 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5388 vcpu->run->internal.ndata = 0;
5389 r = EMULATE_FAIL;
5390 }
6d77dbfc 5391 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5392
5393 return r;
6d77dbfc
GN		 5394}
5395
93c05d3e 5396static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5397 bool write_fault_to_shadow_pgtable,
5398 int emulation_type)
a6f177ef 5399{
95b3cf69 5400 gpa_t gpa = cr2;
ba049e93 5401 kvm_pfn_t pfn;
a6f177ef 5402
991eebf9
GN		 5403 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5404 return false;
5405
95b3cf69
XG		 5406 if (!vcpu->arch.mmu.direct_map) {
5407 /*
5408 * Write permission should be allowed since only
5409 * write access need to be emulated.
5410 */
5411 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5412
95b3cf69
XG		 5413 /*
5414 * If the mapping is invalid in guest, let cpu retry
5415 * it to generate fault.
5416 */
5417 if (gpa == UNMAPPED_GVA)
5418 return true;
5419 }
a6f177ef 5420
8e3d9d06
XG		 5421 /*
5422 * Do not retry the unhandleable instruction if it faults on the
5423 * readonly host memory, otherwise it will goto a infinite loop:
5424 * retry instruction -> write #PF -> emulation fail -> retry
5425 * instruction -> ...
5426 */
5427 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5428
5429 /*
5430 * If the instruction failed on the error pfn, it can not be fixed,
5431 * report the error to userspace.
5432 */
5433 if (is_error_noslot_pfn(pfn))
5434 return false;
5435
5436 kvm_release_pfn_clean(pfn);
5437
5438 /* The instructions are well-emulated on direct mmu. */
5439 if (vcpu->arch.mmu.direct_map) {
5440 unsigned int indirect_shadow_pages;
5441
5442 spin_lock(&vcpu->kvm->mmu_lock);
5443 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5444 spin_unlock(&vcpu->kvm->mmu_lock);
5445
5446 if (indirect_shadow_pages)
5447 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5448
a6f177ef 5449 return true;
8e3d9d06 5450 }
a6f177ef 5451
95b3cf69
XG		 5452 /*
5453 * if emulation was due to access to shadowed page table
5454 * and it failed try to unshadow page and re-enter the
5455 * guest to let CPU execute the instruction.
5456 */
5457 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5458
5459 /*
5460 * If the access faults on its page table, it can not
5461 * be fixed by unprotecting shadow page and it should
5462 * be reported to userspace.
5463 */
5464 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5465}
5466
1cb3f3ae
XG		 5467static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5468 unsigned long cr2, int emulation_type)
5469{
5470 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5471 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5472
5473 last_retry_eip = vcpu->arch.last_retry_eip;
5474 last_retry_addr = vcpu->arch.last_retry_addr;
5475
5476 /*
5477 * If the emulation is caused by #PF and it is non-page_table
5478 * writing instruction, it means the VM-EXIT is caused by shadow
5479 * page protected, we can zap the shadow page and retry this
5480 * instruction directly.
5481 *
5482 * Note: if the guest uses a non-page-table modifying instruction
5483 * on the PDE that points to the instruction, then we will unmap
5484 * the instruction and go to an infinite loop. So, we cache the
5485 * last retried eip and the last fault address, if we meet the eip
5486 * and the address again, we can break out of the potential infinite
5487 * loop.
5488 */
5489 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5490
5491 if (!(emulation_type & EMULTYPE_RETRY))
5492 return false;
5493
5494 if (x86_page_table_writing_insn(ctxt))
5495 return false;
5496
5497 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5498 return false;
5499
5500 vcpu->arch.last_retry_eip = ctxt->eip;
5501 vcpu->arch.last_retry_addr = cr2;
5502
5503 if (!vcpu->arch.mmu.direct_map)
5504 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5505
22368028 5506 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5507
5508 return true;
5509}
5510
716d51ab
GN		 5511static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5512static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5513
64d60670 5514static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5515{
64d60670 5516 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5517 /* This is a good place to trace that we are exiting SMM. */
5518 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5519
c43203ca
PB		 5520 /* Process a latched INIT or SMI, if any. */
5521 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5522 }
699023e2
PB		 5523
5524 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5525}
5526
5527static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5528{
5529 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5530
a584539b 5531 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5532
5533 if (changed & HF_SMM_MASK)
5534 kvm_smm_changed(vcpu);
a584539b
PB		 5535}
5536
4a1e10d5
PB		 5537static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5538 unsigned long *db)
5539{
5540 u32 dr6 = 0;
5541 int i;
5542 u32 enable, rwlen;
5543
5544 enable = dr7;
5545 rwlen = dr7 >> 16;
5546 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5547 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5548 dr6 |= (1 << i);
5549 return dr6;
5550}
5551
c8401dda 5552static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5553{
5554 struct kvm_run *kvm_run = vcpu->run;
5555
c8401dda
PB		 5556 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5557 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5558 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5559 kvm_run->debug.arch.exception = DB_VECTOR;
5560 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5561 *r = EMULATE_USER_EXIT;
5562 } else {
5563 /*
5564 * "Certain debug exceptions may clear bit 0-3. The
5565 * remaining contents of the DR6 register are never
5566 * cleared by the processor".
5567 */
5568 vcpu->arch.dr6 &= ~15;
5569 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5570 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5571 }
5572}
5573
6affcbed
KH		 5574int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5575{
5576 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5577 int r = EMULATE_DONE;
5578
5579 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5580
5581 /*
5582 * rflags is the old, "raw" value of the flags. The new value has
5583 * not been saved yet.
5584 *
5585 * This is correct even for TF set by the guest, because "the
5586 * processor will not generate this exception after the instruction
5587 * that sets the TF flag".
5588 */
5589 if (unlikely(rflags & X86_EFLAGS_TF))
5590 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5591 return r == EMULATE_DONE;
5592}
5593EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5594
4a1e10d5
PB		 5595static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5596{
4a1e10d5
PB		 5597 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5598 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5599 struct kvm_run *kvm_run = vcpu->run;
5600 unsigned long eip = kvm_get_linear_rip(vcpu);
5601 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5602 vcpu->arch.guest_debug_dr7,
5603 vcpu->arch.eff_db);
5604
5605 if (dr6 != 0) {
6f43ed01 5606 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5607 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5608 kvm_run->debug.arch.exception = DB_VECTOR;
5609 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5610 *r = EMULATE_USER_EXIT;
5611 return true;
5612 }
5613 }
5614
4161a569
NA		 5615 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5616 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5617 unsigned long eip = kvm_get_linear_rip(vcpu);
5618 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5619 vcpu->arch.dr7,
5620 vcpu->arch.db);
5621
5622 if (dr6 != 0) {
5623 vcpu->arch.dr6 &= ~15;
6f43ed01 5624 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5625 kvm_queue_exception(vcpu, DB_VECTOR);
5626 *r = EMULATE_DONE;
5627 return true;
5628 }
5629 }
5630
5631 return false;
5632}
5633
51d8b661
AP		 5634int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5635 unsigned long cr2,
dc25e89e
AP		 5636 int emulation_type,
5637 void *insn,
5638 int insn_len)
bbd9b64e 5639{
95cb2295 5640 int r;
9d74191a 5641 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5642 bool writeback = true;
93c05d3e 5643 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5644
93c05d3e
XG		 5645 /*
5646 * Clear write_fault_to_shadow_pgtable here to ensure it is
5647 * never reused.
5648 */
5649 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5650 kvm_clear_exception_queue(vcpu);
8d7d8102 5651
571008da 5652 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5653 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5654
5655 /*
5656 * We will reenter on the same instruction since
5657 * we do not set complete_userspace_io. This does not
5658 * handle watchpoints yet, those would be handled in
5659 * the emulate_ops.
5660 */
5661 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5662 return r;
5663
9d74191a
TY		 5664 ctxt->interruptibility = 0;
5665 ctxt->have_exception = false;
e0ad0b47 5666 ctxt->exception.vector = -1;
9d74191a 5667 ctxt->perm_ok = false;
bbd9b64e 5668
b51e974f 5669 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5670
9d74191a 5671 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5672
e46479f8 5673 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5674 ++vcpu->stat.insn_emulation;
1d2887e2 5675 if (r != EMULATION_OK) {
4005996e
AK		 5676 if (emulation_type & EMULTYPE_TRAP_UD)
5677 return EMULATE_FAIL;
991eebf9
GN		 5678 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5679 emulation_type))
bbd9b64e 5680 return EMULATE_DONE;
6d77dbfc
GN		 5681 if (emulation_type & EMULTYPE_SKIP)
5682 return EMULATE_FAIL;
5683 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5684 }
5685 }
5686
ba8afb6b 5687 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5688 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5689 if (ctxt->eflags & X86_EFLAGS_RF)
5690 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5691 return EMULATE_DONE;
5692 }
5693
1cb3f3ae
XG		 5694 if (retry_instruction(ctxt, cr2, emulation_type))
5695 return EMULATE_DONE;
5696
7ae441ea 5697 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5698 changes registers values during IO operation */
7ae441ea
GN		 5699 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5700 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5701 emulator_invalidate_register_cache(ctxt);
7ae441ea 5702 }
4d2179e1 5703
5cd21917 5704restart:
0f89b207
TL		 5705 /* Save the faulting GPA (cr2) in the address field */
5706 ctxt->exception.address = cr2;
5707
9d74191a 5708 r = x86_emulate_insn(ctxt);
bbd9b64e 5709
775fde86
JR		 5710 if (r == EMULATION_INTERCEPTED)
5711 return EMULATE_DONE;
5712
d2ddd1c4 5713 if (r == EMULATION_FAILED) {
991eebf9
GN		 5714 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5715 emulation_type))
c3cd7ffa
GN		 5716 return EMULATE_DONE;
5717
6d77dbfc 5718 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5719 }
5720
9d74191a 5721 if (ctxt->have_exception) {
d2ddd1c4 5722 r = EMULATE_DONE;
ef54bcfe
PB		 5723 if (inject_emulated_exception(vcpu))
5724 return r;
d2ddd1c4 5725 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5726 if (!vcpu->arch.pio.in) {
5727 /* FIXME: return into emulator if single-stepping. */
3457e419 5728 vcpu->arch.pio.count = 0;
0912c977 5729 } else {
7ae441ea 5730 writeback = false;
716d51ab
GN		 5731 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5732 }
ac0a48c3 5733 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5734 } else if (vcpu->mmio_needed) {
5735 if (!vcpu->mmio_is_write)
5736 writeback = false;
ac0a48c3 5737 r = EMULATE_USER_EXIT;
716d51ab 5738 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5739 } else if (r == EMULATION_RESTART)
5cd21917 5740 goto restart;
d2ddd1c4
GN		 5741 else
5742 r = EMULATE_DONE;
f850e2e6 5743
7ae441ea 5744 if (writeback) {
6addfc42 5745 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5746 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5747 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5748 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 5749 if (r == EMULATE_DONE &&
5750 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
5751 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 5752 if (!ctxt->have_exception ||
5753 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5754 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5755
5756 /*
5757 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5758 * do nothing, and it will be requested again as soon as
5759 * the shadow expires. But we still need to check here,
5760 * because POPF has no interrupt shadow.
5761 */
5762 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5763 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5764 } else
5765 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5766
5767 return r;
de7d789a 5768}
51d8b661 5769EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5770
cf8f70bf 5771int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5772{
cf8f70bf 5773 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5774 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5775 size, port, &val, 1);
cf8f70bf 5776 /* do not return to emulator after return from userspace */
7972995b 5777 vcpu->arch.pio.count = 0;
de7d789a
CO		 5778 return ret;
5779}
cf8f70bf 5780EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5781
8370c3d0
TL		 5782static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5783{
5784 unsigned long val;
5785
5786 /* We should only ever be called with arch.pio.count equal to 1 */
5787 BUG_ON(vcpu->arch.pio.count != 1);
5788
5789 /* For size less than 4 we merge, else we zero extend */
5790 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5791 : 0;
5792
5793 /*
5794 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5795 * the copy and tracing
5796 */
5797 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5798 vcpu->arch.pio.port, &val, 1);
5799 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5800
5801 return 1;
5802}
5803
5804int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5805{
5806 unsigned long val;
5807 int ret;
5808
5809 /* For size less than 4 we merge, else we zero extend */
5810 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5811
5812 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5813 &val, 1);
5814 if (ret) {
5815 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5816 return ret;
5817 }
5818
5819 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5820
5821 return 0;
5822}
5823EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5824
251a5fd6 5825static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5826{
0a3aee0d 5827 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5828 return 0;
8cfdc000
ZA		 5829}
5830
5831static void tsc_khz_changed(void *data)
c8076604 5832{
8cfdc000
ZA		 5833 struct cpufreq_freqs *freq = data;
5834 unsigned long khz = 0;
5835
5836 if (data)
5837 khz = freq->new;
5838 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5839 khz = cpufreq_quick_get(raw_smp_processor_id());
5840 if (!khz)
5841 khz = tsc_khz;
0a3aee0d 5842 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5843}
5844
c8076604
GH		 5845static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5846 void *data)
5847{
5848 struct cpufreq_freqs *freq = data;
5849 struct kvm *kvm;
5850 struct kvm_vcpu *vcpu;
5851 int i, send_ipi = 0;
5852
8cfdc000
ZA		 5853 /*
5854 * We allow guests to temporarily run on slowing clocks,
5855 * provided we notify them after, or to run on accelerating
5856 * clocks, provided we notify them before. Thus time never
5857 * goes backwards.
5858 *
5859 * However, we have a problem. We can't atomically update
5860 * the frequency of a given CPU from this function; it is
5861 * merely a notifier, which can be called from any CPU.
5862 * Changing the TSC frequency at arbitrary points in time
5863 * requires a recomputation of local variables related to
5864 * the TSC for each VCPU. We must flag these local variables
5865 * to be updated and be sure the update takes place with the
5866 * new frequency before any guests proceed.
5867 *
5868 * Unfortunately, the combination of hotplug CPU and frequency
5869 * change creates an intractable locking scenario; the order
5870 * of when these callouts happen is undefined with respect to
5871 * CPU hotplug, and they can race with each other. As such,
5872 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5873 * undefined; you can actually have a CPU frequency change take
5874 * place in between the computation of X and the setting of the
5875 * variable. To protect against this problem, all updates of
5876 * the per_cpu tsc_khz variable are done in an interrupt
5877 * protected IPI, and all callers wishing to update the value
5878 * must wait for a synchronous IPI to complete (which is trivial
5879 * if the caller is on the CPU already). This establishes the
5880 * necessary total order on variable updates.
5881 *
5882 * Note that because a guest time update may take place
5883 * anytime after the setting of the VCPU's request bit, the
5884 * correct TSC value must be set before the request. However,
5885 * to ensure the update actually makes it to any guest which
5886 * starts running in hardware virtualization between the set
5887 * and the acquisition of the spinlock, we must also ping the
5888 * CPU after setting the request bit.
5889 *
5890 */
5891
c8076604
GH		 5892 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5893 return 0;
5894 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5895 return 0;
8cfdc000
ZA		 5896
5897 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5898
2f303b74 5899 spin_lock(&kvm_lock);
c8076604 5900 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5901 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5902 if (vcpu->cpu != freq->cpu)
5903 continue;
c285545f 5904 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5905 if (vcpu->cpu != smp_processor_id())
8cfdc000 5906 send_ipi = 1;
c8076604
GH		 5907 }
5908 }
2f303b74 5909 spin_unlock(&kvm_lock);
c8076604
GH		 5910
5911 if (freq->old < freq->new && send_ipi) {
5912 /*
5913 * We upscale the frequency. Must make the guest
5914 * doesn't see old kvmclock values while running with
5915 * the new frequency, otherwise we risk the guest sees
5916 * time go backwards.
5917 *
5918 * In case we update the frequency for another cpu
5919 * (which might be in guest context) send an interrupt
5920 * to kick the cpu out of guest context. Next time
5921 * guest context is entered kvmclock will be updated,
5922 * so the guest will not see stale values.
5923 */
8cfdc000 5924 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5925 }
5926 return 0;
5927}
5928
5929static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5930 .notifier_call = kvmclock_cpufreq_notifier
5931};
5932
251a5fd6 5933static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 5934{
251a5fd6
SAS		 5935 tsc_khz_changed(NULL);
5936 return 0;
8cfdc000
ZA		 5937}
5938
b820cc0c
ZA		 5939static void kvm_timer_init(void)
5940{
c285545f 5941 max_tsc_khz = tsc_khz;
460dd42e 5942
b820cc0c 5943 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5944#ifdef CONFIG_CPU_FREQ
5945 struct cpufreq_policy policy;
758f588d
BP		 5946 int cpu;
5947
c285545f 5948 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5949 cpu = get_cpu();
5950 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5951 if (policy.cpuinfo.max_freq)
5952 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5953 put_cpu();
c285545f 5954#endif
b820cc0c
ZA		 5955 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5956 CPUFREQ_TRANSITION_NOTIFIER);
5957 }
c285545f 5958 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 5959
73c1b41e 5960 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 5961 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 5962}
5963
ff9d07a0
ZY		 5964static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5965
f5132b01 5966int kvm_is_in_guest(void)
ff9d07a0 5967{
086c9855 5968 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5969}
5970
5971static int kvm_is_user_mode(void)
5972{
5973 int user_mode = 3;
dcf46b94 5974
086c9855
AS		 5975 if (__this_cpu_read(current_vcpu))
5976 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5977
ff9d07a0
ZY		 5978 return user_mode != 0;
5979}
5980
5981static unsigned long kvm_get_guest_ip(void)
5982{
5983 unsigned long ip = 0;
dcf46b94 5984
086c9855
AS		 5985 if (__this_cpu_read(current_vcpu))
5986 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5987
ff9d07a0
ZY		 5988 return ip;
5989}
5990
5991static struct perf_guest_info_callbacks kvm_guest_cbs = {
5992 .is_in_guest = kvm_is_in_guest,
5993 .is_user_mode = kvm_is_user_mode,
5994 .get_guest_ip = kvm_get_guest_ip,
5995};
5996
5997void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5998{
086c9855 5999 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 6000}
6001EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
6002
6003void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6004{
086c9855 6005 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 6006}
6007EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6008
ce88decf
XG		 6009static void kvm_set_mmio_spte_mask(void)
6010{
6011 u64 mask;
6012 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6013
6014 /*
6015 * Set the reserved bits and the present bit of an paging-structure
6016 * entry to generate page fault with PFER.RSV = 1.
6017 */
885032b9 6018 /* Mask the reserved physical address bits. */
d1431483 6019 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6020
885032b9 6021 /* Set the present bit. */
ce88decf
XG		 6022 mask |= 1ull;
6023
6024#ifdef CONFIG_X86_64
6025 /*
6026 * If reserved bit is not supported, clear the present bit to disable
6027 * mmio page fault.
6028 */
6029 if (maxphyaddr == 52)
6030 mask &= ~1ull;
6031#endif
6032
dcdca5fe 6033 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6034}
6035
16e8d74d
MT		 6036#ifdef CONFIG_X86_64
6037static void pvclock_gtod_update_fn(struct work_struct *work)
6038{
d828199e
MT		 6039 struct kvm *kvm;
6040
6041 struct kvm_vcpu *vcpu;
6042 int i;
6043
2f303b74 6044 spin_lock(&kvm_lock);
d828199e
MT		 6045 list_for_each_entry(kvm, &vm_list, vm_list)
6046 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6047 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6048 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6049 spin_unlock(&kvm_lock);
16e8d74d
MT		 6050}
6051
6052static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6053
6054/*
6055 * Notification about pvclock gtod data update.
6056 */
6057static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6058 void *priv)
6059{
6060 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6061 struct timekeeper *tk = priv;
6062
6063 update_pvclock_gtod(tk);
6064
6065 /* disable master clock if host does not trust, or does not
6066 * use, TSC clocksource
6067 */
6068 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6069 atomic_read(&kvm_guest_has_master_clock) != 0)
6070 queue_work(system_long_wq, &pvclock_gtod_work);
6071
6072 return 0;
6073}
6074
6075static struct notifier_block pvclock_gtod_notifier = {
6076 .notifier_call = pvclock_gtod_notify,
6077};
6078#endif
6079
f8c16bba 6080int kvm_arch_init(void *opaque)
043405e1 6081{
b820cc0c 6082 int r;
6b61edf7 6083 struct kvm_x86_ops *ops = opaque;
f8c16bba 6084
f8c16bba
ZX		 6085 if (kvm_x86_ops) {
6086 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6087 r = -EEXIST;
6088 goto out;
f8c16bba
ZX		 6089 }
6090
6091 if (!ops->cpu_has_kvm_support()) {
6092 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6093 r = -EOPNOTSUPP;
6094 goto out;
f8c16bba
ZX		 6095 }
6096 if (ops->disabled_by_bios()) {
6097 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6098 r = -EOPNOTSUPP;
6099 goto out;
f8c16bba
ZX		 6100 }
6101
013f6a5d
MT		 6102 r = -ENOMEM;
6103 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6104 if (!shared_msrs) {
6105 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6106 goto out;
6107 }
6108
97db56ce
AK		 6109 r = kvm_mmu_module_init();
6110 if (r)
013f6a5d 6111 goto out_free_percpu;
97db56ce 6112
ce88decf 6113 kvm_set_mmio_spte_mask();
97db56ce 6114
f8c16bba 6115 kvm_x86_ops = ops;
920c8377 6116
7b52345e 6117 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6118 PT_DIRTY_MASK, PT64_NX_MASK, 0,
f160c7b7 6119 PT_PRESENT_MASK, 0);
b820cc0c 6120 kvm_timer_init();
c8076604 6121
ff9d07a0
ZY		 6122 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6123
d366bf7e 6124 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6125 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6126
c5cc421b 6127 kvm_lapic_init();
16e8d74d
MT		 6128#ifdef CONFIG_X86_64
6129 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6130#endif
6131
f8c16bba 6132 return 0;
56c6d28a 6133
013f6a5d
MT		 6134out_free_percpu:
6135 free_percpu(shared_msrs);
56c6d28a 6136out:
56c6d28a 6137 return r;
043405e1 6138}
8776e519 6139
f8c16bba
ZX		 6140void kvm_arch_exit(void)
6141{
cef84c30 6142 kvm_lapic_exit();
ff9d07a0
ZY		 6143 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6144
888d256e
JK		 6145 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6146 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6147 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6148 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6149#ifdef CONFIG_X86_64
6150 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6151#endif
f8c16bba 6152 kvm_x86_ops = NULL;
56c6d28a 6153 kvm_mmu_module_exit();
013f6a5d 6154 free_percpu(shared_msrs);
56c6d28a 6155}
f8c16bba 6156
5cb56059 6157int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6158{
6159 ++vcpu->stat.halt_exits;
35754c98 6160 if (lapic_in_kernel(vcpu)) {
a4535290 6161 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6162 return 1;
6163 } else {
6164 vcpu->run->exit_reason = KVM_EXIT_HLT;
6165 return 0;
6166 }
6167}
5cb56059
JS		 6168EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6169
6170int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6171{
6affcbed
KH		 6172 int ret = kvm_skip_emulated_instruction(vcpu);
6173 /*
6174 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6175 * KVM_EXIT_DEBUG here.
6176 */
6177 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6178}
8776e519
HB		 6179EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6180
8ef81a9a 6181#ifdef CONFIG_X86_64
55dd00a7
MT		 6182static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6183 unsigned long clock_type)
6184{
6185 struct kvm_clock_pairing clock_pairing;
6186 struct timespec ts;
80fbd89c 6187 u64 cycle;
55dd00a7
MT		 6188 int ret;
6189
6190 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6191 return -KVM_EOPNOTSUPP;
6192
6193 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6194 return -KVM_EOPNOTSUPP;
6195
6196 clock_pairing.sec = ts.tv_sec;
6197 clock_pairing.nsec = ts.tv_nsec;
6198 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6199 clock_pairing.flags = 0;
6200
6201 ret = 0;
6202 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6203 sizeof(struct kvm_clock_pairing)))
6204 ret = -KVM_EFAULT;
6205
6206 return ret;
6207}
8ef81a9a 6208#endif
55dd00a7 6209
6aef266c
SV		 6210/*
6211 * kvm_pv_kick_cpu_op: Kick a vcpu.
6212 *
6213 * @apicid - apicid of vcpu to be kicked.
6214 */
6215static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6216{
24d2166b 6217 struct kvm_lapic_irq lapic_irq;
6aef266c 6218
24d2166b
R		 6219 lapic_irq.shorthand = 0;
6220 lapic_irq.dest_mode = 0;
ebd28fcb 6221 lapic_irq.level = 0;
24d2166b 6222 lapic_irq.dest_id = apicid;
93bbf0b8 6223 lapic_irq.msi_redir_hint = false;
6aef266c 6224
24d2166b 6225 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6226 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6227}
6228
d62caabb
AS		 6229void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6230{
6231 vcpu->arch.apicv_active = false;
6232 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6233}
6234
8776e519
HB		 6235int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6236{
6237 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6238 int op_64_bit, r;
8776e519 6239
6affcbed 6240 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6241
55cd8e5a
GN		 6242 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6243 return kvm_hv_hypercall(vcpu);
6244
5fdbf976
MT		 6245 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6246 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6247 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6248 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6249 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6250
229456fc 6251 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6252
a449c7aa
NA		 6253 op_64_bit = is_64_bit_mode(vcpu);
6254 if (!op_64_bit) {
8776e519
HB		 6255 nr &= 0xFFFFFFFF;
6256 a0 &= 0xFFFFFFFF;
6257 a1 &= 0xFFFFFFFF;
6258 a2 &= 0xFFFFFFFF;
6259 a3 &= 0xFFFFFFFF;
6260 }
6261
07708c4a
JK		 6262 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6263 ret = -KVM_EPERM;
6264 goto out;
6265 }
6266
8776e519 6267 switch (nr) {
b93463aa
AK		 6268 case KVM_HC_VAPIC_POLL_IRQ:
6269 ret = 0;
6270 break;
6aef266c
SV		 6271 case KVM_HC_KICK_CPU:
6272 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6273 ret = 0;
6274 break;
8ef81a9a 6275#ifdef CONFIG_X86_64
55dd00a7
MT		 6276 case KVM_HC_CLOCK_PAIRING:
6277 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6278 break;
8ef81a9a 6279#endif
8776e519
HB		 6280 default:
6281 ret = -KVM_ENOSYS;
6282 break;
6283 }
07708c4a 6284out:
a449c7aa
NA		 6285 if (!op_64_bit)
6286 ret = (u32)ret;
5fdbf976 6287 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6288 ++vcpu->stat.hypercalls;
2f333bcb 6289 return r;
8776e519
HB		 6290}
6291EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6292
b6785def 6293static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6294{
d6aa1000 6295 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6296 char instruction[3];
5fdbf976 6297 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6298
8776e519 6299 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6300
ce2e852e
DV		 6301 return emulator_write_emulated(ctxt, rip, instruction, 3,
6302 &ctxt->exception);
8776e519
HB		 6303}
6304
851ba692 6305static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6306{
782d422b
MG		 6307 return vcpu->run->request_interrupt_window &&
6308 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6309}
6310
851ba692 6311static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6312{
851ba692
AK		 6313 struct kvm_run *kvm_run = vcpu->run;
6314
91586a3b 6315 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6316 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6317 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6318 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6319 kvm_run->ready_for_interrupt_injection =
6320 pic_in_kernel(vcpu->kvm) ||
782d422b 6321 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6322}
6323
95ba8273
GN		 6324static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6325{
6326 int max_irr, tpr;
6327
6328 if (!kvm_x86_ops->update_cr8_intercept)
6329 return;
6330
bce87cce 6331 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6332 return;
6333
d62caabb
AS		 6334 if (vcpu->arch.apicv_active)
6335 return;
6336
8db3baa2
GN		 6337 if (!vcpu->arch.apic->vapic_addr)
6338 max_irr = kvm_lapic_find_highest_irr(vcpu);
6339 else
6340 max_irr = -1;
95ba8273
GN		 6341
6342 if (max_irr != -1)
6343 max_irr >>= 4;
6344
6345 tpr = kvm_lapic_get_cr8(vcpu);
6346
6347 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6348}
6349
b6b8a145 6350static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6351{
b6b8a145
JK		 6352 int r;
6353
95ba8273 6354 /* try to reinject previous events if any */
b59bb7bd 6355 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6356 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6357 vcpu->arch.exception.has_error_code,
6358 vcpu->arch.exception.error_code);
d6e8c854
NA		 6359
6360 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6361 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6362 X86_EFLAGS_RF);
6363
6bdf0662
NA		 6364 if (vcpu->arch.exception.nr == DB_VECTOR &&
6365 (vcpu->arch.dr7 & DR7_GD)) {
6366 vcpu->arch.dr7 &= ~DR7_GD;
6367 kvm_update_dr7(vcpu);
6368 }
6369
cfcd20e5 6370 kvm_x86_ops->queue_exception(vcpu);
b6b8a145 6371 return 0;
b59bb7bd
GN		 6372 }
6373
95ba8273
GN		 6374 if (vcpu->arch.nmi_injected) {
6375 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6376 return 0;
95ba8273
GN		 6377 }
6378
6379 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6380 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6381 return 0;
6382 }
6383
6384 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6385 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6386 if (r != 0)
6387 return r;
95ba8273
GN		 6388 }
6389
6390 /* try to inject new event if pending */
c43203ca
PB		 6391 if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
6392 vcpu->arch.smi_pending = false;
ee2cd4b7 6393 enter_smm(vcpu);
c43203ca 6394 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6395 --vcpu->arch.nmi_pending;
6396 vcpu->arch.nmi_injected = true;
6397 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6398 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6399 /*
6400 * Because interrupts can be injected asynchronously, we are
6401 * calling check_nested_events again here to avoid a race condition.
6402 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6403 * proposal and current concerns. Perhaps we should be setting
6404 * KVM_REQ_EVENT only on certain events and not unconditionally?
6405 */
6406 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6407 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6408 if (r != 0)
6409 return r;
6410 }
95ba8273 6411 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6412 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6413 false);
6414 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6415 }
6416 }
ee2cd4b7 6417
b6b8a145 6418 return 0;
95ba8273
GN		 6419}
6420
7460fb4a
AK		 6421static void process_nmi(struct kvm_vcpu *vcpu)
6422{
6423 unsigned limit = 2;
6424
6425 /*
6426 * x86 is limited to one NMI running, and one NMI pending after it.
6427 * If an NMI is already in progress, limit further NMIs to just one.
6428 * Otherwise, allow two (and we'll inject the first one immediately).
6429 */
6430 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6431 limit = 1;
6432
6433 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6434 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6435 kvm_make_request(KVM_REQ_EVENT, vcpu);
6436}
6437
660a5d51
PB		 6438#define put_smstate(type, buf, offset, val) \
6439 *(type *)((buf) + (offset) - 0x7e00) = val
6440
ee2cd4b7 6441static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6442{
6443 u32 flags = 0;
6444 flags |= seg->g << 23;
6445 flags |= seg->db << 22;
6446 flags |= seg->l << 21;
6447 flags |= seg->avl << 20;
6448 flags |= seg->present << 15;
6449 flags |= seg->dpl << 13;
6450 flags |= seg->s << 12;
6451 flags |= seg->type << 8;
6452 return flags;
6453}
6454
ee2cd4b7 6455static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6456{
6457 struct kvm_segment seg;
6458 int offset;
6459
6460 kvm_get_segment(vcpu, &seg, n);
6461 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6462
6463 if (n < 3)
6464 offset = 0x7f84 + n * 12;
6465 else
6466 offset = 0x7f2c + (n - 3) * 12;
6467
6468 put_smstate(u32, buf, offset + 8, seg.base);
6469 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6470 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6471}
6472
efbb288a 6473#ifdef CONFIG_X86_64
ee2cd4b7 6474static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6475{
6476 struct kvm_segment seg;
6477 int offset;
6478 u16 flags;
6479
6480 kvm_get_segment(vcpu, &seg, n);
6481 offset = 0x7e00 + n * 16;
6482
ee2cd4b7 6483 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6484 put_smstate(u16, buf, offset, seg.selector);
6485 put_smstate(u16, buf, offset + 2, flags);
6486 put_smstate(u32, buf, offset + 4, seg.limit);
6487 put_smstate(u64, buf, offset + 8, seg.base);
6488}
efbb288a 6489#endif
660a5d51 6490
ee2cd4b7 6491static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6492{
6493 struct desc_ptr dt;
6494 struct kvm_segment seg;
6495 unsigned long val;
6496 int i;
6497
6498 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6499 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6500 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6501 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6502
6503 for (i = 0; i < 8; i++)
6504 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6505
6506 kvm_get_dr(vcpu, 6, &val);
6507 put_smstate(u32, buf, 0x7fcc, (u32)val);
6508 kvm_get_dr(vcpu, 7, &val);
6509 put_smstate(u32, buf, 0x7fc8, (u32)val);
6510
6511 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6512 put_smstate(u32, buf, 0x7fc4, seg.selector);
6513 put_smstate(u32, buf, 0x7f64, seg.base);
6514 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6515 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6516
6517 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6518 put_smstate(u32, buf, 0x7fc0, seg.selector);
6519 put_smstate(u32, buf, 0x7f80, seg.base);
6520 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6521 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6522
6523 kvm_x86_ops->get_gdt(vcpu, &dt);
6524 put_smstate(u32, buf, 0x7f74, dt.address);
6525 put_smstate(u32, buf, 0x7f70, dt.size);
6526
6527 kvm_x86_ops->get_idt(vcpu, &dt);
6528 put_smstate(u32, buf, 0x7f58, dt.address);
6529 put_smstate(u32, buf, 0x7f54, dt.size);
6530
6531 for (i = 0; i < 6; i++)
ee2cd4b7 6532 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6533
6534 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6535
6536 /* revision id */
6537 put_smstate(u32, buf, 0x7efc, 0x00020000);
6538 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6539}
6540
ee2cd4b7 6541static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6542{
6543#ifdef CONFIG_X86_64
6544 struct desc_ptr dt;
6545 struct kvm_segment seg;
6546 unsigned long val;
6547 int i;
6548
6549 for (i = 0; i < 16; i++)
6550 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6551
6552 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6553 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6554
6555 kvm_get_dr(vcpu, 6, &val);
6556 put_smstate(u64, buf, 0x7f68, val);
6557 kvm_get_dr(vcpu, 7, &val);
6558 put_smstate(u64, buf, 0x7f60, val);
6559
6560 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6561 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6562 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6563
6564 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6565
6566 /* revision id */
6567 put_smstate(u32, buf, 0x7efc, 0x00020064);
6568
6569 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6570
6571 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6572 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6573 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6574 put_smstate(u32, buf, 0x7e94, seg.limit);
6575 put_smstate(u64, buf, 0x7e98, seg.base);
6576
6577 kvm_x86_ops->get_idt(vcpu, &dt);
6578 put_smstate(u32, buf, 0x7e84, dt.size);
6579 put_smstate(u64, buf, 0x7e88, dt.address);
6580
6581 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6582 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6583 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6584 put_smstate(u32, buf, 0x7e74, seg.limit);
6585 put_smstate(u64, buf, 0x7e78, seg.base);
6586
6587 kvm_x86_ops->get_gdt(vcpu, &dt);
6588 put_smstate(u32, buf, 0x7e64, dt.size);
6589 put_smstate(u64, buf, 0x7e68, dt.address);
6590
6591 for (i = 0; i < 6; i++)
ee2cd4b7 6592 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6593#else
6594 WARN_ON_ONCE(1);
6595#endif
6596}
6597
ee2cd4b7 6598static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6599{
660a5d51 6600 struct kvm_segment cs, ds;
18c3626e 6601 struct desc_ptr dt;
660a5d51
PB		 6602 char buf[512];
6603 u32 cr0;
6604
660a5d51
PB		 6605 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6606 vcpu->arch.hflags |= HF_SMM_MASK;
6607 memset(buf, 0, 512);
6608 if (guest_cpuid_has_longmode(vcpu))
ee2cd4b7 6609 enter_smm_save_state_64(vcpu, buf);
660a5d51 6610 else
ee2cd4b7 6611 enter_smm_save_state_32(vcpu, buf);
660a5d51 6612
54bf36aa 6613 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6614
6615 if (kvm_x86_ops->get_nmi_mask(vcpu))
6616 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6617 else
6618 kvm_x86_ops->set_nmi_mask(vcpu, true);
6619
6620 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6621 kvm_rip_write(vcpu, 0x8000);
6622
6623 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6624 kvm_x86_ops->set_cr0(vcpu, cr0);
6625 vcpu->arch.cr0 = cr0;
6626
6627 kvm_x86_ops->set_cr4(vcpu, 0);
6628
18c3626e
PB		 6629 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6630 dt.address = dt.size = 0;
6631 kvm_x86_ops->set_idt(vcpu, &dt);
6632
660a5d51
PB		 6633 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6634
6635 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6636 cs.base = vcpu->arch.smbase;
6637
6638 ds.selector = 0;
6639 ds.base = 0;
6640
6641 cs.limit = ds.limit = 0xffffffff;
6642 cs.type = ds.type = 0x3;
6643 cs.dpl = ds.dpl = 0;
6644 cs.db = ds.db = 0;
6645 cs.s = ds.s = 1;
6646 cs.l = ds.l = 0;
6647 cs.g = ds.g = 1;
6648 cs.avl = ds.avl = 0;
6649 cs.present = ds.present = 1;
6650 cs.unusable = ds.unusable = 0;
6651 cs.padding = ds.padding = 0;
6652
6653 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6654 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6655 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6656 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6657 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6658 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6659
6660 if (guest_cpuid_has_longmode(vcpu))
6661 kvm_x86_ops->set_efer(vcpu, 0);
6662
6663 kvm_update_cpuid(vcpu);
6664 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6665}
6666
ee2cd4b7 6667static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6668{
6669 vcpu->arch.smi_pending = true;
6670 kvm_make_request(KVM_REQ_EVENT, vcpu);
6671}
6672
2860c4b1
PB		 6673void kvm_make_scan_ioapic_request(struct kvm *kvm)
6674{
6675 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6676}
6677
3d81bc7e 6678static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6679{
5c919412
AS		 6680 u64 eoi_exit_bitmap[4];
6681
3d81bc7e
YZ		 6682 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6683 return;
c7c9c56c 6684
6308630b 6685 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6686
b053b2ae 6687 if (irqchip_split(vcpu->kvm))
6308630b 6688 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6689 else {
76dfafd5 6690 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb 6691 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6692 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6693 }
5c919412
AS		 6694 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6695 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6696 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6697}
6698
a70656b6
RK		 6699static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6700{
6701 ++vcpu->stat.tlb_flush;
6702 kvm_x86_ops->tlb_flush(vcpu);
6703}
6704
4256f43f
TC		 6705void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6706{
c24ae0dc
TC		 6707 struct page *page = NULL;
6708
35754c98 6709 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6710 return;
6711
4256f43f
TC		 6712 if (!kvm_x86_ops->set_apic_access_page_addr)
6713 return;
6714
c24ae0dc 6715 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6716 if (is_error_page(page))
6717 return;
c24ae0dc
TC		 6718 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6719
6720 /*
6721 * Do not pin apic access page in memory, the MMU notifier
6722 * will call us again if it is migrated or swapped out.
6723 */
6724 put_page(page);
4256f43f
TC		 6725}
6726EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6727
fe71557a
TC		 6728void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6729 unsigned long address)
6730{
c24ae0dc
TC		 6731 /*
6732 * The physical address of apic access page is stored in the VMCS.
6733 * Update it when it becomes invalid.
6734 */
6735 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6736 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6737}
6738
9357d939 6739/*
362c698f 6740 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6741 * exiting to the userspace. Otherwise, the value will be returned to the
6742 * userspace.
6743 */
851ba692 6744static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6745{
6746 int r;
62a193ed
MG		 6747 bool req_int_win =
6748 dm_request_for_irq_injection(vcpu) &&
6749 kvm_cpu_accept_dm_intr(vcpu);
6750
730dca42 6751 bool req_immediate_exit = false;
b6c7a5dc 6752
2fa6e1e1 6753 if (kvm_request_pending(vcpu)) {
a8eeb04a 6754 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6755 kvm_mmu_unload(vcpu);
a8eeb04a 6756 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6757 __kvm_migrate_timers(vcpu);
d828199e
MT		 6758 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6759 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6760 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6761 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6762 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6763 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6764 if (unlikely(r))
6765 goto out;
6766 }
a8eeb04a 6767 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6768 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6769 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6770 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6771 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6772 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6773 r = 0;
6774 goto out;
6775 }
a8eeb04a 6776 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6777 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6778 r = 0;
6779 goto out;
6780 }
af585b92
GN		 6781 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6782 /* Page is swapped out. Do synthetic halt */
6783 vcpu->arch.apf.halted = true;
6784 r = 1;
6785 goto out;
6786 }
c9aaa895
GC		 6787 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6788 record_steal_time(vcpu);
64d60670
PB		 6789 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6790 process_smi(vcpu);
7460fb4a
AK		 6791 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6792 process_nmi(vcpu);
f5132b01 6793 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6794 kvm_pmu_handle_event(vcpu);
f5132b01 6795 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6796 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6797 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6798 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6799 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6800 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6801 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6802 vcpu->run->eoi.vector =
6803 vcpu->arch.pending_ioapic_eoi;
6804 r = 0;
6805 goto out;
6806 }
6807 }
3d81bc7e
YZ		 6808 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6809 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6810 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6811 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6812 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6813 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6814 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6815 r = 0;
6816 goto out;
6817 }
e516cebb
AS		 6818 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6819 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6820 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6821 r = 0;
6822 goto out;
6823 }
db397571
AS		 6824 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6825 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6826 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6827 r = 0;
6828 goto out;
6829 }
f3b138c5
AS		 6830
6831 /*
6832 * KVM_REQ_HV_STIMER has to be processed after
6833 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6834 * depend on the guest clock being up-to-date
6835 */
1f4b34f8
AS		 6836 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6837 kvm_hv_process_stimers(vcpu);
2f52d58c 6838 }
b93463aa 6839
b463a6f7 6840 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 6841 ++vcpu->stat.req_event;
66450a21
JK		 6842 kvm_apic_accept_events(vcpu);
6843 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6844 r = 1;
6845 goto out;
6846 }
6847
b6b8a145
JK		 6848 if (inject_pending_event(vcpu, req_int_win) != 0)
6849 req_immediate_exit = true;
321c5658 6850 else {
c43203ca
PB		 6851 /* Enable NMI/IRQ window open exits if needed.
6852 *
6853 * SMIs have two cases: 1) they can be nested, and
6854 * then there is nothing to do here because RSM will
6855 * cause a vmexit anyway; 2) or the SMI can be pending
6856 * because inject_pending_event has completed the
6857 * injection of an IRQ or NMI from the previous vmexit,
6858 * and then we request an immediate exit to inject the SMI.
6859 */
6860 if (vcpu->arch.smi_pending && !is_smm(vcpu))
6861 req_immediate_exit = true;
321c5658
YS		 6862 if (vcpu->arch.nmi_pending)
6863 kvm_x86_ops->enable_nmi_window(vcpu);
6864 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6865 kvm_x86_ops->enable_irq_window(vcpu);
6866 }
b463a6f7
AK		 6867
6868 if (kvm_lapic_enabled(vcpu)) {
6869 update_cr8_intercept(vcpu);
6870 kvm_lapic_sync_to_vapic(vcpu);
6871 }
6872 }
6873
d8368af8
AK		 6874 r = kvm_mmu_reload(vcpu);
6875 if (unlikely(r)) {
d905c069 6876 goto cancel_injection;
d8368af8
AK		 6877 }
6878
b6c7a5dc
HB		 6879 preempt_disable();
6880
6881 kvm_x86_ops->prepare_guest_switch(vcpu);
bd7e5b08 6882 kvm_load_guest_fpu(vcpu);
b95234c8
PB		 6883
6884 /*
6885 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
6886 * IPI are then delayed after guest entry, which ensures that they
6887 * result in virtual interrupt delivery.
6888 */
6889 local_irq_disable();
6b7e2d09
XG		 6890 vcpu->mode = IN_GUEST_MODE;
6891
01b71917
MT		 6892 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6893
0f127d12 6894 /*
b95234c8 6895 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 6896 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 6897 *
6898 * 2) For APICv, we should set ->mode before checking PIR.ON. This
6899 * pairs with the memory barrier implicit in pi_test_and_set_on
6900 * (see vmx_deliver_posted_interrupt).
6901 *
6902 * 3) This also orders the write to mode from any reads to the page
6903 * tables done while the VCPU is running. Please see the comment
6904 * in kvm_flush_remote_tlbs.
6b7e2d09 6905 */
01b71917 6906 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6907
b95234c8
PB		 6908 /*
6909 * This handles the case where a posted interrupt was
6910 * notified with kvm_vcpu_kick.
6911 */
6912 if (kvm_lapic_enabled(vcpu)) {
6913 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6914 kvm_x86_ops->sync_pir_to_irr(vcpu);
6915 }
32f88400 6916
2fa6e1e1 6917 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 6918 || need_resched() || signal_pending(current)) {
6b7e2d09 6919 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6920 smp_wmb();
6c142801
AK		 6921 local_irq_enable();
6922 preempt_enable();
01b71917 6923 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6924 r = 1;
d905c069 6925 goto cancel_injection;
6c142801
AK		 6926 }
6927
fc5b7f3b
DM		 6928 kvm_load_guest_xcr0(vcpu);
6929
c43203ca
PB		 6930 if (req_immediate_exit) {
6931 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 6932 smp_send_reschedule(vcpu->cpu);
c43203ca 6933 }
d6185f20 6934
8b89fe1f
PB		 6935 trace_kvm_entry(vcpu->vcpu_id);
6936 wait_lapic_expire(vcpu);
6edaa530 6937 guest_enter_irqoff();
b6c7a5dc 6938
42dbaa5a 6939 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6940 set_debugreg(0, 7);
6941 set_debugreg(vcpu->arch.eff_db[0], 0);
6942 set_debugreg(vcpu->arch.eff_db[1], 1);
6943 set_debugreg(vcpu->arch.eff_db[2], 2);
6944 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6945 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6946 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6947 }
b6c7a5dc 6948
851ba692 6949 kvm_x86_ops->run(vcpu);
b6c7a5dc 6950
c77fb5fe
PB		 6951 /*
6952 * Do this here before restoring debug registers on the host. And
6953 * since we do this before handling the vmexit, a DR access vmexit
6954 * can (a) read the correct value of the debug registers, (b) set
6955 * KVM_DEBUGREG_WONT_EXIT again.
6956 */
6957 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 6958 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6959 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 6960 kvm_update_dr0123(vcpu);
6961 kvm_update_dr6(vcpu);
6962 kvm_update_dr7(vcpu);
6963 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 6964 }
6965
24f1e32c
FW		 6966 /*
6967 * If the guest has used debug registers, at least dr7
6968 * will be disabled while returning to the host.
6969 * If we don't have active breakpoints in the host, we don't
6970 * care about the messed up debug address registers. But if
6971 * we have some of them active, restore the old state.
6972 */
59d8eb53 6973 if (hw_breakpoint_active())
24f1e32c 6974 hw_breakpoint_restore();
42dbaa5a 6975
4ba76538 6976 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6977
6b7e2d09 6978 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6979 smp_wmb();
a547c6db 6980
fc5b7f3b
DM		 6981 kvm_put_guest_xcr0(vcpu);
6982
a547c6db 6983 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6984
6985 ++vcpu->stat.exits;
6986
f2485b3e 6987 guest_exit_irqoff();
b6c7a5dc 6988
f2485b3e 6989 local_irq_enable();
b6c7a5dc
HB		 6990 preempt_enable();
6991
f656ce01 6992 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6993
b6c7a5dc
HB		 6994 /*
6995 * Profile KVM exit RIPs:
6996 */
6997 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6998 unsigned long rip = kvm_rip_read(vcpu);
6999 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7000 }
7001
cc578287
ZA		 7002 if (unlikely(vcpu->arch.tsc_always_catchup))
7003 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7004
5cfb1d5a
MT		 7005 if (vcpu->arch.apic_attention)
7006 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7007
851ba692 7008 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7009 return r;
7010
7011cancel_injection:
7012 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7013 if (unlikely(vcpu->arch.apic_attention))
7014 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7015out:
7016 return r;
7017}
b6c7a5dc 7018
362c698f
PB		 7019static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7020{
bf9f6ac8
FW		 7021 if (!kvm_arch_vcpu_runnable(vcpu) &&
7022 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7023 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7024 kvm_vcpu_block(vcpu);
7025 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7026
7027 if (kvm_x86_ops->post_block)
7028 kvm_x86_ops->post_block(vcpu);
7029
9c8fd1ba
PB		 7030 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7031 return 1;
7032 }
362c698f
PB		 7033
7034 kvm_apic_accept_events(vcpu);
7035 switch(vcpu->arch.mp_state) {
7036 case KVM_MP_STATE_HALTED:
7037 vcpu->arch.pv.pv_unhalted = false;
7038 vcpu->arch.mp_state =
7039 KVM_MP_STATE_RUNNABLE;
7040 case KVM_MP_STATE_RUNNABLE:
7041 vcpu->arch.apf.halted = false;
7042 break;
7043 case KVM_MP_STATE_INIT_RECEIVED:
7044 break;
7045 default:
7046 return -EINTR;
7047 break;
7048 }
7049 return 1;
7050}
09cec754 7051
5d9bc648
PB		 7052static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7053{
0ad3bed6
PB		 7054 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7055 kvm_x86_ops->check_nested_events(vcpu, false);
7056
5d9bc648
PB		 7057 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7058 !vcpu->arch.apf.halted);
7059}
7060
362c698f 7061static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7062{
7063 int r;
f656ce01 7064 struct kvm *kvm = vcpu->kvm;
d7690175 7065
f656ce01 7066 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7067
362c698f 7068 for (;;) {
58f800d5 7069 if (kvm_vcpu_running(vcpu)) {
851ba692 7070 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7071 } else {
362c698f 7072 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7073 }
7074
09cec754
GN		 7075 if (r <= 0)
7076 break;
7077
72875d8a 7078 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7079 if (kvm_cpu_has_pending_timer(vcpu))
7080 kvm_inject_pending_timer_irqs(vcpu);
7081
782d422b
MG		 7082 if (dm_request_for_irq_injection(vcpu) &&
7083 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7084 r = 0;
7085 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7086 ++vcpu->stat.request_irq_exits;
362c698f 7087 break;
09cec754 7088 }
af585b92
GN		 7089
7090 kvm_check_async_pf_completion(vcpu);
7091
09cec754
GN		 7092 if (signal_pending(current)) {
7093 r = -EINTR;
851ba692 7094 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7095 ++vcpu->stat.signal_exits;
362c698f 7096 break;
09cec754
GN		 7097 }
7098 if (need_resched()) {
f656ce01 7099 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7100 cond_resched();
f656ce01 7101 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7102 }
b6c7a5dc
HB		 7103 }
7104
f656ce01 7105 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7106
7107 return r;
7108}
7109
716d51ab
GN		 7110static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7111{
7112 int r;
7113 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7114 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7115 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7116 if (r != EMULATE_DONE)
7117 return 0;
7118 return 1;
7119}
7120
7121static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7122{
7123 BUG_ON(!vcpu->arch.pio.count);
7124
7125 return complete_emulated_io(vcpu);
7126}
7127
f78146b0
AK		 7128/*
7129 * Implements the following, as a state machine:
7130 *
7131 * read:
7132 * for each fragment
87da7e66
XG		 7133 * for each mmio piece in the fragment
7134 * write gpa, len
7135 * exit
7136 * copy data
f78146b0
AK		 7137 * execute insn
7138 *
7139 * write:
7140 * for each fragment
87da7e66
XG		 7141 * for each mmio piece in the fragment
7142 * write gpa, len
7143 * copy data
7144 * exit
f78146b0 7145 */
716d51ab 7146static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7147{
7148 struct kvm_run *run = vcpu->run;
f78146b0 7149 struct kvm_mmio_fragment *frag;
87da7e66 7150 unsigned len;
5287f194 7151
716d51ab 7152 BUG_ON(!vcpu->mmio_needed);
5287f194 7153
716d51ab 7154 /* Complete previous fragment */
87da7e66
XG		 7155 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7156 len = min(8u, frag->len);
716d51ab 7157 if (!vcpu->mmio_is_write)
87da7e66
XG		 7158 memcpy(frag->data, run->mmio.data, len);
7159
7160 if (frag->len <= 8) {
7161 /* Switch to the next fragment. */
7162 frag++;
7163 vcpu->mmio_cur_fragment++;
7164 } else {
7165 /* Go forward to the next mmio piece. */
7166 frag->data += len;
7167 frag->gpa += len;
7168 frag->len -= len;
7169 }
7170
a08d3b3b 7171 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7172 vcpu->mmio_needed = 0;
0912c977
PB		 7173
7174 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7175 if (vcpu->mmio_is_write)
716d51ab
GN		 7176 return 1;
7177 vcpu->mmio_read_completed = 1;
7178 return complete_emulated_io(vcpu);
7179 }
87da7e66 7180
716d51ab
GN		 7181 run->exit_reason = KVM_EXIT_MMIO;
7182 run->mmio.phys_addr = frag->gpa;
7183 if (vcpu->mmio_is_write)
87da7e66
XG		 7184 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7185 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7186 run->mmio.is_write = vcpu->mmio_is_write;
7187 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7188 return 0;
5287f194
AK		 7189}
7190
716d51ab 7191
b6c7a5dc
HB		 7192int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7193{
c5bedc68 7194 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 7195 int r;
7196 sigset_t sigsaved;
7197
c4d72e2d 7198 fpu__activate_curr(fpu);
e5c30142 7199
ac9f6dc0
AK		 7200 if (vcpu->sigset_active)
7201 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
7202
a4535290 7203 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 7204 kvm_vcpu_block(vcpu);
66450a21 7205 kvm_apic_accept_events(vcpu);
72875d8a 7206 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0
AK		 7207 r = -EAGAIN;
7208 goto out;
b6c7a5dc
HB		 7209 }
7210
b6c7a5dc 7211 /* re-sync apic's tpr */
35754c98 7212 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7213 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7214 r = -EINVAL;
7215 goto out;
7216 }
7217 }
b6c7a5dc 7218
716d51ab
GN		 7219 if (unlikely(vcpu->arch.complete_userspace_io)) {
7220 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7221 vcpu->arch.complete_userspace_io = NULL;
7222 r = cui(vcpu);
7223 if (r <= 0)
7224 goto out;
7225 } else
7226 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7227
460df4c1
PB		 7228 if (kvm_run->immediate_exit)
7229 r = -EINTR;
7230 else
7231 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7232
7233out:
f1d86e46 7234 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 7235 if (vcpu->sigset_active)
7236 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
7237
b6c7a5dc
HB		 7238 return r;
7239}
7240
7241int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7242{
7ae441ea
GN		 7243 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7244 /*
7245 * We are here if userspace calls get_regs() in the middle of
7246 * instruction emulation. Registers state needs to be copied
4a969980 7247 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7248 * that usually, but some bad designed PV devices (vmware
7249 * backdoor interface) need this to work
7250 */
dd856efa 7251 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7252 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7253 }
5fdbf976
MT		 7254 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7255 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7256 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7257 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7258 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7259 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7260 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7261 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7262#ifdef CONFIG_X86_64
5fdbf976
MT		 7263 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7264 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7265 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7266 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7267 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7268 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7269 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7270 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7271#endif
7272
5fdbf976 7273 regs->rip = kvm_rip_read(vcpu);
91586a3b 7274 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7275
b6c7a5dc
HB		 7276 return 0;
7277}
7278
7279int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7280{
7ae441ea
GN		 7281 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7282 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7283
5fdbf976
MT		 7284 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7285 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7286 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7287 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7288 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7289 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7290 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7291 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7292#ifdef CONFIG_X86_64
5fdbf976
MT		 7293 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7294 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7295 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7296 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7297 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7298 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7299 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7300 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7301#endif
7302
5fdbf976 7303 kvm_rip_write(vcpu, regs->rip);
91586a3b 7304 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 7305
b4f14abd
JK		 7306 vcpu->arch.exception.pending = false;
7307
3842d135
AK		 7308 kvm_make_request(KVM_REQ_EVENT, vcpu);
7309
b6c7a5dc
HB		 7310 return 0;
7311}
7312
b6c7a5dc
HB		 7313void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7314{
7315 struct kvm_segment cs;
7316
3e6e0aab 7317 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7318 *db = cs.db;
7319 *l = cs.l;
7320}
7321EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7322
7323int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7324 struct kvm_sregs *sregs)
7325{
89a27f4d 7326 struct desc_ptr dt;
b6c7a5dc 7327
3e6e0aab
GT		 7328 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7329 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7330 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7331 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7332 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7333 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7334
3e6e0aab
GT		 7335 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7336 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7337
7338 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7339 sregs->idt.limit = dt.size;
7340 sregs->idt.base = dt.address;
b6c7a5dc 7341 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7342 sregs->gdt.limit = dt.size;
7343 sregs->gdt.base = dt.address;
b6c7a5dc 7344
4d4ec087 7345 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7346 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7347 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7348 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7349 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7350 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7351 sregs->apic_base = kvm_get_apic_base(vcpu);
7352
923c61bb 7353 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7354
36752c9b 7355 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7356 set_bit(vcpu->arch.interrupt.nr,
7357 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7358
b6c7a5dc
HB		 7359 return 0;
7360}
7361
62d9f0db
MT		 7362int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7363 struct kvm_mp_state *mp_state)
7364{
66450a21 7365 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7366 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7367 vcpu->arch.pv.pv_unhalted)
7368 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7369 else
7370 mp_state->mp_state = vcpu->arch.mp_state;
7371
62d9f0db
MT		 7372 return 0;
7373}
7374
7375int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7376 struct kvm_mp_state *mp_state)
7377{
bce87cce 7378 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7379 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7380 return -EINVAL;
7381
28bf2888
DH		 7382 /* INITs are latched while in SMM */
7383 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7384 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7385 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7386 return -EINVAL;
7387
66450a21
JK		 7388 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7389 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7390 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7391 } else
7392 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7393 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7394 return 0;
7395}
7396
7f3d35fd
KW		 7397int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7398 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7399{
9d74191a 7400 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7401 int ret;
e01c2426 7402
8ec4722d 7403 init_emulate_ctxt(vcpu);
c697518a 7404
7f3d35fd 7405 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7406 has_error_code, error_code);
c697518a 7407
c697518a 7408 if (ret)
19d04437 7409 return EMULATE_FAIL;
37817f29 7410
9d74191a
TY		 7411 kvm_rip_write(vcpu, ctxt->eip);
7412 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7413 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7414 return EMULATE_DONE;
37817f29
IE		 7415}
7416EXPORT_SYMBOL_GPL(kvm_task_switch);
7417
b6c7a5dc
HB		 7418int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7419 struct kvm_sregs *sregs)
7420{
58cb628d 7421 struct msr_data apic_base_msr;
b6c7a5dc 7422 int mmu_reset_needed = 0;
63f42e02 7423 int pending_vec, max_bits, idx;
89a27f4d 7424 struct desc_ptr dt;
b6c7a5dc 7425
6d1068b3
PM		 7426 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7427 return -EINVAL;
7428
89a27f4d
GN		 7429 dt.size = sregs->idt.limit;
7430 dt.address = sregs->idt.base;
b6c7a5dc 7431 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7432 dt.size = sregs->gdt.limit;
7433 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7434 kvm_x86_ops->set_gdt(vcpu, &dt);
7435
ad312c7c 7436 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7437 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7438 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7439 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7440
2d3ad1f4 7441 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7442
f6801dff 7443 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7444 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7445 apic_base_msr.data = sregs->apic_base;
7446 apic_base_msr.host_initiated = true;
7447 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7448
4d4ec087 7449 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7450 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7451 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7452
fc78f519 7453 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7454 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7455 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7456 kvm_update_cpuid(vcpu);
63f42e02
XG		 7457
7458 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7459 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7460 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7461 mmu_reset_needed = 1;
7462 }
63f42e02 7463 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7464
7465 if (mmu_reset_needed)
7466 kvm_mmu_reset_context(vcpu);
7467
a50abc3b 7468 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7469 pending_vec = find_first_bit(
7470 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7471 if (pending_vec < max_bits) {
66fd3f7f 7472 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7473 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7474 }
7475
3e6e0aab
GT		 7476 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7477 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7478 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7479 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7480 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7481 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7482
3e6e0aab
GT		 7483 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7484 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7485
5f0269f5
ME		 7486 update_cr8_intercept(vcpu);
7487
9c3e4aab 7488 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7489 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7490 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7491 !is_protmode(vcpu))
9c3e4aab
MT		 7492 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7493
3842d135
AK		 7494 kvm_make_request(KVM_REQ_EVENT, vcpu);
7495
b6c7a5dc
HB		 7496 return 0;
7497}
7498
d0bfb940
JK		 7499int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7500 struct kvm_guest_debug *dbg)
b6c7a5dc 7501{
355be0b9 7502 unsigned long rflags;
ae675ef0 7503 int i, r;
b6c7a5dc 7504
4f926bf2
JK		 7505 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7506 r = -EBUSY;
7507 if (vcpu->arch.exception.pending)
2122ff5e 7508 goto out;
4f926bf2
JK		 7509 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7510 kvm_queue_exception(vcpu, DB_VECTOR);
7511 else
7512 kvm_queue_exception(vcpu, BP_VECTOR);
7513 }
7514
91586a3b
JK		 7515 /*
7516 * Read rflags as long as potentially injected trace flags are still
7517 * filtered out.
7518 */
7519 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7520
7521 vcpu->guest_debug = dbg->control;
7522 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7523 vcpu->guest_debug = 0;
7524
7525 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7526 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7527 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7528 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7529 } else {
7530 for (i = 0; i < KVM_NR_DB_REGS; i++)
7531 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7532 }
c8639010 7533 kvm_update_dr7(vcpu);
ae675ef0 7534
f92653ee
JK		 7535 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7536 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7537 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7538
91586a3b
JK		 7539 /*
7540 * Trigger an rflags update that will inject or remove the trace
7541 * flags.
7542 */
7543 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7544
a96036b8 7545 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7546
4f926bf2 7547 r = 0;
d0bfb940 7548
2122ff5e 7549out:
b6c7a5dc
HB		 7550
7551 return r;
7552}
7553
8b006791
ZX		 7554/*
7555 * Translate a guest virtual address to a guest physical address.
7556 */
7557int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7558 struct kvm_translation *tr)
7559{
7560 unsigned long vaddr = tr->linear_address;
7561 gpa_t gpa;
f656ce01 7562 int idx;
8b006791 7563
f656ce01 7564 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7565 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7566 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7567 tr->physical_address = gpa;
7568 tr->valid = gpa != UNMAPPED_GVA;
7569 tr->writeable = 1;
7570 tr->usermode = 0;
8b006791
ZX		 7571
7572 return 0;
7573}
7574
d0752060
HB		 7575int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7576{
c47ada30 7577 struct fxregs_state *fxsave =
7366ed77 7578 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7579
d0752060
HB		 7580 memcpy(fpu->fpr, fxsave->st_space, 128);
7581 fpu->fcw = fxsave->cwd;
7582 fpu->fsw = fxsave->swd;
7583 fpu->ftwx = fxsave->twd;
7584 fpu->last_opcode = fxsave->fop;
7585 fpu->last_ip = fxsave->rip;
7586 fpu->last_dp = fxsave->rdp;
7587 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7588
d0752060
HB		 7589 return 0;
7590}
7591
7592int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7593{
c47ada30 7594 struct fxregs_state *fxsave =
7366ed77 7595 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7596
d0752060
HB		 7597 memcpy(fxsave->st_space, fpu->fpr, 128);
7598 fxsave->cwd = fpu->fcw;
7599 fxsave->swd = fpu->fsw;
7600 fxsave->twd = fpu->ftwx;
7601 fxsave->fop = fpu->last_opcode;
7602 fxsave->rip = fpu->last_ip;
7603 fxsave->rdp = fpu->last_dp;
7604 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7605
d0752060
HB		 7606 return 0;
7607}
7608
0ee6a517 7609static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7610{
bf935b0b 7611 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7612 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7613 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7614 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7615
2acf923e
DC		 7616 /*
7617 * Ensure guest xcr0 is valid for loading
7618 */
d91cab78 7619 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7620
ad312c7c 7621 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7622}
d0752060
HB		 7623
7624void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7625{
2608d7a1 7626 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7627 return;
7628
2acf923e
DC		 7629 /*
7630 * Restore all possible states in the guest,
7631 * and assume host would use all available bits.
7632 * Guest xcr0 would be loaded later.
7633 */
d0752060 7634 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7635 __kernel_fpu_begin();
003e2e8b 7636 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7637 trace_kvm_fpu(1);
d0752060 7638}
d0752060
HB		 7639
7640void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7641{
3d42de25 7642 if (!vcpu->guest_fpu_loaded)
d0752060
HB		 7643 return;
7644
7645 vcpu->guest_fpu_loaded = 0;
4f836347 7646 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7647 __kernel_fpu_end();
f096ed85 7648 ++vcpu->stat.fpu_reload;
0c04851c 7649 trace_kvm_fpu(0);
d0752060 7650}
e9b11c17
ZX		 7651
7652void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7653{
bd768e14
IY		 7654 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7655
12f9a48f 7656 kvmclock_reset(vcpu);
7f1ea208 7657
e9b11c17 7658 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 7659 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 7660}
7661
7662struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7663 unsigned int id)
7664{
c447e76b
LL		 7665 struct kvm_vcpu *vcpu;
7666
6755bae8
ZA		 7667 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7668 printk_once(KERN_WARNING
7669 "kvm: SMP vm created on host with unstable TSC; "
7670 "guest TSC will not be reliable\n");
c447e76b
LL		 7671
7672 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7673
c447e76b 7674 return vcpu;
26e5215f 7675}
e9b11c17 7676
26e5215f
AK		 7677int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7678{
7679 int r;
e9b11c17 7680
19efffa2 7681 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7682 r = vcpu_load(vcpu);
7683 if (r)
7684 return r;
d28bc9dd 7685 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7686 kvm_mmu_setup(vcpu);
e9b11c17 7687 vcpu_put(vcpu);
26e5215f 7688 return r;
e9b11c17
ZX		 7689}
7690
31928aa5 7691void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7692{
8fe8ab46 7693 struct msr_data msr;
332967a3 7694 struct kvm *kvm = vcpu->kvm;
42897d86 7695
d3457c87
RK		 7696 kvm_hv_vcpu_postcreate(vcpu);
7697
31928aa5
DD		 7698 if (vcpu_load(vcpu))
7699 return;
8fe8ab46
WA		 7700 msr.data = 0x0;
7701 msr.index = MSR_IA32_TSC;
7702 msr.host_initiated = true;
7703 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7704 vcpu_put(vcpu);
7705
630994b3
MT		 7706 if (!kvmclock_periodic_sync)
7707 return;
7708
332967a3
AJ		 7709 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7710 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7711}
7712
d40ccc62 7713void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7714{
9fc77441 7715 int r;
344d9588
GN		 7716 vcpu->arch.apf.msr_val = 0;
7717
9fc77441
MT		 7718 r = vcpu_load(vcpu);
7719 BUG_ON(r);
e9b11c17
ZX		 7720 kvm_mmu_unload(vcpu);
7721 vcpu_put(vcpu);
7722
7723 kvm_x86_ops->vcpu_free(vcpu);
7724}
7725
d28bc9dd 7726void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7727{
e69fab5d
PB		 7728 vcpu->arch.hflags = 0;
7729
c43203ca 7730 vcpu->arch.smi_pending = 0;
7460fb4a
AK		 7731 atomic_set(&vcpu->arch.nmi_queued, 0);
7732 vcpu->arch.nmi_pending = 0;
448fa4a9 7733 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7734 kvm_clear_interrupt_queue(vcpu);
7735 kvm_clear_exception_queue(vcpu);
448fa4a9 7736
42dbaa5a 7737 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7738 kvm_update_dr0123(vcpu);
6f43ed01 7739 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7740 kvm_update_dr6(vcpu);
42dbaa5a 7741 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7742 kvm_update_dr7(vcpu);
42dbaa5a 7743
1119022c
NA		 7744 vcpu->arch.cr2 = 0;
7745
3842d135 7746 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7747 vcpu->arch.apf.msr_val = 0;
c9aaa895 7748 vcpu->arch.st.msr_val = 0;
3842d135 7749
12f9a48f
GC		 7750 kvmclock_reset(vcpu);
7751
af585b92
GN		 7752 kvm_clear_async_pf_completion_queue(vcpu);
7753 kvm_async_pf_hash_reset(vcpu);
7754 vcpu->arch.apf.halted = false;
3842d135 7755
64d60670 7756 if (!init_event) {
d28bc9dd 7757 kvm_pmu_reset(vcpu);
64d60670 7758 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 7759
7760 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
7761 vcpu->arch.msr_misc_features_enables = 0;
64d60670 7762 }
f5132b01 7763
66f7b72e
JS		 7764 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7765 vcpu->arch.regs_avail = ~0;
7766 vcpu->arch.regs_dirty = ~0;
7767
d28bc9dd 7768 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7769}
7770
2b4a273b 7771void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7772{
7773 struct kvm_segment cs;
7774
7775 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7776 cs.selector = vector << 8;
7777 cs.base = vector << 12;
7778 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7779 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7780}
7781
13a34e06 7782int kvm_arch_hardware_enable(void)
e9b11c17 7783{
ca84d1a2
ZA		 7784 struct kvm *kvm;
7785 struct kvm_vcpu *vcpu;
7786 int i;
0dd6a6ed
ZA		 7787 int ret;
7788 u64 local_tsc;
7789 u64 max_tsc = 0;
7790 bool stable, backwards_tsc = false;
18863bdd
AK		 7791
7792 kvm_shared_msr_cpu_online();
13a34e06 7793 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7794 if (ret != 0)
7795 return ret;
7796
4ea1636b 7797 local_tsc = rdtsc();
0dd6a6ed
ZA		 7798 stable = !check_tsc_unstable();
7799 list_for_each_entry(kvm, &vm_list, vm_list) {
7800 kvm_for_each_vcpu(i, vcpu, kvm) {
7801 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7802 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7803 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7804 backwards_tsc = true;
7805 if (vcpu->arch.last_host_tsc > max_tsc)
7806 max_tsc = vcpu->arch.last_host_tsc;
7807 }
7808 }
7809 }
7810
7811 /*
7812 * Sometimes, even reliable TSCs go backwards. This happens on
7813 * platforms that reset TSC during suspend or hibernate actions, but
7814 * maintain synchronization. We must compensate. Fortunately, we can
7815 * detect that condition here, which happens early in CPU bringup,
7816 * before any KVM threads can be running. Unfortunately, we can't
7817 * bring the TSCs fully up to date with real time, as we aren't yet far
7818 * enough into CPU bringup that we know how much real time has actually
108b249c 7819 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 7820 * variables that haven't been updated yet.
7821 *
7822 * So we simply find the maximum observed TSC above, then record the
7823 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7824 * the adjustment will be applied. Note that we accumulate
7825 * adjustments, in case multiple suspend cycles happen before some VCPU
7826 * gets a chance to run again. In the event that no KVM threads get a
7827 * chance to run, we will miss the entire elapsed period, as we'll have
7828 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7829 * loose cycle time. This isn't too big a deal, since the loss will be
7830 * uniform across all VCPUs (not to mention the scenario is extremely
7831 * unlikely). It is possible that a second hibernate recovery happens
7832 * much faster than a first, causing the observed TSC here to be
7833 * smaller; this would require additional padding adjustment, which is
7834 * why we set last_host_tsc to the local tsc observed here.
7835 *
7836 * N.B. - this code below runs only on platforms with reliable TSC,
7837 * as that is the only way backwards_tsc is set above. Also note
7838 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7839 * have the same delta_cyc adjustment applied if backwards_tsc
7840 * is detected. Note further, this adjustment is only done once,
7841 * as we reset last_host_tsc on all VCPUs to stop this from being
7842 * called multiple times (one for each physical CPU bringup).
7843 *
4a969980 7844 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7845 * will be compensated by the logic in vcpu_load, which sets the TSC to
7846 * catchup mode. This will catchup all VCPUs to real time, but cannot
7847 * guarantee that they stay in perfect synchronization.
7848 */
7849 if (backwards_tsc) {
7850 u64 delta_cyc = max_tsc - local_tsc;
7851 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 7852 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 7853 kvm_for_each_vcpu(i, vcpu, kvm) {
7854 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7855 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7856 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7857 }
7858
7859 /*
7860 * We have to disable TSC offset matching.. if you were
7861 * booting a VM while issuing an S4 host suspend....
7862 * you may have some problem. Solving this issue is
7863 * left as an exercise to the reader.
7864 */
7865 kvm->arch.last_tsc_nsec = 0;
7866 kvm->arch.last_tsc_write = 0;
7867 }
7868
7869 }
7870 return 0;
e9b11c17
ZX		 7871}
7872
13a34e06 7873void kvm_arch_hardware_disable(void)
e9b11c17 7874{
13a34e06
RK		 7875 kvm_x86_ops->hardware_disable();
7876 drop_user_return_notifiers();
e9b11c17
ZX		 7877}
7878
7879int kvm_arch_hardware_setup(void)
7880{
9e9c3fe4
NA		 7881 int r;
7882
7883 r = kvm_x86_ops->hardware_setup();
7884 if (r != 0)
7885 return r;
7886
35181e86
HZ		 7887 if (kvm_has_tsc_control) {
7888 /*
7889 * Make sure the user can only configure tsc_khz values that
7890 * fit into a signed integer.
7891 * A min value is not calculated needed because it will always
7892 * be 1 on all machines.
7893 */
7894 u64 max = min(0x7fffffffULL,
7895 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7896 kvm_max_guest_tsc_khz = max;
7897
ad721883 7898 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7899 }
ad721883 7900
9e9c3fe4
NA		 7901 kvm_init_msr_list();
7902 return 0;
e9b11c17
ZX		 7903}
7904
7905void kvm_arch_hardware_unsetup(void)
7906{
7907 kvm_x86_ops->hardware_unsetup();
7908}
7909
7910void kvm_arch_check_processor_compat(void *rtn)
7911{
7912 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7913}
7914
7915bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7916{
7917 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7918}
7919EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7920
7921bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7922{
7923 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7924}
7925
54e9818f 7926struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 7927EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 7928
e9b11c17
ZX		 7929int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7930{
7931 struct page *page;
7932 struct kvm *kvm;
7933 int r;
7934
7935 BUG_ON(vcpu->kvm == NULL);
7936 kvm = vcpu->kvm;
7937
d62caabb 7938 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7939 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7940 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7941 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7942 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7943 else
a4535290 7944 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7945
7946 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7947 if (!page) {
7948 r = -ENOMEM;
7949 goto fail;
7950 }
ad312c7c 7951 vcpu->arch.pio_data = page_address(page);
e9b11c17 7952
cc578287 7953 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7954
e9b11c17
ZX		 7955 r = kvm_mmu_create(vcpu);
7956 if (r < 0)
7957 goto fail_free_pio_data;
7958
7959 if (irqchip_in_kernel(kvm)) {
7960 r = kvm_create_lapic(vcpu);
7961 if (r < 0)
7962 goto fail_mmu_destroy;
54e9818f
GN		 7963 } else
7964 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7965
890ca9ae
HY		 7966 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7967 GFP_KERNEL);
7968 if (!vcpu->arch.mce_banks) {
7969 r = -ENOMEM;
443c39bc 7970 goto fail_free_lapic;
890ca9ae
HY		 7971 }
7972 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7973
f1797359
WY		 7974 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7975 r = -ENOMEM;
f5f48ee1 7976 goto fail_free_mce_banks;
f1797359 7977 }
f5f48ee1 7978
0ee6a517 7979 fx_init(vcpu);
66f7b72e 7980
ba904635 7981 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7982 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7983
7984 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7985 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7986
5a4f55cd
EK		 7987 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7988
74545705
RK		 7989 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7990
af585b92 7991 kvm_async_pf_hash_reset(vcpu);
f5132b01 7992 kvm_pmu_init(vcpu);
af585b92 7993
1c1a9ce9
SR		 7994 vcpu->arch.pending_external_vector = -1;
7995
5c919412
AS		 7996 kvm_hv_vcpu_init(vcpu);
7997
e9b11c17 7998 return 0;
0ee6a517 7999
f5f48ee1
SY		 8000fail_free_mce_banks:
8001 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8002fail_free_lapic:
8003 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8004fail_mmu_destroy:
8005 kvm_mmu_destroy(vcpu);
8006fail_free_pio_data:
ad312c7c 8007 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8008fail:
8009 return r;
8010}
8011
8012void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8013{
f656ce01
MT		 8014 int idx;
8015
1f4b34f8 8016 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8017 kvm_pmu_destroy(vcpu);
36cb93fd 8018 kfree(vcpu->arch.mce_banks);
e9b11c17 8019 kvm_free_lapic(vcpu);
f656ce01 8020 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8021 kvm_mmu_destroy(vcpu);
f656ce01 8022 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8023 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8024 if (!lapic_in_kernel(vcpu))
54e9818f 8025 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8026}
d19a9cd2 8027
e790d9ef
RK		 8028void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8029{
ae97a3b8 8030 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8031}
8032
e08b9637 8033int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8034{
e08b9637
CO		 8035 if (type)
8036 return -EINVAL;
8037
6ef768fa 8038 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8039 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8040 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8041 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8042 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8043
5550af4d
SY		 8044 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8045 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8046 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8047 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8048 &kvm->arch.irq_sources_bitmap);
5550af4d 8049
038f8c11 8050 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8051 mutex_init(&kvm->arch.apic_map_lock);
3f5ad8be 8052 mutex_init(&kvm->arch.hyperv.hv_lock);
d828199e
MT		 8053 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8054
108b249c 8055 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8056 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8057
7e44e449 8058 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8059 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8060
0eb05bf2 8061 kvm_page_track_init(kvm);
13d268ca 8062 kvm_mmu_init_vm(kvm);
0eb05bf2 8063
03543133
SS		 8064 if (kvm_x86_ops->vm_init)
8065 return kvm_x86_ops->vm_init(kvm);
8066
d89f5eff 8067 return 0;
d19a9cd2
ZX		 8068}
8069
8070static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8071{
9fc77441
MT		 8072 int r;
8073 r = vcpu_load(vcpu);
8074 BUG_ON(r);
d19a9cd2
ZX		 8075 kvm_mmu_unload(vcpu);
8076 vcpu_put(vcpu);
8077}
8078
8079static void kvm_free_vcpus(struct kvm *kvm)
8080{
8081 unsigned int i;
988a2cae 8082 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8083
8084 /*
8085 * Unpin any mmu pages first.
8086 */
af585b92
GN		 8087 kvm_for_each_vcpu(i, vcpu, kvm) {
8088 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8089 kvm_unload_vcpu_mmu(vcpu);
af585b92 8090 }
988a2cae
GN		 8091 kvm_for_each_vcpu(i, vcpu, kvm)
8092 kvm_arch_vcpu_free(vcpu);
8093
8094 mutex_lock(&kvm->lock);
8095 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8096 kvm->vcpus[i] = NULL;
d19a9cd2 8097
988a2cae
GN		 8098 atomic_set(&kvm->online_vcpus, 0);
8099 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8100}
8101
ad8ba2cd
SY		 8102void kvm_arch_sync_events(struct kvm *kvm)
8103{
332967a3 8104 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8105 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8106 kvm_free_pit(kvm);
ad8ba2cd
SY		 8107}
8108
1d8007bd 8109int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8110{
8111 int i, r;
25188b99 8112 unsigned long hva;
f0d648bd
PB		 8113 struct kvm_memslots *slots = kvm_memslots(kvm);
8114 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8115
8116 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8117 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8118 return -EINVAL;
9da0e4d5 8119
f0d648bd
PB		 8120 slot = id_to_memslot(slots, id);
8121 if (size) {
b21629da 8122 if (slot->npages)
f0d648bd
PB		 8123 return -EEXIST;
8124
8125 /*
8126 * MAP_SHARED to prevent internal slot pages from being moved
8127 * by fork()/COW.
8128 */
8129 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8130 MAP_SHARED | MAP_ANONYMOUS, 0);
8131 if (IS_ERR((void *)hva))
8132 return PTR_ERR((void *)hva);
8133 } else {
8134 if (!slot->npages)
8135 return 0;
8136
8137 hva = 0;
8138 }
8139
8140 old = *slot;
9da0e4d5 8141 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8142 struct kvm_userspace_memory_region m;
9da0e4d5 8143
1d8007bd
PB		 8144 m.slot = id | (i << 16);
8145 m.flags = 0;
8146 m.guest_phys_addr = gpa;
f0d648bd 8147 m.userspace_addr = hva;
1d8007bd 8148 m.memory_size = size;
9da0e4d5
PB		 8149 r = __kvm_set_memory_region(kvm, &m);
8150 if (r < 0)
8151 return r;
8152 }
8153
f0d648bd
PB		 8154 if (!size) {
8155 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8156 WARN_ON(r < 0);
8157 }
8158
9da0e4d5
PB		 8159 return 0;
8160}
8161EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8162
1d8007bd 8163int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8164{
8165 int r;
8166
8167 mutex_lock(&kvm->slots_lock);
1d8007bd 8168 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8169 mutex_unlock(&kvm->slots_lock);
8170
8171 return r;
8172}
8173EXPORT_SYMBOL_GPL(x86_set_memory_region);
8174
d19a9cd2
ZX		 8175void kvm_arch_destroy_vm(struct kvm *kvm)
8176{
27469d29
AH		 8177 if (current->mm == kvm->mm) {
8178 /*
8179 * Free memory regions allocated on behalf of userspace,
8180 * unless the the memory map has changed due to process exit
8181 * or fd copying.
8182 */
1d8007bd
PB		 8183 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8184 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8185 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8186 }
03543133
SS		 8187 if (kvm_x86_ops->vm_destroy)
8188 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8189 kvm_pic_destroy(kvm);
8190 kvm_ioapic_destroy(kvm);
d19a9cd2 8191 kvm_free_vcpus(kvm);
af1bae54 8192 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8193 kvm_mmu_uninit_vm(kvm);
2beb6dad 8194 kvm_page_track_cleanup(kvm);
d19a9cd2 8195}
0de10343 8196
5587027c 8197void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8198 struct kvm_memory_slot *dont)
8199{
8200 int i;
8201
d89cc617
TY		 8202 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8203 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8204 kvfree(free->arch.rmap[i]);
d89cc617 8205 free->arch.rmap[i] = NULL;
77d11309 8206 }
d89cc617
TY		 8207 if (i == 0)
8208 continue;
8209
8210 if (!dont || free->arch.lpage_info[i - 1] !=
8211 dont->arch.lpage_info[i - 1]) {
548ef284 8212 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8213 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8214 }
8215 }
21ebbeda
XG		 8216
8217 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8218}
8219
5587027c
AK		 8220int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8221 unsigned long npages)
db3fe4eb
TY		 8222{
8223 int i;
8224
d89cc617 8225 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8226 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8227 unsigned long ugfn;
8228 int lpages;
d89cc617 8229 int level = i + 1;
db3fe4eb
TY		 8230
8231 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8232 slot->base_gfn, level) + 1;
8233
d89cc617 8234 slot->arch.rmap[i] =
a7c3e901 8235 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8236 if (!slot->arch.rmap[i])
77d11309 8237 goto out_free;
d89cc617
TY		 8238 if (i == 0)
8239 continue;
77d11309 8240
a7c3e901 8241 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8242 if (!linfo)
db3fe4eb
TY		 8243 goto out_free;
8244
92f94f1e
XG		 8245 slot->arch.lpage_info[i - 1] = linfo;
8246
db3fe4eb 8247 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8248 linfo[0].disallow_lpage = 1;
db3fe4eb 8249 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8250 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8251 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8252 /*
8253 * If the gfn and userspace address are not aligned wrt each
8254 * other, or if explicitly asked to, disable large page
8255 * support for this slot
8256 */
8257 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8258 !kvm_largepages_enabled()) {
8259 unsigned long j;
8260
8261 for (j = 0; j < lpages; ++j)
92f94f1e 8262 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8263 }
8264 }
8265
21ebbeda
XG		 8266 if (kvm_page_track_create_memslot(slot, npages))
8267 goto out_free;
8268
db3fe4eb
TY		 8269 return 0;
8270
8271out_free:
d89cc617 8272 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8273 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8274 slot->arch.rmap[i] = NULL;
8275 if (i == 0)
8276 continue;
8277
548ef284 8278 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8279 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8280 }
8281 return -ENOMEM;
8282}
8283
15f46015 8284void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8285{
e6dff7d1
TY		 8286 /*
8287 * memslots->generation has been incremented.
8288 * mmio generation may have reached its maximum value.
8289 */
54bf36aa 8290 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8291}
8292
f7784b8e
MT		 8293int kvm_arch_prepare_memory_region(struct kvm *kvm,
8294 struct kvm_memory_slot *memslot,
09170a49 8295 const struct kvm_userspace_memory_region *mem,
7b6195a9 8296 enum kvm_mr_change change)
0de10343 8297{
f7784b8e
MT		 8298 return 0;
8299}
8300
88178fd4
KH		 8301static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8302 struct kvm_memory_slot *new)
8303{
8304 /* Still write protect RO slot */
8305 if (new->flags & KVM_MEM_READONLY) {
8306 kvm_mmu_slot_remove_write_access(kvm, new);
8307 return;
8308 }
8309
8310 /*
8311 * Call kvm_x86_ops dirty logging hooks when they are valid.
8312 *
8313 * kvm_x86_ops->slot_disable_log_dirty is called when:
8314 *
8315 * - KVM_MR_CREATE with dirty logging is disabled
8316 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8317 *
8318 * The reason is, in case of PML, we need to set D-bit for any slots
8319 * with dirty logging disabled in order to eliminate unnecessary GPA
8320 * logging in PML buffer (and potential PML buffer full VMEXT). This
8321 * guarantees leaving PML enabled during guest's lifetime won't have
8322 * any additonal overhead from PML when guest is running with dirty
8323 * logging disabled for memory slots.
8324 *
8325 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8326 * to dirty logging mode.
8327 *
8328 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8329 *
8330 * In case of write protect:
8331 *
8332 * Write protect all pages for dirty logging.
8333 *
8334 * All the sptes including the large sptes which point to this
8335 * slot are set to readonly. We can not create any new large
8336 * spte on this slot until the end of the logging.
8337 *
8338 * See the comments in fast_page_fault().
8339 */
8340 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8341 if (kvm_x86_ops->slot_enable_log_dirty)
8342 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8343 else
8344 kvm_mmu_slot_remove_write_access(kvm, new);
8345 } else {
8346 if (kvm_x86_ops->slot_disable_log_dirty)
8347 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8348 }
8349}
8350
f7784b8e 8351void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8352 const struct kvm_userspace_memory_region *mem,
8482644a 8353 const struct kvm_memory_slot *old,
f36f3f28 8354 const struct kvm_memory_slot *new,
8482644a 8355 enum kvm_mr_change change)
f7784b8e 8356{
8482644a 8357 int nr_mmu_pages = 0;
f7784b8e 8358
48c0e4e9
XG		 8359 if (!kvm->arch.n_requested_mmu_pages)
8360 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8361
48c0e4e9 8362 if (nr_mmu_pages)
0de10343 8363 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8364
3ea3b7fa
WL		 8365 /*
8366 * Dirty logging tracks sptes in 4k granularity, meaning that large
8367 * sptes have to be split. If live migration is successful, the guest
8368 * in the source machine will be destroyed and large sptes will be
8369 * created in the destination. However, if the guest continues to run
8370 * in the source machine (for example if live migration fails), small
8371 * sptes will remain around and cause bad performance.
8372 *
8373 * Scan sptes if dirty logging has been stopped, dropping those
8374 * which can be collapsed into a single large-page spte. Later
8375 * page faults will create the large-page sptes.
8376 */
8377 if ((change != KVM_MR_DELETE) &&
8378 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8379 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8380 kvm_mmu_zap_collapsible_sptes(kvm, new);
8381
c972f3b1 8382 /*
88178fd4 8383 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8384 *
88178fd4
KH		 8385 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8386 * been zapped so no dirty logging staff is needed for old slot. For
8387 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8388 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8389 *
8390 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8391 */
88178fd4 8392 if (change != KVM_MR_DELETE)
f36f3f28 8393 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8394}
1d737c8a 8395
2df72e9b 8396void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8397{
6ca18b69 8398 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8399}
8400
2df72e9b
MT		 8401void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8402 struct kvm_memory_slot *slot)
8403{
ae7cd873 8404 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8405}
8406
5d9bc648
PB		 8407static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8408{
8409 if (!list_empty_careful(&vcpu->async_pf.done))
8410 return true;
8411
8412 if (kvm_apic_has_events(vcpu))
8413 return true;
8414
8415 if (vcpu->arch.pv.pv_unhalted)
8416 return true;
8417
47a66eed
Z		 8418 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8419 (vcpu->arch.nmi_pending &&
8420 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 8421 return true;
8422
47a66eed
Z		 8423 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8424 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 8425 return true;
8426
5d9bc648
PB		 8427 if (kvm_arch_interrupt_allowed(vcpu) &&
8428 kvm_cpu_has_interrupt(vcpu))
8429 return true;
8430
1f4b34f8
AS		 8431 if (kvm_hv_has_stimer_pending(vcpu))
8432 return true;
8433
5d9bc648
PB		 8434 return false;
8435}
8436
1d737c8a
ZX		 8437int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8438{
5d9bc648 8439 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8440}
5736199a 8441
b6d33834 8442int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8443{
b6d33834 8444 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8445}
78646121
GN		 8446
8447int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8448{
8449 return kvm_x86_ops->interrupt_allowed(vcpu);
8450}
229456fc 8451
82b32774 8452unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8453{
82b32774
NA		 8454 if (is_64_bit_mode(vcpu))
8455 return kvm_rip_read(vcpu);
8456 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8457 kvm_rip_read(vcpu));
8458}
8459EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8460
82b32774
NA		 8461bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8462{
8463 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8464}
8465EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8466
94fe45da
JK		 8467unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8468{
8469 unsigned long rflags;
8470
8471 rflags = kvm_x86_ops->get_rflags(vcpu);
8472 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8473 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8474 return rflags;
8475}
8476EXPORT_SYMBOL_GPL(kvm_get_rflags);
8477
6addfc42 8478static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8479{
8480 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8481 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8482 rflags |= X86_EFLAGS_TF;
94fe45da 8483 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8484}
8485
8486void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8487{
8488 __kvm_set_rflags(vcpu, rflags);
3842d135 8489 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8490}
8491EXPORT_SYMBOL_GPL(kvm_set_rflags);
8492
56028d08
GN		 8493void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8494{
8495 int r;
8496
fb67e14f 8497 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8498 work->wakeup_all)
56028d08
GN		 8499 return;
8500
8501 r = kvm_mmu_reload(vcpu);
8502 if (unlikely(r))
8503 return;
8504
fb67e14f
XG		 8505 if (!vcpu->arch.mmu.direct_map &&
8506 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8507 return;
8508
56028d08
GN		 8509 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8510}
8511
af585b92
GN		 8512static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8513{
8514 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8515}
8516
8517static inline u32 kvm_async_pf_next_probe(u32 key)
8518{
8519 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8520}
8521
8522static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8523{
8524 u32 key = kvm_async_pf_hash_fn(gfn);
8525
8526 while (vcpu->arch.apf.gfns[key] != ~0)
8527 key = kvm_async_pf_next_probe(key);
8528
8529 vcpu->arch.apf.gfns[key] = gfn;
8530}
8531
8532static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8533{
8534 int i;
8535 u32 key = kvm_async_pf_hash_fn(gfn);
8536
8537 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8538 (vcpu->arch.apf.gfns[key] != gfn &&
8539 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8540 key = kvm_async_pf_next_probe(key);
8541
8542 return key;
8543}
8544
8545bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8546{
8547 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8548}
8549
8550static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8551{
8552 u32 i, j, k;
8553
8554 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8555 while (true) {
8556 vcpu->arch.apf.gfns[i] = ~0;
8557 do {
8558 j = kvm_async_pf_next_probe(j);
8559 if (vcpu->arch.apf.gfns[j] == ~0)
8560 return;
8561 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8562 /*
8563 * k lies cyclically in ]i,j]
8564 * | i.k.j |
8565 * |....j i.k.| or |.k..j i...|
8566 */
8567 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8568 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8569 i = j;
8570 }
8571}
8572
7c90705b
GN		 8573static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8574{
4e335d9e
PB		 8575
8576 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8577 sizeof(val));
7c90705b
GN		 8578}
8579
af585b92
GN		 8580void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8581 struct kvm_async_pf *work)
8582{
6389ee94
AK		 8583 struct x86_exception fault;
8584
7c90705b 8585 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8586 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8587
8588 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8589 (vcpu->arch.apf.send_user_only &&
8590 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8591 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8592 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8593 fault.vector = PF_VECTOR;
8594 fault.error_code_valid = true;
8595 fault.error_code = 0;
8596 fault.nested_page_fault = false;
8597 fault.address = work->arch.token;
adfe20fb 8598 fault.async_page_fault = true;
6389ee94 8599 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8600 }
af585b92
GN		 8601}
8602
8603void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8604 struct kvm_async_pf *work)
8605{
6389ee94
AK		 8606 struct x86_exception fault;
8607
f2e10669 8608 if (work->wakeup_all)
7c90705b
GN		 8609 work->arch.token = ~0; /* broadcast wakeup */
8610 else
8611 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 8612 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b
GN		 8613
8614 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8615 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8616 fault.vector = PF_VECTOR;
8617 fault.error_code_valid = true;
8618 fault.error_code = 0;
8619 fault.nested_page_fault = false;
8620 fault.address = work->arch.token;
adfe20fb 8621 fault.async_page_fault = true;
6389ee94 8622 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8623 }
e6d53e3b 8624 vcpu->arch.apf.halted = false;
a4fa1635 8625 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8626}
8627
8628bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8629{
8630 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8631 return true;
8632 else
9bc1f09f 8633 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 8634}
8635
5544eb9b
PB		 8636void kvm_arch_start_assignment(struct kvm *kvm)
8637{
8638 atomic_inc(&kvm->arch.assigned_device_count);
8639}
8640EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8641
8642void kvm_arch_end_assignment(struct kvm *kvm)
8643{
8644 atomic_dec(&kvm->arch.assigned_device_count);
8645}
8646EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8647
8648bool kvm_arch_has_assigned_device(struct kvm *kvm)
8649{
8650 return atomic_read(&kvm->arch.assigned_device_count);
8651}
8652EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8653
e0f0bbc5
AW		 8654void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8655{
8656 atomic_inc(&kvm->arch.noncoherent_dma_count);
8657}
8658EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8659
8660void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8661{
8662 atomic_dec(&kvm->arch.noncoherent_dma_count);
8663}
8664EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8665
8666bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8667{
8668 return atomic_read(&kvm->arch.noncoherent_dma_count);
8669}
8670EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8671
14717e20
AW		 8672bool kvm_arch_has_irq_bypass(void)
8673{
8674 return kvm_x86_ops->update_pi_irte != NULL;
8675}
8676
87276880
FW		 8677int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8678 struct irq_bypass_producer *prod)
8679{
8680 struct kvm_kernel_irqfd *irqfd =
8681 container_of(cons, struct kvm_kernel_irqfd, consumer);
8682
14717e20 8683 irqfd->producer = prod;
87276880 8684
14717e20
AW		 8685 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8686 prod->irq, irqfd->gsi, 1);
87276880
FW		 8687}
8688
8689void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8690 struct irq_bypass_producer *prod)
8691{
8692 int ret;
8693 struct kvm_kernel_irqfd *irqfd =
8694 container_of(cons, struct kvm_kernel_irqfd, consumer);
8695
87276880
FW		 8696 WARN_ON(irqfd->producer != prod);
8697 irqfd->producer = NULL;
8698
8699 /*
8700 * When producer of consumer is unregistered, we change back to
8701 * remapped mode, so we can re-use the current implementation
bb3541f1 8702 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8703 * int this case doesn't want to receive the interrupts.
8704 */
8705 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8706 if (ret)
8707 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8708 " fails: %d\n", irqfd->consumer.token, ret);
8709}
8710
8711int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8712 uint32_t guest_irq, bool set)
8713{
8714 if (!kvm_x86_ops->update_pi_irte)
8715 return -EINVAL;
8716
8717 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8718}
8719
52004014
FW		 8720bool kvm_vector_hashing_enabled(void)
8721{
8722 return vector_hashing;
8723}
8724EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8725
229456fc 8726EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8727EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8728EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8729EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8730EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8731EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8732EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8733EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8734EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8735EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8736EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8737EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8738EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8739EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8740EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8741EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8742EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8743EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8744EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
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