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KVM: x86: add kvm_fast_pio() to consolidate fast PIO code
[mirror_ubuntu-focal-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
b0c39dc6 70#include <asm/mshyperv.h>
0092e434 71#include <asm/hypervisor.h>
043405e1 72
d1898b73
DH		 73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
313a3dc7 76#define MAX_IO_MSRS 256
890ca9ae 77#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 80
0f65dd70
AK		 81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
50a37eb4
JR		 84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
1260edbe
LJ		 89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 91#else
1260edbe 92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 93#endif
313a3dc7 94
ba1389b7
AK		 95#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 97
c519265f
RK		 98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 100
cb142eb7 101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 102static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 103static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 105static void store_regs(struct kvm_vcpu *vcpu);
106static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 107
893590c7 108struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 109EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 110
893590c7 111static bool __read_mostly ignore_msrs = 0;
476bc001 112module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 113
fab0aa3b
EM		 114static bool __read_mostly report_ignored_msrs = true;
115module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
116
9ed96e87
MT		 117unsigned int min_timer_period_us = 500;
118module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
119
630994b3
MT		 120static bool __read_mostly kvmclock_periodic_sync = true;
121module_param(kvmclock_periodic_sync, bool, S_IRUGO);
122
893590c7 123bool __read_mostly kvm_has_tsc_control;
92a1f12d 124EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 125u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 126EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 127u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129u64 __read_mostly kvm_max_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 131u64 __read_mostly kvm_default_tsc_scaling_ratio;
132EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 133
cc578287 134/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 135static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 136module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
137
d0659d94 138/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 139unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 140module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
141
52004014
FW		 142static bool __read_mostly vector_hashing = true;
143module_param(vector_hashing, bool, S_IRUGO);
144
18863bdd
AK		 145#define KVM_NR_SHARED_MSRS 16
146
147struct kvm_shared_msrs_global {
148 int nr;
2bf78fa7 149 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 150};
151
152struct kvm_shared_msrs {
153 struct user_return_notifier urn;
154 bool registered;
2bf78fa7
SY		 155 struct kvm_shared_msr_values {
156 u64 host;
157 u64 curr;
158 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 159};
160
161static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 162static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 163
417bc304 164struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 165 { "pf_fixed", VCPU_STAT(pf_fixed) },
166 { "pf_guest", VCPU_STAT(pf_guest) },
167 { "tlb_flush", VCPU_STAT(tlb_flush) },
168 { "invlpg", VCPU_STAT(invlpg) },
169 { "exits", VCPU_STAT(exits) },
170 { "io_exits", VCPU_STAT(io_exits) },
171 { "mmio_exits", VCPU_STAT(mmio_exits) },
172 { "signal_exits", VCPU_STAT(signal_exits) },
173 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 174 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 175 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 176 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 177 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 178 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 179 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 180 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 181 { "request_irq", VCPU_STAT(request_irq_exits) },
182 { "irq_exits", VCPU_STAT(irq_exits) },
183 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 184 { "fpu_reload", VCPU_STAT(fpu_reload) },
185 { "insn_emulation", VCPU_STAT(insn_emulation) },
186 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 187 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 188 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 189 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 190 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
191 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
192 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
193 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
194 { "mmu_flooded", VM_STAT(mmu_flooded) },
195 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 196 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 197 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 198 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 199 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 200 { "max_mmu_page_hash_collisions",
201 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 202 { NULL }
203};
204
2acf923e
DC		 205u64 __read_mostly host_xcr0;
206
b6785def 207static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 208
af585b92
GN		 209static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
210{
211 int i;
212 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
213 vcpu->arch.apf.gfns[i] = ~0;
214}
215
18863bdd
AK		 216static void kvm_on_user_return(struct user_return_notifier *urn)
217{
218 unsigned slot;
18863bdd
AK		 219 struct kvm_shared_msrs *locals
220 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 221 struct kvm_shared_msr_values *values;
1650b4eb
IA		 222 unsigned long flags;
223
224 /*
225 * Disabling irqs at this point since the following code could be
226 * interrupted and executed through kvm_arch_hardware_disable()
227 */
228 local_irq_save(flags);
229 if (locals->registered) {
230 locals->registered = false;
231 user_return_notifier_unregister(urn);
232 }
233 local_irq_restore(flags);
18863bdd 234 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 235 values = &locals->values[slot];
236 if (values->host != values->curr) {
237 wrmsrl(shared_msrs_global.msrs[slot], values->host);
238 values->curr = values->host;
18863bdd
AK		 239 }
240 }
18863bdd
AK		 241}
242
2bf78fa7 243static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 244{
18863bdd 245 u64 value;
013f6a5d
MT		 246 unsigned int cpu = smp_processor_id();
247 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 248
2bf78fa7
SY		 249 /* only read, and nobody should modify it at this time,
250 * so don't need lock */
251 if (slot >= shared_msrs_global.nr) {
252 printk(KERN_ERR "kvm: invalid MSR slot!");
253 return;
254 }
255 rdmsrl_safe(msr, &value);
256 smsr->values[slot].host = value;
257 smsr->values[slot].curr = value;
258}
259
260void kvm_define_shared_msr(unsigned slot, u32 msr)
261{
0123be42 262 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 263 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 264 if (slot >= shared_msrs_global.nr)
265 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 266}
267EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
268
269static void kvm_shared_msr_cpu_online(void)
270{
271 unsigned i;
18863bdd
AK		 272
273 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 274 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 275}
276
8b3c3104 277int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 278{
013f6a5d
MT		 279 unsigned int cpu = smp_processor_id();
280 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 281 int err;
18863bdd 282
2bf78fa7 283 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 284 return 0;
2bf78fa7 285 smsr->values[slot].curr = value;
8b3c3104
AH		 286 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
287 if (err)
288 return 1;
289
18863bdd
AK		 290 if (!smsr->registered) {
291 smsr->urn.on_user_return = kvm_on_user_return;
292 user_return_notifier_register(&smsr->urn);
293 smsr->registered = true;
294 }
8b3c3104 295 return 0;
18863bdd
AK		 296}
297EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
298
13a34e06 299static void drop_user_return_notifiers(void)
3548bab5 300{
013f6a5d
MT		 301 unsigned int cpu = smp_processor_id();
302 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 303
304 if (smsr->registered)
305 kvm_on_user_return(&smsr->urn);
306}
307
6866b83e
CO		 308u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
309{
8a5a87d9 310 return vcpu->arch.apic_base;
6866b83e
CO		 311}
312EXPORT_SYMBOL_GPL(kvm_get_apic_base);
313
58cb628d
JK		 314int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
315{
316 u64 old_state = vcpu->arch.apic_base &
317 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
318 u64 new_state = msr_info->data &
319 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
d6321d49
RK		 320 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
321 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 322
d3802286
JM		 323 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
324 return 1;
58cb628d 325 if (!msr_info->host_initiated &&
d3802286 326 ((new_state == MSR_IA32_APICBASE_ENABLE &&
58cb628d
JK		 327 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
328 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
329 old_state == 0)))
330 return 1;
331
332 kvm_lapic_set_base(vcpu, msr_info->data);
333 return 0;
6866b83e
CO		 334}
335EXPORT_SYMBOL_GPL(kvm_set_apic_base);
336
2605fc21 337asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 338{
339 /* Fault while not rebooting. We want the trace. */
340 BUG();
341}
342EXPORT_SYMBOL_GPL(kvm_spurious_fault);
343
3fd28fce
ED		 344#define EXCPT_BENIGN 0
345#define EXCPT_CONTRIBUTORY 1
346#define EXCPT_PF 2
347
348static int exception_class(int vector)
349{
350 switch (vector) {
351 case PF_VECTOR:
352 return EXCPT_PF;
353 case DE_VECTOR:
354 case TS_VECTOR:
355 case NP_VECTOR:
356 case SS_VECTOR:
357 case GP_VECTOR:
358 return EXCPT_CONTRIBUTORY;
359 default:
360 break;
361 }
362 return EXCPT_BENIGN;
363}
364
d6e8c854
NA		 365#define EXCPT_FAULT 0
366#define EXCPT_TRAP 1
367#define EXCPT_ABORT 2
368#define EXCPT_INTERRUPT 3
369
370static int exception_type(int vector)
371{
372 unsigned int mask;
373
374 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
375 return EXCPT_INTERRUPT;
376
377 mask = 1 << vector;
378
379 /* #DB is trap, as instruction watchpoints are handled elsewhere */
380 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
381 return EXCPT_TRAP;
382
383 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
384 return EXCPT_ABORT;
385
386 /* Reserved exceptions will result in fault */
387 return EXCPT_FAULT;
388}
389
3fd28fce 390static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 391 unsigned nr, bool has_error, u32 error_code,
392 bool reinject)
3fd28fce
ED		 393{
394 u32 prev_nr;
395 int class1, class2;
396
3842d135
AK		 397 kvm_make_request(KVM_REQ_EVENT, vcpu);
398
664f8e26 399 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 400 queue:
3ffb2468
NA		 401 if (has_error && !is_protmode(vcpu))
402 has_error = false;
664f8e26
WL		 403 if (reinject) {
404 /*
405 * On vmentry, vcpu->arch.exception.pending is only
406 * true if an event injection was blocked by
407 * nested_run_pending. In that case, however,
408 * vcpu_enter_guest requests an immediate exit,
409 * and the guest shouldn't proceed far enough to
410 * need reinjection.
411 */
412 WARN_ON_ONCE(vcpu->arch.exception.pending);
413 vcpu->arch.exception.injected = true;
414 } else {
415 vcpu->arch.exception.pending = true;
416 vcpu->arch.exception.injected = false;
417 }
3fd28fce
ED		 418 vcpu->arch.exception.has_error_code = has_error;
419 vcpu->arch.exception.nr = nr;
420 vcpu->arch.exception.error_code = error_code;
421 return;
422 }
423
424 /* to check exception */
425 prev_nr = vcpu->arch.exception.nr;
426 if (prev_nr == DF_VECTOR) {
427 /* triple fault -> shutdown */
a8eeb04a 428 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 429 return;
430 }
431 class1 = exception_class(prev_nr);
432 class2 = exception_class(nr);
433 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
434 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 435 /*
436 * Generate double fault per SDM Table 5-5. Set
437 * exception.pending = true so that the double fault
438 * can trigger a nested vmexit.
439 */
3fd28fce 440 vcpu->arch.exception.pending = true;
664f8e26 441 vcpu->arch.exception.injected = false;
3fd28fce
ED		 442 vcpu->arch.exception.has_error_code = true;
443 vcpu->arch.exception.nr = DF_VECTOR;
444 vcpu->arch.exception.error_code = 0;
445 } else
446 /* replace previous exception with a new one in a hope
447 that instruction re-execution will regenerate lost
448 exception */
449 goto queue;
450}
451
298101da
AK		 452void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
453{
ce7ddec4 454 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 455}
456EXPORT_SYMBOL_GPL(kvm_queue_exception);
457
ce7ddec4
JR		 458void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
459{
460 kvm_multiple_exception(vcpu, nr, false, 0, true);
461}
462EXPORT_SYMBOL_GPL(kvm_requeue_exception);
463
6affcbed 464int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 465{
db8fcefa
AP		 466 if (err)
467 kvm_inject_gp(vcpu, 0);
468 else
6affcbed
KH		 469 return kvm_skip_emulated_instruction(vcpu);
470
471 return 1;
db8fcefa
AP		 472}
473EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 474
6389ee94 475void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 476{
477 ++vcpu->stat.pf_guest;
adfe20fb
WL		 478 vcpu->arch.exception.nested_apf =
479 is_guest_mode(vcpu) && fault->async_page_fault;
480 if (vcpu->arch.exception.nested_apf)
481 vcpu->arch.apf.nested_apf_token = fault->address;
482 else
483 vcpu->arch.cr2 = fault->address;
6389ee94 484 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 485}
27d6c865 486EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 487
ef54bcfe 488static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 489{
6389ee94
AK		 490 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
491 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 492 else
6389ee94 493 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 494
495 return fault->nested_page_fault;
d4f8cf66
JR		 496}
497
3419ffc8
SY		 498void kvm_inject_nmi(struct kvm_vcpu *vcpu)
499{
7460fb4a
AK		 500 atomic_inc(&vcpu->arch.nmi_queued);
501 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 502}
503EXPORT_SYMBOL_GPL(kvm_inject_nmi);
504
298101da
AK		 505void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
506{
ce7ddec4 507 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 508}
509EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
510
ce7ddec4
JR		 511void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
512{
513 kvm_multiple_exception(vcpu, nr, true, error_code, true);
514}
515EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
516
0a79b009
AK		 517/*
518 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
519 * a #GP and return false.
520 */
521bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 522{
0a79b009
AK		 523 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
524 return true;
525 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
526 return false;
298101da 527}
0a79b009 528EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 529
16f8a6f9
NA		 530bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
531{
532 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
533 return true;
534
535 kvm_queue_exception(vcpu, UD_VECTOR);
536 return false;
537}
538EXPORT_SYMBOL_GPL(kvm_require_dr);
539
ec92fe44
JR		 540/*
541 * This function will be used to read from the physical memory of the currently
54bf36aa 542 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 543 * can read from guest physical or from the guest's guest physical memory.
544 */
545int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
546 gfn_t ngfn, void *data, int offset, int len,
547 u32 access)
548{
54987b7a 549 struct x86_exception exception;
ec92fe44
JR		 550 gfn_t real_gfn;
551 gpa_t ngpa;
552
553 ngpa = gfn_to_gpa(ngfn);
54987b7a 554 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 555 if (real_gfn == UNMAPPED_GVA)
556 return -EFAULT;
557
558 real_gfn = gpa_to_gfn(real_gfn);
559
54bf36aa 560 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 561}
562EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
563
69b0049a 564static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 565 void *data, int offset, int len, u32 access)
566{
567 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
568 data, offset, len, access);
569}
570
a03490ed
CO		 571/*
572 * Load the pae pdptrs. Return true is they are all valid.
573 */
ff03a073 574int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 575{
576 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
577 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
578 int i;
579 int ret;
ff03a073 580 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 581
ff03a073
JR		 582 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
583 offset * sizeof(u64), sizeof(pdpte),
584 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 585 if (ret < 0) {
586 ret = 0;
587 goto out;
588 }
589 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 590 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 591 (pdpte[i] &
592 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 593 ret = 0;
594 goto out;
595 }
596 }
597 ret = 1;
598
ff03a073 599 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 600 __set_bit(VCPU_EXREG_PDPTR,
601 (unsigned long *)&vcpu->arch.regs_avail);
602 __set_bit(VCPU_EXREG_PDPTR,
603 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 604out:
a03490ed
CO		 605
606 return ret;
607}
cc4b6871 608EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 609
9ed38ffa 610bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 611{
ff03a073 612 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 613 bool changed = true;
3d06b8bf
JR		 614 int offset;
615 gfn_t gfn;
d835dfec
AK		 616 int r;
617
618 if (is_long_mode(vcpu) || !is_pae(vcpu))
619 return false;
620
6de4f3ad
AK		 621 if (!test_bit(VCPU_EXREG_PDPTR,
622 (unsigned long *)&vcpu->arch.regs_avail))
623 return true;
624
a512177e
PB		 625 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
626 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 627 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
628 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 629 if (r < 0)
630 goto out;
ff03a073 631 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 632out:
d835dfec
AK		 633
634 return changed;
635}
9ed38ffa 636EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 637
49a9b07e 638int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 639{
aad82703 640 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 641 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 642
f9a48e6a
AK		 643 cr0 |= X86_CR0_ET;
644
ab344828 645#ifdef CONFIG_X86_64
0f12244f
GN		 646 if (cr0 & 0xffffffff00000000UL)
647 return 1;
ab344828
GN		 648#endif
649
650 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 651
0f12244f
GN		 652 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
653 return 1;
a03490ed 654
0f12244f
GN		 655 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
656 return 1;
a03490ed
CO		 657
658 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
659#ifdef CONFIG_X86_64
f6801dff 660 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 661 int cs_db, cs_l;
662
0f12244f
GN		 663 if (!is_pae(vcpu))
664 return 1;
a03490ed 665 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 666 if (cs_l)
667 return 1;
a03490ed
CO		 668 } else
669#endif
ff03a073 670 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 671 kvm_read_cr3(vcpu)))
0f12244f 672 return 1;
a03490ed
CO		 673 }
674
ad756a16
MJ		 675 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
676 return 1;
677
a03490ed 678 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 679
d170c419 680 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 681 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 682 kvm_async_pf_hash_reset(vcpu);
683 }
e5f3f027 684
aad82703
SY		 685 if ((cr0 ^ old_cr0) & update_bits)
686 kvm_mmu_reset_context(vcpu);
b18d5431 687
879ae188
LE		 688 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
689 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
690 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 691 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
692
0f12244f
GN		 693 return 0;
694}
2d3ad1f4 695EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 696
2d3ad1f4 697void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 698{
49a9b07e 699 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 700}
2d3ad1f4 701EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 702
42bdf991
MT		 703static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
704{
705 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
706 !vcpu->guest_xcr0_loaded) {
707 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 708 if (vcpu->arch.xcr0 != host_xcr0)
709 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 710 vcpu->guest_xcr0_loaded = 1;
711 }
712}
713
714static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
715{
716 if (vcpu->guest_xcr0_loaded) {
717 if (vcpu->arch.xcr0 != host_xcr0)
718 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
719 vcpu->guest_xcr0_loaded = 0;
720 }
721}
722
69b0049a 723static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 724{
56c103ec
LJ		 725 u64 xcr0 = xcr;
726 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 727 u64 valid_bits;
2acf923e
DC		 728
729 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
730 if (index != XCR_XFEATURE_ENABLED_MASK)
731 return 1;
d91cab78 732 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 733 return 1;
d91cab78 734 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 735 return 1;
46c34cb0
PB		 736
737 /*
738 * Do not allow the guest to set bits that we do not support
739 * saving. However, xcr0 bit 0 is always set, even if the
740 * emulated CPU does not support XSAVE (see fx_init).
741 */
d91cab78 742 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 743 if (xcr0 & ~valid_bits)
2acf923e 744 return 1;
46c34cb0 745
d91cab78
DH		 746 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
747 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 748 return 1;
749
d91cab78
DH		 750 if (xcr0 & XFEATURE_MASK_AVX512) {
751 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 752 return 1;
d91cab78 753 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 754 return 1;
755 }
2acf923e 756 vcpu->arch.xcr0 = xcr0;
56c103ec 757
d91cab78 758 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 759 kvm_update_cpuid(vcpu);
2acf923e
DC		 760 return 0;
761}
762
763int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
764{
764bcbc5
Z		 765 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
766 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 767 kvm_inject_gp(vcpu, 0);
768 return 1;
769 }
770 return 0;
771}
772EXPORT_SYMBOL_GPL(kvm_set_xcr);
773
a83b29c6 774int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 775{
fc78f519 776 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 777 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 778 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 779
0f12244f
GN		 780 if (cr4 & CR4_RESERVED_BITS)
781 return 1;
a03490ed 782
d6321d49 783 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 784 return 1;
785
d6321d49 786 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 787 return 1;
788
d6321d49 789 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 790 return 1;
791
d6321d49 792 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 793 return 1;
794
d6321d49 795 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 796 return 1;
797
fd8cb433 798 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 799 return 1;
800
ae3e61e1
PB		 801 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
802 return 1;
803
a03490ed 804 if (is_long_mode(vcpu)) {
0f12244f
GN		 805 if (!(cr4 & X86_CR4_PAE))
806 return 1;
a2edf57f
AK		 807 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
808 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 809 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
810 kvm_read_cr3(vcpu)))
0f12244f
GN		 811 return 1;
812
ad756a16 813 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 814 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 815 return 1;
816
817 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
818 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
819 return 1;
820 }
821
5e1746d6 822 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 823 return 1;
a03490ed 824
ad756a16
MJ		 825 if (((cr4 ^ old_cr4) & pdptr_bits) ||
826 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 827 kvm_mmu_reset_context(vcpu);
0f12244f 828
b9baba86 829 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 830 kvm_update_cpuid(vcpu);
2acf923e 831
0f12244f
GN		 832 return 0;
833}
2d3ad1f4 834EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 835
2390218b 836int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 837{
ac146235 838#ifdef CONFIG_X86_64
9d88fca7 839 cr3 &= ~CR3_PCID_INVD;
ac146235 840#endif
9d88fca7 841
9f8fe504 842 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 843 kvm_mmu_sync_roots(vcpu);
77c3913b 844 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 845 return 0;
d835dfec
AK		 846 }
847
d1cd3ce9
YZ		 848 if (is_long_mode(vcpu) &&
849 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62)))
850 return 1;
851 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 852 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 853 return 1;
a03490ed 854
0f12244f 855 vcpu->arch.cr3 = cr3;
aff48baa 856 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 857 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 858 return 0;
859}
2d3ad1f4 860EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 861
eea1cff9 862int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 863{
0f12244f
GN		 864 if (cr8 & CR8_RESERVED_BITS)
865 return 1;
35754c98 866 if (lapic_in_kernel(vcpu))
a03490ed
CO		 867 kvm_lapic_set_tpr(vcpu, cr8);
868 else
ad312c7c 869 vcpu->arch.cr8 = cr8;
0f12244f
GN		 870 return 0;
871}
2d3ad1f4 872EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 873
2d3ad1f4 874unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 875{
35754c98 876 if (lapic_in_kernel(vcpu))
a03490ed
CO		 877 return kvm_lapic_get_cr8(vcpu);
878 else
ad312c7c 879 return vcpu->arch.cr8;
a03490ed 880}
2d3ad1f4 881EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 882
ae561ede
NA		 883static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
884{
885 int i;
886
887 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
888 for (i = 0; i < KVM_NR_DB_REGS; i++)
889 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
890 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
891 }
892}
893
73aaf249
JK		 894static void kvm_update_dr6(struct kvm_vcpu *vcpu)
895{
896 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
897 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
898}
899
c8639010
JK		 900static void kvm_update_dr7(struct kvm_vcpu *vcpu)
901{
902 unsigned long dr7;
903
904 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
905 dr7 = vcpu->arch.guest_debug_dr7;
906 else
907 dr7 = vcpu->arch.dr7;
908 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 909 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
910 if (dr7 & DR7_BP_EN_MASK)
911 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 912}
913
6f43ed01
NA		 914static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
915{
916 u64 fixed = DR6_FIXED_1;
917
d6321d49 918 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 919 fixed |= DR6_RTM;
920 return fixed;
921}
922
338dbc97 923static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 924{
925 switch (dr) {
926 case 0 ... 3:
927 vcpu->arch.db[dr] = val;
928 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
929 vcpu->arch.eff_db[dr] = val;
930 break;
931 case 4:
020df079
GN		 932 /* fall through */
933 case 6:
338dbc97
GN		 934 if (val & 0xffffffff00000000ULL)
935 return -1; /* #GP */
6f43ed01 936 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 937 kvm_update_dr6(vcpu);
020df079
GN		 938 break;
939 case 5:
020df079
GN		 940 /* fall through */
941 default: /* 7 */
338dbc97
GN		 942 if (val & 0xffffffff00000000ULL)
943 return -1; /* #GP */
020df079 944 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 945 kvm_update_dr7(vcpu);
020df079
GN		 946 break;
947 }
948
949 return 0;
950}
338dbc97
GN		 951
952int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
953{
16f8a6f9 954 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 955 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 956 return 1;
957 }
958 return 0;
338dbc97 959}
020df079
GN		 960EXPORT_SYMBOL_GPL(kvm_set_dr);
961
16f8a6f9 962int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 963{
964 switch (dr) {
965 case 0 ... 3:
966 *val = vcpu->arch.db[dr];
967 break;
968 case 4:
020df079
GN		 969 /* fall through */
970 case 6:
73aaf249
JK		 971 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
972 *val = vcpu->arch.dr6;
973 else
974 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 975 break;
976 case 5:
020df079
GN		 977 /* fall through */
978 default: /* 7 */
979 *val = vcpu->arch.dr7;
980 break;
981 }
338dbc97
GN		 982 return 0;
983}
020df079
GN		 984EXPORT_SYMBOL_GPL(kvm_get_dr);
985
022cd0e8
AK		 986bool kvm_rdpmc(struct kvm_vcpu *vcpu)
987{
988 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
989 u64 data;
990 int err;
991
c6702c9d 992 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 993 if (err)
994 return err;
995 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
996 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
997 return err;
998}
999EXPORT_SYMBOL_GPL(kvm_rdpmc);
1000
043405e1
CO		 1001/*
1002 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1003 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1004 *
1005 * This list is modified at module load time to reflect the
e3267cbb 1006 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1007 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1008 * may depend on host virtualization features rather than host cpu features.
043405e1 1009 */
e3267cbb 1010
043405e1
CO		 1011static u32 msrs_to_save[] = {
1012 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1013 MSR_STAR,
043405e1
CO		 1014#ifdef CONFIG_X86_64
1015 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1016#endif
b3897a49 1017 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1018 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
d28b387f 1019 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
043405e1
CO		 1020};
1021
1022static unsigned num_msrs_to_save;
1023
62ef68bb
PB		 1024static u32 emulated_msrs[] = {
1025 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1026 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1027 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1028 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1029 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1030 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1031 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1032 HV_X64_MSR_RESET,
11c4b1ca 1033 HV_X64_MSR_VP_INDEX,
9eec50b8 1034 HV_X64_MSR_VP_RUNTIME,
5c919412 1035 HV_X64_MSR_SCONTROL,
1f4b34f8 1036 HV_X64_MSR_STIMER0_CONFIG,
a2e164e7
VK		 1037 HV_X64_MSR_APIC_ASSIST_PAGE,
1038 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1039 HV_X64_MSR_TSC_EMULATION_STATUS,
1040
1041 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1042 MSR_KVM_PV_EOI_EN,
1043
ba904635 1044 MSR_IA32_TSC_ADJUST,
a3e06bbe 1045 MSR_IA32_TSCDEADLINE,
043405e1 1046 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1047 MSR_IA32_MCG_STATUS,
1048 MSR_IA32_MCG_CTL,
c45dcc71 1049 MSR_IA32_MCG_EXT_CTL,
64d60670 1050 MSR_IA32_SMBASE,
52797bf9 1051 MSR_SMI_COUNT,
db2336a8
KH		 1052 MSR_PLATFORM_INFO,
1053 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1054};
1055
62ef68bb
PB		 1056static unsigned num_emulated_msrs;
1057
801e459a
TL		 1058/*
1059 * List of msr numbers which are used to expose MSR-based features that
1060 * can be used by a hypervisor to validate requested CPU features.
1061 */
1062static u32 msr_based_features[] = {
1389309c
PB		 1063 MSR_IA32_VMX_BASIC,
1064 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1065 MSR_IA32_VMX_PINBASED_CTLS,
1066 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1067 MSR_IA32_VMX_PROCBASED_CTLS,
1068 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1069 MSR_IA32_VMX_EXIT_CTLS,
1070 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1071 MSR_IA32_VMX_ENTRY_CTLS,
1072 MSR_IA32_VMX_MISC,
1073 MSR_IA32_VMX_CR0_FIXED0,
1074 MSR_IA32_VMX_CR0_FIXED1,
1075 MSR_IA32_VMX_CR4_FIXED0,
1076 MSR_IA32_VMX_CR4_FIXED1,
1077 MSR_IA32_VMX_VMCS_ENUM,
1078 MSR_IA32_VMX_PROCBASED_CTLS2,
1079 MSR_IA32_VMX_EPT_VPID_CAP,
1080 MSR_IA32_VMX_VMFUNC,
1081
d1d93fa9 1082 MSR_F10H_DECFG,
518e7b94 1083 MSR_IA32_UCODE_REV,
801e459a
TL		 1084};
1085
1086static unsigned int num_msr_based_features;
1087
66421c1e
WL		 1088static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1089{
1090 switch (msr->index) {
518e7b94
WL		 1091 case MSR_IA32_UCODE_REV:
1092 rdmsrl(msr->index, msr->data);
1093 break;
66421c1e
WL		 1094 default:
1095 if (kvm_x86_ops->get_msr_feature(msr))
1096 return 1;
1097 }
1098 return 0;
1099}
1100
801e459a
TL		 1101static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1102{
1103 struct kvm_msr_entry msr;
66421c1e 1104 int r;
801e459a
TL		 1105
1106 msr.index = index;
66421c1e
WL		 1107 r = kvm_get_msr_feature(&msr);
1108 if (r)
1109 return r;
801e459a
TL		 1110
1111 *data = msr.data;
1112
1113 return 0;
1114}
1115
384bb783 1116bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1117{
b69e8cae 1118 if (efer & efer_reserved_bits)
384bb783 1119 return false;
15c4a640 1120
1b4d56b8 1121 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1122 return false;
1b2fd70c 1123
1b4d56b8 1124 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1125 return false;
d8017474 1126
384bb783
JK		 1127 return true;
1128}
1129EXPORT_SYMBOL_GPL(kvm_valid_efer);
1130
1131static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1132{
1133 u64 old_efer = vcpu->arch.efer;
1134
1135 if (!kvm_valid_efer(vcpu, efer))
1136 return 1;
1137
1138 if (is_paging(vcpu)
1139 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1140 return 1;
1141
15c4a640 1142 efer &= ~EFER_LMA;
f6801dff 1143 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1144
a3d204e2
SY		 1145 kvm_x86_ops->set_efer(vcpu, efer);
1146
aad82703
SY		 1147 /* Update reserved bits */
1148 if ((efer ^ old_efer) & EFER_NX)
1149 kvm_mmu_reset_context(vcpu);
1150
b69e8cae 1151 return 0;
15c4a640
CO		 1152}
1153
f2b4b7dd
JR		 1154void kvm_enable_efer_bits(u64 mask)
1155{
1156 efer_reserved_bits &= ~mask;
1157}
1158EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1159
15c4a640
CO		 1160/*
1161 * Writes msr value into into the appropriate "register".
1162 * Returns 0 on success, non-0 otherwise.
1163 * Assumes vcpu_load() was already called.
1164 */
8fe8ab46 1165int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1166{
854e8bb1
NA		 1167 switch (msr->index) {
1168 case MSR_FS_BASE:
1169 case MSR_GS_BASE:
1170 case MSR_KERNEL_GS_BASE:
1171 case MSR_CSTAR:
1172 case MSR_LSTAR:
fd8cb433 1173 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1174 return 1;
1175 break;
1176 case MSR_IA32_SYSENTER_EIP:
1177 case MSR_IA32_SYSENTER_ESP:
1178 /*
1179 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1180 * non-canonical address is written on Intel but not on
1181 * AMD (which ignores the top 32-bits, because it does
1182 * not implement 64-bit SYSENTER).
1183 *
1184 * 64-bit code should hence be able to write a non-canonical
1185 * value on AMD. Making the address canonical ensures that
1186 * vmentry does not fail on Intel after writing a non-canonical
1187 * value, and that something deterministic happens if the guest
1188 * invokes 64-bit SYSENTER.
1189 */
fd8cb433 1190 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1191 }
8fe8ab46 1192 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1193}
854e8bb1 1194EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1195
313a3dc7
CO		 1196/*
1197 * Adapt set_msr() to msr_io()'s calling convention
1198 */
609e36d3
PB		 1199static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1200{
1201 struct msr_data msr;
1202 int r;
1203
1204 msr.index = index;
1205 msr.host_initiated = true;
1206 r = kvm_get_msr(vcpu, &msr);
1207 if (r)
1208 return r;
1209
1210 *data = msr.data;
1211 return 0;
1212}
1213
313a3dc7
CO		 1214static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1215{
8fe8ab46
WA		 1216 struct msr_data msr;
1217
1218 msr.data = *data;
1219 msr.index = index;
1220 msr.host_initiated = true;
1221 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1222}
1223
16e8d74d
MT		 1224#ifdef CONFIG_X86_64
1225struct pvclock_gtod_data {
1226 seqcount_t seq;
1227
1228 struct { /* extract of a clocksource struct */
1229 int vclock_mode;
a5a1d1c2
TG		 1230 u64 cycle_last;
1231 u64 mask;
16e8d74d
MT		 1232 u32 mult;
1233 u32 shift;
1234 } clock;
1235
cbcf2dd3
TG		 1236 u64 boot_ns;
1237 u64 nsec_base;
55dd00a7 1238 u64 wall_time_sec;
16e8d74d
MT		 1239};
1240
1241static struct pvclock_gtod_data pvclock_gtod_data;
1242
1243static void update_pvclock_gtod(struct timekeeper *tk)
1244{
1245 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1246 u64 boot_ns;
1247
876e7881 1248 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1249
1250 write_seqcount_begin(&vdata->seq);
1251
1252 /* copy pvclock gtod data */
876e7881
PZ		 1253 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1254 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1255 vdata->clock.mask = tk->tkr_mono.mask;
1256 vdata->clock.mult = tk->tkr_mono.mult;
1257 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1258
cbcf2dd3 1259 vdata->boot_ns = boot_ns;
876e7881 1260 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1261
55dd00a7
MT		 1262 vdata->wall_time_sec = tk->xtime_sec;
1263
16e8d74d
MT		 1264 write_seqcount_end(&vdata->seq);
1265}
1266#endif
1267
bab5bb39
NK		 1268void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1269{
1270 /*
1271 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1272 * vcpu_enter_guest. This function is only called from
1273 * the physical CPU that is running vcpu.
1274 */
1275 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1276}
16e8d74d 1277
18068523
GOC		 1278static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1279{
9ed3c444
AK		 1280 int version;
1281 int r;
50d0a0f9 1282 struct pvclock_wall_clock wc;
87aeb54f 1283 struct timespec64 boot;
18068523
GOC		 1284
1285 if (!wall_clock)
1286 return;
1287
9ed3c444
AK		 1288 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1289 if (r)
1290 return;
1291
1292 if (version & 1)
1293 ++version; /* first time write, random junk */
1294
1295 ++version;
18068523 1296
1dab1345
NK		 1297 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1298 return;
18068523 1299
50d0a0f9
GH		 1300 /*
1301 * The guest calculates current wall clock time by adding
34c238a1 1302 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1303 * wall clock specified here. guest system time equals host
1304 * system time for us, thus we must fill in host boot time here.
1305 */
87aeb54f 1306 getboottime64(&boot);
50d0a0f9 1307
4b648665 1308 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1309 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1310 boot = timespec64_sub(boot, ts);
4b648665 1311 }
87aeb54f 1312 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1313 wc.nsec = boot.tv_nsec;
1314 wc.version = version;
18068523
GOC		 1315
1316 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1317
1318 version++;
1319 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1320}
1321
50d0a0f9
GH		 1322static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1323{
b51012de
PB		 1324 do_shl32_div32(dividend, divisor);
1325 return dividend;
50d0a0f9
GH		 1326}
1327
3ae13faa 1328static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1329 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1330{
5f4e3f88 1331 uint64_t scaled64;
50d0a0f9
GH		 1332 int32_t shift = 0;
1333 uint64_t tps64;
1334 uint32_t tps32;
1335
3ae13faa
PB		 1336 tps64 = base_hz;
1337 scaled64 = scaled_hz;
50933623 1338 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1339 tps64 >>= 1;
1340 shift--;
1341 }
1342
1343 tps32 = (uint32_t)tps64;
50933623
JK		 1344 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1345 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1346 scaled64 >>= 1;
1347 else
1348 tps32 <<= 1;
50d0a0f9
GH		 1349 shift++;
1350 }
1351
5f4e3f88
ZA		 1352 *pshift = shift;
1353 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1354
3ae13faa
PB		 1355 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1356 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1357}
1358
d828199e 1359#ifdef CONFIG_X86_64
16e8d74d 1360static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1361#endif
16e8d74d 1362
c8076604 1363static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1364static unsigned long max_tsc_khz;
c8076604 1365
cc578287 1366static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1367{
cc578287
ZA		 1368 u64 v = (u64)khz * (1000000 + ppm);
1369 do_div(v, 1000000);
1370 return v;
1e993611
JR		 1371}
1372
381d585c
HZ		 1373static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1374{
1375 u64 ratio;
1376
1377 /* Guest TSC same frequency as host TSC? */
1378 if (!scale) {
1379 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1380 return 0;
1381 }
1382
1383 /* TSC scaling supported? */
1384 if (!kvm_has_tsc_control) {
1385 if (user_tsc_khz > tsc_khz) {
1386 vcpu->arch.tsc_catchup = 1;
1387 vcpu->arch.tsc_always_catchup = 1;
1388 return 0;
1389 } else {
1390 WARN(1, "user requested TSC rate below hardware speed\n");
1391 return -1;
1392 }
1393 }
1394
1395 /* TSC scaling required - calculate ratio */
1396 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1397 user_tsc_khz, tsc_khz);
1398
1399 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1400 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1401 user_tsc_khz);
1402 return -1;
1403 }
1404
1405 vcpu->arch.tsc_scaling_ratio = ratio;
1406 return 0;
1407}
1408
4941b8cb 1409static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1410{
cc578287
ZA		 1411 u32 thresh_lo, thresh_hi;
1412 int use_scaling = 0;
217fc9cf 1413
03ba32ca 1414 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1415 if (user_tsc_khz == 0) {
ad721883
HZ		 1416 /* set tsc_scaling_ratio to a safe value */
1417 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1418 return -1;
ad721883 1419 }
03ba32ca 1420
c285545f 1421 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1422 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1423 &vcpu->arch.virtual_tsc_shift,
1424 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1425 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1426
1427 /*
1428 * Compute the variation in TSC rate which is acceptable
1429 * within the range of tolerance and decide if the
1430 * rate being applied is within that bounds of the hardware
1431 * rate. If so, no scaling or compensation need be done.
1432 */
1433 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1434 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1435 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1436 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1437 use_scaling = 1;
1438 }
4941b8cb 1439 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1440}
1441
1442static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1443{
e26101b1 1444 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1445 vcpu->arch.virtual_tsc_mult,
1446 vcpu->arch.virtual_tsc_shift);
e26101b1 1447 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1448 return tsc;
1449}
1450
b0c39dc6
VK		 1451static inline int gtod_is_based_on_tsc(int mode)
1452{
1453 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1454}
1455
69b0049a 1456static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1457{
1458#ifdef CONFIG_X86_64
1459 bool vcpus_matched;
b48aa97e
MT		 1460 struct kvm_arch *ka = &vcpu->kvm->arch;
1461 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1462
1463 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1464 atomic_read(&vcpu->kvm->online_vcpus));
1465
7f187922
MT		 1466 /*
1467 * Once the masterclock is enabled, always perform request in
1468 * order to update it.
1469 *
1470 * In order to enable masterclock, the host clocksource must be TSC
1471 * and the vcpus need to have matched TSCs. When that happens,
1472 * perform request to enable masterclock.
1473 */
1474 if (ka->use_master_clock ||
b0c39dc6 1475 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1476 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1477
1478 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1479 atomic_read(&vcpu->kvm->online_vcpus),
1480 ka->use_master_clock, gtod->clock.vclock_mode);
1481#endif
1482}
1483
ba904635
WA		 1484static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1485{
3e3f5026 1486 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1487 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1488}
1489
35181e86
HZ		 1490/*
1491 * Multiply tsc by a fixed point number represented by ratio.
1492 *
1493 * The most significant 64-N bits (mult) of ratio represent the
1494 * integral part of the fixed point number; the remaining N bits
1495 * (frac) represent the fractional part, ie. ratio represents a fixed
1496 * point number (mult + frac * 2^(-N)).
1497 *
1498 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1499 */
1500static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1501{
1502 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1503}
1504
1505u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1506{
1507 u64 _tsc = tsc;
1508 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1509
1510 if (ratio != kvm_default_tsc_scaling_ratio)
1511 _tsc = __scale_tsc(ratio, tsc);
1512
1513 return _tsc;
1514}
1515EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1516
07c1419a
HZ		 1517static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1518{
1519 u64 tsc;
1520
1521 tsc = kvm_scale_tsc(vcpu, rdtsc());
1522
1523 return target_tsc - tsc;
1524}
1525
4ba76538
HZ		 1526u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1527{
ea26e4ec 1528 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1529}
1530EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1531
a545ab6a
LC		 1532static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1533{
1534 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1535 vcpu->arch.tsc_offset = offset;
1536}
1537
b0c39dc6
VK		 1538static inline bool kvm_check_tsc_unstable(void)
1539{
1540#ifdef CONFIG_X86_64
1541 /*
1542 * TSC is marked unstable when we're running on Hyper-V,
1543 * 'TSC page' clocksource is good.
1544 */
1545 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1546 return false;
1547#endif
1548 return check_tsc_unstable();
1549}
1550
8fe8ab46 1551void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1552{
1553 struct kvm *kvm = vcpu->kvm;
f38e098f 1554 u64 offset, ns, elapsed;
99e3e30a 1555 unsigned long flags;
b48aa97e 1556 bool matched;
0d3da0d2 1557 bool already_matched;
8fe8ab46 1558 u64 data = msr->data;
c5e8ec8e 1559 bool synchronizing = false;
99e3e30a 1560
038f8c11 1561 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1562 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1563 ns = ktime_get_boot_ns();
f38e098f 1564 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1565
03ba32ca 1566 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1567 if (data == 0 && msr->host_initiated) {
1568 /*
1569 * detection of vcpu initialization -- need to sync
1570 * with other vCPUs. This particularly helps to keep
1571 * kvm_clock stable after CPU hotplug
1572 */
1573 synchronizing = true;
1574 } else {
1575 u64 tsc_exp = kvm->arch.last_tsc_write +
1576 nsec_to_cycles(vcpu, elapsed);
1577 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1578 /*
1579 * Special case: TSC write with a small delta (1 second)
1580 * of virtual cycle time against real time is
1581 * interpreted as an attempt to synchronize the CPU.
1582 */
1583 synchronizing = data < tsc_exp + tsc_hz &&
1584 data + tsc_hz > tsc_exp;
1585 }
c5e8ec8e 1586 }
f38e098f
ZA		 1587
1588 /*
5d3cb0f6
ZA		 1589 * For a reliable TSC, we can match TSC offsets, and for an unstable
1590 * TSC, we add elapsed time in this computation. We could let the
1591 * compensation code attempt to catch up if we fall behind, but
1592 * it's better to try to match offsets from the beginning.
1593 */
c5e8ec8e 1594 if (synchronizing &&
5d3cb0f6 1595 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1596 if (!kvm_check_tsc_unstable()) {
e26101b1 1597 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1598 pr_debug("kvm: matched tsc offset for %llu\n", data);
1599 } else {
857e4099 1600 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1601 data += delta;
07c1419a 1602 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1603 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1604 }
b48aa97e 1605 matched = true;
0d3da0d2 1606 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1607 } else {
1608 /*
1609 * We split periods of matched TSC writes into generations.
1610 * For each generation, we track the original measured
1611 * nanosecond time, offset, and write, so if TSCs are in
1612 * sync, we can match exact offset, and if not, we can match
4a969980 1613 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1614 *
1615 * These values are tracked in kvm->arch.cur_xxx variables.
1616 */
1617 kvm->arch.cur_tsc_generation++;
1618 kvm->arch.cur_tsc_nsec = ns;
1619 kvm->arch.cur_tsc_write = data;
1620 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1621 matched = false;
0d3da0d2 1622 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1623 kvm->arch.cur_tsc_generation, data);
f38e098f 1624 }
e26101b1
ZA		 1625
1626 /*
1627 * We also track th most recent recorded KHZ, write and time to
1628 * allow the matching interval to be extended at each write.
1629 */
f38e098f
ZA		 1630 kvm->arch.last_tsc_nsec = ns;
1631 kvm->arch.last_tsc_write = data;
5d3cb0f6 1632 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1633
b183aa58 1634 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1635
1636 /* Keep track of which generation this VCPU has synchronized to */
1637 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1638 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1639 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1640
d6321d49 1641 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1642 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1643
a545ab6a 1644 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1645 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1646
1647 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1648 if (!matched) {
b48aa97e 1649 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1650 } else if (!already_matched) {
1651 kvm->arch.nr_vcpus_matched_tsc++;
1652 }
b48aa97e
MT		 1653
1654 kvm_track_tsc_matching(vcpu);
1655 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1656}
e26101b1 1657
99e3e30a
ZA		 1658EXPORT_SYMBOL_GPL(kvm_write_tsc);
1659
58ea6767
HZ		 1660static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1661 s64 adjustment)
1662{
ea26e4ec 1663 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1664}
1665
1666static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1667{
1668 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1669 WARN_ON(adjustment < 0);
1670 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1671 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1672}
1673
d828199e
MT		 1674#ifdef CONFIG_X86_64
1675
a5a1d1c2 1676static u64 read_tsc(void)
d828199e 1677{
a5a1d1c2 1678 u64 ret = (u64)rdtsc_ordered();
03b9730b 1679 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1680
1681 if (likely(ret >= last))
1682 return ret;
1683
1684 /*
1685 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1686 * predictable (it's just a function of time and the likely is
d828199e
MT		 1687 * very likely) and there's a data dependence, so force GCC
1688 * to generate a branch instead. I don't barrier() because
1689 * we don't actually need a barrier, and if this function
1690 * ever gets inlined it will generate worse code.
1691 */
1692 asm volatile ("");
1693 return last;
1694}
1695
b0c39dc6 1696static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1697{
1698 long v;
1699 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1700 u64 tsc_pg_val;
1701
1702 switch (gtod->clock.vclock_mode) {
1703 case VCLOCK_HVCLOCK:
1704 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1705 tsc_timestamp);
1706 if (tsc_pg_val != U64_MAX) {
1707 /* TSC page valid */
1708 *mode = VCLOCK_HVCLOCK;
1709 v = (tsc_pg_val - gtod->clock.cycle_last) &
1710 gtod->clock.mask;
1711 } else {
1712 /* TSC page invalid */
1713 *mode = VCLOCK_NONE;
1714 }
1715 break;
1716 case VCLOCK_TSC:
1717 *mode = VCLOCK_TSC;
1718 *tsc_timestamp = read_tsc();
1719 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1720 gtod->clock.mask;
1721 break;
1722 default:
1723 *mode = VCLOCK_NONE;
1724 }
d828199e 1725
b0c39dc6
VK		 1726 if (*mode == VCLOCK_NONE)
1727 *tsc_timestamp = v = 0;
d828199e 1728
d828199e
MT		 1729 return v * gtod->clock.mult;
1730}
1731
b0c39dc6 1732static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1733{
cbcf2dd3 1734 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1735 unsigned long seq;
d828199e 1736 int mode;
cbcf2dd3 1737 u64 ns;
d828199e 1738
d828199e
MT		 1739 do {
1740 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1741 ns = gtod->nsec_base;
b0c39dc6 1742 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1743 ns >>= gtod->clock.shift;
cbcf2dd3 1744 ns += gtod->boot_ns;
d828199e 1745 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1746 *t = ns;
d828199e
MT		 1747
1748 return mode;
1749}
1750
b0c39dc6 1751static int do_realtime(struct timespec *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1752{
1753 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1754 unsigned long seq;
1755 int mode;
1756 u64 ns;
1757
1758 do {
1759 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1760 ts->tv_sec = gtod->wall_time_sec;
1761 ns = gtod->nsec_base;
b0c39dc6 1762 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1763 ns >>= gtod->clock.shift;
1764 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1765
1766 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1767 ts->tv_nsec = ns;
1768
1769 return mode;
1770}
1771
b0c39dc6
VK		 1772/* returns true if host is using TSC based clocksource */
1773static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1774{
d828199e 1775 /* checked again under seqlock below */
b0c39dc6 1776 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1777 return false;
1778
b0c39dc6
VK		 1779 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1780 tsc_timestamp));
d828199e 1781}
55dd00a7 1782
b0c39dc6 1783/* returns true if host is using TSC based clocksource */
55dd00a7 1784static bool kvm_get_walltime_and_clockread(struct timespec *ts,
b0c39dc6 1785 u64 *tsc_timestamp)
55dd00a7
MT		 1786{
1787 /* checked again under seqlock below */
b0c39dc6 1788 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1789 return false;
1790
b0c39dc6 1791 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1792}
d828199e
MT		 1793#endif
1794
1795/*
1796 *
b48aa97e
MT		 1797 * Assuming a stable TSC across physical CPUS, and a stable TSC
1798 * across virtual CPUs, the following condition is possible.
1799 * Each numbered line represents an event visible to both
d828199e
MT		 1800 * CPUs at the next numbered event.
1801 *
1802 * "timespecX" represents host monotonic time. "tscX" represents
1803 * RDTSC value.
1804 *
1805 * VCPU0 on CPU0 | VCPU1 on CPU1
1806 *
1807 * 1. read timespec0,tsc0
1808 * 2. | timespec1 = timespec0 + N
1809 * | tsc1 = tsc0 + M
1810 * 3. transition to guest | transition to guest
1811 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1812 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1813 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1814 *
1815 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1816 *
1817 * - ret0 < ret1
1818 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1819 * ...
1820 * - 0 < N - M => M < N
1821 *
1822 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1823 * always the case (the difference between two distinct xtime instances
1824 * might be smaller then the difference between corresponding TSC reads,
1825 * when updating guest vcpus pvclock areas).
1826 *
1827 * To avoid that problem, do not allow visibility of distinct
1828 * system_timestamp/tsc_timestamp values simultaneously: use a master
1829 * copy of host monotonic time values. Update that master copy
1830 * in lockstep.
1831 *
b48aa97e 1832 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1833 *
1834 */
1835
1836static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1837{
1838#ifdef CONFIG_X86_64
1839 struct kvm_arch *ka = &kvm->arch;
1840 int vclock_mode;
b48aa97e
MT		 1841 bool host_tsc_clocksource, vcpus_matched;
1842
1843 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1844 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1845
1846 /*
1847 * If the host uses TSC clock, then passthrough TSC as stable
1848 * to the guest.
1849 */
b48aa97e 1850 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1851 &ka->master_kernel_ns,
1852 &ka->master_cycle_now);
1853
16a96021 1854 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1855 && !ka->backwards_tsc_observed
54750f2c 1856 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1857
d828199e
MT		 1858 if (ka->use_master_clock)
1859 atomic_set(&kvm_guest_has_master_clock, 1);
1860
1861 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1862 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1863 vcpus_matched);
d828199e
MT		 1864#endif
1865}
1866
2860c4b1
PB		 1867void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1868{
1869 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1870}
1871
2e762ff7
MT		 1872static void kvm_gen_update_masterclock(struct kvm *kvm)
1873{
1874#ifdef CONFIG_X86_64
1875 int i;
1876 struct kvm_vcpu *vcpu;
1877 struct kvm_arch *ka = &kvm->arch;
1878
1879 spin_lock(&ka->pvclock_gtod_sync_lock);
1880 kvm_make_mclock_inprogress_request(kvm);
1881 /* no guest entries from this point */
1882 pvclock_update_vm_gtod_copy(kvm);
1883
1884 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1885 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1886
1887 /* guest entries allowed */
1888 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1889 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1890
1891 spin_unlock(&ka->pvclock_gtod_sync_lock);
1892#endif
1893}
1894
e891a32e 1895u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1896{
108b249c 1897 struct kvm_arch *ka = &kvm->arch;
8b953440 1898 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1899 u64 ret;
108b249c 1900
8b953440
PB		 1901 spin_lock(&ka->pvclock_gtod_sync_lock);
1902 if (!ka->use_master_clock) {
1903 spin_unlock(&ka->pvclock_gtod_sync_lock);
1904 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1905 }
1906
8b953440
PB		 1907 hv_clock.tsc_timestamp = ka->master_cycle_now;
1908 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1909 spin_unlock(&ka->pvclock_gtod_sync_lock);
1910
e2c2206a
WL		 1911 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1912 get_cpu();
1913
e70b57a6
WL		 1914 if (__this_cpu_read(cpu_tsc_khz)) {
1915 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1916 &hv_clock.tsc_shift,
1917 &hv_clock.tsc_to_system_mul);
1918 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1919 } else
1920 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 1921
1922 put_cpu();
1923
1924 return ret;
108b249c
PB		 1925}
1926
0d6dd2ff
PB		 1927static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1928{
1929 struct kvm_vcpu_arch *vcpu = &v->arch;
1930 struct pvclock_vcpu_time_info guest_hv_clock;
1931
4e335d9e 1932 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1933 &guest_hv_clock, sizeof(guest_hv_clock))))
1934 return;
1935
1936 /* This VCPU is paused, but it's legal for a guest to read another
1937 * VCPU's kvmclock, so we really have to follow the specification where
1938 * it says that version is odd if data is being modified, and even after
1939 * it is consistent.
1940 *
1941 * Version field updates must be kept separate. This is because
1942 * kvm_write_guest_cached might use a "rep movs" instruction, and
1943 * writes within a string instruction are weakly ordered. So there
1944 * are three writes overall.
1945 *
1946 * As a small optimization, only write the version field in the first
1947 * and third write. The vcpu->pv_time cache is still valid, because the
1948 * version field is the first in the struct.
1949 */
1950 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1951
51c4b8bb
LA		 1952 if (guest_hv_clock.version & 1)
1953 ++guest_hv_clock.version; /* first time write, random junk */
1954
0d6dd2ff 1955 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1956 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1957 &vcpu->hv_clock,
1958 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1959
1960 smp_wmb();
1961
1962 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1963 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1964
1965 if (vcpu->pvclock_set_guest_stopped_request) {
1966 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1967 vcpu->pvclock_set_guest_stopped_request = false;
1968 }
1969
1970 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1971
4e335d9e
PB		 1972 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1973 &vcpu->hv_clock,
1974 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1975
1976 smp_wmb();
1977
1978 vcpu->hv_clock.version++;
4e335d9e
PB		 1979 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1980 &vcpu->hv_clock,
1981 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1982}
1983
34c238a1 1984static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1985{
78db6a50 1986 unsigned long flags, tgt_tsc_khz;
18068523 1987 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1988 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1989 s64 kernel_ns;
d828199e 1990 u64 tsc_timestamp, host_tsc;
51d59c6b 1991 u8 pvclock_flags;
d828199e
MT		 1992 bool use_master_clock;
1993
1994 kernel_ns = 0;
1995 host_tsc = 0;
18068523 1996
d828199e
MT		 1997 /*
1998 * If the host uses TSC clock, then passthrough TSC as stable
1999 * to the guest.
2000 */
2001 spin_lock(&ka->pvclock_gtod_sync_lock);
2002 use_master_clock = ka->use_master_clock;
2003 if (use_master_clock) {
2004 host_tsc = ka->master_cycle_now;
2005 kernel_ns = ka->master_kernel_ns;
2006 }
2007 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2008
2009 /* Keep irq disabled to prevent changes to the clock */
2010 local_irq_save(flags);
78db6a50
PB		 2011 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2012 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2013 local_irq_restore(flags);
2014 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2015 return 1;
2016 }
d828199e 2017 if (!use_master_clock) {
4ea1636b 2018 host_tsc = rdtsc();
108b249c 2019 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 2020 }
2021
4ba76538 2022 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2023
c285545f
ZA		 2024 /*
2025 * We may have to catch up the TSC to match elapsed wall clock
2026 * time for two reasons, even if kvmclock is used.
2027 * 1) CPU could have been running below the maximum TSC rate
2028 * 2) Broken TSC compensation resets the base at each VCPU
2029 * entry to avoid unknown leaps of TSC even when running
2030 * again on the same CPU. This may cause apparent elapsed
2031 * time to disappear, and the guest to stand still or run
2032 * very slowly.
2033 */
2034 if (vcpu->tsc_catchup) {
2035 u64 tsc = compute_guest_tsc(v, kernel_ns);
2036 if (tsc > tsc_timestamp) {
f1e2b260 2037 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2038 tsc_timestamp = tsc;
2039 }
50d0a0f9
GH		 2040 }
2041
18068523
GOC		 2042 local_irq_restore(flags);
2043
0d6dd2ff 2044 /* With all the info we got, fill in the values */
18068523 2045
78db6a50
PB		 2046 if (kvm_has_tsc_control)
2047 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2048
2049 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2050 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2051 &vcpu->hv_clock.tsc_shift,
2052 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2053 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2054 }
2055
1d5f066e 2056 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2057 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2058 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2059
d828199e 2060 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2061 pvclock_flags = 0;
d828199e
MT		 2062 if (use_master_clock)
2063 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2064
78c0337a
MT		 2065 vcpu->hv_clock.flags = pvclock_flags;
2066
095cf55d
PB		 2067 if (vcpu->pv_time_enabled)
2068 kvm_setup_pvclock_page(v);
2069 if (v == kvm_get_vcpu(v->kvm, 0))
2070 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2071 return 0;
c8076604
GH		 2072}
2073
0061d53d
MT		 2074/*
2075 * kvmclock updates which are isolated to a given vcpu, such as
2076 * vcpu->cpu migration, should not allow system_timestamp from
2077 * the rest of the vcpus to remain static. Otherwise ntp frequency
2078 * correction applies to one vcpu's system_timestamp but not
2079 * the others.
2080 *
2081 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2082 * We need to rate-limit these requests though, as they can
2083 * considerably slow guests that have a large number of vcpus.
2084 * The time for a remote vcpu to update its kvmclock is bound
2085 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2086 */
2087
7e44e449
AJ		 2088#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2089
2090static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2091{
2092 int i;
7e44e449
AJ		 2093 struct delayed_work *dwork = to_delayed_work(work);
2094 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2095 kvmclock_update_work);
2096 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2097 struct kvm_vcpu *vcpu;
2098
2099 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2100 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2101 kvm_vcpu_kick(vcpu);
2102 }
2103}
2104
7e44e449
AJ		 2105static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2106{
2107 struct kvm *kvm = v->kvm;
2108
105b21bb 2109 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2110 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2111 KVMCLOCK_UPDATE_DELAY);
2112}
2113
332967a3
AJ		 2114#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2115
2116static void kvmclock_sync_fn(struct work_struct *work)
2117{
2118 struct delayed_work *dwork = to_delayed_work(work);
2119 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2120 kvmclock_sync_work);
2121 struct kvm *kvm = container_of(ka, struct kvm, arch);
2122
630994b3
MT		 2123 if (!kvmclock_periodic_sync)
2124 return;
2125
332967a3
AJ		 2126 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2127 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2128 KVMCLOCK_SYNC_PERIOD);
2129}
2130
9ffd986c 2131static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2132{
890ca9ae
HY		 2133 u64 mcg_cap = vcpu->arch.mcg_cap;
2134 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2135 u32 msr = msr_info->index;
2136 u64 data = msr_info->data;
890ca9ae 2137
15c4a640 2138 switch (msr) {
15c4a640 2139 case MSR_IA32_MCG_STATUS:
890ca9ae 2140 vcpu->arch.mcg_status = data;
15c4a640 2141 break;
c7ac679c 2142 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2143 if (!(mcg_cap & MCG_CTL_P))
2144 return 1;
2145 if (data != 0 && data != ~(u64)0)
2146 return -1;
2147 vcpu->arch.mcg_ctl = data;
2148 break;
2149 default:
2150 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2151 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2152 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2153 /* only 0 or all 1s can be written to IA32_MCi_CTL
2154 * some Linux kernels though clear bit 10 in bank 4 to
2155 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2156 * this to avoid an uncatched #GP in the guest
2157 */
890ca9ae 2158 if ((offset & 0x3) == 0 &&
114be429 2159 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2160 return -1;
9ffd986c
WL		 2161 if (!msr_info->host_initiated &&
2162 (offset & 0x3) == 1 && data != 0)
2163 return -1;
890ca9ae
HY		 2164 vcpu->arch.mce_banks[offset] = data;
2165 break;
2166 }
2167 return 1;
2168 }
2169 return 0;
2170}
2171
ffde22ac
ES		 2172static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2173{
2174 struct kvm *kvm = vcpu->kvm;
2175 int lm = is_long_mode(vcpu);
2176 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2177 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2178 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2179 : kvm->arch.xen_hvm_config.blob_size_32;
2180 u32 page_num = data & ~PAGE_MASK;
2181 u64 page_addr = data & PAGE_MASK;
2182 u8 *page;
2183 int r;
2184
2185 r = -E2BIG;
2186 if (page_num >= blob_size)
2187 goto out;
2188 r = -ENOMEM;
ff5c2c03
SL		 2189 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2190 if (IS_ERR(page)) {
2191 r = PTR_ERR(page);
ffde22ac 2192 goto out;
ff5c2c03 2193 }
54bf36aa 2194 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2195 goto out_free;
2196 r = 0;
2197out_free:
2198 kfree(page);
2199out:
2200 return r;
2201}
2202
344d9588
GN		 2203static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2204{
2205 gpa_t gpa = data & ~0x3f;
2206
52a5c155
WL		 2207 /* Bits 3:5 are reserved, Should be zero */
2208 if (data & 0x38)
344d9588
GN		 2209 return 1;
2210
2211 vcpu->arch.apf.msr_val = data;
2212
2213 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2214 kvm_clear_async_pf_completion_queue(vcpu);
2215 kvm_async_pf_hash_reset(vcpu);
2216 return 0;
2217 }
2218
4e335d9e 2219 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2220 sizeof(u32)))
344d9588
GN		 2221 return 1;
2222
6adba527 2223 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2224 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2225 kvm_async_pf_wakeup_all(vcpu);
2226 return 0;
2227}
2228
12f9a48f
GC		 2229static void kvmclock_reset(struct kvm_vcpu *vcpu)
2230{
0b79459b 2231 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2232}
2233
f38a7b75
WL		 2234static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2235{
2236 ++vcpu->stat.tlb_flush;
2237 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2238}
2239
c9aaa895
GC		 2240static void record_steal_time(struct kvm_vcpu *vcpu)
2241{
2242 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2243 return;
2244
4e335d9e 2245 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2246 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2247 return;
2248
f38a7b75
WL		 2249 /*
2250 * Doing a TLB flush here, on the guest's behalf, can avoid
2251 * expensive IPIs.
2252 */
2253 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2254 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2255
35f3fae1
WL		 2256 if (vcpu->arch.st.steal.version & 1)
2257 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2258
2259 vcpu->arch.st.steal.version += 1;
2260
4e335d9e 2261 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2262 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2263
2264 smp_wmb();
2265
c54cdf14
LC		 2266 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2267 vcpu->arch.st.last_steal;
2268 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2269
4e335d9e 2270 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2271 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2272
2273 smp_wmb();
2274
2275 vcpu->arch.st.steal.version += 1;
c9aaa895 2276
4e335d9e 2277 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2278 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2279}
2280
8fe8ab46 2281int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2282{
5753785f 2283 bool pr = false;
8fe8ab46
WA		 2284 u32 msr = msr_info->index;
2285 u64 data = msr_info->data;
5753785f 2286
15c4a640 2287 switch (msr) {
2e32b719 2288 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2289 case MSR_IA32_UCODE_WRITE:
2290 case MSR_VM_HSAVE_PA:
2291 case MSR_AMD64_PATCH_LOADER:
2292 case MSR_AMD64_BU_CFG2:
405a353a 2293 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2294 break;
2295
518e7b94
WL		 2296 case MSR_IA32_UCODE_REV:
2297 if (msr_info->host_initiated)
2298 vcpu->arch.microcode_version = data;
2299 break;
15c4a640 2300 case MSR_EFER:
b69e8cae 2301 return set_efer(vcpu, data);
8f1589d9
AP		 2302 case MSR_K7_HWCR:
2303 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2304 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2305 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2306 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2307 if (data != 0) {
a737f256
CD		 2308 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2309 data);
8f1589d9
AP		 2310 return 1;
2311 }
15c4a640 2312 break;
f7c6d140
AP		 2313 case MSR_FAM10H_MMIO_CONF_BASE:
2314 if (data != 0) {
a737f256
CD		 2315 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2316 "0x%llx\n", data);
f7c6d140
AP		 2317 return 1;
2318 }
15c4a640 2319 break;
b5e2fec0
AG		 2320 case MSR_IA32_DEBUGCTLMSR:
2321 if (!data) {
2322 /* We support the non-activated case already */
2323 break;
2324 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2325 /* Values other than LBR and BTF are vendor-specific,
2326 thus reserved and should throw a #GP */
2327 return 1;
2328 }
a737f256
CD		 2329 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2330 __func__, data);
b5e2fec0 2331 break;
9ba075a6 2332 case 0x200 ... 0x2ff:
ff53604b 2333 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2334 case MSR_IA32_APICBASE:
58cb628d 2335 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2336 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2337 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2338 case MSR_IA32_TSCDEADLINE:
2339 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2340 break;
ba904635 2341 case MSR_IA32_TSC_ADJUST:
d6321d49 2342 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2343 if (!msr_info->host_initiated) {
d913b904 2344 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2345 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2346 }
2347 vcpu->arch.ia32_tsc_adjust_msr = data;
2348 }
2349 break;
15c4a640 2350 case MSR_IA32_MISC_ENABLE:
ad312c7c 2351 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2352 break;
64d60670
PB		 2353 case MSR_IA32_SMBASE:
2354 if (!msr_info->host_initiated)
2355 return 1;
2356 vcpu->arch.smbase = data;
2357 break;
52797bf9
LA		 2358 case MSR_SMI_COUNT:
2359 if (!msr_info->host_initiated)
2360 return 1;
2361 vcpu->arch.smi_count = data;
2362 break;
11c6bffa 2363 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2364 case MSR_KVM_WALL_CLOCK:
2365 vcpu->kvm->arch.wall_clock = data;
2366 kvm_write_wall_clock(vcpu->kvm, data);
2367 break;
11c6bffa 2368 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2369 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2370 struct kvm_arch *ka = &vcpu->kvm->arch;
2371
12f9a48f 2372 kvmclock_reset(vcpu);
18068523 2373
54750f2c
MT		 2374 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2375 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2376
2377 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2378 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2379
2380 ka->boot_vcpu_runs_old_kvmclock = tmp;
2381 }
2382
18068523 2383 vcpu->arch.time = data;
0061d53d 2384 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2385
2386 /* we verify if the enable bit is set... */
2387 if (!(data & 1))
2388 break;
2389
4e335d9e 2390 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2391 &vcpu->arch.pv_time, data & ~1ULL,
2392 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2393 vcpu->arch.pv_time_enabled = false;
2394 else
2395 vcpu->arch.pv_time_enabled = true;
32cad84f 2396
18068523
GOC		 2397 break;
2398 }
344d9588
GN		 2399 case MSR_KVM_ASYNC_PF_EN:
2400 if (kvm_pv_enable_async_pf(vcpu, data))
2401 return 1;
2402 break;
c9aaa895
GC		 2403 case MSR_KVM_STEAL_TIME:
2404
2405 if (unlikely(!sched_info_on()))
2406 return 1;
2407
2408 if (data & KVM_STEAL_RESERVED_MASK)
2409 return 1;
2410
4e335d9e 2411 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2412 data & KVM_STEAL_VALID_BITS,
2413 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2414 return 1;
2415
2416 vcpu->arch.st.msr_val = data;
2417
2418 if (!(data & KVM_MSR_ENABLED))
2419 break;
2420
c9aaa895
GC		 2421 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2422
2423 break;
ae7a2a3f
MT		 2424 case MSR_KVM_PV_EOI_EN:
2425 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2426 return 1;
2427 break;
c9aaa895 2428
890ca9ae
HY		 2429 case MSR_IA32_MCG_CTL:
2430 case MSR_IA32_MCG_STATUS:
81760dcc 2431 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2432 return set_msr_mce(vcpu, msr_info);
71db6023 2433
6912ac32
WH		 2434 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2435 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2436 pr = true; /* fall through */
2437 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2438 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2439 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2440 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2441
2442 if (pr || data != 0)
a737f256
CD		 2443 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2444 "0x%x data 0x%llx\n", msr, data);
5753785f 2445 break;
84e0cefa
JS		 2446 case MSR_K7_CLK_CTL:
2447 /*
2448 * Ignore all writes to this no longer documented MSR.
2449 * Writes are only relevant for old K7 processors,
2450 * all pre-dating SVM, but a recommended workaround from
4a969980 2451 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2452 * affected processor models on the command line, hence
2453 * the need to ignore the workaround.
2454 */
2455 break;
55cd8e5a 2456 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2457 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2458 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2459 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2460 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2461 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2462 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2463 return kvm_hv_set_msr_common(vcpu, msr, data,
2464 msr_info->host_initiated);
91c9c3ed 2465 case MSR_IA32_BBL_CR_CTL3:
2466 /* Drop writes to this legacy MSR -- see rdmsr
2467 * counterpart for further detail.
2468 */
fab0aa3b
EM		 2469 if (report_ignored_msrs)
2470 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2471 msr, data);
91c9c3ed 2472 break;
2b036c6b 2473 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2474 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2475 return 1;
2476 vcpu->arch.osvw.length = data;
2477 break;
2478 case MSR_AMD64_OSVW_STATUS:
d6321d49 2479 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2480 return 1;
2481 vcpu->arch.osvw.status = data;
2482 break;
db2336a8
KH		 2483 case MSR_PLATFORM_INFO:
2484 if (!msr_info->host_initiated ||
2485 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2486 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2487 cpuid_fault_enabled(vcpu)))
2488 return 1;
2489 vcpu->arch.msr_platform_info = data;
2490 break;
2491 case MSR_MISC_FEATURES_ENABLES:
2492 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2493 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2494 !supports_cpuid_fault(vcpu)))
2495 return 1;
2496 vcpu->arch.msr_misc_features_enables = data;
2497 break;
15c4a640 2498 default:
ffde22ac
ES		 2499 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2500 return xen_hvm_config(vcpu, data);
c6702c9d 2501 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2502 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2503 if (!ignore_msrs) {
ae0f5499 2504 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2505 msr, data);
ed85c068
AP		 2506 return 1;
2507 } else {
fab0aa3b
EM		 2508 if (report_ignored_msrs)
2509 vcpu_unimpl(vcpu,
2510 "ignored wrmsr: 0x%x data 0x%llx\n",
2511 msr, data);
ed85c068
AP		 2512 break;
2513 }
15c4a640
CO		 2514 }
2515 return 0;
2516}
2517EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2518
2519
2520/*
2521 * Reads an msr value (of 'msr_index') into 'pdata'.
2522 * Returns 0 on success, non-0 otherwise.
2523 * Assumes vcpu_load() was already called.
2524 */
609e36d3 2525int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2526{
609e36d3 2527 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2528}
ff651cb6 2529EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2530
890ca9ae 2531static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2532{
2533 u64 data;
890ca9ae
HY		 2534 u64 mcg_cap = vcpu->arch.mcg_cap;
2535 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2536
2537 switch (msr) {
15c4a640
CO		 2538 case MSR_IA32_P5_MC_ADDR:
2539 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2540 data = 0;
2541 break;
15c4a640 2542 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2543 data = vcpu->arch.mcg_cap;
2544 break;
c7ac679c 2545 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2546 if (!(mcg_cap & MCG_CTL_P))
2547 return 1;
2548 data = vcpu->arch.mcg_ctl;
2549 break;
2550 case MSR_IA32_MCG_STATUS:
2551 data = vcpu->arch.mcg_status;
2552 break;
2553 default:
2554 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2555 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2556 u32 offset = msr - MSR_IA32_MC0_CTL;
2557 data = vcpu->arch.mce_banks[offset];
2558 break;
2559 }
2560 return 1;
2561 }
2562 *pdata = data;
2563 return 0;
2564}
2565
609e36d3 2566int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2567{
609e36d3 2568 switch (msr_info->index) {
890ca9ae 2569 case MSR_IA32_PLATFORM_ID:
15c4a640 2570 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2571 case MSR_IA32_DEBUGCTLMSR:
2572 case MSR_IA32_LASTBRANCHFROMIP:
2573 case MSR_IA32_LASTBRANCHTOIP:
2574 case MSR_IA32_LASTINTFROMIP:
2575 case MSR_IA32_LASTINTTOIP:
60af2ecd 2576 case MSR_K8_SYSCFG:
3afb1121
PB		 2577 case MSR_K8_TSEG_ADDR:
2578 case MSR_K8_TSEG_MASK:
60af2ecd 2579 case MSR_K7_HWCR:
61a6bd67 2580 case MSR_VM_HSAVE_PA:
1fdbd48c 2581 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2582 case MSR_AMD64_NB_CFG:
f7c6d140 2583 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2584 case MSR_AMD64_BU_CFG2:
0c2df2a1 2585 case MSR_IA32_PERF_CTL:
405a353a 2586 case MSR_AMD64_DC_CFG:
609e36d3 2587 msr_info->data = 0;
15c4a640 2588 break;
c51eb52b 2589 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2590 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2591 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2592 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2593 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2594 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2595 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2596 msr_info->data = 0;
5753785f 2597 break;
742bc670 2598 case MSR_IA32_UCODE_REV:
518e7b94 2599 msr_info->data = vcpu->arch.microcode_version;
742bc670 2600 break;
9ba075a6 2601 case MSR_MTRRcap:
9ba075a6 2602 case 0x200 ... 0x2ff:
ff53604b 2603 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2604 case 0xcd: /* fsb frequency */
609e36d3 2605 msr_info->data = 3;
15c4a640 2606 break;
7b914098
JS		 2607 /*
2608 * MSR_EBC_FREQUENCY_ID
2609 * Conservative value valid for even the basic CPU models.
2610 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2611 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2612 * and 266MHz for model 3, or 4. Set Core Clock
2613 * Frequency to System Bus Frequency Ratio to 1 (bits
2614 * 31:24) even though these are only valid for CPU
2615 * models > 2, however guests may end up dividing or
2616 * multiplying by zero otherwise.
2617 */
2618 case MSR_EBC_FREQUENCY_ID:
609e36d3 2619 msr_info->data = 1 << 24;
7b914098 2620 break;
15c4a640 2621 case MSR_IA32_APICBASE:
609e36d3 2622 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2623 break;
0105d1a5 2624 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2625 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2626 break;
a3e06bbe 2627 case MSR_IA32_TSCDEADLINE:
609e36d3 2628 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2629 break;
ba904635 2630 case MSR_IA32_TSC_ADJUST:
609e36d3 2631 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2632 break;
15c4a640 2633 case MSR_IA32_MISC_ENABLE:
609e36d3 2634 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2635 break;
64d60670
PB		 2636 case MSR_IA32_SMBASE:
2637 if (!msr_info->host_initiated)
2638 return 1;
2639 msr_info->data = vcpu->arch.smbase;
15c4a640 2640 break;
52797bf9
LA		 2641 case MSR_SMI_COUNT:
2642 msr_info->data = vcpu->arch.smi_count;
2643 break;
847f0ad8
AG		 2644 case MSR_IA32_PERF_STATUS:
2645 /* TSC increment by tick */
609e36d3 2646 msr_info->data = 1000ULL;
847f0ad8 2647 /* CPU multiplier */
b0996ae4 2648 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2649 break;
15c4a640 2650 case MSR_EFER:
609e36d3 2651 msr_info->data = vcpu->arch.efer;
15c4a640 2652 break;
18068523 2653 case MSR_KVM_WALL_CLOCK:
11c6bffa 2654 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2655 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2656 break;
2657 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2658 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2659 msr_info->data = vcpu->arch.time;
18068523 2660 break;
344d9588 2661 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2662 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2663 break;
c9aaa895 2664 case MSR_KVM_STEAL_TIME:
609e36d3 2665 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2666 break;
1d92128f 2667 case MSR_KVM_PV_EOI_EN:
609e36d3 2668 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2669 break;
890ca9ae
HY		 2670 case MSR_IA32_P5_MC_ADDR:
2671 case MSR_IA32_P5_MC_TYPE:
2672 case MSR_IA32_MCG_CAP:
2673 case MSR_IA32_MCG_CTL:
2674 case MSR_IA32_MCG_STATUS:
81760dcc 2675 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2676 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2677 case MSR_K7_CLK_CTL:
2678 /*
2679 * Provide expected ramp-up count for K7. All other
2680 * are set to zero, indicating minimum divisors for
2681 * every field.
2682 *
2683 * This prevents guest kernels on AMD host with CPU
2684 * type 6, model 8 and higher from exploding due to
2685 * the rdmsr failing.
2686 */
609e36d3 2687 msr_info->data = 0x20000000;
84e0cefa 2688 break;
55cd8e5a 2689 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2690 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2691 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2692 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2693 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2694 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2695 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887
AS		 2696 return kvm_hv_get_msr_common(vcpu,
2697 msr_info->index, &msr_info->data);
55cd8e5a 2698 break;
91c9c3ed 2699 case MSR_IA32_BBL_CR_CTL3:
2700 /* This legacy MSR exists but isn't fully documented in current
2701 * silicon. It is however accessed by winxp in very narrow
2702 * scenarios where it sets bit #19, itself documented as
2703 * a "reserved" bit. Best effort attempt to source coherent
2704 * read data here should the balance of the register be
2705 * interpreted by the guest:
2706 *
2707 * L2 cache control register 3: 64GB range, 256KB size,
2708 * enabled, latency 0x1, configured
2709 */
609e36d3 2710 msr_info->data = 0xbe702111;
91c9c3ed 2711 break;
2b036c6b 2712 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2713 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2714 return 1;
609e36d3 2715 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2716 break;
2717 case MSR_AMD64_OSVW_STATUS:
d6321d49 2718 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2719 return 1;
609e36d3 2720 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2721 break;
db2336a8
KH		 2722 case MSR_PLATFORM_INFO:
2723 msr_info->data = vcpu->arch.msr_platform_info;
2724 break;
2725 case MSR_MISC_FEATURES_ENABLES:
2726 msr_info->data = vcpu->arch.msr_misc_features_enables;
2727 break;
15c4a640 2728 default:
c6702c9d 2729 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2730 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2731 if (!ignore_msrs) {
ae0f5499
BD		 2732 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2733 msr_info->index);
ed85c068
AP		 2734 return 1;
2735 } else {
fab0aa3b
EM		 2736 if (report_ignored_msrs)
2737 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2738 msr_info->index);
609e36d3 2739 msr_info->data = 0;
ed85c068
AP		 2740 }
2741 break;
15c4a640 2742 }
15c4a640
CO		 2743 return 0;
2744}
2745EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2746
313a3dc7
CO		 2747/*
2748 * Read or write a bunch of msrs. All parameters are kernel addresses.
2749 *
2750 * @return number of msrs set successfully.
2751 */
2752static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2753 struct kvm_msr_entry *entries,
2754 int (*do_msr)(struct kvm_vcpu *vcpu,
2755 unsigned index, u64 *data))
2756{
801e459a 2757 int i;
313a3dc7 2758
313a3dc7
CO		 2759 for (i = 0; i < msrs->nmsrs; ++i)
2760 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2761 break;
2762
313a3dc7
CO		 2763 return i;
2764}
2765
2766/*
2767 * Read or write a bunch of msrs. Parameters are user addresses.
2768 *
2769 * @return number of msrs set successfully.
2770 */
2771static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2772 int (*do_msr)(struct kvm_vcpu *vcpu,
2773 unsigned index, u64 *data),
2774 int writeback)
2775{
2776 struct kvm_msrs msrs;
2777 struct kvm_msr_entry *entries;
2778 int r, n;
2779 unsigned size;
2780
2781 r = -EFAULT;
2782 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2783 goto out;
2784
2785 r = -E2BIG;
2786 if (msrs.nmsrs >= MAX_IO_MSRS)
2787 goto out;
2788
313a3dc7 2789 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2790 entries = memdup_user(user_msrs->entries, size);
2791 if (IS_ERR(entries)) {
2792 r = PTR_ERR(entries);
313a3dc7 2793 goto out;
ff5c2c03 2794 }
313a3dc7
CO		 2795
2796 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2797 if (r < 0)
2798 goto out_free;
2799
2800 r = -EFAULT;
2801 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2802 goto out_free;
2803
2804 r = n;
2805
2806out_free:
7a73c028 2807 kfree(entries);
313a3dc7
CO		 2808out:
2809 return r;
2810}
2811
784aa3d7 2812int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2813{
2814 int r;
2815
2816 switch (ext) {
2817 case KVM_CAP_IRQCHIP:
2818 case KVM_CAP_HLT:
2819 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2820 case KVM_CAP_SET_TSS_ADDR:
07716717 2821 case KVM_CAP_EXT_CPUID:
9c15bb1d 2822 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2823 case KVM_CAP_CLOCKSOURCE:
7837699f 2824 case KVM_CAP_PIT:
a28e4f5a 2825 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2826 case KVM_CAP_MP_STATE:
ed848624 2827 case KVM_CAP_SYNC_MMU:
a355c85c 2828 case KVM_CAP_USER_NMI:
52d939a0 2829 case KVM_CAP_REINJECT_CONTROL:
4925663a 2830 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2831 case KVM_CAP_IOEVENTFD:
f848a5a8 2832 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2833 case KVM_CAP_PIT2:
e9f42757 2834 case KVM_CAP_PIT_STATE2:
b927a3ce 2835 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2836 case KVM_CAP_XEN_HVM:
3cfc3092 2837 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2838 case KVM_CAP_HYPERV:
10388a07 2839 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2840 case KVM_CAP_HYPERV_SPIN:
5c919412 2841 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2842 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2843 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 2844 case KVM_CAP_HYPERV_EVENTFD:
ab9f4ecb 2845 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2846 case KVM_CAP_DEBUGREGS:
d2be1651 2847 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2848 case KVM_CAP_XSAVE:
344d9588 2849 case KVM_CAP_ASYNC_PF:
92a1f12d 2850 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2851 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2852 case KVM_CAP_READONLY_MEM:
5f66b620 2853 case KVM_CAP_HYPERV_TIME:
100943c5 2854 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2855 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2856 case KVM_CAP_ENABLE_CAP_VM:
2857 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2858 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2859 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2860 case KVM_CAP_IMMEDIATE_EXIT:
801e459a 2861 case KVM_CAP_GET_MSR_FEATURES:
018d00d2
ZX		 2862 r = 1;
2863 break;
01643c51
KH		 2864 case KVM_CAP_SYNC_REGS:
2865 r = KVM_SYNC_X86_VALID_FIELDS;
2866 break;
e3fd9a93
PB		 2867 case KVM_CAP_ADJUST_CLOCK:
2868 r = KVM_CLOCK_TSC_STABLE;
2869 break;
668fffa3
MT		 2870 case KVM_CAP_X86_GUEST_MWAIT:
2871 r = kvm_mwait_in_guest();
2872 break;
6d396b55
PB		 2873 case KVM_CAP_X86_SMM:
2874 /* SMBASE is usually relocated above 1M on modern chipsets,
2875 * and SMM handlers might indeed rely on 4G segment limits,
2876 * so do not report SMM to be available if real mode is
2877 * emulated via vm86 mode. Still, do not go to great lengths
2878 * to avoid userspace's usage of the feature, because it is a
2879 * fringe case that is not enabled except via specific settings
2880 * of the module parameters.
2881 */
2882 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2883 break;
774ead3a
AK		 2884 case KVM_CAP_VAPIC:
2885 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2886 break;
f725230a 2887 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2888 r = KVM_SOFT_MAX_VCPUS;
2889 break;
2890 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2891 r = KVM_MAX_VCPUS;
2892 break;
a988b910 2893 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2894 r = KVM_USER_MEM_SLOTS;
a988b910 2895 break;
a68a6a72
MT		 2896 case KVM_CAP_PV_MMU: /* obsolete */
2897 r = 0;
2f333bcb 2898 break;
890ca9ae
HY		 2899 case KVM_CAP_MCE:
2900 r = KVM_MAX_MCE_BANKS;
2901 break;
2d5b5a66 2902 case KVM_CAP_XCRS:
d366bf7e 2903 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2904 break;
92a1f12d
JR		 2905 case KVM_CAP_TSC_CONTROL:
2906 r = kvm_has_tsc_control;
2907 break;
37131313
RK		 2908 case KVM_CAP_X2APIC_API:
2909 r = KVM_X2APIC_API_VALID_FLAGS;
2910 break;
018d00d2
ZX		 2911 default:
2912 r = 0;
2913 break;
2914 }
2915 return r;
2916
2917}
2918
043405e1
CO		 2919long kvm_arch_dev_ioctl(struct file *filp,
2920 unsigned int ioctl, unsigned long arg)
2921{
2922 void __user *argp = (void __user *)arg;
2923 long r;
2924
2925 switch (ioctl) {
2926 case KVM_GET_MSR_INDEX_LIST: {
2927 struct kvm_msr_list __user *user_msr_list = argp;
2928 struct kvm_msr_list msr_list;
2929 unsigned n;
2930
2931 r = -EFAULT;
2932 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2933 goto out;
2934 n = msr_list.nmsrs;
62ef68bb 2935 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2936 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2937 goto out;
2938 r = -E2BIG;
e125e7b6 2939 if (n < msr_list.nmsrs)
043405e1
CO		 2940 goto out;
2941 r = -EFAULT;
2942 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2943 num_msrs_to_save * sizeof(u32)))
2944 goto out;
e125e7b6 2945 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2946 &emulated_msrs,
62ef68bb 2947 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2948 goto out;
2949 r = 0;
2950 break;
2951 }
9c15bb1d
BP		 2952 case KVM_GET_SUPPORTED_CPUID:
2953 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2954 struct kvm_cpuid2 __user *cpuid_arg = argp;
2955 struct kvm_cpuid2 cpuid;
2956
2957 r = -EFAULT;
2958 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2959 goto out;
9c15bb1d
BP		 2960
2961 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2962 ioctl);
674eea0f
AK		 2963 if (r)
2964 goto out;
2965
2966 r = -EFAULT;
2967 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2968 goto out;
2969 r = 0;
2970 break;
2971 }
890ca9ae 2972 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2973 r = -EFAULT;
c45dcc71
AR		 2974 if (copy_to_user(argp, &kvm_mce_cap_supported,
2975 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2976 goto out;
2977 r = 0;
2978 break;
801e459a
TL		 2979 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
2980 struct kvm_msr_list __user *user_msr_list = argp;
2981 struct kvm_msr_list msr_list;
2982 unsigned int n;
2983
2984 r = -EFAULT;
2985 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
2986 goto out;
2987 n = msr_list.nmsrs;
2988 msr_list.nmsrs = num_msr_based_features;
2989 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
2990 goto out;
2991 r = -E2BIG;
2992 if (n < msr_list.nmsrs)
2993 goto out;
2994 r = -EFAULT;
2995 if (copy_to_user(user_msr_list->indices, &msr_based_features,
2996 num_msr_based_features * sizeof(u32)))
2997 goto out;
2998 r = 0;
2999 break;
3000 }
3001 case KVM_GET_MSRS:
3002 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3003 break;
890ca9ae 3004 }
043405e1
CO		 3005 default:
3006 r = -EINVAL;
3007 }
3008out:
3009 return r;
3010}
3011
f5f48ee1
SY		 3012static void wbinvd_ipi(void *garbage)
3013{
3014 wbinvd();
3015}
3016
3017static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3018{
e0f0bbc5 3019 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3020}
3021
313a3dc7
CO		 3022void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3023{
f5f48ee1
SY		 3024 /* Address WBINVD may be executed by guest */
3025 if (need_emulate_wbinvd(vcpu)) {
3026 if (kvm_x86_ops->has_wbinvd_exit())
3027 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3028 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3029 smp_call_function_single(vcpu->cpu,
3030 wbinvd_ipi, NULL, 1);
3031 }
3032
313a3dc7 3033 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3034
0dd6a6ed
ZA		 3035 /* Apply any externally detected TSC adjustments (due to suspend) */
3036 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3037 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3038 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3039 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3040 }
8f6055cb 3041
b0c39dc6 3042 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3043 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3044 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3045 if (tsc_delta < 0)
3046 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3047
b0c39dc6 3048 if (kvm_check_tsc_unstable()) {
07c1419a 3049 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3050 vcpu->arch.last_guest_tsc);
a545ab6a 3051 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3052 vcpu->arch.tsc_catchup = 1;
c285545f 3053 }
a749e247
PB		 3054
3055 if (kvm_lapic_hv_timer_in_use(vcpu))
3056 kvm_lapic_restart_hv_timer(vcpu);
3057
d98d07ca
MT		 3058 /*
3059 * On a host with synchronized TSC, there is no need to update
3060 * kvmclock on vcpu->cpu migration
3061 */
3062 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3063 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3064 if (vcpu->cpu != cpu)
1bd2009e 3065 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3066 vcpu->cpu = cpu;
6b7d7e76 3067 }
c9aaa895 3068
c9aaa895 3069 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3070}
3071
0b9f6c46
PX		 3072static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3073{
3074 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3075 return;
3076
fa55eedd 3077 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3078
4e335d9e 3079 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3080 &vcpu->arch.st.steal.preempted,
3081 offsetof(struct kvm_steal_time, preempted),
3082 sizeof(vcpu->arch.st.steal.preempted));
3083}
3084
313a3dc7
CO		 3085void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3086{
cc0d907c 3087 int idx;
de63ad4c
LM		 3088
3089 if (vcpu->preempted)
3090 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3091
931f261b
AA		 3092 /*
3093 * Disable page faults because we're in atomic context here.
3094 * kvm_write_guest_offset_cached() would call might_fault()
3095 * that relies on pagefault_disable() to tell if there's a
3096 * bug. NOTE: the write to guest memory may not go through if
3097 * during postcopy live migration or if there's heavy guest
3098 * paging.
3099 */
3100 pagefault_disable();
cc0d907c
AA		 3101 /*
3102 * kvm_memslots() will be called by
3103 * kvm_write_guest_offset_cached() so take the srcu lock.
3104 */
3105 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3106 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3107 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3108 pagefault_enable();
02daab21 3109 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3110 vcpu->arch.last_host_tsc = rdtsc();
efdab992
WL		 3111 /*
3112 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3113 * on every vmexit, but if not, we might have a stale dr6 from the
3114 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3115 */
3116 set_debugreg(0, 6);
313a3dc7
CO		 3117}
3118
313a3dc7
CO		 3119static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3120 struct kvm_lapic_state *s)
3121{
fa59cc00 3122 if (vcpu->arch.apicv_active)
d62caabb
AS		 3123 kvm_x86_ops->sync_pir_to_irr(vcpu);
3124
a92e2543 3125 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3126}
3127
3128static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3129 struct kvm_lapic_state *s)
3130{
a92e2543
RK		 3131 int r;
3132
3133 r = kvm_apic_set_state(vcpu, s);
3134 if (r)
3135 return r;
cb142eb7 3136 update_cr8_intercept(vcpu);
313a3dc7
CO		 3137
3138 return 0;
3139}
3140
127a457a
MG		 3141static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3142{
3143 return (!lapic_in_kernel(vcpu) ||
3144 kvm_apic_accept_pic_intr(vcpu));
3145}
3146
782d422b
MG		 3147/*
3148 * if userspace requested an interrupt window, check that the
3149 * interrupt window is open.
3150 *
3151 * No need to exit to userspace if we already have an interrupt queued.
3152 */
3153static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3154{
3155 return kvm_arch_interrupt_allowed(vcpu) &&
3156 !kvm_cpu_has_interrupt(vcpu) &&
3157 !kvm_event_needs_reinjection(vcpu) &&
3158 kvm_cpu_accept_dm_intr(vcpu);
3159}
3160
f77bc6a4
ZX		 3161static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3162 struct kvm_interrupt *irq)
3163{
02cdb50f 3164 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3165 return -EINVAL;
1c1a9ce9
SR		 3166
3167 if (!irqchip_in_kernel(vcpu->kvm)) {
3168 kvm_queue_interrupt(vcpu, irq->irq, false);
3169 kvm_make_request(KVM_REQ_EVENT, vcpu);
3170 return 0;
3171 }
3172
3173 /*
3174 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3175 * fail for in-kernel 8259.
3176 */
3177 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3178 return -ENXIO;
f77bc6a4 3179
1c1a9ce9
SR		 3180 if (vcpu->arch.pending_external_vector != -1)
3181 return -EEXIST;
f77bc6a4 3182
1c1a9ce9 3183 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3184 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3185 return 0;
3186}
3187
c4abb7c9
JK		 3188static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3189{
c4abb7c9 3190 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3191
3192 return 0;
3193}
3194
f077825a
PB		 3195static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3196{
64d60670
PB		 3197 kvm_make_request(KVM_REQ_SMI, vcpu);
3198
f077825a
PB		 3199 return 0;
3200}
3201
b209749f
AK		 3202static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3203 struct kvm_tpr_access_ctl *tac)
3204{
3205 if (tac->flags)
3206 return -EINVAL;
3207 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3208 return 0;
3209}
3210
890ca9ae
HY		 3211static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3212 u64 mcg_cap)
3213{
3214 int r;
3215 unsigned bank_num = mcg_cap & 0xff, bank;
3216
3217 r = -EINVAL;
a9e38c3e 3218 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3219 goto out;
c45dcc71 3220 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3221 goto out;
3222 r = 0;
3223 vcpu->arch.mcg_cap = mcg_cap;
3224 /* Init IA32_MCG_CTL to all 1s */
3225 if (mcg_cap & MCG_CTL_P)
3226 vcpu->arch.mcg_ctl = ~(u64)0;
3227 /* Init IA32_MCi_CTL to all 1s */
3228 for (bank = 0; bank < bank_num; bank++)
3229 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3230
3231 if (kvm_x86_ops->setup_mce)
3232 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3233out:
3234 return r;
3235}
3236
3237static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3238 struct kvm_x86_mce *mce)
3239{
3240 u64 mcg_cap = vcpu->arch.mcg_cap;
3241 unsigned bank_num = mcg_cap & 0xff;
3242 u64 *banks = vcpu->arch.mce_banks;
3243
3244 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3245 return -EINVAL;
3246 /*
3247 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3248 * reporting is disabled
3249 */
3250 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3251 vcpu->arch.mcg_ctl != ~(u64)0)
3252 return 0;
3253 banks += 4 * mce->bank;
3254 /*
3255 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3256 * reporting is disabled for the bank
3257 */
3258 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3259 return 0;
3260 if (mce->status & MCI_STATUS_UC) {
3261 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3262 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3263 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3264 return 0;
3265 }
3266 if (banks[1] & MCI_STATUS_VAL)
3267 mce->status |= MCI_STATUS_OVER;
3268 banks[2] = mce->addr;
3269 banks[3] = mce->misc;
3270 vcpu->arch.mcg_status = mce->mcg_status;
3271 banks[1] = mce->status;
3272 kvm_queue_exception(vcpu, MC_VECTOR);
3273 } else if (!(banks[1] & MCI_STATUS_VAL)
3274 || !(banks[1] & MCI_STATUS_UC)) {
3275 if (banks[1] & MCI_STATUS_VAL)
3276 mce->status |= MCI_STATUS_OVER;
3277 banks[2] = mce->addr;
3278 banks[3] = mce->misc;
3279 banks[1] = mce->status;
3280 } else
3281 banks[1] |= MCI_STATUS_OVER;
3282 return 0;
3283}
3284
3cfc3092
JK		 3285static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3286 struct kvm_vcpu_events *events)
3287{
7460fb4a 3288 process_nmi(vcpu);
664f8e26
WL		 3289 /*
3290 * FIXME: pass injected and pending separately. This is only
3291 * needed for nested virtualization, whose state cannot be
3292 * migrated yet. For now we can combine them.
3293 */
03b82a30 3294 events->exception.injected =
664f8e26
WL		 3295 (vcpu->arch.exception.pending ||
3296 vcpu->arch.exception.injected) &&
03b82a30 3297 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3298 events->exception.nr = vcpu->arch.exception.nr;
3299 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3300 events->exception.pad = 0;
3cfc3092
JK		 3301 events->exception.error_code = vcpu->arch.exception.error_code;
3302
03b82a30
JK		 3303 events->interrupt.injected =
3304 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3305 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3306 events->interrupt.soft = 0;
37ccdcbe 3307 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3308
3309 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3310 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3311 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3312 events->nmi.pad = 0;
3cfc3092 3313
66450a21 3314 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3315
f077825a
PB		 3316 events->smi.smm = is_smm(vcpu);
3317 events->smi.pending = vcpu->arch.smi_pending;
3318 events->smi.smm_inside_nmi =
3319 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3320 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3321
dab4b911 3322 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3323 | KVM_VCPUEVENT_VALID_SHADOW
3324 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3325 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3326}
3327
6ef4e07e
XG		 3328static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3329
3cfc3092
JK		 3330static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3331 struct kvm_vcpu_events *events)
3332{
dab4b911 3333 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3334 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3335 | KVM_VCPUEVENT_VALID_SHADOW
3336 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3337 return -EINVAL;
3338
78e546c8 3339 if (events->exception.injected &&
28d06353
JM		 3340 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3341 is_guest_mode(vcpu)))
78e546c8
PB		 3342 return -EINVAL;
3343
28bf2888
DH		 3344 /* INITs are latched while in SMM */
3345 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3346 (events->smi.smm || events->smi.pending) &&
3347 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3348 return -EINVAL;
3349
7460fb4a 3350 process_nmi(vcpu);
664f8e26 3351 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3352 vcpu->arch.exception.pending = events->exception.injected;
3353 vcpu->arch.exception.nr = events->exception.nr;
3354 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3355 vcpu->arch.exception.error_code = events->exception.error_code;
3356
3357 vcpu->arch.interrupt.pending = events->interrupt.injected;
3358 vcpu->arch.interrupt.nr = events->interrupt.nr;
3359 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3360 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3361 kvm_x86_ops->set_interrupt_shadow(vcpu,
3362 events->interrupt.shadow);
3cfc3092
JK		 3363
3364 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3365 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3366 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3367 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3368
66450a21 3369 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3370 lapic_in_kernel(vcpu))
66450a21 3371 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3372
f077825a 3373 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3374 u32 hflags = vcpu->arch.hflags;
f077825a 3375 if (events->smi.smm)
6ef4e07e 3376 hflags |= HF_SMM_MASK;
f077825a 3377 else
6ef4e07e
XG		 3378 hflags &= ~HF_SMM_MASK;
3379 kvm_set_hflags(vcpu, hflags);
3380
f077825a 3381 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3382
3383 if (events->smi.smm) {
3384 if (events->smi.smm_inside_nmi)
3385 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3386 else
f4ef1910
WL		 3387 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3388 if (lapic_in_kernel(vcpu)) {
3389 if (events->smi.latched_init)
3390 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3391 else
3392 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3393 }
f077825a
PB		 3394 }
3395 }
3396
3842d135
AK		 3397 kvm_make_request(KVM_REQ_EVENT, vcpu);
3398
3cfc3092
JK		 3399 return 0;
3400}
3401
a1efbe77
JK		 3402static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3403 struct kvm_debugregs *dbgregs)
3404{
73aaf249
JK		 3405 unsigned long val;
3406
a1efbe77 3407 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3408 kvm_get_dr(vcpu, 6, &val);
73aaf249 3409 dbgregs->dr6 = val;
a1efbe77
JK		 3410 dbgregs->dr7 = vcpu->arch.dr7;
3411 dbgregs->flags = 0;
97e69aa6 3412 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3413}
3414
3415static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3416 struct kvm_debugregs *dbgregs)
3417{
3418 if (dbgregs->flags)
3419 return -EINVAL;
3420
d14bdb55
PB		 3421 if (dbgregs->dr6 & ~0xffffffffull)
3422 return -EINVAL;
3423 if (dbgregs->dr7 & ~0xffffffffull)
3424 return -EINVAL;
3425
a1efbe77 3426 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3427 kvm_update_dr0123(vcpu);
a1efbe77 3428 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3429 kvm_update_dr6(vcpu);
a1efbe77 3430 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3431 kvm_update_dr7(vcpu);
a1efbe77 3432
a1efbe77
JK		 3433 return 0;
3434}
3435
df1daba7
PB		 3436#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3437
3438static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3439{
c47ada30 3440 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3441 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3442 u64 valid;
3443
3444 /*
3445 * Copy legacy XSAVE area, to avoid complications with CPUID
3446 * leaves 0 and 1 in the loop below.
3447 */
3448 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3449
3450 /* Set XSTATE_BV */
00c87e9a 3451 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3452 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3453
3454 /*
3455 * Copy each region from the possibly compacted offset to the
3456 * non-compacted offset.
3457 */
d91cab78 3458 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3459 while (valid) {
3460 u64 feature = valid & -valid;
3461 int index = fls64(feature) - 1;
3462 void *src = get_xsave_addr(xsave, feature);
3463
3464 if (src) {
3465 u32 size, offset, ecx, edx;
3466 cpuid_count(XSTATE_CPUID, index,
3467 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3468 if (feature == XFEATURE_MASK_PKRU)
3469 memcpy(dest + offset, &vcpu->arch.pkru,
3470 sizeof(vcpu->arch.pkru));
3471 else
3472 memcpy(dest + offset, src, size);
3473
df1daba7
PB		 3474 }
3475
3476 valid -= feature;
3477 }
3478}
3479
3480static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3481{
c47ada30 3482 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3483 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3484 u64 valid;
3485
3486 /*
3487 * Copy legacy XSAVE area, to avoid complications with CPUID
3488 * leaves 0 and 1 in the loop below.
3489 */
3490 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3491
3492 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3493 xsave->header.xfeatures = xstate_bv;
782511b0 3494 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3495 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3496
3497 /*
3498 * Copy each region from the non-compacted offset to the
3499 * possibly compacted offset.
3500 */
d91cab78 3501 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3502 while (valid) {
3503 u64 feature = valid & -valid;
3504 int index = fls64(feature) - 1;
3505 void *dest = get_xsave_addr(xsave, feature);
3506
3507 if (dest) {
3508 u32 size, offset, ecx, edx;
3509 cpuid_count(XSTATE_CPUID, index,
3510 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3511 if (feature == XFEATURE_MASK_PKRU)
3512 memcpy(&vcpu->arch.pkru, src + offset,
3513 sizeof(vcpu->arch.pkru));
3514 else
3515 memcpy(dest, src + offset, size);
ee4100da 3516 }
df1daba7
PB		 3517
3518 valid -= feature;
3519 }
3520}
3521
2d5b5a66
SY		 3522static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3523 struct kvm_xsave *guest_xsave)
3524{
d366bf7e 3525 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3526 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3527 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3528 } else {
2d5b5a66 3529 memcpy(guest_xsave->region,
7366ed77 3530 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3531 sizeof(struct fxregs_state));
2d5b5a66 3532 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3533 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3534 }
3535}
3536
a575813b
WL		 3537#define XSAVE_MXCSR_OFFSET 24
3538
2d5b5a66
SY		 3539static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3540 struct kvm_xsave *guest_xsave)
3541{
3542 u64 xstate_bv =
3543 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3544 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3545
d366bf7e 3546 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3547 /*
3548 * Here we allow setting states that are not present in
3549 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3550 * with old userspace.
3551 */
a575813b
WL		 3552 if (xstate_bv & ~kvm_supported_xcr0() ||
3553 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3554 return -EINVAL;
df1daba7 3555 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3556 } else {
a575813b
WL		 3557 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3558 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3559 return -EINVAL;
7366ed77 3560 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3561 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3562 }
3563 return 0;
3564}
3565
3566static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3567 struct kvm_xcrs *guest_xcrs)
3568{
d366bf7e 3569 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3570 guest_xcrs->nr_xcrs = 0;
3571 return;
3572 }
3573
3574 guest_xcrs->nr_xcrs = 1;
3575 guest_xcrs->flags = 0;
3576 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3577 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3578}
3579
3580static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3581 struct kvm_xcrs *guest_xcrs)
3582{
3583 int i, r = 0;
3584
d366bf7e 3585 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3586 return -EINVAL;
3587
3588 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3589 return -EINVAL;
3590
3591 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3592 /* Only support XCR0 currently */
c67a04cb 3593 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3594 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3595 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3596 break;
3597 }
3598 if (r)
3599 r = -EINVAL;
3600 return r;
3601}
3602
1c0b28c2
EM		 3603/*
3604 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3605 * stopped by the hypervisor. This function will be called from the host only.
3606 * EINVAL is returned when the host attempts to set the flag for a guest that
3607 * does not support pv clocks.
3608 */
3609static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3610{
0b79459b 3611 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3612 return -EINVAL;
51d59c6b 3613 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3614 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3615 return 0;
3616}
3617
5c919412
AS		 3618static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3619 struct kvm_enable_cap *cap)
3620{
3621 if (cap->flags)
3622 return -EINVAL;
3623
3624 switch (cap->cap) {
efc479e6
RK		 3625 case KVM_CAP_HYPERV_SYNIC2:
3626 if (cap->args[0])
3627 return -EINVAL;
5c919412 3628 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3629 if (!irqchip_in_kernel(vcpu->kvm))
3630 return -EINVAL;
efc479e6
RK		 3631 return kvm_hv_activate_synic(vcpu, cap->cap ==
3632 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3633 default:
3634 return -EINVAL;
3635 }
3636}
3637
313a3dc7
CO		 3638long kvm_arch_vcpu_ioctl(struct file *filp,
3639 unsigned int ioctl, unsigned long arg)
3640{
3641 struct kvm_vcpu *vcpu = filp->private_data;
3642 void __user *argp = (void __user *)arg;
3643 int r;
d1ac91d8
AK		 3644 union {
3645 struct kvm_lapic_state *lapic;
3646 struct kvm_xsave *xsave;
3647 struct kvm_xcrs *xcrs;
3648 void *buffer;
3649 } u;
3650
9b062471
CD		 3651 vcpu_load(vcpu);
3652
d1ac91d8 3653 u.buffer = NULL;
313a3dc7
CO		 3654 switch (ioctl) {
3655 case KVM_GET_LAPIC: {
2204ae3c 3656 r = -EINVAL;
bce87cce 3657 if (!lapic_in_kernel(vcpu))
2204ae3c 3658 goto out;
d1ac91d8 3659 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3660
b772ff36 3661 r = -ENOMEM;
d1ac91d8 3662 if (!u.lapic)
b772ff36 3663 goto out;
d1ac91d8 3664 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3665 if (r)
3666 goto out;
3667 r = -EFAULT;
d1ac91d8 3668 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3669 goto out;
3670 r = 0;
3671 break;
3672 }
3673 case KVM_SET_LAPIC: {
2204ae3c 3674 r = -EINVAL;
bce87cce 3675 if (!lapic_in_kernel(vcpu))
2204ae3c 3676 goto out;
ff5c2c03 3677 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3678 if (IS_ERR(u.lapic)) {
3679 r = PTR_ERR(u.lapic);
3680 goto out_nofree;
3681 }
ff5c2c03 3682
d1ac91d8 3683 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3684 break;
3685 }
f77bc6a4
ZX		 3686 case KVM_INTERRUPT: {
3687 struct kvm_interrupt irq;
3688
3689 r = -EFAULT;
3690 if (copy_from_user(&irq, argp, sizeof irq))
3691 goto out;
3692 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3693 break;
3694 }
c4abb7c9
JK		 3695 case KVM_NMI: {
3696 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3697 break;
3698 }
f077825a
PB		 3699 case KVM_SMI: {
3700 r = kvm_vcpu_ioctl_smi(vcpu);
3701 break;
3702 }
313a3dc7
CO		 3703 case KVM_SET_CPUID: {
3704 struct kvm_cpuid __user *cpuid_arg = argp;
3705 struct kvm_cpuid cpuid;
3706
3707 r = -EFAULT;
3708 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3709 goto out;
3710 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3711 break;
3712 }
07716717
DK		 3713 case KVM_SET_CPUID2: {
3714 struct kvm_cpuid2 __user *cpuid_arg = argp;
3715 struct kvm_cpuid2 cpuid;
3716
3717 r = -EFAULT;
3718 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3719 goto out;
3720 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3721 cpuid_arg->entries);
07716717
DK		 3722 break;
3723 }
3724 case KVM_GET_CPUID2: {
3725 struct kvm_cpuid2 __user *cpuid_arg = argp;
3726 struct kvm_cpuid2 cpuid;
3727
3728 r = -EFAULT;
3729 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3730 goto out;
3731 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3732 cpuid_arg->entries);
07716717
DK		 3733 if (r)
3734 goto out;
3735 r = -EFAULT;
3736 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3737 goto out;
3738 r = 0;
3739 break;
3740 }
801e459a
TL		 3741 case KVM_GET_MSRS: {
3742 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 3743 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 3744 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3745 break;
801e459a
TL		 3746 }
3747 case KVM_SET_MSRS: {
3748 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 3749 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 3750 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3751 break;
801e459a 3752 }
b209749f
AK		 3753 case KVM_TPR_ACCESS_REPORTING: {
3754 struct kvm_tpr_access_ctl tac;
3755
3756 r = -EFAULT;
3757 if (copy_from_user(&tac, argp, sizeof tac))
3758 goto out;
3759 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3760 if (r)
3761 goto out;
3762 r = -EFAULT;
3763 if (copy_to_user(argp, &tac, sizeof tac))
3764 goto out;
3765 r = 0;
3766 break;
3767 };
b93463aa
AK		 3768 case KVM_SET_VAPIC_ADDR: {
3769 struct kvm_vapic_addr va;
7301d6ab 3770 int idx;
b93463aa
AK		 3771
3772 r = -EINVAL;
35754c98 3773 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3774 goto out;
3775 r = -EFAULT;
3776 if (copy_from_user(&va, argp, sizeof va))
3777 goto out;
7301d6ab 3778 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3779 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3780 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3781 break;
3782 }
890ca9ae
HY		 3783 case KVM_X86_SETUP_MCE: {
3784 u64 mcg_cap;
3785
3786 r = -EFAULT;
3787 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3788 goto out;
3789 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3790 break;
3791 }
3792 case KVM_X86_SET_MCE: {
3793 struct kvm_x86_mce mce;
3794
3795 r = -EFAULT;
3796 if (copy_from_user(&mce, argp, sizeof mce))
3797 goto out;
3798 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3799 break;
3800 }
3cfc3092
JK		 3801 case KVM_GET_VCPU_EVENTS: {
3802 struct kvm_vcpu_events events;
3803
3804 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3805
3806 r = -EFAULT;
3807 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3808 break;
3809 r = 0;
3810 break;
3811 }
3812 case KVM_SET_VCPU_EVENTS: {
3813 struct kvm_vcpu_events events;
3814
3815 r = -EFAULT;
3816 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3817 break;
3818
3819 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3820 break;
3821 }
a1efbe77
JK		 3822 case KVM_GET_DEBUGREGS: {
3823 struct kvm_debugregs dbgregs;
3824
3825 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3826
3827 r = -EFAULT;
3828 if (copy_to_user(argp, &dbgregs,
3829 sizeof(struct kvm_debugregs)))
3830 break;
3831 r = 0;
3832 break;
3833 }
3834 case KVM_SET_DEBUGREGS: {
3835 struct kvm_debugregs dbgregs;
3836
3837 r = -EFAULT;
3838 if (copy_from_user(&dbgregs, argp,
3839 sizeof(struct kvm_debugregs)))
3840 break;
3841
3842 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3843 break;
3844 }
2d5b5a66 3845 case KVM_GET_XSAVE: {
d1ac91d8 3846 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3847 r = -ENOMEM;
d1ac91d8 3848 if (!u.xsave)
2d5b5a66
SY		 3849 break;
3850
d1ac91d8 3851 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3852
3853 r = -EFAULT;
d1ac91d8 3854 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3855 break;
3856 r = 0;
3857 break;
3858 }
3859 case KVM_SET_XSAVE: {
ff5c2c03 3860 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 3861 if (IS_ERR(u.xsave)) {
3862 r = PTR_ERR(u.xsave);
3863 goto out_nofree;
3864 }
2d5b5a66 3865
d1ac91d8 3866 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3867 break;
3868 }
3869 case KVM_GET_XCRS: {
d1ac91d8 3870 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3871 r = -ENOMEM;
d1ac91d8 3872 if (!u.xcrs)
2d5b5a66
SY		 3873 break;
3874
d1ac91d8 3875 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3876
3877 r = -EFAULT;
d1ac91d8 3878 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3879 sizeof(struct kvm_xcrs)))
3880 break;
3881 r = 0;
3882 break;
3883 }
3884 case KVM_SET_XCRS: {
ff5c2c03 3885 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 3886 if (IS_ERR(u.xcrs)) {
3887 r = PTR_ERR(u.xcrs);
3888 goto out_nofree;
3889 }
2d5b5a66 3890
d1ac91d8 3891 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3892 break;
3893 }
92a1f12d
JR		 3894 case KVM_SET_TSC_KHZ: {
3895 u32 user_tsc_khz;
3896
3897 r = -EINVAL;
92a1f12d
JR		 3898 user_tsc_khz = (u32)arg;
3899
3900 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3901 goto out;
3902
cc578287
ZA		 3903 if (user_tsc_khz == 0)
3904 user_tsc_khz = tsc_khz;
3905
381d585c
HZ		 3906 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3907 r = 0;
92a1f12d 3908
92a1f12d
JR		 3909 goto out;
3910 }
3911 case KVM_GET_TSC_KHZ: {
cc578287 3912 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3913 goto out;
3914 }
1c0b28c2
EM		 3915 case KVM_KVMCLOCK_CTRL: {
3916 r = kvm_set_guest_paused(vcpu);
3917 goto out;
3918 }
5c919412
AS		 3919 case KVM_ENABLE_CAP: {
3920 struct kvm_enable_cap cap;
3921
3922 r = -EFAULT;
3923 if (copy_from_user(&cap, argp, sizeof(cap)))
3924 goto out;
3925 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3926 break;
3927 }
313a3dc7
CO		 3928 default:
3929 r = -EINVAL;
3930 }
3931out:
d1ac91d8 3932 kfree(u.buffer);
9b062471
CD		 3933out_nofree:
3934 vcpu_put(vcpu);
313a3dc7
CO		 3935 return r;
3936}
3937
5b1c1493
CO		 3938int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3939{
3940 return VM_FAULT_SIGBUS;
3941}
3942
1fe779f8
CO		 3943static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3944{
3945 int ret;
3946
3947 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3948 return -EINVAL;
1fe779f8
CO		 3949 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3950 return ret;
3951}
3952
b927a3ce
SY		 3953static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3954 u64 ident_addr)
3955{
3956 kvm->arch.ept_identity_map_addr = ident_addr;
3957 return 0;
3958}
3959
1fe779f8
CO		 3960static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3961 u32 kvm_nr_mmu_pages)
3962{
3963 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3964 return -EINVAL;
3965
79fac95e 3966 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3967
3968 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3969 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3970
79fac95e 3971 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3972 return 0;
3973}
3974
3975static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3976{
39de71ec 3977 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3978}
3979
1fe779f8
CO		 3980static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3981{
90bca052 3982 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3983 int r;
3984
3985 r = 0;
3986 switch (chip->chip_id) {
3987 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3988 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3989 sizeof(struct kvm_pic_state));
3990 break;
3991 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3992 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 3993 sizeof(struct kvm_pic_state));
3994 break;
3995 case KVM_IRQCHIP_IOAPIC:
33392b49 3996 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3997 break;
3998 default:
3999 r = -EINVAL;
4000 break;
4001 }
4002 return r;
4003}
4004
4005static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4006{
90bca052 4007 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4008 int r;
4009
4010 r = 0;
4011 switch (chip->chip_id) {
4012 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4013 spin_lock(&pic->lock);
4014 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4015 sizeof(struct kvm_pic_state));
90bca052 4016 spin_unlock(&pic->lock);
1fe779f8
CO		 4017 break;
4018 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4019 spin_lock(&pic->lock);
4020 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4021 sizeof(struct kvm_pic_state));
90bca052 4022 spin_unlock(&pic->lock);
1fe779f8
CO		 4023 break;
4024 case KVM_IRQCHIP_IOAPIC:
33392b49 4025 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4026 break;
4027 default:
4028 r = -EINVAL;
4029 break;
4030 }
90bca052 4031 kvm_pic_update_irq(pic);
1fe779f8
CO		 4032 return r;
4033}
4034
e0f63cb9
SY		 4035static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4036{
34f3941c
RK		 4037 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4038
4039 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4040
4041 mutex_lock(&kps->lock);
4042 memcpy(ps, &kps->channels, sizeof(*ps));
4043 mutex_unlock(&kps->lock);
2da29bcc 4044 return 0;
e0f63cb9
SY		 4045}
4046
4047static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4048{
0185604c 4049 int i;
09edea72
RK		 4050 struct kvm_pit *pit = kvm->arch.vpit;
4051
4052 mutex_lock(&pit->pit_state.lock);
34f3941c 4053 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4054 for (i = 0; i < 3; i++)
09edea72
RK		 4055 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4056 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4057 return 0;
e9f42757
BK		 4058}
4059
4060static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4061{
e9f42757
BK		 4062 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4063 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4064 sizeof(ps->channels));
4065 ps->flags = kvm->arch.vpit->pit_state.flags;
4066 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4067 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4068 return 0;
e9f42757
BK		 4069}
4070
4071static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4072{
2da29bcc 4073 int start = 0;
0185604c 4074 int i;
e9f42757 4075 u32 prev_legacy, cur_legacy;
09edea72
RK		 4076 struct kvm_pit *pit = kvm->arch.vpit;
4077
4078 mutex_lock(&pit->pit_state.lock);
4079 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4080 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4081 if (!prev_legacy && cur_legacy)
4082 start = 1;
09edea72
RK		 4083 memcpy(&pit->pit_state.channels, &ps->channels,
4084 sizeof(pit->pit_state.channels));
4085 pit->pit_state.flags = ps->flags;
0185604c 4086 for (i = 0; i < 3; i++)
09edea72 4087 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4088 start && i == 0);
09edea72 4089 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4090 return 0;
e0f63cb9
SY		 4091}
4092
52d939a0
MT		 4093static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4094 struct kvm_reinject_control *control)
4095{
71474e2f
RK		 4096 struct kvm_pit *pit = kvm->arch.vpit;
4097
4098 if (!pit)
52d939a0 4099 return -ENXIO;
b39c90b6 4100
71474e2f
RK		 4101 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4102 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4103 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4104 */
4105 mutex_lock(&pit->pit_state.lock);
4106 kvm_pit_set_reinject(pit, control->pit_reinject);
4107 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4108
52d939a0
MT		 4109 return 0;
4110}
4111
95d4c16c 4112/**
60c34612
TY		 4113 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4114 * @kvm: kvm instance
4115 * @log: slot id and address to which we copy the log
95d4c16c 4116 *
e108ff2f
PB		 4117 * Steps 1-4 below provide general overview of dirty page logging. See
4118 * kvm_get_dirty_log_protect() function description for additional details.
4119 *
4120 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4121 * always flush the TLB (step 4) even if previous step failed and the dirty
4122 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4123 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4124 * writes will be marked dirty for next log read.
95d4c16c 4125 *
60c34612
TY		 4126 * 1. Take a snapshot of the bit and clear it if needed.
4127 * 2. Write protect the corresponding page.
e108ff2f
PB		 4128 * 3. Copy the snapshot to the userspace.
4129 * 4. Flush TLB's if needed.
5bb064dc 4130 */
60c34612 4131int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4132{
60c34612 4133 bool is_dirty = false;
e108ff2f 4134 int r;
5bb064dc 4135
79fac95e 4136 mutex_lock(&kvm->slots_lock);
5bb064dc 4137
88178fd4
KH		 4138 /*
4139 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4140 */
4141 if (kvm_x86_ops->flush_log_dirty)
4142 kvm_x86_ops->flush_log_dirty(kvm);
4143
e108ff2f 4144 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 4145
4146 /*
4147 * All the TLBs can be flushed out of mmu lock, see the comments in
4148 * kvm_mmu_slot_remove_write_access().
4149 */
e108ff2f 4150 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 4151 if (is_dirty)
4152 kvm_flush_remote_tlbs(kvm);
4153
79fac95e 4154 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4155 return r;
4156}
4157
aa2fbe6d
YZ		 4158int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4159 bool line_status)
23d43cf9
CD		 4160{
4161 if (!irqchip_in_kernel(kvm))
4162 return -ENXIO;
4163
4164 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4165 irq_event->irq, irq_event->level,
4166 line_status);
23d43cf9
CD		 4167 return 0;
4168}
4169
90de4a18
NA		 4170static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4171 struct kvm_enable_cap *cap)
4172{
4173 int r;
4174
4175 if (cap->flags)
4176 return -EINVAL;
4177
4178 switch (cap->cap) {
4179 case KVM_CAP_DISABLE_QUIRKS:
4180 kvm->arch.disabled_quirks = cap->args[0];
4181 r = 0;
4182 break;
49df6397
SR		 4183 case KVM_CAP_SPLIT_IRQCHIP: {
4184 mutex_lock(&kvm->lock);
b053b2ae
SR		 4185 r = -EINVAL;
4186 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4187 goto split_irqchip_unlock;
49df6397
SR		 4188 r = -EEXIST;
4189 if (irqchip_in_kernel(kvm))
4190 goto split_irqchip_unlock;
557abc40 4191 if (kvm->created_vcpus)
49df6397
SR		 4192 goto split_irqchip_unlock;
4193 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4194 if (r)
49df6397
SR		 4195 goto split_irqchip_unlock;
4196 /* Pairs with irqchip_in_kernel. */
4197 smp_wmb();
49776faf 4198 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4199 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4200 r = 0;
4201split_irqchip_unlock:
4202 mutex_unlock(&kvm->lock);
4203 break;
4204 }
37131313
RK		 4205 case KVM_CAP_X2APIC_API:
4206 r = -EINVAL;
4207 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4208 break;
4209
4210 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4211 kvm->arch.x2apic_format = true;
c519265f
RK		 4212 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4213 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4214
4215 r = 0;
4216 break;
90de4a18
NA		 4217 default:
4218 r = -EINVAL;
4219 break;
4220 }
4221 return r;
4222}
4223
1fe779f8
CO		 4224long kvm_arch_vm_ioctl(struct file *filp,
4225 unsigned int ioctl, unsigned long arg)
4226{
4227 struct kvm *kvm = filp->private_data;
4228 void __user *argp = (void __user *)arg;
367e1319 4229 int r = -ENOTTY;
f0d66275
DH		 4230 /*
4231 * This union makes it completely explicit to gcc-3.x
4232 * that these two variables' stack usage should be
4233 * combined, not added together.
4234 */
4235 union {
4236 struct kvm_pit_state ps;
e9f42757 4237 struct kvm_pit_state2 ps2;
c5ff41ce 4238 struct kvm_pit_config pit_config;
f0d66275 4239 } u;
1fe779f8
CO		 4240
4241 switch (ioctl) {
4242 case KVM_SET_TSS_ADDR:
4243 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4244 break;
b927a3ce
SY		 4245 case KVM_SET_IDENTITY_MAP_ADDR: {
4246 u64 ident_addr;
4247
1af1ac91
DH		 4248 mutex_lock(&kvm->lock);
4249 r = -EINVAL;
4250 if (kvm->created_vcpus)
4251 goto set_identity_unlock;
b927a3ce
SY		 4252 r = -EFAULT;
4253 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4254 goto set_identity_unlock;
b927a3ce 4255 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4256set_identity_unlock:
4257 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4258 break;
4259 }
1fe779f8
CO		 4260 case KVM_SET_NR_MMU_PAGES:
4261 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4262 break;
4263 case KVM_GET_NR_MMU_PAGES:
4264 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4265 break;
3ddea128 4266 case KVM_CREATE_IRQCHIP: {
3ddea128 4267 mutex_lock(&kvm->lock);
09941366 4268
3ddea128 4269 r = -EEXIST;
35e6eaa3 4270 if (irqchip_in_kernel(kvm))
3ddea128 4271 goto create_irqchip_unlock;
09941366 4272
3e515705 4273 r = -EINVAL;
557abc40 4274 if (kvm->created_vcpus)
3e515705 4275 goto create_irqchip_unlock;
09941366
RK		 4276
4277 r = kvm_pic_init(kvm);
4278 if (r)
3ddea128 4279 goto create_irqchip_unlock;
09941366
RK		 4280
4281 r = kvm_ioapic_init(kvm);
4282 if (r) {
09941366 4283 kvm_pic_destroy(kvm);
3ddea128 4284 goto create_irqchip_unlock;
09941366
RK		 4285 }
4286
399ec807
AK		 4287 r = kvm_setup_default_irq_routing(kvm);
4288 if (r) {
72bb2fcd 4289 kvm_ioapic_destroy(kvm);
09941366 4290 kvm_pic_destroy(kvm);
71ba994c 4291 goto create_irqchip_unlock;
399ec807 4292 }
49776faf 4293 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4294 smp_wmb();
49776faf 4295 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4296 create_irqchip_unlock:
4297 mutex_unlock(&kvm->lock);
1fe779f8 4298 break;
3ddea128 4299 }
7837699f 4300 case KVM_CREATE_PIT:
c5ff41ce
JK		 4301 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4302 goto create_pit;
4303 case KVM_CREATE_PIT2:
4304 r = -EFAULT;
4305 if (copy_from_user(&u.pit_config, argp,
4306 sizeof(struct kvm_pit_config)))
4307 goto out;
4308 create_pit:
250715a6 4309 mutex_lock(&kvm->lock);
269e05e4
AK		 4310 r = -EEXIST;
4311 if (kvm->arch.vpit)
4312 goto create_pit_unlock;
7837699f 4313 r = -ENOMEM;
c5ff41ce 4314 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4315 if (kvm->arch.vpit)
4316 r = 0;
269e05e4 4317 create_pit_unlock:
250715a6 4318 mutex_unlock(&kvm->lock);
7837699f 4319 break;
1fe779f8
CO		 4320 case KVM_GET_IRQCHIP: {
4321 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4322 struct kvm_irqchip *chip;
1fe779f8 4323
ff5c2c03
SL		 4324 chip = memdup_user(argp, sizeof(*chip));
4325 if (IS_ERR(chip)) {
4326 r = PTR_ERR(chip);
1fe779f8 4327 goto out;
ff5c2c03
SL		 4328 }
4329
1fe779f8 4330 r = -ENXIO;
826da321 4331 if (!irqchip_kernel(kvm))
f0d66275
DH		 4332 goto get_irqchip_out;
4333 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4334 if (r)
f0d66275 4335 goto get_irqchip_out;
1fe779f8 4336 r = -EFAULT;
f0d66275
DH		 4337 if (copy_to_user(argp, chip, sizeof *chip))
4338 goto get_irqchip_out;
1fe779f8 4339 r = 0;
f0d66275
DH		 4340 get_irqchip_out:
4341 kfree(chip);
1fe779f8
CO		 4342 break;
4343 }
4344 case KVM_SET_IRQCHIP: {
4345 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4346 struct kvm_irqchip *chip;
1fe779f8 4347
ff5c2c03
SL		 4348 chip = memdup_user(argp, sizeof(*chip));
4349 if (IS_ERR(chip)) {
4350 r = PTR_ERR(chip);
1fe779f8 4351 goto out;
ff5c2c03
SL		 4352 }
4353
1fe779f8 4354 r = -ENXIO;
826da321 4355 if (!irqchip_kernel(kvm))
f0d66275
DH		 4356 goto set_irqchip_out;
4357 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4358 if (r)
f0d66275 4359 goto set_irqchip_out;
1fe779f8 4360 r = 0;
f0d66275
DH		 4361 set_irqchip_out:
4362 kfree(chip);
1fe779f8
CO		 4363 break;
4364 }
e0f63cb9 4365 case KVM_GET_PIT: {
e0f63cb9 4366 r = -EFAULT;
f0d66275 4367 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4368 goto out;
4369 r = -ENXIO;
4370 if (!kvm->arch.vpit)
4371 goto out;
f0d66275 4372 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4373 if (r)
4374 goto out;
4375 r = -EFAULT;
f0d66275 4376 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4377 goto out;
4378 r = 0;
4379 break;
4380 }
4381 case KVM_SET_PIT: {
e0f63cb9 4382 r = -EFAULT;
f0d66275 4383 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4384 goto out;
4385 r = -ENXIO;
4386 if (!kvm->arch.vpit)
4387 goto out;
f0d66275 4388 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4389 break;
4390 }
e9f42757
BK		 4391 case KVM_GET_PIT2: {
4392 r = -ENXIO;
4393 if (!kvm->arch.vpit)
4394 goto out;
4395 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4396 if (r)
4397 goto out;
4398 r = -EFAULT;
4399 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4400 goto out;
4401 r = 0;
4402 break;
4403 }
4404 case KVM_SET_PIT2: {
4405 r = -EFAULT;
4406 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4407 goto out;
4408 r = -ENXIO;
4409 if (!kvm->arch.vpit)
4410 goto out;
4411 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4412 break;
4413 }
52d939a0
MT		 4414 case KVM_REINJECT_CONTROL: {
4415 struct kvm_reinject_control control;
4416 r = -EFAULT;
4417 if (copy_from_user(&control, argp, sizeof(control)))
4418 goto out;
4419 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4420 break;
4421 }
d71ba788
PB		 4422 case KVM_SET_BOOT_CPU_ID:
4423 r = 0;
4424 mutex_lock(&kvm->lock);
557abc40 4425 if (kvm->created_vcpus)
d71ba788
PB		 4426 r = -EBUSY;
4427 else
4428 kvm->arch.bsp_vcpu_id = arg;
4429 mutex_unlock(&kvm->lock);
4430 break;
ffde22ac 4431 case KVM_XEN_HVM_CONFIG: {
51776043 4432 struct kvm_xen_hvm_config xhc;
ffde22ac 4433 r = -EFAULT;
51776043 4434 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4435 goto out;
4436 r = -EINVAL;
51776043 4437 if (xhc.flags)
ffde22ac 4438 goto out;
51776043 4439 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4440 r = 0;
4441 break;
4442 }
afbcf7ab 4443 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4444 struct kvm_clock_data user_ns;
4445 u64 now_ns;
afbcf7ab
GC		 4446
4447 r = -EFAULT;
4448 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4449 goto out;
4450
4451 r = -EINVAL;
4452 if (user_ns.flags)
4453 goto out;
4454
4455 r = 0;
0bc48bea
RK		 4456 /*
4457 * TODO: userspace has to take care of races with VCPU_RUN, so
4458 * kvm_gen_update_masterclock() can be cut down to locked
4459 * pvclock_update_vm_gtod_copy().
4460 */
4461 kvm_gen_update_masterclock(kvm);
e891a32e 4462 now_ns = get_kvmclock_ns(kvm);
108b249c 4463 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4464 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4465 break;
4466 }
4467 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4468 struct kvm_clock_data user_ns;
4469 u64 now_ns;
4470
e891a32e 4471 now_ns = get_kvmclock_ns(kvm);
108b249c 4472 user_ns.clock = now_ns;
e3fd9a93 4473 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4474 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4475
4476 r = -EFAULT;
4477 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4478 goto out;
4479 r = 0;
4480 break;
4481 }
90de4a18
NA		 4482 case KVM_ENABLE_CAP: {
4483 struct kvm_enable_cap cap;
afbcf7ab 4484
90de4a18
NA		 4485 r = -EFAULT;
4486 if (copy_from_user(&cap, argp, sizeof(cap)))
4487 goto out;
4488 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4489 break;
4490 }
5acc5c06
BS		 4491 case KVM_MEMORY_ENCRYPT_OP: {
4492 r = -ENOTTY;
4493 if (kvm_x86_ops->mem_enc_op)
4494 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4495 break;
4496 }
69eaedee
BS		 4497 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4498 struct kvm_enc_region region;
4499
4500 r = -EFAULT;
4501 if (copy_from_user(&region, argp, sizeof(region)))
4502 goto out;
4503
4504 r = -ENOTTY;
4505 if (kvm_x86_ops->mem_enc_reg_region)
4506 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4507 break;
4508 }
4509 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4510 struct kvm_enc_region region;
4511
4512 r = -EFAULT;
4513 if (copy_from_user(&region, argp, sizeof(region)))
4514 goto out;
4515
4516 r = -ENOTTY;
4517 if (kvm_x86_ops->mem_enc_unreg_region)
4518 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4519 break;
4520 }
faeb7833
RK		 4521 case KVM_HYPERV_EVENTFD: {
4522 struct kvm_hyperv_eventfd hvevfd;
4523
4524 r = -EFAULT;
4525 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4526 goto out;
4527 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4528 break;
4529 }
1fe779f8 4530 default:
ad6260da 4531 r = -ENOTTY;
1fe779f8
CO		 4532 }
4533out:
4534 return r;
4535}
4536
a16b043c 4537static void kvm_init_msr_list(void)
043405e1
CO		 4538{
4539 u32 dummy[2];
4540 unsigned i, j;
4541
62ef68bb 4542 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4543 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4544 continue;
93c4adc7
PB		 4545
4546 /*
4547 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4548 * to the guests in some cases.
93c4adc7
PB		 4549 */
4550 switch (msrs_to_save[i]) {
4551 case MSR_IA32_BNDCFGS:
4552 if (!kvm_x86_ops->mpx_supported())
4553 continue;
4554 break;
9dbe6cf9
PB		 4555 case MSR_TSC_AUX:
4556 if (!kvm_x86_ops->rdtscp_supported())
4557 continue;
4558 break;
93c4adc7
PB		 4559 default:
4560 break;
4561 }
4562
043405e1
CO		 4563 if (j < i)
4564 msrs_to_save[j] = msrs_to_save[i];
4565 j++;
4566 }
4567 num_msrs_to_save = j;
62ef68bb
PB		 4568
4569 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4570 switch (emulated_msrs[i]) {
6d396b55
PB		 4571 case MSR_IA32_SMBASE:
4572 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4573 continue;
4574 break;
62ef68bb
PB		 4575 default:
4576 break;
4577 }
4578
4579 if (j < i)
4580 emulated_msrs[j] = emulated_msrs[i];
4581 j++;
4582 }
4583 num_emulated_msrs = j;
801e459a
TL		 4584
4585 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4586 struct kvm_msr_entry msr;
4587
4588 msr.index = msr_based_features[i];
66421c1e 4589 if (kvm_get_msr_feature(&msr))
801e459a
TL		 4590 continue;
4591
4592 if (j < i)
4593 msr_based_features[j] = msr_based_features[i];
4594 j++;
4595 }
4596 num_msr_based_features = j;
043405e1
CO		 4597}
4598
bda9020e
MT		 4599static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4600 const void *v)
bbd9b64e 4601{
70252a10
AK		 4602 int handled = 0;
4603 int n;
4604
4605 do {
4606 n = min(len, 8);
bce87cce 4607 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4608 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4609 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4610 break;
4611 handled += n;
4612 addr += n;
4613 len -= n;
4614 v += n;
4615 } while (len);
bbd9b64e 4616
70252a10 4617 return handled;
bbd9b64e
CO		 4618}
4619
bda9020e 4620static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4621{
70252a10
AK		 4622 int handled = 0;
4623 int n;
4624
4625 do {
4626 n = min(len, 8);
bce87cce 4627 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4628 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4629 addr, n, v))
4630 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 4631 break;
e39d200f 4632 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 4633 handled += n;
4634 addr += n;
4635 len -= n;
4636 v += n;
4637 } while (len);
bbd9b64e 4638
70252a10 4639 return handled;
bbd9b64e
CO		 4640}
4641
2dafc6c2
GN		 4642static void kvm_set_segment(struct kvm_vcpu *vcpu,
4643 struct kvm_segment *var, int seg)
4644{
4645 kvm_x86_ops->set_segment(vcpu, var, seg);
4646}
4647
4648void kvm_get_segment(struct kvm_vcpu *vcpu,
4649 struct kvm_segment *var, int seg)
4650{
4651 kvm_x86_ops->get_segment(vcpu, var, seg);
4652}
4653
54987b7a
PB		 4654gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4655 struct x86_exception *exception)
02f59dc9
JR		 4656{
4657 gpa_t t_gpa;
02f59dc9
JR		 4658
4659 BUG_ON(!mmu_is_nested(vcpu));
4660
4661 /* NPT walks are always user-walks */
4662 access |= PFERR_USER_MASK;
54987b7a 4663 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4664
4665 return t_gpa;
4666}
4667
ab9ae313
AK		 4668gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4669 struct x86_exception *exception)
1871c602
GN		 4670{
4671 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4672 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4673}
4674
ab9ae313
AK		 4675 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4676 struct x86_exception *exception)
1871c602
GN		 4677{
4678 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4679 access |= PFERR_FETCH_MASK;
ab9ae313 4680 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4681}
4682
ab9ae313
AK		 4683gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4684 struct x86_exception *exception)
1871c602
GN		 4685{
4686 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4687 access |= PFERR_WRITE_MASK;
ab9ae313 4688 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4689}
4690
4691/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4692gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4693 struct x86_exception *exception)
1871c602 4694{
ab9ae313 4695 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4696}
4697
4698static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4699 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4700 struct x86_exception *exception)
bbd9b64e
CO		 4701{
4702 void *data = val;
10589a46 4703 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4704
4705 while (bytes) {
14dfe855 4706 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4707 exception);
bbd9b64e 4708 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4709 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4710 int ret;
4711
bcc55cba 4712 if (gpa == UNMAPPED_GVA)
ab9ae313 4713 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4714 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4715 offset, toread);
10589a46 4716 if (ret < 0) {
c3cd7ffa 4717 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4718 goto out;
4719 }
bbd9b64e 4720
77c2002e
IE		 4721 bytes -= toread;
4722 data += toread;
4723 addr += toread;
bbd9b64e 4724 }
10589a46 4725out:
10589a46 4726 return r;
bbd9b64e 4727}
77c2002e 4728
1871c602 4729/* used for instruction fetching */
0f65dd70
AK		 4730static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4731 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4732 struct x86_exception *exception)
1871c602 4733{
0f65dd70 4734 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4735 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4736 unsigned offset;
4737 int ret;
0f65dd70 4738
44583cba
PB		 4739 /* Inline kvm_read_guest_virt_helper for speed. */
4740 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4741 exception);
4742 if (unlikely(gpa == UNMAPPED_GVA))
4743 return X86EMUL_PROPAGATE_FAULT;
4744
4745 offset = addr & (PAGE_SIZE-1);
4746 if (WARN_ON(offset + bytes > PAGE_SIZE))
4747 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4748 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4749 offset, bytes);
44583cba
PB		 4750 if (unlikely(ret < 0))
4751 return X86EMUL_IO_NEEDED;
4752
4753 return X86EMUL_CONTINUE;
1871c602
GN		 4754}
4755
064aea77 4756int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4757 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4758 struct x86_exception *exception)
1871c602 4759{
0f65dd70 4760 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4761 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4762
1871c602 4763 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4764 exception);
1871c602 4765}
064aea77 4766EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4767
0f65dd70
AK		 4768static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4769 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4770 struct x86_exception *exception)
1871c602 4771{
0f65dd70 4772 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4773 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4774}
4775
7a036a6f
RK		 4776static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4777 unsigned long addr, void *val, unsigned int bytes)
4778{
4779 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4780 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4781
4782 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4783}
4784
6a4d7550 4785int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4786 gva_t addr, void *val,
2dafc6c2 4787 unsigned int bytes,
bcc55cba 4788 struct x86_exception *exception)
77c2002e 4789{
0f65dd70 4790 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4791 void *data = val;
4792 int r = X86EMUL_CONTINUE;
4793
4794 while (bytes) {
14dfe855
JR		 4795 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4796 PFERR_WRITE_MASK,
ab9ae313 4797 exception);
77c2002e
IE		 4798 unsigned offset = addr & (PAGE_SIZE-1);
4799 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4800 int ret;
4801
bcc55cba 4802 if (gpa == UNMAPPED_GVA)
ab9ae313 4803 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4804 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4805 if (ret < 0) {
c3cd7ffa 4806 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4807 goto out;
4808 }
4809
4810 bytes -= towrite;
4811 data += towrite;
4812 addr += towrite;
4813 }
4814out:
4815 return r;
4816}
6a4d7550 4817EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4818
0f89b207
TL		 4819static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4820 gpa_t gpa, bool write)
4821{
4822 /* For APIC access vmexit */
4823 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4824 return 1;
4825
4826 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4827 trace_vcpu_match_mmio(gva, gpa, write, true);
4828 return 1;
4829 }
4830
4831 return 0;
4832}
4833
af7cc7d1
XG		 4834static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4835 gpa_t *gpa, struct x86_exception *exception,
4836 bool write)
4837{
97d64b78
AK		 4838 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4839 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4840
be94f6b7
HH		 4841 /*
4842 * currently PKRU is only applied to ept enabled guest so
4843 * there is no pkey in EPT page table for L1 guest or EPT
4844 * shadow page table for L2 guest.
4845 */
97d64b78 4846 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4847 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4848 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4849 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4850 (gva & (PAGE_SIZE - 1));
4f022648 4851 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4852 return 1;
4853 }
4854
af7cc7d1
XG		 4855 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4856
4857 if (*gpa == UNMAPPED_GVA)
4858 return -1;
4859
0f89b207 4860 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4861}
4862
3200f405 4863int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4864 const void *val, int bytes)
bbd9b64e
CO		 4865{
4866 int ret;
4867
54bf36aa 4868 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4869 if (ret < 0)
bbd9b64e 4870 return 0;
0eb05bf2 4871 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4872 return 1;
4873}
4874
77d197b2
XG		 4875struct read_write_emulator_ops {
4876 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4877 int bytes);
4878 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4879 void *val, int bytes);
4880 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4881 int bytes, void *val);
4882 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4883 void *val, int bytes);
4884 bool write;
4885};
4886
4887static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4888{
4889 if (vcpu->mmio_read_completed) {
77d197b2 4890 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 4891 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 4892 vcpu->mmio_read_completed = 0;
4893 return 1;
4894 }
4895
4896 return 0;
4897}
4898
4899static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4900 void *val, int bytes)
4901{
54bf36aa 4902 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4903}
4904
4905static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4906 void *val, int bytes)
4907{
4908 return emulator_write_phys(vcpu, gpa, val, bytes);
4909}
4910
4911static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4912{
e39d200f 4913 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 4914 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4915}
4916
4917static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4918 void *val, int bytes)
4919{
e39d200f 4920 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 4921 return X86EMUL_IO_NEEDED;
4922}
4923
4924static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4925 void *val, int bytes)
4926{
f78146b0
AK		 4927 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4928
87da7e66 4929 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4930 return X86EMUL_CONTINUE;
4931}
4932
0fbe9b0b 4933static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4934 .read_write_prepare = read_prepare,
4935 .read_write_emulate = read_emulate,
4936 .read_write_mmio = vcpu_mmio_read,
4937 .read_write_exit_mmio = read_exit_mmio,
4938};
4939
0fbe9b0b 4940static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4941 .read_write_emulate = write_emulate,
4942 .read_write_mmio = write_mmio,
4943 .read_write_exit_mmio = write_exit_mmio,
4944 .write = true,
4945};
4946
22388a3c
XG		 4947static int emulator_read_write_onepage(unsigned long addr, void *val,
4948 unsigned int bytes,
4949 struct x86_exception *exception,
4950 struct kvm_vcpu *vcpu,
0fbe9b0b 4951 const struct read_write_emulator_ops *ops)
bbd9b64e 4952{
af7cc7d1
XG		 4953 gpa_t gpa;
4954 int handled, ret;
22388a3c 4955 bool write = ops->write;
f78146b0 4956 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4957 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4958
4959 /*
4960 * If the exit was due to a NPF we may already have a GPA.
4961 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4962 * Note, this cannot be used on string operations since string
4963 * operation using rep will only have the initial GPA from the NPF
4964 * occurred.
4965 */
4966 if (vcpu->arch.gpa_available &&
4967 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 4968 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
4969 gpa = vcpu->arch.gpa_val;
4970 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
4971 } else {
4972 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4973 if (ret < 0)
4974 return X86EMUL_PROPAGATE_FAULT;
0f89b207 4975 }
10589a46 4976
618232e2 4977 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4978 return X86EMUL_CONTINUE;
4979
bbd9b64e
CO		 4980 /*
4981 * Is this MMIO handled locally?
4982 */
22388a3c 4983 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4984 if (handled == bytes)
bbd9b64e 4985 return X86EMUL_CONTINUE;
bbd9b64e 4986
70252a10
AK		 4987 gpa += handled;
4988 bytes -= handled;
4989 val += handled;
4990
87da7e66
XG		 4991 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4992 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4993 frag->gpa = gpa;
4994 frag->data = val;
4995 frag->len = bytes;
f78146b0 4996 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4997}
4998
52eb5a6d
XL		 4999static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5000 unsigned long addr,
22388a3c
XG		 5001 void *val, unsigned int bytes,
5002 struct x86_exception *exception,
0fbe9b0b 5003 const struct read_write_emulator_ops *ops)
bbd9b64e 5004{
0f65dd70 5005 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5006 gpa_t gpa;
5007 int rc;
5008
5009 if (ops->read_write_prepare &&
5010 ops->read_write_prepare(vcpu, val, bytes))
5011 return X86EMUL_CONTINUE;
5012
5013 vcpu->mmio_nr_fragments = 0;
0f65dd70 5014
bbd9b64e
CO		 5015 /* Crossing a page boundary? */
5016 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5017 int now;
bbd9b64e
CO		 5018
5019 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5020 rc = emulator_read_write_onepage(addr, val, now, exception,
5021 vcpu, ops);
5022
bbd9b64e
CO		 5023 if (rc != X86EMUL_CONTINUE)
5024 return rc;
5025 addr += now;
bac15531
NA		 5026 if (ctxt->mode != X86EMUL_MODE_PROT64)
5027 addr = (u32)addr;
bbd9b64e
CO		 5028 val += now;
5029 bytes -= now;
5030 }
22388a3c 5031
f78146b0
AK		 5032 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5033 vcpu, ops);
5034 if (rc != X86EMUL_CONTINUE)
5035 return rc;
5036
5037 if (!vcpu->mmio_nr_fragments)
5038 return rc;
5039
5040 gpa = vcpu->mmio_fragments[0].gpa;
5041
5042 vcpu->mmio_needed = 1;
5043 vcpu->mmio_cur_fragment = 0;
5044
87da7e66 5045 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5046 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5047 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5048 vcpu->run->mmio.phys_addr = gpa;
5049
5050 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5051}
5052
5053static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5054 unsigned long addr,
5055 void *val,
5056 unsigned int bytes,
5057 struct x86_exception *exception)
5058{
5059 return emulator_read_write(ctxt, addr, val, bytes,
5060 exception, &read_emultor);
5061}
5062
52eb5a6d 5063static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5064 unsigned long addr,
5065 const void *val,
5066 unsigned int bytes,
5067 struct x86_exception *exception)
5068{
5069 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5070 exception, &write_emultor);
bbd9b64e 5071}
bbd9b64e 5072
daea3e73
AK		 5073#define CMPXCHG_TYPE(t, ptr, old, new) \
5074 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5075
5076#ifdef CONFIG_X86_64
5077# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5078#else
5079# define CMPXCHG64(ptr, old, new) \
9749a6c0 5080 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5081#endif
5082
0f65dd70
AK		 5083static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5084 unsigned long addr,
bbd9b64e
CO		 5085 const void *old,
5086 const void *new,
5087 unsigned int bytes,
0f65dd70 5088 struct x86_exception *exception)
bbd9b64e 5089{
0f65dd70 5090 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 5091 gpa_t gpa;
5092 struct page *page;
5093 char *kaddr;
5094 bool exchanged;
2bacc55c 5095
daea3e73
AK		 5096 /* guests cmpxchg8b have to be emulated atomically */
5097 if (bytes > 8 || (bytes & (bytes - 1)))
5098 goto emul_write;
10589a46 5099
daea3e73 5100 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5101
daea3e73
AK		 5102 if (gpa == UNMAPPED_GVA ||
5103 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5104 goto emul_write;
2bacc55c 5105
daea3e73
AK		 5106 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5107 goto emul_write;
72dc67a6 5108
54bf36aa 5109 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 5110 if (is_error_page(page))
c19b8bd6 5111 goto emul_write;
72dc67a6 5112
8fd75e12 5113 kaddr = kmap_atomic(page);
daea3e73
AK		 5114 kaddr += offset_in_page(gpa);
5115 switch (bytes) {
5116 case 1:
5117 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5118 break;
5119 case 2:
5120 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5121 break;
5122 case 4:
5123 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5124 break;
5125 case 8:
5126 exchanged = CMPXCHG64(kaddr, old, new);
5127 break;
5128 default:
5129 BUG();
2bacc55c 5130 }
8fd75e12 5131 kunmap_atomic(kaddr);
daea3e73
AK		 5132 kvm_release_page_dirty(page);
5133
5134 if (!exchanged)
5135 return X86EMUL_CMPXCHG_FAILED;
5136
54bf36aa 5137 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 5138 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5139
5140 return X86EMUL_CONTINUE;
4a5f48f6 5141
3200f405 5142emul_write:
daea3e73 5143 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5144
0f65dd70 5145 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5146}
5147
cf8f70bf
GN		 5148static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5149{
cbfc6c91 5150 int r = 0, i;
cf8f70bf 5151
cbfc6c91
WL		 5152 for (i = 0; i < vcpu->arch.pio.count; i++) {
5153 if (vcpu->arch.pio.in)
5154 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5155 vcpu->arch.pio.size, pd);
5156 else
5157 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5158 vcpu->arch.pio.port, vcpu->arch.pio.size,
5159 pd);
5160 if (r)
5161 break;
5162 pd += vcpu->arch.pio.size;
5163 }
cf8f70bf
GN		 5164 return r;
5165}
5166
6f6fbe98
XG		 5167static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5168 unsigned short port, void *val,
5169 unsigned int count, bool in)
cf8f70bf 5170{
cf8f70bf 5171 vcpu->arch.pio.port = port;
6f6fbe98 5172 vcpu->arch.pio.in = in;
7972995b 5173 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5174 vcpu->arch.pio.size = size;
5175
5176 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5177 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5178 return 1;
5179 }
5180
5181 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5182 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5183 vcpu->run->io.size = size;
5184 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5185 vcpu->run->io.count = count;
5186 vcpu->run->io.port = port;
5187
5188 return 0;
5189}
5190
6f6fbe98
XG		 5191static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5192 int size, unsigned short port, void *val,
5193 unsigned int count)
cf8f70bf 5194{
ca1d4a9e 5195 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5196 int ret;
ca1d4a9e 5197
6f6fbe98
XG		 5198 if (vcpu->arch.pio.count)
5199 goto data_avail;
cf8f70bf 5200
cbfc6c91
WL		 5201 memset(vcpu->arch.pio_data, 0, size * count);
5202
6f6fbe98
XG		 5203 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5204 if (ret) {
5205data_avail:
5206 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5207 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5208 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5209 return 1;
5210 }
5211
cf8f70bf
GN		 5212 return 0;
5213}
5214
6f6fbe98
XG		 5215static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5216 int size, unsigned short port,
5217 const void *val, unsigned int count)
5218{
5219 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5220
5221 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5222 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5223 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5224}
5225
bbd9b64e
CO		 5226static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5227{
5228 return kvm_x86_ops->get_segment_base(vcpu, seg);
5229}
5230
3cb16fe7 5231static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5232{
3cb16fe7 5233 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5234}
5235
ae6a2375 5236static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5237{
5238 if (!need_emulate_wbinvd(vcpu))
5239 return X86EMUL_CONTINUE;
5240
5241 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5242 int cpu = get_cpu();
5243
5244 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5245 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5246 wbinvd_ipi, NULL, 1);
2eec7343 5247 put_cpu();
f5f48ee1 5248 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5249 } else
5250 wbinvd();
f5f48ee1
SY		 5251 return X86EMUL_CONTINUE;
5252}
5cb56059
JS		 5253
5254int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5255{
6affcbed
KH		 5256 kvm_emulate_wbinvd_noskip(vcpu);
5257 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5258}
f5f48ee1
SY		 5259EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5260
5cb56059
JS		 5261
5262
bcaf5cc5
AK		 5263static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5264{
5cb56059 5265 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5266}
5267
52eb5a6d
XL		 5268static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5269 unsigned long *dest)
bbd9b64e 5270{
16f8a6f9 5271 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5272}
5273
52eb5a6d
XL		 5274static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5275 unsigned long value)
bbd9b64e 5276{
338dbc97 5277
717746e3 5278 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5279}
5280
52a46617 5281static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5282{
52a46617 5283 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5284}
5285
717746e3 5286static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5287{
717746e3 5288 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5289 unsigned long value;
5290
5291 switch (cr) {
5292 case 0:
5293 value = kvm_read_cr0(vcpu);
5294 break;
5295 case 2:
5296 value = vcpu->arch.cr2;
5297 break;
5298 case 3:
9f8fe504 5299 value = kvm_read_cr3(vcpu);
52a46617
GN		 5300 break;
5301 case 4:
5302 value = kvm_read_cr4(vcpu);
5303 break;
5304 case 8:
5305 value = kvm_get_cr8(vcpu);
5306 break;
5307 default:
a737f256 5308 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5309 return 0;
5310 }
5311
5312 return value;
5313}
5314
717746e3 5315static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5316{
717746e3 5317 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5318 int res = 0;
5319
52a46617
GN		 5320 switch (cr) {
5321 case 0:
49a9b07e 5322 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5323 break;
5324 case 2:
5325 vcpu->arch.cr2 = val;
5326 break;
5327 case 3:
2390218b 5328 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5329 break;
5330 case 4:
a83b29c6 5331 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5332 break;
5333 case 8:
eea1cff9 5334 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5335 break;
5336 default:
a737f256 5337 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5338 res = -1;
52a46617 5339 }
0f12244f
GN		 5340
5341 return res;
52a46617
GN		 5342}
5343
717746e3 5344static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5345{
717746e3 5346 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5347}
5348
4bff1e86 5349static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5350{
4bff1e86 5351 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5352}
5353
4bff1e86 5354static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5355{
4bff1e86 5356 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5357}
5358
1ac9d0cf
AK		 5359static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5360{
5361 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5362}
5363
5364static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5365{
5366 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5367}
5368
4bff1e86
AK		 5369static unsigned long emulator_get_cached_segment_base(
5370 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5371{
4bff1e86 5372 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5373}
5374
1aa36616
AK		 5375static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5376 struct desc_struct *desc, u32 *base3,
5377 int seg)
2dafc6c2
GN		 5378{
5379 struct kvm_segment var;
5380
4bff1e86 5381 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5382 *selector = var.selector;
2dafc6c2 5383
378a8b09
GN		 5384 if (var.unusable) {
5385 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5386 if (base3)
5387 *base3 = 0;
2dafc6c2 5388 return false;
378a8b09 5389 }
2dafc6c2
GN		 5390
5391 if (var.g)
5392 var.limit >>= 12;
5393 set_desc_limit(desc, var.limit);
5394 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5395#ifdef CONFIG_X86_64
5396 if (base3)
5397 *base3 = var.base >> 32;
5398#endif
2dafc6c2
GN		 5399 desc->type = var.type;
5400 desc->s = var.s;
5401 desc->dpl = var.dpl;
5402 desc->p = var.present;
5403 desc->avl = var.avl;
5404 desc->l = var.l;
5405 desc->d = var.db;
5406 desc->g = var.g;
5407
5408 return true;
5409}
5410
1aa36616
AK		 5411static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5412 struct desc_struct *desc, u32 base3,
5413 int seg)
2dafc6c2 5414{
4bff1e86 5415 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5416 struct kvm_segment var;
5417
1aa36616 5418 var.selector = selector;
2dafc6c2 5419 var.base = get_desc_base(desc);
5601d05b
GN		 5420#ifdef CONFIG_X86_64
5421 var.base |= ((u64)base3) << 32;
5422#endif
2dafc6c2
GN		 5423 var.limit = get_desc_limit(desc);
5424 if (desc->g)
5425 var.limit = (var.limit << 12) | 0xfff;
5426 var.type = desc->type;
2dafc6c2
GN		 5427 var.dpl = desc->dpl;
5428 var.db = desc->d;
5429 var.s = desc->s;
5430 var.l = desc->l;
5431 var.g = desc->g;
5432 var.avl = desc->avl;
5433 var.present = desc->p;
5434 var.unusable = !var.present;
5435 var.padding = 0;
5436
5437 kvm_set_segment(vcpu, &var, seg);
5438 return;
5439}
5440
717746e3
AK		 5441static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5442 u32 msr_index, u64 *pdata)
5443{
609e36d3
PB		 5444 struct msr_data msr;
5445 int r;
5446
5447 msr.index = msr_index;
5448 msr.host_initiated = false;
5449 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5450 if (r)
5451 return r;
5452
5453 *pdata = msr.data;
5454 return 0;
717746e3
AK		 5455}
5456
5457static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5458 u32 msr_index, u64 data)
5459{
8fe8ab46
WA		 5460 struct msr_data msr;
5461
5462 msr.data = data;
5463 msr.index = msr_index;
5464 msr.host_initiated = false;
5465 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5466}
5467
64d60670
PB		 5468static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5469{
5470 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5471
5472 return vcpu->arch.smbase;
5473}
5474
5475static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5476{
5477 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5478
5479 vcpu->arch.smbase = smbase;
5480}
5481
67f4d428
NA		 5482static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5483 u32 pmc)
5484{
c6702c9d 5485 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5486}
5487
222d21aa
AK		 5488static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5489 u32 pmc, u64 *pdata)
5490{
c6702c9d 5491 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5492}
5493
6c3287f7
AK		 5494static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5495{
5496 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5497}
5498
2953538e 5499static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5500 struct x86_instruction_info *info,
c4f035c6
AK		 5501 enum x86_intercept_stage stage)
5502{
2953538e 5503 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5504}
5505
e911eb3b
YZ		 5506static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5507 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5508{
e911eb3b 5509 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5510}
5511
dd856efa
AK		 5512static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5513{
5514 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5515}
5516
5517static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5518{
5519 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5520}
5521
801806d9
NA		 5522static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5523{
5524 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5525}
5526
6ed071f0
LP		 5527static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5528{
5529 return emul_to_vcpu(ctxt)->arch.hflags;
5530}
5531
5532static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5533{
5534 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5535}
5536
0234bf88
LP		 5537static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5538{
5539 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5540}
5541
0225fb50 5542static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5543 .read_gpr = emulator_read_gpr,
5544 .write_gpr = emulator_write_gpr,
1871c602 5545 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5546 .write_std = kvm_write_guest_virt_system,
7a036a6f 5547 .read_phys = kvm_read_guest_phys_system,
1871c602 5548 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5549 .read_emulated = emulator_read_emulated,
5550 .write_emulated = emulator_write_emulated,
5551 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5552 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5553 .pio_in_emulated = emulator_pio_in_emulated,
5554 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5555 .get_segment = emulator_get_segment,
5556 .set_segment = emulator_set_segment,
5951c442 5557 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5558 .get_gdt = emulator_get_gdt,
160ce1f1 5559 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5560 .set_gdt = emulator_set_gdt,
5561 .set_idt = emulator_set_idt,
52a46617
GN		 5562 .get_cr = emulator_get_cr,
5563 .set_cr = emulator_set_cr,
9c537244 5564 .cpl = emulator_get_cpl,
35aa5375
GN		 5565 .get_dr = emulator_get_dr,
5566 .set_dr = emulator_set_dr,
64d60670
PB		 5567 .get_smbase = emulator_get_smbase,
5568 .set_smbase = emulator_set_smbase,
717746e3
AK		 5569 .set_msr = emulator_set_msr,
5570 .get_msr = emulator_get_msr,
67f4d428 5571 .check_pmc = emulator_check_pmc,
222d21aa 5572 .read_pmc = emulator_read_pmc,
6c3287f7 5573 .halt = emulator_halt,
bcaf5cc5 5574 .wbinvd = emulator_wbinvd,
d6aa1000 5575 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5576 .intercept = emulator_intercept,
bdb42f5a 5577 .get_cpuid = emulator_get_cpuid,
801806d9 5578 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5579 .get_hflags = emulator_get_hflags,
5580 .set_hflags = emulator_set_hflags,
0234bf88 5581 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5582};
5583
95cb2295
GN		 5584static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5585{
37ccdcbe 5586 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5587 /*
5588 * an sti; sti; sequence only disable interrupts for the first
5589 * instruction. So, if the last instruction, be it emulated or
5590 * not, left the system with the INT_STI flag enabled, it
5591 * means that the last instruction is an sti. We should not
5592 * leave the flag on in this case. The same goes for mov ss
5593 */
37ccdcbe
PB		 5594 if (int_shadow & mask)
5595 mask = 0;
6addfc42 5596 if (unlikely(int_shadow || mask)) {
95cb2295 5597 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5598 if (!mask)
5599 kvm_make_request(KVM_REQ_EVENT, vcpu);
5600 }
95cb2295
GN		 5601}
5602
ef54bcfe 5603static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5604{
5605 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5606 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5607 return kvm_propagate_fault(vcpu, &ctxt->exception);
5608
5609 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5610 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5611 ctxt->exception.error_code);
54b8486f 5612 else
da9cb575 5613 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5614 return false;
54b8486f
GN		 5615}
5616
8ec4722d
MG		 5617static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5618{
adf52235 5619 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5620 int cs_db, cs_l;
5621
8ec4722d
MG		 5622 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5623
adf52235 5624 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5625 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5626
adf52235
TY		 5627 ctxt->eip = kvm_rip_read(vcpu);
5628 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5629 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5630 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5631 cs_db ? X86EMUL_MODE_PROT32 :
5632 X86EMUL_MODE_PROT16;
a584539b 5633 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5634 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5635 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5636
dd856efa 5637 init_decode_cache(ctxt);
7ae441ea 5638 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5639}
5640
71f9833b 5641int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5642{
9d74191a 5643 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5644 int ret;
5645
5646 init_emulate_ctxt(vcpu);
5647
9dac77fa
AK		 5648 ctxt->op_bytes = 2;
5649 ctxt->ad_bytes = 2;
5650 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5651 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5652
5653 if (ret != X86EMUL_CONTINUE)
5654 return EMULATE_FAIL;
5655
9dac77fa 5656 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5657 kvm_rip_write(vcpu, ctxt->eip);
5658 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5659
5660 if (irq == NMI_VECTOR)
7460fb4a 5661 vcpu->arch.nmi_pending = 0;
63995653
MG		 5662 else
5663 vcpu->arch.interrupt.pending = false;
5664
5665 return EMULATE_DONE;
5666}
5667EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5668
6d77dbfc
GN		 5669static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5670{
fc3a9157
JR		 5671 int r = EMULATE_DONE;
5672
6d77dbfc
GN		 5673 ++vcpu->stat.insn_emulation_fail;
5674 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5675 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5676 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5677 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5678 vcpu->run->internal.ndata = 0;
1f4dcb3b 5679 r = EMULATE_USER_EXIT;
fc3a9157 5680 }
6d77dbfc 5681 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5682
5683 return r;
6d77dbfc
GN		 5684}
5685
93c05d3e 5686static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5687 bool write_fault_to_shadow_pgtable,
5688 int emulation_type)
a6f177ef 5689{
95b3cf69 5690 gpa_t gpa = cr2;
ba049e93 5691 kvm_pfn_t pfn;
a6f177ef 5692
991eebf9
GN		 5693 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5694 return false;
5695
95b3cf69
XG		 5696 if (!vcpu->arch.mmu.direct_map) {
5697 /*
5698 * Write permission should be allowed since only
5699 * write access need to be emulated.
5700 */
5701 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5702
95b3cf69
XG		 5703 /*
5704 * If the mapping is invalid in guest, let cpu retry
5705 * it to generate fault.
5706 */
5707 if (gpa == UNMAPPED_GVA)
5708 return true;
5709 }
a6f177ef 5710
8e3d9d06
XG		 5711 /*
5712 * Do not retry the unhandleable instruction if it faults on the
5713 * readonly host memory, otherwise it will goto a infinite loop:
5714 * retry instruction -> write #PF -> emulation fail -> retry
5715 * instruction -> ...
5716 */
5717 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5718
5719 /*
5720 * If the instruction failed on the error pfn, it can not be fixed,
5721 * report the error to userspace.
5722 */
5723 if (is_error_noslot_pfn(pfn))
5724 return false;
5725
5726 kvm_release_pfn_clean(pfn);
5727
5728 /* The instructions are well-emulated on direct mmu. */
5729 if (vcpu->arch.mmu.direct_map) {
5730 unsigned int indirect_shadow_pages;
5731
5732 spin_lock(&vcpu->kvm->mmu_lock);
5733 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5734 spin_unlock(&vcpu->kvm->mmu_lock);
5735
5736 if (indirect_shadow_pages)
5737 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5738
a6f177ef 5739 return true;
8e3d9d06 5740 }
a6f177ef 5741
95b3cf69
XG		 5742 /*
5743 * if emulation was due to access to shadowed page table
5744 * and it failed try to unshadow page and re-enter the
5745 * guest to let CPU execute the instruction.
5746 */
5747 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5748
5749 /*
5750 * If the access faults on its page table, it can not
5751 * be fixed by unprotecting shadow page and it should
5752 * be reported to userspace.
5753 */
5754 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5755}
5756
1cb3f3ae
XG		 5757static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5758 unsigned long cr2, int emulation_type)
5759{
5760 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5761 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5762
5763 last_retry_eip = vcpu->arch.last_retry_eip;
5764 last_retry_addr = vcpu->arch.last_retry_addr;
5765
5766 /*
5767 * If the emulation is caused by #PF and it is non-page_table
5768 * writing instruction, it means the VM-EXIT is caused by shadow
5769 * page protected, we can zap the shadow page and retry this
5770 * instruction directly.
5771 *
5772 * Note: if the guest uses a non-page-table modifying instruction
5773 * on the PDE that points to the instruction, then we will unmap
5774 * the instruction and go to an infinite loop. So, we cache the
5775 * last retried eip and the last fault address, if we meet the eip
5776 * and the address again, we can break out of the potential infinite
5777 * loop.
5778 */
5779 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5780
5781 if (!(emulation_type & EMULTYPE_RETRY))
5782 return false;
5783
5784 if (x86_page_table_writing_insn(ctxt))
5785 return false;
5786
5787 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5788 return false;
5789
5790 vcpu->arch.last_retry_eip = ctxt->eip;
5791 vcpu->arch.last_retry_addr = cr2;
5792
5793 if (!vcpu->arch.mmu.direct_map)
5794 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5795
22368028 5796 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5797
5798 return true;
5799}
5800
716d51ab
GN		 5801static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5802static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5803
64d60670 5804static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5805{
64d60670 5806 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5807 /* This is a good place to trace that we are exiting SMM. */
5808 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5809
c43203ca
PB		 5810 /* Process a latched INIT or SMI, if any. */
5811 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5812 }
699023e2
PB		 5813
5814 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5815}
5816
5817static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5818{
5819 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5820
a584539b 5821 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5822
5823 if (changed & HF_SMM_MASK)
5824 kvm_smm_changed(vcpu);
a584539b
PB		 5825}
5826
4a1e10d5
PB		 5827static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5828 unsigned long *db)
5829{
5830 u32 dr6 = 0;
5831 int i;
5832 u32 enable, rwlen;
5833
5834 enable = dr7;
5835 rwlen = dr7 >> 16;
5836 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5837 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5838 dr6 |= (1 << i);
5839 return dr6;
5840}
5841
c8401dda 5842static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5843{
5844 struct kvm_run *kvm_run = vcpu->run;
5845
c8401dda
PB		 5846 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5847 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5848 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5849 kvm_run->debug.arch.exception = DB_VECTOR;
5850 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5851 *r = EMULATE_USER_EXIT;
5852 } else {
5853 /*
5854 * "Certain debug exceptions may clear bit 0-3. The
5855 * remaining contents of the DR6 register are never
5856 * cleared by the processor".
5857 */
5858 vcpu->arch.dr6 &= ~15;
5859 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5860 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5861 }
5862}
5863
6affcbed
KH		 5864int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5865{
5866 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5867 int r = EMULATE_DONE;
5868
5869 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5870
5871 /*
5872 * rflags is the old, "raw" value of the flags. The new value has
5873 * not been saved yet.
5874 *
5875 * This is correct even for TF set by the guest, because "the
5876 * processor will not generate this exception after the instruction
5877 * that sets the TF flag".
5878 */
5879 if (unlikely(rflags & X86_EFLAGS_TF))
5880 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5881 return r == EMULATE_DONE;
5882}
5883EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5884
4a1e10d5
PB		 5885static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5886{
4a1e10d5
PB		 5887 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5888 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5889 struct kvm_run *kvm_run = vcpu->run;
5890 unsigned long eip = kvm_get_linear_rip(vcpu);
5891 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5892 vcpu->arch.guest_debug_dr7,
5893 vcpu->arch.eff_db);
5894
5895 if (dr6 != 0) {
6f43ed01 5896 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5897 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5898 kvm_run->debug.arch.exception = DB_VECTOR;
5899 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5900 *r = EMULATE_USER_EXIT;
5901 return true;
5902 }
5903 }
5904
4161a569
NA		 5905 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5906 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5907 unsigned long eip = kvm_get_linear_rip(vcpu);
5908 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5909 vcpu->arch.dr7,
5910 vcpu->arch.db);
5911
5912 if (dr6 != 0) {
5913 vcpu->arch.dr6 &= ~15;
6f43ed01 5914 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5915 kvm_queue_exception(vcpu, DB_VECTOR);
5916 *r = EMULATE_DONE;
5917 return true;
5918 }
5919 }
5920
5921 return false;
5922}
5923
51d8b661
AP		 5924int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5925 unsigned long cr2,
dc25e89e
AP		 5926 int emulation_type,
5927 void *insn,
5928 int insn_len)
bbd9b64e 5929{
95cb2295 5930 int r;
9d74191a 5931 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5932 bool writeback = true;
93c05d3e 5933 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5934
93c05d3e
XG		 5935 /*
5936 * Clear write_fault_to_shadow_pgtable here to ensure it is
5937 * never reused.
5938 */
5939 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5940 kvm_clear_exception_queue(vcpu);
8d7d8102 5941
571008da 5942 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5943 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5944
5945 /*
5946 * We will reenter on the same instruction since
5947 * we do not set complete_userspace_io. This does not
5948 * handle watchpoints yet, those would be handled in
5949 * the emulate_ops.
5950 */
d391f120
VK		 5951 if (!(emulation_type & EMULTYPE_SKIP) &&
5952 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 5953 return r;
5954
9d74191a
TY		 5955 ctxt->interruptibility = 0;
5956 ctxt->have_exception = false;
e0ad0b47 5957 ctxt->exception.vector = -1;
9d74191a 5958 ctxt->perm_ok = false;
bbd9b64e 5959
b51e974f 5960 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5961
9d74191a 5962 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5963
e46479f8 5964 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5965 ++vcpu->stat.insn_emulation;
1d2887e2 5966 if (r != EMULATION_OK) {
4005996e
AK		 5967 if (emulation_type & EMULTYPE_TRAP_UD)
5968 return EMULATE_FAIL;
991eebf9
GN		 5969 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5970 emulation_type))
bbd9b64e 5971 return EMULATE_DONE;
6ea6e843
PB		 5972 if (ctxt->have_exception && inject_emulated_exception(vcpu))
5973 return EMULATE_DONE;
6d77dbfc
GN		 5974 if (emulation_type & EMULTYPE_SKIP)
5975 return EMULATE_FAIL;
5976 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5977 }
5978 }
5979
ba8afb6b 5980 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5981 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5982 if (ctxt->eflags & X86_EFLAGS_RF)
5983 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5984 return EMULATE_DONE;
5985 }
5986
1cb3f3ae
XG		 5987 if (retry_instruction(ctxt, cr2, emulation_type))
5988 return EMULATE_DONE;
5989
7ae441ea 5990 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5991 changes registers values during IO operation */
7ae441ea
GN		 5992 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5993 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5994 emulator_invalidate_register_cache(ctxt);
7ae441ea 5995 }
4d2179e1 5996
5cd21917 5997restart:
0f89b207
TL		 5998 /* Save the faulting GPA (cr2) in the address field */
5999 ctxt->exception.address = cr2;
6000
9d74191a 6001 r = x86_emulate_insn(ctxt);
bbd9b64e 6002
775fde86
JR		 6003 if (r == EMULATION_INTERCEPTED)
6004 return EMULATE_DONE;
6005
d2ddd1c4 6006 if (r == EMULATION_FAILED) {
991eebf9
GN		 6007 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6008 emulation_type))
c3cd7ffa
GN		 6009 return EMULATE_DONE;
6010
6d77dbfc 6011 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 6012 }
6013
9d74191a 6014 if (ctxt->have_exception) {
d2ddd1c4 6015 r = EMULATE_DONE;
ef54bcfe
PB		 6016 if (inject_emulated_exception(vcpu))
6017 return r;
d2ddd1c4 6018 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6019 if (!vcpu->arch.pio.in) {
6020 /* FIXME: return into emulator if single-stepping. */
3457e419 6021 vcpu->arch.pio.count = 0;
0912c977 6022 } else {
7ae441ea 6023 writeback = false;
716d51ab
GN		 6024 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6025 }
ac0a48c3 6026 r = EMULATE_USER_EXIT;
7ae441ea
GN		 6027 } else if (vcpu->mmio_needed) {
6028 if (!vcpu->mmio_is_write)
6029 writeback = false;
ac0a48c3 6030 r = EMULATE_USER_EXIT;
716d51ab 6031 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6032 } else if (r == EMULATION_RESTART)
5cd21917 6033 goto restart;
d2ddd1c4
GN		 6034 else
6035 r = EMULATE_DONE;
f850e2e6 6036
7ae441ea 6037 if (writeback) {
6addfc42 6038 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6039 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6040 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 6041 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 6042 if (r == EMULATE_DONE &&
6043 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
6044 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 6045 if (!ctxt->have_exception ||
6046 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6047 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 6048
6049 /*
6050 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6051 * do nothing, and it will be requested again as soon as
6052 * the shadow expires. But we still need to check here,
6053 * because POPF has no interrupt shadow.
6054 */
6055 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6056 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6057 } else
6058 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6059
6060 return r;
de7d789a 6061}
51d8b661 6062EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 6063
dca7f128
SC		 6064static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6065 unsigned short port)
de7d789a 6066{
cf8f70bf 6067 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 6068 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6069 size, port, &val, 1);
cf8f70bf 6070 /* do not return to emulator after return from userspace */
7972995b 6071 vcpu->arch.pio.count = 0;
de7d789a
CO		 6072 return ret;
6073}
de7d789a 6074
8370c3d0
TL		 6075static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6076{
6077 unsigned long val;
6078
6079 /* We should only ever be called with arch.pio.count equal to 1 */
6080 BUG_ON(vcpu->arch.pio.count != 1);
6081
6082 /* For size less than 4 we merge, else we zero extend */
6083 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6084 : 0;
6085
6086 /*
6087 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6088 * the copy and tracing
6089 */
6090 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6091 vcpu->arch.pio.port, &val, 1);
6092 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6093
6094 return 1;
6095}
6096
dca7f128
SC		 6097static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6098 unsigned short port)
8370c3d0
TL		 6099{
6100 unsigned long val;
6101 int ret;
6102
6103 /* For size less than 4 we merge, else we zero extend */
6104 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6105
6106 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6107 &val, 1);
6108 if (ret) {
6109 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6110 return ret;
6111 }
6112
6113 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6114
6115 return 0;
6116}
dca7f128
SC		 6117
6118int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6119{
6120 int ret = kvm_skip_emulated_instruction(vcpu);
6121
6122 /*
6123 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6124 * KVM_EXIT_DEBUG here.
6125 */
6126 if (in)
6127 return kvm_fast_pio_in(vcpu, size, port) && ret;
6128 else
6129 return kvm_fast_pio_out(vcpu, size, port) && ret;
6130}
6131EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 6132
251a5fd6 6133static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6134{
0a3aee0d 6135 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6136 return 0;
8cfdc000
ZA		 6137}
6138
6139static void tsc_khz_changed(void *data)
c8076604 6140{
8cfdc000
ZA		 6141 struct cpufreq_freqs *freq = data;
6142 unsigned long khz = 0;
6143
6144 if (data)
6145 khz = freq->new;
6146 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6147 khz = cpufreq_quick_get(raw_smp_processor_id());
6148 if (!khz)
6149 khz = tsc_khz;
0a3aee0d 6150 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6151}
6152
5fa4ec9c 6153#ifdef CONFIG_X86_64
0092e434
VK		 6154static void kvm_hyperv_tsc_notifier(void)
6155{
0092e434
VK		 6156 struct kvm *kvm;
6157 struct kvm_vcpu *vcpu;
6158 int cpu;
6159
6160 spin_lock(&kvm_lock);
6161 list_for_each_entry(kvm, &vm_list, vm_list)
6162 kvm_make_mclock_inprogress_request(kvm);
6163
6164 hyperv_stop_tsc_emulation();
6165
6166 /* TSC frequency always matches when on Hyper-V */
6167 for_each_present_cpu(cpu)
6168 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6169 kvm_max_guest_tsc_khz = tsc_khz;
6170
6171 list_for_each_entry(kvm, &vm_list, vm_list) {
6172 struct kvm_arch *ka = &kvm->arch;
6173
6174 spin_lock(&ka->pvclock_gtod_sync_lock);
6175
6176 pvclock_update_vm_gtod_copy(kvm);
6177
6178 kvm_for_each_vcpu(cpu, vcpu, kvm)
6179 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6180
6181 kvm_for_each_vcpu(cpu, vcpu, kvm)
6182 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6183
6184 spin_unlock(&ka->pvclock_gtod_sync_lock);
6185 }
6186 spin_unlock(&kvm_lock);
0092e434 6187}
5fa4ec9c 6188#endif
0092e434 6189
c8076604
GH		 6190static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6191 void *data)
6192{
6193 struct cpufreq_freqs *freq = data;
6194 struct kvm *kvm;
6195 struct kvm_vcpu *vcpu;
6196 int i, send_ipi = 0;
6197
8cfdc000
ZA		 6198 /*
6199 * We allow guests to temporarily run on slowing clocks,
6200 * provided we notify them after, or to run on accelerating
6201 * clocks, provided we notify them before. Thus time never
6202 * goes backwards.
6203 *
6204 * However, we have a problem. We can't atomically update
6205 * the frequency of a given CPU from this function; it is
6206 * merely a notifier, which can be called from any CPU.
6207 * Changing the TSC frequency at arbitrary points in time
6208 * requires a recomputation of local variables related to
6209 * the TSC for each VCPU. We must flag these local variables
6210 * to be updated and be sure the update takes place with the
6211 * new frequency before any guests proceed.
6212 *
6213 * Unfortunately, the combination of hotplug CPU and frequency
6214 * change creates an intractable locking scenario; the order
6215 * of when these callouts happen is undefined with respect to
6216 * CPU hotplug, and they can race with each other. As such,
6217 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6218 * undefined; you can actually have a CPU frequency change take
6219 * place in between the computation of X and the setting of the
6220 * variable. To protect against this problem, all updates of
6221 * the per_cpu tsc_khz variable are done in an interrupt
6222 * protected IPI, and all callers wishing to update the value
6223 * must wait for a synchronous IPI to complete (which is trivial
6224 * if the caller is on the CPU already). This establishes the
6225 * necessary total order on variable updates.
6226 *
6227 * Note that because a guest time update may take place
6228 * anytime after the setting of the VCPU's request bit, the
6229 * correct TSC value must be set before the request. However,
6230 * to ensure the update actually makes it to any guest which
6231 * starts running in hardware virtualization between the set
6232 * and the acquisition of the spinlock, we must also ping the
6233 * CPU after setting the request bit.
6234 *
6235 */
6236
c8076604
GH		 6237 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6238 return 0;
6239 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6240 return 0;
8cfdc000
ZA		 6241
6242 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 6243
2f303b74 6244 spin_lock(&kvm_lock);
c8076604 6245 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6246 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 6247 if (vcpu->cpu != freq->cpu)
6248 continue;
c285545f 6249 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 6250 if (vcpu->cpu != smp_processor_id())
8cfdc000 6251 send_ipi = 1;
c8076604
GH		 6252 }
6253 }
2f303b74 6254 spin_unlock(&kvm_lock);
c8076604
GH		 6255
6256 if (freq->old < freq->new && send_ipi) {
6257 /*
6258 * We upscale the frequency. Must make the guest
6259 * doesn't see old kvmclock values while running with
6260 * the new frequency, otherwise we risk the guest sees
6261 * time go backwards.
6262 *
6263 * In case we update the frequency for another cpu
6264 * (which might be in guest context) send an interrupt
6265 * to kick the cpu out of guest context. Next time
6266 * guest context is entered kvmclock will be updated,
6267 * so the guest will not see stale values.
6268 */
8cfdc000 6269 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 6270 }
6271 return 0;
6272}
6273
6274static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6275 .notifier_call = kvmclock_cpufreq_notifier
6276};
6277
251a5fd6 6278static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6279{
251a5fd6
SAS		 6280 tsc_khz_changed(NULL);
6281 return 0;
8cfdc000
ZA		 6282}
6283
b820cc0c
ZA		 6284static void kvm_timer_init(void)
6285{
c285545f 6286 max_tsc_khz = tsc_khz;
460dd42e 6287
b820cc0c 6288 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6289#ifdef CONFIG_CPU_FREQ
6290 struct cpufreq_policy policy;
758f588d
BP		 6291 int cpu;
6292
c285545f 6293 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6294 cpu = get_cpu();
6295 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6296 if (policy.cpuinfo.max_freq)
6297 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6298 put_cpu();
c285545f 6299#endif
b820cc0c
ZA		 6300 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6301 CPUFREQ_TRANSITION_NOTIFIER);
6302 }
c285545f 6303 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6304
73c1b41e 6305 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6306 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6307}
6308
ff9d07a0
ZY		 6309static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6310
f5132b01 6311int kvm_is_in_guest(void)
ff9d07a0 6312{
086c9855 6313 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6314}
6315
6316static int kvm_is_user_mode(void)
6317{
6318 int user_mode = 3;
dcf46b94 6319
086c9855
AS		 6320 if (__this_cpu_read(current_vcpu))
6321 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6322
ff9d07a0
ZY		 6323 return user_mode != 0;
6324}
6325
6326static unsigned long kvm_get_guest_ip(void)
6327{
6328 unsigned long ip = 0;
dcf46b94 6329
086c9855
AS		 6330 if (__this_cpu_read(current_vcpu))
6331 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6332
ff9d07a0
ZY		 6333 return ip;
6334}
6335
6336static struct perf_guest_info_callbacks kvm_guest_cbs = {
6337 .is_in_guest = kvm_is_in_guest,
6338 .is_user_mode = kvm_is_user_mode,
6339 .get_guest_ip = kvm_get_guest_ip,
6340};
6341
6342void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
6343{
086c9855 6344 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 6345}
6346EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
6347
6348void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6349{
086c9855 6350 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 6351}
6352EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6353
ce88decf
XG		 6354static void kvm_set_mmio_spte_mask(void)
6355{
6356 u64 mask;
6357 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6358
6359 /*
6360 * Set the reserved bits and the present bit of an paging-structure
6361 * entry to generate page fault with PFER.RSV = 1.
6362 */
885032b9 6363 /* Mask the reserved physical address bits. */
d1431483 6364 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6365
885032b9 6366 /* Set the present bit. */
ce88decf
XG		 6367 mask |= 1ull;
6368
6369#ifdef CONFIG_X86_64
6370 /*
6371 * If reserved bit is not supported, clear the present bit to disable
6372 * mmio page fault.
6373 */
6374 if (maxphyaddr == 52)
6375 mask &= ~1ull;
6376#endif
6377
dcdca5fe 6378 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6379}
6380
16e8d74d
MT		 6381#ifdef CONFIG_X86_64
6382static void pvclock_gtod_update_fn(struct work_struct *work)
6383{
d828199e
MT		 6384 struct kvm *kvm;
6385
6386 struct kvm_vcpu *vcpu;
6387 int i;
6388
2f303b74 6389 spin_lock(&kvm_lock);
d828199e
MT		 6390 list_for_each_entry(kvm, &vm_list, vm_list)
6391 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6392 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6393 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6394 spin_unlock(&kvm_lock);
16e8d74d
MT		 6395}
6396
6397static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6398
6399/*
6400 * Notification about pvclock gtod data update.
6401 */
6402static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6403 void *priv)
6404{
6405 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6406 struct timekeeper *tk = priv;
6407
6408 update_pvclock_gtod(tk);
6409
6410 /* disable master clock if host does not trust, or does not
b0c39dc6 6411 * use, TSC based clocksource.
16e8d74d 6412 */
b0c39dc6 6413 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6414 atomic_read(&kvm_guest_has_master_clock) != 0)
6415 queue_work(system_long_wq, &pvclock_gtod_work);
6416
6417 return 0;
6418}
6419
6420static struct notifier_block pvclock_gtod_notifier = {
6421 .notifier_call = pvclock_gtod_notify,
6422};
6423#endif
6424
f8c16bba 6425int kvm_arch_init(void *opaque)
043405e1 6426{
b820cc0c 6427 int r;
6b61edf7 6428 struct kvm_x86_ops *ops = opaque;
f8c16bba 6429
f8c16bba
ZX		 6430 if (kvm_x86_ops) {
6431 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6432 r = -EEXIST;
6433 goto out;
f8c16bba
ZX		 6434 }
6435
6436 if (!ops->cpu_has_kvm_support()) {
6437 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6438 r = -EOPNOTSUPP;
6439 goto out;
f8c16bba
ZX		 6440 }
6441 if (ops->disabled_by_bios()) {
6442 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6443 r = -EOPNOTSUPP;
6444 goto out;
f8c16bba
ZX		 6445 }
6446
013f6a5d
MT		 6447 r = -ENOMEM;
6448 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6449 if (!shared_msrs) {
6450 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6451 goto out;
6452 }
6453
97db56ce
AK		 6454 r = kvm_mmu_module_init();
6455 if (r)
013f6a5d 6456 goto out_free_percpu;
97db56ce 6457
ce88decf 6458 kvm_set_mmio_spte_mask();
97db56ce 6459
f8c16bba 6460 kvm_x86_ops = ops;
920c8377 6461
7b52345e 6462 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6463 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6464 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6465 kvm_timer_init();
c8076604 6466
ff9d07a0
ZY		 6467 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6468
d366bf7e 6469 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6470 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6471
c5cc421b 6472 kvm_lapic_init();
16e8d74d
MT		 6473#ifdef CONFIG_X86_64
6474 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 6475
5fa4ec9c 6476 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 6477 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 6478#endif
6479
f8c16bba 6480 return 0;
56c6d28a 6481
013f6a5d
MT		 6482out_free_percpu:
6483 free_percpu(shared_msrs);
56c6d28a 6484out:
56c6d28a 6485 return r;
043405e1 6486}
8776e519 6487
f8c16bba
ZX		 6488void kvm_arch_exit(void)
6489{
0092e434 6490#ifdef CONFIG_X86_64
5fa4ec9c 6491 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 6492 clear_hv_tscchange_cb();
6493#endif
cef84c30 6494 kvm_lapic_exit();
ff9d07a0
ZY		 6495 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6496
888d256e
JK		 6497 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6498 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6499 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6500 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6501#ifdef CONFIG_X86_64
6502 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6503#endif
f8c16bba 6504 kvm_x86_ops = NULL;
56c6d28a 6505 kvm_mmu_module_exit();
013f6a5d 6506 free_percpu(shared_msrs);
56c6d28a 6507}
f8c16bba 6508
5cb56059 6509int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6510{
6511 ++vcpu->stat.halt_exits;
35754c98 6512 if (lapic_in_kernel(vcpu)) {
a4535290 6513 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6514 return 1;
6515 } else {
6516 vcpu->run->exit_reason = KVM_EXIT_HLT;
6517 return 0;
6518 }
6519}
5cb56059
JS		 6520EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6521
6522int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6523{
6affcbed
KH		 6524 int ret = kvm_skip_emulated_instruction(vcpu);
6525 /*
6526 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6527 * KVM_EXIT_DEBUG here.
6528 */
6529 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6530}
8776e519
HB		 6531EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6532
8ef81a9a 6533#ifdef CONFIG_X86_64
55dd00a7
MT		 6534static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6535 unsigned long clock_type)
6536{
6537 struct kvm_clock_pairing clock_pairing;
6538 struct timespec ts;
80fbd89c 6539 u64 cycle;
55dd00a7
MT		 6540 int ret;
6541
6542 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6543 return -KVM_EOPNOTSUPP;
6544
6545 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6546 return -KVM_EOPNOTSUPP;
6547
6548 clock_pairing.sec = ts.tv_sec;
6549 clock_pairing.nsec = ts.tv_nsec;
6550 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6551 clock_pairing.flags = 0;
6552
6553 ret = 0;
6554 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6555 sizeof(struct kvm_clock_pairing)))
6556 ret = -KVM_EFAULT;
6557
6558 return ret;
6559}
8ef81a9a 6560#endif
55dd00a7 6561
6aef266c
SV		 6562/*
6563 * kvm_pv_kick_cpu_op: Kick a vcpu.
6564 *
6565 * @apicid - apicid of vcpu to be kicked.
6566 */
6567static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6568{
24d2166b 6569 struct kvm_lapic_irq lapic_irq;
6aef266c 6570
24d2166b
R		 6571 lapic_irq.shorthand = 0;
6572 lapic_irq.dest_mode = 0;
ebd28fcb 6573 lapic_irq.level = 0;
24d2166b 6574 lapic_irq.dest_id = apicid;
93bbf0b8 6575 lapic_irq.msi_redir_hint = false;
6aef266c 6576
24d2166b 6577 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6578 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6579}
6580
d62caabb
AS		 6581void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6582{
6583 vcpu->arch.apicv_active = false;
6584 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6585}
6586
8776e519
HB		 6587int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6588{
6589 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6590 int op_64_bit, r;
8776e519 6591
6affcbed 6592 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6593
55cd8e5a
GN		 6594 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6595 return kvm_hv_hypercall(vcpu);
6596
5fdbf976
MT		 6597 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6598 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6599 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6600 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6601 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6602
229456fc 6603 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6604
a449c7aa
NA		 6605 op_64_bit = is_64_bit_mode(vcpu);
6606 if (!op_64_bit) {
8776e519
HB		 6607 nr &= 0xFFFFFFFF;
6608 a0 &= 0xFFFFFFFF;
6609 a1 &= 0xFFFFFFFF;
6610 a2 &= 0xFFFFFFFF;
6611 a3 &= 0xFFFFFFFF;
6612 }
6613
07708c4a
JK		 6614 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6615 ret = -KVM_EPERM;
6616 goto out;
6617 }
6618
8776e519 6619 switch (nr) {
b93463aa
AK		 6620 case KVM_HC_VAPIC_POLL_IRQ:
6621 ret = 0;
6622 break;
6aef266c
SV		 6623 case KVM_HC_KICK_CPU:
6624 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6625 ret = 0;
6626 break;
8ef81a9a 6627#ifdef CONFIG_X86_64
55dd00a7
MT		 6628 case KVM_HC_CLOCK_PAIRING:
6629 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6630 break;
8ef81a9a 6631#endif
8776e519
HB		 6632 default:
6633 ret = -KVM_ENOSYS;
6634 break;
6635 }
07708c4a 6636out:
a449c7aa
NA		 6637 if (!op_64_bit)
6638 ret = (u32)ret;
5fdbf976 6639 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6640 ++vcpu->stat.hypercalls;
2f333bcb 6641 return r;
8776e519
HB		 6642}
6643EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6644
b6785def 6645static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6646{
d6aa1000 6647 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6648 char instruction[3];
5fdbf976 6649 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6650
8776e519 6651 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6652
ce2e852e
DV		 6653 return emulator_write_emulated(ctxt, rip, instruction, 3,
6654 &ctxt->exception);
8776e519
HB		 6655}
6656
851ba692 6657static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6658{
782d422b
MG		 6659 return vcpu->run->request_interrupt_window &&
6660 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6661}
6662
851ba692 6663static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6664{
851ba692
AK		 6665 struct kvm_run *kvm_run = vcpu->run;
6666
91586a3b 6667 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6668 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6669 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6670 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6671 kvm_run->ready_for_interrupt_injection =
6672 pic_in_kernel(vcpu->kvm) ||
782d422b 6673 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6674}
6675
95ba8273
GN		 6676static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6677{
6678 int max_irr, tpr;
6679
6680 if (!kvm_x86_ops->update_cr8_intercept)
6681 return;
6682
bce87cce 6683 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6684 return;
6685
d62caabb
AS		 6686 if (vcpu->arch.apicv_active)
6687 return;
6688
8db3baa2
GN		 6689 if (!vcpu->arch.apic->vapic_addr)
6690 max_irr = kvm_lapic_find_highest_irr(vcpu);
6691 else
6692 max_irr = -1;
95ba8273
GN		 6693
6694 if (max_irr != -1)
6695 max_irr >>= 4;
6696
6697 tpr = kvm_lapic_get_cr8(vcpu);
6698
6699 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6700}
6701
b6b8a145 6702static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6703{
b6b8a145
JK		 6704 int r;
6705
95ba8273 6706 /* try to reinject previous events if any */
664f8e26
WL		 6707 if (vcpu->arch.exception.injected) {
6708 kvm_x86_ops->queue_exception(vcpu);
6709 return 0;
6710 }
6711
6712 /*
6713 * Exceptions must be injected immediately, or the exception
6714 * frame will have the address of the NMI or interrupt handler.
6715 */
6716 if (!vcpu->arch.exception.pending) {
6717 if (vcpu->arch.nmi_injected) {
6718 kvm_x86_ops->set_nmi(vcpu);
6719 return 0;
6720 }
6721
6722 if (vcpu->arch.interrupt.pending) {
6723 kvm_x86_ops->set_irq(vcpu);
6724 return 0;
6725 }
6726 }
6727
6728 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6729 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6730 if (r != 0)
6731 return r;
6732 }
6733
6734 /* try to inject new event if pending */
b59bb7bd 6735 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6736 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6737 vcpu->arch.exception.has_error_code,
6738 vcpu->arch.exception.error_code);
d6e8c854 6739
664f8e26
WL		 6740 vcpu->arch.exception.pending = false;
6741 vcpu->arch.exception.injected = true;
6742
d6e8c854
NA		 6743 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6744 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6745 X86_EFLAGS_RF);
6746
6bdf0662
NA		 6747 if (vcpu->arch.exception.nr == DB_VECTOR &&
6748 (vcpu->arch.dr7 & DR7_GD)) {
6749 vcpu->arch.dr7 &= ~DR7_GD;
6750 kvm_update_dr7(vcpu);
6751 }
6752
cfcd20e5 6753 kvm_x86_ops->queue_exception(vcpu);
72d7b374 6754 } else if (vcpu->arch.smi_pending && !is_smm(vcpu) && kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 6755 vcpu->arch.smi_pending = false;
52797bf9 6756 ++vcpu->arch.smi_count;
ee2cd4b7 6757 enter_smm(vcpu);
c43203ca 6758 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6759 --vcpu->arch.nmi_pending;
6760 vcpu->arch.nmi_injected = true;
6761 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6762 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6763 /*
6764 * Because interrupts can be injected asynchronously, we are
6765 * calling check_nested_events again here to avoid a race condition.
6766 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6767 * proposal and current concerns. Perhaps we should be setting
6768 * KVM_REQ_EVENT only on certain events and not unconditionally?
6769 */
6770 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6771 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6772 if (r != 0)
6773 return r;
6774 }
95ba8273 6775 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6776 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6777 false);
6778 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6779 }
6780 }
ee2cd4b7 6781
b6b8a145 6782 return 0;
95ba8273
GN		 6783}
6784
7460fb4a
AK		 6785static void process_nmi(struct kvm_vcpu *vcpu)
6786{
6787 unsigned limit = 2;
6788
6789 /*
6790 * x86 is limited to one NMI running, and one NMI pending after it.
6791 * If an NMI is already in progress, limit further NMIs to just one.
6792 * Otherwise, allow two (and we'll inject the first one immediately).
6793 */
6794 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6795 limit = 1;
6796
6797 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6798 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6799 kvm_make_request(KVM_REQ_EVENT, vcpu);
6800}
6801
ee2cd4b7 6802static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6803{
6804 u32 flags = 0;
6805 flags |= seg->g << 23;
6806 flags |= seg->db << 22;
6807 flags |= seg->l << 21;
6808 flags |= seg->avl << 20;
6809 flags |= seg->present << 15;
6810 flags |= seg->dpl << 13;
6811 flags |= seg->s << 12;
6812 flags |= seg->type << 8;
6813 return flags;
6814}
6815
ee2cd4b7 6816static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6817{
6818 struct kvm_segment seg;
6819 int offset;
6820
6821 kvm_get_segment(vcpu, &seg, n);
6822 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6823
6824 if (n < 3)
6825 offset = 0x7f84 + n * 12;
6826 else
6827 offset = 0x7f2c + (n - 3) * 12;
6828
6829 put_smstate(u32, buf, offset + 8, seg.base);
6830 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6831 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6832}
6833
efbb288a 6834#ifdef CONFIG_X86_64
ee2cd4b7 6835static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6836{
6837 struct kvm_segment seg;
6838 int offset;
6839 u16 flags;
6840
6841 kvm_get_segment(vcpu, &seg, n);
6842 offset = 0x7e00 + n * 16;
6843
ee2cd4b7 6844 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6845 put_smstate(u16, buf, offset, seg.selector);
6846 put_smstate(u16, buf, offset + 2, flags);
6847 put_smstate(u32, buf, offset + 4, seg.limit);
6848 put_smstate(u64, buf, offset + 8, seg.base);
6849}
efbb288a 6850#endif
660a5d51 6851
ee2cd4b7 6852static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6853{
6854 struct desc_ptr dt;
6855 struct kvm_segment seg;
6856 unsigned long val;
6857 int i;
6858
6859 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6860 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6861 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6862 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6863
6864 for (i = 0; i < 8; i++)
6865 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6866
6867 kvm_get_dr(vcpu, 6, &val);
6868 put_smstate(u32, buf, 0x7fcc, (u32)val);
6869 kvm_get_dr(vcpu, 7, &val);
6870 put_smstate(u32, buf, 0x7fc8, (u32)val);
6871
6872 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6873 put_smstate(u32, buf, 0x7fc4, seg.selector);
6874 put_smstate(u32, buf, 0x7f64, seg.base);
6875 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6876 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6877
6878 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6879 put_smstate(u32, buf, 0x7fc0, seg.selector);
6880 put_smstate(u32, buf, 0x7f80, seg.base);
6881 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6882 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6883
6884 kvm_x86_ops->get_gdt(vcpu, &dt);
6885 put_smstate(u32, buf, 0x7f74, dt.address);
6886 put_smstate(u32, buf, 0x7f70, dt.size);
6887
6888 kvm_x86_ops->get_idt(vcpu, &dt);
6889 put_smstate(u32, buf, 0x7f58, dt.address);
6890 put_smstate(u32, buf, 0x7f54, dt.size);
6891
6892 for (i = 0; i < 6; i++)
ee2cd4b7 6893 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6894
6895 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6896
6897 /* revision id */
6898 put_smstate(u32, buf, 0x7efc, 0x00020000);
6899 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6900}
6901
ee2cd4b7 6902static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6903{
6904#ifdef CONFIG_X86_64
6905 struct desc_ptr dt;
6906 struct kvm_segment seg;
6907 unsigned long val;
6908 int i;
6909
6910 for (i = 0; i < 16; i++)
6911 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6912
6913 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6914 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6915
6916 kvm_get_dr(vcpu, 6, &val);
6917 put_smstate(u64, buf, 0x7f68, val);
6918 kvm_get_dr(vcpu, 7, &val);
6919 put_smstate(u64, buf, 0x7f60, val);
6920
6921 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6922 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6923 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6924
6925 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6926
6927 /* revision id */
6928 put_smstate(u32, buf, 0x7efc, 0x00020064);
6929
6930 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6931
6932 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6933 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6934 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6935 put_smstate(u32, buf, 0x7e94, seg.limit);
6936 put_smstate(u64, buf, 0x7e98, seg.base);
6937
6938 kvm_x86_ops->get_idt(vcpu, &dt);
6939 put_smstate(u32, buf, 0x7e84, dt.size);
6940 put_smstate(u64, buf, 0x7e88, dt.address);
6941
6942 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6943 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6944 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6945 put_smstate(u32, buf, 0x7e74, seg.limit);
6946 put_smstate(u64, buf, 0x7e78, seg.base);
6947
6948 kvm_x86_ops->get_gdt(vcpu, &dt);
6949 put_smstate(u32, buf, 0x7e64, dt.size);
6950 put_smstate(u64, buf, 0x7e68, dt.address);
6951
6952 for (i = 0; i < 6; i++)
ee2cd4b7 6953 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6954#else
6955 WARN_ON_ONCE(1);
6956#endif
6957}
6958
ee2cd4b7 6959static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6960{
660a5d51 6961 struct kvm_segment cs, ds;
18c3626e 6962 struct desc_ptr dt;
660a5d51
PB		 6963 char buf[512];
6964 u32 cr0;
6965
660a5d51 6966 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 6967 memset(buf, 0, 512);
d6321d49 6968 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 6969 enter_smm_save_state_64(vcpu, buf);
660a5d51 6970 else
ee2cd4b7 6971 enter_smm_save_state_32(vcpu, buf);
660a5d51 6972
0234bf88
LP		 6973 /*
6974 * Give pre_enter_smm() a chance to make ISA-specific changes to the
6975 * vCPU state (e.g. leave guest mode) after we've saved the state into
6976 * the SMM state-save area.
6977 */
6978 kvm_x86_ops->pre_enter_smm(vcpu, buf);
6979
6980 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 6981 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6982
6983 if (kvm_x86_ops->get_nmi_mask(vcpu))
6984 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6985 else
6986 kvm_x86_ops->set_nmi_mask(vcpu, true);
6987
6988 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6989 kvm_rip_write(vcpu, 0x8000);
6990
6991 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6992 kvm_x86_ops->set_cr0(vcpu, cr0);
6993 vcpu->arch.cr0 = cr0;
6994
6995 kvm_x86_ops->set_cr4(vcpu, 0);
6996
18c3626e
PB		 6997 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6998 dt.address = dt.size = 0;
6999 kvm_x86_ops->set_idt(vcpu, &dt);
7000
660a5d51
PB		 7001 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7002
7003 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7004 cs.base = vcpu->arch.smbase;
7005
7006 ds.selector = 0;
7007 ds.base = 0;
7008
7009 cs.limit = ds.limit = 0xffffffff;
7010 cs.type = ds.type = 0x3;
7011 cs.dpl = ds.dpl = 0;
7012 cs.db = ds.db = 0;
7013 cs.s = ds.s = 1;
7014 cs.l = ds.l = 0;
7015 cs.g = ds.g = 1;
7016 cs.avl = ds.avl = 0;
7017 cs.present = ds.present = 1;
7018 cs.unusable = ds.unusable = 0;
7019 cs.padding = ds.padding = 0;
7020
7021 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7022 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7023 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7024 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7025 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7026 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7027
d6321d49 7028 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 7029 kvm_x86_ops->set_efer(vcpu, 0);
7030
7031 kvm_update_cpuid(vcpu);
7032 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7033}
7034
ee2cd4b7 7035static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7036{
7037 vcpu->arch.smi_pending = true;
7038 kvm_make_request(KVM_REQ_EVENT, vcpu);
7039}
7040
2860c4b1
PB		 7041void kvm_make_scan_ioapic_request(struct kvm *kvm)
7042{
7043 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7044}
7045
3d81bc7e 7046static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7047{
5c919412
AS		 7048 u64 eoi_exit_bitmap[4];
7049
3d81bc7e
YZ		 7050 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7051 return;
c7c9c56c 7052
6308630b 7053 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7054
b053b2ae 7055 if (irqchip_split(vcpu->kvm))
6308630b 7056 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7057 else {
fa59cc00 7058 if (vcpu->arch.apicv_active)
d62caabb 7059 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 7060 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7061 }
5c919412
AS		 7062 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7063 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7064 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7065}
7066
b1394e74
RK		 7067void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7068 unsigned long start, unsigned long end)
7069{
7070 unsigned long apic_address;
7071
7072 /*
7073 * The physical address of apic access page is stored in the VMCS.
7074 * Update it when it becomes invalid.
7075 */
7076 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7077 if (start <= apic_address && apic_address < end)
7078 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
7079}
7080
4256f43f
TC		 7081void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7082{
c24ae0dc
TC		 7083 struct page *page = NULL;
7084
35754c98 7085 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7086 return;
7087
4256f43f
TC		 7088 if (!kvm_x86_ops->set_apic_access_page_addr)
7089 return;
7090
c24ae0dc 7091 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7092 if (is_error_page(page))
7093 return;
c24ae0dc
TC		 7094 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7095
7096 /*
7097 * Do not pin apic access page in memory, the MMU notifier
7098 * will call us again if it is migrated or swapped out.
7099 */
7100 put_page(page);
4256f43f
TC		 7101}
7102EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7103
9357d939 7104/*
362c698f 7105 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7106 * exiting to the userspace. Otherwise, the value will be returned to the
7107 * userspace.
7108 */
851ba692 7109static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7110{
7111 int r;
62a193ed
MG		 7112 bool req_int_win =
7113 dm_request_for_irq_injection(vcpu) &&
7114 kvm_cpu_accept_dm_intr(vcpu);
7115
730dca42 7116 bool req_immediate_exit = false;
b6c7a5dc 7117
2fa6e1e1 7118 if (kvm_request_pending(vcpu)) {
a8eeb04a 7119 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7120 kvm_mmu_unload(vcpu);
a8eeb04a 7121 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7122 __kvm_migrate_timers(vcpu);
d828199e
MT		 7123 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7124 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7125 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7126 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7127 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7128 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7129 if (unlikely(r))
7130 goto out;
7131 }
a8eeb04a 7132 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7133 kvm_mmu_sync_roots(vcpu);
a8eeb04a 7134 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7135 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7136 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7137 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7138 r = 0;
7139 goto out;
7140 }
a8eeb04a 7141 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7142 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7143 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7144 r = 0;
7145 goto out;
7146 }
af585b92
GN		 7147 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7148 /* Page is swapped out. Do synthetic halt */
7149 vcpu->arch.apf.halted = true;
7150 r = 1;
7151 goto out;
7152 }
c9aaa895
GC		 7153 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7154 record_steal_time(vcpu);
64d60670
PB		 7155 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7156 process_smi(vcpu);
7460fb4a
AK		 7157 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7158 process_nmi(vcpu);
f5132b01 7159 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7160 kvm_pmu_handle_event(vcpu);
f5132b01 7161 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7162 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7163 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7164 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7165 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7166 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7167 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7168 vcpu->run->eoi.vector =
7169 vcpu->arch.pending_ioapic_eoi;
7170 r = 0;
7171 goto out;
7172 }
7173 }
3d81bc7e
YZ		 7174 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7175 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 7176 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7177 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7178 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7179 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7180 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7181 r = 0;
7182 goto out;
7183 }
e516cebb
AS		 7184 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7185 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7186 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7187 r = 0;
7188 goto out;
7189 }
db397571
AS		 7190 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7191 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7192 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7193 r = 0;
7194 goto out;
7195 }
f3b138c5
AS		 7196
7197 /*
7198 * KVM_REQ_HV_STIMER has to be processed after
7199 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7200 * depend on the guest clock being up-to-date
7201 */
1f4b34f8
AS		 7202 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7203 kvm_hv_process_stimers(vcpu);
2f52d58c 7204 }
b93463aa 7205
b463a6f7 7206 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7207 ++vcpu->stat.req_event;
66450a21
JK		 7208 kvm_apic_accept_events(vcpu);
7209 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7210 r = 1;
7211 goto out;
7212 }
7213
b6b8a145
JK		 7214 if (inject_pending_event(vcpu, req_int_win) != 0)
7215 req_immediate_exit = true;
321c5658 7216 else {
cc3d967f 7217 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7218 *
cc3d967f
LP		 7219 * SMIs have three cases:
7220 * 1) They can be nested, and then there is nothing to
7221 * do here because RSM will cause a vmexit anyway.
7222 * 2) There is an ISA-specific reason why SMI cannot be
7223 * injected, and the moment when this changes can be
7224 * intercepted.
7225 * 3) Or the SMI can be pending because
7226 * inject_pending_event has completed the injection
7227 * of an IRQ or NMI from the previous vmexit, and
7228 * then we request an immediate exit to inject the
7229 * SMI.
c43203ca
PB		 7230 */
7231 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7232 if (!kvm_x86_ops->enable_smi_window(vcpu))
7233 req_immediate_exit = true;
321c5658
YS		 7234 if (vcpu->arch.nmi_pending)
7235 kvm_x86_ops->enable_nmi_window(vcpu);
7236 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7237 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7238 WARN_ON(vcpu->arch.exception.pending);
321c5658 7239 }
b463a6f7
AK		 7240
7241 if (kvm_lapic_enabled(vcpu)) {
7242 update_cr8_intercept(vcpu);
7243 kvm_lapic_sync_to_vapic(vcpu);
7244 }
7245 }
7246
d8368af8
AK		 7247 r = kvm_mmu_reload(vcpu);
7248 if (unlikely(r)) {
d905c069 7249 goto cancel_injection;
d8368af8
AK		 7250 }
7251
b6c7a5dc
HB		 7252 preempt_disable();
7253
7254 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7255
7256 /*
7257 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7258 * IPI are then delayed after guest entry, which ensures that they
7259 * result in virtual interrupt delivery.
7260 */
7261 local_irq_disable();
6b7e2d09
XG		 7262 vcpu->mode = IN_GUEST_MODE;
7263
01b71917
MT		 7264 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7265
0f127d12 7266 /*
b95234c8 7267 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7268 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 7269 *
7270 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7271 * pairs with the memory barrier implicit in pi_test_and_set_on
7272 * (see vmx_deliver_posted_interrupt).
7273 *
7274 * 3) This also orders the write to mode from any reads to the page
7275 * tables done while the VCPU is running. Please see the comment
7276 * in kvm_flush_remote_tlbs.
6b7e2d09 7277 */
01b71917 7278 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7279
b95234c8
PB		 7280 /*
7281 * This handles the case where a posted interrupt was
7282 * notified with kvm_vcpu_kick.
7283 */
fa59cc00
LA		 7284 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7285 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7286
2fa6e1e1 7287 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7288 || need_resched() || signal_pending(current)) {
6b7e2d09 7289 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7290 smp_wmb();
6c142801
AK		 7291 local_irq_enable();
7292 preempt_enable();
01b71917 7293 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7294 r = 1;
d905c069 7295 goto cancel_injection;
6c142801
AK		 7296 }
7297
fc5b7f3b
DM		 7298 kvm_load_guest_xcr0(vcpu);
7299
c43203ca
PB		 7300 if (req_immediate_exit) {
7301 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 7302 smp_send_reschedule(vcpu->cpu);
c43203ca 7303 }
d6185f20 7304
8b89fe1f 7305 trace_kvm_entry(vcpu->vcpu_id);
9c48d517
WL		 7306 if (lapic_timer_advance_ns)
7307 wait_lapic_expire(vcpu);
6edaa530 7308 guest_enter_irqoff();
b6c7a5dc 7309
42dbaa5a 7310 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7311 set_debugreg(0, 7);
7312 set_debugreg(vcpu->arch.eff_db[0], 0);
7313 set_debugreg(vcpu->arch.eff_db[1], 1);
7314 set_debugreg(vcpu->arch.eff_db[2], 2);
7315 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7316 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7317 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7318 }
b6c7a5dc 7319
851ba692 7320 kvm_x86_ops->run(vcpu);
b6c7a5dc 7321
c77fb5fe
PB		 7322 /*
7323 * Do this here before restoring debug registers on the host. And
7324 * since we do this before handling the vmexit, a DR access vmexit
7325 * can (a) read the correct value of the debug registers, (b) set
7326 * KVM_DEBUGREG_WONT_EXIT again.
7327 */
7328 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7329 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7330 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7331 kvm_update_dr0123(vcpu);
7332 kvm_update_dr6(vcpu);
7333 kvm_update_dr7(vcpu);
7334 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7335 }
7336
24f1e32c
FW		 7337 /*
7338 * If the guest has used debug registers, at least dr7
7339 * will be disabled while returning to the host.
7340 * If we don't have active breakpoints in the host, we don't
7341 * care about the messed up debug address registers. But if
7342 * we have some of them active, restore the old state.
7343 */
59d8eb53 7344 if (hw_breakpoint_active())
24f1e32c 7345 hw_breakpoint_restore();
42dbaa5a 7346
4ba76538 7347 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7348
6b7e2d09 7349 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7350 smp_wmb();
a547c6db 7351
fc5b7f3b
DM		 7352 kvm_put_guest_xcr0(vcpu);
7353
a547c6db 7354 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 7355
7356 ++vcpu->stat.exits;
7357
f2485b3e 7358 guest_exit_irqoff();
b6c7a5dc 7359
f2485b3e 7360 local_irq_enable();
b6c7a5dc
HB		 7361 preempt_enable();
7362
f656ce01 7363 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7364
b6c7a5dc
HB		 7365 /*
7366 * Profile KVM exit RIPs:
7367 */
7368 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7369 unsigned long rip = kvm_rip_read(vcpu);
7370 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7371 }
7372
cc578287
ZA		 7373 if (unlikely(vcpu->arch.tsc_always_catchup))
7374 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7375
5cfb1d5a
MT		 7376 if (vcpu->arch.apic_attention)
7377 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7378
618232e2 7379 vcpu->arch.gpa_available = false;
851ba692 7380 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7381 return r;
7382
7383cancel_injection:
7384 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7385 if (unlikely(vcpu->arch.apic_attention))
7386 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7387out:
7388 return r;
7389}
b6c7a5dc 7390
362c698f
PB		 7391static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7392{
bf9f6ac8
FW		 7393 if (!kvm_arch_vcpu_runnable(vcpu) &&
7394 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7395 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7396 kvm_vcpu_block(vcpu);
7397 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7398
7399 if (kvm_x86_ops->post_block)
7400 kvm_x86_ops->post_block(vcpu);
7401
9c8fd1ba
PB		 7402 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7403 return 1;
7404 }
362c698f
PB		 7405
7406 kvm_apic_accept_events(vcpu);
7407 switch(vcpu->arch.mp_state) {
7408 case KVM_MP_STATE_HALTED:
7409 vcpu->arch.pv.pv_unhalted = false;
7410 vcpu->arch.mp_state =
7411 KVM_MP_STATE_RUNNABLE;
7412 case KVM_MP_STATE_RUNNABLE:
7413 vcpu->arch.apf.halted = false;
7414 break;
7415 case KVM_MP_STATE_INIT_RECEIVED:
7416 break;
7417 default:
7418 return -EINTR;
7419 break;
7420 }
7421 return 1;
7422}
09cec754 7423
5d9bc648
PB		 7424static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7425{
0ad3bed6
PB		 7426 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7427 kvm_x86_ops->check_nested_events(vcpu, false);
7428
5d9bc648
PB		 7429 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7430 !vcpu->arch.apf.halted);
7431}
7432
362c698f 7433static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7434{
7435 int r;
f656ce01 7436 struct kvm *kvm = vcpu->kvm;
d7690175 7437
f656ce01 7438 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7439
362c698f 7440 for (;;) {
58f800d5 7441 if (kvm_vcpu_running(vcpu)) {
851ba692 7442 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7443 } else {
362c698f 7444 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7445 }
7446
09cec754
GN		 7447 if (r <= 0)
7448 break;
7449
72875d8a 7450 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7451 if (kvm_cpu_has_pending_timer(vcpu))
7452 kvm_inject_pending_timer_irqs(vcpu);
7453
782d422b
MG		 7454 if (dm_request_for_irq_injection(vcpu) &&
7455 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7456 r = 0;
7457 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7458 ++vcpu->stat.request_irq_exits;
362c698f 7459 break;
09cec754 7460 }
af585b92
GN		 7461
7462 kvm_check_async_pf_completion(vcpu);
7463
09cec754
GN		 7464 if (signal_pending(current)) {
7465 r = -EINTR;
851ba692 7466 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7467 ++vcpu->stat.signal_exits;
362c698f 7468 break;
09cec754
GN		 7469 }
7470 if (need_resched()) {
f656ce01 7471 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7472 cond_resched();
f656ce01 7473 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7474 }
b6c7a5dc
HB		 7475 }
7476
f656ce01 7477 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7478
7479 return r;
7480}
7481
716d51ab
GN		 7482static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7483{
7484 int r;
7485 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7486 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7487 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7488 if (r != EMULATE_DONE)
7489 return 0;
7490 return 1;
7491}
7492
7493static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7494{
7495 BUG_ON(!vcpu->arch.pio.count);
7496
7497 return complete_emulated_io(vcpu);
7498}
7499
f78146b0
AK		 7500/*
7501 * Implements the following, as a state machine:
7502 *
7503 * read:
7504 * for each fragment
87da7e66
XG		 7505 * for each mmio piece in the fragment
7506 * write gpa, len
7507 * exit
7508 * copy data
f78146b0
AK		 7509 * execute insn
7510 *
7511 * write:
7512 * for each fragment
87da7e66
XG		 7513 * for each mmio piece in the fragment
7514 * write gpa, len
7515 * copy data
7516 * exit
f78146b0 7517 */
716d51ab 7518static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7519{
7520 struct kvm_run *run = vcpu->run;
f78146b0 7521 struct kvm_mmio_fragment *frag;
87da7e66 7522 unsigned len;
5287f194 7523
716d51ab 7524 BUG_ON(!vcpu->mmio_needed);
5287f194 7525
716d51ab 7526 /* Complete previous fragment */
87da7e66
XG		 7527 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7528 len = min(8u, frag->len);
716d51ab 7529 if (!vcpu->mmio_is_write)
87da7e66
XG		 7530 memcpy(frag->data, run->mmio.data, len);
7531
7532 if (frag->len <= 8) {
7533 /* Switch to the next fragment. */
7534 frag++;
7535 vcpu->mmio_cur_fragment++;
7536 } else {
7537 /* Go forward to the next mmio piece. */
7538 frag->data += len;
7539 frag->gpa += len;
7540 frag->len -= len;
7541 }
7542
a08d3b3b 7543 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7544 vcpu->mmio_needed = 0;
0912c977
PB		 7545
7546 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7547 if (vcpu->mmio_is_write)
716d51ab
GN		 7548 return 1;
7549 vcpu->mmio_read_completed = 1;
7550 return complete_emulated_io(vcpu);
7551 }
87da7e66 7552
716d51ab
GN		 7553 run->exit_reason = KVM_EXIT_MMIO;
7554 run->mmio.phys_addr = frag->gpa;
7555 if (vcpu->mmio_is_write)
87da7e66
XG		 7556 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7557 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7558 run->mmio.is_write = vcpu->mmio_is_write;
7559 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7560 return 0;
5287f194
AK		 7561}
7562
b6c7a5dc
HB		 7563int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7564{
7565 int r;
b6c7a5dc 7566
accb757d 7567 vcpu_load(vcpu);
20b7035c 7568 kvm_sigset_activate(vcpu);
5663d8f9
PX		 7569 kvm_load_guest_fpu(vcpu);
7570
a4535290 7571 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7572 if (kvm_run->immediate_exit) {
7573 r = -EINTR;
7574 goto out;
7575 }
b6c7a5dc 7576 kvm_vcpu_block(vcpu);
66450a21 7577 kvm_apic_accept_events(vcpu);
72875d8a 7578 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7579 r = -EAGAIN;
a0595000
JS		 7580 if (signal_pending(current)) {
7581 r = -EINTR;
7582 vcpu->run->exit_reason = KVM_EXIT_INTR;
7583 ++vcpu->stat.signal_exits;
7584 }
ac9f6dc0 7585 goto out;
b6c7a5dc
HB		 7586 }
7587
01643c51
KH		 7588 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
7589 r = -EINVAL;
7590 goto out;
7591 }
7592
7593 if (vcpu->run->kvm_dirty_regs) {
7594 r = sync_regs(vcpu);
7595 if (r != 0)
7596 goto out;
7597 }
7598
b6c7a5dc 7599 /* re-sync apic's tpr */
35754c98 7600 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7601 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7602 r = -EINVAL;
7603 goto out;
7604 }
7605 }
b6c7a5dc 7606
716d51ab
GN		 7607 if (unlikely(vcpu->arch.complete_userspace_io)) {
7608 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7609 vcpu->arch.complete_userspace_io = NULL;
7610 r = cui(vcpu);
7611 if (r <= 0)
5663d8f9 7612 goto out;
716d51ab
GN		 7613 } else
7614 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7615
460df4c1
PB		 7616 if (kvm_run->immediate_exit)
7617 r = -EINTR;
7618 else
7619 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7620
7621out:
5663d8f9 7622 kvm_put_guest_fpu(vcpu);
01643c51
KH		 7623 if (vcpu->run->kvm_valid_regs)
7624 store_regs(vcpu);
f1d86e46 7625 post_kvm_run_save(vcpu);
20b7035c 7626 kvm_sigset_deactivate(vcpu);
b6c7a5dc 7627
accb757d 7628 vcpu_put(vcpu);
b6c7a5dc
HB		 7629 return r;
7630}
7631
01643c51 7632static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7633{
7ae441ea
GN		 7634 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7635 /*
7636 * We are here if userspace calls get_regs() in the middle of
7637 * instruction emulation. Registers state needs to be copied
4a969980 7638 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7639 * that usually, but some bad designed PV devices (vmware
7640 * backdoor interface) need this to work
7641 */
dd856efa 7642 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7643 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7644 }
5fdbf976
MT		 7645 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7646 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7647 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7648 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7649 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7650 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7651 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7652 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7653#ifdef CONFIG_X86_64
5fdbf976
MT		 7654 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7655 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7656 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7657 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7658 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7659 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7660 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7661 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7662#endif
7663
5fdbf976 7664 regs->rip = kvm_rip_read(vcpu);
91586a3b 7665 regs->rflags = kvm_get_rflags(vcpu);
01643c51 7666}
b6c7a5dc 7667
01643c51
KH		 7668int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7669{
7670 vcpu_load(vcpu);
7671 __get_regs(vcpu, regs);
1fc9b76b 7672 vcpu_put(vcpu);
b6c7a5dc
HB		 7673 return 0;
7674}
7675
01643c51 7676static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7677{
7ae441ea
GN		 7678 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7679 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7680
5fdbf976
MT		 7681 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7682 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7683 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7684 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7685 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7686 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7687 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7688 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7689#ifdef CONFIG_X86_64
5fdbf976
MT		 7690 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7691 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7692 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7693 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7694 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7695 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7696 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7697 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7698#endif
7699
5fdbf976 7700 kvm_rip_write(vcpu, regs->rip);
d73235d1 7701 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 7702
b4f14abd
JK		 7703 vcpu->arch.exception.pending = false;
7704
3842d135 7705 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 7706}
3842d135 7707
01643c51
KH		 7708int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7709{
7710 vcpu_load(vcpu);
7711 __set_regs(vcpu, regs);
875656fe 7712 vcpu_put(vcpu);
b6c7a5dc
HB		 7713 return 0;
7714}
7715
b6c7a5dc
HB		 7716void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7717{
7718 struct kvm_segment cs;
7719
3e6e0aab 7720 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7721 *db = cs.db;
7722 *l = cs.l;
7723}
7724EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7725
01643c51 7726static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 7727{
89a27f4d 7728 struct desc_ptr dt;
b6c7a5dc 7729
3e6e0aab
GT		 7730 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7731 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7732 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7733 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7734 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7735 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7736
3e6e0aab
GT		 7737 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7738 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7739
7740 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7741 sregs->idt.limit = dt.size;
7742 sregs->idt.base = dt.address;
b6c7a5dc 7743 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7744 sregs->gdt.limit = dt.size;
7745 sregs->gdt.base = dt.address;
b6c7a5dc 7746
4d4ec087 7747 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7748 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7749 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7750 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7751 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7752 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7753 sregs->apic_base = kvm_get_apic_base(vcpu);
7754
923c61bb 7755 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7756
36752c9b 7757 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7758 set_bit(vcpu->arch.interrupt.nr,
7759 (unsigned long *)sregs->interrupt_bitmap);
01643c51 7760}
16d7a191 7761
01643c51
KH		 7762int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7763 struct kvm_sregs *sregs)
7764{
7765 vcpu_load(vcpu);
7766 __get_sregs(vcpu, sregs);
bcdec41c 7767 vcpu_put(vcpu);
b6c7a5dc
HB		 7768 return 0;
7769}
7770
62d9f0db
MT		 7771int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7772 struct kvm_mp_state *mp_state)
7773{
fd232561
CD		 7774 vcpu_load(vcpu);
7775
66450a21 7776 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7777 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7778 vcpu->arch.pv.pv_unhalted)
7779 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7780 else
7781 mp_state->mp_state = vcpu->arch.mp_state;
7782
fd232561 7783 vcpu_put(vcpu);
62d9f0db
MT		 7784 return 0;
7785}
7786
7787int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7788 struct kvm_mp_state *mp_state)
7789{
e83dff5e
CD		 7790 int ret = -EINVAL;
7791
7792 vcpu_load(vcpu);
7793
bce87cce 7794 if (!lapic_in_kernel(vcpu) &&
66450a21 7795 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 7796 goto out;
66450a21 7797
28bf2888
DH		 7798 /* INITs are latched while in SMM */
7799 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7800 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7801 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 7802 goto out;
28bf2888 7803
66450a21
JK		 7804 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7805 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7806 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7807 } else
7808 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7809 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 7810
7811 ret = 0;
7812out:
7813 vcpu_put(vcpu);
7814 return ret;
62d9f0db
MT		 7815}
7816
7f3d35fd
KW		 7817int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7818 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7819{
9d74191a 7820 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7821 int ret;
e01c2426 7822
8ec4722d 7823 init_emulate_ctxt(vcpu);
c697518a 7824
7f3d35fd 7825 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7826 has_error_code, error_code);
c697518a 7827
c697518a 7828 if (ret)
19d04437 7829 return EMULATE_FAIL;
37817f29 7830
9d74191a
TY		 7831 kvm_rip_write(vcpu, ctxt->eip);
7832 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7833 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7834 return EMULATE_DONE;
37817f29
IE		 7835}
7836EXPORT_SYMBOL_GPL(kvm_task_switch);
7837
f2981033
LT		 7838int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
7839{
37b95951 7840 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 7841 /*
7842 * When EFER.LME and CR0.PG are set, the processor is in
7843 * 64-bit mode (though maybe in a 32-bit code segment).
7844 * CR4.PAE and EFER.LMA must be set.
7845 */
37b95951 7846 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 7847 || !(sregs->efer & EFER_LMA))
7848 return -EINVAL;
7849 } else {
7850 /*
7851 * Not in 64-bit mode: EFER.LMA is clear and the code
7852 * segment cannot be 64-bit.
7853 */
7854 if (sregs->efer & EFER_LMA || sregs->cs.l)
7855 return -EINVAL;
7856 }
7857
7858 return 0;
7859}
7860
01643c51 7861static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 7862{
58cb628d 7863 struct msr_data apic_base_msr;
b6c7a5dc 7864 int mmu_reset_needed = 0;
63f42e02 7865 int pending_vec, max_bits, idx;
89a27f4d 7866 struct desc_ptr dt;
b4ef9d4e
CD		 7867 int ret = -EINVAL;
7868
d6321d49
RK		 7869 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7870 (sregs->cr4 & X86_CR4_OSXSAVE))
b4ef9d4e 7871 goto out;
6d1068b3 7872
f2981033 7873 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 7874 goto out;
f2981033 7875
d3802286
JM		 7876 apic_base_msr.data = sregs->apic_base;
7877 apic_base_msr.host_initiated = true;
7878 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 7879 goto out;
6d1068b3 7880
89a27f4d
GN		 7881 dt.size = sregs->idt.limit;
7882 dt.address = sregs->idt.base;
b6c7a5dc 7883 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7884 dt.size = sregs->gdt.limit;
7885 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7886 kvm_x86_ops->set_gdt(vcpu, &dt);
7887
ad312c7c 7888 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7889 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7890 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7891 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7892
2d3ad1f4 7893 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7894
f6801dff 7895 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7896 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 7897
4d4ec087 7898 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7899 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7900 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7901
fc78f519 7902 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7903 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7904 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7905 kvm_update_cpuid(vcpu);
63f42e02
XG		 7906
7907 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7908 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7909 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7910 mmu_reset_needed = 1;
7911 }
63f42e02 7912 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7913
7914 if (mmu_reset_needed)
7915 kvm_mmu_reset_context(vcpu);
7916
a50abc3b 7917 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7918 pending_vec = find_first_bit(
7919 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7920 if (pending_vec < max_bits) {
66fd3f7f 7921 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7922 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7923 }
7924
3e6e0aab
GT		 7925 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7926 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7927 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7928 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7929 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7930 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7931
3e6e0aab
GT		 7932 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7933 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7934
5f0269f5
ME		 7935 update_cr8_intercept(vcpu);
7936
9c3e4aab 7937 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7938 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7939 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7940 !is_protmode(vcpu))
9c3e4aab
MT		 7941 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7942
3842d135
AK		 7943 kvm_make_request(KVM_REQ_EVENT, vcpu);
7944
b4ef9d4e
CD		 7945 ret = 0;
7946out:
01643c51
KH		 7947 return ret;
7948}
7949
7950int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7951 struct kvm_sregs *sregs)
7952{
7953 int ret;
7954
7955 vcpu_load(vcpu);
7956 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 7957 vcpu_put(vcpu);
7958 return ret;
b6c7a5dc
HB		 7959}
7960
d0bfb940
JK		 7961int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7962 struct kvm_guest_debug *dbg)
b6c7a5dc 7963{
355be0b9 7964 unsigned long rflags;
ae675ef0 7965 int i, r;
b6c7a5dc 7966
66b56562
CD		 7967 vcpu_load(vcpu);
7968
4f926bf2
JK		 7969 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7970 r = -EBUSY;
7971 if (vcpu->arch.exception.pending)
2122ff5e 7972 goto out;
4f926bf2
JK		 7973 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7974 kvm_queue_exception(vcpu, DB_VECTOR);
7975 else
7976 kvm_queue_exception(vcpu, BP_VECTOR);
7977 }
7978
91586a3b
JK		 7979 /*
7980 * Read rflags as long as potentially injected trace flags are still
7981 * filtered out.
7982 */
7983 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7984
7985 vcpu->guest_debug = dbg->control;
7986 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7987 vcpu->guest_debug = 0;
7988
7989 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7990 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7991 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7992 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7993 } else {
7994 for (i = 0; i < KVM_NR_DB_REGS; i++)
7995 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7996 }
c8639010 7997 kvm_update_dr7(vcpu);
ae675ef0 7998
f92653ee
JK		 7999 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8000 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8001 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 8002
91586a3b
JK		 8003 /*
8004 * Trigger an rflags update that will inject or remove the trace
8005 * flags.
8006 */
8007 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 8008
a96036b8 8009 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 8010
4f926bf2 8011 r = 0;
d0bfb940 8012
2122ff5e 8013out:
66b56562 8014 vcpu_put(vcpu);
b6c7a5dc
HB		 8015 return r;
8016}
8017
8b006791
ZX		 8018/*
8019 * Translate a guest virtual address to a guest physical address.
8020 */
8021int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8022 struct kvm_translation *tr)
8023{
8024 unsigned long vaddr = tr->linear_address;
8025 gpa_t gpa;
f656ce01 8026 int idx;
8b006791 8027
1da5b61d
CD		 8028 vcpu_load(vcpu);
8029
f656ce01 8030 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8031 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8032 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8033 tr->physical_address = gpa;
8034 tr->valid = gpa != UNMAPPED_GVA;
8035 tr->writeable = 1;
8036 tr->usermode = 0;
8b006791 8037
1da5b61d 8038 vcpu_put(vcpu);
8b006791
ZX		 8039 return 0;
8040}
8041
d0752060
HB		 8042int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8043{
1393123e 8044 struct fxregs_state *fxsave;
d0752060 8045
1393123e 8046 vcpu_load(vcpu);
d0752060 8047
1393123e 8048 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060
HB		 8049 memcpy(fpu->fpr, fxsave->st_space, 128);
8050 fpu->fcw = fxsave->cwd;
8051 fpu->fsw = fxsave->swd;
8052 fpu->ftwx = fxsave->twd;
8053 fpu->last_opcode = fxsave->fop;
8054 fpu->last_ip = fxsave->rip;
8055 fpu->last_dp = fxsave->rdp;
8056 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
8057
1393123e 8058 vcpu_put(vcpu);
d0752060
HB		 8059 return 0;
8060}
8061
8062int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8063{
6a96bc7f
CD		 8064 struct fxregs_state *fxsave;
8065
8066 vcpu_load(vcpu);
8067
8068 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060 8069
d0752060
HB		 8070 memcpy(fxsave->st_space, fpu->fpr, 128);
8071 fxsave->cwd = fpu->fcw;
8072 fxsave->swd = fpu->fsw;
8073 fxsave->twd = fpu->ftwx;
8074 fxsave->fop = fpu->last_opcode;
8075 fxsave->rip = fpu->last_ip;
8076 fxsave->rdp = fpu->last_dp;
8077 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
8078
6a96bc7f 8079 vcpu_put(vcpu);
d0752060
HB		 8080 return 0;
8081}
8082
01643c51
KH		 8083static void store_regs(struct kvm_vcpu *vcpu)
8084{
8085 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8086
8087 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8088 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8089
8090 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8091 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8092
8093 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8094 kvm_vcpu_ioctl_x86_get_vcpu_events(
8095 vcpu, &vcpu->run->s.regs.events);
8096}
8097
8098static int sync_regs(struct kvm_vcpu *vcpu)
8099{
8100 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8101 return -EINVAL;
8102
8103 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8104 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8105 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8106 }
8107 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8108 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8109 return -EINVAL;
8110 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8111 }
8112 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8113 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8114 vcpu, &vcpu->run->s.regs.events))
8115 return -EINVAL;
8116 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8117 }
8118
8119 return 0;
8120}
8121
0ee6a517 8122static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8123{
bf935b0b 8124 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 8125 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 8126 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 8127 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 8128
2acf923e
DC		 8129 /*
8130 * Ensure guest xcr0 is valid for loading
8131 */
d91cab78 8132 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 8133
ad312c7c 8134 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 8135}
d0752060 8136
f775b13e 8137/* Swap (qemu) user FPU context for the guest FPU context. */
d0752060
HB		 8138void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8139{
f775b13e
RR		 8140 preempt_disable();
8141 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
38cfd5e3
PB		 8142 /* PKRU is separately restored in kvm_x86_ops->run. */
8143 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
8144 ~XFEATURE_MASK_PKRU);
f775b13e 8145 preempt_enable();
0c04851c 8146 trace_kvm_fpu(1);
d0752060 8147}
d0752060 8148
f775b13e 8149/* When vcpu_run ends, restore user space FPU context. */
d0752060
HB		 8150void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8151{
f775b13e 8152 preempt_disable();
4f836347 8153 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
f775b13e
RR		 8154 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
8155 preempt_enable();
f096ed85 8156 ++vcpu->stat.fpu_reload;
0c04851c 8157 trace_kvm_fpu(0);
d0752060 8158}
e9b11c17
ZX		 8159
8160void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8161{
bd768e14
IY		 8162 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8163
12f9a48f 8164 kvmclock_reset(vcpu);
7f1ea208 8165
e9b11c17 8166 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 8167 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 8168}
8169
8170struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8171 unsigned int id)
8172{
c447e76b
LL		 8173 struct kvm_vcpu *vcpu;
8174
b0c39dc6 8175 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 8176 printk_once(KERN_WARNING
8177 "kvm: SMP vm created on host with unstable TSC; "
8178 "guest TSC will not be reliable\n");
c447e76b
LL		 8179
8180 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8181
c447e76b 8182 return vcpu;
26e5215f 8183}
e9b11c17 8184
26e5215f
AK		 8185int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8186{
19efffa2 8187 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 8188 vcpu_load(vcpu);
d28bc9dd 8189 kvm_vcpu_reset(vcpu, false);
8a3c1a33 8190 kvm_mmu_setup(vcpu);
e9b11c17 8191 vcpu_put(vcpu);
ec7660cc 8192 return 0;
e9b11c17
ZX		 8193}
8194
31928aa5 8195void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 8196{
8fe8ab46 8197 struct msr_data msr;
332967a3 8198 struct kvm *kvm = vcpu->kvm;
42897d86 8199
d3457c87
RK		 8200 kvm_hv_vcpu_postcreate(vcpu);
8201
ec7660cc 8202 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 8203 return;
ec7660cc 8204 vcpu_load(vcpu);
8fe8ab46
WA		 8205 msr.data = 0x0;
8206 msr.index = MSR_IA32_TSC;
8207 msr.host_initiated = true;
8208 kvm_write_tsc(vcpu, &msr);
42897d86 8209 vcpu_put(vcpu);
ec7660cc 8210 mutex_unlock(&vcpu->mutex);
42897d86 8211
630994b3
MT		 8212 if (!kvmclock_periodic_sync)
8213 return;
8214
332967a3
AJ		 8215 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8216 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8217}
8218
d40ccc62 8219void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8220{
344d9588
GN		 8221 vcpu->arch.apf.msr_val = 0;
8222
ec7660cc 8223 vcpu_load(vcpu);
e9b11c17
ZX		 8224 kvm_mmu_unload(vcpu);
8225 vcpu_put(vcpu);
8226
8227 kvm_x86_ops->vcpu_free(vcpu);
8228}
8229
d28bc9dd 8230void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8231{
b7e31be3
RK		 8232 kvm_lapic_reset(vcpu, init_event);
8233
e69fab5d
PB		 8234 vcpu->arch.hflags = 0;
8235
c43203ca 8236 vcpu->arch.smi_pending = 0;
52797bf9 8237 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8238 atomic_set(&vcpu->arch.nmi_queued, 0);
8239 vcpu->arch.nmi_pending = 0;
448fa4a9 8240 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8241 kvm_clear_interrupt_queue(vcpu);
8242 kvm_clear_exception_queue(vcpu);
664f8e26 8243 vcpu->arch.exception.pending = false;
448fa4a9 8244
42dbaa5a 8245 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8246 kvm_update_dr0123(vcpu);
6f43ed01 8247 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8248 kvm_update_dr6(vcpu);
42dbaa5a 8249 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8250 kvm_update_dr7(vcpu);
42dbaa5a 8251
1119022c
NA		 8252 vcpu->arch.cr2 = 0;
8253
3842d135 8254 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8255 vcpu->arch.apf.msr_val = 0;
c9aaa895 8256 vcpu->arch.st.msr_val = 0;
3842d135 8257
12f9a48f
GC		 8258 kvmclock_reset(vcpu);
8259
af585b92
GN		 8260 kvm_clear_async_pf_completion_queue(vcpu);
8261 kvm_async_pf_hash_reset(vcpu);
8262 vcpu->arch.apf.halted = false;
3842d135 8263
a554d207
WL		 8264 if (kvm_mpx_supported()) {
8265 void *mpx_state_buffer;
8266
8267 /*
8268 * To avoid have the INIT path from kvm_apic_has_events() that be
8269 * called with loaded FPU and does not let userspace fix the state.
8270 */
f775b13e
RR		 8271 if (init_event)
8272 kvm_put_guest_fpu(vcpu);
a554d207
WL		 8273 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8274 XFEATURE_MASK_BNDREGS);
8275 if (mpx_state_buffer)
8276 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8277 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8278 XFEATURE_MASK_BNDCSR);
8279 if (mpx_state_buffer)
8280 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 8281 if (init_event)
8282 kvm_load_guest_fpu(vcpu);
a554d207
WL		 8283 }
8284
64d60670 8285 if (!init_event) {
d28bc9dd 8286 kvm_pmu_reset(vcpu);
64d60670 8287 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 8288
8289 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8290 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 8291
8292 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 8293 }
f5132b01 8294
66f7b72e
JS		 8295 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8296 vcpu->arch.regs_avail = ~0;
8297 vcpu->arch.regs_dirty = ~0;
8298
a554d207
WL		 8299 vcpu->arch.ia32_xss = 0;
8300
d28bc9dd 8301 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 8302}
8303
2b4a273b 8304void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 8305{
8306 struct kvm_segment cs;
8307
8308 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8309 cs.selector = vector << 8;
8310 cs.base = vector << 12;
8311 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8312 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 8313}
8314
13a34e06 8315int kvm_arch_hardware_enable(void)
e9b11c17 8316{
ca84d1a2
ZA		 8317 struct kvm *kvm;
8318 struct kvm_vcpu *vcpu;
8319 int i;
0dd6a6ed
ZA		 8320 int ret;
8321 u64 local_tsc;
8322 u64 max_tsc = 0;
8323 bool stable, backwards_tsc = false;
18863bdd
AK		 8324
8325 kvm_shared_msr_cpu_online();
13a34e06 8326 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 8327 if (ret != 0)
8328 return ret;
8329
4ea1636b 8330 local_tsc = rdtsc();
b0c39dc6 8331 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 8332 list_for_each_entry(kvm, &vm_list, vm_list) {
8333 kvm_for_each_vcpu(i, vcpu, kvm) {
8334 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 8335 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8336 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8337 backwards_tsc = true;
8338 if (vcpu->arch.last_host_tsc > max_tsc)
8339 max_tsc = vcpu->arch.last_host_tsc;
8340 }
8341 }
8342 }
8343
8344 /*
8345 * Sometimes, even reliable TSCs go backwards. This happens on
8346 * platforms that reset TSC during suspend or hibernate actions, but
8347 * maintain synchronization. We must compensate. Fortunately, we can
8348 * detect that condition here, which happens early in CPU bringup,
8349 * before any KVM threads can be running. Unfortunately, we can't
8350 * bring the TSCs fully up to date with real time, as we aren't yet far
8351 * enough into CPU bringup that we know how much real time has actually
108b249c 8352 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 8353 * variables that haven't been updated yet.
8354 *
8355 * So we simply find the maximum observed TSC above, then record the
8356 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8357 * the adjustment will be applied. Note that we accumulate
8358 * adjustments, in case multiple suspend cycles happen before some VCPU
8359 * gets a chance to run again. In the event that no KVM threads get a
8360 * chance to run, we will miss the entire elapsed period, as we'll have
8361 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8362 * loose cycle time. This isn't too big a deal, since the loss will be
8363 * uniform across all VCPUs (not to mention the scenario is extremely
8364 * unlikely). It is possible that a second hibernate recovery happens
8365 * much faster than a first, causing the observed TSC here to be
8366 * smaller; this would require additional padding adjustment, which is
8367 * why we set last_host_tsc to the local tsc observed here.
8368 *
8369 * N.B. - this code below runs only on platforms with reliable TSC,
8370 * as that is the only way backwards_tsc is set above. Also note
8371 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8372 * have the same delta_cyc adjustment applied if backwards_tsc
8373 * is detected. Note further, this adjustment is only done once,
8374 * as we reset last_host_tsc on all VCPUs to stop this from being
8375 * called multiple times (one for each physical CPU bringup).
8376 *
4a969980 8377 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 8378 * will be compensated by the logic in vcpu_load, which sets the TSC to
8379 * catchup mode. This will catchup all VCPUs to real time, but cannot
8380 * guarantee that they stay in perfect synchronization.
8381 */
8382 if (backwards_tsc) {
8383 u64 delta_cyc = max_tsc - local_tsc;
8384 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8385 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 8386 kvm_for_each_vcpu(i, vcpu, kvm) {
8387 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8388 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8389 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8390 }
8391
8392 /*
8393 * We have to disable TSC offset matching.. if you were
8394 * booting a VM while issuing an S4 host suspend....
8395 * you may have some problem. Solving this issue is
8396 * left as an exercise to the reader.
8397 */
8398 kvm->arch.last_tsc_nsec = 0;
8399 kvm->arch.last_tsc_write = 0;
8400 }
8401
8402 }
8403 return 0;
e9b11c17
ZX		 8404}
8405
13a34e06 8406void kvm_arch_hardware_disable(void)
e9b11c17 8407{
13a34e06
RK		 8408 kvm_x86_ops->hardware_disable();
8409 drop_user_return_notifiers();
e9b11c17
ZX		 8410}
8411
8412int kvm_arch_hardware_setup(void)
8413{
9e9c3fe4
NA		 8414 int r;
8415
8416 r = kvm_x86_ops->hardware_setup();
8417 if (r != 0)
8418 return r;
8419
35181e86
HZ		 8420 if (kvm_has_tsc_control) {
8421 /*
8422 * Make sure the user can only configure tsc_khz values that
8423 * fit into a signed integer.
8424 * A min value is not calculated needed because it will always
8425 * be 1 on all machines.
8426 */
8427 u64 max = min(0x7fffffffULL,
8428 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8429 kvm_max_guest_tsc_khz = max;
8430
ad721883 8431 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8432 }
ad721883 8433
9e9c3fe4
NA		 8434 kvm_init_msr_list();
8435 return 0;
e9b11c17
ZX		 8436}
8437
8438void kvm_arch_hardware_unsetup(void)
8439{
8440 kvm_x86_ops->hardware_unsetup();
8441}
8442
8443void kvm_arch_check_processor_compat(void *rtn)
8444{
8445 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8446}
8447
8448bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8449{
8450 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8451}
8452EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8453
8454bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8455{
8456 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8457}
8458
54e9818f 8459struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8460EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8461
e9b11c17
ZX		 8462int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8463{
8464 struct page *page;
e9b11c17
ZX		 8465 int r;
8466
b2a05fef 8467 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8468 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8469 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8470 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8471 else
a4535290 8472 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8473
8474 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8475 if (!page) {
8476 r = -ENOMEM;
8477 goto fail;
8478 }
ad312c7c 8479 vcpu->arch.pio_data = page_address(page);
e9b11c17 8480
cc578287 8481 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8482
e9b11c17
ZX		 8483 r = kvm_mmu_create(vcpu);
8484 if (r < 0)
8485 goto fail_free_pio_data;
8486
26de7988 8487 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8488 r = kvm_create_lapic(vcpu);
8489 if (r < 0)
8490 goto fail_mmu_destroy;
54e9818f
GN		 8491 } else
8492 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8493
890ca9ae
HY		 8494 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8495 GFP_KERNEL);
8496 if (!vcpu->arch.mce_banks) {
8497 r = -ENOMEM;
443c39bc 8498 goto fail_free_lapic;
890ca9ae
HY		 8499 }
8500 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8501
f1797359
WY		 8502 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8503 r = -ENOMEM;
f5f48ee1 8504 goto fail_free_mce_banks;
f1797359 8505 }
f5f48ee1 8506
0ee6a517 8507 fx_init(vcpu);
66f7b72e 8508
4344ee98 8509 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8510
5a4f55cd
EK		 8511 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8512
74545705
RK		 8513 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8514
af585b92 8515 kvm_async_pf_hash_reset(vcpu);
f5132b01 8516 kvm_pmu_init(vcpu);
af585b92 8517
1c1a9ce9 8518 vcpu->arch.pending_external_vector = -1;
de63ad4c 8519 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8520
5c919412
AS		 8521 kvm_hv_vcpu_init(vcpu);
8522
e9b11c17 8523 return 0;
0ee6a517 8524
f5f48ee1
SY		 8525fail_free_mce_banks:
8526 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8527fail_free_lapic:
8528 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8529fail_mmu_destroy:
8530 kvm_mmu_destroy(vcpu);
8531fail_free_pio_data:
ad312c7c 8532 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8533fail:
8534 return r;
8535}
8536
8537void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8538{
f656ce01
MT		 8539 int idx;
8540
1f4b34f8 8541 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8542 kvm_pmu_destroy(vcpu);
36cb93fd 8543 kfree(vcpu->arch.mce_banks);
e9b11c17 8544 kvm_free_lapic(vcpu);
f656ce01 8545 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8546 kvm_mmu_destroy(vcpu);
f656ce01 8547 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8548 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8549 if (!lapic_in_kernel(vcpu))
54e9818f 8550 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8551}
d19a9cd2 8552
e790d9ef
RK		 8553void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8554{
ae97a3b8 8555 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8556}
8557
e08b9637 8558int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8559{
e08b9637
CO		 8560 if (type)
8561 return -EINVAL;
8562
6ef768fa 8563 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8564 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8565 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8566 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8567 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8568
5550af4d
SY		 8569 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8570 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8571 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8572 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8573 &kvm->arch.irq_sources_bitmap);
5550af4d 8574
038f8c11 8575 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8576 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 8577 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8578
108b249c 8579 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8580 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8581
7e44e449 8582 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8583 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8584
cbc0236a 8585 kvm_hv_init_vm(kvm);
0eb05bf2 8586 kvm_page_track_init(kvm);
13d268ca 8587 kvm_mmu_init_vm(kvm);
0eb05bf2 8588
03543133
SS		 8589 if (kvm_x86_ops->vm_init)
8590 return kvm_x86_ops->vm_init(kvm);
8591
d89f5eff 8592 return 0;
d19a9cd2
ZX		 8593}
8594
8595static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8596{
ec7660cc 8597 vcpu_load(vcpu);
d19a9cd2
ZX		 8598 kvm_mmu_unload(vcpu);
8599 vcpu_put(vcpu);
8600}
8601
8602static void kvm_free_vcpus(struct kvm *kvm)
8603{
8604 unsigned int i;
988a2cae 8605 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8606
8607 /*
8608 * Unpin any mmu pages first.
8609 */
af585b92
GN		 8610 kvm_for_each_vcpu(i, vcpu, kvm) {
8611 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8612 kvm_unload_vcpu_mmu(vcpu);
af585b92 8613 }
988a2cae
GN		 8614 kvm_for_each_vcpu(i, vcpu, kvm)
8615 kvm_arch_vcpu_free(vcpu);
8616
8617 mutex_lock(&kvm->lock);
8618 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8619 kvm->vcpus[i] = NULL;
d19a9cd2 8620
988a2cae
GN		 8621 atomic_set(&kvm->online_vcpus, 0);
8622 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8623}
8624
ad8ba2cd
SY		 8625void kvm_arch_sync_events(struct kvm *kvm)
8626{
332967a3 8627 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8628 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8629 kvm_free_pit(kvm);
ad8ba2cd
SY		 8630}
8631
1d8007bd 8632int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8633{
8634 int i, r;
25188b99 8635 unsigned long hva;
f0d648bd
PB		 8636 struct kvm_memslots *slots = kvm_memslots(kvm);
8637 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8638
8639 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8640 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8641 return -EINVAL;
9da0e4d5 8642
f0d648bd
PB		 8643 slot = id_to_memslot(slots, id);
8644 if (size) {
b21629da 8645 if (slot->npages)
f0d648bd
PB		 8646 return -EEXIST;
8647
8648 /*
8649 * MAP_SHARED to prevent internal slot pages from being moved
8650 * by fork()/COW.
8651 */
8652 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8653 MAP_SHARED | MAP_ANONYMOUS, 0);
8654 if (IS_ERR((void *)hva))
8655 return PTR_ERR((void *)hva);
8656 } else {
8657 if (!slot->npages)
8658 return 0;
8659
8660 hva = 0;
8661 }
8662
8663 old = *slot;
9da0e4d5 8664 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8665 struct kvm_userspace_memory_region m;
9da0e4d5 8666
1d8007bd
PB		 8667 m.slot = id | (i << 16);
8668 m.flags = 0;
8669 m.guest_phys_addr = gpa;
f0d648bd 8670 m.userspace_addr = hva;
1d8007bd 8671 m.memory_size = size;
9da0e4d5
PB		 8672 r = __kvm_set_memory_region(kvm, &m);
8673 if (r < 0)
8674 return r;
8675 }
8676
103c763c
EB		 8677 if (!size)
8678 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 8679
9da0e4d5
PB		 8680 return 0;
8681}
8682EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8683
1d8007bd 8684int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8685{
8686 int r;
8687
8688 mutex_lock(&kvm->slots_lock);
1d8007bd 8689 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8690 mutex_unlock(&kvm->slots_lock);
8691
8692 return r;
8693}
8694EXPORT_SYMBOL_GPL(x86_set_memory_region);
8695
d19a9cd2
ZX		 8696void kvm_arch_destroy_vm(struct kvm *kvm)
8697{
27469d29
AH		 8698 if (current->mm == kvm->mm) {
8699 /*
8700 * Free memory regions allocated on behalf of userspace,
8701 * unless the the memory map has changed due to process exit
8702 * or fd copying.
8703 */
1d8007bd
PB		 8704 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8705 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8706 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8707 }
03543133
SS		 8708 if (kvm_x86_ops->vm_destroy)
8709 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8710 kvm_pic_destroy(kvm);
8711 kvm_ioapic_destroy(kvm);
d19a9cd2 8712 kvm_free_vcpus(kvm);
af1bae54 8713 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8714 kvm_mmu_uninit_vm(kvm);
2beb6dad 8715 kvm_page_track_cleanup(kvm);
cbc0236a 8716 kvm_hv_destroy_vm(kvm);
d19a9cd2 8717}
0de10343 8718
5587027c 8719void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8720 struct kvm_memory_slot *dont)
8721{
8722 int i;
8723
d89cc617
TY		 8724 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8725 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8726 kvfree(free->arch.rmap[i]);
d89cc617 8727 free->arch.rmap[i] = NULL;
77d11309 8728 }
d89cc617
TY		 8729 if (i == 0)
8730 continue;
8731
8732 if (!dont || free->arch.lpage_info[i - 1] !=
8733 dont->arch.lpage_info[i - 1]) {
548ef284 8734 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8735 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8736 }
8737 }
21ebbeda
XG		 8738
8739 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8740}
8741
5587027c
AK		 8742int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8743 unsigned long npages)
db3fe4eb
TY		 8744{
8745 int i;
8746
d89cc617 8747 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8748 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8749 unsigned long ugfn;
8750 int lpages;
d89cc617 8751 int level = i + 1;
db3fe4eb
TY		 8752
8753 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8754 slot->base_gfn, level) + 1;
8755
d89cc617 8756 slot->arch.rmap[i] =
a7c3e901 8757 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8758 if (!slot->arch.rmap[i])
77d11309 8759 goto out_free;
d89cc617
TY		 8760 if (i == 0)
8761 continue;
77d11309 8762
a7c3e901 8763 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8764 if (!linfo)
db3fe4eb
TY		 8765 goto out_free;
8766
92f94f1e
XG		 8767 slot->arch.lpage_info[i - 1] = linfo;
8768
db3fe4eb 8769 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8770 linfo[0].disallow_lpage = 1;
db3fe4eb 8771 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8772 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8773 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8774 /*
8775 * If the gfn and userspace address are not aligned wrt each
8776 * other, or if explicitly asked to, disable large page
8777 * support for this slot
8778 */
8779 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8780 !kvm_largepages_enabled()) {
8781 unsigned long j;
8782
8783 for (j = 0; j < lpages; ++j)
92f94f1e 8784 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8785 }
8786 }
8787
21ebbeda
XG		 8788 if (kvm_page_track_create_memslot(slot, npages))
8789 goto out_free;
8790
db3fe4eb
TY		 8791 return 0;
8792
8793out_free:
d89cc617 8794 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8795 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8796 slot->arch.rmap[i] = NULL;
8797 if (i == 0)
8798 continue;
8799
548ef284 8800 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8801 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8802 }
8803 return -ENOMEM;
8804}
8805
15f46015 8806void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8807{
e6dff7d1
TY		 8808 /*
8809 * memslots->generation has been incremented.
8810 * mmio generation may have reached its maximum value.
8811 */
54bf36aa 8812 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8813}
8814
f7784b8e
MT		 8815int kvm_arch_prepare_memory_region(struct kvm *kvm,
8816 struct kvm_memory_slot *memslot,
09170a49 8817 const struct kvm_userspace_memory_region *mem,
7b6195a9 8818 enum kvm_mr_change change)
0de10343 8819{
f7784b8e
MT		 8820 return 0;
8821}
8822
88178fd4
KH		 8823static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8824 struct kvm_memory_slot *new)
8825{
8826 /* Still write protect RO slot */
8827 if (new->flags & KVM_MEM_READONLY) {
8828 kvm_mmu_slot_remove_write_access(kvm, new);
8829 return;
8830 }
8831
8832 /*
8833 * Call kvm_x86_ops dirty logging hooks when they are valid.
8834 *
8835 * kvm_x86_ops->slot_disable_log_dirty is called when:
8836 *
8837 * - KVM_MR_CREATE with dirty logging is disabled
8838 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8839 *
8840 * The reason is, in case of PML, we need to set D-bit for any slots
8841 * with dirty logging disabled in order to eliminate unnecessary GPA
8842 * logging in PML buffer (and potential PML buffer full VMEXT). This
8843 * guarantees leaving PML enabled during guest's lifetime won't have
8844 * any additonal overhead from PML when guest is running with dirty
8845 * logging disabled for memory slots.
8846 *
8847 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8848 * to dirty logging mode.
8849 *
8850 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8851 *
8852 * In case of write protect:
8853 *
8854 * Write protect all pages for dirty logging.
8855 *
8856 * All the sptes including the large sptes which point to this
8857 * slot are set to readonly. We can not create any new large
8858 * spte on this slot until the end of the logging.
8859 *
8860 * See the comments in fast_page_fault().
8861 */
8862 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8863 if (kvm_x86_ops->slot_enable_log_dirty)
8864 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8865 else
8866 kvm_mmu_slot_remove_write_access(kvm, new);
8867 } else {
8868 if (kvm_x86_ops->slot_disable_log_dirty)
8869 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8870 }
8871}
8872
f7784b8e 8873void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8874 const struct kvm_userspace_memory_region *mem,
8482644a 8875 const struct kvm_memory_slot *old,
f36f3f28 8876 const struct kvm_memory_slot *new,
8482644a 8877 enum kvm_mr_change change)
f7784b8e 8878{
8482644a 8879 int nr_mmu_pages = 0;
f7784b8e 8880
48c0e4e9
XG		 8881 if (!kvm->arch.n_requested_mmu_pages)
8882 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8883
48c0e4e9 8884 if (nr_mmu_pages)
0de10343 8885 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8886
3ea3b7fa
WL		 8887 /*
8888 * Dirty logging tracks sptes in 4k granularity, meaning that large
8889 * sptes have to be split. If live migration is successful, the guest
8890 * in the source machine will be destroyed and large sptes will be
8891 * created in the destination. However, if the guest continues to run
8892 * in the source machine (for example if live migration fails), small
8893 * sptes will remain around and cause bad performance.
8894 *
8895 * Scan sptes if dirty logging has been stopped, dropping those
8896 * which can be collapsed into a single large-page spte. Later
8897 * page faults will create the large-page sptes.
8898 */
8899 if ((change != KVM_MR_DELETE) &&
8900 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8901 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8902 kvm_mmu_zap_collapsible_sptes(kvm, new);
8903
c972f3b1 8904 /*
88178fd4 8905 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8906 *
88178fd4
KH		 8907 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8908 * been zapped so no dirty logging staff is needed for old slot. For
8909 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8910 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8911 *
8912 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8913 */
88178fd4 8914 if (change != KVM_MR_DELETE)
f36f3f28 8915 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8916}
1d737c8a 8917
2df72e9b 8918void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8919{
6ca18b69 8920 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8921}
8922
2df72e9b
MT		 8923void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8924 struct kvm_memory_slot *slot)
8925{
ae7cd873 8926 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8927}
8928
5d9bc648
PB		 8929static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8930{
8931 if (!list_empty_careful(&vcpu->async_pf.done))
8932 return true;
8933
8934 if (kvm_apic_has_events(vcpu))
8935 return true;
8936
8937 if (vcpu->arch.pv.pv_unhalted)
8938 return true;
8939
a5f01f8e
WL		 8940 if (vcpu->arch.exception.pending)
8941 return true;
8942
47a66eed
Z		 8943 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8944 (vcpu->arch.nmi_pending &&
8945 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 8946 return true;
8947
47a66eed
Z		 8948 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8949 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 8950 return true;
8951
5d9bc648
PB		 8952 if (kvm_arch_interrupt_allowed(vcpu) &&
8953 kvm_cpu_has_interrupt(vcpu))
8954 return true;
8955
1f4b34f8
AS		 8956 if (kvm_hv_has_stimer_pending(vcpu))
8957 return true;
8958
5d9bc648
PB		 8959 return false;
8960}
8961
1d737c8a
ZX		 8962int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8963{
5d9bc648 8964 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8965}
5736199a 8966
199b5763
LM		 8967bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
8968{
de63ad4c 8969 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 8970}
8971
b6d33834 8972int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8973{
b6d33834 8974 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8975}
78646121
GN		 8976
8977int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8978{
8979 return kvm_x86_ops->interrupt_allowed(vcpu);
8980}
229456fc 8981
82b32774 8982unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8983{
82b32774
NA		 8984 if (is_64_bit_mode(vcpu))
8985 return kvm_rip_read(vcpu);
8986 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8987 kvm_rip_read(vcpu));
8988}
8989EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8990
82b32774
NA		 8991bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8992{
8993 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8994}
8995EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8996
94fe45da
JK		 8997unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8998{
8999 unsigned long rflags;
9000
9001 rflags = kvm_x86_ops->get_rflags(vcpu);
9002 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 9003 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 9004 return rflags;
9005}
9006EXPORT_SYMBOL_GPL(kvm_get_rflags);
9007
6addfc42 9008static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 9009{
9010 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 9011 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 9012 rflags |= X86_EFLAGS_TF;
94fe45da 9013 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 9014}
9015
9016void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9017{
9018 __kvm_set_rflags(vcpu, rflags);
3842d135 9019 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 9020}
9021EXPORT_SYMBOL_GPL(kvm_set_rflags);
9022
56028d08
GN		 9023void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9024{
9025 int r;
9026
fb67e14f 9027 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 9028 work->wakeup_all)
56028d08
GN		 9029 return;
9030
9031 r = kvm_mmu_reload(vcpu);
9032 if (unlikely(r))
9033 return;
9034
fb67e14f
XG		 9035 if (!vcpu->arch.mmu.direct_map &&
9036 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
9037 return;
9038
56028d08
GN		 9039 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
9040}
9041
af585b92
GN		 9042static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9043{
9044 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9045}
9046
9047static inline u32 kvm_async_pf_next_probe(u32 key)
9048{
9049 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9050}
9051
9052static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9053{
9054 u32 key = kvm_async_pf_hash_fn(gfn);
9055
9056 while (vcpu->arch.apf.gfns[key] != ~0)
9057 key = kvm_async_pf_next_probe(key);
9058
9059 vcpu->arch.apf.gfns[key] = gfn;
9060}
9061
9062static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9063{
9064 int i;
9065 u32 key = kvm_async_pf_hash_fn(gfn);
9066
9067 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9068 (vcpu->arch.apf.gfns[key] != gfn &&
9069 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9070 key = kvm_async_pf_next_probe(key);
9071
9072 return key;
9073}
9074
9075bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9076{
9077 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9078}
9079
9080static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9081{
9082 u32 i, j, k;
9083
9084 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9085 while (true) {
9086 vcpu->arch.apf.gfns[i] = ~0;
9087 do {
9088 j = kvm_async_pf_next_probe(j);
9089 if (vcpu->arch.apf.gfns[j] == ~0)
9090 return;
9091 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9092 /*
9093 * k lies cyclically in ]i,j]
9094 * | i.k.j |
9095 * |....j i.k.| or |.k..j i...|
9096 */
9097 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9098 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9099 i = j;
9100 }
9101}
9102
7c90705b
GN		 9103static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9104{
4e335d9e
PB		 9105
9106 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9107 sizeof(val));
7c90705b
GN		 9108}
9109
9a6e7c39
WL		 9110static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9111{
9112
9113 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9114 sizeof(u32));
9115}
9116
af585b92
GN		 9117void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9118 struct kvm_async_pf *work)
9119{
6389ee94
AK		 9120 struct x86_exception fault;
9121
7c90705b 9122 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 9123 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 9124
9125 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 9126 (vcpu->arch.apf.send_user_only &&
9127 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 9128 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9129 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 9130 fault.vector = PF_VECTOR;
9131 fault.error_code_valid = true;
9132 fault.error_code = 0;
9133 fault.nested_page_fault = false;
9134 fault.address = work->arch.token;
adfe20fb 9135 fault.async_page_fault = true;
6389ee94 9136 kvm_inject_page_fault(vcpu, &fault);
7c90705b 9137 }
af585b92
GN		 9138}
9139
9140void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9141 struct kvm_async_pf *work)
9142{
6389ee94 9143 struct x86_exception fault;
9a6e7c39 9144 u32 val;
6389ee94 9145
f2e10669 9146 if (work->wakeup_all)
7c90705b
GN		 9147 work->arch.token = ~0; /* broadcast wakeup */
9148 else
9149 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 9150 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 9151
9a6e7c39
WL		 9152 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9153 !apf_get_user(vcpu, &val)) {
9154 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9155 vcpu->arch.exception.pending &&
9156 vcpu->arch.exception.nr == PF_VECTOR &&
9157 !apf_put_user(vcpu, 0)) {
9158 vcpu->arch.exception.injected = false;
9159 vcpu->arch.exception.pending = false;
9160 vcpu->arch.exception.nr = 0;
9161 vcpu->arch.exception.has_error_code = false;
9162 vcpu->arch.exception.error_code = 0;
9163 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9164 fault.vector = PF_VECTOR;
9165 fault.error_code_valid = true;
9166 fault.error_code = 0;
9167 fault.nested_page_fault = false;
9168 fault.address = work->arch.token;
9169 fault.async_page_fault = true;
9170 kvm_inject_page_fault(vcpu, &fault);
9171 }
7c90705b 9172 }
e6d53e3b 9173 vcpu->arch.apf.halted = false;
a4fa1635 9174 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 9175}
9176
9177bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9178{
9179 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9180 return true;
9181 else
9bc1f09f 9182 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 9183}
9184
5544eb9b
PB		 9185void kvm_arch_start_assignment(struct kvm *kvm)
9186{
9187 atomic_inc(&kvm->arch.assigned_device_count);
9188}
9189EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9190
9191void kvm_arch_end_assignment(struct kvm *kvm)
9192{
9193 atomic_dec(&kvm->arch.assigned_device_count);
9194}
9195EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9196
9197bool kvm_arch_has_assigned_device(struct kvm *kvm)
9198{
9199 return atomic_read(&kvm->arch.assigned_device_count);
9200}
9201EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9202
e0f0bbc5
AW		 9203void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9204{
9205 atomic_inc(&kvm->arch.noncoherent_dma_count);
9206}
9207EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9208
9209void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9210{
9211 atomic_dec(&kvm->arch.noncoherent_dma_count);
9212}
9213EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9214
9215bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9216{
9217 return atomic_read(&kvm->arch.noncoherent_dma_count);
9218}
9219EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9220
14717e20
AW		 9221bool kvm_arch_has_irq_bypass(void)
9222{
9223 return kvm_x86_ops->update_pi_irte != NULL;
9224}
9225
87276880
FW		 9226int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9227 struct irq_bypass_producer *prod)
9228{
9229 struct kvm_kernel_irqfd *irqfd =
9230 container_of(cons, struct kvm_kernel_irqfd, consumer);
9231
14717e20 9232 irqfd->producer = prod;
87276880 9233
14717e20
AW		 9234 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9235 prod->irq, irqfd->gsi, 1);
87276880
FW		 9236}
9237
9238void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9239 struct irq_bypass_producer *prod)
9240{
9241 int ret;
9242 struct kvm_kernel_irqfd *irqfd =
9243 container_of(cons, struct kvm_kernel_irqfd, consumer);
9244
87276880
FW		 9245 WARN_ON(irqfd->producer != prod);
9246 irqfd->producer = NULL;
9247
9248 /*
9249 * When producer of consumer is unregistered, we change back to
9250 * remapped mode, so we can re-use the current implementation
bb3541f1 9251 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 9252 * int this case doesn't want to receive the interrupts.
9253 */
9254 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9255 if (ret)
9256 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9257 " fails: %d\n", irqfd->consumer.token, ret);
9258}
9259
9260int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9261 uint32_t guest_irq, bool set)
9262{
9263 if (!kvm_x86_ops->update_pi_irte)
9264 return -EINVAL;
9265
9266 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9267}
9268
52004014
FW		 9269bool kvm_vector_hashing_enabled(void)
9270{
9271 return vector_hashing;
9272}
9273EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9274
229456fc 9275EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 9276EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 9277EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9278EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9279EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9280EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 9281EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 9282EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 9283EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 9284EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 9285EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 9286EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 9287EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 9288EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 9289EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 9290EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 9291EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 9292EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9293EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
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