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KVM: x86: Update the exit_qualification access bits while walking an address
[mirror_ubuntu-jammy-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
b0c39dc6 70#include <asm/mshyperv.h>
0092e434 71#include <asm/hypervisor.h>
043405e1 72
d1898b73
DH		 73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
313a3dc7 76#define MAX_IO_MSRS 256
890ca9ae 77#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 80
0f65dd70
AK		 81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
50a37eb4
JR		 84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
1260edbe
LJ		 89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 91#else
1260edbe 92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 93#endif
313a3dc7 94
ba1389b7
AK		 95#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 97
c519265f
RK		 98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 100
cb142eb7 101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 102static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 103static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 105static void store_regs(struct kvm_vcpu *vcpu);
106static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 107
893590c7 108struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 109EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 110
893590c7 111static bool __read_mostly ignore_msrs = 0;
476bc001 112module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 113
fab0aa3b
EM		 114static bool __read_mostly report_ignored_msrs = true;
115module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
116
9ed96e87
MT		 117unsigned int min_timer_period_us = 500;
118module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
119
630994b3
MT		 120static bool __read_mostly kvmclock_periodic_sync = true;
121module_param(kvmclock_periodic_sync, bool, S_IRUGO);
122
893590c7 123bool __read_mostly kvm_has_tsc_control;
92a1f12d 124EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 125u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 126EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 127u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129u64 __read_mostly kvm_max_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 131u64 __read_mostly kvm_default_tsc_scaling_ratio;
132EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 133
cc578287 134/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 135static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 136module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
137
d0659d94 138/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 139unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 140module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
141
52004014
FW		 142static bool __read_mostly vector_hashing = true;
143module_param(vector_hashing, bool, S_IRUGO);
144
18863bdd
AK		 145#define KVM_NR_SHARED_MSRS 16
146
147struct kvm_shared_msrs_global {
148 int nr;
2bf78fa7 149 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 150};
151
152struct kvm_shared_msrs {
153 struct user_return_notifier urn;
154 bool registered;
2bf78fa7
SY		 155 struct kvm_shared_msr_values {
156 u64 host;
157 u64 curr;
158 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 159};
160
161static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 162static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 163
417bc304 164struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 165 { "pf_fixed", VCPU_STAT(pf_fixed) },
166 { "pf_guest", VCPU_STAT(pf_guest) },
167 { "tlb_flush", VCPU_STAT(tlb_flush) },
168 { "invlpg", VCPU_STAT(invlpg) },
169 { "exits", VCPU_STAT(exits) },
170 { "io_exits", VCPU_STAT(io_exits) },
171 { "mmio_exits", VCPU_STAT(mmio_exits) },
172 { "signal_exits", VCPU_STAT(signal_exits) },
173 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 174 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 175 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 176 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 177 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 178 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 179 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 180 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 181 { "request_irq", VCPU_STAT(request_irq_exits) },
182 { "irq_exits", VCPU_STAT(irq_exits) },
183 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 184 { "fpu_reload", VCPU_STAT(fpu_reload) },
185 { "insn_emulation", VCPU_STAT(insn_emulation) },
186 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 187 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 188 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 189 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 190 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
191 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
192 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
193 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
194 { "mmu_flooded", VM_STAT(mmu_flooded) },
195 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 196 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 197 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 198 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 199 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 200 { "max_mmu_page_hash_collisions",
201 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 202 { NULL }
203};
204
2acf923e
DC		 205u64 __read_mostly host_xcr0;
206
b6785def 207static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 208
af585b92
GN		 209static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
210{
211 int i;
212 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
213 vcpu->arch.apf.gfns[i] = ~0;
214}
215
18863bdd
AK		 216static void kvm_on_user_return(struct user_return_notifier *urn)
217{
218 unsigned slot;
18863bdd
AK		 219 struct kvm_shared_msrs *locals
220 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 221 struct kvm_shared_msr_values *values;
1650b4eb
IA		 222 unsigned long flags;
223
224 /*
225 * Disabling irqs at this point since the following code could be
226 * interrupted and executed through kvm_arch_hardware_disable()
227 */
228 local_irq_save(flags);
229 if (locals->registered) {
230 locals->registered = false;
231 user_return_notifier_unregister(urn);
232 }
233 local_irq_restore(flags);
18863bdd 234 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 235 values = &locals->values[slot];
236 if (values->host != values->curr) {
237 wrmsrl(shared_msrs_global.msrs[slot], values->host);
238 values->curr = values->host;
18863bdd
AK		 239 }
240 }
18863bdd
AK		 241}
242
2bf78fa7 243static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 244{
18863bdd 245 u64 value;
013f6a5d
MT		 246 unsigned int cpu = smp_processor_id();
247 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 248
2bf78fa7
SY		 249 /* only read, and nobody should modify it at this time,
250 * so don't need lock */
251 if (slot >= shared_msrs_global.nr) {
252 printk(KERN_ERR "kvm: invalid MSR slot!");
253 return;
254 }
255 rdmsrl_safe(msr, &value);
256 smsr->values[slot].host = value;
257 smsr->values[slot].curr = value;
258}
259
260void kvm_define_shared_msr(unsigned slot, u32 msr)
261{
0123be42 262 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 263 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 264 if (slot >= shared_msrs_global.nr)
265 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 266}
267EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
268
269static void kvm_shared_msr_cpu_online(void)
270{
271 unsigned i;
18863bdd
AK		 272
273 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 274 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 275}
276
8b3c3104 277int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 278{
013f6a5d
MT		 279 unsigned int cpu = smp_processor_id();
280 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 281 int err;
18863bdd 282
2bf78fa7 283 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 284 return 0;
2bf78fa7 285 smsr->values[slot].curr = value;
8b3c3104
AH		 286 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
287 if (err)
288 return 1;
289
18863bdd
AK		 290 if (!smsr->registered) {
291 smsr->urn.on_user_return = kvm_on_user_return;
292 user_return_notifier_register(&smsr->urn);
293 smsr->registered = true;
294 }
8b3c3104 295 return 0;
18863bdd
AK		 296}
297EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
298
13a34e06 299static void drop_user_return_notifiers(void)
3548bab5 300{
013f6a5d
MT		 301 unsigned int cpu = smp_processor_id();
302 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 303
304 if (smsr->registered)
305 kvm_on_user_return(&smsr->urn);
306}
307
6866b83e
CO		 308u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
309{
8a5a87d9 310 return vcpu->arch.apic_base;
6866b83e
CO		 311}
312EXPORT_SYMBOL_GPL(kvm_get_apic_base);
313
58cb628d
JK		 314int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
315{
316 u64 old_state = vcpu->arch.apic_base &
317 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
318 u64 new_state = msr_info->data &
319 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
d6321d49
RK		 320 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
321 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 322
d3802286
JM		 323 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
324 return 1;
58cb628d 325 if (!msr_info->host_initiated &&
d3802286 326 ((new_state == MSR_IA32_APICBASE_ENABLE &&
58cb628d
JK		 327 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
328 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
329 old_state == 0)))
330 return 1;
331
332 kvm_lapic_set_base(vcpu, msr_info->data);
333 return 0;
6866b83e
CO		 334}
335EXPORT_SYMBOL_GPL(kvm_set_apic_base);
336
2605fc21 337asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 338{
339 /* Fault while not rebooting. We want the trace. */
340 BUG();
341}
342EXPORT_SYMBOL_GPL(kvm_spurious_fault);
343
3fd28fce
ED		 344#define EXCPT_BENIGN 0
345#define EXCPT_CONTRIBUTORY 1
346#define EXCPT_PF 2
347
348static int exception_class(int vector)
349{
350 switch (vector) {
351 case PF_VECTOR:
352 return EXCPT_PF;
353 case DE_VECTOR:
354 case TS_VECTOR:
355 case NP_VECTOR:
356 case SS_VECTOR:
357 case GP_VECTOR:
358 return EXCPT_CONTRIBUTORY;
359 default:
360 break;
361 }
362 return EXCPT_BENIGN;
363}
364
d6e8c854
NA		 365#define EXCPT_FAULT 0
366#define EXCPT_TRAP 1
367#define EXCPT_ABORT 2
368#define EXCPT_INTERRUPT 3
369
370static int exception_type(int vector)
371{
372 unsigned int mask;
373
374 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
375 return EXCPT_INTERRUPT;
376
377 mask = 1 << vector;
378
379 /* #DB is trap, as instruction watchpoints are handled elsewhere */
380 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
381 return EXCPT_TRAP;
382
383 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
384 return EXCPT_ABORT;
385
386 /* Reserved exceptions will result in fault */
387 return EXCPT_FAULT;
388}
389
3fd28fce 390static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 391 unsigned nr, bool has_error, u32 error_code,
392 bool reinject)
3fd28fce
ED		 393{
394 u32 prev_nr;
395 int class1, class2;
396
3842d135
AK		 397 kvm_make_request(KVM_REQ_EVENT, vcpu);
398
664f8e26 399 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 400 queue:
3ffb2468
NA		 401 if (has_error && !is_protmode(vcpu))
402 has_error = false;
664f8e26
WL		 403 if (reinject) {
404 /*
405 * On vmentry, vcpu->arch.exception.pending is only
406 * true if an event injection was blocked by
407 * nested_run_pending. In that case, however,
408 * vcpu_enter_guest requests an immediate exit,
409 * and the guest shouldn't proceed far enough to
410 * need reinjection.
411 */
412 WARN_ON_ONCE(vcpu->arch.exception.pending);
413 vcpu->arch.exception.injected = true;
414 } else {
415 vcpu->arch.exception.pending = true;
416 vcpu->arch.exception.injected = false;
417 }
3fd28fce
ED		 418 vcpu->arch.exception.has_error_code = has_error;
419 vcpu->arch.exception.nr = nr;
420 vcpu->arch.exception.error_code = error_code;
421 return;
422 }
423
424 /* to check exception */
425 prev_nr = vcpu->arch.exception.nr;
426 if (prev_nr == DF_VECTOR) {
427 /* triple fault -> shutdown */
a8eeb04a 428 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 429 return;
430 }
431 class1 = exception_class(prev_nr);
432 class2 = exception_class(nr);
433 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
434 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 435 /*
436 * Generate double fault per SDM Table 5-5. Set
437 * exception.pending = true so that the double fault
438 * can trigger a nested vmexit.
439 */
3fd28fce 440 vcpu->arch.exception.pending = true;
664f8e26 441 vcpu->arch.exception.injected = false;
3fd28fce
ED		 442 vcpu->arch.exception.has_error_code = true;
443 vcpu->arch.exception.nr = DF_VECTOR;
444 vcpu->arch.exception.error_code = 0;
445 } else
446 /* replace previous exception with a new one in a hope
447 that instruction re-execution will regenerate lost
448 exception */
449 goto queue;
450}
451
298101da
AK		 452void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
453{
ce7ddec4 454 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 455}
456EXPORT_SYMBOL_GPL(kvm_queue_exception);
457
ce7ddec4
JR		 458void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
459{
460 kvm_multiple_exception(vcpu, nr, false, 0, true);
461}
462EXPORT_SYMBOL_GPL(kvm_requeue_exception);
463
6affcbed 464int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 465{
db8fcefa
AP		 466 if (err)
467 kvm_inject_gp(vcpu, 0);
468 else
6affcbed
KH		 469 return kvm_skip_emulated_instruction(vcpu);
470
471 return 1;
db8fcefa
AP		 472}
473EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 474
6389ee94 475void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 476{
477 ++vcpu->stat.pf_guest;
adfe20fb
WL		 478 vcpu->arch.exception.nested_apf =
479 is_guest_mode(vcpu) && fault->async_page_fault;
480 if (vcpu->arch.exception.nested_apf)
481 vcpu->arch.apf.nested_apf_token = fault->address;
482 else
483 vcpu->arch.cr2 = fault->address;
6389ee94 484 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 485}
27d6c865 486EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 487
ef54bcfe 488static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 489{
6389ee94
AK		 490 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
491 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 492 else
6389ee94 493 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 494
495 return fault->nested_page_fault;
d4f8cf66
JR		 496}
497
3419ffc8
SY		 498void kvm_inject_nmi(struct kvm_vcpu *vcpu)
499{
7460fb4a
AK		 500 atomic_inc(&vcpu->arch.nmi_queued);
501 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 502}
503EXPORT_SYMBOL_GPL(kvm_inject_nmi);
504
298101da
AK		 505void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
506{
ce7ddec4 507 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 508}
509EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
510
ce7ddec4
JR		 511void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
512{
513 kvm_multiple_exception(vcpu, nr, true, error_code, true);
514}
515EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
516
0a79b009
AK		 517/*
518 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
519 * a #GP and return false.
520 */
521bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 522{
0a79b009
AK		 523 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
524 return true;
525 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
526 return false;
298101da 527}
0a79b009 528EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 529
16f8a6f9
NA		 530bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
531{
532 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
533 return true;
534
535 kvm_queue_exception(vcpu, UD_VECTOR);
536 return false;
537}
538EXPORT_SYMBOL_GPL(kvm_require_dr);
539
ec92fe44
JR		 540/*
541 * This function will be used to read from the physical memory of the currently
54bf36aa 542 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 543 * can read from guest physical or from the guest's guest physical memory.
544 */
545int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
546 gfn_t ngfn, void *data, int offset, int len,
547 u32 access)
548{
54987b7a 549 struct x86_exception exception;
ec92fe44
JR		 550 gfn_t real_gfn;
551 gpa_t ngpa;
552
553 ngpa = gfn_to_gpa(ngfn);
54987b7a 554 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 555 if (real_gfn == UNMAPPED_GVA)
556 return -EFAULT;
557
558 real_gfn = gpa_to_gfn(real_gfn);
559
54bf36aa 560 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 561}
562EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
563
69b0049a 564static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 565 void *data, int offset, int len, u32 access)
566{
567 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
568 data, offset, len, access);
569}
570
a03490ed
CO		 571/*
572 * Load the pae pdptrs. Return true is they are all valid.
573 */
ff03a073 574int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 575{
576 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
577 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
578 int i;
579 int ret;
ff03a073 580 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 581
ff03a073
JR		 582 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
583 offset * sizeof(u64), sizeof(pdpte),
584 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 585 if (ret < 0) {
586 ret = 0;
587 goto out;
588 }
589 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 590 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 591 (pdpte[i] &
592 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 593 ret = 0;
594 goto out;
595 }
596 }
597 ret = 1;
598
ff03a073 599 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 600 __set_bit(VCPU_EXREG_PDPTR,
601 (unsigned long *)&vcpu->arch.regs_avail);
602 __set_bit(VCPU_EXREG_PDPTR,
603 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 604out:
a03490ed
CO		 605
606 return ret;
607}
cc4b6871 608EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 609
9ed38ffa 610bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 611{
ff03a073 612 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 613 bool changed = true;
3d06b8bf
JR		 614 int offset;
615 gfn_t gfn;
d835dfec
AK		 616 int r;
617
618 if (is_long_mode(vcpu) || !is_pae(vcpu))
619 return false;
620
6de4f3ad
AK		 621 if (!test_bit(VCPU_EXREG_PDPTR,
622 (unsigned long *)&vcpu->arch.regs_avail))
623 return true;
624
a512177e
PB		 625 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
626 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 627 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
628 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 629 if (r < 0)
630 goto out;
ff03a073 631 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 632out:
d835dfec
AK		 633
634 return changed;
635}
9ed38ffa 636EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 637
49a9b07e 638int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 639{
aad82703 640 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 641 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 642
f9a48e6a
AK		 643 cr0 |= X86_CR0_ET;
644
ab344828 645#ifdef CONFIG_X86_64
0f12244f
GN		 646 if (cr0 & 0xffffffff00000000UL)
647 return 1;
ab344828
GN		 648#endif
649
650 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 651
0f12244f
GN		 652 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
653 return 1;
a03490ed 654
0f12244f
GN		 655 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
656 return 1;
a03490ed
CO		 657
658 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
659#ifdef CONFIG_X86_64
f6801dff 660 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 661 int cs_db, cs_l;
662
0f12244f
GN		 663 if (!is_pae(vcpu))
664 return 1;
a03490ed 665 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 666 if (cs_l)
667 return 1;
a03490ed
CO		 668 } else
669#endif
ff03a073 670 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 671 kvm_read_cr3(vcpu)))
0f12244f 672 return 1;
a03490ed
CO		 673 }
674
ad756a16
MJ		 675 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
676 return 1;
677
a03490ed 678 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 679
d170c419 680 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 681 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 682 kvm_async_pf_hash_reset(vcpu);
683 }
e5f3f027 684
aad82703
SY		 685 if ((cr0 ^ old_cr0) & update_bits)
686 kvm_mmu_reset_context(vcpu);
b18d5431 687
879ae188
LE		 688 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
689 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
690 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 691 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
692
0f12244f
GN		 693 return 0;
694}
2d3ad1f4 695EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 696
2d3ad1f4 697void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 698{
49a9b07e 699 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 700}
2d3ad1f4 701EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 702
42bdf991
MT		 703static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
704{
705 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
706 !vcpu->guest_xcr0_loaded) {
707 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 708 if (vcpu->arch.xcr0 != host_xcr0)
709 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 710 vcpu->guest_xcr0_loaded = 1;
711 }
712}
713
714static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
715{
716 if (vcpu->guest_xcr0_loaded) {
717 if (vcpu->arch.xcr0 != host_xcr0)
718 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
719 vcpu->guest_xcr0_loaded = 0;
720 }
721}
722
69b0049a 723static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 724{
56c103ec
LJ		 725 u64 xcr0 = xcr;
726 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 727 u64 valid_bits;
2acf923e
DC		 728
729 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
730 if (index != XCR_XFEATURE_ENABLED_MASK)
731 return 1;
d91cab78 732 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 733 return 1;
d91cab78 734 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 735 return 1;
46c34cb0
PB		 736
737 /*
738 * Do not allow the guest to set bits that we do not support
739 * saving. However, xcr0 bit 0 is always set, even if the
740 * emulated CPU does not support XSAVE (see fx_init).
741 */
d91cab78 742 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 743 if (xcr0 & ~valid_bits)
2acf923e 744 return 1;
46c34cb0 745
d91cab78
DH		 746 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
747 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 748 return 1;
749
d91cab78
DH		 750 if (xcr0 & XFEATURE_MASK_AVX512) {
751 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 752 return 1;
d91cab78 753 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 754 return 1;
755 }
2acf923e 756 vcpu->arch.xcr0 = xcr0;
56c103ec 757
d91cab78 758 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 759 kvm_update_cpuid(vcpu);
2acf923e
DC		 760 return 0;
761}
762
763int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
764{
764bcbc5
Z		 765 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
766 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 767 kvm_inject_gp(vcpu, 0);
768 return 1;
769 }
770 return 0;
771}
772EXPORT_SYMBOL_GPL(kvm_set_xcr);
773
a83b29c6 774int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 775{
fc78f519 776 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 777 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 778 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 779
0f12244f
GN		 780 if (cr4 & CR4_RESERVED_BITS)
781 return 1;
a03490ed 782
d6321d49 783 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 784 return 1;
785
d6321d49 786 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 787 return 1;
788
d6321d49 789 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 790 return 1;
791
d6321d49 792 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 793 return 1;
794
d6321d49 795 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 796 return 1;
797
fd8cb433 798 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 799 return 1;
800
ae3e61e1
PB		 801 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
802 return 1;
803
a03490ed 804 if (is_long_mode(vcpu)) {
0f12244f
GN		 805 if (!(cr4 & X86_CR4_PAE))
806 return 1;
a2edf57f
AK		 807 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
808 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 809 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
810 kvm_read_cr3(vcpu)))
0f12244f
GN		 811 return 1;
812
ad756a16 813 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 814 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 815 return 1;
816
817 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
818 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
819 return 1;
820 }
821
5e1746d6 822 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 823 return 1;
a03490ed 824
ad756a16
MJ		 825 if (((cr4 ^ old_cr4) & pdptr_bits) ||
826 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 827 kvm_mmu_reset_context(vcpu);
0f12244f 828
b9baba86 829 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 830 kvm_update_cpuid(vcpu);
2acf923e 831
0f12244f
GN		 832 return 0;
833}
2d3ad1f4 834EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 835
2390218b 836int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 837{
ac146235 838#ifdef CONFIG_X86_64
9d88fca7 839 cr3 &= ~CR3_PCID_INVD;
ac146235 840#endif
9d88fca7 841
9f8fe504 842 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 843 kvm_mmu_sync_roots(vcpu);
77c3913b 844 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 845 return 0;
d835dfec
AK		 846 }
847
d1cd3ce9
YZ		 848 if (is_long_mode(vcpu) &&
849 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62)))
850 return 1;
851 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 852 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 853 return 1;
a03490ed 854
0f12244f 855 vcpu->arch.cr3 = cr3;
aff48baa 856 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 857 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 858 return 0;
859}
2d3ad1f4 860EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 861
eea1cff9 862int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 863{
0f12244f
GN		 864 if (cr8 & CR8_RESERVED_BITS)
865 return 1;
35754c98 866 if (lapic_in_kernel(vcpu))
a03490ed
CO		 867 kvm_lapic_set_tpr(vcpu, cr8);
868 else
ad312c7c 869 vcpu->arch.cr8 = cr8;
0f12244f
GN		 870 return 0;
871}
2d3ad1f4 872EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 873
2d3ad1f4 874unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 875{
35754c98 876 if (lapic_in_kernel(vcpu))
a03490ed
CO		 877 return kvm_lapic_get_cr8(vcpu);
878 else
ad312c7c 879 return vcpu->arch.cr8;
a03490ed 880}
2d3ad1f4 881EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 882
ae561ede
NA		 883static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
884{
885 int i;
886
887 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
888 for (i = 0; i < KVM_NR_DB_REGS; i++)
889 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
890 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
891 }
892}
893
73aaf249
JK		 894static void kvm_update_dr6(struct kvm_vcpu *vcpu)
895{
896 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
897 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
898}
899
c8639010
JK		 900static void kvm_update_dr7(struct kvm_vcpu *vcpu)
901{
902 unsigned long dr7;
903
904 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
905 dr7 = vcpu->arch.guest_debug_dr7;
906 else
907 dr7 = vcpu->arch.dr7;
908 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 909 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
910 if (dr7 & DR7_BP_EN_MASK)
911 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 912}
913
6f43ed01
NA		 914static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
915{
916 u64 fixed = DR6_FIXED_1;
917
d6321d49 918 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 919 fixed |= DR6_RTM;
920 return fixed;
921}
922
338dbc97 923static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 924{
925 switch (dr) {
926 case 0 ... 3:
927 vcpu->arch.db[dr] = val;
928 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
929 vcpu->arch.eff_db[dr] = val;
930 break;
931 case 4:
020df079
GN		 932 /* fall through */
933 case 6:
338dbc97
GN		 934 if (val & 0xffffffff00000000ULL)
935 return -1; /* #GP */
6f43ed01 936 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 937 kvm_update_dr6(vcpu);
020df079
GN		 938 break;
939 case 5:
020df079
GN		 940 /* fall through */
941 default: /* 7 */
338dbc97
GN		 942 if (val & 0xffffffff00000000ULL)
943 return -1; /* #GP */
020df079 944 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 945 kvm_update_dr7(vcpu);
020df079
GN		 946 break;
947 }
948
949 return 0;
950}
338dbc97
GN		 951
952int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
953{
16f8a6f9 954 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 955 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 956 return 1;
957 }
958 return 0;
338dbc97 959}
020df079
GN		 960EXPORT_SYMBOL_GPL(kvm_set_dr);
961
16f8a6f9 962int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 963{
964 switch (dr) {
965 case 0 ... 3:
966 *val = vcpu->arch.db[dr];
967 break;
968 case 4:
020df079
GN		 969 /* fall through */
970 case 6:
73aaf249
JK		 971 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
972 *val = vcpu->arch.dr6;
973 else
974 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 975 break;
976 case 5:
020df079
GN		 977 /* fall through */
978 default: /* 7 */
979 *val = vcpu->arch.dr7;
980 break;
981 }
338dbc97
GN		 982 return 0;
983}
020df079
GN		 984EXPORT_SYMBOL_GPL(kvm_get_dr);
985
022cd0e8
AK		 986bool kvm_rdpmc(struct kvm_vcpu *vcpu)
987{
988 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
989 u64 data;
990 int err;
991
c6702c9d 992 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 993 if (err)
994 return err;
995 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
996 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
997 return err;
998}
999EXPORT_SYMBOL_GPL(kvm_rdpmc);
1000
043405e1
CO		 1001/*
1002 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1003 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1004 *
1005 * This list is modified at module load time to reflect the
e3267cbb 1006 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1007 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1008 * may depend on host virtualization features rather than host cpu features.
043405e1 1009 */
e3267cbb 1010
043405e1
CO		 1011static u32 msrs_to_save[] = {
1012 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1013 MSR_STAR,
043405e1
CO		 1014#ifdef CONFIG_X86_64
1015 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1016#endif
b3897a49 1017 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1018 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
d28b387f 1019 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
043405e1
CO		 1020};
1021
1022static unsigned num_msrs_to_save;
1023
62ef68bb
PB		 1024static u32 emulated_msrs[] = {
1025 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1026 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1027 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1028 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1029 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1030 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1031 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1032 HV_X64_MSR_RESET,
11c4b1ca 1033 HV_X64_MSR_VP_INDEX,
9eec50b8 1034 HV_X64_MSR_VP_RUNTIME,
5c919412 1035 HV_X64_MSR_SCONTROL,
1f4b34f8 1036 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 1037 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1038 MSR_KVM_PV_EOI_EN,
1039
ba904635 1040 MSR_IA32_TSC_ADJUST,
a3e06bbe 1041 MSR_IA32_TSCDEADLINE,
043405e1 1042 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1043 MSR_IA32_MCG_STATUS,
1044 MSR_IA32_MCG_CTL,
c45dcc71 1045 MSR_IA32_MCG_EXT_CTL,
64d60670 1046 MSR_IA32_SMBASE,
52797bf9 1047 MSR_SMI_COUNT,
db2336a8
KH		 1048 MSR_PLATFORM_INFO,
1049 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1050};
1051
62ef68bb
PB		 1052static unsigned num_emulated_msrs;
1053
801e459a
TL		 1054/*
1055 * List of msr numbers which are used to expose MSR-based features that
1056 * can be used by a hypervisor to validate requested CPU features.
1057 */
1058static u32 msr_based_features[] = {
1389309c
PB		 1059 MSR_IA32_VMX_BASIC,
1060 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1061 MSR_IA32_VMX_PINBASED_CTLS,
1062 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1063 MSR_IA32_VMX_PROCBASED_CTLS,
1064 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1065 MSR_IA32_VMX_EXIT_CTLS,
1066 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1067 MSR_IA32_VMX_ENTRY_CTLS,
1068 MSR_IA32_VMX_MISC,
1069 MSR_IA32_VMX_CR0_FIXED0,
1070 MSR_IA32_VMX_CR0_FIXED1,
1071 MSR_IA32_VMX_CR4_FIXED0,
1072 MSR_IA32_VMX_CR4_FIXED1,
1073 MSR_IA32_VMX_VMCS_ENUM,
1074 MSR_IA32_VMX_PROCBASED_CTLS2,
1075 MSR_IA32_VMX_EPT_VPID_CAP,
1076 MSR_IA32_VMX_VMFUNC,
1077
d1d93fa9 1078 MSR_F10H_DECFG,
518e7b94 1079 MSR_IA32_UCODE_REV,
801e459a
TL		 1080};
1081
1082static unsigned int num_msr_based_features;
1083
66421c1e
WL		 1084static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1085{
1086 switch (msr->index) {
518e7b94
WL		 1087 case MSR_IA32_UCODE_REV:
1088 rdmsrl(msr->index, msr->data);
1089 break;
66421c1e
WL		 1090 default:
1091 if (kvm_x86_ops->get_msr_feature(msr))
1092 return 1;
1093 }
1094 return 0;
1095}
1096
801e459a
TL		 1097static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1098{
1099 struct kvm_msr_entry msr;
66421c1e 1100 int r;
801e459a
TL		 1101
1102 msr.index = index;
66421c1e
WL		 1103 r = kvm_get_msr_feature(&msr);
1104 if (r)
1105 return r;
801e459a
TL		 1106
1107 *data = msr.data;
1108
1109 return 0;
1110}
1111
384bb783 1112bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1113{
b69e8cae 1114 if (efer & efer_reserved_bits)
384bb783 1115 return false;
15c4a640 1116
1b4d56b8 1117 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1118 return false;
1b2fd70c 1119
1b4d56b8 1120 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1121 return false;
d8017474 1122
384bb783
JK		 1123 return true;
1124}
1125EXPORT_SYMBOL_GPL(kvm_valid_efer);
1126
1127static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1128{
1129 u64 old_efer = vcpu->arch.efer;
1130
1131 if (!kvm_valid_efer(vcpu, efer))
1132 return 1;
1133
1134 if (is_paging(vcpu)
1135 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1136 return 1;
1137
15c4a640 1138 efer &= ~EFER_LMA;
f6801dff 1139 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1140
a3d204e2
SY		 1141 kvm_x86_ops->set_efer(vcpu, efer);
1142
aad82703
SY		 1143 /* Update reserved bits */
1144 if ((efer ^ old_efer) & EFER_NX)
1145 kvm_mmu_reset_context(vcpu);
1146
b69e8cae 1147 return 0;
15c4a640
CO		 1148}
1149
f2b4b7dd
JR		 1150void kvm_enable_efer_bits(u64 mask)
1151{
1152 efer_reserved_bits &= ~mask;
1153}
1154EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1155
15c4a640
CO		 1156/*
1157 * Writes msr value into into the appropriate "register".
1158 * Returns 0 on success, non-0 otherwise.
1159 * Assumes vcpu_load() was already called.
1160 */
8fe8ab46 1161int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1162{
854e8bb1
NA		 1163 switch (msr->index) {
1164 case MSR_FS_BASE:
1165 case MSR_GS_BASE:
1166 case MSR_KERNEL_GS_BASE:
1167 case MSR_CSTAR:
1168 case MSR_LSTAR:
fd8cb433 1169 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1170 return 1;
1171 break;
1172 case MSR_IA32_SYSENTER_EIP:
1173 case MSR_IA32_SYSENTER_ESP:
1174 /*
1175 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1176 * non-canonical address is written on Intel but not on
1177 * AMD (which ignores the top 32-bits, because it does
1178 * not implement 64-bit SYSENTER).
1179 *
1180 * 64-bit code should hence be able to write a non-canonical
1181 * value on AMD. Making the address canonical ensures that
1182 * vmentry does not fail on Intel after writing a non-canonical
1183 * value, and that something deterministic happens if the guest
1184 * invokes 64-bit SYSENTER.
1185 */
fd8cb433 1186 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1187 }
8fe8ab46 1188 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1189}
854e8bb1 1190EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1191
313a3dc7
CO		 1192/*
1193 * Adapt set_msr() to msr_io()'s calling convention
1194 */
609e36d3
PB		 1195static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1196{
1197 struct msr_data msr;
1198 int r;
1199
1200 msr.index = index;
1201 msr.host_initiated = true;
1202 r = kvm_get_msr(vcpu, &msr);
1203 if (r)
1204 return r;
1205
1206 *data = msr.data;
1207 return 0;
1208}
1209
313a3dc7
CO		 1210static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1211{
8fe8ab46
WA		 1212 struct msr_data msr;
1213
1214 msr.data = *data;
1215 msr.index = index;
1216 msr.host_initiated = true;
1217 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1218}
1219
16e8d74d
MT		 1220#ifdef CONFIG_X86_64
1221struct pvclock_gtod_data {
1222 seqcount_t seq;
1223
1224 struct { /* extract of a clocksource struct */
1225 int vclock_mode;
a5a1d1c2
TG		 1226 u64 cycle_last;
1227 u64 mask;
16e8d74d
MT		 1228 u32 mult;
1229 u32 shift;
1230 } clock;
1231
cbcf2dd3
TG		 1232 u64 boot_ns;
1233 u64 nsec_base;
55dd00a7 1234 u64 wall_time_sec;
16e8d74d
MT		 1235};
1236
1237static struct pvclock_gtod_data pvclock_gtod_data;
1238
1239static void update_pvclock_gtod(struct timekeeper *tk)
1240{
1241 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1242 u64 boot_ns;
1243
876e7881 1244 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1245
1246 write_seqcount_begin(&vdata->seq);
1247
1248 /* copy pvclock gtod data */
876e7881
PZ		 1249 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1250 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1251 vdata->clock.mask = tk->tkr_mono.mask;
1252 vdata->clock.mult = tk->tkr_mono.mult;
1253 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1254
cbcf2dd3 1255 vdata->boot_ns = boot_ns;
876e7881 1256 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1257
55dd00a7
MT		 1258 vdata->wall_time_sec = tk->xtime_sec;
1259
16e8d74d
MT		 1260 write_seqcount_end(&vdata->seq);
1261}
1262#endif
1263
bab5bb39
NK		 1264void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1265{
1266 /*
1267 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1268 * vcpu_enter_guest. This function is only called from
1269 * the physical CPU that is running vcpu.
1270 */
1271 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1272}
16e8d74d 1273
18068523
GOC		 1274static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1275{
9ed3c444
AK		 1276 int version;
1277 int r;
50d0a0f9 1278 struct pvclock_wall_clock wc;
87aeb54f 1279 struct timespec64 boot;
18068523
GOC		 1280
1281 if (!wall_clock)
1282 return;
1283
9ed3c444
AK		 1284 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1285 if (r)
1286 return;
1287
1288 if (version & 1)
1289 ++version; /* first time write, random junk */
1290
1291 ++version;
18068523 1292
1dab1345
NK		 1293 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1294 return;
18068523 1295
50d0a0f9
GH		 1296 /*
1297 * The guest calculates current wall clock time by adding
34c238a1 1298 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1299 * wall clock specified here. guest system time equals host
1300 * system time for us, thus we must fill in host boot time here.
1301 */
87aeb54f 1302 getboottime64(&boot);
50d0a0f9 1303
4b648665 1304 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1305 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1306 boot = timespec64_sub(boot, ts);
4b648665 1307 }
87aeb54f 1308 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1309 wc.nsec = boot.tv_nsec;
1310 wc.version = version;
18068523
GOC		 1311
1312 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1313
1314 version++;
1315 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1316}
1317
50d0a0f9
GH		 1318static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1319{
b51012de
PB		 1320 do_shl32_div32(dividend, divisor);
1321 return dividend;
50d0a0f9
GH		 1322}
1323
3ae13faa 1324static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1325 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1326{
5f4e3f88 1327 uint64_t scaled64;
50d0a0f9
GH		 1328 int32_t shift = 0;
1329 uint64_t tps64;
1330 uint32_t tps32;
1331
3ae13faa
PB		 1332 tps64 = base_hz;
1333 scaled64 = scaled_hz;
50933623 1334 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1335 tps64 >>= 1;
1336 shift--;
1337 }
1338
1339 tps32 = (uint32_t)tps64;
50933623
JK		 1340 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1341 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1342 scaled64 >>= 1;
1343 else
1344 tps32 <<= 1;
50d0a0f9
GH		 1345 shift++;
1346 }
1347
5f4e3f88
ZA		 1348 *pshift = shift;
1349 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1350
3ae13faa
PB		 1351 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1352 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1353}
1354
d828199e 1355#ifdef CONFIG_X86_64
16e8d74d 1356static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1357#endif
16e8d74d 1358
c8076604 1359static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1360static unsigned long max_tsc_khz;
c8076604 1361
cc578287 1362static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1363{
cc578287
ZA		 1364 u64 v = (u64)khz * (1000000 + ppm);
1365 do_div(v, 1000000);
1366 return v;
1e993611
JR		 1367}
1368
381d585c
HZ		 1369static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1370{
1371 u64 ratio;
1372
1373 /* Guest TSC same frequency as host TSC? */
1374 if (!scale) {
1375 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1376 return 0;
1377 }
1378
1379 /* TSC scaling supported? */
1380 if (!kvm_has_tsc_control) {
1381 if (user_tsc_khz > tsc_khz) {
1382 vcpu->arch.tsc_catchup = 1;
1383 vcpu->arch.tsc_always_catchup = 1;
1384 return 0;
1385 } else {
1386 WARN(1, "user requested TSC rate below hardware speed\n");
1387 return -1;
1388 }
1389 }
1390
1391 /* TSC scaling required - calculate ratio */
1392 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1393 user_tsc_khz, tsc_khz);
1394
1395 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1396 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1397 user_tsc_khz);
1398 return -1;
1399 }
1400
1401 vcpu->arch.tsc_scaling_ratio = ratio;
1402 return 0;
1403}
1404
4941b8cb 1405static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1406{
cc578287
ZA		 1407 u32 thresh_lo, thresh_hi;
1408 int use_scaling = 0;
217fc9cf 1409
03ba32ca 1410 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1411 if (user_tsc_khz == 0) {
ad721883
HZ		 1412 /* set tsc_scaling_ratio to a safe value */
1413 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1414 return -1;
ad721883 1415 }
03ba32ca 1416
c285545f 1417 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1418 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1419 &vcpu->arch.virtual_tsc_shift,
1420 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1421 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1422
1423 /*
1424 * Compute the variation in TSC rate which is acceptable
1425 * within the range of tolerance and decide if the
1426 * rate being applied is within that bounds of the hardware
1427 * rate. If so, no scaling or compensation need be done.
1428 */
1429 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1430 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1431 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1432 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1433 use_scaling = 1;
1434 }
4941b8cb 1435 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1436}
1437
1438static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1439{
e26101b1 1440 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1441 vcpu->arch.virtual_tsc_mult,
1442 vcpu->arch.virtual_tsc_shift);
e26101b1 1443 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1444 return tsc;
1445}
1446
b0c39dc6
VK		 1447static inline int gtod_is_based_on_tsc(int mode)
1448{
1449 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1450}
1451
69b0049a 1452static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1453{
1454#ifdef CONFIG_X86_64
1455 bool vcpus_matched;
b48aa97e
MT		 1456 struct kvm_arch *ka = &vcpu->kvm->arch;
1457 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1458
1459 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1460 atomic_read(&vcpu->kvm->online_vcpus));
1461
7f187922
MT		 1462 /*
1463 * Once the masterclock is enabled, always perform request in
1464 * order to update it.
1465 *
1466 * In order to enable masterclock, the host clocksource must be TSC
1467 * and the vcpus need to have matched TSCs. When that happens,
1468 * perform request to enable masterclock.
1469 */
1470 if (ka->use_master_clock ||
b0c39dc6 1471 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1472 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1473
1474 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1475 atomic_read(&vcpu->kvm->online_vcpus),
1476 ka->use_master_clock, gtod->clock.vclock_mode);
1477#endif
1478}
1479
ba904635
WA		 1480static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1481{
3e3f5026 1482 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1483 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1484}
1485
35181e86
HZ		 1486/*
1487 * Multiply tsc by a fixed point number represented by ratio.
1488 *
1489 * The most significant 64-N bits (mult) of ratio represent the
1490 * integral part of the fixed point number; the remaining N bits
1491 * (frac) represent the fractional part, ie. ratio represents a fixed
1492 * point number (mult + frac * 2^(-N)).
1493 *
1494 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1495 */
1496static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1497{
1498 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1499}
1500
1501u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1502{
1503 u64 _tsc = tsc;
1504 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1505
1506 if (ratio != kvm_default_tsc_scaling_ratio)
1507 _tsc = __scale_tsc(ratio, tsc);
1508
1509 return _tsc;
1510}
1511EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1512
07c1419a
HZ		 1513static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1514{
1515 u64 tsc;
1516
1517 tsc = kvm_scale_tsc(vcpu, rdtsc());
1518
1519 return target_tsc - tsc;
1520}
1521
4ba76538
HZ		 1522u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1523{
ea26e4ec 1524 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1525}
1526EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1527
a545ab6a
LC		 1528static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1529{
1530 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1531 vcpu->arch.tsc_offset = offset;
1532}
1533
b0c39dc6
VK		 1534static inline bool kvm_check_tsc_unstable(void)
1535{
1536#ifdef CONFIG_X86_64
1537 /*
1538 * TSC is marked unstable when we're running on Hyper-V,
1539 * 'TSC page' clocksource is good.
1540 */
1541 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1542 return false;
1543#endif
1544 return check_tsc_unstable();
1545}
1546
8fe8ab46 1547void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1548{
1549 struct kvm *kvm = vcpu->kvm;
f38e098f 1550 u64 offset, ns, elapsed;
99e3e30a 1551 unsigned long flags;
b48aa97e 1552 bool matched;
0d3da0d2 1553 bool already_matched;
8fe8ab46 1554 u64 data = msr->data;
c5e8ec8e 1555 bool synchronizing = false;
99e3e30a 1556
038f8c11 1557 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1558 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1559 ns = ktime_get_boot_ns();
f38e098f 1560 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1561
03ba32ca 1562 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1563 if (data == 0 && msr->host_initiated) {
1564 /*
1565 * detection of vcpu initialization -- need to sync
1566 * with other vCPUs. This particularly helps to keep
1567 * kvm_clock stable after CPU hotplug
1568 */
1569 synchronizing = true;
1570 } else {
1571 u64 tsc_exp = kvm->arch.last_tsc_write +
1572 nsec_to_cycles(vcpu, elapsed);
1573 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1574 /*
1575 * Special case: TSC write with a small delta (1 second)
1576 * of virtual cycle time against real time is
1577 * interpreted as an attempt to synchronize the CPU.
1578 */
1579 synchronizing = data < tsc_exp + tsc_hz &&
1580 data + tsc_hz > tsc_exp;
1581 }
c5e8ec8e 1582 }
f38e098f
ZA		 1583
1584 /*
5d3cb0f6
ZA		 1585 * For a reliable TSC, we can match TSC offsets, and for an unstable
1586 * TSC, we add elapsed time in this computation. We could let the
1587 * compensation code attempt to catch up if we fall behind, but
1588 * it's better to try to match offsets from the beginning.
1589 */
c5e8ec8e 1590 if (synchronizing &&
5d3cb0f6 1591 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1592 if (!kvm_check_tsc_unstable()) {
e26101b1 1593 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1594 pr_debug("kvm: matched tsc offset for %llu\n", data);
1595 } else {
857e4099 1596 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1597 data += delta;
07c1419a 1598 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1599 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1600 }
b48aa97e 1601 matched = true;
0d3da0d2 1602 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1603 } else {
1604 /*
1605 * We split periods of matched TSC writes into generations.
1606 * For each generation, we track the original measured
1607 * nanosecond time, offset, and write, so if TSCs are in
1608 * sync, we can match exact offset, and if not, we can match
4a969980 1609 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1610 *
1611 * These values are tracked in kvm->arch.cur_xxx variables.
1612 */
1613 kvm->arch.cur_tsc_generation++;
1614 kvm->arch.cur_tsc_nsec = ns;
1615 kvm->arch.cur_tsc_write = data;
1616 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1617 matched = false;
0d3da0d2 1618 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1619 kvm->arch.cur_tsc_generation, data);
f38e098f 1620 }
e26101b1
ZA		 1621
1622 /*
1623 * We also track th most recent recorded KHZ, write and time to
1624 * allow the matching interval to be extended at each write.
1625 */
f38e098f
ZA		 1626 kvm->arch.last_tsc_nsec = ns;
1627 kvm->arch.last_tsc_write = data;
5d3cb0f6 1628 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1629
b183aa58 1630 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1631
1632 /* Keep track of which generation this VCPU has synchronized to */
1633 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1634 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1635 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1636
d6321d49 1637 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1638 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1639
a545ab6a 1640 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1641 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1642
1643 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1644 if (!matched) {
b48aa97e 1645 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1646 } else if (!already_matched) {
1647 kvm->arch.nr_vcpus_matched_tsc++;
1648 }
b48aa97e
MT		 1649
1650 kvm_track_tsc_matching(vcpu);
1651 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1652}
e26101b1 1653
99e3e30a
ZA		 1654EXPORT_SYMBOL_GPL(kvm_write_tsc);
1655
58ea6767
HZ		 1656static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1657 s64 adjustment)
1658{
ea26e4ec 1659 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1660}
1661
1662static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1663{
1664 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1665 WARN_ON(adjustment < 0);
1666 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1667 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1668}
1669
d828199e
MT		 1670#ifdef CONFIG_X86_64
1671
a5a1d1c2 1672static u64 read_tsc(void)
d828199e 1673{
a5a1d1c2 1674 u64 ret = (u64)rdtsc_ordered();
03b9730b 1675 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1676
1677 if (likely(ret >= last))
1678 return ret;
1679
1680 /*
1681 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1682 * predictable (it's just a function of time and the likely is
d828199e
MT		 1683 * very likely) and there's a data dependence, so force GCC
1684 * to generate a branch instead. I don't barrier() because
1685 * we don't actually need a barrier, and if this function
1686 * ever gets inlined it will generate worse code.
1687 */
1688 asm volatile ("");
1689 return last;
1690}
1691
b0c39dc6 1692static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1693{
1694 long v;
1695 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1696 u64 tsc_pg_val;
1697
1698 switch (gtod->clock.vclock_mode) {
1699 case VCLOCK_HVCLOCK:
1700 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1701 tsc_timestamp);
1702 if (tsc_pg_val != U64_MAX) {
1703 /* TSC page valid */
1704 *mode = VCLOCK_HVCLOCK;
1705 v = (tsc_pg_val - gtod->clock.cycle_last) &
1706 gtod->clock.mask;
1707 } else {
1708 /* TSC page invalid */
1709 *mode = VCLOCK_NONE;
1710 }
1711 break;
1712 case VCLOCK_TSC:
1713 *mode = VCLOCK_TSC;
1714 *tsc_timestamp = read_tsc();
1715 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1716 gtod->clock.mask;
1717 break;
1718 default:
1719 *mode = VCLOCK_NONE;
1720 }
d828199e 1721
b0c39dc6
VK		 1722 if (*mode == VCLOCK_NONE)
1723 *tsc_timestamp = v = 0;
d828199e 1724
d828199e
MT		 1725 return v * gtod->clock.mult;
1726}
1727
b0c39dc6 1728static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1729{
cbcf2dd3 1730 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1731 unsigned long seq;
d828199e 1732 int mode;
cbcf2dd3 1733 u64 ns;
d828199e 1734
d828199e
MT		 1735 do {
1736 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1737 ns = gtod->nsec_base;
b0c39dc6 1738 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1739 ns >>= gtod->clock.shift;
cbcf2dd3 1740 ns += gtod->boot_ns;
d828199e 1741 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1742 *t = ns;
d828199e
MT		 1743
1744 return mode;
1745}
1746
b0c39dc6 1747static int do_realtime(struct timespec *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1748{
1749 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1750 unsigned long seq;
1751 int mode;
1752 u64 ns;
1753
1754 do {
1755 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1756 ts->tv_sec = gtod->wall_time_sec;
1757 ns = gtod->nsec_base;
b0c39dc6 1758 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1759 ns >>= gtod->clock.shift;
1760 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1761
1762 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1763 ts->tv_nsec = ns;
1764
1765 return mode;
1766}
1767
b0c39dc6
VK		 1768/* returns true if host is using TSC based clocksource */
1769static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1770{
d828199e 1771 /* checked again under seqlock below */
b0c39dc6 1772 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1773 return false;
1774
b0c39dc6
VK		 1775 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1776 tsc_timestamp));
d828199e 1777}
55dd00a7 1778
b0c39dc6 1779/* returns true if host is using TSC based clocksource */
55dd00a7 1780static bool kvm_get_walltime_and_clockread(struct timespec *ts,
b0c39dc6 1781 u64 *tsc_timestamp)
55dd00a7
MT		 1782{
1783 /* checked again under seqlock below */
b0c39dc6 1784 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1785 return false;
1786
b0c39dc6 1787 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1788}
d828199e
MT		 1789#endif
1790
1791/*
1792 *
b48aa97e
MT		 1793 * Assuming a stable TSC across physical CPUS, and a stable TSC
1794 * across virtual CPUs, the following condition is possible.
1795 * Each numbered line represents an event visible to both
d828199e
MT		 1796 * CPUs at the next numbered event.
1797 *
1798 * "timespecX" represents host monotonic time. "tscX" represents
1799 * RDTSC value.
1800 *
1801 * VCPU0 on CPU0 | VCPU1 on CPU1
1802 *
1803 * 1. read timespec0,tsc0
1804 * 2. | timespec1 = timespec0 + N
1805 * | tsc1 = tsc0 + M
1806 * 3. transition to guest | transition to guest
1807 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1808 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1809 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1810 *
1811 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1812 *
1813 * - ret0 < ret1
1814 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1815 * ...
1816 * - 0 < N - M => M < N
1817 *
1818 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1819 * always the case (the difference between two distinct xtime instances
1820 * might be smaller then the difference between corresponding TSC reads,
1821 * when updating guest vcpus pvclock areas).
1822 *
1823 * To avoid that problem, do not allow visibility of distinct
1824 * system_timestamp/tsc_timestamp values simultaneously: use a master
1825 * copy of host monotonic time values. Update that master copy
1826 * in lockstep.
1827 *
b48aa97e 1828 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1829 *
1830 */
1831
1832static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1833{
1834#ifdef CONFIG_X86_64
1835 struct kvm_arch *ka = &kvm->arch;
1836 int vclock_mode;
b48aa97e
MT		 1837 bool host_tsc_clocksource, vcpus_matched;
1838
1839 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1840 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1841
1842 /*
1843 * If the host uses TSC clock, then passthrough TSC as stable
1844 * to the guest.
1845 */
b48aa97e 1846 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1847 &ka->master_kernel_ns,
1848 &ka->master_cycle_now);
1849
16a96021 1850 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1851 && !ka->backwards_tsc_observed
54750f2c 1852 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1853
d828199e
MT		 1854 if (ka->use_master_clock)
1855 atomic_set(&kvm_guest_has_master_clock, 1);
1856
1857 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1858 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1859 vcpus_matched);
d828199e
MT		 1860#endif
1861}
1862
2860c4b1
PB		 1863void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1864{
1865 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1866}
1867
2e762ff7
MT		 1868static void kvm_gen_update_masterclock(struct kvm *kvm)
1869{
1870#ifdef CONFIG_X86_64
1871 int i;
1872 struct kvm_vcpu *vcpu;
1873 struct kvm_arch *ka = &kvm->arch;
1874
1875 spin_lock(&ka->pvclock_gtod_sync_lock);
1876 kvm_make_mclock_inprogress_request(kvm);
1877 /* no guest entries from this point */
1878 pvclock_update_vm_gtod_copy(kvm);
1879
1880 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1881 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1882
1883 /* guest entries allowed */
1884 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1885 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1886
1887 spin_unlock(&ka->pvclock_gtod_sync_lock);
1888#endif
1889}
1890
e891a32e 1891u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1892{
108b249c 1893 struct kvm_arch *ka = &kvm->arch;
8b953440 1894 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1895 u64 ret;
108b249c 1896
8b953440
PB		 1897 spin_lock(&ka->pvclock_gtod_sync_lock);
1898 if (!ka->use_master_clock) {
1899 spin_unlock(&ka->pvclock_gtod_sync_lock);
1900 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1901 }
1902
8b953440
PB		 1903 hv_clock.tsc_timestamp = ka->master_cycle_now;
1904 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1905 spin_unlock(&ka->pvclock_gtod_sync_lock);
1906
e2c2206a
WL		 1907 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1908 get_cpu();
1909
e70b57a6
WL		 1910 if (__this_cpu_read(cpu_tsc_khz)) {
1911 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1912 &hv_clock.tsc_shift,
1913 &hv_clock.tsc_to_system_mul);
1914 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1915 } else
1916 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 1917
1918 put_cpu();
1919
1920 return ret;
108b249c
PB		 1921}
1922
0d6dd2ff
PB		 1923static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1924{
1925 struct kvm_vcpu_arch *vcpu = &v->arch;
1926 struct pvclock_vcpu_time_info guest_hv_clock;
1927
4e335d9e 1928 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1929 &guest_hv_clock, sizeof(guest_hv_clock))))
1930 return;
1931
1932 /* This VCPU is paused, but it's legal for a guest to read another
1933 * VCPU's kvmclock, so we really have to follow the specification where
1934 * it says that version is odd if data is being modified, and even after
1935 * it is consistent.
1936 *
1937 * Version field updates must be kept separate. This is because
1938 * kvm_write_guest_cached might use a "rep movs" instruction, and
1939 * writes within a string instruction are weakly ordered. So there
1940 * are three writes overall.
1941 *
1942 * As a small optimization, only write the version field in the first
1943 * and third write. The vcpu->pv_time cache is still valid, because the
1944 * version field is the first in the struct.
1945 */
1946 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1947
51c4b8bb
LA		 1948 if (guest_hv_clock.version & 1)
1949 ++guest_hv_clock.version; /* first time write, random junk */
1950
0d6dd2ff 1951 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1952 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1953 &vcpu->hv_clock,
1954 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1955
1956 smp_wmb();
1957
1958 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1959 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1960
1961 if (vcpu->pvclock_set_guest_stopped_request) {
1962 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1963 vcpu->pvclock_set_guest_stopped_request = false;
1964 }
1965
1966 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1967
4e335d9e
PB		 1968 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1969 &vcpu->hv_clock,
1970 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1971
1972 smp_wmb();
1973
1974 vcpu->hv_clock.version++;
4e335d9e
PB		 1975 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1976 &vcpu->hv_clock,
1977 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1978}
1979
34c238a1 1980static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1981{
78db6a50 1982 unsigned long flags, tgt_tsc_khz;
18068523 1983 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1984 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1985 s64 kernel_ns;
d828199e 1986 u64 tsc_timestamp, host_tsc;
51d59c6b 1987 u8 pvclock_flags;
d828199e
MT		 1988 bool use_master_clock;
1989
1990 kernel_ns = 0;
1991 host_tsc = 0;
18068523 1992
d828199e
MT		 1993 /*
1994 * If the host uses TSC clock, then passthrough TSC as stable
1995 * to the guest.
1996 */
1997 spin_lock(&ka->pvclock_gtod_sync_lock);
1998 use_master_clock = ka->use_master_clock;
1999 if (use_master_clock) {
2000 host_tsc = ka->master_cycle_now;
2001 kernel_ns = ka->master_kernel_ns;
2002 }
2003 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2004
2005 /* Keep irq disabled to prevent changes to the clock */
2006 local_irq_save(flags);
78db6a50
PB		 2007 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2008 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2009 local_irq_restore(flags);
2010 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2011 return 1;
2012 }
d828199e 2013 if (!use_master_clock) {
4ea1636b 2014 host_tsc = rdtsc();
108b249c 2015 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 2016 }
2017
4ba76538 2018 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2019
c285545f
ZA		 2020 /*
2021 * We may have to catch up the TSC to match elapsed wall clock
2022 * time for two reasons, even if kvmclock is used.
2023 * 1) CPU could have been running below the maximum TSC rate
2024 * 2) Broken TSC compensation resets the base at each VCPU
2025 * entry to avoid unknown leaps of TSC even when running
2026 * again on the same CPU. This may cause apparent elapsed
2027 * time to disappear, and the guest to stand still or run
2028 * very slowly.
2029 */
2030 if (vcpu->tsc_catchup) {
2031 u64 tsc = compute_guest_tsc(v, kernel_ns);
2032 if (tsc > tsc_timestamp) {
f1e2b260 2033 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2034 tsc_timestamp = tsc;
2035 }
50d0a0f9
GH		 2036 }
2037
18068523
GOC		 2038 local_irq_restore(flags);
2039
0d6dd2ff 2040 /* With all the info we got, fill in the values */
18068523 2041
78db6a50
PB		 2042 if (kvm_has_tsc_control)
2043 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2044
2045 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2046 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2047 &vcpu->hv_clock.tsc_shift,
2048 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2049 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2050 }
2051
1d5f066e 2052 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2053 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2054 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2055
d828199e 2056 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2057 pvclock_flags = 0;
d828199e
MT		 2058 if (use_master_clock)
2059 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2060
78c0337a
MT		 2061 vcpu->hv_clock.flags = pvclock_flags;
2062
095cf55d
PB		 2063 if (vcpu->pv_time_enabled)
2064 kvm_setup_pvclock_page(v);
2065 if (v == kvm_get_vcpu(v->kvm, 0))
2066 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2067 return 0;
c8076604
GH		 2068}
2069
0061d53d
MT		 2070/*
2071 * kvmclock updates which are isolated to a given vcpu, such as
2072 * vcpu->cpu migration, should not allow system_timestamp from
2073 * the rest of the vcpus to remain static. Otherwise ntp frequency
2074 * correction applies to one vcpu's system_timestamp but not
2075 * the others.
2076 *
2077 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2078 * We need to rate-limit these requests though, as they can
2079 * considerably slow guests that have a large number of vcpus.
2080 * The time for a remote vcpu to update its kvmclock is bound
2081 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2082 */
2083
7e44e449
AJ		 2084#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2085
2086static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2087{
2088 int i;
7e44e449
AJ		 2089 struct delayed_work *dwork = to_delayed_work(work);
2090 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2091 kvmclock_update_work);
2092 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2093 struct kvm_vcpu *vcpu;
2094
2095 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2096 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2097 kvm_vcpu_kick(vcpu);
2098 }
2099}
2100
7e44e449
AJ		 2101static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2102{
2103 struct kvm *kvm = v->kvm;
2104
105b21bb 2105 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2106 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2107 KVMCLOCK_UPDATE_DELAY);
2108}
2109
332967a3
AJ		 2110#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2111
2112static void kvmclock_sync_fn(struct work_struct *work)
2113{
2114 struct delayed_work *dwork = to_delayed_work(work);
2115 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2116 kvmclock_sync_work);
2117 struct kvm *kvm = container_of(ka, struct kvm, arch);
2118
630994b3
MT		 2119 if (!kvmclock_periodic_sync)
2120 return;
2121
332967a3
AJ		 2122 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2123 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2124 KVMCLOCK_SYNC_PERIOD);
2125}
2126
9ffd986c 2127static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2128{
890ca9ae
HY		 2129 u64 mcg_cap = vcpu->arch.mcg_cap;
2130 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2131 u32 msr = msr_info->index;
2132 u64 data = msr_info->data;
890ca9ae 2133
15c4a640 2134 switch (msr) {
15c4a640 2135 case MSR_IA32_MCG_STATUS:
890ca9ae 2136 vcpu->arch.mcg_status = data;
15c4a640 2137 break;
c7ac679c 2138 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2139 if (!(mcg_cap & MCG_CTL_P))
2140 return 1;
2141 if (data != 0 && data != ~(u64)0)
2142 return -1;
2143 vcpu->arch.mcg_ctl = data;
2144 break;
2145 default:
2146 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2147 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2148 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2149 /* only 0 or all 1s can be written to IA32_MCi_CTL
2150 * some Linux kernels though clear bit 10 in bank 4 to
2151 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2152 * this to avoid an uncatched #GP in the guest
2153 */
890ca9ae 2154 if ((offset & 0x3) == 0 &&
114be429 2155 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2156 return -1;
9ffd986c
WL		 2157 if (!msr_info->host_initiated &&
2158 (offset & 0x3) == 1 && data != 0)
2159 return -1;
890ca9ae
HY		 2160 vcpu->arch.mce_banks[offset] = data;
2161 break;
2162 }
2163 return 1;
2164 }
2165 return 0;
2166}
2167
ffde22ac
ES		 2168static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2169{
2170 struct kvm *kvm = vcpu->kvm;
2171 int lm = is_long_mode(vcpu);
2172 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2173 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2174 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2175 : kvm->arch.xen_hvm_config.blob_size_32;
2176 u32 page_num = data & ~PAGE_MASK;
2177 u64 page_addr = data & PAGE_MASK;
2178 u8 *page;
2179 int r;
2180
2181 r = -E2BIG;
2182 if (page_num >= blob_size)
2183 goto out;
2184 r = -ENOMEM;
ff5c2c03
SL		 2185 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2186 if (IS_ERR(page)) {
2187 r = PTR_ERR(page);
ffde22ac 2188 goto out;
ff5c2c03 2189 }
54bf36aa 2190 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2191 goto out_free;
2192 r = 0;
2193out_free:
2194 kfree(page);
2195out:
2196 return r;
2197}
2198
344d9588
GN		 2199static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2200{
2201 gpa_t gpa = data & ~0x3f;
2202
52a5c155
WL		 2203 /* Bits 3:5 are reserved, Should be zero */
2204 if (data & 0x38)
344d9588
GN		 2205 return 1;
2206
2207 vcpu->arch.apf.msr_val = data;
2208
2209 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2210 kvm_clear_async_pf_completion_queue(vcpu);
2211 kvm_async_pf_hash_reset(vcpu);
2212 return 0;
2213 }
2214
4e335d9e 2215 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2216 sizeof(u32)))
344d9588
GN		 2217 return 1;
2218
6adba527 2219 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2220 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2221 kvm_async_pf_wakeup_all(vcpu);
2222 return 0;
2223}
2224
12f9a48f
GC		 2225static void kvmclock_reset(struct kvm_vcpu *vcpu)
2226{
0b79459b 2227 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2228}
2229
f38a7b75
WL		 2230static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2231{
2232 ++vcpu->stat.tlb_flush;
2233 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2234}
2235
c9aaa895
GC		 2236static void record_steal_time(struct kvm_vcpu *vcpu)
2237{
2238 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2239 return;
2240
4e335d9e 2241 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2242 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2243 return;
2244
f38a7b75
WL		 2245 /*
2246 * Doing a TLB flush here, on the guest's behalf, can avoid
2247 * expensive IPIs.
2248 */
2249 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2250 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2251
35f3fae1
WL		 2252 if (vcpu->arch.st.steal.version & 1)
2253 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2254
2255 vcpu->arch.st.steal.version += 1;
2256
4e335d9e 2257 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2258 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2259
2260 smp_wmb();
2261
c54cdf14
LC		 2262 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2263 vcpu->arch.st.last_steal;
2264 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2265
4e335d9e 2266 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2267 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2268
2269 smp_wmb();
2270
2271 vcpu->arch.st.steal.version += 1;
c9aaa895 2272
4e335d9e 2273 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2274 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2275}
2276
8fe8ab46 2277int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2278{
5753785f 2279 bool pr = false;
8fe8ab46
WA		 2280 u32 msr = msr_info->index;
2281 u64 data = msr_info->data;
5753785f 2282
15c4a640 2283 switch (msr) {
2e32b719 2284 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2285 case MSR_IA32_UCODE_WRITE:
2286 case MSR_VM_HSAVE_PA:
2287 case MSR_AMD64_PATCH_LOADER:
2288 case MSR_AMD64_BU_CFG2:
405a353a 2289 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2290 break;
2291
518e7b94
WL		 2292 case MSR_IA32_UCODE_REV:
2293 if (msr_info->host_initiated)
2294 vcpu->arch.microcode_version = data;
2295 break;
15c4a640 2296 case MSR_EFER:
b69e8cae 2297 return set_efer(vcpu, data);
8f1589d9
AP		 2298 case MSR_K7_HWCR:
2299 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2300 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2301 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2302 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2303 if (data != 0) {
a737f256
CD		 2304 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2305 data);
8f1589d9
AP		 2306 return 1;
2307 }
15c4a640 2308 break;
f7c6d140
AP		 2309 case MSR_FAM10H_MMIO_CONF_BASE:
2310 if (data != 0) {
a737f256
CD		 2311 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2312 "0x%llx\n", data);
f7c6d140
AP		 2313 return 1;
2314 }
15c4a640 2315 break;
b5e2fec0
AG		 2316 case MSR_IA32_DEBUGCTLMSR:
2317 if (!data) {
2318 /* We support the non-activated case already */
2319 break;
2320 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2321 /* Values other than LBR and BTF are vendor-specific,
2322 thus reserved and should throw a #GP */
2323 return 1;
2324 }
a737f256
CD		 2325 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2326 __func__, data);
b5e2fec0 2327 break;
9ba075a6 2328 case 0x200 ... 0x2ff:
ff53604b 2329 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2330 case MSR_IA32_APICBASE:
58cb628d 2331 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2332 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2333 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2334 case MSR_IA32_TSCDEADLINE:
2335 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2336 break;
ba904635 2337 case MSR_IA32_TSC_ADJUST:
d6321d49 2338 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2339 if (!msr_info->host_initiated) {
d913b904 2340 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2341 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2342 }
2343 vcpu->arch.ia32_tsc_adjust_msr = data;
2344 }
2345 break;
15c4a640 2346 case MSR_IA32_MISC_ENABLE:
ad312c7c 2347 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2348 break;
64d60670
PB		 2349 case MSR_IA32_SMBASE:
2350 if (!msr_info->host_initiated)
2351 return 1;
2352 vcpu->arch.smbase = data;
2353 break;
52797bf9
LA		 2354 case MSR_SMI_COUNT:
2355 if (!msr_info->host_initiated)
2356 return 1;
2357 vcpu->arch.smi_count = data;
2358 break;
11c6bffa 2359 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2360 case MSR_KVM_WALL_CLOCK:
2361 vcpu->kvm->arch.wall_clock = data;
2362 kvm_write_wall_clock(vcpu->kvm, data);
2363 break;
11c6bffa 2364 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2365 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2366 struct kvm_arch *ka = &vcpu->kvm->arch;
2367
12f9a48f 2368 kvmclock_reset(vcpu);
18068523 2369
54750f2c
MT		 2370 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2371 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2372
2373 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2374 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2375
2376 ka->boot_vcpu_runs_old_kvmclock = tmp;
2377 }
2378
18068523 2379 vcpu->arch.time = data;
0061d53d 2380 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2381
2382 /* we verify if the enable bit is set... */
2383 if (!(data & 1))
2384 break;
2385
4e335d9e 2386 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2387 &vcpu->arch.pv_time, data & ~1ULL,
2388 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2389 vcpu->arch.pv_time_enabled = false;
2390 else
2391 vcpu->arch.pv_time_enabled = true;
32cad84f 2392
18068523
GOC		 2393 break;
2394 }
344d9588
GN		 2395 case MSR_KVM_ASYNC_PF_EN:
2396 if (kvm_pv_enable_async_pf(vcpu, data))
2397 return 1;
2398 break;
c9aaa895
GC		 2399 case MSR_KVM_STEAL_TIME:
2400
2401 if (unlikely(!sched_info_on()))
2402 return 1;
2403
2404 if (data & KVM_STEAL_RESERVED_MASK)
2405 return 1;
2406
4e335d9e 2407 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2408 data & KVM_STEAL_VALID_BITS,
2409 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2410 return 1;
2411
2412 vcpu->arch.st.msr_val = data;
2413
2414 if (!(data & KVM_MSR_ENABLED))
2415 break;
2416
c9aaa895
GC		 2417 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2418
2419 break;
ae7a2a3f
MT		 2420 case MSR_KVM_PV_EOI_EN:
2421 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2422 return 1;
2423 break;
c9aaa895 2424
890ca9ae
HY		 2425 case MSR_IA32_MCG_CTL:
2426 case MSR_IA32_MCG_STATUS:
81760dcc 2427 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2428 return set_msr_mce(vcpu, msr_info);
71db6023 2429
6912ac32
WH		 2430 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2431 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2432 pr = true; /* fall through */
2433 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2434 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2435 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2436 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2437
2438 if (pr || data != 0)
a737f256
CD		 2439 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2440 "0x%x data 0x%llx\n", msr, data);
5753785f 2441 break;
84e0cefa
JS		 2442 case MSR_K7_CLK_CTL:
2443 /*
2444 * Ignore all writes to this no longer documented MSR.
2445 * Writes are only relevant for old K7 processors,
2446 * all pre-dating SVM, but a recommended workaround from
4a969980 2447 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2448 * affected processor models on the command line, hence
2449 * the need to ignore the workaround.
2450 */
2451 break;
55cd8e5a 2452 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2453 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2454 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2455 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2456 return kvm_hv_set_msr_common(vcpu, msr, data,
2457 msr_info->host_initiated);
91c9c3ed 2458 case MSR_IA32_BBL_CR_CTL3:
2459 /* Drop writes to this legacy MSR -- see rdmsr
2460 * counterpart for further detail.
2461 */
fab0aa3b
EM		 2462 if (report_ignored_msrs)
2463 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2464 msr, data);
91c9c3ed 2465 break;
2b036c6b 2466 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2467 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2468 return 1;
2469 vcpu->arch.osvw.length = data;
2470 break;
2471 case MSR_AMD64_OSVW_STATUS:
d6321d49 2472 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2473 return 1;
2474 vcpu->arch.osvw.status = data;
2475 break;
db2336a8
KH		 2476 case MSR_PLATFORM_INFO:
2477 if (!msr_info->host_initiated ||
2478 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2479 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2480 cpuid_fault_enabled(vcpu)))
2481 return 1;
2482 vcpu->arch.msr_platform_info = data;
2483 break;
2484 case MSR_MISC_FEATURES_ENABLES:
2485 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2486 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2487 !supports_cpuid_fault(vcpu)))
2488 return 1;
2489 vcpu->arch.msr_misc_features_enables = data;
2490 break;
15c4a640 2491 default:
ffde22ac
ES		 2492 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2493 return xen_hvm_config(vcpu, data);
c6702c9d 2494 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2495 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2496 if (!ignore_msrs) {
ae0f5499 2497 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2498 msr, data);
ed85c068
AP		 2499 return 1;
2500 } else {
fab0aa3b
EM		 2501 if (report_ignored_msrs)
2502 vcpu_unimpl(vcpu,
2503 "ignored wrmsr: 0x%x data 0x%llx\n",
2504 msr, data);
ed85c068
AP		 2505 break;
2506 }
15c4a640
CO		 2507 }
2508 return 0;
2509}
2510EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2511
2512
2513/*
2514 * Reads an msr value (of 'msr_index') into 'pdata'.
2515 * Returns 0 on success, non-0 otherwise.
2516 * Assumes vcpu_load() was already called.
2517 */
609e36d3 2518int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2519{
609e36d3 2520 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2521}
ff651cb6 2522EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2523
890ca9ae 2524static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2525{
2526 u64 data;
890ca9ae
HY		 2527 u64 mcg_cap = vcpu->arch.mcg_cap;
2528 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2529
2530 switch (msr) {
15c4a640
CO		 2531 case MSR_IA32_P5_MC_ADDR:
2532 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2533 data = 0;
2534 break;
15c4a640 2535 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2536 data = vcpu->arch.mcg_cap;
2537 break;
c7ac679c 2538 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2539 if (!(mcg_cap & MCG_CTL_P))
2540 return 1;
2541 data = vcpu->arch.mcg_ctl;
2542 break;
2543 case MSR_IA32_MCG_STATUS:
2544 data = vcpu->arch.mcg_status;
2545 break;
2546 default:
2547 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2548 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2549 u32 offset = msr - MSR_IA32_MC0_CTL;
2550 data = vcpu->arch.mce_banks[offset];
2551 break;
2552 }
2553 return 1;
2554 }
2555 *pdata = data;
2556 return 0;
2557}
2558
609e36d3 2559int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2560{
609e36d3 2561 switch (msr_info->index) {
890ca9ae 2562 case MSR_IA32_PLATFORM_ID:
15c4a640 2563 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2564 case MSR_IA32_DEBUGCTLMSR:
2565 case MSR_IA32_LASTBRANCHFROMIP:
2566 case MSR_IA32_LASTBRANCHTOIP:
2567 case MSR_IA32_LASTINTFROMIP:
2568 case MSR_IA32_LASTINTTOIP:
60af2ecd 2569 case MSR_K8_SYSCFG:
3afb1121
PB		 2570 case MSR_K8_TSEG_ADDR:
2571 case MSR_K8_TSEG_MASK:
60af2ecd 2572 case MSR_K7_HWCR:
61a6bd67 2573 case MSR_VM_HSAVE_PA:
1fdbd48c 2574 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2575 case MSR_AMD64_NB_CFG:
f7c6d140 2576 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2577 case MSR_AMD64_BU_CFG2:
0c2df2a1 2578 case MSR_IA32_PERF_CTL:
405a353a 2579 case MSR_AMD64_DC_CFG:
609e36d3 2580 msr_info->data = 0;
15c4a640 2581 break;
c51eb52b 2582 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2583 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2584 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2585 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2586 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2587 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2588 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2589 msr_info->data = 0;
5753785f 2590 break;
742bc670 2591 case MSR_IA32_UCODE_REV:
518e7b94 2592 msr_info->data = vcpu->arch.microcode_version;
742bc670 2593 break;
9ba075a6 2594 case MSR_MTRRcap:
9ba075a6 2595 case 0x200 ... 0x2ff:
ff53604b 2596 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2597 case 0xcd: /* fsb frequency */
609e36d3 2598 msr_info->data = 3;
15c4a640 2599 break;
7b914098
JS		 2600 /*
2601 * MSR_EBC_FREQUENCY_ID
2602 * Conservative value valid for even the basic CPU models.
2603 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2604 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2605 * and 266MHz for model 3, or 4. Set Core Clock
2606 * Frequency to System Bus Frequency Ratio to 1 (bits
2607 * 31:24) even though these are only valid for CPU
2608 * models > 2, however guests may end up dividing or
2609 * multiplying by zero otherwise.
2610 */
2611 case MSR_EBC_FREQUENCY_ID:
609e36d3 2612 msr_info->data = 1 << 24;
7b914098 2613 break;
15c4a640 2614 case MSR_IA32_APICBASE:
609e36d3 2615 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2616 break;
0105d1a5 2617 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2618 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2619 break;
a3e06bbe 2620 case MSR_IA32_TSCDEADLINE:
609e36d3 2621 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2622 break;
ba904635 2623 case MSR_IA32_TSC_ADJUST:
609e36d3 2624 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2625 break;
15c4a640 2626 case MSR_IA32_MISC_ENABLE:
609e36d3 2627 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2628 break;
64d60670
PB		 2629 case MSR_IA32_SMBASE:
2630 if (!msr_info->host_initiated)
2631 return 1;
2632 msr_info->data = vcpu->arch.smbase;
15c4a640 2633 break;
52797bf9
LA		 2634 case MSR_SMI_COUNT:
2635 msr_info->data = vcpu->arch.smi_count;
2636 break;
847f0ad8
AG		 2637 case MSR_IA32_PERF_STATUS:
2638 /* TSC increment by tick */
609e36d3 2639 msr_info->data = 1000ULL;
847f0ad8 2640 /* CPU multiplier */
b0996ae4 2641 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2642 break;
15c4a640 2643 case MSR_EFER:
609e36d3 2644 msr_info->data = vcpu->arch.efer;
15c4a640 2645 break;
18068523 2646 case MSR_KVM_WALL_CLOCK:
11c6bffa 2647 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2648 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2649 break;
2650 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2651 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2652 msr_info->data = vcpu->arch.time;
18068523 2653 break;
344d9588 2654 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2655 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2656 break;
c9aaa895 2657 case MSR_KVM_STEAL_TIME:
609e36d3 2658 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2659 break;
1d92128f 2660 case MSR_KVM_PV_EOI_EN:
609e36d3 2661 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2662 break;
890ca9ae
HY		 2663 case MSR_IA32_P5_MC_ADDR:
2664 case MSR_IA32_P5_MC_TYPE:
2665 case MSR_IA32_MCG_CAP:
2666 case MSR_IA32_MCG_CTL:
2667 case MSR_IA32_MCG_STATUS:
81760dcc 2668 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2669 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2670 case MSR_K7_CLK_CTL:
2671 /*
2672 * Provide expected ramp-up count for K7. All other
2673 * are set to zero, indicating minimum divisors for
2674 * every field.
2675 *
2676 * This prevents guest kernels on AMD host with CPU
2677 * type 6, model 8 and higher from exploding due to
2678 * the rdmsr failing.
2679 */
609e36d3 2680 msr_info->data = 0x20000000;
84e0cefa 2681 break;
55cd8e5a 2682 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2683 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2684 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2685 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2686 return kvm_hv_get_msr_common(vcpu,
2687 msr_info->index, &msr_info->data);
55cd8e5a 2688 break;
91c9c3ed 2689 case MSR_IA32_BBL_CR_CTL3:
2690 /* This legacy MSR exists but isn't fully documented in current
2691 * silicon. It is however accessed by winxp in very narrow
2692 * scenarios where it sets bit #19, itself documented as
2693 * a "reserved" bit. Best effort attempt to source coherent
2694 * read data here should the balance of the register be
2695 * interpreted by the guest:
2696 *
2697 * L2 cache control register 3: 64GB range, 256KB size,
2698 * enabled, latency 0x1, configured
2699 */
609e36d3 2700 msr_info->data = 0xbe702111;
91c9c3ed 2701 break;
2b036c6b 2702 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2703 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2704 return 1;
609e36d3 2705 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2706 break;
2707 case MSR_AMD64_OSVW_STATUS:
d6321d49 2708 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2709 return 1;
609e36d3 2710 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2711 break;
db2336a8
KH		 2712 case MSR_PLATFORM_INFO:
2713 msr_info->data = vcpu->arch.msr_platform_info;
2714 break;
2715 case MSR_MISC_FEATURES_ENABLES:
2716 msr_info->data = vcpu->arch.msr_misc_features_enables;
2717 break;
15c4a640 2718 default:
c6702c9d 2719 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2720 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2721 if (!ignore_msrs) {
ae0f5499
BD		 2722 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2723 msr_info->index);
ed85c068
AP		 2724 return 1;
2725 } else {
fab0aa3b
EM		 2726 if (report_ignored_msrs)
2727 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2728 msr_info->index);
609e36d3 2729 msr_info->data = 0;
ed85c068
AP		 2730 }
2731 break;
15c4a640 2732 }
15c4a640
CO		 2733 return 0;
2734}
2735EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2736
313a3dc7
CO		 2737/*
2738 * Read or write a bunch of msrs. All parameters are kernel addresses.
2739 *
2740 * @return number of msrs set successfully.
2741 */
2742static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2743 struct kvm_msr_entry *entries,
2744 int (*do_msr)(struct kvm_vcpu *vcpu,
2745 unsigned index, u64 *data))
2746{
801e459a 2747 int i;
313a3dc7 2748
313a3dc7
CO		 2749 for (i = 0; i < msrs->nmsrs; ++i)
2750 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2751 break;
2752
313a3dc7
CO		 2753 return i;
2754}
2755
2756/*
2757 * Read or write a bunch of msrs. Parameters are user addresses.
2758 *
2759 * @return number of msrs set successfully.
2760 */
2761static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2762 int (*do_msr)(struct kvm_vcpu *vcpu,
2763 unsigned index, u64 *data),
2764 int writeback)
2765{
2766 struct kvm_msrs msrs;
2767 struct kvm_msr_entry *entries;
2768 int r, n;
2769 unsigned size;
2770
2771 r = -EFAULT;
2772 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2773 goto out;
2774
2775 r = -E2BIG;
2776 if (msrs.nmsrs >= MAX_IO_MSRS)
2777 goto out;
2778
313a3dc7 2779 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2780 entries = memdup_user(user_msrs->entries, size);
2781 if (IS_ERR(entries)) {
2782 r = PTR_ERR(entries);
313a3dc7 2783 goto out;
ff5c2c03 2784 }
313a3dc7
CO		 2785
2786 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2787 if (r < 0)
2788 goto out_free;
2789
2790 r = -EFAULT;
2791 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2792 goto out_free;
2793
2794 r = n;
2795
2796out_free:
7a73c028 2797 kfree(entries);
313a3dc7
CO		 2798out:
2799 return r;
2800}
2801
784aa3d7 2802int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2803{
2804 int r;
2805
2806 switch (ext) {
2807 case KVM_CAP_IRQCHIP:
2808 case KVM_CAP_HLT:
2809 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2810 case KVM_CAP_SET_TSS_ADDR:
07716717 2811 case KVM_CAP_EXT_CPUID:
9c15bb1d 2812 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2813 case KVM_CAP_CLOCKSOURCE:
7837699f 2814 case KVM_CAP_PIT:
a28e4f5a 2815 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2816 case KVM_CAP_MP_STATE:
ed848624 2817 case KVM_CAP_SYNC_MMU:
a355c85c 2818 case KVM_CAP_USER_NMI:
52d939a0 2819 case KVM_CAP_REINJECT_CONTROL:
4925663a 2820 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2821 case KVM_CAP_IOEVENTFD:
f848a5a8 2822 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2823 case KVM_CAP_PIT2:
e9f42757 2824 case KVM_CAP_PIT_STATE2:
b927a3ce 2825 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2826 case KVM_CAP_XEN_HVM:
3cfc3092 2827 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2828 case KVM_CAP_HYPERV:
10388a07 2829 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2830 case KVM_CAP_HYPERV_SPIN:
5c919412 2831 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2832 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2833 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 2834 case KVM_CAP_HYPERV_EVENTFD:
ab9f4ecb 2835 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2836 case KVM_CAP_DEBUGREGS:
d2be1651 2837 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2838 case KVM_CAP_XSAVE:
344d9588 2839 case KVM_CAP_ASYNC_PF:
92a1f12d 2840 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2841 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2842 case KVM_CAP_READONLY_MEM:
5f66b620 2843 case KVM_CAP_HYPERV_TIME:
100943c5 2844 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2845 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2846 case KVM_CAP_ENABLE_CAP_VM:
2847 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2848 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2849 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2850 case KVM_CAP_IMMEDIATE_EXIT:
801e459a 2851 case KVM_CAP_GET_MSR_FEATURES:
018d00d2
ZX		 2852 r = 1;
2853 break;
01643c51
KH		 2854 case KVM_CAP_SYNC_REGS:
2855 r = KVM_SYNC_X86_VALID_FIELDS;
2856 break;
e3fd9a93
PB		 2857 case KVM_CAP_ADJUST_CLOCK:
2858 r = KVM_CLOCK_TSC_STABLE;
2859 break;
668fffa3
MT		 2860 case KVM_CAP_X86_GUEST_MWAIT:
2861 r = kvm_mwait_in_guest();
2862 break;
6d396b55
PB		 2863 case KVM_CAP_X86_SMM:
2864 /* SMBASE is usually relocated above 1M on modern chipsets,
2865 * and SMM handlers might indeed rely on 4G segment limits,
2866 * so do not report SMM to be available if real mode is
2867 * emulated via vm86 mode. Still, do not go to great lengths
2868 * to avoid userspace's usage of the feature, because it is a
2869 * fringe case that is not enabled except via specific settings
2870 * of the module parameters.
2871 */
2872 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2873 break;
774ead3a
AK		 2874 case KVM_CAP_VAPIC:
2875 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2876 break;
f725230a 2877 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2878 r = KVM_SOFT_MAX_VCPUS;
2879 break;
2880 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2881 r = KVM_MAX_VCPUS;
2882 break;
a988b910 2883 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2884 r = KVM_USER_MEM_SLOTS;
a988b910 2885 break;
a68a6a72
MT		 2886 case KVM_CAP_PV_MMU: /* obsolete */
2887 r = 0;
2f333bcb 2888 break;
890ca9ae
HY		 2889 case KVM_CAP_MCE:
2890 r = KVM_MAX_MCE_BANKS;
2891 break;
2d5b5a66 2892 case KVM_CAP_XCRS:
d366bf7e 2893 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2894 break;
92a1f12d
JR		 2895 case KVM_CAP_TSC_CONTROL:
2896 r = kvm_has_tsc_control;
2897 break;
37131313
RK		 2898 case KVM_CAP_X2APIC_API:
2899 r = KVM_X2APIC_API_VALID_FLAGS;
2900 break;
018d00d2
ZX		 2901 default:
2902 r = 0;
2903 break;
2904 }
2905 return r;
2906
2907}
2908
043405e1
CO		 2909long kvm_arch_dev_ioctl(struct file *filp,
2910 unsigned int ioctl, unsigned long arg)
2911{
2912 void __user *argp = (void __user *)arg;
2913 long r;
2914
2915 switch (ioctl) {
2916 case KVM_GET_MSR_INDEX_LIST: {
2917 struct kvm_msr_list __user *user_msr_list = argp;
2918 struct kvm_msr_list msr_list;
2919 unsigned n;
2920
2921 r = -EFAULT;
2922 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2923 goto out;
2924 n = msr_list.nmsrs;
62ef68bb 2925 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2926 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2927 goto out;
2928 r = -E2BIG;
e125e7b6 2929 if (n < msr_list.nmsrs)
043405e1
CO		 2930 goto out;
2931 r = -EFAULT;
2932 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2933 num_msrs_to_save * sizeof(u32)))
2934 goto out;
e125e7b6 2935 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2936 &emulated_msrs,
62ef68bb 2937 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2938 goto out;
2939 r = 0;
2940 break;
2941 }
9c15bb1d
BP		 2942 case KVM_GET_SUPPORTED_CPUID:
2943 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2944 struct kvm_cpuid2 __user *cpuid_arg = argp;
2945 struct kvm_cpuid2 cpuid;
2946
2947 r = -EFAULT;
2948 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2949 goto out;
9c15bb1d
BP		 2950
2951 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2952 ioctl);
674eea0f
AK		 2953 if (r)
2954 goto out;
2955
2956 r = -EFAULT;
2957 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2958 goto out;
2959 r = 0;
2960 break;
2961 }
890ca9ae 2962 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2963 r = -EFAULT;
c45dcc71
AR		 2964 if (copy_to_user(argp, &kvm_mce_cap_supported,
2965 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2966 goto out;
2967 r = 0;
2968 break;
801e459a
TL		 2969 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
2970 struct kvm_msr_list __user *user_msr_list = argp;
2971 struct kvm_msr_list msr_list;
2972 unsigned int n;
2973
2974 r = -EFAULT;
2975 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
2976 goto out;
2977 n = msr_list.nmsrs;
2978 msr_list.nmsrs = num_msr_based_features;
2979 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
2980 goto out;
2981 r = -E2BIG;
2982 if (n < msr_list.nmsrs)
2983 goto out;
2984 r = -EFAULT;
2985 if (copy_to_user(user_msr_list->indices, &msr_based_features,
2986 num_msr_based_features * sizeof(u32)))
2987 goto out;
2988 r = 0;
2989 break;
2990 }
2991 case KVM_GET_MSRS:
2992 r = msr_io(NULL, argp, do_get_msr_feature, 1);
2993 break;
890ca9ae 2994 }
043405e1
CO		 2995 default:
2996 r = -EINVAL;
2997 }
2998out:
2999 return r;
3000}
3001
f5f48ee1
SY		 3002static void wbinvd_ipi(void *garbage)
3003{
3004 wbinvd();
3005}
3006
3007static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3008{
e0f0bbc5 3009 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3010}
3011
313a3dc7
CO		 3012void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3013{
f5f48ee1
SY		 3014 /* Address WBINVD may be executed by guest */
3015 if (need_emulate_wbinvd(vcpu)) {
3016 if (kvm_x86_ops->has_wbinvd_exit())
3017 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3018 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3019 smp_call_function_single(vcpu->cpu,
3020 wbinvd_ipi, NULL, 1);
3021 }
3022
313a3dc7 3023 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3024
0dd6a6ed
ZA		 3025 /* Apply any externally detected TSC adjustments (due to suspend) */
3026 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3027 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3028 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3029 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3030 }
8f6055cb 3031
b0c39dc6 3032 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3033 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3034 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3035 if (tsc_delta < 0)
3036 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3037
b0c39dc6 3038 if (kvm_check_tsc_unstable()) {
07c1419a 3039 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3040 vcpu->arch.last_guest_tsc);
a545ab6a 3041 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3042 vcpu->arch.tsc_catchup = 1;
c285545f 3043 }
a749e247
PB		 3044
3045 if (kvm_lapic_hv_timer_in_use(vcpu))
3046 kvm_lapic_restart_hv_timer(vcpu);
3047
d98d07ca
MT		 3048 /*
3049 * On a host with synchronized TSC, there is no need to update
3050 * kvmclock on vcpu->cpu migration
3051 */
3052 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3053 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3054 if (vcpu->cpu != cpu)
1bd2009e 3055 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3056 vcpu->cpu = cpu;
6b7d7e76 3057 }
c9aaa895 3058
c9aaa895 3059 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3060}
3061
0b9f6c46
PX		 3062static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3063{
3064 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3065 return;
3066
fa55eedd 3067 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3068
4e335d9e 3069 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3070 &vcpu->arch.st.steal.preempted,
3071 offsetof(struct kvm_steal_time, preempted),
3072 sizeof(vcpu->arch.st.steal.preempted));
3073}
3074
313a3dc7
CO		 3075void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3076{
cc0d907c 3077 int idx;
de63ad4c
LM		 3078
3079 if (vcpu->preempted)
3080 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3081
931f261b
AA		 3082 /*
3083 * Disable page faults because we're in atomic context here.
3084 * kvm_write_guest_offset_cached() would call might_fault()
3085 * that relies on pagefault_disable() to tell if there's a
3086 * bug. NOTE: the write to guest memory may not go through if
3087 * during postcopy live migration or if there's heavy guest
3088 * paging.
3089 */
3090 pagefault_disable();
cc0d907c
AA		 3091 /*
3092 * kvm_memslots() will be called by
3093 * kvm_write_guest_offset_cached() so take the srcu lock.
3094 */
3095 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3096 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3097 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3098 pagefault_enable();
02daab21 3099 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3100 vcpu->arch.last_host_tsc = rdtsc();
efdab992
WL		 3101 /*
3102 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3103 * on every vmexit, but if not, we might have a stale dr6 from the
3104 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3105 */
3106 set_debugreg(0, 6);
313a3dc7
CO		 3107}
3108
313a3dc7
CO		 3109static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3110 struct kvm_lapic_state *s)
3111{
fa59cc00 3112 if (vcpu->arch.apicv_active)
d62caabb
AS		 3113 kvm_x86_ops->sync_pir_to_irr(vcpu);
3114
a92e2543 3115 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3116}
3117
3118static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3119 struct kvm_lapic_state *s)
3120{
a92e2543
RK		 3121 int r;
3122
3123 r = kvm_apic_set_state(vcpu, s);
3124 if (r)
3125 return r;
cb142eb7 3126 update_cr8_intercept(vcpu);
313a3dc7
CO		 3127
3128 return 0;
3129}
3130
127a457a
MG		 3131static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3132{
3133 return (!lapic_in_kernel(vcpu) ||
3134 kvm_apic_accept_pic_intr(vcpu));
3135}
3136
782d422b
MG		 3137/*
3138 * if userspace requested an interrupt window, check that the
3139 * interrupt window is open.
3140 *
3141 * No need to exit to userspace if we already have an interrupt queued.
3142 */
3143static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3144{
3145 return kvm_arch_interrupt_allowed(vcpu) &&
3146 !kvm_cpu_has_interrupt(vcpu) &&
3147 !kvm_event_needs_reinjection(vcpu) &&
3148 kvm_cpu_accept_dm_intr(vcpu);
3149}
3150
f77bc6a4
ZX		 3151static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3152 struct kvm_interrupt *irq)
3153{
02cdb50f 3154 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3155 return -EINVAL;
1c1a9ce9
SR		 3156
3157 if (!irqchip_in_kernel(vcpu->kvm)) {
3158 kvm_queue_interrupt(vcpu, irq->irq, false);
3159 kvm_make_request(KVM_REQ_EVENT, vcpu);
3160 return 0;
3161 }
3162
3163 /*
3164 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3165 * fail for in-kernel 8259.
3166 */
3167 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3168 return -ENXIO;
f77bc6a4 3169
1c1a9ce9
SR		 3170 if (vcpu->arch.pending_external_vector != -1)
3171 return -EEXIST;
f77bc6a4 3172
1c1a9ce9 3173 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3174 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3175 return 0;
3176}
3177
c4abb7c9
JK		 3178static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3179{
c4abb7c9 3180 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3181
3182 return 0;
3183}
3184
f077825a
PB		 3185static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3186{
64d60670
PB		 3187 kvm_make_request(KVM_REQ_SMI, vcpu);
3188
f077825a
PB		 3189 return 0;
3190}
3191
b209749f
AK		 3192static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3193 struct kvm_tpr_access_ctl *tac)
3194{
3195 if (tac->flags)
3196 return -EINVAL;
3197 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3198 return 0;
3199}
3200
890ca9ae
HY		 3201static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3202 u64 mcg_cap)
3203{
3204 int r;
3205 unsigned bank_num = mcg_cap & 0xff, bank;
3206
3207 r = -EINVAL;
a9e38c3e 3208 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3209 goto out;
c45dcc71 3210 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3211 goto out;
3212 r = 0;
3213 vcpu->arch.mcg_cap = mcg_cap;
3214 /* Init IA32_MCG_CTL to all 1s */
3215 if (mcg_cap & MCG_CTL_P)
3216 vcpu->arch.mcg_ctl = ~(u64)0;
3217 /* Init IA32_MCi_CTL to all 1s */
3218 for (bank = 0; bank < bank_num; bank++)
3219 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3220
3221 if (kvm_x86_ops->setup_mce)
3222 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3223out:
3224 return r;
3225}
3226
3227static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3228 struct kvm_x86_mce *mce)
3229{
3230 u64 mcg_cap = vcpu->arch.mcg_cap;
3231 unsigned bank_num = mcg_cap & 0xff;
3232 u64 *banks = vcpu->arch.mce_banks;
3233
3234 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3235 return -EINVAL;
3236 /*
3237 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3238 * reporting is disabled
3239 */
3240 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3241 vcpu->arch.mcg_ctl != ~(u64)0)
3242 return 0;
3243 banks += 4 * mce->bank;
3244 /*
3245 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3246 * reporting is disabled for the bank
3247 */
3248 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3249 return 0;
3250 if (mce->status & MCI_STATUS_UC) {
3251 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3252 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3253 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3254 return 0;
3255 }
3256 if (banks[1] & MCI_STATUS_VAL)
3257 mce->status |= MCI_STATUS_OVER;
3258 banks[2] = mce->addr;
3259 banks[3] = mce->misc;
3260 vcpu->arch.mcg_status = mce->mcg_status;
3261 banks[1] = mce->status;
3262 kvm_queue_exception(vcpu, MC_VECTOR);
3263 } else if (!(banks[1] & MCI_STATUS_VAL)
3264 || !(banks[1] & MCI_STATUS_UC)) {
3265 if (banks[1] & MCI_STATUS_VAL)
3266 mce->status |= MCI_STATUS_OVER;
3267 banks[2] = mce->addr;
3268 banks[3] = mce->misc;
3269 banks[1] = mce->status;
3270 } else
3271 banks[1] |= MCI_STATUS_OVER;
3272 return 0;
3273}
3274
3cfc3092
JK		 3275static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3276 struct kvm_vcpu_events *events)
3277{
7460fb4a 3278 process_nmi(vcpu);
664f8e26
WL		 3279 /*
3280 * FIXME: pass injected and pending separately. This is only
3281 * needed for nested virtualization, whose state cannot be
3282 * migrated yet. For now we can combine them.
3283 */
03b82a30 3284 events->exception.injected =
664f8e26
WL		 3285 (vcpu->arch.exception.pending ||
3286 vcpu->arch.exception.injected) &&
03b82a30 3287 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3288 events->exception.nr = vcpu->arch.exception.nr;
3289 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3290 events->exception.pad = 0;
3cfc3092
JK		 3291 events->exception.error_code = vcpu->arch.exception.error_code;
3292
03b82a30
JK		 3293 events->interrupt.injected =
3294 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3295 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3296 events->interrupt.soft = 0;
37ccdcbe 3297 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3298
3299 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3300 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3301 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3302 events->nmi.pad = 0;
3cfc3092 3303
66450a21 3304 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3305
f077825a
PB		 3306 events->smi.smm = is_smm(vcpu);
3307 events->smi.pending = vcpu->arch.smi_pending;
3308 events->smi.smm_inside_nmi =
3309 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3310 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3311
dab4b911 3312 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3313 | KVM_VCPUEVENT_VALID_SHADOW
3314 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3315 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3316}
3317
6ef4e07e
XG		 3318static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3319
3cfc3092
JK		 3320static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3321 struct kvm_vcpu_events *events)
3322{
dab4b911 3323 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3324 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3325 | KVM_VCPUEVENT_VALID_SHADOW
3326 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3327 return -EINVAL;
3328
78e546c8 3329 if (events->exception.injected &&
28d06353
JM		 3330 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3331 is_guest_mode(vcpu)))
78e546c8
PB		 3332 return -EINVAL;
3333
28bf2888
DH		 3334 /* INITs are latched while in SMM */
3335 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3336 (events->smi.smm || events->smi.pending) &&
3337 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3338 return -EINVAL;
3339
7460fb4a 3340 process_nmi(vcpu);
664f8e26 3341 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3342 vcpu->arch.exception.pending = events->exception.injected;
3343 vcpu->arch.exception.nr = events->exception.nr;
3344 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3345 vcpu->arch.exception.error_code = events->exception.error_code;
3346
3347 vcpu->arch.interrupt.pending = events->interrupt.injected;
3348 vcpu->arch.interrupt.nr = events->interrupt.nr;
3349 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3350 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3351 kvm_x86_ops->set_interrupt_shadow(vcpu,
3352 events->interrupt.shadow);
3cfc3092
JK		 3353
3354 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3355 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3356 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3357 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3358
66450a21 3359 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3360 lapic_in_kernel(vcpu))
66450a21 3361 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3362
f077825a 3363 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3364 u32 hflags = vcpu->arch.hflags;
f077825a 3365 if (events->smi.smm)
6ef4e07e 3366 hflags |= HF_SMM_MASK;
f077825a 3367 else
6ef4e07e
XG		 3368 hflags &= ~HF_SMM_MASK;
3369 kvm_set_hflags(vcpu, hflags);
3370
f077825a 3371 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3372
3373 if (events->smi.smm) {
3374 if (events->smi.smm_inside_nmi)
3375 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3376 else
f4ef1910
WL		 3377 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3378 if (lapic_in_kernel(vcpu)) {
3379 if (events->smi.latched_init)
3380 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3381 else
3382 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3383 }
f077825a
PB		 3384 }
3385 }
3386
3842d135
AK		 3387 kvm_make_request(KVM_REQ_EVENT, vcpu);
3388
3cfc3092
JK		 3389 return 0;
3390}
3391
a1efbe77
JK		 3392static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3393 struct kvm_debugregs *dbgregs)
3394{
73aaf249
JK		 3395 unsigned long val;
3396
a1efbe77 3397 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3398 kvm_get_dr(vcpu, 6, &val);
73aaf249 3399 dbgregs->dr6 = val;
a1efbe77
JK		 3400 dbgregs->dr7 = vcpu->arch.dr7;
3401 dbgregs->flags = 0;
97e69aa6 3402 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3403}
3404
3405static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3406 struct kvm_debugregs *dbgregs)
3407{
3408 if (dbgregs->flags)
3409 return -EINVAL;
3410
d14bdb55
PB		 3411 if (dbgregs->dr6 & ~0xffffffffull)
3412 return -EINVAL;
3413 if (dbgregs->dr7 & ~0xffffffffull)
3414 return -EINVAL;
3415
a1efbe77 3416 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3417 kvm_update_dr0123(vcpu);
a1efbe77 3418 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3419 kvm_update_dr6(vcpu);
a1efbe77 3420 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3421 kvm_update_dr7(vcpu);
a1efbe77 3422
a1efbe77
JK		 3423 return 0;
3424}
3425
df1daba7
PB		 3426#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3427
3428static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3429{
c47ada30 3430 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3431 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3432 u64 valid;
3433
3434 /*
3435 * Copy legacy XSAVE area, to avoid complications with CPUID
3436 * leaves 0 and 1 in the loop below.
3437 */
3438 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3439
3440 /* Set XSTATE_BV */
00c87e9a 3441 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3442 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3443
3444 /*
3445 * Copy each region from the possibly compacted offset to the
3446 * non-compacted offset.
3447 */
d91cab78 3448 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3449 while (valid) {
3450 u64 feature = valid & -valid;
3451 int index = fls64(feature) - 1;
3452 void *src = get_xsave_addr(xsave, feature);
3453
3454 if (src) {
3455 u32 size, offset, ecx, edx;
3456 cpuid_count(XSTATE_CPUID, index,
3457 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3458 if (feature == XFEATURE_MASK_PKRU)
3459 memcpy(dest + offset, &vcpu->arch.pkru,
3460 sizeof(vcpu->arch.pkru));
3461 else
3462 memcpy(dest + offset, src, size);
3463
df1daba7
PB		 3464 }
3465
3466 valid -= feature;
3467 }
3468}
3469
3470static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3471{
c47ada30 3472 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3473 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3474 u64 valid;
3475
3476 /*
3477 * Copy legacy XSAVE area, to avoid complications with CPUID
3478 * leaves 0 and 1 in the loop below.
3479 */
3480 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3481
3482 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3483 xsave->header.xfeatures = xstate_bv;
782511b0 3484 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3485 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3486
3487 /*
3488 * Copy each region from the non-compacted offset to the
3489 * possibly compacted offset.
3490 */
d91cab78 3491 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3492 while (valid) {
3493 u64 feature = valid & -valid;
3494 int index = fls64(feature) - 1;
3495 void *dest = get_xsave_addr(xsave, feature);
3496
3497 if (dest) {
3498 u32 size, offset, ecx, edx;
3499 cpuid_count(XSTATE_CPUID, index,
3500 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3501 if (feature == XFEATURE_MASK_PKRU)
3502 memcpy(&vcpu->arch.pkru, src + offset,
3503 sizeof(vcpu->arch.pkru));
3504 else
3505 memcpy(dest, src + offset, size);
ee4100da 3506 }
df1daba7
PB		 3507
3508 valid -= feature;
3509 }
3510}
3511
2d5b5a66
SY		 3512static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3513 struct kvm_xsave *guest_xsave)
3514{
d366bf7e 3515 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3516 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3517 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3518 } else {
2d5b5a66 3519 memcpy(guest_xsave->region,
7366ed77 3520 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3521 sizeof(struct fxregs_state));
2d5b5a66 3522 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3523 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3524 }
3525}
3526
a575813b
WL		 3527#define XSAVE_MXCSR_OFFSET 24
3528
2d5b5a66
SY		 3529static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3530 struct kvm_xsave *guest_xsave)
3531{
3532 u64 xstate_bv =
3533 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3534 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3535
d366bf7e 3536 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3537 /*
3538 * Here we allow setting states that are not present in
3539 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3540 * with old userspace.
3541 */
a575813b
WL		 3542 if (xstate_bv & ~kvm_supported_xcr0() ||
3543 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3544 return -EINVAL;
df1daba7 3545 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3546 } else {
a575813b
WL		 3547 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3548 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3549 return -EINVAL;
7366ed77 3550 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3551 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3552 }
3553 return 0;
3554}
3555
3556static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3557 struct kvm_xcrs *guest_xcrs)
3558{
d366bf7e 3559 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3560 guest_xcrs->nr_xcrs = 0;
3561 return;
3562 }
3563
3564 guest_xcrs->nr_xcrs = 1;
3565 guest_xcrs->flags = 0;
3566 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3567 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3568}
3569
3570static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3571 struct kvm_xcrs *guest_xcrs)
3572{
3573 int i, r = 0;
3574
d366bf7e 3575 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3576 return -EINVAL;
3577
3578 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3579 return -EINVAL;
3580
3581 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3582 /* Only support XCR0 currently */
c67a04cb 3583 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3584 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3585 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3586 break;
3587 }
3588 if (r)
3589 r = -EINVAL;
3590 return r;
3591}
3592
1c0b28c2
EM		 3593/*
3594 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3595 * stopped by the hypervisor. This function will be called from the host only.
3596 * EINVAL is returned when the host attempts to set the flag for a guest that
3597 * does not support pv clocks.
3598 */
3599static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3600{
0b79459b 3601 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3602 return -EINVAL;
51d59c6b 3603 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3604 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3605 return 0;
3606}
3607
5c919412
AS		 3608static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3609 struct kvm_enable_cap *cap)
3610{
3611 if (cap->flags)
3612 return -EINVAL;
3613
3614 switch (cap->cap) {
efc479e6
RK		 3615 case KVM_CAP_HYPERV_SYNIC2:
3616 if (cap->args[0])
3617 return -EINVAL;
5c919412 3618 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3619 if (!irqchip_in_kernel(vcpu->kvm))
3620 return -EINVAL;
efc479e6
RK		 3621 return kvm_hv_activate_synic(vcpu, cap->cap ==
3622 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3623 default:
3624 return -EINVAL;
3625 }
3626}
3627
313a3dc7
CO		 3628long kvm_arch_vcpu_ioctl(struct file *filp,
3629 unsigned int ioctl, unsigned long arg)
3630{
3631 struct kvm_vcpu *vcpu = filp->private_data;
3632 void __user *argp = (void __user *)arg;
3633 int r;
d1ac91d8
AK		 3634 union {
3635 struct kvm_lapic_state *lapic;
3636 struct kvm_xsave *xsave;
3637 struct kvm_xcrs *xcrs;
3638 void *buffer;
3639 } u;
3640
9b062471
CD		 3641 vcpu_load(vcpu);
3642
d1ac91d8 3643 u.buffer = NULL;
313a3dc7
CO		 3644 switch (ioctl) {
3645 case KVM_GET_LAPIC: {
2204ae3c 3646 r = -EINVAL;
bce87cce 3647 if (!lapic_in_kernel(vcpu))
2204ae3c 3648 goto out;
d1ac91d8 3649 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3650
b772ff36 3651 r = -ENOMEM;
d1ac91d8 3652 if (!u.lapic)
b772ff36 3653 goto out;
d1ac91d8 3654 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3655 if (r)
3656 goto out;
3657 r = -EFAULT;
d1ac91d8 3658 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3659 goto out;
3660 r = 0;
3661 break;
3662 }
3663 case KVM_SET_LAPIC: {
2204ae3c 3664 r = -EINVAL;
bce87cce 3665 if (!lapic_in_kernel(vcpu))
2204ae3c 3666 goto out;
ff5c2c03 3667 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3668 if (IS_ERR(u.lapic)) {
3669 r = PTR_ERR(u.lapic);
3670 goto out_nofree;
3671 }
ff5c2c03 3672
d1ac91d8 3673 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3674 break;
3675 }
f77bc6a4
ZX		 3676 case KVM_INTERRUPT: {
3677 struct kvm_interrupt irq;
3678
3679 r = -EFAULT;
3680 if (copy_from_user(&irq, argp, sizeof irq))
3681 goto out;
3682 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3683 break;
3684 }
c4abb7c9
JK		 3685 case KVM_NMI: {
3686 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3687 break;
3688 }
f077825a
PB		 3689 case KVM_SMI: {
3690 r = kvm_vcpu_ioctl_smi(vcpu);
3691 break;
3692 }
313a3dc7
CO		 3693 case KVM_SET_CPUID: {
3694 struct kvm_cpuid __user *cpuid_arg = argp;
3695 struct kvm_cpuid cpuid;
3696
3697 r = -EFAULT;
3698 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3699 goto out;
3700 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3701 break;
3702 }
07716717
DK		 3703 case KVM_SET_CPUID2: {
3704 struct kvm_cpuid2 __user *cpuid_arg = argp;
3705 struct kvm_cpuid2 cpuid;
3706
3707 r = -EFAULT;
3708 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3709 goto out;
3710 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3711 cpuid_arg->entries);
07716717
DK		 3712 break;
3713 }
3714 case KVM_GET_CPUID2: {
3715 struct kvm_cpuid2 __user *cpuid_arg = argp;
3716 struct kvm_cpuid2 cpuid;
3717
3718 r = -EFAULT;
3719 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3720 goto out;
3721 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3722 cpuid_arg->entries);
07716717
DK		 3723 if (r)
3724 goto out;
3725 r = -EFAULT;
3726 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3727 goto out;
3728 r = 0;
3729 break;
3730 }
801e459a
TL		 3731 case KVM_GET_MSRS: {
3732 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 3733 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 3734 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3735 break;
801e459a
TL		 3736 }
3737 case KVM_SET_MSRS: {
3738 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 3739 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 3740 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3741 break;
801e459a 3742 }
b209749f
AK		 3743 case KVM_TPR_ACCESS_REPORTING: {
3744 struct kvm_tpr_access_ctl tac;
3745
3746 r = -EFAULT;
3747 if (copy_from_user(&tac, argp, sizeof tac))
3748 goto out;
3749 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3750 if (r)
3751 goto out;
3752 r = -EFAULT;
3753 if (copy_to_user(argp, &tac, sizeof tac))
3754 goto out;
3755 r = 0;
3756 break;
3757 };
b93463aa
AK		 3758 case KVM_SET_VAPIC_ADDR: {
3759 struct kvm_vapic_addr va;
7301d6ab 3760 int idx;
b93463aa
AK		 3761
3762 r = -EINVAL;
35754c98 3763 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3764 goto out;
3765 r = -EFAULT;
3766 if (copy_from_user(&va, argp, sizeof va))
3767 goto out;
7301d6ab 3768 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3769 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3770 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3771 break;
3772 }
890ca9ae
HY		 3773 case KVM_X86_SETUP_MCE: {
3774 u64 mcg_cap;
3775
3776 r = -EFAULT;
3777 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3778 goto out;
3779 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3780 break;
3781 }
3782 case KVM_X86_SET_MCE: {
3783 struct kvm_x86_mce mce;
3784
3785 r = -EFAULT;
3786 if (copy_from_user(&mce, argp, sizeof mce))
3787 goto out;
3788 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3789 break;
3790 }
3cfc3092
JK		 3791 case KVM_GET_VCPU_EVENTS: {
3792 struct kvm_vcpu_events events;
3793
3794 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3795
3796 r = -EFAULT;
3797 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3798 break;
3799 r = 0;
3800 break;
3801 }
3802 case KVM_SET_VCPU_EVENTS: {
3803 struct kvm_vcpu_events events;
3804
3805 r = -EFAULT;
3806 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3807 break;
3808
3809 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3810 break;
3811 }
a1efbe77
JK		 3812 case KVM_GET_DEBUGREGS: {
3813 struct kvm_debugregs dbgregs;
3814
3815 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3816
3817 r = -EFAULT;
3818 if (copy_to_user(argp, &dbgregs,
3819 sizeof(struct kvm_debugregs)))
3820 break;
3821 r = 0;
3822 break;
3823 }
3824 case KVM_SET_DEBUGREGS: {
3825 struct kvm_debugregs dbgregs;
3826
3827 r = -EFAULT;
3828 if (copy_from_user(&dbgregs, argp,
3829 sizeof(struct kvm_debugregs)))
3830 break;
3831
3832 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3833 break;
3834 }
2d5b5a66 3835 case KVM_GET_XSAVE: {
d1ac91d8 3836 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3837 r = -ENOMEM;
d1ac91d8 3838 if (!u.xsave)
2d5b5a66
SY		 3839 break;
3840
d1ac91d8 3841 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3842
3843 r = -EFAULT;
d1ac91d8 3844 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3845 break;
3846 r = 0;
3847 break;
3848 }
3849 case KVM_SET_XSAVE: {
ff5c2c03 3850 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 3851 if (IS_ERR(u.xsave)) {
3852 r = PTR_ERR(u.xsave);
3853 goto out_nofree;
3854 }
2d5b5a66 3855
d1ac91d8 3856 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3857 break;
3858 }
3859 case KVM_GET_XCRS: {
d1ac91d8 3860 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3861 r = -ENOMEM;
d1ac91d8 3862 if (!u.xcrs)
2d5b5a66
SY		 3863 break;
3864
d1ac91d8 3865 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3866
3867 r = -EFAULT;
d1ac91d8 3868 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3869 sizeof(struct kvm_xcrs)))
3870 break;
3871 r = 0;
3872 break;
3873 }
3874 case KVM_SET_XCRS: {
ff5c2c03 3875 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 3876 if (IS_ERR(u.xcrs)) {
3877 r = PTR_ERR(u.xcrs);
3878 goto out_nofree;
3879 }
2d5b5a66 3880
d1ac91d8 3881 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3882 break;
3883 }
92a1f12d
JR		 3884 case KVM_SET_TSC_KHZ: {
3885 u32 user_tsc_khz;
3886
3887 r = -EINVAL;
92a1f12d
JR		 3888 user_tsc_khz = (u32)arg;
3889
3890 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3891 goto out;
3892
cc578287
ZA		 3893 if (user_tsc_khz == 0)
3894 user_tsc_khz = tsc_khz;
3895
381d585c
HZ		 3896 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3897 r = 0;
92a1f12d 3898
92a1f12d
JR		 3899 goto out;
3900 }
3901 case KVM_GET_TSC_KHZ: {
cc578287 3902 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3903 goto out;
3904 }
1c0b28c2
EM		 3905 case KVM_KVMCLOCK_CTRL: {
3906 r = kvm_set_guest_paused(vcpu);
3907 goto out;
3908 }
5c919412
AS		 3909 case KVM_ENABLE_CAP: {
3910 struct kvm_enable_cap cap;
3911
3912 r = -EFAULT;
3913 if (copy_from_user(&cap, argp, sizeof(cap)))
3914 goto out;
3915 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3916 break;
3917 }
313a3dc7
CO		 3918 default:
3919 r = -EINVAL;
3920 }
3921out:
d1ac91d8 3922 kfree(u.buffer);
9b062471
CD		 3923out_nofree:
3924 vcpu_put(vcpu);
313a3dc7
CO		 3925 return r;
3926}
3927
5b1c1493
CO		 3928int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3929{
3930 return VM_FAULT_SIGBUS;
3931}
3932
1fe779f8
CO		 3933static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3934{
3935 int ret;
3936
3937 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3938 return -EINVAL;
1fe779f8
CO		 3939 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3940 return ret;
3941}
3942
b927a3ce
SY		 3943static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3944 u64 ident_addr)
3945{
3946 kvm->arch.ept_identity_map_addr = ident_addr;
3947 return 0;
3948}
3949
1fe779f8
CO		 3950static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3951 u32 kvm_nr_mmu_pages)
3952{
3953 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3954 return -EINVAL;
3955
79fac95e 3956 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3957
3958 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3959 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3960
79fac95e 3961 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3962 return 0;
3963}
3964
3965static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3966{
39de71ec 3967 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3968}
3969
1fe779f8
CO		 3970static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3971{
90bca052 3972 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3973 int r;
3974
3975 r = 0;
3976 switch (chip->chip_id) {
3977 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3978 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3979 sizeof(struct kvm_pic_state));
3980 break;
3981 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3982 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 3983 sizeof(struct kvm_pic_state));
3984 break;
3985 case KVM_IRQCHIP_IOAPIC:
33392b49 3986 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3987 break;
3988 default:
3989 r = -EINVAL;
3990 break;
3991 }
3992 return r;
3993}
3994
3995static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3996{
90bca052 3997 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3998 int r;
3999
4000 r = 0;
4001 switch (chip->chip_id) {
4002 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4003 spin_lock(&pic->lock);
4004 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4005 sizeof(struct kvm_pic_state));
90bca052 4006 spin_unlock(&pic->lock);
1fe779f8
CO		 4007 break;
4008 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4009 spin_lock(&pic->lock);
4010 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4011 sizeof(struct kvm_pic_state));
90bca052 4012 spin_unlock(&pic->lock);
1fe779f8
CO		 4013 break;
4014 case KVM_IRQCHIP_IOAPIC:
33392b49 4015 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4016 break;
4017 default:
4018 r = -EINVAL;
4019 break;
4020 }
90bca052 4021 kvm_pic_update_irq(pic);
1fe779f8
CO		 4022 return r;
4023}
4024
e0f63cb9
SY		 4025static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4026{
34f3941c
RK		 4027 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4028
4029 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4030
4031 mutex_lock(&kps->lock);
4032 memcpy(ps, &kps->channels, sizeof(*ps));
4033 mutex_unlock(&kps->lock);
2da29bcc 4034 return 0;
e0f63cb9
SY		 4035}
4036
4037static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4038{
0185604c 4039 int i;
09edea72
RK		 4040 struct kvm_pit *pit = kvm->arch.vpit;
4041
4042 mutex_lock(&pit->pit_state.lock);
34f3941c 4043 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4044 for (i = 0; i < 3; i++)
09edea72
RK		 4045 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4046 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4047 return 0;
e9f42757
BK		 4048}
4049
4050static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4051{
e9f42757
BK		 4052 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4053 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4054 sizeof(ps->channels));
4055 ps->flags = kvm->arch.vpit->pit_state.flags;
4056 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4057 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4058 return 0;
e9f42757
BK		 4059}
4060
4061static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4062{
2da29bcc 4063 int start = 0;
0185604c 4064 int i;
e9f42757 4065 u32 prev_legacy, cur_legacy;
09edea72
RK		 4066 struct kvm_pit *pit = kvm->arch.vpit;
4067
4068 mutex_lock(&pit->pit_state.lock);
4069 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4070 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4071 if (!prev_legacy && cur_legacy)
4072 start = 1;
09edea72
RK		 4073 memcpy(&pit->pit_state.channels, &ps->channels,
4074 sizeof(pit->pit_state.channels));
4075 pit->pit_state.flags = ps->flags;
0185604c 4076 for (i = 0; i < 3; i++)
09edea72 4077 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4078 start && i == 0);
09edea72 4079 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4080 return 0;
e0f63cb9
SY		 4081}
4082
52d939a0
MT		 4083static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4084 struct kvm_reinject_control *control)
4085{
71474e2f
RK		 4086 struct kvm_pit *pit = kvm->arch.vpit;
4087
4088 if (!pit)
52d939a0 4089 return -ENXIO;
b39c90b6 4090
71474e2f
RK		 4091 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4092 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4093 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4094 */
4095 mutex_lock(&pit->pit_state.lock);
4096 kvm_pit_set_reinject(pit, control->pit_reinject);
4097 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4098
52d939a0
MT		 4099 return 0;
4100}
4101
95d4c16c 4102/**
60c34612
TY		 4103 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4104 * @kvm: kvm instance
4105 * @log: slot id and address to which we copy the log
95d4c16c 4106 *
e108ff2f
PB		 4107 * Steps 1-4 below provide general overview of dirty page logging. See
4108 * kvm_get_dirty_log_protect() function description for additional details.
4109 *
4110 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4111 * always flush the TLB (step 4) even if previous step failed and the dirty
4112 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4113 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4114 * writes will be marked dirty for next log read.
95d4c16c 4115 *
60c34612
TY		 4116 * 1. Take a snapshot of the bit and clear it if needed.
4117 * 2. Write protect the corresponding page.
e108ff2f
PB		 4118 * 3. Copy the snapshot to the userspace.
4119 * 4. Flush TLB's if needed.
5bb064dc 4120 */
60c34612 4121int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4122{
60c34612 4123 bool is_dirty = false;
e108ff2f 4124 int r;
5bb064dc 4125
79fac95e 4126 mutex_lock(&kvm->slots_lock);
5bb064dc 4127
88178fd4
KH		 4128 /*
4129 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4130 */
4131 if (kvm_x86_ops->flush_log_dirty)
4132 kvm_x86_ops->flush_log_dirty(kvm);
4133
e108ff2f 4134 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 4135
4136 /*
4137 * All the TLBs can be flushed out of mmu lock, see the comments in
4138 * kvm_mmu_slot_remove_write_access().
4139 */
e108ff2f 4140 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 4141 if (is_dirty)
4142 kvm_flush_remote_tlbs(kvm);
4143
79fac95e 4144 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4145 return r;
4146}
4147
aa2fbe6d
YZ		 4148int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4149 bool line_status)
23d43cf9
CD		 4150{
4151 if (!irqchip_in_kernel(kvm))
4152 return -ENXIO;
4153
4154 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4155 irq_event->irq, irq_event->level,
4156 line_status);
23d43cf9
CD		 4157 return 0;
4158}
4159
90de4a18
NA		 4160static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4161 struct kvm_enable_cap *cap)
4162{
4163 int r;
4164
4165 if (cap->flags)
4166 return -EINVAL;
4167
4168 switch (cap->cap) {
4169 case KVM_CAP_DISABLE_QUIRKS:
4170 kvm->arch.disabled_quirks = cap->args[0];
4171 r = 0;
4172 break;
49df6397
SR		 4173 case KVM_CAP_SPLIT_IRQCHIP: {
4174 mutex_lock(&kvm->lock);
b053b2ae
SR		 4175 r = -EINVAL;
4176 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4177 goto split_irqchip_unlock;
49df6397
SR		 4178 r = -EEXIST;
4179 if (irqchip_in_kernel(kvm))
4180 goto split_irqchip_unlock;
557abc40 4181 if (kvm->created_vcpus)
49df6397
SR		 4182 goto split_irqchip_unlock;
4183 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4184 if (r)
49df6397
SR		 4185 goto split_irqchip_unlock;
4186 /* Pairs with irqchip_in_kernel. */
4187 smp_wmb();
49776faf 4188 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4189 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4190 r = 0;
4191split_irqchip_unlock:
4192 mutex_unlock(&kvm->lock);
4193 break;
4194 }
37131313
RK		 4195 case KVM_CAP_X2APIC_API:
4196 r = -EINVAL;
4197 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4198 break;
4199
4200 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4201 kvm->arch.x2apic_format = true;
c519265f
RK		 4202 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4203 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4204
4205 r = 0;
4206 break;
90de4a18
NA		 4207 default:
4208 r = -EINVAL;
4209 break;
4210 }
4211 return r;
4212}
4213
1fe779f8
CO		 4214long kvm_arch_vm_ioctl(struct file *filp,
4215 unsigned int ioctl, unsigned long arg)
4216{
4217 struct kvm *kvm = filp->private_data;
4218 void __user *argp = (void __user *)arg;
367e1319 4219 int r = -ENOTTY;
f0d66275
DH		 4220 /*
4221 * This union makes it completely explicit to gcc-3.x
4222 * that these two variables' stack usage should be
4223 * combined, not added together.
4224 */
4225 union {
4226 struct kvm_pit_state ps;
e9f42757 4227 struct kvm_pit_state2 ps2;
c5ff41ce 4228 struct kvm_pit_config pit_config;
f0d66275 4229 } u;
1fe779f8
CO		 4230
4231 switch (ioctl) {
4232 case KVM_SET_TSS_ADDR:
4233 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4234 break;
b927a3ce
SY		 4235 case KVM_SET_IDENTITY_MAP_ADDR: {
4236 u64 ident_addr;
4237
1af1ac91
DH		 4238 mutex_lock(&kvm->lock);
4239 r = -EINVAL;
4240 if (kvm->created_vcpus)
4241 goto set_identity_unlock;
b927a3ce
SY		 4242 r = -EFAULT;
4243 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4244 goto set_identity_unlock;
b927a3ce 4245 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4246set_identity_unlock:
4247 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4248 break;
4249 }
1fe779f8
CO		 4250 case KVM_SET_NR_MMU_PAGES:
4251 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4252 break;
4253 case KVM_GET_NR_MMU_PAGES:
4254 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4255 break;
3ddea128 4256 case KVM_CREATE_IRQCHIP: {
3ddea128 4257 mutex_lock(&kvm->lock);
09941366 4258
3ddea128 4259 r = -EEXIST;
35e6eaa3 4260 if (irqchip_in_kernel(kvm))
3ddea128 4261 goto create_irqchip_unlock;
09941366 4262
3e515705 4263 r = -EINVAL;
557abc40 4264 if (kvm->created_vcpus)
3e515705 4265 goto create_irqchip_unlock;
09941366
RK		 4266
4267 r = kvm_pic_init(kvm);
4268 if (r)
3ddea128 4269 goto create_irqchip_unlock;
09941366
RK		 4270
4271 r = kvm_ioapic_init(kvm);
4272 if (r) {
09941366 4273 kvm_pic_destroy(kvm);
3ddea128 4274 goto create_irqchip_unlock;
09941366
RK		 4275 }
4276
399ec807
AK		 4277 r = kvm_setup_default_irq_routing(kvm);
4278 if (r) {
72bb2fcd 4279 kvm_ioapic_destroy(kvm);
09941366 4280 kvm_pic_destroy(kvm);
71ba994c 4281 goto create_irqchip_unlock;
399ec807 4282 }
49776faf 4283 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4284 smp_wmb();
49776faf 4285 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4286 create_irqchip_unlock:
4287 mutex_unlock(&kvm->lock);
1fe779f8 4288 break;
3ddea128 4289 }
7837699f 4290 case KVM_CREATE_PIT:
c5ff41ce
JK		 4291 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4292 goto create_pit;
4293 case KVM_CREATE_PIT2:
4294 r = -EFAULT;
4295 if (copy_from_user(&u.pit_config, argp,
4296 sizeof(struct kvm_pit_config)))
4297 goto out;
4298 create_pit:
250715a6 4299 mutex_lock(&kvm->lock);
269e05e4
AK		 4300 r = -EEXIST;
4301 if (kvm->arch.vpit)
4302 goto create_pit_unlock;
7837699f 4303 r = -ENOMEM;
c5ff41ce 4304 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4305 if (kvm->arch.vpit)
4306 r = 0;
269e05e4 4307 create_pit_unlock:
250715a6 4308 mutex_unlock(&kvm->lock);
7837699f 4309 break;
1fe779f8
CO		 4310 case KVM_GET_IRQCHIP: {
4311 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4312 struct kvm_irqchip *chip;
1fe779f8 4313
ff5c2c03
SL		 4314 chip = memdup_user(argp, sizeof(*chip));
4315 if (IS_ERR(chip)) {
4316 r = PTR_ERR(chip);
1fe779f8 4317 goto out;
ff5c2c03
SL		 4318 }
4319
1fe779f8 4320 r = -ENXIO;
826da321 4321 if (!irqchip_kernel(kvm))
f0d66275
DH		 4322 goto get_irqchip_out;
4323 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4324 if (r)
f0d66275 4325 goto get_irqchip_out;
1fe779f8 4326 r = -EFAULT;
f0d66275
DH		 4327 if (copy_to_user(argp, chip, sizeof *chip))
4328 goto get_irqchip_out;
1fe779f8 4329 r = 0;
f0d66275
DH		 4330 get_irqchip_out:
4331 kfree(chip);
1fe779f8
CO		 4332 break;
4333 }
4334 case KVM_SET_IRQCHIP: {
4335 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4336 struct kvm_irqchip *chip;
1fe779f8 4337
ff5c2c03
SL		 4338 chip = memdup_user(argp, sizeof(*chip));
4339 if (IS_ERR(chip)) {
4340 r = PTR_ERR(chip);
1fe779f8 4341 goto out;
ff5c2c03
SL		 4342 }
4343
1fe779f8 4344 r = -ENXIO;
826da321 4345 if (!irqchip_kernel(kvm))
f0d66275
DH		 4346 goto set_irqchip_out;
4347 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4348 if (r)
f0d66275 4349 goto set_irqchip_out;
1fe779f8 4350 r = 0;
f0d66275
DH		 4351 set_irqchip_out:
4352 kfree(chip);
1fe779f8
CO		 4353 break;
4354 }
e0f63cb9 4355 case KVM_GET_PIT: {
e0f63cb9 4356 r = -EFAULT;
f0d66275 4357 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4358 goto out;
4359 r = -ENXIO;
4360 if (!kvm->arch.vpit)
4361 goto out;
f0d66275 4362 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4363 if (r)
4364 goto out;
4365 r = -EFAULT;
f0d66275 4366 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4367 goto out;
4368 r = 0;
4369 break;
4370 }
4371 case KVM_SET_PIT: {
e0f63cb9 4372 r = -EFAULT;
f0d66275 4373 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4374 goto out;
4375 r = -ENXIO;
4376 if (!kvm->arch.vpit)
4377 goto out;
f0d66275 4378 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4379 break;
4380 }
e9f42757
BK		 4381 case KVM_GET_PIT2: {
4382 r = -ENXIO;
4383 if (!kvm->arch.vpit)
4384 goto out;
4385 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4386 if (r)
4387 goto out;
4388 r = -EFAULT;
4389 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4390 goto out;
4391 r = 0;
4392 break;
4393 }
4394 case KVM_SET_PIT2: {
4395 r = -EFAULT;
4396 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4397 goto out;
4398 r = -ENXIO;
4399 if (!kvm->arch.vpit)
4400 goto out;
4401 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4402 break;
4403 }
52d939a0
MT		 4404 case KVM_REINJECT_CONTROL: {
4405 struct kvm_reinject_control control;
4406 r = -EFAULT;
4407 if (copy_from_user(&control, argp, sizeof(control)))
4408 goto out;
4409 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4410 break;
4411 }
d71ba788
PB		 4412 case KVM_SET_BOOT_CPU_ID:
4413 r = 0;
4414 mutex_lock(&kvm->lock);
557abc40 4415 if (kvm->created_vcpus)
d71ba788
PB		 4416 r = -EBUSY;
4417 else
4418 kvm->arch.bsp_vcpu_id = arg;
4419 mutex_unlock(&kvm->lock);
4420 break;
ffde22ac 4421 case KVM_XEN_HVM_CONFIG: {
51776043 4422 struct kvm_xen_hvm_config xhc;
ffde22ac 4423 r = -EFAULT;
51776043 4424 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4425 goto out;
4426 r = -EINVAL;
51776043 4427 if (xhc.flags)
ffde22ac 4428 goto out;
51776043 4429 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4430 r = 0;
4431 break;
4432 }
afbcf7ab 4433 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4434 struct kvm_clock_data user_ns;
4435 u64 now_ns;
afbcf7ab
GC		 4436
4437 r = -EFAULT;
4438 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4439 goto out;
4440
4441 r = -EINVAL;
4442 if (user_ns.flags)
4443 goto out;
4444
4445 r = 0;
0bc48bea
RK		 4446 /*
4447 * TODO: userspace has to take care of races with VCPU_RUN, so
4448 * kvm_gen_update_masterclock() can be cut down to locked
4449 * pvclock_update_vm_gtod_copy().
4450 */
4451 kvm_gen_update_masterclock(kvm);
e891a32e 4452 now_ns = get_kvmclock_ns(kvm);
108b249c 4453 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4454 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4455 break;
4456 }
4457 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4458 struct kvm_clock_data user_ns;
4459 u64 now_ns;
4460
e891a32e 4461 now_ns = get_kvmclock_ns(kvm);
108b249c 4462 user_ns.clock = now_ns;
e3fd9a93 4463 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4464 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4465
4466 r = -EFAULT;
4467 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4468 goto out;
4469 r = 0;
4470 break;
4471 }
90de4a18
NA		 4472 case KVM_ENABLE_CAP: {
4473 struct kvm_enable_cap cap;
afbcf7ab 4474
90de4a18
NA		 4475 r = -EFAULT;
4476 if (copy_from_user(&cap, argp, sizeof(cap)))
4477 goto out;
4478 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4479 break;
4480 }
5acc5c06
BS		 4481 case KVM_MEMORY_ENCRYPT_OP: {
4482 r = -ENOTTY;
4483 if (kvm_x86_ops->mem_enc_op)
4484 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4485 break;
4486 }
69eaedee
BS		 4487 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4488 struct kvm_enc_region region;
4489
4490 r = -EFAULT;
4491 if (copy_from_user(&region, argp, sizeof(region)))
4492 goto out;
4493
4494 r = -ENOTTY;
4495 if (kvm_x86_ops->mem_enc_reg_region)
4496 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4497 break;
4498 }
4499 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4500 struct kvm_enc_region region;
4501
4502 r = -EFAULT;
4503 if (copy_from_user(&region, argp, sizeof(region)))
4504 goto out;
4505
4506 r = -ENOTTY;
4507 if (kvm_x86_ops->mem_enc_unreg_region)
4508 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4509 break;
4510 }
faeb7833
RK		 4511 case KVM_HYPERV_EVENTFD: {
4512 struct kvm_hyperv_eventfd hvevfd;
4513
4514 r = -EFAULT;
4515 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4516 goto out;
4517 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4518 break;
4519 }
1fe779f8 4520 default:
ad6260da 4521 r = -ENOTTY;
1fe779f8
CO		 4522 }
4523out:
4524 return r;
4525}
4526
a16b043c 4527static void kvm_init_msr_list(void)
043405e1
CO		 4528{
4529 u32 dummy[2];
4530 unsigned i, j;
4531
62ef68bb 4532 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4533 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4534 continue;
93c4adc7
PB		 4535
4536 /*
4537 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4538 * to the guests in some cases.
93c4adc7
PB		 4539 */
4540 switch (msrs_to_save[i]) {
4541 case MSR_IA32_BNDCFGS:
4542 if (!kvm_x86_ops->mpx_supported())
4543 continue;
4544 break;
9dbe6cf9
PB		 4545 case MSR_TSC_AUX:
4546 if (!kvm_x86_ops->rdtscp_supported())
4547 continue;
4548 break;
93c4adc7
PB		 4549 default:
4550 break;
4551 }
4552
043405e1
CO		 4553 if (j < i)
4554 msrs_to_save[j] = msrs_to_save[i];
4555 j++;
4556 }
4557 num_msrs_to_save = j;
62ef68bb
PB		 4558
4559 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4560 switch (emulated_msrs[i]) {
6d396b55
PB		 4561 case MSR_IA32_SMBASE:
4562 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4563 continue;
4564 break;
62ef68bb
PB		 4565 default:
4566 break;
4567 }
4568
4569 if (j < i)
4570 emulated_msrs[j] = emulated_msrs[i];
4571 j++;
4572 }
4573 num_emulated_msrs = j;
801e459a
TL		 4574
4575 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4576 struct kvm_msr_entry msr;
4577
4578 msr.index = msr_based_features[i];
66421c1e 4579 if (kvm_get_msr_feature(&msr))
801e459a
TL		 4580 continue;
4581
4582 if (j < i)
4583 msr_based_features[j] = msr_based_features[i];
4584 j++;
4585 }
4586 num_msr_based_features = j;
043405e1
CO		 4587}
4588
bda9020e
MT		 4589static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4590 const void *v)
bbd9b64e 4591{
70252a10
AK		 4592 int handled = 0;
4593 int n;
4594
4595 do {
4596 n = min(len, 8);
bce87cce 4597 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4598 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4599 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4600 break;
4601 handled += n;
4602 addr += n;
4603 len -= n;
4604 v += n;
4605 } while (len);
bbd9b64e 4606
70252a10 4607 return handled;
bbd9b64e
CO		 4608}
4609
bda9020e 4610static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4611{
70252a10
AK		 4612 int handled = 0;
4613 int n;
4614
4615 do {
4616 n = min(len, 8);
bce87cce 4617 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4618 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4619 addr, n, v))
4620 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 4621 break;
e39d200f 4622 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 4623 handled += n;
4624 addr += n;
4625 len -= n;
4626 v += n;
4627 } while (len);
bbd9b64e 4628
70252a10 4629 return handled;
bbd9b64e
CO		 4630}
4631
2dafc6c2
GN		 4632static void kvm_set_segment(struct kvm_vcpu *vcpu,
4633 struct kvm_segment *var, int seg)
4634{
4635 kvm_x86_ops->set_segment(vcpu, var, seg);
4636}
4637
4638void kvm_get_segment(struct kvm_vcpu *vcpu,
4639 struct kvm_segment *var, int seg)
4640{
4641 kvm_x86_ops->get_segment(vcpu, var, seg);
4642}
4643
54987b7a
PB		 4644gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4645 struct x86_exception *exception)
02f59dc9
JR		 4646{
4647 gpa_t t_gpa;
02f59dc9
JR		 4648
4649 BUG_ON(!mmu_is_nested(vcpu));
4650
4651 /* NPT walks are always user-walks */
4652 access |= PFERR_USER_MASK;
54987b7a 4653 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4654
4655 return t_gpa;
4656}
4657
ab9ae313
AK		 4658gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4659 struct x86_exception *exception)
1871c602
GN		 4660{
4661 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4662 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4663}
4664
ab9ae313
AK		 4665 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4666 struct x86_exception *exception)
1871c602
GN		 4667{
4668 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4669 access |= PFERR_FETCH_MASK;
ab9ae313 4670 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4671}
4672
ab9ae313
AK		 4673gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4674 struct x86_exception *exception)
1871c602
GN		 4675{
4676 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4677 access |= PFERR_WRITE_MASK;
ab9ae313 4678 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4679}
4680
4681/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4682gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4683 struct x86_exception *exception)
1871c602 4684{
ab9ae313 4685 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4686}
4687
4688static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4689 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4690 struct x86_exception *exception)
bbd9b64e
CO		 4691{
4692 void *data = val;
10589a46 4693 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4694
4695 while (bytes) {
14dfe855 4696 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4697 exception);
bbd9b64e 4698 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4699 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4700 int ret;
4701
bcc55cba 4702 if (gpa == UNMAPPED_GVA)
ab9ae313 4703 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4704 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4705 offset, toread);
10589a46 4706 if (ret < 0) {
c3cd7ffa 4707 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4708 goto out;
4709 }
bbd9b64e 4710
77c2002e
IE		 4711 bytes -= toread;
4712 data += toread;
4713 addr += toread;
bbd9b64e 4714 }
10589a46 4715out:
10589a46 4716 return r;
bbd9b64e 4717}
77c2002e 4718
1871c602 4719/* used for instruction fetching */
0f65dd70
AK		 4720static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4721 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4722 struct x86_exception *exception)
1871c602 4723{
0f65dd70 4724 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4725 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4726 unsigned offset;
4727 int ret;
0f65dd70 4728
44583cba
PB		 4729 /* Inline kvm_read_guest_virt_helper for speed. */
4730 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4731 exception);
4732 if (unlikely(gpa == UNMAPPED_GVA))
4733 return X86EMUL_PROPAGATE_FAULT;
4734
4735 offset = addr & (PAGE_SIZE-1);
4736 if (WARN_ON(offset + bytes > PAGE_SIZE))
4737 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4738 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4739 offset, bytes);
44583cba
PB		 4740 if (unlikely(ret < 0))
4741 return X86EMUL_IO_NEEDED;
4742
4743 return X86EMUL_CONTINUE;
1871c602
GN		 4744}
4745
064aea77 4746int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4747 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4748 struct x86_exception *exception)
1871c602 4749{
0f65dd70 4750 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4751 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4752
1871c602 4753 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4754 exception);
1871c602 4755}
064aea77 4756EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4757
0f65dd70
AK		 4758static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4759 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4760 struct x86_exception *exception)
1871c602 4761{
0f65dd70 4762 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4763 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4764}
4765
7a036a6f
RK		 4766static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4767 unsigned long addr, void *val, unsigned int bytes)
4768{
4769 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4770 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4771
4772 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4773}
4774
6a4d7550 4775int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4776 gva_t addr, void *val,
2dafc6c2 4777 unsigned int bytes,
bcc55cba 4778 struct x86_exception *exception)
77c2002e 4779{
0f65dd70 4780 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4781 void *data = val;
4782 int r = X86EMUL_CONTINUE;
4783
4784 while (bytes) {
14dfe855
JR		 4785 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4786 PFERR_WRITE_MASK,
ab9ae313 4787 exception);
77c2002e
IE		 4788 unsigned offset = addr & (PAGE_SIZE-1);
4789 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4790 int ret;
4791
bcc55cba 4792 if (gpa == UNMAPPED_GVA)
ab9ae313 4793 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4794 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4795 if (ret < 0) {
c3cd7ffa 4796 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4797 goto out;
4798 }
4799
4800 bytes -= towrite;
4801 data += towrite;
4802 addr += towrite;
4803 }
4804out:
4805 return r;
4806}
6a4d7550 4807EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4808
0f89b207
TL		 4809static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4810 gpa_t gpa, bool write)
4811{
4812 /* For APIC access vmexit */
4813 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4814 return 1;
4815
4816 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4817 trace_vcpu_match_mmio(gva, gpa, write, true);
4818 return 1;
4819 }
4820
4821 return 0;
4822}
4823
af7cc7d1
XG		 4824static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4825 gpa_t *gpa, struct x86_exception *exception,
4826 bool write)
4827{
97d64b78
AK		 4828 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4829 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4830
be94f6b7
HH		 4831 /*
4832 * currently PKRU is only applied to ept enabled guest so
4833 * there is no pkey in EPT page table for L1 guest or EPT
4834 * shadow page table for L2 guest.
4835 */
97d64b78 4836 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4837 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4838 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4839 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4840 (gva & (PAGE_SIZE - 1));
4f022648 4841 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4842 return 1;
4843 }
4844
af7cc7d1
XG		 4845 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4846
4847 if (*gpa == UNMAPPED_GVA)
4848 return -1;
4849
0f89b207 4850 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4851}
4852
3200f405 4853int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4854 const void *val, int bytes)
bbd9b64e
CO		 4855{
4856 int ret;
4857
54bf36aa 4858 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4859 if (ret < 0)
bbd9b64e 4860 return 0;
0eb05bf2 4861 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4862 return 1;
4863}
4864
77d197b2
XG		 4865struct read_write_emulator_ops {
4866 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4867 int bytes);
4868 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4869 void *val, int bytes);
4870 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4871 int bytes, void *val);
4872 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4873 void *val, int bytes);
4874 bool write;
4875};
4876
4877static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4878{
4879 if (vcpu->mmio_read_completed) {
77d197b2 4880 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 4881 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 4882 vcpu->mmio_read_completed = 0;
4883 return 1;
4884 }
4885
4886 return 0;
4887}
4888
4889static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4890 void *val, int bytes)
4891{
54bf36aa 4892 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4893}
4894
4895static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4896 void *val, int bytes)
4897{
4898 return emulator_write_phys(vcpu, gpa, val, bytes);
4899}
4900
4901static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4902{
e39d200f 4903 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 4904 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4905}
4906
4907static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4908 void *val, int bytes)
4909{
e39d200f 4910 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 4911 return X86EMUL_IO_NEEDED;
4912}
4913
4914static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4915 void *val, int bytes)
4916{
f78146b0
AK		 4917 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4918
87da7e66 4919 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4920 return X86EMUL_CONTINUE;
4921}
4922
0fbe9b0b 4923static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4924 .read_write_prepare = read_prepare,
4925 .read_write_emulate = read_emulate,
4926 .read_write_mmio = vcpu_mmio_read,
4927 .read_write_exit_mmio = read_exit_mmio,
4928};
4929
0fbe9b0b 4930static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4931 .read_write_emulate = write_emulate,
4932 .read_write_mmio = write_mmio,
4933 .read_write_exit_mmio = write_exit_mmio,
4934 .write = true,
4935};
4936
22388a3c
XG		 4937static int emulator_read_write_onepage(unsigned long addr, void *val,
4938 unsigned int bytes,
4939 struct x86_exception *exception,
4940 struct kvm_vcpu *vcpu,
0fbe9b0b 4941 const struct read_write_emulator_ops *ops)
bbd9b64e 4942{
af7cc7d1
XG		 4943 gpa_t gpa;
4944 int handled, ret;
22388a3c 4945 bool write = ops->write;
f78146b0 4946 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4947 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4948
4949 /*
4950 * If the exit was due to a NPF we may already have a GPA.
4951 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4952 * Note, this cannot be used on string operations since string
4953 * operation using rep will only have the initial GPA from the NPF
4954 * occurred.
4955 */
4956 if (vcpu->arch.gpa_available &&
4957 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 4958 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
4959 gpa = vcpu->arch.gpa_val;
4960 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
4961 } else {
4962 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4963 if (ret < 0)
4964 return X86EMUL_PROPAGATE_FAULT;
0f89b207 4965 }
10589a46 4966
618232e2 4967 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4968 return X86EMUL_CONTINUE;
4969
bbd9b64e
CO		 4970 /*
4971 * Is this MMIO handled locally?
4972 */
22388a3c 4973 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4974 if (handled == bytes)
bbd9b64e 4975 return X86EMUL_CONTINUE;
bbd9b64e 4976
70252a10
AK		 4977 gpa += handled;
4978 bytes -= handled;
4979 val += handled;
4980
87da7e66
XG		 4981 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4982 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4983 frag->gpa = gpa;
4984 frag->data = val;
4985 frag->len = bytes;
f78146b0 4986 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4987}
4988
52eb5a6d
XL		 4989static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4990 unsigned long addr,
22388a3c
XG		 4991 void *val, unsigned int bytes,
4992 struct x86_exception *exception,
0fbe9b0b 4993 const struct read_write_emulator_ops *ops)
bbd9b64e 4994{
0f65dd70 4995 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4996 gpa_t gpa;
4997 int rc;
4998
4999 if (ops->read_write_prepare &&
5000 ops->read_write_prepare(vcpu, val, bytes))
5001 return X86EMUL_CONTINUE;
5002
5003 vcpu->mmio_nr_fragments = 0;
0f65dd70 5004
bbd9b64e
CO		 5005 /* Crossing a page boundary? */
5006 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5007 int now;
bbd9b64e
CO		 5008
5009 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5010 rc = emulator_read_write_onepage(addr, val, now, exception,
5011 vcpu, ops);
5012
bbd9b64e
CO		 5013 if (rc != X86EMUL_CONTINUE)
5014 return rc;
5015 addr += now;
bac15531
NA		 5016 if (ctxt->mode != X86EMUL_MODE_PROT64)
5017 addr = (u32)addr;
bbd9b64e
CO		 5018 val += now;
5019 bytes -= now;
5020 }
22388a3c 5021
f78146b0
AK		 5022 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5023 vcpu, ops);
5024 if (rc != X86EMUL_CONTINUE)
5025 return rc;
5026
5027 if (!vcpu->mmio_nr_fragments)
5028 return rc;
5029
5030 gpa = vcpu->mmio_fragments[0].gpa;
5031
5032 vcpu->mmio_needed = 1;
5033 vcpu->mmio_cur_fragment = 0;
5034
87da7e66 5035 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5036 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5037 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5038 vcpu->run->mmio.phys_addr = gpa;
5039
5040 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5041}
5042
5043static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5044 unsigned long addr,
5045 void *val,
5046 unsigned int bytes,
5047 struct x86_exception *exception)
5048{
5049 return emulator_read_write(ctxt, addr, val, bytes,
5050 exception, &read_emultor);
5051}
5052
52eb5a6d 5053static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5054 unsigned long addr,
5055 const void *val,
5056 unsigned int bytes,
5057 struct x86_exception *exception)
5058{
5059 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5060 exception, &write_emultor);
bbd9b64e 5061}
bbd9b64e 5062
daea3e73
AK		 5063#define CMPXCHG_TYPE(t, ptr, old, new) \
5064 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5065
5066#ifdef CONFIG_X86_64
5067# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5068#else
5069# define CMPXCHG64(ptr, old, new) \
9749a6c0 5070 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5071#endif
5072
0f65dd70
AK		 5073static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5074 unsigned long addr,
bbd9b64e
CO		 5075 const void *old,
5076 const void *new,
5077 unsigned int bytes,
0f65dd70 5078 struct x86_exception *exception)
bbd9b64e 5079{
0f65dd70 5080 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 5081 gpa_t gpa;
5082 struct page *page;
5083 char *kaddr;
5084 bool exchanged;
2bacc55c 5085
daea3e73
AK		 5086 /* guests cmpxchg8b have to be emulated atomically */
5087 if (bytes > 8 || (bytes & (bytes - 1)))
5088 goto emul_write;
10589a46 5089
daea3e73 5090 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5091
daea3e73
AK		 5092 if (gpa == UNMAPPED_GVA ||
5093 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5094 goto emul_write;
2bacc55c 5095
daea3e73
AK		 5096 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5097 goto emul_write;
72dc67a6 5098
54bf36aa 5099 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 5100 if (is_error_page(page))
c19b8bd6 5101 goto emul_write;
72dc67a6 5102
8fd75e12 5103 kaddr = kmap_atomic(page);
daea3e73
AK		 5104 kaddr += offset_in_page(gpa);
5105 switch (bytes) {
5106 case 1:
5107 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5108 break;
5109 case 2:
5110 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5111 break;
5112 case 4:
5113 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5114 break;
5115 case 8:
5116 exchanged = CMPXCHG64(kaddr, old, new);
5117 break;
5118 default:
5119 BUG();
2bacc55c 5120 }
8fd75e12 5121 kunmap_atomic(kaddr);
daea3e73
AK		 5122 kvm_release_page_dirty(page);
5123
5124 if (!exchanged)
5125 return X86EMUL_CMPXCHG_FAILED;
5126
54bf36aa 5127 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 5128 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5129
5130 return X86EMUL_CONTINUE;
4a5f48f6 5131
3200f405 5132emul_write:
daea3e73 5133 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5134
0f65dd70 5135 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5136}
5137
cf8f70bf
GN		 5138static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5139{
cbfc6c91 5140 int r = 0, i;
cf8f70bf 5141
cbfc6c91
WL		 5142 for (i = 0; i < vcpu->arch.pio.count; i++) {
5143 if (vcpu->arch.pio.in)
5144 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5145 vcpu->arch.pio.size, pd);
5146 else
5147 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5148 vcpu->arch.pio.port, vcpu->arch.pio.size,
5149 pd);
5150 if (r)
5151 break;
5152 pd += vcpu->arch.pio.size;
5153 }
cf8f70bf
GN		 5154 return r;
5155}
5156
6f6fbe98
XG		 5157static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5158 unsigned short port, void *val,
5159 unsigned int count, bool in)
cf8f70bf 5160{
cf8f70bf 5161 vcpu->arch.pio.port = port;
6f6fbe98 5162 vcpu->arch.pio.in = in;
7972995b 5163 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5164 vcpu->arch.pio.size = size;
5165
5166 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5167 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5168 return 1;
5169 }
5170
5171 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5172 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5173 vcpu->run->io.size = size;
5174 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5175 vcpu->run->io.count = count;
5176 vcpu->run->io.port = port;
5177
5178 return 0;
5179}
5180
6f6fbe98
XG		 5181static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5182 int size, unsigned short port, void *val,
5183 unsigned int count)
cf8f70bf 5184{
ca1d4a9e 5185 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5186 int ret;
ca1d4a9e 5187
6f6fbe98
XG		 5188 if (vcpu->arch.pio.count)
5189 goto data_avail;
cf8f70bf 5190
cbfc6c91
WL		 5191 memset(vcpu->arch.pio_data, 0, size * count);
5192
6f6fbe98
XG		 5193 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5194 if (ret) {
5195data_avail:
5196 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5197 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5198 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5199 return 1;
5200 }
5201
cf8f70bf
GN		 5202 return 0;
5203}
5204
6f6fbe98
XG		 5205static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5206 int size, unsigned short port,
5207 const void *val, unsigned int count)
5208{
5209 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5210
5211 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5212 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5213 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5214}
5215
bbd9b64e
CO		 5216static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5217{
5218 return kvm_x86_ops->get_segment_base(vcpu, seg);
5219}
5220
3cb16fe7 5221static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5222{
3cb16fe7 5223 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5224}
5225
ae6a2375 5226static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5227{
5228 if (!need_emulate_wbinvd(vcpu))
5229 return X86EMUL_CONTINUE;
5230
5231 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5232 int cpu = get_cpu();
5233
5234 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5235 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5236 wbinvd_ipi, NULL, 1);
2eec7343 5237 put_cpu();
f5f48ee1 5238 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5239 } else
5240 wbinvd();
f5f48ee1
SY		 5241 return X86EMUL_CONTINUE;
5242}
5cb56059
JS		 5243
5244int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5245{
6affcbed
KH		 5246 kvm_emulate_wbinvd_noskip(vcpu);
5247 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5248}
f5f48ee1
SY		 5249EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5250
5cb56059
JS		 5251
5252
bcaf5cc5
AK		 5253static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5254{
5cb56059 5255 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5256}
5257
52eb5a6d
XL		 5258static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5259 unsigned long *dest)
bbd9b64e 5260{
16f8a6f9 5261 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5262}
5263
52eb5a6d
XL		 5264static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5265 unsigned long value)
bbd9b64e 5266{
338dbc97 5267
717746e3 5268 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5269}
5270
52a46617 5271static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5272{
52a46617 5273 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5274}
5275
717746e3 5276static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5277{
717746e3 5278 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5279 unsigned long value;
5280
5281 switch (cr) {
5282 case 0:
5283 value = kvm_read_cr0(vcpu);
5284 break;
5285 case 2:
5286 value = vcpu->arch.cr2;
5287 break;
5288 case 3:
9f8fe504 5289 value = kvm_read_cr3(vcpu);
52a46617
GN		 5290 break;
5291 case 4:
5292 value = kvm_read_cr4(vcpu);
5293 break;
5294 case 8:
5295 value = kvm_get_cr8(vcpu);
5296 break;
5297 default:
a737f256 5298 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5299 return 0;
5300 }
5301
5302 return value;
5303}
5304
717746e3 5305static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5306{
717746e3 5307 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5308 int res = 0;
5309
52a46617
GN		 5310 switch (cr) {
5311 case 0:
49a9b07e 5312 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5313 break;
5314 case 2:
5315 vcpu->arch.cr2 = val;
5316 break;
5317 case 3:
2390218b 5318 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5319 break;
5320 case 4:
a83b29c6 5321 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5322 break;
5323 case 8:
eea1cff9 5324 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5325 break;
5326 default:
a737f256 5327 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5328 res = -1;
52a46617 5329 }
0f12244f
GN		 5330
5331 return res;
52a46617
GN		 5332}
5333
717746e3 5334static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5335{
717746e3 5336 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5337}
5338
4bff1e86 5339static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5340{
4bff1e86 5341 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5342}
5343
4bff1e86 5344static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5345{
4bff1e86 5346 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5347}
5348
1ac9d0cf
AK		 5349static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5350{
5351 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5352}
5353
5354static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5355{
5356 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5357}
5358
4bff1e86
AK		 5359static unsigned long emulator_get_cached_segment_base(
5360 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5361{
4bff1e86 5362 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5363}
5364
1aa36616
AK		 5365static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5366 struct desc_struct *desc, u32 *base3,
5367 int seg)
2dafc6c2
GN		 5368{
5369 struct kvm_segment var;
5370
4bff1e86 5371 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5372 *selector = var.selector;
2dafc6c2 5373
378a8b09
GN		 5374 if (var.unusable) {
5375 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5376 if (base3)
5377 *base3 = 0;
2dafc6c2 5378 return false;
378a8b09 5379 }
2dafc6c2
GN		 5380
5381 if (var.g)
5382 var.limit >>= 12;
5383 set_desc_limit(desc, var.limit);
5384 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5385#ifdef CONFIG_X86_64
5386 if (base3)
5387 *base3 = var.base >> 32;
5388#endif
2dafc6c2
GN		 5389 desc->type = var.type;
5390 desc->s = var.s;
5391 desc->dpl = var.dpl;
5392 desc->p = var.present;
5393 desc->avl = var.avl;
5394 desc->l = var.l;
5395 desc->d = var.db;
5396 desc->g = var.g;
5397
5398 return true;
5399}
5400
1aa36616
AK		 5401static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5402 struct desc_struct *desc, u32 base3,
5403 int seg)
2dafc6c2 5404{
4bff1e86 5405 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5406 struct kvm_segment var;
5407
1aa36616 5408 var.selector = selector;
2dafc6c2 5409 var.base = get_desc_base(desc);
5601d05b
GN		 5410#ifdef CONFIG_X86_64
5411 var.base |= ((u64)base3) << 32;
5412#endif
2dafc6c2
GN		 5413 var.limit = get_desc_limit(desc);
5414 if (desc->g)
5415 var.limit = (var.limit << 12) | 0xfff;
5416 var.type = desc->type;
2dafc6c2
GN		 5417 var.dpl = desc->dpl;
5418 var.db = desc->d;
5419 var.s = desc->s;
5420 var.l = desc->l;
5421 var.g = desc->g;
5422 var.avl = desc->avl;
5423 var.present = desc->p;
5424 var.unusable = !var.present;
5425 var.padding = 0;
5426
5427 kvm_set_segment(vcpu, &var, seg);
5428 return;
5429}
5430
717746e3
AK		 5431static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5432 u32 msr_index, u64 *pdata)
5433{
609e36d3
PB		 5434 struct msr_data msr;
5435 int r;
5436
5437 msr.index = msr_index;
5438 msr.host_initiated = false;
5439 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5440 if (r)
5441 return r;
5442
5443 *pdata = msr.data;
5444 return 0;
717746e3
AK		 5445}
5446
5447static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5448 u32 msr_index, u64 data)
5449{
8fe8ab46
WA		 5450 struct msr_data msr;
5451
5452 msr.data = data;
5453 msr.index = msr_index;
5454 msr.host_initiated = false;
5455 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5456}
5457
64d60670
PB		 5458static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5459{
5460 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5461
5462 return vcpu->arch.smbase;
5463}
5464
5465static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5466{
5467 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5468
5469 vcpu->arch.smbase = smbase;
5470}
5471
67f4d428
NA		 5472static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5473 u32 pmc)
5474{
c6702c9d 5475 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5476}
5477
222d21aa
AK		 5478static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5479 u32 pmc, u64 *pdata)
5480{
c6702c9d 5481 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5482}
5483
6c3287f7
AK		 5484static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5485{
5486 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5487}
5488
2953538e 5489static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5490 struct x86_instruction_info *info,
c4f035c6
AK		 5491 enum x86_intercept_stage stage)
5492{
2953538e 5493 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5494}
5495
e911eb3b
YZ		 5496static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5497 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5498{
e911eb3b 5499 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5500}
5501
dd856efa
AK		 5502static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5503{
5504 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5505}
5506
5507static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5508{
5509 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5510}
5511
801806d9
NA		 5512static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5513{
5514 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5515}
5516
6ed071f0
LP		 5517static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5518{
5519 return emul_to_vcpu(ctxt)->arch.hflags;
5520}
5521
5522static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5523{
5524 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5525}
5526
0234bf88
LP		 5527static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5528{
5529 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5530}
5531
0225fb50 5532static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5533 .read_gpr = emulator_read_gpr,
5534 .write_gpr = emulator_write_gpr,
1871c602 5535 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5536 .write_std = kvm_write_guest_virt_system,
7a036a6f 5537 .read_phys = kvm_read_guest_phys_system,
1871c602 5538 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5539 .read_emulated = emulator_read_emulated,
5540 .write_emulated = emulator_write_emulated,
5541 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5542 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5543 .pio_in_emulated = emulator_pio_in_emulated,
5544 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5545 .get_segment = emulator_get_segment,
5546 .set_segment = emulator_set_segment,
5951c442 5547 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5548 .get_gdt = emulator_get_gdt,
160ce1f1 5549 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5550 .set_gdt = emulator_set_gdt,
5551 .set_idt = emulator_set_idt,
52a46617
GN		 5552 .get_cr = emulator_get_cr,
5553 .set_cr = emulator_set_cr,
9c537244 5554 .cpl = emulator_get_cpl,
35aa5375
GN		 5555 .get_dr = emulator_get_dr,
5556 .set_dr = emulator_set_dr,
64d60670
PB		 5557 .get_smbase = emulator_get_smbase,
5558 .set_smbase = emulator_set_smbase,
717746e3
AK		 5559 .set_msr = emulator_set_msr,
5560 .get_msr = emulator_get_msr,
67f4d428 5561 .check_pmc = emulator_check_pmc,
222d21aa 5562 .read_pmc = emulator_read_pmc,
6c3287f7 5563 .halt = emulator_halt,
bcaf5cc5 5564 .wbinvd = emulator_wbinvd,
d6aa1000 5565 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5566 .intercept = emulator_intercept,
bdb42f5a 5567 .get_cpuid = emulator_get_cpuid,
801806d9 5568 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5569 .get_hflags = emulator_get_hflags,
5570 .set_hflags = emulator_set_hflags,
0234bf88 5571 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5572};
5573
95cb2295
GN		 5574static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5575{
37ccdcbe 5576 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5577 /*
5578 * an sti; sti; sequence only disable interrupts for the first
5579 * instruction. So, if the last instruction, be it emulated or
5580 * not, left the system with the INT_STI flag enabled, it
5581 * means that the last instruction is an sti. We should not
5582 * leave the flag on in this case. The same goes for mov ss
5583 */
37ccdcbe
PB		 5584 if (int_shadow & mask)
5585 mask = 0;
6addfc42 5586 if (unlikely(int_shadow || mask)) {
95cb2295 5587 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5588 if (!mask)
5589 kvm_make_request(KVM_REQ_EVENT, vcpu);
5590 }
95cb2295
GN		 5591}
5592
ef54bcfe 5593static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5594{
5595 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5596 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5597 return kvm_propagate_fault(vcpu, &ctxt->exception);
5598
5599 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5600 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5601 ctxt->exception.error_code);
54b8486f 5602 else
da9cb575 5603 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5604 return false;
54b8486f
GN		 5605}
5606
8ec4722d
MG		 5607static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5608{
adf52235 5609 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5610 int cs_db, cs_l;
5611
8ec4722d
MG		 5612 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5613
adf52235 5614 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5615 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5616
adf52235
TY		 5617 ctxt->eip = kvm_rip_read(vcpu);
5618 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5619 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5620 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5621 cs_db ? X86EMUL_MODE_PROT32 :
5622 X86EMUL_MODE_PROT16;
a584539b 5623 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5624 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5625 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5626
dd856efa 5627 init_decode_cache(ctxt);
7ae441ea 5628 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5629}
5630
71f9833b 5631int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5632{
9d74191a 5633 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5634 int ret;
5635
5636 init_emulate_ctxt(vcpu);
5637
9dac77fa
AK		 5638 ctxt->op_bytes = 2;
5639 ctxt->ad_bytes = 2;
5640 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5641 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5642
5643 if (ret != X86EMUL_CONTINUE)
5644 return EMULATE_FAIL;
5645
9dac77fa 5646 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5647 kvm_rip_write(vcpu, ctxt->eip);
5648 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5649
5650 if (irq == NMI_VECTOR)
7460fb4a 5651 vcpu->arch.nmi_pending = 0;
63995653
MG		 5652 else
5653 vcpu->arch.interrupt.pending = false;
5654
5655 return EMULATE_DONE;
5656}
5657EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5658
6d77dbfc
GN		 5659static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5660{
fc3a9157
JR		 5661 int r = EMULATE_DONE;
5662
6d77dbfc
GN		 5663 ++vcpu->stat.insn_emulation_fail;
5664 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5665 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5666 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5667 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5668 vcpu->run->internal.ndata = 0;
1f4dcb3b 5669 r = EMULATE_USER_EXIT;
fc3a9157 5670 }
6d77dbfc 5671 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5672
5673 return r;
6d77dbfc
GN		 5674}
5675
93c05d3e 5676static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5677 bool write_fault_to_shadow_pgtable,
5678 int emulation_type)
a6f177ef 5679{
95b3cf69 5680 gpa_t gpa = cr2;
ba049e93 5681 kvm_pfn_t pfn;
a6f177ef 5682
991eebf9
GN		 5683 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5684 return false;
5685
95b3cf69
XG		 5686 if (!vcpu->arch.mmu.direct_map) {
5687 /*
5688 * Write permission should be allowed since only
5689 * write access need to be emulated.
5690 */
5691 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5692
95b3cf69
XG		 5693 /*
5694 * If the mapping is invalid in guest, let cpu retry
5695 * it to generate fault.
5696 */
5697 if (gpa == UNMAPPED_GVA)
5698 return true;
5699 }
a6f177ef 5700
8e3d9d06
XG		 5701 /*
5702 * Do not retry the unhandleable instruction if it faults on the
5703 * readonly host memory, otherwise it will goto a infinite loop:
5704 * retry instruction -> write #PF -> emulation fail -> retry
5705 * instruction -> ...
5706 */
5707 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5708
5709 /*
5710 * If the instruction failed on the error pfn, it can not be fixed,
5711 * report the error to userspace.
5712 */
5713 if (is_error_noslot_pfn(pfn))
5714 return false;
5715
5716 kvm_release_pfn_clean(pfn);
5717
5718 /* The instructions are well-emulated on direct mmu. */
5719 if (vcpu->arch.mmu.direct_map) {
5720 unsigned int indirect_shadow_pages;
5721
5722 spin_lock(&vcpu->kvm->mmu_lock);
5723 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5724 spin_unlock(&vcpu->kvm->mmu_lock);
5725
5726 if (indirect_shadow_pages)
5727 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5728
a6f177ef 5729 return true;
8e3d9d06 5730 }
a6f177ef 5731
95b3cf69
XG		 5732 /*
5733 * if emulation was due to access to shadowed page table
5734 * and it failed try to unshadow page and re-enter the
5735 * guest to let CPU execute the instruction.
5736 */
5737 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5738
5739 /*
5740 * If the access faults on its page table, it can not
5741 * be fixed by unprotecting shadow page and it should
5742 * be reported to userspace.
5743 */
5744 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5745}
5746
1cb3f3ae
XG		 5747static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5748 unsigned long cr2, int emulation_type)
5749{
5750 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5751 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5752
5753 last_retry_eip = vcpu->arch.last_retry_eip;
5754 last_retry_addr = vcpu->arch.last_retry_addr;
5755
5756 /*
5757 * If the emulation is caused by #PF and it is non-page_table
5758 * writing instruction, it means the VM-EXIT is caused by shadow
5759 * page protected, we can zap the shadow page and retry this
5760 * instruction directly.
5761 *
5762 * Note: if the guest uses a non-page-table modifying instruction
5763 * on the PDE that points to the instruction, then we will unmap
5764 * the instruction and go to an infinite loop. So, we cache the
5765 * last retried eip and the last fault address, if we meet the eip
5766 * and the address again, we can break out of the potential infinite
5767 * loop.
5768 */
5769 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5770
5771 if (!(emulation_type & EMULTYPE_RETRY))
5772 return false;
5773
5774 if (x86_page_table_writing_insn(ctxt))
5775 return false;
5776
5777 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5778 return false;
5779
5780 vcpu->arch.last_retry_eip = ctxt->eip;
5781 vcpu->arch.last_retry_addr = cr2;
5782
5783 if (!vcpu->arch.mmu.direct_map)
5784 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5785
22368028 5786 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5787
5788 return true;
5789}
5790
716d51ab
GN		 5791static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5792static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5793
64d60670 5794static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5795{
64d60670 5796 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5797 /* This is a good place to trace that we are exiting SMM. */
5798 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5799
c43203ca
PB		 5800 /* Process a latched INIT or SMI, if any. */
5801 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5802 }
699023e2
PB		 5803
5804 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5805}
5806
5807static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5808{
5809 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5810
a584539b 5811 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5812
5813 if (changed & HF_SMM_MASK)
5814 kvm_smm_changed(vcpu);
a584539b
PB		 5815}
5816
4a1e10d5
PB		 5817static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5818 unsigned long *db)
5819{
5820 u32 dr6 = 0;
5821 int i;
5822 u32 enable, rwlen;
5823
5824 enable = dr7;
5825 rwlen = dr7 >> 16;
5826 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5827 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5828 dr6 |= (1 << i);
5829 return dr6;
5830}
5831
c8401dda 5832static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5833{
5834 struct kvm_run *kvm_run = vcpu->run;
5835
c8401dda
PB		 5836 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5837 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5838 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5839 kvm_run->debug.arch.exception = DB_VECTOR;
5840 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5841 *r = EMULATE_USER_EXIT;
5842 } else {
5843 /*
5844 * "Certain debug exceptions may clear bit 0-3. The
5845 * remaining contents of the DR6 register are never
5846 * cleared by the processor".
5847 */
5848 vcpu->arch.dr6 &= ~15;
5849 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5850 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5851 }
5852}
5853
6affcbed
KH		 5854int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5855{
5856 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5857 int r = EMULATE_DONE;
5858
5859 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5860
5861 /*
5862 * rflags is the old, "raw" value of the flags. The new value has
5863 * not been saved yet.
5864 *
5865 * This is correct even for TF set by the guest, because "the
5866 * processor will not generate this exception after the instruction
5867 * that sets the TF flag".
5868 */
5869 if (unlikely(rflags & X86_EFLAGS_TF))
5870 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5871 return r == EMULATE_DONE;
5872}
5873EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5874
4a1e10d5
PB		 5875static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5876{
4a1e10d5
PB		 5877 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5878 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5879 struct kvm_run *kvm_run = vcpu->run;
5880 unsigned long eip = kvm_get_linear_rip(vcpu);
5881 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5882 vcpu->arch.guest_debug_dr7,
5883 vcpu->arch.eff_db);
5884
5885 if (dr6 != 0) {
6f43ed01 5886 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5887 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5888 kvm_run->debug.arch.exception = DB_VECTOR;
5889 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5890 *r = EMULATE_USER_EXIT;
5891 return true;
5892 }
5893 }
5894
4161a569
NA		 5895 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5896 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5897 unsigned long eip = kvm_get_linear_rip(vcpu);
5898 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5899 vcpu->arch.dr7,
5900 vcpu->arch.db);
5901
5902 if (dr6 != 0) {
5903 vcpu->arch.dr6 &= ~15;
6f43ed01 5904 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5905 kvm_queue_exception(vcpu, DB_VECTOR);
5906 *r = EMULATE_DONE;
5907 return true;
5908 }
5909 }
5910
5911 return false;
5912}
5913
51d8b661
AP		 5914int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5915 unsigned long cr2,
dc25e89e
AP		 5916 int emulation_type,
5917 void *insn,
5918 int insn_len)
bbd9b64e 5919{
95cb2295 5920 int r;
9d74191a 5921 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5922 bool writeback = true;
93c05d3e 5923 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5924
93c05d3e
XG		 5925 /*
5926 * Clear write_fault_to_shadow_pgtable here to ensure it is
5927 * never reused.
5928 */
5929 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5930 kvm_clear_exception_queue(vcpu);
8d7d8102 5931
571008da 5932 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5933 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5934
5935 /*
5936 * We will reenter on the same instruction since
5937 * we do not set complete_userspace_io. This does not
5938 * handle watchpoints yet, those would be handled in
5939 * the emulate_ops.
5940 */
d391f120
VK		 5941 if (!(emulation_type & EMULTYPE_SKIP) &&
5942 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 5943 return r;
5944
9d74191a
TY		 5945 ctxt->interruptibility = 0;
5946 ctxt->have_exception = false;
e0ad0b47 5947 ctxt->exception.vector = -1;
9d74191a 5948 ctxt->perm_ok = false;
bbd9b64e 5949
b51e974f 5950 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5951
9d74191a 5952 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5953
e46479f8 5954 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5955 ++vcpu->stat.insn_emulation;
1d2887e2 5956 if (r != EMULATION_OK) {
4005996e
AK		 5957 if (emulation_type & EMULTYPE_TRAP_UD)
5958 return EMULATE_FAIL;
991eebf9
GN		 5959 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5960 emulation_type))
bbd9b64e 5961 return EMULATE_DONE;
6ea6e843
PB		 5962 if (ctxt->have_exception && inject_emulated_exception(vcpu))
5963 return EMULATE_DONE;
6d77dbfc
GN		 5964 if (emulation_type & EMULTYPE_SKIP)
5965 return EMULATE_FAIL;
5966 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5967 }
5968 }
5969
ba8afb6b 5970 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5971 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5972 if (ctxt->eflags & X86_EFLAGS_RF)
5973 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5974 return EMULATE_DONE;
5975 }
5976
1cb3f3ae
XG		 5977 if (retry_instruction(ctxt, cr2, emulation_type))
5978 return EMULATE_DONE;
5979
7ae441ea 5980 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5981 changes registers values during IO operation */
7ae441ea
GN		 5982 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5983 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5984 emulator_invalidate_register_cache(ctxt);
7ae441ea 5985 }
4d2179e1 5986
5cd21917 5987restart:
0f89b207
TL		 5988 /* Save the faulting GPA (cr2) in the address field */
5989 ctxt->exception.address = cr2;
5990
9d74191a 5991 r = x86_emulate_insn(ctxt);
bbd9b64e 5992
775fde86
JR		 5993 if (r == EMULATION_INTERCEPTED)
5994 return EMULATE_DONE;
5995
d2ddd1c4 5996 if (r == EMULATION_FAILED) {
991eebf9
GN		 5997 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5998 emulation_type))
c3cd7ffa
GN		 5999 return EMULATE_DONE;
6000
6d77dbfc 6001 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 6002 }
6003
9d74191a 6004 if (ctxt->have_exception) {
d2ddd1c4 6005 r = EMULATE_DONE;
ef54bcfe
PB		 6006 if (inject_emulated_exception(vcpu))
6007 return r;
d2ddd1c4 6008 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6009 if (!vcpu->arch.pio.in) {
6010 /* FIXME: return into emulator if single-stepping. */
3457e419 6011 vcpu->arch.pio.count = 0;
0912c977 6012 } else {
7ae441ea 6013 writeback = false;
716d51ab
GN		 6014 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6015 }
ac0a48c3 6016 r = EMULATE_USER_EXIT;
7ae441ea
GN		 6017 } else if (vcpu->mmio_needed) {
6018 if (!vcpu->mmio_is_write)
6019 writeback = false;
ac0a48c3 6020 r = EMULATE_USER_EXIT;
716d51ab 6021 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6022 } else if (r == EMULATION_RESTART)
5cd21917 6023 goto restart;
d2ddd1c4
GN		 6024 else
6025 r = EMULATE_DONE;
f850e2e6 6026
7ae441ea 6027 if (writeback) {
6addfc42 6028 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6029 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6030 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 6031 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 6032 if (r == EMULATE_DONE &&
6033 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
6034 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 6035 if (!ctxt->have_exception ||
6036 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6037 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 6038
6039 /*
6040 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6041 * do nothing, and it will be requested again as soon as
6042 * the shadow expires. But we still need to check here,
6043 * because POPF has no interrupt shadow.
6044 */
6045 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6046 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6047 } else
6048 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6049
6050 return r;
de7d789a 6051}
51d8b661 6052EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 6053
cf8f70bf 6054int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 6055{
cf8f70bf 6056 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 6057 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6058 size, port, &val, 1);
cf8f70bf 6059 /* do not return to emulator after return from userspace */
7972995b 6060 vcpu->arch.pio.count = 0;
de7d789a
CO		 6061 return ret;
6062}
cf8f70bf 6063EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 6064
8370c3d0
TL		 6065static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6066{
6067 unsigned long val;
6068
6069 /* We should only ever be called with arch.pio.count equal to 1 */
6070 BUG_ON(vcpu->arch.pio.count != 1);
6071
6072 /* For size less than 4 we merge, else we zero extend */
6073 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6074 : 0;
6075
6076 /*
6077 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6078 * the copy and tracing
6079 */
6080 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6081 vcpu->arch.pio.port, &val, 1);
6082 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6083
6084 return 1;
6085}
6086
6087int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
6088{
6089 unsigned long val;
6090 int ret;
6091
6092 /* For size less than 4 we merge, else we zero extend */
6093 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6094
6095 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6096 &val, 1);
6097 if (ret) {
6098 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6099 return ret;
6100 }
6101
6102 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6103
6104 return 0;
6105}
6106EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
6107
251a5fd6 6108static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6109{
0a3aee0d 6110 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6111 return 0;
8cfdc000
ZA		 6112}
6113
6114static void tsc_khz_changed(void *data)
c8076604 6115{
8cfdc000
ZA		 6116 struct cpufreq_freqs *freq = data;
6117 unsigned long khz = 0;
6118
6119 if (data)
6120 khz = freq->new;
6121 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6122 khz = cpufreq_quick_get(raw_smp_processor_id());
6123 if (!khz)
6124 khz = tsc_khz;
0a3aee0d 6125 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6126}
6127
5fa4ec9c 6128#ifdef CONFIG_X86_64
0092e434
VK		 6129static void kvm_hyperv_tsc_notifier(void)
6130{
0092e434
VK		 6131 struct kvm *kvm;
6132 struct kvm_vcpu *vcpu;
6133 int cpu;
6134
6135 spin_lock(&kvm_lock);
6136 list_for_each_entry(kvm, &vm_list, vm_list)
6137 kvm_make_mclock_inprogress_request(kvm);
6138
6139 hyperv_stop_tsc_emulation();
6140
6141 /* TSC frequency always matches when on Hyper-V */
6142 for_each_present_cpu(cpu)
6143 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6144 kvm_max_guest_tsc_khz = tsc_khz;
6145
6146 list_for_each_entry(kvm, &vm_list, vm_list) {
6147 struct kvm_arch *ka = &kvm->arch;
6148
6149 spin_lock(&ka->pvclock_gtod_sync_lock);
6150
6151 pvclock_update_vm_gtod_copy(kvm);
6152
6153 kvm_for_each_vcpu(cpu, vcpu, kvm)
6154 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6155
6156 kvm_for_each_vcpu(cpu, vcpu, kvm)
6157 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6158
6159 spin_unlock(&ka->pvclock_gtod_sync_lock);
6160 }
6161 spin_unlock(&kvm_lock);
0092e434 6162}
5fa4ec9c 6163#endif
0092e434 6164
c8076604
GH		 6165static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6166 void *data)
6167{
6168 struct cpufreq_freqs *freq = data;
6169 struct kvm *kvm;
6170 struct kvm_vcpu *vcpu;
6171 int i, send_ipi = 0;
6172
8cfdc000
ZA		 6173 /*
6174 * We allow guests to temporarily run on slowing clocks,
6175 * provided we notify them after, or to run on accelerating
6176 * clocks, provided we notify them before. Thus time never
6177 * goes backwards.
6178 *
6179 * However, we have a problem. We can't atomically update
6180 * the frequency of a given CPU from this function; it is
6181 * merely a notifier, which can be called from any CPU.
6182 * Changing the TSC frequency at arbitrary points in time
6183 * requires a recomputation of local variables related to
6184 * the TSC for each VCPU. We must flag these local variables
6185 * to be updated and be sure the update takes place with the
6186 * new frequency before any guests proceed.
6187 *
6188 * Unfortunately, the combination of hotplug CPU and frequency
6189 * change creates an intractable locking scenario; the order
6190 * of when these callouts happen is undefined with respect to
6191 * CPU hotplug, and they can race with each other. As such,
6192 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6193 * undefined; you can actually have a CPU frequency change take
6194 * place in between the computation of X and the setting of the
6195 * variable. To protect against this problem, all updates of
6196 * the per_cpu tsc_khz variable are done in an interrupt
6197 * protected IPI, and all callers wishing to update the value
6198 * must wait for a synchronous IPI to complete (which is trivial
6199 * if the caller is on the CPU already). This establishes the
6200 * necessary total order on variable updates.
6201 *
6202 * Note that because a guest time update may take place
6203 * anytime after the setting of the VCPU's request bit, the
6204 * correct TSC value must be set before the request. However,
6205 * to ensure the update actually makes it to any guest which
6206 * starts running in hardware virtualization between the set
6207 * and the acquisition of the spinlock, we must also ping the
6208 * CPU after setting the request bit.
6209 *
6210 */
6211
c8076604
GH		 6212 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6213 return 0;
6214 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6215 return 0;
8cfdc000
ZA		 6216
6217 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 6218
2f303b74 6219 spin_lock(&kvm_lock);
c8076604 6220 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6221 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 6222 if (vcpu->cpu != freq->cpu)
6223 continue;
c285545f 6224 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 6225 if (vcpu->cpu != smp_processor_id())
8cfdc000 6226 send_ipi = 1;
c8076604
GH		 6227 }
6228 }
2f303b74 6229 spin_unlock(&kvm_lock);
c8076604
GH		 6230
6231 if (freq->old < freq->new && send_ipi) {
6232 /*
6233 * We upscale the frequency. Must make the guest
6234 * doesn't see old kvmclock values while running with
6235 * the new frequency, otherwise we risk the guest sees
6236 * time go backwards.
6237 *
6238 * In case we update the frequency for another cpu
6239 * (which might be in guest context) send an interrupt
6240 * to kick the cpu out of guest context. Next time
6241 * guest context is entered kvmclock will be updated,
6242 * so the guest will not see stale values.
6243 */
8cfdc000 6244 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 6245 }
6246 return 0;
6247}
6248
6249static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6250 .notifier_call = kvmclock_cpufreq_notifier
6251};
6252
251a5fd6 6253static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6254{
251a5fd6
SAS		 6255 tsc_khz_changed(NULL);
6256 return 0;
8cfdc000
ZA		 6257}
6258
b820cc0c
ZA		 6259static void kvm_timer_init(void)
6260{
c285545f 6261 max_tsc_khz = tsc_khz;
460dd42e 6262
b820cc0c 6263 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6264#ifdef CONFIG_CPU_FREQ
6265 struct cpufreq_policy policy;
758f588d
BP		 6266 int cpu;
6267
c285545f 6268 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6269 cpu = get_cpu();
6270 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6271 if (policy.cpuinfo.max_freq)
6272 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6273 put_cpu();
c285545f 6274#endif
b820cc0c
ZA		 6275 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6276 CPUFREQ_TRANSITION_NOTIFIER);
6277 }
c285545f 6278 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6279
73c1b41e 6280 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6281 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6282}
6283
ff9d07a0
ZY		 6284static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6285
f5132b01 6286int kvm_is_in_guest(void)
ff9d07a0 6287{
086c9855 6288 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6289}
6290
6291static int kvm_is_user_mode(void)
6292{
6293 int user_mode = 3;
dcf46b94 6294
086c9855
AS		 6295 if (__this_cpu_read(current_vcpu))
6296 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6297
ff9d07a0
ZY		 6298 return user_mode != 0;
6299}
6300
6301static unsigned long kvm_get_guest_ip(void)
6302{
6303 unsigned long ip = 0;
dcf46b94 6304
086c9855
AS		 6305 if (__this_cpu_read(current_vcpu))
6306 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6307
ff9d07a0
ZY		 6308 return ip;
6309}
6310
6311static struct perf_guest_info_callbacks kvm_guest_cbs = {
6312 .is_in_guest = kvm_is_in_guest,
6313 .is_user_mode = kvm_is_user_mode,
6314 .get_guest_ip = kvm_get_guest_ip,
6315};
6316
6317void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
6318{
086c9855 6319 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 6320}
6321EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
6322
6323void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6324{
086c9855 6325 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 6326}
6327EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6328
ce88decf
XG		 6329static void kvm_set_mmio_spte_mask(void)
6330{
6331 u64 mask;
6332 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6333
6334 /*
6335 * Set the reserved bits and the present bit of an paging-structure
6336 * entry to generate page fault with PFER.RSV = 1.
6337 */
885032b9 6338 /* Mask the reserved physical address bits. */
d1431483 6339 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6340
885032b9 6341 /* Set the present bit. */
ce88decf
XG		 6342 mask |= 1ull;
6343
6344#ifdef CONFIG_X86_64
6345 /*
6346 * If reserved bit is not supported, clear the present bit to disable
6347 * mmio page fault.
6348 */
6349 if (maxphyaddr == 52)
6350 mask &= ~1ull;
6351#endif
6352
dcdca5fe 6353 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6354}
6355
16e8d74d
MT		 6356#ifdef CONFIG_X86_64
6357static void pvclock_gtod_update_fn(struct work_struct *work)
6358{
d828199e
MT		 6359 struct kvm *kvm;
6360
6361 struct kvm_vcpu *vcpu;
6362 int i;
6363
2f303b74 6364 spin_lock(&kvm_lock);
d828199e
MT		 6365 list_for_each_entry(kvm, &vm_list, vm_list)
6366 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6367 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6368 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6369 spin_unlock(&kvm_lock);
16e8d74d
MT		 6370}
6371
6372static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6373
6374/*
6375 * Notification about pvclock gtod data update.
6376 */
6377static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6378 void *priv)
6379{
6380 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6381 struct timekeeper *tk = priv;
6382
6383 update_pvclock_gtod(tk);
6384
6385 /* disable master clock if host does not trust, or does not
b0c39dc6 6386 * use, TSC based clocksource.
16e8d74d 6387 */
b0c39dc6 6388 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6389 atomic_read(&kvm_guest_has_master_clock) != 0)
6390 queue_work(system_long_wq, &pvclock_gtod_work);
6391
6392 return 0;
6393}
6394
6395static struct notifier_block pvclock_gtod_notifier = {
6396 .notifier_call = pvclock_gtod_notify,
6397};
6398#endif
6399
f8c16bba 6400int kvm_arch_init(void *opaque)
043405e1 6401{
b820cc0c 6402 int r;
6b61edf7 6403 struct kvm_x86_ops *ops = opaque;
f8c16bba 6404
f8c16bba
ZX		 6405 if (kvm_x86_ops) {
6406 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6407 r = -EEXIST;
6408 goto out;
f8c16bba
ZX		 6409 }
6410
6411 if (!ops->cpu_has_kvm_support()) {
6412 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6413 r = -EOPNOTSUPP;
6414 goto out;
f8c16bba
ZX		 6415 }
6416 if (ops->disabled_by_bios()) {
6417 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6418 r = -EOPNOTSUPP;
6419 goto out;
f8c16bba
ZX		 6420 }
6421
013f6a5d
MT		 6422 r = -ENOMEM;
6423 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6424 if (!shared_msrs) {
6425 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6426 goto out;
6427 }
6428
97db56ce
AK		 6429 r = kvm_mmu_module_init();
6430 if (r)
013f6a5d 6431 goto out_free_percpu;
97db56ce 6432
ce88decf 6433 kvm_set_mmio_spte_mask();
97db56ce 6434
f8c16bba 6435 kvm_x86_ops = ops;
920c8377 6436
7b52345e 6437 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6438 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6439 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6440 kvm_timer_init();
c8076604 6441
ff9d07a0
ZY		 6442 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6443
d366bf7e 6444 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6445 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6446
c5cc421b 6447 kvm_lapic_init();
16e8d74d
MT		 6448#ifdef CONFIG_X86_64
6449 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 6450
5fa4ec9c 6451 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 6452 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 6453#endif
6454
f8c16bba 6455 return 0;
56c6d28a 6456
013f6a5d
MT		 6457out_free_percpu:
6458 free_percpu(shared_msrs);
56c6d28a 6459out:
56c6d28a 6460 return r;
043405e1 6461}
8776e519 6462
f8c16bba
ZX		 6463void kvm_arch_exit(void)
6464{
0092e434 6465#ifdef CONFIG_X86_64
5fa4ec9c 6466 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 6467 clear_hv_tscchange_cb();
6468#endif
cef84c30 6469 kvm_lapic_exit();
ff9d07a0
ZY		 6470 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6471
888d256e
JK		 6472 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6473 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6474 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6475 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6476#ifdef CONFIG_X86_64
6477 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6478#endif
f8c16bba 6479 kvm_x86_ops = NULL;
56c6d28a 6480 kvm_mmu_module_exit();
013f6a5d 6481 free_percpu(shared_msrs);
56c6d28a 6482}
f8c16bba 6483
5cb56059 6484int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6485{
6486 ++vcpu->stat.halt_exits;
35754c98 6487 if (lapic_in_kernel(vcpu)) {
a4535290 6488 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6489 return 1;
6490 } else {
6491 vcpu->run->exit_reason = KVM_EXIT_HLT;
6492 return 0;
6493 }
6494}
5cb56059
JS		 6495EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6496
6497int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6498{
6affcbed
KH		 6499 int ret = kvm_skip_emulated_instruction(vcpu);
6500 /*
6501 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6502 * KVM_EXIT_DEBUG here.
6503 */
6504 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6505}
8776e519
HB		 6506EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6507
8ef81a9a 6508#ifdef CONFIG_X86_64
55dd00a7
MT		 6509static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6510 unsigned long clock_type)
6511{
6512 struct kvm_clock_pairing clock_pairing;
6513 struct timespec ts;
80fbd89c 6514 u64 cycle;
55dd00a7
MT		 6515 int ret;
6516
6517 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6518 return -KVM_EOPNOTSUPP;
6519
6520 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6521 return -KVM_EOPNOTSUPP;
6522
6523 clock_pairing.sec = ts.tv_sec;
6524 clock_pairing.nsec = ts.tv_nsec;
6525 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6526 clock_pairing.flags = 0;
6527
6528 ret = 0;
6529 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6530 sizeof(struct kvm_clock_pairing)))
6531 ret = -KVM_EFAULT;
6532
6533 return ret;
6534}
8ef81a9a 6535#endif
55dd00a7 6536
6aef266c
SV		 6537/*
6538 * kvm_pv_kick_cpu_op: Kick a vcpu.
6539 *
6540 * @apicid - apicid of vcpu to be kicked.
6541 */
6542static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6543{
24d2166b 6544 struct kvm_lapic_irq lapic_irq;
6aef266c 6545
24d2166b
R		 6546 lapic_irq.shorthand = 0;
6547 lapic_irq.dest_mode = 0;
ebd28fcb 6548 lapic_irq.level = 0;
24d2166b 6549 lapic_irq.dest_id = apicid;
93bbf0b8 6550 lapic_irq.msi_redir_hint = false;
6aef266c 6551
24d2166b 6552 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6553 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6554}
6555
d62caabb
AS		 6556void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6557{
6558 vcpu->arch.apicv_active = false;
6559 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6560}
6561
8776e519
HB		 6562int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6563{
6564 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6565 int op_64_bit, r;
8776e519 6566
6affcbed 6567 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6568
55cd8e5a
GN		 6569 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6570 return kvm_hv_hypercall(vcpu);
6571
5fdbf976
MT		 6572 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6573 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6574 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6575 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6576 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6577
229456fc 6578 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6579
a449c7aa
NA		 6580 op_64_bit = is_64_bit_mode(vcpu);
6581 if (!op_64_bit) {
8776e519
HB		 6582 nr &= 0xFFFFFFFF;
6583 a0 &= 0xFFFFFFFF;
6584 a1 &= 0xFFFFFFFF;
6585 a2 &= 0xFFFFFFFF;
6586 a3 &= 0xFFFFFFFF;
6587 }
6588
07708c4a
JK		 6589 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6590 ret = -KVM_EPERM;
6591 goto out;
6592 }
6593
8776e519 6594 switch (nr) {
b93463aa
AK		 6595 case KVM_HC_VAPIC_POLL_IRQ:
6596 ret = 0;
6597 break;
6aef266c
SV		 6598 case KVM_HC_KICK_CPU:
6599 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6600 ret = 0;
6601 break;
8ef81a9a 6602#ifdef CONFIG_X86_64
55dd00a7
MT		 6603 case KVM_HC_CLOCK_PAIRING:
6604 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6605 break;
8ef81a9a 6606#endif
8776e519
HB		 6607 default:
6608 ret = -KVM_ENOSYS;
6609 break;
6610 }
07708c4a 6611out:
a449c7aa
NA		 6612 if (!op_64_bit)
6613 ret = (u32)ret;
5fdbf976 6614 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6615 ++vcpu->stat.hypercalls;
2f333bcb 6616 return r;
8776e519
HB		 6617}
6618EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6619
b6785def 6620static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6621{
d6aa1000 6622 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6623 char instruction[3];
5fdbf976 6624 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6625
8776e519 6626 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6627
ce2e852e
DV		 6628 return emulator_write_emulated(ctxt, rip, instruction, 3,
6629 &ctxt->exception);
8776e519
HB		 6630}
6631
851ba692 6632static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6633{
782d422b
MG		 6634 return vcpu->run->request_interrupt_window &&
6635 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6636}
6637
851ba692 6638static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6639{
851ba692
AK		 6640 struct kvm_run *kvm_run = vcpu->run;
6641
91586a3b 6642 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6643 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6644 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6645 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6646 kvm_run->ready_for_interrupt_injection =
6647 pic_in_kernel(vcpu->kvm) ||
782d422b 6648 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6649}
6650
95ba8273
GN		 6651static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6652{
6653 int max_irr, tpr;
6654
6655 if (!kvm_x86_ops->update_cr8_intercept)
6656 return;
6657
bce87cce 6658 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6659 return;
6660
d62caabb
AS		 6661 if (vcpu->arch.apicv_active)
6662 return;
6663
8db3baa2
GN		 6664 if (!vcpu->arch.apic->vapic_addr)
6665 max_irr = kvm_lapic_find_highest_irr(vcpu);
6666 else
6667 max_irr = -1;
95ba8273
GN		 6668
6669 if (max_irr != -1)
6670 max_irr >>= 4;
6671
6672 tpr = kvm_lapic_get_cr8(vcpu);
6673
6674 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6675}
6676
b6b8a145 6677static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6678{
b6b8a145
JK		 6679 int r;
6680
95ba8273 6681 /* try to reinject previous events if any */
664f8e26
WL		 6682 if (vcpu->arch.exception.injected) {
6683 kvm_x86_ops->queue_exception(vcpu);
6684 return 0;
6685 }
6686
6687 /*
6688 * Exceptions must be injected immediately, or the exception
6689 * frame will have the address of the NMI or interrupt handler.
6690 */
6691 if (!vcpu->arch.exception.pending) {
6692 if (vcpu->arch.nmi_injected) {
6693 kvm_x86_ops->set_nmi(vcpu);
6694 return 0;
6695 }
6696
6697 if (vcpu->arch.interrupt.pending) {
6698 kvm_x86_ops->set_irq(vcpu);
6699 return 0;
6700 }
6701 }
6702
6703 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6704 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6705 if (r != 0)
6706 return r;
6707 }
6708
6709 /* try to inject new event if pending */
b59bb7bd 6710 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6711 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6712 vcpu->arch.exception.has_error_code,
6713 vcpu->arch.exception.error_code);
d6e8c854 6714
664f8e26
WL		 6715 vcpu->arch.exception.pending = false;
6716 vcpu->arch.exception.injected = true;
6717
d6e8c854
NA		 6718 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6719 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6720 X86_EFLAGS_RF);
6721
6bdf0662
NA		 6722 if (vcpu->arch.exception.nr == DB_VECTOR &&
6723 (vcpu->arch.dr7 & DR7_GD)) {
6724 vcpu->arch.dr7 &= ~DR7_GD;
6725 kvm_update_dr7(vcpu);
6726 }
6727
cfcd20e5 6728 kvm_x86_ops->queue_exception(vcpu);
72d7b374 6729 } else if (vcpu->arch.smi_pending && !is_smm(vcpu) && kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 6730 vcpu->arch.smi_pending = false;
52797bf9 6731 ++vcpu->arch.smi_count;
ee2cd4b7 6732 enter_smm(vcpu);
c43203ca 6733 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6734 --vcpu->arch.nmi_pending;
6735 vcpu->arch.nmi_injected = true;
6736 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6737 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6738 /*
6739 * Because interrupts can be injected asynchronously, we are
6740 * calling check_nested_events again here to avoid a race condition.
6741 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6742 * proposal and current concerns. Perhaps we should be setting
6743 * KVM_REQ_EVENT only on certain events and not unconditionally?
6744 */
6745 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6746 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6747 if (r != 0)
6748 return r;
6749 }
95ba8273 6750 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6751 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6752 false);
6753 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6754 }
6755 }
ee2cd4b7 6756
b6b8a145 6757 return 0;
95ba8273
GN		 6758}
6759
7460fb4a
AK		 6760static void process_nmi(struct kvm_vcpu *vcpu)
6761{
6762 unsigned limit = 2;
6763
6764 /*
6765 * x86 is limited to one NMI running, and one NMI pending after it.
6766 * If an NMI is already in progress, limit further NMIs to just one.
6767 * Otherwise, allow two (and we'll inject the first one immediately).
6768 */
6769 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6770 limit = 1;
6771
6772 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6773 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6774 kvm_make_request(KVM_REQ_EVENT, vcpu);
6775}
6776
ee2cd4b7 6777static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6778{
6779 u32 flags = 0;
6780 flags |= seg->g << 23;
6781 flags |= seg->db << 22;
6782 flags |= seg->l << 21;
6783 flags |= seg->avl << 20;
6784 flags |= seg->present << 15;
6785 flags |= seg->dpl << 13;
6786 flags |= seg->s << 12;
6787 flags |= seg->type << 8;
6788 return flags;
6789}
6790
ee2cd4b7 6791static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6792{
6793 struct kvm_segment seg;
6794 int offset;
6795
6796 kvm_get_segment(vcpu, &seg, n);
6797 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6798
6799 if (n < 3)
6800 offset = 0x7f84 + n * 12;
6801 else
6802 offset = 0x7f2c + (n - 3) * 12;
6803
6804 put_smstate(u32, buf, offset + 8, seg.base);
6805 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6806 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6807}
6808
efbb288a 6809#ifdef CONFIG_X86_64
ee2cd4b7 6810static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6811{
6812 struct kvm_segment seg;
6813 int offset;
6814 u16 flags;
6815
6816 kvm_get_segment(vcpu, &seg, n);
6817 offset = 0x7e00 + n * 16;
6818
ee2cd4b7 6819 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6820 put_smstate(u16, buf, offset, seg.selector);
6821 put_smstate(u16, buf, offset + 2, flags);
6822 put_smstate(u32, buf, offset + 4, seg.limit);
6823 put_smstate(u64, buf, offset + 8, seg.base);
6824}
efbb288a 6825#endif
660a5d51 6826
ee2cd4b7 6827static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6828{
6829 struct desc_ptr dt;
6830 struct kvm_segment seg;
6831 unsigned long val;
6832 int i;
6833
6834 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6835 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6836 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6837 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6838
6839 for (i = 0; i < 8; i++)
6840 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6841
6842 kvm_get_dr(vcpu, 6, &val);
6843 put_smstate(u32, buf, 0x7fcc, (u32)val);
6844 kvm_get_dr(vcpu, 7, &val);
6845 put_smstate(u32, buf, 0x7fc8, (u32)val);
6846
6847 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6848 put_smstate(u32, buf, 0x7fc4, seg.selector);
6849 put_smstate(u32, buf, 0x7f64, seg.base);
6850 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6851 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6852
6853 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6854 put_smstate(u32, buf, 0x7fc0, seg.selector);
6855 put_smstate(u32, buf, 0x7f80, seg.base);
6856 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6857 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6858
6859 kvm_x86_ops->get_gdt(vcpu, &dt);
6860 put_smstate(u32, buf, 0x7f74, dt.address);
6861 put_smstate(u32, buf, 0x7f70, dt.size);
6862
6863 kvm_x86_ops->get_idt(vcpu, &dt);
6864 put_smstate(u32, buf, 0x7f58, dt.address);
6865 put_smstate(u32, buf, 0x7f54, dt.size);
6866
6867 for (i = 0; i < 6; i++)
ee2cd4b7 6868 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6869
6870 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6871
6872 /* revision id */
6873 put_smstate(u32, buf, 0x7efc, 0x00020000);
6874 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6875}
6876
ee2cd4b7 6877static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6878{
6879#ifdef CONFIG_X86_64
6880 struct desc_ptr dt;
6881 struct kvm_segment seg;
6882 unsigned long val;
6883 int i;
6884
6885 for (i = 0; i < 16; i++)
6886 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6887
6888 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6889 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6890
6891 kvm_get_dr(vcpu, 6, &val);
6892 put_smstate(u64, buf, 0x7f68, val);
6893 kvm_get_dr(vcpu, 7, &val);
6894 put_smstate(u64, buf, 0x7f60, val);
6895
6896 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6897 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6898 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6899
6900 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6901
6902 /* revision id */
6903 put_smstate(u32, buf, 0x7efc, 0x00020064);
6904
6905 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6906
6907 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6908 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6909 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6910 put_smstate(u32, buf, 0x7e94, seg.limit);
6911 put_smstate(u64, buf, 0x7e98, seg.base);
6912
6913 kvm_x86_ops->get_idt(vcpu, &dt);
6914 put_smstate(u32, buf, 0x7e84, dt.size);
6915 put_smstate(u64, buf, 0x7e88, dt.address);
6916
6917 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6918 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6919 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6920 put_smstate(u32, buf, 0x7e74, seg.limit);
6921 put_smstate(u64, buf, 0x7e78, seg.base);
6922
6923 kvm_x86_ops->get_gdt(vcpu, &dt);
6924 put_smstate(u32, buf, 0x7e64, dt.size);
6925 put_smstate(u64, buf, 0x7e68, dt.address);
6926
6927 for (i = 0; i < 6; i++)
ee2cd4b7 6928 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6929#else
6930 WARN_ON_ONCE(1);
6931#endif
6932}
6933
ee2cd4b7 6934static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6935{
660a5d51 6936 struct kvm_segment cs, ds;
18c3626e 6937 struct desc_ptr dt;
660a5d51
PB		 6938 char buf[512];
6939 u32 cr0;
6940
660a5d51 6941 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 6942 memset(buf, 0, 512);
d6321d49 6943 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 6944 enter_smm_save_state_64(vcpu, buf);
660a5d51 6945 else
ee2cd4b7 6946 enter_smm_save_state_32(vcpu, buf);
660a5d51 6947
0234bf88
LP		 6948 /*
6949 * Give pre_enter_smm() a chance to make ISA-specific changes to the
6950 * vCPU state (e.g. leave guest mode) after we've saved the state into
6951 * the SMM state-save area.
6952 */
6953 kvm_x86_ops->pre_enter_smm(vcpu, buf);
6954
6955 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 6956 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6957
6958 if (kvm_x86_ops->get_nmi_mask(vcpu))
6959 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6960 else
6961 kvm_x86_ops->set_nmi_mask(vcpu, true);
6962
6963 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6964 kvm_rip_write(vcpu, 0x8000);
6965
6966 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6967 kvm_x86_ops->set_cr0(vcpu, cr0);
6968 vcpu->arch.cr0 = cr0;
6969
6970 kvm_x86_ops->set_cr4(vcpu, 0);
6971
18c3626e
PB		 6972 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6973 dt.address = dt.size = 0;
6974 kvm_x86_ops->set_idt(vcpu, &dt);
6975
660a5d51
PB		 6976 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6977
6978 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6979 cs.base = vcpu->arch.smbase;
6980
6981 ds.selector = 0;
6982 ds.base = 0;
6983
6984 cs.limit = ds.limit = 0xffffffff;
6985 cs.type = ds.type = 0x3;
6986 cs.dpl = ds.dpl = 0;
6987 cs.db = ds.db = 0;
6988 cs.s = ds.s = 1;
6989 cs.l = ds.l = 0;
6990 cs.g = ds.g = 1;
6991 cs.avl = ds.avl = 0;
6992 cs.present = ds.present = 1;
6993 cs.unusable = ds.unusable = 0;
6994 cs.padding = ds.padding = 0;
6995
6996 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6997 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6998 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6999 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7000 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7001 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7002
d6321d49 7003 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 7004 kvm_x86_ops->set_efer(vcpu, 0);
7005
7006 kvm_update_cpuid(vcpu);
7007 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7008}
7009
ee2cd4b7 7010static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7011{
7012 vcpu->arch.smi_pending = true;
7013 kvm_make_request(KVM_REQ_EVENT, vcpu);
7014}
7015
2860c4b1
PB		 7016void kvm_make_scan_ioapic_request(struct kvm *kvm)
7017{
7018 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7019}
7020
3d81bc7e 7021static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7022{
5c919412
AS		 7023 u64 eoi_exit_bitmap[4];
7024
3d81bc7e
YZ		 7025 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7026 return;
c7c9c56c 7027
6308630b 7028 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7029
b053b2ae 7030 if (irqchip_split(vcpu->kvm))
6308630b 7031 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7032 else {
fa59cc00 7033 if (vcpu->arch.apicv_active)
d62caabb 7034 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 7035 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7036 }
5c919412
AS		 7037 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7038 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7039 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7040}
7041
b1394e74
RK		 7042void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7043 unsigned long start, unsigned long end)
7044{
7045 unsigned long apic_address;
7046
7047 /*
7048 * The physical address of apic access page is stored in the VMCS.
7049 * Update it when it becomes invalid.
7050 */
7051 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7052 if (start <= apic_address && apic_address < end)
7053 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
7054}
7055
4256f43f
TC		 7056void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7057{
c24ae0dc
TC		 7058 struct page *page = NULL;
7059
35754c98 7060 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7061 return;
7062
4256f43f
TC		 7063 if (!kvm_x86_ops->set_apic_access_page_addr)
7064 return;
7065
c24ae0dc 7066 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7067 if (is_error_page(page))
7068 return;
c24ae0dc
TC		 7069 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7070
7071 /*
7072 * Do not pin apic access page in memory, the MMU notifier
7073 * will call us again if it is migrated or swapped out.
7074 */
7075 put_page(page);
4256f43f
TC		 7076}
7077EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7078
9357d939 7079/*
362c698f 7080 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7081 * exiting to the userspace. Otherwise, the value will be returned to the
7082 * userspace.
7083 */
851ba692 7084static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7085{
7086 int r;
62a193ed
MG		 7087 bool req_int_win =
7088 dm_request_for_irq_injection(vcpu) &&
7089 kvm_cpu_accept_dm_intr(vcpu);
7090
730dca42 7091 bool req_immediate_exit = false;
b6c7a5dc 7092
2fa6e1e1 7093 if (kvm_request_pending(vcpu)) {
a8eeb04a 7094 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7095 kvm_mmu_unload(vcpu);
a8eeb04a 7096 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7097 __kvm_migrate_timers(vcpu);
d828199e
MT		 7098 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7099 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7100 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7101 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7102 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7103 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7104 if (unlikely(r))
7105 goto out;
7106 }
a8eeb04a 7107 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7108 kvm_mmu_sync_roots(vcpu);
a8eeb04a 7109 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7110 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7111 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7112 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7113 r = 0;
7114 goto out;
7115 }
a8eeb04a 7116 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7117 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7118 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7119 r = 0;
7120 goto out;
7121 }
af585b92
GN		 7122 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7123 /* Page is swapped out. Do synthetic halt */
7124 vcpu->arch.apf.halted = true;
7125 r = 1;
7126 goto out;
7127 }
c9aaa895
GC		 7128 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7129 record_steal_time(vcpu);
64d60670
PB		 7130 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7131 process_smi(vcpu);
7460fb4a
AK		 7132 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7133 process_nmi(vcpu);
f5132b01 7134 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7135 kvm_pmu_handle_event(vcpu);
f5132b01 7136 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7137 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7138 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7139 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7140 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7141 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7142 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7143 vcpu->run->eoi.vector =
7144 vcpu->arch.pending_ioapic_eoi;
7145 r = 0;
7146 goto out;
7147 }
7148 }
3d81bc7e
YZ		 7149 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7150 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 7151 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7152 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7153 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7154 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7155 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7156 r = 0;
7157 goto out;
7158 }
e516cebb
AS		 7159 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7160 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7161 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7162 r = 0;
7163 goto out;
7164 }
db397571
AS		 7165 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7166 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7167 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7168 r = 0;
7169 goto out;
7170 }
f3b138c5
AS		 7171
7172 /*
7173 * KVM_REQ_HV_STIMER has to be processed after
7174 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7175 * depend on the guest clock being up-to-date
7176 */
1f4b34f8
AS		 7177 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7178 kvm_hv_process_stimers(vcpu);
2f52d58c 7179 }
b93463aa 7180
b463a6f7 7181 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7182 ++vcpu->stat.req_event;
66450a21
JK		 7183 kvm_apic_accept_events(vcpu);
7184 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7185 r = 1;
7186 goto out;
7187 }
7188
b6b8a145
JK		 7189 if (inject_pending_event(vcpu, req_int_win) != 0)
7190 req_immediate_exit = true;
321c5658 7191 else {
cc3d967f 7192 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7193 *
cc3d967f
LP		 7194 * SMIs have three cases:
7195 * 1) They can be nested, and then there is nothing to
7196 * do here because RSM will cause a vmexit anyway.
7197 * 2) There is an ISA-specific reason why SMI cannot be
7198 * injected, and the moment when this changes can be
7199 * intercepted.
7200 * 3) Or the SMI can be pending because
7201 * inject_pending_event has completed the injection
7202 * of an IRQ or NMI from the previous vmexit, and
7203 * then we request an immediate exit to inject the
7204 * SMI.
c43203ca
PB		 7205 */
7206 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7207 if (!kvm_x86_ops->enable_smi_window(vcpu))
7208 req_immediate_exit = true;
321c5658
YS		 7209 if (vcpu->arch.nmi_pending)
7210 kvm_x86_ops->enable_nmi_window(vcpu);
7211 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7212 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7213 WARN_ON(vcpu->arch.exception.pending);
321c5658 7214 }
b463a6f7
AK		 7215
7216 if (kvm_lapic_enabled(vcpu)) {
7217 update_cr8_intercept(vcpu);
7218 kvm_lapic_sync_to_vapic(vcpu);
7219 }
7220 }
7221
d8368af8
AK		 7222 r = kvm_mmu_reload(vcpu);
7223 if (unlikely(r)) {
d905c069 7224 goto cancel_injection;
d8368af8
AK		 7225 }
7226
b6c7a5dc
HB		 7227 preempt_disable();
7228
7229 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7230
7231 /*
7232 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7233 * IPI are then delayed after guest entry, which ensures that they
7234 * result in virtual interrupt delivery.
7235 */
7236 local_irq_disable();
6b7e2d09
XG		 7237 vcpu->mode = IN_GUEST_MODE;
7238
01b71917
MT		 7239 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7240
0f127d12 7241 /*
b95234c8 7242 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7243 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 7244 *
7245 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7246 * pairs with the memory barrier implicit in pi_test_and_set_on
7247 * (see vmx_deliver_posted_interrupt).
7248 *
7249 * 3) This also orders the write to mode from any reads to the page
7250 * tables done while the VCPU is running. Please see the comment
7251 * in kvm_flush_remote_tlbs.
6b7e2d09 7252 */
01b71917 7253 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7254
b95234c8
PB		 7255 /*
7256 * This handles the case where a posted interrupt was
7257 * notified with kvm_vcpu_kick.
7258 */
fa59cc00
LA		 7259 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7260 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7261
2fa6e1e1 7262 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7263 || need_resched() || signal_pending(current)) {
6b7e2d09 7264 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7265 smp_wmb();
6c142801
AK		 7266 local_irq_enable();
7267 preempt_enable();
01b71917 7268 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7269 r = 1;
d905c069 7270 goto cancel_injection;
6c142801
AK		 7271 }
7272
fc5b7f3b
DM		 7273 kvm_load_guest_xcr0(vcpu);
7274
c43203ca
PB		 7275 if (req_immediate_exit) {
7276 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 7277 smp_send_reschedule(vcpu->cpu);
c43203ca 7278 }
d6185f20 7279
8b89fe1f 7280 trace_kvm_entry(vcpu->vcpu_id);
9c48d517
WL		 7281 if (lapic_timer_advance_ns)
7282 wait_lapic_expire(vcpu);
6edaa530 7283 guest_enter_irqoff();
b6c7a5dc 7284
42dbaa5a 7285 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7286 set_debugreg(0, 7);
7287 set_debugreg(vcpu->arch.eff_db[0], 0);
7288 set_debugreg(vcpu->arch.eff_db[1], 1);
7289 set_debugreg(vcpu->arch.eff_db[2], 2);
7290 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7291 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7292 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7293 }
b6c7a5dc 7294
851ba692 7295 kvm_x86_ops->run(vcpu);
b6c7a5dc 7296
c77fb5fe
PB		 7297 /*
7298 * Do this here before restoring debug registers on the host. And
7299 * since we do this before handling the vmexit, a DR access vmexit
7300 * can (a) read the correct value of the debug registers, (b) set
7301 * KVM_DEBUGREG_WONT_EXIT again.
7302 */
7303 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7304 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7305 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7306 kvm_update_dr0123(vcpu);
7307 kvm_update_dr6(vcpu);
7308 kvm_update_dr7(vcpu);
7309 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7310 }
7311
24f1e32c
FW		 7312 /*
7313 * If the guest has used debug registers, at least dr7
7314 * will be disabled while returning to the host.
7315 * If we don't have active breakpoints in the host, we don't
7316 * care about the messed up debug address registers. But if
7317 * we have some of them active, restore the old state.
7318 */
59d8eb53 7319 if (hw_breakpoint_active())
24f1e32c 7320 hw_breakpoint_restore();
42dbaa5a 7321
4ba76538 7322 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7323
6b7e2d09 7324 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7325 smp_wmb();
a547c6db 7326
fc5b7f3b
DM		 7327 kvm_put_guest_xcr0(vcpu);
7328
a547c6db 7329 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 7330
7331 ++vcpu->stat.exits;
7332
f2485b3e 7333 guest_exit_irqoff();
b6c7a5dc 7334
f2485b3e 7335 local_irq_enable();
b6c7a5dc
HB		 7336 preempt_enable();
7337
f656ce01 7338 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7339
b6c7a5dc
HB		 7340 /*
7341 * Profile KVM exit RIPs:
7342 */
7343 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7344 unsigned long rip = kvm_rip_read(vcpu);
7345 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7346 }
7347
cc578287
ZA		 7348 if (unlikely(vcpu->arch.tsc_always_catchup))
7349 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7350
5cfb1d5a
MT		 7351 if (vcpu->arch.apic_attention)
7352 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7353
618232e2 7354 vcpu->arch.gpa_available = false;
851ba692 7355 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7356 return r;
7357
7358cancel_injection:
7359 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7360 if (unlikely(vcpu->arch.apic_attention))
7361 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7362out:
7363 return r;
7364}
b6c7a5dc 7365
362c698f
PB		 7366static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7367{
bf9f6ac8
FW		 7368 if (!kvm_arch_vcpu_runnable(vcpu) &&
7369 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7370 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7371 kvm_vcpu_block(vcpu);
7372 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7373
7374 if (kvm_x86_ops->post_block)
7375 kvm_x86_ops->post_block(vcpu);
7376
9c8fd1ba
PB		 7377 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7378 return 1;
7379 }
362c698f
PB		 7380
7381 kvm_apic_accept_events(vcpu);
7382 switch(vcpu->arch.mp_state) {
7383 case KVM_MP_STATE_HALTED:
7384 vcpu->arch.pv.pv_unhalted = false;
7385 vcpu->arch.mp_state =
7386 KVM_MP_STATE_RUNNABLE;
7387 case KVM_MP_STATE_RUNNABLE:
7388 vcpu->arch.apf.halted = false;
7389 break;
7390 case KVM_MP_STATE_INIT_RECEIVED:
7391 break;
7392 default:
7393 return -EINTR;
7394 break;
7395 }
7396 return 1;
7397}
09cec754 7398
5d9bc648
PB		 7399static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7400{
0ad3bed6
PB		 7401 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7402 kvm_x86_ops->check_nested_events(vcpu, false);
7403
5d9bc648
PB		 7404 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7405 !vcpu->arch.apf.halted);
7406}
7407
362c698f 7408static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7409{
7410 int r;
f656ce01 7411 struct kvm *kvm = vcpu->kvm;
d7690175 7412
f656ce01 7413 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7414
362c698f 7415 for (;;) {
58f800d5 7416 if (kvm_vcpu_running(vcpu)) {
851ba692 7417 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7418 } else {
362c698f 7419 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7420 }
7421
09cec754
GN		 7422 if (r <= 0)
7423 break;
7424
72875d8a 7425 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7426 if (kvm_cpu_has_pending_timer(vcpu))
7427 kvm_inject_pending_timer_irqs(vcpu);
7428
782d422b
MG		 7429 if (dm_request_for_irq_injection(vcpu) &&
7430 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7431 r = 0;
7432 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7433 ++vcpu->stat.request_irq_exits;
362c698f 7434 break;
09cec754 7435 }
af585b92
GN		 7436
7437 kvm_check_async_pf_completion(vcpu);
7438
09cec754
GN		 7439 if (signal_pending(current)) {
7440 r = -EINTR;
851ba692 7441 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7442 ++vcpu->stat.signal_exits;
362c698f 7443 break;
09cec754
GN		 7444 }
7445 if (need_resched()) {
f656ce01 7446 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7447 cond_resched();
f656ce01 7448 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7449 }
b6c7a5dc
HB		 7450 }
7451
f656ce01 7452 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7453
7454 return r;
7455}
7456
716d51ab
GN		 7457static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7458{
7459 int r;
7460 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7461 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7462 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7463 if (r != EMULATE_DONE)
7464 return 0;
7465 return 1;
7466}
7467
7468static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7469{
7470 BUG_ON(!vcpu->arch.pio.count);
7471
7472 return complete_emulated_io(vcpu);
7473}
7474
f78146b0
AK		 7475/*
7476 * Implements the following, as a state machine:
7477 *
7478 * read:
7479 * for each fragment
87da7e66
XG		 7480 * for each mmio piece in the fragment
7481 * write gpa, len
7482 * exit
7483 * copy data
f78146b0
AK		 7484 * execute insn
7485 *
7486 * write:
7487 * for each fragment
87da7e66
XG		 7488 * for each mmio piece in the fragment
7489 * write gpa, len
7490 * copy data
7491 * exit
f78146b0 7492 */
716d51ab 7493static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7494{
7495 struct kvm_run *run = vcpu->run;
f78146b0 7496 struct kvm_mmio_fragment *frag;
87da7e66 7497 unsigned len;
5287f194 7498
716d51ab 7499 BUG_ON(!vcpu->mmio_needed);
5287f194 7500
716d51ab 7501 /* Complete previous fragment */
87da7e66
XG		 7502 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7503 len = min(8u, frag->len);
716d51ab 7504 if (!vcpu->mmio_is_write)
87da7e66
XG		 7505 memcpy(frag->data, run->mmio.data, len);
7506
7507 if (frag->len <= 8) {
7508 /* Switch to the next fragment. */
7509 frag++;
7510 vcpu->mmio_cur_fragment++;
7511 } else {
7512 /* Go forward to the next mmio piece. */
7513 frag->data += len;
7514 frag->gpa += len;
7515 frag->len -= len;
7516 }
7517
a08d3b3b 7518 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7519 vcpu->mmio_needed = 0;
0912c977
PB		 7520
7521 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7522 if (vcpu->mmio_is_write)
716d51ab
GN		 7523 return 1;
7524 vcpu->mmio_read_completed = 1;
7525 return complete_emulated_io(vcpu);
7526 }
87da7e66 7527
716d51ab
GN		 7528 run->exit_reason = KVM_EXIT_MMIO;
7529 run->mmio.phys_addr = frag->gpa;
7530 if (vcpu->mmio_is_write)
87da7e66
XG		 7531 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7532 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7533 run->mmio.is_write = vcpu->mmio_is_write;
7534 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7535 return 0;
5287f194
AK		 7536}
7537
b6c7a5dc
HB		 7538int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7539{
7540 int r;
b6c7a5dc 7541
accb757d 7542 vcpu_load(vcpu);
20b7035c 7543 kvm_sigset_activate(vcpu);
5663d8f9
PX		 7544 kvm_load_guest_fpu(vcpu);
7545
a4535290 7546 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7547 if (kvm_run->immediate_exit) {
7548 r = -EINTR;
7549 goto out;
7550 }
b6c7a5dc 7551 kvm_vcpu_block(vcpu);
66450a21 7552 kvm_apic_accept_events(vcpu);
72875d8a 7553 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7554 r = -EAGAIN;
a0595000
JS		 7555 if (signal_pending(current)) {
7556 r = -EINTR;
7557 vcpu->run->exit_reason = KVM_EXIT_INTR;
7558 ++vcpu->stat.signal_exits;
7559 }
ac9f6dc0 7560 goto out;
b6c7a5dc
HB		 7561 }
7562
01643c51
KH		 7563 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
7564 r = -EINVAL;
7565 goto out;
7566 }
7567
7568 if (vcpu->run->kvm_dirty_regs) {
7569 r = sync_regs(vcpu);
7570 if (r != 0)
7571 goto out;
7572 }
7573
b6c7a5dc 7574 /* re-sync apic's tpr */
35754c98 7575 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7576 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7577 r = -EINVAL;
7578 goto out;
7579 }
7580 }
b6c7a5dc 7581
716d51ab
GN		 7582 if (unlikely(vcpu->arch.complete_userspace_io)) {
7583 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7584 vcpu->arch.complete_userspace_io = NULL;
7585 r = cui(vcpu);
7586 if (r <= 0)
5663d8f9 7587 goto out;
716d51ab
GN		 7588 } else
7589 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7590
460df4c1
PB		 7591 if (kvm_run->immediate_exit)
7592 r = -EINTR;
7593 else
7594 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7595
7596out:
5663d8f9 7597 kvm_put_guest_fpu(vcpu);
01643c51
KH		 7598 if (vcpu->run->kvm_valid_regs)
7599 store_regs(vcpu);
f1d86e46 7600 post_kvm_run_save(vcpu);
20b7035c 7601 kvm_sigset_deactivate(vcpu);
b6c7a5dc 7602
accb757d 7603 vcpu_put(vcpu);
b6c7a5dc
HB		 7604 return r;
7605}
7606
01643c51 7607static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7608{
7ae441ea
GN		 7609 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7610 /*
7611 * We are here if userspace calls get_regs() in the middle of
7612 * instruction emulation. Registers state needs to be copied
4a969980 7613 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7614 * that usually, but some bad designed PV devices (vmware
7615 * backdoor interface) need this to work
7616 */
dd856efa 7617 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7618 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7619 }
5fdbf976
MT		 7620 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7621 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7622 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7623 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7624 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7625 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7626 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7627 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7628#ifdef CONFIG_X86_64
5fdbf976
MT		 7629 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7630 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7631 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7632 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7633 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7634 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7635 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7636 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7637#endif
7638
5fdbf976 7639 regs->rip = kvm_rip_read(vcpu);
91586a3b 7640 regs->rflags = kvm_get_rflags(vcpu);
01643c51 7641}
b6c7a5dc 7642
01643c51
KH		 7643int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7644{
7645 vcpu_load(vcpu);
7646 __get_regs(vcpu, regs);
1fc9b76b 7647 vcpu_put(vcpu);
b6c7a5dc
HB		 7648 return 0;
7649}
7650
01643c51 7651static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7652{
7ae441ea
GN		 7653 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7654 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7655
5fdbf976
MT		 7656 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7657 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7658 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7659 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7660 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7661 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7662 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7663 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7664#ifdef CONFIG_X86_64
5fdbf976
MT		 7665 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7666 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7667 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7668 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7669 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7670 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7671 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7672 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7673#endif
7674
5fdbf976 7675 kvm_rip_write(vcpu, regs->rip);
d73235d1 7676 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 7677
b4f14abd
JK		 7678 vcpu->arch.exception.pending = false;
7679
3842d135 7680 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 7681}
3842d135 7682
01643c51
KH		 7683int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7684{
7685 vcpu_load(vcpu);
7686 __set_regs(vcpu, regs);
875656fe 7687 vcpu_put(vcpu);
b6c7a5dc
HB		 7688 return 0;
7689}
7690
b6c7a5dc
HB		 7691void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7692{
7693 struct kvm_segment cs;
7694
3e6e0aab 7695 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7696 *db = cs.db;
7697 *l = cs.l;
7698}
7699EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7700
01643c51 7701static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 7702{
89a27f4d 7703 struct desc_ptr dt;
b6c7a5dc 7704
3e6e0aab
GT		 7705 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7706 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7707 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7708 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7709 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7710 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7711
3e6e0aab
GT		 7712 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7713 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7714
7715 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7716 sregs->idt.limit = dt.size;
7717 sregs->idt.base = dt.address;
b6c7a5dc 7718 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7719 sregs->gdt.limit = dt.size;
7720 sregs->gdt.base = dt.address;
b6c7a5dc 7721
4d4ec087 7722 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7723 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7724 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7725 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7726 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7727 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7728 sregs->apic_base = kvm_get_apic_base(vcpu);
7729
923c61bb 7730 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7731
36752c9b 7732 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7733 set_bit(vcpu->arch.interrupt.nr,
7734 (unsigned long *)sregs->interrupt_bitmap);
01643c51 7735}
16d7a191 7736
01643c51
KH		 7737int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7738 struct kvm_sregs *sregs)
7739{
7740 vcpu_load(vcpu);
7741 __get_sregs(vcpu, sregs);
bcdec41c 7742 vcpu_put(vcpu);
b6c7a5dc
HB		 7743 return 0;
7744}
7745
62d9f0db
MT		 7746int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7747 struct kvm_mp_state *mp_state)
7748{
fd232561
CD		 7749 vcpu_load(vcpu);
7750
66450a21 7751 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7752 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7753 vcpu->arch.pv.pv_unhalted)
7754 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7755 else
7756 mp_state->mp_state = vcpu->arch.mp_state;
7757
fd232561 7758 vcpu_put(vcpu);
62d9f0db
MT		 7759 return 0;
7760}
7761
7762int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7763 struct kvm_mp_state *mp_state)
7764{
e83dff5e
CD		 7765 int ret = -EINVAL;
7766
7767 vcpu_load(vcpu);
7768
bce87cce 7769 if (!lapic_in_kernel(vcpu) &&
66450a21 7770 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 7771 goto out;
66450a21 7772
28bf2888
DH		 7773 /* INITs are latched while in SMM */
7774 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7775 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7776 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 7777 goto out;
28bf2888 7778
66450a21
JK		 7779 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7780 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7781 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7782 } else
7783 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7784 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 7785
7786 ret = 0;
7787out:
7788 vcpu_put(vcpu);
7789 return ret;
62d9f0db
MT		 7790}
7791
7f3d35fd
KW		 7792int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7793 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7794{
9d74191a 7795 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7796 int ret;
e01c2426 7797
8ec4722d 7798 init_emulate_ctxt(vcpu);
c697518a 7799
7f3d35fd 7800 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7801 has_error_code, error_code);
c697518a 7802
c697518a 7803 if (ret)
19d04437 7804 return EMULATE_FAIL;
37817f29 7805
9d74191a
TY		 7806 kvm_rip_write(vcpu, ctxt->eip);
7807 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7808 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7809 return EMULATE_DONE;
37817f29
IE		 7810}
7811EXPORT_SYMBOL_GPL(kvm_task_switch);
7812
f2981033
LT		 7813int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
7814{
37b95951 7815 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 7816 /*
7817 * When EFER.LME and CR0.PG are set, the processor is in
7818 * 64-bit mode (though maybe in a 32-bit code segment).
7819 * CR4.PAE and EFER.LMA must be set.
7820 */
37b95951 7821 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 7822 || !(sregs->efer & EFER_LMA))
7823 return -EINVAL;
7824 } else {
7825 /*
7826 * Not in 64-bit mode: EFER.LMA is clear and the code
7827 * segment cannot be 64-bit.
7828 */
7829 if (sregs->efer & EFER_LMA || sregs->cs.l)
7830 return -EINVAL;
7831 }
7832
7833 return 0;
7834}
7835
01643c51 7836static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 7837{
58cb628d 7838 struct msr_data apic_base_msr;
b6c7a5dc 7839 int mmu_reset_needed = 0;
63f42e02 7840 int pending_vec, max_bits, idx;
89a27f4d 7841 struct desc_ptr dt;
b4ef9d4e
CD		 7842 int ret = -EINVAL;
7843
d6321d49
RK		 7844 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7845 (sregs->cr4 & X86_CR4_OSXSAVE))
b4ef9d4e 7846 goto out;
6d1068b3 7847
f2981033 7848 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 7849 goto out;
f2981033 7850
d3802286
JM		 7851 apic_base_msr.data = sregs->apic_base;
7852 apic_base_msr.host_initiated = true;
7853 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 7854 goto out;
6d1068b3 7855
89a27f4d
GN		 7856 dt.size = sregs->idt.limit;
7857 dt.address = sregs->idt.base;
b6c7a5dc 7858 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7859 dt.size = sregs->gdt.limit;
7860 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7861 kvm_x86_ops->set_gdt(vcpu, &dt);
7862
ad312c7c 7863 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7864 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7865 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7866 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7867
2d3ad1f4 7868 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7869
f6801dff 7870 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7871 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 7872
4d4ec087 7873 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7874 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7875 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7876
fc78f519 7877 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7878 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7879 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7880 kvm_update_cpuid(vcpu);
63f42e02
XG		 7881
7882 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7883 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7884 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7885 mmu_reset_needed = 1;
7886 }
63f42e02 7887 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7888
7889 if (mmu_reset_needed)
7890 kvm_mmu_reset_context(vcpu);
7891
a50abc3b 7892 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7893 pending_vec = find_first_bit(
7894 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7895 if (pending_vec < max_bits) {
66fd3f7f 7896 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7897 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7898 }
7899
3e6e0aab
GT		 7900 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7901 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7902 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7903 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7904 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7905 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7906
3e6e0aab
GT		 7907 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7908 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7909
5f0269f5
ME		 7910 update_cr8_intercept(vcpu);
7911
9c3e4aab 7912 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7913 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7914 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7915 !is_protmode(vcpu))
9c3e4aab
MT		 7916 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7917
3842d135
AK		 7918 kvm_make_request(KVM_REQ_EVENT, vcpu);
7919
b4ef9d4e
CD		 7920 ret = 0;
7921out:
01643c51
KH		 7922 return ret;
7923}
7924
7925int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7926 struct kvm_sregs *sregs)
7927{
7928 int ret;
7929
7930 vcpu_load(vcpu);
7931 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 7932 vcpu_put(vcpu);
7933 return ret;
b6c7a5dc
HB		 7934}
7935
d0bfb940
JK		 7936int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7937 struct kvm_guest_debug *dbg)
b6c7a5dc 7938{
355be0b9 7939 unsigned long rflags;
ae675ef0 7940 int i, r;
b6c7a5dc 7941
66b56562
CD		 7942 vcpu_load(vcpu);
7943
4f926bf2
JK		 7944 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7945 r = -EBUSY;
7946 if (vcpu->arch.exception.pending)
2122ff5e 7947 goto out;
4f926bf2
JK		 7948 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7949 kvm_queue_exception(vcpu, DB_VECTOR);
7950 else
7951 kvm_queue_exception(vcpu, BP_VECTOR);
7952 }
7953
91586a3b
JK		 7954 /*
7955 * Read rflags as long as potentially injected trace flags are still
7956 * filtered out.
7957 */
7958 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7959
7960 vcpu->guest_debug = dbg->control;
7961 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7962 vcpu->guest_debug = 0;
7963
7964 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7965 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7966 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7967 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7968 } else {
7969 for (i = 0; i < KVM_NR_DB_REGS; i++)
7970 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7971 }
c8639010 7972 kvm_update_dr7(vcpu);
ae675ef0 7973
f92653ee
JK		 7974 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7975 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7976 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7977
91586a3b
JK		 7978 /*
7979 * Trigger an rflags update that will inject or remove the trace
7980 * flags.
7981 */
7982 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7983
a96036b8 7984 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7985
4f926bf2 7986 r = 0;
d0bfb940 7987
2122ff5e 7988out:
66b56562 7989 vcpu_put(vcpu);
b6c7a5dc
HB		 7990 return r;
7991}
7992
8b006791
ZX		 7993/*
7994 * Translate a guest virtual address to a guest physical address.
7995 */
7996int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7997 struct kvm_translation *tr)
7998{
7999 unsigned long vaddr = tr->linear_address;
8000 gpa_t gpa;
f656ce01 8001 int idx;
8b006791 8002
1da5b61d
CD		 8003 vcpu_load(vcpu);
8004
f656ce01 8005 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8006 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8007 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8008 tr->physical_address = gpa;
8009 tr->valid = gpa != UNMAPPED_GVA;
8010 tr->writeable = 1;
8011 tr->usermode = 0;
8b006791 8012
1da5b61d 8013 vcpu_put(vcpu);
8b006791
ZX		 8014 return 0;
8015}
8016
d0752060
HB		 8017int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8018{
1393123e 8019 struct fxregs_state *fxsave;
d0752060 8020
1393123e 8021 vcpu_load(vcpu);
d0752060 8022
1393123e 8023 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060
HB		 8024 memcpy(fpu->fpr, fxsave->st_space, 128);
8025 fpu->fcw = fxsave->cwd;
8026 fpu->fsw = fxsave->swd;
8027 fpu->ftwx = fxsave->twd;
8028 fpu->last_opcode = fxsave->fop;
8029 fpu->last_ip = fxsave->rip;
8030 fpu->last_dp = fxsave->rdp;
8031 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
8032
1393123e 8033 vcpu_put(vcpu);
d0752060
HB		 8034 return 0;
8035}
8036
8037int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8038{
6a96bc7f
CD		 8039 struct fxregs_state *fxsave;
8040
8041 vcpu_load(vcpu);
8042
8043 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060 8044
d0752060
HB		 8045 memcpy(fxsave->st_space, fpu->fpr, 128);
8046 fxsave->cwd = fpu->fcw;
8047 fxsave->swd = fpu->fsw;
8048 fxsave->twd = fpu->ftwx;
8049 fxsave->fop = fpu->last_opcode;
8050 fxsave->rip = fpu->last_ip;
8051 fxsave->rdp = fpu->last_dp;
8052 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
8053
6a96bc7f 8054 vcpu_put(vcpu);
d0752060
HB		 8055 return 0;
8056}
8057
01643c51
KH		 8058static void store_regs(struct kvm_vcpu *vcpu)
8059{
8060 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8061
8062 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8063 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8064
8065 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8066 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8067
8068 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8069 kvm_vcpu_ioctl_x86_get_vcpu_events(
8070 vcpu, &vcpu->run->s.regs.events);
8071}
8072
8073static int sync_regs(struct kvm_vcpu *vcpu)
8074{
8075 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8076 return -EINVAL;
8077
8078 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8079 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8080 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8081 }
8082 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8083 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8084 return -EINVAL;
8085 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8086 }
8087 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8088 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8089 vcpu, &vcpu->run->s.regs.events))
8090 return -EINVAL;
8091 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8092 }
8093
8094 return 0;
8095}
8096
0ee6a517 8097static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8098{
bf935b0b 8099 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 8100 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 8101 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 8102 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 8103
2acf923e
DC		 8104 /*
8105 * Ensure guest xcr0 is valid for loading
8106 */
d91cab78 8107 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 8108
ad312c7c 8109 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 8110}
d0752060 8111
f775b13e 8112/* Swap (qemu) user FPU context for the guest FPU context. */
d0752060
HB		 8113void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8114{
f775b13e
RR		 8115 preempt_disable();
8116 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
38cfd5e3
PB		 8117 /* PKRU is separately restored in kvm_x86_ops->run. */
8118 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
8119 ~XFEATURE_MASK_PKRU);
f775b13e 8120 preempt_enable();
0c04851c 8121 trace_kvm_fpu(1);
d0752060 8122}
d0752060 8123
f775b13e 8124/* When vcpu_run ends, restore user space FPU context. */
d0752060
HB		 8125void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8126{
f775b13e 8127 preempt_disable();
4f836347 8128 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
f775b13e
RR		 8129 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
8130 preempt_enable();
f096ed85 8131 ++vcpu->stat.fpu_reload;
0c04851c 8132 trace_kvm_fpu(0);
d0752060 8133}
e9b11c17
ZX		 8134
8135void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8136{
bd768e14
IY		 8137 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8138
12f9a48f 8139 kvmclock_reset(vcpu);
7f1ea208 8140
e9b11c17 8141 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 8142 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 8143}
8144
8145struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8146 unsigned int id)
8147{
c447e76b
LL		 8148 struct kvm_vcpu *vcpu;
8149
b0c39dc6 8150 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 8151 printk_once(KERN_WARNING
8152 "kvm: SMP vm created on host with unstable TSC; "
8153 "guest TSC will not be reliable\n");
c447e76b
LL		 8154
8155 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8156
c447e76b 8157 return vcpu;
26e5215f 8158}
e9b11c17 8159
26e5215f
AK		 8160int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8161{
19efffa2 8162 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 8163 vcpu_load(vcpu);
d28bc9dd 8164 kvm_vcpu_reset(vcpu, false);
8a3c1a33 8165 kvm_mmu_setup(vcpu);
e9b11c17 8166 vcpu_put(vcpu);
ec7660cc 8167 return 0;
e9b11c17
ZX		 8168}
8169
31928aa5 8170void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 8171{
8fe8ab46 8172 struct msr_data msr;
332967a3 8173 struct kvm *kvm = vcpu->kvm;
42897d86 8174
d3457c87
RK		 8175 kvm_hv_vcpu_postcreate(vcpu);
8176
ec7660cc 8177 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 8178 return;
ec7660cc 8179 vcpu_load(vcpu);
8fe8ab46
WA		 8180 msr.data = 0x0;
8181 msr.index = MSR_IA32_TSC;
8182 msr.host_initiated = true;
8183 kvm_write_tsc(vcpu, &msr);
42897d86 8184 vcpu_put(vcpu);
ec7660cc 8185 mutex_unlock(&vcpu->mutex);
42897d86 8186
630994b3
MT		 8187 if (!kvmclock_periodic_sync)
8188 return;
8189
332967a3
AJ		 8190 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8191 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8192}
8193
d40ccc62 8194void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8195{
344d9588
GN		 8196 vcpu->arch.apf.msr_val = 0;
8197
ec7660cc 8198 vcpu_load(vcpu);
e9b11c17
ZX		 8199 kvm_mmu_unload(vcpu);
8200 vcpu_put(vcpu);
8201
8202 kvm_x86_ops->vcpu_free(vcpu);
8203}
8204
d28bc9dd 8205void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8206{
b7e31be3
RK		 8207 kvm_lapic_reset(vcpu, init_event);
8208
e69fab5d
PB		 8209 vcpu->arch.hflags = 0;
8210
c43203ca 8211 vcpu->arch.smi_pending = 0;
52797bf9 8212 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8213 atomic_set(&vcpu->arch.nmi_queued, 0);
8214 vcpu->arch.nmi_pending = 0;
448fa4a9 8215 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8216 kvm_clear_interrupt_queue(vcpu);
8217 kvm_clear_exception_queue(vcpu);
664f8e26 8218 vcpu->arch.exception.pending = false;
448fa4a9 8219
42dbaa5a 8220 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8221 kvm_update_dr0123(vcpu);
6f43ed01 8222 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8223 kvm_update_dr6(vcpu);
42dbaa5a 8224 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8225 kvm_update_dr7(vcpu);
42dbaa5a 8226
1119022c
NA		 8227 vcpu->arch.cr2 = 0;
8228
3842d135 8229 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8230 vcpu->arch.apf.msr_val = 0;
c9aaa895 8231 vcpu->arch.st.msr_val = 0;
3842d135 8232
12f9a48f
GC		 8233 kvmclock_reset(vcpu);
8234
af585b92
GN		 8235 kvm_clear_async_pf_completion_queue(vcpu);
8236 kvm_async_pf_hash_reset(vcpu);
8237 vcpu->arch.apf.halted = false;
3842d135 8238
a554d207
WL		 8239 if (kvm_mpx_supported()) {
8240 void *mpx_state_buffer;
8241
8242 /*
8243 * To avoid have the INIT path from kvm_apic_has_events() that be
8244 * called with loaded FPU and does not let userspace fix the state.
8245 */
f775b13e
RR		 8246 if (init_event)
8247 kvm_put_guest_fpu(vcpu);
a554d207
WL		 8248 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8249 XFEATURE_MASK_BNDREGS);
8250 if (mpx_state_buffer)
8251 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8252 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8253 XFEATURE_MASK_BNDCSR);
8254 if (mpx_state_buffer)
8255 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 8256 if (init_event)
8257 kvm_load_guest_fpu(vcpu);
a554d207
WL		 8258 }
8259
64d60670 8260 if (!init_event) {
d28bc9dd 8261 kvm_pmu_reset(vcpu);
64d60670 8262 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 8263
8264 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8265 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 8266
8267 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 8268 }
f5132b01 8269
66f7b72e
JS		 8270 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8271 vcpu->arch.regs_avail = ~0;
8272 vcpu->arch.regs_dirty = ~0;
8273
a554d207
WL		 8274 vcpu->arch.ia32_xss = 0;
8275
d28bc9dd 8276 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 8277}
8278
2b4a273b 8279void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 8280{
8281 struct kvm_segment cs;
8282
8283 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8284 cs.selector = vector << 8;
8285 cs.base = vector << 12;
8286 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8287 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 8288}
8289
13a34e06 8290int kvm_arch_hardware_enable(void)
e9b11c17 8291{
ca84d1a2
ZA		 8292 struct kvm *kvm;
8293 struct kvm_vcpu *vcpu;
8294 int i;
0dd6a6ed
ZA		 8295 int ret;
8296 u64 local_tsc;
8297 u64 max_tsc = 0;
8298 bool stable, backwards_tsc = false;
18863bdd
AK		 8299
8300 kvm_shared_msr_cpu_online();
13a34e06 8301 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 8302 if (ret != 0)
8303 return ret;
8304
4ea1636b 8305 local_tsc = rdtsc();
b0c39dc6 8306 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 8307 list_for_each_entry(kvm, &vm_list, vm_list) {
8308 kvm_for_each_vcpu(i, vcpu, kvm) {
8309 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 8310 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8311 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8312 backwards_tsc = true;
8313 if (vcpu->arch.last_host_tsc > max_tsc)
8314 max_tsc = vcpu->arch.last_host_tsc;
8315 }
8316 }
8317 }
8318
8319 /*
8320 * Sometimes, even reliable TSCs go backwards. This happens on
8321 * platforms that reset TSC during suspend or hibernate actions, but
8322 * maintain synchronization. We must compensate. Fortunately, we can
8323 * detect that condition here, which happens early in CPU bringup,
8324 * before any KVM threads can be running. Unfortunately, we can't
8325 * bring the TSCs fully up to date with real time, as we aren't yet far
8326 * enough into CPU bringup that we know how much real time has actually
108b249c 8327 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 8328 * variables that haven't been updated yet.
8329 *
8330 * So we simply find the maximum observed TSC above, then record the
8331 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8332 * the adjustment will be applied. Note that we accumulate
8333 * adjustments, in case multiple suspend cycles happen before some VCPU
8334 * gets a chance to run again. In the event that no KVM threads get a
8335 * chance to run, we will miss the entire elapsed period, as we'll have
8336 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8337 * loose cycle time. This isn't too big a deal, since the loss will be
8338 * uniform across all VCPUs (not to mention the scenario is extremely
8339 * unlikely). It is possible that a second hibernate recovery happens
8340 * much faster than a first, causing the observed TSC here to be
8341 * smaller; this would require additional padding adjustment, which is
8342 * why we set last_host_tsc to the local tsc observed here.
8343 *
8344 * N.B. - this code below runs only on platforms with reliable TSC,
8345 * as that is the only way backwards_tsc is set above. Also note
8346 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8347 * have the same delta_cyc adjustment applied if backwards_tsc
8348 * is detected. Note further, this adjustment is only done once,
8349 * as we reset last_host_tsc on all VCPUs to stop this from being
8350 * called multiple times (one for each physical CPU bringup).
8351 *
4a969980 8352 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 8353 * will be compensated by the logic in vcpu_load, which sets the TSC to
8354 * catchup mode. This will catchup all VCPUs to real time, but cannot
8355 * guarantee that they stay in perfect synchronization.
8356 */
8357 if (backwards_tsc) {
8358 u64 delta_cyc = max_tsc - local_tsc;
8359 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8360 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 8361 kvm_for_each_vcpu(i, vcpu, kvm) {
8362 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8363 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8364 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8365 }
8366
8367 /*
8368 * We have to disable TSC offset matching.. if you were
8369 * booting a VM while issuing an S4 host suspend....
8370 * you may have some problem. Solving this issue is
8371 * left as an exercise to the reader.
8372 */
8373 kvm->arch.last_tsc_nsec = 0;
8374 kvm->arch.last_tsc_write = 0;
8375 }
8376
8377 }
8378 return 0;
e9b11c17
ZX		 8379}
8380
13a34e06 8381void kvm_arch_hardware_disable(void)
e9b11c17 8382{
13a34e06
RK		 8383 kvm_x86_ops->hardware_disable();
8384 drop_user_return_notifiers();
e9b11c17
ZX		 8385}
8386
8387int kvm_arch_hardware_setup(void)
8388{
9e9c3fe4
NA		 8389 int r;
8390
8391 r = kvm_x86_ops->hardware_setup();
8392 if (r != 0)
8393 return r;
8394
35181e86
HZ		 8395 if (kvm_has_tsc_control) {
8396 /*
8397 * Make sure the user can only configure tsc_khz values that
8398 * fit into a signed integer.
8399 * A min value is not calculated needed because it will always
8400 * be 1 on all machines.
8401 */
8402 u64 max = min(0x7fffffffULL,
8403 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8404 kvm_max_guest_tsc_khz = max;
8405
ad721883 8406 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8407 }
ad721883 8408
9e9c3fe4
NA		 8409 kvm_init_msr_list();
8410 return 0;
e9b11c17
ZX		 8411}
8412
8413void kvm_arch_hardware_unsetup(void)
8414{
8415 kvm_x86_ops->hardware_unsetup();
8416}
8417
8418void kvm_arch_check_processor_compat(void *rtn)
8419{
8420 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8421}
8422
8423bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8424{
8425 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8426}
8427EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8428
8429bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8430{
8431 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8432}
8433
54e9818f 8434struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8435EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8436
e9b11c17
ZX		 8437int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8438{
8439 struct page *page;
e9b11c17
ZX		 8440 int r;
8441
b2a05fef 8442 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8443 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8444 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8445 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8446 else
a4535290 8447 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8448
8449 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8450 if (!page) {
8451 r = -ENOMEM;
8452 goto fail;
8453 }
ad312c7c 8454 vcpu->arch.pio_data = page_address(page);
e9b11c17 8455
cc578287 8456 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8457
e9b11c17
ZX		 8458 r = kvm_mmu_create(vcpu);
8459 if (r < 0)
8460 goto fail_free_pio_data;
8461
26de7988 8462 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8463 r = kvm_create_lapic(vcpu);
8464 if (r < 0)
8465 goto fail_mmu_destroy;
54e9818f
GN		 8466 } else
8467 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8468
890ca9ae
HY		 8469 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8470 GFP_KERNEL);
8471 if (!vcpu->arch.mce_banks) {
8472 r = -ENOMEM;
443c39bc 8473 goto fail_free_lapic;
890ca9ae
HY		 8474 }
8475 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8476
f1797359
WY		 8477 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8478 r = -ENOMEM;
f5f48ee1 8479 goto fail_free_mce_banks;
f1797359 8480 }
f5f48ee1 8481
0ee6a517 8482 fx_init(vcpu);
66f7b72e 8483
4344ee98 8484 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8485
5a4f55cd
EK		 8486 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8487
74545705
RK		 8488 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8489
af585b92 8490 kvm_async_pf_hash_reset(vcpu);
f5132b01 8491 kvm_pmu_init(vcpu);
af585b92 8492
1c1a9ce9 8493 vcpu->arch.pending_external_vector = -1;
de63ad4c 8494 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8495
5c919412
AS		 8496 kvm_hv_vcpu_init(vcpu);
8497
e9b11c17 8498 return 0;
0ee6a517 8499
f5f48ee1
SY		 8500fail_free_mce_banks:
8501 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8502fail_free_lapic:
8503 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8504fail_mmu_destroy:
8505 kvm_mmu_destroy(vcpu);
8506fail_free_pio_data:
ad312c7c 8507 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8508fail:
8509 return r;
8510}
8511
8512void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8513{
f656ce01
MT		 8514 int idx;
8515
1f4b34f8 8516 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8517 kvm_pmu_destroy(vcpu);
36cb93fd 8518 kfree(vcpu->arch.mce_banks);
e9b11c17 8519 kvm_free_lapic(vcpu);
f656ce01 8520 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8521 kvm_mmu_destroy(vcpu);
f656ce01 8522 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8523 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8524 if (!lapic_in_kernel(vcpu))
54e9818f 8525 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8526}
d19a9cd2 8527
e790d9ef
RK		 8528void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8529{
ae97a3b8 8530 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8531}
8532
e08b9637 8533int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8534{
e08b9637
CO		 8535 if (type)
8536 return -EINVAL;
8537
6ef768fa 8538 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8539 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8540 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8541 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8542 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8543
5550af4d
SY		 8544 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8545 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8546 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8547 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8548 &kvm->arch.irq_sources_bitmap);
5550af4d 8549
038f8c11 8550 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8551 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 8552 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8553
108b249c 8554 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8555 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8556
7e44e449 8557 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8558 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8559
cbc0236a 8560 kvm_hv_init_vm(kvm);
0eb05bf2 8561 kvm_page_track_init(kvm);
13d268ca 8562 kvm_mmu_init_vm(kvm);
0eb05bf2 8563
03543133
SS		 8564 if (kvm_x86_ops->vm_init)
8565 return kvm_x86_ops->vm_init(kvm);
8566
d89f5eff 8567 return 0;
d19a9cd2
ZX		 8568}
8569
8570static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8571{
ec7660cc 8572 vcpu_load(vcpu);
d19a9cd2
ZX		 8573 kvm_mmu_unload(vcpu);
8574 vcpu_put(vcpu);
8575}
8576
8577static void kvm_free_vcpus(struct kvm *kvm)
8578{
8579 unsigned int i;
988a2cae 8580 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8581
8582 /*
8583 * Unpin any mmu pages first.
8584 */
af585b92
GN		 8585 kvm_for_each_vcpu(i, vcpu, kvm) {
8586 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8587 kvm_unload_vcpu_mmu(vcpu);
af585b92 8588 }
988a2cae
GN		 8589 kvm_for_each_vcpu(i, vcpu, kvm)
8590 kvm_arch_vcpu_free(vcpu);
8591
8592 mutex_lock(&kvm->lock);
8593 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8594 kvm->vcpus[i] = NULL;
d19a9cd2 8595
988a2cae
GN		 8596 atomic_set(&kvm->online_vcpus, 0);
8597 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8598}
8599
ad8ba2cd
SY		 8600void kvm_arch_sync_events(struct kvm *kvm)
8601{
332967a3 8602 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8603 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8604 kvm_free_pit(kvm);
ad8ba2cd
SY		 8605}
8606
1d8007bd 8607int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8608{
8609 int i, r;
25188b99 8610 unsigned long hva;
f0d648bd
PB		 8611 struct kvm_memslots *slots = kvm_memslots(kvm);
8612 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8613
8614 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8615 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8616 return -EINVAL;
9da0e4d5 8617
f0d648bd
PB		 8618 slot = id_to_memslot(slots, id);
8619 if (size) {
b21629da 8620 if (slot->npages)
f0d648bd
PB		 8621 return -EEXIST;
8622
8623 /*
8624 * MAP_SHARED to prevent internal slot pages from being moved
8625 * by fork()/COW.
8626 */
8627 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8628 MAP_SHARED | MAP_ANONYMOUS, 0);
8629 if (IS_ERR((void *)hva))
8630 return PTR_ERR((void *)hva);
8631 } else {
8632 if (!slot->npages)
8633 return 0;
8634
8635 hva = 0;
8636 }
8637
8638 old = *slot;
9da0e4d5 8639 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8640 struct kvm_userspace_memory_region m;
9da0e4d5 8641
1d8007bd
PB		 8642 m.slot = id | (i << 16);
8643 m.flags = 0;
8644 m.guest_phys_addr = gpa;
f0d648bd 8645 m.userspace_addr = hva;
1d8007bd 8646 m.memory_size = size;
9da0e4d5
PB		 8647 r = __kvm_set_memory_region(kvm, &m);
8648 if (r < 0)
8649 return r;
8650 }
8651
103c763c
EB		 8652 if (!size)
8653 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 8654
9da0e4d5
PB		 8655 return 0;
8656}
8657EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8658
1d8007bd 8659int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8660{
8661 int r;
8662
8663 mutex_lock(&kvm->slots_lock);
1d8007bd 8664 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8665 mutex_unlock(&kvm->slots_lock);
8666
8667 return r;
8668}
8669EXPORT_SYMBOL_GPL(x86_set_memory_region);
8670
d19a9cd2
ZX		 8671void kvm_arch_destroy_vm(struct kvm *kvm)
8672{
27469d29
AH		 8673 if (current->mm == kvm->mm) {
8674 /*
8675 * Free memory regions allocated on behalf of userspace,
8676 * unless the the memory map has changed due to process exit
8677 * or fd copying.
8678 */
1d8007bd
PB		 8679 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8680 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8681 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8682 }
03543133
SS		 8683 if (kvm_x86_ops->vm_destroy)
8684 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8685 kvm_pic_destroy(kvm);
8686 kvm_ioapic_destroy(kvm);
d19a9cd2 8687 kvm_free_vcpus(kvm);
af1bae54 8688 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8689 kvm_mmu_uninit_vm(kvm);
2beb6dad 8690 kvm_page_track_cleanup(kvm);
cbc0236a 8691 kvm_hv_destroy_vm(kvm);
d19a9cd2 8692}
0de10343 8693
5587027c 8694void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8695 struct kvm_memory_slot *dont)
8696{
8697 int i;
8698
d89cc617
TY		 8699 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8700 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8701 kvfree(free->arch.rmap[i]);
d89cc617 8702 free->arch.rmap[i] = NULL;
77d11309 8703 }
d89cc617
TY		 8704 if (i == 0)
8705 continue;
8706
8707 if (!dont || free->arch.lpage_info[i - 1] !=
8708 dont->arch.lpage_info[i - 1]) {
548ef284 8709 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8710 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8711 }
8712 }
21ebbeda
XG		 8713
8714 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8715}
8716
5587027c
AK		 8717int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8718 unsigned long npages)
db3fe4eb
TY		 8719{
8720 int i;
8721
d89cc617 8722 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8723 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8724 unsigned long ugfn;
8725 int lpages;
d89cc617 8726 int level = i + 1;
db3fe4eb
TY		 8727
8728 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8729 slot->base_gfn, level) + 1;
8730
d89cc617 8731 slot->arch.rmap[i] =
a7c3e901 8732 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8733 if (!slot->arch.rmap[i])
77d11309 8734 goto out_free;
d89cc617
TY		 8735 if (i == 0)
8736 continue;
77d11309 8737
a7c3e901 8738 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8739 if (!linfo)
db3fe4eb
TY		 8740 goto out_free;
8741
92f94f1e
XG		 8742 slot->arch.lpage_info[i - 1] = linfo;
8743
db3fe4eb 8744 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8745 linfo[0].disallow_lpage = 1;
db3fe4eb 8746 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8747 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8748 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8749 /*
8750 * If the gfn and userspace address are not aligned wrt each
8751 * other, or if explicitly asked to, disable large page
8752 * support for this slot
8753 */
8754 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8755 !kvm_largepages_enabled()) {
8756 unsigned long j;
8757
8758 for (j = 0; j < lpages; ++j)
92f94f1e 8759 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8760 }
8761 }
8762
21ebbeda
XG		 8763 if (kvm_page_track_create_memslot(slot, npages))
8764 goto out_free;
8765
db3fe4eb
TY		 8766 return 0;
8767
8768out_free:
d89cc617 8769 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8770 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8771 slot->arch.rmap[i] = NULL;
8772 if (i == 0)
8773 continue;
8774
548ef284 8775 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8776 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8777 }
8778 return -ENOMEM;
8779}
8780
15f46015 8781void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8782{
e6dff7d1
TY		 8783 /*
8784 * memslots->generation has been incremented.
8785 * mmio generation may have reached its maximum value.
8786 */
54bf36aa 8787 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8788}
8789
f7784b8e
MT		 8790int kvm_arch_prepare_memory_region(struct kvm *kvm,
8791 struct kvm_memory_slot *memslot,
09170a49 8792 const struct kvm_userspace_memory_region *mem,
7b6195a9 8793 enum kvm_mr_change change)
0de10343 8794{
f7784b8e
MT		 8795 return 0;
8796}
8797
88178fd4
KH		 8798static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8799 struct kvm_memory_slot *new)
8800{
8801 /* Still write protect RO slot */
8802 if (new->flags & KVM_MEM_READONLY) {
8803 kvm_mmu_slot_remove_write_access(kvm, new);
8804 return;
8805 }
8806
8807 /*
8808 * Call kvm_x86_ops dirty logging hooks when they are valid.
8809 *
8810 * kvm_x86_ops->slot_disable_log_dirty is called when:
8811 *
8812 * - KVM_MR_CREATE with dirty logging is disabled
8813 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8814 *
8815 * The reason is, in case of PML, we need to set D-bit for any slots
8816 * with dirty logging disabled in order to eliminate unnecessary GPA
8817 * logging in PML buffer (and potential PML buffer full VMEXT). This
8818 * guarantees leaving PML enabled during guest's lifetime won't have
8819 * any additonal overhead from PML when guest is running with dirty
8820 * logging disabled for memory slots.
8821 *
8822 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8823 * to dirty logging mode.
8824 *
8825 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8826 *
8827 * In case of write protect:
8828 *
8829 * Write protect all pages for dirty logging.
8830 *
8831 * All the sptes including the large sptes which point to this
8832 * slot are set to readonly. We can not create any new large
8833 * spte on this slot until the end of the logging.
8834 *
8835 * See the comments in fast_page_fault().
8836 */
8837 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8838 if (kvm_x86_ops->slot_enable_log_dirty)
8839 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8840 else
8841 kvm_mmu_slot_remove_write_access(kvm, new);
8842 } else {
8843 if (kvm_x86_ops->slot_disable_log_dirty)
8844 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8845 }
8846}
8847
f7784b8e 8848void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8849 const struct kvm_userspace_memory_region *mem,
8482644a 8850 const struct kvm_memory_slot *old,
f36f3f28 8851 const struct kvm_memory_slot *new,
8482644a 8852 enum kvm_mr_change change)
f7784b8e 8853{
8482644a 8854 int nr_mmu_pages = 0;
f7784b8e 8855
48c0e4e9
XG		 8856 if (!kvm->arch.n_requested_mmu_pages)
8857 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8858
48c0e4e9 8859 if (nr_mmu_pages)
0de10343 8860 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8861
3ea3b7fa
WL		 8862 /*
8863 * Dirty logging tracks sptes in 4k granularity, meaning that large
8864 * sptes have to be split. If live migration is successful, the guest
8865 * in the source machine will be destroyed and large sptes will be
8866 * created in the destination. However, if the guest continues to run
8867 * in the source machine (for example if live migration fails), small
8868 * sptes will remain around and cause bad performance.
8869 *
8870 * Scan sptes if dirty logging has been stopped, dropping those
8871 * which can be collapsed into a single large-page spte. Later
8872 * page faults will create the large-page sptes.
8873 */
8874 if ((change != KVM_MR_DELETE) &&
8875 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8876 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8877 kvm_mmu_zap_collapsible_sptes(kvm, new);
8878
c972f3b1 8879 /*
88178fd4 8880 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8881 *
88178fd4
KH		 8882 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8883 * been zapped so no dirty logging staff is needed for old slot. For
8884 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8885 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8886 *
8887 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8888 */
88178fd4 8889 if (change != KVM_MR_DELETE)
f36f3f28 8890 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8891}
1d737c8a 8892
2df72e9b 8893void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8894{
6ca18b69 8895 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8896}
8897
2df72e9b
MT		 8898void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8899 struct kvm_memory_slot *slot)
8900{
ae7cd873 8901 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8902}
8903
5d9bc648
PB		 8904static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8905{
8906 if (!list_empty_careful(&vcpu->async_pf.done))
8907 return true;
8908
8909 if (kvm_apic_has_events(vcpu))
8910 return true;
8911
8912 if (vcpu->arch.pv.pv_unhalted)
8913 return true;
8914
a5f01f8e
WL		 8915 if (vcpu->arch.exception.pending)
8916 return true;
8917
47a66eed
Z		 8918 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8919 (vcpu->arch.nmi_pending &&
8920 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 8921 return true;
8922
47a66eed
Z		 8923 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8924 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 8925 return true;
8926
5d9bc648
PB		 8927 if (kvm_arch_interrupt_allowed(vcpu) &&
8928 kvm_cpu_has_interrupt(vcpu))
8929 return true;
8930
1f4b34f8
AS		 8931 if (kvm_hv_has_stimer_pending(vcpu))
8932 return true;
8933
5d9bc648
PB		 8934 return false;
8935}
8936
1d737c8a
ZX		 8937int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8938{
5d9bc648 8939 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8940}
5736199a 8941
199b5763
LM		 8942bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
8943{
de63ad4c 8944 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 8945}
8946
b6d33834 8947int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8948{
b6d33834 8949 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8950}
78646121
GN		 8951
8952int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8953{
8954 return kvm_x86_ops->interrupt_allowed(vcpu);
8955}
229456fc 8956
82b32774 8957unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8958{
82b32774
NA		 8959 if (is_64_bit_mode(vcpu))
8960 return kvm_rip_read(vcpu);
8961 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8962 kvm_rip_read(vcpu));
8963}
8964EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8965
82b32774
NA		 8966bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8967{
8968 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8969}
8970EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8971
94fe45da
JK		 8972unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8973{
8974 unsigned long rflags;
8975
8976 rflags = kvm_x86_ops->get_rflags(vcpu);
8977 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8978 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8979 return rflags;
8980}
8981EXPORT_SYMBOL_GPL(kvm_get_rflags);
8982
6addfc42 8983static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8984{
8985 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8986 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8987 rflags |= X86_EFLAGS_TF;
94fe45da 8988 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8989}
8990
8991void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8992{
8993 __kvm_set_rflags(vcpu, rflags);
3842d135 8994 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8995}
8996EXPORT_SYMBOL_GPL(kvm_set_rflags);
8997
56028d08
GN		 8998void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8999{
9000 int r;
9001
fb67e14f 9002 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 9003 work->wakeup_all)
56028d08
GN		 9004 return;
9005
9006 r = kvm_mmu_reload(vcpu);
9007 if (unlikely(r))
9008 return;
9009
fb67e14f
XG		 9010 if (!vcpu->arch.mmu.direct_map &&
9011 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
9012 return;
9013
56028d08
GN		 9014 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
9015}
9016
af585b92
GN		 9017static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9018{
9019 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9020}
9021
9022static inline u32 kvm_async_pf_next_probe(u32 key)
9023{
9024 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9025}
9026
9027static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9028{
9029 u32 key = kvm_async_pf_hash_fn(gfn);
9030
9031 while (vcpu->arch.apf.gfns[key] != ~0)
9032 key = kvm_async_pf_next_probe(key);
9033
9034 vcpu->arch.apf.gfns[key] = gfn;
9035}
9036
9037static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9038{
9039 int i;
9040 u32 key = kvm_async_pf_hash_fn(gfn);
9041
9042 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9043 (vcpu->arch.apf.gfns[key] != gfn &&
9044 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9045 key = kvm_async_pf_next_probe(key);
9046
9047 return key;
9048}
9049
9050bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9051{
9052 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9053}
9054
9055static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9056{
9057 u32 i, j, k;
9058
9059 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9060 while (true) {
9061 vcpu->arch.apf.gfns[i] = ~0;
9062 do {
9063 j = kvm_async_pf_next_probe(j);
9064 if (vcpu->arch.apf.gfns[j] == ~0)
9065 return;
9066 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9067 /*
9068 * k lies cyclically in ]i,j]
9069 * | i.k.j |
9070 * |....j i.k.| or |.k..j i...|
9071 */
9072 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9073 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9074 i = j;
9075 }
9076}
9077
7c90705b
GN		 9078static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9079{
4e335d9e
PB		 9080
9081 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9082 sizeof(val));
7c90705b
GN		 9083}
9084
9a6e7c39
WL		 9085static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9086{
9087
9088 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9089 sizeof(u32));
9090}
9091
af585b92
GN		 9092void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9093 struct kvm_async_pf *work)
9094{
6389ee94
AK		 9095 struct x86_exception fault;
9096
7c90705b 9097 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 9098 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 9099
9100 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 9101 (vcpu->arch.apf.send_user_only &&
9102 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 9103 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9104 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 9105 fault.vector = PF_VECTOR;
9106 fault.error_code_valid = true;
9107 fault.error_code = 0;
9108 fault.nested_page_fault = false;
9109 fault.address = work->arch.token;
adfe20fb 9110 fault.async_page_fault = true;
6389ee94 9111 kvm_inject_page_fault(vcpu, &fault);
7c90705b 9112 }
af585b92
GN		 9113}
9114
9115void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9116 struct kvm_async_pf *work)
9117{
6389ee94 9118 struct x86_exception fault;
9a6e7c39 9119 u32 val;
6389ee94 9120
f2e10669 9121 if (work->wakeup_all)
7c90705b
GN		 9122 work->arch.token = ~0; /* broadcast wakeup */
9123 else
9124 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 9125 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 9126
9a6e7c39
WL		 9127 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9128 !apf_get_user(vcpu, &val)) {
9129 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9130 vcpu->arch.exception.pending &&
9131 vcpu->arch.exception.nr == PF_VECTOR &&
9132 !apf_put_user(vcpu, 0)) {
9133 vcpu->arch.exception.injected = false;
9134 vcpu->arch.exception.pending = false;
9135 vcpu->arch.exception.nr = 0;
9136 vcpu->arch.exception.has_error_code = false;
9137 vcpu->arch.exception.error_code = 0;
9138 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9139 fault.vector = PF_VECTOR;
9140 fault.error_code_valid = true;
9141 fault.error_code = 0;
9142 fault.nested_page_fault = false;
9143 fault.address = work->arch.token;
9144 fault.async_page_fault = true;
9145 kvm_inject_page_fault(vcpu, &fault);
9146 }
7c90705b 9147 }
e6d53e3b 9148 vcpu->arch.apf.halted = false;
a4fa1635 9149 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 9150}
9151
9152bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9153{
9154 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9155 return true;
9156 else
9bc1f09f 9157 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 9158}
9159
5544eb9b
PB		 9160void kvm_arch_start_assignment(struct kvm *kvm)
9161{
9162 atomic_inc(&kvm->arch.assigned_device_count);
9163}
9164EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9165
9166void kvm_arch_end_assignment(struct kvm *kvm)
9167{
9168 atomic_dec(&kvm->arch.assigned_device_count);
9169}
9170EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9171
9172bool kvm_arch_has_assigned_device(struct kvm *kvm)
9173{
9174 return atomic_read(&kvm->arch.assigned_device_count);
9175}
9176EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9177
e0f0bbc5
AW		 9178void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9179{
9180 atomic_inc(&kvm->arch.noncoherent_dma_count);
9181}
9182EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9183
9184void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9185{
9186 atomic_dec(&kvm->arch.noncoherent_dma_count);
9187}
9188EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9189
9190bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9191{
9192 return atomic_read(&kvm->arch.noncoherent_dma_count);
9193}
9194EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9195
14717e20
AW		 9196bool kvm_arch_has_irq_bypass(void)
9197{
9198 return kvm_x86_ops->update_pi_irte != NULL;
9199}
9200
87276880
FW		 9201int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9202 struct irq_bypass_producer *prod)
9203{
9204 struct kvm_kernel_irqfd *irqfd =
9205 container_of(cons, struct kvm_kernel_irqfd, consumer);
9206
14717e20 9207 irqfd->producer = prod;
87276880 9208
14717e20
AW		 9209 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9210 prod->irq, irqfd->gsi, 1);
87276880
FW		 9211}
9212
9213void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9214 struct irq_bypass_producer *prod)
9215{
9216 int ret;
9217 struct kvm_kernel_irqfd *irqfd =
9218 container_of(cons, struct kvm_kernel_irqfd, consumer);
9219
87276880
FW		 9220 WARN_ON(irqfd->producer != prod);
9221 irqfd->producer = NULL;
9222
9223 /*
9224 * When producer of consumer is unregistered, we change back to
9225 * remapped mode, so we can re-use the current implementation
bb3541f1 9226 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 9227 * int this case doesn't want to receive the interrupts.
9228 */
9229 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9230 if (ret)
9231 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9232 " fails: %d\n", irqfd->consumer.token, ret);
9233}
9234
9235int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9236 uint32_t guest_irq, bool set)
9237{
9238 if (!kvm_x86_ops->update_pi_irte)
9239 return -EINVAL;
9240
9241 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9242}
9243
52004014
FW		 9244bool kvm_vector_hashing_enabled(void)
9245{
9246 return vector_hashing;
9247}
9248EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9249
229456fc 9250EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 9251EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 9252EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9253EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9254EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9255EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 9256EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 9257EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 9258EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 9259EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 9260EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 9261EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 9262EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 9263EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 9264EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 9265EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 9266EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 9267EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9268EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
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