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KVM: IRQ ACK notifier should be used with in-kernel irqchip
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
62c476c7 37#include <linux/intel-iommu.h>
043405e1
CO		 38
39#include <asm/uaccess.h>
d825ed0a 40#include <asm/msr.h>
a5f61300 41#include <asm/desc.h>
0bed3b56 42#include <asm/mtrr.h>
043405e1 43
313a3dc7 44#define MAX_IO_MSRS 256
a03490ed
CO		 45#define CR0_RESERVED_BITS \
46 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
47 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
48 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
49#define CR4_RESERVED_BITS \
50 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
51 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
52 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
53 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
54
55#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
50a37eb4
JR		 56/* EFER defaults:
57 * - enable syscall per default because its emulated by KVM
58 * - enable LME and LMA per default on 64 bit KVM
59 */
60#ifdef CONFIG_X86_64
61static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
62#else
63static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
64#endif
313a3dc7 65
ba1389b7
AK		 66#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
67#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 68
674eea0f
AK		 69static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
70 struct kvm_cpuid_entry2 __user *entries);
71
97896d04 72struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 73EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 74
417bc304 75struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 76 { "pf_fixed", VCPU_STAT(pf_fixed) },
77 { "pf_guest", VCPU_STAT(pf_guest) },
78 { "tlb_flush", VCPU_STAT(tlb_flush) },
79 { "invlpg", VCPU_STAT(invlpg) },
80 { "exits", VCPU_STAT(exits) },
81 { "io_exits", VCPU_STAT(io_exits) },
82 { "mmio_exits", VCPU_STAT(mmio_exits) },
83 { "signal_exits", VCPU_STAT(signal_exits) },
84 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 85 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 86 { "halt_exits", VCPU_STAT(halt_exits) },
87 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 88 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7 89 { "request_irq", VCPU_STAT(request_irq_exits) },
c4abb7c9 90 { "request_nmi", VCPU_STAT(request_nmi_exits) },
ba1389b7
AK		 91 { "irq_exits", VCPU_STAT(irq_exits) },
92 { "host_state_reload", VCPU_STAT(host_state_reload) },
93 { "efer_reload", VCPU_STAT(efer_reload) },
94 { "fpu_reload", VCPU_STAT(fpu_reload) },
95 { "insn_emulation", VCPU_STAT(insn_emulation) },
96 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 97 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 98 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 99 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
100 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
101 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
102 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
103 { "mmu_flooded", VM_STAT(mmu_flooded) },
104 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 105 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 106 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 107 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 108 { "largepages", VM_STAT(lpages) },
417bc304
HB		 109 { NULL }
110};
111
5fb76f9b
CO		 112unsigned long segment_base(u16 selector)
113{
114 struct descriptor_table gdt;
a5f61300 115 struct desc_struct *d;
5fb76f9b
CO		 116 unsigned long table_base;
117 unsigned long v;
118
119 if (selector == 0)
120 return 0;
121
122 asm("sgdt %0" : "=m"(gdt));
123 table_base = gdt.base;
124
125 if (selector & 4) { /* from ldt */
126 u16 ldt_selector;
127
128 asm("sldt %0" : "=g"(ldt_selector));
129 table_base = segment_base(ldt_selector);
130 }
a5f61300
AK		 131 d = (struct desc_struct *)(table_base + (selector & ~7));
132 v = d->base0 | ((unsigned long)d->base1 << 16) |
133 ((unsigned long)d->base2 << 24);
5fb76f9b 134#ifdef CONFIG_X86_64
a5f61300
AK		 135 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
136 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 137#endif
138 return v;
139}
140EXPORT_SYMBOL_GPL(segment_base);
141
6866b83e
CO		 142u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
143{
144 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 145 return vcpu->arch.apic_base;
6866b83e 146 else
ad312c7c 147 return vcpu->arch.apic_base;
6866b83e
CO		 148}
149EXPORT_SYMBOL_GPL(kvm_get_apic_base);
150
151void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
152{
153 /* TODO: reserve bits check */
154 if (irqchip_in_kernel(vcpu->kvm))
155 kvm_lapic_set_base(vcpu, data);
156 else
ad312c7c 157 vcpu->arch.apic_base = data;
6866b83e
CO		 158}
159EXPORT_SYMBOL_GPL(kvm_set_apic_base);
160
298101da
AK		 161void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
162{
ad312c7c
ZX		 163 WARN_ON(vcpu->arch.exception.pending);
164 vcpu->arch.exception.pending = true;
165 vcpu->arch.exception.has_error_code = false;
166 vcpu->arch.exception.nr = nr;
298101da
AK		 167}
168EXPORT_SYMBOL_GPL(kvm_queue_exception);
169
c3c91fee
AK		 170void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
171 u32 error_code)
172{
173 ++vcpu->stat.pf_guest;
71c4dfaf
JR		 174 if (vcpu->arch.exception.pending) {
175 if (vcpu->arch.exception.nr == PF_VECTOR) {
176 printk(KERN_DEBUG "kvm: inject_page_fault:"
177 " double fault 0x%lx\n", addr);
178 vcpu->arch.exception.nr = DF_VECTOR;
179 vcpu->arch.exception.error_code = 0;
180 } else if (vcpu->arch.exception.nr == DF_VECTOR) {
181 /* triple fault -> shutdown */
182 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
183 }
c3c91fee
AK		 184 return;
185 }
ad312c7c 186 vcpu->arch.cr2 = addr;
c3c91fee
AK		 187 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
188}
189
3419ffc8
SY		 190void kvm_inject_nmi(struct kvm_vcpu *vcpu)
191{
192 vcpu->arch.nmi_pending = 1;
193}
194EXPORT_SYMBOL_GPL(kvm_inject_nmi);
195
298101da
AK		 196void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
197{
ad312c7c
ZX		 198 WARN_ON(vcpu->arch.exception.pending);
199 vcpu->arch.exception.pending = true;
200 vcpu->arch.exception.has_error_code = true;
201 vcpu->arch.exception.nr = nr;
202 vcpu->arch.exception.error_code = error_code;
298101da
AK		 203}
204EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
205
206static void __queue_exception(struct kvm_vcpu *vcpu)
207{
ad312c7c
ZX		 208 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
209 vcpu->arch.exception.has_error_code,
210 vcpu->arch.exception.error_code);
298101da
AK		 211}
212
a03490ed
CO		 213/*
214 * Load the pae pdptrs. Return true is they are all valid.
215 */
216int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
217{
218 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
219 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
220 int i;
221 int ret;
ad312c7c 222 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 223
a03490ed
CO		 224 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
225 offset * sizeof(u64), sizeof(pdpte));
226 if (ret < 0) {
227 ret = 0;
228 goto out;
229 }
230 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
231 if ((pdpte[i] & 1) && (pdpte[i] & 0xfffffff0000001e6ull)) {
232 ret = 0;
233 goto out;
234 }
235 }
236 ret = 1;
237
ad312c7c 238 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
a03490ed 239out:
a03490ed
CO		 240
241 return ret;
242}
cc4b6871 243EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 244
d835dfec
AK		 245static bool pdptrs_changed(struct kvm_vcpu *vcpu)
246{
ad312c7c 247 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 248 bool changed = true;
249 int r;
250
251 if (is_long_mode(vcpu) || !is_pae(vcpu))
252 return false;
253
ad312c7c 254 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 255 if (r < 0)
256 goto out;
ad312c7c 257 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 258out:
d835dfec
AK		 259
260 return changed;
261}
262
2d3ad1f4 263void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 264{
265 if (cr0 & CR0_RESERVED_BITS) {
266 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 267 cr0, vcpu->arch.cr0);
c1a5d4f9 268 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 269 return;
270 }
271
272 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
273 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 274 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 275 return;
276 }
277
278 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
279 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
280 "and a clear PE flag\n");
c1a5d4f9 281 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 282 return;
283 }
284
285 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
286#ifdef CONFIG_X86_64
ad312c7c 287 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 288 int cs_db, cs_l;
289
290 if (!is_pae(vcpu)) {
291 printk(KERN_DEBUG "set_cr0: #GP, start paging "
292 "in long mode while PAE is disabled\n");
c1a5d4f9 293 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 294 return;
295 }
296 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
297 if (cs_l) {
298 printk(KERN_DEBUG "set_cr0: #GP, start paging "
299 "in long mode while CS.L == 1\n");
c1a5d4f9 300 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 301 return;
302
303 }
304 } else
305#endif
ad312c7c 306 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 307 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
308 "reserved bits\n");
c1a5d4f9 309 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 310 return;
311 }
312
313 }
314
315 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 316 vcpu->arch.cr0 = cr0;
a03490ed 317
a03490ed 318 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 319 return;
320}
2d3ad1f4 321EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 322
2d3ad1f4 323void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 324{
2d3ad1f4 325 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
2714d1d3
FEL		 326 KVMTRACE_1D(LMSW, vcpu,
327 (u32)((vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f)),
328 handler);
a03490ed 329}
2d3ad1f4 330EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 331
2d3ad1f4 332void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed
CO		 333{
334 if (cr4 & CR4_RESERVED_BITS) {
335 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 336 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 337 return;
338 }
339
340 if (is_long_mode(vcpu)) {
341 if (!(cr4 & X86_CR4_PAE)) {
342 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
343 "in long mode\n");
c1a5d4f9 344 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 345 return;
346 }
347 } else if (is_paging(vcpu) && !is_pae(vcpu) && (cr4 & X86_CR4_PAE)
ad312c7c 348 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 349 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 350 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 351 return;
352 }
353
354 if (cr4 & X86_CR4_VMXE) {
355 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 356 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 357 return;
358 }
359 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 360 vcpu->arch.cr4 = cr4;
a03490ed 361 kvm_mmu_reset_context(vcpu);
a03490ed 362}
2d3ad1f4 363EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 364
2d3ad1f4 365void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 366{
ad312c7c 367 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 368 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 369 kvm_mmu_flush_tlb(vcpu);
370 return;
371 }
372
a03490ed
CO		 373 if (is_long_mode(vcpu)) {
374 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
375 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 376 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 377 return;
378 }
379 } else {
380 if (is_pae(vcpu)) {
381 if (cr3 & CR3_PAE_RESERVED_BITS) {
382 printk(KERN_DEBUG
383 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 384 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 385 return;
386 }
387 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
388 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
389 "reserved bits\n");
c1a5d4f9 390 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 391 return;
392 }
393 }
394 /*
395 * We don't check reserved bits in nonpae mode, because
396 * this isn't enforced, and VMware depends on this.
397 */
398 }
399
a03490ed
CO		 400 /*
401 * Does the new cr3 value map to physical memory? (Note, we
402 * catch an invalid cr3 even in real-mode, because it would
403 * cause trouble later on when we turn on paging anyway.)
404 *
405 * A real CPU would silently accept an invalid cr3 and would
406 * attempt to use it - with largely undefined (and often hard
407 * to debug) behavior on the guest side.
408 */
409 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 410 kvm_inject_gp(vcpu, 0);
a03490ed 411 else {
ad312c7c
ZX		 412 vcpu->arch.cr3 = cr3;
413 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 414 }
a03490ed 415}
2d3ad1f4 416EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 417
2d3ad1f4 418void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 419{
420 if (cr8 & CR8_RESERVED_BITS) {
421 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 422 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 423 return;
424 }
425 if (irqchip_in_kernel(vcpu->kvm))
426 kvm_lapic_set_tpr(vcpu, cr8);
427 else
ad312c7c 428 vcpu->arch.cr8 = cr8;
a03490ed 429}
2d3ad1f4 430EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 431
2d3ad1f4 432unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 433{
434 if (irqchip_in_kernel(vcpu->kvm))
435 return kvm_lapic_get_cr8(vcpu);
436 else
ad312c7c 437 return vcpu->arch.cr8;
a03490ed 438}
2d3ad1f4 439EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 440
043405e1
CO		 441/*
442 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
443 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
444 *
445 * This list is modified at module load time to reflect the
446 * capabilities of the host cpu.
447 */
448static u32 msrs_to_save[] = {
449 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
450 MSR_K6_STAR,
451#ifdef CONFIG_X86_64
452 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
453#endif
18068523 454 MSR_IA32_TIME_STAMP_COUNTER, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
468d472f 455 MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT
043405e1
CO		 456};
457
458static unsigned num_msrs_to_save;
459
460static u32 emulated_msrs[] = {
461 MSR_IA32_MISC_ENABLE,
462};
463
15c4a640
CO		 464static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
465{
f2b4b7dd 466 if (efer & efer_reserved_bits) {
15c4a640
CO		 467 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
468 efer);
c1a5d4f9 469 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 470 return;
471 }
472
473 if (is_paging(vcpu)
ad312c7c 474 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 475 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 476 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 477 return;
478 }
479
480 kvm_x86_ops->set_efer(vcpu, efer);
481
482 efer &= ~EFER_LMA;
ad312c7c 483 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 484
ad312c7c 485 vcpu->arch.shadow_efer = efer;
15c4a640
CO		 486}
487
f2b4b7dd
JR		 488void kvm_enable_efer_bits(u64 mask)
489{
490 efer_reserved_bits &= ~mask;
491}
492EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
493
494
15c4a640
CO		 495/*
496 * Writes msr value into into the appropriate "register".
497 * Returns 0 on success, non-0 otherwise.
498 * Assumes vcpu_load() was already called.
499 */
500int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
501{
502 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
503}
504
313a3dc7
CO		 505/*
506 * Adapt set_msr() to msr_io()'s calling convention
507 */
508static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
509{
510 return kvm_set_msr(vcpu, index, *data);
511}
512
18068523
GOC		 513static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
514{
515 static int version;
50d0a0f9
GH		 516 struct pvclock_wall_clock wc;
517 struct timespec now, sys, boot;
18068523
GOC		 518
519 if (!wall_clock)
520 return;
521
522 version++;
523
18068523
GOC		 524 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
525
50d0a0f9
GH		 526 /*
527 * The guest calculates current wall clock time by adding
528 * system time (updated by kvm_write_guest_time below) to the
529 * wall clock specified here. guest system time equals host
530 * system time for us, thus we must fill in host boot time here.
531 */
532 now = current_kernel_time();
533 ktime_get_ts(&sys);
534 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
535
536 wc.sec = boot.tv_sec;
537 wc.nsec = boot.tv_nsec;
538 wc.version = version;
18068523
GOC		 539
540 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
541
542 version++;
543 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 544}
545
50d0a0f9
GH		 546static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
547{
548 uint32_t quotient, remainder;
549
550 /* Don't try to replace with do_div(), this one calculates
551 * "(dividend << 32) / divisor" */
552 __asm__ ( "divl %4"
553 : "=a" (quotient), "=d" (remainder)
554 : "0" (0), "1" (dividend), "r" (divisor) );
555 return quotient;
556}
557
558static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
559{
560 uint64_t nsecs = 1000000000LL;
561 int32_t shift = 0;
562 uint64_t tps64;
563 uint32_t tps32;
564
565 tps64 = tsc_khz * 1000LL;
566 while (tps64 > nsecs*2) {
567 tps64 >>= 1;
568 shift--;
569 }
570
571 tps32 = (uint32_t)tps64;
572 while (tps32 <= (uint32_t)nsecs) {
573 tps32 <<= 1;
574 shift++;
575 }
576
577 hv_clock->tsc_shift = shift;
578 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
579
580 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 581 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 582 hv_clock->tsc_to_system_mul);
583}
584
18068523
GOC		 585static void kvm_write_guest_time(struct kvm_vcpu *v)
586{
587 struct timespec ts;
588 unsigned long flags;
589 struct kvm_vcpu_arch *vcpu = &v->arch;
590 void *shared_kaddr;
591
592 if ((!vcpu->time_page))
593 return;
594
50d0a0f9
GH		 595 if (unlikely(vcpu->hv_clock_tsc_khz != tsc_khz)) {
596 kvm_set_time_scale(tsc_khz, &vcpu->hv_clock);
597 vcpu->hv_clock_tsc_khz = tsc_khz;
598 }
599
18068523
GOC		 600 /* Keep irq disabled to prevent changes to the clock */
601 local_irq_save(flags);
602 kvm_get_msr(v, MSR_IA32_TIME_STAMP_COUNTER,
603 &vcpu->hv_clock.tsc_timestamp);
604 ktime_get_ts(&ts);
605 local_irq_restore(flags);
606
607 /* With all the info we got, fill in the values */
608
609 vcpu->hv_clock.system_time = ts.tv_nsec +
610 (NSEC_PER_SEC * (u64)ts.tv_sec);
611 /*
612 * The interface expects us to write an even number signaling that the
613 * update is finished. Since the guest won't see the intermediate
50d0a0f9 614 * state, we just increase by 2 at the end.
18068523 615 */
50d0a0f9 616 vcpu->hv_clock.version += 2;
18068523
GOC		 617
618 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
619
620 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 621 sizeof(vcpu->hv_clock));
18068523
GOC		 622
623 kunmap_atomic(shared_kaddr, KM_USER0);
624
625 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
626}
627
9ba075a6
AK		 628static bool msr_mtrr_valid(unsigned msr)
629{
630 switch (msr) {
631 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
632 case MSR_MTRRfix64K_00000:
633 case MSR_MTRRfix16K_80000:
634 case MSR_MTRRfix16K_A0000:
635 case MSR_MTRRfix4K_C0000:
636 case MSR_MTRRfix4K_C8000:
637 case MSR_MTRRfix4K_D0000:
638 case MSR_MTRRfix4K_D8000:
639 case MSR_MTRRfix4K_E0000:
640 case MSR_MTRRfix4K_E8000:
641 case MSR_MTRRfix4K_F0000:
642 case MSR_MTRRfix4K_F8000:
643 case MSR_MTRRdefType:
644 case MSR_IA32_CR_PAT:
645 return true;
646 case 0x2f8:
647 return true;
648 }
649 return false;
650}
651
652static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
653{
0bed3b56
SY		 654 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
655
9ba075a6
AK		 656 if (!msr_mtrr_valid(msr))
657 return 1;
658
0bed3b56
SY		 659 if (msr == MSR_MTRRdefType) {
660 vcpu->arch.mtrr_state.def_type = data;
661 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
662 } else if (msr == MSR_MTRRfix64K_00000)
663 p[0] = data;
664 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
665 p[1 + msr - MSR_MTRRfix16K_80000] = data;
666 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
667 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
668 else if (msr == MSR_IA32_CR_PAT)
669 vcpu->arch.pat = data;
670 else { /* Variable MTRRs */
671 int idx, is_mtrr_mask;
672 u64 *pt;
673
674 idx = (msr - 0x200) / 2;
675 is_mtrr_mask = msr - 0x200 - 2 * idx;
676 if (!is_mtrr_mask)
677 pt =
678 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
679 else
680 pt =
681 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
682 *pt = data;
683 }
684
685 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 686 return 0;
687}
15c4a640
CO		 688
689int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
690{
691 switch (msr) {
15c4a640
CO		 692 case MSR_EFER:
693 set_efer(vcpu, data);
694 break;
15c4a640
CO		 695 case MSR_IA32_MC0_STATUS:
696 pr_unimpl(vcpu, "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n",
b8688d51 697 __func__, data);
15c4a640
CO		 698 break;
699 case MSR_IA32_MCG_STATUS:
700 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_STATUS 0x%llx, nop\n",
b8688d51 701 __func__, data);
15c4a640 702 break;
c7ac679c
JR		 703 case MSR_IA32_MCG_CTL:
704 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_CTL 0x%llx, nop\n",
b8688d51 705 __func__, data);
c7ac679c 706 break;
b5e2fec0
AG		 707 case MSR_IA32_DEBUGCTLMSR:
708 if (!data) {
709 /* We support the non-activated case already */
710 break;
711 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
712 /* Values other than LBR and BTF are vendor-specific,
713 thus reserved and should throw a #GP */
714 return 1;
715 }
716 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
717 __func__, data);
718 break;
15c4a640
CO		 719 case MSR_IA32_UCODE_REV:
720 case MSR_IA32_UCODE_WRITE:
15c4a640 721 break;
9ba075a6
AK		 722 case 0x200 ... 0x2ff:
723 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 724 case MSR_IA32_APICBASE:
725 kvm_set_apic_base(vcpu, data);
726 break;
727 case MSR_IA32_MISC_ENABLE:
ad312c7c 728 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 729 break;
18068523
GOC		 730 case MSR_KVM_WALL_CLOCK:
731 vcpu->kvm->arch.wall_clock = data;
732 kvm_write_wall_clock(vcpu->kvm, data);
733 break;
734 case MSR_KVM_SYSTEM_TIME: {
735 if (vcpu->arch.time_page) {
736 kvm_release_page_dirty(vcpu->arch.time_page);
737 vcpu->arch.time_page = NULL;
738 }
739
740 vcpu->arch.time = data;
741
742 /* we verify if the enable bit is set... */
743 if (!(data & 1))
744 break;
745
746 /* ...but clean it before doing the actual write */
747 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
748
18068523
GOC		 749 vcpu->arch.time_page =
750 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 751
752 if (is_error_page(vcpu->arch.time_page)) {
753 kvm_release_page_clean(vcpu->arch.time_page);
754 vcpu->arch.time_page = NULL;
755 }
756
757 kvm_write_guest_time(vcpu);
758 break;
759 }
15c4a640 760 default:
565f1fbd 761 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", msr, data);
15c4a640
CO		 762 return 1;
763 }
764 return 0;
765}
766EXPORT_SYMBOL_GPL(kvm_set_msr_common);
767
768
769/*
770 * Reads an msr value (of 'msr_index') into 'pdata'.
771 * Returns 0 on success, non-0 otherwise.
772 * Assumes vcpu_load() was already called.
773 */
774int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
775{
776 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
777}
778
9ba075a6
AK		 779static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
780{
0bed3b56
SY		 781 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
782
9ba075a6
AK		 783 if (!msr_mtrr_valid(msr))
784 return 1;
785
0bed3b56
SY		 786 if (msr == MSR_MTRRdefType)
787 *pdata = vcpu->arch.mtrr_state.def_type +
788 (vcpu->arch.mtrr_state.enabled << 10);
789 else if (msr == MSR_MTRRfix64K_00000)
790 *pdata = p[0];
791 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
792 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
793 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
794 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
795 else if (msr == MSR_IA32_CR_PAT)
796 *pdata = vcpu->arch.pat;
797 else { /* Variable MTRRs */
798 int idx, is_mtrr_mask;
799 u64 *pt;
800
801 idx = (msr - 0x200) / 2;
802 is_mtrr_mask = msr - 0x200 - 2 * idx;
803 if (!is_mtrr_mask)
804 pt =
805 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
806 else
807 pt =
808 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
809 *pdata = *pt;
810 }
811
9ba075a6
AK		 812 return 0;
813}
814
15c4a640
CO		 815int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
816{
817 u64 data;
818
819 switch (msr) {
820 case 0xc0010010: /* SYSCFG */
821 case 0xc0010015: /* HWCR */
822 case MSR_IA32_PLATFORM_ID:
823 case MSR_IA32_P5_MC_ADDR:
824 case MSR_IA32_P5_MC_TYPE:
825 case MSR_IA32_MC0_CTL:
826 case MSR_IA32_MCG_STATUS:
827 case MSR_IA32_MCG_CAP:
c7ac679c 828 case MSR_IA32_MCG_CTL:
15c4a640
CO		 829 case MSR_IA32_MC0_MISC:
830 case MSR_IA32_MC0_MISC+4:
831 case MSR_IA32_MC0_MISC+8:
832 case MSR_IA32_MC0_MISC+12:
833 case MSR_IA32_MC0_MISC+16:
a89c1ad2 834 case MSR_IA32_MC0_MISC+20:
15c4a640 835 case MSR_IA32_UCODE_REV:
15c4a640 836 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 837 case MSR_IA32_DEBUGCTLMSR:
838 case MSR_IA32_LASTBRANCHFROMIP:
839 case MSR_IA32_LASTBRANCHTOIP:
840 case MSR_IA32_LASTINTFROMIP:
841 case MSR_IA32_LASTINTTOIP:
15c4a640
CO		 842 data = 0;
843 break;
9ba075a6
AK		 844 case MSR_MTRRcap:
845 data = 0x500 | KVM_NR_VAR_MTRR;
846 break;
847 case 0x200 ... 0x2ff:
848 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 849 case 0xcd: /* fsb frequency */
850 data = 3;
851 break;
852 case MSR_IA32_APICBASE:
853 data = kvm_get_apic_base(vcpu);
854 break;
855 case MSR_IA32_MISC_ENABLE:
ad312c7c 856 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 857 break;
847f0ad8
AG		 858 case MSR_IA32_PERF_STATUS:
859 /* TSC increment by tick */
860 data = 1000ULL;
861 /* CPU multiplier */
862 data |= (((uint64_t)4ULL) << 40);
863 break;
15c4a640 864 case MSR_EFER:
ad312c7c 865 data = vcpu->arch.shadow_efer;
15c4a640 866 break;
18068523
GOC		 867 case MSR_KVM_WALL_CLOCK:
868 data = vcpu->kvm->arch.wall_clock;
869 break;
870 case MSR_KVM_SYSTEM_TIME:
871 data = vcpu->arch.time;
872 break;
15c4a640
CO		 873 default:
874 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
875 return 1;
876 }
877 *pdata = data;
878 return 0;
879}
880EXPORT_SYMBOL_GPL(kvm_get_msr_common);
881
313a3dc7
CO		 882/*
883 * Read or write a bunch of msrs. All parameters are kernel addresses.
884 *
885 * @return number of msrs set successfully.
886 */
887static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
888 struct kvm_msr_entry *entries,
889 int (*do_msr)(struct kvm_vcpu *vcpu,
890 unsigned index, u64 *data))
891{
892 int i;
893
894 vcpu_load(vcpu);
895
3200f405 896 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 897 for (i = 0; i < msrs->nmsrs; ++i)
898 if (do_msr(vcpu, entries[i].index, &entries[i].data))
899 break;
3200f405 900 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 901
902 vcpu_put(vcpu);
903
904 return i;
905}
906
907/*
908 * Read or write a bunch of msrs. Parameters are user addresses.
909 *
910 * @return number of msrs set successfully.
911 */
912static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
913 int (*do_msr)(struct kvm_vcpu *vcpu,
914 unsigned index, u64 *data),
915 int writeback)
916{
917 struct kvm_msrs msrs;
918 struct kvm_msr_entry *entries;
919 int r, n;
920 unsigned size;
921
922 r = -EFAULT;
923 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
924 goto out;
925
926 r = -E2BIG;
927 if (msrs.nmsrs >= MAX_IO_MSRS)
928 goto out;
929
930 r = -ENOMEM;
931 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
932 entries = vmalloc(size);
933 if (!entries)
934 goto out;
935
936 r = -EFAULT;
937 if (copy_from_user(entries, user_msrs->entries, size))
938 goto out_free;
939
940 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
941 if (r < 0)
942 goto out_free;
943
944 r = -EFAULT;
945 if (writeback && copy_to_user(user_msrs->entries, entries, size))
946 goto out_free;
947
948 r = n;
949
950out_free:
951 vfree(entries);
952out:
953 return r;
954}
955
018d00d2
ZX		 956int kvm_dev_ioctl_check_extension(long ext)
957{
958 int r;
959
960 switch (ext) {
961 case KVM_CAP_IRQCHIP:
962 case KVM_CAP_HLT:
963 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
964 case KVM_CAP_USER_MEMORY:
965 case KVM_CAP_SET_TSS_ADDR:
07716717 966 case KVM_CAP_EXT_CPUID:
18068523 967 case KVM_CAP_CLOCKSOURCE:
7837699f 968 case KVM_CAP_PIT:
a28e4f5a 969 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 970 case KVM_CAP_MP_STATE:
ed848624 971 case KVM_CAP_SYNC_MMU:
018d00d2
ZX		 972 r = 1;
973 break;
542472b5
LV		 974 case KVM_CAP_COALESCED_MMIO:
975 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
976 break;
774ead3a
AK		 977 case KVM_CAP_VAPIC:
978 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
979 break;
f725230a
AK		 980 case KVM_CAP_NR_VCPUS:
981 r = KVM_MAX_VCPUS;
982 break;
a988b910
AK		 983 case KVM_CAP_NR_MEMSLOTS:
984 r = KVM_MEMORY_SLOTS;
985 break;
2f333bcb
MT		 986 case KVM_CAP_PV_MMU:
987 r = !tdp_enabled;
988 break;
62c476c7
BAY		 989 case KVM_CAP_IOMMU:
990 r = intel_iommu_found();
991 break;
018d00d2
ZX		 992 default:
993 r = 0;
994 break;
995 }
996 return r;
997
998}
999
043405e1
CO		 1000long kvm_arch_dev_ioctl(struct file *filp,
1001 unsigned int ioctl, unsigned long arg)
1002{
1003 void __user *argp = (void __user *)arg;
1004 long r;
1005
1006 switch (ioctl) {
1007 case KVM_GET_MSR_INDEX_LIST: {
1008 struct kvm_msr_list __user *user_msr_list = argp;
1009 struct kvm_msr_list msr_list;
1010 unsigned n;
1011
1012 r = -EFAULT;
1013 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1014 goto out;
1015 n = msr_list.nmsrs;
1016 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1017 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1018 goto out;
1019 r = -E2BIG;
1020 if (n < num_msrs_to_save)
1021 goto out;
1022 r = -EFAULT;
1023 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1024 num_msrs_to_save * sizeof(u32)))
1025 goto out;
1026 if (copy_to_user(user_msr_list->indices
1027 + num_msrs_to_save * sizeof(u32),
1028 &emulated_msrs,
1029 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1030 goto out;
1031 r = 0;
1032 break;
1033 }
674eea0f
AK		 1034 case KVM_GET_SUPPORTED_CPUID: {
1035 struct kvm_cpuid2 __user *cpuid_arg = argp;
1036 struct kvm_cpuid2 cpuid;
1037
1038 r = -EFAULT;
1039 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1040 goto out;
1041 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
1042 cpuid_arg->entries);
1043 if (r)
1044 goto out;
1045
1046 r = -EFAULT;
1047 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1048 goto out;
1049 r = 0;
1050 break;
1051 }
043405e1
CO		 1052 default:
1053 r = -EINVAL;
1054 }
1055out:
1056 return r;
1057}
1058
313a3dc7
CO		 1059void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1060{
1061 kvm_x86_ops->vcpu_load(vcpu, cpu);
18068523 1062 kvm_write_guest_time(vcpu);
313a3dc7
CO		 1063}
1064
1065void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1066{
1067 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 1068 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1069}
1070
07716717 1071static int is_efer_nx(void)
313a3dc7
CO		 1072{
1073 u64 efer;
313a3dc7
CO		 1074
1075 rdmsrl(MSR_EFER, efer);
07716717
DK		 1076 return efer & EFER_NX;
1077}
1078
1079static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1080{
1081 int i;
1082 struct kvm_cpuid_entry2 *e, *entry;
1083
313a3dc7 1084 entry = NULL;
ad312c7c
ZX		 1085 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1086 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1087 if (e->function == 0x80000001) {
1088 entry = e;
1089 break;
1090 }
1091 }
07716717 1092 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1093 entry->edx &= ~(1 << 20);
1094 printk(KERN_INFO "kvm: guest NX capability removed\n");
1095 }
1096}
1097
07716717 1098/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1099static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1100 struct kvm_cpuid *cpuid,
1101 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1102{
1103 int r, i;
1104 struct kvm_cpuid_entry *cpuid_entries;
1105
1106 r = -E2BIG;
1107 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1108 goto out;
1109 r = -ENOMEM;
1110 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1111 if (!cpuid_entries)
1112 goto out;
1113 r = -EFAULT;
1114 if (copy_from_user(cpuid_entries, entries,
1115 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1116 goto out_free;
1117 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1118 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1119 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1120 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1121 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1122 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1123 vcpu->arch.cpuid_entries[i].index = 0;
1124 vcpu->arch.cpuid_entries[i].flags = 0;
1125 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1126 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1127 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1128 }
1129 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1130 cpuid_fix_nx_cap(vcpu);
1131 r = 0;
1132
1133out_free:
1134 vfree(cpuid_entries);
1135out:
1136 return r;
1137}
1138
1139static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
1140 struct kvm_cpuid2 *cpuid,
1141 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1142{
1143 int r;
1144
1145 r = -E2BIG;
1146 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1147 goto out;
1148 r = -EFAULT;
ad312c7c 1149 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1150 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1151 goto out;
ad312c7c 1152 vcpu->arch.cpuid_nent = cpuid->nent;
313a3dc7
CO		 1153 return 0;
1154
1155out:
1156 return r;
1157}
1158
07716717
DK		 1159static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
1160 struct kvm_cpuid2 *cpuid,
1161 struct kvm_cpuid_entry2 __user *entries)
1162{
1163 int r;
1164
1165 r = -E2BIG;
ad312c7c 1166 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1167 goto out;
1168 r = -EFAULT;
ad312c7c
ZX		 1169 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
1170 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1171 goto out;
1172 return 0;
1173
1174out:
ad312c7c 1175 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1176 return r;
1177}
1178
1179static inline u32 bit(int bitno)
1180{
1181 return 1 << (bitno & 31);
1182}
1183
1184static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1185 u32 index)
1186{
1187 entry->function = function;
1188 entry->index = index;
1189 cpuid_count(entry->function, entry->index,
1190 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
1191 entry->flags = 0;
1192}
1193
1194static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1195 u32 index, int *nent, int maxnent)
1196{
1197 const u32 kvm_supported_word0_x86_features = bit(X86_FEATURE_FPU) |
1198 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1199 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1200 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1201 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1202 bit(X86_FEATURE_SEP) | bit(X86_FEATURE_PGE) |
1203 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1204 bit(X86_FEATURE_CLFLSH) | bit(X86_FEATURE_MMX) |
1205 bit(X86_FEATURE_FXSR) | bit(X86_FEATURE_XMM) |
1206 bit(X86_FEATURE_XMM2) | bit(X86_FEATURE_SELFSNOOP);
1207 const u32 kvm_supported_word1_x86_features = bit(X86_FEATURE_FPU) |
1208 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1209 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1210 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1211 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1212 bit(X86_FEATURE_PGE) |
1213 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1214 bit(X86_FEATURE_MMX) | bit(X86_FEATURE_FXSR) |
1215 bit(X86_FEATURE_SYSCALL) |
1216 (bit(X86_FEATURE_NX) && is_efer_nx()) |
1217#ifdef CONFIG_X86_64
1218 bit(X86_FEATURE_LM) |
1219#endif
1220 bit(X86_FEATURE_MMXEXT) |
1221 bit(X86_FEATURE_3DNOWEXT) |
1222 bit(X86_FEATURE_3DNOW);
1223 const u32 kvm_supported_word3_x86_features =
1224 bit(X86_FEATURE_XMM3) | bit(X86_FEATURE_CX16);
1225 const u32 kvm_supported_word6_x86_features =
1226 bit(X86_FEATURE_LAHF_LM) | bit(X86_FEATURE_CMP_LEGACY);
1227
1228 /* all func 2 cpuid_count() should be called on the same cpu */
1229 get_cpu();
1230 do_cpuid_1_ent(entry, function, index);
1231 ++*nent;
1232
1233 switch (function) {
1234 case 0:
1235 entry->eax = min(entry->eax, (u32)0xb);
1236 break;
1237 case 1:
1238 entry->edx &= kvm_supported_word0_x86_features;
1239 entry->ecx &= kvm_supported_word3_x86_features;
1240 break;
1241 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1242 * may return different values. This forces us to get_cpu() before
1243 * issuing the first command, and also to emulate this annoying behavior
1244 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1245 case 2: {
1246 int t, times = entry->eax & 0xff;
1247
1248 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1249 for (t = 1; t < times && *nent < maxnent; ++t) {
1250 do_cpuid_1_ent(&entry[t], function, 0);
1251 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1252 ++*nent;
1253 }
1254 break;
1255 }
1256 /* function 4 and 0xb have additional index. */
1257 case 4: {
14af3f3c 1258 int i, cache_type;
07716717
DK		 1259
1260 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1261 /* read more entries until cache_type is zero */
14af3f3c
HH		 1262 for (i = 1; *nent < maxnent; ++i) {
1263 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1264 if (!cache_type)
1265 break;
14af3f3c
HH		 1266 do_cpuid_1_ent(&entry[i], function, i);
1267 entry[i].flags |=
07716717
DK		 1268 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1269 ++*nent;
1270 }
1271 break;
1272 }
1273 case 0xb: {
14af3f3c 1274 int i, level_type;
07716717
DK		 1275
1276 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1277 /* read more entries until level_type is zero */
14af3f3c
HH		 1278 for (i = 1; *nent < maxnent; ++i) {
1279 level_type = entry[i - 1].ecx & 0xff;
07716717
DK		 1280 if (!level_type)
1281 break;
14af3f3c
HH		 1282 do_cpuid_1_ent(&entry[i], function, i);
1283 entry[i].flags |=
07716717
DK		 1284 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1285 ++*nent;
1286 }
1287 break;
1288 }
1289 case 0x80000000:
1290 entry->eax = min(entry->eax, 0x8000001a);
1291 break;
1292 case 0x80000001:
1293 entry->edx &= kvm_supported_word1_x86_features;
1294 entry->ecx &= kvm_supported_word6_x86_features;
1295 break;
1296 }
1297 put_cpu();
1298}
1299
674eea0f 1300static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
07716717
DK		 1301 struct kvm_cpuid_entry2 __user *entries)
1302{
1303 struct kvm_cpuid_entry2 *cpuid_entries;
1304 int limit, nent = 0, r = -E2BIG;
1305 u32 func;
1306
1307 if (cpuid->nent < 1)
1308 goto out;
1309 r = -ENOMEM;
1310 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1311 if (!cpuid_entries)
1312 goto out;
1313
1314 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1315 limit = cpuid_entries[0].eax;
1316 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1317 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1318 &nent, cpuid->nent);
1319 r = -E2BIG;
1320 if (nent >= cpuid->nent)
1321 goto out_free;
1322
1323 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1324 limit = cpuid_entries[nent - 1].eax;
1325 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1326 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1327 &nent, cpuid->nent);
1328 r = -EFAULT;
1329 if (copy_to_user(entries, cpuid_entries,
1330 nent * sizeof(struct kvm_cpuid_entry2)))
1331 goto out_free;
1332 cpuid->nent = nent;
1333 r = 0;
1334
1335out_free:
1336 vfree(cpuid_entries);
1337out:
1338 return r;
1339}
1340
313a3dc7
CO		 1341static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1342 struct kvm_lapic_state *s)
1343{
1344 vcpu_load(vcpu);
ad312c7c 1345 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1346 vcpu_put(vcpu);
1347
1348 return 0;
1349}
1350
1351static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1352 struct kvm_lapic_state *s)
1353{
1354 vcpu_load(vcpu);
ad312c7c 1355 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7
CO		 1356 kvm_apic_post_state_restore(vcpu);
1357 vcpu_put(vcpu);
1358
1359 return 0;
1360}
1361
f77bc6a4
ZX		 1362static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1363 struct kvm_interrupt *irq)
1364{
1365 if (irq->irq < 0 || irq->irq >= 256)
1366 return -EINVAL;
1367 if (irqchip_in_kernel(vcpu->kvm))
1368 return -ENXIO;
1369 vcpu_load(vcpu);
1370
ad312c7c
ZX		 1371 set_bit(irq->irq, vcpu->arch.irq_pending);
1372 set_bit(irq->irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
f77bc6a4
ZX		 1373
1374 vcpu_put(vcpu);
1375
1376 return 0;
1377}
1378
c4abb7c9
JK		 1379static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1380{
1381 vcpu_load(vcpu);
1382 kvm_inject_nmi(vcpu);
1383 vcpu_put(vcpu);
1384
1385 return 0;
1386}
1387
b209749f
AK		 1388static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1389 struct kvm_tpr_access_ctl *tac)
1390{
1391 if (tac->flags)
1392 return -EINVAL;
1393 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1394 return 0;
1395}
1396
313a3dc7
CO		 1397long kvm_arch_vcpu_ioctl(struct file *filp,
1398 unsigned int ioctl, unsigned long arg)
1399{
1400 struct kvm_vcpu *vcpu = filp->private_data;
1401 void __user *argp = (void __user *)arg;
1402 int r;
b772ff36 1403 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 1404
1405 switch (ioctl) {
1406 case KVM_GET_LAPIC: {
b772ff36 1407 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 1408
b772ff36
DH		 1409 r = -ENOMEM;
1410 if (!lapic)
1411 goto out;
1412 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 1413 if (r)
1414 goto out;
1415 r = -EFAULT;
b772ff36 1416 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 1417 goto out;
1418 r = 0;
1419 break;
1420 }
1421 case KVM_SET_LAPIC: {
b772ff36
DH		 1422 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1423 r = -ENOMEM;
1424 if (!lapic)
1425 goto out;
313a3dc7 1426 r = -EFAULT;
b772ff36 1427 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 1428 goto out;
b772ff36 1429 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 1430 if (r)
1431 goto out;
1432 r = 0;
1433 break;
1434 }
f77bc6a4
ZX		 1435 case KVM_INTERRUPT: {
1436 struct kvm_interrupt irq;
1437
1438 r = -EFAULT;
1439 if (copy_from_user(&irq, argp, sizeof irq))
1440 goto out;
1441 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1442 if (r)
1443 goto out;
1444 r = 0;
1445 break;
1446 }
c4abb7c9
JK		 1447 case KVM_NMI: {
1448 r = kvm_vcpu_ioctl_nmi(vcpu);
1449 if (r)
1450 goto out;
1451 r = 0;
1452 break;
1453 }
313a3dc7
CO		 1454 case KVM_SET_CPUID: {
1455 struct kvm_cpuid __user *cpuid_arg = argp;
1456 struct kvm_cpuid cpuid;
1457
1458 r = -EFAULT;
1459 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1460 goto out;
1461 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1462 if (r)
1463 goto out;
1464 break;
1465 }
07716717
DK		 1466 case KVM_SET_CPUID2: {
1467 struct kvm_cpuid2 __user *cpuid_arg = argp;
1468 struct kvm_cpuid2 cpuid;
1469
1470 r = -EFAULT;
1471 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1472 goto out;
1473 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
1474 cpuid_arg->entries);
1475 if (r)
1476 goto out;
1477 break;
1478 }
1479 case KVM_GET_CPUID2: {
1480 struct kvm_cpuid2 __user *cpuid_arg = argp;
1481 struct kvm_cpuid2 cpuid;
1482
1483 r = -EFAULT;
1484 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1485 goto out;
1486 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
1487 cpuid_arg->entries);
1488 if (r)
1489 goto out;
1490 r = -EFAULT;
1491 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1492 goto out;
1493 r = 0;
1494 break;
1495 }
313a3dc7
CO		 1496 case KVM_GET_MSRS:
1497 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1498 break;
1499 case KVM_SET_MSRS:
1500 r = msr_io(vcpu, argp, do_set_msr, 0);
1501 break;
b209749f
AK		 1502 case KVM_TPR_ACCESS_REPORTING: {
1503 struct kvm_tpr_access_ctl tac;
1504
1505 r = -EFAULT;
1506 if (copy_from_user(&tac, argp, sizeof tac))
1507 goto out;
1508 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1509 if (r)
1510 goto out;
1511 r = -EFAULT;
1512 if (copy_to_user(argp, &tac, sizeof tac))
1513 goto out;
1514 r = 0;
1515 break;
1516 };
b93463aa
AK		 1517 case KVM_SET_VAPIC_ADDR: {
1518 struct kvm_vapic_addr va;
1519
1520 r = -EINVAL;
1521 if (!irqchip_in_kernel(vcpu->kvm))
1522 goto out;
1523 r = -EFAULT;
1524 if (copy_from_user(&va, argp, sizeof va))
1525 goto out;
1526 r = 0;
1527 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1528 break;
1529 }
313a3dc7
CO		 1530 default:
1531 r = -EINVAL;
1532 }
1533out:
b772ff36
DH		 1534 if (lapic)
1535 kfree(lapic);
313a3dc7
CO		 1536 return r;
1537}
1538
1fe779f8
CO		 1539static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1540{
1541 int ret;
1542
1543 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1544 return -1;
1545 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1546 return ret;
1547}
1548
1549static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1550 u32 kvm_nr_mmu_pages)
1551{
1552 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1553 return -EINVAL;
1554
72dc67a6 1555 down_write(&kvm->slots_lock);
1fe779f8
CO		 1556
1557 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1558 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1559
72dc67a6 1560 up_write(&kvm->slots_lock);
1fe779f8
CO		 1561 return 0;
1562}
1563
1564static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1565{
f05e70ac 1566 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1567}
1568
e9f85cde
ZX		 1569gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1570{
1571 int i;
1572 struct kvm_mem_alias *alias;
1573
d69fb81f
ZX		 1574 for (i = 0; i < kvm->arch.naliases; ++i) {
1575 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1576 if (gfn >= alias->base_gfn
1577 && gfn < alias->base_gfn + alias->npages)
1578 return alias->target_gfn + gfn - alias->base_gfn;
1579 }
1580 return gfn;
1581}
1582
1fe779f8
CO		 1583/*
1584 * Set a new alias region. Aliases map a portion of physical memory into
1585 * another portion. This is useful for memory windows, for example the PC
1586 * VGA region.
1587 */
1588static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1589 struct kvm_memory_alias *alias)
1590{
1591 int r, n;
1592 struct kvm_mem_alias *p;
1593
1594 r = -EINVAL;
1595 /* General sanity checks */
1596 if (alias->memory_size & (PAGE_SIZE - 1))
1597 goto out;
1598 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1599 goto out;
1600 if (alias->slot >= KVM_ALIAS_SLOTS)
1601 goto out;
1602 if (alias->guest_phys_addr + alias->memory_size
1603 < alias->guest_phys_addr)
1604 goto out;
1605 if (alias->target_phys_addr + alias->memory_size
1606 < alias->target_phys_addr)
1607 goto out;
1608
72dc67a6 1609 down_write(&kvm->slots_lock);
a1708ce8 1610 spin_lock(&kvm->mmu_lock);
1fe779f8 1611
d69fb81f 1612 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 1613 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1614 p->npages = alias->memory_size >> PAGE_SHIFT;
1615 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1616
1617 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 1618 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 1619 break;
d69fb81f 1620 kvm->arch.naliases = n;
1fe779f8 1621
a1708ce8 1622 spin_unlock(&kvm->mmu_lock);
1fe779f8
CO		 1623 kvm_mmu_zap_all(kvm);
1624
72dc67a6 1625 up_write(&kvm->slots_lock);
1fe779f8
CO		 1626
1627 return 0;
1628
1629out:
1630 return r;
1631}
1632
1633static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1634{
1635 int r;
1636
1637 r = 0;
1638 switch (chip->chip_id) {
1639 case KVM_IRQCHIP_PIC_MASTER:
1640 memcpy(&chip->chip.pic,
1641 &pic_irqchip(kvm)->pics[0],
1642 sizeof(struct kvm_pic_state));
1643 break;
1644 case KVM_IRQCHIP_PIC_SLAVE:
1645 memcpy(&chip->chip.pic,
1646 &pic_irqchip(kvm)->pics[1],
1647 sizeof(struct kvm_pic_state));
1648 break;
1649 case KVM_IRQCHIP_IOAPIC:
1650 memcpy(&chip->chip.ioapic,
1651 ioapic_irqchip(kvm),
1652 sizeof(struct kvm_ioapic_state));
1653 break;
1654 default:
1655 r = -EINVAL;
1656 break;
1657 }
1658 return r;
1659}
1660
1661static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1662{
1663 int r;
1664
1665 r = 0;
1666 switch (chip->chip_id) {
1667 case KVM_IRQCHIP_PIC_MASTER:
1668 memcpy(&pic_irqchip(kvm)->pics[0],
1669 &chip->chip.pic,
1670 sizeof(struct kvm_pic_state));
1671 break;
1672 case KVM_IRQCHIP_PIC_SLAVE:
1673 memcpy(&pic_irqchip(kvm)->pics[1],
1674 &chip->chip.pic,
1675 sizeof(struct kvm_pic_state));
1676 break;
1677 case KVM_IRQCHIP_IOAPIC:
1678 memcpy(ioapic_irqchip(kvm),
1679 &chip->chip.ioapic,
1680 sizeof(struct kvm_ioapic_state));
1681 break;
1682 default:
1683 r = -EINVAL;
1684 break;
1685 }
1686 kvm_pic_update_irq(pic_irqchip(kvm));
1687 return r;
1688}
1689
e0f63cb9
SY		 1690static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1691{
1692 int r = 0;
1693
1694 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
1695 return r;
1696}
1697
1698static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1699{
1700 int r = 0;
1701
1702 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
1703 kvm_pit_load_count(kvm, 0, ps->channels[0].count);
1704 return r;
1705}
1706
5bb064dc
ZX		 1707/*
1708 * Get (and clear) the dirty memory log for a memory slot.
1709 */
1710int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
1711 struct kvm_dirty_log *log)
1712{
1713 int r;
1714 int n;
1715 struct kvm_memory_slot *memslot;
1716 int is_dirty = 0;
1717
72dc67a6 1718 down_write(&kvm->slots_lock);
5bb064dc
ZX		 1719
1720 r = kvm_get_dirty_log(kvm, log, &is_dirty);
1721 if (r)
1722 goto out;
1723
1724 /* If nothing is dirty, don't bother messing with page tables. */
1725 if (is_dirty) {
1726 kvm_mmu_slot_remove_write_access(kvm, log->slot);
1727 kvm_flush_remote_tlbs(kvm);
1728 memslot = &kvm->memslots[log->slot];
1729 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
1730 memset(memslot->dirty_bitmap, 0, n);
1731 }
1732 r = 0;
1733out:
72dc67a6 1734 up_write(&kvm->slots_lock);
5bb064dc
ZX		 1735 return r;
1736}
1737
1fe779f8
CO		 1738long kvm_arch_vm_ioctl(struct file *filp,
1739 unsigned int ioctl, unsigned long arg)
1740{
1741 struct kvm *kvm = filp->private_data;
1742 void __user *argp = (void __user *)arg;
1743 int r = -EINVAL;
f0d66275
DH		 1744 /*
1745 * This union makes it completely explicit to gcc-3.x
1746 * that these two variables' stack usage should be
1747 * combined, not added together.
1748 */
1749 union {
1750 struct kvm_pit_state ps;
1751 struct kvm_memory_alias alias;
1752 } u;
1fe779f8
CO		 1753
1754 switch (ioctl) {
1755 case KVM_SET_TSS_ADDR:
1756 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1757 if (r < 0)
1758 goto out;
1759 break;
1760 case KVM_SET_MEMORY_REGION: {
1761 struct kvm_memory_region kvm_mem;
1762 struct kvm_userspace_memory_region kvm_userspace_mem;
1763
1764 r = -EFAULT;
1765 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
1766 goto out;
1767 kvm_userspace_mem.slot = kvm_mem.slot;
1768 kvm_userspace_mem.flags = kvm_mem.flags;
1769 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
1770 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
1771 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
1772 if (r)
1773 goto out;
1774 break;
1775 }
1776 case KVM_SET_NR_MMU_PAGES:
1777 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1778 if (r)
1779 goto out;
1780 break;
1781 case KVM_GET_NR_MMU_PAGES:
1782 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
1783 break;
f0d66275 1784 case KVM_SET_MEMORY_ALIAS:
1fe779f8 1785 r = -EFAULT;
f0d66275 1786 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 1787 goto out;
f0d66275 1788 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 1789 if (r)
1790 goto out;
1791 break;
1fe779f8
CO		 1792 case KVM_CREATE_IRQCHIP:
1793 r = -ENOMEM;
d7deeeb0
ZX		 1794 kvm->arch.vpic = kvm_create_pic(kvm);
1795 if (kvm->arch.vpic) {
1fe779f8
CO		 1796 r = kvm_ioapic_init(kvm);
1797 if (r) {
d7deeeb0
ZX		 1798 kfree(kvm->arch.vpic);
1799 kvm->arch.vpic = NULL;
1fe779f8
CO		 1800 goto out;
1801 }
1802 } else
1803 goto out;
1804 break;
7837699f
SY		 1805 case KVM_CREATE_PIT:
1806 r = -ENOMEM;
1807 kvm->arch.vpit = kvm_create_pit(kvm);
1808 if (kvm->arch.vpit)
1809 r = 0;
1810 break;
1fe779f8
CO		 1811 case KVM_IRQ_LINE: {
1812 struct kvm_irq_level irq_event;
1813
1814 r = -EFAULT;
1815 if (copy_from_user(&irq_event, argp, sizeof irq_event))
1816 goto out;
1817 if (irqchip_in_kernel(kvm)) {
1818 mutex_lock(&kvm->lock);
5550af4d
SY		 1819 kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
1820 irq_event.irq, irq_event.level);
1fe779f8
CO		 1821 mutex_unlock(&kvm->lock);
1822 r = 0;
1823 }
1824 break;
1825 }
1826 case KVM_GET_IRQCHIP: {
1827 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 1828 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 1829
f0d66275
DH		 1830 r = -ENOMEM;
1831 if (!chip)
1fe779f8 1832 goto out;
f0d66275
DH		 1833 r = -EFAULT;
1834 if (copy_from_user(chip, argp, sizeof *chip))
1835 goto get_irqchip_out;
1fe779f8
CO		 1836 r = -ENXIO;
1837 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 1838 goto get_irqchip_out;
1839 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 1840 if (r)
f0d66275 1841 goto get_irqchip_out;
1fe779f8 1842 r = -EFAULT;
f0d66275
DH		 1843 if (copy_to_user(argp, chip, sizeof *chip))
1844 goto get_irqchip_out;
1fe779f8 1845 r = 0;
f0d66275
DH		 1846 get_irqchip_out:
1847 kfree(chip);
1848 if (r)
1849 goto out;
1fe779f8
CO		 1850 break;
1851 }
1852 case KVM_SET_IRQCHIP: {
1853 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 1854 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 1855
f0d66275
DH		 1856 r = -ENOMEM;
1857 if (!chip)
1fe779f8 1858 goto out;
f0d66275
DH		 1859 r = -EFAULT;
1860 if (copy_from_user(chip, argp, sizeof *chip))
1861 goto set_irqchip_out;
1fe779f8
CO		 1862 r = -ENXIO;
1863 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 1864 goto set_irqchip_out;
1865 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 1866 if (r)
f0d66275 1867 goto set_irqchip_out;
1fe779f8 1868 r = 0;
f0d66275
DH		 1869 set_irqchip_out:
1870 kfree(chip);
1871 if (r)
1872 goto out;
1fe779f8
CO		 1873 break;
1874 }
e0f63cb9 1875 case KVM_GET_PIT: {
e0f63cb9 1876 r = -EFAULT;
f0d66275 1877 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 1878 goto out;
1879 r = -ENXIO;
1880 if (!kvm->arch.vpit)
1881 goto out;
f0d66275 1882 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 1883 if (r)
1884 goto out;
1885 r = -EFAULT;
f0d66275 1886 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 1887 goto out;
1888 r = 0;
1889 break;
1890 }
1891 case KVM_SET_PIT: {
e0f63cb9 1892 r = -EFAULT;
f0d66275 1893 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 1894 goto out;
1895 r = -ENXIO;
1896 if (!kvm->arch.vpit)
1897 goto out;
f0d66275 1898 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 1899 if (r)
1900 goto out;
1901 r = 0;
1902 break;
1903 }
1fe779f8
CO		 1904 default:
1905 ;
1906 }
1907out:
1908 return r;
1909}
1910
a16b043c 1911static void kvm_init_msr_list(void)
043405e1
CO		 1912{
1913 u32 dummy[2];
1914 unsigned i, j;
1915
1916 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
1917 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
1918 continue;
1919 if (j < i)
1920 msrs_to_save[j] = msrs_to_save[i];
1921 j++;
1922 }
1923 num_msrs_to_save = j;
1924}
1925
bbd9b64e
CO		 1926/*
1927 * Only apic need an MMIO device hook, so shortcut now..
1928 */
1929static struct kvm_io_device *vcpu_find_pervcpu_dev(struct kvm_vcpu *vcpu,
92760499
LV		 1930 gpa_t addr, int len,
1931 int is_write)
bbd9b64e
CO		 1932{
1933 struct kvm_io_device *dev;
1934
ad312c7c
ZX		 1935 if (vcpu->arch.apic) {
1936 dev = &vcpu->arch.apic->dev;
92760499 1937 if (dev->in_range(dev, addr, len, is_write))
bbd9b64e
CO		 1938 return dev;
1939 }
1940 return NULL;
1941}
1942
1943
1944static struct kvm_io_device *vcpu_find_mmio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 1945 gpa_t addr, int len,
1946 int is_write)
bbd9b64e
CO		 1947{
1948 struct kvm_io_device *dev;
1949
92760499 1950 dev = vcpu_find_pervcpu_dev(vcpu, addr, len, is_write);
bbd9b64e 1951 if (dev == NULL)
92760499
LV		 1952 dev = kvm_io_bus_find_dev(&vcpu->kvm->mmio_bus, addr, len,
1953 is_write);
bbd9b64e
CO		 1954 return dev;
1955}
1956
1957int emulator_read_std(unsigned long addr,
1958 void *val,
1959 unsigned int bytes,
1960 struct kvm_vcpu *vcpu)
1961{
1962 void *data = val;
10589a46 1963 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 1964
1965 while (bytes) {
ad312c7c 1966 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 1967 unsigned offset = addr & (PAGE_SIZE-1);
1968 unsigned tocopy = min(bytes, (unsigned)PAGE_SIZE - offset);
1969 int ret;
1970
10589a46
MT		 1971 if (gpa == UNMAPPED_GVA) {
1972 r = X86EMUL_PROPAGATE_FAULT;
1973 goto out;
1974 }
bbd9b64e 1975 ret = kvm_read_guest(vcpu->kvm, gpa, data, tocopy);
10589a46
MT		 1976 if (ret < 0) {
1977 r = X86EMUL_UNHANDLEABLE;
1978 goto out;
1979 }
bbd9b64e
CO		 1980
1981 bytes -= tocopy;
1982 data += tocopy;
1983 addr += tocopy;
1984 }
10589a46 1985out:
10589a46 1986 return r;
bbd9b64e
CO		 1987}
1988EXPORT_SYMBOL_GPL(emulator_read_std);
1989
bbd9b64e
CO		 1990static int emulator_read_emulated(unsigned long addr,
1991 void *val,
1992 unsigned int bytes,
1993 struct kvm_vcpu *vcpu)
1994{
1995 struct kvm_io_device *mmio_dev;
1996 gpa_t gpa;
1997
1998 if (vcpu->mmio_read_completed) {
1999 memcpy(val, vcpu->mmio_data, bytes);
2000 vcpu->mmio_read_completed = 0;
2001 return X86EMUL_CONTINUE;
2002 }
2003
ad312c7c 2004 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2005
2006 /* For APIC access vmexit */
2007 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2008 goto mmio;
2009
2010 if (emulator_read_std(addr, val, bytes, vcpu)
2011 == X86EMUL_CONTINUE)
2012 return X86EMUL_CONTINUE;
2013 if (gpa == UNMAPPED_GVA)
2014 return X86EMUL_PROPAGATE_FAULT;
2015
2016mmio:
2017 /*
2018 * Is this MMIO handled locally?
2019 */
10589a46 2020 mutex_lock(&vcpu->kvm->lock);
92760499 2021 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 0);
bbd9b64e
CO		 2022 if (mmio_dev) {
2023 kvm_iodevice_read(mmio_dev, gpa, bytes, val);
10589a46 2024 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2025 return X86EMUL_CONTINUE;
2026 }
10589a46 2027 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2028
2029 vcpu->mmio_needed = 1;
2030 vcpu->mmio_phys_addr = gpa;
2031 vcpu->mmio_size = bytes;
2032 vcpu->mmio_is_write = 0;
2033
2034 return X86EMUL_UNHANDLEABLE;
2035}
2036
3200f405 2037int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 2038 const void *val, int bytes)
bbd9b64e
CO		 2039{
2040 int ret;
2041
2042 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 2043 if (ret < 0)
bbd9b64e
CO		 2044 return 0;
2045 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
2046 return 1;
2047}
2048
2049static int emulator_write_emulated_onepage(unsigned long addr,
2050 const void *val,
2051 unsigned int bytes,
2052 struct kvm_vcpu *vcpu)
2053{
2054 struct kvm_io_device *mmio_dev;
10589a46
MT		 2055 gpa_t gpa;
2056
10589a46 2057 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2058
2059 if (gpa == UNMAPPED_GVA) {
c3c91fee 2060 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 2061 return X86EMUL_PROPAGATE_FAULT;
2062 }
2063
2064 /* For APIC access vmexit */
2065 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2066 goto mmio;
2067
2068 if (emulator_write_phys(vcpu, gpa, val, bytes))
2069 return X86EMUL_CONTINUE;
2070
2071mmio:
2072 /*
2073 * Is this MMIO handled locally?
2074 */
10589a46 2075 mutex_lock(&vcpu->kvm->lock);
92760499 2076 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 1);
bbd9b64e
CO		 2077 if (mmio_dev) {
2078 kvm_iodevice_write(mmio_dev, gpa, bytes, val);
10589a46 2079 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2080 return X86EMUL_CONTINUE;
2081 }
10589a46 2082 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2083
2084 vcpu->mmio_needed = 1;
2085 vcpu->mmio_phys_addr = gpa;
2086 vcpu->mmio_size = bytes;
2087 vcpu->mmio_is_write = 1;
2088 memcpy(vcpu->mmio_data, val, bytes);
2089
2090 return X86EMUL_CONTINUE;
2091}
2092
2093int emulator_write_emulated(unsigned long addr,
2094 const void *val,
2095 unsigned int bytes,
2096 struct kvm_vcpu *vcpu)
2097{
2098 /* Crossing a page boundary? */
2099 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2100 int rc, now;
2101
2102 now = -addr & ~PAGE_MASK;
2103 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2104 if (rc != X86EMUL_CONTINUE)
2105 return rc;
2106 addr += now;
2107 val += now;
2108 bytes -= now;
2109 }
2110 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2111}
2112EXPORT_SYMBOL_GPL(emulator_write_emulated);
2113
2114static int emulator_cmpxchg_emulated(unsigned long addr,
2115 const void *old,
2116 const void *new,
2117 unsigned int bytes,
2118 struct kvm_vcpu *vcpu)
2119{
2120 static int reported;
2121
2122 if (!reported) {
2123 reported = 1;
2124 printk(KERN_WARNING "kvm: emulating exchange as write\n");
2125 }
2bacc55c
MT		 2126#ifndef CONFIG_X86_64
2127 /* guests cmpxchg8b have to be emulated atomically */
2128 if (bytes == 8) {
10589a46 2129 gpa_t gpa;
2bacc55c 2130 struct page *page;
c0b49b0d 2131 char *kaddr;
2bacc55c
MT		 2132 u64 val;
2133
10589a46
MT		 2134 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2135
2bacc55c
MT		 2136 if (gpa == UNMAPPED_GVA ||
2137 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2138 goto emul_write;
2139
2140 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2141 goto emul_write;
2142
2143 val = *(u64 *)new;
72dc67a6 2144
2bacc55c 2145 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 2146
c0b49b0d
AM		 2147 kaddr = kmap_atomic(page, KM_USER0);
2148 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2149 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 2150 kvm_release_page_dirty(page);
2151 }
3200f405 2152emul_write:
2bacc55c
MT		 2153#endif
2154
bbd9b64e
CO		 2155 return emulator_write_emulated(addr, new, bytes, vcpu);
2156}
2157
2158static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2159{
2160 return kvm_x86_ops->get_segment_base(vcpu, seg);
2161}
2162
2163int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2164{
a7052897 2165 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 2166 return X86EMUL_CONTINUE;
2167}
2168
2169int emulate_clts(struct kvm_vcpu *vcpu)
2170{
54e445ca 2171 KVMTRACE_0D(CLTS, vcpu, handler);
ad312c7c 2172 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 2173 return X86EMUL_CONTINUE;
2174}
2175
2176int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2177{
2178 struct kvm_vcpu *vcpu = ctxt->vcpu;
2179
2180 switch (dr) {
2181 case 0 ... 3:
2182 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2183 return X86EMUL_CONTINUE;
2184 default:
b8688d51 2185 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2186 return X86EMUL_UNHANDLEABLE;
2187 }
2188}
2189
2190int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2191{
2192 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2193 int exception;
2194
2195 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2196 if (exception) {
2197 /* FIXME: better handling */
2198 return X86EMUL_UNHANDLEABLE;
2199 }
2200 return X86EMUL_CONTINUE;
2201}
2202
2203void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2204{
bbd9b64e 2205 u8 opcodes[4];
5fdbf976 2206 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 2207 unsigned long rip_linear;
2208
f76c710d 2209 if (!printk_ratelimit())
bbd9b64e
CO		 2210 return;
2211
25be4608
GC		 2212 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2213
bbd9b64e
CO		 2214 emulator_read_std(rip_linear, (void *)opcodes, 4, vcpu);
2215
2216 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2217 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 2218}
2219EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2220
14af3f3c 2221static struct x86_emulate_ops emulate_ops = {
bbd9b64e 2222 .read_std = emulator_read_std,
bbd9b64e
CO		 2223 .read_emulated = emulator_read_emulated,
2224 .write_emulated = emulator_write_emulated,
2225 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2226};
2227
5fdbf976
MT		 2228static void cache_all_regs(struct kvm_vcpu *vcpu)
2229{
2230 kvm_register_read(vcpu, VCPU_REGS_RAX);
2231 kvm_register_read(vcpu, VCPU_REGS_RSP);
2232 kvm_register_read(vcpu, VCPU_REGS_RIP);
2233 vcpu->arch.regs_dirty = ~0;
2234}
2235
bbd9b64e
CO		 2236int emulate_instruction(struct kvm_vcpu *vcpu,
2237 struct kvm_run *run,
2238 unsigned long cr2,
2239 u16 error_code,
571008da 2240 int emulation_type)
bbd9b64e
CO		 2241{
2242 int r;
571008da 2243 struct decode_cache *c;
bbd9b64e 2244
26eef70c 2245 kvm_clear_exception_queue(vcpu);
ad312c7c 2246 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976
MT		 2247 /*
2248 * TODO: fix x86_emulate.c to use guest_read/write_register
2249 * instead of direct ->regs accesses, can save hundred cycles
2250 * on Intel for instructions that don't read/change RSP, for
2251 * for example.
2252 */
2253 cache_all_regs(vcpu);
bbd9b64e
CO		 2254
2255 vcpu->mmio_is_write = 0;
ad312c7c 2256 vcpu->arch.pio.string = 0;
bbd9b64e 2257
571008da 2258 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2259 int cs_db, cs_l;
2260 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2261
ad312c7c
ZX		 2262 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2263 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2264 vcpu->arch.emulate_ctxt.mode =
2265 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2266 ? X86EMUL_MODE_REAL : cs_l
2267 ? X86EMUL_MODE_PROT64 : cs_db
2268 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2269
ad312c7c 2270 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da
SY		 2271
2272 /* Reject the instructions other than VMCALL/VMMCALL when
2273 * try to emulate invalid opcode */
2274 c = &vcpu->arch.emulate_ctxt.decode;
2275 if ((emulation_type & EMULTYPE_TRAP_UD) &&
2276 (!(c->twobyte && c->b == 0x01 &&
2277 (c->modrm_reg == 0 || c->modrm_reg == 3) &&
2278 c->modrm_mod == 3 && c->modrm_rm == 1)))
2279 return EMULATE_FAIL;
2280
f2b5756b 2281 ++vcpu->stat.insn_emulation;
bbd9b64e 2282 if (r) {
f2b5756b 2283 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2284 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2285 return EMULATE_DONE;
2286 return EMULATE_FAIL;
2287 }
2288 }
2289
ad312c7c 2290 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
bbd9b64e 2291
ad312c7c 2292 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2293 return EMULATE_DO_MMIO;
2294
2295 if ((r || vcpu->mmio_is_write) && run) {
2296 run->exit_reason = KVM_EXIT_MMIO;
2297 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2298 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2299 run->mmio.len = vcpu->mmio_size;
2300 run->mmio.is_write = vcpu->mmio_is_write;
2301 }
2302
2303 if (r) {
2304 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2305 return EMULATE_DONE;
2306 if (!vcpu->mmio_needed) {
2307 kvm_report_emulation_failure(vcpu, "mmio");
2308 return EMULATE_FAIL;
2309 }
2310 return EMULATE_DO_MMIO;
2311 }
2312
ad312c7c 2313 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2314
2315 if (vcpu->mmio_is_write) {
2316 vcpu->mmio_needed = 0;
2317 return EMULATE_DO_MMIO;
2318 }
2319
2320 return EMULATE_DONE;
2321}
2322EXPORT_SYMBOL_GPL(emulate_instruction);
2323
de7d789a
CO		 2324static void free_pio_guest_pages(struct kvm_vcpu *vcpu)
2325{
2326 int i;
2327
ad312c7c
ZX		 2328 for (i = 0; i < ARRAY_SIZE(vcpu->arch.pio.guest_pages); ++i)
2329 if (vcpu->arch.pio.guest_pages[i]) {
2330 kvm_release_page_dirty(vcpu->arch.pio.guest_pages[i]);
2331 vcpu->arch.pio.guest_pages[i] = NULL;
de7d789a
CO		 2332 }
2333}
2334
2335static int pio_copy_data(struct kvm_vcpu *vcpu)
2336{
ad312c7c 2337 void *p = vcpu->arch.pio_data;
de7d789a
CO		 2338 void *q;
2339 unsigned bytes;
ad312c7c 2340 int nr_pages = vcpu->arch.pio.guest_pages[1] ? 2 : 1;
de7d789a 2341
ad312c7c 2342 q = vmap(vcpu->arch.pio.guest_pages, nr_pages, VM_READ|VM_WRITE,
de7d789a
CO		 2343 PAGE_KERNEL);
2344 if (!q) {
2345 free_pio_guest_pages(vcpu);
2346 return -ENOMEM;
2347 }
ad312c7c
ZX		 2348 q += vcpu->arch.pio.guest_page_offset;
2349 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2350 if (vcpu->arch.pio.in)
de7d789a
CO		 2351 memcpy(q, p, bytes);
2352 else
2353 memcpy(p, q, bytes);
ad312c7c 2354 q -= vcpu->arch.pio.guest_page_offset;
de7d789a
CO		 2355 vunmap(q);
2356 free_pio_guest_pages(vcpu);
2357 return 0;
2358}
2359
2360int complete_pio(struct kvm_vcpu *vcpu)
2361{
ad312c7c 2362 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2363 long delta;
2364 int r;
5fdbf976 2365 unsigned long val;
de7d789a
CO		 2366
2367 if (!io->string) {
5fdbf976
MT		 2368 if (io->in) {
2369 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2370 memcpy(&val, vcpu->arch.pio_data, io->size);
2371 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2372 }
de7d789a
CO		 2373 } else {
2374 if (io->in) {
2375 r = pio_copy_data(vcpu);
5fdbf976 2376 if (r)
de7d789a 2377 return r;
de7d789a
CO		 2378 }
2379
2380 delta = 1;
2381 if (io->rep) {
2382 delta *= io->cur_count;
2383 /*
2384 * The size of the register should really depend on
2385 * current address size.
2386 */
5fdbf976
MT		 2387 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2388 val -= delta;
2389 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 2390 }
2391 if (io->down)
2392 delta = -delta;
2393 delta *= io->size;
5fdbf976
MT		 2394 if (io->in) {
2395 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2396 val += delta;
2397 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2398 } else {
2399 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2400 val += delta;
2401 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2402 }
de7d789a
CO		 2403 }
2404
de7d789a
CO		 2405 io->count -= io->cur_count;
2406 io->cur_count = 0;
2407
2408 return 0;
2409}
2410
2411static void kernel_pio(struct kvm_io_device *pio_dev,
2412 struct kvm_vcpu *vcpu,
2413 void *pd)
2414{
2415 /* TODO: String I/O for in kernel device */
2416
2417 mutex_lock(&vcpu->kvm->lock);
ad312c7c
ZX		 2418 if (vcpu->arch.pio.in)
2419 kvm_iodevice_read(pio_dev, vcpu->arch.pio.port,
2420 vcpu->arch.pio.size,
de7d789a
CO		 2421 pd);
2422 else
ad312c7c
ZX		 2423 kvm_iodevice_write(pio_dev, vcpu->arch.pio.port,
2424 vcpu->arch.pio.size,
de7d789a
CO		 2425 pd);
2426 mutex_unlock(&vcpu->kvm->lock);
2427}
2428
2429static void pio_string_write(struct kvm_io_device *pio_dev,
2430 struct kvm_vcpu *vcpu)
2431{
ad312c7c
ZX		 2432 struct kvm_pio_request *io = &vcpu->arch.pio;
2433 void *pd = vcpu->arch.pio_data;
de7d789a
CO		 2434 int i;
2435
2436 mutex_lock(&vcpu->kvm->lock);
2437 for (i = 0; i < io->cur_count; i++) {
2438 kvm_iodevice_write(pio_dev, io->port,
2439 io->size,
2440 pd);
2441 pd += io->size;
2442 }
2443 mutex_unlock(&vcpu->kvm->lock);
2444}
2445
2446static struct kvm_io_device *vcpu_find_pio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2447 gpa_t addr, int len,
2448 int is_write)
de7d789a 2449{
92760499 2450 return kvm_io_bus_find_dev(&vcpu->kvm->pio_bus, addr, len, is_write);
de7d789a
CO		 2451}
2452
2453int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2454 int size, unsigned port)
2455{
2456 struct kvm_io_device *pio_dev;
5fdbf976 2457 unsigned long val;
de7d789a
CO		 2458
2459 vcpu->run->exit_reason = KVM_EXIT_IO;
2460 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2461 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2462 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2463 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2464 vcpu->run->io.port = vcpu->arch.pio.port = port;
2465 vcpu->arch.pio.in = in;
2466 vcpu->arch.pio.string = 0;
2467 vcpu->arch.pio.down = 0;
2468 vcpu->arch.pio.guest_page_offset = 0;
2469 vcpu->arch.pio.rep = 0;
de7d789a 2470
2714d1d3
FEL		 2471 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2472 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2473 handler);
2474 else
2475 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2476 handler);
2477
5fdbf976
MT		 2478 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2479 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a
CO		 2480
2481 kvm_x86_ops->skip_emulated_instruction(vcpu);
2482
92760499 2483 pio_dev = vcpu_find_pio_dev(vcpu, port, size, !in);
de7d789a 2484 if (pio_dev) {
ad312c7c 2485 kernel_pio(pio_dev, vcpu, vcpu->arch.pio_data);
de7d789a
CO		 2486 complete_pio(vcpu);
2487 return 1;
2488 }
2489 return 0;
2490}
2491EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2492
2493int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2494 int size, unsigned long count, int down,
2495 gva_t address, int rep, unsigned port)
2496{
2497 unsigned now, in_page;
2498 int i, ret = 0;
2499 int nr_pages = 1;
2500 struct page *page;
2501 struct kvm_io_device *pio_dev;
2502
2503 vcpu->run->exit_reason = KVM_EXIT_IO;
2504 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2505 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2506 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2507 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2508 vcpu->run->io.port = vcpu->arch.pio.port = port;
2509 vcpu->arch.pio.in = in;
2510 vcpu->arch.pio.string = 1;
2511 vcpu->arch.pio.down = down;
2512 vcpu->arch.pio.guest_page_offset = offset_in_page(address);
2513 vcpu->arch.pio.rep = rep;
de7d789a 2514
2714d1d3
FEL		 2515 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2516 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2517 handler);
2518 else
2519 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2520 handler);
2521
de7d789a
CO		 2522 if (!count) {
2523 kvm_x86_ops->skip_emulated_instruction(vcpu);
2524 return 1;
2525 }
2526
2527 if (!down)
2528 in_page = PAGE_SIZE - offset_in_page(address);
2529 else
2530 in_page = offset_in_page(address) + size;
2531 now = min(count, (unsigned long)in_page / size);
2532 if (!now) {
2533 /*
2534 * String I/O straddles page boundary. Pin two guest pages
2535 * so that we satisfy atomicity constraints. Do just one
2536 * transaction to avoid complexity.
2537 */
2538 nr_pages = 2;
2539 now = 1;
2540 }
2541 if (down) {
2542 /*
2543 * String I/O in reverse. Yuck. Kill the guest, fix later.
2544 */
2545 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 2546 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2547 return 1;
2548 }
2549 vcpu->run->io.count = now;
ad312c7c 2550 vcpu->arch.pio.cur_count = now;
de7d789a 2551
ad312c7c 2552 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 2553 kvm_x86_ops->skip_emulated_instruction(vcpu);
2554
2555 for (i = 0; i < nr_pages; ++i) {
de7d789a 2556 page = gva_to_page(vcpu, address + i * PAGE_SIZE);
ad312c7c 2557 vcpu->arch.pio.guest_pages[i] = page;
de7d789a 2558 if (!page) {
c1a5d4f9 2559 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2560 free_pio_guest_pages(vcpu);
2561 return 1;
2562 }
2563 }
2564
92760499
LV		 2565 pio_dev = vcpu_find_pio_dev(vcpu, port,
2566 vcpu->arch.pio.cur_count,
2567 !vcpu->arch.pio.in);
ad312c7c 2568 if (!vcpu->arch.pio.in) {
de7d789a
CO		 2569 /* string PIO write */
2570 ret = pio_copy_data(vcpu);
2571 if (ret >= 0 && pio_dev) {
2572 pio_string_write(pio_dev, vcpu);
2573 complete_pio(vcpu);
ad312c7c 2574 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 2575 ret = 1;
2576 }
2577 } else if (pio_dev)
2578 pr_unimpl(vcpu, "no string pio read support yet, "
2579 "port %x size %d count %ld\n",
2580 port, size, count);
2581
2582 return ret;
2583}
2584EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
2585
f8c16bba 2586int kvm_arch_init(void *opaque)
043405e1 2587{
56c6d28a 2588 int r;
f8c16bba
ZX		 2589 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
2590
f8c16bba
ZX		 2591 if (kvm_x86_ops) {
2592 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 2593 r = -EEXIST;
2594 goto out;
f8c16bba
ZX		 2595 }
2596
2597 if (!ops->cpu_has_kvm_support()) {
2598 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 2599 r = -EOPNOTSUPP;
2600 goto out;
f8c16bba
ZX		 2601 }
2602 if (ops->disabled_by_bios()) {
2603 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 2604 r = -EOPNOTSUPP;
2605 goto out;
f8c16bba
ZX		 2606 }
2607
97db56ce
AK		 2608 r = kvm_mmu_module_init();
2609 if (r)
2610 goto out;
2611
2612 kvm_init_msr_list();
2613
f8c16bba 2614 kvm_x86_ops = ops;
56c6d28a 2615 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 2616 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
2617 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
64d4d521 2618 PT_DIRTY_MASK, PT64_NX_MASK, 0, 0);
f8c16bba 2619 return 0;
56c6d28a
ZX		 2620
2621out:
56c6d28a 2622 return r;
043405e1 2623}
8776e519 2624
f8c16bba
ZX		 2625void kvm_arch_exit(void)
2626{
2627 kvm_x86_ops = NULL;
56c6d28a
ZX		 2628 kvm_mmu_module_exit();
2629}
f8c16bba 2630
8776e519
HB		 2631int kvm_emulate_halt(struct kvm_vcpu *vcpu)
2632{
2633 ++vcpu->stat.halt_exits;
2714d1d3 2634 KVMTRACE_0D(HLT, vcpu, handler);
8776e519 2635 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 2636 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 2637 return 1;
2638 } else {
2639 vcpu->run->exit_reason = KVM_EXIT_HLT;
2640 return 0;
2641 }
2642}
2643EXPORT_SYMBOL_GPL(kvm_emulate_halt);
2644
2f333bcb
MT		 2645static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
2646 unsigned long a1)
2647{
2648 if (is_long_mode(vcpu))
2649 return a0;
2650 else
2651 return a0 | ((gpa_t)a1 << 32);
2652}
2653
8776e519
HB		 2654int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
2655{
2656 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 2657 int r = 1;
8776e519 2658
5fdbf976
MT		 2659 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
2660 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
2661 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
2662 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
2663 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 2664
2714d1d3
FEL		 2665 KVMTRACE_1D(VMMCALL, vcpu, (u32)nr, handler);
2666
8776e519
HB		 2667 if (!is_long_mode(vcpu)) {
2668 nr &= 0xFFFFFFFF;
2669 a0 &= 0xFFFFFFFF;
2670 a1 &= 0xFFFFFFFF;
2671 a2 &= 0xFFFFFFFF;
2672 a3 &= 0xFFFFFFFF;
2673 }
2674
2675 switch (nr) {
b93463aa
AK		 2676 case KVM_HC_VAPIC_POLL_IRQ:
2677 ret = 0;
2678 break;
2f333bcb
MT		 2679 case KVM_HC_MMU_OP:
2680 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
2681 break;
8776e519
HB		 2682 default:
2683 ret = -KVM_ENOSYS;
2684 break;
2685 }
5fdbf976 2686 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 2687 ++vcpu->stat.hypercalls;
2f333bcb 2688 return r;
8776e519
HB		 2689}
2690EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
2691
2692int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
2693{
2694 char instruction[3];
2695 int ret = 0;
5fdbf976 2696 unsigned long rip = kvm_rip_read(vcpu);
8776e519 2697
8776e519
HB		 2698
2699 /*
2700 * Blow out the MMU to ensure that no other VCPU has an active mapping
2701 * to ensure that the updated hypercall appears atomically across all
2702 * VCPUs.
2703 */
2704 kvm_mmu_zap_all(vcpu->kvm);
2705
8776e519 2706 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 2707 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 2708 != X86EMUL_CONTINUE)
2709 ret = -EFAULT;
2710
8776e519
HB		 2711 return ret;
2712}
2713
2714static u64 mk_cr_64(u64 curr_cr, u32 new_val)
2715{
2716 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
2717}
2718
2719void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2720{
2721 struct descriptor_table dt = { limit, base };
2722
2723 kvm_x86_ops->set_gdt(vcpu, &dt);
2724}
2725
2726void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2727{
2728 struct descriptor_table dt = { limit, base };
2729
2730 kvm_x86_ops->set_idt(vcpu, &dt);
2731}
2732
2733void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
2734 unsigned long *rflags)
2735{
2d3ad1f4 2736 kvm_lmsw(vcpu, msw);
8776e519
HB		 2737 *rflags = kvm_x86_ops->get_rflags(vcpu);
2738}
2739
2740unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
2741{
54e445ca
JR		 2742 unsigned long value;
2743
8776e519
HB		 2744 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
2745 switch (cr) {
2746 case 0:
54e445ca
JR		 2747 value = vcpu->arch.cr0;
2748 break;
8776e519 2749 case 2:
54e445ca
JR		 2750 value = vcpu->arch.cr2;
2751 break;
8776e519 2752 case 3:
54e445ca
JR		 2753 value = vcpu->arch.cr3;
2754 break;
8776e519 2755 case 4:
54e445ca
JR		 2756 value = vcpu->arch.cr4;
2757 break;
152ff9be 2758 case 8:
54e445ca
JR		 2759 value = kvm_get_cr8(vcpu);
2760 break;
8776e519 2761 default:
b8688d51 2762 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2763 return 0;
2764 }
54e445ca
JR		 2765 KVMTRACE_3D(CR_READ, vcpu, (u32)cr, (u32)value,
2766 (u32)((u64)value >> 32), handler);
2767
2768 return value;
8776e519
HB		 2769}
2770
2771void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
2772 unsigned long *rflags)
2773{
54e445ca
JR		 2774 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)val,
2775 (u32)((u64)val >> 32), handler);
2776
8776e519
HB		 2777 switch (cr) {
2778 case 0:
2d3ad1f4 2779 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 2780 *rflags = kvm_x86_ops->get_rflags(vcpu);
2781 break;
2782 case 2:
ad312c7c 2783 vcpu->arch.cr2 = val;
8776e519
HB		 2784 break;
2785 case 3:
2d3ad1f4 2786 kvm_set_cr3(vcpu, val);
8776e519
HB		 2787 break;
2788 case 4:
2d3ad1f4 2789 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 2790 break;
152ff9be 2791 case 8:
2d3ad1f4 2792 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 2793 break;
8776e519 2794 default:
b8688d51 2795 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2796 }
2797}
2798
07716717
DK		 2799static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
2800{
ad312c7c
ZX		 2801 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
2802 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 2803
2804 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
2805 /* when no next entry is found, the current entry[i] is reselected */
2806 for (j = i + 1; j == i; j = (j + 1) % nent) {
ad312c7c 2807 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 2808 if (ej->function == e->function) {
2809 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
2810 return j;
2811 }
2812 }
2813 return 0; /* silence gcc, even though control never reaches here */
2814}
2815
2816/* find an entry with matching function, matching index (if needed), and that
2817 * should be read next (if it's stateful) */
2818static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
2819 u32 function, u32 index)
2820{
2821 if (e->function != function)
2822 return 0;
2823 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
2824 return 0;
2825 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
2826 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
2827 return 0;
2828 return 1;
2829}
2830
8776e519
HB		 2831void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
2832{
2833 int i;
07716717
DK		 2834 u32 function, index;
2835 struct kvm_cpuid_entry2 *e, *best;
8776e519 2836
5fdbf976
MT		 2837 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
2838 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
2839 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
2840 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
2841 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
2842 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
8776e519 2843 best = NULL;
ad312c7c
ZX		 2844 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2845 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 2846 if (is_matching_cpuid_entry(e, function, index)) {
2847 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
2848 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 2849 best = e;
2850 break;
2851 }
2852 /*
2853 * Both basic or both extended?
2854 */
2855 if (((e->function ^ function) & 0x80000000) == 0)
2856 if (!best || e->function > best->function)
2857 best = e;
2858 }
2859 if (best) {
5fdbf976
MT		 2860 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
2861 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
2862 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
2863 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 2864 }
8776e519 2865 kvm_x86_ops->skip_emulated_instruction(vcpu);
2714d1d3 2866 KVMTRACE_5D(CPUID, vcpu, function,
5fdbf976
MT		 2867 (u32)kvm_register_read(vcpu, VCPU_REGS_RAX),
2868 (u32)kvm_register_read(vcpu, VCPU_REGS_RBX),
2869 (u32)kvm_register_read(vcpu, VCPU_REGS_RCX),
2870 (u32)kvm_register_read(vcpu, VCPU_REGS_RDX), handler);
8776e519
HB		 2871}
2872EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 2873
b6c7a5dc
HB		 2874/*
2875 * Check if userspace requested an interrupt window, and that the
2876 * interrupt window is open.
2877 *
2878 * No need to exit to userspace if we already have an interrupt queued.
2879 */
2880static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
2881 struct kvm_run *kvm_run)
2882{
ad312c7c 2883 return (!vcpu->arch.irq_summary &&
b6c7a5dc 2884 kvm_run->request_interrupt_window &&
ad312c7c 2885 vcpu->arch.interrupt_window_open &&
b6c7a5dc
HB		 2886 (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF));
2887}
2888
c4abb7c9
JK		 2889/*
2890 * Check if userspace requested a NMI window, and that the NMI window
2891 * is open.
2892 *
2893 * No need to exit to userspace if we already have a NMI queued.
2894 */
2895static int dm_request_for_nmi_injection(struct kvm_vcpu *vcpu,
2896 struct kvm_run *kvm_run)
2897{
2898 return (!vcpu->arch.nmi_pending &&
2899 kvm_run->request_nmi_window &&
2900 vcpu->arch.nmi_window_open);
2901}
2902
b6c7a5dc
HB		 2903static void post_kvm_run_save(struct kvm_vcpu *vcpu,
2904 struct kvm_run *kvm_run)
2905{
2906 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 2907 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 2908 kvm_run->apic_base = kvm_get_apic_base(vcpu);
c4abb7c9 2909 if (irqchip_in_kernel(vcpu->kvm)) {
b6c7a5dc 2910 kvm_run->ready_for_interrupt_injection = 1;
c4abb7c9
JK		 2911 kvm_run->ready_for_nmi_injection = 1;
2912 } else {
b6c7a5dc 2913 kvm_run->ready_for_interrupt_injection =
ad312c7c
ZX		 2914 (vcpu->arch.interrupt_window_open &&
2915 vcpu->arch.irq_summary == 0);
c4abb7c9
JK		 2916 kvm_run->ready_for_nmi_injection =
2917 (vcpu->arch.nmi_window_open &&
2918 vcpu->arch.nmi_pending == 0);
2919 }
b6c7a5dc
HB		 2920}
2921
b93463aa
AK		 2922static void vapic_enter(struct kvm_vcpu *vcpu)
2923{
2924 struct kvm_lapic *apic = vcpu->arch.apic;
2925 struct page *page;
2926
2927 if (!apic || !apic->vapic_addr)
2928 return;
2929
2930 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 2931
2932 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 2933}
2934
2935static void vapic_exit(struct kvm_vcpu *vcpu)
2936{
2937 struct kvm_lapic *apic = vcpu->arch.apic;
2938
2939 if (!apic || !apic->vapic_addr)
2940 return;
2941
f8b78fa3 2942 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 2943 kvm_release_page_dirty(apic->vapic_page);
2944 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 2945 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 2946}
2947
d7690175 2948static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
b6c7a5dc
HB		 2949{
2950 int r;
2951
2e53d63a
MT		 2952 if (vcpu->requests)
2953 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
2954 kvm_mmu_unload(vcpu);
2955
b6c7a5dc
HB		 2956 r = kvm_mmu_reload(vcpu);
2957 if (unlikely(r))
2958 goto out;
2959
2f52d58c
AK		 2960 if (vcpu->requests) {
2961 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 2962 __kvm_migrate_timers(vcpu);
4731d4c7
MT		 2963 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
2964 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 2965 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
2966 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 2967 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
2968 &vcpu->requests)) {
2969 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
2970 r = 0;
2971 goto out;
2972 }
71c4dfaf
JR		 2973 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
2974 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2975 r = 0;
2976 goto out;
2977 }
2f52d58c 2978 }
b93463aa 2979
06e05645 2980 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
b6c7a5dc
HB		 2981 kvm_inject_pending_timer_irqs(vcpu);
2982
2983 preempt_disable();
2984
2985 kvm_x86_ops->prepare_guest_switch(vcpu);
2986 kvm_load_guest_fpu(vcpu);
2987
2988 local_irq_disable();
2989
d7690175 2990 if (vcpu->requests || need_resched() || signal_pending(current)) {
6c142801
AK		 2991 local_irq_enable();
2992 preempt_enable();
2993 r = 1;
2994 goto out;
2995 }
2996
29415c37
MT		 2997 if (vcpu->guest_debug.enabled)
2998 kvm_x86_ops->guest_debug_pre(vcpu);
b6c7a5dc 2999
e9571ed5
MT		 3000 vcpu->guest_mode = 1;
3001 /*
3002 * Make sure that guest_mode assignment won't happen after
3003 * testing the pending IRQ vector bitmap.
3004 */
3005 smp_wmb();
3006
ad312c7c 3007 if (vcpu->arch.exception.pending)
298101da
AK		 3008 __queue_exception(vcpu);
3009 else if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3010 kvm_x86_ops->inject_pending_irq(vcpu);
eb9774f0 3011 else
b6c7a5dc
HB		 3012 kvm_x86_ops->inject_pending_vectors(vcpu, kvm_run);
3013
b93463aa
AK		 3014 kvm_lapic_sync_to_vapic(vcpu);
3015
3200f405
MT		 3016 up_read(&vcpu->kvm->slots_lock);
3017
b6c7a5dc
HB		 3018 kvm_guest_enter();
3019
b6c7a5dc 3020
2714d1d3 3021 KVMTRACE_0D(VMENTRY, vcpu, entryexit);
b6c7a5dc
HB		 3022 kvm_x86_ops->run(vcpu, kvm_run);
3023
3024 vcpu->guest_mode = 0;
3025 local_irq_enable();
3026
3027 ++vcpu->stat.exits;
3028
3029 /*
3030 * We must have an instruction between local_irq_enable() and
3031 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3032 * the interrupt shadow. The stat.exits increment will do nicely.
3033 * But we need to prevent reordering, hence this barrier():
3034 */
3035 barrier();
3036
3037 kvm_guest_exit();
3038
3039 preempt_enable();
3040
3200f405
MT		 3041 down_read(&vcpu->kvm->slots_lock);
3042
b6c7a5dc
HB		 3043 /*
3044 * Profile KVM exit RIPs:
3045 */
3046 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 3047 unsigned long rip = kvm_rip_read(vcpu);
3048 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 3049 }
3050
ad312c7c
ZX		 3051 if (vcpu->arch.exception.pending && kvm_x86_ops->exception_injected(vcpu))
3052 vcpu->arch.exception.pending = false;
298101da 3053
b93463aa
AK		 3054 kvm_lapic_sync_from_vapic(vcpu);
3055
b6c7a5dc 3056 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
d7690175
MT		 3057out:
3058 return r;
3059}
b6c7a5dc 3060
d7690175
MT		 3061static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3062{
3063 int r;
3064
3065 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 3066 pr_debug("vcpu %d received sipi with vector # %x\n",
3067 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 3068 kvm_lapic_reset(vcpu);
5f179287 3069 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 3070 if (r)
3071 return r;
3072 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 3073 }
3074
d7690175
MT		 3075 down_read(&vcpu->kvm->slots_lock);
3076 vapic_enter(vcpu);
3077
3078 r = 1;
3079 while (r > 0) {
af2152f5 3080 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
d7690175
MT		 3081 r = vcpu_enter_guest(vcpu, kvm_run);
3082 else {
3083 up_read(&vcpu->kvm->slots_lock);
3084 kvm_vcpu_block(vcpu);
3085 down_read(&vcpu->kvm->slots_lock);
3086 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
3087 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
3088 vcpu->arch.mp_state =
3089 KVM_MP_STATE_RUNNABLE;
3090 if (vcpu->arch.mp_state != KVM_MP_STATE_RUNNABLE)
3091 r = -EINTR;
3092 }
3093
3094 if (r > 0) {
c4abb7c9
JK		 3095 if (dm_request_for_nmi_injection(vcpu, kvm_run)) {
3096 r = -EINTR;
3097 kvm_run->exit_reason = KVM_EXIT_NMI;
3098 ++vcpu->stat.request_nmi_exits;
3099 }
d7690175
MT		 3100 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
3101 r = -EINTR;
3102 kvm_run->exit_reason = KVM_EXIT_INTR;
3103 ++vcpu->stat.request_irq_exits;
3104 }
3105 if (signal_pending(current)) {
3106 r = -EINTR;
3107 kvm_run->exit_reason = KVM_EXIT_INTR;
3108 ++vcpu->stat.signal_exits;
3109 }
3110 if (need_resched()) {
3111 up_read(&vcpu->kvm->slots_lock);
3112 kvm_resched(vcpu);
3113 down_read(&vcpu->kvm->slots_lock);
3114 }
3115 }
b6c7a5dc
HB		 3116 }
3117
d7690175 3118 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3119 post_kvm_run_save(vcpu, kvm_run);
3120
b93463aa
AK		 3121 vapic_exit(vcpu);
3122
b6c7a5dc
HB		 3123 return r;
3124}
3125
3126int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3127{
3128 int r;
3129 sigset_t sigsaved;
3130
3131 vcpu_load(vcpu);
3132
ac9f6dc0
AK		 3133 if (vcpu->sigset_active)
3134 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
3135
a4535290 3136 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 3137 kvm_vcpu_block(vcpu);
d7690175 3138 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 3139 r = -EAGAIN;
3140 goto out;
b6c7a5dc
HB		 3141 }
3142
b6c7a5dc
HB		 3143 /* re-sync apic's tpr */
3144 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 3145 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 3146
ad312c7c 3147 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 3148 r = complete_pio(vcpu);
3149 if (r)
3150 goto out;
3151 }
3152#if CONFIG_HAS_IOMEM
3153 if (vcpu->mmio_needed) {
3154 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3155 vcpu->mmio_read_completed = 1;
3156 vcpu->mmio_needed = 0;
3200f405
MT		 3157
3158 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc 3159 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 3160 vcpu->arch.mmio_fault_cr2, 0,
3161 EMULTYPE_NO_DECODE);
3200f405 3162 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3163 if (r == EMULATE_DO_MMIO) {
3164 /*
3165 * Read-modify-write. Back to userspace.
3166 */
3167 r = 0;
3168 goto out;
3169 }
3170 }
3171#endif
5fdbf976
MT		 3172 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3173 kvm_register_write(vcpu, VCPU_REGS_RAX,
3174 kvm_run->hypercall.ret);
b6c7a5dc
HB		 3175
3176 r = __vcpu_run(vcpu, kvm_run);
3177
3178out:
3179 if (vcpu->sigset_active)
3180 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3181
3182 vcpu_put(vcpu);
3183 return r;
3184}
3185
3186int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3187{
3188 vcpu_load(vcpu);
3189
5fdbf976
MT		 3190 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3191 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3192 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3193 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3194 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3195 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3196 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3197 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 3198#ifdef CONFIG_X86_64
5fdbf976
MT		 3199 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3200 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3201 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3202 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3203 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3204 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3205 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3206 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 3207#endif
3208
5fdbf976 3209 regs->rip = kvm_rip_read(vcpu);
b6c7a5dc
HB		 3210 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3211
3212 /*
3213 * Don't leak debug flags in case they were set for guest debugging
3214 */
3215 if (vcpu->guest_debug.enabled && vcpu->guest_debug.singlestep)
3216 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3217
3218 vcpu_put(vcpu);
3219
3220 return 0;
3221}
3222
3223int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3224{
3225 vcpu_load(vcpu);
3226
5fdbf976
MT		 3227 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3228 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3229 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3230 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3231 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3232 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3233 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3234 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 3235#ifdef CONFIG_X86_64
5fdbf976
MT		 3236 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3237 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3238 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3239 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3240 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3241 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3242 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3243 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
3244
b6c7a5dc
HB		 3245#endif
3246
5fdbf976 3247 kvm_rip_write(vcpu, regs->rip);
b6c7a5dc
HB		 3248 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3249
b6c7a5dc 3250
b4f14abd
JK		 3251 vcpu->arch.exception.pending = false;
3252
b6c7a5dc
HB		 3253 vcpu_put(vcpu);
3254
3255 return 0;
3256}
3257
3e6e0aab
GT		 3258void kvm_get_segment(struct kvm_vcpu *vcpu,
3259 struct kvm_segment *var, int seg)
b6c7a5dc 3260{
14af3f3c 3261 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 3262}
3263
3264void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3265{
3266 struct kvm_segment cs;
3267
3e6e0aab 3268 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 3269 *db = cs.db;
3270 *l = cs.l;
3271}
3272EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3273
3274int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3275 struct kvm_sregs *sregs)
3276{
3277 struct descriptor_table dt;
3278 int pending_vec;
3279
3280 vcpu_load(vcpu);
3281
3e6e0aab
GT		 3282 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3283 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3284 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3285 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3286 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3287 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3288
3e6e0aab
GT		 3289 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3290 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3291
3292 kvm_x86_ops->get_idt(vcpu, &dt);
3293 sregs->idt.limit = dt.limit;
3294 sregs->idt.base = dt.base;
3295 kvm_x86_ops->get_gdt(vcpu, &dt);
3296 sregs->gdt.limit = dt.limit;
3297 sregs->gdt.base = dt.base;
3298
3299 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3300 sregs->cr0 = vcpu->arch.cr0;
3301 sregs->cr2 = vcpu->arch.cr2;
3302 sregs->cr3 = vcpu->arch.cr3;
3303 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3304 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3305 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3306 sregs->apic_base = kvm_get_apic_base(vcpu);
3307
3308 if (irqchip_in_kernel(vcpu->kvm)) {
3309 memset(sregs->interrupt_bitmap, 0,
3310 sizeof sregs->interrupt_bitmap);
3311 pending_vec = kvm_x86_ops->get_irq(vcpu);
3312 if (pending_vec >= 0)
3313 set_bit(pending_vec,
3314 (unsigned long *)sregs->interrupt_bitmap);
3315 } else
ad312c7c 3316 memcpy(sregs->interrupt_bitmap, vcpu->arch.irq_pending,
b6c7a5dc
HB		 3317 sizeof sregs->interrupt_bitmap);
3318
3319 vcpu_put(vcpu);
3320
3321 return 0;
3322}
3323
62d9f0db
MT		 3324int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3325 struct kvm_mp_state *mp_state)
3326{
3327 vcpu_load(vcpu);
3328 mp_state->mp_state = vcpu->arch.mp_state;
3329 vcpu_put(vcpu);
3330 return 0;
3331}
3332
3333int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3334 struct kvm_mp_state *mp_state)
3335{
3336 vcpu_load(vcpu);
3337 vcpu->arch.mp_state = mp_state->mp_state;
3338 vcpu_put(vcpu);
3339 return 0;
3340}
3341
3e6e0aab 3342static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 3343 struct kvm_segment *var, int seg)
3344{
14af3f3c 3345 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 3346}
3347
37817f29
IE		 3348static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3349 struct kvm_segment *kvm_desct)
3350{
3351 kvm_desct->base = seg_desc->base0;
3352 kvm_desct->base |= seg_desc->base1 << 16;
3353 kvm_desct->base |= seg_desc->base2 << 24;
3354 kvm_desct->limit = seg_desc->limit0;
3355 kvm_desct->limit |= seg_desc->limit << 16;
c93cd3a5
MT		 3356 if (seg_desc->g) {
3357 kvm_desct->limit <<= 12;
3358 kvm_desct->limit |= 0xfff;
3359 }
37817f29
IE		 3360 kvm_desct->selector = selector;
3361 kvm_desct->type = seg_desc->type;
3362 kvm_desct->present = seg_desc->p;
3363 kvm_desct->dpl = seg_desc->dpl;
3364 kvm_desct->db = seg_desc->d;
3365 kvm_desct->s = seg_desc->s;
3366 kvm_desct->l = seg_desc->l;
3367 kvm_desct->g = seg_desc->g;
3368 kvm_desct->avl = seg_desc->avl;
3369 if (!selector)
3370 kvm_desct->unusable = 1;
3371 else
3372 kvm_desct->unusable = 0;
3373 kvm_desct->padding = 0;
3374}
3375
3376static void get_segment_descritptor_dtable(struct kvm_vcpu *vcpu,
3377 u16 selector,
3378 struct descriptor_table *dtable)
3379{
3380 if (selector & 1 << 2) {
3381 struct kvm_segment kvm_seg;
3382
3e6e0aab 3383 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 3384
3385 if (kvm_seg.unusable)
3386 dtable->limit = 0;
3387 else
3388 dtable->limit = kvm_seg.limit;
3389 dtable->base = kvm_seg.base;
3390 }
3391 else
3392 kvm_x86_ops->get_gdt(vcpu, dtable);
3393}
3394
3395/* allowed just for 8 bytes segments */
3396static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3397 struct desc_struct *seg_desc)
3398{
98899aa0 3399 gpa_t gpa;
37817f29
IE		 3400 struct descriptor_table dtable;
3401 u16 index = selector >> 3;
3402
3403 get_segment_descritptor_dtable(vcpu, selector, &dtable);
3404
3405 if (dtable.limit < index * 8 + 7) {
3406 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
3407 return 1;
3408 }
98899aa0
MT		 3409 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3410 gpa += index * 8;
3411 return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3412}
3413
3414/* allowed just for 8 bytes segments */
3415static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3416 struct desc_struct *seg_desc)
3417{
98899aa0 3418 gpa_t gpa;
37817f29
IE		 3419 struct descriptor_table dtable;
3420 u16 index = selector >> 3;
3421
3422 get_segment_descritptor_dtable(vcpu, selector, &dtable);
3423
3424 if (dtable.limit < index * 8 + 7)
3425 return 1;
98899aa0
MT		 3426 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3427 gpa += index * 8;
3428 return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3429}
3430
3431static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
3432 struct desc_struct *seg_desc)
3433{
3434 u32 base_addr;
3435
3436 base_addr = seg_desc->base0;
3437 base_addr |= (seg_desc->base1 << 16);
3438 base_addr |= (seg_desc->base2 << 24);
3439
98899aa0 3440 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 3441}
3442
37817f29
IE		 3443static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
3444{
3445 struct kvm_segment kvm_seg;
3446
3e6e0aab 3447 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3448 return kvm_seg.selector;
3449}
3450
3451static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
3452 u16 selector,
3453 struct kvm_segment *kvm_seg)
3454{
3455 struct desc_struct seg_desc;
3456
3457 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
3458 return 1;
3459 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
3460 return 0;
3461}
3462
2259e3a7 3463static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 3464{
3465 struct kvm_segment segvar = {
3466 .base = selector << 4,
3467 .limit = 0xffff,
3468 .selector = selector,
3469 .type = 3,
3470 .present = 1,
3471 .dpl = 3,
3472 .db = 0,
3473 .s = 1,
3474 .l = 0,
3475 .g = 0,
3476 .avl = 0,
3477 .unusable = 0,
3478 };
3479 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
3480 return 0;
3481}
3482
3e6e0aab
GT		 3483int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3484 int type_bits, int seg)
37817f29
IE		 3485{
3486 struct kvm_segment kvm_seg;
3487
f4bbd9aa
AK		 3488 if (!(vcpu->arch.cr0 & X86_CR0_PE))
3489 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 3490 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
3491 return 1;
3492 kvm_seg.type |= type_bits;
3493
3494 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
3495 seg != VCPU_SREG_LDTR)
3496 if (!kvm_seg.s)
3497 kvm_seg.unusable = 1;
3498
3e6e0aab 3499 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3500 return 0;
3501}
3502
3503static void save_state_to_tss32(struct kvm_vcpu *vcpu,
3504 struct tss_segment_32 *tss)
3505{
3506 tss->cr3 = vcpu->arch.cr3;
5fdbf976 3507 tss->eip = kvm_rip_read(vcpu);
37817f29 3508 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 3509 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3510 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3511 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3512 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3513 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3514 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3515 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3516 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 3517 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3518 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3519 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3520 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3521 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
3522 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
3523 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3524 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3525}
3526
3527static int load_state_from_tss32(struct kvm_vcpu *vcpu,
3528 struct tss_segment_32 *tss)
3529{
3530 kvm_set_cr3(vcpu, tss->cr3);
3531
5fdbf976 3532 kvm_rip_write(vcpu, tss->eip);
37817f29
IE		 3533 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
3534
5fdbf976
MT		 3535 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
3536 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
3537 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
3538 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
3539 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
3540 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
3541 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
3542 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 3543
3e6e0aab 3544 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 3545 return 1;
3546
3e6e0aab 3547 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 3548 return 1;
3549
3e6e0aab 3550 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 3551 return 1;
3552
3e6e0aab 3553 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 3554 return 1;
3555
3e6e0aab 3556 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 3557 return 1;
3558
3e6e0aab 3559 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 3560 return 1;
3561
3e6e0aab 3562 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 3563 return 1;
3564 return 0;
3565}
3566
3567static void save_state_to_tss16(struct kvm_vcpu *vcpu,
3568 struct tss_segment_16 *tss)
3569{
5fdbf976 3570 tss->ip = kvm_rip_read(vcpu);
37817f29 3571 tss->flag = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 3572 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3573 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3574 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3575 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3576 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3577 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3578 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
3579 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 3580
3581 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3582 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3583 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3584 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3585 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3586 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3587}
3588
3589static int load_state_from_tss16(struct kvm_vcpu *vcpu,
3590 struct tss_segment_16 *tss)
3591{
5fdbf976 3592 kvm_rip_write(vcpu, tss->ip);
37817f29 3593 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 3594 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
3595 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
3596 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
3597 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
3598 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
3599 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
3600 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
3601 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 3602
3e6e0aab 3603 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 3604 return 1;
3605
3e6e0aab 3606 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 3607 return 1;
3608
3e6e0aab 3609 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 3610 return 1;
3611
3e6e0aab 3612 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 3613 return 1;
3614
3e6e0aab 3615 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 3616 return 1;
3617 return 0;
3618}
3619
8b2cf73c 3620static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
34198bf8 3621 u32 old_tss_base,
37817f29
IE		 3622 struct desc_struct *nseg_desc)
3623{
3624 struct tss_segment_16 tss_segment_16;
3625 int ret = 0;
3626
34198bf8
MT		 3627 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
3628 sizeof tss_segment_16))
37817f29
IE		 3629 goto out;
3630
3631 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 3632
34198bf8
MT		 3633 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
3634 sizeof tss_segment_16))
37817f29 3635 goto out;
34198bf8
MT		 3636
3637 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
3638 &tss_segment_16, sizeof tss_segment_16))
3639 goto out;
3640
37817f29
IE		 3641 if (load_state_from_tss16(vcpu, &tss_segment_16))
3642 goto out;
3643
3644 ret = 1;
3645out:
3646 return ret;
3647}
3648
8b2cf73c 3649static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
34198bf8 3650 u32 old_tss_base,
37817f29
IE		 3651 struct desc_struct *nseg_desc)
3652{
3653 struct tss_segment_32 tss_segment_32;
3654 int ret = 0;
3655
34198bf8
MT		 3656 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
3657 sizeof tss_segment_32))
37817f29
IE		 3658 goto out;
3659
3660 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 3661
34198bf8
MT		 3662 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
3663 sizeof tss_segment_32))
3664 goto out;
3665
3666 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
3667 &tss_segment_32, sizeof tss_segment_32))
37817f29 3668 goto out;
34198bf8 3669
37817f29
IE		 3670 if (load_state_from_tss32(vcpu, &tss_segment_32))
3671 goto out;
3672
3673 ret = 1;
3674out:
3675 return ret;
3676}
3677
3678int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
3679{
3680 struct kvm_segment tr_seg;
3681 struct desc_struct cseg_desc;
3682 struct desc_struct nseg_desc;
3683 int ret = 0;
34198bf8
MT		 3684 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
3685 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 3686
34198bf8 3687 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 3688
34198bf8
MT		 3689 /* FIXME: Handle errors. Failure to read either TSS or their
3690 * descriptors should generate a pagefault.
3691 */
37817f29
IE		 3692 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
3693 goto out;
3694
34198bf8 3695 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 3696 goto out;
3697
37817f29
IE		 3698 if (reason != TASK_SWITCH_IRET) {
3699 int cpl;
3700
3701 cpl = kvm_x86_ops->get_cpl(vcpu);
3702 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
3703 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
3704 return 1;
3705 }
3706 }
3707
3708 if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) {
3709 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
3710 return 1;
3711 }
3712
3713 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 3714 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 3715 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 3716 }
3717
3718 if (reason == TASK_SWITCH_IRET) {
3719 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3720 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
3721 }
3722
3723 kvm_x86_ops->skip_emulated_instruction(vcpu);
37817f29
IE		 3724
3725 if (nseg_desc.type & 8)
34198bf8 3726 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_base,
37817f29
IE		 3727 &nseg_desc);
3728 else
34198bf8 3729 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_base,
37817f29
IE		 3730 &nseg_desc);
3731
3732 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
3733 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3734 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
3735 }
3736
3737 if (reason != TASK_SWITCH_IRET) {
3fe913e7 3738 nseg_desc.type |= (1 << 1);
37817f29
IE		 3739 save_guest_segment_descriptor(vcpu, tss_selector,
3740 &nseg_desc);
3741 }
3742
3743 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
3744 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
3745 tr_seg.type = 11;
3e6e0aab 3746 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 3747out:
37817f29
IE		 3748 return ret;
3749}
3750EXPORT_SYMBOL_GPL(kvm_task_switch);
3751
b6c7a5dc
HB		 3752int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
3753 struct kvm_sregs *sregs)
3754{
3755 int mmu_reset_needed = 0;
3756 int i, pending_vec, max_bits;
3757 struct descriptor_table dt;
3758
3759 vcpu_load(vcpu);
3760
3761 dt.limit = sregs->idt.limit;
3762 dt.base = sregs->idt.base;
3763 kvm_x86_ops->set_idt(vcpu, &dt);
3764 dt.limit = sregs->gdt.limit;
3765 dt.base = sregs->gdt.base;
3766 kvm_x86_ops->set_gdt(vcpu, &dt);
3767
ad312c7c
ZX		 3768 vcpu->arch.cr2 = sregs->cr2;
3769 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
3770 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 3771
2d3ad1f4 3772 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 3773
ad312c7c 3774 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 3775 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 3776 kvm_set_apic_base(vcpu, sregs->apic_base);
3777
3778 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3779
ad312c7c 3780 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 3781 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 3782 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 3783
ad312c7c 3784 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 3785 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3786 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 3787 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 3788
3789 if (mmu_reset_needed)
3790 kvm_mmu_reset_context(vcpu);
3791
3792 if (!irqchip_in_kernel(vcpu->kvm)) {
ad312c7c
ZX		 3793 memcpy(vcpu->arch.irq_pending, sregs->interrupt_bitmap,
3794 sizeof vcpu->arch.irq_pending);
3795 vcpu->arch.irq_summary = 0;
3796 for (i = 0; i < ARRAY_SIZE(vcpu->arch.irq_pending); ++i)
3797 if (vcpu->arch.irq_pending[i])
3798 __set_bit(i, &vcpu->arch.irq_summary);
b6c7a5dc
HB		 3799 } else {
3800 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
3801 pending_vec = find_first_bit(
3802 (const unsigned long *)sregs->interrupt_bitmap,
3803 max_bits);
3804 /* Only pending external irq is handled here */
3805 if (pending_vec < max_bits) {
3806 kvm_x86_ops->set_irq(vcpu, pending_vec);
3807 pr_debug("Set back pending irq %d\n",
3808 pending_vec);
3809 }
e4825800 3810 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 3811 }
3812
3e6e0aab
GT		 3813 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3814 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3815 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3816 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3817 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3818 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3819
3e6e0aab
GT		 3820 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3821 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 3822
9c3e4aab
MT		 3823 /* Older userspace won't unhalt the vcpu on reset. */
3824 if (vcpu->vcpu_id == 0 && kvm_rip_read(vcpu) == 0xfff0 &&
3825 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3826 !(vcpu->arch.cr0 & X86_CR0_PE))
3827 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
3828
b6c7a5dc
HB		 3829 vcpu_put(vcpu);
3830
3831 return 0;
3832}
3833
3834int kvm_arch_vcpu_ioctl_debug_guest(struct kvm_vcpu *vcpu,
3835 struct kvm_debug_guest *dbg)
3836{
3837 int r;
3838
3839 vcpu_load(vcpu);
3840
3841 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
3842
3843 vcpu_put(vcpu);
3844
3845 return r;
3846}
3847
d0752060
HB		 3848/*
3849 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
3850 * we have asm/x86/processor.h
3851 */
3852struct fxsave {
3853 u16 cwd;
3854 u16 swd;
3855 u16 twd;
3856 u16 fop;
3857 u64 rip;
3858 u64 rdp;
3859 u32 mxcsr;
3860 u32 mxcsr_mask;
3861 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
3862#ifdef CONFIG_X86_64
3863 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
3864#else
3865 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
3866#endif
3867};
3868
8b006791
ZX		 3869/*
3870 * Translate a guest virtual address to a guest physical address.
3871 */
3872int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
3873 struct kvm_translation *tr)
3874{
3875 unsigned long vaddr = tr->linear_address;
3876 gpa_t gpa;
3877
3878 vcpu_load(vcpu);
72dc67a6 3879 down_read(&vcpu->kvm->slots_lock);
ad312c7c 3880 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 3881 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 3882 tr->physical_address = gpa;
3883 tr->valid = gpa != UNMAPPED_GVA;
3884 tr->writeable = 1;
3885 tr->usermode = 0;
8b006791
ZX		 3886 vcpu_put(vcpu);
3887
3888 return 0;
3889}
3890
d0752060
HB		 3891int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
3892{
ad312c7c 3893 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 3894
3895 vcpu_load(vcpu);
3896
3897 memcpy(fpu->fpr, fxsave->st_space, 128);
3898 fpu->fcw = fxsave->cwd;
3899 fpu->fsw = fxsave->swd;
3900 fpu->ftwx = fxsave->twd;
3901 fpu->last_opcode = fxsave->fop;
3902 fpu->last_ip = fxsave->rip;
3903 fpu->last_dp = fxsave->rdp;
3904 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
3905
3906 vcpu_put(vcpu);
3907
3908 return 0;
3909}
3910
3911int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
3912{
ad312c7c 3913 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 3914
3915 vcpu_load(vcpu);
3916
3917 memcpy(fxsave->st_space, fpu->fpr, 128);
3918 fxsave->cwd = fpu->fcw;
3919 fxsave->swd = fpu->fsw;
3920 fxsave->twd = fpu->ftwx;
3921 fxsave->fop = fpu->last_opcode;
3922 fxsave->rip = fpu->last_ip;
3923 fxsave->rdp = fpu->last_dp;
3924 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
3925
3926 vcpu_put(vcpu);
3927
3928 return 0;
3929}
3930
3931void fx_init(struct kvm_vcpu *vcpu)
3932{
3933 unsigned after_mxcsr_mask;
3934
bc1a34f1
AA		 3935 /*
3936 * Touch the fpu the first time in non atomic context as if
3937 * this is the first fpu instruction the exception handler
3938 * will fire before the instruction returns and it'll have to
3939 * allocate ram with GFP_KERNEL.
3940 */
3941 if (!used_math())
d6e88aec 3942 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 3943
d0752060
HB		 3944 /* Initialize guest FPU by resetting ours and saving into guest's */
3945 preempt_disable();
d6e88aec
AK		 3946 kvm_fx_save(&vcpu->arch.host_fx_image);
3947 kvm_fx_finit();
3948 kvm_fx_save(&vcpu->arch.guest_fx_image);
3949 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 3950 preempt_enable();
3951
ad312c7c 3952 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 3953 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 3954 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
3955 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 3956 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
3957}
3958EXPORT_SYMBOL_GPL(fx_init);
3959
3960void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
3961{
3962 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
3963 return;
3964
3965 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 3966 kvm_fx_save(&vcpu->arch.host_fx_image);
3967 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 3968}
3969EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
3970
3971void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
3972{
3973 if (!vcpu->guest_fpu_loaded)
3974 return;
3975
3976 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 3977 kvm_fx_save(&vcpu->arch.guest_fx_image);
3978 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 3979 ++vcpu->stat.fpu_reload;
d0752060
HB		 3980}
3981EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 3982
3983void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
3984{
3985 kvm_x86_ops->vcpu_free(vcpu);
3986}
3987
3988struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
3989 unsigned int id)
3990{
26e5215f
AK		 3991 return kvm_x86_ops->vcpu_create(kvm, id);
3992}
e9b11c17 3993
26e5215f
AK		 3994int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
3995{
3996 int r;
e9b11c17
ZX		 3997
3998 /* We do fxsave: this must be aligned. */
ad312c7c 3999 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 4000
0bed3b56 4001 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 4002 vcpu_load(vcpu);
4003 r = kvm_arch_vcpu_reset(vcpu);
4004 if (r == 0)
4005 r = kvm_mmu_setup(vcpu);
4006 vcpu_put(vcpu);
4007 if (r < 0)
4008 goto free_vcpu;
4009
26e5215f 4010 return 0;
e9b11c17
ZX		 4011free_vcpu:
4012 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 4013 return r;
e9b11c17
ZX		 4014}
4015
d40ccc62 4016void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 4017{
4018 vcpu_load(vcpu);
4019 kvm_mmu_unload(vcpu);
4020 vcpu_put(vcpu);
4021
4022 kvm_x86_ops->vcpu_free(vcpu);
4023}
4024
4025int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4026{
448fa4a9
JK		 4027 vcpu->arch.nmi_pending = false;
4028 vcpu->arch.nmi_injected = false;
4029
e9b11c17
ZX		 4030 return kvm_x86_ops->vcpu_reset(vcpu);
4031}
4032
4033void kvm_arch_hardware_enable(void *garbage)
4034{
4035 kvm_x86_ops->hardware_enable(garbage);
4036}
4037
4038void kvm_arch_hardware_disable(void *garbage)
4039{
4040 kvm_x86_ops->hardware_disable(garbage);
4041}
4042
4043int kvm_arch_hardware_setup(void)
4044{
4045 return kvm_x86_ops->hardware_setup();
4046}
4047
4048void kvm_arch_hardware_unsetup(void)
4049{
4050 kvm_x86_ops->hardware_unsetup();
4051}
4052
4053void kvm_arch_check_processor_compat(void *rtn)
4054{
4055 kvm_x86_ops->check_processor_compatibility(rtn);
4056}
4057
4058int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
4059{
4060 struct page *page;
4061 struct kvm *kvm;
4062 int r;
4063
4064 BUG_ON(vcpu->kvm == NULL);
4065 kvm = vcpu->kvm;
4066
ad312c7c 4067 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
e9b11c17 4068 if (!irqchip_in_kernel(kvm) || vcpu->vcpu_id == 0)
a4535290 4069 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 4070 else
a4535290 4071 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 4072
4073 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
4074 if (!page) {
4075 r = -ENOMEM;
4076 goto fail;
4077 }
ad312c7c 4078 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 4079
4080 r = kvm_mmu_create(vcpu);
4081 if (r < 0)
4082 goto fail_free_pio_data;
4083
4084 if (irqchip_in_kernel(kvm)) {
4085 r = kvm_create_lapic(vcpu);
4086 if (r < 0)
4087 goto fail_mmu_destroy;
4088 }
4089
4090 return 0;
4091
4092fail_mmu_destroy:
4093 kvm_mmu_destroy(vcpu);
4094fail_free_pio_data:
ad312c7c 4095 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 4096fail:
4097 return r;
4098}
4099
4100void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
4101{
4102 kvm_free_lapic(vcpu);
3200f405 4103 down_read(&vcpu->kvm->slots_lock);
e9b11c17 4104 kvm_mmu_destroy(vcpu);
3200f405 4105 up_read(&vcpu->kvm->slots_lock);
ad312c7c 4106 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 4107}
d19a9cd2
ZX		 4108
4109struct kvm *kvm_arch_create_vm(void)
4110{
4111 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
4112
4113 if (!kvm)
4114 return ERR_PTR(-ENOMEM);
4115
f05e70ac 4116 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 4117 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 4118
5550af4d
SY		 4119 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
4120 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
4121
d19a9cd2
ZX		 4122 return kvm;
4123}
4124
4125static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
4126{
4127 vcpu_load(vcpu);
4128 kvm_mmu_unload(vcpu);
4129 vcpu_put(vcpu);
4130}
4131
4132static void kvm_free_vcpus(struct kvm *kvm)
4133{
4134 unsigned int i;
4135
4136 /*
4137 * Unpin any mmu pages first.
4138 */
4139 for (i = 0; i < KVM_MAX_VCPUS; ++i)
4140 if (kvm->vcpus[i])
4141 kvm_unload_vcpu_mmu(kvm->vcpus[i]);
4142 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
4143 if (kvm->vcpus[i]) {
4144 kvm_arch_vcpu_free(kvm->vcpus[i]);
4145 kvm->vcpus[i] = NULL;
4146 }
4147 }
4148
4149}
4150
4151void kvm_arch_destroy_vm(struct kvm *kvm)
4152{
62c476c7 4153 kvm_iommu_unmap_guest(kvm);
bfadaded 4154 kvm_free_all_assigned_devices(kvm);
7837699f 4155 kvm_free_pit(kvm);
d7deeeb0
ZX		 4156 kfree(kvm->arch.vpic);
4157 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 4158 kvm_free_vcpus(kvm);
4159 kvm_free_physmem(kvm);
3d45830c
AK		 4160 if (kvm->arch.apic_access_page)
4161 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 4162 if (kvm->arch.ept_identity_pagetable)
4163 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 4164 kfree(kvm);
4165}
0de10343
ZX		 4166
4167int kvm_arch_set_memory_region(struct kvm *kvm,
4168 struct kvm_userspace_memory_region *mem,
4169 struct kvm_memory_slot old,
4170 int user_alloc)
4171{
4172 int npages = mem->memory_size >> PAGE_SHIFT;
4173 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
4174
4175 /*To keep backward compatibility with older userspace,
4176 *x86 needs to hanlde !user_alloc case.
4177 */
4178 if (!user_alloc) {
4179 if (npages && !old.rmap) {
604b38ac
AA		 4180 unsigned long userspace_addr;
4181
72dc67a6 4182 down_write(&current->mm->mmap_sem);
604b38ac
AA		 4183 userspace_addr = do_mmap(NULL, 0,
4184 npages * PAGE_SIZE,
4185 PROT_READ | PROT_WRITE,
acee3c04 4186 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 4187 0);
72dc67a6 4188 up_write(&current->mm->mmap_sem);
0de10343 4189
604b38ac
AA		 4190 if (IS_ERR((void *)userspace_addr))
4191 return PTR_ERR((void *)userspace_addr);
4192
4193 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4194 spin_lock(&kvm->mmu_lock);
4195 memslot->userspace_addr = userspace_addr;
4196 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4197 } else {
4198 if (!old.user_alloc && old.rmap) {
4199 int ret;
4200
72dc67a6 4201 down_write(&current->mm->mmap_sem);
0de10343
ZX		 4202 ret = do_munmap(current->mm, old.userspace_addr,
4203 old.npages * PAGE_SIZE);
72dc67a6 4204 up_write(&current->mm->mmap_sem);
0de10343
ZX		 4205 if (ret < 0)
4206 printk(KERN_WARNING
4207 "kvm_vm_ioctl_set_memory_region: "
4208 "failed to munmap memory\n");
4209 }
4210 }
4211 }
4212
f05e70ac 4213 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 4214 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4215 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4216 }
4217
4218 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
4219 kvm_flush_remote_tlbs(kvm);
4220
4221 return 0;
4222}
1d737c8a 4223
34d4cb8f
MT		 4224void kvm_arch_flush_shadow(struct kvm *kvm)
4225{
4226 kvm_mmu_zap_all(kvm);
4227}
4228
1d737c8a
ZX		 4229int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4230{
a4535290 4231 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
0496fbb9
JK		 4232 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
4233 || vcpu->arch.nmi_pending;
1d737c8a 4234}
5736199a
ZX		 4235
4236static void vcpu_kick_intr(void *info)
4237{
4238#ifdef DEBUG
4239 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)info;
4240 printk(KERN_DEBUG "vcpu_kick_intr %p \n", vcpu);
4241#endif
4242}
4243
4244void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4245{
4246 int ipi_pcpu = vcpu->cpu;
e9571ed5 4247 int cpu = get_cpu();
5736199a
ZX		 4248
4249 if (waitqueue_active(&vcpu->wq)) {
4250 wake_up_interruptible(&vcpu->wq);
4251 ++vcpu->stat.halt_wakeup;
4252 }
e9571ed5
MT		 4253 /*
4254 * We may be called synchronously with irqs disabled in guest mode,
4255 * So need not to call smp_call_function_single() in that case.
4256 */
4257 if (vcpu->guest_mode && vcpu->cpu != cpu)
8691e5a8 4258 smp_call_function_single(ipi_pcpu, vcpu_kick_intr, vcpu, 0);
e9571ed5 4259 put_cpu();
5736199a 4260}
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