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KVM: x86: Fix potential preemption when get the current kvmclock timestamp
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad
IM		 56#include <linux/sched/stat.h>
57
aec51dc4 58#include <trace/events/kvm.h>
2ed152af 59
24f1e32c 60#include <asm/debugreg.h>
d825ed0a 61#include <asm/msr.h>
a5f61300 62#include <asm/desc.h>
890ca9ae 63#include <asm/mce.h>
f89e32e0 64#include <linux/kernel_stat.h>
78f7f1e5 65#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 66#include <asm/pvclock.h>
217fc9cf 67#include <asm/div64.h>
efc64404 68#include <asm/irq_remapping.h>
043405e1 69
d1898b73
DH		 70#define CREATE_TRACE_POINTS
71#include "trace.h"
72
313a3dc7 73#define MAX_IO_MSRS 256
890ca9ae 74#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 75u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
76EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 77
0f65dd70
AK		 78#define emul_to_vcpu(ctxt) \
79 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
80
50a37eb4
JR		 81/* EFER defaults:
82 * - enable syscall per default because its emulated by KVM
83 * - enable LME and LMA per default on 64 bit KVM
84 */
85#ifdef CONFIG_X86_64
1260edbe
LJ		 86static
87u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 88#else
1260edbe 89static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 90#endif
313a3dc7 91
ba1389b7
AK		 92#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
93#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 94
c519265f
RK		 95#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
96 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 97
cb142eb7 98static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 99static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 100static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 101static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 102
893590c7 103struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 104EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 105
893590c7 106static bool __read_mostly ignore_msrs = 0;
476bc001 107module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 108
9ed96e87
MT		 109unsigned int min_timer_period_us = 500;
110module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
111
630994b3
MT		 112static bool __read_mostly kvmclock_periodic_sync = true;
113module_param(kvmclock_periodic_sync, bool, S_IRUGO);
114
893590c7 115bool __read_mostly kvm_has_tsc_control;
92a1f12d 116EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 117u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 118EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 119u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
120EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
121u64 __read_mostly kvm_max_tsc_scaling_ratio;
122EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 123u64 __read_mostly kvm_default_tsc_scaling_ratio;
124EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 125
cc578287 126/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 127static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 128module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
129
d0659d94 130/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 131unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 132module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
133
52004014
FW		 134static bool __read_mostly vector_hashing = true;
135module_param(vector_hashing, bool, S_IRUGO);
136
893590c7 137static bool __read_mostly backwards_tsc_observed = false;
16a96021 138
18863bdd
AK		 139#define KVM_NR_SHARED_MSRS 16
140
141struct kvm_shared_msrs_global {
142 int nr;
2bf78fa7 143 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 144};
145
146struct kvm_shared_msrs {
147 struct user_return_notifier urn;
148 bool registered;
2bf78fa7
SY		 149 struct kvm_shared_msr_values {
150 u64 host;
151 u64 curr;
152 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 153};
154
155static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 156static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 157
417bc304 158struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 159 { "pf_fixed", VCPU_STAT(pf_fixed) },
160 { "pf_guest", VCPU_STAT(pf_guest) },
161 { "tlb_flush", VCPU_STAT(tlb_flush) },
162 { "invlpg", VCPU_STAT(invlpg) },
163 { "exits", VCPU_STAT(exits) },
164 { "io_exits", VCPU_STAT(io_exits) },
165 { "mmio_exits", VCPU_STAT(mmio_exits) },
166 { "signal_exits", VCPU_STAT(signal_exits) },
167 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 168 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 169 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 170 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 171 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 172 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 173 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 174 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 175 { "request_irq", VCPU_STAT(request_irq_exits) },
176 { "irq_exits", VCPU_STAT(irq_exits) },
177 { "host_state_reload", VCPU_STAT(host_state_reload) },
178 { "efer_reload", VCPU_STAT(efer_reload) },
179 { "fpu_reload", VCPU_STAT(fpu_reload) },
180 { "insn_emulation", VCPU_STAT(insn_emulation) },
181 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 182 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 183 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 184 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 185 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
186 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
187 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
188 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
189 { "mmu_flooded", VM_STAT(mmu_flooded) },
190 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 191 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 192 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 193 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 194 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 195 { "max_mmu_page_hash_collisions",
196 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 197 { NULL }
198};
199
2acf923e
DC		 200u64 __read_mostly host_xcr0;
201
b6785def 202static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 203
af585b92
GN		 204static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
205{
206 int i;
207 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
208 vcpu->arch.apf.gfns[i] = ~0;
209}
210
18863bdd
AK		 211static void kvm_on_user_return(struct user_return_notifier *urn)
212{
213 unsigned slot;
18863bdd
AK		 214 struct kvm_shared_msrs *locals
215 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 216 struct kvm_shared_msr_values *values;
1650b4eb
IA		 217 unsigned long flags;
218
219 /*
220 * Disabling irqs at this point since the following code could be
221 * interrupted and executed through kvm_arch_hardware_disable()
222 */
223 local_irq_save(flags);
224 if (locals->registered) {
225 locals->registered = false;
226 user_return_notifier_unregister(urn);
227 }
228 local_irq_restore(flags);
18863bdd 229 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 230 values = &locals->values[slot];
231 if (values->host != values->curr) {
232 wrmsrl(shared_msrs_global.msrs[slot], values->host);
233 values->curr = values->host;
18863bdd
AK		 234 }
235 }
18863bdd
AK		 236}
237
2bf78fa7 238static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 239{
18863bdd 240 u64 value;
013f6a5d
MT		 241 unsigned int cpu = smp_processor_id();
242 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 243
2bf78fa7
SY		 244 /* only read, and nobody should modify it at this time,
245 * so don't need lock */
246 if (slot >= shared_msrs_global.nr) {
247 printk(KERN_ERR "kvm: invalid MSR slot!");
248 return;
249 }
250 rdmsrl_safe(msr, &value);
251 smsr->values[slot].host = value;
252 smsr->values[slot].curr = value;
253}
254
255void kvm_define_shared_msr(unsigned slot, u32 msr)
256{
0123be42 257 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 258 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 259 if (slot >= shared_msrs_global.nr)
260 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 261}
262EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
263
264static void kvm_shared_msr_cpu_online(void)
265{
266 unsigned i;
18863bdd
AK		 267
268 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 269 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 270}
271
8b3c3104 272int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 273{
013f6a5d
MT		 274 unsigned int cpu = smp_processor_id();
275 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 276 int err;
18863bdd 277
2bf78fa7 278 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 279 return 0;
2bf78fa7 280 smsr->values[slot].curr = value;
8b3c3104
AH		 281 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
282 if (err)
283 return 1;
284
18863bdd
AK		 285 if (!smsr->registered) {
286 smsr->urn.on_user_return = kvm_on_user_return;
287 user_return_notifier_register(&smsr->urn);
288 smsr->registered = true;
289 }
8b3c3104 290 return 0;
18863bdd
AK		 291}
292EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
293
13a34e06 294static void drop_user_return_notifiers(void)
3548bab5 295{
013f6a5d
MT		 296 unsigned int cpu = smp_processor_id();
297 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 298
299 if (smsr->registered)
300 kvm_on_user_return(&smsr->urn);
301}
302
6866b83e
CO		 303u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
304{
8a5a87d9 305 return vcpu->arch.apic_base;
6866b83e
CO		 306}
307EXPORT_SYMBOL_GPL(kvm_get_apic_base);
308
58cb628d
JK		 309int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
310{
311 u64 old_state = vcpu->arch.apic_base &
312 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
313 u64 new_state = msr_info->data &
314 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
315 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
316 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
317
318 if (!msr_info->host_initiated &&
319 ((msr_info->data & reserved_bits) != 0 ||
320 new_state == X2APIC_ENABLE ||
321 (new_state == MSR_IA32_APICBASE_ENABLE &&
322 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
323 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
324 old_state == 0)))
325 return 1;
326
327 kvm_lapic_set_base(vcpu, msr_info->data);
328 return 0;
6866b83e
CO		 329}
330EXPORT_SYMBOL_GPL(kvm_set_apic_base);
331
2605fc21 332asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 333{
334 /* Fault while not rebooting. We want the trace. */
335 BUG();
336}
337EXPORT_SYMBOL_GPL(kvm_spurious_fault);
338
3fd28fce
ED		 339#define EXCPT_BENIGN 0
340#define EXCPT_CONTRIBUTORY 1
341#define EXCPT_PF 2
342
343static int exception_class(int vector)
344{
345 switch (vector) {
346 case PF_VECTOR:
347 return EXCPT_PF;
348 case DE_VECTOR:
349 case TS_VECTOR:
350 case NP_VECTOR:
351 case SS_VECTOR:
352 case GP_VECTOR:
353 return EXCPT_CONTRIBUTORY;
354 default:
355 break;
356 }
357 return EXCPT_BENIGN;
358}
359
d6e8c854
NA		 360#define EXCPT_FAULT 0
361#define EXCPT_TRAP 1
362#define EXCPT_ABORT 2
363#define EXCPT_INTERRUPT 3
364
365static int exception_type(int vector)
366{
367 unsigned int mask;
368
369 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
370 return EXCPT_INTERRUPT;
371
372 mask = 1 << vector;
373
374 /* #DB is trap, as instruction watchpoints are handled elsewhere */
375 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
376 return EXCPT_TRAP;
377
378 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
379 return EXCPT_ABORT;
380
381 /* Reserved exceptions will result in fault */
382 return EXCPT_FAULT;
383}
384
3fd28fce 385static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 386 unsigned nr, bool has_error, u32 error_code,
387 bool reinject)
3fd28fce
ED		 388{
389 u32 prev_nr;
390 int class1, class2;
391
3842d135
AK		 392 kvm_make_request(KVM_REQ_EVENT, vcpu);
393
3fd28fce
ED		 394 if (!vcpu->arch.exception.pending) {
395 queue:
3ffb2468
NA		 396 if (has_error && !is_protmode(vcpu))
397 has_error = false;
3fd28fce
ED		 398 vcpu->arch.exception.pending = true;
399 vcpu->arch.exception.has_error_code = has_error;
400 vcpu->arch.exception.nr = nr;
401 vcpu->arch.exception.error_code = error_code;
3f0fd292 402 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 403 return;
404 }
405
406 /* to check exception */
407 prev_nr = vcpu->arch.exception.nr;
408 if (prev_nr == DF_VECTOR) {
409 /* triple fault -> shutdown */
a8eeb04a 410 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 411 return;
412 }
413 class1 = exception_class(prev_nr);
414 class2 = exception_class(nr);
415 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
416 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
417 /* generate double fault per SDM Table 5-5 */
418 vcpu->arch.exception.pending = true;
419 vcpu->arch.exception.has_error_code = true;
420 vcpu->arch.exception.nr = DF_VECTOR;
421 vcpu->arch.exception.error_code = 0;
422 } else
423 /* replace previous exception with a new one in a hope
424 that instruction re-execution will regenerate lost
425 exception */
426 goto queue;
427}
428
298101da
AK		 429void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
430{
ce7ddec4 431 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 432}
433EXPORT_SYMBOL_GPL(kvm_queue_exception);
434
ce7ddec4
JR		 435void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
436{
437 kvm_multiple_exception(vcpu, nr, false, 0, true);
438}
439EXPORT_SYMBOL_GPL(kvm_requeue_exception);
440
6affcbed 441int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 442{
db8fcefa
AP		 443 if (err)
444 kvm_inject_gp(vcpu, 0);
445 else
6affcbed
KH		 446 return kvm_skip_emulated_instruction(vcpu);
447
448 return 1;
db8fcefa
AP		 449}
450EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 451
6389ee94 452void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 453{
454 ++vcpu->stat.pf_guest;
6389ee94
AK		 455 vcpu->arch.cr2 = fault->address;
456 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 457}
27d6c865 458EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 459
ef54bcfe 460static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 461{
6389ee94
AK		 462 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
463 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 464 else
6389ee94 465 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 466
467 return fault->nested_page_fault;
d4f8cf66
JR		 468}
469
3419ffc8
SY		 470void kvm_inject_nmi(struct kvm_vcpu *vcpu)
471{
7460fb4a
AK		 472 atomic_inc(&vcpu->arch.nmi_queued);
473 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 474}
475EXPORT_SYMBOL_GPL(kvm_inject_nmi);
476
298101da
AK		 477void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
478{
ce7ddec4 479 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 480}
481EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
482
ce7ddec4
JR		 483void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
484{
485 kvm_multiple_exception(vcpu, nr, true, error_code, true);
486}
487EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
488
0a79b009
AK		 489/*
490 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
491 * a #GP and return false.
492 */
493bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 494{
0a79b009
AK		 495 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
496 return true;
497 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
498 return false;
298101da 499}
0a79b009 500EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 501
16f8a6f9
NA		 502bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
503{
504 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
505 return true;
506
507 kvm_queue_exception(vcpu, UD_VECTOR);
508 return false;
509}
510EXPORT_SYMBOL_GPL(kvm_require_dr);
511
ec92fe44
JR		 512/*
513 * This function will be used to read from the physical memory of the currently
54bf36aa 514 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 515 * can read from guest physical or from the guest's guest physical memory.
516 */
517int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
518 gfn_t ngfn, void *data, int offset, int len,
519 u32 access)
520{
54987b7a 521 struct x86_exception exception;
ec92fe44
JR		 522 gfn_t real_gfn;
523 gpa_t ngpa;
524
525 ngpa = gfn_to_gpa(ngfn);
54987b7a 526 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 527 if (real_gfn == UNMAPPED_GVA)
528 return -EFAULT;
529
530 real_gfn = gpa_to_gfn(real_gfn);
531
54bf36aa 532 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 533}
534EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
535
69b0049a 536static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 537 void *data, int offset, int len, u32 access)
538{
539 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
540 data, offset, len, access);
541}
542
a03490ed
CO		 543/*
544 * Load the pae pdptrs. Return true is they are all valid.
545 */
ff03a073 546int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 547{
548 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
549 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
550 int i;
551 int ret;
ff03a073 552 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 553
ff03a073
JR		 554 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
555 offset * sizeof(u64), sizeof(pdpte),
556 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 557 if (ret < 0) {
558 ret = 0;
559 goto out;
560 }
561 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 562 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 563 (pdpte[i] &
564 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 565 ret = 0;
566 goto out;
567 }
568 }
569 ret = 1;
570
ff03a073 571 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 572 __set_bit(VCPU_EXREG_PDPTR,
573 (unsigned long *)&vcpu->arch.regs_avail);
574 __set_bit(VCPU_EXREG_PDPTR,
575 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 576out:
a03490ed
CO		 577
578 return ret;
579}
cc4b6871 580EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 581
9ed38ffa 582bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 583{
ff03a073 584 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 585 bool changed = true;
3d06b8bf
JR		 586 int offset;
587 gfn_t gfn;
d835dfec
AK		 588 int r;
589
590 if (is_long_mode(vcpu) || !is_pae(vcpu))
591 return false;
592
6de4f3ad
AK		 593 if (!test_bit(VCPU_EXREG_PDPTR,
594 (unsigned long *)&vcpu->arch.regs_avail))
595 return true;
596
9f8fe504
AK		 597 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
598 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 599 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
600 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 601 if (r < 0)
602 goto out;
ff03a073 603 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 604out:
d835dfec
AK		 605
606 return changed;
607}
9ed38ffa 608EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 609
49a9b07e 610int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 611{
aad82703 612 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 613 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 614
f9a48e6a
AK		 615 cr0 |= X86_CR0_ET;
616
ab344828 617#ifdef CONFIG_X86_64
0f12244f
GN		 618 if (cr0 & 0xffffffff00000000UL)
619 return 1;
ab344828
GN		 620#endif
621
622 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 623
0f12244f
GN		 624 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
625 return 1;
a03490ed 626
0f12244f
GN		 627 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
628 return 1;
a03490ed
CO		 629
630 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
631#ifdef CONFIG_X86_64
f6801dff 632 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 633 int cs_db, cs_l;
634
0f12244f
GN		 635 if (!is_pae(vcpu))
636 return 1;
a03490ed 637 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 638 if (cs_l)
639 return 1;
a03490ed
CO		 640 } else
641#endif
ff03a073 642 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 643 kvm_read_cr3(vcpu)))
0f12244f 644 return 1;
a03490ed
CO		 645 }
646
ad756a16
MJ		 647 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
648 return 1;
649
a03490ed 650 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 651
d170c419 652 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 653 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 654 kvm_async_pf_hash_reset(vcpu);
655 }
e5f3f027 656
aad82703
SY		 657 if ((cr0 ^ old_cr0) & update_bits)
658 kvm_mmu_reset_context(vcpu);
b18d5431 659
879ae188
LE		 660 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
661 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
662 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 663 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
664
0f12244f
GN		 665 return 0;
666}
2d3ad1f4 667EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 668
2d3ad1f4 669void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 670{
49a9b07e 671 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 672}
2d3ad1f4 673EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 674
42bdf991
MT		 675static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
676{
677 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
678 !vcpu->guest_xcr0_loaded) {
679 /* kvm_set_xcr() also depends on this */
680 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
681 vcpu->guest_xcr0_loaded = 1;
682 }
683}
684
685static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
686{
687 if (vcpu->guest_xcr0_loaded) {
688 if (vcpu->arch.xcr0 != host_xcr0)
689 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
690 vcpu->guest_xcr0_loaded = 0;
691 }
692}
693
69b0049a 694static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 695{
56c103ec
LJ		 696 u64 xcr0 = xcr;
697 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 698 u64 valid_bits;
2acf923e
DC		 699
700 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
701 if (index != XCR_XFEATURE_ENABLED_MASK)
702 return 1;
d91cab78 703 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 704 return 1;
d91cab78 705 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 706 return 1;
46c34cb0
PB		 707
708 /*
709 * Do not allow the guest to set bits that we do not support
710 * saving. However, xcr0 bit 0 is always set, even if the
711 * emulated CPU does not support XSAVE (see fx_init).
712 */
d91cab78 713 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 714 if (xcr0 & ~valid_bits)
2acf923e 715 return 1;
46c34cb0 716
d91cab78
DH		 717 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
718 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 719 return 1;
720
d91cab78
DH		 721 if (xcr0 & XFEATURE_MASK_AVX512) {
722 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 723 return 1;
d91cab78 724 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 725 return 1;
726 }
2acf923e 727 vcpu->arch.xcr0 = xcr0;
56c103ec 728
d91cab78 729 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 730 kvm_update_cpuid(vcpu);
2acf923e
DC		 731 return 0;
732}
733
734int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
735{
764bcbc5
Z		 736 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
737 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 738 kvm_inject_gp(vcpu, 0);
739 return 1;
740 }
741 return 0;
742}
743EXPORT_SYMBOL_GPL(kvm_set_xcr);
744
a83b29c6 745int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 746{
fc78f519 747 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 748 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 749 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 750
0f12244f
GN		 751 if (cr4 & CR4_RESERVED_BITS)
752 return 1;
a03490ed 753
2acf923e
DC		 754 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
755 return 1;
756
c68b734f
YW		 757 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
758 return 1;
759
97ec8c06
FW		 760 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
761 return 1;
762
afcbf13f 763 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 764 return 1;
765
b9baba86
HH		 766 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
767 return 1;
768
a03490ed 769 if (is_long_mode(vcpu)) {
0f12244f
GN		 770 if (!(cr4 & X86_CR4_PAE))
771 return 1;
a2edf57f
AK		 772 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
773 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 774 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
775 kvm_read_cr3(vcpu)))
0f12244f
GN		 776 return 1;
777
ad756a16
MJ		 778 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
779 if (!guest_cpuid_has_pcid(vcpu))
780 return 1;
781
782 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
783 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
784 return 1;
785 }
786
5e1746d6 787 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 788 return 1;
a03490ed 789
ad756a16
MJ		 790 if (((cr4 ^ old_cr4) & pdptr_bits) ||
791 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 792 kvm_mmu_reset_context(vcpu);
0f12244f 793
b9baba86 794 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 795 kvm_update_cpuid(vcpu);
2acf923e 796
0f12244f
GN		 797 return 0;
798}
2d3ad1f4 799EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 800
2390218b 801int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 802{
ac146235 803#ifdef CONFIG_X86_64
9d88fca7 804 cr3 &= ~CR3_PCID_INVD;
ac146235 805#endif
9d88fca7 806
9f8fe504 807 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 808 kvm_mmu_sync_roots(vcpu);
77c3913b 809 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 810 return 0;
d835dfec
AK		 811 }
812
a03490ed 813 if (is_long_mode(vcpu)) {
d9f89b88
JK		 814 if (cr3 & CR3_L_MODE_RESERVED_BITS)
815 return 1;
816 } else if (is_pae(vcpu) && is_paging(vcpu) &&
817 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 818 return 1;
a03490ed 819
0f12244f 820 vcpu->arch.cr3 = cr3;
aff48baa 821 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 822 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 823 return 0;
824}
2d3ad1f4 825EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 826
eea1cff9 827int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 828{
0f12244f
GN		 829 if (cr8 & CR8_RESERVED_BITS)
830 return 1;
35754c98 831 if (lapic_in_kernel(vcpu))
a03490ed
CO		 832 kvm_lapic_set_tpr(vcpu, cr8);
833 else
ad312c7c 834 vcpu->arch.cr8 = cr8;
0f12244f
GN		 835 return 0;
836}
2d3ad1f4 837EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 838
2d3ad1f4 839unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 840{
35754c98 841 if (lapic_in_kernel(vcpu))
a03490ed
CO		 842 return kvm_lapic_get_cr8(vcpu);
843 else
ad312c7c 844 return vcpu->arch.cr8;
a03490ed 845}
2d3ad1f4 846EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 847
ae561ede
NA		 848static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
849{
850 int i;
851
852 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
853 for (i = 0; i < KVM_NR_DB_REGS; i++)
854 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
855 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
856 }
857}
858
73aaf249
JK		 859static void kvm_update_dr6(struct kvm_vcpu *vcpu)
860{
861 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
862 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
863}
864
c8639010
JK		 865static void kvm_update_dr7(struct kvm_vcpu *vcpu)
866{
867 unsigned long dr7;
868
869 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
870 dr7 = vcpu->arch.guest_debug_dr7;
871 else
872 dr7 = vcpu->arch.dr7;
873 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 874 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
875 if (dr7 & DR7_BP_EN_MASK)
876 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 877}
878
6f43ed01
NA		 879static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
880{
881 u64 fixed = DR6_FIXED_1;
882
883 if (!guest_cpuid_has_rtm(vcpu))
884 fixed |= DR6_RTM;
885 return fixed;
886}
887
338dbc97 888static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 889{
890 switch (dr) {
891 case 0 ... 3:
892 vcpu->arch.db[dr] = val;
893 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
894 vcpu->arch.eff_db[dr] = val;
895 break;
896 case 4:
020df079
GN		 897 /* fall through */
898 case 6:
338dbc97
GN		 899 if (val & 0xffffffff00000000ULL)
900 return -1; /* #GP */
6f43ed01 901 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 902 kvm_update_dr6(vcpu);
020df079
GN		 903 break;
904 case 5:
020df079
GN		 905 /* fall through */
906 default: /* 7 */
338dbc97
GN		 907 if (val & 0xffffffff00000000ULL)
908 return -1; /* #GP */
020df079 909 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 910 kvm_update_dr7(vcpu);
020df079
GN		 911 break;
912 }
913
914 return 0;
915}
338dbc97
GN		 916
917int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
918{
16f8a6f9 919 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 920 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 921 return 1;
922 }
923 return 0;
338dbc97 924}
020df079
GN		 925EXPORT_SYMBOL_GPL(kvm_set_dr);
926
16f8a6f9 927int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 928{
929 switch (dr) {
930 case 0 ... 3:
931 *val = vcpu->arch.db[dr];
932 break;
933 case 4:
020df079
GN		 934 /* fall through */
935 case 6:
73aaf249
JK		 936 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
937 *val = vcpu->arch.dr6;
938 else
939 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 940 break;
941 case 5:
020df079
GN		 942 /* fall through */
943 default: /* 7 */
944 *val = vcpu->arch.dr7;
945 break;
946 }
338dbc97
GN		 947 return 0;
948}
020df079
GN		 949EXPORT_SYMBOL_GPL(kvm_get_dr);
950
022cd0e8
AK		 951bool kvm_rdpmc(struct kvm_vcpu *vcpu)
952{
953 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
954 u64 data;
955 int err;
956
c6702c9d 957 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 958 if (err)
959 return err;
960 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
961 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
962 return err;
963}
964EXPORT_SYMBOL_GPL(kvm_rdpmc);
965
043405e1
CO		 966/*
967 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
968 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
969 *
970 * This list is modified at module load time to reflect the
e3267cbb 971 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 972 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
973 * may depend on host virtualization features rather than host cpu features.
043405e1 974 */
e3267cbb 975
043405e1
CO		 976static u32 msrs_to_save[] = {
977 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 978 MSR_STAR,
043405e1
CO		 979#ifdef CONFIG_X86_64
980 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
981#endif
b3897a49 982 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 983 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 984};
985
986static unsigned num_msrs_to_save;
987
62ef68bb
PB		 988static u32 emulated_msrs[] = {
989 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
990 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
991 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
992 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 993 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
994 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 995 HV_X64_MSR_RESET,
11c4b1ca 996 HV_X64_MSR_VP_INDEX,
9eec50b8 997 HV_X64_MSR_VP_RUNTIME,
5c919412 998 HV_X64_MSR_SCONTROL,
1f4b34f8 999 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 1000 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1001 MSR_KVM_PV_EOI_EN,
1002
ba904635 1003 MSR_IA32_TSC_ADJUST,
a3e06bbe 1004 MSR_IA32_TSCDEADLINE,
043405e1 1005 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1006 MSR_IA32_MCG_STATUS,
1007 MSR_IA32_MCG_CTL,
c45dcc71 1008 MSR_IA32_MCG_EXT_CTL,
64d60670 1009 MSR_IA32_SMBASE,
db2336a8
KH		 1010 MSR_PLATFORM_INFO,
1011 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1012};
1013
62ef68bb
PB		 1014static unsigned num_emulated_msrs;
1015
384bb783 1016bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1017{
b69e8cae 1018 if (efer & efer_reserved_bits)
384bb783 1019 return false;
15c4a640 1020
1b2fd70c
AG		 1021 if (efer & EFER_FFXSR) {
1022 struct kvm_cpuid_entry2 *feat;
1023
1024 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1025 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 1026 return false;
1b2fd70c
AG		 1027 }
1028
d8017474
AG		 1029 if (efer & EFER_SVME) {
1030 struct kvm_cpuid_entry2 *feat;
1031
1032 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1033 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1034 return false;
d8017474
AG		 1035 }
1036
384bb783
JK		 1037 return true;
1038}
1039EXPORT_SYMBOL_GPL(kvm_valid_efer);
1040
1041static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1042{
1043 u64 old_efer = vcpu->arch.efer;
1044
1045 if (!kvm_valid_efer(vcpu, efer))
1046 return 1;
1047
1048 if (is_paging(vcpu)
1049 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1050 return 1;
1051
15c4a640 1052 efer &= ~EFER_LMA;
f6801dff 1053 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1054
a3d204e2
SY		 1055 kvm_x86_ops->set_efer(vcpu, efer);
1056
aad82703
SY		 1057 /* Update reserved bits */
1058 if ((efer ^ old_efer) & EFER_NX)
1059 kvm_mmu_reset_context(vcpu);
1060
b69e8cae 1061 return 0;
15c4a640
CO		 1062}
1063
f2b4b7dd
JR		 1064void kvm_enable_efer_bits(u64 mask)
1065{
1066 efer_reserved_bits &= ~mask;
1067}
1068EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1069
15c4a640
CO		 1070/*
1071 * Writes msr value into into the appropriate "register".
1072 * Returns 0 on success, non-0 otherwise.
1073 * Assumes vcpu_load() was already called.
1074 */
8fe8ab46 1075int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1076{
854e8bb1
NA		 1077 switch (msr->index) {
1078 case MSR_FS_BASE:
1079 case MSR_GS_BASE:
1080 case MSR_KERNEL_GS_BASE:
1081 case MSR_CSTAR:
1082 case MSR_LSTAR:
1083 if (is_noncanonical_address(msr->data))
1084 return 1;
1085 break;
1086 case MSR_IA32_SYSENTER_EIP:
1087 case MSR_IA32_SYSENTER_ESP:
1088 /*
1089 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1090 * non-canonical address is written on Intel but not on
1091 * AMD (which ignores the top 32-bits, because it does
1092 * not implement 64-bit SYSENTER).
1093 *
1094 * 64-bit code should hence be able to write a non-canonical
1095 * value on AMD. Making the address canonical ensures that
1096 * vmentry does not fail on Intel after writing a non-canonical
1097 * value, and that something deterministic happens if the guest
1098 * invokes 64-bit SYSENTER.
1099 */
1100 msr->data = get_canonical(msr->data);
1101 }
8fe8ab46 1102 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1103}
854e8bb1 1104EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1105
313a3dc7
CO		 1106/*
1107 * Adapt set_msr() to msr_io()'s calling convention
1108 */
609e36d3
PB		 1109static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1110{
1111 struct msr_data msr;
1112 int r;
1113
1114 msr.index = index;
1115 msr.host_initiated = true;
1116 r = kvm_get_msr(vcpu, &msr);
1117 if (r)
1118 return r;
1119
1120 *data = msr.data;
1121 return 0;
1122}
1123
313a3dc7
CO		 1124static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1125{
8fe8ab46
WA		 1126 struct msr_data msr;
1127
1128 msr.data = *data;
1129 msr.index = index;
1130 msr.host_initiated = true;
1131 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1132}
1133
16e8d74d
MT		 1134#ifdef CONFIG_X86_64
1135struct pvclock_gtod_data {
1136 seqcount_t seq;
1137
1138 struct { /* extract of a clocksource struct */
1139 int vclock_mode;
a5a1d1c2
TG		 1140 u64 cycle_last;
1141 u64 mask;
16e8d74d
MT		 1142 u32 mult;
1143 u32 shift;
1144 } clock;
1145
cbcf2dd3
TG		 1146 u64 boot_ns;
1147 u64 nsec_base;
55dd00a7 1148 u64 wall_time_sec;
16e8d74d
MT		 1149};
1150
1151static struct pvclock_gtod_data pvclock_gtod_data;
1152
1153static void update_pvclock_gtod(struct timekeeper *tk)
1154{
1155 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1156 u64 boot_ns;
1157
876e7881 1158 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1159
1160 write_seqcount_begin(&vdata->seq);
1161
1162 /* copy pvclock gtod data */
876e7881
PZ		 1163 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1164 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1165 vdata->clock.mask = tk->tkr_mono.mask;
1166 vdata->clock.mult = tk->tkr_mono.mult;
1167 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1168
cbcf2dd3 1169 vdata->boot_ns = boot_ns;
876e7881 1170 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1171
55dd00a7
MT		 1172 vdata->wall_time_sec = tk->xtime_sec;
1173
16e8d74d
MT		 1174 write_seqcount_end(&vdata->seq);
1175}
1176#endif
1177
bab5bb39
NK		 1178void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1179{
1180 /*
1181 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1182 * vcpu_enter_guest. This function is only called from
1183 * the physical CPU that is running vcpu.
1184 */
1185 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1186}
16e8d74d 1187
18068523
GOC		 1188static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1189{
9ed3c444
AK		 1190 int version;
1191 int r;
50d0a0f9 1192 struct pvclock_wall_clock wc;
87aeb54f 1193 struct timespec64 boot;
18068523
GOC		 1194
1195 if (!wall_clock)
1196 return;
1197
9ed3c444
AK		 1198 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1199 if (r)
1200 return;
1201
1202 if (version & 1)
1203 ++version; /* first time write, random junk */
1204
1205 ++version;
18068523 1206
1dab1345
NK		 1207 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1208 return;
18068523 1209
50d0a0f9
GH		 1210 /*
1211 * The guest calculates current wall clock time by adding
34c238a1 1212 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1213 * wall clock specified here. guest system time equals host
1214 * system time for us, thus we must fill in host boot time here.
1215 */
87aeb54f 1216 getboottime64(&boot);
50d0a0f9 1217
4b648665 1218 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1219 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1220 boot = timespec64_sub(boot, ts);
4b648665 1221 }
87aeb54f 1222 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1223 wc.nsec = boot.tv_nsec;
1224 wc.version = version;
18068523
GOC		 1225
1226 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1227
1228 version++;
1229 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1230}
1231
50d0a0f9
GH		 1232static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1233{
b51012de
PB		 1234 do_shl32_div32(dividend, divisor);
1235 return dividend;
50d0a0f9
GH		 1236}
1237
3ae13faa 1238static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1239 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1240{
5f4e3f88 1241 uint64_t scaled64;
50d0a0f9
GH		 1242 int32_t shift = 0;
1243 uint64_t tps64;
1244 uint32_t tps32;
1245
3ae13faa
PB		 1246 tps64 = base_hz;
1247 scaled64 = scaled_hz;
50933623 1248 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1249 tps64 >>= 1;
1250 shift--;
1251 }
1252
1253 tps32 = (uint32_t)tps64;
50933623
JK		 1254 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1255 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1256 scaled64 >>= 1;
1257 else
1258 tps32 <<= 1;
50d0a0f9
GH		 1259 shift++;
1260 }
1261
5f4e3f88
ZA		 1262 *pshift = shift;
1263 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1264
3ae13faa
PB		 1265 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1266 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1267}
1268
d828199e 1269#ifdef CONFIG_X86_64
16e8d74d 1270static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1271#endif
16e8d74d 1272
c8076604 1273static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1274static unsigned long max_tsc_khz;
c8076604 1275
cc578287 1276static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1277{
cc578287
ZA		 1278 u64 v = (u64)khz * (1000000 + ppm);
1279 do_div(v, 1000000);
1280 return v;
1e993611
JR		 1281}
1282
381d585c
HZ		 1283static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1284{
1285 u64 ratio;
1286
1287 /* Guest TSC same frequency as host TSC? */
1288 if (!scale) {
1289 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1290 return 0;
1291 }
1292
1293 /* TSC scaling supported? */
1294 if (!kvm_has_tsc_control) {
1295 if (user_tsc_khz > tsc_khz) {
1296 vcpu->arch.tsc_catchup = 1;
1297 vcpu->arch.tsc_always_catchup = 1;
1298 return 0;
1299 } else {
1300 WARN(1, "user requested TSC rate below hardware speed\n");
1301 return -1;
1302 }
1303 }
1304
1305 /* TSC scaling required - calculate ratio */
1306 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1307 user_tsc_khz, tsc_khz);
1308
1309 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1310 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1311 user_tsc_khz);
1312 return -1;
1313 }
1314
1315 vcpu->arch.tsc_scaling_ratio = ratio;
1316 return 0;
1317}
1318
4941b8cb 1319static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1320{
cc578287
ZA		 1321 u32 thresh_lo, thresh_hi;
1322 int use_scaling = 0;
217fc9cf 1323
03ba32ca 1324 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1325 if (user_tsc_khz == 0) {
ad721883
HZ		 1326 /* set tsc_scaling_ratio to a safe value */
1327 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1328 return -1;
ad721883 1329 }
03ba32ca 1330
c285545f 1331 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1332 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1333 &vcpu->arch.virtual_tsc_shift,
1334 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1335 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1336
1337 /*
1338 * Compute the variation in TSC rate which is acceptable
1339 * within the range of tolerance and decide if the
1340 * rate being applied is within that bounds of the hardware
1341 * rate. If so, no scaling or compensation need be done.
1342 */
1343 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1344 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1345 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1346 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1347 use_scaling = 1;
1348 }
4941b8cb 1349 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1350}
1351
1352static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1353{
e26101b1 1354 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1355 vcpu->arch.virtual_tsc_mult,
1356 vcpu->arch.virtual_tsc_shift);
e26101b1 1357 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1358 return tsc;
1359}
1360
69b0049a 1361static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1362{
1363#ifdef CONFIG_X86_64
1364 bool vcpus_matched;
b48aa97e
MT		 1365 struct kvm_arch *ka = &vcpu->kvm->arch;
1366 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1367
1368 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1369 atomic_read(&vcpu->kvm->online_vcpus));
1370
7f187922
MT		 1371 /*
1372 * Once the masterclock is enabled, always perform request in
1373 * order to update it.
1374 *
1375 * In order to enable masterclock, the host clocksource must be TSC
1376 * and the vcpus need to have matched TSCs. When that happens,
1377 * perform request to enable masterclock.
1378 */
1379 if (ka->use_master_clock ||
1380 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1381 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1382
1383 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1384 atomic_read(&vcpu->kvm->online_vcpus),
1385 ka->use_master_clock, gtod->clock.vclock_mode);
1386#endif
1387}
1388
ba904635
WA		 1389static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1390{
3e3f5026 1391 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1392 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1393}
1394
35181e86
HZ		 1395/*
1396 * Multiply tsc by a fixed point number represented by ratio.
1397 *
1398 * The most significant 64-N bits (mult) of ratio represent the
1399 * integral part of the fixed point number; the remaining N bits
1400 * (frac) represent the fractional part, ie. ratio represents a fixed
1401 * point number (mult + frac * 2^(-N)).
1402 *
1403 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1404 */
1405static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1406{
1407 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1408}
1409
1410u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1411{
1412 u64 _tsc = tsc;
1413 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1414
1415 if (ratio != kvm_default_tsc_scaling_ratio)
1416 _tsc = __scale_tsc(ratio, tsc);
1417
1418 return _tsc;
1419}
1420EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1421
07c1419a
HZ		 1422static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1423{
1424 u64 tsc;
1425
1426 tsc = kvm_scale_tsc(vcpu, rdtsc());
1427
1428 return target_tsc - tsc;
1429}
1430
4ba76538
HZ		 1431u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1432{
ea26e4ec 1433 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1434}
1435EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1436
a545ab6a
LC		 1437static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1438{
1439 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1440 vcpu->arch.tsc_offset = offset;
1441}
1442
8fe8ab46 1443void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1444{
1445 struct kvm *kvm = vcpu->kvm;
f38e098f 1446 u64 offset, ns, elapsed;
99e3e30a 1447 unsigned long flags;
b48aa97e 1448 bool matched;
0d3da0d2 1449 bool already_matched;
8fe8ab46 1450 u64 data = msr->data;
c5e8ec8e 1451 bool synchronizing = false;
99e3e30a 1452
038f8c11 1453 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1454 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1455 ns = ktime_get_boot_ns();
f38e098f 1456 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1457
03ba32ca 1458 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1459 if (data == 0 && msr->host_initiated) {
1460 /*
1461 * detection of vcpu initialization -- need to sync
1462 * with other vCPUs. This particularly helps to keep
1463 * kvm_clock stable after CPU hotplug
1464 */
1465 synchronizing = true;
1466 } else {
1467 u64 tsc_exp = kvm->arch.last_tsc_write +
1468 nsec_to_cycles(vcpu, elapsed);
1469 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1470 /*
1471 * Special case: TSC write with a small delta (1 second)
1472 * of virtual cycle time against real time is
1473 * interpreted as an attempt to synchronize the CPU.
1474 */
1475 synchronizing = data < tsc_exp + tsc_hz &&
1476 data + tsc_hz > tsc_exp;
1477 }
c5e8ec8e 1478 }
f38e098f
ZA		 1479
1480 /*
5d3cb0f6
ZA		 1481 * For a reliable TSC, we can match TSC offsets, and for an unstable
1482 * TSC, we add elapsed time in this computation. We could let the
1483 * compensation code attempt to catch up if we fall behind, but
1484 * it's better to try to match offsets from the beginning.
1485 */
c5e8ec8e 1486 if (synchronizing &&
5d3cb0f6 1487 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1488 if (!check_tsc_unstable()) {
e26101b1 1489 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1490 pr_debug("kvm: matched tsc offset for %llu\n", data);
1491 } else {
857e4099 1492 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1493 data += delta;
07c1419a 1494 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1495 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1496 }
b48aa97e 1497 matched = true;
0d3da0d2 1498 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1499 } else {
1500 /*
1501 * We split periods of matched TSC writes into generations.
1502 * For each generation, we track the original measured
1503 * nanosecond time, offset, and write, so if TSCs are in
1504 * sync, we can match exact offset, and if not, we can match
4a969980 1505 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1506 *
1507 * These values are tracked in kvm->arch.cur_xxx variables.
1508 */
1509 kvm->arch.cur_tsc_generation++;
1510 kvm->arch.cur_tsc_nsec = ns;
1511 kvm->arch.cur_tsc_write = data;
1512 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1513 matched = false;
0d3da0d2 1514 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1515 kvm->arch.cur_tsc_generation, data);
f38e098f 1516 }
e26101b1
ZA		 1517
1518 /*
1519 * We also track th most recent recorded KHZ, write and time to
1520 * allow the matching interval to be extended at each write.
1521 */
f38e098f
ZA		 1522 kvm->arch.last_tsc_nsec = ns;
1523 kvm->arch.last_tsc_write = data;
5d3cb0f6 1524 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1525
b183aa58 1526 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1527
1528 /* Keep track of which generation this VCPU has synchronized to */
1529 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1530 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1531 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1532
ba904635
WA		 1533 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1534 update_ia32_tsc_adjust_msr(vcpu, offset);
a545ab6a 1535 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1536 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1537
1538 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1539 if (!matched) {
b48aa97e 1540 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1541 } else if (!already_matched) {
1542 kvm->arch.nr_vcpus_matched_tsc++;
1543 }
b48aa97e
MT		 1544
1545 kvm_track_tsc_matching(vcpu);
1546 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1547}
e26101b1 1548
99e3e30a
ZA		 1549EXPORT_SYMBOL_GPL(kvm_write_tsc);
1550
58ea6767
HZ		 1551static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1552 s64 adjustment)
1553{
ea26e4ec 1554 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1555}
1556
1557static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1558{
1559 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1560 WARN_ON(adjustment < 0);
1561 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1562 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1563}
1564
d828199e
MT		 1565#ifdef CONFIG_X86_64
1566
a5a1d1c2 1567static u64 read_tsc(void)
d828199e 1568{
a5a1d1c2 1569 u64 ret = (u64)rdtsc_ordered();
03b9730b 1570 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1571
1572 if (likely(ret >= last))
1573 return ret;
1574
1575 /*
1576 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1577 * predictable (it's just a function of time and the likely is
d828199e
MT		 1578 * very likely) and there's a data dependence, so force GCC
1579 * to generate a branch instead. I don't barrier() because
1580 * we don't actually need a barrier, and if this function
1581 * ever gets inlined it will generate worse code.
1582 */
1583 asm volatile ("");
1584 return last;
1585}
1586
a5a1d1c2 1587static inline u64 vgettsc(u64 *cycle_now)
d828199e
MT		 1588{
1589 long v;
1590 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1591
1592 *cycle_now = read_tsc();
1593
1594 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1595 return v * gtod->clock.mult;
1596}
1597
a5a1d1c2 1598static int do_monotonic_boot(s64 *t, u64 *cycle_now)
d828199e 1599{
cbcf2dd3 1600 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1601 unsigned long seq;
d828199e 1602 int mode;
cbcf2dd3 1603 u64 ns;
d828199e 1604
d828199e
MT		 1605 do {
1606 seq = read_seqcount_begin(&gtod->seq);
1607 mode = gtod->clock.vclock_mode;
cbcf2dd3 1608 ns = gtod->nsec_base;
d828199e
MT		 1609 ns += vgettsc(cycle_now);
1610 ns >>= gtod->clock.shift;
cbcf2dd3 1611 ns += gtod->boot_ns;
d828199e 1612 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1613 *t = ns;
d828199e
MT		 1614
1615 return mode;
1616}
1617
55dd00a7
MT		 1618static int do_realtime(struct timespec *ts, u64 *cycle_now)
1619{
1620 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1621 unsigned long seq;
1622 int mode;
1623 u64 ns;
1624
1625 do {
1626 seq = read_seqcount_begin(&gtod->seq);
1627 mode = gtod->clock.vclock_mode;
1628 ts->tv_sec = gtod->wall_time_sec;
1629 ns = gtod->nsec_base;
1630 ns += vgettsc(cycle_now);
1631 ns >>= gtod->clock.shift;
1632 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1633
1634 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1635 ts->tv_nsec = ns;
1636
1637 return mode;
1638}
1639
d828199e 1640/* returns true if host is using tsc clocksource */
a5a1d1c2 1641static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
d828199e 1642{
d828199e
MT		 1643 /* checked again under seqlock below */
1644 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1645 return false;
1646
cbcf2dd3 1647 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e 1648}
55dd00a7
MT		 1649
1650/* returns true if host is using tsc clocksource */
1651static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1652 u64 *cycle_now)
1653{
1654 /* checked again under seqlock below */
1655 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1656 return false;
1657
1658 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1659}
d828199e
MT		 1660#endif
1661
1662/*
1663 *
b48aa97e
MT		 1664 * Assuming a stable TSC across physical CPUS, and a stable TSC
1665 * across virtual CPUs, the following condition is possible.
1666 * Each numbered line represents an event visible to both
d828199e
MT		 1667 * CPUs at the next numbered event.
1668 *
1669 * "timespecX" represents host monotonic time. "tscX" represents
1670 * RDTSC value.
1671 *
1672 * VCPU0 on CPU0 | VCPU1 on CPU1
1673 *
1674 * 1. read timespec0,tsc0
1675 * 2. | timespec1 = timespec0 + N
1676 * | tsc1 = tsc0 + M
1677 * 3. transition to guest | transition to guest
1678 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1679 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1680 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1681 *
1682 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1683 *
1684 * - ret0 < ret1
1685 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1686 * ...
1687 * - 0 < N - M => M < N
1688 *
1689 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1690 * always the case (the difference between two distinct xtime instances
1691 * might be smaller then the difference between corresponding TSC reads,
1692 * when updating guest vcpus pvclock areas).
1693 *
1694 * To avoid that problem, do not allow visibility of distinct
1695 * system_timestamp/tsc_timestamp values simultaneously: use a master
1696 * copy of host monotonic time values. Update that master copy
1697 * in lockstep.
1698 *
b48aa97e 1699 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1700 *
1701 */
1702
1703static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1704{
1705#ifdef CONFIG_X86_64
1706 struct kvm_arch *ka = &kvm->arch;
1707 int vclock_mode;
b48aa97e
MT		 1708 bool host_tsc_clocksource, vcpus_matched;
1709
1710 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1711 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1712
1713 /*
1714 * If the host uses TSC clock, then passthrough TSC as stable
1715 * to the guest.
1716 */
b48aa97e 1717 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1718 &ka->master_kernel_ns,
1719 &ka->master_cycle_now);
1720
16a96021 1721 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1722 && !backwards_tsc_observed
1723 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1724
d828199e
MT		 1725 if (ka->use_master_clock)
1726 atomic_set(&kvm_guest_has_master_clock, 1);
1727
1728 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1729 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1730 vcpus_matched);
d828199e
MT		 1731#endif
1732}
1733
2860c4b1
PB		 1734void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1735{
1736 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1737}
1738
2e762ff7
MT		 1739static void kvm_gen_update_masterclock(struct kvm *kvm)
1740{
1741#ifdef CONFIG_X86_64
1742 int i;
1743 struct kvm_vcpu *vcpu;
1744 struct kvm_arch *ka = &kvm->arch;
1745
1746 spin_lock(&ka->pvclock_gtod_sync_lock);
1747 kvm_make_mclock_inprogress_request(kvm);
1748 /* no guest entries from this point */
1749 pvclock_update_vm_gtod_copy(kvm);
1750
1751 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1752 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1753
1754 /* guest entries allowed */
1755 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1756 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1757
1758 spin_unlock(&ka->pvclock_gtod_sync_lock);
1759#endif
1760}
1761
e891a32e 1762u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1763{
108b249c 1764 struct kvm_arch *ka = &kvm->arch;
8b953440 1765 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1766 u64 ret;
108b249c 1767
8b953440
PB		 1768 spin_lock(&ka->pvclock_gtod_sync_lock);
1769 if (!ka->use_master_clock) {
1770 spin_unlock(&ka->pvclock_gtod_sync_lock);
1771 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1772 }
1773
8b953440
PB		 1774 hv_clock.tsc_timestamp = ka->master_cycle_now;
1775 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1776 spin_unlock(&ka->pvclock_gtod_sync_lock);
1777
e2c2206a
WL		 1778 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1779 get_cpu();
1780
8b953440
PB		 1781 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1782 &hv_clock.tsc_shift,
1783 &hv_clock.tsc_to_system_mul);
e2c2206a
WL		 1784 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1785
1786 put_cpu();
1787
1788 return ret;
108b249c
PB		 1789}
1790
0d6dd2ff
PB		 1791static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1792{
1793 struct kvm_vcpu_arch *vcpu = &v->arch;
1794 struct pvclock_vcpu_time_info guest_hv_clock;
1795
4e335d9e 1796 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1797 &guest_hv_clock, sizeof(guest_hv_clock))))
1798 return;
1799
1800 /* This VCPU is paused, but it's legal for a guest to read another
1801 * VCPU's kvmclock, so we really have to follow the specification where
1802 * it says that version is odd if data is being modified, and even after
1803 * it is consistent.
1804 *
1805 * Version field updates must be kept separate. This is because
1806 * kvm_write_guest_cached might use a "rep movs" instruction, and
1807 * writes within a string instruction are weakly ordered. So there
1808 * are three writes overall.
1809 *
1810 * As a small optimization, only write the version field in the first
1811 * and third write. The vcpu->pv_time cache is still valid, because the
1812 * version field is the first in the struct.
1813 */
1814 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1815
1816 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1817 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1818 &vcpu->hv_clock,
1819 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1820
1821 smp_wmb();
1822
1823 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1824 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1825
1826 if (vcpu->pvclock_set_guest_stopped_request) {
1827 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1828 vcpu->pvclock_set_guest_stopped_request = false;
1829 }
1830
1831 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1832
4e335d9e
PB		 1833 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1834 &vcpu->hv_clock,
1835 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1836
1837 smp_wmb();
1838
1839 vcpu->hv_clock.version++;
4e335d9e
PB		 1840 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1841 &vcpu->hv_clock,
1842 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1843}
1844
34c238a1 1845static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1846{
78db6a50 1847 unsigned long flags, tgt_tsc_khz;
18068523 1848 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1849 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1850 s64 kernel_ns;
d828199e 1851 u64 tsc_timestamp, host_tsc;
51d59c6b 1852 u8 pvclock_flags;
d828199e
MT		 1853 bool use_master_clock;
1854
1855 kernel_ns = 0;
1856 host_tsc = 0;
18068523 1857
d828199e
MT		 1858 /*
1859 * If the host uses TSC clock, then passthrough TSC as stable
1860 * to the guest.
1861 */
1862 spin_lock(&ka->pvclock_gtod_sync_lock);
1863 use_master_clock = ka->use_master_clock;
1864 if (use_master_clock) {
1865 host_tsc = ka->master_cycle_now;
1866 kernel_ns = ka->master_kernel_ns;
1867 }
1868 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1869
1870 /* Keep irq disabled to prevent changes to the clock */
1871 local_irq_save(flags);
78db6a50
PB		 1872 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1873 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1874 local_irq_restore(flags);
1875 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1876 return 1;
1877 }
d828199e 1878 if (!use_master_clock) {
4ea1636b 1879 host_tsc = rdtsc();
108b249c 1880 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1881 }
1882
4ba76538 1883 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1884
c285545f
ZA		 1885 /*
1886 * We may have to catch up the TSC to match elapsed wall clock
1887 * time for two reasons, even if kvmclock is used.
1888 * 1) CPU could have been running below the maximum TSC rate
1889 * 2) Broken TSC compensation resets the base at each VCPU
1890 * entry to avoid unknown leaps of TSC even when running
1891 * again on the same CPU. This may cause apparent elapsed
1892 * time to disappear, and the guest to stand still or run
1893 * very slowly.
1894 */
1895 if (vcpu->tsc_catchup) {
1896 u64 tsc = compute_guest_tsc(v, kernel_ns);
1897 if (tsc > tsc_timestamp) {
f1e2b260 1898 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1899 tsc_timestamp = tsc;
1900 }
50d0a0f9
GH		 1901 }
1902
18068523
GOC		 1903 local_irq_restore(flags);
1904
0d6dd2ff 1905 /* With all the info we got, fill in the values */
18068523 1906
78db6a50
PB		 1907 if (kvm_has_tsc_control)
1908 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1909
1910 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1911 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1912 &vcpu->hv_clock.tsc_shift,
1913 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1914 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1915 }
1916
1d5f066e 1917 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1918 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1919 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1920
d828199e 1921 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 1922 pvclock_flags = 0;
d828199e
MT		 1923 if (use_master_clock)
1924 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1925
78c0337a
MT		 1926 vcpu->hv_clock.flags = pvclock_flags;
1927
095cf55d
PB		 1928 if (vcpu->pv_time_enabled)
1929 kvm_setup_pvclock_page(v);
1930 if (v == kvm_get_vcpu(v->kvm, 0))
1931 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 1932 return 0;
c8076604
GH		 1933}
1934
0061d53d
MT		 1935/*
1936 * kvmclock updates which are isolated to a given vcpu, such as
1937 * vcpu->cpu migration, should not allow system_timestamp from
1938 * the rest of the vcpus to remain static. Otherwise ntp frequency
1939 * correction applies to one vcpu's system_timestamp but not
1940 * the others.
1941 *
1942 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1943 * We need to rate-limit these requests though, as they can
1944 * considerably slow guests that have a large number of vcpus.
1945 * The time for a remote vcpu to update its kvmclock is bound
1946 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1947 */
1948
7e44e449
AJ		 1949#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1950
1951static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1952{
1953 int i;
7e44e449
AJ		 1954 struct delayed_work *dwork = to_delayed_work(work);
1955 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1956 kvmclock_update_work);
1957 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1958 struct kvm_vcpu *vcpu;
1959
1960 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1961 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1962 kvm_vcpu_kick(vcpu);
1963 }
1964}
1965
7e44e449
AJ		 1966static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1967{
1968 struct kvm *kvm = v->kvm;
1969
105b21bb 1970 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1971 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1972 KVMCLOCK_UPDATE_DELAY);
1973}
1974
332967a3
AJ		 1975#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1976
1977static void kvmclock_sync_fn(struct work_struct *work)
1978{
1979 struct delayed_work *dwork = to_delayed_work(work);
1980 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1981 kvmclock_sync_work);
1982 struct kvm *kvm = container_of(ka, struct kvm, arch);
1983
630994b3
MT		 1984 if (!kvmclock_periodic_sync)
1985 return;
1986
332967a3
AJ		 1987 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1988 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1989 KVMCLOCK_SYNC_PERIOD);
1990}
1991
890ca9ae 1992static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1993{
890ca9ae
HY		 1994 u64 mcg_cap = vcpu->arch.mcg_cap;
1995 unsigned bank_num = mcg_cap & 0xff;
1996
15c4a640 1997 switch (msr) {
15c4a640 1998 case MSR_IA32_MCG_STATUS:
890ca9ae 1999 vcpu->arch.mcg_status = data;
15c4a640 2000 break;
c7ac679c 2001 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2002 if (!(mcg_cap & MCG_CTL_P))
2003 return 1;
2004 if (data != 0 && data != ~(u64)0)
2005 return -1;
2006 vcpu->arch.mcg_ctl = data;
2007 break;
2008 default:
2009 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2010 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2011 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2012 /* only 0 or all 1s can be written to IA32_MCi_CTL
2013 * some Linux kernels though clear bit 10 in bank 4 to
2014 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2015 * this to avoid an uncatched #GP in the guest
2016 */
890ca9ae 2017 if ((offset & 0x3) == 0 &&
114be429 2018 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 2019 return -1;
2020 vcpu->arch.mce_banks[offset] = data;
2021 break;
2022 }
2023 return 1;
2024 }
2025 return 0;
2026}
2027
ffde22ac
ES		 2028static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2029{
2030 struct kvm *kvm = vcpu->kvm;
2031 int lm = is_long_mode(vcpu);
2032 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2033 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2034 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2035 : kvm->arch.xen_hvm_config.blob_size_32;
2036 u32 page_num = data & ~PAGE_MASK;
2037 u64 page_addr = data & PAGE_MASK;
2038 u8 *page;
2039 int r;
2040
2041 r = -E2BIG;
2042 if (page_num >= blob_size)
2043 goto out;
2044 r = -ENOMEM;
ff5c2c03
SL		 2045 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2046 if (IS_ERR(page)) {
2047 r = PTR_ERR(page);
ffde22ac 2048 goto out;
ff5c2c03 2049 }
54bf36aa 2050 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2051 goto out_free;
2052 r = 0;
2053out_free:
2054 kfree(page);
2055out:
2056 return r;
2057}
2058
344d9588
GN		 2059static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2060{
2061 gpa_t gpa = data & ~0x3f;
2062
4a969980 2063 /* Bits 2:5 are reserved, Should be zero */
6adba527 2064 if (data & 0x3c)
344d9588
GN		 2065 return 1;
2066
2067 vcpu->arch.apf.msr_val = data;
2068
2069 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2070 kvm_clear_async_pf_completion_queue(vcpu);
2071 kvm_async_pf_hash_reset(vcpu);
2072 return 0;
2073 }
2074
4e335d9e 2075 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2076 sizeof(u32)))
344d9588
GN		 2077 return 1;
2078
6adba527 2079 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2080 kvm_async_pf_wakeup_all(vcpu);
2081 return 0;
2082}
2083
12f9a48f
GC		 2084static void kvmclock_reset(struct kvm_vcpu *vcpu)
2085{
0b79459b 2086 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2087}
2088
c9aaa895
GC		 2089static void record_steal_time(struct kvm_vcpu *vcpu)
2090{
2091 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2092 return;
2093
4e335d9e 2094 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2095 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2096 return;
2097
0b9f6c46
PX		 2098 vcpu->arch.st.steal.preempted = 0;
2099
35f3fae1
WL		 2100 if (vcpu->arch.st.steal.version & 1)
2101 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2102
2103 vcpu->arch.st.steal.version += 1;
2104
4e335d9e 2105 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2106 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2107
2108 smp_wmb();
2109
c54cdf14
LC		 2110 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2111 vcpu->arch.st.last_steal;
2112 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2113
4e335d9e 2114 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2115 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2116
2117 smp_wmb();
2118
2119 vcpu->arch.st.steal.version += 1;
c9aaa895 2120
4e335d9e 2121 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2122 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2123}
2124
8fe8ab46 2125int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2126{
5753785f 2127 bool pr = false;
8fe8ab46
WA		 2128 u32 msr = msr_info->index;
2129 u64 data = msr_info->data;
5753785f 2130
15c4a640 2131 switch (msr) {
2e32b719
BP		 2132 case MSR_AMD64_NB_CFG:
2133 case MSR_IA32_UCODE_REV:
2134 case MSR_IA32_UCODE_WRITE:
2135 case MSR_VM_HSAVE_PA:
2136 case MSR_AMD64_PATCH_LOADER:
2137 case MSR_AMD64_BU_CFG2:
405a353a 2138 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2139 break;
2140
15c4a640 2141 case MSR_EFER:
b69e8cae 2142 return set_efer(vcpu, data);
8f1589d9
AP		 2143 case MSR_K7_HWCR:
2144 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2145 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2146 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2147 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2148 if (data != 0) {
a737f256
CD		 2149 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2150 data);
8f1589d9
AP		 2151 return 1;
2152 }
15c4a640 2153 break;
f7c6d140
AP		 2154 case MSR_FAM10H_MMIO_CONF_BASE:
2155 if (data != 0) {
a737f256
CD		 2156 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2157 "0x%llx\n", data);
f7c6d140
AP		 2158 return 1;
2159 }
15c4a640 2160 break;
b5e2fec0
AG		 2161 case MSR_IA32_DEBUGCTLMSR:
2162 if (!data) {
2163 /* We support the non-activated case already */
2164 break;
2165 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2166 /* Values other than LBR and BTF are vendor-specific,
2167 thus reserved and should throw a #GP */
2168 return 1;
2169 }
a737f256
CD		 2170 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2171 __func__, data);
b5e2fec0 2172 break;
9ba075a6 2173 case 0x200 ... 0x2ff:
ff53604b 2174 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2175 case MSR_IA32_APICBASE:
58cb628d 2176 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2177 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2178 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2179 case MSR_IA32_TSCDEADLINE:
2180 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2181 break;
ba904635
WA		 2182 case MSR_IA32_TSC_ADJUST:
2183 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2184 if (!msr_info->host_initiated) {
d913b904 2185 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2186 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2187 }
2188 vcpu->arch.ia32_tsc_adjust_msr = data;
2189 }
2190 break;
15c4a640 2191 case MSR_IA32_MISC_ENABLE:
ad312c7c 2192 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2193 break;
64d60670
PB		 2194 case MSR_IA32_SMBASE:
2195 if (!msr_info->host_initiated)
2196 return 1;
2197 vcpu->arch.smbase = data;
2198 break;
11c6bffa 2199 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2200 case MSR_KVM_WALL_CLOCK:
2201 vcpu->kvm->arch.wall_clock = data;
2202 kvm_write_wall_clock(vcpu->kvm, data);
2203 break;
11c6bffa 2204 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2205 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2206 struct kvm_arch *ka = &vcpu->kvm->arch;
2207
12f9a48f 2208 kvmclock_reset(vcpu);
18068523 2209
54750f2c
MT		 2210 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2211 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2212
2213 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2214 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2215
2216 ka->boot_vcpu_runs_old_kvmclock = tmp;
2217 }
2218
18068523 2219 vcpu->arch.time = data;
0061d53d 2220 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2221
2222 /* we verify if the enable bit is set... */
2223 if (!(data & 1))
2224 break;
2225
4e335d9e 2226 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2227 &vcpu->arch.pv_time, data & ~1ULL,
2228 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2229 vcpu->arch.pv_time_enabled = false;
2230 else
2231 vcpu->arch.pv_time_enabled = true;
32cad84f 2232
18068523
GOC		 2233 break;
2234 }
344d9588
GN		 2235 case MSR_KVM_ASYNC_PF_EN:
2236 if (kvm_pv_enable_async_pf(vcpu, data))
2237 return 1;
2238 break;
c9aaa895
GC		 2239 case MSR_KVM_STEAL_TIME:
2240
2241 if (unlikely(!sched_info_on()))
2242 return 1;
2243
2244 if (data & KVM_STEAL_RESERVED_MASK)
2245 return 1;
2246
4e335d9e 2247 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2248 data & KVM_STEAL_VALID_BITS,
2249 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2250 return 1;
2251
2252 vcpu->arch.st.msr_val = data;
2253
2254 if (!(data & KVM_MSR_ENABLED))
2255 break;
2256
c9aaa895
GC		 2257 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2258
2259 break;
ae7a2a3f
MT		 2260 case MSR_KVM_PV_EOI_EN:
2261 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2262 return 1;
2263 break;
c9aaa895 2264
890ca9ae
HY		 2265 case MSR_IA32_MCG_CTL:
2266 case MSR_IA32_MCG_STATUS:
81760dcc 2267 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2268 return set_msr_mce(vcpu, msr, data);
71db6023 2269
6912ac32
WH		 2270 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2271 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2272 pr = true; /* fall through */
2273 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2274 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2275 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2276 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2277
2278 if (pr || data != 0)
a737f256
CD		 2279 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2280 "0x%x data 0x%llx\n", msr, data);
5753785f 2281 break;
84e0cefa
JS		 2282 case MSR_K7_CLK_CTL:
2283 /*
2284 * Ignore all writes to this no longer documented MSR.
2285 * Writes are only relevant for old K7 processors,
2286 * all pre-dating SVM, but a recommended workaround from
4a969980 2287 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2288 * affected processor models on the command line, hence
2289 * the need to ignore the workaround.
2290 */
2291 break;
55cd8e5a 2292 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2293 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2294 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2295 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2296 return kvm_hv_set_msr_common(vcpu, msr, data,
2297 msr_info->host_initiated);
91c9c3ed 2298 case MSR_IA32_BBL_CR_CTL3:
2299 /* Drop writes to this legacy MSR -- see rdmsr
2300 * counterpart for further detail.
2301 */
796f4687 2302 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", msr, data);
91c9c3ed 2303 break;
2b036c6b
BO		 2304 case MSR_AMD64_OSVW_ID_LENGTH:
2305 if (!guest_cpuid_has_osvw(vcpu))
2306 return 1;
2307 vcpu->arch.osvw.length = data;
2308 break;
2309 case MSR_AMD64_OSVW_STATUS:
2310 if (!guest_cpuid_has_osvw(vcpu))
2311 return 1;
2312 vcpu->arch.osvw.status = data;
2313 break;
db2336a8
KH		 2314 case MSR_PLATFORM_INFO:
2315 if (!msr_info->host_initiated ||
2316 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2317 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2318 cpuid_fault_enabled(vcpu)))
2319 return 1;
2320 vcpu->arch.msr_platform_info = data;
2321 break;
2322 case MSR_MISC_FEATURES_ENABLES:
2323 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2324 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2325 !supports_cpuid_fault(vcpu)))
2326 return 1;
2327 vcpu->arch.msr_misc_features_enables = data;
2328 break;
15c4a640 2329 default:
ffde22ac
ES		 2330 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2331 return xen_hvm_config(vcpu, data);
c6702c9d 2332 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2333 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2334 if (!ignore_msrs) {
ae0f5499 2335 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2336 msr, data);
ed85c068
AP		 2337 return 1;
2338 } else {
796f4687 2339 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
a737f256 2340 msr, data);
ed85c068
AP		 2341 break;
2342 }
15c4a640
CO		 2343 }
2344 return 0;
2345}
2346EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2347
2348
2349/*
2350 * Reads an msr value (of 'msr_index') into 'pdata'.
2351 * Returns 0 on success, non-0 otherwise.
2352 * Assumes vcpu_load() was already called.
2353 */
609e36d3 2354int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2355{
609e36d3 2356 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2357}
ff651cb6 2358EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2359
890ca9ae 2360static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2361{
2362 u64 data;
890ca9ae
HY		 2363 u64 mcg_cap = vcpu->arch.mcg_cap;
2364 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2365
2366 switch (msr) {
15c4a640
CO		 2367 case MSR_IA32_P5_MC_ADDR:
2368 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2369 data = 0;
2370 break;
15c4a640 2371 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2372 data = vcpu->arch.mcg_cap;
2373 break;
c7ac679c 2374 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2375 if (!(mcg_cap & MCG_CTL_P))
2376 return 1;
2377 data = vcpu->arch.mcg_ctl;
2378 break;
2379 case MSR_IA32_MCG_STATUS:
2380 data = vcpu->arch.mcg_status;
2381 break;
2382 default:
2383 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2384 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2385 u32 offset = msr - MSR_IA32_MC0_CTL;
2386 data = vcpu->arch.mce_banks[offset];
2387 break;
2388 }
2389 return 1;
2390 }
2391 *pdata = data;
2392 return 0;
2393}
2394
609e36d3 2395int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2396{
609e36d3 2397 switch (msr_info->index) {
890ca9ae 2398 case MSR_IA32_PLATFORM_ID:
15c4a640 2399 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2400 case MSR_IA32_DEBUGCTLMSR:
2401 case MSR_IA32_LASTBRANCHFROMIP:
2402 case MSR_IA32_LASTBRANCHTOIP:
2403 case MSR_IA32_LASTINTFROMIP:
2404 case MSR_IA32_LASTINTTOIP:
60af2ecd 2405 case MSR_K8_SYSCFG:
3afb1121
PB		 2406 case MSR_K8_TSEG_ADDR:
2407 case MSR_K8_TSEG_MASK:
60af2ecd 2408 case MSR_K7_HWCR:
61a6bd67 2409 case MSR_VM_HSAVE_PA:
1fdbd48c 2410 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2411 case MSR_AMD64_NB_CFG:
f7c6d140 2412 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2413 case MSR_AMD64_BU_CFG2:
0c2df2a1 2414 case MSR_IA32_PERF_CTL:
405a353a 2415 case MSR_AMD64_DC_CFG:
609e36d3 2416 msr_info->data = 0;
15c4a640 2417 break;
6912ac32
WH		 2418 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2419 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2420 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2421 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2422 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2423 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2424 msr_info->data = 0;
5753785f 2425 break;
742bc670 2426 case MSR_IA32_UCODE_REV:
609e36d3 2427 msr_info->data = 0x100000000ULL;
742bc670 2428 break;
9ba075a6 2429 case MSR_MTRRcap:
9ba075a6 2430 case 0x200 ... 0x2ff:
ff53604b 2431 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2432 case 0xcd: /* fsb frequency */
609e36d3 2433 msr_info->data = 3;
15c4a640 2434 break;
7b914098
JS		 2435 /*
2436 * MSR_EBC_FREQUENCY_ID
2437 * Conservative value valid for even the basic CPU models.
2438 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2439 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2440 * and 266MHz for model 3, or 4. Set Core Clock
2441 * Frequency to System Bus Frequency Ratio to 1 (bits
2442 * 31:24) even though these are only valid for CPU
2443 * models > 2, however guests may end up dividing or
2444 * multiplying by zero otherwise.
2445 */
2446 case MSR_EBC_FREQUENCY_ID:
609e36d3 2447 msr_info->data = 1 << 24;
7b914098 2448 break;
15c4a640 2449 case MSR_IA32_APICBASE:
609e36d3 2450 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2451 break;
0105d1a5 2452 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2453 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2454 break;
a3e06bbe 2455 case MSR_IA32_TSCDEADLINE:
609e36d3 2456 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2457 break;
ba904635 2458 case MSR_IA32_TSC_ADJUST:
609e36d3 2459 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2460 break;
15c4a640 2461 case MSR_IA32_MISC_ENABLE:
609e36d3 2462 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2463 break;
64d60670
PB		 2464 case MSR_IA32_SMBASE:
2465 if (!msr_info->host_initiated)
2466 return 1;
2467 msr_info->data = vcpu->arch.smbase;
15c4a640 2468 break;
847f0ad8
AG		 2469 case MSR_IA32_PERF_STATUS:
2470 /* TSC increment by tick */
609e36d3 2471 msr_info->data = 1000ULL;
847f0ad8 2472 /* CPU multiplier */
b0996ae4 2473 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2474 break;
15c4a640 2475 case MSR_EFER:
609e36d3 2476 msr_info->data = vcpu->arch.efer;
15c4a640 2477 break;
18068523 2478 case MSR_KVM_WALL_CLOCK:
11c6bffa 2479 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2480 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2481 break;
2482 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2483 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2484 msr_info->data = vcpu->arch.time;
18068523 2485 break;
344d9588 2486 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2487 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2488 break;
c9aaa895 2489 case MSR_KVM_STEAL_TIME:
609e36d3 2490 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2491 break;
1d92128f 2492 case MSR_KVM_PV_EOI_EN:
609e36d3 2493 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2494 break;
890ca9ae
HY		 2495 case MSR_IA32_P5_MC_ADDR:
2496 case MSR_IA32_P5_MC_TYPE:
2497 case MSR_IA32_MCG_CAP:
2498 case MSR_IA32_MCG_CTL:
2499 case MSR_IA32_MCG_STATUS:
81760dcc 2500 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2501 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2502 case MSR_K7_CLK_CTL:
2503 /*
2504 * Provide expected ramp-up count for K7. All other
2505 * are set to zero, indicating minimum divisors for
2506 * every field.
2507 *
2508 * This prevents guest kernels on AMD host with CPU
2509 * type 6, model 8 and higher from exploding due to
2510 * the rdmsr failing.
2511 */
609e36d3 2512 msr_info->data = 0x20000000;
84e0cefa 2513 break;
55cd8e5a 2514 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2515 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2516 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2517 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2518 return kvm_hv_get_msr_common(vcpu,
2519 msr_info->index, &msr_info->data);
55cd8e5a 2520 break;
91c9c3ed 2521 case MSR_IA32_BBL_CR_CTL3:
2522 /* This legacy MSR exists but isn't fully documented in current
2523 * silicon. It is however accessed by winxp in very narrow
2524 * scenarios where it sets bit #19, itself documented as
2525 * a "reserved" bit. Best effort attempt to source coherent
2526 * read data here should the balance of the register be
2527 * interpreted by the guest:
2528 *
2529 * L2 cache control register 3: 64GB range, 256KB size,
2530 * enabled, latency 0x1, configured
2531 */
609e36d3 2532 msr_info->data = 0xbe702111;
91c9c3ed 2533 break;
2b036c6b
BO		 2534 case MSR_AMD64_OSVW_ID_LENGTH:
2535 if (!guest_cpuid_has_osvw(vcpu))
2536 return 1;
609e36d3 2537 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2538 break;
2539 case MSR_AMD64_OSVW_STATUS:
2540 if (!guest_cpuid_has_osvw(vcpu))
2541 return 1;
609e36d3 2542 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2543 break;
db2336a8
KH		 2544 case MSR_PLATFORM_INFO:
2545 msr_info->data = vcpu->arch.msr_platform_info;
2546 break;
2547 case MSR_MISC_FEATURES_ENABLES:
2548 msr_info->data = vcpu->arch.msr_misc_features_enables;
2549 break;
15c4a640 2550 default:
c6702c9d 2551 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2552 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2553 if (!ignore_msrs) {
ae0f5499
BD		 2554 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2555 msr_info->index);
ed85c068
AP		 2556 return 1;
2557 } else {
609e36d3
PB		 2558 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2559 msr_info->data = 0;
ed85c068
AP		 2560 }
2561 break;
15c4a640 2562 }
15c4a640
CO		 2563 return 0;
2564}
2565EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2566
313a3dc7
CO		 2567/*
2568 * Read or write a bunch of msrs. All parameters are kernel addresses.
2569 *
2570 * @return number of msrs set successfully.
2571 */
2572static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2573 struct kvm_msr_entry *entries,
2574 int (*do_msr)(struct kvm_vcpu *vcpu,
2575 unsigned index, u64 *data))
2576{
f656ce01 2577 int i, idx;
313a3dc7 2578
f656ce01 2579 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2580 for (i = 0; i < msrs->nmsrs; ++i)
2581 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2582 break;
f656ce01 2583 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2584
313a3dc7
CO		 2585 return i;
2586}
2587
2588/*
2589 * Read or write a bunch of msrs. Parameters are user addresses.
2590 *
2591 * @return number of msrs set successfully.
2592 */
2593static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2594 int (*do_msr)(struct kvm_vcpu *vcpu,
2595 unsigned index, u64 *data),
2596 int writeback)
2597{
2598 struct kvm_msrs msrs;
2599 struct kvm_msr_entry *entries;
2600 int r, n;
2601 unsigned size;
2602
2603 r = -EFAULT;
2604 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2605 goto out;
2606
2607 r = -E2BIG;
2608 if (msrs.nmsrs >= MAX_IO_MSRS)
2609 goto out;
2610
313a3dc7 2611 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2612 entries = memdup_user(user_msrs->entries, size);
2613 if (IS_ERR(entries)) {
2614 r = PTR_ERR(entries);
313a3dc7 2615 goto out;
ff5c2c03 2616 }
313a3dc7
CO		 2617
2618 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2619 if (r < 0)
2620 goto out_free;
2621
2622 r = -EFAULT;
2623 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2624 goto out_free;
2625
2626 r = n;
2627
2628out_free:
7a73c028 2629 kfree(entries);
313a3dc7
CO		 2630out:
2631 return r;
2632}
2633
784aa3d7 2634int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2635{
2636 int r;
2637
2638 switch (ext) {
2639 case KVM_CAP_IRQCHIP:
2640 case KVM_CAP_HLT:
2641 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2642 case KVM_CAP_SET_TSS_ADDR:
07716717 2643 case KVM_CAP_EXT_CPUID:
9c15bb1d 2644 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2645 case KVM_CAP_CLOCKSOURCE:
7837699f 2646 case KVM_CAP_PIT:
a28e4f5a 2647 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2648 case KVM_CAP_MP_STATE:
ed848624 2649 case KVM_CAP_SYNC_MMU:
a355c85c 2650 case KVM_CAP_USER_NMI:
52d939a0 2651 case KVM_CAP_REINJECT_CONTROL:
4925663a 2652 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2653 case KVM_CAP_IOEVENTFD:
f848a5a8 2654 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2655 case KVM_CAP_PIT2:
e9f42757 2656 case KVM_CAP_PIT_STATE2:
b927a3ce 2657 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2658 case KVM_CAP_XEN_HVM:
3cfc3092 2659 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2660 case KVM_CAP_HYPERV:
10388a07 2661 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2662 case KVM_CAP_HYPERV_SPIN:
5c919412 2663 case KVM_CAP_HYPERV_SYNIC:
ab9f4ecb 2664 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2665 case KVM_CAP_DEBUGREGS:
d2be1651 2666 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2667 case KVM_CAP_XSAVE:
344d9588 2668 case KVM_CAP_ASYNC_PF:
92a1f12d 2669 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2670 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2671 case KVM_CAP_READONLY_MEM:
5f66b620 2672 case KVM_CAP_HYPERV_TIME:
100943c5 2673 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2674 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2675 case KVM_CAP_ENABLE_CAP_VM:
2676 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2677 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2678 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2679 case KVM_CAP_IMMEDIATE_EXIT:
018d00d2
ZX		 2680 r = 1;
2681 break;
e3fd9a93
PB		 2682 case KVM_CAP_ADJUST_CLOCK:
2683 r = KVM_CLOCK_TSC_STABLE;
2684 break;
668fffa3
MT		 2685 case KVM_CAP_X86_GUEST_MWAIT:
2686 r = kvm_mwait_in_guest();
2687 break;
6d396b55
PB		 2688 case KVM_CAP_X86_SMM:
2689 /* SMBASE is usually relocated above 1M on modern chipsets,
2690 * and SMM handlers might indeed rely on 4G segment limits,
2691 * so do not report SMM to be available if real mode is
2692 * emulated via vm86 mode. Still, do not go to great lengths
2693 * to avoid userspace's usage of the feature, because it is a
2694 * fringe case that is not enabled except via specific settings
2695 * of the module parameters.
2696 */
2697 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2698 break;
774ead3a
AK		 2699 case KVM_CAP_VAPIC:
2700 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2701 break;
f725230a 2702 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2703 r = KVM_SOFT_MAX_VCPUS;
2704 break;
2705 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2706 r = KVM_MAX_VCPUS;
2707 break;
a988b910 2708 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2709 r = KVM_USER_MEM_SLOTS;
a988b910 2710 break;
a68a6a72
MT		 2711 case KVM_CAP_PV_MMU: /* obsolete */
2712 r = 0;
2f333bcb 2713 break;
890ca9ae
HY		 2714 case KVM_CAP_MCE:
2715 r = KVM_MAX_MCE_BANKS;
2716 break;
2d5b5a66 2717 case KVM_CAP_XCRS:
d366bf7e 2718 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2719 break;
92a1f12d
JR		 2720 case KVM_CAP_TSC_CONTROL:
2721 r = kvm_has_tsc_control;
2722 break;
37131313
RK		 2723 case KVM_CAP_X2APIC_API:
2724 r = KVM_X2APIC_API_VALID_FLAGS;
2725 break;
018d00d2
ZX		 2726 default:
2727 r = 0;
2728 break;
2729 }
2730 return r;
2731
2732}
2733
043405e1
CO		 2734long kvm_arch_dev_ioctl(struct file *filp,
2735 unsigned int ioctl, unsigned long arg)
2736{
2737 void __user *argp = (void __user *)arg;
2738 long r;
2739
2740 switch (ioctl) {
2741 case KVM_GET_MSR_INDEX_LIST: {
2742 struct kvm_msr_list __user *user_msr_list = argp;
2743 struct kvm_msr_list msr_list;
2744 unsigned n;
2745
2746 r = -EFAULT;
2747 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2748 goto out;
2749 n = msr_list.nmsrs;
62ef68bb 2750 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2751 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2752 goto out;
2753 r = -E2BIG;
e125e7b6 2754 if (n < msr_list.nmsrs)
043405e1
CO		 2755 goto out;
2756 r = -EFAULT;
2757 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2758 num_msrs_to_save * sizeof(u32)))
2759 goto out;
e125e7b6 2760 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2761 &emulated_msrs,
62ef68bb 2762 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2763 goto out;
2764 r = 0;
2765 break;
2766 }
9c15bb1d
BP		 2767 case KVM_GET_SUPPORTED_CPUID:
2768 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2769 struct kvm_cpuid2 __user *cpuid_arg = argp;
2770 struct kvm_cpuid2 cpuid;
2771
2772 r = -EFAULT;
2773 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2774 goto out;
9c15bb1d
BP		 2775
2776 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2777 ioctl);
674eea0f
AK		 2778 if (r)
2779 goto out;
2780
2781 r = -EFAULT;
2782 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2783 goto out;
2784 r = 0;
2785 break;
2786 }
890ca9ae 2787 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2788 r = -EFAULT;
c45dcc71
AR		 2789 if (copy_to_user(argp, &kvm_mce_cap_supported,
2790 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2791 goto out;
2792 r = 0;
2793 break;
2794 }
043405e1
CO		 2795 default:
2796 r = -EINVAL;
2797 }
2798out:
2799 return r;
2800}
2801
f5f48ee1
SY		 2802static void wbinvd_ipi(void *garbage)
2803{
2804 wbinvd();
2805}
2806
2807static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2808{
e0f0bbc5 2809 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2810}
2811
313a3dc7
CO		 2812void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2813{
f5f48ee1
SY		 2814 /* Address WBINVD may be executed by guest */
2815 if (need_emulate_wbinvd(vcpu)) {
2816 if (kvm_x86_ops->has_wbinvd_exit())
2817 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2818 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2819 smp_call_function_single(vcpu->cpu,
2820 wbinvd_ipi, NULL, 1);
2821 }
2822
313a3dc7 2823 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2824
0dd6a6ed
ZA		 2825 /* Apply any externally detected TSC adjustments (due to suspend) */
2826 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2827 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2828 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2829 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2830 }
8f6055cb 2831
48434c20 2832 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2833 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2834 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2835 if (tsc_delta < 0)
2836 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2837
c285545f 2838 if (check_tsc_unstable()) {
07c1419a 2839 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2840 vcpu->arch.last_guest_tsc);
a545ab6a 2841 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2842 vcpu->arch.tsc_catchup = 1;
c285545f 2843 }
e12c8f36
WL		 2844 if (kvm_lapic_hv_timer_in_use(vcpu) &&
2845 kvm_x86_ops->set_hv_timer(vcpu,
498f8162 2846 kvm_get_lapic_target_expiration_tsc(vcpu)))
e12c8f36 2847 kvm_lapic_switch_to_sw_timer(vcpu);
d98d07ca
MT		 2848 /*
2849 * On a host with synchronized TSC, there is no need to update
2850 * kvmclock on vcpu->cpu migration
2851 */
2852 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2853 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 2854 if (vcpu->cpu != cpu)
1bd2009e 2855 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 2856 vcpu->cpu = cpu;
6b7d7e76 2857 }
c9aaa895 2858
c9aaa895 2859 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2860}
2861
0b9f6c46
PX		 2862static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2863{
2864 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2865 return;
2866
2867 vcpu->arch.st.steal.preempted = 1;
2868
4e335d9e 2869 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 2870 &vcpu->arch.st.steal.preempted,
2871 offsetof(struct kvm_steal_time, preempted),
2872 sizeof(vcpu->arch.st.steal.preempted));
2873}
2874
313a3dc7
CO		 2875void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2876{
cc0d907c 2877 int idx;
931f261b
AA		 2878 /*
2879 * Disable page faults because we're in atomic context here.
2880 * kvm_write_guest_offset_cached() would call might_fault()
2881 * that relies on pagefault_disable() to tell if there's a
2882 * bug. NOTE: the write to guest memory may not go through if
2883 * during postcopy live migration or if there's heavy guest
2884 * paging.
2885 */
2886 pagefault_disable();
cc0d907c
AA		 2887 /*
2888 * kvm_memslots() will be called by
2889 * kvm_write_guest_offset_cached() so take the srcu lock.
2890 */
2891 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 2892 kvm_steal_time_set_preempted(vcpu);
cc0d907c 2893 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 2894 pagefault_enable();
02daab21 2895 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2896 kvm_put_guest_fpu(vcpu);
4ea1636b 2897 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2898}
2899
313a3dc7
CO		 2900static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2901 struct kvm_lapic_state *s)
2902{
76dfafd5 2903 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb
AS		 2904 kvm_x86_ops->sync_pir_to_irr(vcpu);
2905
a92e2543 2906 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 2907}
2908
2909static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2910 struct kvm_lapic_state *s)
2911{
a92e2543
RK		 2912 int r;
2913
2914 r = kvm_apic_set_state(vcpu, s);
2915 if (r)
2916 return r;
cb142eb7 2917 update_cr8_intercept(vcpu);
313a3dc7
CO		 2918
2919 return 0;
2920}
2921
127a457a
MG		 2922static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2923{
2924 return (!lapic_in_kernel(vcpu) ||
2925 kvm_apic_accept_pic_intr(vcpu));
2926}
2927
782d422b
MG		 2928/*
2929 * if userspace requested an interrupt window, check that the
2930 * interrupt window is open.
2931 *
2932 * No need to exit to userspace if we already have an interrupt queued.
2933 */
2934static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2935{
2936 return kvm_arch_interrupt_allowed(vcpu) &&
2937 !kvm_cpu_has_interrupt(vcpu) &&
2938 !kvm_event_needs_reinjection(vcpu) &&
2939 kvm_cpu_accept_dm_intr(vcpu);
2940}
2941
f77bc6a4
ZX		 2942static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2943 struct kvm_interrupt *irq)
2944{
02cdb50f 2945 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2946 return -EINVAL;
1c1a9ce9
SR		 2947
2948 if (!irqchip_in_kernel(vcpu->kvm)) {
2949 kvm_queue_interrupt(vcpu, irq->irq, false);
2950 kvm_make_request(KVM_REQ_EVENT, vcpu);
2951 return 0;
2952 }
2953
2954 /*
2955 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2956 * fail for in-kernel 8259.
2957 */
2958 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2959 return -ENXIO;
f77bc6a4 2960
1c1a9ce9
SR		 2961 if (vcpu->arch.pending_external_vector != -1)
2962 return -EEXIST;
f77bc6a4 2963
1c1a9ce9 2964 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2965 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2966 return 0;
2967}
2968
c4abb7c9
JK		 2969static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2970{
c4abb7c9 2971 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2972
2973 return 0;
2974}
2975
f077825a
PB		 2976static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2977{
64d60670
PB		 2978 kvm_make_request(KVM_REQ_SMI, vcpu);
2979
f077825a
PB		 2980 return 0;
2981}
2982
b209749f
AK		 2983static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2984 struct kvm_tpr_access_ctl *tac)
2985{
2986 if (tac->flags)
2987 return -EINVAL;
2988 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2989 return 0;
2990}
2991
890ca9ae
HY		 2992static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2993 u64 mcg_cap)
2994{
2995 int r;
2996 unsigned bank_num = mcg_cap & 0xff, bank;
2997
2998 r = -EINVAL;
a9e38c3e 2999 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3000 goto out;
c45dcc71 3001 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3002 goto out;
3003 r = 0;
3004 vcpu->arch.mcg_cap = mcg_cap;
3005 /* Init IA32_MCG_CTL to all 1s */
3006 if (mcg_cap & MCG_CTL_P)
3007 vcpu->arch.mcg_ctl = ~(u64)0;
3008 /* Init IA32_MCi_CTL to all 1s */
3009 for (bank = 0; bank < bank_num; bank++)
3010 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3011
3012 if (kvm_x86_ops->setup_mce)
3013 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3014out:
3015 return r;
3016}
3017
3018static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3019 struct kvm_x86_mce *mce)
3020{
3021 u64 mcg_cap = vcpu->arch.mcg_cap;
3022 unsigned bank_num = mcg_cap & 0xff;
3023 u64 *banks = vcpu->arch.mce_banks;
3024
3025 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3026 return -EINVAL;
3027 /*
3028 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3029 * reporting is disabled
3030 */
3031 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3032 vcpu->arch.mcg_ctl != ~(u64)0)
3033 return 0;
3034 banks += 4 * mce->bank;
3035 /*
3036 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3037 * reporting is disabled for the bank
3038 */
3039 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3040 return 0;
3041 if (mce->status & MCI_STATUS_UC) {
3042 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3043 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3044 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3045 return 0;
3046 }
3047 if (banks[1] & MCI_STATUS_VAL)
3048 mce->status |= MCI_STATUS_OVER;
3049 banks[2] = mce->addr;
3050 banks[3] = mce->misc;
3051 vcpu->arch.mcg_status = mce->mcg_status;
3052 banks[1] = mce->status;
3053 kvm_queue_exception(vcpu, MC_VECTOR);
3054 } else if (!(banks[1] & MCI_STATUS_VAL)
3055 || !(banks[1] & MCI_STATUS_UC)) {
3056 if (banks[1] & MCI_STATUS_VAL)
3057 mce->status |= MCI_STATUS_OVER;
3058 banks[2] = mce->addr;
3059 banks[3] = mce->misc;
3060 banks[1] = mce->status;
3061 } else
3062 banks[1] |= MCI_STATUS_OVER;
3063 return 0;
3064}
3065
3cfc3092
JK		 3066static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3067 struct kvm_vcpu_events *events)
3068{
7460fb4a 3069 process_nmi(vcpu);
03b82a30
JK		 3070 events->exception.injected =
3071 vcpu->arch.exception.pending &&
3072 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3073 events->exception.nr = vcpu->arch.exception.nr;
3074 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3075 events->exception.pad = 0;
3cfc3092
JK		 3076 events->exception.error_code = vcpu->arch.exception.error_code;
3077
03b82a30
JK		 3078 events->interrupt.injected =
3079 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3080 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3081 events->interrupt.soft = 0;
37ccdcbe 3082 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3083
3084 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3085 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3086 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3087 events->nmi.pad = 0;
3cfc3092 3088
66450a21 3089 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3090
f077825a
PB		 3091 events->smi.smm = is_smm(vcpu);
3092 events->smi.pending = vcpu->arch.smi_pending;
3093 events->smi.smm_inside_nmi =
3094 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3095 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3096
dab4b911 3097 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3098 | KVM_VCPUEVENT_VALID_SHADOW
3099 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3100 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3101}
3102
6ef4e07e
XG		 3103static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3104
3cfc3092
JK		 3105static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3106 struct kvm_vcpu_events *events)
3107{
dab4b911 3108 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3109 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3110 | KVM_VCPUEVENT_VALID_SHADOW
3111 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3112 return -EINVAL;
3113
78e546c8 3114 if (events->exception.injected &&
28d06353
JM		 3115 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3116 is_guest_mode(vcpu)))
78e546c8
PB		 3117 return -EINVAL;
3118
28bf2888
DH		 3119 /* INITs are latched while in SMM */
3120 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3121 (events->smi.smm || events->smi.pending) &&
3122 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3123 return -EINVAL;
3124
7460fb4a 3125 process_nmi(vcpu);
3cfc3092
JK		 3126 vcpu->arch.exception.pending = events->exception.injected;
3127 vcpu->arch.exception.nr = events->exception.nr;
3128 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3129 vcpu->arch.exception.error_code = events->exception.error_code;
3130
3131 vcpu->arch.interrupt.pending = events->interrupt.injected;
3132 vcpu->arch.interrupt.nr = events->interrupt.nr;
3133 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3134 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3135 kvm_x86_ops->set_interrupt_shadow(vcpu,
3136 events->interrupt.shadow);
3cfc3092
JK		 3137
3138 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3139 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3140 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3141 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3142
66450a21 3143 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3144 lapic_in_kernel(vcpu))
66450a21 3145 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3146
f077825a 3147 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3148 u32 hflags = vcpu->arch.hflags;
f077825a 3149 if (events->smi.smm)
6ef4e07e 3150 hflags |= HF_SMM_MASK;
f077825a 3151 else
6ef4e07e
XG		 3152 hflags &= ~HF_SMM_MASK;
3153 kvm_set_hflags(vcpu, hflags);
3154
f077825a
PB		 3155 vcpu->arch.smi_pending = events->smi.pending;
3156 if (events->smi.smm_inside_nmi)
3157 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3158 else
3159 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
bce87cce 3160 if (lapic_in_kernel(vcpu)) {
f077825a
PB		 3161 if (events->smi.latched_init)
3162 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3163 else
3164 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3165 }
3166 }
3167
3842d135
AK		 3168 kvm_make_request(KVM_REQ_EVENT, vcpu);
3169
3cfc3092
JK		 3170 return 0;
3171}
3172
a1efbe77
JK		 3173static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3174 struct kvm_debugregs *dbgregs)
3175{
73aaf249
JK		 3176 unsigned long val;
3177
a1efbe77 3178 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3179 kvm_get_dr(vcpu, 6, &val);
73aaf249 3180 dbgregs->dr6 = val;
a1efbe77
JK		 3181 dbgregs->dr7 = vcpu->arch.dr7;
3182 dbgregs->flags = 0;
97e69aa6 3183 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3184}
3185
3186static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3187 struct kvm_debugregs *dbgregs)
3188{
3189 if (dbgregs->flags)
3190 return -EINVAL;
3191
d14bdb55
PB		 3192 if (dbgregs->dr6 & ~0xffffffffull)
3193 return -EINVAL;
3194 if (dbgregs->dr7 & ~0xffffffffull)
3195 return -EINVAL;
3196
a1efbe77 3197 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3198 kvm_update_dr0123(vcpu);
a1efbe77 3199 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3200 kvm_update_dr6(vcpu);
a1efbe77 3201 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3202 kvm_update_dr7(vcpu);
a1efbe77 3203
a1efbe77
JK		 3204 return 0;
3205}
3206
df1daba7
PB		 3207#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3208
3209static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3210{
c47ada30 3211 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3212 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3213 u64 valid;
3214
3215 /*
3216 * Copy legacy XSAVE area, to avoid complications with CPUID
3217 * leaves 0 and 1 in the loop below.
3218 */
3219 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3220
3221 /* Set XSTATE_BV */
00c87e9a 3222 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3223 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3224
3225 /*
3226 * Copy each region from the possibly compacted offset to the
3227 * non-compacted offset.
3228 */
d91cab78 3229 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3230 while (valid) {
3231 u64 feature = valid & -valid;
3232 int index = fls64(feature) - 1;
3233 void *src = get_xsave_addr(xsave, feature);
3234
3235 if (src) {
3236 u32 size, offset, ecx, edx;
3237 cpuid_count(XSTATE_CPUID, index,
3238 &size, &offset, &ecx, &edx);
3239 memcpy(dest + offset, src, size);
3240 }
3241
3242 valid -= feature;
3243 }
3244}
3245
3246static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3247{
c47ada30 3248 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3249 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3250 u64 valid;
3251
3252 /*
3253 * Copy legacy XSAVE area, to avoid complications with CPUID
3254 * leaves 0 and 1 in the loop below.
3255 */
3256 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3257
3258 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3259 xsave->header.xfeatures = xstate_bv;
782511b0 3260 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3261 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3262
3263 /*
3264 * Copy each region from the non-compacted offset to the
3265 * possibly compacted offset.
3266 */
d91cab78 3267 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3268 while (valid) {
3269 u64 feature = valid & -valid;
3270 int index = fls64(feature) - 1;
3271 void *dest = get_xsave_addr(xsave, feature);
3272
3273 if (dest) {
3274 u32 size, offset, ecx, edx;
3275 cpuid_count(XSTATE_CPUID, index,
3276 &size, &offset, &ecx, &edx);
3277 memcpy(dest, src + offset, size);
ee4100da 3278 }
df1daba7
PB		 3279
3280 valid -= feature;
3281 }
3282}
3283
2d5b5a66
SY		 3284static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3285 struct kvm_xsave *guest_xsave)
3286{
d366bf7e 3287 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3288 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3289 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3290 } else {
2d5b5a66 3291 memcpy(guest_xsave->region,
7366ed77 3292 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3293 sizeof(struct fxregs_state));
2d5b5a66 3294 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3295 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3296 }
3297}
3298
a575813b
WL		 3299#define XSAVE_MXCSR_OFFSET 24
3300
2d5b5a66
SY		 3301static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3302 struct kvm_xsave *guest_xsave)
3303{
3304 u64 xstate_bv =
3305 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3306 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3307
d366bf7e 3308 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3309 /*
3310 * Here we allow setting states that are not present in
3311 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3312 * with old userspace.
3313 */
a575813b
WL		 3314 if (xstate_bv & ~kvm_supported_xcr0() ||
3315 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3316 return -EINVAL;
df1daba7 3317 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3318 } else {
a575813b
WL		 3319 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3320 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3321 return -EINVAL;
7366ed77 3322 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3323 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3324 }
3325 return 0;
3326}
3327
3328static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3329 struct kvm_xcrs *guest_xcrs)
3330{
d366bf7e 3331 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3332 guest_xcrs->nr_xcrs = 0;
3333 return;
3334 }
3335
3336 guest_xcrs->nr_xcrs = 1;
3337 guest_xcrs->flags = 0;
3338 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3339 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3340}
3341
3342static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3343 struct kvm_xcrs *guest_xcrs)
3344{
3345 int i, r = 0;
3346
d366bf7e 3347 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3348 return -EINVAL;
3349
3350 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3351 return -EINVAL;
3352
3353 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3354 /* Only support XCR0 currently */
c67a04cb 3355 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3356 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3357 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3358 break;
3359 }
3360 if (r)
3361 r = -EINVAL;
3362 return r;
3363}
3364
1c0b28c2
EM		 3365/*
3366 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3367 * stopped by the hypervisor. This function will be called from the host only.
3368 * EINVAL is returned when the host attempts to set the flag for a guest that
3369 * does not support pv clocks.
3370 */
3371static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3372{
0b79459b 3373 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3374 return -EINVAL;
51d59c6b 3375 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3376 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3377 return 0;
3378}
3379
5c919412
AS		 3380static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3381 struct kvm_enable_cap *cap)
3382{
3383 if (cap->flags)
3384 return -EINVAL;
3385
3386 switch (cap->cap) {
3387 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3388 if (!irqchip_in_kernel(vcpu->kvm))
3389 return -EINVAL;
5c919412
AS		 3390 return kvm_hv_activate_synic(vcpu);
3391 default:
3392 return -EINVAL;
3393 }
3394}
3395
313a3dc7
CO		 3396long kvm_arch_vcpu_ioctl(struct file *filp,
3397 unsigned int ioctl, unsigned long arg)
3398{
3399 struct kvm_vcpu *vcpu = filp->private_data;
3400 void __user *argp = (void __user *)arg;
3401 int r;
d1ac91d8
AK		 3402 union {
3403 struct kvm_lapic_state *lapic;
3404 struct kvm_xsave *xsave;
3405 struct kvm_xcrs *xcrs;
3406 void *buffer;
3407 } u;
3408
3409 u.buffer = NULL;
313a3dc7
CO		 3410 switch (ioctl) {
3411 case KVM_GET_LAPIC: {
2204ae3c 3412 r = -EINVAL;
bce87cce 3413 if (!lapic_in_kernel(vcpu))
2204ae3c 3414 goto out;
d1ac91d8 3415 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3416
b772ff36 3417 r = -ENOMEM;
d1ac91d8 3418 if (!u.lapic)
b772ff36 3419 goto out;
d1ac91d8 3420 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3421 if (r)
3422 goto out;
3423 r = -EFAULT;
d1ac91d8 3424 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3425 goto out;
3426 r = 0;
3427 break;
3428 }
3429 case KVM_SET_LAPIC: {
2204ae3c 3430 r = -EINVAL;
bce87cce 3431 if (!lapic_in_kernel(vcpu))
2204ae3c 3432 goto out;
ff5c2c03 3433 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3434 if (IS_ERR(u.lapic))
3435 return PTR_ERR(u.lapic);
ff5c2c03 3436
d1ac91d8 3437 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3438 break;
3439 }
f77bc6a4
ZX		 3440 case KVM_INTERRUPT: {
3441 struct kvm_interrupt irq;
3442
3443 r = -EFAULT;
3444 if (copy_from_user(&irq, argp, sizeof irq))
3445 goto out;
3446 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3447 break;
3448 }
c4abb7c9
JK		 3449 case KVM_NMI: {
3450 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3451 break;
3452 }
f077825a
PB		 3453 case KVM_SMI: {
3454 r = kvm_vcpu_ioctl_smi(vcpu);
3455 break;
3456 }
313a3dc7
CO		 3457 case KVM_SET_CPUID: {
3458 struct kvm_cpuid __user *cpuid_arg = argp;
3459 struct kvm_cpuid cpuid;
3460
3461 r = -EFAULT;
3462 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3463 goto out;
3464 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3465 break;
3466 }
07716717
DK		 3467 case KVM_SET_CPUID2: {
3468 struct kvm_cpuid2 __user *cpuid_arg = argp;
3469 struct kvm_cpuid2 cpuid;
3470
3471 r = -EFAULT;
3472 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3473 goto out;
3474 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3475 cpuid_arg->entries);
07716717
DK		 3476 break;
3477 }
3478 case KVM_GET_CPUID2: {
3479 struct kvm_cpuid2 __user *cpuid_arg = argp;
3480 struct kvm_cpuid2 cpuid;
3481
3482 r = -EFAULT;
3483 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3484 goto out;
3485 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3486 cpuid_arg->entries);
07716717
DK		 3487 if (r)
3488 goto out;
3489 r = -EFAULT;
3490 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3491 goto out;
3492 r = 0;
3493 break;
3494 }
313a3dc7 3495 case KVM_GET_MSRS:
609e36d3 3496 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3497 break;
3498 case KVM_SET_MSRS:
3499 r = msr_io(vcpu, argp, do_set_msr, 0);
3500 break;
b209749f
AK		 3501 case KVM_TPR_ACCESS_REPORTING: {
3502 struct kvm_tpr_access_ctl tac;
3503
3504 r = -EFAULT;
3505 if (copy_from_user(&tac, argp, sizeof tac))
3506 goto out;
3507 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3508 if (r)
3509 goto out;
3510 r = -EFAULT;
3511 if (copy_to_user(argp, &tac, sizeof tac))
3512 goto out;
3513 r = 0;
3514 break;
3515 };
b93463aa
AK		 3516 case KVM_SET_VAPIC_ADDR: {
3517 struct kvm_vapic_addr va;
7301d6ab 3518 int idx;
b93463aa
AK		 3519
3520 r = -EINVAL;
35754c98 3521 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3522 goto out;
3523 r = -EFAULT;
3524 if (copy_from_user(&va, argp, sizeof va))
3525 goto out;
7301d6ab 3526 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3527 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3528 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3529 break;
3530 }
890ca9ae
HY		 3531 case KVM_X86_SETUP_MCE: {
3532 u64 mcg_cap;
3533
3534 r = -EFAULT;
3535 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3536 goto out;
3537 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3538 break;
3539 }
3540 case KVM_X86_SET_MCE: {
3541 struct kvm_x86_mce mce;
3542
3543 r = -EFAULT;
3544 if (copy_from_user(&mce, argp, sizeof mce))
3545 goto out;
3546 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3547 break;
3548 }
3cfc3092
JK		 3549 case KVM_GET_VCPU_EVENTS: {
3550 struct kvm_vcpu_events events;
3551
3552 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3553
3554 r = -EFAULT;
3555 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3556 break;
3557 r = 0;
3558 break;
3559 }
3560 case KVM_SET_VCPU_EVENTS: {
3561 struct kvm_vcpu_events events;
3562
3563 r = -EFAULT;
3564 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3565 break;
3566
3567 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3568 break;
3569 }
a1efbe77
JK		 3570 case KVM_GET_DEBUGREGS: {
3571 struct kvm_debugregs dbgregs;
3572
3573 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3574
3575 r = -EFAULT;
3576 if (copy_to_user(argp, &dbgregs,
3577 sizeof(struct kvm_debugregs)))
3578 break;
3579 r = 0;
3580 break;
3581 }
3582 case KVM_SET_DEBUGREGS: {
3583 struct kvm_debugregs dbgregs;
3584
3585 r = -EFAULT;
3586 if (copy_from_user(&dbgregs, argp,
3587 sizeof(struct kvm_debugregs)))
3588 break;
3589
3590 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3591 break;
3592 }
2d5b5a66 3593 case KVM_GET_XSAVE: {
d1ac91d8 3594 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3595 r = -ENOMEM;
d1ac91d8 3596 if (!u.xsave)
2d5b5a66
SY		 3597 break;
3598
d1ac91d8 3599 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3600
3601 r = -EFAULT;
d1ac91d8 3602 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3603 break;
3604 r = 0;
3605 break;
3606 }
3607 case KVM_SET_XSAVE: {
ff5c2c03 3608 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3609 if (IS_ERR(u.xsave))
3610 return PTR_ERR(u.xsave);
2d5b5a66 3611
d1ac91d8 3612 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3613 break;
3614 }
3615 case KVM_GET_XCRS: {
d1ac91d8 3616 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3617 r = -ENOMEM;
d1ac91d8 3618 if (!u.xcrs)
2d5b5a66
SY		 3619 break;
3620
d1ac91d8 3621 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3622
3623 r = -EFAULT;
d1ac91d8 3624 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3625 sizeof(struct kvm_xcrs)))
3626 break;
3627 r = 0;
3628 break;
3629 }
3630 case KVM_SET_XCRS: {
ff5c2c03 3631 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3632 if (IS_ERR(u.xcrs))
3633 return PTR_ERR(u.xcrs);
2d5b5a66 3634
d1ac91d8 3635 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3636 break;
3637 }
92a1f12d
JR		 3638 case KVM_SET_TSC_KHZ: {
3639 u32 user_tsc_khz;
3640
3641 r = -EINVAL;
92a1f12d
JR		 3642 user_tsc_khz = (u32)arg;
3643
3644 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3645 goto out;
3646
cc578287
ZA		 3647 if (user_tsc_khz == 0)
3648 user_tsc_khz = tsc_khz;
3649
381d585c
HZ		 3650 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3651 r = 0;
92a1f12d 3652
92a1f12d
JR		 3653 goto out;
3654 }
3655 case KVM_GET_TSC_KHZ: {
cc578287 3656 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3657 goto out;
3658 }
1c0b28c2
EM		 3659 case KVM_KVMCLOCK_CTRL: {
3660 r = kvm_set_guest_paused(vcpu);
3661 goto out;
3662 }
5c919412
AS		 3663 case KVM_ENABLE_CAP: {
3664 struct kvm_enable_cap cap;
3665
3666 r = -EFAULT;
3667 if (copy_from_user(&cap, argp, sizeof(cap)))
3668 goto out;
3669 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3670 break;
3671 }
313a3dc7
CO		 3672 default:
3673 r = -EINVAL;
3674 }
3675out:
d1ac91d8 3676 kfree(u.buffer);
313a3dc7
CO		 3677 return r;
3678}
3679
5b1c1493
CO		 3680int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3681{
3682 return VM_FAULT_SIGBUS;
3683}
3684
1fe779f8
CO		 3685static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3686{
3687 int ret;
3688
3689 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3690 return -EINVAL;
1fe779f8
CO		 3691 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3692 return ret;
3693}
3694
b927a3ce
SY		 3695static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3696 u64 ident_addr)
3697{
3698 kvm->arch.ept_identity_map_addr = ident_addr;
3699 return 0;
3700}
3701
1fe779f8
CO		 3702static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3703 u32 kvm_nr_mmu_pages)
3704{
3705 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3706 return -EINVAL;
3707
79fac95e 3708 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3709
3710 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3711 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3712
79fac95e 3713 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3714 return 0;
3715}
3716
3717static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3718{
39de71ec 3719 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3720}
3721
1fe779f8
CO		 3722static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3723{
90bca052 3724 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3725 int r;
3726
3727 r = 0;
3728 switch (chip->chip_id) {
3729 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3730 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3731 sizeof(struct kvm_pic_state));
3732 break;
3733 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3734 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 3735 sizeof(struct kvm_pic_state));
3736 break;
3737 case KVM_IRQCHIP_IOAPIC:
33392b49 3738 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3739 break;
3740 default:
3741 r = -EINVAL;
3742 break;
3743 }
3744 return r;
3745}
3746
3747static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3748{
90bca052 3749 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3750 int r;
3751
3752 r = 0;
3753 switch (chip->chip_id) {
3754 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 3755 spin_lock(&pic->lock);
3756 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 3757 sizeof(struct kvm_pic_state));
90bca052 3758 spin_unlock(&pic->lock);
1fe779f8
CO		 3759 break;
3760 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 3761 spin_lock(&pic->lock);
3762 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 3763 sizeof(struct kvm_pic_state));
90bca052 3764 spin_unlock(&pic->lock);
1fe779f8
CO		 3765 break;
3766 case KVM_IRQCHIP_IOAPIC:
33392b49 3767 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3768 break;
3769 default:
3770 r = -EINVAL;
3771 break;
3772 }
90bca052 3773 kvm_pic_update_irq(pic);
1fe779f8
CO		 3774 return r;
3775}
3776
e0f63cb9
SY		 3777static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3778{
34f3941c
RK		 3779 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3780
3781 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3782
3783 mutex_lock(&kps->lock);
3784 memcpy(ps, &kps->channels, sizeof(*ps));
3785 mutex_unlock(&kps->lock);
2da29bcc 3786 return 0;
e0f63cb9
SY		 3787}
3788
3789static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3790{
0185604c 3791 int i;
09edea72
RK		 3792 struct kvm_pit *pit = kvm->arch.vpit;
3793
3794 mutex_lock(&pit->pit_state.lock);
34f3941c 3795 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3796 for (i = 0; i < 3; i++)
09edea72
RK		 3797 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3798 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3799 return 0;
e9f42757
BK		 3800}
3801
3802static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3803{
e9f42757
BK		 3804 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3805 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3806 sizeof(ps->channels));
3807 ps->flags = kvm->arch.vpit->pit_state.flags;
3808 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3809 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3810 return 0;
e9f42757
BK		 3811}
3812
3813static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3814{
2da29bcc 3815 int start = 0;
0185604c 3816 int i;
e9f42757 3817 u32 prev_legacy, cur_legacy;
09edea72
RK		 3818 struct kvm_pit *pit = kvm->arch.vpit;
3819
3820 mutex_lock(&pit->pit_state.lock);
3821 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3822 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3823 if (!prev_legacy && cur_legacy)
3824 start = 1;
09edea72
RK		 3825 memcpy(&pit->pit_state.channels, &ps->channels,
3826 sizeof(pit->pit_state.channels));
3827 pit->pit_state.flags = ps->flags;
0185604c 3828 for (i = 0; i < 3; i++)
09edea72 3829 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3830 start && i == 0);
09edea72 3831 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3832 return 0;
e0f63cb9
SY		 3833}
3834
52d939a0
MT		 3835static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3836 struct kvm_reinject_control *control)
3837{
71474e2f
RK		 3838 struct kvm_pit *pit = kvm->arch.vpit;
3839
3840 if (!pit)
52d939a0 3841 return -ENXIO;
b39c90b6 3842
71474e2f
RK		 3843 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3844 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3845 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3846 */
3847 mutex_lock(&pit->pit_state.lock);
3848 kvm_pit_set_reinject(pit, control->pit_reinject);
3849 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3850
52d939a0
MT		 3851 return 0;
3852}
3853
95d4c16c 3854/**
60c34612
TY		 3855 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3856 * @kvm: kvm instance
3857 * @log: slot id and address to which we copy the log
95d4c16c 3858 *
e108ff2f
PB		 3859 * Steps 1-4 below provide general overview of dirty page logging. See
3860 * kvm_get_dirty_log_protect() function description for additional details.
3861 *
3862 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3863 * always flush the TLB (step 4) even if previous step failed and the dirty
3864 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3865 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3866 * writes will be marked dirty for next log read.
95d4c16c 3867 *
60c34612
TY		 3868 * 1. Take a snapshot of the bit and clear it if needed.
3869 * 2. Write protect the corresponding page.
e108ff2f
PB		 3870 * 3. Copy the snapshot to the userspace.
3871 * 4. Flush TLB's if needed.
5bb064dc 3872 */
60c34612 3873int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3874{
60c34612 3875 bool is_dirty = false;
e108ff2f 3876 int r;
5bb064dc 3877
79fac95e 3878 mutex_lock(&kvm->slots_lock);
5bb064dc 3879
88178fd4
KH		 3880 /*
3881 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3882 */
3883 if (kvm_x86_ops->flush_log_dirty)
3884 kvm_x86_ops->flush_log_dirty(kvm);
3885
e108ff2f 3886 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3887
3888 /*
3889 * All the TLBs can be flushed out of mmu lock, see the comments in
3890 * kvm_mmu_slot_remove_write_access().
3891 */
e108ff2f 3892 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3893 if (is_dirty)
3894 kvm_flush_remote_tlbs(kvm);
3895
79fac95e 3896 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3897 return r;
3898}
3899
aa2fbe6d
YZ		 3900int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3901 bool line_status)
23d43cf9
CD		 3902{
3903 if (!irqchip_in_kernel(kvm))
3904 return -ENXIO;
3905
3906 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3907 irq_event->irq, irq_event->level,
3908 line_status);
23d43cf9
CD		 3909 return 0;
3910}
3911
90de4a18
NA		 3912static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3913 struct kvm_enable_cap *cap)
3914{
3915 int r;
3916
3917 if (cap->flags)
3918 return -EINVAL;
3919
3920 switch (cap->cap) {
3921 case KVM_CAP_DISABLE_QUIRKS:
3922 kvm->arch.disabled_quirks = cap->args[0];
3923 r = 0;
3924 break;
49df6397
SR		 3925 case KVM_CAP_SPLIT_IRQCHIP: {
3926 mutex_lock(&kvm->lock);
b053b2ae
SR		 3927 r = -EINVAL;
3928 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3929 goto split_irqchip_unlock;
49df6397
SR		 3930 r = -EEXIST;
3931 if (irqchip_in_kernel(kvm))
3932 goto split_irqchip_unlock;
557abc40 3933 if (kvm->created_vcpus)
49df6397
SR		 3934 goto split_irqchip_unlock;
3935 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 3936 if (r)
49df6397
SR		 3937 goto split_irqchip_unlock;
3938 /* Pairs with irqchip_in_kernel. */
3939 smp_wmb();
49776faf 3940 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 3941 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3942 r = 0;
3943split_irqchip_unlock:
3944 mutex_unlock(&kvm->lock);
3945 break;
3946 }
37131313
RK		 3947 case KVM_CAP_X2APIC_API:
3948 r = -EINVAL;
3949 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
3950 break;
3951
3952 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
3953 kvm->arch.x2apic_format = true;
c519265f
RK		 3954 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
3955 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 3956
3957 r = 0;
3958 break;
90de4a18
NA		 3959 default:
3960 r = -EINVAL;
3961 break;
3962 }
3963 return r;
3964}
3965
1fe779f8
CO		 3966long kvm_arch_vm_ioctl(struct file *filp,
3967 unsigned int ioctl, unsigned long arg)
3968{
3969 struct kvm *kvm = filp->private_data;
3970 void __user *argp = (void __user *)arg;
367e1319 3971 int r = -ENOTTY;
f0d66275
DH		 3972 /*
3973 * This union makes it completely explicit to gcc-3.x
3974 * that these two variables' stack usage should be
3975 * combined, not added together.
3976 */
3977 union {
3978 struct kvm_pit_state ps;
e9f42757 3979 struct kvm_pit_state2 ps2;
c5ff41ce 3980 struct kvm_pit_config pit_config;
f0d66275 3981 } u;
1fe779f8
CO		 3982
3983 switch (ioctl) {
3984 case KVM_SET_TSS_ADDR:
3985 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3986 break;
b927a3ce
SY		 3987 case KVM_SET_IDENTITY_MAP_ADDR: {
3988 u64 ident_addr;
3989
3990 r = -EFAULT;
3991 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3992 goto out;
3993 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3994 break;
3995 }
1fe779f8
CO		 3996 case KVM_SET_NR_MMU_PAGES:
3997 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3998 break;
3999 case KVM_GET_NR_MMU_PAGES:
4000 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4001 break;
3ddea128 4002 case KVM_CREATE_IRQCHIP: {
3ddea128 4003 mutex_lock(&kvm->lock);
09941366 4004
3ddea128 4005 r = -EEXIST;
35e6eaa3 4006 if (irqchip_in_kernel(kvm))
3ddea128 4007 goto create_irqchip_unlock;
09941366 4008
3e515705 4009 r = -EINVAL;
557abc40 4010 if (kvm->created_vcpus)
3e515705 4011 goto create_irqchip_unlock;
09941366
RK		 4012
4013 r = kvm_pic_init(kvm);
4014 if (r)
3ddea128 4015 goto create_irqchip_unlock;
09941366
RK		 4016
4017 r = kvm_ioapic_init(kvm);
4018 if (r) {
09941366 4019 kvm_pic_destroy(kvm);
3ddea128 4020 goto create_irqchip_unlock;
09941366
RK		 4021 }
4022
399ec807
AK		 4023 r = kvm_setup_default_irq_routing(kvm);
4024 if (r) {
72bb2fcd 4025 kvm_ioapic_destroy(kvm);
09941366 4026 kvm_pic_destroy(kvm);
71ba994c 4027 goto create_irqchip_unlock;
399ec807 4028 }
49776faf 4029 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4030 smp_wmb();
49776faf 4031 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4032 create_irqchip_unlock:
4033 mutex_unlock(&kvm->lock);
1fe779f8 4034 break;
3ddea128 4035 }
7837699f 4036 case KVM_CREATE_PIT:
c5ff41ce
JK		 4037 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4038 goto create_pit;
4039 case KVM_CREATE_PIT2:
4040 r = -EFAULT;
4041 if (copy_from_user(&u.pit_config, argp,
4042 sizeof(struct kvm_pit_config)))
4043 goto out;
4044 create_pit:
250715a6 4045 mutex_lock(&kvm->lock);
269e05e4
AK		 4046 r = -EEXIST;
4047 if (kvm->arch.vpit)
4048 goto create_pit_unlock;
7837699f 4049 r = -ENOMEM;
c5ff41ce 4050 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4051 if (kvm->arch.vpit)
4052 r = 0;
269e05e4 4053 create_pit_unlock:
250715a6 4054 mutex_unlock(&kvm->lock);
7837699f 4055 break;
1fe779f8
CO		 4056 case KVM_GET_IRQCHIP: {
4057 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4058 struct kvm_irqchip *chip;
1fe779f8 4059
ff5c2c03
SL		 4060 chip = memdup_user(argp, sizeof(*chip));
4061 if (IS_ERR(chip)) {
4062 r = PTR_ERR(chip);
1fe779f8 4063 goto out;
ff5c2c03
SL		 4064 }
4065
1fe779f8 4066 r = -ENXIO;
826da321 4067 if (!irqchip_kernel(kvm))
f0d66275
DH		 4068 goto get_irqchip_out;
4069 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4070 if (r)
f0d66275 4071 goto get_irqchip_out;
1fe779f8 4072 r = -EFAULT;
f0d66275
DH		 4073 if (copy_to_user(argp, chip, sizeof *chip))
4074 goto get_irqchip_out;
1fe779f8 4075 r = 0;
f0d66275
DH		 4076 get_irqchip_out:
4077 kfree(chip);
1fe779f8
CO		 4078 break;
4079 }
4080 case KVM_SET_IRQCHIP: {
4081 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4082 struct kvm_irqchip *chip;
1fe779f8 4083
ff5c2c03
SL		 4084 chip = memdup_user(argp, sizeof(*chip));
4085 if (IS_ERR(chip)) {
4086 r = PTR_ERR(chip);
1fe779f8 4087 goto out;
ff5c2c03
SL		 4088 }
4089
1fe779f8 4090 r = -ENXIO;
826da321 4091 if (!irqchip_kernel(kvm))
f0d66275
DH		 4092 goto set_irqchip_out;
4093 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4094 if (r)
f0d66275 4095 goto set_irqchip_out;
1fe779f8 4096 r = 0;
f0d66275
DH		 4097 set_irqchip_out:
4098 kfree(chip);
1fe779f8
CO		 4099 break;
4100 }
e0f63cb9 4101 case KVM_GET_PIT: {
e0f63cb9 4102 r = -EFAULT;
f0d66275 4103 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4104 goto out;
4105 r = -ENXIO;
4106 if (!kvm->arch.vpit)
4107 goto out;
f0d66275 4108 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4109 if (r)
4110 goto out;
4111 r = -EFAULT;
f0d66275 4112 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4113 goto out;
4114 r = 0;
4115 break;
4116 }
4117 case KVM_SET_PIT: {
e0f63cb9 4118 r = -EFAULT;
f0d66275 4119 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4120 goto out;
4121 r = -ENXIO;
4122 if (!kvm->arch.vpit)
4123 goto out;
f0d66275 4124 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4125 break;
4126 }
e9f42757
BK		 4127 case KVM_GET_PIT2: {
4128 r = -ENXIO;
4129 if (!kvm->arch.vpit)
4130 goto out;
4131 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4132 if (r)
4133 goto out;
4134 r = -EFAULT;
4135 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4136 goto out;
4137 r = 0;
4138 break;
4139 }
4140 case KVM_SET_PIT2: {
4141 r = -EFAULT;
4142 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4143 goto out;
4144 r = -ENXIO;
4145 if (!kvm->arch.vpit)
4146 goto out;
4147 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4148 break;
4149 }
52d939a0
MT		 4150 case KVM_REINJECT_CONTROL: {
4151 struct kvm_reinject_control control;
4152 r = -EFAULT;
4153 if (copy_from_user(&control, argp, sizeof(control)))
4154 goto out;
4155 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4156 break;
4157 }
d71ba788
PB		 4158 case KVM_SET_BOOT_CPU_ID:
4159 r = 0;
4160 mutex_lock(&kvm->lock);
557abc40 4161 if (kvm->created_vcpus)
d71ba788
PB		 4162 r = -EBUSY;
4163 else
4164 kvm->arch.bsp_vcpu_id = arg;
4165 mutex_unlock(&kvm->lock);
4166 break;
ffde22ac
ES		 4167 case KVM_XEN_HVM_CONFIG: {
4168 r = -EFAULT;
4169 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4170 sizeof(struct kvm_xen_hvm_config)))
4171 goto out;
4172 r = -EINVAL;
4173 if (kvm->arch.xen_hvm_config.flags)
4174 goto out;
4175 r = 0;
4176 break;
4177 }
afbcf7ab 4178 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4179 struct kvm_clock_data user_ns;
4180 u64 now_ns;
afbcf7ab
GC		 4181
4182 r = -EFAULT;
4183 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4184 goto out;
4185
4186 r = -EINVAL;
4187 if (user_ns.flags)
4188 goto out;
4189
4190 r = 0;
e891a32e 4191 now_ns = get_kvmclock_ns(kvm);
108b249c 4192 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
2e762ff7 4193 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4194 break;
4195 }
4196 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4197 struct kvm_clock_data user_ns;
4198 u64 now_ns;
4199
e891a32e 4200 now_ns = get_kvmclock_ns(kvm);
108b249c 4201 user_ns.clock = now_ns;
e3fd9a93 4202 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4203 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4204
4205 r = -EFAULT;
4206 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4207 goto out;
4208 r = 0;
4209 break;
4210 }
90de4a18
NA		 4211 case KVM_ENABLE_CAP: {
4212 struct kvm_enable_cap cap;
afbcf7ab 4213
90de4a18
NA		 4214 r = -EFAULT;
4215 if (copy_from_user(&cap, argp, sizeof(cap)))
4216 goto out;
4217 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4218 break;
4219 }
1fe779f8 4220 default:
ad6260da 4221 r = -ENOTTY;
1fe779f8
CO		 4222 }
4223out:
4224 return r;
4225}
4226
a16b043c 4227static void kvm_init_msr_list(void)
043405e1
CO		 4228{
4229 u32 dummy[2];
4230 unsigned i, j;
4231
62ef68bb 4232 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4233 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4234 continue;
93c4adc7
PB		 4235
4236 /*
4237 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4238 * to the guests in some cases.
93c4adc7
PB		 4239 */
4240 switch (msrs_to_save[i]) {
4241 case MSR_IA32_BNDCFGS:
4242 if (!kvm_x86_ops->mpx_supported())
4243 continue;
4244 break;
9dbe6cf9
PB		 4245 case MSR_TSC_AUX:
4246 if (!kvm_x86_ops->rdtscp_supported())
4247 continue;
4248 break;
93c4adc7
PB		 4249 default:
4250 break;
4251 }
4252
043405e1
CO		 4253 if (j < i)
4254 msrs_to_save[j] = msrs_to_save[i];
4255 j++;
4256 }
4257 num_msrs_to_save = j;
62ef68bb
PB		 4258
4259 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4260 switch (emulated_msrs[i]) {
6d396b55
PB		 4261 case MSR_IA32_SMBASE:
4262 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4263 continue;
4264 break;
62ef68bb
PB		 4265 default:
4266 break;
4267 }
4268
4269 if (j < i)
4270 emulated_msrs[j] = emulated_msrs[i];
4271 j++;
4272 }
4273 num_emulated_msrs = j;
043405e1
CO		 4274}
4275
bda9020e
MT		 4276static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4277 const void *v)
bbd9b64e 4278{
70252a10
AK		 4279 int handled = 0;
4280 int n;
4281
4282 do {
4283 n = min(len, 8);
bce87cce 4284 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4285 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4286 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4287 break;
4288 handled += n;
4289 addr += n;
4290 len -= n;
4291 v += n;
4292 } while (len);
bbd9b64e 4293
70252a10 4294 return handled;
bbd9b64e
CO		 4295}
4296
bda9020e 4297static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4298{
70252a10
AK		 4299 int handled = 0;
4300 int n;
4301
4302 do {
4303 n = min(len, 8);
bce87cce 4304 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4305 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4306 addr, n, v))
4307 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4308 break;
4309 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4310 handled += n;
4311 addr += n;
4312 len -= n;
4313 v += n;
4314 } while (len);
bbd9b64e 4315
70252a10 4316 return handled;
bbd9b64e
CO		 4317}
4318
2dafc6c2
GN		 4319static void kvm_set_segment(struct kvm_vcpu *vcpu,
4320 struct kvm_segment *var, int seg)
4321{
4322 kvm_x86_ops->set_segment(vcpu, var, seg);
4323}
4324
4325void kvm_get_segment(struct kvm_vcpu *vcpu,
4326 struct kvm_segment *var, int seg)
4327{
4328 kvm_x86_ops->get_segment(vcpu, var, seg);
4329}
4330
54987b7a
PB		 4331gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4332 struct x86_exception *exception)
02f59dc9
JR		 4333{
4334 gpa_t t_gpa;
02f59dc9
JR		 4335
4336 BUG_ON(!mmu_is_nested(vcpu));
4337
4338 /* NPT walks are always user-walks */
4339 access |= PFERR_USER_MASK;
54987b7a 4340 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4341
4342 return t_gpa;
4343}
4344
ab9ae313
AK		 4345gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4346 struct x86_exception *exception)
1871c602
GN		 4347{
4348 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4349 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4350}
4351
ab9ae313
AK		 4352 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4353 struct x86_exception *exception)
1871c602
GN		 4354{
4355 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4356 access |= PFERR_FETCH_MASK;
ab9ae313 4357 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4358}
4359
ab9ae313
AK		 4360gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4361 struct x86_exception *exception)
1871c602
GN		 4362{
4363 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4364 access |= PFERR_WRITE_MASK;
ab9ae313 4365 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4366}
4367
4368/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4369gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4370 struct x86_exception *exception)
1871c602 4371{
ab9ae313 4372 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4373}
4374
4375static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4376 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4377 struct x86_exception *exception)
bbd9b64e
CO		 4378{
4379 void *data = val;
10589a46 4380 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4381
4382 while (bytes) {
14dfe855 4383 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4384 exception);
bbd9b64e 4385 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4386 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4387 int ret;
4388
bcc55cba 4389 if (gpa == UNMAPPED_GVA)
ab9ae313 4390 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4391 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4392 offset, toread);
10589a46 4393 if (ret < 0) {
c3cd7ffa 4394 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4395 goto out;
4396 }
bbd9b64e 4397
77c2002e
IE		 4398 bytes -= toread;
4399 data += toread;
4400 addr += toread;
bbd9b64e 4401 }
10589a46 4402out:
10589a46 4403 return r;
bbd9b64e 4404}
77c2002e 4405
1871c602 4406/* used for instruction fetching */
0f65dd70
AK		 4407static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4408 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4409 struct x86_exception *exception)
1871c602 4410{
0f65dd70 4411 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4412 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4413 unsigned offset;
4414 int ret;
0f65dd70 4415
44583cba
PB		 4416 /* Inline kvm_read_guest_virt_helper for speed. */
4417 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4418 exception);
4419 if (unlikely(gpa == UNMAPPED_GVA))
4420 return X86EMUL_PROPAGATE_FAULT;
4421
4422 offset = addr & (PAGE_SIZE-1);
4423 if (WARN_ON(offset + bytes > PAGE_SIZE))
4424 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4425 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4426 offset, bytes);
44583cba
PB		 4427 if (unlikely(ret < 0))
4428 return X86EMUL_IO_NEEDED;
4429
4430 return X86EMUL_CONTINUE;
1871c602
GN		 4431}
4432
064aea77 4433int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4434 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4435 struct x86_exception *exception)
1871c602 4436{
0f65dd70 4437 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4438 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4439
1871c602 4440 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4441 exception);
1871c602 4442}
064aea77 4443EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4444
0f65dd70
AK		 4445static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4446 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4447 struct x86_exception *exception)
1871c602 4448{
0f65dd70 4449 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4450 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4451}
4452
7a036a6f
RK		 4453static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4454 unsigned long addr, void *val, unsigned int bytes)
4455{
4456 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4457 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4458
4459 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4460}
4461
6a4d7550 4462int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4463 gva_t addr, void *val,
2dafc6c2 4464 unsigned int bytes,
bcc55cba 4465 struct x86_exception *exception)
77c2002e 4466{
0f65dd70 4467 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4468 void *data = val;
4469 int r = X86EMUL_CONTINUE;
4470
4471 while (bytes) {
14dfe855
JR		 4472 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4473 PFERR_WRITE_MASK,
ab9ae313 4474 exception);
77c2002e
IE		 4475 unsigned offset = addr & (PAGE_SIZE-1);
4476 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4477 int ret;
4478
bcc55cba 4479 if (gpa == UNMAPPED_GVA)
ab9ae313 4480 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4481 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4482 if (ret < 0) {
c3cd7ffa 4483 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4484 goto out;
4485 }
4486
4487 bytes -= towrite;
4488 data += towrite;
4489 addr += towrite;
4490 }
4491out:
4492 return r;
4493}
6a4d7550 4494EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4495
0f89b207
TL		 4496static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4497 gpa_t gpa, bool write)
4498{
4499 /* For APIC access vmexit */
4500 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4501 return 1;
4502
4503 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4504 trace_vcpu_match_mmio(gva, gpa, write, true);
4505 return 1;
4506 }
4507
4508 return 0;
4509}
4510
af7cc7d1
XG		 4511static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4512 gpa_t *gpa, struct x86_exception *exception,
4513 bool write)
4514{
97d64b78
AK		 4515 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4516 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4517
be94f6b7
HH		 4518 /*
4519 * currently PKRU is only applied to ept enabled guest so
4520 * there is no pkey in EPT page table for L1 guest or EPT
4521 * shadow page table for L2 guest.
4522 */
97d64b78 4523 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4524 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4525 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4526 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4527 (gva & (PAGE_SIZE - 1));
4f022648 4528 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4529 return 1;
4530 }
4531
af7cc7d1
XG		 4532 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4533
4534 if (*gpa == UNMAPPED_GVA)
4535 return -1;
4536
0f89b207 4537 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4538}
4539
3200f405 4540int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4541 const void *val, int bytes)
bbd9b64e
CO		 4542{
4543 int ret;
4544
54bf36aa 4545 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4546 if (ret < 0)
bbd9b64e 4547 return 0;
0eb05bf2 4548 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4549 return 1;
4550}
4551
77d197b2
XG		 4552struct read_write_emulator_ops {
4553 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4554 int bytes);
4555 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4556 void *val, int bytes);
4557 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4558 int bytes, void *val);
4559 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4560 void *val, int bytes);
4561 bool write;
4562};
4563
4564static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4565{
4566 if (vcpu->mmio_read_completed) {
77d197b2 4567 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4568 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4569 vcpu->mmio_read_completed = 0;
4570 return 1;
4571 }
4572
4573 return 0;
4574}
4575
4576static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4577 void *val, int bytes)
4578{
54bf36aa 4579 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4580}
4581
4582static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4583 void *val, int bytes)
4584{
4585 return emulator_write_phys(vcpu, gpa, val, bytes);
4586}
4587
4588static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4589{
4590 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4591 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4592}
4593
4594static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4595 void *val, int bytes)
4596{
4597 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4598 return X86EMUL_IO_NEEDED;
4599}
4600
4601static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4602 void *val, int bytes)
4603{
f78146b0
AK		 4604 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4605
87da7e66 4606 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4607 return X86EMUL_CONTINUE;
4608}
4609
0fbe9b0b 4610static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4611 .read_write_prepare = read_prepare,
4612 .read_write_emulate = read_emulate,
4613 .read_write_mmio = vcpu_mmio_read,
4614 .read_write_exit_mmio = read_exit_mmio,
4615};
4616
0fbe9b0b 4617static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4618 .read_write_emulate = write_emulate,
4619 .read_write_mmio = write_mmio,
4620 .read_write_exit_mmio = write_exit_mmio,
4621 .write = true,
4622};
4623
22388a3c
XG		 4624static int emulator_read_write_onepage(unsigned long addr, void *val,
4625 unsigned int bytes,
4626 struct x86_exception *exception,
4627 struct kvm_vcpu *vcpu,
0fbe9b0b 4628 const struct read_write_emulator_ops *ops)
bbd9b64e 4629{
af7cc7d1
XG		 4630 gpa_t gpa;
4631 int handled, ret;
22388a3c 4632 bool write = ops->write;
f78146b0 4633 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4634 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4635
4636 /*
4637 * If the exit was due to a NPF we may already have a GPA.
4638 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4639 * Note, this cannot be used on string operations since string
4640 * operation using rep will only have the initial GPA from the NPF
4641 * occurred.
4642 */
4643 if (vcpu->arch.gpa_available &&
4644 emulator_can_use_gpa(ctxt) &&
4645 vcpu_is_mmio_gpa(vcpu, addr, exception->address, write) &&
4646 (addr & ~PAGE_MASK) == (exception->address & ~PAGE_MASK)) {
4647 gpa = exception->address;
4648 goto mmio;
4649 }
10589a46 4650
22388a3c 4651 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4652
af7cc7d1 4653 if (ret < 0)
bbd9b64e 4654 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4655
4656 /* For APIC access vmexit */
af7cc7d1 4657 if (ret)
bbd9b64e
CO		 4658 goto mmio;
4659
22388a3c 4660 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4661 return X86EMUL_CONTINUE;
4662
4663mmio:
4664 /*
4665 * Is this MMIO handled locally?
4666 */
22388a3c 4667 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4668 if (handled == bytes)
bbd9b64e 4669 return X86EMUL_CONTINUE;
bbd9b64e 4670
70252a10
AK		 4671 gpa += handled;
4672 bytes -= handled;
4673 val += handled;
4674
87da7e66
XG		 4675 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4676 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4677 frag->gpa = gpa;
4678 frag->data = val;
4679 frag->len = bytes;
f78146b0 4680 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4681}
4682
52eb5a6d
XL		 4683static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4684 unsigned long addr,
22388a3c
XG		 4685 void *val, unsigned int bytes,
4686 struct x86_exception *exception,
0fbe9b0b 4687 const struct read_write_emulator_ops *ops)
bbd9b64e 4688{
0f65dd70 4689 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4690 gpa_t gpa;
4691 int rc;
4692
4693 if (ops->read_write_prepare &&
4694 ops->read_write_prepare(vcpu, val, bytes))
4695 return X86EMUL_CONTINUE;
4696
4697 vcpu->mmio_nr_fragments = 0;
0f65dd70 4698
bbd9b64e
CO		 4699 /* Crossing a page boundary? */
4700 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4701 int now;
bbd9b64e
CO		 4702
4703 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4704 rc = emulator_read_write_onepage(addr, val, now, exception,
4705 vcpu, ops);
4706
bbd9b64e
CO		 4707 if (rc != X86EMUL_CONTINUE)
4708 return rc;
4709 addr += now;
bac15531
NA		 4710 if (ctxt->mode != X86EMUL_MODE_PROT64)
4711 addr = (u32)addr;
bbd9b64e
CO		 4712 val += now;
4713 bytes -= now;
4714 }
22388a3c 4715
f78146b0
AK		 4716 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4717 vcpu, ops);
4718 if (rc != X86EMUL_CONTINUE)
4719 return rc;
4720
4721 if (!vcpu->mmio_nr_fragments)
4722 return rc;
4723
4724 gpa = vcpu->mmio_fragments[0].gpa;
4725
4726 vcpu->mmio_needed = 1;
4727 vcpu->mmio_cur_fragment = 0;
4728
87da7e66 4729 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4730 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4731 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4732 vcpu->run->mmio.phys_addr = gpa;
4733
4734 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4735}
4736
4737static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4738 unsigned long addr,
4739 void *val,
4740 unsigned int bytes,
4741 struct x86_exception *exception)
4742{
4743 return emulator_read_write(ctxt, addr, val, bytes,
4744 exception, &read_emultor);
4745}
4746
52eb5a6d 4747static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4748 unsigned long addr,
4749 const void *val,
4750 unsigned int bytes,
4751 struct x86_exception *exception)
4752{
4753 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4754 exception, &write_emultor);
bbd9b64e 4755}
bbd9b64e 4756
daea3e73
AK		 4757#define CMPXCHG_TYPE(t, ptr, old, new) \
4758 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4759
4760#ifdef CONFIG_X86_64
4761# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4762#else
4763# define CMPXCHG64(ptr, old, new) \
9749a6c0 4764 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4765#endif
4766
0f65dd70
AK		 4767static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4768 unsigned long addr,
bbd9b64e
CO		 4769 const void *old,
4770 const void *new,
4771 unsigned int bytes,
0f65dd70 4772 struct x86_exception *exception)
bbd9b64e 4773{
0f65dd70 4774 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4775 gpa_t gpa;
4776 struct page *page;
4777 char *kaddr;
4778 bool exchanged;
2bacc55c 4779
daea3e73
AK		 4780 /* guests cmpxchg8b have to be emulated atomically */
4781 if (bytes > 8 || (bytes & (bytes - 1)))
4782 goto emul_write;
10589a46 4783
daea3e73 4784 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4785
daea3e73
AK		 4786 if (gpa == UNMAPPED_GVA ||
4787 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4788 goto emul_write;
2bacc55c 4789
daea3e73
AK		 4790 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4791 goto emul_write;
72dc67a6 4792
54bf36aa 4793 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4794 if (is_error_page(page))
c19b8bd6 4795 goto emul_write;
72dc67a6 4796
8fd75e12 4797 kaddr = kmap_atomic(page);
daea3e73
AK		 4798 kaddr += offset_in_page(gpa);
4799 switch (bytes) {
4800 case 1:
4801 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4802 break;
4803 case 2:
4804 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4805 break;
4806 case 4:
4807 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4808 break;
4809 case 8:
4810 exchanged = CMPXCHG64(kaddr, old, new);
4811 break;
4812 default:
4813 BUG();
2bacc55c 4814 }
8fd75e12 4815 kunmap_atomic(kaddr);
daea3e73
AK		 4816 kvm_release_page_dirty(page);
4817
4818 if (!exchanged)
4819 return X86EMUL_CMPXCHG_FAILED;
4820
54bf36aa 4821 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4822 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4823
4824 return X86EMUL_CONTINUE;
4a5f48f6 4825
3200f405 4826emul_write:
daea3e73 4827 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4828
0f65dd70 4829 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4830}
4831
cf8f70bf
GN		 4832static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4833{
4834 /* TODO: String I/O for in kernel device */
4835 int r;
4836
4837 if (vcpu->arch.pio.in)
e32edf4f 4838 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4839 vcpu->arch.pio.size, pd);
4840 else
e32edf4f 4841 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4842 vcpu->arch.pio.port, vcpu->arch.pio.size,
4843 pd);
4844 return r;
4845}
4846
6f6fbe98
XG		 4847static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4848 unsigned short port, void *val,
4849 unsigned int count, bool in)
cf8f70bf 4850{
cf8f70bf 4851 vcpu->arch.pio.port = port;
6f6fbe98 4852 vcpu->arch.pio.in = in;
7972995b 4853 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4854 vcpu->arch.pio.size = size;
4855
4856 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4857 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4858 return 1;
4859 }
4860
4861 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4862 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4863 vcpu->run->io.size = size;
4864 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4865 vcpu->run->io.count = count;
4866 vcpu->run->io.port = port;
4867
4868 return 0;
4869}
4870
6f6fbe98
XG		 4871static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4872 int size, unsigned short port, void *val,
4873 unsigned int count)
cf8f70bf 4874{
ca1d4a9e 4875 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4876 int ret;
ca1d4a9e 4877
6f6fbe98
XG		 4878 if (vcpu->arch.pio.count)
4879 goto data_avail;
cf8f70bf 4880
6f6fbe98
XG		 4881 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4882 if (ret) {
4883data_avail:
4884 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4885 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4886 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4887 return 1;
4888 }
4889
cf8f70bf
GN		 4890 return 0;
4891}
4892
6f6fbe98
XG		 4893static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4894 int size, unsigned short port,
4895 const void *val, unsigned int count)
4896{
4897 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4898
4899 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4900 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4901 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4902}
4903
bbd9b64e
CO		 4904static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4905{
4906 return kvm_x86_ops->get_segment_base(vcpu, seg);
4907}
4908
3cb16fe7 4909static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4910{
3cb16fe7 4911 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4912}
4913
ae6a2375 4914static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4915{
4916 if (!need_emulate_wbinvd(vcpu))
4917 return X86EMUL_CONTINUE;
4918
4919 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4920 int cpu = get_cpu();
4921
4922 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4923 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4924 wbinvd_ipi, NULL, 1);
2eec7343 4925 put_cpu();
f5f48ee1 4926 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4927 } else
4928 wbinvd();
f5f48ee1
SY		 4929 return X86EMUL_CONTINUE;
4930}
5cb56059
JS		 4931
4932int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4933{
6affcbed
KH		 4934 kvm_emulate_wbinvd_noskip(vcpu);
4935 return kvm_skip_emulated_instruction(vcpu);
5cb56059 4936}
f5f48ee1
SY		 4937EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4938
5cb56059
JS		 4939
4940
bcaf5cc5
AK		 4941static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4942{
5cb56059 4943 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4944}
4945
52eb5a6d
XL		 4946static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4947 unsigned long *dest)
bbd9b64e 4948{
16f8a6f9 4949 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4950}
4951
52eb5a6d
XL		 4952static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4953 unsigned long value)
bbd9b64e 4954{
338dbc97 4955
717746e3 4956 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4957}
4958
52a46617 4959static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4960{
52a46617 4961 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4962}
4963
717746e3 4964static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4965{
717746e3 4966 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4967 unsigned long value;
4968
4969 switch (cr) {
4970 case 0:
4971 value = kvm_read_cr0(vcpu);
4972 break;
4973 case 2:
4974 value = vcpu->arch.cr2;
4975 break;
4976 case 3:
9f8fe504 4977 value = kvm_read_cr3(vcpu);
52a46617
GN		 4978 break;
4979 case 4:
4980 value = kvm_read_cr4(vcpu);
4981 break;
4982 case 8:
4983 value = kvm_get_cr8(vcpu);
4984 break;
4985 default:
a737f256 4986 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4987 return 0;
4988 }
4989
4990 return value;
4991}
4992
717746e3 4993static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4994{
717746e3 4995 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4996 int res = 0;
4997
52a46617
GN		 4998 switch (cr) {
4999 case 0:
49a9b07e 5000 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5001 break;
5002 case 2:
5003 vcpu->arch.cr2 = val;
5004 break;
5005 case 3:
2390218b 5006 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5007 break;
5008 case 4:
a83b29c6 5009 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5010 break;
5011 case 8:
eea1cff9 5012 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5013 break;
5014 default:
a737f256 5015 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5016 res = -1;
52a46617 5017 }
0f12244f
GN		 5018
5019 return res;
52a46617
GN		 5020}
5021
717746e3 5022static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5023{
717746e3 5024 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5025}
5026
4bff1e86 5027static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5028{
4bff1e86 5029 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5030}
5031
4bff1e86 5032static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5033{
4bff1e86 5034 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5035}
5036
1ac9d0cf
AK		 5037static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5038{
5039 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5040}
5041
5042static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5043{
5044 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5045}
5046
4bff1e86
AK		 5047static unsigned long emulator_get_cached_segment_base(
5048 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5049{
4bff1e86 5050 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5051}
5052
1aa36616
AK		 5053static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5054 struct desc_struct *desc, u32 *base3,
5055 int seg)
2dafc6c2
GN		 5056{
5057 struct kvm_segment var;
5058
4bff1e86 5059 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5060 *selector = var.selector;
2dafc6c2 5061
378a8b09
GN		 5062 if (var.unusable) {
5063 memset(desc, 0, sizeof(*desc));
2dafc6c2 5064 return false;
378a8b09 5065 }
2dafc6c2
GN		 5066
5067 if (var.g)
5068 var.limit >>= 12;
5069 set_desc_limit(desc, var.limit);
5070 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5071#ifdef CONFIG_X86_64
5072 if (base3)
5073 *base3 = var.base >> 32;
5074#endif
2dafc6c2
GN		 5075 desc->type = var.type;
5076 desc->s = var.s;
5077 desc->dpl = var.dpl;
5078 desc->p = var.present;
5079 desc->avl = var.avl;
5080 desc->l = var.l;
5081 desc->d = var.db;
5082 desc->g = var.g;
5083
5084 return true;
5085}
5086
1aa36616
AK		 5087static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5088 struct desc_struct *desc, u32 base3,
5089 int seg)
2dafc6c2 5090{
4bff1e86 5091 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5092 struct kvm_segment var;
5093
1aa36616 5094 var.selector = selector;
2dafc6c2 5095 var.base = get_desc_base(desc);
5601d05b
GN		 5096#ifdef CONFIG_X86_64
5097 var.base |= ((u64)base3) << 32;
5098#endif
2dafc6c2
GN		 5099 var.limit = get_desc_limit(desc);
5100 if (desc->g)
5101 var.limit = (var.limit << 12) | 0xfff;
5102 var.type = desc->type;
2dafc6c2
GN		 5103 var.dpl = desc->dpl;
5104 var.db = desc->d;
5105 var.s = desc->s;
5106 var.l = desc->l;
5107 var.g = desc->g;
5108 var.avl = desc->avl;
5109 var.present = desc->p;
5110 var.unusable = !var.present;
5111 var.padding = 0;
5112
5113 kvm_set_segment(vcpu, &var, seg);
5114 return;
5115}
5116
717746e3
AK		 5117static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5118 u32 msr_index, u64 *pdata)
5119{
609e36d3
PB		 5120 struct msr_data msr;
5121 int r;
5122
5123 msr.index = msr_index;
5124 msr.host_initiated = false;
5125 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5126 if (r)
5127 return r;
5128
5129 *pdata = msr.data;
5130 return 0;
717746e3
AK		 5131}
5132
5133static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5134 u32 msr_index, u64 data)
5135{
8fe8ab46
WA		 5136 struct msr_data msr;
5137
5138 msr.data = data;
5139 msr.index = msr_index;
5140 msr.host_initiated = false;
5141 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5142}
5143
64d60670
PB		 5144static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5145{
5146 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5147
5148 return vcpu->arch.smbase;
5149}
5150
5151static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5152{
5153 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5154
5155 vcpu->arch.smbase = smbase;
5156}
5157
67f4d428
NA		 5158static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5159 u32 pmc)
5160{
c6702c9d 5161 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5162}
5163
222d21aa
AK		 5164static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5165 u32 pmc, u64 *pdata)
5166{
c6702c9d 5167 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5168}
5169
6c3287f7
AK		 5170static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5171{
5172 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5173}
5174
5037f6f3
AK		 5175static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5176{
5177 preempt_disable();
5197b808 5178 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5179}
5180
5181static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5182{
5183 preempt_enable();
5184}
5185
2953538e 5186static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5187 struct x86_instruction_info *info,
c4f035c6
AK		 5188 enum x86_intercept_stage stage)
5189{
2953538e 5190 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5191}
5192
0017f93a 5193static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5194 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5195{
0017f93a 5196 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5197}
5198
dd856efa
AK		 5199static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5200{
5201 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5202}
5203
5204static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5205{
5206 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5207}
5208
801806d9
NA		 5209static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5210{
5211 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5212}
5213
6ed071f0
LP		 5214static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5215{
5216 return emul_to_vcpu(ctxt)->arch.hflags;
5217}
5218
5219static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5220{
5221 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5222}
5223
0225fb50 5224static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5225 .read_gpr = emulator_read_gpr,
5226 .write_gpr = emulator_write_gpr,
1871c602 5227 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5228 .write_std = kvm_write_guest_virt_system,
7a036a6f 5229 .read_phys = kvm_read_guest_phys_system,
1871c602 5230 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5231 .read_emulated = emulator_read_emulated,
5232 .write_emulated = emulator_write_emulated,
5233 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5234 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5235 .pio_in_emulated = emulator_pio_in_emulated,
5236 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5237 .get_segment = emulator_get_segment,
5238 .set_segment = emulator_set_segment,
5951c442 5239 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5240 .get_gdt = emulator_get_gdt,
160ce1f1 5241 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5242 .set_gdt = emulator_set_gdt,
5243 .set_idt = emulator_set_idt,
52a46617
GN		 5244 .get_cr = emulator_get_cr,
5245 .set_cr = emulator_set_cr,
9c537244 5246 .cpl = emulator_get_cpl,
35aa5375
GN		 5247 .get_dr = emulator_get_dr,
5248 .set_dr = emulator_set_dr,
64d60670
PB		 5249 .get_smbase = emulator_get_smbase,
5250 .set_smbase = emulator_set_smbase,
717746e3
AK		 5251 .set_msr = emulator_set_msr,
5252 .get_msr = emulator_get_msr,
67f4d428 5253 .check_pmc = emulator_check_pmc,
222d21aa 5254 .read_pmc = emulator_read_pmc,
6c3287f7 5255 .halt = emulator_halt,
bcaf5cc5 5256 .wbinvd = emulator_wbinvd,
d6aa1000 5257 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5258 .get_fpu = emulator_get_fpu,
5259 .put_fpu = emulator_put_fpu,
c4f035c6 5260 .intercept = emulator_intercept,
bdb42f5a 5261 .get_cpuid = emulator_get_cpuid,
801806d9 5262 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5263 .get_hflags = emulator_get_hflags,
5264 .set_hflags = emulator_set_hflags,
bbd9b64e
CO		 5265};
5266
95cb2295
GN		 5267static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5268{
37ccdcbe 5269 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5270 /*
5271 * an sti; sti; sequence only disable interrupts for the first
5272 * instruction. So, if the last instruction, be it emulated or
5273 * not, left the system with the INT_STI flag enabled, it
5274 * means that the last instruction is an sti. We should not
5275 * leave the flag on in this case. The same goes for mov ss
5276 */
37ccdcbe
PB		 5277 if (int_shadow & mask)
5278 mask = 0;
6addfc42 5279 if (unlikely(int_shadow || mask)) {
95cb2295 5280 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5281 if (!mask)
5282 kvm_make_request(KVM_REQ_EVENT, vcpu);
5283 }
95cb2295
GN		 5284}
5285
ef54bcfe 5286static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5287{
5288 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5289 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5290 return kvm_propagate_fault(vcpu, &ctxt->exception);
5291
5292 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5293 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5294 ctxt->exception.error_code);
54b8486f 5295 else
da9cb575 5296 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5297 return false;
54b8486f
GN		 5298}
5299
8ec4722d
MG		 5300static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5301{
adf52235 5302 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5303 int cs_db, cs_l;
5304
8ec4722d
MG		 5305 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5306
adf52235
TY		 5307 ctxt->eflags = kvm_get_rflags(vcpu);
5308 ctxt->eip = kvm_rip_read(vcpu);
5309 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5310 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5311 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5312 cs_db ? X86EMUL_MODE_PROT32 :
5313 X86EMUL_MODE_PROT16;
a584539b 5314 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5315 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5316 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5317
dd856efa 5318 init_decode_cache(ctxt);
7ae441ea 5319 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5320}
5321
71f9833b 5322int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5323{
9d74191a 5324 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5325 int ret;
5326
5327 init_emulate_ctxt(vcpu);
5328
9dac77fa
AK		 5329 ctxt->op_bytes = 2;
5330 ctxt->ad_bytes = 2;
5331 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5332 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5333
5334 if (ret != X86EMUL_CONTINUE)
5335 return EMULATE_FAIL;
5336
9dac77fa 5337 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5338 kvm_rip_write(vcpu, ctxt->eip);
5339 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5340
5341 if (irq == NMI_VECTOR)
7460fb4a 5342 vcpu->arch.nmi_pending = 0;
63995653
MG		 5343 else
5344 vcpu->arch.interrupt.pending = false;
5345
5346 return EMULATE_DONE;
5347}
5348EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5349
6d77dbfc
GN		 5350static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5351{
fc3a9157
JR		 5352 int r = EMULATE_DONE;
5353
6d77dbfc
GN		 5354 ++vcpu->stat.insn_emulation_fail;
5355 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5356 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5357 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5358 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5359 vcpu->run->internal.ndata = 0;
5360 r = EMULATE_FAIL;
5361 }
6d77dbfc 5362 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5363
5364 return r;
6d77dbfc
GN		 5365}
5366
93c05d3e 5367static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5368 bool write_fault_to_shadow_pgtable,
5369 int emulation_type)
a6f177ef 5370{
95b3cf69 5371 gpa_t gpa = cr2;
ba049e93 5372 kvm_pfn_t pfn;
a6f177ef 5373
991eebf9
GN		 5374 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5375 return false;
5376
95b3cf69
XG		 5377 if (!vcpu->arch.mmu.direct_map) {
5378 /*
5379 * Write permission should be allowed since only
5380 * write access need to be emulated.
5381 */
5382 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5383
95b3cf69
XG		 5384 /*
5385 * If the mapping is invalid in guest, let cpu retry
5386 * it to generate fault.
5387 */
5388 if (gpa == UNMAPPED_GVA)
5389 return true;
5390 }
a6f177ef 5391
8e3d9d06
XG		 5392 /*
5393 * Do not retry the unhandleable instruction if it faults on the
5394 * readonly host memory, otherwise it will goto a infinite loop:
5395 * retry instruction -> write #PF -> emulation fail -> retry
5396 * instruction -> ...
5397 */
5398 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5399
5400 /*
5401 * If the instruction failed on the error pfn, it can not be fixed,
5402 * report the error to userspace.
5403 */
5404 if (is_error_noslot_pfn(pfn))
5405 return false;
5406
5407 kvm_release_pfn_clean(pfn);
5408
5409 /* The instructions are well-emulated on direct mmu. */
5410 if (vcpu->arch.mmu.direct_map) {
5411 unsigned int indirect_shadow_pages;
5412
5413 spin_lock(&vcpu->kvm->mmu_lock);
5414 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5415 spin_unlock(&vcpu->kvm->mmu_lock);
5416
5417 if (indirect_shadow_pages)
5418 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5419
a6f177ef 5420 return true;
8e3d9d06 5421 }
a6f177ef 5422
95b3cf69
XG		 5423 /*
5424 * if emulation was due to access to shadowed page table
5425 * and it failed try to unshadow page and re-enter the
5426 * guest to let CPU execute the instruction.
5427 */
5428 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5429
5430 /*
5431 * If the access faults on its page table, it can not
5432 * be fixed by unprotecting shadow page and it should
5433 * be reported to userspace.
5434 */
5435 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5436}
5437
1cb3f3ae
XG		 5438static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5439 unsigned long cr2, int emulation_type)
5440{
5441 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5442 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5443
5444 last_retry_eip = vcpu->arch.last_retry_eip;
5445 last_retry_addr = vcpu->arch.last_retry_addr;
5446
5447 /*
5448 * If the emulation is caused by #PF and it is non-page_table
5449 * writing instruction, it means the VM-EXIT is caused by shadow
5450 * page protected, we can zap the shadow page and retry this
5451 * instruction directly.
5452 *
5453 * Note: if the guest uses a non-page-table modifying instruction
5454 * on the PDE that points to the instruction, then we will unmap
5455 * the instruction and go to an infinite loop. So, we cache the
5456 * last retried eip and the last fault address, if we meet the eip
5457 * and the address again, we can break out of the potential infinite
5458 * loop.
5459 */
5460 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5461
5462 if (!(emulation_type & EMULTYPE_RETRY))
5463 return false;
5464
5465 if (x86_page_table_writing_insn(ctxt))
5466 return false;
5467
5468 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5469 return false;
5470
5471 vcpu->arch.last_retry_eip = ctxt->eip;
5472 vcpu->arch.last_retry_addr = cr2;
5473
5474 if (!vcpu->arch.mmu.direct_map)
5475 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5476
22368028 5477 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5478
5479 return true;
5480}
5481
716d51ab
GN		 5482static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5483static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5484
64d60670 5485static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5486{
64d60670 5487 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5488 /* This is a good place to trace that we are exiting SMM. */
5489 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5490
c43203ca
PB		 5491 /* Process a latched INIT or SMI, if any. */
5492 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5493 }
699023e2
PB		 5494
5495 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5496}
5497
5498static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5499{
5500 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5501
a584539b 5502 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5503
5504 if (changed & HF_SMM_MASK)
5505 kvm_smm_changed(vcpu);
a584539b
PB		 5506}
5507
4a1e10d5
PB		 5508static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5509 unsigned long *db)
5510{
5511 u32 dr6 = 0;
5512 int i;
5513 u32 enable, rwlen;
5514
5515 enable = dr7;
5516 rwlen = dr7 >> 16;
5517 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5518 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5519 dr6 |= (1 << i);
5520 return dr6;
5521}
5522
6addfc42 5523static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5524{
5525 struct kvm_run *kvm_run = vcpu->run;
5526
5527 /*
6addfc42
PB		 5528 * rflags is the old, "raw" value of the flags. The new value has
5529 * not been saved yet.
663f4c61
PB		 5530 *
5531 * This is correct even for TF set by the guest, because "the
5532 * processor will not generate this exception after the instruction
5533 * that sets the TF flag".
5534 */
663f4c61
PB		 5535 if (unlikely(rflags & X86_EFLAGS_TF)) {
5536 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5537 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5538 DR6_RTM;
663f4c61
PB		 5539 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5540 kvm_run->debug.arch.exception = DB_VECTOR;
5541 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5542 *r = EMULATE_USER_EXIT;
5543 } else {
663f4c61
PB		 5544 /*
5545 * "Certain debug exceptions may clear bit 0-3. The
5546 * remaining contents of the DR6 register are never
5547 * cleared by the processor".
5548 */
5549 vcpu->arch.dr6 &= ~15;
6f43ed01 5550 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5551 kvm_queue_exception(vcpu, DB_VECTOR);
5552 }
5553 }
5554}
5555
6affcbed
KH		 5556int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5557{
5558 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5559 int r = EMULATE_DONE;
5560
5561 kvm_x86_ops->skip_emulated_instruction(vcpu);
5562 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5563 return r == EMULATE_DONE;
5564}
5565EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5566
4a1e10d5
PB		 5567static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5568{
4a1e10d5
PB		 5569 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5570 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5571 struct kvm_run *kvm_run = vcpu->run;
5572 unsigned long eip = kvm_get_linear_rip(vcpu);
5573 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5574 vcpu->arch.guest_debug_dr7,
5575 vcpu->arch.eff_db);
5576
5577 if (dr6 != 0) {
6f43ed01 5578 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5579 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5580 kvm_run->debug.arch.exception = DB_VECTOR;
5581 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5582 *r = EMULATE_USER_EXIT;
5583 return true;
5584 }
5585 }
5586
4161a569
NA		 5587 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5588 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5589 unsigned long eip = kvm_get_linear_rip(vcpu);
5590 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5591 vcpu->arch.dr7,
5592 vcpu->arch.db);
5593
5594 if (dr6 != 0) {
5595 vcpu->arch.dr6 &= ~15;
6f43ed01 5596 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5597 kvm_queue_exception(vcpu, DB_VECTOR);
5598 *r = EMULATE_DONE;
5599 return true;
5600 }
5601 }
5602
5603 return false;
5604}
5605
51d8b661
AP		 5606int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5607 unsigned long cr2,
dc25e89e
AP		 5608 int emulation_type,
5609 void *insn,
5610 int insn_len)
bbd9b64e 5611{
95cb2295 5612 int r;
9d74191a 5613 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5614 bool writeback = true;
93c05d3e 5615 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5616
93c05d3e
XG		 5617 /*
5618 * Clear write_fault_to_shadow_pgtable here to ensure it is
5619 * never reused.
5620 */
5621 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5622 kvm_clear_exception_queue(vcpu);
8d7d8102 5623
571008da 5624 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5625 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5626
5627 /*
5628 * We will reenter on the same instruction since
5629 * we do not set complete_userspace_io. This does not
5630 * handle watchpoints yet, those would be handled in
5631 * the emulate_ops.
5632 */
5633 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5634 return r;
5635
9d74191a
TY		 5636 ctxt->interruptibility = 0;
5637 ctxt->have_exception = false;
e0ad0b47 5638 ctxt->exception.vector = -1;
9d74191a 5639 ctxt->perm_ok = false;
bbd9b64e 5640
b51e974f 5641 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5642
9d74191a 5643 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5644
e46479f8 5645 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5646 ++vcpu->stat.insn_emulation;
1d2887e2 5647 if (r != EMULATION_OK) {
4005996e
AK		 5648 if (emulation_type & EMULTYPE_TRAP_UD)
5649 return EMULATE_FAIL;
991eebf9
GN		 5650 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5651 emulation_type))
bbd9b64e 5652 return EMULATE_DONE;
6d77dbfc
GN		 5653 if (emulation_type & EMULTYPE_SKIP)
5654 return EMULATE_FAIL;
5655 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5656 }
5657 }
5658
ba8afb6b 5659 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5660 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5661 if (ctxt->eflags & X86_EFLAGS_RF)
5662 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5663 return EMULATE_DONE;
5664 }
5665
1cb3f3ae
XG		 5666 if (retry_instruction(ctxt, cr2, emulation_type))
5667 return EMULATE_DONE;
5668
7ae441ea 5669 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5670 changes registers values during IO operation */
7ae441ea
GN		 5671 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5672 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5673 emulator_invalidate_register_cache(ctxt);
7ae441ea 5674 }
4d2179e1 5675
5cd21917 5676restart:
0f89b207
TL		 5677 /* Save the faulting GPA (cr2) in the address field */
5678 ctxt->exception.address = cr2;
5679
9d74191a 5680 r = x86_emulate_insn(ctxt);
bbd9b64e 5681
775fde86
JR		 5682 if (r == EMULATION_INTERCEPTED)
5683 return EMULATE_DONE;
5684
d2ddd1c4 5685 if (r == EMULATION_FAILED) {
991eebf9
GN		 5686 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5687 emulation_type))
c3cd7ffa
GN		 5688 return EMULATE_DONE;
5689
6d77dbfc 5690 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5691 }
5692
9d74191a 5693 if (ctxt->have_exception) {
d2ddd1c4 5694 r = EMULATE_DONE;
ef54bcfe
PB		 5695 if (inject_emulated_exception(vcpu))
5696 return r;
d2ddd1c4 5697 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5698 if (!vcpu->arch.pio.in) {
5699 /* FIXME: return into emulator if single-stepping. */
3457e419 5700 vcpu->arch.pio.count = 0;
0912c977 5701 } else {
7ae441ea 5702 writeback = false;
716d51ab
GN		 5703 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5704 }
ac0a48c3 5705 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5706 } else if (vcpu->mmio_needed) {
5707 if (!vcpu->mmio_is_write)
5708 writeback = false;
ac0a48c3 5709 r = EMULATE_USER_EXIT;
716d51ab 5710 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5711 } else if (r == EMULATION_RESTART)
5cd21917 5712 goto restart;
d2ddd1c4
GN		 5713 else
5714 r = EMULATE_DONE;
f850e2e6 5715
7ae441ea 5716 if (writeback) {
6addfc42 5717 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5718 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5719 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5720 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5721 if (r == EMULATE_DONE)
6addfc42 5722 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5723 if (!ctxt->have_exception ||
5724 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5725 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5726
5727 /*
5728 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5729 * do nothing, and it will be requested again as soon as
5730 * the shadow expires. But we still need to check here,
5731 * because POPF has no interrupt shadow.
5732 */
5733 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5734 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5735 } else
5736 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5737
5738 return r;
de7d789a 5739}
51d8b661 5740EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5741
cf8f70bf 5742int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5743{
cf8f70bf 5744 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5745 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5746 size, port, &val, 1);
cf8f70bf 5747 /* do not return to emulator after return from userspace */
7972995b 5748 vcpu->arch.pio.count = 0;
de7d789a
CO		 5749 return ret;
5750}
cf8f70bf 5751EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5752
8370c3d0
TL		 5753static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5754{
5755 unsigned long val;
5756
5757 /* We should only ever be called with arch.pio.count equal to 1 */
5758 BUG_ON(vcpu->arch.pio.count != 1);
5759
5760 /* For size less than 4 we merge, else we zero extend */
5761 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5762 : 0;
5763
5764 /*
5765 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5766 * the copy and tracing
5767 */
5768 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5769 vcpu->arch.pio.port, &val, 1);
5770 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5771
5772 return 1;
5773}
5774
5775int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5776{
5777 unsigned long val;
5778 int ret;
5779
5780 /* For size less than 4 we merge, else we zero extend */
5781 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5782
5783 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5784 &val, 1);
5785 if (ret) {
5786 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5787 return ret;
5788 }
5789
5790 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5791
5792 return 0;
5793}
5794EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5795
251a5fd6 5796static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5797{
0a3aee0d 5798 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5799 return 0;
8cfdc000
ZA		 5800}
5801
5802static void tsc_khz_changed(void *data)
c8076604 5803{
8cfdc000
ZA		 5804 struct cpufreq_freqs *freq = data;
5805 unsigned long khz = 0;
5806
5807 if (data)
5808 khz = freq->new;
5809 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5810 khz = cpufreq_quick_get(raw_smp_processor_id());
5811 if (!khz)
5812 khz = tsc_khz;
0a3aee0d 5813 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5814}
5815
c8076604
GH		 5816static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5817 void *data)
5818{
5819 struct cpufreq_freqs *freq = data;
5820 struct kvm *kvm;
5821 struct kvm_vcpu *vcpu;
5822 int i, send_ipi = 0;
5823
8cfdc000
ZA		 5824 /*
5825 * We allow guests to temporarily run on slowing clocks,
5826 * provided we notify them after, or to run on accelerating
5827 * clocks, provided we notify them before. Thus time never
5828 * goes backwards.
5829 *
5830 * However, we have a problem. We can't atomically update
5831 * the frequency of a given CPU from this function; it is
5832 * merely a notifier, which can be called from any CPU.
5833 * Changing the TSC frequency at arbitrary points in time
5834 * requires a recomputation of local variables related to
5835 * the TSC for each VCPU. We must flag these local variables
5836 * to be updated and be sure the update takes place with the
5837 * new frequency before any guests proceed.
5838 *
5839 * Unfortunately, the combination of hotplug CPU and frequency
5840 * change creates an intractable locking scenario; the order
5841 * of when these callouts happen is undefined with respect to
5842 * CPU hotplug, and they can race with each other. As such,
5843 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5844 * undefined; you can actually have a CPU frequency change take
5845 * place in between the computation of X and the setting of the
5846 * variable. To protect against this problem, all updates of
5847 * the per_cpu tsc_khz variable are done in an interrupt
5848 * protected IPI, and all callers wishing to update the value
5849 * must wait for a synchronous IPI to complete (which is trivial
5850 * if the caller is on the CPU already). This establishes the
5851 * necessary total order on variable updates.
5852 *
5853 * Note that because a guest time update may take place
5854 * anytime after the setting of the VCPU's request bit, the
5855 * correct TSC value must be set before the request. However,
5856 * to ensure the update actually makes it to any guest which
5857 * starts running in hardware virtualization between the set
5858 * and the acquisition of the spinlock, we must also ping the
5859 * CPU after setting the request bit.
5860 *
5861 */
5862
c8076604
GH		 5863 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5864 return 0;
5865 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5866 return 0;
8cfdc000
ZA		 5867
5868 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5869
2f303b74 5870 spin_lock(&kvm_lock);
c8076604 5871 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5872 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5873 if (vcpu->cpu != freq->cpu)
5874 continue;
c285545f 5875 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5876 if (vcpu->cpu != smp_processor_id())
8cfdc000 5877 send_ipi = 1;
c8076604
GH		 5878 }
5879 }
2f303b74 5880 spin_unlock(&kvm_lock);
c8076604
GH		 5881
5882 if (freq->old < freq->new && send_ipi) {
5883 /*
5884 * We upscale the frequency. Must make the guest
5885 * doesn't see old kvmclock values while running with
5886 * the new frequency, otherwise we risk the guest sees
5887 * time go backwards.
5888 *
5889 * In case we update the frequency for another cpu
5890 * (which might be in guest context) send an interrupt
5891 * to kick the cpu out of guest context. Next time
5892 * guest context is entered kvmclock will be updated,
5893 * so the guest will not see stale values.
5894 */
8cfdc000 5895 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5896 }
5897 return 0;
5898}
5899
5900static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5901 .notifier_call = kvmclock_cpufreq_notifier
5902};
5903
251a5fd6 5904static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 5905{
251a5fd6
SAS		 5906 tsc_khz_changed(NULL);
5907 return 0;
8cfdc000
ZA		 5908}
5909
b820cc0c
ZA		 5910static void kvm_timer_init(void)
5911{
c285545f 5912 max_tsc_khz = tsc_khz;
460dd42e 5913
b820cc0c 5914 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5915#ifdef CONFIG_CPU_FREQ
5916 struct cpufreq_policy policy;
758f588d
BP		 5917 int cpu;
5918
c285545f 5919 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5920 cpu = get_cpu();
5921 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5922 if (policy.cpuinfo.max_freq)
5923 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5924 put_cpu();
c285545f 5925#endif
b820cc0c
ZA		 5926 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5927 CPUFREQ_TRANSITION_NOTIFIER);
5928 }
c285545f 5929 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 5930
73c1b41e 5931 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 5932 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 5933}
5934
ff9d07a0
ZY		 5935static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5936
f5132b01 5937int kvm_is_in_guest(void)
ff9d07a0 5938{
086c9855 5939 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5940}
5941
5942static int kvm_is_user_mode(void)
5943{
5944 int user_mode = 3;
dcf46b94 5945
086c9855
AS		 5946 if (__this_cpu_read(current_vcpu))
5947 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5948
ff9d07a0
ZY		 5949 return user_mode != 0;
5950}
5951
5952static unsigned long kvm_get_guest_ip(void)
5953{
5954 unsigned long ip = 0;
dcf46b94 5955
086c9855
AS		 5956 if (__this_cpu_read(current_vcpu))
5957 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5958
ff9d07a0
ZY		 5959 return ip;
5960}
5961
5962static struct perf_guest_info_callbacks kvm_guest_cbs = {
5963 .is_in_guest = kvm_is_in_guest,
5964 .is_user_mode = kvm_is_user_mode,
5965 .get_guest_ip = kvm_get_guest_ip,
5966};
5967
5968void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5969{
086c9855 5970 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5971}
5972EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5973
5974void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5975{
086c9855 5976 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5977}
5978EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5979
ce88decf
XG		 5980static void kvm_set_mmio_spte_mask(void)
5981{
5982 u64 mask;
5983 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5984
5985 /*
5986 * Set the reserved bits and the present bit of an paging-structure
5987 * entry to generate page fault with PFER.RSV = 1.
5988 */
885032b9 5989 /* Mask the reserved physical address bits. */
d1431483 5990 mask = rsvd_bits(maxphyaddr, 51);
885032b9 5991
885032b9 5992 /* Set the present bit. */
ce88decf
XG		 5993 mask |= 1ull;
5994
5995#ifdef CONFIG_X86_64
5996 /*
5997 * If reserved bit is not supported, clear the present bit to disable
5998 * mmio page fault.
5999 */
6000 if (maxphyaddr == 52)
6001 mask &= ~1ull;
6002#endif
6003
6004 kvm_mmu_set_mmio_spte_mask(mask);
6005}
6006
16e8d74d
MT		 6007#ifdef CONFIG_X86_64
6008static void pvclock_gtod_update_fn(struct work_struct *work)
6009{
d828199e
MT		 6010 struct kvm *kvm;
6011
6012 struct kvm_vcpu *vcpu;
6013 int i;
6014
2f303b74 6015 spin_lock(&kvm_lock);
d828199e
MT		 6016 list_for_each_entry(kvm, &vm_list, vm_list)
6017 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6018 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6019 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6020 spin_unlock(&kvm_lock);
16e8d74d
MT		 6021}
6022
6023static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6024
6025/*
6026 * Notification about pvclock gtod data update.
6027 */
6028static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6029 void *priv)
6030{
6031 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6032 struct timekeeper *tk = priv;
6033
6034 update_pvclock_gtod(tk);
6035
6036 /* disable master clock if host does not trust, or does not
6037 * use, TSC clocksource
6038 */
6039 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6040 atomic_read(&kvm_guest_has_master_clock) != 0)
6041 queue_work(system_long_wq, &pvclock_gtod_work);
6042
6043 return 0;
6044}
6045
6046static struct notifier_block pvclock_gtod_notifier = {
6047 .notifier_call = pvclock_gtod_notify,
6048};
6049#endif
6050
f8c16bba 6051int kvm_arch_init(void *opaque)
043405e1 6052{
b820cc0c 6053 int r;
6b61edf7 6054 struct kvm_x86_ops *ops = opaque;
f8c16bba 6055
f8c16bba
ZX		 6056 if (kvm_x86_ops) {
6057 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6058 r = -EEXIST;
6059 goto out;
f8c16bba
ZX		 6060 }
6061
6062 if (!ops->cpu_has_kvm_support()) {
6063 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6064 r = -EOPNOTSUPP;
6065 goto out;
f8c16bba
ZX		 6066 }
6067 if (ops->disabled_by_bios()) {
6068 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6069 r = -EOPNOTSUPP;
6070 goto out;
f8c16bba
ZX		 6071 }
6072
013f6a5d
MT		 6073 r = -ENOMEM;
6074 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6075 if (!shared_msrs) {
6076 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6077 goto out;
6078 }
6079
97db56ce
AK		 6080 r = kvm_mmu_module_init();
6081 if (r)
013f6a5d 6082 goto out_free_percpu;
97db56ce 6083
ce88decf 6084 kvm_set_mmio_spte_mask();
97db56ce 6085
f8c16bba 6086 kvm_x86_ops = ops;
920c8377 6087
7b52345e 6088 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6089 PT_DIRTY_MASK, PT64_NX_MASK, 0,
f160c7b7 6090 PT_PRESENT_MASK, 0);
b820cc0c 6091 kvm_timer_init();
c8076604 6092
ff9d07a0
ZY		 6093 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6094
d366bf7e 6095 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6096 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6097
c5cc421b 6098 kvm_lapic_init();
16e8d74d
MT		 6099#ifdef CONFIG_X86_64
6100 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6101#endif
6102
f8c16bba 6103 return 0;
56c6d28a 6104
013f6a5d
MT		 6105out_free_percpu:
6106 free_percpu(shared_msrs);
56c6d28a 6107out:
56c6d28a 6108 return r;
043405e1 6109}
8776e519 6110
f8c16bba
ZX		 6111void kvm_arch_exit(void)
6112{
cef84c30 6113 kvm_lapic_exit();
ff9d07a0
ZY		 6114 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6115
888d256e
JK		 6116 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6117 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6118 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6119 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6120#ifdef CONFIG_X86_64
6121 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6122#endif
f8c16bba 6123 kvm_x86_ops = NULL;
56c6d28a 6124 kvm_mmu_module_exit();
013f6a5d 6125 free_percpu(shared_msrs);
56c6d28a 6126}
f8c16bba 6127
5cb56059 6128int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6129{
6130 ++vcpu->stat.halt_exits;
35754c98 6131 if (lapic_in_kernel(vcpu)) {
a4535290 6132 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6133 return 1;
6134 } else {
6135 vcpu->run->exit_reason = KVM_EXIT_HLT;
6136 return 0;
6137 }
6138}
5cb56059
JS		 6139EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6140
6141int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6142{
6affcbed
KH		 6143 int ret = kvm_skip_emulated_instruction(vcpu);
6144 /*
6145 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6146 * KVM_EXIT_DEBUG here.
6147 */
6148 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6149}
8776e519
HB		 6150EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6151
8ef81a9a 6152#ifdef CONFIG_X86_64
55dd00a7
MT		 6153static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6154 unsigned long clock_type)
6155{
6156 struct kvm_clock_pairing clock_pairing;
6157 struct timespec ts;
80fbd89c 6158 u64 cycle;
55dd00a7
MT		 6159 int ret;
6160
6161 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6162 return -KVM_EOPNOTSUPP;
6163
6164 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6165 return -KVM_EOPNOTSUPP;
6166
6167 clock_pairing.sec = ts.tv_sec;
6168 clock_pairing.nsec = ts.tv_nsec;
6169 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6170 clock_pairing.flags = 0;
6171
6172 ret = 0;
6173 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6174 sizeof(struct kvm_clock_pairing)))
6175 ret = -KVM_EFAULT;
6176
6177 return ret;
6178}
8ef81a9a 6179#endif
55dd00a7 6180
6aef266c
SV		 6181/*
6182 * kvm_pv_kick_cpu_op: Kick a vcpu.
6183 *
6184 * @apicid - apicid of vcpu to be kicked.
6185 */
6186static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6187{
24d2166b 6188 struct kvm_lapic_irq lapic_irq;
6aef266c 6189
24d2166b
R		 6190 lapic_irq.shorthand = 0;
6191 lapic_irq.dest_mode = 0;
6192 lapic_irq.dest_id = apicid;
93bbf0b8 6193 lapic_irq.msi_redir_hint = false;
6aef266c 6194
24d2166b 6195 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6196 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6197}
6198
d62caabb
AS		 6199void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6200{
6201 vcpu->arch.apicv_active = false;
6202 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6203}
6204
8776e519
HB		 6205int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6206{
6207 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6208 int op_64_bit, r;
8776e519 6209
6affcbed 6210 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6211
55cd8e5a
GN		 6212 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6213 return kvm_hv_hypercall(vcpu);
6214
5fdbf976
MT		 6215 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6216 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6217 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6218 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6219 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6220
229456fc 6221 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6222
a449c7aa
NA		 6223 op_64_bit = is_64_bit_mode(vcpu);
6224 if (!op_64_bit) {
8776e519
HB		 6225 nr &= 0xFFFFFFFF;
6226 a0 &= 0xFFFFFFFF;
6227 a1 &= 0xFFFFFFFF;
6228 a2 &= 0xFFFFFFFF;
6229 a3 &= 0xFFFFFFFF;
6230 }
6231
07708c4a
JK		 6232 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6233 ret = -KVM_EPERM;
6234 goto out;
6235 }
6236
8776e519 6237 switch (nr) {
b93463aa
AK		 6238 case KVM_HC_VAPIC_POLL_IRQ:
6239 ret = 0;
6240 break;
6aef266c
SV		 6241 case KVM_HC_KICK_CPU:
6242 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6243 ret = 0;
6244 break;
8ef81a9a 6245#ifdef CONFIG_X86_64
55dd00a7
MT		 6246 case KVM_HC_CLOCK_PAIRING:
6247 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6248 break;
8ef81a9a 6249#endif
8776e519
HB		 6250 default:
6251 ret = -KVM_ENOSYS;
6252 break;
6253 }
07708c4a 6254out:
a449c7aa
NA		 6255 if (!op_64_bit)
6256 ret = (u32)ret;
5fdbf976 6257 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6258 ++vcpu->stat.hypercalls;
2f333bcb 6259 return r;
8776e519
HB		 6260}
6261EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6262
b6785def 6263static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6264{
d6aa1000 6265 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6266 char instruction[3];
5fdbf976 6267 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6268
8776e519 6269 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6270
ce2e852e
DV		 6271 return emulator_write_emulated(ctxt, rip, instruction, 3,
6272 &ctxt->exception);
8776e519
HB		 6273}
6274
851ba692 6275static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6276{
782d422b
MG		 6277 return vcpu->run->request_interrupt_window &&
6278 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6279}
6280
851ba692 6281static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6282{
851ba692
AK		 6283 struct kvm_run *kvm_run = vcpu->run;
6284
91586a3b 6285 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6286 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6287 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6288 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6289 kvm_run->ready_for_interrupt_injection =
6290 pic_in_kernel(vcpu->kvm) ||
782d422b 6291 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6292}
6293
95ba8273
GN		 6294static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6295{
6296 int max_irr, tpr;
6297
6298 if (!kvm_x86_ops->update_cr8_intercept)
6299 return;
6300
bce87cce 6301 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6302 return;
6303
d62caabb
AS		 6304 if (vcpu->arch.apicv_active)
6305 return;
6306
8db3baa2
GN		 6307 if (!vcpu->arch.apic->vapic_addr)
6308 max_irr = kvm_lapic_find_highest_irr(vcpu);
6309 else
6310 max_irr = -1;
95ba8273
GN		 6311
6312 if (max_irr != -1)
6313 max_irr >>= 4;
6314
6315 tpr = kvm_lapic_get_cr8(vcpu);
6316
6317 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6318}
6319
b6b8a145 6320static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6321{
b6b8a145
JK		 6322 int r;
6323
95ba8273 6324 /* try to reinject previous events if any */
b59bb7bd 6325 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6326 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6327 vcpu->arch.exception.has_error_code,
6328 vcpu->arch.exception.error_code);
d6e8c854
NA		 6329
6330 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6331 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6332 X86_EFLAGS_RF);
6333
6bdf0662
NA		 6334 if (vcpu->arch.exception.nr == DB_VECTOR &&
6335 (vcpu->arch.dr7 & DR7_GD)) {
6336 vcpu->arch.dr7 &= ~DR7_GD;
6337 kvm_update_dr7(vcpu);
6338 }
6339
b59bb7bd
GN		 6340 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6341 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6342 vcpu->arch.exception.error_code,
6343 vcpu->arch.exception.reinject);
b6b8a145 6344 return 0;
b59bb7bd
GN		 6345 }
6346
95ba8273
GN		 6347 if (vcpu->arch.nmi_injected) {
6348 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6349 return 0;
95ba8273
GN		 6350 }
6351
6352 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6353 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6354 return 0;
6355 }
6356
6357 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6358 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6359 if (r != 0)
6360 return r;
95ba8273
GN		 6361 }
6362
6363 /* try to inject new event if pending */
c43203ca
PB		 6364 if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
6365 vcpu->arch.smi_pending = false;
ee2cd4b7 6366 enter_smm(vcpu);
c43203ca 6367 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6368 --vcpu->arch.nmi_pending;
6369 vcpu->arch.nmi_injected = true;
6370 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6371 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6372 /*
6373 * Because interrupts can be injected asynchronously, we are
6374 * calling check_nested_events again here to avoid a race condition.
6375 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6376 * proposal and current concerns. Perhaps we should be setting
6377 * KVM_REQ_EVENT only on certain events and not unconditionally?
6378 */
6379 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6380 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6381 if (r != 0)
6382 return r;
6383 }
95ba8273 6384 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6385 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6386 false);
6387 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6388 }
6389 }
ee2cd4b7 6390
b6b8a145 6391 return 0;
95ba8273
GN		 6392}
6393
7460fb4a
AK		 6394static void process_nmi(struct kvm_vcpu *vcpu)
6395{
6396 unsigned limit = 2;
6397
6398 /*
6399 * x86 is limited to one NMI running, and one NMI pending after it.
6400 * If an NMI is already in progress, limit further NMIs to just one.
6401 * Otherwise, allow two (and we'll inject the first one immediately).
6402 */
6403 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6404 limit = 1;
6405
6406 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6407 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6408 kvm_make_request(KVM_REQ_EVENT, vcpu);
6409}
6410
660a5d51
PB		 6411#define put_smstate(type, buf, offset, val) \
6412 *(type *)((buf) + (offset) - 0x7e00) = val
6413
ee2cd4b7 6414static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6415{
6416 u32 flags = 0;
6417 flags |= seg->g << 23;
6418 flags |= seg->db << 22;
6419 flags |= seg->l << 21;
6420 flags |= seg->avl << 20;
6421 flags |= seg->present << 15;
6422 flags |= seg->dpl << 13;
6423 flags |= seg->s << 12;
6424 flags |= seg->type << 8;
6425 return flags;
6426}
6427
ee2cd4b7 6428static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6429{
6430 struct kvm_segment seg;
6431 int offset;
6432
6433 kvm_get_segment(vcpu, &seg, n);
6434 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6435
6436 if (n < 3)
6437 offset = 0x7f84 + n * 12;
6438 else
6439 offset = 0x7f2c + (n - 3) * 12;
6440
6441 put_smstate(u32, buf, offset + 8, seg.base);
6442 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6443 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6444}
6445
efbb288a 6446#ifdef CONFIG_X86_64
ee2cd4b7 6447static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6448{
6449 struct kvm_segment seg;
6450 int offset;
6451 u16 flags;
6452
6453 kvm_get_segment(vcpu, &seg, n);
6454 offset = 0x7e00 + n * 16;
6455
ee2cd4b7 6456 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6457 put_smstate(u16, buf, offset, seg.selector);
6458 put_smstate(u16, buf, offset + 2, flags);
6459 put_smstate(u32, buf, offset + 4, seg.limit);
6460 put_smstate(u64, buf, offset + 8, seg.base);
6461}
efbb288a 6462#endif
660a5d51 6463
ee2cd4b7 6464static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6465{
6466 struct desc_ptr dt;
6467 struct kvm_segment seg;
6468 unsigned long val;
6469 int i;
6470
6471 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6472 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6473 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6474 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6475
6476 for (i = 0; i < 8; i++)
6477 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6478
6479 kvm_get_dr(vcpu, 6, &val);
6480 put_smstate(u32, buf, 0x7fcc, (u32)val);
6481 kvm_get_dr(vcpu, 7, &val);
6482 put_smstate(u32, buf, 0x7fc8, (u32)val);
6483
6484 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6485 put_smstate(u32, buf, 0x7fc4, seg.selector);
6486 put_smstate(u32, buf, 0x7f64, seg.base);
6487 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6488 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6489
6490 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6491 put_smstate(u32, buf, 0x7fc0, seg.selector);
6492 put_smstate(u32, buf, 0x7f80, seg.base);
6493 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6494 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6495
6496 kvm_x86_ops->get_gdt(vcpu, &dt);
6497 put_smstate(u32, buf, 0x7f74, dt.address);
6498 put_smstate(u32, buf, 0x7f70, dt.size);
6499
6500 kvm_x86_ops->get_idt(vcpu, &dt);
6501 put_smstate(u32, buf, 0x7f58, dt.address);
6502 put_smstate(u32, buf, 0x7f54, dt.size);
6503
6504 for (i = 0; i < 6; i++)
ee2cd4b7 6505 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6506
6507 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6508
6509 /* revision id */
6510 put_smstate(u32, buf, 0x7efc, 0x00020000);
6511 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6512}
6513
ee2cd4b7 6514static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6515{
6516#ifdef CONFIG_X86_64
6517 struct desc_ptr dt;
6518 struct kvm_segment seg;
6519 unsigned long val;
6520 int i;
6521
6522 for (i = 0; i < 16; i++)
6523 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6524
6525 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6526 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6527
6528 kvm_get_dr(vcpu, 6, &val);
6529 put_smstate(u64, buf, 0x7f68, val);
6530 kvm_get_dr(vcpu, 7, &val);
6531 put_smstate(u64, buf, 0x7f60, val);
6532
6533 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6534 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6535 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6536
6537 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6538
6539 /* revision id */
6540 put_smstate(u32, buf, 0x7efc, 0x00020064);
6541
6542 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6543
6544 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6545 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6546 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6547 put_smstate(u32, buf, 0x7e94, seg.limit);
6548 put_smstate(u64, buf, 0x7e98, seg.base);
6549
6550 kvm_x86_ops->get_idt(vcpu, &dt);
6551 put_smstate(u32, buf, 0x7e84, dt.size);
6552 put_smstate(u64, buf, 0x7e88, dt.address);
6553
6554 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6555 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6556 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6557 put_smstate(u32, buf, 0x7e74, seg.limit);
6558 put_smstate(u64, buf, 0x7e78, seg.base);
6559
6560 kvm_x86_ops->get_gdt(vcpu, &dt);
6561 put_smstate(u32, buf, 0x7e64, dt.size);
6562 put_smstate(u64, buf, 0x7e68, dt.address);
6563
6564 for (i = 0; i < 6; i++)
ee2cd4b7 6565 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6566#else
6567 WARN_ON_ONCE(1);
6568#endif
6569}
6570
ee2cd4b7 6571static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6572{
660a5d51 6573 struct kvm_segment cs, ds;
18c3626e 6574 struct desc_ptr dt;
660a5d51
PB		 6575 char buf[512];
6576 u32 cr0;
6577
660a5d51
PB		 6578 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6579 vcpu->arch.hflags |= HF_SMM_MASK;
6580 memset(buf, 0, 512);
6581 if (guest_cpuid_has_longmode(vcpu))
ee2cd4b7 6582 enter_smm_save_state_64(vcpu, buf);
660a5d51 6583 else
ee2cd4b7 6584 enter_smm_save_state_32(vcpu, buf);
660a5d51 6585
54bf36aa 6586 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6587
6588 if (kvm_x86_ops->get_nmi_mask(vcpu))
6589 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6590 else
6591 kvm_x86_ops->set_nmi_mask(vcpu, true);
6592
6593 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6594 kvm_rip_write(vcpu, 0x8000);
6595
6596 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6597 kvm_x86_ops->set_cr0(vcpu, cr0);
6598 vcpu->arch.cr0 = cr0;
6599
6600 kvm_x86_ops->set_cr4(vcpu, 0);
6601
18c3626e
PB		 6602 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6603 dt.address = dt.size = 0;
6604 kvm_x86_ops->set_idt(vcpu, &dt);
6605
660a5d51
PB		 6606 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6607
6608 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6609 cs.base = vcpu->arch.smbase;
6610
6611 ds.selector = 0;
6612 ds.base = 0;
6613
6614 cs.limit = ds.limit = 0xffffffff;
6615 cs.type = ds.type = 0x3;
6616 cs.dpl = ds.dpl = 0;
6617 cs.db = ds.db = 0;
6618 cs.s = ds.s = 1;
6619 cs.l = ds.l = 0;
6620 cs.g = ds.g = 1;
6621 cs.avl = ds.avl = 0;
6622 cs.present = ds.present = 1;
6623 cs.unusable = ds.unusable = 0;
6624 cs.padding = ds.padding = 0;
6625
6626 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6627 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6628 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6629 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6630 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6631 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6632
6633 if (guest_cpuid_has_longmode(vcpu))
6634 kvm_x86_ops->set_efer(vcpu, 0);
6635
6636 kvm_update_cpuid(vcpu);
6637 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6638}
6639
ee2cd4b7 6640static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6641{
6642 vcpu->arch.smi_pending = true;
6643 kvm_make_request(KVM_REQ_EVENT, vcpu);
6644}
6645
2860c4b1
PB		 6646void kvm_make_scan_ioapic_request(struct kvm *kvm)
6647{
6648 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6649}
6650
3d81bc7e 6651static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6652{
5c919412
AS		 6653 u64 eoi_exit_bitmap[4];
6654
3d81bc7e
YZ		 6655 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6656 return;
c7c9c56c 6657
6308630b 6658 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6659
b053b2ae 6660 if (irqchip_split(vcpu->kvm))
6308630b 6661 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6662 else {
76dfafd5 6663 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb 6664 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6665 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6666 }
5c919412
AS		 6667 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6668 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6669 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6670}
6671
a70656b6
RK		 6672static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6673{
6674 ++vcpu->stat.tlb_flush;
6675 kvm_x86_ops->tlb_flush(vcpu);
6676}
6677
4256f43f
TC		 6678void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6679{
c24ae0dc
TC		 6680 struct page *page = NULL;
6681
35754c98 6682 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6683 return;
6684
4256f43f
TC		 6685 if (!kvm_x86_ops->set_apic_access_page_addr)
6686 return;
6687
c24ae0dc 6688 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6689 if (is_error_page(page))
6690 return;
c24ae0dc
TC		 6691 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6692
6693 /*
6694 * Do not pin apic access page in memory, the MMU notifier
6695 * will call us again if it is migrated or swapped out.
6696 */
6697 put_page(page);
4256f43f
TC		 6698}
6699EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6700
fe71557a
TC		 6701void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6702 unsigned long address)
6703{
c24ae0dc
TC		 6704 /*
6705 * The physical address of apic access page is stored in the VMCS.
6706 * Update it when it becomes invalid.
6707 */
6708 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6709 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6710}
6711
9357d939 6712/*
362c698f 6713 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6714 * exiting to the userspace. Otherwise, the value will be returned to the
6715 * userspace.
6716 */
851ba692 6717static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6718{
6719 int r;
62a193ed
MG		 6720 bool req_int_win =
6721 dm_request_for_irq_injection(vcpu) &&
6722 kvm_cpu_accept_dm_intr(vcpu);
6723
730dca42 6724 bool req_immediate_exit = false;
b6c7a5dc 6725
3e007509 6726 if (vcpu->requests) {
a8eeb04a 6727 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6728 kvm_mmu_unload(vcpu);
a8eeb04a 6729 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6730 __kvm_migrate_timers(vcpu);
d828199e
MT		 6731 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6732 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6733 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6734 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6735 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6736 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6737 if (unlikely(r))
6738 goto out;
6739 }
a8eeb04a 6740 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6741 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6742 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6743 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6744 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6745 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6746 r = 0;
6747 goto out;
6748 }
a8eeb04a 6749 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6750 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6751 r = 0;
6752 goto out;
6753 }
af585b92
GN		 6754 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6755 /* Page is swapped out. Do synthetic halt */
6756 vcpu->arch.apf.halted = true;
6757 r = 1;
6758 goto out;
6759 }
c9aaa895
GC		 6760 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6761 record_steal_time(vcpu);
64d60670
PB		 6762 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6763 process_smi(vcpu);
7460fb4a
AK		 6764 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6765 process_nmi(vcpu);
f5132b01 6766 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6767 kvm_pmu_handle_event(vcpu);
f5132b01 6768 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6769 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6770 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6771 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6772 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6773 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6774 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6775 vcpu->run->eoi.vector =
6776 vcpu->arch.pending_ioapic_eoi;
6777 r = 0;
6778 goto out;
6779 }
6780 }
3d81bc7e
YZ		 6781 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6782 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6783 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6784 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6785 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6786 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6787 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6788 r = 0;
6789 goto out;
6790 }
e516cebb
AS		 6791 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6792 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6793 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6794 r = 0;
6795 goto out;
6796 }
db397571
AS		 6797 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6798 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6799 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6800 r = 0;
6801 goto out;
6802 }
f3b138c5
AS		 6803
6804 /*
6805 * KVM_REQ_HV_STIMER has to be processed after
6806 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6807 * depend on the guest clock being up-to-date
6808 */
1f4b34f8
AS		 6809 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6810 kvm_hv_process_stimers(vcpu);
2f52d58c 6811 }
b93463aa 6812
b463a6f7 6813 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 6814 ++vcpu->stat.req_event;
66450a21
JK		 6815 kvm_apic_accept_events(vcpu);
6816 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6817 r = 1;
6818 goto out;
6819 }
6820
b6b8a145
JK		 6821 if (inject_pending_event(vcpu, req_int_win) != 0)
6822 req_immediate_exit = true;
321c5658 6823 else {
c43203ca
PB		 6824 /* Enable NMI/IRQ window open exits if needed.
6825 *
6826 * SMIs have two cases: 1) they can be nested, and
6827 * then there is nothing to do here because RSM will
6828 * cause a vmexit anyway; 2) or the SMI can be pending
6829 * because inject_pending_event has completed the
6830 * injection of an IRQ or NMI from the previous vmexit,
6831 * and then we request an immediate exit to inject the SMI.
6832 */
6833 if (vcpu->arch.smi_pending && !is_smm(vcpu))
6834 req_immediate_exit = true;
321c5658
YS		 6835 if (vcpu->arch.nmi_pending)
6836 kvm_x86_ops->enable_nmi_window(vcpu);
6837 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6838 kvm_x86_ops->enable_irq_window(vcpu);
6839 }
b463a6f7
AK		 6840
6841 if (kvm_lapic_enabled(vcpu)) {
6842 update_cr8_intercept(vcpu);
6843 kvm_lapic_sync_to_vapic(vcpu);
6844 }
6845 }
6846
d8368af8
AK		 6847 r = kvm_mmu_reload(vcpu);
6848 if (unlikely(r)) {
d905c069 6849 goto cancel_injection;
d8368af8
AK		 6850 }
6851
b6c7a5dc
HB		 6852 preempt_disable();
6853
6854 kvm_x86_ops->prepare_guest_switch(vcpu);
bd7e5b08 6855 kvm_load_guest_fpu(vcpu);
b95234c8
PB		 6856
6857 /*
6858 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
6859 * IPI are then delayed after guest entry, which ensures that they
6860 * result in virtual interrupt delivery.
6861 */
6862 local_irq_disable();
6b7e2d09
XG		 6863 vcpu->mode = IN_GUEST_MODE;
6864
01b71917
MT		 6865 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6866
0f127d12 6867 /*
b95234c8 6868 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 6869 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 6870 *
6871 * 2) For APICv, we should set ->mode before checking PIR.ON. This
6872 * pairs with the memory barrier implicit in pi_test_and_set_on
6873 * (see vmx_deliver_posted_interrupt).
6874 *
6875 * 3) This also orders the write to mode from any reads to the page
6876 * tables done while the VCPU is running. Please see the comment
6877 * in kvm_flush_remote_tlbs.
6b7e2d09 6878 */
01b71917 6879 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6880
b95234c8
PB		 6881 /*
6882 * This handles the case where a posted interrupt was
6883 * notified with kvm_vcpu_kick.
6884 */
6885 if (kvm_lapic_enabled(vcpu)) {
6886 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6887 kvm_x86_ops->sync_pir_to_irr(vcpu);
6888 }
32f88400 6889
6b7e2d09 6890 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6891 || need_resched() || signal_pending(current)) {
6b7e2d09 6892 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6893 smp_wmb();
6c142801
AK		 6894 local_irq_enable();
6895 preempt_enable();
01b71917 6896 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6897 r = 1;
d905c069 6898 goto cancel_injection;
6c142801
AK		 6899 }
6900
fc5b7f3b
DM		 6901 kvm_load_guest_xcr0(vcpu);
6902
c43203ca
PB		 6903 if (req_immediate_exit) {
6904 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 6905 smp_send_reschedule(vcpu->cpu);
c43203ca 6906 }
d6185f20 6907
8b89fe1f
PB		 6908 trace_kvm_entry(vcpu->vcpu_id);
6909 wait_lapic_expire(vcpu);
6edaa530 6910 guest_enter_irqoff();
b6c7a5dc 6911
42dbaa5a 6912 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6913 set_debugreg(0, 7);
6914 set_debugreg(vcpu->arch.eff_db[0], 0);
6915 set_debugreg(vcpu->arch.eff_db[1], 1);
6916 set_debugreg(vcpu->arch.eff_db[2], 2);
6917 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6918 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6919 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6920 }
b6c7a5dc 6921
851ba692 6922 kvm_x86_ops->run(vcpu);
b6c7a5dc 6923
c77fb5fe
PB		 6924 /*
6925 * Do this here before restoring debug registers on the host. And
6926 * since we do this before handling the vmexit, a DR access vmexit
6927 * can (a) read the correct value of the debug registers, (b) set
6928 * KVM_DEBUGREG_WONT_EXIT again.
6929 */
6930 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 6931 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6932 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 6933 kvm_update_dr0123(vcpu);
6934 kvm_update_dr6(vcpu);
6935 kvm_update_dr7(vcpu);
6936 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 6937 }
6938
24f1e32c
FW		 6939 /*
6940 * If the guest has used debug registers, at least dr7
6941 * will be disabled while returning to the host.
6942 * If we don't have active breakpoints in the host, we don't
6943 * care about the messed up debug address registers. But if
6944 * we have some of them active, restore the old state.
6945 */
59d8eb53 6946 if (hw_breakpoint_active())
24f1e32c 6947 hw_breakpoint_restore();
42dbaa5a 6948
4ba76538 6949 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6950
6b7e2d09 6951 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6952 smp_wmb();
a547c6db 6953
fc5b7f3b
DM		 6954 kvm_put_guest_xcr0(vcpu);
6955
a547c6db 6956 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6957
6958 ++vcpu->stat.exits;
6959
f2485b3e 6960 guest_exit_irqoff();
b6c7a5dc 6961
f2485b3e 6962 local_irq_enable();
b6c7a5dc
HB		 6963 preempt_enable();
6964
f656ce01 6965 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6966
b6c7a5dc
HB		 6967 /*
6968 * Profile KVM exit RIPs:
6969 */
6970 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6971 unsigned long rip = kvm_rip_read(vcpu);
6972 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6973 }
6974
cc578287
ZA		 6975 if (unlikely(vcpu->arch.tsc_always_catchup))
6976 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6977
5cfb1d5a
MT		 6978 if (vcpu->arch.apic_attention)
6979 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6980
851ba692 6981 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6982 return r;
6983
6984cancel_injection:
6985 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6986 if (unlikely(vcpu->arch.apic_attention))
6987 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6988out:
6989 return r;
6990}
b6c7a5dc 6991
362c698f
PB		 6992static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6993{
bf9f6ac8
FW		 6994 if (!kvm_arch_vcpu_runnable(vcpu) &&
6995 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6996 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6997 kvm_vcpu_block(vcpu);
6998 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6999
7000 if (kvm_x86_ops->post_block)
7001 kvm_x86_ops->post_block(vcpu);
7002
9c8fd1ba
PB		 7003 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7004 return 1;
7005 }
362c698f
PB		 7006
7007 kvm_apic_accept_events(vcpu);
7008 switch(vcpu->arch.mp_state) {
7009 case KVM_MP_STATE_HALTED:
7010 vcpu->arch.pv.pv_unhalted = false;
7011 vcpu->arch.mp_state =
7012 KVM_MP_STATE_RUNNABLE;
7013 case KVM_MP_STATE_RUNNABLE:
7014 vcpu->arch.apf.halted = false;
7015 break;
7016 case KVM_MP_STATE_INIT_RECEIVED:
7017 break;
7018 default:
7019 return -EINTR;
7020 break;
7021 }
7022 return 1;
7023}
09cec754 7024
5d9bc648
PB		 7025static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7026{
0ad3bed6
PB		 7027 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7028 kvm_x86_ops->check_nested_events(vcpu, false);
7029
5d9bc648
PB		 7030 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7031 !vcpu->arch.apf.halted);
7032}
7033
362c698f 7034static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7035{
7036 int r;
f656ce01 7037 struct kvm *kvm = vcpu->kvm;
d7690175 7038
f656ce01 7039 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7040
362c698f 7041 for (;;) {
58f800d5 7042 if (kvm_vcpu_running(vcpu)) {
851ba692 7043 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7044 } else {
362c698f 7045 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7046 }
7047
09cec754
GN		 7048 if (r <= 0)
7049 break;
7050
72875d8a 7051 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7052 if (kvm_cpu_has_pending_timer(vcpu))
7053 kvm_inject_pending_timer_irqs(vcpu);
7054
782d422b
MG		 7055 if (dm_request_for_irq_injection(vcpu) &&
7056 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7057 r = 0;
7058 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7059 ++vcpu->stat.request_irq_exits;
362c698f 7060 break;
09cec754 7061 }
af585b92
GN		 7062
7063 kvm_check_async_pf_completion(vcpu);
7064
09cec754
GN		 7065 if (signal_pending(current)) {
7066 r = -EINTR;
851ba692 7067 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7068 ++vcpu->stat.signal_exits;
362c698f 7069 break;
09cec754
GN		 7070 }
7071 if (need_resched()) {
f656ce01 7072 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7073 cond_resched();
f656ce01 7074 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7075 }
b6c7a5dc
HB		 7076 }
7077
f656ce01 7078 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7079
7080 return r;
7081}
7082
716d51ab
GN		 7083static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7084{
7085 int r;
7086 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7087 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7088 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7089 if (r != EMULATE_DONE)
7090 return 0;
7091 return 1;
7092}
7093
7094static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7095{
7096 BUG_ON(!vcpu->arch.pio.count);
7097
7098 return complete_emulated_io(vcpu);
7099}
7100
f78146b0
AK		 7101/*
7102 * Implements the following, as a state machine:
7103 *
7104 * read:
7105 * for each fragment
87da7e66
XG		 7106 * for each mmio piece in the fragment
7107 * write gpa, len
7108 * exit
7109 * copy data
f78146b0
AK		 7110 * execute insn
7111 *
7112 * write:
7113 * for each fragment
87da7e66
XG		 7114 * for each mmio piece in the fragment
7115 * write gpa, len
7116 * copy data
7117 * exit
f78146b0 7118 */
716d51ab 7119static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7120{
7121 struct kvm_run *run = vcpu->run;
f78146b0 7122 struct kvm_mmio_fragment *frag;
87da7e66 7123 unsigned len;
5287f194 7124
716d51ab 7125 BUG_ON(!vcpu->mmio_needed);
5287f194 7126
716d51ab 7127 /* Complete previous fragment */
87da7e66
XG		 7128 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7129 len = min(8u, frag->len);
716d51ab 7130 if (!vcpu->mmio_is_write)
87da7e66
XG		 7131 memcpy(frag->data, run->mmio.data, len);
7132
7133 if (frag->len <= 8) {
7134 /* Switch to the next fragment. */
7135 frag++;
7136 vcpu->mmio_cur_fragment++;
7137 } else {
7138 /* Go forward to the next mmio piece. */
7139 frag->data += len;
7140 frag->gpa += len;
7141 frag->len -= len;
7142 }
7143
a08d3b3b 7144 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7145 vcpu->mmio_needed = 0;
0912c977
PB		 7146
7147 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7148 if (vcpu->mmio_is_write)
716d51ab
GN		 7149 return 1;
7150 vcpu->mmio_read_completed = 1;
7151 return complete_emulated_io(vcpu);
7152 }
87da7e66 7153
716d51ab
GN		 7154 run->exit_reason = KVM_EXIT_MMIO;
7155 run->mmio.phys_addr = frag->gpa;
7156 if (vcpu->mmio_is_write)
87da7e66
XG		 7157 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7158 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7159 run->mmio.is_write = vcpu->mmio_is_write;
7160 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7161 return 0;
5287f194
AK		 7162}
7163
716d51ab 7164
b6c7a5dc
HB		 7165int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7166{
c5bedc68 7167 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 7168 int r;
7169 sigset_t sigsaved;
7170
c4d72e2d 7171 fpu__activate_curr(fpu);
e5c30142 7172
ac9f6dc0
AK		 7173 if (vcpu->sigset_active)
7174 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
7175
a4535290 7176 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 7177 kvm_vcpu_block(vcpu);
66450a21 7178 kvm_apic_accept_events(vcpu);
72875d8a 7179 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0
AK		 7180 r = -EAGAIN;
7181 goto out;
b6c7a5dc
HB		 7182 }
7183
b6c7a5dc 7184 /* re-sync apic's tpr */
35754c98 7185 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7186 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7187 r = -EINVAL;
7188 goto out;
7189 }
7190 }
b6c7a5dc 7191
716d51ab
GN		 7192 if (unlikely(vcpu->arch.complete_userspace_io)) {
7193 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7194 vcpu->arch.complete_userspace_io = NULL;
7195 r = cui(vcpu);
7196 if (r <= 0)
7197 goto out;
7198 } else
7199 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7200
460df4c1
PB		 7201 if (kvm_run->immediate_exit)
7202 r = -EINTR;
7203 else
7204 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7205
7206out:
f1d86e46 7207 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 7208 if (vcpu->sigset_active)
7209 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
7210
b6c7a5dc
HB		 7211 return r;
7212}
7213
7214int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7215{
7ae441ea
GN		 7216 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7217 /*
7218 * We are here if userspace calls get_regs() in the middle of
7219 * instruction emulation. Registers state needs to be copied
4a969980 7220 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7221 * that usually, but some bad designed PV devices (vmware
7222 * backdoor interface) need this to work
7223 */
dd856efa 7224 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7225 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7226 }
5fdbf976
MT		 7227 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7228 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7229 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7230 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7231 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7232 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7233 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7234 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7235#ifdef CONFIG_X86_64
5fdbf976
MT		 7236 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7237 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7238 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7239 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7240 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7241 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7242 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7243 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7244#endif
7245
5fdbf976 7246 regs->rip = kvm_rip_read(vcpu);
91586a3b 7247 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7248
b6c7a5dc
HB		 7249 return 0;
7250}
7251
7252int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7253{
7ae441ea
GN		 7254 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7255 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7256
5fdbf976
MT		 7257 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7258 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7259 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7260 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7261 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7262 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7263 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7264 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7265#ifdef CONFIG_X86_64
5fdbf976
MT		 7266 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7267 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7268 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7269 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7270 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7271 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7272 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7273 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7274#endif
7275
5fdbf976 7276 kvm_rip_write(vcpu, regs->rip);
91586a3b 7277 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 7278
b4f14abd
JK		 7279 vcpu->arch.exception.pending = false;
7280
3842d135
AK		 7281 kvm_make_request(KVM_REQ_EVENT, vcpu);
7282
b6c7a5dc
HB		 7283 return 0;
7284}
7285
b6c7a5dc
HB		 7286void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7287{
7288 struct kvm_segment cs;
7289
3e6e0aab 7290 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7291 *db = cs.db;
7292 *l = cs.l;
7293}
7294EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7295
7296int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7297 struct kvm_sregs *sregs)
7298{
89a27f4d 7299 struct desc_ptr dt;
b6c7a5dc 7300
3e6e0aab
GT		 7301 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7302 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7303 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7304 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7305 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7306 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7307
3e6e0aab
GT		 7308 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7309 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7310
7311 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7312 sregs->idt.limit = dt.size;
7313 sregs->idt.base = dt.address;
b6c7a5dc 7314 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7315 sregs->gdt.limit = dt.size;
7316 sregs->gdt.base = dt.address;
b6c7a5dc 7317
4d4ec087 7318 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7319 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7320 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7321 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7322 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7323 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7324 sregs->apic_base = kvm_get_apic_base(vcpu);
7325
923c61bb 7326 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7327
36752c9b 7328 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7329 set_bit(vcpu->arch.interrupt.nr,
7330 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7331
b6c7a5dc
HB		 7332 return 0;
7333}
7334
62d9f0db
MT		 7335int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7336 struct kvm_mp_state *mp_state)
7337{
66450a21 7338 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7339 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7340 vcpu->arch.pv.pv_unhalted)
7341 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7342 else
7343 mp_state->mp_state = vcpu->arch.mp_state;
7344
62d9f0db
MT		 7345 return 0;
7346}
7347
7348int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7349 struct kvm_mp_state *mp_state)
7350{
bce87cce 7351 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7352 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7353 return -EINVAL;
7354
28bf2888
DH		 7355 /* INITs are latched while in SMM */
7356 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7357 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7358 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7359 return -EINVAL;
7360
66450a21
JK		 7361 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7362 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7363 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7364 } else
7365 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7366 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7367 return 0;
7368}
7369
7f3d35fd
KW		 7370int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7371 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7372{
9d74191a 7373 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7374 int ret;
e01c2426 7375
8ec4722d 7376 init_emulate_ctxt(vcpu);
c697518a 7377
7f3d35fd 7378 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7379 has_error_code, error_code);
c697518a 7380
c697518a 7381 if (ret)
19d04437 7382 return EMULATE_FAIL;
37817f29 7383
9d74191a
TY		 7384 kvm_rip_write(vcpu, ctxt->eip);
7385 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7386 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7387 return EMULATE_DONE;
37817f29
IE		 7388}
7389EXPORT_SYMBOL_GPL(kvm_task_switch);
7390
b6c7a5dc
HB		 7391int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7392 struct kvm_sregs *sregs)
7393{
58cb628d 7394 struct msr_data apic_base_msr;
b6c7a5dc 7395 int mmu_reset_needed = 0;
63f42e02 7396 int pending_vec, max_bits, idx;
89a27f4d 7397 struct desc_ptr dt;
b6c7a5dc 7398
6d1068b3
PM		 7399 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7400 return -EINVAL;
7401
89a27f4d
GN		 7402 dt.size = sregs->idt.limit;
7403 dt.address = sregs->idt.base;
b6c7a5dc 7404 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7405 dt.size = sregs->gdt.limit;
7406 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7407 kvm_x86_ops->set_gdt(vcpu, &dt);
7408
ad312c7c 7409 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7410 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7411 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7412 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7413
2d3ad1f4 7414 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7415
f6801dff 7416 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7417 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7418 apic_base_msr.data = sregs->apic_base;
7419 apic_base_msr.host_initiated = true;
7420 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7421
4d4ec087 7422 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7423 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7424 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7425
fc78f519 7426 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7427 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7428 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7429 kvm_update_cpuid(vcpu);
63f42e02
XG		 7430
7431 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7432 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7433 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7434 mmu_reset_needed = 1;
7435 }
63f42e02 7436 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7437
7438 if (mmu_reset_needed)
7439 kvm_mmu_reset_context(vcpu);
7440
a50abc3b 7441 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7442 pending_vec = find_first_bit(
7443 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7444 if (pending_vec < max_bits) {
66fd3f7f 7445 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7446 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7447 }
7448
3e6e0aab
GT		 7449 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7450 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7451 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7452 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7453 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7454 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7455
3e6e0aab
GT		 7456 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7457 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7458
5f0269f5
ME		 7459 update_cr8_intercept(vcpu);
7460
9c3e4aab 7461 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7462 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7463 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7464 !is_protmode(vcpu))
9c3e4aab
MT		 7465 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7466
3842d135
AK		 7467 kvm_make_request(KVM_REQ_EVENT, vcpu);
7468
b6c7a5dc
HB		 7469 return 0;
7470}
7471
d0bfb940
JK		 7472int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7473 struct kvm_guest_debug *dbg)
b6c7a5dc 7474{
355be0b9 7475 unsigned long rflags;
ae675ef0 7476 int i, r;
b6c7a5dc 7477
4f926bf2
JK		 7478 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7479 r = -EBUSY;
7480 if (vcpu->arch.exception.pending)
2122ff5e 7481 goto out;
4f926bf2
JK		 7482 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7483 kvm_queue_exception(vcpu, DB_VECTOR);
7484 else
7485 kvm_queue_exception(vcpu, BP_VECTOR);
7486 }
7487
91586a3b
JK		 7488 /*
7489 * Read rflags as long as potentially injected trace flags are still
7490 * filtered out.
7491 */
7492 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7493
7494 vcpu->guest_debug = dbg->control;
7495 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7496 vcpu->guest_debug = 0;
7497
7498 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7499 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7500 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7501 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7502 } else {
7503 for (i = 0; i < KVM_NR_DB_REGS; i++)
7504 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7505 }
c8639010 7506 kvm_update_dr7(vcpu);
ae675ef0 7507
f92653ee
JK		 7508 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7509 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7510 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7511
91586a3b
JK		 7512 /*
7513 * Trigger an rflags update that will inject or remove the trace
7514 * flags.
7515 */
7516 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7517
a96036b8 7518 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7519
4f926bf2 7520 r = 0;
d0bfb940 7521
2122ff5e 7522out:
b6c7a5dc
HB		 7523
7524 return r;
7525}
7526
8b006791
ZX		 7527/*
7528 * Translate a guest virtual address to a guest physical address.
7529 */
7530int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7531 struct kvm_translation *tr)
7532{
7533 unsigned long vaddr = tr->linear_address;
7534 gpa_t gpa;
f656ce01 7535 int idx;
8b006791 7536
f656ce01 7537 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7538 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7539 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7540 tr->physical_address = gpa;
7541 tr->valid = gpa != UNMAPPED_GVA;
7542 tr->writeable = 1;
7543 tr->usermode = 0;
8b006791
ZX		 7544
7545 return 0;
7546}
7547
d0752060
HB		 7548int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7549{
c47ada30 7550 struct fxregs_state *fxsave =
7366ed77 7551 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7552
d0752060
HB		 7553 memcpy(fpu->fpr, fxsave->st_space, 128);
7554 fpu->fcw = fxsave->cwd;
7555 fpu->fsw = fxsave->swd;
7556 fpu->ftwx = fxsave->twd;
7557 fpu->last_opcode = fxsave->fop;
7558 fpu->last_ip = fxsave->rip;
7559 fpu->last_dp = fxsave->rdp;
7560 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7561
d0752060
HB		 7562 return 0;
7563}
7564
7565int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7566{
c47ada30 7567 struct fxregs_state *fxsave =
7366ed77 7568 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7569
d0752060
HB		 7570 memcpy(fxsave->st_space, fpu->fpr, 128);
7571 fxsave->cwd = fpu->fcw;
7572 fxsave->swd = fpu->fsw;
7573 fxsave->twd = fpu->ftwx;
7574 fxsave->fop = fpu->last_opcode;
7575 fxsave->rip = fpu->last_ip;
7576 fxsave->rdp = fpu->last_dp;
7577 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7578
d0752060
HB		 7579 return 0;
7580}
7581
0ee6a517 7582static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7583{
bf935b0b 7584 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7585 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7586 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7587 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7588
2acf923e
DC		 7589 /*
7590 * Ensure guest xcr0 is valid for loading
7591 */
d91cab78 7592 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7593
ad312c7c 7594 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7595}
d0752060
HB		 7596
7597void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7598{
2608d7a1 7599 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7600 return;
7601
2acf923e
DC		 7602 /*
7603 * Restore all possible states in the guest,
7604 * and assume host would use all available bits.
7605 * Guest xcr0 would be loaded later.
7606 */
d0752060 7607 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7608 __kernel_fpu_begin();
003e2e8b 7609 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7610 trace_kvm_fpu(1);
d0752060 7611}
d0752060
HB		 7612
7613void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7614{
3d42de25 7615 if (!vcpu->guest_fpu_loaded)
d0752060
HB		 7616 return;
7617
7618 vcpu->guest_fpu_loaded = 0;
4f836347 7619 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7620 __kernel_fpu_end();
f096ed85 7621 ++vcpu->stat.fpu_reload;
0c04851c 7622 trace_kvm_fpu(0);
d0752060 7623}
e9b11c17
ZX		 7624
7625void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7626{
bd768e14
IY		 7627 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7628
12f9a48f 7629 kvmclock_reset(vcpu);
7f1ea208 7630
e9b11c17 7631 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 7632 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 7633}
7634
7635struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7636 unsigned int id)
7637{
c447e76b
LL		 7638 struct kvm_vcpu *vcpu;
7639
6755bae8
ZA		 7640 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7641 printk_once(KERN_WARNING
7642 "kvm: SMP vm created on host with unstable TSC; "
7643 "guest TSC will not be reliable\n");
c447e76b
LL		 7644
7645 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7646
c447e76b 7647 return vcpu;
26e5215f 7648}
e9b11c17 7649
26e5215f
AK		 7650int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7651{
7652 int r;
e9b11c17 7653
19efffa2 7654 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7655 r = vcpu_load(vcpu);
7656 if (r)
7657 return r;
d28bc9dd 7658 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7659 kvm_mmu_setup(vcpu);
e9b11c17 7660 vcpu_put(vcpu);
26e5215f 7661 return r;
e9b11c17
ZX		 7662}
7663
31928aa5 7664void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7665{
8fe8ab46 7666 struct msr_data msr;
332967a3 7667 struct kvm *kvm = vcpu->kvm;
42897d86 7668
31928aa5
DD		 7669 if (vcpu_load(vcpu))
7670 return;
8fe8ab46
WA		 7671 msr.data = 0x0;
7672 msr.index = MSR_IA32_TSC;
7673 msr.host_initiated = true;
7674 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7675 vcpu_put(vcpu);
7676
630994b3
MT		 7677 if (!kvmclock_periodic_sync)
7678 return;
7679
332967a3
AJ		 7680 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7681 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7682}
7683
d40ccc62 7684void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7685{
9fc77441 7686 int r;
344d9588
GN		 7687 vcpu->arch.apf.msr_val = 0;
7688
9fc77441
MT		 7689 r = vcpu_load(vcpu);
7690 BUG_ON(r);
e9b11c17
ZX		 7691 kvm_mmu_unload(vcpu);
7692 vcpu_put(vcpu);
7693
7694 kvm_x86_ops->vcpu_free(vcpu);
7695}
7696
d28bc9dd 7697void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7698{
e69fab5d
PB		 7699 vcpu->arch.hflags = 0;
7700
c43203ca 7701 vcpu->arch.smi_pending = 0;
7460fb4a
AK		 7702 atomic_set(&vcpu->arch.nmi_queued, 0);
7703 vcpu->arch.nmi_pending = 0;
448fa4a9 7704 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7705 kvm_clear_interrupt_queue(vcpu);
7706 kvm_clear_exception_queue(vcpu);
448fa4a9 7707
42dbaa5a 7708 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7709 kvm_update_dr0123(vcpu);
6f43ed01 7710 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7711 kvm_update_dr6(vcpu);
42dbaa5a 7712 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7713 kvm_update_dr7(vcpu);
42dbaa5a 7714
1119022c
NA		 7715 vcpu->arch.cr2 = 0;
7716
3842d135 7717 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7718 vcpu->arch.apf.msr_val = 0;
c9aaa895 7719 vcpu->arch.st.msr_val = 0;
3842d135 7720
12f9a48f
GC		 7721 kvmclock_reset(vcpu);
7722
af585b92
GN		 7723 kvm_clear_async_pf_completion_queue(vcpu);
7724 kvm_async_pf_hash_reset(vcpu);
7725 vcpu->arch.apf.halted = false;
3842d135 7726
64d60670 7727 if (!init_event) {
d28bc9dd 7728 kvm_pmu_reset(vcpu);
64d60670 7729 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 7730
7731 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
7732 vcpu->arch.msr_misc_features_enables = 0;
64d60670 7733 }
f5132b01 7734
66f7b72e
JS		 7735 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7736 vcpu->arch.regs_avail = ~0;
7737 vcpu->arch.regs_dirty = ~0;
7738
d28bc9dd 7739 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7740}
7741
2b4a273b 7742void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7743{
7744 struct kvm_segment cs;
7745
7746 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7747 cs.selector = vector << 8;
7748 cs.base = vector << 12;
7749 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7750 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7751}
7752
13a34e06 7753int kvm_arch_hardware_enable(void)
e9b11c17 7754{
ca84d1a2
ZA		 7755 struct kvm *kvm;
7756 struct kvm_vcpu *vcpu;
7757 int i;
0dd6a6ed
ZA		 7758 int ret;
7759 u64 local_tsc;
7760 u64 max_tsc = 0;
7761 bool stable, backwards_tsc = false;
18863bdd
AK		 7762
7763 kvm_shared_msr_cpu_online();
13a34e06 7764 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7765 if (ret != 0)
7766 return ret;
7767
4ea1636b 7768 local_tsc = rdtsc();
0dd6a6ed
ZA		 7769 stable = !check_tsc_unstable();
7770 list_for_each_entry(kvm, &vm_list, vm_list) {
7771 kvm_for_each_vcpu(i, vcpu, kvm) {
7772 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7773 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7774 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7775 backwards_tsc = true;
7776 if (vcpu->arch.last_host_tsc > max_tsc)
7777 max_tsc = vcpu->arch.last_host_tsc;
7778 }
7779 }
7780 }
7781
7782 /*
7783 * Sometimes, even reliable TSCs go backwards. This happens on
7784 * platforms that reset TSC during suspend or hibernate actions, but
7785 * maintain synchronization. We must compensate. Fortunately, we can
7786 * detect that condition here, which happens early in CPU bringup,
7787 * before any KVM threads can be running. Unfortunately, we can't
7788 * bring the TSCs fully up to date with real time, as we aren't yet far
7789 * enough into CPU bringup that we know how much real time has actually
108b249c 7790 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 7791 * variables that haven't been updated yet.
7792 *
7793 * So we simply find the maximum observed TSC above, then record the
7794 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7795 * the adjustment will be applied. Note that we accumulate
7796 * adjustments, in case multiple suspend cycles happen before some VCPU
7797 * gets a chance to run again. In the event that no KVM threads get a
7798 * chance to run, we will miss the entire elapsed period, as we'll have
7799 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7800 * loose cycle time. This isn't too big a deal, since the loss will be
7801 * uniform across all VCPUs (not to mention the scenario is extremely
7802 * unlikely). It is possible that a second hibernate recovery happens
7803 * much faster than a first, causing the observed TSC here to be
7804 * smaller; this would require additional padding adjustment, which is
7805 * why we set last_host_tsc to the local tsc observed here.
7806 *
7807 * N.B. - this code below runs only on platforms with reliable TSC,
7808 * as that is the only way backwards_tsc is set above. Also note
7809 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7810 * have the same delta_cyc adjustment applied if backwards_tsc
7811 * is detected. Note further, this adjustment is only done once,
7812 * as we reset last_host_tsc on all VCPUs to stop this from being
7813 * called multiple times (one for each physical CPU bringup).
7814 *
4a969980 7815 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7816 * will be compensated by the logic in vcpu_load, which sets the TSC to
7817 * catchup mode. This will catchup all VCPUs to real time, but cannot
7818 * guarantee that they stay in perfect synchronization.
7819 */
7820 if (backwards_tsc) {
7821 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7822 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7823 list_for_each_entry(kvm, &vm_list, vm_list) {
7824 kvm_for_each_vcpu(i, vcpu, kvm) {
7825 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7826 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7827 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7828 }
7829
7830 /*
7831 * We have to disable TSC offset matching.. if you were
7832 * booting a VM while issuing an S4 host suspend....
7833 * you may have some problem. Solving this issue is
7834 * left as an exercise to the reader.
7835 */
7836 kvm->arch.last_tsc_nsec = 0;
7837 kvm->arch.last_tsc_write = 0;
7838 }
7839
7840 }
7841 return 0;
e9b11c17
ZX		 7842}
7843
13a34e06 7844void kvm_arch_hardware_disable(void)
e9b11c17 7845{
13a34e06
RK		 7846 kvm_x86_ops->hardware_disable();
7847 drop_user_return_notifiers();
e9b11c17
ZX		 7848}
7849
7850int kvm_arch_hardware_setup(void)
7851{
9e9c3fe4
NA		 7852 int r;
7853
7854 r = kvm_x86_ops->hardware_setup();
7855 if (r != 0)
7856 return r;
7857
35181e86
HZ		 7858 if (kvm_has_tsc_control) {
7859 /*
7860 * Make sure the user can only configure tsc_khz values that
7861 * fit into a signed integer.
7862 * A min value is not calculated needed because it will always
7863 * be 1 on all machines.
7864 */
7865 u64 max = min(0x7fffffffULL,
7866 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7867 kvm_max_guest_tsc_khz = max;
7868
ad721883 7869 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7870 }
ad721883 7871
9e9c3fe4
NA		 7872 kvm_init_msr_list();
7873 return 0;
e9b11c17
ZX		 7874}
7875
7876void kvm_arch_hardware_unsetup(void)
7877{
7878 kvm_x86_ops->hardware_unsetup();
7879}
7880
7881void kvm_arch_check_processor_compat(void *rtn)
7882{
7883 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7884}
7885
7886bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7887{
7888 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7889}
7890EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7891
7892bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7893{
7894 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7895}
7896
54e9818f 7897struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 7898EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 7899
e9b11c17
ZX		 7900int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7901{
7902 struct page *page;
7903 struct kvm *kvm;
7904 int r;
7905
7906 BUG_ON(vcpu->kvm == NULL);
7907 kvm = vcpu->kvm;
7908
d62caabb 7909 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7910 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7911 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7912 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7913 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7914 else
a4535290 7915 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7916
7917 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7918 if (!page) {
7919 r = -ENOMEM;
7920 goto fail;
7921 }
ad312c7c 7922 vcpu->arch.pio_data = page_address(page);
e9b11c17 7923
cc578287 7924 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7925
e9b11c17
ZX		 7926 r = kvm_mmu_create(vcpu);
7927 if (r < 0)
7928 goto fail_free_pio_data;
7929
7930 if (irqchip_in_kernel(kvm)) {
7931 r = kvm_create_lapic(vcpu);
7932 if (r < 0)
7933 goto fail_mmu_destroy;
54e9818f
GN		 7934 } else
7935 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7936
890ca9ae
HY		 7937 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7938 GFP_KERNEL);
7939 if (!vcpu->arch.mce_banks) {
7940 r = -ENOMEM;
443c39bc 7941 goto fail_free_lapic;
890ca9ae
HY		 7942 }
7943 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7944
f1797359
WY		 7945 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7946 r = -ENOMEM;
f5f48ee1 7947 goto fail_free_mce_banks;
f1797359 7948 }
f5f48ee1 7949
0ee6a517 7950 fx_init(vcpu);
66f7b72e 7951
ba904635 7952 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7953 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7954
7955 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7956 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7957
5a4f55cd
EK		 7958 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7959
74545705
RK		 7960 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7961
af585b92 7962 kvm_async_pf_hash_reset(vcpu);
f5132b01 7963 kvm_pmu_init(vcpu);
af585b92 7964
1c1a9ce9
SR		 7965 vcpu->arch.pending_external_vector = -1;
7966
5c919412
AS		 7967 kvm_hv_vcpu_init(vcpu);
7968
e9b11c17 7969 return 0;
0ee6a517 7970
f5f48ee1
SY		 7971fail_free_mce_banks:
7972 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7973fail_free_lapic:
7974 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7975fail_mmu_destroy:
7976 kvm_mmu_destroy(vcpu);
7977fail_free_pio_data:
ad312c7c 7978 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7979fail:
7980 return r;
7981}
7982
7983void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7984{
f656ce01
MT		 7985 int idx;
7986
1f4b34f8 7987 kvm_hv_vcpu_uninit(vcpu);
f5132b01 7988 kvm_pmu_destroy(vcpu);
36cb93fd 7989 kfree(vcpu->arch.mce_banks);
e9b11c17 7990 kvm_free_lapic(vcpu);
f656ce01 7991 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7992 kvm_mmu_destroy(vcpu);
f656ce01 7993 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7994 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7995 if (!lapic_in_kernel(vcpu))
54e9818f 7996 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7997}
d19a9cd2 7998
e790d9ef
RK		 7999void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8000{
ae97a3b8 8001 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8002}
8003
e08b9637 8004int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8005{
e08b9637
CO		 8006 if (type)
8007 return -EINVAL;
8008
6ef768fa 8009 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8010 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8011 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8012 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8013 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8014
5550af4d
SY		 8015 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8016 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8017 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8018 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8019 &kvm->arch.irq_sources_bitmap);
5550af4d 8020
038f8c11 8021 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8022 mutex_init(&kvm->arch.apic_map_lock);
3f5ad8be 8023 mutex_init(&kvm->arch.hyperv.hv_lock);
d828199e
MT		 8024 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8025
108b249c 8026 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8027 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8028
7e44e449 8029 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8030 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8031
0eb05bf2 8032 kvm_page_track_init(kvm);
13d268ca 8033 kvm_mmu_init_vm(kvm);
0eb05bf2 8034
03543133
SS		 8035 if (kvm_x86_ops->vm_init)
8036 return kvm_x86_ops->vm_init(kvm);
8037
d89f5eff 8038 return 0;
d19a9cd2
ZX		 8039}
8040
8041static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8042{
9fc77441
MT		 8043 int r;
8044 r = vcpu_load(vcpu);
8045 BUG_ON(r);
d19a9cd2
ZX		 8046 kvm_mmu_unload(vcpu);
8047 vcpu_put(vcpu);
8048}
8049
8050static void kvm_free_vcpus(struct kvm *kvm)
8051{
8052 unsigned int i;
988a2cae 8053 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8054
8055 /*
8056 * Unpin any mmu pages first.
8057 */
af585b92
GN		 8058 kvm_for_each_vcpu(i, vcpu, kvm) {
8059 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8060 kvm_unload_vcpu_mmu(vcpu);
af585b92 8061 }
988a2cae
GN		 8062 kvm_for_each_vcpu(i, vcpu, kvm)
8063 kvm_arch_vcpu_free(vcpu);
8064
8065 mutex_lock(&kvm->lock);
8066 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8067 kvm->vcpus[i] = NULL;
d19a9cd2 8068
988a2cae
GN		 8069 atomic_set(&kvm->online_vcpus, 0);
8070 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8071}
8072
ad8ba2cd
SY		 8073void kvm_arch_sync_events(struct kvm *kvm)
8074{
332967a3 8075 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8076 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8077 kvm_free_pit(kvm);
ad8ba2cd
SY		 8078}
8079
1d8007bd 8080int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8081{
8082 int i, r;
25188b99 8083 unsigned long hva;
f0d648bd
PB		 8084 struct kvm_memslots *slots = kvm_memslots(kvm);
8085 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8086
8087 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8088 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8089 return -EINVAL;
9da0e4d5 8090
f0d648bd
PB		 8091 slot = id_to_memslot(slots, id);
8092 if (size) {
b21629da 8093 if (slot->npages)
f0d648bd
PB		 8094 return -EEXIST;
8095
8096 /*
8097 * MAP_SHARED to prevent internal slot pages from being moved
8098 * by fork()/COW.
8099 */
8100 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8101 MAP_SHARED | MAP_ANONYMOUS, 0);
8102 if (IS_ERR((void *)hva))
8103 return PTR_ERR((void *)hva);
8104 } else {
8105 if (!slot->npages)
8106 return 0;
8107
8108 hva = 0;
8109 }
8110
8111 old = *slot;
9da0e4d5 8112 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8113 struct kvm_userspace_memory_region m;
9da0e4d5 8114
1d8007bd
PB		 8115 m.slot = id | (i << 16);
8116 m.flags = 0;
8117 m.guest_phys_addr = gpa;
f0d648bd 8118 m.userspace_addr = hva;
1d8007bd 8119 m.memory_size = size;
9da0e4d5
PB		 8120 r = __kvm_set_memory_region(kvm, &m);
8121 if (r < 0)
8122 return r;
8123 }
8124
f0d648bd
PB		 8125 if (!size) {
8126 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8127 WARN_ON(r < 0);
8128 }
8129
9da0e4d5
PB		 8130 return 0;
8131}
8132EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8133
1d8007bd 8134int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8135{
8136 int r;
8137
8138 mutex_lock(&kvm->slots_lock);
1d8007bd 8139 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8140 mutex_unlock(&kvm->slots_lock);
8141
8142 return r;
8143}
8144EXPORT_SYMBOL_GPL(x86_set_memory_region);
8145
d19a9cd2
ZX		 8146void kvm_arch_destroy_vm(struct kvm *kvm)
8147{
27469d29
AH		 8148 if (current->mm == kvm->mm) {
8149 /*
8150 * Free memory regions allocated on behalf of userspace,
8151 * unless the the memory map has changed due to process exit
8152 * or fd copying.
8153 */
1d8007bd
PB		 8154 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8155 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8156 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8157 }
03543133
SS		 8158 if (kvm_x86_ops->vm_destroy)
8159 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8160 kvm_pic_destroy(kvm);
8161 kvm_ioapic_destroy(kvm);
d19a9cd2 8162 kvm_free_vcpus(kvm);
af1bae54 8163 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8164 kvm_mmu_uninit_vm(kvm);
2beb6dad 8165 kvm_page_track_cleanup(kvm);
d19a9cd2 8166}
0de10343 8167
5587027c 8168void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8169 struct kvm_memory_slot *dont)
8170{
8171 int i;
8172
d89cc617
TY		 8173 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8174 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8175 kvfree(free->arch.rmap[i]);
d89cc617 8176 free->arch.rmap[i] = NULL;
77d11309 8177 }
d89cc617
TY		 8178 if (i == 0)
8179 continue;
8180
8181 if (!dont || free->arch.lpage_info[i - 1] !=
8182 dont->arch.lpage_info[i - 1]) {
548ef284 8183 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8184 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8185 }
8186 }
21ebbeda
XG		 8187
8188 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8189}
8190
5587027c
AK		 8191int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8192 unsigned long npages)
db3fe4eb
TY		 8193{
8194 int i;
8195
d89cc617 8196 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8197 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8198 unsigned long ugfn;
8199 int lpages;
d89cc617 8200 int level = i + 1;
db3fe4eb
TY		 8201
8202 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8203 slot->base_gfn, level) + 1;
8204
d89cc617 8205 slot->arch.rmap[i] =
a7c3e901 8206 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8207 if (!slot->arch.rmap[i])
77d11309 8208 goto out_free;
d89cc617
TY		 8209 if (i == 0)
8210 continue;
77d11309 8211
a7c3e901 8212 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8213 if (!linfo)
db3fe4eb
TY		 8214 goto out_free;
8215
92f94f1e
XG		 8216 slot->arch.lpage_info[i - 1] = linfo;
8217
db3fe4eb 8218 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8219 linfo[0].disallow_lpage = 1;
db3fe4eb 8220 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8221 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8222 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8223 /*
8224 * If the gfn and userspace address are not aligned wrt each
8225 * other, or if explicitly asked to, disable large page
8226 * support for this slot
8227 */
8228 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8229 !kvm_largepages_enabled()) {
8230 unsigned long j;
8231
8232 for (j = 0; j < lpages; ++j)
92f94f1e 8233 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8234 }
8235 }
8236
21ebbeda
XG		 8237 if (kvm_page_track_create_memslot(slot, npages))
8238 goto out_free;
8239
db3fe4eb
TY		 8240 return 0;
8241
8242out_free:
d89cc617 8243 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8244 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8245 slot->arch.rmap[i] = NULL;
8246 if (i == 0)
8247 continue;
8248
548ef284 8249 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8250 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8251 }
8252 return -ENOMEM;
8253}
8254
15f46015 8255void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8256{
e6dff7d1
TY		 8257 /*
8258 * memslots->generation has been incremented.
8259 * mmio generation may have reached its maximum value.
8260 */
54bf36aa 8261 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8262}
8263
f7784b8e
MT		 8264int kvm_arch_prepare_memory_region(struct kvm *kvm,
8265 struct kvm_memory_slot *memslot,
09170a49 8266 const struct kvm_userspace_memory_region *mem,
7b6195a9 8267 enum kvm_mr_change change)
0de10343 8268{
f7784b8e
MT		 8269 return 0;
8270}
8271
88178fd4
KH		 8272static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8273 struct kvm_memory_slot *new)
8274{
8275 /* Still write protect RO slot */
8276 if (new->flags & KVM_MEM_READONLY) {
8277 kvm_mmu_slot_remove_write_access(kvm, new);
8278 return;
8279 }
8280
8281 /*
8282 * Call kvm_x86_ops dirty logging hooks when they are valid.
8283 *
8284 * kvm_x86_ops->slot_disable_log_dirty is called when:
8285 *
8286 * - KVM_MR_CREATE with dirty logging is disabled
8287 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8288 *
8289 * The reason is, in case of PML, we need to set D-bit for any slots
8290 * with dirty logging disabled in order to eliminate unnecessary GPA
8291 * logging in PML buffer (and potential PML buffer full VMEXT). This
8292 * guarantees leaving PML enabled during guest's lifetime won't have
8293 * any additonal overhead from PML when guest is running with dirty
8294 * logging disabled for memory slots.
8295 *
8296 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8297 * to dirty logging mode.
8298 *
8299 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8300 *
8301 * In case of write protect:
8302 *
8303 * Write protect all pages for dirty logging.
8304 *
8305 * All the sptes including the large sptes which point to this
8306 * slot are set to readonly. We can not create any new large
8307 * spte on this slot until the end of the logging.
8308 *
8309 * See the comments in fast_page_fault().
8310 */
8311 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8312 if (kvm_x86_ops->slot_enable_log_dirty)
8313 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8314 else
8315 kvm_mmu_slot_remove_write_access(kvm, new);
8316 } else {
8317 if (kvm_x86_ops->slot_disable_log_dirty)
8318 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8319 }
8320}
8321
f7784b8e 8322void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8323 const struct kvm_userspace_memory_region *mem,
8482644a 8324 const struct kvm_memory_slot *old,
f36f3f28 8325 const struct kvm_memory_slot *new,
8482644a 8326 enum kvm_mr_change change)
f7784b8e 8327{
8482644a 8328 int nr_mmu_pages = 0;
f7784b8e 8329
48c0e4e9
XG		 8330 if (!kvm->arch.n_requested_mmu_pages)
8331 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8332
48c0e4e9 8333 if (nr_mmu_pages)
0de10343 8334 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8335
3ea3b7fa
WL		 8336 /*
8337 * Dirty logging tracks sptes in 4k granularity, meaning that large
8338 * sptes have to be split. If live migration is successful, the guest
8339 * in the source machine will be destroyed and large sptes will be
8340 * created in the destination. However, if the guest continues to run
8341 * in the source machine (for example if live migration fails), small
8342 * sptes will remain around and cause bad performance.
8343 *
8344 * Scan sptes if dirty logging has been stopped, dropping those
8345 * which can be collapsed into a single large-page spte. Later
8346 * page faults will create the large-page sptes.
8347 */
8348 if ((change != KVM_MR_DELETE) &&
8349 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8350 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8351 kvm_mmu_zap_collapsible_sptes(kvm, new);
8352
c972f3b1 8353 /*
88178fd4 8354 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8355 *
88178fd4
KH		 8356 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8357 * been zapped so no dirty logging staff is needed for old slot. For
8358 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8359 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8360 *
8361 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8362 */
88178fd4 8363 if (change != KVM_MR_DELETE)
f36f3f28 8364 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8365}
1d737c8a 8366
2df72e9b 8367void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8368{
6ca18b69 8369 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8370}
8371
2df72e9b
MT		 8372void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8373 struct kvm_memory_slot *slot)
8374{
ae7cd873 8375 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8376}
8377
5d9bc648
PB		 8378static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8379{
8380 if (!list_empty_careful(&vcpu->async_pf.done))
8381 return true;
8382
8383 if (kvm_apic_has_events(vcpu))
8384 return true;
8385
8386 if (vcpu->arch.pv.pv_unhalted)
8387 return true;
8388
8389 if (atomic_read(&vcpu->arch.nmi_queued))
8390 return true;
8391
72875d8a 8392 if (kvm_test_request(KVM_REQ_SMI, vcpu))
73917739
PB		 8393 return true;
8394
5d9bc648
PB		 8395 if (kvm_arch_interrupt_allowed(vcpu) &&
8396 kvm_cpu_has_interrupt(vcpu))
8397 return true;
8398
1f4b34f8
AS		 8399 if (kvm_hv_has_stimer_pending(vcpu))
8400 return true;
8401
5d9bc648
PB		 8402 return false;
8403}
8404
1d737c8a
ZX		 8405int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8406{
5d9bc648 8407 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8408}
5736199a 8409
b6d33834 8410int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8411{
b6d33834 8412 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8413}
78646121
GN		 8414
8415int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8416{
8417 return kvm_x86_ops->interrupt_allowed(vcpu);
8418}
229456fc 8419
82b32774 8420unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8421{
82b32774
NA		 8422 if (is_64_bit_mode(vcpu))
8423 return kvm_rip_read(vcpu);
8424 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8425 kvm_rip_read(vcpu));
8426}
8427EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8428
82b32774
NA		 8429bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8430{
8431 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8432}
8433EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8434
94fe45da
JK		 8435unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8436{
8437 unsigned long rflags;
8438
8439 rflags = kvm_x86_ops->get_rflags(vcpu);
8440 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8441 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8442 return rflags;
8443}
8444EXPORT_SYMBOL_GPL(kvm_get_rflags);
8445
6addfc42 8446static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8447{
8448 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8449 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8450 rflags |= X86_EFLAGS_TF;
94fe45da 8451 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8452}
8453
8454void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8455{
8456 __kvm_set_rflags(vcpu, rflags);
3842d135 8457 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8458}
8459EXPORT_SYMBOL_GPL(kvm_set_rflags);
8460
56028d08
GN		 8461void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8462{
8463 int r;
8464
fb67e14f 8465 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8466 work->wakeup_all)
56028d08
GN		 8467 return;
8468
8469 r = kvm_mmu_reload(vcpu);
8470 if (unlikely(r))
8471 return;
8472
fb67e14f
XG		 8473 if (!vcpu->arch.mmu.direct_map &&
8474 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8475 return;
8476
56028d08
GN		 8477 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8478}
8479
af585b92
GN		 8480static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8481{
8482 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8483}
8484
8485static inline u32 kvm_async_pf_next_probe(u32 key)
8486{
8487 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8488}
8489
8490static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8491{
8492 u32 key = kvm_async_pf_hash_fn(gfn);
8493
8494 while (vcpu->arch.apf.gfns[key] != ~0)
8495 key = kvm_async_pf_next_probe(key);
8496
8497 vcpu->arch.apf.gfns[key] = gfn;
8498}
8499
8500static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8501{
8502 int i;
8503 u32 key = kvm_async_pf_hash_fn(gfn);
8504
8505 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8506 (vcpu->arch.apf.gfns[key] != gfn &&
8507 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8508 key = kvm_async_pf_next_probe(key);
8509
8510 return key;
8511}
8512
8513bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8514{
8515 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8516}
8517
8518static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8519{
8520 u32 i, j, k;
8521
8522 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8523 while (true) {
8524 vcpu->arch.apf.gfns[i] = ~0;
8525 do {
8526 j = kvm_async_pf_next_probe(j);
8527 if (vcpu->arch.apf.gfns[j] == ~0)
8528 return;
8529 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8530 /*
8531 * k lies cyclically in ]i,j]
8532 * | i.k.j |
8533 * |....j i.k.| or |.k..j i...|
8534 */
8535 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8536 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8537 i = j;
8538 }
8539}
8540
7c90705b
GN		 8541static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8542{
4e335d9e
PB		 8543
8544 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8545 sizeof(val));
7c90705b
GN		 8546}
8547
af585b92
GN		 8548void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8549 struct kvm_async_pf *work)
8550{
6389ee94
AK		 8551 struct x86_exception fault;
8552
7c90705b 8553 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8554 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8555
8556 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8557 (vcpu->arch.apf.send_user_only &&
8558 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8559 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8560 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8561 fault.vector = PF_VECTOR;
8562 fault.error_code_valid = true;
8563 fault.error_code = 0;
8564 fault.nested_page_fault = false;
8565 fault.address = work->arch.token;
8566 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8567 }
af585b92
GN		 8568}
8569
8570void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8571 struct kvm_async_pf *work)
8572{
6389ee94
AK		 8573 struct x86_exception fault;
8574
f2e10669 8575 if (work->wakeup_all)
7c90705b
GN		 8576 work->arch.token = ~0; /* broadcast wakeup */
8577 else
8578 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 8579 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b
GN		 8580
8581 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8582 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8583 fault.vector = PF_VECTOR;
8584 fault.error_code_valid = true;
8585 fault.error_code = 0;
8586 fault.nested_page_fault = false;
8587 fault.address = work->arch.token;
8588 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8589 }
e6d53e3b 8590 vcpu->arch.apf.halted = false;
a4fa1635 8591 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8592}
8593
8594bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8595{
8596 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8597 return true;
8598 else
8599 return !kvm_event_needs_reinjection(vcpu) &&
8600 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8601}
8602
5544eb9b
PB		 8603void kvm_arch_start_assignment(struct kvm *kvm)
8604{
8605 atomic_inc(&kvm->arch.assigned_device_count);
8606}
8607EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8608
8609void kvm_arch_end_assignment(struct kvm *kvm)
8610{
8611 atomic_dec(&kvm->arch.assigned_device_count);
8612}
8613EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8614
8615bool kvm_arch_has_assigned_device(struct kvm *kvm)
8616{
8617 return atomic_read(&kvm->arch.assigned_device_count);
8618}
8619EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8620
e0f0bbc5
AW		 8621void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8622{
8623 atomic_inc(&kvm->arch.noncoherent_dma_count);
8624}
8625EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8626
8627void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8628{
8629 atomic_dec(&kvm->arch.noncoherent_dma_count);
8630}
8631EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8632
8633bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8634{
8635 return atomic_read(&kvm->arch.noncoherent_dma_count);
8636}
8637EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8638
14717e20
AW		 8639bool kvm_arch_has_irq_bypass(void)
8640{
8641 return kvm_x86_ops->update_pi_irte != NULL;
8642}
8643
87276880
FW		 8644int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8645 struct irq_bypass_producer *prod)
8646{
8647 struct kvm_kernel_irqfd *irqfd =
8648 container_of(cons, struct kvm_kernel_irqfd, consumer);
8649
14717e20 8650 irqfd->producer = prod;
87276880 8651
14717e20
AW		 8652 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8653 prod->irq, irqfd->gsi, 1);
87276880
FW		 8654}
8655
8656void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8657 struct irq_bypass_producer *prod)
8658{
8659 int ret;
8660 struct kvm_kernel_irqfd *irqfd =
8661 container_of(cons, struct kvm_kernel_irqfd, consumer);
8662
87276880
FW		 8663 WARN_ON(irqfd->producer != prod);
8664 irqfd->producer = NULL;
8665
8666 /*
8667 * When producer of consumer is unregistered, we change back to
8668 * remapped mode, so we can re-use the current implementation
bb3541f1 8669 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8670 * int this case doesn't want to receive the interrupts.
8671 */
8672 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8673 if (ret)
8674 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8675 " fails: %d\n", irqfd->consumer.token, ret);
8676}
8677
8678int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8679 uint32_t guest_irq, bool set)
8680{
8681 if (!kvm_x86_ops->update_pi_irte)
8682 return -EINVAL;
8683
8684 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8685}
8686
52004014
FW		 8687bool kvm_vector_hashing_enabled(void)
8688{
8689 return vector_hashing;
8690}
8691EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8692
229456fc 8693EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8694EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8695EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8696EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8697EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8698EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8699EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8700EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8701EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8702EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8703EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8704EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8705EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8706EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8707EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8708EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8709EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8710EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8711EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
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