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KVM: Prepare memslot data structures for multiple hugepage sizes
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
229456fc
MT		 40#define CREATE_TRACE_POINTS
41#include "trace.h"
043405e1
CO		 42
43#include <asm/uaccess.h>
d825ed0a 44#include <asm/msr.h>
a5f61300 45#include <asm/desc.h>
0bed3b56 46#include <asm/mtrr.h>
890ca9ae 47#include <asm/mce.h>
043405e1 48
313a3dc7 49#define MAX_IO_MSRS 256
a03490ed
CO		 50#define CR0_RESERVED_BITS \
51 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
52 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
53 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
54#define CR4_RESERVED_BITS \
55 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
56 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
57 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
58 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
59
60#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 61
62#define KVM_MAX_MCE_BANKS 32
63#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
64
50a37eb4
JR		 65/* EFER defaults:
66 * - enable syscall per default because its emulated by KVM
67 * - enable LME and LMA per default on 64 bit KVM
68 */
69#ifdef CONFIG_X86_64
70static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
71#else
72static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
73#endif
313a3dc7 74
ba1389b7
AK		 75#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
76#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 77
674eea0f
AK		 78static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
79 struct kvm_cpuid_entry2 __user *entries);
d8017474
AG		 80struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
81 u32 function, u32 index);
674eea0f 82
97896d04 83struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 84EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 85
417bc304 86struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 87 { "pf_fixed", VCPU_STAT(pf_fixed) },
88 { "pf_guest", VCPU_STAT(pf_guest) },
89 { "tlb_flush", VCPU_STAT(tlb_flush) },
90 { "invlpg", VCPU_STAT(invlpg) },
91 { "exits", VCPU_STAT(exits) },
92 { "io_exits", VCPU_STAT(io_exits) },
93 { "mmio_exits", VCPU_STAT(mmio_exits) },
94 { "signal_exits", VCPU_STAT(signal_exits) },
95 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 96 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 97 { "halt_exits", VCPU_STAT(halt_exits) },
98 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 99 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 100 { "request_irq", VCPU_STAT(request_irq_exits) },
101 { "irq_exits", VCPU_STAT(irq_exits) },
102 { "host_state_reload", VCPU_STAT(host_state_reload) },
103 { "efer_reload", VCPU_STAT(efer_reload) },
104 { "fpu_reload", VCPU_STAT(fpu_reload) },
105 { "insn_emulation", VCPU_STAT(insn_emulation) },
106 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 107 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 108 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 109 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
110 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
111 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
112 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
113 { "mmu_flooded", VM_STAT(mmu_flooded) },
114 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 115 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 116 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 117 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 118 { "largepages", VM_STAT(lpages) },
417bc304
HB		 119 { NULL }
120};
121
5fb76f9b
CO		 122unsigned long segment_base(u16 selector)
123{
124 struct descriptor_table gdt;
a5f61300 125 struct desc_struct *d;
5fb76f9b
CO		 126 unsigned long table_base;
127 unsigned long v;
128
129 if (selector == 0)
130 return 0;
131
132 asm("sgdt %0" : "=m"(gdt));
133 table_base = gdt.base;
134
135 if (selector & 4) { /* from ldt */
136 u16 ldt_selector;
137
138 asm("sldt %0" : "=g"(ldt_selector));
139 table_base = segment_base(ldt_selector);
140 }
a5f61300
AK		 141 d = (struct desc_struct *)(table_base + (selector & ~7));
142 v = d->base0 | ((unsigned long)d->base1 << 16) |
143 ((unsigned long)d->base2 << 24);
5fb76f9b 144#ifdef CONFIG_X86_64
a5f61300
AK		 145 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
146 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 147#endif
148 return v;
149}
150EXPORT_SYMBOL_GPL(segment_base);
151
6866b83e
CO		 152u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
153{
154 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 155 return vcpu->arch.apic_base;
6866b83e 156 else
ad312c7c 157 return vcpu->arch.apic_base;
6866b83e
CO		 158}
159EXPORT_SYMBOL_GPL(kvm_get_apic_base);
160
161void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
162{
163 /* TODO: reserve bits check */
164 if (irqchip_in_kernel(vcpu->kvm))
165 kvm_lapic_set_base(vcpu, data);
166 else
ad312c7c 167 vcpu->arch.apic_base = data;
6866b83e
CO		 168}
169EXPORT_SYMBOL_GPL(kvm_set_apic_base);
170
298101da
AK		 171void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
172{
ad312c7c
ZX		 173 WARN_ON(vcpu->arch.exception.pending);
174 vcpu->arch.exception.pending = true;
175 vcpu->arch.exception.has_error_code = false;
176 vcpu->arch.exception.nr = nr;
298101da
AK		 177}
178EXPORT_SYMBOL_GPL(kvm_queue_exception);
179
c3c91fee
AK		 180void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
181 u32 error_code)
182{
183 ++vcpu->stat.pf_guest;
d8017474 184
71c4dfaf 185 if (vcpu->arch.exception.pending) {
6edf14d8
GN		 186 switch(vcpu->arch.exception.nr) {
187 case DF_VECTOR:
71c4dfaf
JR		 188 /* triple fault -> shutdown */
189 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
6edf14d8
GN		 190 return;
191 case PF_VECTOR:
192 vcpu->arch.exception.nr = DF_VECTOR;
193 vcpu->arch.exception.error_code = 0;
194 return;
195 default:
196 /* replace previous exception with a new one in a hope
197 that instruction re-execution will regenerate lost
198 exception */
199 vcpu->arch.exception.pending = false;
200 break;
71c4dfaf 201 }
c3c91fee 202 }
ad312c7c 203 vcpu->arch.cr2 = addr;
c3c91fee
AK		 204 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
205}
206
3419ffc8
SY		 207void kvm_inject_nmi(struct kvm_vcpu *vcpu)
208{
209 vcpu->arch.nmi_pending = 1;
210}
211EXPORT_SYMBOL_GPL(kvm_inject_nmi);
212
298101da
AK		 213void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
214{
ad312c7c
ZX		 215 WARN_ON(vcpu->arch.exception.pending);
216 vcpu->arch.exception.pending = true;
217 vcpu->arch.exception.has_error_code = true;
218 vcpu->arch.exception.nr = nr;
219 vcpu->arch.exception.error_code = error_code;
298101da
AK		 220}
221EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
222
223static void __queue_exception(struct kvm_vcpu *vcpu)
224{
ad312c7c
ZX		 225 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
226 vcpu->arch.exception.has_error_code,
227 vcpu->arch.exception.error_code);
298101da
AK		 228}
229
a03490ed
CO		 230/*
231 * Load the pae pdptrs. Return true is they are all valid.
232 */
233int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
234{
235 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
236 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
237 int i;
238 int ret;
ad312c7c 239 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 240
a03490ed
CO		 241 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
242 offset * sizeof(u64), sizeof(pdpte));
243 if (ret < 0) {
244 ret = 0;
245 goto out;
246 }
247 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 248 if (is_present_gpte(pdpte[i]) &&
20c466b5 249 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 250 ret = 0;
251 goto out;
252 }
253 }
254 ret = 1;
255
ad312c7c 256 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 257 __set_bit(VCPU_EXREG_PDPTR,
258 (unsigned long *)&vcpu->arch.regs_avail);
259 __set_bit(VCPU_EXREG_PDPTR,
260 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 261out:
a03490ed
CO		 262
263 return ret;
264}
cc4b6871 265EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 266
d835dfec
AK		 267static bool pdptrs_changed(struct kvm_vcpu *vcpu)
268{
ad312c7c 269 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 270 bool changed = true;
271 int r;
272
273 if (is_long_mode(vcpu) || !is_pae(vcpu))
274 return false;
275
6de4f3ad
AK		 276 if (!test_bit(VCPU_EXREG_PDPTR,
277 (unsigned long *)&vcpu->arch.regs_avail))
278 return true;
279
ad312c7c 280 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 281 if (r < 0)
282 goto out;
ad312c7c 283 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 284out:
d835dfec
AK		 285
286 return changed;
287}
288
2d3ad1f4 289void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 290{
291 if (cr0 & CR0_RESERVED_BITS) {
292 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 293 cr0, vcpu->arch.cr0);
c1a5d4f9 294 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 295 return;
296 }
297
298 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
299 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 300 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 301 return;
302 }
303
304 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
305 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
306 "and a clear PE flag\n");
c1a5d4f9 307 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 308 return;
309 }
310
311 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
312#ifdef CONFIG_X86_64
ad312c7c 313 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 314 int cs_db, cs_l;
315
316 if (!is_pae(vcpu)) {
317 printk(KERN_DEBUG "set_cr0: #GP, start paging "
318 "in long mode while PAE is disabled\n");
c1a5d4f9 319 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 320 return;
321 }
322 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
323 if (cs_l) {
324 printk(KERN_DEBUG "set_cr0: #GP, start paging "
325 "in long mode while CS.L == 1\n");
c1a5d4f9 326 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 327 return;
328
329 }
330 } else
331#endif
ad312c7c 332 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 333 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
334 "reserved bits\n");
c1a5d4f9 335 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 336 return;
337 }
338
339 }
340
341 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 342 vcpu->arch.cr0 = cr0;
a03490ed 343
a03490ed 344 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 345 return;
346}
2d3ad1f4 347EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 348
2d3ad1f4 349void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 350{
2d3ad1f4 351 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
a03490ed 352}
2d3ad1f4 353EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 354
2d3ad1f4 355void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 356{
a2edf57f
AK		 357 unsigned long old_cr4 = vcpu->arch.cr4;
358 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
359
a03490ed
CO		 360 if (cr4 & CR4_RESERVED_BITS) {
361 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 362 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 363 return;
364 }
365
366 if (is_long_mode(vcpu)) {
367 if (!(cr4 & X86_CR4_PAE)) {
368 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
369 "in long mode\n");
c1a5d4f9 370 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 371 return;
372 }
a2edf57f
AK		 373 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
374 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 375 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 376 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 377 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 378 return;
379 }
380
381 if (cr4 & X86_CR4_VMXE) {
382 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 383 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 384 return;
385 }
386 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 387 vcpu->arch.cr4 = cr4;
5a41accd 388 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
a03490ed 389 kvm_mmu_reset_context(vcpu);
a03490ed 390}
2d3ad1f4 391EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 392
2d3ad1f4 393void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 394{
ad312c7c 395 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 396 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 397 kvm_mmu_flush_tlb(vcpu);
398 return;
399 }
400
a03490ed
CO		 401 if (is_long_mode(vcpu)) {
402 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
403 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 404 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 405 return;
406 }
407 } else {
408 if (is_pae(vcpu)) {
409 if (cr3 & CR3_PAE_RESERVED_BITS) {
410 printk(KERN_DEBUG
411 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 412 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 413 return;
414 }
415 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
416 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
417 "reserved bits\n");
c1a5d4f9 418 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 419 return;
420 }
421 }
422 /*
423 * We don't check reserved bits in nonpae mode, because
424 * this isn't enforced, and VMware depends on this.
425 */
426 }
427
a03490ed
CO		 428 /*
429 * Does the new cr3 value map to physical memory? (Note, we
430 * catch an invalid cr3 even in real-mode, because it would
431 * cause trouble later on when we turn on paging anyway.)
432 *
433 * A real CPU would silently accept an invalid cr3 and would
434 * attempt to use it - with largely undefined (and often hard
435 * to debug) behavior on the guest side.
436 */
437 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 438 kvm_inject_gp(vcpu, 0);
a03490ed 439 else {
ad312c7c
ZX		 440 vcpu->arch.cr3 = cr3;
441 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 442 }
a03490ed 443}
2d3ad1f4 444EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 445
2d3ad1f4 446void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 447{
448 if (cr8 & CR8_RESERVED_BITS) {
449 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 450 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 451 return;
452 }
453 if (irqchip_in_kernel(vcpu->kvm))
454 kvm_lapic_set_tpr(vcpu, cr8);
455 else
ad312c7c 456 vcpu->arch.cr8 = cr8;
a03490ed 457}
2d3ad1f4 458EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 459
2d3ad1f4 460unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 461{
462 if (irqchip_in_kernel(vcpu->kvm))
463 return kvm_lapic_get_cr8(vcpu);
464 else
ad312c7c 465 return vcpu->arch.cr8;
a03490ed 466}
2d3ad1f4 467EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 468
d8017474
AG		 469static inline u32 bit(int bitno)
470{
471 return 1 << (bitno & 31);
472}
473
043405e1
CO		 474/*
475 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
476 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
477 *
478 * This list is modified at module load time to reflect the
479 * capabilities of the host cpu.
480 */
481static u32 msrs_to_save[] = {
482 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
483 MSR_K6_STAR,
484#ifdef CONFIG_X86_64
485 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
486#endif
af24a4e4 487 MSR_IA32_TSC, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
b286d5d8 488 MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 489};
490
491static unsigned num_msrs_to_save;
492
493static u32 emulated_msrs[] = {
494 MSR_IA32_MISC_ENABLE,
495};
496
15c4a640
CO		 497static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
498{
f2b4b7dd 499 if (efer & efer_reserved_bits) {
15c4a640
CO		 500 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
501 efer);
c1a5d4f9 502 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 503 return;
504 }
505
506 if (is_paging(vcpu)
ad312c7c 507 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 508 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 509 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 510 return;
511 }
512
1b2fd70c
AG		 513 if (efer & EFER_FFXSR) {
514 struct kvm_cpuid_entry2 *feat;
515
516 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
517 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
518 printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
519 kvm_inject_gp(vcpu, 0);
520 return;
521 }
522 }
523
d8017474
AG		 524 if (efer & EFER_SVME) {
525 struct kvm_cpuid_entry2 *feat;
526
527 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
528 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
529 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
530 kvm_inject_gp(vcpu, 0);
531 return;
532 }
533 }
534
15c4a640
CO		 535 kvm_x86_ops->set_efer(vcpu, efer);
536
537 efer &= ~EFER_LMA;
ad312c7c 538 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 539
ad312c7c 540 vcpu->arch.shadow_efer = efer;
9645bb56
AK		 541
542 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
543 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 544}
545
f2b4b7dd
JR		 546void kvm_enable_efer_bits(u64 mask)
547{
548 efer_reserved_bits &= ~mask;
549}
550EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
551
552
15c4a640
CO		 553/*
554 * Writes msr value into into the appropriate "register".
555 * Returns 0 on success, non-0 otherwise.
556 * Assumes vcpu_load() was already called.
557 */
558int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
559{
560 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
561}
562
313a3dc7
CO		 563/*
564 * Adapt set_msr() to msr_io()'s calling convention
565 */
566static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
567{
568 return kvm_set_msr(vcpu, index, *data);
569}
570
18068523
GOC		 571static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
572{
573 static int version;
50d0a0f9
GH		 574 struct pvclock_wall_clock wc;
575 struct timespec now, sys, boot;
18068523
GOC		 576
577 if (!wall_clock)
578 return;
579
580 version++;
581
18068523
GOC		 582 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
583
50d0a0f9
GH		 584 /*
585 * The guest calculates current wall clock time by adding
586 * system time (updated by kvm_write_guest_time below) to the
587 * wall clock specified here. guest system time equals host
588 * system time for us, thus we must fill in host boot time here.
589 */
590 now = current_kernel_time();
591 ktime_get_ts(&sys);
592 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
593
594 wc.sec = boot.tv_sec;
595 wc.nsec = boot.tv_nsec;
596 wc.version = version;
18068523
GOC		 597
598 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
599
600 version++;
601 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 602}
603
50d0a0f9
GH		 604static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
605{
606 uint32_t quotient, remainder;
607
608 /* Don't try to replace with do_div(), this one calculates
609 * "(dividend << 32) / divisor" */
610 __asm__ ( "divl %4"
611 : "=a" (quotient), "=d" (remainder)
612 : "0" (0), "1" (dividend), "r" (divisor) );
613 return quotient;
614}
615
616static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
617{
618 uint64_t nsecs = 1000000000LL;
619 int32_t shift = 0;
620 uint64_t tps64;
621 uint32_t tps32;
622
623 tps64 = tsc_khz * 1000LL;
624 while (tps64 > nsecs*2) {
625 tps64 >>= 1;
626 shift--;
627 }
628
629 tps32 = (uint32_t)tps64;
630 while (tps32 <= (uint32_t)nsecs) {
631 tps32 <<= 1;
632 shift++;
633 }
634
635 hv_clock->tsc_shift = shift;
636 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
637
638 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 639 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 640 hv_clock->tsc_to_system_mul);
641}
642
c8076604
GH		 643static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
644
18068523
GOC		 645static void kvm_write_guest_time(struct kvm_vcpu *v)
646{
647 struct timespec ts;
648 unsigned long flags;
649 struct kvm_vcpu_arch *vcpu = &v->arch;
650 void *shared_kaddr;
463656c0 651 unsigned long this_tsc_khz;
18068523
GOC		 652
653 if ((!vcpu->time_page))
654 return;
655
463656c0
AK		 656 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
657 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
658 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
659 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 660 }
463656c0 661 put_cpu_var(cpu_tsc_khz);
50d0a0f9 662
18068523
GOC		 663 /* Keep irq disabled to prevent changes to the clock */
664 local_irq_save(flags);
af24a4e4 665 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523
GOC		 666 ktime_get_ts(&ts);
667 local_irq_restore(flags);
668
669 /* With all the info we got, fill in the values */
670
671 vcpu->hv_clock.system_time = ts.tv_nsec +
672 (NSEC_PER_SEC * (u64)ts.tv_sec);
673 /*
674 * The interface expects us to write an even number signaling that the
675 * update is finished. Since the guest won't see the intermediate
50d0a0f9 676 * state, we just increase by 2 at the end.
18068523 677 */
50d0a0f9 678 vcpu->hv_clock.version += 2;
18068523
GOC		 679
680 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
681
682 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 683 sizeof(vcpu->hv_clock));
18068523
GOC		 684
685 kunmap_atomic(shared_kaddr, KM_USER0);
686
687 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
688}
689
c8076604
GH		 690static int kvm_request_guest_time_update(struct kvm_vcpu *v)
691{
692 struct kvm_vcpu_arch *vcpu = &v->arch;
693
694 if (!vcpu->time_page)
695 return 0;
696 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
697 return 1;
698}
699
9ba075a6
AK		 700static bool msr_mtrr_valid(unsigned msr)
701{
702 switch (msr) {
703 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
704 case MSR_MTRRfix64K_00000:
705 case MSR_MTRRfix16K_80000:
706 case MSR_MTRRfix16K_A0000:
707 case MSR_MTRRfix4K_C0000:
708 case MSR_MTRRfix4K_C8000:
709 case MSR_MTRRfix4K_D0000:
710 case MSR_MTRRfix4K_D8000:
711 case MSR_MTRRfix4K_E0000:
712 case MSR_MTRRfix4K_E8000:
713 case MSR_MTRRfix4K_F0000:
714 case MSR_MTRRfix4K_F8000:
715 case MSR_MTRRdefType:
716 case MSR_IA32_CR_PAT:
717 return true;
718 case 0x2f8:
719 return true;
720 }
721 return false;
722}
723
d6289b93
MT		 724static bool valid_pat_type(unsigned t)
725{
726 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
727}
728
729static bool valid_mtrr_type(unsigned t)
730{
731 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
732}
733
734static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
735{
736 int i;
737
738 if (!msr_mtrr_valid(msr))
739 return false;
740
741 if (msr == MSR_IA32_CR_PAT) {
742 for (i = 0; i < 8; i++)
743 if (!valid_pat_type((data >> (i * 8)) & 0xff))
744 return false;
745 return true;
746 } else if (msr == MSR_MTRRdefType) {
747 if (data & ~0xcff)
748 return false;
749 return valid_mtrr_type(data & 0xff);
750 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
751 for (i = 0; i < 8 ; i++)
752 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
753 return false;
754 return true;
755 }
756
757 /* variable MTRRs */
758 return valid_mtrr_type(data & 0xff);
759}
760
9ba075a6
AK		 761static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
762{
0bed3b56
SY		 763 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
764
d6289b93 765 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 766 return 1;
767
0bed3b56
SY		 768 if (msr == MSR_MTRRdefType) {
769 vcpu->arch.mtrr_state.def_type = data;
770 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
771 } else if (msr == MSR_MTRRfix64K_00000)
772 p[0] = data;
773 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
774 p[1 + msr - MSR_MTRRfix16K_80000] = data;
775 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
776 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
777 else if (msr == MSR_IA32_CR_PAT)
778 vcpu->arch.pat = data;
779 else { /* Variable MTRRs */
780 int idx, is_mtrr_mask;
781 u64 *pt;
782
783 idx = (msr - 0x200) / 2;
784 is_mtrr_mask = msr - 0x200 - 2 * idx;
785 if (!is_mtrr_mask)
786 pt =
787 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
788 else
789 pt =
790 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
791 *pt = data;
792 }
793
794 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 795 return 0;
796}
15c4a640 797
890ca9ae 798static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 799{
890ca9ae
HY		 800 u64 mcg_cap = vcpu->arch.mcg_cap;
801 unsigned bank_num = mcg_cap & 0xff;
802
15c4a640 803 switch (msr) {
15c4a640 804 case MSR_IA32_MCG_STATUS:
890ca9ae 805 vcpu->arch.mcg_status = data;
15c4a640 806 break;
c7ac679c 807 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 808 if (!(mcg_cap & MCG_CTL_P))
809 return 1;
810 if (data != 0 && data != ~(u64)0)
811 return -1;
812 vcpu->arch.mcg_ctl = data;
813 break;
814 default:
815 if (msr >= MSR_IA32_MC0_CTL &&
816 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
817 u32 offset = msr - MSR_IA32_MC0_CTL;
818 /* only 0 or all 1s can be written to IA32_MCi_CTL */
819 if ((offset & 0x3) == 0 &&
820 data != 0 && data != ~(u64)0)
821 return -1;
822 vcpu->arch.mce_banks[offset] = data;
823 break;
824 }
825 return 1;
826 }
827 return 0;
828}
829
830int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
831{
832 switch (msr) {
833 case MSR_EFER:
834 set_efer(vcpu, data);
c7ac679c 835 break;
b5e2fec0
AG		 836 case MSR_IA32_DEBUGCTLMSR:
837 if (!data) {
838 /* We support the non-activated case already */
839 break;
840 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
841 /* Values other than LBR and BTF are vendor-specific,
842 thus reserved and should throw a #GP */
843 return 1;
844 }
845 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
846 __func__, data);
847 break;
15c4a640
CO		 848 case MSR_IA32_UCODE_REV:
849 case MSR_IA32_UCODE_WRITE:
61a6bd67 850 case MSR_VM_HSAVE_PA:
15c4a640 851 break;
9ba075a6
AK		 852 case 0x200 ... 0x2ff:
853 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 854 case MSR_IA32_APICBASE:
855 kvm_set_apic_base(vcpu, data);
856 break;
857 case MSR_IA32_MISC_ENABLE:
ad312c7c 858 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 859 break;
18068523
GOC		 860 case MSR_KVM_WALL_CLOCK:
861 vcpu->kvm->arch.wall_clock = data;
862 kvm_write_wall_clock(vcpu->kvm, data);
863 break;
864 case MSR_KVM_SYSTEM_TIME: {
865 if (vcpu->arch.time_page) {
866 kvm_release_page_dirty(vcpu->arch.time_page);
867 vcpu->arch.time_page = NULL;
868 }
869
870 vcpu->arch.time = data;
871
872 /* we verify if the enable bit is set... */
873 if (!(data & 1))
874 break;
875
876 /* ...but clean it before doing the actual write */
877 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
878
18068523
GOC		 879 vcpu->arch.time_page =
880 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 881
882 if (is_error_page(vcpu->arch.time_page)) {
883 kvm_release_page_clean(vcpu->arch.time_page);
884 vcpu->arch.time_page = NULL;
885 }
886
c8076604 887 kvm_request_guest_time_update(vcpu);
18068523
GOC		 888 break;
889 }
890ca9ae
HY		 890 case MSR_IA32_MCG_CTL:
891 case MSR_IA32_MCG_STATUS:
892 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
893 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 894
895 /* Performance counters are not protected by a CPUID bit,
896 * so we should check all of them in the generic path for the sake of
897 * cross vendor migration.
898 * Writing a zero into the event select MSRs disables them,
899 * which we perfectly emulate ;-). Any other value should be at least
900 * reported, some guests depend on them.
901 */
902 case MSR_P6_EVNTSEL0:
903 case MSR_P6_EVNTSEL1:
904 case MSR_K7_EVNTSEL0:
905 case MSR_K7_EVNTSEL1:
906 case MSR_K7_EVNTSEL2:
907 case MSR_K7_EVNTSEL3:
908 if (data != 0)
909 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
910 "0x%x data 0x%llx\n", msr, data);
911 break;
912 /* at least RHEL 4 unconditionally writes to the perfctr registers,
913 * so we ignore writes to make it happy.
914 */
915 case MSR_P6_PERFCTR0:
916 case MSR_P6_PERFCTR1:
917 case MSR_K7_PERFCTR0:
918 case MSR_K7_PERFCTR1:
919 case MSR_K7_PERFCTR2:
920 case MSR_K7_PERFCTR3:
921 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
922 "0x%x data 0x%llx\n", msr, data);
923 break;
15c4a640 924 default:
565f1fbd 925 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", msr, data);
15c4a640
CO		 926 return 1;
927 }
928 return 0;
929}
930EXPORT_SYMBOL_GPL(kvm_set_msr_common);
931
932
933/*
934 * Reads an msr value (of 'msr_index') into 'pdata'.
935 * Returns 0 on success, non-0 otherwise.
936 * Assumes vcpu_load() was already called.
937 */
938int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
939{
940 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
941}
942
9ba075a6
AK		 943static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
944{
0bed3b56
SY		 945 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
946
9ba075a6
AK		 947 if (!msr_mtrr_valid(msr))
948 return 1;
949
0bed3b56
SY		 950 if (msr == MSR_MTRRdefType)
951 *pdata = vcpu->arch.mtrr_state.def_type +
952 (vcpu->arch.mtrr_state.enabled << 10);
953 else if (msr == MSR_MTRRfix64K_00000)
954 *pdata = p[0];
955 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
956 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
957 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
958 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
959 else if (msr == MSR_IA32_CR_PAT)
960 *pdata = vcpu->arch.pat;
961 else { /* Variable MTRRs */
962 int idx, is_mtrr_mask;
963 u64 *pt;
964
965 idx = (msr - 0x200) / 2;
966 is_mtrr_mask = msr - 0x200 - 2 * idx;
967 if (!is_mtrr_mask)
968 pt =
969 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
970 else
971 pt =
972 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
973 *pdata = *pt;
974 }
975
9ba075a6
AK		 976 return 0;
977}
978
890ca9ae 979static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 980{
981 u64 data;
890ca9ae
HY		 982 u64 mcg_cap = vcpu->arch.mcg_cap;
983 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 984
985 switch (msr) {
15c4a640
CO		 986 case MSR_IA32_P5_MC_ADDR:
987 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 988 data = 0;
989 break;
15c4a640 990 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 991 data = vcpu->arch.mcg_cap;
992 break;
c7ac679c 993 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 994 if (!(mcg_cap & MCG_CTL_P))
995 return 1;
996 data = vcpu->arch.mcg_ctl;
997 break;
998 case MSR_IA32_MCG_STATUS:
999 data = vcpu->arch.mcg_status;
1000 break;
1001 default:
1002 if (msr >= MSR_IA32_MC0_CTL &&
1003 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1004 u32 offset = msr - MSR_IA32_MC0_CTL;
1005 data = vcpu->arch.mce_banks[offset];
1006 break;
1007 }
1008 return 1;
1009 }
1010 *pdata = data;
1011 return 0;
1012}
1013
1014int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1015{
1016 u64 data;
1017
1018 switch (msr) {
890ca9ae 1019 case MSR_IA32_PLATFORM_ID:
15c4a640 1020 case MSR_IA32_UCODE_REV:
15c4a640 1021 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1022 case MSR_IA32_DEBUGCTLMSR:
1023 case MSR_IA32_LASTBRANCHFROMIP:
1024 case MSR_IA32_LASTBRANCHTOIP:
1025 case MSR_IA32_LASTINTFROMIP:
1026 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1027 case MSR_K8_SYSCFG:
1028 case MSR_K7_HWCR:
61a6bd67 1029 case MSR_VM_HSAVE_PA:
7fe29e0f
AS		 1030 case MSR_P6_EVNTSEL0:
1031 case MSR_P6_EVNTSEL1:
9e699624 1032 case MSR_K7_EVNTSEL0:
15c4a640
CO		 1033 data = 0;
1034 break;
9ba075a6
AK		 1035 case MSR_MTRRcap:
1036 data = 0x500 | KVM_NR_VAR_MTRR;
1037 break;
1038 case 0x200 ... 0x2ff:
1039 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1040 case 0xcd: /* fsb frequency */
1041 data = 3;
1042 break;
1043 case MSR_IA32_APICBASE:
1044 data = kvm_get_apic_base(vcpu);
1045 break;
1046 case MSR_IA32_MISC_ENABLE:
ad312c7c 1047 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1048 break;
847f0ad8
AG		 1049 case MSR_IA32_PERF_STATUS:
1050 /* TSC increment by tick */
1051 data = 1000ULL;
1052 /* CPU multiplier */
1053 data |= (((uint64_t)4ULL) << 40);
1054 break;
15c4a640 1055 case MSR_EFER:
ad312c7c 1056 data = vcpu->arch.shadow_efer;
15c4a640 1057 break;
18068523
GOC		 1058 case MSR_KVM_WALL_CLOCK:
1059 data = vcpu->kvm->arch.wall_clock;
1060 break;
1061 case MSR_KVM_SYSTEM_TIME:
1062 data = vcpu->arch.time;
1063 break;
890ca9ae
HY		 1064 case MSR_IA32_P5_MC_ADDR:
1065 case MSR_IA32_P5_MC_TYPE:
1066 case MSR_IA32_MCG_CAP:
1067 case MSR_IA32_MCG_CTL:
1068 case MSR_IA32_MCG_STATUS:
1069 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1070 return get_msr_mce(vcpu, msr, pdata);
15c4a640
CO		 1071 default:
1072 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1073 return 1;
1074 }
1075 *pdata = data;
1076 return 0;
1077}
1078EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1079
313a3dc7
CO		 1080/*
1081 * Read or write a bunch of msrs. All parameters are kernel addresses.
1082 *
1083 * @return number of msrs set successfully.
1084 */
1085static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1086 struct kvm_msr_entry *entries,
1087 int (*do_msr)(struct kvm_vcpu *vcpu,
1088 unsigned index, u64 *data))
1089{
1090 int i;
1091
1092 vcpu_load(vcpu);
1093
3200f405 1094 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1095 for (i = 0; i < msrs->nmsrs; ++i)
1096 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1097 break;
3200f405 1098 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1099
1100 vcpu_put(vcpu);
1101
1102 return i;
1103}
1104
1105/*
1106 * Read or write a bunch of msrs. Parameters are user addresses.
1107 *
1108 * @return number of msrs set successfully.
1109 */
1110static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1111 int (*do_msr)(struct kvm_vcpu *vcpu,
1112 unsigned index, u64 *data),
1113 int writeback)
1114{
1115 struct kvm_msrs msrs;
1116 struct kvm_msr_entry *entries;
1117 int r, n;
1118 unsigned size;
1119
1120 r = -EFAULT;
1121 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1122 goto out;
1123
1124 r = -E2BIG;
1125 if (msrs.nmsrs >= MAX_IO_MSRS)
1126 goto out;
1127
1128 r = -ENOMEM;
1129 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1130 entries = vmalloc(size);
1131 if (!entries)
1132 goto out;
1133
1134 r = -EFAULT;
1135 if (copy_from_user(entries, user_msrs->entries, size))
1136 goto out_free;
1137
1138 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1139 if (r < 0)
1140 goto out_free;
1141
1142 r = -EFAULT;
1143 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1144 goto out_free;
1145
1146 r = n;
1147
1148out_free:
1149 vfree(entries);
1150out:
1151 return r;
1152}
1153
018d00d2
ZX		 1154int kvm_dev_ioctl_check_extension(long ext)
1155{
1156 int r;
1157
1158 switch (ext) {
1159 case KVM_CAP_IRQCHIP:
1160 case KVM_CAP_HLT:
1161 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1162 case KVM_CAP_SET_TSS_ADDR:
07716717 1163 case KVM_CAP_EXT_CPUID:
c8076604 1164 case KVM_CAP_CLOCKSOURCE:
7837699f 1165 case KVM_CAP_PIT:
a28e4f5a 1166 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1167 case KVM_CAP_MP_STATE:
ed848624 1168 case KVM_CAP_SYNC_MMU:
52d939a0 1169 case KVM_CAP_REINJECT_CONTROL:
4925663a 1170 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1171 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1172 case KVM_CAP_IRQFD:
c5ff41ce 1173 case KVM_CAP_PIT2:
018d00d2
ZX		 1174 r = 1;
1175 break;
542472b5
LV		 1176 case KVM_CAP_COALESCED_MMIO:
1177 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1178 break;
774ead3a
AK		 1179 case KVM_CAP_VAPIC:
1180 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1181 break;
f725230a
AK		 1182 case KVM_CAP_NR_VCPUS:
1183 r = KVM_MAX_VCPUS;
1184 break;
a988b910
AK		 1185 case KVM_CAP_NR_MEMSLOTS:
1186 r = KVM_MEMORY_SLOTS;
1187 break;
2f333bcb
MT		 1188 case KVM_CAP_PV_MMU:
1189 r = !tdp_enabled;
1190 break;
62c476c7 1191 case KVM_CAP_IOMMU:
19de40a8 1192 r = iommu_found();
62c476c7 1193 break;
890ca9ae
HY		 1194 case KVM_CAP_MCE:
1195 r = KVM_MAX_MCE_BANKS;
1196 break;
018d00d2
ZX		 1197 default:
1198 r = 0;
1199 break;
1200 }
1201 return r;
1202
1203}
1204
043405e1
CO		 1205long kvm_arch_dev_ioctl(struct file *filp,
1206 unsigned int ioctl, unsigned long arg)
1207{
1208 void __user *argp = (void __user *)arg;
1209 long r;
1210
1211 switch (ioctl) {
1212 case KVM_GET_MSR_INDEX_LIST: {
1213 struct kvm_msr_list __user *user_msr_list = argp;
1214 struct kvm_msr_list msr_list;
1215 unsigned n;
1216
1217 r = -EFAULT;
1218 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1219 goto out;
1220 n = msr_list.nmsrs;
1221 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1222 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1223 goto out;
1224 r = -E2BIG;
e125e7b6 1225 if (n < msr_list.nmsrs)
043405e1
CO		 1226 goto out;
1227 r = -EFAULT;
1228 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1229 num_msrs_to_save * sizeof(u32)))
1230 goto out;
e125e7b6 1231 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1232 &emulated_msrs,
1233 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1234 goto out;
1235 r = 0;
1236 break;
1237 }
674eea0f
AK		 1238 case KVM_GET_SUPPORTED_CPUID: {
1239 struct kvm_cpuid2 __user *cpuid_arg = argp;
1240 struct kvm_cpuid2 cpuid;
1241
1242 r = -EFAULT;
1243 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1244 goto out;
1245 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1246 cpuid_arg->entries);
674eea0f
AK		 1247 if (r)
1248 goto out;
1249
1250 r = -EFAULT;
1251 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1252 goto out;
1253 r = 0;
1254 break;
1255 }
890ca9ae
HY		 1256 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1257 u64 mce_cap;
1258
1259 mce_cap = KVM_MCE_CAP_SUPPORTED;
1260 r = -EFAULT;
1261 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1262 goto out;
1263 r = 0;
1264 break;
1265 }
043405e1
CO		 1266 default:
1267 r = -EINVAL;
1268 }
1269out:
1270 return r;
1271}
1272
313a3dc7
CO		 1273void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1274{
1275 kvm_x86_ops->vcpu_load(vcpu, cpu);
c8076604 1276 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1277}
1278
1279void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1280{
1281 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 1282 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1283}
1284
07716717 1285static int is_efer_nx(void)
313a3dc7 1286{
e286e86e 1287 unsigned long long efer = 0;
313a3dc7 1288
e286e86e 1289 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1290 return efer & EFER_NX;
1291}
1292
1293static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1294{
1295 int i;
1296 struct kvm_cpuid_entry2 *e, *entry;
1297
313a3dc7 1298 entry = NULL;
ad312c7c
ZX		 1299 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1300 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1301 if (e->function == 0x80000001) {
1302 entry = e;
1303 break;
1304 }
1305 }
07716717 1306 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1307 entry->edx &= ~(1 << 20);
1308 printk(KERN_INFO "kvm: guest NX capability removed\n");
1309 }
1310}
1311
07716717 1312/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1313static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1314 struct kvm_cpuid *cpuid,
1315 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1316{
1317 int r, i;
1318 struct kvm_cpuid_entry *cpuid_entries;
1319
1320 r = -E2BIG;
1321 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1322 goto out;
1323 r = -ENOMEM;
1324 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1325 if (!cpuid_entries)
1326 goto out;
1327 r = -EFAULT;
1328 if (copy_from_user(cpuid_entries, entries,
1329 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1330 goto out_free;
1331 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1332 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1333 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1334 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1335 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1336 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1337 vcpu->arch.cpuid_entries[i].index = 0;
1338 vcpu->arch.cpuid_entries[i].flags = 0;
1339 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1340 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1341 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1342 }
1343 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1344 cpuid_fix_nx_cap(vcpu);
1345 r = 0;
1346
1347out_free:
1348 vfree(cpuid_entries);
1349out:
1350 return r;
1351}
1352
1353static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1354 struct kvm_cpuid2 *cpuid,
1355 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1356{
1357 int r;
1358
1359 r = -E2BIG;
1360 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1361 goto out;
1362 r = -EFAULT;
ad312c7c 1363 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1364 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1365 goto out;
ad312c7c 1366 vcpu->arch.cpuid_nent = cpuid->nent;
313a3dc7
CO		 1367 return 0;
1368
1369out:
1370 return r;
1371}
1372
07716717 1373static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1374 struct kvm_cpuid2 *cpuid,
1375 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1376{
1377 int r;
1378
1379 r = -E2BIG;
ad312c7c 1380 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1381 goto out;
1382 r = -EFAULT;
ad312c7c 1383 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1384 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1385 goto out;
1386 return 0;
1387
1388out:
ad312c7c 1389 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1390 return r;
1391}
1392
07716717 1393static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1394 u32 index)
07716717
DK		 1395{
1396 entry->function = function;
1397 entry->index = index;
1398 cpuid_count(entry->function, entry->index,
19355475 1399 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1400 entry->flags = 0;
1401}
1402
7faa4ee1
AK		 1403#define F(x) bit(X86_FEATURE_##x)
1404
07716717
DK		 1405static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1406 u32 index, int *nent, int maxnent)
1407{
7faa4ee1 1408 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1409#ifdef CONFIG_X86_64
7faa4ee1
AK		 1410 unsigned f_lm = F(LM);
1411#else
1412 unsigned f_lm = 0;
07716717 1413#endif
7faa4ee1
AK		 1414
1415 /* cpuid 1.edx */
1416 const u32 kvm_supported_word0_x86_features =
1417 F(FPU) | F(VME) | F(DE) | F(PSE) |
1418 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1419 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1420 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1421 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1422 0 /* Reserved, DS, ACPI */ | F(MMX) |
1423 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1424 0 /* HTT, TM, Reserved, PBE */;
1425 /* cpuid 0x80000001.edx */
1426 const u32 kvm_supported_word1_x86_features =
1427 F(FPU) | F(VME) | F(DE) | F(PSE) |
1428 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1429 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1430 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1431 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1432 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
1433 F(FXSR) | F(FXSR_OPT) | 0 /* GBPAGES */ | 0 /* RDTSCP */ |
1434 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1435 /* cpuid 1.ecx */
1436 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1437 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1438 0 /* DS-CPL, VMX, SMX, EST */ |
1439 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1440 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1441 0 /* Reserved, DCA */ | F(XMM4_1) |
1442 F(XMM4_2) | 0 /* x2APIC */ | F(MOVBE) | F(POPCNT) |
1443 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1444 /* cpuid 0x80000001.ecx */
07716717 1445 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1446 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1447 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1448 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1449 0 /* SKINIT */ | 0 /* WDT */;
07716717 1450
19355475 1451 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1452 get_cpu();
1453 do_cpuid_1_ent(entry, function, index);
1454 ++*nent;
1455
1456 switch (function) {
1457 case 0:
1458 entry->eax = min(entry->eax, (u32)0xb);
1459 break;
1460 case 1:
1461 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1462 entry->ecx &= kvm_supported_word4_x86_features;
07716717
DK		 1463 break;
1464 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1465 * may return different values. This forces us to get_cpu() before
1466 * issuing the first command, and also to emulate this annoying behavior
1467 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1468 case 2: {
1469 int t, times = entry->eax & 0xff;
1470
1471 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1472 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1473 for (t = 1; t < times && *nent < maxnent; ++t) {
1474 do_cpuid_1_ent(&entry[t], function, 0);
1475 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1476 ++*nent;
1477 }
1478 break;
1479 }
1480 /* function 4 and 0xb have additional index. */
1481 case 4: {
14af3f3c 1482 int i, cache_type;
07716717
DK		 1483
1484 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1485 /* read more entries until cache_type is zero */
14af3f3c
HH		 1486 for (i = 1; *nent < maxnent; ++i) {
1487 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1488 if (!cache_type)
1489 break;
14af3f3c
HH		 1490 do_cpuid_1_ent(&entry[i], function, i);
1491 entry[i].flags |=
07716717
DK		 1492 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1493 ++*nent;
1494 }
1495 break;
1496 }
1497 case 0xb: {
14af3f3c 1498 int i, level_type;
07716717
DK		 1499
1500 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1501 /* read more entries until level_type is zero */
14af3f3c 1502 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1503 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1504 if (!level_type)
1505 break;
14af3f3c
HH		 1506 do_cpuid_1_ent(&entry[i], function, i);
1507 entry[i].flags |=
07716717
DK		 1508 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1509 ++*nent;
1510 }
1511 break;
1512 }
1513 case 0x80000000:
1514 entry->eax = min(entry->eax, 0x8000001a);
1515 break;
1516 case 0x80000001:
1517 entry->edx &= kvm_supported_word1_x86_features;
1518 entry->ecx &= kvm_supported_word6_x86_features;
1519 break;
1520 }
1521 put_cpu();
1522}
1523
7faa4ee1
AK		 1524#undef F
1525
674eea0f 1526static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1527 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1528{
1529 struct kvm_cpuid_entry2 *cpuid_entries;
1530 int limit, nent = 0, r = -E2BIG;
1531 u32 func;
1532
1533 if (cpuid->nent < 1)
1534 goto out;
1535 r = -ENOMEM;
1536 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1537 if (!cpuid_entries)
1538 goto out;
1539
1540 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1541 limit = cpuid_entries[0].eax;
1542 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1543 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1544 &nent, cpuid->nent);
07716717
DK		 1545 r = -E2BIG;
1546 if (nent >= cpuid->nent)
1547 goto out_free;
1548
1549 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1550 limit = cpuid_entries[nent - 1].eax;
1551 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1552 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1553 &nent, cpuid->nent);
cb007648
MM		 1554 r = -E2BIG;
1555 if (nent >= cpuid->nent)
1556 goto out_free;
1557
07716717
DK		 1558 r = -EFAULT;
1559 if (copy_to_user(entries, cpuid_entries,
19355475 1560 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1561 goto out_free;
1562 cpuid->nent = nent;
1563 r = 0;
1564
1565out_free:
1566 vfree(cpuid_entries);
1567out:
1568 return r;
1569}
1570
313a3dc7
CO		 1571static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1572 struct kvm_lapic_state *s)
1573{
1574 vcpu_load(vcpu);
ad312c7c 1575 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1576 vcpu_put(vcpu);
1577
1578 return 0;
1579}
1580
1581static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1582 struct kvm_lapic_state *s)
1583{
1584 vcpu_load(vcpu);
ad312c7c 1585 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7
CO		 1586 kvm_apic_post_state_restore(vcpu);
1587 vcpu_put(vcpu);
1588
1589 return 0;
1590}
1591
f77bc6a4
ZX		 1592static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1593 struct kvm_interrupt *irq)
1594{
1595 if (irq->irq < 0 || irq->irq >= 256)
1596 return -EINVAL;
1597 if (irqchip_in_kernel(vcpu->kvm))
1598 return -ENXIO;
1599 vcpu_load(vcpu);
1600
66fd3f7f 1601 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 1602
1603 vcpu_put(vcpu);
1604
1605 return 0;
1606}
1607
c4abb7c9
JK		 1608static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1609{
1610 vcpu_load(vcpu);
1611 kvm_inject_nmi(vcpu);
1612 vcpu_put(vcpu);
1613
1614 return 0;
1615}
1616
b209749f
AK		 1617static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1618 struct kvm_tpr_access_ctl *tac)
1619{
1620 if (tac->flags)
1621 return -EINVAL;
1622 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1623 return 0;
1624}
1625
890ca9ae
HY		 1626static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
1627 u64 mcg_cap)
1628{
1629 int r;
1630 unsigned bank_num = mcg_cap & 0xff, bank;
1631
1632 r = -EINVAL;
1633 if (!bank_num)
1634 goto out;
1635 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
1636 goto out;
1637 r = 0;
1638 vcpu->arch.mcg_cap = mcg_cap;
1639 /* Init IA32_MCG_CTL to all 1s */
1640 if (mcg_cap & MCG_CTL_P)
1641 vcpu->arch.mcg_ctl = ~(u64)0;
1642 /* Init IA32_MCi_CTL to all 1s */
1643 for (bank = 0; bank < bank_num; bank++)
1644 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
1645out:
1646 return r;
1647}
1648
1649static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
1650 struct kvm_x86_mce *mce)
1651{
1652 u64 mcg_cap = vcpu->arch.mcg_cap;
1653 unsigned bank_num = mcg_cap & 0xff;
1654 u64 *banks = vcpu->arch.mce_banks;
1655
1656 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
1657 return -EINVAL;
1658 /*
1659 * if IA32_MCG_CTL is not all 1s, the uncorrected error
1660 * reporting is disabled
1661 */
1662 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
1663 vcpu->arch.mcg_ctl != ~(u64)0)
1664 return 0;
1665 banks += 4 * mce->bank;
1666 /*
1667 * if IA32_MCi_CTL is not all 1s, the uncorrected error
1668 * reporting is disabled for the bank
1669 */
1670 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
1671 return 0;
1672 if (mce->status & MCI_STATUS_UC) {
1673 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
1674 !(vcpu->arch.cr4 & X86_CR4_MCE)) {
1675 printk(KERN_DEBUG "kvm: set_mce: "
1676 "injects mce exception while "
1677 "previous one is in progress!\n");
1678 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
1679 return 0;
1680 }
1681 if (banks[1] & MCI_STATUS_VAL)
1682 mce->status |= MCI_STATUS_OVER;
1683 banks[2] = mce->addr;
1684 banks[3] = mce->misc;
1685 vcpu->arch.mcg_status = mce->mcg_status;
1686 banks[1] = mce->status;
1687 kvm_queue_exception(vcpu, MC_VECTOR);
1688 } else if (!(banks[1] & MCI_STATUS_VAL)
1689 || !(banks[1] & MCI_STATUS_UC)) {
1690 if (banks[1] & MCI_STATUS_VAL)
1691 mce->status |= MCI_STATUS_OVER;
1692 banks[2] = mce->addr;
1693 banks[3] = mce->misc;
1694 banks[1] = mce->status;
1695 } else
1696 banks[1] |= MCI_STATUS_OVER;
1697 return 0;
1698}
1699
313a3dc7
CO		 1700long kvm_arch_vcpu_ioctl(struct file *filp,
1701 unsigned int ioctl, unsigned long arg)
1702{
1703 struct kvm_vcpu *vcpu = filp->private_data;
1704 void __user *argp = (void __user *)arg;
1705 int r;
b772ff36 1706 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 1707
1708 switch (ioctl) {
1709 case KVM_GET_LAPIC: {
b772ff36 1710 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 1711
b772ff36
DH		 1712 r = -ENOMEM;
1713 if (!lapic)
1714 goto out;
1715 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 1716 if (r)
1717 goto out;
1718 r = -EFAULT;
b772ff36 1719 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 1720 goto out;
1721 r = 0;
1722 break;
1723 }
1724 case KVM_SET_LAPIC: {
b772ff36
DH		 1725 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1726 r = -ENOMEM;
1727 if (!lapic)
1728 goto out;
313a3dc7 1729 r = -EFAULT;
b772ff36 1730 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 1731 goto out;
b772ff36 1732 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 1733 if (r)
1734 goto out;
1735 r = 0;
1736 break;
1737 }
f77bc6a4
ZX		 1738 case KVM_INTERRUPT: {
1739 struct kvm_interrupt irq;
1740
1741 r = -EFAULT;
1742 if (copy_from_user(&irq, argp, sizeof irq))
1743 goto out;
1744 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1745 if (r)
1746 goto out;
1747 r = 0;
1748 break;
1749 }
c4abb7c9
JK		 1750 case KVM_NMI: {
1751 r = kvm_vcpu_ioctl_nmi(vcpu);
1752 if (r)
1753 goto out;
1754 r = 0;
1755 break;
1756 }
313a3dc7
CO		 1757 case KVM_SET_CPUID: {
1758 struct kvm_cpuid __user *cpuid_arg = argp;
1759 struct kvm_cpuid cpuid;
1760
1761 r = -EFAULT;
1762 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1763 goto out;
1764 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1765 if (r)
1766 goto out;
1767 break;
1768 }
07716717
DK		 1769 case KVM_SET_CPUID2: {
1770 struct kvm_cpuid2 __user *cpuid_arg = argp;
1771 struct kvm_cpuid2 cpuid;
1772
1773 r = -EFAULT;
1774 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1775 goto out;
1776 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 1777 cpuid_arg->entries);
07716717
DK		 1778 if (r)
1779 goto out;
1780 break;
1781 }
1782 case KVM_GET_CPUID2: {
1783 struct kvm_cpuid2 __user *cpuid_arg = argp;
1784 struct kvm_cpuid2 cpuid;
1785
1786 r = -EFAULT;
1787 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1788 goto out;
1789 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 1790 cpuid_arg->entries);
07716717
DK		 1791 if (r)
1792 goto out;
1793 r = -EFAULT;
1794 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1795 goto out;
1796 r = 0;
1797 break;
1798 }
313a3dc7
CO		 1799 case KVM_GET_MSRS:
1800 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1801 break;
1802 case KVM_SET_MSRS:
1803 r = msr_io(vcpu, argp, do_set_msr, 0);
1804 break;
b209749f
AK		 1805 case KVM_TPR_ACCESS_REPORTING: {
1806 struct kvm_tpr_access_ctl tac;
1807
1808 r = -EFAULT;
1809 if (copy_from_user(&tac, argp, sizeof tac))
1810 goto out;
1811 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1812 if (r)
1813 goto out;
1814 r = -EFAULT;
1815 if (copy_to_user(argp, &tac, sizeof tac))
1816 goto out;
1817 r = 0;
1818 break;
1819 };
b93463aa
AK		 1820 case KVM_SET_VAPIC_ADDR: {
1821 struct kvm_vapic_addr va;
1822
1823 r = -EINVAL;
1824 if (!irqchip_in_kernel(vcpu->kvm))
1825 goto out;
1826 r = -EFAULT;
1827 if (copy_from_user(&va, argp, sizeof va))
1828 goto out;
1829 r = 0;
1830 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1831 break;
1832 }
890ca9ae
HY		 1833 case KVM_X86_SETUP_MCE: {
1834 u64 mcg_cap;
1835
1836 r = -EFAULT;
1837 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
1838 goto out;
1839 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
1840 break;
1841 }
1842 case KVM_X86_SET_MCE: {
1843 struct kvm_x86_mce mce;
1844
1845 r = -EFAULT;
1846 if (copy_from_user(&mce, argp, sizeof mce))
1847 goto out;
1848 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
1849 break;
1850 }
313a3dc7
CO		 1851 default:
1852 r = -EINVAL;
1853 }
1854out:
7a6ce84c 1855 kfree(lapic);
313a3dc7
CO		 1856 return r;
1857}
1858
1fe779f8
CO		 1859static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1860{
1861 int ret;
1862
1863 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1864 return -1;
1865 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1866 return ret;
1867}
1868
1869static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1870 u32 kvm_nr_mmu_pages)
1871{
1872 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1873 return -EINVAL;
1874
72dc67a6 1875 down_write(&kvm->slots_lock);
7c8a83b7 1876 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 1877
1878 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1879 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1880
7c8a83b7 1881 spin_unlock(&kvm->mmu_lock);
72dc67a6 1882 up_write(&kvm->slots_lock);
1fe779f8
CO		 1883 return 0;
1884}
1885
1886static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1887{
f05e70ac 1888 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1889}
1890
e9f85cde
ZX		 1891gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1892{
1893 int i;
1894 struct kvm_mem_alias *alias;
1895
d69fb81f
ZX		 1896 for (i = 0; i < kvm->arch.naliases; ++i) {
1897 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1898 if (gfn >= alias->base_gfn
1899 && gfn < alias->base_gfn + alias->npages)
1900 return alias->target_gfn + gfn - alias->base_gfn;
1901 }
1902 return gfn;
1903}
1904
1fe779f8
CO		 1905/*
1906 * Set a new alias region. Aliases map a portion of physical memory into
1907 * another portion. This is useful for memory windows, for example the PC
1908 * VGA region.
1909 */
1910static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1911 struct kvm_memory_alias *alias)
1912{
1913 int r, n;
1914 struct kvm_mem_alias *p;
1915
1916 r = -EINVAL;
1917 /* General sanity checks */
1918 if (alias->memory_size & (PAGE_SIZE - 1))
1919 goto out;
1920 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1921 goto out;
1922 if (alias->slot >= KVM_ALIAS_SLOTS)
1923 goto out;
1924 if (alias->guest_phys_addr + alias->memory_size
1925 < alias->guest_phys_addr)
1926 goto out;
1927 if (alias->target_phys_addr + alias->memory_size
1928 < alias->target_phys_addr)
1929 goto out;
1930
72dc67a6 1931 down_write(&kvm->slots_lock);
a1708ce8 1932 spin_lock(&kvm->mmu_lock);
1fe779f8 1933
d69fb81f 1934 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 1935 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1936 p->npages = alias->memory_size >> PAGE_SHIFT;
1937 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1938
1939 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 1940 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 1941 break;
d69fb81f 1942 kvm->arch.naliases = n;
1fe779f8 1943
a1708ce8 1944 spin_unlock(&kvm->mmu_lock);
1fe779f8
CO		 1945 kvm_mmu_zap_all(kvm);
1946
72dc67a6 1947 up_write(&kvm->slots_lock);
1fe779f8
CO		 1948
1949 return 0;
1950
1951out:
1952 return r;
1953}
1954
1955static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1956{
1957 int r;
1958
1959 r = 0;
1960 switch (chip->chip_id) {
1961 case KVM_IRQCHIP_PIC_MASTER:
1962 memcpy(&chip->chip.pic,
1963 &pic_irqchip(kvm)->pics[0],
1964 sizeof(struct kvm_pic_state));
1965 break;
1966 case KVM_IRQCHIP_PIC_SLAVE:
1967 memcpy(&chip->chip.pic,
1968 &pic_irqchip(kvm)->pics[1],
1969 sizeof(struct kvm_pic_state));
1970 break;
1971 case KVM_IRQCHIP_IOAPIC:
1972 memcpy(&chip->chip.ioapic,
1973 ioapic_irqchip(kvm),
1974 sizeof(struct kvm_ioapic_state));
1975 break;
1976 default:
1977 r = -EINVAL;
1978 break;
1979 }
1980 return r;
1981}
1982
1983static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1984{
1985 int r;
1986
1987 r = 0;
1988 switch (chip->chip_id) {
1989 case KVM_IRQCHIP_PIC_MASTER:
1990 memcpy(&pic_irqchip(kvm)->pics[0],
1991 &chip->chip.pic,
1992 sizeof(struct kvm_pic_state));
1993 break;
1994 case KVM_IRQCHIP_PIC_SLAVE:
1995 memcpy(&pic_irqchip(kvm)->pics[1],
1996 &chip->chip.pic,
1997 sizeof(struct kvm_pic_state));
1998 break;
1999 case KVM_IRQCHIP_IOAPIC:
2000 memcpy(ioapic_irqchip(kvm),
2001 &chip->chip.ioapic,
2002 sizeof(struct kvm_ioapic_state));
2003 break;
2004 default:
2005 r = -EINVAL;
2006 break;
2007 }
2008 kvm_pic_update_irq(pic_irqchip(kvm));
2009 return r;
2010}
2011
e0f63cb9
SY		 2012static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2013{
2014 int r = 0;
2015
2016 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
2017 return r;
2018}
2019
2020static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2021{
2022 int r = 0;
2023
2024 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
2025 kvm_pit_load_count(kvm, 0, ps->channels[0].count);
2026 return r;
2027}
2028
52d939a0
MT		 2029static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2030 struct kvm_reinject_control *control)
2031{
2032 if (!kvm->arch.vpit)
2033 return -ENXIO;
2034 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
2035 return 0;
2036}
2037
5bb064dc
ZX		 2038/*
2039 * Get (and clear) the dirty memory log for a memory slot.
2040 */
2041int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2042 struct kvm_dirty_log *log)
2043{
2044 int r;
2045 int n;
2046 struct kvm_memory_slot *memslot;
2047 int is_dirty = 0;
2048
72dc67a6 2049 down_write(&kvm->slots_lock);
5bb064dc
ZX		 2050
2051 r = kvm_get_dirty_log(kvm, log, &is_dirty);
2052 if (r)
2053 goto out;
2054
2055 /* If nothing is dirty, don't bother messing with page tables. */
2056 if (is_dirty) {
7c8a83b7 2057 spin_lock(&kvm->mmu_lock);
5bb064dc 2058 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2059 spin_unlock(&kvm->mmu_lock);
5bb064dc
ZX		 2060 kvm_flush_remote_tlbs(kvm);
2061 memslot = &kvm->memslots[log->slot];
2062 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
2063 memset(memslot->dirty_bitmap, 0, n);
2064 }
2065 r = 0;
2066out:
72dc67a6 2067 up_write(&kvm->slots_lock);
5bb064dc
ZX		 2068 return r;
2069}
2070
1fe779f8
CO		 2071long kvm_arch_vm_ioctl(struct file *filp,
2072 unsigned int ioctl, unsigned long arg)
2073{
2074 struct kvm *kvm = filp->private_data;
2075 void __user *argp = (void __user *)arg;
2076 int r = -EINVAL;
f0d66275
DH		 2077 /*
2078 * This union makes it completely explicit to gcc-3.x
2079 * that these two variables' stack usage should be
2080 * combined, not added together.
2081 */
2082 union {
2083 struct kvm_pit_state ps;
2084 struct kvm_memory_alias alias;
c5ff41ce 2085 struct kvm_pit_config pit_config;
f0d66275 2086 } u;
1fe779f8
CO		 2087
2088 switch (ioctl) {
2089 case KVM_SET_TSS_ADDR:
2090 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2091 if (r < 0)
2092 goto out;
2093 break;
2094 case KVM_SET_MEMORY_REGION: {
2095 struct kvm_memory_region kvm_mem;
2096 struct kvm_userspace_memory_region kvm_userspace_mem;
2097
2098 r = -EFAULT;
2099 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2100 goto out;
2101 kvm_userspace_mem.slot = kvm_mem.slot;
2102 kvm_userspace_mem.flags = kvm_mem.flags;
2103 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2104 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2105 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2106 if (r)
2107 goto out;
2108 break;
2109 }
2110 case KVM_SET_NR_MMU_PAGES:
2111 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2112 if (r)
2113 goto out;
2114 break;
2115 case KVM_GET_NR_MMU_PAGES:
2116 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2117 break;
f0d66275 2118 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2119 r = -EFAULT;
f0d66275 2120 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2121 goto out;
f0d66275 2122 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2123 if (r)
2124 goto out;
2125 break;
1fe779f8
CO		 2126 case KVM_CREATE_IRQCHIP:
2127 r = -ENOMEM;
d7deeeb0
ZX		 2128 kvm->arch.vpic = kvm_create_pic(kvm);
2129 if (kvm->arch.vpic) {
1fe779f8
CO		 2130 r = kvm_ioapic_init(kvm);
2131 if (r) {
d7deeeb0
ZX		 2132 kfree(kvm->arch.vpic);
2133 kvm->arch.vpic = NULL;
1fe779f8
CO		 2134 goto out;
2135 }
2136 } else
2137 goto out;
399ec807
AK		 2138 r = kvm_setup_default_irq_routing(kvm);
2139 if (r) {
2140 kfree(kvm->arch.vpic);
2141 kfree(kvm->arch.vioapic);
2142 goto out;
2143 }
1fe779f8 2144 break;
7837699f 2145 case KVM_CREATE_PIT:
c5ff41ce
JK		 2146 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2147 goto create_pit;
2148 case KVM_CREATE_PIT2:
2149 r = -EFAULT;
2150 if (copy_from_user(&u.pit_config, argp,
2151 sizeof(struct kvm_pit_config)))
2152 goto out;
2153 create_pit:
269e05e4
AK		 2154 mutex_lock(&kvm->lock);
2155 r = -EEXIST;
2156 if (kvm->arch.vpit)
2157 goto create_pit_unlock;
7837699f 2158 r = -ENOMEM;
c5ff41ce 2159 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2160 if (kvm->arch.vpit)
2161 r = 0;
269e05e4
AK		 2162 create_pit_unlock:
2163 mutex_unlock(&kvm->lock);
7837699f 2164 break;
4925663a 2165 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2166 case KVM_IRQ_LINE: {
2167 struct kvm_irq_level irq_event;
2168
2169 r = -EFAULT;
2170 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2171 goto out;
2172 if (irqchip_in_kernel(kvm)) {
4925663a 2173 __s32 status;
fa40a821 2174 mutex_lock(&kvm->irq_lock);
4925663a
GN		 2175 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2176 irq_event.irq, irq_event.level);
fa40a821 2177 mutex_unlock(&kvm->irq_lock);
4925663a
GN		 2178 if (ioctl == KVM_IRQ_LINE_STATUS) {
2179 irq_event.status = status;
2180 if (copy_to_user(argp, &irq_event,
2181 sizeof irq_event))
2182 goto out;
2183 }
1fe779f8
CO		 2184 r = 0;
2185 }
2186 break;
2187 }
2188 case KVM_GET_IRQCHIP: {
2189 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2190 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2191
f0d66275
DH		 2192 r = -ENOMEM;
2193 if (!chip)
1fe779f8 2194 goto out;
f0d66275
DH		 2195 r = -EFAULT;
2196 if (copy_from_user(chip, argp, sizeof *chip))
2197 goto get_irqchip_out;
1fe779f8
CO		 2198 r = -ENXIO;
2199 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2200 goto get_irqchip_out;
2201 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2202 if (r)
f0d66275 2203 goto get_irqchip_out;
1fe779f8 2204 r = -EFAULT;
f0d66275
DH		 2205 if (copy_to_user(argp, chip, sizeof *chip))
2206 goto get_irqchip_out;
1fe779f8 2207 r = 0;
f0d66275
DH		 2208 get_irqchip_out:
2209 kfree(chip);
2210 if (r)
2211 goto out;
1fe779f8
CO		 2212 break;
2213 }
2214 case KVM_SET_IRQCHIP: {
2215 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2216 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2217
f0d66275
DH		 2218 r = -ENOMEM;
2219 if (!chip)
1fe779f8 2220 goto out;
f0d66275
DH		 2221 r = -EFAULT;
2222 if (copy_from_user(chip, argp, sizeof *chip))
2223 goto set_irqchip_out;
1fe779f8
CO		 2224 r = -ENXIO;
2225 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2226 goto set_irqchip_out;
2227 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2228 if (r)
f0d66275 2229 goto set_irqchip_out;
1fe779f8 2230 r = 0;
f0d66275
DH		 2231 set_irqchip_out:
2232 kfree(chip);
2233 if (r)
2234 goto out;
1fe779f8
CO		 2235 break;
2236 }
e0f63cb9 2237 case KVM_GET_PIT: {
e0f63cb9 2238 r = -EFAULT;
f0d66275 2239 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2240 goto out;
2241 r = -ENXIO;
2242 if (!kvm->arch.vpit)
2243 goto out;
f0d66275 2244 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2245 if (r)
2246 goto out;
2247 r = -EFAULT;
f0d66275 2248 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2249 goto out;
2250 r = 0;
2251 break;
2252 }
2253 case KVM_SET_PIT: {
e0f63cb9 2254 r = -EFAULT;
f0d66275 2255 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 2256 goto out;
2257 r = -ENXIO;
2258 if (!kvm->arch.vpit)
2259 goto out;
f0d66275 2260 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 2261 if (r)
2262 goto out;
2263 r = 0;
2264 break;
2265 }
52d939a0
MT		 2266 case KVM_REINJECT_CONTROL: {
2267 struct kvm_reinject_control control;
2268 r = -EFAULT;
2269 if (copy_from_user(&control, argp, sizeof(control)))
2270 goto out;
2271 r = kvm_vm_ioctl_reinject(kvm, &control);
2272 if (r)
2273 goto out;
2274 r = 0;
2275 break;
2276 }
1fe779f8
CO		 2277 default:
2278 ;
2279 }
2280out:
2281 return r;
2282}
2283
a16b043c 2284static void kvm_init_msr_list(void)
043405e1
CO		 2285{
2286 u32 dummy[2];
2287 unsigned i, j;
2288
2289 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
2290 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2291 continue;
2292 if (j < i)
2293 msrs_to_save[j] = msrs_to_save[i];
2294 j++;
2295 }
2296 num_msrs_to_save = j;
2297}
2298
bbd9b64e
CO		 2299/*
2300 * Only apic need an MMIO device hook, so shortcut now..
2301 */
2302static struct kvm_io_device *vcpu_find_pervcpu_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2303 gpa_t addr, int len,
2304 int is_write)
bbd9b64e
CO		 2305{
2306 struct kvm_io_device *dev;
2307
ad312c7c
ZX		 2308 if (vcpu->arch.apic) {
2309 dev = &vcpu->arch.apic->dev;
d76685c4 2310 if (kvm_iodevice_in_range(dev, addr, len, is_write))
bbd9b64e
CO		 2311 return dev;
2312 }
2313 return NULL;
2314}
2315
2316
2317static struct kvm_io_device *vcpu_find_mmio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2318 gpa_t addr, int len,
2319 int is_write)
bbd9b64e
CO		 2320{
2321 struct kvm_io_device *dev;
2322
92760499 2323 dev = vcpu_find_pervcpu_dev(vcpu, addr, len, is_write);
bbd9b64e 2324 if (dev == NULL)
92760499
LV		 2325 dev = kvm_io_bus_find_dev(&vcpu->kvm->mmio_bus, addr, len,
2326 is_write);
bbd9b64e
CO		 2327 return dev;
2328}
2329
cded19f3
HE		 2330static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
2331 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 2332{
2333 void *data = val;
10589a46 2334 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 2335
2336 while (bytes) {
ad312c7c 2337 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e 2338 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 2339 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 2340 int ret;
2341
10589a46
MT		 2342 if (gpa == UNMAPPED_GVA) {
2343 r = X86EMUL_PROPAGATE_FAULT;
2344 goto out;
2345 }
77c2002e 2346 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 2347 if (ret < 0) {
2348 r = X86EMUL_UNHANDLEABLE;
2349 goto out;
2350 }
bbd9b64e 2351
77c2002e
IE		 2352 bytes -= toread;
2353 data += toread;
2354 addr += toread;
bbd9b64e 2355 }
10589a46 2356out:
10589a46 2357 return r;
bbd9b64e 2358}
77c2002e 2359
cded19f3
HE		 2360static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2361 struct kvm_vcpu *vcpu)
77c2002e
IE		 2362{
2363 void *data = val;
2364 int r = X86EMUL_CONTINUE;
2365
2366 while (bytes) {
2367 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2368 unsigned offset = addr & (PAGE_SIZE-1);
2369 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2370 int ret;
2371
2372 if (gpa == UNMAPPED_GVA) {
2373 r = X86EMUL_PROPAGATE_FAULT;
2374 goto out;
2375 }
2376 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2377 if (ret < 0) {
2378 r = X86EMUL_UNHANDLEABLE;
2379 goto out;
2380 }
2381
2382 bytes -= towrite;
2383 data += towrite;
2384 addr += towrite;
2385 }
2386out:
2387 return r;
2388}
2389
bbd9b64e 2390
bbd9b64e
CO		 2391static int emulator_read_emulated(unsigned long addr,
2392 void *val,
2393 unsigned int bytes,
2394 struct kvm_vcpu *vcpu)
2395{
2396 struct kvm_io_device *mmio_dev;
2397 gpa_t gpa;
2398
2399 if (vcpu->mmio_read_completed) {
2400 memcpy(val, vcpu->mmio_data, bytes);
2401 vcpu->mmio_read_completed = 0;
2402 return X86EMUL_CONTINUE;
2403 }
2404
ad312c7c 2405 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2406
2407 /* For APIC access vmexit */
2408 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2409 goto mmio;
2410
77c2002e
IE		 2411 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2412 == X86EMUL_CONTINUE)
bbd9b64e
CO		 2413 return X86EMUL_CONTINUE;
2414 if (gpa == UNMAPPED_GVA)
2415 return X86EMUL_PROPAGATE_FAULT;
2416
2417mmio:
2418 /*
2419 * Is this MMIO handled locally?
2420 */
10589a46 2421 mutex_lock(&vcpu->kvm->lock);
92760499 2422 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 0);
fa40a821 2423 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2424 if (mmio_dev) {
2425 kvm_iodevice_read(mmio_dev, gpa, bytes, val);
2426 return X86EMUL_CONTINUE;
2427 }
2428
2429 vcpu->mmio_needed = 1;
2430 vcpu->mmio_phys_addr = gpa;
2431 vcpu->mmio_size = bytes;
2432 vcpu->mmio_is_write = 0;
2433
2434 return X86EMUL_UNHANDLEABLE;
2435}
2436
3200f405 2437int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 2438 const void *val, int bytes)
bbd9b64e
CO		 2439{
2440 int ret;
2441
2442 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 2443 if (ret < 0)
bbd9b64e 2444 return 0;
ad218f85 2445 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 2446 return 1;
2447}
2448
2449static int emulator_write_emulated_onepage(unsigned long addr,
2450 const void *val,
2451 unsigned int bytes,
2452 struct kvm_vcpu *vcpu)
2453{
2454 struct kvm_io_device *mmio_dev;
10589a46
MT		 2455 gpa_t gpa;
2456
10589a46 2457 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2458
2459 if (gpa == UNMAPPED_GVA) {
c3c91fee 2460 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 2461 return X86EMUL_PROPAGATE_FAULT;
2462 }
2463
2464 /* For APIC access vmexit */
2465 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2466 goto mmio;
2467
2468 if (emulator_write_phys(vcpu, gpa, val, bytes))
2469 return X86EMUL_CONTINUE;
2470
2471mmio:
2472 /*
2473 * Is this MMIO handled locally?
2474 */
10589a46 2475 mutex_lock(&vcpu->kvm->lock);
92760499 2476 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 1);
fa40a821 2477 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2478 if (mmio_dev) {
2479 kvm_iodevice_write(mmio_dev, gpa, bytes, val);
2480 return X86EMUL_CONTINUE;
2481 }
2482
2483 vcpu->mmio_needed = 1;
2484 vcpu->mmio_phys_addr = gpa;
2485 vcpu->mmio_size = bytes;
2486 vcpu->mmio_is_write = 1;
2487 memcpy(vcpu->mmio_data, val, bytes);
2488
2489 return X86EMUL_CONTINUE;
2490}
2491
2492int emulator_write_emulated(unsigned long addr,
2493 const void *val,
2494 unsigned int bytes,
2495 struct kvm_vcpu *vcpu)
2496{
2497 /* Crossing a page boundary? */
2498 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2499 int rc, now;
2500
2501 now = -addr & ~PAGE_MASK;
2502 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2503 if (rc != X86EMUL_CONTINUE)
2504 return rc;
2505 addr += now;
2506 val += now;
2507 bytes -= now;
2508 }
2509 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2510}
2511EXPORT_SYMBOL_GPL(emulator_write_emulated);
2512
2513static int emulator_cmpxchg_emulated(unsigned long addr,
2514 const void *old,
2515 const void *new,
2516 unsigned int bytes,
2517 struct kvm_vcpu *vcpu)
2518{
2519 static int reported;
2520
2521 if (!reported) {
2522 reported = 1;
2523 printk(KERN_WARNING "kvm: emulating exchange as write\n");
2524 }
2bacc55c
MT		 2525#ifndef CONFIG_X86_64
2526 /* guests cmpxchg8b have to be emulated atomically */
2527 if (bytes == 8) {
10589a46 2528 gpa_t gpa;
2bacc55c 2529 struct page *page;
c0b49b0d 2530 char *kaddr;
2bacc55c
MT		 2531 u64 val;
2532
10589a46
MT		 2533 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2534
2bacc55c
MT		 2535 if (gpa == UNMAPPED_GVA ||
2536 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2537 goto emul_write;
2538
2539 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2540 goto emul_write;
2541
2542 val = *(u64 *)new;
72dc67a6 2543
2bacc55c 2544 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 2545
c0b49b0d
AM		 2546 kaddr = kmap_atomic(page, KM_USER0);
2547 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2548 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 2549 kvm_release_page_dirty(page);
2550 }
3200f405 2551emul_write:
2bacc55c
MT		 2552#endif
2553
bbd9b64e
CO		 2554 return emulator_write_emulated(addr, new, bytes, vcpu);
2555}
2556
2557static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2558{
2559 return kvm_x86_ops->get_segment_base(vcpu, seg);
2560}
2561
2562int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2563{
a7052897 2564 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 2565 return X86EMUL_CONTINUE;
2566}
2567
2568int emulate_clts(struct kvm_vcpu *vcpu)
2569{
ad312c7c 2570 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 2571 return X86EMUL_CONTINUE;
2572}
2573
2574int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2575{
2576 struct kvm_vcpu *vcpu = ctxt->vcpu;
2577
2578 switch (dr) {
2579 case 0 ... 3:
2580 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2581 return X86EMUL_CONTINUE;
2582 default:
b8688d51 2583 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2584 return X86EMUL_UNHANDLEABLE;
2585 }
2586}
2587
2588int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2589{
2590 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2591 int exception;
2592
2593 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2594 if (exception) {
2595 /* FIXME: better handling */
2596 return X86EMUL_UNHANDLEABLE;
2597 }
2598 return X86EMUL_CONTINUE;
2599}
2600
2601void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2602{
bbd9b64e 2603 u8 opcodes[4];
5fdbf976 2604 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 2605 unsigned long rip_linear;
2606
f76c710d 2607 if (!printk_ratelimit())
bbd9b64e
CO		 2608 return;
2609
25be4608
GC		 2610 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2611
77c2002e 2612 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
bbd9b64e
CO		 2613
2614 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2615 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 2616}
2617EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2618
14af3f3c 2619static struct x86_emulate_ops emulate_ops = {
77c2002e 2620 .read_std = kvm_read_guest_virt,
bbd9b64e
CO		 2621 .read_emulated = emulator_read_emulated,
2622 .write_emulated = emulator_write_emulated,
2623 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2624};
2625
5fdbf976
MT		 2626static void cache_all_regs(struct kvm_vcpu *vcpu)
2627{
2628 kvm_register_read(vcpu, VCPU_REGS_RAX);
2629 kvm_register_read(vcpu, VCPU_REGS_RSP);
2630 kvm_register_read(vcpu, VCPU_REGS_RIP);
2631 vcpu->arch.regs_dirty = ~0;
2632}
2633
bbd9b64e
CO		 2634int emulate_instruction(struct kvm_vcpu *vcpu,
2635 struct kvm_run *run,
2636 unsigned long cr2,
2637 u16 error_code,
571008da 2638 int emulation_type)
bbd9b64e 2639{
310b5d30 2640 int r, shadow_mask;
571008da 2641 struct decode_cache *c;
bbd9b64e 2642
26eef70c 2643 kvm_clear_exception_queue(vcpu);
ad312c7c 2644 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976
MT		 2645 /*
2646 * TODO: fix x86_emulate.c to use guest_read/write_register
2647 * instead of direct ->regs accesses, can save hundred cycles
2648 * on Intel for instructions that don't read/change RSP, for
2649 * for example.
2650 */
2651 cache_all_regs(vcpu);
bbd9b64e
CO		 2652
2653 vcpu->mmio_is_write = 0;
ad312c7c 2654 vcpu->arch.pio.string = 0;
bbd9b64e 2655
571008da 2656 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2657 int cs_db, cs_l;
2658 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2659
ad312c7c
ZX		 2660 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2661 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2662 vcpu->arch.emulate_ctxt.mode =
2663 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2664 ? X86EMUL_MODE_REAL : cs_l
2665 ? X86EMUL_MODE_PROT64 : cs_db
2666 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2667
ad312c7c 2668 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da 2669
0cb5762e
AP		 2670 /* Only allow emulation of specific instructions on #UD
2671 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 2672 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 2673 if (emulation_type & EMULTYPE_TRAP_UD) {
2674 if (!c->twobyte)
2675 return EMULATE_FAIL;
2676 switch (c->b) {
2677 case 0x01: /* VMMCALL */
2678 if (c->modrm_mod != 3 || c->modrm_rm != 1)
2679 return EMULATE_FAIL;
2680 break;
2681 case 0x34: /* sysenter */
2682 case 0x35: /* sysexit */
2683 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2684 return EMULATE_FAIL;
2685 break;
2686 case 0x05: /* syscall */
2687 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2688 return EMULATE_FAIL;
2689 break;
2690 default:
2691 return EMULATE_FAIL;
2692 }
2693
2694 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
2695 return EMULATE_FAIL;
2696 }
571008da 2697
f2b5756b 2698 ++vcpu->stat.insn_emulation;
bbd9b64e 2699 if (r) {
f2b5756b 2700 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2701 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2702 return EMULATE_DONE;
2703 return EMULATE_FAIL;
2704 }
2705 }
2706
ba8afb6b
GN		 2707 if (emulation_type & EMULTYPE_SKIP) {
2708 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
2709 return EMULATE_DONE;
2710 }
2711
ad312c7c 2712 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 2713 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
2714
2715 if (r == 0)
2716 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 2717
ad312c7c 2718 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2719 return EMULATE_DO_MMIO;
2720
2721 if ((r || vcpu->mmio_is_write) && run) {
2722 run->exit_reason = KVM_EXIT_MMIO;
2723 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2724 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2725 run->mmio.len = vcpu->mmio_size;
2726 run->mmio.is_write = vcpu->mmio_is_write;
2727 }
2728
2729 if (r) {
2730 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2731 return EMULATE_DONE;
2732 if (!vcpu->mmio_needed) {
2733 kvm_report_emulation_failure(vcpu, "mmio");
2734 return EMULATE_FAIL;
2735 }
2736 return EMULATE_DO_MMIO;
2737 }
2738
ad312c7c 2739 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2740
2741 if (vcpu->mmio_is_write) {
2742 vcpu->mmio_needed = 0;
2743 return EMULATE_DO_MMIO;
2744 }
2745
2746 return EMULATE_DONE;
2747}
2748EXPORT_SYMBOL_GPL(emulate_instruction);
2749
de7d789a
CO		 2750static int pio_copy_data(struct kvm_vcpu *vcpu)
2751{
ad312c7c 2752 void *p = vcpu->arch.pio_data;
0f346074 2753 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 2754 unsigned bytes;
0f346074 2755 int ret;
de7d789a 2756
ad312c7c
ZX		 2757 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2758 if (vcpu->arch.pio.in)
0f346074 2759 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
de7d789a 2760 else
0f346074
IE		 2761 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
2762 return ret;
de7d789a
CO		 2763}
2764
2765int complete_pio(struct kvm_vcpu *vcpu)
2766{
ad312c7c 2767 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2768 long delta;
2769 int r;
5fdbf976 2770 unsigned long val;
de7d789a
CO		 2771
2772 if (!io->string) {
5fdbf976
MT		 2773 if (io->in) {
2774 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2775 memcpy(&val, vcpu->arch.pio_data, io->size);
2776 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2777 }
de7d789a
CO		 2778 } else {
2779 if (io->in) {
2780 r = pio_copy_data(vcpu);
5fdbf976 2781 if (r)
de7d789a 2782 return r;
de7d789a
CO		 2783 }
2784
2785 delta = 1;
2786 if (io->rep) {
2787 delta *= io->cur_count;
2788 /*
2789 * The size of the register should really depend on
2790 * current address size.
2791 */
5fdbf976
MT		 2792 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2793 val -= delta;
2794 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 2795 }
2796 if (io->down)
2797 delta = -delta;
2798 delta *= io->size;
5fdbf976
MT		 2799 if (io->in) {
2800 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2801 val += delta;
2802 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2803 } else {
2804 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2805 val += delta;
2806 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2807 }
de7d789a
CO		 2808 }
2809
de7d789a
CO		 2810 io->count -= io->cur_count;
2811 io->cur_count = 0;
2812
2813 return 0;
2814}
2815
2816static void kernel_pio(struct kvm_io_device *pio_dev,
2817 struct kvm_vcpu *vcpu,
2818 void *pd)
2819{
2820 /* TODO: String I/O for in kernel device */
2821
ad312c7c
ZX		 2822 if (vcpu->arch.pio.in)
2823 kvm_iodevice_read(pio_dev, vcpu->arch.pio.port,
2824 vcpu->arch.pio.size,
de7d789a
CO		 2825 pd);
2826 else
ad312c7c
ZX		 2827 kvm_iodevice_write(pio_dev, vcpu->arch.pio.port,
2828 vcpu->arch.pio.size,
de7d789a 2829 pd);
de7d789a
CO		 2830}
2831
2832static void pio_string_write(struct kvm_io_device *pio_dev,
2833 struct kvm_vcpu *vcpu)
2834{
ad312c7c
ZX		 2835 struct kvm_pio_request *io = &vcpu->arch.pio;
2836 void *pd = vcpu->arch.pio_data;
de7d789a
CO		 2837 int i;
2838
de7d789a
CO		 2839 for (i = 0; i < io->cur_count; i++) {
2840 kvm_iodevice_write(pio_dev, io->port,
2841 io->size,
2842 pd);
2843 pd += io->size;
2844 }
de7d789a
CO		 2845}
2846
2847static struct kvm_io_device *vcpu_find_pio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2848 gpa_t addr, int len,
2849 int is_write)
de7d789a 2850{
92760499 2851 return kvm_io_bus_find_dev(&vcpu->kvm->pio_bus, addr, len, is_write);
de7d789a
CO		 2852}
2853
2854int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2855 int size, unsigned port)
2856{
2857 struct kvm_io_device *pio_dev;
5fdbf976 2858 unsigned long val;
de7d789a
CO		 2859
2860 vcpu->run->exit_reason = KVM_EXIT_IO;
2861 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2862 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2863 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2864 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2865 vcpu->run->io.port = vcpu->arch.pio.port = port;
2866 vcpu->arch.pio.in = in;
2867 vcpu->arch.pio.string = 0;
2868 vcpu->arch.pio.down = 0;
ad312c7c 2869 vcpu->arch.pio.rep = 0;
de7d789a 2870
229456fc
MT		 2871 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
2872 size, 1);
2714d1d3 2873
5fdbf976
MT		 2874 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2875 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a 2876
fa40a821 2877 mutex_lock(&vcpu->kvm->lock);
92760499 2878 pio_dev = vcpu_find_pio_dev(vcpu, port, size, !in);
fa40a821 2879 mutex_unlock(&vcpu->kvm->lock);
de7d789a 2880 if (pio_dev) {
ad312c7c 2881 kernel_pio(pio_dev, vcpu, vcpu->arch.pio_data);
de7d789a
CO		 2882 complete_pio(vcpu);
2883 return 1;
2884 }
2885 return 0;
2886}
2887EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2888
2889int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2890 int size, unsigned long count, int down,
2891 gva_t address, int rep, unsigned port)
2892{
2893 unsigned now, in_page;
0f346074 2894 int ret = 0;
de7d789a
CO		 2895 struct kvm_io_device *pio_dev;
2896
2897 vcpu->run->exit_reason = KVM_EXIT_IO;
2898 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2899 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2900 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2901 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2902 vcpu->run->io.port = vcpu->arch.pio.port = port;
2903 vcpu->arch.pio.in = in;
2904 vcpu->arch.pio.string = 1;
2905 vcpu->arch.pio.down = down;
ad312c7c 2906 vcpu->arch.pio.rep = rep;
de7d789a 2907
229456fc
MT		 2908 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
2909 size, count);
2714d1d3 2910
de7d789a
CO		 2911 if (!count) {
2912 kvm_x86_ops->skip_emulated_instruction(vcpu);
2913 return 1;
2914 }
2915
2916 if (!down)
2917 in_page = PAGE_SIZE - offset_in_page(address);
2918 else
2919 in_page = offset_in_page(address) + size;
2920 now = min(count, (unsigned long)in_page / size);
0f346074 2921 if (!now)
de7d789a 2922 now = 1;
de7d789a
CO		 2923 if (down) {
2924 /*
2925 * String I/O in reverse. Yuck. Kill the guest, fix later.
2926 */
2927 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 2928 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2929 return 1;
2930 }
2931 vcpu->run->io.count = now;
ad312c7c 2932 vcpu->arch.pio.cur_count = now;
de7d789a 2933
ad312c7c 2934 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 2935 kvm_x86_ops->skip_emulated_instruction(vcpu);
2936
0f346074 2937 vcpu->arch.pio.guest_gva = address;
de7d789a 2938
fa40a821 2939 mutex_lock(&vcpu->kvm->lock);
92760499
LV		 2940 pio_dev = vcpu_find_pio_dev(vcpu, port,
2941 vcpu->arch.pio.cur_count,
2942 !vcpu->arch.pio.in);
fa40a821
MT		 2943 mutex_unlock(&vcpu->kvm->lock);
2944
ad312c7c 2945 if (!vcpu->arch.pio.in) {
de7d789a
CO		 2946 /* string PIO write */
2947 ret = pio_copy_data(vcpu);
0f346074
IE		 2948 if (ret == X86EMUL_PROPAGATE_FAULT) {
2949 kvm_inject_gp(vcpu, 0);
2950 return 1;
2951 }
2952 if (ret == 0 && pio_dev) {
de7d789a
CO		 2953 pio_string_write(pio_dev, vcpu);
2954 complete_pio(vcpu);
ad312c7c 2955 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 2956 ret = 1;
2957 }
2958 } else if (pio_dev)
2959 pr_unimpl(vcpu, "no string pio read support yet, "
2960 "port %x size %d count %ld\n",
2961 port, size, count);
2962
2963 return ret;
2964}
2965EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
2966
c8076604
GH		 2967static void bounce_off(void *info)
2968{
2969 /* nothing */
2970}
2971
2972static unsigned int ref_freq;
2973static unsigned long tsc_khz_ref;
2974
2975static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
2976 void *data)
2977{
2978 struct cpufreq_freqs *freq = data;
2979 struct kvm *kvm;
2980 struct kvm_vcpu *vcpu;
2981 int i, send_ipi = 0;
2982
2983 if (!ref_freq)
2984 ref_freq = freq->old;
2985
2986 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
2987 return 0;
2988 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
2989 return 0;
2990 per_cpu(cpu_tsc_khz, freq->cpu) = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
2991
2992 spin_lock(&kvm_lock);
2993 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 2994 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 2995 if (vcpu->cpu != freq->cpu)
2996 continue;
2997 if (!kvm_request_guest_time_update(vcpu))
2998 continue;
2999 if (vcpu->cpu != smp_processor_id())
3000 send_ipi++;
3001 }
3002 }
3003 spin_unlock(&kvm_lock);
3004
3005 if (freq->old < freq->new && send_ipi) {
3006 /*
3007 * We upscale the frequency. Must make the guest
3008 * doesn't see old kvmclock values while running with
3009 * the new frequency, otherwise we risk the guest sees
3010 * time go backwards.
3011 *
3012 * In case we update the frequency for another cpu
3013 * (which might be in guest context) send an interrupt
3014 * to kick the cpu out of guest context. Next time
3015 * guest context is entered kvmclock will be updated,
3016 * so the guest will not see stale values.
3017 */
3018 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3019 }
3020 return 0;
3021}
3022
3023static struct notifier_block kvmclock_cpufreq_notifier_block = {
3024 .notifier_call = kvmclock_cpufreq_notifier
3025};
3026
f8c16bba 3027int kvm_arch_init(void *opaque)
043405e1 3028{
c8076604 3029 int r, cpu;
f8c16bba
ZX		 3030 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3031
f8c16bba
ZX		 3032 if (kvm_x86_ops) {
3033 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 3034 r = -EEXIST;
3035 goto out;
f8c16bba
ZX		 3036 }
3037
3038 if (!ops->cpu_has_kvm_support()) {
3039 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 3040 r = -EOPNOTSUPP;
3041 goto out;
f8c16bba
ZX		 3042 }
3043 if (ops->disabled_by_bios()) {
3044 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 3045 r = -EOPNOTSUPP;
3046 goto out;
f8c16bba
ZX		 3047 }
3048
97db56ce
AK		 3049 r = kvm_mmu_module_init();
3050 if (r)
3051 goto out;
3052
3053 kvm_init_msr_list();
3054
f8c16bba 3055 kvm_x86_ops = ops;
56c6d28a 3056 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 3057 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3058 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 3059 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604
GH		 3060
3061 for_each_possible_cpu(cpu)
3062 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
3063 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
3064 tsc_khz_ref = tsc_khz;
3065 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3066 CPUFREQ_TRANSITION_NOTIFIER);
3067 }
3068
f8c16bba 3069 return 0;
56c6d28a
ZX		 3070
3071out:
56c6d28a 3072 return r;
043405e1 3073}
8776e519 3074
f8c16bba
ZX		 3075void kvm_arch_exit(void)
3076{
888d256e
JK		 3077 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3078 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3079 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 3080 kvm_x86_ops = NULL;
56c6d28a
ZX		 3081 kvm_mmu_module_exit();
3082}
f8c16bba 3083
8776e519
HB		 3084int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3085{
3086 ++vcpu->stat.halt_exits;
3087 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 3088 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 3089 return 1;
3090 } else {
3091 vcpu->run->exit_reason = KVM_EXIT_HLT;
3092 return 0;
3093 }
3094}
3095EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3096
2f333bcb
MT		 3097static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3098 unsigned long a1)
3099{
3100 if (is_long_mode(vcpu))
3101 return a0;
3102 else
3103 return a0 | ((gpa_t)a1 << 32);
3104}
3105
8776e519
HB		 3106int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3107{
3108 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 3109 int r = 1;
8776e519 3110
5fdbf976
MT		 3111 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3112 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3113 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3114 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3115 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 3116
229456fc 3117 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 3118
8776e519
HB		 3119 if (!is_long_mode(vcpu)) {
3120 nr &= 0xFFFFFFFF;
3121 a0 &= 0xFFFFFFFF;
3122 a1 &= 0xFFFFFFFF;
3123 a2 &= 0xFFFFFFFF;
3124 a3 &= 0xFFFFFFFF;
3125 }
3126
3127 switch (nr) {
b93463aa
AK		 3128 case KVM_HC_VAPIC_POLL_IRQ:
3129 ret = 0;
3130 break;
2f333bcb
MT		 3131 case KVM_HC_MMU_OP:
3132 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3133 break;
8776e519
HB		 3134 default:
3135 ret = -KVM_ENOSYS;
3136 break;
3137 }
5fdbf976 3138 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 3139 ++vcpu->stat.hypercalls;
2f333bcb 3140 return r;
8776e519
HB		 3141}
3142EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3143
3144int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3145{
3146 char instruction[3];
3147 int ret = 0;
5fdbf976 3148 unsigned long rip = kvm_rip_read(vcpu);
8776e519 3149
8776e519
HB		 3150
3151 /*
3152 * Blow out the MMU to ensure that no other VCPU has an active mapping
3153 * to ensure that the updated hypercall appears atomically across all
3154 * VCPUs.
3155 */
3156 kvm_mmu_zap_all(vcpu->kvm);
3157
8776e519 3158 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 3159 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 3160 != X86EMUL_CONTINUE)
3161 ret = -EFAULT;
3162
8776e519
HB		 3163 return ret;
3164}
3165
3166static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3167{
3168 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3169}
3170
3171void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3172{
3173 struct descriptor_table dt = { limit, base };
3174
3175 kvm_x86_ops->set_gdt(vcpu, &dt);
3176}
3177
3178void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3179{
3180 struct descriptor_table dt = { limit, base };
3181
3182 kvm_x86_ops->set_idt(vcpu, &dt);
3183}
3184
3185void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
3186 unsigned long *rflags)
3187{
2d3ad1f4 3188 kvm_lmsw(vcpu, msw);
8776e519
HB		 3189 *rflags = kvm_x86_ops->get_rflags(vcpu);
3190}
3191
3192unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3193{
54e445ca
JR		 3194 unsigned long value;
3195
8776e519
HB		 3196 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3197 switch (cr) {
3198 case 0:
54e445ca
JR		 3199 value = vcpu->arch.cr0;
3200 break;
8776e519 3201 case 2:
54e445ca
JR		 3202 value = vcpu->arch.cr2;
3203 break;
8776e519 3204 case 3:
54e445ca
JR		 3205 value = vcpu->arch.cr3;
3206 break;
8776e519 3207 case 4:
54e445ca
JR		 3208 value = vcpu->arch.cr4;
3209 break;
152ff9be 3210 case 8:
54e445ca
JR		 3211 value = kvm_get_cr8(vcpu);
3212 break;
8776e519 3213 default:
b8688d51 3214 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3215 return 0;
3216 }
54e445ca
JR		 3217
3218 return value;
8776e519
HB		 3219}
3220
3221void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
3222 unsigned long *rflags)
3223{
3224 switch (cr) {
3225 case 0:
2d3ad1f4 3226 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 3227 *rflags = kvm_x86_ops->get_rflags(vcpu);
3228 break;
3229 case 2:
ad312c7c 3230 vcpu->arch.cr2 = val;
8776e519
HB		 3231 break;
3232 case 3:
2d3ad1f4 3233 kvm_set_cr3(vcpu, val);
8776e519
HB		 3234 break;
3235 case 4:
2d3ad1f4 3236 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 3237 break;
152ff9be 3238 case 8:
2d3ad1f4 3239 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 3240 break;
8776e519 3241 default:
b8688d51 3242 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3243 }
3244}
3245
07716717
DK		 3246static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
3247{
ad312c7c
ZX		 3248 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
3249 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 3250
3251 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
3252 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 3253 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 3254 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 3255 if (ej->function == e->function) {
3256 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
3257 return j;
3258 }
3259 }
3260 return 0; /* silence gcc, even though control never reaches here */
3261}
3262
3263/* find an entry with matching function, matching index (if needed), and that
3264 * should be read next (if it's stateful) */
3265static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
3266 u32 function, u32 index)
3267{
3268 if (e->function != function)
3269 return 0;
3270 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
3271 return 0;
3272 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 3273 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 3274 return 0;
3275 return 1;
3276}
3277
d8017474
AG		 3278struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
3279 u32 function, u32 index)
8776e519
HB		 3280{
3281 int i;
d8017474 3282 struct kvm_cpuid_entry2 *best = NULL;
8776e519 3283
ad312c7c 3284 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 3285 struct kvm_cpuid_entry2 *e;
3286
ad312c7c 3287 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 3288 if (is_matching_cpuid_entry(e, function, index)) {
3289 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
3290 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 3291 best = e;
3292 break;
3293 }
3294 /*
3295 * Both basic or both extended?
3296 */
3297 if (((e->function ^ function) & 0x80000000) == 0)
3298 if (!best || e->function > best->function)
3299 best = e;
3300 }
d8017474
AG		 3301 return best;
3302}
3303
82725b20
DE		 3304int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
3305{
3306 struct kvm_cpuid_entry2 *best;
3307
3308 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
3309 if (best)
3310 return best->eax & 0xff;
3311 return 36;
3312}
3313
d8017474
AG		 3314void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
3315{
3316 u32 function, index;
3317 struct kvm_cpuid_entry2 *best;
3318
3319 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
3320 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3321 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
3322 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
3323 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
3324 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
3325 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 3326 if (best) {
5fdbf976
MT		 3327 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
3328 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
3329 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
3330 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 3331 }
8776e519 3332 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 3333 trace_kvm_cpuid(function,
3334 kvm_register_read(vcpu, VCPU_REGS_RAX),
3335 kvm_register_read(vcpu, VCPU_REGS_RBX),
3336 kvm_register_read(vcpu, VCPU_REGS_RCX),
3337 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 3338}
3339EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 3340
b6c7a5dc
HB		 3341/*
3342 * Check if userspace requested an interrupt window, and that the
3343 * interrupt window is open.
3344 *
3345 * No need to exit to userspace if we already have an interrupt queued.
3346 */
3347static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
3348 struct kvm_run *kvm_run)
3349{
8061823a 3350 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
b6c7a5dc 3351 kvm_run->request_interrupt_window &&
5df56646 3352 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 3353}
3354
3355static void post_kvm_run_save(struct kvm_vcpu *vcpu,
3356 struct kvm_run *kvm_run)
3357{
3358 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 3359 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 3360 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 3361 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3362 kvm_run->ready_for_interrupt_injection = 1;
4531220b 3363 else
b6c7a5dc 3364 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 3365 kvm_arch_interrupt_allowed(vcpu) &&
3366 !kvm_cpu_has_interrupt(vcpu) &&
3367 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 3368}
3369
b93463aa
AK		 3370static void vapic_enter(struct kvm_vcpu *vcpu)
3371{
3372 struct kvm_lapic *apic = vcpu->arch.apic;
3373 struct page *page;
3374
3375 if (!apic || !apic->vapic_addr)
3376 return;
3377
3378 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 3379
3380 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 3381}
3382
3383static void vapic_exit(struct kvm_vcpu *vcpu)
3384{
3385 struct kvm_lapic *apic = vcpu->arch.apic;
3386
3387 if (!apic || !apic->vapic_addr)
3388 return;
3389
f8b78fa3 3390 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3391 kvm_release_page_dirty(apic->vapic_page);
3392 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 3393 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3394}
3395
95ba8273
GN		 3396static void update_cr8_intercept(struct kvm_vcpu *vcpu)
3397{
3398 int max_irr, tpr;
3399
3400 if (!kvm_x86_ops->update_cr8_intercept)
3401 return;
3402
8db3baa2
GN		 3403 if (!vcpu->arch.apic->vapic_addr)
3404 max_irr = kvm_lapic_find_highest_irr(vcpu);
3405 else
3406 max_irr = -1;
95ba8273
GN		 3407
3408 if (max_irr != -1)
3409 max_irr >>= 4;
3410
3411 tpr = kvm_lapic_get_cr8(vcpu);
3412
3413 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
3414}
3415
6a8b1d13 3416static void inject_pending_irq(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
95ba8273
GN		 3417{
3418 /* try to reinject previous events if any */
3419 if (vcpu->arch.nmi_injected) {
3420 kvm_x86_ops->set_nmi(vcpu);
3421 return;
3422 }
3423
3424 if (vcpu->arch.interrupt.pending) {
66fd3f7f 3425 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3426 return;
3427 }
3428
3429 /* try to inject new event if pending */
3430 if (vcpu->arch.nmi_pending) {
3431 if (kvm_x86_ops->nmi_allowed(vcpu)) {
3432 vcpu->arch.nmi_pending = false;
3433 vcpu->arch.nmi_injected = true;
3434 kvm_x86_ops->set_nmi(vcpu);
3435 }
3436 } else if (kvm_cpu_has_interrupt(vcpu)) {
3437 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 3438 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
3439 false);
3440 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3441 }
3442 }
3443}
3444
d7690175 3445static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
b6c7a5dc
HB		 3446{
3447 int r;
6a8b1d13
GN		 3448 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
3449 kvm_run->request_interrupt_window;
b6c7a5dc 3450
2e53d63a
MT		 3451 if (vcpu->requests)
3452 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
3453 kvm_mmu_unload(vcpu);
3454
b6c7a5dc
HB		 3455 r = kvm_mmu_reload(vcpu);
3456 if (unlikely(r))
3457 goto out;
3458
2f52d58c
AK		 3459 if (vcpu->requests) {
3460 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 3461 __kvm_migrate_timers(vcpu);
c8076604
GH		 3462 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
3463 kvm_write_guest_time(vcpu);
4731d4c7
MT		 3464 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
3465 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 3466 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
3467 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 3468 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
3469 &vcpu->requests)) {
3470 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
3471 r = 0;
3472 goto out;
3473 }
71c4dfaf
JR		 3474 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
3475 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
3476 r = 0;
3477 goto out;
3478 }
2f52d58c 3479 }
b93463aa 3480
b6c7a5dc
HB		 3481 preempt_disable();
3482
3483 kvm_x86_ops->prepare_guest_switch(vcpu);
3484 kvm_load_guest_fpu(vcpu);
3485
3486 local_irq_disable();
3487
32f88400
MT		 3488 clear_bit(KVM_REQ_KICK, &vcpu->requests);
3489 smp_mb__after_clear_bit();
3490
d7690175 3491 if (vcpu->requests || need_resched() || signal_pending(current)) {
6c142801
AK		 3492 local_irq_enable();
3493 preempt_enable();
3494 r = 1;
3495 goto out;
3496 }
3497
ad312c7c 3498 if (vcpu->arch.exception.pending)
298101da 3499 __queue_exception(vcpu);
eb9774f0 3500 else
95ba8273 3501 inject_pending_irq(vcpu, kvm_run);
b6c7a5dc 3502
6a8b1d13
GN		 3503 /* enable NMI/IRQ window open exits if needed */
3504 if (vcpu->arch.nmi_pending)
3505 kvm_x86_ops->enable_nmi_window(vcpu);
3506 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
3507 kvm_x86_ops->enable_irq_window(vcpu);
3508
95ba8273 3509 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 3510 update_cr8_intercept(vcpu);
3511 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 3512 }
b93463aa 3513
3200f405
MT		 3514 up_read(&vcpu->kvm->slots_lock);
3515
b6c7a5dc
HB		 3516 kvm_guest_enter();
3517
42dbaa5a
JK		 3518 get_debugreg(vcpu->arch.host_dr6, 6);
3519 get_debugreg(vcpu->arch.host_dr7, 7);
3520 if (unlikely(vcpu->arch.switch_db_regs)) {
3521 get_debugreg(vcpu->arch.host_db[0], 0);
3522 get_debugreg(vcpu->arch.host_db[1], 1);
3523 get_debugreg(vcpu->arch.host_db[2], 2);
3524 get_debugreg(vcpu->arch.host_db[3], 3);
3525
3526 set_debugreg(0, 7);
3527 set_debugreg(vcpu->arch.eff_db[0], 0);
3528 set_debugreg(vcpu->arch.eff_db[1], 1);
3529 set_debugreg(vcpu->arch.eff_db[2], 2);
3530 set_debugreg(vcpu->arch.eff_db[3], 3);
3531 }
b6c7a5dc 3532
229456fc 3533 trace_kvm_entry(vcpu->vcpu_id);
b6c7a5dc
HB		 3534 kvm_x86_ops->run(vcpu, kvm_run);
3535
42dbaa5a
JK		 3536 if (unlikely(vcpu->arch.switch_db_regs)) {
3537 set_debugreg(0, 7);
3538 set_debugreg(vcpu->arch.host_db[0], 0);
3539 set_debugreg(vcpu->arch.host_db[1], 1);
3540 set_debugreg(vcpu->arch.host_db[2], 2);
3541 set_debugreg(vcpu->arch.host_db[3], 3);
3542 }
3543 set_debugreg(vcpu->arch.host_dr6, 6);
3544 set_debugreg(vcpu->arch.host_dr7, 7);
3545
32f88400 3546 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 3547 local_irq_enable();
3548
3549 ++vcpu->stat.exits;
3550
3551 /*
3552 * We must have an instruction between local_irq_enable() and
3553 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3554 * the interrupt shadow. The stat.exits increment will do nicely.
3555 * But we need to prevent reordering, hence this barrier():
3556 */
3557 barrier();
3558
3559 kvm_guest_exit();
3560
3561 preempt_enable();
3562
3200f405
MT		 3563 down_read(&vcpu->kvm->slots_lock);
3564
b6c7a5dc
HB		 3565 /*
3566 * Profile KVM exit RIPs:
3567 */
3568 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 3569 unsigned long rip = kvm_rip_read(vcpu);
3570 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 3571 }
3572
298101da 3573
b93463aa
AK		 3574 kvm_lapic_sync_from_vapic(vcpu);
3575
b6c7a5dc 3576 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
d7690175
MT		 3577out:
3578 return r;
3579}
b6c7a5dc 3580
09cec754 3581
d7690175
MT		 3582static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3583{
3584 int r;
3585
3586 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 3587 pr_debug("vcpu %d received sipi with vector # %x\n",
3588 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 3589 kvm_lapic_reset(vcpu);
5f179287 3590 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 3591 if (r)
3592 return r;
3593 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 3594 }
3595
d7690175
MT		 3596 down_read(&vcpu->kvm->slots_lock);
3597 vapic_enter(vcpu);
3598
3599 r = 1;
3600 while (r > 0) {
af2152f5 3601 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
d7690175
MT		 3602 r = vcpu_enter_guest(vcpu, kvm_run);
3603 else {
3604 up_read(&vcpu->kvm->slots_lock);
3605 kvm_vcpu_block(vcpu);
3606 down_read(&vcpu->kvm->slots_lock);
3607 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 3608 {
3609 switch(vcpu->arch.mp_state) {
3610 case KVM_MP_STATE_HALTED:
d7690175 3611 vcpu->arch.mp_state =
09cec754
GN		 3612 KVM_MP_STATE_RUNNABLE;
3613 case KVM_MP_STATE_RUNNABLE:
3614 break;
3615 case KVM_MP_STATE_SIPI_RECEIVED:
3616 default:
3617 r = -EINTR;
3618 break;
3619 }
3620 }
d7690175
MT		 3621 }
3622
09cec754
GN		 3623 if (r <= 0)
3624 break;
3625
3626 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
3627 if (kvm_cpu_has_pending_timer(vcpu))
3628 kvm_inject_pending_timer_irqs(vcpu);
3629
3630 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
3631 r = -EINTR;
3632 kvm_run->exit_reason = KVM_EXIT_INTR;
3633 ++vcpu->stat.request_irq_exits;
3634 }
3635 if (signal_pending(current)) {
3636 r = -EINTR;
3637 kvm_run->exit_reason = KVM_EXIT_INTR;
3638 ++vcpu->stat.signal_exits;
3639 }
3640 if (need_resched()) {
3641 up_read(&vcpu->kvm->slots_lock);
3642 kvm_resched(vcpu);
3643 down_read(&vcpu->kvm->slots_lock);
d7690175 3644 }
b6c7a5dc
HB		 3645 }
3646
d7690175 3647 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3648 post_kvm_run_save(vcpu, kvm_run);
3649
b93463aa
AK		 3650 vapic_exit(vcpu);
3651
b6c7a5dc
HB		 3652 return r;
3653}
3654
3655int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3656{
3657 int r;
3658 sigset_t sigsaved;
3659
3660 vcpu_load(vcpu);
3661
ac9f6dc0
AK		 3662 if (vcpu->sigset_active)
3663 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
3664
a4535290 3665 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 3666 kvm_vcpu_block(vcpu);
d7690175 3667 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 3668 r = -EAGAIN;
3669 goto out;
b6c7a5dc
HB		 3670 }
3671
b6c7a5dc
HB		 3672 /* re-sync apic's tpr */
3673 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 3674 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 3675
ad312c7c 3676 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 3677 r = complete_pio(vcpu);
3678 if (r)
3679 goto out;
3680 }
3681#if CONFIG_HAS_IOMEM
3682 if (vcpu->mmio_needed) {
3683 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3684 vcpu->mmio_read_completed = 1;
3685 vcpu->mmio_needed = 0;
3200f405
MT		 3686
3687 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc 3688 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 3689 vcpu->arch.mmio_fault_cr2, 0,
3690 EMULTYPE_NO_DECODE);
3200f405 3691 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3692 if (r == EMULATE_DO_MMIO) {
3693 /*
3694 * Read-modify-write. Back to userspace.
3695 */
3696 r = 0;
3697 goto out;
3698 }
3699 }
3700#endif
5fdbf976
MT		 3701 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3702 kvm_register_write(vcpu, VCPU_REGS_RAX,
3703 kvm_run->hypercall.ret);
b6c7a5dc
HB		 3704
3705 r = __vcpu_run(vcpu, kvm_run);
3706
3707out:
3708 if (vcpu->sigset_active)
3709 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3710
3711 vcpu_put(vcpu);
3712 return r;
3713}
3714
3715int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3716{
3717 vcpu_load(vcpu);
3718
5fdbf976
MT		 3719 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3720 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3721 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3722 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3723 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3724 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3725 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3726 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 3727#ifdef CONFIG_X86_64
5fdbf976
MT		 3728 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3729 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3730 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3731 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3732 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3733 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3734 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3735 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 3736#endif
3737
5fdbf976 3738 regs->rip = kvm_rip_read(vcpu);
b6c7a5dc
HB		 3739 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3740
3741 /*
3742 * Don't leak debug flags in case they were set for guest debugging
3743 */
d0bfb940 3744 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
b6c7a5dc
HB		 3745 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3746
3747 vcpu_put(vcpu);
3748
3749 return 0;
3750}
3751
3752int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3753{
3754 vcpu_load(vcpu);
3755
5fdbf976
MT		 3756 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3757 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3758 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3759 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3760 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3761 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3762 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3763 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 3764#ifdef CONFIG_X86_64
5fdbf976
MT		 3765 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3766 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3767 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3768 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3769 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3770 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3771 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3772 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
3773
b6c7a5dc
HB		 3774#endif
3775
5fdbf976 3776 kvm_rip_write(vcpu, regs->rip);
b6c7a5dc
HB		 3777 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3778
b6c7a5dc 3779
b4f14abd
JK		 3780 vcpu->arch.exception.pending = false;
3781
b6c7a5dc
HB		 3782 vcpu_put(vcpu);
3783
3784 return 0;
3785}
3786
3e6e0aab
GT		 3787void kvm_get_segment(struct kvm_vcpu *vcpu,
3788 struct kvm_segment *var, int seg)
b6c7a5dc 3789{
14af3f3c 3790 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 3791}
3792
3793void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3794{
3795 struct kvm_segment cs;
3796
3e6e0aab 3797 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 3798 *db = cs.db;
3799 *l = cs.l;
3800}
3801EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3802
3803int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3804 struct kvm_sregs *sregs)
3805{
3806 struct descriptor_table dt;
b6c7a5dc
HB		 3807
3808 vcpu_load(vcpu);
3809
3e6e0aab
GT		 3810 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3811 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3812 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3813 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3814 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3815 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3816
3e6e0aab
GT		 3817 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3818 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3819
3820 kvm_x86_ops->get_idt(vcpu, &dt);
3821 sregs->idt.limit = dt.limit;
3822 sregs->idt.base = dt.base;
3823 kvm_x86_ops->get_gdt(vcpu, &dt);
3824 sregs->gdt.limit = dt.limit;
3825 sregs->gdt.base = dt.base;
3826
3827 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3828 sregs->cr0 = vcpu->arch.cr0;
3829 sregs->cr2 = vcpu->arch.cr2;
3830 sregs->cr3 = vcpu->arch.cr3;
3831 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3832 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3833 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3834 sregs->apic_base = kvm_get_apic_base(vcpu);
3835
923c61bb 3836 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 3837
36752c9b 3838 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 3839 set_bit(vcpu->arch.interrupt.nr,
3840 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 3841
b6c7a5dc
HB		 3842 vcpu_put(vcpu);
3843
3844 return 0;
3845}
3846
62d9f0db
MT		 3847int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3848 struct kvm_mp_state *mp_state)
3849{
3850 vcpu_load(vcpu);
3851 mp_state->mp_state = vcpu->arch.mp_state;
3852 vcpu_put(vcpu);
3853 return 0;
3854}
3855
3856int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3857 struct kvm_mp_state *mp_state)
3858{
3859 vcpu_load(vcpu);
3860 vcpu->arch.mp_state = mp_state->mp_state;
3861 vcpu_put(vcpu);
3862 return 0;
3863}
3864
3e6e0aab 3865static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 3866 struct kvm_segment *var, int seg)
3867{
14af3f3c 3868 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 3869}
3870
37817f29
IE		 3871static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3872 struct kvm_segment *kvm_desct)
3873{
3874 kvm_desct->base = seg_desc->base0;
3875 kvm_desct->base |= seg_desc->base1 << 16;
3876 kvm_desct->base |= seg_desc->base2 << 24;
3877 kvm_desct->limit = seg_desc->limit0;
3878 kvm_desct->limit |= seg_desc->limit << 16;
c93cd3a5
MT		 3879 if (seg_desc->g) {
3880 kvm_desct->limit <<= 12;
3881 kvm_desct->limit |= 0xfff;
3882 }
37817f29
IE		 3883 kvm_desct->selector = selector;
3884 kvm_desct->type = seg_desc->type;
3885 kvm_desct->present = seg_desc->p;
3886 kvm_desct->dpl = seg_desc->dpl;
3887 kvm_desct->db = seg_desc->d;
3888 kvm_desct->s = seg_desc->s;
3889 kvm_desct->l = seg_desc->l;
3890 kvm_desct->g = seg_desc->g;
3891 kvm_desct->avl = seg_desc->avl;
3892 if (!selector)
3893 kvm_desct->unusable = 1;
3894 else
3895 kvm_desct->unusable = 0;
3896 kvm_desct->padding = 0;
3897}
3898
b8222ad2
AS		 3899static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
3900 u16 selector,
3901 struct descriptor_table *dtable)
37817f29
IE		 3902{
3903 if (selector & 1 << 2) {
3904 struct kvm_segment kvm_seg;
3905
3e6e0aab 3906 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 3907
3908 if (kvm_seg.unusable)
3909 dtable->limit = 0;
3910 else
3911 dtable->limit = kvm_seg.limit;
3912 dtable->base = kvm_seg.base;
3913 }
3914 else
3915 kvm_x86_ops->get_gdt(vcpu, dtable);
3916}
3917
3918/* allowed just for 8 bytes segments */
3919static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3920 struct desc_struct *seg_desc)
3921{
98899aa0 3922 gpa_t gpa;
37817f29
IE		 3923 struct descriptor_table dtable;
3924 u16 index = selector >> 3;
3925
b8222ad2 3926 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3927
3928 if (dtable.limit < index * 8 + 7) {
3929 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
3930 return 1;
3931 }
98899aa0
MT		 3932 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3933 gpa += index * 8;
3934 return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3935}
3936
3937/* allowed just for 8 bytes segments */
3938static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3939 struct desc_struct *seg_desc)
3940{
98899aa0 3941 gpa_t gpa;
37817f29
IE		 3942 struct descriptor_table dtable;
3943 u16 index = selector >> 3;
3944
b8222ad2 3945 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3946
3947 if (dtable.limit < index * 8 + 7)
3948 return 1;
98899aa0
MT		 3949 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3950 gpa += index * 8;
3951 return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3952}
3953
3954static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
3955 struct desc_struct *seg_desc)
3956{
3957 u32 base_addr;
3958
3959 base_addr = seg_desc->base0;
3960 base_addr |= (seg_desc->base1 << 16);
3961 base_addr |= (seg_desc->base2 << 24);
3962
98899aa0 3963 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 3964}
3965
37817f29
IE		 3966static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
3967{
3968 struct kvm_segment kvm_seg;
3969
3e6e0aab 3970 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3971 return kvm_seg.selector;
3972}
3973
3974static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
3975 u16 selector,
3976 struct kvm_segment *kvm_seg)
3977{
3978 struct desc_struct seg_desc;
3979
3980 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
3981 return 1;
3982 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
3983 return 0;
3984}
3985
2259e3a7 3986static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 3987{
3988 struct kvm_segment segvar = {
3989 .base = selector << 4,
3990 .limit = 0xffff,
3991 .selector = selector,
3992 .type = 3,
3993 .present = 1,
3994 .dpl = 3,
3995 .db = 0,
3996 .s = 1,
3997 .l = 0,
3998 .g = 0,
3999 .avl = 0,
4000 .unusable = 0,
4001 };
4002 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
4003 return 0;
4004}
4005
3e6e0aab
GT		 4006int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4007 int type_bits, int seg)
37817f29
IE		 4008{
4009 struct kvm_segment kvm_seg;
4010
f4bbd9aa
AK		 4011 if (!(vcpu->arch.cr0 & X86_CR0_PE))
4012 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 4013 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
4014 return 1;
4015 kvm_seg.type |= type_bits;
4016
4017 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
4018 seg != VCPU_SREG_LDTR)
4019 if (!kvm_seg.s)
4020 kvm_seg.unusable = 1;
4021
3e6e0aab 4022 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4023 return 0;
4024}
4025
4026static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4027 struct tss_segment_32 *tss)
4028{
4029 tss->cr3 = vcpu->arch.cr3;
5fdbf976 4030 tss->eip = kvm_rip_read(vcpu);
37817f29 4031 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 4032 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4033 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4034 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4035 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4036 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4037 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4038 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4039 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4040 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4041 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4042 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4043 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4044 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4045 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4046 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4047}
4048
4049static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4050 struct tss_segment_32 *tss)
4051{
4052 kvm_set_cr3(vcpu, tss->cr3);
4053
5fdbf976 4054 kvm_rip_write(vcpu, tss->eip);
37817f29
IE		 4055 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
4056
5fdbf976
MT		 4057 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4058 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4059 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4060 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4061 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
4062 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
4063 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
4064 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 4065
3e6e0aab 4066 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 4067 return 1;
4068
3e6e0aab 4069 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4070 return 1;
4071
3e6e0aab 4072 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4073 return 1;
4074
3e6e0aab 4075 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4076 return 1;
4077
3e6e0aab 4078 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4079 return 1;
4080
3e6e0aab 4081 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 4082 return 1;
4083
3e6e0aab 4084 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 4085 return 1;
4086 return 0;
4087}
4088
4089static void save_state_to_tss16(struct kvm_vcpu *vcpu,
4090 struct tss_segment_16 *tss)
4091{
5fdbf976 4092 tss->ip = kvm_rip_read(vcpu);
37817f29 4093 tss->flag = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 4094 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4095 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4096 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4097 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4098 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4099 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4100 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
4101 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4102
4103 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4104 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4105 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4106 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4107 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
4108 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
4109}
4110
4111static int load_state_from_tss16(struct kvm_vcpu *vcpu,
4112 struct tss_segment_16 *tss)
4113{
5fdbf976 4114 kvm_rip_write(vcpu, tss->ip);
37817f29 4115 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 4116 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
4117 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
4118 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
4119 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
4120 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
4121 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
4122 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
4123 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 4124
3e6e0aab 4125 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 4126 return 1;
4127
3e6e0aab 4128 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4129 return 1;
4130
3e6e0aab 4131 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4132 return 1;
4133
3e6e0aab 4134 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4135 return 1;
4136
3e6e0aab 4137 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4138 return 1;
4139 return 0;
4140}
4141
8b2cf73c 4142static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37
GN		 4143 u16 old_tss_sel, u32 old_tss_base,
4144 struct desc_struct *nseg_desc)
37817f29
IE		 4145{
4146 struct tss_segment_16 tss_segment_16;
4147 int ret = 0;
4148
34198bf8
MT		 4149 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4150 sizeof tss_segment_16))
37817f29
IE		 4151 goto out;
4152
4153 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 4154
34198bf8
MT		 4155 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4156 sizeof tss_segment_16))
37817f29 4157 goto out;
34198bf8
MT		 4158
4159 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4160 &tss_segment_16, sizeof tss_segment_16))
4161 goto out;
4162
b237ac37
GN		 4163 if (old_tss_sel != 0xffff) {
4164 tss_segment_16.prev_task_link = old_tss_sel;
4165
4166 if (kvm_write_guest(vcpu->kvm,
4167 get_tss_base_addr(vcpu, nseg_desc),
4168 &tss_segment_16.prev_task_link,
4169 sizeof tss_segment_16.prev_task_link))
4170 goto out;
4171 }
4172
37817f29
IE		 4173 if (load_state_from_tss16(vcpu, &tss_segment_16))
4174 goto out;
4175
4176 ret = 1;
4177out:
4178 return ret;
4179}
4180
8b2cf73c 4181static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37 4182 u16 old_tss_sel, u32 old_tss_base,
37817f29
IE		 4183 struct desc_struct *nseg_desc)
4184{
4185 struct tss_segment_32 tss_segment_32;
4186 int ret = 0;
4187
34198bf8
MT		 4188 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4189 sizeof tss_segment_32))
37817f29
IE		 4190 goto out;
4191
4192 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 4193
34198bf8
MT		 4194 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4195 sizeof tss_segment_32))
4196 goto out;
4197
4198 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4199 &tss_segment_32, sizeof tss_segment_32))
37817f29 4200 goto out;
34198bf8 4201
b237ac37
GN		 4202 if (old_tss_sel != 0xffff) {
4203 tss_segment_32.prev_task_link = old_tss_sel;
4204
4205 if (kvm_write_guest(vcpu->kvm,
4206 get_tss_base_addr(vcpu, nseg_desc),
4207 &tss_segment_32.prev_task_link,
4208 sizeof tss_segment_32.prev_task_link))
4209 goto out;
4210 }
4211
37817f29
IE		 4212 if (load_state_from_tss32(vcpu, &tss_segment_32))
4213 goto out;
4214
4215 ret = 1;
4216out:
4217 return ret;
4218}
4219
4220int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
4221{
4222 struct kvm_segment tr_seg;
4223 struct desc_struct cseg_desc;
4224 struct desc_struct nseg_desc;
4225 int ret = 0;
34198bf8
MT		 4226 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
4227 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 4228
34198bf8 4229 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 4230
34198bf8
MT		 4231 /* FIXME: Handle errors. Failure to read either TSS or their
4232 * descriptors should generate a pagefault.
4233 */
37817f29
IE		 4234 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
4235 goto out;
4236
34198bf8 4237 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 4238 goto out;
4239
37817f29
IE		 4240 if (reason != TASK_SWITCH_IRET) {
4241 int cpl;
4242
4243 cpl = kvm_x86_ops->get_cpl(vcpu);
4244 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
4245 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
4246 return 1;
4247 }
4248 }
4249
4250 if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) {
4251 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
4252 return 1;
4253 }
4254
4255 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 4256 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 4257 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 4258 }
4259
4260 if (reason == TASK_SWITCH_IRET) {
4261 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4262 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
4263 }
4264
64a7ec06
GN		 4265 /* set back link to prev task only if NT bit is set in eflags
4266 note that old_tss_sel is not used afetr this point */
4267 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4268 old_tss_sel = 0xffff;
37817f29 4269
b237ac37
GN		 4270 /* set back link to prev task only if NT bit is set in eflags
4271 note that old_tss_sel is not used afetr this point */
4272 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4273 old_tss_sel = 0xffff;
4274
37817f29 4275 if (nseg_desc.type & 8)
b237ac37
GN		 4276 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
4277 old_tss_base, &nseg_desc);
37817f29 4278 else
b237ac37
GN		 4279 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
4280 old_tss_base, &nseg_desc);
37817f29
IE		 4281
4282 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
4283 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4284 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
4285 }
4286
4287 if (reason != TASK_SWITCH_IRET) {
3fe913e7 4288 nseg_desc.type |= (1 << 1);
37817f29
IE		 4289 save_guest_segment_descriptor(vcpu, tss_selector,
4290 &nseg_desc);
4291 }
4292
4293 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
4294 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
4295 tr_seg.type = 11;
3e6e0aab 4296 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 4297out:
37817f29
IE		 4298 return ret;
4299}
4300EXPORT_SYMBOL_GPL(kvm_task_switch);
4301
b6c7a5dc
HB		 4302int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4303 struct kvm_sregs *sregs)
4304{
4305 int mmu_reset_needed = 0;
923c61bb 4306 int pending_vec, max_bits;
b6c7a5dc
HB		 4307 struct descriptor_table dt;
4308
4309 vcpu_load(vcpu);
4310
4311 dt.limit = sregs->idt.limit;
4312 dt.base = sregs->idt.base;
4313 kvm_x86_ops->set_idt(vcpu, &dt);
4314 dt.limit = sregs->gdt.limit;
4315 dt.base = sregs->gdt.base;
4316 kvm_x86_ops->set_gdt(vcpu, &dt);
4317
ad312c7c
ZX		 4318 vcpu->arch.cr2 = sregs->cr2;
4319 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
59839dff
MT		 4320
4321 down_read(&vcpu->kvm->slots_lock);
4322 if (gfn_to_memslot(vcpu->kvm, sregs->cr3 >> PAGE_SHIFT))
4323 vcpu->arch.cr3 = sregs->cr3;
4324 else
4325 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
4326 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc 4327
2d3ad1f4 4328 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 4329
ad312c7c 4330 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 4331 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 4332 kvm_set_apic_base(vcpu, sregs->apic_base);
4333
4334 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
4335
ad312c7c 4336 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 4337 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 4338 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 4339
ad312c7c 4340 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 4341 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
4342 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 4343 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 4344
4345 if (mmu_reset_needed)
4346 kvm_mmu_reset_context(vcpu);
4347
923c61bb
GN		 4348 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4349 pending_vec = find_first_bit(
4350 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4351 if (pending_vec < max_bits) {
66fd3f7f 4352 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 4353 pr_debug("Set back pending irq %d\n", pending_vec);
4354 if (irqchip_in_kernel(vcpu->kvm))
4355 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 4356 }
4357
3e6e0aab
GT		 4358 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4359 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4360 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4361 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4362 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4363 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4364
3e6e0aab
GT		 4365 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4366 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 4367
9c3e4aab 4368 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 4369 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab
MT		 4370 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
4371 !(vcpu->arch.cr0 & X86_CR0_PE))
4372 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4373
b6c7a5dc
HB		 4374 vcpu_put(vcpu);
4375
4376 return 0;
4377}
4378
d0bfb940
JK		 4379int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4380 struct kvm_guest_debug *dbg)
b6c7a5dc 4381{
ae675ef0 4382 int i, r;
b6c7a5dc
HB		 4383
4384 vcpu_load(vcpu);
4385
ae675ef0
JK		 4386 if ((dbg->control & (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) ==
4387 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) {
4388 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4389 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4390 vcpu->arch.switch_db_regs =
4391 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4392 } else {
4393 for (i = 0; i < KVM_NR_DB_REGS; i++)
4394 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4395 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4396 }
4397
b6c7a5dc
HB		 4398 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
4399
d0bfb940
JK		 4400 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
4401 kvm_queue_exception(vcpu, DB_VECTOR);
4402 else if (dbg->control & KVM_GUESTDBG_INJECT_BP)
4403 kvm_queue_exception(vcpu, BP_VECTOR);
4404
b6c7a5dc
HB		 4405 vcpu_put(vcpu);
4406
4407 return r;
4408}
4409
d0752060
HB		 4410/*
4411 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4412 * we have asm/x86/processor.h
4413 */
4414struct fxsave {
4415 u16 cwd;
4416 u16 swd;
4417 u16 twd;
4418 u16 fop;
4419 u64 rip;
4420 u64 rdp;
4421 u32 mxcsr;
4422 u32 mxcsr_mask;
4423 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
4424#ifdef CONFIG_X86_64
4425 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
4426#else
4427 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
4428#endif
4429};
4430
8b006791
ZX		 4431/*
4432 * Translate a guest virtual address to a guest physical address.
4433 */
4434int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
4435 struct kvm_translation *tr)
4436{
4437 unsigned long vaddr = tr->linear_address;
4438 gpa_t gpa;
4439
4440 vcpu_load(vcpu);
72dc67a6 4441 down_read(&vcpu->kvm->slots_lock);
ad312c7c 4442 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 4443 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 4444 tr->physical_address = gpa;
4445 tr->valid = gpa != UNMAPPED_GVA;
4446 tr->writeable = 1;
4447 tr->usermode = 0;
8b006791
ZX		 4448 vcpu_put(vcpu);
4449
4450 return 0;
4451}
4452
d0752060
HB		 4453int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4454{
ad312c7c 4455 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4456
4457 vcpu_load(vcpu);
4458
4459 memcpy(fpu->fpr, fxsave->st_space, 128);
4460 fpu->fcw = fxsave->cwd;
4461 fpu->fsw = fxsave->swd;
4462 fpu->ftwx = fxsave->twd;
4463 fpu->last_opcode = fxsave->fop;
4464 fpu->last_ip = fxsave->rip;
4465 fpu->last_dp = fxsave->rdp;
4466 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
4467
4468 vcpu_put(vcpu);
4469
4470 return 0;
4471}
4472
4473int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4474{
ad312c7c 4475 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4476
4477 vcpu_load(vcpu);
4478
4479 memcpy(fxsave->st_space, fpu->fpr, 128);
4480 fxsave->cwd = fpu->fcw;
4481 fxsave->swd = fpu->fsw;
4482 fxsave->twd = fpu->ftwx;
4483 fxsave->fop = fpu->last_opcode;
4484 fxsave->rip = fpu->last_ip;
4485 fxsave->rdp = fpu->last_dp;
4486 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
4487
4488 vcpu_put(vcpu);
4489
4490 return 0;
4491}
4492
4493void fx_init(struct kvm_vcpu *vcpu)
4494{
4495 unsigned after_mxcsr_mask;
4496
bc1a34f1
AA		 4497 /*
4498 * Touch the fpu the first time in non atomic context as if
4499 * this is the first fpu instruction the exception handler
4500 * will fire before the instruction returns and it'll have to
4501 * allocate ram with GFP_KERNEL.
4502 */
4503 if (!used_math())
d6e88aec 4504 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 4505
d0752060
HB		 4506 /* Initialize guest FPU by resetting ours and saving into guest's */
4507 preempt_disable();
d6e88aec
AK		 4508 kvm_fx_save(&vcpu->arch.host_fx_image);
4509 kvm_fx_finit();
4510 kvm_fx_save(&vcpu->arch.guest_fx_image);
4511 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 4512 preempt_enable();
4513
ad312c7c 4514 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 4515 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 4516 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
4517 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 4518 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
4519}
4520EXPORT_SYMBOL_GPL(fx_init);
4521
4522void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
4523{
4524 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
4525 return;
4526
4527 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 4528 kvm_fx_save(&vcpu->arch.host_fx_image);
4529 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 4530}
4531EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
4532
4533void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
4534{
4535 if (!vcpu->guest_fpu_loaded)
4536 return;
4537
4538 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 4539 kvm_fx_save(&vcpu->arch.guest_fx_image);
4540 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 4541 ++vcpu->stat.fpu_reload;
d0752060
HB		 4542}
4543EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 4544
4545void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
4546{
7f1ea208
JR		 4547 if (vcpu->arch.time_page) {
4548 kvm_release_page_dirty(vcpu->arch.time_page);
4549 vcpu->arch.time_page = NULL;
4550 }
4551
e9b11c17
ZX		 4552 kvm_x86_ops->vcpu_free(vcpu);
4553}
4554
4555struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
4556 unsigned int id)
4557{
26e5215f
AK		 4558 return kvm_x86_ops->vcpu_create(kvm, id);
4559}
e9b11c17 4560
26e5215f
AK		 4561int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
4562{
4563 int r;
e9b11c17
ZX		 4564
4565 /* We do fxsave: this must be aligned. */
ad312c7c 4566 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 4567
0bed3b56 4568 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 4569 vcpu_load(vcpu);
4570 r = kvm_arch_vcpu_reset(vcpu);
4571 if (r == 0)
4572 r = kvm_mmu_setup(vcpu);
4573 vcpu_put(vcpu);
4574 if (r < 0)
4575 goto free_vcpu;
4576
26e5215f 4577 return 0;
e9b11c17
ZX		 4578free_vcpu:
4579 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 4580 return r;
e9b11c17
ZX		 4581}
4582
d40ccc62 4583void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 4584{
4585 vcpu_load(vcpu);
4586 kvm_mmu_unload(vcpu);
4587 vcpu_put(vcpu);
4588
4589 kvm_x86_ops->vcpu_free(vcpu);
4590}
4591
4592int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4593{
448fa4a9
JK		 4594 vcpu->arch.nmi_pending = false;
4595 vcpu->arch.nmi_injected = false;
4596
42dbaa5a
JK		 4597 vcpu->arch.switch_db_regs = 0;
4598 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
4599 vcpu->arch.dr6 = DR6_FIXED_1;
4600 vcpu->arch.dr7 = DR7_FIXED_1;
4601
e9b11c17
ZX		 4602 return kvm_x86_ops->vcpu_reset(vcpu);
4603}
4604
4605void kvm_arch_hardware_enable(void *garbage)
4606{
4607 kvm_x86_ops->hardware_enable(garbage);
4608}
4609
4610void kvm_arch_hardware_disable(void *garbage)
4611{
4612 kvm_x86_ops->hardware_disable(garbage);
4613}
4614
4615int kvm_arch_hardware_setup(void)
4616{
4617 return kvm_x86_ops->hardware_setup();
4618}
4619
4620void kvm_arch_hardware_unsetup(void)
4621{
4622 kvm_x86_ops->hardware_unsetup();
4623}
4624
4625void kvm_arch_check_processor_compat(void *rtn)
4626{
4627 kvm_x86_ops->check_processor_compatibility(rtn);
4628}
4629
4630int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
4631{
4632 struct page *page;
4633 struct kvm *kvm;
4634 int r;
4635
4636 BUG_ON(vcpu->kvm == NULL);
4637 kvm = vcpu->kvm;
4638
ad312c7c 4639 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 4640 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 4641 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 4642 else
a4535290 4643 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 4644
4645 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
4646 if (!page) {
4647 r = -ENOMEM;
4648 goto fail;
4649 }
ad312c7c 4650 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 4651
4652 r = kvm_mmu_create(vcpu);
4653 if (r < 0)
4654 goto fail_free_pio_data;
4655
4656 if (irqchip_in_kernel(kvm)) {
4657 r = kvm_create_lapic(vcpu);
4658 if (r < 0)
4659 goto fail_mmu_destroy;
4660 }
4661
890ca9ae
HY		 4662 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
4663 GFP_KERNEL);
4664 if (!vcpu->arch.mce_banks) {
4665 r = -ENOMEM;
4666 goto fail_mmu_destroy;
4667 }
4668 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
4669
e9b11c17
ZX		 4670 return 0;
4671
4672fail_mmu_destroy:
4673 kvm_mmu_destroy(vcpu);
4674fail_free_pio_data:
ad312c7c 4675 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 4676fail:
4677 return r;
4678}
4679
4680void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
4681{
4682 kvm_free_lapic(vcpu);
3200f405 4683 down_read(&vcpu->kvm->slots_lock);
e9b11c17 4684 kvm_mmu_destroy(vcpu);
3200f405 4685 up_read(&vcpu->kvm->slots_lock);
ad312c7c 4686 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 4687}
d19a9cd2
ZX		 4688
4689struct kvm *kvm_arch_create_vm(void)
4690{
4691 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
4692
4693 if (!kvm)
4694 return ERR_PTR(-ENOMEM);
4695
f05e70ac 4696 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 4697 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 4698
5550af4d
SY		 4699 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
4700 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
4701
53f658b3
MT		 4702 rdtscll(kvm->arch.vm_init_tsc);
4703
d19a9cd2
ZX		 4704 return kvm;
4705}
4706
4707static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
4708{
4709 vcpu_load(vcpu);
4710 kvm_mmu_unload(vcpu);
4711 vcpu_put(vcpu);
4712}
4713
4714static void kvm_free_vcpus(struct kvm *kvm)
4715{
4716 unsigned int i;
988a2cae 4717 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 4718
4719 /*
4720 * Unpin any mmu pages first.
4721 */
988a2cae
GN		 4722 kvm_for_each_vcpu(i, vcpu, kvm)
4723 kvm_unload_vcpu_mmu(vcpu);
4724 kvm_for_each_vcpu(i, vcpu, kvm)
4725 kvm_arch_vcpu_free(vcpu);
4726
4727 mutex_lock(&kvm->lock);
4728 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
4729 kvm->vcpus[i] = NULL;
d19a9cd2 4730
988a2cae
GN		 4731 atomic_set(&kvm->online_vcpus, 0);
4732 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 4733}
4734
ad8ba2cd
SY		 4735void kvm_arch_sync_events(struct kvm *kvm)
4736{
ba4cef31 4737 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 4738}
4739
d19a9cd2
ZX		 4740void kvm_arch_destroy_vm(struct kvm *kvm)
4741{
6eb55818 4742 kvm_iommu_unmap_guest(kvm);
7837699f 4743 kvm_free_pit(kvm);
d7deeeb0
ZX		 4744 kfree(kvm->arch.vpic);
4745 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 4746 kvm_free_vcpus(kvm);
4747 kvm_free_physmem(kvm);
3d45830c
AK		 4748 if (kvm->arch.apic_access_page)
4749 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 4750 if (kvm->arch.ept_identity_pagetable)
4751 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 4752 kfree(kvm);
4753}
0de10343
ZX		 4754
4755int kvm_arch_set_memory_region(struct kvm *kvm,
4756 struct kvm_userspace_memory_region *mem,
4757 struct kvm_memory_slot old,
4758 int user_alloc)
4759{
4760 int npages = mem->memory_size >> PAGE_SHIFT;
4761 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
4762
4763 /*To keep backward compatibility with older userspace,
4764 *x86 needs to hanlde !user_alloc case.
4765 */
4766 if (!user_alloc) {
4767 if (npages && !old.rmap) {
604b38ac
AA		 4768 unsigned long userspace_addr;
4769
72dc67a6 4770 down_write(&current->mm->mmap_sem);
604b38ac
AA		 4771 userspace_addr = do_mmap(NULL, 0,
4772 npages * PAGE_SIZE,
4773 PROT_READ | PROT_WRITE,
acee3c04 4774 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 4775 0);
72dc67a6 4776 up_write(&current->mm->mmap_sem);
0de10343 4777
604b38ac
AA		 4778 if (IS_ERR((void *)userspace_addr))
4779 return PTR_ERR((void *)userspace_addr);
4780
4781 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4782 spin_lock(&kvm->mmu_lock);
4783 memslot->userspace_addr = userspace_addr;
4784 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4785 } else {
4786 if (!old.user_alloc && old.rmap) {
4787 int ret;
4788
72dc67a6 4789 down_write(&current->mm->mmap_sem);
0de10343
ZX		 4790 ret = do_munmap(current->mm, old.userspace_addr,
4791 old.npages * PAGE_SIZE);
72dc67a6 4792 up_write(&current->mm->mmap_sem);
0de10343
ZX		 4793 if (ret < 0)
4794 printk(KERN_WARNING
4795 "kvm_vm_ioctl_set_memory_region: "
4796 "failed to munmap memory\n");
4797 }
4798 }
4799 }
4800
7c8a83b7 4801 spin_lock(&kvm->mmu_lock);
f05e70ac 4802 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 4803 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4804 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4805 }
4806
4807 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 4808 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4809 kvm_flush_remote_tlbs(kvm);
4810
4811 return 0;
4812}
1d737c8a 4813
34d4cb8f
MT		 4814void kvm_arch_flush_shadow(struct kvm *kvm)
4815{
4816 kvm_mmu_zap_all(kvm);
8986ecc0 4817 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 4818}
4819
1d737c8a
ZX		 4820int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4821{
a4535290 4822 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
0496fbb9
JK		 4823 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
4824 || vcpu->arch.nmi_pending;
1d737c8a 4825}
5736199a 4826
5736199a
ZX		 4827void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4828{
32f88400
MT		 4829 int me;
4830 int cpu = vcpu->cpu;
5736199a
ZX		 4831
4832 if (waitqueue_active(&vcpu->wq)) {
4833 wake_up_interruptible(&vcpu->wq);
4834 ++vcpu->stat.halt_wakeup;
4835 }
32f88400
MT		 4836
4837 me = get_cpu();
4838 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
4839 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
4840 smp_send_reschedule(cpu);
e9571ed5 4841 put_cpu();
5736199a 4842}
78646121
GN		 4843
4844int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
4845{
4846 return kvm_x86_ops->interrupt_allowed(vcpu);
4847}
229456fc
MT		 4848
4849EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
4850EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
4851EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
4852EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
4853EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
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