]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - arch/x86/kvm/x86.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: x86: fix CR8 handling
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
af585b92 46#include <linux/hash.h>
aec51dc4 47#include <trace/events/kvm.h>
2ed152af 48
229456fc
MT		 49#define CREATE_TRACE_POINTS
50#include "trace.h"
043405e1 51
24f1e32c 52#include <asm/debugreg.h>
d825ed0a 53#include <asm/msr.h>
a5f61300 54#include <asm/desc.h>
0bed3b56 55#include <asm/mtrr.h>
890ca9ae 56#include <asm/mce.h>
7cf30855 57#include <asm/i387.h>
98918833 58#include <asm/xcr.h>
1d5f066e 59#include <asm/pvclock.h>
217fc9cf 60#include <asm/div64.h>
043405e1 61
313a3dc7 62#define MAX_IO_MSRS 256
a03490ed
CO		 63#define CR0_RESERVED_BITS \
64 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
65 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
66 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
67#define CR4_RESERVED_BITS \
68 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
69 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
70 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
2acf923e 71 | X86_CR4_OSXSAVE \
a03490ed
CO		 72 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
73
74#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 75
76#define KVM_MAX_MCE_BANKS 32
5854dbca 77#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 78
50a37eb4
JR		 79/* EFER defaults:
80 * - enable syscall per default because its emulated by KVM
81 * - enable LME and LMA per default on 64 bit KVM
82 */
83#ifdef CONFIG_X86_64
84static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
85#else
86static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
87#endif
313a3dc7 88
ba1389b7
AK		 89#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 91
cb142eb7 92static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 93static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
94 struct kvm_cpuid_entry2 __user *entries);
95
97896d04 96struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 97EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 98
ed85c068
AP		 99int ignore_msrs = 0;
100module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
101
18863bdd
AK		 102#define KVM_NR_SHARED_MSRS 16
103
104struct kvm_shared_msrs_global {
105 int nr;
2bf78fa7 106 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 107};
108
109struct kvm_shared_msrs {
110 struct user_return_notifier urn;
111 bool registered;
2bf78fa7
SY		 112 struct kvm_shared_msr_values {
113 u64 host;
114 u64 curr;
115 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 116};
117
118static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
119static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
120
417bc304 121struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 122 { "pf_fixed", VCPU_STAT(pf_fixed) },
123 { "pf_guest", VCPU_STAT(pf_guest) },
124 { "tlb_flush", VCPU_STAT(tlb_flush) },
125 { "invlpg", VCPU_STAT(invlpg) },
126 { "exits", VCPU_STAT(exits) },
127 { "io_exits", VCPU_STAT(io_exits) },
128 { "mmio_exits", VCPU_STAT(mmio_exits) },
129 { "signal_exits", VCPU_STAT(signal_exits) },
130 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 131 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 132 { "halt_exits", VCPU_STAT(halt_exits) },
133 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 134 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 135 { "request_irq", VCPU_STAT(request_irq_exits) },
136 { "irq_exits", VCPU_STAT(irq_exits) },
137 { "host_state_reload", VCPU_STAT(host_state_reload) },
138 { "efer_reload", VCPU_STAT(efer_reload) },
139 { "fpu_reload", VCPU_STAT(fpu_reload) },
140 { "insn_emulation", VCPU_STAT(insn_emulation) },
141 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 142 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 143 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 144 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
145 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
146 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
147 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
148 { "mmu_flooded", VM_STAT(mmu_flooded) },
149 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 150 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 151 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 152 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 153 { "largepages", VM_STAT(lpages) },
417bc304
HB		 154 { NULL }
155};
156
2acf923e
DC		 157u64 __read_mostly host_xcr0;
158
af585b92
GN		 159static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
160{
161 int i;
162 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
163 vcpu->arch.apf.gfns[i] = ~0;
164}
165
18863bdd
AK		 166static void kvm_on_user_return(struct user_return_notifier *urn)
167{
168 unsigned slot;
18863bdd
AK		 169 struct kvm_shared_msrs *locals
170 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 171 struct kvm_shared_msr_values *values;
18863bdd
AK		 172
173 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 174 values = &locals->values[slot];
175 if (values->host != values->curr) {
176 wrmsrl(shared_msrs_global.msrs[slot], values->host);
177 values->curr = values->host;
18863bdd
AK		 178 }
179 }
180 locals->registered = false;
181 user_return_notifier_unregister(urn);
182}
183
2bf78fa7 184static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 185{
2bf78fa7 186 struct kvm_shared_msrs *smsr;
18863bdd
AK		 187 u64 value;
188
2bf78fa7
SY		 189 smsr = &__get_cpu_var(shared_msrs);
190 /* only read, and nobody should modify it at this time,
191 * so don't need lock */
192 if (slot >= shared_msrs_global.nr) {
193 printk(KERN_ERR "kvm: invalid MSR slot!");
194 return;
195 }
196 rdmsrl_safe(msr, &value);
197 smsr->values[slot].host = value;
198 smsr->values[slot].curr = value;
199}
200
201void kvm_define_shared_msr(unsigned slot, u32 msr)
202{
18863bdd
AK		 203 if (slot >= shared_msrs_global.nr)
204 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 205 shared_msrs_global.msrs[slot] = msr;
206 /* we need ensured the shared_msr_global have been updated */
207 smp_wmb();
18863bdd
AK		 208}
209EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
210
211static void kvm_shared_msr_cpu_online(void)
212{
213 unsigned i;
18863bdd
AK		 214
215 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 216 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 217}
218
d5696725 219void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 220{
221 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
222
2bf78fa7 223 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 224 return;
2bf78fa7
SY		 225 smsr->values[slot].curr = value;
226 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 227 if (!smsr->registered) {
228 smsr->urn.on_user_return = kvm_on_user_return;
229 user_return_notifier_register(&smsr->urn);
230 smsr->registered = true;
231 }
232}
233EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
234
3548bab5
AK		 235static void drop_user_return_notifiers(void *ignore)
236{
237 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
238
239 if (smsr->registered)
240 kvm_on_user_return(&smsr->urn);
241}
242
6866b83e
CO		 243u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
244{
245 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 246 return vcpu->arch.apic_base;
6866b83e 247 else
ad312c7c 248 return vcpu->arch.apic_base;
6866b83e
CO		 249}
250EXPORT_SYMBOL_GPL(kvm_get_apic_base);
251
252void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
253{
254 /* TODO: reserve bits check */
255 if (irqchip_in_kernel(vcpu->kvm))
256 kvm_lapic_set_base(vcpu, data);
257 else
ad312c7c 258 vcpu->arch.apic_base = data;
6866b83e
CO		 259}
260EXPORT_SYMBOL_GPL(kvm_set_apic_base);
261
3fd28fce
ED		 262#define EXCPT_BENIGN 0
263#define EXCPT_CONTRIBUTORY 1
264#define EXCPT_PF 2
265
266static int exception_class(int vector)
267{
268 switch (vector) {
269 case PF_VECTOR:
270 return EXCPT_PF;
271 case DE_VECTOR:
272 case TS_VECTOR:
273 case NP_VECTOR:
274 case SS_VECTOR:
275 case GP_VECTOR:
276 return EXCPT_CONTRIBUTORY;
277 default:
278 break;
279 }
280 return EXCPT_BENIGN;
281}
282
283static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 284 unsigned nr, bool has_error, u32 error_code,
285 bool reinject)
3fd28fce
ED		 286{
287 u32 prev_nr;
288 int class1, class2;
289
3842d135
AK		 290 kvm_make_request(KVM_REQ_EVENT, vcpu);
291
3fd28fce
ED		 292 if (!vcpu->arch.exception.pending) {
293 queue:
294 vcpu->arch.exception.pending = true;
295 vcpu->arch.exception.has_error_code = has_error;
296 vcpu->arch.exception.nr = nr;
297 vcpu->arch.exception.error_code = error_code;
3f0fd292 298 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 299 return;
300 }
301
302 /* to check exception */
303 prev_nr = vcpu->arch.exception.nr;
304 if (prev_nr == DF_VECTOR) {
305 /* triple fault -> shutdown */
a8eeb04a 306 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 307 return;
308 }
309 class1 = exception_class(prev_nr);
310 class2 = exception_class(nr);
311 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
312 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
313 /* generate double fault per SDM Table 5-5 */
314 vcpu->arch.exception.pending = true;
315 vcpu->arch.exception.has_error_code = true;
316 vcpu->arch.exception.nr = DF_VECTOR;
317 vcpu->arch.exception.error_code = 0;
318 } else
319 /* replace previous exception with a new one in a hope
320 that instruction re-execution will regenerate lost
321 exception */
322 goto queue;
323}
324
298101da
AK		 325void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
326{
ce7ddec4 327 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 328}
329EXPORT_SYMBOL_GPL(kvm_queue_exception);
330
ce7ddec4
JR		 331void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
332{
333 kvm_multiple_exception(vcpu, nr, false, 0, true);
334}
335EXPORT_SYMBOL_GPL(kvm_requeue_exception);
336
6389ee94 337void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 338{
339 ++vcpu->stat.pf_guest;
6389ee94
AK		 340 vcpu->arch.cr2 = fault->address;
341 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee
AK		 342}
343
6389ee94 344void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 345{
6389ee94
AK		 346 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
347 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 348 else
6389ee94 349 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 350}
351
3419ffc8
SY		 352void kvm_inject_nmi(struct kvm_vcpu *vcpu)
353{
3842d135 354 kvm_make_request(KVM_REQ_EVENT, vcpu);
3419ffc8
SY		 355 vcpu->arch.nmi_pending = 1;
356}
357EXPORT_SYMBOL_GPL(kvm_inject_nmi);
358
298101da
AK		 359void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
360{
ce7ddec4 361 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 362}
363EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
364
ce7ddec4
JR		 365void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
366{
367 kvm_multiple_exception(vcpu, nr, true, error_code, true);
368}
369EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
370
0a79b009
AK		 371/*
372 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
373 * a #GP and return false.
374 */
375bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 376{
0a79b009
AK		 377 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
378 return true;
379 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
380 return false;
298101da 381}
0a79b009 382EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 383
ec92fe44
JR		 384/*
385 * This function will be used to read from the physical memory of the currently
386 * running guest. The difference to kvm_read_guest_page is that this function
387 * can read from guest physical or from the guest's guest physical memory.
388 */
389int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
390 gfn_t ngfn, void *data, int offset, int len,
391 u32 access)
392{
393 gfn_t real_gfn;
394 gpa_t ngpa;
395
396 ngpa = gfn_to_gpa(ngfn);
397 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
398 if (real_gfn == UNMAPPED_GVA)
399 return -EFAULT;
400
401 real_gfn = gpa_to_gfn(real_gfn);
402
403 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
404}
405EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
406
3d06b8bf
JR		 407int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
408 void *data, int offset, int len, u32 access)
409{
410 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
411 data, offset, len, access);
412}
413
a03490ed
CO		 414/*
415 * Load the pae pdptrs. Return true is they are all valid.
416 */
ff03a073 417int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 418{
419 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
420 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
421 int i;
422 int ret;
ff03a073 423 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 424
ff03a073
JR		 425 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
426 offset * sizeof(u64), sizeof(pdpte),
427 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 428 if (ret < 0) {
429 ret = 0;
430 goto out;
431 }
432 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 433 if (is_present_gpte(pdpte[i]) &&
20c466b5 434 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 435 ret = 0;
436 goto out;
437 }
438 }
439 ret = 1;
440
ff03a073 441 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 442 __set_bit(VCPU_EXREG_PDPTR,
443 (unsigned long *)&vcpu->arch.regs_avail);
444 __set_bit(VCPU_EXREG_PDPTR,
445 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 446out:
a03490ed
CO		 447
448 return ret;
449}
cc4b6871 450EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 451
d835dfec
AK		 452static bool pdptrs_changed(struct kvm_vcpu *vcpu)
453{
ff03a073 454 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 455 bool changed = true;
3d06b8bf
JR		 456 int offset;
457 gfn_t gfn;
d835dfec
AK		 458 int r;
459
460 if (is_long_mode(vcpu) || !is_pae(vcpu))
461 return false;
462
6de4f3ad
AK		 463 if (!test_bit(VCPU_EXREG_PDPTR,
464 (unsigned long *)&vcpu->arch.regs_avail))
465 return true;
466
3d06b8bf
JR		 467 gfn = (vcpu->arch.cr3 & ~31u) >> PAGE_SHIFT;
468 offset = (vcpu->arch.cr3 & ~31u) & (PAGE_SIZE - 1);
469 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
470 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 471 if (r < 0)
472 goto out;
ff03a073 473 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 474out:
d835dfec
AK		 475
476 return changed;
477}
478
49a9b07e 479int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 480{
aad82703
SY		 481 unsigned long old_cr0 = kvm_read_cr0(vcpu);
482 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
483 X86_CR0_CD | X86_CR0_NW;
484
f9a48e6a
AK		 485 cr0 |= X86_CR0_ET;
486
ab344828 487#ifdef CONFIG_X86_64
0f12244f
GN		 488 if (cr0 & 0xffffffff00000000UL)
489 return 1;
ab344828
GN		 490#endif
491
492 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 493
0f12244f
GN		 494 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
495 return 1;
a03490ed 496
0f12244f
GN		 497 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
498 return 1;
a03490ed
CO		 499
500 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
501#ifdef CONFIG_X86_64
f6801dff 502 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 503 int cs_db, cs_l;
504
0f12244f
GN		 505 if (!is_pae(vcpu))
506 return 1;
a03490ed 507 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 508 if (cs_l)
509 return 1;
a03490ed
CO		 510 } else
511#endif
ff03a073
JR		 512 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
513 vcpu->arch.cr3))
0f12244f 514 return 1;
a03490ed
CO		 515 }
516
517 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 518
e5f3f027
XG		 519 if ((cr0 ^ old_cr0) & X86_CR0_PG)
520 kvm_clear_async_pf_completion_queue(vcpu);
521
aad82703
SY		 522 if ((cr0 ^ old_cr0) & update_bits)
523 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 524 return 0;
525}
2d3ad1f4 526EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 527
2d3ad1f4 528void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 529{
49a9b07e 530 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 531}
2d3ad1f4 532EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 533
2acf923e
DC		 534int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
535{
536 u64 xcr0;
537
538 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
539 if (index != XCR_XFEATURE_ENABLED_MASK)
540 return 1;
541 xcr0 = xcr;
542 if (kvm_x86_ops->get_cpl(vcpu) != 0)
543 return 1;
544 if (!(xcr0 & XSTATE_FP))
545 return 1;
546 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
547 return 1;
548 if (xcr0 & ~host_xcr0)
549 return 1;
550 vcpu->arch.xcr0 = xcr0;
551 vcpu->guest_xcr0_loaded = 0;
552 return 0;
553}
554
555int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
556{
557 if (__kvm_set_xcr(vcpu, index, xcr)) {
558 kvm_inject_gp(vcpu, 0);
559 return 1;
560 }
561 return 0;
562}
563EXPORT_SYMBOL_GPL(kvm_set_xcr);
564
565static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
566{
567 struct kvm_cpuid_entry2 *best;
568
569 best = kvm_find_cpuid_entry(vcpu, 1, 0);
570 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
571}
572
573static void update_cpuid(struct kvm_vcpu *vcpu)
574{
575 struct kvm_cpuid_entry2 *best;
576
577 best = kvm_find_cpuid_entry(vcpu, 1, 0);
578 if (!best)
579 return;
580
581 /* Update OSXSAVE bit */
582 if (cpu_has_xsave && best->function == 0x1) {
583 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
584 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
585 best->ecx |= bit(X86_FEATURE_OSXSAVE);
586 }
587}
588
a83b29c6 589int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 590{
fc78f519 591 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 592 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
593
0f12244f
GN		 594 if (cr4 & CR4_RESERVED_BITS)
595 return 1;
a03490ed 596
2acf923e
DC		 597 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
598 return 1;
599
a03490ed 600 if (is_long_mode(vcpu)) {
0f12244f
GN		 601 if (!(cr4 & X86_CR4_PAE))
602 return 1;
a2edf57f
AK		 603 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
604 && ((cr4 ^ old_cr4) & pdptr_bits)
ff03a073 605 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3))
0f12244f
GN		 606 return 1;
607
608 if (cr4 & X86_CR4_VMXE)
609 return 1;
a03490ed 610
a03490ed 611 kvm_x86_ops->set_cr4(vcpu, cr4);
62ad0755 612
aad82703
SY		 613 if ((cr4 ^ old_cr4) & pdptr_bits)
614 kvm_mmu_reset_context(vcpu);
0f12244f 615
2acf923e
DC		 616 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
617 update_cpuid(vcpu);
618
0f12244f
GN		 619 return 0;
620}
2d3ad1f4 621EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 622
2390218b 623int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 624{
ad312c7c 625 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 626 kvm_mmu_sync_roots(vcpu);
d835dfec 627 kvm_mmu_flush_tlb(vcpu);
0f12244f 628 return 0;
d835dfec
AK		 629 }
630
a03490ed 631 if (is_long_mode(vcpu)) {
0f12244f
GN		 632 if (cr3 & CR3_L_MODE_RESERVED_BITS)
633 return 1;
a03490ed
CO		 634 } else {
635 if (is_pae(vcpu)) {
0f12244f
GN		 636 if (cr3 & CR3_PAE_RESERVED_BITS)
637 return 1;
ff03a073
JR		 638 if (is_paging(vcpu) &&
639 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 640 return 1;
a03490ed
CO		 641 }
642 /*
643 * We don't check reserved bits in nonpae mode, because
644 * this isn't enforced, and VMware depends on this.
645 */
646 }
647
a03490ed
CO		 648 /*
649 * Does the new cr3 value map to physical memory? (Note, we
650 * catch an invalid cr3 even in real-mode, because it would
651 * cause trouble later on when we turn on paging anyway.)
652 *
653 * A real CPU would silently accept an invalid cr3 and would
654 * attempt to use it - with largely undefined (and often hard
655 * to debug) behavior on the guest side.
656 */
657 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 658 return 1;
659 vcpu->arch.cr3 = cr3;
660 vcpu->arch.mmu.new_cr3(vcpu);
661 return 0;
662}
2d3ad1f4 663EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 664
eea1cff9 665int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 666{
0f12244f
GN		 667 if (cr8 & CR8_RESERVED_BITS)
668 return 1;
a03490ed
CO		 669 if (irqchip_in_kernel(vcpu->kvm))
670 kvm_lapic_set_tpr(vcpu, cr8);
671 else
ad312c7c 672 vcpu->arch.cr8 = cr8;
0f12244f
GN		 673 return 0;
674}
2d3ad1f4 675EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 676
2d3ad1f4 677unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 678{
679 if (irqchip_in_kernel(vcpu->kvm))
680 return kvm_lapic_get_cr8(vcpu);
681 else
ad312c7c 682 return vcpu->arch.cr8;
a03490ed 683}
2d3ad1f4 684EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 685
338dbc97 686static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 687{
688 switch (dr) {
689 case 0 ... 3:
690 vcpu->arch.db[dr] = val;
691 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
692 vcpu->arch.eff_db[dr] = val;
693 break;
694 case 4:
338dbc97
GN		 695 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
696 return 1; /* #UD */
020df079
GN		 697 /* fall through */
698 case 6:
338dbc97
GN		 699 if (val & 0xffffffff00000000ULL)
700 return -1; /* #GP */
020df079
GN		 701 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
702 break;
703 case 5:
338dbc97
GN		 704 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
705 return 1; /* #UD */
020df079
GN		 706 /* fall through */
707 default: /* 7 */
338dbc97
GN		 708 if (val & 0xffffffff00000000ULL)
709 return -1; /* #GP */
020df079
GN		 710 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
711 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
712 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
713 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
714 }
715 break;
716 }
717
718 return 0;
719}
338dbc97
GN		 720
721int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
722{
723 int res;
724
725 res = __kvm_set_dr(vcpu, dr, val);
726 if (res > 0)
727 kvm_queue_exception(vcpu, UD_VECTOR);
728 else if (res < 0)
729 kvm_inject_gp(vcpu, 0);
730
731 return res;
732}
020df079
GN		 733EXPORT_SYMBOL_GPL(kvm_set_dr);
734
338dbc97 735static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 736{
737 switch (dr) {
738 case 0 ... 3:
739 *val = vcpu->arch.db[dr];
740 break;
741 case 4:
338dbc97 742 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 743 return 1;
020df079
GN		 744 /* fall through */
745 case 6:
746 *val = vcpu->arch.dr6;
747 break;
748 case 5:
338dbc97 749 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 750 return 1;
020df079
GN		 751 /* fall through */
752 default: /* 7 */
753 *val = vcpu->arch.dr7;
754 break;
755 }
756
757 return 0;
758}
338dbc97
GN		 759
760int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
761{
762 if (_kvm_get_dr(vcpu, dr, val)) {
763 kvm_queue_exception(vcpu, UD_VECTOR);
764 return 1;
765 }
766 return 0;
767}
020df079
GN		 768EXPORT_SYMBOL_GPL(kvm_get_dr);
769
043405e1
CO		 770/*
771 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
772 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
773 *
774 * This list is modified at module load time to reflect the
e3267cbb
GC		 775 * capabilities of the host cpu. This capabilities test skips MSRs that are
776 * kvm-specific. Those are put in the beginning of the list.
043405e1 777 */
e3267cbb 778
344d9588 779#define KVM_SAVE_MSRS_BEGIN 8
043405e1 780static u32 msrs_to_save[] = {
e3267cbb 781 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 782 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 783 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
344d9588 784 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN,
043405e1 785 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 786 MSR_STAR,
043405e1
CO		 787#ifdef CONFIG_X86_64
788 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
789#endif
e90aa41e 790 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 791};
792
793static unsigned num_msrs_to_save;
794
795static u32 emulated_msrs[] = {
796 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 797 MSR_IA32_MCG_STATUS,
798 MSR_IA32_MCG_CTL,
043405e1
CO		 799};
800
b69e8cae 801static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 802{
aad82703
SY		 803 u64 old_efer = vcpu->arch.efer;
804
b69e8cae
RJ		 805 if (efer & efer_reserved_bits)
806 return 1;
15c4a640
CO		 807
808 if (is_paging(vcpu)
b69e8cae
RJ		 809 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
810 return 1;
15c4a640 811
1b2fd70c
AG		 812 if (efer & EFER_FFXSR) {
813 struct kvm_cpuid_entry2 *feat;
814
815 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 816 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
817 return 1;
1b2fd70c
AG		 818 }
819
d8017474
AG		 820 if (efer & EFER_SVME) {
821 struct kvm_cpuid_entry2 *feat;
822
823 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 824 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
825 return 1;
d8017474
AG		 826 }
827
15c4a640 828 efer &= ~EFER_LMA;
f6801dff 829 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 830
a3d204e2
SY		 831 kvm_x86_ops->set_efer(vcpu, efer);
832
9645bb56 833 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 834
aad82703
SY		 835 /* Update reserved bits */
836 if ((efer ^ old_efer) & EFER_NX)
837 kvm_mmu_reset_context(vcpu);
838
b69e8cae 839 return 0;
15c4a640
CO		 840}
841
f2b4b7dd
JR		 842void kvm_enable_efer_bits(u64 mask)
843{
844 efer_reserved_bits &= ~mask;
845}
846EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
847
848
15c4a640
CO		 849/*
850 * Writes msr value into into the appropriate "register".
851 * Returns 0 on success, non-0 otherwise.
852 * Assumes vcpu_load() was already called.
853 */
854int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
855{
856 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
857}
858
313a3dc7
CO		 859/*
860 * Adapt set_msr() to msr_io()'s calling convention
861 */
862static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
863{
864 return kvm_set_msr(vcpu, index, *data);
865}
866
18068523
GOC		 867static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
868{
9ed3c444
AK		 869 int version;
870 int r;
50d0a0f9 871 struct pvclock_wall_clock wc;
923de3cf 872 struct timespec boot;
18068523
GOC		 873
874 if (!wall_clock)
875 return;
876
9ed3c444
AK		 877 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
878 if (r)
879 return;
880
881 if (version & 1)
882 ++version; /* first time write, random junk */
883
884 ++version;
18068523 885
18068523
GOC		 886 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
887
50d0a0f9
GH		 888 /*
889 * The guest calculates current wall clock time by adding
34c238a1 890 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 891 * wall clock specified here. guest system time equals host
892 * system time for us, thus we must fill in host boot time here.
893 */
923de3cf 894 getboottime(&boot);
50d0a0f9
GH		 895
896 wc.sec = boot.tv_sec;
897 wc.nsec = boot.tv_nsec;
898 wc.version = version;
18068523
GOC		 899
900 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
901
902 version++;
903 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 904}
905
50d0a0f9
GH		 906static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
907{
908 uint32_t quotient, remainder;
909
910 /* Don't try to replace with do_div(), this one calculates
911 * "(dividend << 32) / divisor" */
912 __asm__ ( "divl %4"
913 : "=a" (quotient), "=d" (remainder)
914 : "0" (0), "1" (dividend), "r" (divisor) );
915 return quotient;
916}
917
5f4e3f88
ZA		 918static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
919 s8 *pshift, u32 *pmultiplier)
50d0a0f9 920{
5f4e3f88 921 uint64_t scaled64;
50d0a0f9
GH		 922 int32_t shift = 0;
923 uint64_t tps64;
924 uint32_t tps32;
925
5f4e3f88
ZA		 926 tps64 = base_khz * 1000LL;
927 scaled64 = scaled_khz * 1000LL;
50933623 928 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 929 tps64 >>= 1;
930 shift--;
931 }
932
933 tps32 = (uint32_t)tps64;
50933623
JK		 934 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
935 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 936 scaled64 >>= 1;
937 else
938 tps32 <<= 1;
50d0a0f9
GH		 939 shift++;
940 }
941
5f4e3f88
ZA		 942 *pshift = shift;
943 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 944
5f4e3f88
ZA		 945 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
946 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 947}
948
759379dd
ZA		 949static inline u64 get_kernel_ns(void)
950{
951 struct timespec ts;
952
953 WARN_ON(preemptible());
954 ktime_get_ts(&ts);
955 monotonic_to_bootbased(&ts);
956 return timespec_to_ns(&ts);
50d0a0f9
GH		 957}
958
c8076604 959static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 960unsigned long max_tsc_khz;
c8076604 961
8cfdc000
ZA		 962static inline int kvm_tsc_changes_freq(void)
963{
964 int cpu = get_cpu();
965 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
966 cpufreq_quick_get(cpu) != 0;
967 put_cpu();
968 return ret;
969}
970
759379dd
ZA		 971static inline u64 nsec_to_cycles(u64 nsec)
972{
217fc9cf
AK		 973 u64 ret;
974
759379dd
ZA		 975 WARN_ON(preemptible());
976 if (kvm_tsc_changes_freq())
977 printk_once(KERN_WARNING
978 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
217fc9cf
AK		 979 ret = nsec * __get_cpu_var(cpu_tsc_khz);
980 do_div(ret, USEC_PER_SEC);
981 return ret;
759379dd
ZA		 982}
983
c285545f
ZA		 984static void kvm_arch_set_tsc_khz(struct kvm *kvm, u32 this_tsc_khz)
985{
986 /* Compute a scale to convert nanoseconds in TSC cycles */
987 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
988 &kvm->arch.virtual_tsc_shift,
989 &kvm->arch.virtual_tsc_mult);
990 kvm->arch.virtual_tsc_khz = this_tsc_khz;
991}
992
993static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
994{
995 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
996 vcpu->kvm->arch.virtual_tsc_mult,
997 vcpu->kvm->arch.virtual_tsc_shift);
998 tsc += vcpu->arch.last_tsc_write;
999 return tsc;
1000}
1001
99e3e30a
ZA		 1002void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1003{
1004 struct kvm *kvm = vcpu->kvm;
f38e098f 1005 u64 offset, ns, elapsed;
99e3e30a 1006 unsigned long flags;
46543ba4 1007 s64 sdiff;
99e3e30a
ZA		 1008
1009 spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1010 offset = data - native_read_tsc();
759379dd 1011 ns = get_kernel_ns();
f38e098f 1012 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 1013 sdiff = data - kvm->arch.last_tsc_write;
1014 if (sdiff < 0)
1015 sdiff = -sdiff;
f38e098f
ZA		 1016
1017 /*
46543ba4 1018 * Special case: close write to TSC within 5 seconds of
f38e098f 1019 * another CPU is interpreted as an attempt to synchronize
46543ba4
ZA		 1020 * The 5 seconds is to accomodate host load / swapping as
1021 * well as any reset of TSC during the boot process.
f38e098f
ZA		 1022 *
1023 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 1024 * or make a best guest using elapsed value.
f38e098f 1025 */
46543ba4
ZA		 1026 if (sdiff < nsec_to_cycles(5ULL * NSEC_PER_SEC) &&
1027 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 1028 if (!check_tsc_unstable()) {
1029 offset = kvm->arch.last_tsc_offset;
1030 pr_debug("kvm: matched tsc offset for %llu\n", data);
1031 } else {
759379dd
ZA		 1032 u64 delta = nsec_to_cycles(elapsed);
1033 offset += delta;
1034 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1035 }
1036 ns = kvm->arch.last_tsc_nsec;
1037 }
1038 kvm->arch.last_tsc_nsec = ns;
1039 kvm->arch.last_tsc_write = data;
1040 kvm->arch.last_tsc_offset = offset;
99e3e30a
ZA		 1041 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1042 spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1043
1044 /* Reset of TSC must disable overshoot protection below */
1045 vcpu->arch.hv_clock.tsc_timestamp = 0;
c285545f
ZA		 1046 vcpu->arch.last_tsc_write = data;
1047 vcpu->arch.last_tsc_nsec = ns;
99e3e30a
ZA		 1048}
1049EXPORT_SYMBOL_GPL(kvm_write_tsc);
1050
34c238a1 1051static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1052{
18068523
GOC		 1053 unsigned long flags;
1054 struct kvm_vcpu_arch *vcpu = &v->arch;
1055 void *shared_kaddr;
463656c0 1056 unsigned long this_tsc_khz;
1d5f066e
ZA		 1057 s64 kernel_ns, max_kernel_ns;
1058 u64 tsc_timestamp;
18068523 1059
18068523
GOC		 1060 /* Keep irq disabled to prevent changes to the clock */
1061 local_irq_save(flags);
1d5f066e 1062 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
759379dd 1063 kernel_ns = get_kernel_ns();
8cfdc000 1064 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
18068523 1065
8cfdc000 1066 if (unlikely(this_tsc_khz == 0)) {
c285545f 1067 local_irq_restore(flags);
34c238a1 1068 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1069 return 1;
1070 }
18068523 1071
c285545f
ZA		 1072 /*
1073 * We may have to catch up the TSC to match elapsed wall clock
1074 * time for two reasons, even if kvmclock is used.
1075 * 1) CPU could have been running below the maximum TSC rate
1076 * 2) Broken TSC compensation resets the base at each VCPU
1077 * entry to avoid unknown leaps of TSC even when running
1078 * again on the same CPU. This may cause apparent elapsed
1079 * time to disappear, and the guest to stand still or run
1080 * very slowly.
1081 */
1082 if (vcpu->tsc_catchup) {
1083 u64 tsc = compute_guest_tsc(v, kernel_ns);
1084 if (tsc > tsc_timestamp) {
1085 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1086 tsc_timestamp = tsc;
1087 }
50d0a0f9
GH		 1088 }
1089
18068523
GOC		 1090 local_irq_restore(flags);
1091
c285545f
ZA		 1092 if (!vcpu->time_page)
1093 return 0;
18068523 1094
1d5f066e
ZA		 1095 /*
1096 * Time as measured by the TSC may go backwards when resetting the base
1097 * tsc_timestamp. The reason for this is that the TSC resolution is
1098 * higher than the resolution of the other clock scales. Thus, many
1099 * possible measurments of the TSC correspond to one measurement of any
1100 * other clock, and so a spread of values is possible. This is not a
1101 * problem for the computation of the nanosecond clock; with TSC rates
1102 * around 1GHZ, there can only be a few cycles which correspond to one
1103 * nanosecond value, and any path through this code will inevitably
1104 * take longer than that. However, with the kernel_ns value itself,
1105 * the precision may be much lower, down to HZ granularity. If the
1106 * first sampling of TSC against kernel_ns ends in the low part of the
1107 * range, and the second in the high end of the range, we can get:
1108 *
1109 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1110 *
1111 * As the sampling errors potentially range in the thousands of cycles,
1112 * it is possible such a time value has already been observed by the
1113 * guest. To protect against this, we must compute the system time as
1114 * observed by the guest and ensure the new system time is greater.
1115 */
1116 max_kernel_ns = 0;
1117 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1118 max_kernel_ns = vcpu->last_guest_tsc -
1119 vcpu->hv_clock.tsc_timestamp;
1120 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1121 vcpu->hv_clock.tsc_to_system_mul,
1122 vcpu->hv_clock.tsc_shift);
1123 max_kernel_ns += vcpu->last_kernel_ns;
1124 }
afbcf7ab 1125
e48672fa 1126 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1127 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1128 &vcpu->hv_clock.tsc_shift,
1129 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1130 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1131 }
1132
1d5f066e
ZA		 1133 if (max_kernel_ns > kernel_ns)
1134 kernel_ns = max_kernel_ns;
1135
8cfdc000 1136 /* With all the info we got, fill in the values */
1d5f066e 1137 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1138 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1139 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1140 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1141 vcpu->hv_clock.flags = 0;
1142
18068523
GOC		 1143 /*
1144 * The interface expects us to write an even number signaling that the
1145 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1146 * state, we just increase by 2 at the end.
18068523 1147 */
50d0a0f9 1148 vcpu->hv_clock.version += 2;
18068523
GOC		 1149
1150 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1151
1152 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1153 sizeof(vcpu->hv_clock));
18068523
GOC		 1154
1155 kunmap_atomic(shared_kaddr, KM_USER0);
1156
1157 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1158 return 0;
c8076604
GH		 1159}
1160
9ba075a6
AK		 1161static bool msr_mtrr_valid(unsigned msr)
1162{
1163 switch (msr) {
1164 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1165 case MSR_MTRRfix64K_00000:
1166 case MSR_MTRRfix16K_80000:
1167 case MSR_MTRRfix16K_A0000:
1168 case MSR_MTRRfix4K_C0000:
1169 case MSR_MTRRfix4K_C8000:
1170 case MSR_MTRRfix4K_D0000:
1171 case MSR_MTRRfix4K_D8000:
1172 case MSR_MTRRfix4K_E0000:
1173 case MSR_MTRRfix4K_E8000:
1174 case MSR_MTRRfix4K_F0000:
1175 case MSR_MTRRfix4K_F8000:
1176 case MSR_MTRRdefType:
1177 case MSR_IA32_CR_PAT:
1178 return true;
1179 case 0x2f8:
1180 return true;
1181 }
1182 return false;
1183}
1184
d6289b93
MT		 1185static bool valid_pat_type(unsigned t)
1186{
1187 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1188}
1189
1190static bool valid_mtrr_type(unsigned t)
1191{
1192 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1193}
1194
1195static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1196{
1197 int i;
1198
1199 if (!msr_mtrr_valid(msr))
1200 return false;
1201
1202 if (msr == MSR_IA32_CR_PAT) {
1203 for (i = 0; i < 8; i++)
1204 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1205 return false;
1206 return true;
1207 } else if (msr == MSR_MTRRdefType) {
1208 if (data & ~0xcff)
1209 return false;
1210 return valid_mtrr_type(data & 0xff);
1211 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1212 for (i = 0; i < 8 ; i++)
1213 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1214 return false;
1215 return true;
1216 }
1217
1218 /* variable MTRRs */
1219 return valid_mtrr_type(data & 0xff);
1220}
1221
9ba075a6
AK		 1222static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1223{
0bed3b56
SY		 1224 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1225
d6289b93 1226 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1227 return 1;
1228
0bed3b56
SY		 1229 if (msr == MSR_MTRRdefType) {
1230 vcpu->arch.mtrr_state.def_type = data;
1231 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1232 } else if (msr == MSR_MTRRfix64K_00000)
1233 p[0] = data;
1234 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1235 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1236 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1237 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1238 else if (msr == MSR_IA32_CR_PAT)
1239 vcpu->arch.pat = data;
1240 else { /* Variable MTRRs */
1241 int idx, is_mtrr_mask;
1242 u64 *pt;
1243
1244 idx = (msr - 0x200) / 2;
1245 is_mtrr_mask = msr - 0x200 - 2 * idx;
1246 if (!is_mtrr_mask)
1247 pt =
1248 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1249 else
1250 pt =
1251 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1252 *pt = data;
1253 }
1254
1255 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1256 return 0;
1257}
15c4a640 1258
890ca9ae 1259static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1260{
890ca9ae
HY		 1261 u64 mcg_cap = vcpu->arch.mcg_cap;
1262 unsigned bank_num = mcg_cap & 0xff;
1263
15c4a640 1264 switch (msr) {
15c4a640 1265 case MSR_IA32_MCG_STATUS:
890ca9ae 1266 vcpu->arch.mcg_status = data;
15c4a640 1267 break;
c7ac679c 1268 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1269 if (!(mcg_cap & MCG_CTL_P))
1270 return 1;
1271 if (data != 0 && data != ~(u64)0)
1272 return -1;
1273 vcpu->arch.mcg_ctl = data;
1274 break;
1275 default:
1276 if (msr >= MSR_IA32_MC0_CTL &&
1277 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1278 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1279 /* only 0 or all 1s can be written to IA32_MCi_CTL
1280 * some Linux kernels though clear bit 10 in bank 4 to
1281 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1282 * this to avoid an uncatched #GP in the guest
1283 */
890ca9ae 1284 if ((offset & 0x3) == 0 &&
114be429 1285 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1286 return -1;
1287 vcpu->arch.mce_banks[offset] = data;
1288 break;
1289 }
1290 return 1;
1291 }
1292 return 0;
1293}
1294
ffde22ac
ES		 1295static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1296{
1297 struct kvm *kvm = vcpu->kvm;
1298 int lm = is_long_mode(vcpu);
1299 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1300 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1301 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1302 : kvm->arch.xen_hvm_config.blob_size_32;
1303 u32 page_num = data & ~PAGE_MASK;
1304 u64 page_addr = data & PAGE_MASK;
1305 u8 *page;
1306 int r;
1307
1308 r = -E2BIG;
1309 if (page_num >= blob_size)
1310 goto out;
1311 r = -ENOMEM;
1312 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1313 if (!page)
1314 goto out;
1315 r = -EFAULT;
1316 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1317 goto out_free;
1318 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1319 goto out_free;
1320 r = 0;
1321out_free:
1322 kfree(page);
1323out:
1324 return r;
1325}
1326
55cd8e5a
GN		 1327static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1328{
1329 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1330}
1331
1332static bool kvm_hv_msr_partition_wide(u32 msr)
1333{
1334 bool r = false;
1335 switch (msr) {
1336 case HV_X64_MSR_GUEST_OS_ID:
1337 case HV_X64_MSR_HYPERCALL:
1338 r = true;
1339 break;
1340 }
1341
1342 return r;
1343}
1344
1345static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1346{
1347 struct kvm *kvm = vcpu->kvm;
1348
1349 switch (msr) {
1350 case HV_X64_MSR_GUEST_OS_ID:
1351 kvm->arch.hv_guest_os_id = data;
1352 /* setting guest os id to zero disables hypercall page */
1353 if (!kvm->arch.hv_guest_os_id)
1354 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1355 break;
1356 case HV_X64_MSR_HYPERCALL: {
1357 u64 gfn;
1358 unsigned long addr;
1359 u8 instructions[4];
1360
1361 /* if guest os id is not set hypercall should remain disabled */
1362 if (!kvm->arch.hv_guest_os_id)
1363 break;
1364 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1365 kvm->arch.hv_hypercall = data;
1366 break;
1367 }
1368 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1369 addr = gfn_to_hva(kvm, gfn);
1370 if (kvm_is_error_hva(addr))
1371 return 1;
1372 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1373 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1374 if (copy_to_user((void __user *)addr, instructions, 4))
1375 return 1;
1376 kvm->arch.hv_hypercall = data;
1377 break;
1378 }
1379 default:
1380 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1381 "data 0x%llx\n", msr, data);
1382 return 1;
1383 }
1384 return 0;
1385}
1386
1387static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1388{
10388a07
GN		 1389 switch (msr) {
1390 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1391 unsigned long addr;
55cd8e5a 1392
10388a07
GN		 1393 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1394 vcpu->arch.hv_vapic = data;
1395 break;
1396 }
1397 addr = gfn_to_hva(vcpu->kvm, data >>
1398 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1399 if (kvm_is_error_hva(addr))
1400 return 1;
1401 if (clear_user((void __user *)addr, PAGE_SIZE))
1402 return 1;
1403 vcpu->arch.hv_vapic = data;
1404 break;
1405 }
1406 case HV_X64_MSR_EOI:
1407 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1408 case HV_X64_MSR_ICR:
1409 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1410 case HV_X64_MSR_TPR:
1411 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1412 default:
1413 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1414 "data 0x%llx\n", msr, data);
1415 return 1;
1416 }
1417
1418 return 0;
55cd8e5a
GN		 1419}
1420
344d9588
GN		 1421static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1422{
1423 gpa_t gpa = data & ~0x3f;
1424
6adba527
GN		 1425 /* Bits 2:5 are resrved, Should be zero */
1426 if (data & 0x3c)
344d9588
GN		 1427 return 1;
1428
1429 vcpu->arch.apf.msr_val = data;
1430
1431 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1432 kvm_clear_async_pf_completion_queue(vcpu);
1433 kvm_async_pf_hash_reset(vcpu);
1434 return 0;
1435 }
1436
1437 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1438 return 1;
1439
6adba527 1440 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1441 kvm_async_pf_wakeup_all(vcpu);
1442 return 0;
1443}
1444
15c4a640
CO		 1445int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1446{
1447 switch (msr) {
15c4a640 1448 case MSR_EFER:
b69e8cae 1449 return set_efer(vcpu, data);
8f1589d9
AP		 1450 case MSR_K7_HWCR:
1451 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1452 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1453 if (data != 0) {
1454 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1455 data);
1456 return 1;
1457 }
15c4a640 1458 break;
f7c6d140
AP		 1459 case MSR_FAM10H_MMIO_CONF_BASE:
1460 if (data != 0) {
1461 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1462 "0x%llx\n", data);
1463 return 1;
1464 }
15c4a640 1465 break;
c323c0e5 1466 case MSR_AMD64_NB_CFG:
c7ac679c 1467 break;
b5e2fec0
AG		 1468 case MSR_IA32_DEBUGCTLMSR:
1469 if (!data) {
1470 /* We support the non-activated case already */
1471 break;
1472 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1473 /* Values other than LBR and BTF are vendor-specific,
1474 thus reserved and should throw a #GP */
1475 return 1;
1476 }
1477 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1478 __func__, data);
1479 break;
15c4a640
CO		 1480 case MSR_IA32_UCODE_REV:
1481 case MSR_IA32_UCODE_WRITE:
61a6bd67 1482 case MSR_VM_HSAVE_PA:
6098ca93 1483 case MSR_AMD64_PATCH_LOADER:
15c4a640 1484 break;
9ba075a6
AK		 1485 case 0x200 ... 0x2ff:
1486 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1487 case MSR_IA32_APICBASE:
1488 kvm_set_apic_base(vcpu, data);
1489 break;
0105d1a5
GN		 1490 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1491 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1492 case MSR_IA32_MISC_ENABLE:
ad312c7c 1493 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1494 break;
11c6bffa 1495 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1496 case MSR_KVM_WALL_CLOCK:
1497 vcpu->kvm->arch.wall_clock = data;
1498 kvm_write_wall_clock(vcpu->kvm, data);
1499 break;
11c6bffa 1500 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1501 case MSR_KVM_SYSTEM_TIME: {
1502 if (vcpu->arch.time_page) {
1503 kvm_release_page_dirty(vcpu->arch.time_page);
1504 vcpu->arch.time_page = NULL;
1505 }
1506
1507 vcpu->arch.time = data;
c285545f 1508 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1509
1510 /* we verify if the enable bit is set... */
1511 if (!(data & 1))
1512 break;
1513
1514 /* ...but clean it before doing the actual write */
1515 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1516
18068523
GOC		 1517 vcpu->arch.time_page =
1518 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1519
1520 if (is_error_page(vcpu->arch.time_page)) {
1521 kvm_release_page_clean(vcpu->arch.time_page);
1522 vcpu->arch.time_page = NULL;
1523 }
18068523
GOC		 1524 break;
1525 }
344d9588
GN		 1526 case MSR_KVM_ASYNC_PF_EN:
1527 if (kvm_pv_enable_async_pf(vcpu, data))
1528 return 1;
1529 break;
890ca9ae
HY		 1530 case MSR_IA32_MCG_CTL:
1531 case MSR_IA32_MCG_STATUS:
1532 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1533 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1534
1535 /* Performance counters are not protected by a CPUID bit,
1536 * so we should check all of them in the generic path for the sake of
1537 * cross vendor migration.
1538 * Writing a zero into the event select MSRs disables them,
1539 * which we perfectly emulate ;-). Any other value should be at least
1540 * reported, some guests depend on them.
1541 */
1542 case MSR_P6_EVNTSEL0:
1543 case MSR_P6_EVNTSEL1:
1544 case MSR_K7_EVNTSEL0:
1545 case MSR_K7_EVNTSEL1:
1546 case MSR_K7_EVNTSEL2:
1547 case MSR_K7_EVNTSEL3:
1548 if (data != 0)
1549 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1550 "0x%x data 0x%llx\n", msr, data);
1551 break;
1552 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1553 * so we ignore writes to make it happy.
1554 */
1555 case MSR_P6_PERFCTR0:
1556 case MSR_P6_PERFCTR1:
1557 case MSR_K7_PERFCTR0:
1558 case MSR_K7_PERFCTR1:
1559 case MSR_K7_PERFCTR2:
1560 case MSR_K7_PERFCTR3:
1561 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1562 "0x%x data 0x%llx\n", msr, data);
1563 break;
84e0cefa
JS		 1564 case MSR_K7_CLK_CTL:
1565 /*
1566 * Ignore all writes to this no longer documented MSR.
1567 * Writes are only relevant for old K7 processors,
1568 * all pre-dating SVM, but a recommended workaround from
1569 * AMD for these chips. It is possible to speicify the
1570 * affected processor models on the command line, hence
1571 * the need to ignore the workaround.
1572 */
1573 break;
55cd8e5a
GN		 1574 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1575 if (kvm_hv_msr_partition_wide(msr)) {
1576 int r;
1577 mutex_lock(&vcpu->kvm->lock);
1578 r = set_msr_hyperv_pw(vcpu, msr, data);
1579 mutex_unlock(&vcpu->kvm->lock);
1580 return r;
1581 } else
1582 return set_msr_hyperv(vcpu, msr, data);
1583 break;
15c4a640 1584 default:
ffde22ac
ES		 1585 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1586 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1587 if (!ignore_msrs) {
1588 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1589 msr, data);
1590 return 1;
1591 } else {
1592 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1593 msr, data);
1594 break;
1595 }
15c4a640
CO		 1596 }
1597 return 0;
1598}
1599EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1600
1601
1602/*
1603 * Reads an msr value (of 'msr_index') into 'pdata'.
1604 * Returns 0 on success, non-0 otherwise.
1605 * Assumes vcpu_load() was already called.
1606 */
1607int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1608{
1609 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1610}
1611
9ba075a6
AK		 1612static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1613{
0bed3b56
SY		 1614 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1615
9ba075a6
AK		 1616 if (!msr_mtrr_valid(msr))
1617 return 1;
1618
0bed3b56
SY		 1619 if (msr == MSR_MTRRdefType)
1620 *pdata = vcpu->arch.mtrr_state.def_type +
1621 (vcpu->arch.mtrr_state.enabled << 10);
1622 else if (msr == MSR_MTRRfix64K_00000)
1623 *pdata = p[0];
1624 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1625 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1626 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1627 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1628 else if (msr == MSR_IA32_CR_PAT)
1629 *pdata = vcpu->arch.pat;
1630 else { /* Variable MTRRs */
1631 int idx, is_mtrr_mask;
1632 u64 *pt;
1633
1634 idx = (msr - 0x200) / 2;
1635 is_mtrr_mask = msr - 0x200 - 2 * idx;
1636 if (!is_mtrr_mask)
1637 pt =
1638 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1639 else
1640 pt =
1641 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1642 *pdata = *pt;
1643 }
1644
9ba075a6
AK		 1645 return 0;
1646}
1647
890ca9ae 1648static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1649{
1650 u64 data;
890ca9ae
HY		 1651 u64 mcg_cap = vcpu->arch.mcg_cap;
1652 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1653
1654 switch (msr) {
15c4a640
CO		 1655 case MSR_IA32_P5_MC_ADDR:
1656 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1657 data = 0;
1658 break;
15c4a640 1659 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1660 data = vcpu->arch.mcg_cap;
1661 break;
c7ac679c 1662 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1663 if (!(mcg_cap & MCG_CTL_P))
1664 return 1;
1665 data = vcpu->arch.mcg_ctl;
1666 break;
1667 case MSR_IA32_MCG_STATUS:
1668 data = vcpu->arch.mcg_status;
1669 break;
1670 default:
1671 if (msr >= MSR_IA32_MC0_CTL &&
1672 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1673 u32 offset = msr - MSR_IA32_MC0_CTL;
1674 data = vcpu->arch.mce_banks[offset];
1675 break;
1676 }
1677 return 1;
1678 }
1679 *pdata = data;
1680 return 0;
1681}
1682
55cd8e5a
GN		 1683static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1684{
1685 u64 data = 0;
1686 struct kvm *kvm = vcpu->kvm;
1687
1688 switch (msr) {
1689 case HV_X64_MSR_GUEST_OS_ID:
1690 data = kvm->arch.hv_guest_os_id;
1691 break;
1692 case HV_X64_MSR_HYPERCALL:
1693 data = kvm->arch.hv_hypercall;
1694 break;
1695 default:
1696 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1697 return 1;
1698 }
1699
1700 *pdata = data;
1701 return 0;
1702}
1703
1704static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1705{
1706 u64 data = 0;
1707
1708 switch (msr) {
1709 case HV_X64_MSR_VP_INDEX: {
1710 int r;
1711 struct kvm_vcpu *v;
1712 kvm_for_each_vcpu(r, v, vcpu->kvm)
1713 if (v == vcpu)
1714 data = r;
1715 break;
1716 }
10388a07
GN		 1717 case HV_X64_MSR_EOI:
1718 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1719 case HV_X64_MSR_ICR:
1720 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1721 case HV_X64_MSR_TPR:
1722 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1723 default:
1724 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1725 return 1;
1726 }
1727 *pdata = data;
1728 return 0;
1729}
1730
890ca9ae
HY		 1731int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1732{
1733 u64 data;
1734
1735 switch (msr) {
890ca9ae 1736 case MSR_IA32_PLATFORM_ID:
15c4a640 1737 case MSR_IA32_UCODE_REV:
15c4a640 1738 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1739 case MSR_IA32_DEBUGCTLMSR:
1740 case MSR_IA32_LASTBRANCHFROMIP:
1741 case MSR_IA32_LASTBRANCHTOIP:
1742 case MSR_IA32_LASTINTFROMIP:
1743 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1744 case MSR_K8_SYSCFG:
1745 case MSR_K7_HWCR:
61a6bd67 1746 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1747 case MSR_P6_PERFCTR0:
1748 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1749 case MSR_P6_EVNTSEL0:
1750 case MSR_P6_EVNTSEL1:
9e699624 1751 case MSR_K7_EVNTSEL0:
1f3ee616 1752 case MSR_K7_PERFCTR0:
1fdbd48c 1753 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1754 case MSR_AMD64_NB_CFG:
f7c6d140 1755 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1756 data = 0;
1757 break;
9ba075a6
AK		 1758 case MSR_MTRRcap:
1759 data = 0x500 | KVM_NR_VAR_MTRR;
1760 break;
1761 case 0x200 ... 0x2ff:
1762 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1763 case 0xcd: /* fsb frequency */
1764 data = 3;
1765 break;
7b914098
JS		 1766 /*
1767 * MSR_EBC_FREQUENCY_ID
1768 * Conservative value valid for even the basic CPU models.
1769 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1770 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1771 * and 266MHz for model 3, or 4. Set Core Clock
1772 * Frequency to System Bus Frequency Ratio to 1 (bits
1773 * 31:24) even though these are only valid for CPU
1774 * models > 2, however guests may end up dividing or
1775 * multiplying by zero otherwise.
1776 */
1777 case MSR_EBC_FREQUENCY_ID:
1778 data = 1 << 24;
1779 break;
15c4a640
CO		 1780 case MSR_IA32_APICBASE:
1781 data = kvm_get_apic_base(vcpu);
1782 break;
0105d1a5
GN		 1783 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1784 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1785 break;
15c4a640 1786 case MSR_IA32_MISC_ENABLE:
ad312c7c 1787 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1788 break;
847f0ad8
AG		 1789 case MSR_IA32_PERF_STATUS:
1790 /* TSC increment by tick */
1791 data = 1000ULL;
1792 /* CPU multiplier */
1793 data |= (((uint64_t)4ULL) << 40);
1794 break;
15c4a640 1795 case MSR_EFER:
f6801dff 1796 data = vcpu->arch.efer;
15c4a640 1797 break;
18068523 1798 case MSR_KVM_WALL_CLOCK:
11c6bffa 1799 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1800 data = vcpu->kvm->arch.wall_clock;
1801 break;
1802 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1803 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1804 data = vcpu->arch.time;
1805 break;
344d9588
GN		 1806 case MSR_KVM_ASYNC_PF_EN:
1807 data = vcpu->arch.apf.msr_val;
1808 break;
890ca9ae
HY		 1809 case MSR_IA32_P5_MC_ADDR:
1810 case MSR_IA32_P5_MC_TYPE:
1811 case MSR_IA32_MCG_CAP:
1812 case MSR_IA32_MCG_CTL:
1813 case MSR_IA32_MCG_STATUS:
1814 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1815 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1816 case MSR_K7_CLK_CTL:
1817 /*
1818 * Provide expected ramp-up count for K7. All other
1819 * are set to zero, indicating minimum divisors for
1820 * every field.
1821 *
1822 * This prevents guest kernels on AMD host with CPU
1823 * type 6, model 8 and higher from exploding due to
1824 * the rdmsr failing.
1825 */
1826 data = 0x20000000;
1827 break;
55cd8e5a
GN		 1828 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1829 if (kvm_hv_msr_partition_wide(msr)) {
1830 int r;
1831 mutex_lock(&vcpu->kvm->lock);
1832 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1833 mutex_unlock(&vcpu->kvm->lock);
1834 return r;
1835 } else
1836 return get_msr_hyperv(vcpu, msr, pdata);
1837 break;
15c4a640 1838 default:
ed85c068
AP		 1839 if (!ignore_msrs) {
1840 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1841 return 1;
1842 } else {
1843 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1844 data = 0;
1845 }
1846 break;
15c4a640
CO		 1847 }
1848 *pdata = data;
1849 return 0;
1850}
1851EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1852
313a3dc7
CO		 1853/*
1854 * Read or write a bunch of msrs. All parameters are kernel addresses.
1855 *
1856 * @return number of msrs set successfully.
1857 */
1858static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1859 struct kvm_msr_entry *entries,
1860 int (*do_msr)(struct kvm_vcpu *vcpu,
1861 unsigned index, u64 *data))
1862{
f656ce01 1863 int i, idx;
313a3dc7 1864
f656ce01 1865 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1866 for (i = 0; i < msrs->nmsrs; ++i)
1867 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1868 break;
f656ce01 1869 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1870
313a3dc7
CO		 1871 return i;
1872}
1873
1874/*
1875 * Read or write a bunch of msrs. Parameters are user addresses.
1876 *
1877 * @return number of msrs set successfully.
1878 */
1879static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1880 int (*do_msr)(struct kvm_vcpu *vcpu,
1881 unsigned index, u64 *data),
1882 int writeback)
1883{
1884 struct kvm_msrs msrs;
1885 struct kvm_msr_entry *entries;
1886 int r, n;
1887 unsigned size;
1888
1889 r = -EFAULT;
1890 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1891 goto out;
1892
1893 r = -E2BIG;
1894 if (msrs.nmsrs >= MAX_IO_MSRS)
1895 goto out;
1896
1897 r = -ENOMEM;
1898 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1899 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1900 if (!entries)
1901 goto out;
1902
1903 r = -EFAULT;
1904 if (copy_from_user(entries, user_msrs->entries, size))
1905 goto out_free;
1906
1907 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1908 if (r < 0)
1909 goto out_free;
1910
1911 r = -EFAULT;
1912 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1913 goto out_free;
1914
1915 r = n;
1916
1917out_free:
7a73c028 1918 kfree(entries);
313a3dc7
CO		 1919out:
1920 return r;
1921}
1922
018d00d2
ZX		 1923int kvm_dev_ioctl_check_extension(long ext)
1924{
1925 int r;
1926
1927 switch (ext) {
1928 case KVM_CAP_IRQCHIP:
1929 case KVM_CAP_HLT:
1930 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1931 case KVM_CAP_SET_TSS_ADDR:
07716717 1932 case KVM_CAP_EXT_CPUID:
c8076604 1933 case KVM_CAP_CLOCKSOURCE:
7837699f 1934 case KVM_CAP_PIT:
a28e4f5a 1935 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1936 case KVM_CAP_MP_STATE:
ed848624 1937 case KVM_CAP_SYNC_MMU:
a355c85c 1938 case KVM_CAP_USER_NMI:
52d939a0 1939 case KVM_CAP_REINJECT_CONTROL:
4925663a 1940 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1941 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1942 case KVM_CAP_IRQFD:
d34e6b17 1943 case KVM_CAP_IOEVENTFD:
c5ff41ce 1944 case KVM_CAP_PIT2:
e9f42757 1945 case KVM_CAP_PIT_STATE2:
b927a3ce 1946 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1947 case KVM_CAP_XEN_HVM:
afbcf7ab 1948 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1949 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1950 case KVM_CAP_HYPERV:
10388a07 1951 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1952 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1953 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1954 case KVM_CAP_DEBUGREGS:
d2be1651 1955 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 1956 case KVM_CAP_XSAVE:
344d9588 1957 case KVM_CAP_ASYNC_PF:
018d00d2
ZX		 1958 r = 1;
1959 break;
542472b5
LV		 1960 case KVM_CAP_COALESCED_MMIO:
1961 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1962 break;
774ead3a
AK		 1963 case KVM_CAP_VAPIC:
1964 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1965 break;
f725230a
AK		 1966 case KVM_CAP_NR_VCPUS:
1967 r = KVM_MAX_VCPUS;
1968 break;
a988b910
AK		 1969 case KVM_CAP_NR_MEMSLOTS:
1970 r = KVM_MEMORY_SLOTS;
1971 break;
a68a6a72
MT		 1972 case KVM_CAP_PV_MMU: /* obsolete */
1973 r = 0;
2f333bcb 1974 break;
62c476c7 1975 case KVM_CAP_IOMMU:
19de40a8 1976 r = iommu_found();
62c476c7 1977 break;
890ca9ae
HY		 1978 case KVM_CAP_MCE:
1979 r = KVM_MAX_MCE_BANKS;
1980 break;
2d5b5a66
SY		 1981 case KVM_CAP_XCRS:
1982 r = cpu_has_xsave;
1983 break;
018d00d2
ZX		 1984 default:
1985 r = 0;
1986 break;
1987 }
1988 return r;
1989
1990}
1991
043405e1
CO		 1992long kvm_arch_dev_ioctl(struct file *filp,
1993 unsigned int ioctl, unsigned long arg)
1994{
1995 void __user *argp = (void __user *)arg;
1996 long r;
1997
1998 switch (ioctl) {
1999 case KVM_GET_MSR_INDEX_LIST: {
2000 struct kvm_msr_list __user *user_msr_list = argp;
2001 struct kvm_msr_list msr_list;
2002 unsigned n;
2003
2004 r = -EFAULT;
2005 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2006 goto out;
2007 n = msr_list.nmsrs;
2008 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2009 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2010 goto out;
2011 r = -E2BIG;
e125e7b6 2012 if (n < msr_list.nmsrs)
043405e1
CO		 2013 goto out;
2014 r = -EFAULT;
2015 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2016 num_msrs_to_save * sizeof(u32)))
2017 goto out;
e125e7b6 2018 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2019 &emulated_msrs,
2020 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2021 goto out;
2022 r = 0;
2023 break;
2024 }
674eea0f
AK		 2025 case KVM_GET_SUPPORTED_CPUID: {
2026 struct kvm_cpuid2 __user *cpuid_arg = argp;
2027 struct kvm_cpuid2 cpuid;
2028
2029 r = -EFAULT;
2030 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2031 goto out;
2032 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2033 cpuid_arg->entries);
674eea0f
AK		 2034 if (r)
2035 goto out;
2036
2037 r = -EFAULT;
2038 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2039 goto out;
2040 r = 0;
2041 break;
2042 }
890ca9ae
HY		 2043 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2044 u64 mce_cap;
2045
2046 mce_cap = KVM_MCE_CAP_SUPPORTED;
2047 r = -EFAULT;
2048 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2049 goto out;
2050 r = 0;
2051 break;
2052 }
043405e1
CO		 2053 default:
2054 r = -EINVAL;
2055 }
2056out:
2057 return r;
2058}
2059
f5f48ee1
SY		 2060static void wbinvd_ipi(void *garbage)
2061{
2062 wbinvd();
2063}
2064
2065static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2066{
2067 return vcpu->kvm->arch.iommu_domain &&
2068 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2069}
2070
313a3dc7
CO		 2071void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2072{
f5f48ee1
SY		 2073 /* Address WBINVD may be executed by guest */
2074 if (need_emulate_wbinvd(vcpu)) {
2075 if (kvm_x86_ops->has_wbinvd_exit())
2076 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2077 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2078 smp_call_function_single(vcpu->cpu,
2079 wbinvd_ipi, NULL, 1);
2080 }
2081
313a3dc7 2082 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2083 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa
ZA		 2084 /* Make sure TSC doesn't go backwards */
2085 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2086 native_read_tsc() - vcpu->arch.last_host_tsc;
2087 if (tsc_delta < 0)
2088 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2089 if (check_tsc_unstable()) {
e48672fa 2090 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
c285545f
ZA		 2091 vcpu->arch.tsc_catchup = 1;
2092 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2093 }
2094 if (vcpu->cpu != cpu)
2095 kvm_migrate_timers(vcpu);
e48672fa 2096 vcpu->cpu = cpu;
6b7d7e76 2097 }
313a3dc7
CO		 2098}
2099
2100void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2101{
02daab21 2102 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2103 kvm_put_guest_fpu(vcpu);
e48672fa 2104 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2105}
2106
07716717 2107static int is_efer_nx(void)
313a3dc7 2108{
e286e86e 2109 unsigned long long efer = 0;
313a3dc7 2110
e286e86e 2111 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 2112 return efer & EFER_NX;
2113}
2114
2115static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2116{
2117 int i;
2118 struct kvm_cpuid_entry2 *e, *entry;
2119
313a3dc7 2120 entry = NULL;
ad312c7c
ZX		 2121 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2122 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 2123 if (e->function == 0x80000001) {
2124 entry = e;
2125 break;
2126 }
2127 }
07716717 2128 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 2129 entry->edx &= ~(1 << 20);
2130 printk(KERN_INFO "kvm: guest NX capability removed\n");
2131 }
2132}
2133
07716717 2134/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 2135static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2136 struct kvm_cpuid *cpuid,
2137 struct kvm_cpuid_entry __user *entries)
07716717
DK		 2138{
2139 int r, i;
2140 struct kvm_cpuid_entry *cpuid_entries;
2141
2142 r = -E2BIG;
2143 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2144 goto out;
2145 r = -ENOMEM;
2146 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2147 if (!cpuid_entries)
2148 goto out;
2149 r = -EFAULT;
2150 if (copy_from_user(cpuid_entries, entries,
2151 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2152 goto out_free;
2153 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 2154 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2155 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2156 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2157 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2158 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2159 vcpu->arch.cpuid_entries[i].index = 0;
2160 vcpu->arch.cpuid_entries[i].flags = 0;
2161 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2162 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2163 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2164 }
2165 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2166 cpuid_fix_nx_cap(vcpu);
2167 r = 0;
fc61b800 2168 kvm_apic_set_version(vcpu);
0e851880 2169 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2170 update_cpuid(vcpu);
07716717
DK		 2171
2172out_free:
2173 vfree(cpuid_entries);
2174out:
2175 return r;
2176}
2177
2178static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2179 struct kvm_cpuid2 *cpuid,
2180 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2181{
2182 int r;
2183
2184 r = -E2BIG;
2185 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2186 goto out;
2187 r = -EFAULT;
ad312c7c 2188 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2189 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2190 goto out;
ad312c7c 2191 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2192 kvm_apic_set_version(vcpu);
0e851880 2193 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2194 update_cpuid(vcpu);
313a3dc7
CO		 2195 return 0;
2196
2197out:
2198 return r;
2199}
2200
07716717 2201static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2202 struct kvm_cpuid2 *cpuid,
2203 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2204{
2205 int r;
2206
2207 r = -E2BIG;
ad312c7c 2208 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2209 goto out;
2210 r = -EFAULT;
ad312c7c 2211 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2212 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2213 goto out;
2214 return 0;
2215
2216out:
ad312c7c 2217 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2218 return r;
2219}
2220
945ee35e
AK		 2221static void cpuid_mask(u32 *word, int wordnum)
2222{
2223 *word &= boot_cpu_data.x86_capability[wordnum];
2224}
2225
07716717 2226static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2227 u32 index)
07716717
DK		 2228{
2229 entry->function = function;
2230 entry->index = index;
2231 cpuid_count(entry->function, entry->index,
19355475 2232 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2233 entry->flags = 0;
2234}
2235
7faa4ee1
AK		 2236#define F(x) bit(X86_FEATURE_##x)
2237
07716717
DK		 2238static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2239 u32 index, int *nent, int maxnent)
2240{
7faa4ee1 2241 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2242#ifdef CONFIG_X86_64
17cc3935
SY		 2243 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2244 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2245 unsigned f_lm = F(LM);
2246#else
17cc3935 2247 unsigned f_gbpages = 0;
7faa4ee1 2248 unsigned f_lm = 0;
07716717 2249#endif
4e47c7a6 2250 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2251
2252 /* cpuid 1.edx */
2253 const u32 kvm_supported_word0_x86_features =
2254 F(FPU) | F(VME) | F(DE) | F(PSE) |
2255 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2256 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2257 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2258 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2259 0 /* Reserved, DS, ACPI */ | F(MMX) |
2260 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2261 0 /* HTT, TM, Reserved, PBE */;
2262 /* cpuid 0x80000001.edx */
2263 const u32 kvm_supported_word1_x86_features =
2264 F(FPU) | F(VME) | F(DE) | F(PSE) |
2265 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2266 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2267 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2268 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2269 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2270 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2271 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2272 /* cpuid 1.ecx */
2273 const u32 kvm_supported_word4_x86_features =
6c3f6041 2274 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2275 0 /* DS-CPL, VMX, SMX, EST */ |
2276 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2277 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2278 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2279 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6d886fd0
AP		 2280 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
2281 F(F16C);
7faa4ee1 2282 /* cpuid 0x80000001.ecx */
07716717 2283 const u32 kvm_supported_word6_x86_features =
4c62a2dc 2284 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
7faa4ee1 2285 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
7ef8aa72 2286 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) |
6d886fd0 2287 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM);
07716717 2288
19355475 2289 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2290 get_cpu();
2291 do_cpuid_1_ent(entry, function, index);
2292 ++*nent;
2293
2294 switch (function) {
2295 case 0:
2acf923e 2296 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2297 break;
2298 case 1:
2299 entry->edx &= kvm_supported_word0_x86_features;
945ee35e 2300 cpuid_mask(&entry->edx, 0);
7faa4ee1 2301 entry->ecx &= kvm_supported_word4_x86_features;
945ee35e 2302 cpuid_mask(&entry->ecx, 4);
0d1de2d9
GN		 2303 /* we support x2apic emulation even if host does not support
2304 * it since we emulate x2apic in software */
2305 entry->ecx |= F(X2APIC);
07716717
DK		 2306 break;
2307 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2308 * may return different values. This forces us to get_cpu() before
2309 * issuing the first command, and also to emulate this annoying behavior
2310 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2311 case 2: {
2312 int t, times = entry->eax & 0xff;
2313
2314 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2315 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2316 for (t = 1; t < times && *nent < maxnent; ++t) {
2317 do_cpuid_1_ent(&entry[t], function, 0);
2318 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2319 ++*nent;
2320 }
2321 break;
2322 }
2323 /* function 4 and 0xb have additional index. */
2324 case 4: {
14af3f3c 2325 int i, cache_type;
07716717
DK		 2326
2327 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2328 /* read more entries until cache_type is zero */
14af3f3c
HH		 2329 for (i = 1; *nent < maxnent; ++i) {
2330 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2331 if (!cache_type)
2332 break;
14af3f3c
HH		 2333 do_cpuid_1_ent(&entry[i], function, i);
2334 entry[i].flags |=
07716717
DK		 2335 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2336 ++*nent;
2337 }
2338 break;
2339 }
2340 case 0xb: {
14af3f3c 2341 int i, level_type;
07716717
DK		 2342
2343 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2344 /* read more entries until level_type is zero */
14af3f3c 2345 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2346 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2347 if (!level_type)
2348 break;
14af3f3c
HH		 2349 do_cpuid_1_ent(&entry[i], function, i);
2350 entry[i].flags |=
07716717
DK		 2351 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2352 ++*nent;
2353 }
2354 break;
2355 }
2acf923e
DC		 2356 case 0xd: {
2357 int i;
2358
2359 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2360 for (i = 1; *nent < maxnent; ++i) {
2361 if (entry[i - 1].eax == 0 && i != 2)
2362 break;
2363 do_cpuid_1_ent(&entry[i], function, i);
2364 entry[i].flags |=
2365 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2366 ++*nent;
2367 }
2368 break;
2369 }
84478c82
GC		 2370 case KVM_CPUID_SIGNATURE: {
2371 char signature[12] = "KVMKVMKVM\0\0";
2372 u32 *sigptr = (u32 *)signature;
2373 entry->eax = 0;
2374 entry->ebx = sigptr[0];
2375 entry->ecx = sigptr[1];
2376 entry->edx = sigptr[2];
2377 break;
2378 }
2379 case KVM_CPUID_FEATURES:
2380 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2381 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64
GC		 2382 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2383 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2384 entry->ebx = 0;
2385 entry->ecx = 0;
2386 entry->edx = 0;
2387 break;
07716717
DK		 2388 case 0x80000000:
2389 entry->eax = min(entry->eax, 0x8000001a);
2390 break;
2391 case 0x80000001:
2392 entry->edx &= kvm_supported_word1_x86_features;
945ee35e 2393 cpuid_mask(&entry->edx, 1);
07716717 2394 entry->ecx &= kvm_supported_word6_x86_features;
945ee35e 2395 cpuid_mask(&entry->ecx, 6);
07716717
DK		 2396 break;
2397 }
d4330ef2
JR		 2398
2399 kvm_x86_ops->set_supported_cpuid(function, entry);
2400
07716717
DK		 2401 put_cpu();
2402}
2403
7faa4ee1
AK		 2404#undef F
2405
674eea0f 2406static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2407 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2408{
2409 struct kvm_cpuid_entry2 *cpuid_entries;
2410 int limit, nent = 0, r = -E2BIG;
2411 u32 func;
2412
2413 if (cpuid->nent < 1)
2414 goto out;
6a544355
AK		 2415 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2416 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2417 r = -ENOMEM;
2418 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2419 if (!cpuid_entries)
2420 goto out;
2421
2422 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2423 limit = cpuid_entries[0].eax;
2424 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2425 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2426 &nent, cpuid->nent);
07716717
DK		 2427 r = -E2BIG;
2428 if (nent >= cpuid->nent)
2429 goto out_free;
2430
2431 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2432 limit = cpuid_entries[nent - 1].eax;
2433 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2434 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2435 &nent, cpuid->nent);
84478c82
GC		 2436
2437
2438
2439 r = -E2BIG;
2440 if (nent >= cpuid->nent)
2441 goto out_free;
2442
2443 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2444 cpuid->nent);
2445
2446 r = -E2BIG;
2447 if (nent >= cpuid->nent)
2448 goto out_free;
2449
2450 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2451 cpuid->nent);
2452
cb007648
MM		 2453 r = -E2BIG;
2454 if (nent >= cpuid->nent)
2455 goto out_free;
2456
07716717
DK		 2457 r = -EFAULT;
2458 if (copy_to_user(entries, cpuid_entries,
19355475 2459 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2460 goto out_free;
2461 cpuid->nent = nent;
2462 r = 0;
2463
2464out_free:
2465 vfree(cpuid_entries);
2466out:
2467 return r;
2468}
2469
313a3dc7
CO		 2470static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2471 struct kvm_lapic_state *s)
2472{
ad312c7c 2473 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2474
2475 return 0;
2476}
2477
2478static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2479 struct kvm_lapic_state *s)
2480{
ad312c7c 2481 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2482 kvm_apic_post_state_restore(vcpu);
cb142eb7 2483 update_cr8_intercept(vcpu);
313a3dc7
CO		 2484
2485 return 0;
2486}
2487
f77bc6a4
ZX		 2488static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2489 struct kvm_interrupt *irq)
2490{
2491 if (irq->irq < 0 || irq->irq >= 256)
2492 return -EINVAL;
2493 if (irqchip_in_kernel(vcpu->kvm))
2494 return -ENXIO;
f77bc6a4 2495
66fd3f7f 2496 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2497 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2498
f77bc6a4
ZX		 2499 return 0;
2500}
2501
c4abb7c9
JK		 2502static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2503{
c4abb7c9 2504 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2505
2506 return 0;
2507}
2508
b209749f
AK		 2509static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2510 struct kvm_tpr_access_ctl *tac)
2511{
2512 if (tac->flags)
2513 return -EINVAL;
2514 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2515 return 0;
2516}
2517
890ca9ae
HY		 2518static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2519 u64 mcg_cap)
2520{
2521 int r;
2522 unsigned bank_num = mcg_cap & 0xff, bank;
2523
2524 r = -EINVAL;
a9e38c3e 2525 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2526 goto out;
2527 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2528 goto out;
2529 r = 0;
2530 vcpu->arch.mcg_cap = mcg_cap;
2531 /* Init IA32_MCG_CTL to all 1s */
2532 if (mcg_cap & MCG_CTL_P)
2533 vcpu->arch.mcg_ctl = ~(u64)0;
2534 /* Init IA32_MCi_CTL to all 1s */
2535 for (bank = 0; bank < bank_num; bank++)
2536 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2537out:
2538 return r;
2539}
2540
2541static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2542 struct kvm_x86_mce *mce)
2543{
2544 u64 mcg_cap = vcpu->arch.mcg_cap;
2545 unsigned bank_num = mcg_cap & 0xff;
2546 u64 *banks = vcpu->arch.mce_banks;
2547
2548 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2549 return -EINVAL;
2550 /*
2551 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2552 * reporting is disabled
2553 */
2554 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2555 vcpu->arch.mcg_ctl != ~(u64)0)
2556 return 0;
2557 banks += 4 * mce->bank;
2558 /*
2559 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2560 * reporting is disabled for the bank
2561 */
2562 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2563 return 0;
2564 if (mce->status & MCI_STATUS_UC) {
2565 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2566 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2567 printk(KERN_DEBUG "kvm: set_mce: "
2568 "injects mce exception while "
2569 "previous one is in progress!\n");
a8eeb04a 2570 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2571 return 0;
2572 }
2573 if (banks[1] & MCI_STATUS_VAL)
2574 mce->status |= MCI_STATUS_OVER;
2575 banks[2] = mce->addr;
2576 banks[3] = mce->misc;
2577 vcpu->arch.mcg_status = mce->mcg_status;
2578 banks[1] = mce->status;
2579 kvm_queue_exception(vcpu, MC_VECTOR);
2580 } else if (!(banks[1] & MCI_STATUS_VAL)
2581 || !(banks[1] & MCI_STATUS_UC)) {
2582 if (banks[1] & MCI_STATUS_VAL)
2583 mce->status |= MCI_STATUS_OVER;
2584 banks[2] = mce->addr;
2585 banks[3] = mce->misc;
2586 banks[1] = mce->status;
2587 } else
2588 banks[1] |= MCI_STATUS_OVER;
2589 return 0;
2590}
2591
3cfc3092
JK		 2592static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2593 struct kvm_vcpu_events *events)
2594{
03b82a30
JK		 2595 events->exception.injected =
2596 vcpu->arch.exception.pending &&
2597 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2598 events->exception.nr = vcpu->arch.exception.nr;
2599 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2600 events->exception.pad = 0;
3cfc3092
JK		 2601 events->exception.error_code = vcpu->arch.exception.error_code;
2602
03b82a30
JK		 2603 events->interrupt.injected =
2604 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2605 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2606 events->interrupt.soft = 0;
48005f64
JK		 2607 events->interrupt.shadow =
2608 kvm_x86_ops->get_interrupt_shadow(vcpu,
2609 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2610
2611 events->nmi.injected = vcpu->arch.nmi_injected;
2612 events->nmi.pending = vcpu->arch.nmi_pending;
2613 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2614 events->nmi.pad = 0;
3cfc3092
JK		 2615
2616 events->sipi_vector = vcpu->arch.sipi_vector;
2617
dab4b911 2618 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2619 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2620 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2621 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2622}
2623
2624static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2625 struct kvm_vcpu_events *events)
2626{
dab4b911 2627 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2628 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2629 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2630 return -EINVAL;
2631
3cfc3092
JK		 2632 vcpu->arch.exception.pending = events->exception.injected;
2633 vcpu->arch.exception.nr = events->exception.nr;
2634 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2635 vcpu->arch.exception.error_code = events->exception.error_code;
2636
2637 vcpu->arch.interrupt.pending = events->interrupt.injected;
2638 vcpu->arch.interrupt.nr = events->interrupt.nr;
2639 vcpu->arch.interrupt.soft = events->interrupt.soft;
2640 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2641 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2642 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2643 kvm_x86_ops->set_interrupt_shadow(vcpu,
2644 events->interrupt.shadow);
3cfc3092
JK		 2645
2646 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2647 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2648 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2649 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2650
dab4b911
JK		 2651 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2652 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2653
3842d135
AK		 2654 kvm_make_request(KVM_REQ_EVENT, vcpu);
2655
3cfc3092
JK		 2656 return 0;
2657}
2658
a1efbe77
JK		 2659static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2660 struct kvm_debugregs *dbgregs)
2661{
a1efbe77
JK		 2662 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2663 dbgregs->dr6 = vcpu->arch.dr6;
2664 dbgregs->dr7 = vcpu->arch.dr7;
2665 dbgregs->flags = 0;
97e69aa6 2666 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2667}
2668
2669static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2670 struct kvm_debugregs *dbgregs)
2671{
2672 if (dbgregs->flags)
2673 return -EINVAL;
2674
a1efbe77
JK		 2675 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2676 vcpu->arch.dr6 = dbgregs->dr6;
2677 vcpu->arch.dr7 = dbgregs->dr7;
2678
a1efbe77
JK		 2679 return 0;
2680}
2681
2d5b5a66
SY		 2682static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2683 struct kvm_xsave *guest_xsave)
2684{
2685 if (cpu_has_xsave)
2686 memcpy(guest_xsave->region,
2687 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2688 xstate_size);
2d5b5a66
SY		 2689 else {
2690 memcpy(guest_xsave->region,
2691 &vcpu->arch.guest_fpu.state->fxsave,
2692 sizeof(struct i387_fxsave_struct));
2693 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2694 XSTATE_FPSSE;
2695 }
2696}
2697
2698static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2699 struct kvm_xsave *guest_xsave)
2700{
2701 u64 xstate_bv =
2702 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2703
2704 if (cpu_has_xsave)
2705 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2706 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2707 else {
2708 if (xstate_bv & ~XSTATE_FPSSE)
2709 return -EINVAL;
2710 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2711 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2712 }
2713 return 0;
2714}
2715
2716static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2717 struct kvm_xcrs *guest_xcrs)
2718{
2719 if (!cpu_has_xsave) {
2720 guest_xcrs->nr_xcrs = 0;
2721 return;
2722 }
2723
2724 guest_xcrs->nr_xcrs = 1;
2725 guest_xcrs->flags = 0;
2726 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2727 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2728}
2729
2730static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2731 struct kvm_xcrs *guest_xcrs)
2732{
2733 int i, r = 0;
2734
2735 if (!cpu_has_xsave)
2736 return -EINVAL;
2737
2738 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2739 return -EINVAL;
2740
2741 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2742 /* Only support XCR0 currently */
2743 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2744 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2745 guest_xcrs->xcrs[0].value);
2746 break;
2747 }
2748 if (r)
2749 r = -EINVAL;
2750 return r;
2751}
2752
313a3dc7
CO		 2753long kvm_arch_vcpu_ioctl(struct file *filp,
2754 unsigned int ioctl, unsigned long arg)
2755{
2756 struct kvm_vcpu *vcpu = filp->private_data;
2757 void __user *argp = (void __user *)arg;
2758 int r;
d1ac91d8
AK		 2759 union {
2760 struct kvm_lapic_state *lapic;
2761 struct kvm_xsave *xsave;
2762 struct kvm_xcrs *xcrs;
2763 void *buffer;
2764 } u;
2765
2766 u.buffer = NULL;
313a3dc7
CO		 2767 switch (ioctl) {
2768 case KVM_GET_LAPIC: {
2204ae3c
MT		 2769 r = -EINVAL;
2770 if (!vcpu->arch.apic)
2771 goto out;
d1ac91d8 2772 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2773
b772ff36 2774 r = -ENOMEM;
d1ac91d8 2775 if (!u.lapic)
b772ff36 2776 goto out;
d1ac91d8 2777 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2778 if (r)
2779 goto out;
2780 r = -EFAULT;
d1ac91d8 2781 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2782 goto out;
2783 r = 0;
2784 break;
2785 }
2786 case KVM_SET_LAPIC: {
2204ae3c
MT		 2787 r = -EINVAL;
2788 if (!vcpu->arch.apic)
2789 goto out;
d1ac91d8 2790 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2791 r = -ENOMEM;
d1ac91d8 2792 if (!u.lapic)
b772ff36 2793 goto out;
313a3dc7 2794 r = -EFAULT;
d1ac91d8 2795 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2796 goto out;
d1ac91d8 2797 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2798 if (r)
2799 goto out;
2800 r = 0;
2801 break;
2802 }
f77bc6a4
ZX		 2803 case KVM_INTERRUPT: {
2804 struct kvm_interrupt irq;
2805
2806 r = -EFAULT;
2807 if (copy_from_user(&irq, argp, sizeof irq))
2808 goto out;
2809 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2810 if (r)
2811 goto out;
2812 r = 0;
2813 break;
2814 }
c4abb7c9
JK		 2815 case KVM_NMI: {
2816 r = kvm_vcpu_ioctl_nmi(vcpu);
2817 if (r)
2818 goto out;
2819 r = 0;
2820 break;
2821 }
313a3dc7
CO		 2822 case KVM_SET_CPUID: {
2823 struct kvm_cpuid __user *cpuid_arg = argp;
2824 struct kvm_cpuid cpuid;
2825
2826 r = -EFAULT;
2827 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2828 goto out;
2829 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2830 if (r)
2831 goto out;
2832 break;
2833 }
07716717
DK		 2834 case KVM_SET_CPUID2: {
2835 struct kvm_cpuid2 __user *cpuid_arg = argp;
2836 struct kvm_cpuid2 cpuid;
2837
2838 r = -EFAULT;
2839 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2840 goto out;
2841 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2842 cpuid_arg->entries);
07716717
DK		 2843 if (r)
2844 goto out;
2845 break;
2846 }
2847 case KVM_GET_CPUID2: {
2848 struct kvm_cpuid2 __user *cpuid_arg = argp;
2849 struct kvm_cpuid2 cpuid;
2850
2851 r = -EFAULT;
2852 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2853 goto out;
2854 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2855 cpuid_arg->entries);
07716717
DK		 2856 if (r)
2857 goto out;
2858 r = -EFAULT;
2859 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2860 goto out;
2861 r = 0;
2862 break;
2863 }
313a3dc7
CO		 2864 case KVM_GET_MSRS:
2865 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2866 break;
2867 case KVM_SET_MSRS:
2868 r = msr_io(vcpu, argp, do_set_msr, 0);
2869 break;
b209749f
AK		 2870 case KVM_TPR_ACCESS_REPORTING: {
2871 struct kvm_tpr_access_ctl tac;
2872
2873 r = -EFAULT;
2874 if (copy_from_user(&tac, argp, sizeof tac))
2875 goto out;
2876 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2877 if (r)
2878 goto out;
2879 r = -EFAULT;
2880 if (copy_to_user(argp, &tac, sizeof tac))
2881 goto out;
2882 r = 0;
2883 break;
2884 };
b93463aa
AK		 2885 case KVM_SET_VAPIC_ADDR: {
2886 struct kvm_vapic_addr va;
2887
2888 r = -EINVAL;
2889 if (!irqchip_in_kernel(vcpu->kvm))
2890 goto out;
2891 r = -EFAULT;
2892 if (copy_from_user(&va, argp, sizeof va))
2893 goto out;
2894 r = 0;
2895 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2896 break;
2897 }
890ca9ae
HY		 2898 case KVM_X86_SETUP_MCE: {
2899 u64 mcg_cap;
2900
2901 r = -EFAULT;
2902 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2903 goto out;
2904 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2905 break;
2906 }
2907 case KVM_X86_SET_MCE: {
2908 struct kvm_x86_mce mce;
2909
2910 r = -EFAULT;
2911 if (copy_from_user(&mce, argp, sizeof mce))
2912 goto out;
2913 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2914 break;
2915 }
3cfc3092
JK		 2916 case KVM_GET_VCPU_EVENTS: {
2917 struct kvm_vcpu_events events;
2918
2919 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2920
2921 r = -EFAULT;
2922 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2923 break;
2924 r = 0;
2925 break;
2926 }
2927 case KVM_SET_VCPU_EVENTS: {
2928 struct kvm_vcpu_events events;
2929
2930 r = -EFAULT;
2931 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2932 break;
2933
2934 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2935 break;
2936 }
a1efbe77
JK		 2937 case KVM_GET_DEBUGREGS: {
2938 struct kvm_debugregs dbgregs;
2939
2940 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2941
2942 r = -EFAULT;
2943 if (copy_to_user(argp, &dbgregs,
2944 sizeof(struct kvm_debugregs)))
2945 break;
2946 r = 0;
2947 break;
2948 }
2949 case KVM_SET_DEBUGREGS: {
2950 struct kvm_debugregs dbgregs;
2951
2952 r = -EFAULT;
2953 if (copy_from_user(&dbgregs, argp,
2954 sizeof(struct kvm_debugregs)))
2955 break;
2956
2957 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2958 break;
2959 }
2d5b5a66 2960 case KVM_GET_XSAVE: {
d1ac91d8 2961 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2962 r = -ENOMEM;
d1ac91d8 2963 if (!u.xsave)
2d5b5a66
SY		 2964 break;
2965
d1ac91d8 2966 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2967
2968 r = -EFAULT;
d1ac91d8 2969 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2970 break;
2971 r = 0;
2972 break;
2973 }
2974 case KVM_SET_XSAVE: {
d1ac91d8 2975 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2976 r = -ENOMEM;
d1ac91d8 2977 if (!u.xsave)
2d5b5a66
SY		 2978 break;
2979
2980 r = -EFAULT;
d1ac91d8 2981 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2982 break;
2983
d1ac91d8 2984 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2985 break;
2986 }
2987 case KVM_GET_XCRS: {
d1ac91d8 2988 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2989 r = -ENOMEM;
d1ac91d8 2990 if (!u.xcrs)
2d5b5a66
SY		 2991 break;
2992
d1ac91d8 2993 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2994
2995 r = -EFAULT;
d1ac91d8 2996 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2997 sizeof(struct kvm_xcrs)))
2998 break;
2999 r = 0;
3000 break;
3001 }
3002 case KVM_SET_XCRS: {
d1ac91d8 3003 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3004 r = -ENOMEM;
d1ac91d8 3005 if (!u.xcrs)
2d5b5a66
SY		 3006 break;
3007
3008 r = -EFAULT;
d1ac91d8 3009 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 3010 sizeof(struct kvm_xcrs)))
3011 break;
3012
d1ac91d8 3013 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3014 break;
3015 }
313a3dc7
CO		 3016 default:
3017 r = -EINVAL;
3018 }
3019out:
d1ac91d8 3020 kfree(u.buffer);
313a3dc7
CO		 3021 return r;
3022}
3023
1fe779f8
CO		 3024static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3025{
3026 int ret;
3027
3028 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3029 return -1;
3030 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3031 return ret;
3032}
3033
b927a3ce
SY		 3034static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3035 u64 ident_addr)
3036{
3037 kvm->arch.ept_identity_map_addr = ident_addr;
3038 return 0;
3039}
3040
1fe779f8
CO		 3041static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3042 u32 kvm_nr_mmu_pages)
3043{
3044 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3045 return -EINVAL;
3046
79fac95e 3047 mutex_lock(&kvm->slots_lock);
7c8a83b7 3048 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 3049
3050 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3051 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3052
7c8a83b7 3053 spin_unlock(&kvm->mmu_lock);
79fac95e 3054 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3055 return 0;
3056}
3057
3058static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3059{
39de71ec 3060 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3061}
3062
1fe779f8
CO		 3063static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3064{
3065 int r;
3066
3067 r = 0;
3068 switch (chip->chip_id) {
3069 case KVM_IRQCHIP_PIC_MASTER:
3070 memcpy(&chip->chip.pic,
3071 &pic_irqchip(kvm)->pics[0],
3072 sizeof(struct kvm_pic_state));
3073 break;
3074 case KVM_IRQCHIP_PIC_SLAVE:
3075 memcpy(&chip->chip.pic,
3076 &pic_irqchip(kvm)->pics[1],
3077 sizeof(struct kvm_pic_state));
3078 break;
3079 case KVM_IRQCHIP_IOAPIC:
eba0226b 3080 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3081 break;
3082 default:
3083 r = -EINVAL;
3084 break;
3085 }
3086 return r;
3087}
3088
3089static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3090{
3091 int r;
3092
3093 r = 0;
3094 switch (chip->chip_id) {
3095 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3096 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3097 memcpy(&pic_irqchip(kvm)->pics[0],
3098 &chip->chip.pic,
3099 sizeof(struct kvm_pic_state));
f4f51050 3100 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3101 break;
3102 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3103 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3104 memcpy(&pic_irqchip(kvm)->pics[1],
3105 &chip->chip.pic,
3106 sizeof(struct kvm_pic_state));
f4f51050 3107 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3108 break;
3109 case KVM_IRQCHIP_IOAPIC:
eba0226b 3110 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3111 break;
3112 default:
3113 r = -EINVAL;
3114 break;
3115 }
3116 kvm_pic_update_irq(pic_irqchip(kvm));
3117 return r;
3118}
3119
e0f63cb9
SY		 3120static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3121{
3122 int r = 0;
3123
894a9c55 3124 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3125 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3126 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3127 return r;
3128}
3129
3130static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3131{
3132 int r = 0;
3133
894a9c55 3134 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3135 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3136 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3137 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3138 return r;
3139}
3140
3141static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3142{
3143 int r = 0;
3144
3145 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3146 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3147 sizeof(ps->channels));
3148 ps->flags = kvm->arch.vpit->pit_state.flags;
3149 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3150 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3151 return r;
3152}
3153
3154static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3155{
3156 int r = 0, start = 0;
3157 u32 prev_legacy, cur_legacy;
3158 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3159 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3160 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3161 if (!prev_legacy && cur_legacy)
3162 start = 1;
3163 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3164 sizeof(kvm->arch.vpit->pit_state.channels));
3165 kvm->arch.vpit->pit_state.flags = ps->flags;
3166 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3167 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3168 return r;
3169}
3170
52d939a0
MT		 3171static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3172 struct kvm_reinject_control *control)
3173{
3174 if (!kvm->arch.vpit)
3175 return -ENXIO;
894a9c55 3176 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3177 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3178 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3179 return 0;
3180}
3181
5bb064dc
ZX		 3182/*
3183 * Get (and clear) the dirty memory log for a memory slot.
3184 */
3185int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3186 struct kvm_dirty_log *log)
3187{
87bf6e7d 3188 int r, i;
5bb064dc 3189 struct kvm_memory_slot *memslot;
87bf6e7d 3190 unsigned long n;
b050b015 3191 unsigned long is_dirty = 0;
5bb064dc 3192
79fac95e 3193 mutex_lock(&kvm->slots_lock);
5bb064dc 3194
b050b015
MT		 3195 r = -EINVAL;
3196 if (log->slot >= KVM_MEMORY_SLOTS)
3197 goto out;
3198
3199 memslot = &kvm->memslots->memslots[log->slot];
3200 r = -ENOENT;
3201 if (!memslot->dirty_bitmap)
3202 goto out;
3203
87bf6e7d 3204 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3205
b050b015
MT		 3206 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3207 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3208
3209 /* If nothing is dirty, don't bother messing with page tables. */
3210 if (is_dirty) {
b050b015 3211 struct kvm_memslots *slots, *old_slots;
914ebccd 3212 unsigned long *dirty_bitmap;
b050b015 3213
515a0127
TY		 3214 dirty_bitmap = memslot->dirty_bitmap_head;
3215 if (memslot->dirty_bitmap == dirty_bitmap)
3216 dirty_bitmap += n / sizeof(long);
914ebccd 3217 memset(dirty_bitmap, 0, n);
b050b015 3218
914ebccd
TY		 3219 r = -ENOMEM;
3220 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
515a0127 3221 if (!slots)
914ebccd 3222 goto out;
b050b015
MT		 3223 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3224 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
49c7754c 3225 slots->generation++;
b050b015
MT		 3226
3227 old_slots = kvm->memslots;
3228 rcu_assign_pointer(kvm->memslots, slots);
3229 synchronize_srcu_expedited(&kvm->srcu);
3230 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3231 kfree(old_slots);
914ebccd 3232
edde99ce
MT		 3233 spin_lock(&kvm->mmu_lock);
3234 kvm_mmu_slot_remove_write_access(kvm, log->slot);
3235 spin_unlock(&kvm->mmu_lock);
3236
914ebccd 3237 r = -EFAULT;
515a0127 3238 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
914ebccd 3239 goto out;
914ebccd
TY		 3240 } else {
3241 r = -EFAULT;
3242 if (clear_user(log->dirty_bitmap, n))
3243 goto out;
5bb064dc 3244 }
b050b015 3245
5bb064dc
ZX		 3246 r = 0;
3247out:
79fac95e 3248 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3249 return r;
3250}
3251
1fe779f8
CO		 3252long kvm_arch_vm_ioctl(struct file *filp,
3253 unsigned int ioctl, unsigned long arg)
3254{
3255 struct kvm *kvm = filp->private_data;
3256 void __user *argp = (void __user *)arg;
367e1319 3257 int r = -ENOTTY;
f0d66275
DH		 3258 /*
3259 * This union makes it completely explicit to gcc-3.x
3260 * that these two variables' stack usage should be
3261 * combined, not added together.
3262 */
3263 union {
3264 struct kvm_pit_state ps;
e9f42757 3265 struct kvm_pit_state2 ps2;
c5ff41ce 3266 struct kvm_pit_config pit_config;
f0d66275 3267 } u;
1fe779f8
CO		 3268
3269 switch (ioctl) {
3270 case KVM_SET_TSS_ADDR:
3271 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3272 if (r < 0)
3273 goto out;
3274 break;
b927a3ce
SY		 3275 case KVM_SET_IDENTITY_MAP_ADDR: {
3276 u64 ident_addr;
3277
3278 r = -EFAULT;
3279 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3280 goto out;
3281 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3282 if (r < 0)
3283 goto out;
3284 break;
3285 }
1fe779f8
CO		 3286 case KVM_SET_NR_MMU_PAGES:
3287 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3288 if (r)
3289 goto out;
3290 break;
3291 case KVM_GET_NR_MMU_PAGES:
3292 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3293 break;
3ddea128
MT		 3294 case KVM_CREATE_IRQCHIP: {
3295 struct kvm_pic *vpic;
3296
3297 mutex_lock(&kvm->lock);
3298 r = -EEXIST;
3299 if (kvm->arch.vpic)
3300 goto create_irqchip_unlock;
1fe779f8 3301 r = -ENOMEM;
3ddea128
MT		 3302 vpic = kvm_create_pic(kvm);
3303 if (vpic) {
1fe779f8
CO		 3304 r = kvm_ioapic_init(kvm);
3305 if (r) {
175504cd 3306 mutex_lock(&kvm->slots_lock);
72bb2fcd
WY		 3307 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3308 &vpic->dev);
175504cd 3309 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3310 kfree(vpic);
3311 goto create_irqchip_unlock;
1fe779f8
CO		 3312 }
3313 } else
3ddea128
MT		 3314 goto create_irqchip_unlock;
3315 smp_wmb();
3316 kvm->arch.vpic = vpic;
3317 smp_wmb();
399ec807
AK		 3318 r = kvm_setup_default_irq_routing(kvm);
3319 if (r) {
175504cd 3320 mutex_lock(&kvm->slots_lock);
3ddea128 3321 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3322 kvm_ioapic_destroy(kvm);
3323 kvm_destroy_pic(kvm);
3ddea128 3324 mutex_unlock(&kvm->irq_lock);
175504cd 3325 mutex_unlock(&kvm->slots_lock);
399ec807 3326 }
3ddea128
MT		 3327 create_irqchip_unlock:
3328 mutex_unlock(&kvm->lock);
1fe779f8 3329 break;
3ddea128 3330 }
7837699f 3331 case KVM_CREATE_PIT:
c5ff41ce
JK		 3332 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3333 goto create_pit;
3334 case KVM_CREATE_PIT2:
3335 r = -EFAULT;
3336 if (copy_from_user(&u.pit_config, argp,
3337 sizeof(struct kvm_pit_config)))
3338 goto out;
3339 create_pit:
79fac95e 3340 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3341 r = -EEXIST;
3342 if (kvm->arch.vpit)
3343 goto create_pit_unlock;
7837699f 3344 r = -ENOMEM;
c5ff41ce 3345 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3346 if (kvm->arch.vpit)
3347 r = 0;
269e05e4 3348 create_pit_unlock:
79fac95e 3349 mutex_unlock(&kvm->slots_lock);
7837699f 3350 break;
4925663a 3351 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3352 case KVM_IRQ_LINE: {
3353 struct kvm_irq_level irq_event;
3354
3355 r = -EFAULT;
3356 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3357 goto out;
160d2f6c 3358 r = -ENXIO;
1fe779f8 3359 if (irqchip_in_kernel(kvm)) {
4925663a 3360 __s32 status;
4925663a
GN		 3361 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3362 irq_event.irq, irq_event.level);
4925663a 3363 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3364 r = -EFAULT;
4925663a
GN		 3365 irq_event.status = status;
3366 if (copy_to_user(argp, &irq_event,
3367 sizeof irq_event))
3368 goto out;
3369 }
1fe779f8
CO		 3370 r = 0;
3371 }
3372 break;
3373 }
3374 case KVM_GET_IRQCHIP: {
3375 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3376 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3377
f0d66275
DH		 3378 r = -ENOMEM;
3379 if (!chip)
1fe779f8 3380 goto out;
f0d66275
DH		 3381 r = -EFAULT;
3382 if (copy_from_user(chip, argp, sizeof *chip))
3383 goto get_irqchip_out;
1fe779f8
CO		 3384 r = -ENXIO;
3385 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3386 goto get_irqchip_out;
3387 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3388 if (r)
f0d66275 3389 goto get_irqchip_out;
1fe779f8 3390 r = -EFAULT;
f0d66275
DH		 3391 if (copy_to_user(argp, chip, sizeof *chip))
3392 goto get_irqchip_out;
1fe779f8 3393 r = 0;
f0d66275
DH		 3394 get_irqchip_out:
3395 kfree(chip);
3396 if (r)
3397 goto out;
1fe779f8
CO		 3398 break;
3399 }
3400 case KVM_SET_IRQCHIP: {
3401 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3402 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3403
f0d66275
DH		 3404 r = -ENOMEM;
3405 if (!chip)
1fe779f8 3406 goto out;
f0d66275
DH		 3407 r = -EFAULT;
3408 if (copy_from_user(chip, argp, sizeof *chip))
3409 goto set_irqchip_out;
1fe779f8
CO		 3410 r = -ENXIO;
3411 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3412 goto set_irqchip_out;
3413 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3414 if (r)
f0d66275 3415 goto set_irqchip_out;
1fe779f8 3416 r = 0;
f0d66275
DH		 3417 set_irqchip_out:
3418 kfree(chip);
3419 if (r)
3420 goto out;
1fe779f8
CO		 3421 break;
3422 }
e0f63cb9 3423 case KVM_GET_PIT: {
e0f63cb9 3424 r = -EFAULT;
f0d66275 3425 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3426 goto out;
3427 r = -ENXIO;
3428 if (!kvm->arch.vpit)
3429 goto out;
f0d66275 3430 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3431 if (r)
3432 goto out;
3433 r = -EFAULT;
f0d66275 3434 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3435 goto out;
3436 r = 0;
3437 break;
3438 }
3439 case KVM_SET_PIT: {
e0f63cb9 3440 r = -EFAULT;
f0d66275 3441 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3442 goto out;
3443 r = -ENXIO;
3444 if (!kvm->arch.vpit)
3445 goto out;
f0d66275 3446 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3447 if (r)
3448 goto out;
3449 r = 0;
3450 break;
3451 }
e9f42757
BK		 3452 case KVM_GET_PIT2: {
3453 r = -ENXIO;
3454 if (!kvm->arch.vpit)
3455 goto out;
3456 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3457 if (r)
3458 goto out;
3459 r = -EFAULT;
3460 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3461 goto out;
3462 r = 0;
3463 break;
3464 }
3465 case KVM_SET_PIT2: {
3466 r = -EFAULT;
3467 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3468 goto out;
3469 r = -ENXIO;
3470 if (!kvm->arch.vpit)
3471 goto out;
3472 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3473 if (r)
3474 goto out;
3475 r = 0;
3476 break;
3477 }
52d939a0
MT		 3478 case KVM_REINJECT_CONTROL: {
3479 struct kvm_reinject_control control;
3480 r = -EFAULT;
3481 if (copy_from_user(&control, argp, sizeof(control)))
3482 goto out;
3483 r = kvm_vm_ioctl_reinject(kvm, &control);
3484 if (r)
3485 goto out;
3486 r = 0;
3487 break;
3488 }
ffde22ac
ES		 3489 case KVM_XEN_HVM_CONFIG: {
3490 r = -EFAULT;
3491 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3492 sizeof(struct kvm_xen_hvm_config)))
3493 goto out;
3494 r = -EINVAL;
3495 if (kvm->arch.xen_hvm_config.flags)
3496 goto out;
3497 r = 0;
3498 break;
3499 }
afbcf7ab 3500 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3501 struct kvm_clock_data user_ns;
3502 u64 now_ns;
3503 s64 delta;
3504
3505 r = -EFAULT;
3506 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3507 goto out;
3508
3509 r = -EINVAL;
3510 if (user_ns.flags)
3511 goto out;
3512
3513 r = 0;
395c6b0a 3514 local_irq_disable();
759379dd 3515 now_ns = get_kernel_ns();
afbcf7ab 3516 delta = user_ns.clock - now_ns;
395c6b0a 3517 local_irq_enable();
afbcf7ab
GC		 3518 kvm->arch.kvmclock_offset = delta;
3519 break;
3520 }
3521 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3522 struct kvm_clock_data user_ns;
3523 u64 now_ns;
3524
395c6b0a 3525 local_irq_disable();
759379dd 3526 now_ns = get_kernel_ns();
afbcf7ab 3527 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3528 local_irq_enable();
afbcf7ab 3529 user_ns.flags = 0;
97e69aa6 3530 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3531
3532 r = -EFAULT;
3533 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3534 goto out;
3535 r = 0;
3536 break;
3537 }
3538
1fe779f8
CO		 3539 default:
3540 ;
3541 }
3542out:
3543 return r;
3544}
3545
a16b043c 3546static void kvm_init_msr_list(void)
043405e1
CO		 3547{
3548 u32 dummy[2];
3549 unsigned i, j;
3550
e3267cbb
GC		 3551 /* skip the first msrs in the list. KVM-specific */
3552 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3553 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3554 continue;
3555 if (j < i)
3556 msrs_to_save[j] = msrs_to_save[i];
3557 j++;
3558 }
3559 num_msrs_to_save = j;
3560}
3561
bda9020e
MT		 3562static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3563 const void *v)
bbd9b64e 3564{
bda9020e
MT		 3565 if (vcpu->arch.apic &&
3566 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3567 return 0;
bbd9b64e 3568
e93f8a0f 3569 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3570}
3571
bda9020e 3572static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3573{
bda9020e
MT		 3574 if (vcpu->arch.apic &&
3575 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3576 return 0;
bbd9b64e 3577
e93f8a0f 3578 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3579}
3580
2dafc6c2
GN		 3581static void kvm_set_segment(struct kvm_vcpu *vcpu,
3582 struct kvm_segment *var, int seg)
3583{
3584 kvm_x86_ops->set_segment(vcpu, var, seg);
3585}
3586
3587void kvm_get_segment(struct kvm_vcpu *vcpu,
3588 struct kvm_segment *var, int seg)
3589{
3590 kvm_x86_ops->get_segment(vcpu, var, seg);
3591}
3592
c30a358d
JR		 3593static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3594{
3595 return gpa;
3596}
3597
02f59dc9
JR		 3598static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3599{
3600 gpa_t t_gpa;
ab9ae313 3601 struct x86_exception exception;
02f59dc9
JR		 3602
3603 BUG_ON(!mmu_is_nested(vcpu));
3604
3605 /* NPT walks are always user-walks */
3606 access |= PFERR_USER_MASK;
ab9ae313 3607 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3608
3609 return t_gpa;
3610}
3611
ab9ae313
AK		 3612gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3613 struct x86_exception *exception)
1871c602
GN		 3614{
3615 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3616 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3617}
3618
ab9ae313
AK		 3619 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3620 struct x86_exception *exception)
1871c602
GN		 3621{
3622 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3623 access |= PFERR_FETCH_MASK;
ab9ae313 3624 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3625}
3626
ab9ae313
AK		 3627gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3628 struct x86_exception *exception)
1871c602
GN		 3629{
3630 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3631 access |= PFERR_WRITE_MASK;
ab9ae313 3632 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3633}
3634
3635/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3636gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3637 struct x86_exception *exception)
bcc55cba 3638{
ab9ae313 3639 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
bcc55cba
AK		 3640}
3641
1871c602
GN		 3642static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3643 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3644 struct x86_exception *exception)
bbd9b64e
CO		 3645{
3646 void *data = val;
10589a46 3647 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3648
3649 while (bytes) {
14dfe855 3650 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3651 exception);
bbd9b64e 3652 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3653 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3654 int ret;
3655
bcc55cba 3656 if (gpa == UNMAPPED_GVA)
ab9ae313 3657 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3658 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3659 if (ret < 0) {
c3cd7ffa 3660 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3661 goto out;
3662 }
bbd9b64e 3663
77c2002e
IE		 3664 bytes -= toread;
3665 data += toread;
3666 addr += toread;
bbd9b64e 3667 }
10589a46 3668out:
10589a46 3669 return r;
bbd9b64e 3670}
77c2002e 3671
1871c602
GN		 3672/* used for instruction fetching */
3673static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
bcc55cba
AK		 3674 struct kvm_vcpu *vcpu,
3675 struct x86_exception *exception)
1871c602
GN		 3676{
3677 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3678 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3679 access | PFERR_FETCH_MASK,
3680 exception);
1871c602
GN		 3681}
3682
3683static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
bcc55cba
AK		 3684 struct kvm_vcpu *vcpu,
3685 struct x86_exception *exception)
1871c602
GN		 3686{
3687 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3688 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3689 exception);
1871c602
GN		 3690}
3691
3692static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
bcc55cba
AK		 3693 struct kvm_vcpu *vcpu,
3694 struct x86_exception *exception)
1871c602 3695{
bcc55cba 3696 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3697}
3698
7972995b 3699static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3700 unsigned int bytes,
7972995b 3701 struct kvm_vcpu *vcpu,
bcc55cba 3702 struct x86_exception *exception)
77c2002e
IE		 3703{
3704 void *data = val;
3705 int r = X86EMUL_CONTINUE;
3706
3707 while (bytes) {
14dfe855
JR		 3708 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3709 PFERR_WRITE_MASK,
ab9ae313 3710 exception);
77c2002e
IE		 3711 unsigned offset = addr & (PAGE_SIZE-1);
3712 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3713 int ret;
3714
bcc55cba 3715 if (gpa == UNMAPPED_GVA)
ab9ae313 3716 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3717 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3718 if (ret < 0) {
c3cd7ffa 3719 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3720 goto out;
3721 }
3722
3723 bytes -= towrite;
3724 data += towrite;
3725 addr += towrite;
3726 }
3727out:
3728 return r;
3729}
3730
bbd9b64e
CO		 3731static int emulator_read_emulated(unsigned long addr,
3732 void *val,
3733 unsigned int bytes,
bcc55cba 3734 struct x86_exception *exception,
bbd9b64e
CO		 3735 struct kvm_vcpu *vcpu)
3736{
bbd9b64e
CO		 3737 gpa_t gpa;
3738
3739 if (vcpu->mmio_read_completed) {
3740 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3741 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3742 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3743 vcpu->mmio_read_completed = 0;
3744 return X86EMUL_CONTINUE;
3745 }
3746
ab9ae313 3747 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, exception);
1871c602 3748
8fe681e9 3749 if (gpa == UNMAPPED_GVA)
ab9ae313 3750 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3751
3752 /* For APIC access vmexit */
3753 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3754 goto mmio;
3755
bcc55cba
AK		 3756 if (kvm_read_guest_virt(addr, val, bytes, vcpu, exception)
3757 == X86EMUL_CONTINUE)
bbd9b64e 3758 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3759
3760mmio:
3761 /*
3762 * Is this MMIO handled locally?
3763 */
aec51dc4
AK		 3764 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3765 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3766 return X86EMUL_CONTINUE;
3767 }
aec51dc4
AK		 3768
3769 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3770
3771 vcpu->mmio_needed = 1;
411c35b7
GN		 3772 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3773 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3774 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3775 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
bbd9b64e 3776
c3cd7ffa 3777 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3778}
3779
3200f405 3780int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 3781 const void *val, int bytes)
bbd9b64e
CO		 3782{
3783 int ret;
3784
3785 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3786 if (ret < 0)
bbd9b64e 3787 return 0;
ad218f85 3788 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3789 return 1;
3790}
3791
3792static int emulator_write_emulated_onepage(unsigned long addr,
3793 const void *val,
3794 unsigned int bytes,
bcc55cba 3795 struct x86_exception *exception,
bbd9b64e
CO		 3796 struct kvm_vcpu *vcpu)
3797{
10589a46
MT		 3798 gpa_t gpa;
3799
ab9ae313 3800 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, exception);
bbd9b64e 3801
8fe681e9 3802 if (gpa == UNMAPPED_GVA)
ab9ae313 3803 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3804
3805 /* For APIC access vmexit */
3806 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3807 goto mmio;
3808
3809 if (emulator_write_phys(vcpu, gpa, val, bytes))
3810 return X86EMUL_CONTINUE;
3811
3812mmio:
aec51dc4 3813 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3814 /*
3815 * Is this MMIO handled locally?
3816 */
bda9020e 3817 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3818 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3819
3820 vcpu->mmio_needed = 1;
411c35b7
GN		 3821 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3822 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3823 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3824 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
3825 memcpy(vcpu->run->mmio.data, val, bytes);
bbd9b64e
CO		 3826
3827 return X86EMUL_CONTINUE;
3828}
3829
3830int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3831 const void *val,
3832 unsigned int bytes,
bcc55cba 3833 struct x86_exception *exception,
8f6abd06 3834 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3835{
3836 /* Crossing a page boundary? */
3837 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3838 int rc, now;
3839
3840 now = -addr & ~PAGE_MASK;
bcc55cba 3841 rc = emulator_write_emulated_onepage(addr, val, now, exception,
8fe681e9 3842 vcpu);
bbd9b64e
CO		 3843 if (rc != X86EMUL_CONTINUE)
3844 return rc;
3845 addr += now;
3846 val += now;
3847 bytes -= now;
3848 }
bcc55cba 3849 return emulator_write_emulated_onepage(addr, val, bytes, exception,
8fe681e9 3850 vcpu);
bbd9b64e 3851}
bbd9b64e 3852
daea3e73
AK		 3853#define CMPXCHG_TYPE(t, ptr, old, new) \
3854 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3855
3856#ifdef CONFIG_X86_64
3857# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3858#else
3859# define CMPXCHG64(ptr, old, new) \
9749a6c0 3860 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3861#endif
3862
bbd9b64e
CO		 3863static int emulator_cmpxchg_emulated(unsigned long addr,
3864 const void *old,
3865 const void *new,
3866 unsigned int bytes,
bcc55cba 3867 struct x86_exception *exception,
bbd9b64e
CO		 3868 struct kvm_vcpu *vcpu)
3869{
daea3e73
AK		 3870 gpa_t gpa;
3871 struct page *page;
3872 char *kaddr;
3873 bool exchanged;
2bacc55c 3874
daea3e73
AK		 3875 /* guests cmpxchg8b have to be emulated atomically */
3876 if (bytes > 8 || (bytes & (bytes - 1)))
3877 goto emul_write;
10589a46 3878
daea3e73 3879 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3880
daea3e73
AK		 3881 if (gpa == UNMAPPED_GVA ||
3882 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3883 goto emul_write;
2bacc55c 3884
daea3e73
AK		 3885 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3886 goto emul_write;
72dc67a6 3887
daea3e73 3888 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3889 if (is_error_page(page)) {
3890 kvm_release_page_clean(page);
3891 goto emul_write;
3892 }
72dc67a6 3893
daea3e73
AK		 3894 kaddr = kmap_atomic(page, KM_USER0);
3895 kaddr += offset_in_page(gpa);
3896 switch (bytes) {
3897 case 1:
3898 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3899 break;
3900 case 2:
3901 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3902 break;
3903 case 4:
3904 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3905 break;
3906 case 8:
3907 exchanged = CMPXCHG64(kaddr, old, new);
3908 break;
3909 default:
3910 BUG();
2bacc55c 3911 }
daea3e73
AK		 3912 kunmap_atomic(kaddr, KM_USER0);
3913 kvm_release_page_dirty(page);
3914
3915 if (!exchanged)
3916 return X86EMUL_CMPXCHG_FAILED;
3917
8f6abd06
GN		 3918 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3919
3920 return X86EMUL_CONTINUE;
4a5f48f6 3921
3200f405 3922emul_write:
daea3e73 3923 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3924
bcc55cba 3925 return emulator_write_emulated(addr, new, bytes, exception, vcpu);
bbd9b64e
CO		 3926}
3927
cf8f70bf
GN		 3928static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3929{
3930 /* TODO: String I/O for in kernel device */
3931 int r;
3932
3933 if (vcpu->arch.pio.in)
3934 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3935 vcpu->arch.pio.size, pd);
3936 else
3937 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3938 vcpu->arch.pio.port, vcpu->arch.pio.size,
3939 pd);
3940 return r;
3941}
3942
3943
3944static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3945 unsigned int count, struct kvm_vcpu *vcpu)
3946{
7972995b 3947 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3948 goto data_avail;
3949
61cfab2e 3950 trace_kvm_pio(0, port, size, count);
cf8f70bf
GN		 3951
3952 vcpu->arch.pio.port = port;
3953 vcpu->arch.pio.in = 1;
7972995b 3954 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3955 vcpu->arch.pio.size = size;
3956
3957 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3958 data_avail:
3959 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3960 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3961 return 1;
3962 }
3963
3964 vcpu->run->exit_reason = KVM_EXIT_IO;
3965 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3966 vcpu->run->io.size = size;
3967 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3968 vcpu->run->io.count = count;
3969 vcpu->run->io.port = port;
3970
3971 return 0;
3972}
3973
3974static int emulator_pio_out_emulated(int size, unsigned short port,
3975 const void *val, unsigned int count,
3976 struct kvm_vcpu *vcpu)
3977{
61cfab2e 3978 trace_kvm_pio(1, port, size, count);
cf8f70bf
GN		 3979
3980 vcpu->arch.pio.port = port;
3981 vcpu->arch.pio.in = 0;
7972995b 3982 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3983 vcpu->arch.pio.size = size;
3984
3985 memcpy(vcpu->arch.pio_data, val, size * count);
3986
3987 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3988 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3989 return 1;
3990 }
3991
3992 vcpu->run->exit_reason = KVM_EXIT_IO;
3993 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3994 vcpu->run->io.size = size;
3995 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3996 vcpu->run->io.count = count;
3997 vcpu->run->io.port = port;
3998
3999 return 0;
4000}
4001
bbd9b64e
CO		 4002static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4003{
4004 return kvm_x86_ops->get_segment_base(vcpu, seg);
4005}
4006
4007int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
4008{
a7052897 4009 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 4010 return X86EMUL_CONTINUE;
4011}
4012
f5f48ee1
SY		 4013int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4014{
4015 if (!need_emulate_wbinvd(vcpu))
4016 return X86EMUL_CONTINUE;
4017
4018 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4019 int cpu = get_cpu();
4020
4021 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4022 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4023 wbinvd_ipi, NULL, 1);
2eec7343 4024 put_cpu();
f5f48ee1 4025 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4026 } else
4027 wbinvd();
f5f48ee1
SY		 4028 return X86EMUL_CONTINUE;
4029}
4030EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4031
bbd9b64e
CO		 4032int emulate_clts(struct kvm_vcpu *vcpu)
4033{
4d4ec087 4034 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 4035 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 4036 return X86EMUL_CONTINUE;
4037}
4038
35aa5375 4039int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
bbd9b64e 4040{
338dbc97 4041 return _kvm_get_dr(vcpu, dr, dest);
bbd9b64e
CO		 4042}
4043
35aa5375 4044int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
bbd9b64e 4045{
338dbc97
GN		 4046
4047 return __kvm_set_dr(vcpu, dr, value);
bbd9b64e
CO		 4048}
4049
52a46617 4050static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4051{
52a46617 4052 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4053}
4054
52a46617 4055static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 4056{
52a46617
GN		 4057 unsigned long value;
4058
4059 switch (cr) {
4060 case 0:
4061 value = kvm_read_cr0(vcpu);
4062 break;
4063 case 2:
4064 value = vcpu->arch.cr2;
4065 break;
4066 case 3:
4067 value = vcpu->arch.cr3;
4068 break;
4069 case 4:
4070 value = kvm_read_cr4(vcpu);
4071 break;
4072 case 8:
4073 value = kvm_get_cr8(vcpu);
4074 break;
4075 default:
4076 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4077 return 0;
4078 }
4079
4080 return value;
4081}
4082
0f12244f 4083static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
52a46617 4084{
0f12244f
GN		 4085 int res = 0;
4086
52a46617
GN		 4087 switch (cr) {
4088 case 0:
49a9b07e 4089 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4090 break;
4091 case 2:
4092 vcpu->arch.cr2 = val;
4093 break;
4094 case 3:
2390218b 4095 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4096 break;
4097 case 4:
a83b29c6 4098 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4099 break;
4100 case 8:
eea1cff9 4101 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4102 break;
4103 default:
4104 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4105 res = -1;
52a46617 4106 }
0f12244f
GN		 4107
4108 return res;
52a46617
GN		 4109}
4110
9c537244
GN		 4111static int emulator_get_cpl(struct kvm_vcpu *vcpu)
4112{
4113 return kvm_x86_ops->get_cpl(vcpu);
4114}
4115
2dafc6c2
GN		 4116static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4117{
4118 kvm_x86_ops->get_gdt(vcpu, dt);
4119}
4120
160ce1f1
MG		 4121static void emulator_get_idt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4122{
4123 kvm_x86_ops->get_idt(vcpu, dt);
4124}
4125
5951c442
GN		 4126static unsigned long emulator_get_cached_segment_base(int seg,
4127 struct kvm_vcpu *vcpu)
4128{
4129 return get_segment_base(vcpu, seg);
4130}
4131
2dafc6c2
GN		 4132static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
4133 struct kvm_vcpu *vcpu)
4134{
4135 struct kvm_segment var;
4136
4137 kvm_get_segment(vcpu, &var, seg);
4138
4139 if (var.unusable)
4140 return false;
4141
4142 if (var.g)
4143 var.limit >>= 12;
4144 set_desc_limit(desc, var.limit);
4145 set_desc_base(desc, (unsigned long)var.base);
4146 desc->type = var.type;
4147 desc->s = var.s;
4148 desc->dpl = var.dpl;
4149 desc->p = var.present;
4150 desc->avl = var.avl;
4151 desc->l = var.l;
4152 desc->d = var.db;
4153 desc->g = var.g;
4154
4155 return true;
4156}
4157
4158static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
4159 struct kvm_vcpu *vcpu)
4160{
4161 struct kvm_segment var;
4162
4163 /* needed to preserve selector */
4164 kvm_get_segment(vcpu, &var, seg);
4165
4166 var.base = get_desc_base(desc);
4167 var.limit = get_desc_limit(desc);
4168 if (desc->g)
4169 var.limit = (var.limit << 12) | 0xfff;
4170 var.type = desc->type;
4171 var.present = desc->p;
4172 var.dpl = desc->dpl;
4173 var.db = desc->d;
4174 var.s = desc->s;
4175 var.l = desc->l;
4176 var.g = desc->g;
4177 var.avl = desc->avl;
4178 var.present = desc->p;
4179 var.unusable = !var.present;
4180 var.padding = 0;
4181
4182 kvm_set_segment(vcpu, &var, seg);
4183 return;
4184}
4185
4186static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
4187{
4188 struct kvm_segment kvm_seg;
4189
4190 kvm_get_segment(vcpu, &kvm_seg, seg);
4191 return kvm_seg.selector;
4192}
4193
4194static void emulator_set_segment_selector(u16 sel, int seg,
4195 struct kvm_vcpu *vcpu)
4196{
4197 struct kvm_segment kvm_seg;
4198
4199 kvm_get_segment(vcpu, &kvm_seg, seg);
4200 kvm_seg.selector = sel;
4201 kvm_set_segment(vcpu, &kvm_seg, seg);
4202}
4203
14af3f3c 4204static struct x86_emulate_ops emulate_ops = {
1871c602 4205 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4206 .write_std = kvm_write_guest_virt_system,
1871c602 4207 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4208 .read_emulated = emulator_read_emulated,
4209 .write_emulated = emulator_write_emulated,
4210 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 4211 .pio_in_emulated = emulator_pio_in_emulated,
4212 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 4213 .get_cached_descriptor = emulator_get_cached_descriptor,
4214 .set_cached_descriptor = emulator_set_cached_descriptor,
4215 .get_segment_selector = emulator_get_segment_selector,
4216 .set_segment_selector = emulator_set_segment_selector,
5951c442 4217 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4218 .get_gdt = emulator_get_gdt,
160ce1f1 4219 .get_idt = emulator_get_idt,
52a46617
GN		 4220 .get_cr = emulator_get_cr,
4221 .set_cr = emulator_set_cr,
9c537244 4222 .cpl = emulator_get_cpl,
35aa5375
GN		 4223 .get_dr = emulator_get_dr,
4224 .set_dr = emulator_set_dr,
3fb1b5db
GN		 4225 .set_msr = kvm_set_msr,
4226 .get_msr = kvm_get_msr,
bbd9b64e
CO		 4227};
4228
5fdbf976
MT		 4229static void cache_all_regs(struct kvm_vcpu *vcpu)
4230{
4231 kvm_register_read(vcpu, VCPU_REGS_RAX);
4232 kvm_register_read(vcpu, VCPU_REGS_RSP);
4233 kvm_register_read(vcpu, VCPU_REGS_RIP);
4234 vcpu->arch.regs_dirty = ~0;
4235}
4236
95cb2295
GN		 4237static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4238{
4239 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4240 /*
4241 * an sti; sti; sequence only disable interrupts for the first
4242 * instruction. So, if the last instruction, be it emulated or
4243 * not, left the system with the INT_STI flag enabled, it
4244 * means that the last instruction is an sti. We should not
4245 * leave the flag on in this case. The same goes for mov ss
4246 */
4247 if (!(int_shadow & mask))
4248 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4249}
4250
54b8486f
GN		 4251static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4252{
4253 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4254 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4255 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4256 else if (ctxt->exception.error_code_valid)
4257 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4258 ctxt->exception.error_code);
54b8486f 4259 else
da9cb575 4260 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4261}
4262
8ec4722d
MG		 4263static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4264{
4265 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4266 int cs_db, cs_l;
4267
4268 cache_all_regs(vcpu);
4269
4270 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4271
4272 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4273 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4274 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4275 vcpu->arch.emulate_ctxt.mode =
4276 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4277 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4278 ? X86EMUL_MODE_VM86 : cs_l
4279 ? X86EMUL_MODE_PROT64 : cs_db
4280 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4281 memset(c, 0, sizeof(struct decode_cache));
4282 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4283}
4284
63995653
MG		 4285int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq)
4286{
4287 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4288 int ret;
4289
4290 init_emulate_ctxt(vcpu);
4291
4292 vcpu->arch.emulate_ctxt.decode.op_bytes = 2;
4293 vcpu->arch.emulate_ctxt.decode.ad_bytes = 2;
4294 vcpu->arch.emulate_ctxt.decode.eip = vcpu->arch.emulate_ctxt.eip;
4295 ret = emulate_int_real(&vcpu->arch.emulate_ctxt, &emulate_ops, irq);
4296
4297 if (ret != X86EMUL_CONTINUE)
4298 return EMULATE_FAIL;
4299
4300 vcpu->arch.emulate_ctxt.eip = c->eip;
4301 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4302 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4303 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4304
4305 if (irq == NMI_VECTOR)
4306 vcpu->arch.nmi_pending = false;
4307 else
4308 vcpu->arch.interrupt.pending = false;
4309
4310 return EMULATE_DONE;
4311}
4312EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4313
6d77dbfc
GN		 4314static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4315{
fc3a9157
JR		 4316 int r = EMULATE_DONE;
4317
6d77dbfc
GN		 4318 ++vcpu->stat.insn_emulation_fail;
4319 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4320 if (!is_guest_mode(vcpu)) {
4321 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4322 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4323 vcpu->run->internal.ndata = 0;
4324 r = EMULATE_FAIL;
4325 }
6d77dbfc 4326 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4327
4328 return r;
6d77dbfc
GN		 4329}
4330
a6f177ef
GN		 4331static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4332{
4333 gpa_t gpa;
4334
68be0803
GN		 4335 if (tdp_enabled)
4336 return false;
4337
a6f177ef
GN		 4338 /*
4339 * if emulation was due to access to shadowed page table
4340 * and it failed try to unshadow page and re-entetr the
4341 * guest to let CPU execute the instruction.
4342 */
4343 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4344 return true;
4345
4346 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4347
4348 if (gpa == UNMAPPED_GVA)
4349 return true; /* let cpu generate fault */
4350
4351 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4352 return true;
4353
4354 return false;
4355}
4356
bbd9b64e 4357int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 4358 unsigned long cr2,
4359 u16 error_code,
571008da 4360 int emulation_type)
bbd9b64e 4361{
95cb2295 4362 int r;
4d2179e1 4363 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
bbd9b64e 4364
26eef70c 4365 kvm_clear_exception_queue(vcpu);
ad312c7c 4366 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 4367 /*
56e82318 4368 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 4369 * instead of direct ->regs accesses, can save hundred cycles
4370 * on Intel for instructions that don't read/change RSP, for
4371 * for example.
4372 */
4373 cache_all_regs(vcpu);
bbd9b64e 4374
571008da 4375 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4376 init_emulate_ctxt(vcpu);
95cb2295 4377 vcpu->arch.emulate_ctxt.interruptibility = 0;
da9cb575 4378 vcpu->arch.emulate_ctxt.have_exception = false;
4fc40f07 4379 vcpu->arch.emulate_ctxt.perm_ok = false;
bbd9b64e 4380
9aabc88f 4381 r = x86_decode_insn(&vcpu->arch.emulate_ctxt);
d47f00a6
JR		 4382 if (r == X86EMUL_PROPAGATE_FAULT)
4383 goto done;
bbd9b64e 4384
e46479f8 4385 trace_kvm_emulate_insn_start(vcpu);
571008da 4386
0cb5762e
AP		 4387 /* Only allow emulation of specific instructions on #UD
4388 * (namely VMMCALL, sysenter, sysexit, syscall)*/
0cb5762e
AP		 4389 if (emulation_type & EMULTYPE_TRAP_UD) {
4390 if (!c->twobyte)
4391 return EMULATE_FAIL;
4392 switch (c->b) {
4393 case 0x01: /* VMMCALL */
4394 if (c->modrm_mod != 3 || c->modrm_rm != 1)
4395 return EMULATE_FAIL;
4396 break;
4397 case 0x34: /* sysenter */
4398 case 0x35: /* sysexit */
4399 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4400 return EMULATE_FAIL;
4401 break;
4402 case 0x05: /* syscall */
4403 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4404 return EMULATE_FAIL;
4405 break;
4406 default:
4407 return EMULATE_FAIL;
4408 }
4409
4410 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
4411 return EMULATE_FAIL;
4412 }
571008da 4413
f2b5756b 4414 ++vcpu->stat.insn_emulation;
bbd9b64e 4415 if (r) {
a6f177ef 4416 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4417 return EMULATE_DONE;
6d77dbfc
GN		 4418 if (emulation_type & EMULTYPE_SKIP)
4419 return EMULATE_FAIL;
4420 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4421 }
4422 }
4423
ba8afb6b
GN		 4424 if (emulation_type & EMULTYPE_SKIP) {
4425 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4426 return EMULATE_DONE;
4427 }
4428
4d2179e1
GN		 4429 /* this is needed for vmware backdor interface to work since it
4430 changes registers values during IO operation */
4431 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4432
5cd21917 4433restart:
9aabc88f 4434 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt);
bbd9b64e 4435
d2ddd1c4 4436 if (r == EMULATION_FAILED) {
a6f177ef 4437 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4438 return EMULATE_DONE;
4439
6d77dbfc 4440 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4441 }
4442
d47f00a6 4443done:
da9cb575 4444 if (vcpu->arch.emulate_ctxt.have_exception) {
54b8486f 4445 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4446 r = EMULATE_DONE;
4447 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4448 if (!vcpu->arch.pio.in)
4449 vcpu->arch.pio.count = 0;
e85d28f8
GN		 4450 r = EMULATE_DO_MMIO;
4451 } else if (vcpu->mmio_needed) {
3457e419
GN		 4452 if (vcpu->mmio_is_write)
4453 vcpu->mmio_needed = 0;
e85d28f8 4454 r = EMULATE_DO_MMIO;
d2ddd1c4 4455 } else if (r == EMULATION_RESTART)
5cd21917 4456 goto restart;
d2ddd1c4
GN		 4457 else
4458 r = EMULATE_DONE;
f850e2e6 4459
e85d28f8
GN		 4460 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
4461 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 4462 kvm_make_request(KVM_REQ_EVENT, vcpu);
e85d28f8
GN		 4463 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4464 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4465
4466 return r;
de7d789a 4467}
bbd9b64e 4468EXPORT_SYMBOL_GPL(emulate_instruction);
de7d789a 4469
cf8f70bf 4470int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4471{
cf8f70bf
GN		 4472 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4473 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
4474 /* do not return to emulator after return from userspace */
7972995b 4475 vcpu->arch.pio.count = 0;
de7d789a
CO		 4476 return ret;
4477}
cf8f70bf 4478EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4479
8cfdc000
ZA		 4480static void tsc_bad(void *info)
4481{
4482 __get_cpu_var(cpu_tsc_khz) = 0;
4483}
4484
4485static void tsc_khz_changed(void *data)
c8076604 4486{
8cfdc000
ZA		 4487 struct cpufreq_freqs *freq = data;
4488 unsigned long khz = 0;
4489
4490 if (data)
4491 khz = freq->new;
4492 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4493 khz = cpufreq_quick_get(raw_smp_processor_id());
4494 if (!khz)
4495 khz = tsc_khz;
4496 __get_cpu_var(cpu_tsc_khz) = khz;
c8076604
GH		 4497}
4498
c8076604
GH		 4499static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4500 void *data)
4501{
4502 struct cpufreq_freqs *freq = data;
4503 struct kvm *kvm;
4504 struct kvm_vcpu *vcpu;
4505 int i, send_ipi = 0;
4506
8cfdc000
ZA		 4507 /*
4508 * We allow guests to temporarily run on slowing clocks,
4509 * provided we notify them after, or to run on accelerating
4510 * clocks, provided we notify them before. Thus time never
4511 * goes backwards.
4512 *
4513 * However, we have a problem. We can't atomically update
4514 * the frequency of a given CPU from this function; it is
4515 * merely a notifier, which can be called from any CPU.
4516 * Changing the TSC frequency at arbitrary points in time
4517 * requires a recomputation of local variables related to
4518 * the TSC for each VCPU. We must flag these local variables
4519 * to be updated and be sure the update takes place with the
4520 * new frequency before any guests proceed.
4521 *
4522 * Unfortunately, the combination of hotplug CPU and frequency
4523 * change creates an intractable locking scenario; the order
4524 * of when these callouts happen is undefined with respect to
4525 * CPU hotplug, and they can race with each other. As such,
4526 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4527 * undefined; you can actually have a CPU frequency change take
4528 * place in between the computation of X and the setting of the
4529 * variable. To protect against this problem, all updates of
4530 * the per_cpu tsc_khz variable are done in an interrupt
4531 * protected IPI, and all callers wishing to update the value
4532 * must wait for a synchronous IPI to complete (which is trivial
4533 * if the caller is on the CPU already). This establishes the
4534 * necessary total order on variable updates.
4535 *
4536 * Note that because a guest time update may take place
4537 * anytime after the setting of the VCPU's request bit, the
4538 * correct TSC value must be set before the request. However,
4539 * to ensure the update actually makes it to any guest which
4540 * starts running in hardware virtualization between the set
4541 * and the acquisition of the spinlock, we must also ping the
4542 * CPU after setting the request bit.
4543 *
4544 */
4545
c8076604
GH		 4546 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4547 return 0;
4548 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4549 return 0;
8cfdc000
ZA		 4550
4551 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4552
4553 spin_lock(&kvm_lock);
4554 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4555 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4556 if (vcpu->cpu != freq->cpu)
4557 continue;
c285545f 4558 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4559 if (vcpu->cpu != smp_processor_id())
8cfdc000 4560 send_ipi = 1;
c8076604
GH		 4561 }
4562 }
4563 spin_unlock(&kvm_lock);
4564
4565 if (freq->old < freq->new && send_ipi) {
4566 /*
4567 * We upscale the frequency. Must make the guest
4568 * doesn't see old kvmclock values while running with
4569 * the new frequency, otherwise we risk the guest sees
4570 * time go backwards.
4571 *
4572 * In case we update the frequency for another cpu
4573 * (which might be in guest context) send an interrupt
4574 * to kick the cpu out of guest context. Next time
4575 * guest context is entered kvmclock will be updated,
4576 * so the guest will not see stale values.
4577 */
8cfdc000 4578 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4579 }
4580 return 0;
4581}
4582
4583static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4584 .notifier_call = kvmclock_cpufreq_notifier
4585};
4586
4587static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4588 unsigned long action, void *hcpu)
4589{
4590 unsigned int cpu = (unsigned long)hcpu;
4591
4592 switch (action) {
4593 case CPU_ONLINE:
4594 case CPU_DOWN_FAILED:
4595 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4596 break;
4597 case CPU_DOWN_PREPARE:
4598 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4599 break;
4600 }
4601 return NOTIFY_OK;
4602}
4603
4604static struct notifier_block kvmclock_cpu_notifier_block = {
4605 .notifier_call = kvmclock_cpu_notifier,
4606 .priority = -INT_MAX
c8076604
GH		 4607};
4608
b820cc0c
ZA		 4609static void kvm_timer_init(void)
4610{
4611 int cpu;
4612
c285545f 4613 max_tsc_khz = tsc_khz;
8cfdc000 4614 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4615 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4616#ifdef CONFIG_CPU_FREQ
4617 struct cpufreq_policy policy;
4618 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 4619 cpu = get_cpu();
4620 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 4621 if (policy.cpuinfo.max_freq)
4622 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 4623 put_cpu();
c285545f 4624#endif
b820cc0c
ZA		 4625 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4626 CPUFREQ_TRANSITION_NOTIFIER);
4627 }
c285545f 4628 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4629 for_each_online_cpu(cpu)
4630 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4631}
4632
ff9d07a0
ZY		 4633static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4634
4635static int kvm_is_in_guest(void)
4636{
4637 return percpu_read(current_vcpu) != NULL;
4638}
4639
4640static int kvm_is_user_mode(void)
4641{
4642 int user_mode = 3;
dcf46b94 4643
ff9d07a0
ZY		 4644 if (percpu_read(current_vcpu))
4645 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4646
ff9d07a0
ZY		 4647 return user_mode != 0;
4648}
4649
4650static unsigned long kvm_get_guest_ip(void)
4651{
4652 unsigned long ip = 0;
dcf46b94 4653
ff9d07a0
ZY		 4654 if (percpu_read(current_vcpu))
4655 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4656
ff9d07a0
ZY		 4657 return ip;
4658}
4659
4660static struct perf_guest_info_callbacks kvm_guest_cbs = {
4661 .is_in_guest = kvm_is_in_guest,
4662 .is_user_mode = kvm_is_user_mode,
4663 .get_guest_ip = kvm_get_guest_ip,
4664};
4665
4666void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4667{
4668 percpu_write(current_vcpu, vcpu);
4669}
4670EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4671
4672void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4673{
4674 percpu_write(current_vcpu, NULL);
4675}
4676EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4677
f8c16bba 4678int kvm_arch_init(void *opaque)
043405e1 4679{
b820cc0c 4680 int r;
f8c16bba
ZX		 4681 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4682
f8c16bba
ZX		 4683 if (kvm_x86_ops) {
4684 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4685 r = -EEXIST;
4686 goto out;
f8c16bba
ZX		 4687 }
4688
4689 if (!ops->cpu_has_kvm_support()) {
4690 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4691 r = -EOPNOTSUPP;
4692 goto out;
f8c16bba
ZX		 4693 }
4694 if (ops->disabled_by_bios()) {
4695 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4696 r = -EOPNOTSUPP;
4697 goto out;
f8c16bba
ZX		 4698 }
4699
97db56ce
AK		 4700 r = kvm_mmu_module_init();
4701 if (r)
4702 goto out;
4703
4704 kvm_init_msr_list();
4705
f8c16bba 4706 kvm_x86_ops = ops;
56c6d28a 4707 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e 4708 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4709 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4710
b820cc0c 4711 kvm_timer_init();
c8076604 4712
ff9d07a0
ZY		 4713 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4714
2acf923e
DC		 4715 if (cpu_has_xsave)
4716 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4717
f8c16bba 4718 return 0;
56c6d28a
ZX		 4719
4720out:
56c6d28a 4721 return r;
043405e1 4722}
8776e519 4723
f8c16bba
ZX		 4724void kvm_arch_exit(void)
4725{
ff9d07a0
ZY		 4726 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4727
888d256e
JK		 4728 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4729 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4730 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4731 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4732 kvm_x86_ops = NULL;
56c6d28a
ZX		 4733 kvm_mmu_module_exit();
4734}
f8c16bba 4735
8776e519
HB		 4736int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4737{
4738 ++vcpu->stat.halt_exits;
4739 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4740 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4741 return 1;
4742 } else {
4743 vcpu->run->exit_reason = KVM_EXIT_HLT;
4744 return 0;
4745 }
4746}
4747EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4748
2f333bcb
MT		 4749static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4750 unsigned long a1)
4751{
4752 if (is_long_mode(vcpu))
4753 return a0;
4754 else
4755 return a0 | ((gpa_t)a1 << 32);
4756}
4757
55cd8e5a
GN		 4758int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4759{
4760 u64 param, ingpa, outgpa, ret;
4761 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4762 bool fast, longmode;
4763 int cs_db, cs_l;
4764
4765 /*
4766 * hypercall generates UD from non zero cpl and real mode
4767 * per HYPER-V spec
4768 */
3eeb3288 4769 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4770 kvm_queue_exception(vcpu, UD_VECTOR);
4771 return 0;
4772 }
4773
4774 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4775 longmode = is_long_mode(vcpu) && cs_l == 1;
4776
4777 if (!longmode) {
ccd46936
GN		 4778 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4779 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4780 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4781 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4782 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4783 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4784 }
4785#ifdef CONFIG_X86_64
4786 else {
4787 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4788 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4789 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4790 }
4791#endif
4792
4793 code = param & 0xffff;
4794 fast = (param >> 16) & 0x1;
4795 rep_cnt = (param >> 32) & 0xfff;
4796 rep_idx = (param >> 48) & 0xfff;
4797
4798 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4799
c25bc163
GN		 4800 switch (code) {
4801 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4802 kvm_vcpu_on_spin(vcpu);
4803 break;
4804 default:
4805 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4806 break;
4807 }
55cd8e5a
GN		 4808
4809 ret = res | (((u64)rep_done & 0xfff) << 32);
4810 if (longmode) {
4811 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4812 } else {
4813 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4814 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4815 }
4816
4817 return 1;
4818}
4819
8776e519
HB		 4820int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4821{
4822 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4823 int r = 1;
8776e519 4824
55cd8e5a
GN		 4825 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4826 return kvm_hv_hypercall(vcpu);
4827
5fdbf976
MT		 4828 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4829 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4830 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4831 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4832 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4833
229456fc 4834 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4835
8776e519
HB		 4836 if (!is_long_mode(vcpu)) {
4837 nr &= 0xFFFFFFFF;
4838 a0 &= 0xFFFFFFFF;
4839 a1 &= 0xFFFFFFFF;
4840 a2 &= 0xFFFFFFFF;
4841 a3 &= 0xFFFFFFFF;
4842 }
4843
07708c4a
JK		 4844 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4845 ret = -KVM_EPERM;
4846 goto out;
4847 }
4848
8776e519 4849 switch (nr) {
b93463aa
AK		 4850 case KVM_HC_VAPIC_POLL_IRQ:
4851 ret = 0;
4852 break;
2f333bcb
MT		 4853 case KVM_HC_MMU_OP:
4854 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4855 break;
8776e519
HB		 4856 default:
4857 ret = -KVM_ENOSYS;
4858 break;
4859 }
07708c4a 4860out:
5fdbf976 4861 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4862 ++vcpu->stat.hypercalls;
2f333bcb 4863 return r;
8776e519
HB		 4864}
4865EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4866
4867int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4868{
4869 char instruction[3];
5fdbf976 4870 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4871
8776e519
HB		 4872 /*
4873 * Blow out the MMU to ensure that no other VCPU has an active mapping
4874 * to ensure that the updated hypercall appears atomically across all
4875 * VCPUs.
4876 */
4877 kvm_mmu_zap_all(vcpu->kvm);
4878
8776e519 4879 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4880
8fe681e9 4881 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
8776e519
HB		 4882}
4883
8776e519
HB		 4884void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4885{
89a27f4d 4886 struct desc_ptr dt = { limit, base };
8776e519
HB		 4887
4888 kvm_x86_ops->set_gdt(vcpu, &dt);
4889}
4890
4891void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4892{
89a27f4d 4893 struct desc_ptr dt = { limit, base };
8776e519
HB		 4894
4895 kvm_x86_ops->set_idt(vcpu, &dt);
4896}
4897
07716717
DK		 4898static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4899{
ad312c7c
ZX		 4900 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4901 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4902
4903 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4904 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4905 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4906 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4907 if (ej->function == e->function) {
4908 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4909 return j;
4910 }
4911 }
4912 return 0; /* silence gcc, even though control never reaches here */
4913}
4914
4915/* find an entry with matching function, matching index (if needed), and that
4916 * should be read next (if it's stateful) */
4917static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4918 u32 function, u32 index)
4919{
4920 if (e->function != function)
4921 return 0;
4922 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4923 return 0;
4924 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4925 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4926 return 0;
4927 return 1;
4928}
4929
d8017474
AG		 4930struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4931 u32 function, u32 index)
8776e519
HB		 4932{
4933 int i;
d8017474 4934 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4935
ad312c7c 4936 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4937 struct kvm_cpuid_entry2 *e;
4938
ad312c7c 4939 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4940 if (is_matching_cpuid_entry(e, function, index)) {
4941 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4942 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4943 best = e;
4944 break;
4945 }
4946 /*
4947 * Both basic or both extended?
4948 */
4949 if (((e->function ^ function) & 0x80000000) == 0)
4950 if (!best || e->function > best->function)
4951 best = e;
4952 }
d8017474
AG		 4953 return best;
4954}
0e851880 4955EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4956
82725b20
DE		 4957int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4958{
4959 struct kvm_cpuid_entry2 *best;
4960
f7a71197
AK		 4961 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4962 if (!best || best->eax < 0x80000008)
4963 goto not_found;
82725b20
DE		 4964 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4965 if (best)
4966 return best->eax & 0xff;
f7a71197 4967not_found:
82725b20
DE		 4968 return 36;
4969}
4970
d8017474
AG		 4971void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4972{
4973 u32 function, index;
4974 struct kvm_cpuid_entry2 *best;
4975
4976 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4977 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4978 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4979 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4980 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4981 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4982 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4983 if (best) {
5fdbf976
MT		 4984 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4985 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4986 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4987 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4988 }
8776e519 4989 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4990 trace_kvm_cpuid(function,
4991 kvm_register_read(vcpu, VCPU_REGS_RAX),
4992 kvm_register_read(vcpu, VCPU_REGS_RBX),
4993 kvm_register_read(vcpu, VCPU_REGS_RCX),
4994 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4995}
4996EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4997
b6c7a5dc
HB		 4998/*
4999 * Check if userspace requested an interrupt window, and that the
5000 * interrupt window is open.
5001 *
5002 * No need to exit to userspace if we already have an interrupt queued.
5003 */
851ba692 5004static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5005{
8061823a 5006 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5007 vcpu->run->request_interrupt_window &&
5df56646 5008 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5009}
5010
851ba692 5011static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5012{
851ba692
AK		 5013 struct kvm_run *kvm_run = vcpu->run;
5014
91586a3b 5015 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5016 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5017 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5018 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5019 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5020 else
b6c7a5dc 5021 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5022 kvm_arch_interrupt_allowed(vcpu) &&
5023 !kvm_cpu_has_interrupt(vcpu) &&
5024 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5025}
5026
b93463aa
AK		 5027static void vapic_enter(struct kvm_vcpu *vcpu)
5028{
5029 struct kvm_lapic *apic = vcpu->arch.apic;
5030 struct page *page;
5031
5032 if (!apic || !apic->vapic_addr)
5033 return;
5034
5035 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 5036
5037 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 5038}
5039
5040static void vapic_exit(struct kvm_vcpu *vcpu)
5041{
5042 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5043 int idx;
b93463aa
AK		 5044
5045 if (!apic || !apic->vapic_addr)
5046 return;
5047
f656ce01 5048 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5049 kvm_release_page_dirty(apic->vapic_page);
5050 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5051 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5052}
5053
95ba8273
GN		 5054static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5055{
5056 int max_irr, tpr;
5057
5058 if (!kvm_x86_ops->update_cr8_intercept)
5059 return;
5060
88c808fd
AK		 5061 if (!vcpu->arch.apic)
5062 return;
5063
8db3baa2
GN		 5064 if (!vcpu->arch.apic->vapic_addr)
5065 max_irr = kvm_lapic_find_highest_irr(vcpu);
5066 else
5067 max_irr = -1;
95ba8273
GN		 5068
5069 if (max_irr != -1)
5070 max_irr >>= 4;
5071
5072 tpr = kvm_lapic_get_cr8(vcpu);
5073
5074 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5075}
5076
851ba692 5077static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5078{
5079 /* try to reinject previous events if any */
b59bb7bd 5080 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5081 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5082 vcpu->arch.exception.has_error_code,
5083 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5084 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5085 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5086 vcpu->arch.exception.error_code,
5087 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5088 return;
5089 }
5090
95ba8273
GN		 5091 if (vcpu->arch.nmi_injected) {
5092 kvm_x86_ops->set_nmi(vcpu);
5093 return;
5094 }
5095
5096 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5097 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5098 return;
5099 }
5100
5101 /* try to inject new event if pending */
5102 if (vcpu->arch.nmi_pending) {
5103 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5104 vcpu->arch.nmi_pending = false;
5105 vcpu->arch.nmi_injected = true;
5106 kvm_x86_ops->set_nmi(vcpu);
5107 }
5108 } else if (kvm_cpu_has_interrupt(vcpu)) {
5109 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5110 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5111 false);
5112 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5113 }
5114 }
5115}
5116
2acf923e
DC		 5117static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5118{
5119 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5120 !vcpu->guest_xcr0_loaded) {
5121 /* kvm_set_xcr() also depends on this */
5122 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5123 vcpu->guest_xcr0_loaded = 1;
5124 }
5125}
5126
5127static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5128{
5129 if (vcpu->guest_xcr0_loaded) {
5130 if (vcpu->arch.xcr0 != host_xcr0)
5131 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5132 vcpu->guest_xcr0_loaded = 0;
5133 }
5134}
5135
851ba692 5136static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5137{
5138 int r;
6a8b1d13 5139 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5140 vcpu->run->request_interrupt_window;
b6c7a5dc 5141
3e007509 5142 if (vcpu->requests) {
a8eeb04a 5143 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5144 kvm_mmu_unload(vcpu);
a8eeb04a 5145 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5146 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5147 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5148 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5149 if (unlikely(r))
5150 goto out;
5151 }
a8eeb04a 5152 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5153 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5154 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5155 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5156 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5157 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5158 r = 0;
5159 goto out;
5160 }
a8eeb04a 5161 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5162 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5163 r = 0;
5164 goto out;
5165 }
a8eeb04a 5166 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5167 vcpu->fpu_active = 0;
5168 kvm_x86_ops->fpu_deactivate(vcpu);
5169 }
af585b92
GN		 5170 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5171 /* Page is swapped out. Do synthetic halt */
5172 vcpu->arch.apf.halted = true;
5173 r = 1;
5174 goto out;
5175 }
2f52d58c 5176 }
b93463aa 5177
3e007509
AK		 5178 r = kvm_mmu_reload(vcpu);
5179 if (unlikely(r))
5180 goto out;
5181
b463a6f7
AK		 5182 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5183 inject_pending_event(vcpu);
5184
5185 /* enable NMI/IRQ window open exits if needed */
5186 if (vcpu->arch.nmi_pending)
5187 kvm_x86_ops->enable_nmi_window(vcpu);
5188 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5189 kvm_x86_ops->enable_irq_window(vcpu);
5190
5191 if (kvm_lapic_enabled(vcpu)) {
5192 update_cr8_intercept(vcpu);
5193 kvm_lapic_sync_to_vapic(vcpu);
5194 }
5195 }
5196
b6c7a5dc
HB		 5197 preempt_disable();
5198
5199 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5200 if (vcpu->fpu_active)
5201 kvm_load_guest_fpu(vcpu);
2acf923e 5202 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5203
d94e1dc9
AK		 5204 atomic_set(&vcpu->guest_mode, 1);
5205 smp_wmb();
b6c7a5dc 5206
d94e1dc9 5207 local_irq_disable();
32f88400 5208
d94e1dc9
AK		 5209 if (!atomic_read(&vcpu->guest_mode) || vcpu->requests
5210 || need_resched() || signal_pending(current)) {
5211 atomic_set(&vcpu->guest_mode, 0);
5212 smp_wmb();
6c142801
AK		 5213 local_irq_enable();
5214 preempt_enable();
b463a6f7 5215 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5216 r = 1;
5217 goto out;
5218 }
5219
f656ce01 5220 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5221
b6c7a5dc
HB		 5222 kvm_guest_enter();
5223
42dbaa5a 5224 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5225 set_debugreg(0, 7);
5226 set_debugreg(vcpu->arch.eff_db[0], 0);
5227 set_debugreg(vcpu->arch.eff_db[1], 1);
5228 set_debugreg(vcpu->arch.eff_db[2], 2);
5229 set_debugreg(vcpu->arch.eff_db[3], 3);
5230 }
b6c7a5dc 5231
229456fc 5232 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5233 kvm_x86_ops->run(vcpu);
b6c7a5dc 5234
24f1e32c
FW		 5235 /*
5236 * If the guest has used debug registers, at least dr7
5237 * will be disabled while returning to the host.
5238 * If we don't have active breakpoints in the host, we don't
5239 * care about the messed up debug address registers. But if
5240 * we have some of them active, restore the old state.
5241 */
59d8eb53 5242 if (hw_breakpoint_active())
24f1e32c 5243 hw_breakpoint_restore();
42dbaa5a 5244
1d5f066e
ZA		 5245 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5246
d94e1dc9
AK		 5247 atomic_set(&vcpu->guest_mode, 0);
5248 smp_wmb();
b6c7a5dc
HB		 5249 local_irq_enable();
5250
5251 ++vcpu->stat.exits;
5252
5253 /*
5254 * We must have an instruction between local_irq_enable() and
5255 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5256 * the interrupt shadow. The stat.exits increment will do nicely.
5257 * But we need to prevent reordering, hence this barrier():
5258 */
5259 barrier();
5260
5261 kvm_guest_exit();
5262
5263 preempt_enable();
5264
f656ce01 5265 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5266
b6c7a5dc
HB		 5267 /*
5268 * Profile KVM exit RIPs:
5269 */
5270 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5271 unsigned long rip = kvm_rip_read(vcpu);
5272 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5273 }
5274
298101da 5275
b93463aa
AK		 5276 kvm_lapic_sync_from_vapic(vcpu);
5277
851ba692 5278 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5279out:
5280 return r;
5281}
b6c7a5dc 5282
09cec754 5283
851ba692 5284static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5285{
5286 int r;
f656ce01 5287 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5288
5289 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5290 pr_debug("vcpu %d received sipi with vector # %x\n",
5291 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5292 kvm_lapic_reset(vcpu);
5f179287 5293 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5294 if (r)
5295 return r;
5296 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5297 }
5298
f656ce01 5299 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5300 vapic_enter(vcpu);
5301
5302 r = 1;
5303 while (r > 0) {
af585b92
GN		 5304 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5305 !vcpu->arch.apf.halted)
851ba692 5306 r = vcpu_enter_guest(vcpu);
d7690175 5307 else {
f656ce01 5308 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5309 kvm_vcpu_block(vcpu);
f656ce01 5310 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5311 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5312 {
5313 switch(vcpu->arch.mp_state) {
5314 case KVM_MP_STATE_HALTED:
d7690175 5315 vcpu->arch.mp_state =
09cec754
GN		 5316 KVM_MP_STATE_RUNNABLE;
5317 case KVM_MP_STATE_RUNNABLE:
af585b92 5318 vcpu->arch.apf.halted = false;
09cec754
GN		 5319 break;
5320 case KVM_MP_STATE_SIPI_RECEIVED:
5321 default:
5322 r = -EINTR;
5323 break;
5324 }
5325 }
d7690175
MT		 5326 }
5327
09cec754
GN		 5328 if (r <= 0)
5329 break;
5330
5331 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5332 if (kvm_cpu_has_pending_timer(vcpu))
5333 kvm_inject_pending_timer_irqs(vcpu);
5334
851ba692 5335 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5336 r = -EINTR;
851ba692 5337 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5338 ++vcpu->stat.request_irq_exits;
5339 }
af585b92
GN		 5340
5341 kvm_check_async_pf_completion(vcpu);
5342
09cec754
GN		 5343 if (signal_pending(current)) {
5344 r = -EINTR;
851ba692 5345 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5346 ++vcpu->stat.signal_exits;
5347 }
5348 if (need_resched()) {
f656ce01 5349 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5350 kvm_resched(vcpu);
f656ce01 5351 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5352 }
b6c7a5dc
HB		 5353 }
5354
f656ce01 5355 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5356
b93463aa
AK		 5357 vapic_exit(vcpu);
5358
b6c7a5dc
HB		 5359 return r;
5360}
5361
5362int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5363{
5364 int r;
5365 sigset_t sigsaved;
5366
ac9f6dc0
AK		 5367 if (vcpu->sigset_active)
5368 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5369
a4535290 5370 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5371 kvm_vcpu_block(vcpu);
d7690175 5372 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5373 r = -EAGAIN;
5374 goto out;
b6c7a5dc
HB		 5375 }
5376
b6c7a5dc 5377 /* re-sync apic's tpr */
eea1cff9
AP		 5378 if (!irqchip_in_kernel(vcpu->kvm)) {
5379 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5380 r = -EINVAL;
5381 goto out;
5382 }
5383 }
b6c7a5dc 5384
d2ddd1c4 5385 if (vcpu->arch.pio.count || vcpu->mmio_needed) {
92bf9748
GN		 5386 if (vcpu->mmio_needed) {
5387 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
5388 vcpu->mmio_read_completed = 1;
5389 vcpu->mmio_needed = 0;
b6c7a5dc 5390 }
f656ce01 5391 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5cd21917 5392 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
f656ce01 5393 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6d77dbfc 5394 if (r != EMULATE_DONE) {
b6c7a5dc
HB		 5395 r = 0;
5396 goto out;
5397 }
5398 }
5fdbf976
MT		 5399 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5400 kvm_register_write(vcpu, VCPU_REGS_RAX,
5401 kvm_run->hypercall.ret);
b6c7a5dc 5402
851ba692 5403 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5404
5405out:
f1d86e46 5406 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5407 if (vcpu->sigset_active)
5408 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5409
b6c7a5dc
HB		 5410 return r;
5411}
5412
5413int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5414{
5fdbf976
MT		 5415 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5416 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5417 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5418 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5419 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5420 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5421 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5422 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5423#ifdef CONFIG_X86_64
5fdbf976
MT		 5424 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5425 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5426 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5427 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5428 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5429 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5430 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5431 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5432#endif
5433
5fdbf976 5434 regs->rip = kvm_rip_read(vcpu);
91586a3b 5435 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5436
b6c7a5dc
HB		 5437 return 0;
5438}
5439
5440int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5441{
5fdbf976
MT		 5442 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5443 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5444 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5445 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5446 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5447 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5448 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5449 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5450#ifdef CONFIG_X86_64
5fdbf976
MT		 5451 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5452 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5453 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5454 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5455 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5456 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5457 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5458 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5459#endif
5460
5fdbf976 5461 kvm_rip_write(vcpu, regs->rip);
91586a3b 5462 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5463
b4f14abd
JK		 5464 vcpu->arch.exception.pending = false;
5465
3842d135
AK		 5466 kvm_make_request(KVM_REQ_EVENT, vcpu);
5467
b6c7a5dc
HB		 5468 return 0;
5469}
5470
b6c7a5dc
HB		 5471void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5472{
5473 struct kvm_segment cs;
5474
3e6e0aab 5475 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5476 *db = cs.db;
5477 *l = cs.l;
5478}
5479EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5480
5481int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5482 struct kvm_sregs *sregs)
5483{
89a27f4d 5484 struct desc_ptr dt;
b6c7a5dc 5485
3e6e0aab
GT		 5486 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5487 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5488 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5489 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5490 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5491 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5492
3e6e0aab
GT		 5493 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5494 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5495
5496 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5497 sregs->idt.limit = dt.size;
5498 sregs->idt.base = dt.address;
b6c7a5dc 5499 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5500 sregs->gdt.limit = dt.size;
5501 sregs->gdt.base = dt.address;
b6c7a5dc 5502
4d4ec087 5503 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 5504 sregs->cr2 = vcpu->arch.cr2;
5505 sregs->cr3 = vcpu->arch.cr3;
fc78f519 5506 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5507 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5508 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5509 sregs->apic_base = kvm_get_apic_base(vcpu);
5510
923c61bb 5511 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5512
36752c9b 5513 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5514 set_bit(vcpu->arch.interrupt.nr,
5515 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5516
b6c7a5dc
HB		 5517 return 0;
5518}
5519
62d9f0db
MT		 5520int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5521 struct kvm_mp_state *mp_state)
5522{
62d9f0db 5523 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5524 return 0;
5525}
5526
5527int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5528 struct kvm_mp_state *mp_state)
5529{
62d9f0db 5530 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5531 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5532 return 0;
5533}
5534
e269fb21
JK		 5535int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5536 bool has_error_code, u32 error_code)
b6c7a5dc 5537{
4d2179e1 5538 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
8ec4722d 5539 int ret;
e01c2426 5540
8ec4722d 5541 init_emulate_ctxt(vcpu);
c697518a 5542
9aabc88f 5543 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt,
e269fb21
JK		 5544 tss_selector, reason, has_error_code,
5545 error_code);
c697518a 5546
c697518a 5547 if (ret)
19d04437 5548 return EMULATE_FAIL;
37817f29 5549
4d2179e1 5550 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 5551 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
19d04437 5552 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 5553 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5554 return EMULATE_DONE;
37817f29
IE		 5555}
5556EXPORT_SYMBOL_GPL(kvm_task_switch);
5557
b6c7a5dc
HB		 5558int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5559 struct kvm_sregs *sregs)
5560{
5561 int mmu_reset_needed = 0;
923c61bb 5562 int pending_vec, max_bits;
89a27f4d 5563 struct desc_ptr dt;
b6c7a5dc 5564
89a27f4d
GN		 5565 dt.size = sregs->idt.limit;
5566 dt.address = sregs->idt.base;
b6c7a5dc 5567 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5568 dt.size = sregs->gdt.limit;
5569 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5570 kvm_x86_ops->set_gdt(vcpu, &dt);
5571
ad312c7c
ZX		 5572 vcpu->arch.cr2 = sregs->cr2;
5573 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5574 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5575
2d3ad1f4 5576 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5577
f6801dff 5578 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5579 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5580 kvm_set_apic_base(vcpu, sregs->apic_base);
5581
4d4ec087 5582 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5583 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5584 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5585
fc78f519 5586 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5587 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c
SY		 5588 if (sregs->cr4 & X86_CR4_OSXSAVE)
5589 update_cpuid(vcpu);
7c93be44 5590 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ff03a073 5591 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
7c93be44
MT		 5592 mmu_reset_needed = 1;
5593 }
b6c7a5dc
HB		 5594
5595 if (mmu_reset_needed)
5596 kvm_mmu_reset_context(vcpu);
5597
923c61bb
GN		 5598 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5599 pending_vec = find_first_bit(
5600 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5601 if (pending_vec < max_bits) {
66fd3f7f 5602 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5603 pr_debug("Set back pending irq %d\n", pending_vec);
5604 if (irqchip_in_kernel(vcpu->kvm))
5605 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5606 }
5607
3e6e0aab
GT		 5608 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5609 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5610 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5611 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5612 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5613 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5614
3e6e0aab
GT		 5615 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5616 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5617
5f0269f5
ME		 5618 update_cr8_intercept(vcpu);
5619
9c3e4aab 5620 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5621 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5622 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5623 !is_protmode(vcpu))
9c3e4aab
MT		 5624 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5625
3842d135
AK		 5626 kvm_make_request(KVM_REQ_EVENT, vcpu);
5627
b6c7a5dc
HB		 5628 return 0;
5629}
5630
d0bfb940
JK		 5631int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5632 struct kvm_guest_debug *dbg)
b6c7a5dc 5633{
355be0b9 5634 unsigned long rflags;
ae675ef0 5635 int i, r;
b6c7a5dc 5636
4f926bf2
JK		 5637 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5638 r = -EBUSY;
5639 if (vcpu->arch.exception.pending)
2122ff5e 5640 goto out;
4f926bf2
JK		 5641 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5642 kvm_queue_exception(vcpu, DB_VECTOR);
5643 else
5644 kvm_queue_exception(vcpu, BP_VECTOR);
5645 }
5646
91586a3b
JK		 5647 /*
5648 * Read rflags as long as potentially injected trace flags are still
5649 * filtered out.
5650 */
5651 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5652
5653 vcpu->guest_debug = dbg->control;
5654 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5655 vcpu->guest_debug = 0;
5656
5657 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5658 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5659 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5660 vcpu->arch.switch_db_regs =
5661 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5662 } else {
5663 for (i = 0; i < KVM_NR_DB_REGS; i++)
5664 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5665 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5666 }
5667
f92653ee
JK		 5668 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5669 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5670 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5671
91586a3b
JK		 5672 /*
5673 * Trigger an rflags update that will inject or remove the trace
5674 * flags.
5675 */
5676 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5677
355be0b9 5678 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5679
4f926bf2 5680 r = 0;
d0bfb940 5681
2122ff5e 5682out:
b6c7a5dc
HB		 5683
5684 return r;
5685}
5686
8b006791
ZX		 5687/*
5688 * Translate a guest virtual address to a guest physical address.
5689 */
5690int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5691 struct kvm_translation *tr)
5692{
5693 unsigned long vaddr = tr->linear_address;
5694 gpa_t gpa;
f656ce01 5695 int idx;
8b006791 5696
f656ce01 5697 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5698 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5699 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5700 tr->physical_address = gpa;
5701 tr->valid = gpa != UNMAPPED_GVA;
5702 tr->writeable = 1;
5703 tr->usermode = 0;
8b006791
ZX		 5704
5705 return 0;
5706}
5707
d0752060
HB		 5708int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5709{
98918833
SY		 5710 struct i387_fxsave_struct *fxsave =
5711 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5712
d0752060
HB		 5713 memcpy(fpu->fpr, fxsave->st_space, 128);
5714 fpu->fcw = fxsave->cwd;
5715 fpu->fsw = fxsave->swd;
5716 fpu->ftwx = fxsave->twd;
5717 fpu->last_opcode = fxsave->fop;
5718 fpu->last_ip = fxsave->rip;
5719 fpu->last_dp = fxsave->rdp;
5720 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5721
d0752060
HB		 5722 return 0;
5723}
5724
5725int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5726{
98918833
SY		 5727 struct i387_fxsave_struct *fxsave =
5728 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5729
d0752060
HB		 5730 memcpy(fxsave->st_space, fpu->fpr, 128);
5731 fxsave->cwd = fpu->fcw;
5732 fxsave->swd = fpu->fsw;
5733 fxsave->twd = fpu->ftwx;
5734 fxsave->fop = fpu->last_opcode;
5735 fxsave->rip = fpu->last_ip;
5736 fxsave->rdp = fpu->last_dp;
5737 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5738
d0752060
HB		 5739 return 0;
5740}
5741
10ab25cd 5742int fx_init(struct kvm_vcpu *vcpu)
d0752060 5743{
10ab25cd
JK		 5744 int err;
5745
5746 err = fpu_alloc(&vcpu->arch.guest_fpu);
5747 if (err)
5748 return err;
5749
98918833 5750 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5751
2acf923e
DC		 5752 /*
5753 * Ensure guest xcr0 is valid for loading
5754 */
5755 vcpu->arch.xcr0 = XSTATE_FP;
5756
ad312c7c 5757 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5758
5759 return 0;
d0752060
HB		 5760}
5761EXPORT_SYMBOL_GPL(fx_init);
5762
98918833
SY		 5763static void fx_free(struct kvm_vcpu *vcpu)
5764{
5765 fpu_free(&vcpu->arch.guest_fpu);
5766}
5767
d0752060
HB		 5768void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5769{
2608d7a1 5770 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5771 return;
5772
2acf923e
DC		 5773 /*
5774 * Restore all possible states in the guest,
5775 * and assume host would use all available bits.
5776 * Guest xcr0 would be loaded later.
5777 */
5778 kvm_put_guest_xcr0(vcpu);
d0752060 5779 vcpu->guest_fpu_loaded = 1;
7cf30855 5780 unlazy_fpu(current);
98918833 5781 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5782 trace_kvm_fpu(1);
d0752060 5783}
d0752060
HB		 5784
5785void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5786{
2acf923e
DC		 5787 kvm_put_guest_xcr0(vcpu);
5788
d0752060
HB		 5789 if (!vcpu->guest_fpu_loaded)
5790 return;
5791
5792 vcpu->guest_fpu_loaded = 0;
98918833 5793 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5794 ++vcpu->stat.fpu_reload;
a8eeb04a 5795 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5796 trace_kvm_fpu(0);
d0752060 5797}
e9b11c17
ZX		 5798
5799void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5800{
7f1ea208
JR		 5801 if (vcpu->arch.time_page) {
5802 kvm_release_page_dirty(vcpu->arch.time_page);
5803 vcpu->arch.time_page = NULL;
5804 }
5805
f5f48ee1 5806 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5807 fx_free(vcpu);
e9b11c17
ZX		 5808 kvm_x86_ops->vcpu_free(vcpu);
5809}
5810
5811struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5812 unsigned int id)
5813{
6755bae8
ZA		 5814 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5815 printk_once(KERN_WARNING
5816 "kvm: SMP vm created on host with unstable TSC; "
5817 "guest TSC will not be reliable\n");
26e5215f
AK		 5818 return kvm_x86_ops->vcpu_create(kvm, id);
5819}
e9b11c17 5820
26e5215f
AK		 5821int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5822{
5823 int r;
e9b11c17 5824
0bed3b56 5825 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5826 vcpu_load(vcpu);
5827 r = kvm_arch_vcpu_reset(vcpu);
5828 if (r == 0)
5829 r = kvm_mmu_setup(vcpu);
5830 vcpu_put(vcpu);
5831 if (r < 0)
5832 goto free_vcpu;
5833
26e5215f 5834 return 0;
e9b11c17
ZX		 5835free_vcpu:
5836 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5837 return r;
e9b11c17
ZX		 5838}
5839
d40ccc62 5840void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 5841{
344d9588
GN		 5842 vcpu->arch.apf.msr_val = 0;
5843
e9b11c17
ZX		 5844 vcpu_load(vcpu);
5845 kvm_mmu_unload(vcpu);
5846 vcpu_put(vcpu);
5847
98918833 5848 fx_free(vcpu);
e9b11c17
ZX		 5849 kvm_x86_ops->vcpu_free(vcpu);
5850}
5851
5852int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5853{
448fa4a9
JK		 5854 vcpu->arch.nmi_pending = false;
5855 vcpu->arch.nmi_injected = false;
5856
42dbaa5a
JK		 5857 vcpu->arch.switch_db_regs = 0;
5858 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5859 vcpu->arch.dr6 = DR6_FIXED_1;
5860 vcpu->arch.dr7 = DR7_FIXED_1;
5861
3842d135 5862 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 5863 vcpu->arch.apf.msr_val = 0;
3842d135 5864
af585b92
GN		 5865 kvm_clear_async_pf_completion_queue(vcpu);
5866 kvm_async_pf_hash_reset(vcpu);
5867 vcpu->arch.apf.halted = false;
5868
e9b11c17
ZX		 5869 return kvm_x86_ops->vcpu_reset(vcpu);
5870}
5871
10474ae8 5872int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5873{
ca84d1a2
ZA		 5874 struct kvm *kvm;
5875 struct kvm_vcpu *vcpu;
5876 int i;
18863bdd
AK		 5877
5878 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 5879 list_for_each_entry(kvm, &vm_list, vm_list)
5880 kvm_for_each_vcpu(i, vcpu, kvm)
5881 if (vcpu->cpu == smp_processor_id())
c285545f 5882 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10474ae8 5883 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5884}
5885
5886void kvm_arch_hardware_disable(void *garbage)
5887{
5888 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5889 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5890}
5891
5892int kvm_arch_hardware_setup(void)
5893{
5894 return kvm_x86_ops->hardware_setup();
5895}
5896
5897void kvm_arch_hardware_unsetup(void)
5898{
5899 kvm_x86_ops->hardware_unsetup();
5900}
5901
5902void kvm_arch_check_processor_compat(void *rtn)
5903{
5904 kvm_x86_ops->check_processor_compatibility(rtn);
5905}
5906
5907int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5908{
5909 struct page *page;
5910 struct kvm *kvm;
5911 int r;
5912
5913 BUG_ON(vcpu->kvm == NULL);
5914 kvm = vcpu->kvm;
5915
9aabc88f 5916 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
14dfe855 5917 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
ad312c7c 5918 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c30a358d 5919 vcpu->arch.mmu.translate_gpa = translate_gpa;
02f59dc9 5920 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
c5af89b6 5921 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5922 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5923 else
a4535290 5924 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5925
5926 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5927 if (!page) {
5928 r = -ENOMEM;
5929 goto fail;
5930 }
ad312c7c 5931 vcpu->arch.pio_data = page_address(page);
e9b11c17 5932
c285545f
ZA		 5933 if (!kvm->arch.virtual_tsc_khz)
5934 kvm_arch_set_tsc_khz(kvm, max_tsc_khz);
5935
e9b11c17
ZX		 5936 r = kvm_mmu_create(vcpu);
5937 if (r < 0)
5938 goto fail_free_pio_data;
5939
5940 if (irqchip_in_kernel(kvm)) {
5941 r = kvm_create_lapic(vcpu);
5942 if (r < 0)
5943 goto fail_mmu_destroy;
5944 }
5945
890ca9ae
HY		 5946 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5947 GFP_KERNEL);
5948 if (!vcpu->arch.mce_banks) {
5949 r = -ENOMEM;
443c39bc 5950 goto fail_free_lapic;
890ca9ae
HY		 5951 }
5952 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5953
f5f48ee1
SY		 5954 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
5955 goto fail_free_mce_banks;
5956
af585b92
GN		 5957 kvm_async_pf_hash_reset(vcpu);
5958
e9b11c17 5959 return 0;
f5f48ee1
SY		 5960fail_free_mce_banks:
5961 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 5962fail_free_lapic:
5963 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5964fail_mmu_destroy:
5965 kvm_mmu_destroy(vcpu);
5966fail_free_pio_data:
ad312c7c 5967 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5968fail:
5969 return r;
5970}
5971
5972void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5973{
f656ce01
MT		 5974 int idx;
5975
36cb93fd 5976 kfree(vcpu->arch.mce_banks);
e9b11c17 5977 kvm_free_lapic(vcpu);
f656ce01 5978 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5979 kvm_mmu_destroy(vcpu);
f656ce01 5980 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5981 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5982}
d19a9cd2 5983
d89f5eff 5984int kvm_arch_init_vm(struct kvm *kvm)
d19a9cd2 5985{
f05e70ac 5986 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5987 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5988
5550af4d
SY		 5989 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5990 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5991
99e3e30a 5992 spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 5993
d89f5eff 5994 return 0;
d19a9cd2
ZX		 5995}
5996
5997static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5998{
5999 vcpu_load(vcpu);
6000 kvm_mmu_unload(vcpu);
6001 vcpu_put(vcpu);
6002}
6003
6004static void kvm_free_vcpus(struct kvm *kvm)
6005{
6006 unsigned int i;
988a2cae 6007 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6008
6009 /*
6010 * Unpin any mmu pages first.
6011 */
af585b92
GN		 6012 kvm_for_each_vcpu(i, vcpu, kvm) {
6013 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6014 kvm_unload_vcpu_mmu(vcpu);
af585b92 6015 }
988a2cae
GN		 6016 kvm_for_each_vcpu(i, vcpu, kvm)
6017 kvm_arch_vcpu_free(vcpu);
6018
6019 mutex_lock(&kvm->lock);
6020 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6021 kvm->vcpus[i] = NULL;
d19a9cd2 6022
988a2cae
GN		 6023 atomic_set(&kvm->online_vcpus, 0);
6024 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6025}
6026
ad8ba2cd
SY		 6027void kvm_arch_sync_events(struct kvm *kvm)
6028{
ba4cef31 6029 kvm_free_all_assigned_devices(kvm);
aea924f6 6030 kvm_free_pit(kvm);
ad8ba2cd
SY		 6031}
6032
d19a9cd2
ZX		 6033void kvm_arch_destroy_vm(struct kvm *kvm)
6034{
6eb55818 6035 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6036 kfree(kvm->arch.vpic);
6037 kfree(kvm->arch.vioapic);
d19a9cd2 6038 kvm_free_vcpus(kvm);
3d45830c
AK		 6039 if (kvm->arch.apic_access_page)
6040 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6041 if (kvm->arch.ept_identity_pagetable)
6042 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2 6043}
0de10343 6044
f7784b8e
MT		 6045int kvm_arch_prepare_memory_region(struct kvm *kvm,
6046 struct kvm_memory_slot *memslot,
0de10343 6047 struct kvm_memory_slot old,
f7784b8e 6048 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6049 int user_alloc)
6050{
f7784b8e 6051 int npages = memslot->npages;
7ac77099
AK		 6052 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6053
6054 /* Prevent internal slot pages from being moved by fork()/COW. */
6055 if (memslot->id >= KVM_MEMORY_SLOTS)
6056 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6057
6058 /*To keep backward compatibility with older userspace,
6059 *x86 needs to hanlde !user_alloc case.
6060 */
6061 if (!user_alloc) {
6062 if (npages && !old.rmap) {
604b38ac
AA		 6063 unsigned long userspace_addr;
6064
72dc67a6 6065 down_write(&current->mm->mmap_sem);
604b38ac
AA		 6066 userspace_addr = do_mmap(NULL, 0,
6067 npages * PAGE_SIZE,
6068 PROT_READ | PROT_WRITE,
7ac77099 6069 map_flags,
604b38ac 6070 0);
72dc67a6 6071 up_write(&current->mm->mmap_sem);
0de10343 6072
604b38ac
AA		 6073 if (IS_ERR((void *)userspace_addr))
6074 return PTR_ERR((void *)userspace_addr);
6075
604b38ac 6076 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6077 }
6078 }
6079
f7784b8e
MT		 6080
6081 return 0;
6082}
6083
6084void kvm_arch_commit_memory_region(struct kvm *kvm,
6085 struct kvm_userspace_memory_region *mem,
6086 struct kvm_memory_slot old,
6087 int user_alloc)
6088{
6089
6090 int npages = mem->memory_size >> PAGE_SHIFT;
6091
6092 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6093 int ret;
6094
6095 down_write(&current->mm->mmap_sem);
6096 ret = do_munmap(current->mm, old.userspace_addr,
6097 old.npages * PAGE_SIZE);
6098 up_write(&current->mm->mmap_sem);
6099 if (ret < 0)
6100 printk(KERN_WARNING
6101 "kvm_vm_ioctl_set_memory_region: "
6102 "failed to munmap memory\n");
6103 }
6104
7c8a83b7 6105 spin_lock(&kvm->mmu_lock);
f05e70ac 6106 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 6107 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6108 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
6109 }
6110
6111 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6112 spin_unlock(&kvm->mmu_lock);
0de10343 6113}
1d737c8a 6114
34d4cb8f
MT		 6115void kvm_arch_flush_shadow(struct kvm *kvm)
6116{
6117 kvm_mmu_zap_all(kvm);
8986ecc0 6118 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6119}
6120
1d737c8a
ZX		 6121int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6122{
af585b92
GN		 6123 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6124 !vcpu->arch.apf.halted)
6125 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100
GN		 6126 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6127 || vcpu->arch.nmi_pending ||
6128 (kvm_arch_interrupt_allowed(vcpu) &&
6129 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6130}
5736199a 6131
5736199a
ZX		 6132void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6133{
32f88400
MT		 6134 int me;
6135 int cpu = vcpu->cpu;
5736199a
ZX		 6136
6137 if (waitqueue_active(&vcpu->wq)) {
6138 wake_up_interruptible(&vcpu->wq);
6139 ++vcpu->stat.halt_wakeup;
6140 }
32f88400
MT		 6141
6142 me = get_cpu();
6143 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
d94e1dc9 6144 if (atomic_xchg(&vcpu->guest_mode, 0))
32f88400 6145 smp_send_reschedule(cpu);
e9571ed5 6146 put_cpu();
5736199a 6147}
78646121
GN		 6148
6149int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6150{
6151 return kvm_x86_ops->interrupt_allowed(vcpu);
6152}
229456fc 6153
f92653ee
JK		 6154bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6155{
6156 unsigned long current_rip = kvm_rip_read(vcpu) +
6157 get_segment_base(vcpu, VCPU_SREG_CS);
6158
6159 return current_rip == linear_rip;
6160}
6161EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6162
94fe45da
JK		 6163unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6164{
6165 unsigned long rflags;
6166
6167 rflags = kvm_x86_ops->get_rflags(vcpu);
6168 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6169 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6170 return rflags;
6171}
6172EXPORT_SYMBOL_GPL(kvm_get_rflags);
6173
6174void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6175{
6176 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6177 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6178 rflags |= X86_EFLAGS_TF;
94fe45da 6179 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6180 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6181}
6182EXPORT_SYMBOL_GPL(kvm_set_rflags);
6183
56028d08
GN		 6184void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6185{
6186 int r;
6187
fb67e14f 6188 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6189 is_error_page(work->page))
56028d08
GN		 6190 return;
6191
6192 r = kvm_mmu_reload(vcpu);
6193 if (unlikely(r))
6194 return;
6195
fb67e14f
XG		 6196 if (!vcpu->arch.mmu.direct_map &&
6197 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6198 return;
6199
56028d08
GN		 6200 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6201}
6202
af585b92
GN		 6203static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6204{
6205 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6206}
6207
6208static inline u32 kvm_async_pf_next_probe(u32 key)
6209{
6210 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6211}
6212
6213static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6214{
6215 u32 key = kvm_async_pf_hash_fn(gfn);
6216
6217 while (vcpu->arch.apf.gfns[key] != ~0)
6218 key = kvm_async_pf_next_probe(key);
6219
6220 vcpu->arch.apf.gfns[key] = gfn;
6221}
6222
6223static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6224{
6225 int i;
6226 u32 key = kvm_async_pf_hash_fn(gfn);
6227
6228 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6229 (vcpu->arch.apf.gfns[key] != gfn &&
6230 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6231 key = kvm_async_pf_next_probe(key);
6232
6233 return key;
6234}
6235
6236bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6237{
6238 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6239}
6240
6241static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6242{
6243 u32 i, j, k;
6244
6245 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6246 while (true) {
6247 vcpu->arch.apf.gfns[i] = ~0;
6248 do {
6249 j = kvm_async_pf_next_probe(j);
6250 if (vcpu->arch.apf.gfns[j] == ~0)
6251 return;
6252 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6253 /*
6254 * k lies cyclically in ]i,j]
6255 * | i.k.j |
6256 * |....j i.k.| or |.k..j i...|
6257 */
6258 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6259 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6260 i = j;
6261 }
6262}
6263
7c90705b
GN		 6264static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6265{
6266
6267 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6268 sizeof(val));
6269}
6270
af585b92
GN		 6271void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6272 struct kvm_async_pf *work)
6273{
6389ee94
AK		 6274 struct x86_exception fault;
6275
7c90705b 6276 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6277 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6278
6279 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6280 (vcpu->arch.apf.send_user_only &&
6281 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6282 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6283 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6284 fault.vector = PF_VECTOR;
6285 fault.error_code_valid = true;
6286 fault.error_code = 0;
6287 fault.nested_page_fault = false;
6288 fault.address = work->arch.token;
6289 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6290 }
af585b92
GN		 6291}
6292
6293void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6294 struct kvm_async_pf *work)
6295{
6389ee94
AK		 6296 struct x86_exception fault;
6297
7c90705b
GN		 6298 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6299 if (is_error_page(work->page))
6300 work->arch.token = ~0; /* broadcast wakeup */
6301 else
6302 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6303
6304 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6305 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6306 fault.vector = PF_VECTOR;
6307 fault.error_code_valid = true;
6308 fault.error_code = 0;
6309 fault.nested_page_fault = false;
6310 fault.address = work->arch.token;
6311 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6312 }
e6d53e3b 6313 vcpu->arch.apf.halted = false;
7c90705b
GN		 6314}
6315
6316bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6317{
6318 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6319 return true;
6320 else
6321 return !kvm_event_needs_reinjection(vcpu) &&
6322 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6323}
6324
229456fc
MT		 6325EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6326EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6327EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6328EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6329EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6330EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6331EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6332EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6333EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6334EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6335EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6336EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Ubuntu Artful kernel mirror