]>
Commit | Line | Data |
---|---|---|
20c8ccb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
043405e1 CO |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * | |
5 | * derived from drivers/kvm/kvm_main.c | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
8 | * Copyright (C) 2008 Qumranet, Inc. |
9 | * Copyright IBM Corporation, 2008 | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
043405e1 CO |
11 | * |
12 | * Authors: | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
15 | * Amit Shah <amit.shah@qumranet.com> |
16 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
17 | */ |
18 | ||
edf88417 | 19 | #include <linux/kvm_host.h> |
313a3dc7 | 20 | #include "irq.h" |
1d737c8a | 21 | #include "mmu.h" |
7837699f | 22 | #include "i8254.h" |
37817f29 | 23 | #include "tss.h" |
5fdbf976 | 24 | #include "kvm_cache_regs.h" |
26eef70c | 25 | #include "x86.h" |
00b27a3e | 26 | #include "cpuid.h" |
474a5bb9 | 27 | #include "pmu.h" |
e83d5887 | 28 | #include "hyperv.h" |
8df14af4 | 29 | #include "lapic.h" |
313a3dc7 | 30 | |
18068523 | 31 | #include <linux/clocksource.h> |
4d5c5d0f | 32 | #include <linux/interrupt.h> |
313a3dc7 CO |
33 | #include <linux/kvm.h> |
34 | #include <linux/fs.h> | |
35 | #include <linux/vmalloc.h> | |
1767e931 PG |
36 | #include <linux/export.h> |
37 | #include <linux/moduleparam.h> | |
0de10343 | 38 | #include <linux/mman.h> |
2bacc55c | 39 | #include <linux/highmem.h> |
19de40a8 | 40 | #include <linux/iommu.h> |
62c476c7 | 41 | #include <linux/intel-iommu.h> |
c8076604 | 42 | #include <linux/cpufreq.h> |
18863bdd | 43 | #include <linux/user-return-notifier.h> |
a983fb23 | 44 | #include <linux/srcu.h> |
5a0e3ad6 | 45 | #include <linux/slab.h> |
ff9d07a0 | 46 | #include <linux/perf_event.h> |
7bee342a | 47 | #include <linux/uaccess.h> |
af585b92 | 48 | #include <linux/hash.h> |
a1b60c1c | 49 | #include <linux/pci.h> |
16e8d74d MT |
50 | #include <linux/timekeeper_internal.h> |
51 | #include <linux/pvclock_gtod.h> | |
87276880 FW |
52 | #include <linux/kvm_irqfd.h> |
53 | #include <linux/irqbypass.h> | |
3905f9ad | 54 | #include <linux/sched/stat.h> |
0c5f81da | 55 | #include <linux/sched/isolation.h> |
d0ec49d4 | 56 | #include <linux/mem_encrypt.h> |
3905f9ad | 57 | |
aec51dc4 | 58 | #include <trace/events/kvm.h> |
2ed152af | 59 | |
24f1e32c | 60 | #include <asm/debugreg.h> |
d825ed0a | 61 | #include <asm/msr.h> |
a5f61300 | 62 | #include <asm/desc.h> |
890ca9ae | 63 | #include <asm/mce.h> |
f89e32e0 | 64 | #include <linux/kernel_stat.h> |
78f7f1e5 | 65 | #include <asm/fpu/internal.h> /* Ugh! */ |
1d5f066e | 66 | #include <asm/pvclock.h> |
217fc9cf | 67 | #include <asm/div64.h> |
efc64404 | 68 | #include <asm/irq_remapping.h> |
b0c39dc6 | 69 | #include <asm/mshyperv.h> |
0092e434 | 70 | #include <asm/hypervisor.h> |
bf8c55d8 | 71 | #include <asm/intel_pt.h> |
b3dc0695 | 72 | #include <asm/emulate_prefix.h> |
dd2cb348 | 73 | #include <clocksource/hyperv_timer.h> |
043405e1 | 74 | |
d1898b73 DH |
75 | #define CREATE_TRACE_POINTS |
76 | #include "trace.h" | |
77 | ||
313a3dc7 | 78 | #define MAX_IO_MSRS 256 |
890ca9ae | 79 | #define KVM_MAX_MCE_BANKS 32 |
c45dcc71 AR |
80 | u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; |
81 | EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); | |
890ca9ae | 82 | |
0f65dd70 AK |
83 | #define emul_to_vcpu(ctxt) \ |
84 | container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) | |
85 | ||
50a37eb4 JR |
86 | /* EFER defaults: |
87 | * - enable syscall per default because its emulated by KVM | |
88 | * - enable LME and LMA per default on 64 bit KVM | |
89 | */ | |
90 | #ifdef CONFIG_X86_64 | |
1260edbe LJ |
91 | static |
92 | u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); | |
50a37eb4 | 93 | #else |
1260edbe | 94 | static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); |
50a37eb4 | 95 | #endif |
313a3dc7 | 96 | |
b11306b5 SC |
97 | static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; |
98 | ||
833b45de PB |
99 | #define VM_STAT(x, ...) offsetof(struct kvm, stat.x), KVM_STAT_VM, ## __VA_ARGS__ |
100 | #define VCPU_STAT(x, ...) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU, ## __VA_ARGS__ | |
417bc304 | 101 | |
c519265f RK |
102 | #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ |
103 | KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) | |
37131313 | 104 | |
cb142eb7 | 105 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
7460fb4a | 106 | static void process_nmi(struct kvm_vcpu *vcpu); |
ee2cd4b7 | 107 | static void enter_smm(struct kvm_vcpu *vcpu); |
6addfc42 | 108 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); |
01643c51 KH |
109 | static void store_regs(struct kvm_vcpu *vcpu); |
110 | static int sync_regs(struct kvm_vcpu *vcpu); | |
674eea0f | 111 | |
893590c7 | 112 | struct kvm_x86_ops *kvm_x86_ops __read_mostly; |
5fdbf976 | 113 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 114 | |
893590c7 | 115 | static bool __read_mostly ignore_msrs = 0; |
476bc001 | 116 | module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); |
ed85c068 | 117 | |
fab0aa3b EM |
118 | static bool __read_mostly report_ignored_msrs = true; |
119 | module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); | |
120 | ||
4c27625b | 121 | unsigned int min_timer_period_us = 200; |
9ed96e87 MT |
122 | module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); |
123 | ||
630994b3 MT |
124 | static bool __read_mostly kvmclock_periodic_sync = true; |
125 | module_param(kvmclock_periodic_sync, bool, S_IRUGO); | |
126 | ||
893590c7 | 127 | bool __read_mostly kvm_has_tsc_control; |
92a1f12d | 128 | EXPORT_SYMBOL_GPL(kvm_has_tsc_control); |
893590c7 | 129 | u32 __read_mostly kvm_max_guest_tsc_khz; |
92a1f12d | 130 | EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); |
bc9b961b HZ |
131 | u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; |
132 | EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); | |
133 | u64 __read_mostly kvm_max_tsc_scaling_ratio; | |
134 | EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); | |
64672c95 YJ |
135 | u64 __read_mostly kvm_default_tsc_scaling_ratio; |
136 | EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); | |
92a1f12d | 137 | |
cc578287 | 138 | /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ |
893590c7 | 139 | static u32 __read_mostly tsc_tolerance_ppm = 250; |
cc578287 ZA |
140 | module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); |
141 | ||
c3941d9e SC |
142 | /* |
143 | * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables | |
144 | * adaptive tuning starting from default advancment of 1000ns. '0' disables | |
145 | * advancement entirely. Any other value is used as-is and disables adaptive | |
146 | * tuning, i.e. allows priveleged userspace to set an exact advancement time. | |
147 | */ | |
148 | static int __read_mostly lapic_timer_advance_ns = -1; | |
0e6edceb | 149 | module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR); |
d0659d94 | 150 | |
52004014 FW |
151 | static bool __read_mostly vector_hashing = true; |
152 | module_param(vector_hashing, bool, S_IRUGO); | |
153 | ||
c4ae60e4 LA |
154 | bool __read_mostly enable_vmware_backdoor = false; |
155 | module_param(enable_vmware_backdoor, bool, S_IRUGO); | |
156 | EXPORT_SYMBOL_GPL(enable_vmware_backdoor); | |
157 | ||
6c86eedc WL |
158 | static bool __read_mostly force_emulation_prefix = false; |
159 | module_param(force_emulation_prefix, bool, S_IRUGO); | |
160 | ||
0c5f81da WL |
161 | int __read_mostly pi_inject_timer = -1; |
162 | module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); | |
163 | ||
18863bdd AK |
164 | #define KVM_NR_SHARED_MSRS 16 |
165 | ||
166 | struct kvm_shared_msrs_global { | |
167 | int nr; | |
2bf78fa7 | 168 | u32 msrs[KVM_NR_SHARED_MSRS]; |
18863bdd AK |
169 | }; |
170 | ||
171 | struct kvm_shared_msrs { | |
172 | struct user_return_notifier urn; | |
173 | bool registered; | |
2bf78fa7 SY |
174 | struct kvm_shared_msr_values { |
175 | u64 host; | |
176 | u64 curr; | |
177 | } values[KVM_NR_SHARED_MSRS]; | |
18863bdd AK |
178 | }; |
179 | ||
180 | static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; | |
013f6a5d | 181 | static struct kvm_shared_msrs __percpu *shared_msrs; |
18863bdd | 182 | |
139a12cf AL |
183 | static u64 __read_mostly host_xss; |
184 | ||
417bc304 | 185 | struct kvm_stats_debugfs_item debugfs_entries[] = { |
ba1389b7 AK |
186 | { "pf_fixed", VCPU_STAT(pf_fixed) }, |
187 | { "pf_guest", VCPU_STAT(pf_guest) }, | |
188 | { "tlb_flush", VCPU_STAT(tlb_flush) }, | |
189 | { "invlpg", VCPU_STAT(invlpg) }, | |
190 | { "exits", VCPU_STAT(exits) }, | |
191 | { "io_exits", VCPU_STAT(io_exits) }, | |
192 | { "mmio_exits", VCPU_STAT(mmio_exits) }, | |
193 | { "signal_exits", VCPU_STAT(signal_exits) }, | |
194 | { "irq_window", VCPU_STAT(irq_window_exits) }, | |
f08864b4 | 195 | { "nmi_window", VCPU_STAT(nmi_window_exits) }, |
ba1389b7 | 196 | { "halt_exits", VCPU_STAT(halt_exits) }, |
f7819512 | 197 | { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, |
62bea5bf | 198 | { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) }, |
3491caf2 | 199 | { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) }, |
ba1389b7 | 200 | { "halt_wakeup", VCPU_STAT(halt_wakeup) }, |
f11c3a8d | 201 | { "hypercalls", VCPU_STAT(hypercalls) }, |
ba1389b7 AK |
202 | { "request_irq", VCPU_STAT(request_irq_exits) }, |
203 | { "irq_exits", VCPU_STAT(irq_exits) }, | |
204 | { "host_state_reload", VCPU_STAT(host_state_reload) }, | |
ba1389b7 AK |
205 | { "fpu_reload", VCPU_STAT(fpu_reload) }, |
206 | { "insn_emulation", VCPU_STAT(insn_emulation) }, | |
207 | { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, | |
fa89a817 | 208 | { "irq_injections", VCPU_STAT(irq_injections) }, |
c4abb7c9 | 209 | { "nmi_injections", VCPU_STAT(nmi_injections) }, |
0f1e261e | 210 | { "req_event", VCPU_STAT(req_event) }, |
c595ceee | 211 | { "l1d_flush", VCPU_STAT(l1d_flush) }, |
4cee5764 AK |
212 | { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, |
213 | { "mmu_pte_write", VM_STAT(mmu_pte_write) }, | |
214 | { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, | |
215 | { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, | |
216 | { "mmu_flooded", VM_STAT(mmu_flooded) }, | |
217 | { "mmu_recycled", VM_STAT(mmu_recycled) }, | |
dfc5aa00 | 218 | { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, |
4731d4c7 | 219 | { "mmu_unsync", VM_STAT(mmu_unsync) }, |
0f74a24c | 220 | { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, |
833b45de | 221 | { "largepages", VM_STAT(lpages, .mode = 0444) }, |
b8e8c830 | 222 | { "nx_largepages_splitted", VM_STAT(nx_lpage_splits, .mode = 0444) }, |
f3414bc7 DM |
223 | { "max_mmu_page_hash_collisions", |
224 | VM_STAT(max_mmu_page_hash_collisions) }, | |
417bc304 HB |
225 | { NULL } |
226 | }; | |
227 | ||
2acf923e DC |
228 | u64 __read_mostly host_xcr0; |
229 | ||
b666a4b6 MO |
230 | struct kmem_cache *x86_fpu_cache; |
231 | EXPORT_SYMBOL_GPL(x86_fpu_cache); | |
232 | ||
b6785def | 233 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); |
d6aa1000 | 234 | |
af585b92 GN |
235 | static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) |
236 | { | |
237 | int i; | |
238 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) | |
239 | vcpu->arch.apf.gfns[i] = ~0; | |
240 | } | |
241 | ||
18863bdd AK |
242 | static void kvm_on_user_return(struct user_return_notifier *urn) |
243 | { | |
244 | unsigned slot; | |
18863bdd AK |
245 | struct kvm_shared_msrs *locals |
246 | = container_of(urn, struct kvm_shared_msrs, urn); | |
2bf78fa7 | 247 | struct kvm_shared_msr_values *values; |
1650b4eb IA |
248 | unsigned long flags; |
249 | ||
250 | /* | |
251 | * Disabling irqs at this point since the following code could be | |
252 | * interrupted and executed through kvm_arch_hardware_disable() | |
253 | */ | |
254 | local_irq_save(flags); | |
255 | if (locals->registered) { | |
256 | locals->registered = false; | |
257 | user_return_notifier_unregister(urn); | |
258 | } | |
259 | local_irq_restore(flags); | |
18863bdd | 260 | for (slot = 0; slot < shared_msrs_global.nr; ++slot) { |
2bf78fa7 SY |
261 | values = &locals->values[slot]; |
262 | if (values->host != values->curr) { | |
263 | wrmsrl(shared_msrs_global.msrs[slot], values->host); | |
264 | values->curr = values->host; | |
18863bdd AK |
265 | } |
266 | } | |
18863bdd AK |
267 | } |
268 | ||
2bf78fa7 SY |
269 | void kvm_define_shared_msr(unsigned slot, u32 msr) |
270 | { | |
0123be42 | 271 | BUG_ON(slot >= KVM_NR_SHARED_MSRS); |
c847fe88 | 272 | shared_msrs_global.msrs[slot] = msr; |
18863bdd AK |
273 | if (slot >= shared_msrs_global.nr) |
274 | shared_msrs_global.nr = slot + 1; | |
18863bdd AK |
275 | } |
276 | EXPORT_SYMBOL_GPL(kvm_define_shared_msr); | |
277 | ||
278 | static void kvm_shared_msr_cpu_online(void) | |
279 | { | |
05c19c2f SC |
280 | unsigned int cpu = smp_processor_id(); |
281 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
282 | u64 value; | |
283 | int i; | |
18863bdd | 284 | |
05c19c2f SC |
285 | for (i = 0; i < shared_msrs_global.nr; ++i) { |
286 | rdmsrl_safe(shared_msrs_global.msrs[i], &value); | |
287 | smsr->values[i].host = value; | |
288 | smsr->values[i].curr = value; | |
289 | } | |
18863bdd AK |
290 | } |
291 | ||
8b3c3104 | 292 | int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) |
18863bdd | 293 | { |
013f6a5d MT |
294 | unsigned int cpu = smp_processor_id(); |
295 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
8b3c3104 | 296 | int err; |
18863bdd | 297 | |
de1fca5d PB |
298 | value = (value & mask) | (smsr->values[slot].host & ~mask); |
299 | if (value == smsr->values[slot].curr) | |
8b3c3104 | 300 | return 0; |
8b3c3104 AH |
301 | err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); |
302 | if (err) | |
303 | return 1; | |
304 | ||
de1fca5d | 305 | smsr->values[slot].curr = value; |
18863bdd AK |
306 | if (!smsr->registered) { |
307 | smsr->urn.on_user_return = kvm_on_user_return; | |
308 | user_return_notifier_register(&smsr->urn); | |
309 | smsr->registered = true; | |
310 | } | |
8b3c3104 | 311 | return 0; |
18863bdd AK |
312 | } |
313 | EXPORT_SYMBOL_GPL(kvm_set_shared_msr); | |
314 | ||
13a34e06 | 315 | static void drop_user_return_notifiers(void) |
3548bab5 | 316 | { |
013f6a5d MT |
317 | unsigned int cpu = smp_processor_id(); |
318 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
3548bab5 AK |
319 | |
320 | if (smsr->registered) | |
321 | kvm_on_user_return(&smsr->urn); | |
322 | } | |
323 | ||
6866b83e CO |
324 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
325 | { | |
8a5a87d9 | 326 | return vcpu->arch.apic_base; |
6866b83e CO |
327 | } |
328 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
329 | ||
58871649 JM |
330 | enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) |
331 | { | |
332 | return kvm_apic_mode(kvm_get_apic_base(vcpu)); | |
333 | } | |
334 | EXPORT_SYMBOL_GPL(kvm_get_apic_mode); | |
335 | ||
58cb628d JK |
336 | int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
337 | { | |
58871649 JM |
338 | enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); |
339 | enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); | |
d6321d49 RK |
340 | u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff | |
341 | (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); | |
58cb628d | 342 | |
58871649 | 343 | if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) |
58cb628d | 344 | return 1; |
58871649 JM |
345 | if (!msr_info->host_initiated) { |
346 | if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) | |
347 | return 1; | |
348 | if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) | |
349 | return 1; | |
350 | } | |
58cb628d JK |
351 | |
352 | kvm_lapic_set_base(vcpu, msr_info->data); | |
353 | return 0; | |
6866b83e CO |
354 | } |
355 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
356 | ||
2605fc21 | 357 | asmlinkage __visible void kvm_spurious_fault(void) |
e3ba45b8 GL |
358 | { |
359 | /* Fault while not rebooting. We want the trace. */ | |
b4fdcf60 | 360 | BUG_ON(!kvm_rebooting); |
e3ba45b8 GL |
361 | } |
362 | EXPORT_SYMBOL_GPL(kvm_spurious_fault); | |
363 | ||
3fd28fce ED |
364 | #define EXCPT_BENIGN 0 |
365 | #define EXCPT_CONTRIBUTORY 1 | |
366 | #define EXCPT_PF 2 | |
367 | ||
368 | static int exception_class(int vector) | |
369 | { | |
370 | switch (vector) { | |
371 | case PF_VECTOR: | |
372 | return EXCPT_PF; | |
373 | case DE_VECTOR: | |
374 | case TS_VECTOR: | |
375 | case NP_VECTOR: | |
376 | case SS_VECTOR: | |
377 | case GP_VECTOR: | |
378 | return EXCPT_CONTRIBUTORY; | |
379 | default: | |
380 | break; | |
381 | } | |
382 | return EXCPT_BENIGN; | |
383 | } | |
384 | ||
d6e8c854 NA |
385 | #define EXCPT_FAULT 0 |
386 | #define EXCPT_TRAP 1 | |
387 | #define EXCPT_ABORT 2 | |
388 | #define EXCPT_INTERRUPT 3 | |
389 | ||
390 | static int exception_type(int vector) | |
391 | { | |
392 | unsigned int mask; | |
393 | ||
394 | if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) | |
395 | return EXCPT_INTERRUPT; | |
396 | ||
397 | mask = 1 << vector; | |
398 | ||
399 | /* #DB is trap, as instruction watchpoints are handled elsewhere */ | |
400 | if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) | |
401 | return EXCPT_TRAP; | |
402 | ||
403 | if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) | |
404 | return EXCPT_ABORT; | |
405 | ||
406 | /* Reserved exceptions will result in fault */ | |
407 | return EXCPT_FAULT; | |
408 | } | |
409 | ||
da998b46 JM |
410 | void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) |
411 | { | |
412 | unsigned nr = vcpu->arch.exception.nr; | |
413 | bool has_payload = vcpu->arch.exception.has_payload; | |
414 | unsigned long payload = vcpu->arch.exception.payload; | |
415 | ||
416 | if (!has_payload) | |
417 | return; | |
418 | ||
419 | switch (nr) { | |
f10c729f JM |
420 | case DB_VECTOR: |
421 | /* | |
422 | * "Certain debug exceptions may clear bit 0-3. The | |
423 | * remaining contents of the DR6 register are never | |
424 | * cleared by the processor". | |
425 | */ | |
426 | vcpu->arch.dr6 &= ~DR_TRAP_BITS; | |
427 | /* | |
428 | * DR6.RTM is set by all #DB exceptions that don't clear it. | |
429 | */ | |
430 | vcpu->arch.dr6 |= DR6_RTM; | |
431 | vcpu->arch.dr6 |= payload; | |
432 | /* | |
433 | * Bit 16 should be set in the payload whenever the #DB | |
434 | * exception should clear DR6.RTM. This makes the payload | |
435 | * compatible with the pending debug exceptions under VMX. | |
436 | * Though not currently documented in the SDM, this also | |
437 | * makes the payload compatible with the exit qualification | |
438 | * for #DB exceptions under VMX. | |
439 | */ | |
440 | vcpu->arch.dr6 ^= payload & DR6_RTM; | |
441 | break; | |
da998b46 JM |
442 | case PF_VECTOR: |
443 | vcpu->arch.cr2 = payload; | |
444 | break; | |
445 | } | |
446 | ||
447 | vcpu->arch.exception.has_payload = false; | |
448 | vcpu->arch.exception.payload = 0; | |
449 | } | |
450 | EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); | |
451 | ||
3fd28fce | 452 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, |
ce7ddec4 | 453 | unsigned nr, bool has_error, u32 error_code, |
91e86d22 | 454 | bool has_payload, unsigned long payload, bool reinject) |
3fd28fce ED |
455 | { |
456 | u32 prev_nr; | |
457 | int class1, class2; | |
458 | ||
3842d135 AK |
459 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
460 | ||
664f8e26 | 461 | if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { |
3fd28fce | 462 | queue: |
3ffb2468 NA |
463 | if (has_error && !is_protmode(vcpu)) |
464 | has_error = false; | |
664f8e26 WL |
465 | if (reinject) { |
466 | /* | |
467 | * On vmentry, vcpu->arch.exception.pending is only | |
468 | * true if an event injection was blocked by | |
469 | * nested_run_pending. In that case, however, | |
470 | * vcpu_enter_guest requests an immediate exit, | |
471 | * and the guest shouldn't proceed far enough to | |
472 | * need reinjection. | |
473 | */ | |
474 | WARN_ON_ONCE(vcpu->arch.exception.pending); | |
475 | vcpu->arch.exception.injected = true; | |
91e86d22 JM |
476 | if (WARN_ON_ONCE(has_payload)) { |
477 | /* | |
478 | * A reinjected event has already | |
479 | * delivered its payload. | |
480 | */ | |
481 | has_payload = false; | |
482 | payload = 0; | |
483 | } | |
664f8e26 WL |
484 | } else { |
485 | vcpu->arch.exception.pending = true; | |
486 | vcpu->arch.exception.injected = false; | |
487 | } | |
3fd28fce ED |
488 | vcpu->arch.exception.has_error_code = has_error; |
489 | vcpu->arch.exception.nr = nr; | |
490 | vcpu->arch.exception.error_code = error_code; | |
91e86d22 JM |
491 | vcpu->arch.exception.has_payload = has_payload; |
492 | vcpu->arch.exception.payload = payload; | |
da998b46 JM |
493 | /* |
494 | * In guest mode, payload delivery should be deferred, | |
495 | * so that the L1 hypervisor can intercept #PF before | |
f10c729f JM |
496 | * CR2 is modified (or intercept #DB before DR6 is |
497 | * modified under nVMX). However, for ABI | |
498 | * compatibility with KVM_GET_VCPU_EVENTS and | |
499 | * KVM_SET_VCPU_EVENTS, we can't delay payload | |
500 | * delivery unless userspace has enabled this | |
501 | * functionality via the per-VM capability, | |
502 | * KVM_CAP_EXCEPTION_PAYLOAD. | |
da998b46 JM |
503 | */ |
504 | if (!vcpu->kvm->arch.exception_payload_enabled || | |
505 | !is_guest_mode(vcpu)) | |
506 | kvm_deliver_exception_payload(vcpu); | |
3fd28fce ED |
507 | return; |
508 | } | |
509 | ||
510 | /* to check exception */ | |
511 | prev_nr = vcpu->arch.exception.nr; | |
512 | if (prev_nr == DF_VECTOR) { | |
513 | /* triple fault -> shutdown */ | |
a8eeb04a | 514 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
3fd28fce ED |
515 | return; |
516 | } | |
517 | class1 = exception_class(prev_nr); | |
518 | class2 = exception_class(nr); | |
519 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) | |
520 | || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
664f8e26 WL |
521 | /* |
522 | * Generate double fault per SDM Table 5-5. Set | |
523 | * exception.pending = true so that the double fault | |
524 | * can trigger a nested vmexit. | |
525 | */ | |
3fd28fce | 526 | vcpu->arch.exception.pending = true; |
664f8e26 | 527 | vcpu->arch.exception.injected = false; |
3fd28fce ED |
528 | vcpu->arch.exception.has_error_code = true; |
529 | vcpu->arch.exception.nr = DF_VECTOR; | |
530 | vcpu->arch.exception.error_code = 0; | |
c851436a JM |
531 | vcpu->arch.exception.has_payload = false; |
532 | vcpu->arch.exception.payload = 0; | |
3fd28fce ED |
533 | } else |
534 | /* replace previous exception with a new one in a hope | |
535 | that instruction re-execution will regenerate lost | |
536 | exception */ | |
537 | goto queue; | |
538 | } | |
539 | ||
298101da AK |
540 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
541 | { | |
91e86d22 | 542 | kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); |
298101da AK |
543 | } |
544 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
545 | ||
ce7ddec4 JR |
546 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
547 | { | |
91e86d22 | 548 | kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); |
ce7ddec4 JR |
549 | } |
550 | EXPORT_SYMBOL_GPL(kvm_requeue_exception); | |
551 | ||
f10c729f JM |
552 | static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, |
553 | unsigned long payload) | |
554 | { | |
555 | kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); | |
556 | } | |
557 | ||
da998b46 JM |
558 | static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, |
559 | u32 error_code, unsigned long payload) | |
560 | { | |
561 | kvm_multiple_exception(vcpu, nr, true, error_code, | |
562 | true, payload, false); | |
563 | } | |
564 | ||
6affcbed | 565 | int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) |
c3c91fee | 566 | { |
db8fcefa AP |
567 | if (err) |
568 | kvm_inject_gp(vcpu, 0); | |
569 | else | |
6affcbed KH |
570 | return kvm_skip_emulated_instruction(vcpu); |
571 | ||
572 | return 1; | |
db8fcefa AP |
573 | } |
574 | EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); | |
8df25a32 | 575 | |
6389ee94 | 576 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
c3c91fee AK |
577 | { |
578 | ++vcpu->stat.pf_guest; | |
adfe20fb WL |
579 | vcpu->arch.exception.nested_apf = |
580 | is_guest_mode(vcpu) && fault->async_page_fault; | |
da998b46 | 581 | if (vcpu->arch.exception.nested_apf) { |
adfe20fb | 582 | vcpu->arch.apf.nested_apf_token = fault->address; |
da998b46 JM |
583 | kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); |
584 | } else { | |
585 | kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, | |
586 | fault->address); | |
587 | } | |
c3c91fee | 588 | } |
27d6c865 | 589 | EXPORT_SYMBOL_GPL(kvm_inject_page_fault); |
c3c91fee | 590 | |
ef54bcfe | 591 | static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
d4f8cf66 | 592 | { |
6389ee94 AK |
593 | if (mmu_is_nested(vcpu) && !fault->nested_page_fault) |
594 | vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); | |
d4f8cf66 | 595 | else |
44dd3ffa | 596 | vcpu->arch.mmu->inject_page_fault(vcpu, fault); |
ef54bcfe PB |
597 | |
598 | return fault->nested_page_fault; | |
d4f8cf66 JR |
599 | } |
600 | ||
3419ffc8 SY |
601 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
602 | { | |
7460fb4a AK |
603 | atomic_inc(&vcpu->arch.nmi_queued); |
604 | kvm_make_request(KVM_REQ_NMI, vcpu); | |
3419ffc8 SY |
605 | } |
606 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
607 | ||
298101da AK |
608 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
609 | { | |
91e86d22 | 610 | kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); |
298101da AK |
611 | } |
612 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
613 | ||
ce7ddec4 JR |
614 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
615 | { | |
91e86d22 | 616 | kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); |
ce7ddec4 JR |
617 | } |
618 | EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); | |
619 | ||
0a79b009 AK |
620 | /* |
621 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
622 | * a #GP and return false. | |
623 | */ | |
624 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 625 | { |
0a79b009 AK |
626 | if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) |
627 | return true; | |
628 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
629 | return false; | |
298101da | 630 | } |
0a79b009 | 631 | EXPORT_SYMBOL_GPL(kvm_require_cpl); |
298101da | 632 | |
16f8a6f9 NA |
633 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) |
634 | { | |
635 | if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
636 | return true; | |
637 | ||
638 | kvm_queue_exception(vcpu, UD_VECTOR); | |
639 | return false; | |
640 | } | |
641 | EXPORT_SYMBOL_GPL(kvm_require_dr); | |
642 | ||
ec92fe44 JR |
643 | /* |
644 | * This function will be used to read from the physical memory of the currently | |
54bf36aa | 645 | * running guest. The difference to kvm_vcpu_read_guest_page is that this function |
ec92fe44 JR |
646 | * can read from guest physical or from the guest's guest physical memory. |
647 | */ | |
648 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
649 | gfn_t ngfn, void *data, int offset, int len, | |
650 | u32 access) | |
651 | { | |
54987b7a | 652 | struct x86_exception exception; |
ec92fe44 JR |
653 | gfn_t real_gfn; |
654 | gpa_t ngpa; | |
655 | ||
656 | ngpa = gfn_to_gpa(ngfn); | |
54987b7a | 657 | real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); |
ec92fe44 JR |
658 | if (real_gfn == UNMAPPED_GVA) |
659 | return -EFAULT; | |
660 | ||
661 | real_gfn = gpa_to_gfn(real_gfn); | |
662 | ||
54bf36aa | 663 | return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); |
ec92fe44 JR |
664 | } |
665 | EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); | |
666 | ||
69b0049a | 667 | static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, |
3d06b8bf JR |
668 | void *data, int offset, int len, u32 access) |
669 | { | |
670 | return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, | |
671 | data, offset, len, access); | |
672 | } | |
673 | ||
16cfacc8 SC |
674 | static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) |
675 | { | |
676 | return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) | | |
677 | rsvd_bits(1, 2); | |
678 | } | |
679 | ||
a03490ed | 680 | /* |
16cfacc8 | 681 | * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. |
a03490ed | 682 | */ |
ff03a073 | 683 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) |
a03490ed CO |
684 | { |
685 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
686 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
687 | int i; | |
688 | int ret; | |
ff03a073 | 689 | u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; |
a03490ed | 690 | |
ff03a073 JR |
691 | ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, |
692 | offset * sizeof(u64), sizeof(pdpte), | |
693 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
a03490ed CO |
694 | if (ret < 0) { |
695 | ret = 0; | |
696 | goto out; | |
697 | } | |
698 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
812f30b2 | 699 | if ((pdpte[i] & PT_PRESENT_MASK) && |
16cfacc8 | 700 | (pdpte[i] & pdptr_rsvd_bits(vcpu))) { |
a03490ed CO |
701 | ret = 0; |
702 | goto out; | |
703 | } | |
704 | } | |
705 | ret = 1; | |
706 | ||
ff03a073 | 707 | memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); |
cb3c1e2f SC |
708 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); |
709 | ||
a03490ed | 710 | out: |
a03490ed CO |
711 | |
712 | return ret; | |
713 | } | |
cc4b6871 | 714 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 715 | |
9ed38ffa | 716 | bool pdptrs_changed(struct kvm_vcpu *vcpu) |
d835dfec | 717 | { |
ff03a073 | 718 | u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; |
3d06b8bf JR |
719 | int offset; |
720 | gfn_t gfn; | |
d835dfec AK |
721 | int r; |
722 | ||
bf03d4f9 | 723 | if (!is_pae_paging(vcpu)) |
d835dfec AK |
724 | return false; |
725 | ||
cb3c1e2f | 726 | if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR)) |
6de4f3ad AK |
727 | return true; |
728 | ||
a512177e PB |
729 | gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT; |
730 | offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1); | |
3d06b8bf JR |
731 | r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), |
732 | PFERR_USER_MASK | PFERR_WRITE_MASK); | |
d835dfec | 733 | if (r < 0) |
7f7f0d9c | 734 | return true; |
d835dfec | 735 | |
7f7f0d9c | 736 | return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; |
d835dfec | 737 | } |
9ed38ffa | 738 | EXPORT_SYMBOL_GPL(pdptrs_changed); |
d835dfec | 739 | |
49a9b07e | 740 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 741 | { |
aad82703 | 742 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
d81135a5 | 743 | unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; |
aad82703 | 744 | |
f9a48e6a AK |
745 | cr0 |= X86_CR0_ET; |
746 | ||
ab344828 | 747 | #ifdef CONFIG_X86_64 |
0f12244f GN |
748 | if (cr0 & 0xffffffff00000000UL) |
749 | return 1; | |
ab344828 GN |
750 | #endif |
751 | ||
752 | cr0 &= ~CR0_RESERVED_BITS; | |
a03490ed | 753 | |
0f12244f GN |
754 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) |
755 | return 1; | |
a03490ed | 756 | |
0f12244f GN |
757 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) |
758 | return 1; | |
a03490ed CO |
759 | |
760 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { | |
761 | #ifdef CONFIG_X86_64 | |
f6801dff | 762 | if ((vcpu->arch.efer & EFER_LME)) { |
a03490ed CO |
763 | int cs_db, cs_l; |
764 | ||
0f12244f GN |
765 | if (!is_pae(vcpu)) |
766 | return 1; | |
a03490ed | 767 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
0f12244f GN |
768 | if (cs_l) |
769 | return 1; | |
a03490ed CO |
770 | } else |
771 | #endif | |
ff03a073 | 772 | if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
9f8fe504 | 773 | kvm_read_cr3(vcpu))) |
0f12244f | 774 | return 1; |
a03490ed CO |
775 | } |
776 | ||
ad756a16 MJ |
777 | if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) |
778 | return 1; | |
779 | ||
a03490ed | 780 | kvm_x86_ops->set_cr0(vcpu, cr0); |
a03490ed | 781 | |
d170c419 | 782 | if ((cr0 ^ old_cr0) & X86_CR0_PG) { |
e5f3f027 | 783 | kvm_clear_async_pf_completion_queue(vcpu); |
d170c419 LJ |
784 | kvm_async_pf_hash_reset(vcpu); |
785 | } | |
e5f3f027 | 786 | |
aad82703 SY |
787 | if ((cr0 ^ old_cr0) & update_bits) |
788 | kvm_mmu_reset_context(vcpu); | |
b18d5431 | 789 | |
879ae188 LE |
790 | if (((cr0 ^ old_cr0) & X86_CR0_CD) && |
791 | kvm_arch_has_noncoherent_dma(vcpu->kvm) && | |
792 | !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) | |
b18d5431 XG |
793 | kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); |
794 | ||
0f12244f GN |
795 | return 0; |
796 | } | |
2d3ad1f4 | 797 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 798 | |
2d3ad1f4 | 799 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 800 | { |
49a9b07e | 801 | (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); |
a03490ed | 802 | } |
2d3ad1f4 | 803 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 804 | |
139a12cf | 805 | void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) |
42bdf991 | 806 | { |
139a12cf AL |
807 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { |
808 | ||
809 | if (vcpu->arch.xcr0 != host_xcr0) | |
810 | xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); | |
811 | ||
812 | if (vcpu->arch.xsaves_enabled && | |
813 | vcpu->arch.ia32_xss != host_xss) | |
814 | wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); | |
815 | } | |
42bdf991 | 816 | } |
139a12cf | 817 | EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state); |
42bdf991 | 818 | |
139a12cf | 819 | void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) |
42bdf991 | 820 | { |
139a12cf AL |
821 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { |
822 | ||
823 | if (vcpu->arch.xcr0 != host_xcr0) | |
824 | xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); | |
825 | ||
826 | if (vcpu->arch.xsaves_enabled && | |
827 | vcpu->arch.ia32_xss != host_xss) | |
828 | wrmsrl(MSR_IA32_XSS, host_xss); | |
829 | } | |
830 | ||
42bdf991 | 831 | } |
139a12cf | 832 | EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state); |
42bdf991 | 833 | |
69b0049a | 834 | static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) |
2acf923e | 835 | { |
56c103ec LJ |
836 | u64 xcr0 = xcr; |
837 | u64 old_xcr0 = vcpu->arch.xcr0; | |
46c34cb0 | 838 | u64 valid_bits; |
2acf923e DC |
839 | |
840 | /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ | |
841 | if (index != XCR_XFEATURE_ENABLED_MASK) | |
842 | return 1; | |
d91cab78 | 843 | if (!(xcr0 & XFEATURE_MASK_FP)) |
2acf923e | 844 | return 1; |
d91cab78 | 845 | if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) |
2acf923e | 846 | return 1; |
46c34cb0 PB |
847 | |
848 | /* | |
849 | * Do not allow the guest to set bits that we do not support | |
850 | * saving. However, xcr0 bit 0 is always set, even if the | |
851 | * emulated CPU does not support XSAVE (see fx_init). | |
852 | */ | |
d91cab78 | 853 | valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; |
46c34cb0 | 854 | if (xcr0 & ~valid_bits) |
2acf923e | 855 | return 1; |
46c34cb0 | 856 | |
d91cab78 DH |
857 | if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != |
858 | (!(xcr0 & XFEATURE_MASK_BNDCSR))) | |
390bd528 LJ |
859 | return 1; |
860 | ||
d91cab78 DH |
861 | if (xcr0 & XFEATURE_MASK_AVX512) { |
862 | if (!(xcr0 & XFEATURE_MASK_YMM)) | |
612263b3 | 863 | return 1; |
d91cab78 | 864 | if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) |
612263b3 CP |
865 | return 1; |
866 | } | |
2acf923e | 867 | vcpu->arch.xcr0 = xcr0; |
56c103ec | 868 | |
d91cab78 | 869 | if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) |
56c103ec | 870 | kvm_update_cpuid(vcpu); |
2acf923e DC |
871 | return 0; |
872 | } | |
873 | ||
874 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) | |
875 | { | |
764bcbc5 Z |
876 | if (kvm_x86_ops->get_cpl(vcpu) != 0 || |
877 | __kvm_set_xcr(vcpu, index, xcr)) { | |
2acf923e DC |
878 | kvm_inject_gp(vcpu, 0); |
879 | return 1; | |
880 | } | |
881 | return 0; | |
882 | } | |
883 | EXPORT_SYMBOL_GPL(kvm_set_xcr); | |
884 | ||
345599f9 SC |
885 | #define __cr4_reserved_bits(__cpu_has, __c) \ |
886 | ({ \ | |
887 | u64 __reserved_bits = CR4_RESERVED_BITS; \ | |
888 | \ | |
889 | if (!__cpu_has(__c, X86_FEATURE_XSAVE)) \ | |
890 | __reserved_bits |= X86_CR4_OSXSAVE; \ | |
891 | if (!__cpu_has(__c, X86_FEATURE_SMEP)) \ | |
892 | __reserved_bits |= X86_CR4_SMEP; \ | |
893 | if (!__cpu_has(__c, X86_FEATURE_SMAP)) \ | |
894 | __reserved_bits |= X86_CR4_SMAP; \ | |
895 | if (!__cpu_has(__c, X86_FEATURE_FSGSBASE)) \ | |
896 | __reserved_bits |= X86_CR4_FSGSBASE; \ | |
897 | if (!__cpu_has(__c, X86_FEATURE_PKU)) \ | |
898 | __reserved_bits |= X86_CR4_PKE; \ | |
899 | if (!__cpu_has(__c, X86_FEATURE_LA57)) \ | |
900 | __reserved_bits |= X86_CR4_LA57; \ | |
901 | __reserved_bits; \ | |
902 | }) | |
a03490ed | 903 | |
b11306b5 SC |
904 | static u64 kvm_host_cr4_reserved_bits(struct cpuinfo_x86 *c) |
905 | { | |
345599f9 | 906 | u64 reserved_bits = __cr4_reserved_bits(cpu_has, c); |
2acf923e | 907 | |
87382003 | 908 | if (cpuid_ecx(0x7) & feature_bit(LA57)) |
345599f9 | 909 | reserved_bits &= ~X86_CR4_LA57; |
c68b734f | 910 | |
345599f9 SC |
911 | if (kvm_x86_ops->umip_emulated()) |
912 | reserved_bits &= ~X86_CR4_UMIP; | |
97ec8c06 | 913 | |
b11306b5 SC |
914 | return reserved_bits; |
915 | } | |
74dc2b4f | 916 | |
3ca94192 | 917 | static int kvm_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 918 | { |
b11306b5 | 919 | if (cr4 & cr4_reserved_bits) |
3ca94192 | 920 | return -EINVAL; |
b9baba86 | 921 | |
345599f9 | 922 | if (cr4 & __cr4_reserved_bits(guest_cpuid_has, vcpu)) |
3ca94192 WL |
923 | return -EINVAL; |
924 | ||
925 | return 0; | |
926 | } | |
927 | ||
928 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
929 | { | |
930 | unsigned long old_cr4 = kvm_read_cr4(vcpu); | |
931 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | | |
932 | X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE; | |
933 | ||
934 | if (kvm_valid_cr4(vcpu, cr4)) | |
ae3e61e1 PB |
935 | return 1; |
936 | ||
a03490ed | 937 | if (is_long_mode(vcpu)) { |
0f12244f GN |
938 | if (!(cr4 & X86_CR4_PAE)) |
939 | return 1; | |
a2edf57f AK |
940 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
941 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
9f8fe504 AK |
942 | && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
943 | kvm_read_cr3(vcpu))) | |
0f12244f GN |
944 | return 1; |
945 | ||
ad756a16 | 946 | if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { |
d6321d49 | 947 | if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) |
ad756a16 MJ |
948 | return 1; |
949 | ||
950 | /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ | |
951 | if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) | |
952 | return 1; | |
953 | } | |
954 | ||
5e1746d6 | 955 | if (kvm_x86_ops->set_cr4(vcpu, cr4)) |
0f12244f | 956 | return 1; |
a03490ed | 957 | |
ad756a16 MJ |
958 | if (((cr4 ^ old_cr4) & pdptr_bits) || |
959 | (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) | |
aad82703 | 960 | kvm_mmu_reset_context(vcpu); |
0f12244f | 961 | |
b9baba86 | 962 | if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE)) |
00b27a3e | 963 | kvm_update_cpuid(vcpu); |
2acf923e | 964 | |
0f12244f GN |
965 | return 0; |
966 | } | |
2d3ad1f4 | 967 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 968 | |
2390218b | 969 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 970 | { |
ade61e28 | 971 | bool skip_tlb_flush = false; |
ac146235 | 972 | #ifdef CONFIG_X86_64 |
c19986fe JS |
973 | bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); |
974 | ||
ade61e28 | 975 | if (pcid_enabled) { |
208320ba JS |
976 | skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; |
977 | cr3 &= ~X86_CR3_PCID_NOFLUSH; | |
ade61e28 | 978 | } |
ac146235 | 979 | #endif |
9d88fca7 | 980 | |
9f8fe504 | 981 | if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { |
956bf353 JS |
982 | if (!skip_tlb_flush) { |
983 | kvm_mmu_sync_roots(vcpu); | |
ade61e28 | 984 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
956bf353 | 985 | } |
0f12244f | 986 | return 0; |
d835dfec AK |
987 | } |
988 | ||
d1cd3ce9 | 989 | if (is_long_mode(vcpu) && |
a780a3ea | 990 | (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63))) |
d1cd3ce9 | 991 | return 1; |
bf03d4f9 PB |
992 | else if (is_pae_paging(vcpu) && |
993 | !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) | |
346874c9 | 994 | return 1; |
a03490ed | 995 | |
ade61e28 | 996 | kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush); |
0f12244f | 997 | vcpu->arch.cr3 = cr3; |
cb3c1e2f | 998 | kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); |
7c390d35 | 999 | |
0f12244f GN |
1000 | return 0; |
1001 | } | |
2d3ad1f4 | 1002 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 1003 | |
eea1cff9 | 1004 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed | 1005 | { |
0f12244f GN |
1006 | if (cr8 & CR8_RESERVED_BITS) |
1007 | return 1; | |
35754c98 | 1008 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
1009 | kvm_lapic_set_tpr(vcpu, cr8); |
1010 | else | |
ad312c7c | 1011 | vcpu->arch.cr8 = cr8; |
0f12244f GN |
1012 | return 0; |
1013 | } | |
2d3ad1f4 | 1014 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 1015 | |
2d3ad1f4 | 1016 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed | 1017 | { |
35754c98 | 1018 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
1019 | return kvm_lapic_get_cr8(vcpu); |
1020 | else | |
ad312c7c | 1021 | return vcpu->arch.cr8; |
a03490ed | 1022 | } |
2d3ad1f4 | 1023 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 1024 | |
ae561ede NA |
1025 | static void kvm_update_dr0123(struct kvm_vcpu *vcpu) |
1026 | { | |
1027 | int i; | |
1028 | ||
1029 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
1030 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
1031 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
1032 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; | |
1033 | } | |
1034 | } | |
1035 | ||
73aaf249 JK |
1036 | static void kvm_update_dr6(struct kvm_vcpu *vcpu) |
1037 | { | |
1038 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
1039 | kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); | |
1040 | } | |
1041 | ||
c8639010 JK |
1042 | static void kvm_update_dr7(struct kvm_vcpu *vcpu) |
1043 | { | |
1044 | unsigned long dr7; | |
1045 | ||
1046 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
1047 | dr7 = vcpu->arch.guest_debug_dr7; | |
1048 | else | |
1049 | dr7 = vcpu->arch.dr7; | |
1050 | kvm_x86_ops->set_dr7(vcpu, dr7); | |
360b948d PB |
1051 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; |
1052 | if (dr7 & DR7_BP_EN_MASK) | |
1053 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; | |
c8639010 JK |
1054 | } |
1055 | ||
6f43ed01 NA |
1056 | static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) |
1057 | { | |
1058 | u64 fixed = DR6_FIXED_1; | |
1059 | ||
d6321d49 | 1060 | if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) |
6f43ed01 NA |
1061 | fixed |= DR6_RTM; |
1062 | return fixed; | |
1063 | } | |
1064 | ||
338dbc97 | 1065 | static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) |
020df079 | 1066 | { |
ea740059 MP |
1067 | size_t size = ARRAY_SIZE(vcpu->arch.db); |
1068 | ||
020df079 GN |
1069 | switch (dr) { |
1070 | case 0 ... 3: | |
ea740059 | 1071 | vcpu->arch.db[array_index_nospec(dr, size)] = val; |
020df079 GN |
1072 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) |
1073 | vcpu->arch.eff_db[dr] = val; | |
1074 | break; | |
1075 | case 4: | |
020df079 GN |
1076 | /* fall through */ |
1077 | case 6: | |
338dbc97 GN |
1078 | if (val & 0xffffffff00000000ULL) |
1079 | return -1; /* #GP */ | |
6f43ed01 | 1080 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); |
73aaf249 | 1081 | kvm_update_dr6(vcpu); |
020df079 GN |
1082 | break; |
1083 | case 5: | |
020df079 GN |
1084 | /* fall through */ |
1085 | default: /* 7 */ | |
b91991bf | 1086 | if (!kvm_dr7_valid(val)) |
338dbc97 | 1087 | return -1; /* #GP */ |
020df079 | 1088 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; |
c8639010 | 1089 | kvm_update_dr7(vcpu); |
020df079 GN |
1090 | break; |
1091 | } | |
1092 | ||
1093 | return 0; | |
1094 | } | |
338dbc97 GN |
1095 | |
1096 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) | |
1097 | { | |
16f8a6f9 | 1098 | if (__kvm_set_dr(vcpu, dr, val)) { |
338dbc97 | 1099 | kvm_inject_gp(vcpu, 0); |
16f8a6f9 NA |
1100 | return 1; |
1101 | } | |
1102 | return 0; | |
338dbc97 | 1103 | } |
020df079 GN |
1104 | EXPORT_SYMBOL_GPL(kvm_set_dr); |
1105 | ||
16f8a6f9 | 1106 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) |
020df079 | 1107 | { |
ea740059 MP |
1108 | size_t size = ARRAY_SIZE(vcpu->arch.db); |
1109 | ||
020df079 GN |
1110 | switch (dr) { |
1111 | case 0 ... 3: | |
ea740059 | 1112 | *val = vcpu->arch.db[array_index_nospec(dr, size)]; |
020df079 GN |
1113 | break; |
1114 | case 4: | |
020df079 GN |
1115 | /* fall through */ |
1116 | case 6: | |
73aaf249 JK |
1117 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) |
1118 | *val = vcpu->arch.dr6; | |
1119 | else | |
1120 | *val = kvm_x86_ops->get_dr6(vcpu); | |
020df079 GN |
1121 | break; |
1122 | case 5: | |
020df079 GN |
1123 | /* fall through */ |
1124 | default: /* 7 */ | |
1125 | *val = vcpu->arch.dr7; | |
1126 | break; | |
1127 | } | |
338dbc97 GN |
1128 | return 0; |
1129 | } | |
020df079 GN |
1130 | EXPORT_SYMBOL_GPL(kvm_get_dr); |
1131 | ||
022cd0e8 AK |
1132 | bool kvm_rdpmc(struct kvm_vcpu *vcpu) |
1133 | { | |
de3cd117 | 1134 | u32 ecx = kvm_rcx_read(vcpu); |
022cd0e8 AK |
1135 | u64 data; |
1136 | int err; | |
1137 | ||
c6702c9d | 1138 | err = kvm_pmu_rdpmc(vcpu, ecx, &data); |
022cd0e8 AK |
1139 | if (err) |
1140 | return err; | |
de3cd117 SC |
1141 | kvm_rax_write(vcpu, (u32)data); |
1142 | kvm_rdx_write(vcpu, data >> 32); | |
022cd0e8 AK |
1143 | return err; |
1144 | } | |
1145 | EXPORT_SYMBOL_GPL(kvm_rdpmc); | |
1146 | ||
043405e1 CO |
1147 | /* |
1148 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
1149 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
1150 | * | |
7a5ee6ed CQ |
1151 | * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) |
1152 | * extract the supported MSRs from the related const lists. | |
1153 | * msrs_to_save is selected from the msrs_to_save_all to reflect the | |
e3267cbb | 1154 | * capabilities of the host cpu. This capabilities test skips MSRs that are |
7a5ee6ed | 1155 | * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs |
62ef68bb | 1156 | * may depend on host virtualization features rather than host cpu features. |
043405e1 | 1157 | */ |
e3267cbb | 1158 | |
7a5ee6ed | 1159 | static const u32 msrs_to_save_all[] = { |
043405e1 | 1160 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, |
8c06585d | 1161 | MSR_STAR, |
043405e1 CO |
1162 | #ifdef CONFIG_X86_64 |
1163 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
1164 | #endif | |
b3897a49 | 1165 | MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, |
32ad73db | 1166 | MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, |
2bdb76c0 | 1167 | MSR_IA32_SPEC_CTRL, |
bf8c55d8 CP |
1168 | MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, |
1169 | MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, | |
1170 | MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, | |
1171 | MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, | |
1172 | MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, | |
1173 | MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, | |
6e3ba4ab TX |
1174 | MSR_IA32_UMWAIT_CONTROL, |
1175 | ||
e2ada66e JM |
1176 | MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, |
1177 | MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3, | |
1178 | MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, | |
1179 | MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, | |
1180 | MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, | |
1181 | MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, | |
1182 | MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, | |
1183 | MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, | |
1184 | MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9, | |
1185 | MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11, | |
1186 | MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13, | |
1187 | MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15, | |
1188 | MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17, | |
e2ada66e JM |
1189 | MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, |
1190 | MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, | |
1191 | MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, | |
1192 | MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, | |
1193 | MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9, | |
1194 | MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11, | |
1195 | MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13, | |
1196 | MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15, | |
1197 | MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17, | |
043405e1 CO |
1198 | }; |
1199 | ||
7a5ee6ed | 1200 | static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)]; |
043405e1 CO |
1201 | static unsigned num_msrs_to_save; |
1202 | ||
7a5ee6ed | 1203 | static const u32 emulated_msrs_all[] = { |
62ef68bb PB |
1204 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, |
1205 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, | |
1206 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, | |
1207 | HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, | |
72c139ba | 1208 | HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, |
e7d9513b AS |
1209 | HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, |
1210 | HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, | |
e516cebb | 1211 | HV_X64_MSR_RESET, |
11c4b1ca | 1212 | HV_X64_MSR_VP_INDEX, |
9eec50b8 | 1213 | HV_X64_MSR_VP_RUNTIME, |
5c919412 | 1214 | HV_X64_MSR_SCONTROL, |
1f4b34f8 | 1215 | HV_X64_MSR_STIMER0_CONFIG, |
d4abc577 | 1216 | HV_X64_MSR_VP_ASSIST_PAGE, |
a2e164e7 VK |
1217 | HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, |
1218 | HV_X64_MSR_TSC_EMULATION_STATUS, | |
1219 | ||
1220 | MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, | |
62ef68bb PB |
1221 | MSR_KVM_PV_EOI_EN, |
1222 | ||
ba904635 | 1223 | MSR_IA32_TSC_ADJUST, |
a3e06bbe | 1224 | MSR_IA32_TSCDEADLINE, |
2bdb76c0 | 1225 | MSR_IA32_ARCH_CAPABILITIES, |
043405e1 | 1226 | MSR_IA32_MISC_ENABLE, |
908e75f3 AK |
1227 | MSR_IA32_MCG_STATUS, |
1228 | MSR_IA32_MCG_CTL, | |
c45dcc71 | 1229 | MSR_IA32_MCG_EXT_CTL, |
64d60670 | 1230 | MSR_IA32_SMBASE, |
52797bf9 | 1231 | MSR_SMI_COUNT, |
db2336a8 KH |
1232 | MSR_PLATFORM_INFO, |
1233 | MSR_MISC_FEATURES_ENABLES, | |
bc226f07 | 1234 | MSR_AMD64_VIRT_SPEC_CTRL, |
6c6a2ab9 | 1235 | MSR_IA32_POWER_CTL, |
99634e3e | 1236 | MSR_IA32_UCODE_REV, |
191c8137 | 1237 | |
95c5c7c7 PB |
1238 | /* |
1239 | * The following list leaves out MSRs whose values are determined | |
1240 | * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs. | |
1241 | * We always support the "true" VMX control MSRs, even if the host | |
1242 | * processor does not, so I am putting these registers here rather | |
7a5ee6ed | 1243 | * than in msrs_to_save_all. |
95c5c7c7 PB |
1244 | */ |
1245 | MSR_IA32_VMX_BASIC, | |
1246 | MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
1247 | MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
1248 | MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
1249 | MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
1250 | MSR_IA32_VMX_MISC, | |
1251 | MSR_IA32_VMX_CR0_FIXED0, | |
1252 | MSR_IA32_VMX_CR4_FIXED0, | |
1253 | MSR_IA32_VMX_VMCS_ENUM, | |
1254 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
1255 | MSR_IA32_VMX_EPT_VPID_CAP, | |
1256 | MSR_IA32_VMX_VMFUNC, | |
1257 | ||
191c8137 | 1258 | MSR_K7_HWCR, |
2d5ba19b | 1259 | MSR_KVM_POLL_CONTROL, |
043405e1 CO |
1260 | }; |
1261 | ||
7a5ee6ed | 1262 | static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]; |
62ef68bb PB |
1263 | static unsigned num_emulated_msrs; |
1264 | ||
801e459a TL |
1265 | /* |
1266 | * List of msr numbers which are used to expose MSR-based features that | |
1267 | * can be used by a hypervisor to validate requested CPU features. | |
1268 | */ | |
7a5ee6ed | 1269 | static const u32 msr_based_features_all[] = { |
1389309c PB |
1270 | MSR_IA32_VMX_BASIC, |
1271 | MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
1272 | MSR_IA32_VMX_PINBASED_CTLS, | |
1273 | MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
1274 | MSR_IA32_VMX_PROCBASED_CTLS, | |
1275 | MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
1276 | MSR_IA32_VMX_EXIT_CTLS, | |
1277 | MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
1278 | MSR_IA32_VMX_ENTRY_CTLS, | |
1279 | MSR_IA32_VMX_MISC, | |
1280 | MSR_IA32_VMX_CR0_FIXED0, | |
1281 | MSR_IA32_VMX_CR0_FIXED1, | |
1282 | MSR_IA32_VMX_CR4_FIXED0, | |
1283 | MSR_IA32_VMX_CR4_FIXED1, | |
1284 | MSR_IA32_VMX_VMCS_ENUM, | |
1285 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
1286 | MSR_IA32_VMX_EPT_VPID_CAP, | |
1287 | MSR_IA32_VMX_VMFUNC, | |
1288 | ||
d1d93fa9 | 1289 | MSR_F10H_DECFG, |
518e7b94 | 1290 | MSR_IA32_UCODE_REV, |
cd283252 | 1291 | MSR_IA32_ARCH_CAPABILITIES, |
801e459a TL |
1292 | }; |
1293 | ||
7a5ee6ed | 1294 | static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)]; |
801e459a TL |
1295 | static unsigned int num_msr_based_features; |
1296 | ||
4d22c17c | 1297 | static u64 kvm_get_arch_capabilities(void) |
5b76a3cf | 1298 | { |
4d22c17c | 1299 | u64 data = 0; |
5b76a3cf | 1300 | |
4d22c17c XL |
1301 | if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) |
1302 | rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data); | |
5b76a3cf | 1303 | |
b8e8c830 PB |
1304 | /* |
1305 | * If nx_huge_pages is enabled, KVM's shadow paging will ensure that | |
1306 | * the nested hypervisor runs with NX huge pages. If it is not, | |
1307 | * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other | |
1308 | * L1 guests, so it need not worry about its own (L2) guests. | |
1309 | */ | |
1310 | data |= ARCH_CAP_PSCHANGE_MC_NO; | |
1311 | ||
5b76a3cf PB |
1312 | /* |
1313 | * If we're doing cache flushes (either "always" or "cond") | |
1314 | * we will do one whenever the guest does a vmlaunch/vmresume. | |
1315 | * If an outer hypervisor is doing the cache flush for us | |
1316 | * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that | |
1317 | * capability to the guest too, and if EPT is disabled we're not | |
1318 | * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will | |
1319 | * require a nested hypervisor to do a flush of its own. | |
1320 | */ | |
1321 | if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) | |
1322 | data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; | |
1323 | ||
0c54914d PB |
1324 | if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) |
1325 | data |= ARCH_CAP_RDCL_NO; | |
1326 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
1327 | data |= ARCH_CAP_SSB_NO; | |
1328 | if (!boot_cpu_has_bug(X86_BUG_MDS)) | |
1329 | data |= ARCH_CAP_MDS_NO; | |
1330 | ||
e1d38b63 | 1331 | /* |
c11f83e0 PB |
1332 | * On TAA affected systems: |
1333 | * - nothing to do if TSX is disabled on the host. | |
1334 | * - we emulate TSX_CTRL if present on the host. | |
1335 | * This lets the guest use VERW to clear CPU buffers. | |
e1d38b63 | 1336 | */ |
cbbaa272 | 1337 | if (!boot_cpu_has(X86_FEATURE_RTM)) |
c11f83e0 | 1338 | data &= ~(ARCH_CAP_TAA_NO | ARCH_CAP_TSX_CTRL_MSR); |
cbbaa272 PB |
1339 | else if (!boot_cpu_has_bug(X86_BUG_TAA)) |
1340 | data |= ARCH_CAP_TAA_NO; | |
e1d38b63 | 1341 | |
5b76a3cf PB |
1342 | return data; |
1343 | } | |
5b76a3cf | 1344 | |
66421c1e WL |
1345 | static int kvm_get_msr_feature(struct kvm_msr_entry *msr) |
1346 | { | |
1347 | switch (msr->index) { | |
cd283252 | 1348 | case MSR_IA32_ARCH_CAPABILITIES: |
5b76a3cf PB |
1349 | msr->data = kvm_get_arch_capabilities(); |
1350 | break; | |
1351 | case MSR_IA32_UCODE_REV: | |
cd283252 | 1352 | rdmsrl_safe(msr->index, &msr->data); |
518e7b94 | 1353 | break; |
66421c1e WL |
1354 | default: |
1355 | if (kvm_x86_ops->get_msr_feature(msr)) | |
1356 | return 1; | |
1357 | } | |
1358 | return 0; | |
1359 | } | |
1360 | ||
801e459a TL |
1361 | static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) |
1362 | { | |
1363 | struct kvm_msr_entry msr; | |
66421c1e | 1364 | int r; |
801e459a TL |
1365 | |
1366 | msr.index = index; | |
66421c1e WL |
1367 | r = kvm_get_msr_feature(&msr); |
1368 | if (r) | |
1369 | return r; | |
801e459a TL |
1370 | |
1371 | *data = msr.data; | |
1372 | ||
1373 | return 0; | |
1374 | } | |
1375 | ||
11988499 | 1376 | static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) |
15c4a640 | 1377 | { |
1b4d56b8 | 1378 | if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) |
11988499 | 1379 | return false; |
1b2fd70c | 1380 | |
1b4d56b8 | 1381 | if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) |
11988499 | 1382 | return false; |
d8017474 | 1383 | |
0a629563 SC |
1384 | if (efer & (EFER_LME | EFER_LMA) && |
1385 | !guest_cpuid_has(vcpu, X86_FEATURE_LM)) | |
1386 | return false; | |
1387 | ||
1388 | if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) | |
1389 | return false; | |
d8017474 | 1390 | |
384bb783 | 1391 | return true; |
11988499 SC |
1392 | |
1393 | } | |
1394 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) | |
1395 | { | |
1396 | if (efer & efer_reserved_bits) | |
1397 | return false; | |
1398 | ||
1399 | return __kvm_valid_efer(vcpu, efer); | |
384bb783 JK |
1400 | } |
1401 | EXPORT_SYMBOL_GPL(kvm_valid_efer); | |
1402 | ||
11988499 | 1403 | static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
384bb783 JK |
1404 | { |
1405 | u64 old_efer = vcpu->arch.efer; | |
11988499 | 1406 | u64 efer = msr_info->data; |
384bb783 | 1407 | |
11988499 | 1408 | if (efer & efer_reserved_bits) |
66f61c92 | 1409 | return 1; |
384bb783 | 1410 | |
11988499 SC |
1411 | if (!msr_info->host_initiated) { |
1412 | if (!__kvm_valid_efer(vcpu, efer)) | |
1413 | return 1; | |
1414 | ||
1415 | if (is_paging(vcpu) && | |
1416 | (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) | |
1417 | return 1; | |
1418 | } | |
384bb783 | 1419 | |
15c4a640 | 1420 | efer &= ~EFER_LMA; |
f6801dff | 1421 | efer |= vcpu->arch.efer & EFER_LMA; |
15c4a640 | 1422 | |
a3d204e2 SY |
1423 | kvm_x86_ops->set_efer(vcpu, efer); |
1424 | ||
aad82703 SY |
1425 | /* Update reserved bits */ |
1426 | if ((efer ^ old_efer) & EFER_NX) | |
1427 | kvm_mmu_reset_context(vcpu); | |
1428 | ||
b69e8cae | 1429 | return 0; |
15c4a640 CO |
1430 | } |
1431 | ||
f2b4b7dd JR |
1432 | void kvm_enable_efer_bits(u64 mask) |
1433 | { | |
1434 | efer_reserved_bits &= ~mask; | |
1435 | } | |
1436 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
1437 | ||
15c4a640 | 1438 | /* |
f20935d8 SC |
1439 | * Write @data into the MSR specified by @index. Select MSR specific fault |
1440 | * checks are bypassed if @host_initiated is %true. | |
15c4a640 CO |
1441 | * Returns 0 on success, non-0 otherwise. |
1442 | * Assumes vcpu_load() was already called. | |
1443 | */ | |
f20935d8 SC |
1444 | static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, |
1445 | bool host_initiated) | |
15c4a640 | 1446 | { |
f20935d8 SC |
1447 | struct msr_data msr; |
1448 | ||
1449 | switch (index) { | |
854e8bb1 NA |
1450 | case MSR_FS_BASE: |
1451 | case MSR_GS_BASE: | |
1452 | case MSR_KERNEL_GS_BASE: | |
1453 | case MSR_CSTAR: | |
1454 | case MSR_LSTAR: | |
f20935d8 | 1455 | if (is_noncanonical_address(data, vcpu)) |
854e8bb1 NA |
1456 | return 1; |
1457 | break; | |
1458 | case MSR_IA32_SYSENTER_EIP: | |
1459 | case MSR_IA32_SYSENTER_ESP: | |
1460 | /* | |
1461 | * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if | |
1462 | * non-canonical address is written on Intel but not on | |
1463 | * AMD (which ignores the top 32-bits, because it does | |
1464 | * not implement 64-bit SYSENTER). | |
1465 | * | |
1466 | * 64-bit code should hence be able to write a non-canonical | |
1467 | * value on AMD. Making the address canonical ensures that | |
1468 | * vmentry does not fail on Intel after writing a non-canonical | |
1469 | * value, and that something deterministic happens if the guest | |
1470 | * invokes 64-bit SYSENTER. | |
1471 | */ | |
f20935d8 | 1472 | data = get_canonical(data, vcpu_virt_addr_bits(vcpu)); |
854e8bb1 | 1473 | } |
f20935d8 SC |
1474 | |
1475 | msr.data = data; | |
1476 | msr.index = index; | |
1477 | msr.host_initiated = host_initiated; | |
1478 | ||
1479 | return kvm_x86_ops->set_msr(vcpu, &msr); | |
15c4a640 CO |
1480 | } |
1481 | ||
313a3dc7 | 1482 | /* |
f20935d8 SC |
1483 | * Read the MSR specified by @index into @data. Select MSR specific fault |
1484 | * checks are bypassed if @host_initiated is %true. | |
1485 | * Returns 0 on success, non-0 otherwise. | |
1486 | * Assumes vcpu_load() was already called. | |
313a3dc7 | 1487 | */ |
edef5c36 PB |
1488 | int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, |
1489 | bool host_initiated) | |
609e36d3 PB |
1490 | { |
1491 | struct msr_data msr; | |
f20935d8 | 1492 | int ret; |
609e36d3 PB |
1493 | |
1494 | msr.index = index; | |
f20935d8 | 1495 | msr.host_initiated = host_initiated; |
609e36d3 | 1496 | |
f20935d8 SC |
1497 | ret = kvm_x86_ops->get_msr(vcpu, &msr); |
1498 | if (!ret) | |
1499 | *data = msr.data; | |
1500 | return ret; | |
609e36d3 PB |
1501 | } |
1502 | ||
f20935d8 | 1503 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) |
313a3dc7 | 1504 | { |
f20935d8 SC |
1505 | return __kvm_get_msr(vcpu, index, data, false); |
1506 | } | |
1507 | EXPORT_SYMBOL_GPL(kvm_get_msr); | |
8fe8ab46 | 1508 | |
f20935d8 SC |
1509 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) |
1510 | { | |
1511 | return __kvm_set_msr(vcpu, index, data, false); | |
1512 | } | |
1513 | EXPORT_SYMBOL_GPL(kvm_set_msr); | |
1514 | ||
1edce0a9 SC |
1515 | int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) |
1516 | { | |
1517 | u32 ecx = kvm_rcx_read(vcpu); | |
1518 | u64 data; | |
1519 | ||
1520 | if (kvm_get_msr(vcpu, ecx, &data)) { | |
1521 | trace_kvm_msr_read_ex(ecx); | |
1522 | kvm_inject_gp(vcpu, 0); | |
1523 | return 1; | |
1524 | } | |
1525 | ||
1526 | trace_kvm_msr_read(ecx, data); | |
1527 | ||
1528 | kvm_rax_write(vcpu, data & -1u); | |
1529 | kvm_rdx_write(vcpu, (data >> 32) & -1u); | |
1530 | return kvm_skip_emulated_instruction(vcpu); | |
1531 | } | |
1532 | EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); | |
1533 | ||
1534 | int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) | |
1535 | { | |
1536 | u32 ecx = kvm_rcx_read(vcpu); | |
1537 | u64 data = kvm_read_edx_eax(vcpu); | |
1538 | ||
1539 | if (kvm_set_msr(vcpu, ecx, data)) { | |
1540 | trace_kvm_msr_write_ex(ecx, data); | |
1541 | kvm_inject_gp(vcpu, 0); | |
1542 | return 1; | |
1543 | } | |
1544 | ||
1545 | trace_kvm_msr_write(ecx, data); | |
1546 | return kvm_skip_emulated_instruction(vcpu); | |
1547 | } | |
1548 | EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); | |
1549 | ||
1e9e2622 WL |
1550 | /* |
1551 | * The fast path for frequent and performance sensitive wrmsr emulation, | |
1552 | * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces | |
1553 | * the latency of virtual IPI by avoiding the expensive bits of transitioning | |
1554 | * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the | |
1555 | * other cases which must be called after interrupts are enabled on the host. | |
1556 | */ | |
1557 | static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data) | |
1558 | { | |
1559 | if (lapic_in_kernel(vcpu) && apic_x2apic_mode(vcpu->arch.apic) && | |
1560 | ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) && | |
1561 | ((data & APIC_MODE_MASK) == APIC_DM_FIXED)) { | |
1562 | ||
1563 | kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32)); | |
1564 | return kvm_lapic_reg_write(vcpu->arch.apic, APIC_ICR, (u32)data); | |
1565 | } | |
1566 | ||
1567 | return 1; | |
1568 | } | |
1569 | ||
1570 | enum exit_fastpath_completion handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu) | |
1571 | { | |
1572 | u32 msr = kvm_rcx_read(vcpu); | |
1573 | u64 data = kvm_read_edx_eax(vcpu); | |
1574 | int ret = 0; | |
1575 | ||
1576 | switch (msr) { | |
1577 | case APIC_BASE_MSR + (APIC_ICR >> 4): | |
1578 | ret = handle_fastpath_set_x2apic_icr_irqoff(vcpu, data); | |
1579 | break; | |
1580 | default: | |
1581 | return EXIT_FASTPATH_NONE; | |
1582 | } | |
1583 | ||
1584 | if (!ret) { | |
1585 | trace_kvm_msr_write(msr, data); | |
1586 | return EXIT_FASTPATH_SKIP_EMUL_INS; | |
1587 | } | |
1588 | ||
1589 | return EXIT_FASTPATH_NONE; | |
1590 | } | |
1591 | EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); | |
1592 | ||
f20935d8 SC |
1593 | /* |
1594 | * Adapt set_msr() to msr_io()'s calling convention | |
1595 | */ | |
1596 | static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
1597 | { | |
1598 | return __kvm_get_msr(vcpu, index, data, true); | |
1599 | } | |
1600 | ||
1601 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
1602 | { | |
1603 | return __kvm_set_msr(vcpu, index, *data, true); | |
313a3dc7 CO |
1604 | } |
1605 | ||
16e8d74d | 1606 | #ifdef CONFIG_X86_64 |
53fafdbb MT |
1607 | struct pvclock_clock { |
1608 | int vclock_mode; | |
1609 | u64 cycle_last; | |
1610 | u64 mask; | |
1611 | u32 mult; | |
1612 | u32 shift; | |
1613 | }; | |
1614 | ||
16e8d74d MT |
1615 | struct pvclock_gtod_data { |
1616 | seqcount_t seq; | |
1617 | ||
53fafdbb MT |
1618 | struct pvclock_clock clock; /* extract of a clocksource struct */ |
1619 | struct pvclock_clock raw_clock; /* extract of a clocksource struct */ | |
16e8d74d | 1620 | |
53fafdbb | 1621 | u64 boot_ns_raw; |
cbcf2dd3 TG |
1622 | u64 boot_ns; |
1623 | u64 nsec_base; | |
55dd00a7 | 1624 | u64 wall_time_sec; |
53fafdbb | 1625 | u64 monotonic_raw_nsec; |
16e8d74d MT |
1626 | }; |
1627 | ||
1628 | static struct pvclock_gtod_data pvclock_gtod_data; | |
1629 | ||
1630 | static void update_pvclock_gtod(struct timekeeper *tk) | |
1631 | { | |
1632 | struct pvclock_gtod_data *vdata = &pvclock_gtod_data; | |
53fafdbb | 1633 | u64 boot_ns, boot_ns_raw; |
cbcf2dd3 | 1634 | |
876e7881 | 1635 | boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot)); |
53fafdbb | 1636 | boot_ns_raw = ktime_to_ns(ktime_add(tk->tkr_raw.base, tk->offs_boot)); |
16e8d74d MT |
1637 | |
1638 | write_seqcount_begin(&vdata->seq); | |
1639 | ||
1640 | /* copy pvclock gtod data */ | |
876e7881 PZ |
1641 | vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode; |
1642 | vdata->clock.cycle_last = tk->tkr_mono.cycle_last; | |
1643 | vdata->clock.mask = tk->tkr_mono.mask; | |
1644 | vdata->clock.mult = tk->tkr_mono.mult; | |
1645 | vdata->clock.shift = tk->tkr_mono.shift; | |
16e8d74d | 1646 | |
53fafdbb MT |
1647 | vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->archdata.vclock_mode; |
1648 | vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last; | |
1649 | vdata->raw_clock.mask = tk->tkr_raw.mask; | |
1650 | vdata->raw_clock.mult = tk->tkr_raw.mult; | |
1651 | vdata->raw_clock.shift = tk->tkr_raw.shift; | |
1652 | ||
cbcf2dd3 | 1653 | vdata->boot_ns = boot_ns; |
876e7881 | 1654 | vdata->nsec_base = tk->tkr_mono.xtime_nsec; |
16e8d74d | 1655 | |
55dd00a7 MT |
1656 | vdata->wall_time_sec = tk->xtime_sec; |
1657 | ||
53fafdbb MT |
1658 | vdata->boot_ns_raw = boot_ns_raw; |
1659 | vdata->monotonic_raw_nsec = tk->tkr_raw.xtime_nsec; | |
1660 | ||
16e8d74d MT |
1661 | write_seqcount_end(&vdata->seq); |
1662 | } | |
1663 | #endif | |
1664 | ||
bab5bb39 NK |
1665 | void kvm_set_pending_timer(struct kvm_vcpu *vcpu) |
1666 | { | |
bab5bb39 | 1667 | kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); |
4d151bf3 | 1668 | kvm_vcpu_kick(vcpu); |
bab5bb39 | 1669 | } |
16e8d74d | 1670 | |
18068523 GOC |
1671 | static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) |
1672 | { | |
9ed3c444 AK |
1673 | int version; |
1674 | int r; | |
50d0a0f9 | 1675 | struct pvclock_wall_clock wc; |
87aeb54f | 1676 | struct timespec64 boot; |
18068523 GOC |
1677 | |
1678 | if (!wall_clock) | |
1679 | return; | |
1680 | ||
9ed3c444 AK |
1681 | r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); |
1682 | if (r) | |
1683 | return; | |
1684 | ||
1685 | if (version & 1) | |
1686 | ++version; /* first time write, random junk */ | |
1687 | ||
1688 | ++version; | |
18068523 | 1689 | |
1dab1345 NK |
1690 | if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) |
1691 | return; | |
18068523 | 1692 | |
50d0a0f9 GH |
1693 | /* |
1694 | * The guest calculates current wall clock time by adding | |
34c238a1 | 1695 | * system time (updated by kvm_guest_time_update below) to the |
50d0a0f9 GH |
1696 | * wall clock specified here. guest system time equals host |
1697 | * system time for us, thus we must fill in host boot time here. | |
1698 | */ | |
87aeb54f | 1699 | getboottime64(&boot); |
50d0a0f9 | 1700 | |
4b648665 | 1701 | if (kvm->arch.kvmclock_offset) { |
87aeb54f AB |
1702 | struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset); |
1703 | boot = timespec64_sub(boot, ts); | |
4b648665 | 1704 | } |
87aeb54f | 1705 | wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */ |
50d0a0f9 GH |
1706 | wc.nsec = boot.tv_nsec; |
1707 | wc.version = version; | |
18068523 GOC |
1708 | |
1709 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
1710 | ||
1711 | version++; | |
1712 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
1713 | } |
1714 | ||
50d0a0f9 GH |
1715 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
1716 | { | |
b51012de PB |
1717 | do_shl32_div32(dividend, divisor); |
1718 | return dividend; | |
50d0a0f9 GH |
1719 | } |
1720 | ||
3ae13faa | 1721 | static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, |
5f4e3f88 | 1722 | s8 *pshift, u32 *pmultiplier) |
50d0a0f9 | 1723 | { |
5f4e3f88 | 1724 | uint64_t scaled64; |
50d0a0f9 GH |
1725 | int32_t shift = 0; |
1726 | uint64_t tps64; | |
1727 | uint32_t tps32; | |
1728 | ||
3ae13faa PB |
1729 | tps64 = base_hz; |
1730 | scaled64 = scaled_hz; | |
50933623 | 1731 | while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { |
50d0a0f9 GH |
1732 | tps64 >>= 1; |
1733 | shift--; | |
1734 | } | |
1735 | ||
1736 | tps32 = (uint32_t)tps64; | |
50933623 JK |
1737 | while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { |
1738 | if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) | |
5f4e3f88 ZA |
1739 | scaled64 >>= 1; |
1740 | else | |
1741 | tps32 <<= 1; | |
50d0a0f9 GH |
1742 | shift++; |
1743 | } | |
1744 | ||
5f4e3f88 ZA |
1745 | *pshift = shift; |
1746 | *pmultiplier = div_frac(scaled64, tps32); | |
50d0a0f9 GH |
1747 | } |
1748 | ||
d828199e | 1749 | #ifdef CONFIG_X86_64 |
16e8d74d | 1750 | static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); |
d828199e | 1751 | #endif |
16e8d74d | 1752 | |
c8076604 | 1753 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
69b0049a | 1754 | static unsigned long max_tsc_khz; |
c8076604 | 1755 | |
cc578287 | 1756 | static u32 adjust_tsc_khz(u32 khz, s32 ppm) |
1e993611 | 1757 | { |
cc578287 ZA |
1758 | u64 v = (u64)khz * (1000000 + ppm); |
1759 | do_div(v, 1000000); | |
1760 | return v; | |
1e993611 JR |
1761 | } |
1762 | ||
381d585c HZ |
1763 | static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) |
1764 | { | |
1765 | u64 ratio; | |
1766 | ||
1767 | /* Guest TSC same frequency as host TSC? */ | |
1768 | if (!scale) { | |
1769 | vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; | |
1770 | return 0; | |
1771 | } | |
1772 | ||
1773 | /* TSC scaling supported? */ | |
1774 | if (!kvm_has_tsc_control) { | |
1775 | if (user_tsc_khz > tsc_khz) { | |
1776 | vcpu->arch.tsc_catchup = 1; | |
1777 | vcpu->arch.tsc_always_catchup = 1; | |
1778 | return 0; | |
1779 | } else { | |
3f16a5c3 | 1780 | pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); |
381d585c HZ |
1781 | return -1; |
1782 | } | |
1783 | } | |
1784 | ||
1785 | /* TSC scaling required - calculate ratio */ | |
1786 | ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, | |
1787 | user_tsc_khz, tsc_khz); | |
1788 | ||
1789 | if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { | |
3f16a5c3 PB |
1790 | pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", |
1791 | user_tsc_khz); | |
381d585c HZ |
1792 | return -1; |
1793 | } | |
1794 | ||
1795 | vcpu->arch.tsc_scaling_ratio = ratio; | |
1796 | return 0; | |
1797 | } | |
1798 | ||
4941b8cb | 1799 | static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) |
759379dd | 1800 | { |
cc578287 ZA |
1801 | u32 thresh_lo, thresh_hi; |
1802 | int use_scaling = 0; | |
217fc9cf | 1803 | |
03ba32ca | 1804 | /* tsc_khz can be zero if TSC calibration fails */ |
4941b8cb | 1805 | if (user_tsc_khz == 0) { |
ad721883 HZ |
1806 | /* set tsc_scaling_ratio to a safe value */ |
1807 | vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; | |
381d585c | 1808 | return -1; |
ad721883 | 1809 | } |
03ba32ca | 1810 | |
c285545f | 1811 | /* Compute a scale to convert nanoseconds in TSC cycles */ |
3ae13faa | 1812 | kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, |
cc578287 ZA |
1813 | &vcpu->arch.virtual_tsc_shift, |
1814 | &vcpu->arch.virtual_tsc_mult); | |
4941b8cb | 1815 | vcpu->arch.virtual_tsc_khz = user_tsc_khz; |
cc578287 ZA |
1816 | |
1817 | /* | |
1818 | * Compute the variation in TSC rate which is acceptable | |
1819 | * within the range of tolerance and decide if the | |
1820 | * rate being applied is within that bounds of the hardware | |
1821 | * rate. If so, no scaling or compensation need be done. | |
1822 | */ | |
1823 | thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); | |
1824 | thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); | |
4941b8cb PB |
1825 | if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { |
1826 | pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); | |
cc578287 ZA |
1827 | use_scaling = 1; |
1828 | } | |
4941b8cb | 1829 | return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); |
c285545f ZA |
1830 | } |
1831 | ||
1832 | static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) | |
1833 | { | |
e26101b1 | 1834 | u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, |
cc578287 ZA |
1835 | vcpu->arch.virtual_tsc_mult, |
1836 | vcpu->arch.virtual_tsc_shift); | |
e26101b1 | 1837 | tsc += vcpu->arch.this_tsc_write; |
c285545f ZA |
1838 | return tsc; |
1839 | } | |
1840 | ||
b0c39dc6 VK |
1841 | static inline int gtod_is_based_on_tsc(int mode) |
1842 | { | |
1843 | return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK; | |
1844 | } | |
1845 | ||
69b0049a | 1846 | static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) |
b48aa97e MT |
1847 | { |
1848 | #ifdef CONFIG_X86_64 | |
1849 | bool vcpus_matched; | |
b48aa97e MT |
1850 | struct kvm_arch *ka = &vcpu->kvm->arch; |
1851 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
1852 | ||
1853 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
1854 | atomic_read(&vcpu->kvm->online_vcpus)); | |
1855 | ||
7f187922 MT |
1856 | /* |
1857 | * Once the masterclock is enabled, always perform request in | |
1858 | * order to update it. | |
1859 | * | |
1860 | * In order to enable masterclock, the host clocksource must be TSC | |
1861 | * and the vcpus need to have matched TSCs. When that happens, | |
1862 | * perform request to enable masterclock. | |
1863 | */ | |
1864 | if (ka->use_master_clock || | |
b0c39dc6 | 1865 | (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) |
b48aa97e MT |
1866 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
1867 | ||
1868 | trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, | |
1869 | atomic_read(&vcpu->kvm->online_vcpus), | |
1870 | ka->use_master_clock, gtod->clock.vclock_mode); | |
1871 | #endif | |
1872 | } | |
1873 | ||
ba904635 WA |
1874 | static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) |
1875 | { | |
e79f245d | 1876 | u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu); |
ba904635 WA |
1877 | vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; |
1878 | } | |
1879 | ||
35181e86 HZ |
1880 | /* |
1881 | * Multiply tsc by a fixed point number represented by ratio. | |
1882 | * | |
1883 | * The most significant 64-N bits (mult) of ratio represent the | |
1884 | * integral part of the fixed point number; the remaining N bits | |
1885 | * (frac) represent the fractional part, ie. ratio represents a fixed | |
1886 | * point number (mult + frac * 2^(-N)). | |
1887 | * | |
1888 | * N equals to kvm_tsc_scaling_ratio_frac_bits. | |
1889 | */ | |
1890 | static inline u64 __scale_tsc(u64 ratio, u64 tsc) | |
1891 | { | |
1892 | return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); | |
1893 | } | |
1894 | ||
1895 | u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) | |
1896 | { | |
1897 | u64 _tsc = tsc; | |
1898 | u64 ratio = vcpu->arch.tsc_scaling_ratio; | |
1899 | ||
1900 | if (ratio != kvm_default_tsc_scaling_ratio) | |
1901 | _tsc = __scale_tsc(ratio, tsc); | |
1902 | ||
1903 | return _tsc; | |
1904 | } | |
1905 | EXPORT_SYMBOL_GPL(kvm_scale_tsc); | |
1906 | ||
07c1419a HZ |
1907 | static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) |
1908 | { | |
1909 | u64 tsc; | |
1910 | ||
1911 | tsc = kvm_scale_tsc(vcpu, rdtsc()); | |
1912 | ||
1913 | return target_tsc - tsc; | |
1914 | } | |
1915 | ||
4ba76538 HZ |
1916 | u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) |
1917 | { | |
e79f245d KA |
1918 | u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu); |
1919 | ||
1920 | return tsc_offset + kvm_scale_tsc(vcpu, host_tsc); | |
4ba76538 HZ |
1921 | } |
1922 | EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); | |
1923 | ||
a545ab6a LC |
1924 | static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
1925 | { | |
326e7425 | 1926 | vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset); |
a545ab6a LC |
1927 | } |
1928 | ||
b0c39dc6 VK |
1929 | static inline bool kvm_check_tsc_unstable(void) |
1930 | { | |
1931 | #ifdef CONFIG_X86_64 | |
1932 | /* | |
1933 | * TSC is marked unstable when we're running on Hyper-V, | |
1934 | * 'TSC page' clocksource is good. | |
1935 | */ | |
1936 | if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK) | |
1937 | return false; | |
1938 | #endif | |
1939 | return check_tsc_unstable(); | |
1940 | } | |
1941 | ||
8fe8ab46 | 1942 | void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) |
99e3e30a ZA |
1943 | { |
1944 | struct kvm *kvm = vcpu->kvm; | |
f38e098f | 1945 | u64 offset, ns, elapsed; |
99e3e30a | 1946 | unsigned long flags; |
b48aa97e | 1947 | bool matched; |
0d3da0d2 | 1948 | bool already_matched; |
8fe8ab46 | 1949 | u64 data = msr->data; |
c5e8ec8e | 1950 | bool synchronizing = false; |
99e3e30a | 1951 | |
038f8c11 | 1952 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); |
07c1419a | 1953 | offset = kvm_compute_tsc_offset(vcpu, data); |
9285ec4c | 1954 | ns = ktime_get_boottime_ns(); |
f38e098f | 1955 | elapsed = ns - kvm->arch.last_tsc_nsec; |
5d3cb0f6 | 1956 | |
03ba32ca | 1957 | if (vcpu->arch.virtual_tsc_khz) { |
bd8fab39 DP |
1958 | if (data == 0 && msr->host_initiated) { |
1959 | /* | |
1960 | * detection of vcpu initialization -- need to sync | |
1961 | * with other vCPUs. This particularly helps to keep | |
1962 | * kvm_clock stable after CPU hotplug | |
1963 | */ | |
1964 | synchronizing = true; | |
1965 | } else { | |
1966 | u64 tsc_exp = kvm->arch.last_tsc_write + | |
1967 | nsec_to_cycles(vcpu, elapsed); | |
1968 | u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; | |
1969 | /* | |
1970 | * Special case: TSC write with a small delta (1 second) | |
1971 | * of virtual cycle time against real time is | |
1972 | * interpreted as an attempt to synchronize the CPU. | |
1973 | */ | |
1974 | synchronizing = data < tsc_exp + tsc_hz && | |
1975 | data + tsc_hz > tsc_exp; | |
1976 | } | |
c5e8ec8e | 1977 | } |
f38e098f ZA |
1978 | |
1979 | /* | |
5d3cb0f6 ZA |
1980 | * For a reliable TSC, we can match TSC offsets, and for an unstable |
1981 | * TSC, we add elapsed time in this computation. We could let the | |
1982 | * compensation code attempt to catch up if we fall behind, but | |
1983 | * it's better to try to match offsets from the beginning. | |
1984 | */ | |
c5e8ec8e | 1985 | if (synchronizing && |
5d3cb0f6 | 1986 | vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { |
b0c39dc6 | 1987 | if (!kvm_check_tsc_unstable()) { |
e26101b1 | 1988 | offset = kvm->arch.cur_tsc_offset; |
f38e098f | 1989 | } else { |
857e4099 | 1990 | u64 delta = nsec_to_cycles(vcpu, elapsed); |
5d3cb0f6 | 1991 | data += delta; |
07c1419a | 1992 | offset = kvm_compute_tsc_offset(vcpu, data); |
f38e098f | 1993 | } |
b48aa97e | 1994 | matched = true; |
0d3da0d2 | 1995 | already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); |
e26101b1 ZA |
1996 | } else { |
1997 | /* | |
1998 | * We split periods of matched TSC writes into generations. | |
1999 | * For each generation, we track the original measured | |
2000 | * nanosecond time, offset, and write, so if TSCs are in | |
2001 | * sync, we can match exact offset, and if not, we can match | |
4a969980 | 2002 | * exact software computation in compute_guest_tsc() |
e26101b1 ZA |
2003 | * |
2004 | * These values are tracked in kvm->arch.cur_xxx variables. | |
2005 | */ | |
2006 | kvm->arch.cur_tsc_generation++; | |
2007 | kvm->arch.cur_tsc_nsec = ns; | |
2008 | kvm->arch.cur_tsc_write = data; | |
2009 | kvm->arch.cur_tsc_offset = offset; | |
b48aa97e | 2010 | matched = false; |
f38e098f | 2011 | } |
e26101b1 ZA |
2012 | |
2013 | /* | |
2014 | * We also track th most recent recorded KHZ, write and time to | |
2015 | * allow the matching interval to be extended at each write. | |
2016 | */ | |
f38e098f ZA |
2017 | kvm->arch.last_tsc_nsec = ns; |
2018 | kvm->arch.last_tsc_write = data; | |
5d3cb0f6 | 2019 | kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; |
99e3e30a | 2020 | |
b183aa58 | 2021 | vcpu->arch.last_guest_tsc = data; |
e26101b1 ZA |
2022 | |
2023 | /* Keep track of which generation this VCPU has synchronized to */ | |
2024 | vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; | |
2025 | vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; | |
2026 | vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; | |
2027 | ||
d6321d49 | 2028 | if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) |
ba904635 | 2029 | update_ia32_tsc_adjust_msr(vcpu, offset); |
d6321d49 | 2030 | |
a545ab6a | 2031 | kvm_vcpu_write_tsc_offset(vcpu, offset); |
e26101b1 | 2032 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); |
b48aa97e MT |
2033 | |
2034 | spin_lock(&kvm->arch.pvclock_gtod_sync_lock); | |
0d3da0d2 | 2035 | if (!matched) { |
b48aa97e | 2036 | kvm->arch.nr_vcpus_matched_tsc = 0; |
0d3da0d2 TG |
2037 | } else if (!already_matched) { |
2038 | kvm->arch.nr_vcpus_matched_tsc++; | |
2039 | } | |
b48aa97e MT |
2040 | |
2041 | kvm_track_tsc_matching(vcpu); | |
2042 | spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); | |
99e3e30a | 2043 | } |
e26101b1 | 2044 | |
99e3e30a ZA |
2045 | EXPORT_SYMBOL_GPL(kvm_write_tsc); |
2046 | ||
58ea6767 HZ |
2047 | static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, |
2048 | s64 adjustment) | |
2049 | { | |
326e7425 LS |
2050 | u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu); |
2051 | kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); | |
58ea6767 HZ |
2052 | } |
2053 | ||
2054 | static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) | |
2055 | { | |
2056 | if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) | |
2057 | WARN_ON(adjustment < 0); | |
2058 | adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); | |
ea26e4ec | 2059 | adjust_tsc_offset_guest(vcpu, adjustment); |
58ea6767 HZ |
2060 | } |
2061 | ||
d828199e MT |
2062 | #ifdef CONFIG_X86_64 |
2063 | ||
a5a1d1c2 | 2064 | static u64 read_tsc(void) |
d828199e | 2065 | { |
a5a1d1c2 | 2066 | u64 ret = (u64)rdtsc_ordered(); |
03b9730b | 2067 | u64 last = pvclock_gtod_data.clock.cycle_last; |
d828199e MT |
2068 | |
2069 | if (likely(ret >= last)) | |
2070 | return ret; | |
2071 | ||
2072 | /* | |
2073 | * GCC likes to generate cmov here, but this branch is extremely | |
6a6256f9 | 2074 | * predictable (it's just a function of time and the likely is |
d828199e MT |
2075 | * very likely) and there's a data dependence, so force GCC |
2076 | * to generate a branch instead. I don't barrier() because | |
2077 | * we don't actually need a barrier, and if this function | |
2078 | * ever gets inlined it will generate worse code. | |
2079 | */ | |
2080 | asm volatile (""); | |
2081 | return last; | |
2082 | } | |
2083 | ||
53fafdbb MT |
2084 | static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, |
2085 | int *mode) | |
d828199e MT |
2086 | { |
2087 | long v; | |
b0c39dc6 VK |
2088 | u64 tsc_pg_val; |
2089 | ||
53fafdbb | 2090 | switch (clock->vclock_mode) { |
b0c39dc6 VK |
2091 | case VCLOCK_HVCLOCK: |
2092 | tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), | |
2093 | tsc_timestamp); | |
2094 | if (tsc_pg_val != U64_MAX) { | |
2095 | /* TSC page valid */ | |
2096 | *mode = VCLOCK_HVCLOCK; | |
53fafdbb MT |
2097 | v = (tsc_pg_val - clock->cycle_last) & |
2098 | clock->mask; | |
b0c39dc6 VK |
2099 | } else { |
2100 | /* TSC page invalid */ | |
2101 | *mode = VCLOCK_NONE; | |
2102 | } | |
2103 | break; | |
2104 | case VCLOCK_TSC: | |
2105 | *mode = VCLOCK_TSC; | |
2106 | *tsc_timestamp = read_tsc(); | |
53fafdbb MT |
2107 | v = (*tsc_timestamp - clock->cycle_last) & |
2108 | clock->mask; | |
b0c39dc6 VK |
2109 | break; |
2110 | default: | |
2111 | *mode = VCLOCK_NONE; | |
2112 | } | |
d828199e | 2113 | |
b0c39dc6 VK |
2114 | if (*mode == VCLOCK_NONE) |
2115 | *tsc_timestamp = v = 0; | |
d828199e | 2116 | |
53fafdbb | 2117 | return v * clock->mult; |
d828199e MT |
2118 | } |
2119 | ||
53fafdbb | 2120 | static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp) |
d828199e | 2121 | { |
cbcf2dd3 | 2122 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; |
d828199e | 2123 | unsigned long seq; |
d828199e | 2124 | int mode; |
cbcf2dd3 | 2125 | u64 ns; |
d828199e | 2126 | |
d828199e MT |
2127 | do { |
2128 | seq = read_seqcount_begin(>od->seq); | |
53fafdbb MT |
2129 | ns = gtod->monotonic_raw_nsec; |
2130 | ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode); | |
d828199e | 2131 | ns >>= gtod->clock.shift; |
53fafdbb | 2132 | ns += gtod->boot_ns_raw; |
d828199e | 2133 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); |
cbcf2dd3 | 2134 | *t = ns; |
d828199e MT |
2135 | |
2136 | return mode; | |
2137 | } | |
2138 | ||
899a31f5 | 2139 | static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) |
55dd00a7 MT |
2140 | { |
2141 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
2142 | unsigned long seq; | |
2143 | int mode; | |
2144 | u64 ns; | |
2145 | ||
2146 | do { | |
2147 | seq = read_seqcount_begin(>od->seq); | |
55dd00a7 MT |
2148 | ts->tv_sec = gtod->wall_time_sec; |
2149 | ns = gtod->nsec_base; | |
53fafdbb | 2150 | ns += vgettsc(>od->clock, tsc_timestamp, &mode); |
55dd00a7 MT |
2151 | ns >>= gtod->clock.shift; |
2152 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); | |
2153 | ||
2154 | ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); | |
2155 | ts->tv_nsec = ns; | |
2156 | ||
2157 | return mode; | |
2158 | } | |
2159 | ||
b0c39dc6 VK |
2160 | /* returns true if host is using TSC based clocksource */ |
2161 | static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) | |
d828199e | 2162 | { |
d828199e | 2163 | /* checked again under seqlock below */ |
b0c39dc6 | 2164 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
d828199e MT |
2165 | return false; |
2166 | ||
53fafdbb | 2167 | return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns, |
b0c39dc6 | 2168 | tsc_timestamp)); |
d828199e | 2169 | } |
55dd00a7 | 2170 | |
b0c39dc6 | 2171 | /* returns true if host is using TSC based clocksource */ |
899a31f5 | 2172 | static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, |
b0c39dc6 | 2173 | u64 *tsc_timestamp) |
55dd00a7 MT |
2174 | { |
2175 | /* checked again under seqlock below */ | |
b0c39dc6 | 2176 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
55dd00a7 MT |
2177 | return false; |
2178 | ||
b0c39dc6 | 2179 | return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); |
55dd00a7 | 2180 | } |
d828199e MT |
2181 | #endif |
2182 | ||
2183 | /* | |
2184 | * | |
b48aa97e MT |
2185 | * Assuming a stable TSC across physical CPUS, and a stable TSC |
2186 | * across virtual CPUs, the following condition is possible. | |
2187 | * Each numbered line represents an event visible to both | |
d828199e MT |
2188 | * CPUs at the next numbered event. |
2189 | * | |
2190 | * "timespecX" represents host monotonic time. "tscX" represents | |
2191 | * RDTSC value. | |
2192 | * | |
2193 | * VCPU0 on CPU0 | VCPU1 on CPU1 | |
2194 | * | |
2195 | * 1. read timespec0,tsc0 | |
2196 | * 2. | timespec1 = timespec0 + N | |
2197 | * | tsc1 = tsc0 + M | |
2198 | * 3. transition to guest | transition to guest | |
2199 | * 4. ret0 = timespec0 + (rdtsc - tsc0) | | |
2200 | * 5. | ret1 = timespec1 + (rdtsc - tsc1) | |
2201 | * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) | |
2202 | * | |
2203 | * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: | |
2204 | * | |
2205 | * - ret0 < ret1 | |
2206 | * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) | |
2207 | * ... | |
2208 | * - 0 < N - M => M < N | |
2209 | * | |
2210 | * That is, when timespec0 != timespec1, M < N. Unfortunately that is not | |
2211 | * always the case (the difference between two distinct xtime instances | |
2212 | * might be smaller then the difference between corresponding TSC reads, | |
2213 | * when updating guest vcpus pvclock areas). | |
2214 | * | |
2215 | * To avoid that problem, do not allow visibility of distinct | |
2216 | * system_timestamp/tsc_timestamp values simultaneously: use a master | |
2217 | * copy of host monotonic time values. Update that master copy | |
2218 | * in lockstep. | |
2219 | * | |
b48aa97e | 2220 | * Rely on synchronization of host TSCs and guest TSCs for monotonicity. |
d828199e MT |
2221 | * |
2222 | */ | |
2223 | ||
2224 | static void pvclock_update_vm_gtod_copy(struct kvm *kvm) | |
2225 | { | |
2226 | #ifdef CONFIG_X86_64 | |
2227 | struct kvm_arch *ka = &kvm->arch; | |
2228 | int vclock_mode; | |
b48aa97e MT |
2229 | bool host_tsc_clocksource, vcpus_matched; |
2230 | ||
2231 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
2232 | atomic_read(&kvm->online_vcpus)); | |
d828199e MT |
2233 | |
2234 | /* | |
2235 | * If the host uses TSC clock, then passthrough TSC as stable | |
2236 | * to the guest. | |
2237 | */ | |
b48aa97e | 2238 | host_tsc_clocksource = kvm_get_time_and_clockread( |
d828199e MT |
2239 | &ka->master_kernel_ns, |
2240 | &ka->master_cycle_now); | |
2241 | ||
16a96021 | 2242 | ka->use_master_clock = host_tsc_clocksource && vcpus_matched |
a826faf1 | 2243 | && !ka->backwards_tsc_observed |
54750f2c | 2244 | && !ka->boot_vcpu_runs_old_kvmclock; |
b48aa97e | 2245 | |
d828199e MT |
2246 | if (ka->use_master_clock) |
2247 | atomic_set(&kvm_guest_has_master_clock, 1); | |
2248 | ||
2249 | vclock_mode = pvclock_gtod_data.clock.vclock_mode; | |
b48aa97e MT |
2250 | trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, |
2251 | vcpus_matched); | |
d828199e MT |
2252 | #endif |
2253 | } | |
2254 | ||
2860c4b1 PB |
2255 | void kvm_make_mclock_inprogress_request(struct kvm *kvm) |
2256 | { | |
2257 | kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); | |
2258 | } | |
2259 | ||
2e762ff7 MT |
2260 | static void kvm_gen_update_masterclock(struct kvm *kvm) |
2261 | { | |
2262 | #ifdef CONFIG_X86_64 | |
2263 | int i; | |
2264 | struct kvm_vcpu *vcpu; | |
2265 | struct kvm_arch *ka = &kvm->arch; | |
2266 | ||
2267 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
2268 | kvm_make_mclock_inprogress_request(kvm); | |
2269 | /* no guest entries from this point */ | |
2270 | pvclock_update_vm_gtod_copy(kvm); | |
2271 | ||
2272 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 2273 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
2e762ff7 MT |
2274 | |
2275 | /* guest entries allowed */ | |
2276 | kvm_for_each_vcpu(i, vcpu, kvm) | |
72875d8a | 2277 | kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); |
2e762ff7 MT |
2278 | |
2279 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
2280 | #endif | |
2281 | } | |
2282 | ||
e891a32e | 2283 | u64 get_kvmclock_ns(struct kvm *kvm) |
108b249c | 2284 | { |
108b249c | 2285 | struct kvm_arch *ka = &kvm->arch; |
8b953440 | 2286 | struct pvclock_vcpu_time_info hv_clock; |
e2c2206a | 2287 | u64 ret; |
108b249c | 2288 | |
8b953440 PB |
2289 | spin_lock(&ka->pvclock_gtod_sync_lock); |
2290 | if (!ka->use_master_clock) { | |
2291 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
9285ec4c | 2292 | return ktime_get_boottime_ns() + ka->kvmclock_offset; |
108b249c PB |
2293 | } |
2294 | ||
8b953440 PB |
2295 | hv_clock.tsc_timestamp = ka->master_cycle_now; |
2296 | hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; | |
2297 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
2298 | ||
e2c2206a WL |
2299 | /* both __this_cpu_read() and rdtsc() should be on the same cpu */ |
2300 | get_cpu(); | |
2301 | ||
e70b57a6 WL |
2302 | if (__this_cpu_read(cpu_tsc_khz)) { |
2303 | kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, | |
2304 | &hv_clock.tsc_shift, | |
2305 | &hv_clock.tsc_to_system_mul); | |
2306 | ret = __pvclock_read_cycles(&hv_clock, rdtsc()); | |
2307 | } else | |
9285ec4c | 2308 | ret = ktime_get_boottime_ns() + ka->kvmclock_offset; |
e2c2206a WL |
2309 | |
2310 | put_cpu(); | |
2311 | ||
2312 | return ret; | |
108b249c PB |
2313 | } |
2314 | ||
0d6dd2ff PB |
2315 | static void kvm_setup_pvclock_page(struct kvm_vcpu *v) |
2316 | { | |
2317 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
2318 | struct pvclock_vcpu_time_info guest_hv_clock; | |
2319 | ||
4e335d9e | 2320 | if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, |
0d6dd2ff PB |
2321 | &guest_hv_clock, sizeof(guest_hv_clock)))) |
2322 | return; | |
2323 | ||
2324 | /* This VCPU is paused, but it's legal for a guest to read another | |
2325 | * VCPU's kvmclock, so we really have to follow the specification where | |
2326 | * it says that version is odd if data is being modified, and even after | |
2327 | * it is consistent. | |
2328 | * | |
2329 | * Version field updates must be kept separate. This is because | |
2330 | * kvm_write_guest_cached might use a "rep movs" instruction, and | |
2331 | * writes within a string instruction are weakly ordered. So there | |
2332 | * are three writes overall. | |
2333 | * | |
2334 | * As a small optimization, only write the version field in the first | |
2335 | * and third write. The vcpu->pv_time cache is still valid, because the | |
2336 | * version field is the first in the struct. | |
2337 | */ | |
2338 | BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); | |
2339 | ||
51c4b8bb LA |
2340 | if (guest_hv_clock.version & 1) |
2341 | ++guest_hv_clock.version; /* first time write, random junk */ | |
2342 | ||
0d6dd2ff | 2343 | vcpu->hv_clock.version = guest_hv_clock.version + 1; |
4e335d9e PB |
2344 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
2345 | &vcpu->hv_clock, | |
2346 | sizeof(vcpu->hv_clock.version)); | |
0d6dd2ff PB |
2347 | |
2348 | smp_wmb(); | |
2349 | ||
2350 | /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ | |
2351 | vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); | |
2352 | ||
2353 | if (vcpu->pvclock_set_guest_stopped_request) { | |
2354 | vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; | |
2355 | vcpu->pvclock_set_guest_stopped_request = false; | |
2356 | } | |
2357 | ||
2358 | trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); | |
2359 | ||
4e335d9e PB |
2360 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
2361 | &vcpu->hv_clock, | |
2362 | sizeof(vcpu->hv_clock)); | |
0d6dd2ff PB |
2363 | |
2364 | smp_wmb(); | |
2365 | ||
2366 | vcpu->hv_clock.version++; | |
4e335d9e PB |
2367 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
2368 | &vcpu->hv_clock, | |
2369 | sizeof(vcpu->hv_clock.version)); | |
0d6dd2ff PB |
2370 | } |
2371 | ||
34c238a1 | 2372 | static int kvm_guest_time_update(struct kvm_vcpu *v) |
18068523 | 2373 | { |
78db6a50 | 2374 | unsigned long flags, tgt_tsc_khz; |
18068523 | 2375 | struct kvm_vcpu_arch *vcpu = &v->arch; |
d828199e | 2376 | struct kvm_arch *ka = &v->kvm->arch; |
f25e656d | 2377 | s64 kernel_ns; |
d828199e | 2378 | u64 tsc_timestamp, host_tsc; |
51d59c6b | 2379 | u8 pvclock_flags; |
d828199e MT |
2380 | bool use_master_clock; |
2381 | ||
2382 | kernel_ns = 0; | |
2383 | host_tsc = 0; | |
18068523 | 2384 | |
d828199e MT |
2385 | /* |
2386 | * If the host uses TSC clock, then passthrough TSC as stable | |
2387 | * to the guest. | |
2388 | */ | |
2389 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
2390 | use_master_clock = ka->use_master_clock; | |
2391 | if (use_master_clock) { | |
2392 | host_tsc = ka->master_cycle_now; | |
2393 | kernel_ns = ka->master_kernel_ns; | |
2394 | } | |
2395 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
c09664bb MT |
2396 | |
2397 | /* Keep irq disabled to prevent changes to the clock */ | |
2398 | local_irq_save(flags); | |
78db6a50 PB |
2399 | tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); |
2400 | if (unlikely(tgt_tsc_khz == 0)) { | |
c09664bb MT |
2401 | local_irq_restore(flags); |
2402 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); | |
2403 | return 1; | |
2404 | } | |
d828199e | 2405 | if (!use_master_clock) { |
4ea1636b | 2406 | host_tsc = rdtsc(); |
9285ec4c | 2407 | kernel_ns = ktime_get_boottime_ns(); |
d828199e MT |
2408 | } |
2409 | ||
4ba76538 | 2410 | tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); |
d828199e | 2411 | |
c285545f ZA |
2412 | /* |
2413 | * We may have to catch up the TSC to match elapsed wall clock | |
2414 | * time for two reasons, even if kvmclock is used. | |
2415 | * 1) CPU could have been running below the maximum TSC rate | |
2416 | * 2) Broken TSC compensation resets the base at each VCPU | |
2417 | * entry to avoid unknown leaps of TSC even when running | |
2418 | * again on the same CPU. This may cause apparent elapsed | |
2419 | * time to disappear, and the guest to stand still or run | |
2420 | * very slowly. | |
2421 | */ | |
2422 | if (vcpu->tsc_catchup) { | |
2423 | u64 tsc = compute_guest_tsc(v, kernel_ns); | |
2424 | if (tsc > tsc_timestamp) { | |
f1e2b260 | 2425 | adjust_tsc_offset_guest(v, tsc - tsc_timestamp); |
c285545f ZA |
2426 | tsc_timestamp = tsc; |
2427 | } | |
50d0a0f9 GH |
2428 | } |
2429 | ||
18068523 GOC |
2430 | local_irq_restore(flags); |
2431 | ||
0d6dd2ff | 2432 | /* With all the info we got, fill in the values */ |
18068523 | 2433 | |
78db6a50 PB |
2434 | if (kvm_has_tsc_control) |
2435 | tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz); | |
2436 | ||
2437 | if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { | |
3ae13faa | 2438 | kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, |
5f4e3f88 ZA |
2439 | &vcpu->hv_clock.tsc_shift, |
2440 | &vcpu->hv_clock.tsc_to_system_mul); | |
78db6a50 | 2441 | vcpu->hw_tsc_khz = tgt_tsc_khz; |
8cfdc000 ZA |
2442 | } |
2443 | ||
1d5f066e | 2444 | vcpu->hv_clock.tsc_timestamp = tsc_timestamp; |
759379dd | 2445 | vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; |
28e4639a | 2446 | vcpu->last_guest_tsc = tsc_timestamp; |
51d59c6b | 2447 | |
d828199e | 2448 | /* If the host uses TSC clocksource, then it is stable */ |
0d6dd2ff | 2449 | pvclock_flags = 0; |
d828199e MT |
2450 | if (use_master_clock) |
2451 | pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; | |
2452 | ||
78c0337a MT |
2453 | vcpu->hv_clock.flags = pvclock_flags; |
2454 | ||
095cf55d PB |
2455 | if (vcpu->pv_time_enabled) |
2456 | kvm_setup_pvclock_page(v); | |
2457 | if (v == kvm_get_vcpu(v->kvm, 0)) | |
2458 | kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); | |
8cfdc000 | 2459 | return 0; |
c8076604 GH |
2460 | } |
2461 | ||
0061d53d MT |
2462 | /* |
2463 | * kvmclock updates which are isolated to a given vcpu, such as | |
2464 | * vcpu->cpu migration, should not allow system_timestamp from | |
2465 | * the rest of the vcpus to remain static. Otherwise ntp frequency | |
2466 | * correction applies to one vcpu's system_timestamp but not | |
2467 | * the others. | |
2468 | * | |
2469 | * So in those cases, request a kvmclock update for all vcpus. | |
7e44e449 AJ |
2470 | * We need to rate-limit these requests though, as they can |
2471 | * considerably slow guests that have a large number of vcpus. | |
2472 | * The time for a remote vcpu to update its kvmclock is bound | |
2473 | * by the delay we use to rate-limit the updates. | |
0061d53d MT |
2474 | */ |
2475 | ||
7e44e449 AJ |
2476 | #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) |
2477 | ||
2478 | static void kvmclock_update_fn(struct work_struct *work) | |
0061d53d MT |
2479 | { |
2480 | int i; | |
7e44e449 AJ |
2481 | struct delayed_work *dwork = to_delayed_work(work); |
2482 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
2483 | kvmclock_update_work); | |
2484 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
0061d53d MT |
2485 | struct kvm_vcpu *vcpu; |
2486 | ||
2487 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
105b21bb | 2488 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0061d53d MT |
2489 | kvm_vcpu_kick(vcpu); |
2490 | } | |
2491 | } | |
2492 | ||
7e44e449 AJ |
2493 | static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) |
2494 | { | |
2495 | struct kvm *kvm = v->kvm; | |
2496 | ||
105b21bb | 2497 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); |
7e44e449 AJ |
2498 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, |
2499 | KVMCLOCK_UPDATE_DELAY); | |
2500 | } | |
2501 | ||
332967a3 AJ |
2502 | #define KVMCLOCK_SYNC_PERIOD (300 * HZ) |
2503 | ||
2504 | static void kvmclock_sync_fn(struct work_struct *work) | |
2505 | { | |
2506 | struct delayed_work *dwork = to_delayed_work(work); | |
2507 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
2508 | kvmclock_sync_work); | |
2509 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
2510 | ||
630994b3 MT |
2511 | if (!kvmclock_periodic_sync) |
2512 | return; | |
2513 | ||
332967a3 AJ |
2514 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); |
2515 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
2516 | KVMCLOCK_SYNC_PERIOD); | |
2517 | } | |
2518 | ||
191c8137 BP |
2519 | /* |
2520 | * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. | |
2521 | */ | |
2522 | static bool can_set_mci_status(struct kvm_vcpu *vcpu) | |
2523 | { | |
2524 | /* McStatusWrEn enabled? */ | |
2525 | if (guest_cpuid_is_amd(vcpu)) | |
2526 | return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); | |
2527 | ||
2528 | return false; | |
2529 | } | |
2530 | ||
9ffd986c | 2531 | static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 2532 | { |
890ca9ae HY |
2533 | u64 mcg_cap = vcpu->arch.mcg_cap; |
2534 | unsigned bank_num = mcg_cap & 0xff; | |
9ffd986c WL |
2535 | u32 msr = msr_info->index; |
2536 | u64 data = msr_info->data; | |
890ca9ae | 2537 | |
15c4a640 | 2538 | switch (msr) { |
15c4a640 | 2539 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 2540 | vcpu->arch.mcg_status = data; |
15c4a640 | 2541 | break; |
c7ac679c | 2542 | case MSR_IA32_MCG_CTL: |
44883f01 PB |
2543 | if (!(mcg_cap & MCG_CTL_P) && |
2544 | (data || !msr_info->host_initiated)) | |
890ca9ae HY |
2545 | return 1; |
2546 | if (data != 0 && data != ~(u64)0) | |
44883f01 | 2547 | return 1; |
890ca9ae HY |
2548 | vcpu->arch.mcg_ctl = data; |
2549 | break; | |
2550 | default: | |
2551 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 2552 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
6ec4c5ee MP |
2553 | u32 offset = array_index_nospec( |
2554 | msr - MSR_IA32_MC0_CTL, | |
2555 | MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); | |
2556 | ||
114be429 AP |
2557 | /* only 0 or all 1s can be written to IA32_MCi_CTL |
2558 | * some Linux kernels though clear bit 10 in bank 4 to | |
2559 | * workaround a BIOS/GART TBL issue on AMD K8s, ignore | |
2560 | * this to avoid an uncatched #GP in the guest | |
2561 | */ | |
890ca9ae | 2562 | if ((offset & 0x3) == 0 && |
114be429 | 2563 | data != 0 && (data | (1 << 10)) != ~(u64)0) |
890ca9ae | 2564 | return -1; |
191c8137 BP |
2565 | |
2566 | /* MCi_STATUS */ | |
9ffd986c | 2567 | if (!msr_info->host_initiated && |
191c8137 BP |
2568 | (offset & 0x3) == 1 && data != 0) { |
2569 | if (!can_set_mci_status(vcpu)) | |
2570 | return -1; | |
2571 | } | |
2572 | ||
890ca9ae HY |
2573 | vcpu->arch.mce_banks[offset] = data; |
2574 | break; | |
2575 | } | |
2576 | return 1; | |
2577 | } | |
2578 | return 0; | |
2579 | } | |
2580 | ||
ffde22ac ES |
2581 | static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) |
2582 | { | |
2583 | struct kvm *kvm = vcpu->kvm; | |
2584 | int lm = is_long_mode(vcpu); | |
2585 | u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 | |
2586 | : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; | |
2587 | u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 | |
2588 | : kvm->arch.xen_hvm_config.blob_size_32; | |
2589 | u32 page_num = data & ~PAGE_MASK; | |
2590 | u64 page_addr = data & PAGE_MASK; | |
2591 | u8 *page; | |
2592 | int r; | |
2593 | ||
2594 | r = -E2BIG; | |
2595 | if (page_num >= blob_size) | |
2596 | goto out; | |
2597 | r = -ENOMEM; | |
ff5c2c03 SL |
2598 | page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); |
2599 | if (IS_ERR(page)) { | |
2600 | r = PTR_ERR(page); | |
ffde22ac | 2601 | goto out; |
ff5c2c03 | 2602 | } |
54bf36aa | 2603 | if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) |
ffde22ac ES |
2604 | goto out_free; |
2605 | r = 0; | |
2606 | out_free: | |
2607 | kfree(page); | |
2608 | out: | |
2609 | return r; | |
2610 | } | |
2611 | ||
344d9588 GN |
2612 | static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) |
2613 | { | |
2614 | gpa_t gpa = data & ~0x3f; | |
2615 | ||
52a5c155 WL |
2616 | /* Bits 3:5 are reserved, Should be zero */ |
2617 | if (data & 0x38) | |
344d9588 GN |
2618 | return 1; |
2619 | ||
2620 | vcpu->arch.apf.msr_val = data; | |
2621 | ||
2622 | if (!(data & KVM_ASYNC_PF_ENABLED)) { | |
2623 | kvm_clear_async_pf_completion_queue(vcpu); | |
2624 | kvm_async_pf_hash_reset(vcpu); | |
2625 | return 0; | |
2626 | } | |
2627 | ||
4e335d9e | 2628 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, |
8f964525 | 2629 | sizeof(u32))) |
344d9588 GN |
2630 | return 1; |
2631 | ||
6adba527 | 2632 | vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); |
52a5c155 | 2633 | vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; |
344d9588 GN |
2634 | kvm_async_pf_wakeup_all(vcpu); |
2635 | return 0; | |
2636 | } | |
2637 | ||
12f9a48f GC |
2638 | static void kvmclock_reset(struct kvm_vcpu *vcpu) |
2639 | { | |
0b79459b | 2640 | vcpu->arch.pv_time_enabled = false; |
49dedf0d | 2641 | vcpu->arch.time = 0; |
12f9a48f GC |
2642 | } |
2643 | ||
f38a7b75 WL |
2644 | static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa) |
2645 | { | |
2646 | ++vcpu->stat.tlb_flush; | |
2647 | kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa); | |
2648 | } | |
2649 | ||
c9aaa895 GC |
2650 | static void record_steal_time(struct kvm_vcpu *vcpu) |
2651 | { | |
b0431382 BO |
2652 | struct kvm_host_map map; |
2653 | struct kvm_steal_time *st; | |
2654 | ||
c9aaa895 GC |
2655 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) |
2656 | return; | |
2657 | ||
b0431382 BO |
2658 | /* -EAGAIN is returned in atomic context so we can just return. */ |
2659 | if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, | |
2660 | &map, &vcpu->arch.st.cache, false)) | |
c9aaa895 GC |
2661 | return; |
2662 | ||
b0431382 BO |
2663 | st = map.hva + |
2664 | offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); | |
2665 | ||
f38a7b75 WL |
2666 | /* |
2667 | * Doing a TLB flush here, on the guest's behalf, can avoid | |
2668 | * expensive IPIs. | |
2669 | */ | |
b382f44e | 2670 | trace_kvm_pv_tlb_flush(vcpu->vcpu_id, |
b0431382 BO |
2671 | st->preempted & KVM_VCPU_FLUSH_TLB); |
2672 | if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB) | |
f38a7b75 | 2673 | kvm_vcpu_flush_tlb(vcpu, false); |
0b9f6c46 | 2674 | |
a6bd811f | 2675 | vcpu->arch.st.preempted = 0; |
35f3fae1 | 2676 | |
b0431382 BO |
2677 | if (st->version & 1) |
2678 | st->version += 1; /* first time write, random junk */ | |
35f3fae1 | 2679 | |
b0431382 | 2680 | st->version += 1; |
35f3fae1 WL |
2681 | |
2682 | smp_wmb(); | |
2683 | ||
b0431382 | 2684 | st->steal += current->sched_info.run_delay - |
c54cdf14 LC |
2685 | vcpu->arch.st.last_steal; |
2686 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
35f3fae1 | 2687 | |
35f3fae1 WL |
2688 | smp_wmb(); |
2689 | ||
b0431382 | 2690 | st->version += 1; |
c9aaa895 | 2691 | |
b0431382 | 2692 | kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false); |
c9aaa895 GC |
2693 | } |
2694 | ||
8fe8ab46 | 2695 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 2696 | { |
5753785f | 2697 | bool pr = false; |
8fe8ab46 WA |
2698 | u32 msr = msr_info->index; |
2699 | u64 data = msr_info->data; | |
5753785f | 2700 | |
15c4a640 | 2701 | switch (msr) { |
2e32b719 | 2702 | case MSR_AMD64_NB_CFG: |
2e32b719 BP |
2703 | case MSR_IA32_UCODE_WRITE: |
2704 | case MSR_VM_HSAVE_PA: | |
2705 | case MSR_AMD64_PATCH_LOADER: | |
2706 | case MSR_AMD64_BU_CFG2: | |
405a353a | 2707 | case MSR_AMD64_DC_CFG: |
0e1b869f | 2708 | case MSR_F15H_EX_CFG: |
2e32b719 BP |
2709 | break; |
2710 | ||
518e7b94 WL |
2711 | case MSR_IA32_UCODE_REV: |
2712 | if (msr_info->host_initiated) | |
2713 | vcpu->arch.microcode_version = data; | |
2714 | break; | |
0cf9135b SC |
2715 | case MSR_IA32_ARCH_CAPABILITIES: |
2716 | if (!msr_info->host_initiated) | |
2717 | return 1; | |
2718 | vcpu->arch.arch_capabilities = data; | |
2719 | break; | |
15c4a640 | 2720 | case MSR_EFER: |
11988499 | 2721 | return set_efer(vcpu, msr_info); |
8f1589d9 AP |
2722 | case MSR_K7_HWCR: |
2723 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
82494028 | 2724 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ |
a223c313 | 2725 | data &= ~(u64)0x8; /* ignore TLB cache disable */ |
191c8137 BP |
2726 | |
2727 | /* Handle McStatusWrEn */ | |
2728 | if (data == BIT_ULL(18)) { | |
2729 | vcpu->arch.msr_hwcr = data; | |
2730 | } else if (data != 0) { | |
a737f256 CD |
2731 | vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", |
2732 | data); | |
8f1589d9 AP |
2733 | return 1; |
2734 | } | |
15c4a640 | 2735 | break; |
f7c6d140 AP |
2736 | case MSR_FAM10H_MMIO_CONF_BASE: |
2737 | if (data != 0) { | |
a737f256 CD |
2738 | vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " |
2739 | "0x%llx\n", data); | |
f7c6d140 AP |
2740 | return 1; |
2741 | } | |
15c4a640 | 2742 | break; |
b5e2fec0 AG |
2743 | case MSR_IA32_DEBUGCTLMSR: |
2744 | if (!data) { | |
2745 | /* We support the non-activated case already */ | |
2746 | break; | |
2747 | } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { | |
2748 | /* Values other than LBR and BTF are vendor-specific, | |
2749 | thus reserved and should throw a #GP */ | |
2750 | return 1; | |
2751 | } | |
a737f256 CD |
2752 | vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", |
2753 | __func__, data); | |
b5e2fec0 | 2754 | break; |
9ba075a6 | 2755 | case 0x200 ... 0x2ff: |
ff53604b | 2756 | return kvm_mtrr_set_msr(vcpu, msr, data); |
15c4a640 | 2757 | case MSR_IA32_APICBASE: |
58cb628d | 2758 | return kvm_set_apic_base(vcpu, msr_info); |
0105d1a5 GN |
2759 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
2760 | return kvm_x2apic_msr_write(vcpu, msr, data); | |
a3e06bbe LJ |
2761 | case MSR_IA32_TSCDEADLINE: |
2762 | kvm_set_lapic_tscdeadline_msr(vcpu, data); | |
2763 | break; | |
ba904635 | 2764 | case MSR_IA32_TSC_ADJUST: |
d6321d49 | 2765 | if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { |
ba904635 | 2766 | if (!msr_info->host_initiated) { |
d913b904 | 2767 | s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; |
d7add054 | 2768 | adjust_tsc_offset_guest(vcpu, adj); |
ba904635 WA |
2769 | } |
2770 | vcpu->arch.ia32_tsc_adjust_msr = data; | |
2771 | } | |
2772 | break; | |
15c4a640 | 2773 | case MSR_IA32_MISC_ENABLE: |
511a8556 WL |
2774 | if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && |
2775 | ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { | |
2776 | if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) | |
2777 | return 1; | |
2778 | vcpu->arch.ia32_misc_enable_msr = data; | |
2779 | kvm_update_cpuid(vcpu); | |
2780 | } else { | |
2781 | vcpu->arch.ia32_misc_enable_msr = data; | |
2782 | } | |
15c4a640 | 2783 | break; |
64d60670 PB |
2784 | case MSR_IA32_SMBASE: |
2785 | if (!msr_info->host_initiated) | |
2786 | return 1; | |
2787 | vcpu->arch.smbase = data; | |
2788 | break; | |
73f624f4 PB |
2789 | case MSR_IA32_POWER_CTL: |
2790 | vcpu->arch.msr_ia32_power_ctl = data; | |
2791 | break; | |
dd259935 PB |
2792 | case MSR_IA32_TSC: |
2793 | kvm_write_tsc(vcpu, msr_info); | |
2794 | break; | |
864e2ab2 AL |
2795 | case MSR_IA32_XSS: |
2796 | if (!msr_info->host_initiated && | |
2797 | !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) | |
2798 | return 1; | |
2799 | /* | |
2800 | * We do support PT if kvm_x86_ops->pt_supported(), but we do | |
2801 | * not support IA32_XSS[bit 8]. Guests will have to use | |
2802 | * RDMSR/WRMSR rather than XSAVES/XRSTORS to save/restore PT | |
2803 | * MSRs. | |
2804 | */ | |
2805 | if (data != 0) | |
2806 | return 1; | |
2807 | vcpu->arch.ia32_xss = data; | |
2808 | break; | |
52797bf9 LA |
2809 | case MSR_SMI_COUNT: |
2810 | if (!msr_info->host_initiated) | |
2811 | return 1; | |
2812 | vcpu->arch.smi_count = data; | |
2813 | break; | |
11c6bffa | 2814 | case MSR_KVM_WALL_CLOCK_NEW: |
18068523 GOC |
2815 | case MSR_KVM_WALL_CLOCK: |
2816 | vcpu->kvm->arch.wall_clock = data; | |
2817 | kvm_write_wall_clock(vcpu->kvm, data); | |
2818 | break; | |
11c6bffa | 2819 | case MSR_KVM_SYSTEM_TIME_NEW: |
18068523 | 2820 | case MSR_KVM_SYSTEM_TIME: { |
54750f2c MT |
2821 | struct kvm_arch *ka = &vcpu->kvm->arch; |
2822 | ||
54750f2c MT |
2823 | if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { |
2824 | bool tmp = (msr == MSR_KVM_SYSTEM_TIME); | |
2825 | ||
2826 | if (ka->boot_vcpu_runs_old_kvmclock != tmp) | |
1bd2009e | 2827 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
54750f2c MT |
2828 | |
2829 | ka->boot_vcpu_runs_old_kvmclock = tmp; | |
2830 | } | |
2831 | ||
18068523 | 2832 | vcpu->arch.time = data; |
0061d53d | 2833 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
18068523 GOC |
2834 | |
2835 | /* we verify if the enable bit is set... */ | |
49dedf0d | 2836 | vcpu->arch.pv_time_enabled = false; |
18068523 GOC |
2837 | if (!(data & 1)) |
2838 | break; | |
2839 | ||
49dedf0d | 2840 | if (!kvm_gfn_to_hva_cache_init(vcpu->kvm, |
8f964525 AH |
2841 | &vcpu->arch.pv_time, data & ~1ULL, |
2842 | sizeof(struct pvclock_vcpu_time_info))) | |
0b79459b | 2843 | vcpu->arch.pv_time_enabled = true; |
32cad84f | 2844 | |
18068523 GOC |
2845 | break; |
2846 | } | |
344d9588 GN |
2847 | case MSR_KVM_ASYNC_PF_EN: |
2848 | if (kvm_pv_enable_async_pf(vcpu, data)) | |
2849 | return 1; | |
2850 | break; | |
c9aaa895 GC |
2851 | case MSR_KVM_STEAL_TIME: |
2852 | ||
2853 | if (unlikely(!sched_info_on())) | |
2854 | return 1; | |
2855 | ||
2856 | if (data & KVM_STEAL_RESERVED_MASK) | |
2857 | return 1; | |
2858 | ||
c9aaa895 GC |
2859 | vcpu->arch.st.msr_val = data; |
2860 | ||
2861 | if (!(data & KVM_MSR_ENABLED)) | |
2862 | break; | |
2863 | ||
c9aaa895 GC |
2864 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
2865 | ||
2866 | break; | |
ae7a2a3f | 2867 | case MSR_KVM_PV_EOI_EN: |
72bbf935 | 2868 | if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8))) |
ae7a2a3f MT |
2869 | return 1; |
2870 | break; | |
c9aaa895 | 2871 | |
2d5ba19b MT |
2872 | case MSR_KVM_POLL_CONTROL: |
2873 | /* only enable bit supported */ | |
2874 | if (data & (-1ULL << 1)) | |
2875 | return 1; | |
2876 | ||
2877 | vcpu->arch.msr_kvm_poll_control = data; | |
2878 | break; | |
2879 | ||
890ca9ae HY |
2880 | case MSR_IA32_MCG_CTL: |
2881 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 2882 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
9ffd986c | 2883 | return set_msr_mce(vcpu, msr_info); |
71db6023 | 2884 | |
6912ac32 WH |
2885 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: |
2886 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
2887 | pr = true; /* fall through */ | |
2888 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: | |
2889 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 2890 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 2891 | return kvm_pmu_set_msr(vcpu, msr_info); |
5753785f GN |
2892 | |
2893 | if (pr || data != 0) | |
a737f256 CD |
2894 | vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " |
2895 | "0x%x data 0x%llx\n", msr, data); | |
5753785f | 2896 | break; |
84e0cefa JS |
2897 | case MSR_K7_CLK_CTL: |
2898 | /* | |
2899 | * Ignore all writes to this no longer documented MSR. | |
2900 | * Writes are only relevant for old K7 processors, | |
2901 | * all pre-dating SVM, but a recommended workaround from | |
4a969980 | 2902 | * AMD for these chips. It is possible to specify the |
84e0cefa JS |
2903 | * affected processor models on the command line, hence |
2904 | * the need to ignore the workaround. | |
2905 | */ | |
2906 | break; | |
55cd8e5a | 2907 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
e7d9513b AS |
2908 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
2909 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 2910 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
2911 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
2912 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
2913 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
e7d9513b AS |
2914 | return kvm_hv_set_msr_common(vcpu, msr, data, |
2915 | msr_info->host_initiated); | |
91c9c3ed | 2916 | case MSR_IA32_BBL_CR_CTL3: |
2917 | /* Drop writes to this legacy MSR -- see rdmsr | |
2918 | * counterpart for further detail. | |
2919 | */ | |
fab0aa3b EM |
2920 | if (report_ignored_msrs) |
2921 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", | |
2922 | msr, data); | |
91c9c3ed | 2923 | break; |
2b036c6b | 2924 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 2925 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
2926 | return 1; |
2927 | vcpu->arch.osvw.length = data; | |
2928 | break; | |
2929 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 2930 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
2931 | return 1; |
2932 | vcpu->arch.osvw.status = data; | |
2933 | break; | |
db2336a8 KH |
2934 | case MSR_PLATFORM_INFO: |
2935 | if (!msr_info->host_initiated || | |
db2336a8 KH |
2936 | (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && |
2937 | cpuid_fault_enabled(vcpu))) | |
2938 | return 1; | |
2939 | vcpu->arch.msr_platform_info = data; | |
2940 | break; | |
2941 | case MSR_MISC_FEATURES_ENABLES: | |
2942 | if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || | |
2943 | (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && | |
2944 | !supports_cpuid_fault(vcpu))) | |
2945 | return 1; | |
2946 | vcpu->arch.msr_misc_features_enables = data; | |
2947 | break; | |
15c4a640 | 2948 | default: |
ffde22ac ES |
2949 | if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) |
2950 | return xen_hvm_config(vcpu, data); | |
c6702c9d | 2951 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 2952 | return kvm_pmu_set_msr(vcpu, msr_info); |
ed85c068 | 2953 | if (!ignore_msrs) { |
ae0f5499 | 2954 | vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n", |
a737f256 | 2955 | msr, data); |
ed85c068 AP |
2956 | return 1; |
2957 | } else { | |
fab0aa3b EM |
2958 | if (report_ignored_msrs) |
2959 | vcpu_unimpl(vcpu, | |
2960 | "ignored wrmsr: 0x%x data 0x%llx\n", | |
2961 | msr, data); | |
ed85c068 AP |
2962 | break; |
2963 | } | |
15c4a640 CO |
2964 | } |
2965 | return 0; | |
2966 | } | |
2967 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
2968 | ||
44883f01 | 2969 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) |
15c4a640 CO |
2970 | { |
2971 | u64 data; | |
890ca9ae HY |
2972 | u64 mcg_cap = vcpu->arch.mcg_cap; |
2973 | unsigned bank_num = mcg_cap & 0xff; | |
15c4a640 CO |
2974 | |
2975 | switch (msr) { | |
15c4a640 CO |
2976 | case MSR_IA32_P5_MC_ADDR: |
2977 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
2978 | data = 0; |
2979 | break; | |
15c4a640 | 2980 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
2981 | data = vcpu->arch.mcg_cap; |
2982 | break; | |
c7ac679c | 2983 | case MSR_IA32_MCG_CTL: |
44883f01 | 2984 | if (!(mcg_cap & MCG_CTL_P) && !host) |
890ca9ae HY |
2985 | return 1; |
2986 | data = vcpu->arch.mcg_ctl; | |
2987 | break; | |
2988 | case MSR_IA32_MCG_STATUS: | |
2989 | data = vcpu->arch.mcg_status; | |
2990 | break; | |
2991 | default: | |
2992 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 2993 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
6ec4c5ee MP |
2994 | u32 offset = array_index_nospec( |
2995 | msr - MSR_IA32_MC0_CTL, | |
2996 | MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); | |
2997 | ||
890ca9ae HY |
2998 | data = vcpu->arch.mce_banks[offset]; |
2999 | break; | |
3000 | } | |
3001 | return 1; | |
3002 | } | |
3003 | *pdata = data; | |
3004 | return 0; | |
3005 | } | |
3006 | ||
609e36d3 | 3007 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
890ca9ae | 3008 | { |
609e36d3 | 3009 | switch (msr_info->index) { |
890ca9ae | 3010 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 3011 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
3012 | case MSR_IA32_DEBUGCTLMSR: |
3013 | case MSR_IA32_LASTBRANCHFROMIP: | |
3014 | case MSR_IA32_LASTBRANCHTOIP: | |
3015 | case MSR_IA32_LASTINTFROMIP: | |
3016 | case MSR_IA32_LASTINTTOIP: | |
60af2ecd | 3017 | case MSR_K8_SYSCFG: |
3afb1121 PB |
3018 | case MSR_K8_TSEG_ADDR: |
3019 | case MSR_K8_TSEG_MASK: | |
61a6bd67 | 3020 | case MSR_VM_HSAVE_PA: |
1fdbd48c | 3021 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 3022 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 3023 | case MSR_FAM10H_MMIO_CONF_BASE: |
2e32b719 | 3024 | case MSR_AMD64_BU_CFG2: |
0c2df2a1 | 3025 | case MSR_IA32_PERF_CTL: |
405a353a | 3026 | case MSR_AMD64_DC_CFG: |
0e1b869f | 3027 | case MSR_F15H_EX_CFG: |
609e36d3 | 3028 | msr_info->data = 0; |
15c4a640 | 3029 | break; |
c51eb52b | 3030 | case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: |
6912ac32 WH |
3031 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: |
3032 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: | |
3033 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
3034 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 3035 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
609e36d3 PB |
3036 | return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); |
3037 | msr_info->data = 0; | |
5753785f | 3038 | break; |
742bc670 | 3039 | case MSR_IA32_UCODE_REV: |
518e7b94 | 3040 | msr_info->data = vcpu->arch.microcode_version; |
742bc670 | 3041 | break; |
0cf9135b SC |
3042 | case MSR_IA32_ARCH_CAPABILITIES: |
3043 | if (!msr_info->host_initiated && | |
3044 | !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) | |
3045 | return 1; | |
3046 | msr_info->data = vcpu->arch.arch_capabilities; | |
3047 | break; | |
73f624f4 PB |
3048 | case MSR_IA32_POWER_CTL: |
3049 | msr_info->data = vcpu->arch.msr_ia32_power_ctl; | |
3050 | break; | |
dd259935 PB |
3051 | case MSR_IA32_TSC: |
3052 | msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset; | |
3053 | break; | |
9ba075a6 | 3054 | case MSR_MTRRcap: |
9ba075a6 | 3055 | case 0x200 ... 0x2ff: |
ff53604b | 3056 | return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); |
15c4a640 | 3057 | case 0xcd: /* fsb frequency */ |
609e36d3 | 3058 | msr_info->data = 3; |
15c4a640 | 3059 | break; |
7b914098 JS |
3060 | /* |
3061 | * MSR_EBC_FREQUENCY_ID | |
3062 | * Conservative value valid for even the basic CPU models. | |
3063 | * Models 0,1: 000 in bits 23:21 indicating a bus speed of | |
3064 | * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, | |
3065 | * and 266MHz for model 3, or 4. Set Core Clock | |
3066 | * Frequency to System Bus Frequency Ratio to 1 (bits | |
3067 | * 31:24) even though these are only valid for CPU | |
3068 | * models > 2, however guests may end up dividing or | |
3069 | * multiplying by zero otherwise. | |
3070 | */ | |
3071 | case MSR_EBC_FREQUENCY_ID: | |
609e36d3 | 3072 | msr_info->data = 1 << 24; |
7b914098 | 3073 | break; |
15c4a640 | 3074 | case MSR_IA32_APICBASE: |
609e36d3 | 3075 | msr_info->data = kvm_get_apic_base(vcpu); |
15c4a640 | 3076 | break; |
0105d1a5 | 3077 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
609e36d3 | 3078 | return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); |
0105d1a5 | 3079 | break; |
a3e06bbe | 3080 | case MSR_IA32_TSCDEADLINE: |
609e36d3 | 3081 | msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); |
a3e06bbe | 3082 | break; |
ba904635 | 3083 | case MSR_IA32_TSC_ADJUST: |
609e36d3 | 3084 | msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; |
ba904635 | 3085 | break; |
15c4a640 | 3086 | case MSR_IA32_MISC_ENABLE: |
609e36d3 | 3087 | msr_info->data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 3088 | break; |
64d60670 PB |
3089 | case MSR_IA32_SMBASE: |
3090 | if (!msr_info->host_initiated) | |
3091 | return 1; | |
3092 | msr_info->data = vcpu->arch.smbase; | |
15c4a640 | 3093 | break; |
52797bf9 LA |
3094 | case MSR_SMI_COUNT: |
3095 | msr_info->data = vcpu->arch.smi_count; | |
3096 | break; | |
847f0ad8 AG |
3097 | case MSR_IA32_PERF_STATUS: |
3098 | /* TSC increment by tick */ | |
609e36d3 | 3099 | msr_info->data = 1000ULL; |
847f0ad8 | 3100 | /* CPU multiplier */ |
b0996ae4 | 3101 | msr_info->data |= (((uint64_t)4ULL) << 40); |
847f0ad8 | 3102 | break; |
15c4a640 | 3103 | case MSR_EFER: |
609e36d3 | 3104 | msr_info->data = vcpu->arch.efer; |
15c4a640 | 3105 | break; |
18068523 | 3106 | case MSR_KVM_WALL_CLOCK: |
11c6bffa | 3107 | case MSR_KVM_WALL_CLOCK_NEW: |
609e36d3 | 3108 | msr_info->data = vcpu->kvm->arch.wall_clock; |
18068523 GOC |
3109 | break; |
3110 | case MSR_KVM_SYSTEM_TIME: | |
11c6bffa | 3111 | case MSR_KVM_SYSTEM_TIME_NEW: |
609e36d3 | 3112 | msr_info->data = vcpu->arch.time; |
18068523 | 3113 | break; |
344d9588 | 3114 | case MSR_KVM_ASYNC_PF_EN: |
609e36d3 | 3115 | msr_info->data = vcpu->arch.apf.msr_val; |
344d9588 | 3116 | break; |
c9aaa895 | 3117 | case MSR_KVM_STEAL_TIME: |
609e36d3 | 3118 | msr_info->data = vcpu->arch.st.msr_val; |
c9aaa895 | 3119 | break; |
1d92128f | 3120 | case MSR_KVM_PV_EOI_EN: |
609e36d3 | 3121 | msr_info->data = vcpu->arch.pv_eoi.msr_val; |
1d92128f | 3122 | break; |
2d5ba19b MT |
3123 | case MSR_KVM_POLL_CONTROL: |
3124 | msr_info->data = vcpu->arch.msr_kvm_poll_control; | |
3125 | break; | |
890ca9ae HY |
3126 | case MSR_IA32_P5_MC_ADDR: |
3127 | case MSR_IA32_P5_MC_TYPE: | |
3128 | case MSR_IA32_MCG_CAP: | |
3129 | case MSR_IA32_MCG_CTL: | |
3130 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 3131 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
44883f01 PB |
3132 | return get_msr_mce(vcpu, msr_info->index, &msr_info->data, |
3133 | msr_info->host_initiated); | |
864e2ab2 AL |
3134 | case MSR_IA32_XSS: |
3135 | if (!msr_info->host_initiated && | |
3136 | !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) | |
3137 | return 1; | |
3138 | msr_info->data = vcpu->arch.ia32_xss; | |
3139 | break; | |
84e0cefa JS |
3140 | case MSR_K7_CLK_CTL: |
3141 | /* | |
3142 | * Provide expected ramp-up count for K7. All other | |
3143 | * are set to zero, indicating minimum divisors for | |
3144 | * every field. | |
3145 | * | |
3146 | * This prevents guest kernels on AMD host with CPU | |
3147 | * type 6, model 8 and higher from exploding due to | |
3148 | * the rdmsr failing. | |
3149 | */ | |
609e36d3 | 3150 | msr_info->data = 0x20000000; |
84e0cefa | 3151 | break; |
55cd8e5a | 3152 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
e7d9513b AS |
3153 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
3154 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 3155 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
3156 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
3157 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
3158 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
e83d5887 | 3159 | return kvm_hv_get_msr_common(vcpu, |
44883f01 PB |
3160 | msr_info->index, &msr_info->data, |
3161 | msr_info->host_initiated); | |
55cd8e5a | 3162 | break; |
91c9c3ed | 3163 | case MSR_IA32_BBL_CR_CTL3: |
3164 | /* This legacy MSR exists but isn't fully documented in current | |
3165 | * silicon. It is however accessed by winxp in very narrow | |
3166 | * scenarios where it sets bit #19, itself documented as | |
3167 | * a "reserved" bit. Best effort attempt to source coherent | |
3168 | * read data here should the balance of the register be | |
3169 | * interpreted by the guest: | |
3170 | * | |
3171 | * L2 cache control register 3: 64GB range, 256KB size, | |
3172 | * enabled, latency 0x1, configured | |
3173 | */ | |
609e36d3 | 3174 | msr_info->data = 0xbe702111; |
91c9c3ed | 3175 | break; |
2b036c6b | 3176 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 3177 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 3178 | return 1; |
609e36d3 | 3179 | msr_info->data = vcpu->arch.osvw.length; |
2b036c6b BO |
3180 | break; |
3181 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 3182 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 3183 | return 1; |
609e36d3 | 3184 | msr_info->data = vcpu->arch.osvw.status; |
2b036c6b | 3185 | break; |
db2336a8 | 3186 | case MSR_PLATFORM_INFO: |
6fbbde9a DS |
3187 | if (!msr_info->host_initiated && |
3188 | !vcpu->kvm->arch.guest_can_read_msr_platform_info) | |
3189 | return 1; | |
db2336a8 KH |
3190 | msr_info->data = vcpu->arch.msr_platform_info; |
3191 | break; | |
3192 | case MSR_MISC_FEATURES_ENABLES: | |
3193 | msr_info->data = vcpu->arch.msr_misc_features_enables; | |
3194 | break; | |
191c8137 BP |
3195 | case MSR_K7_HWCR: |
3196 | msr_info->data = vcpu->arch.msr_hwcr; | |
3197 | break; | |
15c4a640 | 3198 | default: |
c6702c9d | 3199 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
609e36d3 | 3200 | return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); |
ed85c068 | 3201 | if (!ignore_msrs) { |
ae0f5499 BD |
3202 | vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n", |
3203 | msr_info->index); | |
ed85c068 AP |
3204 | return 1; |
3205 | } else { | |
fab0aa3b EM |
3206 | if (report_ignored_msrs) |
3207 | vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", | |
3208 | msr_info->index); | |
609e36d3 | 3209 | msr_info->data = 0; |
ed85c068 AP |
3210 | } |
3211 | break; | |
15c4a640 | 3212 | } |
15c4a640 CO |
3213 | return 0; |
3214 | } | |
3215 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
3216 | ||
313a3dc7 CO |
3217 | /* |
3218 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
3219 | * | |
3220 | * @return number of msrs set successfully. | |
3221 | */ | |
3222 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
3223 | struct kvm_msr_entry *entries, | |
3224 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
3225 | unsigned index, u64 *data)) | |
3226 | { | |
801e459a | 3227 | int i; |
313a3dc7 | 3228 | |
313a3dc7 CO |
3229 | for (i = 0; i < msrs->nmsrs; ++i) |
3230 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
3231 | break; | |
3232 | ||
313a3dc7 CO |
3233 | return i; |
3234 | } | |
3235 | ||
3236 | /* | |
3237 | * Read or write a bunch of msrs. Parameters are user addresses. | |
3238 | * | |
3239 | * @return number of msrs set successfully. | |
3240 | */ | |
3241 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
3242 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
3243 | unsigned index, u64 *data), | |
3244 | int writeback) | |
3245 | { | |
3246 | struct kvm_msrs msrs; | |
3247 | struct kvm_msr_entry *entries; | |
3248 | int r, n; | |
3249 | unsigned size; | |
3250 | ||
3251 | r = -EFAULT; | |
0e96f31e | 3252 | if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) |
313a3dc7 CO |
3253 | goto out; |
3254 | ||
3255 | r = -E2BIG; | |
3256 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
3257 | goto out; | |
3258 | ||
313a3dc7 | 3259 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; |
ff5c2c03 SL |
3260 | entries = memdup_user(user_msrs->entries, size); |
3261 | if (IS_ERR(entries)) { | |
3262 | r = PTR_ERR(entries); | |
313a3dc7 | 3263 | goto out; |
ff5c2c03 | 3264 | } |
313a3dc7 CO |
3265 | |
3266 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
3267 | if (r < 0) | |
3268 | goto out_free; | |
3269 | ||
3270 | r = -EFAULT; | |
3271 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
3272 | goto out_free; | |
3273 | ||
3274 | r = n; | |
3275 | ||
3276 | out_free: | |
7a73c028 | 3277 | kfree(entries); |
313a3dc7 CO |
3278 | out: |
3279 | return r; | |
3280 | } | |
3281 | ||
4d5422ce WL |
3282 | static inline bool kvm_can_mwait_in_guest(void) |
3283 | { | |
3284 | return boot_cpu_has(X86_FEATURE_MWAIT) && | |
8e9b29b6 KA |
3285 | !boot_cpu_has_bug(X86_BUG_MONITOR) && |
3286 | boot_cpu_has(X86_FEATURE_ARAT); | |
4d5422ce WL |
3287 | } |
3288 | ||
784aa3d7 | 3289 | int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) |
018d00d2 | 3290 | { |
4d5422ce | 3291 | int r = 0; |
018d00d2 ZX |
3292 | |
3293 | switch (ext) { | |
3294 | case KVM_CAP_IRQCHIP: | |
3295 | case KVM_CAP_HLT: | |
3296 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 3297 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 3298 | case KVM_CAP_EXT_CPUID: |
9c15bb1d | 3299 | case KVM_CAP_EXT_EMUL_CPUID: |
c8076604 | 3300 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 3301 | case KVM_CAP_PIT: |
a28e4f5a | 3302 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 3303 | case KVM_CAP_MP_STATE: |
ed848624 | 3304 | case KVM_CAP_SYNC_MMU: |
a355c85c | 3305 | case KVM_CAP_USER_NMI: |
52d939a0 | 3306 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 3307 | case KVM_CAP_IRQ_INJECT_STATUS: |
d34e6b17 | 3308 | case KVM_CAP_IOEVENTFD: |
f848a5a8 | 3309 | case KVM_CAP_IOEVENTFD_NO_LENGTH: |
c5ff41ce | 3310 | case KVM_CAP_PIT2: |
e9f42757 | 3311 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 3312 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
ffde22ac | 3313 | case KVM_CAP_XEN_HVM: |
3cfc3092 | 3314 | case KVM_CAP_VCPU_EVENTS: |
55cd8e5a | 3315 | case KVM_CAP_HYPERV: |
10388a07 | 3316 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 3317 | case KVM_CAP_HYPERV_SPIN: |
5c919412 | 3318 | case KVM_CAP_HYPERV_SYNIC: |
efc479e6 | 3319 | case KVM_CAP_HYPERV_SYNIC2: |
d3457c87 | 3320 | case KVM_CAP_HYPERV_VP_INDEX: |
faeb7833 | 3321 | case KVM_CAP_HYPERV_EVENTFD: |
c1aea919 | 3322 | case KVM_CAP_HYPERV_TLBFLUSH: |
214ff83d | 3323 | case KVM_CAP_HYPERV_SEND_IPI: |
2bc39970 | 3324 | case KVM_CAP_HYPERV_CPUID: |
ab9f4ecb | 3325 | case KVM_CAP_PCI_SEGMENT: |
a1efbe77 | 3326 | case KVM_CAP_DEBUGREGS: |
d2be1651 | 3327 | case KVM_CAP_X86_ROBUST_SINGLESTEP: |
2d5b5a66 | 3328 | case KVM_CAP_XSAVE: |
344d9588 | 3329 | case KVM_CAP_ASYNC_PF: |
92a1f12d | 3330 | case KVM_CAP_GET_TSC_KHZ: |
1c0b28c2 | 3331 | case KVM_CAP_KVMCLOCK_CTRL: |
4d8b81ab | 3332 | case KVM_CAP_READONLY_MEM: |
5f66b620 | 3333 | case KVM_CAP_HYPERV_TIME: |
100943c5 | 3334 | case KVM_CAP_IOAPIC_POLARITY_IGNORED: |
defcf51f | 3335 | case KVM_CAP_TSC_DEADLINE_TIMER: |
90de4a18 | 3336 | case KVM_CAP_DISABLE_QUIRKS: |
d71ba788 | 3337 | case KVM_CAP_SET_BOOT_CPU_ID: |
49df6397 | 3338 | case KVM_CAP_SPLIT_IRQCHIP: |
460df4c1 | 3339 | case KVM_CAP_IMMEDIATE_EXIT: |
66bb8a06 | 3340 | case KVM_CAP_PMU_EVENT_FILTER: |
801e459a | 3341 | case KVM_CAP_GET_MSR_FEATURES: |
6fbbde9a | 3342 | case KVM_CAP_MSR_PLATFORM_INFO: |
c4f55198 | 3343 | case KVM_CAP_EXCEPTION_PAYLOAD: |
018d00d2 ZX |
3344 | r = 1; |
3345 | break; | |
01643c51 KH |
3346 | case KVM_CAP_SYNC_REGS: |
3347 | r = KVM_SYNC_X86_VALID_FIELDS; | |
3348 | break; | |
e3fd9a93 PB |
3349 | case KVM_CAP_ADJUST_CLOCK: |
3350 | r = KVM_CLOCK_TSC_STABLE; | |
3351 | break; | |
4d5422ce | 3352 | case KVM_CAP_X86_DISABLE_EXITS: |
b5170063 WL |
3353 | r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE | |
3354 | KVM_X86_DISABLE_EXITS_CSTATE; | |
4d5422ce WL |
3355 | if(kvm_can_mwait_in_guest()) |
3356 | r |= KVM_X86_DISABLE_EXITS_MWAIT; | |
668fffa3 | 3357 | break; |
6d396b55 PB |
3358 | case KVM_CAP_X86_SMM: |
3359 | /* SMBASE is usually relocated above 1M on modern chipsets, | |
3360 | * and SMM handlers might indeed rely on 4G segment limits, | |
3361 | * so do not report SMM to be available if real mode is | |
3362 | * emulated via vm86 mode. Still, do not go to great lengths | |
3363 | * to avoid userspace's usage of the feature, because it is a | |
3364 | * fringe case that is not enabled except via specific settings | |
3365 | * of the module parameters. | |
3366 | */ | |
bc226f07 | 3367 | r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE); |
6d396b55 | 3368 | break; |
774ead3a AK |
3369 | case KVM_CAP_VAPIC: |
3370 | r = !kvm_x86_ops->cpu_has_accelerated_tpr(); | |
3371 | break; | |
f725230a | 3372 | case KVM_CAP_NR_VCPUS: |
8c3ba334 SL |
3373 | r = KVM_SOFT_MAX_VCPUS; |
3374 | break; | |
3375 | case KVM_CAP_MAX_VCPUS: | |
f725230a AK |
3376 | r = KVM_MAX_VCPUS; |
3377 | break; | |
a86cb413 TH |
3378 | case KVM_CAP_MAX_VCPU_ID: |
3379 | r = KVM_MAX_VCPU_ID; | |
3380 | break; | |
a68a6a72 MT |
3381 | case KVM_CAP_PV_MMU: /* obsolete */ |
3382 | r = 0; | |
2f333bcb | 3383 | break; |
890ca9ae HY |
3384 | case KVM_CAP_MCE: |
3385 | r = KVM_MAX_MCE_BANKS; | |
3386 | break; | |
2d5b5a66 | 3387 | case KVM_CAP_XCRS: |
d366bf7e | 3388 | r = boot_cpu_has(X86_FEATURE_XSAVE); |
2d5b5a66 | 3389 | break; |
92a1f12d JR |
3390 | case KVM_CAP_TSC_CONTROL: |
3391 | r = kvm_has_tsc_control; | |
3392 | break; | |
37131313 RK |
3393 | case KVM_CAP_X2APIC_API: |
3394 | r = KVM_X2APIC_API_VALID_FLAGS; | |
3395 | break; | |
8fcc4b59 JM |
3396 | case KVM_CAP_NESTED_STATE: |
3397 | r = kvm_x86_ops->get_nested_state ? | |
be43c440 | 3398 | kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0; |
8fcc4b59 | 3399 | break; |
344c6c80 | 3400 | case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: |
5a0165f6 VK |
3401 | r = kvm_x86_ops->enable_direct_tlbflush != NULL; |
3402 | break; | |
3403 | case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: | |
3404 | r = kvm_x86_ops->nested_enable_evmcs != NULL; | |
344c6c80 | 3405 | break; |
018d00d2 | 3406 | default: |
018d00d2 ZX |
3407 | break; |
3408 | } | |
3409 | return r; | |
3410 | ||
3411 | } | |
3412 | ||
043405e1 CO |
3413 | long kvm_arch_dev_ioctl(struct file *filp, |
3414 | unsigned int ioctl, unsigned long arg) | |
3415 | { | |
3416 | void __user *argp = (void __user *)arg; | |
3417 | long r; | |
3418 | ||
3419 | switch (ioctl) { | |
3420 | case KVM_GET_MSR_INDEX_LIST: { | |
3421 | struct kvm_msr_list __user *user_msr_list = argp; | |
3422 | struct kvm_msr_list msr_list; | |
3423 | unsigned n; | |
3424 | ||
3425 | r = -EFAULT; | |
0e96f31e | 3426 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) |
043405e1 CO |
3427 | goto out; |
3428 | n = msr_list.nmsrs; | |
62ef68bb | 3429 | msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; |
0e96f31e | 3430 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) |
043405e1 CO |
3431 | goto out; |
3432 | r = -E2BIG; | |
e125e7b6 | 3433 | if (n < msr_list.nmsrs) |
043405e1 CO |
3434 | goto out; |
3435 | r = -EFAULT; | |
3436 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
3437 | num_msrs_to_save * sizeof(u32))) | |
3438 | goto out; | |
e125e7b6 | 3439 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 | 3440 | &emulated_msrs, |
62ef68bb | 3441 | num_emulated_msrs * sizeof(u32))) |
043405e1 CO |
3442 | goto out; |
3443 | r = 0; | |
3444 | break; | |
3445 | } | |
9c15bb1d BP |
3446 | case KVM_GET_SUPPORTED_CPUID: |
3447 | case KVM_GET_EMULATED_CPUID: { | |
674eea0f AK |
3448 | struct kvm_cpuid2 __user *cpuid_arg = argp; |
3449 | struct kvm_cpuid2 cpuid; | |
3450 | ||
3451 | r = -EFAULT; | |
0e96f31e | 3452 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
674eea0f | 3453 | goto out; |
9c15bb1d BP |
3454 | |
3455 | r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, | |
3456 | ioctl); | |
674eea0f AK |
3457 | if (r) |
3458 | goto out; | |
3459 | ||
3460 | r = -EFAULT; | |
0e96f31e | 3461 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) |
674eea0f AK |
3462 | goto out; |
3463 | r = 0; | |
3464 | break; | |
3465 | } | |
890ca9ae | 3466 | case KVM_X86_GET_MCE_CAP_SUPPORTED: { |
890ca9ae | 3467 | r = -EFAULT; |
c45dcc71 AR |
3468 | if (copy_to_user(argp, &kvm_mce_cap_supported, |
3469 | sizeof(kvm_mce_cap_supported))) | |
890ca9ae HY |
3470 | goto out; |
3471 | r = 0; | |
3472 | break; | |
801e459a TL |
3473 | case KVM_GET_MSR_FEATURE_INDEX_LIST: { |
3474 | struct kvm_msr_list __user *user_msr_list = argp; | |
3475 | struct kvm_msr_list msr_list; | |
3476 | unsigned int n; | |
3477 | ||
3478 | r = -EFAULT; | |
3479 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) | |
3480 | goto out; | |
3481 | n = msr_list.nmsrs; | |
3482 | msr_list.nmsrs = num_msr_based_features; | |
3483 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) | |
3484 | goto out; | |
3485 | r = -E2BIG; | |
3486 | if (n < msr_list.nmsrs) | |
3487 | goto out; | |
3488 | r = -EFAULT; | |
3489 | if (copy_to_user(user_msr_list->indices, &msr_based_features, | |
3490 | num_msr_based_features * sizeof(u32))) | |
3491 | goto out; | |
3492 | r = 0; | |
3493 | break; | |
3494 | } | |
3495 | case KVM_GET_MSRS: | |
3496 | r = msr_io(NULL, argp, do_get_msr_feature, 1); | |
3497 | break; | |
890ca9ae | 3498 | } |
043405e1 CO |
3499 | default: |
3500 | r = -EINVAL; | |
3501 | } | |
3502 | out: | |
3503 | return r; | |
3504 | } | |
3505 | ||
f5f48ee1 SY |
3506 | static void wbinvd_ipi(void *garbage) |
3507 | { | |
3508 | wbinvd(); | |
3509 | } | |
3510 | ||
3511 | static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
3512 | { | |
e0f0bbc5 | 3513 | return kvm_arch_has_noncoherent_dma(vcpu->kvm); |
f5f48ee1 SY |
3514 | } |
3515 | ||
313a3dc7 CO |
3516 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
3517 | { | |
f5f48ee1 SY |
3518 | /* Address WBINVD may be executed by guest */ |
3519 | if (need_emulate_wbinvd(vcpu)) { | |
3520 | if (kvm_x86_ops->has_wbinvd_exit()) | |
3521 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
3522 | else if (vcpu->cpu != -1 && vcpu->cpu != cpu) | |
3523 | smp_call_function_single(vcpu->cpu, | |
3524 | wbinvd_ipi, NULL, 1); | |
3525 | } | |
3526 | ||
313a3dc7 | 3527 | kvm_x86_ops->vcpu_load(vcpu, cpu); |
8f6055cb | 3528 | |
0dd6a6ed ZA |
3529 | /* Apply any externally detected TSC adjustments (due to suspend) */ |
3530 | if (unlikely(vcpu->arch.tsc_offset_adjustment)) { | |
3531 | adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); | |
3532 | vcpu->arch.tsc_offset_adjustment = 0; | |
105b21bb | 3533 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed | 3534 | } |
8f6055cb | 3535 | |
b0c39dc6 | 3536 | if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { |
6f526ec5 | 3537 | s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : |
4ea1636b | 3538 | rdtsc() - vcpu->arch.last_host_tsc; |
e48672fa ZA |
3539 | if (tsc_delta < 0) |
3540 | mark_tsc_unstable("KVM discovered backwards TSC"); | |
ce7a058a | 3541 | |
b0c39dc6 | 3542 | if (kvm_check_tsc_unstable()) { |
07c1419a | 3543 | u64 offset = kvm_compute_tsc_offset(vcpu, |
b183aa58 | 3544 | vcpu->arch.last_guest_tsc); |
a545ab6a | 3545 | kvm_vcpu_write_tsc_offset(vcpu, offset); |
c285545f | 3546 | vcpu->arch.tsc_catchup = 1; |
c285545f | 3547 | } |
a749e247 PB |
3548 | |
3549 | if (kvm_lapic_hv_timer_in_use(vcpu)) | |
3550 | kvm_lapic_restart_hv_timer(vcpu); | |
3551 | ||
d98d07ca MT |
3552 | /* |
3553 | * On a host with synchronized TSC, there is no need to update | |
3554 | * kvmclock on vcpu->cpu migration | |
3555 | */ | |
3556 | if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) | |
0061d53d | 3557 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
c285545f | 3558 | if (vcpu->cpu != cpu) |
1bd2009e | 3559 | kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); |
e48672fa | 3560 | vcpu->cpu = cpu; |
6b7d7e76 | 3561 | } |
c9aaa895 | 3562 | |
c9aaa895 | 3563 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
313a3dc7 CO |
3564 | } |
3565 | ||
0b9f6c46 PX |
3566 | static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) |
3567 | { | |
b0431382 BO |
3568 | struct kvm_host_map map; |
3569 | struct kvm_steal_time *st; | |
3570 | ||
0b9f6c46 PX |
3571 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) |
3572 | return; | |
3573 | ||
a6bd811f | 3574 | if (vcpu->arch.st.preempted) |
8c6de56a BO |
3575 | return; |
3576 | ||
b0431382 BO |
3577 | if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map, |
3578 | &vcpu->arch.st.cache, true)) | |
3579 | return; | |
3580 | ||
3581 | st = map.hva + | |
3582 | offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); | |
0b9f6c46 | 3583 | |
a6bd811f | 3584 | st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; |
0b9f6c46 | 3585 | |
b0431382 | 3586 | kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true); |
0b9f6c46 PX |
3587 | } |
3588 | ||
313a3dc7 CO |
3589 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) |
3590 | { | |
cc0d907c | 3591 | int idx; |
de63ad4c LM |
3592 | |
3593 | if (vcpu->preempted) | |
3594 | vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu); | |
3595 | ||
931f261b AA |
3596 | /* |
3597 | * Disable page faults because we're in atomic context here. | |
3598 | * kvm_write_guest_offset_cached() would call might_fault() | |
3599 | * that relies on pagefault_disable() to tell if there's a | |
3600 | * bug. NOTE: the write to guest memory may not go through if | |
3601 | * during postcopy live migration or if there's heavy guest | |
3602 | * paging. | |
3603 | */ | |
3604 | pagefault_disable(); | |
cc0d907c AA |
3605 | /* |
3606 | * kvm_memslots() will be called by | |
3607 | * kvm_write_guest_offset_cached() so take the srcu lock. | |
3608 | */ | |
3609 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
0b9f6c46 | 3610 | kvm_steal_time_set_preempted(vcpu); |
cc0d907c | 3611 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
931f261b | 3612 | pagefault_enable(); |
02daab21 | 3613 | kvm_x86_ops->vcpu_put(vcpu); |
4ea1636b | 3614 | vcpu->arch.last_host_tsc = rdtsc(); |
efdab992 | 3615 | /* |
f9dcf08e RK |
3616 | * If userspace has set any breakpoints or watchpoints, dr6 is restored |
3617 | * on every vmexit, but if not, we might have a stale dr6 from the | |
3618 | * guest. do_debug expects dr6 to be cleared after it runs, do the same. | |
efdab992 | 3619 | */ |
f9dcf08e | 3620 | set_debugreg(0, 6); |
313a3dc7 CO |
3621 | } |
3622 | ||
313a3dc7 CO |
3623 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
3624 | struct kvm_lapic_state *s) | |
3625 | { | |
fa59cc00 | 3626 | if (vcpu->arch.apicv_active) |
d62caabb AS |
3627 | kvm_x86_ops->sync_pir_to_irr(vcpu); |
3628 | ||
a92e2543 | 3629 | return kvm_apic_get_state(vcpu, s); |
313a3dc7 CO |
3630 | } |
3631 | ||
3632 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
3633 | struct kvm_lapic_state *s) | |
3634 | { | |
a92e2543 RK |
3635 | int r; |
3636 | ||
3637 | r = kvm_apic_set_state(vcpu, s); | |
3638 | if (r) | |
3639 | return r; | |
cb142eb7 | 3640 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
3641 | |
3642 | return 0; | |
3643 | } | |
3644 | ||
127a457a MG |
3645 | static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) |
3646 | { | |
3647 | return (!lapic_in_kernel(vcpu) || | |
3648 | kvm_apic_accept_pic_intr(vcpu)); | |
3649 | } | |
3650 | ||
782d422b MG |
3651 | /* |
3652 | * if userspace requested an interrupt window, check that the | |
3653 | * interrupt window is open. | |
3654 | * | |
3655 | * No need to exit to userspace if we already have an interrupt queued. | |
3656 | */ | |
3657 | static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) | |
3658 | { | |
3659 | return kvm_arch_interrupt_allowed(vcpu) && | |
3660 | !kvm_cpu_has_interrupt(vcpu) && | |
3661 | !kvm_event_needs_reinjection(vcpu) && | |
3662 | kvm_cpu_accept_dm_intr(vcpu); | |
3663 | } | |
3664 | ||
f77bc6a4 ZX |
3665 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
3666 | struct kvm_interrupt *irq) | |
3667 | { | |
02cdb50f | 3668 | if (irq->irq >= KVM_NR_INTERRUPTS) |
f77bc6a4 | 3669 | return -EINVAL; |
1c1a9ce9 SR |
3670 | |
3671 | if (!irqchip_in_kernel(vcpu->kvm)) { | |
3672 | kvm_queue_interrupt(vcpu, irq->irq, false); | |
3673 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
3674 | return 0; | |
3675 | } | |
3676 | ||
3677 | /* | |
3678 | * With in-kernel LAPIC, we only use this to inject EXTINT, so | |
3679 | * fail for in-kernel 8259. | |
3680 | */ | |
3681 | if (pic_in_kernel(vcpu->kvm)) | |
f77bc6a4 | 3682 | return -ENXIO; |
f77bc6a4 | 3683 | |
1c1a9ce9 SR |
3684 | if (vcpu->arch.pending_external_vector != -1) |
3685 | return -EEXIST; | |
f77bc6a4 | 3686 | |
1c1a9ce9 | 3687 | vcpu->arch.pending_external_vector = irq->irq; |
934bf653 | 3688 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f77bc6a4 ZX |
3689 | return 0; |
3690 | } | |
3691 | ||
c4abb7c9 JK |
3692 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
3693 | { | |
c4abb7c9 | 3694 | kvm_inject_nmi(vcpu); |
c4abb7c9 JK |
3695 | |
3696 | return 0; | |
3697 | } | |
3698 | ||
f077825a PB |
3699 | static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) |
3700 | { | |
64d60670 PB |
3701 | kvm_make_request(KVM_REQ_SMI, vcpu); |
3702 | ||
f077825a PB |
3703 | return 0; |
3704 | } | |
3705 | ||
b209749f AK |
3706 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
3707 | struct kvm_tpr_access_ctl *tac) | |
3708 | { | |
3709 | if (tac->flags) | |
3710 | return -EINVAL; | |
3711 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
3712 | return 0; | |
3713 | } | |
3714 | ||
890ca9ae HY |
3715 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
3716 | u64 mcg_cap) | |
3717 | { | |
3718 | int r; | |
3719 | unsigned bank_num = mcg_cap & 0xff, bank; | |
3720 | ||
3721 | r = -EINVAL; | |
a9e38c3e | 3722 | if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) |
890ca9ae | 3723 | goto out; |
c45dcc71 | 3724 | if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) |
890ca9ae HY |
3725 | goto out; |
3726 | r = 0; | |
3727 | vcpu->arch.mcg_cap = mcg_cap; | |
3728 | /* Init IA32_MCG_CTL to all 1s */ | |
3729 | if (mcg_cap & MCG_CTL_P) | |
3730 | vcpu->arch.mcg_ctl = ~(u64)0; | |
3731 | /* Init IA32_MCi_CTL to all 1s */ | |
3732 | for (bank = 0; bank < bank_num; bank++) | |
3733 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
c45dcc71 | 3734 | |
92735b1b | 3735 | kvm_x86_ops->setup_mce(vcpu); |
890ca9ae HY |
3736 | out: |
3737 | return r; | |
3738 | } | |
3739 | ||
3740 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
3741 | struct kvm_x86_mce *mce) | |
3742 | { | |
3743 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
3744 | unsigned bank_num = mcg_cap & 0xff; | |
3745 | u64 *banks = vcpu->arch.mce_banks; | |
3746 | ||
3747 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
3748 | return -EINVAL; | |
3749 | /* | |
3750 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
3751 | * reporting is disabled | |
3752 | */ | |
3753 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
3754 | vcpu->arch.mcg_ctl != ~(u64)0) | |
3755 | return 0; | |
3756 | banks += 4 * mce->bank; | |
3757 | /* | |
3758 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
3759 | * reporting is disabled for the bank | |
3760 | */ | |
3761 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
3762 | return 0; | |
3763 | if (mce->status & MCI_STATUS_UC) { | |
3764 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
fc78f519 | 3765 | !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { |
a8eeb04a | 3766 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
890ca9ae HY |
3767 | return 0; |
3768 | } | |
3769 | if (banks[1] & MCI_STATUS_VAL) | |
3770 | mce->status |= MCI_STATUS_OVER; | |
3771 | banks[2] = mce->addr; | |
3772 | banks[3] = mce->misc; | |
3773 | vcpu->arch.mcg_status = mce->mcg_status; | |
3774 | banks[1] = mce->status; | |
3775 | kvm_queue_exception(vcpu, MC_VECTOR); | |
3776 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
3777 | || !(banks[1] & MCI_STATUS_UC)) { | |
3778 | if (banks[1] & MCI_STATUS_VAL) | |
3779 | mce->status |= MCI_STATUS_OVER; | |
3780 | banks[2] = mce->addr; | |
3781 | banks[3] = mce->misc; | |
3782 | banks[1] = mce->status; | |
3783 | } else | |
3784 | banks[1] |= MCI_STATUS_OVER; | |
3785 | return 0; | |
3786 | } | |
3787 | ||
3cfc3092 JK |
3788 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
3789 | struct kvm_vcpu_events *events) | |
3790 | { | |
7460fb4a | 3791 | process_nmi(vcpu); |
59073aaf | 3792 | |
664f8e26 | 3793 | /* |
59073aaf JM |
3794 | * The API doesn't provide the instruction length for software |
3795 | * exceptions, so don't report them. As long as the guest RIP | |
3796 | * isn't advanced, we should expect to encounter the exception | |
3797 | * again. | |
664f8e26 | 3798 | */ |
59073aaf JM |
3799 | if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { |
3800 | events->exception.injected = 0; | |
3801 | events->exception.pending = 0; | |
3802 | } else { | |
3803 | events->exception.injected = vcpu->arch.exception.injected; | |
3804 | events->exception.pending = vcpu->arch.exception.pending; | |
3805 | /* | |
3806 | * For ABI compatibility, deliberately conflate | |
3807 | * pending and injected exceptions when | |
3808 | * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. | |
3809 | */ | |
3810 | if (!vcpu->kvm->arch.exception_payload_enabled) | |
3811 | events->exception.injected |= | |
3812 | vcpu->arch.exception.pending; | |
3813 | } | |
3cfc3092 JK |
3814 | events->exception.nr = vcpu->arch.exception.nr; |
3815 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
3816 | events->exception.error_code = vcpu->arch.exception.error_code; | |
59073aaf JM |
3817 | events->exception_has_payload = vcpu->arch.exception.has_payload; |
3818 | events->exception_payload = vcpu->arch.exception.payload; | |
3cfc3092 | 3819 | |
03b82a30 | 3820 | events->interrupt.injected = |
04140b41 | 3821 | vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; |
3cfc3092 | 3822 | events->interrupt.nr = vcpu->arch.interrupt.nr; |
03b82a30 | 3823 | events->interrupt.soft = 0; |
37ccdcbe | 3824 | events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); |
3cfc3092 JK |
3825 | |
3826 | events->nmi.injected = vcpu->arch.nmi_injected; | |
7460fb4a | 3827 | events->nmi.pending = vcpu->arch.nmi_pending != 0; |
3cfc3092 | 3828 | events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); |
97e69aa6 | 3829 | events->nmi.pad = 0; |
3cfc3092 | 3830 | |
66450a21 | 3831 | events->sipi_vector = 0; /* never valid when reporting to user space */ |
3cfc3092 | 3832 | |
f077825a PB |
3833 | events->smi.smm = is_smm(vcpu); |
3834 | events->smi.pending = vcpu->arch.smi_pending; | |
3835 | events->smi.smm_inside_nmi = | |
3836 | !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); | |
3837 | events->smi.latched_init = kvm_lapic_latched_init(vcpu); | |
3838 | ||
dab4b911 | 3839 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
f077825a PB |
3840 | | KVM_VCPUEVENT_VALID_SHADOW |
3841 | | KVM_VCPUEVENT_VALID_SMM); | |
59073aaf JM |
3842 | if (vcpu->kvm->arch.exception_payload_enabled) |
3843 | events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; | |
3844 | ||
97e69aa6 | 3845 | memset(&events->reserved, 0, sizeof(events->reserved)); |
3cfc3092 JK |
3846 | } |
3847 | ||
c5833c7a | 3848 | static void kvm_smm_changed(struct kvm_vcpu *vcpu); |
6ef4e07e | 3849 | |
3cfc3092 JK |
3850 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, |
3851 | struct kvm_vcpu_events *events) | |
3852 | { | |
dab4b911 | 3853 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 | 3854 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
f077825a | 3855 | | KVM_VCPUEVENT_VALID_SHADOW |
59073aaf JM |
3856 | | KVM_VCPUEVENT_VALID_SMM |
3857 | | KVM_VCPUEVENT_VALID_PAYLOAD)) | |
3cfc3092 JK |
3858 | return -EINVAL; |
3859 | ||
59073aaf JM |
3860 | if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { |
3861 | if (!vcpu->kvm->arch.exception_payload_enabled) | |
3862 | return -EINVAL; | |
3863 | if (events->exception.pending) | |
3864 | events->exception.injected = 0; | |
3865 | else | |
3866 | events->exception_has_payload = 0; | |
3867 | } else { | |
3868 | events->exception.pending = 0; | |
3869 | events->exception_has_payload = 0; | |
3870 | } | |
3871 | ||
3872 | if ((events->exception.injected || events->exception.pending) && | |
3873 | (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) | |
78e546c8 PB |
3874 | return -EINVAL; |
3875 | ||
28bf2888 DH |
3876 | /* INITs are latched while in SMM */ |
3877 | if (events->flags & KVM_VCPUEVENT_VALID_SMM && | |
3878 | (events->smi.smm || events->smi.pending) && | |
3879 | vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) | |
3880 | return -EINVAL; | |
3881 | ||
7460fb4a | 3882 | process_nmi(vcpu); |
59073aaf JM |
3883 | vcpu->arch.exception.injected = events->exception.injected; |
3884 | vcpu->arch.exception.pending = events->exception.pending; | |
3cfc3092 JK |
3885 | vcpu->arch.exception.nr = events->exception.nr; |
3886 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
3887 | vcpu->arch.exception.error_code = events->exception.error_code; | |
59073aaf JM |
3888 | vcpu->arch.exception.has_payload = events->exception_has_payload; |
3889 | vcpu->arch.exception.payload = events->exception_payload; | |
3cfc3092 | 3890 | |
04140b41 | 3891 | vcpu->arch.interrupt.injected = events->interrupt.injected; |
3cfc3092 JK |
3892 | vcpu->arch.interrupt.nr = events->interrupt.nr; |
3893 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
48005f64 JK |
3894 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) |
3895 | kvm_x86_ops->set_interrupt_shadow(vcpu, | |
3896 | events->interrupt.shadow); | |
3cfc3092 JK |
3897 | |
3898 | vcpu->arch.nmi_injected = events->nmi.injected; | |
dab4b911 JK |
3899 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) |
3900 | vcpu->arch.nmi_pending = events->nmi.pending; | |
3cfc3092 JK |
3901 | kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); |
3902 | ||
66450a21 | 3903 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && |
bce87cce | 3904 | lapic_in_kernel(vcpu)) |
66450a21 | 3905 | vcpu->arch.apic->sipi_vector = events->sipi_vector; |
3cfc3092 | 3906 | |
f077825a | 3907 | if (events->flags & KVM_VCPUEVENT_VALID_SMM) { |
c5833c7a SC |
3908 | if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) { |
3909 | if (events->smi.smm) | |
3910 | vcpu->arch.hflags |= HF_SMM_MASK; | |
3911 | else | |
3912 | vcpu->arch.hflags &= ~HF_SMM_MASK; | |
3913 | kvm_smm_changed(vcpu); | |
3914 | } | |
6ef4e07e | 3915 | |
f077825a | 3916 | vcpu->arch.smi_pending = events->smi.pending; |
f4ef1910 WL |
3917 | |
3918 | if (events->smi.smm) { | |
3919 | if (events->smi.smm_inside_nmi) | |
3920 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; | |
f077825a | 3921 | else |
f4ef1910 | 3922 | vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; |
ff90afa7 LA |
3923 | } |
3924 | ||
3925 | if (lapic_in_kernel(vcpu)) { | |
3926 | if (events->smi.latched_init) | |
3927 | set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
3928 | else | |
3929 | clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
f077825a PB |
3930 | } |
3931 | } | |
3932 | ||
3842d135 AK |
3933 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
3934 | ||
3cfc3092 JK |
3935 | return 0; |
3936 | } | |
3937 | ||
a1efbe77 JK |
3938 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, |
3939 | struct kvm_debugregs *dbgregs) | |
3940 | { | |
73aaf249 JK |
3941 | unsigned long val; |
3942 | ||
a1efbe77 | 3943 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); |
16f8a6f9 | 3944 | kvm_get_dr(vcpu, 6, &val); |
73aaf249 | 3945 | dbgregs->dr6 = val; |
a1efbe77 JK |
3946 | dbgregs->dr7 = vcpu->arch.dr7; |
3947 | dbgregs->flags = 0; | |
97e69aa6 | 3948 | memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); |
a1efbe77 JK |
3949 | } |
3950 | ||
3951 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
3952 | struct kvm_debugregs *dbgregs) | |
3953 | { | |
3954 | if (dbgregs->flags) | |
3955 | return -EINVAL; | |
3956 | ||
d14bdb55 PB |
3957 | if (dbgregs->dr6 & ~0xffffffffull) |
3958 | return -EINVAL; | |
3959 | if (dbgregs->dr7 & ~0xffffffffull) | |
3960 | return -EINVAL; | |
3961 | ||
a1efbe77 | 3962 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); |
ae561ede | 3963 | kvm_update_dr0123(vcpu); |
a1efbe77 | 3964 | vcpu->arch.dr6 = dbgregs->dr6; |
73aaf249 | 3965 | kvm_update_dr6(vcpu); |
a1efbe77 | 3966 | vcpu->arch.dr7 = dbgregs->dr7; |
9926c9fd | 3967 | kvm_update_dr7(vcpu); |
a1efbe77 | 3968 | |
a1efbe77 JK |
3969 | return 0; |
3970 | } | |
3971 | ||
df1daba7 PB |
3972 | #define XSTATE_COMPACTION_ENABLED (1ULL << 63) |
3973 | ||
3974 | static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) | |
3975 | { | |
b666a4b6 | 3976 | struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; |
400e4b20 | 3977 | u64 xstate_bv = xsave->header.xfeatures; |
df1daba7 PB |
3978 | u64 valid; |
3979 | ||
3980 | /* | |
3981 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
3982 | * leaves 0 and 1 in the loop below. | |
3983 | */ | |
3984 | memcpy(dest, xsave, XSAVE_HDR_OFFSET); | |
3985 | ||
3986 | /* Set XSTATE_BV */ | |
00c87e9a | 3987 | xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE; |
df1daba7 PB |
3988 | *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; |
3989 | ||
3990 | /* | |
3991 | * Copy each region from the possibly compacted offset to the | |
3992 | * non-compacted offset. | |
3993 | */ | |
d91cab78 | 3994 | valid = xstate_bv & ~XFEATURE_MASK_FPSSE; |
df1daba7 | 3995 | while (valid) { |
abd16d68 SAS |
3996 | u64 xfeature_mask = valid & -valid; |
3997 | int xfeature_nr = fls64(xfeature_mask) - 1; | |
3998 | void *src = get_xsave_addr(xsave, xfeature_nr); | |
df1daba7 PB |
3999 | |
4000 | if (src) { | |
4001 | u32 size, offset, ecx, edx; | |
abd16d68 | 4002 | cpuid_count(XSTATE_CPUID, xfeature_nr, |
df1daba7 | 4003 | &size, &offset, &ecx, &edx); |
abd16d68 | 4004 | if (xfeature_nr == XFEATURE_PKRU) |
38cfd5e3 PB |
4005 | memcpy(dest + offset, &vcpu->arch.pkru, |
4006 | sizeof(vcpu->arch.pkru)); | |
4007 | else | |
4008 | memcpy(dest + offset, src, size); | |
4009 | ||
df1daba7 PB |
4010 | } |
4011 | ||
abd16d68 | 4012 | valid -= xfeature_mask; |
df1daba7 PB |
4013 | } |
4014 | } | |
4015 | ||
4016 | static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) | |
4017 | { | |
b666a4b6 | 4018 | struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; |
df1daba7 PB |
4019 | u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); |
4020 | u64 valid; | |
4021 | ||
4022 | /* | |
4023 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
4024 | * leaves 0 and 1 in the loop below. | |
4025 | */ | |
4026 | memcpy(xsave, src, XSAVE_HDR_OFFSET); | |
4027 | ||
4028 | /* Set XSTATE_BV and possibly XCOMP_BV. */ | |
400e4b20 | 4029 | xsave->header.xfeatures = xstate_bv; |
782511b0 | 4030 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
3a54450b | 4031 | xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; |
df1daba7 PB |
4032 | |
4033 | /* | |
4034 | * Copy each region from the non-compacted offset to the | |
4035 | * possibly compacted offset. | |
4036 | */ | |
d91cab78 | 4037 | valid = xstate_bv & ~XFEATURE_MASK_FPSSE; |
df1daba7 | 4038 | while (valid) { |
abd16d68 SAS |
4039 | u64 xfeature_mask = valid & -valid; |
4040 | int xfeature_nr = fls64(xfeature_mask) - 1; | |
4041 | void *dest = get_xsave_addr(xsave, xfeature_nr); | |
df1daba7 PB |
4042 | |
4043 | if (dest) { | |
4044 | u32 size, offset, ecx, edx; | |
abd16d68 | 4045 | cpuid_count(XSTATE_CPUID, xfeature_nr, |
df1daba7 | 4046 | &size, &offset, &ecx, &edx); |
abd16d68 | 4047 | if (xfeature_nr == XFEATURE_PKRU) |
38cfd5e3 PB |
4048 | memcpy(&vcpu->arch.pkru, src + offset, |
4049 | sizeof(vcpu->arch.pkru)); | |
4050 | else | |
4051 | memcpy(dest, src + offset, size); | |
ee4100da | 4052 | } |
df1daba7 | 4053 | |
abd16d68 | 4054 | valid -= xfeature_mask; |
df1daba7 PB |
4055 | } |
4056 | } | |
4057 | ||
2d5b5a66 SY |
4058 | static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, |
4059 | struct kvm_xsave *guest_xsave) | |
4060 | { | |
d366bf7e | 4061 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
df1daba7 PB |
4062 | memset(guest_xsave, 0, sizeof(struct kvm_xsave)); |
4063 | fill_xsave((u8 *) guest_xsave->region, vcpu); | |
4344ee98 | 4064 | } else { |
2d5b5a66 | 4065 | memcpy(guest_xsave->region, |
b666a4b6 | 4066 | &vcpu->arch.guest_fpu->state.fxsave, |
c47ada30 | 4067 | sizeof(struct fxregs_state)); |
2d5b5a66 | 4068 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = |
d91cab78 | 4069 | XFEATURE_MASK_FPSSE; |
2d5b5a66 SY |
4070 | } |
4071 | } | |
4072 | ||
a575813b WL |
4073 | #define XSAVE_MXCSR_OFFSET 24 |
4074 | ||
2d5b5a66 SY |
4075 | static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, |
4076 | struct kvm_xsave *guest_xsave) | |
4077 | { | |
4078 | u64 xstate_bv = | |
4079 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; | |
a575813b | 4080 | u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)]; |
2d5b5a66 | 4081 | |
d366bf7e | 4082 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
d7876f1b PB |
4083 | /* |
4084 | * Here we allow setting states that are not present in | |
4085 | * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility | |
4086 | * with old userspace. | |
4087 | */ | |
a575813b WL |
4088 | if (xstate_bv & ~kvm_supported_xcr0() || |
4089 | mxcsr & ~mxcsr_feature_mask) | |
d7876f1b | 4090 | return -EINVAL; |
df1daba7 | 4091 | load_xsave(vcpu, (u8 *)guest_xsave->region); |
d7876f1b | 4092 | } else { |
a575813b WL |
4093 | if (xstate_bv & ~XFEATURE_MASK_FPSSE || |
4094 | mxcsr & ~mxcsr_feature_mask) | |
2d5b5a66 | 4095 | return -EINVAL; |
b666a4b6 | 4096 | memcpy(&vcpu->arch.guest_fpu->state.fxsave, |
c47ada30 | 4097 | guest_xsave->region, sizeof(struct fxregs_state)); |
2d5b5a66 SY |
4098 | } |
4099 | return 0; | |
4100 | } | |
4101 | ||
4102 | static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, | |
4103 | struct kvm_xcrs *guest_xcrs) | |
4104 | { | |
d366bf7e | 4105 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) { |
2d5b5a66 SY |
4106 | guest_xcrs->nr_xcrs = 0; |
4107 | return; | |
4108 | } | |
4109 | ||
4110 | guest_xcrs->nr_xcrs = 1; | |
4111 | guest_xcrs->flags = 0; | |
4112 | guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; | |
4113 | guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; | |
4114 | } | |
4115 | ||
4116 | static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, | |
4117 | struct kvm_xcrs *guest_xcrs) | |
4118 | { | |
4119 | int i, r = 0; | |
4120 | ||
d366bf7e | 4121 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) |
2d5b5a66 SY |
4122 | return -EINVAL; |
4123 | ||
4124 | if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) | |
4125 | return -EINVAL; | |
4126 | ||
4127 | for (i = 0; i < guest_xcrs->nr_xcrs; i++) | |
4128 | /* Only support XCR0 currently */ | |
c67a04cb | 4129 | if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { |
2d5b5a66 | 4130 | r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, |
c67a04cb | 4131 | guest_xcrs->xcrs[i].value); |
2d5b5a66 SY |
4132 | break; |
4133 | } | |
4134 | if (r) | |
4135 | r = -EINVAL; | |
4136 | return r; | |
4137 | } | |
4138 | ||
1c0b28c2 EM |
4139 | /* |
4140 | * kvm_set_guest_paused() indicates to the guest kernel that it has been | |
4141 | * stopped by the hypervisor. This function will be called from the host only. | |
4142 | * EINVAL is returned when the host attempts to set the flag for a guest that | |
4143 | * does not support pv clocks. | |
4144 | */ | |
4145 | static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) | |
4146 | { | |
0b79459b | 4147 | if (!vcpu->arch.pv_time_enabled) |
1c0b28c2 | 4148 | return -EINVAL; |
51d59c6b | 4149 | vcpu->arch.pvclock_set_guest_stopped_request = true; |
1c0b28c2 EM |
4150 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
4151 | return 0; | |
4152 | } | |
4153 | ||
5c919412 AS |
4154 | static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, |
4155 | struct kvm_enable_cap *cap) | |
4156 | { | |
57b119da VK |
4157 | int r; |
4158 | uint16_t vmcs_version; | |
4159 | void __user *user_ptr; | |
4160 | ||
5c919412 AS |
4161 | if (cap->flags) |
4162 | return -EINVAL; | |
4163 | ||
4164 | switch (cap->cap) { | |
efc479e6 RK |
4165 | case KVM_CAP_HYPERV_SYNIC2: |
4166 | if (cap->args[0]) | |
4167 | return -EINVAL; | |
b2869f28 GS |
4168 | /* fall through */ |
4169 | ||
5c919412 | 4170 | case KVM_CAP_HYPERV_SYNIC: |
546d87e5 WL |
4171 | if (!irqchip_in_kernel(vcpu->kvm)) |
4172 | return -EINVAL; | |
efc479e6 RK |
4173 | return kvm_hv_activate_synic(vcpu, cap->cap == |
4174 | KVM_CAP_HYPERV_SYNIC2); | |
57b119da | 4175 | case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: |
5158917c SC |
4176 | if (!kvm_x86_ops->nested_enable_evmcs) |
4177 | return -ENOTTY; | |
57b119da VK |
4178 | r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version); |
4179 | if (!r) { | |
4180 | user_ptr = (void __user *)(uintptr_t)cap->args[0]; | |
4181 | if (copy_to_user(user_ptr, &vmcs_version, | |
4182 | sizeof(vmcs_version))) | |
4183 | r = -EFAULT; | |
4184 | } | |
4185 | return r; | |
344c6c80 TL |
4186 | case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: |
4187 | if (!kvm_x86_ops->enable_direct_tlbflush) | |
4188 | return -ENOTTY; | |
4189 | ||
4190 | return kvm_x86_ops->enable_direct_tlbflush(vcpu); | |
57b119da | 4191 | |
5c919412 AS |
4192 | default: |
4193 | return -EINVAL; | |
4194 | } | |
4195 | } | |
4196 | ||
313a3dc7 CO |
4197 | long kvm_arch_vcpu_ioctl(struct file *filp, |
4198 | unsigned int ioctl, unsigned long arg) | |
4199 | { | |
4200 | struct kvm_vcpu *vcpu = filp->private_data; | |
4201 | void __user *argp = (void __user *)arg; | |
4202 | int r; | |
d1ac91d8 AK |
4203 | union { |
4204 | struct kvm_lapic_state *lapic; | |
4205 | struct kvm_xsave *xsave; | |
4206 | struct kvm_xcrs *xcrs; | |
4207 | void *buffer; | |
4208 | } u; | |
4209 | ||
9b062471 CD |
4210 | vcpu_load(vcpu); |
4211 | ||
d1ac91d8 | 4212 | u.buffer = NULL; |
313a3dc7 CO |
4213 | switch (ioctl) { |
4214 | case KVM_GET_LAPIC: { | |
2204ae3c | 4215 | r = -EINVAL; |
bce87cce | 4216 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 4217 | goto out; |
254272ce BG |
4218 | u.lapic = kzalloc(sizeof(struct kvm_lapic_state), |
4219 | GFP_KERNEL_ACCOUNT); | |
313a3dc7 | 4220 | |
b772ff36 | 4221 | r = -ENOMEM; |
d1ac91d8 | 4222 | if (!u.lapic) |
b772ff36 | 4223 | goto out; |
d1ac91d8 | 4224 | r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); |
313a3dc7 CO |
4225 | if (r) |
4226 | goto out; | |
4227 | r = -EFAULT; | |
d1ac91d8 | 4228 | if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
4229 | goto out; |
4230 | r = 0; | |
4231 | break; | |
4232 | } | |
4233 | case KVM_SET_LAPIC: { | |
2204ae3c | 4234 | r = -EINVAL; |
bce87cce | 4235 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 4236 | goto out; |
ff5c2c03 | 4237 | u.lapic = memdup_user(argp, sizeof(*u.lapic)); |
9b062471 CD |
4238 | if (IS_ERR(u.lapic)) { |
4239 | r = PTR_ERR(u.lapic); | |
4240 | goto out_nofree; | |
4241 | } | |
ff5c2c03 | 4242 | |
d1ac91d8 | 4243 | r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); |
313a3dc7 CO |
4244 | break; |
4245 | } | |
f77bc6a4 ZX |
4246 | case KVM_INTERRUPT: { |
4247 | struct kvm_interrupt irq; | |
4248 | ||
4249 | r = -EFAULT; | |
0e96f31e | 4250 | if (copy_from_user(&irq, argp, sizeof(irq))) |
f77bc6a4 ZX |
4251 | goto out; |
4252 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
f77bc6a4 ZX |
4253 | break; |
4254 | } | |
c4abb7c9 JK |
4255 | case KVM_NMI: { |
4256 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
c4abb7c9 JK |
4257 | break; |
4258 | } | |
f077825a PB |
4259 | case KVM_SMI: { |
4260 | r = kvm_vcpu_ioctl_smi(vcpu); | |
4261 | break; | |
4262 | } | |
313a3dc7 CO |
4263 | case KVM_SET_CPUID: { |
4264 | struct kvm_cpuid __user *cpuid_arg = argp; | |
4265 | struct kvm_cpuid cpuid; | |
4266 | ||
4267 | r = -EFAULT; | |
0e96f31e | 4268 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
313a3dc7 CO |
4269 | goto out; |
4270 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
313a3dc7 CO |
4271 | break; |
4272 | } | |
07716717 DK |
4273 | case KVM_SET_CPUID2: { |
4274 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
4275 | struct kvm_cpuid2 cpuid; | |
4276 | ||
4277 | r = -EFAULT; | |
0e96f31e | 4278 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
07716717 DK |
4279 | goto out; |
4280 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 4281 | cpuid_arg->entries); |
07716717 DK |
4282 | break; |
4283 | } | |
4284 | case KVM_GET_CPUID2: { | |
4285 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
4286 | struct kvm_cpuid2 cpuid; | |
4287 | ||
4288 | r = -EFAULT; | |
0e96f31e | 4289 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
07716717 DK |
4290 | goto out; |
4291 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 4292 | cpuid_arg->entries); |
07716717 DK |
4293 | if (r) |
4294 | goto out; | |
4295 | r = -EFAULT; | |
0e96f31e | 4296 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) |
07716717 DK |
4297 | goto out; |
4298 | r = 0; | |
4299 | break; | |
4300 | } | |
801e459a TL |
4301 | case KVM_GET_MSRS: { |
4302 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
609e36d3 | 4303 | r = msr_io(vcpu, argp, do_get_msr, 1); |
801e459a | 4304 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 4305 | break; |
801e459a TL |
4306 | } |
4307 | case KVM_SET_MSRS: { | |
4308 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
313a3dc7 | 4309 | r = msr_io(vcpu, argp, do_set_msr, 0); |
801e459a | 4310 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 4311 | break; |
801e459a | 4312 | } |
b209749f AK |
4313 | case KVM_TPR_ACCESS_REPORTING: { |
4314 | struct kvm_tpr_access_ctl tac; | |
4315 | ||
4316 | r = -EFAULT; | |
0e96f31e | 4317 | if (copy_from_user(&tac, argp, sizeof(tac))) |
b209749f AK |
4318 | goto out; |
4319 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
4320 | if (r) | |
4321 | goto out; | |
4322 | r = -EFAULT; | |
0e96f31e | 4323 | if (copy_to_user(argp, &tac, sizeof(tac))) |
b209749f AK |
4324 | goto out; |
4325 | r = 0; | |
4326 | break; | |
4327 | }; | |
b93463aa AK |
4328 | case KVM_SET_VAPIC_ADDR: { |
4329 | struct kvm_vapic_addr va; | |
7301d6ab | 4330 | int idx; |
b93463aa AK |
4331 | |
4332 | r = -EINVAL; | |
35754c98 | 4333 | if (!lapic_in_kernel(vcpu)) |
b93463aa AK |
4334 | goto out; |
4335 | r = -EFAULT; | |
0e96f31e | 4336 | if (copy_from_user(&va, argp, sizeof(va))) |
b93463aa | 4337 | goto out; |
7301d6ab | 4338 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
fda4e2e8 | 4339 | r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); |
7301d6ab | 4340 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b93463aa AK |
4341 | break; |
4342 | } | |
890ca9ae HY |
4343 | case KVM_X86_SETUP_MCE: { |
4344 | u64 mcg_cap; | |
4345 | ||
4346 | r = -EFAULT; | |
0e96f31e | 4347 | if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) |
890ca9ae HY |
4348 | goto out; |
4349 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
4350 | break; | |
4351 | } | |
4352 | case KVM_X86_SET_MCE: { | |
4353 | struct kvm_x86_mce mce; | |
4354 | ||
4355 | r = -EFAULT; | |
0e96f31e | 4356 | if (copy_from_user(&mce, argp, sizeof(mce))) |
890ca9ae HY |
4357 | goto out; |
4358 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
4359 | break; | |
4360 | } | |
3cfc3092 JK |
4361 | case KVM_GET_VCPU_EVENTS: { |
4362 | struct kvm_vcpu_events events; | |
4363 | ||
4364 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
4365 | ||
4366 | r = -EFAULT; | |
4367 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
4368 | break; | |
4369 | r = 0; | |
4370 | break; | |
4371 | } | |
4372 | case KVM_SET_VCPU_EVENTS: { | |
4373 | struct kvm_vcpu_events events; | |
4374 | ||
4375 | r = -EFAULT; | |
4376 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
4377 | break; | |
4378 | ||
4379 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
4380 | break; | |
4381 | } | |
a1efbe77 JK |
4382 | case KVM_GET_DEBUGREGS: { |
4383 | struct kvm_debugregs dbgregs; | |
4384 | ||
4385 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
4386 | ||
4387 | r = -EFAULT; | |
4388 | if (copy_to_user(argp, &dbgregs, | |
4389 | sizeof(struct kvm_debugregs))) | |
4390 | break; | |
4391 | r = 0; | |
4392 | break; | |
4393 | } | |
4394 | case KVM_SET_DEBUGREGS: { | |
4395 | struct kvm_debugregs dbgregs; | |
4396 | ||
4397 | r = -EFAULT; | |
4398 | if (copy_from_user(&dbgregs, argp, | |
4399 | sizeof(struct kvm_debugregs))) | |
4400 | break; | |
4401 | ||
4402 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
4403 | break; | |
4404 | } | |
2d5b5a66 | 4405 | case KVM_GET_XSAVE: { |
254272ce | 4406 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); |
2d5b5a66 | 4407 | r = -ENOMEM; |
d1ac91d8 | 4408 | if (!u.xsave) |
2d5b5a66 SY |
4409 | break; |
4410 | ||
d1ac91d8 | 4411 | kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
4412 | |
4413 | r = -EFAULT; | |
d1ac91d8 | 4414 | if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
4415 | break; |
4416 | r = 0; | |
4417 | break; | |
4418 | } | |
4419 | case KVM_SET_XSAVE: { | |
ff5c2c03 | 4420 | u.xsave = memdup_user(argp, sizeof(*u.xsave)); |
9b062471 CD |
4421 | if (IS_ERR(u.xsave)) { |
4422 | r = PTR_ERR(u.xsave); | |
4423 | goto out_nofree; | |
4424 | } | |
2d5b5a66 | 4425 | |
d1ac91d8 | 4426 | r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
4427 | break; |
4428 | } | |
4429 | case KVM_GET_XCRS: { | |
254272ce | 4430 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); |
2d5b5a66 | 4431 | r = -ENOMEM; |
d1ac91d8 | 4432 | if (!u.xcrs) |
2d5b5a66 SY |
4433 | break; |
4434 | ||
d1ac91d8 | 4435 | kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
4436 | |
4437 | r = -EFAULT; | |
d1ac91d8 | 4438 | if (copy_to_user(argp, u.xcrs, |
2d5b5a66 SY |
4439 | sizeof(struct kvm_xcrs))) |
4440 | break; | |
4441 | r = 0; | |
4442 | break; | |
4443 | } | |
4444 | case KVM_SET_XCRS: { | |
ff5c2c03 | 4445 | u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); |
9b062471 CD |
4446 | if (IS_ERR(u.xcrs)) { |
4447 | r = PTR_ERR(u.xcrs); | |
4448 | goto out_nofree; | |
4449 | } | |
2d5b5a66 | 4450 | |
d1ac91d8 | 4451 | r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
4452 | break; |
4453 | } | |
92a1f12d JR |
4454 | case KVM_SET_TSC_KHZ: { |
4455 | u32 user_tsc_khz; | |
4456 | ||
4457 | r = -EINVAL; | |
92a1f12d JR |
4458 | user_tsc_khz = (u32)arg; |
4459 | ||
4460 | if (user_tsc_khz >= kvm_max_guest_tsc_khz) | |
4461 | goto out; | |
4462 | ||
cc578287 ZA |
4463 | if (user_tsc_khz == 0) |
4464 | user_tsc_khz = tsc_khz; | |
4465 | ||
381d585c HZ |
4466 | if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) |
4467 | r = 0; | |
92a1f12d | 4468 | |
92a1f12d JR |
4469 | goto out; |
4470 | } | |
4471 | case KVM_GET_TSC_KHZ: { | |
cc578287 | 4472 | r = vcpu->arch.virtual_tsc_khz; |
92a1f12d JR |
4473 | goto out; |
4474 | } | |
1c0b28c2 EM |
4475 | case KVM_KVMCLOCK_CTRL: { |
4476 | r = kvm_set_guest_paused(vcpu); | |
4477 | goto out; | |
4478 | } | |
5c919412 AS |
4479 | case KVM_ENABLE_CAP: { |
4480 | struct kvm_enable_cap cap; | |
4481 | ||
4482 | r = -EFAULT; | |
4483 | if (copy_from_user(&cap, argp, sizeof(cap))) | |
4484 | goto out; | |
4485 | r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); | |
4486 | break; | |
4487 | } | |
8fcc4b59 JM |
4488 | case KVM_GET_NESTED_STATE: { |
4489 | struct kvm_nested_state __user *user_kvm_nested_state = argp; | |
4490 | u32 user_data_size; | |
4491 | ||
4492 | r = -EINVAL; | |
4493 | if (!kvm_x86_ops->get_nested_state) | |
4494 | break; | |
4495 | ||
4496 | BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); | |
26b471c7 | 4497 | r = -EFAULT; |
8fcc4b59 | 4498 | if (get_user(user_data_size, &user_kvm_nested_state->size)) |
26b471c7 | 4499 | break; |
8fcc4b59 JM |
4500 | |
4501 | r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state, | |
4502 | user_data_size); | |
4503 | if (r < 0) | |
26b471c7 | 4504 | break; |
8fcc4b59 JM |
4505 | |
4506 | if (r > user_data_size) { | |
4507 | if (put_user(r, &user_kvm_nested_state->size)) | |
26b471c7 LA |
4508 | r = -EFAULT; |
4509 | else | |
4510 | r = -E2BIG; | |
4511 | break; | |
8fcc4b59 | 4512 | } |
26b471c7 | 4513 | |
8fcc4b59 JM |
4514 | r = 0; |
4515 | break; | |
4516 | } | |
4517 | case KVM_SET_NESTED_STATE: { | |
4518 | struct kvm_nested_state __user *user_kvm_nested_state = argp; | |
4519 | struct kvm_nested_state kvm_state; | |
ad5996d9 | 4520 | int idx; |
8fcc4b59 JM |
4521 | |
4522 | r = -EINVAL; | |
4523 | if (!kvm_x86_ops->set_nested_state) | |
4524 | break; | |
4525 | ||
26b471c7 | 4526 | r = -EFAULT; |
8fcc4b59 | 4527 | if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) |
26b471c7 | 4528 | break; |
8fcc4b59 | 4529 | |
26b471c7 | 4530 | r = -EINVAL; |
8fcc4b59 | 4531 | if (kvm_state.size < sizeof(kvm_state)) |
26b471c7 | 4532 | break; |
8fcc4b59 JM |
4533 | |
4534 | if (kvm_state.flags & | |
8cab6507 VK |
4535 | ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE |
4536 | | KVM_STATE_NESTED_EVMCS)) | |
26b471c7 | 4537 | break; |
8fcc4b59 JM |
4538 | |
4539 | /* nested_run_pending implies guest_mode. */ | |
8cab6507 VK |
4540 | if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) |
4541 | && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) | |
26b471c7 | 4542 | break; |
8fcc4b59 | 4543 | |
ad5996d9 | 4544 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
8fcc4b59 | 4545 | r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state); |
ad5996d9 | 4546 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8fcc4b59 JM |
4547 | break; |
4548 | } | |
2bc39970 VK |
4549 | case KVM_GET_SUPPORTED_HV_CPUID: { |
4550 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
4551 | struct kvm_cpuid2 cpuid; | |
4552 | ||
4553 | r = -EFAULT; | |
4554 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) | |
4555 | goto out; | |
4556 | ||
4557 | r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid, | |
4558 | cpuid_arg->entries); | |
4559 | if (r) | |
4560 | goto out; | |
4561 | ||
4562 | r = -EFAULT; | |
4563 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) | |
4564 | goto out; | |
4565 | r = 0; | |
4566 | break; | |
4567 | } | |
313a3dc7 CO |
4568 | default: |
4569 | r = -EINVAL; | |
4570 | } | |
4571 | out: | |
d1ac91d8 | 4572 | kfree(u.buffer); |
9b062471 CD |
4573 | out_nofree: |
4574 | vcpu_put(vcpu); | |
313a3dc7 CO |
4575 | return r; |
4576 | } | |
4577 | ||
1499fa80 | 4578 | vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) |
5b1c1493 CO |
4579 | { |
4580 | return VM_FAULT_SIGBUS; | |
4581 | } | |
4582 | ||
1fe779f8 CO |
4583 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
4584 | { | |
4585 | int ret; | |
4586 | ||
4587 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
951179ce | 4588 | return -EINVAL; |
1fe779f8 CO |
4589 | ret = kvm_x86_ops->set_tss_addr(kvm, addr); |
4590 | return ret; | |
4591 | } | |
4592 | ||
b927a3ce SY |
4593 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
4594 | u64 ident_addr) | |
4595 | { | |
2ac52ab8 | 4596 | return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr); |
b927a3ce SY |
4597 | } |
4598 | ||
1fe779f8 | 4599 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
bc8a3d89 | 4600 | unsigned long kvm_nr_mmu_pages) |
1fe779f8 CO |
4601 | { |
4602 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
4603 | return -EINVAL; | |
4604 | ||
79fac95e | 4605 | mutex_lock(&kvm->slots_lock); |
1fe779f8 CO |
4606 | |
4607 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 4608 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 4609 | |
79fac95e | 4610 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
4611 | return 0; |
4612 | } | |
4613 | ||
bc8a3d89 | 4614 | static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) |
1fe779f8 | 4615 | { |
39de71ec | 4616 | return kvm->arch.n_max_mmu_pages; |
1fe779f8 CO |
4617 | } |
4618 | ||
1fe779f8 CO |
4619 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) |
4620 | { | |
90bca052 | 4621 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
4622 | int r; |
4623 | ||
4624 | r = 0; | |
4625 | switch (chip->chip_id) { | |
4626 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 | 4627 | memcpy(&chip->chip.pic, &pic->pics[0], |
1fe779f8 CO |
4628 | sizeof(struct kvm_pic_state)); |
4629 | break; | |
4630 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 | 4631 | memcpy(&chip->chip.pic, &pic->pics[1], |
1fe779f8 CO |
4632 | sizeof(struct kvm_pic_state)); |
4633 | break; | |
4634 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 4635 | kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
4636 | break; |
4637 | default: | |
4638 | r = -EINVAL; | |
4639 | break; | |
4640 | } | |
4641 | return r; | |
4642 | } | |
4643 | ||
4644 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
4645 | { | |
90bca052 | 4646 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
4647 | int r; |
4648 | ||
4649 | r = 0; | |
4650 | switch (chip->chip_id) { | |
4651 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 DH |
4652 | spin_lock(&pic->lock); |
4653 | memcpy(&pic->pics[0], &chip->chip.pic, | |
1fe779f8 | 4654 | sizeof(struct kvm_pic_state)); |
90bca052 | 4655 | spin_unlock(&pic->lock); |
1fe779f8 CO |
4656 | break; |
4657 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 DH |
4658 | spin_lock(&pic->lock); |
4659 | memcpy(&pic->pics[1], &chip->chip.pic, | |
1fe779f8 | 4660 | sizeof(struct kvm_pic_state)); |
90bca052 | 4661 | spin_unlock(&pic->lock); |
1fe779f8 CO |
4662 | break; |
4663 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 4664 | kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
4665 | break; |
4666 | default: | |
4667 | r = -EINVAL; | |
4668 | break; | |
4669 | } | |
90bca052 | 4670 | kvm_pic_update_irq(pic); |
1fe779f8 CO |
4671 | return r; |
4672 | } | |
4673 | ||
e0f63cb9 SY |
4674 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
4675 | { | |
34f3941c RK |
4676 | struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; |
4677 | ||
4678 | BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); | |
4679 | ||
4680 | mutex_lock(&kps->lock); | |
4681 | memcpy(ps, &kps->channels, sizeof(*ps)); | |
4682 | mutex_unlock(&kps->lock); | |
2da29bcc | 4683 | return 0; |
e0f63cb9 SY |
4684 | } |
4685 | ||
4686 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
4687 | { | |
0185604c | 4688 | int i; |
09edea72 RK |
4689 | struct kvm_pit *pit = kvm->arch.vpit; |
4690 | ||
4691 | mutex_lock(&pit->pit_state.lock); | |
34f3941c | 4692 | memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); |
0185604c | 4693 | for (i = 0; i < 3; i++) |
09edea72 RK |
4694 | kvm_pit_load_count(pit, i, ps->channels[i].count, 0); |
4695 | mutex_unlock(&pit->pit_state.lock); | |
2da29bcc | 4696 | return 0; |
e9f42757 BK |
4697 | } |
4698 | ||
4699 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
4700 | { | |
e9f42757 BK |
4701 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
4702 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
4703 | sizeof(ps->channels)); | |
4704 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
4705 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
97e69aa6 | 4706 | memset(&ps->reserved, 0, sizeof(ps->reserved)); |
2da29bcc | 4707 | return 0; |
e9f42757 BK |
4708 | } |
4709 | ||
4710 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
4711 | { | |
2da29bcc | 4712 | int start = 0; |
0185604c | 4713 | int i; |
e9f42757 | 4714 | u32 prev_legacy, cur_legacy; |
09edea72 RK |
4715 | struct kvm_pit *pit = kvm->arch.vpit; |
4716 | ||
4717 | mutex_lock(&pit->pit_state.lock); | |
4718 | prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
e9f42757 BK |
4719 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; |
4720 | if (!prev_legacy && cur_legacy) | |
4721 | start = 1; | |
09edea72 RK |
4722 | memcpy(&pit->pit_state.channels, &ps->channels, |
4723 | sizeof(pit->pit_state.channels)); | |
4724 | pit->pit_state.flags = ps->flags; | |
0185604c | 4725 | for (i = 0; i < 3; i++) |
09edea72 | 4726 | kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, |
e5e57e7a | 4727 | start && i == 0); |
09edea72 | 4728 | mutex_unlock(&pit->pit_state.lock); |
2da29bcc | 4729 | return 0; |
e0f63cb9 SY |
4730 | } |
4731 | ||
52d939a0 MT |
4732 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
4733 | struct kvm_reinject_control *control) | |
4734 | { | |
71474e2f RK |
4735 | struct kvm_pit *pit = kvm->arch.vpit; |
4736 | ||
71474e2f RK |
4737 | /* pit->pit_state.lock was overloaded to prevent userspace from getting |
4738 | * an inconsistent state after running multiple KVM_REINJECT_CONTROL | |
4739 | * ioctls in parallel. Use a separate lock if that ioctl isn't rare. | |
4740 | */ | |
4741 | mutex_lock(&pit->pit_state.lock); | |
4742 | kvm_pit_set_reinject(pit, control->pit_reinject); | |
4743 | mutex_unlock(&pit->pit_state.lock); | |
b39c90b6 | 4744 | |
52d939a0 MT |
4745 | return 0; |
4746 | } | |
4747 | ||
95d4c16c | 4748 | /** |
60c34612 TY |
4749 | * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot |
4750 | * @kvm: kvm instance | |
4751 | * @log: slot id and address to which we copy the log | |
95d4c16c | 4752 | * |
e108ff2f PB |
4753 | * Steps 1-4 below provide general overview of dirty page logging. See |
4754 | * kvm_get_dirty_log_protect() function description for additional details. | |
4755 | * | |
4756 | * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we | |
4757 | * always flush the TLB (step 4) even if previous step failed and the dirty | |
4758 | * bitmap may be corrupt. Regardless of previous outcome the KVM logging API | |
4759 | * does not preclude user space subsequent dirty log read. Flushing TLB ensures | |
4760 | * writes will be marked dirty for next log read. | |
95d4c16c | 4761 | * |
60c34612 TY |
4762 | * 1. Take a snapshot of the bit and clear it if needed. |
4763 | * 2. Write protect the corresponding page. | |
e108ff2f PB |
4764 | * 3. Copy the snapshot to the userspace. |
4765 | * 4. Flush TLB's if needed. | |
5bb064dc | 4766 | */ |
60c34612 | 4767 | int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) |
5bb064dc | 4768 | { |
8fe65a82 | 4769 | bool flush = false; |
e108ff2f | 4770 | int r; |
5bb064dc | 4771 | |
79fac95e | 4772 | mutex_lock(&kvm->slots_lock); |
5bb064dc | 4773 | |
88178fd4 KH |
4774 | /* |
4775 | * Flush potentially hardware-cached dirty pages to dirty_bitmap. | |
4776 | */ | |
4777 | if (kvm_x86_ops->flush_log_dirty) | |
4778 | kvm_x86_ops->flush_log_dirty(kvm); | |
4779 | ||
8fe65a82 | 4780 | r = kvm_get_dirty_log_protect(kvm, log, &flush); |
198c74f4 XG |
4781 | |
4782 | /* | |
4783 | * All the TLBs can be flushed out of mmu lock, see the comments in | |
4784 | * kvm_mmu_slot_remove_write_access(). | |
4785 | */ | |
e108ff2f | 4786 | lockdep_assert_held(&kvm->slots_lock); |
8fe65a82 | 4787 | if (flush) |
2a31b9db PB |
4788 | kvm_flush_remote_tlbs(kvm); |
4789 | ||
4790 | mutex_unlock(&kvm->slots_lock); | |
4791 | return r; | |
4792 | } | |
4793 | ||
4794 | int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log) | |
4795 | { | |
4796 | bool flush = false; | |
4797 | int r; | |
4798 | ||
4799 | mutex_lock(&kvm->slots_lock); | |
4800 | ||
4801 | /* | |
4802 | * Flush potentially hardware-cached dirty pages to dirty_bitmap. | |
4803 | */ | |
4804 | if (kvm_x86_ops->flush_log_dirty) | |
4805 | kvm_x86_ops->flush_log_dirty(kvm); | |
4806 | ||
4807 | r = kvm_clear_dirty_log_protect(kvm, log, &flush); | |
4808 | ||
4809 | /* | |
4810 | * All the TLBs can be flushed out of mmu lock, see the comments in | |
4811 | * kvm_mmu_slot_remove_write_access(). | |
4812 | */ | |
4813 | lockdep_assert_held(&kvm->slots_lock); | |
4814 | if (flush) | |
198c74f4 XG |
4815 | kvm_flush_remote_tlbs(kvm); |
4816 | ||
79fac95e | 4817 | mutex_unlock(&kvm->slots_lock); |
5bb064dc ZX |
4818 | return r; |
4819 | } | |
4820 | ||
aa2fbe6d YZ |
4821 | int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, |
4822 | bool line_status) | |
23d43cf9 CD |
4823 | { |
4824 | if (!irqchip_in_kernel(kvm)) | |
4825 | return -ENXIO; | |
4826 | ||
4827 | irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, | |
aa2fbe6d YZ |
4828 | irq_event->irq, irq_event->level, |
4829 | line_status); | |
23d43cf9 CD |
4830 | return 0; |
4831 | } | |
4832 | ||
e5d83c74 PB |
4833 | int kvm_vm_ioctl_enable_cap(struct kvm *kvm, |
4834 | struct kvm_enable_cap *cap) | |
90de4a18 NA |
4835 | { |
4836 | int r; | |
4837 | ||
4838 | if (cap->flags) | |
4839 | return -EINVAL; | |
4840 | ||
4841 | switch (cap->cap) { | |
4842 | case KVM_CAP_DISABLE_QUIRKS: | |
4843 | kvm->arch.disabled_quirks = cap->args[0]; | |
4844 | r = 0; | |
4845 | break; | |
49df6397 SR |
4846 | case KVM_CAP_SPLIT_IRQCHIP: { |
4847 | mutex_lock(&kvm->lock); | |
b053b2ae SR |
4848 | r = -EINVAL; |
4849 | if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) | |
4850 | goto split_irqchip_unlock; | |
49df6397 SR |
4851 | r = -EEXIST; |
4852 | if (irqchip_in_kernel(kvm)) | |
4853 | goto split_irqchip_unlock; | |
557abc40 | 4854 | if (kvm->created_vcpus) |
49df6397 SR |
4855 | goto split_irqchip_unlock; |
4856 | r = kvm_setup_empty_irq_routing(kvm); | |
5c0aea0e | 4857 | if (r) |
49df6397 SR |
4858 | goto split_irqchip_unlock; |
4859 | /* Pairs with irqchip_in_kernel. */ | |
4860 | smp_wmb(); | |
49776faf | 4861 | kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; |
b053b2ae | 4862 | kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; |
49df6397 SR |
4863 | r = 0; |
4864 | split_irqchip_unlock: | |
4865 | mutex_unlock(&kvm->lock); | |
4866 | break; | |
4867 | } | |
37131313 RK |
4868 | case KVM_CAP_X2APIC_API: |
4869 | r = -EINVAL; | |
4870 | if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) | |
4871 | break; | |
4872 | ||
4873 | if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) | |
4874 | kvm->arch.x2apic_format = true; | |
c519265f RK |
4875 | if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) |
4876 | kvm->arch.x2apic_broadcast_quirk_disabled = true; | |
37131313 RK |
4877 | |
4878 | r = 0; | |
4879 | break; | |
4d5422ce WL |
4880 | case KVM_CAP_X86_DISABLE_EXITS: |
4881 | r = -EINVAL; | |
4882 | if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) | |
4883 | break; | |
4884 | ||
4885 | if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && | |
4886 | kvm_can_mwait_in_guest()) | |
4887 | kvm->arch.mwait_in_guest = true; | |
766d3571 | 4888 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) |
caa057a2 | 4889 | kvm->arch.hlt_in_guest = true; |
b31c114b WL |
4890 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) |
4891 | kvm->arch.pause_in_guest = true; | |
b5170063 WL |
4892 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) |
4893 | kvm->arch.cstate_in_guest = true; | |
4d5422ce WL |
4894 | r = 0; |
4895 | break; | |
6fbbde9a DS |
4896 | case KVM_CAP_MSR_PLATFORM_INFO: |
4897 | kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; | |
4898 | r = 0; | |
c4f55198 JM |
4899 | break; |
4900 | case KVM_CAP_EXCEPTION_PAYLOAD: | |
4901 | kvm->arch.exception_payload_enabled = cap->args[0]; | |
4902 | r = 0; | |
6fbbde9a | 4903 | break; |
90de4a18 NA |
4904 | default: |
4905 | r = -EINVAL; | |
4906 | break; | |
4907 | } | |
4908 | return r; | |
4909 | } | |
4910 | ||
1fe779f8 CO |
4911 | long kvm_arch_vm_ioctl(struct file *filp, |
4912 | unsigned int ioctl, unsigned long arg) | |
4913 | { | |
4914 | struct kvm *kvm = filp->private_data; | |
4915 | void __user *argp = (void __user *)arg; | |
367e1319 | 4916 | int r = -ENOTTY; |
f0d66275 DH |
4917 | /* |
4918 | * This union makes it completely explicit to gcc-3.x | |
4919 | * that these two variables' stack usage should be | |
4920 | * combined, not added together. | |
4921 | */ | |
4922 | union { | |
4923 | struct kvm_pit_state ps; | |
e9f42757 | 4924 | struct kvm_pit_state2 ps2; |
c5ff41ce | 4925 | struct kvm_pit_config pit_config; |
f0d66275 | 4926 | } u; |
1fe779f8 CO |
4927 | |
4928 | switch (ioctl) { | |
4929 | case KVM_SET_TSS_ADDR: | |
4930 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
1fe779f8 | 4931 | break; |
b927a3ce SY |
4932 | case KVM_SET_IDENTITY_MAP_ADDR: { |
4933 | u64 ident_addr; | |
4934 | ||
1af1ac91 DH |
4935 | mutex_lock(&kvm->lock); |
4936 | r = -EINVAL; | |
4937 | if (kvm->created_vcpus) | |
4938 | goto set_identity_unlock; | |
b927a3ce | 4939 | r = -EFAULT; |
0e96f31e | 4940 | if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) |
1af1ac91 | 4941 | goto set_identity_unlock; |
b927a3ce | 4942 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); |
1af1ac91 DH |
4943 | set_identity_unlock: |
4944 | mutex_unlock(&kvm->lock); | |
b927a3ce SY |
4945 | break; |
4946 | } | |
1fe779f8 CO |
4947 | case KVM_SET_NR_MMU_PAGES: |
4948 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
1fe779f8 CO |
4949 | break; |
4950 | case KVM_GET_NR_MMU_PAGES: | |
4951 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
4952 | break; | |
3ddea128 | 4953 | case KVM_CREATE_IRQCHIP: { |
3ddea128 | 4954 | mutex_lock(&kvm->lock); |
09941366 | 4955 | |
3ddea128 | 4956 | r = -EEXIST; |
35e6eaa3 | 4957 | if (irqchip_in_kernel(kvm)) |
3ddea128 | 4958 | goto create_irqchip_unlock; |
09941366 | 4959 | |
3e515705 | 4960 | r = -EINVAL; |
557abc40 | 4961 | if (kvm->created_vcpus) |
3e515705 | 4962 | goto create_irqchip_unlock; |
09941366 RK |
4963 | |
4964 | r = kvm_pic_init(kvm); | |
4965 | if (r) | |
3ddea128 | 4966 | goto create_irqchip_unlock; |
09941366 RK |
4967 | |
4968 | r = kvm_ioapic_init(kvm); | |
4969 | if (r) { | |
09941366 | 4970 | kvm_pic_destroy(kvm); |
3ddea128 | 4971 | goto create_irqchip_unlock; |
09941366 RK |
4972 | } |
4973 | ||
399ec807 AK |
4974 | r = kvm_setup_default_irq_routing(kvm); |
4975 | if (r) { | |
72bb2fcd | 4976 | kvm_ioapic_destroy(kvm); |
09941366 | 4977 | kvm_pic_destroy(kvm); |
71ba994c | 4978 | goto create_irqchip_unlock; |
399ec807 | 4979 | } |
49776faf | 4980 | /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ |
71ba994c | 4981 | smp_wmb(); |
49776faf | 4982 | kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; |
3ddea128 MT |
4983 | create_irqchip_unlock: |
4984 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 4985 | break; |
3ddea128 | 4986 | } |
7837699f | 4987 | case KVM_CREATE_PIT: |
c5ff41ce JK |
4988 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
4989 | goto create_pit; | |
4990 | case KVM_CREATE_PIT2: | |
4991 | r = -EFAULT; | |
4992 | if (copy_from_user(&u.pit_config, argp, | |
4993 | sizeof(struct kvm_pit_config))) | |
4994 | goto out; | |
4995 | create_pit: | |
250715a6 | 4996 | mutex_lock(&kvm->lock); |
269e05e4 AK |
4997 | r = -EEXIST; |
4998 | if (kvm->arch.vpit) | |
4999 | goto create_pit_unlock; | |
7837699f | 5000 | r = -ENOMEM; |
c5ff41ce | 5001 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
5002 | if (kvm->arch.vpit) |
5003 | r = 0; | |
269e05e4 | 5004 | create_pit_unlock: |
250715a6 | 5005 | mutex_unlock(&kvm->lock); |
7837699f | 5006 | break; |
1fe779f8 CO |
5007 | case KVM_GET_IRQCHIP: { |
5008 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 5009 | struct kvm_irqchip *chip; |
1fe779f8 | 5010 | |
ff5c2c03 SL |
5011 | chip = memdup_user(argp, sizeof(*chip)); |
5012 | if (IS_ERR(chip)) { | |
5013 | r = PTR_ERR(chip); | |
1fe779f8 | 5014 | goto out; |
ff5c2c03 SL |
5015 | } |
5016 | ||
1fe779f8 | 5017 | r = -ENXIO; |
826da321 | 5018 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
5019 | goto get_irqchip_out; |
5020 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 5021 | if (r) |
f0d66275 | 5022 | goto get_irqchip_out; |
1fe779f8 | 5023 | r = -EFAULT; |
0e96f31e | 5024 | if (copy_to_user(argp, chip, sizeof(*chip))) |
f0d66275 | 5025 | goto get_irqchip_out; |
1fe779f8 | 5026 | r = 0; |
f0d66275 DH |
5027 | get_irqchip_out: |
5028 | kfree(chip); | |
1fe779f8 CO |
5029 | break; |
5030 | } | |
5031 | case KVM_SET_IRQCHIP: { | |
5032 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 5033 | struct kvm_irqchip *chip; |
1fe779f8 | 5034 | |
ff5c2c03 SL |
5035 | chip = memdup_user(argp, sizeof(*chip)); |
5036 | if (IS_ERR(chip)) { | |
5037 | r = PTR_ERR(chip); | |
1fe779f8 | 5038 | goto out; |
ff5c2c03 SL |
5039 | } |
5040 | ||
1fe779f8 | 5041 | r = -ENXIO; |
826da321 | 5042 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
5043 | goto set_irqchip_out; |
5044 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
f0d66275 DH |
5045 | set_irqchip_out: |
5046 | kfree(chip); | |
1fe779f8 CO |
5047 | break; |
5048 | } | |
e0f63cb9 | 5049 | case KVM_GET_PIT: { |
e0f63cb9 | 5050 | r = -EFAULT; |
f0d66275 | 5051 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
5052 | goto out; |
5053 | r = -ENXIO; | |
5054 | if (!kvm->arch.vpit) | |
5055 | goto out; | |
f0d66275 | 5056 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
5057 | if (r) |
5058 | goto out; | |
5059 | r = -EFAULT; | |
f0d66275 | 5060 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
5061 | goto out; |
5062 | r = 0; | |
5063 | break; | |
5064 | } | |
5065 | case KVM_SET_PIT: { | |
e0f63cb9 | 5066 | r = -EFAULT; |
0e96f31e | 5067 | if (copy_from_user(&u.ps, argp, sizeof(u.ps))) |
e0f63cb9 SY |
5068 | goto out; |
5069 | r = -ENXIO; | |
5070 | if (!kvm->arch.vpit) | |
5071 | goto out; | |
f0d66275 | 5072 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
e0f63cb9 SY |
5073 | break; |
5074 | } | |
e9f42757 BK |
5075 | case KVM_GET_PIT2: { |
5076 | r = -ENXIO; | |
5077 | if (!kvm->arch.vpit) | |
5078 | goto out; | |
5079 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
5080 | if (r) | |
5081 | goto out; | |
5082 | r = -EFAULT; | |
5083 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
5084 | goto out; | |
5085 | r = 0; | |
5086 | break; | |
5087 | } | |
5088 | case KVM_SET_PIT2: { | |
5089 | r = -EFAULT; | |
5090 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
5091 | goto out; | |
5092 | r = -ENXIO; | |
5093 | if (!kvm->arch.vpit) | |
5094 | goto out; | |
5095 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); | |
e9f42757 BK |
5096 | break; |
5097 | } | |
52d939a0 MT |
5098 | case KVM_REINJECT_CONTROL: { |
5099 | struct kvm_reinject_control control; | |
5100 | r = -EFAULT; | |
5101 | if (copy_from_user(&control, argp, sizeof(control))) | |
5102 | goto out; | |
cad23e72 ML |
5103 | r = -ENXIO; |
5104 | if (!kvm->arch.vpit) | |
5105 | goto out; | |
52d939a0 | 5106 | r = kvm_vm_ioctl_reinject(kvm, &control); |
52d939a0 MT |
5107 | break; |
5108 | } | |
d71ba788 PB |
5109 | case KVM_SET_BOOT_CPU_ID: |
5110 | r = 0; | |
5111 | mutex_lock(&kvm->lock); | |
557abc40 | 5112 | if (kvm->created_vcpus) |
d71ba788 PB |
5113 | r = -EBUSY; |
5114 | else | |
5115 | kvm->arch.bsp_vcpu_id = arg; | |
5116 | mutex_unlock(&kvm->lock); | |
5117 | break; | |
ffde22ac | 5118 | case KVM_XEN_HVM_CONFIG: { |
51776043 | 5119 | struct kvm_xen_hvm_config xhc; |
ffde22ac | 5120 | r = -EFAULT; |
51776043 | 5121 | if (copy_from_user(&xhc, argp, sizeof(xhc))) |
ffde22ac ES |
5122 | goto out; |
5123 | r = -EINVAL; | |
51776043 | 5124 | if (xhc.flags) |
ffde22ac | 5125 | goto out; |
51776043 | 5126 | memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc)); |
ffde22ac ES |
5127 | r = 0; |
5128 | break; | |
5129 | } | |
afbcf7ab | 5130 | case KVM_SET_CLOCK: { |
afbcf7ab GC |
5131 | struct kvm_clock_data user_ns; |
5132 | u64 now_ns; | |
afbcf7ab GC |
5133 | |
5134 | r = -EFAULT; | |
5135 | if (copy_from_user(&user_ns, argp, sizeof(user_ns))) | |
5136 | goto out; | |
5137 | ||
5138 | r = -EINVAL; | |
5139 | if (user_ns.flags) | |
5140 | goto out; | |
5141 | ||
5142 | r = 0; | |
0bc48bea RK |
5143 | /* |
5144 | * TODO: userspace has to take care of races with VCPU_RUN, so | |
5145 | * kvm_gen_update_masterclock() can be cut down to locked | |
5146 | * pvclock_update_vm_gtod_copy(). | |
5147 | */ | |
5148 | kvm_gen_update_masterclock(kvm); | |
e891a32e | 5149 | now_ns = get_kvmclock_ns(kvm); |
108b249c | 5150 | kvm->arch.kvmclock_offset += user_ns.clock - now_ns; |
0bc48bea | 5151 | kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE); |
afbcf7ab GC |
5152 | break; |
5153 | } | |
5154 | case KVM_GET_CLOCK: { | |
afbcf7ab GC |
5155 | struct kvm_clock_data user_ns; |
5156 | u64 now_ns; | |
5157 | ||
e891a32e | 5158 | now_ns = get_kvmclock_ns(kvm); |
108b249c | 5159 | user_ns.clock = now_ns; |
e3fd9a93 | 5160 | user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; |
97e69aa6 | 5161 | memset(&user_ns.pad, 0, sizeof(user_ns.pad)); |
afbcf7ab GC |
5162 | |
5163 | r = -EFAULT; | |
5164 | if (copy_to_user(argp, &user_ns, sizeof(user_ns))) | |
5165 | goto out; | |
5166 | r = 0; | |
5167 | break; | |
5168 | } | |
5acc5c06 BS |
5169 | case KVM_MEMORY_ENCRYPT_OP: { |
5170 | r = -ENOTTY; | |
5171 | if (kvm_x86_ops->mem_enc_op) | |
5172 | r = kvm_x86_ops->mem_enc_op(kvm, argp); | |
5173 | break; | |
5174 | } | |
69eaedee BS |
5175 | case KVM_MEMORY_ENCRYPT_REG_REGION: { |
5176 | struct kvm_enc_region region; | |
5177 | ||
5178 | r = -EFAULT; | |
5179 | if (copy_from_user(®ion, argp, sizeof(region))) | |
5180 | goto out; | |
5181 | ||
5182 | r = -ENOTTY; | |
5183 | if (kvm_x86_ops->mem_enc_reg_region) | |
5184 | r = kvm_x86_ops->mem_enc_reg_region(kvm, ®ion); | |
5185 | break; | |
5186 | } | |
5187 | case KVM_MEMORY_ENCRYPT_UNREG_REGION: { | |
5188 | struct kvm_enc_region region; | |
5189 | ||
5190 | r = -EFAULT; | |
5191 | if (copy_from_user(®ion, argp, sizeof(region))) | |
5192 | goto out; | |
5193 | ||
5194 | r = -ENOTTY; | |
5195 | if (kvm_x86_ops->mem_enc_unreg_region) | |
5196 | r = kvm_x86_ops->mem_enc_unreg_region(kvm, ®ion); | |
5197 | break; | |
5198 | } | |
faeb7833 RK |
5199 | case KVM_HYPERV_EVENTFD: { |
5200 | struct kvm_hyperv_eventfd hvevfd; | |
5201 | ||
5202 | r = -EFAULT; | |
5203 | if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) | |
5204 | goto out; | |
5205 | r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); | |
5206 | break; | |
5207 | } | |
66bb8a06 EH |
5208 | case KVM_SET_PMU_EVENT_FILTER: |
5209 | r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); | |
5210 | break; | |
1fe779f8 | 5211 | default: |
ad6260da | 5212 | r = -ENOTTY; |
1fe779f8 CO |
5213 | } |
5214 | out: | |
5215 | return r; | |
5216 | } | |
5217 | ||
a16b043c | 5218 | static void kvm_init_msr_list(void) |
043405e1 | 5219 | { |
24c29b7a | 5220 | struct x86_pmu_capability x86_pmu; |
043405e1 | 5221 | u32 dummy[2]; |
7a5ee6ed | 5222 | unsigned i; |
043405e1 | 5223 | |
e2ada66e | 5224 | BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4, |
7a5ee6ed | 5225 | "Please update the fixed PMCs in msrs_to_saved_all[]"); |
24c29b7a PB |
5226 | |
5227 | perf_get_x86_pmu_capability(&x86_pmu); | |
e2ada66e | 5228 | |
6cbee2b9 XL |
5229 | num_msrs_to_save = 0; |
5230 | num_emulated_msrs = 0; | |
5231 | num_msr_based_features = 0; | |
5232 | ||
7a5ee6ed CQ |
5233 | for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) { |
5234 | if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0) | |
043405e1 | 5235 | continue; |
93c4adc7 PB |
5236 | |
5237 | /* | |
5238 | * Even MSRs that are valid in the host may not be exposed | |
9dbe6cf9 | 5239 | * to the guests in some cases. |
93c4adc7 | 5240 | */ |
7a5ee6ed | 5241 | switch (msrs_to_save_all[i]) { |
93c4adc7 | 5242 | case MSR_IA32_BNDCFGS: |
503234b3 | 5243 | if (!kvm_mpx_supported()) |
93c4adc7 PB |
5244 | continue; |
5245 | break; | |
9dbe6cf9 PB |
5246 | case MSR_TSC_AUX: |
5247 | if (!kvm_x86_ops->rdtscp_supported()) | |
5248 | continue; | |
5249 | break; | |
bf8c55d8 CP |
5250 | case MSR_IA32_RTIT_CTL: |
5251 | case MSR_IA32_RTIT_STATUS: | |
5252 | if (!kvm_x86_ops->pt_supported()) | |
5253 | continue; | |
5254 | break; | |
5255 | case MSR_IA32_RTIT_CR3_MATCH: | |
5256 | if (!kvm_x86_ops->pt_supported() || | |
5257 | !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) | |
5258 | continue; | |
5259 | break; | |
5260 | case MSR_IA32_RTIT_OUTPUT_BASE: | |
5261 | case MSR_IA32_RTIT_OUTPUT_MASK: | |
5262 | if (!kvm_x86_ops->pt_supported() || | |
5263 | (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && | |
5264 | !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) | |
5265 | continue; | |
5266 | break; | |
5267 | case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: { | |
5268 | if (!kvm_x86_ops->pt_supported() || | |
7a5ee6ed | 5269 | msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >= |
bf8c55d8 CP |
5270 | intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) |
5271 | continue; | |
5272 | break; | |
cf05a67b | 5273 | case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17: |
7a5ee6ed | 5274 | if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >= |
24c29b7a PB |
5275 | min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) |
5276 | continue; | |
5277 | break; | |
cf05a67b | 5278 | case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17: |
7a5ee6ed | 5279 | if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= |
24c29b7a PB |
5280 | min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) |
5281 | continue; | |
bf8c55d8 | 5282 | } |
93c4adc7 PB |
5283 | default: |
5284 | break; | |
5285 | } | |
5286 | ||
7a5ee6ed | 5287 | msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i]; |
043405e1 | 5288 | } |
62ef68bb | 5289 | |
7a5ee6ed CQ |
5290 | for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) { |
5291 | if (!kvm_x86_ops->has_emulated_msr(emulated_msrs_all[i])) | |
bc226f07 | 5292 | continue; |
62ef68bb | 5293 | |
7a5ee6ed | 5294 | emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i]; |
62ef68bb | 5295 | } |
801e459a | 5296 | |
7a5ee6ed | 5297 | for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) { |
801e459a TL |
5298 | struct kvm_msr_entry msr; |
5299 | ||
7a5ee6ed | 5300 | msr.index = msr_based_features_all[i]; |
66421c1e | 5301 | if (kvm_get_msr_feature(&msr)) |
801e459a TL |
5302 | continue; |
5303 | ||
7a5ee6ed | 5304 | msr_based_features[num_msr_based_features++] = msr_based_features_all[i]; |
801e459a | 5305 | } |
043405e1 CO |
5306 | } |
5307 | ||
bda9020e MT |
5308 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
5309 | const void *v) | |
bbd9b64e | 5310 | { |
70252a10 AK |
5311 | int handled = 0; |
5312 | int n; | |
5313 | ||
5314 | do { | |
5315 | n = min(len, 8); | |
bce87cce | 5316 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
5317 | !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) |
5318 | && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 AK |
5319 | break; |
5320 | handled += n; | |
5321 | addr += n; | |
5322 | len -= n; | |
5323 | v += n; | |
5324 | } while (len); | |
bbd9b64e | 5325 | |
70252a10 | 5326 | return handled; |
bbd9b64e CO |
5327 | } |
5328 | ||
bda9020e | 5329 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 5330 | { |
70252a10 AK |
5331 | int handled = 0; |
5332 | int n; | |
5333 | ||
5334 | do { | |
5335 | n = min(len, 8); | |
bce87cce | 5336 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
5337 | !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, |
5338 | addr, n, v)) | |
5339 | && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 | 5340 | break; |
e39d200f | 5341 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); |
70252a10 AK |
5342 | handled += n; |
5343 | addr += n; | |
5344 | len -= n; | |
5345 | v += n; | |
5346 | } while (len); | |
bbd9b64e | 5347 | |
70252a10 | 5348 | return handled; |
bbd9b64e CO |
5349 | } |
5350 | ||
2dafc6c2 GN |
5351 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
5352 | struct kvm_segment *var, int seg) | |
5353 | { | |
5354 | kvm_x86_ops->set_segment(vcpu, var, seg); | |
5355 | } | |
5356 | ||
5357 | void kvm_get_segment(struct kvm_vcpu *vcpu, | |
5358 | struct kvm_segment *var, int seg) | |
5359 | { | |
5360 | kvm_x86_ops->get_segment(vcpu, var, seg); | |
5361 | } | |
5362 | ||
54987b7a PB |
5363 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
5364 | struct x86_exception *exception) | |
02f59dc9 JR |
5365 | { |
5366 | gpa_t t_gpa; | |
02f59dc9 JR |
5367 | |
5368 | BUG_ON(!mmu_is_nested(vcpu)); | |
5369 | ||
5370 | /* NPT walks are always user-walks */ | |
5371 | access |= PFERR_USER_MASK; | |
44dd3ffa | 5372 | t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception); |
02f59dc9 JR |
5373 | |
5374 | return t_gpa; | |
5375 | } | |
5376 | ||
ab9ae313 AK |
5377 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
5378 | struct x86_exception *exception) | |
1871c602 GN |
5379 | { |
5380 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
ab9ae313 | 5381 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
5382 | } |
5383 | ||
ab9ae313 AK |
5384 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, |
5385 | struct x86_exception *exception) | |
1871c602 GN |
5386 | { |
5387 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
5388 | access |= PFERR_FETCH_MASK; | |
ab9ae313 | 5389 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
5390 | } |
5391 | ||
ab9ae313 AK |
5392 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, |
5393 | struct x86_exception *exception) | |
1871c602 GN |
5394 | { |
5395 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
5396 | access |= PFERR_WRITE_MASK; | |
ab9ae313 | 5397 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
5398 | } |
5399 | ||
5400 | /* uses this to access any guest's mapped memory without checking CPL */ | |
ab9ae313 AK |
5401 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, |
5402 | struct x86_exception *exception) | |
1871c602 | 5403 | { |
ab9ae313 | 5404 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); |
1871c602 GN |
5405 | } |
5406 | ||
5407 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
5408 | struct kvm_vcpu *vcpu, u32 access, | |
bcc55cba | 5409 | struct x86_exception *exception) |
bbd9b64e CO |
5410 | { |
5411 | void *data = val; | |
10589a46 | 5412 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
5413 | |
5414 | while (bytes) { | |
14dfe855 | 5415 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, |
ab9ae313 | 5416 | exception); |
bbd9b64e | 5417 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 5418 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
5419 | int ret; |
5420 | ||
bcc55cba | 5421 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 5422 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa PB |
5423 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, |
5424 | offset, toread); | |
10589a46 | 5425 | if (ret < 0) { |
c3cd7ffa | 5426 | r = X86EMUL_IO_NEEDED; |
10589a46 MT |
5427 | goto out; |
5428 | } | |
bbd9b64e | 5429 | |
77c2002e IE |
5430 | bytes -= toread; |
5431 | data += toread; | |
5432 | addr += toread; | |
bbd9b64e | 5433 | } |
10589a46 | 5434 | out: |
10589a46 | 5435 | return r; |
bbd9b64e | 5436 | } |
77c2002e | 5437 | |
1871c602 | 5438 | /* used for instruction fetching */ |
0f65dd70 AK |
5439 | static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, |
5440 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 5441 | struct x86_exception *exception) |
1871c602 | 5442 | { |
0f65dd70 | 5443 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
1871c602 | 5444 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
44583cba PB |
5445 | unsigned offset; |
5446 | int ret; | |
0f65dd70 | 5447 | |
44583cba PB |
5448 | /* Inline kvm_read_guest_virt_helper for speed. */ |
5449 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, | |
5450 | exception); | |
5451 | if (unlikely(gpa == UNMAPPED_GVA)) | |
5452 | return X86EMUL_PROPAGATE_FAULT; | |
5453 | ||
5454 | offset = addr & (PAGE_SIZE-1); | |
5455 | if (WARN_ON(offset + bytes > PAGE_SIZE)) | |
5456 | bytes = (unsigned)PAGE_SIZE - offset; | |
54bf36aa PB |
5457 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, |
5458 | offset, bytes); | |
44583cba PB |
5459 | if (unlikely(ret < 0)) |
5460 | return X86EMUL_IO_NEEDED; | |
5461 | ||
5462 | return X86EMUL_CONTINUE; | |
1871c602 GN |
5463 | } |
5464 | ||
ce14e868 | 5465 | int kvm_read_guest_virt(struct kvm_vcpu *vcpu, |
0f65dd70 | 5466 | gva_t addr, void *val, unsigned int bytes, |
bcc55cba | 5467 | struct x86_exception *exception) |
1871c602 GN |
5468 | { |
5469 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
0f65dd70 | 5470 | |
353c0956 PB |
5471 | /* |
5472 | * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED | |
5473 | * is returned, but our callers are not ready for that and they blindly | |
5474 | * call kvm_inject_page_fault. Ensure that they at least do not leak | |
5475 | * uninitialized kernel stack memory into cr2 and error code. | |
5476 | */ | |
5477 | memset(exception, 0, sizeof(*exception)); | |
1871c602 | 5478 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, |
bcc55cba | 5479 | exception); |
1871c602 | 5480 | } |
064aea77 | 5481 | EXPORT_SYMBOL_GPL(kvm_read_guest_virt); |
1871c602 | 5482 | |
ce14e868 PB |
5483 | static int emulator_read_std(struct x86_emulate_ctxt *ctxt, |
5484 | gva_t addr, void *val, unsigned int bytes, | |
3c9fa24c | 5485 | struct x86_exception *exception, bool system) |
1871c602 | 5486 | { |
0f65dd70 | 5487 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
3c9fa24c PB |
5488 | u32 access = 0; |
5489 | ||
5490 | if (!system && kvm_x86_ops->get_cpl(vcpu) == 3) | |
5491 | access |= PFERR_USER_MASK; | |
5492 | ||
5493 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); | |
1871c602 GN |
5494 | } |
5495 | ||
7a036a6f RK |
5496 | static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, |
5497 | unsigned long addr, void *val, unsigned int bytes) | |
5498 | { | |
5499 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
5500 | int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); | |
5501 | ||
5502 | return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; | |
5503 | } | |
5504 | ||
ce14e868 PB |
5505 | static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, |
5506 | struct kvm_vcpu *vcpu, u32 access, | |
5507 | struct x86_exception *exception) | |
77c2002e IE |
5508 | { |
5509 | void *data = val; | |
5510 | int r = X86EMUL_CONTINUE; | |
5511 | ||
5512 | while (bytes) { | |
14dfe855 | 5513 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, |
ce14e868 | 5514 | access, |
ab9ae313 | 5515 | exception); |
77c2002e IE |
5516 | unsigned offset = addr & (PAGE_SIZE-1); |
5517 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
5518 | int ret; | |
5519 | ||
bcc55cba | 5520 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 5521 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa | 5522 | ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); |
77c2002e | 5523 | if (ret < 0) { |
c3cd7ffa | 5524 | r = X86EMUL_IO_NEEDED; |
77c2002e IE |
5525 | goto out; |
5526 | } | |
5527 | ||
5528 | bytes -= towrite; | |
5529 | data += towrite; | |
5530 | addr += towrite; | |
5531 | } | |
5532 | out: | |
5533 | return r; | |
5534 | } | |
ce14e868 PB |
5535 | |
5536 | static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, | |
3c9fa24c PB |
5537 | unsigned int bytes, struct x86_exception *exception, |
5538 | bool system) | |
ce14e868 PB |
5539 | { |
5540 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
3c9fa24c PB |
5541 | u32 access = PFERR_WRITE_MASK; |
5542 | ||
5543 | if (!system && kvm_x86_ops->get_cpl(vcpu) == 3) | |
5544 | access |= PFERR_USER_MASK; | |
ce14e868 PB |
5545 | |
5546 | return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, | |
3c9fa24c | 5547 | access, exception); |
ce14e868 PB |
5548 | } |
5549 | ||
5550 | int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, | |
5551 | unsigned int bytes, struct x86_exception *exception) | |
5552 | { | |
c595ceee PB |
5553 | /* kvm_write_guest_virt_system can pull in tons of pages. */ |
5554 | vcpu->arch.l1tf_flush_l1d = true; | |
5555 | ||
541ab2ae FH |
5556 | /* |
5557 | * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED | |
5558 | * is returned, but our callers are not ready for that and they blindly | |
5559 | * call kvm_inject_page_fault. Ensure that they at least do not leak | |
5560 | * uninitialized kernel stack memory into cr2 and error code. | |
5561 | */ | |
5562 | memset(exception, 0, sizeof(*exception)); | |
ce14e868 PB |
5563 | return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, |
5564 | PFERR_WRITE_MASK, exception); | |
5565 | } | |
6a4d7550 | 5566 | EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); |
77c2002e | 5567 | |
082d06ed WL |
5568 | int handle_ud(struct kvm_vcpu *vcpu) |
5569 | { | |
b3dc0695 | 5570 | static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX }; |
6c86eedc | 5571 | int emul_type = EMULTYPE_TRAP_UD; |
6c86eedc WL |
5572 | char sig[5]; /* ud2; .ascii "kvm" */ |
5573 | struct x86_exception e; | |
5574 | ||
5575 | if (force_emulation_prefix && | |
3c9fa24c PB |
5576 | kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), |
5577 | sig, sizeof(sig), &e) == 0 && | |
b3dc0695 | 5578 | memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) { |
6c86eedc | 5579 | kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); |
b4000606 | 5580 | emul_type = EMULTYPE_TRAP_UD_FORCED; |
6c86eedc | 5581 | } |
082d06ed | 5582 | |
60fc3d02 | 5583 | return kvm_emulate_instruction(vcpu, emul_type); |
082d06ed WL |
5584 | } |
5585 | EXPORT_SYMBOL_GPL(handle_ud); | |
5586 | ||
0f89b207 TL |
5587 | static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
5588 | gpa_t gpa, bool write) | |
5589 | { | |
5590 | /* For APIC access vmexit */ | |
5591 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
5592 | return 1; | |
5593 | ||
5594 | if (vcpu_match_mmio_gpa(vcpu, gpa)) { | |
5595 | trace_vcpu_match_mmio(gva, gpa, write, true); | |
5596 | return 1; | |
5597 | } | |
5598 | ||
5599 | return 0; | |
5600 | } | |
5601 | ||
af7cc7d1 XG |
5602 | static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
5603 | gpa_t *gpa, struct x86_exception *exception, | |
5604 | bool write) | |
5605 | { | |
97d64b78 AK |
5606 | u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) |
5607 | | (write ? PFERR_WRITE_MASK : 0); | |
af7cc7d1 | 5608 | |
be94f6b7 HH |
5609 | /* |
5610 | * currently PKRU is only applied to ept enabled guest so | |
5611 | * there is no pkey in EPT page table for L1 guest or EPT | |
5612 | * shadow page table for L2 guest. | |
5613 | */ | |
97d64b78 | 5614 | if (vcpu_match_mmio_gva(vcpu, gva) |
97ec8c06 | 5615 | && !permission_fault(vcpu, vcpu->arch.walk_mmu, |
871bd034 | 5616 | vcpu->arch.mmio_access, 0, access)) { |
bebb106a XG |
5617 | *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | |
5618 | (gva & (PAGE_SIZE - 1)); | |
4f022648 | 5619 | trace_vcpu_match_mmio(gva, *gpa, write, false); |
bebb106a XG |
5620 | return 1; |
5621 | } | |
5622 | ||
af7cc7d1 XG |
5623 | *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
5624 | ||
5625 | if (*gpa == UNMAPPED_GVA) | |
5626 | return -1; | |
5627 | ||
0f89b207 | 5628 | return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); |
af7cc7d1 XG |
5629 | } |
5630 | ||
3200f405 | 5631 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
bcc55cba | 5632 | const void *val, int bytes) |
bbd9b64e CO |
5633 | { |
5634 | int ret; | |
5635 | ||
54bf36aa | 5636 | ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); |
9f811285 | 5637 | if (ret < 0) |
bbd9b64e | 5638 | return 0; |
0eb05bf2 | 5639 | kvm_page_track_write(vcpu, gpa, val, bytes); |
bbd9b64e CO |
5640 | return 1; |
5641 | } | |
5642 | ||
77d197b2 XG |
5643 | struct read_write_emulator_ops { |
5644 | int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, | |
5645 | int bytes); | |
5646 | int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
5647 | void *val, int bytes); | |
5648 | int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
5649 | int bytes, void *val); | |
5650 | int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
5651 | void *val, int bytes); | |
5652 | bool write; | |
5653 | }; | |
5654 | ||
5655 | static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) | |
5656 | { | |
5657 | if (vcpu->mmio_read_completed) { | |
77d197b2 | 5658 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
e39d200f | 5659 | vcpu->mmio_fragments[0].gpa, val); |
77d197b2 XG |
5660 | vcpu->mmio_read_completed = 0; |
5661 | return 1; | |
5662 | } | |
5663 | ||
5664 | return 0; | |
5665 | } | |
5666 | ||
5667 | static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
5668 | void *val, int bytes) | |
5669 | { | |
54bf36aa | 5670 | return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); |
77d197b2 XG |
5671 | } |
5672 | ||
5673 | static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
5674 | void *val, int bytes) | |
5675 | { | |
5676 | return emulator_write_phys(vcpu, gpa, val, bytes); | |
5677 | } | |
5678 | ||
5679 | static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) | |
5680 | { | |
e39d200f | 5681 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); |
77d197b2 XG |
5682 | return vcpu_mmio_write(vcpu, gpa, bytes, val); |
5683 | } | |
5684 | ||
5685 | static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
5686 | void *val, int bytes) | |
5687 | { | |
e39d200f | 5688 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); |
77d197b2 XG |
5689 | return X86EMUL_IO_NEEDED; |
5690 | } | |
5691 | ||
5692 | static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
5693 | void *val, int bytes) | |
5694 | { | |
f78146b0 AK |
5695 | struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; |
5696 | ||
87da7e66 | 5697 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); |
77d197b2 XG |
5698 | return X86EMUL_CONTINUE; |
5699 | } | |
5700 | ||
0fbe9b0b | 5701 | static const struct read_write_emulator_ops read_emultor = { |
77d197b2 XG |
5702 | .read_write_prepare = read_prepare, |
5703 | .read_write_emulate = read_emulate, | |
5704 | .read_write_mmio = vcpu_mmio_read, | |
5705 | .read_write_exit_mmio = read_exit_mmio, | |
5706 | }; | |
5707 | ||
0fbe9b0b | 5708 | static const struct read_write_emulator_ops write_emultor = { |
77d197b2 XG |
5709 | .read_write_emulate = write_emulate, |
5710 | .read_write_mmio = write_mmio, | |
5711 | .read_write_exit_mmio = write_exit_mmio, | |
5712 | .write = true, | |
5713 | }; | |
5714 | ||
22388a3c XG |
5715 | static int emulator_read_write_onepage(unsigned long addr, void *val, |
5716 | unsigned int bytes, | |
5717 | struct x86_exception *exception, | |
5718 | struct kvm_vcpu *vcpu, | |
0fbe9b0b | 5719 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 5720 | { |
af7cc7d1 XG |
5721 | gpa_t gpa; |
5722 | int handled, ret; | |
22388a3c | 5723 | bool write = ops->write; |
f78146b0 | 5724 | struct kvm_mmio_fragment *frag; |
0f89b207 TL |
5725 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
5726 | ||
5727 | /* | |
5728 | * If the exit was due to a NPF we may already have a GPA. | |
5729 | * If the GPA is present, use it to avoid the GVA to GPA table walk. | |
5730 | * Note, this cannot be used on string operations since string | |
5731 | * operation using rep will only have the initial GPA from the NPF | |
5732 | * occurred. | |
5733 | */ | |
5734 | if (vcpu->arch.gpa_available && | |
5735 | emulator_can_use_gpa(ctxt) && | |
618232e2 BS |
5736 | (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) { |
5737 | gpa = vcpu->arch.gpa_val; | |
5738 | ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); | |
5739 | } else { | |
5740 | ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); | |
5741 | if (ret < 0) | |
5742 | return X86EMUL_PROPAGATE_FAULT; | |
0f89b207 | 5743 | } |
10589a46 | 5744 | |
618232e2 | 5745 | if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) |
bbd9b64e CO |
5746 | return X86EMUL_CONTINUE; |
5747 | ||
bbd9b64e CO |
5748 | /* |
5749 | * Is this MMIO handled locally? | |
5750 | */ | |
22388a3c | 5751 | handled = ops->read_write_mmio(vcpu, gpa, bytes, val); |
70252a10 | 5752 | if (handled == bytes) |
bbd9b64e | 5753 | return X86EMUL_CONTINUE; |
bbd9b64e | 5754 | |
70252a10 AK |
5755 | gpa += handled; |
5756 | bytes -= handled; | |
5757 | val += handled; | |
5758 | ||
87da7e66 XG |
5759 | WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); |
5760 | frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; | |
5761 | frag->gpa = gpa; | |
5762 | frag->data = val; | |
5763 | frag->len = bytes; | |
f78146b0 | 5764 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
5765 | } |
5766 | ||
52eb5a6d XL |
5767 | static int emulator_read_write(struct x86_emulate_ctxt *ctxt, |
5768 | unsigned long addr, | |
22388a3c XG |
5769 | void *val, unsigned int bytes, |
5770 | struct x86_exception *exception, | |
0fbe9b0b | 5771 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 5772 | { |
0f65dd70 | 5773 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
f78146b0 AK |
5774 | gpa_t gpa; |
5775 | int rc; | |
5776 | ||
5777 | if (ops->read_write_prepare && | |
5778 | ops->read_write_prepare(vcpu, val, bytes)) | |
5779 | return X86EMUL_CONTINUE; | |
5780 | ||
5781 | vcpu->mmio_nr_fragments = 0; | |
0f65dd70 | 5782 | |
bbd9b64e CO |
5783 | /* Crossing a page boundary? */ |
5784 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
f78146b0 | 5785 | int now; |
bbd9b64e CO |
5786 | |
5787 | now = -addr & ~PAGE_MASK; | |
22388a3c XG |
5788 | rc = emulator_read_write_onepage(addr, val, now, exception, |
5789 | vcpu, ops); | |
5790 | ||
bbd9b64e CO |
5791 | if (rc != X86EMUL_CONTINUE) |
5792 | return rc; | |
5793 | addr += now; | |
bac15531 NA |
5794 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
5795 | addr = (u32)addr; | |
bbd9b64e CO |
5796 | val += now; |
5797 | bytes -= now; | |
5798 | } | |
22388a3c | 5799 | |
f78146b0 AK |
5800 | rc = emulator_read_write_onepage(addr, val, bytes, exception, |
5801 | vcpu, ops); | |
5802 | if (rc != X86EMUL_CONTINUE) | |
5803 | return rc; | |
5804 | ||
5805 | if (!vcpu->mmio_nr_fragments) | |
5806 | return rc; | |
5807 | ||
5808 | gpa = vcpu->mmio_fragments[0].gpa; | |
5809 | ||
5810 | vcpu->mmio_needed = 1; | |
5811 | vcpu->mmio_cur_fragment = 0; | |
5812 | ||
87da7e66 | 5813 | vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); |
f78146b0 AK |
5814 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; |
5815 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
5816 | vcpu->run->mmio.phys_addr = gpa; | |
5817 | ||
5818 | return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); | |
22388a3c XG |
5819 | } |
5820 | ||
5821 | static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, | |
5822 | unsigned long addr, | |
5823 | void *val, | |
5824 | unsigned int bytes, | |
5825 | struct x86_exception *exception) | |
5826 | { | |
5827 | return emulator_read_write(ctxt, addr, val, bytes, | |
5828 | exception, &read_emultor); | |
5829 | } | |
5830 | ||
52eb5a6d | 5831 | static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, |
22388a3c XG |
5832 | unsigned long addr, |
5833 | const void *val, | |
5834 | unsigned int bytes, | |
5835 | struct x86_exception *exception) | |
5836 | { | |
5837 | return emulator_read_write(ctxt, addr, (void *)val, bytes, | |
5838 | exception, &write_emultor); | |
bbd9b64e | 5839 | } |
bbd9b64e | 5840 | |
daea3e73 AK |
5841 | #define CMPXCHG_TYPE(t, ptr, old, new) \ |
5842 | (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) | |
5843 | ||
5844 | #ifdef CONFIG_X86_64 | |
5845 | # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) | |
5846 | #else | |
5847 | # define CMPXCHG64(ptr, old, new) \ | |
9749a6c0 | 5848 | (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) |
daea3e73 AK |
5849 | #endif |
5850 | ||
0f65dd70 AK |
5851 | static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, |
5852 | unsigned long addr, | |
bbd9b64e CO |
5853 | const void *old, |
5854 | const void *new, | |
5855 | unsigned int bytes, | |
0f65dd70 | 5856 | struct x86_exception *exception) |
bbd9b64e | 5857 | { |
42e35f80 | 5858 | struct kvm_host_map map; |
0f65dd70 | 5859 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
daea3e73 | 5860 | gpa_t gpa; |
daea3e73 AK |
5861 | char *kaddr; |
5862 | bool exchanged; | |
2bacc55c | 5863 | |
daea3e73 AK |
5864 | /* guests cmpxchg8b have to be emulated atomically */ |
5865 | if (bytes > 8 || (bytes & (bytes - 1))) | |
5866 | goto emul_write; | |
10589a46 | 5867 | |
daea3e73 | 5868 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); |
2bacc55c | 5869 | |
daea3e73 AK |
5870 | if (gpa == UNMAPPED_GVA || |
5871 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
5872 | goto emul_write; | |
2bacc55c | 5873 | |
daea3e73 AK |
5874 | if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) |
5875 | goto emul_write; | |
72dc67a6 | 5876 | |
42e35f80 | 5877 | if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map)) |
c19b8bd6 | 5878 | goto emul_write; |
72dc67a6 | 5879 | |
42e35f80 KA |
5880 | kaddr = map.hva + offset_in_page(gpa); |
5881 | ||
daea3e73 AK |
5882 | switch (bytes) { |
5883 | case 1: | |
5884 | exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); | |
5885 | break; | |
5886 | case 2: | |
5887 | exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); | |
5888 | break; | |
5889 | case 4: | |
5890 | exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); | |
5891 | break; | |
5892 | case 8: | |
5893 | exchanged = CMPXCHG64(kaddr, old, new); | |
5894 | break; | |
5895 | default: | |
5896 | BUG(); | |
2bacc55c | 5897 | } |
42e35f80 KA |
5898 | |
5899 | kvm_vcpu_unmap(vcpu, &map, true); | |
daea3e73 AK |
5900 | |
5901 | if (!exchanged) | |
5902 | return X86EMUL_CMPXCHG_FAILED; | |
5903 | ||
0eb05bf2 | 5904 | kvm_page_track_write(vcpu, gpa, new, bytes); |
8f6abd06 GN |
5905 | |
5906 | return X86EMUL_CONTINUE; | |
4a5f48f6 | 5907 | |
3200f405 | 5908 | emul_write: |
daea3e73 | 5909 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); |
2bacc55c | 5910 | |
0f65dd70 | 5911 | return emulator_write_emulated(ctxt, addr, new, bytes, exception); |
bbd9b64e CO |
5912 | } |
5913 | ||
cf8f70bf GN |
5914 | static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) |
5915 | { | |
cbfc6c91 | 5916 | int r = 0, i; |
cf8f70bf | 5917 | |
cbfc6c91 WL |
5918 | for (i = 0; i < vcpu->arch.pio.count; i++) { |
5919 | if (vcpu->arch.pio.in) | |
5920 | r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, | |
5921 | vcpu->arch.pio.size, pd); | |
5922 | else | |
5923 | r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, | |
5924 | vcpu->arch.pio.port, vcpu->arch.pio.size, | |
5925 | pd); | |
5926 | if (r) | |
5927 | break; | |
5928 | pd += vcpu->arch.pio.size; | |
5929 | } | |
cf8f70bf GN |
5930 | return r; |
5931 | } | |
5932 | ||
6f6fbe98 XG |
5933 | static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, |
5934 | unsigned short port, void *val, | |
5935 | unsigned int count, bool in) | |
cf8f70bf | 5936 | { |
cf8f70bf | 5937 | vcpu->arch.pio.port = port; |
6f6fbe98 | 5938 | vcpu->arch.pio.in = in; |
7972995b | 5939 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
5940 | vcpu->arch.pio.size = size; |
5941 | ||
5942 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
7972995b | 5943 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
5944 | return 1; |
5945 | } | |
5946 | ||
5947 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
6f6fbe98 | 5948 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; |
cf8f70bf GN |
5949 | vcpu->run->io.size = size; |
5950 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
5951 | vcpu->run->io.count = count; | |
5952 | vcpu->run->io.port = port; | |
5953 | ||
5954 | return 0; | |
5955 | } | |
5956 | ||
6f6fbe98 XG |
5957 | static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
5958 | int size, unsigned short port, void *val, | |
5959 | unsigned int count) | |
cf8f70bf | 5960 | { |
ca1d4a9e | 5961 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
6f6fbe98 | 5962 | int ret; |
ca1d4a9e | 5963 | |
6f6fbe98 XG |
5964 | if (vcpu->arch.pio.count) |
5965 | goto data_avail; | |
cf8f70bf | 5966 | |
cbfc6c91 WL |
5967 | memset(vcpu->arch.pio_data, 0, size * count); |
5968 | ||
6f6fbe98 XG |
5969 | ret = emulator_pio_in_out(vcpu, size, port, val, count, true); |
5970 | if (ret) { | |
5971 | data_avail: | |
5972 | memcpy(val, vcpu->arch.pio_data, size * count); | |
1171903d | 5973 | trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); |
7972995b | 5974 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
5975 | return 1; |
5976 | } | |
5977 | ||
cf8f70bf GN |
5978 | return 0; |
5979 | } | |
5980 | ||
6f6fbe98 XG |
5981 | static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, |
5982 | int size, unsigned short port, | |
5983 | const void *val, unsigned int count) | |
5984 | { | |
5985 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
5986 | ||
5987 | memcpy(vcpu->arch.pio_data, val, size * count); | |
1171903d | 5988 | trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); |
6f6fbe98 XG |
5989 | return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); |
5990 | } | |
5991 | ||
bbd9b64e CO |
5992 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) |
5993 | { | |
5994 | return kvm_x86_ops->get_segment_base(vcpu, seg); | |
5995 | } | |
5996 | ||
3cb16fe7 | 5997 | static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) |
bbd9b64e | 5998 | { |
3cb16fe7 | 5999 | kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); |
bbd9b64e CO |
6000 | } |
6001 | ||
ae6a2375 | 6002 | static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) |
f5f48ee1 SY |
6003 | { |
6004 | if (!need_emulate_wbinvd(vcpu)) | |
6005 | return X86EMUL_CONTINUE; | |
6006 | ||
6007 | if (kvm_x86_ops->has_wbinvd_exit()) { | |
2eec7343 JK |
6008 | int cpu = get_cpu(); |
6009 | ||
6010 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
f5f48ee1 SY |
6011 | smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, |
6012 | wbinvd_ipi, NULL, 1); | |
2eec7343 | 6013 | put_cpu(); |
f5f48ee1 | 6014 | cpumask_clear(vcpu->arch.wbinvd_dirty_mask); |
2eec7343 JK |
6015 | } else |
6016 | wbinvd(); | |
f5f48ee1 SY |
6017 | return X86EMUL_CONTINUE; |
6018 | } | |
5cb56059 JS |
6019 | |
6020 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
6021 | { | |
6affcbed KH |
6022 | kvm_emulate_wbinvd_noskip(vcpu); |
6023 | return kvm_skip_emulated_instruction(vcpu); | |
5cb56059 | 6024 | } |
f5f48ee1 SY |
6025 | EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); |
6026 | ||
5cb56059 JS |
6027 | |
6028 | ||
bcaf5cc5 AK |
6029 | static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) |
6030 | { | |
5cb56059 | 6031 | kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); |
bcaf5cc5 AK |
6032 | } |
6033 | ||
52eb5a6d XL |
6034 | static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, |
6035 | unsigned long *dest) | |
bbd9b64e | 6036 | { |
16f8a6f9 | 6037 | return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); |
bbd9b64e CO |
6038 | } |
6039 | ||
52eb5a6d XL |
6040 | static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, |
6041 | unsigned long value) | |
bbd9b64e | 6042 | { |
338dbc97 | 6043 | |
717746e3 | 6044 | return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); |
bbd9b64e CO |
6045 | } |
6046 | ||
52a46617 | 6047 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) |
5fdbf976 | 6048 | { |
52a46617 | 6049 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; |
5fdbf976 MT |
6050 | } |
6051 | ||
717746e3 | 6052 | static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) |
bbd9b64e | 6053 | { |
717746e3 | 6054 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
52a46617 GN |
6055 | unsigned long value; |
6056 | ||
6057 | switch (cr) { | |
6058 | case 0: | |
6059 | value = kvm_read_cr0(vcpu); | |
6060 | break; | |
6061 | case 2: | |
6062 | value = vcpu->arch.cr2; | |
6063 | break; | |
6064 | case 3: | |
9f8fe504 | 6065 | value = kvm_read_cr3(vcpu); |
52a46617 GN |
6066 | break; |
6067 | case 4: | |
6068 | value = kvm_read_cr4(vcpu); | |
6069 | break; | |
6070 | case 8: | |
6071 | value = kvm_get_cr8(vcpu); | |
6072 | break; | |
6073 | default: | |
a737f256 | 6074 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
52a46617 GN |
6075 | return 0; |
6076 | } | |
6077 | ||
6078 | return value; | |
6079 | } | |
6080 | ||
717746e3 | 6081 | static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) |
52a46617 | 6082 | { |
717746e3 | 6083 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
0f12244f GN |
6084 | int res = 0; |
6085 | ||
52a46617 GN |
6086 | switch (cr) { |
6087 | case 0: | |
49a9b07e | 6088 | res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
52a46617 GN |
6089 | break; |
6090 | case 2: | |
6091 | vcpu->arch.cr2 = val; | |
6092 | break; | |
6093 | case 3: | |
2390218b | 6094 | res = kvm_set_cr3(vcpu, val); |
52a46617 GN |
6095 | break; |
6096 | case 4: | |
a83b29c6 | 6097 | res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
52a46617 GN |
6098 | break; |
6099 | case 8: | |
eea1cff9 | 6100 | res = kvm_set_cr8(vcpu, val); |
52a46617 GN |
6101 | break; |
6102 | default: | |
a737f256 | 6103 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
0f12244f | 6104 | res = -1; |
52a46617 | 6105 | } |
0f12244f GN |
6106 | |
6107 | return res; | |
52a46617 GN |
6108 | } |
6109 | ||
717746e3 | 6110 | static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) |
9c537244 | 6111 | { |
717746e3 | 6112 | return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); |
9c537244 GN |
6113 | } |
6114 | ||
4bff1e86 | 6115 | static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
2dafc6c2 | 6116 | { |
4bff1e86 | 6117 | kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); |
2dafc6c2 GN |
6118 | } |
6119 | ||
4bff1e86 | 6120 | static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
160ce1f1 | 6121 | { |
4bff1e86 | 6122 | kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); |
160ce1f1 MG |
6123 | } |
6124 | ||
1ac9d0cf AK |
6125 | static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
6126 | { | |
6127 | kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); | |
6128 | } | |
6129 | ||
6130 | static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) | |
6131 | { | |
6132 | kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); | |
6133 | } | |
6134 | ||
4bff1e86 AK |
6135 | static unsigned long emulator_get_cached_segment_base( |
6136 | struct x86_emulate_ctxt *ctxt, int seg) | |
5951c442 | 6137 | { |
4bff1e86 | 6138 | return get_segment_base(emul_to_vcpu(ctxt), seg); |
5951c442 GN |
6139 | } |
6140 | ||
1aa36616 AK |
6141 | static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, |
6142 | struct desc_struct *desc, u32 *base3, | |
6143 | int seg) | |
2dafc6c2 GN |
6144 | { |
6145 | struct kvm_segment var; | |
6146 | ||
4bff1e86 | 6147 | kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); |
1aa36616 | 6148 | *selector = var.selector; |
2dafc6c2 | 6149 | |
378a8b09 GN |
6150 | if (var.unusable) { |
6151 | memset(desc, 0, sizeof(*desc)); | |
f0367ee1 RK |
6152 | if (base3) |
6153 | *base3 = 0; | |
2dafc6c2 | 6154 | return false; |
378a8b09 | 6155 | } |
2dafc6c2 GN |
6156 | |
6157 | if (var.g) | |
6158 | var.limit >>= 12; | |
6159 | set_desc_limit(desc, var.limit); | |
6160 | set_desc_base(desc, (unsigned long)var.base); | |
5601d05b GN |
6161 | #ifdef CONFIG_X86_64 |
6162 | if (base3) | |
6163 | *base3 = var.base >> 32; | |
6164 | #endif | |
2dafc6c2 GN |
6165 | desc->type = var.type; |
6166 | desc->s = var.s; | |
6167 | desc->dpl = var.dpl; | |
6168 | desc->p = var.present; | |
6169 | desc->avl = var.avl; | |
6170 | desc->l = var.l; | |
6171 | desc->d = var.db; | |
6172 | desc->g = var.g; | |
6173 | ||
6174 | return true; | |
6175 | } | |
6176 | ||
1aa36616 AK |
6177 | static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, |
6178 | struct desc_struct *desc, u32 base3, | |
6179 | int seg) | |
2dafc6c2 | 6180 | { |
4bff1e86 | 6181 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
2dafc6c2 GN |
6182 | struct kvm_segment var; |
6183 | ||
1aa36616 | 6184 | var.selector = selector; |
2dafc6c2 | 6185 | var.base = get_desc_base(desc); |
5601d05b GN |
6186 | #ifdef CONFIG_X86_64 |
6187 | var.base |= ((u64)base3) << 32; | |
6188 | #endif | |
2dafc6c2 GN |
6189 | var.limit = get_desc_limit(desc); |
6190 | if (desc->g) | |
6191 | var.limit = (var.limit << 12) | 0xfff; | |
6192 | var.type = desc->type; | |
2dafc6c2 GN |
6193 | var.dpl = desc->dpl; |
6194 | var.db = desc->d; | |
6195 | var.s = desc->s; | |
6196 | var.l = desc->l; | |
6197 | var.g = desc->g; | |
6198 | var.avl = desc->avl; | |
6199 | var.present = desc->p; | |
6200 | var.unusable = !var.present; | |
6201 | var.padding = 0; | |
6202 | ||
6203 | kvm_set_segment(vcpu, &var, seg); | |
6204 | return; | |
6205 | } | |
6206 | ||
717746e3 AK |
6207 | static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, |
6208 | u32 msr_index, u64 *pdata) | |
6209 | { | |
f20935d8 | 6210 | return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata); |
717746e3 AK |
6211 | } |
6212 | ||
6213 | static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, | |
6214 | u32 msr_index, u64 data) | |
6215 | { | |
f20935d8 | 6216 | return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data); |
717746e3 AK |
6217 | } |
6218 | ||
64d60670 PB |
6219 | static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) |
6220 | { | |
6221 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
6222 | ||
6223 | return vcpu->arch.smbase; | |
6224 | } | |
6225 | ||
6226 | static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) | |
6227 | { | |
6228 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
6229 | ||
6230 | vcpu->arch.smbase = smbase; | |
6231 | } | |
6232 | ||
67f4d428 NA |
6233 | static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, |
6234 | u32 pmc) | |
6235 | { | |
98ff80f5 | 6236 | return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc); |
67f4d428 NA |
6237 | } |
6238 | ||
222d21aa AK |
6239 | static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, |
6240 | u32 pmc, u64 *pdata) | |
6241 | { | |
c6702c9d | 6242 | return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); |
222d21aa AK |
6243 | } |
6244 | ||
6c3287f7 AK |
6245 | static void emulator_halt(struct x86_emulate_ctxt *ctxt) |
6246 | { | |
6247 | emul_to_vcpu(ctxt)->arch.halt_request = 1; | |
6248 | } | |
6249 | ||
2953538e | 6250 | static int emulator_intercept(struct x86_emulate_ctxt *ctxt, |
8a76d7f2 | 6251 | struct x86_instruction_info *info, |
c4f035c6 AK |
6252 | enum x86_intercept_stage stage) |
6253 | { | |
2953538e | 6254 | return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); |
c4f035c6 AK |
6255 | } |
6256 | ||
e911eb3b YZ |
6257 | static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, |
6258 | u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit) | |
bdb42f5a | 6259 | { |
e911eb3b | 6260 | return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit); |
bdb42f5a SB |
6261 | } |
6262 | ||
5ae78e95 SC |
6263 | static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt) |
6264 | { | |
6265 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM); | |
6266 | } | |
6267 | ||
6268 | static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt) | |
6269 | { | |
6270 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE); | |
6271 | } | |
6272 | ||
6273 | static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt) | |
6274 | { | |
6275 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR); | |
6276 | } | |
6277 | ||
dd856efa AK |
6278 | static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) |
6279 | { | |
6280 | return kvm_register_read(emul_to_vcpu(ctxt), reg); | |
6281 | } | |
6282 | ||
6283 | static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) | |
6284 | { | |
6285 | kvm_register_write(emul_to_vcpu(ctxt), reg, val); | |
6286 | } | |
6287 | ||
801806d9 NA |
6288 | static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) |
6289 | { | |
6290 | kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked); | |
6291 | } | |
6292 | ||
6ed071f0 LP |
6293 | static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) |
6294 | { | |
6295 | return emul_to_vcpu(ctxt)->arch.hflags; | |
6296 | } | |
6297 | ||
6298 | static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags) | |
6299 | { | |
c5833c7a | 6300 | emul_to_vcpu(ctxt)->arch.hflags = emul_flags; |
6ed071f0 LP |
6301 | } |
6302 | ||
ed19321f SC |
6303 | static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, |
6304 | const char *smstate) | |
0234bf88 | 6305 | { |
ed19321f | 6306 | return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate); |
0234bf88 LP |
6307 | } |
6308 | ||
c5833c7a SC |
6309 | static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt) |
6310 | { | |
6311 | kvm_smm_changed(emul_to_vcpu(ctxt)); | |
6312 | } | |
6313 | ||
02d4160f VK |
6314 | static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) |
6315 | { | |
6316 | return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); | |
6317 | } | |
6318 | ||
0225fb50 | 6319 | static const struct x86_emulate_ops emulate_ops = { |
dd856efa AK |
6320 | .read_gpr = emulator_read_gpr, |
6321 | .write_gpr = emulator_write_gpr, | |
ce14e868 PB |
6322 | .read_std = emulator_read_std, |
6323 | .write_std = emulator_write_std, | |
7a036a6f | 6324 | .read_phys = kvm_read_guest_phys_system, |
1871c602 | 6325 | .fetch = kvm_fetch_guest_virt, |
bbd9b64e CO |
6326 | .read_emulated = emulator_read_emulated, |
6327 | .write_emulated = emulator_write_emulated, | |
6328 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
3cb16fe7 | 6329 | .invlpg = emulator_invlpg, |
cf8f70bf GN |
6330 | .pio_in_emulated = emulator_pio_in_emulated, |
6331 | .pio_out_emulated = emulator_pio_out_emulated, | |
1aa36616 AK |
6332 | .get_segment = emulator_get_segment, |
6333 | .set_segment = emulator_set_segment, | |
5951c442 | 6334 | .get_cached_segment_base = emulator_get_cached_segment_base, |
2dafc6c2 | 6335 | .get_gdt = emulator_get_gdt, |
160ce1f1 | 6336 | .get_idt = emulator_get_idt, |
1ac9d0cf AK |
6337 | .set_gdt = emulator_set_gdt, |
6338 | .set_idt = emulator_set_idt, | |
52a46617 GN |
6339 | .get_cr = emulator_get_cr, |
6340 | .set_cr = emulator_set_cr, | |
9c537244 | 6341 | .cpl = emulator_get_cpl, |
35aa5375 GN |
6342 | .get_dr = emulator_get_dr, |
6343 | .set_dr = emulator_set_dr, | |
64d60670 PB |
6344 | .get_smbase = emulator_get_smbase, |
6345 | .set_smbase = emulator_set_smbase, | |
717746e3 AK |
6346 | .set_msr = emulator_set_msr, |
6347 | .get_msr = emulator_get_msr, | |
67f4d428 | 6348 | .check_pmc = emulator_check_pmc, |
222d21aa | 6349 | .read_pmc = emulator_read_pmc, |
6c3287f7 | 6350 | .halt = emulator_halt, |
bcaf5cc5 | 6351 | .wbinvd = emulator_wbinvd, |
d6aa1000 | 6352 | .fix_hypercall = emulator_fix_hypercall, |
c4f035c6 | 6353 | .intercept = emulator_intercept, |
bdb42f5a | 6354 | .get_cpuid = emulator_get_cpuid, |
5ae78e95 SC |
6355 | .guest_has_long_mode = emulator_guest_has_long_mode, |
6356 | .guest_has_movbe = emulator_guest_has_movbe, | |
6357 | .guest_has_fxsr = emulator_guest_has_fxsr, | |
801806d9 | 6358 | .set_nmi_mask = emulator_set_nmi_mask, |
6ed071f0 LP |
6359 | .get_hflags = emulator_get_hflags, |
6360 | .set_hflags = emulator_set_hflags, | |
0234bf88 | 6361 | .pre_leave_smm = emulator_pre_leave_smm, |
c5833c7a | 6362 | .post_leave_smm = emulator_post_leave_smm, |
02d4160f | 6363 | .set_xcr = emulator_set_xcr, |
bbd9b64e CO |
6364 | }; |
6365 | ||
95cb2295 GN |
6366 | static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) |
6367 | { | |
37ccdcbe | 6368 | u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); |
95cb2295 GN |
6369 | /* |
6370 | * an sti; sti; sequence only disable interrupts for the first | |
6371 | * instruction. So, if the last instruction, be it emulated or | |
6372 | * not, left the system with the INT_STI flag enabled, it | |
6373 | * means that the last instruction is an sti. We should not | |
6374 | * leave the flag on in this case. The same goes for mov ss | |
6375 | */ | |
37ccdcbe PB |
6376 | if (int_shadow & mask) |
6377 | mask = 0; | |
6addfc42 | 6378 | if (unlikely(int_shadow || mask)) { |
95cb2295 | 6379 | kvm_x86_ops->set_interrupt_shadow(vcpu, mask); |
6addfc42 PB |
6380 | if (!mask) |
6381 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
6382 | } | |
95cb2295 GN |
6383 | } |
6384 | ||
ef54bcfe | 6385 | static bool inject_emulated_exception(struct kvm_vcpu *vcpu) |
54b8486f GN |
6386 | { |
6387 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; | |
da9cb575 | 6388 | if (ctxt->exception.vector == PF_VECTOR) |
ef54bcfe PB |
6389 | return kvm_propagate_fault(vcpu, &ctxt->exception); |
6390 | ||
6391 | if (ctxt->exception.error_code_valid) | |
da9cb575 AK |
6392 | kvm_queue_exception_e(vcpu, ctxt->exception.vector, |
6393 | ctxt->exception.error_code); | |
54b8486f | 6394 | else |
da9cb575 | 6395 | kvm_queue_exception(vcpu, ctxt->exception.vector); |
ef54bcfe | 6396 | return false; |
54b8486f GN |
6397 | } |
6398 | ||
8ec4722d MG |
6399 | static void init_emulate_ctxt(struct kvm_vcpu *vcpu) |
6400 | { | |
adf52235 | 6401 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
8ec4722d MG |
6402 | int cs_db, cs_l; |
6403 | ||
8ec4722d MG |
6404 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
6405 | ||
adf52235 | 6406 | ctxt->eflags = kvm_get_rflags(vcpu); |
c8401dda PB |
6407 | ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; |
6408 | ||
adf52235 TY |
6409 | ctxt->eip = kvm_rip_read(vcpu); |
6410 | ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : | |
6411 | (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : | |
42bf549f | 6412 | (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : |
adf52235 TY |
6413 | cs_db ? X86EMUL_MODE_PROT32 : |
6414 | X86EMUL_MODE_PROT16; | |
a584539b | 6415 | BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); |
64d60670 PB |
6416 | BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); |
6417 | BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); | |
adf52235 | 6418 | |
dd856efa | 6419 | init_decode_cache(ctxt); |
7ae441ea | 6420 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; |
8ec4722d MG |
6421 | } |
6422 | ||
9497e1f2 | 6423 | void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) |
63995653 | 6424 | { |
9d74191a | 6425 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
63995653 MG |
6426 | int ret; |
6427 | ||
6428 | init_emulate_ctxt(vcpu); | |
6429 | ||
9dac77fa AK |
6430 | ctxt->op_bytes = 2; |
6431 | ctxt->ad_bytes = 2; | |
6432 | ctxt->_eip = ctxt->eip + inc_eip; | |
9d74191a | 6433 | ret = emulate_int_real(ctxt, irq); |
63995653 | 6434 | |
9497e1f2 SC |
6435 | if (ret != X86EMUL_CONTINUE) { |
6436 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
6437 | } else { | |
6438 | ctxt->eip = ctxt->_eip; | |
6439 | kvm_rip_write(vcpu, ctxt->eip); | |
6440 | kvm_set_rflags(vcpu, ctxt->eflags); | |
6441 | } | |
63995653 MG |
6442 | } |
6443 | EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); | |
6444 | ||
e2366171 | 6445 | static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) |
6d77dbfc | 6446 | { |
6d77dbfc GN |
6447 | ++vcpu->stat.insn_emulation_fail; |
6448 | trace_kvm_emulate_insn_failed(vcpu); | |
e2366171 | 6449 | |
42cbf068 SC |
6450 | if (emulation_type & EMULTYPE_VMWARE_GP) { |
6451 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
60fc3d02 | 6452 | return 1; |
42cbf068 | 6453 | } |
e2366171 | 6454 | |
738fece4 SC |
6455 | if (emulation_type & EMULTYPE_SKIP) { |
6456 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
6457 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
6458 | vcpu->run->internal.ndata = 0; | |
60fc3d02 | 6459 | return 0; |
738fece4 SC |
6460 | } |
6461 | ||
22da61c9 SC |
6462 | kvm_queue_exception(vcpu, UD_VECTOR); |
6463 | ||
a2b9e6c1 | 6464 | if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) { |
fc3a9157 JR |
6465 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
6466 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
6467 | vcpu->run->internal.ndata = 0; | |
60fc3d02 | 6468 | return 0; |
fc3a9157 | 6469 | } |
e2366171 | 6470 | |
60fc3d02 | 6471 | return 1; |
6d77dbfc GN |
6472 | } |
6473 | ||
736c291c | 6474 | static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
991eebf9 GN |
6475 | bool write_fault_to_shadow_pgtable, |
6476 | int emulation_type) | |
a6f177ef | 6477 | { |
736c291c | 6478 | gpa_t gpa = cr2_or_gpa; |
ba049e93 | 6479 | kvm_pfn_t pfn; |
a6f177ef | 6480 | |
384bf221 | 6481 | if (!(emulation_type & EMULTYPE_ALLOW_RETRY)) |
991eebf9 GN |
6482 | return false; |
6483 | ||
6c3dfeb6 SC |
6484 | if (WARN_ON_ONCE(is_guest_mode(vcpu))) |
6485 | return false; | |
6486 | ||
44dd3ffa | 6487 | if (!vcpu->arch.mmu->direct_map) { |
95b3cf69 XG |
6488 | /* |
6489 | * Write permission should be allowed since only | |
6490 | * write access need to be emulated. | |
6491 | */ | |
736c291c | 6492 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); |
a6f177ef | 6493 | |
95b3cf69 XG |
6494 | /* |
6495 | * If the mapping is invalid in guest, let cpu retry | |
6496 | * it to generate fault. | |
6497 | */ | |
6498 | if (gpa == UNMAPPED_GVA) | |
6499 | return true; | |
6500 | } | |
a6f177ef | 6501 | |
8e3d9d06 XG |
6502 | /* |
6503 | * Do not retry the unhandleable instruction if it faults on the | |
6504 | * readonly host memory, otherwise it will goto a infinite loop: | |
6505 | * retry instruction -> write #PF -> emulation fail -> retry | |
6506 | * instruction -> ... | |
6507 | */ | |
6508 | pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); | |
95b3cf69 XG |
6509 | |
6510 | /* | |
6511 | * If the instruction failed on the error pfn, it can not be fixed, | |
6512 | * report the error to userspace. | |
6513 | */ | |
6514 | if (is_error_noslot_pfn(pfn)) | |
6515 | return false; | |
6516 | ||
6517 | kvm_release_pfn_clean(pfn); | |
6518 | ||
6519 | /* The instructions are well-emulated on direct mmu. */ | |
44dd3ffa | 6520 | if (vcpu->arch.mmu->direct_map) { |
95b3cf69 XG |
6521 | unsigned int indirect_shadow_pages; |
6522 | ||
6523 | spin_lock(&vcpu->kvm->mmu_lock); | |
6524 | indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; | |
6525 | spin_unlock(&vcpu->kvm->mmu_lock); | |
6526 | ||
6527 | if (indirect_shadow_pages) | |
6528 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
6529 | ||
a6f177ef | 6530 | return true; |
8e3d9d06 | 6531 | } |
a6f177ef | 6532 | |
95b3cf69 XG |
6533 | /* |
6534 | * if emulation was due to access to shadowed page table | |
6535 | * and it failed try to unshadow page and re-enter the | |
6536 | * guest to let CPU execute the instruction. | |
6537 | */ | |
6538 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
93c05d3e XG |
6539 | |
6540 | /* | |
6541 | * If the access faults on its page table, it can not | |
6542 | * be fixed by unprotecting shadow page and it should | |
6543 | * be reported to userspace. | |
6544 | */ | |
6545 | return !write_fault_to_shadow_pgtable; | |
a6f177ef GN |
6546 | } |
6547 | ||
1cb3f3ae | 6548 | static bool retry_instruction(struct x86_emulate_ctxt *ctxt, |
736c291c | 6549 | gpa_t cr2_or_gpa, int emulation_type) |
1cb3f3ae XG |
6550 | { |
6551 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
736c291c | 6552 | unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa; |
1cb3f3ae XG |
6553 | |
6554 | last_retry_eip = vcpu->arch.last_retry_eip; | |
6555 | last_retry_addr = vcpu->arch.last_retry_addr; | |
6556 | ||
6557 | /* | |
6558 | * If the emulation is caused by #PF and it is non-page_table | |
6559 | * writing instruction, it means the VM-EXIT is caused by shadow | |
6560 | * page protected, we can zap the shadow page and retry this | |
6561 | * instruction directly. | |
6562 | * | |
6563 | * Note: if the guest uses a non-page-table modifying instruction | |
6564 | * on the PDE that points to the instruction, then we will unmap | |
6565 | * the instruction and go to an infinite loop. So, we cache the | |
6566 | * last retried eip and the last fault address, if we meet the eip | |
6567 | * and the address again, we can break out of the potential infinite | |
6568 | * loop. | |
6569 | */ | |
6570 | vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; | |
6571 | ||
384bf221 | 6572 | if (!(emulation_type & EMULTYPE_ALLOW_RETRY)) |
1cb3f3ae XG |
6573 | return false; |
6574 | ||
6c3dfeb6 SC |
6575 | if (WARN_ON_ONCE(is_guest_mode(vcpu))) |
6576 | return false; | |
6577 | ||
1cb3f3ae XG |
6578 | if (x86_page_table_writing_insn(ctxt)) |
6579 | return false; | |
6580 | ||
736c291c | 6581 | if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa) |
1cb3f3ae XG |
6582 | return false; |
6583 | ||
6584 | vcpu->arch.last_retry_eip = ctxt->eip; | |
736c291c | 6585 | vcpu->arch.last_retry_addr = cr2_or_gpa; |
1cb3f3ae | 6586 | |
44dd3ffa | 6587 | if (!vcpu->arch.mmu->direct_map) |
736c291c | 6588 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); |
1cb3f3ae | 6589 | |
22368028 | 6590 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); |
1cb3f3ae XG |
6591 | |
6592 | return true; | |
6593 | } | |
6594 | ||
716d51ab GN |
6595 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu); |
6596 | static int complete_emulated_pio(struct kvm_vcpu *vcpu); | |
6597 | ||
64d60670 | 6598 | static void kvm_smm_changed(struct kvm_vcpu *vcpu) |
a584539b | 6599 | { |
64d60670 | 6600 | if (!(vcpu->arch.hflags & HF_SMM_MASK)) { |
660a5d51 PB |
6601 | /* This is a good place to trace that we are exiting SMM. */ |
6602 | trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); | |
6603 | ||
c43203ca PB |
6604 | /* Process a latched INIT or SMI, if any. */ |
6605 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
64d60670 | 6606 | } |
699023e2 PB |
6607 | |
6608 | kvm_mmu_reset_context(vcpu); | |
64d60670 PB |
6609 | } |
6610 | ||
4a1e10d5 PB |
6611 | static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, |
6612 | unsigned long *db) | |
6613 | { | |
6614 | u32 dr6 = 0; | |
6615 | int i; | |
6616 | u32 enable, rwlen; | |
6617 | ||
6618 | enable = dr7; | |
6619 | rwlen = dr7 >> 16; | |
6620 | for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) | |
6621 | if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) | |
6622 | dr6 |= (1 << i); | |
6623 | return dr6; | |
6624 | } | |
6625 | ||
120c2c4f | 6626 | static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu) |
663f4c61 PB |
6627 | { |
6628 | struct kvm_run *kvm_run = vcpu->run; | |
6629 | ||
c8401dda PB |
6630 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { |
6631 | kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM; | |
6632 | kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; | |
6633 | kvm_run->debug.arch.exception = DB_VECTOR; | |
6634 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
60fc3d02 | 6635 | return 0; |
663f4c61 | 6636 | } |
120c2c4f | 6637 | kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); |
60fc3d02 | 6638 | return 1; |
663f4c61 PB |
6639 | } |
6640 | ||
6affcbed KH |
6641 | int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) |
6642 | { | |
6643 | unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); | |
f8ea7c60 | 6644 | int r; |
6affcbed | 6645 | |
f8ea7c60 | 6646 | r = kvm_x86_ops->skip_emulated_instruction(vcpu); |
60fc3d02 | 6647 | if (unlikely(!r)) |
f8ea7c60 | 6648 | return 0; |
c8401dda PB |
6649 | |
6650 | /* | |
6651 | * rflags is the old, "raw" value of the flags. The new value has | |
6652 | * not been saved yet. | |
6653 | * | |
6654 | * This is correct even for TF set by the guest, because "the | |
6655 | * processor will not generate this exception after the instruction | |
6656 | * that sets the TF flag". | |
6657 | */ | |
6658 | if (unlikely(rflags & X86_EFLAGS_TF)) | |
120c2c4f | 6659 | r = kvm_vcpu_do_singlestep(vcpu); |
60fc3d02 | 6660 | return r; |
6affcbed KH |
6661 | } |
6662 | EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); | |
6663 | ||
4a1e10d5 PB |
6664 | static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) |
6665 | { | |
4a1e10d5 PB |
6666 | if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && |
6667 | (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { | |
82b32774 NA |
6668 | struct kvm_run *kvm_run = vcpu->run; |
6669 | unsigned long eip = kvm_get_linear_rip(vcpu); | |
6670 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
6671 | vcpu->arch.guest_debug_dr7, |
6672 | vcpu->arch.eff_db); | |
6673 | ||
6674 | if (dr6 != 0) { | |
6f43ed01 | 6675 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; |
82b32774 | 6676 | kvm_run->debug.arch.pc = eip; |
4a1e10d5 PB |
6677 | kvm_run->debug.arch.exception = DB_VECTOR; |
6678 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
60fc3d02 | 6679 | *r = 0; |
4a1e10d5 PB |
6680 | return true; |
6681 | } | |
6682 | } | |
6683 | ||
4161a569 NA |
6684 | if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && |
6685 | !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { | |
82b32774 NA |
6686 | unsigned long eip = kvm_get_linear_rip(vcpu); |
6687 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
6688 | vcpu->arch.dr7, |
6689 | vcpu->arch.db); | |
6690 | ||
6691 | if (dr6 != 0) { | |
1fc5d194 | 6692 | vcpu->arch.dr6 &= ~DR_TRAP_BITS; |
6f43ed01 | 6693 | vcpu->arch.dr6 |= dr6 | DR6_RTM; |
4a1e10d5 | 6694 | kvm_queue_exception(vcpu, DB_VECTOR); |
60fc3d02 | 6695 | *r = 1; |
4a1e10d5 PB |
6696 | return true; |
6697 | } | |
6698 | } | |
6699 | ||
6700 | return false; | |
6701 | } | |
6702 | ||
04789b66 LA |
6703 | static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) |
6704 | { | |
2d7921c4 AM |
6705 | switch (ctxt->opcode_len) { |
6706 | case 1: | |
6707 | switch (ctxt->b) { | |
6708 | case 0xe4: /* IN */ | |
6709 | case 0xe5: | |
6710 | case 0xec: | |
6711 | case 0xed: | |
6712 | case 0xe6: /* OUT */ | |
6713 | case 0xe7: | |
6714 | case 0xee: | |
6715 | case 0xef: | |
6716 | case 0x6c: /* INS */ | |
6717 | case 0x6d: | |
6718 | case 0x6e: /* OUTS */ | |
6719 | case 0x6f: | |
6720 | return true; | |
6721 | } | |
6722 | break; | |
6723 | case 2: | |
6724 | switch (ctxt->b) { | |
6725 | case 0x33: /* RDPMC */ | |
6726 | return true; | |
6727 | } | |
6728 | break; | |
04789b66 LA |
6729 | } |
6730 | ||
6731 | return false; | |
6732 | } | |
6733 | ||
736c291c SC |
6734 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
6735 | int emulation_type, void *insn, int insn_len) | |
bbd9b64e | 6736 | { |
95cb2295 | 6737 | int r; |
9d74191a | 6738 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
7ae441ea | 6739 | bool writeback = true; |
93c05d3e | 6740 | bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; |
bbd9b64e | 6741 | |
c595ceee PB |
6742 | vcpu->arch.l1tf_flush_l1d = true; |
6743 | ||
93c05d3e XG |
6744 | /* |
6745 | * Clear write_fault_to_shadow_pgtable here to ensure it is | |
6746 | * never reused. | |
6747 | */ | |
6748 | vcpu->arch.write_fault_to_shadow_pgtable = false; | |
26eef70c | 6749 | kvm_clear_exception_queue(vcpu); |
8d7d8102 | 6750 | |
571008da | 6751 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
8ec4722d | 6752 | init_emulate_ctxt(vcpu); |
4a1e10d5 PB |
6753 | |
6754 | /* | |
6755 | * We will reenter on the same instruction since | |
6756 | * we do not set complete_userspace_io. This does not | |
6757 | * handle watchpoints yet, those would be handled in | |
6758 | * the emulate_ops. | |
6759 | */ | |
d391f120 VK |
6760 | if (!(emulation_type & EMULTYPE_SKIP) && |
6761 | kvm_vcpu_check_breakpoint(vcpu, &r)) | |
4a1e10d5 PB |
6762 | return r; |
6763 | ||
9d74191a TY |
6764 | ctxt->interruptibility = 0; |
6765 | ctxt->have_exception = false; | |
e0ad0b47 | 6766 | ctxt->exception.vector = -1; |
9d74191a | 6767 | ctxt->perm_ok = false; |
bbd9b64e | 6768 | |
b51e974f | 6769 | ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; |
4005996e | 6770 | |
9d74191a | 6771 | r = x86_decode_insn(ctxt, insn, insn_len); |
bbd9b64e | 6772 | |
e46479f8 | 6773 | trace_kvm_emulate_insn_start(vcpu); |
f2b5756b | 6774 | ++vcpu->stat.insn_emulation; |
1d2887e2 | 6775 | if (r != EMULATION_OK) { |
b4000606 | 6776 | if ((emulation_type & EMULTYPE_TRAP_UD) || |
c83fad65 SC |
6777 | (emulation_type & EMULTYPE_TRAP_UD_FORCED)) { |
6778 | kvm_queue_exception(vcpu, UD_VECTOR); | |
60fc3d02 | 6779 | return 1; |
c83fad65 | 6780 | } |
736c291c SC |
6781 | if (reexecute_instruction(vcpu, cr2_or_gpa, |
6782 | write_fault_to_spt, | |
6783 | emulation_type)) | |
60fc3d02 | 6784 | return 1; |
8530a79c | 6785 | if (ctxt->have_exception) { |
c8848cee JD |
6786 | /* |
6787 | * #UD should result in just EMULATION_FAILED, and trap-like | |
6788 | * exception should not be encountered during decode. | |
6789 | */ | |
6790 | WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || | |
6791 | exception_type(ctxt->exception.vector) == EXCPT_TRAP); | |
8530a79c | 6792 | inject_emulated_exception(vcpu); |
60fc3d02 | 6793 | return 1; |
8530a79c | 6794 | } |
e2366171 | 6795 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
6796 | } |
6797 | } | |
6798 | ||
42cbf068 SC |
6799 | if ((emulation_type & EMULTYPE_VMWARE_GP) && |
6800 | !is_vmware_backdoor_opcode(ctxt)) { | |
6801 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
60fc3d02 | 6802 | return 1; |
42cbf068 | 6803 | } |
04789b66 | 6804 | |
1957aa63 SC |
6805 | /* |
6806 | * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks | |
6807 | * for kvm_skip_emulated_instruction(). The caller is responsible for | |
6808 | * updating interruptibility state and injecting single-step #DBs. | |
6809 | */ | |
ba8afb6b | 6810 | if (emulation_type & EMULTYPE_SKIP) { |
9dac77fa | 6811 | kvm_rip_write(vcpu, ctxt->_eip); |
bb663c7a NA |
6812 | if (ctxt->eflags & X86_EFLAGS_RF) |
6813 | kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); | |
60fc3d02 | 6814 | return 1; |
ba8afb6b GN |
6815 | } |
6816 | ||
736c291c | 6817 | if (retry_instruction(ctxt, cr2_or_gpa, emulation_type)) |
60fc3d02 | 6818 | return 1; |
1cb3f3ae | 6819 | |
7ae441ea | 6820 | /* this is needed for vmware backdoor interface to work since it |
4d2179e1 | 6821 | changes registers values during IO operation */ |
7ae441ea GN |
6822 | if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { |
6823 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; | |
dd856efa | 6824 | emulator_invalidate_register_cache(ctxt); |
7ae441ea | 6825 | } |
4d2179e1 | 6826 | |
5cd21917 | 6827 | restart: |
0f89b207 | 6828 | /* Save the faulting GPA (cr2) in the address field */ |
736c291c | 6829 | ctxt->exception.address = cr2_or_gpa; |
0f89b207 | 6830 | |
9d74191a | 6831 | r = x86_emulate_insn(ctxt); |
bbd9b64e | 6832 | |
775fde86 | 6833 | if (r == EMULATION_INTERCEPTED) |
60fc3d02 | 6834 | return 1; |
775fde86 | 6835 | |
d2ddd1c4 | 6836 | if (r == EMULATION_FAILED) { |
736c291c | 6837 | if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt, |
991eebf9 | 6838 | emulation_type)) |
60fc3d02 | 6839 | return 1; |
c3cd7ffa | 6840 | |
e2366171 | 6841 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
6842 | } |
6843 | ||
9d74191a | 6844 | if (ctxt->have_exception) { |
60fc3d02 | 6845 | r = 1; |
ef54bcfe PB |
6846 | if (inject_emulated_exception(vcpu)) |
6847 | return r; | |
d2ddd1c4 | 6848 | } else if (vcpu->arch.pio.count) { |
0912c977 PB |
6849 | if (!vcpu->arch.pio.in) { |
6850 | /* FIXME: return into emulator if single-stepping. */ | |
3457e419 | 6851 | vcpu->arch.pio.count = 0; |
0912c977 | 6852 | } else { |
7ae441ea | 6853 | writeback = false; |
716d51ab GN |
6854 | vcpu->arch.complete_userspace_io = complete_emulated_pio; |
6855 | } | |
60fc3d02 | 6856 | r = 0; |
7ae441ea | 6857 | } else if (vcpu->mmio_needed) { |
bc8a0aaf SC |
6858 | ++vcpu->stat.mmio_exits; |
6859 | ||
7ae441ea GN |
6860 | if (!vcpu->mmio_is_write) |
6861 | writeback = false; | |
60fc3d02 | 6862 | r = 0; |
716d51ab | 6863 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; |
7ae441ea | 6864 | } else if (r == EMULATION_RESTART) |
5cd21917 | 6865 | goto restart; |
d2ddd1c4 | 6866 | else |
60fc3d02 | 6867 | r = 1; |
f850e2e6 | 6868 | |
7ae441ea | 6869 | if (writeback) { |
6addfc42 | 6870 | unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); |
9d74191a | 6871 | toggle_interruptibility(vcpu, ctxt->interruptibility); |
7ae441ea | 6872 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
38827dbd | 6873 | if (!ctxt->have_exception || |
75ee23b3 SC |
6874 | exception_type(ctxt->exception.vector) == EXCPT_TRAP) { |
6875 | kvm_rip_write(vcpu, ctxt->eip); | |
60fc3d02 | 6876 | if (r && ctxt->tf) |
120c2c4f | 6877 | r = kvm_vcpu_do_singlestep(vcpu); |
38827dbd | 6878 | __kvm_set_rflags(vcpu, ctxt->eflags); |
75ee23b3 | 6879 | } |
6addfc42 PB |
6880 | |
6881 | /* | |
6882 | * For STI, interrupts are shadowed; so KVM_REQ_EVENT will | |
6883 | * do nothing, and it will be requested again as soon as | |
6884 | * the shadow expires. But we still need to check here, | |
6885 | * because POPF has no interrupt shadow. | |
6886 | */ | |
6887 | if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) | |
6888 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7ae441ea GN |
6889 | } else |
6890 | vcpu->arch.emulate_regs_need_sync_to_vcpu = true; | |
e85d28f8 GN |
6891 | |
6892 | return r; | |
de7d789a | 6893 | } |
c60658d1 SC |
6894 | |
6895 | int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) | |
6896 | { | |
6897 | return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); | |
6898 | } | |
6899 | EXPORT_SYMBOL_GPL(kvm_emulate_instruction); | |
6900 | ||
6901 | int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, | |
6902 | void *insn, int insn_len) | |
6903 | { | |
6904 | return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); | |
6905 | } | |
6906 | EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); | |
de7d789a | 6907 | |
8764ed55 SC |
6908 | static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) |
6909 | { | |
6910 | vcpu->arch.pio.count = 0; | |
6911 | return 1; | |
6912 | } | |
6913 | ||
45def77e SC |
6914 | static int complete_fast_pio_out(struct kvm_vcpu *vcpu) |
6915 | { | |
6916 | vcpu->arch.pio.count = 0; | |
6917 | ||
6918 | if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) | |
6919 | return 1; | |
6920 | ||
6921 | return kvm_skip_emulated_instruction(vcpu); | |
6922 | } | |
6923 | ||
dca7f128 SC |
6924 | static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, |
6925 | unsigned short port) | |
de7d789a | 6926 | { |
de3cd117 | 6927 | unsigned long val = kvm_rax_read(vcpu); |
ca1d4a9e AK |
6928 | int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, |
6929 | size, port, &val, 1); | |
8764ed55 SC |
6930 | if (ret) |
6931 | return ret; | |
45def77e | 6932 | |
8764ed55 SC |
6933 | /* |
6934 | * Workaround userspace that relies on old KVM behavior of %rip being | |
6935 | * incremented prior to exiting to userspace to handle "OUT 0x7e". | |
6936 | */ | |
6937 | if (port == 0x7e && | |
6938 | kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { | |
6939 | vcpu->arch.complete_userspace_io = | |
6940 | complete_fast_pio_out_port_0x7e; | |
6941 | kvm_skip_emulated_instruction(vcpu); | |
6942 | } else { | |
45def77e SC |
6943 | vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); |
6944 | vcpu->arch.complete_userspace_io = complete_fast_pio_out; | |
6945 | } | |
8764ed55 | 6946 | return 0; |
de7d789a | 6947 | } |
de7d789a | 6948 | |
8370c3d0 TL |
6949 | static int complete_fast_pio_in(struct kvm_vcpu *vcpu) |
6950 | { | |
6951 | unsigned long val; | |
6952 | ||
6953 | /* We should only ever be called with arch.pio.count equal to 1 */ | |
6954 | BUG_ON(vcpu->arch.pio.count != 1); | |
6955 | ||
45def77e SC |
6956 | if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { |
6957 | vcpu->arch.pio.count = 0; | |
6958 | return 1; | |
6959 | } | |
6960 | ||
8370c3d0 | 6961 | /* For size less than 4 we merge, else we zero extend */ |
de3cd117 | 6962 | val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; |
8370c3d0 TL |
6963 | |
6964 | /* | |
6965 | * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform | |
6966 | * the copy and tracing | |
6967 | */ | |
6968 | emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size, | |
6969 | vcpu->arch.pio.port, &val, 1); | |
de3cd117 | 6970 | kvm_rax_write(vcpu, val); |
8370c3d0 | 6971 | |
45def77e | 6972 | return kvm_skip_emulated_instruction(vcpu); |
8370c3d0 TL |
6973 | } |
6974 | ||
dca7f128 SC |
6975 | static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, |
6976 | unsigned short port) | |
8370c3d0 TL |
6977 | { |
6978 | unsigned long val; | |
6979 | int ret; | |
6980 | ||
6981 | /* For size less than 4 we merge, else we zero extend */ | |
de3cd117 | 6982 | val = (size < 4) ? kvm_rax_read(vcpu) : 0; |
8370c3d0 TL |
6983 | |
6984 | ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port, | |
6985 | &val, 1); | |
6986 | if (ret) { | |
de3cd117 | 6987 | kvm_rax_write(vcpu, val); |
8370c3d0 TL |
6988 | return ret; |
6989 | } | |
6990 | ||
45def77e | 6991 | vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); |
8370c3d0 TL |
6992 | vcpu->arch.complete_userspace_io = complete_fast_pio_in; |
6993 | ||
6994 | return 0; | |
6995 | } | |
dca7f128 SC |
6996 | |
6997 | int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) | |
6998 | { | |
45def77e | 6999 | int ret; |
dca7f128 | 7000 | |
dca7f128 | 7001 | if (in) |
45def77e | 7002 | ret = kvm_fast_pio_in(vcpu, size, port); |
dca7f128 | 7003 | else |
45def77e SC |
7004 | ret = kvm_fast_pio_out(vcpu, size, port); |
7005 | return ret && kvm_skip_emulated_instruction(vcpu); | |
dca7f128 SC |
7006 | } |
7007 | EXPORT_SYMBOL_GPL(kvm_fast_pio); | |
8370c3d0 | 7008 | |
251a5fd6 | 7009 | static int kvmclock_cpu_down_prep(unsigned int cpu) |
8cfdc000 | 7010 | { |
0a3aee0d | 7011 | __this_cpu_write(cpu_tsc_khz, 0); |
251a5fd6 | 7012 | return 0; |
8cfdc000 ZA |
7013 | } |
7014 | ||
7015 | static void tsc_khz_changed(void *data) | |
c8076604 | 7016 | { |
8cfdc000 ZA |
7017 | struct cpufreq_freqs *freq = data; |
7018 | unsigned long khz = 0; | |
7019 | ||
7020 | if (data) | |
7021 | khz = freq->new; | |
7022 | else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
7023 | khz = cpufreq_quick_get(raw_smp_processor_id()); | |
7024 | if (!khz) | |
7025 | khz = tsc_khz; | |
0a3aee0d | 7026 | __this_cpu_write(cpu_tsc_khz, khz); |
c8076604 GH |
7027 | } |
7028 | ||
5fa4ec9c | 7029 | #ifdef CONFIG_X86_64 |
0092e434 VK |
7030 | static void kvm_hyperv_tsc_notifier(void) |
7031 | { | |
0092e434 VK |
7032 | struct kvm *kvm; |
7033 | struct kvm_vcpu *vcpu; | |
7034 | int cpu; | |
7035 | ||
0d9ce162 | 7036 | mutex_lock(&kvm_lock); |
0092e434 VK |
7037 | list_for_each_entry(kvm, &vm_list, vm_list) |
7038 | kvm_make_mclock_inprogress_request(kvm); | |
7039 | ||
7040 | hyperv_stop_tsc_emulation(); | |
7041 | ||
7042 | /* TSC frequency always matches when on Hyper-V */ | |
7043 | for_each_present_cpu(cpu) | |
7044 | per_cpu(cpu_tsc_khz, cpu) = tsc_khz; | |
7045 | kvm_max_guest_tsc_khz = tsc_khz; | |
7046 | ||
7047 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
7048 | struct kvm_arch *ka = &kvm->arch; | |
7049 | ||
7050 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
7051 | ||
7052 | pvclock_update_vm_gtod_copy(kvm); | |
7053 | ||
7054 | kvm_for_each_vcpu(cpu, vcpu, kvm) | |
7055 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
7056 | ||
7057 | kvm_for_each_vcpu(cpu, vcpu, kvm) | |
7058 | kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); | |
7059 | ||
7060 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
7061 | } | |
0d9ce162 | 7062 | mutex_unlock(&kvm_lock); |
0092e434 | 7063 | } |
5fa4ec9c | 7064 | #endif |
0092e434 | 7065 | |
df24014a | 7066 | static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) |
c8076604 | 7067 | { |
c8076604 GH |
7068 | struct kvm *kvm; |
7069 | struct kvm_vcpu *vcpu; | |
7070 | int i, send_ipi = 0; | |
7071 | ||
8cfdc000 ZA |
7072 | /* |
7073 | * We allow guests to temporarily run on slowing clocks, | |
7074 | * provided we notify them after, or to run on accelerating | |
7075 | * clocks, provided we notify them before. Thus time never | |
7076 | * goes backwards. | |
7077 | * | |
7078 | * However, we have a problem. We can't atomically update | |
7079 | * the frequency of a given CPU from this function; it is | |
7080 | * merely a notifier, which can be called from any CPU. | |
7081 | * Changing the TSC frequency at arbitrary points in time | |
7082 | * requires a recomputation of local variables related to | |
7083 | * the TSC for each VCPU. We must flag these local variables | |
7084 | * to be updated and be sure the update takes place with the | |
7085 | * new frequency before any guests proceed. | |
7086 | * | |
7087 | * Unfortunately, the combination of hotplug CPU and frequency | |
7088 | * change creates an intractable locking scenario; the order | |
7089 | * of when these callouts happen is undefined with respect to | |
7090 | * CPU hotplug, and they can race with each other. As such, | |
7091 | * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is | |
7092 | * undefined; you can actually have a CPU frequency change take | |
7093 | * place in between the computation of X and the setting of the | |
7094 | * variable. To protect against this problem, all updates of | |
7095 | * the per_cpu tsc_khz variable are done in an interrupt | |
7096 | * protected IPI, and all callers wishing to update the value | |
7097 | * must wait for a synchronous IPI to complete (which is trivial | |
7098 | * if the caller is on the CPU already). This establishes the | |
7099 | * necessary total order on variable updates. | |
7100 | * | |
7101 | * Note that because a guest time update may take place | |
7102 | * anytime after the setting of the VCPU's request bit, the | |
7103 | * correct TSC value must be set before the request. However, | |
7104 | * to ensure the update actually makes it to any guest which | |
7105 | * starts running in hardware virtualization between the set | |
7106 | * and the acquisition of the spinlock, we must also ping the | |
7107 | * CPU after setting the request bit. | |
7108 | * | |
7109 | */ | |
7110 | ||
df24014a | 7111 | smp_call_function_single(cpu, tsc_khz_changed, freq, 1); |
c8076604 | 7112 | |
0d9ce162 | 7113 | mutex_lock(&kvm_lock); |
c8076604 | 7114 | list_for_each_entry(kvm, &vm_list, vm_list) { |
988a2cae | 7115 | kvm_for_each_vcpu(i, vcpu, kvm) { |
df24014a | 7116 | if (vcpu->cpu != cpu) |
c8076604 | 7117 | continue; |
c285545f | 7118 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0d9ce162 | 7119 | if (vcpu->cpu != raw_smp_processor_id()) |
8cfdc000 | 7120 | send_ipi = 1; |
c8076604 GH |
7121 | } |
7122 | } | |
0d9ce162 | 7123 | mutex_unlock(&kvm_lock); |
c8076604 GH |
7124 | |
7125 | if (freq->old < freq->new && send_ipi) { | |
7126 | /* | |
7127 | * We upscale the frequency. Must make the guest | |
7128 | * doesn't see old kvmclock values while running with | |
7129 | * the new frequency, otherwise we risk the guest sees | |
7130 | * time go backwards. | |
7131 | * | |
7132 | * In case we update the frequency for another cpu | |
7133 | * (which might be in guest context) send an interrupt | |
7134 | * to kick the cpu out of guest context. Next time | |
7135 | * guest context is entered kvmclock will be updated, | |
7136 | * so the guest will not see stale values. | |
7137 | */ | |
df24014a | 7138 | smp_call_function_single(cpu, tsc_khz_changed, freq, 1); |
c8076604 | 7139 | } |
df24014a VK |
7140 | } |
7141 | ||
7142 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, | |
7143 | void *data) | |
7144 | { | |
7145 | struct cpufreq_freqs *freq = data; | |
7146 | int cpu; | |
7147 | ||
7148 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) | |
7149 | return 0; | |
7150 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
7151 | return 0; | |
7152 | ||
7153 | for_each_cpu(cpu, freq->policy->cpus) | |
7154 | __kvmclock_cpufreq_notifier(freq, cpu); | |
7155 | ||
c8076604 GH |
7156 | return 0; |
7157 | } | |
7158 | ||
7159 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
8cfdc000 ZA |
7160 | .notifier_call = kvmclock_cpufreq_notifier |
7161 | }; | |
7162 | ||
251a5fd6 | 7163 | static int kvmclock_cpu_online(unsigned int cpu) |
8cfdc000 | 7164 | { |
251a5fd6 SAS |
7165 | tsc_khz_changed(NULL); |
7166 | return 0; | |
8cfdc000 ZA |
7167 | } |
7168 | ||
b820cc0c ZA |
7169 | static void kvm_timer_init(void) |
7170 | { | |
c285545f | 7171 | max_tsc_khz = tsc_khz; |
460dd42e | 7172 | |
b820cc0c | 7173 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
c285545f ZA |
7174 | #ifdef CONFIG_CPU_FREQ |
7175 | struct cpufreq_policy policy; | |
758f588d BP |
7176 | int cpu; |
7177 | ||
c285545f | 7178 | memset(&policy, 0, sizeof(policy)); |
3e26f230 AK |
7179 | cpu = get_cpu(); |
7180 | cpufreq_get_policy(&policy, cpu); | |
c285545f ZA |
7181 | if (policy.cpuinfo.max_freq) |
7182 | max_tsc_khz = policy.cpuinfo.max_freq; | |
3e26f230 | 7183 | put_cpu(); |
c285545f | 7184 | #endif |
b820cc0c ZA |
7185 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
7186 | CPUFREQ_TRANSITION_NOTIFIER); | |
7187 | } | |
460dd42e | 7188 | |
73c1b41e | 7189 | cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", |
251a5fd6 | 7190 | kvmclock_cpu_online, kvmclock_cpu_down_prep); |
b820cc0c ZA |
7191 | } |
7192 | ||
dd60d217 AK |
7193 | DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); |
7194 | EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu); | |
ff9d07a0 | 7195 | |
f5132b01 | 7196 | int kvm_is_in_guest(void) |
ff9d07a0 | 7197 | { |
086c9855 | 7198 | return __this_cpu_read(current_vcpu) != NULL; |
ff9d07a0 ZY |
7199 | } |
7200 | ||
7201 | static int kvm_is_user_mode(void) | |
7202 | { | |
7203 | int user_mode = 3; | |
dcf46b94 | 7204 | |
086c9855 AS |
7205 | if (__this_cpu_read(current_vcpu)) |
7206 | user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 7207 | |
ff9d07a0 ZY |
7208 | return user_mode != 0; |
7209 | } | |
7210 | ||
7211 | static unsigned long kvm_get_guest_ip(void) | |
7212 | { | |
7213 | unsigned long ip = 0; | |
dcf46b94 | 7214 | |
086c9855 AS |
7215 | if (__this_cpu_read(current_vcpu)) |
7216 | ip = kvm_rip_read(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 7217 | |
ff9d07a0 ZY |
7218 | return ip; |
7219 | } | |
7220 | ||
8479e04e LK |
7221 | static void kvm_handle_intel_pt_intr(void) |
7222 | { | |
7223 | struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu); | |
7224 | ||
7225 | kvm_make_request(KVM_REQ_PMI, vcpu); | |
7226 | __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT, | |
7227 | (unsigned long *)&vcpu->arch.pmu.global_status); | |
7228 | } | |
7229 | ||
ff9d07a0 ZY |
7230 | static struct perf_guest_info_callbacks kvm_guest_cbs = { |
7231 | .is_in_guest = kvm_is_in_guest, | |
7232 | .is_user_mode = kvm_is_user_mode, | |
7233 | .get_guest_ip = kvm_get_guest_ip, | |
8479e04e | 7234 | .handle_intel_pt_intr = kvm_handle_intel_pt_intr, |
ff9d07a0 ZY |
7235 | }; |
7236 | ||
16e8d74d MT |
7237 | #ifdef CONFIG_X86_64 |
7238 | static void pvclock_gtod_update_fn(struct work_struct *work) | |
7239 | { | |
d828199e MT |
7240 | struct kvm *kvm; |
7241 | ||
7242 | struct kvm_vcpu *vcpu; | |
7243 | int i; | |
7244 | ||
0d9ce162 | 7245 | mutex_lock(&kvm_lock); |
d828199e MT |
7246 | list_for_each_entry(kvm, &vm_list, vm_list) |
7247 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 7248 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
d828199e | 7249 | atomic_set(&kvm_guest_has_master_clock, 0); |
0d9ce162 | 7250 | mutex_unlock(&kvm_lock); |
16e8d74d MT |
7251 | } |
7252 | ||
7253 | static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); | |
7254 | ||
7255 | /* | |
7256 | * Notification about pvclock gtod data update. | |
7257 | */ | |
7258 | static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, | |
7259 | void *priv) | |
7260 | { | |
7261 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
7262 | struct timekeeper *tk = priv; | |
7263 | ||
7264 | update_pvclock_gtod(tk); | |
7265 | ||
7266 | /* disable master clock if host does not trust, or does not | |
b0c39dc6 | 7267 | * use, TSC based clocksource. |
16e8d74d | 7268 | */ |
b0c39dc6 | 7269 | if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && |
16e8d74d MT |
7270 | atomic_read(&kvm_guest_has_master_clock) != 0) |
7271 | queue_work(system_long_wq, &pvclock_gtod_work); | |
7272 | ||
7273 | return 0; | |
7274 | } | |
7275 | ||
7276 | static struct notifier_block pvclock_gtod_notifier = { | |
7277 | .notifier_call = pvclock_gtod_notify, | |
7278 | }; | |
7279 | #endif | |
7280 | ||
f8c16bba | 7281 | int kvm_arch_init(void *opaque) |
043405e1 | 7282 | { |
b820cc0c | 7283 | int r; |
6b61edf7 | 7284 | struct kvm_x86_ops *ops = opaque; |
f8c16bba | 7285 | |
f8c16bba ZX |
7286 | if (kvm_x86_ops) { |
7287 | printk(KERN_ERR "kvm: already loaded the other module\n"); | |
56c6d28a ZX |
7288 | r = -EEXIST; |
7289 | goto out; | |
f8c16bba ZX |
7290 | } |
7291 | ||
7292 | if (!ops->cpu_has_kvm_support()) { | |
7293 | printk(KERN_ERR "kvm: no hardware support\n"); | |
56c6d28a ZX |
7294 | r = -EOPNOTSUPP; |
7295 | goto out; | |
f8c16bba ZX |
7296 | } |
7297 | if (ops->disabled_by_bios()) { | |
7298 | printk(KERN_ERR "kvm: disabled by bios\n"); | |
56c6d28a ZX |
7299 | r = -EOPNOTSUPP; |
7300 | goto out; | |
f8c16bba ZX |
7301 | } |
7302 | ||
b666a4b6 MO |
7303 | /* |
7304 | * KVM explicitly assumes that the guest has an FPU and | |
7305 | * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the | |
7306 | * vCPU's FPU state as a fxregs_state struct. | |
7307 | */ | |
7308 | if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { | |
7309 | printk(KERN_ERR "kvm: inadequate fpu\n"); | |
7310 | r = -EOPNOTSUPP; | |
7311 | goto out; | |
7312 | } | |
7313 | ||
013f6a5d | 7314 | r = -ENOMEM; |
ed8e4812 | 7315 | x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu), |
b666a4b6 MO |
7316 | __alignof__(struct fpu), SLAB_ACCOUNT, |
7317 | NULL); | |
7318 | if (!x86_fpu_cache) { | |
7319 | printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n"); | |
7320 | goto out; | |
7321 | } | |
7322 | ||
013f6a5d MT |
7323 | shared_msrs = alloc_percpu(struct kvm_shared_msrs); |
7324 | if (!shared_msrs) { | |
7325 | printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); | |
b666a4b6 | 7326 | goto out_free_x86_fpu_cache; |
013f6a5d MT |
7327 | } |
7328 | ||
97db56ce AK |
7329 | r = kvm_mmu_module_init(); |
7330 | if (r) | |
013f6a5d | 7331 | goto out_free_percpu; |
97db56ce | 7332 | |
f8c16bba | 7333 | kvm_x86_ops = ops; |
920c8377 | 7334 | |
7b52345e | 7335 | kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, |
ffb128c8 | 7336 | PT_DIRTY_MASK, PT64_NX_MASK, 0, |
d0ec49d4 | 7337 | PT_PRESENT_MASK, 0, sme_me_mask); |
b820cc0c | 7338 | kvm_timer_init(); |
c8076604 | 7339 | |
ff9d07a0 ZY |
7340 | perf_register_guest_info_callbacks(&kvm_guest_cbs); |
7341 | ||
d366bf7e | 7342 | if (boot_cpu_has(X86_FEATURE_XSAVE)) |
2acf923e DC |
7343 | host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); |
7344 | ||
c5cc421b | 7345 | kvm_lapic_init(); |
0c5f81da WL |
7346 | if (pi_inject_timer == -1) |
7347 | pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER); | |
16e8d74d MT |
7348 | #ifdef CONFIG_X86_64 |
7349 | pvclock_gtod_register_notifier(&pvclock_gtod_notifier); | |
0092e434 | 7350 | |
5fa4ec9c | 7351 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 | 7352 | set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); |
16e8d74d MT |
7353 | #endif |
7354 | ||
f8c16bba | 7355 | return 0; |
56c6d28a | 7356 | |
013f6a5d MT |
7357 | out_free_percpu: |
7358 | free_percpu(shared_msrs); | |
b666a4b6 MO |
7359 | out_free_x86_fpu_cache: |
7360 | kmem_cache_destroy(x86_fpu_cache); | |
56c6d28a | 7361 | out: |
56c6d28a | 7362 | return r; |
043405e1 | 7363 | } |
8776e519 | 7364 | |
f8c16bba ZX |
7365 | void kvm_arch_exit(void) |
7366 | { | |
0092e434 | 7367 | #ifdef CONFIG_X86_64 |
5fa4ec9c | 7368 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 VK |
7369 | clear_hv_tscchange_cb(); |
7370 | #endif | |
cef84c30 | 7371 | kvm_lapic_exit(); |
ff9d07a0 ZY |
7372 | perf_unregister_guest_info_callbacks(&kvm_guest_cbs); |
7373 | ||
888d256e JK |
7374 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
7375 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
7376 | CPUFREQ_TRANSITION_NOTIFIER); | |
251a5fd6 | 7377 | cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); |
16e8d74d MT |
7378 | #ifdef CONFIG_X86_64 |
7379 | pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); | |
7380 | #endif | |
f8c16bba | 7381 | kvm_x86_ops = NULL; |
56c6d28a | 7382 | kvm_mmu_module_exit(); |
013f6a5d | 7383 | free_percpu(shared_msrs); |
b666a4b6 | 7384 | kmem_cache_destroy(x86_fpu_cache); |
56c6d28a | 7385 | } |
f8c16bba | 7386 | |
5cb56059 | 7387 | int kvm_vcpu_halt(struct kvm_vcpu *vcpu) |
8776e519 HB |
7388 | { |
7389 | ++vcpu->stat.halt_exits; | |
35754c98 | 7390 | if (lapic_in_kernel(vcpu)) { |
a4535290 | 7391 | vcpu->arch.mp_state = KVM_MP_STATE_HALTED; |
8776e519 HB |
7392 | return 1; |
7393 | } else { | |
7394 | vcpu->run->exit_reason = KVM_EXIT_HLT; | |
7395 | return 0; | |
7396 | } | |
7397 | } | |
5cb56059 JS |
7398 | EXPORT_SYMBOL_GPL(kvm_vcpu_halt); |
7399 | ||
7400 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) | |
7401 | { | |
6affcbed KH |
7402 | int ret = kvm_skip_emulated_instruction(vcpu); |
7403 | /* | |
7404 | * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered | |
7405 | * KVM_EXIT_DEBUG here. | |
7406 | */ | |
7407 | return kvm_vcpu_halt(vcpu) && ret; | |
5cb56059 | 7408 | } |
8776e519 HB |
7409 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); |
7410 | ||
8ef81a9a | 7411 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
7412 | static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, |
7413 | unsigned long clock_type) | |
7414 | { | |
7415 | struct kvm_clock_pairing clock_pairing; | |
899a31f5 | 7416 | struct timespec64 ts; |
80fbd89c | 7417 | u64 cycle; |
55dd00a7 MT |
7418 | int ret; |
7419 | ||
7420 | if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) | |
7421 | return -KVM_EOPNOTSUPP; | |
7422 | ||
7423 | if (kvm_get_walltime_and_clockread(&ts, &cycle) == false) | |
7424 | return -KVM_EOPNOTSUPP; | |
7425 | ||
7426 | clock_pairing.sec = ts.tv_sec; | |
7427 | clock_pairing.nsec = ts.tv_nsec; | |
7428 | clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); | |
7429 | clock_pairing.flags = 0; | |
bcbfbd8e | 7430 | memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); |
55dd00a7 MT |
7431 | |
7432 | ret = 0; | |
7433 | if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, | |
7434 | sizeof(struct kvm_clock_pairing))) | |
7435 | ret = -KVM_EFAULT; | |
7436 | ||
7437 | return ret; | |
7438 | } | |
8ef81a9a | 7439 | #endif |
55dd00a7 | 7440 | |
6aef266c SV |
7441 | /* |
7442 | * kvm_pv_kick_cpu_op: Kick a vcpu. | |
7443 | * | |
7444 | * @apicid - apicid of vcpu to be kicked. | |
7445 | */ | |
7446 | static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) | |
7447 | { | |
24d2166b | 7448 | struct kvm_lapic_irq lapic_irq; |
6aef266c | 7449 | |
150a84fe | 7450 | lapic_irq.shorthand = APIC_DEST_NOSHORT; |
c96001c5 | 7451 | lapic_irq.dest_mode = APIC_DEST_PHYSICAL; |
ebd28fcb | 7452 | lapic_irq.level = 0; |
24d2166b | 7453 | lapic_irq.dest_id = apicid; |
93bbf0b8 | 7454 | lapic_irq.msi_redir_hint = false; |
6aef266c | 7455 | |
24d2166b | 7456 | lapic_irq.delivery_mode = APIC_DM_REMRD; |
795a149e | 7457 | kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); |
6aef266c SV |
7458 | } |
7459 | ||
d62caabb AS |
7460 | void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu) |
7461 | { | |
f7589cca PB |
7462 | if (!lapic_in_kernel(vcpu)) { |
7463 | WARN_ON_ONCE(vcpu->arch.apicv_active); | |
7464 | return; | |
7465 | } | |
7466 | if (!vcpu->arch.apicv_active) | |
7467 | return; | |
7468 | ||
d62caabb AS |
7469 | vcpu->arch.apicv_active = false; |
7470 | kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu); | |
7471 | } | |
7472 | ||
4e19c36f SS |
7473 | bool kvm_apicv_activated(struct kvm *kvm) |
7474 | { | |
7475 | return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0); | |
7476 | } | |
7477 | EXPORT_SYMBOL_GPL(kvm_apicv_activated); | |
7478 | ||
7479 | void kvm_apicv_init(struct kvm *kvm, bool enable) | |
7480 | { | |
7481 | if (enable) | |
7482 | clear_bit(APICV_INHIBIT_REASON_DISABLE, | |
7483 | &kvm->arch.apicv_inhibit_reasons); | |
7484 | else | |
7485 | set_bit(APICV_INHIBIT_REASON_DISABLE, | |
7486 | &kvm->arch.apicv_inhibit_reasons); | |
7487 | } | |
7488 | EXPORT_SYMBOL_GPL(kvm_apicv_init); | |
7489 | ||
71506297 WL |
7490 | static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id) |
7491 | { | |
7492 | struct kvm_vcpu *target = NULL; | |
7493 | struct kvm_apic_map *map; | |
7494 | ||
7495 | rcu_read_lock(); | |
7496 | map = rcu_dereference(kvm->arch.apic_map); | |
7497 | ||
7498 | if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) | |
7499 | target = map->phys_map[dest_id]->vcpu; | |
7500 | ||
7501 | rcu_read_unlock(); | |
7502 | ||
266e85a5 | 7503 | if (target && READ_ONCE(target->ready)) |
71506297 WL |
7504 | kvm_vcpu_yield_to(target); |
7505 | } | |
7506 | ||
8776e519 HB |
7507 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
7508 | { | |
7509 | unsigned long nr, a0, a1, a2, a3, ret; | |
6356ee0c | 7510 | int op_64_bit; |
8776e519 | 7511 | |
696ca779 RK |
7512 | if (kvm_hv_hypercall_enabled(vcpu->kvm)) |
7513 | return kvm_hv_hypercall(vcpu); | |
55cd8e5a | 7514 | |
de3cd117 SC |
7515 | nr = kvm_rax_read(vcpu); |
7516 | a0 = kvm_rbx_read(vcpu); | |
7517 | a1 = kvm_rcx_read(vcpu); | |
7518 | a2 = kvm_rdx_read(vcpu); | |
7519 | a3 = kvm_rsi_read(vcpu); | |
8776e519 | 7520 | |
229456fc | 7521 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 7522 | |
a449c7aa NA |
7523 | op_64_bit = is_64_bit_mode(vcpu); |
7524 | if (!op_64_bit) { | |
8776e519 HB |
7525 | nr &= 0xFFFFFFFF; |
7526 | a0 &= 0xFFFFFFFF; | |
7527 | a1 &= 0xFFFFFFFF; | |
7528 | a2 &= 0xFFFFFFFF; | |
7529 | a3 &= 0xFFFFFFFF; | |
7530 | } | |
7531 | ||
07708c4a JK |
7532 | if (kvm_x86_ops->get_cpl(vcpu) != 0) { |
7533 | ret = -KVM_EPERM; | |
696ca779 | 7534 | goto out; |
07708c4a JK |
7535 | } |
7536 | ||
8776e519 | 7537 | switch (nr) { |
b93463aa AK |
7538 | case KVM_HC_VAPIC_POLL_IRQ: |
7539 | ret = 0; | |
7540 | break; | |
6aef266c SV |
7541 | case KVM_HC_KICK_CPU: |
7542 | kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); | |
266e85a5 | 7543 | kvm_sched_yield(vcpu->kvm, a1); |
6aef266c SV |
7544 | ret = 0; |
7545 | break; | |
8ef81a9a | 7546 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
7547 | case KVM_HC_CLOCK_PAIRING: |
7548 | ret = kvm_pv_clock_pairing(vcpu, a0, a1); | |
7549 | break; | |
1ed199a4 | 7550 | #endif |
4180bf1b WL |
7551 | case KVM_HC_SEND_IPI: |
7552 | ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); | |
7553 | break; | |
71506297 WL |
7554 | case KVM_HC_SCHED_YIELD: |
7555 | kvm_sched_yield(vcpu->kvm, a0); | |
7556 | ret = 0; | |
7557 | break; | |
8776e519 HB |
7558 | default: |
7559 | ret = -KVM_ENOSYS; | |
7560 | break; | |
7561 | } | |
696ca779 | 7562 | out: |
a449c7aa NA |
7563 | if (!op_64_bit) |
7564 | ret = (u32)ret; | |
de3cd117 | 7565 | kvm_rax_write(vcpu, ret); |
6356ee0c | 7566 | |
f11c3a8d | 7567 | ++vcpu->stat.hypercalls; |
6356ee0c | 7568 | return kvm_skip_emulated_instruction(vcpu); |
8776e519 HB |
7569 | } |
7570 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
7571 | ||
b6785def | 7572 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) |
8776e519 | 7573 | { |
d6aa1000 | 7574 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
8776e519 | 7575 | char instruction[3]; |
5fdbf976 | 7576 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 7577 | |
8776e519 | 7578 | kvm_x86_ops->patch_hypercall(vcpu, instruction); |
8776e519 | 7579 | |
ce2e852e DV |
7580 | return emulator_write_emulated(ctxt, rip, instruction, 3, |
7581 | &ctxt->exception); | |
8776e519 HB |
7582 | } |
7583 | ||
851ba692 | 7584 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 7585 | { |
782d422b MG |
7586 | return vcpu->run->request_interrupt_window && |
7587 | likely(!pic_in_kernel(vcpu->kvm)); | |
b6c7a5dc HB |
7588 | } |
7589 | ||
851ba692 | 7590 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 7591 | { |
851ba692 AK |
7592 | struct kvm_run *kvm_run = vcpu->run; |
7593 | ||
91586a3b | 7594 | kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; |
f077825a | 7595 | kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0; |
2d3ad1f4 | 7596 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 7597 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
127a457a MG |
7598 | kvm_run->ready_for_interrupt_injection = |
7599 | pic_in_kernel(vcpu->kvm) || | |
782d422b | 7600 | kvm_vcpu_ready_for_interrupt_injection(vcpu); |
b6c7a5dc HB |
7601 | } |
7602 | ||
95ba8273 GN |
7603 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
7604 | { | |
7605 | int max_irr, tpr; | |
7606 | ||
7607 | if (!kvm_x86_ops->update_cr8_intercept) | |
7608 | return; | |
7609 | ||
bce87cce | 7610 | if (!lapic_in_kernel(vcpu)) |
88c808fd AK |
7611 | return; |
7612 | ||
d62caabb AS |
7613 | if (vcpu->arch.apicv_active) |
7614 | return; | |
7615 | ||
8db3baa2 GN |
7616 | if (!vcpu->arch.apic->vapic_addr) |
7617 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
7618 | else | |
7619 | max_irr = -1; | |
95ba8273 GN |
7620 | |
7621 | if (max_irr != -1) | |
7622 | max_irr >>= 4; | |
7623 | ||
7624 | tpr = kvm_lapic_get_cr8(vcpu); | |
7625 | ||
7626 | kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); | |
7627 | } | |
7628 | ||
b6b8a145 | 7629 | static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) |
95ba8273 | 7630 | { |
b6b8a145 JK |
7631 | int r; |
7632 | ||
95ba8273 | 7633 | /* try to reinject previous events if any */ |
664f8e26 | 7634 | |
1a680e35 LA |
7635 | if (vcpu->arch.exception.injected) |
7636 | kvm_x86_ops->queue_exception(vcpu); | |
664f8e26 | 7637 | /* |
a042c26f LA |
7638 | * Do not inject an NMI or interrupt if there is a pending |
7639 | * exception. Exceptions and interrupts are recognized at | |
7640 | * instruction boundaries, i.e. the start of an instruction. | |
7641 | * Trap-like exceptions, e.g. #DB, have higher priority than | |
7642 | * NMIs and interrupts, i.e. traps are recognized before an | |
7643 | * NMI/interrupt that's pending on the same instruction. | |
7644 | * Fault-like exceptions, e.g. #GP and #PF, are the lowest | |
7645 | * priority, but are only generated (pended) during instruction | |
7646 | * execution, i.e. a pending fault-like exception means the | |
7647 | * fault occurred on the *previous* instruction and must be | |
7648 | * serviced prior to recognizing any new events in order to | |
7649 | * fully complete the previous instruction. | |
664f8e26 | 7650 | */ |
1a680e35 LA |
7651 | else if (!vcpu->arch.exception.pending) { |
7652 | if (vcpu->arch.nmi_injected) | |
664f8e26 | 7653 | kvm_x86_ops->set_nmi(vcpu); |
1a680e35 | 7654 | else if (vcpu->arch.interrupt.injected) |
664f8e26 | 7655 | kvm_x86_ops->set_irq(vcpu); |
664f8e26 WL |
7656 | } |
7657 | ||
1a680e35 LA |
7658 | /* |
7659 | * Call check_nested_events() even if we reinjected a previous event | |
7660 | * in order for caller to determine if it should require immediate-exit | |
7661 | * from L2 to L1 due to pending L1 events which require exit | |
7662 | * from L2 to L1. | |
7663 | */ | |
664f8e26 WL |
7664 | if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { |
7665 | r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); | |
7666 | if (r != 0) | |
7667 | return r; | |
7668 | } | |
7669 | ||
7670 | /* try to inject new event if pending */ | |
b59bb7bd | 7671 | if (vcpu->arch.exception.pending) { |
5c1c85d0 AK |
7672 | trace_kvm_inj_exception(vcpu->arch.exception.nr, |
7673 | vcpu->arch.exception.has_error_code, | |
7674 | vcpu->arch.exception.error_code); | |
d6e8c854 | 7675 | |
1a680e35 | 7676 | WARN_ON_ONCE(vcpu->arch.exception.injected); |
664f8e26 WL |
7677 | vcpu->arch.exception.pending = false; |
7678 | vcpu->arch.exception.injected = true; | |
7679 | ||
d6e8c854 NA |
7680 | if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) |
7681 | __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | | |
7682 | X86_EFLAGS_RF); | |
7683 | ||
f10c729f JM |
7684 | if (vcpu->arch.exception.nr == DB_VECTOR) { |
7685 | /* | |
7686 | * This code assumes that nSVM doesn't use | |
7687 | * check_nested_events(). If it does, the | |
7688 | * DR6/DR7 changes should happen before L1 | |
7689 | * gets a #VMEXIT for an intercepted #DB in | |
7690 | * L2. (Under VMX, on the other hand, the | |
7691 | * DR6/DR7 changes should not happen in the | |
7692 | * event of a VM-exit to L1 for an intercepted | |
7693 | * #DB in L2.) | |
7694 | */ | |
7695 | kvm_deliver_exception_payload(vcpu); | |
7696 | if (vcpu->arch.dr7 & DR7_GD) { | |
7697 | vcpu->arch.dr7 &= ~DR7_GD; | |
7698 | kvm_update_dr7(vcpu); | |
7699 | } | |
6bdf0662 NA |
7700 | } |
7701 | ||
cfcd20e5 | 7702 | kvm_x86_ops->queue_exception(vcpu); |
1a680e35 LA |
7703 | } |
7704 | ||
7705 | /* Don't consider new event if we re-injected an event */ | |
7706 | if (kvm_event_needs_reinjection(vcpu)) | |
7707 | return 0; | |
7708 | ||
7709 | if (vcpu->arch.smi_pending && !is_smm(vcpu) && | |
7710 | kvm_x86_ops->smi_allowed(vcpu)) { | |
c43203ca | 7711 | vcpu->arch.smi_pending = false; |
52797bf9 | 7712 | ++vcpu->arch.smi_count; |
ee2cd4b7 | 7713 | enter_smm(vcpu); |
c43203ca | 7714 | } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) { |
321c5658 YS |
7715 | --vcpu->arch.nmi_pending; |
7716 | vcpu->arch.nmi_injected = true; | |
7717 | kvm_x86_ops->set_nmi(vcpu); | |
c7c9c56c | 7718 | } else if (kvm_cpu_has_injectable_intr(vcpu)) { |
9242b5b6 BD |
7719 | /* |
7720 | * Because interrupts can be injected asynchronously, we are | |
7721 | * calling check_nested_events again here to avoid a race condition. | |
7722 | * See https://lkml.org/lkml/2014/7/2/60 for discussion about this | |
7723 | * proposal and current concerns. Perhaps we should be setting | |
7724 | * KVM_REQ_EVENT only on certain events and not unconditionally? | |
7725 | */ | |
7726 | if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { | |
7727 | r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); | |
7728 | if (r != 0) | |
7729 | return r; | |
7730 | } | |
95ba8273 | 7731 | if (kvm_x86_ops->interrupt_allowed(vcpu)) { |
66fd3f7f GN |
7732 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), |
7733 | false); | |
7734 | kvm_x86_ops->set_irq(vcpu); | |
95ba8273 GN |
7735 | } |
7736 | } | |
ee2cd4b7 | 7737 | |
b6b8a145 | 7738 | return 0; |
95ba8273 GN |
7739 | } |
7740 | ||
7460fb4a AK |
7741 | static void process_nmi(struct kvm_vcpu *vcpu) |
7742 | { | |
7743 | unsigned limit = 2; | |
7744 | ||
7745 | /* | |
7746 | * x86 is limited to one NMI running, and one NMI pending after it. | |
7747 | * If an NMI is already in progress, limit further NMIs to just one. | |
7748 | * Otherwise, allow two (and we'll inject the first one immediately). | |
7749 | */ | |
7750 | if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) | |
7751 | limit = 1; | |
7752 | ||
7753 | vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); | |
7754 | vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); | |
7755 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7756 | } | |
7757 | ||
ee2cd4b7 | 7758 | static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) |
660a5d51 PB |
7759 | { |
7760 | u32 flags = 0; | |
7761 | flags |= seg->g << 23; | |
7762 | flags |= seg->db << 22; | |
7763 | flags |= seg->l << 21; | |
7764 | flags |= seg->avl << 20; | |
7765 | flags |= seg->present << 15; | |
7766 | flags |= seg->dpl << 13; | |
7767 | flags |= seg->s << 12; | |
7768 | flags |= seg->type << 8; | |
7769 | return flags; | |
7770 | } | |
7771 | ||
ee2cd4b7 | 7772 | static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) |
660a5d51 PB |
7773 | { |
7774 | struct kvm_segment seg; | |
7775 | int offset; | |
7776 | ||
7777 | kvm_get_segment(vcpu, &seg, n); | |
7778 | put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); | |
7779 | ||
7780 | if (n < 3) | |
7781 | offset = 0x7f84 + n * 12; | |
7782 | else | |
7783 | offset = 0x7f2c + (n - 3) * 12; | |
7784 | ||
7785 | put_smstate(u32, buf, offset + 8, seg.base); | |
7786 | put_smstate(u32, buf, offset + 4, seg.limit); | |
ee2cd4b7 | 7787 | put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
7788 | } |
7789 | ||
efbb288a | 7790 | #ifdef CONFIG_X86_64 |
ee2cd4b7 | 7791 | static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) |
660a5d51 PB |
7792 | { |
7793 | struct kvm_segment seg; | |
7794 | int offset; | |
7795 | u16 flags; | |
7796 | ||
7797 | kvm_get_segment(vcpu, &seg, n); | |
7798 | offset = 0x7e00 + n * 16; | |
7799 | ||
ee2cd4b7 | 7800 | flags = enter_smm_get_segment_flags(&seg) >> 8; |
660a5d51 PB |
7801 | put_smstate(u16, buf, offset, seg.selector); |
7802 | put_smstate(u16, buf, offset + 2, flags); | |
7803 | put_smstate(u32, buf, offset + 4, seg.limit); | |
7804 | put_smstate(u64, buf, offset + 8, seg.base); | |
7805 | } | |
efbb288a | 7806 | #endif |
660a5d51 | 7807 | |
ee2cd4b7 | 7808 | static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) |
660a5d51 PB |
7809 | { |
7810 | struct desc_ptr dt; | |
7811 | struct kvm_segment seg; | |
7812 | unsigned long val; | |
7813 | int i; | |
7814 | ||
7815 | put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); | |
7816 | put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); | |
7817 | put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); | |
7818 | put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); | |
7819 | ||
7820 | for (i = 0; i < 8; i++) | |
7821 | put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); | |
7822 | ||
7823 | kvm_get_dr(vcpu, 6, &val); | |
7824 | put_smstate(u32, buf, 0x7fcc, (u32)val); | |
7825 | kvm_get_dr(vcpu, 7, &val); | |
7826 | put_smstate(u32, buf, 0x7fc8, (u32)val); | |
7827 | ||
7828 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
7829 | put_smstate(u32, buf, 0x7fc4, seg.selector); | |
7830 | put_smstate(u32, buf, 0x7f64, seg.base); | |
7831 | put_smstate(u32, buf, 0x7f60, seg.limit); | |
ee2cd4b7 | 7832 | put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
7833 | |
7834 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
7835 | put_smstate(u32, buf, 0x7fc0, seg.selector); | |
7836 | put_smstate(u32, buf, 0x7f80, seg.base); | |
7837 | put_smstate(u32, buf, 0x7f7c, seg.limit); | |
ee2cd4b7 | 7838 | put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
7839 | |
7840 | kvm_x86_ops->get_gdt(vcpu, &dt); | |
7841 | put_smstate(u32, buf, 0x7f74, dt.address); | |
7842 | put_smstate(u32, buf, 0x7f70, dt.size); | |
7843 | ||
7844 | kvm_x86_ops->get_idt(vcpu, &dt); | |
7845 | put_smstate(u32, buf, 0x7f58, dt.address); | |
7846 | put_smstate(u32, buf, 0x7f54, dt.size); | |
7847 | ||
7848 | for (i = 0; i < 6; i++) | |
ee2cd4b7 | 7849 | enter_smm_save_seg_32(vcpu, buf, i); |
660a5d51 PB |
7850 | |
7851 | put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); | |
7852 | ||
7853 | /* revision id */ | |
7854 | put_smstate(u32, buf, 0x7efc, 0x00020000); | |
7855 | put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); | |
7856 | } | |
7857 | ||
b68f3cc7 | 7858 | #ifdef CONFIG_X86_64 |
ee2cd4b7 | 7859 | static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) |
660a5d51 | 7860 | { |
660a5d51 PB |
7861 | struct desc_ptr dt; |
7862 | struct kvm_segment seg; | |
7863 | unsigned long val; | |
7864 | int i; | |
7865 | ||
7866 | for (i = 0; i < 16; i++) | |
7867 | put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); | |
7868 | ||
7869 | put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); | |
7870 | put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); | |
7871 | ||
7872 | kvm_get_dr(vcpu, 6, &val); | |
7873 | put_smstate(u64, buf, 0x7f68, val); | |
7874 | kvm_get_dr(vcpu, 7, &val); | |
7875 | put_smstate(u64, buf, 0x7f60, val); | |
7876 | ||
7877 | put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); | |
7878 | put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); | |
7879 | put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); | |
7880 | ||
7881 | put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); | |
7882 | ||
7883 | /* revision id */ | |
7884 | put_smstate(u32, buf, 0x7efc, 0x00020064); | |
7885 | ||
7886 | put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); | |
7887 | ||
7888 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
7889 | put_smstate(u16, buf, 0x7e90, seg.selector); | |
ee2cd4b7 | 7890 | put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); |
660a5d51 PB |
7891 | put_smstate(u32, buf, 0x7e94, seg.limit); |
7892 | put_smstate(u64, buf, 0x7e98, seg.base); | |
7893 | ||
7894 | kvm_x86_ops->get_idt(vcpu, &dt); | |
7895 | put_smstate(u32, buf, 0x7e84, dt.size); | |
7896 | put_smstate(u64, buf, 0x7e88, dt.address); | |
7897 | ||
7898 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
7899 | put_smstate(u16, buf, 0x7e70, seg.selector); | |
ee2cd4b7 | 7900 | put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); |
660a5d51 PB |
7901 | put_smstate(u32, buf, 0x7e74, seg.limit); |
7902 | put_smstate(u64, buf, 0x7e78, seg.base); | |
7903 | ||
7904 | kvm_x86_ops->get_gdt(vcpu, &dt); | |
7905 | put_smstate(u32, buf, 0x7e64, dt.size); | |
7906 | put_smstate(u64, buf, 0x7e68, dt.address); | |
7907 | ||
7908 | for (i = 0; i < 6; i++) | |
ee2cd4b7 | 7909 | enter_smm_save_seg_64(vcpu, buf, i); |
660a5d51 | 7910 | } |
b68f3cc7 | 7911 | #endif |
660a5d51 | 7912 | |
ee2cd4b7 | 7913 | static void enter_smm(struct kvm_vcpu *vcpu) |
64d60670 | 7914 | { |
660a5d51 | 7915 | struct kvm_segment cs, ds; |
18c3626e | 7916 | struct desc_ptr dt; |
660a5d51 PB |
7917 | char buf[512]; |
7918 | u32 cr0; | |
7919 | ||
660a5d51 | 7920 | trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); |
660a5d51 | 7921 | memset(buf, 0, 512); |
b68f3cc7 | 7922 | #ifdef CONFIG_X86_64 |
d6321d49 | 7923 | if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) |
ee2cd4b7 | 7924 | enter_smm_save_state_64(vcpu, buf); |
660a5d51 | 7925 | else |
b68f3cc7 | 7926 | #endif |
ee2cd4b7 | 7927 | enter_smm_save_state_32(vcpu, buf); |
660a5d51 | 7928 | |
0234bf88 LP |
7929 | /* |
7930 | * Give pre_enter_smm() a chance to make ISA-specific changes to the | |
7931 | * vCPU state (e.g. leave guest mode) after we've saved the state into | |
7932 | * the SMM state-save area. | |
7933 | */ | |
7934 | kvm_x86_ops->pre_enter_smm(vcpu, buf); | |
7935 | ||
7936 | vcpu->arch.hflags |= HF_SMM_MASK; | |
54bf36aa | 7937 | kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); |
660a5d51 PB |
7938 | |
7939 | if (kvm_x86_ops->get_nmi_mask(vcpu)) | |
7940 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; | |
7941 | else | |
7942 | kvm_x86_ops->set_nmi_mask(vcpu, true); | |
7943 | ||
7944 | kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); | |
7945 | kvm_rip_write(vcpu, 0x8000); | |
7946 | ||
7947 | cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); | |
7948 | kvm_x86_ops->set_cr0(vcpu, cr0); | |
7949 | vcpu->arch.cr0 = cr0; | |
7950 | ||
7951 | kvm_x86_ops->set_cr4(vcpu, 0); | |
7952 | ||
18c3626e PB |
7953 | /* Undocumented: IDT limit is set to zero on entry to SMM. */ |
7954 | dt.address = dt.size = 0; | |
7955 | kvm_x86_ops->set_idt(vcpu, &dt); | |
7956 | ||
660a5d51 PB |
7957 | __kvm_set_dr(vcpu, 7, DR7_FIXED_1); |
7958 | ||
7959 | cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; | |
7960 | cs.base = vcpu->arch.smbase; | |
7961 | ||
7962 | ds.selector = 0; | |
7963 | ds.base = 0; | |
7964 | ||
7965 | cs.limit = ds.limit = 0xffffffff; | |
7966 | cs.type = ds.type = 0x3; | |
7967 | cs.dpl = ds.dpl = 0; | |
7968 | cs.db = ds.db = 0; | |
7969 | cs.s = ds.s = 1; | |
7970 | cs.l = ds.l = 0; | |
7971 | cs.g = ds.g = 1; | |
7972 | cs.avl = ds.avl = 0; | |
7973 | cs.present = ds.present = 1; | |
7974 | cs.unusable = ds.unusable = 0; | |
7975 | cs.padding = ds.padding = 0; | |
7976 | ||
7977 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
7978 | kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); | |
7979 | kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); | |
7980 | kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); | |
7981 | kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); | |
7982 | kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); | |
7983 | ||
b68f3cc7 | 7984 | #ifdef CONFIG_X86_64 |
d6321d49 | 7985 | if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) |
660a5d51 | 7986 | kvm_x86_ops->set_efer(vcpu, 0); |
b68f3cc7 | 7987 | #endif |
660a5d51 PB |
7988 | |
7989 | kvm_update_cpuid(vcpu); | |
7990 | kvm_mmu_reset_context(vcpu); | |
64d60670 PB |
7991 | } |
7992 | ||
ee2cd4b7 | 7993 | static void process_smi(struct kvm_vcpu *vcpu) |
c43203ca PB |
7994 | { |
7995 | vcpu->arch.smi_pending = true; | |
7996 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7997 | } | |
7998 | ||
7ee30bc1 NNL |
7999 | void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, |
8000 | unsigned long *vcpu_bitmap) | |
8001 | { | |
8002 | cpumask_var_t cpus; | |
7ee30bc1 NNL |
8003 | |
8004 | zalloc_cpumask_var(&cpus, GFP_ATOMIC); | |
8005 | ||
db5a95ec MW |
8006 | kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, |
8007 | vcpu_bitmap, cpus); | |
7ee30bc1 NNL |
8008 | |
8009 | free_cpumask_var(cpus); | |
8010 | } | |
8011 | ||
2860c4b1 PB |
8012 | void kvm_make_scan_ioapic_request(struct kvm *kvm) |
8013 | { | |
8014 | kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); | |
8015 | } | |
8016 | ||
8df14af4 SS |
8017 | void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) |
8018 | { | |
8019 | if (!lapic_in_kernel(vcpu)) | |
8020 | return; | |
8021 | ||
8022 | vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm); | |
8023 | kvm_apic_update_apicv(vcpu); | |
8024 | kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu); | |
8025 | } | |
8026 | EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv); | |
8027 | ||
8028 | /* | |
8029 | * NOTE: Do not hold any lock prior to calling this. | |
8030 | * | |
8031 | * In particular, kvm_request_apicv_update() expects kvm->srcu not to be | |
8032 | * locked, because it calls __x86_set_memory_region() which does | |
8033 | * synchronize_srcu(&kvm->srcu). | |
8034 | */ | |
8035 | void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit) | |
8036 | { | |
ef8efd7a SS |
8037 | if (!kvm_x86_ops->check_apicv_inhibit_reasons || |
8038 | !kvm_x86_ops->check_apicv_inhibit_reasons(bit)) | |
8039 | return; | |
8040 | ||
8df14af4 SS |
8041 | if (activate) { |
8042 | if (!test_and_clear_bit(bit, &kvm->arch.apicv_inhibit_reasons) || | |
8043 | !kvm_apicv_activated(kvm)) | |
8044 | return; | |
8045 | } else { | |
8046 | if (test_and_set_bit(bit, &kvm->arch.apicv_inhibit_reasons) || | |
8047 | kvm_apicv_activated(kvm)) | |
8048 | return; | |
8049 | } | |
8050 | ||
24bbf74c | 8051 | trace_kvm_apicv_update_request(activate, bit); |
8df14af4 SS |
8052 | kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE); |
8053 | } | |
8054 | EXPORT_SYMBOL_GPL(kvm_request_apicv_update); | |
8055 | ||
3d81bc7e | 8056 | static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) |
c7c9c56c | 8057 | { |
dcbd3e49 | 8058 | if (!kvm_apic_present(vcpu)) |
3d81bc7e | 8059 | return; |
c7c9c56c | 8060 | |
6308630b | 8061 | bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); |
c7c9c56c | 8062 | |
b053b2ae | 8063 | if (irqchip_split(vcpu->kvm)) |
6308630b | 8064 | kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); |
db2bdcbb | 8065 | else { |
fa59cc00 | 8066 | if (vcpu->arch.apicv_active) |
d62caabb | 8067 | kvm_x86_ops->sync_pir_to_irr(vcpu); |
e97f852f WL |
8068 | if (ioapic_in_kernel(vcpu->kvm)) |
8069 | kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); | |
db2bdcbb | 8070 | } |
e40ff1d6 LA |
8071 | |
8072 | if (is_guest_mode(vcpu)) | |
8073 | vcpu->arch.load_eoi_exitmap_pending = true; | |
8074 | else | |
8075 | kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); | |
8076 | } | |
8077 | ||
8078 | static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) | |
8079 | { | |
8080 | u64 eoi_exit_bitmap[4]; | |
8081 | ||
8082 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) | |
8083 | return; | |
8084 | ||
5c919412 AS |
8085 | bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors, |
8086 | vcpu_to_synic(vcpu)->vec_bitmap, 256); | |
8087 | kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); | |
c7c9c56c YZ |
8088 | } |
8089 | ||
93065ac7 MH |
8090 | int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, |
8091 | unsigned long start, unsigned long end, | |
8092 | bool blockable) | |
b1394e74 RK |
8093 | { |
8094 | unsigned long apic_address; | |
8095 | ||
8096 | /* | |
8097 | * The physical address of apic access page is stored in the VMCS. | |
8098 | * Update it when it becomes invalid. | |
8099 | */ | |
8100 | apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); | |
8101 | if (start <= apic_address && apic_address < end) | |
8102 | kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); | |
93065ac7 MH |
8103 | |
8104 | return 0; | |
b1394e74 RK |
8105 | } |
8106 | ||
4256f43f TC |
8107 | void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) |
8108 | { | |
c24ae0dc TC |
8109 | struct page *page = NULL; |
8110 | ||
35754c98 | 8111 | if (!lapic_in_kernel(vcpu)) |
f439ed27 PB |
8112 | return; |
8113 | ||
4256f43f TC |
8114 | if (!kvm_x86_ops->set_apic_access_page_addr) |
8115 | return; | |
8116 | ||
c24ae0dc | 8117 | page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); |
e8fd5e9e AA |
8118 | if (is_error_page(page)) |
8119 | return; | |
c24ae0dc TC |
8120 | kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page)); |
8121 | ||
8122 | /* | |
8123 | * Do not pin apic access page in memory, the MMU notifier | |
8124 | * will call us again if it is migrated or swapped out. | |
8125 | */ | |
8126 | put_page(page); | |
4256f43f | 8127 | } |
4256f43f | 8128 | |
d264ee0c SC |
8129 | void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) |
8130 | { | |
8131 | smp_send_reschedule(vcpu->cpu); | |
8132 | } | |
8133 | EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); | |
8134 | ||
9357d939 | 8135 | /* |
362c698f | 8136 | * Returns 1 to let vcpu_run() continue the guest execution loop without |
9357d939 TY |
8137 | * exiting to the userspace. Otherwise, the value will be returned to the |
8138 | * userspace. | |
8139 | */ | |
851ba692 | 8140 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
8141 | { |
8142 | int r; | |
62a193ed MG |
8143 | bool req_int_win = |
8144 | dm_request_for_irq_injection(vcpu) && | |
8145 | kvm_cpu_accept_dm_intr(vcpu); | |
1e9e2622 | 8146 | enum exit_fastpath_completion exit_fastpath = EXIT_FASTPATH_NONE; |
62a193ed | 8147 | |
730dca42 | 8148 | bool req_immediate_exit = false; |
b6c7a5dc | 8149 | |
2fa6e1e1 | 8150 | if (kvm_request_pending(vcpu)) { |
671ddc70 JM |
8151 | if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu)) { |
8152 | if (unlikely(!kvm_x86_ops->get_vmcs12_pages(vcpu))) { | |
8153 | r = 0; | |
8154 | goto out; | |
8155 | } | |
8156 | } | |
a8eeb04a | 8157 | if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) |
2e53d63a | 8158 | kvm_mmu_unload(vcpu); |
a8eeb04a | 8159 | if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) |
2f599714 | 8160 | __kvm_migrate_timers(vcpu); |
d828199e MT |
8161 | if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) |
8162 | kvm_gen_update_masterclock(vcpu->kvm); | |
0061d53d MT |
8163 | if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) |
8164 | kvm_gen_kvmclock_update(vcpu); | |
34c238a1 ZA |
8165 | if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { |
8166 | r = kvm_guest_time_update(vcpu); | |
8cfdc000 ZA |
8167 | if (unlikely(r)) |
8168 | goto out; | |
8169 | } | |
a8eeb04a | 8170 | if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) |
4731d4c7 | 8171 | kvm_mmu_sync_roots(vcpu); |
6e42782f JS |
8172 | if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu)) |
8173 | kvm_mmu_load_cr3(vcpu); | |
a8eeb04a | 8174 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) |
c2ba05cc | 8175 | kvm_vcpu_flush_tlb(vcpu, true); |
a8eeb04a | 8176 | if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { |
851ba692 | 8177 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
8178 | r = 0; |
8179 | goto out; | |
8180 | } | |
a8eeb04a | 8181 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
851ba692 | 8182 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
bbeac283 | 8183 | vcpu->mmio_needed = 0; |
71c4dfaf JR |
8184 | r = 0; |
8185 | goto out; | |
8186 | } | |
af585b92 GN |
8187 | if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { |
8188 | /* Page is swapped out. Do synthetic halt */ | |
8189 | vcpu->arch.apf.halted = true; | |
8190 | r = 1; | |
8191 | goto out; | |
8192 | } | |
c9aaa895 GC |
8193 | if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) |
8194 | record_steal_time(vcpu); | |
64d60670 PB |
8195 | if (kvm_check_request(KVM_REQ_SMI, vcpu)) |
8196 | process_smi(vcpu); | |
7460fb4a AK |
8197 | if (kvm_check_request(KVM_REQ_NMI, vcpu)) |
8198 | process_nmi(vcpu); | |
f5132b01 | 8199 | if (kvm_check_request(KVM_REQ_PMU, vcpu)) |
c6702c9d | 8200 | kvm_pmu_handle_event(vcpu); |
f5132b01 | 8201 | if (kvm_check_request(KVM_REQ_PMI, vcpu)) |
c6702c9d | 8202 | kvm_pmu_deliver_pmi(vcpu); |
7543a635 SR |
8203 | if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { |
8204 | BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); | |
8205 | if (test_bit(vcpu->arch.pending_ioapic_eoi, | |
6308630b | 8206 | vcpu->arch.ioapic_handled_vectors)) { |
7543a635 SR |
8207 | vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; |
8208 | vcpu->run->eoi.vector = | |
8209 | vcpu->arch.pending_ioapic_eoi; | |
8210 | r = 0; | |
8211 | goto out; | |
8212 | } | |
8213 | } | |
3d81bc7e YZ |
8214 | if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) |
8215 | vcpu_scan_ioapic(vcpu); | |
e40ff1d6 LA |
8216 | if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) |
8217 | vcpu_load_eoi_exitmap(vcpu); | |
4256f43f TC |
8218 | if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) |
8219 | kvm_vcpu_reload_apic_access_page(vcpu); | |
2ce79189 AS |
8220 | if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { |
8221 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
8222 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; | |
8223 | r = 0; | |
8224 | goto out; | |
8225 | } | |
e516cebb AS |
8226 | if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { |
8227 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
8228 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; | |
8229 | r = 0; | |
8230 | goto out; | |
8231 | } | |
db397571 AS |
8232 | if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { |
8233 | vcpu->run->exit_reason = KVM_EXIT_HYPERV; | |
8234 | vcpu->run->hyperv = vcpu->arch.hyperv.exit; | |
8235 | r = 0; | |
8236 | goto out; | |
8237 | } | |
f3b138c5 AS |
8238 | |
8239 | /* | |
8240 | * KVM_REQ_HV_STIMER has to be processed after | |
8241 | * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers | |
8242 | * depend on the guest clock being up-to-date | |
8243 | */ | |
1f4b34f8 AS |
8244 | if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) |
8245 | kvm_hv_process_stimers(vcpu); | |
8df14af4 SS |
8246 | if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) |
8247 | kvm_vcpu_update_apicv(vcpu); | |
2f52d58c | 8248 | } |
b93463aa | 8249 | |
b463a6f7 | 8250 | if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { |
0f1e261e | 8251 | ++vcpu->stat.req_event; |
66450a21 JK |
8252 | kvm_apic_accept_events(vcpu); |
8253 | if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { | |
8254 | r = 1; | |
8255 | goto out; | |
8256 | } | |
8257 | ||
b6b8a145 JK |
8258 | if (inject_pending_event(vcpu, req_int_win) != 0) |
8259 | req_immediate_exit = true; | |
321c5658 | 8260 | else { |
cc3d967f | 8261 | /* Enable SMI/NMI/IRQ window open exits if needed. |
c43203ca | 8262 | * |
cc3d967f LP |
8263 | * SMIs have three cases: |
8264 | * 1) They can be nested, and then there is nothing to | |
8265 | * do here because RSM will cause a vmexit anyway. | |
8266 | * 2) There is an ISA-specific reason why SMI cannot be | |
8267 | * injected, and the moment when this changes can be | |
8268 | * intercepted. | |
8269 | * 3) Or the SMI can be pending because | |
8270 | * inject_pending_event has completed the injection | |
8271 | * of an IRQ or NMI from the previous vmexit, and | |
8272 | * then we request an immediate exit to inject the | |
8273 | * SMI. | |
c43203ca PB |
8274 | */ |
8275 | if (vcpu->arch.smi_pending && !is_smm(vcpu)) | |
cc3d967f LP |
8276 | if (!kvm_x86_ops->enable_smi_window(vcpu)) |
8277 | req_immediate_exit = true; | |
321c5658 YS |
8278 | if (vcpu->arch.nmi_pending) |
8279 | kvm_x86_ops->enable_nmi_window(vcpu); | |
8280 | if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) | |
8281 | kvm_x86_ops->enable_irq_window(vcpu); | |
664f8e26 | 8282 | WARN_ON(vcpu->arch.exception.pending); |
321c5658 | 8283 | } |
b463a6f7 AK |
8284 | |
8285 | if (kvm_lapic_enabled(vcpu)) { | |
8286 | update_cr8_intercept(vcpu); | |
8287 | kvm_lapic_sync_to_vapic(vcpu); | |
8288 | } | |
8289 | } | |
8290 | ||
d8368af8 AK |
8291 | r = kvm_mmu_reload(vcpu); |
8292 | if (unlikely(r)) { | |
d905c069 | 8293 | goto cancel_injection; |
d8368af8 AK |
8294 | } |
8295 | ||
b6c7a5dc HB |
8296 | preempt_disable(); |
8297 | ||
8298 | kvm_x86_ops->prepare_guest_switch(vcpu); | |
b95234c8 PB |
8299 | |
8300 | /* | |
8301 | * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt | |
8302 | * IPI are then delayed after guest entry, which ensures that they | |
8303 | * result in virtual interrupt delivery. | |
8304 | */ | |
8305 | local_irq_disable(); | |
6b7e2d09 XG |
8306 | vcpu->mode = IN_GUEST_MODE; |
8307 | ||
01b71917 MT |
8308 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
8309 | ||
0f127d12 | 8310 | /* |
b95234c8 | 8311 | * 1) We should set ->mode before checking ->requests. Please see |
cde9af6e | 8312 | * the comment in kvm_vcpu_exiting_guest_mode(). |
b95234c8 | 8313 | * |
81b01667 | 8314 | * 2) For APICv, we should set ->mode before checking PID.ON. This |
b95234c8 PB |
8315 | * pairs with the memory barrier implicit in pi_test_and_set_on |
8316 | * (see vmx_deliver_posted_interrupt). | |
8317 | * | |
8318 | * 3) This also orders the write to mode from any reads to the page | |
8319 | * tables done while the VCPU is running. Please see the comment | |
8320 | * in kvm_flush_remote_tlbs. | |
6b7e2d09 | 8321 | */ |
01b71917 | 8322 | smp_mb__after_srcu_read_unlock(); |
b6c7a5dc | 8323 | |
b95234c8 PB |
8324 | /* |
8325 | * This handles the case where a posted interrupt was | |
8326 | * notified with kvm_vcpu_kick. | |
8327 | */ | |
fa59cc00 LA |
8328 | if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active) |
8329 | kvm_x86_ops->sync_pir_to_irr(vcpu); | |
32f88400 | 8330 | |
2fa6e1e1 | 8331 | if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) |
d94e1dc9 | 8332 | || need_resched() || signal_pending(current)) { |
6b7e2d09 | 8333 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 8334 | smp_wmb(); |
6c142801 AK |
8335 | local_irq_enable(); |
8336 | preempt_enable(); | |
01b71917 | 8337 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
6c142801 | 8338 | r = 1; |
d905c069 | 8339 | goto cancel_injection; |
6c142801 AK |
8340 | } |
8341 | ||
c43203ca PB |
8342 | if (req_immediate_exit) { |
8343 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
d264ee0c | 8344 | kvm_x86_ops->request_immediate_exit(vcpu); |
c43203ca | 8345 | } |
d6185f20 | 8346 | |
8b89fe1f | 8347 | trace_kvm_entry(vcpu->vcpu_id); |
6edaa530 | 8348 | guest_enter_irqoff(); |
b6c7a5dc | 8349 | |
2620fe26 SC |
8350 | fpregs_assert_state_consistent(); |
8351 | if (test_thread_flag(TIF_NEED_FPU_LOAD)) | |
8352 | switch_fpu_return(); | |
5f409e20 | 8353 | |
42dbaa5a | 8354 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
8355 | set_debugreg(0, 7); |
8356 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
8357 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
8358 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
8359 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
c77fb5fe | 8360 | set_debugreg(vcpu->arch.dr6, 6); |
ae561ede | 8361 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; |
42dbaa5a | 8362 | } |
b6c7a5dc | 8363 | |
851ba692 | 8364 | kvm_x86_ops->run(vcpu); |
b6c7a5dc | 8365 | |
c77fb5fe PB |
8366 | /* |
8367 | * Do this here before restoring debug registers on the host. And | |
8368 | * since we do this before handling the vmexit, a DR access vmexit | |
8369 | * can (a) read the correct value of the debug registers, (b) set | |
8370 | * KVM_DEBUGREG_WONT_EXIT again. | |
8371 | */ | |
8372 | if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { | |
c77fb5fe PB |
8373 | WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); |
8374 | kvm_x86_ops->sync_dirty_debug_regs(vcpu); | |
70e4da7a PB |
8375 | kvm_update_dr0123(vcpu); |
8376 | kvm_update_dr6(vcpu); | |
8377 | kvm_update_dr7(vcpu); | |
8378 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; | |
c77fb5fe PB |
8379 | } |
8380 | ||
24f1e32c FW |
8381 | /* |
8382 | * If the guest has used debug registers, at least dr7 | |
8383 | * will be disabled while returning to the host. | |
8384 | * If we don't have active breakpoints in the host, we don't | |
8385 | * care about the messed up debug address registers. But if | |
8386 | * we have some of them active, restore the old state. | |
8387 | */ | |
59d8eb53 | 8388 | if (hw_breakpoint_active()) |
24f1e32c | 8389 | hw_breakpoint_restore(); |
42dbaa5a | 8390 | |
4ba76538 | 8391 | vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); |
1d5f066e | 8392 | |
6b7e2d09 | 8393 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 8394 | smp_wmb(); |
a547c6db | 8395 | |
1e9e2622 | 8396 | kvm_x86_ops->handle_exit_irqoff(vcpu, &exit_fastpath); |
b6c7a5dc | 8397 | |
d7a08882 SC |
8398 | /* |
8399 | * Consume any pending interrupts, including the possible source of | |
8400 | * VM-Exit on SVM and any ticks that occur between VM-Exit and now. | |
8401 | * An instruction is required after local_irq_enable() to fully unblock | |
8402 | * interrupts on processors that implement an interrupt shadow, the | |
8403 | * stat.exits increment will do nicely. | |
8404 | */ | |
8405 | kvm_before_interrupt(vcpu); | |
8406 | local_irq_enable(); | |
b6c7a5dc | 8407 | ++vcpu->stat.exits; |
d7a08882 SC |
8408 | local_irq_disable(); |
8409 | kvm_after_interrupt(vcpu); | |
b6c7a5dc | 8410 | |
f2485b3e | 8411 | guest_exit_irqoff(); |
ec0671d5 WL |
8412 | if (lapic_in_kernel(vcpu)) { |
8413 | s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta; | |
8414 | if (delta != S64_MIN) { | |
8415 | trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta); | |
8416 | vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN; | |
8417 | } | |
8418 | } | |
b6c7a5dc | 8419 | |
f2485b3e | 8420 | local_irq_enable(); |
b6c7a5dc HB |
8421 | preempt_enable(); |
8422 | ||
f656ce01 | 8423 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
3200f405 | 8424 | |
b6c7a5dc HB |
8425 | /* |
8426 | * Profile KVM exit RIPs: | |
8427 | */ | |
8428 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
8429 | unsigned long rip = kvm_rip_read(vcpu); |
8430 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
8431 | } |
8432 | ||
cc578287 ZA |
8433 | if (unlikely(vcpu->arch.tsc_always_catchup)) |
8434 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
298101da | 8435 | |
5cfb1d5a MT |
8436 | if (vcpu->arch.apic_attention) |
8437 | kvm_lapic_sync_from_vapic(vcpu); | |
b93463aa | 8438 | |
618232e2 | 8439 | vcpu->arch.gpa_available = false; |
1e9e2622 | 8440 | r = kvm_x86_ops->handle_exit(vcpu, exit_fastpath); |
d905c069 MT |
8441 | return r; |
8442 | ||
8443 | cancel_injection: | |
8444 | kvm_x86_ops->cancel_injection(vcpu); | |
ae7a2a3f MT |
8445 | if (unlikely(vcpu->arch.apic_attention)) |
8446 | kvm_lapic_sync_from_vapic(vcpu); | |
d7690175 MT |
8447 | out: |
8448 | return r; | |
8449 | } | |
b6c7a5dc | 8450 | |
362c698f PB |
8451 | static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) |
8452 | { | |
bf9f6ac8 FW |
8453 | if (!kvm_arch_vcpu_runnable(vcpu) && |
8454 | (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) { | |
9c8fd1ba PB |
8455 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
8456 | kvm_vcpu_block(vcpu); | |
8457 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); | |
bf9f6ac8 FW |
8458 | |
8459 | if (kvm_x86_ops->post_block) | |
8460 | kvm_x86_ops->post_block(vcpu); | |
8461 | ||
9c8fd1ba PB |
8462 | if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) |
8463 | return 1; | |
8464 | } | |
362c698f PB |
8465 | |
8466 | kvm_apic_accept_events(vcpu); | |
8467 | switch(vcpu->arch.mp_state) { | |
8468 | case KVM_MP_STATE_HALTED: | |
8469 | vcpu->arch.pv.pv_unhalted = false; | |
8470 | vcpu->arch.mp_state = | |
8471 | KVM_MP_STATE_RUNNABLE; | |
b2869f28 | 8472 | /* fall through */ |
362c698f PB |
8473 | case KVM_MP_STATE_RUNNABLE: |
8474 | vcpu->arch.apf.halted = false; | |
8475 | break; | |
8476 | case KVM_MP_STATE_INIT_RECEIVED: | |
8477 | break; | |
8478 | default: | |
8479 | return -EINTR; | |
8480 | break; | |
8481 | } | |
8482 | return 1; | |
8483 | } | |
09cec754 | 8484 | |
5d9bc648 PB |
8485 | static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) |
8486 | { | |
0ad3bed6 PB |
8487 | if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) |
8488 | kvm_x86_ops->check_nested_events(vcpu, false); | |
8489 | ||
5d9bc648 PB |
8490 | return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
8491 | !vcpu->arch.apf.halted); | |
8492 | } | |
8493 | ||
362c698f | 8494 | static int vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
8495 | { |
8496 | int r; | |
f656ce01 | 8497 | struct kvm *kvm = vcpu->kvm; |
d7690175 | 8498 | |
f656ce01 | 8499 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
c595ceee | 8500 | vcpu->arch.l1tf_flush_l1d = true; |
d7690175 | 8501 | |
362c698f | 8502 | for (;;) { |
58f800d5 | 8503 | if (kvm_vcpu_running(vcpu)) { |
851ba692 | 8504 | r = vcpu_enter_guest(vcpu); |
bf9f6ac8 | 8505 | } else { |
362c698f | 8506 | r = vcpu_block(kvm, vcpu); |
bf9f6ac8 FW |
8507 | } |
8508 | ||
09cec754 GN |
8509 | if (r <= 0) |
8510 | break; | |
8511 | ||
72875d8a | 8512 | kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu); |
09cec754 GN |
8513 | if (kvm_cpu_has_pending_timer(vcpu)) |
8514 | kvm_inject_pending_timer_irqs(vcpu); | |
8515 | ||
782d422b MG |
8516 | if (dm_request_for_irq_injection(vcpu) && |
8517 | kvm_vcpu_ready_for_interrupt_injection(vcpu)) { | |
4ca7dd8c PB |
8518 | r = 0; |
8519 | vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; | |
09cec754 | 8520 | ++vcpu->stat.request_irq_exits; |
362c698f | 8521 | break; |
09cec754 | 8522 | } |
af585b92 GN |
8523 | |
8524 | kvm_check_async_pf_completion(vcpu); | |
8525 | ||
09cec754 GN |
8526 | if (signal_pending(current)) { |
8527 | r = -EINTR; | |
851ba692 | 8528 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 | 8529 | ++vcpu->stat.signal_exits; |
362c698f | 8530 | break; |
09cec754 GN |
8531 | } |
8532 | if (need_resched()) { | |
f656ce01 | 8533 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
c08ac06a | 8534 | cond_resched(); |
f656ce01 | 8535 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 8536 | } |
b6c7a5dc HB |
8537 | } |
8538 | ||
f656ce01 | 8539 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
b6c7a5dc HB |
8540 | |
8541 | return r; | |
8542 | } | |
8543 | ||
716d51ab GN |
8544 | static inline int complete_emulated_io(struct kvm_vcpu *vcpu) |
8545 | { | |
8546 | int r; | |
60fc3d02 | 8547 | |
716d51ab | 8548 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
0ce97a2b | 8549 | r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); |
716d51ab | 8550 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
60fc3d02 | 8551 | return r; |
716d51ab GN |
8552 | } |
8553 | ||
8554 | static int complete_emulated_pio(struct kvm_vcpu *vcpu) | |
8555 | { | |
8556 | BUG_ON(!vcpu->arch.pio.count); | |
8557 | ||
8558 | return complete_emulated_io(vcpu); | |
8559 | } | |
8560 | ||
f78146b0 AK |
8561 | /* |
8562 | * Implements the following, as a state machine: | |
8563 | * | |
8564 | * read: | |
8565 | * for each fragment | |
87da7e66 XG |
8566 | * for each mmio piece in the fragment |
8567 | * write gpa, len | |
8568 | * exit | |
8569 | * copy data | |
f78146b0 AK |
8570 | * execute insn |
8571 | * | |
8572 | * write: | |
8573 | * for each fragment | |
87da7e66 XG |
8574 | * for each mmio piece in the fragment |
8575 | * write gpa, len | |
8576 | * copy data | |
8577 | * exit | |
f78146b0 | 8578 | */ |
716d51ab | 8579 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu) |
5287f194 AK |
8580 | { |
8581 | struct kvm_run *run = vcpu->run; | |
f78146b0 | 8582 | struct kvm_mmio_fragment *frag; |
87da7e66 | 8583 | unsigned len; |
5287f194 | 8584 | |
716d51ab | 8585 | BUG_ON(!vcpu->mmio_needed); |
5287f194 | 8586 | |
716d51ab | 8587 | /* Complete previous fragment */ |
87da7e66 XG |
8588 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; |
8589 | len = min(8u, frag->len); | |
716d51ab | 8590 | if (!vcpu->mmio_is_write) |
87da7e66 XG |
8591 | memcpy(frag->data, run->mmio.data, len); |
8592 | ||
8593 | if (frag->len <= 8) { | |
8594 | /* Switch to the next fragment. */ | |
8595 | frag++; | |
8596 | vcpu->mmio_cur_fragment++; | |
8597 | } else { | |
8598 | /* Go forward to the next mmio piece. */ | |
8599 | frag->data += len; | |
8600 | frag->gpa += len; | |
8601 | frag->len -= len; | |
8602 | } | |
8603 | ||
a08d3b3b | 8604 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { |
716d51ab | 8605 | vcpu->mmio_needed = 0; |
0912c977 PB |
8606 | |
8607 | /* FIXME: return into emulator if single-stepping. */ | |
cef4dea0 | 8608 | if (vcpu->mmio_is_write) |
716d51ab GN |
8609 | return 1; |
8610 | vcpu->mmio_read_completed = 1; | |
8611 | return complete_emulated_io(vcpu); | |
8612 | } | |
87da7e66 | 8613 | |
716d51ab GN |
8614 | run->exit_reason = KVM_EXIT_MMIO; |
8615 | run->mmio.phys_addr = frag->gpa; | |
8616 | if (vcpu->mmio_is_write) | |
87da7e66 XG |
8617 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); |
8618 | run->mmio.len = min(8u, frag->len); | |
716d51ab GN |
8619 | run->mmio.is_write = vcpu->mmio_is_write; |
8620 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; | |
8621 | return 0; | |
5287f194 AK |
8622 | } |
8623 | ||
c9aef3b8 SC |
8624 | static void kvm_save_current_fpu(struct fpu *fpu) |
8625 | { | |
8626 | /* | |
8627 | * If the target FPU state is not resident in the CPU registers, just | |
8628 | * memcpy() from current, else save CPU state directly to the target. | |
8629 | */ | |
8630 | if (test_thread_flag(TIF_NEED_FPU_LOAD)) | |
8631 | memcpy(&fpu->state, ¤t->thread.fpu.state, | |
8632 | fpu_kernel_xstate_size); | |
8633 | else | |
8634 | copy_fpregs_to_fpstate(fpu); | |
8635 | } | |
8636 | ||
822f312d SAS |
8637 | /* Swap (qemu) user FPU context for the guest FPU context. */ |
8638 | static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) | |
8639 | { | |
5f409e20 RR |
8640 | fpregs_lock(); |
8641 | ||
c9aef3b8 SC |
8642 | kvm_save_current_fpu(vcpu->arch.user_fpu); |
8643 | ||
822f312d | 8644 | /* PKRU is separately restored in kvm_x86_ops->run. */ |
b666a4b6 | 8645 | __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state, |
822f312d | 8646 | ~XFEATURE_MASK_PKRU); |
5f409e20 RR |
8647 | |
8648 | fpregs_mark_activate(); | |
8649 | fpregs_unlock(); | |
8650 | ||
822f312d SAS |
8651 | trace_kvm_fpu(1); |
8652 | } | |
8653 | ||
8654 | /* When vcpu_run ends, restore user space FPU context. */ | |
8655 | static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
8656 | { | |
5f409e20 RR |
8657 | fpregs_lock(); |
8658 | ||
c9aef3b8 SC |
8659 | kvm_save_current_fpu(vcpu->arch.guest_fpu); |
8660 | ||
d9a710e5 | 8661 | copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state); |
5f409e20 RR |
8662 | |
8663 | fpregs_mark_activate(); | |
8664 | fpregs_unlock(); | |
8665 | ||
822f312d SAS |
8666 | ++vcpu->stat.fpu_reload; |
8667 | trace_kvm_fpu(0); | |
8668 | } | |
8669 | ||
b6c7a5dc HB |
8670 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
8671 | { | |
8672 | int r; | |
b6c7a5dc | 8673 | |
accb757d | 8674 | vcpu_load(vcpu); |
20b7035c | 8675 | kvm_sigset_activate(vcpu); |
5663d8f9 PX |
8676 | kvm_load_guest_fpu(vcpu); |
8677 | ||
a4535290 | 8678 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
2f173d26 JS |
8679 | if (kvm_run->immediate_exit) { |
8680 | r = -EINTR; | |
8681 | goto out; | |
8682 | } | |
b6c7a5dc | 8683 | kvm_vcpu_block(vcpu); |
66450a21 | 8684 | kvm_apic_accept_events(vcpu); |
72875d8a | 8685 | kvm_clear_request(KVM_REQ_UNHALT, vcpu); |
ac9f6dc0 | 8686 | r = -EAGAIN; |
a0595000 JS |
8687 | if (signal_pending(current)) { |
8688 | r = -EINTR; | |
8689 | vcpu->run->exit_reason = KVM_EXIT_INTR; | |
8690 | ++vcpu->stat.signal_exits; | |
8691 | } | |
ac9f6dc0 | 8692 | goto out; |
b6c7a5dc HB |
8693 | } |
8694 | ||
01643c51 KH |
8695 | if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) { |
8696 | r = -EINVAL; | |
8697 | goto out; | |
8698 | } | |
8699 | ||
8700 | if (vcpu->run->kvm_dirty_regs) { | |
8701 | r = sync_regs(vcpu); | |
8702 | if (r != 0) | |
8703 | goto out; | |
8704 | } | |
8705 | ||
b6c7a5dc | 8706 | /* re-sync apic's tpr */ |
35754c98 | 8707 | if (!lapic_in_kernel(vcpu)) { |
eea1cff9 AP |
8708 | if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { |
8709 | r = -EINVAL; | |
8710 | goto out; | |
8711 | } | |
8712 | } | |
b6c7a5dc | 8713 | |
716d51ab GN |
8714 | if (unlikely(vcpu->arch.complete_userspace_io)) { |
8715 | int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; | |
8716 | vcpu->arch.complete_userspace_io = NULL; | |
8717 | r = cui(vcpu); | |
8718 | if (r <= 0) | |
5663d8f9 | 8719 | goto out; |
716d51ab GN |
8720 | } else |
8721 | WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); | |
5287f194 | 8722 | |
460df4c1 PB |
8723 | if (kvm_run->immediate_exit) |
8724 | r = -EINTR; | |
8725 | else | |
8726 | r = vcpu_run(vcpu); | |
b6c7a5dc HB |
8727 | |
8728 | out: | |
5663d8f9 | 8729 | kvm_put_guest_fpu(vcpu); |
01643c51 KH |
8730 | if (vcpu->run->kvm_valid_regs) |
8731 | store_regs(vcpu); | |
f1d86e46 | 8732 | post_kvm_run_save(vcpu); |
20b7035c | 8733 | kvm_sigset_deactivate(vcpu); |
b6c7a5dc | 8734 | |
accb757d | 8735 | vcpu_put(vcpu); |
b6c7a5dc HB |
8736 | return r; |
8737 | } | |
8738 | ||
01643c51 | 8739 | static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 8740 | { |
7ae441ea GN |
8741 | if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { |
8742 | /* | |
8743 | * We are here if userspace calls get_regs() in the middle of | |
8744 | * instruction emulation. Registers state needs to be copied | |
4a969980 | 8745 | * back from emulation context to vcpu. Userspace shouldn't do |
7ae441ea GN |
8746 | * that usually, but some bad designed PV devices (vmware |
8747 | * backdoor interface) need this to work | |
8748 | */ | |
dd856efa | 8749 | emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); |
7ae441ea GN |
8750 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
8751 | } | |
de3cd117 SC |
8752 | regs->rax = kvm_rax_read(vcpu); |
8753 | regs->rbx = kvm_rbx_read(vcpu); | |
8754 | regs->rcx = kvm_rcx_read(vcpu); | |
8755 | regs->rdx = kvm_rdx_read(vcpu); | |
8756 | regs->rsi = kvm_rsi_read(vcpu); | |
8757 | regs->rdi = kvm_rdi_read(vcpu); | |
e9c16c78 | 8758 | regs->rsp = kvm_rsp_read(vcpu); |
de3cd117 | 8759 | regs->rbp = kvm_rbp_read(vcpu); |
b6c7a5dc | 8760 | #ifdef CONFIG_X86_64 |
de3cd117 SC |
8761 | regs->r8 = kvm_r8_read(vcpu); |
8762 | regs->r9 = kvm_r9_read(vcpu); | |
8763 | regs->r10 = kvm_r10_read(vcpu); | |
8764 | regs->r11 = kvm_r11_read(vcpu); | |
8765 | regs->r12 = kvm_r12_read(vcpu); | |
8766 | regs->r13 = kvm_r13_read(vcpu); | |
8767 | regs->r14 = kvm_r14_read(vcpu); | |
8768 | regs->r15 = kvm_r15_read(vcpu); | |
b6c7a5dc HB |
8769 | #endif |
8770 | ||
5fdbf976 | 8771 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 8772 | regs->rflags = kvm_get_rflags(vcpu); |
01643c51 | 8773 | } |
b6c7a5dc | 8774 | |
01643c51 KH |
8775 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
8776 | { | |
8777 | vcpu_load(vcpu); | |
8778 | __get_regs(vcpu, regs); | |
1fc9b76b | 8779 | vcpu_put(vcpu); |
b6c7a5dc HB |
8780 | return 0; |
8781 | } | |
8782 | ||
01643c51 | 8783 | static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 8784 | { |
7ae441ea GN |
8785 | vcpu->arch.emulate_regs_need_sync_from_vcpu = true; |
8786 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; | |
8787 | ||
de3cd117 SC |
8788 | kvm_rax_write(vcpu, regs->rax); |
8789 | kvm_rbx_write(vcpu, regs->rbx); | |
8790 | kvm_rcx_write(vcpu, regs->rcx); | |
8791 | kvm_rdx_write(vcpu, regs->rdx); | |
8792 | kvm_rsi_write(vcpu, regs->rsi); | |
8793 | kvm_rdi_write(vcpu, regs->rdi); | |
e9c16c78 | 8794 | kvm_rsp_write(vcpu, regs->rsp); |
de3cd117 | 8795 | kvm_rbp_write(vcpu, regs->rbp); |
b6c7a5dc | 8796 | #ifdef CONFIG_X86_64 |
de3cd117 SC |
8797 | kvm_r8_write(vcpu, regs->r8); |
8798 | kvm_r9_write(vcpu, regs->r9); | |
8799 | kvm_r10_write(vcpu, regs->r10); | |
8800 | kvm_r11_write(vcpu, regs->r11); | |
8801 | kvm_r12_write(vcpu, regs->r12); | |
8802 | kvm_r13_write(vcpu, regs->r13); | |
8803 | kvm_r14_write(vcpu, regs->r14); | |
8804 | kvm_r15_write(vcpu, regs->r15); | |
b6c7a5dc HB |
8805 | #endif |
8806 | ||
5fdbf976 | 8807 | kvm_rip_write(vcpu, regs->rip); |
d73235d1 | 8808 | kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); |
b6c7a5dc | 8809 | |
b4f14abd JK |
8810 | vcpu->arch.exception.pending = false; |
8811 | ||
3842d135 | 8812 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
01643c51 | 8813 | } |
3842d135 | 8814 | |
01643c51 KH |
8815 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
8816 | { | |
8817 | vcpu_load(vcpu); | |
8818 | __set_regs(vcpu, regs); | |
875656fe | 8819 | vcpu_put(vcpu); |
b6c7a5dc HB |
8820 | return 0; |
8821 | } | |
8822 | ||
b6c7a5dc HB |
8823 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
8824 | { | |
8825 | struct kvm_segment cs; | |
8826 | ||
3e6e0aab | 8827 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
8828 | *db = cs.db; |
8829 | *l = cs.l; | |
8830 | } | |
8831 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
8832 | ||
01643c51 | 8833 | static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
b6c7a5dc | 8834 | { |
89a27f4d | 8835 | struct desc_ptr dt; |
b6c7a5dc | 8836 | |
3e6e0aab GT |
8837 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
8838 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
8839 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
8840 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
8841 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
8842 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 8843 | |
3e6e0aab GT |
8844 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
8845 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc HB |
8846 | |
8847 | kvm_x86_ops->get_idt(vcpu, &dt); | |
89a27f4d GN |
8848 | sregs->idt.limit = dt.size; |
8849 | sregs->idt.base = dt.address; | |
b6c7a5dc | 8850 | kvm_x86_ops->get_gdt(vcpu, &dt); |
89a27f4d GN |
8851 | sregs->gdt.limit = dt.size; |
8852 | sregs->gdt.base = dt.address; | |
b6c7a5dc | 8853 | |
4d4ec087 | 8854 | sregs->cr0 = kvm_read_cr0(vcpu); |
ad312c7c | 8855 | sregs->cr2 = vcpu->arch.cr2; |
9f8fe504 | 8856 | sregs->cr3 = kvm_read_cr3(vcpu); |
fc78f519 | 8857 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 8858 | sregs->cr8 = kvm_get_cr8(vcpu); |
f6801dff | 8859 | sregs->efer = vcpu->arch.efer; |
b6c7a5dc HB |
8860 | sregs->apic_base = kvm_get_apic_base(vcpu); |
8861 | ||
0e96f31e | 8862 | memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap)); |
b6c7a5dc | 8863 | |
04140b41 | 8864 | if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
8865 | set_bit(vcpu->arch.interrupt.nr, |
8866 | (unsigned long *)sregs->interrupt_bitmap); | |
01643c51 | 8867 | } |
16d7a191 | 8868 | |
01643c51 KH |
8869 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, |
8870 | struct kvm_sregs *sregs) | |
8871 | { | |
8872 | vcpu_load(vcpu); | |
8873 | __get_sregs(vcpu, sregs); | |
bcdec41c | 8874 | vcpu_put(vcpu); |
b6c7a5dc HB |
8875 | return 0; |
8876 | } | |
8877 | ||
62d9f0db MT |
8878 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
8879 | struct kvm_mp_state *mp_state) | |
8880 | { | |
fd232561 | 8881 | vcpu_load(vcpu); |
f958bd23 SC |
8882 | if (kvm_mpx_supported()) |
8883 | kvm_load_guest_fpu(vcpu); | |
fd232561 | 8884 | |
66450a21 | 8885 | kvm_apic_accept_events(vcpu); |
6aef266c SV |
8886 | if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && |
8887 | vcpu->arch.pv.pv_unhalted) | |
8888 | mp_state->mp_state = KVM_MP_STATE_RUNNABLE; | |
8889 | else | |
8890 | mp_state->mp_state = vcpu->arch.mp_state; | |
8891 | ||
f958bd23 SC |
8892 | if (kvm_mpx_supported()) |
8893 | kvm_put_guest_fpu(vcpu); | |
fd232561 | 8894 | vcpu_put(vcpu); |
62d9f0db MT |
8895 | return 0; |
8896 | } | |
8897 | ||
8898 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
8899 | struct kvm_mp_state *mp_state) | |
8900 | { | |
e83dff5e CD |
8901 | int ret = -EINVAL; |
8902 | ||
8903 | vcpu_load(vcpu); | |
8904 | ||
bce87cce | 8905 | if (!lapic_in_kernel(vcpu) && |
66450a21 | 8906 | mp_state->mp_state != KVM_MP_STATE_RUNNABLE) |
e83dff5e | 8907 | goto out; |
66450a21 | 8908 | |
27cbe7d6 LA |
8909 | /* |
8910 | * KVM_MP_STATE_INIT_RECEIVED means the processor is in | |
8911 | * INIT state; latched init should be reported using | |
8912 | * KVM_SET_VCPU_EVENTS, so reject it here. | |
8913 | */ | |
8914 | if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) && | |
28bf2888 DH |
8915 | (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || |
8916 | mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) | |
e83dff5e | 8917 | goto out; |
28bf2888 | 8918 | |
66450a21 JK |
8919 | if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { |
8920 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
8921 | set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); | |
8922 | } else | |
8923 | vcpu->arch.mp_state = mp_state->mp_state; | |
3842d135 | 8924 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
e83dff5e CD |
8925 | |
8926 | ret = 0; | |
8927 | out: | |
8928 | vcpu_put(vcpu); | |
8929 | return ret; | |
62d9f0db MT |
8930 | } |
8931 | ||
7f3d35fd KW |
8932 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
8933 | int reason, bool has_error_code, u32 error_code) | |
b6c7a5dc | 8934 | { |
9d74191a | 8935 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
8ec4722d | 8936 | int ret; |
e01c2426 | 8937 | |
8ec4722d | 8938 | init_emulate_ctxt(vcpu); |
c697518a | 8939 | |
7f3d35fd | 8940 | ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, |
9d74191a | 8941 | has_error_code, error_code); |
1051778f SC |
8942 | if (ret) { |
8943 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
8944 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
8945 | vcpu->run->internal.ndata = 0; | |
60fc3d02 | 8946 | return 0; |
1051778f | 8947 | } |
37817f29 | 8948 | |
9d74191a TY |
8949 | kvm_rip_write(vcpu, ctxt->eip); |
8950 | kvm_set_rflags(vcpu, ctxt->eflags); | |
3842d135 | 8951 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
60fc3d02 | 8952 | return 1; |
37817f29 IE |
8953 | } |
8954 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
8955 | ||
3140c156 | 8956 | static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
f2981033 | 8957 | { |
37b95951 | 8958 | if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { |
f2981033 LT |
8959 | /* |
8960 | * When EFER.LME and CR0.PG are set, the processor is in | |
8961 | * 64-bit mode (though maybe in a 32-bit code segment). | |
8962 | * CR4.PAE and EFER.LMA must be set. | |
8963 | */ | |
37b95951 | 8964 | if (!(sregs->cr4 & X86_CR4_PAE) |
f2981033 LT |
8965 | || !(sregs->efer & EFER_LMA)) |
8966 | return -EINVAL; | |
8967 | } else { | |
8968 | /* | |
8969 | * Not in 64-bit mode: EFER.LMA is clear and the code | |
8970 | * segment cannot be 64-bit. | |
8971 | */ | |
8972 | if (sregs->efer & EFER_LMA || sregs->cs.l) | |
8973 | return -EINVAL; | |
8974 | } | |
8975 | ||
3ca94192 | 8976 | return kvm_valid_cr4(vcpu, sregs->cr4); |
f2981033 LT |
8977 | } |
8978 | ||
01643c51 | 8979 | static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
b6c7a5dc | 8980 | { |
58cb628d | 8981 | struct msr_data apic_base_msr; |
b6c7a5dc | 8982 | int mmu_reset_needed = 0; |
c4d21882 | 8983 | int cpuid_update_needed = 0; |
63f42e02 | 8984 | int pending_vec, max_bits, idx; |
89a27f4d | 8985 | struct desc_ptr dt; |
b4ef9d4e CD |
8986 | int ret = -EINVAL; |
8987 | ||
f2981033 | 8988 | if (kvm_valid_sregs(vcpu, sregs)) |
8dbfb2bf | 8989 | goto out; |
f2981033 | 8990 | |
d3802286 JM |
8991 | apic_base_msr.data = sregs->apic_base; |
8992 | apic_base_msr.host_initiated = true; | |
8993 | if (kvm_set_apic_base(vcpu, &apic_base_msr)) | |
b4ef9d4e | 8994 | goto out; |
6d1068b3 | 8995 | |
89a27f4d GN |
8996 | dt.size = sregs->idt.limit; |
8997 | dt.address = sregs->idt.base; | |
b6c7a5dc | 8998 | kvm_x86_ops->set_idt(vcpu, &dt); |
89a27f4d GN |
8999 | dt.size = sregs->gdt.limit; |
9000 | dt.address = sregs->gdt.base; | |
b6c7a5dc HB |
9001 | kvm_x86_ops->set_gdt(vcpu, &dt); |
9002 | ||
ad312c7c | 9003 | vcpu->arch.cr2 = sregs->cr2; |
9f8fe504 | 9004 | mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; |
dc7e795e | 9005 | vcpu->arch.cr3 = sregs->cr3; |
cb3c1e2f | 9006 | kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); |
b6c7a5dc | 9007 | |
2d3ad1f4 | 9008 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 9009 | |
f6801dff | 9010 | mmu_reset_needed |= vcpu->arch.efer != sregs->efer; |
b6c7a5dc | 9011 | kvm_x86_ops->set_efer(vcpu, sregs->efer); |
b6c7a5dc | 9012 | |
4d4ec087 | 9013 | mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
b6c7a5dc | 9014 | kvm_x86_ops->set_cr0(vcpu, sregs->cr0); |
d7306163 | 9015 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 9016 | |
fc78f519 | 9017 | mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
c4d21882 WH |
9018 | cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) & |
9019 | (X86_CR4_OSXSAVE | X86_CR4_PKE)); | |
b6c7a5dc | 9020 | kvm_x86_ops->set_cr4(vcpu, sregs->cr4); |
c4d21882 | 9021 | if (cpuid_update_needed) |
00b27a3e | 9022 | kvm_update_cpuid(vcpu); |
63f42e02 XG |
9023 | |
9024 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
bf03d4f9 | 9025 | if (is_pae_paging(vcpu)) { |
9f8fe504 | 9026 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
7c93be44 MT |
9027 | mmu_reset_needed = 1; |
9028 | } | |
63f42e02 | 9029 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b6c7a5dc HB |
9030 | |
9031 | if (mmu_reset_needed) | |
9032 | kvm_mmu_reset_context(vcpu); | |
9033 | ||
a50abc3b | 9034 | max_bits = KVM_NR_INTERRUPTS; |
923c61bb GN |
9035 | pending_vec = find_first_bit( |
9036 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
9037 | if (pending_vec < max_bits) { | |
66fd3f7f | 9038 | kvm_queue_interrupt(vcpu, pending_vec, false); |
923c61bb | 9039 | pr_debug("Set back pending irq %d\n", pending_vec); |
b6c7a5dc HB |
9040 | } |
9041 | ||
3e6e0aab GT |
9042 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
9043 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
9044 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
9045 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
9046 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
9047 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 9048 | |
3e6e0aab GT |
9049 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
9050 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 9051 | |
5f0269f5 ME |
9052 | update_cr8_intercept(vcpu); |
9053 | ||
9c3e4aab | 9054 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 9055 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 9056 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
3eeb3288 | 9057 | !is_protmode(vcpu)) |
9c3e4aab MT |
9058 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
9059 | ||
3842d135 AK |
9060 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
9061 | ||
b4ef9d4e CD |
9062 | ret = 0; |
9063 | out: | |
01643c51 KH |
9064 | return ret; |
9065 | } | |
9066 | ||
9067 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, | |
9068 | struct kvm_sregs *sregs) | |
9069 | { | |
9070 | int ret; | |
9071 | ||
9072 | vcpu_load(vcpu); | |
9073 | ret = __set_sregs(vcpu, sregs); | |
b4ef9d4e CD |
9074 | vcpu_put(vcpu); |
9075 | return ret; | |
b6c7a5dc HB |
9076 | } |
9077 | ||
d0bfb940 JK |
9078 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
9079 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 9080 | { |
355be0b9 | 9081 | unsigned long rflags; |
ae675ef0 | 9082 | int i, r; |
b6c7a5dc | 9083 | |
66b56562 CD |
9084 | vcpu_load(vcpu); |
9085 | ||
4f926bf2 JK |
9086 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
9087 | r = -EBUSY; | |
9088 | if (vcpu->arch.exception.pending) | |
2122ff5e | 9089 | goto out; |
4f926bf2 JK |
9090 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
9091 | kvm_queue_exception(vcpu, DB_VECTOR); | |
9092 | else | |
9093 | kvm_queue_exception(vcpu, BP_VECTOR); | |
9094 | } | |
9095 | ||
91586a3b JK |
9096 | /* |
9097 | * Read rflags as long as potentially injected trace flags are still | |
9098 | * filtered out. | |
9099 | */ | |
9100 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
9101 | |
9102 | vcpu->guest_debug = dbg->control; | |
9103 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
9104 | vcpu->guest_debug = 0; | |
9105 | ||
9106 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
9107 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
9108 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
c8639010 | 9109 | vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; |
ae675ef0 JK |
9110 | } else { |
9111 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
9112 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
ae675ef0 | 9113 | } |
c8639010 | 9114 | kvm_update_dr7(vcpu); |
ae675ef0 | 9115 | |
f92653ee JK |
9116 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
9117 | vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + | |
9118 | get_segment_base(vcpu, VCPU_SREG_CS); | |
94fe45da | 9119 | |
91586a3b JK |
9120 | /* |
9121 | * Trigger an rflags update that will inject or remove the trace | |
9122 | * flags. | |
9123 | */ | |
9124 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 9125 | |
a96036b8 | 9126 | kvm_x86_ops->update_bp_intercept(vcpu); |
b6c7a5dc | 9127 | |
4f926bf2 | 9128 | r = 0; |
d0bfb940 | 9129 | |
2122ff5e | 9130 | out: |
66b56562 | 9131 | vcpu_put(vcpu); |
b6c7a5dc HB |
9132 | return r; |
9133 | } | |
9134 | ||
8b006791 ZX |
9135 | /* |
9136 | * Translate a guest virtual address to a guest physical address. | |
9137 | */ | |
9138 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
9139 | struct kvm_translation *tr) | |
9140 | { | |
9141 | unsigned long vaddr = tr->linear_address; | |
9142 | gpa_t gpa; | |
f656ce01 | 9143 | int idx; |
8b006791 | 9144 | |
1da5b61d CD |
9145 | vcpu_load(vcpu); |
9146 | ||
f656ce01 | 9147 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1871c602 | 9148 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); |
f656ce01 | 9149 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 ZX |
9150 | tr->physical_address = gpa; |
9151 | tr->valid = gpa != UNMAPPED_GVA; | |
9152 | tr->writeable = 1; | |
9153 | tr->usermode = 0; | |
8b006791 | 9154 | |
1da5b61d | 9155 | vcpu_put(vcpu); |
8b006791 ZX |
9156 | return 0; |
9157 | } | |
9158 | ||
d0752060 HB |
9159 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
9160 | { | |
1393123e | 9161 | struct fxregs_state *fxsave; |
d0752060 | 9162 | |
1393123e | 9163 | vcpu_load(vcpu); |
d0752060 | 9164 | |
b666a4b6 | 9165 | fxsave = &vcpu->arch.guest_fpu->state.fxsave; |
d0752060 HB |
9166 | memcpy(fpu->fpr, fxsave->st_space, 128); |
9167 | fpu->fcw = fxsave->cwd; | |
9168 | fpu->fsw = fxsave->swd; | |
9169 | fpu->ftwx = fxsave->twd; | |
9170 | fpu->last_opcode = fxsave->fop; | |
9171 | fpu->last_ip = fxsave->rip; | |
9172 | fpu->last_dp = fxsave->rdp; | |
0e96f31e | 9173 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); |
d0752060 | 9174 | |
1393123e | 9175 | vcpu_put(vcpu); |
d0752060 HB |
9176 | return 0; |
9177 | } | |
9178 | ||
9179 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
9180 | { | |
6a96bc7f CD |
9181 | struct fxregs_state *fxsave; |
9182 | ||
9183 | vcpu_load(vcpu); | |
9184 | ||
b666a4b6 | 9185 | fxsave = &vcpu->arch.guest_fpu->state.fxsave; |
d0752060 | 9186 | |
d0752060 HB |
9187 | memcpy(fxsave->st_space, fpu->fpr, 128); |
9188 | fxsave->cwd = fpu->fcw; | |
9189 | fxsave->swd = fpu->fsw; | |
9190 | fxsave->twd = fpu->ftwx; | |
9191 | fxsave->fop = fpu->last_opcode; | |
9192 | fxsave->rip = fpu->last_ip; | |
9193 | fxsave->rdp = fpu->last_dp; | |
0e96f31e | 9194 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); |
d0752060 | 9195 | |
6a96bc7f | 9196 | vcpu_put(vcpu); |
d0752060 HB |
9197 | return 0; |
9198 | } | |
9199 | ||
01643c51 KH |
9200 | static void store_regs(struct kvm_vcpu *vcpu) |
9201 | { | |
9202 | BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); | |
9203 | ||
9204 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) | |
9205 | __get_regs(vcpu, &vcpu->run->s.regs.regs); | |
9206 | ||
9207 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) | |
9208 | __get_sregs(vcpu, &vcpu->run->s.regs.sregs); | |
9209 | ||
9210 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) | |
9211 | kvm_vcpu_ioctl_x86_get_vcpu_events( | |
9212 | vcpu, &vcpu->run->s.regs.events); | |
9213 | } | |
9214 | ||
9215 | static int sync_regs(struct kvm_vcpu *vcpu) | |
9216 | { | |
9217 | if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS) | |
9218 | return -EINVAL; | |
9219 | ||
9220 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { | |
9221 | __set_regs(vcpu, &vcpu->run->s.regs.regs); | |
9222 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; | |
9223 | } | |
9224 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { | |
9225 | if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) | |
9226 | return -EINVAL; | |
9227 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; | |
9228 | } | |
9229 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { | |
9230 | if (kvm_vcpu_ioctl_x86_set_vcpu_events( | |
9231 | vcpu, &vcpu->run->s.regs.events)) | |
9232 | return -EINVAL; | |
9233 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; | |
9234 | } | |
9235 | ||
9236 | return 0; | |
9237 | } | |
9238 | ||
0ee6a517 | 9239 | static void fx_init(struct kvm_vcpu *vcpu) |
d0752060 | 9240 | { |
b666a4b6 | 9241 | fpstate_init(&vcpu->arch.guest_fpu->state); |
782511b0 | 9242 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
b666a4b6 | 9243 | vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv = |
df1daba7 | 9244 | host_xcr0 | XSTATE_COMPACTION_ENABLED; |
d0752060 | 9245 | |
2acf923e DC |
9246 | /* |
9247 | * Ensure guest xcr0 is valid for loading | |
9248 | */ | |
d91cab78 | 9249 | vcpu->arch.xcr0 = XFEATURE_MASK_FP; |
2acf923e | 9250 | |
ad312c7c | 9251 | vcpu->arch.cr0 |= X86_CR0_ET; |
d0752060 | 9252 | } |
d0752060 | 9253 | |
897cc38e | 9254 | int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) |
e9b11c17 | 9255 | { |
897cc38e SC |
9256 | if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) |
9257 | pr_warn_once("kvm: SMP vm created on host with unstable TSC; " | |
9258 | "guest TSC will not be reliable\n"); | |
7f1ea208 | 9259 | |
897cc38e | 9260 | return 0; |
e9b11c17 ZX |
9261 | } |
9262 | ||
e529ef66 | 9263 | int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) |
e9b11c17 | 9264 | { |
95a0d01e SC |
9265 | struct page *page; |
9266 | int r; | |
c447e76b | 9267 | |
95a0d01e SC |
9268 | vcpu->arch.emulate_ctxt.ops = &emulate_ops; |
9269 | if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) | |
9270 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
9271 | else | |
9272 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; | |
c447e76b | 9273 | |
95a0d01e | 9274 | kvm_set_tsc_khz(vcpu, max_tsc_khz); |
c447e76b | 9275 | |
95a0d01e SC |
9276 | r = kvm_mmu_create(vcpu); |
9277 | if (r < 0) | |
9278 | return r; | |
9279 | ||
9280 | if (irqchip_in_kernel(vcpu->kvm)) { | |
95a0d01e SC |
9281 | r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); |
9282 | if (r < 0) | |
9283 | goto fail_mmu_destroy; | |
4e19c36f SS |
9284 | if (kvm_apicv_activated(vcpu->kvm)) |
9285 | vcpu->arch.apicv_active = true; | |
95a0d01e SC |
9286 | } else |
9287 | static_key_slow_inc(&kvm_no_apic_vcpu); | |
9288 | ||
9289 | r = -ENOMEM; | |
9290 | ||
9291 | page = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
9292 | if (!page) | |
9293 | goto fail_free_lapic; | |
9294 | vcpu->arch.pio_data = page_address(page); | |
9295 | ||
9296 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, | |
9297 | GFP_KERNEL_ACCOUNT); | |
9298 | if (!vcpu->arch.mce_banks) | |
9299 | goto fail_free_pio_data; | |
9300 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
9301 | ||
9302 | if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, | |
9303 | GFP_KERNEL_ACCOUNT)) | |
9304 | goto fail_free_mce_banks; | |
9305 | ||
9306 | vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache, | |
9307 | GFP_KERNEL_ACCOUNT); | |
9308 | if (!vcpu->arch.user_fpu) { | |
9309 | pr_err("kvm: failed to allocate userspace's fpu\n"); | |
9310 | goto free_wbinvd_dirty_mask; | |
9311 | } | |
9312 | ||
9313 | vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, | |
9314 | GFP_KERNEL_ACCOUNT); | |
9315 | if (!vcpu->arch.guest_fpu) { | |
9316 | pr_err("kvm: failed to allocate vcpu's fpu\n"); | |
9317 | goto free_user_fpu; | |
9318 | } | |
9319 | fx_init(vcpu); | |
9320 | ||
9321 | vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; | |
9322 | ||
9323 | vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); | |
9324 | ||
9325 | vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; | |
9326 | ||
9327 | kvm_async_pf_hash_reset(vcpu); | |
9328 | kvm_pmu_init(vcpu); | |
9329 | ||
9330 | vcpu->arch.pending_external_vector = -1; | |
9331 | vcpu->arch.preempted_in_kernel = false; | |
9332 | ||
9333 | kvm_hv_vcpu_init(vcpu); | |
9334 | ||
9335 | r = kvm_x86_ops->vcpu_create(vcpu); | |
9336 | if (r) | |
9337 | goto free_guest_fpu; | |
e9b11c17 | 9338 | |
0cf9135b | 9339 | vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); |
e53d88af | 9340 | vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; |
19efffa2 | 9341 | kvm_vcpu_mtrr_init(vcpu); |
ec7660cc | 9342 | vcpu_load(vcpu); |
d28bc9dd | 9343 | kvm_vcpu_reset(vcpu, false); |
e1732991 | 9344 | kvm_init_mmu(vcpu, false); |
e9b11c17 | 9345 | vcpu_put(vcpu); |
ec7660cc | 9346 | return 0; |
95a0d01e SC |
9347 | |
9348 | free_guest_fpu: | |
9349 | kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu); | |
9350 | free_user_fpu: | |
9351 | kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); | |
9352 | free_wbinvd_dirty_mask: | |
9353 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); | |
9354 | fail_free_mce_banks: | |
9355 | kfree(vcpu->arch.mce_banks); | |
9356 | fail_free_pio_data: | |
9357 | free_page((unsigned long)vcpu->arch.pio_data); | |
9358 | fail_free_lapic: | |
9359 | kvm_free_lapic(vcpu); | |
9360 | fail_mmu_destroy: | |
9361 | kvm_mmu_destroy(vcpu); | |
9362 | return r; | |
e9b11c17 ZX |
9363 | } |
9364 | ||
31928aa5 | 9365 | void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) |
42897d86 | 9366 | { |
8fe8ab46 | 9367 | struct msr_data msr; |
332967a3 | 9368 | struct kvm *kvm = vcpu->kvm; |
42897d86 | 9369 | |
d3457c87 RK |
9370 | kvm_hv_vcpu_postcreate(vcpu); |
9371 | ||
ec7660cc | 9372 | if (mutex_lock_killable(&vcpu->mutex)) |
31928aa5 | 9373 | return; |
ec7660cc | 9374 | vcpu_load(vcpu); |
8fe8ab46 WA |
9375 | msr.data = 0x0; |
9376 | msr.index = MSR_IA32_TSC; | |
9377 | msr.host_initiated = true; | |
9378 | kvm_write_tsc(vcpu, &msr); | |
42897d86 | 9379 | vcpu_put(vcpu); |
2d5ba19b MT |
9380 | |
9381 | /* poll control enabled by default */ | |
9382 | vcpu->arch.msr_kvm_poll_control = 1; | |
9383 | ||
ec7660cc | 9384 | mutex_unlock(&vcpu->mutex); |
42897d86 | 9385 | |
630994b3 MT |
9386 | if (!kvmclock_periodic_sync) |
9387 | return; | |
9388 | ||
332967a3 AJ |
9389 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, |
9390 | KVMCLOCK_SYNC_PERIOD); | |
42897d86 MT |
9391 | } |
9392 | ||
d40ccc62 | 9393 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 | 9394 | { |
4cbc418a | 9395 | struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache; |
95a0d01e | 9396 | int idx; |
344d9588 | 9397 | |
4cbc418a PB |
9398 | kvm_release_pfn(cache->pfn, cache->dirty, cache); |
9399 | ||
50b143e1 | 9400 | kvmclock_reset(vcpu); |
e9b11c17 ZX |
9401 | |
9402 | kvm_x86_ops->vcpu_free(vcpu); | |
50b143e1 | 9403 | |
50b143e1 SC |
9404 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); |
9405 | kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); | |
9406 | kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu); | |
95a0d01e SC |
9407 | |
9408 | kvm_hv_vcpu_uninit(vcpu); | |
9409 | kvm_pmu_destroy(vcpu); | |
9410 | kfree(vcpu->arch.mce_banks); | |
9411 | kvm_free_lapic(vcpu); | |
9412 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
9413 | kvm_mmu_destroy(vcpu); | |
9414 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
9415 | free_page((unsigned long)vcpu->arch.pio_data); | |
9416 | if (!lapic_in_kernel(vcpu)) | |
9417 | static_key_slow_dec(&kvm_no_apic_vcpu); | |
e9b11c17 ZX |
9418 | } |
9419 | ||
d28bc9dd | 9420 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
e9b11c17 | 9421 | { |
b7e31be3 RK |
9422 | kvm_lapic_reset(vcpu, init_event); |
9423 | ||
e69fab5d PB |
9424 | vcpu->arch.hflags = 0; |
9425 | ||
c43203ca | 9426 | vcpu->arch.smi_pending = 0; |
52797bf9 | 9427 | vcpu->arch.smi_count = 0; |
7460fb4a AK |
9428 | atomic_set(&vcpu->arch.nmi_queued, 0); |
9429 | vcpu->arch.nmi_pending = 0; | |
448fa4a9 | 9430 | vcpu->arch.nmi_injected = false; |
5f7552d4 NA |
9431 | kvm_clear_interrupt_queue(vcpu); |
9432 | kvm_clear_exception_queue(vcpu); | |
448fa4a9 | 9433 | |
42dbaa5a | 9434 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); |
ae561ede | 9435 | kvm_update_dr0123(vcpu); |
6f43ed01 | 9436 | vcpu->arch.dr6 = DR6_INIT; |
73aaf249 | 9437 | kvm_update_dr6(vcpu); |
42dbaa5a | 9438 | vcpu->arch.dr7 = DR7_FIXED_1; |
c8639010 | 9439 | kvm_update_dr7(vcpu); |
42dbaa5a | 9440 | |
1119022c NA |
9441 | vcpu->arch.cr2 = 0; |
9442 | ||
3842d135 | 9443 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
344d9588 | 9444 | vcpu->arch.apf.msr_val = 0; |
c9aaa895 | 9445 | vcpu->arch.st.msr_val = 0; |
3842d135 | 9446 | |
12f9a48f GC |
9447 | kvmclock_reset(vcpu); |
9448 | ||
af585b92 GN |
9449 | kvm_clear_async_pf_completion_queue(vcpu); |
9450 | kvm_async_pf_hash_reset(vcpu); | |
9451 | vcpu->arch.apf.halted = false; | |
3842d135 | 9452 | |
a554d207 WL |
9453 | if (kvm_mpx_supported()) { |
9454 | void *mpx_state_buffer; | |
9455 | ||
9456 | /* | |
9457 | * To avoid have the INIT path from kvm_apic_has_events() that be | |
9458 | * called with loaded FPU and does not let userspace fix the state. | |
9459 | */ | |
f775b13e RR |
9460 | if (init_event) |
9461 | kvm_put_guest_fpu(vcpu); | |
b666a4b6 | 9462 | mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, |
abd16d68 | 9463 | XFEATURE_BNDREGS); |
a554d207 WL |
9464 | if (mpx_state_buffer) |
9465 | memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state)); | |
b666a4b6 | 9466 | mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, |
abd16d68 | 9467 | XFEATURE_BNDCSR); |
a554d207 WL |
9468 | if (mpx_state_buffer) |
9469 | memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr)); | |
f775b13e RR |
9470 | if (init_event) |
9471 | kvm_load_guest_fpu(vcpu); | |
a554d207 WL |
9472 | } |
9473 | ||
64d60670 | 9474 | if (!init_event) { |
d28bc9dd | 9475 | kvm_pmu_reset(vcpu); |
64d60670 | 9476 | vcpu->arch.smbase = 0x30000; |
db2336a8 | 9477 | |
db2336a8 | 9478 | vcpu->arch.msr_misc_features_enables = 0; |
a554d207 WL |
9479 | |
9480 | vcpu->arch.xcr0 = XFEATURE_MASK_FP; | |
64d60670 | 9481 | } |
f5132b01 | 9482 | |
66f7b72e JS |
9483 | memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); |
9484 | vcpu->arch.regs_avail = ~0; | |
9485 | vcpu->arch.regs_dirty = ~0; | |
9486 | ||
a554d207 WL |
9487 | vcpu->arch.ia32_xss = 0; |
9488 | ||
d28bc9dd | 9489 | kvm_x86_ops->vcpu_reset(vcpu, init_event); |
e9b11c17 ZX |
9490 | } |
9491 | ||
2b4a273b | 9492 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) |
66450a21 JK |
9493 | { |
9494 | struct kvm_segment cs; | |
9495 | ||
9496 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
9497 | cs.selector = vector << 8; | |
9498 | cs.base = vector << 12; | |
9499 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
9500 | kvm_rip_write(vcpu, 0); | |
e9b11c17 ZX |
9501 | } |
9502 | ||
13a34e06 | 9503 | int kvm_arch_hardware_enable(void) |
e9b11c17 | 9504 | { |
ca84d1a2 ZA |
9505 | struct kvm *kvm; |
9506 | struct kvm_vcpu *vcpu; | |
9507 | int i; | |
0dd6a6ed ZA |
9508 | int ret; |
9509 | u64 local_tsc; | |
9510 | u64 max_tsc = 0; | |
9511 | bool stable, backwards_tsc = false; | |
18863bdd AK |
9512 | |
9513 | kvm_shared_msr_cpu_online(); | |
13a34e06 | 9514 | ret = kvm_x86_ops->hardware_enable(); |
0dd6a6ed ZA |
9515 | if (ret != 0) |
9516 | return ret; | |
9517 | ||
4ea1636b | 9518 | local_tsc = rdtsc(); |
b0c39dc6 | 9519 | stable = !kvm_check_tsc_unstable(); |
0dd6a6ed ZA |
9520 | list_for_each_entry(kvm, &vm_list, vm_list) { |
9521 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
9522 | if (!stable && vcpu->cpu == smp_processor_id()) | |
105b21bb | 9523 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
9524 | if (stable && vcpu->arch.last_host_tsc > local_tsc) { |
9525 | backwards_tsc = true; | |
9526 | if (vcpu->arch.last_host_tsc > max_tsc) | |
9527 | max_tsc = vcpu->arch.last_host_tsc; | |
9528 | } | |
9529 | } | |
9530 | } | |
9531 | ||
9532 | /* | |
9533 | * Sometimes, even reliable TSCs go backwards. This happens on | |
9534 | * platforms that reset TSC during suspend or hibernate actions, but | |
9535 | * maintain synchronization. We must compensate. Fortunately, we can | |
9536 | * detect that condition here, which happens early in CPU bringup, | |
9537 | * before any KVM threads can be running. Unfortunately, we can't | |
9538 | * bring the TSCs fully up to date with real time, as we aren't yet far | |
9539 | * enough into CPU bringup that we know how much real time has actually | |
9285ec4c | 9540 | * elapsed; our helper function, ktime_get_boottime_ns() will be using boot |
0dd6a6ed ZA |
9541 | * variables that haven't been updated yet. |
9542 | * | |
9543 | * So we simply find the maximum observed TSC above, then record the | |
9544 | * adjustment to TSC in each VCPU. When the VCPU later gets loaded, | |
9545 | * the adjustment will be applied. Note that we accumulate | |
9546 | * adjustments, in case multiple suspend cycles happen before some VCPU | |
9547 | * gets a chance to run again. In the event that no KVM threads get a | |
9548 | * chance to run, we will miss the entire elapsed period, as we'll have | |
9549 | * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may | |
9550 | * loose cycle time. This isn't too big a deal, since the loss will be | |
9551 | * uniform across all VCPUs (not to mention the scenario is extremely | |
9552 | * unlikely). It is possible that a second hibernate recovery happens | |
9553 | * much faster than a first, causing the observed TSC here to be | |
9554 | * smaller; this would require additional padding adjustment, which is | |
9555 | * why we set last_host_tsc to the local tsc observed here. | |
9556 | * | |
9557 | * N.B. - this code below runs only on platforms with reliable TSC, | |
9558 | * as that is the only way backwards_tsc is set above. Also note | |
9559 | * that this runs for ALL vcpus, which is not a bug; all VCPUs should | |
9560 | * have the same delta_cyc adjustment applied if backwards_tsc | |
9561 | * is detected. Note further, this adjustment is only done once, | |
9562 | * as we reset last_host_tsc on all VCPUs to stop this from being | |
9563 | * called multiple times (one for each physical CPU bringup). | |
9564 | * | |
4a969980 | 9565 | * Platforms with unreliable TSCs don't have to deal with this, they |
0dd6a6ed ZA |
9566 | * will be compensated by the logic in vcpu_load, which sets the TSC to |
9567 | * catchup mode. This will catchup all VCPUs to real time, but cannot | |
9568 | * guarantee that they stay in perfect synchronization. | |
9569 | */ | |
9570 | if (backwards_tsc) { | |
9571 | u64 delta_cyc = max_tsc - local_tsc; | |
9572 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
a826faf1 | 9573 | kvm->arch.backwards_tsc_observed = true; |
0dd6a6ed ZA |
9574 | kvm_for_each_vcpu(i, vcpu, kvm) { |
9575 | vcpu->arch.tsc_offset_adjustment += delta_cyc; | |
9576 | vcpu->arch.last_host_tsc = local_tsc; | |
105b21bb | 9577 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
9578 | } |
9579 | ||
9580 | /* | |
9581 | * We have to disable TSC offset matching.. if you were | |
9582 | * booting a VM while issuing an S4 host suspend.... | |
9583 | * you may have some problem. Solving this issue is | |
9584 | * left as an exercise to the reader. | |
9585 | */ | |
9586 | kvm->arch.last_tsc_nsec = 0; | |
9587 | kvm->arch.last_tsc_write = 0; | |
9588 | } | |
9589 | ||
9590 | } | |
9591 | return 0; | |
e9b11c17 ZX |
9592 | } |
9593 | ||
13a34e06 | 9594 | void kvm_arch_hardware_disable(void) |
e9b11c17 | 9595 | { |
13a34e06 RK |
9596 | kvm_x86_ops->hardware_disable(); |
9597 | drop_user_return_notifiers(); | |
e9b11c17 ZX |
9598 | } |
9599 | ||
9600 | int kvm_arch_hardware_setup(void) | |
9601 | { | |
9e9c3fe4 NA |
9602 | int r; |
9603 | ||
9604 | r = kvm_x86_ops->hardware_setup(); | |
9605 | if (r != 0) | |
9606 | return r; | |
9607 | ||
b11306b5 SC |
9608 | cr4_reserved_bits = kvm_host_cr4_reserved_bits(&boot_cpu_data); |
9609 | ||
35181e86 HZ |
9610 | if (kvm_has_tsc_control) { |
9611 | /* | |
9612 | * Make sure the user can only configure tsc_khz values that | |
9613 | * fit into a signed integer. | |
273ba457 | 9614 | * A min value is not calculated because it will always |
35181e86 HZ |
9615 | * be 1 on all machines. |
9616 | */ | |
9617 | u64 max = min(0x7fffffffULL, | |
9618 | __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); | |
9619 | kvm_max_guest_tsc_khz = max; | |
9620 | ||
ad721883 | 9621 | kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; |
35181e86 | 9622 | } |
ad721883 | 9623 | |
139a12cf AL |
9624 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
9625 | rdmsrl(MSR_IA32_XSS, host_xss); | |
9626 | ||
9e9c3fe4 NA |
9627 | kvm_init_msr_list(); |
9628 | return 0; | |
e9b11c17 ZX |
9629 | } |
9630 | ||
9631 | void kvm_arch_hardware_unsetup(void) | |
9632 | { | |
9633 | kvm_x86_ops->hardware_unsetup(); | |
9634 | } | |
9635 | ||
f257d6dc | 9636 | int kvm_arch_check_processor_compat(void) |
e9b11c17 | 9637 | { |
f1cdecf5 SC |
9638 | struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); |
9639 | ||
9640 | WARN_ON(!irqs_disabled()); | |
9641 | ||
9642 | if (kvm_host_cr4_reserved_bits(c) != cr4_reserved_bits) | |
9643 | return -EIO; | |
9644 | ||
f257d6dc | 9645 | return kvm_x86_ops->check_processor_compatibility(); |
d71ba788 PB |
9646 | } |
9647 | ||
9648 | bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) | |
9649 | { | |
9650 | return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; | |
9651 | } | |
9652 | EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); | |
9653 | ||
9654 | bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) | |
9655 | { | |
9656 | return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; | |
e9b11c17 ZX |
9657 | } |
9658 | ||
54e9818f | 9659 | struct static_key kvm_no_apic_vcpu __read_mostly; |
bce87cce | 9660 | EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu); |
54e9818f | 9661 | |
e790d9ef RK |
9662 | void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) |
9663 | { | |
b35e5548 LX |
9664 | struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); |
9665 | ||
c595ceee | 9666 | vcpu->arch.l1tf_flush_l1d = true; |
b35e5548 LX |
9667 | if (pmu->version && unlikely(pmu->event_count)) { |
9668 | pmu->need_cleanup = true; | |
9669 | kvm_make_request(KVM_REQ_PMU, vcpu); | |
9670 | } | |
ae97a3b8 | 9671 | kvm_x86_ops->sched_in(vcpu, cpu); |
e790d9ef RK |
9672 | } |
9673 | ||
e08b9637 | 9674 | int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) |
d19a9cd2 | 9675 | { |
e08b9637 CO |
9676 | if (type) |
9677 | return -EINVAL; | |
9678 | ||
6ef768fa | 9679 | INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); |
f05e70ac | 9680 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
10605204 | 9681 | INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); |
1aa9b957 | 9682 | INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages); |
4d5c5d0f | 9683 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
e0f0bbc5 | 9684 | atomic_set(&kvm->arch.noncoherent_dma_count, 0); |
d19a9cd2 | 9685 | |
5550af4d SY |
9686 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
9687 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
7a84428a AW |
9688 | /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ |
9689 | set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, | |
9690 | &kvm->arch.irq_sources_bitmap); | |
5550af4d | 9691 | |
038f8c11 | 9692 | raw_spin_lock_init(&kvm->arch.tsc_write_lock); |
1e08ec4a | 9693 | mutex_init(&kvm->arch.apic_map_lock); |
d828199e MT |
9694 | spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); |
9695 | ||
9285ec4c | 9696 | kvm->arch.kvmclock_offset = -ktime_get_boottime_ns(); |
d828199e | 9697 | pvclock_update_vm_gtod_copy(kvm); |
53f658b3 | 9698 | |
6fbbde9a DS |
9699 | kvm->arch.guest_can_read_msr_platform_info = true; |
9700 | ||
7e44e449 | 9701 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); |
332967a3 | 9702 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); |
7e44e449 | 9703 | |
cbc0236a | 9704 | kvm_hv_init_vm(kvm); |
0eb05bf2 | 9705 | kvm_page_track_init(kvm); |
13d268ca | 9706 | kvm_mmu_init_vm(kvm); |
0eb05bf2 | 9707 | |
92735b1b | 9708 | return kvm_x86_ops->vm_init(kvm); |
d19a9cd2 ZX |
9709 | } |
9710 | ||
1aa9b957 JS |
9711 | int kvm_arch_post_init_vm(struct kvm *kvm) |
9712 | { | |
9713 | return kvm_mmu_post_init_vm(kvm); | |
9714 | } | |
9715 | ||
d19a9cd2 ZX |
9716 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) |
9717 | { | |
ec7660cc | 9718 | vcpu_load(vcpu); |
d19a9cd2 ZX |
9719 | kvm_mmu_unload(vcpu); |
9720 | vcpu_put(vcpu); | |
9721 | } | |
9722 | ||
9723 | static void kvm_free_vcpus(struct kvm *kvm) | |
9724 | { | |
9725 | unsigned int i; | |
988a2cae | 9726 | struct kvm_vcpu *vcpu; |
d19a9cd2 ZX |
9727 | |
9728 | /* | |
9729 | * Unpin any mmu pages first. | |
9730 | */ | |
af585b92 GN |
9731 | kvm_for_each_vcpu(i, vcpu, kvm) { |
9732 | kvm_clear_async_pf_completion_queue(vcpu); | |
988a2cae | 9733 | kvm_unload_vcpu_mmu(vcpu); |
af585b92 | 9734 | } |
988a2cae | 9735 | kvm_for_each_vcpu(i, vcpu, kvm) |
4543bdc0 | 9736 | kvm_vcpu_destroy(vcpu); |
988a2cae GN |
9737 | |
9738 | mutex_lock(&kvm->lock); | |
9739 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
9740 | kvm->vcpus[i] = NULL; | |
d19a9cd2 | 9741 | |
988a2cae GN |
9742 | atomic_set(&kvm->online_vcpus, 0); |
9743 | mutex_unlock(&kvm->lock); | |
d19a9cd2 ZX |
9744 | } |
9745 | ||
ad8ba2cd SY |
9746 | void kvm_arch_sync_events(struct kvm *kvm) |
9747 | { | |
332967a3 | 9748 | cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); |
7e44e449 | 9749 | cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); |
aea924f6 | 9750 | kvm_free_pit(kvm); |
ad8ba2cd SY |
9751 | } |
9752 | ||
1d8007bd | 9753 | int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) |
9da0e4d5 PB |
9754 | { |
9755 | int i, r; | |
25188b99 | 9756 | unsigned long hva; |
f0d648bd PB |
9757 | struct kvm_memslots *slots = kvm_memslots(kvm); |
9758 | struct kvm_memory_slot *slot, old; | |
9da0e4d5 PB |
9759 | |
9760 | /* Called with kvm->slots_lock held. */ | |
1d8007bd PB |
9761 | if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) |
9762 | return -EINVAL; | |
9da0e4d5 | 9763 | |
f0d648bd PB |
9764 | slot = id_to_memslot(slots, id); |
9765 | if (size) { | |
b21629da | 9766 | if (slot->npages) |
f0d648bd PB |
9767 | return -EEXIST; |
9768 | ||
9769 | /* | |
9770 | * MAP_SHARED to prevent internal slot pages from being moved | |
9771 | * by fork()/COW. | |
9772 | */ | |
9773 | hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, | |
9774 | MAP_SHARED | MAP_ANONYMOUS, 0); | |
9775 | if (IS_ERR((void *)hva)) | |
9776 | return PTR_ERR((void *)hva); | |
9777 | } else { | |
9778 | if (!slot->npages) | |
9779 | return 0; | |
9780 | ||
9781 | hva = 0; | |
9782 | } | |
9783 | ||
9784 | old = *slot; | |
9da0e4d5 | 9785 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
1d8007bd | 9786 | struct kvm_userspace_memory_region m; |
9da0e4d5 | 9787 | |
1d8007bd PB |
9788 | m.slot = id | (i << 16); |
9789 | m.flags = 0; | |
9790 | m.guest_phys_addr = gpa; | |
f0d648bd | 9791 | m.userspace_addr = hva; |
1d8007bd | 9792 | m.memory_size = size; |
9da0e4d5 PB |
9793 | r = __kvm_set_memory_region(kvm, &m); |
9794 | if (r < 0) | |
9795 | return r; | |
9796 | } | |
9797 | ||
103c763c EB |
9798 | if (!size) |
9799 | vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE); | |
f0d648bd | 9800 | |
9da0e4d5 PB |
9801 | return 0; |
9802 | } | |
9803 | EXPORT_SYMBOL_GPL(__x86_set_memory_region); | |
9804 | ||
1aa9b957 JS |
9805 | void kvm_arch_pre_destroy_vm(struct kvm *kvm) |
9806 | { | |
9807 | kvm_mmu_pre_destroy_vm(kvm); | |
9808 | } | |
9809 | ||
d19a9cd2 ZX |
9810 | void kvm_arch_destroy_vm(struct kvm *kvm) |
9811 | { | |
27469d29 AH |
9812 | if (current->mm == kvm->mm) { |
9813 | /* | |
9814 | * Free memory regions allocated on behalf of userspace, | |
9815 | * unless the the memory map has changed due to process exit | |
9816 | * or fd copying. | |
9817 | */ | |
6a3c623b PX |
9818 | mutex_lock(&kvm->slots_lock); |
9819 | __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, | |
9820 | 0, 0); | |
9821 | __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, | |
9822 | 0, 0); | |
9823 | __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); | |
9824 | mutex_unlock(&kvm->slots_lock); | |
27469d29 | 9825 | } |
03543133 SS |
9826 | if (kvm_x86_ops->vm_destroy) |
9827 | kvm_x86_ops->vm_destroy(kvm); | |
c761159c PX |
9828 | kvm_pic_destroy(kvm); |
9829 | kvm_ioapic_destroy(kvm); | |
d19a9cd2 | 9830 | kvm_free_vcpus(kvm); |
af1bae54 | 9831 | kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); |
66bb8a06 | 9832 | kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); |
13d268ca | 9833 | kvm_mmu_uninit_vm(kvm); |
2beb6dad | 9834 | kvm_page_track_cleanup(kvm); |
cbc0236a | 9835 | kvm_hv_destroy_vm(kvm); |
d19a9cd2 | 9836 | } |
0de10343 | 9837 | |
5587027c | 9838 | void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, |
db3fe4eb TY |
9839 | struct kvm_memory_slot *dont) |
9840 | { | |
9841 | int i; | |
9842 | ||
d89cc617 TY |
9843 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
9844 | if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { | |
548ef284 | 9845 | kvfree(free->arch.rmap[i]); |
d89cc617 | 9846 | free->arch.rmap[i] = NULL; |
77d11309 | 9847 | } |
d89cc617 TY |
9848 | if (i == 0) |
9849 | continue; | |
9850 | ||
9851 | if (!dont || free->arch.lpage_info[i - 1] != | |
9852 | dont->arch.lpage_info[i - 1]) { | |
548ef284 | 9853 | kvfree(free->arch.lpage_info[i - 1]); |
d89cc617 | 9854 | free->arch.lpage_info[i - 1] = NULL; |
db3fe4eb TY |
9855 | } |
9856 | } | |
21ebbeda XG |
9857 | |
9858 | kvm_page_track_free_memslot(free, dont); | |
db3fe4eb TY |
9859 | } |
9860 | ||
5587027c AK |
9861 | int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, |
9862 | unsigned long npages) | |
db3fe4eb TY |
9863 | { |
9864 | int i; | |
9865 | ||
d89cc617 | 9866 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
92f94f1e | 9867 | struct kvm_lpage_info *linfo; |
db3fe4eb TY |
9868 | unsigned long ugfn; |
9869 | int lpages; | |
d89cc617 | 9870 | int level = i + 1; |
db3fe4eb TY |
9871 | |
9872 | lpages = gfn_to_index(slot->base_gfn + npages - 1, | |
9873 | slot->base_gfn, level) + 1; | |
9874 | ||
d89cc617 | 9875 | slot->arch.rmap[i] = |
778e1cdd | 9876 | kvcalloc(lpages, sizeof(*slot->arch.rmap[i]), |
254272ce | 9877 | GFP_KERNEL_ACCOUNT); |
d89cc617 | 9878 | if (!slot->arch.rmap[i]) |
77d11309 | 9879 | goto out_free; |
d89cc617 TY |
9880 | if (i == 0) |
9881 | continue; | |
77d11309 | 9882 | |
254272ce | 9883 | linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); |
92f94f1e | 9884 | if (!linfo) |
db3fe4eb TY |
9885 | goto out_free; |
9886 | ||
92f94f1e XG |
9887 | slot->arch.lpage_info[i - 1] = linfo; |
9888 | ||
db3fe4eb | 9889 | if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 9890 | linfo[0].disallow_lpage = 1; |
db3fe4eb | 9891 | if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 9892 | linfo[lpages - 1].disallow_lpage = 1; |
db3fe4eb TY |
9893 | ugfn = slot->userspace_addr >> PAGE_SHIFT; |
9894 | /* | |
9895 | * If the gfn and userspace address are not aligned wrt each | |
9896 | * other, or if explicitly asked to, disable large page | |
9897 | * support for this slot | |
9898 | */ | |
9899 | if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || | |
9900 | !kvm_largepages_enabled()) { | |
9901 | unsigned long j; | |
9902 | ||
9903 | for (j = 0; j < lpages; ++j) | |
92f94f1e | 9904 | linfo[j].disallow_lpage = 1; |
db3fe4eb TY |
9905 | } |
9906 | } | |
9907 | ||
21ebbeda XG |
9908 | if (kvm_page_track_create_memslot(slot, npages)) |
9909 | goto out_free; | |
9910 | ||
db3fe4eb TY |
9911 | return 0; |
9912 | ||
9913 | out_free: | |
d89cc617 | 9914 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
548ef284 | 9915 | kvfree(slot->arch.rmap[i]); |
d89cc617 TY |
9916 | slot->arch.rmap[i] = NULL; |
9917 | if (i == 0) | |
9918 | continue; | |
9919 | ||
548ef284 | 9920 | kvfree(slot->arch.lpage_info[i - 1]); |
d89cc617 | 9921 | slot->arch.lpage_info[i - 1] = NULL; |
db3fe4eb TY |
9922 | } |
9923 | return -ENOMEM; | |
9924 | } | |
9925 | ||
15248258 | 9926 | void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) |
e59dbe09 | 9927 | { |
91724814 BO |
9928 | struct kvm_vcpu *vcpu; |
9929 | int i; | |
9930 | ||
e6dff7d1 TY |
9931 | /* |
9932 | * memslots->generation has been incremented. | |
9933 | * mmio generation may have reached its maximum value. | |
9934 | */ | |
15248258 | 9935 | kvm_mmu_invalidate_mmio_sptes(kvm, gen); |
91724814 BO |
9936 | |
9937 | /* Force re-initialization of steal_time cache */ | |
9938 | kvm_for_each_vcpu(i, vcpu, kvm) | |
9939 | kvm_vcpu_kick(vcpu); | |
e59dbe09 TY |
9940 | } |
9941 | ||
f7784b8e MT |
9942 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
9943 | struct kvm_memory_slot *memslot, | |
09170a49 | 9944 | const struct kvm_userspace_memory_region *mem, |
7b6195a9 | 9945 | enum kvm_mr_change change) |
0de10343 | 9946 | { |
f7784b8e MT |
9947 | return 0; |
9948 | } | |
9949 | ||
88178fd4 KH |
9950 | static void kvm_mmu_slot_apply_flags(struct kvm *kvm, |
9951 | struct kvm_memory_slot *new) | |
9952 | { | |
9953 | /* Still write protect RO slot */ | |
9954 | if (new->flags & KVM_MEM_READONLY) { | |
9955 | kvm_mmu_slot_remove_write_access(kvm, new); | |
9956 | return; | |
9957 | } | |
9958 | ||
9959 | /* | |
9960 | * Call kvm_x86_ops dirty logging hooks when they are valid. | |
9961 | * | |
9962 | * kvm_x86_ops->slot_disable_log_dirty is called when: | |
9963 | * | |
9964 | * - KVM_MR_CREATE with dirty logging is disabled | |
9965 | * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag | |
9966 | * | |
9967 | * The reason is, in case of PML, we need to set D-bit for any slots | |
9968 | * with dirty logging disabled in order to eliminate unnecessary GPA | |
0a03cbda | 9969 | * logging in PML buffer (and potential PML buffer full VMEXIT). This |
88178fd4 | 9970 | * guarantees leaving PML enabled during guest's lifetime won't have |
bdd303cb | 9971 | * any additional overhead from PML when guest is running with dirty |
88178fd4 KH |
9972 | * logging disabled for memory slots. |
9973 | * | |
9974 | * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot | |
9975 | * to dirty logging mode. | |
9976 | * | |
9977 | * If kvm_x86_ops dirty logging hooks are invalid, use write protect. | |
9978 | * | |
9979 | * In case of write protect: | |
9980 | * | |
9981 | * Write protect all pages for dirty logging. | |
9982 | * | |
9983 | * All the sptes including the large sptes which point to this | |
9984 | * slot are set to readonly. We can not create any new large | |
9985 | * spte on this slot until the end of the logging. | |
9986 | * | |
9987 | * See the comments in fast_page_fault(). | |
9988 | */ | |
9989 | if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { | |
9990 | if (kvm_x86_ops->slot_enable_log_dirty) | |
9991 | kvm_x86_ops->slot_enable_log_dirty(kvm, new); | |
9992 | else | |
9993 | kvm_mmu_slot_remove_write_access(kvm, new); | |
9994 | } else { | |
9995 | if (kvm_x86_ops->slot_disable_log_dirty) | |
9996 | kvm_x86_ops->slot_disable_log_dirty(kvm, new); | |
9997 | } | |
9998 | } | |
9999 | ||
f7784b8e | 10000 | void kvm_arch_commit_memory_region(struct kvm *kvm, |
09170a49 | 10001 | const struct kvm_userspace_memory_region *mem, |
8482644a | 10002 | const struct kvm_memory_slot *old, |
f36f3f28 | 10003 | const struct kvm_memory_slot *new, |
8482644a | 10004 | enum kvm_mr_change change) |
f7784b8e | 10005 | { |
48c0e4e9 | 10006 | if (!kvm->arch.n_requested_mmu_pages) |
4d66623c WY |
10007 | kvm_mmu_change_mmu_pages(kvm, |
10008 | kvm_mmu_calculate_default_mmu_pages(kvm)); | |
1c91cad4 | 10009 | |
3ea3b7fa WL |
10010 | /* |
10011 | * Dirty logging tracks sptes in 4k granularity, meaning that large | |
10012 | * sptes have to be split. If live migration is successful, the guest | |
10013 | * in the source machine will be destroyed and large sptes will be | |
10014 | * created in the destination. However, if the guest continues to run | |
10015 | * in the source machine (for example if live migration fails), small | |
10016 | * sptes will remain around and cause bad performance. | |
10017 | * | |
10018 | * Scan sptes if dirty logging has been stopped, dropping those | |
10019 | * which can be collapsed into a single large-page spte. Later | |
10020 | * page faults will create the large-page sptes. | |
319109a2 SC |
10021 | * |
10022 | * There is no need to do this in any of the following cases: | |
10023 | * CREATE: No dirty mappings will already exist. | |
10024 | * MOVE/DELETE: The old mappings will already have been cleaned up by | |
10025 | * kvm_arch_flush_shadow_memslot() | |
3ea3b7fa | 10026 | */ |
319109a2 | 10027 | if (change == KVM_MR_FLAGS_ONLY && |
3ea3b7fa WL |
10028 | (old->flags & KVM_MEM_LOG_DIRTY_PAGES) && |
10029 | !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) | |
10030 | kvm_mmu_zap_collapsible_sptes(kvm, new); | |
10031 | ||
c972f3b1 | 10032 | /* |
88178fd4 | 10033 | * Set up write protection and/or dirty logging for the new slot. |
c126d94f | 10034 | * |
88178fd4 KH |
10035 | * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have |
10036 | * been zapped so no dirty logging staff is needed for old slot. For | |
10037 | * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the | |
10038 | * new and it's also covered when dealing with the new slot. | |
f36f3f28 PB |
10039 | * |
10040 | * FIXME: const-ify all uses of struct kvm_memory_slot. | |
c972f3b1 | 10041 | */ |
88178fd4 | 10042 | if (change != KVM_MR_DELETE) |
f36f3f28 | 10043 | kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new); |
0de10343 | 10044 | } |
1d737c8a | 10045 | |
2df72e9b | 10046 | void kvm_arch_flush_shadow_all(struct kvm *kvm) |
34d4cb8f | 10047 | { |
7390de1e | 10048 | kvm_mmu_zap_all(kvm); |
34d4cb8f MT |
10049 | } |
10050 | ||
2df72e9b MT |
10051 | void kvm_arch_flush_shadow_memslot(struct kvm *kvm, |
10052 | struct kvm_memory_slot *slot) | |
10053 | { | |
ae7cd873 | 10054 | kvm_page_track_flush_slot(kvm, slot); |
2df72e9b MT |
10055 | } |
10056 | ||
e6c67d8c LA |
10057 | static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) |
10058 | { | |
10059 | return (is_guest_mode(vcpu) && | |
10060 | kvm_x86_ops->guest_apic_has_interrupt && | |
10061 | kvm_x86_ops->guest_apic_has_interrupt(vcpu)); | |
10062 | } | |
10063 | ||
5d9bc648 PB |
10064 | static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) |
10065 | { | |
10066 | if (!list_empty_careful(&vcpu->async_pf.done)) | |
10067 | return true; | |
10068 | ||
10069 | if (kvm_apic_has_events(vcpu)) | |
10070 | return true; | |
10071 | ||
10072 | if (vcpu->arch.pv.pv_unhalted) | |
10073 | return true; | |
10074 | ||
a5f01f8e WL |
10075 | if (vcpu->arch.exception.pending) |
10076 | return true; | |
10077 | ||
47a66eed Z |
10078 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || |
10079 | (vcpu->arch.nmi_pending && | |
10080 | kvm_x86_ops->nmi_allowed(vcpu))) | |
5d9bc648 PB |
10081 | return true; |
10082 | ||
47a66eed Z |
10083 | if (kvm_test_request(KVM_REQ_SMI, vcpu) || |
10084 | (vcpu->arch.smi_pending && !is_smm(vcpu))) | |
73917739 PB |
10085 | return true; |
10086 | ||
5d9bc648 | 10087 | if (kvm_arch_interrupt_allowed(vcpu) && |
e6c67d8c LA |
10088 | (kvm_cpu_has_interrupt(vcpu) || |
10089 | kvm_guest_apic_has_interrupt(vcpu))) | |
5d9bc648 PB |
10090 | return true; |
10091 | ||
1f4b34f8 AS |
10092 | if (kvm_hv_has_stimer_pending(vcpu)) |
10093 | return true; | |
10094 | ||
5d9bc648 PB |
10095 | return false; |
10096 | } | |
10097 | ||
1d737c8a ZX |
10098 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
10099 | { | |
5d9bc648 | 10100 | return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); |
1d737c8a | 10101 | } |
5736199a | 10102 | |
17e433b5 WL |
10103 | bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) |
10104 | { | |
10105 | if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) | |
10106 | return true; | |
10107 | ||
10108 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || | |
10109 | kvm_test_request(KVM_REQ_SMI, vcpu) || | |
10110 | kvm_test_request(KVM_REQ_EVENT, vcpu)) | |
10111 | return true; | |
10112 | ||
10113 | if (vcpu->arch.apicv_active && kvm_x86_ops->dy_apicv_has_pending_interrupt(vcpu)) | |
10114 | return true; | |
10115 | ||
10116 | return false; | |
10117 | } | |
10118 | ||
199b5763 LM |
10119 | bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) |
10120 | { | |
de63ad4c | 10121 | return vcpu->arch.preempted_in_kernel; |
199b5763 LM |
10122 | } |
10123 | ||
b6d33834 | 10124 | int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) |
5736199a | 10125 | { |
b6d33834 | 10126 | return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; |
5736199a | 10127 | } |
78646121 GN |
10128 | |
10129 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
10130 | { | |
10131 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
10132 | } | |
229456fc | 10133 | |
82b32774 | 10134 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) |
f92653ee | 10135 | { |
82b32774 NA |
10136 | if (is_64_bit_mode(vcpu)) |
10137 | return kvm_rip_read(vcpu); | |
10138 | return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + | |
10139 | kvm_rip_read(vcpu)); | |
10140 | } | |
10141 | EXPORT_SYMBOL_GPL(kvm_get_linear_rip); | |
f92653ee | 10142 | |
82b32774 NA |
10143 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) |
10144 | { | |
10145 | return kvm_get_linear_rip(vcpu) == linear_rip; | |
f92653ee JK |
10146 | } |
10147 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
10148 | ||
94fe45da JK |
10149 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
10150 | { | |
10151 | unsigned long rflags; | |
10152 | ||
10153 | rflags = kvm_x86_ops->get_rflags(vcpu); | |
10154 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
c310bac5 | 10155 | rflags &= ~X86_EFLAGS_TF; |
94fe45da JK |
10156 | return rflags; |
10157 | } | |
10158 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
10159 | ||
6addfc42 | 10160 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) |
94fe45da JK |
10161 | { |
10162 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
f92653ee | 10163 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) |
c310bac5 | 10164 | rflags |= X86_EFLAGS_TF; |
94fe45da | 10165 | kvm_x86_ops->set_rflags(vcpu, rflags); |
6addfc42 PB |
10166 | } |
10167 | ||
10168 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
10169 | { | |
10170 | __kvm_set_rflags(vcpu, rflags); | |
3842d135 | 10171 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
94fe45da JK |
10172 | } |
10173 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
10174 | ||
56028d08 GN |
10175 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) |
10176 | { | |
10177 | int r; | |
10178 | ||
44dd3ffa | 10179 | if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) || |
f2e10669 | 10180 | work->wakeup_all) |
56028d08 GN |
10181 | return; |
10182 | ||
10183 | r = kvm_mmu_reload(vcpu); | |
10184 | if (unlikely(r)) | |
10185 | return; | |
10186 | ||
44dd3ffa VK |
10187 | if (!vcpu->arch.mmu->direct_map && |
10188 | work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu)) | |
fb67e14f XG |
10189 | return; |
10190 | ||
736c291c | 10191 | vcpu->arch.mmu->page_fault(vcpu, work->cr2_or_gpa, 0, true); |
56028d08 GN |
10192 | } |
10193 | ||
af585b92 GN |
10194 | static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) |
10195 | { | |
10196 | return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); | |
10197 | } | |
10198 | ||
10199 | static inline u32 kvm_async_pf_next_probe(u32 key) | |
10200 | { | |
10201 | return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); | |
10202 | } | |
10203 | ||
10204 | static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
10205 | { | |
10206 | u32 key = kvm_async_pf_hash_fn(gfn); | |
10207 | ||
10208 | while (vcpu->arch.apf.gfns[key] != ~0) | |
10209 | key = kvm_async_pf_next_probe(key); | |
10210 | ||
10211 | vcpu->arch.apf.gfns[key] = gfn; | |
10212 | } | |
10213 | ||
10214 | static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) | |
10215 | { | |
10216 | int i; | |
10217 | u32 key = kvm_async_pf_hash_fn(gfn); | |
10218 | ||
10219 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && | |
c7d28c24 XG |
10220 | (vcpu->arch.apf.gfns[key] != gfn && |
10221 | vcpu->arch.apf.gfns[key] != ~0); i++) | |
af585b92 GN |
10222 | key = kvm_async_pf_next_probe(key); |
10223 | ||
10224 | return key; | |
10225 | } | |
10226 | ||
10227 | bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
10228 | { | |
10229 | return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; | |
10230 | } | |
10231 | ||
10232 | static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
10233 | { | |
10234 | u32 i, j, k; | |
10235 | ||
10236 | i = j = kvm_async_pf_gfn_slot(vcpu, gfn); | |
10237 | while (true) { | |
10238 | vcpu->arch.apf.gfns[i] = ~0; | |
10239 | do { | |
10240 | j = kvm_async_pf_next_probe(j); | |
10241 | if (vcpu->arch.apf.gfns[j] == ~0) | |
10242 | return; | |
10243 | k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); | |
10244 | /* | |
10245 | * k lies cyclically in ]i,j] | |
10246 | * | i.k.j | | |
10247 | * |....j i.k.| or |.k..j i...| | |
10248 | */ | |
10249 | } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); | |
10250 | vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; | |
10251 | i = j; | |
10252 | } | |
10253 | } | |
10254 | ||
7c90705b GN |
10255 | static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) |
10256 | { | |
4e335d9e PB |
10257 | |
10258 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, | |
10259 | sizeof(val)); | |
7c90705b GN |
10260 | } |
10261 | ||
9a6e7c39 WL |
10262 | static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val) |
10263 | { | |
10264 | ||
10265 | return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val, | |
10266 | sizeof(u32)); | |
10267 | } | |
10268 | ||
1dfdb45e PB |
10269 | static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) |
10270 | { | |
10271 | if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu)) | |
10272 | return false; | |
10273 | ||
10274 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || | |
10275 | (vcpu->arch.apf.send_user_only && | |
10276 | kvm_x86_ops->get_cpl(vcpu) == 0)) | |
10277 | return false; | |
10278 | ||
10279 | return true; | |
10280 | } | |
10281 | ||
10282 | bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) | |
10283 | { | |
10284 | if (unlikely(!lapic_in_kernel(vcpu) || | |
10285 | kvm_event_needs_reinjection(vcpu) || | |
10286 | vcpu->arch.exception.pending)) | |
10287 | return false; | |
10288 | ||
10289 | if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) | |
10290 | return false; | |
10291 | ||
10292 | /* | |
10293 | * If interrupts are off we cannot even use an artificial | |
10294 | * halt state. | |
10295 | */ | |
10296 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
10297 | } | |
10298 | ||
af585b92 GN |
10299 | void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
10300 | struct kvm_async_pf *work) | |
10301 | { | |
6389ee94 AK |
10302 | struct x86_exception fault; |
10303 | ||
736c291c | 10304 | trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa); |
af585b92 | 10305 | kvm_add_async_pf_gfn(vcpu, work->arch.gfn); |
7c90705b | 10306 | |
1dfdb45e PB |
10307 | if (kvm_can_deliver_async_pf(vcpu) && |
10308 | !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { | |
6389ee94 AK |
10309 | fault.vector = PF_VECTOR; |
10310 | fault.error_code_valid = true; | |
10311 | fault.error_code = 0; | |
10312 | fault.nested_page_fault = false; | |
10313 | fault.address = work->arch.token; | |
adfe20fb | 10314 | fault.async_page_fault = true; |
6389ee94 | 10315 | kvm_inject_page_fault(vcpu, &fault); |
1dfdb45e PB |
10316 | } else { |
10317 | /* | |
10318 | * It is not possible to deliver a paravirtualized asynchronous | |
10319 | * page fault, but putting the guest in an artificial halt state | |
10320 | * can be beneficial nevertheless: if an interrupt arrives, we | |
10321 | * can deliver it timely and perhaps the guest will schedule | |
10322 | * another process. When the instruction that triggered a page | |
10323 | * fault is retried, hopefully the page will be ready in the host. | |
10324 | */ | |
10325 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
7c90705b | 10326 | } |
af585b92 GN |
10327 | } |
10328 | ||
10329 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
10330 | struct kvm_async_pf *work) | |
10331 | { | |
6389ee94 | 10332 | struct x86_exception fault; |
9a6e7c39 | 10333 | u32 val; |
6389ee94 | 10334 | |
f2e10669 | 10335 | if (work->wakeup_all) |
7c90705b GN |
10336 | work->arch.token = ~0; /* broadcast wakeup */ |
10337 | else | |
10338 | kvm_del_async_pf_gfn(vcpu, work->arch.gfn); | |
736c291c | 10339 | trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa); |
7c90705b | 10340 | |
9a6e7c39 WL |
10341 | if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED && |
10342 | !apf_get_user(vcpu, &val)) { | |
10343 | if (val == KVM_PV_REASON_PAGE_NOT_PRESENT && | |
10344 | vcpu->arch.exception.pending && | |
10345 | vcpu->arch.exception.nr == PF_VECTOR && | |
10346 | !apf_put_user(vcpu, 0)) { | |
10347 | vcpu->arch.exception.injected = false; | |
10348 | vcpu->arch.exception.pending = false; | |
10349 | vcpu->arch.exception.nr = 0; | |
10350 | vcpu->arch.exception.has_error_code = false; | |
10351 | vcpu->arch.exception.error_code = 0; | |
c851436a JM |
10352 | vcpu->arch.exception.has_payload = false; |
10353 | vcpu->arch.exception.payload = 0; | |
9a6e7c39 WL |
10354 | } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { |
10355 | fault.vector = PF_VECTOR; | |
10356 | fault.error_code_valid = true; | |
10357 | fault.error_code = 0; | |
10358 | fault.nested_page_fault = false; | |
10359 | fault.address = work->arch.token; | |
10360 | fault.async_page_fault = true; | |
10361 | kvm_inject_page_fault(vcpu, &fault); | |
10362 | } | |
7c90705b | 10363 | } |
e6d53e3b | 10364 | vcpu->arch.apf.halted = false; |
a4fa1635 | 10365 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
7c90705b GN |
10366 | } |
10367 | ||
10368 | bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) | |
10369 | { | |
10370 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) | |
10371 | return true; | |
10372 | else | |
9bc1f09f | 10373 | return kvm_can_do_async_pf(vcpu); |
af585b92 GN |
10374 | } |
10375 | ||
5544eb9b PB |
10376 | void kvm_arch_start_assignment(struct kvm *kvm) |
10377 | { | |
10378 | atomic_inc(&kvm->arch.assigned_device_count); | |
10379 | } | |
10380 | EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); | |
10381 | ||
10382 | void kvm_arch_end_assignment(struct kvm *kvm) | |
10383 | { | |
10384 | atomic_dec(&kvm->arch.assigned_device_count); | |
10385 | } | |
10386 | EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); | |
10387 | ||
10388 | bool kvm_arch_has_assigned_device(struct kvm *kvm) | |
10389 | { | |
10390 | return atomic_read(&kvm->arch.assigned_device_count); | |
10391 | } | |
10392 | EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); | |
10393 | ||
e0f0bbc5 AW |
10394 | void kvm_arch_register_noncoherent_dma(struct kvm *kvm) |
10395 | { | |
10396 | atomic_inc(&kvm->arch.noncoherent_dma_count); | |
10397 | } | |
10398 | EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); | |
10399 | ||
10400 | void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) | |
10401 | { | |
10402 | atomic_dec(&kvm->arch.noncoherent_dma_count); | |
10403 | } | |
10404 | EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); | |
10405 | ||
10406 | bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) | |
10407 | { | |
10408 | return atomic_read(&kvm->arch.noncoherent_dma_count); | |
10409 | } | |
10410 | EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); | |
10411 | ||
14717e20 AW |
10412 | bool kvm_arch_has_irq_bypass(void) |
10413 | { | |
92735b1b | 10414 | return true; |
14717e20 AW |
10415 | } |
10416 | ||
87276880 FW |
10417 | int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, |
10418 | struct irq_bypass_producer *prod) | |
10419 | { | |
10420 | struct kvm_kernel_irqfd *irqfd = | |
10421 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
10422 | ||
14717e20 | 10423 | irqfd->producer = prod; |
87276880 | 10424 | |
14717e20 AW |
10425 | return kvm_x86_ops->update_pi_irte(irqfd->kvm, |
10426 | prod->irq, irqfd->gsi, 1); | |
87276880 FW |
10427 | } |
10428 | ||
10429 | void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, | |
10430 | struct irq_bypass_producer *prod) | |
10431 | { | |
10432 | int ret; | |
10433 | struct kvm_kernel_irqfd *irqfd = | |
10434 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
10435 | ||
87276880 FW |
10436 | WARN_ON(irqfd->producer != prod); |
10437 | irqfd->producer = NULL; | |
10438 | ||
10439 | /* | |
10440 | * When producer of consumer is unregistered, we change back to | |
10441 | * remapped mode, so we can re-use the current implementation | |
bb3541f1 | 10442 | * when the irq is masked/disabled or the consumer side (KVM |
87276880 FW |
10443 | * int this case doesn't want to receive the interrupts. |
10444 | */ | |
10445 | ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0); | |
10446 | if (ret) | |
10447 | printk(KERN_INFO "irq bypass consumer (token %p) unregistration" | |
10448 | " fails: %d\n", irqfd->consumer.token, ret); | |
10449 | } | |
10450 | ||
10451 | int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, | |
10452 | uint32_t guest_irq, bool set) | |
10453 | { | |
87276880 FW |
10454 | return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set); |
10455 | } | |
10456 | ||
52004014 FW |
10457 | bool kvm_vector_hashing_enabled(void) |
10458 | { | |
10459 | return vector_hashing; | |
10460 | } | |
52004014 | 10461 | |
2d5ba19b MT |
10462 | bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) |
10463 | { | |
10464 | return (vcpu->arch.msr_kvm_poll_control & 1) == 0; | |
10465 | } | |
10466 | EXPORT_SYMBOL_GPL(kvm_arch_no_poll); | |
10467 | ||
6441fa61 PB |
10468 | u64 kvm_spec_ctrl_valid_bits(struct kvm_vcpu *vcpu) |
10469 | { | |
10470 | uint64_t bits = SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD; | |
10471 | ||
10472 | /* The STIBP bit doesn't fault even if it's not advertised */ | |
10473 | if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) && | |
10474 | !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS)) | |
10475 | bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP); | |
10476 | if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL) && | |
10477 | !boot_cpu_has(X86_FEATURE_AMD_IBRS)) | |
10478 | bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP); | |
10479 | ||
10480 | if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL_SSBD) && | |
10481 | !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD)) | |
10482 | bits &= ~SPEC_CTRL_SSBD; | |
10483 | if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) && | |
10484 | !boot_cpu_has(X86_FEATURE_AMD_SSBD)) | |
10485 | bits &= ~SPEC_CTRL_SSBD; | |
10486 | ||
10487 | return bits; | |
10488 | } | |
10489 | EXPORT_SYMBOL_GPL(kvm_spec_ctrl_valid_bits); | |
2d5ba19b | 10490 | |
229456fc | 10491 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
931c33b1 | 10492 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); |
229456fc MT |
10493 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); |
10494 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
10495 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
10496 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
0ac406de | 10497 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); |
d8cabddf | 10498 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 10499 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 10500 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
5497b955 | 10501 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); |
ec1ff790 | 10502 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 10503 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |
2e554e8d | 10504 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); |
489223ed | 10505 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); |
4f75bcc3 | 10506 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); |
843e4330 | 10507 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); |
efc64404 | 10508 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); |
18f40c53 SS |
10509 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); |
10510 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); | |
24bbf74c | 10511 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request); |