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kvm: vmx: Defer setting of DR6 until #DB delivery
[mirror_ubuntu-focal-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
b0c39dc6 70#include <asm/mshyperv.h>
0092e434 71#include <asm/hypervisor.h>
043405e1 72
d1898b73
DH		 73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
313a3dc7 76#define MAX_IO_MSRS 256
890ca9ae 77#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 80
0f65dd70
AK		 81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
50a37eb4
JR		 84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
1260edbe
LJ		 89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 91#else
1260edbe 92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 93#endif
313a3dc7 94
ba1389b7
AK		 95#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 97
c519265f
RK		 98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 100
cb142eb7 101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 102static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 103static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 105static void store_regs(struct kvm_vcpu *vcpu);
106static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 107
893590c7 108struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 109EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 110
893590c7 111static bool __read_mostly ignore_msrs = 0;
476bc001 112module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 113
fab0aa3b
EM		 114static bool __read_mostly report_ignored_msrs = true;
115module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
116
4c27625b 117unsigned int min_timer_period_us = 200;
9ed96e87
MT		 118module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
119
630994b3
MT		 120static bool __read_mostly kvmclock_periodic_sync = true;
121module_param(kvmclock_periodic_sync, bool, S_IRUGO);
122
893590c7 123bool __read_mostly kvm_has_tsc_control;
92a1f12d 124EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 125u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 126EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 127u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129u64 __read_mostly kvm_max_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 131u64 __read_mostly kvm_default_tsc_scaling_ratio;
132EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 133
cc578287 134/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 135static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 136module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
137
d0659d94 138/* lapic timer advance (tscdeadline mode only) in nanoseconds */
3b8a5df6 139unsigned int __read_mostly lapic_timer_advance_ns = 1000;
d0659d94 140module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
c5ce8235 141EXPORT_SYMBOL_GPL(lapic_timer_advance_ns);
d0659d94 142
52004014
FW		 143static bool __read_mostly vector_hashing = true;
144module_param(vector_hashing, bool, S_IRUGO);
145
c4ae60e4
LA		 146bool __read_mostly enable_vmware_backdoor = false;
147module_param(enable_vmware_backdoor, bool, S_IRUGO);
148EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
149
6c86eedc
WL		 150static bool __read_mostly force_emulation_prefix = false;
151module_param(force_emulation_prefix, bool, S_IRUGO);
152
18863bdd
AK		 153#define KVM_NR_SHARED_MSRS 16
154
155struct kvm_shared_msrs_global {
156 int nr;
2bf78fa7 157 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 158};
159
160struct kvm_shared_msrs {
161 struct user_return_notifier urn;
162 bool registered;
2bf78fa7
SY		 163 struct kvm_shared_msr_values {
164 u64 host;
165 u64 curr;
166 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 167};
168
169static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 170static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 171
417bc304 172struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 173 { "pf_fixed", VCPU_STAT(pf_fixed) },
174 { "pf_guest", VCPU_STAT(pf_guest) },
175 { "tlb_flush", VCPU_STAT(tlb_flush) },
176 { "invlpg", VCPU_STAT(invlpg) },
177 { "exits", VCPU_STAT(exits) },
178 { "io_exits", VCPU_STAT(io_exits) },
179 { "mmio_exits", VCPU_STAT(mmio_exits) },
180 { "signal_exits", VCPU_STAT(signal_exits) },
181 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 182 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 183 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 184 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 185 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 186 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 187 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 188 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 189 { "request_irq", VCPU_STAT(request_irq_exits) },
190 { "irq_exits", VCPU_STAT(irq_exits) },
191 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 192 { "fpu_reload", VCPU_STAT(fpu_reload) },
193 { "insn_emulation", VCPU_STAT(insn_emulation) },
194 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 195 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 196 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 197 { "req_event", VCPU_STAT(req_event) },
c595ceee 198 { "l1d_flush", VCPU_STAT(l1d_flush) },
4cee5764
AK		 199 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
200 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
201 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
202 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
203 { "mmu_flooded", VM_STAT(mmu_flooded) },
204 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 205 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 206 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 207 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 208 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 209 { "max_mmu_page_hash_collisions",
210 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 211 { NULL }
212};
213
2acf923e
DC		 214u64 __read_mostly host_xcr0;
215
b6785def 216static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 217
af585b92
GN		 218static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
219{
220 int i;
221 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
222 vcpu->arch.apf.gfns[i] = ~0;
223}
224
18863bdd
AK		 225static void kvm_on_user_return(struct user_return_notifier *urn)
226{
227 unsigned slot;
18863bdd
AK		 228 struct kvm_shared_msrs *locals
229 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 230 struct kvm_shared_msr_values *values;
1650b4eb
IA		 231 unsigned long flags;
232
233 /*
234 * Disabling irqs at this point since the following code could be
235 * interrupted and executed through kvm_arch_hardware_disable()
236 */
237 local_irq_save(flags);
238 if (locals->registered) {
239 locals->registered = false;
240 user_return_notifier_unregister(urn);
241 }
242 local_irq_restore(flags);
18863bdd 243 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 244 values = &locals->values[slot];
245 if (values->host != values->curr) {
246 wrmsrl(shared_msrs_global.msrs[slot], values->host);
247 values->curr = values->host;
18863bdd
AK		 248 }
249 }
18863bdd
AK		 250}
251
2bf78fa7 252static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 253{
18863bdd 254 u64 value;
013f6a5d
MT		 255 unsigned int cpu = smp_processor_id();
256 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 257
2bf78fa7
SY		 258 /* only read, and nobody should modify it at this time,
259 * so don't need lock */
260 if (slot >= shared_msrs_global.nr) {
261 printk(KERN_ERR "kvm: invalid MSR slot!");
262 return;
263 }
264 rdmsrl_safe(msr, &value);
265 smsr->values[slot].host = value;
266 smsr->values[slot].curr = value;
267}
268
269void kvm_define_shared_msr(unsigned slot, u32 msr)
270{
0123be42 271 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 272 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 273 if (slot >= shared_msrs_global.nr)
274 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 275}
276EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
277
278static void kvm_shared_msr_cpu_online(void)
279{
280 unsigned i;
18863bdd
AK		 281
282 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 283 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 284}
285
8b3c3104 286int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 287{
013f6a5d
MT		 288 unsigned int cpu = smp_processor_id();
289 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 290 int err;
18863bdd 291
2bf78fa7 292 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 293 return 0;
2bf78fa7 294 smsr->values[slot].curr = value;
8b3c3104
AH		 295 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
296 if (err)
297 return 1;
298
18863bdd
AK		 299 if (!smsr->registered) {
300 smsr->urn.on_user_return = kvm_on_user_return;
301 user_return_notifier_register(&smsr->urn);
302 smsr->registered = true;
303 }
8b3c3104 304 return 0;
18863bdd
AK		 305}
306EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
307
13a34e06 308static void drop_user_return_notifiers(void)
3548bab5 309{
013f6a5d
MT		 310 unsigned int cpu = smp_processor_id();
311 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 312
313 if (smsr->registered)
314 kvm_on_user_return(&smsr->urn);
315}
316
6866b83e
CO		 317u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
318{
8a5a87d9 319 return vcpu->arch.apic_base;
6866b83e
CO		 320}
321EXPORT_SYMBOL_GPL(kvm_get_apic_base);
322
58871649
JM		 323enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
324{
325 return kvm_apic_mode(kvm_get_apic_base(vcpu));
326}
327EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
328
58cb628d
JK		 329int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
330{
58871649
JM		 331 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
332 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
d6321d49
RK		 333 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
334 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 335
58871649 336 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
58cb628d 337 return 1;
58871649
JM		 338 if (!msr_info->host_initiated) {
339 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
340 return 1;
341 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
342 return 1;
343 }
58cb628d
JK		 344
345 kvm_lapic_set_base(vcpu, msr_info->data);
346 return 0;
6866b83e
CO		 347}
348EXPORT_SYMBOL_GPL(kvm_set_apic_base);
349
2605fc21 350asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 351{
352 /* Fault while not rebooting. We want the trace. */
353 BUG();
354}
355EXPORT_SYMBOL_GPL(kvm_spurious_fault);
356
3fd28fce
ED		 357#define EXCPT_BENIGN 0
358#define EXCPT_CONTRIBUTORY 1
359#define EXCPT_PF 2
360
361static int exception_class(int vector)
362{
363 switch (vector) {
364 case PF_VECTOR:
365 return EXCPT_PF;
366 case DE_VECTOR:
367 case TS_VECTOR:
368 case NP_VECTOR:
369 case SS_VECTOR:
370 case GP_VECTOR:
371 return EXCPT_CONTRIBUTORY;
372 default:
373 break;
374 }
375 return EXCPT_BENIGN;
376}
377
d6e8c854
NA		 378#define EXCPT_FAULT 0
379#define EXCPT_TRAP 1
380#define EXCPT_ABORT 2
381#define EXCPT_INTERRUPT 3
382
383static int exception_type(int vector)
384{
385 unsigned int mask;
386
387 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
388 return EXCPT_INTERRUPT;
389
390 mask = 1 << vector;
391
392 /* #DB is trap, as instruction watchpoints are handled elsewhere */
393 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
394 return EXCPT_TRAP;
395
396 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
397 return EXCPT_ABORT;
398
399 /* Reserved exceptions will result in fault */
400 return EXCPT_FAULT;
401}
402
da998b46
JM		 403void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
404{
405 unsigned nr = vcpu->arch.exception.nr;
406 bool has_payload = vcpu->arch.exception.has_payload;
407 unsigned long payload = vcpu->arch.exception.payload;
408
409 if (!has_payload)
410 return;
411
412 switch (nr) {
f10c729f
JM		 413 case DB_VECTOR:
414 /*
415 * "Certain debug exceptions may clear bit 0-3. The
416 * remaining contents of the DR6 register are never
417 * cleared by the processor".
418 */
419 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
420 /*
421 * DR6.RTM is set by all #DB exceptions that don't clear it.
422 */
423 vcpu->arch.dr6 |= DR6_RTM;
424 vcpu->arch.dr6 |= payload;
425 /*
426 * Bit 16 should be set in the payload whenever the #DB
427 * exception should clear DR6.RTM. This makes the payload
428 * compatible with the pending debug exceptions under VMX.
429 * Though not currently documented in the SDM, this also
430 * makes the payload compatible with the exit qualification
431 * for #DB exceptions under VMX.
432 */
433 vcpu->arch.dr6 ^= payload & DR6_RTM;
434 break;
da998b46
JM		 435 case PF_VECTOR:
436 vcpu->arch.cr2 = payload;
437 break;
438 }
439
440 vcpu->arch.exception.has_payload = false;
441 vcpu->arch.exception.payload = 0;
442}
443EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
444
3fd28fce 445static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4 446 unsigned nr, bool has_error, u32 error_code,
91e86d22 447 bool has_payload, unsigned long payload, bool reinject)
3fd28fce
ED		 448{
449 u32 prev_nr;
450 int class1, class2;
451
3842d135
AK		 452 kvm_make_request(KVM_REQ_EVENT, vcpu);
453
664f8e26 454 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 455 queue:
3ffb2468
NA		 456 if (has_error && !is_protmode(vcpu))
457 has_error = false;
664f8e26
WL		 458 if (reinject) {
459 /*
460 * On vmentry, vcpu->arch.exception.pending is only
461 * true if an event injection was blocked by
462 * nested_run_pending. In that case, however,
463 * vcpu_enter_guest requests an immediate exit,
464 * and the guest shouldn't proceed far enough to
465 * need reinjection.
466 */
467 WARN_ON_ONCE(vcpu->arch.exception.pending);
468 vcpu->arch.exception.injected = true;
91e86d22
JM		 469 if (WARN_ON_ONCE(has_payload)) {
470 /*
471 * A reinjected event has already
472 * delivered its payload.
473 */
474 has_payload = false;
475 payload = 0;
476 }
664f8e26
WL		 477 } else {
478 vcpu->arch.exception.pending = true;
479 vcpu->arch.exception.injected = false;
480 }
3fd28fce
ED		 481 vcpu->arch.exception.has_error_code = has_error;
482 vcpu->arch.exception.nr = nr;
483 vcpu->arch.exception.error_code = error_code;
91e86d22
JM		 484 vcpu->arch.exception.has_payload = has_payload;
485 vcpu->arch.exception.payload = payload;
da998b46
JM		 486 /*
487 * In guest mode, payload delivery should be deferred,
488 * so that the L1 hypervisor can intercept #PF before
f10c729f
JM		 489 * CR2 is modified (or intercept #DB before DR6 is
490 * modified under nVMX). However, for ABI
491 * compatibility with KVM_GET_VCPU_EVENTS and
492 * KVM_SET_VCPU_EVENTS, we can't delay payload
493 * delivery unless userspace has enabled this
494 * functionality via the per-VM capability,
495 * KVM_CAP_EXCEPTION_PAYLOAD.
da998b46
JM		 496 */
497 if (!vcpu->kvm->arch.exception_payload_enabled ||
498 !is_guest_mode(vcpu))
499 kvm_deliver_exception_payload(vcpu);
3fd28fce
ED		 500 return;
501 }
502
503 /* to check exception */
504 prev_nr = vcpu->arch.exception.nr;
505 if (prev_nr == DF_VECTOR) {
506 /* triple fault -> shutdown */
a8eeb04a 507 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 508 return;
509 }
510 class1 = exception_class(prev_nr);
511 class2 = exception_class(nr);
512 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
513 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 514 /*
515 * Generate double fault per SDM Table 5-5. Set
516 * exception.pending = true so that the double fault
517 * can trigger a nested vmexit.
518 */
3fd28fce 519 vcpu->arch.exception.pending = true;
664f8e26 520 vcpu->arch.exception.injected = false;
3fd28fce
ED		 521 vcpu->arch.exception.has_error_code = true;
522 vcpu->arch.exception.nr = DF_VECTOR;
523 vcpu->arch.exception.error_code = 0;
c851436a
JM		 524 vcpu->arch.exception.has_payload = false;
525 vcpu->arch.exception.payload = 0;
3fd28fce
ED		 526 } else
527 /* replace previous exception with a new one in a hope
528 that instruction re-execution will regenerate lost
529 exception */
530 goto queue;
531}
532
298101da
AK		 533void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
534{
91e86d22 535 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
298101da
AK		 536}
537EXPORT_SYMBOL_GPL(kvm_queue_exception);
538
ce7ddec4
JR		 539void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
540{
91e86d22 541 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
ce7ddec4
JR		 542}
543EXPORT_SYMBOL_GPL(kvm_requeue_exception);
544
f10c729f
JM		 545static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
546 unsigned long payload)
547{
548 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
549}
550
da998b46
JM		 551static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
552 u32 error_code, unsigned long payload)
553{
554 kvm_multiple_exception(vcpu, nr, true, error_code,
555 true, payload, false);
556}
557
6affcbed 558int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 559{
db8fcefa
AP		 560 if (err)
561 kvm_inject_gp(vcpu, 0);
562 else
6affcbed
KH		 563 return kvm_skip_emulated_instruction(vcpu);
564
565 return 1;
db8fcefa
AP		 566}
567EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 568
6389ee94 569void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 570{
571 ++vcpu->stat.pf_guest;
adfe20fb
WL		 572 vcpu->arch.exception.nested_apf =
573 is_guest_mode(vcpu) && fault->async_page_fault;
da998b46 574 if (vcpu->arch.exception.nested_apf) {
adfe20fb 575 vcpu->arch.apf.nested_apf_token = fault->address;
da998b46
JM		 576 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
577 } else {
578 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
579 fault->address);
580 }
c3c91fee 581}
27d6c865 582EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 583
ef54bcfe 584static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 585{
6389ee94
AK		 586 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
587 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 588 else
44dd3ffa 589 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
ef54bcfe
PB		 590
591 return fault->nested_page_fault;
d4f8cf66
JR		 592}
593
3419ffc8
SY		 594void kvm_inject_nmi(struct kvm_vcpu *vcpu)
595{
7460fb4a
AK		 596 atomic_inc(&vcpu->arch.nmi_queued);
597 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 598}
599EXPORT_SYMBOL_GPL(kvm_inject_nmi);
600
298101da
AK		 601void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
602{
91e86d22 603 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
298101da
AK		 604}
605EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
606
ce7ddec4
JR		 607void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
608{
91e86d22 609 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
ce7ddec4
JR		 610}
611EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
612
0a79b009
AK		 613/*
614 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
615 * a #GP and return false.
616 */
617bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 618{
0a79b009
AK		 619 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
620 return true;
621 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
622 return false;
298101da 623}
0a79b009 624EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 625
16f8a6f9
NA		 626bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
627{
628 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
629 return true;
630
631 kvm_queue_exception(vcpu, UD_VECTOR);
632 return false;
633}
634EXPORT_SYMBOL_GPL(kvm_require_dr);
635
ec92fe44
JR		 636/*
637 * This function will be used to read from the physical memory of the currently
54bf36aa 638 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 639 * can read from guest physical or from the guest's guest physical memory.
640 */
641int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
642 gfn_t ngfn, void *data, int offset, int len,
643 u32 access)
644{
54987b7a 645 struct x86_exception exception;
ec92fe44
JR		 646 gfn_t real_gfn;
647 gpa_t ngpa;
648
649 ngpa = gfn_to_gpa(ngfn);
54987b7a 650 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 651 if (real_gfn == UNMAPPED_GVA)
652 return -EFAULT;
653
654 real_gfn = gpa_to_gfn(real_gfn);
655
54bf36aa 656 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 657}
658EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
659
69b0049a 660static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 661 void *data, int offset, int len, u32 access)
662{
663 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
664 data, offset, len, access);
665}
666
a03490ed
CO		 667/*
668 * Load the pae pdptrs. Return true is they are all valid.
669 */
ff03a073 670int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 671{
672 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
673 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
674 int i;
675 int ret;
ff03a073 676 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 677
ff03a073
JR		 678 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
679 offset * sizeof(u64), sizeof(pdpte),
680 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 681 if (ret < 0) {
682 ret = 0;
683 goto out;
684 }
685 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 686 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50 687 (pdpte[i] &
44dd3ffa 688 vcpu->arch.mmu->guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 689 ret = 0;
690 goto out;
691 }
692 }
693 ret = 1;
694
ff03a073 695 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 696 __set_bit(VCPU_EXREG_PDPTR,
697 (unsigned long *)&vcpu->arch.regs_avail);
698 __set_bit(VCPU_EXREG_PDPTR,
699 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 700out:
a03490ed
CO		 701
702 return ret;
703}
cc4b6871 704EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 705
9ed38ffa 706bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 707{
ff03a073 708 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 709 bool changed = true;
3d06b8bf
JR		 710 int offset;
711 gfn_t gfn;
d835dfec
AK		 712 int r;
713
d35b34a9 714 if (is_long_mode(vcpu) || !is_pae(vcpu) || !is_paging(vcpu))
d835dfec
AK		 715 return false;
716
6de4f3ad
AK		 717 if (!test_bit(VCPU_EXREG_PDPTR,
718 (unsigned long *)&vcpu->arch.regs_avail))
719 return true;
720
a512177e
PB		 721 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
722 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 723 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
724 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 725 if (r < 0)
726 goto out;
ff03a073 727 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 728out:
d835dfec
AK		 729
730 return changed;
731}
9ed38ffa 732EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 733
49a9b07e 734int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 735{
aad82703 736 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 737 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 738
f9a48e6a
AK		 739 cr0 |= X86_CR0_ET;
740
ab344828 741#ifdef CONFIG_X86_64
0f12244f
GN		 742 if (cr0 & 0xffffffff00000000UL)
743 return 1;
ab344828
GN		 744#endif
745
746 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 747
0f12244f
GN		 748 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
749 return 1;
a03490ed 750
0f12244f
GN		 751 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
752 return 1;
a03490ed
CO		 753
754 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
755#ifdef CONFIG_X86_64
f6801dff 756 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 757 int cs_db, cs_l;
758
0f12244f
GN		 759 if (!is_pae(vcpu))
760 return 1;
a03490ed 761 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 762 if (cs_l)
763 return 1;
a03490ed
CO		 764 } else
765#endif
ff03a073 766 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 767 kvm_read_cr3(vcpu)))
0f12244f 768 return 1;
a03490ed
CO		 769 }
770
ad756a16
MJ		 771 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
772 return 1;
773
a03490ed 774 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 775
d170c419 776 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 777 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 778 kvm_async_pf_hash_reset(vcpu);
779 }
e5f3f027 780
aad82703
SY		 781 if ((cr0 ^ old_cr0) & update_bits)
782 kvm_mmu_reset_context(vcpu);
b18d5431 783
879ae188
LE		 784 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
785 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
786 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 787 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
788
0f12244f
GN		 789 return 0;
790}
2d3ad1f4 791EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 792
2d3ad1f4 793void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 794{
49a9b07e 795 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 796}
2d3ad1f4 797EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 798
42bdf991
MT		 799static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
800{
801 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
802 !vcpu->guest_xcr0_loaded) {
803 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 804 if (vcpu->arch.xcr0 != host_xcr0)
805 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 806 vcpu->guest_xcr0_loaded = 1;
807 }
808}
809
810static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
811{
812 if (vcpu->guest_xcr0_loaded) {
813 if (vcpu->arch.xcr0 != host_xcr0)
814 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
815 vcpu->guest_xcr0_loaded = 0;
816 }
817}
818
69b0049a 819static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 820{
56c103ec
LJ		 821 u64 xcr0 = xcr;
822 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 823 u64 valid_bits;
2acf923e
DC		 824
825 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
826 if (index != XCR_XFEATURE_ENABLED_MASK)
827 return 1;
d91cab78 828 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 829 return 1;
d91cab78 830 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 831 return 1;
46c34cb0
PB		 832
833 /*
834 * Do not allow the guest to set bits that we do not support
835 * saving. However, xcr0 bit 0 is always set, even if the
836 * emulated CPU does not support XSAVE (see fx_init).
837 */
d91cab78 838 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 839 if (xcr0 & ~valid_bits)
2acf923e 840 return 1;
46c34cb0 841
d91cab78
DH		 842 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
843 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 844 return 1;
845
d91cab78
DH		 846 if (xcr0 & XFEATURE_MASK_AVX512) {
847 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 848 return 1;
d91cab78 849 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 850 return 1;
851 }
2acf923e 852 vcpu->arch.xcr0 = xcr0;
56c103ec 853
d91cab78 854 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 855 kvm_update_cpuid(vcpu);
2acf923e
DC		 856 return 0;
857}
858
859int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
860{
764bcbc5
Z		 861 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
862 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 863 kvm_inject_gp(vcpu, 0);
864 return 1;
865 }
866 return 0;
867}
868EXPORT_SYMBOL_GPL(kvm_set_xcr);
869
a83b29c6 870int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 871{
fc78f519 872 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 873 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 874 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 875
0f12244f
GN		 876 if (cr4 & CR4_RESERVED_BITS)
877 return 1;
a03490ed 878
d6321d49 879 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 880 return 1;
881
d6321d49 882 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 883 return 1;
884
d6321d49 885 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 886 return 1;
887
d6321d49 888 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 889 return 1;
890
d6321d49 891 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 892 return 1;
893
fd8cb433 894 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 895 return 1;
896
ae3e61e1
PB		 897 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
898 return 1;
899
a03490ed 900 if (is_long_mode(vcpu)) {
0f12244f
GN		 901 if (!(cr4 & X86_CR4_PAE))
902 return 1;
a2edf57f
AK		 903 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
904 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 905 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
906 kvm_read_cr3(vcpu)))
0f12244f
GN		 907 return 1;
908
ad756a16 909 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 910 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 911 return 1;
912
913 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
914 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
915 return 1;
916 }
917
5e1746d6 918 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 919 return 1;
a03490ed 920
ad756a16
MJ		 921 if (((cr4 ^ old_cr4) & pdptr_bits) ||
922 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 923 kvm_mmu_reset_context(vcpu);
0f12244f 924
b9baba86 925 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 926 kvm_update_cpuid(vcpu);
2acf923e 927
0f12244f
GN		 928 return 0;
929}
2d3ad1f4 930EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 931
2390218b 932int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 933{
ade61e28 934 bool skip_tlb_flush = false;
ac146235 935#ifdef CONFIG_X86_64
c19986fe
JS		 936 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
937
ade61e28 938 if (pcid_enabled) {
208320ba
JS		 939 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
940 cr3 &= ~X86_CR3_PCID_NOFLUSH;
ade61e28 941 }
ac146235 942#endif
9d88fca7 943
9f8fe504 944 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
956bf353
JS		 945 if (!skip_tlb_flush) {
946 kvm_mmu_sync_roots(vcpu);
ade61e28 947 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
956bf353 948 }
0f12244f 949 return 0;
d835dfec
AK		 950 }
951
d1cd3ce9 952 if (is_long_mode(vcpu) &&
a780a3ea 953 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
d1cd3ce9
YZ		 954 return 1;
955 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 956 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 957 return 1;
a03490ed 958
ade61e28 959 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
0f12244f 960 vcpu->arch.cr3 = cr3;
aff48baa 961 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7c390d35 962
0f12244f
GN		 963 return 0;
964}
2d3ad1f4 965EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 966
eea1cff9 967int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 968{
0f12244f
GN		 969 if (cr8 & CR8_RESERVED_BITS)
970 return 1;
35754c98 971 if (lapic_in_kernel(vcpu))
a03490ed
CO		 972 kvm_lapic_set_tpr(vcpu, cr8);
973 else
ad312c7c 974 vcpu->arch.cr8 = cr8;
0f12244f
GN		 975 return 0;
976}
2d3ad1f4 977EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 978
2d3ad1f4 979unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 980{
35754c98 981 if (lapic_in_kernel(vcpu))
a03490ed
CO		 982 return kvm_lapic_get_cr8(vcpu);
983 else
ad312c7c 984 return vcpu->arch.cr8;
a03490ed 985}
2d3ad1f4 986EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 987
ae561ede
NA		 988static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
989{
990 int i;
991
992 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
993 for (i = 0; i < KVM_NR_DB_REGS; i++)
994 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
995 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
996 }
997}
998
73aaf249
JK		 999static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1000{
1001 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1002 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1003}
1004
c8639010
JK		 1005static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1006{
1007 unsigned long dr7;
1008
1009 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1010 dr7 = vcpu->arch.guest_debug_dr7;
1011 else
1012 dr7 = vcpu->arch.dr7;
1013 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 1014 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1015 if (dr7 & DR7_BP_EN_MASK)
1016 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 1017}
1018
6f43ed01
NA		 1019static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1020{
1021 u64 fixed = DR6_FIXED_1;
1022
d6321d49 1023 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 1024 fixed |= DR6_RTM;
1025 return fixed;
1026}
1027
338dbc97 1028static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 1029{
1030 switch (dr) {
1031 case 0 ... 3:
1032 vcpu->arch.db[dr] = val;
1033 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1034 vcpu->arch.eff_db[dr] = val;
1035 break;
1036 case 4:
020df079
GN		 1037 /* fall through */
1038 case 6:
338dbc97
GN		 1039 if (val & 0xffffffff00000000ULL)
1040 return -1; /* #GP */
6f43ed01 1041 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 1042 kvm_update_dr6(vcpu);
020df079
GN		 1043 break;
1044 case 5:
020df079
GN		 1045 /* fall through */
1046 default: /* 7 */
338dbc97
GN		 1047 if (val & 0xffffffff00000000ULL)
1048 return -1; /* #GP */
020df079 1049 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 1050 kvm_update_dr7(vcpu);
020df079
GN		 1051 break;
1052 }
1053
1054 return 0;
1055}
338dbc97
GN		 1056
1057int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1058{
16f8a6f9 1059 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 1060 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 1061 return 1;
1062 }
1063 return 0;
338dbc97 1064}
020df079
GN		 1065EXPORT_SYMBOL_GPL(kvm_set_dr);
1066
16f8a6f9 1067int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 1068{
1069 switch (dr) {
1070 case 0 ... 3:
1071 *val = vcpu->arch.db[dr];
1072 break;
1073 case 4:
020df079
GN		 1074 /* fall through */
1075 case 6:
73aaf249
JK		 1076 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1077 *val = vcpu->arch.dr6;
1078 else
1079 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 1080 break;
1081 case 5:
020df079
GN		 1082 /* fall through */
1083 default: /* 7 */
1084 *val = vcpu->arch.dr7;
1085 break;
1086 }
338dbc97
GN		 1087 return 0;
1088}
020df079
GN		 1089EXPORT_SYMBOL_GPL(kvm_get_dr);
1090
022cd0e8
AK		 1091bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1092{
1093 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
1094 u64 data;
1095 int err;
1096
c6702c9d 1097 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 1098 if (err)
1099 return err;
1100 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
1101 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
1102 return err;
1103}
1104EXPORT_SYMBOL_GPL(kvm_rdpmc);
1105
043405e1
CO		 1106/*
1107 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1108 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1109 *
1110 * This list is modified at module load time to reflect the
e3267cbb 1111 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1112 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1113 * may depend on host virtualization features rather than host cpu features.
043405e1 1114 */
e3267cbb 1115
043405e1
CO		 1116static u32 msrs_to_save[] = {
1117 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1118 MSR_STAR,
043405e1
CO		 1119#ifdef CONFIG_X86_64
1120 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1121#endif
b3897a49 1122 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1123 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
d28b387f 1124 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
043405e1
CO		 1125};
1126
1127static unsigned num_msrs_to_save;
1128
62ef68bb
PB		 1129static u32 emulated_msrs[] = {
1130 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1131 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1132 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1133 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1134 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1135 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1136 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1137 HV_X64_MSR_RESET,
11c4b1ca 1138 HV_X64_MSR_VP_INDEX,
9eec50b8 1139 HV_X64_MSR_VP_RUNTIME,
5c919412 1140 HV_X64_MSR_SCONTROL,
1f4b34f8 1141 HV_X64_MSR_STIMER0_CONFIG,
d4abc577 1142 HV_X64_MSR_VP_ASSIST_PAGE,
a2e164e7
VK		 1143 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1144 HV_X64_MSR_TSC_EMULATION_STATUS,
1145
1146 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1147 MSR_KVM_PV_EOI_EN,
1148
ba904635 1149 MSR_IA32_TSC_ADJUST,
a3e06bbe 1150 MSR_IA32_TSCDEADLINE,
043405e1 1151 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1152 MSR_IA32_MCG_STATUS,
1153 MSR_IA32_MCG_CTL,
c45dcc71 1154 MSR_IA32_MCG_EXT_CTL,
64d60670 1155 MSR_IA32_SMBASE,
52797bf9 1156 MSR_SMI_COUNT,
db2336a8
KH		 1157 MSR_PLATFORM_INFO,
1158 MSR_MISC_FEATURES_ENABLES,
bc226f07 1159 MSR_AMD64_VIRT_SPEC_CTRL,
043405e1
CO		 1160};
1161
62ef68bb
PB		 1162static unsigned num_emulated_msrs;
1163
801e459a
TL		 1164/*
1165 * List of msr numbers which are used to expose MSR-based features that
1166 * can be used by a hypervisor to validate requested CPU features.
1167 */
1168static u32 msr_based_features[] = {
1389309c
PB		 1169 MSR_IA32_VMX_BASIC,
1170 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1171 MSR_IA32_VMX_PINBASED_CTLS,
1172 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1173 MSR_IA32_VMX_PROCBASED_CTLS,
1174 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1175 MSR_IA32_VMX_EXIT_CTLS,
1176 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1177 MSR_IA32_VMX_ENTRY_CTLS,
1178 MSR_IA32_VMX_MISC,
1179 MSR_IA32_VMX_CR0_FIXED0,
1180 MSR_IA32_VMX_CR0_FIXED1,
1181 MSR_IA32_VMX_CR4_FIXED0,
1182 MSR_IA32_VMX_CR4_FIXED1,
1183 MSR_IA32_VMX_VMCS_ENUM,
1184 MSR_IA32_VMX_PROCBASED_CTLS2,
1185 MSR_IA32_VMX_EPT_VPID_CAP,
1186 MSR_IA32_VMX_VMFUNC,
1187
d1d93fa9 1188 MSR_F10H_DECFG,
518e7b94 1189 MSR_IA32_UCODE_REV,
cd283252 1190 MSR_IA32_ARCH_CAPABILITIES,
801e459a
TL		 1191};
1192
1193static unsigned int num_msr_based_features;
1194
5b76a3cf
PB		 1195u64 kvm_get_arch_capabilities(void)
1196{
1197 u64 data;
1198
1199 rdmsrl_safe(MSR_IA32_ARCH_CAPABILITIES, &data);
1200
1201 /*
1202 * If we're doing cache flushes (either "always" or "cond")
1203 * we will do one whenever the guest does a vmlaunch/vmresume.
1204 * If an outer hypervisor is doing the cache flush for us
1205 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1206 * capability to the guest too, and if EPT is disabled we're not
1207 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1208 * require a nested hypervisor to do a flush of its own.
1209 */
1210 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1211 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1212
1213 return data;
1214}
1215EXPORT_SYMBOL_GPL(kvm_get_arch_capabilities);
1216
66421c1e
WL		 1217static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1218{
1219 switch (msr->index) {
cd283252 1220 case MSR_IA32_ARCH_CAPABILITIES:
5b76a3cf
PB		 1221 msr->data = kvm_get_arch_capabilities();
1222 break;
1223 case MSR_IA32_UCODE_REV:
cd283252 1224 rdmsrl_safe(msr->index, &msr->data);
518e7b94 1225 break;
66421c1e
WL		 1226 default:
1227 if (kvm_x86_ops->get_msr_feature(msr))
1228 return 1;
1229 }
1230 return 0;
1231}
1232
801e459a
TL		 1233static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1234{
1235 struct kvm_msr_entry msr;
66421c1e 1236 int r;
801e459a
TL		 1237
1238 msr.index = index;
66421c1e
WL		 1239 r = kvm_get_msr_feature(&msr);
1240 if (r)
1241 return r;
801e459a
TL		 1242
1243 *data = msr.data;
1244
1245 return 0;
1246}
1247
384bb783 1248bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1249{
b69e8cae 1250 if (efer & efer_reserved_bits)
384bb783 1251 return false;
15c4a640 1252
1b4d56b8 1253 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1254 return false;
1b2fd70c 1255
1b4d56b8 1256 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1257 return false;
d8017474 1258
384bb783
JK		 1259 return true;
1260}
1261EXPORT_SYMBOL_GPL(kvm_valid_efer);
1262
1263static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1264{
1265 u64 old_efer = vcpu->arch.efer;
1266
1267 if (!kvm_valid_efer(vcpu, efer))
1268 return 1;
1269
1270 if (is_paging(vcpu)
1271 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1272 return 1;
1273
15c4a640 1274 efer &= ~EFER_LMA;
f6801dff 1275 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1276
a3d204e2
SY		 1277 kvm_x86_ops->set_efer(vcpu, efer);
1278
aad82703
SY		 1279 /* Update reserved bits */
1280 if ((efer ^ old_efer) & EFER_NX)
1281 kvm_mmu_reset_context(vcpu);
1282
b69e8cae 1283 return 0;
15c4a640
CO		 1284}
1285
f2b4b7dd
JR		 1286void kvm_enable_efer_bits(u64 mask)
1287{
1288 efer_reserved_bits &= ~mask;
1289}
1290EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1291
15c4a640
CO		 1292/*
1293 * Writes msr value into into the appropriate "register".
1294 * Returns 0 on success, non-0 otherwise.
1295 * Assumes vcpu_load() was already called.
1296 */
8fe8ab46 1297int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1298{
854e8bb1
NA		 1299 switch (msr->index) {
1300 case MSR_FS_BASE:
1301 case MSR_GS_BASE:
1302 case MSR_KERNEL_GS_BASE:
1303 case MSR_CSTAR:
1304 case MSR_LSTAR:
fd8cb433 1305 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1306 return 1;
1307 break;
1308 case MSR_IA32_SYSENTER_EIP:
1309 case MSR_IA32_SYSENTER_ESP:
1310 /*
1311 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1312 * non-canonical address is written on Intel but not on
1313 * AMD (which ignores the top 32-bits, because it does
1314 * not implement 64-bit SYSENTER).
1315 *
1316 * 64-bit code should hence be able to write a non-canonical
1317 * value on AMD. Making the address canonical ensures that
1318 * vmentry does not fail on Intel after writing a non-canonical
1319 * value, and that something deterministic happens if the guest
1320 * invokes 64-bit SYSENTER.
1321 */
fd8cb433 1322 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1323 }
8fe8ab46 1324 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1325}
854e8bb1 1326EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1327
313a3dc7
CO		 1328/*
1329 * Adapt set_msr() to msr_io()'s calling convention
1330 */
609e36d3
PB		 1331static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1332{
1333 struct msr_data msr;
1334 int r;
1335
1336 msr.index = index;
1337 msr.host_initiated = true;
1338 r = kvm_get_msr(vcpu, &msr);
1339 if (r)
1340 return r;
1341
1342 *data = msr.data;
1343 return 0;
1344}
1345
313a3dc7
CO		 1346static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1347{
8fe8ab46
WA		 1348 struct msr_data msr;
1349
1350 msr.data = *data;
1351 msr.index = index;
1352 msr.host_initiated = true;
1353 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1354}
1355
16e8d74d
MT		 1356#ifdef CONFIG_X86_64
1357struct pvclock_gtod_data {
1358 seqcount_t seq;
1359
1360 struct { /* extract of a clocksource struct */
1361 int vclock_mode;
a5a1d1c2
TG		 1362 u64 cycle_last;
1363 u64 mask;
16e8d74d
MT		 1364 u32 mult;
1365 u32 shift;
1366 } clock;
1367
cbcf2dd3
TG		 1368 u64 boot_ns;
1369 u64 nsec_base;
55dd00a7 1370 u64 wall_time_sec;
16e8d74d
MT		 1371};
1372
1373static struct pvclock_gtod_data pvclock_gtod_data;
1374
1375static void update_pvclock_gtod(struct timekeeper *tk)
1376{
1377 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1378 u64 boot_ns;
1379
876e7881 1380 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1381
1382 write_seqcount_begin(&vdata->seq);
1383
1384 /* copy pvclock gtod data */
876e7881
PZ		 1385 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1386 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1387 vdata->clock.mask = tk->tkr_mono.mask;
1388 vdata->clock.mult = tk->tkr_mono.mult;
1389 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1390
cbcf2dd3 1391 vdata->boot_ns = boot_ns;
876e7881 1392 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1393
55dd00a7
MT		 1394 vdata->wall_time_sec = tk->xtime_sec;
1395
16e8d74d
MT		 1396 write_seqcount_end(&vdata->seq);
1397}
1398#endif
1399
bab5bb39
NK		 1400void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1401{
1402 /*
1403 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1404 * vcpu_enter_guest. This function is only called from
1405 * the physical CPU that is running vcpu.
1406 */
1407 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1408}
16e8d74d 1409
18068523
GOC		 1410static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1411{
9ed3c444
AK		 1412 int version;
1413 int r;
50d0a0f9 1414 struct pvclock_wall_clock wc;
87aeb54f 1415 struct timespec64 boot;
18068523
GOC		 1416
1417 if (!wall_clock)
1418 return;
1419
9ed3c444
AK		 1420 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1421 if (r)
1422 return;
1423
1424 if (version & 1)
1425 ++version; /* first time write, random junk */
1426
1427 ++version;
18068523 1428
1dab1345
NK		 1429 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1430 return;
18068523 1431
50d0a0f9
GH		 1432 /*
1433 * The guest calculates current wall clock time by adding
34c238a1 1434 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1435 * wall clock specified here. guest system time equals host
1436 * system time for us, thus we must fill in host boot time here.
1437 */
87aeb54f 1438 getboottime64(&boot);
50d0a0f9 1439
4b648665 1440 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1441 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1442 boot = timespec64_sub(boot, ts);
4b648665 1443 }
87aeb54f 1444 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1445 wc.nsec = boot.tv_nsec;
1446 wc.version = version;
18068523
GOC		 1447
1448 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1449
1450 version++;
1451 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1452}
1453
50d0a0f9
GH		 1454static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1455{
b51012de
PB		 1456 do_shl32_div32(dividend, divisor);
1457 return dividend;
50d0a0f9
GH		 1458}
1459
3ae13faa 1460static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1461 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1462{
5f4e3f88 1463 uint64_t scaled64;
50d0a0f9
GH		 1464 int32_t shift = 0;
1465 uint64_t tps64;
1466 uint32_t tps32;
1467
3ae13faa
PB		 1468 tps64 = base_hz;
1469 scaled64 = scaled_hz;
50933623 1470 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1471 tps64 >>= 1;
1472 shift--;
1473 }
1474
1475 tps32 = (uint32_t)tps64;
50933623
JK		 1476 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1477 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1478 scaled64 >>= 1;
1479 else
1480 tps32 <<= 1;
50d0a0f9
GH		 1481 shift++;
1482 }
1483
5f4e3f88
ZA		 1484 *pshift = shift;
1485 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1486
3ae13faa
PB		 1487 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1488 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1489}
1490
d828199e 1491#ifdef CONFIG_X86_64
16e8d74d 1492static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1493#endif
16e8d74d 1494
c8076604 1495static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1496static unsigned long max_tsc_khz;
c8076604 1497
cc578287 1498static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1499{
cc578287
ZA		 1500 u64 v = (u64)khz * (1000000 + ppm);
1501 do_div(v, 1000000);
1502 return v;
1e993611
JR		 1503}
1504
381d585c
HZ		 1505static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1506{
1507 u64 ratio;
1508
1509 /* Guest TSC same frequency as host TSC? */
1510 if (!scale) {
1511 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1512 return 0;
1513 }
1514
1515 /* TSC scaling supported? */
1516 if (!kvm_has_tsc_control) {
1517 if (user_tsc_khz > tsc_khz) {
1518 vcpu->arch.tsc_catchup = 1;
1519 vcpu->arch.tsc_always_catchup = 1;
1520 return 0;
1521 } else {
1522 WARN(1, "user requested TSC rate below hardware speed\n");
1523 return -1;
1524 }
1525 }
1526
1527 /* TSC scaling required - calculate ratio */
1528 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1529 user_tsc_khz, tsc_khz);
1530
1531 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1532 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1533 user_tsc_khz);
1534 return -1;
1535 }
1536
1537 vcpu->arch.tsc_scaling_ratio = ratio;
1538 return 0;
1539}
1540
4941b8cb 1541static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1542{
cc578287
ZA		 1543 u32 thresh_lo, thresh_hi;
1544 int use_scaling = 0;
217fc9cf 1545
03ba32ca 1546 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1547 if (user_tsc_khz == 0) {
ad721883
HZ		 1548 /* set tsc_scaling_ratio to a safe value */
1549 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1550 return -1;
ad721883 1551 }
03ba32ca 1552
c285545f 1553 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1554 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1555 &vcpu->arch.virtual_tsc_shift,
1556 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1557 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1558
1559 /*
1560 * Compute the variation in TSC rate which is acceptable
1561 * within the range of tolerance and decide if the
1562 * rate being applied is within that bounds of the hardware
1563 * rate. If so, no scaling or compensation need be done.
1564 */
1565 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1566 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1567 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1568 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1569 use_scaling = 1;
1570 }
4941b8cb 1571 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1572}
1573
1574static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1575{
e26101b1 1576 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1577 vcpu->arch.virtual_tsc_mult,
1578 vcpu->arch.virtual_tsc_shift);
e26101b1 1579 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1580 return tsc;
1581}
1582
b0c39dc6
VK		 1583static inline int gtod_is_based_on_tsc(int mode)
1584{
1585 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1586}
1587
69b0049a 1588static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1589{
1590#ifdef CONFIG_X86_64
1591 bool vcpus_matched;
b48aa97e
MT		 1592 struct kvm_arch *ka = &vcpu->kvm->arch;
1593 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1594
1595 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1596 atomic_read(&vcpu->kvm->online_vcpus));
1597
7f187922
MT		 1598 /*
1599 * Once the masterclock is enabled, always perform request in
1600 * order to update it.
1601 *
1602 * In order to enable masterclock, the host clocksource must be TSC
1603 * and the vcpus need to have matched TSCs. When that happens,
1604 * perform request to enable masterclock.
1605 */
1606 if (ka->use_master_clock ||
b0c39dc6 1607 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1608 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1609
1610 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1611 atomic_read(&vcpu->kvm->online_vcpus),
1612 ka->use_master_clock, gtod->clock.vclock_mode);
1613#endif
1614}
1615
ba904635
WA		 1616static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1617{
e79f245d 1618 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
ba904635
WA		 1619 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1620}
1621
35181e86
HZ		 1622/*
1623 * Multiply tsc by a fixed point number represented by ratio.
1624 *
1625 * The most significant 64-N bits (mult) of ratio represent the
1626 * integral part of the fixed point number; the remaining N bits
1627 * (frac) represent the fractional part, ie. ratio represents a fixed
1628 * point number (mult + frac * 2^(-N)).
1629 *
1630 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1631 */
1632static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1633{
1634 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1635}
1636
1637u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1638{
1639 u64 _tsc = tsc;
1640 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1641
1642 if (ratio != kvm_default_tsc_scaling_ratio)
1643 _tsc = __scale_tsc(ratio, tsc);
1644
1645 return _tsc;
1646}
1647EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1648
07c1419a
HZ		 1649static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1650{
1651 u64 tsc;
1652
1653 tsc = kvm_scale_tsc(vcpu, rdtsc());
1654
1655 return target_tsc - tsc;
1656}
1657
4ba76538
HZ		 1658u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1659{
e79f245d
KA		 1660 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1661
1662 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1663}
1664EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1665
a545ab6a
LC		 1666static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1667{
1668 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1669 vcpu->arch.tsc_offset = offset;
1670}
1671
b0c39dc6
VK		 1672static inline bool kvm_check_tsc_unstable(void)
1673{
1674#ifdef CONFIG_X86_64
1675 /*
1676 * TSC is marked unstable when we're running on Hyper-V,
1677 * 'TSC page' clocksource is good.
1678 */
1679 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1680 return false;
1681#endif
1682 return check_tsc_unstable();
1683}
1684
8fe8ab46 1685void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1686{
1687 struct kvm *kvm = vcpu->kvm;
f38e098f 1688 u64 offset, ns, elapsed;
99e3e30a 1689 unsigned long flags;
b48aa97e 1690 bool matched;
0d3da0d2 1691 bool already_matched;
8fe8ab46 1692 u64 data = msr->data;
c5e8ec8e 1693 bool synchronizing = false;
99e3e30a 1694
038f8c11 1695 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1696 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1697 ns = ktime_get_boot_ns();
f38e098f 1698 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1699
03ba32ca 1700 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1701 if (data == 0 && msr->host_initiated) {
1702 /*
1703 * detection of vcpu initialization -- need to sync
1704 * with other vCPUs. This particularly helps to keep
1705 * kvm_clock stable after CPU hotplug
1706 */
1707 synchronizing = true;
1708 } else {
1709 u64 tsc_exp = kvm->arch.last_tsc_write +
1710 nsec_to_cycles(vcpu, elapsed);
1711 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1712 /*
1713 * Special case: TSC write with a small delta (1 second)
1714 * of virtual cycle time against real time is
1715 * interpreted as an attempt to synchronize the CPU.
1716 */
1717 synchronizing = data < tsc_exp + tsc_hz &&
1718 data + tsc_hz > tsc_exp;
1719 }
c5e8ec8e 1720 }
f38e098f
ZA		 1721
1722 /*
5d3cb0f6
ZA		 1723 * For a reliable TSC, we can match TSC offsets, and for an unstable
1724 * TSC, we add elapsed time in this computation. We could let the
1725 * compensation code attempt to catch up if we fall behind, but
1726 * it's better to try to match offsets from the beginning.
1727 */
c5e8ec8e 1728 if (synchronizing &&
5d3cb0f6 1729 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1730 if (!kvm_check_tsc_unstable()) {
e26101b1 1731 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1732 pr_debug("kvm: matched tsc offset for %llu\n", data);
1733 } else {
857e4099 1734 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1735 data += delta;
07c1419a 1736 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1737 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1738 }
b48aa97e 1739 matched = true;
0d3da0d2 1740 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1741 } else {
1742 /*
1743 * We split periods of matched TSC writes into generations.
1744 * For each generation, we track the original measured
1745 * nanosecond time, offset, and write, so if TSCs are in
1746 * sync, we can match exact offset, and if not, we can match
4a969980 1747 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1748 *
1749 * These values are tracked in kvm->arch.cur_xxx variables.
1750 */
1751 kvm->arch.cur_tsc_generation++;
1752 kvm->arch.cur_tsc_nsec = ns;
1753 kvm->arch.cur_tsc_write = data;
1754 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1755 matched = false;
0d3da0d2 1756 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1757 kvm->arch.cur_tsc_generation, data);
f38e098f 1758 }
e26101b1
ZA		 1759
1760 /*
1761 * We also track th most recent recorded KHZ, write and time to
1762 * allow the matching interval to be extended at each write.
1763 */
f38e098f
ZA		 1764 kvm->arch.last_tsc_nsec = ns;
1765 kvm->arch.last_tsc_write = data;
5d3cb0f6 1766 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1767
b183aa58 1768 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1769
1770 /* Keep track of which generation this VCPU has synchronized to */
1771 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1772 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1773 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1774
d6321d49 1775 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1776 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1777
a545ab6a 1778 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1779 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1780
1781 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1782 if (!matched) {
b48aa97e 1783 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1784 } else if (!already_matched) {
1785 kvm->arch.nr_vcpus_matched_tsc++;
1786 }
b48aa97e
MT		 1787
1788 kvm_track_tsc_matching(vcpu);
1789 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1790}
e26101b1 1791
99e3e30a
ZA		 1792EXPORT_SYMBOL_GPL(kvm_write_tsc);
1793
58ea6767
HZ		 1794static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1795 s64 adjustment)
1796{
ea26e4ec 1797 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1798}
1799
1800static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1801{
1802 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1803 WARN_ON(adjustment < 0);
1804 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1805 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1806}
1807
d828199e
MT		 1808#ifdef CONFIG_X86_64
1809
a5a1d1c2 1810static u64 read_tsc(void)
d828199e 1811{
a5a1d1c2 1812 u64 ret = (u64)rdtsc_ordered();
03b9730b 1813 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1814
1815 if (likely(ret >= last))
1816 return ret;
1817
1818 /*
1819 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1820 * predictable (it's just a function of time and the likely is
d828199e
MT		 1821 * very likely) and there's a data dependence, so force GCC
1822 * to generate a branch instead. I don't barrier() because
1823 * we don't actually need a barrier, and if this function
1824 * ever gets inlined it will generate worse code.
1825 */
1826 asm volatile ("");
1827 return last;
1828}
1829
b0c39dc6 1830static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1831{
1832 long v;
1833 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1834 u64 tsc_pg_val;
1835
1836 switch (gtod->clock.vclock_mode) {
1837 case VCLOCK_HVCLOCK:
1838 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1839 tsc_timestamp);
1840 if (tsc_pg_val != U64_MAX) {
1841 /* TSC page valid */
1842 *mode = VCLOCK_HVCLOCK;
1843 v = (tsc_pg_val - gtod->clock.cycle_last) &
1844 gtod->clock.mask;
1845 } else {
1846 /* TSC page invalid */
1847 *mode = VCLOCK_NONE;
1848 }
1849 break;
1850 case VCLOCK_TSC:
1851 *mode = VCLOCK_TSC;
1852 *tsc_timestamp = read_tsc();
1853 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1854 gtod->clock.mask;
1855 break;
1856 default:
1857 *mode = VCLOCK_NONE;
1858 }
d828199e 1859
b0c39dc6
VK		 1860 if (*mode == VCLOCK_NONE)
1861 *tsc_timestamp = v = 0;
d828199e 1862
d828199e
MT		 1863 return v * gtod->clock.mult;
1864}
1865
b0c39dc6 1866static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1867{
cbcf2dd3 1868 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1869 unsigned long seq;
d828199e 1870 int mode;
cbcf2dd3 1871 u64 ns;
d828199e 1872
d828199e
MT		 1873 do {
1874 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1875 ns = gtod->nsec_base;
b0c39dc6 1876 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1877 ns >>= gtod->clock.shift;
cbcf2dd3 1878 ns += gtod->boot_ns;
d828199e 1879 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1880 *t = ns;
d828199e
MT		 1881
1882 return mode;
1883}
1884
899a31f5 1885static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1886{
1887 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1888 unsigned long seq;
1889 int mode;
1890 u64 ns;
1891
1892 do {
1893 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1894 ts->tv_sec = gtod->wall_time_sec;
1895 ns = gtod->nsec_base;
b0c39dc6 1896 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1897 ns >>= gtod->clock.shift;
1898 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1899
1900 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1901 ts->tv_nsec = ns;
1902
1903 return mode;
1904}
1905
b0c39dc6
VK		 1906/* returns true if host is using TSC based clocksource */
1907static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1908{
d828199e 1909 /* checked again under seqlock below */
b0c39dc6 1910 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1911 return false;
1912
b0c39dc6
VK		 1913 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1914 tsc_timestamp));
d828199e 1915}
55dd00a7 1916
b0c39dc6 1917/* returns true if host is using TSC based clocksource */
899a31f5 1918static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
b0c39dc6 1919 u64 *tsc_timestamp)
55dd00a7
MT		 1920{
1921 /* checked again under seqlock below */
b0c39dc6 1922 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1923 return false;
1924
b0c39dc6 1925 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1926}
d828199e
MT		 1927#endif
1928
1929/*
1930 *
b48aa97e
MT		 1931 * Assuming a stable TSC across physical CPUS, and a stable TSC
1932 * across virtual CPUs, the following condition is possible.
1933 * Each numbered line represents an event visible to both
d828199e
MT		 1934 * CPUs at the next numbered event.
1935 *
1936 * "timespecX" represents host monotonic time. "tscX" represents
1937 * RDTSC value.
1938 *
1939 * VCPU0 on CPU0 | VCPU1 on CPU1
1940 *
1941 * 1. read timespec0,tsc0
1942 * 2. | timespec1 = timespec0 + N
1943 * | tsc1 = tsc0 + M
1944 * 3. transition to guest | transition to guest
1945 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1946 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1947 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1948 *
1949 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1950 *
1951 * - ret0 < ret1
1952 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1953 * ...
1954 * - 0 < N - M => M < N
1955 *
1956 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1957 * always the case (the difference between two distinct xtime instances
1958 * might be smaller then the difference between corresponding TSC reads,
1959 * when updating guest vcpus pvclock areas).
1960 *
1961 * To avoid that problem, do not allow visibility of distinct
1962 * system_timestamp/tsc_timestamp values simultaneously: use a master
1963 * copy of host monotonic time values. Update that master copy
1964 * in lockstep.
1965 *
b48aa97e 1966 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1967 *
1968 */
1969
1970static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1971{
1972#ifdef CONFIG_X86_64
1973 struct kvm_arch *ka = &kvm->arch;
1974 int vclock_mode;
b48aa97e
MT		 1975 bool host_tsc_clocksource, vcpus_matched;
1976
1977 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1978 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1979
1980 /*
1981 * If the host uses TSC clock, then passthrough TSC as stable
1982 * to the guest.
1983 */
b48aa97e 1984 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1985 &ka->master_kernel_ns,
1986 &ka->master_cycle_now);
1987
16a96021 1988 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1989 && !ka->backwards_tsc_observed
54750f2c 1990 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1991
d828199e
MT		 1992 if (ka->use_master_clock)
1993 atomic_set(&kvm_guest_has_master_clock, 1);
1994
1995 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1996 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1997 vcpus_matched);
d828199e
MT		 1998#endif
1999}
2000
2860c4b1
PB		 2001void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2002{
2003 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2004}
2005
2e762ff7
MT		 2006static void kvm_gen_update_masterclock(struct kvm *kvm)
2007{
2008#ifdef CONFIG_X86_64
2009 int i;
2010 struct kvm_vcpu *vcpu;
2011 struct kvm_arch *ka = &kvm->arch;
2012
2013 spin_lock(&ka->pvclock_gtod_sync_lock);
2014 kvm_make_mclock_inprogress_request(kvm);
2015 /* no guest entries from this point */
2016 pvclock_update_vm_gtod_copy(kvm);
2017
2018 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 2019 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 2020
2021 /* guest entries allowed */
2022 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 2023 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 2024
2025 spin_unlock(&ka->pvclock_gtod_sync_lock);
2026#endif
2027}
2028
e891a32e 2029u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 2030{
108b249c 2031 struct kvm_arch *ka = &kvm->arch;
8b953440 2032 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 2033 u64 ret;
108b249c 2034
8b953440
PB		 2035 spin_lock(&ka->pvclock_gtod_sync_lock);
2036 if (!ka->use_master_clock) {
2037 spin_unlock(&ka->pvclock_gtod_sync_lock);
2038 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 2039 }
2040
8b953440
PB		 2041 hv_clock.tsc_timestamp = ka->master_cycle_now;
2042 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2043 spin_unlock(&ka->pvclock_gtod_sync_lock);
2044
e2c2206a
WL		 2045 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2046 get_cpu();
2047
e70b57a6
WL		 2048 if (__this_cpu_read(cpu_tsc_khz)) {
2049 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2050 &hv_clock.tsc_shift,
2051 &hv_clock.tsc_to_system_mul);
2052 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2053 } else
2054 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 2055
2056 put_cpu();
2057
2058 return ret;
108b249c
PB		 2059}
2060
0d6dd2ff
PB		 2061static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2062{
2063 struct kvm_vcpu_arch *vcpu = &v->arch;
2064 struct pvclock_vcpu_time_info guest_hv_clock;
2065
4e335d9e 2066 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 2067 &guest_hv_clock, sizeof(guest_hv_clock))))
2068 return;
2069
2070 /* This VCPU is paused, but it's legal for a guest to read another
2071 * VCPU's kvmclock, so we really have to follow the specification where
2072 * it says that version is odd if data is being modified, and even after
2073 * it is consistent.
2074 *
2075 * Version field updates must be kept separate. This is because
2076 * kvm_write_guest_cached might use a "rep movs" instruction, and
2077 * writes within a string instruction are weakly ordered. So there
2078 * are three writes overall.
2079 *
2080 * As a small optimization, only write the version field in the first
2081 * and third write. The vcpu->pv_time cache is still valid, because the
2082 * version field is the first in the struct.
2083 */
2084 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2085
51c4b8bb
LA		 2086 if (guest_hv_clock.version & 1)
2087 ++guest_hv_clock.version; /* first time write, random junk */
2088
0d6dd2ff 2089 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 2090 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2091 &vcpu->hv_clock,
2092 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2093
2094 smp_wmb();
2095
2096 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2097 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2098
2099 if (vcpu->pvclock_set_guest_stopped_request) {
2100 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2101 vcpu->pvclock_set_guest_stopped_request = false;
2102 }
2103
2104 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2105
4e335d9e
PB		 2106 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2107 &vcpu->hv_clock,
2108 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 2109
2110 smp_wmb();
2111
2112 vcpu->hv_clock.version++;
4e335d9e
PB		 2113 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2114 &vcpu->hv_clock,
2115 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2116}
2117
34c238a1 2118static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 2119{
78db6a50 2120 unsigned long flags, tgt_tsc_khz;
18068523 2121 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 2122 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 2123 s64 kernel_ns;
d828199e 2124 u64 tsc_timestamp, host_tsc;
51d59c6b 2125 u8 pvclock_flags;
d828199e
MT		 2126 bool use_master_clock;
2127
2128 kernel_ns = 0;
2129 host_tsc = 0;
18068523 2130
d828199e
MT		 2131 /*
2132 * If the host uses TSC clock, then passthrough TSC as stable
2133 * to the guest.
2134 */
2135 spin_lock(&ka->pvclock_gtod_sync_lock);
2136 use_master_clock = ka->use_master_clock;
2137 if (use_master_clock) {
2138 host_tsc = ka->master_cycle_now;
2139 kernel_ns = ka->master_kernel_ns;
2140 }
2141 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2142
2143 /* Keep irq disabled to prevent changes to the clock */
2144 local_irq_save(flags);
78db6a50
PB		 2145 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2146 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2147 local_irq_restore(flags);
2148 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2149 return 1;
2150 }
d828199e 2151 if (!use_master_clock) {
4ea1636b 2152 host_tsc = rdtsc();
108b249c 2153 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 2154 }
2155
4ba76538 2156 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2157
c285545f
ZA		 2158 /*
2159 * We may have to catch up the TSC to match elapsed wall clock
2160 * time for two reasons, even if kvmclock is used.
2161 * 1) CPU could have been running below the maximum TSC rate
2162 * 2) Broken TSC compensation resets the base at each VCPU
2163 * entry to avoid unknown leaps of TSC even when running
2164 * again on the same CPU. This may cause apparent elapsed
2165 * time to disappear, and the guest to stand still or run
2166 * very slowly.
2167 */
2168 if (vcpu->tsc_catchup) {
2169 u64 tsc = compute_guest_tsc(v, kernel_ns);
2170 if (tsc > tsc_timestamp) {
f1e2b260 2171 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2172 tsc_timestamp = tsc;
2173 }
50d0a0f9
GH		 2174 }
2175
18068523
GOC		 2176 local_irq_restore(flags);
2177
0d6dd2ff 2178 /* With all the info we got, fill in the values */
18068523 2179
78db6a50
PB		 2180 if (kvm_has_tsc_control)
2181 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2182
2183 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2184 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2185 &vcpu->hv_clock.tsc_shift,
2186 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2187 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2188 }
2189
1d5f066e 2190 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2191 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2192 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2193
d828199e 2194 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2195 pvclock_flags = 0;
d828199e
MT		 2196 if (use_master_clock)
2197 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2198
78c0337a
MT		 2199 vcpu->hv_clock.flags = pvclock_flags;
2200
095cf55d
PB		 2201 if (vcpu->pv_time_enabled)
2202 kvm_setup_pvclock_page(v);
2203 if (v == kvm_get_vcpu(v->kvm, 0))
2204 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2205 return 0;
c8076604
GH		 2206}
2207
0061d53d
MT		 2208/*
2209 * kvmclock updates which are isolated to a given vcpu, such as
2210 * vcpu->cpu migration, should not allow system_timestamp from
2211 * the rest of the vcpus to remain static. Otherwise ntp frequency
2212 * correction applies to one vcpu's system_timestamp but not
2213 * the others.
2214 *
2215 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2216 * We need to rate-limit these requests though, as they can
2217 * considerably slow guests that have a large number of vcpus.
2218 * The time for a remote vcpu to update its kvmclock is bound
2219 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2220 */
2221
7e44e449
AJ		 2222#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2223
2224static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2225{
2226 int i;
7e44e449
AJ		 2227 struct delayed_work *dwork = to_delayed_work(work);
2228 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2229 kvmclock_update_work);
2230 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2231 struct kvm_vcpu *vcpu;
2232
2233 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2234 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2235 kvm_vcpu_kick(vcpu);
2236 }
2237}
2238
7e44e449
AJ		 2239static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2240{
2241 struct kvm *kvm = v->kvm;
2242
105b21bb 2243 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2244 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2245 KVMCLOCK_UPDATE_DELAY);
2246}
2247
332967a3
AJ		 2248#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2249
2250static void kvmclock_sync_fn(struct work_struct *work)
2251{
2252 struct delayed_work *dwork = to_delayed_work(work);
2253 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2254 kvmclock_sync_work);
2255 struct kvm *kvm = container_of(ka, struct kvm, arch);
2256
630994b3
MT		 2257 if (!kvmclock_periodic_sync)
2258 return;
2259
332967a3
AJ		 2260 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2261 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2262 KVMCLOCK_SYNC_PERIOD);
2263}
2264
9ffd986c 2265static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2266{
890ca9ae
HY		 2267 u64 mcg_cap = vcpu->arch.mcg_cap;
2268 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2269 u32 msr = msr_info->index;
2270 u64 data = msr_info->data;
890ca9ae 2271
15c4a640 2272 switch (msr) {
15c4a640 2273 case MSR_IA32_MCG_STATUS:
890ca9ae 2274 vcpu->arch.mcg_status = data;
15c4a640 2275 break;
c7ac679c 2276 case MSR_IA32_MCG_CTL:
44883f01
PB		 2277 if (!(mcg_cap & MCG_CTL_P) &&
2278 (data || !msr_info->host_initiated))
890ca9ae
HY		 2279 return 1;
2280 if (data != 0 && data != ~(u64)0)
44883f01 2281 return 1;
890ca9ae
HY		 2282 vcpu->arch.mcg_ctl = data;
2283 break;
2284 default:
2285 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2286 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2287 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2288 /* only 0 or all 1s can be written to IA32_MCi_CTL
2289 * some Linux kernels though clear bit 10 in bank 4 to
2290 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2291 * this to avoid an uncatched #GP in the guest
2292 */
890ca9ae 2293 if ((offset & 0x3) == 0 &&
114be429 2294 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2295 return -1;
9ffd986c
WL		 2296 if (!msr_info->host_initiated &&
2297 (offset & 0x3) == 1 && data != 0)
2298 return -1;
890ca9ae
HY		 2299 vcpu->arch.mce_banks[offset] = data;
2300 break;
2301 }
2302 return 1;
2303 }
2304 return 0;
2305}
2306
ffde22ac
ES		 2307static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2308{
2309 struct kvm *kvm = vcpu->kvm;
2310 int lm = is_long_mode(vcpu);
2311 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2312 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2313 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2314 : kvm->arch.xen_hvm_config.blob_size_32;
2315 u32 page_num = data & ~PAGE_MASK;
2316 u64 page_addr = data & PAGE_MASK;
2317 u8 *page;
2318 int r;
2319
2320 r = -E2BIG;
2321 if (page_num >= blob_size)
2322 goto out;
2323 r = -ENOMEM;
ff5c2c03
SL		 2324 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2325 if (IS_ERR(page)) {
2326 r = PTR_ERR(page);
ffde22ac 2327 goto out;
ff5c2c03 2328 }
54bf36aa 2329 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2330 goto out_free;
2331 r = 0;
2332out_free:
2333 kfree(page);
2334out:
2335 return r;
2336}
2337
344d9588
GN		 2338static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2339{
2340 gpa_t gpa = data & ~0x3f;
2341
52a5c155
WL		 2342 /* Bits 3:5 are reserved, Should be zero */
2343 if (data & 0x38)
344d9588
GN		 2344 return 1;
2345
2346 vcpu->arch.apf.msr_val = data;
2347
2348 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2349 kvm_clear_async_pf_completion_queue(vcpu);
2350 kvm_async_pf_hash_reset(vcpu);
2351 return 0;
2352 }
2353
4e335d9e 2354 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2355 sizeof(u32)))
344d9588
GN		 2356 return 1;
2357
6adba527 2358 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2359 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2360 kvm_async_pf_wakeup_all(vcpu);
2361 return 0;
2362}
2363
12f9a48f
GC		 2364static void kvmclock_reset(struct kvm_vcpu *vcpu)
2365{
0b79459b 2366 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2367}
2368
f38a7b75
WL		 2369static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2370{
2371 ++vcpu->stat.tlb_flush;
2372 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2373}
2374
c9aaa895
GC		 2375static void record_steal_time(struct kvm_vcpu *vcpu)
2376{
2377 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2378 return;
2379
4e335d9e 2380 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2381 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2382 return;
2383
f38a7b75
WL		 2384 /*
2385 * Doing a TLB flush here, on the guest's behalf, can avoid
2386 * expensive IPIs.
2387 */
2388 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2389 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2390
35f3fae1
WL		 2391 if (vcpu->arch.st.steal.version & 1)
2392 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2393
2394 vcpu->arch.st.steal.version += 1;
2395
4e335d9e 2396 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2397 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2398
2399 smp_wmb();
2400
c54cdf14
LC		 2401 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2402 vcpu->arch.st.last_steal;
2403 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2404
4e335d9e 2405 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2406 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2407
2408 smp_wmb();
2409
2410 vcpu->arch.st.steal.version += 1;
c9aaa895 2411
4e335d9e 2412 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2413 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2414}
2415
8fe8ab46 2416int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2417{
5753785f 2418 bool pr = false;
8fe8ab46
WA		 2419 u32 msr = msr_info->index;
2420 u64 data = msr_info->data;
5753785f 2421
15c4a640 2422 switch (msr) {
2e32b719 2423 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2424 case MSR_IA32_UCODE_WRITE:
2425 case MSR_VM_HSAVE_PA:
2426 case MSR_AMD64_PATCH_LOADER:
2427 case MSR_AMD64_BU_CFG2:
405a353a 2428 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2429 break;
2430
518e7b94
WL		 2431 case MSR_IA32_UCODE_REV:
2432 if (msr_info->host_initiated)
2433 vcpu->arch.microcode_version = data;
2434 break;
15c4a640 2435 case MSR_EFER:
b69e8cae 2436 return set_efer(vcpu, data);
8f1589d9
AP		 2437 case MSR_K7_HWCR:
2438 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2439 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2440 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2441 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2442 if (data != 0) {
a737f256
CD		 2443 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2444 data);
8f1589d9
AP		 2445 return 1;
2446 }
15c4a640 2447 break;
f7c6d140
AP		 2448 case MSR_FAM10H_MMIO_CONF_BASE:
2449 if (data != 0) {
a737f256
CD		 2450 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2451 "0x%llx\n", data);
f7c6d140
AP		 2452 return 1;
2453 }
15c4a640 2454 break;
b5e2fec0
AG		 2455 case MSR_IA32_DEBUGCTLMSR:
2456 if (!data) {
2457 /* We support the non-activated case already */
2458 break;
2459 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2460 /* Values other than LBR and BTF are vendor-specific,
2461 thus reserved and should throw a #GP */
2462 return 1;
2463 }
a737f256
CD		 2464 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2465 __func__, data);
b5e2fec0 2466 break;
9ba075a6 2467 case 0x200 ... 0x2ff:
ff53604b 2468 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2469 case MSR_IA32_APICBASE:
58cb628d 2470 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2471 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2472 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2473 case MSR_IA32_TSCDEADLINE:
2474 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2475 break;
ba904635 2476 case MSR_IA32_TSC_ADJUST:
d6321d49 2477 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2478 if (!msr_info->host_initiated) {
d913b904 2479 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2480 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2481 }
2482 vcpu->arch.ia32_tsc_adjust_msr = data;
2483 }
2484 break;
15c4a640 2485 case MSR_IA32_MISC_ENABLE:
ad312c7c 2486 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2487 break;
64d60670
PB		 2488 case MSR_IA32_SMBASE:
2489 if (!msr_info->host_initiated)
2490 return 1;
2491 vcpu->arch.smbase = data;
2492 break;
dd259935
PB		 2493 case MSR_IA32_TSC:
2494 kvm_write_tsc(vcpu, msr_info);
2495 break;
52797bf9
LA		 2496 case MSR_SMI_COUNT:
2497 if (!msr_info->host_initiated)
2498 return 1;
2499 vcpu->arch.smi_count = data;
2500 break;
11c6bffa 2501 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2502 case MSR_KVM_WALL_CLOCK:
2503 vcpu->kvm->arch.wall_clock = data;
2504 kvm_write_wall_clock(vcpu->kvm, data);
2505 break;
11c6bffa 2506 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2507 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2508 struct kvm_arch *ka = &vcpu->kvm->arch;
2509
12f9a48f 2510 kvmclock_reset(vcpu);
18068523 2511
54750f2c
MT		 2512 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2513 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2514
2515 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2516 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2517
2518 ka->boot_vcpu_runs_old_kvmclock = tmp;
2519 }
2520
18068523 2521 vcpu->arch.time = data;
0061d53d 2522 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2523
2524 /* we verify if the enable bit is set... */
2525 if (!(data & 1))
2526 break;
2527
4e335d9e 2528 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2529 &vcpu->arch.pv_time, data & ~1ULL,
2530 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2531 vcpu->arch.pv_time_enabled = false;
2532 else
2533 vcpu->arch.pv_time_enabled = true;
32cad84f 2534
18068523
GOC		 2535 break;
2536 }
344d9588
GN		 2537 case MSR_KVM_ASYNC_PF_EN:
2538 if (kvm_pv_enable_async_pf(vcpu, data))
2539 return 1;
2540 break;
c9aaa895
GC		 2541 case MSR_KVM_STEAL_TIME:
2542
2543 if (unlikely(!sched_info_on()))
2544 return 1;
2545
2546 if (data & KVM_STEAL_RESERVED_MASK)
2547 return 1;
2548
4e335d9e 2549 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2550 data & KVM_STEAL_VALID_BITS,
2551 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2552 return 1;
2553
2554 vcpu->arch.st.msr_val = data;
2555
2556 if (!(data & KVM_MSR_ENABLED))
2557 break;
2558
c9aaa895
GC		 2559 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2560
2561 break;
ae7a2a3f 2562 case MSR_KVM_PV_EOI_EN:
72bbf935 2563 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
ae7a2a3f
MT		 2564 return 1;
2565 break;
c9aaa895 2566
890ca9ae
HY		 2567 case MSR_IA32_MCG_CTL:
2568 case MSR_IA32_MCG_STATUS:
81760dcc 2569 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2570 return set_msr_mce(vcpu, msr_info);
71db6023 2571
6912ac32
WH		 2572 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2573 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2574 pr = true; /* fall through */
2575 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2576 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2577 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2578 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2579
2580 if (pr || data != 0)
a737f256
CD		 2581 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2582 "0x%x data 0x%llx\n", msr, data);
5753785f 2583 break;
84e0cefa
JS		 2584 case MSR_K7_CLK_CTL:
2585 /*
2586 * Ignore all writes to this no longer documented MSR.
2587 * Writes are only relevant for old K7 processors,
2588 * all pre-dating SVM, but a recommended workaround from
4a969980 2589 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2590 * affected processor models on the command line, hence
2591 * the need to ignore the workaround.
2592 */
2593 break;
55cd8e5a 2594 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2595 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2596 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2597 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2598 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2599 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2600 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2601 return kvm_hv_set_msr_common(vcpu, msr, data,
2602 msr_info->host_initiated);
91c9c3ed 2603 case MSR_IA32_BBL_CR_CTL3:
2604 /* Drop writes to this legacy MSR -- see rdmsr
2605 * counterpart for further detail.
2606 */
fab0aa3b
EM		 2607 if (report_ignored_msrs)
2608 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2609 msr, data);
91c9c3ed 2610 break;
2b036c6b 2611 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2612 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2613 return 1;
2614 vcpu->arch.osvw.length = data;
2615 break;
2616 case MSR_AMD64_OSVW_STATUS:
d6321d49 2617 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2618 return 1;
2619 vcpu->arch.osvw.status = data;
2620 break;
db2336a8
KH		 2621 case MSR_PLATFORM_INFO:
2622 if (!msr_info->host_initiated ||
db2336a8
KH		 2623 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2624 cpuid_fault_enabled(vcpu)))
2625 return 1;
2626 vcpu->arch.msr_platform_info = data;
2627 break;
2628 case MSR_MISC_FEATURES_ENABLES:
2629 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2630 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2631 !supports_cpuid_fault(vcpu)))
2632 return 1;
2633 vcpu->arch.msr_misc_features_enables = data;
2634 break;
15c4a640 2635 default:
ffde22ac
ES		 2636 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2637 return xen_hvm_config(vcpu, data);
c6702c9d 2638 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2639 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2640 if (!ignore_msrs) {
ae0f5499 2641 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2642 msr, data);
ed85c068
AP		 2643 return 1;
2644 } else {
fab0aa3b
EM		 2645 if (report_ignored_msrs)
2646 vcpu_unimpl(vcpu,
2647 "ignored wrmsr: 0x%x data 0x%llx\n",
2648 msr, data);
ed85c068
AP		 2649 break;
2650 }
15c4a640
CO		 2651 }
2652 return 0;
2653}
2654EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2655
2656
2657/*
2658 * Reads an msr value (of 'msr_index') into 'pdata'.
2659 * Returns 0 on success, non-0 otherwise.
2660 * Assumes vcpu_load() was already called.
2661 */
609e36d3 2662int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2663{
609e36d3 2664 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2665}
ff651cb6 2666EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2667
44883f01 2668static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
15c4a640
CO		 2669{
2670 u64 data;
890ca9ae
HY		 2671 u64 mcg_cap = vcpu->arch.mcg_cap;
2672 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2673
2674 switch (msr) {
15c4a640
CO		 2675 case MSR_IA32_P5_MC_ADDR:
2676 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2677 data = 0;
2678 break;
15c4a640 2679 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2680 data = vcpu->arch.mcg_cap;
2681 break;
c7ac679c 2682 case MSR_IA32_MCG_CTL:
44883f01 2683 if (!(mcg_cap & MCG_CTL_P) && !host)
890ca9ae
HY		 2684 return 1;
2685 data = vcpu->arch.mcg_ctl;
2686 break;
2687 case MSR_IA32_MCG_STATUS:
2688 data = vcpu->arch.mcg_status;
2689 break;
2690 default:
2691 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2692 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2693 u32 offset = msr - MSR_IA32_MC0_CTL;
2694 data = vcpu->arch.mce_banks[offset];
2695 break;
2696 }
2697 return 1;
2698 }
2699 *pdata = data;
2700 return 0;
2701}
2702
609e36d3 2703int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2704{
609e36d3 2705 switch (msr_info->index) {
890ca9ae 2706 case MSR_IA32_PLATFORM_ID:
15c4a640 2707 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2708 case MSR_IA32_DEBUGCTLMSR:
2709 case MSR_IA32_LASTBRANCHFROMIP:
2710 case MSR_IA32_LASTBRANCHTOIP:
2711 case MSR_IA32_LASTINTFROMIP:
2712 case MSR_IA32_LASTINTTOIP:
60af2ecd 2713 case MSR_K8_SYSCFG:
3afb1121
PB		 2714 case MSR_K8_TSEG_ADDR:
2715 case MSR_K8_TSEG_MASK:
60af2ecd 2716 case MSR_K7_HWCR:
61a6bd67 2717 case MSR_VM_HSAVE_PA:
1fdbd48c 2718 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2719 case MSR_AMD64_NB_CFG:
f7c6d140 2720 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2721 case MSR_AMD64_BU_CFG2:
0c2df2a1 2722 case MSR_IA32_PERF_CTL:
405a353a 2723 case MSR_AMD64_DC_CFG:
609e36d3 2724 msr_info->data = 0;
15c4a640 2725 break;
c51eb52b 2726 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2727 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2728 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2729 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2730 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2731 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2732 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2733 msr_info->data = 0;
5753785f 2734 break;
742bc670 2735 case MSR_IA32_UCODE_REV:
518e7b94 2736 msr_info->data = vcpu->arch.microcode_version;
742bc670 2737 break;
dd259935
PB		 2738 case MSR_IA32_TSC:
2739 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2740 break;
9ba075a6 2741 case MSR_MTRRcap:
9ba075a6 2742 case 0x200 ... 0x2ff:
ff53604b 2743 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2744 case 0xcd: /* fsb frequency */
609e36d3 2745 msr_info->data = 3;
15c4a640 2746 break;
7b914098
JS		 2747 /*
2748 * MSR_EBC_FREQUENCY_ID
2749 * Conservative value valid for even the basic CPU models.
2750 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2751 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2752 * and 266MHz for model 3, or 4. Set Core Clock
2753 * Frequency to System Bus Frequency Ratio to 1 (bits
2754 * 31:24) even though these are only valid for CPU
2755 * models > 2, however guests may end up dividing or
2756 * multiplying by zero otherwise.
2757 */
2758 case MSR_EBC_FREQUENCY_ID:
609e36d3 2759 msr_info->data = 1 << 24;
7b914098 2760 break;
15c4a640 2761 case MSR_IA32_APICBASE:
609e36d3 2762 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2763 break;
0105d1a5 2764 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2765 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2766 break;
a3e06bbe 2767 case MSR_IA32_TSCDEADLINE:
609e36d3 2768 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2769 break;
ba904635 2770 case MSR_IA32_TSC_ADJUST:
609e36d3 2771 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2772 break;
15c4a640 2773 case MSR_IA32_MISC_ENABLE:
609e36d3 2774 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2775 break;
64d60670
PB		 2776 case MSR_IA32_SMBASE:
2777 if (!msr_info->host_initiated)
2778 return 1;
2779 msr_info->data = vcpu->arch.smbase;
15c4a640 2780 break;
52797bf9
LA		 2781 case MSR_SMI_COUNT:
2782 msr_info->data = vcpu->arch.smi_count;
2783 break;
847f0ad8
AG		 2784 case MSR_IA32_PERF_STATUS:
2785 /* TSC increment by tick */
609e36d3 2786 msr_info->data = 1000ULL;
847f0ad8 2787 /* CPU multiplier */
b0996ae4 2788 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2789 break;
15c4a640 2790 case MSR_EFER:
609e36d3 2791 msr_info->data = vcpu->arch.efer;
15c4a640 2792 break;
18068523 2793 case MSR_KVM_WALL_CLOCK:
11c6bffa 2794 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2795 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2796 break;
2797 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2798 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2799 msr_info->data = vcpu->arch.time;
18068523 2800 break;
344d9588 2801 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2802 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2803 break;
c9aaa895 2804 case MSR_KVM_STEAL_TIME:
609e36d3 2805 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2806 break;
1d92128f 2807 case MSR_KVM_PV_EOI_EN:
609e36d3 2808 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2809 break;
890ca9ae
HY		 2810 case MSR_IA32_P5_MC_ADDR:
2811 case MSR_IA32_P5_MC_TYPE:
2812 case MSR_IA32_MCG_CAP:
2813 case MSR_IA32_MCG_CTL:
2814 case MSR_IA32_MCG_STATUS:
81760dcc 2815 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
44883f01
PB		 2816 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
2817 msr_info->host_initiated);
84e0cefa
JS		 2818 case MSR_K7_CLK_CTL:
2819 /*
2820 * Provide expected ramp-up count for K7. All other
2821 * are set to zero, indicating minimum divisors for
2822 * every field.
2823 *
2824 * This prevents guest kernels on AMD host with CPU
2825 * type 6, model 8 and higher from exploding due to
2826 * the rdmsr failing.
2827 */
609e36d3 2828 msr_info->data = 0x20000000;
84e0cefa 2829 break;
55cd8e5a 2830 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2831 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2832 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2833 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2834 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2835 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2836 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887 2837 return kvm_hv_get_msr_common(vcpu,
44883f01
PB		 2838 msr_info->index, &msr_info->data,
2839 msr_info->host_initiated);
55cd8e5a 2840 break;
91c9c3ed 2841 case MSR_IA32_BBL_CR_CTL3:
2842 /* This legacy MSR exists but isn't fully documented in current
2843 * silicon. It is however accessed by winxp in very narrow
2844 * scenarios where it sets bit #19, itself documented as
2845 * a "reserved" bit. Best effort attempt to source coherent
2846 * read data here should the balance of the register be
2847 * interpreted by the guest:
2848 *
2849 * L2 cache control register 3: 64GB range, 256KB size,
2850 * enabled, latency 0x1, configured
2851 */
609e36d3 2852 msr_info->data = 0xbe702111;
91c9c3ed 2853 break;
2b036c6b 2854 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2855 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2856 return 1;
609e36d3 2857 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2858 break;
2859 case MSR_AMD64_OSVW_STATUS:
d6321d49 2860 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2861 return 1;
609e36d3 2862 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2863 break;
db2336a8 2864 case MSR_PLATFORM_INFO:
6fbbde9a
DS		 2865 if (!msr_info->host_initiated &&
2866 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
2867 return 1;
db2336a8
KH		 2868 msr_info->data = vcpu->arch.msr_platform_info;
2869 break;
2870 case MSR_MISC_FEATURES_ENABLES:
2871 msr_info->data = vcpu->arch.msr_misc_features_enables;
2872 break;
15c4a640 2873 default:
c6702c9d 2874 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2875 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2876 if (!ignore_msrs) {
ae0f5499
BD		 2877 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2878 msr_info->index);
ed85c068
AP		 2879 return 1;
2880 } else {
fab0aa3b
EM		 2881 if (report_ignored_msrs)
2882 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2883 msr_info->index);
609e36d3 2884 msr_info->data = 0;
ed85c068
AP		 2885 }
2886 break;
15c4a640 2887 }
15c4a640
CO		 2888 return 0;
2889}
2890EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2891
313a3dc7
CO		 2892/*
2893 * Read or write a bunch of msrs. All parameters are kernel addresses.
2894 *
2895 * @return number of msrs set successfully.
2896 */
2897static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2898 struct kvm_msr_entry *entries,
2899 int (*do_msr)(struct kvm_vcpu *vcpu,
2900 unsigned index, u64 *data))
2901{
801e459a 2902 int i;
313a3dc7 2903
313a3dc7
CO		 2904 for (i = 0; i < msrs->nmsrs; ++i)
2905 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2906 break;
2907
313a3dc7
CO		 2908 return i;
2909}
2910
2911/*
2912 * Read or write a bunch of msrs. Parameters are user addresses.
2913 *
2914 * @return number of msrs set successfully.
2915 */
2916static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2917 int (*do_msr)(struct kvm_vcpu *vcpu,
2918 unsigned index, u64 *data),
2919 int writeback)
2920{
2921 struct kvm_msrs msrs;
2922 struct kvm_msr_entry *entries;
2923 int r, n;
2924 unsigned size;
2925
2926 r = -EFAULT;
2927 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2928 goto out;
2929
2930 r = -E2BIG;
2931 if (msrs.nmsrs >= MAX_IO_MSRS)
2932 goto out;
2933
313a3dc7 2934 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2935 entries = memdup_user(user_msrs->entries, size);
2936 if (IS_ERR(entries)) {
2937 r = PTR_ERR(entries);
313a3dc7 2938 goto out;
ff5c2c03 2939 }
313a3dc7
CO		 2940
2941 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2942 if (r < 0)
2943 goto out_free;
2944
2945 r = -EFAULT;
2946 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2947 goto out_free;
2948
2949 r = n;
2950
2951out_free:
7a73c028 2952 kfree(entries);
313a3dc7
CO		 2953out:
2954 return r;
2955}
2956
4d5422ce
WL		 2957static inline bool kvm_can_mwait_in_guest(void)
2958{
2959 return boot_cpu_has(X86_FEATURE_MWAIT) &&
8e9b29b6
KA		 2960 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
2961 boot_cpu_has(X86_FEATURE_ARAT);
4d5422ce
WL		 2962}
2963
784aa3d7 2964int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2 2965{
4d5422ce 2966 int r = 0;
018d00d2
ZX		 2967
2968 switch (ext) {
2969 case KVM_CAP_IRQCHIP:
2970 case KVM_CAP_HLT:
2971 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2972 case KVM_CAP_SET_TSS_ADDR:
07716717 2973 case KVM_CAP_EXT_CPUID:
9c15bb1d 2974 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2975 case KVM_CAP_CLOCKSOURCE:
7837699f 2976 case KVM_CAP_PIT:
a28e4f5a 2977 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2978 case KVM_CAP_MP_STATE:
ed848624 2979 case KVM_CAP_SYNC_MMU:
a355c85c 2980 case KVM_CAP_USER_NMI:
52d939a0 2981 case KVM_CAP_REINJECT_CONTROL:
4925663a 2982 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2983 case KVM_CAP_IOEVENTFD:
f848a5a8 2984 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2985 case KVM_CAP_PIT2:
e9f42757 2986 case KVM_CAP_PIT_STATE2:
b927a3ce 2987 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2988 case KVM_CAP_XEN_HVM:
3cfc3092 2989 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2990 case KVM_CAP_HYPERV:
10388a07 2991 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2992 case KVM_CAP_HYPERV_SPIN:
5c919412 2993 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2994 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2995 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 2996 case KVM_CAP_HYPERV_EVENTFD:
c1aea919 2997 case KVM_CAP_HYPERV_TLBFLUSH:
214ff83d 2998 case KVM_CAP_HYPERV_SEND_IPI:
57b119da 2999 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
ab9f4ecb 3000 case KVM_CAP_PCI_SEGMENT:
a1efbe77 3001 case KVM_CAP_DEBUGREGS:
d2be1651 3002 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 3003 case KVM_CAP_XSAVE:
344d9588 3004 case KVM_CAP_ASYNC_PF:
92a1f12d 3005 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 3006 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 3007 case KVM_CAP_READONLY_MEM:
5f66b620 3008 case KVM_CAP_HYPERV_TIME:
100943c5 3009 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 3010 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 3011 case KVM_CAP_ENABLE_CAP_VM:
3012 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 3013 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 3014 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 3015 case KVM_CAP_IMMEDIATE_EXIT:
801e459a 3016 case KVM_CAP_GET_MSR_FEATURES:
6fbbde9a 3017 case KVM_CAP_MSR_PLATFORM_INFO:
018d00d2
ZX		 3018 r = 1;
3019 break;
01643c51
KH		 3020 case KVM_CAP_SYNC_REGS:
3021 r = KVM_SYNC_X86_VALID_FIELDS;
3022 break;
e3fd9a93
PB		 3023 case KVM_CAP_ADJUST_CLOCK:
3024 r = KVM_CLOCK_TSC_STABLE;
3025 break;
4d5422ce 3026 case KVM_CAP_X86_DISABLE_EXITS:
766d3571 3027 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE;
4d5422ce
WL		 3028 if(kvm_can_mwait_in_guest())
3029 r |= KVM_X86_DISABLE_EXITS_MWAIT;
668fffa3 3030 break;
6d396b55
PB		 3031 case KVM_CAP_X86_SMM:
3032 /* SMBASE is usually relocated above 1M on modern chipsets,
3033 * and SMM handlers might indeed rely on 4G segment limits,
3034 * so do not report SMM to be available if real mode is
3035 * emulated via vm86 mode. Still, do not go to great lengths
3036 * to avoid userspace's usage of the feature, because it is a
3037 * fringe case that is not enabled except via specific settings
3038 * of the module parameters.
3039 */
bc226f07 3040 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
6d396b55 3041 break;
774ead3a
AK		 3042 case KVM_CAP_VAPIC:
3043 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3044 break;
f725230a 3045 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 3046 r = KVM_SOFT_MAX_VCPUS;
3047 break;
3048 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 3049 r = KVM_MAX_VCPUS;
3050 break;
a988b910 3051 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 3052 r = KVM_USER_MEM_SLOTS;
a988b910 3053 break;
a68a6a72
MT		 3054 case KVM_CAP_PV_MMU: /* obsolete */
3055 r = 0;
2f333bcb 3056 break;
890ca9ae
HY		 3057 case KVM_CAP_MCE:
3058 r = KVM_MAX_MCE_BANKS;
3059 break;
2d5b5a66 3060 case KVM_CAP_XCRS:
d366bf7e 3061 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 3062 break;
92a1f12d
JR		 3063 case KVM_CAP_TSC_CONTROL:
3064 r = kvm_has_tsc_control;
3065 break;
37131313
RK		 3066 case KVM_CAP_X2APIC_API:
3067 r = KVM_X2APIC_API_VALID_FLAGS;
3068 break;
8fcc4b59
JM		 3069 case KVM_CAP_NESTED_STATE:
3070 r = kvm_x86_ops->get_nested_state ?
3071 kvm_x86_ops->get_nested_state(NULL, 0, 0) : 0;
3072 break;
018d00d2 3073 default:
018d00d2
ZX		 3074 break;
3075 }
3076 return r;
3077
3078}
3079
043405e1
CO		 3080long kvm_arch_dev_ioctl(struct file *filp,
3081 unsigned int ioctl, unsigned long arg)
3082{
3083 void __user *argp = (void __user *)arg;
3084 long r;
3085
3086 switch (ioctl) {
3087 case KVM_GET_MSR_INDEX_LIST: {
3088 struct kvm_msr_list __user *user_msr_list = argp;
3089 struct kvm_msr_list msr_list;
3090 unsigned n;
3091
3092 r = -EFAULT;
3093 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
3094 goto out;
3095 n = msr_list.nmsrs;
62ef68bb 3096 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 3097 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
3098 goto out;
3099 r = -E2BIG;
e125e7b6 3100 if (n < msr_list.nmsrs)
043405e1
CO		 3101 goto out;
3102 r = -EFAULT;
3103 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3104 num_msrs_to_save * sizeof(u32)))
3105 goto out;
e125e7b6 3106 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 3107 &emulated_msrs,
62ef68bb 3108 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 3109 goto out;
3110 r = 0;
3111 break;
3112 }
9c15bb1d
BP		 3113 case KVM_GET_SUPPORTED_CPUID:
3114 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 3115 struct kvm_cpuid2 __user *cpuid_arg = argp;
3116 struct kvm_cpuid2 cpuid;
3117
3118 r = -EFAULT;
3119 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3120 goto out;
9c15bb1d
BP		 3121
3122 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3123 ioctl);
674eea0f
AK		 3124 if (r)
3125 goto out;
3126
3127 r = -EFAULT;
3128 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3129 goto out;
3130 r = 0;
3131 break;
3132 }
890ca9ae 3133 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 3134 r = -EFAULT;
c45dcc71
AR		 3135 if (copy_to_user(argp, &kvm_mce_cap_supported,
3136 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 3137 goto out;
3138 r = 0;
3139 break;
801e459a
TL		 3140 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3141 struct kvm_msr_list __user *user_msr_list = argp;
3142 struct kvm_msr_list msr_list;
3143 unsigned int n;
3144
3145 r = -EFAULT;
3146 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3147 goto out;
3148 n = msr_list.nmsrs;
3149 msr_list.nmsrs = num_msr_based_features;
3150 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3151 goto out;
3152 r = -E2BIG;
3153 if (n < msr_list.nmsrs)
3154 goto out;
3155 r = -EFAULT;
3156 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3157 num_msr_based_features * sizeof(u32)))
3158 goto out;
3159 r = 0;
3160 break;
3161 }
3162 case KVM_GET_MSRS:
3163 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3164 break;
890ca9ae 3165 }
043405e1
CO		 3166 default:
3167 r = -EINVAL;
3168 }
3169out:
3170 return r;
3171}
3172
f5f48ee1
SY		 3173static void wbinvd_ipi(void *garbage)
3174{
3175 wbinvd();
3176}
3177
3178static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3179{
e0f0bbc5 3180 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3181}
3182
313a3dc7
CO		 3183void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3184{
f5f48ee1
SY		 3185 /* Address WBINVD may be executed by guest */
3186 if (need_emulate_wbinvd(vcpu)) {
3187 if (kvm_x86_ops->has_wbinvd_exit())
3188 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3189 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3190 smp_call_function_single(vcpu->cpu,
3191 wbinvd_ipi, NULL, 1);
3192 }
3193
313a3dc7 3194 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3195
0dd6a6ed
ZA		 3196 /* Apply any externally detected TSC adjustments (due to suspend) */
3197 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3198 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3199 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3200 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3201 }
8f6055cb 3202
b0c39dc6 3203 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3204 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3205 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3206 if (tsc_delta < 0)
3207 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3208
b0c39dc6 3209 if (kvm_check_tsc_unstable()) {
07c1419a 3210 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3211 vcpu->arch.last_guest_tsc);
a545ab6a 3212 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3213 vcpu->arch.tsc_catchup = 1;
c285545f 3214 }
a749e247
PB		 3215
3216 if (kvm_lapic_hv_timer_in_use(vcpu))
3217 kvm_lapic_restart_hv_timer(vcpu);
3218
d98d07ca
MT		 3219 /*
3220 * On a host with synchronized TSC, there is no need to update
3221 * kvmclock on vcpu->cpu migration
3222 */
3223 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3224 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3225 if (vcpu->cpu != cpu)
1bd2009e 3226 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3227 vcpu->cpu = cpu;
6b7d7e76 3228 }
c9aaa895 3229
c9aaa895 3230 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3231}
3232
0b9f6c46
PX		 3233static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3234{
3235 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3236 return;
3237
fa55eedd 3238 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3239
4e335d9e 3240 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3241 &vcpu->arch.st.steal.preempted,
3242 offsetof(struct kvm_steal_time, preempted),
3243 sizeof(vcpu->arch.st.steal.preempted));
3244}
3245
313a3dc7
CO		 3246void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3247{
cc0d907c 3248 int idx;
de63ad4c
LM		 3249
3250 if (vcpu->preempted)
3251 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3252
931f261b
AA		 3253 /*
3254 * Disable page faults because we're in atomic context here.
3255 * kvm_write_guest_offset_cached() would call might_fault()
3256 * that relies on pagefault_disable() to tell if there's a
3257 * bug. NOTE: the write to guest memory may not go through if
3258 * during postcopy live migration or if there's heavy guest
3259 * paging.
3260 */
3261 pagefault_disable();
cc0d907c
AA		 3262 /*
3263 * kvm_memslots() will be called by
3264 * kvm_write_guest_offset_cached() so take the srcu lock.
3265 */
3266 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3267 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3268 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3269 pagefault_enable();
02daab21 3270 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3271 vcpu->arch.last_host_tsc = rdtsc();
efdab992 3272 /*
0e0a53c5
PB		 3273 * Here dr6 is either zero or, if the guest has run and userspace
3274 * has not set any breakpoints or watchpoints, it can be set to
3275 * the guest dr6 (stored in vcpu->arch.dr6). do_debug expects dr6
3276 * to be cleared after it runs, so clear the host register. However,
3277 * MOV to DR can be expensive when running nested, omit it if
3278 * vcpu->arch.dr6 is already zero: in that case, the host dr6 cannot
3279 * currently be nonzero.
efdab992 3280 */
0e0a53c5
PB		 3281 if (vcpu->arch.dr6)
3282 set_debugreg(0, 6);
313a3dc7
CO		 3283}
3284
313a3dc7
CO		 3285static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3286 struct kvm_lapic_state *s)
3287{
fa59cc00 3288 if (vcpu->arch.apicv_active)
d62caabb
AS		 3289 kvm_x86_ops->sync_pir_to_irr(vcpu);
3290
a92e2543 3291 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3292}
3293
3294static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3295 struct kvm_lapic_state *s)
3296{
a92e2543
RK		 3297 int r;
3298
3299 r = kvm_apic_set_state(vcpu, s);
3300 if (r)
3301 return r;
cb142eb7 3302 update_cr8_intercept(vcpu);
313a3dc7
CO		 3303
3304 return 0;
3305}
3306
127a457a
MG		 3307static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3308{
3309 return (!lapic_in_kernel(vcpu) ||
3310 kvm_apic_accept_pic_intr(vcpu));
3311}
3312
782d422b
MG		 3313/*
3314 * if userspace requested an interrupt window, check that the
3315 * interrupt window is open.
3316 *
3317 * No need to exit to userspace if we already have an interrupt queued.
3318 */
3319static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3320{
3321 return kvm_arch_interrupt_allowed(vcpu) &&
3322 !kvm_cpu_has_interrupt(vcpu) &&
3323 !kvm_event_needs_reinjection(vcpu) &&
3324 kvm_cpu_accept_dm_intr(vcpu);
3325}
3326
f77bc6a4
ZX		 3327static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3328 struct kvm_interrupt *irq)
3329{
02cdb50f 3330 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3331 return -EINVAL;
1c1a9ce9
SR		 3332
3333 if (!irqchip_in_kernel(vcpu->kvm)) {
3334 kvm_queue_interrupt(vcpu, irq->irq, false);
3335 kvm_make_request(KVM_REQ_EVENT, vcpu);
3336 return 0;
3337 }
3338
3339 /*
3340 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3341 * fail for in-kernel 8259.
3342 */
3343 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3344 return -ENXIO;
f77bc6a4 3345
1c1a9ce9
SR		 3346 if (vcpu->arch.pending_external_vector != -1)
3347 return -EEXIST;
f77bc6a4 3348
1c1a9ce9 3349 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3350 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3351 return 0;
3352}
3353
c4abb7c9
JK		 3354static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3355{
c4abb7c9 3356 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3357
3358 return 0;
3359}
3360
f077825a
PB		 3361static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3362{
64d60670
PB		 3363 kvm_make_request(KVM_REQ_SMI, vcpu);
3364
f077825a
PB		 3365 return 0;
3366}
3367
b209749f
AK		 3368static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3369 struct kvm_tpr_access_ctl *tac)
3370{
3371 if (tac->flags)
3372 return -EINVAL;
3373 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3374 return 0;
3375}
3376
890ca9ae
HY		 3377static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3378 u64 mcg_cap)
3379{
3380 int r;
3381 unsigned bank_num = mcg_cap & 0xff, bank;
3382
3383 r = -EINVAL;
a9e38c3e 3384 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3385 goto out;
c45dcc71 3386 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3387 goto out;
3388 r = 0;
3389 vcpu->arch.mcg_cap = mcg_cap;
3390 /* Init IA32_MCG_CTL to all 1s */
3391 if (mcg_cap & MCG_CTL_P)
3392 vcpu->arch.mcg_ctl = ~(u64)0;
3393 /* Init IA32_MCi_CTL to all 1s */
3394 for (bank = 0; bank < bank_num; bank++)
3395 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3396
3397 if (kvm_x86_ops->setup_mce)
3398 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3399out:
3400 return r;
3401}
3402
3403static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3404 struct kvm_x86_mce *mce)
3405{
3406 u64 mcg_cap = vcpu->arch.mcg_cap;
3407 unsigned bank_num = mcg_cap & 0xff;
3408 u64 *banks = vcpu->arch.mce_banks;
3409
3410 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3411 return -EINVAL;
3412 /*
3413 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3414 * reporting is disabled
3415 */
3416 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3417 vcpu->arch.mcg_ctl != ~(u64)0)
3418 return 0;
3419 banks += 4 * mce->bank;
3420 /*
3421 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3422 * reporting is disabled for the bank
3423 */
3424 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3425 return 0;
3426 if (mce->status & MCI_STATUS_UC) {
3427 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3428 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3429 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3430 return 0;
3431 }
3432 if (banks[1] & MCI_STATUS_VAL)
3433 mce->status |= MCI_STATUS_OVER;
3434 banks[2] = mce->addr;
3435 banks[3] = mce->misc;
3436 vcpu->arch.mcg_status = mce->mcg_status;
3437 banks[1] = mce->status;
3438 kvm_queue_exception(vcpu, MC_VECTOR);
3439 } else if (!(banks[1] & MCI_STATUS_VAL)
3440 || !(banks[1] & MCI_STATUS_UC)) {
3441 if (banks[1] & MCI_STATUS_VAL)
3442 mce->status |= MCI_STATUS_OVER;
3443 banks[2] = mce->addr;
3444 banks[3] = mce->misc;
3445 banks[1] = mce->status;
3446 } else
3447 banks[1] |= MCI_STATUS_OVER;
3448 return 0;
3449}
3450
3cfc3092
JK		 3451static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3452 struct kvm_vcpu_events *events)
3453{
7460fb4a 3454 process_nmi(vcpu);
59073aaf 3455
664f8e26 3456 /*
59073aaf
JM		 3457 * The API doesn't provide the instruction length for software
3458 * exceptions, so don't report them. As long as the guest RIP
3459 * isn't advanced, we should expect to encounter the exception
3460 * again.
664f8e26 3461 */
59073aaf
JM		 3462 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3463 events->exception.injected = 0;
3464 events->exception.pending = 0;
3465 } else {
3466 events->exception.injected = vcpu->arch.exception.injected;
3467 events->exception.pending = vcpu->arch.exception.pending;
3468 /*
3469 * For ABI compatibility, deliberately conflate
3470 * pending and injected exceptions when
3471 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3472 */
3473 if (!vcpu->kvm->arch.exception_payload_enabled)
3474 events->exception.injected |=
3475 vcpu->arch.exception.pending;
3476 }
3cfc3092
JK		 3477 events->exception.nr = vcpu->arch.exception.nr;
3478 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3479 events->exception.error_code = vcpu->arch.exception.error_code;
59073aaf
JM		 3480 events->exception_has_payload = vcpu->arch.exception.has_payload;
3481 events->exception_payload = vcpu->arch.exception.payload;
3cfc3092 3482
03b82a30 3483 events->interrupt.injected =
04140b41 3484 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3cfc3092 3485 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3486 events->interrupt.soft = 0;
37ccdcbe 3487 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3488
3489 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3490 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3491 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3492 events->nmi.pad = 0;
3cfc3092 3493
66450a21 3494 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3495
f077825a
PB		 3496 events->smi.smm = is_smm(vcpu);
3497 events->smi.pending = vcpu->arch.smi_pending;
3498 events->smi.smm_inside_nmi =
3499 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3500 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3501
dab4b911 3502 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3503 | KVM_VCPUEVENT_VALID_SHADOW
3504 | KVM_VCPUEVENT_VALID_SMM);
59073aaf
JM		 3505 if (vcpu->kvm->arch.exception_payload_enabled)
3506 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3507
97e69aa6 3508 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3509}
3510
6ef4e07e
XG		 3511static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3512
3cfc3092
JK		 3513static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3514 struct kvm_vcpu_events *events)
3515{
dab4b911 3516 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3517 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a 3518 | KVM_VCPUEVENT_VALID_SHADOW
59073aaf
JM		 3519 | KVM_VCPUEVENT_VALID_SMM
3520 | KVM_VCPUEVENT_VALID_PAYLOAD))
3cfc3092
JK		 3521 return -EINVAL;
3522
59073aaf
JM		 3523 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3524 if (!vcpu->kvm->arch.exception_payload_enabled)
3525 return -EINVAL;
3526 if (events->exception.pending)
3527 events->exception.injected = 0;
3528 else
3529 events->exception_has_payload = 0;
3530 } else {
3531 events->exception.pending = 0;
3532 events->exception_has_payload = 0;
3533 }
3534
3535 if ((events->exception.injected || events->exception.pending) &&
3536 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
78e546c8
PB		 3537 return -EINVAL;
3538
28bf2888
DH		 3539 /* INITs are latched while in SMM */
3540 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3541 (events->smi.smm || events->smi.pending) &&
3542 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3543 return -EINVAL;
3544
7460fb4a 3545 process_nmi(vcpu);
59073aaf
JM		 3546 vcpu->arch.exception.injected = events->exception.injected;
3547 vcpu->arch.exception.pending = events->exception.pending;
3cfc3092
JK		 3548 vcpu->arch.exception.nr = events->exception.nr;
3549 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3550 vcpu->arch.exception.error_code = events->exception.error_code;
59073aaf
JM		 3551 vcpu->arch.exception.has_payload = events->exception_has_payload;
3552 vcpu->arch.exception.payload = events->exception_payload;
3cfc3092 3553
04140b41 3554 vcpu->arch.interrupt.injected = events->interrupt.injected;
3cfc3092
JK		 3555 vcpu->arch.interrupt.nr = events->interrupt.nr;
3556 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3557 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3558 kvm_x86_ops->set_interrupt_shadow(vcpu,
3559 events->interrupt.shadow);
3cfc3092
JK		 3560
3561 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3562 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3563 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3564 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3565
66450a21 3566 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3567 lapic_in_kernel(vcpu))
66450a21 3568 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3569
f077825a 3570 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3571 u32 hflags = vcpu->arch.hflags;
f077825a 3572 if (events->smi.smm)
6ef4e07e 3573 hflags |= HF_SMM_MASK;
f077825a 3574 else
6ef4e07e
XG		 3575 hflags &= ~HF_SMM_MASK;
3576 kvm_set_hflags(vcpu, hflags);
3577
f077825a 3578 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3579
3580 if (events->smi.smm) {
3581 if (events->smi.smm_inside_nmi)
3582 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3583 else
f4ef1910
WL		 3584 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3585 if (lapic_in_kernel(vcpu)) {
3586 if (events->smi.latched_init)
3587 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3588 else
3589 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3590 }
f077825a
PB		 3591 }
3592 }
3593
3842d135
AK		 3594 kvm_make_request(KVM_REQ_EVENT, vcpu);
3595
3cfc3092
JK		 3596 return 0;
3597}
3598
a1efbe77
JK		 3599static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3600 struct kvm_debugregs *dbgregs)
3601{
73aaf249
JK		 3602 unsigned long val;
3603
a1efbe77 3604 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3605 kvm_get_dr(vcpu, 6, &val);
73aaf249 3606 dbgregs->dr6 = val;
a1efbe77
JK		 3607 dbgregs->dr7 = vcpu->arch.dr7;
3608 dbgregs->flags = 0;
97e69aa6 3609 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3610}
3611
3612static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3613 struct kvm_debugregs *dbgregs)
3614{
3615 if (dbgregs->flags)
3616 return -EINVAL;
3617
d14bdb55
PB		 3618 if (dbgregs->dr6 & ~0xffffffffull)
3619 return -EINVAL;
3620 if (dbgregs->dr7 & ~0xffffffffull)
3621 return -EINVAL;
3622
a1efbe77 3623 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3624 kvm_update_dr0123(vcpu);
a1efbe77 3625 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3626 kvm_update_dr6(vcpu);
a1efbe77 3627 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3628 kvm_update_dr7(vcpu);
a1efbe77 3629
a1efbe77
JK		 3630 return 0;
3631}
3632
df1daba7
PB		 3633#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3634
3635static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3636{
c47ada30 3637 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3638 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3639 u64 valid;
3640
3641 /*
3642 * Copy legacy XSAVE area, to avoid complications with CPUID
3643 * leaves 0 and 1 in the loop below.
3644 */
3645 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3646
3647 /* Set XSTATE_BV */
00c87e9a 3648 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3649 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3650
3651 /*
3652 * Copy each region from the possibly compacted offset to the
3653 * non-compacted offset.
3654 */
d91cab78 3655 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3656 while (valid) {
3657 u64 feature = valid & -valid;
3658 int index = fls64(feature) - 1;
3659 void *src = get_xsave_addr(xsave, feature);
3660
3661 if (src) {
3662 u32 size, offset, ecx, edx;
3663 cpuid_count(XSTATE_CPUID, index,
3664 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3665 if (feature == XFEATURE_MASK_PKRU)
3666 memcpy(dest + offset, &vcpu->arch.pkru,
3667 sizeof(vcpu->arch.pkru));
3668 else
3669 memcpy(dest + offset, src, size);
3670
df1daba7
PB		 3671 }
3672
3673 valid -= feature;
3674 }
3675}
3676
3677static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3678{
c47ada30 3679 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3680 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3681 u64 valid;
3682
3683 /*
3684 * Copy legacy XSAVE area, to avoid complications with CPUID
3685 * leaves 0 and 1 in the loop below.
3686 */
3687 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3688
3689 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3690 xsave->header.xfeatures = xstate_bv;
782511b0 3691 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3692 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3693
3694 /*
3695 * Copy each region from the non-compacted offset to the
3696 * possibly compacted offset.
3697 */
d91cab78 3698 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3699 while (valid) {
3700 u64 feature = valid & -valid;
3701 int index = fls64(feature) - 1;
3702 void *dest = get_xsave_addr(xsave, feature);
3703
3704 if (dest) {
3705 u32 size, offset, ecx, edx;
3706 cpuid_count(XSTATE_CPUID, index,
3707 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3708 if (feature == XFEATURE_MASK_PKRU)
3709 memcpy(&vcpu->arch.pkru, src + offset,
3710 sizeof(vcpu->arch.pkru));
3711 else
3712 memcpy(dest, src + offset, size);
ee4100da 3713 }
df1daba7
PB		 3714
3715 valid -= feature;
3716 }
3717}
3718
2d5b5a66
SY		 3719static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3720 struct kvm_xsave *guest_xsave)
3721{
d366bf7e 3722 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3723 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3724 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3725 } else {
2d5b5a66 3726 memcpy(guest_xsave->region,
7366ed77 3727 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3728 sizeof(struct fxregs_state));
2d5b5a66 3729 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3730 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3731 }
3732}
3733
a575813b
WL		 3734#define XSAVE_MXCSR_OFFSET 24
3735
2d5b5a66
SY		 3736static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3737 struct kvm_xsave *guest_xsave)
3738{
3739 u64 xstate_bv =
3740 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3741 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3742
d366bf7e 3743 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3744 /*
3745 * Here we allow setting states that are not present in
3746 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3747 * with old userspace.
3748 */
a575813b
WL		 3749 if (xstate_bv & ~kvm_supported_xcr0() ||
3750 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3751 return -EINVAL;
df1daba7 3752 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3753 } else {
a575813b
WL		 3754 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3755 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3756 return -EINVAL;
7366ed77 3757 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3758 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3759 }
3760 return 0;
3761}
3762
3763static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3764 struct kvm_xcrs *guest_xcrs)
3765{
d366bf7e 3766 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3767 guest_xcrs->nr_xcrs = 0;
3768 return;
3769 }
3770
3771 guest_xcrs->nr_xcrs = 1;
3772 guest_xcrs->flags = 0;
3773 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3774 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3775}
3776
3777static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3778 struct kvm_xcrs *guest_xcrs)
3779{
3780 int i, r = 0;
3781
d366bf7e 3782 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3783 return -EINVAL;
3784
3785 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3786 return -EINVAL;
3787
3788 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3789 /* Only support XCR0 currently */
c67a04cb 3790 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3791 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3792 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3793 break;
3794 }
3795 if (r)
3796 r = -EINVAL;
3797 return r;
3798}
3799
1c0b28c2
EM		 3800/*
3801 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3802 * stopped by the hypervisor. This function will be called from the host only.
3803 * EINVAL is returned when the host attempts to set the flag for a guest that
3804 * does not support pv clocks.
3805 */
3806static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3807{
0b79459b 3808 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3809 return -EINVAL;
51d59c6b 3810 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3811 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3812 return 0;
3813}
3814
5c919412
AS		 3815static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3816 struct kvm_enable_cap *cap)
3817{
57b119da
VK		 3818 int r;
3819 uint16_t vmcs_version;
3820 void __user *user_ptr;
3821
5c919412
AS		 3822 if (cap->flags)
3823 return -EINVAL;
3824
3825 switch (cap->cap) {
efc479e6
RK		 3826 case KVM_CAP_HYPERV_SYNIC2:
3827 if (cap->args[0])
3828 return -EINVAL;
5c919412 3829 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3830 if (!irqchip_in_kernel(vcpu->kvm))
3831 return -EINVAL;
efc479e6
RK		 3832 return kvm_hv_activate_synic(vcpu, cap->cap ==
3833 KVM_CAP_HYPERV_SYNIC2);
57b119da
VK		 3834 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3835 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
3836 if (!r) {
3837 user_ptr = (void __user *)(uintptr_t)cap->args[0];
3838 if (copy_to_user(user_ptr, &vmcs_version,
3839 sizeof(vmcs_version)))
3840 r = -EFAULT;
3841 }
3842 return r;
3843
5c919412
AS		 3844 default:
3845 return -EINVAL;
3846 }
3847}
3848
313a3dc7
CO		 3849long kvm_arch_vcpu_ioctl(struct file *filp,
3850 unsigned int ioctl, unsigned long arg)
3851{
3852 struct kvm_vcpu *vcpu = filp->private_data;
3853 void __user *argp = (void __user *)arg;
3854 int r;
d1ac91d8
AK		 3855 union {
3856 struct kvm_lapic_state *lapic;
3857 struct kvm_xsave *xsave;
3858 struct kvm_xcrs *xcrs;
3859 void *buffer;
3860 } u;
3861
9b062471
CD		 3862 vcpu_load(vcpu);
3863
d1ac91d8 3864 u.buffer = NULL;
313a3dc7
CO		 3865 switch (ioctl) {
3866 case KVM_GET_LAPIC: {
2204ae3c 3867 r = -EINVAL;
bce87cce 3868 if (!lapic_in_kernel(vcpu))
2204ae3c 3869 goto out;
d1ac91d8 3870 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3871
b772ff36 3872 r = -ENOMEM;
d1ac91d8 3873 if (!u.lapic)
b772ff36 3874 goto out;
d1ac91d8 3875 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3876 if (r)
3877 goto out;
3878 r = -EFAULT;
d1ac91d8 3879 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3880 goto out;
3881 r = 0;
3882 break;
3883 }
3884 case KVM_SET_LAPIC: {
2204ae3c 3885 r = -EINVAL;
bce87cce 3886 if (!lapic_in_kernel(vcpu))
2204ae3c 3887 goto out;
ff5c2c03 3888 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3889 if (IS_ERR(u.lapic)) {
3890 r = PTR_ERR(u.lapic);
3891 goto out_nofree;
3892 }
ff5c2c03 3893
d1ac91d8 3894 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3895 break;
3896 }
f77bc6a4
ZX		 3897 case KVM_INTERRUPT: {
3898 struct kvm_interrupt irq;
3899
3900 r = -EFAULT;
3901 if (copy_from_user(&irq, argp, sizeof irq))
3902 goto out;
3903 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3904 break;
3905 }
c4abb7c9
JK		 3906 case KVM_NMI: {
3907 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3908 break;
3909 }
f077825a
PB		 3910 case KVM_SMI: {
3911 r = kvm_vcpu_ioctl_smi(vcpu);
3912 break;
3913 }
313a3dc7
CO		 3914 case KVM_SET_CPUID: {
3915 struct kvm_cpuid __user *cpuid_arg = argp;
3916 struct kvm_cpuid cpuid;
3917
3918 r = -EFAULT;
3919 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3920 goto out;
3921 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3922 break;
3923 }
07716717
DK		 3924 case KVM_SET_CPUID2: {
3925 struct kvm_cpuid2 __user *cpuid_arg = argp;
3926 struct kvm_cpuid2 cpuid;
3927
3928 r = -EFAULT;
3929 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3930 goto out;
3931 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3932 cpuid_arg->entries);
07716717
DK		 3933 break;
3934 }
3935 case KVM_GET_CPUID2: {
3936 struct kvm_cpuid2 __user *cpuid_arg = argp;
3937 struct kvm_cpuid2 cpuid;
3938
3939 r = -EFAULT;
3940 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3941 goto out;
3942 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3943 cpuid_arg->entries);
07716717
DK		 3944 if (r)
3945 goto out;
3946 r = -EFAULT;
3947 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3948 goto out;
3949 r = 0;
3950 break;
3951 }
801e459a
TL		 3952 case KVM_GET_MSRS: {
3953 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 3954 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 3955 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3956 break;
801e459a
TL		 3957 }
3958 case KVM_SET_MSRS: {
3959 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 3960 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 3961 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3962 break;
801e459a 3963 }
b209749f
AK		 3964 case KVM_TPR_ACCESS_REPORTING: {
3965 struct kvm_tpr_access_ctl tac;
3966
3967 r = -EFAULT;
3968 if (copy_from_user(&tac, argp, sizeof tac))
3969 goto out;
3970 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3971 if (r)
3972 goto out;
3973 r = -EFAULT;
3974 if (copy_to_user(argp, &tac, sizeof tac))
3975 goto out;
3976 r = 0;
3977 break;
3978 };
b93463aa
AK		 3979 case KVM_SET_VAPIC_ADDR: {
3980 struct kvm_vapic_addr va;
7301d6ab 3981 int idx;
b93463aa
AK		 3982
3983 r = -EINVAL;
35754c98 3984 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3985 goto out;
3986 r = -EFAULT;
3987 if (copy_from_user(&va, argp, sizeof va))
3988 goto out;
7301d6ab 3989 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3990 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3991 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3992 break;
3993 }
890ca9ae
HY		 3994 case KVM_X86_SETUP_MCE: {
3995 u64 mcg_cap;
3996
3997 r = -EFAULT;
3998 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3999 goto out;
4000 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4001 break;
4002 }
4003 case KVM_X86_SET_MCE: {
4004 struct kvm_x86_mce mce;
4005
4006 r = -EFAULT;
4007 if (copy_from_user(&mce, argp, sizeof mce))
4008 goto out;
4009 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4010 break;
4011 }
3cfc3092
JK		 4012 case KVM_GET_VCPU_EVENTS: {
4013 struct kvm_vcpu_events events;
4014
4015 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4016
4017 r = -EFAULT;
4018 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4019 break;
4020 r = 0;
4021 break;
4022 }
4023 case KVM_SET_VCPU_EVENTS: {
4024 struct kvm_vcpu_events events;
4025
4026 r = -EFAULT;
4027 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4028 break;
4029
4030 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4031 break;
4032 }
a1efbe77
JK		 4033 case KVM_GET_DEBUGREGS: {
4034 struct kvm_debugregs dbgregs;
4035
4036 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4037
4038 r = -EFAULT;
4039 if (copy_to_user(argp, &dbgregs,
4040 sizeof(struct kvm_debugregs)))
4041 break;
4042 r = 0;
4043 break;
4044 }
4045 case KVM_SET_DEBUGREGS: {
4046 struct kvm_debugregs dbgregs;
4047
4048 r = -EFAULT;
4049 if (copy_from_user(&dbgregs, argp,
4050 sizeof(struct kvm_debugregs)))
4051 break;
4052
4053 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4054 break;
4055 }
2d5b5a66 4056 case KVM_GET_XSAVE: {
d1ac91d8 4057 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 4058 r = -ENOMEM;
d1ac91d8 4059 if (!u.xsave)
2d5b5a66
SY		 4060 break;
4061
d1ac91d8 4062 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4063
4064 r = -EFAULT;
d1ac91d8 4065 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 4066 break;
4067 r = 0;
4068 break;
4069 }
4070 case KVM_SET_XSAVE: {
ff5c2c03 4071 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 4072 if (IS_ERR(u.xsave)) {
4073 r = PTR_ERR(u.xsave);
4074 goto out_nofree;
4075 }
2d5b5a66 4076
d1ac91d8 4077 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4078 break;
4079 }
4080 case KVM_GET_XCRS: {
d1ac91d8 4081 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 4082 r = -ENOMEM;
d1ac91d8 4083 if (!u.xcrs)
2d5b5a66
SY		 4084 break;
4085
d1ac91d8 4086 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4087
4088 r = -EFAULT;
d1ac91d8 4089 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 4090 sizeof(struct kvm_xcrs)))
4091 break;
4092 r = 0;
4093 break;
4094 }
4095 case KVM_SET_XCRS: {
ff5c2c03 4096 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 4097 if (IS_ERR(u.xcrs)) {
4098 r = PTR_ERR(u.xcrs);
4099 goto out_nofree;
4100 }
2d5b5a66 4101
d1ac91d8 4102 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4103 break;
4104 }
92a1f12d
JR		 4105 case KVM_SET_TSC_KHZ: {
4106 u32 user_tsc_khz;
4107
4108 r = -EINVAL;
92a1f12d
JR		 4109 user_tsc_khz = (u32)arg;
4110
4111 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4112 goto out;
4113
cc578287
ZA		 4114 if (user_tsc_khz == 0)
4115 user_tsc_khz = tsc_khz;
4116
381d585c
HZ		 4117 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4118 r = 0;
92a1f12d 4119
92a1f12d
JR		 4120 goto out;
4121 }
4122 case KVM_GET_TSC_KHZ: {
cc578287 4123 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 4124 goto out;
4125 }
1c0b28c2
EM		 4126 case KVM_KVMCLOCK_CTRL: {
4127 r = kvm_set_guest_paused(vcpu);
4128 goto out;
4129 }
5c919412
AS		 4130 case KVM_ENABLE_CAP: {
4131 struct kvm_enable_cap cap;
4132
4133 r = -EFAULT;
4134 if (copy_from_user(&cap, argp, sizeof(cap)))
4135 goto out;
4136 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4137 break;
4138 }
8fcc4b59
JM		 4139 case KVM_GET_NESTED_STATE: {
4140 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4141 u32 user_data_size;
4142
4143 r = -EINVAL;
4144 if (!kvm_x86_ops->get_nested_state)
4145 break;
4146
4147 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
26b471c7 4148 r = -EFAULT;
8fcc4b59 4149 if (get_user(user_data_size, &user_kvm_nested_state->size))
26b471c7 4150 break;
8fcc4b59
JM		 4151
4152 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4153 user_data_size);
4154 if (r < 0)
26b471c7 4155 break;
8fcc4b59
JM		 4156
4157 if (r > user_data_size) {
4158 if (put_user(r, &user_kvm_nested_state->size))
26b471c7
LA		 4159 r = -EFAULT;
4160 else
4161 r = -E2BIG;
4162 break;
8fcc4b59 4163 }
26b471c7 4164
8fcc4b59
JM		 4165 r = 0;
4166 break;
4167 }
4168 case KVM_SET_NESTED_STATE: {
4169 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4170 struct kvm_nested_state kvm_state;
4171
4172 r = -EINVAL;
4173 if (!kvm_x86_ops->set_nested_state)
4174 break;
4175
26b471c7 4176 r = -EFAULT;
8fcc4b59 4177 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
26b471c7 4178 break;
8fcc4b59 4179
26b471c7 4180 r = -EINVAL;
8fcc4b59 4181 if (kvm_state.size < sizeof(kvm_state))
26b471c7 4182 break;
8fcc4b59
JM		 4183
4184 if (kvm_state.flags &
8cab6507
VK		 4185 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4186 | KVM_STATE_NESTED_EVMCS))
26b471c7 4187 break;
8fcc4b59
JM		 4188
4189 /* nested_run_pending implies guest_mode. */
8cab6507
VK		 4190 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4191 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
26b471c7 4192 break;
8fcc4b59
JM		 4193
4194 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4195 break;
4196 }
313a3dc7
CO		 4197 default:
4198 r = -EINVAL;
4199 }
4200out:
d1ac91d8 4201 kfree(u.buffer);
9b062471
CD		 4202out_nofree:
4203 vcpu_put(vcpu);
313a3dc7
CO		 4204 return r;
4205}
4206
1499fa80 4207vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5b1c1493
CO		 4208{
4209 return VM_FAULT_SIGBUS;
4210}
4211
1fe779f8
CO		 4212static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4213{
4214 int ret;
4215
4216 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 4217 return -EINVAL;
1fe779f8
CO		 4218 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4219 return ret;
4220}
4221
b927a3ce
SY		 4222static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4223 u64 ident_addr)
4224{
2ac52ab8 4225 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 4226}
4227
1fe779f8
CO		 4228static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4229 u32 kvm_nr_mmu_pages)
4230{
4231 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4232 return -EINVAL;
4233
79fac95e 4234 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 4235
4236 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 4237 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 4238
79fac95e 4239 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 4240 return 0;
4241}
4242
4243static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4244{
39de71ec 4245 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 4246}
4247
1fe779f8
CO		 4248static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4249{
90bca052 4250 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4251 int r;
4252
4253 r = 0;
4254 switch (chip->chip_id) {
4255 case KVM_IRQCHIP_PIC_MASTER:
90bca052 4256 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 4257 sizeof(struct kvm_pic_state));
4258 break;
4259 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 4260 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 4261 sizeof(struct kvm_pic_state));
4262 break;
4263 case KVM_IRQCHIP_IOAPIC:
33392b49 4264 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4265 break;
4266 default:
4267 r = -EINVAL;
4268 break;
4269 }
4270 return r;
4271}
4272
4273static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4274{
90bca052 4275 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4276 int r;
4277
4278 r = 0;
4279 switch (chip->chip_id) {
4280 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4281 spin_lock(&pic->lock);
4282 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4283 sizeof(struct kvm_pic_state));
90bca052 4284 spin_unlock(&pic->lock);
1fe779f8
CO		 4285 break;
4286 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4287 spin_lock(&pic->lock);
4288 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4289 sizeof(struct kvm_pic_state));
90bca052 4290 spin_unlock(&pic->lock);
1fe779f8
CO		 4291 break;
4292 case KVM_IRQCHIP_IOAPIC:
33392b49 4293 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4294 break;
4295 default:
4296 r = -EINVAL;
4297 break;
4298 }
90bca052 4299 kvm_pic_update_irq(pic);
1fe779f8
CO		 4300 return r;
4301}
4302
e0f63cb9
SY		 4303static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4304{
34f3941c
RK		 4305 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4306
4307 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4308
4309 mutex_lock(&kps->lock);
4310 memcpy(ps, &kps->channels, sizeof(*ps));
4311 mutex_unlock(&kps->lock);
2da29bcc 4312 return 0;
e0f63cb9
SY		 4313}
4314
4315static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4316{
0185604c 4317 int i;
09edea72
RK		 4318 struct kvm_pit *pit = kvm->arch.vpit;
4319
4320 mutex_lock(&pit->pit_state.lock);
34f3941c 4321 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4322 for (i = 0; i < 3; i++)
09edea72
RK		 4323 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4324 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4325 return 0;
e9f42757
BK		 4326}
4327
4328static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4329{
e9f42757
BK		 4330 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4331 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4332 sizeof(ps->channels));
4333 ps->flags = kvm->arch.vpit->pit_state.flags;
4334 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4335 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4336 return 0;
e9f42757
BK		 4337}
4338
4339static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4340{
2da29bcc 4341 int start = 0;
0185604c 4342 int i;
e9f42757 4343 u32 prev_legacy, cur_legacy;
09edea72
RK		 4344 struct kvm_pit *pit = kvm->arch.vpit;
4345
4346 mutex_lock(&pit->pit_state.lock);
4347 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4348 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4349 if (!prev_legacy && cur_legacy)
4350 start = 1;
09edea72
RK		 4351 memcpy(&pit->pit_state.channels, &ps->channels,
4352 sizeof(pit->pit_state.channels));
4353 pit->pit_state.flags = ps->flags;
0185604c 4354 for (i = 0; i < 3; i++)
09edea72 4355 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4356 start && i == 0);
09edea72 4357 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4358 return 0;
e0f63cb9
SY		 4359}
4360
52d939a0
MT		 4361static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4362 struct kvm_reinject_control *control)
4363{
71474e2f
RK		 4364 struct kvm_pit *pit = kvm->arch.vpit;
4365
4366 if (!pit)
52d939a0 4367 return -ENXIO;
b39c90b6 4368
71474e2f
RK		 4369 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4370 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4371 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4372 */
4373 mutex_lock(&pit->pit_state.lock);
4374 kvm_pit_set_reinject(pit, control->pit_reinject);
4375 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4376
52d939a0
MT		 4377 return 0;
4378}
4379
95d4c16c 4380/**
60c34612
TY		 4381 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4382 * @kvm: kvm instance
4383 * @log: slot id and address to which we copy the log
95d4c16c 4384 *
e108ff2f
PB		 4385 * Steps 1-4 below provide general overview of dirty page logging. See
4386 * kvm_get_dirty_log_protect() function description for additional details.
4387 *
4388 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4389 * always flush the TLB (step 4) even if previous step failed and the dirty
4390 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4391 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4392 * writes will be marked dirty for next log read.
95d4c16c 4393 *
60c34612
TY		 4394 * 1. Take a snapshot of the bit and clear it if needed.
4395 * 2. Write protect the corresponding page.
e108ff2f
PB		 4396 * 3. Copy the snapshot to the userspace.
4397 * 4. Flush TLB's if needed.
5bb064dc 4398 */
60c34612 4399int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4400{
60c34612 4401 bool is_dirty = false;
e108ff2f 4402 int r;
5bb064dc 4403
79fac95e 4404 mutex_lock(&kvm->slots_lock);
5bb064dc 4405
88178fd4
KH		 4406 /*
4407 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4408 */
4409 if (kvm_x86_ops->flush_log_dirty)
4410 kvm_x86_ops->flush_log_dirty(kvm);
4411
e108ff2f 4412 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 4413
4414 /*
4415 * All the TLBs can be flushed out of mmu lock, see the comments in
4416 * kvm_mmu_slot_remove_write_access().
4417 */
e108ff2f 4418 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 4419 if (is_dirty)
4420 kvm_flush_remote_tlbs(kvm);
4421
79fac95e 4422 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4423 return r;
4424}
4425
aa2fbe6d
YZ		 4426int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4427 bool line_status)
23d43cf9
CD		 4428{
4429 if (!irqchip_in_kernel(kvm))
4430 return -ENXIO;
4431
4432 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4433 irq_event->irq, irq_event->level,
4434 line_status);
23d43cf9
CD		 4435 return 0;
4436}
4437
90de4a18
NA		 4438static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4439 struct kvm_enable_cap *cap)
4440{
4441 int r;
4442
4443 if (cap->flags)
4444 return -EINVAL;
4445
4446 switch (cap->cap) {
4447 case KVM_CAP_DISABLE_QUIRKS:
4448 kvm->arch.disabled_quirks = cap->args[0];
4449 r = 0;
4450 break;
49df6397
SR		 4451 case KVM_CAP_SPLIT_IRQCHIP: {
4452 mutex_lock(&kvm->lock);
b053b2ae
SR		 4453 r = -EINVAL;
4454 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4455 goto split_irqchip_unlock;
49df6397
SR		 4456 r = -EEXIST;
4457 if (irqchip_in_kernel(kvm))
4458 goto split_irqchip_unlock;
557abc40 4459 if (kvm->created_vcpus)
49df6397
SR		 4460 goto split_irqchip_unlock;
4461 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4462 if (r)
49df6397
SR		 4463 goto split_irqchip_unlock;
4464 /* Pairs with irqchip_in_kernel. */
4465 smp_wmb();
49776faf 4466 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4467 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4468 r = 0;
4469split_irqchip_unlock:
4470 mutex_unlock(&kvm->lock);
4471 break;
4472 }
37131313
RK		 4473 case KVM_CAP_X2APIC_API:
4474 r = -EINVAL;
4475 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4476 break;
4477
4478 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4479 kvm->arch.x2apic_format = true;
c519265f
RK		 4480 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4481 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4482
4483 r = 0;
4484 break;
4d5422ce
WL		 4485 case KVM_CAP_X86_DISABLE_EXITS:
4486 r = -EINVAL;
4487 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4488 break;
4489
4490 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4491 kvm_can_mwait_in_guest())
4492 kvm->arch.mwait_in_guest = true;
766d3571 4493 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
caa057a2 4494 kvm->arch.hlt_in_guest = true;
b31c114b
WL		 4495 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4496 kvm->arch.pause_in_guest = true;
4d5422ce
WL		 4497 r = 0;
4498 break;
6fbbde9a
DS		 4499 case KVM_CAP_MSR_PLATFORM_INFO:
4500 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4501 r = 0;
4502 break;
90de4a18
NA		 4503 default:
4504 r = -EINVAL;
4505 break;
4506 }
4507 return r;
4508}
4509
1fe779f8
CO		 4510long kvm_arch_vm_ioctl(struct file *filp,
4511 unsigned int ioctl, unsigned long arg)
4512{
4513 struct kvm *kvm = filp->private_data;
4514 void __user *argp = (void __user *)arg;
367e1319 4515 int r = -ENOTTY;
f0d66275
DH		 4516 /*
4517 * This union makes it completely explicit to gcc-3.x
4518 * that these two variables' stack usage should be
4519 * combined, not added together.
4520 */
4521 union {
4522 struct kvm_pit_state ps;
e9f42757 4523 struct kvm_pit_state2 ps2;
c5ff41ce 4524 struct kvm_pit_config pit_config;
f0d66275 4525 } u;
1fe779f8
CO		 4526
4527 switch (ioctl) {
4528 case KVM_SET_TSS_ADDR:
4529 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4530 break;
b927a3ce
SY		 4531 case KVM_SET_IDENTITY_MAP_ADDR: {
4532 u64 ident_addr;
4533
1af1ac91
DH		 4534 mutex_lock(&kvm->lock);
4535 r = -EINVAL;
4536 if (kvm->created_vcpus)
4537 goto set_identity_unlock;
b927a3ce
SY		 4538 r = -EFAULT;
4539 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4540 goto set_identity_unlock;
b927a3ce 4541 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4542set_identity_unlock:
4543 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4544 break;
4545 }
1fe779f8
CO		 4546 case KVM_SET_NR_MMU_PAGES:
4547 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4548 break;
4549 case KVM_GET_NR_MMU_PAGES:
4550 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4551 break;
3ddea128 4552 case KVM_CREATE_IRQCHIP: {
3ddea128 4553 mutex_lock(&kvm->lock);
09941366 4554
3ddea128 4555 r = -EEXIST;
35e6eaa3 4556 if (irqchip_in_kernel(kvm))
3ddea128 4557 goto create_irqchip_unlock;
09941366 4558
3e515705 4559 r = -EINVAL;
557abc40 4560 if (kvm->created_vcpus)
3e515705 4561 goto create_irqchip_unlock;
09941366
RK		 4562
4563 r = kvm_pic_init(kvm);
4564 if (r)
3ddea128 4565 goto create_irqchip_unlock;
09941366
RK		 4566
4567 r = kvm_ioapic_init(kvm);
4568 if (r) {
09941366 4569 kvm_pic_destroy(kvm);
3ddea128 4570 goto create_irqchip_unlock;
09941366
RK		 4571 }
4572
399ec807
AK		 4573 r = kvm_setup_default_irq_routing(kvm);
4574 if (r) {
72bb2fcd 4575 kvm_ioapic_destroy(kvm);
09941366 4576 kvm_pic_destroy(kvm);
71ba994c 4577 goto create_irqchip_unlock;
399ec807 4578 }
49776faf 4579 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4580 smp_wmb();
49776faf 4581 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4582 create_irqchip_unlock:
4583 mutex_unlock(&kvm->lock);
1fe779f8 4584 break;
3ddea128 4585 }
7837699f 4586 case KVM_CREATE_PIT:
c5ff41ce
JK		 4587 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4588 goto create_pit;
4589 case KVM_CREATE_PIT2:
4590 r = -EFAULT;
4591 if (copy_from_user(&u.pit_config, argp,
4592 sizeof(struct kvm_pit_config)))
4593 goto out;
4594 create_pit:
250715a6 4595 mutex_lock(&kvm->lock);
269e05e4
AK		 4596 r = -EEXIST;
4597 if (kvm->arch.vpit)
4598 goto create_pit_unlock;
7837699f 4599 r = -ENOMEM;
c5ff41ce 4600 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4601 if (kvm->arch.vpit)
4602 r = 0;
269e05e4 4603 create_pit_unlock:
250715a6 4604 mutex_unlock(&kvm->lock);
7837699f 4605 break;
1fe779f8
CO		 4606 case KVM_GET_IRQCHIP: {
4607 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4608 struct kvm_irqchip *chip;
1fe779f8 4609
ff5c2c03
SL		 4610 chip = memdup_user(argp, sizeof(*chip));
4611 if (IS_ERR(chip)) {
4612 r = PTR_ERR(chip);
1fe779f8 4613 goto out;
ff5c2c03
SL		 4614 }
4615
1fe779f8 4616 r = -ENXIO;
826da321 4617 if (!irqchip_kernel(kvm))
f0d66275
DH		 4618 goto get_irqchip_out;
4619 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4620 if (r)
f0d66275 4621 goto get_irqchip_out;
1fe779f8 4622 r = -EFAULT;
f0d66275
DH		 4623 if (copy_to_user(argp, chip, sizeof *chip))
4624 goto get_irqchip_out;
1fe779f8 4625 r = 0;
f0d66275
DH		 4626 get_irqchip_out:
4627 kfree(chip);
1fe779f8
CO		 4628 break;
4629 }
4630 case KVM_SET_IRQCHIP: {
4631 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4632 struct kvm_irqchip *chip;
1fe779f8 4633
ff5c2c03
SL		 4634 chip = memdup_user(argp, sizeof(*chip));
4635 if (IS_ERR(chip)) {
4636 r = PTR_ERR(chip);
1fe779f8 4637 goto out;
ff5c2c03
SL		 4638 }
4639
1fe779f8 4640 r = -ENXIO;
826da321 4641 if (!irqchip_kernel(kvm))
f0d66275
DH		 4642 goto set_irqchip_out;
4643 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4644 if (r)
f0d66275 4645 goto set_irqchip_out;
1fe779f8 4646 r = 0;
f0d66275
DH		 4647 set_irqchip_out:
4648 kfree(chip);
1fe779f8
CO		 4649 break;
4650 }
e0f63cb9 4651 case KVM_GET_PIT: {
e0f63cb9 4652 r = -EFAULT;
f0d66275 4653 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4654 goto out;
4655 r = -ENXIO;
4656 if (!kvm->arch.vpit)
4657 goto out;
f0d66275 4658 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4659 if (r)
4660 goto out;
4661 r = -EFAULT;
f0d66275 4662 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4663 goto out;
4664 r = 0;
4665 break;
4666 }
4667 case KVM_SET_PIT: {
e0f63cb9 4668 r = -EFAULT;
f0d66275 4669 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4670 goto out;
4671 r = -ENXIO;
4672 if (!kvm->arch.vpit)
4673 goto out;
f0d66275 4674 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4675 break;
4676 }
e9f42757
BK		 4677 case KVM_GET_PIT2: {
4678 r = -ENXIO;
4679 if (!kvm->arch.vpit)
4680 goto out;
4681 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4682 if (r)
4683 goto out;
4684 r = -EFAULT;
4685 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4686 goto out;
4687 r = 0;
4688 break;
4689 }
4690 case KVM_SET_PIT2: {
4691 r = -EFAULT;
4692 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4693 goto out;
4694 r = -ENXIO;
4695 if (!kvm->arch.vpit)
4696 goto out;
4697 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4698 break;
4699 }
52d939a0
MT		 4700 case KVM_REINJECT_CONTROL: {
4701 struct kvm_reinject_control control;
4702 r = -EFAULT;
4703 if (copy_from_user(&control, argp, sizeof(control)))
4704 goto out;
4705 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4706 break;
4707 }
d71ba788
PB		 4708 case KVM_SET_BOOT_CPU_ID:
4709 r = 0;
4710 mutex_lock(&kvm->lock);
557abc40 4711 if (kvm->created_vcpus)
d71ba788
PB		 4712 r = -EBUSY;
4713 else
4714 kvm->arch.bsp_vcpu_id = arg;
4715 mutex_unlock(&kvm->lock);
4716 break;
ffde22ac 4717 case KVM_XEN_HVM_CONFIG: {
51776043 4718 struct kvm_xen_hvm_config xhc;
ffde22ac 4719 r = -EFAULT;
51776043 4720 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4721 goto out;
4722 r = -EINVAL;
51776043 4723 if (xhc.flags)
ffde22ac 4724 goto out;
51776043 4725 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4726 r = 0;
4727 break;
4728 }
afbcf7ab 4729 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4730 struct kvm_clock_data user_ns;
4731 u64 now_ns;
afbcf7ab
GC		 4732
4733 r = -EFAULT;
4734 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4735 goto out;
4736
4737 r = -EINVAL;
4738 if (user_ns.flags)
4739 goto out;
4740
4741 r = 0;
0bc48bea
RK		 4742 /*
4743 * TODO: userspace has to take care of races with VCPU_RUN, so
4744 * kvm_gen_update_masterclock() can be cut down to locked
4745 * pvclock_update_vm_gtod_copy().
4746 */
4747 kvm_gen_update_masterclock(kvm);
e891a32e 4748 now_ns = get_kvmclock_ns(kvm);
108b249c 4749 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4750 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4751 break;
4752 }
4753 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4754 struct kvm_clock_data user_ns;
4755 u64 now_ns;
4756
e891a32e 4757 now_ns = get_kvmclock_ns(kvm);
108b249c 4758 user_ns.clock = now_ns;
e3fd9a93 4759 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4760 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4761
4762 r = -EFAULT;
4763 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4764 goto out;
4765 r = 0;
4766 break;
4767 }
90de4a18
NA		 4768 case KVM_ENABLE_CAP: {
4769 struct kvm_enable_cap cap;
afbcf7ab 4770
90de4a18
NA		 4771 r = -EFAULT;
4772 if (copy_from_user(&cap, argp, sizeof(cap)))
4773 goto out;
4774 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4775 break;
4776 }
5acc5c06
BS		 4777 case KVM_MEMORY_ENCRYPT_OP: {
4778 r = -ENOTTY;
4779 if (kvm_x86_ops->mem_enc_op)
4780 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4781 break;
4782 }
69eaedee
BS		 4783 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4784 struct kvm_enc_region region;
4785
4786 r = -EFAULT;
4787 if (copy_from_user(&region, argp, sizeof(region)))
4788 goto out;
4789
4790 r = -ENOTTY;
4791 if (kvm_x86_ops->mem_enc_reg_region)
4792 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4793 break;
4794 }
4795 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4796 struct kvm_enc_region region;
4797
4798 r = -EFAULT;
4799 if (copy_from_user(&region, argp, sizeof(region)))
4800 goto out;
4801
4802 r = -ENOTTY;
4803 if (kvm_x86_ops->mem_enc_unreg_region)
4804 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4805 break;
4806 }
faeb7833
RK		 4807 case KVM_HYPERV_EVENTFD: {
4808 struct kvm_hyperv_eventfd hvevfd;
4809
4810 r = -EFAULT;
4811 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4812 goto out;
4813 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4814 break;
4815 }
1fe779f8 4816 default:
ad6260da 4817 r = -ENOTTY;
1fe779f8
CO		 4818 }
4819out:
4820 return r;
4821}
4822
a16b043c 4823static void kvm_init_msr_list(void)
043405e1
CO		 4824{
4825 u32 dummy[2];
4826 unsigned i, j;
4827
62ef68bb 4828 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4829 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4830 continue;
93c4adc7
PB		 4831
4832 /*
4833 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4834 * to the guests in some cases.
93c4adc7
PB		 4835 */
4836 switch (msrs_to_save[i]) {
4837 case MSR_IA32_BNDCFGS:
503234b3 4838 if (!kvm_mpx_supported())
93c4adc7
PB		 4839 continue;
4840 break;
9dbe6cf9
PB		 4841 case MSR_TSC_AUX:
4842 if (!kvm_x86_ops->rdtscp_supported())
4843 continue;
4844 break;
93c4adc7
PB		 4845 default:
4846 break;
4847 }
4848
043405e1
CO		 4849 if (j < i)
4850 msrs_to_save[j] = msrs_to_save[i];
4851 j++;
4852 }
4853 num_msrs_to_save = j;
62ef68bb
PB		 4854
4855 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
bc226f07
TL		 4856 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
4857 continue;
62ef68bb
PB		 4858
4859 if (j < i)
4860 emulated_msrs[j] = emulated_msrs[i];
4861 j++;
4862 }
4863 num_emulated_msrs = j;
801e459a
TL		 4864
4865 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4866 struct kvm_msr_entry msr;
4867
4868 msr.index = msr_based_features[i];
66421c1e 4869 if (kvm_get_msr_feature(&msr))
801e459a
TL		 4870 continue;
4871
4872 if (j < i)
4873 msr_based_features[j] = msr_based_features[i];
4874 j++;
4875 }
4876 num_msr_based_features = j;
043405e1
CO		 4877}
4878
bda9020e
MT		 4879static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4880 const void *v)
bbd9b64e 4881{
70252a10
AK		 4882 int handled = 0;
4883 int n;
4884
4885 do {
4886 n = min(len, 8);
bce87cce 4887 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4888 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4889 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4890 break;
4891 handled += n;
4892 addr += n;
4893 len -= n;
4894 v += n;
4895 } while (len);
bbd9b64e 4896
70252a10 4897 return handled;
bbd9b64e
CO		 4898}
4899
bda9020e 4900static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4901{
70252a10
AK		 4902 int handled = 0;
4903 int n;
4904
4905 do {
4906 n = min(len, 8);
bce87cce 4907 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4908 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4909 addr, n, v))
4910 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 4911 break;
e39d200f 4912 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 4913 handled += n;
4914 addr += n;
4915 len -= n;
4916 v += n;
4917 } while (len);
bbd9b64e 4918
70252a10 4919 return handled;
bbd9b64e
CO		 4920}
4921
2dafc6c2
GN		 4922static void kvm_set_segment(struct kvm_vcpu *vcpu,
4923 struct kvm_segment *var, int seg)
4924{
4925 kvm_x86_ops->set_segment(vcpu, var, seg);
4926}
4927
4928void kvm_get_segment(struct kvm_vcpu *vcpu,
4929 struct kvm_segment *var, int seg)
4930{
4931 kvm_x86_ops->get_segment(vcpu, var, seg);
4932}
4933
54987b7a
PB		 4934gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4935 struct x86_exception *exception)
02f59dc9
JR		 4936{
4937 gpa_t t_gpa;
02f59dc9
JR		 4938
4939 BUG_ON(!mmu_is_nested(vcpu));
4940
4941 /* NPT walks are always user-walks */
4942 access |= PFERR_USER_MASK;
44dd3ffa 4943 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4944
4945 return t_gpa;
4946}
4947
ab9ae313
AK		 4948gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4949 struct x86_exception *exception)
1871c602
GN		 4950{
4951 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4952 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4953}
4954
ab9ae313
AK		 4955 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4956 struct x86_exception *exception)
1871c602
GN		 4957{
4958 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4959 access |= PFERR_FETCH_MASK;
ab9ae313 4960 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4961}
4962
ab9ae313
AK		 4963gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4964 struct x86_exception *exception)
1871c602
GN		 4965{
4966 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4967 access |= PFERR_WRITE_MASK;
ab9ae313 4968 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4969}
4970
4971/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4972gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4973 struct x86_exception *exception)
1871c602 4974{
ab9ae313 4975 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4976}
4977
4978static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4979 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4980 struct x86_exception *exception)
bbd9b64e
CO		 4981{
4982 void *data = val;
10589a46 4983 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4984
4985 while (bytes) {
14dfe855 4986 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4987 exception);
bbd9b64e 4988 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4989 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4990 int ret;
4991
bcc55cba 4992 if (gpa == UNMAPPED_GVA)
ab9ae313 4993 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4994 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4995 offset, toread);
10589a46 4996 if (ret < 0) {
c3cd7ffa 4997 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4998 goto out;
4999 }
bbd9b64e 5000
77c2002e
IE		 5001 bytes -= toread;
5002 data += toread;
5003 addr += toread;
bbd9b64e 5004 }
10589a46 5005out:
10589a46 5006 return r;
bbd9b64e 5007}
77c2002e 5008
1871c602 5009/* used for instruction fetching */
0f65dd70
AK		 5010static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5011 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5012 struct x86_exception *exception)
1871c602 5013{
0f65dd70 5014 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 5015 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 5016 unsigned offset;
5017 int ret;
0f65dd70 5018
44583cba
PB		 5019 /* Inline kvm_read_guest_virt_helper for speed. */
5020 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5021 exception);
5022 if (unlikely(gpa == UNMAPPED_GVA))
5023 return X86EMUL_PROPAGATE_FAULT;
5024
5025 offset = addr & (PAGE_SIZE-1);
5026 if (WARN_ON(offset + bytes > PAGE_SIZE))
5027 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 5028 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5029 offset, bytes);
44583cba
PB		 5030 if (unlikely(ret < 0))
5031 return X86EMUL_IO_NEEDED;
5032
5033 return X86EMUL_CONTINUE;
1871c602
GN		 5034}
5035
ce14e868 5036int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
0f65dd70 5037 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5038 struct x86_exception *exception)
1871c602
GN		 5039{
5040 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 5041
1871c602 5042 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 5043 exception);
1871c602 5044}
064aea77 5045EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 5046
ce14e868
PB		 5047static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5048 gva_t addr, void *val, unsigned int bytes,
3c9fa24c 5049 struct x86_exception *exception, bool system)
1871c602 5050{
0f65dd70 5051 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5052 u32 access = 0;
5053
5054 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5055 access |= PFERR_USER_MASK;
5056
5057 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
1871c602
GN		 5058}
5059
7a036a6f
RK		 5060static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5061 unsigned long addr, void *val, unsigned int bytes)
5062{
5063 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5064 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5065
5066 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5067}
5068
ce14e868
PB		 5069static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5070 struct kvm_vcpu *vcpu, u32 access,
5071 struct x86_exception *exception)
77c2002e
IE		 5072{
5073 void *data = val;
5074 int r = X86EMUL_CONTINUE;
5075
5076 while (bytes) {
14dfe855 5077 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
ce14e868 5078 access,
ab9ae313 5079 exception);
77c2002e
IE		 5080 unsigned offset = addr & (PAGE_SIZE-1);
5081 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5082 int ret;
5083
bcc55cba 5084 if (gpa == UNMAPPED_GVA)
ab9ae313 5085 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 5086 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 5087 if (ret < 0) {
c3cd7ffa 5088 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 5089 goto out;
5090 }
5091
5092 bytes -= towrite;
5093 data += towrite;
5094 addr += towrite;
5095 }
5096out:
5097 return r;
5098}
ce14e868
PB		 5099
5100static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
3c9fa24c
PB		 5101 unsigned int bytes, struct x86_exception *exception,
5102 bool system)
ce14e868
PB		 5103{
5104 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5105 u32 access = PFERR_WRITE_MASK;
5106
5107 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5108 access |= PFERR_USER_MASK;
ce14e868
PB		 5109
5110 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
3c9fa24c 5111 access, exception);
ce14e868
PB		 5112}
5113
5114int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5115 unsigned int bytes, struct x86_exception *exception)
5116{
c595ceee
PB		 5117 /* kvm_write_guest_virt_system can pull in tons of pages. */
5118 vcpu->arch.l1tf_flush_l1d = true;
5119
ce14e868
PB		 5120 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5121 PFERR_WRITE_MASK, exception);
5122}
6a4d7550 5123EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 5124
082d06ed
WL		 5125int handle_ud(struct kvm_vcpu *vcpu)
5126{
6c86eedc 5127 int emul_type = EMULTYPE_TRAP_UD;
082d06ed 5128 enum emulation_result er;
6c86eedc
WL		 5129 char sig[5]; /* ud2; .ascii "kvm" */
5130 struct x86_exception e;
5131
5132 if (force_emulation_prefix &&
3c9fa24c
PB		 5133 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5134 sig, sizeof(sig), &e) == 0 &&
6c86eedc
WL		 5135 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5136 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5137 emul_type = 0;
5138 }
082d06ed 5139
0ce97a2b 5140 er = kvm_emulate_instruction(vcpu, emul_type);
082d06ed
WL		 5141 if (er == EMULATE_USER_EXIT)
5142 return 0;
5143 if (er != EMULATE_DONE)
5144 kvm_queue_exception(vcpu, UD_VECTOR);
5145 return 1;
5146}
5147EXPORT_SYMBOL_GPL(handle_ud);
5148
0f89b207
TL		 5149static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5150 gpa_t gpa, bool write)
5151{
5152 /* For APIC access vmexit */
5153 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5154 return 1;
5155
5156 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5157 trace_vcpu_match_mmio(gva, gpa, write, true);
5158 return 1;
5159 }
5160
5161 return 0;
5162}
5163
af7cc7d1
XG		 5164static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5165 gpa_t *gpa, struct x86_exception *exception,
5166 bool write)
5167{
97d64b78
AK		 5168 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5169 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 5170
be94f6b7
HH		 5171 /*
5172 * currently PKRU is only applied to ept enabled guest so
5173 * there is no pkey in EPT page table for L1 guest or EPT
5174 * shadow page table for L2 guest.
5175 */
97d64b78 5176 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 5177 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 5178 vcpu->arch.access, 0, access)) {
bebb106a
XG		 5179 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5180 (gva & (PAGE_SIZE - 1));
4f022648 5181 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 5182 return 1;
5183 }
5184
af7cc7d1
XG		 5185 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5186
5187 if (*gpa == UNMAPPED_GVA)
5188 return -1;
5189
0f89b207 5190 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 5191}
5192
3200f405 5193int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 5194 const void *val, int bytes)
bbd9b64e
CO		 5195{
5196 int ret;
5197
54bf36aa 5198 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 5199 if (ret < 0)
bbd9b64e 5200 return 0;
0eb05bf2 5201 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 5202 return 1;
5203}
5204
77d197b2
XG		 5205struct read_write_emulator_ops {
5206 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5207 int bytes);
5208 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5209 void *val, int bytes);
5210 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5211 int bytes, void *val);
5212 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5213 void *val, int bytes);
5214 bool write;
5215};
5216
5217static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5218{
5219 if (vcpu->mmio_read_completed) {
77d197b2 5220 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 5221 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 5222 vcpu->mmio_read_completed = 0;
5223 return 1;
5224 }
5225
5226 return 0;
5227}
5228
5229static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5230 void *val, int bytes)
5231{
54bf36aa 5232 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 5233}
5234
5235static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5236 void *val, int bytes)
5237{
5238 return emulator_write_phys(vcpu, gpa, val, bytes);
5239}
5240
5241static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5242{
e39d200f 5243 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 5244 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5245}
5246
5247static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5248 void *val, int bytes)
5249{
e39d200f 5250 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 5251 return X86EMUL_IO_NEEDED;
5252}
5253
5254static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5255 void *val, int bytes)
5256{
f78146b0
AK		 5257 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5258
87da7e66 5259 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 5260 return X86EMUL_CONTINUE;
5261}
5262
0fbe9b0b 5263static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 5264 .read_write_prepare = read_prepare,
5265 .read_write_emulate = read_emulate,
5266 .read_write_mmio = vcpu_mmio_read,
5267 .read_write_exit_mmio = read_exit_mmio,
5268};
5269
0fbe9b0b 5270static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 5271 .read_write_emulate = write_emulate,
5272 .read_write_mmio = write_mmio,
5273 .read_write_exit_mmio = write_exit_mmio,
5274 .write = true,
5275};
5276
22388a3c
XG		 5277static int emulator_read_write_onepage(unsigned long addr, void *val,
5278 unsigned int bytes,
5279 struct x86_exception *exception,
5280 struct kvm_vcpu *vcpu,
0fbe9b0b 5281 const struct read_write_emulator_ops *ops)
bbd9b64e 5282{
af7cc7d1
XG		 5283 gpa_t gpa;
5284 int handled, ret;
22388a3c 5285 bool write = ops->write;
f78146b0 5286 struct kvm_mmio_fragment *frag;
0f89b207
TL		 5287 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5288
5289 /*
5290 * If the exit was due to a NPF we may already have a GPA.
5291 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5292 * Note, this cannot be used on string operations since string
5293 * operation using rep will only have the initial GPA from the NPF
5294 * occurred.
5295 */
5296 if (vcpu->arch.gpa_available &&
5297 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 5298 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5299 gpa = vcpu->arch.gpa_val;
5300 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5301 } else {
5302 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5303 if (ret < 0)
5304 return X86EMUL_PROPAGATE_FAULT;
0f89b207 5305 }
10589a46 5306
618232e2 5307 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 5308 return X86EMUL_CONTINUE;
5309
bbd9b64e
CO		 5310 /*
5311 * Is this MMIO handled locally?
5312 */
22388a3c 5313 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 5314 if (handled == bytes)
bbd9b64e 5315 return X86EMUL_CONTINUE;
bbd9b64e 5316
70252a10
AK		 5317 gpa += handled;
5318 bytes -= handled;
5319 val += handled;
5320
87da7e66
XG		 5321 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5322 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5323 frag->gpa = gpa;
5324 frag->data = val;
5325 frag->len = bytes;
f78146b0 5326 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5327}
5328
52eb5a6d
XL		 5329static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5330 unsigned long addr,
22388a3c
XG		 5331 void *val, unsigned int bytes,
5332 struct x86_exception *exception,
0fbe9b0b 5333 const struct read_write_emulator_ops *ops)
bbd9b64e 5334{
0f65dd70 5335 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5336 gpa_t gpa;
5337 int rc;
5338
5339 if (ops->read_write_prepare &&
5340 ops->read_write_prepare(vcpu, val, bytes))
5341 return X86EMUL_CONTINUE;
5342
5343 vcpu->mmio_nr_fragments = 0;
0f65dd70 5344
bbd9b64e
CO		 5345 /* Crossing a page boundary? */
5346 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5347 int now;
bbd9b64e
CO		 5348
5349 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5350 rc = emulator_read_write_onepage(addr, val, now, exception,
5351 vcpu, ops);
5352
bbd9b64e
CO		 5353 if (rc != X86EMUL_CONTINUE)
5354 return rc;
5355 addr += now;
bac15531
NA		 5356 if (ctxt->mode != X86EMUL_MODE_PROT64)
5357 addr = (u32)addr;
bbd9b64e
CO		 5358 val += now;
5359 bytes -= now;
5360 }
22388a3c 5361
f78146b0
AK		 5362 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5363 vcpu, ops);
5364 if (rc != X86EMUL_CONTINUE)
5365 return rc;
5366
5367 if (!vcpu->mmio_nr_fragments)
5368 return rc;
5369
5370 gpa = vcpu->mmio_fragments[0].gpa;
5371
5372 vcpu->mmio_needed = 1;
5373 vcpu->mmio_cur_fragment = 0;
5374
87da7e66 5375 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5376 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5377 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5378 vcpu->run->mmio.phys_addr = gpa;
5379
5380 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5381}
5382
5383static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5384 unsigned long addr,
5385 void *val,
5386 unsigned int bytes,
5387 struct x86_exception *exception)
5388{
5389 return emulator_read_write(ctxt, addr, val, bytes,
5390 exception, &read_emultor);
5391}
5392
52eb5a6d 5393static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5394 unsigned long addr,
5395 const void *val,
5396 unsigned int bytes,
5397 struct x86_exception *exception)
5398{
5399 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5400 exception, &write_emultor);
bbd9b64e 5401}
bbd9b64e 5402
daea3e73
AK		 5403#define CMPXCHG_TYPE(t, ptr, old, new) \
5404 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5405
5406#ifdef CONFIG_X86_64
5407# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5408#else
5409# define CMPXCHG64(ptr, old, new) \
9749a6c0 5410 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5411#endif
5412
0f65dd70
AK		 5413static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5414 unsigned long addr,
bbd9b64e
CO		 5415 const void *old,
5416 const void *new,
5417 unsigned int bytes,
0f65dd70 5418 struct x86_exception *exception)
bbd9b64e 5419{
0f65dd70 5420 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 5421 gpa_t gpa;
5422 struct page *page;
5423 char *kaddr;
5424 bool exchanged;
2bacc55c 5425
daea3e73
AK		 5426 /* guests cmpxchg8b have to be emulated atomically */
5427 if (bytes > 8 || (bytes & (bytes - 1)))
5428 goto emul_write;
10589a46 5429
daea3e73 5430 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5431
daea3e73
AK		 5432 if (gpa == UNMAPPED_GVA ||
5433 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5434 goto emul_write;
2bacc55c 5435
daea3e73
AK		 5436 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5437 goto emul_write;
72dc67a6 5438
54bf36aa 5439 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 5440 if (is_error_page(page))
c19b8bd6 5441 goto emul_write;
72dc67a6 5442
8fd75e12 5443 kaddr = kmap_atomic(page);
daea3e73
AK		 5444 kaddr += offset_in_page(gpa);
5445 switch (bytes) {
5446 case 1:
5447 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5448 break;
5449 case 2:
5450 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5451 break;
5452 case 4:
5453 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5454 break;
5455 case 8:
5456 exchanged = CMPXCHG64(kaddr, old, new);
5457 break;
5458 default:
5459 BUG();
2bacc55c 5460 }
8fd75e12 5461 kunmap_atomic(kaddr);
daea3e73
AK		 5462 kvm_release_page_dirty(page);
5463
5464 if (!exchanged)
5465 return X86EMUL_CMPXCHG_FAILED;
5466
54bf36aa 5467 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 5468 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5469
5470 return X86EMUL_CONTINUE;
4a5f48f6 5471
3200f405 5472emul_write:
daea3e73 5473 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5474
0f65dd70 5475 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5476}
5477
cf8f70bf
GN		 5478static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5479{
cbfc6c91 5480 int r = 0, i;
cf8f70bf 5481
cbfc6c91
WL		 5482 for (i = 0; i < vcpu->arch.pio.count; i++) {
5483 if (vcpu->arch.pio.in)
5484 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5485 vcpu->arch.pio.size, pd);
5486 else
5487 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5488 vcpu->arch.pio.port, vcpu->arch.pio.size,
5489 pd);
5490 if (r)
5491 break;
5492 pd += vcpu->arch.pio.size;
5493 }
cf8f70bf
GN		 5494 return r;
5495}
5496
6f6fbe98
XG		 5497static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5498 unsigned short port, void *val,
5499 unsigned int count, bool in)
cf8f70bf 5500{
cf8f70bf 5501 vcpu->arch.pio.port = port;
6f6fbe98 5502 vcpu->arch.pio.in = in;
7972995b 5503 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5504 vcpu->arch.pio.size = size;
5505
5506 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5507 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5508 return 1;
5509 }
5510
5511 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5512 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5513 vcpu->run->io.size = size;
5514 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5515 vcpu->run->io.count = count;
5516 vcpu->run->io.port = port;
5517
5518 return 0;
5519}
5520
6f6fbe98
XG		 5521static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5522 int size, unsigned short port, void *val,
5523 unsigned int count)
cf8f70bf 5524{
ca1d4a9e 5525 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5526 int ret;
ca1d4a9e 5527
6f6fbe98
XG		 5528 if (vcpu->arch.pio.count)
5529 goto data_avail;
cf8f70bf 5530
cbfc6c91
WL		 5531 memset(vcpu->arch.pio_data, 0, size * count);
5532
6f6fbe98
XG		 5533 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5534 if (ret) {
5535data_avail:
5536 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5537 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5538 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5539 return 1;
5540 }
5541
cf8f70bf
GN		 5542 return 0;
5543}
5544
6f6fbe98
XG		 5545static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5546 int size, unsigned short port,
5547 const void *val, unsigned int count)
5548{
5549 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5550
5551 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5552 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5553 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5554}
5555
bbd9b64e
CO		 5556static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5557{
5558 return kvm_x86_ops->get_segment_base(vcpu, seg);
5559}
5560
3cb16fe7 5561static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5562{
3cb16fe7 5563 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5564}
5565
ae6a2375 5566static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5567{
5568 if (!need_emulate_wbinvd(vcpu))
5569 return X86EMUL_CONTINUE;
5570
5571 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5572 int cpu = get_cpu();
5573
5574 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5575 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5576 wbinvd_ipi, NULL, 1);
2eec7343 5577 put_cpu();
f5f48ee1 5578 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5579 } else
5580 wbinvd();
f5f48ee1
SY		 5581 return X86EMUL_CONTINUE;
5582}
5cb56059
JS		 5583
5584int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5585{
6affcbed
KH		 5586 kvm_emulate_wbinvd_noskip(vcpu);
5587 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5588}
f5f48ee1
SY		 5589EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5590
5cb56059
JS		 5591
5592
bcaf5cc5
AK		 5593static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5594{
5cb56059 5595 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5596}
5597
52eb5a6d
XL		 5598static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5599 unsigned long *dest)
bbd9b64e 5600{
16f8a6f9 5601 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5602}
5603
52eb5a6d
XL		 5604static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5605 unsigned long value)
bbd9b64e 5606{
338dbc97 5607
717746e3 5608 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5609}
5610
52a46617 5611static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5612{
52a46617 5613 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5614}
5615
717746e3 5616static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5617{
717746e3 5618 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5619 unsigned long value;
5620
5621 switch (cr) {
5622 case 0:
5623 value = kvm_read_cr0(vcpu);
5624 break;
5625 case 2:
5626 value = vcpu->arch.cr2;
5627 break;
5628 case 3:
9f8fe504 5629 value = kvm_read_cr3(vcpu);
52a46617
GN		 5630 break;
5631 case 4:
5632 value = kvm_read_cr4(vcpu);
5633 break;
5634 case 8:
5635 value = kvm_get_cr8(vcpu);
5636 break;
5637 default:
a737f256 5638 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5639 return 0;
5640 }
5641
5642 return value;
5643}
5644
717746e3 5645static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5646{
717746e3 5647 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5648 int res = 0;
5649
52a46617
GN		 5650 switch (cr) {
5651 case 0:
49a9b07e 5652 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5653 break;
5654 case 2:
5655 vcpu->arch.cr2 = val;
5656 break;
5657 case 3:
2390218b 5658 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5659 break;
5660 case 4:
a83b29c6 5661 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5662 break;
5663 case 8:
eea1cff9 5664 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5665 break;
5666 default:
a737f256 5667 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5668 res = -1;
52a46617 5669 }
0f12244f
GN		 5670
5671 return res;
52a46617
GN		 5672}
5673
717746e3 5674static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5675{
717746e3 5676 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5677}
5678
4bff1e86 5679static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5680{
4bff1e86 5681 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5682}
5683
4bff1e86 5684static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5685{
4bff1e86 5686 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5687}
5688
1ac9d0cf
AK		 5689static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5690{
5691 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5692}
5693
5694static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5695{
5696 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5697}
5698
4bff1e86
AK		 5699static unsigned long emulator_get_cached_segment_base(
5700 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5701{
4bff1e86 5702 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5703}
5704
1aa36616
AK		 5705static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5706 struct desc_struct *desc, u32 *base3,
5707 int seg)
2dafc6c2
GN		 5708{
5709 struct kvm_segment var;
5710
4bff1e86 5711 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5712 *selector = var.selector;
2dafc6c2 5713
378a8b09
GN		 5714 if (var.unusable) {
5715 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5716 if (base3)
5717 *base3 = 0;
2dafc6c2 5718 return false;
378a8b09 5719 }
2dafc6c2
GN		 5720
5721 if (var.g)
5722 var.limit >>= 12;
5723 set_desc_limit(desc, var.limit);
5724 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5725#ifdef CONFIG_X86_64
5726 if (base3)
5727 *base3 = var.base >> 32;
5728#endif
2dafc6c2
GN		 5729 desc->type = var.type;
5730 desc->s = var.s;
5731 desc->dpl = var.dpl;
5732 desc->p = var.present;
5733 desc->avl = var.avl;
5734 desc->l = var.l;
5735 desc->d = var.db;
5736 desc->g = var.g;
5737
5738 return true;
5739}
5740
1aa36616
AK		 5741static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5742 struct desc_struct *desc, u32 base3,
5743 int seg)
2dafc6c2 5744{
4bff1e86 5745 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5746 struct kvm_segment var;
5747
1aa36616 5748 var.selector = selector;
2dafc6c2 5749 var.base = get_desc_base(desc);
5601d05b
GN		 5750#ifdef CONFIG_X86_64
5751 var.base |= ((u64)base3) << 32;
5752#endif
2dafc6c2
GN		 5753 var.limit = get_desc_limit(desc);
5754 if (desc->g)
5755 var.limit = (var.limit << 12) | 0xfff;
5756 var.type = desc->type;
2dafc6c2
GN		 5757 var.dpl = desc->dpl;
5758 var.db = desc->d;
5759 var.s = desc->s;
5760 var.l = desc->l;
5761 var.g = desc->g;
5762 var.avl = desc->avl;
5763 var.present = desc->p;
5764 var.unusable = !var.present;
5765 var.padding = 0;
5766
5767 kvm_set_segment(vcpu, &var, seg);
5768 return;
5769}
5770
717746e3
AK		 5771static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5772 u32 msr_index, u64 *pdata)
5773{
609e36d3
PB		 5774 struct msr_data msr;
5775 int r;
5776
5777 msr.index = msr_index;
5778 msr.host_initiated = false;
5779 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5780 if (r)
5781 return r;
5782
5783 *pdata = msr.data;
5784 return 0;
717746e3
AK		 5785}
5786
5787static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5788 u32 msr_index, u64 data)
5789{
8fe8ab46
WA		 5790 struct msr_data msr;
5791
5792 msr.data = data;
5793 msr.index = msr_index;
5794 msr.host_initiated = false;
5795 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5796}
5797
64d60670
PB		 5798static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5799{
5800 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5801
5802 return vcpu->arch.smbase;
5803}
5804
5805static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5806{
5807 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5808
5809 vcpu->arch.smbase = smbase;
5810}
5811
67f4d428
NA		 5812static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5813 u32 pmc)
5814{
c6702c9d 5815 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5816}
5817
222d21aa
AK		 5818static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5819 u32 pmc, u64 *pdata)
5820{
c6702c9d 5821 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5822}
5823
6c3287f7
AK		 5824static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5825{
5826 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5827}
5828
2953538e 5829static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5830 struct x86_instruction_info *info,
c4f035c6
AK		 5831 enum x86_intercept_stage stage)
5832{
2953538e 5833 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5834}
5835
e911eb3b
YZ		 5836static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5837 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5838{
e911eb3b 5839 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5840}
5841
dd856efa
AK		 5842static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5843{
5844 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5845}
5846
5847static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5848{
5849 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5850}
5851
801806d9
NA		 5852static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5853{
5854 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5855}
5856
6ed071f0
LP		 5857static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5858{
5859 return emul_to_vcpu(ctxt)->arch.hflags;
5860}
5861
5862static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5863{
5864 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5865}
5866
0234bf88
LP		 5867static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5868{
5869 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5870}
5871
0225fb50 5872static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5873 .read_gpr = emulator_read_gpr,
5874 .write_gpr = emulator_write_gpr,
ce14e868
PB		 5875 .read_std = emulator_read_std,
5876 .write_std = emulator_write_std,
7a036a6f 5877 .read_phys = kvm_read_guest_phys_system,
1871c602 5878 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5879 .read_emulated = emulator_read_emulated,
5880 .write_emulated = emulator_write_emulated,
5881 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5882 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5883 .pio_in_emulated = emulator_pio_in_emulated,
5884 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5885 .get_segment = emulator_get_segment,
5886 .set_segment = emulator_set_segment,
5951c442 5887 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5888 .get_gdt = emulator_get_gdt,
160ce1f1 5889 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5890 .set_gdt = emulator_set_gdt,
5891 .set_idt = emulator_set_idt,
52a46617
GN		 5892 .get_cr = emulator_get_cr,
5893 .set_cr = emulator_set_cr,
9c537244 5894 .cpl = emulator_get_cpl,
35aa5375
GN		 5895 .get_dr = emulator_get_dr,
5896 .set_dr = emulator_set_dr,
64d60670
PB		 5897 .get_smbase = emulator_get_smbase,
5898 .set_smbase = emulator_set_smbase,
717746e3
AK		 5899 .set_msr = emulator_set_msr,
5900 .get_msr = emulator_get_msr,
67f4d428 5901 .check_pmc = emulator_check_pmc,
222d21aa 5902 .read_pmc = emulator_read_pmc,
6c3287f7 5903 .halt = emulator_halt,
bcaf5cc5 5904 .wbinvd = emulator_wbinvd,
d6aa1000 5905 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5906 .intercept = emulator_intercept,
bdb42f5a 5907 .get_cpuid = emulator_get_cpuid,
801806d9 5908 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5909 .get_hflags = emulator_get_hflags,
5910 .set_hflags = emulator_set_hflags,
0234bf88 5911 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5912};
5913
95cb2295
GN		 5914static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5915{
37ccdcbe 5916 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5917 /*
5918 * an sti; sti; sequence only disable interrupts for the first
5919 * instruction. So, if the last instruction, be it emulated or
5920 * not, left the system with the INT_STI flag enabled, it
5921 * means that the last instruction is an sti. We should not
5922 * leave the flag on in this case. The same goes for mov ss
5923 */
37ccdcbe
PB		 5924 if (int_shadow & mask)
5925 mask = 0;
6addfc42 5926 if (unlikely(int_shadow || mask)) {
95cb2295 5927 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5928 if (!mask)
5929 kvm_make_request(KVM_REQ_EVENT, vcpu);
5930 }
95cb2295
GN		 5931}
5932
ef54bcfe 5933static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5934{
5935 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5936 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5937 return kvm_propagate_fault(vcpu, &ctxt->exception);
5938
5939 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5940 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5941 ctxt->exception.error_code);
54b8486f 5942 else
da9cb575 5943 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5944 return false;
54b8486f
GN		 5945}
5946
8ec4722d
MG		 5947static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5948{
adf52235 5949 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5950 int cs_db, cs_l;
5951
8ec4722d
MG		 5952 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5953
adf52235 5954 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5955 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5956
adf52235
TY		 5957 ctxt->eip = kvm_rip_read(vcpu);
5958 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5959 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5960 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5961 cs_db ? X86EMUL_MODE_PROT32 :
5962 X86EMUL_MODE_PROT16;
a584539b 5963 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5964 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5965 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5966
dd856efa 5967 init_decode_cache(ctxt);
7ae441ea 5968 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5969}
5970
71f9833b 5971int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5972{
9d74191a 5973 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5974 int ret;
5975
5976 init_emulate_ctxt(vcpu);
5977
9dac77fa
AK		 5978 ctxt->op_bytes = 2;
5979 ctxt->ad_bytes = 2;
5980 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5981 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5982
5983 if (ret != X86EMUL_CONTINUE)
5984 return EMULATE_FAIL;
5985
9dac77fa 5986 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5987 kvm_rip_write(vcpu, ctxt->eip);
5988 kvm_set_rflags(vcpu, ctxt->eflags);
63995653 5989
63995653
MG		 5990 return EMULATE_DONE;
5991}
5992EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5993
e2366171 5994static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 5995{
fc3a9157
JR		 5996 int r = EMULATE_DONE;
5997
6d77dbfc
GN		 5998 ++vcpu->stat.insn_emulation_fail;
5999 trace_kvm_emulate_insn_failed(vcpu);
e2366171
LA		 6000
6001 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
6002 return EMULATE_FAIL;
6003
a2b9e6c1 6004 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 6005 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6006 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6007 vcpu->run->internal.ndata = 0;
1f4dcb3b 6008 r = EMULATE_USER_EXIT;
fc3a9157 6009 }
e2366171 6010
6d77dbfc 6011 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 6012
6013 return r;
6d77dbfc
GN		 6014}
6015
93c05d3e 6016static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 6017 bool write_fault_to_shadow_pgtable,
6018 int emulation_type)
a6f177ef 6019{
95b3cf69 6020 gpa_t gpa = cr2;
ba049e93 6021 kvm_pfn_t pfn;
a6f177ef 6022
384bf221 6023 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
991eebf9
GN		 6024 return false;
6025
6c3dfeb6
SC		 6026 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6027 return false;
6028
44dd3ffa 6029 if (!vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6030 /*
6031 * Write permission should be allowed since only
6032 * write access need to be emulated.
6033 */
6034 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 6035
95b3cf69
XG		 6036 /*
6037 * If the mapping is invalid in guest, let cpu retry
6038 * it to generate fault.
6039 */
6040 if (gpa == UNMAPPED_GVA)
6041 return true;
6042 }
a6f177ef 6043
8e3d9d06
XG		 6044 /*
6045 * Do not retry the unhandleable instruction if it faults on the
6046 * readonly host memory, otherwise it will goto a infinite loop:
6047 * retry instruction -> write #PF -> emulation fail -> retry
6048 * instruction -> ...
6049 */
6050 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 6051
6052 /*
6053 * If the instruction failed on the error pfn, it can not be fixed,
6054 * report the error to userspace.
6055 */
6056 if (is_error_noslot_pfn(pfn))
6057 return false;
6058
6059 kvm_release_pfn_clean(pfn);
6060
6061 /* The instructions are well-emulated on direct mmu. */
44dd3ffa 6062 if (vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6063 unsigned int indirect_shadow_pages;
6064
6065 spin_lock(&vcpu->kvm->mmu_lock);
6066 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6067 spin_unlock(&vcpu->kvm->mmu_lock);
6068
6069 if (indirect_shadow_pages)
6070 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6071
a6f177ef 6072 return true;
8e3d9d06 6073 }
a6f177ef 6074
95b3cf69
XG		 6075 /*
6076 * if emulation was due to access to shadowed page table
6077 * and it failed try to unshadow page and re-enter the
6078 * guest to let CPU execute the instruction.
6079 */
6080 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 6081
6082 /*
6083 * If the access faults on its page table, it can not
6084 * be fixed by unprotecting shadow page and it should
6085 * be reported to userspace.
6086 */
6087 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 6088}
6089
1cb3f3ae
XG		 6090static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6091 unsigned long cr2, int emulation_type)
6092{
6093 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6094 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
6095
6096 last_retry_eip = vcpu->arch.last_retry_eip;
6097 last_retry_addr = vcpu->arch.last_retry_addr;
6098
6099 /*
6100 * If the emulation is caused by #PF and it is non-page_table
6101 * writing instruction, it means the VM-EXIT is caused by shadow
6102 * page protected, we can zap the shadow page and retry this
6103 * instruction directly.
6104 *
6105 * Note: if the guest uses a non-page-table modifying instruction
6106 * on the PDE that points to the instruction, then we will unmap
6107 * the instruction and go to an infinite loop. So, we cache the
6108 * last retried eip and the last fault address, if we meet the eip
6109 * and the address again, we can break out of the potential infinite
6110 * loop.
6111 */
6112 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6113
384bf221 6114 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
1cb3f3ae
XG		 6115 return false;
6116
6c3dfeb6
SC		 6117 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6118 return false;
6119
1cb3f3ae
XG		 6120 if (x86_page_table_writing_insn(ctxt))
6121 return false;
6122
6123 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
6124 return false;
6125
6126 vcpu->arch.last_retry_eip = ctxt->eip;
6127 vcpu->arch.last_retry_addr = cr2;
6128
44dd3ffa 6129 if (!vcpu->arch.mmu->direct_map)
1cb3f3ae
XG		 6130 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6131
22368028 6132 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 6133
6134 return true;
6135}
6136
716d51ab
GN		 6137static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6138static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6139
64d60670 6140static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 6141{
64d60670 6142 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 6143 /* This is a good place to trace that we are exiting SMM. */
6144 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6145
c43203ca
PB		 6146 /* Process a latched INIT or SMI, if any. */
6147 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 6148 }
699023e2
PB		 6149
6150 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6151}
6152
6153static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
6154{
6155 unsigned changed = vcpu->arch.hflags ^ emul_flags;
6156
a584539b 6157 vcpu->arch.hflags = emul_flags;
64d60670
PB		 6158
6159 if (changed & HF_SMM_MASK)
6160 kvm_smm_changed(vcpu);
a584539b
PB		 6161}
6162
4a1e10d5
PB		 6163static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6164 unsigned long *db)
6165{
6166 u32 dr6 = 0;
6167 int i;
6168 u32 enable, rwlen;
6169
6170 enable = dr7;
6171 rwlen = dr7 >> 16;
6172 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6173 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6174 dr6 |= (1 << i);
6175 return dr6;
6176}
6177
c8401dda 6178static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 6179{
6180 struct kvm_run *kvm_run = vcpu->run;
6181
c8401dda
PB		 6182 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6183 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6184 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6185 kvm_run->debug.arch.exception = DB_VECTOR;
6186 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6187 *r = EMULATE_USER_EXIT;
6188 } else {
f10c729f 6189 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
663f4c61
PB		 6190 }
6191}
6192
6affcbed
KH		 6193int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6194{
6195 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6196 int r = EMULATE_DONE;
6197
6198 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 6199
6200 /*
6201 * rflags is the old, "raw" value of the flags. The new value has
6202 * not been saved yet.
6203 *
6204 * This is correct even for TF set by the guest, because "the
6205 * processor will not generate this exception after the instruction
6206 * that sets the TF flag".
6207 */
6208 if (unlikely(rflags & X86_EFLAGS_TF))
6209 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 6210 return r == EMULATE_DONE;
6211}
6212EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6213
4a1e10d5
PB		 6214static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6215{
4a1e10d5
PB		 6216 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6217 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 6218 struct kvm_run *kvm_run = vcpu->run;
6219 unsigned long eip = kvm_get_linear_rip(vcpu);
6220 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6221 vcpu->arch.guest_debug_dr7,
6222 vcpu->arch.eff_db);
6223
6224 if (dr6 != 0) {
6f43ed01 6225 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 6226 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 6227 kvm_run->debug.arch.exception = DB_VECTOR;
6228 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6229 *r = EMULATE_USER_EXIT;
6230 return true;
6231 }
6232 }
6233
4161a569
NA		 6234 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6235 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 6236 unsigned long eip = kvm_get_linear_rip(vcpu);
6237 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6238 vcpu->arch.dr7,
6239 vcpu->arch.db);
6240
6241 if (dr6 != 0) {
6242 vcpu->arch.dr6 &= ~15;
6f43ed01 6243 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 6244 kvm_queue_exception(vcpu, DB_VECTOR);
6245 *r = EMULATE_DONE;
6246 return true;
6247 }
6248 }
6249
6250 return false;
6251}
6252
04789b66
LA		 6253static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6254{
2d7921c4
AM		 6255 switch (ctxt->opcode_len) {
6256 case 1:
6257 switch (ctxt->b) {
6258 case 0xe4: /* IN */
6259 case 0xe5:
6260 case 0xec:
6261 case 0xed:
6262 case 0xe6: /* OUT */
6263 case 0xe7:
6264 case 0xee:
6265 case 0xef:
6266 case 0x6c: /* INS */
6267 case 0x6d:
6268 case 0x6e: /* OUTS */
6269 case 0x6f:
6270 return true;
6271 }
6272 break;
6273 case 2:
6274 switch (ctxt->b) {
6275 case 0x33: /* RDPMC */
6276 return true;
6277 }
6278 break;
04789b66
LA		 6279 }
6280
6281 return false;
6282}
6283
51d8b661
AP		 6284int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6285 unsigned long cr2,
dc25e89e
AP		 6286 int emulation_type,
6287 void *insn,
6288 int insn_len)
bbd9b64e 6289{
95cb2295 6290 int r;
9d74191a 6291 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 6292 bool writeback = true;
93c05d3e 6293 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 6294
c595ceee
PB		 6295 vcpu->arch.l1tf_flush_l1d = true;
6296
93c05d3e
XG		 6297 /*
6298 * Clear write_fault_to_shadow_pgtable here to ensure it is
6299 * never reused.
6300 */
6301 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 6302 kvm_clear_exception_queue(vcpu);
8d7d8102 6303
571008da 6304 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 6305 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 6306
6307 /*
6308 * We will reenter on the same instruction since
6309 * we do not set complete_userspace_io. This does not
6310 * handle watchpoints yet, those would be handled in
6311 * the emulate_ops.
6312 */
d391f120
VK		 6313 if (!(emulation_type & EMULTYPE_SKIP) &&
6314 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 6315 return r;
6316
9d74191a
TY		 6317 ctxt->interruptibility = 0;
6318 ctxt->have_exception = false;
e0ad0b47 6319 ctxt->exception.vector = -1;
9d74191a 6320 ctxt->perm_ok = false;
bbd9b64e 6321
b51e974f 6322 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 6323
9d74191a 6324 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 6325
e46479f8 6326 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 6327 ++vcpu->stat.insn_emulation;
1d2887e2 6328 if (r != EMULATION_OK) {
4005996e
AK		 6329 if (emulation_type & EMULTYPE_TRAP_UD)
6330 return EMULATE_FAIL;
991eebf9
GN		 6331 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6332 emulation_type))
bbd9b64e 6333 return EMULATE_DONE;
6ea6e843
PB		 6334 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6335 return EMULATE_DONE;
6d77dbfc
GN		 6336 if (emulation_type & EMULTYPE_SKIP)
6337 return EMULATE_FAIL;
e2366171 6338 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6339 }
6340 }
6341
04789b66
LA		 6342 if ((emulation_type & EMULTYPE_VMWARE) &&
6343 !is_vmware_backdoor_opcode(ctxt))
6344 return EMULATE_FAIL;
6345
ba8afb6b 6346 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6347 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6348 if (ctxt->eflags & X86_EFLAGS_RF)
6349 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 6350 return EMULATE_DONE;
6351 }
6352
1cb3f3ae
XG		 6353 if (retry_instruction(ctxt, cr2, emulation_type))
6354 return EMULATE_DONE;
6355
7ae441ea 6356 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6357 changes registers values during IO operation */
7ae441ea
GN		 6358 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6359 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6360 emulator_invalidate_register_cache(ctxt);
7ae441ea 6361 }
4d2179e1 6362
5cd21917 6363restart:
0f89b207
TL		 6364 /* Save the faulting GPA (cr2) in the address field */
6365 ctxt->exception.address = cr2;
6366
9d74191a 6367 r = x86_emulate_insn(ctxt);
bbd9b64e 6368
775fde86
JR		 6369 if (r == EMULATION_INTERCEPTED)
6370 return EMULATE_DONE;
6371
d2ddd1c4 6372 if (r == EMULATION_FAILED) {
991eebf9
GN		 6373 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6374 emulation_type))
c3cd7ffa
GN		 6375 return EMULATE_DONE;
6376
e2366171 6377 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6378 }
6379
9d74191a 6380 if (ctxt->have_exception) {
d2ddd1c4 6381 r = EMULATE_DONE;
ef54bcfe
PB		 6382 if (inject_emulated_exception(vcpu))
6383 return r;
d2ddd1c4 6384 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6385 if (!vcpu->arch.pio.in) {
6386 /* FIXME: return into emulator if single-stepping. */
3457e419 6387 vcpu->arch.pio.count = 0;
0912c977 6388 } else {
7ae441ea 6389 writeback = false;
716d51ab
GN		 6390 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6391 }
ac0a48c3 6392 r = EMULATE_USER_EXIT;
7ae441ea
GN		 6393 } else if (vcpu->mmio_needed) {
6394 if (!vcpu->mmio_is_write)
6395 writeback = false;
ac0a48c3 6396 r = EMULATE_USER_EXIT;
716d51ab 6397 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6398 } else if (r == EMULATION_RESTART)
5cd21917 6399 goto restart;
d2ddd1c4
GN		 6400 else
6401 r = EMULATE_DONE;
f850e2e6 6402
7ae441ea 6403 if (writeback) {
6addfc42 6404 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6405 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6406 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 6407 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 6408 if (r == EMULATE_DONE &&
6409 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
6410 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 6411 if (!ctxt->have_exception ||
6412 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6413 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 6414
6415 /*
6416 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6417 * do nothing, and it will be requested again as soon as
6418 * the shadow expires. But we still need to check here,
6419 * because POPF has no interrupt shadow.
6420 */
6421 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6422 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6423 } else
6424 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6425
6426 return r;
de7d789a 6427}
c60658d1
SC		 6428
6429int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6430{
6431 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6432}
6433EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6434
6435int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6436 void *insn, int insn_len)
6437{
6438 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6439}
6440EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
de7d789a 6441
dca7f128
SC		 6442static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6443 unsigned short port)
de7d789a 6444{
cf8f70bf 6445 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 6446 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6447 size, port, &val, 1);
cf8f70bf 6448 /* do not return to emulator after return from userspace */
7972995b 6449 vcpu->arch.pio.count = 0;
de7d789a
CO		 6450 return ret;
6451}
de7d789a 6452
8370c3d0
TL		 6453static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6454{
6455 unsigned long val;
6456
6457 /* We should only ever be called with arch.pio.count equal to 1 */
6458 BUG_ON(vcpu->arch.pio.count != 1);
6459
6460 /* For size less than 4 we merge, else we zero extend */
6461 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6462 : 0;
6463
6464 /*
6465 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6466 * the copy and tracing
6467 */
6468 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6469 vcpu->arch.pio.port, &val, 1);
6470 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6471
6472 return 1;
6473}
6474
dca7f128
SC		 6475static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6476 unsigned short port)
8370c3d0
TL		 6477{
6478 unsigned long val;
6479 int ret;
6480
6481 /* For size less than 4 we merge, else we zero extend */
6482 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6483
6484 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6485 &val, 1);
6486 if (ret) {
6487 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6488 return ret;
6489 }
6490
6491 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6492
6493 return 0;
6494}
dca7f128
SC		 6495
6496int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6497{
6498 int ret = kvm_skip_emulated_instruction(vcpu);
6499
6500 /*
6501 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6502 * KVM_EXIT_DEBUG here.
6503 */
6504 if (in)
6505 return kvm_fast_pio_in(vcpu, size, port) && ret;
6506 else
6507 return kvm_fast_pio_out(vcpu, size, port) && ret;
6508}
6509EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 6510
251a5fd6 6511static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6512{
0a3aee0d 6513 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6514 return 0;
8cfdc000
ZA		 6515}
6516
6517static void tsc_khz_changed(void *data)
c8076604 6518{
8cfdc000
ZA		 6519 struct cpufreq_freqs *freq = data;
6520 unsigned long khz = 0;
6521
6522 if (data)
6523 khz = freq->new;
6524 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6525 khz = cpufreq_quick_get(raw_smp_processor_id());
6526 if (!khz)
6527 khz = tsc_khz;
0a3aee0d 6528 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6529}
6530
5fa4ec9c 6531#ifdef CONFIG_X86_64
0092e434
VK		 6532static void kvm_hyperv_tsc_notifier(void)
6533{
0092e434
VK		 6534 struct kvm *kvm;
6535 struct kvm_vcpu *vcpu;
6536 int cpu;
6537
6538 spin_lock(&kvm_lock);
6539 list_for_each_entry(kvm, &vm_list, vm_list)
6540 kvm_make_mclock_inprogress_request(kvm);
6541
6542 hyperv_stop_tsc_emulation();
6543
6544 /* TSC frequency always matches when on Hyper-V */
6545 for_each_present_cpu(cpu)
6546 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6547 kvm_max_guest_tsc_khz = tsc_khz;
6548
6549 list_for_each_entry(kvm, &vm_list, vm_list) {
6550 struct kvm_arch *ka = &kvm->arch;
6551
6552 spin_lock(&ka->pvclock_gtod_sync_lock);
6553
6554 pvclock_update_vm_gtod_copy(kvm);
6555
6556 kvm_for_each_vcpu(cpu, vcpu, kvm)
6557 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6558
6559 kvm_for_each_vcpu(cpu, vcpu, kvm)
6560 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6561
6562 spin_unlock(&ka->pvclock_gtod_sync_lock);
6563 }
6564 spin_unlock(&kvm_lock);
0092e434 6565}
5fa4ec9c 6566#endif
0092e434 6567
c8076604
GH		 6568static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6569 void *data)
6570{
6571 struct cpufreq_freqs *freq = data;
6572 struct kvm *kvm;
6573 struct kvm_vcpu *vcpu;
6574 int i, send_ipi = 0;
6575
8cfdc000
ZA		 6576 /*
6577 * We allow guests to temporarily run on slowing clocks,
6578 * provided we notify them after, or to run on accelerating
6579 * clocks, provided we notify them before. Thus time never
6580 * goes backwards.
6581 *
6582 * However, we have a problem. We can't atomically update
6583 * the frequency of a given CPU from this function; it is
6584 * merely a notifier, which can be called from any CPU.
6585 * Changing the TSC frequency at arbitrary points in time
6586 * requires a recomputation of local variables related to
6587 * the TSC for each VCPU. We must flag these local variables
6588 * to be updated and be sure the update takes place with the
6589 * new frequency before any guests proceed.
6590 *
6591 * Unfortunately, the combination of hotplug CPU and frequency
6592 * change creates an intractable locking scenario; the order
6593 * of when these callouts happen is undefined with respect to
6594 * CPU hotplug, and they can race with each other. As such,
6595 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6596 * undefined; you can actually have a CPU frequency change take
6597 * place in between the computation of X and the setting of the
6598 * variable. To protect against this problem, all updates of
6599 * the per_cpu tsc_khz variable are done in an interrupt
6600 * protected IPI, and all callers wishing to update the value
6601 * must wait for a synchronous IPI to complete (which is trivial
6602 * if the caller is on the CPU already). This establishes the
6603 * necessary total order on variable updates.
6604 *
6605 * Note that because a guest time update may take place
6606 * anytime after the setting of the VCPU's request bit, the
6607 * correct TSC value must be set before the request. However,
6608 * to ensure the update actually makes it to any guest which
6609 * starts running in hardware virtualization between the set
6610 * and the acquisition of the spinlock, we must also ping the
6611 * CPU after setting the request bit.
6612 *
6613 */
6614
c8076604
GH		 6615 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6616 return 0;
6617 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6618 return 0;
8cfdc000
ZA		 6619
6620 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 6621
2f303b74 6622 spin_lock(&kvm_lock);
c8076604 6623 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6624 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 6625 if (vcpu->cpu != freq->cpu)
6626 continue;
c285545f 6627 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 6628 if (vcpu->cpu != smp_processor_id())
8cfdc000 6629 send_ipi = 1;
c8076604
GH		 6630 }
6631 }
2f303b74 6632 spin_unlock(&kvm_lock);
c8076604
GH		 6633
6634 if (freq->old < freq->new && send_ipi) {
6635 /*
6636 * We upscale the frequency. Must make the guest
6637 * doesn't see old kvmclock values while running with
6638 * the new frequency, otherwise we risk the guest sees
6639 * time go backwards.
6640 *
6641 * In case we update the frequency for another cpu
6642 * (which might be in guest context) send an interrupt
6643 * to kick the cpu out of guest context. Next time
6644 * guest context is entered kvmclock will be updated,
6645 * so the guest will not see stale values.
6646 */
8cfdc000 6647 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 6648 }
6649 return 0;
6650}
6651
6652static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6653 .notifier_call = kvmclock_cpufreq_notifier
6654};
6655
251a5fd6 6656static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6657{
251a5fd6
SAS		 6658 tsc_khz_changed(NULL);
6659 return 0;
8cfdc000
ZA		 6660}
6661
b820cc0c
ZA		 6662static void kvm_timer_init(void)
6663{
c285545f 6664 max_tsc_khz = tsc_khz;
460dd42e 6665
b820cc0c 6666 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6667#ifdef CONFIG_CPU_FREQ
6668 struct cpufreq_policy policy;
758f588d
BP		 6669 int cpu;
6670
c285545f 6671 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6672 cpu = get_cpu();
6673 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6674 if (policy.cpuinfo.max_freq)
6675 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6676 put_cpu();
c285545f 6677#endif
b820cc0c
ZA		 6678 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6679 CPUFREQ_TRANSITION_NOTIFIER);
6680 }
c285545f 6681 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6682
73c1b41e 6683 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6684 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6685}
6686
dd60d217
AK		 6687DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6688EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
ff9d07a0 6689
f5132b01 6690int kvm_is_in_guest(void)
ff9d07a0 6691{
086c9855 6692 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6693}
6694
6695static int kvm_is_user_mode(void)
6696{
6697 int user_mode = 3;
dcf46b94 6698
086c9855
AS		 6699 if (__this_cpu_read(current_vcpu))
6700 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6701
ff9d07a0
ZY		 6702 return user_mode != 0;
6703}
6704
6705static unsigned long kvm_get_guest_ip(void)
6706{
6707 unsigned long ip = 0;
dcf46b94 6708
086c9855
AS		 6709 if (__this_cpu_read(current_vcpu))
6710 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6711
ff9d07a0
ZY		 6712 return ip;
6713}
6714
6715static struct perf_guest_info_callbacks kvm_guest_cbs = {
6716 .is_in_guest = kvm_is_in_guest,
6717 .is_user_mode = kvm_is_user_mode,
6718 .get_guest_ip = kvm_get_guest_ip,
6719};
6720
ce88decf
XG		 6721static void kvm_set_mmio_spte_mask(void)
6722{
6723 u64 mask;
6724 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6725
6726 /*
6727 * Set the reserved bits and the present bit of an paging-structure
6728 * entry to generate page fault with PFER.RSV = 1.
6729 */
28a1f3ac
JS		 6730
6731 /*
6732 * Mask the uppermost physical address bit, which would be reserved as
6733 * long as the supported physical address width is less than 52.
6734 */
6735 mask = 1ull << 51;
885032b9 6736
885032b9 6737 /* Set the present bit. */
ce88decf
XG		 6738 mask |= 1ull;
6739
ce88decf
XG		 6740 /*
6741 * If reserved bit is not supported, clear the present bit to disable
6742 * mmio page fault.
6743 */
7288bde1 6744 if (IS_ENABLED(CONFIG_X86_64) && maxphyaddr == 52)
ce88decf 6745 mask &= ~1ull;
ce88decf 6746
dcdca5fe 6747 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6748}
6749
16e8d74d
MT		 6750#ifdef CONFIG_X86_64
6751static void pvclock_gtod_update_fn(struct work_struct *work)
6752{
d828199e
MT		 6753 struct kvm *kvm;
6754
6755 struct kvm_vcpu *vcpu;
6756 int i;
6757
2f303b74 6758 spin_lock(&kvm_lock);
d828199e
MT		 6759 list_for_each_entry(kvm, &vm_list, vm_list)
6760 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6761 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6762 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6763 spin_unlock(&kvm_lock);
16e8d74d
MT		 6764}
6765
6766static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6767
6768/*
6769 * Notification about pvclock gtod data update.
6770 */
6771static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6772 void *priv)
6773{
6774 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6775 struct timekeeper *tk = priv;
6776
6777 update_pvclock_gtod(tk);
6778
6779 /* disable master clock if host does not trust, or does not
b0c39dc6 6780 * use, TSC based clocksource.
16e8d74d 6781 */
b0c39dc6 6782 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6783 atomic_read(&kvm_guest_has_master_clock) != 0)
6784 queue_work(system_long_wq, &pvclock_gtod_work);
6785
6786 return 0;
6787}
6788
6789static struct notifier_block pvclock_gtod_notifier = {
6790 .notifier_call = pvclock_gtod_notify,
6791};
6792#endif
6793
f8c16bba 6794int kvm_arch_init(void *opaque)
043405e1 6795{
b820cc0c 6796 int r;
6b61edf7 6797 struct kvm_x86_ops *ops = opaque;
f8c16bba 6798
f8c16bba
ZX		 6799 if (kvm_x86_ops) {
6800 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6801 r = -EEXIST;
6802 goto out;
f8c16bba
ZX		 6803 }
6804
6805 if (!ops->cpu_has_kvm_support()) {
6806 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6807 r = -EOPNOTSUPP;
6808 goto out;
f8c16bba
ZX		 6809 }
6810 if (ops->disabled_by_bios()) {
6811 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6812 r = -EOPNOTSUPP;
6813 goto out;
f8c16bba
ZX		 6814 }
6815
013f6a5d
MT		 6816 r = -ENOMEM;
6817 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6818 if (!shared_msrs) {
6819 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6820 goto out;
6821 }
6822
97db56ce
AK		 6823 r = kvm_mmu_module_init();
6824 if (r)
013f6a5d 6825 goto out_free_percpu;
97db56ce 6826
ce88decf 6827 kvm_set_mmio_spte_mask();
97db56ce 6828
f8c16bba 6829 kvm_x86_ops = ops;
920c8377 6830
7b52345e 6831 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6832 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6833 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6834 kvm_timer_init();
c8076604 6835
ff9d07a0
ZY		 6836 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6837
d366bf7e 6838 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6839 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6840
c5cc421b 6841 kvm_lapic_init();
16e8d74d
MT		 6842#ifdef CONFIG_X86_64
6843 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 6844
5fa4ec9c 6845 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 6846 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 6847#endif
6848
f8c16bba 6849 return 0;
56c6d28a 6850
013f6a5d
MT		 6851out_free_percpu:
6852 free_percpu(shared_msrs);
56c6d28a 6853out:
56c6d28a 6854 return r;
043405e1 6855}
8776e519 6856
f8c16bba
ZX		 6857void kvm_arch_exit(void)
6858{
0092e434 6859#ifdef CONFIG_X86_64
5fa4ec9c 6860 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 6861 clear_hv_tscchange_cb();
6862#endif
cef84c30 6863 kvm_lapic_exit();
ff9d07a0
ZY		 6864 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6865
888d256e
JK		 6866 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6867 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6868 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6869 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6870#ifdef CONFIG_X86_64
6871 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6872#endif
f8c16bba 6873 kvm_x86_ops = NULL;
56c6d28a 6874 kvm_mmu_module_exit();
013f6a5d 6875 free_percpu(shared_msrs);
56c6d28a 6876}
f8c16bba 6877
5cb56059 6878int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6879{
6880 ++vcpu->stat.halt_exits;
35754c98 6881 if (lapic_in_kernel(vcpu)) {
a4535290 6882 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6883 return 1;
6884 } else {
6885 vcpu->run->exit_reason = KVM_EXIT_HLT;
6886 return 0;
6887 }
6888}
5cb56059
JS		 6889EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6890
6891int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6892{
6affcbed
KH		 6893 int ret = kvm_skip_emulated_instruction(vcpu);
6894 /*
6895 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6896 * KVM_EXIT_DEBUG here.
6897 */
6898 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6899}
8776e519
HB		 6900EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6901
8ef81a9a 6902#ifdef CONFIG_X86_64
55dd00a7
MT		 6903static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6904 unsigned long clock_type)
6905{
6906 struct kvm_clock_pairing clock_pairing;
899a31f5 6907 struct timespec64 ts;
80fbd89c 6908 u64 cycle;
55dd00a7
MT		 6909 int ret;
6910
6911 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6912 return -KVM_EOPNOTSUPP;
6913
6914 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6915 return -KVM_EOPNOTSUPP;
6916
6917 clock_pairing.sec = ts.tv_sec;
6918 clock_pairing.nsec = ts.tv_nsec;
6919 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6920 clock_pairing.flags = 0;
6921
6922 ret = 0;
6923 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6924 sizeof(struct kvm_clock_pairing)))
6925 ret = -KVM_EFAULT;
6926
6927 return ret;
6928}
8ef81a9a 6929#endif
55dd00a7 6930
6aef266c
SV		 6931/*
6932 * kvm_pv_kick_cpu_op: Kick a vcpu.
6933 *
6934 * @apicid - apicid of vcpu to be kicked.
6935 */
6936static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6937{
24d2166b 6938 struct kvm_lapic_irq lapic_irq;
6aef266c 6939
24d2166b
R		 6940 lapic_irq.shorthand = 0;
6941 lapic_irq.dest_mode = 0;
ebd28fcb 6942 lapic_irq.level = 0;
24d2166b 6943 lapic_irq.dest_id = apicid;
93bbf0b8 6944 lapic_irq.msi_redir_hint = false;
6aef266c 6945
24d2166b 6946 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6947 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6948}
6949
d62caabb
AS		 6950void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6951{
6952 vcpu->arch.apicv_active = false;
6953 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6954}
6955
8776e519
HB		 6956int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6957{
6958 unsigned long nr, a0, a1, a2, a3, ret;
6356ee0c 6959 int op_64_bit;
8776e519 6960
696ca779
RK		 6961 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6962 return kvm_hv_hypercall(vcpu);
55cd8e5a 6963
5fdbf976
MT		 6964 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6965 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6966 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6967 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6968 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6969
229456fc 6970 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6971
a449c7aa
NA		 6972 op_64_bit = is_64_bit_mode(vcpu);
6973 if (!op_64_bit) {
8776e519
HB		 6974 nr &= 0xFFFFFFFF;
6975 a0 &= 0xFFFFFFFF;
6976 a1 &= 0xFFFFFFFF;
6977 a2 &= 0xFFFFFFFF;
6978 a3 &= 0xFFFFFFFF;
6979 }
6980
07708c4a
JK		 6981 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6982 ret = -KVM_EPERM;
696ca779 6983 goto out;
07708c4a
JK		 6984 }
6985
8776e519 6986 switch (nr) {
b93463aa
AK		 6987 case KVM_HC_VAPIC_POLL_IRQ:
6988 ret = 0;
6989 break;
6aef266c
SV		 6990 case KVM_HC_KICK_CPU:
6991 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6992 ret = 0;
6993 break;
8ef81a9a 6994#ifdef CONFIG_X86_64
55dd00a7
MT		 6995 case KVM_HC_CLOCK_PAIRING:
6996 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6997 break;
4180bf1b
WL		 6998 case KVM_HC_SEND_IPI:
6999 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7000 break;
8ef81a9a 7001#endif
8776e519
HB		 7002 default:
7003 ret = -KVM_ENOSYS;
7004 break;
7005 }
696ca779 7006out:
a449c7aa
NA		 7007 if (!op_64_bit)
7008 ret = (u32)ret;
5fdbf976 7009 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6356ee0c 7010
f11c3a8d 7011 ++vcpu->stat.hypercalls;
6356ee0c 7012 return kvm_skip_emulated_instruction(vcpu);
8776e519
HB		 7013}
7014EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7015
b6785def 7016static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 7017{
d6aa1000 7018 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 7019 char instruction[3];
5fdbf976 7020 unsigned long rip = kvm_rip_read(vcpu);
8776e519 7021
8776e519 7022 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 7023
ce2e852e
DV		 7024 return emulator_write_emulated(ctxt, rip, instruction, 3,
7025 &ctxt->exception);
8776e519
HB		 7026}
7027
851ba692 7028static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 7029{
782d422b
MG		 7030 return vcpu->run->request_interrupt_window &&
7031 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 7032}
7033
851ba692 7034static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 7035{
851ba692
AK		 7036 struct kvm_run *kvm_run = vcpu->run;
7037
91586a3b 7038 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 7039 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 7040 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 7041 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 7042 kvm_run->ready_for_interrupt_injection =
7043 pic_in_kernel(vcpu->kvm) ||
782d422b 7044 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 7045}
7046
95ba8273
GN		 7047static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7048{
7049 int max_irr, tpr;
7050
7051 if (!kvm_x86_ops->update_cr8_intercept)
7052 return;
7053
bce87cce 7054 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 7055 return;
7056
d62caabb
AS		 7057 if (vcpu->arch.apicv_active)
7058 return;
7059
8db3baa2
GN		 7060 if (!vcpu->arch.apic->vapic_addr)
7061 max_irr = kvm_lapic_find_highest_irr(vcpu);
7062 else
7063 max_irr = -1;
95ba8273
GN		 7064
7065 if (max_irr != -1)
7066 max_irr >>= 4;
7067
7068 tpr = kvm_lapic_get_cr8(vcpu);
7069
7070 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7071}
7072
b6b8a145 7073static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 7074{
b6b8a145
JK		 7075 int r;
7076
95ba8273 7077 /* try to reinject previous events if any */
664f8e26 7078
1a680e35
LA		 7079 if (vcpu->arch.exception.injected)
7080 kvm_x86_ops->queue_exception(vcpu);
664f8e26 7081 /*
a042c26f
LA		 7082 * Do not inject an NMI or interrupt if there is a pending
7083 * exception. Exceptions and interrupts are recognized at
7084 * instruction boundaries, i.e. the start of an instruction.
7085 * Trap-like exceptions, e.g. #DB, have higher priority than
7086 * NMIs and interrupts, i.e. traps are recognized before an
7087 * NMI/interrupt that's pending on the same instruction.
7088 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7089 * priority, but are only generated (pended) during instruction
7090 * execution, i.e. a pending fault-like exception means the
7091 * fault occurred on the *previous* instruction and must be
7092 * serviced prior to recognizing any new events in order to
7093 * fully complete the previous instruction.
664f8e26 7094 */
1a680e35
LA		 7095 else if (!vcpu->arch.exception.pending) {
7096 if (vcpu->arch.nmi_injected)
664f8e26 7097 kvm_x86_ops->set_nmi(vcpu);
1a680e35 7098 else if (vcpu->arch.interrupt.injected)
664f8e26 7099 kvm_x86_ops->set_irq(vcpu);
664f8e26
WL		 7100 }
7101
1a680e35
LA		 7102 /*
7103 * Call check_nested_events() even if we reinjected a previous event
7104 * in order for caller to determine if it should require immediate-exit
7105 * from L2 to L1 due to pending L1 events which require exit
7106 * from L2 to L1.
7107 */
664f8e26
WL		 7108 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7109 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7110 if (r != 0)
7111 return r;
7112 }
7113
7114 /* try to inject new event if pending */
b59bb7bd 7115 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 7116 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7117 vcpu->arch.exception.has_error_code,
7118 vcpu->arch.exception.error_code);
d6e8c854 7119
1a680e35 7120 WARN_ON_ONCE(vcpu->arch.exception.injected);
664f8e26
WL		 7121 vcpu->arch.exception.pending = false;
7122 vcpu->arch.exception.injected = true;
7123
d6e8c854
NA		 7124 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7125 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7126 X86_EFLAGS_RF);
7127
f10c729f
JM		 7128 if (vcpu->arch.exception.nr == DB_VECTOR) {
7129 /*
7130 * This code assumes that nSVM doesn't use
7131 * check_nested_events(). If it does, the
7132 * DR6/DR7 changes should happen before L1
7133 * gets a #VMEXIT for an intercepted #DB in
7134 * L2. (Under VMX, on the other hand, the
7135 * DR6/DR7 changes should not happen in the
7136 * event of a VM-exit to L1 for an intercepted
7137 * #DB in L2.)
7138 */
7139 kvm_deliver_exception_payload(vcpu);
7140 if (vcpu->arch.dr7 & DR7_GD) {
7141 vcpu->arch.dr7 &= ~DR7_GD;
7142 kvm_update_dr7(vcpu);
7143 }
6bdf0662
NA		 7144 }
7145
cfcd20e5 7146 kvm_x86_ops->queue_exception(vcpu);
1a680e35
LA		 7147 }
7148
7149 /* Don't consider new event if we re-injected an event */
7150 if (kvm_event_needs_reinjection(vcpu))
7151 return 0;
7152
7153 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7154 kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 7155 vcpu->arch.smi_pending = false;
52797bf9 7156 ++vcpu->arch.smi_count;
ee2cd4b7 7157 enter_smm(vcpu);
c43203ca 7158 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 7159 --vcpu->arch.nmi_pending;
7160 vcpu->arch.nmi_injected = true;
7161 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 7162 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 7163 /*
7164 * Because interrupts can be injected asynchronously, we are
7165 * calling check_nested_events again here to avoid a race condition.
7166 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7167 * proposal and current concerns. Perhaps we should be setting
7168 * KVM_REQ_EVENT only on certain events and not unconditionally?
7169 */
7170 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7171 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7172 if (r != 0)
7173 return r;
7174 }
95ba8273 7175 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 7176 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7177 false);
7178 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 7179 }
7180 }
ee2cd4b7 7181
b6b8a145 7182 return 0;
95ba8273
GN		 7183}
7184
7460fb4a
AK		 7185static void process_nmi(struct kvm_vcpu *vcpu)
7186{
7187 unsigned limit = 2;
7188
7189 /*
7190 * x86 is limited to one NMI running, and one NMI pending after it.
7191 * If an NMI is already in progress, limit further NMIs to just one.
7192 * Otherwise, allow two (and we'll inject the first one immediately).
7193 */
7194 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7195 limit = 1;
7196
7197 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7198 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7199 kvm_make_request(KVM_REQ_EVENT, vcpu);
7200}
7201
ee2cd4b7 7202static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 7203{
7204 u32 flags = 0;
7205 flags |= seg->g << 23;
7206 flags |= seg->db << 22;
7207 flags |= seg->l << 21;
7208 flags |= seg->avl << 20;
7209 flags |= seg->present << 15;
7210 flags |= seg->dpl << 13;
7211 flags |= seg->s << 12;
7212 flags |= seg->type << 8;
7213 return flags;
7214}
7215
ee2cd4b7 7216static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7217{
7218 struct kvm_segment seg;
7219 int offset;
7220
7221 kvm_get_segment(vcpu, &seg, n);
7222 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7223
7224 if (n < 3)
7225 offset = 0x7f84 + n * 12;
7226 else
7227 offset = 0x7f2c + (n - 3) * 12;
7228
7229 put_smstate(u32, buf, offset + 8, seg.base);
7230 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 7231 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7232}
7233
efbb288a 7234#ifdef CONFIG_X86_64
ee2cd4b7 7235static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7236{
7237 struct kvm_segment seg;
7238 int offset;
7239 u16 flags;
7240
7241 kvm_get_segment(vcpu, &seg, n);
7242 offset = 0x7e00 + n * 16;
7243
ee2cd4b7 7244 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 7245 put_smstate(u16, buf, offset, seg.selector);
7246 put_smstate(u16, buf, offset + 2, flags);
7247 put_smstate(u32, buf, offset + 4, seg.limit);
7248 put_smstate(u64, buf, offset + 8, seg.base);
7249}
efbb288a 7250#endif
660a5d51 7251
ee2cd4b7 7252static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7253{
7254 struct desc_ptr dt;
7255 struct kvm_segment seg;
7256 unsigned long val;
7257 int i;
7258
7259 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7260 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7261 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7262 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7263
7264 for (i = 0; i < 8; i++)
7265 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7266
7267 kvm_get_dr(vcpu, 6, &val);
7268 put_smstate(u32, buf, 0x7fcc, (u32)val);
7269 kvm_get_dr(vcpu, 7, &val);
7270 put_smstate(u32, buf, 0x7fc8, (u32)val);
7271
7272 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7273 put_smstate(u32, buf, 0x7fc4, seg.selector);
7274 put_smstate(u32, buf, 0x7f64, seg.base);
7275 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 7276 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7277
7278 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7279 put_smstate(u32, buf, 0x7fc0, seg.selector);
7280 put_smstate(u32, buf, 0x7f80, seg.base);
7281 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 7282 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7283
7284 kvm_x86_ops->get_gdt(vcpu, &dt);
7285 put_smstate(u32, buf, 0x7f74, dt.address);
7286 put_smstate(u32, buf, 0x7f70, dt.size);
7287
7288 kvm_x86_ops->get_idt(vcpu, &dt);
7289 put_smstate(u32, buf, 0x7f58, dt.address);
7290 put_smstate(u32, buf, 0x7f54, dt.size);
7291
7292 for (i = 0; i < 6; i++)
ee2cd4b7 7293 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 7294
7295 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7296
7297 /* revision id */
7298 put_smstate(u32, buf, 0x7efc, 0x00020000);
7299 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7300}
7301
ee2cd4b7 7302static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7303{
7304#ifdef CONFIG_X86_64
7305 struct desc_ptr dt;
7306 struct kvm_segment seg;
7307 unsigned long val;
7308 int i;
7309
7310 for (i = 0; i < 16; i++)
7311 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7312
7313 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7314 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7315
7316 kvm_get_dr(vcpu, 6, &val);
7317 put_smstate(u64, buf, 0x7f68, val);
7318 kvm_get_dr(vcpu, 7, &val);
7319 put_smstate(u64, buf, 0x7f60, val);
7320
7321 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7322 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7323 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7324
7325 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7326
7327 /* revision id */
7328 put_smstate(u32, buf, 0x7efc, 0x00020064);
7329
7330 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7331
7332 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7333 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 7334 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7335 put_smstate(u32, buf, 0x7e94, seg.limit);
7336 put_smstate(u64, buf, 0x7e98, seg.base);
7337
7338 kvm_x86_ops->get_idt(vcpu, &dt);
7339 put_smstate(u32, buf, 0x7e84, dt.size);
7340 put_smstate(u64, buf, 0x7e88, dt.address);
7341
7342 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7343 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 7344 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7345 put_smstate(u32, buf, 0x7e74, seg.limit);
7346 put_smstate(u64, buf, 0x7e78, seg.base);
7347
7348 kvm_x86_ops->get_gdt(vcpu, &dt);
7349 put_smstate(u32, buf, 0x7e64, dt.size);
7350 put_smstate(u64, buf, 0x7e68, dt.address);
7351
7352 for (i = 0; i < 6; i++)
ee2cd4b7 7353 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 7354#else
7355 WARN_ON_ONCE(1);
7356#endif
7357}
7358
ee2cd4b7 7359static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 7360{
660a5d51 7361 struct kvm_segment cs, ds;
18c3626e 7362 struct desc_ptr dt;
660a5d51
PB		 7363 char buf[512];
7364 u32 cr0;
7365
660a5d51 7366 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7367 memset(buf, 0, 512);
d6321d49 7368 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7369 enter_smm_save_state_64(vcpu, buf);
660a5d51 7370 else
ee2cd4b7 7371 enter_smm_save_state_32(vcpu, buf);
660a5d51 7372
0234bf88
LP		 7373 /*
7374 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7375 * vCPU state (e.g. leave guest mode) after we've saved the state into
7376 * the SMM state-save area.
7377 */
7378 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7379
7380 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7381 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7382
7383 if (kvm_x86_ops->get_nmi_mask(vcpu))
7384 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7385 else
7386 kvm_x86_ops->set_nmi_mask(vcpu, true);
7387
7388 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7389 kvm_rip_write(vcpu, 0x8000);
7390
7391 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7392 kvm_x86_ops->set_cr0(vcpu, cr0);
7393 vcpu->arch.cr0 = cr0;
7394
7395 kvm_x86_ops->set_cr4(vcpu, 0);
7396
18c3626e
PB		 7397 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7398 dt.address = dt.size = 0;
7399 kvm_x86_ops->set_idt(vcpu, &dt);
7400
660a5d51
PB		 7401 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7402
7403 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7404 cs.base = vcpu->arch.smbase;
7405
7406 ds.selector = 0;
7407 ds.base = 0;
7408
7409 cs.limit = ds.limit = 0xffffffff;
7410 cs.type = ds.type = 0x3;
7411 cs.dpl = ds.dpl = 0;
7412 cs.db = ds.db = 0;
7413 cs.s = ds.s = 1;
7414 cs.l = ds.l = 0;
7415 cs.g = ds.g = 1;
7416 cs.avl = ds.avl = 0;
7417 cs.present = ds.present = 1;
7418 cs.unusable = ds.unusable = 0;
7419 cs.padding = ds.padding = 0;
7420
7421 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7422 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7423 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7424 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7425 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7426 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7427
d6321d49 7428 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 7429 kvm_x86_ops->set_efer(vcpu, 0);
7430
7431 kvm_update_cpuid(vcpu);
7432 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7433}
7434
ee2cd4b7 7435static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7436{
7437 vcpu->arch.smi_pending = true;
7438 kvm_make_request(KVM_REQ_EVENT, vcpu);
7439}
7440
2860c4b1
PB		 7441void kvm_make_scan_ioapic_request(struct kvm *kvm)
7442{
7443 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7444}
7445
3d81bc7e 7446static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7447{
3d81bc7e
YZ		 7448 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7449 return;
c7c9c56c 7450
6308630b 7451 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7452
b053b2ae 7453 if (irqchip_split(vcpu->kvm))
6308630b 7454 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7455 else {
fa59cc00 7456 if (vcpu->arch.apicv_active)
d62caabb 7457 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 7458 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7459 }
e40ff1d6
LA		 7460
7461 if (is_guest_mode(vcpu))
7462 vcpu->arch.load_eoi_exitmap_pending = true;
7463 else
7464 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7465}
7466
7467static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7468{
7469 u64 eoi_exit_bitmap[4];
7470
7471 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7472 return;
7473
5c919412
AS		 7474 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7475 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7476 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7477}
7478
93065ac7
MH		 7479int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7480 unsigned long start, unsigned long end,
7481 bool blockable)
b1394e74
RK		 7482{
7483 unsigned long apic_address;
7484
7485 /*
7486 * The physical address of apic access page is stored in the VMCS.
7487 * Update it when it becomes invalid.
7488 */
7489 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7490 if (start <= apic_address && apic_address < end)
7491 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
93065ac7
MH		 7492
7493 return 0;
b1394e74
RK		 7494}
7495
4256f43f
TC		 7496void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7497{
c24ae0dc
TC		 7498 struct page *page = NULL;
7499
35754c98 7500 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7501 return;
7502
4256f43f
TC		 7503 if (!kvm_x86_ops->set_apic_access_page_addr)
7504 return;
7505
c24ae0dc 7506 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7507 if (is_error_page(page))
7508 return;
c24ae0dc
TC		 7509 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7510
7511 /*
7512 * Do not pin apic access page in memory, the MMU notifier
7513 * will call us again if it is migrated or swapped out.
7514 */
7515 put_page(page);
4256f43f
TC		 7516}
7517EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7518
d264ee0c
SC		 7519void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
7520{
7521 smp_send_reschedule(vcpu->cpu);
7522}
7523EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
7524
9357d939 7525/*
362c698f 7526 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7527 * exiting to the userspace. Otherwise, the value will be returned to the
7528 * userspace.
7529 */
851ba692 7530static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7531{
7532 int r;
62a193ed
MG		 7533 bool req_int_win =
7534 dm_request_for_irq_injection(vcpu) &&
7535 kvm_cpu_accept_dm_intr(vcpu);
7536
730dca42 7537 bool req_immediate_exit = false;
b6c7a5dc 7538
2fa6e1e1 7539 if (kvm_request_pending(vcpu)) {
7f7f1ba3
PB		 7540 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7541 kvm_x86_ops->get_vmcs12_pages(vcpu);
a8eeb04a 7542 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7543 kvm_mmu_unload(vcpu);
a8eeb04a 7544 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7545 __kvm_migrate_timers(vcpu);
d828199e
MT		 7546 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7547 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7548 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7549 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7550 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7551 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7552 if (unlikely(r))
7553 goto out;
7554 }
a8eeb04a 7555 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7556 kvm_mmu_sync_roots(vcpu);
6e42782f
JS		 7557 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7558 kvm_mmu_load_cr3(vcpu);
a8eeb04a 7559 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7560 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7561 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7562 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7563 r = 0;
7564 goto out;
7565 }
a8eeb04a 7566 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7567 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7568 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7569 r = 0;
7570 goto out;
7571 }
af585b92
GN		 7572 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7573 /* Page is swapped out. Do synthetic halt */
7574 vcpu->arch.apf.halted = true;
7575 r = 1;
7576 goto out;
7577 }
c9aaa895
GC		 7578 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7579 record_steal_time(vcpu);
64d60670
PB		 7580 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7581 process_smi(vcpu);
7460fb4a
AK		 7582 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7583 process_nmi(vcpu);
f5132b01 7584 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7585 kvm_pmu_handle_event(vcpu);
f5132b01 7586 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7587 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7588 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7589 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7590 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7591 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7592 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7593 vcpu->run->eoi.vector =
7594 vcpu->arch.pending_ioapic_eoi;
7595 r = 0;
7596 goto out;
7597 }
7598 }
3d81bc7e
YZ		 7599 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7600 vcpu_scan_ioapic(vcpu);
e40ff1d6
LA		 7601 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7602 vcpu_load_eoi_exitmap(vcpu);
4256f43f
TC		 7603 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7604 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7605 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7606 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7607 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7608 r = 0;
7609 goto out;
7610 }
e516cebb
AS		 7611 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7612 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7613 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7614 r = 0;
7615 goto out;
7616 }
db397571
AS		 7617 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7618 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7619 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7620 r = 0;
7621 goto out;
7622 }
f3b138c5
AS		 7623
7624 /*
7625 * KVM_REQ_HV_STIMER has to be processed after
7626 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7627 * depend on the guest clock being up-to-date
7628 */
1f4b34f8
AS		 7629 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7630 kvm_hv_process_stimers(vcpu);
2f52d58c 7631 }
b93463aa 7632
b463a6f7 7633 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7634 ++vcpu->stat.req_event;
66450a21
JK		 7635 kvm_apic_accept_events(vcpu);
7636 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7637 r = 1;
7638 goto out;
7639 }
7640
b6b8a145
JK		 7641 if (inject_pending_event(vcpu, req_int_win) != 0)
7642 req_immediate_exit = true;
321c5658 7643 else {
cc3d967f 7644 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7645 *
cc3d967f
LP		 7646 * SMIs have three cases:
7647 * 1) They can be nested, and then there is nothing to
7648 * do here because RSM will cause a vmexit anyway.
7649 * 2) There is an ISA-specific reason why SMI cannot be
7650 * injected, and the moment when this changes can be
7651 * intercepted.
7652 * 3) Or the SMI can be pending because
7653 * inject_pending_event has completed the injection
7654 * of an IRQ or NMI from the previous vmexit, and
7655 * then we request an immediate exit to inject the
7656 * SMI.
c43203ca
PB		 7657 */
7658 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7659 if (!kvm_x86_ops->enable_smi_window(vcpu))
7660 req_immediate_exit = true;
321c5658
YS		 7661 if (vcpu->arch.nmi_pending)
7662 kvm_x86_ops->enable_nmi_window(vcpu);
7663 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7664 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7665 WARN_ON(vcpu->arch.exception.pending);
321c5658 7666 }
b463a6f7
AK		 7667
7668 if (kvm_lapic_enabled(vcpu)) {
7669 update_cr8_intercept(vcpu);
7670 kvm_lapic_sync_to_vapic(vcpu);
7671 }
7672 }
7673
d8368af8
AK		 7674 r = kvm_mmu_reload(vcpu);
7675 if (unlikely(r)) {
d905c069 7676 goto cancel_injection;
d8368af8
AK		 7677 }
7678
b6c7a5dc
HB		 7679 preempt_disable();
7680
7681 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7682
7683 /*
7684 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7685 * IPI are then delayed after guest entry, which ensures that they
7686 * result in virtual interrupt delivery.
7687 */
7688 local_irq_disable();
6b7e2d09
XG		 7689 vcpu->mode = IN_GUEST_MODE;
7690
01b71917
MT		 7691 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7692
0f127d12 7693 /*
b95234c8 7694 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7695 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 7696 *
7697 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7698 * pairs with the memory barrier implicit in pi_test_and_set_on
7699 * (see vmx_deliver_posted_interrupt).
7700 *
7701 * 3) This also orders the write to mode from any reads to the page
7702 * tables done while the VCPU is running. Please see the comment
7703 * in kvm_flush_remote_tlbs.
6b7e2d09 7704 */
01b71917 7705 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7706
b95234c8
PB		 7707 /*
7708 * This handles the case where a posted interrupt was
7709 * notified with kvm_vcpu_kick.
7710 */
fa59cc00
LA		 7711 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7712 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7713
2fa6e1e1 7714 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7715 || need_resched() || signal_pending(current)) {
6b7e2d09 7716 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7717 smp_wmb();
6c142801
AK		 7718 local_irq_enable();
7719 preempt_enable();
01b71917 7720 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7721 r = 1;
d905c069 7722 goto cancel_injection;
6c142801
AK		 7723 }
7724
fc5b7f3b
DM		 7725 kvm_load_guest_xcr0(vcpu);
7726
c43203ca
PB		 7727 if (req_immediate_exit) {
7728 kvm_make_request(KVM_REQ_EVENT, vcpu);
d264ee0c 7729 kvm_x86_ops->request_immediate_exit(vcpu);
c43203ca 7730 }
d6185f20 7731
8b89fe1f 7732 trace_kvm_entry(vcpu->vcpu_id);
9c48d517
WL		 7733 if (lapic_timer_advance_ns)
7734 wait_lapic_expire(vcpu);
6edaa530 7735 guest_enter_irqoff();
b6c7a5dc 7736
42dbaa5a 7737 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7738 set_debugreg(0, 7);
7739 set_debugreg(vcpu->arch.eff_db[0], 0);
7740 set_debugreg(vcpu->arch.eff_db[1], 1);
7741 set_debugreg(vcpu->arch.eff_db[2], 2);
7742 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7743 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7744 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7745 }
b6c7a5dc 7746
851ba692 7747 kvm_x86_ops->run(vcpu);
b6c7a5dc 7748
c77fb5fe
PB		 7749 /*
7750 * Do this here before restoring debug registers on the host. And
7751 * since we do this before handling the vmexit, a DR access vmexit
7752 * can (a) read the correct value of the debug registers, (b) set
7753 * KVM_DEBUGREG_WONT_EXIT again.
7754 */
7755 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7756 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7757 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7758 kvm_update_dr0123(vcpu);
7759 kvm_update_dr6(vcpu);
7760 kvm_update_dr7(vcpu);
7761 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7762 }
7763
24f1e32c
FW		 7764 /*
7765 * If the guest has used debug registers, at least dr7
7766 * will be disabled while returning to the host.
7767 * If we don't have active breakpoints in the host, we don't
7768 * care about the messed up debug address registers. But if
7769 * we have some of them active, restore the old state.
7770 */
59d8eb53 7771 if (hw_breakpoint_active())
24f1e32c 7772 hw_breakpoint_restore();
42dbaa5a 7773
4ba76538 7774 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7775
6b7e2d09 7776 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7777 smp_wmb();
a547c6db 7778
fc5b7f3b
DM		 7779 kvm_put_guest_xcr0(vcpu);
7780
dd60d217 7781 kvm_before_interrupt(vcpu);
a547c6db 7782 kvm_x86_ops->handle_external_intr(vcpu);
dd60d217 7783 kvm_after_interrupt(vcpu);
b6c7a5dc
HB		 7784
7785 ++vcpu->stat.exits;
7786
f2485b3e 7787 guest_exit_irqoff();
b6c7a5dc 7788
f2485b3e 7789 local_irq_enable();
b6c7a5dc
HB		 7790 preempt_enable();
7791
f656ce01 7792 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7793
b6c7a5dc
HB		 7794 /*
7795 * Profile KVM exit RIPs:
7796 */
7797 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7798 unsigned long rip = kvm_rip_read(vcpu);
7799 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7800 }
7801
cc578287
ZA		 7802 if (unlikely(vcpu->arch.tsc_always_catchup))
7803 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7804
5cfb1d5a
MT		 7805 if (vcpu->arch.apic_attention)
7806 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7807
618232e2 7808 vcpu->arch.gpa_available = false;
851ba692 7809 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7810 return r;
7811
7812cancel_injection:
7813 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7814 if (unlikely(vcpu->arch.apic_attention))
7815 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7816out:
7817 return r;
7818}
b6c7a5dc 7819
362c698f
PB		 7820static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7821{
bf9f6ac8
FW		 7822 if (!kvm_arch_vcpu_runnable(vcpu) &&
7823 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7824 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7825 kvm_vcpu_block(vcpu);
7826 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7827
7828 if (kvm_x86_ops->post_block)
7829 kvm_x86_ops->post_block(vcpu);
7830
9c8fd1ba
PB		 7831 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7832 return 1;
7833 }
362c698f
PB		 7834
7835 kvm_apic_accept_events(vcpu);
7836 switch(vcpu->arch.mp_state) {
7837 case KVM_MP_STATE_HALTED:
7838 vcpu->arch.pv.pv_unhalted = false;
7839 vcpu->arch.mp_state =
7840 KVM_MP_STATE_RUNNABLE;
7841 case KVM_MP_STATE_RUNNABLE:
7842 vcpu->arch.apf.halted = false;
7843 break;
7844 case KVM_MP_STATE_INIT_RECEIVED:
7845 break;
7846 default:
7847 return -EINTR;
7848 break;
7849 }
7850 return 1;
7851}
09cec754 7852
5d9bc648
PB		 7853static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7854{
0ad3bed6
PB		 7855 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7856 kvm_x86_ops->check_nested_events(vcpu, false);
7857
5d9bc648
PB		 7858 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7859 !vcpu->arch.apf.halted);
7860}
7861
362c698f 7862static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7863{
7864 int r;
f656ce01 7865 struct kvm *kvm = vcpu->kvm;
d7690175 7866
f656ce01 7867 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
c595ceee 7868 vcpu->arch.l1tf_flush_l1d = true;
d7690175 7869
362c698f 7870 for (;;) {
58f800d5 7871 if (kvm_vcpu_running(vcpu)) {
851ba692 7872 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7873 } else {
362c698f 7874 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7875 }
7876
09cec754
GN		 7877 if (r <= 0)
7878 break;
7879
72875d8a 7880 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7881 if (kvm_cpu_has_pending_timer(vcpu))
7882 kvm_inject_pending_timer_irqs(vcpu);
7883
782d422b
MG		 7884 if (dm_request_for_irq_injection(vcpu) &&
7885 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7886 r = 0;
7887 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7888 ++vcpu->stat.request_irq_exits;
362c698f 7889 break;
09cec754 7890 }
af585b92
GN		 7891
7892 kvm_check_async_pf_completion(vcpu);
7893
09cec754
GN		 7894 if (signal_pending(current)) {
7895 r = -EINTR;
851ba692 7896 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7897 ++vcpu->stat.signal_exits;
362c698f 7898 break;
09cec754
GN		 7899 }
7900 if (need_resched()) {
f656ce01 7901 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7902 cond_resched();
f656ce01 7903 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7904 }
b6c7a5dc
HB		 7905 }
7906
f656ce01 7907 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7908
7909 return r;
7910}
7911
716d51ab
GN		 7912static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7913{
7914 int r;
7915 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
0ce97a2b 7916 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
716d51ab
GN		 7917 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7918 if (r != EMULATE_DONE)
7919 return 0;
7920 return 1;
7921}
7922
7923static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7924{
7925 BUG_ON(!vcpu->arch.pio.count);
7926
7927 return complete_emulated_io(vcpu);
7928}
7929
f78146b0
AK		 7930/*
7931 * Implements the following, as a state machine:
7932 *
7933 * read:
7934 * for each fragment
87da7e66
XG		 7935 * for each mmio piece in the fragment
7936 * write gpa, len
7937 * exit
7938 * copy data
f78146b0
AK		 7939 * execute insn
7940 *
7941 * write:
7942 * for each fragment
87da7e66
XG		 7943 * for each mmio piece in the fragment
7944 * write gpa, len
7945 * copy data
7946 * exit
f78146b0 7947 */
716d51ab 7948static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7949{
7950 struct kvm_run *run = vcpu->run;
f78146b0 7951 struct kvm_mmio_fragment *frag;
87da7e66 7952 unsigned len;
5287f194 7953
716d51ab 7954 BUG_ON(!vcpu->mmio_needed);
5287f194 7955
716d51ab 7956 /* Complete previous fragment */
87da7e66
XG		 7957 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7958 len = min(8u, frag->len);
716d51ab 7959 if (!vcpu->mmio_is_write)
87da7e66
XG		 7960 memcpy(frag->data, run->mmio.data, len);
7961
7962 if (frag->len <= 8) {
7963 /* Switch to the next fragment. */
7964 frag++;
7965 vcpu->mmio_cur_fragment++;
7966 } else {
7967 /* Go forward to the next mmio piece. */
7968 frag->data += len;
7969 frag->gpa += len;
7970 frag->len -= len;
7971 }
7972
a08d3b3b 7973 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7974 vcpu->mmio_needed = 0;
0912c977
PB		 7975
7976 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7977 if (vcpu->mmio_is_write)
716d51ab
GN		 7978 return 1;
7979 vcpu->mmio_read_completed = 1;
7980 return complete_emulated_io(vcpu);
7981 }
87da7e66 7982
716d51ab
GN		 7983 run->exit_reason = KVM_EXIT_MMIO;
7984 run->mmio.phys_addr = frag->gpa;
7985 if (vcpu->mmio_is_write)
87da7e66
XG		 7986 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7987 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7988 run->mmio.is_write = vcpu->mmio_is_write;
7989 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7990 return 0;
5287f194
AK		 7991}
7992
822f312d
SAS		 7993/* Swap (qemu) user FPU context for the guest FPU context. */
7994static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7995{
7996 preempt_disable();
7997 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
7998 /* PKRU is separately restored in kvm_x86_ops->run. */
7999 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
8000 ~XFEATURE_MASK_PKRU);
8001 preempt_enable();
8002 trace_kvm_fpu(1);
8003}
8004
8005/* When vcpu_run ends, restore user space FPU context. */
8006static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8007{
8008 preempt_disable();
8009 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
8010 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
8011 preempt_enable();
8012 ++vcpu->stat.fpu_reload;
8013 trace_kvm_fpu(0);
8014}
8015
b6c7a5dc
HB		 8016int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8017{
8018 int r;
b6c7a5dc 8019
accb757d 8020 vcpu_load(vcpu);
20b7035c 8021 kvm_sigset_activate(vcpu);
5663d8f9
PX		 8022 kvm_load_guest_fpu(vcpu);
8023
a4535290 8024 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 8025 if (kvm_run->immediate_exit) {
8026 r = -EINTR;
8027 goto out;
8028 }
b6c7a5dc 8029 kvm_vcpu_block(vcpu);
66450a21 8030 kvm_apic_accept_events(vcpu);
72875d8a 8031 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 8032 r = -EAGAIN;
a0595000
JS		 8033 if (signal_pending(current)) {
8034 r = -EINTR;
8035 vcpu->run->exit_reason = KVM_EXIT_INTR;
8036 ++vcpu->stat.signal_exits;
8037 }
ac9f6dc0 8038 goto out;
b6c7a5dc
HB		 8039 }
8040
01643c51
KH		 8041 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8042 r = -EINVAL;
8043 goto out;
8044 }
8045
8046 if (vcpu->run->kvm_dirty_regs) {
8047 r = sync_regs(vcpu);
8048 if (r != 0)
8049 goto out;
8050 }
8051
b6c7a5dc 8052 /* re-sync apic's tpr */
35754c98 8053 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 8054 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8055 r = -EINVAL;
8056 goto out;
8057 }
8058 }
b6c7a5dc 8059
716d51ab
GN		 8060 if (unlikely(vcpu->arch.complete_userspace_io)) {
8061 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8062 vcpu->arch.complete_userspace_io = NULL;
8063 r = cui(vcpu);
8064 if (r <= 0)
5663d8f9 8065 goto out;
716d51ab
GN		 8066 } else
8067 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 8068
460df4c1
PB		 8069 if (kvm_run->immediate_exit)
8070 r = -EINTR;
8071 else
8072 r = vcpu_run(vcpu);
b6c7a5dc
HB		 8073
8074out:
5663d8f9 8075 kvm_put_guest_fpu(vcpu);
01643c51
KH		 8076 if (vcpu->run->kvm_valid_regs)
8077 store_regs(vcpu);
f1d86e46 8078 post_kvm_run_save(vcpu);
20b7035c 8079 kvm_sigset_deactivate(vcpu);
b6c7a5dc 8080
accb757d 8081 vcpu_put(vcpu);
b6c7a5dc
HB		 8082 return r;
8083}
8084
01643c51 8085static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8086{
7ae441ea
GN		 8087 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8088 /*
8089 * We are here if userspace calls get_regs() in the middle of
8090 * instruction emulation. Registers state needs to be copied
4a969980 8091 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 8092 * that usually, but some bad designed PV devices (vmware
8093 * backdoor interface) need this to work
8094 */
dd856efa 8095 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 8096 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8097 }
5fdbf976
MT		 8098 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
8099 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
8100 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
8101 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
8102 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
8103 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
8104 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8105 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 8106#ifdef CONFIG_X86_64
5fdbf976
MT		 8107 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
8108 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
8109 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
8110 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
8111 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
8112 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
8113 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
8114 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 8115#endif
8116
5fdbf976 8117 regs->rip = kvm_rip_read(vcpu);
91586a3b 8118 regs->rflags = kvm_get_rflags(vcpu);
01643c51 8119}
b6c7a5dc 8120
01643c51
KH		 8121int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8122{
8123 vcpu_load(vcpu);
8124 __get_regs(vcpu, regs);
1fc9b76b 8125 vcpu_put(vcpu);
b6c7a5dc
HB		 8126 return 0;
8127}
8128
01643c51 8129static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8130{
7ae441ea
GN		 8131 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8132 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8133
5fdbf976
MT		 8134 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
8135 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
8136 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
8137 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
8138 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
8139 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
8140 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
8141 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 8142#ifdef CONFIG_X86_64
5fdbf976
MT		 8143 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
8144 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
8145 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
8146 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
8147 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
8148 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
8149 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
8150 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 8151#endif
8152
5fdbf976 8153 kvm_rip_write(vcpu, regs->rip);
d73235d1 8154 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 8155
b4f14abd
JK		 8156 vcpu->arch.exception.pending = false;
8157
3842d135 8158 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 8159}
3842d135 8160
01643c51
KH		 8161int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8162{
8163 vcpu_load(vcpu);
8164 __set_regs(vcpu, regs);
875656fe 8165 vcpu_put(vcpu);
b6c7a5dc
HB		 8166 return 0;
8167}
8168
b6c7a5dc
HB		 8169void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8170{
8171 struct kvm_segment cs;
8172
3e6e0aab 8173 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 8174 *db = cs.db;
8175 *l = cs.l;
8176}
8177EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8178
01643c51 8179static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8180{
89a27f4d 8181 struct desc_ptr dt;
b6c7a5dc 8182
3e6e0aab
GT		 8183 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8184 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8185 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8186 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8187 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8188 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8189
3e6e0aab
GT		 8190 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8191 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 8192
8193 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 8194 sregs->idt.limit = dt.size;
8195 sregs->idt.base = dt.address;
b6c7a5dc 8196 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 8197 sregs->gdt.limit = dt.size;
8198 sregs->gdt.base = dt.address;
b6c7a5dc 8199
4d4ec087 8200 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 8201 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 8202 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 8203 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 8204 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 8205 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 8206 sregs->apic_base = kvm_get_apic_base(vcpu);
8207
923c61bb 8208 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 8209
04140b41 8210 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 8211 set_bit(vcpu->arch.interrupt.nr,
8212 (unsigned long *)sregs->interrupt_bitmap);
01643c51 8213}
16d7a191 8214
01643c51
KH		 8215int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8216 struct kvm_sregs *sregs)
8217{
8218 vcpu_load(vcpu);
8219 __get_sregs(vcpu, sregs);
bcdec41c 8220 vcpu_put(vcpu);
b6c7a5dc
HB		 8221 return 0;
8222}
8223
62d9f0db
MT		 8224int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8225 struct kvm_mp_state *mp_state)
8226{
fd232561
CD		 8227 vcpu_load(vcpu);
8228
66450a21 8229 kvm_apic_accept_events(vcpu);
6aef266c
SV		 8230 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8231 vcpu->arch.pv.pv_unhalted)
8232 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8233 else
8234 mp_state->mp_state = vcpu->arch.mp_state;
8235
fd232561 8236 vcpu_put(vcpu);
62d9f0db
MT		 8237 return 0;
8238}
8239
8240int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8241 struct kvm_mp_state *mp_state)
8242{
e83dff5e
CD		 8243 int ret = -EINVAL;
8244
8245 vcpu_load(vcpu);
8246
bce87cce 8247 if (!lapic_in_kernel(vcpu) &&
66450a21 8248 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 8249 goto out;
66450a21 8250
28bf2888
DH		 8251 /* INITs are latched while in SMM */
8252 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8253 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8254 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 8255 goto out;
28bf2888 8256
66450a21
JK		 8257 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8258 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8259 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8260 } else
8261 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 8262 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 8263
8264 ret = 0;
8265out:
8266 vcpu_put(vcpu);
8267 return ret;
62d9f0db
MT		 8268}
8269
7f3d35fd
KW		 8270int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8271 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 8272{
9d74191a 8273 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 8274 int ret;
e01c2426 8275
8ec4722d 8276 init_emulate_ctxt(vcpu);
c697518a 8277
7f3d35fd 8278 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 8279 has_error_code, error_code);
c697518a 8280
c697518a 8281 if (ret)
19d04437 8282 return EMULATE_FAIL;
37817f29 8283
9d74191a
TY		 8284 kvm_rip_write(vcpu, ctxt->eip);
8285 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 8286 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 8287 return EMULATE_DONE;
37817f29
IE		 8288}
8289EXPORT_SYMBOL_GPL(kvm_task_switch);
8290
3140c156 8291static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
f2981033 8292{
74fec5b9
TL		 8293 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8294 (sregs->cr4 & X86_CR4_OSXSAVE))
8295 return -EINVAL;
8296
37b95951 8297 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 8298 /*
8299 * When EFER.LME and CR0.PG are set, the processor is in
8300 * 64-bit mode (though maybe in a 32-bit code segment).
8301 * CR4.PAE and EFER.LMA must be set.
8302 */
37b95951 8303 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 8304 || !(sregs->efer & EFER_LMA))
8305 return -EINVAL;
8306 } else {
8307 /*
8308 * Not in 64-bit mode: EFER.LMA is clear and the code
8309 * segment cannot be 64-bit.
8310 */
8311 if (sregs->efer & EFER_LMA || sregs->cs.l)
8312 return -EINVAL;
8313 }
8314
8315 return 0;
8316}
8317
01643c51 8318static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8319{
58cb628d 8320 struct msr_data apic_base_msr;
b6c7a5dc 8321 int mmu_reset_needed = 0;
c4d21882 8322 int cpuid_update_needed = 0;
63f42e02 8323 int pending_vec, max_bits, idx;
89a27f4d 8324 struct desc_ptr dt;
b4ef9d4e
CD		 8325 int ret = -EINVAL;
8326
f2981033 8327 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 8328 goto out;
f2981033 8329
d3802286
JM		 8330 apic_base_msr.data = sregs->apic_base;
8331 apic_base_msr.host_initiated = true;
8332 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 8333 goto out;
6d1068b3 8334
89a27f4d
GN		 8335 dt.size = sregs->idt.limit;
8336 dt.address = sregs->idt.base;
b6c7a5dc 8337 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 8338 dt.size = sregs->gdt.limit;
8339 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 8340 kvm_x86_ops->set_gdt(vcpu, &dt);
8341
ad312c7c 8342 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 8343 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 8344 vcpu->arch.cr3 = sregs->cr3;
aff48baa 8345 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 8346
2d3ad1f4 8347 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 8348
f6801dff 8349 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 8350 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 8351
4d4ec087 8352 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 8353 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 8354 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 8355
fc78f519 8356 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
c4d21882
WH		 8357 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8358 (X86_CR4_OSXSAVE | X86_CR4_PKE));
b6c7a5dc 8359 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
c4d21882 8360 if (cpuid_update_needed)
00b27a3e 8361 kvm_update_cpuid(vcpu);
63f42e02
XG		 8362
8363 idx = srcu_read_lock(&vcpu->kvm->srcu);
d35b34a9 8364 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu)) {
9f8fe504 8365 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 8366 mmu_reset_needed = 1;
8367 }
63f42e02 8368 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 8369
8370 if (mmu_reset_needed)
8371 kvm_mmu_reset_context(vcpu);
8372
a50abc3b 8373 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 8374 pending_vec = find_first_bit(
8375 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8376 if (pending_vec < max_bits) {
66fd3f7f 8377 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 8378 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 8379 }
8380
3e6e0aab
GT		 8381 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8382 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8383 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8384 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8385 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8386 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8387
3e6e0aab
GT		 8388 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8389 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 8390
5f0269f5
ME		 8391 update_cr8_intercept(vcpu);
8392
9c3e4aab 8393 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 8394 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 8395 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 8396 !is_protmode(vcpu))
9c3e4aab
MT		 8397 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8398
3842d135
AK		 8399 kvm_make_request(KVM_REQ_EVENT, vcpu);
8400
b4ef9d4e
CD		 8401 ret = 0;
8402out:
01643c51
KH		 8403 return ret;
8404}
8405
8406int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8407 struct kvm_sregs *sregs)
8408{
8409 int ret;
8410
8411 vcpu_load(vcpu);
8412 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 8413 vcpu_put(vcpu);
8414 return ret;
b6c7a5dc
HB		 8415}
8416
d0bfb940
JK		 8417int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8418 struct kvm_guest_debug *dbg)
b6c7a5dc 8419{
355be0b9 8420 unsigned long rflags;
ae675ef0 8421 int i, r;
b6c7a5dc 8422
66b56562
CD		 8423 vcpu_load(vcpu);
8424
4f926bf2
JK		 8425 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8426 r = -EBUSY;
8427 if (vcpu->arch.exception.pending)
2122ff5e 8428 goto out;
4f926bf2
JK		 8429 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8430 kvm_queue_exception(vcpu, DB_VECTOR);
8431 else
8432 kvm_queue_exception(vcpu, BP_VECTOR);
8433 }
8434
91586a3b
JK		 8435 /*
8436 * Read rflags as long as potentially injected trace flags are still
8437 * filtered out.
8438 */
8439 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 8440
8441 vcpu->guest_debug = dbg->control;
8442 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8443 vcpu->guest_debug = 0;
8444
8445 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 8446 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8447 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 8448 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 8449 } else {
8450 for (i = 0; i < KVM_NR_DB_REGS; i++)
8451 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 8452 }
c8639010 8453 kvm_update_dr7(vcpu);
ae675ef0 8454
f92653ee
JK		 8455 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8456 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8457 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 8458
91586a3b
JK		 8459 /*
8460 * Trigger an rflags update that will inject or remove the trace
8461 * flags.
8462 */
8463 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 8464
a96036b8 8465 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 8466
4f926bf2 8467 r = 0;
d0bfb940 8468
2122ff5e 8469out:
66b56562 8470 vcpu_put(vcpu);
b6c7a5dc
HB		 8471 return r;
8472}
8473
8b006791
ZX		 8474/*
8475 * Translate a guest virtual address to a guest physical address.
8476 */
8477int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8478 struct kvm_translation *tr)
8479{
8480 unsigned long vaddr = tr->linear_address;
8481 gpa_t gpa;
f656ce01 8482 int idx;
8b006791 8483
1da5b61d
CD		 8484 vcpu_load(vcpu);
8485
f656ce01 8486 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8487 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8488 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8489 tr->physical_address = gpa;
8490 tr->valid = gpa != UNMAPPED_GVA;
8491 tr->writeable = 1;
8492 tr->usermode = 0;
8b006791 8493
1da5b61d 8494 vcpu_put(vcpu);
8b006791
ZX		 8495 return 0;
8496}
8497
d0752060
HB		 8498int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8499{
1393123e 8500 struct fxregs_state *fxsave;
d0752060 8501
1393123e 8502 vcpu_load(vcpu);
d0752060 8503
1393123e 8504 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060
HB		 8505 memcpy(fpu->fpr, fxsave->st_space, 128);
8506 fpu->fcw = fxsave->cwd;
8507 fpu->fsw = fxsave->swd;
8508 fpu->ftwx = fxsave->twd;
8509 fpu->last_opcode = fxsave->fop;
8510 fpu->last_ip = fxsave->rip;
8511 fpu->last_dp = fxsave->rdp;
8512 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
8513
1393123e 8514 vcpu_put(vcpu);
d0752060
HB		 8515 return 0;
8516}
8517
8518int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8519{
6a96bc7f
CD		 8520 struct fxregs_state *fxsave;
8521
8522 vcpu_load(vcpu);
8523
8524 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060 8525
d0752060
HB		 8526 memcpy(fxsave->st_space, fpu->fpr, 128);
8527 fxsave->cwd = fpu->fcw;
8528 fxsave->swd = fpu->fsw;
8529 fxsave->twd = fpu->ftwx;
8530 fxsave->fop = fpu->last_opcode;
8531 fxsave->rip = fpu->last_ip;
8532 fxsave->rdp = fpu->last_dp;
8533 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
8534
6a96bc7f 8535 vcpu_put(vcpu);
d0752060
HB		 8536 return 0;
8537}
8538
01643c51
KH		 8539static void store_regs(struct kvm_vcpu *vcpu)
8540{
8541 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8542
8543 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8544 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8545
8546 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8547 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8548
8549 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8550 kvm_vcpu_ioctl_x86_get_vcpu_events(
8551 vcpu, &vcpu->run->s.regs.events);
8552}
8553
8554static int sync_regs(struct kvm_vcpu *vcpu)
8555{
8556 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8557 return -EINVAL;
8558
8559 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8560 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8561 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8562 }
8563 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8564 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8565 return -EINVAL;
8566 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8567 }
8568 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8569 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8570 vcpu, &vcpu->run->s.regs.events))
8571 return -EINVAL;
8572 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8573 }
8574
8575 return 0;
8576}
8577
0ee6a517 8578static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8579{
bf935b0b 8580 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 8581 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 8582 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 8583 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 8584
2acf923e
DC		 8585 /*
8586 * Ensure guest xcr0 is valid for loading
8587 */
d91cab78 8588 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 8589
ad312c7c 8590 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 8591}
d0752060 8592
e9b11c17
ZX		 8593void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8594{
bd768e14
IY		 8595 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8596
12f9a48f 8597 kvmclock_reset(vcpu);
7f1ea208 8598
e9b11c17 8599 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 8600 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 8601}
8602
8603struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8604 unsigned int id)
8605{
c447e76b
LL		 8606 struct kvm_vcpu *vcpu;
8607
b0c39dc6 8608 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 8609 printk_once(KERN_WARNING
8610 "kvm: SMP vm created on host with unstable TSC; "
8611 "guest TSC will not be reliable\n");
c447e76b
LL		 8612
8613 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8614
c447e76b 8615 return vcpu;
26e5215f 8616}
e9b11c17 8617
26e5215f
AK		 8618int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8619{
19efffa2 8620 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 8621 vcpu_load(vcpu);
d28bc9dd 8622 kvm_vcpu_reset(vcpu, false);
e1732991 8623 kvm_init_mmu(vcpu, false);
e9b11c17 8624 vcpu_put(vcpu);
ec7660cc 8625 return 0;
e9b11c17
ZX		 8626}
8627
31928aa5 8628void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 8629{
8fe8ab46 8630 struct msr_data msr;
332967a3 8631 struct kvm *kvm = vcpu->kvm;
42897d86 8632
d3457c87
RK		 8633 kvm_hv_vcpu_postcreate(vcpu);
8634
ec7660cc 8635 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 8636 return;
ec7660cc 8637 vcpu_load(vcpu);
8fe8ab46
WA		 8638 msr.data = 0x0;
8639 msr.index = MSR_IA32_TSC;
8640 msr.host_initiated = true;
8641 kvm_write_tsc(vcpu, &msr);
42897d86 8642 vcpu_put(vcpu);
ec7660cc 8643 mutex_unlock(&vcpu->mutex);
42897d86 8644
630994b3
MT		 8645 if (!kvmclock_periodic_sync)
8646 return;
8647
332967a3
AJ		 8648 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8649 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8650}
8651
d40ccc62 8652void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8653{
344d9588
GN		 8654 vcpu->arch.apf.msr_val = 0;
8655
ec7660cc 8656 vcpu_load(vcpu);
e9b11c17
ZX		 8657 kvm_mmu_unload(vcpu);
8658 vcpu_put(vcpu);
8659
8660 kvm_x86_ops->vcpu_free(vcpu);
8661}
8662
d28bc9dd 8663void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8664{
b7e31be3
RK		 8665 kvm_lapic_reset(vcpu, init_event);
8666
e69fab5d
PB		 8667 vcpu->arch.hflags = 0;
8668
c43203ca 8669 vcpu->arch.smi_pending = 0;
52797bf9 8670 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8671 atomic_set(&vcpu->arch.nmi_queued, 0);
8672 vcpu->arch.nmi_pending = 0;
448fa4a9 8673 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8674 kvm_clear_interrupt_queue(vcpu);
8675 kvm_clear_exception_queue(vcpu);
664f8e26 8676 vcpu->arch.exception.pending = false;
448fa4a9 8677
42dbaa5a 8678 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8679 kvm_update_dr0123(vcpu);
6f43ed01 8680 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8681 kvm_update_dr6(vcpu);
42dbaa5a 8682 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8683 kvm_update_dr7(vcpu);
42dbaa5a 8684
1119022c
NA		 8685 vcpu->arch.cr2 = 0;
8686
3842d135 8687 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8688 vcpu->arch.apf.msr_val = 0;
c9aaa895 8689 vcpu->arch.st.msr_val = 0;
3842d135 8690
12f9a48f
GC		 8691 kvmclock_reset(vcpu);
8692
af585b92
GN		 8693 kvm_clear_async_pf_completion_queue(vcpu);
8694 kvm_async_pf_hash_reset(vcpu);
8695 vcpu->arch.apf.halted = false;
3842d135 8696
a554d207
WL		 8697 if (kvm_mpx_supported()) {
8698 void *mpx_state_buffer;
8699
8700 /*
8701 * To avoid have the INIT path from kvm_apic_has_events() that be
8702 * called with loaded FPU and does not let userspace fix the state.
8703 */
f775b13e
RR		 8704 if (init_event)
8705 kvm_put_guest_fpu(vcpu);
a554d207
WL		 8706 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8707 XFEATURE_MASK_BNDREGS);
8708 if (mpx_state_buffer)
8709 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8710 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8711 XFEATURE_MASK_BNDCSR);
8712 if (mpx_state_buffer)
8713 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 8714 if (init_event)
8715 kvm_load_guest_fpu(vcpu);
a554d207
WL		 8716 }
8717
64d60670 8718 if (!init_event) {
d28bc9dd 8719 kvm_pmu_reset(vcpu);
64d60670 8720 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 8721
8722 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8723 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 8724
8725 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 8726 }
f5132b01 8727
66f7b72e
JS		 8728 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8729 vcpu->arch.regs_avail = ~0;
8730 vcpu->arch.regs_dirty = ~0;
8731
a554d207
WL		 8732 vcpu->arch.ia32_xss = 0;
8733
d28bc9dd 8734 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 8735}
8736
2b4a273b 8737void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 8738{
8739 struct kvm_segment cs;
8740
8741 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8742 cs.selector = vector << 8;
8743 cs.base = vector << 12;
8744 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8745 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 8746}
8747
13a34e06 8748int kvm_arch_hardware_enable(void)
e9b11c17 8749{
ca84d1a2
ZA		 8750 struct kvm *kvm;
8751 struct kvm_vcpu *vcpu;
8752 int i;
0dd6a6ed
ZA		 8753 int ret;
8754 u64 local_tsc;
8755 u64 max_tsc = 0;
8756 bool stable, backwards_tsc = false;
18863bdd
AK		 8757
8758 kvm_shared_msr_cpu_online();
13a34e06 8759 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 8760 if (ret != 0)
8761 return ret;
8762
4ea1636b 8763 local_tsc = rdtsc();
b0c39dc6 8764 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 8765 list_for_each_entry(kvm, &vm_list, vm_list) {
8766 kvm_for_each_vcpu(i, vcpu, kvm) {
8767 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 8768 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8769 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8770 backwards_tsc = true;
8771 if (vcpu->arch.last_host_tsc > max_tsc)
8772 max_tsc = vcpu->arch.last_host_tsc;
8773 }
8774 }
8775 }
8776
8777 /*
8778 * Sometimes, even reliable TSCs go backwards. This happens on
8779 * platforms that reset TSC during suspend or hibernate actions, but
8780 * maintain synchronization. We must compensate. Fortunately, we can
8781 * detect that condition here, which happens early in CPU bringup,
8782 * before any KVM threads can be running. Unfortunately, we can't
8783 * bring the TSCs fully up to date with real time, as we aren't yet far
8784 * enough into CPU bringup that we know how much real time has actually
108b249c 8785 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 8786 * variables that haven't been updated yet.
8787 *
8788 * So we simply find the maximum observed TSC above, then record the
8789 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8790 * the adjustment will be applied. Note that we accumulate
8791 * adjustments, in case multiple suspend cycles happen before some VCPU
8792 * gets a chance to run again. In the event that no KVM threads get a
8793 * chance to run, we will miss the entire elapsed period, as we'll have
8794 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8795 * loose cycle time. This isn't too big a deal, since the loss will be
8796 * uniform across all VCPUs (not to mention the scenario is extremely
8797 * unlikely). It is possible that a second hibernate recovery happens
8798 * much faster than a first, causing the observed TSC here to be
8799 * smaller; this would require additional padding adjustment, which is
8800 * why we set last_host_tsc to the local tsc observed here.
8801 *
8802 * N.B. - this code below runs only on platforms with reliable TSC,
8803 * as that is the only way backwards_tsc is set above. Also note
8804 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8805 * have the same delta_cyc adjustment applied if backwards_tsc
8806 * is detected. Note further, this adjustment is only done once,
8807 * as we reset last_host_tsc on all VCPUs to stop this from being
8808 * called multiple times (one for each physical CPU bringup).
8809 *
4a969980 8810 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 8811 * will be compensated by the logic in vcpu_load, which sets the TSC to
8812 * catchup mode. This will catchup all VCPUs to real time, but cannot
8813 * guarantee that they stay in perfect synchronization.
8814 */
8815 if (backwards_tsc) {
8816 u64 delta_cyc = max_tsc - local_tsc;
8817 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8818 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 8819 kvm_for_each_vcpu(i, vcpu, kvm) {
8820 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8821 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8822 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8823 }
8824
8825 /*
8826 * We have to disable TSC offset matching.. if you were
8827 * booting a VM while issuing an S4 host suspend....
8828 * you may have some problem. Solving this issue is
8829 * left as an exercise to the reader.
8830 */
8831 kvm->arch.last_tsc_nsec = 0;
8832 kvm->arch.last_tsc_write = 0;
8833 }
8834
8835 }
8836 return 0;
e9b11c17
ZX		 8837}
8838
13a34e06 8839void kvm_arch_hardware_disable(void)
e9b11c17 8840{
13a34e06
RK		 8841 kvm_x86_ops->hardware_disable();
8842 drop_user_return_notifiers();
e9b11c17
ZX		 8843}
8844
8845int kvm_arch_hardware_setup(void)
8846{
9e9c3fe4
NA		 8847 int r;
8848
8849 r = kvm_x86_ops->hardware_setup();
8850 if (r != 0)
8851 return r;
8852
35181e86
HZ		 8853 if (kvm_has_tsc_control) {
8854 /*
8855 * Make sure the user can only configure tsc_khz values that
8856 * fit into a signed integer.
273ba457 8857 * A min value is not calculated because it will always
35181e86
HZ		 8858 * be 1 on all machines.
8859 */
8860 u64 max = min(0x7fffffffULL,
8861 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8862 kvm_max_guest_tsc_khz = max;
8863
ad721883 8864 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8865 }
ad721883 8866
9e9c3fe4
NA		 8867 kvm_init_msr_list();
8868 return 0;
e9b11c17
ZX		 8869}
8870
8871void kvm_arch_hardware_unsetup(void)
8872{
8873 kvm_x86_ops->hardware_unsetup();
8874}
8875
8876void kvm_arch_check_processor_compat(void *rtn)
8877{
8878 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8879}
8880
8881bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8882{
8883 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8884}
8885EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8886
8887bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8888{
8889 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8890}
8891
54e9818f 8892struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8893EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8894
e9b11c17
ZX		 8895int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8896{
8897 struct page *page;
e9b11c17
ZX		 8898 int r;
8899
b2a05fef 8900 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8901 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8902 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8903 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8904 else
a4535290 8905 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8906
8907 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8908 if (!page) {
8909 r = -ENOMEM;
8910 goto fail;
8911 }
ad312c7c 8912 vcpu->arch.pio_data = page_address(page);
e9b11c17 8913
cc578287 8914 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8915
e9b11c17
ZX		 8916 r = kvm_mmu_create(vcpu);
8917 if (r < 0)
8918 goto fail_free_pio_data;
8919
26de7988 8920 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8921 r = kvm_create_lapic(vcpu);
8922 if (r < 0)
8923 goto fail_mmu_destroy;
54e9818f
GN		 8924 } else
8925 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8926
890ca9ae
HY		 8927 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8928 GFP_KERNEL);
8929 if (!vcpu->arch.mce_banks) {
8930 r = -ENOMEM;
443c39bc 8931 goto fail_free_lapic;
890ca9ae
HY		 8932 }
8933 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8934
f1797359
WY		 8935 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8936 r = -ENOMEM;
f5f48ee1 8937 goto fail_free_mce_banks;
f1797359 8938 }
f5f48ee1 8939
0ee6a517 8940 fx_init(vcpu);
66f7b72e 8941
4344ee98 8942 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8943
5a4f55cd
EK		 8944 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8945
74545705
RK		 8946 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8947
af585b92 8948 kvm_async_pf_hash_reset(vcpu);
f5132b01 8949 kvm_pmu_init(vcpu);
af585b92 8950
1c1a9ce9 8951 vcpu->arch.pending_external_vector = -1;
de63ad4c 8952 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8953
5c919412
AS		 8954 kvm_hv_vcpu_init(vcpu);
8955
e9b11c17 8956 return 0;
0ee6a517 8957
f5f48ee1
SY		 8958fail_free_mce_banks:
8959 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8960fail_free_lapic:
8961 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8962fail_mmu_destroy:
8963 kvm_mmu_destroy(vcpu);
8964fail_free_pio_data:
ad312c7c 8965 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8966fail:
8967 return r;
8968}
8969
8970void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8971{
f656ce01
MT		 8972 int idx;
8973
1f4b34f8 8974 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8975 kvm_pmu_destroy(vcpu);
36cb93fd 8976 kfree(vcpu->arch.mce_banks);
e9b11c17 8977 kvm_free_lapic(vcpu);
f656ce01 8978 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8979 kvm_mmu_destroy(vcpu);
f656ce01 8980 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8981 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8982 if (!lapic_in_kernel(vcpu))
54e9818f 8983 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8984}
d19a9cd2 8985
e790d9ef
RK		 8986void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8987{
c595ceee 8988 vcpu->arch.l1tf_flush_l1d = true;
ae97a3b8 8989 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8990}
8991
e08b9637 8992int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8993{
e08b9637
CO		 8994 if (type)
8995 return -EINVAL;
8996
6ef768fa 8997 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8998 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8999 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 9000 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 9001 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 9002
5550af4d
SY		 9003 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9004 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 9005 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9006 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9007 &kvm->arch.irq_sources_bitmap);
5550af4d 9008
038f8c11 9009 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 9010 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 9011 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9012
108b249c 9013 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 9014 pvclock_update_vm_gtod_copy(kvm);
53f658b3 9015
6fbbde9a
DS		 9016 kvm->arch.guest_can_read_msr_platform_info = true;
9017
7e44e449 9018 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 9019 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 9020
cbc0236a 9021 kvm_hv_init_vm(kvm);
0eb05bf2 9022 kvm_page_track_init(kvm);
13d268ca 9023 kvm_mmu_init_vm(kvm);
0eb05bf2 9024
03543133
SS		 9025 if (kvm_x86_ops->vm_init)
9026 return kvm_x86_ops->vm_init(kvm);
9027
d89f5eff 9028 return 0;
d19a9cd2
ZX		 9029}
9030
9031static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9032{
ec7660cc 9033 vcpu_load(vcpu);
d19a9cd2
ZX		 9034 kvm_mmu_unload(vcpu);
9035 vcpu_put(vcpu);
9036}
9037
9038static void kvm_free_vcpus(struct kvm *kvm)
9039{
9040 unsigned int i;
988a2cae 9041 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 9042
9043 /*
9044 * Unpin any mmu pages first.
9045 */
af585b92
GN		 9046 kvm_for_each_vcpu(i, vcpu, kvm) {
9047 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 9048 kvm_unload_vcpu_mmu(vcpu);
af585b92 9049 }
988a2cae
GN		 9050 kvm_for_each_vcpu(i, vcpu, kvm)
9051 kvm_arch_vcpu_free(vcpu);
9052
9053 mutex_lock(&kvm->lock);
9054 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9055 kvm->vcpus[i] = NULL;
d19a9cd2 9056
988a2cae
GN		 9057 atomic_set(&kvm->online_vcpus, 0);
9058 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 9059}
9060
ad8ba2cd
SY		 9061void kvm_arch_sync_events(struct kvm *kvm)
9062{
332967a3 9063 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 9064 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 9065 kvm_free_pit(kvm);
ad8ba2cd
SY		 9066}
9067
1d8007bd 9068int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9069{
9070 int i, r;
25188b99 9071 unsigned long hva;
f0d648bd
PB		 9072 struct kvm_memslots *slots = kvm_memslots(kvm);
9073 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 9074
9075 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 9076 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9077 return -EINVAL;
9da0e4d5 9078
f0d648bd
PB		 9079 slot = id_to_memslot(slots, id);
9080 if (size) {
b21629da 9081 if (slot->npages)
f0d648bd
PB		 9082 return -EEXIST;
9083
9084 /*
9085 * MAP_SHARED to prevent internal slot pages from being moved
9086 * by fork()/COW.
9087 */
9088 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9089 MAP_SHARED | MAP_ANONYMOUS, 0);
9090 if (IS_ERR((void *)hva))
9091 return PTR_ERR((void *)hva);
9092 } else {
9093 if (!slot->npages)
9094 return 0;
9095
9096 hva = 0;
9097 }
9098
9099 old = *slot;
9da0e4d5 9100 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 9101 struct kvm_userspace_memory_region m;
9da0e4d5 9102
1d8007bd
PB		 9103 m.slot = id | (i << 16);
9104 m.flags = 0;
9105 m.guest_phys_addr = gpa;
f0d648bd 9106 m.userspace_addr = hva;
1d8007bd 9107 m.memory_size = size;
9da0e4d5
PB		 9108 r = __kvm_set_memory_region(kvm, &m);
9109 if (r < 0)
9110 return r;
9111 }
9112
103c763c
EB		 9113 if (!size)
9114 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 9115
9da0e4d5
PB		 9116 return 0;
9117}
9118EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9119
1d8007bd 9120int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9121{
9122 int r;
9123
9124 mutex_lock(&kvm->slots_lock);
1d8007bd 9125 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 9126 mutex_unlock(&kvm->slots_lock);
9127
9128 return r;
9129}
9130EXPORT_SYMBOL_GPL(x86_set_memory_region);
9131
d19a9cd2
ZX		 9132void kvm_arch_destroy_vm(struct kvm *kvm)
9133{
27469d29
AH		 9134 if (current->mm == kvm->mm) {
9135 /*
9136 * Free memory regions allocated on behalf of userspace,
9137 * unless the the memory map has changed due to process exit
9138 * or fd copying.
9139 */
1d8007bd
PB		 9140 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9141 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9142 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 9143 }
03543133
SS		 9144 if (kvm_x86_ops->vm_destroy)
9145 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 9146 kvm_pic_destroy(kvm);
9147 kvm_ioapic_destroy(kvm);
d19a9cd2 9148 kvm_free_vcpus(kvm);
af1bae54 9149 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 9150 kvm_mmu_uninit_vm(kvm);
2beb6dad 9151 kvm_page_track_cleanup(kvm);
cbc0236a 9152 kvm_hv_destroy_vm(kvm);
d19a9cd2 9153}
0de10343 9154
5587027c 9155void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 9156 struct kvm_memory_slot *dont)
9157{
9158 int i;
9159
d89cc617
TY		 9160 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9161 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 9162 kvfree(free->arch.rmap[i]);
d89cc617 9163 free->arch.rmap[i] = NULL;
77d11309 9164 }
d89cc617
TY		 9165 if (i == 0)
9166 continue;
9167
9168 if (!dont || free->arch.lpage_info[i - 1] !=
9169 dont->arch.lpage_info[i - 1]) {
548ef284 9170 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 9171 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9172 }
9173 }
21ebbeda
XG		 9174
9175 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 9176}
9177
5587027c
AK		 9178int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9179 unsigned long npages)
db3fe4eb
TY		 9180{
9181 int i;
9182
d89cc617 9183 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 9184 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 9185 unsigned long ugfn;
9186 int lpages;
d89cc617 9187 int level = i + 1;
db3fe4eb
TY		 9188
9189 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9190 slot->base_gfn, level) + 1;
9191
d89cc617 9192 slot->arch.rmap[i] =
778e1cdd
KC		 9193 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
9194 GFP_KERNEL);
d89cc617 9195 if (!slot->arch.rmap[i])
77d11309 9196 goto out_free;
d89cc617
TY		 9197 if (i == 0)
9198 continue;
77d11309 9199
778e1cdd 9200 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL);
92f94f1e 9201 if (!linfo)
db3fe4eb
TY		 9202 goto out_free;
9203
92f94f1e
XG		 9204 slot->arch.lpage_info[i - 1] = linfo;
9205
db3fe4eb 9206 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9207 linfo[0].disallow_lpage = 1;
db3fe4eb 9208 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9209 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 9210 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9211 /*
9212 * If the gfn and userspace address are not aligned wrt each
9213 * other, or if explicitly asked to, disable large page
9214 * support for this slot
9215 */
9216 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9217 !kvm_largepages_enabled()) {
9218 unsigned long j;
9219
9220 for (j = 0; j < lpages; ++j)
92f94f1e 9221 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 9222 }
9223 }
9224
21ebbeda
XG		 9225 if (kvm_page_track_create_memslot(slot, npages))
9226 goto out_free;
9227
db3fe4eb
TY		 9228 return 0;
9229
9230out_free:
d89cc617 9231 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 9232 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 9233 slot->arch.rmap[i] = NULL;
9234 if (i == 0)
9235 continue;
9236
548ef284 9237 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 9238 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9239 }
9240 return -ENOMEM;
9241}
9242
15f46015 9243void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 9244{
e6dff7d1
TY		 9245 /*
9246 * memslots->generation has been incremented.
9247 * mmio generation may have reached its maximum value.
9248 */
54bf36aa 9249 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 9250}
9251
f7784b8e
MT		 9252int kvm_arch_prepare_memory_region(struct kvm *kvm,
9253 struct kvm_memory_slot *memslot,
09170a49 9254 const struct kvm_userspace_memory_region *mem,
7b6195a9 9255 enum kvm_mr_change change)
0de10343 9256{
f7784b8e
MT		 9257 return 0;
9258}
9259
88178fd4
KH		 9260static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9261 struct kvm_memory_slot *new)
9262{
9263 /* Still write protect RO slot */
9264 if (new->flags & KVM_MEM_READONLY) {
9265 kvm_mmu_slot_remove_write_access(kvm, new);
9266 return;
9267 }
9268
9269 /*
9270 * Call kvm_x86_ops dirty logging hooks when they are valid.
9271 *
9272 * kvm_x86_ops->slot_disable_log_dirty is called when:
9273 *
9274 * - KVM_MR_CREATE with dirty logging is disabled
9275 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9276 *
9277 * The reason is, in case of PML, we need to set D-bit for any slots
9278 * with dirty logging disabled in order to eliminate unnecessary GPA
9279 * logging in PML buffer (and potential PML buffer full VMEXT). This
9280 * guarantees leaving PML enabled during guest's lifetime won't have
9281 * any additonal overhead from PML when guest is running with dirty
9282 * logging disabled for memory slots.
9283 *
9284 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9285 * to dirty logging mode.
9286 *
9287 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9288 *
9289 * In case of write protect:
9290 *
9291 * Write protect all pages for dirty logging.
9292 *
9293 * All the sptes including the large sptes which point to this
9294 * slot are set to readonly. We can not create any new large
9295 * spte on this slot until the end of the logging.
9296 *
9297 * See the comments in fast_page_fault().
9298 */
9299 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9300 if (kvm_x86_ops->slot_enable_log_dirty)
9301 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9302 else
9303 kvm_mmu_slot_remove_write_access(kvm, new);
9304 } else {
9305 if (kvm_x86_ops->slot_disable_log_dirty)
9306 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9307 }
9308}
9309
f7784b8e 9310void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 9311 const struct kvm_userspace_memory_region *mem,
8482644a 9312 const struct kvm_memory_slot *old,
f36f3f28 9313 const struct kvm_memory_slot *new,
8482644a 9314 enum kvm_mr_change change)
f7784b8e 9315{
8482644a 9316 int nr_mmu_pages = 0;
f7784b8e 9317
48c0e4e9
XG		 9318 if (!kvm->arch.n_requested_mmu_pages)
9319 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
9320
48c0e4e9 9321 if (nr_mmu_pages)
0de10343 9322 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 9323
3ea3b7fa
WL		 9324 /*
9325 * Dirty logging tracks sptes in 4k granularity, meaning that large
9326 * sptes have to be split. If live migration is successful, the guest
9327 * in the source machine will be destroyed and large sptes will be
9328 * created in the destination. However, if the guest continues to run
9329 * in the source machine (for example if live migration fails), small
9330 * sptes will remain around and cause bad performance.
9331 *
9332 * Scan sptes if dirty logging has been stopped, dropping those
9333 * which can be collapsed into a single large-page spte. Later
9334 * page faults will create the large-page sptes.
9335 */
9336 if ((change != KVM_MR_DELETE) &&
9337 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9338 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9339 kvm_mmu_zap_collapsible_sptes(kvm, new);
9340
c972f3b1 9341 /*
88178fd4 9342 * Set up write protection and/or dirty logging for the new slot.
c126d94f 9343 *
88178fd4
KH		 9344 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9345 * been zapped so no dirty logging staff is needed for old slot. For
9346 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9347 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 9348 *
9349 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 9350 */
88178fd4 9351 if (change != KVM_MR_DELETE)
f36f3f28 9352 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 9353}
1d737c8a 9354
2df72e9b 9355void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 9356{
6ca18b69 9357 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 9358}
9359
2df72e9b
MT		 9360void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9361 struct kvm_memory_slot *slot)
9362{
ae7cd873 9363 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 9364}
9365
e6c67d8c
LA		 9366static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9367{
9368 return (is_guest_mode(vcpu) &&
9369 kvm_x86_ops->guest_apic_has_interrupt &&
9370 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9371}
9372
5d9bc648
PB		 9373static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9374{
9375 if (!list_empty_careful(&vcpu->async_pf.done))
9376 return true;
9377
9378 if (kvm_apic_has_events(vcpu))
9379 return true;
9380
9381 if (vcpu->arch.pv.pv_unhalted)
9382 return true;
9383
a5f01f8e
WL		 9384 if (vcpu->arch.exception.pending)
9385 return true;
9386
47a66eed
Z		 9387 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9388 (vcpu->arch.nmi_pending &&
9389 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 9390 return true;
9391
47a66eed
Z		 9392 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9393 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 9394 return true;
9395
5d9bc648 9396 if (kvm_arch_interrupt_allowed(vcpu) &&
e6c67d8c
LA		 9397 (kvm_cpu_has_interrupt(vcpu) ||
9398 kvm_guest_apic_has_interrupt(vcpu)))
5d9bc648
PB		 9399 return true;
9400
1f4b34f8
AS		 9401 if (kvm_hv_has_stimer_pending(vcpu))
9402 return true;
9403
5d9bc648
PB		 9404 return false;
9405}
9406
1d737c8a
ZX		 9407int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9408{
5d9bc648 9409 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 9410}
5736199a 9411
199b5763
LM		 9412bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9413{
de63ad4c 9414 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 9415}
9416
b6d33834 9417int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 9418{
b6d33834 9419 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 9420}
78646121
GN		 9421
9422int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9423{
9424 return kvm_x86_ops->interrupt_allowed(vcpu);
9425}
229456fc 9426
82b32774 9427unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 9428{
82b32774
NA		 9429 if (is_64_bit_mode(vcpu))
9430 return kvm_rip_read(vcpu);
9431 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9432 kvm_rip_read(vcpu));
9433}
9434EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 9435
82b32774
NA		 9436bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9437{
9438 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 9439}
9440EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9441
94fe45da
JK		 9442unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9443{
9444 unsigned long rflags;
9445
9446 rflags = kvm_x86_ops->get_rflags(vcpu);
9447 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 9448 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 9449 return rflags;
9450}
9451EXPORT_SYMBOL_GPL(kvm_get_rflags);
9452
6addfc42 9453static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 9454{
9455 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 9456 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 9457 rflags |= X86_EFLAGS_TF;
94fe45da 9458 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 9459}
9460
9461void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9462{
9463 __kvm_set_rflags(vcpu, rflags);
3842d135 9464 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 9465}
9466EXPORT_SYMBOL_GPL(kvm_set_rflags);
9467
56028d08
GN		 9468void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9469{
9470 int r;
9471
44dd3ffa 9472 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
f2e10669 9473 work->wakeup_all)
56028d08
GN		 9474 return;
9475
9476 r = kvm_mmu_reload(vcpu);
9477 if (unlikely(r))
9478 return;
9479
44dd3ffa
VK		 9480 if (!vcpu->arch.mmu->direct_map &&
9481 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
fb67e14f
XG		 9482 return;
9483
44dd3ffa 9484 vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true);
56028d08
GN		 9485}
9486
af585b92
GN		 9487static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9488{
9489 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9490}
9491
9492static inline u32 kvm_async_pf_next_probe(u32 key)
9493{
9494 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9495}
9496
9497static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9498{
9499 u32 key = kvm_async_pf_hash_fn(gfn);
9500
9501 while (vcpu->arch.apf.gfns[key] != ~0)
9502 key = kvm_async_pf_next_probe(key);
9503
9504 vcpu->arch.apf.gfns[key] = gfn;
9505}
9506
9507static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9508{
9509 int i;
9510 u32 key = kvm_async_pf_hash_fn(gfn);
9511
9512 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9513 (vcpu->arch.apf.gfns[key] != gfn &&
9514 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9515 key = kvm_async_pf_next_probe(key);
9516
9517 return key;
9518}
9519
9520bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9521{
9522 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9523}
9524
9525static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9526{
9527 u32 i, j, k;
9528
9529 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9530 while (true) {
9531 vcpu->arch.apf.gfns[i] = ~0;
9532 do {
9533 j = kvm_async_pf_next_probe(j);
9534 if (vcpu->arch.apf.gfns[j] == ~0)
9535 return;
9536 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9537 /*
9538 * k lies cyclically in ]i,j]
9539 * | i.k.j |
9540 * |....j i.k.| or |.k..j i...|
9541 */
9542 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9543 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9544 i = j;
9545 }
9546}
9547
7c90705b
GN		 9548static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9549{
4e335d9e
PB		 9550
9551 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9552 sizeof(val));
7c90705b
GN		 9553}
9554
9a6e7c39
WL		 9555static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9556{
9557
9558 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9559 sizeof(u32));
9560}
9561
af585b92
GN		 9562void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9563 struct kvm_async_pf *work)
9564{
6389ee94
AK		 9565 struct x86_exception fault;
9566
7c90705b 9567 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 9568 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 9569
9570 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 9571 (vcpu->arch.apf.send_user_only &&
9572 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 9573 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9574 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 9575 fault.vector = PF_VECTOR;
9576 fault.error_code_valid = true;
9577 fault.error_code = 0;
9578 fault.nested_page_fault = false;
9579 fault.address = work->arch.token;
adfe20fb 9580 fault.async_page_fault = true;
6389ee94 9581 kvm_inject_page_fault(vcpu, &fault);
7c90705b 9582 }
af585b92
GN		 9583}
9584
9585void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9586 struct kvm_async_pf *work)
9587{
6389ee94 9588 struct x86_exception fault;
9a6e7c39 9589 u32 val;
6389ee94 9590
f2e10669 9591 if (work->wakeup_all)
7c90705b
GN		 9592 work->arch.token = ~0; /* broadcast wakeup */
9593 else
9594 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 9595 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 9596
9a6e7c39
WL		 9597 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9598 !apf_get_user(vcpu, &val)) {
9599 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9600 vcpu->arch.exception.pending &&
9601 vcpu->arch.exception.nr == PF_VECTOR &&
9602 !apf_put_user(vcpu, 0)) {
9603 vcpu->arch.exception.injected = false;
9604 vcpu->arch.exception.pending = false;
9605 vcpu->arch.exception.nr = 0;
9606 vcpu->arch.exception.has_error_code = false;
9607 vcpu->arch.exception.error_code = 0;
c851436a
JM		 9608 vcpu->arch.exception.has_payload = false;
9609 vcpu->arch.exception.payload = 0;
9a6e7c39
WL		 9610 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9611 fault.vector = PF_VECTOR;
9612 fault.error_code_valid = true;
9613 fault.error_code = 0;
9614 fault.nested_page_fault = false;
9615 fault.address = work->arch.token;
9616 fault.async_page_fault = true;
9617 kvm_inject_page_fault(vcpu, &fault);
9618 }
7c90705b 9619 }
e6d53e3b 9620 vcpu->arch.apf.halted = false;
a4fa1635 9621 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 9622}
9623
9624bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9625{
9626 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9627 return true;
9628 else
9bc1f09f 9629 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 9630}
9631
5544eb9b
PB		 9632void kvm_arch_start_assignment(struct kvm *kvm)
9633{
9634 atomic_inc(&kvm->arch.assigned_device_count);
9635}
9636EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9637
9638void kvm_arch_end_assignment(struct kvm *kvm)
9639{
9640 atomic_dec(&kvm->arch.assigned_device_count);
9641}
9642EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9643
9644bool kvm_arch_has_assigned_device(struct kvm *kvm)
9645{
9646 return atomic_read(&kvm->arch.assigned_device_count);
9647}
9648EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9649
e0f0bbc5
AW		 9650void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9651{
9652 atomic_inc(&kvm->arch.noncoherent_dma_count);
9653}
9654EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9655
9656void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9657{
9658 atomic_dec(&kvm->arch.noncoherent_dma_count);
9659}
9660EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9661
9662bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9663{
9664 return atomic_read(&kvm->arch.noncoherent_dma_count);
9665}
9666EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9667
14717e20
AW		 9668bool kvm_arch_has_irq_bypass(void)
9669{
9670 return kvm_x86_ops->update_pi_irte != NULL;
9671}
9672
87276880
FW		 9673int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9674 struct irq_bypass_producer *prod)
9675{
9676 struct kvm_kernel_irqfd *irqfd =
9677 container_of(cons, struct kvm_kernel_irqfd, consumer);
9678
14717e20 9679 irqfd->producer = prod;
87276880 9680
14717e20
AW		 9681 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9682 prod->irq, irqfd->gsi, 1);
87276880
FW		 9683}
9684
9685void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9686 struct irq_bypass_producer *prod)
9687{
9688 int ret;
9689 struct kvm_kernel_irqfd *irqfd =
9690 container_of(cons, struct kvm_kernel_irqfd, consumer);
9691
87276880
FW		 9692 WARN_ON(irqfd->producer != prod);
9693 irqfd->producer = NULL;
9694
9695 /*
9696 * When producer of consumer is unregistered, we change back to
9697 * remapped mode, so we can re-use the current implementation
bb3541f1 9698 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 9699 * int this case doesn't want to receive the interrupts.
9700 */
9701 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9702 if (ret)
9703 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9704 " fails: %d\n", irqfd->consumer.token, ret);
9705}
9706
9707int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9708 uint32_t guest_irq, bool set)
9709{
9710 if (!kvm_x86_ops->update_pi_irte)
9711 return -EINVAL;
9712
9713 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9714}
9715
52004014
FW		 9716bool kvm_vector_hashing_enabled(void)
9717{
9718 return vector_hashing;
9719}
9720EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9721
229456fc 9722EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 9723EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 9724EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9725EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9726EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9727EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 9728EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 9729EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 9730EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 9731EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 9732EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 9733EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 9734EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 9735EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 9736EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 9737EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 9738EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 9739EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9740EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
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